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/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream crosspoint
*/
module axis_crosspoint #
(
// Number of AXI stream inputs
parameter S_COUNT = 4,
// Number of AXI stream outputs
parameter M_COUNT = 4,
// Width of AXI stream interfaces in bits
parameter DATA_WIDTH = 8,
// Propagate tkeep signal
parameter KEEP_ENABLE = (DATA_WIDTH>8),
// tkeep signal width (words per cycle)
parameter KEEP_WIDTH = (DATA_WIDTH/8),
// Propagate tlast signal
parameter LAST_ENABLE = 1,
// Propagate tid signal
parameter ID_ENABLE = 0,
// tid signal width
parameter ID_WIDTH = 8,
// Propagate tdest signal
parameter DEST_ENABLE = 0,
// tdest signal width
parameter DEST_WIDTH = 8,
// Propagate tuser signal
parameter USER_ENABLE = 1,
// tuser signal width
parameter USER_WIDTH = 1
)
(
input wire clk,
input wire rst,
/*
* AXI Stream inputs
*/
input wire [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata,
input wire [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep,
input wire [S_COUNT-1:0] s_axis_tvalid,
input wire [S_COUNT-1:0] s_axis_tlast,
input wire [S_COUNT*ID_WIDTH-1:0] s_axis_tid,
input wire [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest,
input wire [S_COUNT*USER_WIDTH-1:0] s_axis_tuser,
/*
* AXI Stream outputs
*/
output wire [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata,
output wire [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep,
output wire [M_COUNT-1:0] m_axis_tvalid,
output wire [M_COUNT-1:0] m_axis_tlast,
output wire [M_COUNT*ID_WIDTH-1:0] m_axis_tid,
output wire [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest,
output wire [M_COUNT*USER_WIDTH-1:0] m_axis_tuser,
/*
* Control
*/
input wire [M_COUNT*$clog2(S_COUNT)-1:0] select
);
parameter CL_S_COUNT = $clog2(S_COUNT);
reg [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata_reg = {S_COUNT*DATA_WIDTH{1'b0}};
reg [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep_reg = {S_COUNT*KEEP_WIDTH{1'b0}};
reg [S_COUNT-1:0] s_axis_tvalid_reg = {S_COUNT{1'b0}};
reg [S_COUNT-1:0] s_axis_tlast_reg = {S_COUNT{1'b0}};
reg [S_COUNT*ID_WIDTH-1:0] s_axis_tid_reg = {S_COUNT*ID_WIDTH{1'b0}};
reg [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest_reg = {S_COUNT*DEST_WIDTH{1'b0}};
reg [S_COUNT*USER_WIDTH-1:0] s_axis_tuser_reg = {S_COUNT*USER_WIDTH{1'b0}};
reg [M_COUNT*DATA_WIDTH-1:0] m_axis_tdata_reg = {M_COUNT*DATA_WIDTH{1'b0}};
reg [M_COUNT*KEEP_WIDTH-1:0] m_axis_tkeep_reg = {M_COUNT*KEEP_WIDTH{1'b0}};
reg [M_COUNT-1:0] m_axis_tvalid_reg = {M_COUNT{1'b0}};
reg [M_COUNT-1:0] m_axis_tlast_reg = {M_COUNT{1'b0}};
reg [M_COUNT*ID_WIDTH-1:0] m_axis_tid_reg = {M_COUNT*ID_WIDTH{1'b0}};
reg [M_COUNT*DEST_WIDTH-1:0] m_axis_tdest_reg = {M_COUNT*DEST_WIDTH{1'b0}};
reg [M_COUNT*USER_WIDTH-1:0] m_axis_tuser_reg = {M_COUNT*USER_WIDTH{1'b0}};
reg [M_COUNT*CL_S_COUNT-1:0] select_reg = {M_COUNT*CL_S_COUNT{1'b0}};
assign m_axis_tdata = m_axis_tdata_reg;
assign m_axis_tkeep = KEEP_ENABLE ? m_axis_tkeep_reg : {M_COUNT*KEEP_WIDTH{1'b1}};
assign m_axis_tvalid = m_axis_tvalid_reg;
assign m_axis_tlast = LAST_ENABLE ? m_axis_tlast_reg : {M_COUNT{1'b1}};
assign m_axis_tid = ID_ENABLE ? m_axis_tid_reg : {M_COUNT*ID_WIDTH{1'b0}};
assign m_axis_tdest = DEST_ENABLE ? m_axis_tdest_reg : {M_COUNT*DEST_WIDTH{1'b0}};
assign m_axis_tuser = USER_ENABLE ? m_axis_tuser_reg : {M_COUNT*USER_WIDTH{1'b0}};
integer i;
always @(posedge clk) begin
if (rst) begin
s_axis_tvalid_reg <= {S_COUNT{1'b0}};
m_axis_tvalid_reg <= {S_COUNT{1'b0}};
select_reg <= {M_COUNT*CL_S_COUNT{1'b0}};
end else begin
s_axis_tvalid_reg <= s_axis_tvalid;
for (i = 0; i < M_COUNT; i = i + 1) begin
m_axis_tvalid_reg[i] <= s_axis_tvalid_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]];
end
select_reg <= select;
end
s_axis_tdata_reg <= s_axis_tdata;
s_axis_tkeep_reg <= s_axis_tkeep;
s_axis_tlast_reg <= s_axis_tlast;
s_axis_tid_reg <= s_axis_tid;
s_axis_tdest_reg <= s_axis_tdest;
s_axis_tuser_reg <= s_axis_tuser;
for (i = 0; i < M_COUNT; i = i + 1) begin
m_axis_tdata_reg[i*DATA_WIDTH +: DATA_WIDTH] <= s_axis_tdata_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]*DATA_WIDTH +: DATA_WIDTH];
m_axis_tkeep_reg[i*KEEP_WIDTH +: KEEP_WIDTH] <= s_axis_tkeep_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]*KEEP_WIDTH +: KEEP_WIDTH];
m_axis_tlast_reg[i] <= s_axis_tlast_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]];
m_axis_tid_reg[i*ID_WIDTH +: ID_WIDTH] <= s_axis_tid_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]*ID_WIDTH +: ID_WIDTH];
m_axis_tdest_reg[i*DEST_WIDTH +: DEST_WIDTH] <= s_axis_tdest_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]*DEST_WIDTH +: DEST_WIDTH];
m_axis_tuser_reg[i*USER_WIDTH +: USER_WIDTH] <= s_axis_tuser_reg[select_reg[i*CL_S_COUNT +: CL_S_COUNT]*USER_WIDTH +: USER_WIDTH];
end
end
endmodule
|
`timescale 1ns/1ps
module axi_master_rd #(
parameter ID_WIDTH = 2,
parameter ADDR_WIDTH = 64,
parameter DATA_WIDTH = 512,
parameter AWUSER_WIDTH = 8,
parameter ARUSER_WIDTH = 8,
parameter WUSER_WIDTH = 1,
parameter RUSER_WIDTH = 1,
parameter BUSER_WIDTH = 1
)
(
input clk ,
input rst_n ,
input clear ,
input [031:0] i_snap_context,
//---- AXI bus ----
// AXI read address channel
output [ID_WIDTH - 1:0] m_axi_arid ,
output reg[ADDR_WIDTH - 1:0] m_axi_araddr ,
output reg[007:0] m_axi_arlen ,
output [002:0] m_axi_arsize ,
output [001:0] m_axi_arburst ,
output [ARUSER_WIDTH - 1:0] m_axi_aruser ,
output [003:0] m_axi_arcache ,
output [001:0] m_axi_arlock ,
output [002:0] m_axi_arprot ,
output [003:0] m_axi_arqos ,
output [003:0] m_axi_arregion,
output reg m_axi_arvalid ,
input m_axi_arready ,
// AXI read data channel
output reg m_axi_rready ,
input [ID_WIDTH - 1:0] m_axi_rid ,
input [DATA_WIDTH - 1:0] m_axi_rdata ,
input [001:0] m_axi_rresp ,
input m_axi_rlast ,
input m_axi_rvalid ,
//---- local bus ----
output lcl_obusy ,
input lcl_ostart ,
input [ADDR_WIDTH - 1:0] lcl_oaddr ,
input [007:0] lcl_onum ,
output lcl_ordy ,
input lcl_rden ,
output lcl_dv ,
output [DATA_WIDTH - 1:0] lcl_dout ,
output lcl_odone ,
//---- status report ----
output [005:0] status ,
output [003:0] error
);
//---- declarations ----
wire local_valid_request;
wire fifo_rdbuf_irdy;
wire fifo_rdbuf_flush;
wire fifo_rdbuf_empty;
wire read_data_handshake;
wire read_last_handshake;
reg [001:0] rd_error;
reg fifo_rdbuf_den;
reg [511:0] fifo_rdbuf_din;
reg fifo_rdbuf_iend;
reg [003:0] rdreq_cnt;
reg rdreq_hold;
reg rdreq_full;
wire fifo_rdbuf_overflow,fifo_rdbuf_underflow;
reg rdovfl, rdudfl;
reg obusy;
//---- parameters ----
parameter MAX_RDREQ_NUM = 8;
//---- signals for AXI advanced features ----
assign m_axi_arid = 20'd0;
assign m_axi_arsize = 3'd6; // 2^6=512
assign m_axi_arburst = 2'd1; // INCR mode for memory access
assign m_axi_arcache = 4'd3; // Normal Non-cacheable Bufferable
assign m_axi_aruser = i_snap_context[ARUSER_WIDTH - 1:0];
assign m_axi_arprot = 3'd0;
assign m_axi_arqos = 4'd0;
assign m_axi_arregion = 4'd0; //?
assign m_axi_arlock = 2'b00; // normal access
/***********************************************************************
* reading channel *
***********************************************************************/
//---- AXI reading valid, address and burst length ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
m_axi_arvalid <= 1'b0;
else if(lcl_ostart & ~lcl_obusy)
m_axi_arvalid <= 1'b1;
else if(m_axi_arready)
m_axi_arvalid <= 1'b0;
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
m_axi_arlen <= 8'b0;
m_axi_araddr <= 64'b0;
end
else if(lcl_ostart)
begin
m_axi_arlen <= lcl_onum - 8'd1;
m_axi_araddr <= lcl_oaddr;
end
//---- axi read data transferred into fifo ----
assign read_data_handshake = m_axi_rready & m_axi_rvalid;
assign read_last_handshake = read_data_handshake & m_axi_rlast;
always@(posedge clk or negedge rst_n)
if(~rst_n)
begin
m_axi_rready <= 1'b0;
fifo_rdbuf_den <= 1'b0;
fifo_rdbuf_din <= 512'd0;
fifo_rdbuf_iend <= 1'b0;
end
else
begin
m_axi_rready <= fifo_rdbuf_irdy;
fifo_rdbuf_den <= read_data_handshake;
fifo_rdbuf_din <= m_axi_rdata;
fifo_rdbuf_iend <= read_last_handshake;
end
//---- reading FIFO, regular, AXI master -> local ----
fifo_axi_lcl maxi_rdbuf(
.clk (clk ),
.rst_n(rst_n ),
.clr (clear ),
.ovfl (fifo_rdbuf_overflow ),
.udfl (fifo_rdbuf_underflow),
.iend (fifo_rdbuf_iend ), //synced with,or after the last input data
.irdy (fifo_rdbuf_irdy ), //stop asserting den when irdy is 0, but with margin
.den (fifo_rdbuf_den ),
.din (fifo_rdbuf_din ),
.rdrq (lcl_rden ), //MUST be deasserted when olast is 1
.olast(lcl_odone ), //synced with the last output data
.ordy (lcl_ordy ), //stop asserting rdrq when ordy is 0, but with margin
.dout (lcl_dout ),
.dv (lcl_dv ), //one clk delay against rdrq. (regular FIFO)
.empty(fifo_rdbuf_empty ),
.flush(fifo_rdbuf_flush )
);
//---- count local read request ----
assign local_valid_request = (lcl_ostart & ~lcl_obusy);
//---- count local read request ----
// try to avoid conincidence of spontaneous asserting of valid lcl_ostart and end of the last burst read data
always@(posedge clk or negedge rst_n)
if(~rst_n)
rdreq_cnt <= 4'b0;
else if(local_valid_request & ~read_last_handshake)
rdreq_cnt <= rdreq_cnt + 4'd1;
else if(~local_valid_request & read_last_handshake)
rdreq_cnt <= rdreq_cnt - 4'd1;
//---- hold read request till last request sent ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
rdreq_hold <= 1'b0;
else if(local_valid_request)
rdreq_hold <= 1'b1;
else if(m_axi_arready & m_axi_arvalid)
rdreq_hold <= 1'b0;
//---- indicate read request limit reached ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
rdreq_full <= 1'b0;
else
rdreq_full <= (rdreq_cnt == MAX_RDREQ_NUM-1);
//---- local read request should be silent when this busy signal asserts, otherwise will be ignored ----
// 1). to lcl_ostart: minimum interval between consecutive read request determined by axi slave side response time not met
// 2). to lcl_ostart: maximum read request number reached
always@(posedge clk or negedge rst_n)
if(~rst_n)
obusy <= 1'b0;
else if(local_valid_request)
obusy <= 1'b1;
else
obusy <= rdreq_hold | rdreq_full;
assign lcl_obusy = obusy;
/***********************************************************************
* status gathering and report *
***********************************************************************/
//---- status report ----
assign status = {
fifo_rdbuf_flush, // b[5]
fifo_rdbuf_empty, // b[4]
rdovfl, // b[3]
rdudfl, // b[2]
rd_error // b[1:0]
};
assign error = {
rdovfl,
rdudfl,
rd_error
};
//---- axi write response ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
rd_error <= 2'b0;
else if(read_data_handshake & (m_axi_rresp != 2'b0))
rd_error <= m_axi_rresp;
//---- FIFO error capture ----
always@(posedge clk or negedge rst_n)
if(~rst_n)
{rdovfl,rdudfl} <= 2'b0;
else if(clear)
{rdovfl,rdudfl} <= 2'b0;
else
case({fifo_rdbuf_overflow,fifo_rdbuf_underflow})
2'b01: {rdovfl,rdudfl} <= {rdovfl,1'b1};
2'b10: {rdovfl,rdudfl} <= {1'b1,rdudfl};
default:;
endcase
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module uart #(
//parameter csr_addr = 4'h0,
parameter clk_freq = 100000000,
parameter baud = 115200
) (
//cpu_read_write
//wb_input
input [31:0] dat_i,
input [31:0] adr_i,
input we_i,
input stb_i,
//wb_output
output reg [31:0] dat_o,
output ack_o,
input sys_clk,
input sys_rst,
output rx_irq,
output tx_irq,
input uart_rx,
output uart_tx,
input rx_iack
);
reg [15:0] divisor;
wire [7:0] rx_data;
wire [7:0] tx_data;
wire tx_wr;
wire rx_done, tx_done;
wire tx_busy;
wire full_rx, full_tx, empty_rx, empty_tx;
reg thru = 0;
wire uart_tx_transceiver;
wire [7:0] rx_data_out;
reg fifo_rx_wr = 0;
reg tmpflag = 0;
wire fifo_rx_rd;
reg fifo_rd_once = 0;
wire [7:0] tx_data_out;
wire fifo_tx_rd;
reg tran_tx_wr = 0;
reg fifo_busy;
wire uart_wr;
uart_transceiver transceiver(
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.uart_rx(uart_rx),
.uart_tx(uart_tx_transceiver),
.divisor(divisor),
.rx_data(rx_data),
.rx_done(rx_done),
.tx_data(tx_data_out),
.tx_wr(tran_tx_wr),
.tx_done(tx_done),
.tx_busy(tx_busy),
.rx_busy(rx_busy)
);
// always @(posedge sys_clk) begin
// if(rx_done & ~fifo_rx_wr) fifo_rx_wr = 1;
// else if(~rx_done & fifo_rx_wr & ~tmpflag) begin
// fifo_rx_wr = 1;
// tmpflag = 1;
// end
// else if(tmpflag) begin
// fifo_rx_wr = 0;
// tmpflag = 0;
// end
// end
always @(posedge sys_clk) begin
if(rx_done) fifo_rx_wr = 1;
else fifo_rx_wr = 0;
end
assign fifo_rx_rd = rx_wr & ~fifo_rd_once;
always @(posedge sys_clk) begin
if(rx_wr) fifo_rd_once = 1;
else fifo_rd_once = 0;
end
assign rx_irq = full_rx & ~rx_iack;
uart_fifo fifo_rx (
.clk(sys_clk), // input clk
.rst(sys_rst), // input rst
.din(rx_data), // input [7 : 0] din
.wr_en(fifo_rx_wr), // input wr_en
.rd_en(fifo_rx_rd), // input rd_en
.dout(rx_data_out), // output [7 : 0] dout
.full(full_rx), // output full
.empty(empty_rx), // output empty
.data_count() // output [7 : 0] data_count
);
assign fifo_tx_rd = ~tx_busy & ~empty_tx;
always @(posedge sys_clk) begin
tran_tx_wr = fifo_tx_rd;
end
always @(posedge sys_clk) begin
if(tx_wr) fifo_busy = 1;
else fifo_busy = 0;
end
//assign tx_irq = full_tx;
uart_fifo fifo_tx (
.clk(sys_clk), // input clk
.rst(sys_rst), // input rst
.din(tx_data), // input [7 : 0] din
.wr_en(tx_wr & ~fifo_busy), // input wr_en
.rd_en(tran_tx_wr & tx_done/*fifo_tx_rd*/), // input rd_en
.dout(tx_data_out), // output [7 : 0] dout
.full(full_tx), // output full
.empty(empty_tx), // output empty
.data_count() // output [7 : 0] data_count
);
assign uart_tx = thru ? uart_rx : uart_tx_transceiver;
/* CSR interface */
//wire csr_selected = csr_a[13:10] == csr_addr;
assign tx_data = dat_i[7:0];
//assign tx_wr = csr_selected & csr_we & (csr_a[1:0] == 2'b00);
assign tx_wr = stb_i & ack_o & we_i & (adr_i[1:0] == 2'b00);
assign rx_wr = stb_i & ack_o & ~we_i & (adr_i[1:0] == 2'b00) & ~empty_rx;
parameter default_divisor = clk_freq/baud/16;
assign ack_o = stb_i & (we_i?~full_tx:1) ;//& ((we_i&~full_tx) | (~we_i&~empty_rx));
assign uart_wr = stb_i && ack_o;
always @(posedge sys_clk or posedge sys_rst) begin
if(sys_rst) begin
divisor <= default_divisor;
dat_o <= 32'd0;
end else if(uart_wr) begin
dat_o <= 32'd0;
case(adr_i[1:0])
2'b00: if(rx_wr) begin dat_o <= {23'h0, 1'b1, rx_data_out}; end
2'b01: dat_o <= divisor;
2'b10: dat_o <= thru;
endcase
if(we_i/*csr_we*/) begin
case(adr_i[1:0])
2'b00:; /* handled by transceiver */
2'b01: divisor <= dat_i[15:0];
2'b10: thru <= dat_i[0];
endcase
end
end
end
//always @(posedge sys_clk) begin
// if(sys_rst) begin
// divisor <= default_divisor;
// dat_o <= 32'd0;
// end else begin
// dat_o <= 32'd0;
// if(stb_i && ack_o/*csr_selected*/) begin
// case(adr_i[1:0])
// 2'b00: dat_o <= rx_data;
// 2'b01: dat_o <= divisor;
// 2'b10: dat_o <= thru;
// endcase
// if(we_i/*csr_we*/) begin
// case(adr_i[1:0])
// 2'b00:; /* handled by transceiver */
// 2'b01: divisor <= dat_i[15:0];
// 2'b10: thru <= dat_i[0];
// endcase
// end
// end
// end
//end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DFRTP_2_V
`define SKY130_FD_SC_HDLL__DFRTP_2_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog wrapper for dfrtp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__dfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dfrtp_2 (
Q ,
CLK ,
D ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dfrtp_2 (
Q ,
CLK ,
D ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__dfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DFRTP_2_V
|
// Verilog test fixture created from schematic B:\NICNAC16\dunc16.sch - Wed Sep 17 00:13:28 2014
`timescale 1ns / 1ps
module dunc16_dunc16_sch_tb();
// Inputs
reg CLK;
reg RESET;
// Output
wire I_STA;
wire I_LDA;
wire I_JMP;
wire I_ADD;
wire I_BL;
wire I_RET;
wire I_BAN;
wire EN_MD;
wire EN_MA;
wire EN_AC;
wire EN_PC;
wire EN_IR;
wire DO_BL;
wire DO_JUMP;
wire DO_RET;
wire DO_ADD;
wire DO_LDA;
wire INCR_PC;
wire [15:0] PC_OUT;
wire [15:0] AC_OUT;
wire [15:0] AC_IN;
wire [15:0] MD_OUT;
wire [15:0] PC_IN;
wire [3:0] IR_OUT;
wire [15:0] LINK_OUT;
wire [15:0] MA_OUT;
wire [15:0] MA_IN;
wire [15:0] MD_IN;
wire [15:0] MEMORY_READ;
wire [15:0] MMO;
wire AZ;
wire AN;
reg ININ;
// Bidirs
// Instantiate the UUT
dunc16 UUT (
.I_STA(I_STA),
.I_LDA(I_LDA),
.I_JMP(I_JMP),
.I_BAN(I_BAN),
.I_ADD(I_ADD),
.I_BL(I_BL),
.I_RET(I_RET),
.AN(AN),
.AZ(AZ),
.DO_BL(DO_BL),
.DO_RET(DO_RET),
.DO_JUMP(DO_JUMP),
.DO_ADD(DO_ADD),
.DO_LDA(DO_LDA),
.INCR_PC(INCR_PC),
.T0(T0),
.T1(T1),
.T2(T2),
.T3(T3),
.EN_MD(EN_MD),
.EN_MA(EN_MA),
.EN_AC(EN_AC),
.EN_PC(EN_PC),
.EN_IR(EN_IR),
.MEMORY_READ(MEMORY_READ),
.AC_OUT(AC_OUT),
.AC_IN(AC_IN),
.MD_OUT(MD_OUT),
.IR_OUT(IR_OUT),
.LINK_OUT(LINK_OUT),
.PC_OUT(PC_OUT),
.PC_IN(PC_IN),
.MA_IN (MA_IN),
.MD_IN (MD_IN),
.MMO(MMO),
.MA_OUT(MA_OUT),
.ININ(ININ),
.CLK(CLK),
.RESET(RESET)
);
initial begin
$monitor("%b%b%b%b PC=%h, f%be%b, s%bl%b. %h %h",UUT.T0,UUT.T1,UUT.T2,UUT.T3,UUT.PC.Q,UUT.FETCH, UUT.EXECUTE, I_STA, UUT.I_LDA, UUT.MD.Q, UUT.AC.Q);
end
initial begin
ININ = 0;
CLK = 0;
//start reset
RESET = 1'b1;
repeat(4)
#1
CLK = ~CLK;
RESET = 1'b0;
// end reset
forever
#1
CLK = ~CLK; // generate a clock
end
initial begin
@(negedge RESET); // wait for reset
repeat (960)
@(posedge CLK);
$finish;
end
endmodule
|
/*******************************************************************************
* Module: simul_axi_master_wdata
* Date:2014-03-24
* Author: Andrey Filippov
* Description: Simulation model for AXI write data channel
*
* Copyright (c) 2014 Elphel, Inc..
* simul_axi_master_wdata.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* simul_axi_master_wdata.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
`timescale 1ns/1ps
module simul_axi_master_wdata#(
parameter integer ID_WIDTH=12,
parameter integer DATA_WIDTH=32,
parameter integer WSTB_WIDTH= 4,
parameter integer LATENCY=0, // minimal delay between inout and output ( 0 - next cycle)
parameter integer DEPTH=8, // maximal number of commands in FIFO
parameter DATA_DELAY = 3.5,
parameter VALID_DELAY = 4.0
)(
input clk,
input reset,
input [ID_WIDTH-1:0] wid_in,
input [DATA_WIDTH-1:0] wdata_in,
input [WSTB_WIDTH-1:0] wstrb_in,
input wlast_in,
output [ID_WIDTH-1:0] wid,
output [DATA_WIDTH-1:0] wdata,
output [WSTB_WIDTH-1:0] wstrb,
output wlast,
output wvalid,
input wready,
input set_cmd, // latch all other input data at posedge of clock
output ready // command/data FIFO can accept command
);
wire [ID_WIDTH-1:0] wid_out;
wire [DATA_WIDTH-1:0] wdata_out;
wire [WSTB_WIDTH-1:0] wstrb_out;
wire wlast_out;
wire wvalid_out;
assign #(DATA_DELAY) wid= wid_out;
assign #(DATA_DELAY) wdata= wdata_out;
assign #(DATA_DELAY) wstrb= wstrb_out;
assign #(DATA_DELAY) wlast= wlast_out;
assign #(VALID_DELAY) wvalid= wvalid_out;
simul_axi_fifo
#(
.WIDTH(ID_WIDTH+DATA_WIDTH+WSTB_WIDTH+1), // total number of output bits
.LATENCY(LATENCY), // minimal delay between inout and output ( 0 - next cycle)
.DEPTH(DEPTH) // maximal number of commands in FIFO
) simul_axi_fifo_i (
.clk(clk), // input clk,
.reset(reset), // input reset,
.data_in({wid_in, wdata_in, wstrb_in, wlast_in}), // input [WIDTH-1:0] data_in,
.load(set_cmd), // input load,
.input_ready(ready), // output input_ready,
.data_out({wid_out, wdata_out, wstrb_out, wlast_out}), // output [WIDTH-1:0] data_out,
.valid(wvalid_out), // output valid,
.ready(wready)); // input ready);
endmodule
|
`timescale 1 ns / 1 ps
module fillbox_v1_0 #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Master Bus Interface M00_AXI
parameter C_M00_AXI_TARGET_SLAVE_BASE_ADDR = 32'h10000000,
parameter integer C_M00_AXI_BURST_LEN = 16,
parameter integer C_M00_AXI_ID_WIDTH = 1,
parameter integer C_M00_AXI_ADDR_WIDTH = 32,
parameter integer C_M00_AXI_DATA_WIDTH = 32,
parameter integer C_M00_AXI_AWUSER_WIDTH = 0,
parameter integer C_M00_AXI_ARUSER_WIDTH = 0,
parameter integer C_M00_AXI_WUSER_WIDTH = 0,
parameter integer C_M00_AXI_RUSER_WIDTH = 0,
parameter integer C_M00_AXI_BUSER_WIDTH = 0,
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 5
)
(
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Master Bus Interface M00_AXI
// input wire m00_axi_init_axi_txn,
output wire m00_axi_txn_done,
output wire m00_axi_error,
input wire m00_axi_aclk,
input wire m00_axi_aresetn,
output wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_awid,
output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_awaddr,
output wire [7 : 0] m00_axi_awlen,
output wire [2 : 0] m00_axi_awsize,
output wire [1 : 0] m00_axi_awburst,
output wire m00_axi_awlock,
output wire [3 : 0] m00_axi_awcache,
output wire [2 : 0] m00_axi_awprot,
output wire [3 : 0] m00_axi_awqos,
output wire [C_M00_AXI_AWUSER_WIDTH-1 : 0] m00_axi_awuser,
output wire m00_axi_awvalid,
input wire m00_axi_awready,
output wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_wdata,
output wire [C_M00_AXI_DATA_WIDTH/8-1 : 0] m00_axi_wstrb,
output wire m00_axi_wlast,
output wire [C_M00_AXI_WUSER_WIDTH-1 : 0] m00_axi_wuser,
output wire m00_axi_wvalid,
input wire m00_axi_wready,
input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_bid,
input wire [1 : 0] m00_axi_bresp,
input wire [C_M00_AXI_BUSER_WIDTH-1 : 0] m00_axi_buser,
input wire m00_axi_bvalid,
output wire m00_axi_bready,
output wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_arid,
output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_araddr,
output wire [7 : 0] m00_axi_arlen,
output wire [2 : 0] m00_axi_arsize,
output wire [1 : 0] m00_axi_arburst,
output wire m00_axi_arlock,
output wire [3 : 0] m00_axi_arcache,
output wire [2 : 0] m00_axi_arprot,
output wire [3 : 0] m00_axi_arqos,
output wire [C_M00_AXI_ARUSER_WIDTH-1 : 0] m00_axi_aruser,
output wire m00_axi_arvalid,
input wire m00_axi_arready,
input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_rid,
input wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_rdata,
input wire [1 : 0] m00_axi_rresp,
input wire m00_axi_rlast,
input wire [C_M00_AXI_RUSER_WIDTH-1 : 0] m00_axi_ruser,
input wire m00_axi_rvalid,
output wire m00_axi_rready,
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
// user signals
wire [27:0] vram;
wire [9:0] width;
wire [9:0] height;
wire [15:0] color;
wire start;
wire done;
assign m00_axi_txn_done = done;
// Instantiation of Axi Bus Interface M00_AXI
fillbox_v1_0_M00_AXI # (
.C_M_TARGET_SLAVE_BASE_ADDR(C_M00_AXI_TARGET_SLAVE_BASE_ADDR),
.C_M_AXI_BURST_LEN(C_M00_AXI_BURST_LEN),
.C_M_AXI_ID_WIDTH(C_M00_AXI_ID_WIDTH),
.C_M_AXI_ADDR_WIDTH(C_M00_AXI_ADDR_WIDTH),
.C_M_AXI_DATA_WIDTH(C_M00_AXI_DATA_WIDTH),
.C_M_AXI_AWUSER_WIDTH(C_M00_AXI_AWUSER_WIDTH),
.C_M_AXI_ARUSER_WIDTH(C_M00_AXI_ARUSER_WIDTH),
.C_M_AXI_WUSER_WIDTH(C_M00_AXI_WUSER_WIDTH),
.C_M_AXI_RUSER_WIDTH(C_M00_AXI_RUSER_WIDTH),
.C_M_AXI_BUSER_WIDTH(C_M00_AXI_BUSER_WIDTH)
) fillbox_v1_0_M00_AXI_inst (
// user part start
.vram(vram),
.width(width),
.height(height),
.color(color),
.INIT_AXI_TXN(start),
.TXN_DONE(done),
// user part end
.ERROR(m00_axi_error),
.M_AXI_ACLK(m00_axi_aclk),
.M_AXI_ARESETN(m00_axi_aresetn),
.M_AXI_AWID(m00_axi_awid),
.M_AXI_AWADDR(m00_axi_awaddr),
.M_AXI_AWLEN(m00_axi_awlen),
.M_AXI_AWSIZE(m00_axi_awsize),
.M_AXI_AWBURST(m00_axi_awburst),
.M_AXI_AWLOCK(m00_axi_awlock),
.M_AXI_AWCACHE(m00_axi_awcache),
.M_AXI_AWPROT(m00_axi_awprot),
.M_AXI_AWQOS(m00_axi_awqos),
.M_AXI_AWUSER(m00_axi_awuser),
.M_AXI_AWVALID(m00_axi_awvalid),
.M_AXI_AWREADY(m00_axi_awready),
.M_AXI_WDATA(m00_axi_wdata),
.M_AXI_WSTRB(m00_axi_wstrb),
.M_AXI_WLAST(m00_axi_wlast),
.M_AXI_WUSER(m00_axi_wuser),
.M_AXI_WVALID(m00_axi_wvalid),
.M_AXI_WREADY(m00_axi_wready),
.M_AXI_BID(m00_axi_bid),
.M_AXI_BRESP(m00_axi_bresp),
.M_AXI_BUSER(m00_axi_buser),
.M_AXI_BVALID(m00_axi_bvalid),
.M_AXI_BREADY(m00_axi_bready),
.M_AXI_ARID(m00_axi_arid),
.M_AXI_ARADDR(m00_axi_araddr),
.M_AXI_ARLEN(m00_axi_arlen),
.M_AXI_ARSIZE(m00_axi_arsize),
.M_AXI_ARBURST(m00_axi_arburst),
.M_AXI_ARLOCK(m00_axi_arlock),
.M_AXI_ARCACHE(m00_axi_arcache),
.M_AXI_ARPROT(m00_axi_arprot),
.M_AXI_ARQOS(m00_axi_arqos),
.M_AXI_ARUSER(m00_axi_aruser),
.M_AXI_ARVALID(m00_axi_arvalid),
.M_AXI_ARREADY(m00_axi_arready),
.M_AXI_RID(m00_axi_rid),
.M_AXI_RDATA(m00_axi_rdata),
.M_AXI_RRESP(m00_axi_rresp),
.M_AXI_RLAST(m00_axi_rlast),
.M_AXI_RUSER(m00_axi_ruser),
.M_AXI_RVALID(m00_axi_rvalid),
.M_AXI_RREADY(m00_axi_rready)
);
// Instantiation of Axi Bus Interface S00_AXI
fillbox_v1_0_S00_AXI # (
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
) fillbox_v1_0_S00_AXI_inst (
// user part start
.vram(vram),
.width(width),
.height(height),
.color(color),
.start(start),
.done(done),
// user part end
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
// Add user logic here
// User logic ends
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2018 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2018.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / DSP_PREADD_DATA
// /___/ /\ Filename : DSP_PREADD_DATA.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 07/15/12 - Migrate from E1.
// 12/10/12 - Add dynamic registers
// 01/11/13 - DIN, D_DATA data width change (26/24) sync4 yml
// 04/23/13 - 714772 - remove sensitivity to negedge GSR
// 05/07/13 - 716896 - INMODE_INV_REG mis sized
// 10/22/14 - 808642 - Added #1 to $finish
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module DSP_PREADD_DATA #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter integer ADREG = 1,
parameter AMULTSEL = "A",
parameter BMULTSEL = "B",
parameter integer DREG = 1,
parameter integer INMODEREG = 1,
parameter [0:0] IS_CLK_INVERTED = 1'b0,
parameter [4:0] IS_INMODE_INVERTED = 5'b00000,
parameter [0:0] IS_RSTD_INVERTED = 1'b0,
parameter [0:0] IS_RSTINMODE_INVERTED = 1'b0,
parameter PREADDINSEL = "A",
parameter USE_MULT = "MULTIPLY"
)(
output [26:0] A2A1,
output ADDSUB,
output [26:0] AD_DATA,
output [17:0] B2B1,
output [26:0] D_DATA,
output INMODE_2,
output [26:0] PREADD_AB,
input [26:0] A1_DATA,
input [26:0] A2_DATA,
input [26:0] AD,
input [17:0] B1_DATA,
input [17:0] B2_DATA,
input CEAD,
input CED,
input CEINMODE,
input CLK,
input [26:0] DIN,
input [4:0] INMODE,
input RSTD,
input RSTINMODE
);
// define constants
localparam MODULE_NAME = "DSP_PREADD_DATA";
// Parameter encodings and registers
localparam AMULTSEL_A = 0;
localparam AMULTSEL_AD = 1;
localparam BMULTSEL_AD = 1;
localparam BMULTSEL_B = 0;
localparam PREADDINSEL_A = 0;
localparam PREADDINSEL_B = 1;
localparam USE_MULT_DYNAMIC = 1;
localparam USE_MULT_MULTIPLY = 0;
localparam USE_MULT_NONE = 2;
reg trig_attr;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "DSP_PREADD_DATA_dr.v"
`else
reg [31:0] ADREG_REG = ADREG;
reg [16:1] AMULTSEL_REG = AMULTSEL;
reg [16:1] BMULTSEL_REG = BMULTSEL;
reg [31:0] DREG_REG = DREG;
reg [31:0] INMODEREG_REG = INMODEREG;
reg [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED;
reg [4:0] IS_INMODE_INVERTED_REG = IS_INMODE_INVERTED;
reg [0:0] IS_RSTD_INVERTED_REG = IS_RSTD_INVERTED;
reg [0:0] IS_RSTINMODE_INVERTED_REG = IS_RSTINMODE_INVERTED;
reg [8:1] PREADDINSEL_REG = PREADDINSEL;
reg [64:1] USE_MULT_REG = USE_MULT;
`endif
`ifdef XIL_XECLIB
wire ADREG_BIN;
wire AMULTSEL_BIN;
wire BMULTSEL_BIN;
wire DREG_BIN;
wire INMODEREG_BIN;
wire PREADDINSEL_BIN;
wire [1:0] USE_MULT_BIN;
`else
reg ADREG_BIN;
reg AMULTSEL_BIN;
reg BMULTSEL_BIN;
reg DREG_BIN;
reg INMODEREG_BIN;
reg PREADDINSEL_BIN;
reg [1:0] USE_MULT_BIN;
`endif
`ifdef XIL_XECLIB
reg glblGSR = 1'b0;
`else
tri0 glblGSR = glbl.GSR;
`endif
wire CEAD_in;
wire CED_in;
wire CEINMODE_in;
wire CLK_in;
wire RSTD_in;
wire RSTINMODE_in;
wire [17:0] B1_DATA_in;
wire [17:0] B2_DATA_in;
wire [26:0] A1_DATA_in;
wire [26:0] A2_DATA_in;
wire [26:0] AD_in;
wire [26:0] DIN_in;
wire [4:0] INMODE_in;
`ifdef XIL_TIMING
wire CEAD_delay;
wire CED_delay;
wire CEINMODE_delay;
wire CLK_delay;
wire RSTD_delay;
wire RSTINMODE_delay;
wire [26:0] AD_delay;
wire [26:0] DIN_delay;
wire [4:0] INMODE_delay;
`endif
`ifdef XIL_TIMING
assign AD_in = AD_delay;
assign CEAD_in = (CEAD !== 1'bz) && CEAD_delay; // rv 0
assign CED_in = (CED !== 1'bz) && CED_delay; // rv 0
assign CEINMODE_in = CEINMODE_delay;
assign CLK_in = (CLK !== 1'bz) && (CLK_delay ^ IS_CLK_INVERTED_REG); // rv 0
assign DIN_in[0] = (DIN[0] !== 1'bz) && DIN_delay[0]; // rv 0
assign DIN_in[10] = (DIN[10] !== 1'bz) && DIN_delay[10]; // rv 0
assign DIN_in[11] = (DIN[11] !== 1'bz) && DIN_delay[11]; // rv 0
assign DIN_in[12] = (DIN[12] !== 1'bz) && DIN_delay[12]; // rv 0
assign DIN_in[13] = (DIN[13] !== 1'bz) && DIN_delay[13]; // rv 0
assign DIN_in[14] = (DIN[14] !== 1'bz) && DIN_delay[14]; // rv 0
assign DIN_in[15] = (DIN[15] !== 1'bz) && DIN_delay[15]; // rv 0
assign DIN_in[16] = (DIN[16] !== 1'bz) && DIN_delay[16]; // rv 0
assign DIN_in[17] = (DIN[17] !== 1'bz) && DIN_delay[17]; // rv 0
assign DIN_in[18] = (DIN[18] !== 1'bz) && DIN_delay[18]; // rv 0
assign DIN_in[19] = (DIN[19] !== 1'bz) && DIN_delay[19]; // rv 0
assign DIN_in[1] = (DIN[1] !== 1'bz) && DIN_delay[1]; // rv 0
assign DIN_in[20] = (DIN[20] !== 1'bz) && DIN_delay[20]; // rv 0
assign DIN_in[21] = (DIN[21] !== 1'bz) && DIN_delay[21]; // rv 0
assign DIN_in[22] = (DIN[22] !== 1'bz) && DIN_delay[22]; // rv 0
assign DIN_in[23] = (DIN[23] !== 1'bz) && DIN_delay[23]; // rv 0
assign DIN_in[24] = (DIN[24] !== 1'bz) && DIN_delay[24]; // rv 0
assign DIN_in[25] = (DIN[25] !== 1'bz) && DIN_delay[25]; // rv 0
assign DIN_in[26] = (DIN[26] !== 1'bz) && DIN_delay[26]; // rv 0
assign DIN_in[2] = (DIN[2] !== 1'bz) && DIN_delay[2]; // rv 0
assign DIN_in[3] = (DIN[3] !== 1'bz) && DIN_delay[3]; // rv 0
assign DIN_in[4] = (DIN[4] !== 1'bz) && DIN_delay[4]; // rv 0
assign DIN_in[5] = (DIN[5] !== 1'bz) && DIN_delay[5]; // rv 0
assign DIN_in[6] = (DIN[6] !== 1'bz) && DIN_delay[6]; // rv 0
assign DIN_in[7] = (DIN[7] !== 1'bz) && DIN_delay[7]; // rv 0
assign DIN_in[8] = (DIN[8] !== 1'bz) && DIN_delay[8]; // rv 0
assign DIN_in[9] = (DIN[9] !== 1'bz) && DIN_delay[9]; // rv 0
assign INMODE_in[0] = (INMODE[0] !== 1'bz) && (INMODE_delay[0] ^ IS_INMODE_INVERTED_REG[0]); // rv 0
assign INMODE_in[1] = (INMODE[1] !== 1'bz) && (INMODE_delay[1] ^ IS_INMODE_INVERTED_REG[1]); // rv 0
assign INMODE_in[2] = (INMODE[2] !== 1'bz) && (INMODE_delay[2] ^ IS_INMODE_INVERTED_REG[2]); // rv 0
assign INMODE_in[3] = (INMODE[3] !== 1'bz) && (INMODE_delay[3] ^ IS_INMODE_INVERTED_REG[3]); // rv 0
assign INMODE_in[4] = (INMODE[4] !== 1'bz) && (INMODE_delay[4] ^ IS_INMODE_INVERTED_REG[4]); // rv 0
assign RSTD_in = (RSTD !== 1'bz) && (RSTD_delay ^ IS_RSTD_INVERTED_REG); // rv 0
assign RSTINMODE_in = (RSTINMODE !== 1'bz) && (RSTINMODE_delay ^ IS_RSTINMODE_INVERTED_REG); // rv 0
`else
assign AD_in = AD;
assign CEAD_in = (CEAD !== 1'bz) && CEAD; // rv 0
assign CED_in = (CED !== 1'bz) && CED; // rv 0
assign CEINMODE_in = CEINMODE;
assign CLK_in = (CLK !== 1'bz) && (CLK ^ IS_CLK_INVERTED_REG); // rv 0
assign DIN_in[0] = (DIN[0] !== 1'bz) && DIN[0]; // rv 0
assign DIN_in[10] = (DIN[10] !== 1'bz) && DIN[10]; // rv 0
assign DIN_in[11] = (DIN[11] !== 1'bz) && DIN[11]; // rv 0
assign DIN_in[12] = (DIN[12] !== 1'bz) && DIN[12]; // rv 0
assign DIN_in[13] = (DIN[13] !== 1'bz) && DIN[13]; // rv 0
assign DIN_in[14] = (DIN[14] !== 1'bz) && DIN[14]; // rv 0
assign DIN_in[15] = (DIN[15] !== 1'bz) && DIN[15]; // rv 0
assign DIN_in[16] = (DIN[16] !== 1'bz) && DIN[16]; // rv 0
assign DIN_in[17] = (DIN[17] !== 1'bz) && DIN[17]; // rv 0
assign DIN_in[18] = (DIN[18] !== 1'bz) && DIN[18]; // rv 0
assign DIN_in[19] = (DIN[19] !== 1'bz) && DIN[19]; // rv 0
assign DIN_in[1] = (DIN[1] !== 1'bz) && DIN[1]; // rv 0
assign DIN_in[20] = (DIN[20] !== 1'bz) && DIN[20]; // rv 0
assign DIN_in[21] = (DIN[21] !== 1'bz) && DIN[21]; // rv 0
assign DIN_in[22] = (DIN[22] !== 1'bz) && DIN[22]; // rv 0
assign DIN_in[23] = (DIN[23] !== 1'bz) && DIN[23]; // rv 0
assign DIN_in[24] = (DIN[24] !== 1'bz) && DIN[24]; // rv 0
assign DIN_in[25] = (DIN[25] !== 1'bz) && DIN[25]; // rv 0
assign DIN_in[26] = (DIN[26] !== 1'bz) && DIN[26]; // rv 0
assign DIN_in[2] = (DIN[2] !== 1'bz) && DIN[2]; // rv 0
assign DIN_in[3] = (DIN[3] !== 1'bz) && DIN[3]; // rv 0
assign DIN_in[4] = (DIN[4] !== 1'bz) && DIN[4]; // rv 0
assign DIN_in[5] = (DIN[5] !== 1'bz) && DIN[5]; // rv 0
assign DIN_in[6] = (DIN[6] !== 1'bz) && DIN[6]; // rv 0
assign DIN_in[7] = (DIN[7] !== 1'bz) && DIN[7]; // rv 0
assign DIN_in[8] = (DIN[8] !== 1'bz) && DIN[8]; // rv 0
assign DIN_in[9] = (DIN[9] !== 1'bz) && DIN[9]; // rv 0
assign INMODE_in[0] = (INMODE[0] !== 1'bz) && (INMODE[0] ^ IS_INMODE_INVERTED_REG[0]); // rv 0
assign INMODE_in[1] = (INMODE[1] !== 1'bz) && (INMODE[1] ^ IS_INMODE_INVERTED_REG[1]); // rv 0
assign INMODE_in[2] = (INMODE[2] !== 1'bz) && (INMODE[2] ^ IS_INMODE_INVERTED_REG[2]); // rv 0
assign INMODE_in[3] = (INMODE[3] !== 1'bz) && (INMODE[3] ^ IS_INMODE_INVERTED_REG[3]); // rv 0
assign INMODE_in[4] = (INMODE[4] !== 1'bz) && (INMODE[4] ^ IS_INMODE_INVERTED_REG[4]); // rv 0
assign RSTD_in = (RSTD !== 1'bz) && (RSTD ^ IS_RSTD_INVERTED_REG); // rv 0
assign RSTINMODE_in = (RSTINMODE !== 1'bz) && (RSTINMODE ^ IS_RSTINMODE_INVERTED_REG); // rv 0
`endif
assign A1_DATA_in = A1_DATA;
assign A2_DATA_in = A2_DATA;
assign B1_DATA_in = B1_DATA;
assign B2_DATA_in = B2_DATA;
`ifndef XIL_XECLIB
reg attr_test;
reg attr_err;
initial begin
trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
attr_test = 1'b1;
`else
attr_test = 1'b0;
`endif
attr_err = 1'b0;
#1;
trig_attr = ~trig_attr;
end
`endif
`ifdef XIL_XECLIB
assign ADREG_BIN = ADREG_REG[0];
assign AMULTSEL_BIN =
(AMULTSEL_REG == "A") ? AMULTSEL_A :
(AMULTSEL_REG == "AD") ? AMULTSEL_AD :
AMULTSEL_A;
assign BMULTSEL_BIN =
(BMULTSEL_REG == "B") ? BMULTSEL_B :
(BMULTSEL_REG == "AD") ? BMULTSEL_AD :
BMULTSEL_B;
assign DREG_BIN = DREG_REG[0];
assign INMODEREG_BIN = INMODEREG_REG[0];
assign PREADDINSEL_BIN =
(PREADDINSEL_REG == "A") ? PREADDINSEL_A :
(PREADDINSEL_REG == "B") ? PREADDINSEL_B :
PREADDINSEL_A;
assign USE_MULT_BIN =
(USE_MULT_REG == "MULTIPLY") ? USE_MULT_MULTIPLY :
(USE_MULT_REG == "DYNAMIC") ? USE_MULT_DYNAMIC :
(USE_MULT_REG == "NONE") ? USE_MULT_NONE :
USE_MULT_MULTIPLY;
`else
always @(trig_attr) begin
#1;
ADREG_BIN = ADREG_REG[0];
AMULTSEL_BIN =
(AMULTSEL_REG == "A") ? AMULTSEL_A :
(AMULTSEL_REG == "AD") ? AMULTSEL_AD :
AMULTSEL_A;
BMULTSEL_BIN =
(BMULTSEL_REG == "B") ? BMULTSEL_B :
(BMULTSEL_REG == "AD") ? BMULTSEL_AD :
BMULTSEL_B;
DREG_BIN = DREG_REG[0];
INMODEREG_BIN = INMODEREG_REG[0];
PREADDINSEL_BIN =
(PREADDINSEL_REG == "A") ? PREADDINSEL_A :
(PREADDINSEL_REG == "B") ? PREADDINSEL_B :
PREADDINSEL_A;
USE_MULT_BIN =
(USE_MULT_REG == "MULTIPLY") ? USE_MULT_MULTIPLY :
(USE_MULT_REG == "DYNAMIC") ? USE_MULT_DYNAMIC :
(USE_MULT_REG == "NONE") ? USE_MULT_NONE :
USE_MULT_MULTIPLY;
end
`endif
`ifndef XIL_TIMING
initial begin
$display("Error: [Unisim %s-100] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME);
#1 $finish;
end
`endif
`ifndef XIL_XECLIB
always @(trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((ADREG_REG != 1) &&
(ADREG_REG != 0))) begin
$display("Error: [Unisim %s-101] ADREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, ADREG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((AMULTSEL_REG != "A") &&
(AMULTSEL_REG != "AD"))) begin
$display("Error: [Unisim %s-102] AMULTSEL attribute is set to %s. Legal values for this attribute are A or AD. Instance: %m", MODULE_NAME, AMULTSEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((BMULTSEL_REG != "B") &&
(BMULTSEL_REG != "AD"))) begin
$display("Error: [Unisim %s-103] BMULTSEL attribute is set to %s. Legal values for this attribute are B or AD. Instance: %m", MODULE_NAME, BMULTSEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DREG_REG != 1) &&
(DREG_REG != 0))) begin
$display("Error: [Unisim %s-104] DREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, DREG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((INMODEREG_REG != 1) &&
(INMODEREG_REG != 0))) begin
$display("Error: [Unisim %s-105] INMODEREG attribute is set to %d. Legal values for this attribute are 1 or 0. Instance: %m", MODULE_NAME, INMODEREG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PREADDINSEL_REG != "A") &&
(PREADDINSEL_REG != "B"))) begin
$display("Error: [Unisim %s-110] PREADDINSEL attribute is set to %s. Legal values for this attribute are A or B. Instance: %m", MODULE_NAME, PREADDINSEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USE_MULT_REG != "MULTIPLY") &&
(USE_MULT_REG != "DYNAMIC") &&
(USE_MULT_REG != "NONE"))) begin
$display("Error: [Unisim %s-111] USE_MULT attribute is set to %s. Legal values for this attribute are MULTIPLY, DYNAMIC or NONE. Instance: %m", MODULE_NAME, USE_MULT_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
`ifdef XIL_TIMING
reg notifier;
`endif
// begin behavioral model
localparam D_WIDTH = 27;
wire [26:0] a1a2_i_mux;
wire [17:0] b1b2_i_mux;
wire [4:0] INMODE_mux;
reg [4:0] INMODE_reg;
reg [D_WIDTH-1:0] AD_DATA_reg;
reg [D_WIDTH-1:0] D_DATA_reg;
reg DREG_INT;
reg ADREG_INT;
// initialize regs
`ifndef XIL_XECLIB
initial begin
INMODE_reg = 5'b0;
AD_DATA_reg = {D_WIDTH{1'b0}};
D_DATA_reg = {D_WIDTH{1'b0}};
end
`endif
always @ (*) begin
if (((AMULTSEL_BIN == AMULTSEL_A) &&
(BMULTSEL_BIN == BMULTSEL_B)) ||
(USE_MULT_BIN == USE_MULT_NONE)) begin
DREG_INT = 1'b0;
end else begin
DREG_INT = DREG_BIN;
end
end
always @ (*) begin
if (((AMULTSEL_BIN == AMULTSEL_A) && (BMULTSEL_BIN == BMULTSEL_B)) ||
(USE_MULT_BIN == USE_MULT_NONE)) begin
ADREG_INT = 1'b0;
end else begin
ADREG_INT = ADREG_BIN;
end
end
assign a1a2_i_mux = INMODE_mux[0] ? A1_DATA_in : A2_DATA_in;
assign b1b2_i_mux = INMODE_mux[4] ? B1_DATA_in : B2_DATA_in;
assign A2A1 = ((PREADDINSEL_BIN==PREADDINSEL_A) && INMODE_mux[1]) ? 27'b0 : a1a2_i_mux;
assign B2B1 = ((PREADDINSEL_BIN==PREADDINSEL_B) && INMODE_mux[1]) ? 18'b0 : b1b2_i_mux;
assign ADDSUB = INMODE_mux[3];
assign INMODE_2 = INMODE_mux[2];
assign PREADD_AB = (PREADDINSEL_BIN==PREADDINSEL_B) ? {{9{B2B1[17]}}, B2B1} : A2A1;
//*********************************************************
//********** INMODE signal registering ************
//*********************************************************
// new
always @(posedge CLK_in) begin
if (RSTINMODE_in || (INMODEREG_BIN == 1'b0) || glblGSR) begin
INMODE_reg <= 5'b0;
end else if (CEINMODE_in) begin
INMODE_reg <= INMODE_in;
end
end
assign INMODE_mux = (INMODEREG_BIN == 1'b1) ? INMODE_reg : INMODE_in;
//*********************************************************
//*** Input register D with 1 level deep of register
//*********************************************************
always @(posedge CLK_in) begin
if (RSTD_in || (DREG_INT == 1'b0) || glblGSR) begin
D_DATA_reg <= {D_WIDTH{1'b0}};
end else if (CED_in) begin
D_DATA_reg <= DIN_in;
end
end
assign D_DATA = (DREG_INT == 1'b1) ? D_DATA_reg : DIN_in;
//*********************************************************
//*** Input register AD with 1 level deep of register
//*********************************************************
always @(posedge CLK_in) begin
if (RSTD_in || glblGSR) begin
AD_DATA_reg <= 27'b0;
end else if (CEAD_in) AD_DATA_reg <= AD_in;
end
assign AD_DATA = (ADREG_INT == 1'b1) ? AD_DATA_reg : AD_in;
// end behavioral model
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
wire clk_en_n;
wire clk_en_p;
assign clk_en_n = IS_CLK_INVERTED_REG;
assign clk_en_p = ~IS_CLK_INVERTED_REG;
`endif
specify
(A1_DATA *> A2A1) = (0:0:0, 0:0:0);
(A1_DATA *> PREADD_AB) = (0:0:0, 0:0:0);
(A2_DATA *> A2A1) = (0:0:0, 0:0:0);
(A2_DATA *> PREADD_AB) = (0:0:0, 0:0:0);
(AD *> AD_DATA) = (0:0:0, 0:0:0);
(B1_DATA *> B2B1) = (0:0:0, 0:0:0);
(B1_DATA *> PREADD_AB) = (0:0:0, 0:0:0);
(B2_DATA *> B2B1) = (0:0:0, 0:0:0);
(B2_DATA *> PREADD_AB) = (0:0:0, 0:0:0);
(CLK *> A2A1) = (0:0:0, 0:0:0);
(CLK *> AD_DATA) = (0:0:0, 0:0:0);
(CLK *> B2B1) = (0:0:0, 0:0:0);
(CLK *> D_DATA) = (0:0:0, 0:0:0);
(CLK *> PREADD_AB) = (0:0:0, 0:0:0);
(CLK => ADDSUB) = (0:0:0, 0:0:0);
(CLK => INMODE_2) = (0:0:0, 0:0:0);
(DIN *> D_DATA) = (0:0:0, 0:0:0);
(INMODE *> A2A1) = (0:0:0, 0:0:0);
(INMODE *> ADDSUB) = (0:0:0, 0:0:0);
(INMODE *> B2B1) = (0:0:0, 0:0:0);
(INMODE *> INMODE_2) = (0:0:0, 0:0:0);
(INMODE *> PREADD_AB) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
$setuphold (negedge CLK, negedge AD, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, AD_delay);
$setuphold (negedge CLK, negedge CEAD, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CEAD_delay);
$setuphold (negedge CLK, negedge CED, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CED_delay);
$setuphold (negedge CLK, negedge CEINMODE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CEINMODE_delay);
$setuphold (negedge CLK, negedge DIN, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, DIN_delay);
$setuphold (negedge CLK, negedge INMODE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INMODE_delay);
$setuphold (negedge CLK, negedge RSTD, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RSTD_delay);
$setuphold (negedge CLK, negedge RSTINMODE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RSTINMODE_delay);
$setuphold (negedge CLK, posedge AD, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, AD_delay);
$setuphold (negedge CLK, posedge CEAD, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CEAD_delay);
$setuphold (negedge CLK, posedge CED, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CED_delay);
$setuphold (negedge CLK, posedge CEINMODE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, CEINMODE_delay);
$setuphold (negedge CLK, posedge DIN, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, DIN_delay);
$setuphold (negedge CLK, posedge INMODE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INMODE_delay);
$setuphold (negedge CLK, posedge RSTD, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RSTD_delay);
$setuphold (negedge CLK, posedge RSTINMODE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RSTINMODE_delay);
$setuphold (posedge CLK, negedge AD, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, AD_delay);
$setuphold (posedge CLK, negedge CEAD, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CEAD_delay);
$setuphold (posedge CLK, negedge CED, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CED_delay);
$setuphold (posedge CLK, negedge CEINMODE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CEINMODE_delay);
$setuphold (posedge CLK, negedge DIN, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, DIN_delay);
$setuphold (posedge CLK, negedge INMODE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INMODE_delay);
$setuphold (posedge CLK, negedge RSTD, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RSTD_delay);
$setuphold (posedge CLK, negedge RSTINMODE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RSTINMODE_delay);
$setuphold (posedge CLK, posedge AD, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, AD_delay);
$setuphold (posedge CLK, posedge CEAD, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CEAD_delay);
$setuphold (posedge CLK, posedge CED, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CED_delay);
$setuphold (posedge CLK, posedge CEINMODE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, CEINMODE_delay);
$setuphold (posedge CLK, posedge DIN, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, DIN_delay);
$setuphold (posedge CLK, posedge INMODE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INMODE_delay);
$setuphold (posedge CLK, posedge RSTD, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RSTD_delay);
$setuphold (posedge CLK, posedge RSTINMODE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RSTINMODE_delay);
`endif
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__BUF_BEHAVIORAL_V
`define SKY130_FD_SC_HD__BUF_BEHAVIORAL_V
/**
* buf: Buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__buf (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__BUF_BEHAVIORAL_V |
`include "bsg_mem_3r1w_sync_macros.vh"
module bsg_mem_3r1w_sync #( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
, parameter read_write_same_addr_p = 0
, parameter addr_width_lp = `BSG_SAFE_CLOG2(els_p)
, parameter harden_p = 1
)
( input clk_i
, input reset_i
, input w_v_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
, input r0_v_i
, input [addr_width_lp-1:0] r0_addr_i
, output logic [width_p-1:0] r0_data_o
, input r1_v_i
, input [addr_width_lp-1:0] r1_addr_i
, output logic [width_p-1:0] r1_data_o
, input r2_v_i
, input [addr_width_lp-1:0] r2_addr_i
, output logic [width_p-1:0] r2_data_o
);
wire unused = reset_i;
// TODO: Define more hardened macro configs here
`bsg_mem_3r1w_sync_macro(32,64,1) else
//`bsg_mem_3r1w_sync_macro(32,32,2) else
// no hardened version found
begin: notmacro
bsg_mem_3r1w_sync_synth #(.width_p(width_p), .els_p(els_p), .read_write_same_addr_p(read_write_same_addr_p))
synth
(.*);
end // block: notmacro
//synopsys translate_off
always_ff @(negedge clk_i)
if (w_v_i)
begin
assert (w_addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
assert (~(r0_addr_i == w_addr_i && r0_v_i && !read_write_same_addr_p))
else $error("%m: port 0 Attempt to read and write same address");
assert (~(r1_addr_i == w_addr_i && r1_v_i && !read_write_same_addr_p))
else $error("%m: port 1 Attempt to read and write same address");
assert (~(r2_addr_i == w_addr_i && r2_v_i && !read_write_same_addr_p))
else $error("%m: port 2 Attempt to read and write same address");
end
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d, harden_p=%d (%m)",width_p,els_p,read_write_same_addr_p,harden_p);
end
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_3r1w_sync)
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:27:05 03/13/2015
// Design Name: serializer
// Module Name: C:/Users/omicronns/Workspaces/webpack-ise/sys-rek/lab3/serializer/tb_serializer.v
// Project Name: serializer
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: serializer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_serializer;
wire [7:0] data;
wire clk;
wire send;
wire txd;
serializer_gen_test generator (
.data(data),
.send(send),
.clk(clk)
);
// Instantiate the Unit Under Test (UUT)
serializer #(
.WIDTH(8)
)
uut(
.data(data),
.rst(0),
.clk(clk),
.send(send),
.txd(txd)
);
serializer_check_test writer (
.clk(clk),
.txd(txd)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : Drawing Engine Register Block Level 1
// File : der_reg_1.v
// Author : Jim MacLeod
// Created : 30-Dec-2008
// RCS File : $Source:$
// Status : $Id:$
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module is the First input register stage
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module der_reg_1
(
input de_clk, // drawing engine clock input
input de_rstn, // de reset input
input hb_clk, // host bus clock input
input hb_rstn, // host bus reset input
input [31:0] hb_din, // host bus data
input [8:2] dlp_adr, // host bus address
input hb_wstrb, // host bus write strobes
input [3:0] hb_ben, // host bus byte enables
input hb_csn, // host bus chip select
input cmdack, // command ack from the dispatcher
input en_3d, // Enable 3D Core.
input de_clint_tog, // Clip Int toggle signal.
input de_ddint_tog, // Clip Int toggle signal.
output reg [1:0] intm, // Interrupt Mask register.
output reg [1:0] intp, // Interrupt Mask register.
output [14:0] buf_ctrl_1, // buffer control register output
output reg [31:0] sorg_1, // source origin register output
output reg [31:0] dorg_1, // destination origin register output
output reg [11:0] sptch_1, // source pitch register output
output reg [11:0] dptch_1, // destination pitch register output
output reg [3:0] opc_1, // opcode register output
output reg [3:0] rop_1, // raster opcode register output
output reg [4:0] style_1, // drawing style register output
output reg [3:0] patrn_1, // drawing pattern style register
output reg [2:0] hdf_1, // source fetch disable
output reg [2:0] clp_1, // drawing clip control register output
output reg [31:0] fore_1, // foreground color register output
output reg [31:0] back_1, // background color register output
output reg [3:0] mask_1, // plane mask register output
output reg [23:0] de_key_1, // raster op mask register output
output reg [31:0] lpat_1, // line pattern register output
output reg [15:0] pctrl_1, // line pattern control register output
output reg [31:0] clptl_1, // clipping top left corner register
output reg [31:0] clpbr_1, /* clipping bottom right corner
* output To maintain compatibility,
* the XY ports are either XY or CP
* based on opcode */
output reg [31:0] xy0_1, // parameter register output XY0
output reg [31:0] xy1_1, // parameter register output XY1
output reg [31:0] xy2_1, // parameter register output XY2
output reg [31:0] xy3_1, // parameter register output XY3
output reg [31:0] xy4_1, // parameter register output XY4
output reg [15:0] alpha_1, // Alpha value register
output reg [17:0] acntrl_1, // Alpha control register
output reg cmdrdy, // command ready output to dispatcher
output reg busy_hb, // busy signal to the host
output stpl_1, // packed stipple bit level one
output reg cmd_trig_comb, // Combinational command trigger
// Outputs to CP reg block
output reg [1:0] bc_lvl_1, // Line vertical limit
output reg interrupt,
output reg [6:0] mem_offset_1, // Define the offset in memory for ops
output reg [3:0] sorg_upper_1 // Define the offset in memory for ops
);
parameter
INTM_INTP = 6'b0_0000_0, // Int mask, Int reg, 0x00.
BUSY_FLOW = 6'b0_0000_1, // Int mask, Int reg, 0x08.
NA_XYW = 6'b0_0001_0, // XYW Address/Size, 0x10.
NA_TSORG = 6'b0_0001_1, // Text offset Sorg 0x18.
MEM_BCTRL = 6'b0_0010_0, // Buffer Control, 0x20.
DORG_SORG = 6'b0_0010_1, // Dest and Src Origin. 0x28.
DPTCH_SPTCH = 6'b0_0100_0,
CMDR = 6'b0_0100_1,
ROP_OPC = 6'b0_0101_0,
PATRN_STYLE = 6'b0_0101_1,
SFD_CLP = 6'b0_0110_0,
BACK_FORE = 6'b0_0110_1,
DEKEY_MASK = 6'b0_0111_0,
PCTRL_LPAT = 6'b0_0111_1,
CLPBR_CLPTL = 6'b0_1000_0,
XY1_XY0 = 6'b0_1000_1,
XY3_XY2 = 6'b0_1001_0,
NA_XY4 = 6'b0_1001_1,
TBOARD_ALPHA = 6'b1_0010_1,
ACNTRL_CMD = 6'b1_0110_1,
TRG3D_CP24 = 6'b1_1101_1;
wire [1:0] bc_nc_r = 2'b00; // Buffer Control No Connection.
wire hb_cmdclr;
reg hb_cmdclr_d,hb_cmdclr_dd,hb_cmdclr_ddd;
/***************************************************************************/
/* DEFINE ALL FIRST LEVEL REGISTERS IN THE DRAWING ENGINE */
/***************************************************************************/
reg bc_cr_r; /* Cache ready bit. */
reg bc_co_r; /* Cache on bit. */
reg bc_cs_r; /* Cache select bit. */
reg bc_org_md_r; /* origin mode. */
reg bc_8pg_r; /* force 8 page mode. */
reg [1:0] hform_r; /* Host format */
reg [2:0] key_ctrl_r;
reg bc_sen_r;
reg [1:0] bc_de_ps_r;
reg set_cl;
reg clint_1;
reg clint;
reg set_dd;
reg ddint_1;
reg ddint;
/***************************************************************************/
/* DEFINE OTHER REGISTERS */
/***************************************************************************/
reg cmdrdy_r; // command is ready for execution.
reg cmdrdy_rr; // command is ready for execution.
reg hcmd_rdy_tog; // host syncronous command ready
/***************************************************************************/
/* */
/* ASSIGN OUTPUTS TO REGISTERS */
/* */
/***************************************************************************/
assign buf_ctrl_1 = {
bc_cr_r, // [14]
bc_sen_r, // [13]
bc_co_r, // [12]
bc_cs_r, // [11]
hform_r, // [10:9]
bc_de_ps_r, // [8:7]
bc_nc_r, // [6:5]
bc_org_md_r, // [4]
bc_8pg_r, // [3]
key_ctrl_r // [2:0]
};
assign stpl_1 = style_1[3];
//
// REGISTER WRITE FUNCTION
// BYTE SELECTION ORDER
//
// | 31-24 | 23-16 | 15-8 | 7-0 |
// |hb_ben[3]|hb_ben[2]|hb_ben[1]|hb_ben[0]|
//
always @* begin
if(dlp_adr == {MEM_BCTRL, 1'b0} && !hb_csn && hb_wstrb && !hb_ben[3] && hb_din[31]) bc_cr_r = 1'b1;
else bc_cr_r = 1'b0;
end
//
// Interrupts.
//
always @(posedge hb_clk or negedge hb_rstn) begin
if (!hb_rstn) intp <= 2'b00;
else if (!hb_ben[0] && !hb_csn && hb_wstrb && (dlp_adr == {INTM_INTP, 1'b0}))
intp <= hb_din[1:0];
else begin
if (set_dd) intp[0] <= 1'b1;
if (set_cl) intp[1] <= 1'b1;
end
end
always @(posedge hb_clk) begin
set_cl <= clint ^ clint_1;
clint_1 <= clint;
clint <= de_clint_tog;
set_dd <= ddint ^ ddint_1;
ddint_1 <= ddint;
ddint <= de_ddint_tog;
interrupt <= |(intm & intp);
end
////////////////////////////////////////////////////////////////////////////
//
// Register Writes.
//
always @(posedge hb_clk or negedge hb_rstn) begin
if (!hb_rstn) begin
opc_1 <= 4'h0;
bc_cs_r <= 1'b0;
acntrl_1 <= 18'b0;
mem_offset_1 <= 7'b0;
sorg_upper_1 <= 4'b0;
hdf_1 <= 3'b0;
end else if (!hb_csn && hb_wstrb) begin
case (dlp_adr)
{INTM_INTP, 1'b1}: begin
if(!hb_ben[0]) intm <= hb_din[1:0];
end
{NA_TSORG, 1'b0}:
if(!hb_ben[3]) sorg_upper_1 <= hb_din[31:28];
{MEM_BCTRL, 1'b0}: begin
if(!hb_ben[3]) bc_co_r <= hb_din[30];
if(!hb_ben[3]) bc_cs_r <= hb_din[29];
if(!hb_ben[3]) hform_r <= hb_din[27:26];
if(!hb_ben[3]) bc_de_ps_r <= hb_din[25:24];
if(!hb_ben[1]) bc_org_md_r <= hb_din[15];
if(!hb_ben[1]) bc_sen_r <= hb_din[8];
if(!hb_ben[0]) {bc_lvl_1,bc_8pg_r} <= hb_din[7:5];
if(!hb_ben[0]) key_ctrl_r <= hb_din[2:0];
end
{MEM_BCTRL, 1'b1}: begin
if(!hb_ben[3]) mem_offset_1 <= hb_din[31:25];
end
{DORG_SORG, 1'b0}: begin
if(!hb_ben[0]) sorg_1[7:0] <= hb_din[7:0];
if(!hb_ben[1]) sorg_1[15:8] <= hb_din[15:8];
if(!hb_ben[2]) sorg_1[23:16] <= hb_din[23:16];
if(!hb_ben[3]) sorg_1[31:24] <= hb_din[31:24];
end
{DORG_SORG, 1'b1}: begin
if(!hb_ben[0]) dorg_1[7:0] <= hb_din[7:0];
if(!hb_ben[1]) dorg_1[15:8] <= hb_din[15:8];
if(!hb_ben[2]) dorg_1[23:16] <= hb_din[23:16];
if(!hb_ben[3]) dorg_1[31:24] <= hb_din[31:24];
end
{DPTCH_SPTCH, 1'b0}: begin
if(!hb_ben[0]) sptch_1[3:0] <= hb_din[7:4];
if(!hb_ben[1]) sptch_1[11:4] <= hb_din[15:8];
end
{DPTCH_SPTCH, 1'b1}: begin
if(!hb_ben[0]) dptch_1[3:0] <= hb_din[7:4];
if(!hb_ben[1]) dptch_1[11:4] <= hb_din[15:8];
end
{CMDR, 1'b0}, {ACNTRL_CMD, 1'b0}: begin
if(!hb_ben[0]) opc_1 <= hb_din[3:0];
if(!hb_ben[1]) rop_1 <= hb_din[11:8];
if(!hb_ben[2]) {clp_1,style_1} <= hb_din[23:16];
if(!hb_ben[3]) {hdf_1,patrn_1} <= hb_din[30:24];
end
{ROP_OPC, 1'b0}:
if(!hb_ben[0]) opc_1 <= hb_din[3:0];
{ROP_OPC, 1'b1}:
if(!hb_ben[0]) rop_1 <= hb_din[3:0];
{PATRN_STYLE, 1'b0}:
if(!hb_ben[0]) style_1 <= hb_din[4:0];
{PATRN_STYLE, 1'b1}:
if(!hb_ben[0]) patrn_1 <= hb_din[3:0];
{SFD_CLP, 1'b0}:
if(!hb_ben[0]) clp_1 <= hb_din[2:0];
{SFD_CLP, 1'b1}:
if(!hb_ben[0]) hdf_1 <= hb_din[2:0];
{BACK_FORE, 1'b0}: begin
if(!hb_ben[0]) fore_1[7:0] <= hb_din[7:0];
if(!hb_ben[1]) fore_1[15:8] <= hb_din[15:8];
if(!hb_ben[2]) fore_1[23:16] <= hb_din[23:16];
if(!hb_ben[3]) fore_1[31:24] <= hb_din[31:24];
end
{BACK_FORE, 1'b1}: begin
if(!hb_ben[0]) back_1[7:0] <= hb_din[7:0];
if(!hb_ben[1]) back_1[15:8] <= hb_din[15:8];
if(!hb_ben[2]) back_1[23:16] <= hb_din[23:16];
if(!hb_ben[3]) back_1[31:24] <= hb_din[31:24];
end
{DEKEY_MASK, 1'b0}: begin
// The plane mask now operates on the byte level.
// If any bit is set in a byte then unmask the whole byte
if(!hb_ben[0]) mask_1[0] <= |hb_din[7:0];
if(!hb_ben[1]) mask_1[1] <= |hb_din[15:8];
if(!hb_ben[2]) mask_1[2] <= |hb_din[23:16];
if(!hb_ben[3]) mask_1[3] <= |hb_din[31:24];
end
{DEKEY_MASK, 1'b1}: begin
if(!hb_ben[0]) de_key_1[7:0] <= hb_din[7:0];
if(!hb_ben[1]) de_key_1[15:8] <= hb_din[15:8];
if(!hb_ben[2]) de_key_1[23:16] <= hb_din[23:16];
end
{PCTRL_LPAT, 1'b0}: begin
if(!hb_ben[0]) lpat_1[7:0] <= hb_din[7:0];
if(!hb_ben[1]) lpat_1[15:8] <= hb_din[15:8];
if(!hb_ben[2]) lpat_1[23:16] <= hb_din[23:16];
if(!hb_ben[3]) lpat_1[31:24] <= hb_din[31:24];
end
{PCTRL_LPAT, 1'b1}: begin
if(!hb_ben[0]) pctrl_1[7:0] <= hb_din[7:0];
if(!hb_ben[1]) pctrl_1[15:8] <= hb_din[15:8];
end
{CLPBR_CLPTL, 1'b0}: begin
if(!hb_ben[0]) clptl_1[7:0] <= hb_din[7:0];
if(!hb_ben[1]) clptl_1[15:8] <= hb_din[15:8];
if(!hb_ben[2]) clptl_1[23:16] <= hb_din[23:16];
if(!hb_ben[3]) clptl_1[31:24] <= hb_din[31:24];
end
{CLPBR_CLPTL, 1'b1}: begin
if(!hb_ben[0]) clpbr_1[7:0] <= hb_din[7:0];
if(!hb_ben[1]) clpbr_1[15:8] <= hb_din[15:8];
if(!hb_ben[2]) clpbr_1[23:16] <= hb_din[23:16];
if(!hb_ben[3]) clpbr_1[31:24] <= hb_din[31:24];
end
{XY1_XY0, 1'b0}: begin
if(!hb_ben[0]) xy0_1[7:0] <= hb_din[7:0];
if(!hb_ben[1]) xy0_1[15:8] <= hb_din[15:8];
if(!hb_ben[2]) xy0_1[23:16] <= hb_din[23:16];
if(!hb_ben[3]) xy0_1[31:24] <= hb_din[31:24];
end
{XY1_XY0, 1'b1}: begin
if(!hb_ben[0]) xy1_1[7:0] <= hb_din[7:0];
if(!hb_ben[1]) xy1_1[15:8] <= hb_din[15:8];
if(!hb_ben[2]) xy1_1[23:16] <= hb_din[23:16];
if(!hb_ben[3]) xy1_1[31:24] <= hb_din[31:24];
end
{XY3_XY2, 1'b0}: begin
if(!hb_ben[0]) xy2_1[7:0] <= hb_din[7:0];
if(!hb_ben[1]) xy2_1[15:8] <= hb_din[15:8];
if(!hb_ben[2]) xy2_1[23:16] <= hb_din[23:16];
if(!hb_ben[3]) xy2_1[31:24] <= hb_din[31:24];
end
{XY3_XY2, 1'b1}: begin
if(!hb_ben[0]) xy3_1[7:0] <= hb_din[7:0];
if(!hb_ben[1]) xy3_1[15:8] <= hb_din[15:8];
if(!hb_ben[2]) xy3_1[23:16] <= hb_din[23:16];
if(!hb_ben[3]) xy3_1[31:24] <= hb_din[31:24];
end
{NA_XY4, 1'b0}: begin
if(!hb_ben[0]) xy4_1[7:0] <= hb_din[7:0];
if(!hb_ben[1]) xy4_1[15:8] <= hb_din[15:8];
if(!hb_ben[2]) xy4_1[23:16] <= hb_din[23:16];
if(!hb_ben[3]) xy4_1[31:24] <= hb_din[31:24];
end
{TBOARD_ALPHA, 1'b0}: begin
if(!hb_ben[0]) alpha_1[7:0] <= hb_din[7:0];
if(!hb_ben[1]) alpha_1[15:8] <= hb_din[15:8];
end
{ACNTRL_CMD, 1'b1}: begin
if(!hb_ben[0]) acntrl_1[7:0] <= hb_din[7:0];// dst(4), src(4)
if(!hb_ben[1]) acntrl_1[10:8] <= hb_din[10:8]; //
if(!hb_ben[2]) acntrl_1[14:11] <= hb_din[20:16]; //
if(!hb_ben[3]) acntrl_1[17:15] <= hb_din[26:24]; //
end
endcase // case(dlp_adr)
end
end // always @ (posedge hb_clk)
/***************************************************************************/
/* LATCH THE COMMAND TRIGGER */
/***************************************************************************/
// Hit XY1 or CP1 and not in 3D line or Triangle
always @* cmd_trig_comb = (!hb_csn && hb_wstrb && (dlp_adr == {XY1_XY0, 1'b1}) && !hb_ben[3]) ||
// Hit 3D trigger
(!hb_csn && hb_wstrb && (dlp_adr == {TRG3D_CP24, 1'b1}) && !hb_ben[3] && en_3d);
//
// Busy to the host goes active right away.
//
always @(posedge hb_clk or negedge hb_rstn) begin
if (!hb_rstn) busy_hb <= 1'b0;
else if (hb_cmdclr) busy_hb <= 1'b0;
else if (cmd_trig_comb) busy_hb <= 1'b1;
end
//
//Once the dispatcher accepts the command the cmdack is sent back.
// This toggles "hb_cmdclr_ddd"
always @(posedge de_clk or negedge hb_rstn) begin
if (!hb_rstn) hb_cmdclr_ddd <= 1'b0;
else if (cmdack) hb_cmdclr_ddd <= ~hb_cmdclr_ddd;
end
// Syncronize the command clear toggle
always @(posedge hb_clk) begin
hb_cmdclr_dd <= hb_cmdclr_ddd;
hb_cmdclr_d <= hb_cmdclr_dd;
end
// Generate host bus command clear signal.
// This clears "busy_hb".
assign hb_cmdclr = hb_cmdclr_d ^ hb_cmdclr_dd;
always @(posedge hb_clk, negedge hb_rstn) begin
if (!hb_rstn) hcmd_rdy_tog <= 1'b0;
else if (cmd_trig_comb) hcmd_rdy_tog <= ~hcmd_rdy_tog;
end
// Syncronize command ready.
always @(posedge de_clk, negedge de_rstn) begin
if(!de_rstn) cmdrdy <= 1'b0;
else if(cmdrdy_rr ^ cmdrdy_r) cmdrdy <= 1'b1;
else if(cmdack) cmdrdy <= 1'b0;
end
// Syncronize command ready.
always @(posedge de_clk) begin
cmdrdy_rr <= cmdrdy_r;
cmdrdy_r <= hcmd_rdy_tog;
end
//////////////////////////////////////////////////////////////////////////////
// Simulation debug stuff.
`ifdef RTL_SIM
always @* begin
if (cmdack) begin
case (opc_1)
4'h0:
$display($stime, " Executing NOP\n");
4'h1: begin
$display($stime, " Executing BitBlt\n");
$display("\t\tFORE: %h", fore_1);
$display("\t\tBACK: %h", back_1);
$display("\t\tXY0: %h", xy0_1);
$display("\t\tXY1: %h", xy1_1);
$display("\t\tXY2: %h", xy2_1);
$display("\t\tXY3: %h", xy3_1);
$display("\t\tXY4: %h", xy4_1);
end
4'h2: begin
$display($stime, " Executing Line\n");
$display("\t\tFORE: %h", fore_1);
$display("\t\tBACK: %h", back_1);
$display("\t\tXY0: %h", xy0_1);
$display("\t\tXY1: %h", xy1_1);
end
4'h3: begin
$display($stime, " Executing ELine\n");
$display("\t\tFORE: %h", fore_1);
$display("\t\tBACK: %h", back_1);
$display("\t\tXY0: %h", xy0_1);
$display("\t\tXY1: %h", xy1_1);
$display("\t\tXY2: %h", xy2_1);
$display("\t\tXY3: %h", xy3_1);
end
4'h5: begin
$display($stime, " Executing PLine\n");
$display("\t\tFORE: %h", fore_1);
$display("\t\tBACK: %h", back_1);
$display("\t\tXY0: %h", xy0_1);
end
4'h6: begin
$display($stime, " Obsolete OPCODE RXFER\n");
end
4'h7: begin
$display($stime, " Obsolete OPCODE WXFER\n");
end
4'h8: begin
$display($stime, " Executing 3D Line\n");
end
4'h9: begin
$display($stime, " Executing 3D Triangle\n");
end
4'ha: begin
$display($stime, " Executing Texture Invalidate\n");
end
4'hb: begin
$display($stime, " Executing Load Palette\n");
end
default: begin
$display($stime, "Undefined Opcode\n");
$display("Undefined Opcode = %h", opc_1);
end
endcase // case (rop)
end // if (cmdack)
end // always @ *
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND3B_SYMBOL_V
`define SKY130_FD_SC_MS__NAND3B_SYMBOL_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nand3b (
//# {{data|Data Signals}}
input A_N,
input B ,
input C ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND3B_SYMBOL_V
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire5;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
wire locked = sub_wire5;
altpll altpll_component (
.areset (areset),
.inclk (sub_wire1),
.clk (sub_wire3),
.locked (sub_wire5),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 45,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 161,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 41666,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "45"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "85.866669"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "24.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "161"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "85.90908000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "45"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "161"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "41666"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE
// Retrieval info: CBX_MODULE_PREFIX: ON
|
//wishbone master interconnect testbench
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/* Log
04/16/2013
-implement naming convention
08/30/2012
-Major overhall of the testbench
-modfied the way reads and writes happen, now each write requires the
number of 32-bit data packets even if the user sends only 1
-there is no more streaming as the data_count will implicity declare
that a read/write is streaming
-added the ih_reset which has not been formally defined within the
system, but will more than likely reset the entire statemachine
11/12/2011
-overhauled the design to behave more similar to a real I/O handler
-changed the timeout to 40 seconds to allow the wishbone master to catch
nacks
11/08/2011
-added interrupt support
*/
`timescale 1 ns/1 ps
`define TIMEOUT_COUNT 40
`define INPUT_FILE "sim/master_input_test_data.txt"
`define OUTPUT_FILE "sim/master_output_test_data.txt"
`define CLK_HALF_PERIOD 10
`define CLK_PERIOD (2 * `CLK_HALF_PERIOD)
`define SLEEP_HALF_CLK #(`CLK_HALF_PERIOD)
`define SLEEP_FULL_CLK #(`CLK_PERIOD)
//Sleep a number of clock cycles
`define SLEEP_CLK(x) #(x * `CLK_PERIOD)
//`define VERBOSE
module wishbone_master_tb (
);
//Virtual Host Interface Signals
//reg clk = 0;
wire clk;
//reg rst = 0;
wire rst;
wire w_master_ready;
reg r_in_ready = 0;
reg [31:0] r_in_command = 32'h00000000;
reg [31:0] r_in_address = 32'h00000000;
reg [31:0] r_in_data = 32'h00000000;
reg [27:0] r_in_data_count = 0;
reg r_out_ready = 0;
wire w_out_en;
wire [31:0] w_out_status;
wire [31:0] w_out_address;
wire [31:0] w_out_data;
wire [27:0] w_out_data_count;
reg r_ih_reset = 0;
//wishbone signals
wire w_wbm_we;
wire w_wbm_cyc;
wire w_wbm_stb;
wire [3:0] w_wbm_sel;
wire [31:0] w_wbm_adr;
wire [31:0] w_wbm_dat_o;
wire [31:0] w_wbm_dat_i;
wire w_wbm_ack;
wire w_wbm_int;
//Wishbone Slave 0 (SDB) signals
wire w_wbs0_we;
wire w_wbs0_cyc;
wire [31:0] w_wbs0_dat_o;
wire w_wbs0_stb;
wire [3:0] w_wbs0_sel;
wire w_wbs0_ack;
wire [31:0] w_wbs0_dat_i;
wire [31:0] w_wbs0_adr;
wire w_wbs0_int;
//wishbone slave 1 (Unit Under Test) signals
wire w_wbs1_we;
wire w_wbs1_cyc;
wire w_wbs1_stb;
wire [3:0] w_wbs1_sel;
wire w_wbs1_ack;
wire [31:0] w_wbs1_dat_i;
wire [31:0] w_wbs1_dat_o;
wire [31:0] w_wbs1_adr;
wire w_wbs1_int;
//Local Parameters
localparam WAIT_FOR_SDRAM = 8'h00;
localparam IDLE = 8'h01;
localparam SEND_COMMAND = 8'h02;
localparam MASTER_READ_COMMAND = 8'h03;
localparam RESET = 8'h04;
localparam PING_RESPONSE = 8'h05;
localparam WRITE_DATA = 8'h06;
localparam WRITE_RESPONSE = 8'h07;
localparam GET_WRITE_DATA = 8'h08;
localparam READ_RESPONSE = 8'h09;
localparam READ_MORE_DATA = 8'h0A;
localparam FINISHED = 8'h0B;
//Registers/Wires/Simulation Integers
integer fd_in;
integer fd_out;
integer read_count;
integer timeout_count;
integer ch;
integer data_count;
reg [3:0] state = IDLE;
reg prev_int = 0;
reg execute_command;
reg command_finished;
reg request_more_data;
reg request_more_data_ack;
reg [27:0] data_write_count;
reg [27:0] data_read_count;
//Submodules
wishbone_master wm (
.clk (clk ),
.rst (rst ),
.i_ih_rst (r_ih_reset ),
.i_ready (r_in_ready ),
.i_command (r_in_command ),
.i_address (r_in_address ),
.i_data (r_in_data ),
.i_data_count (r_in_data_count ),
.i_out_ready (r_out_ready ),
.o_en (w_out_en ),
.o_status (w_out_status ),
.o_address (w_out_address ),
.o_data (w_out_data ),
.o_data_count (w_out_data_count ),
.o_master_ready (w_master_ready ),
.o_per_we (w_wbm_we ),
.o_per_adr (w_wbm_adr ),
.o_per_dat (w_wbm_dat_i ),
.i_per_dat (w_wbm_dat_o ),
.o_per_stb (w_wbm_stb ),
.o_per_cyc (w_wbm_cyc ),
.o_per_msk (w_wbm_msk ),
.o_per_sel (w_wbm_sel ),
.i_per_ack (w_wbm_ack ),
.i_per_int (w_wbm_int )
);
//slave 1
wb_nysa_artemis_platform s1 (
.clk (clk ),
.rst (rst ),
.i_wbs_we (w_wbs1_we ),
.i_wbs_cyc (w_wbs1_cyc ),
.i_wbs_dat (w_wbs1_dat_i ),
.i_wbs_stb (w_wbs1_stb ),
.o_wbs_ack (w_wbs1_ack ),
.o_wbs_dat (w_wbs1_dat_o ),
.i_wbs_adr (w_wbs1_adr ),
.o_wbs_int (w_wbs1_int )
);
wishbone_interconnect wi (
.clk (clk ),
.rst (rst ),
.i_m_we (w_wbm_we ),
.i_m_cyc (w_wbm_cyc ),
.i_m_stb (w_wbm_stb ),
.o_m_ack (w_wbm_ack ),
.i_m_dat (w_wbm_dat_i ),
.o_m_dat (w_wbm_dat_o ),
.i_m_adr (w_wbm_adr ),
.o_m_int (w_wbm_int ),
.o_s0_we (w_wbs0_we ),
.o_s0_cyc (w_wbs0_cyc ),
.o_s0_stb (w_wbs0_stb ),
.i_s0_ack (w_wbs0_ack ),
.o_s0_dat (w_wbs0_dat_i ),
.i_s0_dat (w_wbs0_dat_o ),
.o_s0_adr (w_wbs0_adr ),
.i_s0_int (w_wbs0_int ),
.o_s1_we (w_wbs1_we ),
.o_s1_cyc (w_wbs1_cyc ),
.o_s1_stb (w_wbs1_stb ),
.i_s1_ack (w_wbs1_ack ),
.o_s1_dat (w_wbs1_dat_i ),
.i_s1_dat (w_wbs1_dat_o ),
.o_s1_adr (w_wbs1_adr ),
.i_s1_int (w_wbs1_int )
);
assign w_wbs0_ack = 0;
assign w_wbs0_dat_o = 0;
assign start = 1;
//always #`CLK_HALF_PERIOD clk = ~clk;
initial begin
fd_out = 0;
read_count = 0;
data_count = 0;
timeout_count = 0;
request_more_data_ack <= 0;
execute_command <= 0;
$dumpfile ("design.vcd");
$dumpvars (0, wishbone_master_tb);
fd_in = $fopen(`INPUT_FILE, "r");
fd_out = $fopen(`OUTPUT_FILE, "w");
`SLEEP_HALF_CLK;
// rst <= 0;
`SLEEP_CLK(100);
// rst <= 1;
//clear the handler signals
r_in_ready <= 0;
r_in_command <= 0;
r_in_address <= 32'h0;
r_in_data <= 32'h0;
r_in_data_count <= 0;
r_out_ready <= 0;
//clear wishbone signals
`SLEEP_CLK(10);
// rst <= 0;
r_out_ready <= 1;
if (fd_in == 0) begin
$display ("TB: input stimulus file was not found");
end
else begin
//while there is still data to be read from the file
while (!$feof(fd_in)) begin
//read in a command
read_count = $fscanf (fd_in, "%h:%h:%h:%h\n",
r_in_data_count,
r_in_command,
r_in_address,
r_in_data);
//Handle Frindge commands/comments
if (read_count != 4) begin
if (read_count == 0) begin
ch = $fgetc(fd_in);
if (ch == "\#") begin
//$display ("Eat a comment");
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
`ifdef VERBOSE $display (""); `endif
end
else begin
`ifdef VERBOSE $display ("Error unrecognized line: %h" % ch); `endif
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
end
end
else if (read_count == 1) begin
`ifdef VERBOSE $display ("Sleep for %h Clock cycles", r_in_data_count); `endif
`SLEEP_CLK(r_in_data_count);
`ifdef VERBOSE $display ("Sleep Finished"); `endif
end
else begin
`ifdef VERBOSE $display ("Error: read_count = %h != 4", read_count); `endif
`ifdef VERBOSE $display ("Character: %h", ch); `endif
end
end
else begin
`ifdef VERBOSE
case (r_in_command)
0: $display ("TB: Executing PING commad");
1: $display ("TB: Executing WRITE command");
2: $display ("TB: Executing READ command");
3: $display ("TB: Executing RESET command");
endcase
`endif
`ifdef VERBOSE $display ("Execute Command"); `endif
execute_command <= 1;
`SLEEP_CLK(1);
while (~command_finished) begin
request_more_data_ack <= 0;
if ((r_in_command & 32'h0000FFFF) == 1) begin
if (request_more_data && ~request_more_data_ack) begin
read_count = $fscanf(fd_in, "%h\n", r_in_data);
`ifdef VERBOSE $display ("TB: reading a new double word: %h", r_in_data); `endif
request_more_data_ack <= 1;
end
end
//so time porgresses wait a tick
`SLEEP_CLK(1);
//this doesn't need to be here, but there is a weird behavior in iverilog
//that wont allow me to put a delay in right before an 'end' statement
//execute_command <= 1;
end //while command is not finished
execute_command <= 0;
while (command_finished) begin
`ifdef VERBOSE $display ("Command Finished"); `endif
`SLEEP_CLK(1);
execute_command <= 0;
end
`SLEEP_CLK(50);
`ifdef VERBOSE $display ("TB: finished command"); `endif
end //end read_count == 4
end //end while ! eof
end //end not reset
`SLEEP_CLK(50);
$fclose (fd_in);
$fclose (fd_out);
$finish();
end
//initial begin
// $monitor("%t, state: %h", $time, state);
//end
//initial begin
// $monitor("%t, data: %h, state: %h, execute command: %h", $time, w_wbm_dat_o, state, execute_command);
//end
//initial begin
//$monitor("%t, state: %h, execute: %h, cmd_fin: %h", $time, state, execute_command, command_finished);
//$monitor("%t, state: %h, write_size: %d, write_count: %d, execute: %h", $time, state, r_in_data_count, data_write_count, execute_command);
//end
always @ (posedge clk) begin
if (rst) begin
state <= WAIT_FOR_SDRAM;
request_more_data <= 0;
timeout_count <= 0;
prev_int <= 0;
r_ih_reset <= 0;
data_write_count <= 0;
data_read_count <= 1;
command_finished <= 0;
end
else begin
r_ih_reset <= 0;
r_in_ready <= 0;
r_out_ready <= 1;
command_finished <= 0;
//Countdown the NACK timeout
if (execute_command && timeout_count < `TIMEOUT_COUNT) begin
timeout_count <= timeout_count + 1;
end
if (execute_command && timeout_count >= `TIMEOUT_COUNT) begin
`ifdef VERBOSE
case (r_in_command)
0: $display ("TB: Master timed out while executing PING commad");
1: $display ("TB: Master timed out while executing WRITE command");
2: $display ("TB: Master timed out while executing READ command");
3: $display ("TB: Master timed out while executing RESET command");
endcase
`endif
command_finished <= 1;
state <= IDLE;
timeout_count <= 0;
end //end reached the end of a timeout
case (state)
WAIT_FOR_SDRAM: begin
timeout_count <= 0;
r_in_ready <= 0;
//Uncomment 'start' conditional to wait for SDRAM to finish starting
//up
if (start) begin
`ifdef VERBOSE $display ("TB: sdram is ready"); `endif
state <= IDLE;
end
end
IDLE: begin
timeout_count <= 0;
command_finished <= 0;
data_write_count <= 1;
if (execute_command && !command_finished) begin
state <= SEND_COMMAND;
end
data_read_count <= 1;
end
SEND_COMMAND: begin
timeout_count <= 0;
if (w_master_ready) begin
r_in_ready <= 1;
state <= MASTER_READ_COMMAND;
end
end
MASTER_READ_COMMAND: begin
r_in_ready <= 1;
if (!w_master_ready) begin
r_in_ready <= 0;
case (r_in_command & 32'h0000FFFF)
0: begin
state <= PING_RESPONSE;
end
1: begin
if (r_in_data_count > 1) begin
`ifdef VERBOSE $display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data); `endif
if (data_write_count < r_in_data_count) begin
state <= WRITE_DATA;
timeout_count <= 0;
data_write_count<= data_write_count + 1;
end
else begin
`ifdef VERBOSE $display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count); `endif
state <= WRITE_RESPONSE;
end
end
else begin
`ifdef VERBOSE $display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data); `endif
`ifdef VERBOSE $display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count); `endif
state <= WRITE_RESPONSE;
end
end
2: begin
state <= READ_RESPONSE;
end
3: begin
state <= RESET;
end
endcase
end
end
RESET: begin
r_ih_reset <= 1;
state <= RESET;
end
PING_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == 8'hFF) begin
`ifdef VERBOSE $display ("TB: Ping Response Good"); `endif
end
else begin
`ifdef VERBOSE $display ("TB: Ping Response Bad (Malformed response: %h)", w_out_status); `endif
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
state <= FINISHED;
end
end
WRITE_DATA: begin
if (!r_in_ready && w_master_ready) begin
state <= GET_WRITE_DATA;
request_more_data <= 1;
end
end
WRITE_RESPONSE: begin
`ifdef VERBOSE $display ("In Write Response"); `endif
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h01))) begin
`ifdef VERBOSE $display ("TB: Write Response Good"); `endif
end
else begin
`ifdef VERBOSE $display ("TB: Write Response Bad (Malformed response: %h)", w_out_status); `endif
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
state <= FINISHED;
end
end
GET_WRITE_DATA: begin
if (request_more_data_ack) begin
request_more_data <= 0;
r_in_ready <= 1;
state <= SEND_COMMAND;
end
end
READ_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h02))) begin
`ifdef VERBOSE $display ("TB: Read Response Good"); `endif
if (w_out_data_count > 0) begin
if (data_read_count < w_out_data_count) begin
state <= READ_MORE_DATA;
timeout_count <= 0;
data_read_count <= data_read_count + 1;
end
else begin
state <= FINISHED;
end
end
end
else begin
`ifdef VERBOSE $display ("TB: Read Response Bad (Malformed response: %h)", w_out_status); `endif
state <= FINISHED;
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
end
end
READ_MORE_DATA: begin
if (w_out_en) begin
timeout_count <= 0;
r_out_ready <= 0;
`ifdef VERBOSE $display ("TB: Read a 32bit data packet"); `endif
`ifdef VERBOSE $display ("TB: \tRead Data: %h", w_out_data); `endif
data_read_count <= data_read_count + 1;
end
if (data_read_count >= r_in_data_count) begin
state <= FINISHED;
end
end
FINISHED: begin
command_finished <= 1;
if (!execute_command) begin
`ifdef VERBOSE $display ("Execute Command is low"); `endif
command_finished <= 0;
state <= IDLE;
end
end
endcase
if (w_out_en && w_out_status == `PERIPH_INTERRUPT) begin
`ifdef VERBOSE $display("TB: Output Handler Recieved interrupt"); `endif
`ifdef VERBOSE $display("TB:\tcommand: %h", w_out_status); `endif
`ifdef VERBOSE $display("TB:\taddress: %h", w_out_address); `endif
`ifdef VERBOSE $display("TB:\tdata: %h", w_out_data); `endif
end
end//not reset
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O41A_SYMBOL_V
`define SKY130_FD_SC_LP__O41A_SYMBOL_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o41a (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input A4,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O41A_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21BA_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__O21BA_PP_SYMBOL_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__o21ba (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21BA_PP_SYMBOL_V
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MEMC
// / / Filename: mcb_traffic_gen.v
// /___/ /\ Date Last Modified: $Date:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Virtex7
//Design Name: s7ven_data_gen
//Purpose: This is top level module of memory traffic generator which can
// generate different CMD_PATTERN and DATA_PATTERN to Virtex 7
// hard memory controller core.
// Supported Data pattern: 0 : Reserved.
// 1 : FIXED_DATA_MODE.
// 2 : ADDR_DATA_MODE
// 3 : HAMMER_DATA_MODE
// 4 : NEIGHBOR_DATA_MODE
// 5 : WALKING1_DATA_MODE
// 6 : WALKING0_DATA_MODE
// 7 : TRUE_PRBS_MODE
//
//
//Reference:
//Revision History: 1.1
//*****************************************************************************
`timescale 1ps/1ps
`ifndef TCQ
`define TCQ 100
`endif
module s7ven_data_gen #
( parameter DMODE = "WRITE",
parameter nCK_PER_CLK = 2, // 2: Memc core speed 1/2 of memory clock speed.
// User data bus width = 4 x DQs data width.
// 4: memc core speed 1/4 of memory clock speed.
// User data bus width = 8 x DQs data width.
parameter TCQ = 100,
parameter BL_WIDTH = 6, // USER_Interface Command Burst Length
parameter FAMILY = "SPARTAN6",
parameter EYE_TEST = "FALSE",
parameter ADDR_WIDTH = 32,
parameter MEM_BURST_LEN = 8,
parameter START_ADDR = 32'h00000000,
parameter DWIDTH = 32,
parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter NUM_DQ_PINS = 72,
parameter COLUMN_WIDTH = 10,
parameter SEL_VICTIM_LINE = 3 // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
// parameter [287:0] ALL_1 = {288{1'b1}},
// parameter [287:0] ALL_0 = {288{1'b0}}
)
(
input clk_i, //
input rst_i,
input [31:0] prbs_fseed_i,
input mode_load_i,
input mem_init_done_i,
input wr_data_mask_gen_i,
input [3:0] data_mode_i, // "00" = bram;
input data_rdy_i,
input cmd_startA,
input cmd_startB,
input cmd_startC,
input cmd_startD,
input cmd_startE,
input [31:0] simple_data0 ,
input [31:0] simple_data1 ,
input [31:0] simple_data2 ,
input [31:0] simple_data3 ,
input [31:0] simple_data4 ,
input [31:0] simple_data5 ,
input [31:0] simple_data6 ,
input [31:0] simple_data7 ,
input [ADDR_WIDTH-1:0] m_addr_i, // generated address used to determine data pattern.
input [31:0] fixed_data_i,
input [ADDR_WIDTH-1:0] addr_i, // generated address used to determine data pattern.
input [BL_WIDTH:0] user_burst_cnt, // generated burst length for control the burst data
input fifo_rdy_i, // connect from mcb_wr_full when used as wr_data_gen
// connect from mcb_rd_empty when used as rd_data_gen
// When both data_rdy and data_valid is asserted, the ouput data is valid.
// input [(DWIDTH/8)-1:0] wr_mask_count;
output [(NUM_DQ_PINS*nCK_PER_CLK*2/8)-1:0] data_mask_o,
output [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_o , // generated data pattern
output bram_rd_valid_o
);
//
localparam PRBS_WIDTH = 8;//BL_WIDTH;
localparam TAPS_VALUE = (BL_WIDTH == 8) ? 8'b10001110 :
// (BL_WIDTH == 10) ? 10'b1000000100:
8'b10001110 ;
wire [31:0] prbs_data;
reg [35:0] acounts;
wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] fdata;
wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] bdata;
wire [31:0] bram_data;
wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] adata_tmp;
wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] adata;
wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] hammer_data;
reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] w1data;
reg [NUM_DQ_PINS*2-1:0] hdata;
reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] w0data;
reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data;
reg burst_count_reached2;
reg data_valid;
reg [2:0] walk_cnt;
reg [ADDR_WIDTH-1:0] user_address;
reg [ADDR_WIDTH-1:0] m_addr_r; // generated address used to determine data pattern.
reg sel_w1gen_logic;
//reg [7:0] BLANK;
reg [4*NUM_DQ_PINS -1 :0] sel_victimline_r;
wire data_clk_en,data_clk_en2;
wire [NUM_DQ_PINS*2*nCK_PER_CLK-1:0] full_prbs_data2;
wire [NUM_DQ_PINS*2*nCK_PER_CLK-1:0] psuedo_prbs_data;
reg [2*nCK_PER_CLK-1:0] prbs_mux_data;
reg [NUM_DQ_PINS*4-1:0] h_prbsdata;
wire [BL_WIDTH-1:0] prbs_seed;
reg [5:0] prbs_mux_counter;
reg [2*nCK_PER_CLK*16-1:0] prbs_comb_data;
reg prbs_seeded;
reg prbs_comb_data_load;
reg mode_has_loaded;
wire [127:0] prbs_shift_value;
reg next_calib_data;
reg [4*NUM_DQ_PINS-1:0 ] calib_data;
wire [2*nCK_PER_CLK*NUM_DQ_PINS/8 -1:0] w1data_group;
wire [31:0] mcb_prbs_data;
wire [NUM_DQ_PINS-1:0] prbsdata_rising_0;
wire [NUM_DQ_PINS-1:0] prbsdata_falling_0;
wire [NUM_DQ_PINS-1:0] prbsdata_rising_1;
wire [NUM_DQ_PINS-1:0] prbsdata_falling_1;
wire [NUM_DQ_PINS-1:0] prbsdata_rising_2;
wire [NUM_DQ_PINS-1:0] prbsdata_falling_2;
wire [NUM_DQ_PINS-1:0] prbsdata_rising_3;
wire [NUM_DQ_PINS-1:0] prbsdata_falling_3 ;
wire [BL_WIDTH-1:0] prbs_o0,prbs_o1,prbs_o2,prbs_o3,prbs_o4,prbs_o5,prbs_o6,prbs_o7;
wire [BL_WIDTH-1:0] prbs_o8,prbs_o9,prbs_o10,prbs_o11,prbs_o12,prbs_o13,prbs_o14,prbs_o15;
wire [3:0] prbs_shift_value0,prbs_shift_value1,prbs_shift_value2,prbs_shift_value3,prbs_shift_value4;
wire [3:0] prbs_shift_value5,prbs_shift_value6,prbs_shift_value7,prbs_shift_value8,prbs_shift_value9;
wire [3:0] prbs_shift_value10,prbs_shift_value11,prbs_shift_value12,prbs_shift_value13,prbs_shift_value14;
wire [3:0] prbs_shift_value15;
wire [3:0] prbs_shift_value16,prbs_shift_value17,prbs_shift_value18,prbs_shift_value19,prbs_shift_value20;
wire [3:0] prbs_shift_value21,prbs_shift_value22,prbs_shift_value23,prbs_shift_value24,prbs_shift_value25;
wire [3:0] prbs_shift_value26,prbs_shift_value27,prbs_shift_value28,prbs_shift_value29,prbs_shift_value30;
wire [3:0] prbs_shift_value31;
//wire [nCK_PER_CLK * 32 -1 :0] prbs_shift_value;
wire [nCK_PER_CLK * 256 -1:0] ReSeedcounter;
reg mode_load_r1,mode_load_r2;
reg [3:0] htstpoint ;
reg data_clk_en2_r;
reg force_load;
reg [NUM_DQ_PINS-1:0] wdatamask_ripplecnt;
//wire [4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] ALL_1 =
reg mode_load_r;
reg user_burst_cnt_larger_1_r;
integer i,j,k;
localparam USER_BUS_DWIDTH = (nCK_PER_CLK == 2) ? NUM_DQ_PINS*4 : NUM_DQ_PINS*8;
//*********************************************************************************************
localparam BRAM_DATAL_MODE = 4'b0000;
localparam FIXED_DATA_MODE = 4'b0001;
localparam ADDR_DATA_MODE = 4'b0010;
localparam HAMMER_DATA_MODE = 4'b0011;
localparam NEIGHBOR_DATA_MODE = 4'b0100;
localparam WALKING1_DATA_MODE = 4'b0101;
localparam WALKING0_DATA_MODE = 4'b0110;
localparam PRBS_DATA_MODE = 4'b0111;
assign data_o = data;
if (nCK_PER_CLK == 4)
assign full_prbs_data2 = {prbsdata_falling_3,prbsdata_rising_3,prbsdata_falling_2,prbsdata_rising_2,prbsdata_falling_1,prbsdata_rising_1,prbsdata_falling_0,prbsdata_rising_0};
else
assign full_prbs_data2 = {prbsdata_falling_1,prbsdata_rising_1,prbsdata_falling_0,prbsdata_rising_0};
generate
genvar p;
for (p = 0; p < NUM_DQ_PINS*nCK_PER_CLK*2/32; p = p+1) begin
assign psuedo_prbs_data[p*32+31:p*32] = mcb_prbs_data;
end
endgenerate
reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] w1data_o;
reg [3:0] data_mode_rr_a;
reg [3:0] data_mode_rr_c;
// write data mask generation.
// Only support data pattern = address data mode.
// When wdatamask_ripple_cnt is asserted, the corresponding wr_data word will be jammed with 8'hff.
assign data_mask_o = (wr_data_mask_gen_i == 1'b1 && mem_init_done_i) ? wdatamask_ripplecnt :{ NUM_DQ_PINS*nCK_PER_CLK*2/8{1'b0}};
always @ (posedge clk_i)
begin
if (rst_i || ~wr_data_mask_gen_i || ~mem_init_done_i)
wdatamask_ripplecnt <= 'b0;
else if (cmd_startA)
//wdatamask_ripplecnt <= {15'd0,1'b1};
wdatamask_ripplecnt <= {{NUM_DQ_PINS-1{1'b0}},1'b1};
else if (user_burst_cnt_larger_1_r && data_rdy_i)
wdatamask_ripplecnt <= {wdatamask_ripplecnt[NUM_DQ_PINS-2:0],wdatamask_ripplecnt[NUM_DQ_PINS-1]};
end
generate
genvar n;
for (n = 0; n < NUM_DQ_PINS*nCK_PER_CLK*2/8; n = n+1) begin
assign adata[n*8+7:n*8] = adata_tmp[n*8+7:n*8] | {8{wdatamask_ripplecnt[NUM_DQ_PINS-1]}};
end
endgenerate
always @ (posedge clk_i)
begin
data_mode_rr_a <= #TCQ data_mode_i;
data_mode_rr_c <= #TCQ data_mode_i;
end
assign bdata = {USER_BUS_DWIDTH/32{bram_data[31:0]}};
// selected data pattern go through "data" mux to user data bus.
// 72 pin 1: failed
always @ (bdata,calib_data,hammer_data,adata,data_mode_rr_a,w1data,full_prbs_data2,psuedo_prbs_data)
begin
case(data_mode_rr_a) //
// Simple Data Pattern for bring up
// 0: Reserved
// 1: 32 bits fixed_data from user defined inputs.
// The data from this static pattern is concatenated together multiple times
// to make up the required number of bits as needed.
// 2: 32 bits address as data
// The data from this pattern is concatenated together multiple times
// to make up the required number of bits as needed.
// 4: simple 8data pattern and repeats every 8 words. The pattern is embedded in RAM.
// 5,6: Walkign 1,0 data.
// a Calibration data pattern
// 0,1,2,3,4,9: use bram to implemnt.
4'b0000,4'b0001,4'b0100,4'b1001: data = bdata;
4'b0010: data = adata; // address as data
4'b0011: data = hammer_data;
4'b0101, 4'b110: data = w1data; // walking 1 or walking 0 data
// when vio_instr_mode_value set to 4'hf,the init_mem_pattern_ctr module
// will automatically set the data_mode_o to 0x8
4'b1010: data =calib_data;
// Characterization Mode
// 2: Address as data
// 3: hammer data with option to select VICTIM line which output is always high.
// 7: Hammer PRBS. Only valid in V6,V7 family
// 9: Slow 2 MHz hammer pattern.
4'b0111: data = full_prbs_data2;//{prbs_data,prbs_data,prbs_data,prbs_data}; // "011" = prbs
4'b1000: data = psuedo_prbs_data;//{prbs_data,prbs_data,prbs_data,prbs_data}; // "011" = prbs
default : begin
// for (i=0; i <= 4*NUM_DQ_PINS - 1; i= i+1) begin: neighbor_data
// data = begin
// for (
data = adata;
end
endcase
end
// phy calibration data pattern
//
always @ (posedge clk_i)
if (rst_i) begin
next_calib_data <= 1'b0;
calib_data <= #TCQ {{(NUM_DQ_PINS/8){8'h55}},{(NUM_DQ_PINS/8){8'haa}},{(NUM_DQ_PINS/8){8'h00}},{(NUM_DQ_PINS/8){8'hff}}};
end
else if (cmd_startA)
begin
calib_data <= #TCQ {{(NUM_DQ_PINS/8){8'h55}},{(NUM_DQ_PINS/8){8'haa}},{(NUM_DQ_PINS/8){8'h00}},{(NUM_DQ_PINS/8){8'hff}}};
next_calib_data <=#TCQ 1'b1;
// calib_data <= 'b0;
end
else if (fifo_rdy_i)
begin
next_calib_data <= #TCQ ~next_calib_data;
if (next_calib_data )
calib_data <= #TCQ {{(NUM_DQ_PINS/8){8'h66}},{(NUM_DQ_PINS/8){8'h99}},{(NUM_DQ_PINS/8){8'haa}},{(NUM_DQ_PINS/8){8'h55}}};
else
calib_data <= #TCQ {{(NUM_DQ_PINS/8){8'h55}},{(NUM_DQ_PINS/8){8'haa}},{(NUM_DQ_PINS/8){8'h00}},{(NUM_DQ_PINS/8){8'hff}}};
end
/*
always @ (posedge clk_i)
begin calib_data <= 'b0;
end
*/
//**************************************************************************
// Pattern bram generates fixed input, hammer, simple 8 repeat data pattern.
//**************************************************************************
function integer logb2;
input [31:0] in;
integer i;
begin
i = in;
for(logb2=1; i>0; logb2=logb2+1)
i = i >> 1;
end
endfunction
vio_init_pattern_bram #
( .MEM_BURST_LEN (MEM_BURST_LEN),
.START_ADDR (START_ADDR),
.NUM_DQ_PINS (NUM_DQ_PINS),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE)
)
vio_init_pattern_bram
(
.clk_i (clk_i ),
.rst_i (rst_i ),
// BL8 : least 3 address bits are always zero.
// BL4 " least 2 address bits are always zero.
// for walking 1's or 0's, the least 8 address bits are always zero.
.cmd_addr (addr_i),
.cmd_start (cmd_startB),
.mode_load_i (mode_load_i),
.data_mode_i (data_mode_rr_a),
//.w1data (w1data),
.data0 (simple_data0 ),
.data1 (simple_data1 ),
.data2 (simple_data2 ),
.data3 (simple_data3 ),
.data4 (simple_data4 ),
.data5 (simple_data5 ),
.data6 (simple_data6 ),
.data7 (simple_data7 ),
.data8 (fixed_data_i ),
.bram_rd_valid_o (bram_rd_valid_o),
.bram_rd_rdy_i (user_burst_cnt_larger_1_r & (data_rdy_i | cmd_startB)),
.dout_o (bram_data)
);
//**************************************************************
// Functions to be used byg Walking 1 and Walking 0 circuits.
//**************************************************************
function [2*nCK_PER_CLK*NUM_DQ_PINS-1:0] NbData_Gen (input integer i );
integer j;
begin
j = i/2;
NbData_Gen = {4*NUM_DQ_PINS{1'b0}};
if(i %2) begin
NbData_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00010000;
NbData_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b00100000;
NbData_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00000000;
NbData_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b00000000;
end else begin
NbData_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00000001;
NbData_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b00000010;
NbData_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00000000;
NbData_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b00000000;
end
end
endfunction
function [2*nCK_PER_CLK*NUM_DQ_PINS-1:0] Data_Gen (input integer i );
integer j;
begin
j = i/2;
Data_Gen = {2*nCK_PER_CLK*NUM_DQ_PINS{1'b0}};
if(i %2) begin
if (nCK_PER_CLK == 2) begin
Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00010000;
Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b01000000;
Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00100000;
Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b10000000;
end
else begin
Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00010000;
Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00100000;
Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b01000000;
Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b10000000;
Data_Gen[(4*NUM_DQ_PINS+j*8)+:8] = 8'b00000001;
Data_Gen[(5*NUM_DQ_PINS+j*8)+:8] = 8'b00000010;
Data_Gen[(6*NUM_DQ_PINS+j*8)+:8] = 8'b00000100;
Data_Gen[(7*NUM_DQ_PINS+j*8)+:8] = 8'b00001000;
end
end else begin
if (nCK_PER_CLK == 2) begin
Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00000001;
Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00000010;
Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b00000100;
Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b00001000;
end
else begin
Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00000001;
Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00000010;
Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b00000100;
Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b00001000;
Data_Gen[(4*NUM_DQ_PINS+j*8)+:8] = 8'b00010000;
Data_Gen[(5*NUM_DQ_PINS+j*8)+:8] = 8'b00100000;
Data_Gen[(6*NUM_DQ_PINS+j*8)+:8] = 8'b01000000;
Data_Gen[(7*NUM_DQ_PINS+j*8)+:8] = 8'b10000000;
end
end
end
endfunction
function [2*nCK_PER_CLK*NUM_DQ_PINS-1:0] Data_GenW0 (input integer i);
integer j;
begin
j = i/2;
Data_GenW0 = {2*nCK_PER_CLK*NUM_DQ_PINS{1'b1}};
if(i %2) begin
if (nCK_PER_CLK == 2) begin
Data_GenW0[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11101111;
Data_GenW0[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11011111;
Data_GenW0[(2*NUM_DQ_PINS+j*8)+:8] = 8'b10111111;
Data_GenW0[(3*NUM_DQ_PINS+j*8)+:8] = 8'b01111111;
end
else begin
Data_GenW0[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11101111;
Data_GenW0[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11011111;
Data_GenW0[(2*NUM_DQ_PINS+j*8)+:8] = 8'b10111111;
Data_GenW0[(3*NUM_DQ_PINS+j*8)+:8] = 8'b01111111;
Data_GenW0[(4*NUM_DQ_PINS+j*8)+:8] = 8'b11111110;
Data_GenW0[(5*NUM_DQ_PINS+j*8)+:8] = 8'b11111101;
Data_GenW0[(6*NUM_DQ_PINS+j*8)+:8] = 8'b11111011;
Data_GenW0[(7*NUM_DQ_PINS+j*8)+:8] = 8'b11110111;
end
end else begin
if (nCK_PER_CLK == 2) begin
Data_GenW0[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11111110;
Data_GenW0[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11111101;
Data_GenW0[(2*NUM_DQ_PINS+j*8)+:8] = 8'b11111011;
Data_GenW0[(3*NUM_DQ_PINS+j*8)+:8] = 8'b11110111;
end
else begin
Data_GenW0[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11111110;
Data_GenW0[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11111101;
Data_GenW0[(2*NUM_DQ_PINS+j*8)+:8] = 8'b11111011;
Data_GenW0[(3*NUM_DQ_PINS+j*8)+:8] = 8'b11110111;
Data_GenW0[(4*NUM_DQ_PINS+j*8)+:8] = 8'b11101111;
Data_GenW0[(5*NUM_DQ_PINS+j*8)+:8] = 8'b11011111;
Data_GenW0[(6*NUM_DQ_PINS+j*8)+:8] = 8'b10111111;
Data_GenW0[(7*NUM_DQ_PINS+j*8)+:8] = 8'b01111111;
end
end
end
endfunction
always @ (posedge clk_i) begin
if (data_mode_rr_c[2:0] == 3'b101 || data_mode_rr_c[2:0] == 3'b100 || data_mode_rr_c[2:0] == 3'b110) // WALKING ONES
sel_w1gen_logic <= #TCQ 1'b1;
else
sel_w1gen_logic <= #TCQ 1'b0;
end
generate
genvar m;
for (m=0; m < (2*nCK_PER_CLK*NUM_DQ_PINS/8) - 1; m= m+1) begin: w1_gp
assign w1data_group[m] = ( (w1data[(m*8+7):m*8]) != 8'h00);
end
endgenerate
generate
if ((NUM_DQ_PINS == 8 ) &&(DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_ALL")) begin : WALKING_ONE_8_PATTERN
always @ (posedge clk_i) begin
if( (fifo_rdy_i ) || cmd_startC )
if (cmd_startC ) begin
if (sel_w1gen_logic) begin
if (data_mode_i == 4'b0101)
w1data <= #TCQ Data_Gen(0);
else
w1data <= #TCQ Data_GenW0(0);
end
end
else if ( MEM_BURST_LEN == 8 && fifo_rdy_i ) begin
if ( nCK_PER_CLK == 2)
begin
w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]};
w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]};
w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]};
w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]};
end
else begin
w1data[8*NUM_DQ_PINS - 1:7*NUM_DQ_PINS] <= #TCQ w1data[8*NUM_DQ_PINS - 1:7*NUM_DQ_PINS ];
w1data[7*NUM_DQ_PINS - 1:6*NUM_DQ_PINS] <= #TCQ w1data[7*NUM_DQ_PINS - 1:6*NUM_DQ_PINS ];
w1data[6*NUM_DQ_PINS - 1:5*NUM_DQ_PINS] <= #TCQ w1data[6*NUM_DQ_PINS - 1:5*NUM_DQ_PINS ];
w1data[5*NUM_DQ_PINS - 1:4*NUM_DQ_PINS] <= #TCQ w1data[5*NUM_DQ_PINS - 1:4*NUM_DQ_PINS ];
w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS ] ;
w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS ];
w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS ] ;
w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS ];
end
end
end
end
endgenerate
generate
if ((NUM_DQ_PINS != 8 ) &&(DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_ALL")) begin : WALKING_ONE_64_PATTERN
always @ (posedge clk_i) begin
if( (fifo_rdy_i ) || cmd_startC )
if (cmd_startC ) begin
if (sel_w1gen_logic) begin
if (data_mode_i == 4'b0101)
w1data <= #TCQ Data_Gen(0);
else
w1data <= #TCQ Data_GenW0(0);
end
end
else if ( MEM_BURST_LEN == 8 && fifo_rdy_i ) begin
if ( nCK_PER_CLK == 2)
begin
w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]};
w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]};
w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]};
w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]};
end
else begin
w1data[8*NUM_DQ_PINS - 1:7*NUM_DQ_PINS] <= #TCQ {w1data[8*NUM_DQ_PINS - 9:7*NUM_DQ_PINS ],w1data[8*NUM_DQ_PINS - 1:8*NUM_DQ_PINS - 8]};
w1data[7*NUM_DQ_PINS - 1:6*NUM_DQ_PINS] <= #TCQ {w1data[7*NUM_DQ_PINS - 9:6*NUM_DQ_PINS ],w1data[7*NUM_DQ_PINS - 1:7*NUM_DQ_PINS - 8]};
w1data[6*NUM_DQ_PINS - 1:5*NUM_DQ_PINS] <= #TCQ {w1data[6*NUM_DQ_PINS - 9:5*NUM_DQ_PINS ],w1data[6*NUM_DQ_PINS - 1:6*NUM_DQ_PINS - 8]};
w1data[5*NUM_DQ_PINS - 1:4*NUM_DQ_PINS] <= #TCQ {w1data[5*NUM_DQ_PINS - 9:4*NUM_DQ_PINS ],w1data[5*NUM_DQ_PINS - 1:5*NUM_DQ_PINS - 8]};
w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 9:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 8]};
w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 9:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 8]};
w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 9:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 8]};
w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 9:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 8]};
end
end
end
end
endgenerate
// HAMMER_PATTERN_MINUS: generate walking HAMMER data pattern except 1 bit for the whole burst. The incoming addr_i[5:2] determine
// the position of the pin driving oppsite polarity
// addr_i[6:2] = 5'h0f ; 32 bit data port
// => the rsing data pattern will be 32'b11111111_11111111_01111111_11111111
// => the falling data pattern will be 32'b00000000_00000000_00000000_00000000
// Only generate NUM_DQ_PINS width of hdata and will do concatenation in above level.
always @ (posedge clk_i) begin
//for (j=0; j <= 1; j= j+1) //
// for (i= 0; i <= 31; i= i+1) //begin: hammer_data
for (i= 0; i <= 2*NUM_DQ_PINS - 1; i= i+1) //begin: hammer_data
if ( i >= NUM_DQ_PINS )
if (SEL_VICTIM_LINE == NUM_DQ_PINS)
hdata[i] <= 1'b0;
else if (
((i == SEL_VICTIM_LINE-1) ||
(i-NUM_DQ_PINS) == SEL_VICTIM_LINE ))//||
// (i-(NUM_DQ_PINS*2)) == SEL_VICTIM_LINE ||
// (i-(NUM_DQ_PINS*3)) == SEL_VICTIM_LINE))
hdata[i] <= 1'b1;
else
hdata[i] <= 1'b0;
else
hdata[i] <= 1'b1;
end
generate
if (nCK_PER_CLK == 2) begin : HAMMER_2
assign hammer_data = {2{hdata[2*NUM_DQ_PINS - 1:0]}};
end
endgenerate
generate
if (nCK_PER_CLK == 4) begin : HAMMER_4
assign hammer_data = {4{hdata[2*NUM_DQ_PINS - 1:0]}};
end
endgenerate
//nCK_PER_CLK : 1,2,4
// ADDRESS_PATTERN: use the address as the 1st data pattern for the whole burst. For example
// Dataport 32 bit width with starting addr_i = 32'h12345678, burst length 8
// => the 1st data pattern : 32'h12345680
// => the 2nd data pattern : 32'h12345688
// => the 3rd data pattern : 32'h12345690
// => the 4th data pattern : 32'h12345698
generate
if (DATA_PATTERN == "DGEN_ADDR" || DATA_PATTERN == "DGEN_ALL") begin : ADDRESS_PATTERN
always @ (posedge clk_i)
begin
if (cmd_startD)
acounts[35:0] <= #TCQ {4'b0000,addr_i} ;
else if (user_burst_cnt_larger_1_r && data_rdy_i ) begin
if (nCK_PER_CLK == 2)
if (FAMILY == "VIRTEX6")
acounts <= #TCQ acounts + 4;
else begin // "SPARTAN6"
if (DWIDTH == 32)
acounts <= #TCQ acounts + 4;
else if (DWIDTH == 64)
acounts <= #TCQ acounts + 8;
else if (DWIDTH == 64)
acounts <= #TCQ acounts + 16;
end
else
acounts <= #TCQ acounts + 8;
end
else
acounts <= #TCQ acounts;
end
assign adata_tmp = {USER_BUS_DWIDTH/32{acounts[31:0]}};
end
endgenerate
// PRBS_PATTERN: use the address as the PRBS seed data pattern for the whole burst. For example
// Dataport 32 bit width with starting addr_i = 30'h12345678, user burst length 4
//
//
//
//
generate
// When doing eye_test, traffic gen only does write and want to
// keep the prbs random and address is fixed at a location.
if (EYE_TEST == "TRUE") begin : d_clk_en1
assign data_clk_en = 1'b1;//fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1;
end
endgenerate
always @ (posedge clk_i)
begin
if (user_burst_cnt > 6'd1 || cmd_startE)
user_burst_cnt_larger_1_r <= 1'b1;
else
user_burst_cnt_larger_1_r <= 1'b0;
end
generate
if (EYE_TEST == "FALSE" || EYE_TEST == "READ_EYE") begin : d_clk_en2
assign data_clk_en = fifo_rdy_i && data_rdy_i && user_burst_cnt_larger_1_r > 6'd0;
assign data_clk_en2 = fifo_rdy_i && data_rdy_i && user_burst_cnt_larger_1_r > 6'd0;
end
endgenerate
generate
if (DATA_PATTERN == "DGEN_PRBS" || DATA_PATTERN == "DGEN_ALL") begin : PSUEDO_PRBS_PATTERN
// PRBS DATA GENERATION
// xor all the tap positions before feedback to 1st stage.
always @ (posedge clk_i)
m_addr_r <= m_addr_i;
data_prbs_gen #
(
.PRBS_WIDTH (32),
.SEED_WIDTH (32),
.EYE_TEST (EYE_TEST)
)
data_prbs_gen
(
.clk_i (clk_i),
.rst_i (rst_i),
.clk_en (data_clk_en),
// .prbs_fseed_i (prbs_fseed_i),
.prbs_seed_init (cmd_startE),
.prbs_seed_i (m_addr_i[31:0]),
.prbs_o (mcb_prbs_data)
);
end
endgenerate
wire [31:0] ReSeedcounter_o;
assign prbs_seed = START_ADDR[BL_WIDTH+1:2];//addr_i[13:2];
always @ (posedge clk_i)
begin
if (rst_i)
prbs_seeded <= 1'b0;
else if (cmd_startE)
if ( data_mode_i == 4'b0111)
prbs_seeded <= 1'b1;
else
prbs_seeded <= 1'b0;
end
//localparam TAPS_VALUE = 12'b100000101001;//10'b1001000000; 256
//localparam TAPS_VALUE = 10'b1000000100;//10'b1001000000; 64
//localparam TAPS_VALUE = 9'b100001000;//9'b1001000000; 64
//localparam TAPS_VALUE = 8'b10001110;//10'b1001000000; repeated in 16 cmd writes
assign prbs_shift_value0 = prbs_shift_value[3:0];
assign prbs_shift_value1 = prbs_shift_value[7:4];
assign prbs_shift_value2 = prbs_shift_value[11:8];
assign prbs_shift_value3 = prbs_shift_value[15:12];
assign prbs_shift_value4 = prbs_shift_value[19:16];
assign prbs_shift_value5 = prbs_shift_value[23:20];
assign prbs_shift_value6 = prbs_shift_value[27:24];
assign prbs_shift_value7 = prbs_shift_value[31:28];
assign prbs_shift_value8 = prbs_shift_value[35:32];
assign prbs_shift_value9 = prbs_shift_value[39:36];
assign prbs_shift_value10 = prbs_shift_value[43:40];
assign prbs_shift_value11 = prbs_shift_value[47:44];
assign prbs_shift_value12 = prbs_shift_value[51:48];
assign prbs_shift_value13 = prbs_shift_value[55:52];
assign prbs_shift_value14 = prbs_shift_value[59:56];
assign prbs_shift_value15 = prbs_shift_value[63:60];
generate
if (nCK_PER_CLK == 4 ) begin
assign prbs_shift_value16 = prbs_shift_value[67:64];
assign prbs_shift_value17 = prbs_shift_value[71:68];
assign prbs_shift_value18 = prbs_shift_value[75:72];
assign prbs_shift_value19 = prbs_shift_value[79:76];
assign prbs_shift_value20 = prbs_shift_value[83:80];
assign prbs_shift_value21 = prbs_shift_value[87:84];
assign prbs_shift_value22 = prbs_shift_value[91:88];
assign prbs_shift_value23 = prbs_shift_value[95:92];
assign prbs_shift_value24 = prbs_shift_value[99:96];
assign prbs_shift_value25 = prbs_shift_value[103:100];
assign prbs_shift_value26 = prbs_shift_value[107:104];
assign prbs_shift_value27 = prbs_shift_value[111:108];
assign prbs_shift_value28 = prbs_shift_value[115:112];
assign prbs_shift_value29 = prbs_shift_value[119:116];
assign prbs_shift_value30 = prbs_shift_value[123:120];
assign prbs_shift_value31 = prbs_shift_value[127:124];
end
endgenerate
genvar l;
generate
for (l = 0; l < nCK_PER_CLK*8; l = l + 1) begin: prbs_modules
tg_prbs_gen #
(
.PRBS_WIDTH (PRBS_WIDTH),
.START_ADDR (START_ADDR),
.PRBS_OFFSET (l*4),
.TAPS (TAPS_VALUE)
)
u_data_prbs_gen
(
.clk_i (clk_i),
.rst (rst_i),
.clk_en (data_clk_en),
// .prbs_seed_init (prbs_seed_init),
.prbs_seed_i (prbs_seed[PRBS_WIDTH-1:0]),//(m_addr_i[31:0]),
.initialize_done (),
.prbs_shift_value (prbs_shift_value[(l+1)*4-1:(l)*4]),
// ADDED, richc 020810: declare ports to avoid warnings
.prbs_o (),
.ReSeedcounter_o (ReSeedcounter[(l+1)*32-1:(l)*32])
);
end endgenerate
// need a mux circuit to mux out prbs_ox to full_prbs bus.
always @ (posedge clk_i)
begin
if (rst_i)
prbs_mux_counter <= 'b0;
else if (data_clk_en )
prbs_mux_counter <= prbs_mux_counter + 1'b1;
end
always @ (posedge clk_i)
begin
if (rst_i)
mode_has_loaded <= 1'b0;
else if ( mode_load_r2 )
mode_has_loaded <= 1'b1;
end
// assert force_load whenever prbs generator has cycle through.
always @ (posedge clk_i)
begin
data_clk_en2_r <= data_clk_en2;
if (ReSeedcounter[31:0] == 0 && data_clk_en2_r && ~data_clk_en2)
force_load <= 1'b1;
else
force_load <= 1'b0;
end
always @ (posedge clk_i)
begin
if (rst_i)
prbs_comb_data_load <= 1'b0;
else if (prbs_mux_counter == 63 //&& DMODE == "WRITE" ||
)
prbs_comb_data_load <= 1'b1;
else if (data_clk_en2)
prbs_comb_data_load <= 1'b0;
end
// 16 PRBS generators are running in parallel. Each one is four cycles earlier to its next one.
//
always @ (posedge clk_i) begin
//if ((mode_load_i & ~mode_has_loaded )|| (prbs_comb_data_load && data_clk_en2))
if ((mode_load_i & ~mode_has_loaded )|| (prbs_comb_data_load && data_clk_en2 && ReSeedcounter[5:0] == 0) || force_load)
prbs_comb_data <= {
prbs_shift_value31,prbs_shift_value30,prbs_shift_value29,prbs_shift_value28,
prbs_shift_value27,prbs_shift_value26,prbs_shift_value25,prbs_shift_value24,
prbs_shift_value23 ,prbs_shift_value22,prbs_shift_value21,prbs_shift_value20,
prbs_shift_value19 ,prbs_shift_value18,prbs_shift_value17,prbs_shift_value16,
prbs_shift_value15,prbs_shift_value14,prbs_shift_value13,prbs_shift_value12,
prbs_shift_value11,prbs_shift_value10,prbs_shift_value9,prbs_shift_value8,
prbs_shift_value7 ,prbs_shift_value6,prbs_shift_value5,prbs_shift_value4,
prbs_shift_value3 ,prbs_shift_value2,prbs_shift_value1,prbs_shift_value0
};
end
always @ (posedge clk_i) begin
mode_load_r1 <= mode_load_i;
mode_load_r2 <= mode_load_r1;
end
always @ (posedge clk_i) begin
if ((mode_load_r1 && ~mode_has_loaded) || (ReSeedcounter[31:0] == 0 && ~data_clk_en2 && nCK_PER_CLK == 4) ||
(ReSeedcounter[31:0] == 0 && nCK_PER_CLK == 2 && data_clk_en2))
// needed to preload the previous value in READ mode.
if (nCK_PER_CLK == 4)
prbs_mux_data <= #TCQ {prbs_shift_value1,prbs_shift_value0};
else
prbs_mux_data <= #TCQ {prbs_shift_value0};
else if (data_clk_en2 ) begin
case (prbs_mux_counter[3:0])
// 8
0 : if (ReSeedcounter[31:0] == 0)
prbs_mux_data <= #TCQ {prbs_shift_value0};
else
prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*1 - 1:nCK_PER_CLK*2*0];
1 : prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*2 - 1:nCK_PER_CLK*2*1 ];
2 : prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*3 - 1:nCK_PER_CLK*2*2 ];//[23:16];
3 : prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*4 - 1:nCK_PER_CLK*2*3 ];//[31:24];
4 : prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*5 - 1:nCK_PER_CLK*2*4 ];//[39:32];
5 : prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*6 - 1:nCK_PER_CLK*2*5 ];//[47:40];
6 : prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*7 - 1:nCK_PER_CLK*2*6 ];//[55:48];
7 : prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*8 - 1:nCK_PER_CLK*2*7 ];//[63:56];
8 : prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*9 - 1:nCK_PER_CLK*2*8 ];//[71:64];
9 : prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*10 - 1:nCK_PER_CLK*2*9 ];//[79:72];
10: prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*11 - 1:nCK_PER_CLK*2*10];//[87:80];
11: prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*12 - 1:nCK_PER_CLK*2*11];//[95:88];
12: prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*13 - 1:nCK_PER_CLK*2*12];//[103:96];
13: prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*14 - 1:nCK_PER_CLK*2*13];//[111:104];
14: prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*15 - 1:nCK_PER_CLK*2*14];//[119:112];
15: prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2*16 - 1:nCK_PER_CLK*2*15];//[127:120];
default: prbs_mux_data <= #TCQ prbs_comb_data[nCK_PER_CLK*2 - 1:nCK_PER_CLK*2*0 ];//[7:0];
endcase
end
end
assign prbsdata_rising_0 = {NUM_DQ_PINS{prbs_mux_data[3]}};
assign prbsdata_falling_0 = {NUM_DQ_PINS{prbs_mux_data[2]}};
assign prbsdata_rising_1 = {NUM_DQ_PINS{prbs_mux_data[1]}};
assign prbsdata_falling_1 = {NUM_DQ_PINS{prbs_mux_data[0]}};
assign prbsdata_rising_2 = {NUM_DQ_PINS{prbs_mux_data[7]}};
assign prbsdata_falling_2 = {NUM_DQ_PINS{prbs_mux_data[6]}};
assign prbsdata_rising_3 = {NUM_DQ_PINS{prbs_mux_data[5]}};
assign prbsdata_falling_3 = {NUM_DQ_PINS{prbs_mux_data[4]}};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DLATCH_P_BLACKBOX_V
`define SKY130_FD_SC_LP__UDP_DLATCH_P_BLACKBOX_V
/**
* udp_dlatch$P: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__udp_dlatch$P (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DLATCH_P_BLACKBOX_V
|
/*
* This file was generated by the scsynth tool, and is availablefor use under
* the MIT license. More information can be found at
* https://github.com/arminalaghi/scsynth/
*/
module ReSC_test_paper_example(); //a testbench for an ReSC module
reg [9:0] x_bin; //binary value of input
reg start;
wire done;
wire [9:0] z_bin; //binary value of output
reg [9:0] expected_z; //expected output
reg clk;
reg reset;
ReSC_wrapper_paper_example ReSC (
.x_bin (x_bin),
.start (start),
.done (done),
.z_bin (z_bin),
.clk (clk),
.reset (reset)
);
always begin
#1 clk <= ~clk;
end
initial begin
clk = 0;
reset = 1;
#1 reset = 0;
start = 1;
#2 x_bin = 10'd510;
expected_z = 10'd512;
start = 0;
#2054 x_bin = 10'd84;
expected_z = 10'd339;
start = 0;
#2054 x_bin = 10'd858;
expected_z = 10'd626;
start = 0;
#2054 x_bin = 10'd1;
expected_z = 10'd257;
start = 0;
#2054 x_bin = 10'd632;
expected_z = 10'd537;
start = 0;
#2054 x_bin = 10'd623;
expected_z = 10'd534;
start = 0;
#2054 x_bin = 10'd1018;
expected_z = 10'd761;
start = 0;
#2054 x_bin = 10'd675;
expected_z = 10'd548;
start = 0;
#2054 x_bin = 10'd450;
expected_z = 10'd500;
start = 0;
#2054 x_bin = 10'd426;
expected_z = 10'd495;
start = 0;
#2054 x_bin = 10'd644;
expected_z = 10'd539;
start = 0;
#2068 $stop;
end
always @(posedge done) begin
$display("x: %b, z: %b, expected_z: %b", x_bin, z_bin, expected_z);
start = 1;
end
endmodule
|
//
module SGMII_PORT(
clk,
ammc_clk,
reset,
//rx_clk,
sgmii_clk,
out_pkt_wrreq,
out_pkt,
out_valid_wrreq,
out_valid,
out_pkt_almostfull,
out2_pkt_wrreq,
out2_pkt,
//out2_pkt_usedw,
out2_pkt_almost_full,
out2_valid_wrreq,
out2_valid,
pkt_receive_add,
pkt_discard_add,
pkt_send_add,
ref_clk,
txp,
rxp,
address,
write,
read,
writedata,
readdata,
waitrequest,
reconfig_clk//37.5Mhz ----50Mhz
);
input clk;
input ammc_clk;
input sgmii_clk;
//output rx_clk;
input reset;
input out2_pkt_wrreq;//output to port2;
input [133:0] out2_pkt;
output out2_pkt_almost_full;
input out2_valid_wrreq;
input out2_valid;
output out_pkt_wrreq;
output [133:0] out_pkt;
input out_pkt_almostfull;
output out_valid_wrreq;
output out_valid;
output pkt_receive_add;
output pkt_discard_add;
output pkt_send_add;
input ref_clk;
output txp;
input rxp;
input [7:0] address;
input write;
input read;
input [31:0] writedata;
output [31:0] readdata;
output waitrequest;
input reconfig_clk;//37.5Mhz ----50Mhz
wire [7:0] acc_address;
wire acc_write;
wire acc_read;
wire [31:0] acc_writedata;
wire [31:0] acc_readdata;
wire acc_waitrequest;
SGMII_TX SGMII_TX(
.clk (clk),
.reset (reset),
.ff_tx_clk (sgmii_clk),
.ff_tx_data (ff_tx_data),
.ff_tx_mod (ff_tx_mod),
.ff_tx_sop (ff_tx_sop),
.ff_tx_eop (ff_tx_eop),
.ff_tx_err (ff_tx_err),
.ff_tx_wren (ff_tx_wren),
.ff_tx_crc_fwd (ff_tx_crc_fwd),
.tx_ff_uflow (tx_ff_uflow),
.ff_tx_rdy (ff_tx_rdy),
.ff_tx_septy (ff_tx_septy),
.ff_tx_a_full (ff_tx_a_full),
.ff_tx_a_empty (ff_tx_a_empty),
.pkt_send_add (pkt_send_add),
.data_in_wrreq (out2_pkt_wrreq),
.data_in (out2_pkt),
.data_in_almostfull (out2_pkt_almost_full),
.data_in_valid_wrreq (out2_valid_wrreq),
.data_in_valid (out2_valid) );
SGMII_RX SGMII_RX(
.reset (reset),
.ff_rx_clk (sgmii_clk),
.ff_rx_rdy (ff_rx_rdy),
.ff_rx_data (ff_rx_data),
.ff_rx_mod (ff_rx_mod),
.ff_rx_sop (ff_rx_sop),
.ff_rx_eop (ff_rx_eop),
.rx_err (rx_err),
.rx_err_stat (rx_err_stat),
.rx_frm_type (rx_frm_type),
.ff_rx_dsav (ff_rx_dsav),
.ff_rx_dval (ff_rx_dval),
.ff_rx_a_full (ff_rx_a_full),
.ff_rx_a_empty (ff_rx_a_empty),
.pkt_receive_add (pkt_receive_add),
.pkt_discard_add (pkt_discard_add),
.out_pkt_wrreq (out_pkt_wrreq),
.out_pkt (out_pkt),
.out_pkt_almostfull (out_pkt_almostfull),
.out_valid_wrreq (out_valid_wrreq),
.out_valid (out_valid)
);
wire ff_tx_clk;
wire [31:0] ff_tx_data;
wire [1:0] ff_tx_mod;
wire ff_tx_sop;
wire ff_tx_eop;
wire ff_tx_err;
wire ff_tx_wren;
wire ff_tx_crc_fwd;
wire tx_ff_uflow;
wire ff_tx_rdy;
wire ff_tx_septy;
wire ff_tx_a_full;
wire ff_tx_a_empty;
wire reset;
wire ff_rx_clk;
wire ff_rx_rdy;
wire [31:0] ff_rx_data;
wire [1:0] ff_rx_mod;
wire ff_rx_sop;
wire ff_rx_eop;
wire [5:0] rx_err;
wire [17:0] rx_err_stat;
wire [3:0] rx_frm_type;
wire ff_rx_dsav;
wire ff_rx_dval;
wire ff_rx_a_full;
wire ff_rx_a_empty;
mac_sgmii mac_sgmii(
//MAC Transmit Interface Signals
.ff_tx_clk (sgmii_clk),
.ff_tx_data (ff_tx_data),
.ff_tx_mod (ff_tx_mod),
.ff_tx_sop (ff_tx_sop),
.ff_tx_eop (ff_tx_eop),
.ff_tx_err (ff_tx_err),
.ff_tx_wren (ff_tx_wren),
.ff_tx_crc_fwd (ff_tx_crc_fwd),
.tx_ff_uflow (tx_ff_uflow),
.ff_tx_rdy (ff_tx_rdy),
.ff_tx_septy (ff_tx_septy),
.ff_tx_a_full (ff_tx_a_full),
.ff_tx_a_empty (ff_tx_a_empty),
//MAC Receive Interface Signals
.ff_rx_clk (sgmii_clk),
.ff_rx_rdy (ff_rx_rdy),
.ff_rx_data (ff_rx_data),
.ff_rx_mod (ff_rx_mod),
.ff_rx_sop (ff_rx_sop),
.ff_rx_eop (ff_rx_eop),
.rx_err (rx_err),
.rx_err_stat (rx_err_stat),
.rx_frm_type (rx_frm_type),
.ff_rx_dsav (ff_rx_dsav),
.ff_rx_dval (ff_rx_dval),
.ff_rx_a_full (ff_rx_a_full),
.ff_rx_a_empty (ff_rx_a_empty),
//MAC Contro
.clk (ammc_clk),
// .address (address),
// .write (write),
// .read (read),
// .writedata (writedata),
// .readdata (readdata),
// .waitrequest (waitrequest),
.reg_addr (address),
.reg_wr (write),
.reg_rd (read),
.reg_data_in (writedata),
.reg_data_out (readdata),
.reg_busy (waitrequest),
// .reg_addr (acc_address),
// .reg_wr (acc_write),
// .reg_rd (acc_read),
// .reg_data_in (acc_writedata),
// .reg_data_out (acc_readdata),
// .reg_busy (acc_waitrequest),
//reset sgmii
.reset (~reset),
.rxp (rxp),
.txp (txp),
.ref_clk (ref_clk),
//LED
.led_an (),
.led_char_err (),
.led_link (),
.led_disp_err (),
.led_crs (),
.led_col (),
//SERDES Control Signals
.rx_recovclkout (),
//.gxb_cal_blk_clk (ref_clk),
.pcs_pwrdn_out (),
// .gxb_pwrdn_in (1'b0),
//.gxb_pwrdn_in (~reset),//ZQ0830
// .reconfig_clk (reconfig_clk),
.reconfig_togxb (4'b010),
.reconfig_fromgxb ()
// .reconfig_busy (1'b0)
);
//MAC_REG_ACC MAC_REG_ACC(
//.clk (ammc_clk),
//.reset (reset),
//.waitrequest (waitrequest),
//.readdata (readdata),
//
//.address (address),
//.write (write),
//.read (read),
//.writedata (writedata) );
/*MAC_REG_ACC MAC_REG_ACC(
.clk (ammc_clk),
.reset (reset),
.waitrequest (acc_waitrequest),
.readdata (acc_readdata),
.address (acc_address),
.write (acc_write),
.read (acc_read),
.writedata (acc_writedata) );*/
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3_SYMBOL_V
`define SKY130_FD_SC_LP__NAND3_SYMBOL_V
/**
* nand3: 3-input NAND.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nand3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3_SYMBOL_V
|
`timescale 1ns / 1ps
/***********************************************************************************************************************
* *
* ANTIKERNEL v0.1 *
* *
* Copyright (c) 2012-2017 Andrew D. Zonenberg *
* All rights reserved. *
* *
* Redistribution and use in source and binary forms, with or without modification, are permitted provided that the *
* following conditions are met: *
* *
* * Redistributions of source code must retain the above copyright notice, this list of conditions, and the *
* following disclaimer. *
* *
* * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the *
* following disclaimer in the documentation and/or other materials provided with the distribution. *
* *
* * Neither the name of the author nor the names of any contributors may be used to endorse or promote products *
* derived from this software without specific prior written permission. *
* *
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED *
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL *
* THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES *
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR *
* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
* POSSIBILITY OF SUCH DAMAGE. *
* *
***********************************************************************************************************************/
/**
@file
@author Andrew D. Zonenberg
@brief A parameterizable width / depth (addressable up to 32 bits for now) shift register.
dout_concat is a concatenated copy of the shift register elements for use in formal verification only.
Do not use it for synthesis.
dout_concat is LEFT aligned!
MSB is most recent word pushed
*/
module ShiftRegisterMacro #(
parameter WIDTH = 16,
parameter DEPTH = 32,
parameter ADDR_BITS = 5
) (
input wire clk,
input wire[ADDR_BITS-1 : 0] addr,
input wire[WIDTH-1 : 0] din,
input wire ce,
output wire[WIDTH-1 : 0] dout
`ifdef FORMAL
, output reg[WIDTH*DEPTH - 1 : 0] dout_concat
`endif
);
////////////////////////////////////////////////////////////////////////////////////////////////
// Sanity checking
generate
initial begin
if(DEPTH > 32) begin
$display("ERROR - ShiftRegisterMacro only supports depth values less than 32 for now");
$finish;
end
end
endgenerate
////////////////////////////////////////////////////////////////////////////////////////////////
// The RAM itself
`ifndef FORMAL
genvar i;
generate
for(i=0; i<WIDTH; i = i+1) begin: shregblock
ShiftRegisterPrimitiveWrapper #(.DEPTH(32), .ADDR_BITS(ADDR_BITS)) shregbit (
.clk(clk),
.addr(addr),
.din(din[i]),
.ce(ce),
.dout(dout[i])
);
end
endgenerate
`else
//More easily constrainable behavioral simulation model
//We can easily constrain this with a .smtc file to match an inferred RAM, MemoryMacro, etc
integer i;
reg[WIDTH-1 : 0] storage[DEPTH-1 : 0];
assign dout = storage[addr];
initial begin
for(i=0; i<DEPTH; i=i+1)
storage[i] <= 0;
end
always @(posedge clk) begin
if(ce) begin
for(i=DEPTH-1; i>=1; i=i-1)
storage[i] <= storage[i-1];
storage[0] <= din;
end
end
`endif
////////////////////////////////////////////////////////////////////////////////////////////////
// Dedicated output for formal verification only
`ifdef FORMAL
always @(*) begin
for(i=0; i<DEPTH; i=i+1)
dout_concat[i*WIDTH +: WIDTH] <= storage[DEPTH - i - 1];
end
`endif
endmodule
/**
@brief Dumb wrapper around a single SRL* to use vector addresses.
Parameterizable depth.
*/
module ShiftRegisterPrimitiveWrapper #(
parameter DEPTH = 32,
parameter ADDR_BITS = 5
) (
input wire clk,
input wire[ADDR_BITS-1 : 0] addr,
input wire din,
input wire ce,
output wire dout);
generate
if(DEPTH == 32) begin
//instantiate the Xilinx primitive
`ifndef FORMAL
SRLC32E #(
.INIT(32'h00000000)
) shreg (
.Q(dout),
.Q31(), //cascade output not used yet
.A(addr),
.CE(ce),
.CLK(clk),
.D(din)
);
//simple behavioral model
`else
reg[31:0] data = 0;
assign dout = data[addr];
always @(posedge clk) begin
if(ce)
data <= {data[30:0], din};
end
`endif
end
else begin
initial begin
$display("Invalid depth");
$finish;
end
end
endgenerate
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The IFU to implement entire instruction fetch unit.
//
// ====================================================================
`include "e203_defines.v"
module e203_ifu(
output[`E203_PC_SIZE-1:0] inspect_pc,
output ifu_active,
input itcm_nohold,
input [`E203_PC_SIZE-1:0] pc_rtvec,
`ifdef E203_HAS_ITCM //{
input ifu2itcm_holdup,
//input ifu2itcm_replay,
// The ITCM address region indication signal
input [`E203_ADDR_SIZE-1:0] itcm_region_indic,
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// Bus Interface to ITCM, internal protocol called ICB (Internal Chip Bus)
// * Bus cmd channel
output ifu2itcm_icb_cmd_valid, // Handshake valid
input ifu2itcm_icb_cmd_ready, // Handshake ready
// Note: The data on rdata or wdata channel must be naturally
// aligned, this is in line with the AXI definition
output [`E203_ITCM_ADDR_WIDTH-1:0] ifu2itcm_icb_cmd_addr, // Bus transaction start addr
// * Bus RSP channel
input ifu2itcm_icb_rsp_valid, // Response valid
output ifu2itcm_icb_rsp_ready, // Response ready
input ifu2itcm_icb_rsp_err, // Response error
// Note: the RSP rdata is inline with AXI definition
input [`E203_ITCM_DATA_WIDTH-1:0] ifu2itcm_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_MEM_ITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// Bus Interface to System Memory, internal protocol called ICB (Internal Chip Bus)
// * Bus cmd channel
output ifu2biu_icb_cmd_valid, // Handshake valid
input ifu2biu_icb_cmd_ready, // Handshake ready
// Note: The data on rdata or wdata channel must be naturally
// aligned, this is in line with the AXI definition
output [`E203_ADDR_SIZE-1:0] ifu2biu_icb_cmd_addr, // Bus transaction start addr
// * Bus RSP channel
input ifu2biu_icb_rsp_valid, // Response valid
output ifu2biu_icb_rsp_ready, // Response ready
input ifu2biu_icb_rsp_err, // Response error
// Note: the RSP rdata is inline with AXI definition
input [`E203_SYSMEM_DATA_WIDTH-1:0] ifu2biu_icb_rsp_rdata,
//input ifu2biu_replay,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The IR stage to EXU interface
output [`E203_INSTR_SIZE-1:0] ifu_o_ir,// The instruction register
output [`E203_PC_SIZE-1:0] ifu_o_pc, // The PC register along with
output ifu_o_pc_vld,
output ifu_o_misalgn, // The fetch misalign
output ifu_o_buserr, // The fetch bus error
output [`E203_RFIDX_WIDTH-1:0] ifu_o_rs1idx,
output [`E203_RFIDX_WIDTH-1:0] ifu_o_rs2idx,
output ifu_o_prdt_taken, // The Bxx is predicted as taken
output ifu_o_muldiv_b2b,
output ifu_o_valid, // Handshake signals with EXU stage
input ifu_o_ready,
output pipe_flush_ack,
input pipe_flush_req,
input [`E203_PC_SIZE-1:0] pipe_flush_add_op1,
input [`E203_PC_SIZE-1:0] pipe_flush_add_op2,
`ifdef E203_TIMING_BOOST//}
input [`E203_PC_SIZE-1:0] pipe_flush_pc,
`endif//}
// The halt request come from other commit stage
// If the ifu_halt_req is asserting, then IFU will stop fetching new
// instructions and after the oustanding transactions are completed,
// asserting the ifu_halt_ack as the response.
// The IFU will resume fetching only after the ifu_halt_req is deasserted
input ifu_halt_req,
output ifu_halt_ack,
input oitf_empty,
input [`E203_XLEN-1:0] rf2ifu_x1,
input [`E203_XLEN-1:0] rf2ifu_rs1,
input dec2ifu_rden,
input dec2ifu_rs1en,
input [`E203_RFIDX_WIDTH-1:0] dec2ifu_rdidx,
input dec2ifu_mulhsu,
input dec2ifu_div ,
input dec2ifu_rem ,
input dec2ifu_divu ,
input dec2ifu_remu ,
input clk,
input rst_n
);
wire ifu_req_valid;
wire ifu_req_ready;
wire [`E203_PC_SIZE-1:0] ifu_req_pc;
wire ifu_req_seq;
wire ifu_req_seq_rv32;
wire [`E203_PC_SIZE-1:0] ifu_req_last_pc;
wire ifu_rsp_valid;
wire ifu_rsp_ready;
wire ifu_rsp_err;
//wire ifu_rsp_replay;
wire [`E203_INSTR_SIZE-1:0] ifu_rsp_instr;
e203_ifu_ifetch u_e203_ifu_ifetch(
.inspect_pc (inspect_pc),
.pc_rtvec (pc_rtvec),
.ifu_req_valid (ifu_req_valid),
.ifu_req_ready (ifu_req_ready),
.ifu_req_pc (ifu_req_pc ),
.ifu_req_seq (ifu_req_seq ),
.ifu_req_seq_rv32(ifu_req_seq_rv32),
.ifu_req_last_pc (ifu_req_last_pc ),
.ifu_rsp_valid (ifu_rsp_valid),
.ifu_rsp_ready (ifu_rsp_ready),
.ifu_rsp_err (ifu_rsp_err ),
//.ifu_rsp_replay(ifu_rsp_replay),
.ifu_rsp_instr (ifu_rsp_instr),
.ifu_o_ir (ifu_o_ir ),
.ifu_o_pc (ifu_o_pc ),
.ifu_o_pc_vld (ifu_o_pc_vld ),
.ifu_o_misalgn (ifu_o_misalgn),
.ifu_o_buserr (ifu_o_buserr ),
.ifu_o_rs1idx (ifu_o_rs1idx),
.ifu_o_rs2idx (ifu_o_rs2idx),
.ifu_o_prdt_taken(ifu_o_prdt_taken),
.ifu_o_muldiv_b2b(ifu_o_muldiv_b2b),
.ifu_o_valid (ifu_o_valid ),
.ifu_o_ready (ifu_o_ready ),
.pipe_flush_ack (pipe_flush_ack ),
.pipe_flush_req (pipe_flush_req ),
.pipe_flush_add_op1 (pipe_flush_add_op1),
`ifdef E203_TIMING_BOOST//}
.pipe_flush_pc (pipe_flush_pc),
`endif//}
.pipe_flush_add_op2 (pipe_flush_add_op2),
.ifu_halt_req (ifu_halt_req ),
.ifu_halt_ack (ifu_halt_ack ),
.oitf_empty (oitf_empty ),
.rf2ifu_x1 (rf2ifu_x1 ),
.rf2ifu_rs1 (rf2ifu_rs1 ),
.dec2ifu_rden (dec2ifu_rden ),
.dec2ifu_rs1en (dec2ifu_rs1en),
.dec2ifu_rdidx (dec2ifu_rdidx),
.dec2ifu_mulhsu(dec2ifu_mulhsu),
.dec2ifu_div (dec2ifu_div ),
.dec2ifu_rem (dec2ifu_rem ),
.dec2ifu_divu (dec2ifu_divu ),
.dec2ifu_remu (dec2ifu_remu ),
.clk (clk ),
.rst_n (rst_n )
);
e203_ifu_ift2icb u_e203_ifu_ift2icb (
.ifu_req_valid (ifu_req_valid),
.ifu_req_ready (ifu_req_ready),
.ifu_req_pc (ifu_req_pc ),
.ifu_req_seq (ifu_req_seq ),
.ifu_req_seq_rv32(ifu_req_seq_rv32),
.ifu_req_last_pc (ifu_req_last_pc ),
.ifu_rsp_valid (ifu_rsp_valid),
.ifu_rsp_ready (ifu_rsp_ready),
.ifu_rsp_err (ifu_rsp_err ),
//.ifu_rsp_replay(ifu_rsp_replay),
.ifu_rsp_instr (ifu_rsp_instr),
.itcm_nohold (itcm_nohold),
`ifdef E203_HAS_ITCM //{
.itcm_region_indic (itcm_region_indic),
.ifu2itcm_icb_cmd_valid(ifu2itcm_icb_cmd_valid),
.ifu2itcm_icb_cmd_ready(ifu2itcm_icb_cmd_ready),
.ifu2itcm_icb_cmd_addr (ifu2itcm_icb_cmd_addr ),
.ifu2itcm_icb_rsp_valid(ifu2itcm_icb_rsp_valid),
.ifu2itcm_icb_rsp_ready(ifu2itcm_icb_rsp_ready),
.ifu2itcm_icb_rsp_err (ifu2itcm_icb_rsp_err ),
.ifu2itcm_icb_rsp_rdata(ifu2itcm_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_MEM_ITF //{
.ifu2biu_icb_cmd_valid(ifu2biu_icb_cmd_valid),
.ifu2biu_icb_cmd_ready(ifu2biu_icb_cmd_ready),
.ifu2biu_icb_cmd_addr (ifu2biu_icb_cmd_addr ),
.ifu2biu_icb_rsp_valid(ifu2biu_icb_rsp_valid),
.ifu2biu_icb_rsp_ready(ifu2biu_icb_rsp_ready),
.ifu2biu_icb_rsp_err (ifu2biu_icb_rsp_err ),
.ifu2biu_icb_rsp_rdata(ifu2biu_icb_rsp_rdata),
//.ifu2biu_replay (ifu2biu_replay),
`endif//}
`ifdef E203_HAS_ITCM //{
.ifu2itcm_holdup (ifu2itcm_holdup),
//.ifu2itcm_replay (ifu2itcm_replay),
`endif//}
.clk (clk ),
.rst_n (rst_n )
);
assign ifu_active = 1'b1;// Seems the IFU never rest at block level
endmodule
|
// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//===----------------------------------------------------------------------===//
//
// C backend 'push' primitive
//
// Upstream are signals that go to the feedback (snk node is a acl_pop),
// downstream are signals that continue into our "normal" pipeline.
//
// dir indicates if you want to push it to the feedback
// 1 - push to feedback
// 0 - bypass, just push out to downstream
//===----------------------------------------------------------------------===//
// altera message_off 10036
module acl_push (
clock,
resetn,
// interface from kernel pipeline, input stream
dir,
data_in,
valid_in,
stall_out,
predicate,
// interface to kernel pipeline, downstream
valid_out,
stall_in,
data_out,
// interface to pipeline feedback, upstream
feedback_out,
feedback_valid_out,
feedback_stall_in
);
parameter DATA_WIDTH = 32;
parameter FIFO_DEPTH = 1;
parameter MIN_FIFO_LATENCY = 0;
// style can be "REGULAR", for a regular push
// or "TOKEN" for a special fifo that hands out tokens
parameter string STYLE = "REGULAR"; // "REGULAR"/"TOKEN"
parameter STALLFREE = 0;
parameter ENABLED = 0;
input clock, resetn, stall_in, valid_in, feedback_stall_in;
output stall_out, valid_out, feedback_valid_out;
input [DATA_WIDTH-1:0] data_in;
input dir;
input predicate;
output [DATA_WIDTH-1:0] data_out, feedback_out;
wire [DATA_WIDTH-1:0] feedback;
wire data_downstream, data_upstream;
wire push_upstream;
assign push_upstream = dir & ~predicate;
assign data_upstream = valid_in & push_upstream;
assign data_downstream = valid_in;
wire feedback_stall, feedback_valid;
reg consumed_downstream, consumed_upstream;
assign valid_out = data_downstream & !consumed_downstream;
assign feedback_valid = data_upstream & !consumed_upstream & (ENABLED ? ~stall_in : 1'b1);
assign data_out = data_in;
assign feedback = data_in;
//assign stall_out = valid_in & ( ~(data_downstream & ~stall_in) & ~(data_upstream & ~feedback_stall));
// assign stall_out = valid_in & ( ~(data_downstream & ~stall_in) | ~(data_upstream & ~feedback_stall));
assign stall_out = stall_in | (feedback_stall & push_upstream );
generate
if (ENABLED) begin
always @(posedge clock or negedge resetn) begin
if (!resetn) begin
consumed_downstream <= 1'b0;
consumed_upstream <= 1'b0;
end else begin
if (~stall_in) begin
if (consumed_downstream)
consumed_downstream <= stall_out;
else
consumed_downstream <= stall_out & data_downstream;
consumed_upstream <= 1'b0;
end
end
end
end else begin
always @(posedge clock or negedge resetn) begin
if (!resetn) begin
consumed_downstream <= 1'b0;
consumed_upstream <= 1'b0;
end else begin
if (consumed_downstream)
consumed_downstream <= stall_out;
else
consumed_downstream <= stall_out & (data_downstream & ~stall_in);
if (consumed_upstream)
consumed_upstream <= stall_out;
else
consumed_upstream <= stall_out & (data_upstream & ~feedback_stall);
end
end
end
endgenerate
localparam TYPE = MIN_FIFO_LATENCY < 1 ? (FIFO_DEPTH < 8 ? "zl_reg" : "zl_ram") : (MIN_FIFO_LATENCY < 3 ? (FIFO_DEPTH < 8 ? "ll_reg" : "ll_ram") : (FIFO_DEPTH < 8 ? "ll_reg" : "ram"));
generate
if ( STYLE == "TOKEN" )
begin
acl_token_fifo_counter
#(
.DEPTH(FIFO_DEPTH)
)
fifo (
.clock(clock),
.resetn(resetn),
.data_out(feedback_out),
.valid_in(feedback_valid),
.valid_out(feedback_valid_out),
.stall_in(feedback_stall_in),
.stall_out(feedback_stall)
);
end
else if (FIFO_DEPTH == 0) begin
// if no FIFO depth is requested, just connect
// feedback directly to output
assign feedback_out = feedback;
assign feedback_valid_out = feedback_valid;
assign feedback_stall = feedback_stall_in;
end
else if (FIFO_DEPTH == 1 && MIN_FIFO_LATENCY == 0) begin
// simply add a staging register if the requested depth is 1
// and the latency must be 0
acl_staging_reg #(
.WIDTH(DATA_WIDTH)
) staging_reg (
.clk(clock),
.reset(~resetn),
.i_data(feedback),
.i_valid(feedback_valid),
.o_stall(feedback_stall),
.o_data(feedback_out),
.o_valid(feedback_valid_out),
.i_stall(feedback_stall_in)
);
end
else
begin
// only allow full write in stall free clusters if you're an ll_reg
// otherwise, comb cycles can form, since stall_out depends on
// stall_in the acl_data_fifo. To make up for the last space, we
// add a capacity of 1 to the FIFO
localparam OFFSET = ( (TYPE == "ll_reg") && !STALLFREE ) ? 1 : 0;
localparam ALLOW_FULL_WRITE = ( (TYPE == "ll_reg") && !STALLFREE ) ? 0 : 1;
acl_data_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.DEPTH(((TYPE == "ram") || (TYPE == "ll_ram") || (TYPE == "zl_ram")) ? FIFO_DEPTH + 1 : FIFO_DEPTH + OFFSET),
.IMPL(TYPE),
.ALLOW_FULL_WRITE(ALLOW_FULL_WRITE)
)
fifo (
.clock(clock),
.resetn(resetn),
.data_in(feedback),
.data_out(feedback_out),
.valid_in(feedback_valid),
.valid_out(feedback_valid_out),
.stall_in(feedback_stall_in),
.stall_out(feedback_stall)
);
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A221OI_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__A221OI_PP_BLACKBOX_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__a221oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A221OI_PP_BLACKBOX_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// including negligence, or under any other theory of
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//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pcie_top.v
// Version : 3.0
//----------------------------------------------------------------------------//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express //
// Filename : pcie3_7x_0_pcie_top.v //
// Description : Instantiates GEN3 PCIe Integrated Block Wrapper and //
// connects the IP to the PIPE Interface Pipeline module, the //
// PCIe Initialization Controller, and the TPH Table //
// implemented in a RAMB36 //
//---------- PIPE Wrapper Hierarchy ------------------------------------------//
// pcie_top.v //
// pcie_init_ctrl.v //
// pcie_tlp_tph_tbl_7vx.v //
// pcie_7vx.v //
// PCIE_3_0 //
// pcie_bram_7vx.v //
// pcie_bram_7vx_rep.v //
// pcie_bram_7vx_rep_8k.v //
// pcie_bram_7vx_req.v //
// pcie_bram_7vx_8k.v //
// pcie_bram_7vx_cpl.v //
// pcie_bram_7vx_8k.v //
// pcie_bram_7vx_16k.v //
// pcie_pipe_pipeline.v //
// pcie_pipe_lane.v //
// pcie_pipe_misc.v //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie3_7x_0_pcie_top #(
parameter TCQ = 100,
parameter PIPE_SIM_MODE = "FALSE",
parameter PIPE_PIPELINE_STAGES = 0,
parameter ARI_CAP_ENABLE = "FALSE",
parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE",
parameter AXISTEN_IF_CC_PARITY_CHK = "TRUE",
parameter AXISTEN_IF_CQ_ALIGNMENT_MODE = "FALSE",
parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE",
parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000,
parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE",
parameter AXISTEN_IF_RC_ALIGNMENT_MODE = "FALSE",
parameter AXISTEN_IF_RC_STRADDLE = "FALSE",
parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "FALSE",
parameter AXISTEN_IF_RQ_PARITY_CHK = "TRUE",
parameter [1:0] AXISTEN_IF_WIDTH = 2'h2,
parameter C_DATA_WIDTH = 256,
parameter CRM_CORE_CLK_FREQ_500 = "TRUE",
parameter [1:0] CRM_USER_CLK_FREQ = 2'h2,
parameter [7:0] DNSTREAM_LINK_NUM = 8'h00,
parameter [1:0] GEN3_PCS_AUTO_REALIGN = 2'h1,
parameter GEN3_PCS_RX_ELECIDLE_INTERNAL = "TRUE",
parameter KEEP_WIDTH = C_DATA_WIDTH / 32,
parameter [8:0] LL_ACK_TIMEOUT = 9'h000,
parameter LL_ACK_TIMEOUT_EN = "FALSE",
parameter integer LL_ACK_TIMEOUT_FUNC = 0,
parameter [15:0] LL_CPL_FC_UPDATE_TIMER = 16'h0000,
parameter LL_CPL_FC_UPDATE_TIMER_OVERRIDE = "FALSE",
parameter [15:0] LL_FC_UPDATE_TIMER = 16'h0000,
parameter LL_FC_UPDATE_TIMER_OVERRIDE = "FALSE",
parameter [15:0] LL_NP_FC_UPDATE_TIMER = 16'h0000,
parameter LL_NP_FC_UPDATE_TIMER_OVERRIDE = "FALSE",
parameter [15:0] LL_P_FC_UPDATE_TIMER = 16'h0000,
parameter LL_P_FC_UPDATE_TIMER_OVERRIDE = "FALSE",
parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000,
parameter LL_REPLAY_TIMEOUT_EN = "FALSE",
parameter integer LL_REPLAY_TIMEOUT_FUNC = 0,
parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h0FA,
parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE",
parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE",
parameter PF0_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
parameter PF0_AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000,
parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000,
parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00,
parameter [3:0] PF0_ARI_CAP_VER = 4'h1,
parameter [4:0] PF0_BAR0_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_BAR0_CONTROL = 3'h4,
parameter [4:0] PF0_BAR1_APERTURE_SIZE = 5'h00,
parameter [2:0] PF0_BAR1_CONTROL = 3'h0,
parameter [4:0] PF0_BAR2_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_BAR2_CONTROL = 3'h4,
parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_BAR3_CONTROL = 3'h0,
parameter [4:0] PF0_BAR4_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_BAR4_CONTROL = 3'h4,
parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_BAR5_CONTROL = 3'h0,
parameter [7:0] PF0_BIST_REGISTER = 8'h00,
parameter [7:0] PF0_CAPABILITY_POINTER = 8'h50,
parameter [23:0] PF0_CLASS_CODE = 24'h000000,
parameter [15:0] PF0_DEVICE_ID = 16'h0000,
parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE",
parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE",
parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE",
parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE",
parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE",
parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0,
parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE",
parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0,
parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0,
parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE",
parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE",
parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3,
parameter [11:0] PF0_DPA_CAP_NEXTPTR = 12'h000,
parameter [11:0] VF0_ARI_CAP_NEXTPTR = 12'h000,
parameter [11:0] VF1_ARI_CAP_NEXTPTR = 12'h000,
parameter [11:0] VF2_ARI_CAP_NEXTPTR = 12'h000,
parameter [11:0] VF3_ARI_CAP_NEXTPTR = 12'h000,
parameter [11:0] VF4_ARI_CAP_NEXTPTR = 12'h000,
parameter [11:0] VF5_ARI_CAP_NEXTPTR = 12'h000,
parameter VF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
parameter VF0_TPHR_CAP_ENABLE = "FALSE",
parameter VF0_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] VF0_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] VF0_TPHR_CAP_ST_MODE_SEL = 3'h0,
parameter [1:0] VF0_TPHR_CAP_ST_TABLE_LOC = 2'h0,
parameter [10:0] VF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] VF0_TPHR_CAP_VER = 4'h1,
parameter VF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
parameter VF1_TPHR_CAP_ENABLE = "FALSE",
parameter VF1_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] VF1_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] VF1_TPHR_CAP_ST_MODE_SEL = 3'h0,
parameter [1:0] VF1_TPHR_CAP_ST_TABLE_LOC = 2'h0,
parameter [10:0] VF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] VF1_TPHR_CAP_VER = 4'h1,
parameter VF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
parameter VF2_TPHR_CAP_ENABLE = "FALSE",
parameter VF2_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] VF2_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] VF2_TPHR_CAP_ST_MODE_SEL = 3'h0,
parameter [1:0] VF2_TPHR_CAP_ST_TABLE_LOC = 2'h0,
parameter [10:0] VF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] VF2_TPHR_CAP_VER = 4'h1,
parameter VF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
parameter VF3_TPHR_CAP_ENABLE = "FALSE",
parameter VF3_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] VF3_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] VF3_TPHR_CAP_ST_MODE_SEL = 3'h0,
parameter [1:0] VF3_TPHR_CAP_ST_TABLE_LOC = 2'h0,
parameter [10:0] VF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] VF3_TPHR_CAP_VER = 4'h1,
parameter VF4_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
parameter VF4_TPHR_CAP_ENABLE = "FALSE",
parameter VF4_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] VF4_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] VF4_TPHR_CAP_ST_MODE_SEL = 3'h0,
parameter [1:0] VF4_TPHR_CAP_ST_TABLE_LOC = 2'h0,
parameter [10:0] VF4_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] VF4_TPHR_CAP_VER = 4'h1,
parameter VF5_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
parameter VF5_TPHR_CAP_ENABLE = "FALSE",
parameter VF5_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] VF5_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] VF5_TPHR_CAP_ST_MODE_SEL = 3'h0,
parameter [1:0] VF5_TPHR_CAP_ST_TABLE_LOC = 2'h0,
parameter [10:0] VF5_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] VF5_TPHR_CAP_VER = 4'h1,
parameter [4:0] PF0_DPA_CAP_SUB_STATE_CONTROL = 5'h00,
parameter PF0_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE",
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00,
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00,
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00,
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00,
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00,
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00,
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00,
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00,
parameter [3:0] PF0_DPA_CAP_VER = 4'h1,
parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C,
parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03,
parameter PF0_EXPANSION_ROM_ENABLE = "FALSE",
parameter [7:0] PF0_INTERRUPT_LINE = 8'h00,
parameter [2:0] PF0_INTERRUPT_PIN = 3'h1,
parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0,
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7,
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7,
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7,
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7,
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7,
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7,
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7,
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7,
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7,
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7,
parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE",
parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000,
parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000,
parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000,
parameter [3:0] PF0_LTR_CAP_VER = 4'h1,
parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00,
parameter integer PF0_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer PF0_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00,
parameter [11:0] PF0_PB_CAP_NEXTPTR = 12'h000,
parameter PF0_PB_CAP_SYSTEM_ALLOCATED = "FALSE",
parameter [3:0] PF0_PB_CAP_VER = 4'h1,
parameter [7:0] PF0_PM_CAP_ID = 8'h01,
parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00,
parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE",
parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE",
parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE",
parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE",
parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3,
parameter PF0_PM_CSR_NOSOFTRESET = "TRUE",
parameter PF0_RBAR_CAP_ENABLE = "FALSE",
parameter [2:0] PF0_RBAR_CAP_INDEX0 = 3'h0,
parameter [2:0] PF0_RBAR_CAP_INDEX1 = 3'h0,
parameter [2:0] PF0_RBAR_CAP_INDEX2 = 3'h0,
parameter [11:0] PF0_RBAR_CAP_NEXTPTR = 12'h000,
parameter [19:0] PF0_RBAR_CAP_SIZE0 = 20'h00000,
parameter [19:0] PF0_RBAR_CAP_SIZE1 = 20'h00000,
parameter [19:0] PF0_RBAR_CAP_SIZE2 = 20'h00000,
parameter [3:0] PF0_RBAR_CAP_VER = 4'h1,
parameter [2:0] PF0_RBAR_NUM = 3'h1,
parameter [7:0] PF0_REVISION_ID = 8'h00,
parameter [4:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4,
parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00,
parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0,
parameter [4:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4,
parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0,
parameter [4:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4,
parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03,
parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0,
parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000,
parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000,
parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000,
parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1,
parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000,
parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000,
parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000,
parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000,
parameter [15:0] PF0_SUBSYSTEM_ID = 16'h0000,
parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
parameter PF0_TPHR_CAP_ENABLE = "FALSE",
parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0,
parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0,
parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] PF0_TPHR_CAP_VER = 4'h1,
parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000,
parameter [3:0] PF0_VC_CAP_VER = 4'h1,
parameter PF1_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE",
parameter PF1_AER_CAP_ECRC_GEN_CAPABLE = "FALSE",
parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000,
parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000,
parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00,
parameter [4:0] PF1_BAR0_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_BAR0_CONTROL = 3'h4,
parameter [4:0] PF1_BAR1_APERTURE_SIZE = 5'h00,
parameter [2:0] PF1_BAR1_CONTROL = 3'h0,
parameter [4:0] PF1_BAR2_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_BAR2_CONTROL = 3'h4,
parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_BAR3_CONTROL = 3'h0,
parameter [4:0] PF1_BAR4_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_BAR4_CONTROL = 3'h4,
parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_BAR5_CONTROL = 3'h0,
parameter [7:0] PF1_BIST_REGISTER = 8'h00,
parameter [7:0] PF1_CAPABILITY_POINTER = 8'h50,
parameter [23:0] PF1_CLASS_CODE = 24'h000000,
parameter [15:0] PF1_DEVICE_ID = 16'h0000,
parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3,
parameter [11:0] PF1_DPA_CAP_NEXTPTR = 12'h000,
parameter [4:0] PF1_DPA_CAP_SUB_STATE_CONTROL = 5'h00,
parameter PF1_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE",
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00,
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00,
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00,
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00,
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00,
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00,
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00,
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00,
parameter [3:0] PF1_DPA_CAP_VER = 4'h1,
parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C,
parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03,
parameter PF1_EXPANSION_ROM_ENABLE = "FALSE",
parameter [7:0] PF1_INTERRUPT_LINE = 8'h00,
parameter [2:0] PF1_INTERRUPT_PIN = 3'h1,
parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00,
parameter integer PF1_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer PF1_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00,
parameter [11:0] PF1_PB_CAP_NEXTPTR = 12'h000,
parameter PF1_PB_CAP_SYSTEM_ALLOCATED = "FALSE",
parameter [3:0] PF1_PB_CAP_VER = 4'h1,
parameter [7:0] PF1_PM_CAP_ID = 8'h01,
parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] PF1_PM_CAP_VER_ID = 3'h3,
parameter PF1_RBAR_CAP_ENABLE = "FALSE",
parameter [2:0] PF1_RBAR_CAP_INDEX0 = 3'h0,
parameter [2:0] PF1_RBAR_CAP_INDEX1 = 3'h0,
parameter [2:0] PF1_RBAR_CAP_INDEX2 = 3'h0,
parameter [11:0] PF1_RBAR_CAP_NEXTPTR = 12'h000,
parameter [19:0] PF1_RBAR_CAP_SIZE0 = 20'h00000,
parameter [19:0] PF1_RBAR_CAP_SIZE1 = 20'h00000,
parameter [19:0] PF1_RBAR_CAP_SIZE2 = 20'h00000,
parameter [3:0] PF1_RBAR_CAP_VER = 4'h1,
parameter [2:0] PF1_RBAR_NUM = 3'h1,
parameter [7:0] PF1_REVISION_ID = 8'h00,
parameter [4:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4,
parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00,
parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0,
parameter [4:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4,
parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0,
parameter [4:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4,
parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03,
parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0,
parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000,
parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000,
parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000,
parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1,
parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000,
parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000,
parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000,
parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000,
parameter [15:0] PF1_SUBSYSTEM_ID = 16'h0000,
parameter PF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE",
parameter PF1_TPHR_CAP_ENABLE = "FALSE",
parameter PF1_TPHR_CAP_INT_VEC_MODE = "TRUE",
parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000,
parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0,
parameter [1:0] PF1_TPHR_CAP_ST_TABLE_LOC = 2'h0,
parameter [10:0] PF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000,
parameter [3:0] PF1_TPHR_CAP_VER = 4'h1,
parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE",
parameter PL_DISABLE_GEN3_DC_BALANCE = "FALSE",
parameter PL_DISABLE_SCRAMBLING = "FALSE",
parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE",
parameter PL_EQ_ADAPT_DISABLE_COEFF_CHECK = "FALSE",
parameter PL_EQ_ADAPT_DISABLE_PRESET_CHECK = "FALSE",
parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02,
parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1,
parameter PL_EQ_BYPASS_PHASE23 = "FALSE",
parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE",
parameter [15:0] PL_LANE0_EQ_CONTROL = 16'h3F00,
parameter [15:0] PL_LANE1_EQ_CONTROL = 16'h3F00,
parameter [15:0] PL_LANE2_EQ_CONTROL = 16'h3F00,
parameter [15:0] PL_LANE3_EQ_CONTROL = 16'h3F00,
parameter [15:0] PL_LANE4_EQ_CONTROL = 16'h3F00,
parameter [15:0] PL_LANE5_EQ_CONTROL = 16'h3F00,
parameter [15:0] PL_LANE6_EQ_CONTROL = 16'h3F00,
parameter [15:0] PL_LANE7_EQ_CONTROL = 16'h3F00,
parameter [2:0] PL_LINK_CAP_MAX_LINK_SPEED = 3'h4,
parameter [3:0] PL_LINK_CAP_MAX_LINK_WIDTH = 4'h8,
parameter integer PL_N_FTS_COMCLK_GEN1 = 255,
parameter integer PL_N_FTS_COMCLK_GEN2 = 255,
parameter integer PL_N_FTS_COMCLK_GEN3 = 255,
parameter integer PL_N_FTS_GEN1 = 255,
parameter integer PL_N_FTS_GEN2 = 255,
parameter integer PL_N_FTS_GEN3 = 255,
parameter PL_SIM_FAST_LINK_TRAINING = "FALSE",
parameter PL_UPSTREAM_FACING = "TRUE",
parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h05DC,
parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h00000,
parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE",
parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000000,
parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h186A0,
parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0064,
parameter SIM_VERSION = "1.0",
parameter integer SPARE_BIT0 = 0,
parameter integer SPARE_BIT1 = 0,
parameter integer SPARE_BIT2 = 0,
parameter integer SPARE_BIT3 = 0,
parameter integer SPARE_BIT4 = 0,
parameter integer SPARE_BIT5 = 0,
parameter integer SPARE_BIT6 = 0,
parameter integer SPARE_BIT7 = 0,
parameter integer SPARE_BIT8 = 0,
parameter [7:0] SPARE_BYTE0 = 8'h00,
parameter [7:0] SPARE_BYTE1 = 8'h00,
parameter [7:0] SPARE_BYTE2 = 8'h00,
parameter [7:0] SPARE_BYTE3 = 8'h00,
parameter [31:0] SPARE_WORD0 = 32'h00000000,
parameter [31:0] SPARE_WORD1 = 32'h00000000,
parameter [31:0] SPARE_WORD2 = 32'h00000000,
parameter [31:0] SPARE_WORD3 = 32'h00000000,
parameter SRIOV_CAP_ENABLE = "FALSE",
parameter [23:0] TL_COMPL_TIMEOUT_REG0 = 24'hBEBC20,
parameter [27:0] TL_COMPL_TIMEOUT_REG1 = 28'h0000000,
parameter [11:0] TL_CREDITS_CD = 12'h3E0,
parameter [7:0] TL_CREDITS_CH = 8'h20,
parameter [11:0] TL_CREDITS_NPD = 12'h028,
parameter [7:0] TL_CREDITS_NPH = 8'h20,
parameter [11:0] TL_CREDITS_PD = 12'h198,
parameter [7:0] TL_CREDITS_PH = 8'h20,
parameter TL_ENABLE_MESSAGE_RID_CHECK_ENABLE = "TRUE",
parameter TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE",
parameter TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE",
parameter TL_LEGACY_MODE_ENABLE = "FALSE",
parameter TL_PF_ENABLE_REG = "FALSE",
parameter TL_TAG_MGMT_ENABLE = "TRUE",
parameter [7:0] VF0_CAPABILITY_POINTER = 8'h50,
parameter integer VF0_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] VF0_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer VF0_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] VF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] VF0_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer VF0_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] VF0_PM_CAP_ID = 8'h01,
parameter [7:0] VF0_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] VF0_PM_CAP_VER_ID = 3'h3,
parameter integer VF1_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] VF1_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer VF1_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] VF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] VF1_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer VF1_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] VF1_PM_CAP_ID = 8'h01,
parameter [7:0] VF1_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] VF1_PM_CAP_VER_ID = 3'h3,
parameter integer VF2_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] VF2_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer VF2_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] VF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] VF2_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer VF2_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] VF2_PM_CAP_ID = 8'h01,
parameter [7:0] VF2_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] VF2_PM_CAP_VER_ID = 3'h3,
parameter integer VF3_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] VF3_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer VF3_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] VF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] VF3_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer VF3_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] VF3_PM_CAP_ID = 8'h01,
parameter [7:0] VF3_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] VF3_PM_CAP_VER_ID = 3'h3,
parameter integer VF4_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] VF4_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer VF4_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] VF4_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] VF4_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer VF4_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] VF4_PM_CAP_ID = 8'h01,
parameter [7:0] VF4_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] VF4_PM_CAP_VER_ID = 3'h3,
parameter integer VF5_MSIX_CAP_PBA_BIR = 0,
parameter [28:0] VF5_MSIX_CAP_PBA_OFFSET = 29'h00000050,
parameter integer VF5_MSIX_CAP_TABLE_BIR = 0,
parameter [28:0] VF5_MSIX_CAP_TABLE_OFFSET = 29'h00000040,
parameter [10:0] VF5_MSIX_CAP_TABLE_SIZE = 11'h000,
parameter integer VF5_MSI_CAP_MULTIMSGCAP = 0,
parameter [7:0] VF5_PM_CAP_ID = 8'h01,
parameter [7:0] VF5_PM_CAP_NEXTPTR = 8'h00,
parameter [2:0] VF5_PM_CAP_VER_ID = 3'h3,
parameter IMPL_TARGET = "HARD",
parameter NO_DECODE_LOGIC = "TRUE",
parameter INTERFACE_SPEED = "500 MHZ",
parameter COMPLETION_SPACE = "16KB"
) (
input core_clk,
input rec_clk,
input user_clk,
input pipe_clk,
input phy_rdy, // GT is ready : 1b = GT Ready
input mmcm_lock, // MMCM Locked : 1b = MMCM Locked
input s_axis_rq_tlast,
input [C_DATA_WIDTH-1:0] s_axis_rq_tdata,
input [59:0] s_axis_rq_tuser,
input [KEEP_WIDTH-1:0] s_axis_rq_tkeep,
output [3:0] s_axis_rq_tready,
input s_axis_rq_tvalid,
output [C_DATA_WIDTH-1:0] m_axis_rc_tdata,
output [74:0] m_axis_rc_tuser,
output m_axis_rc_tlast,
output [KEEP_WIDTH-1:0] m_axis_rc_tkeep,
output m_axis_rc_tvalid,
input [21:0] m_axis_rc_tready,
output [C_DATA_WIDTH-1:0] m_axis_cq_tdata,
output [84:0] m_axis_cq_tuser,
output m_axis_cq_tlast,
output [KEEP_WIDTH-1:0] m_axis_cq_tkeep,
output m_axis_cq_tvalid,
input [21:0] m_axis_cq_tready,
input [C_DATA_WIDTH-1:0] s_axis_cc_tdata,
input [32:0] s_axis_cc_tuser,
input s_axis_cc_tlast,
input [KEEP_WIDTH-1:0] s_axis_cc_tkeep,
input s_axis_cc_tvalid,
output [3:0] s_axis_cc_tready,
output [3:0] pcie_rq_seq_num,
output pcie_rq_seq_num_vld,
output [5:0] pcie_rq_tag,
output pcie_rq_tag_vld,
output [1:0] pcie_tfc_nph_av,
output [1:0] pcie_tfc_npd_av,
input pcie_cq_np_req,
output [5:0] pcie_cq_np_req_count,
input [18:0] cfg_mgmt_addr,
input cfg_mgmt_write,
input [31:0] cfg_mgmt_write_data,
input [3:0] cfg_mgmt_byte_enable,
input cfg_mgmt_read,
output [31:0] cfg_mgmt_read_data,
output cfg_mgmt_read_write_done,
input cfg_mgmt_type1_cfg_reg_access,
output cfg_phy_link_down,
output [1:0] cfg_phy_link_status,
output [3:0] cfg_negotiated_width,
output [2:0] cfg_current_speed,
output [2:0] cfg_max_payload,
output [2:0] cfg_max_read_req,
output [7:0] cfg_function_status,
output [5:0] cfg_function_power_state,
output [11:0] cfg_vf_status,
output [17:0] cfg_vf_power_state,
output [1:0] cfg_link_power_state,
output cfg_err_cor_out,
output cfg_err_nonfatal_out,
output cfg_err_fatal_out,
output cfg_local_error,
output cfg_ltr_enable,
output [5:0] cfg_ltssm_state,
output [1:0] cfg_rcb_status,
output [1:0] cfg_dpa_substate_change,
output [1:0] cfg_obff_enable,
output cfg_pl_status_change,
output [1:0] cfg_tph_requester_enable,
output [5:0] cfg_tph_st_mode,
output [5:0] cfg_vf_tph_requester_enable,
output [17:0] cfg_vf_tph_st_mode,
output cfg_msg_received,
output [7:0] cfg_msg_received_data,
output [4:0] cfg_msg_received_type,
input cfg_msg_transmit,
input [2:0] cfg_msg_transmit_type,
input [31:0] cfg_msg_transmit_data,
output cfg_msg_transmit_done,
output [7:0] cfg_fc_ph,
output [11:0] cfg_fc_pd,
output [7:0] cfg_fc_nph,
output [11:0] cfg_fc_npd,
output [7:0] cfg_fc_cplh,
output [11:0] cfg_fc_cpld,
input [2:0] cfg_fc_sel,
input [2:0] cfg_per_func_status_control,
output [15:0] cfg_per_func_status_data,
input [2:0] cfg_per_function_number,
input cfg_per_function_output_request,
output cfg_per_function_update_done,
input [63:0] cfg_dsn,
input cfg_power_state_change_ack,
output cfg_power_state_change_interrupt,
input cfg_err_cor_in,
input cfg_err_uncor_in,
output [1:0] cfg_flr_in_process,
input [1:0] cfg_flr_done,
output [5:0] cfg_vf_flr_in_process,
input [5:0] cfg_vf_flr_done,
input cfg_link_training_enable,
input [3:0] cfg_interrupt_int,
input [1:0] cfg_interrupt_pending,
output cfg_interrupt_sent,
output [1:0] cfg_interrupt_msi_enable,
output [5:0] cfg_interrupt_msi_vf_enable,
output [5:0] cfg_interrupt_msi_mmenable,
output cfg_interrupt_msi_mask_update,
output [31:0] cfg_interrupt_msi_data,
input [3:0] cfg_interrupt_msi_select,
input [31:0] cfg_interrupt_msi_int,
input [63:0] cfg_interrupt_msi_pending_status,
output cfg_interrupt_msi_sent,
output cfg_interrupt_msi_fail,
output [1:0] cfg_interrupt_msix_enable,
output [1:0] cfg_interrupt_msix_mask,
output [5:0] cfg_interrupt_msix_vf_enable,
output [5:0] cfg_interrupt_msix_vf_mask,
input [31:0] cfg_interrupt_msix_data,
input [63:0] cfg_interrupt_msix_address,
input cfg_interrupt_msix_int,
output cfg_interrupt_msix_sent,
output cfg_interrupt_msix_fail,
input [2:0] cfg_interrupt_msi_attr,
input cfg_interrupt_msi_tph_present,
input [1:0] cfg_interrupt_msi_tph_type,
input [8:0] cfg_interrupt_msi_tph_st_tag,
input [2:0] cfg_interrupt_msi_function_number,
output cfg_ext_read_received,
output cfg_ext_write_received,
output [9:0] cfg_ext_register_number,
output [7:0] cfg_ext_function_number,
output [31:0] cfg_ext_write_data,
output [3:0] cfg_ext_write_byte_enable,
input [31:0] cfg_ext_read_data,
input cfg_ext_read_data_valid,
input [15:0] cfg_dev_id,
input [15:0] cfg_vend_id,
input [7:0] cfg_rev_id,
input [15:0] cfg_subsys_id,
input [15:0] cfg_subsys_vend_id,
input [7:0] cfg_ds_port_number,
// EP only
output cfg_hot_reset_out,
input cfg_config_space_enable,
input cfg_req_pm_transition_l23_ready,
// RP only
input cfg_hot_reset_in,
input [7:0] cfg_ds_bus_number,
input [4:0] cfg_ds_device_number,
input [2:0] cfg_ds_function_number,
output drp_rdy,
output [15:0] drp_do,
input drp_clk,
input drp_en,
input drp_we,
input [10:0] drp_addr,
input [15:0] drp_di,
// TPH Interface
input [4:0] user_tph_stt_address,
input [2:0] user_tph_function_num,
output [31:0] user_tph_stt_read_data,
output user_tph_stt_read_data_valid,
input user_tph_stt_read_enable,
output wire pipe_rx0_polarity_gt,
output wire pipe_rx1_polarity_gt,
output wire pipe_rx2_polarity_gt,
output wire pipe_rx3_polarity_gt,
output wire pipe_rx4_polarity_gt,
output wire pipe_rx5_polarity_gt,
output wire pipe_rx6_polarity_gt,
output wire pipe_rx7_polarity_gt,
output wire pipe_tx0_compliance_gt,
output wire pipe_tx1_compliance_gt,
output wire pipe_tx2_compliance_gt,
output wire pipe_tx3_compliance_gt,
output wire pipe_tx4_compliance_gt,
output wire pipe_tx5_compliance_gt,
output wire pipe_tx6_compliance_gt,
output wire pipe_tx7_compliance_gt,
output wire pipe_tx0_data_valid_gt,
output wire pipe_tx1_data_valid_gt,
output wire pipe_tx2_data_valid_gt,
output wire pipe_tx3_data_valid_gt,
output wire pipe_tx4_data_valid_gt,
output wire pipe_tx5_data_valid_gt,
output wire pipe_tx6_data_valid_gt,
output wire pipe_tx7_data_valid_gt,
output wire pipe_tx0_elec_idle_gt,
output wire pipe_tx1_elec_idle_gt,
output wire pipe_tx2_elec_idle_gt,
output wire pipe_tx3_elec_idle_gt,
output wire pipe_tx4_elec_idle_gt,
output wire pipe_tx5_elec_idle_gt,
output wire pipe_tx6_elec_idle_gt,
output wire pipe_tx7_elec_idle_gt,
output wire pipe_tx0_start_block_gt,
output wire pipe_tx1_start_block_gt,
output wire pipe_tx2_start_block_gt,
output wire pipe_tx3_start_block_gt,
output wire pipe_tx4_start_block_gt,
output wire pipe_tx5_start_block_gt,
output wire pipe_tx6_start_block_gt,
output wire pipe_tx7_start_block_gt,
output pipe_tx_deemph_gt,
output pipe_tx_rcvr_det_gt,
output [1:0] pipe_tx_rate_gt,
output [2:0] pipe_tx_margin_gt,
output pipe_tx_swing_gt,
input [5:0] pipe_tx_eqfs_gt,
input [5:0] pipe_tx_eqlf_gt,
output wire pipe_tx_reset_gt,
output wire [1:0] pipe_rx0_eqcontrol_gt,
output wire [1:0] pipe_rx1_eqcontrol_gt,
output wire [1:0] pipe_rx2_eqcontrol_gt,
output wire [1:0] pipe_rx3_eqcontrol_gt,
output wire [1:0] pipe_rx4_eqcontrol_gt,
output wire [1:0] pipe_rx5_eqcontrol_gt,
output wire [1:0] pipe_rx6_eqcontrol_gt,
output wire [1:0] pipe_rx7_eqcontrol_gt,
output wire [1:0] pipe_tx0_char_is_k_gt,
output wire [1:0] pipe_tx1_char_is_k_gt,
output wire [1:0] pipe_tx2_char_is_k_gt,
output wire [1:0] pipe_tx3_char_is_k_gt,
output wire [1:0] pipe_tx4_char_is_k_gt,
output wire [1:0] pipe_tx5_char_is_k_gt,
output wire [1:0] pipe_tx6_char_is_k_gt,
output wire [1:0] pipe_tx7_char_is_k_gt,
output wire [1:0] pipe_tx0_eqcontrol_gt,
output wire [1:0] pipe_tx1_eqcontrol_gt,
output wire [1:0] pipe_tx2_eqcontrol_gt,
output wire [1:0] pipe_tx3_eqcontrol_gt,
output wire [1:0] pipe_tx4_eqcontrol_gt,
output wire [1:0] pipe_tx5_eqcontrol_gt,
output wire [1:0] pipe_tx6_eqcontrol_gt,
output wire [1:0] pipe_tx7_eqcontrol_gt,
output wire [1:0] pipe_tx0_powerdown_gt,
output wire [1:0] pipe_tx1_powerdown_gt,
output wire [1:0] pipe_tx2_powerdown_gt,
output wire [1:0] pipe_tx3_powerdown_gt,
output wire [1:0] pipe_tx4_powerdown_gt,
output wire [1:0] pipe_tx5_powerdown_gt,
output wire [1:0] pipe_tx6_powerdown_gt,
output wire [1:0] pipe_tx7_powerdown_gt,
output wire [1:0] pipe_tx0_syncheader_gt,
output wire [1:0] pipe_tx1_syncheader_gt,
output wire [1:0] pipe_tx2_syncheader_gt,
output wire [1:0] pipe_tx3_syncheader_gt,
output wire [1:0] pipe_tx4_syncheader_gt,
output wire [1:0] pipe_tx5_syncheader_gt,
output wire [1:0] pipe_tx6_syncheader_gt,
output wire [1:0] pipe_tx7_syncheader_gt,
output wire [2:0] pipe_rx0_eqpreset_gt,
output wire [2:0] pipe_rx1_eqpreset_gt,
output wire [2:0] pipe_rx2_eqpreset_gt,
output wire [2:0] pipe_rx3_eqpreset_gt,
output wire [2:0] pipe_rx4_eqpreset_gt,
output wire [2:0] pipe_rx5_eqpreset_gt,
output wire [2:0] pipe_rx6_eqpreset_gt,
output wire [2:0] pipe_rx7_eqpreset_gt,
output wire [31:0] pipe_tx0_data_gt,
output wire [31:0] pipe_tx1_data_gt,
output wire [31:0] pipe_tx2_data_gt,
output wire [31:0] pipe_tx3_data_gt,
output wire [31:0] pipe_tx4_data_gt,
output wire [31:0] pipe_tx5_data_gt,
output wire [31:0] pipe_tx6_data_gt,
output wire [31:0] pipe_tx7_data_gt,
output wire [3:0] pipe_rx0_eqlp_txpreset_gt,
output wire [3:0] pipe_rx1_eqlp_txpreset_gt,
output wire [3:0] pipe_rx2_eqlp_txpreset_gt,
output wire [3:0] pipe_rx3_eqlp_txpreset_gt,
output wire [3:0] pipe_rx4_eqlp_txpreset_gt,
output wire [3:0] pipe_rx5_eqlp_txpreset_gt,
output wire [3:0] pipe_rx6_eqlp_txpreset_gt,
output wire [3:0] pipe_rx7_eqlp_txpreset_gt,
output wire [3:0] pipe_tx0_eqpreset_gt,
output wire [3:0] pipe_tx1_eqpreset_gt,
output wire [3:0] pipe_tx2_eqpreset_gt,
output wire [3:0] pipe_tx3_eqpreset_gt,
output wire [3:0] pipe_tx4_eqpreset_gt,
output wire [3:0] pipe_tx5_eqpreset_gt,
output wire [3:0] pipe_tx6_eqpreset_gt,
output wire [3:0] pipe_tx7_eqpreset_gt,
output wire [5:0] pipe_rx0_eqlp_lffs_gt,
output wire [5:0] pipe_rx1_eqlp_lffs_gt,
output wire [5:0] pipe_rx2_eqlp_lffs_gt,
output wire [5:0] pipe_rx3_eqlp_lffs_gt,
output wire [5:0] pipe_rx4_eqlp_lffs_gt,
output wire [5:0] pipe_rx5_eqlp_lffs_gt,
output wire [5:0] pipe_rx6_eqlp_lffs_gt,
output wire [5:0] pipe_rx7_eqlp_lffs_gt,
output wire [5:0] pipe_tx0_eqdeemph_gt,
output wire [5:0] pipe_tx1_eqdeemph_gt,
output wire [5:0] pipe_tx2_eqdeemph_gt,
output wire [5:0] pipe_tx3_eqdeemph_gt,
output wire [5:0] pipe_tx4_eqdeemph_gt,
output wire [5:0] pipe_tx5_eqdeemph_gt,
output wire [5:0] pipe_tx6_eqdeemph_gt,
output wire [5:0] pipe_tx7_eqdeemph_gt,
output wire [7:0] pipe_rx_slide_gt,
input wire [7:0] pipe_rx_syncdone_gt,
input pipe_rx0_data_valid_gt,
input pipe_rx1_data_valid_gt,
input pipe_rx2_data_valid_gt,
input pipe_rx3_data_valid_gt,
input pipe_rx4_data_valid_gt,
input pipe_rx5_data_valid_gt,
input pipe_rx6_data_valid_gt,
input pipe_rx7_data_valid_gt,
input pipe_rx0_elec_idle_gt,
input pipe_rx1_elec_idle_gt,
input pipe_rx2_elec_idle_gt,
input pipe_rx3_elec_idle_gt,
input pipe_rx4_elec_idle_gt,
input pipe_rx5_elec_idle_gt,
input pipe_rx6_elec_idle_gt,
input pipe_rx7_elec_idle_gt,
input pipe_rx0_eqdone_gt,
input pipe_rx1_eqdone_gt,
input pipe_rx2_eqdone_gt,
input pipe_rx3_eqdone_gt,
input pipe_rx4_eqdone_gt,
input pipe_rx5_eqdone_gt,
input pipe_rx6_eqdone_gt,
input pipe_rx7_eqdone_gt,
input pipe_rx0_eqlp_adaptdone_gt,
input pipe_rx1_eqlp_adaptdone_gt,
input pipe_rx2_eqlp_adaptdone_gt,
input pipe_rx3_eqlp_adaptdone_gt,
input pipe_rx4_eqlp_adaptdone_gt,
input pipe_rx5_eqlp_adaptdone_gt,
input pipe_rx6_eqlp_adaptdone_gt,
input pipe_rx7_eqlp_adaptdone_gt,
input pipe_rx0_eqlp_lffs_sel_gt,
input pipe_rx1_eqlp_lffs_sel_gt,
input pipe_rx2_eqlp_lffs_sel_gt,
input pipe_rx3_eqlp_lffs_sel_gt,
input pipe_rx4_eqlp_lffs_sel_gt,
input pipe_rx5_eqlp_lffs_sel_gt,
input pipe_rx6_eqlp_lffs_sel_gt,
input pipe_rx7_eqlp_lffs_sel_gt,
input pipe_rx0_phy_status_gt,
input pipe_rx1_phy_status_gt,
input pipe_rx2_phy_status_gt,
input pipe_rx3_phy_status_gt,
input pipe_rx4_phy_status_gt,
input pipe_rx5_phy_status_gt,
input pipe_rx6_phy_status_gt,
input pipe_rx7_phy_status_gt,
input pipe_rx0_start_block_gt,
input pipe_rx1_start_block_gt,
input pipe_rx2_start_block_gt,
input pipe_rx3_start_block_gt,
input pipe_rx4_start_block_gt,
input pipe_rx5_start_block_gt,
input pipe_rx6_start_block_gt,
input pipe_rx7_start_block_gt,
input pipe_rx0_valid_gt,
input pipe_rx1_valid_gt,
input pipe_rx2_valid_gt,
input pipe_rx3_valid_gt,
input pipe_rx4_valid_gt,
input pipe_rx5_valid_gt,
input pipe_rx6_valid_gt,
input pipe_rx7_valid_gt,
input pipe_tx0_eqdone_gt,
input pipe_tx1_eqdone_gt,
input pipe_tx2_eqdone_gt,
input pipe_tx3_eqdone_gt,
input pipe_tx4_eqdone_gt,
input pipe_tx5_eqdone_gt,
input pipe_tx6_eqdone_gt,
input pipe_tx7_eqdone_gt,
input [17:0] pipe_rx0_eqlp_new_txcoef_forpreset_gt,
input [17:0] pipe_rx1_eqlp_new_txcoef_forpreset_gt,
input [17:0] pipe_rx2_eqlp_new_txcoef_forpreset_gt,
input [17:0] pipe_rx3_eqlp_new_txcoef_forpreset_gt,
input [17:0] pipe_rx4_eqlp_new_txcoef_forpreset_gt,
input [17:0] pipe_rx5_eqlp_new_txcoef_forpreset_gt,
input [17:0] pipe_rx6_eqlp_new_txcoef_forpreset_gt,
input [17:0] pipe_rx7_eqlp_new_txcoef_forpreset_gt,
input [17:0] pipe_tx0_eqcoeff_gt,
input [17:0] pipe_tx1_eqcoeff_gt,
input [17:0] pipe_tx2_eqcoeff_gt,
input [17:0] pipe_tx3_eqcoeff_gt,
input [17:0] pipe_tx4_eqcoeff_gt,
input [17:0] pipe_tx5_eqcoeff_gt,
input [17:0] pipe_tx6_eqcoeff_gt,
input [17:0] pipe_tx7_eqcoeff_gt,
input [1:0] pipe_rx0_char_is_k_gt,
input [1:0] pipe_rx1_char_is_k_gt,
input [1:0] pipe_rx2_char_is_k_gt,
input [1:0] pipe_rx3_char_is_k_gt,
input [1:0] pipe_rx4_char_is_k_gt,
input [1:0] pipe_rx5_char_is_k_gt,
input [1:0] pipe_rx6_char_is_k_gt,
input [1:0] pipe_rx7_char_is_k_gt,
input [1:0] pipe_rx0_syncheader_gt,
input [1:0] pipe_rx1_syncheader_gt,
input [1:0] pipe_rx2_syncheader_gt,
input [1:0] pipe_rx3_syncheader_gt,
input [1:0] pipe_rx4_syncheader_gt,
input [1:0] pipe_rx5_syncheader_gt,
input [1:0] pipe_rx6_syncheader_gt,
input [1:0] pipe_rx7_syncheader_gt,
input [2:0] pipe_rx0_status_gt,
input [2:0] pipe_rx1_status_gt,
input [2:0] pipe_rx2_status_gt,
input [2:0] pipe_rx3_status_gt,
input [2:0] pipe_rx4_status_gt,
input [2:0] pipe_rx5_status_gt,
input [2:0] pipe_rx6_status_gt,
input [2:0] pipe_rx7_status_gt,
input [31:0] pipe_rx0_data_gt,
input [31:0] pipe_rx1_data_gt,
input [31:0] pipe_rx2_data_gt,
input [31:0] pipe_rx3_data_gt,
input [31:0] pipe_rx4_data_gt,
input [31:0] pipe_rx5_data_gt,
input [31:0] pipe_rx6_data_gt,
input [31:0] pipe_rx7_data_gt
);
//extra wires to math the axi ports size//
//MAXICQTDATA
wire [255:0] m_axis_cq_tdata_256;
assign m_axis_cq_tdata=m_axis_cq_tdata_256[C_DATA_WIDTH-1 : 0];
//MAXISRCTDATA
wire [255:0] m_axis_rc_tdata_256;
assign m_axis_rc_tdata=m_axis_rc_tdata_256[C_DATA_WIDTH-1 : 0];
//MAXISCQTKEEP
wire [7:0] m_axis_cq_tkeep_w;
assign m_axis_cq_tkeep=m_axis_cq_tkeep_w [(C_DATA_WIDTH/32)-1 : 0];
//MAXISRCTKEEP
wire [7:0] m_axis_rc_tkeep_w;
assign m_axis_rc_tkeep=m_axis_rc_tkeep_w [(C_DATA_WIDTH/32)-1 : 0];
//SAXISRQTDATA
//assign saxiscctdata_extra_wire=256'd0;
wire [255:0] s_axis_rq_tdata_256;
assign s_axis_rq_tdata_256 =s_axis_rq_tdata;
//SAXISCSTDATA
//assign saxiscctdata_extra_wire=256'd0;
wire [255:0] s_axis_cc_tdata_256;
assign s_axis_cc_tdata_256 =s_axis_cc_tdata;
//SAXISCCTKEEP
wire [7:0] s_axis_cc_tkeep_w;
assign s_axis_cc_tkeep_w =s_axis_cc_tkeep;
//SAXISRQTKEEP
wire [7:0] s_axis_rq_tkeep_w;
assign s_axis_rq_tkeep_w = s_axis_rq_tkeep;
//----------------------------------//
// PIPE signals //
//----------------------------------//
wire pipe_tx_rcvr_det;
wire pipe_tx_reset;
wire [1:0] pipe_tx_rate;
wire pipe_tx_deemph;
wire [2:0] pipe_tx_margin;
wire pipe_tx_swing;
wire [5:0] pipe_tx_eqfs;
wire [5:0] pipe_tx_eqlf;
wire [7:0] pipe_rx_slide;
wire [7:0] pipe_rx_syncdone;
// Pipe Per-Lane Signals - Lane 0
wire [ 1:0] pipe_rx0_char_is_k;
wire [31:0] pipe_rx0_data;
wire pipe_rx0_valid;
wire pipe_rx0_data_valid;
wire [ 2:0] pipe_rx0_status;
wire pipe_rx0_phy_status;
wire pipe_rx0_elec_idle;
wire pipe_rx0_eqdone;
wire pipe_rx0_eqlp_adaptdone;
wire pipe_rx0_eqlp_lffs_sel;
wire [3:0] pipe_rx0_eqlp_txpreset;
wire [17:0] pipe_rx0_eqlp_new_txcoef_forpreset;
wire pipe_rx0_start_block;
wire [ 1:0] pipe_rx0_syncheader;
wire pipe_rx0_polarity;
wire [ 1:0] pipe_rx0_eqcontrol;
wire [ 5:0] pipe_rx0_eqlp_lffs;
wire [ 2:0] pipe_rx0_eqpreset;
wire [17:0] pipe_tx0_eqcoeff;
wire pipe_tx0_eqdone;
wire pipe_tx0_compliance;
wire [ 1:0] pipe_tx0_char_is_k;
wire [31:0] pipe_tx0_data;
wire pipe_tx0_elec_idle;
wire [ 1:0] pipe_tx0_powerdown;
wire pipe_tx0_data_valid;
wire pipe_tx0_start_block;
wire [ 1:0] pipe_tx0_syncheader;
wire [ 1:0] pipe_tx0_eqcontrol;
wire [ 5:0] pipe_tx0_eqdeemph;
wire [ 3:0] pipe_tx0_eqpreset;
// Pipe Per-Lane Signals - Lane 1
wire [ 1:0] pipe_rx1_char_is_k;
wire [31:0] pipe_rx1_data;
wire pipe_rx1_valid;
wire pipe_rx1_data_valid;
wire [ 2:0] pipe_rx1_status;
wire pipe_rx1_phy_status;
wire pipe_rx1_elec_idle;
wire pipe_rx1_eqdone;
wire pipe_rx1_eqlp_adaptdone;
wire pipe_rx1_eqlp_lffs_sel;
wire [3:0] pipe_rx1_eqlp_txpreset;
wire [17:0] pipe_rx1_eqlp_new_txcoef_forpreset;
wire pipe_rx1_start_block;
wire [ 1:0] pipe_rx1_syncheader;
wire pipe_rx1_polarity;
wire [ 1:0] pipe_rx1_eqcontrol;
wire [ 5:0] pipe_rx1_eqlp_lffs;
wire [ 2:0] pipe_rx1_eqpreset;
wire [17:0] pipe_tx1_eqcoeff;
wire pipe_tx1_eqdone;
wire pipe_tx1_compliance;
wire [ 1:0] pipe_tx1_char_is_k;
wire [31:0] pipe_tx1_data;
wire pipe_tx1_elec_idle;
wire [ 1:0] pipe_tx1_powerdown;
wire pipe_tx1_data_valid;
wire pipe_tx1_start_block;
wire [ 1:0] pipe_tx1_syncheader;
wire [ 1:0] pipe_tx1_eqcontrol;
wire [ 5:0] pipe_tx1_eqdeemph;
wire [ 3:0] pipe_tx1_eqpreset;
// Pipe Per-Lane Signals - Lane 2
wire [ 1:0] pipe_rx2_char_is_k;
wire [31:0] pipe_rx2_data;
wire pipe_rx2_valid;
wire pipe_rx2_data_valid;
wire [ 2:0] pipe_rx2_status;
wire pipe_rx2_phy_status;
wire pipe_rx2_elec_idle;
wire pipe_rx2_eqdone;
wire pipe_rx2_eqlp_adaptdone;
wire pipe_rx2_eqlp_lffs_sel;
wire [3:0] pipe_rx2_eqlp_txpreset;
wire [17:0] pipe_rx2_eqlp_new_txcoef_forpreset;
wire pipe_rx2_start_block;
wire [ 1:0] pipe_rx2_syncheader;
wire pipe_rx2_polarity;
wire [ 1:0] pipe_rx2_eqcontrol;
wire [ 5:0] pipe_rx2_eqlp_lffs;
wire [ 2:0] pipe_rx2_eqpreset;
wire [17:0] pipe_tx2_eqcoeff;
wire pipe_tx2_eqdone;
wire pipe_tx2_compliance;
wire [ 1:0] pipe_tx2_char_is_k;
wire [31:0] pipe_tx2_data;
wire pipe_tx2_elec_idle;
wire [ 1:0] pipe_tx2_powerdown;
wire pipe_tx2_data_valid;
wire pipe_tx2_start_block;
wire [ 1:0] pipe_tx2_syncheader;
wire [ 1:0] pipe_tx2_eqcontrol;
wire [ 5:0] pipe_tx2_eqdeemph;
wire [ 3:0] pipe_tx2_eqpreset;
// Pipe Per-Lane Signals - Lane 3
wire [ 1:0] pipe_rx3_char_is_k;
wire [31:0] pipe_rx3_data;
wire pipe_rx3_valid;
wire pipe_rx3_data_valid;
wire [ 2:0] pipe_rx3_status;
wire pipe_rx3_phy_status;
wire pipe_rx3_elec_idle;
wire pipe_rx3_eqdone;
wire pipe_rx3_eqlp_adaptdone;
wire pipe_rx3_eqlp_lffs_sel;
wire [3:0] pipe_rx3_eqlp_txpreset;
wire [17:0] pipe_rx3_eqlp_new_txcoef_forpreset;
wire pipe_rx3_start_block;
wire [ 1:0] pipe_rx3_syncheader;
wire pipe_rx3_polarity;
wire [ 1:0] pipe_rx3_eqcontrol;
wire [ 5:0] pipe_rx3_eqlp_lffs;
wire [ 2:0] pipe_rx3_eqpreset;
wire [17:0] pipe_tx3_eqcoeff;
wire pipe_tx3_eqdone;
wire pipe_tx3_compliance;
wire [ 1:0] pipe_tx3_char_is_k;
wire [31:0] pipe_tx3_data;
wire pipe_tx3_elec_idle;
wire [ 1:0] pipe_tx3_powerdown;
wire pipe_tx3_data_valid;
wire pipe_tx3_start_block;
wire [ 1:0] pipe_tx3_syncheader;
wire [ 1:0] pipe_tx3_eqcontrol;
wire [ 5:0] pipe_tx3_eqdeemph;
wire [ 3:0] pipe_tx3_eqpreset;
// Pipe Per-Lane Signals - Lane 4
wire [ 1:0] pipe_rx4_char_is_k;
wire [31:0] pipe_rx4_data;
wire pipe_rx4_valid;
wire pipe_rx4_data_valid;
wire [ 2:0] pipe_rx4_status;
wire pipe_rx4_phy_status;
wire pipe_rx4_elec_idle;
wire pipe_rx4_eqdone;
wire pipe_rx4_eqlp_adaptdone;
wire pipe_rx4_eqlp_lffs_sel;
wire [3:0] pipe_rx4_eqlp_txpreset;
wire [17:0] pipe_rx4_eqlp_new_txcoef_forpreset;
wire pipe_rx4_start_block;
wire [ 1:0] pipe_rx4_syncheader;
wire pipe_rx4_polarity;
wire [ 1:0] pipe_rx4_eqcontrol;
wire [ 5:0] pipe_rx4_eqlp_lffs;
wire [ 2:0] pipe_rx4_eqpreset;
wire [17:0] pipe_tx4_eqcoeff;
wire pipe_tx4_eqdone;
wire pipe_tx4_compliance;
wire [ 1:0] pipe_tx4_char_is_k;
wire [31:0] pipe_tx4_data;
wire pipe_tx4_elec_idle;
wire [ 1:0] pipe_tx4_powerdown;
wire pipe_tx4_data_valid;
wire pipe_tx4_start_block;
wire [ 1:0] pipe_tx4_syncheader;
wire [ 1:0] pipe_tx4_eqcontrol;
wire [ 5:0] pipe_tx4_eqdeemph;
wire [ 3:0] pipe_tx4_eqpreset;
// Pipe Per-Lane Signals - Lane 5
wire [ 1:0] pipe_rx5_char_is_k;
wire [31:0] pipe_rx5_data;
wire pipe_rx5_valid;
wire pipe_rx5_data_valid;
wire [ 2:0] pipe_rx5_status;
wire pipe_rx5_phy_status;
wire pipe_rx5_elec_idle;
wire pipe_rx5_eqdone;
wire pipe_rx5_eqlp_adaptdone;
wire pipe_rx5_eqlp_lffs_sel;
wire [3:0] pipe_rx5_eqlp_txpreset;
wire [17:0] pipe_rx5_eqlp_new_txcoef_forpreset;
wire pipe_rx5_start_block;
wire [ 1:0] pipe_rx5_syncheader;
wire pipe_rx5_polarity;
wire [ 1:0] pipe_rx5_eqcontrol;
wire [ 5:0] pipe_rx5_eqlp_lffs;
wire [ 2:0] pipe_rx5_eqpreset;
wire [17:0] pipe_tx5_eqcoeff;
wire pipe_tx5_eqdone;
wire pipe_tx5_compliance;
wire [ 1:0] pipe_tx5_char_is_k;
wire [31:0] pipe_tx5_data;
wire pipe_tx5_elec_idle;
wire [ 1:0] pipe_tx5_powerdown;
wire pipe_tx5_data_valid;
wire pipe_tx5_start_block;
wire [ 1:0] pipe_tx5_syncheader;
wire [ 1:0] pipe_tx5_eqcontrol;
wire [ 5:0] pipe_tx5_eqdeemph;
wire [ 3:0] pipe_tx5_eqpreset;
// Pipe Per-Lane Signals - Lane 6
wire [ 1:0] pipe_rx6_char_is_k;
wire [31:0] pipe_rx6_data;
wire pipe_rx6_valid;
wire pipe_rx6_data_valid;
wire [ 2:0] pipe_rx6_status;
wire pipe_rx6_phy_status;
wire pipe_rx6_elec_idle;
wire pipe_rx6_eqdone;
wire pipe_rx6_eqlp_adaptdone;
wire pipe_rx6_eqlp_lffs_sel;
wire [3:0] pipe_rx6_eqlp_txpreset;
wire [17:0] pipe_rx6_eqlp_new_txcoef_forpreset;
wire pipe_rx6_start_block;
wire [ 1:0] pipe_rx6_syncheader;
wire pipe_rx6_polarity;
wire [ 1:0] pipe_rx6_eqcontrol;
wire [ 5:0] pipe_rx6_eqlp_lffs;
wire [ 2:0] pipe_rx6_eqpreset;
wire [17:0] pipe_tx6_eqcoeff;
wire pipe_tx6_eqdone;
wire pipe_tx6_compliance;
wire [ 1:0] pipe_tx6_char_is_k;
wire [31:0] pipe_tx6_data;
wire pipe_tx6_elec_idle;
wire [ 1:0] pipe_tx6_powerdown;
wire pipe_tx6_data_valid;
wire pipe_tx6_start_block;
wire [ 1:0] pipe_tx6_syncheader;
wire [ 1:0] pipe_tx6_eqcontrol;
wire [ 5:0] pipe_tx6_eqdeemph;
wire [ 3:0] pipe_tx6_eqpreset;
// Pipe Per-Lane Signals - Lane 7
wire [ 1:0] pipe_rx7_char_is_k;
wire [31:0] pipe_rx7_data;
wire pipe_rx7_valid;
wire pipe_rx7_data_valid;
wire [ 2:0] pipe_rx7_status;
wire pipe_rx7_phy_status;
wire pipe_rx7_elec_idle;
wire pipe_rx7_eqdone;
wire pipe_rx7_eqlp_adaptdone;
wire pipe_rx7_eqlp_lffs_sel;
wire [3:0] pipe_rx7_eqlp_txpreset;
wire [17:0] pipe_rx7_eqlp_new_txcoef_forpreset;
wire pipe_rx7_start_block;
wire [ 1:0] pipe_rx7_syncheader;
wire pipe_rx7_polarity;
wire [ 1:0] pipe_rx7_eqcontrol;
wire [ 5:0] pipe_rx7_eqlp_lffs;
wire [ 2:0] pipe_rx7_eqpreset;
wire [17:0] pipe_tx7_eqcoeff;
wire pipe_tx7_eqdone;
wire pipe_tx7_compliance;
wire [ 1:0] pipe_tx7_char_is_k;
wire [31:0] pipe_tx7_data;
wire pipe_tx7_elec_idle;
wire [ 1:0] pipe_tx7_powerdown;
wire pipe_tx7_data_valid;
wire pipe_tx7_start_block;
wire [ 1:0] pipe_tx7_syncheader;
wire [ 1:0] pipe_tx7_eqcontrol;
wire [ 5:0] pipe_tx7_eqdeemph;
wire [ 3:0] pipe_tx7_eqpreset;
// Pipe Per-Lane Signals - Force Adapt
wire [31:0] pipe_rx0_data_pcie;
wire [31:0] pipe_rx1_data_pcie;
wire [31:0] pipe_rx2_data_pcie;
wire [31:0] pipe_rx3_data_pcie;
wire [31:0] pipe_rx4_data_pcie;
wire [31:0] pipe_rx5_data_pcie;
wire [31:0] pipe_rx6_data_pcie;
wire [31:0] pipe_rx7_data_pcie;
wire [1:0] pipe_rx0_eqcontrol_pcie;
wire [1:0] pipe_rx1_eqcontrol_pcie;
wire [1:0] pipe_rx2_eqcontrol_pcie;
wire [1:0] pipe_rx3_eqcontrol_pcie;
wire [1:0] pipe_rx4_eqcontrol_pcie;
wire [1:0] pipe_rx5_eqcontrol_pcie;
wire [1:0] pipe_rx6_eqcontrol_pcie;
wire [1:0] pipe_rx7_eqcontrol_pcie;
//----------------------------------//
// Non PIPE signals //
//----------------------------------//
// Initialization Controller Signals
wire reset_n;
wire pipe_reset_n;
wire mgmt_reset_n;
wire mgmt_sticky_reset_n;
wire cfg_input_update_done;
wire cfg_input_update_request;
wire cfg_mc_update_done;
wire cfg_mc_update_request;
// TLP Hints Table Signals
wire [4:0] cfg_tph_stt_address;
wire [2:0] cfg_tph_function_num;
wire [31:0] cfg_tph_stt_write_data;
wire cfg_tph_stt_write_enable;
wire [3:0] cfg_tph_stt_write_byte_valid;
wire [31:0] cfg_tph_stt_read_data;
wire cfg_tph_stt_read_enable;
wire cfg_tph_stt_read_data_valid;
// Disable Gen3PCS in PIPE Simulation Mode
wire gen3pcsdisable ;
assign gen3pcsdisable = (PIPE_SIM_MODE == "FALSE") ? 1'b0 : 1'b1 ;
// PCIe Initialization Controller
pcie3_7x_0_pcie_init_ctrl_7vx # (
.PL_UPSTREAM_FACING ( PL_UPSTREAM_FACING ),
.TCQ ( TCQ )
) pcie_init_ctrl_7vx_i (
.clk_i (user_clk),
.reset_n_o (reset_n),
.pipe_reset_n_o (pipe_reset_n),
.mgmt_reset_n_o (mgmt_reset_n),
.mgmt_sticky_reset_n_o (mgmt_sticky_reset_n),
.mmcm_lock_i (mmcm_lock),
.phy_rdy_i (phy_rdy),
.cfg_input_update_done_i (cfg_input_update_done),
.cfg_input_update_request_o (cfg_input_update_request),
.cfg_mc_update_done_i (cfg_mc_update_done),
.cfg_mc_update_request_o (cfg_mc_update_request),
.user_cfg_input_update_i ( 1'b0 ),
.state_o ( )
);
// PCIe TLP Processing Hints Table
pcie3_7x_0_pcie_tlp_tph_tbl_7vx # (
.TCQ (TCQ )
) pcie_tlp_tph_tbl_7vx_i (
.user_clk ( user_clk ), // User Clock
.reset_n ( reset_n ), // Warm, Hot Reset, active low
// Integrated Block Interface
.cfg_tph_stt_address_i ( cfg_tph_stt_address ), // Address
.cfg_tph_function_num_i ( cfg_tph_function_num ), // Function #
.cfg_tph_stt_write_data_i ( cfg_tph_stt_write_data ), // Write Data
.cfg_tph_stt_write_enable_i ( cfg_tph_stt_write_enable ), // Write Data Enable
.cfg_tph_stt_write_byte_valid_i ( cfg_tph_stt_write_byte_valid ), // WBE
.cfg_tph_stt_read_data_o ( cfg_tph_stt_read_data ), // Read Data
.cfg_tph_stt_read_enable_i ( cfg_tph_stt_read_enable ), // Read Data Enable
.cfg_tph_stt_read_data_valid_o ( cfg_tph_stt_read_data_valid ), // Read Data Valid
// User Interface
.user_tph_stt_address_i ( user_tph_stt_address ), // Address
.user_tph_function_num_i ( user_tph_function_num ), // Function #
.user_tph_stt_read_data_o ( user_tph_stt_read_data ), // Read Data
.user_tph_stt_read_data_valid_o ( user_tph_stt_read_data_valid ), // Read Data Valid
.user_tph_stt_read_enable_i ( user_tph_stt_read_enable ) // Read Data Enable
);
pcie3_7x_0_pcie_7vx #(
.ARI_CAP_ENABLE ( ARI_CAP_ENABLE ),
.AXISTEN_IF_CC_ALIGNMENT_MODE ( AXISTEN_IF_CC_ALIGNMENT_MODE ),
.AXISTEN_IF_CC_PARITY_CHK ( AXISTEN_IF_CC_PARITY_CHK ),
.AXISTEN_IF_CQ_ALIGNMENT_MODE ( AXISTEN_IF_CQ_ALIGNMENT_MODE ),
.AXISTEN_IF_ENABLE_CLIENT_TAG ( AXISTEN_IF_ENABLE_CLIENT_TAG ),
.AXISTEN_IF_ENABLE_MSG_ROUTE ( AXISTEN_IF_ENABLE_MSG_ROUTE ),
.AXISTEN_IF_ENABLE_RX_MSG_INTFC ( AXISTEN_IF_ENABLE_RX_MSG_INTFC ),
.AXISTEN_IF_RC_ALIGNMENT_MODE ( AXISTEN_IF_RC_ALIGNMENT_MODE ),
.AXISTEN_IF_RC_STRADDLE ( AXISTEN_IF_RC_STRADDLE ),
.AXISTEN_IF_RQ_ALIGNMENT_MODE ( AXISTEN_IF_RQ_ALIGNMENT_MODE ),
.AXISTEN_IF_RQ_PARITY_CHK ( AXISTEN_IF_RQ_PARITY_CHK ),
.AXISTEN_IF_WIDTH ( AXISTEN_IF_WIDTH ),
.CRM_CORE_CLK_FREQ_500 ( CRM_CORE_CLK_FREQ_500 ),
.CRM_USER_CLK_FREQ ( CRM_USER_CLK_FREQ ),
.DNSTREAM_LINK_NUM ( DNSTREAM_LINK_NUM ),
.GEN3_PCS_AUTO_REALIGN ( GEN3_PCS_AUTO_REALIGN ),
.GEN3_PCS_RX_ELECIDLE_INTERNAL ( GEN3_PCS_RX_ELECIDLE_INTERNAL ),
.LL_ACK_TIMEOUT ( LL_ACK_TIMEOUT ),
.LL_ACK_TIMEOUT_EN ( LL_ACK_TIMEOUT_EN ),
.LL_ACK_TIMEOUT_FUNC ( LL_ACK_TIMEOUT_FUNC ),
.LL_CPL_FC_UPDATE_TIMER ( LL_CPL_FC_UPDATE_TIMER ),
.LL_CPL_FC_UPDATE_TIMER_OVERRIDE ( LL_CPL_FC_UPDATE_TIMER_OVERRIDE ),
.LL_FC_UPDATE_TIMER ( LL_FC_UPDATE_TIMER ),
.LL_FC_UPDATE_TIMER_OVERRIDE ( LL_FC_UPDATE_TIMER_OVERRIDE ),
.LL_NP_FC_UPDATE_TIMER ( LL_NP_FC_UPDATE_TIMER ),
.LL_NP_FC_UPDATE_TIMER_OVERRIDE ( LL_NP_FC_UPDATE_TIMER_OVERRIDE ),
.LL_P_FC_UPDATE_TIMER ( LL_P_FC_UPDATE_TIMER ),
.LL_P_FC_UPDATE_TIMER_OVERRIDE ( LL_P_FC_UPDATE_TIMER_OVERRIDE ),
.LL_REPLAY_TIMEOUT ( LL_REPLAY_TIMEOUT ),
.LL_REPLAY_TIMEOUT_EN ( LL_REPLAY_TIMEOUT_EN ),
.LL_REPLAY_TIMEOUT_FUNC ( LL_REPLAY_TIMEOUT_FUNC ),
.LTR_TX_MESSAGE_MINIMUM_INTERVAL ( LTR_TX_MESSAGE_MINIMUM_INTERVAL ),
.LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE ( LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE ),
.LTR_TX_MESSAGE_ON_LTR_ENABLE ( LTR_TX_MESSAGE_ON_LTR_ENABLE ),
.PF0_AER_CAP_ECRC_CHECK_CAPABLE ( PF0_AER_CAP_ECRC_CHECK_CAPABLE ),
.PF0_AER_CAP_ECRC_GEN_CAPABLE ( PF0_AER_CAP_ECRC_GEN_CAPABLE ),
.PF0_AER_CAP_NEXTPTR ( PF0_AER_CAP_NEXTPTR ),
.PF0_ARI_CAP_NEXTPTR ( PF0_ARI_CAP_NEXTPTR ),
.PF0_ARI_CAP_NEXT_FUNC ( PF0_ARI_CAP_NEXT_FUNC ),
.PF0_ARI_CAP_VER ( PF0_ARI_CAP_VER ),
.PF0_BAR0_APERTURE_SIZE ( PF0_BAR0_APERTURE_SIZE ),
.PF0_BAR0_CONTROL ( PF0_BAR0_CONTROL ),
.PF0_BAR1_APERTURE_SIZE ( PF0_BAR1_APERTURE_SIZE ),
.PF0_BAR1_CONTROL ( PF0_BAR1_CONTROL ),
.PF0_BAR2_APERTURE_SIZE ( PF0_BAR2_APERTURE_SIZE ),
.PF0_BAR2_CONTROL ( PF0_BAR2_CONTROL ),
.PF0_BAR3_APERTURE_SIZE ( PF0_BAR3_APERTURE_SIZE ),
.PF0_BAR3_CONTROL ( PF0_BAR3_CONTROL ),
.PF0_BAR4_APERTURE_SIZE ( PF0_BAR4_APERTURE_SIZE ),
.PF0_BAR4_CONTROL ( PF0_BAR4_CONTROL ),
.PF0_BAR5_APERTURE_SIZE ( PF0_BAR5_APERTURE_SIZE ),
.PF0_BAR5_CONTROL ( PF0_BAR5_CONTROL ),
.PF0_BIST_REGISTER ( PF0_BIST_REGISTER ),
.PF0_CAPABILITY_POINTER ( PF0_CAPABILITY_POINTER ),
.PF0_CLASS_CODE ( PF0_CLASS_CODE ),
.PF0_DEVICE_ID ( PF0_DEVICE_ID ),
.PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT ( PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT ),
.PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT ( PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT ),
.PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT ( PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT ),
.PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE ( PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE ),
.PF0_DEV_CAP2_LTR_SUPPORT ( PF0_DEV_CAP2_LTR_SUPPORT ),
.PF0_DEV_CAP2_OBFF_SUPPORT ( PF0_DEV_CAP2_OBFF_SUPPORT ),
.PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT ( PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT ),
.PF0_DEV_CAP_ENDPOINT_L0S_LATENCY ( PF0_DEV_CAP_ENDPOINT_L0S_LATENCY ),
.PF0_DEV_CAP_ENDPOINT_L1_LATENCY ( PF0_DEV_CAP_ENDPOINT_L1_LATENCY ),
.PF0_DEV_CAP_EXT_TAG_SUPPORTED ( PF0_DEV_CAP_EXT_TAG_SUPPORTED ),
.PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ( PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE ),
.PF0_DEV_CAP_MAX_PAYLOAD_SIZE ( PF0_DEV_CAP_MAX_PAYLOAD_SIZE ),
.PF0_DPA_CAP_NEXTPTR ( PF0_DPA_CAP_NEXTPTR ),
.VF0_ARI_CAP_NEXTPTR (VF0_ARI_CAP_NEXTPTR ),
.VF1_ARI_CAP_NEXTPTR (VF1_ARI_CAP_NEXTPTR ),
.VF2_ARI_CAP_NEXTPTR (VF2_ARI_CAP_NEXTPTR ),
.VF3_ARI_CAP_NEXTPTR (VF3_ARI_CAP_NEXTPTR ),
.VF4_ARI_CAP_NEXTPTR (VF4_ARI_CAP_NEXTPTR ),
.VF5_ARI_CAP_NEXTPTR (VF5_ARI_CAP_NEXTPTR ),
.VF0_TPHR_CAP_DEV_SPECIFIC_MODE (VF0_TPHR_CAP_DEV_SPECIFIC_MODE),
.VF0_TPHR_CAP_ENABLE (VF0_TPHR_CAP_ENABLE),
.VF0_TPHR_CAP_INT_VEC_MODE (VF0_TPHR_CAP_INT_VEC_MODE),
.VF0_TPHR_CAP_NEXTPTR (VF0_TPHR_CAP_NEXTPTR),
.VF0_TPHR_CAP_ST_MODE_SEL (VF0_TPHR_CAP_ST_MODE_SEL),
.VF0_TPHR_CAP_ST_TABLE_LOC (VF0_TPHR_CAP_ST_TABLE_LOC),
.VF0_TPHR_CAP_ST_TABLE_SIZE (VF0_TPHR_CAP_ST_TABLE_SIZE),
.VF0_TPHR_CAP_VER (VF0_TPHR_CAP_VER),
.VF1_TPHR_CAP_DEV_SPECIFIC_MODE (VF1_TPHR_CAP_DEV_SPECIFIC_MODE),
.VF1_TPHR_CAP_ENABLE (VF1_TPHR_CAP_ENABLE),
.VF1_TPHR_CAP_INT_VEC_MODE (VF1_TPHR_CAP_INT_VEC_MODE),
.VF1_TPHR_CAP_NEXTPTR (VF1_TPHR_CAP_NEXTPTR),
.VF1_TPHR_CAP_ST_MODE_SEL (VF1_TPHR_CAP_ST_MODE_SEL),
.VF1_TPHR_CAP_ST_TABLE_LOC (VF1_TPHR_CAP_ST_TABLE_LOC),
.VF1_TPHR_CAP_ST_TABLE_SIZE (VF1_TPHR_CAP_ST_TABLE_SIZE),
.VF1_TPHR_CAP_VER (VF1_TPHR_CAP_VER),
.VF2_TPHR_CAP_DEV_SPECIFIC_MODE (VF2_TPHR_CAP_DEV_SPECIFIC_MODE),
.VF2_TPHR_CAP_ENABLE (VF2_TPHR_CAP_ENABLE),
.VF2_TPHR_CAP_INT_VEC_MODE (VF2_TPHR_CAP_INT_VEC_MODE),
.VF2_TPHR_CAP_NEXTPTR (VF2_TPHR_CAP_NEXTPTR),
.VF2_TPHR_CAP_ST_MODE_SEL (VF2_TPHR_CAP_ST_MODE_SEL),
.VF2_TPHR_CAP_ST_TABLE_LOC (VF2_TPHR_CAP_ST_TABLE_LOC),
.VF2_TPHR_CAP_ST_TABLE_SIZE (VF2_TPHR_CAP_ST_TABLE_SIZE),
.VF2_TPHR_CAP_VER (VF2_TPHR_CAP_VER),
.VF3_TPHR_CAP_DEV_SPECIFIC_MODE (VF3_TPHR_CAP_DEV_SPECIFIC_MODE),
.VF3_TPHR_CAP_ENABLE (VF3_TPHR_CAP_ENABLE),
.VF3_TPHR_CAP_INT_VEC_MODE (VF3_TPHR_CAP_INT_VEC_MODE),
.VF3_TPHR_CAP_NEXTPTR (VF3_TPHR_CAP_NEXTPTR),
.VF3_TPHR_CAP_ST_MODE_SEL (VF3_TPHR_CAP_ST_MODE_SEL),
.VF3_TPHR_CAP_ST_TABLE_LOC (VF3_TPHR_CAP_ST_TABLE_LOC),
.VF3_TPHR_CAP_ST_TABLE_SIZE (VF3_TPHR_CAP_ST_TABLE_SIZE),
.VF3_TPHR_CAP_VER (VF3_TPHR_CAP_VER),
.VF4_TPHR_CAP_DEV_SPECIFIC_MODE (VF4_TPHR_CAP_DEV_SPECIFIC_MODE),
.VF4_TPHR_CAP_ENABLE (VF4_TPHR_CAP_ENABLE),
.VF4_TPHR_CAP_INT_VEC_MODE (VF4_TPHR_CAP_INT_VEC_MODE),
.VF4_TPHR_CAP_NEXTPTR (VF4_TPHR_CAP_NEXTPTR),
.VF4_TPHR_CAP_ST_MODE_SEL (VF4_TPHR_CAP_ST_MODE_SEL),
.VF4_TPHR_CAP_ST_TABLE_LOC (VF4_TPHR_CAP_ST_TABLE_LOC),
.VF4_TPHR_CAP_ST_TABLE_SIZE (VF4_TPHR_CAP_ST_TABLE_SIZE),
.VF4_TPHR_CAP_VER (VF4_TPHR_CAP_VER),
.VF5_TPHR_CAP_DEV_SPECIFIC_MODE (VF5_TPHR_CAP_DEV_SPECIFIC_MODE),
.VF5_TPHR_CAP_ENABLE (VF5_TPHR_CAP_ENABLE),
.VF5_TPHR_CAP_INT_VEC_MODE (VF5_TPHR_CAP_INT_VEC_MODE),
.VF5_TPHR_CAP_NEXTPTR (VF5_TPHR_CAP_NEXTPTR),
.VF5_TPHR_CAP_ST_MODE_SEL (VF5_TPHR_CAP_ST_MODE_SEL),
.VF5_TPHR_CAP_ST_TABLE_LOC (VF5_TPHR_CAP_ST_TABLE_LOC),
.VF5_TPHR_CAP_ST_TABLE_SIZE (VF5_TPHR_CAP_ST_TABLE_SIZE),
.VF5_TPHR_CAP_VER (VF5_TPHR_CAP_VER),
.PF0_DPA_CAP_SUB_STATE_CONTROL ( PF0_DPA_CAP_SUB_STATE_CONTROL ),
.PF0_DPA_CAP_SUB_STATE_CONTROL_EN ( PF0_DPA_CAP_SUB_STATE_CONTROL_EN ),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 ( PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 ),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 ( PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 ),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 ( PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 ),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 ( PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 ),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 ( PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 ),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 ( PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 ),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 ( PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 ),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 ( PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 ),
.PF0_DPA_CAP_VER ( PF0_DPA_CAP_VER ),
.PF0_DSN_CAP_NEXTPTR ( PF0_DSN_CAP_NEXTPTR ),
.PF0_EXPANSION_ROM_APERTURE_SIZE ( PF0_EXPANSION_ROM_APERTURE_SIZE ),
.PF0_EXPANSION_ROM_ENABLE ( PF0_EXPANSION_ROM_ENABLE ),
.PF0_INTERRUPT_LINE ( PF0_INTERRUPT_LINE ),
.PF0_INTERRUPT_PIN ( PF0_INTERRUPT_PIN ),
.PF0_LINK_CAP_ASPM_SUPPORT ( PF0_LINK_CAP_ASPM_SUPPORT ),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ( PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 ),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ( PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 ),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 ( PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 ),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 ( PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 ),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 ( PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 ),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 ( PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 ),
.PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ( PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 ),
.PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ( PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 ),
.PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 ( PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 ),
.PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 ( PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 ),
.PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 ( PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 ),
.PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 ( PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 ),
.PF0_LINK_STATUS_SLOT_CLOCK_CONFIG ( PF0_LINK_STATUS_SLOT_CLOCK_CONFIG ),
.PF0_LTR_CAP_MAX_NOSNOOP_LAT ( PF0_LTR_CAP_MAX_NOSNOOP_LAT ),
.PF0_LTR_CAP_MAX_SNOOP_LAT ( PF0_LTR_CAP_MAX_SNOOP_LAT ),
.PF0_LTR_CAP_NEXTPTR ( PF0_LTR_CAP_NEXTPTR ),
.PF0_LTR_CAP_VER ( PF0_LTR_CAP_VER ),
.PF0_MSIX_CAP_NEXTPTR ( PF0_MSIX_CAP_NEXTPTR ),
.PF0_MSIX_CAP_PBA_BIR ( PF0_MSIX_CAP_PBA_BIR ),
.PF0_MSIX_CAP_PBA_OFFSET ( PF0_MSIX_CAP_PBA_OFFSET ),
.PF0_MSIX_CAP_TABLE_BIR ( PF0_MSIX_CAP_TABLE_BIR ),
.PF0_MSIX_CAP_TABLE_OFFSET ( PF0_MSIX_CAP_TABLE_OFFSET ),
.PF0_MSIX_CAP_TABLE_SIZE ( PF0_MSIX_CAP_TABLE_SIZE ),
.PF0_MSI_CAP_MULTIMSGCAP ( PF0_MSI_CAP_MULTIMSGCAP ),
.PF0_MSI_CAP_NEXTPTR ( PF0_MSI_CAP_NEXTPTR ),
.PF0_PB_CAP_NEXTPTR ( PF0_PB_CAP_NEXTPTR ),
.PF0_PB_CAP_SYSTEM_ALLOCATED ( PF0_PB_CAP_SYSTEM_ALLOCATED ),
.PF0_PB_CAP_VER ( PF0_PB_CAP_VER ),
.PF0_PM_CAP_ID ( PF0_PM_CAP_ID ),
.PF0_PM_CAP_NEXTPTR ( PF0_PM_CAP_NEXTPTR ),
.PF0_PM_CAP_PMESUPPORT_D0 ( PF0_PM_CAP_PMESUPPORT_D0 ),
.PF0_PM_CAP_PMESUPPORT_D1 ( PF0_PM_CAP_PMESUPPORT_D1 ),
.PF0_PM_CAP_PMESUPPORT_D3HOT ( PF0_PM_CAP_PMESUPPORT_D3HOT ),
.PF0_PM_CAP_SUPP_D1_STATE ( PF0_PM_CAP_SUPP_D1_STATE ),
.PF0_PM_CAP_VER_ID ( PF0_PM_CAP_VER_ID ),
.PF0_PM_CSR_NOSOFTRESET ( PF0_PM_CSR_NOSOFTRESET ),
.PF0_RBAR_CAP_ENABLE ( PF0_RBAR_CAP_ENABLE ),
.PF0_RBAR_CAP_INDEX0 ( PF0_RBAR_CAP_INDEX0 ),
.PF0_RBAR_CAP_INDEX1 ( PF0_RBAR_CAP_INDEX1 ),
.PF0_RBAR_CAP_INDEX2 ( PF0_RBAR_CAP_INDEX2 ),
.PF0_RBAR_CAP_NEXTPTR ( PF0_RBAR_CAP_NEXTPTR ),
.PF0_RBAR_CAP_SIZE0 ( PF0_RBAR_CAP_SIZE0 ),
.PF0_RBAR_CAP_SIZE1 ( PF0_RBAR_CAP_SIZE1 ),
.PF0_RBAR_CAP_SIZE2 ( PF0_RBAR_CAP_SIZE2 ),
.PF0_RBAR_CAP_VER ( PF0_RBAR_CAP_VER ),
.PF0_RBAR_NUM ( PF0_RBAR_NUM ),
.PF0_REVISION_ID ( PF0_REVISION_ID ),
.PF0_SRIOV_BAR0_APERTURE_SIZE ( PF0_SRIOV_BAR0_APERTURE_SIZE ),
.PF0_SRIOV_BAR0_CONTROL ( PF0_SRIOV_BAR0_CONTROL ),
.PF0_SRIOV_BAR1_APERTURE_SIZE ( PF0_SRIOV_BAR1_APERTURE_SIZE ),
.PF0_SRIOV_BAR1_CONTROL ( PF0_SRIOV_BAR1_CONTROL ),
.PF0_SRIOV_BAR2_APERTURE_SIZE ( PF0_SRIOV_BAR2_APERTURE_SIZE ),
.PF0_SRIOV_BAR2_CONTROL ( PF0_SRIOV_BAR2_CONTROL ),
.PF0_SRIOV_BAR3_APERTURE_SIZE ( PF0_SRIOV_BAR3_APERTURE_SIZE ),
.PF0_SRIOV_BAR3_CONTROL ( PF0_SRIOV_BAR3_CONTROL ),
.PF0_SRIOV_BAR4_APERTURE_SIZE ( PF0_SRIOV_BAR4_APERTURE_SIZE ),
.PF0_SRIOV_BAR4_CONTROL ( PF0_SRIOV_BAR4_CONTROL ),
.PF0_SRIOV_BAR5_APERTURE_SIZE ( PF0_SRIOV_BAR5_APERTURE_SIZE ),
.PF0_SRIOV_BAR5_CONTROL ( PF0_SRIOV_BAR5_CONTROL ),
.PF0_SRIOV_CAP_INITIAL_VF ( PF0_SRIOV_CAP_INITIAL_VF ),
.PF0_SRIOV_CAP_NEXTPTR ( PF0_SRIOV_CAP_NEXTPTR ),
.PF0_SRIOV_CAP_TOTAL_VF ( PF0_SRIOV_CAP_TOTAL_VF ),
.PF0_SRIOV_CAP_VER ( PF0_SRIOV_CAP_VER ),
.PF0_SRIOV_FIRST_VF_OFFSET ( PF0_SRIOV_FIRST_VF_OFFSET ),
.PF0_SRIOV_FUNC_DEP_LINK ( PF0_SRIOV_FUNC_DEP_LINK ),
.PF0_SRIOV_SUPPORTED_PAGE_SIZE ( PF0_SRIOV_SUPPORTED_PAGE_SIZE ),
.PF0_SRIOV_VF_DEVICE_ID ( PF0_SRIOV_VF_DEVICE_ID ),
.PF0_SUBSYSTEM_ID ( PF0_SUBSYSTEM_ID ),
.PF0_TPHR_CAP_DEV_SPECIFIC_MODE ( PF0_TPHR_CAP_DEV_SPECIFIC_MODE ),
.PF0_TPHR_CAP_ENABLE ( PF0_TPHR_CAP_ENABLE ),
.PF0_TPHR_CAP_INT_VEC_MODE ( PF0_TPHR_CAP_INT_VEC_MODE ),
.PF0_TPHR_CAP_NEXTPTR ( PF0_TPHR_CAP_NEXTPTR ),
.PF0_TPHR_CAP_ST_MODE_SEL ( PF0_TPHR_CAP_ST_MODE_SEL ),
.PF0_TPHR_CAP_ST_TABLE_LOC ( PF0_TPHR_CAP_ST_TABLE_LOC ),
.PF0_TPHR_CAP_ST_TABLE_SIZE ( PF0_TPHR_CAP_ST_TABLE_SIZE ),
.PF0_TPHR_CAP_VER ( PF0_TPHR_CAP_VER ),
.PF0_VC_CAP_NEXTPTR ( PF0_VC_CAP_NEXTPTR ),
.PF0_VC_CAP_VER ( PF0_VC_CAP_VER ),
.PF1_AER_CAP_ECRC_CHECK_CAPABLE ( PF1_AER_CAP_ECRC_CHECK_CAPABLE ),
.PF1_AER_CAP_ECRC_GEN_CAPABLE ( PF1_AER_CAP_ECRC_GEN_CAPABLE ),
.PF1_AER_CAP_NEXTPTR ( PF1_AER_CAP_NEXTPTR ),
.PF1_ARI_CAP_NEXTPTR ( PF1_ARI_CAP_NEXTPTR ),
.PF1_ARI_CAP_NEXT_FUNC ( PF1_ARI_CAP_NEXT_FUNC ),
.PF1_BAR0_APERTURE_SIZE ( PF1_BAR0_APERTURE_SIZE ),
.PF1_BAR0_CONTROL ( PF1_BAR0_CONTROL ),
.PF1_BAR1_APERTURE_SIZE ( PF1_BAR1_APERTURE_SIZE ),
.PF1_BAR1_CONTROL ( PF1_BAR1_CONTROL ),
.PF1_BAR2_APERTURE_SIZE ( PF1_BAR2_APERTURE_SIZE ),
.PF1_BAR2_CONTROL ( PF1_BAR2_CONTROL ),
.PF1_BAR3_APERTURE_SIZE ( PF1_BAR3_APERTURE_SIZE ),
.PF1_BAR3_CONTROL ( PF1_BAR3_CONTROL ),
.PF1_BAR4_APERTURE_SIZE ( PF1_BAR4_APERTURE_SIZE ),
.PF1_BAR4_CONTROL ( PF1_BAR4_CONTROL ),
.PF1_BAR5_APERTURE_SIZE ( PF1_BAR5_APERTURE_SIZE ),
.PF1_BAR5_CONTROL ( PF1_BAR5_CONTROL ),
.PF1_BIST_REGISTER ( PF1_BIST_REGISTER ),
.PF1_CAPABILITY_POINTER ( PF1_CAPABILITY_POINTER ),
.PF1_CLASS_CODE ( PF1_CLASS_CODE ),
.PF1_DEVICE_ID ( PF1_DEVICE_ID ),
.PF1_DEV_CAP_MAX_PAYLOAD_SIZE ( PF1_DEV_CAP_MAX_PAYLOAD_SIZE ),
.PF1_DPA_CAP_NEXTPTR ( PF1_DPA_CAP_NEXTPTR ),
.PF1_DPA_CAP_SUB_STATE_CONTROL ( PF1_DPA_CAP_SUB_STATE_CONTROL ),
.PF1_DPA_CAP_SUB_STATE_CONTROL_EN ( PF1_DPA_CAP_SUB_STATE_CONTROL_EN ),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 ( PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 ),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 ( PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 ),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 ( PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 ),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 ( PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 ),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 ( PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 ),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 ( PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 ),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 ( PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 ),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 ( PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 ),
.PF1_DPA_CAP_VER ( PF1_DPA_CAP_VER ),
.PF1_DSN_CAP_NEXTPTR ( PF1_DSN_CAP_NEXTPTR ),
.PF1_EXPANSION_ROM_APERTURE_SIZE ( PF1_EXPANSION_ROM_APERTURE_SIZE ),
.PF1_EXPANSION_ROM_ENABLE ( PF1_EXPANSION_ROM_ENABLE ),
.PF1_INTERRUPT_LINE ( PF1_INTERRUPT_LINE ),
.PF1_INTERRUPT_PIN ( PF1_INTERRUPT_PIN ),
.PF1_MSIX_CAP_NEXTPTR ( PF1_MSIX_CAP_NEXTPTR ),
.PF1_MSIX_CAP_PBA_BIR ( PF1_MSIX_CAP_PBA_BIR ),
.PF1_MSIX_CAP_PBA_OFFSET ( PF1_MSIX_CAP_PBA_OFFSET ),
.PF1_MSIX_CAP_TABLE_BIR ( PF1_MSIX_CAP_TABLE_BIR ),
.PF1_MSIX_CAP_TABLE_OFFSET ( PF1_MSIX_CAP_TABLE_OFFSET ),
.PF1_MSIX_CAP_TABLE_SIZE ( PF1_MSIX_CAP_TABLE_SIZE ),
.PF1_MSI_CAP_MULTIMSGCAP ( PF1_MSI_CAP_MULTIMSGCAP ),
.PF1_MSI_CAP_NEXTPTR ( PF1_MSI_CAP_NEXTPTR ),
.PF1_PB_CAP_NEXTPTR ( PF1_PB_CAP_NEXTPTR ),
.PF1_PB_CAP_SYSTEM_ALLOCATED ( PF1_PB_CAP_SYSTEM_ALLOCATED ),
.PF1_PB_CAP_VER ( PF1_PB_CAP_VER ),
.PF1_PM_CAP_ID ( PF1_PM_CAP_ID ),
.PF1_PM_CAP_NEXTPTR ( PF1_PM_CAP_NEXTPTR ),
.PF1_PM_CAP_VER_ID ( PF1_PM_CAP_VER_ID ),
.PF1_RBAR_CAP_ENABLE ( PF1_RBAR_CAP_ENABLE ),
.PF1_RBAR_CAP_INDEX0 ( PF1_RBAR_CAP_INDEX0 ),
.PF1_RBAR_CAP_INDEX1 ( PF1_RBAR_CAP_INDEX1 ),
.PF1_RBAR_CAP_INDEX2 ( PF1_RBAR_CAP_INDEX2 ),
.PF1_RBAR_CAP_NEXTPTR ( PF1_RBAR_CAP_NEXTPTR ),
.PF1_RBAR_CAP_SIZE0 ( PF1_RBAR_CAP_SIZE0 ),
.PF1_RBAR_CAP_SIZE1 ( PF1_RBAR_CAP_SIZE1 ),
.PF1_RBAR_CAP_SIZE2 ( PF1_RBAR_CAP_SIZE2 ),
.PF1_RBAR_CAP_VER ( PF1_RBAR_CAP_VER ),
.PF1_RBAR_NUM ( PF1_RBAR_NUM ),
.PF1_REVISION_ID ( PF1_REVISION_ID ),
.PF1_SRIOV_BAR0_APERTURE_SIZE ( PF1_SRIOV_BAR0_APERTURE_SIZE ),
.PF1_SRIOV_BAR0_CONTROL ( PF1_SRIOV_BAR0_CONTROL ),
.PF1_SRIOV_BAR1_APERTURE_SIZE ( PF1_SRIOV_BAR1_APERTURE_SIZE ),
.PF1_SRIOV_BAR1_CONTROL ( PF1_SRIOV_BAR1_CONTROL ),
.PF1_SRIOV_BAR2_APERTURE_SIZE ( PF1_SRIOV_BAR2_APERTURE_SIZE ),
.PF1_SRIOV_BAR2_CONTROL ( PF1_SRIOV_BAR2_CONTROL ),
.PF1_SRIOV_BAR3_APERTURE_SIZE ( PF1_SRIOV_BAR3_APERTURE_SIZE ),
.PF1_SRIOV_BAR3_CONTROL ( PF1_SRIOV_BAR3_CONTROL ),
.PF1_SRIOV_BAR4_APERTURE_SIZE ( PF1_SRIOV_BAR4_APERTURE_SIZE ),
.PF1_SRIOV_BAR4_CONTROL ( PF1_SRIOV_BAR4_CONTROL ),
.PF1_SRIOV_BAR5_APERTURE_SIZE ( PF1_SRIOV_BAR5_APERTURE_SIZE ),
.PF1_SRIOV_BAR5_CONTROL ( PF1_SRIOV_BAR5_CONTROL ),
.PF1_SRIOV_CAP_INITIAL_VF ( PF1_SRIOV_CAP_INITIAL_VF ),
.PF1_SRIOV_CAP_NEXTPTR ( PF1_SRIOV_CAP_NEXTPTR ),
.PF1_SRIOV_CAP_TOTAL_VF ( PF1_SRIOV_CAP_TOTAL_VF ),
.PF1_SRIOV_CAP_VER ( PF1_SRIOV_CAP_VER ),
.PF1_SRIOV_FIRST_VF_OFFSET ( PF1_SRIOV_FIRST_VF_OFFSET ),
.PF1_SRIOV_FUNC_DEP_LINK ( PF1_SRIOV_FUNC_DEP_LINK ),
.PF1_SRIOV_SUPPORTED_PAGE_SIZE ( PF1_SRIOV_SUPPORTED_PAGE_SIZE ),
.PF1_SRIOV_VF_DEVICE_ID ( PF1_SRIOV_VF_DEVICE_ID ),
.PF1_SUBSYSTEM_ID ( PF1_SUBSYSTEM_ID ),
.PF1_TPHR_CAP_DEV_SPECIFIC_MODE ( PF1_TPHR_CAP_DEV_SPECIFIC_MODE ),
.PF1_TPHR_CAP_ENABLE ( PF1_TPHR_CAP_ENABLE ),
.PF1_TPHR_CAP_INT_VEC_MODE ( PF1_TPHR_CAP_INT_VEC_MODE ),
.PF1_TPHR_CAP_NEXTPTR ( PF1_TPHR_CAP_NEXTPTR ),
.PF1_TPHR_CAP_ST_MODE_SEL ( PF1_TPHR_CAP_ST_MODE_SEL ),
.PF1_TPHR_CAP_ST_TABLE_LOC ( PF1_TPHR_CAP_ST_TABLE_LOC ),
.PF1_TPHR_CAP_ST_TABLE_SIZE ( PF1_TPHR_CAP_ST_TABLE_SIZE ),
.PF1_TPHR_CAP_VER ( PF1_TPHR_CAP_VER ),
.PL_DISABLE_EI_INFER_IN_L0 ( PL_DISABLE_EI_INFER_IN_L0 ),
.PL_DISABLE_GEN3_DC_BALANCE ( PL_DISABLE_GEN3_DC_BALANCE ),
.PL_DISABLE_SCRAMBLING ( PL_DISABLE_SCRAMBLING ),
.PL_DISABLE_UPCONFIG_CAPABLE ( PL_DISABLE_UPCONFIG_CAPABLE ),
.PL_EQ_ADAPT_DISABLE_COEFF_CHECK ( PL_EQ_ADAPT_DISABLE_COEFF_CHECK ),
.PL_EQ_ADAPT_DISABLE_PRESET_CHECK ( PL_EQ_ADAPT_DISABLE_PRESET_CHECK ),
.PL_EQ_ADAPT_ITER_COUNT ( PL_EQ_ADAPT_ITER_COUNT ),
.PL_EQ_ADAPT_REJECT_RETRY_COUNT ( PL_EQ_ADAPT_REJECT_RETRY_COUNT ),
.PL_EQ_BYPASS_PHASE23 ( PL_EQ_BYPASS_PHASE23 ),
.PL_EQ_SHORT_ADAPT_PHASE ( PL_EQ_SHORT_ADAPT_PHASE ),
.PL_LANE0_EQ_CONTROL ( PL_LANE0_EQ_CONTROL ),
.PL_LANE1_EQ_CONTROL ( PL_LANE1_EQ_CONTROL ),
.PL_LANE2_EQ_CONTROL ( PL_LANE2_EQ_CONTROL ),
.PL_LANE3_EQ_CONTROL ( PL_LANE3_EQ_CONTROL ),
.PL_LANE4_EQ_CONTROL ( PL_LANE4_EQ_CONTROL ),
.PL_LANE5_EQ_CONTROL ( PL_LANE5_EQ_CONTROL ),
.PL_LANE6_EQ_CONTROL ( PL_LANE6_EQ_CONTROL ),
.PL_LANE7_EQ_CONTROL ( PL_LANE7_EQ_CONTROL ),
.PL_LINK_CAP_MAX_LINK_SPEED ( PL_LINK_CAP_MAX_LINK_SPEED ),
.PL_LINK_CAP_MAX_LINK_WIDTH ( PL_LINK_CAP_MAX_LINK_WIDTH ),
.PL_N_FTS_COMCLK_GEN1 ( PL_N_FTS_COMCLK_GEN1 ),
.PL_N_FTS_COMCLK_GEN2 ( PL_N_FTS_COMCLK_GEN2 ),
.PL_N_FTS_COMCLK_GEN3 ( PL_N_FTS_COMCLK_GEN3 ),
.PL_N_FTS_GEN1 ( PL_N_FTS_GEN1 ),
.PL_N_FTS_GEN2 ( PL_N_FTS_GEN2 ),
.PL_N_FTS_GEN3 ( PL_N_FTS_GEN3 ),
.PL_SIM_FAST_LINK_TRAINING ( PL_SIM_FAST_LINK_TRAINING ),
.PL_UPSTREAM_FACING ( PL_UPSTREAM_FACING ),
.PM_ASPML0S_TIMEOUT ( PM_ASPML0S_TIMEOUT ),
.PM_ASPML1_ENTRY_DELAY ( PM_ASPML1_ENTRY_DELAY ),
.PM_ENABLE_SLOT_POWER_CAPTURE ( PM_ENABLE_SLOT_POWER_CAPTURE ),
.PM_L1_REENTRY_DELAY ( PM_L1_REENTRY_DELAY ),
.PM_PME_SERVICE_TIMEOUT_DELAY ( PM_PME_SERVICE_TIMEOUT_DELAY ),
.PM_PME_TURNOFF_ACK_DELAY ( PM_PME_TURNOFF_ACK_DELAY ),
.SIM_VERSION ( SIM_VERSION ),
.SPARE_BIT0 ( SPARE_BIT0 ),
.SPARE_BIT1 ( SPARE_BIT1 ),
.SPARE_BIT2 ( SPARE_BIT2 ),
.SPARE_BIT3 ( SPARE_BIT3 ),
.SPARE_BIT4 ( SPARE_BIT4 ),
.SPARE_BIT5 ( SPARE_BIT5 ),
.SPARE_BIT6 ( SPARE_BIT6 ),
.SPARE_BIT7 ( SPARE_BIT7 ),
.SPARE_BIT8 ( SPARE_BIT8 ),
.SPARE_BYTE0 ( SPARE_BYTE0 ),
.SPARE_BYTE1 ( SPARE_BYTE1 ),
.SPARE_BYTE2 ( SPARE_BYTE2 ),
.SPARE_BYTE3 ( SPARE_BYTE3 ),
.SPARE_WORD0 ( SPARE_WORD0 ),
.SPARE_WORD1 ( SPARE_WORD1 ),
.SPARE_WORD2 ( SPARE_WORD2 ),
.SPARE_WORD3 ( SPARE_WORD3 ),
.SRIOV_CAP_ENABLE ( SRIOV_CAP_ENABLE ),
.TL_COMPL_TIMEOUT_REG0 ( TL_COMPL_TIMEOUT_REG0 ),
.TL_COMPL_TIMEOUT_REG1 ( TL_COMPL_TIMEOUT_REG1 ),
.TL_CREDITS_CD ( TL_CREDITS_CD ),
.TL_CREDITS_CH ( TL_CREDITS_CH ),
.TL_CREDITS_NPD ( TL_CREDITS_NPD ),
.TL_CREDITS_NPH ( TL_CREDITS_NPH ),
.TL_CREDITS_PD ( TL_CREDITS_PD ),
.TL_CREDITS_PH ( TL_CREDITS_PH ),
.TL_ENABLE_MESSAGE_RID_CHECK_ENABLE ( TL_ENABLE_MESSAGE_RID_CHECK_ENABLE ),
.TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE ( TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE ),
.TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE ( TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE ),
.TL_LEGACY_MODE_ENABLE ( TL_LEGACY_MODE_ENABLE ),
.TL_PF_ENABLE_REG ( TL_PF_ENABLE_REG ),
.TL_TAG_MGMT_ENABLE ( TL_TAG_MGMT_ENABLE ),
.VF0_CAPABILITY_POINTER ( VF0_CAPABILITY_POINTER ),
.VF0_MSIX_CAP_PBA_BIR ( VF0_MSIX_CAP_PBA_BIR ),
.VF0_MSIX_CAP_PBA_OFFSET ( VF0_MSIX_CAP_PBA_OFFSET ),
.VF0_MSIX_CAP_TABLE_BIR ( VF0_MSIX_CAP_TABLE_BIR ),
.VF0_MSIX_CAP_TABLE_OFFSET ( VF0_MSIX_CAP_TABLE_OFFSET ),
.VF0_MSIX_CAP_TABLE_SIZE ( VF0_MSIX_CAP_TABLE_SIZE ),
.VF0_MSI_CAP_MULTIMSGCAP ( VF0_MSI_CAP_MULTIMSGCAP ),
.VF0_PM_CAP_ID ( VF0_PM_CAP_ID ),
.VF0_PM_CAP_NEXTPTR ( VF0_PM_CAP_NEXTPTR ),
.VF0_PM_CAP_VER_ID ( VF0_PM_CAP_VER_ID ),
.VF1_MSIX_CAP_PBA_BIR ( VF1_MSIX_CAP_PBA_BIR ),
.VF1_MSIX_CAP_PBA_OFFSET ( VF1_MSIX_CAP_PBA_OFFSET ),
.VF1_MSIX_CAP_TABLE_BIR ( VF1_MSIX_CAP_TABLE_BIR ),
.VF1_MSIX_CAP_TABLE_OFFSET ( VF1_MSIX_CAP_TABLE_OFFSET ),
.VF1_MSIX_CAP_TABLE_SIZE ( VF1_MSIX_CAP_TABLE_SIZE ),
.VF1_MSI_CAP_MULTIMSGCAP ( VF1_MSI_CAP_MULTIMSGCAP ),
.VF1_PM_CAP_ID ( VF1_PM_CAP_ID ),
.VF1_PM_CAP_NEXTPTR ( VF1_PM_CAP_NEXTPTR ),
.VF1_PM_CAP_VER_ID ( VF1_PM_CAP_VER_ID ),
.VF2_MSIX_CAP_PBA_BIR ( VF2_MSIX_CAP_PBA_BIR ),
.VF2_MSIX_CAP_PBA_OFFSET ( VF2_MSIX_CAP_PBA_OFFSET ),
.VF2_MSIX_CAP_TABLE_BIR ( VF2_MSIX_CAP_TABLE_BIR ),
.VF2_MSIX_CAP_TABLE_OFFSET ( VF2_MSIX_CAP_TABLE_OFFSET ),
.VF2_MSIX_CAP_TABLE_SIZE ( VF2_MSIX_CAP_TABLE_SIZE ),
.VF2_MSI_CAP_MULTIMSGCAP ( VF2_MSI_CAP_MULTIMSGCAP ),
.VF2_PM_CAP_ID ( VF2_PM_CAP_ID ),
.VF2_PM_CAP_NEXTPTR ( VF2_PM_CAP_NEXTPTR ),
.VF2_PM_CAP_VER_ID ( VF2_PM_CAP_VER_ID ),
.VF3_MSIX_CAP_PBA_BIR ( VF3_MSIX_CAP_PBA_BIR ),
.VF3_MSIX_CAP_PBA_OFFSET ( VF3_MSIX_CAP_PBA_OFFSET ),
.VF3_MSIX_CAP_TABLE_BIR ( VF3_MSIX_CAP_TABLE_BIR ),
.VF3_MSIX_CAP_TABLE_OFFSET ( VF3_MSIX_CAP_TABLE_OFFSET ),
.VF3_MSIX_CAP_TABLE_SIZE ( VF3_MSIX_CAP_TABLE_SIZE ),
.VF3_MSI_CAP_MULTIMSGCAP ( VF3_MSI_CAP_MULTIMSGCAP ),
.VF3_PM_CAP_ID ( VF3_PM_CAP_ID ),
.VF3_PM_CAP_NEXTPTR ( VF3_PM_CAP_NEXTPTR ),
.VF3_PM_CAP_VER_ID ( VF3_PM_CAP_VER_ID ),
.VF4_MSIX_CAP_PBA_BIR ( VF4_MSIX_CAP_PBA_BIR ),
.VF4_MSIX_CAP_PBA_OFFSET ( VF4_MSIX_CAP_PBA_OFFSET ),
.VF4_MSIX_CAP_TABLE_BIR ( VF4_MSIX_CAP_TABLE_BIR ),
.VF4_MSIX_CAP_TABLE_OFFSET ( VF4_MSIX_CAP_TABLE_OFFSET ),
.VF4_MSIX_CAP_TABLE_SIZE ( VF4_MSIX_CAP_TABLE_SIZE ),
.VF4_MSI_CAP_MULTIMSGCAP ( VF4_MSI_CAP_MULTIMSGCAP ),
.VF4_PM_CAP_ID ( VF4_PM_CAP_ID ),
.VF4_PM_CAP_NEXTPTR ( VF4_PM_CAP_NEXTPTR ),
.VF4_PM_CAP_VER_ID ( VF4_PM_CAP_VER_ID ),
.VF5_MSIX_CAP_PBA_BIR ( VF5_MSIX_CAP_PBA_BIR ),
.VF5_MSIX_CAP_PBA_OFFSET ( VF5_MSIX_CAP_PBA_OFFSET ),
.VF5_MSIX_CAP_TABLE_BIR ( VF5_MSIX_CAP_TABLE_BIR ),
.VF5_MSIX_CAP_TABLE_OFFSET ( VF5_MSIX_CAP_TABLE_OFFSET ),
.VF5_MSIX_CAP_TABLE_SIZE ( VF5_MSIX_CAP_TABLE_SIZE ),
.VF5_MSI_CAP_MULTIMSGCAP ( VF5_MSI_CAP_MULTIMSGCAP ),
.VF5_PM_CAP_ID ( VF5_PM_CAP_ID ),
.VF5_PM_CAP_NEXTPTR ( VF5_PM_CAP_NEXTPTR ),
.VF5_PM_CAP_VER_ID ( VF5_PM_CAP_VER_ID ),
.IMPL_TARGET ( IMPL_TARGET ),
.NO_DECODE_LOGIC ( NO_DECODE_LOGIC ),
.INTERFACE_SPEED ( INTERFACE_SPEED ),
.COMPLETION_SPACE ( COMPLETION_SPACE )
)
pcie_7vx_i(
.CFGERRCOROUT ( cfg_err_cor_out ),
.CFGERRFATALOUT ( cfg_err_fatal_out ),
.CFGERRNONFATALOUT ( cfg_err_nonfatal_out ),
.CFGEXTREADRECEIVED ( cfg_ext_read_received ),
.CFGEXTWRITERECEIVED ( cfg_ext_write_received ),
.CFGHOTRESETOUT ( cfg_hot_reset_out ),
.CFGINPUTUPDATEDONE ( cfg_input_update_done ),
.CFGINTERRUPTAOUTPUT ( ),
.CFGINTERRUPTBOUTPUT ( ),
.CFGINTERRUPTCOUTPUT ( ),
.CFGINTERRUPTDOUTPUT ( ),
.CFGINTERRUPTMSIFAIL ( cfg_interrupt_msi_fail ),
.CFGINTERRUPTMSIMASKUPDATE ( cfg_interrupt_msi_mask_update ),
.CFGINTERRUPTMSISENT ( cfg_interrupt_msi_sent ),
.CFGINTERRUPTMSIXFAIL ( cfg_interrupt_msix_fail ),
.CFGINTERRUPTMSIXSENT ( cfg_interrupt_msix_sent ),
.CFGINTERRUPTSENT ( cfg_interrupt_sent ),
.CFGLOCALERROR ( cfg_local_error ),
.CFGLTRENABLE ( cfg_ltr_enable ),
.CFGMCUPDATEDONE ( cfg_mc_update_done ),
.CFGMGMTREADWRITEDONE ( cfg_mgmt_read_write_done ),
.CFGMSGRECEIVED ( cfg_msg_received ),
.CFGMSGTRANSMITDONE ( cfg_msg_transmit_done ),
.CFGPERFUNCTIONUPDATEDONE ( cfg_per_function_update_done ),
.CFGPHYLINKDOWN ( cfg_phy_link_down ),
.CFGPLSTATUSCHANGE ( cfg_pl_status_change ),
.CFGPOWERSTATECHANGEINTERRUPT ( cfg_power_state_change_interrupt ),
.CFGTPHSTTREADENABLE ( cfg_tph_stt_read_enable ),
.CFGTPHSTTWRITEENABLE ( cfg_tph_stt_write_enable ),
.DRPRDY ( drp_rdy ),
.MAXISCQTLAST ( m_axis_cq_tlast ),
.MAXISCQTVALID ( m_axis_cq_tvalid ),
.MAXISRCTLAST ( m_axis_rc_tlast ),
.MAXISRCTVALID ( m_axis_rc_tvalid ),
.PCIERQSEQNUMVLD ( pcie_rq_seq_num_vld ),
.PCIERQTAGVLD ( pcie_rq_tag_vld ),
.PIPERX0POLARITY ( pipe_rx0_polarity ),
.PIPERX1POLARITY ( pipe_rx1_polarity ),
.PIPERX2POLARITY ( pipe_rx2_polarity ),
.PIPERX3POLARITY ( pipe_rx3_polarity ),
.PIPERX4POLARITY ( pipe_rx4_polarity ),
.PIPERX5POLARITY ( pipe_rx5_polarity ),
.PIPERX6POLARITY ( pipe_rx6_polarity ),
.PIPERX7POLARITY ( pipe_rx7_polarity ),
.PIPETX0COMPLIANCE ( pipe_tx0_compliance ),
.PIPETX1COMPLIANCE ( pipe_tx1_compliance ),
.PIPETX2COMPLIANCE ( pipe_tx2_compliance ),
.PIPETX3COMPLIANCE ( pipe_tx3_compliance ),
.PIPETX4COMPLIANCE ( pipe_tx4_compliance ),
.PIPETX5COMPLIANCE ( pipe_tx5_compliance ),
.PIPETX6COMPLIANCE ( pipe_tx6_compliance ),
.PIPETX7COMPLIANCE ( pipe_tx7_compliance ),
.PIPETXDEEMPH ( pipe_tx_deemph ),
.PIPETXRCVRDET ( pipe_tx_rcvr_det ),
.PIPETXRESET ( pipe_tx_reset ),
.PIPETXSWING ( pipe_tx_swing ),
.PLEQINPROGRESS ( ),
.CFGFCCPLD ( cfg_fc_cpld ),
.CFGFCNPD ( cfg_fc_npd ),
.CFGFCPD ( cfg_fc_pd ),
.CFGVFSTATUS ( cfg_vf_status ),
.CFGPERFUNCSTATUSDATA ( cfg_per_func_status_data ),
.DBGDATAOUT ( ),
.DRPDO ( drp_do ),
.CFGVFPOWERSTATE ( cfg_vf_power_state ),
.CFGVFTPHSTMODE ( cfg_vf_tph_st_mode ),
.CFGDPASUBSTATECHANGE ( cfg_dpa_substate_change ),
.CFGFLRINPROCESS ( cfg_flr_in_process ),
.CFGINTERRUPTMSIENABLE ( cfg_interrupt_msi_enable ),
.CFGINTERRUPTMSIXENABLE ( cfg_interrupt_msix_enable ),
.CFGINTERRUPTMSIXMASK ( cfg_interrupt_msix_mask ),
.CFGLINKPOWERSTATE ( cfg_link_power_state ),
.CFGOBFFENABLE ( cfg_obff_enable ),
.CFGPHYLINKSTATUS ( cfg_phy_link_status ),
.CFGRCBSTATUS ( cfg_rcb_status ),
.CFGTPHREQUESTERENABLE ( cfg_tph_requester_enable ),
.PCIETFCNPDAV ( pcie_tfc_npd_av ),
.PCIETFCNPHAV ( pcie_tfc_nph_av ),
.PIPERX0EQCONTROL ( pipe_rx0_eqcontrol_pcie ),
.PIPERX1EQCONTROL ( pipe_rx1_eqcontrol_pcie ),
.PIPERX2EQCONTROL ( pipe_rx2_eqcontrol_pcie ),
.PIPERX3EQCONTROL ( pipe_rx3_eqcontrol_pcie ),
.PIPERX4EQCONTROL ( pipe_rx4_eqcontrol_pcie ),
.PIPERX5EQCONTROL ( pipe_rx5_eqcontrol_pcie ),
.PIPERX6EQCONTROL ( pipe_rx6_eqcontrol_pcie ),
.PIPERX7EQCONTROL ( pipe_rx7_eqcontrol_pcie ),
.PIPETX0CHARISK ( pipe_tx0_char_is_k ),
.PIPETX0EQCONTROL ( pipe_tx0_eqcontrol ),
.PIPETX0POWERDOWN ( pipe_tx0_powerdown ),
.PIPETX0SYNCHEADER ( pipe_tx0_syncheader ),
.PIPETX1CHARISK ( pipe_tx1_char_is_k ),
.PIPETX1EQCONTROL ( pipe_tx1_eqcontrol ),
.PIPETX1POWERDOWN ( pipe_tx1_powerdown ),
.PIPETX1SYNCHEADER ( pipe_tx1_syncheader ),
.PIPETX2CHARISK ( pipe_tx2_char_is_k ),
.PIPETX2EQCONTROL ( pipe_tx2_eqcontrol ),
.PIPETX2POWERDOWN ( pipe_tx2_powerdown ),
.PIPETX2SYNCHEADER ( pipe_tx2_syncheader ),
.PIPETX3CHARISK ( pipe_tx3_char_is_k ),
.PIPETX3EQCONTROL ( pipe_tx3_eqcontrol ),
.PIPETX3POWERDOWN ( pipe_tx3_powerdown ),
.PIPETX3SYNCHEADER ( pipe_tx3_syncheader ),
.PIPETX4CHARISK ( pipe_tx4_char_is_k ),
.PIPETX4EQCONTROL ( pipe_tx4_eqcontrol ),
.PIPETX4POWERDOWN ( pipe_tx4_powerdown ),
.PIPETX4SYNCHEADER ( pipe_tx4_syncheader ),
.PIPETX5CHARISK ( pipe_tx5_char_is_k ),
.PIPETX5EQCONTROL ( pipe_tx5_eqcontrol ),
.PIPETX5POWERDOWN ( pipe_tx5_powerdown ),
.PIPETX5SYNCHEADER ( pipe_tx5_syncheader ),
.PIPETX6CHARISK ( pipe_tx6_char_is_k ),
.PIPETX6EQCONTROL ( pipe_tx6_eqcontrol ),
.PIPETX6POWERDOWN ( pipe_tx6_powerdown ),
.PIPETX6SYNCHEADER ( pipe_tx6_syncheader ),
.PIPETX7CHARISK ( pipe_tx7_char_is_k ),
.PIPETX7EQCONTROL ( pipe_tx7_eqcontrol ),
.PIPETX7POWERDOWN ( pipe_tx7_powerdown ),
.PIPETX7SYNCHEADER ( pipe_tx7_syncheader ),
.PIPETXRATE ( pipe_tx_rate ),
.PLEQPHASE ( ),
.MAXISCQTDATA ( m_axis_cq_tdata_256 ),
.MAXISRCTDATA ( m_axis_rc_tdata_256 ),
.CFGCURRENTSPEED ( cfg_current_speed ),
.CFGMAXPAYLOAD ( cfg_max_payload ),
.CFGMAXREADREQ ( cfg_max_read_req ),
.CFGTPHFUNCTIONNUM ( cfg_tph_function_num ),
.PIPERX0EQPRESET ( pipe_rx0_eqpreset ),
.PIPERX1EQPRESET ( pipe_rx1_eqpreset ),
.PIPERX2EQPRESET ( pipe_rx2_eqpreset ),
.PIPERX3EQPRESET ( pipe_rx3_eqpreset ),
.PIPERX4EQPRESET ( pipe_rx4_eqpreset ),
.PIPERX5EQPRESET ( pipe_rx5_eqpreset ),
.PIPERX6EQPRESET ( pipe_rx6_eqpreset ),
.PIPERX7EQPRESET ( pipe_rx7_eqpreset ),
.PIPETXMARGIN ( pipe_tx_margin ),
.CFGEXTWRITEDATA ( cfg_ext_write_data ),
.CFGINTERRUPTMSIDATA ( cfg_interrupt_msi_data ),
.CFGMGMTREADDATA ( cfg_mgmt_read_data ),
.CFGTPHSTTWRITEDATA ( cfg_tph_stt_write_data ),
.PIPETX0DATA ( pipe_tx0_data ),
.PIPETX1DATA ( pipe_tx1_data ),
.PIPETX2DATA ( pipe_tx2_data ),
.PIPETX3DATA ( pipe_tx3_data ),
.PIPETX4DATA ( pipe_tx4_data ),
.PIPETX5DATA ( pipe_tx5_data ),
.PIPETX6DATA ( pipe_tx6_data ),
.PIPETX7DATA ( pipe_tx7_data ),
.PIPETX0DATAVALID ( pipe_tx0_data_valid ),
.PIPETX1DATAVALID ( pipe_tx1_data_valid ),
.PIPETX2DATAVALID ( pipe_tx2_data_valid ),
.PIPETX3DATAVALID ( pipe_tx3_data_valid ),
.PIPETX4DATAVALID ( pipe_tx4_data_valid ),
.PIPETX5DATAVALID ( pipe_tx5_data_valid ),
.PIPETX6DATAVALID ( pipe_tx6_data_valid ),
.PIPETX7DATAVALID ( pipe_tx7_data_valid ),
.PIPETX0ELECIDLE ( pipe_tx0_elec_idle ),
.PIPETX1ELECIDLE ( pipe_tx1_elec_idle ),
.PIPETX2ELECIDLE ( pipe_tx2_elec_idle ),
.PIPETX3ELECIDLE ( pipe_tx3_elec_idle ),
.PIPETX4ELECIDLE ( pipe_tx4_elec_idle ),
.PIPETX5ELECIDLE ( pipe_tx5_elec_idle ),
.PIPETX6ELECIDLE ( pipe_tx6_elec_idle ),
.PIPETX7ELECIDLE ( pipe_tx7_elec_idle ),
.PIPETX0STARTBLOCK ( pipe_tx0_start_block ),
.PIPETX1STARTBLOCK ( pipe_tx1_start_block ),
.PIPETX2STARTBLOCK ( pipe_tx2_start_block ),
.PIPETX3STARTBLOCK ( pipe_tx3_start_block ),
.PIPETX4STARTBLOCK ( pipe_tx4_start_block ),
.PIPETX5STARTBLOCK ( pipe_tx5_start_block ),
.PIPETX6STARTBLOCK ( pipe_tx6_start_block ),
.PIPETX7STARTBLOCK ( pipe_tx7_start_block ),
.CFGEXTWRITEBYTEENABLE ( cfg_ext_write_byte_enable ),
.CFGNEGOTIATEDWIDTH ( cfg_negotiated_width ),
.CFGTPHSTTWRITEBYTEVALID ( cfg_tph_stt_write_byte_valid ),
.PCIERQSEQNUM ( pcie_rq_seq_num ),
.PIPERX0EQLPTXPRESET ( pipe_rx0_eqlp_txpreset ),
.PIPERX1EQLPTXPRESET ( pipe_rx1_eqlp_txpreset ),
.PIPERX2EQLPTXPRESET ( pipe_rx2_eqlp_txpreset ),
.PIPERX3EQLPTXPRESET ( pipe_rx3_eqlp_txpreset ),
.PIPERX4EQLPTXPRESET ( pipe_rx4_eqlp_txpreset ),
.PIPERX5EQLPTXPRESET ( pipe_rx5_eqlp_txpreset ),
.PIPERX6EQLPTXPRESET ( pipe_rx6_eqlp_txpreset ),
.PIPERX7EQLPTXPRESET ( pipe_rx7_eqlp_txpreset ),
.PIPETX0EQPRESET ( pipe_tx0_eqpreset ),
.PIPETX1EQPRESET ( pipe_tx1_eqpreset ),
.PIPETX2EQPRESET ( pipe_tx2_eqpreset ),
.PIPETX3EQPRESET ( pipe_tx3_eqpreset ),
.PIPETX4EQPRESET ( pipe_tx4_eqpreset ),
.PIPETX5EQPRESET ( pipe_tx5_eqpreset ),
.PIPETX6EQPRESET ( pipe_tx6_eqpreset ),
.PIPETX7EQPRESET ( pipe_tx7_eqpreset ),
.SAXISCCTREADY ( s_axis_cc_tready ),
.SAXISRQTREADY ( s_axis_rq_tready ),
.CFGMSGRECEIVEDTYPE ( cfg_msg_received_type ),
.CFGTPHSTTADDRESS ( cfg_tph_stt_address ),
.CFGFUNCTIONPOWERSTATE ( cfg_function_power_state ),
.CFGINTERRUPTMSIMMENABLE ( cfg_interrupt_msi_mmenable ),
.CFGINTERRUPTMSIVFENABLE ( cfg_interrupt_msi_vf_enable ),
.CFGINTERRUPTMSIXVFENABLE ( cfg_interrupt_msix_vf_enable ),
.CFGINTERRUPTMSIXVFMASK ( cfg_interrupt_msix_vf_mask ),
.CFGLTSSMSTATE ( cfg_ltssm_state ),
.CFGTPHSTMODE ( cfg_tph_st_mode ),
.CFGVFFLRINPROCESS ( cfg_vf_flr_in_process ),
.CFGVFTPHREQUESTERENABLE ( cfg_vf_tph_requester_enable ),
.PCIECQNPREQCOUNT ( pcie_cq_np_req_count ),
.PCIERQTAG ( pcie_rq_tag ),
.PIPERX0EQLPLFFS ( pipe_rx0_eqlp_lffs ),
.PIPERX1EQLPLFFS ( pipe_rx1_eqlp_lffs ),
.PIPERX2EQLPLFFS ( pipe_rx2_eqlp_lffs ),
.PIPERX3EQLPLFFS ( pipe_rx3_eqlp_lffs ),
.PIPERX4EQLPLFFS ( pipe_rx4_eqlp_lffs ),
.PIPERX5EQLPLFFS ( pipe_rx5_eqlp_lffs ),
.PIPERX6EQLPLFFS ( pipe_rx6_eqlp_lffs ),
.PIPERX7EQLPLFFS ( pipe_rx7_eqlp_lffs ),
.PIPETX0EQDEEMPH ( pipe_tx0_eqdeemph ),
.PIPETX1EQDEEMPH ( pipe_tx1_eqdeemph ),
.PIPETX2EQDEEMPH ( pipe_tx2_eqdeemph ),
.PIPETX3EQDEEMPH ( pipe_tx3_eqdeemph ),
.PIPETX4EQDEEMPH ( pipe_tx4_eqdeemph ),
.PIPETX5EQDEEMPH ( pipe_tx5_eqdeemph ),
.PIPETX6EQDEEMPH ( pipe_tx6_eqdeemph ),
.PIPETX7EQDEEMPH ( pipe_tx7_eqdeemph ),
.MAXISRCTUSER ( m_axis_rc_tuser ),
.CFGEXTFUNCTIONNUMBER ( cfg_ext_function_number ),
.CFGFCCPLH ( cfg_fc_cplh ),
.CFGFCNPH ( cfg_fc_nph ),
.CFGFCPH ( cfg_fc_ph ),
.CFGFUNCTIONSTATUS ( cfg_function_status ),
.CFGMSGRECEIVEDDATA ( cfg_msg_received_data ),
.MAXISCQTKEEP ( m_axis_cq_tkeep_w ),
.MAXISRCTKEEP ( m_axis_rc_tkeep_w ),
.PLGEN3PCSRXSLIDE ( pipe_rx_slide ),
.MAXISCQTUSER ( m_axis_cq_tuser ),
.CFGEXTREGISTERNUMBER ( cfg_ext_register_number ),
.CFGCONFIGSPACEENABLE ( cfg_config_space_enable ),
.CFGERRCORIN ( cfg_err_cor_in ),
.CFGERRUNCORIN ( cfg_err_uncor_in ),
.CFGEXTREADDATAVALID ( cfg_ext_read_data_valid ),
.CFGHOTRESETIN ( cfg_hot_reset_in ),
.CFGINPUTUPDATEREQUEST ( cfg_input_update_request ),
.CFGINTERRUPTMSITPHPRESENT ( cfg_interrupt_msi_tph_present ),
.CFGINTERRUPTMSIXINT ( cfg_interrupt_msix_int ),
.CFGLINKTRAININGENABLE ( cfg_link_training_enable ),
.CFGMCUPDATEREQUEST ( cfg_mc_update_request ),
.CFGMGMTREAD ( cfg_mgmt_read ),
.CFGMGMTTYPE1CFGREGACCESS ( cfg_mgmt_type1_cfg_reg_access ),
.CFGMGMTWRITE ( cfg_mgmt_write ),
.CFGMSGTRANSMIT ( cfg_msg_transmit ),
.CFGPERFUNCTIONOUTPUTREQUEST ( cfg_per_function_output_request ),
.CFGPOWERSTATECHANGEACK ( cfg_power_state_change_ack ),
.CFGREQPMTRANSITIONL23READY ( cfg_req_pm_transition_l23_ready ),
.CFGTPHSTTREADDATAVALID ( cfg_tph_stt_read_data_valid ),
.CORECLK ( core_clk ), // 250MHz for 5.0GT/s. 500MHz for 8.0GT/s
.CORECLKMICOMPLETIONRAML ( core_clk ),
.CORECLKMICOMPLETIONRAMU ( core_clk ),
.CORECLKMIREPLAYRAM ( core_clk ),
.CORECLKMIREQUESTRAM ( core_clk ),
.DRPCLK ( drp_clk ),
.DRPEN ( drp_en ),
.DRPWE ( drp_we ),
.MGMTRESETN ( mgmt_reset_n ),
.MGMTSTICKYRESETN ( mgmt_sticky_reset_n ),
.PCIECQNPREQ ( pcie_cq_np_req ),
.PIPECLK ( pipe_clk ),
.PIPERESETN ( pipe_reset_n ),
.PIPERX0DATAVALID ( pipe_rx0_data_valid ),
.PIPERX0ELECIDLE ( pipe_rx0_elec_idle ),
.PIPERX0EQDONE ( pipe_rx0_eqdone ),
.PIPERX0EQLPADAPTDONE ( pipe_rx0_eqlp_adaptdone ),
.PIPERX0EQLPLFFSSEL ( pipe_rx0_eqlp_lffs_sel ),
.PIPERX0PHYSTATUS ( pipe_rx0_phy_status ),
.PIPERX0STARTBLOCK ( pipe_rx0_start_block ),
.PIPERX0VALID ( pipe_rx0_valid ),
.PIPERX1DATAVALID ( pipe_rx1_data_valid ),
.PIPERX1ELECIDLE ( pipe_rx1_elec_idle ),
.PIPERX1EQDONE ( pipe_rx1_eqdone ),
.PIPERX1EQLPADAPTDONE ( pipe_rx1_eqlp_adaptdone ),
.PIPERX1EQLPLFFSSEL ( pipe_rx1_eqlp_lffs_sel ),
.PIPERX1PHYSTATUS ( pipe_rx1_phy_status ),
.PIPERX1STARTBLOCK ( pipe_rx1_start_block ),
.PIPERX1VALID ( pipe_rx1_valid ),
.PIPERX2DATAVALID ( pipe_rx2_data_valid ),
.PIPERX2ELECIDLE ( pipe_rx2_elec_idle ),
.PIPERX2EQDONE ( pipe_rx2_eqdone ),
.PIPERX2EQLPADAPTDONE ( pipe_rx2_eqlp_adaptdone ),
.PIPERX2EQLPLFFSSEL ( pipe_rx2_eqlp_lffs_sel ),
.PIPERX2PHYSTATUS ( pipe_rx2_phy_status ),
.PIPERX2STARTBLOCK ( pipe_rx2_start_block ),
.PIPERX2VALID ( pipe_rx2_valid ),
.PIPERX3DATAVALID ( pipe_rx3_data_valid ),
.PIPERX3ELECIDLE ( pipe_rx3_elec_idle ),
.PIPERX3EQDONE ( pipe_rx3_eqdone ),
.PIPERX3EQLPADAPTDONE ( pipe_rx3_eqlp_adaptdone ),
.PIPERX3EQLPLFFSSEL ( pipe_rx3_eqlp_lffs_sel ),
.PIPERX3PHYSTATUS ( pipe_rx3_phy_status ),
.PIPERX3STARTBLOCK ( pipe_rx3_start_block ),
.PIPERX3VALID ( pipe_rx3_valid ),
.PIPERX4DATAVALID ( pipe_rx4_data_valid ),
.PIPERX4ELECIDLE ( pipe_rx4_elec_idle ),
.PIPERX4EQDONE ( pipe_rx4_eqdone ),
.PIPERX4EQLPADAPTDONE ( pipe_rx4_eqlp_adaptdone ),
.PIPERX4EQLPLFFSSEL ( pipe_rx4_eqlp_lffs_sel ),
.PIPERX4PHYSTATUS ( pipe_rx4_phy_status ),
.PIPERX4STARTBLOCK ( pipe_rx4_start_block ),
.PIPERX4VALID ( pipe_rx4_valid ),
.PIPERX5DATAVALID ( pipe_rx5_data_valid ),
.PIPERX5ELECIDLE ( pipe_rx5_elec_idle ),
.PIPERX5EQDONE ( pipe_rx5_eqdone ),
.PIPERX5EQLPADAPTDONE ( pipe_rx5_eqlp_adaptdone ),
.PIPERX5EQLPLFFSSEL ( pipe_rx5_eqlp_lffs_sel ),
.PIPERX5PHYSTATUS ( pipe_rx5_phy_status ),
.PIPERX5STARTBLOCK ( pipe_rx5_start_block ),
.PIPERX5VALID ( pipe_rx5_valid ),
.PIPERX6DATAVALID ( pipe_rx6_data_valid ),
.PIPERX6ELECIDLE ( pipe_rx6_elec_idle ),
.PIPERX6EQDONE ( pipe_rx6_eqdone ),
.PIPERX6EQLPADAPTDONE ( pipe_rx6_eqlp_adaptdone ),
.PIPERX6EQLPLFFSSEL ( pipe_rx6_eqlp_lffs_sel ),
.PIPERX6PHYSTATUS ( pipe_rx6_phy_status ),
.PIPERX6STARTBLOCK ( pipe_rx6_start_block ),
.PIPERX6VALID ( pipe_rx6_valid ),
.PIPERX7DATAVALID ( pipe_rx7_data_valid ),
.PIPERX7ELECIDLE ( pipe_rx7_elec_idle ),
.PIPERX7EQDONE ( pipe_rx7_eqdone ),
.PIPERX7EQLPADAPTDONE ( pipe_rx7_eqlp_adaptdone ),
.PIPERX7EQLPLFFSSEL ( pipe_rx7_eqlp_lffs_sel ),
.PIPERX7PHYSTATUS ( pipe_rx7_phy_status ),
.PIPERX7STARTBLOCK ( pipe_rx7_start_block ),
.PIPERX7VALID ( pipe_rx7_valid ),
.PIPETX0EQDONE ( pipe_tx0_eqdone ),
.PIPETX1EQDONE ( pipe_tx1_eqdone ),
.PIPETX2EQDONE ( pipe_tx2_eqdone ),
.PIPETX3EQDONE ( pipe_tx3_eqdone ),
.PIPETX4EQDONE ( pipe_tx4_eqdone ),
.PIPETX5EQDONE ( pipe_tx5_eqdone ),
.PIPETX6EQDONE ( pipe_tx6_eqdone ),
.PIPETX7EQDONE ( pipe_tx7_eqdone ),
.PLDISABLESCRAMBLER ( 1'b0 ),
.PLEQRESETEIEOSCOUNT ( 1'b0 ),
.PLGEN3PCSDISABLE ( gen3pcsdisable ),
.RECCLK ( rec_clk ),
.RESETN ( reset_n ),
.SAXISCCTLAST ( s_axis_cc_tlast ),
.SAXISCCTVALID ( s_axis_cc_tvalid ),
.SAXISRQTLAST ( s_axis_rq_tlast ),
.SAXISRQTVALID ( s_axis_rq_tvalid ),
.USERCLK ( user_clk ),
.DRPADDR ( drp_addr ),
.CFGDEVID ( cfg_dev_id ),
.CFGSUBSYSID ( cfg_subsys_id ),
.CFGSUBSYSVENDID ( cfg_subsys_vend_id ),
.CFGVENDID ( cfg_vend_id ),
.DRPDI ( drp_di ),
.PIPERX0EQLPNEWTXCOEFFORPRESET ( pipe_rx0_eqlp_new_txcoef_forpreset ),
.PIPERX1EQLPNEWTXCOEFFORPRESET ( pipe_rx1_eqlp_new_txcoef_forpreset ),
.PIPERX2EQLPNEWTXCOEFFORPRESET ( pipe_rx2_eqlp_new_txcoef_forpreset ),
.PIPERX3EQLPNEWTXCOEFFORPRESET ( pipe_rx3_eqlp_new_txcoef_forpreset ),
.PIPERX4EQLPNEWTXCOEFFORPRESET ( pipe_rx4_eqlp_new_txcoef_forpreset ),
.PIPERX5EQLPNEWTXCOEFFORPRESET ( pipe_rx5_eqlp_new_txcoef_forpreset ),
.PIPERX6EQLPNEWTXCOEFFORPRESET ( pipe_rx6_eqlp_new_txcoef_forpreset ),
.PIPERX7EQLPNEWTXCOEFFORPRESET ( pipe_rx7_eqlp_new_txcoef_forpreset ),
.PIPETX0EQCOEFF ( pipe_tx0_eqcoeff ),
.PIPETX1EQCOEFF ( pipe_tx1_eqcoeff ),
.PIPETX2EQCOEFF ( pipe_tx2_eqcoeff ),
.PIPETX3EQCOEFF ( pipe_tx3_eqcoeff ),
.PIPETX4EQCOEFF ( pipe_tx4_eqcoeff ),
.PIPETX5EQCOEFF ( pipe_tx5_eqcoeff ),
.PIPETX6EQCOEFF ( pipe_tx6_eqcoeff ),
.PIPETX7EQCOEFF ( pipe_tx7_eqcoeff ),
.CFGMGMTADDR ( cfg_mgmt_addr ),
.CFGFLRDONE ( cfg_flr_done ),
.CFGINTERRUPTMSITPHTYPE ( cfg_interrupt_msi_tph_type ),
.CFGINTERRUPTPENDING ( cfg_interrupt_pending ),
.PIPERX0CHARISK ( pipe_rx0_char_is_k ),
.PIPERX0SYNCHEADER ( pipe_rx0_syncheader ),
.PIPERX1CHARISK ( pipe_rx1_char_is_k ),
.PIPERX1SYNCHEADER ( pipe_rx1_syncheader ),
.PIPERX2CHARISK ( pipe_rx2_char_is_k ),
.PIPERX2SYNCHEADER ( pipe_rx2_syncheader ),
.PIPERX3CHARISK ( pipe_rx3_char_is_k ),
.PIPERX3SYNCHEADER ( pipe_rx3_syncheader ),
.PIPERX4CHARISK ( pipe_rx4_char_is_k ),
.PIPERX4SYNCHEADER ( pipe_rx4_syncheader ),
.PIPERX5CHARISK ( pipe_rx5_char_is_k ),
.PIPERX5SYNCHEADER ( pipe_rx5_syncheader ),
.PIPERX6CHARISK ( pipe_rx6_char_is_k ),
.PIPERX6SYNCHEADER ( pipe_rx6_syncheader ),
.PIPERX7CHARISK ( pipe_rx7_char_is_k ),
.PIPERX7SYNCHEADER ( pipe_rx7_syncheader ),
.MAXISCQTREADY ( m_axis_cq_tready ),
.MAXISRCTREADY ( m_axis_rc_tready ),
.SAXISCCTDATA ( s_axis_cc_tdata_256 ),
.SAXISRQTDATA ( s_axis_rq_tdata_256 ),
.CFGDSFUNCTIONNUMBER ( cfg_ds_function_number ),
.CFGFCSEL ( cfg_fc_sel ),
.CFGINTERRUPTMSIATTR ( cfg_interrupt_msi_attr ),
.CFGINTERRUPTMSIFUNCTIONNUMBER ( cfg_interrupt_msi_function_number ),
.CFGMSGTRANSMITTYPE ( cfg_msg_transmit_type ),
.CFGPERFUNCSTATUSCONTROL ( cfg_per_func_status_control ),
.CFGPERFUNCTIONNUMBER ( cfg_per_function_number ),
.PIPERX0STATUS ( pipe_rx0_status ),
.PIPERX1STATUS ( pipe_rx1_status ),
.PIPERX2STATUS ( pipe_rx2_status ),
.PIPERX3STATUS ( pipe_rx3_status ),
.PIPERX4STATUS ( pipe_rx4_status ),
.PIPERX5STATUS ( pipe_rx5_status ),
.PIPERX6STATUS ( pipe_rx6_status ),
.PIPERX7STATUS ( pipe_rx7_status ),
.CFGEXTREADDATA ( cfg_ext_read_data ),
.CFGINTERRUPTMSIINT ( cfg_interrupt_msi_int ),
.CFGINTERRUPTMSIXDATA ( cfg_interrupt_msix_data ),
.CFGMGMTWRITEDATA ( cfg_mgmt_write_data ),
.CFGMSGTRANSMITDATA ( cfg_msg_transmit_data ),
.CFGTPHSTTREADDATA ( cfg_tph_stt_read_data ),
.PIPERX0DATA ( pipe_rx0_data_pcie ),
.PIPERX1DATA ( pipe_rx1_data_pcie ),
.PIPERX2DATA ( pipe_rx2_data_pcie ),
.PIPERX3DATA ( pipe_rx3_data_pcie ),
.PIPERX4DATA ( pipe_rx4_data_pcie ),
.PIPERX5DATA ( pipe_rx5_data_pcie ),
.PIPERX6DATA ( pipe_rx6_data_pcie ),
.PIPERX7DATA ( pipe_rx7_data_pcie ),
.SAXISCCTUSER ( s_axis_cc_tuser ),
.CFGINTERRUPTINT ( cfg_interrupt_int ),
.CFGINTERRUPTMSISELECT ( cfg_interrupt_msi_select ),
.CFGMGMTBYTEENABLE ( cfg_mgmt_byte_enable ),
.CFGDSDEVICENUMBER ( cfg_ds_device_number ),
.SAXISRQTUSER ( s_axis_rq_tuser ),
.CFGVFFLRDONE ( cfg_vf_flr_done ),
.PIPEEQFS ( pipe_tx_eqfs ),
.PIPEEQLF ( pipe_tx_eqlf ),
.CFGDSN ( cfg_dsn ),
.CFGINTERRUPTMSIPENDINGSTATUS ( cfg_interrupt_msi_pending_status ),
.CFGINTERRUPTMSIXADDRESS ( cfg_interrupt_msix_address ),
.CFGDSBUSNUMBER ( cfg_ds_bus_number ),
.CFGDSPORTNUMBER ( cfg_ds_port_number ),
.CFGREVID ( cfg_rev_id ),
.PLGEN3PCSRXSYNCDONE ( pipe_rx_syncdone ),
.SAXISCCTKEEP ( s_axis_cc_tkeep_w ),
.SAXISRQTKEEP ( s_axis_rq_tkeep_w ),
.CFGINTERRUPTMSITPHSTTAG ( cfg_interrupt_msi_tph_st_tag )
);
//------------------------------------------------------------------------------------------------------------------//
// Force Adapt for Gen3 //
//------------------------------------------------------------------------------------------------------------------//
pcie3_7x_0_pcie_force_adapt force_adapt_i(
.pipe_clk(pipe_clk),
.user_clk(user_clk),
.cfg_ltssm_state(cfg_ltssm_state),
.cfg_current_speed(cfg_current_speed),
.pipe_tx0_rate(pipe_tx_rate),
.pipe_rx0_elec_idle(pipe_rx0_elec_idle),
.pipe_rx0_eqlp_adaptdone(pipe_rx0_eqlp_adaptdone),
.pipe_tx0_eqcontrol(pipe_tx0_eqcontrol),
.pipe_rx0_data_in(pipe_rx0_data),
.pipe_rx1_data_in(pipe_rx1_data),
.pipe_rx2_data_in(pipe_rx2_data),
.pipe_rx3_data_in(pipe_rx3_data),
.pipe_rx4_data_in(pipe_rx4_data),
.pipe_rx5_data_in(pipe_rx5_data),
.pipe_rx6_data_in(pipe_rx6_data),
.pipe_rx7_data_in(pipe_rx7_data),
.pipe_rx0_eqcontrol_in(pipe_rx0_eqcontrol_pcie),
.pipe_rx1_eqcontrol_in(pipe_rx1_eqcontrol_pcie),
.pipe_rx2_eqcontrol_in(pipe_rx2_eqcontrol_pcie),
.pipe_rx3_eqcontrol_in(pipe_rx3_eqcontrol_pcie),
.pipe_rx4_eqcontrol_in(pipe_rx4_eqcontrol_pcie),
.pipe_rx5_eqcontrol_in(pipe_rx5_eqcontrol_pcie),
.pipe_rx6_eqcontrol_in(pipe_rx6_eqcontrol_pcie),
.pipe_rx7_eqcontrol_in(pipe_rx7_eqcontrol_pcie),
.pipe_rx0_data_out(pipe_rx0_data_pcie),
.pipe_rx1_data_out(pipe_rx1_data_pcie),
.pipe_rx2_data_out(pipe_rx2_data_pcie),
.pipe_rx3_data_out(pipe_rx3_data_pcie),
.pipe_rx4_data_out(pipe_rx4_data_pcie),
.pipe_rx5_data_out(pipe_rx5_data_pcie),
.pipe_rx6_data_out(pipe_rx6_data_pcie),
.pipe_rx7_data_out(pipe_rx7_data_pcie),
.pipe_rx0_eqcontrol_out(pipe_rx0_eqcontrol),
.pipe_rx1_eqcontrol_out(pipe_rx1_eqcontrol),
.pipe_rx2_eqcontrol_out(pipe_rx2_eqcontrol),
.pipe_rx3_eqcontrol_out(pipe_rx3_eqcontrol),
.pipe_rx4_eqcontrol_out(pipe_rx4_eqcontrol),
.pipe_rx5_eqcontrol_out(pipe_rx5_eqcontrol),
.pipe_rx6_eqcontrol_out(pipe_rx6_eqcontrol),
.pipe_rx7_eqcontrol_out(pipe_rx7_eqcontrol)
);
//------------------------------------------------------------------------------------------------------------------//
// PIPE Interface PIPELINE Module //
//------------------------------------------------------------------------------------------------------------------//
pcie3_7x_0_pcie_pipe_pipeline #
(
.TCQ ( TCQ ),
.LINK_CAP_MAX_LINK_WIDTH ( PL_LINK_CAP_MAX_LINK_WIDTH ),
.PIPE_PIPELINE_STAGES ( PIPE_PIPELINE_STAGES )
)
pcie_pipe_pipeline_i (
// Pipe Per-Link Signals
.pipe_tx_rcvr_det_i ( pipe_tx_rcvr_det ),
.pipe_tx_reset_i ( pipe_tx_reset ),
.pipe_tx_rate_i ( pipe_tx_rate ),
.pipe_tx_deemph_i ( pipe_tx_deemph ),
.pipe_tx_margin_i ( pipe_tx_margin ),
.pipe_tx_swing_i ( pipe_tx_swing ),
.pipe_tx_eqfs_i ( pipe_tx_eqfs_gt ),
.pipe_tx_eqlf_i ( pipe_tx_eqlf_gt ),
.pipe_tx_rcvr_det_o ( pipe_tx_rcvr_det_gt ),
.pipe_tx_reset_o ( pipe_tx_reset_gt ),
.pipe_tx_rate_o ( pipe_tx_rate_gt ),
.pipe_tx_deemph_o ( pipe_tx_deemph_gt ),
.pipe_tx_margin_o ( pipe_tx_margin_gt ),
.pipe_tx_swing_o ( pipe_tx_swing_gt ),
.pipe_tx_eqfs_o ( pipe_tx_eqfs ),
.pipe_tx_eqlf_o ( pipe_tx_eqlf ),
// Pipe Per-Lane Signals
.pipe_rxslide_i ( pipe_rx_slide ),
.pipe_rxsyncdone_i ( pipe_rx_syncdone_gt ),
.pipe_rxslide_o ( pipe_rx_slide_gt ),
.pipe_rxsyncdone_o ( pipe_rx_syncdone ),
// Pipe Per-Lane Signals - Lane 0
.pipe_rx0_char_is_k_o ( pipe_rx0_char_is_k ),
.pipe_rx0_data_o ( pipe_rx0_data ),
.pipe_rx0_valid_o ( pipe_rx0_valid ),
.pipe_rx0_data_valid_o ( pipe_rx0_data_valid ),
.pipe_rx0_status_o ( pipe_rx0_status ),
.pipe_rx0_phy_status_o ( pipe_rx0_phy_status ),
.pipe_rx0_elec_idle_o ( pipe_rx0_elec_idle ),
.pipe_rx0_eqdone_o ( pipe_rx0_eqdone ),
.pipe_rx0_eqlpadaptdone_o ( pipe_rx0_eqlp_adaptdone ),
.pipe_rx0_eqlplffssel_o ( pipe_rx0_eqlp_lffs_sel ),
.pipe_rx0_eqlpnewtxcoefforpreset_o ( pipe_rx0_eqlp_new_txcoef_forpreset ),
.pipe_rx0_startblock_o ( pipe_rx0_start_block ),
.pipe_rx0_syncheader_o ( pipe_rx0_syncheader ),
.pipe_rx0_polarity_i ( pipe_rx0_polarity ),
.pipe_rx0_eqcontrol_i ( pipe_rx0_eqcontrol ),
.pipe_rx0_eqlplffs_i ( pipe_rx0_eqlp_lffs ),
.pipe_rx0_eqlptxpreset_i ( pipe_rx0_eqlp_txpreset ),
.pipe_rx0_eqpreset_i ( pipe_rx0_eqpreset ),
.pipe_tx0_eqcoeff_o ( pipe_tx0_eqcoeff ),
.pipe_tx0_eqdone_o ( pipe_tx0_eqdone ),
.pipe_tx0_compliance_i ( pipe_tx0_compliance ),
.pipe_tx0_char_is_k_i ( pipe_tx0_char_is_k ),
.pipe_tx0_data_i ( pipe_tx0_data ),
.pipe_tx0_elec_idle_i ( pipe_tx0_elec_idle ),
.pipe_tx0_powerdown_i ( pipe_tx0_powerdown ),
.pipe_tx0_datavalid_i ( pipe_tx0_data_valid ),
.pipe_tx0_startblock_i ( pipe_tx0_start_block ),
.pipe_tx0_syncheader_i ( pipe_tx0_syncheader ),
.pipe_tx0_eqcontrol_i ( pipe_tx0_eqcontrol ),
.pipe_tx0_eqdeemph_i ( pipe_tx0_eqdeemph ),
.pipe_tx0_eqpreset_i ( pipe_tx0_eqpreset ),
.pipe_rx0_char_is_k_i ( pipe_rx0_char_is_k_gt ),
.pipe_rx0_data_i ( pipe_rx0_data_gt ),
.pipe_rx0_valid_i ( pipe_rx0_valid_gt ),
.pipe_rx0_data_valid_i ( pipe_rx0_data_valid_gt ),
.pipe_rx0_status_i ( pipe_rx0_status_gt ),
.pipe_rx0_phy_status_i ( pipe_rx0_phy_status_gt ),
.pipe_rx0_elec_idle_i ( pipe_rx0_elec_idle_gt ),
.pipe_rx0_eqdone_i ( pipe_rx0_eqdone_gt ),
.pipe_rx0_eqlpadaptdone_i ( pipe_rx0_eqlp_adaptdone_gt ),
.pipe_rx0_eqlplffssel_i ( pipe_rx0_eqlp_lffs_sel_gt ),
.pipe_rx0_eqlpnewtxcoefforpreset_i ( pipe_rx0_eqlp_new_txcoef_forpreset_gt ),
.pipe_rx0_startblock_i ( pipe_rx0_start_block_gt ),
.pipe_rx0_syncheader_i ( pipe_rx0_syncheader_gt ),
.pipe_rx0_polarity_o ( pipe_rx0_polarity_gt ),
.pipe_rx0_eqcontrol_o ( pipe_rx0_eqcontrol_gt ),
.pipe_rx0_eqlplffs_o ( pipe_rx0_eqlp_lffs_gt ),
.pipe_rx0_eqlptxpreset_o ( pipe_rx0_eqlp_txpreset_gt ),
.pipe_rx0_eqpreset_o ( pipe_rx0_eqpreset_gt ),
.pipe_tx0_eqcoeff_i ( pipe_tx0_eqcoeff_gt ),
.pipe_tx0_eqdone_i ( pipe_tx0_eqdone_gt ),
.pipe_tx0_compliance_o ( pipe_tx0_compliance_gt ),
.pipe_tx0_char_is_k_o ( pipe_tx0_char_is_k_gt ),
.pipe_tx0_data_o ( pipe_tx0_data_gt ),
.pipe_tx0_elec_idle_o ( pipe_tx0_elec_idle_gt ),
.pipe_tx0_powerdown_o ( pipe_tx0_powerdown_gt ),
.pipe_tx0_datavalid_o ( pipe_tx0_data_valid_gt ),
.pipe_tx0_startblock_o ( pipe_tx0_start_block_gt ),
.pipe_tx0_syncheader_o ( pipe_tx0_syncheader_gt ),
.pipe_tx0_eqcontrol_o ( pipe_tx0_eqcontrol_gt ),
.pipe_tx0_eqdeemph_o ( pipe_tx0_eqdeemph_gt ),
.pipe_tx0_eqpreset_o ( pipe_tx0_eqpreset_gt ),
// Pipe Per-Lane Signals - Lane 1
.pipe_rx1_char_is_k_o ( pipe_rx1_char_is_k ),
.pipe_rx1_data_o ( pipe_rx1_data ),
.pipe_rx1_valid_o ( pipe_rx1_valid ),
.pipe_rx1_data_valid_o ( pipe_rx1_data_valid ),
.pipe_rx1_status_o ( pipe_rx1_status ),
.pipe_rx1_phy_status_o ( pipe_rx1_phy_status ),
.pipe_rx1_elec_idle_o ( pipe_rx1_elec_idle ),
.pipe_rx1_eqdone_o ( pipe_rx1_eqdone ),
.pipe_rx1_eqlpadaptdone_o ( pipe_rx1_eqlp_adaptdone ),
.pipe_rx1_eqlplffssel_o ( pipe_rx1_eqlp_lffs_sel ),
.pipe_rx1_eqlpnewtxcoefforpreset_o ( pipe_rx1_eqlp_new_txcoef_forpreset ),
.pipe_rx1_startblock_o ( pipe_rx1_start_block ),
.pipe_rx1_syncheader_o ( pipe_rx1_syncheader ),
.pipe_rx1_polarity_i ( pipe_rx1_polarity ),
.pipe_rx1_eqcontrol_i ( pipe_rx1_eqcontrol ),
.pipe_rx1_eqlplffs_i ( pipe_rx1_eqlp_lffs ),
.pipe_rx1_eqlptxpreset_i ( pipe_rx1_eqlp_txpreset ),
.pipe_rx1_eqpreset_i ( pipe_rx1_eqpreset ),
.pipe_tx1_eqcoeff_o ( pipe_tx1_eqcoeff ),
.pipe_tx1_eqdone_o ( pipe_tx1_eqdone ),
.pipe_tx1_compliance_i ( pipe_tx1_compliance ),
.pipe_tx1_char_is_k_i ( pipe_tx1_char_is_k ),
.pipe_tx1_data_i ( pipe_tx1_data ),
.pipe_tx1_elec_idle_i ( pipe_tx1_elec_idle ),
.pipe_tx1_powerdown_i ( pipe_tx1_powerdown ),
.pipe_tx1_datavalid_i ( pipe_tx1_data_valid ),
.pipe_tx1_startblock_i ( pipe_tx1_start_block ),
.pipe_tx1_syncheader_i ( pipe_tx1_syncheader ),
.pipe_tx1_eqcontrol_i ( pipe_tx1_eqcontrol ),
.pipe_tx1_eqdeemph_i ( pipe_tx1_eqdeemph ),
.pipe_tx1_eqpreset_i ( pipe_tx1_eqpreset ),
.pipe_rx1_char_is_k_i ( pipe_rx1_char_is_k_gt ),
.pipe_rx1_data_i ( pipe_rx1_data_gt ),
.pipe_rx1_valid_i ( pipe_rx1_valid_gt ),
.pipe_rx1_data_valid_i ( pipe_rx1_data_valid_gt ),
.pipe_rx1_status_i ( pipe_rx1_status_gt ),
.pipe_rx1_phy_status_i ( pipe_rx1_phy_status_gt ),
.pipe_rx1_elec_idle_i ( pipe_rx1_elec_idle_gt ),
.pipe_rx1_eqdone_i ( pipe_rx1_eqdone_gt ),
.pipe_rx1_eqlpadaptdone_i ( pipe_rx1_eqlp_adaptdone_gt ),
.pipe_rx1_eqlplffssel_i ( pipe_rx1_eqlp_lffs_sel_gt ),
.pipe_rx1_eqlpnewtxcoefforpreset_i ( pipe_rx1_eqlp_new_txcoef_forpreset_gt ),
.pipe_rx1_startblock_i ( pipe_rx1_start_block_gt ),
.pipe_rx1_syncheader_i ( pipe_rx1_syncheader_gt ),
.pipe_rx1_polarity_o ( pipe_rx1_polarity_gt ),
.pipe_rx1_eqcontrol_o ( pipe_rx1_eqcontrol_gt ),
.pipe_rx1_eqlplffs_o ( pipe_rx1_eqlp_lffs_gt ),
.pipe_rx1_eqlptxpreset_o ( pipe_rx1_eqlp_txpreset_gt ),
.pipe_rx1_eqpreset_o ( pipe_rx1_eqpreset_gt ),
.pipe_tx1_eqcoeff_i ( pipe_tx1_eqcoeff_gt ),
.pipe_tx1_eqdone_i ( pipe_tx1_eqdone_gt ),
.pipe_tx1_compliance_o ( pipe_tx1_compliance_gt ),
.pipe_tx1_char_is_k_o ( pipe_tx1_char_is_k_gt ),
.pipe_tx1_data_o ( pipe_tx1_data_gt ),
.pipe_tx1_elec_idle_o ( pipe_tx1_elec_idle_gt ),
.pipe_tx1_powerdown_o ( pipe_tx1_powerdown_gt ),
.pipe_tx1_datavalid_o ( pipe_tx1_data_valid_gt ),
.pipe_tx1_startblock_o ( pipe_tx1_start_block_gt ),
.pipe_tx1_syncheader_o ( pipe_tx1_syncheader_gt ),
.pipe_tx1_eqcontrol_o ( pipe_tx1_eqcontrol_gt ),
.pipe_tx1_eqdeemph_o ( pipe_tx1_eqdeemph_gt ),
.pipe_tx1_eqpreset_o ( pipe_tx1_eqpreset_gt ),
// Pipe Per-Lane Signals - Lane 2
.pipe_rx2_char_is_k_o ( pipe_rx2_char_is_k ),
.pipe_rx2_data_o ( pipe_rx2_data ),
.pipe_rx2_valid_o ( pipe_rx2_valid ),
.pipe_rx2_data_valid_o ( pipe_rx2_data_valid ),
.pipe_rx2_status_o ( pipe_rx2_status ),
.pipe_rx2_phy_status_o ( pipe_rx2_phy_status ),
.pipe_rx2_elec_idle_o ( pipe_rx2_elec_idle ),
.pipe_rx2_eqdone_o ( pipe_rx2_eqdone ),
.pipe_rx2_eqlpadaptdone_o ( pipe_rx2_eqlp_adaptdone ),
.pipe_rx2_eqlplffssel_o ( pipe_rx2_eqlp_lffs_sel ),
.pipe_rx2_eqlpnewtxcoefforpreset_o ( pipe_rx2_eqlp_new_txcoef_forpreset ),
.pipe_rx2_startblock_o ( pipe_rx2_start_block ),
.pipe_rx2_syncheader_o ( pipe_rx2_syncheader ),
.pipe_rx2_polarity_i ( pipe_rx2_polarity ),
.pipe_rx2_eqcontrol_i ( pipe_rx2_eqcontrol ),
.pipe_rx2_eqlplffs_i ( pipe_rx2_eqlp_lffs ),
.pipe_rx2_eqlptxpreset_i ( pipe_rx2_eqlp_txpreset ),
.pipe_rx2_eqpreset_i ( pipe_rx2_eqpreset ),
.pipe_tx2_eqcoeff_o ( pipe_tx2_eqcoeff ),
.pipe_tx2_eqdone_o ( pipe_tx2_eqdone ),
.pipe_tx2_compliance_i ( pipe_tx2_compliance ),
.pipe_tx2_char_is_k_i ( pipe_tx2_char_is_k ),
.pipe_tx2_data_i ( pipe_tx2_data ),
.pipe_tx2_elec_idle_i ( pipe_tx2_elec_idle ),
.pipe_tx2_powerdown_i ( pipe_tx2_powerdown ),
.pipe_tx2_datavalid_i ( pipe_tx2_data_valid ),
.pipe_tx2_startblock_i ( pipe_tx2_start_block ),
.pipe_tx2_syncheader_i ( pipe_tx2_syncheader ),
.pipe_tx2_eqcontrol_i ( pipe_tx2_eqcontrol ),
.pipe_tx2_eqdeemph_i ( pipe_tx2_eqdeemph ),
.pipe_tx2_eqpreset_i ( pipe_tx2_eqpreset ),
.pipe_rx2_char_is_k_i ( pipe_rx2_char_is_k_gt ),
.pipe_rx2_data_i ( pipe_rx2_data_gt ),
.pipe_rx2_valid_i ( pipe_rx2_valid_gt ),
.pipe_rx2_data_valid_i ( pipe_rx2_data_valid_gt ),
.pipe_rx2_status_i ( pipe_rx2_status_gt ),
.pipe_rx2_phy_status_i ( pipe_rx2_phy_status_gt ),
.pipe_rx2_elec_idle_i ( pipe_rx2_elec_idle_gt ),
.pipe_rx2_eqdone_i ( pipe_rx2_eqdone_gt ),
.pipe_rx2_eqlpadaptdone_i ( pipe_rx2_eqlp_adaptdone_gt ),
.pipe_rx2_eqlplffssel_i ( pipe_rx2_eqlp_lffs_sel_gt ),
.pipe_rx2_eqlpnewtxcoefforpreset_i ( pipe_rx2_eqlp_new_txcoef_forpreset_gt ),
.pipe_rx2_startblock_i ( pipe_rx2_start_block_gt ),
.pipe_rx2_syncheader_i ( pipe_rx2_syncheader_gt ),
.pipe_rx2_polarity_o ( pipe_rx2_polarity_gt ),
.pipe_rx2_eqcontrol_o ( pipe_rx2_eqcontrol_gt ),
.pipe_rx2_eqlplffs_o ( pipe_rx2_eqlp_lffs_gt ),
.pipe_rx2_eqlptxpreset_o ( pipe_rx2_eqlp_txpreset_gt ),
.pipe_rx2_eqpreset_o ( pipe_rx2_eqpreset_gt ),
.pipe_tx2_eqcoeff_i ( pipe_tx2_eqcoeff_gt ),
.pipe_tx2_eqdone_i ( pipe_tx2_eqdone_gt ),
.pipe_tx2_compliance_o ( pipe_tx2_compliance_gt ),
.pipe_tx2_char_is_k_o ( pipe_tx2_char_is_k_gt ),
.pipe_tx2_data_o ( pipe_tx2_data_gt ),
.pipe_tx2_elec_idle_o ( pipe_tx2_elec_idle_gt ),
.pipe_tx2_powerdown_o ( pipe_tx2_powerdown_gt ),
.pipe_tx2_datavalid_o ( pipe_tx2_data_valid_gt ),
.pipe_tx2_startblock_o ( pipe_tx2_start_block_gt ),
.pipe_tx2_syncheader_o ( pipe_tx2_syncheader_gt ),
.pipe_tx2_eqcontrol_o ( pipe_tx2_eqcontrol_gt ),
.pipe_tx2_eqdeemph_o ( pipe_tx2_eqdeemph_gt ),
.pipe_tx2_eqpreset_o ( pipe_tx2_eqpreset_gt ),
// Pipe Per-Lane Signals - Lane 3
.pipe_rx3_char_is_k_o ( pipe_rx3_char_is_k ),
.pipe_rx3_data_o ( pipe_rx3_data ),
.pipe_rx3_valid_o ( pipe_rx3_valid ),
.pipe_rx3_data_valid_o ( pipe_rx3_data_valid ),
.pipe_rx3_status_o ( pipe_rx3_status ),
.pipe_rx3_phy_status_o ( pipe_rx3_phy_status ),
.pipe_rx3_elec_idle_o ( pipe_rx3_elec_idle ),
.pipe_rx3_eqdone_o ( pipe_rx3_eqdone ),
.pipe_rx3_eqlpadaptdone_o ( pipe_rx3_eqlp_adaptdone ),
.pipe_rx3_eqlplffssel_o ( pipe_rx3_eqlp_lffs_sel ),
.pipe_rx3_eqlpnewtxcoefforpreset_o ( pipe_rx3_eqlp_new_txcoef_forpreset ),
.pipe_rx3_startblock_o ( pipe_rx3_start_block ),
.pipe_rx3_syncheader_o ( pipe_rx3_syncheader ),
.pipe_rx3_polarity_i ( pipe_rx3_polarity ),
.pipe_rx3_eqcontrol_i ( pipe_rx3_eqcontrol ),
.pipe_rx3_eqlplffs_i ( pipe_rx3_eqlp_lffs ),
.pipe_rx3_eqlptxpreset_i ( pipe_rx3_eqlp_txpreset ),
.pipe_rx3_eqpreset_i ( pipe_rx3_eqpreset ),
.pipe_tx3_eqcoeff_o ( pipe_tx3_eqcoeff ),
.pipe_tx3_eqdone_o ( pipe_tx3_eqdone ),
.pipe_tx3_compliance_i ( pipe_tx3_compliance ),
.pipe_tx3_char_is_k_i ( pipe_tx3_char_is_k ),
.pipe_tx3_data_i ( pipe_tx3_data ),
.pipe_tx3_elec_idle_i ( pipe_tx3_elec_idle ),
.pipe_tx3_powerdown_i ( pipe_tx3_powerdown ),
.pipe_tx3_datavalid_i ( pipe_tx3_data_valid ),
.pipe_tx3_startblock_i ( pipe_tx3_start_block ),
.pipe_tx3_syncheader_i ( pipe_tx3_syncheader ),
.pipe_tx3_eqcontrol_i ( pipe_tx3_eqcontrol ),
.pipe_tx3_eqdeemph_i ( pipe_tx3_eqdeemph ),
.pipe_tx3_eqpreset_i ( pipe_tx3_eqpreset ),
.pipe_rx3_char_is_k_i ( pipe_rx3_char_is_k_gt ),
.pipe_rx3_data_i ( pipe_rx3_data_gt ),
.pipe_rx3_valid_i ( pipe_rx3_valid_gt ),
.pipe_rx3_data_valid_i ( pipe_rx3_data_valid_gt ),
.pipe_rx3_status_i ( pipe_rx3_status_gt ),
.pipe_rx3_phy_status_i ( pipe_rx3_phy_status_gt ),
.pipe_rx3_elec_idle_i ( pipe_rx3_elec_idle_gt ),
.pipe_rx3_eqdone_i ( pipe_rx3_eqdone_gt ),
.pipe_rx3_eqlpadaptdone_i ( pipe_rx3_eqlp_adaptdone_gt ),
.pipe_rx3_eqlplffssel_i ( pipe_rx3_eqlp_lffs_sel_gt ),
.pipe_rx3_eqlpnewtxcoefforpreset_i ( pipe_rx3_eqlp_new_txcoef_forpreset_gt ),
.pipe_rx3_startblock_i ( pipe_rx3_start_block_gt ),
.pipe_rx3_syncheader_i ( pipe_rx3_syncheader_gt ),
.pipe_rx3_polarity_o ( pipe_rx3_polarity_gt ),
.pipe_rx3_eqcontrol_o ( pipe_rx3_eqcontrol_gt ),
.pipe_rx3_eqlplffs_o ( pipe_rx3_eqlp_lffs_gt ),
.pipe_rx3_eqlptxpreset_o ( pipe_rx3_eqlp_txpreset_gt ),
.pipe_rx3_eqpreset_o ( pipe_rx3_eqpreset_gt ),
.pipe_tx3_eqcoeff_i ( pipe_tx3_eqcoeff_gt ),
.pipe_tx3_eqdone_i ( pipe_tx3_eqdone_gt ),
.pipe_tx3_compliance_o ( pipe_tx3_compliance_gt ),
.pipe_tx3_char_is_k_o ( pipe_tx3_char_is_k_gt ),
.pipe_tx3_data_o ( pipe_tx3_data_gt ),
.pipe_tx3_elec_idle_o ( pipe_tx3_elec_idle_gt ),
.pipe_tx3_powerdown_o ( pipe_tx3_powerdown_gt ),
.pipe_tx3_datavalid_o ( pipe_tx3_data_valid_gt ),
.pipe_tx3_startblock_o ( pipe_tx3_start_block_gt ),
.pipe_tx3_syncheader_o ( pipe_tx3_syncheader_gt ),
.pipe_tx3_eqcontrol_o ( pipe_tx3_eqcontrol_gt ),
.pipe_tx3_eqdeemph_o ( pipe_tx3_eqdeemph_gt ),
.pipe_tx3_eqpreset_o ( pipe_tx3_eqpreset_gt ),
// Pipe Per-Lane Signals - Lane 4
.pipe_rx4_char_is_k_o ( pipe_rx4_char_is_k ),
.pipe_rx4_data_o ( pipe_rx4_data ),
.pipe_rx4_valid_o ( pipe_rx4_valid ),
.pipe_rx4_data_valid_o ( pipe_rx4_data_valid ),
.pipe_rx4_status_o ( pipe_rx4_status ),
.pipe_rx4_phy_status_o ( pipe_rx4_phy_status ),
.pipe_rx4_elec_idle_o ( pipe_rx4_elec_idle ),
.pipe_rx4_eqdone_o ( pipe_rx4_eqdone ),
.pipe_rx4_eqlpadaptdone_o ( pipe_rx4_eqlp_adaptdone ),
.pipe_rx4_eqlplffssel_o ( pipe_rx4_eqlp_lffs_sel ),
.pipe_rx4_eqlpnewtxcoefforpreset_o ( pipe_rx4_eqlp_new_txcoef_forpreset ),
.pipe_rx4_startblock_o ( pipe_rx4_start_block ),
.pipe_rx4_syncheader_o ( pipe_rx4_syncheader ),
.pipe_rx4_polarity_i ( pipe_rx4_polarity ),
.pipe_rx4_eqcontrol_i ( pipe_rx4_eqcontrol ),
.pipe_rx4_eqlplffs_i ( pipe_rx4_eqlp_lffs ),
.pipe_rx4_eqlptxpreset_i ( pipe_rx4_eqlp_txpreset ),
.pipe_rx4_eqpreset_i ( pipe_rx4_eqpreset ),
.pipe_tx4_eqcoeff_o ( pipe_tx4_eqcoeff ),
.pipe_tx4_eqdone_o ( pipe_tx4_eqdone ),
.pipe_tx4_compliance_i ( pipe_tx4_compliance ),
.pipe_tx4_char_is_k_i ( pipe_tx4_char_is_k ),
.pipe_tx4_data_i ( pipe_tx4_data ),
.pipe_tx4_elec_idle_i ( pipe_tx4_elec_idle ),
.pipe_tx4_powerdown_i ( pipe_tx4_powerdown ),
.pipe_tx4_datavalid_i ( pipe_tx4_data_valid ),
.pipe_tx4_startblock_i ( pipe_tx4_start_block ),
.pipe_tx4_syncheader_i ( pipe_tx4_syncheader ),
.pipe_tx4_eqcontrol_i ( pipe_tx4_eqcontrol ),
.pipe_tx4_eqdeemph_i ( pipe_tx4_eqdeemph ),
.pipe_tx4_eqpreset_i ( pipe_tx4_eqpreset ),
.pipe_rx4_char_is_k_i ( pipe_rx4_char_is_k_gt ),
.pipe_rx4_data_i ( pipe_rx4_data_gt ),
.pipe_rx4_valid_i ( pipe_rx4_valid_gt ),
.pipe_rx4_data_valid_i ( pipe_rx4_data_valid_gt ),
.pipe_rx4_status_i ( pipe_rx4_status_gt ),
.pipe_rx4_phy_status_i ( pipe_rx4_phy_status_gt ),
.pipe_rx4_elec_idle_i ( pipe_rx4_elec_idle_gt ),
.pipe_rx4_eqdone_i ( pipe_rx4_eqdone_gt ),
.pipe_rx4_eqlpadaptdone_i ( pipe_rx4_eqlp_adaptdone_gt ),
.pipe_rx4_eqlplffssel_i ( pipe_rx4_eqlp_lffs_sel_gt ),
.pipe_rx4_eqlpnewtxcoefforpreset_i ( pipe_rx4_eqlp_new_txcoef_forpreset_gt ),
.pipe_rx4_startblock_i ( pipe_rx4_start_block_gt ),
.pipe_rx4_syncheader_i ( pipe_rx4_syncheader_gt ),
.pipe_rx4_polarity_o ( pipe_rx4_polarity_gt ),
.pipe_rx4_eqcontrol_o ( pipe_rx4_eqcontrol_gt ),
.pipe_rx4_eqlplffs_o ( pipe_rx4_eqlp_lffs_gt ),
.pipe_rx4_eqlptxpreset_o ( pipe_rx4_eqlp_txpreset_gt ),
.pipe_rx4_eqpreset_o ( pipe_rx4_eqpreset_gt ),
.pipe_tx4_eqcoeff_i ( pipe_tx4_eqcoeff_gt ),
.pipe_tx4_eqdone_i ( pipe_tx4_eqdone_gt ),
.pipe_tx4_compliance_o ( pipe_tx4_compliance_gt ),
.pipe_tx4_char_is_k_o ( pipe_tx4_char_is_k_gt ),
.pipe_tx4_data_o ( pipe_tx4_data_gt ),
.pipe_tx4_elec_idle_o ( pipe_tx4_elec_idle_gt ),
.pipe_tx4_powerdown_o ( pipe_tx4_powerdown_gt ),
.pipe_tx4_datavalid_o ( pipe_tx4_data_valid_gt ),
.pipe_tx4_startblock_o ( pipe_tx4_start_block_gt ),
.pipe_tx4_syncheader_o ( pipe_tx4_syncheader_gt ),
.pipe_tx4_eqcontrol_o ( pipe_tx4_eqcontrol_gt ),
.pipe_tx4_eqdeemph_o ( pipe_tx4_eqdeemph_gt ),
.pipe_tx4_eqpreset_o ( pipe_tx4_eqpreset_gt ),
// Pipe Per-Lane Signals - Lane 5
.pipe_rx5_char_is_k_o ( pipe_rx5_char_is_k ),
.pipe_rx5_data_o ( pipe_rx5_data ),
.pipe_rx5_valid_o ( pipe_rx5_valid ),
.pipe_rx5_data_valid_o ( pipe_rx5_data_valid ),
.pipe_rx5_status_o ( pipe_rx5_status ),
.pipe_rx5_phy_status_o ( pipe_rx5_phy_status ),
.pipe_rx5_elec_idle_o ( pipe_rx5_elec_idle ),
.pipe_rx5_eqdone_o ( pipe_rx5_eqdone ),
.pipe_rx5_eqlpadaptdone_o ( pipe_rx5_eqlp_adaptdone ),
.pipe_rx5_eqlplffssel_o ( pipe_rx5_eqlp_lffs_sel ),
.pipe_rx5_eqlpnewtxcoefforpreset_o ( pipe_rx5_eqlp_new_txcoef_forpreset ),
.pipe_rx5_startblock_o ( pipe_rx5_start_block ),
.pipe_rx5_syncheader_o ( pipe_rx5_syncheader ),
.pipe_rx5_polarity_i ( pipe_rx5_polarity ),
.pipe_rx5_eqcontrol_i ( pipe_rx5_eqcontrol ),
.pipe_rx5_eqlplffs_i ( pipe_rx5_eqlp_lffs ),
.pipe_rx5_eqlptxpreset_i ( pipe_rx5_eqlp_txpreset ),
.pipe_rx5_eqpreset_i ( pipe_rx5_eqpreset ),
.pipe_tx5_eqcoeff_o ( pipe_tx5_eqcoeff ),
.pipe_tx5_eqdone_o ( pipe_tx5_eqdone ),
.pipe_tx5_compliance_i ( pipe_tx5_compliance ),
.pipe_tx5_char_is_k_i ( pipe_tx5_char_is_k ),
.pipe_tx5_data_i ( pipe_tx5_data ),
.pipe_tx5_elec_idle_i ( pipe_tx5_elec_idle ),
.pipe_tx5_powerdown_i ( pipe_tx5_powerdown ),
.pipe_tx5_datavalid_i ( pipe_tx5_data_valid ),
.pipe_tx5_startblock_i ( pipe_tx5_start_block ),
.pipe_tx5_syncheader_i ( pipe_tx5_syncheader ),
.pipe_tx5_eqcontrol_i ( pipe_tx5_eqcontrol ),
.pipe_tx5_eqdeemph_i ( pipe_tx5_eqdeemph ),
.pipe_tx5_eqpreset_i ( pipe_tx5_eqpreset ),
.pipe_rx5_char_is_k_i ( pipe_rx5_char_is_k_gt ),
.pipe_rx5_data_i ( pipe_rx5_data_gt ),
.pipe_rx5_valid_i ( pipe_rx5_valid_gt ),
.pipe_rx5_data_valid_i ( pipe_rx5_data_valid_gt ),
.pipe_rx5_status_i ( pipe_rx5_status_gt ),
.pipe_rx5_phy_status_i ( pipe_rx5_phy_status_gt ),
.pipe_rx5_elec_idle_i ( pipe_rx5_elec_idle_gt ),
.pipe_rx5_eqdone_i ( pipe_rx5_eqdone_gt ),
.pipe_rx5_eqlpadaptdone_i ( pipe_rx5_eqlp_adaptdone_gt ),
.pipe_rx5_eqlplffssel_i ( pipe_rx5_eqlp_lffs_sel_gt ),
.pipe_rx5_eqlpnewtxcoefforpreset_i ( pipe_rx5_eqlp_new_txcoef_forpreset_gt ),
.pipe_rx5_startblock_i ( pipe_rx5_start_block_gt ),
.pipe_rx5_syncheader_i ( pipe_rx5_syncheader_gt ),
.pipe_rx5_polarity_o ( pipe_rx5_polarity_gt ),
.pipe_rx5_eqcontrol_o ( pipe_rx5_eqcontrol_gt ),
.pipe_rx5_eqlplffs_o ( pipe_rx5_eqlp_lffs_gt ),
.pipe_rx5_eqlptxpreset_o ( pipe_rx5_eqlp_txpreset_gt ),
.pipe_rx5_eqpreset_o ( pipe_rx5_eqpreset_gt ),
.pipe_tx5_eqcoeff_i ( pipe_tx5_eqcoeff_gt ),
.pipe_tx5_eqdone_i ( pipe_tx5_eqdone_gt ),
.pipe_tx5_compliance_o ( pipe_tx5_compliance_gt ),
.pipe_tx5_char_is_k_o ( pipe_tx5_char_is_k_gt ),
.pipe_tx5_data_o ( pipe_tx5_data_gt ),
.pipe_tx5_elec_idle_o ( pipe_tx5_elec_idle_gt ),
.pipe_tx5_powerdown_o ( pipe_tx5_powerdown_gt ),
.pipe_tx5_datavalid_o ( pipe_tx5_data_valid_gt ),
.pipe_tx5_startblock_o ( pipe_tx5_start_block_gt ),
.pipe_tx5_syncheader_o ( pipe_tx5_syncheader_gt ),
.pipe_tx5_eqcontrol_o ( pipe_tx5_eqcontrol_gt ),
.pipe_tx5_eqdeemph_o ( pipe_tx5_eqdeemph_gt ),
.pipe_tx5_eqpreset_o ( pipe_tx5_eqpreset_gt ),
// Pipe Per-Lane Signals - Lane 6
.pipe_rx6_char_is_k_o ( pipe_rx6_char_is_k ),
.pipe_rx6_data_o ( pipe_rx6_data ),
.pipe_rx6_valid_o ( pipe_rx6_valid ),
.pipe_rx6_data_valid_o ( pipe_rx6_data_valid ),
.pipe_rx6_status_o ( pipe_rx6_status ),
.pipe_rx6_phy_status_o ( pipe_rx6_phy_status ),
.pipe_rx6_elec_idle_o ( pipe_rx6_elec_idle ),
.pipe_rx6_eqdone_o ( pipe_rx6_eqdone ),
.pipe_rx6_eqlpadaptdone_o ( pipe_rx6_eqlp_adaptdone ),
.pipe_rx6_eqlplffssel_o ( pipe_rx6_eqlp_lffs_sel ),
.pipe_rx6_eqlpnewtxcoefforpreset_o ( pipe_rx6_eqlp_new_txcoef_forpreset ),
.pipe_rx6_startblock_o ( pipe_rx6_start_block ),
.pipe_rx6_syncheader_o ( pipe_rx6_syncheader ),
.pipe_rx6_polarity_i ( pipe_rx6_polarity ),
.pipe_rx6_eqcontrol_i ( pipe_rx6_eqcontrol ),
.pipe_rx6_eqlplffs_i ( pipe_rx6_eqlp_lffs ),
.pipe_rx6_eqlptxpreset_i ( pipe_rx6_eqlp_txpreset ),
.pipe_rx6_eqpreset_i ( pipe_rx6_eqpreset ),
.pipe_tx6_eqcoeff_o ( pipe_tx6_eqcoeff ),
.pipe_tx6_eqdone_o ( pipe_tx6_eqdone ),
.pipe_tx6_compliance_i ( pipe_tx6_compliance ),
.pipe_tx6_char_is_k_i ( pipe_tx6_char_is_k ),
.pipe_tx6_data_i ( pipe_tx6_data ),
.pipe_tx6_elec_idle_i ( pipe_tx6_elec_idle ),
.pipe_tx6_powerdown_i ( pipe_tx6_powerdown ),
.pipe_tx6_datavalid_i ( pipe_tx6_data_valid ),
.pipe_tx6_startblock_i ( pipe_tx6_start_block ),
.pipe_tx6_syncheader_i ( pipe_tx6_syncheader ),
.pipe_tx6_eqcontrol_i ( pipe_tx6_eqcontrol ),
.pipe_tx6_eqdeemph_i ( pipe_tx6_eqdeemph ),
.pipe_tx6_eqpreset_i ( pipe_tx6_eqpreset ),
.pipe_rx6_char_is_k_i ( pipe_rx6_char_is_k_gt ),
.pipe_rx6_data_i ( pipe_rx6_data_gt ),
.pipe_rx6_valid_i ( pipe_rx6_valid_gt ),
.pipe_rx6_data_valid_i ( pipe_rx6_data_valid_gt ),
.pipe_rx6_status_i ( pipe_rx6_status_gt ),
.pipe_rx6_phy_status_i ( pipe_rx6_phy_status_gt ),
.pipe_rx6_elec_idle_i ( pipe_rx6_elec_idle_gt ),
.pipe_rx6_eqdone_i ( pipe_rx6_eqdone_gt ),
.pipe_rx6_eqlpadaptdone_i ( pipe_rx6_eqlp_adaptdone_gt ),
.pipe_rx6_eqlplffssel_i ( pipe_rx6_eqlp_lffs_sel_gt ),
.pipe_rx6_eqlpnewtxcoefforpreset_i ( pipe_rx6_eqlp_new_txcoef_forpreset_gt ),
.pipe_rx6_startblock_i ( pipe_rx6_start_block_gt ),
.pipe_rx6_syncheader_i ( pipe_rx6_syncheader_gt ),
.pipe_rx6_polarity_o ( pipe_rx6_polarity_gt ),
.pipe_rx6_eqcontrol_o ( pipe_rx6_eqcontrol_gt ),
.pipe_rx6_eqlplffs_o ( pipe_rx6_eqlp_lffs_gt ),
.pipe_rx6_eqlptxpreset_o ( pipe_rx6_eqlp_txpreset_gt ),
.pipe_rx6_eqpreset_o ( pipe_rx6_eqpreset_gt ),
.pipe_tx6_eqcoeff_i ( pipe_tx6_eqcoeff_gt ),
.pipe_tx6_eqdone_i ( pipe_tx6_eqdone_gt ),
.pipe_tx6_compliance_o ( pipe_tx6_compliance_gt ),
.pipe_tx6_char_is_k_o ( pipe_tx6_char_is_k_gt ),
.pipe_tx6_data_o ( pipe_tx6_data_gt ),
.pipe_tx6_elec_idle_o ( pipe_tx6_elec_idle_gt ),
.pipe_tx6_powerdown_o ( pipe_tx6_powerdown_gt ),
.pipe_tx6_datavalid_o ( pipe_tx6_data_valid_gt ),
.pipe_tx6_startblock_o ( pipe_tx6_start_block_gt ),
.pipe_tx6_syncheader_o ( pipe_tx6_syncheader_gt ),
.pipe_tx6_eqcontrol_o ( pipe_tx6_eqcontrol_gt ),
.pipe_tx6_eqdeemph_o ( pipe_tx6_eqdeemph_gt ),
.pipe_tx6_eqpreset_o ( pipe_tx6_eqpreset_gt ),
// Pipe Per-Lane Signals - Lane 7
.pipe_rx7_char_is_k_o ( pipe_rx7_char_is_k ),
.pipe_rx7_data_o ( pipe_rx7_data ),
.pipe_rx7_valid_o ( pipe_rx7_valid ),
.pipe_rx7_data_valid_o ( pipe_rx7_data_valid ),
.pipe_rx7_status_o ( pipe_rx7_status ),
.pipe_rx7_phy_status_o ( pipe_rx7_phy_status ),
.pipe_rx7_elec_idle_o ( pipe_rx7_elec_idle ),
.pipe_rx7_eqdone_o ( pipe_rx7_eqdone ),
.pipe_rx7_eqlpadaptdone_o ( pipe_rx7_eqlp_adaptdone ),
.pipe_rx7_eqlplffssel_o ( pipe_rx7_eqlp_lffs_sel ),
.pipe_rx7_eqlpnewtxcoefforpreset_o ( pipe_rx7_eqlp_new_txcoef_forpreset ),
.pipe_rx7_startblock_o ( pipe_rx7_start_block ),
.pipe_rx7_syncheader_o ( pipe_rx7_syncheader ),
.pipe_rx7_polarity_i ( pipe_rx7_polarity ),
.pipe_rx7_eqcontrol_i ( pipe_rx7_eqcontrol ),
.pipe_rx7_eqlplffs_i ( pipe_rx7_eqlp_lffs ),
.pipe_rx7_eqlptxpreset_i ( pipe_rx7_eqlp_txpreset ),
.pipe_rx7_eqpreset_i ( pipe_rx7_eqpreset ),
.pipe_tx7_eqcoeff_o ( pipe_tx7_eqcoeff ),
.pipe_tx7_eqdone_o ( pipe_tx7_eqdone ),
.pipe_tx7_compliance_i ( pipe_tx7_compliance ),
.pipe_tx7_char_is_k_i ( pipe_tx7_char_is_k ),
.pipe_tx7_data_i ( pipe_tx7_data ),
.pipe_tx7_elec_idle_i ( pipe_tx7_elec_idle ),
.pipe_tx7_powerdown_i ( pipe_tx7_powerdown ),
.pipe_tx7_datavalid_i ( pipe_tx7_data_valid ),
.pipe_tx7_startblock_i ( pipe_tx7_start_block ),
.pipe_tx7_syncheader_i ( pipe_tx7_syncheader ),
.pipe_tx7_eqcontrol_i ( pipe_tx7_eqcontrol ),
.pipe_tx7_eqdeemph_i ( pipe_tx7_eqdeemph ),
.pipe_tx7_eqpreset_i ( pipe_tx7_eqpreset ),
.pipe_rx7_char_is_k_i ( pipe_rx7_char_is_k_gt ),
.pipe_rx7_data_i ( pipe_rx7_data_gt ),
.pipe_rx7_valid_i ( pipe_rx7_valid_gt ),
.pipe_rx7_data_valid_i ( pipe_rx7_data_valid_gt ),
.pipe_rx7_status_i ( pipe_rx7_status_gt ),
.pipe_rx7_phy_status_i ( pipe_rx7_phy_status_gt ),
.pipe_rx7_elec_idle_i ( pipe_rx7_elec_idle_gt ),
.pipe_rx7_eqdone_i ( pipe_rx7_eqdone_gt ),
.pipe_rx7_eqlpadaptdone_i ( pipe_rx7_eqlp_adaptdone_gt ),
.pipe_rx7_eqlplffssel_i ( pipe_rx7_eqlp_lffs_sel_gt ),
.pipe_rx7_eqlpnewtxcoefforpreset_i ( pipe_rx7_eqlp_new_txcoef_forpreset_gt ),
.pipe_rx7_startblock_i ( pipe_rx7_start_block_gt ),
.pipe_rx7_syncheader_i ( pipe_rx7_syncheader_gt ),
.pipe_rx7_polarity_o ( pipe_rx7_polarity_gt ),
.pipe_rx7_eqcontrol_o ( pipe_rx7_eqcontrol_gt ),
.pipe_rx7_eqlplffs_o ( pipe_rx7_eqlp_lffs_gt ),
.pipe_rx7_eqlptxpreset_o ( pipe_rx7_eqlp_txpreset_gt ),
.pipe_rx7_eqpreset_o ( pipe_rx7_eqpreset_gt ),
.pipe_tx7_eqcoeff_i ( pipe_tx7_eqcoeff_gt ),
.pipe_tx7_eqdone_i ( pipe_tx7_eqdone_gt ),
.pipe_tx7_compliance_o ( pipe_tx7_compliance_gt ),
.pipe_tx7_char_is_k_o ( pipe_tx7_char_is_k_gt ),
.pipe_tx7_data_o ( pipe_tx7_data_gt ),
.pipe_tx7_elec_idle_o ( pipe_tx7_elec_idle_gt ),
.pipe_tx7_powerdown_o ( pipe_tx7_powerdown_gt ),
.pipe_tx7_datavalid_o ( pipe_tx7_data_valid_gt ),
.pipe_tx7_startblock_o ( pipe_tx7_start_block_gt ),
.pipe_tx7_syncheader_o ( pipe_tx7_syncheader_gt ),
.pipe_tx7_eqcontrol_o ( pipe_tx7_eqcontrol_gt ),
.pipe_tx7_eqdeemph_o ( pipe_tx7_eqdeemph_gt ),
.pipe_tx7_eqpreset_o ( pipe_tx7_eqpreset_gt ),
// Non PIPE signals
.pipe_clk ( pipe_clk ),
.rst_n ( reset_n )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND3B_PP_SYMBOL_V
`define SKY130_FD_SC_HS__NAND3B_PP_SYMBOL_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nand3b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
output Y ,
//# {{power|Power}}
input VPWR,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND3B_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A221O_FUNCTIONAL_V
`define SKY130_FD_SC_HD__A221O_FUNCTIONAL_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a221o (
X ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
or or0 (or0_out_X, and1_out, and0_out, C1);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A221O_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O211AI_2_V
`define SKY130_FD_SC_MS__O211AI_2_V
/**
* o211ai: 2-input OR into first input of 3-input NAND.
*
* Y = !((A1 | A2) & B1 & C1)
*
* Verilog wrapper for o211ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o211ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o211ai_2 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o211ai_2 (
Y ,
A1,
A2,
B1,
C1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o211ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O211AI_2_V
|
// megafunction wizard: %Altera PLL v14.0%
// GENERATION: XML
// audio_clock.v
// Generated using ACDS version 14.0 200 at 2018.07.21.20:09:16
`timescale 1 ps / 1 ps
module audio_clock (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire outclk_1 // outclk1.clk
);
audio_clock_0002 audio_clock_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.outclk_1 (outclk_1), // outclk1.clk
.locked () // (terminated)
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2018 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_pll" version="14.0" >
// Retrieval info: <generic name="debug_print_output" value="false" />
// Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
// Retrieval info: <generic name="device_family" value="Cyclone V" />
// Retrieval info: <generic name="device" value="Unknown" />
// Retrieval info: <generic name="gui_device_speed_grade" value="8" />
// Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
// Retrieval info: <generic name="gui_reference_clock_frequency" value="12.0" />
// Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
// Retrieval info: <generic name="gui_operation_mode" value="direct" />
// Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
// Retrieval info: <generic name="gui_fractional_cout" value="32" />
// Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
// Retrieval info: <generic name="gui_use_locked" value="false" />
// Retrieval info: <generic name="gui_en_adv_params" value="false" />
// Retrieval info: <generic name="gui_number_of_clocks" value="2" />
// Retrieval info: <generic name="gui_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />
// Retrieval info: <generic name="gui_cascade_counter0" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency0" value="3.072" />
// Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units0" value="ps" />
// Retrieval info: <generic name="gui_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_duty_cycle0" value="50" />
// Retrieval info: <generic name="gui_cascade_counter1" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency1" value="1.0" />
// Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units1" value="ps" />
// Retrieval info: <generic name="gui_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_duty_cycle1" value="50" />
// Retrieval info: <generic name="gui_cascade_counter2" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units2" value="ps" />
// Retrieval info: <generic name="gui_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_duty_cycle2" value="50" />
// Retrieval info: <generic name="gui_cascade_counter3" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units3" value="ps" />
// Retrieval info: <generic name="gui_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_duty_cycle3" value="50" />
// Retrieval info: <generic name="gui_cascade_counter4" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units4" value="ps" />
// Retrieval info: <generic name="gui_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_duty_cycle4" value="50" />
// Retrieval info: <generic name="gui_cascade_counter5" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units5" value="ps" />
// Retrieval info: <generic name="gui_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_duty_cycle5" value="50" />
// Retrieval info: <generic name="gui_cascade_counter6" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units6" value="ps" />
// Retrieval info: <generic name="gui_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_duty_cycle6" value="50" />
// Retrieval info: <generic name="gui_cascade_counter7" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units7" value="ps" />
// Retrieval info: <generic name="gui_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_duty_cycle7" value="50" />
// Retrieval info: <generic name="gui_cascade_counter8" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units8" value="ps" />
// Retrieval info: <generic name="gui_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_duty_cycle8" value="50" />
// Retrieval info: <generic name="gui_cascade_counter9" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units9" value="ps" />
// Retrieval info: <generic name="gui_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_duty_cycle9" value="50" />
// Retrieval info: <generic name="gui_cascade_counter10" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units10" value="ps" />
// Retrieval info: <generic name="gui_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_duty_cycle10" value="50" />
// Retrieval info: <generic name="gui_cascade_counter11" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units11" value="ps" />
// Retrieval info: <generic name="gui_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_duty_cycle11" value="50" />
// Retrieval info: <generic name="gui_cascade_counter12" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units12" value="ps" />
// Retrieval info: <generic name="gui_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_duty_cycle12" value="50" />
// Retrieval info: <generic name="gui_cascade_counter13" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units13" value="ps" />
// Retrieval info: <generic name="gui_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_duty_cycle13" value="50" />
// Retrieval info: <generic name="gui_cascade_counter14" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units14" value="ps" />
// Retrieval info: <generic name="gui_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_duty_cycle14" value="50" />
// Retrieval info: <generic name="gui_cascade_counter15" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units15" value="ps" />
// Retrieval info: <generic name="gui_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_duty_cycle15" value="50" />
// Retrieval info: <generic name="gui_cascade_counter16" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units16" value="ps" />
// Retrieval info: <generic name="gui_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_duty_cycle16" value="50" />
// Retrieval info: <generic name="gui_cascade_counter17" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units17" value="ps" />
// Retrieval info: <generic name="gui_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_duty_cycle17" value="50" />
// Retrieval info: <generic name="gui_pll_auto_reset" value="Off" />
// Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
// Retrieval info: <generic name="gui_en_reconf" value="false" />
// Retrieval info: <generic name="gui_en_dps_ports" value="false" />
// Retrieval info: <generic name="gui_en_phout_ports" value="false" />
// Retrieval info: <generic name="gui_phout_division" value="1" />
// Retrieval info: <generic name="gui_en_lvds_ports" value="false" />
// Retrieval info: <generic name="gui_mif_generate" value="false" />
// Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
// Retrieval info: <generic name="gui_dps_cntr" value="C0" />
// Retrieval info: <generic name="gui_dps_num" value="1" />
// Retrieval info: <generic name="gui_dps_dir" value="Positive" />
// Retrieval info: <generic name="gui_refclk_switch" value="false" />
// Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
// Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
// Retrieval info: <generic name="gui_switchover_delay" value="0" />
// Retrieval info: <generic name="gui_active_clk" value="false" />
// Retrieval info: <generic name="gui_clk_bad" value="false" />
// Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
// Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
// Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
// Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
// Retrieval info: <generic name="AUTO_REFCLK_CLOCK_RATE" value="-1" />
// Retrieval info: </instance>
// IPFS_FILES : audio_clock.vo
// RELATED_FILES: audio_clock.v, audio_clock_0002.v
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NAND3_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__NAND3_PP_BLACKBOX_V
/**
* nand3: 3-input NAND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nand3 (
Y ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NAND3_PP_BLACKBOX_V
|
// ============================================================================
// Constant sources
// Reduce logic_0 and logic_1 cells to 1'b0 and 1'b1. Const sources suitable
// for VPR will be added by Yosys during EBLIF write.
module logic_0(output a);
assign a = 0;
endmodule
module logic_1(output a);
assign a = 1;
endmodule
// ============================================================================
// IO and clock buffers
module inpad(output Q, input P);
parameter IO_PAD = "";
parameter IO_LOC = "";
parameter IO_TYPE = "";
generate if (IO_TYPE == "SDIOMUX") begin
SDIOMUX_CELL _TECHMAP_REPLACE_ (
.I_PAD_$inp(P),
.I_DAT(Q),
.I_EN (1'b1),
.O_PAD_$out(),
.O_DAT(),
.O_EN (1'b1)
);
end else begin
BIDIR_CELL # (
.ESEL (1'b1),
.OSEL (1'b1),
.FIXHOLD (1'b0),
.WPD (1'b0),
.DS (1'b0)
) _TECHMAP_REPLACE_ (
.I_PAD_$inp(P),
.I_DAT(Q),
.I_EN (1'b1),
.O_PAD_$out(),
.O_DAT(),
.O_EN (1'b0)
);
end endgenerate
endmodule
module outpad(output P, input A);
parameter IO_PAD = "";
parameter IO_LOC = "";
parameter IO_TYPE = "";
generate if (IO_TYPE == "SDIOMUX") begin
SDIOMUX_CELL _TECHMAP_REPLACE_ (
.I_PAD_$inp(),
.I_DAT(),
.I_EN (1'b1),
.O_PAD_$out(P),
.O_DAT(A),
.O_EN (1'b0)
);
end else begin
BIDIR_CELL # (
.ESEL (1'b1),
.OSEL (1'b1),
.FIXHOLD (1'b0),
.WPD (1'b0),
.DS (1'b0)
) _TECHMAP_REPLACE_ (
.I_PAD_$inp(),
.I_DAT(),
.I_EN (1'b0),
.O_PAD_$out(P),
.O_DAT(A),
.O_EN (1'b1)
);
end endgenerate
endmodule
module bipad(input A, input EN, output Q, inout P);
parameter IO_PAD = "";
parameter IO_LOC = "";
parameter IO_TYPE = "";
generate if (IO_TYPE == "SDIOMUX") begin
wire nEN;
inv INV (
.A(EN),
.Q(nEN)
);
SDIOMUX_CELL SDIOMUX (
.I_PAD_$inp(P),
.I_DAT(Q),
.I_EN (1'b1),
.O_PAD_$out(P),
.O_DAT(A),
.O_EN (nEN)
);
end else begin
BIDIR_CELL # (
.ESEL (1'b1),
.OSEL (1'b1),
.FIXHOLD (1'b0),
.WPD (1'b0),
.DS (1'b0)
) _TECHMAP_REPLACE_ (
.I_PAD_$inp(P),
.I_DAT(Q),
.I_EN (1'b1),
.O_PAD_$out(P),
.O_DAT(A),
.O_EN (EN)
);
end endgenerate
endmodule
module ckpad(output Q, input P);
parameter IO_PAD = "";
parameter IO_LOC = "";
parameter IO_TYPE = "";
// If the IO_TYPE is not set or it is set to CLOCK map the ckpad to a CLOCK
// cell.
generate if (IO_TYPE == "" || IO_TYPE == "CLOCK") begin
// In VPR GMUX has to be explicityl present in the netlist. Add it here.
wire C;
CLOCK_CELL clock (
.I_PAD(P),
.O_CLK(C)
);
GMUX_IP gmux (
.IP (C),
.IZ (Q),
.IS0 (1'b0)
);
// Otherwise make it an inpad cell that gets mapped to BIDIR or SDIOMUX
end else begin
inpad #(
.IO_PAD(IO_PAD),
.IO_LOC(IO_LOC),
.IO_TYPE(IO_TYPE)
) _TECHMAP_REPLACE_ (
.Q(Q),
.P(P)
);
end endgenerate
endmodule
// ============================================================================
module qhsckibuff(input A, output Z);
// The qhsckibuff is used to reach the global clock network from the regular
// routing network. The clock gets inverted.
wire AI;
inv inv (.A(A), .Q(AI));
GMUX_IC gmux (
.IC (AI),
.IZ (Z),
.IS0 (1'b1)
);
endmodule
module qhsckbuff(input A, output Z);
// The qhsckbuff is used to reach the global clock network from the regular
// routing network.
GMUX_IC _TECHMAP_REPLACE_ (
.IC (A),
.IZ (Z),
.IS0 (1'b1)
);
endmodule
module gclkbuff(input A, output Z);
// The gclkbuff is used to reach the global clock network from the regular
// routing network.
GMUX_IC _TECHMAP_REPLACE_ (
.IC (A),
.IZ (Z),
.IS0 (1'b1)
);
endmodule
// ============================================================================
// logic_cell_macro
module logic_cell_macro(
input BA1,
input BA2,
input BAB,
input BAS1,
input BAS2,
input BB1,
input BB2,
input BBS1,
input BBS2,
input BSL,
input F1,
input F2,
input FS,
input QCK,
input QCKS,
input QDI,
input QDS,
input QEN,
input QRT,
input QST,
input TA1,
input TA2,
input TAB,
input TAS1,
input TAS2,
input TB1,
input TB2,
input TBS,
input TBS1,
input TBS2,
input TSL,
output CZ,
output FZ,
output QZ,
output TZ
);
wire [1023:0] _TECHMAP_DO_ = "proc; clean";
parameter _TECHMAP_CONSTMSK_TAS1_ = 1'bx;
parameter _TECHMAP_CONSTVAL_TAS1_ = 1'bx;
parameter _TECHMAP_CONSTMSK_TAS2_ = 1'bx;
parameter _TECHMAP_CONSTVAL_TAS2_ = 1'bx;
parameter _TECHMAP_CONSTMSK_TBS1_ = 1'bx;
parameter _TECHMAP_CONSTVAL_TBS1_ = 1'bx;
parameter _TECHMAP_CONSTMSK_TBS2_ = 1'bx;
parameter _TECHMAP_CONSTVAL_TBS2_ = 1'bx;
parameter _TECHMAP_CONSTMSK_BAS1_ = 1'bx;
parameter _TECHMAP_CONSTVAL_BAS1_ = 1'bx;
parameter _TECHMAP_CONSTMSK_BAS2_ = 1'bx;
parameter _TECHMAP_CONSTVAL_BAS2_ = 1'bx;
parameter _TECHMAP_CONSTMSK_BBS1_ = 1'bx;
parameter _TECHMAP_CONSTVAL_BBS1_ = 1'bx;
parameter _TECHMAP_CONSTMSK_BBS2_ = 1'bx;
parameter _TECHMAP_CONSTVAL_BBS2_ = 1'bx;
parameter _TECHMAP_CONSTMSK_QCKS_ = 1'bx;
parameter _TECHMAP_CONSTVAL_QCKS_ = 1'bx;
localparam [0:0] P_TAS1 = (_TECHMAP_CONSTMSK_TAS1_ == 1'b1) && (_TECHMAP_CONSTVAL_TAS1_ == 1'b1);
localparam [0:0] P_TAS2 = (_TECHMAP_CONSTMSK_TAS2_ == 1'b1) && (_TECHMAP_CONSTVAL_TAS2_ == 1'b1);
localparam [0:0] P_TBS1 = (_TECHMAP_CONSTMSK_TBS1_ == 1'b1) && (_TECHMAP_CONSTVAL_TBS1_ == 1'b1);
localparam [0:0] P_TBS2 = (_TECHMAP_CONSTMSK_TBS2_ == 1'b1) && (_TECHMAP_CONSTVAL_TBS2_ == 1'b1);
localparam [0:0] P_BAS1 = (_TECHMAP_CONSTMSK_BAS1_ == 1'b1) && (_TECHMAP_CONSTVAL_BAS1_ == 1'b1);
localparam [0:0] P_BAS2 = (_TECHMAP_CONSTMSK_BAS2_ == 1'b1) && (_TECHMAP_CONSTVAL_BAS2_ == 1'b1);
localparam [0:0] P_BBS1 = (_TECHMAP_CONSTMSK_BBS1_ == 1'b1) && (_TECHMAP_CONSTVAL_BBS1_ == 1'b1);
localparam [0:0] P_BBS2 = (_TECHMAP_CONSTMSK_BBS2_ == 1'b1) && (_TECHMAP_CONSTVAL_BBS2_ == 1'b1);
localparam [0:0] P_QCKS = (_TECHMAP_CONSTMSK_QCKS_ == 1'b1) && (_TECHMAP_CONSTVAL_QCKS_ == 1'b1);
// Make Yosys fail in case when any of the non-routable ports is connected
// to anything but const.
generate if (_TECHMAP_CONSTMSK_TAS1_ != 1'b1 ||
_TECHMAP_CONSTMSK_TAS2_ != 1'b1 ||
_TECHMAP_CONSTMSK_TBS1_ != 1'b1 ||
_TECHMAP_CONSTMSK_TBS2_ != 1'b1 ||
_TECHMAP_CONSTMSK_BAS1_ != 1'b1 ||
_TECHMAP_CONSTMSK_BAS2_ != 1'b1 ||
_TECHMAP_CONSTMSK_BBS1_ != 1'b1 ||
_TECHMAP_CONSTMSK_BBS2_ != 1'b1 ||
_TECHMAP_CONSTMSK_QCKS_ != 1'b1)
begin
wire _TECHMAP_FAIL_;
end endgenerate
LOGIC_MACRO #
(
.TAS1 (P_TAS1),
.TAS2 (P_TAS2),
.TBS1 (P_TBS1),
.TBS2 (P_TBS2),
.BAS1 (P_BAS1),
.BAS2 (P_BAS2),
.BBS1 (P_BBS1),
.BBS2 (P_BBS2),
.Z_QCKS (!P_QCKS)
) _TECHMAP_REPLACE_ (
.TBS (TBS),
.TAB (TAB),
.TSL (TSL),
.TA1 (TA1),
.TA2 (TA2),
.TB1 (TB1),
.TB2 (TB2),
.BAB (BAB),
.BSL (BSL),
.BA1 (BA1),
.BA2 (BA2),
.BB1 (BB1),
.BB2 (BB2),
.TZ (TZ),
.CZ (CZ),
.QCK (QCK),
.QST (QST),
.QRT (QRT),
.QEN (QEN),
.QDI (QDI),
.QDS (QDS),
.QZ (QZ),
.F1 (F1),
.F2 (F2),
.FS (FS),
.FZ (FZ)
);
endmodule
// ============================================================================
// basic logic elements
module inv (
output Q,
input A,
);
// The F-Frag
F_FRAG f_frag (
.F1(1'b1),
.F2(1'b0),
.FS(A),
.FZ(Q)
);
endmodule
// ============================================================================
// Multiplexers
module mux2x0 (
output Q,
input S,
input A,
input B
);
// The F-Frag
F_FRAG f_frag (
.F1(A),
.F2(B),
.FS(S),
.FZ(Q)
);
endmodule
module mux4x0 (
output Q,
input S0,
input S1,
input A,
input B,
input C,
input D
);
// T_FRAG to be packed either into T_FRAG or B_FRAG.
T_FRAG # (
.XAS1(1'b0),
.XAS2(1'b0),
.XBS1(1'b0),
.XBS2(1'b0)
)
t_frag (
.TBS(1'b1), // Always route to const1
.XAB(S1),
.XSL(S0),
.XA1(A),
.XA2(B),
.XB1(C),
.XB2(D),
.XZ (Q)
);
endmodule
module mux8x0 (
output Q,
input S0,
input S1,
input S2,
input A,
input B,
input C,
input D,
input E,
input F,
input G,
input H
);
C_FRAG # (
.TAS1(1'b0),
.TAS2(1'b0),
.TBS1(1'b0),
.TBS2(1'b0),
.BAS1(1'b0),
.BAS2(1'b0),
.BBS1(1'b0),
.BBS2(1'b0),
)
c_frag (
.TBS(S2),
.TAB(S1),
.TSL(S0),
.TA1(A),
.TA2(B),
.TB1(C),
.TB2(D),
.BAB(S1),
.BSL(S0),
.BA1(E),
.BA2(F),
.BB1(G),
.BB2(H),
.CZ (Q)
);
endmodule
// ============================================================================
// LUTs
module LUT1 (
output O,
input I0
);
parameter [1:0] INIT = 0;
parameter EQN = "(I0)";
// The F-Frag
F_FRAG f_frag (
.F1(INIT[0]),
.F2(INIT[1]),
.FS(I0),
.FZ(O)
);
endmodule
module LUT2 (
output O,
input I0,
input I1
);
parameter [3:0] INIT = 0;
parameter EQN = "(I0)";
wire XSL = I0;
wire XAB = I1;
wire XA1 = INIT[0];
wire XA2 = INIT[1];
wire XB1 = INIT[2];
wire XB2 = INIT[3];
// T_FRAG to be packed either into T_FRAG or B_FRAG.
T_FRAG # (
.XAS1(1'b0),
.XAS2(1'b0),
.XBS1(1'b0),
.XBS2(1'b0)
)
t_frag
(
.TBS(1'b1), // Always route to const1
.XAB(XAB),
.XSL(XSL),
.XA1(XA1),
.XA2(XA2),
.XB1(XB1),
.XB2(XB2),
.XZ (O)
);
endmodule
module LUT3 (
output O,
input I0,
input I1,
input I2
);
parameter [7:0] INIT = 0;
parameter EQN = "(I0)";
wire XSL = I1;
wire XAB = I2;
// Two bit group [H,L]
// H =0: T[AB]S[12] = GND, H=1: VCC
// HL=00: T[AB][12] = GND, HL=11: VCC, else I0
wire XA1;
wire XA2;
wire XB1;
wire XB2;
generate case(INIT[1:0])
2'b00: assign XA1 = 1'b0;
2'b11: assign XA1 = 1'b0;
default: assign XA1 = I0;
endcase endgenerate
generate case(INIT[3:2])
2'b00: assign XA2 = 1'b0;
2'b11: assign XA2 = 1'b0;
default: assign XA2 = I0;
endcase endgenerate
generate case(INIT[5:4])
2'b00: assign XB1 = 1'b0;
2'b11: assign XB1 = 1'b0;
default: assign XB1 = I0;
endcase endgenerate
generate case(INIT[7:6])
2'b00: assign XB2 = 1'b0;
2'b11: assign XB2 = 1'b0;
default: assign XB2 = I0;
endcase endgenerate
localparam XAS1 = INIT[0];
localparam XAS2 = INIT[2];
localparam XBS1 = INIT[4];
localparam XBS2 = INIT[6];
// T_FRAG to be packed either into T_FRAG or B_FRAG.
T_FRAG # (
.XAS1(XAS1),
.XAS2(XAS2),
.XBS1(XBS1),
.XBS2(XBS2)
)
t_frag
(
.TBS(1'b1), // Always route to const1
.XAB(XAB),
.XSL(XSL),
.XA1(XA1),
.XA2(XA2),
.XB1(XB1),
.XB2(XB2),
.XZ (O)
);
endmodule
module LUT4 (
output O,
input I0,
input I1,
input I2,
input I3
);
parameter [15:0] INIT = 0;
parameter EQN = "(I0)";
wire TSL = I1;
wire BSL = I1;
wire TAB = I2;
wire BAB = I2;
wire TBS = I3;
// Two bit group [H,L]
// H =0: [TB][AB]S[12] = GND, H=1: VCC
// HL=00: [TB][AB][12] = GND, HL=11: VCC, else I0
wire TA1;
wire TA2;
wire TB1;
wire TB2;
wire BA1;
wire BA2;
wire BB1;
wire BB2;
generate case(INIT[ 1: 0])
2'b00: assign TA1 = 1'b0;
2'b11: assign TA1 = 1'b0;
default: assign TA1 = I0;
endcase endgenerate
generate case(INIT[ 3: 2])
2'b00: assign TA2 = 1'b0;
2'b11: assign TA2 = 1'b0;
default: assign TA2 = I0;
endcase endgenerate
generate case(INIT[ 5: 4])
2'b00: assign TB1 = 1'b0;
2'b11: assign TB1 = 1'b0;
default: assign TB1 = I0;
endcase endgenerate
generate case(INIT[ 7: 6])
2'b00: assign TB2 = 1'b0;
2'b11: assign TB2 = 1'b0;
default: assign TB2 = I0;
endcase endgenerate
generate case(INIT[ 9: 8])
2'b00: assign BA1 = 1'b0;
2'b11: assign BA1 = 1'b0;
default: assign BA1 = I0;
endcase endgenerate
generate case(INIT[11:10])
2'b00: assign BA2 = 1'b0;
2'b11: assign BA2 = 1'b0;
default: assign BA2 = I0;
endcase endgenerate
generate case(INIT[13:12])
2'b00: assign BB1 = 1'b0;
2'b11: assign BB1 = 1'b0;
default: assign BB1 = I0;
endcase endgenerate
generate case(INIT[15:14])
2'b00: assign BB2 = 1'b0;
2'b11: assign BB2 = 1'b0;
default: assign BB2 = I0;
endcase endgenerate
localparam TAS1 = INIT[ 0];
localparam TAS2 = INIT[ 2];
localparam TBS1 = INIT[ 4];
localparam TBS2 = INIT[ 6];
localparam BAS1 = INIT[ 8];
localparam BAS2 = INIT[10];
localparam BBS1 = INIT[12];
localparam BBS2 = INIT[14];
// The C-Frag
C_FRAG # (
.TAS1(TAS1),
.TAS2(TAS2),
.TBS1(TBS1),
.TBS2(TBS2),
.BAS1(BAS1),
.BAS2(BAS2),
.BBS1(BBS1),
.BBS2(BBS2)
)
c_frag
(
.TBS(TBS),
.TAB(TAB),
.TSL(TSL),
.TA1(TA1),
.TA2(TA2),
.TB1(TB1),
.TB2(TB2),
.BAB(BAB),
.BSL(BSL),
.BA1(BA1),
.BA2(BA2),
.BB1(BB1),
.BB2(BB2),
.CZ (O)
);
endmodule
// ============================================================================
// Flip-Flops
module dff(
output Q,
input D,
input CLK
);
parameter [0:0] INIT = 1'b0;
Q_FRAG # (
.Z_QCKS (1'b1)
)
_TECHMAP_REPLACE_
(
.QCK(CLK),
.QST(1'b0),
.QRT(1'b0),
.QEN(1'b1),
.QD (D),
.QZ (Q),
.CONST0 (1'b0),
.CONST1 (1'b1)
);
endmodule
module dffc(
output Q,
input D,
input CLK,
input CLR
);
parameter [0:0] INIT = 1'b0;
Q_FRAG # (
.Z_QCKS (1'b1)
)
_TECHMAP_REPLACE_
(
.QCK(CLK),
.QST(1'b0),
.QRT(CLR),
.QEN(1'b1),
.QD (D),
.QZ (Q),
.CONST0 (1'b0),
.CONST1 (1'b1)
);
endmodule
module dffp(
output Q,
input D,
input CLK,
input PRE
);
parameter [0:0] INIT = 1'b0;
Q_FRAG # (
.Z_QCKS (1'b1)
)
_TECHMAP_REPLACE_
(
.QCK(CLK),
.QST(PRE),
.QRT(1'b0),
.QEN(1'b1),
.QD (D),
.QZ (Q),
.CONST0 (1'b0),
.CONST1 (1'b1)
);
endmodule
module dffpc(
output Q,
input D,
input CLK,
input CLR,
input PRE
);
parameter [0:0] INIT = 1'b0;
Q_FRAG # (
.Z_QCKS (1'b1)
)
_TECHMAP_REPLACE_
(
.QCK(CLK),
.QST(PRE),
.QRT(CLR),
.QEN(1'b1),
.QD (D),
.QZ (Q),
.CONST0 (1'b0),
.CONST1 (1'b1)
);
endmodule
module dffe(
output Q,
input D,
input CLK,
input EN
);
parameter [0:0] INIT = 1'b0;
Q_FRAG # (
.Z_QCKS (1'b1)
)
_TECHMAP_REPLACE_
(
.QCK(CLK),
.QST(1'b0),
.QRT(1'b0),
.QEN(EN),
.QD (D),
.QZ (Q),
.CONST0 (1'b0),
.CONST1 (1'b1)
);
endmodule
module dffec(
output Q,
input D,
input CLK,
input EN,
input CLR
);
parameter [0:0] INIT = 1'b0;
Q_FRAG # (
.Z_QCKS (1'b1)
)
_TECHMAP_REPLACE_
(
.QCK(CLK),
.QST(1'b0),
.QRT(CLR),
.QEN(EN),
.QD (D),
.QZ (Q),
.CONST0 (1'b0),
.CONST1 (1'b1)
);
endmodule
module dffepc(
output Q,
input D,
input CLK,
input EN,
input CLR,
input PRE
);
parameter [0:0] INIT = 1'b0;
Q_FRAG # (
.Z_QCKS (1'b1)
)
_TECHMAP_REPLACE_
(
.QCK(CLK),
.QST(PRE),
.QRT(CLR),
.QEN(EN),
.QD (D),
.QZ (Q),
.CONST0 (1'b0),
.CONST1 (1'b1)
);
endmodule
module dffsc(
output Q,
input D,
input CLK,
input CLR,
);
parameter [0:0] INIT = 1'b0;
Q_FRAG # (
.Z_QCKS (1'b1)
)
_TECHMAP_REPLACE_
(
.QCK(CLK),
.QST(1'b0),
.QRT(CLR),
.QEN(1'b1),
.QD (D),
.QZ (Q),
.CONST0 (1'b0),
.CONST1 (1'b1)
);
endmodule
// ============================================================================
// The "qlal4s3b_cell_macro" macro
module qlal4s3b_cell_macro (
input WB_CLK,
input WBs_ACK,
input [31:0] WBs_RD_DAT,
output [3:0] WBs_BYTE_STB,
output WBs_CYC,
output WBs_WE,
output WBs_RD,
output WBs_STB,
output [16:0] WBs_ADR,
input [3:0] SDMA_Req,
input [3:0] SDMA_Sreq,
output [3:0] SDMA_Done,
output [3:0] SDMA_Active,
input [3:0] FB_msg_out,
input [7:0] FB_Int_Clr,
output FB_Start,
input FB_Busy,
output WB_RST,
output Sys_PKfb_Rst,
output Clk_C16,
output Clk_C16_Rst,
output Clk_C21,
output Clk_C21_Rst,
output Sys_Pclk,
output Sys_Pclk_Rst,
input Sys_PKfb_Clk,
input [31:0] FB_PKfbData,
output [31:0] WBs_WR_DAT,
input [3:0] FB_PKfbPush,
input FB_PKfbSOF,
input FB_PKfbEOF,
output [7:0] Sensor_Int,
output FB_PKfbOverflow,
output [23:0] TimeStamp,
input Sys_PSel,
input [15:0] SPIm_Paddr,
input SPIm_PEnable,
input SPIm_PWrite,
input [31:0] SPIm_PWdata,
output SPIm_PReady,
output SPIm_PSlvErr,
output [31:0] SPIm_Prdata,
input [15:0] Device_ID,
input [13:0] FBIO_In_En,
input [13:0] FBIO_Out,
input [13:0] FBIO_Out_En,
output [13:0] FBIO_In,
inout [13:0] SFBIO,
input Device_ID_6S,
input Device_ID_4S,
input SPIm_PWdata_26S,
input SPIm_PWdata_24S,
input SPIm_PWdata_14S,
input SPIm_PWdata_11S,
input SPIm_PWdata_0S,
input SPIm_Paddr_8S,
input SPIm_Paddr_6S,
input FB_PKfbPush_1S,
input FB_PKfbData_31S,
input FB_PKfbData_21S,
input FB_PKfbData_19S,
input FB_PKfbData_9S,
input FB_PKfbData_6S,
input Sys_PKfb_ClkS,
input FB_BusyS,
input WB_CLKS
);
ASSP #() _TECHMAP_REPLACE_
(
.WB_CLK (WB_CLK ),
.WBs_ACK (WBs_ACK ),
.WBs_RD_DAT (WBs_RD_DAT ),
.WBs_BYTE_STB (WBs_BYTE_STB ),
.WBs_CYC (WBs_CYC ),
.WBs_WE (WBs_WE ),
.WBs_RD (WBs_RD ),
.WBs_STB (WBs_STB ),
.WBs_ADR (WBs_ADR ),
.SDMA_Req (SDMA_Req ),
.SDMA_Sreq (SDMA_Sreq ),
.SDMA_Done (SDMA_Done ),
.SDMA_Active (SDMA_Active ),
.FB_msg_out (FB_msg_out ),
.FB_Int_Clr (FB_Int_Clr ),
.FB_Start (FB_Start ),
.FB_Busy (FB_Busy ),
.WB_RST (WB_RST ),
.Sys_PKfb_Rst (Sys_PKfb_Rst ),
.Sys_Clk0 (Clk_C16 ),
.Sys_Clk0_Rst (Clk_C16_Rst ),
.Sys_Clk1 (Clk_C21 ),
.Sys_Clk1_Rst (Clk_C21_Rst ),
.Sys_Pclk (Sys_Pclk ),
.Sys_Pclk_Rst (Sys_Pclk_Rst ),
.Sys_PKfb_Clk (Sys_PKfb_Clk ),
.FB_PKfbData (FB_PKfbData ),
.WBs_WR_DAT (WBs_WR_DAT ),
.FB_PKfbPush (FB_PKfbPush ),
.FB_PKfbSOF (FB_PKfbSOF ),
.FB_PKfbEOF (FB_PKfbEOF ),
.Sensor_Int (Sensor_Int ),
.FB_PKfbOverflow (FB_PKfbOverflow),
.TimeStamp (TimeStamp ),
.Sys_PSel (Sys_PSel ),
.SPIm_Paddr (SPIm_Paddr ),
.SPIm_PEnable (SPIm_PEnable ),
.SPIm_PWrite (SPIm_PWrite ),
.SPIm_PWdata (SPIm_PWdata ),
.SPIm_PReady (SPIm_PReady ),
.SPIm_PSlvErr (SPIm_PSlvErr ),
.SPIm_Prdata (SPIm_Prdata ),
.Device_ID (Device_ID )
);
// TODO: The macro "qlal4s3b_cell_macro" has a bunch of non-routable signals
// Figure out what they are responsible for and if there are any bits they
// control.
endmodule
module qlal4s3_mult_32x32_cell (
input [31:0] Amult,
input [31:0] Bmult,
input [1:0] Valid_mult,
output [63:0] Cmult);
MULT #() _TECHMAP_REPLACE_
(
.Amult(Amult),
.Bmult(Bmult),
.Valid_mult(Valid_mult),
.Cmult(Cmult),
.sel_mul_32x32(1'b1)
);
endmodule /* qlal4s3_32x32_mult_cell */
module qlal4s3_mult_16x16_cell (
input [15:0] Amult,
input [15:0] Bmult,
input [1:0] Valid_mult,
output [31:0] Cmult);
wire [31:0] Amult_int;
wire [31:0] Bmult_int;
wire [63:0] Cmult_int;
assign Amult_int = {16'b0, Amult};
assign Bmult_int = {16'b0, Bmult};
assign Cmult = Cmult_int[15:0];
MULT #() _TECHMAP_REPLACE_
(
.Amult(Amult_int),
.Bmult(Bmult_int),
.Valid_mult(Valid_mult),
.Cmult(Cmult_int),
.sel_mul_32x32(1'b0)
);
endmodule /* qlal4s3_16x16_mult_cell */
module qlal4s3_mult_cell_macro(
input [31:0] Amult,
input [31:0] Bmult,
input [1:0] Valid_mult,
input sel_mul_32x32,
output [63:0] Cmult);
MULT #() _TECHMAP_REPLACE_
(
.Amult(Amult),
.Bmult(Bmult),
.Valid_mult(Valid_mult),
.Cmult(Cmult),
.sel_mul_32x32(sel_mul_32x32)
);
endmodule
|
//Define XOR_32bit
module XOR_32bit(out , A ,B);
// I/O port declaration
output [31:0] out;
input [31:0] A,B;
xor c0(out[0],A[0],B[0]);
xor c1(out[1],A[1],B[1]);
xor c2(out[2],A[2],B[2]);
xor c3(out[3],A[3],B[3]);
xor c4(out[4],A[4],B[4]);
xor c5(out[5],A[5],B[5]);
xor c6(out[6],A[6],B[6]);
xor c7(out[7],A[7],B[7]);
xor c8(out[8],A[8],B[8]);
xor c9(out[9],A[9],B[9]);
xor c10(out[10],A[10],B[10]);
xor c11(out[11],A[11],B[11]);
xor c12(out[12],A[12],B[12]);
xor c13(out[13],A[13],B[13]);
xor c14(out[14],A[14],B[14]);
xor c15(out[15],A[15],B[15]);
xor c16(out[16],A[16],B[16]);
xor c17(out[17],A[17],B[17]);
xor c18(out[18],A[18],B[18]);
xor c19(out[19],A[19],B[19]);
xor c20(out[20],A[20],B[20]);
xor c21(out[21],A[21],B[21]);
xor c22(out[22],A[22],B[22]);
xor c23(out[23],A[23],B[23]);
xor c24(out[24],A[24],B[24]);
xor c25(out[25],A[25],B[25]);
xor c26(out[26],A[26],B[26]);
xor c27(out[27],A[27],B[27]);
xor c28(out[28],A[28],B[28]);
xor c29(out[29],A[29],B[29]);
xor c30(out[30],A[30],B[30]);
xor c31(out[31],A[31],B[31]);
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_clock_mux.v
//
// *Module Description:
// Standard clock mux for the openMSP430
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 103 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2011-03-05 15:44:48 +0100 (Sat, 05 Mar 2011) $
//----------------------------------------------------------------------------
module omsp_clock_mux (
// OUTPUTs
clk_out, // Clock output
// INPUTs
clk_in0, // Clock input 0
clk_in1, // Clock input 1
reset, // Reset
scan_mode, // Scan mode (clk_in0 is selected in scan mode)
select // Clock selection
);
// OUTPUTs
//=========
output clk_out; // Clock output
// INPUTs
//=========
input clk_in0; // Clock input 0
input clk_in1; // Clock input 1
input reset; // Reset
input scan_mode; // Scan mode (clk_in0 is selected in scan mode)
input select; // Clock selection
//===========================================================================================================================//
// 1) CLOCK MUX //
//===========================================================================================================================//
// //
// The following (glitch free) clock mux is implemented as following: //
// //
// //
// //
// //
// +-----. +--------+ +--------+ //
// select >>----+-------------O| \ | | | | +-----. //
// | | |---| D Q |---| D Q |--+-------| \ //
// | +-------O| / | | | | | | |O-+ //
// | | +-----' | | | | | +--O| / | //
// | | | /\ | | /\ | | | +-----' | //
// | | +--+--+--+ +--+--+--+ | | | //
// | | O | | | | //
// | | | | | | | +-----. //
// clk_in0 >>----------------------------------+------------+-----------+ +--| \ //
// | | | | |----<< clk_out //
// | | +---------------------------------------+ +--| / //
// | | | | +-----' //
// | +---------------------------------------------+ | //
// | | | | //
// | | +-----. +--------+ +--------+ | | //
// | +-O| \ | | | | | +-----. | //
// | | |---| D Q |---| D Q |--+-------| \ | //
// +--------------| / | | | | | |O-+ //
// +-----' | | | | +--O| / //
// | /\ | | /\ | | +-----' //
// +--+--+--+ +--+--+--+ | //
// O | | //
// | | | //
// clk_in1 >>----------------------------------+------------+-----------+ //
// //
// //
//===========================================================================================================================//
//-----------------------------------------------------------------------------
// Wire declarations
//-----------------------------------------------------------------------------
wire in0_select;
reg in0_select_s;
reg in0_select_ss;
wire in0_enable;
wire in1_select;
reg in1_select_s;
reg in1_select_ss;
wire in1_enable;
wire clk_in0_inv;
wire clk_in1_inv;
wire gated_clk_in0;
wire gated_clk_in1;
//-----------------------------------------------------------------------------
// CLK_IN0 Selection
//-----------------------------------------------------------------------------
assign in0_select = ~select & ~in1_select_ss;
always @ (posedge clk_in0_inv or posedge reset)
if (reset) in0_select_s <= 1'b1;
else in0_select_s <= in0_select;
always @ (posedge clk_in0 or posedge reset)
if (reset) in0_select_ss <= 1'b1;
else in0_select_ss <= in0_select_s;
assign in0_enable = in0_select_ss | scan_mode;
//-----------------------------------------------------------------------------
// CLK_IN1 Selection
//-----------------------------------------------------------------------------
assign in1_select = select & ~in0_select_ss;
always @ (posedge clk_in1_inv or posedge reset)
if (reset) in1_select_s <= 1'b0;
else in1_select_s <= in1_select;
always @ (posedge clk_in1 or posedge reset)
if (reset) in1_select_ss <= 1'b0;
else in1_select_ss <= in1_select_s;
assign in1_enable = in1_select_ss & ~scan_mode;
//-----------------------------------------------------------------------------
// Clock MUX
//-----------------------------------------------------------------------------
//
// IMPORTANT NOTE:
// Because the clock network is a critical part of the design,
// the following combinatorial logic should be replaced with
// direct instanciation of standard cells from target library.
// Don't forget the "dont_touch" attribute to make sure
// synthesis won't mess it up.
//
// Replace with standard cell INVERTER
assign clk_in0_inv = ~clk_in0;
assign clk_in1_inv = ~clk_in1;
// Replace with standard cell NAND2
assign gated_clk_in0 = ~(clk_in0_inv & in0_enable);
assign gated_clk_in1 = ~(clk_in1_inv & in1_enable);
// Replace with standard cell AND2
assign clk_out = (gated_clk_in0 & gated_clk_in1);
endmodule // omsp_clock_gate
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O221A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__O221A_BEHAVIORAL_PP_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o221a (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
and and0 (and0_out_X , or0_out, or1_out, C1 );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O221A_BEHAVIORAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/13/2016 05:51:29 PM
// Design Name:
// Module Name: Testbench_Barrel_Shifter
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Testbench_Barrel_Shifter ();
parameter PERIOD = 10;
parameter EWR=5;
parameter SWR=26;
//inputs
reg clk;
reg rst;
reg load_i;
reg [EWR-1:0] Shift_Value_i;
reg [SWR-1:0] Shift_Data_i;
reg Left_Right_i;
reg Bit_Shift_i;
///////////////////OUTPUT//////////////////////////7
wire [SWR-1:0] N_mant_o;
Barrel_Shifter #(.SWR(SWR),.EWR(EWR)) uut(
.clk(clk),
.rst(rst),
.load_i(load_i),
.Shift_Value_i(Shift_Value_i),
.Shift_Data_i(Shift_Data_i),
.Left_Right_i(Left_Right_i),
.Bit_Shift_i(Bit_Shift_i),
.N_mant_o(N_mant_o)
);
integer Contador_shiftvalue = 0;
always begin
#(5*PERIOD/2) Contador_shiftvalue = Contador_shiftvalue + 1;
Shift_Value_i = Contador_shiftvalue;
#(5*PERIOD/2);
end
always @ (N_mant_o )
begin
$monitor($time,"REA Salida = %b Entrada = %b Numero de Corrimiento: %d",N_mant_o,Shift_Data_i, Shift_Value_i);
$display($time,"TEO Salida = %b Entrada = %b Numero de Corrimiento: %d",(Shift_Data_i>>Shift_Value_i),Shift_Data_i,Shift_Value_i);
end
initial begin
// Initialize Input
rst = 1;
clk = 0;
load_i = 0;
Shift_Value_i = 0;
Shift_Data_i = $random;
Left_Right_i = 0;
Bit_Shift_i = 0;
#40 rst = 0;
load_i = 1;
end
initial begin
clk = 1'b0;
#(PERIOD/2);
forever
#(PERIOD/2) clk = ~clk;
end
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module ddr3_s4_uniphy_example_if0_p0_altdqdqs (
core_clock_in,
reset_n_core_clock_in,
fr_clock_in,
hr_clock_in,
write_strobe_clock_in,
strobe_ena_hr_clock_in,
strobe_ena_clock_in,
capture_strobe_ena,
read_write_data_io,
write_oe_in,
strobe_io,
output_strobe_ena,
strobe_n_io,
oct_ena_in,
read_data_out,
capture_strobe_out,
write_data_in,
extra_write_data_in,
extra_write_data_out,
parallelterminationcontrol_in,
seriesterminationcontrol_in,
config_data_in,
config_update,
config_dqs_ena,
config_io_ena,
config_extra_io_ena,
config_dqs_io_ena,
config_clock_in,
dll_delayctrl_in
);
input [6-1:0] dll_delayctrl_in;
input core_clock_in;
input reset_n_core_clock_in;
input fr_clock_in;
input hr_clock_in;
input write_strobe_clock_in;
input strobe_ena_hr_clock_in;
input strobe_ena_clock_in;
input [2-1:0] capture_strobe_ena;
inout [8-1:0] read_write_data_io;
input [2*8-1:0] write_oe_in;
inout strobe_io;
input [2-1:0] output_strobe_ena;
inout strobe_n_io;
input [2-1:0] oct_ena_in;
output [2 * 1 * 8-1:0] read_data_out;
output capture_strobe_out;
input [2 * 2 * 8-1:0] write_data_in;
input [2 * 2 * 1-1:0] extra_write_data_in;
output [1-1:0] extra_write_data_out;
input [14-1:0] parallelterminationcontrol_in;
input [14-1:0] seriesterminationcontrol_in;
input config_data_in;
input config_update;
input config_dqs_ena;
input [8-1:0] config_io_ena;
input [1-1:0] config_extra_io_ena;
input config_dqs_io_ena;
input config_clock_in;
parameter ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL = "";
altdq_dqs2_ddio_3reg_stratixiv altdq_dqs2_inst (
.core_clock_in( core_clock_in),
.reset_n_core_clock_in (reset_n_core_clock_in),
.fr_clock_in( fr_clock_in),
.hr_clock_in( hr_clock_in),
.write_strobe_clock_in (write_strobe_clock_in),
.strobe_ena_hr_clock_in( strobe_ena_hr_clock_in),
.strobe_ena_clock_in( strobe_ena_clock_in),
.capture_strobe_ena( capture_strobe_ena),
.read_write_data_io( read_write_data_io),
.write_oe_in( write_oe_in),
.strobe_io( strobe_io),
.output_strobe_ena( output_strobe_ena),
.strobe_n_io( strobe_n_io),
.oct_ena_in( oct_ena_in),
.read_data_out( read_data_out),
.capture_strobe_out( capture_strobe_out),
.write_data_in( write_data_in),
.extra_write_data_in( extra_write_data_in),
.extra_write_data_out( extra_write_data_out),
.parallelterminationcontrol_in( parallelterminationcontrol_in),
.seriesterminationcontrol_in( seriesterminationcontrol_in),
.config_data_in( config_data_in),
.config_update( config_update),
.config_dqs_ena( config_dqs_ena),
.config_io_ena( config_io_ena),
.config_extra_io_ena( config_extra_io_ena),
.config_dqs_io_ena( config_dqs_io_ena),
.config_clock_in( config_clock_in),
.dll_delayctrl_in(dll_delayctrl_in)
);
defparam altdq_dqs2_inst.PIN_WIDTH = 8;
defparam altdq_dqs2_inst.PIN_TYPE = "bidir";
defparam altdq_dqs2_inst.USE_INPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_OUTPUT_PHASE_ALIGNMENT = "true";
defparam altdq_dqs2_inst.USE_LDC_AS_LOW_SKEW_CLOCK = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_INPUT = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_OUTPUT = "true";
defparam altdq_dqs2_inst.DIFFERENTIAL_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SEPARATE_CAPTURE_STROBE = "false";
defparam altdq_dqs2_inst.INPUT_FREQ = 533;
defparam altdq_dqs2_inst.INPUT_FREQ_PS = "1876 ps";
defparam altdq_dqs2_inst.DELAY_CHAIN_BUFFER_MODE = "HIGH";
defparam altdq_dqs2_inst.DQS_PHASE_SETTING = 2;
defparam altdq_dqs2_inst.DQS_PHASE_SHIFT = 9000;
defparam altdq_dqs2_inst.DQS_ENABLE_PHASE_SETTING = 0;
defparam altdq_dqs2_inst.USE_DYNAMIC_CONFIG = "true";
defparam altdq_dqs2_inst.INVERT_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.USE_TERMINATION_CONTROL = "true";
defparam altdq_dqs2_inst.USE_DQS_ENABLE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE_RESET = "false";
defparam altdq_dqs2_inst.DIFFERENTIAL_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_BIDIR_STROBE = "true";
defparam altdq_dqs2_inst.REVERSE_READ_WORDS = "false";
defparam altdq_dqs2_inst.EXTRA_OUTPUT_WIDTH = 1;
defparam altdq_dqs2_inst.DYNAMIC_MODE = "dynamic";
defparam altdq_dqs2_inst.OCT_SERIES_TERM_CONTROL_WIDTH = 14;
defparam altdq_dqs2_inst.OCT_PARALLEL_TERM_CONTROL_WIDTH = 14;
defparam altdq_dqs2_inst.DLL_WIDTH = 6;
defparam altdq_dqs2_inst.USE_DATA_OE_FOR_OCT = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_WIDTH = 2;
defparam altdq_dqs2_inst.USE_OCT_ENA_IN_FOR_OCT = "true";
defparam altdq_dqs2_inst.PREAMBLE_TYPE = "high";
defparam altdq_dqs2_inst.USE_OFFSET_CTRL = "false";
defparam altdq_dqs2_inst.HR_DDIO_OUT_HAS_THREE_REGS = "true";
defparam altdq_dqs2_inst.DQS_ENABLE_PHASECTRL = "true";
defparam altdq_dqs2_inst.USE_2X_FF = "false";
defparam altdq_dqs2_inst.DLL_USE_2X_CLK = "false";
defparam altdq_dqs2_inst.USE_DQS_TRACKING = "false";
defparam altdq_dqs2_inst.CALIBRATION_SUPPORT = "false";
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2004 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Output Buffer
// /___/ /\ Filename : OBUF.v
// \ \ / \ Timestamp : Thu Mar 25 16:42:59 PST 2004
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 02/22/06 - CR#226003 - Added integer, real parameter type
// 05/23/07 - Changed timescale to 1 ps / 1 ps.
`timescale 1 ps / 1 ps
`celldefine
module OBUF (O, I);
parameter CAPACITANCE = "DONT_CARE";
parameter integer DRIVE = 12;
parameter IOSTANDARD = "DEFAULT";
`ifdef XIL_TIMING
parameter LOC = " UNPLACED";
`endif
parameter SLEW = "SLOW";
output O;
input I;
tri0 GTS = glbl.GTS;
bufif0 B1 (O, I, GTS);
initial begin
case (CAPACITANCE)
"LOW", "NORMAL", "DONT_CARE" : ;
default : begin
$display("Attribute Syntax Error : The attribute CAPACITANCE on OBUF instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
#1 $finish;
end
endcase
end
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: O.87xd
// \ \ Application: netgen
// / / Filename: fifo_36x512_hf.v
// /___/ /\ Timestamp: Thu Nov 8 18:41:46 2012
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_36x512_hf.ngc /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_36x512_hf.v
// Device : 5vlx330ff1760-1
// Input file : /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_36x512_hf.ngc
// Output file : /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_36x512_hf.v
// # of Modules : 1
// Design Name : fifo_36x512_hf
// Xilinx : /remote/Xilinx/13.4/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module fifo_36x512_hf (
clk, rd_en, rst, empty, wr_en, full, prog_empty, prog_full, dout, din
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
input rd_en;
input rst;
output empty;
input wr_en;
output full;
output prog_empty;
output prog_full;
output [35 : 0] dout;
input [35 : 0] din;
// synthesis translate_off
wire N0;
wire N2;
wire \U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/Mshreg_power_on_wr_rst_0_3 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_reg_10 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/prog_empty_fifo ;
wire \U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/prog_empty_q_12 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/prog_full_fifo ;
wire \U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/prog_full_q_14 ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_RDERR_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_WRERR_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_RDCOUNT<8>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_RDCOUNT<7>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_RDCOUNT<6>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_RDCOUNT<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_RDCOUNT<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_RDCOUNT<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_RDCOUNT<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_RDCOUNT<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_RDCOUNT<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_WRCOUNT<8>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_WRCOUNT<7>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_WRCOUNT<6>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_WRCOUNT<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_WRCOUNT<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_WRCOUNT<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_WRCOUNT<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_WRCOUNT<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_WRCOUNT<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/Mshreg_power_on_wr_rst_0_Q15_UNCONNECTED ;
wire [0 : 0] \U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rd_rst_i ;
wire [0 : 0] \U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/power_on_wr_rst ;
wire [4 : 0] \U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb ;
assign
prog_empty = \U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/prog_empty_q_12 ,
prog_full = \U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/prog_full_q_14 ;
GND XST_GND (
.G(N0)
);
FDPE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_reg (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb [0]),
.D(N0),
.PRE(rst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_reg_10 )
);
FD #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb_4 (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_reg_10 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb [4])
);
FD #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb_3 (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb [4]),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb [3])
);
FD #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb_2 (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb [3]),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb [2])
);
FD #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb_1 (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb [2]),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb [1])
);
FD #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb_0 (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb [1]),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_fb [0])
);
FIFO18_36 #(
.ALMOST_FULL_OFFSET ( 9'h006 ),
.SIM_MODE ( "SAFE" ),
.DO_REG ( 0 ),
.EN_SYN ( "TRUE" ),
.FIRST_WORD_FALL_THROUGH ( "FALSE" ),
.ALMOST_EMPTY_OFFSET ( 9'h100 ))
\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18 (
.RDEN(rd_en),
.WREN(wr_en),
.RST(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rd_rst_i [0]),
.RDCLK(clk),
.WRCLK(clk),
.ALMOSTEMPTY(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/prog_empty_fifo ),
.ALMOSTFULL(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/prog_full_fifo ),
.EMPTY(empty),
.FULL(full),
.RDERR(\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_RDERR_UNCONNECTED ),
.WRERR(\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_WRERR_UNCONNECTED ),
.DI({din[31], din[30], din[29], din[28], din[27], din[26], din[25], din[24], din[23], din[22], din[21], din[20], din[19], din[18], din[17],
din[16], din[15], din[14], din[13], din[12], din[11], din[10], din[9], din[8], din[7], din[6], din[5], din[4], din[3], din[2], din[1], din[0]}),
.DIP({din[35], din[34], din[33], din[32]}),
.DO({dout[31], dout[30], dout[29], dout[28], dout[27], dout[26], dout[25], dout[24], dout[23], dout[22], dout[21], dout[20], dout[19], dout[18],
dout[17], dout[16], dout[15], dout[14], dout[13], dout[12], dout[11], dout[10], dout[9], dout[8], dout[7], dout[6], dout[5], dout[4], dout[3], dout[2]
, dout[1], dout[0]}),
.DOP({dout[35], dout[34], dout[33], dout[32]}),
.RDCOUNT({\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_RDCOUNT<8>_UNCONNECTED
, \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_RDCOUNT<7>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_RDCOUNT<6>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_RDCOUNT<5>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_RDCOUNT<4>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_RDCOUNT<3>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_RDCOUNT<2>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_RDCOUNT<1>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_RDCOUNT<0>_UNCONNECTED }),
.WRCOUNT({\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_WRCOUNT<8>_UNCONNECTED
, \NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_WRCOUNT<7>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_WRCOUNT<6>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_WRCOUNT<5>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_WRCOUNT<4>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_WRCOUNT<3>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_WRCOUNT<2>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_WRCOUNT<1>_UNCONNECTED ,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/gw36.sngfifo18_WRCOUNT<0>_UNCONNECTED })
);
FDP #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/prog_empty_q (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/prog_empty_fifo ),
.PRE(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rd_rst_i [0]),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/prog_empty_q_12 )
);
FDC #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/prog_full_q (
.C(clk),
.CLR(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rd_rst_i [0]),
.D(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/prog_full_fifo ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/v5_fifo.fblk/gextw[1].inst_extd/gonep.inst_prim/prog_full_q_14 )
);
LUT2 #(
.INIT ( 4'hE ))
\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/RD_RST_I<1>1 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/wr_rst_reg_10 ),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/power_on_wr_rst [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rd_rst_i [0])
);
VCC XST_VCC (
.P(N2)
);
SRLC16E #(
.INIT ( 16'h001F ))
\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/Mshreg_power_on_wr_rst_0 (
.A0(N0),
.A1(N0),
.A2(N2),
.A3(N0),
.CE(N2),
.CLK(clk),
.D(N0),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/Mshreg_power_on_wr_rst_0_3 ),
.Q15(\NLW_U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/Mshreg_power_on_wr_rst_0_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/power_on_wr_rst_0 (
.C(clk),
.CE(N2),
.D(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/Mshreg_power_on_wr_rst_0_3 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/gbiv5.bi/rstbt/power_on_wr_rst [0])
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFBBN_FUNCTIONAL_V
`define SKY130_FD_SC_MS__DFBBN_FUNCTIONAL_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr/sky130_fd_sc_ms__udp_dff_nsr.v"
`celldefine
module sky130_fd_sc_ms__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Local signals
wire RESET;
wire SET ;
wire CLK ;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
not not2 (CLK , CLK_N );
sky130_fd_sc_ms__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D);
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFBBN_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S15KAPWR_BLACKBOX_V
`define SKY130_FD_SC_LP__DLYBUF4S15KAPWR_BLACKBOX_V
/**
* dlybuf4s15kapwr: Delay Buffer 4-stage 0.15um length inner stage
* gates on keep-alive power rail.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlybuf4s15kapwr (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S15KAPWR_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PR_PP_PKG_S_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_DFF_PR_PP_PKG_S_BLACKBOX_V
/**
* udp_dff$PR_pp$PKG$s: Positive edge triggered D flip-flop with
* active high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$PR_pp$PKG$s (
Q ,
D ,
CLK ,
RESET ,
SLEEP_B,
KAPWR ,
VGND ,
VPWR
);
output Q ;
input D ;
input CLK ;
input RESET ;
input SLEEP_B;
input KAPWR ;
input VGND ;
input VPWR ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PR_PP_PKG_S_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A211O_PP_SYMBOL_V
`define SKY130_FD_SC_MS__A211O_PP_SYMBOL_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a211o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input C1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A211O_PP_SYMBOL_V
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: read_posted_fifo.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This module instantiated by read_data_path module and sits between
// mcb_flow_control module and read_data_gen module to buffer up the
// commands that has sent to memory controller.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module read_posted_fifo #
(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter MEM_BURST_LEN = 4,
parameter ADDR_WIDTH = 32,
parameter BL_WIDTH = 6
)
(
input clk_i,
input rst_i,
output reg cmd_rdy_o,
input memc_cmd_full_i,
input cmd_valid_i,
input data_valid_i,
input cmd_start_i,
input [ADDR_WIDTH-1:0] addr_i,
input [BL_WIDTH-1:0] bl_i,
input [2:0] cmd_sent,
input [5:0] bl_sent ,
input cmd_en_i ,
output gen_valid_o,
output [ADDR_WIDTH-1:0] gen_addr_o,
output [BL_WIDTH-1:0] gen_bl_o,
output rd_mdata_en
);
//reg empty_r;
reg [10:0] INC_COUNTS;
reg rd_en_r;
wire full;
wire empty;
wire wr_en;
reg mcb_rd_fifo_port_almost_full;
reg [6:0] buf_avail_r;
reg [6:0] rd_data_received_counts;
reg [6:0] rd_data_counts_asked;
reg dfifo_has_enough_room;
reg [1:0] wait_cnt;
reg wait_done;
assign rd_mdata_en = rd_en_r;
generate
if (FAMILY == "SPARTAN6")
begin: gen_sp6_cmd_rdy
always @ (posedge clk_i)
cmd_rdy_o <= #TCQ !full & dfifo_has_enough_room ;//& wait_done;
end
// if ((FAMILY == "VIRTEX7") || (FAMILY == "7SERIES") || (FAMILY == "KINTEX7") || (FAMILY == "ARTIX7") ||
// (FAMILY == "VIRTEX6") )
else
begin: gen_v6_cmd_rdy
always @ (posedge clk_i)
cmd_rdy_o <= #TCQ !full & wait_done & dfifo_has_enough_room;
end
endgenerate
always @ (posedge clk_i)
begin
if (rst_i)
wait_cnt <= #TCQ 'b0;
else if (cmd_rdy_o && cmd_valid_i)
wait_cnt <= #TCQ 2'b10;
else if (wait_cnt > 0)
wait_cnt <= #TCQ wait_cnt - 1'b1;
end
always @(posedge clk_i)
begin
if (rst_i)
wait_done <= #TCQ 1'b1;
else if (cmd_rdy_o && cmd_valid_i)
wait_done <= #TCQ 1'b0;
else if (wait_cnt == 0)
wait_done <= #TCQ 1'b1;
else
wait_done <= #TCQ 1'b0;
end
reg dfifo_has_enough_room_d1;
always @ (posedge clk_i)
begin
dfifo_has_enough_room <= #TCQ (buf_avail_r >= 32 ) ? 1'b1: 1'b0;
dfifo_has_enough_room_d1 <= #TCQ dfifo_has_enough_room ;
end
// remove the dfifo_has_enough_room term. Just need to push pressure to the front to stop
// sending more read commands but still accepting it if there is one coming.
assign wr_en = cmd_valid_i & !full & wait_done;
/*localparam MEM_BURST_INT = MEM_BURST_LEN ;
generate
if (FAMILY == "VIRTEX6" ) begin : INC_COUNTS_V
always @ (posedge clk_i) begin
if ( (NUM_DQ_PINS >= 128 && NUM_DQ_PINS <= 144)) //256
INC_COUNTS <= #TCQ 64 * (MEM_BURST_INT/4);
else if ( (NUM_DQ_PINS >= 64 && NUM_DQ_PINS < 128)) //256
INC_COUNTS <= #TCQ 32 * (MEM_BURST_INT/4);
else if ((NUM_DQ_PINS >= 32) && (NUM_DQ_PINS < 64)) //128
INC_COUNTS <= #TCQ 16 * (MEM_BURST_INT/4) ;
else if ((NUM_DQ_PINS == 16) || (NUM_DQ_PINS == 24)) //64
INC_COUNTS <= #TCQ 8 * (MEM_BURST_INT/4);
else if ((NUM_DQ_PINS == 8) )
INC_COUNTS <= #TCQ 4 * (MEM_BURST_INT/4);
end
end
endgenerate
*/
always @ (posedge clk_i)
begin
if (rst_i) begin
rd_data_counts_asked <= #TCQ 'b0;
end
else if (cmd_en_i && cmd_sent[0] == 1 && ~memc_cmd_full_i) begin
// if (FAMILY == "SPARTAN6)
// rd_data_counts_asked <= #TCQ rd_data_counts_asked + (bl_sent + 7'b0000001) ;
// else
// begin
// if (MEM_BURST_LEN == 8)
rd_data_counts_asked <= #TCQ rd_data_counts_asked + 1'b1 ;
end
end
always @ (posedge clk_i)
begin
if (rst_i) begin
rd_data_received_counts <= #TCQ 'b0;
end
else if (data_valid_i) begin
rd_data_received_counts <= #TCQ rd_data_received_counts + 1'b1;
end
end
// calculate how many buf still available
always @ (posedge clk_i)
if (rd_data_received_counts[6] == rd_data_counts_asked[6])
buf_avail_r <= #TCQ (rd_data_received_counts[5:0] - rd_data_counts_asked[5:0] + 7'd64 );
else
buf_avail_r <= #TCQ ( rd_data_received_counts[5:0] - rd_data_counts_asked[5:0] );
always @ (posedge clk_i) begin
rd_en_r <= #TCQ cmd_start_i;
end
assign gen_valid_o = !empty;
afifo #
(
.TCQ (TCQ),
.DSIZE (BL_WIDTH+ADDR_WIDTH),
.FIFO_DEPTH (16),
.ASIZE (4),
.SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency
)
rd_fifo
(
.wr_clk (clk_i),
.rst (rst_i),
.wr_en (wr_en),
.wr_data ({bl_i,addr_i}),
.rd_en (rd_en_r),
.rd_clk (clk_i),
.rd_data ({gen_bl_o,gen_addr_o}),
.full (full),
.empty (empty),
.almost_full ()
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__FA_TB_V
`define SKY130_FD_SC_LP__FA_TB_V
/**
* fa: Full adder.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__fa.v"
module top();
// Inputs are registered
reg A;
reg B;
reg CIN;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire COUT;
wire SUM;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
CIN = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 CIN = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 CIN = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 CIN = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 CIN = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 CIN = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_lp__fa dut (.A(A), .B(B), .CIN(CIN), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .COUT(COUT), .SUM(SUM));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__FA_TB_V
|
`include "timescale.vh"
module hello (
input resn, // Reset, active low.
input clk,
output serialOut // The serial output.
);
// UART TX testing "Hello World!"
reg wr;
wire [7:0] char;
reg [3:0] state;
wire empty;
reg [3:0] messageIdx;
rom message (
.addr(messageIdx),
.clk(clk),
.q(char)
);
uartTx t1 (
.resn(resn), // Reset, active low.
.clk(clk), // Clock, (Use 50Mhz for 115200 baud).
.wr(wr), // Writes data to holding register on rising clock
.data(char), // Data to be transmitted.
.serialOut(serialOut), // The serial outout.
.empty(empty) // TRUE when ready to accept next character.
);
always @(posedge clk or negedge resn)
begin
if (!resn) begin
state <= 0;
wr <= 0;
messageIdx <= 0;
end else begin
case (state)
0 : begin
messageIdx <= messageIdx + 1;
wr <= 1;
state <= 1;
end
1: begin
wr <= 0;
state <= 2;
end
2: begin
if (empty == 1) begin
state <= 0;
end
end
default : ;
endcase
end
end
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* Ethernet multiplexer
*/
module eth_mux #
(
parameter S_COUNT = 4,
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
parameter ID_ENABLE = 0,
parameter ID_WIDTH = 8,
parameter DEST_ENABLE = 0,
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1
)
(
input wire clk,
input wire rst,
/*
* Ethernet frame inputs
*/
input wire [S_COUNT-1:0] s_eth_hdr_valid,
output wire [S_COUNT-1:0] s_eth_hdr_ready,
input wire [S_COUNT*48-1:0] s_eth_dest_mac,
input wire [S_COUNT*48-1:0] s_eth_src_mac,
input wire [S_COUNT*16-1:0] s_eth_type,
input wire [S_COUNT*DATA_WIDTH-1:0] s_eth_payload_axis_tdata,
input wire [S_COUNT*KEEP_WIDTH-1:0] s_eth_payload_axis_tkeep,
input wire [S_COUNT-1:0] s_eth_payload_axis_tvalid,
output wire [S_COUNT-1:0] s_eth_payload_axis_tready,
input wire [S_COUNT-1:0] s_eth_payload_axis_tlast,
input wire [S_COUNT*ID_WIDTH-1:0] s_eth_payload_axis_tid,
input wire [S_COUNT*DEST_WIDTH-1:0] s_eth_payload_axis_tdest,
input wire [S_COUNT*USER_WIDTH-1:0] s_eth_payload_axis_tuser,
/*
* Ethernet frame output
*/
output wire m_eth_hdr_valid,
input wire m_eth_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [DATA_WIDTH-1:0] m_eth_payload_axis_tdata,
output wire [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep,
output wire m_eth_payload_axis_tvalid,
input wire m_eth_payload_axis_tready,
output wire m_eth_payload_axis_tlast,
output wire [ID_WIDTH-1:0] m_eth_payload_axis_tid,
output wire [DEST_WIDTH-1:0] m_eth_payload_axis_tdest,
output wire [USER_WIDTH-1:0] m_eth_payload_axis_tuser,
/*
* Control
*/
input wire enable,
input wire [$clog2(S_COUNT)-1:0] select
);
parameter CL_S_COUNT = $clog2(S_COUNT);
reg [CL_S_COUNT-1:0] select_reg = 2'd0, select_next;
reg frame_reg = 1'b0, frame_next;
reg [S_COUNT-1:0] s_eth_hdr_ready_reg = 0, s_eth_hdr_ready_next;
reg [S_COUNT-1:0] s_eth_payload_axis_tready_reg = 0, s_eth_payload_axis_tready_next;
reg m_eth_hdr_valid_reg = 1'b0, m_eth_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0, m_eth_dest_mac_next;
reg [47:0] m_eth_src_mac_reg = 48'd0, m_eth_src_mac_next;
reg [15:0] m_eth_type_reg = 16'd0, m_eth_type_next;
// internal datapath
reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_int;
reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_int;
reg m_eth_payload_axis_tvalid_int;
reg m_eth_payload_axis_tready_int_reg = 1'b0;
reg m_eth_payload_axis_tlast_int;
reg [ID_WIDTH-1:0] m_eth_payload_axis_tid_int;
reg [DEST_WIDTH-1:0] m_eth_payload_axis_tdest_int;
reg [USER_WIDTH-1:0] m_eth_payload_axis_tuser_int;
wire m_eth_payload_axis_tready_int_early;
assign s_eth_hdr_ready = s_eth_hdr_ready_reg;
assign s_eth_payload_axis_tready = s_eth_payload_axis_tready_reg;
assign m_eth_hdr_valid = m_eth_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
// mux for incoming packet
wire [DATA_WIDTH-1:0] current_s_tdata = s_eth_payload_axis_tdata[select_reg*DATA_WIDTH +: DATA_WIDTH];
wire [KEEP_WIDTH-1:0] current_s_tkeep = s_eth_payload_axis_tkeep[select_reg*KEEP_WIDTH +: KEEP_WIDTH];
wire current_s_tvalid = s_eth_payload_axis_tvalid[select_reg];
wire current_s_tready = s_eth_payload_axis_tready[select_reg];
wire current_s_tlast = s_eth_payload_axis_tlast[select_reg];
wire [ID_WIDTH-1:0] current_s_tid = s_eth_payload_axis_tid[select_reg*ID_WIDTH +: ID_WIDTH];
wire [DEST_WIDTH-1:0] current_s_tdest = s_eth_payload_axis_tdest[select_reg*DEST_WIDTH +: DEST_WIDTH];
wire [USER_WIDTH-1:0] current_s_tuser = s_eth_payload_axis_tuser[select_reg*USER_WIDTH +: USER_WIDTH];
always @* begin
select_next = select_reg;
frame_next = frame_reg;
s_eth_hdr_ready_next = 0;
s_eth_payload_axis_tready_next = 0;
m_eth_hdr_valid_next = m_eth_hdr_valid_reg && !m_eth_hdr_ready;
m_eth_dest_mac_next = m_eth_dest_mac_reg;
m_eth_src_mac_next = m_eth_src_mac_reg;
m_eth_type_next = m_eth_type_reg;
if (current_s_tvalid & current_s_tready) begin
// end of frame detection
if (current_s_tlast) begin
frame_next = 1'b0;
end
end
if (!frame_reg && enable && !m_eth_hdr_valid && (s_eth_hdr_valid & (1 << select))) begin
// start of frame, grab select value
frame_next = 1'b1;
select_next = select;
s_eth_hdr_ready_next = (1 << select);
m_eth_hdr_valid_next = 1'b1;
m_eth_dest_mac_next = s_eth_dest_mac[select*48 +: 48];
m_eth_src_mac_next = s_eth_src_mac[select*48 +: 48];
m_eth_type_next = s_eth_type[select*16 +: 16];
end
// generate ready signal on selected port
s_eth_payload_axis_tready_next = (m_eth_payload_axis_tready_int_early && frame_next) << select_next;
// pass through selected packet data
m_eth_payload_axis_tdata_int = current_s_tdata;
m_eth_payload_axis_tkeep_int = current_s_tkeep;
m_eth_payload_axis_tvalid_int = current_s_tvalid && current_s_tready && frame_reg;
m_eth_payload_axis_tlast_int = current_s_tlast;
m_eth_payload_axis_tid_int = current_s_tid;
m_eth_payload_axis_tdest_int = current_s_tdest;
m_eth_payload_axis_tuser_int = current_s_tuser;
end
always @(posedge clk) begin
if (rst) begin
select_reg <= 0;
frame_reg <= 1'b0;
s_eth_hdr_ready_reg <= 0;
s_eth_payload_axis_tready_reg <= 0;
m_eth_hdr_valid_reg <= 1'b0;
end else begin
select_reg <= select_next;
frame_reg <= frame_next;
s_eth_hdr_ready_reg <= s_eth_hdr_ready_next;
s_eth_payload_axis_tready_reg <= s_eth_payload_axis_tready_next;
m_eth_hdr_valid_reg <= m_eth_hdr_valid_next;
end
m_eth_dest_mac_reg <= m_eth_dest_mac_next;
m_eth_src_mac_reg <= m_eth_src_mac_next;
m_eth_type_reg <= m_eth_type_next;
end
// output datapath logic
reg [DATA_WIDTH-1:0] m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg m_eth_payload_axis_tvalid_reg = 1'b0, m_eth_payload_axis_tvalid_next;
reg m_eth_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] m_eth_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] m_eth_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] m_eth_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
reg [DATA_WIDTH-1:0] temp_m_eth_payload_axis_tdata_reg = {DATA_WIDTH{1'b0}};
reg [KEEP_WIDTH-1:0] temp_m_eth_payload_axis_tkeep_reg = {KEEP_WIDTH{1'b0}};
reg temp_m_eth_payload_axis_tvalid_reg = 1'b0, temp_m_eth_payload_axis_tvalid_next;
reg temp_m_eth_payload_axis_tlast_reg = 1'b0;
reg [ID_WIDTH-1:0] temp_m_eth_payload_axis_tid_reg = {ID_WIDTH{1'b0}};
reg [DEST_WIDTH-1:0] temp_m_eth_payload_axis_tdest_reg = {DEST_WIDTH{1'b0}};
reg [USER_WIDTH-1:0] temp_m_eth_payload_axis_tuser_reg = {USER_WIDTH{1'b0}};
// datapath control
reg store_axis_int_to_output;
reg store_axis_int_to_temp;
reg store_axis_temp_to_output;
assign m_eth_payload_axis_tdata = m_eth_payload_axis_tdata_reg;
assign m_eth_payload_axis_tkeep = KEEP_ENABLE ? m_eth_payload_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
assign m_eth_payload_axis_tvalid = m_eth_payload_axis_tvalid_reg;
assign m_eth_payload_axis_tlast = m_eth_payload_axis_tlast_reg;
assign m_eth_payload_axis_tid = ID_ENABLE ? m_eth_payload_axis_tid_reg : {ID_WIDTH{1'b0}};
assign m_eth_payload_axis_tdest = DEST_ENABLE ? m_eth_payload_axis_tdest_reg : {DEST_WIDTH{1'b0}};
assign m_eth_payload_axis_tuser = USER_ENABLE ? m_eth_payload_axis_tuser_reg : {USER_WIDTH{1'b0}};
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_eth_payload_axis_tready_int_early = m_eth_payload_axis_tready || (!temp_m_eth_payload_axis_tvalid_reg && (!m_eth_payload_axis_tvalid_reg || !m_eth_payload_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
store_axis_int_to_output = 1'b0;
store_axis_int_to_temp = 1'b0;
store_axis_temp_to_output = 1'b0;
if (m_eth_payload_axis_tready_int_reg) begin
// input is ready
if (m_eth_payload_axis_tready || !m_eth_payload_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_axis_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_eth_payload_axis_tvalid_next = m_eth_payload_axis_tvalid_int;
store_axis_int_to_temp = 1'b1;
end
end else if (m_eth_payload_axis_tready) begin
// input is not ready, but output is ready
m_eth_payload_axis_tvalid_next = temp_m_eth_payload_axis_tvalid_reg;
temp_m_eth_payload_axis_tvalid_next = 1'b0;
store_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_eth_payload_axis_tvalid_reg <= 1'b0;
m_eth_payload_axis_tready_int_reg <= 1'b0;
temp_m_eth_payload_axis_tvalid_reg <= 1'b0;
end else begin
m_eth_payload_axis_tvalid_reg <= m_eth_payload_axis_tvalid_next;
m_eth_payload_axis_tready_int_reg <= m_eth_payload_axis_tready_int_early;
temp_m_eth_payload_axis_tvalid_reg <= temp_m_eth_payload_axis_tvalid_next;
end
// datapath
if (store_axis_int_to_output) begin
m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
m_eth_payload_axis_tid_reg <= m_eth_payload_axis_tid_int;
m_eth_payload_axis_tdest_reg <= m_eth_payload_axis_tdest_int;
m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end else if (store_axis_temp_to_output) begin
m_eth_payload_axis_tdata_reg <= temp_m_eth_payload_axis_tdata_reg;
m_eth_payload_axis_tkeep_reg <= temp_m_eth_payload_axis_tkeep_reg;
m_eth_payload_axis_tlast_reg <= temp_m_eth_payload_axis_tlast_reg;
m_eth_payload_axis_tid_reg <= temp_m_eth_payload_axis_tid_reg;
m_eth_payload_axis_tdest_reg <= temp_m_eth_payload_axis_tdest_reg;
m_eth_payload_axis_tuser_reg <= temp_m_eth_payload_axis_tuser_reg;
end
if (store_axis_int_to_temp) begin
temp_m_eth_payload_axis_tdata_reg <= m_eth_payload_axis_tdata_int;
temp_m_eth_payload_axis_tkeep_reg <= m_eth_payload_axis_tkeep_int;
temp_m_eth_payload_axis_tlast_reg <= m_eth_payload_axis_tlast_int;
temp_m_eth_payload_axis_tid_reg <= m_eth_payload_axis_tid_int;
temp_m_eth_payload_axis_tdest_reg <= m_eth_payload_axis_tdest_int;
temp_m_eth_payload_axis_tuser_reg <= m_eth_payload_axis_tuser_int;
end
end
endmodule
`resetall
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_wishbone.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// ////
//// All additional information is available in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_wishbone.v,v $
// Revision 1.58 2005/03/21 20:07:18 igorm
// Some small fixes + some troubles fixed.
//
// Revision 1.57 2005/02/21 11:35:33 igorm
// Defer indication fixed.
//
// Revision 1.56 2004/04/30 10:30:00 igorm
// Accidently deleted line put back.
//
// Revision 1.55 2004/04/26 15:26:23 igorm
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
// previous update of the core.
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
// register. (thanks to Mathias and Torbjorn)
// - Multicast reception was fixed. Thanks to Ulrich Gries
//
// Revision 1.54 2003/11/12 18:24:59 tadejm
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
//
// Revision 1.53 2003/10/17 07:46:17 markom
// mbist signals updated according to newest convention
//
// Revision 1.52 2003/01/30 14:51:31 mohor
// Reset has priority in some flipflops.
//
// Revision 1.51 2003/01/30 13:36:22 mohor
// A new bug (entered with previous update) fixed. When abort occured sometimes
// data transmission was blocked.
//
// Revision 1.50 2003/01/22 13:49:26 tadejm
// When control packets were received, they were ignored in some cases.
//
// Revision 1.49 2003/01/21 12:09:40 mohor
// When receiving normal data frame and RxFlow control was switched on, RXB
// interrupt was not set.
//
// Revision 1.48 2003/01/20 12:05:26 mohor
// When in full duplex, transmit was sometimes blocked. Fixed.
//
// Revision 1.47 2002/11/22 13:26:21 mohor
// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
// anywhere. Removed.
//
// Revision 1.46 2002/11/22 01:57:06 mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.45 2002/11/19 17:33:34 mohor
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
// that a frame was received because of the promiscous mode.
//
// Revision 1.44 2002/11/13 22:21:40 tadejm
// RxError is not generated when small frame reception is enabled and small
// frames are received.
//
// Revision 1.43 2002/10/18 20:53:34 mohor
// case changed to casex.
//
// Revision 1.42 2002/10/18 17:04:20 tadejm
// Changed BIST scan signals.
//
// Revision 1.41 2002/10/18 15:42:09 tadejm
// Igor added WB burst support and repaired BUG when handling TX under-run and retry.
//
// Revision 1.40 2002/10/14 16:07:02 mohor
// TxStatus is written after last access to the TX fifo is finished (in case of abort
// or retry). TxDone is fixed.
//
// Revision 1.39 2002/10/11 15:35:20 mohor
// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
// TxDone and TxRetry are generated after the current WISHBONE access is
// finished.
//
// Revision 1.38 2002/10/10 16:29:30 mohor
// BIST added.
//
// Revision 1.37 2002/09/11 14:18:46 mohor
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
//
// Revision 1.36 2002/09/10 13:48:46 mohor
// Reception is possible after RxPointer is read and not after BD is read. For
// that reason RxBDReady is changed to RxReady.
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
// comes, interrupt is generated.
//
// Revision 1.35 2002/09/10 10:35:23 mohor
// Ethernet debug registers removed.
//
// Revision 1.34 2002/09/08 16:31:49 mohor
// Async reset for WB_ACK_O removed (when core was in reset, it was
// impossible to access BDs).
// RxPointers and TxPointers names changed to be more descriptive.
// TxUnderRun synchronized.
//
// Revision 1.33 2002/09/04 18:47:57 mohor
// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
// was not used OK.
//
// Revision 1.32 2002/08/14 19:31:48 mohor
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
// need to multiply or devide any more.
//
// Revision 1.31 2002/07/25 18:29:01 mohor
// WriteRxDataToMemory signal changed so end of frame (when last word is
// written to fifo) is changed.
//
// Revision 1.30 2002/07/23 15:28:31 mohor
// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
//
// Revision 1.29 2002/07/20 00:41:32 mohor
// ShiftEnded synchronization changed.
//
// Revision 1.28 2002/07/18 16:11:46 mohor
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
//
// Revision 1.27 2002/07/11 02:53:20 mohor
// RxPointer bug fixed.
//
// Revision 1.26 2002/07/10 13:12:38 mohor
// Previous bug wasn't succesfully removed. Now fixed.
//
// Revision 1.25 2002/07/09 23:53:24 mohor
// Master state machine had a bug when switching from master write to
// master read.
//
// Revision 1.24 2002/07/09 20:44:41 mohor
// m_wb_cyc_o signal released after every single transfer.
//
// Revision 1.23 2002/05/03 10:15:50 mohor
// Outputs registered. Reset changed for eth_wishbone module.
//
// Revision 1.22 2002/04/24 08:52:19 mohor
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
// bug fixed.
//
// Revision 1.21 2002/03/29 16:18:11 lampret
// Small typo fixed.
//
// Revision 1.20 2002/03/25 16:19:12 mohor
// Any address can be used for Tx and Rx BD pointers. Address does not need
// to be aligned.
//
// Revision 1.19 2002/03/19 12:51:50 mohor
// Comments in Slovene language removed.
//
// Revision 1.18 2002/03/19 12:46:52 mohor
// casex changed with case, fifo reset changed.
//
// Revision 1.17 2002/03/09 16:08:45 mohor
// rx_fifo was not always cleared ok. Fixed.
//
// Revision 1.16 2002/03/09 13:51:20 mohor
// Status was not latched correctly sometimes. Fixed.
//
// Revision 1.15 2002/03/08 06:56:46 mohor
// Big Endian problem when sending frames fixed.
//
// Revision 1.14 2002/03/02 19:12:40 mohor
// Byte ordering changed (Big Endian used). casex changed with case because
// Xilinx Foundation had problems. Tested in HW. It WORKS.
//
// Revision 1.13 2002/02/26 16:59:55 mohor
// Small fixes for external/internal DMA missmatches.
//
// Revision 1.12 2002/02/26 16:22:07 mohor
// Interrupts changed
//
// Revision 1.11 2002/02/15 17:07:39 mohor
// Status was not written correctly when frames were discarted because of
// address mismatch.
//
// Revision 1.10 2002/02/15 12:17:39 mohor
// RxStartFrm cleared when abort or retry comes.
//
// Revision 1.9 2002/02/15 11:59:10 mohor
// Changes that were lost when updating from 1.5 to 1.8 fixed.
//
// Revision 1.8 2002/02/14 20:54:33 billditt
// Addition of new module eth_addrcheck.v
//
// Revision 1.7 2002/02/12 17:03:47 mohor
// RxOverRun added to statuses.
//
// Revision 1.6 2002/02/11 09:18:22 mohor
// Tx status is written back to the BD.
//
// Revision 1.5 2002/02/08 16:21:54 mohor
// Rx status is written back to the BD.
//
// Revision 1.4 2002/02/06 14:10:21 mohor
// non-DMA host interface added. Select the right configutation in eth_defines.
//
// Revision 1.3 2002/02/05 16:44:39 mohor
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
// MHz. Statuses, overrun, control frame transmission and reception still need
// to be fixed.
//
// Revision 1.2 2002/02/01 12:46:51 mohor
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
// added.
//
// Revision 1.1 2002/01/23 10:47:59 mohor
// Initial version. Equals to eth_wishbonedma.v at this moment.
//
//
//
`include "eth_defines.v"
`include "timescale.v"
module eth_wishbone
(
// WISHBONE common
WB_CLK_I, WB_DAT_I, WB_DAT_O,
// WISHBONE slave
WB_ADR_I, WB_WE_I, WB_ACK_O,
BDCs,
Reset,
// WISHBONE master
m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
`ifdef ETH_WISHBONE_B3
m_wb_cti_o, m_wb_bte_o,
`endif
//TX
MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
PerPacketPad,
//RX
MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, RxStatusWriteLatched_sync2,
// Register
r_TxEn, r_RxEn, r_TxBDNum, r_RxFlow, r_PassAll,
// Interrupts
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
// Rx Status
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,
ReceivedPauseFrm,
// Tx Status
RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, RstDeferLatched, CarrierSenseLost
// Bist
`ifdef ETH_BIST
,
// debug chain signals
mbist_si_i, // bist scan serial in
mbist_so_o, // bist scan serial out
mbist_ctrl_i // bist chain shift control
`endif
);
parameter Tp = 1;
// WISHBONE common
input WB_CLK_I; // WISHBONE clock
input [31:0] WB_DAT_I; // WISHBONE data input
output [31:0] WB_DAT_O; // WISHBONE data output
// WISHBONE slave
input [9:2] WB_ADR_I; // WISHBONE address input
input WB_WE_I; // WISHBONE write enable input
input [3:0] BDCs; // Buffer descriptors are selected
output WB_ACK_O; // WISHBONE acknowledge output
// WISHBONE master
output [29:0] m_wb_adr_o; //
output [3:0] m_wb_sel_o; //
output m_wb_we_o; //
output [31:0] m_wb_dat_o; //
output m_wb_cyc_o; //
output m_wb_stb_o; //
input [31:0] m_wb_dat_i; //
input m_wb_ack_i; //
input m_wb_err_i; //
`ifdef ETH_WISHBONE_B3
output [2:0] m_wb_cti_o; // Cycle Type Identifier
output [1:0] m_wb_bte_o; // Burst Type Extension
reg [2:0] m_wb_cti_o; // Cycle Type Identifier
`endif
input Reset; // Reset signal
// Rx Status signals
input InvalidSymbol; // Invalid symbol was received during reception in 100 Mbps mode
input LatchedCrcError; // CRC error
input RxLateCollision; // Late collision occured while receiving frame
input ShortFrame; // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
input DribbleNibble; // Extra nibble received
input ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
input [15:0] RxLength; // Length of the incoming frame
input LoadRxStatus; // Rx status was loaded
input ReceivedPacketGood;// Received packet's length and CRC are good
input AddressMiss; // When a packet is received AddressMiss status is written to the Rx BD
input r_RxFlow;
input r_PassAll;
input ReceivedPauseFrm;
// Tx Status signals
input [3:0] RetryCntLatched; // Latched Retry Counter
input RetryLimit; // Retry limit reached (Retry Max value + 1 attempts were made)
input LateCollLatched; // Late collision occured
input DeferLatched; // Defer indication (Frame was defered before sucessfully sent)
output RstDeferLatched;
input CarrierSenseLost; // Carrier Sense was lost during the frame transmission
// Tx
input MTxClk; // Transmit clock (from PHY)
input TxUsedData; // Transmit packet used data
input TxRetry; // Transmit packet retry
input TxAbort; // Transmit packet abort
input TxDone; // Transmission ended
output TxStartFrm; // Transmit packet start frame
output TxEndFrm; // Transmit packet end frame
output [7:0] TxData; // Transmit packet data byte
output TxUnderRun; // Transmit packet under-run
output PerPacketCrcEn; // Per packet crc enable
output PerPacketPad; // Per packet pading
// Rx
input MRxClk; // Receive clock (from PHY)
input [7:0] RxData; // Received data byte (from PHY)
input RxValid; //
input RxStartFrm; //
input RxEndFrm; //
input RxAbort; // This signal is set when address doesn't match.
output RxStatusWriteLatched_sync2;
//Register
input r_TxEn; // Transmit enable
input r_RxEn; // Receive enable
input [7:0] r_TxBDNum; // Receive buffer descriptor number
// Interrupts
output TxB_IRQ;
output TxE_IRQ;
output RxB_IRQ;
output RxE_IRQ;
output Busy_IRQ;
// Bist
`ifdef ETH_BIST
input mbist_si_i; // bist scan serial in
output mbist_so_o; // bist scan serial out
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
`endif
reg TxB_IRQ;
reg TxE_IRQ;
reg RxB_IRQ;
reg RxE_IRQ;
reg TxStartFrm;
reg TxEndFrm;
reg [7:0] TxData;
reg TxUnderRun;
reg TxUnderRun_wb;
reg TxBDRead;
wire TxStatusWrite;
reg [1:0] TxValidBytesLatched;
reg [15:0] TxLength;
reg [15:0] LatchedTxLength;
reg [14:11] TxStatus;
reg [14:13] RxStatus;
reg TxStartFrm_wb;
reg TxRetry_wb;
reg TxAbort_wb;
reg TxDone_wb;
reg TxDone_wb_q;
reg TxAbort_wb_q;
reg TxRetry_wb_q;
reg TxRetryPacket;
reg TxRetryPacket_NotCleared;
reg TxDonePacket;
reg TxDonePacket_NotCleared;
reg TxAbortPacket;
reg TxAbortPacket_NotCleared;
reg RxBDReady;
reg RxReady;
reg TxBDReady;
reg RxBDRead;
reg [31:0] TxDataLatched;
reg [1:0] TxByteCnt;
reg LastWord;
reg ReadTxDataFromFifo_tck;
reg BlockingTxStatusWrite;
reg BlockingTxBDRead;
reg Flop;
reg [7:1] TxBDAddress;
reg [7:1] RxBDAddress;
reg TxRetrySync1;
reg TxAbortSync1;
reg TxDoneSync1;
reg TxAbort_q;
reg TxRetry_q;
reg TxUsedData_q;
reg [31:0] RxDataLatched2;
reg [31:8] RxDataLatched1; // Big Endian Byte Ordering
reg [1:0] RxValidBytes;
reg [1:0] RxByteCnt;
reg LastByteIn;
reg ShiftWillEnd;
reg WriteRxDataToFifo;
reg [15:0] LatchedRxLength;
reg RxAbortLatched;
reg ShiftEnded;
reg RxOverrun;
reg [3:0] BDWrite; // BD Write Enable for access from WISHBONE side
reg BDRead; // BD Read access from WISHBONE side
wire [31:0] RxBDDataIn; // Rx BD data in
wire [31:0] TxBDDataIn; // Tx BD data in
reg TxEndFrm_wb;
wire TxRetryPulse;
wire TxDonePulse;
wire TxAbortPulse;
wire StartRxBDRead;
wire StartTxBDRead;
wire TxIRQEn;
wire WrapTxStatusBit;
wire RxIRQEn;
wire WrapRxStatusBit;
wire [1:0] TxValidBytes;
wire [7:1] TempTxBDAddress;
wire [7:1] TempRxBDAddress;
wire RxStatusWrite;
wire RxBufferFull;
wire RxBufferAlmostEmpty;
wire RxBufferEmpty;
reg WB_ACK_O;
wire [8:0] RxStatusIn;
reg [8:0] RxStatusInLatched;
reg WbEn, WbEn_q;
reg RxEn, RxEn_q;
reg TxEn, TxEn_q;
reg r_TxEn_q;
reg r_RxEn_q;
wire ram_ce;
wire [3:0] ram_we;
wire ram_oe;
reg [7:0] ram_addr;
reg [31:0] ram_di;
wire [31:0] ram_do;
wire StartTxPointerRead;
reg TxPointerRead;
reg TxEn_needed;
reg RxEn_needed;
wire StartRxPointerRead;
reg RxPointerRead;
`ifdef ETH_WISHBONE_B3
assign m_wb_bte_o = 2'b00; // Linear burst
`endif
assign m_wb_stb_o = m_wb_cyc_o;
always @ (posedge WB_CLK_I)
begin
WB_ACK_O <=#Tp (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
end
assign WB_DAT_O = ram_do;
// Generic synchronous single-port RAM interface
eth_spram_256x32 bd_ram (
.clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
`ifdef ETH_BIST
,
.mbist_si_i (mbist_si_i),
.mbist_so_o (mbist_so_o),
.mbist_ctrl_i (mbist_ctrl_i)
`endif
);
assign ram_ce = 1'b1;
assign ram_we = (BDWrite & {4{(WbEn & WbEn_q)}}) | {4{(TxStatusWrite | RxStatusWrite)}};
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxEn_needed <=#Tp 1'b0;
else
if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
TxEn_needed <=#Tp 1'b1;
else
if(TxPointerRead & TxEn & TxEn_q)
TxEn_needed <=#Tp 1'b0;
end
// Enabling access to the RAM for three devices.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
begin
WbEn <=#Tp 1'b1;
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b0;
ram_addr <=#Tp 8'h0;
ram_di <=#Tp 32'h0;
BDRead <=#Tp 1'b0;
BDWrite <=#Tp 1'b0;
end
else
begin
// Switching between three stages depends on enable signals
case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case
5'b100_10, 5'b100_11 :
begin
WbEn <=#Tp 1'b0;
RxEn <=#Tp 1'b1; // wb access stage and r_RxEn is enabled
TxEn <=#Tp 1'b0;
ram_addr <=#Tp {RxBDAddress, RxPointerRead};
ram_di <=#Tp RxBDDataIn;
end
5'b100_01 :
begin
WbEn <=#Tp 1'b0;
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b1; // wb access stage, r_RxEn is disabled but r_TxEn is enabled
ram_addr <=#Tp {TxBDAddress, TxPointerRead};
ram_di <=#Tp TxBDDataIn;
end
5'b010_00, 5'b010_10 :
begin
WbEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is disabled
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b0;
ram_addr <=#Tp WB_ADR_I[9:2];
ram_di <=#Tp WB_DAT_I;
BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
BDRead <=#Tp (|BDCs) & ~WB_WE_I;
end
5'b010_01, 5'b010_11 :
begin
WbEn <=#Tp 1'b0;
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is enabled
ram_addr <=#Tp {TxBDAddress, TxPointerRead};
ram_di <=#Tp TxBDDataIn;
end
5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
begin
WbEn <=#Tp 1'b1; // TxEn access stage (we always go to wb access stage)
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b0;
ram_addr <=#Tp WB_ADR_I[9:2];
ram_di <=#Tp WB_DAT_I;
BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
BDRead <=#Tp (|BDCs) & ~WB_WE_I;
end
5'b100_00 :
begin
WbEn <=#Tp 1'b0; // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
end
5'b000_00 :
begin
WbEn <=#Tp 1'b1; // Idle state. We go to WbEn access stage.
RxEn <=#Tp 1'b0;
TxEn <=#Tp 1'b0;
ram_addr <=#Tp WB_ADR_I[9:2];
ram_di <=#Tp WB_DAT_I;
BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
BDRead <=#Tp (|BDCs) & ~WB_WE_I;
end
endcase
end
end
// Delayed stage signals
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
begin
WbEn_q <=#Tp 1'b0;
RxEn_q <=#Tp 1'b0;
TxEn_q <=#Tp 1'b0;
r_TxEn_q <=#Tp 1'b0;
r_RxEn_q <=#Tp 1'b0;
end
else
begin
WbEn_q <=#Tp WbEn;
RxEn_q <=#Tp RxEn;
TxEn_q <=#Tp TxEn;
r_TxEn_q <=#Tp r_TxEn;
r_RxEn_q <=#Tp r_RxEn;
end
end
// Changes for tx occur every second clock. Flop is used for this manner.
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
Flop <=#Tp 1'b0;
else
if(TxDone | TxAbort | TxRetry_q)
Flop <=#Tp 1'b0;
else
if(TxUsedData)
Flop <=#Tp ~Flop;
end
wire ResetTxBDReady;
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
// Latching READY status of the Tx buffer descriptor
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxBDReady <=#Tp 1'b0;
else
if(TxEn & TxEn_q & TxBDRead)
TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.
else // Only packets larger then 4 bytes are transmitted.
if(ResetTxBDReady)
TxBDReady <=#Tp 1'b0;
end
// Reading the Tx buffer descriptor
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxBDRead <=#Tp 1'b1;
else
if(StartTxBDRead)
TxBDRead <=#Tp 1'b1;
else
if(TxBDReady)
TxBDRead <=#Tp 1'b0;
end
// Reading Tx BD pointer
assign StartTxPointerRead = TxBDRead & TxBDReady;
// Reading Tx BD Pointer
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxPointerRead <=#Tp 1'b0;
else
if(StartTxPointerRead)
TxPointerRead <=#Tp 1'b1;
else
if(TxEn_q)
TxPointerRead <=#Tp 1'b0;
end
// Writing status back to the Tx buffer descriptor
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
// Status writing must occur only once. Meanwhile it is blocked.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
BlockingTxStatusWrite <=#Tp 1'b0;
else
if(~TxDone_wb & ~TxAbort_wb)
BlockingTxStatusWrite <=#Tp 1'b0;
else
if(TxStatusWrite)
BlockingTxStatusWrite <=#Tp 1'b1;
end
reg BlockingTxStatusWrite_sync1;
reg BlockingTxStatusWrite_sync2;
reg BlockingTxStatusWrite_sync3;
// Synchronizing BlockingTxStatusWrite to MTxClk
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
BlockingTxStatusWrite_sync1 <=#Tp 1'b0;
else
BlockingTxStatusWrite_sync1 <=#Tp BlockingTxStatusWrite;
end
// Synchronizing BlockingTxStatusWrite to MTxClk
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
BlockingTxStatusWrite_sync2 <=#Tp 1'b0;
else
BlockingTxStatusWrite_sync2 <=#Tp BlockingTxStatusWrite_sync1;
end
// Synchronizing BlockingTxStatusWrite to MTxClk
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
BlockingTxStatusWrite_sync3 <=#Tp 1'b0;
else
BlockingTxStatusWrite_sync3 <=#Tp BlockingTxStatusWrite_sync2;
end
assign RstDeferLatched = BlockingTxStatusWrite_sync2 & ~BlockingTxStatusWrite_sync3;
// TxBDRead state is activated only once.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
BlockingTxBDRead <=#Tp 1'b0;
else
if(StartTxBDRead)
BlockingTxBDRead <=#Tp 1'b1;
else
if(~StartTxBDRead & ~TxBDReady)
BlockingTxBDRead <=#Tp 1'b0;
end
// Latching status from the tx buffer descriptor
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxStatus <=#Tp 4'h0;
else
if(TxEn & TxEn_q & TxBDRead)
TxStatus <=#Tp ram_do[14:11];
end
reg ReadTxDataFromMemory;
wire WriteRxDataToMemory;
reg MasterWbTX;
reg MasterWbRX;
reg [29:0] m_wb_adr_o;
reg m_wb_cyc_o;
reg [3:0] m_wb_sel_o;
reg m_wb_we_o;
wire TxLengthEq0;
wire TxLengthLt4;
reg BlockingIncrementTxPointer;
reg [31:2] TxPointerMSB;
reg [1:0] TxPointerLSB;
reg [1:0] TxPointerLSB_rst;
reg [31:2] RxPointerMSB;
reg [1:0] RxPointerLSB_rst;
wire RxBurstAcc;
wire RxWordAcc;
wire RxHalfAcc;
wire RxByteAcc;
//Latching length from the buffer descriptor;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxLength <=#Tp 16'h0;
else
if(TxEn & TxEn_q & TxBDRead)
TxLength <=#Tp ram_do[31:16];
else
if(MasterWbTX & m_wb_ack_i)
begin
if(TxLengthLt4)
TxLength <=#Tp 16'h0;
else
if(TxPointerLSB_rst==2'h0)
TxLength <=#Tp TxLength - 3'h4; // Length is subtracted at the data request
else
if(TxPointerLSB_rst==2'h1)
TxLength <=#Tp TxLength - 3'h3; // Length is subtracted at the data request
else
if(TxPointerLSB_rst==2'h2)
TxLength <=#Tp TxLength - 3'h2; // Length is subtracted at the data request
else
if(TxPointerLSB_rst==2'h3)
TxLength <=#Tp TxLength - 3'h1; // Length is subtracted at the data request
end
end
//Latching length from the buffer descriptor;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
LatchedTxLength <=#Tp 16'h0;
else
if(TxEn & TxEn_q & TxBDRead)
LatchedTxLength <=#Tp ram_do[31:16];
end
assign TxLengthEq0 = TxLength == 0;
assign TxLengthLt4 = TxLength < 4;
reg cyc_cleared;
reg IncrTxPointer;
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched
// because TxPointerMSB is only used for word-aligned accesses.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxPointerMSB <=#Tp 30'h0;
else
if(TxEn & TxEn_q & TxPointerRead)
TxPointerMSB <=#Tp ram_do[31:2];
else
if(IncrTxPointer & ~BlockingIncrementTxPointer)
TxPointerMSB <=#Tp TxPointerMSB + 1'b1; // TxPointer is word-aligned
end
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed,
// valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This
// signals are used for proper selection of the start byte (TxData and TxByteCnt) are
// set by this two bits.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxPointerLSB[1:0] <=#Tp 0;
else
if(TxEn & TxEn_q & TxPointerRead)
TxPointerLSB[1:0] <=#Tp ram_do[1:0];
end
// Latching 2 MSB bits of the buffer descriptor.
// After the read access, TxLength needs to be decremented for the number of the valid
// bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are
// valid so this two bits are reset to zero.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxPointerLSB_rst[1:0] <=#Tp 0;
else
if(TxEn & TxEn_q & TxPointerRead)
TxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
else
if(MasterWbTX & m_wb_ack_i) // After first access pointer is word alligned
TxPointerLSB_rst[1:0] <=#Tp 0;
end
reg [3:0] RxByteSel;
wire MasterAccessFinished;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
BlockingIncrementTxPointer <=#Tp 0;
else
if(MasterAccessFinished)
BlockingIncrementTxPointer <=#Tp 0;
else
if(IncrTxPointer)
BlockingIncrementTxPointer <=#Tp 1'b1;
end
wire TxBufferAlmostFull;
wire TxBufferFull;
wire TxBufferEmpty;
wire TxBufferAlmostEmpty;
wire SetReadTxDataFromMemory;
reg BlockReadTxDataFromMemory;
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ReadTxDataFromMemory <=#Tp 1'b0;
else
if(TxLengthEq0 | TxAbortPulse | TxRetryPulse)
ReadTxDataFromMemory <=#Tp 1'b0;
else
if(SetReadTxDataFromMemory)
ReadTxDataFromMemory <=#Tp 1'b1;
end
reg tx_burst_en;
reg rx_burst_en;
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory;
wire tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
wire [31:0] TxData_wb;
wire ReadTxDataFromFifo_wb;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
BlockReadTxDataFromMemory <=#Tp 1'b0;
else
if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (~cyc_cleared) & (!(TxAbortPacket_NotCleared | TxRetryPacket_NotCleared)))
BlockReadTxDataFromMemory <=#Tp 1'b1;
else
if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
BlockReadTxDataFromMemory <=#Tp 1'b0;
end
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
reg [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
reg [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
wire rx_burst;
wire enough_data_in_rxfifo_for_burst;
wire enough_data_in_rxfifo_for_burst_plus1;
// Enabling master wishbone access to the memory for two devices TX and RX.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
begin
MasterWbTX <=#Tp 1'b0;
MasterWbRX <=#Tp 1'b0;
m_wb_adr_o <=#Tp 30'h0;
m_wb_cyc_o <=#Tp 1'b0;
m_wb_we_o <=#Tp 1'b0;
m_wb_sel_o <=#Tp 4'h0;
cyc_cleared<=#Tp 1'b0;
tx_burst_cnt<=#Tp 0;
rx_burst_cnt<=#Tp 0;
IncrTxPointer<=#Tp 1'b0;
tx_burst_en<=#Tp 1'b1;
rx_burst_en<=#Tp 1'b0;
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b0;
`endif
end
else
begin
// Switching between two stages depends on enable signals
casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared, tx_burst, rx_burst}) // synopsys parallel_case
8'b00_10_00_10, // Idle and MRB needed
8'b10_1x_10_1x, // MRB continues
8'b10_10_01_10, // Clear (previously MR) and MRB needed
8'b01_1x_01_1x : // Clear (previously MW) and MRB needed
begin
MasterWbTX <=#Tp 1'b1; // tx burst
MasterWbRX <=#Tp 1'b0;
m_wb_cyc_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b0;
m_wb_sel_o <=#Tp 4'hf;
cyc_cleared<=#Tp 1'b0;
IncrTxPointer<=#Tp 1'b1;
tx_burst_cnt <=#Tp tx_burst_cnt+3'h1;
if(tx_burst_cnt==0)
m_wb_adr_o <=#Tp TxPointerMSB;
else
m_wb_adr_o <=#Tp m_wb_adr_o+1'b1;
if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
begin
tx_burst_en<=#Tp 1'b0;
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b111;
`endif
end
else
begin
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b010;
`endif
end
end
8'b00_x1_00_x1, // Idle and MWB needed
8'b01_x1_10_x1, // MWB continues
8'b01_01_01_01, // Clear (previously MW) and MWB needed
8'b10_x1_01_x1 : // Clear (previously MR) and MWB needed
begin
MasterWbTX <=#Tp 1'b0; // rx burst
MasterWbRX <=#Tp 1'b1;
m_wb_cyc_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b1;
m_wb_sel_o <=#Tp RxByteSel;
IncrTxPointer<=#Tp 1'b0;
cyc_cleared<=#Tp 1'b0;
rx_burst_cnt <=#Tp rx_burst_cnt+3'h1;
if(rx_burst_cnt==0)
m_wb_adr_o <=#Tp RxPointerMSB;
else
m_wb_adr_o <=#Tp m_wb_adr_o+1'b1;
if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
begin
rx_burst_en<=#Tp 1'b0;
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b111;
`endif
end
else
begin
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b010;
`endif
end
end
8'b00_x1_00_x0 : // idle and MW is needed (data write to rx buffer)
begin
MasterWbTX <=#Tp 1'b0;
MasterWbRX <=#Tp 1'b1;
m_wb_adr_o <=#Tp RxPointerMSB;
m_wb_cyc_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b1;
m_wb_sel_o <=#Tp RxByteSel;
IncrTxPointer<=#Tp 1'b0;
end
8'b00_10_00_00 : // idle and MR is needed (data read from tx buffer)
begin
MasterWbTX <=#Tp 1'b1;
MasterWbRX <=#Tp 1'b0;
m_wb_adr_o <=#Tp TxPointerMSB;
m_wb_cyc_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b0;
m_wb_sel_o <=#Tp 4'hf;
IncrTxPointer<=#Tp 1'b1;
end
8'b10_10_01_00, // MR and MR is needed (data read from tx buffer)
8'b01_1x_01_0x : // MW and MR is needed (data read from tx buffer)
begin
MasterWbTX <=#Tp 1'b1;
MasterWbRX <=#Tp 1'b0;
m_wb_adr_o <=#Tp TxPointerMSB;
m_wb_cyc_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b0;
m_wb_sel_o <=#Tp 4'hf;
cyc_cleared<=#Tp 1'b0;
IncrTxPointer<=#Tp 1'b1;
end
8'b01_01_01_00, // MW and MW needed (data write to rx buffer)
8'b10_x1_01_x0 : // MR and MW is needed (data write to rx buffer)
begin
MasterWbTX <=#Tp 1'b0;
MasterWbRX <=#Tp 1'b1;
m_wb_adr_o <=#Tp RxPointerMSB;
m_wb_cyc_o <=#Tp 1'b1;
m_wb_we_o <=#Tp 1'b1;
m_wb_sel_o <=#Tp RxByteSel;
cyc_cleared<=#Tp 1'b0;
IncrTxPointer<=#Tp 1'b0;
end
8'b01_01_10_00, // MW and MW needed (cycle is cleared between previous and next access)
8'b01_1x_10_x0, // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
8'b10_10_10_00, // MR and MR needed (cycle is cleared between previous and next access)
8'b10_x1_10_0x : // MR and MR or MW or MWB (cycle is cleared between previous and next access)
begin
m_wb_cyc_o <=#Tp 1'b0; // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
cyc_cleared<=#Tp 1'b1;
IncrTxPointer<=#Tp 1'b0;
tx_burst_cnt<=#Tp 0;
tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
rx_burst_cnt<=#Tp 0;
rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used.
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b0;
`endif
end
8'bxx_00_10_00, // whatever and no master read or write is needed (ack or err comes finishing previous access)
8'bxx_00_01_00 : // Between cyc_cleared request was cleared
begin
MasterWbTX <=#Tp 1'b0;
MasterWbRX <=#Tp 1'b0;
m_wb_cyc_o <=#Tp 1'b0;
cyc_cleared<=#Tp 1'b0;
IncrTxPointer<=#Tp 1'b0;
rx_burst_cnt<=#Tp 0;
rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used.
`ifdef ETH_WISHBONE_B3
m_wb_cti_o <=#Tp 3'b0;
`endif
end
8'b00_00_00_00: // whatever and no master read or write is needed (ack or err comes finishing previous access)
begin
tx_burst_cnt<=#Tp 0;
tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
end
default: // Don't touch
begin
MasterWbTX <=#Tp MasterWbTX;
MasterWbRX <=#Tp MasterWbRX;
m_wb_cyc_o <=#Tp m_wb_cyc_o;
m_wb_sel_o <=#Tp m_wb_sel_o;
IncrTxPointer<=#Tp IncrTxPointer;
end
endcase
end
end
wire TxFifoClear;
assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
eth_fifo #(`ETH_TX_FIFO_DATA_WIDTH, `ETH_TX_FIFO_DEPTH, `ETH_TX_FIFO_CNT_WIDTH)
tx_fifo ( .data_in(m_wb_dat_i), .data_out(TxData_wb),
.clk(WB_CLK_I), .reset(Reset),
.write(MasterWbTX & m_wb_ack_i), .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
.clear(TxFifoClear), .full(TxBufferFull),
.almost_full(TxBufferAlmostFull), .almost_empty(TxBufferAlmostEmpty),
.empty(TxBufferEmpty), .cnt(txfifo_cnt)
);
reg StartOccured;
reg TxStartFrm_sync1;
reg TxStartFrm_sync2;
reg TxStartFrm_syncb1;
reg TxStartFrm_syncb2;
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxStartFrm_wb <=#Tp 1'b0;
else
if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
TxStartFrm_wb <=#Tp 1'b1;
else
if(TxStartFrm_syncb2)
TxStartFrm_wb <=#Tp 1'b0;
end
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
StartOccured <=#Tp 1'b0;
else
if(TxStartFrm_wb)
StartOccured <=#Tp 1'b1;
else
if(ResetTxBDReady)
StartOccured <=#Tp 1'b0;
end
// Synchronizing TxStartFrm_wb to MTxClk
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxStartFrm_sync1 <=#Tp 1'b0;
else
TxStartFrm_sync1 <=#Tp TxStartFrm_wb;
end
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxStartFrm_sync2 <=#Tp 1'b0;
else
TxStartFrm_sync2 <=#Tp TxStartFrm_sync1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxStartFrm_syncb1 <=#Tp 1'b0;
else
TxStartFrm_syncb1 <=#Tp TxStartFrm_sync2;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxStartFrm_syncb2 <=#Tp 1'b0;
else
TxStartFrm_syncb2 <=#Tp TxStartFrm_syncb1;
end
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxStartFrm <=#Tp 1'b0;
else
if(TxStartFrm_sync2)
TxStartFrm <=#Tp 1'b1;
else
if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry & (~TxRetry_q) | TxAbort & (~TxAbort_q)))
TxStartFrm <=#Tp 1'b0;
end
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
// TxEndFrm_wb: indicator of the end of frame
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxEndFrm_wb <=#Tp 1'b0;
else
if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
TxEndFrm_wb <=#Tp 1'b1;
else
if(TxRetryPulse | TxDonePulse | TxAbortPulse)
TxEndFrm_wb <=#Tp 1'b0;
end
// Marks which bytes are valid within the word.
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
reg LatchValidBytes;
reg LatchValidBytes_q;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
LatchValidBytes <=#Tp 1'b0;
else
if(TxLengthLt4 & TxBDReady)
LatchValidBytes <=#Tp 1'b1;
else
LatchValidBytes <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
LatchValidBytes_q <=#Tp 1'b0;
else
LatchValidBytes_q <=#Tp LatchValidBytes;
end
// Latching valid bytes
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxValidBytesLatched <=#Tp 2'h0;
else
if(LatchValidBytes & ~LatchValidBytes_q)
TxValidBytesLatched <=#Tp TxValidBytes;
else
if(TxRetryPulse | TxDonePulse | TxAbortPulse)
TxValidBytesLatched <=#Tp 2'h0;
end
assign TxIRQEn = TxStatus[14];
assign WrapTxStatusBit = TxStatus[13];
assign PerPacketPad = TxStatus[12];
assign PerPacketCrcEn = TxStatus[11];
assign RxIRQEn = RxStatus[14];
assign WrapRxStatusBit = RxStatus[13];
// Temporary Tx and Rx buffer descriptor address
assign TempTxBDAddress[7:1] = {7{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD)
assign TempRxBDAddress[7:1] = {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0]) | // Using first Rx BD
{7{~WrapRxStatusBit}} & (RxBDAddress + 1'b1) ; // Using next Rx BD (incremenrement address)
// Latching Tx buffer descriptor address
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxBDAddress <=#Tp 7'h0;
else if (r_TxEn & (~r_TxEn_q))
TxBDAddress <=#Tp 7'h0;
else if (TxStatusWrite)
TxBDAddress <=#Tp TempTxBDAddress;
end
// Latching Rx buffer descriptor address
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxBDAddress <=#Tp 7'h0;
else if(r_RxEn & (~r_RxEn_q))
RxBDAddress <=#Tp r_TxBDNum[6:0];
else if(RxStatusWrite)
RxBDAddress <=#Tp TempRxBDAddress;
end
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched};
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
// Signals used for various purposes
assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q;
assign TxDonePulse = TxDone_wb & ~TxDone_wb_q;
assign TxAbortPulse = TxAbort_wb & ~TxAbort_wb_q;
// Generating delayed signals
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
begin
TxAbort_q <=#Tp 1'b0;
TxRetry_q <=#Tp 1'b0;
TxUsedData_q <=#Tp 1'b0;
end
else
begin
TxAbort_q <=#Tp TxAbort;
TxRetry_q <=#Tp TxRetry;
TxUsedData_q <=#Tp TxUsedData;
end
end
// Generating delayed signals
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
begin
TxDone_wb_q <=#Tp 1'b0;
TxAbort_wb_q <=#Tp 1'b0;
TxRetry_wb_q <=#Tp 1'b0;
end
else
begin
TxDone_wb_q <=#Tp TxDone_wb;
TxAbort_wb_q <=#Tp TxAbort_wb;
TxRetry_wb_q <=#Tp TxRetry_wb;
end
end
reg TxAbortPacketBlocked;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxAbortPacket <=#Tp 1'b0;
else
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) |
TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked))
TxAbortPacket <=#Tp 1'b1;
else
TxAbortPacket <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxAbortPacket_NotCleared <=#Tp 1'b0;
else
if(TxEn & TxEn_q & TxAbortPacket_NotCleared)
TxAbortPacket_NotCleared <=#Tp 1'b0;
else
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) |
TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked))
TxAbortPacket_NotCleared <=#Tp 1'b1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxAbortPacketBlocked <=#Tp 1'b0;
else
if(!TxAbort_wb & TxAbort_wb_q)
TxAbortPacketBlocked <=#Tp 1'b0;
else
if(TxAbortPacket)
TxAbortPacketBlocked <=#Tp 1'b1;
end
reg TxRetryPacketBlocked;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxRetryPacket <=#Tp 1'b0;
else
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
TxRetryPacket <=#Tp 1'b1;
else
TxRetryPacket <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxRetryPacket_NotCleared <=#Tp 1'b0;
else
if(StartTxBDRead)
TxRetryPacket_NotCleared <=#Tp 1'b0;
else
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
TxRetryPacket_NotCleared <=#Tp 1'b1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxRetryPacketBlocked <=#Tp 1'b0;
else
if(!TxRetry_wb & TxRetry_wb_q)
TxRetryPacketBlocked <=#Tp 1'b0;
else
if(TxRetryPacket)
TxRetryPacketBlocked <=#Tp 1'b1;
end
reg TxDonePacketBlocked;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxDonePacket <=#Tp 1'b0;
else
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxDonePacketBlocked |
TxDone_wb & !MasterWbTX & !TxDonePacketBlocked)
TxDonePacket <=#Tp 1'b1;
else
TxDonePacket <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxDonePacket_NotCleared <=#Tp 1'b0;
else
if(TxEn & TxEn_q & TxDonePacket_NotCleared)
TxDonePacket_NotCleared <=#Tp 1'b0;
else
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & (~TxDonePacketBlocked) |
TxDone_wb & !MasterWbTX & (~TxDonePacketBlocked))
TxDonePacket_NotCleared <=#Tp 1'b1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxDonePacketBlocked <=#Tp 1'b0;
else
if(!TxDone_wb & TxDone_wb_q)
TxDonePacketBlocked <=#Tp 1'b0;
else
if(TxDonePacket)
TxDonePacketBlocked <=#Tp 1'b1;
end
// Indication of the last word
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
LastWord <=#Tp 1'b0;
else
if((TxEndFrm | TxAbort | TxRetry) & Flop)
LastWord <=#Tp 1'b0;
else
if(TxUsedData & Flop & TxByteCnt == 2'h3)
LastWord <=#Tp TxEndFrm_wb;
end
// Tx end frame generation
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxEndFrm <=#Tp 1'b0;
else
if(Flop & TxEndFrm | TxAbort | TxRetry_q)
TxEndFrm <=#Tp 1'b0;
else
if(Flop & LastWord)
begin
case (TxValidBytesLatched) // synopsys parallel_case
1 : TxEndFrm <=#Tp TxByteCnt == 2'h0;
2 : TxEndFrm <=#Tp TxByteCnt == 2'h1;
3 : TxEndFrm <=#Tp TxByteCnt == 2'h2;
0 : TxEndFrm <=#Tp TxByteCnt == 2'h3;
default : TxEndFrm <=#Tp 1'b0;
endcase
end
end
// Tx data selection (latching)
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxData <=#Tp 0;
else
if(TxStartFrm_sync2 & ~TxStartFrm)
case(TxPointerLSB) // synopsys parallel_case
2'h0 : TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering
2'h1 : TxData <=#Tp TxData_wb[23:16]; // Big Endian Byte Ordering
2'h2 : TxData <=#Tp TxData_wb[15:08]; // Big Endian Byte Ordering
2'h3 : TxData <=#Tp TxData_wb[07:00]; // Big Endian Byte Ordering
endcase
else
if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering
else
if(TxUsedData & Flop)
begin
case(TxByteCnt) // synopsys parallel_case
0 : TxData <=#Tp TxDataLatched[31:24]; // Big Endian Byte Ordering
1 : TxData <=#Tp TxDataLatched[23:16];
2 : TxData <=#Tp TxDataLatched[15:8];
3 : TxData <=#Tp TxDataLatched[7:0];
endcase
end
end
// Latching tx data
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxDataLatched[31:0] <=#Tp 32'h0;
else
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
TxDataLatched[31:0] <=#Tp TxData_wb[31:0];
end
// Tx under run
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxUnderRun_wb <=#Tp 1'b0;
else
if(TxAbortPulse)
TxUnderRun_wb <=#Tp 1'b0;
else
if(TxBufferEmpty & ReadTxDataFromFifo_wb)
TxUnderRun_wb <=#Tp 1'b1;
end
reg TxUnderRun_sync1;
// Tx under run
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxUnderRun_sync1 <=#Tp 1'b0;
else
if(TxUnderRun_wb)
TxUnderRun_sync1 <=#Tp 1'b1;
else
if(BlockingTxStatusWrite_sync2)
TxUnderRun_sync1 <=#Tp 1'b0;
end
// Tx under run
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxUnderRun <=#Tp 1'b0;
else
if(BlockingTxStatusWrite_sync2)
TxUnderRun <=#Tp 1'b0;
else
if(TxUnderRun_sync1)
TxUnderRun <=#Tp 1'b1;
end
// Tx Byte counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxByteCnt <=#Tp 2'h0;
else
if(TxAbort_q | TxRetry_q)
TxByteCnt <=#Tp 2'h0;
else
if(TxStartFrm & ~TxUsedData)
case(TxPointerLSB) // synopsys parallel_case
2'h0 : TxByteCnt <=#Tp 2'h1;
2'h1 : TxByteCnt <=#Tp 2'h2;
2'h2 : TxByteCnt <=#Tp 2'h3;
2'h3 : TxByteCnt <=#Tp 2'h0;
endcase
else
if(TxUsedData & Flop)
TxByteCnt <=#Tp TxByteCnt + 1'b1;
end
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
reg ReadTxDataFromFifo_sync1;
reg ReadTxDataFromFifo_sync2;
reg ReadTxDataFromFifo_sync3;
reg ReadTxDataFromFifo_syncb1;
reg ReadTxDataFromFifo_syncb2;
reg ReadTxDataFromFifo_syncb3;
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_tck <=#Tp 1'b0;
else
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
ReadTxDataFromFifo_tck <=#Tp 1'b1;
else
if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
ReadTxDataFromFifo_tck <=#Tp 1'b0;
end
// Synchronizing TxStartFrm_wb to MTxClk
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_sync1 <=#Tp 1'b0;
else
ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_sync2 <=#Tp 1'b0;
else
ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1;
end
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_syncb1 <=#Tp 1'b0;
else
ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2;
end
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
else
ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
end
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_syncb3 <=#Tp 1'b0;
else
ReadTxDataFromFifo_syncb3 <=#Tp ReadTxDataFromFifo_syncb2;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
else
ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2;
end
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxRetrySync1 <=#Tp 1'b0;
else
TxRetrySync1 <=#Tp TxRetry;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxRetry_wb <=#Tp 1'b0;
else
TxRetry_wb <=#Tp TxRetrySync1;
end
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxDoneSync1 <=#Tp 1'b0;
else
TxDoneSync1 <=#Tp TxDone;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxDone_wb <=#Tp 1'b0;
else
TxDone_wb <=#Tp TxDoneSync1;
end
// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxAbortSync1 <=#Tp 1'b0;
else
TxAbortSync1 <=#Tp TxAbort;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxAbort_wb <=#Tp 1'b0;
else
TxAbort_wb <=#Tp TxAbortSync1;
end
reg RxAbortSync1;
reg RxAbortSync2;
reg RxAbortSync3;
reg RxAbortSync4;
reg RxAbortSyncb1;
reg RxAbortSyncb2;
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4 | r_RxEn & ~r_RxEn_q;
// Reading the Rx buffer descriptor
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxBDRead <=#Tp 1'b0;
else
if(StartRxBDRead & ~RxReady)
RxBDRead <=#Tp 1'b1;
else
if(RxBDReady)
RxBDRead <=#Tp 1'b0;
end
// Reading of the next receive buffer descriptor starts after reception status is
// written to the previous one.
// Latching READY status of the Rx buffer descriptor
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxBDReady <=#Tp 1'b0;
else
if(RxPointerRead)
RxBDReady <=#Tp 1'b0;
else
if(RxEn & RxEn_q & RxBDRead)
RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
end
// Latching Rx buffer descriptor status
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxStatus <=#Tp 2'h0;
else
if(RxEn & RxEn_q & RxBDRead)
RxStatus <=#Tp ram_do[14:13];
end
// RxReady generation
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxReady <=#Tp 1'b0;
else
if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3 | ~r_RxEn & r_RxEn_q)
RxReady <=#Tp 1'b0;
else
if(RxEn & RxEn_q & RxPointerRead)
RxReady <=#Tp 1'b1;
end
// Reading Rx BD pointer
assign StartRxPointerRead = RxBDRead & RxBDReady;
// Reading Tx BD Pointer
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxPointerRead <=#Tp 1'b0;
else
if(StartRxPointerRead)
RxPointerRead <=#Tp 1'b1;
else
if(RxEn & RxEn_q)
RxPointerRead <=#Tp 1'b0;
end
//Latching Rx buffer pointer from buffer descriptor;
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxPointerMSB <=#Tp 30'h0;
else
if(RxEn & RxEn_q & RxPointerRead)
RxPointerMSB <=#Tp ram_do[31:2];
else
if(MasterWbRX & m_wb_ack_i)
RxPointerMSB <=#Tp RxPointerMSB + 1'b1; // Word access (always word access. m_wb_sel_o are used for selecting bytes)
end
//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxPointerLSB_rst[1:0] <=#Tp 0;
else
if(MasterWbRX & m_wb_ack_i) // After first write all RxByteSel are active
RxPointerLSB_rst[1:0] <=#Tp 0;
else
if(RxEn & RxEn_q & RxPointerRead)
RxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
end
always @ (RxPointerLSB_rst)
begin
case(RxPointerLSB_rst[1:0]) // synopsys parallel_case
2'h0 : RxByteSel[3:0] = 4'hf;
2'h1 : RxByteSel[3:0] = 4'h7;
2'h2 : RxByteSel[3:0] = 4'h3;
2'h3 : RxByteSel[3:0] = 4'h1;
endcase
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxEn_needed <=#Tp 1'b0;
else
if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
RxEn_needed <=#Tp 1'b1;
else
if(RxPointerRead & RxEn & RxEn_q)
RxEn_needed <=#Tp 1'b0;
end
// Reception status is written back to the buffer descriptor after the end of frame is detected.
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
reg RxEnableWindow;
// Indicating that last byte is being reveived
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LastByteIn <=#Tp 1'b0;
else
if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
LastByteIn <=#Tp 1'b0;
else
if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
LastByteIn <=#Tp 1'b1;
end
reg ShiftEnded_rck;
reg ShiftEndedSync1;
reg ShiftEndedSync2;
reg ShiftEndedSync3;
reg ShiftEndedSync_c1;
reg ShiftEndedSync_c2;
wire StartShiftWillEnd;
assign StartShiftWillEnd = LastByteIn | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
// Indicating that data reception will end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShiftWillEnd <=#Tp 1'b0;
else
if(ShiftEnded_rck | RxAbort)
ShiftWillEnd <=#Tp 1'b0;
else
if(StartShiftWillEnd)
ShiftWillEnd <=#Tp 1'b1;
end
// Receive byte counter
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxByteCnt <=#Tp 2'h0;
else
if(ShiftEnded_rck | RxAbort)
RxByteCnt <=#Tp 2'h0;
else
if(RxValid & RxStartFrm & RxReady)
case(RxPointerLSB_rst) // synopsys parallel_case
2'h0 : RxByteCnt <=#Tp 2'h1;
2'h1 : RxByteCnt <=#Tp 2'h2;
2'h2 : RxByteCnt <=#Tp 2'h3;
2'h3 : RxByteCnt <=#Tp 2'h0;
endcase
else
if(RxValid & RxEnableWindow & RxReady | LastByteIn)
RxByteCnt <=#Tp RxByteCnt + 1'b1;
end
// Indicates how many bytes are valid within the last word
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxValidBytes <=#Tp 2'h1;
else
if(RxValid & RxStartFrm)
case(RxPointerLSB_rst) // synopsys parallel_case
2'h0 : RxValidBytes <=#Tp 2'h1;
2'h1 : RxValidBytes <=#Tp 2'h2;
2'h2 : RxValidBytes <=#Tp 2'h3;
2'h3 : RxValidBytes <=#Tp 2'h0;
endcase
else
if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
RxValidBytes <=#Tp RxValidBytes + 1'b1;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxDataLatched1 <=#Tp 24'h0;
else
if(RxValid & RxReady & ~LastByteIn)
if(RxStartFrm)
begin
case(RxPointerLSB_rst) // synopsys parallel_case
2'h0: RxDataLatched1[31:24] <=#Tp RxData; // Big Endian Byte Ordering
2'h1: RxDataLatched1[23:16] <=#Tp RxData;
2'h2: RxDataLatched1[15:8] <=#Tp RxData;
2'h3: RxDataLatched1 <=#Tp RxDataLatched1;
endcase
end
else if (RxEnableWindow)
begin
case(RxByteCnt) // synopsys parallel_case
2'h0: RxDataLatched1[31:24] <=#Tp RxData; // Big Endian Byte Ordering
2'h1: RxDataLatched1[23:16] <=#Tp RxData;
2'h2: RxDataLatched1[15:8] <=#Tp RxData;
2'h3: RxDataLatched1 <=#Tp RxDataLatched1;
endcase
end
end
wire SetWriteRxDataToFifo;
// Assembling data that will be written to the rx_fifo
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxDataLatched2 <=#Tp 32'h0;
else
if(SetWriteRxDataToFifo & ~ShiftWillEnd)
RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
else
if(SetWriteRxDataToFifo & ShiftWillEnd)
case(RxValidBytes) // synopsys parallel_case
0 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], 8'h0};
endcase
end
reg WriteRxDataToFifoSync1;
reg WriteRxDataToFifoSync2;
reg WriteRxDataToFifoSync3;
// Indicating start of the reception process
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) |
(RxValid & RxReady & RxStartFrm & (&RxPointerLSB_rst)) |
(ShiftWillEnd & LastByteIn & (&RxByteCnt));
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
WriteRxDataToFifo <=#Tp 1'b0;
else
if(SetWriteRxDataToFifo & ~RxAbort)
WriteRxDataToFifo <=#Tp 1'b1;
else
if(WriteRxDataToFifoSync2 | RxAbort)
WriteRxDataToFifo <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
WriteRxDataToFifoSync1 <=#Tp 1'b0;
else
if(WriteRxDataToFifo)
WriteRxDataToFifoSync1 <=#Tp 1'b1;
else
WriteRxDataToFifoSync1 <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
WriteRxDataToFifoSync2 <=#Tp 1'b0;
else
WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
WriteRxDataToFifoSync3 <=#Tp 1'b0;
else
WriteRxDataToFifoSync3 <=#Tp WriteRxDataToFifoSync2;
end
wire WriteRxDataToFifo_wb;
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3;
reg LatchedRxStartFrm;
reg SyncRxStartFrm;
reg SyncRxStartFrm_q;
reg SyncRxStartFrm_q2;
wire RxFifoReset;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LatchedRxStartFrm <=#Tp 0;
else
if(RxStartFrm & ~SyncRxStartFrm_q)
LatchedRxStartFrm <=#Tp 1;
else
if(SyncRxStartFrm_q)
LatchedRxStartFrm <=#Tp 0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
SyncRxStartFrm <=#Tp 0;
else
if(LatchedRxStartFrm)
SyncRxStartFrm <=#Tp 1;
else
SyncRxStartFrm <=#Tp 0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
SyncRxStartFrm_q <=#Tp 0;
else
SyncRxStartFrm_q <=#Tp SyncRxStartFrm;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
SyncRxStartFrm_q2 <=#Tp 0;
else
SyncRxStartFrm_q2 <=#Tp SyncRxStartFrm_q;
end
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
eth_fifo #(`ETH_RX_FIFO_DATA_WIDTH, `ETH_RX_FIFO_DEPTH, `ETH_RX_FIFO_CNT_WIDTH)
rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o),
.clk(WB_CLK_I), .reset(Reset),
.write(WriteRxDataToFifo_wb & ~RxBufferFull), .read(MasterWbRX & m_wb_ack_i),
.clear(RxFifoReset), .full(RxBufferFull),
.almost_full(), .almost_empty(RxBufferAlmostEmpty),
.empty(RxBufferEmpty), .cnt(rxfifo_cnt)
);
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
assign WriteRxDataToMemory = ~RxBufferEmpty;
assign rx_burst = rx_burst_en & WriteRxDataToMemory;
// Generation of the end-of-frame signal
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShiftEnded_rck <=#Tp 1'b0;
else
if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
ShiftEnded_rck <=#Tp 1'b1;
else
if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
ShiftEnded_rck <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ShiftEndedSync1 <=#Tp 1'b0;
else
ShiftEndedSync1 <=#Tp ShiftEnded_rck;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ShiftEndedSync2 <=#Tp 1'b0;
else
ShiftEndedSync2 <=#Tp ShiftEndedSync1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ShiftEndedSync3 <=#Tp 1'b0;
else
if(ShiftEndedSync1 & ~ShiftEndedSync2)
ShiftEndedSync3 <=#Tp 1'b1;
else
if(ShiftEnded)
ShiftEndedSync3 <=#Tp 1'b0;
end
// Generation of the end-of-frame signal
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
ShiftEnded <=#Tp 1'b0;
else
if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
ShiftEnded <=#Tp 1'b1;
else
if(RxStatusWrite)
ShiftEnded <=#Tp 1'b0;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShiftEndedSync_c1 <=#Tp 1'b0;
else
ShiftEndedSync_c1 <=#Tp ShiftEndedSync2;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
ShiftEndedSync_c2 <=#Tp 1'b0;
else
ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1;
end
// Generation of the end-of-frame signal
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxEnableWindow <=#Tp 1'b0;
else
if(RxStartFrm)
RxEnableWindow <=#Tp 1'b1;
else
if(RxEndFrm | RxAbort)
RxEnableWindow <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxAbortSync1 <=#Tp 1'b0;
else
RxAbortSync1 <=#Tp RxAbortLatched;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxAbortSync2 <=#Tp 1'b0;
else
RxAbortSync2 <=#Tp RxAbortSync1;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxAbortSync3 <=#Tp 1'b0;
else
RxAbortSync3 <=#Tp RxAbortSync2;
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxAbortSync4 <=#Tp 1'b0;
else
RxAbortSync4 <=#Tp RxAbortSync3;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxAbortSyncb1 <=#Tp 1'b0;
else
RxAbortSyncb1 <=#Tp RxAbortSync2;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxAbortSyncb2 <=#Tp 1'b0;
else
RxAbortSyncb2 <=#Tp RxAbortSyncb1;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxAbortLatched <=#Tp 1'b0;
else
if(RxAbortSyncb2)
RxAbortLatched <=#Tp 1'b0;
else
if(RxAbort)
RxAbortLatched <=#Tp 1'b1;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
LatchedRxLength[15:0] <=#Tp 16'h0;
else
if(LoadRxStatus)
LatchedRxLength[15:0] <=#Tp RxLength[15:0];
end
assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
RxStatusInLatched <=#Tp 'h0;
else
if(LoadRxStatus)
RxStatusInLatched <=#Tp RxStatusIn;
end
// Rx overrun
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxOverrun <=#Tp 1'b0;
else
if(RxStatusWrite)
RxOverrun <=#Tp 1'b0;
else
if(RxBufferFull & WriteRxDataToFifo_wb)
RxOverrun <=#Tp 1'b1;
end
wire TxError;
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
wire RxError;
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
// are aborted when signal r_RecSmall is set to 0 in MODER register.
// AddressMiss is identifying that a frame was received because of the promiscous
// mode and is not an error
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
reg RxStatusWriteLatched;
reg RxStatusWriteLatched_sync1;
reg RxStatusWriteLatched_sync2;
reg RxStatusWriteLatched_syncb1;
reg RxStatusWriteLatched_syncb2;
// Latching and synchronizing RxStatusWrite signal. This signal is used for clearing the ReceivedPauseFrm signal
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxStatusWriteLatched <=#Tp 1'b0;
else
if(RxStatusWriteLatched_syncb2)
RxStatusWriteLatched <=#Tp 1'b0;
else
if(RxStatusWrite)
RxStatusWriteLatched <=#Tp 1'b1;
end
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
begin
RxStatusWriteLatched_sync1 <=#Tp 1'b0;
RxStatusWriteLatched_sync2 <=#Tp 1'b0;
end
else
begin
RxStatusWriteLatched_sync1 <=#Tp RxStatusWriteLatched;
RxStatusWriteLatched_sync2 <=#Tp RxStatusWriteLatched_sync1;
end
end
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
begin
RxStatusWriteLatched_syncb1 <=#Tp 1'b0;
RxStatusWriteLatched_syncb2 <=#Tp 1'b0;
end
else
begin
RxStatusWriteLatched_syncb1 <=#Tp RxStatusWriteLatched_sync2;
RxStatusWriteLatched_syncb2 <=#Tp RxStatusWriteLatched_syncb1;
end
end
// Tx Done Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxB_IRQ <=#Tp 1'b0;
else
if(TxStatusWrite & TxIRQEn)
TxB_IRQ <=#Tp ~TxError;
else
TxB_IRQ <=#Tp 1'b0;
end
// Tx Error Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
TxE_IRQ <=#Tp 1'b0;
else
if(TxStatusWrite & TxIRQEn)
TxE_IRQ <=#Tp TxError;
else
TxE_IRQ <=#Tp 1'b0;
end
// Rx Done Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxB_IRQ <=#Tp 1'b0;
else
if(RxStatusWrite & RxIRQEn & ReceivedPacketGood & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
RxB_IRQ <=#Tp (~RxError);
else
RxB_IRQ <=#Tp 1'b0;
end
// Rx Error Interrupt
always @ (posedge WB_CLK_I or posedge Reset)
begin
if(Reset)
RxE_IRQ <=#Tp 1'b0;
else
if(RxStatusWrite & RxIRQEn & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
RxE_IRQ <=#Tp RxError;
else
RxE_IRQ <=#Tp 1'b0;
end
// Busy Interrupt
reg Busy_IRQ_rck;
reg Busy_IRQ_sync1;
reg Busy_IRQ_sync2;
reg Busy_IRQ_sync3;
reg Busy_IRQ_syncb1;
reg Busy_IRQ_syncb2;
always @ (posedge MRxClk or posedge Reset)
begin
if(Reset)
Busy_IRQ_rck <=#Tp 1'b0;
else
if(RxValid & RxStartFrm & ~RxReady)
Busy_IRQ_rck <=#Tp 1'b1;
else
if(Busy_IRQ_syncb2)
Busy_IRQ_rck <=#Tp 1'b0;
end
always @ (posedge WB_CLK_I)
begin
Busy_IRQ_sync1 <=#Tp Busy_IRQ_rck;
Busy_IRQ_sync2 <=#Tp Busy_IRQ_sync1;
Busy_IRQ_sync3 <=#Tp Busy_IRQ_sync2;
end
always @ (posedge MRxClk)
begin
Busy_IRQ_syncb1 <=#Tp Busy_IRQ_sync2;
Busy_IRQ_syncb2 <=#Tp Busy_IRQ_syncb1;
end
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A32OI_SYMBOL_V
`define SKY130_FD_SC_MS__A32OI_SYMBOL_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a32oi (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input B2,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A32OI_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/24 21:16:49
// Design Name:
// Module Name: T_ff_enable_behavior_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module T_ff_enable_behavior_tb(
);
reg T, Clk, reset_n;
wire Q;
T_ff_enable_behavior DUT (.T(T), .Clk(Clk), .reset_n(reset_n), .Q(Q));
initial begin
#300 $finish;
end
initial begin
T = 0; Clk = 0; reset_n = 0;
#10 reset_n = 1;
#10 Clk = 1;
#10 Clk = 0; T = 1;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0; T = 0;
#10 Clk = 1;
#10 Clk = 0; reset_n = 0;
#10 Clk = 1;
#10 Clk = 0; reset_n = 1;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0; T = 1;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0;
#10 Clk = 1;
#10 Clk = 0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR4BB_SYMBOL_V
`define SKY130_FD_SC_HD__OR4BB_SYMBOL_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__or4bb (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N,
input D_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR4BB_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O31A_PP_SYMBOL_V
`define SKY130_FD_SC_HD__O31A_PP_SYMBOL_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o31a (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O31A_PP_SYMBOL_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module convolve_kernel_fcud
#(parameter
ID = 26,
NUM_STAGE = 5,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
//------------------------Instantiation------------------
convolve_kernel_ap_fmul_3_max_dsp_32 convolve_kernel_ap_fmul_3_max_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
endmodule
|
/*
* 2D Cube Simulator
* CSCB58 Summer 2017 Final Project
* Team members:
* Shuang Wu
* Pingfan Xu
*/
module 2DCubeSimulator(
LEDR,
CLOCK_50, // On Board 50 MHz
KEY,
SW,
VGA_CLK, // VGA Clock
VGA_HS, // VGA H_SYNC
VGA_VS, // VGA V_SYNC
VGA_BLANK_N, // VGA BLANK
VGA_SYNC_N, // VGA SYNC
VGA_R, // VGA Red[9:0]
VGA_G, // VGA Green[9:0]
VGA_B // VGA Blue[9:0]
);
output [7:0] LEDR;
input CLOCK_50; // 50 MHz
input [9:0] SW;
input [3:0] KEY;
// Declare your inputs and outputs here
// Do not change the following outputs
output VGA_CLK; // VGA Clock
output VGA_HS; // VGA H_SYNC
output VGA_VS; // VGA V_SYNC
output VGA_BLANK_N; // VGA BLANK
output VGA_SYNC_N; // VGA SYNC
output [9:0] VGA_R; // VGA Red[9:0]
output [9:0] VGA_G; // VGA Green[9:0]
output [9:0] VGA_B; // VGA Blue[9:0]
//signals
reg writeEn, draw, stopcount, draw_all;
//colour
wire [2:0] colour;
//X8, Y8, Colour3
reg [1025:0] code = 1026'b0000100000001000110_0000110000001000110_0001000000001000110_0000100000001100110_0000110000001100110_0001000000001100110_0000100000010000110_0000110000010000110_0001000000010000110_0001100000001000101_0001110000001000101_0010000000001000101_0001100000001100101_0001110000001100101_0010000000001100101_0001100000010000101_0001110000010000101_0010000000010000101_0010100000001000001_0010110000001000001_0011000000001000001_0010100000001100001_0010110000001100001_0011000000001100001_0010100000010000001_0010110000010000001_0011000000010000001_0000100000011000111_0000110000011000111_0001000000011000111_0000100000011100111_0000110000011100111_0001000000011100111_0000100000100000111_0000110000100000111_0001000000100000111_0001100000011000100_0001110000011000100_0010000000011000100_0001100000011100100_0001110000011100100_0010000000011100100_0001100000100000100_0001110000100000100_0010000000100000100_0010100000011000010_0010110000011000010_0011000000011000010_0010100000011100010_0010110000011100010_0011000000011100010_0010100000100000010_0010110000100000010_0011000000100000010;//1025:0
reg [1025:0] codereg, coderegshifter;
wire [7:0] input_x, input_y, X, Y;
// Create an Instance of a VGA controller - there can be only one!
// Define the number of colours as well as the initial background
// image file (.MIF) for the controller.
vga_adapter VGA(
.resetn(KEY[3]),
.clock(CLOCK_50),
.colour(colour),
.x(input_x),
.y(input_y),
.plot(writeEn),
/* Signals for the DAC to drive the monitor. */
.VGA_R(VGA_R),
.VGA_G(VGA_G),
.VGA_B(VGA_B),
.VGA_HS(VGA_HS),
.VGA_VS(VGA_VS),
.VGA_BLANK(VGA_BLANK_N),
.VGA_SYNC(VGA_SYNC_N),
.VGA_CLK(VGA_CLK));
defparam VGA.RESOLUTION = "160x120";
defparam VGA.MONOCHROME = "FALSE";
defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;
defparam VGA.BACKGROUND_IMAGE = "black.mif";
reg [1:0] current_state, next_state;
localparam DRAW_ALL = 2'b00, REST = 2'b01, ADJUSTMENT = 2'b11, TEMP = 2'b10;
//Main FSM
always@(posedge CLOCK_50)
begin
case (current_state)
DRAW_ALL: next_state = draw_all? REST : DRAW_ALL;
REST: next_state = (~KEY[0])? ADJUSTMENT : REST;// KEY[0] for load the operation code ie.up&cw
ADJUSTMENT: next_state = TEMP;
TEMP: next_state = DRAW_ALL;
endcase
end
//several actions can be performed;
localparam UP_CW = 8'b0100_0001, UP_CCW = 8'b0000_0001, DOWN_CW = 8'b0100_0010, DOWN_CCW = 8'b0000_0010, LEFT_CW = 8'b0100_0100, LEFT_CCW = 8'b0000_0100;
localparam RIGHT_CW = 8'b0100_1000, RIGHT_CCW = 8'b0000_1000, FRONT_CW = 8'b0101_0000, FRONT_CCW = 8'b0001_0000, BACK_CW = 8'b0110_0000, BACK_CCW = 8'b0010_0000;
//Corresponding FSM actions;
always@(posedge CLOCK_50)
begin
draw_all <= 1'b0;
case (current_state)
DRAW_ALL: begin
if (coderegshifter[18:0] == 19'd0)
begin
draw_all <= 1'b1;
end
else if (delay && (coderegshifter[18:0] != 19'd0))
begin
writeEn <= 1;
end
else if (!delay && (coderegshifter[18:0] != 19'd0))
begin
test <= 1'b1;//to check whether this condition
coderegshifter[1025:0] = (coderegshifter[1025:0] >> 19);
end
current_state <= next_state;
end
REST: begin
current_state <= next_state;
end
ADJUSTMENT:
begin
if (SW[7] == 1)//if reset
begin
codereg <= code;//default value;
end
else if (SW[7:0] == UP_CW)//if up&cw, change wires and then load into a reg for later shifting
begin
codereg[971:969] <= codereg[1009:1007]; // 1->3
codereg[1009:1007] <= codereg[895:893]; // 7->1
codereg[895:893] <= codereg[857:855]; // 9->7
codereg[857:855] <= codereg[971:969]; // 3->9
codereg[914:912] <= codereg[990:988]; // 2->6
codereg[990:988] <= codereg[952:950]; // 4->2
codereg[952:950] <= codereg[876:874]; // 8->4
codereg[876:874] <= codereg[914:912]; // 6->8
codereg[838:836] <= codereg[667:665]; //front to left
codereg[819:817] <= codereg[648:646]; //
codereg[800:798] <= codereg[629:627]; //
codereg[667:665] <= codereg[325:323]; //right to front
codereg[648:646] <= codereg[306:304]; //
codereg[629:627] <= codereg[287:285]; //
codereg[325:323] <= codereg[154:152]; //back to right
codereg[306:304] <= codereg[135:133]; //
codereg[287:285] <= codereg[116:114];
codereg[154:152] <= codereg[838:836]; //left to back
codereg[135:133] <= codereg[819:817];
codereg[116:114] <= codereg[800:798];
end
else if (SW[7:0] == UP_CCW)//if up&ccw,
begin
codereg[895:893] <= codereg[1009:1007]; // 1->7
codereg[1009:1007] <= codereg[971:969]; // 3->1
codereg[971:969] <= codereg[857:855]; // 9->3
codereg[857:855] <= codereg[895:893]; // 7->9
codereg[952:950] <= codereg[990:988]; // 2->4
codereg[990:988] <= codereg[914:912]; // 6->2
codereg[914:912] <= codereg[876:874]; // 8->6
codereg[876:874] <= codereg[952:950]; // 4->8
codereg[325:323] <= codereg[667:665]; //front to right
codereg[306:304] <= codereg[648:646]; //
codereg[287:285] <= codereg[629:627]; //
codereg[667:665] <= codereg[838:836]; //left to front
codereg[648:646] <= codereg[819:817];
codereg[629:627] <= codereg[800:798];
codereg[838:836] <= codereg[154:152]; //back to left
codereg[819:817] <= codereg[135:133];
codereg[800:798] <= codereg[116:114];
codereg[154:152] <= codereg[325:323]; //right to back
codereg[135:133] <= codereg[306:304];
codereg[116:114] <= codereg[287:285];
end
else if (SW[7:0] == DOWN_CW)//if down&cw,
begin
codereg[458:456] <= codereg[496:494]; // 28->30
codereg[496:494] <= codereg[382:380]; // 34->28
codereg[382:380] <= codereg[344:342]; // 36->34
codereg[344:342] <= codereg[458:456]; // 30->36
codereg[401:399] <= codereg[477:475]; // 29->33
codereg[477:475] <= codereg[439:437]; // 31->29
codereg[439:437] <= codereg[363:361]; // 35->31
codereg[363:361] <= codereg[401:399]; // 33->35
codereg[211:209] <= codereg[553:551]; //front to right
codereg[192:190] <= codereg[534:532];
codereg[173:171] <= codereg[515:513];
codereg[553:551] <= codereg[724:722]; //left to front
codereg[534:532] <= codereg[705:703];
codereg[515:513] <= codereg[686:684];
codereg[724:722] <= codereg[40:38]; //back to left
codereg[705:703] <= codereg[21:19];
codereg[686:684] <= codereg[2:0];
codereg[40:38] <= codereg[211:209]; //right to back
codereg[21:19] <= codereg[192:190];
codereg[2:0] <= codereg[173:171];
end
else if (SW[7:0] == DOWN_CCW)//if down&ccw,
begin
codereg[382:380] <= codereg[496:494]; // 28->34
codereg[496:494] <= codereg[458:456]; // 30->28
codereg[458:456] <= codereg[344:342]; // 36->30
codereg[344:342] <= codereg[382:380]; // 34->36
codereg[439:437] <= codereg[477:475]; // 29->31
codereg[477:475] <= codereg[401:399]; // 33->29
codereg[401:399] <= codereg[363:361]; // 35->33
codereg[363:361] <= codereg[439:437]; // 31->35
codereg[724:722] <= codereg[553:551]; //front to left
codereg[705:703] <= codereg[534:532];
codereg[686:684] <= codereg[515:513];
codereg[553:551] <= codereg[211:209]; //right to front
codereg[534:532] <= codereg[192:190];
codereg[515:513] <= codereg[173:171];
codereg[211:209] <= codereg[40:38]; //back to right
codereg[192:190] <= codereg[21:19];
codereg[173:171] <= codereg[2:0];
codereg[40:38] <= codereg[724:722]; //left to back
codereg[21:19] <= codereg[705:703];
codereg[2:0] <= codereg[686:684];
end
else if (SW[7:0] == LEFT_CW)//if left&cw,
begin
codereg[800:798] <= codereg[838:836]; // 10->12
codereg[838:836] <= codereg[724:722]; // 16->10
codereg[724:722] <= codereg[686:684]; // 18->16
codereg[686:684] <= codereg[800:798]; // 12->18
codereg[743:741] <= codereg[819:817]; // 11->15
codereg[819:817] <= codereg[781:779]; // 13->11
codereg[781:779] <= codereg[705:703]; // 17->13
codereg[705:703] <= codereg[743:741]; // 15->17
//front to down
codereg[496:494] <= codereg[667:665]; //19->28
codereg[439:437] <= codereg[610:608]; //22->31
codereg[382:380] <= codereg[553:551]; //25->34
//up to front
codereg[667:665] <= codereg[1009:1007]; //1->19
codereg[610:608] <= codereg[952:950]; //4->22
codereg[553:551] <= codereg[895:893]; //7->25
//back to up
codereg[1009:1007] <= codereg[2:0]; //54->1
codereg[952:950] <= codereg[59:57]; //51->4
codereg[895:893] <= codereg[116:114]; //48->7
//down to back
codereg[2:0] <= codereg[496:494]; //28->54
codereg[59:57] <= codereg[439:437]; //31->51
codereg[116:114] <= codereg[382:380]; //34->48
end
else if (SW[7:0] == LEFT_CCW)
begin
codereg[724:722] <= codereg[838:836]; // 10->16
codereg[838:836] <= codereg[800:798]; // 12->10
codereg[800:798] <= codereg[686:684]; // 18->12
codereg[686:684] <= codereg[724:722]; // 16->18
codereg[781:779] <= codereg[819:817]; // 11->13
codereg[819:817] <= codereg[743:741]; // 15->11
codereg[743:741] <= codereg[705:703]; // 17->15
codereg[705:703] <= codereg[781:779]; // 13->17
//front to up
codereg[1009:1007] <= codereg[667:665];
codereg[952:950] <= codereg[610:608];
codereg[895:893] <= codereg[553:551];
//up to back
codereg[2:0] <= codereg[1009:1007];
codereg[59:57] <= codereg[952:950];
codereg[116:114] <= codereg[895:893];
//back to down
codereg[496:494] <= codereg[2:0];
codereg[439:437] <= codereg[59:57];
codereg[382:380] <= codereg[116:114];
//down to front
codereg[667:665] <= codereg[496:494];
codereg[610:608] <= codereg[439:437];
codereg[553:551] <= codereg[382:380];
end
else if (SW[7:0] == RIGHT_CW)
begin
codereg[287:285] <= codereg[325:323]; // 37->39
codereg[325:323] <= codereg[211:209]; // 43->37
codereg[211:209] <= codereg[173:171]; // 45->43
codereg[173:171] <= codereg[287:285]; // 39->45
codereg[230:228] <= codereg[306:304]; // 38->42
codereg[306:304] <= codereg[268:266]; // 40->38
codereg[268:266] <= codereg[192:190]; // 44->40
codereg[192:190] <= codereg[230:228]; // 42->44
//front to up
codereg[971:969] <= codereg[629:627]; //21->3
codereg[914:912] <= codereg[572:570]; //24->6
codereg[857:855] <= codereg[515:513]; //27->9
//up to back
codereg[40:38] <= codereg[971:969]; //3->52
codereg[97:95] <= codereg[914:912]; //6->49
codereg[154:152] <= codereg[857:855]; //9->46
//back to down
codereg[458:456] <= codereg[40:38]; //52->30
codereg[401:399] <= codereg[97:95]; //49->33
codereg[344:342] <= codereg[154:152]; //46->36
//down to front
codereg[629:627] <= codereg[458:456]; //30->21
codereg[572:570] <= codereg[401:399]; //33->24
codereg[515:513] <= codereg[344:342]; //36->27
end
else if (SW[7:0] == RIGHT_CCW)
begin
codereg[211:209] <= codereg[325:323]; // 37->43
codereg[325:323] <= codereg[287:285]; // 39->37
codereg[287:285] <= codereg[173:171]; // 45->39
codereg[173:171] <= codereg[211:209]; // 43->45
codereg[268:266] <= codereg[306:304]; // 38->40
codereg[306:304] <= codereg[230:228]; // 42->38
codereg[230:228] <= codereg[192:190]; // 44->42
codereg[192:190] <= codereg[268:266]; // 40->44
codereg[458:456] <= codereg[629:627];
codereg[401:399] <= codereg[572:570];
codereg[344:342] <= codereg[515:513];
//up to front
codereg[629:627] <= codereg[971:969];
codereg[572:570] <= codereg[914:912];
codereg[515:513] <= codereg[857:855];
//back to up
codereg[971:969] <= codereg[40:38];
codereg[914:912] <= codereg[97:95];
codereg[857:855] <= codereg[154:152];
//down to back
codereg[40:38] <= codereg[458:456];
codereg[97:95] <= codereg[401:399];
codereg[154:152] <= codereg[344:342];
end
else if (SW[7:0] == FRONT_CW)
begin
codereg[629:627] <= codereg[667:665]; // 19->21
codereg[667:665] <= codereg[553:551]; // 25->19
codereg[553:551] <= codereg[515:513]; // 27->25
codereg[515:513] <= codereg[629:627]; // 21->27
codereg[572:570] <= codereg[648:646]; // 20->24
codereg[648:646] <= codereg[610:608]; // 22->20
codereg[610:608] <= codereg[534:532]; // 26->22
codereg[534:532] <= codereg[572:570]; // 24->26
codereg[325:323] <= codereg[895:893]; //UP to Right
codereg[268:266] <= codereg[876:874];
codereg[211:209] <= codereg[857:855];
codereg[458:456] <= codereg[325:323]; //Right to Down
codereg[477:475] <= codereg[268:266];
codereg[496:494] <= codereg[211:209];
codereg[686:684] <= codereg[458:456]; //Down to Left
codereg[743:741] <= codereg[477:475];
codereg[800:798] <= codereg[496:494];
codereg[895:893] <= codereg[686:684]; //Left to Up
codereg[876:874] <= codereg[743:741];
codereg[857:855] <= codereg[800:798];
end
else if (SW[7:0] == FRONT_CCW)
begin
codereg[553:551] <= codereg[667:665]; // 19->25
codereg[667:665] <= codereg[629:627]; // 21->19
codereg[629:627] <= codereg[515:513]; // 27->21
codereg[515:513] <= codereg[553:551]; // 25->27
codereg[610:608] <= codereg[648:646]; // 20->22
codereg[648:646] <= codereg[572:570]; // 24->20
codereg[572:570] <= codereg[534:532]; // 26->24
codereg[534:532] <= codereg[610:608]; // 22->26
codereg[686:684] <= codereg[895:893]; //UP to Left
codereg[743:741] <= codereg[876:874];
codereg[800:798] <= codereg[857:855];
codereg[458:456] <= codereg[686:684]; //Left to Down
codereg[477:475] <= codereg[743:741];
codereg[496:494] <= codereg[800:798];
codereg[325:323] <= codereg[458:456]; //Down to Right
codereg[268:266] <= codereg[477:475];
codereg[211:209] <= codereg[496:494];
codereg[895:893] <= codereg[325:323]; //Right to Up
codereg[876:874] <= codereg[268:266];
codereg[857:855] <= codereg[211:209];
end
else if (SW[7:0] == BACK_CW)
begin
codereg[116:114] <= codereg[154:152]; // 46->48
codereg[154:152] <= codereg[40:38]; // 52->46
codereg[40:38] <= codereg[2:0]; // 54->52
codereg[2:0] <= codereg[116:114]; // 48->54
codereg[59:57] <= codereg[135:133]; // 47->51
codereg[135:133] <= codereg[97:95]; // 49->47
codereg[97:95] <= codereg[21:19]; // 53->49
codereg[21:19] <= codereg[59:57]; // 51->53
codereg[724:722] <= codereg[1009:1007]; //Up to Left
codereg[781:779] <= codereg[990:988];
codereg[838:836] <= codereg[971:969];
codereg[344:342] <= codereg[724:722]; //Left to Down
codereg[363:361] <= codereg[781:779];
codereg[382:380] <= codereg[838:836];
codereg[287:285] <= codereg[344:342]; //Down to Right
codereg[230:228] <= codereg[363:361];
codereg[173:171] <= codereg[382:380];
codereg[1009:1007] <= codereg[287:285]; //Right to Up
codereg[990:988] <= codereg[230:228];
codereg[971:969] <= codereg[173:171];
end
else if (SW[7:0] == BACK_CCW)
begin
codereg[40:38] <= codereg[154:152]; // 46->52
codereg[154:152] <= codereg[116:114]; // 48->46
codereg[116:114] <= codereg[2:0]; // 54->48
codereg[2:0] <= codereg[40:38]; // 52->54
codereg[97:95] <= codereg[135:133]; // 47->49
codereg[135:133] <= codereg[59:57]; // 51->47
codereg[59:57] <= codereg[21:19]; // 53->51
codereg[21:19] <= codereg[97:95]; // 49->53
codereg[287:285] <= codereg[1009:1007]; //Up to Right
codereg[230:228] <= codereg[990:988];
codereg[173:171] <= codereg[971:969];
codereg[344:342] <= codereg[287:285]; //Right to Down
codereg[363:361] <= codereg[230:228];
codereg[382:380] <= codereg[173:171];
codereg[724:722] <= codereg[344:342]; //Down to Left
codereg[781:779] <= codereg[363:361];
codereg[838:836] <= codereg[382:380];
codereg[1009:1007] <= codereg[724:722]; //Left to Up
codereg[990:988] <= codereg[781:779];
codereg[971:969] <= codereg[838:836];
end
else//else, no change
begin
end
stopcount <= 1;
current_state <= next_state;
end
TEMP: begin
coderegshifter[1025:0] <= codereg[1025:0];
stopcount <= 0;
current_state <= next_state;
end
endcase
end
//assignments for current pixel location to draw
assign X = coderegshifter[18:11];
assign Y = coderegshifter[10:3];
assign colour = coderegshifter[2:0];
reg [3:0] counter_out;
assign input_x = X + counter_out[1:0];
assign input_y = Y + counter_out[3:2];
//counter for 4*4
always @(posedge CLOCK_50)
begin
if (counter_out == 4'b1111)
begin
counter_out <= 4'b0;
end
else
begin
counter_out <= counter_out + 1;
end
end
//timer for delay
reg [6:0] count = 7'b0;
reg delay;
always @(posedge CLOCK_50)
begin
if(count==7'd100)//adjustable counter for delay
begin
count<=7'd0;
delay<=0;
end
else if(stopcount)
begin
count<=7'd0;
end
else
begin
count<=count+1;
delay<=1;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O31A_BEHAVIORAL_V
`define SKY130_FD_SC_HD__O31A_BEHAVIORAL_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__o31a (
X ,
A1,
A2,
A3,
B1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X, or0_out, B1 );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O31A_BEHAVIORAL_V |
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Data Cache top level ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instantiation of all DC blocks. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_dc_top.v,v $
// Revision 1.8 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.6.4.2 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.6.4.1 2003/07/08 15:36:37 lampret
// Added embedded memory QMEM.
//
// Revision 1.6 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.5 2002/08/18 19:54:47 lampret
// Added store buffer.
//
// Revision 1.4 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.3 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.9 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
// no message
//
// Revision 1.4 2001/08/13 03:36:20 lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
// Revision 1.3 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.2 2001/07/22 03:31:53 lampret
// Fixed RAM's oen bug. Cache bypass under development.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "rtl/verilog/or1200/timescale.v"
// synopsys translate_on
`include "rtl/verilog/or1200/or1200_defines.v"
//
// Data cache
//
module or1200_dc_top(
// Rst, clk and clock control
clk, rst,
// External i/f
dcsb_dat_o, dcsb_adr_o, dcsb_cyc_o, dcsb_stb_o, dcsb_we_o, dcsb_sel_o, dcsb_cab_o,
dcsb_dat_i, dcsb_ack_i, dcsb_err_i,
// Internal i/f
dc_en,
dcqmem_adr_i, dcqmem_cycstb_i, dcqmem_ci_i,
dcqmem_we_i, dcqmem_sel_i, dcqmem_tag_i, dcqmem_dat_i,
dcqmem_dat_o, dcqmem_ack_o, dcqmem_rty_o, dcqmem_err_o, dcqmem_tag_o,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// SPRs
spr_cs, spr_write, spr_dat_i
);
parameter dw = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// External I/F
//
output [dw-1:0] dcsb_dat_o;
output [31:0] dcsb_adr_o;
output dcsb_cyc_o;
output dcsb_stb_o;
output dcsb_we_o;
output [3:0] dcsb_sel_o;
output dcsb_cab_o;
input [dw-1:0] dcsb_dat_i;
input dcsb_ack_i;
input dcsb_err_i;
//
// Internal I/F
//
input dc_en;
input [31:0] dcqmem_adr_i;
input dcqmem_cycstb_i;
input dcqmem_ci_i;
input dcqmem_we_i;
input [3:0] dcqmem_sel_i;
input [3:0] dcqmem_tag_i;
input [dw-1:0] dcqmem_dat_i;
output [dw-1:0] dcqmem_dat_o;
output dcqmem_ack_o;
output dcqmem_rty_o;
output dcqmem_err_o;
output [3:0] dcqmem_tag_o;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// SPR access
//
input spr_cs;
input spr_write;
input [31:0] spr_dat_i;
//
// Internal wires and regs
//
wire tag_v;
wire [`OR1200_DCTAG_W-2:0] tag;
wire [dw-1:0] to_dcram;
wire [dw-1:0] from_dcram;
wire [31:0] saved_addr;
wire [3:0] dcram_we;
wire dctag_we;
wire [31:0] dc_addr;
wire dcfsm_biu_read;
wire dcfsm_biu_write;
reg tagcomp_miss;
wire [`OR1200_DCINDXH:`OR1200_DCLS] dctag_addr;
wire dctag_en;
wire dctag_v;
wire dc_inv;
wire dcfsm_first_hit_ack;
wire dcfsm_first_miss_ack;
wire dcfsm_first_miss_err;
wire dcfsm_burst;
wire dcfsm_tag_we;
`ifdef OR1200_BIST
//
// RAM BIST
//
wire mbist_ram_so;
wire mbist_tag_so;
wire mbist_ram_si = mbist_si_i;
wire mbist_tag_si = mbist_ram_so;
assign mbist_so_o = mbist_tag_so;
`endif
//
// Simple assignments
//
assign dcsb_adr_o = dc_addr;
assign dc_inv = spr_cs & spr_write;
assign dctag_we = dcfsm_tag_we | dc_inv;
assign dctag_addr = dc_inv ? spr_dat_i[`OR1200_DCINDXH:`OR1200_DCLS] : dc_addr[`OR1200_DCINDXH:`OR1200_DCLS];
assign dctag_en = dc_inv | dc_en;
assign dctag_v = ~dc_inv;
//
// Data to BIU is from DCRAM when DC is enabled or from LSU when
// DC is disabled
//
assign dcsb_dat_o = dcqmem_dat_i;
//
// Bypases of the DC when DC is disabled
//
assign dcsb_cyc_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcqmem_cycstb_i;
assign dcsb_stb_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcqmem_cycstb_i;
assign dcsb_we_o = (dc_en) ? dcfsm_biu_write : dcqmem_we_i;
assign dcsb_sel_o = (dc_en & dcfsm_biu_read & !dcfsm_biu_write & !dcqmem_ci_i) ? 4'b1111 : dcqmem_sel_i;
assign dcsb_cab_o = (dc_en) ? dcfsm_burst : 1'b0;
assign dcqmem_rty_o = ~dcqmem_ack_o;
assign dcqmem_tag_o = dcqmem_err_o ? `OR1200_DTAG_BE : dcqmem_tag_i;
//
// DC/LSU normal and error termination
//
assign dcqmem_ack_o = dc_en ? dcfsm_first_hit_ack | dcfsm_first_miss_ack : dcsb_ack_i;
assign dcqmem_err_o = dc_en ? dcfsm_first_miss_err : dcsb_err_i;
//
// Select between claddr generated by DC FSM and addr[3:2] generated by LSU
//
//assign dc_addr = (dcfsm_biu_read | dcfsm_biu_write) ? saved_addr : dcqmem_adr_i;
//
// Select between input data generated by LSU or by BIU
//
assign to_dcram = (dcfsm_biu_read) ? dcsb_dat_i : dcqmem_dat_i;
//
// Select between data generated by DCRAM or passed by BIU
//
assign dcqmem_dat_o = dcfsm_first_miss_ack | !dc_en ? dcsb_dat_i : from_dcram;
//
// Tag comparison
//
always @(tag or saved_addr or tag_v) begin
if ((tag != saved_addr[31:`OR1200_DCTAGL]) || !tag_v)
tagcomp_miss = 1'b1;
else
tagcomp_miss = 1'b0;
end
//
// Instantiation of DC Finite State Machine
//
or1200_dc_fsm or1200_dc_fsm(
.clk(clk),
.rst(rst),
.dc_en(dc_en),
.dcqmem_cycstb_i(dcqmem_cycstb_i),
.dcqmem_ci_i(dcqmem_ci_i),
.dcqmem_we_i(dcqmem_we_i),
.dcqmem_sel_i(dcqmem_sel_i),
.tagcomp_miss(tagcomp_miss),
.biudata_valid(dcsb_ack_i),
.biudata_error(dcsb_err_i),
.start_addr(dcqmem_adr_i),
.saved_addr(saved_addr),
.dcram_we(dcram_we),
.biu_read(dcfsm_biu_read),
.biu_write(dcfsm_biu_write),
.first_hit_ack(dcfsm_first_hit_ack),
.first_miss_ack(dcfsm_first_miss_ack),
.first_miss_err(dcfsm_first_miss_err),
.burst(dcfsm_burst),
.tag_we(dcfsm_tag_we),
.dc_addr(dc_addr)
);
//
// Instantiation of DC main memory
//
or1200_dc_ram or1200_dc_ram(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_ram_si),
.mbist_so_o(mbist_ram_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.addr(dc_addr[`OR1200_DCINDXH:2]),
.en(dc_en),
.we(dcram_we),
.datain(to_dcram),
.dataout(from_dcram)
);
//
// Instantiation of DC TAG memory
//
or1200_dc_tag or1200_dc_tag(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_tag_si),
.mbist_so_o(mbist_tag_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.addr(dctag_addr),
.en(dctag_en),
.we(dctag_we),
.datain({dc_addr[31:`OR1200_DCTAGL], dctag_v}),
.tag_v(tag_v),
.tag(tag)
);
endmodule
|
// ====================================================================
// Radio-86RK FPGA REPLICA
//
// Copyright (C) 2011 Dmitry Tselikov
//
// This core is distributed under modified BSD license.
// For complete licensing information see LICENSE.TXT.
// --------------------------------------------------------------------
//
// An open implementation of Radio-86RK home computer
//
// Author: Dmitry Tselikov http://bashkiria-2m.narod.ru/
//
// Design File: radio86rk.v
//
// Top level design file.
// --------------------------------------------------------------------
// Ported to "Aeon Lite" by Dmitriy Schapotschkin aka ILoveSpeccy
// http://www.speccyland.net '2015
module radio86rk(
input clk50,
inout [15:0] SRAM_DQ, // SRAM Data bus 16 Bits
output [17:0] SRAM_ADDR, // SRAM Address bus 18 Bits
output SRAM_UB_N, // SRAM High-byte Data Mask
output SRAM_LB_N, // SRAM Low-byte Data Mask
output SRAM_WE_N, // SRAM Write Enable
output SRAM_CE_N, // SRAM Chip Enable
output SRAM_OE_N, // SRAM Output Enable
output SOUND_L,
output SOUND_R,
output VGA_HS,
output VGA_VS,
output [3:0] VGA_R,
output [3:0] VGA_G,
output [3:0] VGA_B,
input PS2_CLK,
input PS2_DAT,
input SD_DAT, // SD Card Data (MISO)
output SD_DAT3, // SD Card Data 3 (CSn)
output SD_CMD, // SD Card Command Signal (MOSI)
output SD_CLK // SD Card Clock (SCK)
);
reg startup;
reg tapein = 1'b0;
wire hdla;
wire cpurst;
wire videomode;
wire[7:0] ppa1_o;
wire[7:0] ppa1_a;
wire[7:0] ppa1_b;
wire[7:0] ppa1_c;
//////////////////// RESET ////////////////////
reg[3:0] reset_cnt;
reg reset_n;
wire reset = ~reset_n;
always @(posedge clk50) begin
// if (KEY[0] && reset_cnt==4'd14)
if (!cpurst && reset_cnt==4'd14)
reset_n <= 1'b1;
else begin
reset_n <= 1'b0;
reset_cnt <= reset_cnt+4'd1;
end
end
//////////////////// MEM ////////////////////
wire sram_msb = 0;
wire[7:0] mem_o = sram_msb ? SRAM_DQ[15:8] : SRAM_DQ[7:0];
wire[7:0] rom_o;
assign SRAM_DQ[7:0] = SRAM_WE_N| sram_msb ? 8'bZZZZZZZZ : cpu_o;
assign SRAM_DQ[15:8] = 8'bZZZZZZZZ; // SRAM_WE_N|~sram_msb ? 8'bZZZZZZZZ : cpu_o;
assign SRAM_ADDR = vid_rd ? {3'b000,vid_addr[14:0]} : {3'b000,addrbus[14:0]};
assign SRAM_UB_N = vid_rd ? 1'b0 : ~sram_msb;
assign SRAM_LB_N = vid_rd ? 1'b0 : sram_msb;
assign SRAM_WE_N = vid_rd ? 1'b1 : cpu_wr_n|addrbus[15]|hlda;
assign SRAM_OE_N = ~(vid_rd|cpu_rd);
assign SRAM_CE_N = 0;
biossd rom(.clka(clk50), .addra({addrbus[11]|startup,addrbus[10:0]}), .douta(rom_o));
//////////////////// CPU ////////////////////
wire[15:0] addrbus;
wire[7:0] cpu_o;
wire cpu_sync;
wire cpu_rd;
wire cpu_wr_n;
wire cpu_int;
wire cpu_inta_n;
wire inte;
reg[7:0] cpu_i;
always @(*)
casex (addrbus[15:13])
3'b0xx: cpu_i = startup ? rom_o : mem_o;
3'b100: cpu_i = ppa1_o;
3'b101: cpu_i = sd_o;
3'b110: cpu_i = crt_o;
3'b111: cpu_i = rom_o;
endcase
wire ppa1_we_n = addrbus[15:13]!=3'b100|cpu_wr_n;
wire ppa2_we_n = addrbus[15:13]!=3'b101|cpu_wr_n;
wire crt_we_n = addrbus[15:13]!=3'b110|cpu_wr_n;
wire crt_rd_n = addrbus[15:13]!=3'b110|~cpu_rd;
wire dma_we_n = addrbus[15:13]!=3'b111|cpu_wr_n;
reg cpu_flag;
reg[10:0] cpu_cnt;
wire cpu_ce = cpu_ce2;
wire cpu_ce2 = cpu_flag^cpu_cnt[10];
always @(posedge clk50) begin
cpu_cnt <= cpu_cnt + 11'd41;
cpu_flag <= cpu_flag^cpu_ce2;
startup <= reset|(startup&~addrbus[15]);
end
k580wm80a CPU(.clk(clk50), .ce(cpu_ce & hlda==0), .reset(reset),
.idata(cpu_i), .addr(addrbus), .sync(cpu_sync), .rd(cpu_rd), .wr_n(cpu_wr_n),
.intr(cpu_int), .inta_n(cpu_inta_n), .odata(cpu_o), .inte_o(inte));
//////////////////// VIDEO ////////////////////
wire[7:0] crt_o;
wire[3:0] vid_line;
wire[6:0] vid_char;
wire[15:0] vid_addr;
wire[3:0] dma_dack;
wire[7:0] dma_o;
wire[1:0] vid_lattr;
wire[1:0] vid_gattr;
wire vid_cce,vid_drq,vid_irq;
wire vid_lten,vid_vsp,vid_rvv,vid_hilight;
wire dma_owe_n,dma_ord_n,dma_oiowe_n,dma_oiord_n;
wire vid_rd = ~dma_oiord_n;
k580wt57 dma(.clk(clk50), .ce(vid_cce), .reset(reset),
.iaddr(addrbus[3:0]), .idata(cpu_o), .drq({1'b0,vid_drq,2'b00}), .iwe_n(dma_we_n), .ird_n(1'b1),
.hlda(hlda), .hrq(hlda), .dack(dma_dack), .odata(dma_o), .oaddr(vid_addr),
.owe_n(dma_owe_n), .ord_n(dma_ord_n), .oiowe_n(dma_oiowe_n), .oiord_n(dma_oiord_n) );
k580wg75 crt(.clk(clk50), .ce(vid_cce),
.iaddr(addrbus[0]), .idata(cpu_o), .iwe_n(crt_we_n), .ird_n(crt_rd_n),
.vrtc(VGA_VS), .hrtc(VGA_HS), .dack(dma_dack[2]), .ichar(mem_o), .drq(vid_drq), .irq(vid_irq),
.odata(crt_o), .line(vid_line), .ochar(vid_char), .lten(vid_lten), .vsp(vid_vsp),
.rvv(vid_rvv), .hilight(vid_hilight), .lattr(vid_lattr), .gattr(vid_gattr) );
rk_video vid(.clk50mhz(clk50), .hr(VGA_HS), .vr(VGA_VS), .cce(vid_cce),
.r(VGA_R), .g(VGA_G), .b(VGA_B), .line(vid_line), .ichar(vid_char),
.vsp(vid_vsp), .lten(vid_lten), .rvv(vid_rvv), .videomode(videomode) );
//////////////////// KBD ////////////////////
wire[7:0] kbd_o;
wire[2:0] kbd_shift;
rk_kbd kbd(.clk(clk50), .reset(reset), .ps2_clk(PS2_CLK), .ps2_dat(PS2_DAT),
.addr(~ppa1_a), .odata(kbd_o), .cpurst(cpurst), .videomode(videomode), .shift(kbd_shift));
//////////////////// SYS PPA ////////////////////
k580ww55 ppa1(.clk(clk50), .reset(reset), .addr(addrbus[1:0]), .we_n(ppa1_we_n),
.idata(cpu_o), .odata(ppa1_o), .ipa(ppa1_a), .opa(ppa1_a),
.ipb(~kbd_o), .opb(ppa1_b), .ipc({~kbd_shift,tapein,ppa1_c[3:0]}), .opc(ppa1_c));
//////////////////// SOUND ////////////////////
assign SOUND_L = ppa1_c[0]^inte;
assign SOUND_R = ppa1_c[0]^inte;
//////////////////// SD CARD ////////////////////
reg sdcs;
reg sdclk;
reg sdcmd;
reg[6:0] sddata;
wire[7:0] sd_o = {sddata, SD_DAT};
assign SD_DAT3 = ~sdcs;
assign SD_CMD = sdcmd;
assign SD_CLK = sdclk;
always @(posedge clk50 or posedge reset) begin
if (reset) begin
sdcs <= 1'b0;
sdclk <= 1'b0;
sdcmd <= 1'h1;
end else begin
if (addrbus[0]==1'b0 && ~ppa2_we_n) sdcs <= cpu_o[0];
if (addrbus[0]==1'b1 && ~ppa2_we_n) begin
if (sdclk) sddata <= {sddata[5:0],SD_DAT};
sdcmd <= cpu_o[7];
sdclk <= 1'b0;
end
if (cpu_rd) sdclk <= 1'b1;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XOR2_0_V
`define SKY130_FD_SC_LP__XOR2_0_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog wrapper for xor2 with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__xor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xor2_0 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xor2_0 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__XOR2_0_V
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: O.87xd
// \ \ Application: netgen
// / / Filename: adder.v
// /___/ /\ Timestamp: Thu Nov 8 18:31:31 2012
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/ktown/caeSMVMv2/coregen/tmp/_cg/adder.ngc /home/ktown/caeSMVMv2/coregen/tmp/_cg/adder.v
// Device : 5vlx330ff1760-1
// Input file : /home/ktown/caeSMVMv2/coregen/tmp/_cg/adder.ngc
// Output file : /home/ktown/caeSMVMv2/coregen/tmp/_cg/adder.v
// # of Modules : 1
// Design Name : adder
// Xilinx : /remote/Xilinx/13.4/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module adder (
clk, result, a, b
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
output [63 : 0] result;
input [63 : 0] a;
input [63 : 0] b;
// synthesis translate_off
wire sig00000001;
wire sig00000002;
wire sig00000003;
wire sig00000004;
wire sig00000005;
wire sig00000006;
wire sig00000007;
wire sig00000008;
wire sig00000009;
wire sig0000000a;
wire sig0000000b;
wire sig0000000c;
wire sig0000000d;
wire sig0000000e;
wire sig0000000f;
wire sig00000010;
wire sig00000011;
wire sig00000012;
wire sig00000013;
wire sig00000014;
wire sig00000015;
wire sig00000016;
wire sig00000017;
wire sig00000018;
wire sig00000019;
wire sig0000001a;
wire sig0000001b;
wire sig0000001c;
wire sig0000001d;
wire sig0000001e;
wire sig0000001f;
wire sig00000020;
wire sig00000021;
wire sig00000022;
wire sig00000023;
wire sig00000024;
wire sig00000025;
wire sig00000026;
wire sig00000027;
wire sig00000028;
wire sig00000029;
wire sig0000002a;
wire sig0000002b;
wire sig0000002c;
wire sig0000002d;
wire sig0000002e;
wire sig0000002f;
wire sig00000030;
wire sig00000031;
wire sig00000032;
wire sig00000033;
wire sig00000034;
wire sig00000035;
wire sig00000036;
wire sig00000037;
wire sig00000038;
wire sig00000039;
wire sig0000003a;
wire sig0000003b;
wire sig0000003c;
wire sig0000003d;
wire sig0000003e;
wire sig0000003f;
wire sig00000040;
wire sig00000041;
wire sig00000042;
wire sig00000043;
wire sig00000044;
wire sig00000045;
wire sig00000046;
wire sig00000047;
wire sig00000048;
wire sig00000049;
wire sig0000004a;
wire sig0000004b;
wire sig0000004c;
wire sig0000004d;
wire sig0000004e;
wire sig0000004f;
wire sig00000050;
wire sig00000051;
wire sig00000052;
wire sig00000053;
wire sig00000054;
wire sig00000055;
wire sig00000056;
wire sig00000057;
wire sig00000058;
wire sig00000059;
wire sig0000005a;
wire sig0000005b;
wire sig0000005c;
wire sig0000005d;
wire sig0000005e;
wire sig0000005f;
wire sig00000060;
wire sig00000061;
wire sig00000062;
wire sig00000063;
wire sig00000064;
wire sig00000065;
wire sig00000066;
wire sig00000067;
wire sig00000068;
wire sig00000069;
wire sig0000006a;
wire sig0000006b;
wire sig0000006c;
wire sig0000006d;
wire sig0000006e;
wire sig0000006f;
wire sig00000070;
wire sig00000071;
wire sig00000072;
wire sig00000073;
wire sig00000074;
wire sig00000075;
wire sig00000076;
wire sig00000077;
wire sig00000078;
wire sig00000079;
wire sig0000007a;
wire sig0000007b;
wire sig0000007c;
wire sig0000007d;
wire sig0000007e;
wire sig0000007f;
wire sig00000080;
wire sig00000081;
wire sig00000082;
wire sig00000083;
wire sig00000084;
wire sig00000085;
wire sig00000086;
wire sig00000087;
wire sig00000088;
wire sig00000089;
wire sig0000008a;
wire sig0000008b;
wire sig0000008c;
wire sig0000008d;
wire sig0000008e;
wire sig0000008f;
wire sig00000090;
wire sig00000091;
wire sig00000092;
wire sig00000093;
wire sig00000094;
wire sig00000095;
wire sig00000096;
wire sig00000097;
wire sig00000098;
wire sig00000099;
wire sig0000009a;
wire sig0000009b;
wire sig0000009c;
wire sig0000009d;
wire sig0000009e;
wire sig0000009f;
wire sig000000a0;
wire sig000000a1;
wire sig000000a2;
wire sig000000a3;
wire sig000000a4;
wire sig000000a5;
wire sig000000a6;
wire sig000000a7;
wire sig000000a8;
wire sig000000a9;
wire sig000000aa;
wire sig000000ab;
wire sig000000ac;
wire sig000000ad;
wire sig000000ae;
wire sig000000af;
wire sig000000b0;
wire sig000000b1;
wire sig000000b2;
wire sig000000b3;
wire sig000000b4;
wire sig000000b5;
wire sig000000b6;
wire sig000000b7;
wire sig000000b8;
wire sig000000b9;
wire sig000000ba;
wire sig000000bb;
wire sig000000bc;
wire sig000000bd;
wire sig000000be;
wire sig000000bf;
wire sig000000c0;
wire sig000000c1;
wire sig000000c2;
wire sig000000c3;
wire sig000000c4;
wire sig000000c5;
wire sig000000c6;
wire sig000000c7;
wire sig000000c8;
wire sig000000c9;
wire sig000000ca;
wire sig000000cb;
wire sig000000cc;
wire sig000000cd;
wire sig000000ce;
wire sig000000cf;
wire sig000000d0;
wire sig000000d1;
wire sig000000d2;
wire sig000000d3;
wire sig000000d4;
wire sig000000d5;
wire sig000000d6;
wire sig000000d7;
wire sig000000d8;
wire sig000000d9;
wire sig000000da;
wire sig000000db;
wire sig000000dc;
wire sig000000dd;
wire sig000000de;
wire sig000000df;
wire sig000000e0;
wire sig000000e1;
wire sig000000e2;
wire sig000000e3;
wire sig000000e4;
wire sig000000e5;
wire sig000000e6;
wire sig000000e7;
wire sig000000e8;
wire sig000000e9;
wire sig000000ea;
wire sig000000eb;
wire sig000000ec;
wire sig000000ed;
wire sig000000ee;
wire sig000000ef;
wire sig000000f0;
wire sig000000f1;
wire sig000000f2;
wire sig000000f3;
wire sig000000f4;
wire sig000000f5;
wire sig000000f6;
wire sig000000f7;
wire sig000000f8;
wire sig000000f9;
wire sig000000fa;
wire sig000000fb;
wire sig000000fc;
wire sig000000fd;
wire sig000000fe;
wire sig000000ff;
wire sig00000100;
wire sig00000101;
wire sig00000102;
wire sig00000103;
wire sig00000104;
wire sig00000105;
wire sig00000106;
wire sig00000107;
wire sig00000108;
wire sig00000109;
wire sig0000010a;
wire sig0000010b;
wire sig0000010c;
wire sig0000010d;
wire sig0000010e;
wire sig0000010f;
wire sig00000110;
wire sig00000111;
wire sig00000112;
wire sig00000113;
wire sig00000114;
wire sig00000115;
wire sig00000116;
wire sig00000117;
wire sig00000118;
wire sig00000119;
wire sig0000011a;
wire sig0000011b;
wire sig0000011c;
wire sig0000011d;
wire sig0000011e;
wire sig0000011f;
wire sig00000120;
wire sig00000121;
wire sig00000122;
wire sig00000123;
wire sig00000124;
wire sig00000125;
wire sig00000126;
wire sig00000127;
wire sig00000128;
wire sig00000129;
wire sig0000012a;
wire sig0000012b;
wire sig0000012c;
wire sig0000012d;
wire sig0000012e;
wire sig0000012f;
wire sig00000130;
wire sig00000131;
wire sig00000132;
wire sig00000133;
wire sig00000134;
wire sig00000135;
wire sig00000136;
wire sig00000137;
wire sig00000138;
wire sig00000139;
wire sig0000013a;
wire sig0000013b;
wire sig0000013c;
wire sig0000013d;
wire sig0000013e;
wire sig0000013f;
wire sig00000140;
wire sig00000141;
wire sig00000142;
wire sig00000143;
wire sig00000144;
wire sig00000145;
wire sig00000146;
wire sig00000147;
wire sig00000148;
wire sig00000149;
wire sig0000014a;
wire sig0000014b;
wire sig0000014c;
wire sig0000014d;
wire sig0000014e;
wire sig0000014f;
wire sig00000150;
wire sig00000151;
wire sig00000152;
wire sig00000153;
wire sig00000154;
wire sig00000155;
wire sig00000156;
wire sig00000157;
wire sig00000158;
wire sig00000159;
wire sig0000015a;
wire sig0000015b;
wire sig0000015c;
wire sig0000015d;
wire sig0000015e;
wire sig0000015f;
wire sig00000160;
wire sig00000161;
wire sig00000162;
wire sig00000163;
wire sig00000164;
wire sig00000165;
wire sig00000166;
wire sig00000167;
wire sig00000168;
wire sig00000169;
wire sig0000016a;
wire sig0000016b;
wire sig0000016c;
wire sig0000016d;
wire sig0000016e;
wire sig0000016f;
wire sig00000170;
wire sig00000171;
wire sig00000172;
wire sig00000173;
wire sig00000174;
wire sig00000175;
wire sig00000176;
wire sig00000177;
wire sig00000178;
wire sig00000179;
wire sig0000017a;
wire sig0000017b;
wire sig0000017c;
wire sig0000017d;
wire sig0000017e;
wire sig0000017f;
wire sig00000180;
wire sig00000181;
wire sig00000182;
wire sig00000183;
wire sig00000184;
wire sig00000185;
wire sig00000186;
wire sig00000187;
wire sig00000188;
wire sig00000189;
wire sig0000018a;
wire sig0000018b;
wire sig0000018c;
wire sig0000018d;
wire sig0000018e;
wire sig0000018f;
wire sig00000190;
wire sig00000191;
wire sig00000192;
wire sig00000193;
wire sig00000194;
wire sig00000195;
wire sig00000196;
wire sig00000197;
wire sig00000198;
wire sig00000199;
wire sig0000019a;
wire sig0000019b;
wire sig0000019c;
wire sig0000019d;
wire sig0000019e;
wire sig0000019f;
wire sig000001a0;
wire sig000001a1;
wire sig000001a2;
wire sig000001a3;
wire sig000001a4;
wire sig000001a5;
wire sig000001a6;
wire sig000001a7;
wire sig000001a8;
wire sig000001a9;
wire sig000001aa;
wire sig000001ab;
wire sig000001ac;
wire sig000001ad;
wire sig000001ae;
wire sig000001af;
wire sig000001b0;
wire sig000001b1;
wire sig000001b2;
wire sig000001b3;
wire sig000001b4;
wire sig000001b5;
wire sig000001b6;
wire sig000001b7;
wire sig000001b8;
wire sig000001b9;
wire sig000001ba;
wire sig000001bb;
wire sig000001bc;
wire sig000001bd;
wire sig000001be;
wire sig000001bf;
wire sig000001c0;
wire sig000001c1;
wire sig000001c2;
wire sig000001c3;
wire sig000001c4;
wire sig000001c5;
wire sig000001c6;
wire sig000001c7;
wire sig000001c8;
wire sig000001c9;
wire sig000001ca;
wire sig000001cb;
wire sig000001cc;
wire sig000001cd;
wire sig000001ce;
wire sig000001cf;
wire sig000001d0;
wire sig000001d1;
wire sig000001d2;
wire sig000001d3;
wire sig000001d4;
wire sig000001d5;
wire sig000001d6;
wire sig000001d7;
wire sig000001d8;
wire sig000001d9;
wire sig000001da;
wire sig000001db;
wire sig000001dc;
wire sig000001dd;
wire sig000001de;
wire sig000001df;
wire sig000001e0;
wire sig000001e1;
wire sig000001e2;
wire sig000001e3;
wire sig000001e4;
wire sig000001e5;
wire sig000001e6;
wire sig000001e7;
wire sig000001e8;
wire sig000001e9;
wire sig000001ea;
wire sig000001eb;
wire sig000001ec;
wire sig000001ed;
wire sig000001ee;
wire sig000001ef;
wire sig000001f0;
wire sig000001f1;
wire sig000001f2;
wire sig000001f3;
wire sig000001f4;
wire sig000001f5;
wire sig000001f6;
wire sig000001f7;
wire sig000001f8;
wire sig000001f9;
wire sig000001fa;
wire sig000001fb;
wire sig000001fc;
wire sig000001fd;
wire sig000001fe;
wire sig000001ff;
wire sig00000200;
wire sig00000201;
wire sig00000202;
wire sig00000203;
wire sig00000204;
wire sig00000205;
wire sig00000206;
wire sig00000207;
wire sig00000208;
wire sig00000209;
wire sig0000020a;
wire sig0000020b;
wire sig0000020c;
wire sig0000020d;
wire sig0000020e;
wire sig0000020f;
wire sig00000210;
wire sig00000211;
wire sig00000212;
wire sig00000213;
wire sig00000214;
wire sig00000215;
wire sig00000216;
wire sig00000217;
wire sig00000218;
wire sig00000219;
wire sig0000021a;
wire sig0000021b;
wire sig0000021c;
wire sig0000021d;
wire sig0000021e;
wire sig0000021f;
wire sig00000220;
wire sig00000221;
wire sig00000222;
wire sig00000223;
wire sig00000224;
wire sig00000225;
wire sig00000226;
wire sig00000227;
wire sig00000228;
wire sig00000229;
wire sig0000022a;
wire sig0000022b;
wire sig0000022c;
wire sig0000022d;
wire sig0000022e;
wire sig0000022f;
wire sig00000230;
wire sig00000231;
wire sig00000232;
wire sig00000233;
wire sig00000234;
wire sig00000235;
wire sig00000236;
wire sig00000237;
wire sig00000238;
wire sig00000239;
wire sig0000023a;
wire sig0000023b;
wire sig0000023c;
wire sig0000023d;
wire sig0000023e;
wire sig0000023f;
wire sig00000240;
wire sig00000241;
wire sig00000242;
wire sig00000243;
wire sig00000244;
wire sig00000245;
wire sig00000246;
wire sig00000247;
wire sig00000248;
wire sig00000249;
wire sig0000024a;
wire sig0000024b;
wire sig0000024c;
wire sig0000024d;
wire sig0000024e;
wire sig0000024f;
wire sig00000250;
wire sig00000251;
wire sig00000252;
wire sig00000253;
wire sig00000254;
wire sig00000255;
wire sig00000256;
wire sig00000257;
wire sig00000258;
wire sig00000259;
wire sig0000025a;
wire sig0000025b;
wire sig0000025c;
wire sig0000025d;
wire sig0000025e;
wire sig0000025f;
wire sig00000260;
wire sig00000261;
wire sig00000262;
wire sig00000263;
wire sig00000264;
wire sig00000265;
wire sig00000266;
wire sig00000267;
wire sig00000268;
wire sig00000269;
wire sig0000026a;
wire sig0000026b;
wire sig0000026c;
wire sig0000026d;
wire sig0000026e;
wire sig0000026f;
wire sig00000270;
wire sig00000271;
wire sig00000272;
wire sig00000273;
wire sig00000274;
wire sig00000275;
wire sig00000276;
wire sig00000277;
wire sig00000278;
wire sig00000279;
wire sig0000027a;
wire sig0000027b;
wire sig0000027c;
wire sig0000027d;
wire sig0000027e;
wire sig0000027f;
wire sig00000280;
wire sig00000281;
wire sig00000282;
wire sig00000283;
wire sig00000284;
wire sig00000285;
wire sig00000286;
wire sig00000287;
wire sig00000288;
wire sig00000289;
wire sig0000028a;
wire sig0000028b;
wire sig0000028c;
wire sig0000028d;
wire sig0000028e;
wire sig0000028f;
wire sig00000290;
wire sig00000291;
wire sig00000292;
wire sig00000293;
wire sig00000294;
wire sig00000295;
wire sig00000296;
wire sig00000297;
wire sig00000298;
wire sig00000299;
wire sig0000029a;
wire sig0000029b;
wire sig0000029c;
wire sig0000029d;
wire sig0000029e;
wire sig0000029f;
wire sig000002a0;
wire sig000002a1;
wire sig000002a2;
wire sig000002a3;
wire sig000002a4;
wire sig000002a5;
wire sig000002a6;
wire sig000002a7;
wire sig000002a8;
wire sig000002a9;
wire sig000002aa;
wire sig000002ab;
wire sig000002ac;
wire sig000002ad;
wire sig000002ae;
wire sig000002af;
wire sig000002b0;
wire sig000002b1;
wire sig000002b2;
wire sig000002b3;
wire sig000002b4;
wire sig000002b5;
wire sig000002b6;
wire sig000002b7;
wire sig000002b8;
wire sig000002b9;
wire sig000002ba;
wire sig000002bb;
wire sig000002bc;
wire sig000002bd;
wire sig000002be;
wire sig000002bf;
wire sig000002c0;
wire sig000002c1;
wire sig000002c2;
wire sig000002c3;
wire sig000002c4;
wire sig000002c5;
wire sig000002c6;
wire sig000002c7;
wire sig000002c8;
wire sig000002c9;
wire sig000002ca;
wire sig000002cb;
wire sig000002cc;
wire sig000002cd;
wire sig000002ce;
wire sig000002cf;
wire sig000002d0;
wire sig000002d1;
wire sig000002d2;
wire sig000002d3;
wire sig000002d4;
wire sig000002d5;
wire sig000002d6;
wire sig000002d7;
wire sig000002d8;
wire sig000002d9;
wire sig000002da;
wire sig000002db;
wire sig000002dc;
wire sig000002dd;
wire sig000002de;
wire sig000002df;
wire sig000002e0;
wire sig000002e1;
wire sig000002e2;
wire sig000002e3;
wire sig000002e4;
wire sig000002e5;
wire sig000002e6;
wire sig000002e7;
wire sig000002e8;
wire sig000002e9;
wire sig000002ea;
wire sig000002eb;
wire sig000002ec;
wire sig000002ed;
wire sig000002ee;
wire sig000002ef;
wire sig000002f0;
wire sig000002f1;
wire sig000002f2;
wire sig000002f3;
wire sig000002f4;
wire sig000002f5;
wire sig000002f6;
wire sig000002f7;
wire sig000002f8;
wire sig000002f9;
wire sig000002fa;
wire sig000002fb;
wire sig000002fc;
wire sig000002fd;
wire sig000002fe;
wire sig000002ff;
wire sig00000300;
wire sig00000301;
wire sig00000302;
wire sig00000303;
wire sig00000304;
wire sig00000305;
wire sig00000306;
wire sig00000307;
wire sig00000308;
wire sig00000309;
wire sig0000030a;
wire sig0000030b;
wire sig0000030c;
wire sig0000030d;
wire sig0000030e;
wire sig0000030f;
wire sig00000310;
wire sig00000311;
wire sig00000312;
wire sig00000313;
wire sig00000314;
wire sig00000315;
wire sig00000316;
wire sig00000317;
wire sig00000318;
wire sig00000319;
wire sig0000031a;
wire sig0000031b;
wire sig0000031c;
wire sig0000031d;
wire sig0000031e;
wire sig0000031f;
wire sig00000320;
wire sig00000321;
wire sig00000322;
wire sig00000323;
wire sig00000324;
wire sig00000325;
wire sig00000326;
wire sig00000327;
wire sig00000328;
wire sig00000329;
wire sig0000032a;
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wire sig0000073a;
wire sig0000073b;
wire sig0000073c;
wire sig0000073d;
wire sig0000073e;
wire sig0000073f;
wire sig00000740;
wire sig00000741;
wire sig00000742;
wire sig00000743;
wire sig00000744;
wire sig00000745;
wire sig00000746;
wire sig00000747;
wire sig00000748;
wire sig00000749;
wire sig0000074a;
wire sig0000074b;
wire sig0000074c;
wire sig0000074d;
wire sig0000074e;
wire sig0000074f;
wire sig00000750;
wire sig00000751;
wire sig00000752;
wire sig00000753;
wire sig00000754;
wire sig00000755;
wire sig00000756;
wire sig00000757;
wire sig00000758;
wire sig00000759;
wire sig0000075a;
wire sig0000075b;
wire sig0000075c;
wire sig0000075d;
wire sig0000075e;
wire sig0000075f;
wire sig00000760;
wire sig00000761;
wire sig00000762;
wire sig00000763;
wire sig00000764;
wire sig00000765;
wire sig00000766;
wire sig00000767;
wire sig00000768;
wire sig00000769;
wire sig0000076a;
wire sig0000076b;
wire sig0000076c;
wire sig0000076d;
wire sig0000076e;
wire sig0000076f;
wire sig00000770;
wire sig00000771;
wire sig00000772;
wire sig00000773;
wire sig00000774;
wire sig00000775;
wire sig00000776;
wire sig00000777;
wire sig00000778;
wire sig00000779;
wire sig0000077a;
wire sig0000077b;
wire sig0000077c;
wire sig0000077d;
wire sig0000077e;
wire sig0000077f;
wire sig00000780;
wire sig00000781;
wire sig00000782;
wire sig00000783;
wire sig00000784;
wire sig00000785;
wire sig00000786;
wire sig00000787;
wire sig00000788;
wire sig00000789;
wire sig0000078a;
wire sig0000078b;
wire sig0000078c;
wire sig0000078d;
wire sig0000078e;
wire sig0000078f;
wire sig00000790;
wire sig00000791;
wire sig00000792;
wire sig00000793;
wire sig00000794;
wire sig00000795;
wire sig00000796;
wire sig00000797;
wire sig00000798;
wire sig00000799;
wire sig0000079a;
wire sig0000079b;
wire sig0000079c;
wire sig0000079d;
wire sig0000079e;
wire sig0000079f;
wire sig000007a0;
wire sig000007a1;
wire sig000007a2;
wire sig000007a3;
wire sig000007a4;
wire sig000007a5;
wire sig000007a6;
wire sig000007a7;
wire sig000007a8;
wire sig000007a9;
wire sig000007aa;
wire sig000007ab;
wire sig000007ac;
wire sig000007ad;
wire sig000007ae;
wire sig000007af;
wire sig000007b0;
wire sig000007b1;
wire sig000007b2;
wire sig000007b3;
wire sig000007b4;
wire sig000007b5;
wire sig000007b6;
wire sig000007b7;
wire sig000007b8;
wire sig000007b9;
wire sig000007ba;
wire sig000007bb;
wire sig000007bc;
wire sig000007bd;
wire sig000007be;
wire sig000007bf;
wire sig000007c0;
wire sig000007c1;
wire sig000007c2;
wire sig000007c3;
wire sig000007c4;
wire sig000007c5;
wire sig000007c6;
wire sig000007c7;
wire sig000007c8;
wire sig000007c9;
wire sig000007ca;
wire sig000007cb;
wire sig000007cc;
wire sig000007cd;
wire sig000007ce;
wire sig000007cf;
wire sig000007d0;
wire sig000007d1;
wire sig000007d2;
wire sig000007d3;
wire sig000007d4;
wire sig000007d5;
wire sig000007d6;
wire sig000007d7;
wire sig000007d8;
wire sig000007d9;
wire sig000007da;
wire sig000007db;
wire sig000007dc;
wire sig000007dd;
wire sig000007de;
wire sig000007df;
wire sig000007e0;
wire sig000007e1;
wire sig000007e2;
wire sig000007e3;
wire sig000007e4;
wire sig000007e5;
wire sig000007e6;
wire sig000007e7;
wire sig000007e8;
wire sig000007e9;
wire sig000007ea;
wire sig000007eb;
wire sig000007ec;
wire sig000007ed;
wire sig000007ee;
wire sig000007ef;
wire sig000007f0;
wire sig000007f1;
wire sig000007f2;
wire sig000007f3;
wire sig000007f4;
wire sig000007f5;
wire sig000007f6;
wire sig000007f7;
wire sig000007f8;
wire sig000007f9;
wire sig000007fa;
wire sig000007fb;
wire sig000007fc;
wire sig000007fd;
wire sig000007fe;
wire sig000007ff;
wire sig00000800;
wire sig00000801;
wire sig00000802;
wire sig00000803;
wire sig00000804;
wire sig00000805;
wire sig00000806;
wire sig00000807;
wire sig00000808;
wire sig00000809;
wire sig0000080a;
wire sig0000080b;
wire sig0000080c;
wire sig0000080d;
wire sig0000080e;
wire sig0000080f;
wire sig00000810;
wire sig00000811;
wire sig00000812;
wire sig00000813;
wire sig00000814;
wire sig00000815;
wire sig00000816;
wire sig00000817;
wire sig00000818;
wire sig00000819;
wire sig0000081a;
wire sig0000081b;
wire sig0000081c;
wire sig0000081d;
wire sig0000081e;
wire sig0000081f;
wire sig00000820;
wire sig00000821;
wire sig00000822;
wire sig00000823;
wire sig00000824;
wire sig00000825;
wire sig00000826;
wire sig00000827;
wire sig00000828;
wire sig00000829;
wire sig0000082a;
wire sig0000082b;
wire sig0000082c;
wire sig0000082d;
wire sig0000082e;
wire sig0000082f;
wire sig00000830;
wire sig00000831;
wire sig00000832;
wire sig00000833;
wire sig00000834;
wire sig00000835;
wire sig00000836;
wire sig00000837;
wire sig00000838;
wire sig00000839;
wire sig0000083a;
wire sig0000083b;
wire sig0000083c;
wire sig0000083d;
wire sig0000083e;
wire sig0000083f;
wire sig00000840;
wire sig00000841;
wire sig00000842;
wire sig00000843;
wire sig00000844;
wire sig00000845;
wire sig00000846;
wire sig00000847;
wire sig00000848;
wire sig00000849;
wire sig0000084a;
wire sig0000084b;
wire sig0000084c;
wire sig0000084d;
wire sig0000084e;
wire sig0000084f;
wire sig00000850;
wire sig00000851;
wire sig00000852;
wire sig00000853;
wire sig00000854;
wire sig00000855;
wire sig00000856;
wire sig00000857;
wire sig00000858;
wire sig00000859;
wire sig0000085a;
wire sig0000085b;
wire sig0000085c;
wire sig0000085d;
wire sig0000085e;
wire sig0000085f;
wire sig00000860;
wire sig00000861;
wire sig00000862;
wire sig00000863;
wire sig00000864;
wire sig00000865;
wire sig00000866;
wire sig00000867;
wire sig00000868;
wire sig00000869;
wire sig0000086a;
wire sig0000086b;
wire sig0000086c;
wire sig0000086d;
wire sig0000086e;
wire sig0000086f;
wire sig00000870;
wire sig00000871;
wire sig00000872;
wire sig00000873;
wire sig00000874;
wire sig00000875;
wire sig00000876;
wire sig00000877;
wire sig00000878;
wire sig00000879;
wire sig0000087a;
wire sig0000087b;
wire sig0000087c;
wire sig0000087d;
wire sig0000087e;
wire sig0000087f;
wire sig00000880;
wire sig00000881;
wire sig00000882;
wire sig00000883;
wire sig00000884;
wire sig00000885;
wire sig00000886;
wire sig00000887;
wire sig00000888;
wire sig00000889;
wire sig0000088a;
wire sig0000088b;
wire sig0000088c;
wire sig0000088d;
wire sig0000088e;
wire sig0000088f;
wire sig00000890;
wire sig00000891;
wire sig00000892;
wire sig00000893;
wire sig00000894;
wire sig00000895;
wire sig00000896;
wire sig00000897;
wire sig00000898;
wire sig00000899;
wire sig0000089a;
wire sig0000089b;
wire sig0000089c;
wire sig0000089d;
wire sig0000089e;
wire sig0000089f;
wire sig000008a0;
wire sig000008a1;
wire sig000008a2;
wire sig000008a3;
wire sig000008a4;
wire sig000008a5;
wire sig000008a6;
wire sig000008a7;
wire sig000008a8;
wire sig000008a9;
wire sig000008aa;
wire sig000008ab;
wire sig000008ac;
wire sig000008ad;
wire sig000008ae;
wire sig000008af;
wire sig000008b0;
wire sig000008b1;
wire sig000008b2;
wire sig000008b3;
wire sig000008b4;
wire sig000008b5;
wire sig000008b6;
wire sig000008b7;
wire sig000008b8;
wire \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/sign_op ;
wire sig000008b9;
wire sig000008ba;
wire sig000008bb;
wire sig000008bc;
wire NLW_blk000002f9_O_UNCONNECTED;
wire NLW_blk000002fa_O_UNCONNECTED;
wire NLW_blk000002fc_O_UNCONNECTED;
wire NLW_blk000002fe_O_UNCONNECTED;
wire NLW_blk00000300_O_UNCONNECTED;
wire NLW_blk00000302_O_UNCONNECTED;
wire NLW_blk00000304_O_UNCONNECTED;
wire NLW_blk00000306_O_UNCONNECTED;
wire NLW_blk00000308_O_UNCONNECTED;
wire NLW_blk0000030a_O_UNCONNECTED;
wire NLW_blk0000030c_O_UNCONNECTED;
wire NLW_blk000003d9_O_UNCONNECTED;
wire NLW_blk00000875_Q15_UNCONNECTED;
wire NLW_blk00000877_Q15_UNCONNECTED;
wire NLW_blk00000879_Q15_UNCONNECTED;
wire NLW_blk0000087b_Q15_UNCONNECTED;
wire NLW_blk0000087d_Q15_UNCONNECTED;
wire NLW_blk0000087f_Q15_UNCONNECTED;
wire NLW_blk00000881_Q15_UNCONNECTED;
wire NLW_blk00000883_Q15_UNCONNECTED;
wire NLW_blk00000885_Q15_UNCONNECTED;
wire NLW_blk00000887_Q15_UNCONNECTED;
wire NLW_blk00000889_Q15_UNCONNECTED;
wire NLW_blk0000088b_Q15_UNCONNECTED;
wire NLW_blk0000088d_Q15_UNCONNECTED;
wire NLW_blk0000088f_Q15_UNCONNECTED;
wire NLW_blk00000891_Q15_UNCONNECTED;
wire NLW_blk00000893_Q15_UNCONNECTED;
wire NLW_blk00000895_Q15_UNCONNECTED;
wire NLW_blk00000897_Q15_UNCONNECTED;
wire NLW_blk00000899_Q15_UNCONNECTED;
wire NLW_blk0000089b_Q15_UNCONNECTED;
wire NLW_blk0000089d_Q15_UNCONNECTED;
wire NLW_blk0000089f_Q15_UNCONNECTED;
wire NLW_blk000008a1_Q15_UNCONNECTED;
wire NLW_blk000008a3_Q15_UNCONNECTED;
wire NLW_blk000008a5_Q15_UNCONNECTED;
wire NLW_blk000008a7_Q15_UNCONNECTED;
wire NLW_blk000008a9_Q15_UNCONNECTED;
wire NLW_blk000008ab_Q15_UNCONNECTED;
wire NLW_blk000008ad_Q15_UNCONNECTED;
wire NLW_blk000008af_Q15_UNCONNECTED;
wire NLW_blk000008b1_Q15_UNCONNECTED;
wire NLW_blk000008b3_Q15_UNCONNECTED;
wire NLW_blk000008b5_Q15_UNCONNECTED;
wire NLW_blk000008b7_Q15_UNCONNECTED;
wire NLW_blk000008b9_Q15_UNCONNECTED;
wire NLW_blk000008bb_Q15_UNCONNECTED;
wire NLW_blk000008bd_Q15_UNCONNECTED;
wire NLW_blk000008bf_Q15_UNCONNECTED;
wire NLW_blk000008c1_Q15_UNCONNECTED;
wire NLW_blk000008c3_Q15_UNCONNECTED;
wire NLW_blk000008c5_Q15_UNCONNECTED;
wire NLW_blk000008c7_Q15_UNCONNECTED;
wire NLW_blk000008c9_Q15_UNCONNECTED;
wire NLW_blk000008cb_Q15_UNCONNECTED;
wire NLW_blk000008cd_Q15_UNCONNECTED;
wire NLW_blk000008cf_Q15_UNCONNECTED;
wire NLW_blk000008d1_Q15_UNCONNECTED;
wire NLW_blk000008d3_Q15_UNCONNECTED;
wire NLW_blk000008d5_Q15_UNCONNECTED;
wire NLW_blk000008d7_Q15_UNCONNECTED;
wire NLW_blk000008d9_Q15_UNCONNECTED;
wire NLW_blk000008db_Q15_UNCONNECTED;
wire NLW_blk000008dd_Q15_UNCONNECTED;
wire NLW_blk000008df_Q15_UNCONNECTED;
wire NLW_blk000008e1_Q15_UNCONNECTED;
wire NLW_blk000008e3_Q15_UNCONNECTED;
wire NLW_blk000008e5_Q15_UNCONNECTED;
wire NLW_blk000008e7_Q15_UNCONNECTED;
wire NLW_blk000008e9_Q15_UNCONNECTED;
wire NLW_blk000008eb_Q15_UNCONNECTED;
wire NLW_blk000008ed_Q15_UNCONNECTED;
wire NLW_blk000008ef_Q15_UNCONNECTED;
wire NLW_blk000008f1_Q15_UNCONNECTED;
wire NLW_blk000008f3_Q15_UNCONNECTED;
wire NLW_blk000008f5_Q15_UNCONNECTED;
wire NLW_blk000008f7_Q15_UNCONNECTED;
wire NLW_blk000008f9_Q15_UNCONNECTED;
wire NLW_blk000008fb_Q15_UNCONNECTED;
wire NLW_blk000008fd_Q15_UNCONNECTED;
wire NLW_blk000008ff_Q15_UNCONNECTED;
wire NLW_blk00000901_Q15_UNCONNECTED;
wire NLW_blk00000903_Q15_UNCONNECTED;
wire NLW_blk00000905_Q15_UNCONNECTED;
wire NLW_blk00000907_Q15_UNCONNECTED;
wire [10 : 0] \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op ;
wire [51 : 0] \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op ;
assign
result[63] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/sign_op ,
result[62] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [10],
result[61] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [9],
result[60] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [8],
result[59] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [7],
result[58] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [6],
result[57] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [5],
result[56] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [4],
result[55] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [3],
result[54] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [2],
result[53] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [1],
result[52] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [0],
result[51] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [51],
result[50] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [50],
result[49] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [49],
result[48] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [48],
result[47] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [47],
result[46] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [46],
result[45] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [45],
result[44] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [44],
result[43] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [43],
result[42] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [42],
result[41] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [41],
result[40] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [40],
result[39] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [39],
result[38] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [38],
result[37] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [37],
result[36] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [36],
result[35] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [35],
result[34] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [34],
result[33] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [33],
result[32] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [32],
result[31] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [31],
result[30] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [30],
result[29] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [29],
result[28] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [28],
result[27] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [27],
result[26] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [26],
result[25] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [25],
result[24] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [24],
result[23] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [23],
result[22] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [22],
result[21] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [21],
result[20] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [20],
result[19] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [19],
result[18] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [18],
result[17] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [17],
result[16] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [16],
result[15] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [15],
result[14] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [14],
result[13] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [13],
result[12] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [12],
result[11] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [11],
result[10] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [10],
result[9] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [9],
result[8] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [8],
result[7] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [7],
result[6] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [6],
result[5] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [5],
result[4] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [4],
result[3] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [3],
result[2] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [2],
result[1] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [1],
result[0] = \U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [0];
GND blk00000001 (
.G(sig00000001)
);
VCC blk00000002 (
.P(sig00000002)
);
FDE #(
.INIT ( 1'b0 ))
blk00000003 (
.C(clk),
.CE(sig00000002),
.D(sig000003df),
.Q(sig0000035e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000004 (
.C(clk),
.CE(sig00000002),
.D(sig000003dd),
.Q(sig0000035a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000005 (
.C(clk),
.CE(sig00000002),
.D(sig00000130),
.Q(sig0000035b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000006 (
.C(clk),
.CE(sig00000002),
.D(sig0000035c),
.Q(sig0000035d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000007 (
.C(clk),
.CE(sig00000002),
.D(sig000008bc),
.Q(sig0000035c)
);
MUXCY blk00000008 (
.CI(sig00000001),
.DI(sig00000458),
.S(sig00000316),
.O(sig00000315)
);
XORCY blk00000009 (
.CI(sig00000001),
.LI(sig00000316),
.O(sig00000369)
);
MUXCY blk0000000a (
.CI(sig00000315),
.DI(sig00000001),
.S(sig00000360),
.O(sig00000317)
);
XORCY blk0000000b (
.CI(sig00000315),
.LI(sig00000360),
.O(sig0000036b)
);
MUXCY blk0000000c (
.CI(sig00000317),
.DI(sig00000001),
.S(sig00000361),
.O(sig00000318)
);
XORCY blk0000000d (
.CI(sig00000317),
.LI(sig00000361),
.O(sig0000036c)
);
MUXCY blk0000000e (
.CI(sig00000318),
.DI(sig00000001),
.S(sig00000362),
.O(sig00000319)
);
XORCY blk0000000f (
.CI(sig00000318),
.LI(sig00000362),
.O(sig0000036d)
);
MUXCY blk00000010 (
.CI(sig00000319),
.DI(sig00000001),
.S(sig00000363),
.O(sig0000031a)
);
XORCY blk00000011 (
.CI(sig00000319),
.LI(sig00000363),
.O(sig0000036e)
);
MUXCY blk00000012 (
.CI(sig0000031a),
.DI(sig00000001),
.S(sig00000364),
.O(sig0000031b)
);
XORCY blk00000013 (
.CI(sig0000031a),
.LI(sig00000364),
.O(sig0000036f)
);
MUXCY blk00000014 (
.CI(sig0000031b),
.DI(sig00000001),
.S(sig00000365),
.O(sig0000031c)
);
XORCY blk00000015 (
.CI(sig0000031b),
.LI(sig00000365),
.O(sig00000370)
);
MUXCY blk00000016 (
.CI(sig0000031c),
.DI(sig00000001),
.S(sig00000366),
.O(sig0000031d)
);
XORCY blk00000017 (
.CI(sig0000031c),
.LI(sig00000366),
.O(sig00000371)
);
MUXCY blk00000018 (
.CI(sig0000031d),
.DI(sig00000001),
.S(sig00000367),
.O(sig0000031e)
);
XORCY blk00000019 (
.CI(sig0000031d),
.LI(sig00000367),
.O(sig00000372)
);
MUXCY blk0000001a (
.CI(sig0000031e),
.DI(sig00000001),
.S(sig00000368),
.O(sig0000031f)
);
XORCY blk0000001b (
.CI(sig0000031e),
.LI(sig00000368),
.O(sig00000373)
);
XORCY blk0000001c (
.CI(sig0000031f),
.LI(sig0000035f),
.O(sig0000036a)
);
FD #(
.INIT ( 1'b0 ))
blk0000001d (
.C(clk),
.D(sig000003d6),
.Q(sig0000034f)
);
FD #(
.INIT ( 1'b0 ))
blk0000001e (
.C(clk),
.D(sig000003d5),
.Q(sig0000034e)
);
FD #(
.INIT ( 1'b0 ))
blk0000001f (
.C(clk),
.D(sig000003d3),
.Q(sig0000034c)
);
FD #(
.INIT ( 1'b0 ))
blk00000020 (
.C(clk),
.D(sig000003d2),
.Q(sig0000034b)
);
FD #(
.INIT ( 1'b0 ))
blk00000021 (
.C(clk),
.D(sig000003d1),
.Q(sig0000034a)
);
FD #(
.INIT ( 1'b0 ))
blk00000022 (
.C(clk),
.D(sig000003d0),
.Q(sig00000349)
);
FD #(
.INIT ( 1'b0 ))
blk00000023 (
.C(clk),
.D(sig000003cf),
.Q(sig00000348)
);
FD #(
.INIT ( 1'b0 ))
blk00000024 (
.C(clk),
.D(sig000003ce),
.Q(sig00000347)
);
FD #(
.INIT ( 1'b0 ))
blk00000025 (
.C(clk),
.D(sig000003cd),
.Q(sig00000346)
);
FD #(
.INIT ( 1'b0 ))
blk00000026 (
.C(clk),
.D(sig000003cc),
.Q(sig00000345)
);
FD #(
.INIT ( 1'b0 ))
blk00000027 (
.C(clk),
.D(sig000003cb),
.Q(sig00000344)
);
FD #(
.INIT ( 1'b0 ))
blk00000028 (
.C(clk),
.D(sig000003ca),
.Q(sig00000343)
);
FD #(
.INIT ( 1'b0 ))
blk00000029 (
.C(clk),
.D(sig000003c8),
.Q(sig00000341)
);
FD #(
.INIT ( 1'b0 ))
blk0000002a (
.C(clk),
.D(sig000003c7),
.Q(sig00000340)
);
FD #(
.INIT ( 1'b0 ))
blk0000002b (
.C(clk),
.D(sig000003c6),
.Q(sig0000033f)
);
FD #(
.INIT ( 1'b0 ))
blk0000002c (
.C(clk),
.D(sig000003c5),
.Q(sig0000033e)
);
FD #(
.INIT ( 1'b0 ))
blk0000002d (
.C(clk),
.D(sig000003c4),
.Q(sig0000033d)
);
FD #(
.INIT ( 1'b0 ))
blk0000002e (
.C(clk),
.D(sig000003c3),
.Q(sig0000033c)
);
FD #(
.INIT ( 1'b0 ))
blk0000002f (
.C(clk),
.D(sig000003c2),
.Q(sig0000033b)
);
FD #(
.INIT ( 1'b0 ))
blk00000030 (
.C(clk),
.D(sig000003c1),
.Q(sig0000033a)
);
FD #(
.INIT ( 1'b0 ))
blk00000031 (
.C(clk),
.D(sig000003c0),
.Q(sig00000339)
);
FD #(
.INIT ( 1'b0 ))
blk00000032 (
.C(clk),
.D(sig000003bf),
.Q(sig00000338)
);
FD #(
.INIT ( 1'b0 ))
blk00000033 (
.C(clk),
.D(sig000003bd),
.Q(sig00000336)
);
FD #(
.INIT ( 1'b0 ))
blk00000034 (
.C(clk),
.D(sig000003bc),
.Q(sig00000335)
);
FD #(
.INIT ( 1'b0 ))
blk00000035 (
.C(clk),
.D(sig000003bb),
.Q(sig00000334)
);
FD #(
.INIT ( 1'b0 ))
blk00000036 (
.C(clk),
.D(sig000003ba),
.Q(sig00000333)
);
FD #(
.INIT ( 1'b0 ))
blk00000037 (
.C(clk),
.D(sig000003b9),
.Q(sig00000332)
);
FD #(
.INIT ( 1'b0 ))
blk00000038 (
.C(clk),
.D(sig000003b8),
.Q(sig00000331)
);
FD #(
.INIT ( 1'b0 ))
blk00000039 (
.C(clk),
.D(sig000003b7),
.Q(sig00000330)
);
FD #(
.INIT ( 1'b0 ))
blk0000003a (
.C(clk),
.D(sig000003b6),
.Q(sig0000032f)
);
FD #(
.INIT ( 1'b0 ))
blk0000003b (
.C(clk),
.D(sig000003b5),
.Q(sig0000032e)
);
FD #(
.INIT ( 1'b0 ))
blk0000003c (
.C(clk),
.D(sig000003b4),
.Q(sig0000032d)
);
FD #(
.INIT ( 1'b0 ))
blk0000003d (
.C(clk),
.D(sig000003b2),
.Q(sig0000032b)
);
FD #(
.INIT ( 1'b0 ))
blk0000003e (
.C(clk),
.D(sig000003b1),
.Q(sig0000032a)
);
FD #(
.INIT ( 1'b0 ))
blk0000003f (
.C(clk),
.D(sig000003b0),
.Q(sig00000329)
);
FD #(
.INIT ( 1'b0 ))
blk00000040 (
.C(clk),
.D(sig000003af),
.Q(sig00000328)
);
FD #(
.INIT ( 1'b0 ))
blk00000041 (
.C(clk),
.D(sig000003ae),
.Q(sig00000327)
);
FD #(
.INIT ( 1'b0 ))
blk00000042 (
.C(clk),
.D(sig000003ad),
.Q(sig00000326)
);
FD #(
.INIT ( 1'b0 ))
blk00000043 (
.C(clk),
.D(sig000003ac),
.Q(sig00000325)
);
FD #(
.INIT ( 1'b0 ))
blk00000044 (
.C(clk),
.D(sig000003ab),
.Q(sig00000324)
);
FD #(
.INIT ( 1'b0 ))
blk00000045 (
.C(clk),
.D(sig000003aa),
.Q(sig00000323)
);
FD #(
.INIT ( 1'b0 ))
blk00000046 (
.C(clk),
.D(sig000003a9),
.Q(sig00000322)
);
FD #(
.INIT ( 1'b0 ))
blk00000047 (
.C(clk),
.D(sig000003dc),
.Q(sig00000355)
);
FD #(
.INIT ( 1'b0 ))
blk00000048 (
.C(clk),
.D(sig000003db),
.Q(sig00000354)
);
FD #(
.INIT ( 1'b0 ))
blk00000049 (
.C(clk),
.D(sig000003da),
.Q(sig00000353)
);
FD #(
.INIT ( 1'b0 ))
blk0000004a (
.C(clk),
.D(sig000003d9),
.Q(sig00000352)
);
FD #(
.INIT ( 1'b0 ))
blk0000004b (
.C(clk),
.D(sig000003d8),
.Q(sig0000034d)
);
FD #(
.INIT ( 1'b0 ))
blk0000004c (
.C(clk),
.D(sig000003d4),
.Q(sig00000342)
);
FD #(
.INIT ( 1'b0 ))
blk0000004d (
.C(clk),
.D(sig000003c9),
.Q(sig00000337)
);
FD #(
.INIT ( 1'b0 ))
blk0000004e (
.C(clk),
.D(sig000003be),
.Q(sig0000032c)
);
FD #(
.INIT ( 1'b0 ))
blk0000004f (
.C(clk),
.D(sig000003b3),
.Q(sig00000321)
);
FD #(
.INIT ( 1'b0 ))
blk00000050 (
.C(clk),
.D(sig000003a8),
.Q(sig00000320)
);
FDE #(
.INIT ( 1'b0 ))
blk00000051 (
.C(clk),
.CE(sig00000002),
.D(sig0000036a),
.Q(sig0000001e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000052 (
.C(clk),
.CE(sig00000002),
.D(sig00000373),
.Q(sig00000026)
);
FDE #(
.INIT ( 1'b0 ))
blk00000053 (
.C(clk),
.CE(sig00000002),
.D(sig00000372),
.Q(sig00000025)
);
FDE #(
.INIT ( 1'b0 ))
blk00000054 (
.C(clk),
.CE(sig00000002),
.D(sig00000371),
.Q(sig00000024)
);
FDE #(
.INIT ( 1'b0 ))
blk00000055 (
.C(clk),
.CE(sig00000002),
.D(sig00000370),
.Q(sig00000023)
);
FDE #(
.INIT ( 1'b0 ))
blk00000056 (
.C(clk),
.CE(sig00000002),
.D(sig0000036f),
.Q(sig00000022)
);
FDE #(
.INIT ( 1'b0 ))
blk00000057 (
.C(clk),
.CE(sig00000002),
.D(sig0000036e),
.Q(sig00000021)
);
FDE #(
.INIT ( 1'b0 ))
blk00000058 (
.C(clk),
.CE(sig00000002),
.D(sig0000036d),
.Q(sig00000020)
);
FDE #(
.INIT ( 1'b0 ))
blk00000059 (
.C(clk),
.CE(sig00000002),
.D(sig0000036c),
.Q(sig0000001f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000005a (
.C(clk),
.CE(sig00000002),
.D(sig0000036b),
.Q(sig0000001d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000005b (
.C(clk),
.CE(sig00000002),
.D(sig00000369),
.Q(sig0000001c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000005c (
.C(clk),
.CE(sig00000002),
.D(sig000000ce),
.Q(sig00000027)
);
FDE #(
.INIT ( 1'b0 ))
blk0000005d (
.C(clk),
.CE(sig00000002),
.D(sig000000d9),
.Q(sig00000028)
);
FDE #(
.INIT ( 1'b0 ))
blk0000005e (
.C(clk),
.CE(sig00000002),
.D(sig000000e4),
.Q(sig00000033)
);
FDE #(
.INIT ( 1'b0 ))
blk0000005f (
.C(clk),
.CE(sig00000002),
.D(sig000000ef),
.Q(sig0000003e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000060 (
.C(clk),
.CE(sig00000002),
.D(sig000000fa),
.Q(sig00000049)
);
FDE #(
.INIT ( 1'b0 ))
blk00000061 (
.C(clk),
.CE(sig00000002),
.D(sig00000100),
.Q(sig00000054)
);
FDE #(
.INIT ( 1'b0 ))
blk00000062 (
.C(clk),
.CE(sig00000002),
.D(sig00000101),
.Q(sig0000005a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000063 (
.C(clk),
.CE(sig00000002),
.D(sig00000102),
.Q(sig0000005b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000064 (
.C(clk),
.CE(sig00000002),
.D(sig00000103),
.Q(sig0000005c)
);
FDE #(
.INIT ( 1'b0 ))
blk00000065 (
.C(clk),
.CE(sig00000002),
.D(sig00000104),
.Q(sig0000005d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000066 (
.C(clk),
.CE(sig00000002),
.D(sig000000cf),
.Q(sig00000029)
);
FDE #(
.INIT ( 1'b0 ))
blk00000067 (
.C(clk),
.CE(sig00000002),
.D(sig000000d0),
.Q(sig0000002a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000068 (
.C(clk),
.CE(sig00000002),
.D(sig000000d1),
.Q(sig0000002b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000069 (
.C(clk),
.CE(sig00000002),
.D(sig000000d2),
.Q(sig0000002c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000006a (
.C(clk),
.CE(sig00000002),
.D(sig000000d3),
.Q(sig0000002d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000006b (
.C(clk),
.CE(sig00000002),
.D(sig000000d4),
.Q(sig0000002e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000006c (
.C(clk),
.CE(sig00000002),
.D(sig000000d5),
.Q(sig0000002f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000006d (
.C(clk),
.CE(sig00000002),
.D(sig000000d6),
.Q(sig00000030)
);
FDE #(
.INIT ( 1'b0 ))
blk0000006e (
.C(clk),
.CE(sig00000002),
.D(sig000000d7),
.Q(sig00000031)
);
FDE #(
.INIT ( 1'b0 ))
blk0000006f (
.C(clk),
.CE(sig00000002),
.D(sig000000d8),
.Q(sig00000032)
);
FDE #(
.INIT ( 1'b0 ))
blk00000070 (
.C(clk),
.CE(sig00000002),
.D(sig000000da),
.Q(sig00000034)
);
FDE #(
.INIT ( 1'b0 ))
blk00000071 (
.C(clk),
.CE(sig00000002),
.D(sig000000db),
.Q(sig00000035)
);
FDE #(
.INIT ( 1'b0 ))
blk00000072 (
.C(clk),
.CE(sig00000002),
.D(sig000000dc),
.Q(sig00000036)
);
FDE #(
.INIT ( 1'b0 ))
blk00000073 (
.C(clk),
.CE(sig00000002),
.D(sig000000dd),
.Q(sig00000037)
);
FDE #(
.INIT ( 1'b0 ))
blk00000074 (
.C(clk),
.CE(sig00000002),
.D(sig000000de),
.Q(sig00000038)
);
FDE #(
.INIT ( 1'b0 ))
blk00000075 (
.C(clk),
.CE(sig00000002),
.D(sig000000df),
.Q(sig00000039)
);
FDE #(
.INIT ( 1'b0 ))
blk00000076 (
.C(clk),
.CE(sig00000002),
.D(sig000000e0),
.Q(sig0000003a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000077 (
.C(clk),
.CE(sig00000002),
.D(sig000000e1),
.Q(sig0000003b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000078 (
.C(clk),
.CE(sig00000002),
.D(sig000000e2),
.Q(sig0000003c)
);
FDE #(
.INIT ( 1'b0 ))
blk00000079 (
.C(clk),
.CE(sig00000002),
.D(sig000000e3),
.Q(sig0000003d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000007a (
.C(clk),
.CE(sig00000002),
.D(sig000000e5),
.Q(sig0000003f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000007b (
.C(clk),
.CE(sig00000002),
.D(sig000000e6),
.Q(sig00000040)
);
FDE #(
.INIT ( 1'b0 ))
blk0000007c (
.C(clk),
.CE(sig00000002),
.D(sig000000e7),
.Q(sig00000041)
);
FDE #(
.INIT ( 1'b0 ))
blk0000007d (
.C(clk),
.CE(sig00000002),
.D(sig000000e8),
.Q(sig00000042)
);
FDE #(
.INIT ( 1'b0 ))
blk0000007e (
.C(clk),
.CE(sig00000002),
.D(sig000000e9),
.Q(sig00000043)
);
FDE #(
.INIT ( 1'b0 ))
blk0000007f (
.C(clk),
.CE(sig00000002),
.D(sig000000ea),
.Q(sig00000044)
);
FDE #(
.INIT ( 1'b0 ))
blk00000080 (
.C(clk),
.CE(sig00000002),
.D(sig000000eb),
.Q(sig00000045)
);
FDE #(
.INIT ( 1'b0 ))
blk00000081 (
.C(clk),
.CE(sig00000002),
.D(sig000000ec),
.Q(sig00000046)
);
FDE #(
.INIT ( 1'b0 ))
blk00000082 (
.C(clk),
.CE(sig00000002),
.D(sig000000ed),
.Q(sig00000047)
);
FDE #(
.INIT ( 1'b0 ))
blk00000083 (
.C(clk),
.CE(sig00000002),
.D(sig000000ee),
.Q(sig00000048)
);
FDE #(
.INIT ( 1'b0 ))
blk00000084 (
.C(clk),
.CE(sig00000002),
.D(sig000000f0),
.Q(sig0000004a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000085 (
.C(clk),
.CE(sig00000002),
.D(sig000000f1),
.Q(sig0000004b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000086 (
.C(clk),
.CE(sig00000002),
.D(sig000000f2),
.Q(sig0000004c)
);
FDE #(
.INIT ( 1'b0 ))
blk00000087 (
.C(clk),
.CE(sig00000002),
.D(sig000000f3),
.Q(sig0000004d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000088 (
.C(clk),
.CE(sig00000002),
.D(sig000000f4),
.Q(sig0000004e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000089 (
.C(clk),
.CE(sig00000002),
.D(sig000000f5),
.Q(sig0000004f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000008a (
.C(clk),
.CE(sig00000002),
.D(sig000000f6),
.Q(sig00000050)
);
FDE #(
.INIT ( 1'b0 ))
blk0000008b (
.C(clk),
.CE(sig00000002),
.D(sig000000f7),
.Q(sig00000051)
);
FDE #(
.INIT ( 1'b0 ))
blk0000008c (
.C(clk),
.CE(sig00000002),
.D(sig000000f8),
.Q(sig00000052)
);
FDE #(
.INIT ( 1'b0 ))
blk0000008d (
.C(clk),
.CE(sig00000002),
.D(sig000000f9),
.Q(sig00000053)
);
FDE #(
.INIT ( 1'b0 ))
blk0000008e (
.C(clk),
.CE(sig00000002),
.D(sig000000fb),
.Q(sig00000055)
);
FDE #(
.INIT ( 1'b0 ))
blk0000008f (
.C(clk),
.CE(sig00000002),
.D(sig000000fc),
.Q(sig00000056)
);
FDE #(
.INIT ( 1'b0 ))
blk00000090 (
.C(clk),
.CE(sig00000002),
.D(sig000000fd),
.Q(sig00000057)
);
FDE #(
.INIT ( 1'b0 ))
blk00000091 (
.C(clk),
.CE(sig00000002),
.D(sig000000fe),
.Q(sig00000058)
);
FDE #(
.INIT ( 1'b0 ))
blk00000092 (
.C(clk),
.CE(sig00000002),
.D(sig000000ff),
.Q(sig00000059)
);
FDE #(
.INIT ( 1'b0 ))
blk00000093 (
.C(clk),
.CE(sig00000002),
.D(sig00000097),
.Q(sig0000005e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000094 (
.C(clk),
.CE(sig00000002),
.D(sig000000a2),
.Q(sig0000005f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000095 (
.C(clk),
.CE(sig00000002),
.D(sig000000ad),
.Q(sig0000006a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000096 (
.C(clk),
.CE(sig00000002),
.D(sig000000b8),
.Q(sig00000075)
);
FDE #(
.INIT ( 1'b0 ))
blk00000097 (
.C(clk),
.CE(sig00000002),
.D(sig000000c3),
.Q(sig00000080)
);
FDE #(
.INIT ( 1'b0 ))
blk00000098 (
.C(clk),
.CE(sig00000002),
.D(sig000000c9),
.Q(sig0000008b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000099 (
.C(clk),
.CE(sig00000002),
.D(sig000000ca),
.Q(sig00000091)
);
FDE #(
.INIT ( 1'b0 ))
blk0000009a (
.C(clk),
.CE(sig00000002),
.D(sig000000cb),
.Q(sig00000092)
);
FDE #(
.INIT ( 1'b0 ))
blk0000009b (
.C(clk),
.CE(sig00000002),
.D(sig000000cc),
.Q(sig00000093)
);
FDE #(
.INIT ( 1'b0 ))
blk0000009c (
.C(clk),
.CE(sig00000002),
.D(sig000000cd),
.Q(sig00000094)
);
FDE #(
.INIT ( 1'b0 ))
blk0000009d (
.C(clk),
.CE(sig00000002),
.D(sig00000098),
.Q(sig00000060)
);
FDE #(
.INIT ( 1'b0 ))
blk0000009e (
.C(clk),
.CE(sig00000002),
.D(sig00000099),
.Q(sig00000061)
);
FDE #(
.INIT ( 1'b0 ))
blk0000009f (
.C(clk),
.CE(sig00000002),
.D(sig0000009a),
.Q(sig00000062)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a0 (
.C(clk),
.CE(sig00000002),
.D(sig0000009b),
.Q(sig00000063)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a1 (
.C(clk),
.CE(sig00000002),
.D(sig0000009c),
.Q(sig00000064)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a2 (
.C(clk),
.CE(sig00000002),
.D(sig0000009d),
.Q(sig00000065)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a3 (
.C(clk),
.CE(sig00000002),
.D(sig0000009e),
.Q(sig00000066)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a4 (
.C(clk),
.CE(sig00000002),
.D(sig0000009f),
.Q(sig00000067)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a5 (
.C(clk),
.CE(sig00000002),
.D(sig000000a0),
.Q(sig00000068)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a6 (
.C(clk),
.CE(sig00000002),
.D(sig000000a1),
.Q(sig00000069)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a7 (
.C(clk),
.CE(sig00000002),
.D(sig000000a3),
.Q(sig0000006b)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a8 (
.C(clk),
.CE(sig00000002),
.D(sig000000a4),
.Q(sig0000006c)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a9 (
.C(clk),
.CE(sig00000002),
.D(sig000000a5),
.Q(sig0000006d)
);
FDE #(
.INIT ( 1'b0 ))
blk000000aa (
.C(clk),
.CE(sig00000002),
.D(sig000000a6),
.Q(sig0000006e)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ab (
.C(clk),
.CE(sig00000002),
.D(sig000000a7),
.Q(sig0000006f)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ac (
.C(clk),
.CE(sig00000002),
.D(sig000000a8),
.Q(sig00000070)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ad (
.C(clk),
.CE(sig00000002),
.D(sig000000a9),
.Q(sig00000071)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ae (
.C(clk),
.CE(sig00000002),
.D(sig000000aa),
.Q(sig00000072)
);
FDE #(
.INIT ( 1'b0 ))
blk000000af (
.C(clk),
.CE(sig00000002),
.D(sig000000ab),
.Q(sig00000073)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b0 (
.C(clk),
.CE(sig00000002),
.D(sig000000ac),
.Q(sig00000074)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b1 (
.C(clk),
.CE(sig00000002),
.D(sig000000ae),
.Q(sig00000076)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b2 (
.C(clk),
.CE(sig00000002),
.D(sig000000af),
.Q(sig00000077)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b3 (
.C(clk),
.CE(sig00000002),
.D(sig000000b0),
.Q(sig00000078)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b4 (
.C(clk),
.CE(sig00000002),
.D(sig000000b1),
.Q(sig00000079)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b5 (
.C(clk),
.CE(sig00000002),
.D(sig000000b2),
.Q(sig0000007a)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b6 (
.C(clk),
.CE(sig00000002),
.D(sig000000b3),
.Q(sig0000007b)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b7 (
.C(clk),
.CE(sig00000002),
.D(sig000000b4),
.Q(sig0000007c)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b8 (
.C(clk),
.CE(sig00000002),
.D(sig000000b5),
.Q(sig0000007d)
);
FDE #(
.INIT ( 1'b0 ))
blk000000b9 (
.C(clk),
.CE(sig00000002),
.D(sig000000b6),
.Q(sig0000007e)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ba (
.C(clk),
.CE(sig00000002),
.D(sig000000b7),
.Q(sig0000007f)
);
FDE #(
.INIT ( 1'b0 ))
blk000000bb (
.C(clk),
.CE(sig00000002),
.D(sig000000b9),
.Q(sig00000081)
);
FDE #(
.INIT ( 1'b0 ))
blk000000bc (
.C(clk),
.CE(sig00000002),
.D(sig000000ba),
.Q(sig00000082)
);
FDE #(
.INIT ( 1'b0 ))
blk000000bd (
.C(clk),
.CE(sig00000002),
.D(sig000000bb),
.Q(sig00000083)
);
FDE #(
.INIT ( 1'b0 ))
blk000000be (
.C(clk),
.CE(sig00000002),
.D(sig000000bc),
.Q(sig00000084)
);
FDE #(
.INIT ( 1'b0 ))
blk000000bf (
.C(clk),
.CE(sig00000002),
.D(sig000000bd),
.Q(sig00000085)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c0 (
.C(clk),
.CE(sig00000002),
.D(sig000000be),
.Q(sig00000086)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c1 (
.C(clk),
.CE(sig00000002),
.D(sig000000bf),
.Q(sig00000087)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c2 (
.C(clk),
.CE(sig00000002),
.D(sig000000c0),
.Q(sig00000088)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c3 (
.C(clk),
.CE(sig00000002),
.D(sig000000c1),
.Q(sig00000089)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c4 (
.C(clk),
.CE(sig00000002),
.D(sig000000c2),
.Q(sig0000008a)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c5 (
.C(clk),
.CE(sig00000002),
.D(sig000000c4),
.Q(sig0000008c)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c6 (
.C(clk),
.CE(sig00000002),
.D(sig000000c5),
.Q(sig0000008d)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c7 (
.C(clk),
.CE(sig00000002),
.D(sig000000c6),
.Q(sig0000008e)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c8 (
.C(clk),
.CE(sig00000002),
.D(sig000000c7),
.Q(sig0000008f)
);
FDE #(
.INIT ( 1'b0 ))
blk000000c9 (
.C(clk),
.CE(sig00000002),
.D(sig000000c8),
.Q(sig00000090)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ca (
.C(clk),
.CE(sig00000002),
.D(sig0000001f),
.Q(sig00000095)
);
FDE #(
.INIT ( 1'b0 ))
blk000000cb (
.C(clk),
.CE(sig00000002),
.D(sig00000020),
.Q(sig00000096)
);
MUXCY blk000000cc (
.CI(sig00000108),
.DI(sig00000001),
.S(sig00000117),
.O(sig00000109)
);
MUXCY blk000000cd (
.CI(sig00000107),
.DI(sig00000001),
.S(sig00000116),
.O(sig00000108)
);
MUXCY blk000000ce (
.CI(sig00000106),
.DI(sig00000001),
.S(sig00000115),
.O(sig00000107)
);
MUXCY blk000000cf (
.CI(sig00000105),
.DI(sig00000001),
.S(sig00000114),
.O(sig00000106)
);
MUXCY blk000000d0 (
.CI(sig00000112),
.DI(sig00000001),
.S(sig00000120),
.O(sig00000105)
);
MUXCY blk000000d1 (
.CI(sig00000111),
.DI(sig00000001),
.S(sig0000011f),
.O(sig00000112)
);
MUXCY blk000000d2 (
.CI(sig00000110),
.DI(sig00000001),
.S(sig0000011e),
.O(sig00000111)
);
MUXCY blk000000d3 (
.CI(sig0000010f),
.DI(sig00000001),
.S(sig0000011d),
.O(sig00000110)
);
MUXCY blk000000d4 (
.CI(sig0000010e),
.DI(sig00000001),
.S(sig0000011c),
.O(sig0000010f)
);
MUXCY blk000000d5 (
.CI(sig0000010d),
.DI(sig00000001),
.S(sig0000011b),
.O(sig0000010e)
);
MUXCY blk000000d6 (
.CI(sig0000010c),
.DI(sig00000001),
.S(sig0000011a),
.O(sig0000010d)
);
MUXCY blk000000d7 (
.CI(sig0000010b),
.DI(sig00000001),
.S(sig00000119),
.O(sig0000010c)
);
MUXCY blk000000d8 (
.CI(sig0000010a),
.DI(sig00000001),
.S(sig00000118),
.O(sig0000010b)
);
MUXCY blk000000d9 (
.CI(sig00000002),
.DI(sig00000001),
.S(sig00000113),
.O(sig0000010a)
);
FDE #(
.INIT ( 1'b0 ))
blk000000da (
.C(clk),
.CE(sig00000002),
.D(sig00000109),
.Q(sig00000139)
);
FDE #(
.INIT ( 1'b0 ))
blk000000db (
.C(clk),
.CE(sig00000002),
.D(sig00000108),
.Q(sig00000138)
);
FDE #(
.INIT ( 1'b0 ))
blk000000dc (
.C(clk),
.CE(sig00000002),
.D(sig00000107),
.Q(sig00000137)
);
FDE #(
.INIT ( 1'b0 ))
blk000000dd (
.C(clk),
.CE(sig00000002),
.D(sig00000106),
.Q(sig00000136)
);
FDE #(
.INIT ( 1'b0 ))
blk000000de (
.C(clk),
.CE(sig00000002),
.D(sig00000105),
.Q(sig00000135)
);
FDE #(
.INIT ( 1'b0 ))
blk000000df (
.C(clk),
.CE(sig00000002),
.D(sig00000112),
.Q(sig00000142)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e0 (
.C(clk),
.CE(sig00000002),
.D(sig00000111),
.Q(sig00000141)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e1 (
.C(clk),
.CE(sig00000002),
.D(sig00000110),
.Q(sig00000140)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e2 (
.C(clk),
.CE(sig00000002),
.D(sig0000010f),
.Q(sig0000013f)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e3 (
.C(clk),
.CE(sig00000002),
.D(sig0000010e),
.Q(sig0000013e)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e4 (
.C(clk),
.CE(sig00000002),
.D(sig0000010d),
.Q(sig0000013d)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e5 (
.C(clk),
.CE(sig00000002),
.D(sig0000010c),
.Q(sig0000013c)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e6 (
.C(clk),
.CE(sig00000002),
.D(sig0000010b),
.Q(sig0000013b)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e7 (
.C(clk),
.CE(sig00000002),
.D(sig0000010a),
.Q(sig0000013a)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e8 (
.C(clk),
.CE(sig00000002),
.D(sig00000143),
.Q(sig00000121)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e9 (
.C(clk),
.CE(sig00000002),
.D(sig00000148),
.Q(sig00000122)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ea (
.C(clk),
.CE(sig00000002),
.D(sig00000149),
.Q(sig00000128)
);
FDE #(
.INIT ( 1'b0 ))
blk000000eb (
.C(clk),
.CE(sig00000002),
.D(sig0000014a),
.Q(sig00000129)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ec (
.C(clk),
.CE(sig00000002),
.D(sig0000014b),
.Q(sig0000012a)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ed (
.C(clk),
.CE(sig00000002),
.D(sig0000014c),
.Q(sig0000012b)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ee (
.C(clk),
.CE(sig00000002),
.D(sig0000014d),
.Q(sig0000012c)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ef (
.C(clk),
.CE(sig00000002),
.D(sig0000014e),
.Q(sig0000012d)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f0 (
.C(clk),
.CE(sig00000002),
.D(sig0000014f),
.Q(sig0000012e)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f1 (
.C(clk),
.CE(sig00000002),
.D(sig00000150),
.Q(sig0000012f)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f2 (
.C(clk),
.CE(sig00000002),
.D(sig00000144),
.Q(sig00000123)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f3 (
.C(clk),
.CE(sig00000002),
.D(sig00000145),
.Q(sig00000124)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f4 (
.C(clk),
.CE(sig00000002),
.D(sig00000146),
.Q(sig00000125)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f5 (
.C(clk),
.CE(sig00000002),
.D(sig00000147),
.Q(sig00000126)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f6 (
.C(clk),
.CE(sig00000002),
.D(sig00000002),
.Q(sig00000127)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f7 (
.C(clk),
.CE(sig00000002),
.D(sig00000155),
.Q(sig00000130)
);
MUXF8 blk000000f8 (
.I0(sig00000133),
.I1(sig00000134),
.S(sig00000132),
.O(sig00000155)
);
MUXF7 blk000000f9 (
.I0(sig00000153),
.I1(sig00000154),
.S(sig00000131),
.O(sig00000134)
);
MUXF7 blk000000fa (
.I0(sig00000151),
.I1(sig00000152),
.S(sig00000131),
.O(sig00000133)
);
FDE #(
.INIT ( 1'b0 ))
blk000000fb (
.C(clk),
.CE(sig00000002),
.D(sig00000021),
.Q(sig00000131)
);
FDE #(
.INIT ( 1'b0 ))
blk000000fc (
.C(clk),
.CE(sig00000002),
.D(sig00000022),
.Q(sig00000132)
);
FDE #(
.INIT ( 1'b0 ))
blk000000fd (
.C(clk),
.CE(sig00000002),
.D(sig00000263),
.Q(sig000002c0)
);
MUXCY blk000000fe (
.CI(sig000002bf),
.DI(sig00000001),
.S(sig000002c1),
.O(sig00000252)
);
XORCY blk000000ff (
.CI(sig000002bf),
.LI(sig000002c1),
.O(sig00000264)
);
MUXCY blk00000100 (
.CI(sig00000252),
.DI(sig00000001),
.S(sig000002c2),
.O(sig0000025b)
);
XORCY blk00000101 (
.CI(sig00000252),
.LI(sig000002c2),
.O(sig0000026f)
);
MUXCY blk00000102 (
.CI(sig0000025b),
.DI(sig000001c4),
.S(sig000002f2),
.O(sig0000025c)
);
XORCY blk00000103 (
.CI(sig0000025b),
.LI(sig000002f2),
.O(sig00000277)
);
MUXCY blk00000104 (
.CI(sig0000025c),
.DI(sig000001c5),
.S(sig000002f3),
.O(sig0000025d)
);
XORCY blk00000105 (
.CI(sig0000025c),
.LI(sig000002f3),
.O(sig00000278)
);
MUXCY blk00000106 (
.CI(sig0000025d),
.DI(sig000001d0),
.S(sig000002f4),
.O(sig0000025e)
);
XORCY blk00000107 (
.CI(sig0000025d),
.LI(sig000002f4),
.O(sig00000279)
);
MUXCY blk00000108 (
.CI(sig0000025e),
.DI(sig000001d6),
.S(sig000002f5),
.O(sig0000025f)
);
XORCY blk00000109 (
.CI(sig0000025e),
.LI(sig000002f5),
.O(sig0000027a)
);
MUXCY blk0000010a (
.CI(sig0000025f),
.DI(sig000001d7),
.S(sig000002f6),
.O(sig00000260)
);
XORCY blk0000010b (
.CI(sig0000025f),
.LI(sig000002f6),
.O(sig0000027b)
);
MUXCY blk0000010c (
.CI(sig00000260),
.DI(sig000001d8),
.S(sig000002f7),
.O(sig00000261)
);
XORCY blk0000010d (
.CI(sig00000260),
.LI(sig000002f7),
.O(sig0000027c)
);
MUXCY blk0000010e (
.CI(sig00000261),
.DI(sig000001d9),
.S(sig000002f8),
.O(sig00000262)
);
XORCY blk0000010f (
.CI(sig00000261),
.LI(sig000002f8),
.O(sig0000027d)
);
MUXCY blk00000110 (
.CI(sig00000262),
.DI(sig000001da),
.S(sig000002e0),
.O(sig00000248)
);
XORCY blk00000111 (
.CI(sig00000262),
.LI(sig000002e0),
.O(sig0000027e)
);
MUXCY blk00000112 (
.CI(sig00000248),
.DI(sig000001db),
.S(sig000002e1),
.O(sig00000249)
);
XORCY blk00000113 (
.CI(sig00000248),
.LI(sig000002e1),
.O(sig00000265)
);
MUXCY blk00000114 (
.CI(sig00000249),
.DI(sig000001dc),
.S(sig000002e2),
.O(sig0000024a)
);
XORCY blk00000115 (
.CI(sig00000249),
.LI(sig000002e2),
.O(sig00000266)
);
MUXCY blk00000116 (
.CI(sig0000024a),
.DI(sig000001c6),
.S(sig000002e3),
.O(sig0000024b)
);
XORCY blk00000117 (
.CI(sig0000024a),
.LI(sig000002e3),
.O(sig00000267)
);
MUXCY blk00000118 (
.CI(sig0000024b),
.DI(sig000001c7),
.S(sig000002e4),
.O(sig0000024c)
);
XORCY blk00000119 (
.CI(sig0000024b),
.LI(sig000002e4),
.O(sig00000268)
);
MUXCY blk0000011a (
.CI(sig0000024c),
.DI(sig000001c8),
.S(sig000002e5),
.O(sig0000024d)
);
XORCY blk0000011b (
.CI(sig0000024c),
.LI(sig000002e5),
.O(sig00000269)
);
MUXCY blk0000011c (
.CI(sig0000024d),
.DI(sig000001c9),
.S(sig000002e6),
.O(sig0000024e)
);
XORCY blk0000011d (
.CI(sig0000024d),
.LI(sig000002e6),
.O(sig0000026a)
);
MUXCY blk0000011e (
.CI(sig0000024e),
.DI(sig000001ca),
.S(sig000002e7),
.O(sig0000024f)
);
XORCY blk0000011f (
.CI(sig0000024e),
.LI(sig000002e7),
.O(sig0000026b)
);
MUXCY blk00000120 (
.CI(sig0000024f),
.DI(sig000001cb),
.S(sig000002e8),
.O(sig00000250)
);
XORCY blk00000121 (
.CI(sig0000024f),
.LI(sig000002e8),
.O(sig0000026c)
);
MUXCY blk00000122 (
.CI(sig00000250),
.DI(sig000001cc),
.S(sig000002e9),
.O(sig00000251)
);
XORCY blk00000123 (
.CI(sig00000250),
.LI(sig000002e9),
.O(sig0000026d)
);
MUXCY blk00000124 (
.CI(sig00000251),
.DI(sig000001cd),
.S(sig000002ea),
.O(sig00000253)
);
XORCY blk00000125 (
.CI(sig00000251),
.LI(sig000002ea),
.O(sig0000026e)
);
MUXCY blk00000126 (
.CI(sig00000253),
.DI(sig000001ce),
.S(sig000002eb),
.O(sig00000254)
);
XORCY blk00000127 (
.CI(sig00000253),
.LI(sig000002eb),
.O(sig00000270)
);
MUXCY blk00000128 (
.CI(sig00000254),
.DI(sig000001cf),
.S(sig000002ec),
.O(sig00000255)
);
XORCY blk00000129 (
.CI(sig00000254),
.LI(sig000002ec),
.O(sig00000271)
);
MUXCY blk0000012a (
.CI(sig00000255),
.DI(sig000001d1),
.S(sig000002ed),
.O(sig00000256)
);
XORCY blk0000012b (
.CI(sig00000255),
.LI(sig000002ed),
.O(sig00000272)
);
MUXCY blk0000012c (
.CI(sig00000256),
.DI(sig000001d2),
.S(sig000002ee),
.O(sig00000257)
);
XORCY blk0000012d (
.CI(sig00000256),
.LI(sig000002ee),
.O(sig00000273)
);
MUXCY blk0000012e (
.CI(sig00000257),
.DI(sig000001d3),
.S(sig000002ef),
.O(sig00000258)
);
XORCY blk0000012f (
.CI(sig00000257),
.LI(sig000002ef),
.O(sig00000274)
);
MUXCY blk00000130 (
.CI(sig00000258),
.DI(sig000001d4),
.S(sig000002f0),
.O(sig00000259)
);
XORCY blk00000131 (
.CI(sig00000258),
.LI(sig000002f0),
.O(sig00000275)
);
MUXCY blk00000132 (
.CI(sig00000259),
.DI(sig000001d5),
.S(sig000002f1),
.O(sig0000025a)
);
XORCY blk00000133 (
.CI(sig00000259),
.LI(sig000002f1),
.O(sig00000276)
);
XORCY blk00000134 (
.CI(sig0000025a),
.LI(sig00000001),
.O(sig00000263)
);
FD #(
.INIT ( 1'b0 ))
blk00000135 (
.C(clk),
.D(sig00000240),
.Q(sig00000225)
);
FD #(
.INIT ( 1'b0 ))
blk00000136 (
.C(clk),
.D(sig0000023f),
.Q(sig00000224)
);
FD #(
.INIT ( 1'b0 ))
blk00000137 (
.C(clk),
.D(sig0000023e),
.Q(sig00000223)
);
FD #(
.INIT ( 1'b0 ))
blk00000138 (
.C(clk),
.D(sig0000023d),
.Q(sig00000222)
);
FD #(
.INIT ( 1'b0 ))
blk00000139 (
.C(clk),
.D(sig0000023c),
.Q(sig00000221)
);
FD #(
.INIT ( 1'b0 ))
blk0000013a (
.C(clk),
.D(sig0000023b),
.Q(sig00000220)
);
FD #(
.INIT ( 1'b0 ))
blk0000013b (
.C(clk),
.D(sig0000023a),
.Q(sig0000021f)
);
FD #(
.INIT ( 1'b0 ))
blk0000013c (
.C(clk),
.D(sig00000238),
.Q(sig0000021d)
);
FD #(
.INIT ( 1'b0 ))
blk0000013d (
.C(clk),
.D(sig00000237),
.Q(sig0000021c)
);
FD #(
.INIT ( 1'b0 ))
blk0000013e (
.C(clk),
.D(sig00000236),
.Q(sig0000021b)
);
FD #(
.INIT ( 1'b0 ))
blk0000013f (
.C(clk),
.D(sig00000235),
.Q(sig0000021a)
);
FD #(
.INIT ( 1'b0 ))
blk00000140 (
.C(clk),
.D(sig00000234),
.Q(sig00000219)
);
FD #(
.INIT ( 1'b0 ))
blk00000141 (
.C(clk),
.D(sig00000233),
.Q(sig00000218)
);
FD #(
.INIT ( 1'b0 ))
blk00000142 (
.C(clk),
.D(sig00000232),
.Q(sig00000217)
);
FD #(
.INIT ( 1'b0 ))
blk00000143 (
.C(clk),
.D(sig00000231),
.Q(sig00000216)
);
FD #(
.INIT ( 1'b0 ))
blk00000144 (
.C(clk),
.D(sig00000230),
.Q(sig00000215)
);
FD #(
.INIT ( 1'b0 ))
blk00000145 (
.C(clk),
.D(sig0000022f),
.Q(sig00000214)
);
FD #(
.INIT ( 1'b0 ))
blk00000146 (
.C(clk),
.D(sig00000247),
.Q(sig0000022c)
);
FD #(
.INIT ( 1'b0 ))
blk00000147 (
.C(clk),
.D(sig00000246),
.Q(sig0000022b)
);
FD #(
.INIT ( 1'b0 ))
blk00000148 (
.C(clk),
.D(sig00000245),
.Q(sig0000022a)
);
FD #(
.INIT ( 1'b0 ))
blk00000149 (
.C(clk),
.D(sig00000244),
.Q(sig00000229)
);
FD #(
.INIT ( 1'b0 ))
blk0000014a (
.C(clk),
.D(sig00000243),
.Q(sig00000228)
);
FD #(
.INIT ( 1'b0 ))
blk0000014b (
.C(clk),
.D(sig00000242),
.Q(sig00000227)
);
FD #(
.INIT ( 1'b0 ))
blk0000014c (
.C(clk),
.D(sig00000241),
.Q(sig00000226)
);
FD #(
.INIT ( 1'b0 ))
blk0000014d (
.C(clk),
.D(sig00000239),
.Q(sig0000021e)
);
FD #(
.INIT ( 1'b0 ))
blk0000014e (
.C(clk),
.D(sig0000022e),
.Q(sig00000213)
);
FD #(
.INIT ( 1'b0 ))
blk0000014f (
.C(clk),
.D(sig0000022d),
.Q(sig00000212)
);
FD #(
.INIT ( 1'b0 ))
blk00000150 (
.C(clk),
.D(sig00000276),
.Q(sig00000240)
);
FD #(
.INIT ( 1'b0 ))
blk00000151 (
.C(clk),
.D(sig00000275),
.Q(sig0000023f)
);
FD #(
.INIT ( 1'b0 ))
blk00000152 (
.C(clk),
.D(sig00000274),
.Q(sig0000023e)
);
FD #(
.INIT ( 1'b0 ))
blk00000153 (
.C(clk),
.D(sig00000273),
.Q(sig0000023d)
);
FD #(
.INIT ( 1'b0 ))
blk00000154 (
.C(clk),
.D(sig00000272),
.Q(sig0000023c)
);
FD #(
.INIT ( 1'b0 ))
blk00000155 (
.C(clk),
.D(sig00000271),
.Q(sig0000023b)
);
FD #(
.INIT ( 1'b0 ))
blk00000156 (
.C(clk),
.D(sig00000270),
.Q(sig0000023a)
);
FD #(
.INIT ( 1'b0 ))
blk00000157 (
.C(clk),
.D(sig0000026e),
.Q(sig00000238)
);
FD #(
.INIT ( 1'b0 ))
blk00000158 (
.C(clk),
.D(sig0000026d),
.Q(sig00000237)
);
FD #(
.INIT ( 1'b0 ))
blk00000159 (
.C(clk),
.D(sig0000026c),
.Q(sig00000236)
);
FD #(
.INIT ( 1'b0 ))
blk0000015a (
.C(clk),
.D(sig0000026b),
.Q(sig00000235)
);
FD #(
.INIT ( 1'b0 ))
blk0000015b (
.C(clk),
.D(sig0000026a),
.Q(sig00000234)
);
FD #(
.INIT ( 1'b0 ))
blk0000015c (
.C(clk),
.D(sig00000269),
.Q(sig00000233)
);
FD #(
.INIT ( 1'b0 ))
blk0000015d (
.C(clk),
.D(sig00000268),
.Q(sig00000232)
);
FD #(
.INIT ( 1'b0 ))
blk0000015e (
.C(clk),
.D(sig00000267),
.Q(sig00000231)
);
FD #(
.INIT ( 1'b0 ))
blk0000015f (
.C(clk),
.D(sig00000266),
.Q(sig00000230)
);
FD #(
.INIT ( 1'b0 ))
blk00000160 (
.C(clk),
.D(sig00000265),
.Q(sig0000022f)
);
FD #(
.INIT ( 1'b0 ))
blk00000161 (
.C(clk),
.D(sig0000027e),
.Q(sig00000247)
);
FD #(
.INIT ( 1'b0 ))
blk00000162 (
.C(clk),
.D(sig0000027d),
.Q(sig00000246)
);
FD #(
.INIT ( 1'b0 ))
blk00000163 (
.C(clk),
.D(sig0000027c),
.Q(sig00000245)
);
FD #(
.INIT ( 1'b0 ))
blk00000164 (
.C(clk),
.D(sig0000027b),
.Q(sig00000244)
);
FD #(
.INIT ( 1'b0 ))
blk00000165 (
.C(clk),
.D(sig0000027a),
.Q(sig00000243)
);
FD #(
.INIT ( 1'b0 ))
blk00000166 (
.C(clk),
.D(sig00000279),
.Q(sig00000242)
);
FD #(
.INIT ( 1'b0 ))
blk00000167 (
.C(clk),
.D(sig00000278),
.Q(sig00000241)
);
FD #(
.INIT ( 1'b0 ))
blk00000168 (
.C(clk),
.D(sig00000277),
.Q(sig00000239)
);
FD #(
.INIT ( 1'b0 ))
blk00000169 (
.C(clk),
.D(sig0000026f),
.Q(sig0000022e)
);
FD #(
.INIT ( 1'b0 ))
blk0000016a (
.C(clk),
.D(sig00000264),
.Q(sig0000022d)
);
MUXCY blk0000016b (
.CI(sig00000002),
.DI(sig00000001),
.S(sig00000281),
.O(sig00000282)
);
MUXCY blk0000016c (
.CI(sig00000282),
.DI(sig0000018f),
.S(sig000002f9),
.O(sig0000028d)
);
XORCY blk0000016d (
.CI(sig00000282),
.LI(sig000002f9),
.O(sig000002c3)
);
MUXCY blk0000016e (
.CI(sig0000028d),
.DI(sig00000190),
.S(sig00000304),
.O(sig00000297)
);
XORCY blk0000016f (
.CI(sig0000028d),
.LI(sig00000304),
.O(sig000002ce)
);
MUXCY blk00000170 (
.CI(sig00000297),
.DI(sig0000019b),
.S(sig0000030d),
.O(sig00000298)
);
XORCY blk00000171 (
.CI(sig00000297),
.LI(sig0000030d),
.O(sig000002d8)
);
MUXCY blk00000172 (
.CI(sig00000298),
.DI(sig000001a4),
.S(sig0000030e),
.O(sig00000299)
);
XORCY blk00000173 (
.CI(sig00000298),
.LI(sig0000030e),
.O(sig000002d9)
);
MUXCY blk00000174 (
.CI(sig00000299),
.DI(sig000001a5),
.S(sig0000030f),
.O(sig0000029a)
);
XORCY blk00000175 (
.CI(sig00000299),
.LI(sig0000030f),
.O(sig000002da)
);
MUXCY blk00000176 (
.CI(sig0000029a),
.DI(sig000001a6),
.S(sig00000310),
.O(sig0000029b)
);
XORCY blk00000177 (
.CI(sig0000029a),
.LI(sig00000310),
.O(sig000002db)
);
MUXCY blk00000178 (
.CI(sig0000029b),
.DI(sig000001a7),
.S(sig00000311),
.O(sig0000029c)
);
XORCY blk00000179 (
.CI(sig0000029b),
.LI(sig00000311),
.O(sig000002dc)
);
MUXCY blk0000017a (
.CI(sig0000029c),
.DI(sig000001a8),
.S(sig00000312),
.O(sig0000029d)
);
XORCY blk0000017b (
.CI(sig0000029c),
.LI(sig00000312),
.O(sig000002dd)
);
MUXCY blk0000017c (
.CI(sig0000029d),
.DI(sig000001a9),
.S(sig00000313),
.O(sig0000029e)
);
XORCY blk0000017d (
.CI(sig0000029d),
.LI(sig00000313),
.O(sig000002de)
);
MUXCY blk0000017e (
.CI(sig0000029e),
.DI(sig000001aa),
.S(sig00000314),
.O(sig00000283)
);
XORCY blk0000017f (
.CI(sig0000029e),
.LI(sig00000314),
.O(sig000002df)
);
MUXCY blk00000180 (
.CI(sig00000283),
.DI(sig00000191),
.S(sig000002fa),
.O(sig00000284)
);
XORCY blk00000181 (
.CI(sig00000283),
.LI(sig000002fa),
.O(sig000002c4)
);
MUXCY blk00000182 (
.CI(sig00000284),
.DI(sig00000192),
.S(sig000002fb),
.O(sig00000285)
);
XORCY blk00000183 (
.CI(sig00000284),
.LI(sig000002fb),
.O(sig000002c5)
);
MUXCY blk00000184 (
.CI(sig00000285),
.DI(sig00000193),
.S(sig000002fc),
.O(sig00000286)
);
XORCY blk00000185 (
.CI(sig00000285),
.LI(sig000002fc),
.O(sig000002c6)
);
MUXCY blk00000186 (
.CI(sig00000286),
.DI(sig00000194),
.S(sig000002fd),
.O(sig00000287)
);
XORCY blk00000187 (
.CI(sig00000286),
.LI(sig000002fd),
.O(sig000002c7)
);
MUXCY blk00000188 (
.CI(sig00000287),
.DI(sig00000195),
.S(sig000002fe),
.O(sig00000288)
);
XORCY blk00000189 (
.CI(sig00000287),
.LI(sig000002fe),
.O(sig000002c8)
);
MUXCY blk0000018a (
.CI(sig00000288),
.DI(sig00000196),
.S(sig000002ff),
.O(sig00000289)
);
XORCY blk0000018b (
.CI(sig00000288),
.LI(sig000002ff),
.O(sig000002c9)
);
MUXCY blk0000018c (
.CI(sig00000289),
.DI(sig00000197),
.S(sig00000300),
.O(sig0000028a)
);
XORCY blk0000018d (
.CI(sig00000289),
.LI(sig00000300),
.O(sig000002ca)
);
MUXCY blk0000018e (
.CI(sig0000028a),
.DI(sig00000198),
.S(sig00000301),
.O(sig0000028b)
);
XORCY blk0000018f (
.CI(sig0000028a),
.LI(sig00000301),
.O(sig000002cb)
);
MUXCY blk00000190 (
.CI(sig0000028b),
.DI(sig00000199),
.S(sig00000302),
.O(sig0000028c)
);
XORCY blk00000191 (
.CI(sig0000028b),
.LI(sig00000302),
.O(sig000002cc)
);
MUXCY blk00000192 (
.CI(sig0000028c),
.DI(sig0000019a),
.S(sig00000303),
.O(sig0000028e)
);
XORCY blk00000193 (
.CI(sig0000028c),
.LI(sig00000303),
.O(sig000002cd)
);
MUXCY blk00000194 (
.CI(sig0000028e),
.DI(sig0000019c),
.S(sig00000305),
.O(sig0000028f)
);
XORCY blk00000195 (
.CI(sig0000028e),
.LI(sig00000305),
.O(sig000002cf)
);
MUXCY blk00000196 (
.CI(sig0000028f),
.DI(sig0000019d),
.S(sig00000306),
.O(sig00000290)
);
XORCY blk00000197 (
.CI(sig0000028f),
.LI(sig00000306),
.O(sig000002d0)
);
MUXCY blk00000198 (
.CI(sig00000290),
.DI(sig0000019e),
.S(sig00000307),
.O(sig00000291)
);
XORCY blk00000199 (
.CI(sig00000290),
.LI(sig00000307),
.O(sig000002d1)
);
MUXCY blk0000019a (
.CI(sig00000291),
.DI(sig0000019f),
.S(sig00000308),
.O(sig00000292)
);
XORCY blk0000019b (
.CI(sig00000291),
.LI(sig00000308),
.O(sig000002d2)
);
MUXCY blk0000019c (
.CI(sig00000292),
.DI(sig000001a0),
.S(sig00000309),
.O(sig00000293)
);
XORCY blk0000019d (
.CI(sig00000292),
.LI(sig00000309),
.O(sig000002d3)
);
MUXCY blk0000019e (
.CI(sig00000293),
.DI(sig000001a1),
.S(sig0000030a),
.O(sig00000294)
);
XORCY blk0000019f (
.CI(sig00000293),
.LI(sig0000030a),
.O(sig000002d4)
);
MUXCY blk000001a0 (
.CI(sig00000294),
.DI(sig000001a2),
.S(sig0000030b),
.O(sig00000295)
);
XORCY blk000001a1 (
.CI(sig00000294),
.LI(sig0000030b),
.O(sig000002d5)
);
MUXCY blk000001a2 (
.CI(sig00000295),
.DI(sig000001a3),
.S(sig0000030c),
.O(sig00000296)
);
XORCY blk000001a3 (
.CI(sig00000295),
.LI(sig0000030c),
.O(sig000002d6)
);
XORCY blk000001a4 (
.CI(sig00000296),
.LI(sig00000280),
.O(sig000002d7)
);
FD #(
.INIT ( 1'b0 ))
blk000001a5 (
.C(clk),
.D(sig000002c3),
.Q(sig000002a0)
);
FD #(
.INIT ( 1'b0 ))
blk000001a6 (
.C(clk),
.D(sig000002ce),
.Q(sig000002a1)
);
FD #(
.INIT ( 1'b0 ))
blk000001a7 (
.C(clk),
.D(sig000002d8),
.Q(sig000002ac)
);
FD #(
.INIT ( 1'b0 ))
blk000001a8 (
.C(clk),
.D(sig000002d9),
.Q(sig000002b6)
);
FD #(
.INIT ( 1'b0 ))
blk000001a9 (
.C(clk),
.D(sig000002da),
.Q(sig000002b7)
);
FD #(
.INIT ( 1'b0 ))
blk000001aa (
.C(clk),
.D(sig000002db),
.Q(sig000002b8)
);
FD #(
.INIT ( 1'b0 ))
blk000001ab (
.C(clk),
.D(sig000002dc),
.Q(sig000002b9)
);
FD #(
.INIT ( 1'b0 ))
blk000001ac (
.C(clk),
.D(sig000002dd),
.Q(sig000002ba)
);
FD #(
.INIT ( 1'b0 ))
blk000001ad (
.C(clk),
.D(sig000002de),
.Q(sig000002bb)
);
FD #(
.INIT ( 1'b0 ))
blk000001ae (
.C(clk),
.D(sig000002df),
.Q(sig000002bc)
);
FD #(
.INIT ( 1'b0 ))
blk000001af (
.C(clk),
.D(sig000002c4),
.Q(sig000002a2)
);
FD #(
.INIT ( 1'b0 ))
blk000001b0 (
.C(clk),
.D(sig000002c5),
.Q(sig000002a3)
);
FD #(
.INIT ( 1'b0 ))
blk000001b1 (
.C(clk),
.D(sig000002c6),
.Q(sig000002a4)
);
FD #(
.INIT ( 1'b0 ))
blk000001b2 (
.C(clk),
.D(sig000002c7),
.Q(sig000002a5)
);
FD #(
.INIT ( 1'b0 ))
blk000001b3 (
.C(clk),
.D(sig000002c8),
.Q(sig000002a6)
);
FD #(
.INIT ( 1'b0 ))
blk000001b4 (
.C(clk),
.D(sig000002c9),
.Q(sig000002a7)
);
FD #(
.INIT ( 1'b0 ))
blk000001b5 (
.C(clk),
.D(sig000002ca),
.Q(sig000002a8)
);
FD #(
.INIT ( 1'b0 ))
blk000001b6 (
.C(clk),
.D(sig000002cb),
.Q(sig000002a9)
);
FD #(
.INIT ( 1'b0 ))
blk000001b7 (
.C(clk),
.D(sig000002cc),
.Q(sig000002aa)
);
FD #(
.INIT ( 1'b0 ))
blk000001b8 (
.C(clk),
.D(sig000002cd),
.Q(sig000002ab)
);
FD #(
.INIT ( 1'b0 ))
blk000001b9 (
.C(clk),
.D(sig000002cf),
.Q(sig000002ad)
);
FD #(
.INIT ( 1'b0 ))
blk000001ba (
.C(clk),
.D(sig000002d0),
.Q(sig000002ae)
);
FD #(
.INIT ( 1'b0 ))
blk000001bb (
.C(clk),
.D(sig000002d1),
.Q(sig000002af)
);
FD #(
.INIT ( 1'b0 ))
blk000001bc (
.C(clk),
.D(sig000002d2),
.Q(sig000002b0)
);
FD #(
.INIT ( 1'b0 ))
blk000001bd (
.C(clk),
.D(sig000002d3),
.Q(sig000002b1)
);
FD #(
.INIT ( 1'b0 ))
blk000001be (
.C(clk),
.D(sig000002d4),
.Q(sig000002b2)
);
FD #(
.INIT ( 1'b0 ))
blk000001bf (
.C(clk),
.D(sig000002d5),
.Q(sig000002b3)
);
FD #(
.INIT ( 1'b0 ))
blk000001c0 (
.C(clk),
.D(sig000002d6),
.Q(sig000002b4)
);
FD #(
.INIT ( 1'b0 ))
blk000001c1 (
.C(clk),
.D(sig000002d7),
.Q(sig000002b5)
);
FD #(
.INIT ( 1'b0 ))
blk000001c2 (
.C(clk),
.D(sig00000072),
.Q(sig000001f6)
);
FD #(
.INIT ( 1'b0 ))
blk000001c3 (
.C(clk),
.D(sig00000073),
.Q(sig000001f7)
);
FD #(
.INIT ( 1'b0 ))
blk000001c4 (
.C(clk),
.D(sig00000074),
.Q(sig00000202)
);
FD #(
.INIT ( 1'b0 ))
blk000001c5 (
.C(clk),
.D(sig00000076),
.Q(sig0000020b)
);
FD #(
.INIT ( 1'b0 ))
blk000001c6 (
.C(clk),
.D(sig00000077),
.Q(sig0000020c)
);
FD #(
.INIT ( 1'b0 ))
blk000001c7 (
.C(clk),
.D(sig00000078),
.Q(sig0000020d)
);
FD #(
.INIT ( 1'b0 ))
blk000001c8 (
.C(clk),
.D(sig00000079),
.Q(sig0000020e)
);
FD #(
.INIT ( 1'b0 ))
blk000001c9 (
.C(clk),
.D(sig0000007a),
.Q(sig0000020f)
);
FD #(
.INIT ( 1'b0 ))
blk000001ca (
.C(clk),
.D(sig0000007b),
.Q(sig00000210)
);
FD #(
.INIT ( 1'b0 ))
blk000001cb (
.C(clk),
.D(sig0000007c),
.Q(sig00000211)
);
FD #(
.INIT ( 1'b0 ))
blk000001cc (
.C(clk),
.D(sig0000007d),
.Q(sig000001f8)
);
FD #(
.INIT ( 1'b0 ))
blk000001cd (
.C(clk),
.D(sig0000007e),
.Q(sig000001f9)
);
FD #(
.INIT ( 1'b0 ))
blk000001ce (
.C(clk),
.D(sig0000007f),
.Q(sig000001fa)
);
FD #(
.INIT ( 1'b0 ))
blk000001cf (
.C(clk),
.D(sig00000081),
.Q(sig000001fb)
);
FD #(
.INIT ( 1'b0 ))
blk000001d0 (
.C(clk),
.D(sig00000082),
.Q(sig000001fc)
);
FD #(
.INIT ( 1'b0 ))
blk000001d1 (
.C(clk),
.D(sig00000083),
.Q(sig000001fd)
);
FD #(
.INIT ( 1'b0 ))
blk000001d2 (
.C(clk),
.D(sig00000084),
.Q(sig000001fe)
);
FD #(
.INIT ( 1'b0 ))
blk000001d3 (
.C(clk),
.D(sig00000085),
.Q(sig000001ff)
);
FD #(
.INIT ( 1'b0 ))
blk000001d4 (
.C(clk),
.D(sig00000086),
.Q(sig00000200)
);
FD #(
.INIT ( 1'b0 ))
blk000001d5 (
.C(clk),
.D(sig00000087),
.Q(sig00000201)
);
FD #(
.INIT ( 1'b0 ))
blk000001d6 (
.C(clk),
.D(sig00000088),
.Q(sig00000203)
);
FD #(
.INIT ( 1'b0 ))
blk000001d7 (
.C(clk),
.D(sig00000089),
.Q(sig00000204)
);
FD #(
.INIT ( 1'b0 ))
blk000001d8 (
.C(clk),
.D(sig0000008a),
.Q(sig00000205)
);
FD #(
.INIT ( 1'b0 ))
blk000001d9 (
.C(clk),
.D(sig0000008c),
.Q(sig00000206)
);
FD #(
.INIT ( 1'b0 ))
blk000001da (
.C(clk),
.D(sig0000008d),
.Q(sig00000207)
);
FD #(
.INIT ( 1'b0 ))
blk000001db (
.C(clk),
.D(sig0000008e),
.Q(sig00000208)
);
FD #(
.INIT ( 1'b0 ))
blk000001dc (
.C(clk),
.D(sig0000008f),
.Q(sig00000209)
);
FD #(
.INIT ( 1'b0 ))
blk000001dd (
.C(clk),
.D(sig00000090),
.Q(sig0000020a)
);
MUXCY blk000001de (
.CI(sig000002be),
.DI(sig00000001),
.S(sig0000027f),
.O(sig000002bf)
);
MUXCY blk000001df (
.CI(sig00000357),
.DI(sig00000001),
.S(sig00000002),
.O(sig000002be)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e0 (
.C(clk),
.CE(sig00000002),
.D(sig00000359),
.Q(sig00000156)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e1 (
.C(clk),
.CE(sig00000002),
.D(sig00000357),
.Q(sig0000029f)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e2 (
.C(clk),
.CE(sig00000002),
.D(sig0000035e),
.Q(sig000002bd)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e3 (
.C(clk),
.CE(sig00000002),
.D(sig000005e0),
.Q(sig00000528)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e4 (
.C(clk),
.CE(sig00000002),
.D(sig000005ee),
.Q(sig000005a3)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e5 (
.C(clk),
.CE(sig00000002),
.D(b[63]),
.Q(sig0000046c)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e6 (
.C(clk),
.CE(sig00000002),
.D(a[63]),
.Q(sig00000454)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e7 (
.C(clk),
.CE(sig00000002),
.D(sig000005eb),
.Q(sig000005a2)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e8 (
.C(clk),
.CE(sig00000002),
.D(sig000005d7),
.Q(sig0000051b)
);
FDE #(
.INIT ( 1'b0 ))
blk000001e9 (
.C(clk),
.CE(sig00000002),
.D(sig000005d6),
.Q(sig0000051c)
);
FDE #(
.INIT ( 1'b0 ))
blk000001ea (
.C(clk),
.CE(sig00000002),
.D(sig000005ea),
.Q(sig000004da)
);
FDE #(
.INIT ( 1'b0 ))
blk000001eb (
.C(clk),
.CE(sig00000002),
.D(sig000005a5),
.Q(sig000004d5)
);
FDE #(
.INIT ( 1'b0 ))
blk000001ec (
.C(clk),
.CE(sig00000002),
.D(sig000005a8),
.Q(sig000004d3)
);
FDE #(
.INIT ( 1'b0 ))
blk000001ed (
.C(clk),
.CE(sig00000002),
.D(sig000005aa),
.Q(sig000004d6)
);
FDE #(
.INIT ( 1'b0 ))
blk000001ee (
.C(clk),
.CE(sig00000002),
.D(sig000005a7),
.Q(sig000004d2)
);
FDE #(
.INIT ( 1'b0 ))
blk000001ef (
.C(clk),
.CE(sig00000002),
.D(sig000005a4),
.Q(sig000004d0)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f0 (
.C(clk),
.CE(sig00000002),
.D(sig000005a9),
.Q(sig000004d4)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f1 (
.C(clk),
.CE(sig00000002),
.D(sig000008bb),
.Q(sig000004d1)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f2 (
.C(clk),
.CE(sig00000002),
.D(sig0000046e),
.Q(sig0000046d)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f3 (
.C(clk),
.CE(sig00000002),
.D(sig00000627),
.Q(sig0000046e)
);
FD #(
.INIT ( 1'b0 ))
blk000001f4 (
.C(clk),
.D(sig000005db),
.Q(sig000004ce)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f5 (
.C(clk),
.CE(sig00000002),
.D(sig0000049a),
.Q(sig00000486)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f6 (
.C(clk),
.CE(sig00000002),
.D(sig00000499),
.Q(sig00000485)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f7 (
.C(clk),
.CE(sig00000002),
.D(sig00000484),
.Q(sig00000470)
);
FDE #(
.INIT ( 1'b0 ))
blk000001f8 (
.C(clk),
.CE(sig00000002),
.D(sig00000483),
.Q(sig0000046f)
);
LUT2 #(
.INIT ( 4'h9 ))
blk000001f9 (
.I0(b[52]),
.I1(a[52]),
.O(sig000004f8)
);
MUXCY blk000001fa (
.CI(sig00000002),
.DI(b[52]),
.S(sig000004f8),
.O(sig000004ed)
);
XORCY blk000001fb (
.CI(sig00000002),
.LI(sig000004f8),
.O(sig000005ad)
);
LUT2 #(
.INIT ( 4'h9 ))
blk000001fc (
.I0(b[53]),
.I1(a[53]),
.O(sig000004fa)
);
MUXCY blk000001fd (
.CI(sig000004ed),
.DI(b[53]),
.S(sig000004fa),
.O(sig000004ef)
);
XORCY blk000001fe (
.CI(sig000004ed),
.LI(sig000004fa),
.O(sig000005b0)
);
LUT2 #(
.INIT ( 4'h9 ))
blk000001ff (
.I0(b[54]),
.I1(a[54]),
.O(sig000004fb)
);
MUXCY blk00000200 (
.CI(sig000004ef),
.DI(b[54]),
.S(sig000004fb),
.O(sig000004f0)
);
XORCY blk00000201 (
.CI(sig000004ef),
.LI(sig000004fb),
.O(sig000005b1)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000202 (
.I0(b[55]),
.I1(a[55]),
.O(sig000004fc)
);
MUXCY blk00000203 (
.CI(sig000004f0),
.DI(b[55]),
.S(sig000004fc),
.O(sig000004f1)
);
XORCY blk00000204 (
.CI(sig000004f0),
.LI(sig000004fc),
.O(sig000005b2)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000205 (
.I0(b[56]),
.I1(a[56]),
.O(sig000004fd)
);
MUXCY blk00000206 (
.CI(sig000004f1),
.DI(b[56]),
.S(sig000004fd),
.O(sig000004f2)
);
XORCY blk00000207 (
.CI(sig000004f1),
.LI(sig000004fd),
.O(sig000005b3)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000208 (
.I0(b[57]),
.I1(a[57]),
.O(sig000004fe)
);
MUXCY blk00000209 (
.CI(sig000004f2),
.DI(b[57]),
.S(sig000004fe),
.O(sig000004f3)
);
XORCY blk0000020a (
.CI(sig000004f2),
.LI(sig000004fe),
.O(sig000005b4)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000020b (
.I0(b[58]),
.I1(a[58]),
.O(sig000004ff)
);
MUXCY blk0000020c (
.CI(sig000004f3),
.DI(b[58]),
.S(sig000004ff),
.O(sig000004f4)
);
XORCY blk0000020d (
.CI(sig000004f3),
.LI(sig000004ff),
.O(sig000005b5)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000020e (
.I0(b[59]),
.I1(a[59]),
.O(sig00000500)
);
MUXCY blk0000020f (
.CI(sig000004f4),
.DI(b[59]),
.S(sig00000500),
.O(sig000004f5)
);
XORCY blk00000210 (
.CI(sig000004f4),
.LI(sig00000500),
.O(sig000005b6)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000211 (
.I0(b[60]),
.I1(a[60]),
.O(sig00000501)
);
MUXCY blk00000212 (
.CI(sig000004f5),
.DI(b[60]),
.S(sig00000501),
.O(sig000004f6)
);
XORCY blk00000213 (
.CI(sig000004f5),
.LI(sig00000501),
.O(sig000005b7)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000214 (
.I0(b[61]),
.I1(a[61]),
.O(sig00000502)
);
MUXCY blk00000215 (
.CI(sig000004f6),
.DI(b[61]),
.S(sig00000502),
.O(sig000004f7)
);
XORCY blk00000216 (
.CI(sig000004f6),
.LI(sig00000502),
.O(sig000005b8)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000217 (
.I0(b[62]),
.I1(a[62]),
.O(sig000004f9)
);
MUXCY blk00000218 (
.CI(sig000004f7),
.DI(b[62]),
.S(sig000004f9),
.O(sig000004ee)
);
XORCY blk00000219 (
.CI(sig000004f7),
.LI(sig000004f9),
.O(sig000005ae)
);
XORCY blk0000021a (
.CI(sig000004ee),
.LI(sig00000002),
.O(sig000005af)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000021b (
.I0(sig000004c2),
.I1(sig0000065d),
.O(sig0000050e)
);
MUXCY blk0000021c (
.CI(sig00000002),
.DI(sig000004c2),
.S(sig0000050e),
.O(sig00000503)
);
XORCY blk0000021d (
.CI(sig00000002),
.LI(sig0000050e),
.O(sig000005de)
);
LUT2 #(
.INIT ( 4'h9 ))
blk0000021e (
.I0(sig000004c3),
.I1(sig0000065e),
.O(sig00000510)
);
MUXCY blk0000021f (
.CI(sig00000503),
.DI(sig000004c3),
.S(sig00000510),
.O(sig00000505)
);
XORCY blk00000220 (
.CI(sig00000503),
.LI(sig00000510),
.O(sig000005e1)
);
MUXCY blk00000221 (
.CI(sig00000505),
.DI(sig000004c5),
.S(sig00000511),
.O(sig00000506)
);
XORCY blk00000222 (
.CI(sig00000505),
.LI(sig00000511),
.O(sig000005e2)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000223 (
.I0(sig000004c6),
.I1(sig0000065b),
.O(sig00000512)
);
MUXCY blk00000224 (
.CI(sig00000506),
.DI(sig000004c6),
.S(sig00000512),
.O(sig00000507)
);
XORCY blk00000225 (
.CI(sig00000506),
.LI(sig00000512),
.O(sig000005e3)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000226 (
.I0(sig000004c7),
.I1(sig0000062b),
.O(sig00000513)
);
MUXCY blk00000227 (
.CI(sig00000507),
.DI(sig000004c7),
.S(sig00000513),
.O(sig00000508)
);
XORCY blk00000228 (
.CI(sig00000507),
.LI(sig00000513),
.O(sig000005e4)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000229 (
.I0(sig000004c8),
.I1(sig0000062a),
.O(sig00000514)
);
MUXCY blk0000022a (
.CI(sig00000508),
.DI(sig000004c8),
.S(sig00000514),
.O(sig00000509)
);
XORCY blk0000022b (
.CI(sig00000508),
.LI(sig00000514),
.O(sig000005e5)
);
MUXCY blk0000022c (
.CI(sig00000509),
.DI(sig000004c9),
.S(sig00000515),
.O(sig0000050a)
);
XORCY blk0000022d (
.CI(sig00000509),
.LI(sig00000515),
.O(sig000005e6)
);
MUXCY blk0000022e (
.CI(sig0000050a),
.DI(sig000004ca),
.S(sig00000516),
.O(sig0000050b)
);
XORCY blk0000022f (
.CI(sig0000050a),
.LI(sig00000516),
.O(sig000005e7)
);
MUXCY blk00000230 (
.CI(sig0000050b),
.DI(sig000004cb),
.S(sig00000517),
.O(sig0000050c)
);
XORCY blk00000231 (
.CI(sig0000050b),
.LI(sig00000517),
.O(sig000005e8)
);
MUXCY blk00000232 (
.CI(sig0000050c),
.DI(sig000004cc),
.S(sig00000518),
.O(sig0000050d)
);
XORCY blk00000233 (
.CI(sig0000050c),
.LI(sig00000518),
.O(sig000005e9)
);
MUXCY blk00000234 (
.CI(sig0000050d),
.DI(sig000004c4),
.S(sig0000050f),
.O(sig00000504)
);
XORCY blk00000235 (
.CI(sig0000050d),
.LI(sig0000050f),
.O(sig000005df)
);
XORCY blk00000236 (
.CI(sig00000504),
.LI(sig00000002),
.O(sig000005e0)
);
FD #(
.INIT ( 1'b0 ))
blk00000237 (
.C(clk),
.D(sig000004ec),
.Q(sig0000049f)
);
FD #(
.INIT ( 1'b0 ))
blk00000238 (
.C(clk),
.D(sig000005ed),
.Q(sig0000049e)
);
FD #(
.INIT ( 1'b0 ))
blk00000239 (
.C(clk),
.D(sig000005ba),
.Q(sig0000049d)
);
FD #(
.INIT ( 1'b0 ))
blk0000023a (
.C(clk),
.D(sig000005b9),
.Q(sig0000049c)
);
FD #(
.INIT ( 1'b0 ))
blk0000023b (
.C(clk),
.D(sig000005ec),
.Q(sig0000049b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000023c (
.C(clk),
.CE(sig00000002),
.D(sig0000051f),
.Q(sig000004e3)
);
FDE #(
.INIT ( 1'b0 ))
blk0000023d (
.C(clk),
.CE(sig00000002),
.D(sig00000527),
.Q(sig000004eb)
);
FDE #(
.INIT ( 1'b0 ))
blk0000023e (
.C(clk),
.CE(sig00000002),
.D(sig00000526),
.Q(sig000004ea)
);
FDE #(
.INIT ( 1'b0 ))
blk0000023f (
.C(clk),
.CE(sig00000002),
.D(sig00000525),
.Q(sig000004e9)
);
FDE #(
.INIT ( 1'b0 ))
blk00000240 (
.C(clk),
.CE(sig00000002),
.D(sig00000524),
.Q(sig000004e8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000241 (
.C(clk),
.CE(sig00000002),
.D(sig00000523),
.Q(sig000004e7)
);
FDE #(
.INIT ( 1'b0 ))
blk00000242 (
.C(clk),
.CE(sig00000002),
.D(sig00000522),
.Q(sig000004e6)
);
FDE #(
.INIT ( 1'b0 ))
blk00000243 (
.C(clk),
.CE(sig00000002),
.D(sig00000521),
.Q(sig000004e5)
);
FDE #(
.INIT ( 1'b0 ))
blk00000244 (
.C(clk),
.CE(sig00000002),
.D(sig00000520),
.Q(sig000004e4)
);
FDE #(
.INIT ( 1'b0 ))
blk00000245 (
.C(clk),
.CE(sig00000002),
.D(sig0000051e),
.Q(sig000004e2)
);
FDE #(
.INIT ( 1'b0 ))
blk00000246 (
.C(clk),
.CE(sig00000002),
.D(sig0000051d),
.Q(sig000004e1)
);
FDE #(
.INIT ( 1'b0 ))
blk00000247 (
.C(clk),
.CE(sig00000002),
.D(sig000005df),
.Q(sig0000051f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000248 (
.C(clk),
.CE(sig00000002),
.D(sig000005e9),
.Q(sig00000527)
);
FDE #(
.INIT ( 1'b0 ))
blk00000249 (
.C(clk),
.CE(sig00000002),
.D(sig000005e8),
.Q(sig00000526)
);
FDE #(
.INIT ( 1'b0 ))
blk0000024a (
.C(clk),
.CE(sig00000002),
.D(sig000005e7),
.Q(sig00000525)
);
FDE #(
.INIT ( 1'b0 ))
blk0000024b (
.C(clk),
.CE(sig00000002),
.D(sig000005e6),
.Q(sig00000524)
);
FDE #(
.INIT ( 1'b0 ))
blk0000024c (
.C(clk),
.CE(sig00000002),
.D(sig000005e5),
.Q(sig00000523)
);
FDE #(
.INIT ( 1'b0 ))
blk0000024d (
.C(clk),
.CE(sig00000002),
.D(sig000005e4),
.Q(sig00000522)
);
FDE #(
.INIT ( 1'b0 ))
blk0000024e (
.C(clk),
.CE(sig00000002),
.D(sig000005e3),
.Q(sig00000521)
);
FDE #(
.INIT ( 1'b0 ))
blk0000024f (
.C(clk),
.CE(sig00000002),
.D(sig000005e2),
.Q(sig00000520)
);
FDE #(
.INIT ( 1'b0 ))
blk00000250 (
.C(clk),
.CE(sig00000002),
.D(sig000005e1),
.Q(sig0000051e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000251 (
.C(clk),
.CE(sig00000002),
.D(sig000005de),
.Q(sig0000051d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000252 (
.C(clk),
.CE(sig00000002),
.D(b[62]),
.Q(sig00000463)
);
FDE #(
.INIT ( 1'b0 ))
blk00000253 (
.C(clk),
.CE(sig00000002),
.D(b[61]),
.Q(sig0000046b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000254 (
.C(clk),
.CE(sig00000002),
.D(b[60]),
.Q(sig0000046a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000255 (
.C(clk),
.CE(sig00000002),
.D(b[59]),
.Q(sig00000469)
);
FDE #(
.INIT ( 1'b0 ))
blk00000256 (
.C(clk),
.CE(sig00000002),
.D(b[58]),
.Q(sig00000468)
);
FDE #(
.INIT ( 1'b0 ))
blk00000257 (
.C(clk),
.CE(sig00000002),
.D(b[57]),
.Q(sig00000467)
);
FDE #(
.INIT ( 1'b0 ))
blk00000258 (
.C(clk),
.CE(sig00000002),
.D(b[56]),
.Q(sig00000466)
);
FDE #(
.INIT ( 1'b0 ))
blk00000259 (
.C(clk),
.CE(sig00000002),
.D(b[55]),
.Q(sig00000465)
);
FDE #(
.INIT ( 1'b0 ))
blk0000025a (
.C(clk),
.CE(sig00000002),
.D(b[54]),
.Q(sig00000464)
);
FDE #(
.INIT ( 1'b0 ))
blk0000025b (
.C(clk),
.CE(sig00000002),
.D(b[53]),
.Q(sig00000462)
);
FDE #(
.INIT ( 1'b0 ))
blk0000025c (
.C(clk),
.CE(sig00000002),
.D(b[52]),
.Q(sig00000461)
);
FDE #(
.INIT ( 1'b0 ))
blk0000025d (
.C(clk),
.CE(sig00000002),
.D(a[62]),
.Q(sig0000044b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000025e (
.C(clk),
.CE(sig00000002),
.D(a[61]),
.Q(sig00000453)
);
FDE #(
.INIT ( 1'b0 ))
blk0000025f (
.C(clk),
.CE(sig00000002),
.D(a[60]),
.Q(sig00000452)
);
FDE #(
.INIT ( 1'b0 ))
blk00000260 (
.C(clk),
.CE(sig00000002),
.D(a[59]),
.Q(sig00000451)
);
FDE #(
.INIT ( 1'b0 ))
blk00000261 (
.C(clk),
.CE(sig00000002),
.D(a[58]),
.Q(sig00000450)
);
FDE #(
.INIT ( 1'b0 ))
blk00000262 (
.C(clk),
.CE(sig00000002),
.D(a[57]),
.Q(sig0000044f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000263 (
.C(clk),
.CE(sig00000002),
.D(a[56]),
.Q(sig0000044e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000264 (
.C(clk),
.CE(sig00000002),
.D(a[55]),
.Q(sig0000044d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000265 (
.C(clk),
.CE(sig00000002),
.D(a[54]),
.Q(sig0000044c)
);
FDE #(
.INIT ( 1'b0 ))
blk00000266 (
.C(clk),
.CE(sig00000002),
.D(a[53]),
.Q(sig0000044a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000267 (
.C(clk),
.CE(sig00000002),
.D(a[52]),
.Q(sig00000449)
);
FD #(
.INIT ( 1'b0 ))
blk00000268 (
.C(clk),
.D(sig000005af),
.Q(sig00000458)
);
FD #(
.INIT ( 1'b0 ))
blk00000269 (
.C(clk),
.D(sig000005ae),
.Q(sig00000457)
);
FD #(
.INIT ( 1'b0 ))
blk0000026a (
.C(clk),
.D(sig000005b8),
.Q(sig00000460)
);
FD #(
.INIT ( 1'b0 ))
blk0000026b (
.C(clk),
.D(sig000005b7),
.Q(sig0000045f)
);
FD #(
.INIT ( 1'b0 ))
blk0000026c (
.C(clk),
.D(sig000005b6),
.Q(sig0000045e)
);
FD #(
.INIT ( 1'b0 ))
blk0000026d (
.C(clk),
.D(sig000005b5),
.Q(sig0000045d)
);
FD #(
.INIT ( 1'b0 ))
blk0000026e (
.C(clk),
.D(sig000005b4),
.Q(sig0000045c)
);
FD #(
.INIT ( 1'b0 ))
blk0000026f (
.C(clk),
.D(sig000005b3),
.Q(sig0000045b)
);
FD #(
.INIT ( 1'b0 ))
blk00000270 (
.C(clk),
.D(sig000005b2),
.Q(sig0000045a)
);
FD #(
.INIT ( 1'b0 ))
blk00000271 (
.C(clk),
.D(sig000005b1),
.Q(sig00000459)
);
FD #(
.INIT ( 1'b0 ))
blk00000272 (
.C(clk),
.D(sig000005b0),
.Q(sig00000456)
);
FD #(
.INIT ( 1'b0 ))
blk00000273 (
.C(clk),
.D(sig000005ad),
.Q(sig00000455)
);
FD #(
.INIT ( 1'b0 ))
blk00000274 (
.C(clk),
.D(sig000005bb),
.Q(sig000004d9)
);
FD #(
.INIT ( 1'b0 ))
blk00000275 (
.C(clk),
.D(sig000005c2),
.Q(sig000004ae)
);
FD #(
.INIT ( 1'b0 ))
blk00000276 (
.C(clk),
.D(sig000005c1),
.Q(sig000004ad)
);
FD #(
.INIT ( 1'b0 ))
blk00000277 (
.C(clk),
.D(sig000005cb),
.Q(sig000004b6)
);
FD #(
.INIT ( 1'b0 ))
blk00000278 (
.C(clk),
.D(sig000005ca),
.Q(sig000004b5)
);
FD #(
.INIT ( 1'b0 ))
blk00000279 (
.C(clk),
.D(sig000005c9),
.Q(sig000004b4)
);
FD #(
.INIT ( 1'b0 ))
blk0000027a (
.C(clk),
.D(sig000005c8),
.Q(sig000004b3)
);
FD #(
.INIT ( 1'b0 ))
blk0000027b (
.C(clk),
.D(sig000005c7),
.Q(sig000004b2)
);
FD #(
.INIT ( 1'b0 ))
blk0000027c (
.C(clk),
.D(sig000005c6),
.Q(sig000004b1)
);
FD #(
.INIT ( 1'b0 ))
blk0000027d (
.C(clk),
.D(sig000005c5),
.Q(sig000004b0)
);
FD #(
.INIT ( 1'b0 ))
blk0000027e (
.C(clk),
.D(sig000005c4),
.Q(sig000004af)
);
FD #(
.INIT ( 1'b0 ))
blk0000027f (
.C(clk),
.D(sig000005c3),
.Q(sig000004ac)
);
FD #(
.INIT ( 1'b0 ))
blk00000280 (
.C(clk),
.D(sig000005c0),
.Q(sig000004ab)
);
XORCY blk00000281 (
.CI(sig000004a1),
.LI(sig00000001),
.O(sig000005c2)
);
XORCY blk00000282 (
.CI(sig000004a0),
.LI(sig000005cc),
.O(sig000005c1)
);
MUXCY blk00000283 (
.CI(sig000004a0),
.DI(sig00000001),
.S(sig000005cc),
.O(sig000004a1)
);
XORCY blk00000284 (
.CI(sig000004aa),
.LI(sig000005d5),
.O(sig000005cb)
);
MUXCY blk00000285 (
.CI(sig000004aa),
.DI(sig00000001),
.S(sig000005d5),
.O(sig000004a0)
);
XORCY blk00000286 (
.CI(sig000004a9),
.LI(sig000005d4),
.O(sig000005ca)
);
MUXCY blk00000287 (
.CI(sig000004a9),
.DI(sig00000001),
.S(sig000005d4),
.O(sig000004aa)
);
XORCY blk00000288 (
.CI(sig000004a8),
.LI(sig000005d3),
.O(sig000005c9)
);
MUXCY blk00000289 (
.CI(sig000004a8),
.DI(sig00000001),
.S(sig000005d3),
.O(sig000004a9)
);
XORCY blk0000028a (
.CI(sig000004a7),
.LI(sig000005d2),
.O(sig000005c8)
);
MUXCY blk0000028b (
.CI(sig000004a7),
.DI(sig00000001),
.S(sig000005d2),
.O(sig000004a8)
);
XORCY blk0000028c (
.CI(sig000004a6),
.LI(sig000005d1),
.O(sig000005c7)
);
MUXCY blk0000028d (
.CI(sig000004a6),
.DI(sig00000001),
.S(sig000005d1),
.O(sig000004a7)
);
XORCY blk0000028e (
.CI(sig000004a5),
.LI(sig000005d0),
.O(sig000005c6)
);
MUXCY blk0000028f (
.CI(sig000004a5),
.DI(sig00000001),
.S(sig000005d0),
.O(sig000004a6)
);
XORCY blk00000290 (
.CI(sig000004a4),
.LI(sig000005cf),
.O(sig000005c5)
);
MUXCY blk00000291 (
.CI(sig000004a4),
.DI(sig00000001),
.S(sig000005cf),
.O(sig000004a5)
);
XORCY blk00000292 (
.CI(sig000004a3),
.LI(sig000005ce),
.O(sig000005c4)
);
MUXCY blk00000293 (
.CI(sig000004a3),
.DI(sig00000001),
.S(sig000005ce),
.O(sig000004a4)
);
XORCY blk00000294 (
.CI(sig000004a2),
.LI(sig000005cd),
.O(sig000005c3)
);
MUXCY blk00000295 (
.CI(sig000004a2),
.DI(sig00000001),
.S(sig000005cd),
.O(sig000004a3)
);
XORCY blk00000296 (
.CI(sig00000001),
.LI(sig000005ab),
.O(sig000005c0)
);
MUXCY blk00000297 (
.CI(sig00000001),
.DI(sig00000002),
.S(sig000005ab),
.O(sig000004a2)
);
FDE #(
.INIT ( 1'b0 ))
blk00000298 (
.C(clk),
.CE(sig00000002),
.D(sig00000479),
.Q(sig000005a6)
);
MUXCY blk00000299 (
.CI(sig00000002),
.DI(sig00000001),
.S(sig0000047a),
.O(sig00000471)
);
MUXCY blk0000029a (
.CI(sig00000471),
.DI(sig00000001),
.S(sig0000047b),
.O(sig00000472)
);
MUXCY blk0000029b (
.CI(sig00000472),
.DI(sig00000001),
.S(sig0000047c),
.O(sig00000473)
);
MUXCY blk0000029c (
.CI(sig00000473),
.DI(sig00000001),
.S(sig0000047d),
.O(sig00000474)
);
MUXCY blk0000029d (
.CI(sig00000474),
.DI(sig00000001),
.S(sig0000047e),
.O(sig00000475)
);
MUXCY blk0000029e (
.CI(sig00000475),
.DI(sig00000001),
.S(sig0000047f),
.O(sig00000476)
);
MUXCY blk0000029f (
.CI(sig00000476),
.DI(sig00000001),
.S(sig00000480),
.O(sig00000477)
);
MUXCY blk000002a0 (
.CI(sig00000477),
.DI(sig00000001),
.S(sig00000481),
.O(sig00000478)
);
MUXCY blk000002a1 (
.CI(sig00000478),
.DI(sig00000001),
.S(sig00000482),
.O(sig00000479)
);
FDE #(
.INIT ( 1'b0 ))
blk000002a2 (
.C(clk),
.CE(sig00000002),
.D(sig0000048f),
.Q(sig000005ac)
);
MUXCY blk000002a3 (
.CI(sig00000002),
.DI(sig00000001),
.S(sig00000490),
.O(sig00000487)
);
MUXCY blk000002a4 (
.CI(sig00000487),
.DI(sig00000001),
.S(sig00000491),
.O(sig00000488)
);
MUXCY blk000002a5 (
.CI(sig00000488),
.DI(sig00000001),
.S(sig00000492),
.O(sig00000489)
);
MUXCY blk000002a6 (
.CI(sig00000489),
.DI(sig00000001),
.S(sig00000493),
.O(sig0000048a)
);
MUXCY blk000002a7 (
.CI(sig0000048a),
.DI(sig00000001),
.S(sig00000494),
.O(sig0000048b)
);
MUXCY blk000002a8 (
.CI(sig0000048b),
.DI(sig00000001),
.S(sig00000495),
.O(sig0000048c)
);
MUXCY blk000002a9 (
.CI(sig0000048c),
.DI(sig00000001),
.S(sig00000496),
.O(sig0000048d)
);
MUXCY blk000002aa (
.CI(sig0000048d),
.DI(sig00000001),
.S(sig00000497),
.O(sig0000048e)
);
MUXCY blk000002ab (
.CI(sig0000048e),
.DI(sig00000001),
.S(sig00000498),
.O(sig0000048f)
);
FDE #(
.INIT ( 1'b0 ))
blk000002ac (
.C(clk),
.CE(sig00000002),
.D(sig0000052f),
.Q(sig000005a0)
);
MUXCY blk000002ad (
.CI(sig00000001),
.DI(sig00000539),
.S(sig00000549),
.O(sig00000530)
);
MUXCY blk000002ae (
.CI(sig00000530),
.DI(sig00000540),
.S(sig00000550),
.O(sig00000531)
);
MUXCY blk000002af (
.CI(sig00000531),
.DI(sig00000541),
.S(sig00000551),
.O(sig00000532)
);
MUXCY blk000002b0 (
.CI(sig00000532),
.DI(sig00000542),
.S(sig00000552),
.O(sig00000533)
);
MUXCY blk000002b1 (
.CI(sig00000533),
.DI(sig00000543),
.S(sig00000553),
.O(sig00000534)
);
MUXCY blk000002b2 (
.CI(sig00000534),
.DI(sig00000544),
.S(sig00000554),
.O(sig00000535)
);
MUXCY blk000002b3 (
.CI(sig00000535),
.DI(sig00000545),
.S(sig00000555),
.O(sig00000536)
);
MUXCY blk000002b4 (
.CI(sig00000536),
.DI(sig00000546),
.S(sig00000556),
.O(sig00000537)
);
MUXCY blk000002b5 (
.CI(sig00000537),
.DI(sig00000547),
.S(sig00000557),
.O(sig00000538)
);
MUXCY blk000002b6 (
.CI(sig00000538),
.DI(sig00000548),
.S(sig00000558),
.O(sig00000529)
);
MUXCY blk000002b7 (
.CI(sig00000529),
.DI(sig0000053a),
.S(sig0000054a),
.O(sig0000052a)
);
MUXCY blk000002b8 (
.CI(sig0000052a),
.DI(sig0000053b),
.S(sig0000054b),
.O(sig0000052b)
);
MUXCY blk000002b9 (
.CI(sig0000052b),
.DI(sig0000053c),
.S(sig0000054c),
.O(sig0000052c)
);
MUXCY blk000002ba (
.CI(sig0000052c),
.DI(sig0000053d),
.S(sig0000054d),
.O(sig0000052d)
);
MUXCY blk000002bb (
.CI(sig0000052d),
.DI(sig0000053e),
.S(sig0000054e),
.O(sig0000052e)
);
MUXCY blk000002bc (
.CI(sig0000052e),
.DI(sig0000053f),
.S(sig0000054f),
.O(sig0000052f)
);
FDE #(
.INIT ( 1'b0 ))
blk000002bd (
.C(clk),
.CE(sig00000002),
.D(sig00000575),
.Q(sig000005a1)
);
MUXCY blk000002be (
.CI(sig00000001),
.DI(sig0000057f),
.S(sig0000058f),
.O(sig00000576)
);
MUXCY blk000002bf (
.CI(sig00000576),
.DI(sig00000586),
.S(sig00000596),
.O(sig00000577)
);
MUXCY blk000002c0 (
.CI(sig00000577),
.DI(sig00000587),
.S(sig00000597),
.O(sig00000578)
);
MUXCY blk000002c1 (
.CI(sig00000578),
.DI(sig00000588),
.S(sig00000598),
.O(sig00000579)
);
MUXCY blk000002c2 (
.CI(sig00000579),
.DI(sig00000589),
.S(sig00000599),
.O(sig0000057a)
);
MUXCY blk000002c3 (
.CI(sig0000057a),
.DI(sig0000058a),
.S(sig0000059a),
.O(sig0000057b)
);
MUXCY blk000002c4 (
.CI(sig0000057b),
.DI(sig0000058b),
.S(sig0000059b),
.O(sig0000057c)
);
MUXCY blk000002c5 (
.CI(sig0000057c),
.DI(sig0000058c),
.S(sig0000059c),
.O(sig0000057d)
);
MUXCY blk000002c6 (
.CI(sig0000057d),
.DI(sig0000058d),
.S(sig0000059d),
.O(sig0000057e)
);
MUXCY blk000002c7 (
.CI(sig0000057e),
.DI(sig0000058e),
.S(sig0000059e),
.O(sig0000056f)
);
MUXCY blk000002c8 (
.CI(sig0000056f),
.DI(sig00000580),
.S(sig00000590),
.O(sig00000570)
);
MUXCY blk000002c9 (
.CI(sig00000570),
.DI(sig00000581),
.S(sig00000591),
.O(sig00000571)
);
MUXCY blk000002ca (
.CI(sig00000571),
.DI(sig00000582),
.S(sig00000592),
.O(sig00000572)
);
MUXCY blk000002cb (
.CI(sig00000572),
.DI(sig00000583),
.S(sig00000593),
.O(sig00000573)
);
MUXCY blk000002cc (
.CI(sig00000573),
.DI(sig00000584),
.S(sig00000594),
.O(sig00000574)
);
MUXCY blk000002cd (
.CI(sig00000574),
.DI(sig00000585),
.S(sig00000595),
.O(sig00000575)
);
FDE #(
.INIT ( 1'b0 ))
blk000002ce (
.C(clk),
.CE(sig00000002),
.D(sig0000055a),
.Q(sig0000059f)
);
MUXCY blk000002cf (
.CI(sig00000002),
.DI(sig00000001),
.S(sig00000564),
.O(sig0000055b)
);
MUXCY blk000002d0 (
.CI(sig0000055b),
.DI(sig00000001),
.S(sig00000566),
.O(sig0000055c)
);
MUXCY blk000002d1 (
.CI(sig0000055c),
.DI(sig00000001),
.S(sig00000567),
.O(sig0000055d)
);
MUXCY blk000002d2 (
.CI(sig0000055d),
.DI(sig00000001),
.S(sig00000568),
.O(sig0000055e)
);
MUXCY blk000002d3 (
.CI(sig0000055e),
.DI(sig00000001),
.S(sig00000569),
.O(sig0000055f)
);
MUXCY blk000002d4 (
.CI(sig0000055f),
.DI(sig00000001),
.S(sig0000056a),
.O(sig00000560)
);
MUXCY blk000002d5 (
.CI(sig00000560),
.DI(sig00000001),
.S(sig0000056b),
.O(sig00000561)
);
MUXCY blk000002d6 (
.CI(sig00000561),
.DI(sig00000001),
.S(sig0000056c),
.O(sig00000562)
);
MUXCY blk000002d7 (
.CI(sig00000562),
.DI(sig00000001),
.S(sig0000056d),
.O(sig00000563)
);
MUXCY blk000002d8 (
.CI(sig00000563),
.DI(sig00000001),
.S(sig0000056e),
.O(sig00000559)
);
MUXCY blk000002d9 (
.CI(sig00000559),
.DI(sig00000001),
.S(sig00000565),
.O(sig0000055a)
);
FD #(
.INIT ( 1'b0 ))
blk000002da (
.C(clk),
.D(sig0000065e),
.Q(sig00000852)
);
FD #(
.INIT ( 1'b0 ))
blk000002db (
.C(clk),
.D(sig0000065d),
.Q(sig00000851)
);
FD #(
.INIT ( 1'b0 ))
blk000002dc (
.C(clk),
.D(sig000006c8),
.Q(sig00000849)
);
FD #(
.INIT ( 1'b0 ))
blk000002dd (
.C(clk),
.D(sig000006d3),
.Q(sig00000848)
);
FD #(
.INIT ( 1'b0 ))
blk000002de (
.C(clk),
.D(sig000006de),
.Q(sig00000847)
);
FD #(
.INIT ( 1'b0 ))
blk000002df (
.C(clk),
.D(sig000006e9),
.Q(sig00000846)
);
FD #(
.INIT ( 1'b0 ))
blk000002e0 (
.C(clk),
.D(sig000006f4),
.Q(sig00000845)
);
FD #(
.INIT ( 1'b0 ))
blk000002e1 (
.C(clk),
.D(sig000006fb),
.Q(sig00000844)
);
FD #(
.INIT ( 1'b0 ))
blk000002e2 (
.C(clk),
.D(sig000006fc),
.Q(sig00000843)
);
FD #(
.INIT ( 1'b0 ))
blk000002e3 (
.C(clk),
.D(sig000006fd),
.Q(sig00000842)
);
FD #(
.INIT ( 1'b0 ))
blk000002e4 (
.C(clk),
.D(sig000006fe),
.Q(sig00000841)
);
FD #(
.INIT ( 1'b0 ))
blk000002e5 (
.C(clk),
.D(sig000006c9),
.Q(sig0000083f)
);
FD #(
.INIT ( 1'b0 ))
blk000002e6 (
.C(clk),
.D(sig000006ca),
.Q(sig0000083e)
);
FD #(
.INIT ( 1'b0 ))
blk000002e7 (
.C(clk),
.D(sig000006cb),
.Q(sig0000083d)
);
FD #(
.INIT ( 1'b0 ))
blk000002e8 (
.C(clk),
.D(sig000006cc),
.Q(sig0000083c)
);
FD #(
.INIT ( 1'b0 ))
blk000002e9 (
.C(clk),
.D(sig000006cd),
.Q(sig0000083b)
);
FD #(
.INIT ( 1'b0 ))
blk000002ea (
.C(clk),
.D(sig000006ce),
.Q(sig0000083a)
);
FD #(
.INIT ( 1'b0 ))
blk000002eb (
.C(clk),
.D(sig000006cf),
.Q(sig00000839)
);
FD #(
.INIT ( 1'b0 ))
blk000002ec (
.C(clk),
.D(sig000006d0),
.Q(sig00000838)
);
FD #(
.INIT ( 1'b0 ))
blk000002ed (
.C(clk),
.D(sig000006d1),
.Q(sig00000837)
);
FD #(
.INIT ( 1'b0 ))
blk000002ee (
.C(clk),
.D(sig000006d2),
.Q(sig00000836)
);
FD #(
.INIT ( 1'b0 ))
blk000002ef (
.C(clk),
.D(sig000006d4),
.Q(sig00000850)
);
FD #(
.INIT ( 1'b0 ))
blk000002f0 (
.C(clk),
.D(sig000006d5),
.Q(sig0000084f)
);
FD #(
.INIT ( 1'b0 ))
blk000002f1 (
.C(clk),
.D(sig000006d6),
.Q(sig0000084e)
);
FD #(
.INIT ( 1'b0 ))
blk000002f2 (
.C(clk),
.D(sig000006d7),
.Q(sig0000084d)
);
FD #(
.INIT ( 1'b0 ))
blk000002f3 (
.C(clk),
.D(sig000006d8),
.Q(sig0000084c)
);
FD #(
.INIT ( 1'b0 ))
blk000002f4 (
.C(clk),
.D(sig000006d9),
.Q(sig0000084b)
);
FD #(
.INIT ( 1'b0 ))
blk000002f5 (
.C(clk),
.D(sig000006da),
.Q(sig0000084a)
);
FD #(
.INIT ( 1'b0 ))
blk000002f6 (
.C(clk),
.D(sig000006db),
.Q(sig00000840)
);
FD #(
.INIT ( 1'b0 ))
blk000002f7 (
.C(clk),
.D(sig000006dc),
.Q(sig00000835)
);
FD #(
.INIT ( 1'b0 ))
blk000002f8 (
.C(clk),
.D(sig000006dd),
.Q(sig00000834)
);
XORCY blk000002f9 (
.CI(sig0000076d),
.LI(sig00000001),
.O(NLW_blk000002f9_O_UNCONNECTED)
);
XORCY blk000002fa (
.CI(sig00000776),
.LI(sig00000001),
.O(NLW_blk000002fa_O_UNCONNECTED)
);
MUXCY blk000002fb (
.CI(sig00000776),
.DI(sig00000001),
.S(sig00000001),
.O(sig0000076d)
);
XORCY blk000002fc (
.CI(sig00000775),
.LI(sig00000001),
.O(NLW_blk000002fc_O_UNCONNECTED)
);
MUXCY blk000002fd (
.CI(sig00000775),
.DI(sig00000001),
.S(sig00000001),
.O(sig00000776)
);
XORCY blk000002fe (
.CI(sig00000774),
.LI(sig00000001),
.O(NLW_blk000002fe_O_UNCONNECTED)
);
MUXCY blk000002ff (
.CI(sig00000774),
.DI(sig00000001),
.S(sig00000001),
.O(sig00000775)
);
XORCY blk00000300 (
.CI(sig00000773),
.LI(sig00000001),
.O(NLW_blk00000300_O_UNCONNECTED)
);
MUXCY blk00000301 (
.CI(sig00000773),
.DI(sig00000001),
.S(sig00000001),
.O(sig00000774)
);
XORCY blk00000302 (
.CI(sig00000772),
.LI(sig00000001),
.O(NLW_blk00000302_O_UNCONNECTED)
);
MUXCY blk00000303 (
.CI(sig00000772),
.DI(sig00000001),
.S(sig00000001),
.O(sig00000773)
);
XORCY blk00000304 (
.CI(sig00000771),
.LI(sig00000001),
.O(NLW_blk00000304_O_UNCONNECTED)
);
MUXCY blk00000305 (
.CI(sig00000771),
.DI(sig00000001),
.S(sig00000001),
.O(sig00000772)
);
XORCY blk00000306 (
.CI(sig00000770),
.LI(sig00000001),
.O(NLW_blk00000306_O_UNCONNECTED)
);
MUXCY blk00000307 (
.CI(sig00000770),
.DI(sig00000001),
.S(sig00000001),
.O(sig00000771)
);
XORCY blk00000308 (
.CI(sig0000076f),
.LI(sig00000001),
.O(NLW_blk00000308_O_UNCONNECTED)
);
MUXCY blk00000309 (
.CI(sig0000076f),
.DI(sig00000001),
.S(sig00000001),
.O(sig00000770)
);
XORCY blk0000030a (
.CI(sig0000076e),
.LI(sig00000001),
.O(NLW_blk0000030a_O_UNCONNECTED)
);
MUXCY blk0000030b (
.CI(sig0000076e),
.DI(sig00000001),
.S(sig00000001),
.O(sig0000076f)
);
XORCY blk0000030c (
.CI(sig0000085c),
.LI(sig00000001),
.O(NLW_blk0000030c_O_UNCONNECTED)
);
MUXCY blk0000030d (
.CI(sig0000085c),
.DI(sig00000001),
.S(sig00000001),
.O(sig0000076e)
);
MUXCY blk0000030e (
.CI(sig00000002),
.DI(sig00000001),
.S(sig00000859),
.O(sig00000854)
);
MUXCY blk0000030f (
.CI(sig00000854),
.DI(sig00000002),
.S(sig0000085a),
.O(sig00000855)
);
MUXCY blk00000310 (
.CI(sig00000855),
.DI(sig00000002),
.S(sig00000853),
.O(sig00000856)
);
MUXCY blk00000311 (
.CI(sig00000856),
.DI(sig00000001),
.S(sig0000085b),
.O(sig00000857)
);
MUXCY blk00000312 (
.CI(sig00000857),
.DI(sig00000001),
.S(sig00000002),
.O(sig00000858)
);
MUXCY blk00000313 (
.CI(sig00000858),
.DI(sig00000002),
.S(sig00000002),
.O(sig00000892)
);
FD #(
.INIT ( 1'b0 ))
blk00000314 (
.C(clk),
.D(sig000007c6),
.Q(sig00000791)
);
FD #(
.INIT ( 1'b0 ))
blk00000315 (
.C(clk),
.D(sig000007d1),
.Q(sig00000792)
);
FD #(
.INIT ( 1'b0 ))
blk00000316 (
.C(clk),
.D(sig000007d8),
.Q(sig0000079d)
);
FD #(
.INIT ( 1'b0 ))
blk00000317 (
.C(clk),
.D(sig000007d9),
.Q(sig000007a4)
);
FD #(
.INIT ( 1'b0 ))
blk00000318 (
.C(clk),
.D(sig000007da),
.Q(sig000007a5)
);
FD #(
.INIT ( 1'b0 ))
blk00000319 (
.C(clk),
.D(sig000007db),
.Q(sig000007a6)
);
FD #(
.INIT ( 1'b0 ))
blk0000031a (
.C(clk),
.D(sig000007dc),
.Q(sig000007a7)
);
FD #(
.INIT ( 1'b0 ))
blk0000031b (
.C(clk),
.D(sig000007dd),
.Q(sig000007a8)
);
FD #(
.INIT ( 1'b0 ))
blk0000031c (
.C(clk),
.D(sig000007de),
.Q(sig000007a9)
);
FD #(
.INIT ( 1'b0 ))
blk0000031d (
.C(clk),
.D(sig000007df),
.Q(sig000007aa)
);
FD #(
.INIT ( 1'b0 ))
blk0000031e (
.C(clk),
.D(sig000007c7),
.Q(sig00000793)
);
FD #(
.INIT ( 1'b0 ))
blk0000031f (
.C(clk),
.D(sig000007c8),
.Q(sig00000794)
);
FD #(
.INIT ( 1'b0 ))
blk00000320 (
.C(clk),
.D(sig000007c9),
.Q(sig00000795)
);
FD #(
.INIT ( 1'b0 ))
blk00000321 (
.C(clk),
.D(sig000007ca),
.Q(sig00000796)
);
FD #(
.INIT ( 1'b0 ))
blk00000322 (
.C(clk),
.D(sig000007cb),
.Q(sig00000797)
);
FD #(
.INIT ( 1'b0 ))
blk00000323 (
.C(clk),
.D(sig000007cc),
.Q(sig00000798)
);
FD #(
.INIT ( 1'b0 ))
blk00000324 (
.C(clk),
.D(sig000007cd),
.Q(sig00000799)
);
FD #(
.INIT ( 1'b0 ))
blk00000325 (
.C(clk),
.D(sig000007ce),
.Q(sig0000079a)
);
FD #(
.INIT ( 1'b0 ))
blk00000326 (
.C(clk),
.D(sig000007cf),
.Q(sig0000079b)
);
FD #(
.INIT ( 1'b0 ))
blk00000327 (
.C(clk),
.D(sig000007d0),
.Q(sig0000079c)
);
FD #(
.INIT ( 1'b0 ))
blk00000328 (
.C(clk),
.D(sig000007d2),
.Q(sig0000079e)
);
FD #(
.INIT ( 1'b0 ))
blk00000329 (
.C(clk),
.D(sig000007d3),
.Q(sig0000079f)
);
FD #(
.INIT ( 1'b0 ))
blk0000032a (
.C(clk),
.D(sig000007d4),
.Q(sig000007a0)
);
FD #(
.INIT ( 1'b0 ))
blk0000032b (
.C(clk),
.D(sig000007d5),
.Q(sig000007a1)
);
FD #(
.INIT ( 1'b0 ))
blk0000032c (
.C(clk),
.D(sig000007d6),
.Q(sig000007a2)
);
FD #(
.INIT ( 1'b0 ))
blk0000032d (
.C(clk),
.D(sig000007d7),
.Q(sig000007a3)
);
FD #(
.INIT ( 1'b0 ))
blk0000032e (
.C(clk),
.D(sig00000791),
.Q(sig00000777)
);
FD #(
.INIT ( 1'b0 ))
blk0000032f (
.C(clk),
.D(sig00000792),
.Q(sig00000778)
);
FD #(
.INIT ( 1'b0 ))
blk00000330 (
.C(clk),
.D(sig0000079d),
.Q(sig00000783)
);
FD #(
.INIT ( 1'b0 ))
blk00000331 (
.C(clk),
.D(sig000007a4),
.Q(sig0000078a)
);
FD #(
.INIT ( 1'b0 ))
blk00000332 (
.C(clk),
.D(sig000007a5),
.Q(sig0000078b)
);
FD #(
.INIT ( 1'b0 ))
blk00000333 (
.C(clk),
.D(sig000007a6),
.Q(sig0000078c)
);
FD #(
.INIT ( 1'b0 ))
blk00000334 (
.C(clk),
.D(sig000007a7),
.Q(sig0000078d)
);
FD #(
.INIT ( 1'b0 ))
blk00000335 (
.C(clk),
.D(sig000007a8),
.Q(sig0000078e)
);
FD #(
.INIT ( 1'b0 ))
blk00000336 (
.C(clk),
.D(sig000007a9),
.Q(sig0000078f)
);
FD #(
.INIT ( 1'b0 ))
blk00000337 (
.C(clk),
.D(sig000007aa),
.Q(sig00000790)
);
FD #(
.INIT ( 1'b0 ))
blk00000338 (
.C(clk),
.D(sig00000793),
.Q(sig00000779)
);
FD #(
.INIT ( 1'b0 ))
blk00000339 (
.C(clk),
.D(sig00000794),
.Q(sig0000077a)
);
FD #(
.INIT ( 1'b0 ))
blk0000033a (
.C(clk),
.D(sig00000795),
.Q(sig0000077b)
);
FD #(
.INIT ( 1'b0 ))
blk0000033b (
.C(clk),
.D(sig00000796),
.Q(sig0000077c)
);
FD #(
.INIT ( 1'b0 ))
blk0000033c (
.C(clk),
.D(sig00000797),
.Q(sig0000077d)
);
FD #(
.INIT ( 1'b0 ))
blk0000033d (
.C(clk),
.D(sig00000798),
.Q(sig0000077e)
);
FD #(
.INIT ( 1'b0 ))
blk0000033e (
.C(clk),
.D(sig00000799),
.Q(sig0000077f)
);
FD #(
.INIT ( 1'b0 ))
blk0000033f (
.C(clk),
.D(sig0000079a),
.Q(sig00000780)
);
FD #(
.INIT ( 1'b0 ))
blk00000340 (
.C(clk),
.D(sig0000079b),
.Q(sig00000781)
);
FD #(
.INIT ( 1'b0 ))
blk00000341 (
.C(clk),
.D(sig0000079c),
.Q(sig00000782)
);
FD #(
.INIT ( 1'b0 ))
blk00000342 (
.C(clk),
.D(sig0000079e),
.Q(sig00000784)
);
FD #(
.INIT ( 1'b0 ))
blk00000343 (
.C(clk),
.D(sig0000079f),
.Q(sig00000785)
);
FD #(
.INIT ( 1'b0 ))
blk00000344 (
.C(clk),
.D(sig000007a0),
.Q(sig00000786)
);
FD #(
.INIT ( 1'b0 ))
blk00000345 (
.C(clk),
.D(sig000007a1),
.Q(sig00000787)
);
FD #(
.INIT ( 1'b0 ))
blk00000346 (
.C(clk),
.D(sig000007a2),
.Q(sig00000788)
);
FD #(
.INIT ( 1'b0 ))
blk00000347 (
.C(clk),
.D(sig000007a3),
.Q(sig00000789)
);
XORCY blk00000348 (
.CI(sig000007bc),
.LI(sig00000001),
.O(sig000007c5)
);
XORCY blk00000349 (
.CI(sig000007bb),
.LI(sig0000086f),
.O(sig000007d7)
);
MUXCY blk0000034a (
.CI(sig000007bb),
.DI(sig00000001),
.S(sig0000086f),
.O(sig000007bc)
);
XORCY blk0000034b (
.CI(sig000007ba),
.LI(sig0000086e),
.O(sig000007d6)
);
MUXCY blk0000034c (
.CI(sig000007ba),
.DI(sig00000001),
.S(sig0000086e),
.O(sig000007bb)
);
XORCY blk0000034d (
.CI(sig000007b9),
.LI(sig0000086d),
.O(sig000007d5)
);
MUXCY blk0000034e (
.CI(sig000007b9),
.DI(sig00000001),
.S(sig0000086d),
.O(sig000007ba)
);
XORCY blk0000034f (
.CI(sig000007b8),
.LI(sig0000086c),
.O(sig000007d4)
);
MUXCY blk00000350 (
.CI(sig000007b8),
.DI(sig00000001),
.S(sig0000086c),
.O(sig000007b9)
);
XORCY blk00000351 (
.CI(sig000007b7),
.LI(sig0000086b),
.O(sig000007d3)
);
MUXCY blk00000352 (
.CI(sig000007b7),
.DI(sig00000001),
.S(sig0000086b),
.O(sig000007b8)
);
XORCY blk00000353 (
.CI(sig000007b6),
.LI(sig0000086a),
.O(sig000007d2)
);
MUXCY blk00000354 (
.CI(sig000007b6),
.DI(sig00000001),
.S(sig0000086a),
.O(sig000007b7)
);
XORCY blk00000355 (
.CI(sig000007b4),
.LI(sig00000868),
.O(sig000007d0)
);
MUXCY blk00000356 (
.CI(sig000007b4),
.DI(sig00000001),
.S(sig00000868),
.O(sig000007b6)
);
XORCY blk00000357 (
.CI(sig000007b3),
.LI(sig00000867),
.O(sig000007cf)
);
MUXCY blk00000358 (
.CI(sig000007b3),
.DI(sig00000001),
.S(sig00000867),
.O(sig000007b4)
);
XORCY blk00000359 (
.CI(sig000007b2),
.LI(sig00000866),
.O(sig000007ce)
);
MUXCY blk0000035a (
.CI(sig000007b2),
.DI(sig00000001),
.S(sig00000866),
.O(sig000007b3)
);
XORCY blk0000035b (
.CI(sig000007b1),
.LI(sig00000865),
.O(sig000007cd)
);
MUXCY blk0000035c (
.CI(sig000007b1),
.DI(sig00000001),
.S(sig00000865),
.O(sig000007b2)
);
XORCY blk0000035d (
.CI(sig000007b0),
.LI(sig00000864),
.O(sig000007cc)
);
MUXCY blk0000035e (
.CI(sig000007b0),
.DI(sig00000001),
.S(sig00000864),
.O(sig000007b1)
);
XORCY blk0000035f (
.CI(sig000007af),
.LI(sig00000863),
.O(sig000007cb)
);
MUXCY blk00000360 (
.CI(sig000007af),
.DI(sig00000001),
.S(sig00000863),
.O(sig000007b0)
);
XORCY blk00000361 (
.CI(sig000007ae),
.LI(sig00000862),
.O(sig000007ca)
);
MUXCY blk00000362 (
.CI(sig000007ae),
.DI(sig00000001),
.S(sig00000862),
.O(sig000007af)
);
XORCY blk00000363 (
.CI(sig000007ad),
.LI(sig00000861),
.O(sig000007c9)
);
MUXCY blk00000364 (
.CI(sig000007ad),
.DI(sig00000001),
.S(sig00000861),
.O(sig000007ae)
);
XORCY blk00000365 (
.CI(sig000007ac),
.LI(sig00000860),
.O(sig000007c8)
);
MUXCY blk00000366 (
.CI(sig000007ac),
.DI(sig00000001),
.S(sig00000860),
.O(sig000007ad)
);
XORCY blk00000367 (
.CI(sig000007ab),
.LI(sig0000085f),
.O(sig000007c7)
);
MUXCY blk00000368 (
.CI(sig000007ab),
.DI(sig00000001),
.S(sig0000085f),
.O(sig000007ac)
);
XORCY blk00000369 (
.CI(sig000007c4),
.LI(sig00000877),
.O(sig000007df)
);
MUXCY blk0000036a (
.CI(sig000007c4),
.DI(sig00000001),
.S(sig00000877),
.O(sig000007ab)
);
XORCY blk0000036b (
.CI(sig000007c3),
.LI(sig00000876),
.O(sig000007de)
);
MUXCY blk0000036c (
.CI(sig000007c3),
.DI(sig00000001),
.S(sig00000876),
.O(sig000007c4)
);
XORCY blk0000036d (
.CI(sig000007c2),
.LI(sig00000875),
.O(sig000007dd)
);
MUXCY blk0000036e (
.CI(sig000007c2),
.DI(sig00000001),
.S(sig00000875),
.O(sig000007c3)
);
XORCY blk0000036f (
.CI(sig000007c1),
.LI(sig00000874),
.O(sig000007dc)
);
MUXCY blk00000370 (
.CI(sig000007c1),
.DI(sig00000001),
.S(sig00000874),
.O(sig000007c2)
);
XORCY blk00000371 (
.CI(sig000007c0),
.LI(sig00000873),
.O(sig000007db)
);
MUXCY blk00000372 (
.CI(sig000007c0),
.DI(sig00000001),
.S(sig00000873),
.O(sig000007c1)
);
XORCY blk00000373 (
.CI(sig000007bf),
.LI(sig00000872),
.O(sig000007da)
);
MUXCY blk00000374 (
.CI(sig000007bf),
.DI(sig00000001),
.S(sig00000872),
.O(sig000007c0)
);
XORCY blk00000375 (
.CI(sig000007be),
.LI(sig00000871),
.O(sig000007d9)
);
MUXCY blk00000376 (
.CI(sig000007be),
.DI(sig00000001),
.S(sig00000871),
.O(sig000007bf)
);
XORCY blk00000377 (
.CI(sig000007bd),
.LI(sig00000870),
.O(sig000007d8)
);
MUXCY blk00000378 (
.CI(sig000007bd),
.DI(sig00000001),
.S(sig00000870),
.O(sig000007be)
);
XORCY blk00000379 (
.CI(sig000007b5),
.LI(sig00000869),
.O(sig000007d1)
);
MUXCY blk0000037a (
.CI(sig000007b5),
.DI(sig00000001),
.S(sig00000869),
.O(sig000007bd)
);
XORCY blk0000037b (
.CI(sig00000892),
.LI(sig0000085e),
.O(sig000007c6)
);
MUXCY blk0000037c (
.CI(sig00000892),
.DI(sig00000001),
.S(sig0000085e),
.O(sig000007b5)
);
FDE #(
.INIT ( 1'b0 ))
blk0000037d (
.C(clk),
.CE(sig00000002),
.D(sig000007c5),
.Q(sig0000085d)
);
FD #(
.INIT ( 1'b0 ))
blk0000037e (
.C(clk),
.D(sig00000819),
.Q(sig000007e0)
);
FD #(
.INIT ( 1'b0 ))
blk0000037f (
.C(clk),
.D(sig00000824),
.Q(sig000007e1)
);
FD #(
.INIT ( 1'b0 ))
blk00000380 (
.C(clk),
.D(sig0000082c),
.Q(sig000007ec)
);
FD #(
.INIT ( 1'b0 ))
blk00000381 (
.C(clk),
.D(sig0000082d),
.Q(sig000007f4)
);
FD #(
.INIT ( 1'b0 ))
blk00000382 (
.C(clk),
.D(sig0000082e),
.Q(sig000007f5)
);
FD #(
.INIT ( 1'b0 ))
blk00000383 (
.C(clk),
.D(sig0000082f),
.Q(sig000007f6)
);
FD #(
.INIT ( 1'b0 ))
blk00000384 (
.C(clk),
.D(sig00000830),
.Q(sig000007f7)
);
FD #(
.INIT ( 1'b0 ))
blk00000385 (
.C(clk),
.D(sig00000831),
.Q(sig000007f8)
);
FD #(
.INIT ( 1'b0 ))
blk00000386 (
.C(clk),
.D(sig00000832),
.Q(sig000007f9)
);
FD #(
.INIT ( 1'b0 ))
blk00000387 (
.C(clk),
.D(sig00000833),
.Q(sig000007fa)
);
FD #(
.INIT ( 1'b0 ))
blk00000388 (
.C(clk),
.D(sig0000081a),
.Q(sig000007e2)
);
FD #(
.INIT ( 1'b0 ))
blk00000389 (
.C(clk),
.D(sig0000081b),
.Q(sig000007e3)
);
FD #(
.INIT ( 1'b0 ))
blk0000038a (
.C(clk),
.D(sig0000081c),
.Q(sig000007e4)
);
FD #(
.INIT ( 1'b0 ))
blk0000038b (
.C(clk),
.D(sig0000081d),
.Q(sig000007e5)
);
FD #(
.INIT ( 1'b0 ))
blk0000038c (
.C(clk),
.D(sig0000081e),
.Q(sig000007e6)
);
FD #(
.INIT ( 1'b0 ))
blk0000038d (
.C(clk),
.D(sig0000081f),
.Q(sig000007e7)
);
FD #(
.INIT ( 1'b0 ))
blk0000038e (
.C(clk),
.D(sig00000820),
.Q(sig000007e8)
);
FD #(
.INIT ( 1'b0 ))
blk0000038f (
.C(clk),
.D(sig00000821),
.Q(sig000007e9)
);
FD #(
.INIT ( 1'b0 ))
blk00000390 (
.C(clk),
.D(sig00000822),
.Q(sig000007ea)
);
FD #(
.INIT ( 1'b0 ))
blk00000391 (
.C(clk),
.D(sig00000823),
.Q(sig000007eb)
);
FD #(
.INIT ( 1'b0 ))
blk00000392 (
.C(clk),
.D(sig00000825),
.Q(sig000007ed)
);
FD #(
.INIT ( 1'b0 ))
blk00000393 (
.C(clk),
.D(sig00000826),
.Q(sig000007ee)
);
FD #(
.INIT ( 1'b0 ))
blk00000394 (
.C(clk),
.D(sig00000827),
.Q(sig000007ef)
);
FD #(
.INIT ( 1'b0 ))
blk00000395 (
.C(clk),
.D(sig00000828),
.Q(sig000007f0)
);
FD #(
.INIT ( 1'b0 ))
blk00000396 (
.C(clk),
.D(sig00000829),
.Q(sig000007f1)
);
FD #(
.INIT ( 1'b0 ))
blk00000397 (
.C(clk),
.D(sig0000082a),
.Q(sig000007f2)
);
FD #(
.INIT ( 1'b0 ))
blk00000398 (
.C(clk),
.D(sig0000082b),
.Q(sig000007f3)
);
XORCY blk00000399 (
.CI(sig0000080f),
.LI(sig00000001),
.O(sig00000818)
);
XORCY blk0000039a (
.CI(sig0000080e),
.LI(sig00000002),
.O(sig0000082b)
);
MUXCY blk0000039b (
.CI(sig0000080e),
.DI(sig00000002),
.S(sig00000002),
.O(sig0000080f)
);
XORCY blk0000039c (
.CI(sig0000080d),
.LI(sig00000889),
.O(sig0000082a)
);
MUXCY blk0000039d (
.CI(sig0000080d),
.DI(sig00000001),
.S(sig00000889),
.O(sig0000080e)
);
XORCY blk0000039e (
.CI(sig0000080c),
.LI(sig00000888),
.O(sig00000829)
);
MUXCY blk0000039f (
.CI(sig0000080c),
.DI(sig00000001),
.S(sig00000888),
.O(sig0000080d)
);
XORCY blk000003a0 (
.CI(sig0000080b),
.LI(sig00000887),
.O(sig00000828)
);
MUXCY blk000003a1 (
.CI(sig0000080b),
.DI(sig00000001),
.S(sig00000887),
.O(sig0000080c)
);
XORCY blk000003a2 (
.CI(sig0000080a),
.LI(sig00000886),
.O(sig00000827)
);
MUXCY blk000003a3 (
.CI(sig0000080a),
.DI(sig00000001),
.S(sig00000886),
.O(sig0000080b)
);
XORCY blk000003a4 (
.CI(sig00000809),
.LI(sig00000885),
.O(sig00000826)
);
MUXCY blk000003a5 (
.CI(sig00000809),
.DI(sig00000001),
.S(sig00000885),
.O(sig0000080a)
);
XORCY blk000003a6 (
.CI(sig00000808),
.LI(sig00000884),
.O(sig00000825)
);
MUXCY blk000003a7 (
.CI(sig00000808),
.DI(sig00000001),
.S(sig00000884),
.O(sig00000809)
);
XORCY blk000003a8 (
.CI(sig00000806),
.LI(sig00000882),
.O(sig00000823)
);
MUXCY blk000003a9 (
.CI(sig00000806),
.DI(sig00000001),
.S(sig00000882),
.O(sig00000808)
);
XORCY blk000003aa (
.CI(sig00000805),
.LI(sig00000881),
.O(sig00000822)
);
MUXCY blk000003ab (
.CI(sig00000805),
.DI(sig00000001),
.S(sig00000881),
.O(sig00000806)
);
XORCY blk000003ac (
.CI(sig00000804),
.LI(sig00000880),
.O(sig00000821)
);
MUXCY blk000003ad (
.CI(sig00000804),
.DI(sig00000001),
.S(sig00000880),
.O(sig00000805)
);
XORCY blk000003ae (
.CI(sig00000803),
.LI(sig0000087f),
.O(sig00000820)
);
MUXCY blk000003af (
.CI(sig00000803),
.DI(sig00000001),
.S(sig0000087f),
.O(sig00000804)
);
XORCY blk000003b0 (
.CI(sig00000802),
.LI(sig0000087e),
.O(sig0000081f)
);
MUXCY blk000003b1 (
.CI(sig00000802),
.DI(sig00000001),
.S(sig0000087e),
.O(sig00000803)
);
XORCY blk000003b2 (
.CI(sig00000801),
.LI(sig0000087d),
.O(sig0000081e)
);
MUXCY blk000003b3 (
.CI(sig00000801),
.DI(sig00000001),
.S(sig0000087d),
.O(sig00000802)
);
XORCY blk000003b4 (
.CI(sig00000800),
.LI(sig0000087c),
.O(sig0000081d)
);
MUXCY blk000003b5 (
.CI(sig00000800),
.DI(sig00000001),
.S(sig0000087c),
.O(sig00000801)
);
XORCY blk000003b6 (
.CI(sig000007ff),
.LI(sig0000087b),
.O(sig0000081c)
);
MUXCY blk000003b7 (
.CI(sig000007ff),
.DI(sig00000001),
.S(sig0000087b),
.O(sig00000800)
);
XORCY blk000003b8 (
.CI(sig000007fe),
.LI(sig0000087a),
.O(sig0000081b)
);
MUXCY blk000003b9 (
.CI(sig000007fe),
.DI(sig00000001),
.S(sig0000087a),
.O(sig000007ff)
);
XORCY blk000003ba (
.CI(sig000007fd),
.LI(sig00000879),
.O(sig0000081a)
);
MUXCY blk000003bb (
.CI(sig000007fd),
.DI(sig00000001),
.S(sig00000879),
.O(sig000007fe)
);
XORCY blk000003bc (
.CI(sig00000817),
.LI(sig00000891),
.O(sig00000833)
);
MUXCY blk000003bd (
.CI(sig00000817),
.DI(sig00000001),
.S(sig00000891),
.O(sig000007fd)
);
XORCY blk000003be (
.CI(sig00000816),
.LI(sig00000890),
.O(sig00000832)
);
MUXCY blk000003bf (
.CI(sig00000816),
.DI(sig00000001),
.S(sig00000890),
.O(sig00000817)
);
XORCY blk000003c0 (
.CI(sig00000815),
.LI(sig0000088f),
.O(sig00000831)
);
MUXCY blk000003c1 (
.CI(sig00000815),
.DI(sig00000001),
.S(sig0000088f),
.O(sig00000816)
);
XORCY blk000003c2 (
.CI(sig00000814),
.LI(sig0000088e),
.O(sig00000830)
);
MUXCY blk000003c3 (
.CI(sig00000814),
.DI(sig00000001),
.S(sig0000088e),
.O(sig00000815)
);
XORCY blk000003c4 (
.CI(sig00000813),
.LI(sig0000088d),
.O(sig0000082f)
);
MUXCY blk000003c5 (
.CI(sig00000813),
.DI(sig00000001),
.S(sig0000088d),
.O(sig00000814)
);
XORCY blk000003c6 (
.CI(sig00000812),
.LI(sig0000088c),
.O(sig0000082e)
);
MUXCY blk000003c7 (
.CI(sig00000812),
.DI(sig00000001),
.S(sig0000088c),
.O(sig00000813)
);
XORCY blk000003c8 (
.CI(sig00000811),
.LI(sig0000088b),
.O(sig0000082d)
);
MUXCY blk000003c9 (
.CI(sig00000811),
.DI(sig00000001),
.S(sig0000088b),
.O(sig00000812)
);
XORCY blk000003ca (
.CI(sig00000810),
.LI(sig0000088a),
.O(sig0000082c)
);
MUXCY blk000003cb (
.CI(sig00000810),
.DI(sig00000001),
.S(sig0000088a),
.O(sig00000811)
);
XORCY blk000003cc (
.CI(sig00000807),
.LI(sig00000883),
.O(sig00000824)
);
MUXCY blk000003cd (
.CI(sig00000807),
.DI(sig00000001),
.S(sig00000883),
.O(sig00000810)
);
XORCY blk000003ce (
.CI(sig000007fc),
.LI(sig00000878),
.O(sig00000819)
);
MUXCY blk000003cf (
.CI(sig000007fc),
.DI(sig00000001),
.S(sig00000878),
.O(sig00000807)
);
MUXCY blk000003d0 (
.CI(sig00000002),
.DI(sig00000001),
.S(sig000007fb),
.O(sig000007fc)
);
FDE #(
.INIT ( 1'b0 ))
blk000003d1 (
.C(clk),
.CE(sig00000002),
.D(sig00000818),
.Q(sig0000085c)
);
FDE #(
.INIT ( 1'b0 ))
blk000003d2 (
.C(clk),
.CE(sig00000002),
.D(sig00000675),
.Q(sig00000627)
);
FDE #(
.INIT ( 1'b0 ))
blk000003d3 (
.C(clk),
.CE(sig00000002),
.D(sig00000895),
.Q(sig0000065c)
);
FDE #(
.INIT ( 1'b0 ))
blk000003d4 (
.C(clk),
.CE(sig00000002),
.D(sig0000064d),
.Q(sig0000065b)
);
FDE #(
.INIT ( 1'b0 ))
blk000003d5 (
.C(clk),
.CE(sig00000002),
.D(sig00000663),
.Q(sig0000065d)
);
FDE #(
.INIT ( 1'b0 ))
blk000003d6 (
.C(clk),
.CE(sig00000002),
.D(sig00000664),
.Q(sig0000065e)
);
MUXF7 blk000003d7 (
.I0(sig00000660),
.I1(sig00000662),
.S(sig0000064d),
.O(sig00000664)
);
MUXF7 blk000003d8 (
.I0(sig0000065f),
.I1(sig00000661),
.S(sig0000064d),
.O(sig00000663)
);
MUXF7 blk000003d9 (
.I0(sig00000665),
.I1(sig00000666),
.S(sig0000064d),
.O(NLW_blk000003d9_O_UNCONNECTED)
);
MUXCY blk000003da (
.CI(sig0000066d),
.DI(sig00000001),
.S(sig0000068e),
.O(sig0000066e)
);
MUXCY blk000003db (
.CI(sig0000066c),
.DI(sig00000001),
.S(sig0000068d),
.O(sig0000066d)
);
MUXCY blk000003dc (
.CI(sig0000066b),
.DI(sig00000001),
.S(sig0000068c),
.O(sig0000066c)
);
MUXCY blk000003dd (
.CI(sig0000066a),
.DI(sig00000001),
.S(sig0000068b),
.O(sig0000066b)
);
MUXCY blk000003de (
.CI(sig00000669),
.DI(sig00000001),
.S(sig0000068a),
.O(sig0000066a)
);
MUXCY blk000003df (
.CI(sig00000668),
.DI(sig00000001),
.S(sig00000689),
.O(sig00000669)
);
MUXCY blk000003e0 (
.CI(sig00000667),
.DI(sig00000001),
.S(sig00000688),
.O(sig00000668)
);
MUXCY blk000003e1 (
.CI(sig00000002),
.DI(sig00000001),
.S(sig00000683),
.O(sig00000667)
);
FDE #(
.INIT ( 1'b0 ))
blk000003e2 (
.C(clk),
.CE(sig00000002),
.D(sig0000066e),
.Q(sig00000897)
);
FDE #(
.INIT ( 1'b0 ))
blk000003e3 (
.C(clk),
.CE(sig00000002),
.D(sig0000066d),
.Q(sig00000680)
);
FDE #(
.INIT ( 1'b0 ))
blk000003e4 (
.C(clk),
.CE(sig00000002),
.D(sig0000066c),
.Q(sig0000067f)
);
FDE #(
.INIT ( 1'b0 ))
blk000003e5 (
.C(clk),
.CE(sig00000002),
.D(sig0000066b),
.Q(sig0000067e)
);
FDE #(
.INIT ( 1'b0 ))
blk000003e6 (
.C(clk),
.CE(sig00000002),
.D(sig0000066a),
.Q(sig0000067d)
);
FDE #(
.INIT ( 1'b0 ))
blk000003e7 (
.C(clk),
.CE(sig00000002),
.D(sig00000669),
.Q(sig0000067c)
);
FDE #(
.INIT ( 1'b0 ))
blk000003e8 (
.C(clk),
.CE(sig00000002),
.D(sig00000668),
.Q(sig0000067b)
);
FDE #(
.INIT ( 1'b0 ))
blk000003e9 (
.C(clk),
.CE(sig00000002),
.D(sig00000667),
.Q(sig00000676)
);
MUXCY blk000003ea (
.CI(sig00000673),
.DI(sig00000001),
.S(sig00000687),
.O(sig00000674)
);
MUXCY blk000003eb (
.CI(sig00000672),
.DI(sig00000001),
.S(sig00000686),
.O(sig00000673)
);
MUXCY blk000003ec (
.CI(sig00000671),
.DI(sig00000001),
.S(sig00000685),
.O(sig00000672)
);
MUXCY blk000003ed (
.CI(sig00000670),
.DI(sig00000001),
.S(sig00000684),
.O(sig00000671)
);
MUXCY blk000003ee (
.CI(sig0000066f),
.DI(sig00000001),
.S(sig00000690),
.O(sig00000670)
);
MUXCY blk000003ef (
.CI(sig00000002),
.DI(sig00000001),
.S(sig0000068f),
.O(sig0000066f)
);
FDE #(
.INIT ( 1'b0 ))
blk000003f0 (
.C(clk),
.CE(sig00000002),
.D(sig00000674),
.Q(sig0000067a)
);
FDE #(
.INIT ( 1'b0 ))
blk000003f1 (
.C(clk),
.CE(sig00000002),
.D(sig00000673),
.Q(sig00000679)
);
FDE #(
.INIT ( 1'b0 ))
blk000003f2 (
.C(clk),
.CE(sig00000002),
.D(sig00000672),
.Q(sig00000678)
);
FDE #(
.INIT ( 1'b0 ))
blk000003f3 (
.C(clk),
.CE(sig00000002),
.D(sig00000671),
.Q(sig00000677)
);
FDE #(
.INIT ( 1'b0 ))
blk000003f4 (
.C(clk),
.CE(sig00000002),
.D(sig00000670),
.Q(sig00000682)
);
FDE #(
.INIT ( 1'b0 ))
blk000003f5 (
.C(clk),
.CE(sig00000002),
.D(sig0000066f),
.Q(sig00000681)
);
FD #(
.INIT ( 1'b0 ))
blk000003f6 (
.C(clk),
.D(sig00000644),
.Q(sig0000062c)
);
FD #(
.INIT ( 1'b0 ))
blk000003f7 (
.C(clk),
.D(sig00000645),
.Q(sig0000062d)
);
FD #(
.INIT ( 1'b0 ))
blk000003f8 (
.C(clk),
.D(sig00000646),
.Q(sig0000062e)
);
FD #(
.INIT ( 1'b0 ))
blk000003f9 (
.C(clk),
.D(sig00000647),
.Q(sig0000062f)
);
FD #(
.INIT ( 1'b0 ))
blk000003fa (
.C(clk),
.D(sig00000648),
.Q(sig00000630)
);
FD #(
.INIT ( 1'b0 ))
blk000003fb (
.C(clk),
.D(sig00000649),
.Q(sig00000631)
);
FD #(
.INIT ( 1'b0 ))
blk000003fc (
.C(clk),
.D(sig0000064a),
.Q(sig00000632)
);
FD #(
.INIT ( 1'b0 ))
blk000003fd (
.C(clk),
.D(sig0000064b),
.Q(sig00000633)
);
MUXF7 blk000003fe (
.I0(sig0000063b),
.I1(sig00000643),
.S(sig00000897),
.O(sig0000064b)
);
MUXF7 blk000003ff (
.I0(sig0000063a),
.I1(sig00000642),
.S(sig00000897),
.O(sig0000064a)
);
MUXF7 blk00000400 (
.I0(sig00000639),
.I1(sig00000641),
.S(sig00000897),
.O(sig00000649)
);
MUXF7 blk00000401 (
.I0(sig00000638),
.I1(sig00000640),
.S(sig00000897),
.O(sig00000648)
);
MUXF7 blk00000402 (
.I0(sig00000637),
.I1(sig0000063f),
.S(sig00000897),
.O(sig00000647)
);
MUXF7 blk00000403 (
.I0(sig00000636),
.I1(sig0000063e),
.S(sig00000897),
.O(sig00000646)
);
MUXF7 blk00000404 (
.I0(sig00000635),
.I1(sig0000063d),
.S(sig00000897),
.O(sig00000645)
);
MUXF7 blk00000405 (
.I0(sig00000634),
.I1(sig0000063c),
.S(sig00000897),
.O(sig00000644)
);
MUXF7 blk00000406 (
.I0(sig00000653),
.I1(sig00000001),
.S(sig00000897),
.O(sig0000065a)
);
MUXF7 blk00000407 (
.I0(sig00000652),
.I1(sig00000656),
.S(sig00000897),
.O(sig00000659)
);
MUXF7 blk00000408 (
.I0(sig00000651),
.I1(sig00000655),
.S(sig00000897),
.O(sig00000658)
);
MUXF7 blk00000409 (
.I0(sig00000650),
.I1(sig00000654),
.S(sig00000897),
.O(sig00000657)
);
FD #(
.INIT ( 1'b0 ))
blk0000040a (
.C(clk),
.D(sig00000657),
.Q(sig0000064c)
);
FD #(
.INIT ( 1'b0 ))
blk0000040b (
.C(clk),
.D(sig00000658),
.Q(sig0000064d)
);
FD #(
.INIT ( 1'b0 ))
blk0000040c (
.C(clk),
.D(sig00000659),
.Q(sig0000064e)
);
FD #(
.INIT ( 1'b0 ))
blk0000040d (
.C(clk),
.D(sig0000065a),
.Q(sig0000064f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000040e (
.C(clk),
.CE(sig00000002),
.D(sig00000730),
.Q(sig000006fa)
);
FDE #(
.INIT ( 1'b0 ))
blk0000040f (
.C(clk),
.CE(sig00000002),
.D(sig0000072f),
.Q(sig000006f9)
);
FDE #(
.INIT ( 1'b0 ))
blk00000410 (
.C(clk),
.CE(sig00000002),
.D(sig0000072e),
.Q(sig000006f8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000411 (
.C(clk),
.CE(sig00000002),
.D(sig0000072d),
.Q(sig000006f7)
);
FDE #(
.INIT ( 1'b0 ))
blk00000412 (
.C(clk),
.CE(sig00000002),
.D(sig0000072c),
.Q(sig000006f6)
);
FDE #(
.INIT ( 1'b0 ))
blk00000413 (
.C(clk),
.CE(sig00000002),
.D(sig0000072b),
.Q(sig000006f5)
);
FDE #(
.INIT ( 1'b0 ))
blk00000414 (
.C(clk),
.CE(sig00000002),
.D(sig00000729),
.Q(sig000006f3)
);
FDE #(
.INIT ( 1'b0 ))
blk00000415 (
.C(clk),
.CE(sig00000002),
.D(sig00000728),
.Q(sig000006f2)
);
FDE #(
.INIT ( 1'b0 ))
blk00000416 (
.C(clk),
.CE(sig00000002),
.D(sig00000727),
.Q(sig000006f1)
);
FDE #(
.INIT ( 1'b0 ))
blk00000417 (
.C(clk),
.CE(sig00000002),
.D(sig00000726),
.Q(sig000006f0)
);
FDE #(
.INIT ( 1'b0 ))
blk00000418 (
.C(clk),
.CE(sig00000002),
.D(sig00000725),
.Q(sig000006ef)
);
FDE #(
.INIT ( 1'b0 ))
blk00000419 (
.C(clk),
.CE(sig00000002),
.D(sig00000724),
.Q(sig000006ee)
);
FDE #(
.INIT ( 1'b0 ))
blk0000041a (
.C(clk),
.CE(sig00000002),
.D(sig00000723),
.Q(sig000006ed)
);
FDE #(
.INIT ( 1'b0 ))
blk0000041b (
.C(clk),
.CE(sig00000002),
.D(sig00000722),
.Q(sig000006ec)
);
FDE #(
.INIT ( 1'b0 ))
blk0000041c (
.C(clk),
.CE(sig00000002),
.D(sig00000721),
.Q(sig000006eb)
);
FDE #(
.INIT ( 1'b0 ))
blk0000041d (
.C(clk),
.CE(sig00000002),
.D(sig00000720),
.Q(sig000006ea)
);
FDE #(
.INIT ( 1'b0 ))
blk0000041e (
.C(clk),
.CE(sig00000002),
.D(sig0000071e),
.Q(sig000006e8)
);
FDE #(
.INIT ( 1'b0 ))
blk0000041f (
.C(clk),
.CE(sig00000002),
.D(sig0000071d),
.Q(sig000006e7)
);
FDE #(
.INIT ( 1'b0 ))
blk00000420 (
.C(clk),
.CE(sig00000002),
.D(sig0000071c),
.Q(sig000006e6)
);
FDE #(
.INIT ( 1'b0 ))
blk00000421 (
.C(clk),
.CE(sig00000002),
.D(sig0000071b),
.Q(sig000006e5)
);
FDE #(
.INIT ( 1'b0 ))
blk00000422 (
.C(clk),
.CE(sig00000002),
.D(sig0000071a),
.Q(sig000006e4)
);
FDE #(
.INIT ( 1'b0 ))
blk00000423 (
.C(clk),
.CE(sig00000002),
.D(sig00000719),
.Q(sig000006e3)
);
FDE #(
.INIT ( 1'b0 ))
blk00000424 (
.C(clk),
.CE(sig00000002),
.D(sig00000718),
.Q(sig000006e2)
);
FDE #(
.INIT ( 1'b0 ))
blk00000425 (
.C(clk),
.CE(sig00000002),
.D(sig00000717),
.Q(sig000006e1)
);
FDE #(
.INIT ( 1'b0 ))
blk00000426 (
.C(clk),
.CE(sig00000002),
.D(sig00000716),
.Q(sig000006e0)
);
FDE #(
.INIT ( 1'b0 ))
blk00000427 (
.C(clk),
.CE(sig00000002),
.D(sig00000715),
.Q(sig000006df)
);
FDE #(
.INIT ( 1'b0 ))
blk00000428 (
.C(clk),
.CE(sig00000002),
.D(sig00000713),
.Q(sig000006dd)
);
FDE #(
.INIT ( 1'b0 ))
blk00000429 (
.C(clk),
.CE(sig00000002),
.D(sig00000712),
.Q(sig000006dc)
);
FDE #(
.INIT ( 1'b0 ))
blk0000042a (
.C(clk),
.CE(sig00000002),
.D(sig00000711),
.Q(sig000006db)
);
FDE #(
.INIT ( 1'b0 ))
blk0000042b (
.C(clk),
.CE(sig00000002),
.D(sig00000710),
.Q(sig000006da)
);
FDE #(
.INIT ( 1'b0 ))
blk0000042c (
.C(clk),
.CE(sig00000002),
.D(sig0000070f),
.Q(sig000006d9)
);
FDE #(
.INIT ( 1'b0 ))
blk0000042d (
.C(clk),
.CE(sig00000002),
.D(sig0000070e),
.Q(sig000006d8)
);
FDE #(
.INIT ( 1'b0 ))
blk0000042e (
.C(clk),
.CE(sig00000002),
.D(sig0000070d),
.Q(sig000006d7)
);
FDE #(
.INIT ( 1'b0 ))
blk0000042f (
.C(clk),
.CE(sig00000002),
.D(sig0000070c),
.Q(sig000006d6)
);
FDE #(
.INIT ( 1'b0 ))
blk00000430 (
.C(clk),
.CE(sig00000002),
.D(sig0000070b),
.Q(sig000006d5)
);
FDE #(
.INIT ( 1'b0 ))
blk00000431 (
.C(clk),
.CE(sig00000002),
.D(sig0000070a),
.Q(sig000006d4)
);
FDE #(
.INIT ( 1'b0 ))
blk00000432 (
.C(clk),
.CE(sig00000002),
.D(sig00000708),
.Q(sig000006d2)
);
FDE #(
.INIT ( 1'b0 ))
blk00000433 (
.C(clk),
.CE(sig00000002),
.D(sig00000707),
.Q(sig000006d1)
);
FDE #(
.INIT ( 1'b0 ))
blk00000434 (
.C(clk),
.CE(sig00000002),
.D(sig00000706),
.Q(sig000006d0)
);
FDE #(
.INIT ( 1'b0 ))
blk00000435 (
.C(clk),
.CE(sig00000002),
.D(sig00000705),
.Q(sig000006cf)
);
FDE #(
.INIT ( 1'b0 ))
blk00000436 (
.C(clk),
.CE(sig00000002),
.D(sig00000704),
.Q(sig000006ce)
);
FDE #(
.INIT ( 1'b0 ))
blk00000437 (
.C(clk),
.CE(sig00000002),
.D(sig00000703),
.Q(sig000006cd)
);
FDE #(
.INIT ( 1'b0 ))
blk00000438 (
.C(clk),
.CE(sig00000002),
.D(sig00000702),
.Q(sig000006cc)
);
FDE #(
.INIT ( 1'b0 ))
blk00000439 (
.C(clk),
.CE(sig00000002),
.D(sig00000701),
.Q(sig000006cb)
);
FDE #(
.INIT ( 1'b0 ))
blk0000043a (
.C(clk),
.CE(sig00000002),
.D(sig00000700),
.Q(sig000006ca)
);
FDE #(
.INIT ( 1'b0 ))
blk0000043b (
.C(clk),
.CE(sig00000002),
.D(sig000006ff),
.Q(sig000006c9)
);
FDE #(
.INIT ( 1'b0 ))
blk0000043c (
.C(clk),
.CE(sig00000002),
.D(sig00000735),
.Q(sig000006fe)
);
FDE #(
.INIT ( 1'b0 ))
blk0000043d (
.C(clk),
.CE(sig00000002),
.D(sig00000734),
.Q(sig000006fd)
);
FDE #(
.INIT ( 1'b0 ))
blk0000043e (
.C(clk),
.CE(sig00000002),
.D(sig00000733),
.Q(sig000006fc)
);
FDE #(
.INIT ( 1'b0 ))
blk0000043f (
.C(clk),
.CE(sig00000002),
.D(sig00000732),
.Q(sig000006fb)
);
FDE #(
.INIT ( 1'b0 ))
blk00000440 (
.C(clk),
.CE(sig00000002),
.D(sig00000731),
.Q(sig000006f4)
);
FDE #(
.INIT ( 1'b0 ))
blk00000441 (
.C(clk),
.CE(sig00000002),
.D(sig0000072a),
.Q(sig000006e9)
);
FDE #(
.INIT ( 1'b0 ))
blk00000442 (
.C(clk),
.CE(sig00000002),
.D(sig0000071f),
.Q(sig000006de)
);
FDE #(
.INIT ( 1'b0 ))
blk00000443 (
.C(clk),
.CE(sig00000002),
.D(sig00000714),
.Q(sig000006d3)
);
FDE #(
.INIT ( 1'b0 ))
blk00000444 (
.C(clk),
.CE(sig00000002),
.D(sig00000709),
.Q(sig000006c8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000445 (
.C(clk),
.CE(sig00000002),
.D(sig00000767),
.Q(sig000006c3)
);
FDE #(
.INIT ( 1'b0 ))
blk00000446 (
.C(clk),
.CE(sig00000002),
.D(sig00000766),
.Q(sig000006c2)
);
FDE #(
.INIT ( 1'b0 ))
blk00000447 (
.C(clk),
.CE(sig00000002),
.D(sig00000765),
.Q(sig000006c1)
);
FDE #(
.INIT ( 1'b0 ))
blk00000448 (
.C(clk),
.CE(sig00000002),
.D(sig00000764),
.Q(sig000006c0)
);
FDE #(
.INIT ( 1'b0 ))
blk00000449 (
.C(clk),
.CE(sig00000002),
.D(sig00000763),
.Q(sig000006bf)
);
FDE #(
.INIT ( 1'b0 ))
blk0000044a (
.C(clk),
.CE(sig00000002),
.D(sig00000762),
.Q(sig000006be)
);
FDE #(
.INIT ( 1'b0 ))
blk0000044b (
.C(clk),
.CE(sig00000002),
.D(sig00000760),
.Q(sig000006bc)
);
FDE #(
.INIT ( 1'b0 ))
blk0000044c (
.C(clk),
.CE(sig00000002),
.D(sig0000075f),
.Q(sig000006bb)
);
FDE #(
.INIT ( 1'b0 ))
blk0000044d (
.C(clk),
.CE(sig00000002),
.D(sig0000075e),
.Q(sig000006ba)
);
FDE #(
.INIT ( 1'b0 ))
blk0000044e (
.C(clk),
.CE(sig00000002),
.D(sig0000075d),
.Q(sig000006b9)
);
FDE #(
.INIT ( 1'b0 ))
blk0000044f (
.C(clk),
.CE(sig00000002),
.D(sig0000075c),
.Q(sig000006b8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000450 (
.C(clk),
.CE(sig00000002),
.D(sig0000075b),
.Q(sig000006b7)
);
FDE #(
.INIT ( 1'b0 ))
blk00000451 (
.C(clk),
.CE(sig00000002),
.D(sig0000075a),
.Q(sig000006b6)
);
FDE #(
.INIT ( 1'b0 ))
blk00000452 (
.C(clk),
.CE(sig00000002),
.D(sig00000759),
.Q(sig000006b5)
);
FDE #(
.INIT ( 1'b0 ))
blk00000453 (
.C(clk),
.CE(sig00000002),
.D(sig00000758),
.Q(sig000006b4)
);
FDE #(
.INIT ( 1'b0 ))
blk00000454 (
.C(clk),
.CE(sig00000002),
.D(sig00000757),
.Q(sig000006b3)
);
FDE #(
.INIT ( 1'b0 ))
blk00000455 (
.C(clk),
.CE(sig00000002),
.D(sig00000755),
.Q(sig000006b1)
);
FDE #(
.INIT ( 1'b0 ))
blk00000456 (
.C(clk),
.CE(sig00000002),
.D(sig00000754),
.Q(sig000006b0)
);
FDE #(
.INIT ( 1'b0 ))
blk00000457 (
.C(clk),
.CE(sig00000002),
.D(sig00000753),
.Q(sig000006af)
);
FDE #(
.INIT ( 1'b0 ))
blk00000458 (
.C(clk),
.CE(sig00000002),
.D(sig00000752),
.Q(sig000006ae)
);
FDE #(
.INIT ( 1'b0 ))
blk00000459 (
.C(clk),
.CE(sig00000002),
.D(sig00000751),
.Q(sig000006ad)
);
FDE #(
.INIT ( 1'b0 ))
blk0000045a (
.C(clk),
.CE(sig00000002),
.D(sig00000750),
.Q(sig000006ac)
);
FDE #(
.INIT ( 1'b0 ))
blk0000045b (
.C(clk),
.CE(sig00000002),
.D(sig0000074f),
.Q(sig000006ab)
);
FDE #(
.INIT ( 1'b0 ))
blk0000045c (
.C(clk),
.CE(sig00000002),
.D(sig0000074e),
.Q(sig000006aa)
);
FDE #(
.INIT ( 1'b0 ))
blk0000045d (
.C(clk),
.CE(sig00000002),
.D(sig0000074d),
.Q(sig000006a9)
);
FDE #(
.INIT ( 1'b0 ))
blk0000045e (
.C(clk),
.CE(sig00000002),
.D(sig0000074c),
.Q(sig000006a8)
);
FDE #(
.INIT ( 1'b0 ))
blk0000045f (
.C(clk),
.CE(sig00000002),
.D(sig0000074a),
.Q(sig000006a6)
);
FDE #(
.INIT ( 1'b0 ))
blk00000460 (
.C(clk),
.CE(sig00000002),
.D(sig00000749),
.Q(sig000006a5)
);
FDE #(
.INIT ( 1'b0 ))
blk00000461 (
.C(clk),
.CE(sig00000002),
.D(sig00000748),
.Q(sig000006a4)
);
FDE #(
.INIT ( 1'b0 ))
blk00000462 (
.C(clk),
.CE(sig00000002),
.D(sig00000747),
.Q(sig000006a3)
);
FDE #(
.INIT ( 1'b0 ))
blk00000463 (
.C(clk),
.CE(sig00000002),
.D(sig00000746),
.Q(sig000006a2)
);
FDE #(
.INIT ( 1'b0 ))
blk00000464 (
.C(clk),
.CE(sig00000002),
.D(sig00000745),
.Q(sig000006a1)
);
FDE #(
.INIT ( 1'b0 ))
blk00000465 (
.C(clk),
.CE(sig00000002),
.D(sig00000744),
.Q(sig000006a0)
);
FDE #(
.INIT ( 1'b0 ))
blk00000466 (
.C(clk),
.CE(sig00000002),
.D(sig00000743),
.Q(sig0000069f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000467 (
.C(clk),
.CE(sig00000002),
.D(sig00000742),
.Q(sig0000069e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000468 (
.C(clk),
.CE(sig00000002),
.D(sig00000741),
.Q(sig0000069d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000469 (
.C(clk),
.CE(sig00000002),
.D(sig0000073f),
.Q(sig0000069b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000046a (
.C(clk),
.CE(sig00000002),
.D(sig0000073e),
.Q(sig0000069a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000046b (
.C(clk),
.CE(sig00000002),
.D(sig0000073d),
.Q(sig00000699)
);
FDE #(
.INIT ( 1'b0 ))
blk0000046c (
.C(clk),
.CE(sig00000002),
.D(sig0000073c),
.Q(sig00000698)
);
FDE #(
.INIT ( 1'b0 ))
blk0000046d (
.C(clk),
.CE(sig00000002),
.D(sig0000073b),
.Q(sig00000697)
);
FDE #(
.INIT ( 1'b0 ))
blk0000046e (
.C(clk),
.CE(sig00000002),
.D(sig0000073a),
.Q(sig00000696)
);
FDE #(
.INIT ( 1'b0 ))
blk0000046f (
.C(clk),
.CE(sig00000002),
.D(sig00000739),
.Q(sig00000695)
);
FDE #(
.INIT ( 1'b0 ))
blk00000470 (
.C(clk),
.CE(sig00000002),
.D(sig00000738),
.Q(sig00000694)
);
FDE #(
.INIT ( 1'b0 ))
blk00000471 (
.C(clk),
.CE(sig00000002),
.D(sig00000737),
.Q(sig00000693)
);
FDE #(
.INIT ( 1'b0 ))
blk00000472 (
.C(clk),
.CE(sig00000002),
.D(sig00000736),
.Q(sig00000692)
);
FDE #(
.INIT ( 1'b0 ))
blk00000473 (
.C(clk),
.CE(sig00000002),
.D(sig0000076c),
.Q(sig000006c7)
);
FDE #(
.INIT ( 1'b0 ))
blk00000474 (
.C(clk),
.CE(sig00000002),
.D(sig0000076b),
.Q(sig000006c6)
);
FDE #(
.INIT ( 1'b0 ))
blk00000475 (
.C(clk),
.CE(sig00000002),
.D(sig0000076a),
.Q(sig000006c5)
);
FDE #(
.INIT ( 1'b0 ))
blk00000476 (
.C(clk),
.CE(sig00000002),
.D(sig00000769),
.Q(sig000006c4)
);
FDE #(
.INIT ( 1'b0 ))
blk00000477 (
.C(clk),
.CE(sig00000002),
.D(sig00000768),
.Q(sig000006bd)
);
FDE #(
.INIT ( 1'b0 ))
blk00000478 (
.C(clk),
.CE(sig00000002),
.D(sig00000761),
.Q(sig000006b2)
);
FDE #(
.INIT ( 1'b0 ))
blk00000479 (
.C(clk),
.CE(sig00000002),
.D(sig00000756),
.Q(sig000006a7)
);
FDE #(
.INIT ( 1'b0 ))
blk0000047a (
.C(clk),
.CE(sig00000002),
.D(sig0000074b),
.Q(sig0000069c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000047b (
.C(clk),
.CE(sig00000002),
.D(sig00000740),
.Q(sig00000691)
);
FDRS blk0000047c (
.C(clk),
.D(sig00000779),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [10])
);
FDRS blk0000047d (
.C(clk),
.D(sig0000077a),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [11])
);
FDRS blk0000047e (
.C(clk),
.D(sig0000077b),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [12])
);
FDRS blk0000047f (
.C(clk),
.D(sig0000077c),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [13])
);
FDRS blk00000480 (
.C(clk),
.D(sig0000077d),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [14])
);
FDRS blk00000481 (
.C(clk),
.D(sig00000784),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [20])
);
FDRS blk00000482 (
.C(clk),
.D(sig0000077e),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [15])
);
FDRS blk00000483 (
.C(clk),
.D(sig00000785),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [21])
);
FDRS blk00000484 (
.C(clk),
.D(sig0000077f),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [16])
);
FDRS blk00000485 (
.C(clk),
.D(sig00000780),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [17])
);
FDRS blk00000486 (
.C(clk),
.D(sig00000786),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [22])
);
FDRS blk00000487 (
.C(clk),
.D(sig00000787),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [23])
);
FDRS blk00000488 (
.C(clk),
.D(sig00000781),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [18])
);
FDRS blk00000489 (
.C(clk),
.D(sig00000788),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [24])
);
FDRS blk0000048a (
.C(clk),
.D(sig00000782),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [19])
);
FDRS blk0000048b (
.C(clk),
.D(sig000007f6),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [31])
);
FDRS blk0000048c (
.C(clk),
.D(sig000007f5),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [30])
);
FDRS blk0000048d (
.C(clk),
.D(sig00000789),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [25])
);
FDRS blk0000048e (
.C(clk),
.D(sig000007e0),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [26])
);
FDRS blk0000048f (
.C(clk),
.D(sig00000777),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [0])
);
FDRS blk00000490 (
.C(clk),
.D(sig000007f7),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [32])
);
FDRS blk00000491 (
.C(clk),
.D(sig000007e1),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [27])
);
FDRS blk00000492 (
.C(clk),
.D(sig000007ec),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [28])
);
FDRS blk00000493 (
.C(clk),
.D(sig00000778),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [1])
);
FDRS blk00000494 (
.C(clk),
.D(sig000007f8),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [33])
);
FDRS blk00000495 (
.C(clk),
.D(sig00000783),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [2])
);
FDRS blk00000496 (
.C(clk),
.D(sig000007f9),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [34])
);
FDRS blk00000497 (
.C(clk),
.D(sig000007f4),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [29])
);
FDRS blk00000498 (
.C(clk),
.D(sig0000078a),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [3])
);
FDRS blk00000499 (
.C(clk),
.D(sig000007e6),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [40])
);
FDRS blk0000049a (
.C(clk),
.D(sig000007fa),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [35])
);
FDRS blk0000049b (
.C(clk),
.D(sig0000078b),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [4])
);
FDRS blk0000049c (
.C(clk),
.D(sig000007e7),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [41])
);
FDRS blk0000049d (
.C(clk),
.D(sig000007e2),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [36])
);
FDRS blk0000049e (
.C(clk),
.D(sig0000078c),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [5])
);
FDRS blk0000049f (
.C(clk),
.D(sig000007e8),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [42])
);
FDRS blk000004a0 (
.C(clk),
.D(sig000007e3),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [37])
);
FDRS blk000004a1 (
.C(clk),
.D(sig000007e4),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [38])
);
FDRS blk000004a2 (
.C(clk),
.D(sig0000078d),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [6])
);
FDRS blk000004a3 (
.C(clk),
.D(sig000007e9),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [43])
);
FDRS blk000004a4 (
.C(clk),
.D(sig0000078e),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [7])
);
FDRS blk000004a5 (
.C(clk),
.D(sig000007ea),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [44])
);
FDRS blk000004a6 (
.C(clk),
.D(sig000007e5),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [39])
);
FDRS blk000004a7 (
.C(clk),
.D(sig0000078f),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [8])
);
FDRS blk000004a8 (
.C(clk),
.D(sig00000790),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [9])
);
FDRS blk000004a9 (
.C(clk),
.D(sig000007f1),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [50])
);
FDRS blk000004aa (
.C(clk),
.D(sig000007eb),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [45])
);
FDRS blk000004ab (
.C(clk),
.D(sig000007f2),
.R(sig0000049e),
.S(sig0000049d),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [51])
);
FDRS blk000004ac (
.C(clk),
.D(sig000007ed),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [46])
);
FDRS blk000004ad (
.C(clk),
.D(sig000005a2),
.R(sig00000001),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/sign_op )
);
FDRS blk000004ae (
.C(clk),
.D(sig000007ee),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [47])
);
FDRS blk000004af (
.C(clk),
.D(sig000007ef),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [48])
);
FDRS blk000004b0 (
.C(clk),
.D(sig000007f0),
.R(sig0000049f),
.S(sig00000001),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/mant_op [49])
);
FD blk000004b1 (
.C(clk),
.D(sig000008ae),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [0])
);
FD blk000004b2 (
.C(clk),
.D(sig000008b0),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [1])
);
FD blk000004b3 (
.C(clk),
.D(sig000008b1),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [2])
);
FD blk000004b4 (
.C(clk),
.D(sig000008b2),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [3])
);
FD blk000004b5 (
.C(clk),
.D(sig000008b3),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [4])
);
FD blk000004b6 (
.C(clk),
.D(sig000008b4),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [5])
);
FD blk000004b7 (
.C(clk),
.D(sig000008b5),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [6])
);
FD blk000004b8 (
.C(clk),
.D(sig000008b6),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [7])
);
FD blk000004b9 (
.C(clk),
.D(sig000008b7),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [8])
);
FD blk000004ba (
.C(clk),
.D(sig000008b8),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [9])
);
FD blk000004bb (
.C(clk),
.D(sig000008af),
.Q(\U0/op_inst/FLT_PT_OP/ADDSUB_OP.SPEED_OP.LOGIC.OP/OP/exp_op [10])
);
MUXCY blk000004bc (
.CI(sig00000001),
.DI(sig000008a3),
.S(sig000008a2),
.O(sig00000898)
);
XORCY blk000004bd (
.CI(sig00000001),
.LI(sig000008a2),
.O(sig000008ae)
);
MUXCY blk000004be (
.CI(sig00000898),
.DI(sig00000001),
.S(sig000008a5),
.O(sig00000899)
);
XORCY blk000004bf (
.CI(sig00000898),
.LI(sig000008a5),
.O(sig000008b0)
);
MUXCY blk000004c0 (
.CI(sig00000899),
.DI(sig00000001),
.S(sig000008a6),
.O(sig0000089a)
);
XORCY blk000004c1 (
.CI(sig00000899),
.LI(sig000008a6),
.O(sig000008b1)
);
MUXCY blk000004c2 (
.CI(sig0000089a),
.DI(sig00000001),
.S(sig000008a7),
.O(sig0000089b)
);
XORCY blk000004c3 (
.CI(sig0000089a),
.LI(sig000008a7),
.O(sig000008b2)
);
MUXCY blk000004c4 (
.CI(sig0000089b),
.DI(sig00000001),
.S(sig000008a8),
.O(sig0000089c)
);
XORCY blk000004c5 (
.CI(sig0000089b),
.LI(sig000008a8),
.O(sig000008b3)
);
MUXCY blk000004c6 (
.CI(sig0000089c),
.DI(sig00000001),
.S(sig000008a9),
.O(sig0000089d)
);
XORCY blk000004c7 (
.CI(sig0000089c),
.LI(sig000008a9),
.O(sig000008b4)
);
MUXCY blk000004c8 (
.CI(sig0000089d),
.DI(sig00000001),
.S(sig000008aa),
.O(sig0000089e)
);
XORCY blk000004c9 (
.CI(sig0000089d),
.LI(sig000008aa),
.O(sig000008b5)
);
MUXCY blk000004ca (
.CI(sig0000089e),
.DI(sig00000001),
.S(sig000008ab),
.O(sig0000089f)
);
XORCY blk000004cb (
.CI(sig0000089e),
.LI(sig000008ab),
.O(sig000008b6)
);
MUXCY blk000004cc (
.CI(sig0000089f),
.DI(sig00000001),
.S(sig000008ac),
.O(sig000008a0)
);
XORCY blk000004cd (
.CI(sig0000089f),
.LI(sig000008ac),
.O(sig000008b7)
);
MUXCY blk000004ce (
.CI(sig000008a0),
.DI(sig00000001),
.S(sig000008ad),
.O(sig000008a1)
);
XORCY blk000004cf (
.CI(sig000008a0),
.LI(sig000008ad),
.O(sig000008b8)
);
XORCY blk000004d0 (
.CI(sig000008a1),
.LI(sig000008a4),
.O(sig000008af)
);
FDE #(
.INIT ( 1'b0 ))
blk000004d1 (
.C(clk),
.CE(sig00000002),
.D(sig00000212),
.Q(sig000005ef)
);
FDE #(
.INIT ( 1'b0 ))
blk000004d2 (
.C(clk),
.CE(sig00000002),
.D(sig00000213),
.Q(sig000005f0)
);
FDE #(
.INIT ( 1'b0 ))
blk000004d3 (
.C(clk),
.CE(sig00000002),
.D(sig0000021e),
.Q(sig000005fb)
);
FDE #(
.INIT ( 1'b0 ))
blk000004d4 (
.C(clk),
.CE(sig00000002),
.D(sig00000226),
.Q(sig00000606)
);
FDE #(
.INIT ( 1'b0 ))
blk000004d5 (
.C(clk),
.CE(sig00000002),
.D(sig00000227),
.Q(sig00000611)
);
FDE #(
.INIT ( 1'b0 ))
blk000004d6 (
.C(clk),
.CE(sig00000002),
.D(sig00000228),
.Q(sig0000061c)
);
FDE #(
.INIT ( 1'b0 ))
blk000004d7 (
.C(clk),
.CE(sig00000002),
.D(sig00000229),
.Q(sig00000623)
);
FDE #(
.INIT ( 1'b0 ))
blk000004d8 (
.C(clk),
.CE(sig00000002),
.D(sig0000022a),
.Q(sig00000624)
);
FDE #(
.INIT ( 1'b0 ))
blk000004d9 (
.C(clk),
.CE(sig00000002),
.D(sig0000022b),
.Q(sig00000625)
);
FDE #(
.INIT ( 1'b0 ))
blk000004da (
.C(clk),
.CE(sig00000002),
.D(sig0000022c),
.Q(sig00000626)
);
FDE #(
.INIT ( 1'b0 ))
blk000004db (
.C(clk),
.CE(sig00000002),
.D(sig00000214),
.Q(sig000005f1)
);
FDE #(
.INIT ( 1'b0 ))
blk000004dc (
.C(clk),
.CE(sig00000002),
.D(sig00000215),
.Q(sig000005f2)
);
FDE #(
.INIT ( 1'b0 ))
blk000004dd (
.C(clk),
.CE(sig00000002),
.D(sig00000216),
.Q(sig000005f3)
);
FDE #(
.INIT ( 1'b0 ))
blk000004de (
.C(clk),
.CE(sig00000002),
.D(sig00000217),
.Q(sig000005f4)
);
FDE #(
.INIT ( 1'b0 ))
blk000004df (
.C(clk),
.CE(sig00000002),
.D(sig00000218),
.Q(sig000005f5)
);
FDE #(
.INIT ( 1'b0 ))
blk000004e0 (
.C(clk),
.CE(sig00000002),
.D(sig00000219),
.Q(sig000005f6)
);
FDE #(
.INIT ( 1'b0 ))
blk000004e1 (
.C(clk),
.CE(sig00000002),
.D(sig0000021a),
.Q(sig000005f7)
);
FDE #(
.INIT ( 1'b0 ))
blk000004e2 (
.C(clk),
.CE(sig00000002),
.D(sig0000021b),
.Q(sig000005f8)
);
FDE #(
.INIT ( 1'b0 ))
blk000004e3 (
.C(clk),
.CE(sig00000002),
.D(sig0000021c),
.Q(sig000005f9)
);
FDE #(
.INIT ( 1'b0 ))
blk000004e4 (
.C(clk),
.CE(sig00000002),
.D(sig0000021d),
.Q(sig000005fa)
);
FDE #(
.INIT ( 1'b0 ))
blk000004e5 (
.C(clk),
.CE(sig00000002),
.D(sig0000021f),
.Q(sig000005fc)
);
FDE #(
.INIT ( 1'b0 ))
blk000004e6 (
.C(clk),
.CE(sig00000002),
.D(sig00000220),
.Q(sig000005fd)
);
FDE #(
.INIT ( 1'b0 ))
blk000004e7 (
.C(clk),
.CE(sig00000002),
.D(sig00000221),
.Q(sig000005fe)
);
FDE #(
.INIT ( 1'b0 ))
blk000004e8 (
.C(clk),
.CE(sig00000002),
.D(sig00000222),
.Q(sig000005ff)
);
FDE #(
.INIT ( 1'b0 ))
blk000004e9 (
.C(clk),
.CE(sig00000002),
.D(sig00000223),
.Q(sig00000600)
);
FDE #(
.INIT ( 1'b0 ))
blk000004ea (
.C(clk),
.CE(sig00000002),
.D(sig00000224),
.Q(sig00000601)
);
FDE #(
.INIT ( 1'b0 ))
blk000004eb (
.C(clk),
.CE(sig00000002),
.D(sig00000225),
.Q(sig00000602)
);
FDE #(
.INIT ( 1'b0 ))
blk000004ec (
.C(clk),
.CE(sig00000002),
.D(sig000002a0),
.Q(sig00000603)
);
FDE #(
.INIT ( 1'b0 ))
blk000004ed (
.C(clk),
.CE(sig00000002),
.D(sig000002a1),
.Q(sig00000604)
);
FDE #(
.INIT ( 1'b0 ))
blk000004ee (
.C(clk),
.CE(sig00000002),
.D(sig000002ac),
.Q(sig00000605)
);
FDE #(
.INIT ( 1'b0 ))
blk000004ef (
.C(clk),
.CE(sig00000002),
.D(sig000002b6),
.Q(sig00000607)
);
FDE #(
.INIT ( 1'b0 ))
blk000004f0 (
.C(clk),
.CE(sig00000002),
.D(sig000002b7),
.Q(sig00000608)
);
FDE #(
.INIT ( 1'b0 ))
blk000004f1 (
.C(clk),
.CE(sig00000002),
.D(sig000002b8),
.Q(sig00000609)
);
FDE #(
.INIT ( 1'b0 ))
blk000004f2 (
.C(clk),
.CE(sig00000002),
.D(sig000002b9),
.Q(sig0000060a)
);
FDE #(
.INIT ( 1'b0 ))
blk000004f3 (
.C(clk),
.CE(sig00000002),
.D(sig000002ba),
.Q(sig0000060b)
);
FDE #(
.INIT ( 1'b0 ))
blk000004f4 (
.C(clk),
.CE(sig00000002),
.D(sig000002bb),
.Q(sig0000060c)
);
FDE #(
.INIT ( 1'b0 ))
blk000004f5 (
.C(clk),
.CE(sig00000002),
.D(sig000002bc),
.Q(sig0000060d)
);
FDE #(
.INIT ( 1'b0 ))
blk000004f6 (
.C(clk),
.CE(sig00000002),
.D(sig000002a2),
.Q(sig0000060e)
);
FDE #(
.INIT ( 1'b0 ))
blk000004f7 (
.C(clk),
.CE(sig00000002),
.D(sig000002a3),
.Q(sig0000060f)
);
FDE #(
.INIT ( 1'b0 ))
blk000004f8 (
.C(clk),
.CE(sig00000002),
.D(sig000002a4),
.Q(sig00000610)
);
FDE #(
.INIT ( 1'b0 ))
blk000004f9 (
.C(clk),
.CE(sig00000002),
.D(sig000002a5),
.Q(sig00000612)
);
FDE #(
.INIT ( 1'b0 ))
blk000004fa (
.C(clk),
.CE(sig00000002),
.D(sig000002a6),
.Q(sig00000613)
);
FDE #(
.INIT ( 1'b0 ))
blk000004fb (
.C(clk),
.CE(sig00000002),
.D(sig000002a7),
.Q(sig00000614)
);
FDE #(
.INIT ( 1'b0 ))
blk000004fc (
.C(clk),
.CE(sig00000002),
.D(sig000002a8),
.Q(sig00000615)
);
FDE #(
.INIT ( 1'b0 ))
blk000004fd (
.C(clk),
.CE(sig00000002),
.D(sig000002a9),
.Q(sig00000616)
);
FDE #(
.INIT ( 1'b0 ))
blk000004fe (
.C(clk),
.CE(sig00000002),
.D(sig000002aa),
.Q(sig00000617)
);
FDE #(
.INIT ( 1'b0 ))
blk000004ff (
.C(clk),
.CE(sig00000002),
.D(sig000002ab),
.Q(sig00000618)
);
FDE #(
.INIT ( 1'b0 ))
blk00000500 (
.C(clk),
.CE(sig00000002),
.D(sig000002ad),
.Q(sig00000619)
);
FDE #(
.INIT ( 1'b0 ))
blk00000501 (
.C(clk),
.CE(sig00000002),
.D(sig000002ae),
.Q(sig0000061a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000502 (
.C(clk),
.CE(sig00000002),
.D(sig000002af),
.Q(sig0000061b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000503 (
.C(clk),
.CE(sig00000002),
.D(sig000002b0),
.Q(sig0000061d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000504 (
.C(clk),
.CE(sig00000002),
.D(sig000002b1),
.Q(sig0000061e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000505 (
.C(clk),
.CE(sig00000002),
.D(sig000002b2),
.Q(sig0000061f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000506 (
.C(clk),
.CE(sig00000002),
.D(sig000002b3),
.Q(sig00000620)
);
FDE #(
.INIT ( 1'b0 ))
blk00000507 (
.C(clk),
.CE(sig00000002),
.D(sig000002b4),
.Q(sig00000621)
);
FDE #(
.INIT ( 1'b0 ))
blk00000508 (
.C(clk),
.CE(sig00000002),
.D(sig000002b5),
.Q(sig00000622)
);
FDE #(
.INIT ( 1'b0 ))
blk00000509 (
.C(clk),
.CE(sig00000002),
.D(a[0]),
.Q(sig000003e1)
);
FDE #(
.INIT ( 1'b0 ))
blk0000050a (
.C(clk),
.CE(sig00000002),
.D(a[1]),
.Q(sig000003e2)
);
FDE #(
.INIT ( 1'b0 ))
blk0000050b (
.C(clk),
.CE(sig00000002),
.D(a[2]),
.Q(sig000003ed)
);
FDE #(
.INIT ( 1'b0 ))
blk0000050c (
.C(clk),
.CE(sig00000002),
.D(a[3]),
.Q(sig000003f8)
);
FDE #(
.INIT ( 1'b0 ))
blk0000050d (
.C(clk),
.CE(sig00000002),
.D(a[4]),
.Q(sig00000403)
);
FDE #(
.INIT ( 1'b0 ))
blk0000050e (
.C(clk),
.CE(sig00000002),
.D(a[5]),
.Q(sig0000040e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000050f (
.C(clk),
.CE(sig00000002),
.D(a[6]),
.Q(sig00000411)
);
FDE #(
.INIT ( 1'b0 ))
blk00000510 (
.C(clk),
.CE(sig00000002),
.D(a[7]),
.Q(sig00000412)
);
FDE #(
.INIT ( 1'b0 ))
blk00000511 (
.C(clk),
.CE(sig00000002),
.D(a[8]),
.Q(sig00000413)
);
FDE #(
.INIT ( 1'b0 ))
blk00000512 (
.C(clk),
.CE(sig00000002),
.D(a[9]),
.Q(sig00000414)
);
FDE #(
.INIT ( 1'b0 ))
blk00000513 (
.C(clk),
.CE(sig00000002),
.D(a[10]),
.Q(sig000003e3)
);
FDE #(
.INIT ( 1'b0 ))
blk00000514 (
.C(clk),
.CE(sig00000002),
.D(a[11]),
.Q(sig000003e4)
);
FDE #(
.INIT ( 1'b0 ))
blk00000515 (
.C(clk),
.CE(sig00000002),
.D(a[12]),
.Q(sig000003e5)
);
FDE #(
.INIT ( 1'b0 ))
blk00000516 (
.C(clk),
.CE(sig00000002),
.D(a[13]),
.Q(sig000003e6)
);
FDE #(
.INIT ( 1'b0 ))
blk00000517 (
.C(clk),
.CE(sig00000002),
.D(a[14]),
.Q(sig000003e7)
);
FDE #(
.INIT ( 1'b0 ))
blk00000518 (
.C(clk),
.CE(sig00000002),
.D(a[15]),
.Q(sig000003e8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000519 (
.C(clk),
.CE(sig00000002),
.D(a[16]),
.Q(sig000003e9)
);
FDE #(
.INIT ( 1'b0 ))
blk0000051a (
.C(clk),
.CE(sig00000002),
.D(a[17]),
.Q(sig000003ea)
);
FDE #(
.INIT ( 1'b0 ))
blk0000051b (
.C(clk),
.CE(sig00000002),
.D(a[18]),
.Q(sig000003eb)
);
FDE #(
.INIT ( 1'b0 ))
blk0000051c (
.C(clk),
.CE(sig00000002),
.D(a[19]),
.Q(sig000003ec)
);
FDE #(
.INIT ( 1'b0 ))
blk0000051d (
.C(clk),
.CE(sig00000002),
.D(a[20]),
.Q(sig000003ee)
);
FDE #(
.INIT ( 1'b0 ))
blk0000051e (
.C(clk),
.CE(sig00000002),
.D(a[21]),
.Q(sig000003ef)
);
FDE #(
.INIT ( 1'b0 ))
blk0000051f (
.C(clk),
.CE(sig00000002),
.D(a[22]),
.Q(sig000003f0)
);
FDE #(
.INIT ( 1'b0 ))
blk00000520 (
.C(clk),
.CE(sig00000002),
.D(a[23]),
.Q(sig000003f1)
);
FDE #(
.INIT ( 1'b0 ))
blk00000521 (
.C(clk),
.CE(sig00000002),
.D(a[24]),
.Q(sig000003f2)
);
FDE #(
.INIT ( 1'b0 ))
blk00000522 (
.C(clk),
.CE(sig00000002),
.D(a[25]),
.Q(sig000003f3)
);
FDE #(
.INIT ( 1'b0 ))
blk00000523 (
.C(clk),
.CE(sig00000002),
.D(a[26]),
.Q(sig000003f4)
);
FDE #(
.INIT ( 1'b0 ))
blk00000524 (
.C(clk),
.CE(sig00000002),
.D(a[27]),
.Q(sig000003f5)
);
FDE #(
.INIT ( 1'b0 ))
blk00000525 (
.C(clk),
.CE(sig00000002),
.D(a[28]),
.Q(sig000003f6)
);
FDE #(
.INIT ( 1'b0 ))
blk00000526 (
.C(clk),
.CE(sig00000002),
.D(a[29]),
.Q(sig000003f7)
);
FDE #(
.INIT ( 1'b0 ))
blk00000527 (
.C(clk),
.CE(sig00000002),
.D(a[30]),
.Q(sig000003f9)
);
FDE #(
.INIT ( 1'b0 ))
blk00000528 (
.C(clk),
.CE(sig00000002),
.D(a[31]),
.Q(sig000003fa)
);
FDE #(
.INIT ( 1'b0 ))
blk00000529 (
.C(clk),
.CE(sig00000002),
.D(a[32]),
.Q(sig000003fb)
);
FDE #(
.INIT ( 1'b0 ))
blk0000052a (
.C(clk),
.CE(sig00000002),
.D(a[33]),
.Q(sig000003fc)
);
FDE #(
.INIT ( 1'b0 ))
blk0000052b (
.C(clk),
.CE(sig00000002),
.D(a[34]),
.Q(sig000003fd)
);
FDE #(
.INIT ( 1'b0 ))
blk0000052c (
.C(clk),
.CE(sig00000002),
.D(a[35]),
.Q(sig000003fe)
);
FDE #(
.INIT ( 1'b0 ))
blk0000052d (
.C(clk),
.CE(sig00000002),
.D(a[36]),
.Q(sig000003ff)
);
FDE #(
.INIT ( 1'b0 ))
blk0000052e (
.C(clk),
.CE(sig00000002),
.D(a[37]),
.Q(sig00000400)
);
FDE #(
.INIT ( 1'b0 ))
blk0000052f (
.C(clk),
.CE(sig00000002),
.D(a[38]),
.Q(sig00000401)
);
FDE #(
.INIT ( 1'b0 ))
blk00000530 (
.C(clk),
.CE(sig00000002),
.D(a[39]),
.Q(sig00000402)
);
FDE #(
.INIT ( 1'b0 ))
blk00000531 (
.C(clk),
.CE(sig00000002),
.D(a[40]),
.Q(sig00000404)
);
FDE #(
.INIT ( 1'b0 ))
blk00000532 (
.C(clk),
.CE(sig00000002),
.D(a[41]),
.Q(sig00000405)
);
FDE #(
.INIT ( 1'b0 ))
blk00000533 (
.C(clk),
.CE(sig00000002),
.D(a[42]),
.Q(sig00000406)
);
FDE #(
.INIT ( 1'b0 ))
blk00000534 (
.C(clk),
.CE(sig00000002),
.D(a[43]),
.Q(sig00000407)
);
FDE #(
.INIT ( 1'b0 ))
blk00000535 (
.C(clk),
.CE(sig00000002),
.D(a[44]),
.Q(sig00000408)
);
FDE #(
.INIT ( 1'b0 ))
blk00000536 (
.C(clk),
.CE(sig00000002),
.D(a[45]),
.Q(sig00000409)
);
FDE #(
.INIT ( 1'b0 ))
blk00000537 (
.C(clk),
.CE(sig00000002),
.D(a[46]),
.Q(sig0000040a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000538 (
.C(clk),
.CE(sig00000002),
.D(a[47]),
.Q(sig0000040b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000539 (
.C(clk),
.CE(sig00000002),
.D(a[48]),
.Q(sig0000040c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000053a (
.C(clk),
.CE(sig00000002),
.D(a[49]),
.Q(sig0000040d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000053b (
.C(clk),
.CE(sig00000002),
.D(a[50]),
.Q(sig0000040f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000053c (
.C(clk),
.CE(sig00000002),
.D(a[51]),
.Q(sig00000410)
);
FDE #(
.INIT ( 1'b0 ))
blk0000053d (
.C(clk),
.CE(sig00000002),
.D(b[0]),
.Q(sig00000415)
);
FDE #(
.INIT ( 1'b0 ))
blk0000053e (
.C(clk),
.CE(sig00000002),
.D(b[1]),
.Q(sig00000416)
);
FDE #(
.INIT ( 1'b0 ))
blk0000053f (
.C(clk),
.CE(sig00000002),
.D(b[2]),
.Q(sig00000421)
);
FDE #(
.INIT ( 1'b0 ))
blk00000540 (
.C(clk),
.CE(sig00000002),
.D(b[3]),
.Q(sig0000042c)
);
FDE #(
.INIT ( 1'b0 ))
blk00000541 (
.C(clk),
.CE(sig00000002),
.D(b[4]),
.Q(sig00000437)
);
FDE #(
.INIT ( 1'b0 ))
blk00000542 (
.C(clk),
.CE(sig00000002),
.D(b[5]),
.Q(sig00000442)
);
FDE #(
.INIT ( 1'b0 ))
blk00000543 (
.C(clk),
.CE(sig00000002),
.D(b[6]),
.Q(sig00000445)
);
FDE #(
.INIT ( 1'b0 ))
blk00000544 (
.C(clk),
.CE(sig00000002),
.D(b[7]),
.Q(sig00000446)
);
FDE #(
.INIT ( 1'b0 ))
blk00000545 (
.C(clk),
.CE(sig00000002),
.D(b[8]),
.Q(sig00000447)
);
FDE #(
.INIT ( 1'b0 ))
blk00000546 (
.C(clk),
.CE(sig00000002),
.D(b[9]),
.Q(sig00000448)
);
FDE #(
.INIT ( 1'b0 ))
blk00000547 (
.C(clk),
.CE(sig00000002),
.D(b[10]),
.Q(sig00000417)
);
FDE #(
.INIT ( 1'b0 ))
blk00000548 (
.C(clk),
.CE(sig00000002),
.D(b[11]),
.Q(sig00000418)
);
FDE #(
.INIT ( 1'b0 ))
blk00000549 (
.C(clk),
.CE(sig00000002),
.D(b[12]),
.Q(sig00000419)
);
FDE #(
.INIT ( 1'b0 ))
blk0000054a (
.C(clk),
.CE(sig00000002),
.D(b[13]),
.Q(sig0000041a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000054b (
.C(clk),
.CE(sig00000002),
.D(b[14]),
.Q(sig0000041b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000054c (
.C(clk),
.CE(sig00000002),
.D(b[15]),
.Q(sig0000041c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000054d (
.C(clk),
.CE(sig00000002),
.D(b[16]),
.Q(sig0000041d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000054e (
.C(clk),
.CE(sig00000002),
.D(b[17]),
.Q(sig0000041e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000054f (
.C(clk),
.CE(sig00000002),
.D(b[18]),
.Q(sig0000041f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000550 (
.C(clk),
.CE(sig00000002),
.D(b[19]),
.Q(sig00000420)
);
FDE #(
.INIT ( 1'b0 ))
blk00000551 (
.C(clk),
.CE(sig00000002),
.D(b[20]),
.Q(sig00000422)
);
FDE #(
.INIT ( 1'b0 ))
blk00000552 (
.C(clk),
.CE(sig00000002),
.D(b[21]),
.Q(sig00000423)
);
FDE #(
.INIT ( 1'b0 ))
blk00000553 (
.C(clk),
.CE(sig00000002),
.D(b[22]),
.Q(sig00000424)
);
FDE #(
.INIT ( 1'b0 ))
blk00000554 (
.C(clk),
.CE(sig00000002),
.D(b[23]),
.Q(sig00000425)
);
FDE #(
.INIT ( 1'b0 ))
blk00000555 (
.C(clk),
.CE(sig00000002),
.D(b[24]),
.Q(sig00000426)
);
FDE #(
.INIT ( 1'b0 ))
blk00000556 (
.C(clk),
.CE(sig00000002),
.D(b[25]),
.Q(sig00000427)
);
FDE #(
.INIT ( 1'b0 ))
blk00000557 (
.C(clk),
.CE(sig00000002),
.D(b[26]),
.Q(sig00000428)
);
FDE #(
.INIT ( 1'b0 ))
blk00000558 (
.C(clk),
.CE(sig00000002),
.D(b[27]),
.Q(sig00000429)
);
FDE #(
.INIT ( 1'b0 ))
blk00000559 (
.C(clk),
.CE(sig00000002),
.D(b[28]),
.Q(sig0000042a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000055a (
.C(clk),
.CE(sig00000002),
.D(b[29]),
.Q(sig0000042b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000055b (
.C(clk),
.CE(sig00000002),
.D(b[30]),
.Q(sig0000042d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000055c (
.C(clk),
.CE(sig00000002),
.D(b[31]),
.Q(sig0000042e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000055d (
.C(clk),
.CE(sig00000002),
.D(b[32]),
.Q(sig0000042f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000055e (
.C(clk),
.CE(sig00000002),
.D(b[33]),
.Q(sig00000430)
);
FDE #(
.INIT ( 1'b0 ))
blk0000055f (
.C(clk),
.CE(sig00000002),
.D(b[34]),
.Q(sig00000431)
);
FDE #(
.INIT ( 1'b0 ))
blk00000560 (
.C(clk),
.CE(sig00000002),
.D(b[35]),
.Q(sig00000432)
);
FDE #(
.INIT ( 1'b0 ))
blk00000561 (
.C(clk),
.CE(sig00000002),
.D(b[36]),
.Q(sig00000433)
);
FDE #(
.INIT ( 1'b0 ))
blk00000562 (
.C(clk),
.CE(sig00000002),
.D(b[37]),
.Q(sig00000434)
);
FDE #(
.INIT ( 1'b0 ))
blk00000563 (
.C(clk),
.CE(sig00000002),
.D(b[38]),
.Q(sig00000435)
);
FDE #(
.INIT ( 1'b0 ))
blk00000564 (
.C(clk),
.CE(sig00000002),
.D(b[39]),
.Q(sig00000436)
);
FDE #(
.INIT ( 1'b0 ))
blk00000565 (
.C(clk),
.CE(sig00000002),
.D(b[40]),
.Q(sig00000438)
);
FDE #(
.INIT ( 1'b0 ))
blk00000566 (
.C(clk),
.CE(sig00000002),
.D(b[41]),
.Q(sig00000439)
);
FDE #(
.INIT ( 1'b0 ))
blk00000567 (
.C(clk),
.CE(sig00000002),
.D(b[42]),
.Q(sig0000043a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000568 (
.C(clk),
.CE(sig00000002),
.D(b[43]),
.Q(sig0000043b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000569 (
.C(clk),
.CE(sig00000002),
.D(b[44]),
.Q(sig0000043c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000056a (
.C(clk),
.CE(sig00000002),
.D(b[45]),
.Q(sig0000043d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000056b (
.C(clk),
.CE(sig00000002),
.D(b[46]),
.Q(sig0000043e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000056c (
.C(clk),
.CE(sig00000002),
.D(b[47]),
.Q(sig0000043f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000056d (
.C(clk),
.CE(sig00000002),
.D(b[48]),
.Q(sig00000440)
);
FDE #(
.INIT ( 1'b0 ))
blk0000056e (
.C(clk),
.CE(sig00000002),
.D(b[49]),
.Q(sig00000441)
);
FDE #(
.INIT ( 1'b0 ))
blk0000056f (
.C(clk),
.CE(sig00000002),
.D(b[50]),
.Q(sig00000443)
);
FDE #(
.INIT ( 1'b0 ))
blk00000570 (
.C(clk),
.CE(sig00000002),
.D(b[51]),
.Q(sig00000444)
);
FDE #(
.INIT ( 1'b0 ))
blk00000571 (
.C(clk),
.CE(sig00000002),
.D(sig000008b9),
.Q(sig000003e0)
);
LUT2 #(
.INIT ( 4'h8 ))
blk00000572 (
.I0(sig0000064e),
.I1(sig0000064f),
.O(sig00000666)
);
LUT2 #(
.INIT ( 4'h8 ))
blk00000573 (
.I0(sig0000064c),
.I1(sig0000064d),
.O(sig00000665)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000574 (
.I0(b[52]),
.I1(a[52]),
.O(sig000008b9)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000575 (
.I0(b[63]),
.I1(a[63]),
.O(sig000005ee)
);
LUT2 #(
.INIT ( 4'h4 ))
blk00000576 (
.I0(a[62]),
.I1(b[62]),
.O(sig00000585)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk00000577 (
.I0(b[31]),
.I1(b[30]),
.I2(a[30]),
.I3(a[31]),
.O(sig0000053f)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000578 (
.I0(b[62]),
.I1(a[62]),
.O(sig00000595)
);
LUT2 #(
.INIT ( 4'h9 ))
blk00000579 (
.I0(b[62]),
.I1(a[62]),
.O(sig00000565)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk0000057a (
.I0(b[48]),
.I1(b[49]),
.I2(b[50]),
.I3(b[51]),
.O(sig00000498)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk0000057b (
.I0(a[48]),
.I1(a[49]),
.I2(a[50]),
.I3(a[51]),
.O(sig00000482)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000057c (
.I0(b[30]),
.I1(a[30]),
.I2(b[31]),
.I3(a[31]),
.O(sig0000054f)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk0000057d (
.I0(b[61]),
.I1(b[60]),
.I2(a[60]),
.I3(a[61]),
.O(sig00000584)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk0000057e (
.I0(b[29]),
.I1(b[28]),
.I2(a[28]),
.I3(a[29]),
.O(sig0000053e)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000057f (
.I0(b[60]),
.I1(a[60]),
.I2(b[61]),
.I3(a[61]),
.O(sig00000594)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000580 (
.I0(b[28]),
.I1(a[28]),
.I2(b[29]),
.I3(a[29]),
.O(sig0000054e)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000581 (
.I0(b[42]),
.I1(b[43]),
.I2(b[44]),
.I3(b[45]),
.I4(b[46]),
.I5(b[47]),
.O(sig00000497)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000582 (
.I0(a[42]),
.I1(a[43]),
.I2(a[44]),
.I3(a[45]),
.I4(a[46]),
.I5(a[47]),
.O(sig00000481)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000583 (
.I0(b[59]),
.I1(a[59]),
.I2(b[60]),
.I3(a[60]),
.I4(b[61]),
.I5(a[61]),
.O(sig0000056e)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk00000584 (
.I0(b[59]),
.I1(b[58]),
.I2(a[58]),
.I3(a[59]),
.O(sig00000583)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk00000585 (
.I0(b[27]),
.I1(b[26]),
.I2(a[26]),
.I3(a[27]),
.O(sig0000053d)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000586 (
.I0(b[58]),
.I1(a[58]),
.I2(b[59]),
.I3(a[59]),
.O(sig00000593)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000587 (
.I0(b[26]),
.I1(a[26]),
.I2(b[27]),
.I3(a[27]),
.O(sig0000054d)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000588 (
.I0(b[36]),
.I1(b[37]),
.I2(b[38]),
.I3(b[39]),
.I4(b[40]),
.I5(b[41]),
.O(sig00000496)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000589 (
.I0(a[36]),
.I1(a[37]),
.I2(a[38]),
.I3(a[39]),
.I4(a[40]),
.I5(a[41]),
.O(sig00000480)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk0000058a (
.I0(b[56]),
.I1(a[56]),
.I2(b[57]),
.I3(a[57]),
.I4(b[58]),
.I5(a[58]),
.O(sig0000056d)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk0000058b (
.I0(b[57]),
.I1(b[56]),
.I2(a[56]),
.I3(a[57]),
.O(sig00000582)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk0000058c (
.I0(b[25]),
.I1(b[24]),
.I2(a[24]),
.I3(a[25]),
.O(sig0000053c)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000058d (
.I0(b[56]),
.I1(a[56]),
.I2(b[57]),
.I3(a[57]),
.O(sig00000592)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000058e (
.I0(b[24]),
.I1(a[24]),
.I2(b[25]),
.I3(a[25]),
.O(sig0000054c)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000058f (
.I0(b[30]),
.I1(b[31]),
.I2(b[32]),
.I3(b[33]),
.I4(b[34]),
.I5(b[35]),
.O(sig00000495)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000590 (
.I0(a[30]),
.I1(a[31]),
.I2(a[32]),
.I3(a[33]),
.I4(a[34]),
.I5(a[35]),
.O(sig0000047f)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000591 (
.I0(b[53]),
.I1(a[53]),
.I2(b[54]),
.I3(a[54]),
.I4(b[55]),
.I5(a[55]),
.O(sig0000056c)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk00000592 (
.I0(b[55]),
.I1(b[54]),
.I2(a[54]),
.I3(a[55]),
.O(sig00000581)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk00000593 (
.I0(b[23]),
.I1(b[22]),
.I2(a[22]),
.I3(a[23]),
.O(sig0000053b)
);
LUT2 #(
.INIT ( 4'h8 ))
blk00000594 (
.I0(sig00000897),
.I1(sig0000067a),
.O(sig00000675)
);
LUT2 #(
.INIT ( 4'h8 ))
blk00000595 (
.I0(sig000004cf),
.I1(sig0000051a),
.O(sig000005d6)
);
LUT2 #(
.INIT ( 4'h4 ))
blk00000596 (
.I0(sig000004de),
.I1(sig000004dd),
.O(sig000005ba)
);
LUT2 #(
.INIT ( 4'h8 ))
blk00000597 (
.I0(sig00000454),
.I1(sig0000046c),
.O(sig000005a5)
);
LUT2 #(
.INIT ( 4'hE ))
blk00000598 (
.I0(sig00000486),
.I1(sig00000470),
.O(sig000008bc)
);
LUT2 #(
.INIT ( 4'hE ))
blk00000599 (
.I0(sig0000035a),
.I1(sig0000035d),
.O(sig000003df)
);
LUT2 #(
.INIT ( 4'h7 ))
blk0000059a (
.I0(sig00000320),
.I1(sig0000001d),
.O(sig00000143)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000059b (
.I0(sig0000046c),
.I1(sig00000454),
.O(sig000005aa)
);
LUT3 #(
.INIT ( 8'h57 ))
blk0000059c (
.I0(sig0000001d),
.I1(sig00000350),
.I2(sig0000034f),
.O(sig00000147)
);
LUT3 #(
.INIT ( 8'h57 ))
blk0000059d (
.I0(sig0000001d),
.I1(sig0000034b),
.I2(sig0000034a),
.O(sig00000146)
);
LUT3 #(
.INIT ( 8'h57 ))
blk0000059e (
.I0(sig0000001d),
.I1(sig00000347),
.I2(sig00000346),
.O(sig00000145)
);
LUT3 #(
.INIT ( 8'h57 ))
blk0000059f (
.I0(sig0000001d),
.I1(sig00000343),
.I2(sig00000341),
.O(sig00000144)
);
LUT3 #(
.INIT ( 8'h57 ))
blk000005a0 (
.I0(sig0000001d),
.I1(sig0000033e),
.I2(sig0000033d),
.O(sig00000150)
);
LUT3 #(
.INIT ( 8'h57 ))
blk000005a1 (
.I0(sig0000001d),
.I1(sig0000033a),
.I2(sig00000339),
.O(sig0000014f)
);
LUT3 #(
.INIT ( 8'h57 ))
blk000005a2 (
.I0(sig0000001d),
.I1(sig00000335),
.I2(sig00000334),
.O(sig0000014e)
);
LUT3 #(
.INIT ( 8'h57 ))
blk000005a3 (
.I0(sig0000001d),
.I1(sig00000331),
.I2(sig00000330),
.O(sig0000014d)
);
LUT3 #(
.INIT ( 8'h57 ))
blk000005a4 (
.I0(sig0000001d),
.I1(sig0000032d),
.I2(sig0000032b),
.O(sig0000014c)
);
LUT3 #(
.INIT ( 8'h57 ))
blk000005a5 (
.I0(sig0000001d),
.I1(sig00000328),
.I2(sig00000327),
.O(sig0000014b)
);
LUT3 #(
.INIT ( 8'h57 ))
blk000005a6 (
.I0(sig0000001d),
.I1(sig00000324),
.I2(sig00000323),
.O(sig0000014a)
);
LUT3 #(
.INIT ( 8'h57 ))
blk000005a7 (
.I0(sig0000001d),
.I1(sig00000354),
.I2(sig00000353),
.O(sig00000149)
);
LUT3 #(
.INIT ( 8'h57 ))
blk000005a8 (
.I0(sig0000001d),
.I1(sig00000342),
.I2(sig00000337),
.O(sig00000148)
);
LUT3 #(
.INIT ( 8'h02 ))
blk000005a9 (
.I0(sig00000059),
.I1(sig00000096),
.I2(sig00000095),
.O(sig000000c8)
);
LUT3 #(
.INIT ( 8'h02 ))
blk000005aa (
.I0(sig00000058),
.I1(sig00000096),
.I2(sig00000095),
.O(sig000000c7)
);
LUT3 #(
.INIT ( 8'h02 ))
blk000005ab (
.I0(sig00000057),
.I1(sig00000096),
.I2(sig00000095),
.O(sig000000c6)
);
LUT3 #(
.INIT ( 8'h02 ))
blk000005ac (
.I0(sig00000056),
.I1(sig00000096),
.I2(sig00000095),
.O(sig000000c5)
);
LUT4 #(
.INIT ( 16'hA8AA ))
blk000005ad (
.I0(sig000004d8),
.I1(sig000004de),
.I2(sig000004dd),
.I3(sig0000046d),
.O(sig000005eb)
);
LUT4 #(
.INIT ( 16'h22F2 ))
blk000005ae (
.I0(sig0000046f),
.I1(sig000005a6),
.I2(sig00000485),
.I3(sig000005ac),
.O(sig000005a9)
);
LUT4 #(
.INIT ( 16'hF888 ))
blk000005af (
.I0(sig00000485),
.I1(sig000005ac),
.I2(sig0000046f),
.I3(sig000005a6),
.O(sig000005a7)
);
LUT4 #(
.INIT ( 16'h8000 ))
blk000005b0 (
.I0(sig00000485),
.I1(sig000005ac),
.I2(sig0000046f),
.I3(sig000005a6),
.O(sig000005a4)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk000005b1 (
.I0(sig00000022),
.I1(sig00000021),
.I2(sig00000351),
.I3(sig0000033f),
.O(sig000000ed)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk000005b2 (
.I0(sig00000022),
.I1(sig00000021),
.I2(sig00000350),
.I3(sig0000033e),
.O(sig000000ec)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk000005b3 (
.I0(sig00000022),
.I1(sig00000021),
.I2(sig0000034f),
.I3(sig0000033d),
.O(sig000000eb)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk000005b4 (
.I0(sig00000022),
.I1(sig00000021),
.I2(sig0000034e),
.I3(sig0000033c),
.O(sig000000ea)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk000005b5 (
.I0(sig00000022),
.I1(sig00000021),
.I2(sig0000034c),
.I3(sig0000033b),
.O(sig000000e9)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk000005b6 (
.I0(sig00000022),
.I1(sig00000021),
.I2(sig0000034b),
.I3(sig0000033a),
.O(sig000000e8)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk000005b7 (
.I0(sig00000022),
.I1(sig00000021),
.I2(sig0000034a),
.I3(sig00000339),
.O(sig000000e7)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk000005b8 (
.I0(sig00000022),
.I1(sig00000021),
.I2(sig00000349),
.I3(sig00000338),
.O(sig000000e6)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk000005b9 (
.I0(sig00000022),
.I1(sig00000021),
.I2(sig00000348),
.I3(sig00000336),
.O(sig000000e5)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk000005ba (
.I0(sig00000022),
.I1(sig00000021),
.I2(sig00000347),
.I3(sig00000335),
.O(sig000000e3)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk000005bb (
.I0(sig00000022),
.I1(sig00000021),
.I2(sig00000346),
.I3(sig00000334),
.O(sig000000e2)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk000005bc (
.I0(sig00000022),
.I1(sig00000021),
.I2(sig00000345),
.I3(sig00000333),
.O(sig000000e1)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk000005bd (
.I0(sig00000022),
.I1(sig00000021),
.I2(sig00000344),
.I3(sig00000332),
.O(sig000000e0)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk000005be (
.I0(sig00000022),
.I1(sig00000021),
.I2(sig00000343),
.I3(sig00000331),
.O(sig000000df)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk000005bf (
.I0(sig00000022),
.I1(sig00000021),
.I2(sig00000341),
.I3(sig00000330),
.O(sig000000de)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk000005c0 (
.I0(sig00000022),
.I1(sig00000021),
.I2(sig00000340),
.I3(sig0000032f),
.O(sig000000dd)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk000005c1 (
.I0(sig00000096),
.I1(sig00000095),
.I2(sig00000059),
.I3(sig00000055),
.O(sig000000c4)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk000005c2 (
.I0(sig00000096),
.I1(sig00000095),
.I2(sig00000058),
.I3(sig00000053),
.O(sig000000c2)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk000005c3 (
.I0(sig00000096),
.I1(sig00000095),
.I2(sig00000057),
.I3(sig00000052),
.O(sig000000c1)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk000005c4 (
.I0(sig00000096),
.I1(sig00000095),
.I2(sig00000056),
.I3(sig00000051),
.O(sig000000c0)
);
LUT4 #(
.INIT ( 16'hEC4C ))
blk000005c5 (
.I0(sig0000046f),
.I1(sig0000046c),
.I2(sig000005a6),
.I3(sig00000454),
.O(sig000005a8)
);
LUT5 #(
.INIT ( 32'h55555554 ))
blk000005c6 (
.I0(sig000004dd),
.I1(sig0000046d),
.I2(sig000004de),
.I3(sig00000528),
.I4(sig0000051b),
.O(sig000005b9)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk000005c7 (
.I0(sig00000021),
.I1(sig00000022),
.I2(sig00000343),
.I3(sig00000354),
.I4(sig00000331),
.O(sig00000104)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk000005c8 (
.I0(sig00000021),
.I1(sig00000022),
.I2(sig00000341),
.I3(sig00000353),
.I4(sig00000330),
.O(sig00000103)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk000005c9 (
.I0(sig00000021),
.I1(sig00000022),
.I2(sig00000340),
.I3(sig00000352),
.I4(sig0000032f),
.O(sig00000102)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk000005ca (
.I0(sig00000021),
.I1(sig00000022),
.I2(sig00000351),
.I3(sig0000032e),
.I4(sig0000033f),
.O(sig000000dc)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk000005cb (
.I0(sig00000021),
.I1(sig00000022),
.I2(sig00000350),
.I3(sig0000032d),
.I4(sig0000033e),
.O(sig000000db)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk000005cc (
.I0(sig00000021),
.I1(sig00000022),
.I2(sig0000034f),
.I3(sig0000032b),
.I4(sig0000033d),
.O(sig000000da)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk000005cd (
.I0(sig00000021),
.I1(sig00000022),
.I2(sig0000034e),
.I3(sig0000032a),
.I4(sig0000033c),
.O(sig000000d8)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk000005ce (
.I0(sig00000021),
.I1(sig00000022),
.I2(sig0000034c),
.I3(sig00000329),
.I4(sig0000033b),
.O(sig000000d7)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk000005cf (
.I0(sig00000021),
.I1(sig00000022),
.I2(sig0000034b),
.I3(sig00000328),
.I4(sig0000033a),
.O(sig000000d6)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk000005d0 (
.I0(sig00000021),
.I1(sig00000022),
.I2(sig0000034a),
.I3(sig00000327),
.I4(sig00000339),
.O(sig000000d5)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk000005d1 (
.I0(sig00000021),
.I1(sig00000022),
.I2(sig00000349),
.I3(sig00000326),
.I4(sig00000338),
.O(sig000000d4)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk000005d2 (
.I0(sig00000021),
.I1(sig00000022),
.I2(sig00000348),
.I3(sig00000325),
.I4(sig00000336),
.O(sig000000d3)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk000005d3 (
.I0(sig00000021),
.I1(sig00000022),
.I2(sig00000347),
.I3(sig00000324),
.I4(sig00000335),
.O(sig000000d2)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk000005d4 (
.I0(sig00000021),
.I1(sig00000022),
.I2(sig00000346),
.I3(sig00000323),
.I4(sig00000334),
.O(sig000000d1)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk000005d5 (
.I0(sig00000021),
.I1(sig00000022),
.I2(sig00000345),
.I3(sig00000322),
.I4(sig00000333),
.O(sig000000d0)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk000005d6 (
.I0(sig00000021),
.I1(sig00000022),
.I2(sig00000344),
.I3(sig00000355),
.I4(sig00000332),
.O(sig000000cf)
);
LUT5 #(
.INIT ( 32'hEC64A820 ))
blk000005d7 (
.I0(sig00000022),
.I1(sig00000021),
.I2(sig00000339),
.I3(sig0000034a),
.I4(sig00000327),
.O(sig000000ce)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk000005d8 (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000059),
.I3(sig00000050),
.I4(sig00000055),
.O(sig000000bf)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk000005d9 (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000058),
.I3(sig0000004f),
.I4(sig00000053),
.O(sig000000be)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk000005da (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000057),
.I3(sig0000004e),
.I4(sig00000052),
.O(sig000000bd)
);
LUT5 #(
.INIT ( 32'h73625140 ))
blk000005db (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000056),
.I3(sig0000004d),
.I4(sig00000051),
.O(sig000000bc)
);
LUT6 #(
.INIT ( 64'hFFFFFFFF55555554 ))
blk000005dc (
.I0(sig000004dd),
.I1(sig0000046d),
.I2(sig0000051c),
.I3(sig00000528),
.I4(sig0000051b),
.I5(sig000004de),
.O(sig000005ed)
);
LUT6 #(
.INIT ( 64'hAAAAAAAAAAAAABAA ))
blk000005dd (
.I0(sig000004dd),
.I1(sig000004de),
.I2(sig0000046d),
.I3(sig0000051c),
.I4(sig00000528),
.I5(sig0000051b),
.O(sig000005ec)
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFFFFFFFE ))
blk000005de (
.I0(sig0000046d),
.I1(sig0000051c),
.I2(sig00000528),
.I3(sig0000051b),
.I4(sig000004dd),
.I5(sig000004de),
.O(sig000004ec)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005df (
.I0(sig00000021),
.I1(sig00000022),
.I2(sig00000351),
.I3(sig0000033f),
.I4(sig0000034d),
.I5(sig0000032e),
.O(sig00000101)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005e0 (
.I0(sig00000021),
.I1(sig00000022),
.I2(sig00000350),
.I3(sig0000033e),
.I4(sig00000342),
.I5(sig0000032d),
.O(sig00000100)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005e1 (
.I0(sig00000021),
.I1(sig00000022),
.I2(sig0000034f),
.I3(sig0000033d),
.I4(sig00000337),
.I5(sig0000032b),
.O(sig000000fa)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005e2 (
.I0(sig00000021),
.I1(sig00000022),
.I2(sig0000034e),
.I3(sig0000033c),
.I4(sig0000032c),
.I5(sig0000032a),
.O(sig000000ef)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005e3 (
.I0(sig00000021),
.I1(sig00000022),
.I2(sig0000034c),
.I3(sig0000033b),
.I4(sig00000321),
.I5(sig00000329),
.O(sig000000e4)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005e4 (
.I0(sig00000021),
.I1(sig00000022),
.I2(sig0000034b),
.I3(sig0000033a),
.I4(sig00000320),
.I5(sig00000328),
.O(sig000000d9)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005e5 (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000035),
.I3(sig00000030),
.I4(sig0000005d),
.I5(sig0000002c),
.O(sig000000cd)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005e6 (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000034),
.I3(sig0000002f),
.I4(sig0000005c),
.I5(sig0000002b),
.O(sig000000cc)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005e7 (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000032),
.I3(sig0000002e),
.I4(sig0000005b),
.I5(sig0000002a),
.O(sig000000cb)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005e8 (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000031),
.I3(sig0000002d),
.I4(sig0000005a),
.I5(sig00000029),
.O(sig000000ca)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005e9 (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000030),
.I3(sig0000002c),
.I4(sig00000054),
.I5(sig0000005d),
.O(sig000000c9)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005ea (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig0000002f),
.I3(sig0000002b),
.I4(sig00000049),
.I5(sig0000005c),
.O(sig000000c3)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005eb (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000059),
.I3(sig00000055),
.I4(sig0000004c),
.I5(sig00000050),
.O(sig000000bb)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005ec (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000058),
.I3(sig00000053),
.I4(sig0000004b),
.I5(sig0000004f),
.O(sig000000ba)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005ed (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000057),
.I3(sig00000052),
.I4(sig0000004a),
.I5(sig0000004e),
.O(sig000000b9)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005ee (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig0000002e),
.I3(sig0000002a),
.I4(sig0000003e),
.I5(sig0000005b),
.O(sig000000b8)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005ef (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000056),
.I3(sig00000051),
.I4(sig00000048),
.I5(sig0000004d),
.O(sig000000b7)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005f0 (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000055),
.I3(sig00000050),
.I4(sig00000047),
.I5(sig0000004c),
.O(sig000000b6)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005f1 (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000053),
.I3(sig0000004f),
.I4(sig00000046),
.I5(sig0000004b),
.O(sig000000b5)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005f2 (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000052),
.I3(sig0000004e),
.I4(sig00000045),
.I5(sig0000004a),
.O(sig000000b4)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005f3 (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000051),
.I3(sig0000004d),
.I4(sig00000044),
.I5(sig00000048),
.O(sig000000b3)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005f4 (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000050),
.I3(sig0000004c),
.I4(sig00000043),
.I5(sig00000047),
.O(sig000000b2)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005f5 (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig0000004f),
.I3(sig0000004b),
.I4(sig00000042),
.I5(sig00000046),
.O(sig000000b1)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005f6 (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig0000004e),
.I3(sig0000004a),
.I4(sig00000041),
.I5(sig00000045),
.O(sig000000b0)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005f7 (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig0000004d),
.I3(sig00000048),
.I4(sig00000040),
.I5(sig00000044),
.O(sig000000af)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005f8 (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig0000004c),
.I3(sig00000047),
.I4(sig0000003f),
.I5(sig00000043),
.O(sig000000ae)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005f9 (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig0000002d),
.I3(sig00000029),
.I4(sig00000033),
.I5(sig0000005a),
.O(sig000000ad)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005fa (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig0000004b),
.I3(sig00000046),
.I4(sig0000003d),
.I5(sig00000042),
.O(sig000000ac)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005fb (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig0000004a),
.I3(sig00000045),
.I4(sig0000003c),
.I5(sig00000041),
.O(sig000000ab)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005fc (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000048),
.I3(sig00000044),
.I4(sig0000003b),
.I5(sig00000040),
.O(sig000000aa)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005fd (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000047),
.I3(sig00000043),
.I4(sig0000003a),
.I5(sig0000003f),
.O(sig000000a9)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005fe (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000046),
.I3(sig00000042),
.I4(sig00000039),
.I5(sig0000003d),
.O(sig000000a8)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk000005ff (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000045),
.I3(sig00000041),
.I4(sig00000038),
.I5(sig0000003c),
.O(sig000000a7)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk00000600 (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000044),
.I3(sig00000040),
.I4(sig00000037),
.I5(sig0000003b),
.O(sig000000a6)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk00000601 (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000043),
.I3(sig0000003f),
.I4(sig00000036),
.I5(sig0000003a),
.O(sig000000a5)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk00000602 (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000042),
.I3(sig0000003d),
.I4(sig00000035),
.I5(sig00000039),
.O(sig000000a4)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk00000603 (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000041),
.I3(sig0000003c),
.I4(sig00000034),
.I5(sig00000038),
.O(sig000000a3)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk00000604 (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig0000002c),
.I3(sig0000005d),
.I4(sig00000028),
.I5(sig00000054),
.O(sig000000a2)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk00000605 (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000040),
.I3(sig0000003b),
.I4(sig00000032),
.I5(sig00000037),
.O(sig000000a1)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk00000606 (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig0000003f),
.I3(sig0000003a),
.I4(sig00000031),
.I5(sig00000036),
.O(sig000000a0)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk00000607 (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig0000003d),
.I3(sig00000039),
.I4(sig00000030),
.I5(sig00000035),
.O(sig0000009f)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk00000608 (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig0000003c),
.I3(sig00000038),
.I4(sig0000002f),
.I5(sig00000034),
.O(sig0000009e)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk00000609 (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig0000003b),
.I3(sig00000037),
.I4(sig0000002e),
.I5(sig00000032),
.O(sig0000009d)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk0000060a (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig0000003a),
.I3(sig00000036),
.I4(sig0000002d),
.I5(sig00000031),
.O(sig0000009c)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk0000060b (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000039),
.I3(sig00000035),
.I4(sig0000002c),
.I5(sig00000030),
.O(sig0000009b)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk0000060c (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000038),
.I3(sig00000034),
.I4(sig0000002b),
.I5(sig0000002f),
.O(sig0000009a)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk0000060d (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000037),
.I3(sig00000032),
.I4(sig0000002a),
.I5(sig0000002e),
.O(sig00000099)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk0000060e (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig00000036),
.I3(sig00000031),
.I4(sig00000029),
.I5(sig0000002d),
.O(sig00000098)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk0000060f (
.I0(sig00000095),
.I1(sig00000096),
.I2(sig0000002b),
.I3(sig0000005c),
.I4(sig00000027),
.I5(sig00000049),
.O(sig00000097)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000610 (
.I0(b[54]),
.I1(a[54]),
.I2(b[55]),
.I3(a[55]),
.O(sig00000591)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000611 (
.I0(b[22]),
.I1(a[22]),
.I2(b[23]),
.I3(a[23]),
.O(sig0000054b)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000612 (
.I0(b[24]),
.I1(b[25]),
.I2(b[26]),
.I3(b[27]),
.I4(b[28]),
.I5(b[29]),
.O(sig00000494)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000613 (
.I0(a[24]),
.I1(a[25]),
.I2(a[26]),
.I3(a[27]),
.I4(a[28]),
.I5(a[29]),
.O(sig0000047e)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000614 (
.I0(b[50]),
.I1(a[50]),
.I2(b[51]),
.I3(a[51]),
.I4(b[52]),
.I5(a[52]),
.O(sig0000056b)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk00000615 (
.I0(b[53]),
.I1(b[52]),
.I2(a[52]),
.I3(a[53]),
.O(sig00000580)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk00000616 (
.I0(b[21]),
.I1(b[20]),
.I2(a[20]),
.I3(a[21]),
.O(sig0000053a)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000617 (
.I0(b[52]),
.I1(a[52]),
.I2(b[53]),
.I3(a[53]),
.O(sig00000590)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000618 (
.I0(b[20]),
.I1(a[20]),
.I2(b[21]),
.I3(a[21]),
.O(sig0000054a)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000619 (
.I0(b[18]),
.I1(b[19]),
.I2(b[20]),
.I3(b[21]),
.I4(b[22]),
.I5(b[23]),
.O(sig00000493)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000061a (
.I0(a[18]),
.I1(a[19]),
.I2(a[20]),
.I3(a[21]),
.I4(a[22]),
.I5(a[23]),
.O(sig0000047d)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk0000061b (
.I0(b[47]),
.I1(a[47]),
.I2(b[48]),
.I3(a[48]),
.I4(b[49]),
.I5(a[49]),
.O(sig0000056a)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk0000061c (
.I0(b[51]),
.I1(b[50]),
.I2(a[50]),
.I3(a[51]),
.O(sig0000058e)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk0000061d (
.I0(b[19]),
.I1(b[18]),
.I2(a[18]),
.I3(a[19]),
.O(sig00000548)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000061e (
.I0(b[50]),
.I1(a[50]),
.I2(b[51]),
.I3(a[51]),
.O(sig0000059e)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000061f (
.I0(b[18]),
.I1(a[18]),
.I2(b[19]),
.I3(a[19]),
.O(sig00000558)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000620 (
.I0(b[12]),
.I1(b[13]),
.I2(b[14]),
.I3(b[15]),
.I4(b[16]),
.I5(b[17]),
.O(sig00000492)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000621 (
.I0(a[12]),
.I1(a[13]),
.I2(a[14]),
.I3(a[15]),
.I4(a[16]),
.I5(a[17]),
.O(sig0000047c)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000622 (
.I0(b[44]),
.I1(a[44]),
.I2(b[45]),
.I3(a[45]),
.I4(b[46]),
.I5(a[46]),
.O(sig00000569)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk00000623 (
.I0(b[49]),
.I1(b[48]),
.I2(a[48]),
.I3(a[49]),
.O(sig0000058d)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk00000624 (
.I0(b[17]),
.I1(b[16]),
.I2(a[16]),
.I3(a[17]),
.O(sig00000547)
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFFFFFFFE ))
blk00000625 (
.I0(b[57]),
.I1(b[56]),
.I2(b[55]),
.I3(b[54]),
.I4(b[53]),
.I5(b[52]),
.O(sig00000008)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000626 (
.I0(b[62]),
.I1(b[61]),
.I2(b[60]),
.I3(b[59]),
.I4(b[58]),
.I5(sig00000008),
.O(sig0000049a)
);
LUT6 #(
.INIT ( 64'h8000000000000000 ))
blk00000627 (
.I0(b[57]),
.I1(b[56]),
.I2(b[55]),
.I3(b[54]),
.I4(b[53]),
.I5(b[52]),
.O(sig00000013)
);
LUT6 #(
.INIT ( 64'h8000000000000000 ))
blk00000628 (
.I0(b[62]),
.I1(b[61]),
.I2(b[60]),
.I3(b[59]),
.I4(b[58]),
.I5(sig00000013),
.O(sig00000499)
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFFFFFFFE ))
blk00000629 (
.I0(a[57]),
.I1(a[56]),
.I2(a[55]),
.I3(a[54]),
.I4(a[53]),
.I5(a[52]),
.O(sig0000001a)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000062a (
.I0(a[62]),
.I1(a[61]),
.I2(a[60]),
.I3(a[59]),
.I4(a[58]),
.I5(sig0000001a),
.O(sig00000484)
);
LUT6 #(
.INIT ( 64'h8000000000000000 ))
blk0000062b (
.I0(a[57]),
.I1(a[56]),
.I2(a[55]),
.I3(a[54]),
.I4(a[53]),
.I5(a[52]),
.O(sig0000001b)
);
LUT6 #(
.INIT ( 64'h8000000000000000 ))
blk0000062c (
.I0(a[62]),
.I1(a[61]),
.I2(a[60]),
.I3(a[59]),
.I4(a[58]),
.I5(sig0000001b),
.O(sig00000483)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000062d (
.I0(b[48]),
.I1(a[48]),
.I2(b[49]),
.I3(a[49]),
.O(sig0000059d)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000062e (
.I0(b[16]),
.I1(a[16]),
.I2(b[17]),
.I3(a[17]),
.O(sig00000557)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000062f (
.I0(b[6]),
.I1(b[7]),
.I2(b[8]),
.I3(b[9]),
.I4(b[10]),
.I5(b[11]),
.O(sig00000491)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000630 (
.I0(a[6]),
.I1(a[7]),
.I2(a[8]),
.I3(a[9]),
.I4(a[10]),
.I5(a[11]),
.O(sig0000047b)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000631 (
.I0(b[41]),
.I1(a[41]),
.I2(b[42]),
.I3(a[42]),
.I4(b[43]),
.I5(a[43]),
.O(sig00000568)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk00000632 (
.I0(b[47]),
.I1(b[46]),
.I2(a[46]),
.I3(a[47]),
.O(sig0000058c)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk00000633 (
.I0(b[15]),
.I1(b[14]),
.I2(a[14]),
.I3(a[15]),
.O(sig00000546)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000634 (
.I0(b[46]),
.I1(a[46]),
.I2(b[47]),
.I3(a[47]),
.O(sig0000059c)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000635 (
.I0(b[14]),
.I1(a[14]),
.I2(b[15]),
.I3(a[15]),
.O(sig00000556)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000636 (
.I0(b[0]),
.I1(b[1]),
.I2(b[2]),
.I3(b[3]),
.I4(b[4]),
.I5(b[5]),
.O(sig00000490)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000637 (
.I0(a[0]),
.I1(a[1]),
.I2(a[2]),
.I3(a[3]),
.I4(a[4]),
.I5(a[5]),
.O(sig0000047a)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000638 (
.I0(b[38]),
.I1(a[38]),
.I2(b[39]),
.I3(a[39]),
.I4(b[40]),
.I5(a[40]),
.O(sig00000567)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk00000639 (
.I0(b[45]),
.I1(b[44]),
.I2(a[44]),
.I3(a[45]),
.O(sig0000058b)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk0000063a (
.I0(b[13]),
.I1(b[12]),
.I2(a[12]),
.I3(a[13]),
.O(sig00000545)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000063b (
.I0(b[44]),
.I1(a[44]),
.I2(b[45]),
.I3(a[45]),
.O(sig0000059b)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000063c (
.I0(b[12]),
.I1(a[12]),
.I2(b[13]),
.I3(a[13]),
.O(sig00000555)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk0000063d (
.I0(b[35]),
.I1(a[35]),
.I2(b[36]),
.I3(a[36]),
.I4(b[37]),
.I5(a[37]),
.O(sig00000566)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk0000063e (
.I0(b[43]),
.I1(b[42]),
.I2(a[42]),
.I3(a[43]),
.O(sig0000058a)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk0000063f (
.I0(b[11]),
.I1(b[10]),
.I2(a[10]),
.I3(a[11]),
.O(sig00000544)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000640 (
.I0(b[42]),
.I1(a[42]),
.I2(b[43]),
.I3(a[43]),
.O(sig0000059a)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000641 (
.I0(b[10]),
.I1(a[10]),
.I2(b[11]),
.I3(a[11]),
.O(sig00000554)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000642 (
.I0(b[32]),
.I1(a[32]),
.I2(b[33]),
.I3(a[33]),
.I4(b[34]),
.I5(a[34]),
.O(sig00000564)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000643 (
.I0(sig00000458),
.I1(sig00000457),
.O(sig0000035f)
);
LUT3 #(
.INIT ( 8'h54 ))
blk00000644 (
.I0(sig0000049c),
.I1(sig0000049b),
.I2(sig000004e3),
.O(sig000008a4)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk00000645 (
.I0(b[41]),
.I1(b[40]),
.I2(a[40]),
.I3(a[41]),
.O(sig00000589)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk00000646 (
.I0(b[9]),
.I1(b[8]),
.I2(a[8]),
.I3(a[9]),
.O(sig00000543)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000647 (
.I0(b[40]),
.I1(a[40]),
.I2(b[41]),
.I3(a[41]),
.O(sig00000599)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000648 (
.I0(b[8]),
.I1(a[8]),
.I2(b[9]),
.I3(a[9]),
.O(sig00000553)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk00000649 (
.I0(b[39]),
.I1(b[38]),
.I2(a[38]),
.I3(a[39]),
.O(sig00000588)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk0000064a (
.I0(b[7]),
.I1(b[6]),
.I2(a[6]),
.I3(a[7]),
.O(sig00000542)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000064b (
.I0(b[38]),
.I1(a[38]),
.I2(b[39]),
.I3(a[39]),
.O(sig00000598)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000064c (
.I0(b[6]),
.I1(a[6]),
.I2(b[7]),
.I3(a[7]),
.O(sig00000552)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk0000064d (
.I0(b[37]),
.I1(b[36]),
.I2(a[36]),
.I3(a[37]),
.O(sig00000587)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk0000064e (
.I0(b[5]),
.I1(b[4]),
.I2(a[4]),
.I3(a[5]),
.O(sig00000541)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000064f (
.I0(b[36]),
.I1(a[36]),
.I2(b[37]),
.I3(a[37]),
.O(sig00000597)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000650 (
.I0(b[4]),
.I1(a[4]),
.I2(b[5]),
.I3(a[5]),
.O(sig00000551)
);
LUT2 #(
.INIT ( 4'h8 ))
blk00000651 (
.I0(sig0000067d),
.I1(sig00000897),
.O(sig00000653)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000652 (
.I0(sig0000064c),
.I1(sig0000062f),
.I2(sig0000062d),
.O(sig00000660)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000653 (
.I0(sig0000064c),
.I1(sig0000062e),
.I2(sig0000062c),
.O(sig0000065f)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000654 (
.I0(sig0000067d),
.I1(sig00000680),
.I2(sig0000067c),
.O(sig00000652)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000655 (
.I0(sig0000067d),
.I1(sig0000067f),
.I2(sig0000067b),
.O(sig00000651)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000656 (
.I0(sig0000067d),
.I1(sig0000067e),
.I2(sig00000676),
.O(sig00000650)
);
LUT2 #(
.INIT ( 4'h4 ))
blk00000657 (
.I0(sig00000678),
.I1(sig00000677),
.O(sig00000656)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000658 (
.I0(sig0000064e),
.I1(sig00000633),
.I2(sig00000631),
.O(sig00000662)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000659 (
.I0(sig0000064e),
.I1(sig00000632),
.I2(sig00000630),
.O(sig00000661)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk0000065a (
.I0(sig00000678),
.I1(sig0000067a),
.I2(sig00000682),
.O(sig00000655)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk0000065b (
.I0(sig00000678),
.I1(sig00000679),
.I2(sig00000681),
.O(sig00000654)
);
LUT5 #(
.INIT ( 32'h01010100 ))
blk0000065c (
.I0(sig00000678),
.I1(sig000005f1),
.I2(sig000005f2),
.I3(sig00000625),
.I4(sig00000626),
.O(sig00000643)
);
LUT5 #(
.INIT ( 32'h11110010 ))
blk0000065d (
.I0(sig00000678),
.I1(sig000005f2),
.I2(sig00000625),
.I3(sig00000626),
.I4(sig000005f1),
.O(sig00000642)
);
LUT5 #(
.INIT ( 32'h01010100 ))
blk0000065e (
.I0(sig00000678),
.I1(sig000005f5),
.I2(sig000005f6),
.I3(sig000005f3),
.I4(sig000005f4),
.O(sig00000641)
);
LUT5 #(
.INIT ( 32'h11110010 ))
blk0000065f (
.I0(sig00000678),
.I1(sig000005f6),
.I2(sig000005f3),
.I3(sig000005f4),
.I4(sig000005f5),
.O(sig00000640)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk00000660 (
.I0(b[35]),
.I1(b[34]),
.I2(a[34]),
.I3(a[35]),
.O(sig00000586)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk00000661 (
.I0(b[3]),
.I1(b[2]),
.I2(a[2]),
.I3(a[3]),
.O(sig00000540)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000662 (
.I0(b[34]),
.I1(a[34]),
.I2(b[35]),
.I3(a[35]),
.O(sig00000596)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000663 (
.I0(b[2]),
.I1(a[2]),
.I2(b[3]),
.I3(a[3]),
.O(sig00000550)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk00000664 (
.I0(b[33]),
.I1(b[32]),
.I2(a[32]),
.I3(a[33]),
.O(sig0000057f)
);
LUT4 #(
.INIT ( 16'h08AE ))
blk00000665 (
.I0(b[1]),
.I1(b[0]),
.I2(a[0]),
.I3(a[1]),
.O(sig00000539)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000666 (
.I0(b[32]),
.I1(a[32]),
.I2(b[33]),
.I3(a[33]),
.O(sig0000058f)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000667 (
.I0(b[0]),
.I1(a[0]),
.I2(b[1]),
.I3(a[1]),
.O(sig00000549)
);
LUT3 #(
.INIT ( 8'h01 ))
blk00000668 (
.I0(sig0000034f),
.I1(sig00000350),
.I2(sig00000351),
.O(sig00000117)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000669 (
.I0(sig000002a0),
.I1(sig00000225),
.I2(sig00000224),
.I3(sig00000223),
.O(sig0000068e)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk0000066a (
.I0(sig00000226),
.I1(sig0000021e),
.I2(sig00000213),
.I3(sig00000212),
.O(sig00000687)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk0000066b (
.I0(sig000002b7),
.I1(sig000002b6),
.I2(sig000002ac),
.I3(sig000002a1),
.O(sig0000068d)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk0000066c (
.I0(sig0000022a),
.I1(sig00000229),
.I2(sig00000228),
.I3(sig00000227),
.O(sig00000686)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk0000066d (
.I0(sig0000034a),
.I1(sig0000034b),
.I2(sig0000034c),
.I3(sig0000034e),
.O(sig00000116)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk0000066e (
.I0(sig000002bb),
.I1(sig000002ba),
.I2(sig000002b9),
.I3(sig000002b8),
.O(sig0000068c)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk0000066f (
.I0(sig00000215),
.I1(sig00000214),
.I2(sig0000022c),
.I3(sig0000022b),
.O(sig00000685)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000670 (
.I0(sig00000346),
.I1(sig00000347),
.I2(sig00000348),
.I3(sig00000349),
.O(sig00000115)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000671 (
.I0(sig000002a4),
.I1(sig000002a3),
.I2(sig000002a2),
.I3(sig000002bc),
.O(sig0000068b)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000672 (
.I0(sig00000219),
.I1(sig00000218),
.I2(sig00000217),
.I3(sig00000216),
.O(sig00000684)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000673 (
.I0(sig00000341),
.I1(sig00000343),
.I2(sig00000344),
.I3(sig00000345),
.O(sig00000114)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000674 (
.I0(sig0000021d),
.I1(sig0000021c),
.I2(sig0000021b),
.I3(sig0000021a),
.O(sig00000690)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000675 (
.I0(sig000002a8),
.I1(sig000002a7),
.I2(sig000002a6),
.I3(sig000002a5),
.O(sig0000068a)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000676 (
.I0(sig0000033d),
.I1(sig0000033e),
.I2(sig0000033f),
.I3(sig00000340),
.O(sig00000120)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000677 (
.I0(sig00000222),
.I1(sig00000221),
.I2(sig00000220),
.I3(sig0000021f),
.O(sig0000068f)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000678 (
.I0(sig000002ad),
.I1(sig000002ab),
.I2(sig000002aa),
.I3(sig000002a9),
.O(sig00000689)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000679 (
.I0(sig00000339),
.I1(sig0000033a),
.I2(sig0000033b),
.I3(sig0000033c),
.O(sig0000011f)
);
LUT4 #(
.INIT ( 16'hFFAB ))
blk0000067a (
.I0(sig00000603),
.I1(sig00000601),
.I2(sig00000600),
.I3(sig00000602),
.O(sig00000003)
);
LUT6 #(
.INIT ( 64'h01010100ABABABAA ))
blk0000067b (
.I0(sig0000067d),
.I1(sig00000614),
.I2(sig00000615),
.I3(sig00000612),
.I4(sig00000613),
.I5(sig00000003),
.O(sig0000063b)
);
LUT4 #(
.INIT ( 16'hBBAB ))
blk0000067c (
.I0(sig00000603),
.I1(sig00000602),
.I2(sig00000600),
.I3(sig00000601),
.O(sig00000004)
);
LUT6 #(
.INIT ( 64'h05050100AFAFABAA ))
blk0000067d (
.I0(sig0000067d),
.I1(sig00000613),
.I2(sig00000615),
.I3(sig00000612),
.I4(sig00000614),
.I5(sig00000004),
.O(sig0000063a)
);
LUT4 #(
.INIT ( 16'hFFAB ))
blk0000067e (
.I0(sig00000608),
.I1(sig00000605),
.I2(sig00000604),
.I3(sig00000607),
.O(sig00000005)
);
LUT6 #(
.INIT ( 64'h01010100ABABABAA ))
blk0000067f (
.I0(sig0000067d),
.I1(sig00000618),
.I2(sig00000619),
.I3(sig00000616),
.I4(sig00000617),
.I5(sig00000005),
.O(sig00000639)
);
LUT4 #(
.INIT ( 16'hBBAB ))
blk00000680 (
.I0(sig00000608),
.I1(sig00000607),
.I2(sig00000604),
.I3(sig00000605),
.O(sig00000006)
);
LUT6 #(
.INIT ( 64'h05050100AFAFABAA ))
blk00000681 (
.I0(sig0000067d),
.I1(sig00000617),
.I2(sig00000619),
.I3(sig00000616),
.I4(sig00000618),
.I5(sig00000006),
.O(sig00000638)
);
LUT4 #(
.INIT ( 16'hFFAB ))
blk00000682 (
.I0(sig0000060c),
.I1(sig0000060a),
.I2(sig00000609),
.I3(sig0000060b),
.O(sig00000007)
);
LUT6 #(
.INIT ( 64'h01010100ABABABAA ))
blk00000683 (
.I0(sig0000067d),
.I1(sig0000061d),
.I2(sig0000061e),
.I3(sig0000061a),
.I4(sig0000061b),
.I5(sig00000007),
.O(sig00000637)
);
LUT4 #(
.INIT ( 16'hBBAB ))
blk00000684 (
.I0(sig0000060c),
.I1(sig0000060b),
.I2(sig00000609),
.I3(sig0000060a),
.O(sig00000009)
);
LUT6 #(
.INIT ( 64'h05050100AFAFABAA ))
blk00000685 (
.I0(sig0000067d),
.I1(sig0000061b),
.I2(sig0000061e),
.I3(sig0000061a),
.I4(sig0000061d),
.I5(sig00000009),
.O(sig00000636)
);
LUT4 #(
.INIT ( 16'hFFAB ))
blk00000686 (
.I0(sig00000610),
.I1(sig0000060e),
.I2(sig0000060d),
.I3(sig0000060f),
.O(sig0000000a)
);
LUT6 #(
.INIT ( 64'h01010100ABABABAA ))
blk00000687 (
.I0(sig0000067d),
.I1(sig00000621),
.I2(sig00000622),
.I3(sig0000061f),
.I4(sig00000620),
.I5(sig0000000a),
.O(sig00000635)
);
LUT4 #(
.INIT ( 16'hBBAB ))
blk00000688 (
.I0(sig00000610),
.I1(sig0000060f),
.I2(sig0000060d),
.I3(sig0000060e),
.O(sig0000000b)
);
LUT6 #(
.INIT ( 64'h05050100AFAFABAA ))
blk00000689 (
.I0(sig0000067d),
.I1(sig00000620),
.I2(sig00000622),
.I3(sig0000061f),
.I4(sig00000621),
.I5(sig0000000b),
.O(sig00000634)
);
LUT4 #(
.INIT ( 16'hFFAB ))
blk0000068a (
.I0(sig000005f9),
.I1(sig000005f8),
.I2(sig000005f7),
.I3(sig000005fa),
.O(sig0000000c)
);
LUT6 #(
.INIT ( 64'h0202020057575755 ))
blk0000068b (
.I0(sig00000678),
.I1(sig000005fb),
.I2(sig00000606),
.I3(sig000005f0),
.I4(sig000005ef),
.I5(sig0000000c),
.O(sig0000063f)
);
LUT4 #(
.INIT ( 16'hBBAB ))
blk0000068c (
.I0(sig000005fa),
.I1(sig000005f9),
.I2(sig000005f7),
.I3(sig000005f8),
.O(sig0000000d)
);
LUT6 #(
.INIT ( 64'h0A0A02005F5F5755 ))
blk0000068d (
.I0(sig00000678),
.I1(sig000005f0),
.I2(sig00000606),
.I3(sig000005ef),
.I4(sig000005fb),
.I5(sig0000000d),
.O(sig0000063e)
);
LUT4 #(
.INIT ( 16'hFFAB ))
blk0000068e (
.I0(sig000005fe),
.I1(sig000005fd),
.I2(sig000005fc),
.I3(sig000005ff),
.O(sig0000000e)
);
LUT6 #(
.INIT ( 64'h0202020057575755 ))
blk0000068f (
.I0(sig00000678),
.I1(sig00000623),
.I2(sig00000624),
.I3(sig0000061c),
.I4(sig00000611),
.I5(sig0000000e),
.O(sig0000063d)
);
LUT4 #(
.INIT ( 16'hBBAB ))
blk00000690 (
.I0(sig000005ff),
.I1(sig000005fe),
.I2(sig000005fc),
.I3(sig000005fd),
.O(sig0000000f)
);
LUT6 #(
.INIT ( 64'h0A0A02005F5F5755 ))
blk00000691 (
.I0(sig00000678),
.I1(sig0000061c),
.I2(sig00000624),
.I3(sig00000611),
.I4(sig00000623),
.I5(sig0000000f),
.O(sig0000063c)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000692 (
.I0(sig000002b1),
.I1(sig000002b0),
.I2(sig000002af),
.I3(sig000002ae),
.O(sig00000688)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000693 (
.I0(sig00000334),
.I1(sig00000335),
.I2(sig00000336),
.I3(sig00000338),
.O(sig0000011e)
);
LUT2 #(
.INIT ( 4'h8 ))
blk00000694 (
.I0(sig00000486),
.I1(sig00000470),
.O(sig000008bb)
);
LUT3 #(
.INIT ( 8'hEA ))
blk00000695 (
.I0(sig000005a1),
.I1(sig0000059f),
.I2(sig000005a0),
.O(sig000008ba)
);
LUT3 #(
.INIT ( 8'hAC ))
blk00000696 (
.I0(sig0000064e),
.I1(sig0000064c),
.I2(sig0000064d),
.O(sig00000895)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk00000697 (
.I0(sig000006c7),
.I1(sig00000695),
.I2(sig00000699),
.I3(sig0000069e),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig00000735)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk00000698 (
.I0(sig000006c6),
.I1(sig00000694),
.I2(sig00000698),
.I3(sig0000069d),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig00000734)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk00000699 (
.I0(sig000006c5),
.I1(sig00000693),
.I2(sig00000697),
.I3(sig0000069b),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig00000733)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk0000069a (
.I0(sig000006c4),
.I1(sig00000692),
.I2(sig00000696),
.I3(sig0000069a),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig00000732)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk0000069b (
.I0(sig000006bd),
.I1(sig000006c7),
.I2(sig00000695),
.I3(sig00000699),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig00000731)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk0000069c (
.I0(sig000006b2),
.I1(sig000006c6),
.I2(sig00000694),
.I3(sig00000698),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig0000072a)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk0000069d (
.I0(sig000006ba),
.I1(sig000006b6),
.I2(sig000006bf),
.I3(sig000006c3),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig00000723)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk0000069e (
.I0(sig000006b9),
.I1(sig000006b5),
.I2(sig000006be),
.I3(sig000006c2),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig00000722)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk0000069f (
.I0(sig000006b8),
.I1(sig000006b4),
.I2(sig000006bc),
.I3(sig000006c1),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig00000721)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006a0 (
.I0(sig000006b7),
.I1(sig000006b3),
.I2(sig000006bb),
.I3(sig000006c0),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig00000720)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk000006a1 (
.I0(sig000006a7),
.I1(sig000006c5),
.I2(sig00000693),
.I3(sig00000697),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig0000071f)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006a2 (
.I0(sig000006b6),
.I1(sig000006b1),
.I2(sig000006ba),
.I3(sig000006bf),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig0000071e)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006a3 (
.I0(sig000006b5),
.I1(sig000006b0),
.I2(sig000006b9),
.I3(sig000006be),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig0000071d)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006a4 (
.I0(sig000006b4),
.I1(sig000006af),
.I2(sig000006b8),
.I3(sig000006bc),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig0000071c)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006a5 (
.I0(sig000006b3),
.I1(sig000006ae),
.I2(sig000006b7),
.I3(sig000006bb),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig0000071b)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006a6 (
.I0(sig000006b1),
.I1(sig000006ad),
.I2(sig000006b6),
.I3(sig000006ba),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig0000071a)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006a7 (
.I0(sig000006b0),
.I1(sig000006ac),
.I2(sig000006b5),
.I3(sig000006b9),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig00000719)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006a8 (
.I0(sig000006af),
.I1(sig000006ab),
.I2(sig000006b4),
.I3(sig000006b8),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig00000718)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006a9 (
.I0(sig000006ae),
.I1(sig000006aa),
.I2(sig000006b3),
.I3(sig000006b7),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig00000717)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006aa (
.I0(sig000006ad),
.I1(sig000006a9),
.I2(sig000006b1),
.I3(sig000006b6),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig00000716)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006ab (
.I0(sig000006ac),
.I1(sig000006a8),
.I2(sig000006b0),
.I3(sig000006b5),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig00000715)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk000006ac (
.I0(sig0000069c),
.I1(sig000006c4),
.I2(sig00000692),
.I3(sig00000696),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig00000714)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006ad (
.I0(sig000006ab),
.I1(sig000006a6),
.I2(sig000006af),
.I3(sig000006b4),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig00000713)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006ae (
.I0(sig000006aa),
.I1(sig000006a5),
.I2(sig000006ae),
.I3(sig000006b3),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig00000712)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006af (
.I0(sig000006a9),
.I1(sig000006a4),
.I2(sig000006ad),
.I3(sig000006b1),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig00000711)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006b0 (
.I0(sig000006a8),
.I1(sig000006a3),
.I2(sig000006ac),
.I3(sig000006b0),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig00000710)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006b1 (
.I0(sig000006a6),
.I1(sig000006a2),
.I2(sig000006ab),
.I3(sig000006af),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig0000070f)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006b2 (
.I0(sig000006a5),
.I1(sig000006a1),
.I2(sig000006aa),
.I3(sig000006ae),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig0000070e)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006b3 (
.I0(sig000006a4),
.I1(sig000006a0),
.I2(sig000006a9),
.I3(sig000006ad),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig0000070d)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006b4 (
.I0(sig000006a3),
.I1(sig0000069f),
.I2(sig000006a8),
.I3(sig000006ac),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig0000070c)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006b5 (
.I0(sig000006a2),
.I1(sig0000069e),
.I2(sig000006a6),
.I3(sig000006ab),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig0000070b)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006b6 (
.I0(sig000006a1),
.I1(sig0000069d),
.I2(sig000006a5),
.I3(sig000006aa),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig0000070a)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk000006b7 (
.I0(sig00000691),
.I1(sig000006bd),
.I2(sig000006c7),
.I3(sig00000695),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig00000709)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006b8 (
.I0(sig000006a0),
.I1(sig0000069b),
.I2(sig000006a4),
.I3(sig000006a9),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig00000708)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006b9 (
.I0(sig0000069f),
.I1(sig0000069a),
.I2(sig000006a3),
.I3(sig000006a8),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig00000707)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006ba (
.I0(sig0000069e),
.I1(sig00000699),
.I2(sig000006a2),
.I3(sig000006a6),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig00000706)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006bb (
.I0(sig0000069d),
.I1(sig00000698),
.I2(sig000006a1),
.I3(sig000006a5),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig00000705)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006bc (
.I0(sig0000069b),
.I1(sig00000697),
.I2(sig000006a0),
.I3(sig000006a4),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig00000704)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006bd (
.I0(sig0000069a),
.I1(sig00000696),
.I2(sig0000069f),
.I3(sig000006a3),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig00000703)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006be (
.I0(sig00000699),
.I1(sig00000695),
.I2(sig0000069e),
.I3(sig000006a2),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig00000702)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk000006bf (
.I0(sig00000694),
.I1(sig00000698),
.I2(sig0000069d),
.I3(sig000006a1),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig00000701)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk000006c0 (
.I0(sig00000693),
.I1(sig00000697),
.I2(sig0000069b),
.I3(sig000006a0),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig00000700)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk000006c1 (
.I0(sig00000692),
.I1(sig00000696),
.I2(sig0000069a),
.I3(sig0000069f),
.I4(sig0000064d),
.I5(sig00000895),
.O(sig000006ff)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006c2 (
.I0(sig00000413),
.I1(sig00000447),
.I2(sig00000448),
.I3(sig00000414),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003dc)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006c3 (
.I0(sig00000412),
.I1(sig00000446),
.I2(sig00000447),
.I3(sig00000413),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003db)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006c4 (
.I0(sig00000411),
.I1(sig00000445),
.I2(sig00000446),
.I3(sig00000412),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003da)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006c5 (
.I0(sig0000040e),
.I1(sig00000442),
.I2(sig00000445),
.I3(sig00000411),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003d9)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006c6 (
.I0(sig00000403),
.I1(sig00000437),
.I2(sig00000442),
.I3(sig0000040e),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003d8)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006c7 (
.I0(sig0000040f),
.I1(sig00000443),
.I2(sig00000444),
.I3(sig00000410),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003d6)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006c8 (
.I0(sig0000040d),
.I1(sig00000441),
.I2(sig00000443),
.I3(sig0000040f),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003d5)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006c9 (
.I0(sig000003f8),
.I1(sig0000042c),
.I2(sig00000437),
.I3(sig00000403),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003d4)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006ca (
.I0(sig0000040c),
.I1(sig00000440),
.I2(sig00000441),
.I3(sig0000040d),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003d3)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006cb (
.I0(sig0000040b),
.I1(sig0000043f),
.I2(sig00000440),
.I3(sig0000040c),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003d2)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006cc (
.I0(sig0000040a),
.I1(sig0000043e),
.I2(sig0000043f),
.I3(sig0000040b),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003d1)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006cd (
.I0(sig00000409),
.I1(sig0000043d),
.I2(sig0000043e),
.I3(sig0000040a),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003d0)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006ce (
.I0(sig00000408),
.I1(sig0000043c),
.I2(sig0000043d),
.I3(sig00000409),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003cf)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006cf (
.I0(sig00000407),
.I1(sig0000043b),
.I2(sig0000043c),
.I3(sig00000408),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003ce)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006d0 (
.I0(sig00000406),
.I1(sig0000043a),
.I2(sig0000043b),
.I3(sig00000407),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003cd)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006d1 (
.I0(sig00000405),
.I1(sig00000439),
.I2(sig0000043a),
.I3(sig00000406),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003cc)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006d2 (
.I0(sig00000404),
.I1(sig00000438),
.I2(sig00000439),
.I3(sig00000405),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003cb)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006d3 (
.I0(sig00000402),
.I1(sig00000436),
.I2(sig00000438),
.I3(sig00000404),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003ca)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006d4 (
.I0(sig000003ed),
.I1(sig00000421),
.I2(sig0000042c),
.I3(sig000003f8),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003c9)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006d5 (
.I0(sig00000401),
.I1(sig00000435),
.I2(sig00000436),
.I3(sig00000402),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003c8)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006d6 (
.I0(sig00000400),
.I1(sig00000434),
.I2(sig00000435),
.I3(sig00000401),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003c7)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006d7 (
.I0(sig000003ff),
.I1(sig00000433),
.I2(sig00000434),
.I3(sig00000400),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003c6)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006d8 (
.I0(sig000003fe),
.I1(sig00000432),
.I2(sig00000433),
.I3(sig000003ff),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003c5)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006d9 (
.I0(sig000003fd),
.I1(sig00000431),
.I2(sig00000432),
.I3(sig000003fe),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003c4)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006da (
.I0(sig000003fc),
.I1(sig00000430),
.I2(sig00000431),
.I3(sig000003fd),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003c3)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006db (
.I0(sig000003fb),
.I1(sig0000042f),
.I2(sig00000430),
.I3(sig000003fc),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003c2)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006dc (
.I0(sig000003fa),
.I1(sig0000042e),
.I2(sig0000042f),
.I3(sig000003fb),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003c1)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006dd (
.I0(sig000003f9),
.I1(sig0000042d),
.I2(sig0000042e),
.I3(sig000003fa),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003c0)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006de (
.I0(sig000003f7),
.I1(sig0000042b),
.I2(sig0000042d),
.I3(sig000003f9),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003bf)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006df (
.I0(sig000003e2),
.I1(sig00000416),
.I2(sig00000421),
.I3(sig000003ed),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003be)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006e0 (
.I0(sig000003f6),
.I1(sig0000042a),
.I2(sig0000042b),
.I3(sig000003f7),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003bd)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006e1 (
.I0(sig000003f5),
.I1(sig00000429),
.I2(sig0000042a),
.I3(sig000003f6),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003bc)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006e2 (
.I0(sig000003f4),
.I1(sig00000428),
.I2(sig00000429),
.I3(sig000003f5),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003bb)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006e3 (
.I0(sig000003f3),
.I1(sig00000427),
.I2(sig00000428),
.I3(sig000003f4),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003ba)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006e4 (
.I0(sig000003f2),
.I1(sig00000426),
.I2(sig00000427),
.I3(sig000003f3),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003b9)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006e5 (
.I0(sig000003f1),
.I1(sig00000425),
.I2(sig00000426),
.I3(sig000003f2),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003b8)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006e6 (
.I0(sig000003f0),
.I1(sig00000424),
.I2(sig00000425),
.I3(sig000003f1),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003b7)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006e7 (
.I0(sig000003ef),
.I1(sig00000423),
.I2(sig00000424),
.I3(sig000003f0),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003b6)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006e8 (
.I0(sig000003ee),
.I1(sig00000422),
.I2(sig00000423),
.I3(sig000003ef),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003b5)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006e9 (
.I0(sig000003ec),
.I1(sig00000420),
.I2(sig00000422),
.I3(sig000003ee),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003b4)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006ea (
.I0(sig000003e1),
.I1(sig00000415),
.I2(sig00000416),
.I3(sig000003e2),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003b3)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006eb (
.I0(sig000003eb),
.I1(sig0000041f),
.I2(sig00000420),
.I3(sig000003ec),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003b2)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006ec (
.I0(sig000003ea),
.I1(sig0000041e),
.I2(sig0000041f),
.I3(sig000003eb),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003b1)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006ed (
.I0(sig000003e9),
.I1(sig0000041d),
.I2(sig0000041e),
.I3(sig000003ea),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003b0)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006ee (
.I0(sig000003e8),
.I1(sig0000041c),
.I2(sig0000041d),
.I3(sig000003e9),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003af)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006ef (
.I0(sig000003e7),
.I1(sig0000041b),
.I2(sig0000041c),
.I3(sig000003e8),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003ae)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006f0 (
.I0(sig000003e6),
.I1(sig0000041a),
.I2(sig0000041b),
.I3(sig000003e7),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003ad)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006f1 (
.I0(sig000003e5),
.I1(sig00000419),
.I2(sig0000041a),
.I3(sig000003e6),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003ac)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006f2 (
.I0(sig000003e4),
.I1(sig00000418),
.I2(sig00000419),
.I3(sig000003e5),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003ab)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006f3 (
.I0(sig000003e3),
.I1(sig00000417),
.I2(sig00000418),
.I3(sig000003e4),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003aa)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk000006f4 (
.I0(sig00000414),
.I1(sig00000448),
.I2(sig00000417),
.I3(sig000003e3),
.I4(sig000003e0),
.I5(sig000008ba),
.O(sig000003a9)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk000006f5 (
.I0(sig0000061a),
.I1(sig00000609),
.I2(sig000005f7),
.I3(sig000005ef),
.I4(sig00000897),
.I5(sig00000896),
.O(sig0000076a)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk000006f6 (
.I0(sig0000061b),
.I1(sig0000060a),
.I2(sig000005f8),
.I3(sig000005f0),
.I4(sig00000897),
.I5(sig00000896),
.O(sig00000769)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk000006f7 (
.I0(sig0000061d),
.I1(sig0000060b),
.I2(sig000005f9),
.I3(sig000005fb),
.I4(sig00000897),
.I5(sig00000896),
.O(sig00000768)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk000006f8 (
.I0(sig0000061e),
.I1(sig0000060c),
.I2(sig000005fa),
.I3(sig00000606),
.I4(sig00000897),
.I5(sig00000896),
.O(sig00000761)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk000006f9 (
.I0(sig0000061f),
.I1(sig0000060d),
.I2(sig000005fc),
.I3(sig00000611),
.I4(sig00000897),
.I5(sig00000896),
.O(sig00000756)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk000006fa (
.I0(sig00000620),
.I1(sig0000060e),
.I2(sig000005fd),
.I3(sig0000061c),
.I4(sig00000897),
.I5(sig00000896),
.O(sig0000074b)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk000006fb (
.I0(sig00000621),
.I1(sig0000060f),
.I2(sig000005fe),
.I3(sig00000623),
.I4(sig00000897),
.I5(sig00000896),
.O(sig00000740)
);
LUT2 #(
.INIT ( 4'h8 ))
blk000006fc (
.I0(sig00000021),
.I1(sig00000022),
.O(sig000003de)
);
LUT3 #(
.INIT ( 8'h80 ))
blk000006fd (
.I0(sig000004b2),
.I1(sig000004b3),
.I2(sig000004b0),
.O(sig000005dd)
);
LUT5 #(
.INIT ( 32'h00008000 ))
blk000006fe (
.I0(sig000004b4),
.I1(sig000004b5),
.I2(sig000004b6),
.I3(sig000004ad),
.I4(sig000004ae),
.O(sig000005dc)
);
LUT6 #(
.INIT ( 64'h8000000000000000 ))
blk000006ff (
.I0(sig000004ac),
.I1(sig000004af),
.I2(sig000004b1),
.I3(sig000004ab),
.I4(sig000005dd),
.I5(sig000005dc),
.O(sig000005db)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000700 (
.I0(sig000002b5),
.I1(sig000002b4),
.I2(sig000002b3),
.I3(sig000002b2),
.O(sig00000683)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000701 (
.I0(sig00000330),
.I1(sig00000331),
.I2(sig00000332),
.I3(sig00000333),
.O(sig0000011d)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000702 (
.I0(sig0000032b),
.I1(sig0000032d),
.I2(sig0000032e),
.I3(sig0000032f),
.O(sig0000011c)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000703 (
.I0(sig00000327),
.I1(sig00000328),
.I2(sig00000329),
.I3(sig0000032a),
.O(sig0000011b)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000704 (
.I0(sig00000323),
.I1(sig00000324),
.I2(sig00000325),
.I3(sig00000326),
.O(sig0000011a)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000705 (
.I0(sig00000353),
.I1(sig00000354),
.I2(sig00000355),
.I3(sig00000322),
.O(sig00000119)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000706 (
.I0(sig00000337),
.I1(sig00000342),
.I2(sig0000034d),
.I3(sig00000352),
.O(sig00000118)
);
LUT3 #(
.INIT ( 8'h01 ))
blk00000707 (
.I0(sig00000320),
.I1(sig00000321),
.I2(sig0000032c),
.O(sig00000113)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000708 (
.I0(sig00000458),
.I1(sig00000460),
.O(sig00000368)
);
LUT3 #(
.INIT ( 8'h54 ))
blk00000709 (
.I0(sig0000049c),
.I1(sig0000049b),
.I2(sig000004eb),
.O(sig000008ad)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk0000070a (
.I0(sig00000458),
.I1(sig0000044b),
.I2(sig00000463),
.O(sig000005cc)
);
LUT5 #(
.INIT ( 32'h04FBFB04 ))
blk0000070b (
.I0(sig00000156),
.I1(sig0000020a),
.I2(sig000002bd),
.I3(sig000001a3),
.I4(sig0000029f),
.O(sig0000030c)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk0000070c (
.I0(sig0000065e),
.I1(sig0000065d),
.I2(sig000006df),
.I3(sig000006dc),
.I4(sig000006db),
.I5(sig000006dd),
.O(sig0000086f)
);
LUT6 #(
.INIT ( 64'h6666999666666966 ))
blk0000070d (
.I0(sig000001d5),
.I1(sig00000357),
.I2(sig00000359),
.I3(sig00000071),
.I4(sig0000035e),
.I5(sig00000073),
.O(sig000002f1)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000070e (
.I0(sig00000458),
.I1(sig0000045f),
.O(sig00000367)
);
LUT3 #(
.INIT ( 8'h54 ))
blk0000070f (
.I0(sig0000049c),
.I1(sig0000049b),
.I2(sig000004ea),
.O(sig000008ac)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000710 (
.I0(sig00000458),
.I1(sig00000453),
.I2(sig0000046b),
.O(sig000005d5)
);
LUT5 #(
.INIT ( 32'h04FBFB04 ))
blk00000711 (
.I0(sig00000156),
.I1(sig00000209),
.I2(sig000002bd),
.I3(sig000001a2),
.I4(sig0000029f),
.O(sig0000030b)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk00000712 (
.I0(sig00000852),
.I1(sig00000851),
.I2(sig00000846),
.I3(sig00000848),
.I4(sig00000849),
.I5(sig00000847),
.O(sig00000889)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk00000713 (
.I0(sig0000065e),
.I1(sig0000065d),
.I2(sig000006e0),
.I3(sig000006dd),
.I4(sig000006dc),
.I5(sig000006df),
.O(sig0000086e)
);
LUT6 #(
.INIT ( 64'h6666999666666966 ))
blk00000714 (
.I0(sig000001d4),
.I1(sig00000357),
.I2(sig00000359),
.I3(sig00000070),
.I4(sig0000035e),
.I5(sig00000072),
.O(sig000002f0)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000715 (
.I0(sig00000458),
.I1(sig0000045e),
.O(sig00000366)
);
LUT3 #(
.INIT ( 8'h54 ))
blk00000716 (
.I0(sig0000049c),
.I1(sig0000049b),
.I2(sig000004e9),
.O(sig000008ab)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000717 (
.I0(sig00000458),
.I1(sig00000452),
.I2(sig0000046a),
.O(sig000005d4)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk00000718 (
.I0(sig00000852),
.I1(sig00000851),
.I2(sig00000845),
.I3(sig00000847),
.I4(sig00000848),
.I5(sig00000846),
.O(sig00000888)
);
LUT6 #(
.INIT ( 64'hF7B3E6A2D591C480 ))
blk00000719 (
.I0(sig0000065e),
.I1(sig0000065d),
.I2(sig000006e1),
.I3(sig000006df),
.I4(sig000006dd),
.I5(sig000006e0),
.O(sig0000086d)
);
LUT6 #(
.INIT ( 64'h6666999666666966 ))
blk0000071a (
.I0(sig000001a1),
.I1(sig0000029f),
.I2(sig00000156),
.I3(sig00000208),
.I4(sig000002bd),
.I5(sig0000020a),
.O(sig0000030a)
);
LUT6 #(
.INIT ( 64'h6666999666666966 ))
blk0000071b (
.I0(sig000001d3),
.I1(sig00000357),
.I2(sig00000359),
.I3(sig0000006f),
.I4(sig0000035e),
.I5(sig00000071),
.O(sig000002ef)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000071c (
.I0(sig00000458),
.I1(sig0000045d),
.O(sig00000365)
);
LUT3 #(
.INIT ( 8'h54 ))
blk0000071d (
.I0(sig0000049c),
.I1(sig0000049b),
.I2(sig000004e8),
.O(sig000008aa)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk0000071e (
.I0(sig00000458),
.I1(sig00000451),
.I2(sig00000469),
.O(sig000005d3)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk0000071f (
.I0(sig00000847),
.I1(sig00000845),
.I2(sig00000846),
.I3(sig00000844),
.I4(sig00000851),
.I5(sig00000852),
.O(sig00000887)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk00000720 (
.I0(sig000006e1),
.I1(sig000006df),
.I2(sig000006e0),
.I3(sig000006e2),
.I4(sig0000065d),
.I5(sig0000065e),
.O(sig0000086c)
);
LUT6 #(
.INIT ( 64'h6666999666666966 ))
blk00000721 (
.I0(sig000001a0),
.I1(sig0000029f),
.I2(sig00000156),
.I3(sig00000207),
.I4(sig000002bd),
.I5(sig00000209),
.O(sig00000309)
);
LUT6 #(
.INIT ( 64'h6666999666666966 ))
blk00000722 (
.I0(sig000001d2),
.I1(sig00000357),
.I2(sig00000359),
.I3(sig0000006e),
.I4(sig0000035e),
.I5(sig00000070),
.O(sig000002ee)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000723 (
.I0(sig00000458),
.I1(sig0000045c),
.O(sig00000364)
);
LUT3 #(
.INIT ( 8'h54 ))
blk00000724 (
.I0(sig0000049c),
.I1(sig0000049b),
.I2(sig000004e7),
.O(sig000008a9)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000725 (
.I0(sig00000458),
.I1(sig00000450),
.I2(sig00000468),
.O(sig000005d2)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk00000726 (
.I0(sig00000844),
.I1(sig00000846),
.I2(sig00000845),
.I3(sig00000843),
.I4(sig00000851),
.I5(sig00000852),
.O(sig00000886)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk00000727 (
.I0(sig000006e2),
.I1(sig000006e0),
.I2(sig000006e1),
.I3(sig000006e3),
.I4(sig0000065d),
.I5(sig0000065e),
.O(sig0000086b)
);
LUT6 #(
.INIT ( 64'h6666999666666966 ))
blk00000728 (
.I0(sig0000019f),
.I1(sig0000029f),
.I2(sig00000156),
.I3(sig00000206),
.I4(sig000002bd),
.I5(sig00000208),
.O(sig00000308)
);
LUT6 #(
.INIT ( 64'h6666999666666966 ))
blk00000729 (
.I0(sig000001d1),
.I1(sig00000357),
.I2(sig00000359),
.I3(sig0000006d),
.I4(sig0000035e),
.I5(sig0000006f),
.O(sig000002ed)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000072a (
.I0(sig00000458),
.I1(sig0000045b),
.O(sig00000363)
);
LUT3 #(
.INIT ( 8'h54 ))
blk0000072b (
.I0(sig0000049c),
.I1(sig0000049b),
.I2(sig000004e6),
.O(sig000008a8)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk0000072c (
.I0(sig00000458),
.I1(sig0000044f),
.I2(sig00000467),
.O(sig000005d1)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk0000072d (
.I0(sig00000843),
.I1(sig00000845),
.I2(sig00000844),
.I3(sig00000842),
.I4(sig00000851),
.I5(sig00000852),
.O(sig00000885)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk0000072e (
.I0(sig000006e3),
.I1(sig000006e1),
.I2(sig000006e2),
.I3(sig000006e4),
.I4(sig0000065d),
.I5(sig0000065e),
.O(sig0000086a)
);
LUT6 #(
.INIT ( 64'h6666999666666966 ))
blk0000072f (
.I0(sig0000019e),
.I1(sig0000029f),
.I2(sig00000156),
.I3(sig00000205),
.I4(sig000002bd),
.I5(sig00000207),
.O(sig00000307)
);
LUT6 #(
.INIT ( 64'h6666999666666966 ))
blk00000730 (
.I0(sig000001cf),
.I1(sig00000357),
.I2(sig00000359),
.I3(sig0000006c),
.I4(sig0000035e),
.I5(sig0000006e),
.O(sig000002ec)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000731 (
.I0(sig00000458),
.I1(sig0000045a),
.O(sig00000362)
);
LUT3 #(
.INIT ( 8'h54 ))
blk00000732 (
.I0(sig0000049c),
.I1(sig0000049b),
.I2(sig000004e5),
.O(sig000008a7)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000733 (
.I0(sig00000458),
.I1(sig0000044e),
.I2(sig00000466),
.O(sig000005d0)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk00000734 (
.I0(sig00000842),
.I1(sig00000844),
.I2(sig00000843),
.I3(sig00000841),
.I4(sig00000851),
.I5(sig00000852),
.O(sig00000884)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk00000735 (
.I0(sig000006e4),
.I1(sig000006e2),
.I2(sig000006e3),
.I3(sig000006e5),
.I4(sig0000065d),
.I5(sig0000065e),
.O(sig00000868)
);
LUT6 #(
.INIT ( 64'h6666999666666966 ))
blk00000736 (
.I0(sig0000019d),
.I1(sig0000029f),
.I2(sig00000156),
.I3(sig00000204),
.I4(sig000002bd),
.I5(sig00000206),
.O(sig00000306)
);
LUT6 #(
.INIT ( 64'h6666999666666966 ))
blk00000737 (
.I0(sig000001ce),
.I1(sig00000357),
.I2(sig00000359),
.I3(sig0000006b),
.I4(sig0000035e),
.I5(sig0000006d),
.O(sig000002eb)
);
LUT2 #(
.INIT ( 4'h6 ))
blk00000738 (
.I0(sig00000458),
.I1(sig00000459),
.O(sig00000361)
);
LUT3 #(
.INIT ( 8'h54 ))
blk00000739 (
.I0(sig0000049c),
.I1(sig0000049b),
.I2(sig000004e4),
.O(sig000008a6)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk0000073a (
.I0(sig00000458),
.I1(sig0000044d),
.I2(sig00000465),
.O(sig000005cf)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk0000073b (
.I0(sig00000841),
.I1(sig00000843),
.I2(sig00000842),
.I3(sig0000083f),
.I4(sig00000851),
.I5(sig00000852),
.O(sig00000882)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk0000073c (
.I0(sig000006e5),
.I1(sig000006e3),
.I2(sig000006e4),
.I3(sig000006e6),
.I4(sig0000065d),
.I5(sig0000065e),
.O(sig00000867)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk0000073d (
.I0(sig0000019c),
.I1(sig00000205),
.I2(sig00000203),
.I3(sig000002bd),
.I4(sig00000156),
.I5(sig0000029f),
.O(sig00000305)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk0000073e (
.I0(sig000001cd),
.I1(sig0000006c),
.I2(sig00000069),
.I3(sig0000035e),
.I4(sig00000359),
.I5(sig00000357),
.O(sig000002ea)
);
LUT2 #(
.INIT ( 4'h6 ))
blk0000073f (
.I0(sig00000458),
.I1(sig00000456),
.O(sig00000360)
);
LUT3 #(
.INIT ( 8'h54 ))
blk00000740 (
.I0(sig0000049c),
.I1(sig0000049b),
.I2(sig000004e2),
.O(sig000008a5)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000741 (
.I0(sig00000458),
.I1(sig0000044c),
.I2(sig00000464),
.O(sig000005ce)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk00000742 (
.I0(sig0000083f),
.I1(sig00000842),
.I2(sig00000841),
.I3(sig0000083e),
.I4(sig00000851),
.I5(sig00000852),
.O(sig00000881)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk00000743 (
.I0(sig000006e6),
.I1(sig000006e4),
.I2(sig000006e5),
.I3(sig000006e7),
.I4(sig0000065d),
.I5(sig0000065e),
.O(sig00000866)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk00000744 (
.I0(sig0000019a),
.I1(sig00000204),
.I2(sig00000201),
.I3(sig000002bd),
.I4(sig00000156),
.I5(sig0000029f),
.O(sig00000303)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk00000745 (
.I0(sig000001cc),
.I1(sig0000006b),
.I2(sig00000068),
.I3(sig0000035e),
.I4(sig00000359),
.I5(sig00000357),
.O(sig000002e9)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000746 (
.I0(sig00000458),
.I1(sig0000044a),
.I2(sig00000462),
.O(sig000005cd)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk00000747 (
.I0(sig0000083e),
.I1(sig00000841),
.I2(sig0000083f),
.I3(sig0000083d),
.I4(sig00000851),
.I5(sig00000852),
.O(sig00000880)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk00000748 (
.I0(sig000006e7),
.I1(sig000006e5),
.I2(sig000006e6),
.I3(sig000006e8),
.I4(sig0000065d),
.I5(sig0000065e),
.O(sig00000865)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk00000749 (
.I0(sig00000199),
.I1(sig00000203),
.I2(sig00000200),
.I3(sig000002bd),
.I4(sig00000156),
.I5(sig0000029f),
.O(sig00000302)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk0000074a (
.I0(sig000001cb),
.I1(sig00000069),
.I2(sig00000067),
.I3(sig0000035e),
.I4(sig00000359),
.I5(sig00000357),
.O(sig000002e8)
);
LUT3 #(
.INIT ( 8'h20 ))
blk0000074b (
.I0(sig0000012e),
.I1(sig00000095),
.I2(sig00000141),
.O(sig00000010)
);
LUT5 #(
.INIT ( 32'h8F808080 ))
blk0000074c (
.I0(sig00000124),
.I1(sig00000136),
.I2(sig00000095),
.I3(sig00000123),
.I4(sig00000135),
.O(sig00000011)
);
LUT3 #(
.INIT ( 8'hF8 ))
blk0000074d (
.I0(sig0000012e),
.I1(sig00000141),
.I2(sig00000095),
.O(sig00000012)
);
LUT6 #(
.INIT ( 64'hFFF8F7F00F080700 ))
blk0000074e (
.I0(sig0000012f),
.I1(sig00000142),
.I2(sig00000096),
.I3(sig00000010),
.I4(sig00000012),
.I5(sig00000011),
.O(sig00000153)
);
LUT5 #(
.INIT ( 32'h8F808080 ))
blk0000074f (
.I0(sig00000126),
.I1(sig00000138),
.I2(sig00000095),
.I3(sig00000125),
.I4(sig00000137),
.O(sig00000014)
);
LUT5 #(
.INIT ( 32'h1DDD3FFF ))
blk00000750 (
.I0(sig0000013d),
.I1(sig00000095),
.I2(sig0000013e),
.I3(sig0000012b),
.I4(sig0000012a),
.O(sig00000015)
);
LUT3 #(
.INIT ( 8'hDF ))
blk00000751 (
.I0(sig0000013f),
.I1(sig00000095),
.I2(sig0000012c),
.O(sig00000016)
);
LUT3 #(
.INIT ( 8'hEA ))
blk00000752 (
.I0(sig00000095),
.I1(sig0000013f),
.I2(sig0000012c),
.O(sig00000017)
);
LUT6 #(
.INIT ( 64'h80F000708FFF0F7F ))
blk00000753 (
.I0(sig0000012d),
.I1(sig00000140),
.I2(sig00000096),
.I3(sig00000016),
.I4(sig00000017),
.I5(sig00000015),
.O(sig00000152)
);
LUT3 #(
.INIT ( 8'h1B ))
blk00000754 (
.I0(sig00000458),
.I1(sig00000461),
.I2(sig00000449),
.O(sig000005ab)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk00000755 (
.I0(sig0000083d),
.I1(sig0000083f),
.I2(sig0000083e),
.I3(sig0000083c),
.I4(sig00000851),
.I5(sig00000852),
.O(sig0000087f)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk00000756 (
.I0(sig000006e8),
.I1(sig000006e6),
.I2(sig000006e7),
.I3(sig000006ea),
.I4(sig0000065d),
.I5(sig0000065e),
.O(sig00000864)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk00000757 (
.I0(sig00000198),
.I1(sig00000201),
.I2(sig000001ff),
.I3(sig000002bd),
.I4(sig00000156),
.I5(sig0000029f),
.O(sig00000301)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk00000758 (
.I0(sig000001ca),
.I1(sig00000068),
.I2(sig00000066),
.I3(sig0000035e),
.I4(sig00000359),
.I5(sig00000357),
.O(sig000002e7)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk00000759 (
.I0(sig0000083c),
.I1(sig0000083e),
.I2(sig0000083d),
.I3(sig0000083b),
.I4(sig00000851),
.I5(sig00000852),
.O(sig0000087e)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk0000075a (
.I0(sig000006ea),
.I1(sig000006e7),
.I2(sig000006e8),
.I3(sig000006eb),
.I4(sig0000065d),
.I5(sig0000065e),
.O(sig00000863)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk0000075b (
.I0(sig00000197),
.I1(sig00000200),
.I2(sig000001fe),
.I3(sig000002bd),
.I4(sig00000156),
.I5(sig0000029f),
.O(sig00000300)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk0000075c (
.I0(sig000001c9),
.I1(sig00000067),
.I2(sig00000065),
.I3(sig0000035e),
.I4(sig00000359),
.I5(sig00000357),
.O(sig000002e6)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk0000075d (
.I0(sig0000083b),
.I1(sig0000083d),
.I2(sig0000083c),
.I3(sig0000083a),
.I4(sig00000851),
.I5(sig00000852),
.O(sig0000087d)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk0000075e (
.I0(sig000006eb),
.I1(sig000006e8),
.I2(sig000006ea),
.I3(sig000006ec),
.I4(sig0000065d),
.I5(sig0000065e),
.O(sig00000862)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk0000075f (
.I0(sig00000196),
.I1(sig000001ff),
.I2(sig000001fd),
.I3(sig000002bd),
.I4(sig00000156),
.I5(sig0000029f),
.O(sig000002ff)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk00000760 (
.I0(sig000001c8),
.I1(sig00000066),
.I2(sig00000064),
.I3(sig0000035e),
.I4(sig00000359),
.I5(sig00000357),
.O(sig000002e5)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk00000761 (
.I0(sig0000083a),
.I1(sig0000083c),
.I2(sig0000083b),
.I3(sig00000839),
.I4(sig00000851),
.I5(sig00000852),
.O(sig0000087c)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk00000762 (
.I0(sig000006ec),
.I1(sig000006ea),
.I2(sig000006eb),
.I3(sig000006ed),
.I4(sig0000065d),
.I5(sig0000065e),
.O(sig00000861)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk00000763 (
.I0(sig00000195),
.I1(sig000001fe),
.I2(sig000001fc),
.I3(sig000002bd),
.I4(sig00000156),
.I5(sig0000029f),
.O(sig000002fe)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk00000764 (
.I0(sig000001c7),
.I1(sig00000065),
.I2(sig00000063),
.I3(sig0000035e),
.I4(sig00000359),
.I5(sig00000357),
.O(sig000002e4)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk00000765 (
.I0(sig00000839),
.I1(sig0000083b),
.I2(sig0000083a),
.I3(sig00000838),
.I4(sig00000851),
.I5(sig00000852),
.O(sig0000087b)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk00000766 (
.I0(sig000006ed),
.I1(sig000006eb),
.I2(sig000006ec),
.I3(sig000006ee),
.I4(sig0000065d),
.I5(sig0000065e),
.O(sig00000860)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk00000767 (
.I0(sig00000194),
.I1(sig000001fd),
.I2(sig000001fb),
.I3(sig000002bd),
.I4(sig00000156),
.I5(sig0000029f),
.O(sig000002fd)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk00000768 (
.I0(sig000001c6),
.I1(sig00000064),
.I2(sig00000062),
.I3(sig0000035e),
.I4(sig00000359),
.I5(sig00000357),
.O(sig000002e3)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk00000769 (
.I0(sig00000897),
.I1(sig00000678),
.I2(sig0000067d),
.O(sig00000896)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000076a (
.I0(sig000004c6),
.I1(sig0000065b),
.I2(sig000004c7),
.I3(sig0000062b),
.O(sig000005d9)
);
LUT5 #(
.INIT ( 32'h00000009 ))
blk0000076b (
.I0(sig000004c8),
.I1(sig0000062a),
.I2(sig000004ca),
.I3(sig000004cb),
.I4(sig000004c9),
.O(sig000005da)
);
LUT6 #(
.INIT ( 64'h0000000000009009 ))
blk0000076c (
.I0(sig000004c2),
.I1(sig0000065d),
.I2(sig000004c3),
.I3(sig0000065e),
.I4(sig000004c4),
.I5(sig000004cc),
.O(sig000005d8)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk0000076d (
.I0(sig00000838),
.I1(sig0000083a),
.I2(sig00000839),
.I3(sig00000837),
.I4(sig00000851),
.I5(sig00000852),
.O(sig0000087a)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk0000076e (
.I0(sig000006ed),
.I1(sig000006ec),
.I2(sig000006ee),
.I3(sig000006ef),
.I4(sig0000065e),
.I5(sig0000065d),
.O(sig0000085f)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk0000076f (
.I0(sig00000193),
.I1(sig000001fc),
.I2(sig000001fa),
.I3(sig000002bd),
.I4(sig00000156),
.I5(sig0000029f),
.O(sig000002fc)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk00000770 (
.I0(sig000001dc),
.I1(sig00000063),
.I2(sig00000061),
.I3(sig0000035e),
.I4(sig00000359),
.I5(sig00000357),
.O(sig000002e2)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk00000771 (
.I0(sig00000837),
.I1(sig00000839),
.I2(sig00000838),
.I3(sig00000836),
.I4(sig00000851),
.I5(sig00000852),
.O(sig00000879)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk00000772 (
.I0(sig000006ef),
.I1(sig000006ed),
.I2(sig000006ee),
.I3(sig000006f0),
.I4(sig0000065d),
.I5(sig0000065e),
.O(sig00000877)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk00000773 (
.I0(sig00000192),
.I1(sig000001fb),
.I2(sig000001f9),
.I3(sig000002bd),
.I4(sig00000156),
.I5(sig0000029f),
.O(sig000002fb)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk00000774 (
.I0(sig000001db),
.I1(sig00000062),
.I2(sig00000060),
.I3(sig0000035e),
.I4(sig00000359),
.I5(sig00000357),
.O(sig000002e1)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk00000775 (
.I0(sig00000837),
.I1(sig00000838),
.I2(sig00000836),
.I3(sig00000850),
.I4(sig00000852),
.I5(sig00000851),
.O(sig00000891)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk00000776 (
.I0(sig000006f0),
.I1(sig000006ee),
.I2(sig000006ef),
.I3(sig000006f1),
.I4(sig0000065d),
.I5(sig0000065e),
.O(sig00000876)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk00000777 (
.I0(sig00000191),
.I1(sig000001fa),
.I2(sig000001f8),
.I3(sig000002bd),
.I4(sig00000156),
.I5(sig0000029f),
.O(sig000002fa)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk00000778 (
.I0(sig000001da),
.I1(sig00000061),
.I2(sig00000094),
.I3(sig0000035e),
.I4(sig00000359),
.I5(sig00000357),
.O(sig000002e0)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk00000779 (
.I0(sig00000850),
.I1(sig00000837),
.I2(sig00000836),
.I3(sig0000084f),
.I4(sig00000851),
.I5(sig00000852),
.O(sig00000890)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk0000077a (
.I0(sig000006f1),
.I1(sig000006ef),
.I2(sig000006f0),
.I3(sig000006f2),
.I4(sig0000065d),
.I5(sig0000065e),
.O(sig00000875)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk0000077b (
.I0(sig000001aa),
.I1(sig000001f9),
.I2(sig00000211),
.I3(sig000002bd),
.I4(sig00000156),
.I5(sig0000029f),
.O(sig00000314)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk0000077c (
.I0(sig000001d9),
.I1(sig00000060),
.I2(sig00000093),
.I3(sig0000035e),
.I4(sig00000359),
.I5(sig00000357),
.O(sig000002f8)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk0000077d (
.I0(sig0000084f),
.I1(sig00000836),
.I2(sig00000850),
.I3(sig0000084e),
.I4(sig00000851),
.I5(sig00000852),
.O(sig0000088f)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk0000077e (
.I0(sig000006f2),
.I1(sig000006f0),
.I2(sig000006f1),
.I3(sig000006f3),
.I4(sig0000065d),
.I5(sig0000065e),
.O(sig00000874)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk0000077f (
.I0(sig000001a9),
.I1(sig000001f8),
.I2(sig00000210),
.I3(sig000002bd),
.I4(sig00000156),
.I5(sig0000029f),
.O(sig00000313)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk00000780 (
.I0(sig000001d8),
.I1(sig00000094),
.I2(sig00000092),
.I3(sig0000035e),
.I4(sig00000359),
.I5(sig00000357),
.O(sig000002f7)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk00000781 (
.I0(sig0000084e),
.I1(sig00000850),
.I2(sig0000084f),
.I3(sig0000084d),
.I4(sig00000851),
.I5(sig00000852),
.O(sig0000088e)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk00000782 (
.I0(sig000006f3),
.I1(sig000006f1),
.I2(sig000006f2),
.I3(sig000006f5),
.I4(sig0000065d),
.I5(sig0000065e),
.O(sig00000873)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk00000783 (
.I0(sig000001a8),
.I1(sig00000211),
.I2(sig0000020f),
.I3(sig000002bd),
.I4(sig00000156),
.I5(sig0000029f),
.O(sig00000312)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk00000784 (
.I0(sig000001d7),
.I1(sig00000093),
.I2(sig00000091),
.I3(sig0000035e),
.I4(sig00000359),
.I5(sig00000357),
.O(sig000002f6)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk00000785 (
.I0(sig0000084d),
.I1(sig0000084f),
.I2(sig0000084e),
.I3(sig0000084c),
.I4(sig00000851),
.I5(sig00000852),
.O(sig0000088d)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk00000786 (
.I0(sig000006f5),
.I1(sig000006f2),
.I2(sig000006f3),
.I3(sig000006f6),
.I4(sig0000065d),
.I5(sig0000065e),
.O(sig00000872)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk00000787 (
.I0(sig000001a7),
.I1(sig00000210),
.I2(sig0000020e),
.I3(sig000002bd),
.I4(sig00000156),
.I5(sig0000029f),
.O(sig00000311)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk00000788 (
.I0(sig000001d6),
.I1(sig00000092),
.I2(sig0000008b),
.I3(sig0000035e),
.I4(sig00000359),
.I5(sig00000357),
.O(sig000002f5)
);
LUT3 #(
.INIT ( 8'h54 ))
blk00000789 (
.I0(sig0000049c),
.I1(sig0000049b),
.I2(sig000004e1),
.O(sig000008a3)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk0000078a (
.I0(sig0000084c),
.I1(sig0000084e),
.I2(sig0000084d),
.I3(sig0000084b),
.I4(sig00000851),
.I5(sig00000852),
.O(sig0000088c)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk0000078b (
.I0(sig000006f6),
.I1(sig000006f3),
.I2(sig000006f5),
.I3(sig000006f7),
.I4(sig0000065d),
.I5(sig0000065e),
.O(sig00000871)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk0000078c (
.I0(sig000001a6),
.I1(sig0000020f),
.I2(sig0000020d),
.I3(sig000002bd),
.I4(sig00000156),
.I5(sig0000029f),
.O(sig00000310)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk0000078d (
.I0(sig000001d0),
.I1(sig00000091),
.I2(sig00000080),
.I3(sig0000035e),
.I4(sig00000359),
.I5(sig00000357),
.O(sig000002f4)
);
LUT6 #(
.INIT ( 64'hFF00AAAAF0F0CCCC ))
blk0000078e (
.I0(sig0000084b),
.I1(sig0000084d),
.I2(sig0000084c),
.I3(sig0000084a),
.I4(sig00000851),
.I5(sig00000852),
.O(sig0000088b)
);
LUT6 #(
.INIT ( 64'hFF00F0F0CCCCAAAA ))
blk0000078f (
.I0(sig000006f5),
.I1(sig000006f6),
.I2(sig000006f7),
.I3(sig000006f8),
.I4(sig0000065d),
.I5(sig0000065e),
.O(sig00000870)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk00000790 (
.I0(sig000001a5),
.I1(sig0000020e),
.I2(sig0000020c),
.I3(sig000002bd),
.I4(sig00000156),
.I5(sig0000029f),
.O(sig0000030f)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk00000791 (
.I0(sig000001c5),
.I1(sig0000008b),
.I2(sig00000075),
.I3(sig0000035e),
.I4(sig00000359),
.I5(sig00000357),
.O(sig000002f3)
);
LUT6 #(
.INIT ( 64'hAAAACCCCFF00F0F0 ))
blk00000792 (
.I0(sig00000840),
.I1(sig0000084a),
.I2(sig0000084c),
.I3(sig0000084b),
.I4(sig00000851),
.I5(sig00000852),
.O(sig0000088a)
);
LUT6 #(
.INIT ( 64'hFF00CCCCF0F0AAAA ))
blk00000793 (
.I0(sig000006f6),
.I1(sig000006f8),
.I2(sig000006f7),
.I3(sig000006f9),
.I4(sig0000065d),
.I5(sig0000065e),
.O(sig00000869)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk00000794 (
.I0(sig000001a4),
.I1(sig0000020d),
.I2(sig0000020b),
.I3(sig000002bd),
.I4(sig00000156),
.I5(sig0000029f),
.O(sig0000030e)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk00000795 (
.I0(sig000001c4),
.I1(sig00000080),
.I2(sig0000006a),
.I3(sig0000035e),
.I4(sig00000359),
.I5(sig00000357),
.O(sig000002f2)
);
LUT5 #(
.INIT ( 32'hF30CF50A ))
blk00000796 (
.I0(sig0000005f),
.I1(sig00000075),
.I2(sig0000035e),
.I3(sig00000357),
.I4(sig00000359),
.O(sig000002c2)
);
LUT6 #(
.INIT ( 64'hAAAACCCCFF00F0F0 ))
blk00000797 (
.I0(sig00000835),
.I1(sig00000840),
.I2(sig0000084b),
.I3(sig0000084a),
.I4(sig00000851),
.I5(sig00000852),
.O(sig00000883)
);
LUT6 #(
.INIT ( 64'hAAAACCCCFF00F0F0 ))
blk00000798 (
.I0(sig000006fa),
.I1(sig000006f9),
.I2(sig000006f7),
.I3(sig000006f8),
.I4(sig0000065d),
.I5(sig0000065e),
.O(sig0000085e)
);
LUT6 #(
.INIT ( 64'h559955A5AA66AA5A ))
blk00000799 (
.I0(sig0000019b),
.I1(sig0000020c),
.I2(sig00000202),
.I3(sig000002bd),
.I4(sig00000156),
.I5(sig0000029f),
.O(sig0000030d)
);
LUT5 #(
.INIT ( 32'hF30CF50A ))
blk0000079a (
.I0(sig0000005e),
.I1(sig0000006a),
.I2(sig0000035e),
.I3(sig00000357),
.I4(sig00000359),
.O(sig000002c1)
);
LUT6 #(
.INIT ( 64'hAAAACCCCF0F0FF00 ))
blk0000079b (
.I0(sig00000834),
.I1(sig00000835),
.I2(sig00000840),
.I3(sig0000084a),
.I4(sig00000851),
.I5(sig00000852),
.O(sig00000878)
);
LUT6 #(
.INIT ( 64'h33C33399CC3CCC66 ))
blk0000079c (
.I0(sig000001f7),
.I1(sig00000190),
.I2(sig0000020b),
.I3(sig000002bd),
.I4(sig00000156),
.I5(sig0000029f),
.O(sig00000304)
);
LUT6 #(
.INIT ( 64'h33C33399CC3CCC66 ))
blk0000079d (
.I0(sig000001f6),
.I1(sig0000018f),
.I2(sig00000202),
.I3(sig000002bd),
.I4(sig00000156),
.I5(sig0000029f),
.O(sig000002f9)
);
LUT5 #(
.INIT ( 32'h00CCAAF0 ))
blk0000079e (
.I0(sig000006fa),
.I1(sig000006f9),
.I2(sig000006f8),
.I3(sig0000065e),
.I4(sig0000065d),
.O(sig0000085b)
);
LUT4 #(
.INIT ( 16'hFF51 ))
blk0000079f (
.I0(sig000006fa),
.I1(sig000006f9),
.I2(sig0000065d),
.I3(sig0000065e),
.O(sig0000085a)
);
LUT6 #(
.INIT ( 64'hAAAACCCCFF00F0F0 ))
blk000007a0 (
.I0(sig000006fa),
.I1(sig000006f9),
.I2(sig000006f7),
.I3(sig000006f8),
.I4(sig0000065d),
.I5(sig0000065e),
.O(sig00000859)
);
FDR #(
.INIT ( 1'b0 ))
blk000007a1 (
.C(clk),
.D(sig00000002),
.R(sig000003e0),
.Q(sig00000351)
);
FDS #(
.INIT ( 1'b0 ))
blk000007a2 (
.C(clk),
.D(sig000003d7),
.S(sig000003e0),
.Q(sig00000350)
);
FDR #(
.INIT ( 1'b0 ))
blk000007a3 (
.C(clk),
.D(sig00000385),
.R(sig000008bb),
.Q(sig00000173)
);
FDR #(
.INIT ( 1'b0 ))
blk000007a4 (
.C(clk),
.D(sig00000386),
.R(sig000008bb),
.Q(sig00000174)
);
FDR #(
.INIT ( 1'b0 ))
blk000007a5 (
.C(clk),
.D(sig00000387),
.R(sig000008bb),
.Q(sig0000017f)
);
FDR #(
.INIT ( 1'b0 ))
blk000007a6 (
.C(clk),
.D(sig00000388),
.R(sig000008bb),
.Q(sig00000188)
);
FDR #(
.INIT ( 1'b0 ))
blk000007a7 (
.C(clk),
.D(sig00000389),
.R(sig000008bb),
.Q(sig00000189)
);
FDR #(
.INIT ( 1'b0 ))
blk000007a8 (
.C(clk),
.D(sig0000038b),
.R(sig000008bb),
.Q(sig0000018a)
);
FDR #(
.INIT ( 1'b0 ))
blk000007a9 (
.C(clk),
.D(sig0000038c),
.R(sig000008bb),
.Q(sig0000018b)
);
FDR #(
.INIT ( 1'b0 ))
blk000007aa (
.C(clk),
.D(sig0000038d),
.R(sig000008bb),
.Q(sig0000018c)
);
FDR #(
.INIT ( 1'b0 ))
blk000007ab (
.C(clk),
.D(sig0000038e),
.R(sig000008bb),
.Q(sig0000018d)
);
FDR #(
.INIT ( 1'b0 ))
blk000007ac (
.C(clk),
.D(sig0000038f),
.R(sig000008bb),
.Q(sig0000018e)
);
FDR #(
.INIT ( 1'b0 ))
blk000007ad (
.C(clk),
.D(sig00000390),
.R(sig000008bb),
.Q(sig00000175)
);
FDR #(
.INIT ( 1'b0 ))
blk000007ae (
.C(clk),
.D(sig00000391),
.R(sig000008bb),
.Q(sig00000176)
);
FDR #(
.INIT ( 1'b0 ))
blk000007af (
.C(clk),
.D(sig00000392),
.R(sig000008bb),
.Q(sig00000177)
);
FDR #(
.INIT ( 1'b0 ))
blk000007b0 (
.C(clk),
.D(sig00000393),
.R(sig000008bb),
.Q(sig00000178)
);
FDR #(
.INIT ( 1'b0 ))
blk000007b1 (
.C(clk),
.D(sig00000394),
.R(sig000008bb),
.Q(sig00000179)
);
FDR #(
.INIT ( 1'b0 ))
blk000007b2 (
.C(clk),
.D(sig00000396),
.R(sig000008bb),
.Q(sig0000017a)
);
FDR #(
.INIT ( 1'b0 ))
blk000007b3 (
.C(clk),
.D(sig00000397),
.R(sig000008bb),
.Q(sig0000017b)
);
FDR #(
.INIT ( 1'b0 ))
blk000007b4 (
.C(clk),
.D(sig00000398),
.R(sig000008bb),
.Q(sig0000017c)
);
FDR #(
.INIT ( 1'b0 ))
blk000007b5 (
.C(clk),
.D(sig00000399),
.R(sig000008bb),
.Q(sig0000017d)
);
FDR #(
.INIT ( 1'b0 ))
blk000007b6 (
.C(clk),
.D(sig0000039a),
.R(sig000008bb),
.Q(sig0000017e)
);
FDR #(
.INIT ( 1'b0 ))
blk000007b7 (
.C(clk),
.D(sig0000039b),
.R(sig000008bb),
.Q(sig00000180)
);
FDR #(
.INIT ( 1'b0 ))
blk000007b8 (
.C(clk),
.D(sig0000039c),
.R(sig000008bb),
.Q(sig00000181)
);
FDR #(
.INIT ( 1'b0 ))
blk000007b9 (
.C(clk),
.D(sig0000039d),
.R(sig000008bb),
.Q(sig00000182)
);
FDR #(
.INIT ( 1'b0 ))
blk000007ba (
.C(clk),
.D(sig0000039e),
.R(sig000008bb),
.Q(sig00000183)
);
FDR #(
.INIT ( 1'b0 ))
blk000007bb (
.C(clk),
.D(sig0000039f),
.R(sig000008bb),
.Q(sig00000184)
);
FDR #(
.INIT ( 1'b0 ))
blk000007bc (
.C(clk),
.D(sig000003a1),
.R(sig000008bb),
.Q(sig00000185)
);
FDR #(
.INIT ( 1'b0 ))
blk000007bd (
.C(clk),
.D(sig000003a2),
.R(sig000008bb),
.Q(sig00000186)
);
FDR #(
.INIT ( 1'b0 ))
blk000007be (
.C(clk),
.D(sig00000002),
.R(sig000008bb),
.Q(sig00000187)
);
FDR #(
.INIT ( 1'b0 ))
blk000007bf (
.C(clk),
.D(sig00000374),
.R(sig000008bb),
.Q(sig000001dd)
);
FDR #(
.INIT ( 1'b0 ))
blk000007c0 (
.C(clk),
.D(sig0000037f),
.R(sig000008bb),
.Q(sig000001de)
);
FDR #(
.INIT ( 1'b0 ))
blk000007c1 (
.C(clk),
.D(sig0000038a),
.R(sig000008bb),
.Q(sig000001e9)
);
FDR #(
.INIT ( 1'b0 ))
blk000007c2 (
.C(clk),
.D(sig00000395),
.R(sig000008bb),
.Q(sig000001ef)
);
FDR #(
.INIT ( 1'b0 ))
blk000007c3 (
.C(clk),
.D(sig000003a0),
.R(sig000008bb),
.Q(sig000001f0)
);
FDR #(
.INIT ( 1'b0 ))
blk000007c4 (
.C(clk),
.D(sig000003a3),
.R(sig000008bb),
.Q(sig000001f1)
);
FDR #(
.INIT ( 1'b0 ))
blk000007c5 (
.C(clk),
.D(sig000003a4),
.R(sig000008bb),
.Q(sig000001f2)
);
FDR #(
.INIT ( 1'b0 ))
blk000007c6 (
.C(clk),
.D(sig000003a5),
.R(sig000008bb),
.Q(sig000001f3)
);
FDR #(
.INIT ( 1'b0 ))
blk000007c7 (
.C(clk),
.D(sig000003a6),
.R(sig000008bb),
.Q(sig000001f4)
);
FDR #(
.INIT ( 1'b0 ))
blk000007c8 (
.C(clk),
.D(sig000003a7),
.R(sig000008bb),
.Q(sig000001f5)
);
FDR #(
.INIT ( 1'b0 ))
blk000007c9 (
.C(clk),
.D(sig00000375),
.R(sig000008bb),
.Q(sig000001df)
);
FDR #(
.INIT ( 1'b0 ))
blk000007ca (
.C(clk),
.D(sig00000376),
.R(sig000008bb),
.Q(sig000001e0)
);
FDR #(
.INIT ( 1'b0 ))
blk000007cb (
.C(clk),
.D(sig00000377),
.R(sig000008bb),
.Q(sig000001e1)
);
FDR #(
.INIT ( 1'b0 ))
blk000007cc (
.C(clk),
.D(sig00000378),
.R(sig000008bb),
.Q(sig000001e2)
);
FDR #(
.INIT ( 1'b0 ))
blk000007cd (
.C(clk),
.D(sig00000379),
.R(sig000008bb),
.Q(sig000001e3)
);
FDR #(
.INIT ( 1'b0 ))
blk000007ce (
.C(clk),
.D(sig0000037a),
.R(sig000008bb),
.Q(sig000001e4)
);
FDR #(
.INIT ( 1'b0 ))
blk000007cf (
.C(clk),
.D(sig0000037b),
.R(sig000008bb),
.Q(sig000001e5)
);
FDR #(
.INIT ( 1'b0 ))
blk000007d0 (
.C(clk),
.D(sig0000037c),
.R(sig000008bb),
.Q(sig000001e6)
);
FDR #(
.INIT ( 1'b0 ))
blk000007d1 (
.C(clk),
.D(sig0000037d),
.R(sig000008bb),
.Q(sig000001e7)
);
FDR #(
.INIT ( 1'b0 ))
blk000007d2 (
.C(clk),
.D(sig0000037e),
.R(sig000008bb),
.Q(sig000001e8)
);
FDR #(
.INIT ( 1'b0 ))
blk000007d3 (
.C(clk),
.D(sig00000380),
.R(sig000008bb),
.Q(sig000001ea)
);
FDR #(
.INIT ( 1'b0 ))
blk000007d4 (
.C(clk),
.D(sig00000381),
.R(sig000008bb),
.Q(sig000001eb)
);
FDR #(
.INIT ( 1'b0 ))
blk000007d5 (
.C(clk),
.D(sig00000382),
.R(sig000008bb),
.Q(sig000001ec)
);
FDR #(
.INIT ( 1'b0 ))
blk000007d6 (
.C(clk),
.D(sig00000383),
.R(sig000008bb),
.Q(sig000001ed)
);
FDR #(
.INIT ( 1'b0 ))
blk000007d7 (
.C(clk),
.D(sig00000384),
.R(sig000008bb),
.Q(sig000001ee)
);
FDS #(
.INIT ( 1'b0 ))
blk000007d8 (
.C(clk),
.D(sig000005bf),
.S(sig000004d1),
.Q(sig000004e0)
);
LUT4 #(
.INIT ( 16'h1054 ))
blk000007d9 (
.I0(sig000004d4),
.I1(sig000004d0),
.I2(sig000004d2),
.I3(sig000004d6),
.O(sig000005bf)
);
FDRS #(
.INIT ( 1'b0 ))
blk000007da (
.C(clk),
.D(sig000005be),
.R(sig000004d1),
.S(sig000004d0),
.Q(sig000004df)
);
LUT2 #(
.INIT ( 4'hE ))
blk000007db (
.I0(sig000004d2),
.I1(sig000004d4),
.O(sig000005be)
);
LUT5 #(
.INIT ( 32'hCF8FC080 ))
blk000007dc (
.I0(sig00000139),
.I1(sig00000127),
.I2(sig00000096),
.I3(sig00000095),
.I4(sig00000014),
.O(sig00000154)
);
LUT1 #(
.INIT ( 2'h2 ))
blk000007dd (
.I0(sig000002c0),
.O(sig00000281)
);
LUT1 #(
.INIT ( 2'h2 ))
blk000007de (
.I0(sig00000130),
.O(sig0000027f)
);
LUT2 #(
.INIT ( 4'h9 ))
blk000007df (
.I0(sig000004c5),
.I1(sig0000065c),
.O(sig00000511)
);
LUT1 #(
.INIT ( 2'h2 ))
blk000007e0 (
.I0(sig00000894),
.O(sig00000853)
);
LUT1 #(
.INIT ( 2'h2 ))
blk000007e1 (
.I0(sig0000085d),
.O(sig000007fb)
);
LUT1 #(
.INIT ( 2'h2 ))
blk000007e2 (
.I0(sig0000029f),
.O(sig00000280)
);
LUT4 #(
.INIT ( 16'h0F09 ))
blk000007e3 (
.I0(sig000007f3),
.I1(sig000004e1),
.I2(sig0000049c),
.I3(sig0000049b),
.O(sig000008a2)
);
LUT5 #(
.INIT ( 32'h8F808080 ))
blk000007e4 (
.I0(sig0000013c),
.I1(sig00000129),
.I2(sig00000096),
.I3(sig0000013a),
.I4(sig00000122),
.O(sig00000018)
);
LUT6 #(
.INIT ( 64'hFEAEAEAE54040404 ))
blk000007e5 (
.I0(sig00000095),
.I1(sig00000121),
.I2(sig00000096),
.I3(sig00000128),
.I4(sig0000013b),
.I5(sig00000018),
.O(sig00000151)
);
LUT5 #(
.INIT ( 32'hFFFFFFFE ))
blk000007e6 (
.I0(sig0000001e),
.I1(sig00000023),
.I2(sig00000024),
.I3(sig00000025),
.I4(sig00000026),
.O(sig00000019)
);
LUT6 #(
.INIT ( 64'hFFFFFFFFF8F00000 ))
blk000007e7 (
.I0(sig0000001c),
.I1(sig0000001f),
.I2(sig00000020),
.I3(sig0000001d),
.I4(sig000003de),
.I5(sig00000019),
.O(sig000003dd)
);
LUT5 #(
.INIT ( 32'h90000000 ))
blk000007e8 (
.I0(sig000004c5),
.I1(sig0000065c),
.I2(sig000005d9),
.I3(sig000005da),
.I4(sig000005d8),
.O(sig000005d7)
);
LUT3 #(
.INIT ( 8'h02 ))
blk000007e9 (
.I0(sig000006c3),
.I1(sig0000064d),
.I2(sig0000064c),
.O(sig00000730)
);
LUT3 #(
.INIT ( 8'h02 ))
blk000007ea (
.I0(sig000006c2),
.I1(sig0000064d),
.I2(sig0000064c),
.O(sig0000072f)
);
LUT3 #(
.INIT ( 8'h02 ))
blk000007eb (
.I0(sig000006c1),
.I1(sig0000064d),
.I2(sig0000064c),
.O(sig0000072e)
);
LUT3 #(
.INIT ( 8'h02 ))
blk000007ec (
.I0(sig000006c0),
.I1(sig0000064d),
.I2(sig0000064c),
.O(sig0000072d)
);
LUT3 #(
.INIT ( 8'h02 ))
blk000007ed (
.I0(sig000005ef),
.I1(sig00000897),
.I2(sig0000067d),
.O(sig00000767)
);
LUT3 #(
.INIT ( 8'h02 ))
blk000007ee (
.I0(sig000005f0),
.I1(sig00000897),
.I2(sig0000067d),
.O(sig00000766)
);
LUT3 #(
.INIT ( 8'h02 ))
blk000007ef (
.I0(sig000005fb),
.I1(sig00000897),
.I2(sig0000067d),
.O(sig00000765)
);
LUT3 #(
.INIT ( 8'h02 ))
blk000007f0 (
.I0(sig00000606),
.I1(sig00000897),
.I2(sig0000067d),
.O(sig00000764)
);
LUT3 #(
.INIT ( 8'h02 ))
blk000007f1 (
.I0(sig00000611),
.I1(sig00000897),
.I2(sig0000067d),
.O(sig00000763)
);
LUT3 #(
.INIT ( 8'h02 ))
blk000007f2 (
.I0(sig0000061c),
.I1(sig00000897),
.I2(sig0000067d),
.O(sig00000762)
);
LUT3 #(
.INIT ( 8'h02 ))
blk000007f3 (
.I0(sig00000623),
.I1(sig00000897),
.I2(sig0000067d),
.O(sig00000760)
);
LUT3 #(
.INIT ( 8'h02 ))
blk000007f4 (
.I0(sig00000624),
.I1(sig00000897),
.I2(sig0000067d),
.O(sig0000075f)
);
LUT3 #(
.INIT ( 8'h02 ))
blk000007f5 (
.I0(sig00000625),
.I1(sig00000897),
.I2(sig0000067d),
.O(sig0000075e)
);
LUT3 #(
.INIT ( 8'h02 ))
blk000007f6 (
.I0(sig00000626),
.I1(sig00000897),
.I2(sig0000067d),
.O(sig0000075d)
);
LUT3 #(
.INIT ( 8'h02 ))
blk000007f7 (
.I0(sig000005f1),
.I1(sig00000897),
.I2(sig0000067d),
.O(sig0000075c)
);
LUT3 #(
.INIT ( 8'h02 ))
blk000007f8 (
.I0(sig000005f2),
.I1(sig00000897),
.I2(sig0000067d),
.O(sig0000075b)
);
LUT3 #(
.INIT ( 8'h02 ))
blk000007f9 (
.I0(sig000005f3),
.I1(sig00000897),
.I2(sig0000067d),
.O(sig0000075a)
);
LUT3 #(
.INIT ( 8'h02 ))
blk000007fa (
.I0(sig000005f4),
.I1(sig00000897),
.I2(sig0000067d),
.O(sig00000759)
);
LUT3 #(
.INIT ( 8'h02 ))
blk000007fb (
.I0(sig000005f5),
.I1(sig00000897),
.I2(sig0000067d),
.O(sig00000758)
);
LUT3 #(
.INIT ( 8'h02 ))
blk000007fc (
.I0(sig000005f6),
.I1(sig00000897),
.I2(sig0000067d),
.O(sig00000757)
);
LUT3 #(
.INIT ( 8'h02 ))
blk000007fd (
.I0(sig00000351),
.I1(sig00000022),
.I2(sig00000021),
.O(sig000000ff)
);
LUT3 #(
.INIT ( 8'h02 ))
blk000007fe (
.I0(sig00000350),
.I1(sig00000022),
.I2(sig00000021),
.O(sig000000fe)
);
LUT3 #(
.INIT ( 8'h02 ))
blk000007ff (
.I0(sig0000034f),
.I1(sig00000022),
.I2(sig00000021),
.O(sig000000fd)
);
LUT3 #(
.INIT ( 8'h02 ))
blk00000800 (
.I0(sig0000034e),
.I1(sig00000022),
.I2(sig00000021),
.O(sig000000fc)
);
LUT3 #(
.INIT ( 8'h02 ))
blk00000801 (
.I0(sig0000034c),
.I1(sig00000022),
.I2(sig00000021),
.O(sig000000fb)
);
LUT3 #(
.INIT ( 8'h02 ))
blk00000802 (
.I0(sig0000034b),
.I1(sig00000022),
.I2(sig00000021),
.O(sig000000f9)
);
LUT3 #(
.INIT ( 8'h02 ))
blk00000803 (
.I0(sig0000034a),
.I1(sig00000022),
.I2(sig00000021),
.O(sig000000f8)
);
LUT3 #(
.INIT ( 8'h02 ))
blk00000804 (
.I0(sig00000349),
.I1(sig00000022),
.I2(sig00000021),
.O(sig000000f7)
);
LUT3 #(
.INIT ( 8'h02 ))
blk00000805 (
.I0(sig00000348),
.I1(sig00000022),
.I2(sig00000021),
.O(sig000000f6)
);
LUT3 #(
.INIT ( 8'h02 ))
blk00000806 (
.I0(sig00000347),
.I1(sig00000022),
.I2(sig00000021),
.O(sig000000f5)
);
LUT3 #(
.INIT ( 8'h02 ))
blk00000807 (
.I0(sig00000346),
.I1(sig00000022),
.I2(sig00000021),
.O(sig000000f4)
);
LUT3 #(
.INIT ( 8'h02 ))
blk00000808 (
.I0(sig00000345),
.I1(sig00000022),
.I2(sig00000021),
.O(sig000000f3)
);
LUT3 #(
.INIT ( 8'h02 ))
blk00000809 (
.I0(sig00000344),
.I1(sig00000022),
.I2(sig00000021),
.O(sig000000f2)
);
LUT3 #(
.INIT ( 8'h02 ))
blk0000080a (
.I0(sig00000343),
.I1(sig00000022),
.I2(sig00000021),
.O(sig000000f1)
);
LUT3 #(
.INIT ( 8'h02 ))
blk0000080b (
.I0(sig00000341),
.I1(sig00000022),
.I2(sig00000021),
.O(sig000000f0)
);
LUT3 #(
.INIT ( 8'h02 ))
blk0000080c (
.I0(sig00000340),
.I1(sig00000022),
.I2(sig00000021),
.O(sig000000ee)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk0000080d (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig000005ef),
.I3(sig000005f7),
.O(sig00000755)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk0000080e (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig000005f0),
.I3(sig000005f8),
.O(sig00000754)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk0000080f (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig000005fb),
.I3(sig000005f9),
.O(sig00000753)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk00000810 (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig00000606),
.I3(sig000005fa),
.O(sig00000752)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk00000811 (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig00000611),
.I3(sig000005fc),
.O(sig00000751)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk00000812 (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig0000061c),
.I3(sig000005fd),
.O(sig00000750)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk00000813 (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig00000623),
.I3(sig000005fe),
.O(sig0000074f)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk00000814 (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig00000624),
.I3(sig000005ff),
.O(sig0000074e)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk00000815 (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig00000625),
.I3(sig00000600),
.O(sig0000074d)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk00000816 (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig00000626),
.I3(sig00000601),
.O(sig0000074c)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk00000817 (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig000005f1),
.I3(sig00000602),
.O(sig0000074a)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk00000818 (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig000005f2),
.I3(sig00000603),
.O(sig00000749)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk00000819 (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig000005f3),
.I3(sig00000604),
.O(sig00000748)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk0000081a (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig000005f4),
.I3(sig00000605),
.O(sig00000747)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk0000081b (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig000005f5),
.I3(sig00000607),
.O(sig00000746)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk0000081c (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig000005f6),
.I3(sig00000608),
.O(sig00000745)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk0000081d (
.I0(sig0000064d),
.I1(sig0000064c),
.I2(sig000006c3),
.I3(sig000006bf),
.O(sig0000072c)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk0000081e (
.I0(sig0000064d),
.I1(sig0000064c),
.I2(sig000006c2),
.I3(sig000006be),
.O(sig0000072b)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk0000081f (
.I0(sig0000064d),
.I1(sig0000064c),
.I2(sig000006c1),
.I3(sig000006bc),
.O(sig00000729)
);
LUT4 #(
.INIT ( 16'h5140 ))
blk00000820 (
.I0(sig0000064d),
.I1(sig0000064c),
.I2(sig000006c0),
.I3(sig000006bb),
.O(sig00000728)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000821 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig0000046c),
.I3(sig000005a1),
.I4(sig00000454),
.O(sig000005ea)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000822 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000410),
.I3(sig000005a1),
.I4(sig00000444),
.O(sig000003d7)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000823 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000427),
.I3(sig000005a1),
.I4(sig000003f3),
.O(sig00000385)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000824 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000428),
.I3(sig000005a1),
.I4(sig000003f4),
.O(sig00000386)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000825 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000429),
.I3(sig000005a1),
.I4(sig000003f5),
.O(sig00000387)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000826 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig0000042a),
.I3(sig000005a1),
.I4(sig000003f6),
.O(sig00000388)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000827 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig0000042b),
.I3(sig000005a1),
.I4(sig000003f7),
.O(sig00000389)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000828 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig0000042d),
.I3(sig000005a1),
.I4(sig000003f9),
.O(sig0000038b)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000829 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig0000042e),
.I3(sig000005a1),
.I4(sig000003fa),
.O(sig0000038c)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk0000082a (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig0000042f),
.I3(sig000005a1),
.I4(sig000003fb),
.O(sig0000038d)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk0000082b (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000430),
.I3(sig000005a1),
.I4(sig000003fc),
.O(sig0000038e)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk0000082c (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000431),
.I3(sig000005a1),
.I4(sig000003fd),
.O(sig0000038f)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk0000082d (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000432),
.I3(sig000005a1),
.I4(sig000003fe),
.O(sig00000390)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk0000082e (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000433),
.I3(sig000005a1),
.I4(sig000003ff),
.O(sig00000391)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk0000082f (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000434),
.I3(sig000005a1),
.I4(sig00000400),
.O(sig00000392)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000830 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000435),
.I3(sig000005a1),
.I4(sig00000401),
.O(sig00000393)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000831 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000436),
.I3(sig000005a1),
.I4(sig00000402),
.O(sig00000394)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000832 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000438),
.I3(sig000005a1),
.I4(sig00000404),
.O(sig00000396)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000833 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000439),
.I3(sig000005a1),
.I4(sig00000405),
.O(sig00000397)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000834 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig0000043a),
.I3(sig000005a1),
.I4(sig00000406),
.O(sig00000398)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000835 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig0000043b),
.I3(sig000005a1),
.I4(sig00000407),
.O(sig00000399)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000836 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig0000043c),
.I3(sig000005a1),
.I4(sig00000408),
.O(sig0000039a)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000837 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig0000043d),
.I3(sig000005a1),
.I4(sig00000409),
.O(sig0000039b)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000838 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig0000043e),
.I3(sig000005a1),
.I4(sig0000040a),
.O(sig0000039c)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000839 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig0000043f),
.I3(sig000005a1),
.I4(sig0000040b),
.O(sig0000039d)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk0000083a (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000440),
.I3(sig000005a1),
.I4(sig0000040c),
.O(sig0000039e)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk0000083b (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000441),
.I3(sig000005a1),
.I4(sig0000040d),
.O(sig0000039f)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk0000083c (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000443),
.I3(sig000005a1),
.I4(sig0000040f),
.O(sig000003a1)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk0000083d (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000444),
.I3(sig000005a1),
.I4(sig00000410),
.O(sig000003a2)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk0000083e (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000415),
.I3(sig000005a1),
.I4(sig000003e1),
.O(sig00000374)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk0000083f (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000416),
.I3(sig000005a1),
.I4(sig000003e2),
.O(sig0000037f)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000840 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000421),
.I3(sig000005a1),
.I4(sig000003ed),
.O(sig0000038a)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000841 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig0000042c),
.I3(sig000005a1),
.I4(sig000003f8),
.O(sig00000395)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000842 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000437),
.I3(sig000005a1),
.I4(sig00000403),
.O(sig000003a0)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000843 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000442),
.I3(sig000005a1),
.I4(sig0000040e),
.O(sig000003a3)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000844 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000445),
.I3(sig000005a1),
.I4(sig00000411),
.O(sig000003a4)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000845 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000446),
.I3(sig000005a1),
.I4(sig00000412),
.O(sig000003a5)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000846 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000447),
.I3(sig000005a1),
.I4(sig00000413),
.O(sig000003a6)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000847 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000448),
.I3(sig000005a1),
.I4(sig00000414),
.O(sig000003a7)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000848 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000417),
.I3(sig000005a1),
.I4(sig000003e3),
.O(sig00000375)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000849 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000418),
.I3(sig000005a1),
.I4(sig000003e4),
.O(sig00000376)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk0000084a (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000419),
.I3(sig000005a1),
.I4(sig000003e5),
.O(sig00000377)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk0000084b (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig0000041a),
.I3(sig000005a1),
.I4(sig000003e6),
.O(sig00000378)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk0000084c (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig0000041b),
.I3(sig000005a1),
.I4(sig000003e7),
.O(sig00000379)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk0000084d (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig0000041c),
.I3(sig000005a1),
.I4(sig000003e8),
.O(sig0000037a)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk0000084e (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig0000041d),
.I3(sig000005a1),
.I4(sig000003e9),
.O(sig0000037b)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk0000084f (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig0000041e),
.I3(sig000005a1),
.I4(sig000003ea),
.O(sig0000037c)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000850 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig0000041f),
.I3(sig000005a1),
.I4(sig000003eb),
.O(sig0000037d)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000851 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000420),
.I3(sig000005a1),
.I4(sig000003ec),
.O(sig0000037e)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000852 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000422),
.I3(sig000005a1),
.I4(sig000003ee),
.O(sig00000380)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000853 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000423),
.I3(sig000005a1),
.I4(sig000003ef),
.O(sig00000381)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000854 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000424),
.I3(sig000005a1),
.I4(sig000003f0),
.O(sig00000382)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000855 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000425),
.I3(sig000005a1),
.I4(sig000003f1),
.O(sig00000383)
);
LUT5 #(
.INIT ( 32'hF0F7F080 ))
blk00000856 (
.I0(sig000005a0),
.I1(sig0000059f),
.I2(sig00000426),
.I3(sig000005a1),
.I4(sig000003f2),
.O(sig00000384)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000857 (
.I0(sig0000064d),
.I1(sig0000064c),
.I2(sig000006ba),
.I3(sig000006bf),
.I4(sig0000064e),
.I5(sig000006c3),
.O(sig00000727)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000858 (
.I0(sig0000064d),
.I1(sig0000064c),
.I2(sig000006b9),
.I3(sig000006be),
.I4(sig0000064e),
.I5(sig000006c2),
.O(sig00000726)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000859 (
.I0(sig0000064d),
.I1(sig0000064c),
.I2(sig000006b8),
.I3(sig000006bc),
.I4(sig0000064e),
.I5(sig000006c1),
.O(sig00000725)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk0000085a (
.I0(sig0000064d),
.I1(sig0000064c),
.I2(sig000006b7),
.I3(sig000006bb),
.I4(sig0000064e),
.I5(sig000006c0),
.O(sig00000724)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk0000085b (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig00000618),
.I3(sig00000607),
.I4(sig00000678),
.I5(sig000005f5),
.O(sig0000076c)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk0000085c (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig00000619),
.I3(sig00000608),
.I4(sig00000678),
.I5(sig000005f6),
.O(sig0000076b)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk0000085d (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig00000609),
.I3(sig000005f7),
.I4(sig00000678),
.I5(sig000005ef),
.O(sig00000744)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk0000085e (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig0000060a),
.I3(sig000005f8),
.I4(sig00000678),
.I5(sig000005f0),
.O(sig00000743)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk0000085f (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig0000060b),
.I3(sig000005f9),
.I4(sig00000678),
.I5(sig000005fb),
.O(sig00000742)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000860 (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig0000060c),
.I3(sig000005fa),
.I4(sig00000678),
.I5(sig00000606),
.O(sig00000741)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000861 (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig0000060d),
.I3(sig000005fc),
.I4(sig00000678),
.I5(sig00000611),
.O(sig0000073f)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000862 (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig0000060e),
.I3(sig000005fd),
.I4(sig00000678),
.I5(sig0000061c),
.O(sig0000073e)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000863 (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig0000060f),
.I3(sig000005fe),
.I4(sig00000678),
.I5(sig00000623),
.O(sig0000073d)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000864 (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig00000610),
.I3(sig000005ff),
.I4(sig00000678),
.I5(sig00000624),
.O(sig0000073c)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000865 (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig00000612),
.I3(sig00000600),
.I4(sig00000678),
.I5(sig00000625),
.O(sig0000073b)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000866 (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig00000613),
.I3(sig00000601),
.I4(sig00000678),
.I5(sig00000626),
.O(sig0000073a)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000867 (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig00000614),
.I3(sig00000602),
.I4(sig00000678),
.I5(sig000005f1),
.O(sig00000739)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000868 (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig00000615),
.I3(sig00000603),
.I4(sig00000678),
.I5(sig000005f2),
.O(sig00000738)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk00000869 (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig00000616),
.I3(sig00000604),
.I4(sig00000678),
.I5(sig000005f3),
.O(sig00000737)
);
LUT6 #(
.INIT ( 64'h5410FEBA54105410 ))
blk0000086a (
.I0(sig00000897),
.I1(sig0000067d),
.I2(sig00000617),
.I3(sig00000605),
.I4(sig00000678),
.I5(sig000005f4),
.O(sig00000736)
);
LUT6 #(
.INIT ( 64'hAAA80200AA882200 ))
blk0000086b (
.I0(sig000003e0),
.I1(sig000005a1),
.I2(sig0000059f),
.I3(sig00000415),
.I4(sig000003e1),
.I5(sig000005a0),
.O(sig000003a8)
);
LUT1 #(
.INIT ( 2'h2 ))
blk0000086c (
.I0(sig00000455),
.O(sig00000316)
);
INV blk0000086d (
.I(sig000004c4),
.O(sig0000050f)
);
INV blk0000086e (
.I(sig000004c9),
.O(sig00000515)
);
INV blk0000086f (
.I(sig000004ca),
.O(sig00000516)
);
INV blk00000870 (
.I(sig000004cb),
.O(sig00000517)
);
INV blk00000871 (
.I(sig000004cc),
.O(sig00000518)
);
LUT6 #(
.INIT ( 64'hF5F5F4F501010001 ))
blk00000872 (
.I0(sig000004d4),
.I1(sig000004d0),
.I2(sig000004d1),
.I3(sig000004d2),
.I4(sig000004d3),
.I5(sig000004d5),
.O(sig000005bc)
);
LUT6 #(
.INIT ( 64'hF5F4F4F401000000 ))
blk00000873 (
.I0(sig000004d4),
.I1(sig000004d0),
.I2(sig000004d1),
.I3(sig000004d2),
.I4(sig000004d3),
.I5(sig000004d5),
.O(sig000005bd)
);
MUXF7 blk00000874 (
.I0(sig000005bd),
.I1(sig000005bc),
.S(sig000004da),
.O(sig000005bb)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000875 (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig00000173),
.Q(sig00000157),
.Q15(NLW_blk00000875_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000876 (
.C(clk),
.CE(sig00000002),
.D(sig00000157),
.Q(sig0000018f)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000877 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig0000001d),
.Q(sig00000358),
.Q15(NLW_blk00000877_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000878 (
.C(clk),
.CE(sig00000002),
.D(sig00000358),
.Q(sig00000359)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000879 (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000005a3),
.Q(sig00000356),
.Q15(NLW_blk00000879_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000087a (
.C(clk),
.CE(sig00000002),
.D(sig00000356),
.Q(sig00000357)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000087b (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig00000174),
.Q(sig00000158),
.Q15(NLW_blk0000087b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000087c (
.C(clk),
.CE(sig00000002),
.D(sig00000158),
.Q(sig00000190)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000087d (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig0000017f),
.Q(sig00000163),
.Q15(NLW_blk0000087d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000087e (
.C(clk),
.CE(sig00000002),
.D(sig00000163),
.Q(sig0000019b)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000087f (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig0000018a),
.Q(sig0000016e),
.Q15(NLW_blk0000087f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000880 (
.C(clk),
.CE(sig00000002),
.D(sig0000016e),
.Q(sig000001a6)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000881 (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig00000188),
.Q(sig0000016c),
.Q15(NLW_blk00000881_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000882 (
.C(clk),
.CE(sig00000002),
.D(sig0000016c),
.Q(sig000001a4)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000883 (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig00000189),
.Q(sig0000016d),
.Q15(NLW_blk00000883_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000884 (
.C(clk),
.CE(sig00000002),
.D(sig0000016d),
.Q(sig000001a5)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000885 (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig0000018b),
.Q(sig0000016f),
.Q15(NLW_blk00000885_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000886 (
.C(clk),
.CE(sig00000002),
.D(sig0000016f),
.Q(sig000001a7)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000887 (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig0000018c),
.Q(sig00000170),
.Q15(NLW_blk00000887_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000888 (
.C(clk),
.CE(sig00000002),
.D(sig00000170),
.Q(sig000001a8)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000889 (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig00000175),
.Q(sig00000159),
.Q15(NLW_blk00000889_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000088a (
.C(clk),
.CE(sig00000002),
.D(sig00000159),
.Q(sig00000191)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000088b (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig0000018d),
.Q(sig00000171),
.Q15(NLW_blk0000088b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000088c (
.C(clk),
.CE(sig00000002),
.D(sig00000171),
.Q(sig000001a9)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000088d (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig0000018e),
.Q(sig00000172),
.Q15(NLW_blk0000088d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000088e (
.C(clk),
.CE(sig00000002),
.D(sig00000172),
.Q(sig000001aa)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000088f (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig00000176),
.Q(sig0000015a),
.Q15(NLW_blk0000088f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000890 (
.C(clk),
.CE(sig00000002),
.D(sig0000015a),
.Q(sig00000192)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000891 (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig00000177),
.Q(sig0000015b),
.Q15(NLW_blk00000891_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000892 (
.C(clk),
.CE(sig00000002),
.D(sig0000015b),
.Q(sig00000193)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000893 (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig00000178),
.Q(sig0000015c),
.Q15(NLW_blk00000893_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000894 (
.C(clk),
.CE(sig00000002),
.D(sig0000015c),
.Q(sig00000194)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000895 (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig00000179),
.Q(sig0000015d),
.Q15(NLW_blk00000895_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000896 (
.C(clk),
.CE(sig00000002),
.D(sig0000015d),
.Q(sig00000195)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000897 (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig0000017a),
.Q(sig0000015e),
.Q15(NLW_blk00000897_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000898 (
.C(clk),
.CE(sig00000002),
.D(sig0000015e),
.Q(sig00000196)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000899 (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig0000017b),
.Q(sig0000015f),
.Q15(NLW_blk00000899_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000089a (
.C(clk),
.CE(sig00000002),
.D(sig0000015f),
.Q(sig00000197)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000089b (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig0000017e),
.Q(sig00000162),
.Q15(NLW_blk0000089b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000089c (
.C(clk),
.CE(sig00000002),
.D(sig00000162),
.Q(sig0000019a)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000089d (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig0000017c),
.Q(sig00000160),
.Q15(NLW_blk0000089d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000089e (
.C(clk),
.CE(sig00000002),
.D(sig00000160),
.Q(sig00000198)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000089f (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig0000017d),
.Q(sig00000161),
.Q15(NLW_blk0000089f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008a0 (
.C(clk),
.CE(sig00000002),
.D(sig00000161),
.Q(sig00000199)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008a1 (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig00000180),
.Q(sig00000164),
.Q15(NLW_blk000008a1_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008a2 (
.C(clk),
.CE(sig00000002),
.D(sig00000164),
.Q(sig0000019c)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008a3 (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig00000181),
.Q(sig00000165),
.Q15(NLW_blk000008a3_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008a4 (
.C(clk),
.CE(sig00000002),
.D(sig00000165),
.Q(sig0000019d)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008a5 (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig00000182),
.Q(sig00000166),
.Q15(NLW_blk000008a5_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008a6 (
.C(clk),
.CE(sig00000002),
.D(sig00000166),
.Q(sig0000019e)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008a7 (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig00000183),
.Q(sig00000167),
.Q15(NLW_blk000008a7_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008a8 (
.C(clk),
.CE(sig00000002),
.D(sig00000167),
.Q(sig0000019f)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008a9 (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig00000184),
.Q(sig00000168),
.Q15(NLW_blk000008a9_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008aa (
.C(clk),
.CE(sig00000002),
.D(sig00000168),
.Q(sig000001a0)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008ab (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig00000185),
.Q(sig00000169),
.Q15(NLW_blk000008ab_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008ac (
.C(clk),
.CE(sig00000002),
.D(sig00000169),
.Q(sig000001a1)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008ad (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000001dd),
.Q(sig000001ab),
.Q15(NLW_blk000008ad_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008ae (
.C(clk),
.CE(sig00000002),
.D(sig000001ab),
.Q(sig000001c4)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008af (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig00000186),
.Q(sig0000016a),
.Q15(NLW_blk000008af_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008b0 (
.C(clk),
.CE(sig00000002),
.D(sig0000016a),
.Q(sig000001a2)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008b1 (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig00000187),
.Q(sig0000016b),
.Q15(NLW_blk000008b1_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008b2 (
.C(clk),
.CE(sig00000002),
.D(sig0000016b),
.Q(sig000001a3)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008b3 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000001de),
.Q(sig000001ac),
.Q15(NLW_blk000008b3_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008b4 (
.C(clk),
.CE(sig00000002),
.D(sig000001ac),
.Q(sig000001c5)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008b5 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000001e9),
.Q(sig000001b7),
.Q15(NLW_blk000008b5_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008b6 (
.C(clk),
.CE(sig00000002),
.D(sig000001b7),
.Q(sig000001d0)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008b7 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000001ef),
.Q(sig000001bd),
.Q15(NLW_blk000008b7_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008b8 (
.C(clk),
.CE(sig00000002),
.D(sig000001bd),
.Q(sig000001d6)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008b9 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000001f0),
.Q(sig000001be),
.Q15(NLW_blk000008b9_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008ba (
.C(clk),
.CE(sig00000002),
.D(sig000001be),
.Q(sig000001d7)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008bb (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000001f1),
.Q(sig000001bf),
.Q15(NLW_blk000008bb_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008bc (
.C(clk),
.CE(sig00000002),
.D(sig000001bf),
.Q(sig000001d8)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008bd (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000001f2),
.Q(sig000001c0),
.Q15(NLW_blk000008bd_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008be (
.C(clk),
.CE(sig00000002),
.D(sig000001c0),
.Q(sig000001d9)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008bf (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000001f5),
.Q(sig000001c3),
.Q15(NLW_blk000008bf_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008c0 (
.C(clk),
.CE(sig00000002),
.D(sig000001c3),
.Q(sig000001dc)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008c1 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000001f3),
.Q(sig000001c1),
.Q15(NLW_blk000008c1_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008c2 (
.C(clk),
.CE(sig00000002),
.D(sig000001c1),
.Q(sig000001da)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008c3 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000001f4),
.Q(sig000001c2),
.Q15(NLW_blk000008c3_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008c4 (
.C(clk),
.CE(sig00000002),
.D(sig000001c2),
.Q(sig000001db)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008c5 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000001df),
.Q(sig000001ad),
.Q15(NLW_blk000008c5_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008c6 (
.C(clk),
.CE(sig00000002),
.D(sig000001ad),
.Q(sig000001c6)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008c7 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000001e0),
.Q(sig000001ae),
.Q15(NLW_blk000008c7_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008c8 (
.C(clk),
.CE(sig00000002),
.D(sig000001ae),
.Q(sig000001c7)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008c9 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000001e3),
.Q(sig000001b1),
.Q15(NLW_blk000008c9_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008ca (
.C(clk),
.CE(sig00000002),
.D(sig000001b1),
.Q(sig000001ca)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008cb (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000001e1),
.Q(sig000001af),
.Q15(NLW_blk000008cb_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008cc (
.C(clk),
.CE(sig00000002),
.D(sig000001af),
.Q(sig000001c8)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008cd (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000001e2),
.Q(sig000001b0),
.Q15(NLW_blk000008cd_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008ce (
.C(clk),
.CE(sig00000002),
.D(sig000001b0),
.Q(sig000001c9)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008cf (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000001e4),
.Q(sig000001b2),
.Q15(NLW_blk000008cf_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008d0 (
.C(clk),
.CE(sig00000002),
.D(sig000001b2),
.Q(sig000001cb)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008d1 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000001e5),
.Q(sig000001b3),
.Q15(NLW_blk000008d1_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008d2 (
.C(clk),
.CE(sig00000002),
.D(sig000001b3),
.Q(sig000001cc)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008d3 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000001e8),
.Q(sig000001b6),
.Q15(NLW_blk000008d3_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008d4 (
.C(clk),
.CE(sig00000002),
.D(sig000001b6),
.Q(sig000001cf)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008d5 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000001e6),
.Q(sig000001b4),
.Q15(NLW_blk000008d5_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008d6 (
.C(clk),
.CE(sig00000002),
.D(sig000001b4),
.Q(sig000001cd)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008d7 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000001e7),
.Q(sig000001b5),
.Q15(NLW_blk000008d7_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008d8 (
.C(clk),
.CE(sig00000002),
.D(sig000001b5),
.Q(sig000001ce)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008d9 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000001ea),
.Q(sig000001b8),
.Q15(NLW_blk000008d9_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008da (
.C(clk),
.CE(sig00000002),
.D(sig000001b8),
.Q(sig000001d1)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008db (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000001eb),
.Q(sig000001b9),
.Q15(NLW_blk000008db_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008dc (
.C(clk),
.CE(sig00000002),
.D(sig000001b9),
.Q(sig000001d2)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008dd (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000001ec),
.Q(sig000001ba),
.Q15(NLW_blk000008dd_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008de (
.C(clk),
.CE(sig00000002),
.D(sig000001ba),
.Q(sig000001d3)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008df (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000001ed),
.Q(sig000001bb),
.Q15(NLW_blk000008df_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008e0 (
.C(clk),
.CE(sig00000002),
.D(sig000001bb),
.Q(sig000001d4)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008e1 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000001ee),
.Q(sig000001bc),
.Q15(NLW_blk000008e1_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008e2 (
.C(clk),
.CE(sig00000002),
.D(sig000001bc),
.Q(sig000001d5)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008e3 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000002),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000004ce),
.Q(sig000004cd),
.Q15(NLW_blk000008e3_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008e4 (
.C(clk),
.CE(sig00000002),
.D(sig000004cd),
.Q(sig000004cf)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008e5 (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000002),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000004df),
.Q(sig000004db),
.Q15(NLW_blk000008e5_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008e6 (
.C(clk),
.CE(sig00000002),
.D(sig000004db),
.Q(sig000004dd)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008e7 (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000002b5),
.Q(sig00000519),
.Q15(NLW_blk000008e7_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008e8 (
.C(clk),
.CE(sig00000002),
.D(sig00000519),
.Q(sig0000051a)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008e9 (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000002),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000004e0),
.Q(sig000004dc),
.Q15(NLW_blk000008e9_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008ea (
.C(clk),
.CE(sig00000002),
.D(sig000004dc),
.Q(sig000004de)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008eb (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000002),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000004d9),
.Q(sig000004d7),
.Q15(NLW_blk000008eb_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008ec (
.C(clk),
.CE(sig00000002),
.D(sig000004d7),
.Q(sig000004d8)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008ed (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000002),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000004ad),
.Q(sig000004b9),
.Q15(NLW_blk000008ed_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008ee (
.C(clk),
.CE(sig00000002),
.D(sig000004b9),
.Q(sig000004c4)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008ef (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000002),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000004b6),
.Q(sig000004c1),
.Q15(NLW_blk000008ef_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008f0 (
.C(clk),
.CE(sig00000002),
.D(sig000004c1),
.Q(sig000004cc)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008f1 (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000002),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000004b5),
.Q(sig000004c0),
.Q15(NLW_blk000008f1_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008f2 (
.C(clk),
.CE(sig00000002),
.D(sig000004c0),
.Q(sig000004cb)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008f3 (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000002),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000004b4),
.Q(sig000004bf),
.Q15(NLW_blk000008f3_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008f4 (
.C(clk),
.CE(sig00000002),
.D(sig000004bf),
.Q(sig000004ca)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008f5 (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000002),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000004b3),
.Q(sig000004be),
.Q15(NLW_blk000008f5_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008f6 (
.C(clk),
.CE(sig00000002),
.D(sig000004be),
.Q(sig000004c9)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008f7 (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000002),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000004b0),
.Q(sig000004bb),
.Q15(NLW_blk000008f7_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008f8 (
.C(clk),
.CE(sig00000002),
.D(sig000004bb),
.Q(sig000004c6)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008f9 (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000002),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000004b2),
.Q(sig000004bd),
.Q15(NLW_blk000008f9_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008fa (
.C(clk),
.CE(sig00000002),
.D(sig000004bd),
.Q(sig000004c8)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008fb (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000002),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000004b1),
.Q(sig000004bc),
.Q15(NLW_blk000008fb_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008fc (
.C(clk),
.CE(sig00000002),
.D(sig000004bc),
.Q(sig000004c7)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008fd (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000002),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000004af),
.Q(sig000004ba),
.Q15(NLW_blk000008fd_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000008fe (
.C(clk),
.CE(sig00000002),
.D(sig000004ba),
.Q(sig000004c5)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000008ff (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000002),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000004ac),
.Q(sig000004b8),
.Q15(NLW_blk000008ff_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000900 (
.C(clk),
.CE(sig00000002),
.D(sig000004b8),
.Q(sig000004c3)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000901 (
.A0(sig00000002),
.A1(sig00000001),
.A2(sig00000002),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig000004ab),
.Q(sig000004b7),
.Q15(NLW_blk00000901_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000902 (
.C(clk),
.CE(sig00000002),
.D(sig000004b7),
.Q(sig000004c2)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000903 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig00000896),
.Q(sig00000629),
.Q15(NLW_blk00000903_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000904 (
.C(clk),
.CE(sig00000002),
.D(sig00000629),
.Q(sig0000062b)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000905 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig00000897),
.Q(sig00000628),
.Q15(NLW_blk00000905_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000906 (
.C(clk),
.CE(sig00000002),
.D(sig00000628),
.Q(sig0000062a)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000907 (
.A0(sig00000001),
.A1(sig00000002),
.A2(sig00000001),
.A3(sig00000001),
.CE(sig00000002),
.CLK(clk),
.D(sig0000035b),
.Q(sig00000893),
.Q15(NLW_blk00000907_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000908 (
.C(clk),
.CE(sig00000002),
.D(sig00000893),
.Q(sig00000894)
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
(* Copyright (c) 2008-2012, 2015, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
(* begin hide *)
Require Import List.
Require Import CpdtTactics.
Definition bad : unit := tt.
Set Implicit Arguments.
Set Asymmetric Patterns.
(* end hide *)
(** %\chapter{Infinite Data and Proofs}% *)
(** In lazy functional programming languages like %\index{Haskell}%Haskell, infinite data structures are everywhere%~\cite{whyfp}%. Infinite lists and more exotic datatypes provide convenient abstractions for communication between parts of a program. Achieving similar convenience without infinite lazy structures would, in many cases, require acrobatic inversions of control flow.
%\index{laziness}%Laziness is easy to implement in Haskell, where all the definitions in a program may be thought of as mutually recursive. In such an unconstrained setting, it is easy to implement an infinite loop when you really meant to build an infinite list, where any finite prefix of the list should be forceable in finite time. Haskell programmers learn how to avoid such slip-ups. In Coq, such a laissez-faire policy is not good enough.
We spent some time in the last chapter discussing the %\index{Curry-Howard correspondence}%Curry-Howard isomorphism, where proofs are identified with functional programs. In such a setting, infinite loops, intended or otherwise, are disastrous. If Coq allowed the full breadth of definitions that Haskell did, we could code up an infinite loop and use it to prove any proposition vacuously. That is, the addition of general recursion would make CIC _inconsistent_. For an arbitrary proposition [P], we could write:
[[
Fixpoint bad (u : unit) : P := bad u.
]]
This would leave us with [bad tt] as a proof of [P].
There are also algorithmic considerations that make universal termination very desirable. We have seen how tactics like [reflexivity] compare terms up to equivalence under computational rules. Calls to recursive, pattern-matching functions are simplified automatically, with no need for explicit proof steps. It would be very hard to hold onto that kind of benefit if it became possible to write non-terminating programs; we would be running smack into the halting problem.
One solution is to use types to contain the possibility of non-termination. For instance, we can create a "non-termination monad," inside which we must write all of our general-recursive programs; several such approaches are surveyed in Chapter 7. This is a heavyweight solution, and so we would like to avoid it whenever possible.
Luckily, Coq has special support for a class of lazy data structures that happens to contain most examples found in Haskell. That mechanism,%\index{co-inductive types}% _co-inductive types_, is the subject of this chapter. *)
(** * Computing with Infinite Data *)
(** Let us begin with the most basic type of infinite data, _streams_, or lazy lists.%\index{Vernacular commands!CoInductive}% *)
Section stream.
Variable A : Type.
CoInductive stream : Type :=
| Cons : A -> stream -> stream.
End stream.
(* begin hide *)
(* begin thide *)
CoInductive evilStream := Nil.
(* end thide *)
(* end hide *)
(** The definition is surprisingly simple. Starting from the definition of [list], we just need to change the keyword [Inductive] to [CoInductive]. We could have left a [Nil] constructor in our definition, but we will leave it out to force all of our streams to be infinite.
How do we write down a stream constant? Obviously, simple application of constructors is not good enough, since we could only denote finite objects that way. Rather, whereas recursive definitions were necessary to _use_ values of recursive inductive types effectively, here we find that we need%\index{co-recursive definitions}% _co-recursive definitions_ to _build_ values of co-inductive types effectively.
We can define a stream consisting only of zeroes.%\index{Vernacular commands!CoFixpoint}% *)
CoFixpoint zeroes : stream nat := Cons 0 zeroes.
(* EX: Define a stream that alternates between [true] and [false]. *)
(* begin thide *)
(** We can also define a stream that alternates between [true] and [false]. *)
CoFixpoint trues_falses : stream bool := Cons true falses_trues
with falses_trues : stream bool := Cons false trues_falses.
(* end thide *)
(** Co-inductive values are fair game as arguments to recursive functions, and we can use that fact to write a function to take a finite approximation of a stream. *)
(* EX: Define a function to calculate a finite approximation of a stream, to a particular length. *)
(* begin thide *)
Fixpoint approx A (s : stream A) (n : nat) : list A :=
match n with
| O => nil
| S n' =>
match s with
| Cons h t => h :: approx t n'
end
end.
Eval simpl in approx zeroes 10.
(** %\vspace{-.15in}% [[
= 0 :: 0 :: 0 :: 0 :: 0 :: 0 :: 0 :: 0 :: 0 :: 0 :: nil
: list nat
]]
*)
Eval simpl in approx trues_falses 10.
(** %\vspace{-.15in}% [[
= true
:: false
:: true
:: false
:: true :: false :: true :: false :: true :: false :: nil
: list bool
]]
*)
(* end thide *)
(* begin hide *)
(* begin thide *)
Definition looper := 0.
(* end thide *)
(* end hide *)
(** So far, it looks like co-inductive types might be a magic bullet, allowing us to import all of the Haskeller's usual tricks. However, there are important restrictions that are dual to the restrictions on the use of inductive types. Fixpoints _consume_ values of inductive types, with restrictions on which _arguments_ may be passed in recursive calls. Dually, co-fixpoints _produce_ values of co-inductive types, with restrictions on what may be done with the _results_ of co-recursive calls.
The restriction for co-inductive types shows up as the%\index{guardedness condition}% _guardedness condition_. First, consider this stream definition, which would be legal in Haskell.
[[
CoFixpoint looper : stream nat := looper.
]]
<<
Error:
Recursive definition of looper is ill-formed.
In environment
looper : stream nat
unguarded recursive call in "looper"
>>
The rule we have run afoul of here is that _every co-recursive call must be guarded by a constructor_; that is, every co-recursive call must be a direct argument to a constructor of the co-inductive type we are generating. It is a good thing that this rule is enforced. If the definition of [looper] were accepted, our [approx] function would run forever when passed [looper], and we would have fallen into inconsistency.
Some familiar functions are easy to write in co-recursive fashion. *)
Section map.
Variables A B : Type.
Variable f : A -> B.
CoFixpoint map (s : stream A) : stream B :=
match s with
| Cons h t => Cons (f h) (map t)
end.
End map.
(* begin hide *)
(* begin thide *)
Definition filter := 0.
(* end thide *)
(* end hide *)
(** This code is a literal copy of that for the list [map] function, with the [nil] case removed and [Fixpoint] changed to [CoFixpoint]. Many other standard functions on lazy data structures can be implemented just as easily. Some, like [filter], cannot be implemented. Since the predicate passed to [filter] may reject every element of the stream, we cannot satisfy the guardedness condition.
The implications of the condition can be subtle. To illustrate how, we start off with another co-recursive function definition that _is_ legal. The function [interleave] takes two streams and produces a new stream that alternates between their elements. *)
Section interleave.
Variable A : Type.
CoFixpoint interleave (s1 s2 : stream A) : stream A :=
match s1, s2 with
| Cons h1 t1, Cons h2 t2 => Cons h1 (Cons h2 (interleave t1 t2))
end.
End interleave.
(** Now say we want to write a weird stuttering version of [map] that repeats elements in a particular way, based on interleaving. *)
Section map'.
Variables A B : Type.
Variable f : A -> B.
(* begin thide *)
(** %\vspace{-.15in}%[[
CoFixpoint map' (s : stream A) : stream B :=
match s with
| Cons h t => interleave (Cons (f h) (map' t)) (Cons (f h) (map' t))
end.
]]
%\vspace{-.15in}%We get another error message about an unguarded recursive call. *)
End map'.
(** What is going wrong here? Imagine that, instead of [interleave], we had called some other, less well-behaved function on streams. Here is one simpler example demonstrating the essential pitfall. We start by defining a standard function for taking the tail of a stream. Since streams are infinite, this operation is total. *)
Definition tl A (s : stream A) : stream A :=
match s with
| Cons _ s' => s'
end.
(** Coq rejects the following definition that uses [tl].
[[
CoFixpoint bad : stream nat := tl (Cons 0 bad).
]]
Imagine that Coq had accepted our definition, and consider how we might evaluate [approx bad 1]. We would be trying to calculate the first element in the stream [bad]. However, it is not hard to see that the definition of [bad] "begs the question": unfolding the definition of [tl], we see that we essentially say "define [bad] to equal itself"! Of course such an equation admits no single well-defined solution, which does not fit well with the determinism of Gallina reduction.
Coq's complete rule for co-recursive definitions includes not just the basic guardedness condition, but also a requirement about where co-recursive calls may occur. In particular, a co-recursive call must be a direct argument to a constructor, _nested only inside of other constructor calls or [fun] or [match] expressions_. In the definition of [bad], we erroneously nested the co-recursive call inside a call to [tl], and we nested inside a call to [interleave] in the definition of [map'].
Coq helps the user out a little by performing the guardedness check after using computation to simplify terms. For instance, any co-recursive function definition can be expanded by inserting extra calls to an identity function, and this change preserves guardedness. However, in other cases computational simplification can reveal why definitions are dangerous. Consider what happens when we inline the definition of [tl] in [bad]:
[[
CoFixpoint bad : stream nat := bad.
]]
This is the same looping definition we rejected earlier. A similar inlining process reveals an alternate view on our failed definition of [map']:
[[
CoFixpoint map' (s : stream A) : stream B :=
match s with
| Cons h t => Cons (f h) (Cons (f h) (interleave (map' t) (map' t)))
end.
]]
Clearly in this case the [map'] calls are not immediate arguments to constructors, so we violate the guardedness condition. *)
(* end thide *)
(** A more interesting question is why that condition is the right one. We can make an intuitive argument that the original [map'] definition is perfectly reasonable and denotes a well-understood transformation on streams, such that every output would behave properly with [approx]. The guardedness condition is an example of a syntactic check for%\index{productivity}% _productivity_ of co-recursive definitions. A productive definition can be thought of as one whose outputs can be forced in finite time to any finite approximation level, as with [approx]. If we replaced the guardedness condition with more involved checks, we might be able to detect and allow a broader range of productive definitions. However, mistakes in these checks could cause inconsistency, and programmers would need to understand the new, more complex checks. Coq's design strikes a balance between consistency and simplicity with its choice of guard condition, though we can imagine other worthwhile balances being struck, too. *)
(** * Infinite Proofs *)
(** Let us say we want to give two different definitions of a stream of all ones, and then we want to prove that they are equivalent. *)
CoFixpoint ones : stream nat := Cons 1 ones.
Definition ones' := map S zeroes.
(** The obvious statement of the equality is this: *)
Theorem ones_eq : ones = ones'.
(* begin hide *)
(* begin thide *)
Definition foo := @eq.
(* end thide *)
(* end hide *)
(** However, faced with the initial subgoal, it is not at all clear how this theorem can be proved. In fact, it is unprovable. The [eq] predicate that we use is fundamentally limited to equalities that can be demonstrated by finite, syntactic arguments. To prove this equivalence, we will need to introduce a new relation. *)
(* begin thide *)
Abort.
(** Co-inductive datatypes make sense by analogy from Haskell. What we need now is a _co-inductive proposition_. That is, we want to define a proposition whose proofs may be infinite, subject to the guardedness condition. The idea of infinite proofs does not show up in usual mathematics, but it can be very useful (unsurprisingly) for reasoning about infinite data structures. Besides examples from Haskell, infinite data and proofs will also turn out to be useful for modelling inherently infinite mathematical objects, like program executions.
We are ready for our first %\index{co-inductive predicates}%co-inductive predicate. *)
Section stream_eq.
Variable A : Type.
CoInductive stream_eq : stream A -> stream A -> Prop :=
| Stream_eq : forall h t1 t2,
stream_eq t1 t2
-> stream_eq (Cons h t1) (Cons h t2).
End stream_eq.
(** We say that two streams are equal if and only if they have the same heads and their tails are equal. We use the normal finite-syntactic equality for the heads, and we refer to our new equality recursively for the tails.
We can try restating the theorem with [stream_eq]. *)
Theorem ones_eq : stream_eq ones ones'.
(** Coq does not support tactical co-inductive proofs as well as it supports tactical inductive proofs. The usual starting point is the [cofix] tactic, which asks to structure this proof as a co-fixpoint. *)
cofix.
(** [[
ones_eq : stream_eq ones ones'
============================
stream_eq ones ones'
]]
It looks like this proof might be easier than we expected! *)
assumption.
(** <<
Proof completed.
>>
Unfortunately, we are due for some disappointment in our victory lap.
[[
Qed.
]]
<<
Error:
Recursive definition of ones_eq is ill-formed.
In environment
ones_eq : stream_eq ones ones'
unguarded recursive call in "ones_eq"
>>
Via the Curry-Howard correspondence, the same guardedness condition applies to our co-inductive proofs as to our co-inductive data structures. We should be grateful that this proof is rejected, because, if it were not, the same proof structure could be used to prove any co-inductive theorem vacuously, by direct appeal to itself!
Thinking about how Coq would generate a proof term from the proof script above, we see that the problem is that we are violating the guardedness condition. During our proofs, Coq can help us check whether we have yet gone wrong in this way. We can run the command [Guarded] in any context to see if it is possible to finish the proof in a way that will yield a properly guarded proof term.%\index{Vernacular commands!Guarded}%
[[
Guarded.
]]
Running [Guarded] here gives us the same error message that we got when we tried to run [Qed]. In larger proofs, [Guarded] can be helpful in detecting problems _before_ we think we are ready to run [Qed].
We need to start the co-induction by applying [stream_eq]'s constructor. To do that, we need to know that both arguments to the predicate are [Cons]es. Informally, this is trivial, but [simpl] is not able to help us. *)
Undo.
simpl.
(** [[
ones_eq : stream_eq ones ones'
============================
stream_eq ones ones'
]]
It turns out that we are best served by proving an auxiliary lemma. *)
Abort.
(** First, we need to define a function that seems pointless at first glance. *)
Definition frob A (s : stream A) : stream A :=
match s with
| Cons h t => Cons h t
end.
(** Next, we need to prove a theorem that seems equally pointless. *)
Theorem frob_eq : forall A (s : stream A), s = frob s.
destruct s; reflexivity.
Qed.
(** But, miraculously, this theorem turns out to be just what we needed. *)
Theorem ones_eq : stream_eq ones ones'.
cofix.
(** We can use the theorem to rewrite the two streams. *)
rewrite (frob_eq ones).
rewrite (frob_eq ones').
(** [[
ones_eq : stream_eq ones ones'
============================
stream_eq (frob ones) (frob ones')
]]
Now [simpl] is able to reduce the streams. *)
simpl.
(** [[
ones_eq : stream_eq ones ones'
============================
stream_eq (Cons 1 ones)
(Cons 1
((cofix map (s : stream nat) : stream nat :=
match s with
| Cons h t => Cons (S h) (map t)
end) zeroes))
]]
Note the [cofix] notation for anonymous co-recursion, which is analogous to the [fix] notation we have already seen for recursion. Since we have exposed the [Cons] structure of each stream, we can apply the constructor of [stream_eq]. *)
constructor.
(** [[
ones_eq : stream_eq ones ones'
============================
stream_eq ones
((cofix map (s : stream nat) : stream nat :=
match s with
| Cons h t => Cons (S h) (map t)
end) zeroes)
]]
Now, modulo unfolding of the definition of [map], we have matched our assumption. *)
assumption.
Qed.
(** Why did this silly-looking trick help? The answer has to do with the constraints placed on Coq's evaluation rules by the need for termination. The [cofix]-related restriction that foiled our first attempt at using [simpl] is dual to a restriction for [fix]. In particular, an application of an anonymous [fix] only reduces when the top-level structure of the recursive argument is known. Otherwise, we would be unfolding the recursive definition ad infinitum.
Fixpoints only reduce when enough is known about the _definitions_ of their arguments. Dually, co-fixpoints only reduce when enough is known about _how their results will be used_. In particular, a [cofix] is only expanded when it is the discriminee of a [match]. Rewriting with our superficially silly lemma wrapped new [match]es around the two [cofix]es, triggering reduction.
If [cofix]es reduced haphazardly, it would be easy to run into infinite loops in evaluation, since we are, after all, building infinite objects.
One common source of difficulty with co-inductive proofs is bad interaction with standard Coq automation machinery. If we try to prove [ones_eq'] with automation, like we have in previous inductive proofs, we get an invalid proof. *)
Theorem ones_eq' : stream_eq ones ones'.
cofix; crush.
(** %\vspace{-.25in}%[[
Guarded.
]]
%\vspace{-.25in}%
*)
Abort.
(** The standard [auto] machinery sees that our goal matches an assumption and so applies that assumption, even though this violates guardedness. A correct proof strategy for a theorem like this usually starts by [destruct]ing some parameter and running a custom tactic to figure out the first proof rule to apply for each case. Alternatively, there are tricks that can be played with "hiding" the co-inductive hypothesis.
%\medskip%
Must we always be cautious with automation in proofs by co-induction? Induction seems to have dual versions of the same pitfalls inherent in it, and yet we avoid those pitfalls by encapsulating safe Curry-Howard recursion schemes inside named induction principles. It turns out that we can usually do the same with%\index{co-induction principles}% _co-induction principles_. Let us take that tack here, so that we can arrive at an [induction x; crush]-style proof for [ones_eq'].
An induction principle is parameterized over a predicate characterizing what we mean to prove, _as a function of the inductive fact that we already know_. Dually, a co-induction principle ought to be parameterized over a predicate characterizing what we mean to prove, _as a function of the arguments to the co-inductive predicate that we are trying to prove_.
To state a useful principle for [stream_eq], it will be useful first to define the stream head function. *)
Definition hd A (s : stream A) : A :=
match s with
| Cons x _ => x
end.
(** Now we enter a section for the co-induction principle, based on %\index{Park's principle}%Park's principle as introduced in a tutorial by Gim%\'%enez%~\cite{IT}%. *)
Section stream_eq_coind.
Variable A : Type.
Variable R : stream A -> stream A -> Prop.
(** This relation generalizes the theorem we want to prove, defining a set of pairs of streams that we must eventually prove contains the particular pair we care about. *)
Hypothesis Cons_case_hd : forall s1 s2, R s1 s2 -> hd s1 = hd s2.
Hypothesis Cons_case_tl : forall s1 s2, R s1 s2 -> R (tl s1) (tl s2).
(** Two hypotheses characterize what makes a good choice of [R]: it enforces equality of stream heads, and it is %``%#<i>#hereditary#</i>#%''% in the sense that an [R] stream pair passes on "[R]-ness" to its tails. An established technical term for such a relation is%\index{bisimulation}% _bisimulation_. *)
(** Now it is straightforward to prove the principle, which says that any stream pair in [R] is equal. The reader may wish to step through the proof script to see what is going on. *)
Theorem stream_eq_coind : forall s1 s2, R s1 s2 -> stream_eq s1 s2.
cofix; destruct s1; destruct s2; intro.
generalize (Cons_case_hd H); intro Heq; simpl in Heq; rewrite Heq.
constructor.
apply stream_eq_coind.
apply (Cons_case_tl H).
Qed.
End stream_eq_coind.
(** To see why this proof is guarded, we can print it and verify that the one co-recursive call is an immediate argument to a constructor. *)
Print stream_eq_coind.
(** We omit the output and proceed to proving [ones_eq''] again. The only bit of ingenuity is in choosing [R], and in this case the most restrictive predicate works. *)
Theorem ones_eq'' : stream_eq ones ones'.
apply (stream_eq_coind (fun s1 s2 => s1 = ones /\ s2 = ones')); crush.
Qed.
(** Note that this proof achieves the proper reduction behavior via [hd] and [tl], rather than [frob] as in the last proof. All three functions pattern match on their arguments, catalyzing computation steps.
Compared to the inductive proofs that we are used to, it still seems unsatisfactory that we had to write out a choice of [R] in the last proof. An alternate is to capture a common pattern of co-recursion in a more specialized co-induction principle. For the current example, that pattern is: prove [stream_eq s1 s2] where [s1] and [s2] are defined as their own tails. *)
Section stream_eq_loop.
Variable A : Type.
Variables s1 s2 : stream A.
Hypothesis Cons_case_hd : hd s1 = hd s2.
Hypothesis loop1 : tl s1 = s1.
Hypothesis loop2 : tl s2 = s2.
(** The proof of the principle includes a choice of [R], so that we no longer need to make such choices thereafter. *)
Theorem stream_eq_loop : stream_eq s1 s2.
apply (stream_eq_coind (fun s1' s2' => s1' = s1 /\ s2' = s2)); crush.
Qed.
End stream_eq_loop.
Theorem ones_eq''' : stream_eq ones ones'.
apply stream_eq_loop; crush.
Qed.
(* end thide *)
(** Let us put [stream_eq_coind] through its paces a bit more, considering two different ways to compute infinite streams of all factorial values. First, we import the [fact] factorial function from the standard library. *)
Require Import Arith.
Print fact.
(** %\vspace{-.15in}%[[
fact =
fix fact (n : nat) : nat :=
match n with
| 0 => 1
| S n0 => S n0 * fact n0
end
: nat -> nat
]]
*)
(** The simplest way to compute the factorial stream involves calling [fact] afresh at each position. *)
CoFixpoint fact_slow' (n : nat) := Cons (fact n) (fact_slow' (S n)).
Definition fact_slow := fact_slow' 1.
(** A more clever, optimized method maintains an accumulator of the previous factorial, so that each new entry can be computed with a single multiplication. *)
CoFixpoint fact_iter' (cur acc : nat) := Cons acc (fact_iter' (S cur) (acc * cur)).
Definition fact_iter := fact_iter' 2 1.
(** We can verify that the streams are equal up to particular finite bounds. *)
Eval simpl in approx fact_iter 5.
(** %\vspace{-.15in}%[[
= 1 :: 2 :: 6 :: 24 :: 120 :: nil
: list nat
]]
*)
Eval simpl in approx fact_slow 5.
(** %\vspace{-.15in}%[[
= 1 :: 2 :: 6 :: 24 :: 120 :: nil
: list nat
]]
Now, to prove that the two versions are equivalent, it is helpful to prove (and add as a proof hint) a quick lemma about the computational behavior of [fact]. (I intentionally skip explaining its proof at this point.) *)
(* begin thide *)
Lemma fact_def : forall x n,
fact_iter' x (fact n * S n) = fact_iter' x (fact (S n)).
simpl; intros; f_equal; ring.
Qed.
Hint Resolve fact_def.
(** With the hint added, it is easy to prove an auxiliary lemma relating [fact_iter'] and [fact_slow']. The key bit of ingenuity is introduction of an existential quantifier for the shared parameter [n]. *)
Lemma fact_eq' : forall n, stream_eq (fact_iter' (S n) (fact n)) (fact_slow' n).
intro; apply (stream_eq_coind (fun s1 s2 => exists n, s1 = fact_iter' (S n) (fact n)
/\ s2 = fact_slow' n)); crush; eauto.
Qed.
(** The final theorem is a direct corollary of [fact_eq']. *)
Theorem fact_eq : stream_eq fact_iter fact_slow.
apply fact_eq'.
Qed.
(** As in the case of [ones_eq'], we may be unsatisfied that we needed to write down a choice of [R] that seems to duplicate information already present in a lemma statement. We can facilitate a simpler proof by defining a co-induction principle specialized to goals that begin with single universal quantifiers, and the strategy can be extended in a straightforward way to principles for other counts of quantifiers. (Our [stream_eq_loop] principle is effectively the instantiation of this technique to zero quantifiers.) *)
Section stream_eq_onequant.
Variables A B : Type.
(** We have the types [A], the domain of the one quantifier; and [B], the type of data found in the streams. *)
Variables f g : A -> stream B.
(** The two streams we compare must be of the forms [f x] and [g x], for some shared [x]. Note that this falls out naturally when [x] is a shared universally quantified variable in a lemma statement. *)
Hypothesis Cons_case_hd : forall x, hd (f x) = hd (g x).
Hypothesis Cons_case_tl : forall x, exists y, tl (f x) = f y /\ tl (g x) = g y.
(** These conditions are inspired by the bisimulation requirements, with a more general version of the [R] choice we made for [fact_eq'] inlined into the hypotheses of [stream_eq_coind]. *)
Theorem stream_eq_onequant : forall x, stream_eq (f x) (g x).
intro; apply (stream_eq_coind (fun s1 s2 => exists x, s1 = f x /\ s2 = g x)); crush; eauto.
Qed.
End stream_eq_onequant.
Lemma fact_eq'' : forall n, stream_eq (fact_iter' (S n) (fact n)) (fact_slow' n).
apply stream_eq_onequant; crush; eauto.
Qed.
(** We have arrived at one of our customary automated proofs, thanks to the new principle. *)
(* end thide *)
(** * Simple Modeling of Non-Terminating Programs *)
(** We close the chapter with a quick motivating example for more complex uses of co-inductive types. We will define a co-inductive semantics for a simple imperative programming language and use that semantics to prove the correctness of a trivial optimization that removes spurious additions by 0. We follow the technique of%\index{co-inductive big-step operational semantics}% _co-inductive big-step operational semantics_ %\cite{BigStep}%.
We define a suggestive synonym for [nat], as we will consider programs over infinitely many variables, represented as [nat]s. *)
Definition var := nat.
(** We define a type [vars] of maps from variables to values. To define a function [set] for setting a variable's value in a map, we use the standard library function [beq_nat] for comparing natural numbers. *)
Definition vars := var -> nat.
Definition set (vs : vars) (v : var) (n : nat) : vars :=
fun v' => if beq_nat v v' then n else vs v'.
(** We define a simple arithmetic expression language with variables, and we give it a semantics via an interpreter. *)
Inductive exp : Set :=
| Const : nat -> exp
| Var : var -> exp
| Plus : exp -> exp -> exp.
Fixpoint evalExp (vs : vars) (e : exp) : nat :=
match e with
| Const n => n
| Var v => vs v
| Plus e1 e2 => evalExp vs e1 + evalExp vs e2
end.
(** Finally, we define a language of commands. It includes variable assignment, sequencing, and a <<while>> form that repeats as long as its test expression evaluates to a nonzero value. *)
Inductive cmd : Set :=
| Assign : var -> exp -> cmd
| Seq : cmd -> cmd -> cmd
| While : exp -> cmd -> cmd.
(** We could define an inductive relation to characterize the results of command evaluation. However, such a relation would not capture _nonterminating_ executions. With a co-inductive relation, we can capture both cases. The parameters of the relation are an initial state, a command, and a final state. A program that does not terminate in a particular initial state is related to _any_ final state. For more realistic languages than this one, it is often possible for programs to _crash_, in which case a semantics would generally relate their executions to no final states; so relating safely non-terminating programs to all final states provides a crucial distinction. *)
CoInductive evalCmd : vars -> cmd -> vars -> Prop :=
| EvalAssign : forall vs v e, evalCmd vs (Assign v e) (set vs v (evalExp vs e))
| EvalSeq : forall vs1 vs2 vs3 c1 c2, evalCmd vs1 c1 vs2
-> evalCmd vs2 c2 vs3
-> evalCmd vs1 (Seq c1 c2) vs3
| EvalWhileFalse : forall vs e c, evalExp vs e = 0
-> evalCmd vs (While e c) vs
| EvalWhileTrue : forall vs1 vs2 vs3 e c, evalExp vs1 e <> 0
-> evalCmd vs1 c vs2
-> evalCmd vs2 (While e c) vs3
-> evalCmd vs1 (While e c) vs3.
(** Having learned our lesson in the last section, before proceeding, we build a co-induction principle for [evalCmd]. *)
Section evalCmd_coind.
Variable R : vars -> cmd -> vars -> Prop.
Hypothesis AssignCase : forall vs1 vs2 v e, R vs1 (Assign v e) vs2
-> vs2 = set vs1 v (evalExp vs1 e).
Hypothesis SeqCase : forall vs1 vs3 c1 c2, R vs1 (Seq c1 c2) vs3
-> exists vs2, R vs1 c1 vs2 /\ R vs2 c2 vs3.
Hypothesis WhileCase : forall vs1 vs3 e c, R vs1 (While e c) vs3
-> (evalExp vs1 e = 0 /\ vs3 = vs1)
\/ exists vs2, evalExp vs1 e <> 0 /\ R vs1 c vs2 /\ R vs2 (While e c) vs3.
(** The proof is routine. We make use of a form of %\index{tactics!destruct}%[destruct] that takes an%\index{intro pattern}% _intro pattern_ in an [as] clause. These patterns control how deeply we break apart the components of an inductive value, and we refer the reader to the Coq manual for more details. *)
Theorem evalCmd_coind : forall vs1 c vs2, R vs1 c vs2 -> evalCmd vs1 c vs2.
cofix; intros; destruct c.
rewrite (AssignCase H); constructor.
destruct (SeqCase H) as [? [? ?]]; econstructor; eauto.
destruct (WhileCase H) as [[? ?] | [? [? [? ?]]]]; subst; econstructor; eauto.
Qed.
End evalCmd_coind.
(** Now that we have a co-induction principle, we should use it to prove something! Our example is a trivial program optimizer that finds places to replace [0 + e] with [e]. *)
Fixpoint optExp (e : exp) : exp :=
match e with
| Plus (Const 0) e => optExp e
| Plus e1 e2 => Plus (optExp e1) (optExp e2)
| _ => e
end.
Fixpoint optCmd (c : cmd) : cmd :=
match c with
| Assign v e => Assign v (optExp e)
| Seq c1 c2 => Seq (optCmd c1) (optCmd c2)
| While e c => While (optExp e) (optCmd c)
end.
(** Before proving correctness of [optCmd], we prove a lemma about [optExp]. This is where we have to do the most work, choosing pattern match opportunities automatically. *)
(* begin thide *)
Lemma optExp_correct : forall vs e, evalExp vs (optExp e) = evalExp vs e.
induction e; crush;
repeat (match goal with
| [ |- context[match ?E with Const _ => _ | _ => _ end] ] => destruct E
| [ |- context[match ?E with O => _ | S _ => _ end] ] => destruct E
end; crush).
Qed.
Hint Rewrite optExp_correct.
(** The final theorem is easy to establish, using our co-induction principle and a bit of Ltac smarts that we leave unexplained for now. Curious readers can consult the Coq manual, or wait for the later chapters of this book about proof automation. At a high level, we show inclusions between behaviors, going in both directions between original and optimized programs. *)
Ltac finisher := match goal with
| [ H : evalCmd _ _ _ |- _ ] => ((inversion H; [])
|| (inversion H; [|])); subst
end; crush; eauto 10.
Lemma optCmd_correct1 : forall vs1 c vs2, evalCmd vs1 c vs2
-> evalCmd vs1 (optCmd c) vs2.
intros; apply (evalCmd_coind (fun vs1 c' vs2 => exists c, evalCmd vs1 c vs2
/\ c' = optCmd c)); eauto; crush;
match goal with
| [ H : _ = optCmd ?E |- _ ] => destruct E; simpl in *; discriminate
|| injection H; intros; subst
end; finisher.
Qed.
Lemma optCmd_correct2 : forall vs1 c vs2, evalCmd vs1 (optCmd c) vs2
-> evalCmd vs1 c vs2.
intros; apply (evalCmd_coind (fun vs1 c vs2 => evalCmd vs1 (optCmd c) vs2));
crush; finisher.
Qed.
Theorem optCmd_correct : forall vs1 c vs2, evalCmd vs1 (optCmd c) vs2
<-> evalCmd vs1 c vs2.
intuition; apply optCmd_correct1 || apply optCmd_correct2; assumption.
Qed.
(* end thide *)
(** In this form, the theorem tells us that the optimizer preserves observable behavior of both terminating and nonterminating programs, but we did not have to do more work than for the case of terminating programs alone. We merely took the natural inductive definition for terminating executions, made it co-inductive, and applied the appropriate co-induction principle. Curious readers might experiment with adding command constructs like <<if>>; the same proof script should continue working, after the co-induction principle is extended to the new evaluation rules. *)
|
module brainfuck_top
(
input clk, rst_n,
output LCD_BLON, // LCD Back Light ON/OFF
output LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN, // LCD Enable
output LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
inout [7:0] LCD_DATA, // LCD Data bus 8 bits
input [7:0] key_in,
input key_d_en,
output txd,
input rxd,
output of_err
);
wire [31:0] op;
reg op_en;
wire [11:0] dp;
wire [15:0] d_o;
wire w_en, w_sel, w_wait;
wire [15:0] d_i;
wire r_en, d_en, r_sel;
wire ram_w_en, ram_r_en;
reg ram_d_en;
wire [15:0] ram_d_i;
wire s_rst;
wire rst;
reg lcd_wen;
reg [8:0] lcd_wdt;
wire lcd_status;
wire [11:0] pc;
wire pc_r;
assign rst = !rst_n;
brainfuck bf( .clk(clk), .rst(rst), .s_rst(s_rst),
.pc(pc), .op_r_req(pc_r), .op(op), .op_den(op_en),
.dp_adr(dp), .data_out(d_o), .data_w_req(w_en), .data_w_sel(w_sel), .data_w_wait(w_wait),
.data_in(d_i), .data_r_req(r_en), .data_r_sel(r_sel), .data_den(d_en)
);
LCDCONTROL lcd(.CLK(clk), .RST(rst), .WRITE(lcd_wen), .WRDATA(lcd_wdt), .STATUS(lcd_status),
.LCD_BLON(LCD_BLON), .LCD_RW(LCD_RW), .LCD_EN(LCD_EN), .LCD_RS(LCD_RS), .LCD_DATA(LCD_DATA)
);
wire [8:0] cmd_in;
reg [8:0] cmd [31:0];
reg [5:0] cmd_len;
wire cmd_st, cmd_busy, cmd_en;
integer ci;
wire [7:0] udout;
wire udout_en;
uart uart_1( .clk(clk), .rst(rst), .txd(txd), .rxd(rxd), .din(cmd_in), .din_en(cmd_en),
.dout(udout), .dout_en(udout_en), .of_err(of_err)
);
always @(posedge clk or posedge rst) begin
if (rst) begin
cmd[0] <= 9'h38;
cmd[1] <= 9'h0c;
cmd[2] <= 9'h01;
cmd[3] <= 9'h06;
cmd[4] <= 9'h80;
for(ci=5; ci<32; ci=ci+1) begin
cmd[ci] <= 0;
end
cmd_len <= 6'd5;
end // if (rst)
else begin
if (cmd_st) begin
for(ci=0; ci<31; ci=ci+1) begin
cmd[ci] <= cmd[ci+1];
end
if (cmd_en) begin
cmd[cmd_len-6'h1] <= cmd_in;
end
else begin
cmd_len <= cmd_len - 6'h1;
end
end
else if (cmd_len < 6'd32 & cmd_en==1) begin
cmd[cmd_len] <= cmd_in;
cmd_len <= cmd_len + 6'h1;
end
end // else: !if(rst)
end // always @ (posedge clk or posedge rst)
assign cmd_st = (cmd_len>0 & cmd_busy==0);
assign cmd_busy = lcd_status | lcd_wen;
assign cmd_in = {1'b1, d_o[7:0]};
assign cmd_en = (w_en & w_sel) ? 1'b1 : 1'b0;
assign w_wait = (w_sel & cmd_len >= 6'h32) ? 1'b1 : 1'b0;
always @(posedge clk or posedge rst) begin
if (rst) begin
lcd_wen <= 0;
lcd_wdt <= 0;
end
else begin
if (cmd_st) begin
lcd_wen <= 1;
lcd_wdt <= cmd[0];
end
else begin
lcd_wen <= 0;
end
end // else: !if(rst)
end // always @ (posedge clk or rst)
// program memory
drom32 drom_inst ( .address ( pc ), .clock ( clk ), .q ( op ) );
// data memory
dmem16 dmem_inst (.address ( dp ), .clock ( clk ), .data ( d_o ), .wren ( ram_w_en ), .q ( ram_d_i ));
assign ram_w_en = (w_sel==0) ? w_en : 1'b0;
assign ram_r_en = (r_sel==0) ? r_en : 1'b0;
assign d_en = (r_sel==0) ? ram_d_en : key_d_en;
assign d_i = (r_sel==0) ? ram_d_i : {8'h0, key_in};
assign s_rst = 0;
always @(posedge clk or posedge rst) begin
if (rst)
op_en <= 0;
else
op_en <= pc_r;
end
always @(posedge clk or posedge rst) begin
if (rst)
ram_d_en <= 0;
else
ram_d_en <= ram_r_en;
end
endmodule // brainfuck_top
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O21A_2_V
`define SKY130_FD_SC_MS__O21A_2_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog wrapper for o21a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o21a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o21a_2 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o21a_2 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O21A_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__O21A_FUNCTIONAL_PP_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o21a (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21A_FUNCTIONAL_PP_V |
//-----------------------------------------------------------------------------
// qmfir_0_wrapper.v
//-----------------------------------------------------------------------------
(* x_core_info = "qmfir_v1_00_a" *)
module qmfir_0_wrapper
(
SPLB_Clk,
SPLB_Rst,
PLB_ABus,
PLB_UABus,
PLB_PAValid,
PLB_SAValid,
PLB_rdPrim,
PLB_wrPrim,
PLB_masterID,
PLB_abort,
PLB_busLock,
PLB_RNW,
PLB_BE,
PLB_MSize,
PLB_size,
PLB_type,
PLB_lockErr,
PLB_wrDBus,
PLB_wrBurst,
PLB_rdBurst,
PLB_wrPendReq,
PLB_rdPendReq,
PLB_wrPendPri,
PLB_rdPendPri,
PLB_reqPri,
PLB_TAttribute,
Sl_addrAck,
Sl_SSize,
Sl_wait,
Sl_rearbitrate,
Sl_wrDAck,
Sl_wrComp,
Sl_wrBTerm,
Sl_rdDBus,
Sl_rdWdAddr,
Sl_rdDAck,
Sl_rdComp,
Sl_rdBTerm,
Sl_MBusy,
Sl_MWrErr,
Sl_MRdErr,
Sl_MIRQ,
IP2INTC_Irpt
);
input SPLB_Clk;
input SPLB_Rst;
input [0:31] PLB_ABus;
input [0:31] PLB_UABus;
input PLB_PAValid;
input PLB_SAValid;
input PLB_rdPrim;
input PLB_wrPrim;
input [0:0] PLB_masterID;
input PLB_abort;
input PLB_busLock;
input PLB_RNW;
input [0:15] PLB_BE;
input [0:1] PLB_MSize;
input [0:3] PLB_size;
input [0:2] PLB_type;
input PLB_lockErr;
input [0:127] PLB_wrDBus;
input PLB_wrBurst;
input PLB_rdBurst;
input PLB_wrPendReq;
input PLB_rdPendReq;
input [0:1] PLB_wrPendPri;
input [0:1] PLB_rdPendPri;
input [0:1] PLB_reqPri;
input [0:15] PLB_TAttribute;
output Sl_addrAck;
output [0:1] Sl_SSize;
output Sl_wait;
output Sl_rearbitrate;
output Sl_wrDAck;
output Sl_wrComp;
output Sl_wrBTerm;
output [0:127] Sl_rdDBus;
output [0:3] Sl_rdWdAddr;
output Sl_rdDAck;
output Sl_rdComp;
output Sl_rdBTerm;
output [0:0] Sl_MBusy;
output [0:0] Sl_MWrErr;
output [0:0] Sl_MRdErr;
output [0:0] Sl_MIRQ;
output IP2INTC_Irpt;
qmfir
#(
.C_BASEADDR ( 32'hcea00000 ),
.C_HIGHADDR ( 32'hcea0ffff ),
.C_SPLB_AWIDTH ( 32 ),
.C_SPLB_DWIDTH ( 128 ),
.C_SPLB_NUM_MASTERS ( 1 ),
.C_SPLB_MID_WIDTH ( 1 ),
.C_SPLB_NATIVE_DWIDTH ( 32 ),
.C_SPLB_P2P ( 0 ),
.C_SPLB_SUPPORT_BURSTS ( 0 ),
.C_SPLB_SMALLEST_MASTER ( 128 ),
.C_SPLB_CLK_PERIOD_PS ( 8000 ),
.C_INCLUDE_DPHASE_TIMER ( 1 ),
.C_FAMILY ( "virtex5" ),
.C_MEM0_BASEADDR ( 32'hc1a20000 ),
.C_MEM0_HIGHADDR ( 32'hc1a2ffff ),
.C_MEM1_BASEADDR ( 32'hc1a00000 ),
.C_MEM1_HIGHADDR ( 32'hc1a0ffff ),
.C_MEM2_BASEADDR ( 32'hc1a40000 ),
.C_MEM2_HIGHADDR ( 32'hc1a4ffff )
)
qmfir_0 (
.SPLB_Clk ( SPLB_Clk ),
.SPLB_Rst ( SPLB_Rst ),
.PLB_ABus ( PLB_ABus ),
.PLB_UABus ( PLB_UABus ),
.PLB_PAValid ( PLB_PAValid ),
.PLB_SAValid ( PLB_SAValid ),
.PLB_rdPrim ( PLB_rdPrim ),
.PLB_wrPrim ( PLB_wrPrim ),
.PLB_masterID ( PLB_masterID ),
.PLB_abort ( PLB_abort ),
.PLB_busLock ( PLB_busLock ),
.PLB_RNW ( PLB_RNW ),
.PLB_BE ( PLB_BE ),
.PLB_MSize ( PLB_MSize ),
.PLB_size ( PLB_size ),
.PLB_type ( PLB_type ),
.PLB_lockErr ( PLB_lockErr ),
.PLB_wrDBus ( PLB_wrDBus ),
.PLB_wrBurst ( PLB_wrBurst ),
.PLB_rdBurst ( PLB_rdBurst ),
.PLB_wrPendReq ( PLB_wrPendReq ),
.PLB_rdPendReq ( PLB_rdPendReq ),
.PLB_wrPendPri ( PLB_wrPendPri ),
.PLB_rdPendPri ( PLB_rdPendPri ),
.PLB_reqPri ( PLB_reqPri ),
.PLB_TAttribute ( PLB_TAttribute ),
.Sl_addrAck ( Sl_addrAck ),
.Sl_SSize ( Sl_SSize ),
.Sl_wait ( Sl_wait ),
.Sl_rearbitrate ( Sl_rearbitrate ),
.Sl_wrDAck ( Sl_wrDAck ),
.Sl_wrComp ( Sl_wrComp ),
.Sl_wrBTerm ( Sl_wrBTerm ),
.Sl_rdDBus ( Sl_rdDBus ),
.Sl_rdWdAddr ( Sl_rdWdAddr ),
.Sl_rdDAck ( Sl_rdDAck ),
.Sl_rdComp ( Sl_rdComp ),
.Sl_rdBTerm ( Sl_rdBTerm ),
.Sl_MBusy ( Sl_MBusy ),
.Sl_MWrErr ( Sl_MWrErr ),
.Sl_MRdErr ( Sl_MRdErr ),
.Sl_MIRQ ( Sl_MIRQ ),
.IP2INTC_Irpt ( IP2INTC_Irpt )
);
endmodule
|
//
// Generated by Bluespec Compiler, version 2013.01.beta5 (build 30325, 2013-01-23)
//
// On Mon Feb 3 15:05:03 EST 2014
//
//
// Ports:
// Name I/O size props
// wciS0_SResp O 2 reg
// wciS0_SData O 32 reg
// wciS0_SThreadBusy O 1
// wciS0_SFlag O 2
// wmiM0_MCmd O 3
// wmiM0_MReqLast O 1
// wmiM0_MReqInfo O 1
// wmiM0_MAddrSpace O 1
// wmiM0_MAddr O 14
// wmiM0_MBurstLength O 12
// wmiM0_MDataValid O 1
// wmiM0_MDataLast O 1
// wmiM0_MData O 128
// wmiM0_MDataByteEn O 16
// wmiM0_MFlag O 32
// wmiM0_MReset_n O 1
// wsiM0_MCmd O 3
// wsiM0_MReqLast O 1
// wsiM0_MBurstPrecise O 1
// wsiM0_MBurstLength O 12
// wsiM0_MData O 128 reg
// wsiM0_MByteEn O 16 reg
// wsiM0_MReqInfo O 8
// wsiM0_MReset_n O 1
// wsiS0_SThreadBusy O 1
// wsiS0_SReset_n O 1
// wciS0_Clk I 1 clock
// wciS0_MReset_n I 1 reset
// wciS0_MCmd I 3
// wciS0_MAddrSpace I 1
// wciS0_MByteEn I 4
// wciS0_MAddr I 32
// wciS0_MData I 32
// wciS0_MFlag I 2 unused
// wmiM0_SResp I 2
// wmiM0_SData I 128
// wmiM0_SFlag I 32 reg
// wsiS0_MCmd I 3
// wsiS0_MBurstLength I 12
// wsiS0_MData I 128
// wsiS0_MByteEn I 16
// wsiS0_MReqInfo I 8
// wmiM0_SThreadBusy I 1 reg
// wmiM0_SDataThreadBusy I 1 reg
// wmiM0_SRespLast I 1 unused
// wmiM0_SReset_n I 1 reg
// wsiM0_SThreadBusy I 1 reg
// wsiM0_SReset_n I 1 reg
// wsiS0_MReqLast I 1
// wsiS0_MBurstPrecise I 1
// wsiS0_MReset_n I 1 reg
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkSMAdapter16B(wciS0_Clk,
wciS0_MReset_n,
wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData,
wciS0_SResp,
wciS0_SData,
wciS0_SThreadBusy,
wciS0_SFlag,
wciS0_MFlag,
wmiM0_MCmd,
wmiM0_MReqLast,
wmiM0_MReqInfo,
wmiM0_MAddrSpace,
wmiM0_MAddr,
wmiM0_MBurstLength,
wmiM0_MDataValid,
wmiM0_MDataLast,
wmiM0_MData,
wmiM0_MDataByteEn,
wmiM0_SResp,
wmiM0_SData,
wmiM0_SThreadBusy,
wmiM0_SDataThreadBusy,
wmiM0_SRespLast,
wmiM0_SFlag,
wmiM0_MFlag,
wmiM0_MReset_n,
wmiM0_SReset_n,
wsiM0_MCmd,
wsiM0_MReqLast,
wsiM0_MBurstPrecise,
wsiM0_MBurstLength,
wsiM0_MData,
wsiM0_MByteEn,
wsiM0_MReqInfo,
wsiM0_SThreadBusy,
wsiM0_MReset_n,
wsiM0_SReset_n,
wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo,
wsiS0_SThreadBusy,
wsiS0_SReset_n,
wsiS0_MReset_n);
parameter [31 : 0] smaCtrlInit = 32'b0;
parameter [0 : 0] hasDebugLogic = 1'b0;
input wciS0_Clk;
input wciS0_MReset_n;
// action method wciS0_mCmd
input [2 : 0] wciS0_MCmd;
// action method wciS0_mAddrSpace
input wciS0_MAddrSpace;
// action method wciS0_mByteEn
input [3 : 0] wciS0_MByteEn;
// action method wciS0_mAddr
input [31 : 0] wciS0_MAddr;
// action method wciS0_mData
input [31 : 0] wciS0_MData;
// value method wciS0_sResp
output [1 : 0] wciS0_SResp;
// value method wciS0_sData
output [31 : 0] wciS0_SData;
// value method wciS0_sThreadBusy
output wciS0_SThreadBusy;
// value method wciS0_sFlag
output [1 : 0] wciS0_SFlag;
// action method wciS0_mFlag
input [1 : 0] wciS0_MFlag;
// value method wmiM0_mCmd
output [2 : 0] wmiM0_MCmd;
// value method wmiM0_mReqLast
output wmiM0_MReqLast;
// value method wmiM0_mReqInfo
output wmiM0_MReqInfo;
// value method wmiM0_mAddrSpace
output wmiM0_MAddrSpace;
// value method wmiM0_mAddr
output [13 : 0] wmiM0_MAddr;
// value method wmiM0_mBurstLength
output [11 : 0] wmiM0_MBurstLength;
// value method wmiM0_mDataValid
output wmiM0_MDataValid;
// value method wmiM0_mDataLast
output wmiM0_MDataLast;
// value method wmiM0_mData
output [127 : 0] wmiM0_MData;
// value method wmiM0_mDataInfo
// value method wmiM0_mDataByteEn
output [15 : 0] wmiM0_MDataByteEn;
// action method wmiM0_sResp
input [1 : 0] wmiM0_SResp;
// action method wmiM0_sData
input [127 : 0] wmiM0_SData;
// action method wmiM0_sThreadBusy
input wmiM0_SThreadBusy;
// action method wmiM0_sDataThreadBusy
input wmiM0_SDataThreadBusy;
// action method wmiM0_sRespLast
input wmiM0_SRespLast;
// action method wmiM0_sFlag
input [31 : 0] wmiM0_SFlag;
// value method wmiM0_mFlag
output [31 : 0] wmiM0_MFlag;
// value method wmiM0_mReset_n
output wmiM0_MReset_n;
// action method wmiM0_sReset_n
input wmiM0_SReset_n;
// value method wsiM0_mCmd
output [2 : 0] wsiM0_MCmd;
// value method wsiM0_mReqLast
output wsiM0_MReqLast;
// value method wsiM0_mBurstPrecise
output wsiM0_MBurstPrecise;
// value method wsiM0_mBurstLength
output [11 : 0] wsiM0_MBurstLength;
// value method wsiM0_mData
output [127 : 0] wsiM0_MData;
// value method wsiM0_mByteEn
output [15 : 0] wsiM0_MByteEn;
// value method wsiM0_mReqInfo
output [7 : 0] wsiM0_MReqInfo;
// value method wsiM0_mDataInfo
// action method wsiM0_sThreadBusy
input wsiM0_SThreadBusy;
// value method wsiM0_mReset_n
output wsiM0_MReset_n;
// action method wsiM0_sReset_n
input wsiM0_SReset_n;
// action method wsiS0_mCmd
input [2 : 0] wsiS0_MCmd;
// action method wsiS0_mReqLast
input wsiS0_MReqLast;
// action method wsiS0_mBurstPrecise
input wsiS0_MBurstPrecise;
// action method wsiS0_mBurstLength
input [11 : 0] wsiS0_MBurstLength;
// action method wsiS0_mData
input [127 : 0] wsiS0_MData;
// action method wsiS0_mByteEn
input [15 : 0] wsiS0_MByteEn;
// action method wsiS0_mReqInfo
input [7 : 0] wsiS0_MReqInfo;
// action method wsiS0_mDataInfo
// value method wsiS0_sThreadBusy
output wsiS0_SThreadBusy;
// value method wsiS0_sReset_n
output wsiS0_SReset_n;
// action method wsiS0_mReset_n
input wsiS0_MReset_n;
// signals for module outputs
wire [127 : 0] wmiM0_MData, wsiM0_MData;
wire [31 : 0] wciS0_SData, wmiM0_MFlag;
wire [15 : 0] wmiM0_MDataByteEn, wsiM0_MByteEn;
wire [13 : 0] wmiM0_MAddr;
wire [11 : 0] wmiM0_MBurstLength, wsiM0_MBurstLength;
wire [7 : 0] wsiM0_MReqInfo;
wire [2 : 0] wmiM0_MCmd, wsiM0_MCmd;
wire [1 : 0] wciS0_SFlag, wciS0_SResp;
wire wciS0_SThreadBusy,
wmiM0_MAddrSpace,
wmiM0_MDataLast,
wmiM0_MDataValid,
wmiM0_MReqInfo,
wmiM0_MReqLast,
wmiM0_MReset_n,
wsiM0_MBurstPrecise,
wsiM0_MReqLast,
wsiM0_MReset_n,
wsiS0_SReset_n,
wsiS0_SThreadBusy;
// inlined wires
wire [168 : 0] respF_wDataIn_wget,
respF_wDataOut_wget,
wsiM_reqFifo_x_wire_wget,
wsiS_wsiReq_wget;
wire [145 : 0] wmi_dhF_x_wire_wget;
wire [129 : 0] wmi_wmiResponse_wget;
wire [127 : 0] wmi_Em_sData_w_wget, wsi_Es_mData_w_wget;
wire [95 : 0] wsiM_extStatusW_wget, wsiS_extStatusW_wget;
wire [71 : 0] wci_wslv_wciReq_wget;
wire [33 : 0] wci_wslv_respF_x_wire_wget;
wire [31 : 0] wci_wci_Es_mAddr_w_wget,
wci_wci_Es_mData_w_wget,
wmi_mFlagF_x_wire_wget,
wmi_reqF_x_wire_wget;
wire [15 : 0] wsi_Es_mByteEn_w_wget;
wire [11 : 0] fabRespCredit_acc_v1_wget,
fabRespCredit_acc_v2_wget,
wsi_Es_mBurstLength_w_wget;
wire [7 : 0] wsi_Es_mReqInfo_w_wget;
wire [3 : 0] wci_wci_Es_mByteEn_w_wget;
wire [2 : 0] wci_wci_Es_mCmd_w_wget,
wci_wslv_wEdge_wget,
wsi_Es_mCmd_w_wget;
wire [1 : 0] wmi_Em_sResp_w_wget;
wire fabRespCredit_acc_v1_whas,
fabRespCredit_acc_v2_whas,
mesgPreRequest_1_wget,
mesgPreRequest_1_whas,
respF_pwClear_whas,
respF_pwDequeue_whas,
respF_pwEnqueue_whas,
respF_wDataIn_whas,
respF_wDataOut_whas,
wci_wci_Es_mAddrSpace_w_wget,
wci_wci_Es_mAddrSpace_w_whas,
wci_wci_Es_mAddr_w_whas,
wci_wci_Es_mByteEn_w_whas,
wci_wci_Es_mCmd_w_whas,
wci_wci_Es_mData_w_whas,
wci_wslv_ctlAckReg_1_wget,
wci_wslv_ctlAckReg_1_whas,
wci_wslv_reqF_r_clr_whas,
wci_wslv_reqF_r_deq_whas,
wci_wslv_reqF_r_enq_whas,
wci_wslv_respF_dequeueing_whas,
wci_wslv_respF_enqueueing_whas,
wci_wslv_respF_x_wire_whas,
wci_wslv_sFlagReg_1_wget,
wci_wslv_sFlagReg_1_whas,
wci_wslv_sThreadBusy_pw_whas,
wci_wslv_wEdge_whas,
wci_wslv_wciReq_whas,
wci_wslv_wci_cfrd_pw_whas,
wci_wslv_wci_cfwr_pw_whas,
wci_wslv_wci_ctrl_pw_whas,
wmi_Em_sData_w_whas,
wmi_Em_sResp_w_whas,
wmi_dhF_dequeueing_whas,
wmi_dhF_enqueueing_whas,
wmi_dhF_x_wire_whas,
wmi_mFlagF_dequeueing_whas,
wmi_mFlagF_enqueueing_whas,
wmi_mFlagF_x_wire_whas,
wmi_operateD_1_wget,
wmi_operateD_1_whas,
wmi_peerIsReady_1_wget,
wmi_peerIsReady_1_whas,
wmi_reqF_dequeueing_whas,
wmi_reqF_enqueueing_whas,
wmi_reqF_x_wire_whas,
wmi_sDataThreadBusy_d_1_wget,
wmi_sDataThreadBusy_d_1_whas,
wmi_sThreadBusy_d_1_wget,
wmi_sThreadBusy_d_1_whas,
wmi_wmiResponse_whas,
wsiM_operateD_1_wget,
wsiM_operateD_1_whas,
wsiM_peerIsReady_1_wget,
wsiM_peerIsReady_1_whas,
wsiM_reqFifo_dequeueing_whas,
wsiM_reqFifo_enqueueing_whas,
wsiM_reqFifo_x_wire_whas,
wsiM_sThreadBusy_pw_whas,
wsiS_operateD_1_wget,
wsiS_operateD_1_whas,
wsiS_peerIsReady_1_wget,
wsiS_peerIsReady_1_whas,
wsiS_reqFifo_doResetClr_whas,
wsiS_reqFifo_doResetDeq_whas,
wsiS_reqFifo_doResetEnq_whas,
wsiS_reqFifo_r_clr_whas,
wsiS_reqFifo_r_deq_whas,
wsiS_reqFifo_r_enq_whas,
wsiS_sThreadBusy_dw_wget,
wsiS_sThreadBusy_dw_whas,
wsiS_wsiReq_whas,
wsi_Es_mBurstLength_w_whas,
wsi_Es_mBurstPrecise_w_whas,
wsi_Es_mByteEn_w_whas,
wsi_Es_mCmd_w_whas,
wsi_Es_mDataInfo_w_whas,
wsi_Es_mData_w_whas,
wsi_Es_mReqInfo_w_whas,
wsi_Es_mReqLast_w_whas;
// register abortCount
reg [31 : 0] abortCount;
wire [31 : 0] abortCount_D_IN;
wire abortCount_EN;
// register doAbort
reg doAbort;
wire doAbort_D_IN, doAbort_EN;
// register endOfMessage
reg endOfMessage;
wire endOfMessage_D_IN, endOfMessage_EN;
// register errCount
reg [127 : 0] errCount;
wire [127 : 0] errCount_D_IN;
wire errCount_EN;
// register fabRespCredit_value
reg [11 : 0] fabRespCredit_value;
wire [11 : 0] fabRespCredit_value_D_IN;
wire fabRespCredit_value_EN;
// register fabWordsCurReq
reg [13 : 0] fabWordsCurReq;
wire [13 : 0] fabWordsCurReq_D_IN;
wire fabWordsCurReq_EN;
// register fabWordsRemain
reg [13 : 0] fabWordsRemain;
wire [13 : 0] fabWordsRemain_D_IN;
wire fabWordsRemain_EN;
// register firstMsgReq
reg firstMsgReq;
wire firstMsgReq_D_IN, firstMsgReq_EN;
// register lastMesg
reg [31 : 0] lastMesg;
wire [31 : 0] lastMesg_D_IN;
wire lastMesg_EN;
// register mesgCount
reg [31 : 0] mesgCount;
reg [31 : 0] mesgCount_D_IN;
wire mesgCount_EN;
// register mesgLengthSoFar
reg [13 : 0] mesgLengthSoFar;
wire [13 : 0] mesgLengthSoFar_D_IN;
wire mesgLengthSoFar_EN;
// register mesgPreRequest
reg mesgPreRequest;
wire mesgPreRequest_D_IN, mesgPreRequest_EN;
// register mesgReqAddr
reg [13 : 0] mesgReqAddr;
wire [13 : 0] mesgReqAddr_D_IN;
wire mesgReqAddr_EN;
// register mesgReqOK
reg mesgReqOK;
wire mesgReqOK_D_IN, mesgReqOK_EN;
// register opcode
reg [8 : 0] opcode;
wire [8 : 0] opcode_D_IN;
wire opcode_EN;
// register readyToPush
reg readyToPush;
wire readyToPush_D_IN, readyToPush_EN;
// register readyToRequest
reg readyToRequest;
wire readyToRequest_D_IN, readyToRequest_EN;
// register respF_rCache
reg [181 : 0] respF_rCache;
wire [181 : 0] respF_rCache_D_IN;
wire respF_rCache_EN;
// register respF_rRdPtr
reg [11 : 0] respF_rRdPtr;
wire [11 : 0] respF_rRdPtr_D_IN;
wire respF_rRdPtr_EN;
// register respF_rWrPtr
reg [11 : 0] respF_rWrPtr;
wire [11 : 0] respF_rWrPtr_D_IN;
wire respF_rWrPtr_EN;
// register smaCtrl
reg [31 : 0] smaCtrl;
wire [31 : 0] smaCtrl_D_IN;
wire smaCtrl_EN;
// register thisMesg
reg [31 : 0] thisMesg;
reg [31 : 0] thisMesg_D_IN;
wire thisMesg_EN;
// register unrollCnt
reg [15 : 0] unrollCnt;
wire [15 : 0] unrollCnt_D_IN;
wire unrollCnt_EN;
// register valExpect
reg [127 : 0] valExpect;
wire [127 : 0] valExpect_D_IN;
wire valExpect_EN;
// register wci_wslv_cEdge
reg [2 : 0] wci_wslv_cEdge;
wire [2 : 0] wci_wslv_cEdge_D_IN;
wire wci_wslv_cEdge_EN;
// register wci_wslv_cState
reg [2 : 0] wci_wslv_cState;
wire [2 : 0] wci_wslv_cState_D_IN;
wire wci_wslv_cState_EN;
// register wci_wslv_ctlAckReg
reg wci_wslv_ctlAckReg;
wire wci_wslv_ctlAckReg_D_IN, wci_wslv_ctlAckReg_EN;
// register wci_wslv_ctlOpActive
reg wci_wslv_ctlOpActive;
wire wci_wslv_ctlOpActive_D_IN, wci_wslv_ctlOpActive_EN;
// register wci_wslv_illegalEdge
reg wci_wslv_illegalEdge;
wire wci_wslv_illegalEdge_D_IN, wci_wslv_illegalEdge_EN;
// register wci_wslv_isReset_isInReset
reg wci_wslv_isReset_isInReset;
wire wci_wslv_isReset_isInReset_D_IN, wci_wslv_isReset_isInReset_EN;
// register wci_wslv_nState
reg [2 : 0] wci_wslv_nState;
reg [2 : 0] wci_wslv_nState_D_IN;
wire wci_wslv_nState_EN;
// register wci_wslv_reqF_countReg
reg [1 : 0] wci_wslv_reqF_countReg;
wire [1 : 0] wci_wslv_reqF_countReg_D_IN;
wire wci_wslv_reqF_countReg_EN;
// register wci_wslv_respF_cntr_r
reg [1 : 0] wci_wslv_respF_cntr_r;
wire [1 : 0] wci_wslv_respF_cntr_r_D_IN;
wire wci_wslv_respF_cntr_r_EN;
// register wci_wslv_respF_q_0
reg [33 : 0] wci_wslv_respF_q_0;
reg [33 : 0] wci_wslv_respF_q_0_D_IN;
wire wci_wslv_respF_q_0_EN;
// register wci_wslv_respF_q_1
reg [33 : 0] wci_wslv_respF_q_1;
reg [33 : 0] wci_wslv_respF_q_1_D_IN;
wire wci_wslv_respF_q_1_EN;
// register wci_wslv_sFlagReg
reg wci_wslv_sFlagReg;
wire wci_wslv_sFlagReg_D_IN, wci_wslv_sFlagReg_EN;
// register wci_wslv_sThreadBusy_d
reg wci_wslv_sThreadBusy_d;
wire wci_wslv_sThreadBusy_d_D_IN, wci_wslv_sThreadBusy_d_EN;
// register wmi_busyWithMessage
reg wmi_busyWithMessage;
wire wmi_busyWithMessage_D_IN, wmi_busyWithMessage_EN;
// register wmi_dhF_cntr_r
reg [1 : 0] wmi_dhF_cntr_r;
wire [1 : 0] wmi_dhF_cntr_r_D_IN;
wire wmi_dhF_cntr_r_EN;
// register wmi_dhF_q_0
reg [145 : 0] wmi_dhF_q_0;
reg [145 : 0] wmi_dhF_q_0_D_IN;
wire wmi_dhF_q_0_EN;
// register wmi_dhF_q_1
reg [145 : 0] wmi_dhF_q_1;
reg [145 : 0] wmi_dhF_q_1_D_IN;
wire wmi_dhF_q_1_EN;
// register wmi_errorSticky
reg wmi_errorSticky;
wire wmi_errorSticky_D_IN, wmi_errorSticky_EN;
// register wmi_isReset_isInReset
reg wmi_isReset_isInReset;
wire wmi_isReset_isInReset_D_IN, wmi_isReset_isInReset_EN;
// register wmi_mFlagF_cntr_r
reg [1 : 0] wmi_mFlagF_cntr_r;
wire [1 : 0] wmi_mFlagF_cntr_r_D_IN;
wire wmi_mFlagF_cntr_r_EN;
// register wmi_mFlagF_q_0
reg [31 : 0] wmi_mFlagF_q_0;
reg [31 : 0] wmi_mFlagF_q_0_D_IN;
wire wmi_mFlagF_q_0_EN;
// register wmi_mFlagF_q_1
reg [31 : 0] wmi_mFlagF_q_1;
reg [31 : 0] wmi_mFlagF_q_1_D_IN;
wire wmi_mFlagF_q_1_EN;
// register wmi_operateD
reg wmi_operateD;
wire wmi_operateD_D_IN, wmi_operateD_EN;
// register wmi_peerIsReady
reg wmi_peerIsReady;
wire wmi_peerIsReady_D_IN, wmi_peerIsReady_EN;
// register wmi_reqF_cntr_r
reg [1 : 0] wmi_reqF_cntr_r;
wire [1 : 0] wmi_reqF_cntr_r_D_IN;
wire wmi_reqF_cntr_r_EN;
// register wmi_reqF_q_0
reg [31 : 0] wmi_reqF_q_0;
reg [31 : 0] wmi_reqF_q_0_D_IN;
wire wmi_reqF_q_0_EN;
// register wmi_reqF_q_1
reg [31 : 0] wmi_reqF_q_1;
reg [31 : 0] wmi_reqF_q_1_D_IN;
wire wmi_reqF_q_1_EN;
// register wmi_sDataThreadBusy_d
reg wmi_sDataThreadBusy_d;
wire wmi_sDataThreadBusy_d_D_IN, wmi_sDataThreadBusy_d_EN;
// register wmi_sFlagReg
reg [31 : 0] wmi_sFlagReg;
wire [31 : 0] wmi_sFlagReg_D_IN;
wire wmi_sFlagReg_EN;
// register wmi_sThreadBusy_d
reg wmi_sThreadBusy_d;
wire wmi_sThreadBusy_d_D_IN, wmi_sThreadBusy_d_EN;
// register wmi_statusR
reg [7 : 0] wmi_statusR;
wire [7 : 0] wmi_statusR_D_IN;
wire wmi_statusR_EN;
// register wmi_trafficSticky
reg wmi_trafficSticky;
wire wmi_trafficSticky_D_IN, wmi_trafficSticky_EN;
// register wmwtBeginCount
reg [31 : 0] wmwtBeginCount;
wire [31 : 0] wmwtBeginCount_D_IN;
wire wmwtBeginCount_EN;
// register wmwtFinalCount
reg [31 : 0] wmwtFinalCount;
wire [31 : 0] wmwtFinalCount_D_IN;
wire wmwtFinalCount_EN;
// register wmwtPushCount
reg [31 : 0] wmwtPushCount;
wire [31 : 0] wmwtPushCount_D_IN;
wire wmwtPushCount_EN;
// register wsiM_burstKind
reg [1 : 0] wsiM_burstKind;
wire [1 : 0] wsiM_burstKind_D_IN;
wire wsiM_burstKind_EN;
// register wsiM_errorSticky
reg wsiM_errorSticky;
wire wsiM_errorSticky_D_IN, wsiM_errorSticky_EN;
// register wsiM_iMesgCount
reg [31 : 0] wsiM_iMesgCount;
wire [31 : 0] wsiM_iMesgCount_D_IN;
wire wsiM_iMesgCount_EN;
// register wsiM_isReset_isInReset
reg wsiM_isReset_isInReset;
wire wsiM_isReset_isInReset_D_IN, wsiM_isReset_isInReset_EN;
// register wsiM_operateD
reg wsiM_operateD;
wire wsiM_operateD_D_IN, wsiM_operateD_EN;
// register wsiM_pMesgCount
reg [31 : 0] wsiM_pMesgCount;
wire [31 : 0] wsiM_pMesgCount_D_IN;
wire wsiM_pMesgCount_EN;
// register wsiM_peerIsReady
reg wsiM_peerIsReady;
wire wsiM_peerIsReady_D_IN, wsiM_peerIsReady_EN;
// register wsiM_reqFifo_cntr_r
reg [1 : 0] wsiM_reqFifo_cntr_r;
wire [1 : 0] wsiM_reqFifo_cntr_r_D_IN;
wire wsiM_reqFifo_cntr_r_EN;
// register wsiM_reqFifo_q_0
reg [168 : 0] wsiM_reqFifo_q_0;
reg [168 : 0] wsiM_reqFifo_q_0_D_IN;
wire wsiM_reqFifo_q_0_EN;
// register wsiM_reqFifo_q_1
reg [168 : 0] wsiM_reqFifo_q_1;
reg [168 : 0] wsiM_reqFifo_q_1_D_IN;
wire wsiM_reqFifo_q_1_EN;
// register wsiM_sThreadBusy_d
reg wsiM_sThreadBusy_d;
wire wsiM_sThreadBusy_d_D_IN, wsiM_sThreadBusy_d_EN;
// register wsiM_statusR
reg [7 : 0] wsiM_statusR;
wire [7 : 0] wsiM_statusR_D_IN;
wire wsiM_statusR_EN;
// register wsiM_tBusyCount
reg [31 : 0] wsiM_tBusyCount;
wire [31 : 0] wsiM_tBusyCount_D_IN;
wire wsiM_tBusyCount_EN;
// register wsiM_trafficSticky
reg wsiM_trafficSticky;
wire wsiM_trafficSticky_D_IN, wsiM_trafficSticky_EN;
// register wsiS_burstKind
reg [1 : 0] wsiS_burstKind;
wire [1 : 0] wsiS_burstKind_D_IN;
wire wsiS_burstKind_EN;
// register wsiS_errorSticky
reg wsiS_errorSticky;
wire wsiS_errorSticky_D_IN, wsiS_errorSticky_EN;
// register wsiS_iMesgCount
reg [31 : 0] wsiS_iMesgCount;
wire [31 : 0] wsiS_iMesgCount_D_IN;
wire wsiS_iMesgCount_EN;
// register wsiS_isReset_isInReset
reg wsiS_isReset_isInReset;
wire wsiS_isReset_isInReset_D_IN, wsiS_isReset_isInReset_EN;
// register wsiS_mesgWordLength
reg [11 : 0] wsiS_mesgWordLength;
wire [11 : 0] wsiS_mesgWordLength_D_IN;
wire wsiS_mesgWordLength_EN;
// register wsiS_operateD
reg wsiS_operateD;
wire wsiS_operateD_D_IN, wsiS_operateD_EN;
// register wsiS_pMesgCount
reg [31 : 0] wsiS_pMesgCount;
wire [31 : 0] wsiS_pMesgCount_D_IN;
wire wsiS_pMesgCount_EN;
// register wsiS_peerIsReady
reg wsiS_peerIsReady;
wire wsiS_peerIsReady_D_IN, wsiS_peerIsReady_EN;
// register wsiS_reqFifo_countReg
reg [1 : 0] wsiS_reqFifo_countReg;
wire [1 : 0] wsiS_reqFifo_countReg_D_IN;
wire wsiS_reqFifo_countReg_EN;
// register wsiS_reqFifo_levelsValid
reg wsiS_reqFifo_levelsValid;
wire wsiS_reqFifo_levelsValid_D_IN, wsiS_reqFifo_levelsValid_EN;
// register wsiS_statusR
reg [7 : 0] wsiS_statusR;
wire [7 : 0] wsiS_statusR_D_IN;
wire wsiS_statusR_EN;
// register wsiS_tBusyCount
reg [31 : 0] wsiS_tBusyCount;
wire [31 : 0] wsiS_tBusyCount_D_IN;
wire wsiS_tBusyCount_EN;
// register wsiS_trafficSticky
reg wsiS_trafficSticky;
wire wsiS_trafficSticky_D_IN, wsiS_trafficSticky_EN;
// register wsiS_wordCount
reg [11 : 0] wsiS_wordCount;
wire [11 : 0] wsiS_wordCount_D_IN;
wire wsiS_wordCount_EN;
// ports of submodule mesgTokenF
wire mesgTokenF_CLR,
mesgTokenF_DEQ,
mesgTokenF_EMPTY_N,
mesgTokenF_ENQ,
mesgTokenF_FULL_N;
// ports of submodule respF_memory
wire [168 : 0] respF_memory_DIA, respF_memory_DIB, respF_memory_DOB;
wire [10 : 0] respF_memory_ADDRA, respF_memory_ADDRB;
wire respF_memory_ENA, respF_memory_ENB, respF_memory_WEA, respF_memory_WEB;
// ports of submodule wci_wslv_reqF
wire [71 : 0] wci_wslv_reqF_D_IN, wci_wslv_reqF_D_OUT;
wire wci_wslv_reqF_CLR,
wci_wslv_reqF_DEQ,
wci_wslv_reqF_EMPTY_N,
wci_wslv_reqF_ENQ;
// ports of submodule wmi_respF
wire [129 : 0] wmi_respF_D_IN, wmi_respF_D_OUT;
wire wmi_respF_CLR,
wmi_respF_DEQ,
wmi_respF_EMPTY_N,
wmi_respF_ENQ,
wmi_respF_FULL_N;
// ports of submodule wsiS_reqFifo
wire [168 : 0] wsiS_reqFifo_D_IN, wsiS_reqFifo_D_OUT;
wire wsiS_reqFifo_CLR,
wsiS_reqFifo_DEQ,
wsiS_reqFifo_EMPTY_N,
wsiS_reqFifo_ENQ,
wsiS_reqFifo_FULL_N;
// rule scheduling signals
wire CAN_FIRE_RL_wmrd_mesgBodyPreRequest,
CAN_FIRE_RL_wmwt_mesgBegin,
CAN_FIRE_RL_wmwt_messagePush,
WILL_FIRE_RL_wci_cfrd,
WILL_FIRE_RL_wci_cfwr,
WILL_FIRE_RL_wci_ctrl_EiI,
WILL_FIRE_RL_wci_ctrl_IsO,
WILL_FIRE_RL_wci_ctrl_OrE,
WILL_FIRE_RL_wci_wslv_ctl_op_complete,
WILL_FIRE_RL_wci_wslv_ctl_op_start,
WILL_FIRE_RL_wci_wslv_respF_both,
WILL_FIRE_RL_wci_wslv_respF_decCtr,
WILL_FIRE_RL_wci_wslv_respF_incCtr,
WILL_FIRE_RL_wmi_dhF_both,
WILL_FIRE_RL_wmi_dhF_decCtr,
WILL_FIRE_RL_wmi_dhF_incCtr,
WILL_FIRE_RL_wmi_mFlagF_both,
WILL_FIRE_RL_wmi_mFlagF_decCtr,
WILL_FIRE_RL_wmi_mFlagF_incCtr,
WILL_FIRE_RL_wmi_reqF_both,
WILL_FIRE_RL_wmi_reqF_decCtr,
WILL_FIRE_RL_wmi_reqF_deq,
WILL_FIRE_RL_wmi_reqF_incCtr,
WILL_FIRE_RL_wmrd_mesgBodyRequest,
WILL_FIRE_RL_wmrd_mesgResptoWsi,
WILL_FIRE_RL_wmwt_doAbort,
WILL_FIRE_RL_wmwt_mesgBegin,
WILL_FIRE_RL_wmwt_messageFinalize,
WILL_FIRE_RL_wsiM_reqFifo_both,
WILL_FIRE_RL_wsiM_reqFifo_decCtr,
WILL_FIRE_RL_wsiM_reqFifo_deq,
WILL_FIRE_RL_wsiM_reqFifo_incCtr,
WILL_FIRE_RL_wsiS_reqFifo_enq,
WILL_FIRE_RL_wsiS_reqFifo_reset,
WILL_FIRE_RL_wsipass_doMessagePush;
// inputs to muxes for submodule ports
reg [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_2;
wire [168 : 0] MUX_wsiM_reqFifo_q_0_write_1__VAL_1,
MUX_wsiM_reqFifo_q_0_write_1__VAL_2,
MUX_wsiM_reqFifo_q_1_write_1__VAL_1,
MUX_wsiM_reqFifo_x_wire_wset_1__VAL_3;
wire [145 : 0] MUX_wmi_dhF_q_0_write_1__VAL_1,
MUX_wmi_dhF_q_0_write_1__VAL_2,
MUX_wmi_dhF_q_1_write_1__VAL_1;
wire [33 : 0] MUX_wci_wslv_respF_q_0_write_1__VAL_1,
MUX_wci_wslv_respF_q_1_write_1__VAL_1,
MUX_wci_wslv_respF_x_wire_wset_1__VAL_1,
MUX_wci_wslv_respF_x_wire_wset_1__VAL_2;
wire [31 : 0] MUX_mesgCount_write_1__VAL_2,
MUX_thisMesg_write_1__VAL_1,
MUX_thisMesg_write_1__VAL_2,
MUX_wmi_mFlagF_q_0_write_1__VAL_1,
MUX_wmi_mFlagF_q_1_write_1__VAL_1,
MUX_wmi_mFlagF_x_wire_wset_1__VAL_2,
MUX_wmi_reqF_q_0_write_1__VAL_1,
MUX_wmi_reqF_q_0_write_1__VAL_2,
MUX_wmi_reqF_q_1_write_1__VAL_1,
MUX_wmi_reqF_x_wire_wset_1__VAL_1,
MUX_wmi_reqF_x_wire_wset_1__VAL_2;
wire [15 : 0] MUX_unrollCnt_write_1__VAL_1, MUX_unrollCnt_write_1__VAL_2;
wire [13 : 0] MUX_fabWordsRemain_write_1__VAL_1,
MUX_fabWordsRemain_write_1__VAL_2,
MUX_mesgReqAddr_write_1__VAL_2;
wire [11 : 0] MUX_fabRespCredit_value_write_1__VAL_2;
wire [8 : 0] MUX_opcode_write_1__VAL_3;
wire [1 : 0] MUX_wci_wslv_respF_cntr_r_write_1__VAL_2,
MUX_wmi_dhF_cntr_r_write_1__VAL_2,
MUX_wmi_mFlagF_cntr_r_write_1__VAL_2,
MUX_wmi_reqF_cntr_r_write_1__VAL_2,
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1,
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2;
wire MUX_endOfMessage_write_1__SEL_1,
MUX_mesgCount_write_1__SEL_1,
MUX_mesgReqOK_write_1__SEL_3,
MUX_unrollCnt_write_1__SEL_1,
MUX_unrollCnt_write_1__SEL_2,
MUX_wci_wslv_illegalEdge_write_1__SEL_1,
MUX_wci_wslv_illegalEdge_write_1__VAL_1,
MUX_wci_wslv_respF_q_0_write_1__SEL_1,
MUX_wci_wslv_respF_q_0_write_1__SEL_2,
MUX_wci_wslv_respF_q_1_write_1__SEL_1,
MUX_wci_wslv_respF_q_1_write_1__SEL_2,
MUX_wmi_dhF_q_0_write_1__SEL_1,
MUX_wmi_dhF_q_0_write_1__SEL_2,
MUX_wmi_dhF_q_1_write_1__SEL_1,
MUX_wmi_dhF_q_1_write_1__SEL_2,
MUX_wmi_mFlagF_q_0_write_1__SEL_1,
MUX_wmi_mFlagF_q_0_write_1__SEL_2,
MUX_wmi_mFlagF_q_1_write_1__SEL_1,
MUX_wmi_mFlagF_q_1_write_1__SEL_2,
MUX_wmi_mFlagF_x_wire_wset_1__SEL_1,
MUX_wmi_reqF_q_0_write_1__SEL_1,
MUX_wmi_reqF_q_0_write_1__SEL_2,
MUX_wmi_reqF_q_1_write_1__SEL_1,
MUX_wmi_reqF_q_1_write_1__SEL_2,
MUX_wsiM_reqFifo_q_0_write_1__SEL_1,
MUX_wsiM_reqFifo_q_0_write_1__SEL_2,
MUX_wsiM_reqFifo_q_1_write_1__SEL_1,
MUX_wsiM_reqFifo_q_1_write_1__SEL_2,
MUX_wsiM_reqFifo_x_wire_wset_1__SEL_1,
MUX_wsiM_reqFifo_x_wire_wset_1__SEL_2,
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3;
// remaining internal signals
reg [63 : 0] v__h18073,
v__h22489,
v__h22548,
v__h24386,
v__h24569,
v__h24765,
v__h25422,
v__h3597,
v__h3772,
v__h3916;
reg [31 : 0] g_data__h24937;
wire [163 : 0] IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d437;
wire [31 : 0] rdat__h24980,
rdat__h24986,
rdat__h24992,
rdat__h25005,
rdat__h25028,
rdat__h25128,
rdat__h25142,
rdat__h25150,
rdat__h25156,
rdat__h25170,
rdat__h25178,
rdat__h25184,
rdat__h25190,
rdat__h25196,
rdat__h25202,
rdat__h25212,
value__h6387,
x__h18676;
wire [23 : 0] b__h17784,
mesgMetaF_length__h23070,
residue__h17647,
x__h17904;
wire [15 : 0] sendData_byteEn__h18619,
wsiBurstLength__h18535,
x__h25032,
x_length__h23961;
wire [13 : 0] b__h18157, mlB__h22903, mlInc__h22902;
wire [11 : 0] b__h14802, sendData_burstLength__h18617, x__h16103, x__h16253;
wire [7 : 0] mesgMetaF_opcode__h23069;
wire [4 : 0] x__h23108,
x__h23120,
x__h23132,
x__h23144,
x__h23156,
x__h23168,
x__h23180,
x__h23192,
x__h23204,
x__h23216,
x__h23228,
x__h23240,
x__h23252,
x__h23264,
x__h23276,
y__h23109,
y__h23121,
y__h23133,
y__h23145,
y__h23157,
y__h23169,
y__h23181,
y__h23193,
y__h23205,
y__h23217,
y__h23229,
y__h23241,
y__h23253,
y__h23265,
y__h23277;
wire [2 : 0] IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d431;
wire [1 : 0] wci_wslv_respF_cntr_r_8_MINUS_1___d27,
wmi_dhF_cntr_r_05_MINUS_1___d213,
wmi_mFlagF_cntr_r_83_MINUS_1___d191,
wmi_reqF_cntr_r_61_MINUS_1___d169;
wire NOT_wmi_reqF_cntr_r_61_EQ_2_73_74_AND_wmi_oper_ETC___d521,
_dfoo1,
_dfoo11,
_dfoo13,
_dfoo15,
_dfoo17,
_dfoo19,
_dfoo3,
_dfoo5,
_dfoo7,
_dfoo9,
wmi_respF_i_notEmpty__34_AND_smaCtrl_62_BIT_4__ETC___d539,
wsiS_reqFifo_i_notEmpty__61_AND_NOT_smaCtrl_62_ETC___d667,
x__h18328,
x__h25206;
// value method wciS0_sResp
assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ;
// value method wciS0_sData
assign wciS0_SData = wci_wslv_respF_q_0[31:0] ;
// value method wciS0_sThreadBusy
assign wciS0_SThreadBusy =
wci_wslv_reqF_countReg > 2'd1 || wci_wslv_isReset_isInReset ;
// value method wciS0_sFlag
assign wciS0_SFlag = { 1'd1, wci_wslv_sFlagReg } ;
// value method wmiM0_mCmd
assign wmiM0_MCmd = wmi_sThreadBusy_d ? 3'd0 : wmi_reqF_q_0[31:29] ;
// value method wmiM0_mReqLast
assign wmiM0_MReqLast = !wmi_sThreadBusy_d && wmi_reqF_q_0[28] ;
// value method wmiM0_mReqInfo
assign wmiM0_MReqInfo = !wmi_sThreadBusy_d && wmi_reqF_q_0[27] ;
// value method wmiM0_mAddrSpace
assign wmiM0_MAddrSpace = !wmi_sThreadBusy_d && wmi_reqF_q_0[26] ;
// value method wmiM0_mAddr
assign wmiM0_MAddr = wmi_sThreadBusy_d ? 14'd0 : wmi_reqF_q_0[25:12] ;
// value method wmiM0_mBurstLength
assign wmiM0_MBurstLength = wmi_sThreadBusy_d ? 12'd0 : wmi_reqF_q_0[11:0] ;
// value method wmiM0_mDataValid
assign wmiM0_MDataValid = !wmi_sDataThreadBusy_d && wmi_dhF_q_0[145] ;
// value method wmiM0_mDataLast
assign wmiM0_MDataLast = !wmi_sDataThreadBusy_d && wmi_dhF_q_0[144] ;
// value method wmiM0_mData
assign wmiM0_MData = wmi_sDataThreadBusy_d ? 128'd0 : wmi_dhF_q_0[143:16] ;
// value method wmiM0_mDataByteEn
assign wmiM0_MDataByteEn =
wmi_sDataThreadBusy_d ? 16'd0 : wmi_dhF_q_0[15:0] ;
// value method wmiM0_mFlag
assign wmiM0_MFlag = wmi_sThreadBusy_d ? 32'd0 : wmi_mFlagF_q_0 ;
// value method wmiM0_mReset_n
assign wmiM0_MReset_n = !wmi_isReset_isInReset && wmi_operateD ;
// value method wsiM0_mCmd
assign wsiM0_MCmd = wsiM_sThreadBusy_d ? 3'd0 : wsiM_reqFifo_q_0[168:166] ;
// value method wsiM0_mReqLast
assign wsiM0_MReqLast = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[165] ;
// value method wsiM0_mBurstPrecise
assign wsiM0_MBurstPrecise = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[164] ;
// value method wsiM0_mBurstLength
assign wsiM0_MBurstLength =
wsiM_sThreadBusy_d ? 12'd0 : wsiM_reqFifo_q_0[163:152] ;
// value method wsiM0_mData
assign wsiM0_MData = wsiM_reqFifo_q_0[151:24] ;
// value method wsiM0_mByteEn
assign wsiM0_MByteEn = wsiM_reqFifo_q_0[23:8] ;
// value method wsiM0_mReqInfo
assign wsiM0_MReqInfo = wsiM_sThreadBusy_d ? 8'd0 : wsiM_reqFifo_q_0[7:0] ;
// value method wsiM0_mReset_n
assign wsiM0_MReset_n = !wsiM_isReset_isInReset && wsiM_operateD ;
// value method wsiS0_sThreadBusy
assign wsiS0_SThreadBusy =
!wsiS_sThreadBusy_dw_whas || wsiS_sThreadBusy_dw_wget ;
// value method wsiS0_sReset_n
assign wsiS0_SReset_n = !wsiS_isReset_isInReset && wsiS_operateD ;
// submodule mesgTokenF
FIFO10 #(.guarded(32'd1)) mesgTokenF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.ENQ(mesgTokenF_ENQ),
.DEQ(mesgTokenF_DEQ),
.CLR(mesgTokenF_CLR),
.FULL_N(mesgTokenF_FULL_N),
.EMPTY_N(mesgTokenF_EMPTY_N));
// submodule respF_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd11),
.DATA_WIDTH(32'd169),
.MEMSIZE(12'd2048)) respF_memory(.CLKA(wciS0_Clk),
.CLKB(wciS0_Clk),
.ADDRA(respF_memory_ADDRA),
.ADDRB(respF_memory_ADDRB),
.DIA(respF_memory_DIA),
.DIB(respF_memory_DIB),
.WEA(respF_memory_WEA),
.WEB(respF_memory_WEB),
.ENA(respF_memory_ENA),
.ENB(respF_memory_ENB),
.DOA(),
.DOB(respF_memory_DOB));
// submodule wci_wslv_reqF
SizedFIFO #(.p1width(32'd72),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wci_wslv_reqF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wci_wslv_reqF_D_IN),
.ENQ(wci_wslv_reqF_ENQ),
.DEQ(wci_wslv_reqF_DEQ),
.CLR(wci_wslv_reqF_CLR),
.D_OUT(wci_wslv_reqF_D_OUT),
.FULL_N(),
.EMPTY_N(wci_wslv_reqF_EMPTY_N));
// submodule wmi_respF
FIFO2 #(.width(32'd130), .guarded(32'd1)) wmi_respF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wmi_respF_D_IN),
.ENQ(wmi_respF_ENQ),
.DEQ(wmi_respF_DEQ),
.CLR(wmi_respF_CLR),
.D_OUT(wmi_respF_D_OUT),
.FULL_N(wmi_respF_FULL_N),
.EMPTY_N(wmi_respF_EMPTY_N));
// submodule wsiS_reqFifo
SizedFIFO #(.p1width(32'd169),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wsiS_reqFifo(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wsiS_reqFifo_D_IN),
.ENQ(wsiS_reqFifo_ENQ),
.DEQ(wsiS_reqFifo_DEQ),
.CLR(wsiS_reqFifo_CLR),
.D_OUT(wsiS_reqFifo_D_OUT),
.FULL_N(wsiS_reqFifo_FULL_N),
.EMPTY_N(wsiS_reqFifo_EMPTY_N));
// rule RL_wmrd_mesgBodyPreRequest
assign CAN_FIRE_RL_wmrd_mesgBodyPreRequest =
wci_wslv_cState == 3'd2 &&
(smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 ||
smaCtrl[3:0] == 4'h9) &&
fabWordsRemain != 14'd0 &&
(fabRespCredit_value ^ 12'h800) > 12'd2048 &&
mesgReqOK ;
// rule RL_wmrd_mesgBodyRequest
assign WILL_FIRE_RL_wmrd_mesgBodyRequest =
NOT_wmi_reqF_cntr_r_61_EQ_2_73_74_AND_wmi_oper_ETC___d521 &&
wci_wslv_cState == 3'd2 &&
(smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 ||
smaCtrl[3:0] == 4'h9) &&
mesgPreRequest ;
// rule RL_wci_wslv_ctl_op_start
assign WILL_FIRE_RL_wci_wslv_ctl_op_start =
wci_wslv_reqF_EMPTY_N && wci_wslv_wci_ctrl_pw_whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_ctrl_EiI
assign WILL_FIRE_RL_wci_ctrl_EiI =
wci_wslv_wci_ctrl_pw_whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd0 &&
wci_wslv_reqF_D_OUT[36:34] == 3'd0 ;
// rule RL_wci_ctrl_OrE
assign WILL_FIRE_RL_wci_ctrl_OrE =
wci_wslv_wci_ctrl_pw_whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd2 &&
wci_wslv_reqF_D_OUT[36:34] == 3'd3 ;
// rule RL_wmi_reqF_deq
assign WILL_FIRE_RL_wmi_reqF_deq =
wmi_operateD && wmi_peerIsReady && !wmi_sThreadBusy_d ;
// rule RL_wsiM_reqFifo_deq
assign WILL_FIRE_RL_wsiM_reqFifo_deq =
wsiM_reqFifo_cntr_r != 2'd0 && !wsiM_sThreadBusy_d ;
// rule RL_wsipass_doMessagePush
assign WILL_FIRE_RL_wsipass_doMessagePush =
wsiS_reqFifo_EMPTY_N &&
(smaCtrl[4] || wsiM_reqFifo_cntr_r != 2'd2) &&
wci_wslv_cState == 3'd2 &&
smaCtrl[3:0] == 4'h0 ;
// rule RL_wci_cfrd
assign WILL_FIRE_RL_wci_cfrd =
wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF_EMPTY_N &&
wci_wslv_wci_cfrd_pw_whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wmwt_mesgBegin
assign CAN_FIRE_RL_wmwt_mesgBegin =
wsiS_reqFifo_EMPTY_N && mesgTokenF_FULL_N &&
wci_wslv_cState == 3'd2 &&
(smaCtrl[3:0] == 4'h2 || smaCtrl[3:0] == 4'h3) &&
!wmi_sThreadBusy_d &&
!wmi_sDataThreadBusy_d &&
!opcode[8] ;
assign WILL_FIRE_RL_wmwt_mesgBegin =
CAN_FIRE_RL_wmwt_mesgBegin &&
!MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
// rule RL_wmwt_messagePush
assign CAN_FIRE_RL_wmwt_messagePush =
wmi_reqF_cntr_r != 2'd2 && wmi_dhF_cntr_r != 2'd2 &&
wmi_operateD &&
wmi_peerIsReady &&
wsiS_reqFifo_i_notEmpty__61_AND_NOT_smaCtrl_62_ETC___d667 &&
wci_wslv_cState == 3'd2 &&
(smaCtrl[3:0] == 4'h2 || smaCtrl[3:0] == 4'h3) &&
readyToPush ;
// rule RL_wmwt_doAbort
assign WILL_FIRE_RL_wmwt_doAbort =
wci_wslv_cState == 3'd2 &&
(smaCtrl[3:0] == 4'h2 || smaCtrl[3:0] == 4'h3) &&
doAbort ;
// rule RL_wmwt_messageFinalize
assign WILL_FIRE_RL_wmwt_messageFinalize =
mesgTokenF_EMPTY_N && wci_wslv_cState == 3'd2 &&
(smaCtrl[3:0] == 4'h2 || smaCtrl[3:0] == 4'h3) &&
!doAbort &&
endOfMessage ;
// rule RL_wmi_reqF_incCtr
assign WILL_FIRE_RL_wmi_reqF_incCtr =
wmi_reqF_x_wire_whas && wmi_reqF_enqueueing_whas &&
!wmi_reqF_dequeueing_whas ;
// rule RL_wmi_reqF_decCtr
assign WILL_FIRE_RL_wmi_reqF_decCtr =
wmi_reqF_dequeueing_whas && !wmi_reqF_enqueueing_whas ;
// rule RL_wmi_reqF_both
assign WILL_FIRE_RL_wmi_reqF_both =
wmi_reqF_x_wire_whas && wmi_reqF_dequeueing_whas &&
wmi_reqF_enqueueing_whas ;
// rule RL_wmi_mFlagF_incCtr
assign WILL_FIRE_RL_wmi_mFlagF_incCtr =
wmi_mFlagF_enqueueing_whas && wmi_mFlagF_enqueueing_whas &&
!wmi_mFlagF_dequeueing_whas ;
// rule RL_wmi_mFlagF_decCtr
assign WILL_FIRE_RL_wmi_mFlagF_decCtr =
wmi_mFlagF_dequeueing_whas && !wmi_mFlagF_enqueueing_whas ;
// rule RL_wmi_mFlagF_both
assign WILL_FIRE_RL_wmi_mFlagF_both =
wmi_mFlagF_enqueueing_whas && wmi_mFlagF_dequeueing_whas &&
wmi_mFlagF_enqueueing_whas ;
// rule RL_wmi_dhF_incCtr
assign WILL_FIRE_RL_wmi_dhF_incCtr =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
!wmi_dhF_dequeueing_whas ;
// rule RL_wmi_dhF_decCtr
assign WILL_FIRE_RL_wmi_dhF_decCtr =
wmi_dhF_dequeueing_whas &&
!MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
// rule RL_wmi_dhF_both
assign WILL_FIRE_RL_wmi_dhF_both =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
wmi_dhF_dequeueing_whas &&
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
// rule RL_wmrd_mesgResptoWsi
assign WILL_FIRE_RL_wmrd_mesgResptoWsi =
wsiM_reqFifo_cntr_r != 2'd2 && respF_rRdPtr != respF_rWrPtr &&
wci_wslv_cState == 3'd2 &&
(smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 ||
smaCtrl[3:0] == 4'h9) ;
// rule RL_wci_cfwr
assign WILL_FIRE_RL_wci_cfwr =
wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_reqF_EMPTY_N &&
wci_wslv_wci_cfwr_pw_whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wsiM_reqFifo_incCtr
assign WILL_FIRE_RL_wsiM_reqFifo_incCtr =
wsiM_reqFifo_enqueueing_whas && wsiM_reqFifo_enqueueing_whas &&
!WILL_FIRE_RL_wsiM_reqFifo_deq ;
// rule RL_wsiM_reqFifo_decCtr
assign WILL_FIRE_RL_wsiM_reqFifo_decCtr =
WILL_FIRE_RL_wsiM_reqFifo_deq && !wsiM_reqFifo_enqueueing_whas ;
// rule RL_wsiM_reqFifo_both
assign WILL_FIRE_RL_wsiM_reqFifo_both =
wsiM_reqFifo_enqueueing_whas && WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_enqueueing_whas ;
// rule RL_wci_ctrl_IsO
assign WILL_FIRE_RL_wci_ctrl_IsO =
wci_wslv_wci_ctrl_pw_whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd1 &&
wci_wslv_reqF_D_OUT[36:34] == 3'd1 ;
// rule RL_wci_wslv_ctl_op_complete
assign WILL_FIRE_RL_wci_wslv_ctl_op_complete =
wci_wslv_respF_cntr_r != 2'd2 && wci_wslv_ctlOpActive &&
wci_wslv_ctlAckReg ;
// rule RL_wci_wslv_respF_incCtr
assign WILL_FIRE_RL_wci_wslv_respF_incCtr =
wci_wslv_respF_x_wire_whas && wci_wslv_respF_enqueueing_whas &&
!(wci_wslv_respF_cntr_r != 2'd0) ;
// rule RL_wci_wslv_respF_decCtr
assign WILL_FIRE_RL_wci_wslv_respF_decCtr =
wci_wslv_respF_cntr_r != 2'd0 &&
!wci_wslv_respF_enqueueing_whas ;
// rule RL_wci_wslv_respF_both
assign WILL_FIRE_RL_wci_wslv_respF_both =
wci_wslv_respF_x_wire_whas && wci_wslv_respF_cntr_r != 2'd0 &&
wci_wslv_respF_enqueueing_whas ;
// rule RL_wsiS_reqFifo_enq
assign WILL_FIRE_RL_wsiS_reqFifo_enq =
wsiS_reqFifo_FULL_N && wsiS_operateD && wsiS_peerIsReady &&
wsiS_wsiReq_wget[168:166] == 3'd1 ;
// rule RL_wsiS_reqFifo_reset
assign WILL_FIRE_RL_wsiS_reqFifo_reset =
WILL_FIRE_RL_wsiS_reqFifo_enq || wsiS_reqFifo_r_deq_whas ;
// inputs to muxes for submodule ports
assign MUX_endOfMessage_write_1__SEL_1 =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
wsiS_reqFifo_D_OUT[165] ;
assign MUX_mesgCount_write_1__SEL_1 =
MUX_unrollCnt_write_1__SEL_2 && unrollCnt == 16'd1 ;
assign MUX_mesgReqOK_write_1__SEL_3 =
CAN_FIRE_RL_wmrd_mesgBodyPreRequest &&
!WILL_FIRE_RL_wmrd_mesgBodyRequest ;
assign MUX_unrollCnt_write_1__SEL_1 =
wci_wslv_cState == 3'd2 &&
(smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 ||
smaCtrl[3:0] == 4'h9) &&
!wmi_sThreadBusy_d &&
!wmi_sDataThreadBusy_d &&
unrollCnt == 16'd0 ;
assign MUX_unrollCnt_write_1__SEL_2 =
wmi_respF_i_notEmpty__34_AND_smaCtrl_62_BIT_4__ETC___d539 &&
wci_wslv_cState == 3'd2 &&
(smaCtrl[3:0] == 4'h1 || smaCtrl[3:0] == 4'h4 ||
smaCtrl[3:0] == 4'h9) &&
unrollCnt != 16'd0 ;
assign MUX_wci_wslv_illegalEdge_write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF_D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 &&
wci_wslv_cState != 3'd3 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd2 && wci_wslv_cState != 3'd2 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd3 && wci_wslv_cState != 3'd3 &&
wci_wslv_cState != 3'd2 &&
wci_wslv_cState != 3'd1 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd4 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd5 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd6 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd7) ;
assign MUX_wci_wslv_respF_q_0_write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ;
assign MUX_wci_wslv_respF_q_0_write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd0 ;
assign MUX_wci_wslv_respF_q_1_write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ;
assign MUX_wci_wslv_respF_q_1_write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd1 ;
assign MUX_wmi_dhF_q_0_write_1__SEL_1 =
WILL_FIRE_RL_wmi_dhF_both && _dfoo15 ;
assign MUX_wmi_dhF_q_0_write_1__SEL_2 =
WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd0 ;
assign MUX_wmi_dhF_q_1_write_1__SEL_1 =
WILL_FIRE_RL_wmi_dhF_both && _dfoo13 ;
assign MUX_wmi_dhF_q_1_write_1__SEL_2 =
WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd1 ;
assign MUX_wmi_mFlagF_q_0_write_1__SEL_1 =
WILL_FIRE_RL_wmi_mFlagF_both && _dfoo11 ;
assign MUX_wmi_mFlagF_q_0_write_1__SEL_2 =
WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_cntr_r == 2'd0 ;
assign MUX_wmi_mFlagF_q_1_write_1__SEL_1 =
WILL_FIRE_RL_wmi_mFlagF_both && _dfoo9 ;
assign MUX_wmi_mFlagF_q_1_write_1__SEL_2 =
WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_cntr_r == 2'd1 ;
assign MUX_wmi_mFlagF_x_wire_wset_1__SEL_1 =
WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18328 ;
assign MUX_wmi_reqF_q_0_write_1__SEL_1 =
WILL_FIRE_RL_wmi_reqF_both && _dfoo7 ;
assign MUX_wmi_reqF_q_0_write_1__SEL_2 =
WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_cntr_r == 2'd0 ;
assign MUX_wmi_reqF_q_1_write_1__SEL_1 =
WILL_FIRE_RL_wmi_reqF_both && _dfoo5 ;
assign MUX_wmi_reqF_q_1_write_1__SEL_2 =
WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_cntr_r == 2'd1 ;
assign MUX_wsiM_reqFifo_q_0_write_1__SEL_1 =
WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo19 ;
assign MUX_wsiM_reqFifo_q_0_write_1__SEL_2 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd0 ;
assign MUX_wsiM_reqFifo_q_1_write_1__SEL_1 =
WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo17 ;
assign MUX_wsiM_reqFifo_q_1_write_1__SEL_2 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_cntr_r == 2'd1 ;
assign MUX_wsiM_reqFifo_x_wire_wset_1__SEL_1 =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
smaCtrl[3:0] == 4'h3 ;
assign MUX_wsiM_reqFifo_x_wire_wset_1__SEL_2 =
WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] ;
assign MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 =
CAN_FIRE_RL_wmwt_messagePush &&
!WILL_FIRE_RL_wmwt_messageFinalize ;
assign MUX_fabRespCredit_value_write_1__VAL_2 =
fabRespCredit_value +
(WILL_FIRE_RL_wmrd_mesgBodyRequest ? b__h14802 : 12'd0) +
(WILL_FIRE_RL_wmrd_mesgResptoWsi ? 12'd1 : 12'd0) ;
assign MUX_fabWordsRemain_write_1__VAL_1 =
(wmi_sFlagReg[23:0] == 24'd0) ? 14'd1 : b__h17784[13:0] ;
assign MUX_fabWordsRemain_write_1__VAL_2 = fabWordsRemain - fabWordsCurReq ;
assign MUX_mesgCount_write_1__VAL_2 = mesgCount + 32'd1 ;
assign MUX_mesgReqAddr_write_1__VAL_2 =
mesgReqAddr + { fabWordsCurReq[9:0], 4'd0 } ;
assign MUX_opcode_write_1__VAL_3 = { 1'd1, wsiS_reqFifo_D_OUT[7:0] } ;
assign MUX_thisMesg_write_1__VAL_1 =
{ mesgCount[7:0], mesgMetaF_opcode__h23069, x_length__h23961 } ;
assign MUX_thisMesg_write_1__VAL_2 =
{ mesgCount[7:0], wmi_sFlagReg[31:24], wmi_sFlagReg[15:0] } ;
assign MUX_unrollCnt_write_1__VAL_1 =
(wmi_sFlagReg[23:0] == 24'd0) ? 16'd1 : b__h17784[15:0] ;
assign MUX_unrollCnt_write_1__VAL_2 = unrollCnt - 16'd1 ;
assign MUX_wci_wslv_illegalEdge_write_1__VAL_1 =
wci_wslv_reqF_D_OUT[36:34] != 3'd4 &&
wci_wslv_reqF_D_OUT[36:34] != 3'd5 &&
wci_wslv_reqF_D_OUT[36:34] != 3'd6 ;
assign MUX_wci_wslv_respF_cntr_r_write_1__VAL_2 =
wci_wslv_respF_cntr_r + 2'd1 ;
assign MUX_wci_wslv_respF_q_0_write_1__VAL_1 =
(wci_wslv_respF_cntr_r == 2'd1) ?
MUX_wci_wslv_respF_q_0_write_1__VAL_2 :
wci_wslv_respF_q_1 ;
always@(WILL_FIRE_RL_wci_wslv_ctl_op_complete or
MUX_wci_wslv_respF_x_wire_wset_1__VAL_1 or
WILL_FIRE_RL_wci_cfrd or
MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 or WILL_FIRE_RL_wci_cfwr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_wslv_ctl_op_complete:
MUX_wci_wslv_respF_q_0_write_1__VAL_2 =
MUX_wci_wslv_respF_x_wire_wset_1__VAL_1;
WILL_FIRE_RL_wci_cfrd:
MUX_wci_wslv_respF_q_0_write_1__VAL_2 =
MUX_wci_wslv_respF_x_wire_wset_1__VAL_2;
WILL_FIRE_RL_wci_cfwr:
MUX_wci_wslv_respF_q_0_write_1__VAL_2 = 34'h1C0DE4201;
default: MUX_wci_wslv_respF_q_0_write_1__VAL_2 =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign MUX_wci_wslv_respF_q_1_write_1__VAL_1 =
(wci_wslv_respF_cntr_r == 2'd2) ?
MUX_wci_wslv_respF_q_0_write_1__VAL_2 :
34'h0AAAAAAAA ;
assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_1 =
wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ;
assign MUX_wci_wslv_respF_x_wire_wset_1__VAL_2 = { 2'd1, g_data__h24937 } ;
assign MUX_wmi_dhF_cntr_r_write_1__VAL_2 = wmi_dhF_cntr_r + 2'd1 ;
assign MUX_wmi_dhF_q_0_write_1__VAL_1 =
(wmi_dhF_cntr_r == 2'd1) ?
MUX_wmi_dhF_q_0_write_1__VAL_2 :
wmi_dhF_q_1 ;
assign MUX_wmi_dhF_q_0_write_1__VAL_2 =
{ 1'd1, wsiS_reqFifo_D_OUT[165], wsiS_reqFifo_D_OUT[151:8] } ;
assign MUX_wmi_dhF_q_1_write_1__VAL_1 =
(wmi_dhF_cntr_r == 2'd2) ?
MUX_wmi_dhF_q_0_write_1__VAL_2 :
146'd0 ;
assign MUX_wmi_mFlagF_cntr_r_write_1__VAL_2 = wmi_mFlagF_cntr_r + 2'd1 ;
assign MUX_wmi_mFlagF_q_0_write_1__VAL_1 =
(wmi_mFlagF_cntr_r == 2'd1) ? value__h6387 : wmi_mFlagF_q_1 ;
assign MUX_wmi_mFlagF_q_1_write_1__VAL_1 =
(wmi_mFlagF_cntr_r == 2'd2) ? value__h6387 : 32'd0 ;
assign MUX_wmi_mFlagF_x_wire_wset_1__VAL_2 =
{ mesgMetaF_opcode__h23069, mesgMetaF_length__h23070 } ;
assign MUX_wmi_reqF_cntr_r_write_1__VAL_2 = wmi_reqF_cntr_r + 2'd1 ;
assign MUX_wmi_reqF_q_0_write_1__VAL_1 =
(wmi_reqF_cntr_r == 2'd1) ?
MUX_wmi_reqF_q_0_write_1__VAL_2 :
wmi_reqF_q_1 ;
assign MUX_wmi_reqF_q_0_write_1__VAL_2 =
WILL_FIRE_RL_wmrd_mesgBodyRequest ?
MUX_wmi_reqF_x_wire_wset_1__VAL_1 :
MUX_wmi_reqF_x_wire_wset_1__VAL_2 ;
assign MUX_wmi_reqF_q_1_write_1__VAL_1 =
(wmi_reqF_cntr_r == 2'd2) ?
MUX_wmi_reqF_q_0_write_1__VAL_2 :
32'd0 ;
assign MUX_wmi_reqF_x_wire_wset_1__VAL_1 =
{ 4'd5, x__h18328, 1'b0, mesgReqAddr, fabWordsCurReq[11:0] } ;
assign MUX_wmi_reqF_x_wire_wset_1__VAL_2 =
{ 4'd3, wsiS_reqFifo_D_OUT[165], 1'b0, mesgLengthSoFar, 12'd1 } ;
assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 = wsiM_reqFifo_cntr_r - 2'd1 ;
assign MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 = wsiM_reqFifo_cntr_r + 2'd1 ;
assign MUX_wsiM_reqFifo_q_0_write_1__VAL_1 =
(wsiM_reqFifo_cntr_r == 2'd1) ?
MUX_wsiM_reqFifo_q_0_write_1__VAL_2 :
wsiM_reqFifo_q_1 ;
assign MUX_wsiM_reqFifo_q_0_write_1__VAL_2 =
(MUX_wsiM_reqFifo_x_wire_wset_1__SEL_1 ||
MUX_wsiM_reqFifo_x_wire_wset_1__SEL_2) ?
wsiS_reqFifo_D_OUT :
MUX_wsiM_reqFifo_x_wire_wset_1__VAL_3 ;
assign MUX_wsiM_reqFifo_q_1_write_1__VAL_1 =
(wsiM_reqFifo_cntr_r == 2'd2) ?
MUX_wsiM_reqFifo_q_0_write_1__VAL_2 :
169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00 ;
assign MUX_wsiM_reqFifo_x_wire_wset_1__VAL_3 =
(respF_rCache[181] && respF_rCache[180:169] == respF_rRdPtr) ?
respF_rCache[168:0] :
respF_memory_DOB ;
// inlined wires
assign wci_wslv_wciReq_wget =
{ wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData } ;
assign wci_wslv_wciReq_whas = 1'd1 ;
assign wci_wslv_respF_x_wire_wget = MUX_wci_wslv_respF_q_0_write_1__VAL_2 ;
assign wci_wslv_respF_x_wire_whas =
WILL_FIRE_RL_wci_wslv_ctl_op_complete || WILL_FIRE_RL_wci_cfrd ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_wslv_wEdge_wget = wci_wslv_reqF_D_OUT[36:34] ;
assign wci_wslv_wEdge_whas = WILL_FIRE_RL_wci_wslv_ctl_op_start ;
assign wci_wslv_sFlagReg_1_wget = 1'b0 ;
assign wci_wslv_sFlagReg_1_whas = 1'b0 ;
assign wci_wslv_ctlAckReg_1_wget = 1'd1 ;
assign wci_wslv_ctlAckReg_1_whas =
WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO ||
WILL_FIRE_RL_wci_ctrl_EiI ;
assign wci_wci_Es_mCmd_w_wget = wciS0_MCmd ;
assign wci_wci_Es_mCmd_w_whas = 1'd1 ;
assign wci_wci_Es_mAddrSpace_w_wget = wciS0_MAddrSpace ;
assign wci_wci_Es_mAddrSpace_w_whas = 1'd1 ;
assign wci_wci_Es_mByteEn_w_wget = wciS0_MByteEn ;
assign wci_wci_Es_mByteEn_w_whas = 1'd1 ;
assign wci_wci_Es_mAddr_w_wget = wciS0_MAddr ;
assign wci_wci_Es_mAddr_w_whas = 1'd1 ;
assign wci_wci_Es_mData_w_wget = wciS0_MData ;
assign wci_wci_Es_mData_w_whas = 1'd1 ;
assign wmi_reqF_x_wire_wget = MUX_wmi_reqF_q_0_write_1__VAL_2 ;
assign wmi_reqF_x_wire_whas =
WILL_FIRE_RL_wmrd_mesgBodyRequest ||
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wmi_mFlagF_x_wire_wget = value__h6387 ;
assign wmi_mFlagF_x_wire_whas = wmi_mFlagF_enqueueing_whas ;
assign wmi_dhF_x_wire_wget = MUX_wmi_dhF_q_0_write_1__VAL_2 ;
assign wmi_dhF_x_wire_whas = MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wmi_wmiResponse_wget = { wmiM0_SResp, wmiM0_SData } ;
assign wmi_wmiResponse_whas = 1'd1 ;
assign wmi_sThreadBusy_d_1_wget = 1'd1 ;
assign wmi_sThreadBusy_d_1_whas = wmiM0_SThreadBusy ;
assign wmi_sDataThreadBusy_d_1_wget = 1'd1 ;
assign wmi_sDataThreadBusy_d_1_whas = wmiM0_SDataThreadBusy ;
assign wmi_operateD_1_wget = 1'd1 ;
assign wmi_operateD_1_whas = wci_wslv_cState == 3'd2 ;
assign wmi_peerIsReady_1_wget = 1'd1 ;
assign wmi_peerIsReady_1_whas = wmiM0_SReset_n ;
assign wsiM_reqFifo_x_wire_wget = MUX_wsiM_reqFifo_q_0_write_1__VAL_2 ;
assign wsiM_reqFifo_x_wire_whas = wsiM_reqFifo_enqueueing_whas ;
assign wsiM_operateD_1_wget = 1'd1 ;
assign wsiM_operateD_1_whas = wci_wslv_cState == 3'd2 ;
assign wsiM_peerIsReady_1_wget = 1'd1 ;
assign wsiM_peerIsReady_1_whas = wsiM0_SReset_n ;
assign wsiS_wsiReq_wget =
{ wsiS0_MCmd,
wsiS0_MReqLast,
wsiS0_MBurstPrecise,
wsiS0_MBurstLength,
wsiS0_MData,
wsiS0_MByteEn,
wsiS0_MReqInfo } ;
assign wsiS_wsiReq_whas = 1'd1 ;
assign wsiS_operateD_1_wget = 1'd1 ;
assign wsiS_operateD_1_whas = wci_wslv_cState == 3'd2 ;
assign wsiS_peerIsReady_1_wget = 1'd1 ;
assign wsiS_peerIsReady_1_whas = wsiS0_MReset_n ;
assign wsiS_sThreadBusy_dw_wget = wsiS_reqFifo_countReg > 2'd1 ;
assign wsiS_sThreadBusy_dw_whas =
wsiS_reqFifo_levelsValid && wsiS_operateD && wsiS_peerIsReady ;
assign fabRespCredit_acc_v1_wget = b__h14802 ;
assign fabRespCredit_acc_v1_whas = WILL_FIRE_RL_wmrd_mesgBodyRequest ;
assign fabRespCredit_acc_v2_wget = 12'd1 ;
assign fabRespCredit_acc_v2_whas = WILL_FIRE_RL_wmrd_mesgResptoWsi ;
assign mesgPreRequest_1_wget = 1'd1 ;
assign mesgPreRequest_1_whas = MUX_mesgReqOK_write_1__SEL_3 ;
assign respF_wDataIn_wget =
{ 3'd1,
unrollCnt == 16'd1,
!smaCtrl[5],
sendData_burstLength__h18617,
wmi_respF_D_OUT[127:0],
sendData_byteEn__h18619,
thisMesg[23:16] } ;
assign respF_wDataIn_whas = respF_pwEnqueue_whas ;
assign respF_wDataOut_wget = MUX_wsiM_reqFifo_x_wire_wset_1__VAL_3 ;
assign respF_wDataOut_whas = 1'd1 ;
assign wsi_Es_mCmd_w_wget = wsiS0_MCmd ;
assign wsi_Es_mCmd_w_whas = 1'd1 ;
assign wsi_Es_mBurstLength_w_wget = wsiS0_MBurstLength ;
assign wsi_Es_mBurstLength_w_whas = 1'd1 ;
assign wsi_Es_mData_w_wget = wsiS0_MData ;
assign wsi_Es_mData_w_whas = 1'd1 ;
assign wsi_Es_mByteEn_w_wget = wsiS0_MByteEn ;
assign wsi_Es_mByteEn_w_whas = 1'd1 ;
assign wsi_Es_mReqInfo_w_wget = wsiS0_MReqInfo ;
assign wsi_Es_mReqInfo_w_whas = 1'd1 ;
assign wmi_Em_sResp_w_wget = wmiM0_SResp ;
assign wmi_Em_sResp_w_whas = 1'd1 ;
assign wmi_Em_sData_w_wget = wmiM0_SData ;
assign wmi_Em_sData_w_whas = 1'd1 ;
assign wci_wslv_reqF_r_enq_whas = wci_wslv_wciReq_wget[71:69] != 3'd0 ;
assign wci_wslv_reqF_r_deq_whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_wslv_ctl_op_start ;
assign wci_wslv_reqF_r_clr_whas = 1'b0 ;
assign wci_wslv_respF_enqueueing_whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign wci_wslv_respF_dequeueing_whas = wci_wslv_respF_cntr_r != 2'd0 ;
assign wci_wslv_sThreadBusy_pw_whas = 1'b0 ;
assign wci_wslv_wci_cfwr_pw_whas =
wci_wslv_reqF_EMPTY_N && wci_wslv_reqF_D_OUT[68] &&
wci_wslv_reqF_D_OUT[71:69] == 3'd1 ;
assign wci_wslv_wci_cfrd_pw_whas =
wci_wslv_reqF_EMPTY_N && wci_wslv_reqF_D_OUT[68] &&
wci_wslv_reqF_D_OUT[71:69] == 3'd2 ;
assign wci_wslv_wci_ctrl_pw_whas =
wci_wslv_reqF_EMPTY_N && !wci_wslv_reqF_D_OUT[68] &&
wci_wslv_reqF_D_OUT[71:69] == 3'd2 ;
assign wmi_reqF_enqueueing_whas =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ||
WILL_FIRE_RL_wmrd_mesgBodyRequest ;
assign wmi_reqF_dequeueing_whas =
WILL_FIRE_RL_wmi_reqF_deq && wmi_reqF_cntr_r != 2'd0 ;
assign wmi_mFlagF_enqueueing_whas =
WILL_FIRE_RL_wmrd_mesgBodyRequest && x__h18328 ||
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
wsiS_reqFifo_D_OUT[165] ;
assign wmi_mFlagF_dequeueing_whas =
WILL_FIRE_RL_wmi_reqF_deq && wmi_reqF_q_0[27] &&
wmi_mFlagF_cntr_r != 2'd0 ;
assign wmi_dhF_enqueueing_whas =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wmi_dhF_dequeueing_whas =
wmi_operateD && wmi_peerIsReady && !wmi_sDataThreadBusy_d &&
wmi_dhF_cntr_r != 2'd0 ;
assign wsiM_reqFifo_enqueueing_whas =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
smaCtrl[3:0] == 4'h3 ||
WILL_FIRE_RL_wsipass_doMessagePush && !smaCtrl[4] ||
WILL_FIRE_RL_wmrd_mesgResptoWsi ;
assign wsiM_reqFifo_dequeueing_whas = WILL_FIRE_RL_wsiM_reqFifo_deq ;
assign wsiM_sThreadBusy_pw_whas = wsiM0_SThreadBusy ;
assign wsiS_reqFifo_r_enq_whas = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_r_deq_whas =
WILL_FIRE_RL_wsipass_doMessagePush ||
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
assign wsiS_reqFifo_r_clr_whas = 1'b0 ;
assign wsiS_reqFifo_doResetEnq_whas = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_doResetDeq_whas = wsiS_reqFifo_r_deq_whas ;
assign wsiS_reqFifo_doResetClr_whas = 1'b0 ;
assign respF_pwDequeue_whas = WILL_FIRE_RL_wmrd_mesgResptoWsi ;
assign respF_pwEnqueue_whas = MUX_unrollCnt_write_1__SEL_2 && !smaCtrl[4] ;
assign respF_pwClear_whas = 1'b0 ;
assign wsi_Es_mReqLast_w_whas = wsiS0_MReqLast ;
assign wsi_Es_mBurstPrecise_w_whas = wsiS0_MBurstPrecise ;
assign wsi_Es_mDataInfo_w_whas = 1'd1 ;
assign wsiM_extStatusW_wget =
{ wsiM_pMesgCount, wsiM_iMesgCount, wsiM_tBusyCount } ;
assign wsiS_extStatusW_wget =
{ wsiS_pMesgCount, wsiS_iMesgCount, wsiS_tBusyCount } ;
// register abortCount
assign abortCount_D_IN = abortCount + 32'd1 ;
assign abortCount_EN = WILL_FIRE_RL_wmwt_doAbort ;
// register doAbort
assign doAbort_D_IN = 1'd0 ;
assign doAbort_EN = WILL_FIRE_RL_wmwt_doAbort ;
// register endOfMessage
assign endOfMessage_D_IN = MUX_endOfMessage_write_1__SEL_1 ;
assign endOfMessage_EN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
wsiS_reqFifo_D_OUT[165] ||
WILL_FIRE_RL_wmwt_messageFinalize ;
// register errCount
assign errCount_D_IN = errCount + 128'd1 ;
assign errCount_EN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
wsiS_reqFifo_D_OUT[151:24] != valExpect &&
(!wsiS_reqFifo_D_OUT[165] || wsiS_reqFifo_D_OUT[23:8] != 16'd0 ||
mesgLengthSoFar != 14'd0) ;
// register fabRespCredit_value
assign fabRespCredit_value_D_IN =
WILL_FIRE_RL_wci_ctrl_IsO ?
12'd1024 :
MUX_fabRespCredit_value_write_1__VAL_2 ;
assign fabRespCredit_value_EN = 1'b1 ;
// register fabWordsCurReq
assign fabWordsCurReq_D_IN =
(fabWordsRemain <= b__h18157) ? fabWordsRemain : b__h18157 ;
assign fabWordsCurReq_EN = MUX_mesgReqOK_write_1__SEL_3 ;
// register fabWordsRemain
assign fabWordsRemain_D_IN =
MUX_unrollCnt_write_1__SEL_1 ?
MUX_fabWordsRemain_write_1__VAL_1 :
MUX_fabWordsRemain_write_1__VAL_2 ;
assign fabWordsRemain_EN =
MUX_unrollCnt_write_1__SEL_1 ||
WILL_FIRE_RL_wmrd_mesgBodyRequest ;
// register firstMsgReq
assign firstMsgReq_D_IN = 1'b0 ;
assign firstMsgReq_EN = 1'b0 ;
// register lastMesg
assign lastMesg_D_IN =
(MUX_endOfMessage_write_1__SEL_1 ||
MUX_unrollCnt_write_1__SEL_1) ?
thisMesg :
32'hFEFEFFFE ;
assign lastMesg_EN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
wsiS_reqFifo_D_OUT[165] ||
MUX_unrollCnt_write_1__SEL_1 ||
WILL_FIRE_RL_wci_ctrl_IsO ;
// register mesgCount
always@(MUX_mesgCount_write_1__SEL_1 or
MUX_mesgCount_write_1__VAL_2 or
WILL_FIRE_RL_wmwt_messageFinalize or WILL_FIRE_RL_wci_ctrl_IsO)
begin
case (1'b1) // synopsys parallel_case
MUX_mesgCount_write_1__SEL_1:
mesgCount_D_IN = MUX_mesgCount_write_1__VAL_2;
WILL_FIRE_RL_wmwt_messageFinalize:
mesgCount_D_IN = MUX_mesgCount_write_1__VAL_2;
WILL_FIRE_RL_wci_ctrl_IsO: mesgCount_D_IN = 32'd0;
default: mesgCount_D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign mesgCount_EN =
MUX_unrollCnt_write_1__SEL_2 && unrollCnt == 16'd1 ||
WILL_FIRE_RL_wmwt_messageFinalize ||
WILL_FIRE_RL_wci_ctrl_IsO ;
// register mesgLengthSoFar
assign mesgLengthSoFar_D_IN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ?
mlB__h22903 :
14'd0 ;
assign mesgLengthSoFar_EN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ||
WILL_FIRE_RL_wmwt_mesgBegin ;
// register mesgPreRequest
assign mesgPreRequest_D_IN = MUX_mesgReqOK_write_1__SEL_3 ;
assign mesgPreRequest_EN = 1'd1 ;
// register mesgReqAddr
assign mesgReqAddr_D_IN =
MUX_unrollCnt_write_1__SEL_1 ?
14'd0 :
MUX_mesgReqAddr_write_1__VAL_2 ;
assign mesgReqAddr_EN =
WILL_FIRE_RL_wmrd_mesgBodyRequest ||
MUX_unrollCnt_write_1__SEL_1 ;
// register mesgReqOK
assign mesgReqOK_D_IN =
MUX_unrollCnt_write_1__SEL_2 || MUX_unrollCnt_write_1__SEL_1 ;
assign mesgReqOK_EN =
CAN_FIRE_RL_wmrd_mesgBodyPreRequest &&
!WILL_FIRE_RL_wmrd_mesgBodyRequest ||
MUX_unrollCnt_write_1__SEL_1 ||
MUX_unrollCnt_write_1__SEL_2 ;
// register opcode
assign opcode_D_IN =
(WILL_FIRE_RL_wmwt_messageFinalize ||
WILL_FIRE_RL_wmwt_doAbort) ?
9'd170 :
MUX_opcode_write_1__VAL_3 ;
assign opcode_EN =
WILL_FIRE_RL_wmwt_messageFinalize || WILL_FIRE_RL_wmwt_doAbort ||
WILL_FIRE_RL_wmwt_mesgBegin ;
// register readyToPush
assign readyToPush_D_IN =
!WILL_FIRE_RL_wmwt_doAbort && !MUX_endOfMessage_write_1__SEL_1 ;
assign readyToPush_EN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
wsiS_reqFifo_D_OUT[165] ||
WILL_FIRE_RL_wmwt_doAbort ||
WILL_FIRE_RL_wmwt_mesgBegin ;
// register readyToRequest
assign readyToRequest_D_IN = 1'b0 ;
assign readyToRequest_EN = 1'b0 ;
// register respF_rCache
assign respF_rCache_D_IN =
{ 1'd1,
respF_rWrPtr,
IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d431,
respF_pwEnqueue_whas && respF_wDataIn_wget[165],
respF_pwEnqueue_whas && respF_wDataIn_wget[164],
IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d437 } ;
assign respF_rCache_EN = respF_pwEnqueue_whas ;
// register respF_rRdPtr
assign respF_rRdPtr_D_IN = x__h16253 ;
assign respF_rRdPtr_EN = WILL_FIRE_RL_wmrd_mesgResptoWsi ;
// register respF_rWrPtr
assign respF_rWrPtr_D_IN = x__h16103 ;
assign respF_rWrPtr_EN = respF_pwEnqueue_whas ;
// register smaCtrl
assign smaCtrl_D_IN = wci_wslv_reqF_D_OUT[31:0] ;
assign smaCtrl_EN =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF_D_OUT[39:32] == 8'h0 ;
// register thisMesg
always@(MUX_endOfMessage_write_1__SEL_1 or
MUX_thisMesg_write_1__VAL_1 or
MUX_unrollCnt_write_1__SEL_1 or
MUX_thisMesg_write_1__VAL_2 or WILL_FIRE_RL_wci_ctrl_IsO)
begin
case (1'b1) // synopsys parallel_case
MUX_endOfMessage_write_1__SEL_1:
thisMesg_D_IN = MUX_thisMesg_write_1__VAL_1;
MUX_unrollCnt_write_1__SEL_1:
thisMesg_D_IN = MUX_thisMesg_write_1__VAL_2;
WILL_FIRE_RL_wci_ctrl_IsO: thisMesg_D_IN = 32'hFEFEFFFE;
default: thisMesg_D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign thisMesg_EN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
wsiS_reqFifo_D_OUT[165] ||
MUX_unrollCnt_write_1__SEL_1 ||
WILL_FIRE_RL_wci_ctrl_IsO ;
// register unrollCnt
assign unrollCnt_D_IN =
MUX_unrollCnt_write_1__SEL_1 ?
MUX_unrollCnt_write_1__VAL_1 :
MUX_unrollCnt_write_1__VAL_2 ;
assign unrollCnt_EN =
MUX_unrollCnt_write_1__SEL_1 || MUX_unrollCnt_write_1__SEL_2 ;
// register valExpect
assign valExpect_D_IN = valExpect + 128'd1 ;
assign valExpect_EN =
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 &&
(!wsiS_reqFifo_D_OUT[165] || wsiS_reqFifo_D_OUT[23:8] != 16'd0 ||
mesgLengthSoFar != 14'd0) ;
// register wci_wslv_cEdge
assign wci_wslv_cEdge_D_IN = wci_wslv_reqF_D_OUT[36:34] ;
assign wci_wslv_cEdge_EN = WILL_FIRE_RL_wci_wslv_ctl_op_start ;
// register wci_wslv_cState
assign wci_wslv_cState_D_IN = wci_wslv_nState ;
assign wci_wslv_cState_EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge ;
// register wci_wslv_ctlAckReg
assign wci_wslv_ctlAckReg_D_IN = wci_wslv_ctlAckReg_1_whas ;
assign wci_wslv_ctlAckReg_EN = 1'd1 ;
// register wci_wslv_ctlOpActive
assign wci_wslv_ctlOpActive_D_IN = !WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign wci_wslv_ctlOpActive_EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete ||
WILL_FIRE_RL_wci_wslv_ctl_op_start ;
// register wci_wslv_illegalEdge
assign wci_wslv_illegalEdge_D_IN =
MUX_wci_wslv_illegalEdge_write_1__SEL_1 &&
MUX_wci_wslv_illegalEdge_write_1__VAL_1 ;
assign wci_wslv_illegalEdge_EN =
MUX_wci_wslv_illegalEdge_write_1__SEL_1 ||
WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;
// register wci_wslv_isReset_isInReset
assign wci_wslv_isReset_isInReset_D_IN = 1'd0 ;
assign wci_wslv_isReset_isInReset_EN = wci_wslv_isReset_isInReset ;
// register wci_wslv_nState
always@(wci_wslv_reqF_D_OUT)
begin
case (wci_wslv_reqF_D_OUT[36:34])
3'd0: wci_wslv_nState_D_IN = 3'd1;
3'd1: wci_wslv_nState_D_IN = 3'd2;
3'd2: wci_wslv_nState_D_IN = 3'd3;
default: wci_wslv_nState_D_IN = 3'd0;
endcase
end
assign wci_wslv_nState_EN =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF_D_OUT[36:34] == 3'd0 && wci_wslv_cState == 3'd0 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd1 &&
(wci_wslv_cState == 3'd1 || wci_wslv_cState == 3'd3) ||
wci_wslv_reqF_D_OUT[36:34] == 3'd2 && wci_wslv_cState == 3'd2 ||
wci_wslv_reqF_D_OUT[36:34] == 3'd3 &&
(wci_wslv_cState == 3'd3 || wci_wslv_cState == 3'd2 ||
wci_wslv_cState == 3'd1)) ;
// register wci_wslv_reqF_countReg
assign wci_wslv_reqF_countReg_D_IN =
(wci_wslv_wciReq_wget[71:69] != 3'd0) ?
wci_wslv_reqF_countReg + 2'd1 :
wci_wslv_reqF_countReg - 2'd1 ;
assign wci_wslv_reqF_countReg_EN =
(wci_wslv_wciReq_wget[71:69] != 3'd0) !=
wci_wslv_reqF_r_deq_whas ;
// register wci_wslv_respF_cntr_r
assign wci_wslv_respF_cntr_r_D_IN =
WILL_FIRE_RL_wci_wslv_respF_decCtr ?
wci_wslv_respF_cntr_r_8_MINUS_1___d27 :
MUX_wci_wslv_respF_cntr_r_write_1__VAL_2 ;
assign wci_wslv_respF_cntr_r_EN =
WILL_FIRE_RL_wci_wslv_respF_decCtr ||
WILL_FIRE_RL_wci_wslv_respF_incCtr ;
// register wci_wslv_respF_q_0
always@(MUX_wci_wslv_respF_q_0_write_1__SEL_1 or
MUX_wci_wslv_respF_q_0_write_1__VAL_1 or
MUX_wci_wslv_respF_q_0_write_1__SEL_2 or
MUX_wci_wslv_respF_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_wslv_respF_q_0_write_1__SEL_1:
wci_wslv_respF_q_0_D_IN = MUX_wci_wslv_respF_q_0_write_1__VAL_1;
MUX_wci_wslv_respF_q_0_write_1__SEL_2:
wci_wslv_respF_q_0_D_IN = MUX_wci_wslv_respF_q_0_write_1__VAL_2;
WILL_FIRE_RL_wci_wslv_respF_decCtr:
wci_wslv_respF_q_0_D_IN = wci_wslv_respF_q_1;
default: wci_wslv_respF_q_0_D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_wslv_respF_q_0_EN =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo3 ||
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd0 ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_respF_q_1
always@(MUX_wci_wslv_respF_q_1_write_1__SEL_1 or
MUX_wci_wslv_respF_q_1_write_1__VAL_1 or
MUX_wci_wslv_respF_q_1_write_1__SEL_2 or
MUX_wci_wslv_respF_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wci_wslv_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_wslv_respF_q_1_write_1__SEL_1:
wci_wslv_respF_q_1_D_IN = MUX_wci_wslv_respF_q_1_write_1__VAL_1;
MUX_wci_wslv_respF_q_1_write_1__SEL_2:
wci_wslv_respF_q_1_D_IN = MUX_wci_wslv_respF_q_0_write_1__VAL_2;
WILL_FIRE_RL_wci_wslv_respF_decCtr:
wci_wslv_respF_q_1_D_IN = 34'h0AAAAAAAA;
default: wci_wslv_respF_q_1_D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_wslv_respF_q_1_EN =
WILL_FIRE_RL_wci_wslv_respF_both && _dfoo1 ||
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_cntr_r == 2'd1 ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_sFlagReg
assign wci_wslv_sFlagReg_D_IN = 1'b0 ;
assign wci_wslv_sFlagReg_EN = 1'd1 ;
// register wci_wslv_sThreadBusy_d
assign wci_wslv_sThreadBusy_d_D_IN = 1'b0 ;
assign wci_wslv_sThreadBusy_d_EN = 1'd1 ;
// register wmi_busyWithMessage
assign wmi_busyWithMessage_D_IN = 1'b0 ;
assign wmi_busyWithMessage_EN = 1'b0 ;
// register wmi_dhF_cntr_r
assign wmi_dhF_cntr_r_D_IN =
WILL_FIRE_RL_wmi_dhF_decCtr ?
wmi_dhF_cntr_r_05_MINUS_1___d213 :
MUX_wmi_dhF_cntr_r_write_1__VAL_2 ;
assign wmi_dhF_cntr_r_EN =
WILL_FIRE_RL_wmi_dhF_decCtr || WILL_FIRE_RL_wmi_dhF_incCtr ;
// register wmi_dhF_q_0
always@(MUX_wmi_dhF_q_0_write_1__SEL_1 or
MUX_wmi_dhF_q_0_write_1__VAL_1 or
MUX_wmi_dhF_q_0_write_1__SEL_2 or
MUX_wmi_dhF_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wmi_dhF_decCtr or wmi_dhF_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wmi_dhF_q_0_write_1__SEL_1:
wmi_dhF_q_0_D_IN = MUX_wmi_dhF_q_0_write_1__VAL_1;
MUX_wmi_dhF_q_0_write_1__SEL_2:
wmi_dhF_q_0_D_IN = MUX_wmi_dhF_q_0_write_1__VAL_2;
WILL_FIRE_RL_wmi_dhF_decCtr: wmi_dhF_q_0_D_IN = wmi_dhF_q_1;
default: wmi_dhF_q_0_D_IN =
146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmi_dhF_q_0_EN =
WILL_FIRE_RL_wmi_dhF_both && _dfoo15 ||
WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd0 ||
WILL_FIRE_RL_wmi_dhF_decCtr ;
// register wmi_dhF_q_1
always@(MUX_wmi_dhF_q_1_write_1__SEL_1 or
MUX_wmi_dhF_q_1_write_1__VAL_1 or
MUX_wmi_dhF_q_1_write_1__SEL_2 or
MUX_wmi_dhF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wmi_dhF_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wmi_dhF_q_1_write_1__SEL_1:
wmi_dhF_q_1_D_IN = MUX_wmi_dhF_q_1_write_1__VAL_1;
MUX_wmi_dhF_q_1_write_1__SEL_2:
wmi_dhF_q_1_D_IN = MUX_wmi_dhF_q_0_write_1__VAL_2;
WILL_FIRE_RL_wmi_dhF_decCtr: wmi_dhF_q_1_D_IN = 146'd0;
default: wmi_dhF_q_1_D_IN =
146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmi_dhF_q_1_EN =
WILL_FIRE_RL_wmi_dhF_both && _dfoo13 ||
WILL_FIRE_RL_wmi_dhF_incCtr && wmi_dhF_cntr_r == 2'd1 ||
WILL_FIRE_RL_wmi_dhF_decCtr ;
// register wmi_errorSticky
assign wmi_errorSticky_D_IN = 1'b0 ;
assign wmi_errorSticky_EN = 1'b0 ;
// register wmi_isReset_isInReset
assign wmi_isReset_isInReset_D_IN = 1'd0 ;
assign wmi_isReset_isInReset_EN = wmi_isReset_isInReset ;
// register wmi_mFlagF_cntr_r
assign wmi_mFlagF_cntr_r_D_IN =
WILL_FIRE_RL_wmi_mFlagF_decCtr ?
wmi_mFlagF_cntr_r_83_MINUS_1___d191 :
MUX_wmi_mFlagF_cntr_r_write_1__VAL_2 ;
assign wmi_mFlagF_cntr_r_EN =
WILL_FIRE_RL_wmi_mFlagF_decCtr ||
WILL_FIRE_RL_wmi_mFlagF_incCtr ;
// register wmi_mFlagF_q_0
always@(MUX_wmi_mFlagF_q_0_write_1__SEL_1 or
MUX_wmi_mFlagF_q_0_write_1__VAL_1 or
MUX_wmi_mFlagF_q_0_write_1__SEL_2 or
value__h6387 or WILL_FIRE_RL_wmi_mFlagF_decCtr or wmi_mFlagF_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wmi_mFlagF_q_0_write_1__SEL_1:
wmi_mFlagF_q_0_D_IN = MUX_wmi_mFlagF_q_0_write_1__VAL_1;
MUX_wmi_mFlagF_q_0_write_1__SEL_2: wmi_mFlagF_q_0_D_IN = value__h6387;
WILL_FIRE_RL_wmi_mFlagF_decCtr: wmi_mFlagF_q_0_D_IN = wmi_mFlagF_q_1;
default: wmi_mFlagF_q_0_D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmi_mFlagF_q_0_EN =
WILL_FIRE_RL_wmi_mFlagF_both && _dfoo11 ||
WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_cntr_r == 2'd0 ||
WILL_FIRE_RL_wmi_mFlagF_decCtr ;
// register wmi_mFlagF_q_1
always@(MUX_wmi_mFlagF_q_1_write_1__SEL_1 or
MUX_wmi_mFlagF_q_1_write_1__VAL_1 or
MUX_wmi_mFlagF_q_1_write_1__SEL_2 or
value__h6387 or WILL_FIRE_RL_wmi_mFlagF_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wmi_mFlagF_q_1_write_1__SEL_1:
wmi_mFlagF_q_1_D_IN = MUX_wmi_mFlagF_q_1_write_1__VAL_1;
MUX_wmi_mFlagF_q_1_write_1__SEL_2: wmi_mFlagF_q_1_D_IN = value__h6387;
WILL_FIRE_RL_wmi_mFlagF_decCtr: wmi_mFlagF_q_1_D_IN = 32'd0;
default: wmi_mFlagF_q_1_D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmi_mFlagF_q_1_EN =
WILL_FIRE_RL_wmi_mFlagF_both && _dfoo9 ||
WILL_FIRE_RL_wmi_mFlagF_incCtr && wmi_mFlagF_cntr_r == 2'd1 ||
WILL_FIRE_RL_wmi_mFlagF_decCtr ;
// register wmi_operateD
assign wmi_operateD_D_IN = wci_wslv_cState == 3'd2 ;
assign wmi_operateD_EN = 1'd1 ;
// register wmi_peerIsReady
assign wmi_peerIsReady_D_IN = wmiM0_SReset_n ;
assign wmi_peerIsReady_EN = 1'd1 ;
// register wmi_reqF_cntr_r
assign wmi_reqF_cntr_r_D_IN =
WILL_FIRE_RL_wmi_reqF_decCtr ?
wmi_reqF_cntr_r_61_MINUS_1___d169 :
MUX_wmi_reqF_cntr_r_write_1__VAL_2 ;
assign wmi_reqF_cntr_r_EN =
WILL_FIRE_RL_wmi_reqF_decCtr || WILL_FIRE_RL_wmi_reqF_incCtr ;
// register wmi_reqF_q_0
always@(MUX_wmi_reqF_q_0_write_1__SEL_1 or
MUX_wmi_reqF_q_0_write_1__VAL_1 or
MUX_wmi_reqF_q_0_write_1__SEL_2 or
MUX_wmi_reqF_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wmi_reqF_decCtr or wmi_reqF_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wmi_reqF_q_0_write_1__SEL_1:
wmi_reqF_q_0_D_IN = MUX_wmi_reqF_q_0_write_1__VAL_1;
MUX_wmi_reqF_q_0_write_1__SEL_2:
wmi_reqF_q_0_D_IN = MUX_wmi_reqF_q_0_write_1__VAL_2;
WILL_FIRE_RL_wmi_reqF_decCtr: wmi_reqF_q_0_D_IN = wmi_reqF_q_1;
default: wmi_reqF_q_0_D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmi_reqF_q_0_EN =
WILL_FIRE_RL_wmi_reqF_both && _dfoo7 ||
WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_cntr_r == 2'd0 ||
WILL_FIRE_RL_wmi_reqF_decCtr ;
// register wmi_reqF_q_1
always@(MUX_wmi_reqF_q_1_write_1__SEL_1 or
MUX_wmi_reqF_q_1_write_1__VAL_1 or
MUX_wmi_reqF_q_1_write_1__SEL_2 or
MUX_wmi_reqF_q_0_write_1__VAL_2 or WILL_FIRE_RL_wmi_reqF_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wmi_reqF_q_1_write_1__SEL_1:
wmi_reqF_q_1_D_IN = MUX_wmi_reqF_q_1_write_1__VAL_1;
MUX_wmi_reqF_q_1_write_1__SEL_2:
wmi_reqF_q_1_D_IN = MUX_wmi_reqF_q_0_write_1__VAL_2;
WILL_FIRE_RL_wmi_reqF_decCtr: wmi_reqF_q_1_D_IN = 32'd0;
default: wmi_reqF_q_1_D_IN = 32'hAAAAAAAA /* unspecified value */ ;
endcase
end
assign wmi_reqF_q_1_EN =
WILL_FIRE_RL_wmi_reqF_both && _dfoo5 ||
WILL_FIRE_RL_wmi_reqF_incCtr && wmi_reqF_cntr_r == 2'd1 ||
WILL_FIRE_RL_wmi_reqF_decCtr ;
// register wmi_sDataThreadBusy_d
assign wmi_sDataThreadBusy_d_D_IN = wmiM0_SDataThreadBusy ;
assign wmi_sDataThreadBusy_d_EN = 1'd1 ;
// register wmi_sFlagReg
assign wmi_sFlagReg_D_IN = wmiM0_SFlag ;
assign wmi_sFlagReg_EN = 1'd1 ;
// register wmi_sThreadBusy_d
assign wmi_sThreadBusy_d_D_IN = wmiM0_SThreadBusy ;
assign wmi_sThreadBusy_d_EN = 1'd1 ;
// register wmi_statusR
assign wmi_statusR_D_IN = 8'h0 ;
assign wmi_statusR_EN = 1'b0 ;
// register wmi_trafficSticky
assign wmi_trafficSticky_D_IN = 1'b0 ;
assign wmi_trafficSticky_EN = 1'b0 ;
// register wmwtBeginCount
assign wmwtBeginCount_D_IN = wmwtBeginCount + 32'd1 ;
assign wmwtBeginCount_EN = WILL_FIRE_RL_wmwt_mesgBegin ;
// register wmwtFinalCount
assign wmwtFinalCount_D_IN = wmwtFinalCount + 32'd1 ;
assign wmwtFinalCount_EN = WILL_FIRE_RL_wmwt_messageFinalize ;
// register wmwtPushCount
assign wmwtPushCount_D_IN = wmwtPushCount + 32'd1 ;
assign wmwtPushCount_EN = MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ;
// register wsiM_burstKind
assign wsiM_burstKind_D_IN =
(wsiM_burstKind == 2'd0) ?
(wsiM_reqFifo_q_0[164] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiM_burstKind_EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[168:166] == 3'd1 &&
(wsiM_burstKind == 2'd0 ||
(wsiM_burstKind == 2'd1 || wsiM_burstKind == 2'd2) &&
wsiM_reqFifo_q_0[165]) ;
// register wsiM_errorSticky
assign wsiM_errorSticky_D_IN = 1'b0 ;
assign wsiM_errorSticky_EN = 1'b0 ;
// register wsiM_iMesgCount
assign wsiM_iMesgCount_D_IN = wsiM_iMesgCount + 32'd1 ;
assign wsiM_iMesgCount_EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[168:166] == 3'd1 &&
wsiM_burstKind == 2'd2 &&
wsiM_reqFifo_q_0[165] ;
// register wsiM_isReset_isInReset
assign wsiM_isReset_isInReset_D_IN = 1'd0 ;
assign wsiM_isReset_isInReset_EN = wsiM_isReset_isInReset ;
// register wsiM_operateD
assign wsiM_operateD_D_IN = wci_wslv_cState == 3'd2 ;
assign wsiM_operateD_EN = 1'd1 ;
// register wsiM_pMesgCount
assign wsiM_pMesgCount_D_IN = wsiM_pMesgCount + 32'd1 ;
assign wsiM_pMesgCount_EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[168:166] == 3'd1 &&
wsiM_burstKind == 2'd1 &&
wsiM_reqFifo_q_0[165] ;
// register wsiM_peerIsReady
assign wsiM_peerIsReady_D_IN = wsiM0_SReset_n ;
assign wsiM_peerIsReady_EN = 1'd1 ;
// register wsiM_reqFifo_cntr_r
assign wsiM_reqFifo_cntr_r_D_IN =
WILL_FIRE_RL_wsiM_reqFifo_decCtr ?
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 :
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_2 ;
assign wsiM_reqFifo_cntr_r_EN =
WILL_FIRE_RL_wsiM_reqFifo_decCtr ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr ;
// register wsiM_reqFifo_q_0
always@(MUX_wsiM_reqFifo_q_0_write_1__SEL_1 or
MUX_wsiM_reqFifo_q_0_write_1__VAL_1 or
MUX_wsiM_reqFifo_q_0_write_1__SEL_2 or
MUX_wsiM_reqFifo_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1)
begin
case (1'b1) // synopsys parallel_case
MUX_wsiM_reqFifo_q_0_write_1__SEL_1:
wsiM_reqFifo_q_0_D_IN = MUX_wsiM_reqFifo_q_0_write_1__VAL_1;
MUX_wsiM_reqFifo_q_0_write_1__SEL_2:
wsiM_reqFifo_q_0_D_IN = MUX_wsiM_reqFifo_q_0_write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_0_D_IN = wsiM_reqFifo_q_1;
default: wsiM_reqFifo_q_0_D_IN =
169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_0_EN =
WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo19 ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr &&
wsiM_reqFifo_cntr_r == 2'd0 ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_reqFifo_q_1
always@(MUX_wsiM_reqFifo_q_1_write_1__SEL_1 or
MUX_wsiM_reqFifo_q_1_write_1__VAL_1 or
MUX_wsiM_reqFifo_q_1_write_1__SEL_2 or
MUX_wsiM_reqFifo_q_0_write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr)
begin
case (1'b1) // synopsys parallel_case
MUX_wsiM_reqFifo_q_1_write_1__SEL_1:
wsiM_reqFifo_q_1_D_IN = MUX_wsiM_reqFifo_q_1_write_1__VAL_1;
MUX_wsiM_reqFifo_q_1_write_1__SEL_2:
wsiM_reqFifo_q_1_D_IN = MUX_wsiM_reqFifo_q_0_write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_1_D_IN =
169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
default: wsiM_reqFifo_q_1_D_IN =
169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_1_EN =
WILL_FIRE_RL_wsiM_reqFifo_both && _dfoo17 ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr &&
wsiM_reqFifo_cntr_r == 2'd1 ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_sThreadBusy_d
assign wsiM_sThreadBusy_d_D_IN = wsiM0_SThreadBusy ;
assign wsiM_sThreadBusy_d_EN = 1'd1 ;
// register wsiM_statusR
assign wsiM_statusR_D_IN =
{ wsiM_isReset_isInReset,
!wsiM_peerIsReady,
!wsiM_operateD,
wsiM_errorSticky,
wsiM_burstKind != 2'd0,
wsiM_sThreadBusy_d,
1'd0,
wsiM_trafficSticky } ;
assign wsiM_statusR_EN = 1'd1 ;
// register wsiM_tBusyCount
assign wsiM_tBusyCount_D_IN = wsiM_tBusyCount + 32'd1 ;
assign wsiM_tBusyCount_EN =
wsiM_operateD && wsiM_peerIsReady && wsiM_sThreadBusy_d ;
// register wsiM_trafficSticky
assign wsiM_trafficSticky_D_IN = 1'd1 ;
assign wsiM_trafficSticky_EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[168:166] == 3'd1 ;
// register wsiS_burstKind
assign wsiS_burstKind_D_IN =
(wsiS_burstKind == 2'd0) ?
(wsiS_wsiReq_wget[164] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiS_burstKind_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq &&
(wsiS_burstKind == 2'd0 ||
(wsiS_burstKind == 2'd1 || wsiS_burstKind == 2'd2) &&
wsiS_wsiReq_wget[165]) ;
// register wsiS_errorSticky
assign wsiS_errorSticky_D_IN = 1'b0 ;
assign wsiS_errorSticky_EN = 1'b0 ;
// register wsiS_iMesgCount
assign wsiS_iMesgCount_D_IN = wsiS_iMesgCount + 32'd1 ;
assign wsiS_iMesgCount_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd2 &&
wsiS_wsiReq_wget[165] ;
// register wsiS_isReset_isInReset
assign wsiS_isReset_isInReset_D_IN = 1'd0 ;
assign wsiS_isReset_isInReset_EN = wsiS_isReset_isInReset ;
// register wsiS_mesgWordLength
assign wsiS_mesgWordLength_D_IN = wsiS_wordCount ;
assign wsiS_mesgWordLength_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_wsiReq_wget[165] ;
// register wsiS_operateD
assign wsiS_operateD_D_IN = wci_wslv_cState == 3'd2 ;
assign wsiS_operateD_EN = 1'd1 ;
// register wsiS_pMesgCount
assign wsiS_pMesgCount_D_IN = wsiS_pMesgCount + 32'd1 ;
assign wsiS_pMesgCount_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq && wsiS_burstKind == 2'd1 &&
wsiS_wsiReq_wget[165] ;
// register wsiS_peerIsReady
assign wsiS_peerIsReady_D_IN = wsiS0_MReset_n ;
assign wsiS_peerIsReady_EN = 1'd1 ;
// register wsiS_reqFifo_countReg
assign wsiS_reqFifo_countReg_D_IN =
WILL_FIRE_RL_wsiS_reqFifo_enq ?
wsiS_reqFifo_countReg + 2'd1 :
wsiS_reqFifo_countReg - 2'd1 ;
assign wsiS_reqFifo_countReg_EN =
WILL_FIRE_RL_wsiS_reqFifo_enq != wsiS_reqFifo_r_deq_whas ;
// register wsiS_reqFifo_levelsValid
assign wsiS_reqFifo_levelsValid_D_IN = WILL_FIRE_RL_wsiS_reqFifo_reset ;
assign wsiS_reqFifo_levelsValid_EN =
WILL_FIRE_RL_wsipass_doMessagePush ||
MUX_wsiS_reqFifo_levelsValid_write_1__SEL_3 ||
WILL_FIRE_RL_wsiS_reqFifo_enq ||
WILL_FIRE_RL_wsiS_reqFifo_reset ;
// register wsiS_statusR
assign wsiS_statusR_D_IN =
{ wsiS_isReset_isInReset,
!wsiS_peerIsReady,
!wsiS_operateD,
wsiS_errorSticky,
wsiS_burstKind != 2'd0,
!wsiS_sThreadBusy_dw_whas || wsiS_sThreadBusy_dw_wget,
1'd0,
wsiS_trafficSticky } ;
assign wsiS_statusR_EN = 1'd1 ;
// register wsiS_tBusyCount
assign wsiS_tBusyCount_D_IN = wsiS_tBusyCount + 32'd1 ;
assign wsiS_tBusyCount_EN =
wsiS_operateD && wsiS_peerIsReady &&
(!wsiS_sThreadBusy_dw_whas || wsiS_sThreadBusy_dw_wget) ;
// register wsiS_trafficSticky
assign wsiS_trafficSticky_D_IN = 1'd1 ;
assign wsiS_trafficSticky_EN = WILL_FIRE_RL_wsiS_reqFifo_enq ;
// register wsiS_wordCount
assign wsiS_wordCount_D_IN =
wsiS_wsiReq_wget[165] ? 12'd1 : wsiS_wordCount + 12'd1 ;
assign wsiS_wordCount_EN = WILL_FIRE_RL_wsiS_reqFifo_enq ;
// submodule mesgTokenF
assign mesgTokenF_ENQ = WILL_FIRE_RL_wmwt_mesgBegin ;
assign mesgTokenF_DEQ = WILL_FIRE_RL_wmwt_messageFinalize ;
assign mesgTokenF_CLR = 1'b0 ;
// submodule respF_memory
assign respF_memory_ADDRA = respF_rWrPtr[10:0] ;
assign respF_memory_ADDRB =
WILL_FIRE_RL_wmrd_mesgResptoWsi ?
x__h16253[10:0] :
respF_rRdPtr[10:0] ;
assign respF_memory_DIA =
{ IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d431,
respF_pwEnqueue_whas && respF_wDataIn_wget[165],
respF_pwEnqueue_whas && respF_wDataIn_wget[164],
IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d437 } ;
assign respF_memory_DIB =
169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign respF_memory_WEA = respF_pwEnqueue_whas ;
assign respF_memory_WEB = 1'd0 ;
assign respF_memory_ENA = 1'b1 ;
assign respF_memory_ENB = 1'b1 ;
// submodule wci_wslv_reqF
assign wci_wslv_reqF_D_IN = wci_wslv_wciReq_wget ;
assign wci_wslv_reqF_ENQ = wci_wslv_wciReq_wget[71:69] != 3'd0 ;
assign wci_wslv_reqF_DEQ = wci_wslv_reqF_r_deq_whas ;
assign wci_wslv_reqF_CLR = 1'b0 ;
// submodule wmi_respF
assign wmi_respF_D_IN = wmi_wmiResponse_wget ;
assign wmi_respF_ENQ =
wmi_respF_FULL_N && wmi_operateD && wmi_peerIsReady &&
wmi_wmiResponse_wget[129:128] != 2'd0 ;
assign wmi_respF_DEQ = MUX_unrollCnt_write_1__SEL_2 ;
assign wmi_respF_CLR = 1'b0 ;
// submodule wsiS_reqFifo
assign wsiS_reqFifo_D_IN = wsiS_wsiReq_wget ;
assign wsiS_reqFifo_ENQ = WILL_FIRE_RL_wsiS_reqFifo_enq ;
assign wsiS_reqFifo_DEQ = wsiS_reqFifo_r_deq_whas ;
assign wsiS_reqFifo_CLR = 1'b0 ;
// remaining internal signals
assign IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d431 =
respF_pwEnqueue_whas ? respF_wDataIn_wget[168:166] : 3'd0 ;
assign IF_respF_wDataIn_whas__28_THEN_respF_wDataIn_w_ETC___d437 =
respF_pwEnqueue_whas ? respF_wDataIn_wget[163:0] : 164'd0 ;
assign NOT_wmi_reqF_cntr_r_61_EQ_2_73_74_AND_wmi_oper_ETC___d521 =
wmi_reqF_cntr_r != 2'd2 && wmi_operateD && wmi_peerIsReady &&
(!x__h18328 || wmi_mFlagF_cntr_r != 2'd2) ;
assign _dfoo1 =
wci_wslv_respF_cntr_r != 2'd2 ||
wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd1 ;
assign _dfoo11 =
wmi_mFlagF_cntr_r != 2'd1 ||
wmi_mFlagF_cntr_r_83_MINUS_1___d191 == 2'd0 ;
assign _dfoo13 =
wmi_dhF_cntr_r != 2'd2 ||
wmi_dhF_cntr_r_05_MINUS_1___d213 == 2'd1 ;
assign _dfoo15 =
wmi_dhF_cntr_r != 2'd1 ||
wmi_dhF_cntr_r_05_MINUS_1___d213 == 2'd0 ;
assign _dfoo17 =
wsiM_reqFifo_cntr_r != 2'd2 ||
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 == 2'd1 ;
assign _dfoo19 =
wsiM_reqFifo_cntr_r != 2'd1 ||
MUX_wsiM_reqFifo_cntr_r_write_1__VAL_1 == 2'd0 ;
assign _dfoo3 =
wci_wslv_respF_cntr_r != 2'd1 ||
wci_wslv_respF_cntr_r_8_MINUS_1___d27 == 2'd0 ;
assign _dfoo5 =
wmi_reqF_cntr_r != 2'd2 ||
wmi_reqF_cntr_r_61_MINUS_1___d169 == 2'd1 ;
assign _dfoo7 =
wmi_reqF_cntr_r != 2'd1 ||
wmi_reqF_cntr_r_61_MINUS_1___d169 == 2'd0 ;
assign _dfoo9 =
wmi_mFlagF_cntr_r != 2'd2 ||
wmi_mFlagF_cntr_r_83_MINUS_1___d191 == 2'd1 ;
assign b__h14802 = -fabWordsCurReq[11:0] ;
assign b__h17784 = x__h17904 + residue__h17647 ;
assign b__h18157 = { {2{fabRespCredit_value[11]}}, fabRespCredit_value } ;
assign mesgMetaF_length__h23070 =
(wsiS_reqFifo_D_OUT[165] && wsiS_reqFifo_D_OUT[23:8] == 16'd0 &&
mesgLengthSoFar == 14'd0) ?
24'd0 :
{ 10'd0, mlB__h22903 } ;
assign mesgMetaF_opcode__h23069 = opcode[8] ? opcode[7:0] : 8'd0 ;
assign mlB__h22903 = mesgLengthSoFar + mlInc__h22902 ;
assign mlInc__h22902 =
wsiS_reqFifo_D_OUT[165] ?
{ 9'd0, x__h23108 + y__h23109 } :
14'd16 ;
assign rdat__h24980 = hasDebugLogic ? mesgCount : 32'd0 ;
assign rdat__h24986 = hasDebugLogic ? abortCount : 32'd0 ;
assign rdat__h24992 = hasDebugLogic ? thisMesg : 32'd0 ;
assign rdat__h25005 = hasDebugLogic ? lastMesg : 32'd0 ;
assign rdat__h25028 = hasDebugLogic ? { 16'd0, x__h25032 } : 32'd0 ;
assign rdat__h25128 = hasDebugLogic ? wsiS_extStatusW_wget[95:64] : 32'd0 ;
assign rdat__h25142 = hasDebugLogic ? wsiS_extStatusW_wget[63:32] : 32'd0 ;
assign rdat__h25150 = hasDebugLogic ? wsiS_extStatusW_wget[31:0] : 32'd0 ;
assign rdat__h25156 = hasDebugLogic ? wsiM_extStatusW_wget[95:64] : 32'd0 ;
assign rdat__h25170 = hasDebugLogic ? wsiM_extStatusW_wget[63:32] : 32'd0 ;
assign rdat__h25178 = hasDebugLogic ? wsiM_extStatusW_wget[31:0] : 32'd0 ;
assign rdat__h25184 = hasDebugLogic ? wmwtBeginCount : 32'd0 ;
assign rdat__h25190 = hasDebugLogic ? wmwtPushCount : 32'd0 ;
assign rdat__h25196 = hasDebugLogic ? wmwtFinalCount : 32'd0 ;
assign rdat__h25202 = hasDebugLogic ? { 31'd0, x__h25206 } : 32'd0 ;
assign rdat__h25212 = hasDebugLogic ? 32'hFEEDC0DE : 32'd0 ;
assign residue__h17647 =
({ 2'd0, wmi_sFlagReg[3:0] } == 6'd0) ? 24'd0 : 24'd1 ;
assign sendData_burstLength__h18617 =
(thisMesg[15:0] == 16'd0 || smaCtrl[5] && unrollCnt == 16'd1) ?
12'd1 :
(smaCtrl[5] ? 12'd4095 : wsiBurstLength__h18535[11:0]) ;
assign sendData_byteEn__h18619 =
(thisMesg[15:0] == 16'd0) ?
thisMesg[15:0] :
((unrollCnt == 16'd1) ? x__h18676[15:0] : 16'd65535) ;
assign value__h6387 =
MUX_wmi_mFlagF_x_wire_wset_1__SEL_1 ?
32'hAAAAAAAA /* unspecified value */ :
MUX_wmi_mFlagF_x_wire_wset_1__VAL_2 ;
assign wci_wslv_respF_cntr_r_8_MINUS_1___d27 =
wci_wslv_respF_cntr_r - 2'd1 ;
assign wmi_dhF_cntr_r_05_MINUS_1___d213 = wmi_dhF_cntr_r - 2'd1 ;
assign wmi_mFlagF_cntr_r_83_MINUS_1___d191 = wmi_mFlagF_cntr_r - 2'd1 ;
assign wmi_reqF_cntr_r_61_MINUS_1___d169 = wmi_reqF_cntr_r - 2'd1 ;
assign wmi_respF_i_notEmpty__34_AND_smaCtrl_62_BIT_4__ETC___d539 =
wmi_respF_EMPTY_N &&
(smaCtrl[4] || respF_rRdPtr + 12'd1024 != respF_rWrPtr) ;
assign wsiBurstLength__h18535 =
smaCtrl[5] ? 16'd2 : { 4'd0, thisMesg[15:4] } ;
assign wsiS_reqFifo_i_notEmpty__61_AND_NOT_smaCtrl_62_ETC___d667 =
wsiS_reqFifo_EMPTY_N &&
(smaCtrl[3:0] != 4'h3 || wsiM_reqFifo_cntr_r != 2'd2) &&
(!wsiS_reqFifo_D_OUT[165] || wmi_mFlagF_cntr_r != 2'd2) ;
assign x__h16103 = respF_rWrPtr + 12'd1 ;
assign x__h16253 = respF_rRdPtr + 12'd1 ;
assign x__h17904 = { 4'd0, wmi_sFlagReg[23:4] } ;
assign x__h18328 = fabWordsRemain == fabWordsCurReq ;
assign x__h18676 =
({ 2'd0, thisMesg[3:0] } == 6'd0) ?
32'hFFFFFFFF :
(({ 2'd0, thisMesg[3:0] } <= 6'd1) ?
32'd1 :
(({ 2'd0, thisMesg[3:0] } <= 6'd2) ?
32'd3 :
(({ 2'd0, thisMesg[3:0] } <= 6'd3) ?
32'd7 :
(({ 2'd0, thisMesg[3:0] } <= 6'd4) ?
32'd15 :
(({ 2'd0, thisMesg[3:0] } <= 6'd5) ?
32'd31 :
(({ 2'd0, thisMesg[3:0] } <= 6'd6) ?
32'd63 :
(({ 2'd0, thisMesg[3:0] } <= 6'd7) ?
32'd127 :
(({ 2'd0, thisMesg[3:0] } <= 6'd8) ?
32'd255 :
(({ 2'd0, thisMesg[3:0] } <= 6'd9) ?
32'd511 :
(({ 2'd0, thisMesg[3:0] } <=
6'd10) ?
32'd1023 :
(({ 2'd0, thisMesg[3:0] } <=
6'd11) ?
32'd2047 :
(({ 2'd0, thisMesg[3:0] } <=
6'd12) ?
32'd4095 :
(({ 2'd0,
thisMesg[3:0] } <=
6'd13) ?
32'd8191 :
(({ 2'd0,
thisMesg[3:0] } <=
6'd14) ?
32'd16383 :
(({ 2'd0,
thisMesg[3:0] } <=
6'd15) ?
32'd32767 :
(({ 2'd0,
thisMesg[3:0] } <=
6'd16) ?
32'd65535 :
(({ 2'd0,
thisMesg[3:0] } <=
6'd17) ?
32'd131071 :
(({ 2'd0,
thisMesg[3:0] } <=
6'd18) ?
32'd262143 :
(({ 2'd0,
thisMesg[3:0] } <=
6'd19) ?
32'd524287 :
(({ 2'd0,
thisMesg[3:0] } <=
6'd20) ?
32'd1048575 :
(({ 2'd0,
thisMesg[3:0] } <=
6'd21) ?
32'd2097151 :
(({ 2'd0,
thisMesg[3:0] } <=
6'd22) ?
32'd4194303 :
(({ 2'd0,
thisMesg[3:0] } <=
6'd23) ?
32'd8388607 :
(({ 2'd0,
thisMesg[3:0] } <=
6'd24) ?
32'd16777215 :
(({ 2'd0,
thisMesg[3:0] } <=
6'd25) ?
32'd33554431 :
(({ 2'd0,
thisMesg[3:0] } <=
6'd26) ?
32'd67108863 :
(({ 2'd0,
thisMesg[3:0] } <=
6'd27) ?
32'd134217727 :
(({ 2'd0,
thisMesg[3:0] } <=
6'd28) ?
32'd268435455 :
(({ 2'd0,
thisMesg[3:0] } <=
6'd29) ?
32'd536870911 :
(({ 2'd0,
thisMesg[3:0] } <=
6'd30) ?
32'd1073741823 :
(({ 2'd0,
thisMesg[3:0] } <=
6'd31) ?
32'h7FFFFFFF :
32'hFFFFFFFF))))))))))))))))))))))))))))))) ;
assign x__h23108 = x__h23120 + y__h23121 ;
assign x__h23120 = x__h23132 + y__h23133 ;
assign x__h23132 = x__h23144 + y__h23145 ;
assign x__h23144 = x__h23156 + y__h23157 ;
assign x__h23156 = x__h23168 + y__h23169 ;
assign x__h23168 = x__h23180 + y__h23181 ;
assign x__h23180 = x__h23192 + y__h23193 ;
assign x__h23192 = x__h23204 + y__h23205 ;
assign x__h23204 = x__h23216 + y__h23217 ;
assign x__h23216 = x__h23228 + y__h23229 ;
assign x__h23228 = x__h23240 + y__h23241 ;
assign x__h23240 = x__h23252 + y__h23253 ;
assign x__h23252 = x__h23264 + y__h23265 ;
assign x__h23264 = x__h23276 + y__h23277 ;
assign x__h23276 = { 4'd0, wsiS_reqFifo_D_OUT[23] } ;
assign x__h25032 = { wsiS_statusR, wsiM_statusR } ;
assign x__h25206 = wmi_sThreadBusy_d || wmi_sDataThreadBusy_d ;
assign x_length__h23961 = { 2'd0, mlB__h22903 } ;
assign y__h23109 = { 4'd0, wsiS_reqFifo_D_OUT[8] } ;
assign y__h23121 = { 4'd0, wsiS_reqFifo_D_OUT[9] } ;
assign y__h23133 = { 4'd0, wsiS_reqFifo_D_OUT[10] } ;
assign y__h23145 = { 4'd0, wsiS_reqFifo_D_OUT[11] } ;
assign y__h23157 = { 4'd0, wsiS_reqFifo_D_OUT[12] } ;
assign y__h23169 = { 4'd0, wsiS_reqFifo_D_OUT[13] } ;
assign y__h23181 = { 4'd0, wsiS_reqFifo_D_OUT[14] } ;
assign y__h23193 = { 4'd0, wsiS_reqFifo_D_OUT[15] } ;
assign y__h23205 = { 4'd0, wsiS_reqFifo_D_OUT[16] } ;
assign y__h23217 = { 4'd0, wsiS_reqFifo_D_OUT[17] } ;
assign y__h23229 = { 4'd0, wsiS_reqFifo_D_OUT[18] } ;
assign y__h23241 = { 4'd0, wsiS_reqFifo_D_OUT[19] } ;
assign y__h23253 = { 4'd0, wsiS_reqFifo_D_OUT[20] } ;
assign y__h23265 = { 4'd0, wsiS_reqFifo_D_OUT[21] } ;
assign y__h23277 = { 4'd0, wsiS_reqFifo_D_OUT[22] } ;
always@(wci_wslv_reqF_D_OUT or
smaCtrl or
rdat__h24980 or
rdat__h24986 or
rdat__h24992 or
rdat__h25005 or
rdat__h25028 or
rdat__h25128 or
rdat__h25142 or
rdat__h25150 or
rdat__h25156 or
rdat__h25170 or
rdat__h25178 or
rdat__h25184 or
rdat__h25190 or rdat__h25196 or rdat__h25202 or rdat__h25212)
begin
case (wci_wslv_reqF_D_OUT[39:32])
8'h0: g_data__h24937 = smaCtrl;
8'h04: g_data__h24937 = rdat__h24980;
8'h08: g_data__h24937 = rdat__h24986;
8'h10: g_data__h24937 = rdat__h24992;
8'h14: g_data__h24937 = rdat__h25005;
8'h18: g_data__h24937 = rdat__h25028;
8'h20: g_data__h24937 = rdat__h25128;
8'h24: g_data__h24937 = rdat__h25142;
8'h28: g_data__h24937 = rdat__h25150;
8'h2C: g_data__h24937 = rdat__h25156;
8'h30: g_data__h24937 = rdat__h25170;
8'h34: g_data__h24937 = rdat__h25178;
8'h38: g_data__h24937 = rdat__h25184;
8'h3C: g_data__h24937 = rdat__h25190;
8'h40: g_data__h24937 = rdat__h25196;
8'h44: g_data__h24937 = rdat__h25202;
8'h48: g_data__h24937 = rdat__h25212;
default: g_data__h24937 = 32'd0;
endcase
end
// handling of inlined registers
always@(posedge wciS0_Clk)
begin
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
abortCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
doAbort <= `BSV_ASSIGNMENT_DELAY 1'd0;
endOfMessage <= `BSV_ASSIGNMENT_DELAY 1'd0;
errCount <= `BSV_ASSIGNMENT_DELAY 128'd0;
fabRespCredit_value <= `BSV_ASSIGNMENT_DELAY 12'd0;
fabWordsRemain <= `BSV_ASSIGNMENT_DELAY 14'd0;
firstMsgReq <= `BSV_ASSIGNMENT_DELAY 1'd0;
lastMesg <= `BSV_ASSIGNMENT_DELAY 32'hFEFEFFFE;
mesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
mesgLengthSoFar <= `BSV_ASSIGNMENT_DELAY 14'd0;
mesgPreRequest <= `BSV_ASSIGNMENT_DELAY 1'd0;
mesgReqOK <= `BSV_ASSIGNMENT_DELAY 1'd0;
opcode <= `BSV_ASSIGNMENT_DELAY 9'd170;
readyToPush <= `BSV_ASSIGNMENT_DELAY 1'd0;
readyToRequest <= `BSV_ASSIGNMENT_DELAY 1'd0;
respF_rCache <= `BSV_ASSIGNMENT_DELAY
182'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
respF_rRdPtr <= `BSV_ASSIGNMENT_DELAY 12'd0;
respF_rWrPtr <= `BSV_ASSIGNMENT_DELAY 12'd0;
smaCtrl <= `BSV_ASSIGNMENT_DELAY smaCtrlInit;
thisMesg <= `BSV_ASSIGNMENT_DELAY 32'hFEFEFFFE;
unrollCnt <= `BSV_ASSIGNMENT_DELAY 16'd0;
valExpect <= `BSV_ASSIGNMENT_DELAY 128'd0;
wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2;
wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wmi_busyWithMessage <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_dhF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wmi_dhF_q_0 <= `BSV_ASSIGNMENT_DELAY 146'd0;
wmi_dhF_q_1 <= `BSV_ASSIGNMENT_DELAY 146'd0;
wmi_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_mFlagF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wmi_mFlagF_q_0 <= `BSV_ASSIGNMENT_DELAY 32'd0;
wmi_mFlagF_q_1 <= `BSV_ASSIGNMENT_DELAY 32'd0;
wmi_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wmi_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY 32'd0;
wmi_reqF_q_1 <= `BSV_ASSIGNMENT_DELAY 32'd0;
wmi_sDataThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_sFlagReg <= `BSV_ASSIGNMENT_DELAY 32'd0;
wmi_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmi_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wmwtBeginCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wmwtFinalCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wmwtPushCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY
169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY
169'h00000AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA00;
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY 12'd1;
end
else
begin
if (abortCount_EN)
abortCount <= `BSV_ASSIGNMENT_DELAY abortCount_D_IN;
if (doAbort_EN) doAbort <= `BSV_ASSIGNMENT_DELAY doAbort_D_IN;
if (endOfMessage_EN)
endOfMessage <= `BSV_ASSIGNMENT_DELAY endOfMessage_D_IN;
if (errCount_EN) errCount <= `BSV_ASSIGNMENT_DELAY errCount_D_IN;
if (fabRespCredit_value_EN)
fabRespCredit_value <= `BSV_ASSIGNMENT_DELAY
fabRespCredit_value_D_IN;
if (fabWordsRemain_EN)
fabWordsRemain <= `BSV_ASSIGNMENT_DELAY fabWordsRemain_D_IN;
if (firstMsgReq_EN)
firstMsgReq <= `BSV_ASSIGNMENT_DELAY firstMsgReq_D_IN;
if (lastMesg_EN) lastMesg <= `BSV_ASSIGNMENT_DELAY lastMesg_D_IN;
if (mesgCount_EN) mesgCount <= `BSV_ASSIGNMENT_DELAY mesgCount_D_IN;
if (mesgLengthSoFar_EN)
mesgLengthSoFar <= `BSV_ASSIGNMENT_DELAY mesgLengthSoFar_D_IN;
if (mesgPreRequest_EN)
mesgPreRequest <= `BSV_ASSIGNMENT_DELAY mesgPreRequest_D_IN;
if (mesgReqOK_EN) mesgReqOK <= `BSV_ASSIGNMENT_DELAY mesgReqOK_D_IN;
if (opcode_EN) opcode <= `BSV_ASSIGNMENT_DELAY opcode_D_IN;
if (readyToPush_EN)
readyToPush <= `BSV_ASSIGNMENT_DELAY readyToPush_D_IN;
if (readyToRequest_EN)
readyToRequest <= `BSV_ASSIGNMENT_DELAY readyToRequest_D_IN;
if (respF_rCache_EN)
respF_rCache <= `BSV_ASSIGNMENT_DELAY respF_rCache_D_IN;
if (respF_rRdPtr_EN)
respF_rRdPtr <= `BSV_ASSIGNMENT_DELAY respF_rRdPtr_D_IN;
if (respF_rWrPtr_EN)
respF_rWrPtr <= `BSV_ASSIGNMENT_DELAY respF_rWrPtr_D_IN;
if (smaCtrl_EN) smaCtrl <= `BSV_ASSIGNMENT_DELAY smaCtrl_D_IN;
if (thisMesg_EN) thisMesg <= `BSV_ASSIGNMENT_DELAY thisMesg_D_IN;
if (unrollCnt_EN) unrollCnt <= `BSV_ASSIGNMENT_DELAY unrollCnt_D_IN;
if (valExpect_EN) valExpect <= `BSV_ASSIGNMENT_DELAY valExpect_D_IN;
if (wci_wslv_cEdge_EN)
wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY wci_wslv_cEdge_D_IN;
if (wci_wslv_cState_EN)
wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY wci_wslv_cState_D_IN;
if (wci_wslv_ctlAckReg_EN)
wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_ctlAckReg_D_IN;
if (wci_wslv_ctlOpActive_EN)
wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY
wci_wslv_ctlOpActive_D_IN;
if (wci_wslv_illegalEdge_EN)
wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY
wci_wslv_illegalEdge_D_IN;
if (wci_wslv_nState_EN)
wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY wci_wslv_nState_D_IN;
if (wci_wslv_reqF_countReg_EN)
wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY
wci_wslv_reqF_countReg_D_IN;
if (wci_wslv_respF_cntr_r_EN)
wci_wslv_respF_cntr_r <= `BSV_ASSIGNMENT_DELAY
wci_wslv_respF_cntr_r_D_IN;
if (wci_wslv_respF_q_0_EN)
wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0_D_IN;
if (wci_wslv_respF_q_1_EN)
wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_1_D_IN;
if (wci_wslv_sFlagReg_EN)
wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_sFlagReg_D_IN;
if (wci_wslv_sThreadBusy_d_EN)
wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
wci_wslv_sThreadBusy_d_D_IN;
if (wmi_busyWithMessage_EN)
wmi_busyWithMessage <= `BSV_ASSIGNMENT_DELAY
wmi_busyWithMessage_D_IN;
if (wmi_dhF_cntr_r_EN)
wmi_dhF_cntr_r <= `BSV_ASSIGNMENT_DELAY wmi_dhF_cntr_r_D_IN;
if (wmi_dhF_q_0_EN)
wmi_dhF_q_0 <= `BSV_ASSIGNMENT_DELAY wmi_dhF_q_0_D_IN;
if (wmi_dhF_q_1_EN)
wmi_dhF_q_1 <= `BSV_ASSIGNMENT_DELAY wmi_dhF_q_1_D_IN;
if (wmi_errorSticky_EN)
wmi_errorSticky <= `BSV_ASSIGNMENT_DELAY wmi_errorSticky_D_IN;
if (wmi_mFlagF_cntr_r_EN)
wmi_mFlagF_cntr_r <= `BSV_ASSIGNMENT_DELAY wmi_mFlagF_cntr_r_D_IN;
if (wmi_mFlagF_q_0_EN)
wmi_mFlagF_q_0 <= `BSV_ASSIGNMENT_DELAY wmi_mFlagF_q_0_D_IN;
if (wmi_mFlagF_q_1_EN)
wmi_mFlagF_q_1 <= `BSV_ASSIGNMENT_DELAY wmi_mFlagF_q_1_D_IN;
if (wmi_operateD_EN)
wmi_operateD <= `BSV_ASSIGNMENT_DELAY wmi_operateD_D_IN;
if (wmi_peerIsReady_EN)
wmi_peerIsReady <= `BSV_ASSIGNMENT_DELAY wmi_peerIsReady_D_IN;
if (wmi_reqF_cntr_r_EN)
wmi_reqF_cntr_r <= `BSV_ASSIGNMENT_DELAY wmi_reqF_cntr_r_D_IN;
if (wmi_reqF_q_0_EN)
wmi_reqF_q_0 <= `BSV_ASSIGNMENT_DELAY wmi_reqF_q_0_D_IN;
if (wmi_reqF_q_1_EN)
wmi_reqF_q_1 <= `BSV_ASSIGNMENT_DELAY wmi_reqF_q_1_D_IN;
if (wmi_sDataThreadBusy_d_EN)
wmi_sDataThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
wmi_sDataThreadBusy_d_D_IN;
if (wmi_sFlagReg_EN)
wmi_sFlagReg <= `BSV_ASSIGNMENT_DELAY wmi_sFlagReg_D_IN;
if (wmi_sThreadBusy_d_EN)
wmi_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wmi_sThreadBusy_d_D_IN;
if (wmi_trafficSticky_EN)
wmi_trafficSticky <= `BSV_ASSIGNMENT_DELAY wmi_trafficSticky_D_IN;
if (wmwtBeginCount_EN)
wmwtBeginCount <= `BSV_ASSIGNMENT_DELAY wmwtBeginCount_D_IN;
if (wmwtFinalCount_EN)
wmwtFinalCount <= `BSV_ASSIGNMENT_DELAY wmwtFinalCount_D_IN;
if (wmwtPushCount_EN)
wmwtPushCount <= `BSV_ASSIGNMENT_DELAY wmwtPushCount_D_IN;
if (wsiM_burstKind_EN)
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY wsiM_burstKind_D_IN;
if (wsiM_errorSticky_EN)
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiM_errorSticky_D_IN;
if (wsiM_iMesgCount_EN)
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_iMesgCount_D_IN;
if (wsiM_operateD_EN)
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY wsiM_operateD_D_IN;
if (wsiM_pMesgCount_EN)
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount_D_IN;
if (wsiM_peerIsReady_EN)
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady_D_IN;
if (wsiM_reqFifo_cntr_r_EN)
wsiM_reqFifo_cntr_r <= `BSV_ASSIGNMENT_DELAY
wsiM_reqFifo_cntr_r_D_IN;
if (wsiM_reqFifo_q_0_EN)
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0_D_IN;
if (wsiM_reqFifo_q_1_EN)
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_1_D_IN;
if (wsiM_sThreadBusy_d_EN)
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wsiM_sThreadBusy_d_D_IN;
if (wsiM_tBusyCount_EN)
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiM_tBusyCount_D_IN;
if (wsiM_trafficSticky_EN)
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiM_trafficSticky_D_IN;
if (wsiS_burstKind_EN)
wsiS_burstKind <= `BSV_ASSIGNMENT_DELAY wsiS_burstKind_D_IN;
if (wsiS_errorSticky_EN)
wsiS_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiS_errorSticky_D_IN;
if (wsiS_iMesgCount_EN)
wsiS_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_iMesgCount_D_IN;
if (wsiS_operateD_EN)
wsiS_operateD <= `BSV_ASSIGNMENT_DELAY wsiS_operateD_D_IN;
if (wsiS_pMesgCount_EN)
wsiS_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiS_pMesgCount_D_IN;
if (wsiS_peerIsReady_EN)
wsiS_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiS_peerIsReady_D_IN;
if (wsiS_reqFifo_countReg_EN)
wsiS_reqFifo_countReg <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_countReg_D_IN;
if (wsiS_reqFifo_levelsValid_EN)
wsiS_reqFifo_levelsValid <= `BSV_ASSIGNMENT_DELAY
wsiS_reqFifo_levelsValid_D_IN;
if (wsiS_tBusyCount_EN)
wsiS_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiS_tBusyCount_D_IN;
if (wsiS_trafficSticky_EN)
wsiS_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiS_trafficSticky_D_IN;
if (wsiS_wordCount_EN)
wsiS_wordCount <= `BSV_ASSIGNMENT_DELAY wsiS_wordCount_D_IN;
end
if (fabWordsCurReq_EN)
fabWordsCurReq <= `BSV_ASSIGNMENT_DELAY fabWordsCurReq_D_IN;
if (mesgReqAddr_EN) mesgReqAddr <= `BSV_ASSIGNMENT_DELAY mesgReqAddr_D_IN;
if (wmi_statusR_EN) wmi_statusR <= `BSV_ASSIGNMENT_DELAY wmi_statusR_D_IN;
if (wsiM_statusR_EN)
wsiM_statusR <= `BSV_ASSIGNMENT_DELAY wsiM_statusR_D_IN;
if (wsiS_mesgWordLength_EN)
wsiS_mesgWordLength <= `BSV_ASSIGNMENT_DELAY wsiS_mesgWordLength_D_IN;
if (wsiS_statusR_EN)
wsiS_statusR <= `BSV_ASSIGNMENT_DELAY wsiS_statusR_D_IN;
end
always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n)
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wmi_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (wci_wslv_isReset_isInReset_EN)
wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wci_wslv_isReset_isInReset_D_IN;
if (wmi_isReset_isInReset_EN)
wmi_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wmi_isReset_isInReset_D_IN;
if (wsiM_isReset_isInReset_EN)
wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsiM_isReset_isInReset_D_IN;
if (wsiS_isReset_isInReset_EN)
wsiS_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsiS_isReset_isInReset_D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
abortCount = 32'hAAAAAAAA;
doAbort = 1'h0;
endOfMessage = 1'h0;
errCount = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
fabRespCredit_value = 12'hAAA;
fabWordsCurReq = 14'h2AAA;
fabWordsRemain = 14'h2AAA;
firstMsgReq = 1'h0;
lastMesg = 32'hAAAAAAAA;
mesgCount = 32'hAAAAAAAA;
mesgLengthSoFar = 14'h2AAA;
mesgPreRequest = 1'h0;
mesgReqAddr = 14'h2AAA;
mesgReqOK = 1'h0;
opcode = 9'h0AA;
readyToPush = 1'h0;
readyToRequest = 1'h0;
respF_rCache = 182'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
respF_rRdPtr = 12'hAAA;
respF_rWrPtr = 12'hAAA;
smaCtrl = 32'hAAAAAAAA;
thisMesg = 32'hAAAAAAAA;
unrollCnt = 16'hAAAA;
valExpect = 128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wci_wslv_cEdge = 3'h2;
wci_wslv_cState = 3'h2;
wci_wslv_ctlAckReg = 1'h0;
wci_wslv_ctlOpActive = 1'h0;
wci_wslv_illegalEdge = 1'h0;
wci_wslv_isReset_isInReset = 1'h0;
wci_wslv_nState = 3'h2;
wci_wslv_reqF_countReg = 2'h2;
wci_wslv_respF_cntr_r = 2'h2;
wci_wslv_respF_q_0 = 34'h2AAAAAAAA;
wci_wslv_respF_q_1 = 34'h2AAAAAAAA;
wci_wslv_sFlagReg = 1'h0;
wci_wslv_sThreadBusy_d = 1'h0;
wmi_busyWithMessage = 1'h0;
wmi_dhF_cntr_r = 2'h2;
wmi_dhF_q_0 = 146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wmi_dhF_q_1 = 146'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wmi_errorSticky = 1'h0;
wmi_isReset_isInReset = 1'h0;
wmi_mFlagF_cntr_r = 2'h2;
wmi_mFlagF_q_0 = 32'hAAAAAAAA;
wmi_mFlagF_q_1 = 32'hAAAAAAAA;
wmi_operateD = 1'h0;
wmi_peerIsReady = 1'h0;
wmi_reqF_cntr_r = 2'h2;
wmi_reqF_q_0 = 32'hAAAAAAAA;
wmi_reqF_q_1 = 32'hAAAAAAAA;
wmi_sDataThreadBusy_d = 1'h0;
wmi_sFlagReg = 32'hAAAAAAAA;
wmi_sThreadBusy_d = 1'h0;
wmi_statusR = 8'hAA;
wmi_trafficSticky = 1'h0;
wmwtBeginCount = 32'hAAAAAAAA;
wmwtFinalCount = 32'hAAAAAAAA;
wmwtPushCount = 32'hAAAAAAAA;
wsiM_burstKind = 2'h2;
wsiM_errorSticky = 1'h0;
wsiM_iMesgCount = 32'hAAAAAAAA;
wsiM_isReset_isInReset = 1'h0;
wsiM_operateD = 1'h0;
wsiM_pMesgCount = 32'hAAAAAAAA;
wsiM_peerIsReady = 1'h0;
wsiM_reqFifo_cntr_r = 2'h2;
wsiM_reqFifo_q_0 = 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wsiM_reqFifo_q_1 = 169'h0AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
wsiM_sThreadBusy_d = 1'h0;
wsiM_statusR = 8'hAA;
wsiM_tBusyCount = 32'hAAAAAAAA;
wsiM_trafficSticky = 1'h0;
wsiS_burstKind = 2'h2;
wsiS_errorSticky = 1'h0;
wsiS_iMesgCount = 32'hAAAAAAAA;
wsiS_isReset_isInReset = 1'h0;
wsiS_mesgWordLength = 12'hAAA;
wsiS_operateD = 1'h0;
wsiS_pMesgCount = 32'hAAAAAAAA;
wsiS_peerIsReady = 1'h0;
wsiS_reqFifo_countReg = 2'h2;
wsiS_reqFifo_levelsValid = 1'h0;
wsiS_statusR = 8'hAA;
wsiS_tBusyCount = 32'hAAAAAAAA;
wsiS_trafficSticky = 1'h0;
wsiS_wordCount = 12'hAAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge wciS0_Clk)
begin
#0;
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
begin
v__h3597 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
$display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x",
v__h3597,
wci_wslv_reqF_D_OUT[36:34],
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (MUX_unrollCnt_write_1__SEL_1)
begin
v__h18073 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (MUX_unrollCnt_write_1__SEL_1)
$display("[%0d]: %m: wmrd_mesgBegin mesgCount:%0h mesgLength:%0h reqInfo:%0h",
v__h18073,
mesgCount,
wmi_sFlagReg[23:0],
wmi_sFlagReg[31:24]);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo_D_OUT[164])
begin
v__h22489 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wmwt_mesgBegin && wsiS_reqFifo_D_OUT[164])
$display("[%0d]: %m: mesgBegin PRECISE mesgCount:%0x WSI burstLength:%0x reqInfo:%0x",
v__h22489,
mesgCount,
wsiS_reqFifo_D_OUT[163:152],
wsiS_reqFifo_D_OUT[7:0]);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo_D_OUT[164])
begin
v__h22548 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wmwt_mesgBegin && !wsiS_reqFifo_D_OUT[164])
$display("[%0d]: %m: wmwt_mesgBegin IMPRECISE mesgCount:%0x",
v__h22548,
mesgCount);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wmwt_doAbort)
begin
v__h24386 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wmwt_doAbort)
$display("[%0d]: %m: wmwt_doAbort", v__h24386);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wmwt_messageFinalize)
begin
v__h24569 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wmwt_messageFinalize)
$display("[%0d]: %m: wmwt_messageFinalize mesgCount:%0x WSI mesgLength:%0x",
v__h24569,
mesgCount,
thisMesg[15:0]);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr)
begin
v__h24765 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr)
$display("[%0d]: %m: SMAdapter WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x",
v__h24765,
wci_wslv_reqF_D_OUT[63:32],
wci_wslv_reqF_D_OUT[67:64],
wci_wslv_reqF_D_OUT[31:0]);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO)
begin
v__h25422 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO)
$display("[%0d]: %m: Starting SMAdapter smaCtrl:%0x",
v__h25422,
smaCtrl);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd)
$display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/SMAdapter.bsv\", line 300, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
begin
v__h3916 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x",
v__h3916,
wci_wslv_cEdge,
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
begin
v__h3772 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x",
v__h3772,
wci_wslv_cEdge,
wci_wslv_cState,
wci_wslv_nState);
end
// synopsys translate_on
endmodule // mkSMAdapter16B
|
/*
* 専用レジスタ
* ゼロレジスタ
* アドレスレジスタ
* ベースレジスタ
* インデックスレジスタ
* スタックポインタ
* ベースポインタ
* データレジスタ
* 入力レジスタ
* 出力レジスタ
*/
module ZeroRegister (
input clock, write, reset,
input [3:0] address,
input [15:0] writeData,
output [15:0] data);
reg [15:0] out = 16'b0;
always @ (posedge clock) begin
out = 16'b0;
end
assign data = out;
endmodule
module AddressRegister (
input clock, write, reset,
input [3:0] address,
input [15:0] writeData,
output [15:0] data);
reg [15:0] out = 16'b0;
always @ (posedge clock) begin
if (reset)
out = 16'b0;
else if (write)
out = writeData;
end
assign data = out;
endmodule
module BaseRegister(
input clock, write, reset,
input [15:0] address,
input [15:0] writeData,
output [15:0] data);
reg [15:0] base [0:65535];
integer i;
initial begin
for (i = 0; i < 65536; i = i + 1)
base[i] = 16'b0;
end
always @ (posedge clock) begin
if (reset)
for (i = 0; i < 65536; i = i + 1)
base[i] = 16'b0;
else if (write)
base[address] = writeData;
end
assign data = base[address];
endmodule
module IndexRegister(
input clock, write, reset,
input [15:0] address,
input [15:0] writeData,
output [15:0] data);
reg [15:0] index [0:65535];
integer i;
initial begin
for (i = 0; i < 65536; i = i + 1)
index[i] = 16'b0;
end
always @ (posedge clock) begin
if (reset)
for (i = 0; i < 65536; i = i + 1)
index[i] = 16'b0;
else if (write)
index[address] = writeData;
end
assign data = index[address];
endmodule
module StackPointerRegister (
input clock, reset,
input [1:0] op,
input [15:0] writeData,
output [15:0] data);
reg [15:0] stackPointer;
always @ (posedge clock) begin
if (reset)
stackPointer = 16'b0;
else
case (op)
2'b00 : stackPointer = stackPointer + 1;
2'b01 : stackPointer = stackPointer - 1;
2'b10 : stackPointer = writeData;
2'b11 : stackPointer = stackPointer;
default : stackPointer = stackPointer;
endcase
end
assign data = stackPointer;
endmodule
module BasePointerRegister (
input clock, write, reset,
input [15:0] writeData,
output [15:0] data);
reg [15:0] basePointer;
always @ (posedge clock) begin
if (reset)
basePointer = 16'b0;
else if (write)
basePointer = writeData;
end
assign data = basePointer;
endmodule
module InputRegister (
input clock, write, reset,
input [15:0] writeData,
output [15:0] data);
reg [15:0] out = 16'b0;
always @ (posedge clock) begin
if (reset)
out = 16'b0;
else if (write)
out = writeData;
end
assign data = out;
endmodule
module OutputRegister (
input clock, write, reset,
input [15:0] writeData,
output [15:0] data);
reg [15:0] out = 16'b0;
always @ (posedge clock) begin
if (reset)
out = 16'b0;
else if (write)
out = writeData;
end
assign data = out;
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_clock_converter:2.1
// IP Revision: 10
(* X_CORE_INFO = "axi_clock_converter_v2_1_10_axi_clock_converter,Vivado 2016.4" *)
(* CHECK_LICENSE_TYPE = "mig_wrap_auto_cc_0,axi_clock_converter_v2_1_10_axi_clock_converter,{}" *)
(* CORE_GENERATION_INFO = "mig_wrap_auto_cc_0,axi_clock_converter_v2_1_10_axi_clock_converter,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_clock_converter,x_ipVersion=2.1,x_ipCoreRevision=10,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_AXI_ID_WIDTH=4,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=1,C_AXI_PROTOCOL=0,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=\
1,C_AXI_BUSER_WIDTH=1,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_SYNCHRONIZER_STAGE=3}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module mig_wrap_auto_cc_0 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_aclk,
m_axi_aresetn,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [3 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [3 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [3 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [3 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 MI_CLK CLK" *)
input wire m_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 MI_RST RST" *)
input wire m_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
output wire [3 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
input wire [3 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
output wire [3 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
input wire [3 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_clock_converter_v2_1_10_axi_clock_converter #(
.C_FAMILY("artix7"),
.C_AXI_ID_WIDTH(4),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(1),
.C_AXI_PROTOCOL(0),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(4'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_aclk(m_axi_aclk),
.m_axi_aresetn(m_axi_aresetn),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAPVGND_PP_SYMBOL_V
`define SKY130_FD_SC_LP__TAPVGND_PP_SYMBOL_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__tapvgnd (
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAPVGND_PP_SYMBOL_V
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
module c1_inputs(
input nCTRL1_ZONE,
input nCTRL2_ZONE,
input nSTATUSB_ZONE,
output [15:8] M68K_DATA,
input [9:0] P1_IN,
input [9:0] P2_IN,
input nWP, nCD2, nCD1,
input SYSTEM_MODE
);
// REG_P1CNT
assign M68K_DATA[15:8] = nCTRL1_ZONE ? 8'bzzzzzzzz : P1_IN[7:0];
// REG_P2CNT
assign M68K_DATA[15:8] = nCTRL2_ZONE ? 8'bzzzzzzzz : P2_IN[7:0];
// REG_STATUS_B
assign M68K_DATA[15:8] = nSTATUSB_ZONE ? 8'bzzzzzzzz : {SYSTEM_MODE, nWP, nCD2, nCD1, P2_IN[9:8], P1_IN[9:8]};
endmodule
|
/*
-----------------------------------------------------------------------------
General Sound
-----------------------------------------------------------------------------
18.08.2018 Reworked first verilog version
19.08.2018 Produce proper signed output
20.08.2018 Use external SDR/DDR RAM for page 2 and up
21.05.2020 Use external SDR/DDR RAM for all ROM/RAM
CPU: Z80 @ 28MHz
ROM: 32K
RAM: up to 4096KB
INT: 37.5KHz
#xxBB Command register - регистр команд, доступный для записи
#xxBB Status register - регистр состояния, доступный для чтения
bit 7 флаг данных
bit <6:1> Не определен
bit 0 флаг команд. Этот регистр позволяет определить состояние GS, в частности можно ли прочитать или записать очередной байт данных, или подать очередную команду, и т.п.
#xxB3 Data register - регистр данных, доступный для записи. В этот регистр Спектрум записывает данные, например, это могут быть аргументы команд.
#xxB3 Output register - регистр вывода, доступный для чтения. Из этого регистра Спектрум читает данные, идущие от GS
Внутренние порта:
#xx00 "расширенная память" - регистр доступный для записи
bit <3:0> переключают страницы по 32Kb, страница 0 - ПЗУ
bit <7:0> не используются
порты 1 - 5 "обеспечивают связь с SPECTRUM'ом"
#xx01 чтение команды General Sound'ом
bit <7:0> код команды
#xx02 чтение данных General Sound'ом
bit <7:0> данные
#xx03 запись данных General Sound'ом для SPECTRUM'a
bit <7:0> данные
#xx04 чтение слова состояния General Sound'ом
bit 0 флаг команд
bit 7 флаг данных
#xx05 сбрасывает бит D0 (флаг команд) слова состояния
порты 6 - 9 "регулировка громкости" в каналах 1 - 4
#xx06 "регулировка громкости" в канале 1
bit <5:0> громкость
bit <7:6> не используются
#xx07 "регулировка громкости" в канале 2
bit <5:0> громкость
bit <7:6> не используются
#xx08 "регулировка громкости" в канале 3
bit <5:0> громкость
bit <7:6> не используются
#xx09 "регулировка громкости" в канале 4
bit <5:0> громкость
bit <7:6> не используются
#xx0A устанавливает бит 7 слова состояния не равным биту 0 порта #xx00
#xx0B устанавливает бит 0 слова состояния равным биту 5 порта #xx06
Распределение памяти
#0000 - #3FFF - первые 16Kb ПЗУ
#4000 - #7FFF - первые 16Kb первой страницы ОЗУ
#8000 - #FFFF - листаемые страницы по 32Kb
страница 0 - ПЗУ,
страница 1 - первая страница ОЗУ
страницы 2... ОЗУ
Данные в каналы заносятся при чтении процессором ОЗУ по адресам #6000 - #7FFF автоматически.
*/
module gs
(
input RESET,
input CLK,
input CE_N,
input CE_P,
input A,
input [7:0] DI,
output [7:0] DO,
input CS_n,
input WR_n,
input RD_n,
output [20:0] MEM_ADDR,
output [7:0] MEM_DI,
input [7:0] MEM_DO,
output MEM_RD,
output MEM_WR,
input MEM_WAIT,
output [14:0] OUTL,
output [14:0] OUTR
);
parameter INT_DIV = 291;
// port #xxBB : #xxB3
assign DO = A ? {flag_data, 6'b111111, flag_cmd} : port_03;
// CPU
reg int_n;
wire cpu_m1_n;
wire cpu_mreq_n;
wire cpu_iorq_n;
wire cpu_rfsh_n;
wire cpu_rd_n;
wire cpu_wr_n;
wire [15:0] cpu_a_bus;
wire [7:0] cpu_do_bus;
T80pa cpu
(
.RESET_n(~RESET),
.CLK(CLK),
.CEN_n(CE_N),
.CEN_p(CE_P),
.INT_n(int_n),
.M1_n(cpu_m1_n),
.MREQ_n(cpu_mreq_n),
.RFSH_n(cpu_rfsh_n),
.IORQ_n(cpu_iorq_n),
.RD_n(cpu_rd_n),
.WR_n(cpu_wr_n),
.A(cpu_a_bus),
.DO(cpu_do_bus),
.DI(cpu_di_bus)
);
wire CE = CE_P;
reg WR_n_d;
reg RD_n_d;
wire RD = RD_n_d & ~RD_n;
wire WR = WR_n_d & ~WR_n;
always @(posedge CLK) begin
RD_n_d <= RD_n;
WR_n_d <= WR_n;
end
// INT#
always @(posedge CLK) begin
reg [9:0] cnt;
if (RESET) begin
cnt <= 0;
int_n <= 1;
end else if(CE) begin
cnt <= cnt + 1'b1;
if (cnt == INT_DIV) begin // 37.48kHz
cnt <= 0;
int_n <= 0;
end
end
if (~cpu_iorq_n & ~cpu_m1_n) int_n <= 1;
end
reg flag_data;
reg flag_cmd;
always @(posedge CLK) begin
if (~cpu_iorq_n & cpu_m1_n) begin
case(cpu_a_bus[3:0])
'h2: flag_data <= 0;
'h3: flag_data <= 1;
'h5: flag_cmd <= 0;
'hA: flag_data <= ~port_00[0];
'hB: flag_cmd <= port_09[5];
endcase
end
if (~CS_n) begin
if (~A & RD) flag_data <= 0;
if (~A & WR) flag_data <= 1;
if ( A & WR) flag_cmd <= 1;
end
end
reg [7:0] port_BB;
reg [7:0] port_B3;
always @(posedge CLK) begin
if (RESET) begin
port_BB <= 0;
port_B3 <= 0;
end
else if (~CS_n && WR) begin
if(A) port_BB <= DI;
else port_B3 <= DI;
end
end
reg [5:0] port_00;
reg [7:0] port_03;
reg signed [6:0] port_06, port_07, port_08, port_09;
reg signed [7:0] ch_a, ch_b, ch_c, ch_d;
always @(posedge CLK) begin
if (RESET) begin
port_00 <= 0;
port_03 <= 0;
end
else begin
if (~cpu_iorq_n & ~cpu_wr_n) begin
case(cpu_a_bus[3:0])
0: port_00 <= cpu_do_bus[5:0];
3: port_03 <= cpu_do_bus;
6: port_06 <= cpu_do_bus[5:0];
7: port_07 <= cpu_do_bus[5:0];
8: port_08 <= cpu_do_bus[5:0];
9: port_09 <= cpu_do_bus[5:0];
endcase
end
if (mem_rd && cpu_a_bus[15:13] == 3 && ~MEM_WAIT) begin
case(cpu_a_bus[9:8])
0: ch_a <= {~MEM_DO[7],MEM_DO[6:0]};
1: ch_b <= {~MEM_DO[7],MEM_DO[6:0]};
2: ch_c <= {~MEM_DO[7],MEM_DO[6:0]};
3: ch_d <= {~MEM_DO[7],MEM_DO[6:0]};
endcase
end
end
end
wire [7:0] cpu_di_bus =
mem_rd ? MEM_DO :
(~cpu_iorq_n && ~cpu_rd_n && cpu_a_bus[3:0] == 1) ? port_BB :
(~cpu_iorq_n && ~cpu_rd_n && cpu_a_bus[3:0] == 2) ? port_B3 :
(~cpu_iorq_n && ~cpu_rd_n && cpu_a_bus[3:0] == 4) ? {flag_data, 6'b111111, flag_cmd} :
8'hFF;
wire mem_wr = ~cpu_wr_n & ~cpu_mreq_n & |page_addr;
wire mem_rd = ~cpu_rd_n & ~cpu_mreq_n;
wire [5:0] page_addr = cpu_a_bus[15] ? port_00 : cpu_a_bus[14];
assign MEM_ADDR = {page_addr, &cpu_a_bus[15:14], cpu_a_bus[13:0]};
assign MEM_RD = mem_rd;
assign MEM_WR = mem_wr;
assign MEM_DI = cpu_do_bus;
reg signed [14:0] out_a,out_b,out_c,out_d;
always @(posedge CLK) begin
if(CE) begin
out_a <= ch_a * port_06;
out_b <= ch_b * port_07;
out_c <= ch_c * port_08;
out_d <= ch_d * port_09;
end
end
reg signed [14:0] outl, outr;
always @(posedge CLK) begin
if(CE) begin
outl <= out_a + out_b;
outr <= out_c + out_d;
end
end
assign OUTL = outl;
assign OUTR = outr;
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 17:15:04 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W16 ( add_sub, in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
input add_sub;
wire n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46,
n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60,
n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74,
n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88,
n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100, n101,
n102, n103, n104, n105, n106, n107, n108, n109, n110;
NAND2XLTS U51 ( .A(n33), .B(n87), .Y(n89) );
XOR2X1TS U52 ( .A(n62), .B(in2[11]), .Y(n94) );
NAND2X1TS U53 ( .A(n71), .B(in1[13]), .Y(n87) );
NAND2X1TS U54 ( .A(n74), .B(n36), .Y(n58) );
NAND2BX1TS U55 ( .AN(in2[13]), .B(n59), .Y(n74) );
NAND2X1TS U56 ( .A(n67), .B(n36), .Y(n68) );
CMPR32X2TS U57 ( .A(n100), .B(in1[6]), .C(n99), .CO(n55), .S(res[6]) );
OR2X2TS U58 ( .A(n51), .B(n35), .Y(n34) );
INVX4TS U59 ( .A(n35), .Y(n36) );
NOR2X4TS U60 ( .A(n53), .B(in2[8]), .Y(n57) );
INVX4TS U61 ( .A(add_sub), .Y(n35) );
CLKINVX6TS U62 ( .A(in2[1]), .Y(n44) );
CLKINVX6TS U63 ( .A(in2[3]), .Y(n42) );
CLKINVX6TS U64 ( .A(in2[0]), .Y(n43) );
INVX8TS U65 ( .A(in2[2]), .Y(n41) );
NAND2BX2TS U66 ( .AN(in2[11]), .B(n61), .Y(n67) );
NOR2XLTS U67 ( .A(n61), .B(n35), .Y(n62) );
INVX2TS U68 ( .A(n78), .Y(n77) );
NOR2X4TS U69 ( .A(n67), .B(in2[12]), .Y(n59) );
NOR2X4TS U70 ( .A(n65), .B(in2[10]), .Y(n61) );
AO21X2TS U71 ( .A0(n33), .A1(n70), .B0(n72), .Y(n37) );
NAND2X2TS U72 ( .A(n76), .B(in1[15]), .Y(n78) );
XNOR2X2TS U73 ( .A(n58), .B(in2[14]), .Y(n73) );
NOR2X2TS U74 ( .A(n59), .B(n35), .Y(n60) );
ADDFHX2TS U75 ( .A(n56), .B(in1[7]), .CI(n55), .CO(n97), .S(res[7]) );
OAI31X1TS U76 ( .A0(in2[2]), .A1(in2[1]), .A2(in2[0]), .B0(n36), .Y(n106) );
NAND2X2TS U77 ( .A(n83), .B(n82), .Y(n85) );
NOR2X2TS U78 ( .A(n73), .B(in1[14]), .Y(n81) );
NAND2X2TS U79 ( .A(n73), .B(in1[14]), .Y(n82) );
NOR2X2TS U80 ( .A(n39), .B(n86), .Y(n38) );
INVX2TS U81 ( .A(n86), .Y(n33) );
NAND2X2TS U82 ( .A(n69), .B(in1[12]), .Y(n90) );
OR2X2TS U83 ( .A(n69), .B(in1[12]), .Y(n46) );
XNOR2X2TS U84 ( .A(n68), .B(in2[12]), .Y(n69) );
NOR2BX2TS U85 ( .AN(in1[5]), .B(n110), .Y(n99) );
NAND2BXLTS U86 ( .AN(in1[5]), .B(n110), .Y(res[5]) );
XNOR2X2TS U87 ( .A(n50), .B(in2[5]), .Y(n110) );
NAND2BXLTS U88 ( .AN(in1[4]), .B(n109), .Y(res[4]) );
OAI21XLTS U89 ( .A0(in2[1]), .A1(n102), .B0(n101), .Y(res[1]) );
OAI21XLTS U90 ( .A0(in2[2]), .A1(n104), .B0(n103), .Y(res[2]) );
OAI21XLTS U91 ( .A0(in2[3]), .A1(n106), .B0(n105), .Y(res[3]) );
XOR2X1TS U92 ( .A(n108), .B(in2[4]), .Y(n109) );
OR2X1TS U93 ( .A(in2[0]), .B(in1[0]), .Y(res[0]) );
XNOR2X1TS U94 ( .A(n34), .B(in2[7]), .Y(n56) );
OAI21X1TS U95 ( .A0(n74), .A1(in2[14]), .B0(n36), .Y(n75) );
AO21X2TS U96 ( .A0(n79), .A1(n45), .B0(n77), .Y(res[16]) );
NAND2X2TS U97 ( .A(n45), .B(n78), .Y(n80) );
OR2X2TS U98 ( .A(n76), .B(in1[15]), .Y(n45) );
NOR2X2TS U99 ( .A(n49), .B(n35), .Y(n50) );
AFHCONX4TS U100 ( .A(in1[10]), .B(n95), .CI(n96), .CON(n93), .S(res[10]) );
AOI21X4TS U101 ( .A0(n91), .A1(n38), .B0(n37), .Y(n84) );
XNOR2X1TS U102 ( .A(n79), .B(n80), .Y(res[15]) );
OAI21X4TS U103 ( .A0(n84), .A1(n81), .B0(n82), .Y(n79) );
XNOR2X2TS U104 ( .A(n75), .B(in2[15]), .Y(n76) );
AFHCONX4TS U105 ( .A(in1[8]), .B(n98), .CI(n97), .CON(n63), .S(res[8]) );
AFHCINX4TS U106 ( .CIN(n63), .B(n64), .A(in1[9]), .S(res[9]), .CO(n96) );
NOR2X8TS U107 ( .A(n47), .B(in2[6]), .Y(n51) );
NAND2X4TS U108 ( .A(n47), .B(add_sub), .Y(n48) );
NAND2X8TS U109 ( .A(n49), .B(n40), .Y(n47) );
AFHCINX4TS U110 ( .CIN(n93), .B(n94), .A(in1[11]), .S(res[11]), .CO(n91) );
NOR2X8TS U111 ( .A(n107), .B(in2[4]), .Y(n49) );
XOR2X4TS U112 ( .A(n60), .B(in2[13]), .Y(n71) );
NAND2BX4TS U113 ( .AN(in2[7]), .B(n51), .Y(n53) );
NAND2BX4TS U114 ( .AN(in2[9]), .B(n57), .Y(n65) );
INVX2TS U115 ( .A(in2[5]), .Y(n40) );
NOR2X2TS U116 ( .A(n71), .B(in1[13]), .Y(n86) );
INVX2TS U117 ( .A(n90), .Y(n70) );
INVX2TS U118 ( .A(n46), .Y(n39) );
XNOR2X1TS U119 ( .A(n48), .B(in2[6]), .Y(n100) );
XNOR2X1TS U120 ( .A(n54), .B(in2[8]), .Y(n98) );
NAND2X1TS U121 ( .A(n53), .B(n36), .Y(n54) );
XOR2X1TS U122 ( .A(n52), .B(in2[9]), .Y(n64) );
NOR2X1TS U123 ( .A(n57), .B(n35), .Y(n52) );
XNOR2X1TS U124 ( .A(n92), .B(n91), .Y(res[12]) );
NAND2X1TS U125 ( .A(n46), .B(n90), .Y(n92) );
XOR2X1TS U126 ( .A(n89), .B(n88), .Y(res[13]) );
AOI21X1TS U127 ( .A0(n91), .A1(n46), .B0(n70), .Y(n88) );
XOR2X1TS U128 ( .A(n85), .B(n84), .Y(res[14]) );
INVX2TS U129 ( .A(n81), .Y(n83) );
NAND4X8TS U130 ( .A(n44), .B(n43), .C(n42), .D(n41), .Y(n107) );
INVX2TS U131 ( .A(n87), .Y(n72) );
NAND2X1TS U132 ( .A(n65), .B(n36), .Y(n66) );
XNOR2X1TS U133 ( .A(n66), .B(in2[10]), .Y(n95) );
NAND2X1TS U134 ( .A(in2[0]), .B(n36), .Y(n102) );
AOI21X1TS U135 ( .A0(in2[1]), .A1(n102), .B0(in1[1]), .Y(n101) );
OAI21X1TS U136 ( .A0(in2[1]), .A1(in2[0]), .B0(n36), .Y(n104) );
AOI21X1TS U137 ( .A0(in2[2]), .A1(n104), .B0(in1[2]), .Y(n103) );
AOI21X1TS U138 ( .A0(in2[3]), .A1(n106), .B0(in1[3]), .Y(n105) );
NAND2X1TS U139 ( .A(n107), .B(n36), .Y(n108) );
initial $sdf_annotate("Approx_adder_LOALPL6_syn.sdf");
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYMETAL6S4S_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__DLYMETAL6S4S_FUNCTIONAL_PP_V
/**
* dlymetal6s4s: 6-inverter delay with output from 4th inverter on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__dlymetal6s4s (
VPWR,
VGND,
X ,
A
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYMETAL6S4S_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4_SYMBOL_V
`define SKY130_FD_SC_HD__NOR4_SYMBOL_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__nor4 (
//# {{data|Data Signals}}
input A,
input B,
input C,
input D,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4_SYMBOL_V
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module image_filter_SubS (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
src_rows_V_read,
src_cols_V_read,
src_data_stream_0_V_dout,
src_data_stream_0_V_empty_n,
src_data_stream_0_V_read,
src_data_stream_1_V_dout,
src_data_stream_1_V_empty_n,
src_data_stream_1_V_read,
src_data_stream_2_V_dout,
src_data_stream_2_V_empty_n,
src_data_stream_2_V_read,
dst_rows_V_read,
dst_cols_V_read,
dst_data_stream_0_V_din,
dst_data_stream_0_V_full_n,
dst_data_stream_0_V_write,
dst_data_stream_1_V_din,
dst_data_stream_1_V_full_n,
dst_data_stream_1_V_write,
dst_data_stream_2_V_din,
dst_data_stream_2_V_full_n,
dst_data_stream_2_V_write
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 2'b1;
parameter ap_ST_st2_fsm_1 = 2'b10;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_true = 1'b1;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [11:0] src_rows_V_read;
input [11:0] src_cols_V_read;
input [7:0] src_data_stream_0_V_dout;
input src_data_stream_0_V_empty_n;
output src_data_stream_0_V_read;
input [7:0] src_data_stream_1_V_dout;
input src_data_stream_1_V_empty_n;
output src_data_stream_1_V_read;
input [7:0] src_data_stream_2_V_dout;
input src_data_stream_2_V_empty_n;
output src_data_stream_2_V_read;
input [11:0] dst_rows_V_read;
input [11:0] dst_cols_V_read;
output [7:0] dst_data_stream_0_V_din;
input dst_data_stream_0_V_full_n;
output dst_data_stream_0_V_write;
output [7:0] dst_data_stream_1_V_din;
input dst_data_stream_1_V_full_n;
output dst_data_stream_1_V_write;
output [7:0] dst_data_stream_2_V_din;
input dst_data_stream_2_V_full_n;
output dst_data_stream_2_V_write;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg src_data_stream_0_V_read;
reg src_data_stream_1_V_read;
reg src_data_stream_2_V_read;
reg dst_data_stream_0_V_write;
reg dst_data_stream_1_V_write;
reg dst_data_stream_2_V_write;
reg ap_done_reg = 1'b0;
(* fsm_encoding = "none" *) reg [1:0] ap_CS_fsm = 2'b1;
reg ap_sig_cseq_ST_st1_fsm_0;
reg ap_sig_bdd_21;
reg ap_sig_bdd_61;
wire grp_image_filter_arithm_pro_1_fu_77_ap_start;
wire grp_image_filter_arithm_pro_1_fu_77_ap_done;
wire grp_image_filter_arithm_pro_1_fu_77_ap_idle;
wire grp_image_filter_arithm_pro_1_fu_77_ap_ready;
wire [7:0] grp_image_filter_arithm_pro_1_fu_77_src_data_stream_0_V_dout;
wire grp_image_filter_arithm_pro_1_fu_77_src_data_stream_0_V_empty_n;
wire grp_image_filter_arithm_pro_1_fu_77_src_data_stream_0_V_read;
wire [7:0] grp_image_filter_arithm_pro_1_fu_77_src_data_stream_1_V_dout;
wire grp_image_filter_arithm_pro_1_fu_77_src_data_stream_1_V_empty_n;
wire grp_image_filter_arithm_pro_1_fu_77_src_data_stream_1_V_read;
wire [7:0] grp_image_filter_arithm_pro_1_fu_77_src_data_stream_2_V_dout;
wire grp_image_filter_arithm_pro_1_fu_77_src_data_stream_2_V_empty_n;
wire grp_image_filter_arithm_pro_1_fu_77_src_data_stream_2_V_read;
wire [11:0] grp_image_filter_arithm_pro_1_fu_77_dst_rows_V_read;
wire [11:0] grp_image_filter_arithm_pro_1_fu_77_dst_cols_V_read;
wire [7:0] grp_image_filter_arithm_pro_1_fu_77_dst_data_stream_0_V_din;
wire grp_image_filter_arithm_pro_1_fu_77_dst_data_stream_0_V_full_n;
wire grp_image_filter_arithm_pro_1_fu_77_dst_data_stream_0_V_write;
wire [7:0] grp_image_filter_arithm_pro_1_fu_77_dst_data_stream_1_V_din;
wire grp_image_filter_arithm_pro_1_fu_77_dst_data_stream_1_V_full_n;
wire grp_image_filter_arithm_pro_1_fu_77_dst_data_stream_1_V_write;
wire [7:0] grp_image_filter_arithm_pro_1_fu_77_dst_data_stream_2_V_din;
wire grp_image_filter_arithm_pro_1_fu_77_dst_data_stream_2_V_full_n;
wire grp_image_filter_arithm_pro_1_fu_77_dst_data_stream_2_V_write;
reg grp_image_filter_arithm_pro_1_fu_77_ap_start_ap_start_reg = 1'b0;
reg ap_sig_cseq_ST_st2_fsm_1;
reg ap_sig_bdd_99;
reg [1:0] ap_NS_fsm;
image_filter_arithm_pro_1 grp_image_filter_arithm_pro_1_fu_77(
.ap_clk( ap_clk ),
.ap_rst( ap_rst ),
.ap_start( grp_image_filter_arithm_pro_1_fu_77_ap_start ),
.ap_done( grp_image_filter_arithm_pro_1_fu_77_ap_done ),
.ap_idle( grp_image_filter_arithm_pro_1_fu_77_ap_idle ),
.ap_ready( grp_image_filter_arithm_pro_1_fu_77_ap_ready ),
.src_data_stream_0_V_dout( grp_image_filter_arithm_pro_1_fu_77_src_data_stream_0_V_dout ),
.src_data_stream_0_V_empty_n( grp_image_filter_arithm_pro_1_fu_77_src_data_stream_0_V_empty_n ),
.src_data_stream_0_V_read( grp_image_filter_arithm_pro_1_fu_77_src_data_stream_0_V_read ),
.src_data_stream_1_V_dout( grp_image_filter_arithm_pro_1_fu_77_src_data_stream_1_V_dout ),
.src_data_stream_1_V_empty_n( grp_image_filter_arithm_pro_1_fu_77_src_data_stream_1_V_empty_n ),
.src_data_stream_1_V_read( grp_image_filter_arithm_pro_1_fu_77_src_data_stream_1_V_read ),
.src_data_stream_2_V_dout( grp_image_filter_arithm_pro_1_fu_77_src_data_stream_2_V_dout ),
.src_data_stream_2_V_empty_n( grp_image_filter_arithm_pro_1_fu_77_src_data_stream_2_V_empty_n ),
.src_data_stream_2_V_read( grp_image_filter_arithm_pro_1_fu_77_src_data_stream_2_V_read ),
.dst_rows_V_read( grp_image_filter_arithm_pro_1_fu_77_dst_rows_V_read ),
.dst_cols_V_read( grp_image_filter_arithm_pro_1_fu_77_dst_cols_V_read ),
.dst_data_stream_0_V_din( grp_image_filter_arithm_pro_1_fu_77_dst_data_stream_0_V_din ),
.dst_data_stream_0_V_full_n( grp_image_filter_arithm_pro_1_fu_77_dst_data_stream_0_V_full_n ),
.dst_data_stream_0_V_write( grp_image_filter_arithm_pro_1_fu_77_dst_data_stream_0_V_write ),
.dst_data_stream_1_V_din( grp_image_filter_arithm_pro_1_fu_77_dst_data_stream_1_V_din ),
.dst_data_stream_1_V_full_n( grp_image_filter_arithm_pro_1_fu_77_dst_data_stream_1_V_full_n ),
.dst_data_stream_1_V_write( grp_image_filter_arithm_pro_1_fu_77_dst_data_stream_1_V_write ),
.dst_data_stream_2_V_din( grp_image_filter_arithm_pro_1_fu_77_dst_data_stream_2_V_din ),
.dst_data_stream_2_V_full_n( grp_image_filter_arithm_pro_1_fu_77_dst_data_stream_2_V_full_n ),
.dst_data_stream_2_V_write( grp_image_filter_arithm_pro_1_fu_77_dst_data_stream_2_V_write )
);
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_done_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_done_reg
if (ap_rst == 1'b1) begin
ap_done_reg <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_continue)) begin
ap_done_reg <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(ap_const_logic_0 == grp_image_filter_arithm_pro_1_fu_77_ap_done))) begin
ap_done_reg <= ap_const_logic_1;
end
end
end
/// grp_image_filter_arithm_pro_1_fu_77_ap_start_ap_start_reg assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_grp_image_filter_arithm_pro_1_fu_77_ap_start_ap_start_reg
if (ap_rst == 1'b1) begin
grp_image_filter_arithm_pro_1_fu_77_ap_start_ap_start_reg <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~ap_sig_bdd_61)) begin
grp_image_filter_arithm_pro_1_fu_77_ap_start_ap_start_reg <= ap_const_logic_1;
end else if ((ap_const_logic_1 == grp_image_filter_arithm_pro_1_fu_77_ap_ready)) begin
grp_image_filter_arithm_pro_1_fu_77_ap_start_ap_start_reg <= ap_const_logic_0;
end
end
end
/// ap_done assign process. ///
always @ (ap_done_reg or grp_image_filter_arithm_pro_1_fu_77_ap_done or ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 == ap_done_reg) | ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(ap_const_logic_0 == grp_image_filter_arithm_pro_1_fu_77_ap_done)))) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (grp_image_filter_arithm_pro_1_fu_77_ap_done or ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~(ap_const_logic_0 == grp_image_filter_arithm_pro_1_fu_77_ap_done))) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st1_fsm_0 assign process. ///
always @ (ap_sig_bdd_21)
begin
if (ap_sig_bdd_21) begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st2_fsm_1 assign process. ///
always @ (ap_sig_bdd_99)
begin
if (ap_sig_bdd_99) begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_0;
end
end
/// dst_data_stream_0_V_write assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or grp_image_filter_arithm_pro_1_fu_77_dst_data_stream_0_V_write or ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) | (ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1))) begin
dst_data_stream_0_V_write = grp_image_filter_arithm_pro_1_fu_77_dst_data_stream_0_V_write;
end else begin
dst_data_stream_0_V_write = ap_const_logic_0;
end
end
/// dst_data_stream_1_V_write assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or grp_image_filter_arithm_pro_1_fu_77_dst_data_stream_1_V_write or ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) | (ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1))) begin
dst_data_stream_1_V_write = grp_image_filter_arithm_pro_1_fu_77_dst_data_stream_1_V_write;
end else begin
dst_data_stream_1_V_write = ap_const_logic_0;
end
end
/// dst_data_stream_2_V_write assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or grp_image_filter_arithm_pro_1_fu_77_dst_data_stream_2_V_write or ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) | (ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1))) begin
dst_data_stream_2_V_write = grp_image_filter_arithm_pro_1_fu_77_dst_data_stream_2_V_write;
end else begin
dst_data_stream_2_V_write = ap_const_logic_0;
end
end
/// src_data_stream_0_V_read assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or grp_image_filter_arithm_pro_1_fu_77_src_data_stream_0_V_read or ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) | (ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1))) begin
src_data_stream_0_V_read = grp_image_filter_arithm_pro_1_fu_77_src_data_stream_0_V_read;
end else begin
src_data_stream_0_V_read = ap_const_logic_0;
end
end
/// src_data_stream_1_V_read assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or grp_image_filter_arithm_pro_1_fu_77_src_data_stream_1_V_read or ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) | (ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1))) begin
src_data_stream_1_V_read = grp_image_filter_arithm_pro_1_fu_77_src_data_stream_1_V_read;
end else begin
src_data_stream_1_V_read = ap_const_logic_0;
end
end
/// src_data_stream_2_V_read assign process. ///
always @ (ap_sig_cseq_ST_st1_fsm_0 or grp_image_filter_arithm_pro_1_fu_77_src_data_stream_2_V_read or ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) | (ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1))) begin
src_data_stream_2_V_read = grp_image_filter_arithm_pro_1_fu_77_src_data_stream_2_V_read;
end else begin
src_data_stream_2_V_read = ap_const_logic_0;
end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_CS_fsm or ap_sig_bdd_61 or grp_image_filter_arithm_pro_1_fu_77_ap_done)
begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
begin
if (~ap_sig_bdd_61) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
end
ap_ST_st2_fsm_1 :
begin
if (~(ap_const_logic_0 == grp_image_filter_arithm_pro_1_fu_77_ap_done)) begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end else begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end
end
default :
begin
ap_NS_fsm = 'bx;
end
endcase
end
/// ap_sig_bdd_21 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_21 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end
/// ap_sig_bdd_61 assign process. ///
always @ (ap_start or ap_done_reg)
begin
ap_sig_bdd_61 = ((ap_start == ap_const_logic_0) | (ap_done_reg == ap_const_logic_1));
end
/// ap_sig_bdd_99 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_99 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1]);
end
assign dst_data_stream_0_V_din = grp_image_filter_arithm_pro_1_fu_77_dst_data_stream_0_V_din;
assign dst_data_stream_1_V_din = grp_image_filter_arithm_pro_1_fu_77_dst_data_stream_1_V_din;
assign dst_data_stream_2_V_din = grp_image_filter_arithm_pro_1_fu_77_dst_data_stream_2_V_din;
assign grp_image_filter_arithm_pro_1_fu_77_ap_start = grp_image_filter_arithm_pro_1_fu_77_ap_start_ap_start_reg;
assign grp_image_filter_arithm_pro_1_fu_77_dst_cols_V_read = dst_cols_V_read;
assign grp_image_filter_arithm_pro_1_fu_77_dst_data_stream_0_V_full_n = dst_data_stream_0_V_full_n;
assign grp_image_filter_arithm_pro_1_fu_77_dst_data_stream_1_V_full_n = dst_data_stream_1_V_full_n;
assign grp_image_filter_arithm_pro_1_fu_77_dst_data_stream_2_V_full_n = dst_data_stream_2_V_full_n;
assign grp_image_filter_arithm_pro_1_fu_77_dst_rows_V_read = dst_rows_V_read;
assign grp_image_filter_arithm_pro_1_fu_77_src_data_stream_0_V_dout = src_data_stream_0_V_dout;
assign grp_image_filter_arithm_pro_1_fu_77_src_data_stream_0_V_empty_n = src_data_stream_0_V_empty_n;
assign grp_image_filter_arithm_pro_1_fu_77_src_data_stream_1_V_dout = src_data_stream_1_V_dout;
assign grp_image_filter_arithm_pro_1_fu_77_src_data_stream_1_V_empty_n = src_data_stream_1_V_empty_n;
assign grp_image_filter_arithm_pro_1_fu_77_src_data_stream_2_V_dout = src_data_stream_2_V_dout;
assign grp_image_filter_arithm_pro_1_fu_77_src_data_stream_2_V_empty_n = src_data_stream_2_V_empty_n;
endmodule //image_filter_SubS
|
/**
* testbench.v
*
*/
module testbench();
localparam width_p = 32;
localparam ring_width_p = width_p*2 + 1;
localparam rom_addr_width_p = 32;
logic clk;
logic reset;
bsg_nonsynth_clock_gen #(
.cycle_time_p(10)
) clock_gen (
.o(clk)
);
bsg_nonsynth_reset_gen #(
.reset_cycles_lo_p(4)
,.reset_cycles_hi_p(4)
) reset_gen (
.clk_i(clk)
,.async_reset_o(reset)
);
logic v_li;
logic [width_p-1:0] a_li;
logic [width_p-1:0] b_li;
logic sub_li;
logic ready_lo;
logic v_lo;
logic yumi_li;
logic [width_p-1:0] z_lo;
logic unimplemented;
logic invalid;
logic overflow;
logic underflow;
bsg_fpu_add_sub #(
.e_p(8)
,.m_p(23)
) dut (
.clk_i(clk)
,.reset_i(reset)
,.en_i(1'b1)
,.v_i(v_li)
,.a_i(a_li)
,.b_i(b_li)
,.sub_i(sub_li)
,.ready_o(ready_lo)
,.v_o(v_lo)
,.z_o(z_lo)
,.yumi_i(yumi_li)
,.unimplemented_o(unimplemented)
,.invalid_o(invalid)
,.overflow_o(overflow)
,.underflow_o(underflow)
);
logic [ring_width_p-1:0] tr_data_li;
logic tr_ready_lo;
logic tr_v_lo;
logic [ring_width_p-1:0] tr_data_lo;
logic tr_yumi_li;
logic [rom_addr_width_p-1:0] rom_addr;
logic [ring_width_p+4-1:0] rom_data;
logic done_lo;
bsg_fsb_node_trace_replay #(
.ring_width_p(ring_width_p)
,.rom_addr_width_p(rom_addr_width_p)
) tr (
.clk_i(clk)
,.reset_i(reset)
,.en_i(1'b1)
,.v_i(v_lo)
,.data_i(tr_data_li)
,.ready_o(tr_ready_lo)
,.v_o(v_li)
,.data_o(tr_data_lo)
,.yumi_i(tr_yumi_li)
,.rom_addr_o(rom_addr)
,.rom_data_i(rom_data)
,.done_o(done_lo)
,.error_o()
);
bsg_fpu_trace_rom #(
.width_p(ring_width_p+4)
,.addr_width_p(rom_addr_width_p)
) rom (
.addr_i(rom_addr)
,.data_o(rom_data)
);
assign yumi_li = v_lo & tr_ready_lo;
assign tr_yumi_li = v_li & ready_lo;
assign {sub_li, a_li, b_li} = tr_data_lo;
assign tr_data_li = {
{ring_width_p-width_p-4{1'b0}},
unimplemented,
invalid,
overflow,
underflow,
z_lo
};
initial begin
wait(done_lo);
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21BO_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__A21BO_FUNCTIONAL_PP_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a21bo (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out_X , B1_N, nand0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nand1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21BO_FUNCTIONAL_PP_V |
module alu (a_input, b_input, funct, res, z);
// input
input [31:0] a_input;
input [31:0] b_input;
input [4:0] funct;
// output
output [31:0] res;
output z;
// reg
reg [31:0] res = 0;
reg z = 0;
reg [31:0] hi = 0;
reg [31:0] lo = 0;
// combinational logic but easier to understand format
always @(a_input or b_input or funct)
begin
if (funct == 'b00000)
begin
// sll
res = a_input << b_input;
z = 0;
$display("%d = %d << %d", $signed(res), $signed(a_input), $signed(b_input));
end
else if (funct == 'b00001)
begin
// srl
res = a_input >> b_input;
z = 0;
$display("%d = %d >> %d", $signed(res), $signed(a_input), $signed(b_input));
end
else if (funct == 'b00010)
begin
// sra
res = $signed(a_input) >>> $signed(b_input);
z = 0;
$display("%d = %d >>> %d", $signed(res), $signed(a_input), $signed(b_input));
end
else if (funct == 'b00011)
begin
// mfhi
res = hi;
z = 0;
$display("HI = %d", res);
end
else if (funct == 'b00100)
begin
// mflo
res = lo;
z = 0;
$display("LO = %d", res);
end
else if (funct == 'b00101)
begin
// mul
res = ($signed(a_input) * $signed(b_input));
z = 0;
$display("%d = %d * %d", $signed(res), $signed(a_input), $signed(b_input));
end
else if (funct == 'b00110)
begin
// div
lo = ($signed(a_input) / $signed(b_input));
hi = ($signed(a_input) % $signed(b_input));
$display("%d = %d / %d", $signed(lo), $signed(a_input), $signed(b_input));
z = 0;
end
else if (funct == 'b00111)
begin
// divu
hi = ($unsigned(a_input) / $unsigned(b_input));
lo = ($unsigned(a_input) % $unsigned(b_input));
z = 0;
end
else if (funct == 'b01000)
begin
// add rd, rs, rt
res = $signed(a_input) + $signed(b_input);
z = 0;
$display("%d = %d + %d", $signed(res), $signed(a_input), $signed(b_input));
end
else if (funct == 'b01001)
begin
// addu rd, rs, rt
res = a_input + b_input;
z = 0;
$display("%d = u%d + u%d", $signed(res), $signed(a_input), $signed(b_input));
end
else if (funct == 'b01010)
begin
// sub rd, rs, rt
res = $signed(a_input) - $signed(b_input);
z = 0;
$display("%d = %d - %d", $signed(res), $signed(a_input), $signed(b_input));
end
else if (funct == 'b01011)
begin
// subu rd, rs, rt
res = a_input - b_input;
z = 0;
$display("%d = u%d - u%d", $signed(res), $signed(a_input), $signed(b_input));
end
else if (funct == 'b01100)
begin
// and rd, rs, rt
res = a_input & b_input;
z = 0;
$display("%d = %d & %d", $signed(res), $signed(a_input), $signed(b_input));
end
else if (funct == 'b01101)
begin
// or rd, rs, rt
res = a_input | b_input;
z = 0;
$display("%d = %d | %d", $signed(res), $signed(a_input), $signed(b_input));
end
else if (funct == 'b01110)
begin
// xor rd, rs, rt
res = a_input ^ b_input;
z = 0;
$display("%d = %d ^ %d", $signed(res), $signed(a_input), $signed(b_input));
end
else if (funct == 'b01111)
begin
// nor rd, rs, rt
res = ~(a_input | b_input);
z = 0;
$display("%d = ~(%d | %d)", $signed(res), $signed(a_input), $signed(b_input));
end
else if (funct == 'b10000)
begin
// slt rd, rs, rt
res = $signed(a_input) < $signed(b_input) ? 1 : 0;
z = 0;
$display("%d = (%d < %d)", $signed(res), $signed(a_input), $signed(b_input));
end
else if (funct == 'b10001)
begin
// sltu rd, rs, rt
res = a_input < b_input ? 1 : 0;
z = 0;
$display("%d = u%d < u%d", $signed(res), $signed(a_input), $signed(b_input));
end
else if (funct == 'b10010)
begin
// lui
res = b_input << 16;
z = 0;
$display("%d = %d << 16", $signed(res), $signed(b_input));
end
else if (funct == 'b10011)
begin
// beq rd, rs, rt
z = a_input == b_input ? 1 : 0;
res = 0;
$display("%d = %d == %d", z, $signed(a_input), $signed(b_input));
end
else if (funct == 'b10100)
begin
// blt rd, rs, rt
z = $signed(a_input) < $signed(b_input) ? 1 : 0;
res = 0;
$display("%d = %d < %d", z, $signed(a_input), $signed(b_input));
end
else if (funct == 'b10101)
begin
// bne rd, rs, rt
z = a_input != b_input ? 1 : 0;
res = 0;
$display("%d = %d != %d", z, $signed(a_input), $signed(b_input));
end
else if (funct == 'b10110)
begin
// bleq rd, rs, rt
z = $signed(a_input) <= $signed(b_input) ? 1 : 0;
res = 0;
$display("%d = %d <= %d", z, $signed(a_input), $signed(b_input));
end
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUF_FUNCTIONAL_V
`define SKY130_FD_SC_LP__LSBUF_FUNCTIONAL_V
/**
* lsbuf: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__lsbuf (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
wire destpwr ;
wire vgnd ;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (X , buf0_out_X, destpwr, vgnd);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUF_FUNCTIONAL_V |
// ################################################################
// $Header: /var/lib/cvs/dncvs/FPGA/dini/pcie/pcie_dma/user_fpga/pcie_interface.v,v 1.57 2015/03/17 18:15:46 bpoladian Exp $
// ################################################################
// Description:
// This module translates between the internal bus for NMB/PCIe Design
// and an easy-to-understand Target/DMA interface for the user.
// ################################################################
// $Log: pcie_interface.v,v $
// Revision 1.57 2015/03/17 18:15:46 bpoladian
// Added simulation checks for demand-mode DMA byte enables and addressing.
//
// Revision 1.56 2015/03/12 19:37:14 bpoladian
// Use bit 0 of target_read_ctrl for BE logic.
//
// Revision 1.55 2015/03/12 19:35:32 bpoladian
// Use last_be for upper 32 bits of a 64-bit read.
//
// Revision 1.54 2014/09/09 20:15:01 neal
// Removed some debug registers.
//
// Revision 1.53 2014/09/02 23:25:26 neal
// Re-enabled some debug registers.
//
// Revision 1.52 2014/08/27 19:07:31 bpoladian
// Can now use fewer than 3 dma engines without compilation errors.
//
// Revision 1.51 2014/08/24 00:47:42 neal
// Fixed reset resync.
//
// Revision 1.50 2014/07/18 18:11:42 neal
// Adjusted some fifo parameters.
//
// Revision 1.49 2014/07/08 15:20:52 neal
// Used RAM's output register in async fifos.
//
// Revision 1.48 2014/07/01 22:47:42 neal
// Changed async fifo to having an output register.
//
// Revision 1.47 2014/05/01 20:21:00 neal
// Added a port to the fifo.
//
// Revision 1.46 2013/08/12 21:44:15 bpoladian
// Fixed almostfull output for unused DMA engines.
//
// Revision 1.45 2013/05/23 17:49:54 neal
// Really removed the FIFOs when a DMA engine isn't needed.
//
// Revision 1.44 2013/05/21 20:48:15 neal
// Added some parameters to optionally disable DMA engines (both frequency and size optimization).
//
// Revision 1.43 2013/05/16 00:19:08 bpoladian
// Fixed one-transfer-per-cycle for new DMA fifo.
//
// Revision 1.42 2013/05/09 20:34:40 bpoladian
// Fixed byte addressing comment.
//
// Revision 1.41 2013/04/22 22:06:31 bpoladian
// Use async_blk_reg FIFO to improve timing instead of using an extra pipeline stage for fromhost data/ctrl.
//
// Revision 1.40 2013/01/03 19:24:09 neal
// Made all 3 of the DMA engines not transfer data when a target access is in progress.
//
// Revision 1.39 2012/11/30 22:24:26 bpoladian
// Add option for limiting interface to one fromhost transfer per cycle.
//
// Revision 1.38 2012/11/06 00:38:37 bpoladian
// Use synthesis directive instead of define for simulation warning.
//
// Revision 1.37 2012/09/28 21:25:38 bpoladian
// Logicial inversion of logic. Caused DMA to only advance when there was a target read instead of preventing DMA advance during a target read.
//
// Revision 1.36 2012/09/28 20:42:37 bpoladian
// Moved dma fromhost stall on target access one clock cycle earlier.
//
// Revision 1.35 2012/09/26 19:15:41 bpoladian
// Don't send DMA transactions on same cycle as target to make downstream muxing easier.
//
// Revision 1.34 2012/09/14 16:19:20 neal
// Fixed a vivado warning.
//
// Revision 1.33 2012/08/08 22:13:26 neal
// Registered reset on the correct clock domains.
//
// Revision 1.32 2012/07/25 22:03:48 bpoladian
// Make user_interrupts a single bit.
//
// Revision 1.31 2012/05/06 21:01:33 bpoladian
// Increased depth to fully utilize blockram.
//
// Revision 1.30 2012/03/20 18:36:35 bpoladian
// Reverted to large target fromhost FIFO due to latency of almostfull signal across NMB link.
//
// Revision 1.29 2012/03/19 21:20:36 bpoladian
// Reduced size/type of target fromhost FIFO.
//
// Revision 1.28 2012/03/19 17:45:14 bpoladian
// Change target tohost FIFO to small selectram FIFO.
//
// Revision 1.27 2012/01/19 19:29:29 neal
// Updated to a newer toe tx code base.
// Fixed synthesis warnings.
//
// Revision 1.26 2011/12/09 22:11:21 bpoladian
// Clear the read pending bit on timeout.
//
// Revision 1.25 2011/09/14 02:16:25 bpoladian
// Linted all assignment widths.
// Changed asynchronous always blocks to assign statements.
//
// Revision 1.24 2010/11/23 21:20:21 bpoladian
// Fixed bit width for unused DMA ctrl.
//
// Revision 1.23 2010/11/23 21:18:04 bpoladian
// Fixed bit width on dma_tohost_info.
//
// Revision 1.22 2010/10/14 18:20:29 bpoladian
// Fixed bug w/ multiple DMA streams writing simultaneously.
//
// Revision 1.21 2010/10/05 23:33:27 bpoladian
// Fixed case->casex.
//
// Revision 1.20 2010/10/05 22:20:10 bpoladian
// Cleaned up state transaction logic.
//
// Revision 1.19 2010/10/01 02:10:31 bpoladian
// Bigger FIFOs.
//
// Revision 1.18 2010/09/09 23:07:08 bpoladian
// Target read now prevents all updates on target interface while pending.
//
// Revision 1.17 2010/08/12 03:28:43 bpoladian
// Increase almostfull limit for return data.
//
// Revision 1.16 2010/07/01 02:20:23 bpoladian
// Fixed pipelining problem w/ back to back DMA transactions from separate engines.
//
// Revision 1.15 2010/06/11 17:47:00 jack
// display time in simulation debug messg
//
// Revision 1.14 2010/03/15 23:54:57 bpoladian
// Fixed alignment/handling of valid, transaction_type, and read_en.
//
// Revision 1.13 2010/03/12 00:55:55 bpoladian
// Higher almostfull limits.
//
// Revision 1.12 2010/03/11 04:46:13 bpoladian
// Fixed DMA2 almostfull bug.
//
// Revision 1.11 2010/03/03 03:11:51 bpoladian
// Removed target_bar port.
//
// Revision 1.10 2010/01/22 04:27:59 bpoladian
// pcie_tohost_info now 5 bits.
//
// Revision 1.9 2010/01/20 19:24:08 bpoladian
// Split hiaddr register into bar-specific registers.
//
// Revision 1.8 2010/01/19 01:02:34 bpoladian
// Fixed almost_full dma flags.
//
// Revision 1.7 2010/01/15 07:09:46 bpoladian
// Implemented 64-bit target accesses.
//
// Revision 1.6 2010/01/13 21:10:06 bpoladian
// Fixed info/ctrl signals.
//
// Revision 1.5 2009/11/05 23:52:13 bpoladian
// Separated almostfull flags for each transaction type.
//
// Revision 1.4 2009/11/03 04:23:43 bpoladian
// Fixed range on dma_fromhost_info.
//
// Revision 1.3 2009/10/30 23:34:07 bpoladian
// Fixed byte enables. Added generate labels.
//
// Revision 1.2 2009/10/28 02:31:20 bpoladian
// Make target_address_valid clear when not in address phase.
//
// Revision 1.1 2009/10/27 21:10:51 bpoladian
// Moved to new folder.
//
// Revision 1.3 2009/10/27 18:31:09 bpoladian
// Lots of syntactic and logical corrections.
//
// Revision 1.2 2009/10/22 04:12:38 bpoladian
// Code overhaul of pcie_x8_user_interface.
//
// Revision 1.1 2009/10/21 22:54:31 bpoladian
// Initial revision. Port list only.
//
// ################################################################
`include "dini/fifo/fifo_async_blk_reg.v"
`include "dini/fifo/fifo_async_sel.v"
`include "dini/misc/reset_resync.v"
`include "dini/pcie/pcie_dma/user_fpga/pcie_defines.v"
`ifdef INCL_PCIE_INTERFACE
`else
`define INCL_PCIE_INTERFACE
module pcie_interface #(
parameter NUM_DMA_ENGINES = 3,
parameter MAX_DMA_ENGINES = 3,
parameter ONE_XFER_PER_CYCLE = 1, // Only allow one fromhost interface to transfer data per clock cycle - makes muxing easy
parameter ADD_PIPELINE_OUTPUT = 0,
parameter DMA_ENGINE_ENABLES = 3'b111 // enable all DMA engines
) (
// clocks, resets
input clk,
input reset,
input user_clk, // clock from user
// Internal Bus
input [63:0] pcie_fromhost_data,
input [NUM_DMA_ENGINES:0] pcie_fromhost_transaction_type, // [0] for bar access
input [1:0] pcie_fromhost_isaddress,
input [1:0] pcie_fromhost_info,
input [1:0] pcie_fromhost_valid,
input [NUM_DMA_ENGINES:0] pcie_fromhost_almost_full,
// Internal Bus
output reg [63:0] pcie_tohost_data,
output reg [NUM_DMA_ENGINES:0] pcie_tohost_transaction_type, // [0] for bar access
output reg [4:0] pcie_tohost_info,
output reg [1:0] pcie_tohost_valid,
output reg [NUM_DMA_ENGINES:0] pcie_tohost_almost_full,
// to user, from_host, target signals
output reg [63:0] target_address, // 32-bit-aligned byte address ([1:0]==2'b0)
output reg [63:0] target_write_data,
output reg [7:0] target_write_be,
output reg target_address_valid,
output reg target_write_enable,
output reg target_read_enable,
output reg [3:0] target_request_tag,
input target_write_accept,
// debug only
output reg [2:0] debug_target_bar,
// to user, from_host, DMA0 signals
output [63:0] dma0_from_host_data,
output [7:0] dma0_from_host_ctrl,
output dma0_from_host_valid,
input dma0_from_host_advance,
// to user, from_host, DMA1 signals
output [63:0] dma1_from_host_data,
output [7:0] dma1_from_host_ctrl,
output dma1_from_host_valid,
input dma1_from_host_advance,
// to user, from_host, DMA2 signals
output [63:0] dma2_from_host_data,
output [7:0] dma2_from_host_ctrl,
output dma2_from_host_valid,
input dma2_from_host_advance,
// from user, to_host target signals
input [63:0] target_read_data,
input target_read_accept,
input [3:0] target_read_data_tag,
input target_read_data_valid,
output reg [7:0] target_read_ctrl,
input [7:0] target_read_data_ctrl,
// from user, to_host DMA0 signals
input [63:0] dma0_to_host_data,
input [7:0] dma0_to_host_ctrl,
input dma0_to_host_valid,
output dma0_to_host_almost_full,
// from user, to_host DMA1 signals
input [63:0] dma1_to_host_data,
input [7:0] dma1_to_host_ctrl,
input dma1_to_host_valid,
output dma1_to_host_almost_full,
// from user, to_host DMA2 signals
input [63:0] dma2_to_host_data,
input [7:0] dma2_to_host_ctrl,
input dma2_to_host_valid,
output dma2_to_host_almost_full
);
`include "dini/misc/functions.v"
/////////////////////////////////////////////////////////////////
// Target FromHost FIFO
/////////////////////////////////////////////////////////////////
wire [63:0] target_fromhost_data;
wire [1:0] target_fromhost_info;
wire [1:0] target_fromhost_isaddress;
wire target_fromhost_almostfull;
reg target_fromhost_read_en;
wire target_fromhost_empty;
reg target_fromhost_empty_d;
wire [1:0] target_fromhost_valid;
reg [3:0] target_first_be;
reg [3:0] target_last_be;
reg [31:0] bar1_hiaddr;
reg [31:0] bar2_hiaddr;
reg [31:0] bar4_hiaddr;
reg target_read_pending;
reg reset_clk;
wire reset_userclk;
always @(posedge clk or posedge reset) begin
if (reset) begin
reset_clk <= 1'b1;
end else begin
reset_clk <= 1'b0;
end
end
reset_resync i_rst_userclk (
.clk_in(clk),
.rst_in(reset),
.clk_out(user_clk),
.rst_out(reset_userclk)
);
fifo_async_blk_reg #(
.ADDR_W (9),
.DATA_W (2+2+2+64),
.ALMOSTFULL_LIMIT (128),
.ONECLOCK (0),
.INPUT_REG(0),
.OUTPUT_REG(3)
) i_fifo_target_fromhost (
.reset (reset_clk),
.wr_clk (clk),
.wr_en ((|pcie_fromhost_valid) & pcie_fromhost_transaction_type[0]),
.wr_din ({pcie_fromhost_info, pcie_fromhost_valid, pcie_fromhost_isaddress, pcie_fromhost_data}),
.wr_full_flaky (),
.wr_almostfull (target_fromhost_almostfull),
.wr_full_count_flaky (),
.rd_clk (user_clk),
.rd_en (target_fromhost_read_en),
.rd_dout ({target_fromhost_info, target_fromhost_valid, target_fromhost_isaddress, target_fromhost_data}),
.rd_empty (target_fromhost_empty),
.rd_empty_count (),
.rd_empty_ff()
);
reg [1:0] target_state;
localparam TARGET_ADDR = 2'b00;
localparam TARGET_FIRST_DATA = 2'b01;
localparam TARGET_DATA = 2'b10;
localparam TARGET_INVALID = 2'b11;
reg [10:0] target_pending_counter;
always @ (posedge user_clk or posedge reset_userclk) begin
if (reset_userclk) begin
target_address <= 'b0;
target_write_data <= 'b0;
target_write_be <= 'b0;
debug_target_bar <= 'b0;
target_address_valid <= 'b0;
target_write_enable <= 'b0;
target_read_enable <= 'b0;
target_read_pending <= 'b0;
target_first_be <= 'b0;
target_last_be <= 'b0;
target_request_tag <= 'b0;
target_read_ctrl <= 'b0;
target_state <= TARGET_ADDR;
target_fromhost_read_en <= 'b0;
target_fromhost_empty_d <= 'b0;
bar1_hiaddr <= 'b0;
bar2_hiaddr <= 'b0;
bar4_hiaddr <= 'b0;
end else begin
target_fromhost_empty_d <= target_fromhost_empty;
target_fromhost_read_en <= ~(target_fromhost_empty | target_fromhost_read_en | target_write_enable | target_read_enable | target_read_pending);
if(target_write_enable & target_write_accept)
target_write_enable <= 1'b0;
if(target_read_enable & target_read_accept)
target_read_enable <= 1'b0;
if(target_read_pending)
target_pending_counter <= target_pending_counter + 1'b1;
else
target_pending_counter <= 'b0;
if(target_read_data_valid | (&target_pending_counter))
target_read_pending <= 1'b0;
target_address_valid <= 1'b0;
case(target_state)
TARGET_INVALID: begin
target_state <= TARGET_ADDR;
end
TARGET_ADDR: begin
if(target_fromhost_read_en & ~target_fromhost_empty) begin
if(target_fromhost_isaddress[0]) begin
// BAR0 never resides in user space, so use this bit to load hiaddr
if(target_fromhost_data[`FH_ADDR_BAR0_HIT_BIT]) begin
case(target_fromhost_data[`FH_ADDR_BAR_HIT_RANGE+1])
3'b001: bar1_hiaddr <= target_fromhost_data[`FH_ADDR_ADDRESS_RANGE];
3'b010: bar2_hiaddr <= target_fromhost_data[`FH_ADDR_ADDRESS_RANGE];
3'b100: bar4_hiaddr <= target_fromhost_data[`FH_ADDR_ADDRESS_RANGE];
default: ;
endcase
end else begin
case(target_fromhost_data[`FH_ADDR_BAR_HIT_RANGE+1])
3'b001: target_address[63:32] <= bar1_hiaddr;
3'b010: target_address[63:32] <= bar2_hiaddr;
3'b100: target_address[63:32] <= bar4_hiaddr;
default: target_address[63:32] <= 'b0;
endcase
target_address[31:0] <= target_fromhost_data[`FH_ADDR_ADDRESS_RANGE];
target_address_valid <= 1'b1;
target_first_be <= target_fromhost_data[`FH_ADDR_FIRST_BE_RANGE];
target_last_be <= target_fromhost_data[`FH_ADDR_LAST_BE_RANGE];
debug_target_bar <= target_fromhost_data[`FH_ADDR_BAR_HIT_RANGE+1];
target_request_tag <= target_fromhost_data[`FH_ADDR_TAG_RANGE];
target_read_enable <= target_fromhost_data[`FH_ADDR_RD_NWR_BIT];
target_read_pending <= target_fromhost_data[`FH_ADDR_RD_NWR_BIT];
target_read_ctrl <= {7'h0, target_fromhost_info[1]};
if(~target_fromhost_data[`FH_ADDR_RD_NWR_BIT])
target_state <= TARGET_FIRST_DATA;
end
// synthesis translate_off
end else begin
$display("ERROR: pcie_interface.v: Expected Address Phase of User Target Access! %t",$time);
$stop;
// synthesis translate_on
end
end
end
TARGET_FIRST_DATA: begin
if(target_fromhost_read_en & ~target_fromhost_empty) begin
target_write_data <= target_fromhost_data;
target_write_enable <= 1'b1;
if(target_fromhost_isaddress[1]) begin
target_write_be[3:0] <= target_fromhost_valid[0] ? target_first_be : 4'h0;
target_write_be[7:4] <= target_fromhost_valid[1] ? (target_read_ctrl[0] ? target_last_be : target_first_be) : 4'h0;
target_state <= TARGET_ADDR;
end else begin
target_write_be[3:0] <= target_fromhost_valid[0] ? target_first_be : 4'h0;
target_write_be[7:4] <= target_fromhost_valid[1] ? 4'hF : 4'h0;
target_state <= TARGET_DATA;
end
end
end
TARGET_DATA: begin
if(target_fromhost_read_en & ~target_fromhost_empty) begin
target_write_data <= target_fromhost_data;
target_write_enable <= 1'b1;
if(target_fromhost_isaddress[1]) begin
target_write_be[3:0] <= target_fromhost_valid[1] ? 4'hF : target_last_be;
target_write_be[7:4] <= target_fromhost_valid[1] ? target_last_be : 4'h0;
target_state <= TARGET_ADDR;
end else begin
target_write_be[7:0] <= 8'hFF;
end
end
end
endcase
end
end
/////////////////////////////////////////////////////////////////
// DMA FromHost FIFO
/////////////////////////////////////////////////////////////////
wire [63:0] dma_fromhost_data [MAX_DMA_ENGINES-1:0];
wire [1:0] dma_fromhost_info [MAX_DMA_ENGINES-1:0];
wire [1:0] dma_fromhost_isaddress [MAX_DMA_ENGINES-1:0];
wire [1:0] dma_fromhost_valid [MAX_DMA_ENGINES-1:0];
wire [MAX_DMA_ENGINES-1:0] dma_fromhost_almostfull;
wire [MAX_DMA_ENGINES-1:0] dma_fromhost_read_en;
wire [MAX_DMA_ENGINES-1:0] dma_fromhost_empty;
genvar u;
generate
for(u=0; u<NUM_DMA_ENGINES; u=u+1) begin : dma_fromhost_fifos
if (DMA_ENGINE_ENABLES[u]) begin
fifo_async_blk_reg #(
.ADDR_W (9),
.DATA_W (2+2+2+64),
.ALMOSTFULL_LIMIT (128),
.ONECLOCK (0),
.INPUT_REG(0),
.OUTPUT_REG(3)
) i_fifo_dma_fromhost (
.reset (reset_clk),
.wr_clk (clk),
.wr_en ((|pcie_fromhost_valid) & pcie_fromhost_transaction_type[u+1]),
.wr_din ({pcie_fromhost_info, pcie_fromhost_valid, pcie_fromhost_isaddress, pcie_fromhost_data}),
.wr_full_flaky (),
.wr_almostfull (dma_fromhost_almostfull[u]),
.wr_full_count_flaky (),
.rd_clk (user_clk),
.rd_en (dma_fromhost_read_en[u]),
.rd_dout ({dma_fromhost_info[u], dma_fromhost_valid[u], dma_fromhost_isaddress[u], dma_fromhost_data[u]}),
.rd_empty (dma_fromhost_empty[u]),
.rd_empty_count (),
.rd_empty_ff ()
);
end else begin
assign {dma_fromhost_info[u], dma_fromhost_valid[u], dma_fromhost_isaddress[u], dma_fromhost_data[u]} = 'b0;
assign dma_fromhost_empty[u] = 1'b1;
assign dma_fromhost_almostfull[u] = 1'b0;
end
end
endgenerate
// keep track of some debug stuff!
`ifdef FPGA0_PCIEDEBUG_ADDRESSMATCH
(* dont_touch="TRUE", keep="TRUE" *) reg [63:0] fromhost_last0_dat;
(* dont_touch="TRUE", keep="TRUE" *) reg [1:0] fromhost_last0_isaddr;
(* dont_touch="TRUE", keep="TRUE" *) reg [1:0] fromhost_last0_valid;
(* dont_touch="TRUE", keep="TRUE" *) reg [1:0] fromhost_last0_info;
(* dont_touch="TRUE", keep="TRUE" *) reg [63:0] fromhost_last1_dat;
(* dont_touch="TRUE", keep="TRUE" *) reg [1:0] fromhost_last1_isaddr;
(* dont_touch="TRUE", keep="TRUE" *) reg [1:0] fromhost_last1_valid;
(* dont_touch="TRUE", keep="TRUE" *) reg [1:0] fromhost_last1_info;
always @(posedge user_clk or posedge reset_userclk) begin
if (reset_userclk) begin
fromhost_last0_dat <= 'b0;
fromhost_last0_isaddr <= 'b0;
fromhost_last0_valid <= 'b0;
fromhost_last0_info <= 'b0;
fromhost_last1_dat <= 'b0;
fromhost_last1_isaddr <= 'b0;
fromhost_last1_valid <= 'b0;
fromhost_last1_info <= 'b0;
end else begin
if (dma_fromhost_read_en[1] & (~dma_fromhost_empty[1])) begin
fromhost_last0_dat <= dma_fromhost_data[1];
fromhost_last0_isaddr <= dma_fromhost_isaddress[1];
fromhost_last0_valid <= dma_fromhost_valid[1];
fromhost_last0_info <= dma_fromhost_info[1];
fromhost_last1_dat <= fromhost_last0_dat;
fromhost_last1_isaddr <= fromhost_last0_isaddr;
fromhost_last1_valid <= fromhost_last0_valid;
fromhost_last1_info <= fromhost_last0_info;
end
end
end
`endif // FPGA0_PCIEDEBUG_ADDRESSMATCH
generate
if(ONE_XFER_PER_CYCLE) begin : gen_easy_muxing
// Don't send fromhost transactions on the same clock cycle
// This will make the muxing easier downstream
assign dma_fromhost_read_en[0] = dma0_from_host_advance & target_fromhost_empty_d;
assign dma_fromhost_read_en[1] = dma1_from_host_advance & target_fromhost_empty_d & (~(dma_fromhost_read_en[0] & (~dma_fromhost_empty[0])));
assign dma_fromhost_read_en[2] = dma2_from_host_advance & target_fromhost_empty_d & (~(dma_fromhost_read_en[0] & (~dma_fromhost_empty[0]))) & (~(dma_fromhost_read_en[1] & (~dma_fromhost_empty[1])));
end else begin : gen_best_throughput
// This will allow for any interface to transfer data independent of the other interfaces
assign dma_fromhost_read_en[0] = dma0_from_host_advance;
assign dma_fromhost_read_en[1] = dma1_from_host_advance;
assign dma_fromhost_read_en[2] = dma2_from_host_advance;
end
endgenerate
// Use async_blk_reg FIFO here to help w/ timing instead of adding extra pipeline flops
assign dma0_from_host_data = dma_fromhost_data[0];
assign dma0_from_host_ctrl = {2'h0, dma_fromhost_info[0], dma_fromhost_valid[0], dma_fromhost_isaddress[0]};
assign dma0_from_host_valid = (~dma_fromhost_empty[0]) & dma_fromhost_read_en[0];
assign dma1_from_host_data = dma_fromhost_data[1];
assign dma1_from_host_ctrl = {2'h0, dma_fromhost_info[1], dma_fromhost_valid[1], dma_fromhost_isaddress[1]};
assign dma1_from_host_valid = (~dma_fromhost_empty[1]) & dma_fromhost_read_en[1];
assign dma2_from_host_data = dma_fromhost_data[2];
assign dma2_from_host_ctrl = {2'h0, dma_fromhost_info[2], dma_fromhost_valid[2], dma_fromhost_isaddress[2]};
assign dma2_from_host_valid = (~dma_fromhost_empty[2]) & dma_fromhost_read_en[2];
/////////////////////////////////////////////////////////////////
// Target ToHost FIFO
/////////////////////////////////////////////////////////////////
wire [63:0] target_tohost_data;
wire [4:0] target_tohost_info;
wire target_tohost_empty;
reg target_tohost_read_en;
wire [6:0] target_tohost_ctrl_unused;
// This will never overflow because we do at most one read
// at a time to guarantee ordering
fifo_async_sel #(
.ADDR_W (3),
.DATA_W (8+4+64),
.ALMOSTFULL_LIMIT (1),
.ONECLOCK (0),
.GEN_WRALMOSTFULL (0)
) i_fifo_target_tohost (
.reset (reset_userclk),
.wr_clk (user_clk),
.wr_en (target_read_data_valid),
.wr_din ({target_read_data_ctrl, target_read_data_tag, target_read_data}),
.wr_full (),
.wr_almostfull (),
.wr_full_count (),
.rd_clk (clk),
.rd_en (target_tohost_read_en),
.rd_dout ({target_tohost_ctrl_unused, target_tohost_info[0], target_tohost_info[4:1], target_tohost_data}),
.rd_empty (target_tohost_empty),
.rd_empty_count ()
);
/////////////////////////////////////////////////////////////////
// DMA ToHost FIFO
/////////////////////////////////////////////////////////////////
wire [63:0] dma_tohost_data_in [MAX_DMA_ENGINES-1:0];
wire [7:0] dma_tohost_ctrl_in [MAX_DMA_ENGINES-1:0];
wire [MAX_DMA_ENGINES-1:0] dma_tohost_valid;
wire [MAX_DMA_ENGINES-1:0] dma_tohost_almostfull;
wire [63:0] dma_tohost_data [MAX_DMA_ENGINES-1:0];
wire [4:0] dma_tohost_info [MAX_DMA_ENGINES-1:0];
wire [MAX_DMA_ENGINES-1:0] dma_tohost_empty;
reg [MAX_DMA_ENGINES-1:0] dma_tohost_read_en;
wire [2:0] dma_tohost_ctrl_unused [MAX_DMA_ENGINES-1:0];
assign dma_tohost_data_in[0] = dma0_to_host_data;
assign dma_tohost_data_in[1] = dma1_to_host_data;
assign dma_tohost_data_in[2] = dma2_to_host_data;
assign dma_tohost_ctrl_in[0] = dma0_to_host_ctrl;
assign dma_tohost_ctrl_in[1] = dma1_to_host_ctrl;
assign dma_tohost_ctrl_in[2] = dma2_to_host_ctrl;
assign dma_tohost_valid[0] = dma0_to_host_valid;
assign dma_tohost_valid[1] = dma1_to_host_valid;
assign dma_tohost_valid[2] = dma2_to_host_valid;
assign dma0_to_host_almost_full = dma_tohost_almostfull[0];
assign dma1_to_host_almost_full = dma_tohost_almostfull[1];
assign dma2_to_host_almost_full = dma_tohost_almostfull[2];
genvar t;
generate
for(t=0; t<NUM_DMA_ENGINES; t=t+1) begin : dma_tohost_fifos
if (DMA_ENGINE_ENABLES[t]) begin
fifo_async_blk_reg #(
.ADDR_W (9),
.DATA_W (8+64),
.ALMOSTFULL_LIMIT (128),
.ONECLOCK (0),
.INPUT_REG(0),
.OUTPUT_REG(3)
) i_fifo_dma_tohost (
.reset (reset_userclk),
.wr_clk (user_clk),
.wr_en (dma_tohost_valid[t]),
.wr_din ({dma_tohost_ctrl_in[t], dma_tohost_data_in[t]}),
.wr_full_flaky (),
.wr_almostfull (dma_tohost_almostfull[t]),
.wr_full_count_flaky (),
.rd_clk (clk),
.rd_en (dma_tohost_read_en[t]),
.rd_dout ({dma_tohost_ctrl_unused[t], dma_tohost_info[t], dma_tohost_data[t]}),
.rd_empty (dma_tohost_empty[t]),
.rd_empty_count (),
.rd_empty_ff()
);
end else begin
assign dma_tohost_ctrl_unused[t] = 'b0;
assign dma_tohost_info[t] = 'b0;
assign dma_tohost_data[t] = 'b0;
assign dma_tohost_empty[t] = 1'b1;
assign dma_tohost_almostfull[t] = 1'b0;
end
end
endgenerate
/////////////////////////////////////////////////////////////////
// ToHost Mux
/////////////////////////////////////////////////////////////////
integer i;
reg [log2(NUM_DMA_ENGINES)-1:0] dma_engine_active;
reg [log2(NUM_DMA_ENGINES)-1:0] dma_engine_active_d;
reg [NUM_DMA_ENGINES:0] pcie_tohost_transaction_state;
always @ (posedge clk or posedge reset_clk) begin
if (reset_clk) begin
pcie_tohost_data <= 'b0;
pcie_tohost_transaction_state <= 'b0;
pcie_tohost_transaction_type <= 'b0;
pcie_tohost_info <= 'b0;
pcie_tohost_valid <= 'b0;
pcie_tohost_almost_full <= 'b0;
target_tohost_read_en <= 'b0;
dma_tohost_read_en <= 'b0;
dma_engine_active <= 'b0;
dma_engine_active_d <= 'b0;
end else begin
pcie_tohost_almost_full[0] <= target_fromhost_almostfull;
for(i=0; i<NUM_DMA_ENGINES; i=i+1)
pcie_tohost_almost_full[i+1] <= dma_fromhost_almostfull[i];
pcie_tohost_transaction_state <= {(~dma_tohost_empty), ~target_tohost_empty};
dma_engine_active <= 'b0;
for(i=0; i<NUM_DMA_ENGINES; i=i+1) begin
if(~dma_tohost_empty[i] & ~pcie_fromhost_almost_full[i+1])
dma_engine_active <= i[log2(NUM_DMA_ENGINES)-1:0];
end
dma_engine_active_d <= dma_engine_active;
/* verilator lint_off CASEX */
casex (pcie_tohost_transaction_state)
// No Transaction
4'b0000: begin
target_tohost_read_en <= 'b0;
dma_tohost_read_en <= 'b0;
end
// Target Transaction
4'bxxx1: begin
target_tohost_read_en <= ~pcie_fromhost_almost_full[0];
dma_tohost_read_en <= 'b0;
end
// DMA Transaction
default: begin
target_tohost_read_en <= 'b0;
dma_tohost_read_en <= 'b0;
dma_tohost_read_en[dma_engine_active] <= ~pcie_fromhost_almost_full[dma_engine_active+1];
end
endcase
/* verilator lint_on CASEX */
pcie_tohost_valid <= 2'b00;
if(target_tohost_read_en) begin
pcie_tohost_transaction_type <= {{NUM_DMA_ENGINES{1'b0}}, 1'b1} << 0;
pcie_tohost_data <= target_tohost_data;
pcie_tohost_info <= target_tohost_info;
pcie_tohost_valid <= {2{~target_tohost_empty}};
end else if(dma_tohost_read_en[dma_engine_active_d]) begin
pcie_tohost_transaction_type <= {{NUM_DMA_ENGINES{1'b0}}, 1'b1} << (dma_engine_active_d+1);
pcie_tohost_data <= dma_tohost_data[dma_engine_active_d];
pcie_tohost_info <= dma_tohost_info[dma_engine_active_d];
pcie_tohost_valid <= {2{~dma_tohost_empty[dma_engine_active_d]}};
// synthesis translate_off
// Demand-mode checks
if(dma_tohost_info[dma_engine_active_d][2] & dma_tohost_info[dma_engine_active_d][4]) begin
// Check demand-mode length and byte enables
if(~dma_tohost_info[dma_engine_active_d][3]) begin
// Byte enables active
if(~dma_tohost_data[dma_engine_active_d][28] & dma_tohost_data[dma_engine_active_d][26]) begin
if(dma_tohost_data[dma_engine_active_d][23:20]==0) begin
$display("%m: ERROR: Demand-mode descriptor byte enables are active, but first dword byte enables are 0!");
$stop;
end
if(dma_tohost_data[dma_engine_active_d][19:16]==0) begin
$display("%m: ERROR: Demand-mode descriptor byte enables are active, but last dword byte enables are 0!");
$stop;
end
if(dma_tohost_data[dma_engine_active_d][15:0]>1) begin
casex(dma_tohost_data[dma_engine_active_d][23:20])
4'bxx01,
4'bx01x,
4'b01xx: begin
$display("%m: ERROR: Demand-mode descriptor first byte-enable causes discontinuous bytes!");
$stop;
end
default: ;
endcase
casex(dma_tohost_data[dma_engine_active_d][19:16])
4'b10xx,
4'bx10x,
4'bxx10: begin
$display("%m: ERROR: Demand-mode descriptor last byte-enable causes discontinuous bytes!");
$stop;
end
default: ;
endcase
end
if(dma_tohost_data[dma_engine_active_d][15:0]==1) begin
if(dma_tohost_data[dma_engine_active_d][19:16]!=0)
$display("%m: WARNING: Demand-mode descriptor last byte-enable will be ignored for packet w/ dword_length==1");
end
end
end
// Check demand-mode address
if(dma_tohost_info[dma_engine_active_d][3]) begin
if(|dma_tohost_data[dma_engine_active_d][1:0]) begin
$display("%m: ERROR: Demand-mode address is not DWORD aligned! (Bits 1:0 must always be 2'b00)");
$stop;
end
end
end
// synthesis translate_on
end
end
end
endmodule
`endif // INCL_PCIE_INTERFACE
|
(** * Stlc: The Simply Typed Lambda-Calculus *)
Require Export Types.
(* ###################################################################### *)
(** * The Simply Typed Lambda-Calculus *)
(** The simply typed lambda-calculus (STLC) is a tiny core calculus
embodying the key concept of _functional abstraction_, which shows
up in pretty much every real-world programming language in some
form (functions, procedures, methods, etc.).
We will follow exactly the same pattern as in the previous
chapter when formalizing this calculus (syntax, small-step
semantics, typing rules) and its main properties (progress and
preservation). The new technical challenges (which will take some
work to deal with) all arise from the mechanisms of _variable
binding_ and _substitution_. *)
(* ###################################################################### *)
(** ** Overview *)
(** The STLC is built on some collection of _base types_ -- booleans,
numbers, strings, etc. The exact choice of base types doesn't
matter -- the construction of the language and its theoretical
properties work out pretty much the same -- so for the sake of
brevity let's take just [Bool] for the moment. At the end of the
chapter we'll see how to add more base types, and in later
chapters we'll enrich the pure STLC with other useful constructs
like pairs, records, subtyping, and mutable state.
Starting from the booleans, we add three things:
- variables
- function abstractions
- application
This gives us the following collection of abstract syntax
constructors (written out here in informal BNF notation -- we'll
formalize it below).
*)
(** Informal concrete syntax:
t ::= x variable
| \x:T1.t2 abstraction
| t1 t2 application
| true constant true
| false constant false
| if t1 then t2 else t3 conditional
*)
(** The [\] symbol (backslash, in ascii) in a function abstraction
[\x:T1.t2] is generally written as a greek letter "lambda" (hence
the name of the calculus). The variable [x] is called the
_parameter_ to the function; the term [t1] is its _body_. The
annotation [:T] specifies the type of arguments that the function
can be applied to. *)
(** Some examples:
- [\x:Bool. x]
The identity function for booleans.
- [(\x:Bool. x) true]
The identity function for booleans, applied to the boolean [true].
- [\x:Bool. if x then false else true]
The boolean "not" function.
- [\x:Bool. true]
The constant function that takes every (boolean) argument to
[true]. *)
(**
- [\x:Bool. \y:Bool. x]
A two-argument function that takes two booleans and returns
the first one. (Note that, as in Coq, a two-argument function
is really a one-argument function whose body is also a
one-argument function.)
- [(\x:Bool. \y:Bool. x) false true]
A two-argument function that takes two booleans and returns
the first one, applied to the booleans [false] and [true].
Note that, as in Coq, application associates to the left --
i.e., this expression is parsed as [((\x:Bool. \y:Bool. x)
false) true].
- [\f:Bool->Bool. f (f true)]
A higher-order function that takes a _function_ [f] (from
booleans to booleans) as an argument, applies [f] to [true],
and applies [f] again to the result.
- [(\f:Bool->Bool. f (f true)) (\x:Bool. false)]
The same higher-order function, applied to the constantly
[false] function. *)
(** As the last several examples show, the STLC is a language of
_higher-order_ functions: we can write down functions that take
other functions as arguments and/or return other functions as
results.
Another point to note is that the STLC doesn't provide any
primitive syntax for defining _named_ functions -- all functions
are "anonymous." We'll see in chapter [MoreStlc] that it is easy
to add named functions to what we've got -- indeed, the
fundamental naming and binding mechanisms are exactly the same.
The _types_ of the STLC include [Bool], which classifies the
boolean constants [true] and [false] as well as more complex
computations that yield booleans, plus _arrow types_ that classify
functions. *)
(**
T ::= Bool
| T1 -> T2
For example:
- [\x:Bool. false] has type [Bool->Bool]
- [\x:Bool. x] has type [Bool->Bool]
- [(\x:Bool. x) true] has type [Bool]
- [\x:Bool. \y:Bool. x] has type [Bool->Bool->Bool] (i.e. [Bool -> (Bool->Bool)])
- [(\x:Bool. \y:Bool. x) false] has type [Bool->Bool]
- [(\x:Bool. \y:Bool. x) false true] has type [Bool]
*)
(* ###################################################################### *)
(** ** Syntax *)
Module STLC.
(* ################################### *)
(** *** Types *)
Inductive ty : Type :=
| TBool : ty
| TArrow : ty -> ty -> ty.
(* ################################### *)
(** *** Terms *)
Inductive tm : Type :=
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Tactic Notation "t_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tvar" | Case_aux c "tapp"
| Case_aux c "tabs" | Case_aux c "ttrue"
| Case_aux c "tfalse" | Case_aux c "tif" ].
(** Note that an abstraction [\x:T.t] (formally, [tabs x T t]) is
always annotated with the type [T] of its parameter, in contrast
to Coq (and other functional languages like ML, Haskell, etc.),
which use _type inference_ to fill in missing annotations. We're
not considering type inference here, to keep things simple. *)
(** Some examples... *)
Definition x := (Id 0).
Definition y := (Id 1).
Definition z := (Id 2).
Hint Unfold x.
Hint Unfold y.
Hint Unfold z.
(** [idB = \x:Bool. x] *)
Notation idB :=
(tabs x TBool (tvar x)).
(** [idBB = \x:Bool->Bool. x] *)
Notation idBB :=
(tabs x (TArrow TBool TBool) (tvar x)).
(** [idBBBB = \x:(Bool->Bool) -> (Bool->Bool). x] *)
Notation idBBBB :=
(tabs x (TArrow (TArrow TBool TBool)
(TArrow TBool TBool))
(tvar x)).
(** [k = \x:Bool. \y:Bool. x] *)
Notation k := (tabs x TBool (tabs y TBool (tvar x))).
(** [notB = \x:Bool. if x then false else true] *)
Notation notB := (tabs x TBool (tif (tvar x) tfalse ttrue)).
(** (We write these as [Notation]s rather than [Definition]s to make
things easier for [auto].) *)
(* ###################################################################### *)
(** ** Operational Semantics *)
(** To define the small-step semantics of STLC terms, we begin -- as
always -- by defining the set of values. Next, we define the
critical notions of _free variables_ and _substitution_, which are
used in the reduction rule for application expressions. And
finally we give the small-step relation itself. *)
(* ################################### *)
(** *** Values *)
(** To define the values of the STLC, we have a few cases to consider.
First, for the boolean part of the language, the situation is
clear: [true] and [false] are the only values. An [if]
expression is never a value. *)
(** Second, an application is clearly not a value: It represents a
function being invoked on some argument, which clearly still has
work left to do. *)
(** Third, for abstractions, we have a choice:
- We can say that [\x:T.t1] is a value only when [t1] is a
value -- i.e., only if the function's body has been
reduced (as much as it can be without knowing what argument it
is going to be applied to).
- Or we can say that [\x:T.t1] is always a value, no matter
whether [t1] is one or not -- in other words, we can say that
reduction stops at abstractions.
Coq, in its built-in functional programming langauge, makes the
first choice -- for example,
Eval simpl in (fun x:bool => 3 + 4)
yields [fun x:bool => 7].
Most real-world functional programming languages make the second
choice -- reduction of a function's body only begins when the
function is actually applied to an argument. We also make the
second choice here. *)
(** Finally, having made the choice not to reduce under abstractions,
we don't need to worry about whether variables are values, since
we'll always be reducing programs "from the outside in," and that
means the [step] relation will always be working with closed
terms (ones with no free variables). *)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tabs x T t)
| v_true :
value ttrue
| v_false :
value tfalse.
Hint Constructors value.
(* ###################################################################### *)
(** *** Free Variables and Substitution *)
(** Now we come to the heart of the STLC: the operation of
substituting one term for a variable in another term.
This operation will be used below to define the operational
semantics of function application, where we will need to
substitute the argument term for the function parameter in the
function's body. For example, we reduce
(\x:Bool. if x then true else x) false
to
if false then true else false
]]
by substituting [false] for the parameter [x] in the body of the
function.
In general, we need to be able to substitute some given
term [s] for occurrences of some variable [x] in another term [t].
In informal discussions, this is usually written [ [x:=s]t ] and
pronounced "substitute [x] with [s] in [t]." *)
(** Here are some examples:
- [[x:=true] (if x then x else false)] yields [if true then true else false]
- [[x:=true] x] yields [true]
- [[x:=true] (if x then x else y)] yields [if true then true else y]
- [[x:=true] y] yields [y]
- [[x:=true] false] yields [false] (vacuous substitution)
- [[x:=true] (\y:Bool. if y then x else false)] yields [\y:Bool. if y then true else false]
- [[x:=true] (\y:Bool. x)] yields [\y:Bool. true]
- [[x:=true] (\y:Bool. y)] yields [\y:Bool. y]
- [[x:=true] (\x:Bool. x)] yields [\x:Bool. x]
The last example is very important: substituting [x] with [true] in
[\x:Bool. x] does _not_ yield [\x:Bool. true]! The reason for
this is that the [x] in the body of [\x:Bool. x] is _bound_ by the
abstraction: it is a new, local name that just happens to be
spelled the same as some global name [x]. *)
(** Here is the definition, informally...
[x:=s]x = s
[x:=s]y = y if x <> y
[x:=s](\x:T11.t12) = \x:T11. t12
[x:=s](\y:T11.t12) = \y:T11. [x:=s]t12 if x <> y
[x:=s](t1 t2) = ([x:=s]t1) ([x:=s]t2)
[x:=s]true = true
[x:=s]false = false
[x:=s](if t1 then t2 else t3) =
if [x:=s]t1 then [x:=s]t2 else [x:=s]t3
]]
... and formally: *)
Reserved Notation "'[' x ':=' s ']' t" (at level 20).
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar x' =>
if eq_id_dec x x' then s else t
| tabs x' T t1 =>
tabs x' T (if eq_id_dec x x' then t1 else ([x:=s] t1))
| tapp t1 t2 =>
tapp ([x:=s] t1) ([x:=s] t2)
| ttrue =>
ttrue
| tfalse =>
tfalse
| tif t1 t2 t3 =>
tif ([x:=s] t1) ([x:=s] t2) ([x:=s] t3)
end
where "'[' x ':=' s ']' t" := (subst x s t).
(** _Technical note_: Substitution becomes trickier to define if we
consider the case where [s], the term being substituted for a
variable in some other term, may itself contain free variables.
Since we are only interested here in defining the [step] relation
on closed terms (i.e., terms like [\x:Bool. x], that do not mention
variables are not bound by some enclosing lambda), we can skip
this extra complexity here, but it must be dealt with when
formalizing richer languages. *)
(** *** *)
(** **** Exercise: 3 stars (substi) *)
(** The definition that we gave above uses Coq's [Fixpoint] facility
to define substitution as a _function_. Suppose, instead, we
wanted to define substitution as an inductive _relation_ [substi].
We've begun the definition by providing the [Inductive] header and
one of the constructors; your job is to fill in the rest of the
constructors. *)
Inductive substi (s:tm) (x:id) : tm -> tm -> Prop :=
| s_var1 :
substi s x (tvar x) s
| s_var2 : forall y:id,
x <> y -> substi s x (tvar y) (tvar y)
| s_abs1 : forall T t,
substi s x (tabs x T t) (tabs x T t)
| s_abs2 : forall y T t t',
x <> y ->
substi s x t t' ->
substi s x (tabs y T t) (tabs y T t')
| s_app : forall t1 t2 t1' t2',
substi s x t1 t1' ->
substi s x t2 t2' ->
substi s x (tapp t1 t2) (tapp t1' t2')
| s_true : substi s x ttrue ttrue
| s_false : substi s x tfalse tfalse
| s_if : forall t1 t1' t2 t2' t3 t3',
substi s x t1 t1' ->
substi s x t2 t2' ->
substi s x t3 t3' ->
substi s x (tif t1 t2 t3) (tif t1' t2' t3')
.
Hint Constructors substi.
Theorem substi_correct : forall s x t t',
[x:=s]t = t' <-> substi s x t t'.
Proof. intros s x t t'. split.
Case "->". generalize dependent t'.
t_cases (induction t) SCase; intros.
SCase "tvar". unfold subst in H. destruct (eq_id_dec x i); subst.
apply s_var1. apply s_var2. assumption.
SCase "tapp".
replace ([x := s]tapp t1 t2) with (tapp ([x := s]t1) ([x := s] t2)) in H by reflexivity.
rewrite <- H. constructor. apply IHt1. reflexivity. apply IHt2. reflexivity.
SCase "tabs".
unfold subst in H.
destruct (eq_id_dec x i).
SSCase "x=i". rewrite <- H. subst. constructor.
SSCase "x<>i". fold subst in H. rewrite <- H. constructor. assumption. apply IHt. reflexivity.
SCase "ttrue".
simpl in H. rewrite <- H. constructor.
SCase "tfalse".
simpl in H. rewrite <- H. constructor.
SCase "tif".
rewrite <- H.
replace ([x := s]tif t1 t2 t3) with (tif ([x := s]t1) ([x := s]t2) ([x := s]t3)) by reflexivity.
constructor. auto. auto. auto.
Case "<-". generalize dependent t'.
t_cases (induction t) SCase; intros.
SCase "tvar". inversion H; subst; unfold subst.
SSCase "x=i". destruct (eq_id_dec i i). reflexivity. apply ex_falso_quodlibet. apply n. reflexivity.
SSCase "x<>i". destruct (eq_id_dec x i). unfold not in H1. apply H1 in e. inversion e. reflexivity.
SCase "tapp". inversion H; subst; clear H. apply IHt1 in H2. apply IHt2 in H4.
replace ([x := s]tapp t1 t2) with (tapp ([x := s]t1) ([x := s]t2)) by reflexivity. rewrite H2. rewrite H4. reflexivity.
SCase "tabs". inversion H; subst.
SSCase "i=i". unfold subst. destruct (eq_id_dec i i). reflexivity. contradiction n. reflexivity.
SSCase "x<>i". unfold subst. destruct (eq_id_dec x i). apply H4 in e. inversion e. fold subst.
apply IHt in H5. rewrite H5. reflexivity.
SCase "ttrue". inversion H. reflexivity.
SCase "tfalse". inversion H. reflexivity.
SCase "tif". inversion H; subst. apply IHt1 in H3. apply IHt2 in H5. apply IHt3 in H6.
replace ([x := s]tif t1 t2 t3) with (tif ([x := s]t1) ([x := s]t2) ([x := s]t3)) by reflexivity.
rewrite H3. rewrite H5. rewrite H6. reflexivity.
Qed.
(** [] *)
(* ################################### *)
(** *** Reduction *)
(** The small-step reduction relation for STLC now follows the same
pattern as the ones we have seen before. Intuitively, to reduce a
function application, we first reduce its left-hand side until it
becomes a literal function; then we reduce its right-hand
side (the argument) until it is also a value; and finally we
substitute the argument for the bound variable in the body of the
function. This last rule, written informally as
(\x:T.t12) v2 ==> [x:=v2]t12
is traditionally called "beta-reduction". *)
(**
value v2
---------------------------- (ST_AppAbs)
(\x:T.t12) v2 ==> [x:=v2]t12
t1 ==> t1'
---------------- (ST_App1)
t1 t2 ==> t1' t2
value v1
t2 ==> t2'
---------------- (ST_App2)
v1 t2 ==> v1 t2'
*)
(** ... plus the usual rules for booleans:
-------------------------------- (ST_IfTrue)
(if true then t1 else t2) ==> t1
--------------------------------- (ST_IfFalse)
(if false then t1 else t2) ==> t2
t1 ==> t1'
---------------------------------------------------- (ST_If)
(if t1 then t2 else t3) ==> (if t1' then t2 else t3)
*)
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T t12 v2,
value v2 ->
(tapp (tabs x T t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
tapp t1 t2 ==> tapp t1' t2
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
tapp v1 t2 ==> tapp v1 t2'
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif t1 t2 t3) ==> (tif t1' t2 t3)
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_AppAbs" | Case_aux c "ST_App1"
| Case_aux c "ST_App2" | Case_aux c "ST_IfTrue"
| Case_aux c "ST_IfFalse" | Case_aux c "ST_If" ].
Hint Constructors step.
Notation multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
(* ##################################### *)
(** *** Examples *)
(** Example:
((\x:Bool->Bool. x) (\x:Bool. x)) ==>* (\x:Bool. x)
i.e.
(idBB idB) ==>* idB
*)
Lemma step_example1 :
(tapp idBB idB) ==>* idB.
Proof.
eapply multi_step.
apply ST_AppAbs.
apply v_abs.
simpl.
apply multi_refl. Qed.
(** Example:
((\x:Bool->Bool. x) ((\x:Bool->Bool. x) (\x:Bool. x)))
==>* (\x:Bool. x)
i.e.
(idBB (idBB idB)) ==>* idB.
*)
Lemma step_example2 :
(tapp idBB (tapp idBB idB)) ==>* idB.
Proof.
eapply multi_step.
apply ST_App2. auto.
apply ST_AppAbs. auto.
eapply multi_step.
apply ST_AppAbs. simpl. auto.
simpl. apply multi_refl. Qed.
(** Example:
((\x:Bool->Bool. x) (\x:Bool. if x then false
else true)) true)
==>* false
i.e.
((idBB notB) ttrue) ==>* tfalse.
*)
Lemma step_example3 :
tapp (tapp idBB notB) ttrue ==>* tfalse.
Proof.
eapply multi_step.
apply ST_App1. apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_IfTrue. apply multi_refl. Qed.
(** Example:
((\x:Bool->Bool. x) ((\x:Bool. if x then false
else true) true))
==>* false
i.e.
(idBB (notB ttrue)) ==>* tfalse.
*)
Lemma step_example4 :
tapp idBB (tapp notB ttrue) ==>* tfalse.
Proof.
eapply multi_step.
apply ST_App2. auto.
apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_App2. auto.
apply ST_IfTrue.
eapply multi_step.
apply ST_AppAbs. auto. simpl.
apply multi_refl. Qed.
(** A more automatic proof *)
Lemma step_example1' :
(tapp idBB idB) ==>* idB.
Proof. normalize. Qed.
(** Again, we can use the [normalize] tactic from above to simplify
the proof. *)
Lemma step_example2' :
(tapp idBB (tapp idBB idB)) ==>* idB.
Proof.
normalize.
Qed.
Lemma step_example3' :
tapp (tapp idBB notB) ttrue ==>* tfalse.
Proof. normalize. Qed.
Lemma step_example4' :
tapp idBB (tapp notB ttrue) ==>* tfalse.
Proof. normalize. Qed.
(** **** Exercise: 2 stars (step_example3) *)
(** Try to do this one both with and without [normalize]. *)
Lemma step_example5 :
(tapp (tapp idBBBB idBB) idB)
==>* idB.
Proof.
eapply multi_step. apply ST_App1. apply ST_AppAbs. auto. simpl.
eapply multi_step. apply ST_AppAbs. auto. simpl.
apply multi_refl.
Qed.
Lemma step_example5' :
(tapp (tapp idBBBB idBB) idB)
==>* idB.
Proof. normalize. Qed.
(** [] *)
(* ###################################################################### *)
(** ** Typing *)
(* ################################### *)
(** *** Contexts *)
(** _Question_: What is the type of the term "[x y]"?
_Answer_: It depends on the types of [x] and [y]!
I.e., in order to assign a type to a term, we need to know
what assumptions we should make about the types of its free
variables.
This leads us to a three-place "typing judgment", informally
written [Gamma |- t : T], where [Gamma] is a
"typing context" -- a mapping from variables to their types. *)
(** We hide the definition of partial maps in a module since it is
actually defined in [SfLib]. *)
Module PartialMap.
Definition partial_map (A:Type) := id -> option A.
Definition empty {A:Type} : partial_map A := (fun _ => None).
(** Informally, we'll write [Gamma, x:T] for "extend the partial
function [Gamma] to also map [x] to [T]." Formally, we use the
function [extend] to add a binding to a partial map. *)
Definition extend {A:Type} (Gamma : partial_map A) (x:id) (T : A) :=
fun x' => if eq_id_dec x x' then Some T else Gamma x'.
Lemma extend_eq : forall A (ctxt: partial_map A) x T,
(extend ctxt x T) x = Some T.
Proof.
intros. unfold extend. rewrite eq_id. auto.
Qed.
Lemma extend_neq : forall A (ctxt: partial_map A) x1 T x2,
x2 <> x1 ->
(extend ctxt x2 T) x1 = ctxt x1.
Proof.
intros. unfold extend. rewrite neq_id; auto.
Qed.
End PartialMap.
Definition context := partial_map ty.
(* ################################### *)
(** *** Typing Relation *)
(**
Gamma x = T
-------------- (T_Var)
Gamma |- x \in T
Gamma , x:T11 |- t12 \in T12
---------------------------- (T_Abs)
Gamma |- \x:T11.t12 \in T11->T12
Gamma |- t1 \in T11->T12
Gamma |- t2 \in T11
---------------------- (T_App)
Gamma |- t1 t2 \in T12
-------------------- (T_True)
Gamma |- true \in Bool
--------------------- (T_False)
Gamma |- false \in Bool
Gamma |- t1 \in Bool Gamma |- t2 \in T Gamma |- t3 \in T
-------------------------------------------------------- (T_If)
Gamma |- if t1 then t2 else t3 \in T
We can read the three-place relation [Gamma |- t \in T] as:
"to the term [t] we can assign the type [T] using as types for
the free variables of [t] the ones specified in the context
[Gamma]." *)
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T,
Gamma x = Some T ->
Gamma |- tvar x \in T
| T_Abs : forall Gamma x T11 T12 t12,
extend Gamma x T11 |- t12 \in T12 ->
Gamma |- tabs x T11 t12 \in TArrow T11 T12
| T_App : forall T11 T12 Gamma t1 t2,
Gamma |- t1 \in TArrow T11 T12 ->
Gamma |- t2 \in T11 ->
Gamma |- tapp t1 t2 \in T12
| T_True : forall Gamma,
Gamma |- ttrue \in TBool
| T_False : forall Gamma,
Gamma |- tfalse \in TBool
| T_If : forall t1 t2 t3 T Gamma,
Gamma |- t1 \in TBool ->
Gamma |- t2 \in T ->
Gamma |- t3 \in T ->
Gamma |- tif t1 t2 t3 \in T
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_Var" | Case_aux c "T_Abs"
| Case_aux c "T_App" | Case_aux c "T_True"
| Case_aux c "T_False" | Case_aux c "T_If" ].
Hint Constructors has_type.
(* ################################### *)
(** *** Examples *)
Example typing_example_1 :
empty |- tabs x TBool (tvar x) \in TArrow TBool TBool.
Proof.
apply T_Abs. apply T_Var. reflexivity. Qed.
(** Note that since we added the [has_type] constructors to the hints
database, auto can actually solve this one immediately. *)
Example typing_example_1' :
empty |- tabs x TBool (tvar x) \in TArrow TBool TBool.
Proof. auto. Qed.
(** Another example:
empty |- \x:A. \y:A->A. y (y x))
\in A -> (A->A) -> A.
*)
Example typing_example_2 :
empty |-
(tabs x TBool
(tabs y (TArrow TBool TBool)
(tapp (tvar y) (tapp (tvar y) (tvar x))))) \in
(TArrow TBool (TArrow (TArrow TBool TBool) TBool)).
Proof with auto using extend_eq.
apply T_Abs.
apply T_Abs.
eapply T_App. apply T_Var...
eapply T_App. apply T_Var...
apply T_Var...
Qed.
(** **** Exercise: 2 stars, optional (typing_example_2_full) *)
(** Prove the same result without using [auto], [eauto], or
[eapply]. *)
Example typing_example_2_full :
empty |-
(tabs x TBool
(tabs y (TArrow TBool TBool)
(tapp (tvar y) (tapp (tvar y) (tvar x))))) \in
(TArrow TBool (TArrow (TArrow TBool TBool) TBool)).
Proof.
apply T_Abs.
apply T_Abs.
apply T_App with (T11:=TBool). apply T_Var. apply extend_eq.
apply T_App with (T11:=TBool). apply T_Var. apply extend_eq.
apply T_Var. apply extend_neq. unfold not. intros. inversion H.
Qed.
(** [] *)
(** **** Exercise: 2 stars (typing_example_3) *)
(** Formally prove the following typing derivation holds: *)
(**
empty |- \x:Bool->Bool. \y:Bool->Bool. \z:Bool.
y (x z)
\in T.
*)
Tactic Notation "solve_neq" :=
unfold not; intro Contra; inversion Contra.
Example typing_example_3 :
exists T,
empty |-
(tabs x (TArrow TBool TBool)
(tabs y (TArrow TBool TBool)
(tabs z TBool
(tapp (tvar y) (tapp (tvar x) (tvar z)))))) \in
T.
Proof with auto.
exists (TArrow (TArrow TBool TBool) (TArrow (TArrow TBool TBool) (TArrow TBool TBool))).
apply T_Abs.
apply T_Abs.
apply T_Abs.
apply T_App with (T11:=TBool). apply T_Var. apply extend_neq. solve_neq.
apply T_App with (T11:=TBool). apply T_Var. apply extend_neq. solve_neq.
apply T_Var. apply extend_eq.
Qed.
(** [] *)
(** We can also show that terms are _not_ typable. For example, let's
formally check that there is no typing derivation assigning a type
to the term [\x:Bool. \y:Bool, x y] -- i.e.,
~ exists T,
empty |- \x:Bool. \y:Bool, x y : T.
*)
Example typing_nonexample_1 :
~ exists T,
empty |-
(tabs x TBool
(tabs y TBool
(tapp (tvar x) (tvar y)))) \in
T.
Proof.
intros Hc. inversion Hc.
(* The [clear] tactic is useful here for tidying away bits of
the context that we're not going to need again. *)
inversion H. subst. clear H.
inversion H5. subst. clear H5.
inversion H4. subst. clear H4.
inversion H2. subst. clear H2.
inversion H5. subst. clear H5.
(* rewrite extend_neq in H1. rewrite extend_eq in H1. *)
inversion H1. Qed.
(** **** Exercise: 3 stars, optional (typing_nonexample_3) *)
(** Another nonexample:
~ (exists S, exists T,
empty |- \x:S. x x : T).
*)
Lemma no_infinite_nested_type :
~ (exists T, exists S, T = TArrow T S).
Proof.
intros Hc. inversion Hc as [T H]. clear Hc. induction T.
Case "TBool". inversion H. inversion H0.
Case "TArrow". inversion H as [S' H1]. inversion H1. apply IHT1. exists T2. assumption.
Qed.
Example typing_nonexample_3 :
~ (exists S, exists T,
empty |-
(tabs x S
(tapp (tvar x) (tvar x))) \in
T).
Proof.
intros Hc. inversion Hc as [S H]. clear Hc.
inversion H as [T H1]. subst.
inversion H1. subst. clear H1.
inversion H6. subst. clear H6.
inversion H3. subst. clear H3.
inversion H2. subst. inversion H5. subst. rewrite H2 in H3. inversion H3.
symmetry in H1. apply no_infinite_nested_type. exists T11. exists T12. assumption.
Qed.
(** [] *)
End STLC.
(* $Date: 2013-07-18 09:59:22 -0400 (Thu, 18 Jul 2013) $ *)
|
module SigmaDeltaFast_tb ();
parameter WIDTH = 4;
parameter OUTLEN = (1 << WIDTH);
// UUT Signals
reg clk; ///< System Clock
reg rst; ///< Reset, active high & synchronous
reg en; ///< Enable (use to clock at slower rate)
reg signed [WIDTH-1:0] in;
wire [OUTLEN-1:0] sdOut; ///< Sigma-delta output
// Testbench Signals
wire sdOutComp; ///< Sigma-delta value for comparison
wire [15:0] out; ///< Sinc^3 filtered version of sdOut
reg [OUTLEN-1:0] shiftReg;
integer i;
integer enCount;
always #1 clk = ~clk;
// Strobe every OUTLEN cycles
always @(posedge clk) begin
if (enCount == 0) begin
enCount = OUTLEN-1;
en = 1'b1;
shiftReg = sdOut;
end
else begin
enCount = enCount - 1;
en = 1'b0;
shiftReg = shiftReg >> 1;
end
end
initial begin
shiftReg = 32'hAAAA_AAAA;
enCount = 'd0;
clk = 1'b0;
rst = 1'b1;
en = 1'b0;
in = 'd0;
@(posedge clk) rst = 1'b1;
@(posedge clk) rst = 1'b1;
@(posedge clk) rst = 1'b0;
#10000 in = (2**(WIDTH-1))-1;
#10000 in = -(2**(WIDTH-1));
#10000 in = (2**(WIDTH-2));
#10000 in = -(2**(WIDTH-2));
#10000 in = 0;
for (i=0; i<2**18; i=i+1) begin
@(posedge en) in = $rtoi((2.0**(WIDTH-1)-1)*$sin(3.141259*2.0*($itor(i)/2.0**15 + $itor(i)**2/2.0**22)));
end
#10000 $stop();
end
SigmaDeltaFast #(
.WIDTH(WIDTH),
.OUTLEN(OUTLEN)
)
uut (
.clk(clk), ///< System clock
.rst(rst), ///< Reset, synchronous active high
.en(en), ///< Enable to run the modulator
.in(in), ///< [WIDTH-1:0] Input to modulator
.sdOut(sdOut) ///< [OUTLEN-1:0] Sigma delta stream, LSB=first sample, MSB=last sample
);
SigmaDelta1stOrder #(
.WIDTH(WIDTH)
)
comparison (
.clk(clk),
.rst(rst),
.en(1'b1),
.in(in), ///< [WIDTH-1:0]
.sdOut(sdOutComp)
);
Sinc3Filter #(
.OSR(32) // Output width is 3*ceil(log2(OSR))+1
)
filterOut (
.clk(clk),
.en(1'b1), ///< Enable (use to clock at slower rate)
.in(shiftReg[0]),
.out(out) ///< [3*$clog2(OSR):0]
);
endmodule
|
// Quartus Prime Verilog Template
// Single port RAM with single read/write address and initial contents
// specified with an initial block
module phyIniCommand0
#(parameter DATA_WIDTH=32, parameter ADDR_WIDTH=4)
(
input [(DATA_WIDTH-1):0] data,
input [(ADDR_WIDTH-1):0] addr,
input we, clk,
output [(DATA_WIDTH-1):0] q
);
// Declare the RAM variable
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0];
// Variable to hold the registered read address
reg [ADDR_WIDTH-1:0] addr_reg;
// Specify the initial contents. You can also use the $readmemb
// system task to initialize the RAM variable from a text file.
// See the $readmemb template page for details.
initial
begin : INIT
$readmemb("C:/altera/16.0/myProjects/PHYctrl_100Mbps/ram_init0.txt", ram);
end
always @ (posedge clk)
begin
// Write
if (we)
ram[addr] <= data;
addr_reg <= addr;
end
// Continuous assignment implies read returns NEW data.
// This is the natural behavior of the TriMatrix memory
// blocks in Single Port mode.
assign q = ram[addr_reg];
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
//////////////////////////////////////////////////////////////////////////////
//
// Description :
// Performs blending and logical operations under the control of the mc_de
// block on raw pixel data. Mc_de performs necessary memory read cycles to
// fill the mff and pops to the drawing engine to provide data for this block
// to operate on according to the blend_ctrl_data control bus. Mc_de also
// sets up memory write cycles so that the generated data can be written out
// to off-chip memory resources.
//
// Other Information:
// The blend_ctrl_data register is a packed control bus that contains a number
// of pieces of data and control for blending that is sent from the drawing
// engine with the request. Its format is as follows:
// blend_ctrl_data[1:0] de_pix: 00 8 bits per pixel color
// 01 16bpp 5-5-5 mode ??????????
// 10 16bpp 5-6-5 mode ??????????
// 11 32bpp
// blend_ctrl_data[3:2] de_bw:
//
// blend_ctrl_data[35:4] de_bwcolor:
//
// and on, and on...
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module mc_dat
#
(
parameter BYTES = 4
)
(
input mclock,
input reset_n,
input [66:0] blend_ctrl_data,
input mc_dat_pop,
input pipe_enable,
input [3:0] rc_dev_sel,
input [(BYTES*8)-1:0] hst_data,
input [(BYTES*8)-1:0] de_data,
input [(BYTES*4)-1:0] de_adata,
input [(BYTES*8)-1:0] de_zdata,
input [31:0] vga_data,
input [BYTES-1:0] hst_byte_mask,
input [BYTES-1:0] de_byte_mask,
input [BYTES-1:0] de_byte_zmask,
input [3:0] vga_wen,
input [(BYTES*8)-1:0] mff_data,
input rc_rd_sel,
input [4:0] z_data,
input unload_z,
input push_z,
input [(BYTES*8)-1:0] read_data,
output [(BYTES*8)-1:0] fb_data_out,
output [BYTES-1:0] fb_dqm,
output reg [31:0] kcol_rd, // key color
output reg [2:0] kcnt_rd, // keying control
output reg [1:0] pix
);
// states for constructing the correct comparisons
localparam NEVER = 3'b000,/* A win will never occur */
ALWAYS = 3'b001,/* A win shall always occur */
LESS = 3'b010,/* Win if new < old */
LEQUAL = 3'b011,/* Win if new <= old */
EQUAL = 3'b100,/* Win if new = old */
GEQUAL = 3'b101,/* Win if new >= old */
GREATER = 3'b110,/* Win if new > old */
NOTEQUAL= 3'b111;/* Win if new != old */
reg [3:0] bsrcr; // Source Blending Register
reg [2:0] bdstr; // Destination Blending Register
reg blend_en; // Blending Enabled
reg [7:0] bsrc_alpha; // Source Alpha register
reg [7:0] bdst_alpha; // Destination Alpha register
reg [3:0] rop; // Raster op select
reg [3:0] rop_i[5:0];// Raster op select pipelined
reg [1:0] pix_i[5:0];
reg [1:0] blend_en_pipe;
reg [(BYTES*8)-1:0] de_data_i;
reg [(BYTES*4)-1:0] de_adata_i;
reg [(BYTES*8)-1:0] de_zdata_i;
reg [(BYTES*8)-1:0] z_store_i;
reg [BYTES-1:0] de_byte_mask_i;
reg [BYTES-1:0] de_byte_zmask_i;
reg [BYTES-1:0] new_z_mask;
reg [(BYTES*8)-1:0] mff_data_i;
reg z_ro_i, z_en_i;
reg [2:0] z_op_i;
reg [2:0] z_pipe;
reg [(BYTES*8)-1:0] z_store;
reg bsrc_en, bdst_en; // source and dest blend reg en
// int loop0;
integer loop0;
// 09/10/2010 Bypass the pipe_enable register.
// (jmacleod)
always @* {kcol_rd, kcnt_rd} = blend_ctrl_data[35:1];
always @(posedge mclock) begin
if (pipe_enable) begin
// {pix, bsrcr, bdstr, bsrc_alpha, bdst_alpha, rop, kcol_rd, kcnt_rd,
// blend_en} <= blend_ctrl_data;
// 09/10/2010 Remove kcol_rd and kcnt_rd from the pipe_enable register.
// (jmacleod)
{pix, bsrcr, bdstr, bsrc_alpha, bdst_alpha, rop,
blend_en} <= {blend_ctrl_data[64:36], blend_ctrl_data[0]};
bsrc_en <= blend_ctrl_data[65];
bdst_en <= blend_ctrl_data[66];
rop_i[0] <= rop;
rop_i[1] <= rop_i[0];
rop_i[2] <= rop_i[1];
rop_i[3] <= rop_i[2];
rop_i[4] <= rop_i[3];
rop_i[5] <= rop_i[4];
pix_i[0] <= pix;
pix_i[1] <= pix_i[0];
pix_i[2] <= pix_i[1];
pix_i[3] <= pix_i[2];
pix_i[4] <= pix_i[3];
pix_i[5] <= pix_i[4];
z_pipe[0] <= unload_z;
z_pipe[1] <= z_pipe[0];
z_pipe[2] <= z_pipe[1];
blend_en_pipe <= {blend_en_pipe[0], blend_en};
de_data_i <= de_data;
de_adata_i <= de_adata;
de_zdata_i <= de_zdata;
z_op_i <= z_data[2:0];
z_en_i <= z_data[3];
z_ro_i <= z_data[4];
de_byte_mask_i <= de_byte_mask;
de_byte_zmask_i <= de_byte_zmask;
mff_data_i <= mff_data;
if(push_z) z_store <= read_data;
z_store_i <= z_store;
end
end
mc_datmsk #
(
.BYTES (BYTES)
) mc_datmsk
(
.mclock (mclock),
.mc_dat_pop (mc_dat_pop),
.pipe_enable (mc_dat_pop | pipe_enable),
.ifb_dev_sel (rc_dev_sel),
.hst_byte_mask (hst_byte_mask),
.vga_wen (vga_wen),
.de_byte_mask_fast (de_byte_mask),
.de_byte_mask (de_byte_mask_i),
.de_byte_zmask (de_byte_zmask_i),
.new_z_mask (new_z_mask),
.rc_rd_sel (rc_rd_sel),
.z_en (z_en_i),
.z_ro (z_ro_i),
.ram_dqm (fb_dqm)
);
wire [3:0] rop_i_2 = rop_i[2];
mc_dat16 mc_dat[(BYTES/2)-1:0]
(
.mclock (mclock),
.hst_data (hst_data),
.src_data (de_data_i),
.alpha_data (de_adata_i),
.dst_alpha ({{2{mff_data_i[127:120]}},
{2{mff_data_i[95:88]}},
{2{mff_data_i[63:56]}},
{2{mff_data_i[31:24]}}}),
.dst_data (mff_data_i),
.de_data (de_data),
.vga_data (vga_data[15:0]), // FIX_ME
// .vga_data ({4{vga_data}}),
.z_data (de_zdata_i),
.bsrc_alpha (bsrc_alpha),
.bdst_alpha (bdst_alpha),
.src_factor_select (bsrcr[2:0]),
.dst_factor_select (bdstr[2:0]),
.src_reg_en (bsrc_en),
.dst_reg_en (bdst_en),
.pix (pix), // pixel_format
.pix_2 (pix), // pixel_format
.blend_en (blend_en_pipe[1]),
.mc_dat_pop (mc_dat_pop),
.pipe_enable (mc_dat_pop | pipe_enable),
.ifb_dev_sel (rc_dev_sel),
.rop (rop), // raster_operation
.rop2 (rop_i_2), // Adec has a problem with this, rop_i[2]), // raster_operation
// Output.
.ram_data_out (fb_data_out)
);
// Z comparison
always @(posedge mclock)
if (z_pipe[1])
casex({pix_i[0], z_op_i})
{2'bxx, ALWAYS}: new_z_mask <= {BYTES{1'b0}};
// 16 BPP modes
{2'bx1, LESS}:
for (loop0 = 0; loop0 < BYTES/2; loop0 = loop0 + 1)
if (de_zdata_i[loop0*16+:16] < z_store_i[loop0*16+:16])
new_z_mask[loop0*2+:2] <= 2'b00;
else
new_z_mask[loop0*2+:2] <= 2'b11;
{2'bx1, LEQUAL}:
for (loop0 = 0; loop0 < BYTES/2; loop0 = loop0 + 1)
if (de_zdata_i[loop0*16+:16] <= z_store_i[loop0*16+:16])
new_z_mask[loop0*2+:2] <= 2'b00;
else
new_z_mask[loop0*2+:2] <= 2'b11;
{2'bx1, EQUAL}:
for (loop0 = 0; loop0 < BYTES/2; loop0 = loop0 + 1)
if (de_zdata_i[loop0*16+:16] == z_store_i[loop0*16+:16])
new_z_mask[loop0*2+:2] <= 2'b00;
else
new_z_mask[loop0*2+:2] <= 2'b11;
{2'bx1, GEQUAL}:
for (loop0 = 0; loop0 < BYTES/2; loop0 = loop0 + 1)
if (de_zdata_i[loop0*16+:16] >= z_store_i[loop0*16+:16])
new_z_mask[loop0*2+:2] <= 2'b00;
else
new_z_mask[loop0*2+:2] <= 2'b11;
{2'bx1, GREATER}:
for (loop0 = 0; loop0 < BYTES/2; loop0 = loop0 + 1)
if (de_zdata_i[loop0*16+:16] > z_store_i[loop0*16+:16])
new_z_mask[loop0*2+:2] <= 2'b00;
else
new_z_mask[loop0*2+:2] <= 2'b11;
{2'bx1, NOTEQUAL}:
for (loop0 = 0; loop0 < BYTES/2; loop0 = loop0 + 1)
if (de_zdata_i[loop0*16+:16] != z_store_i[loop0*16+:16])
new_z_mask[loop0*2+:2] <= 2'b00;
else
new_z_mask[loop0*2+:2] <= 2'b11;
// 32 bit Z.
{2'b10, LESS}:
for (loop0 = 0; loop0 < BYTES/4; loop0 = loop0 + 1)
if (de_zdata_i[loop0*32+:32] < z_store_i[loop0*32+:32])
new_z_mask[loop0*4+:4] <= 4'b0000;
else
new_z_mask[loop0*4+:4] <= 4'b1111;
{2'b10, LEQUAL}:
for (loop0 = 0; loop0 < BYTES/4; loop0 = loop0 + 1)
if (de_zdata_i[loop0*32+:32] <= z_store_i[loop0*32+:32])
new_z_mask[loop0*4+:4] <= 4'b0000;
else
new_z_mask[loop0*4+:4] <= 4'b1111;
{2'b10, EQUAL}:
for (loop0 = 0; loop0 < BYTES/4; loop0 = loop0 + 1)
if (de_zdata_i[loop0*32+:32] == z_store_i[loop0*32+:32])
new_z_mask[loop0*4+:4] <= 4'b0000;
else
new_z_mask[loop0*4+:4] <= 4'b1111;
{2'b10, GEQUAL}:
for (loop0 = 0; loop0 < BYTES/4; loop0 = loop0 + 1)
if (de_zdata_i[loop0*32+:32] >= z_store_i[loop0*32+:32])
new_z_mask[loop0*4+:4] <= 4'b0000;
else
new_z_mask[loop0*4+:4] <= 4'b1111;
{2'b10, GREATER}:
for (loop0 = 0; loop0 < BYTES/4; loop0 = loop0 + 1)
if (de_zdata_i[loop0*32+:32] > z_store_i[loop0*32+:32])
new_z_mask[loop0*4+:4] <= 4'b0000;
else
new_z_mask[loop0*4+:4] <= 4'b1111;
{2'b10, NOTEQUAL}:
for (loop0 = 0; loop0 < BYTES/4; loop0 = loop0 + 1)
if (de_zdata_i[loop0*32+:32] != z_store_i[loop0*32+:32])
new_z_mask[loop0*4+:4] <= 4'b0000;
else
new_z_mask[loop0*4+:4] <= 4'b1111;
default: new_z_mask <= {BYTES{1'b1}};
endcase // casex ({pix_i[0], z_op_i})
endmodule
|
// -*- verilog -*-
// Copyright (c) 2012 Ben Reynwar
// Released under MIT License (see LICENSE.txt)
// A qa_wrapper with a splitter and message_stream_combiner
module qa_wrapper
#(
parameter WDTH = 32
)
(
input wire clk,
input wire reset,
input wire [WDTH-1:0] in_data,
input wire in_nd,
output reg [WDTH-1:0] out_data,
output reg out_nd
);
// Separate the input stream into a sample stream and a message stream.
wire [WDTH-1:0] mid1_data;
wire [WDTH-1:0] mid2_data;
wire [WDTH-1:0] staged_data;
wire staged_nd;
wire mid_nd;
wire splitter_error;
wire rst_n;
assign rst_n = ~reset;
split #(2, 1) split_0
(.clk(clk),
.rst_n(rst_n),
.in_data(in_data),
.in_nd(in_nd),
.out_data({mid1_data, mid2_data}),
.out_nd(mid_nd)
);
message_stream_combiner
#(2, 1, WDTH, `COMBINER_BUFFER_LENGTH, `LOG_COMBINER_BUFFER_LENGTH,
`MAX_PACKET_LENGTH, `MSG_LENGTH_WIDTH)
message_stream_combiner_0
(.clk(clk),
.rst_n(rst_n),
.in_data({mid1_data, mid2_data}),
.in_nd({mid_nd, mid_nd}),
.out_data(staged_data),
.out_nd(staged_nd),
.error(combiner_error)
);
always @ (posedge clk)
begin
if (combiner_error)
begin
out_nd <= 1'b1;
out_data <= `ERRORCODE;
end
else
begin
out_nd <= staged_nd;
out_data <= staged_data;
end
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A41OI_4_V
`define SKY130_FD_SC_LS__A41OI_4_V
/**
* a41oi: 4-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3 & A4) | B1)
*
* Verilog wrapper for a41oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__a41oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a41oi_4 (
Y ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__a41oi_4 (
Y ,
A1,
A2,
A3,
A4,
B1
);
output Y ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__a41oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.A4(A4),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__A41OI_4_V
|
`timescale 1ns / 1ps
module Approx_adder
#(parameter W=26, parameter LowL=16) (
input wire add_sub,
input wire [W-1:0] in1,
input wire [W-1:0] in2,
output wire [W:0] res
);
wire [W-1:0] in2_signed;
wire [LowL-1:0] lower_res;
wire approx_cout;
`ifdef ACAIN16Q4
assign in2_signed = (add_sub) ? ~in2 : in2;
ACA_I_N16_Q4 ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif ETAIIN16Q4
assign in2_signed = (add_sub) ? ~in2 : in2;
ETAII_N16_Q4 ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif ETAIIN16Q8
assign in2_signed = (add_sub) ? ~in2 : in2;
ETAII_N16_Q8 ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif ACAIIN16Q4
assign in2_signed = (add_sub) ? ~in2 : in2;
ACA_II_N16_Q4 ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif ACAIIN16Q8
assign in2_signed = (add_sub) ? ~in2 : in2;
ACA_II_N16_Q8 ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif GDAN16M4P4
assign in2_signed = (add_sub) ? ~in2 : in2;
GDA_St_N16_M4_P4 ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif GDAN16M4P8
assign in2_signed = (add_sub) ? ~in2 : in2;
GDA_St_N16_M4_P8 ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif GeArN16R2P4
assign in2_signed = (add_sub) ? ~in2 : in2;
GeAr_N16_R2_P4 ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif GeArN16R4P4
assign in2_signed = (add_sub) ? ~in2 : in2;
GeAr_N16_R4_P4 ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif GeArN16R4P8
assign in2_signed = (add_sub) ? ~in2 : in2;
GeAr_N16_R4_P8 ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif LOALPL4
assign in2_signed = (add_sub) ? ~in2 : in2;
LOA #(.LPL(4), .W(16)) ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif LOALPL5
assign in2_signed = (add_sub) ? ~in2 : in2;
LOA #(.LPL(5), .W(16)) ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif LOALPL6
assign in2_signed = (add_sub) ? ~in2 : in2;
LOA #(.LPL(6), .W(16)) ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif LOALPL7
assign in2_signed = (add_sub) ? ~in2 : in2;
LOA #(.LPL(7), .W(16)) ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif LOALPL8
assign in2_signed = (add_sub) ? ~in2 : in2;
LOA #(.LPL(8), .W(16)) ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif LOALPL9
assign in2_signed = (add_sub) ? ~in2 : in2;
LOA #(.LPL(9), .W(16)) ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif LOALPL10
assign in2_signed = (add_sub) ? ~in2 : in2;
LOA #(.LPL(10), .W(16)) ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif LOALPL11
assign in2_signed = (add_sub) ? ~in2 : in2;
LOA #(.LPL(11), .W(16)) ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif LOALPL12
assign in2_signed = (add_sub) ? ~in2 : in2;
LOA #(.LPL(12), .W(16)) ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif LOALPL13
assign in2_signed = (add_sub) ? ~in2 : in2;
LOA #(.LPL(13), .W(16)) ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`elsif GeArN16R6P4
assign in2_signed = (add_sub) ? ~in2 : in2;
GeAr_N16_R6_P4 ApproxAdd (.in1(in1[LowL-1:0]), .in2(in2_signed[LowL-1:0]), .res({approx_cout,lower_res}));
always @* begin : ADD_SUB_SGF
res = {(in1[W-1:LowL] + in2_signed[W-1:LowL] + approx_cout),lower_res};
end
`else
assign res = (add_sub) ? (in1 - in2) : (in1 + in2);
`endif
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: flop_rptrs_xb3.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module flop_rptrs_xb3(/*AUTOARG*/
// Outputs
sparc_out, so, jbussync2_out, jbussync1_out, grst_out,
gdbginit_out, ddrsync2_out, ddrsync1_out, cken_out,
// Inputs
spare_in, se, sd, jbussync2_in, jbussync1_in, grst_in,
gdbginit_in, gclk, ddrsync2_in, ddrsync1_in, cken_in, agrst_l,
adbginit_l
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [25:0] cken_out; // From cken_ff_25_ of bw_u1_soffasr_2x.v, ...
output ddrsync1_out; // From ddrsync1_ff of bw_u1_soffasr_2x.v
output ddrsync2_out; // From ddrsync2_ff of bw_u1_soffasr_2x.v
output gdbginit_out; // From gdbginit_ff of bw_u1_soffasr_2x.v
output grst_out; // From gclk_ff of bw_u1_soffasr_2x.v
output jbussync1_out; // From jbussync1_ff of bw_u1_soffasr_2x.v
output jbussync2_out; // From jbussync2_ff of bw_u1_soffasr_2x.v
output so; // From scanout_latch of bw_u1_scanlg_2x.v
output [5:0] sparc_out; // From spare_ff_5_ of bw_u1_soffasr_2x.v, ...
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input adbginit_l; // To gdbginit_ff of bw_u1_soffasr_2x.v
input agrst_l; // To spare_ff_5_ of bw_u1_soffasr_2x.v, ...
input [25:0] cken_in; // To cken_ff_25_ of bw_u1_soffasr_2x.v, ...
input ddrsync1_in; // To ddrsync1_ff of bw_u1_soffasr_2x.v
input ddrsync2_in; // To ddrsync2_ff of bw_u1_soffasr_2x.v
input gclk; // To I73 of bw_u1_ckbuf_33x.v
input gdbginit_in; // To gdbginit_ff of bw_u1_soffasr_2x.v
input grst_in; // To gclk_ff of bw_u1_soffasr_2x.v
input jbussync1_in; // To jbussync1_ff of bw_u1_soffasr_2x.v
input jbussync2_in; // To jbussync2_ff of bw_u1_soffasr_2x.v
input sd; // To spare_ff_5_ of bw_u1_soffasr_2x.v
input se; // To spare_ff_5_ of bw_u1_soffasr_2x.v, ...
input [5:0] spare_in; // To spare_ff_5_ of bw_u1_soffasr_2x.v, ...
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire clk; // From I73 of bw_u1_ckbuf_33x.v
wire scan_data_0; // From spare_ff_5_ of bw_u1_soffasr_2x.v
wire scan_data_1; // From spare_ff_4_ of bw_u1_soffasr_2x.v
wire scan_data_10; // From gdbginit_ff of bw_u1_soffasr_2x.v
wire scan_data_11; // From gclk_ff of bw_u1_soffasr_2x.v
wire scan_data_2; // From spare_ff_3_ of bw_u1_soffasr_2x.v
wire scan_data_3; // From spare_ff_2_ of bw_u1_soffasr_2x.v
wire scan_data_4; // From spare_ff_1_ of bw_u1_soffasr_2x.v
wire scan_data_5; // From spare_ff_0_ of bw_u1_soffasr_2x.v
wire scan_data_6; // From jbussync2_ff of bw_u1_soffasr_2x.v
wire scan_data_7; // From jbussync1_ff of bw_u1_soffasr_2x.v
wire scan_data_8; // From ddrsync2_ff of bw_u1_soffasr_2x.v
wire scan_data_9; // From ddrsync1_ff of bw_u1_soffasr_2x.v
// End of automatics
/* bw_u1_ckbuf_33x AUTO_TEMPLATE (
.clk (clk ),
.rclk (gclk ) ); */
bw_u1_ckbuf_33x I73
(/*AUTOINST*/
// Outputs
.clk (clk ), // Templated
// Inputs
.rclk (gclk )); // Templated
/* bw_u1_soffasr_2x AUTO_TEMPLATE (
.q (sparc_out[@]),
.d (spare_in[@]),
.ck (clk ),
.r_l (agrst_l ),
.s_l (1'b1),
.sd (scan_data_@"(- 4 @)" ),
.so (scan_data_@"(- 5 @)" ),
); */
bw_u1_soffasr_2x spare_ff_5_
(
// Inputs
.sd (sd ),
/*AUTOINST*/
// Outputs
.q (sparc_out[5]), // Templated
.so (scan_data_0 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[5]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se));
bw_u1_soffasr_2x spare_ff_4_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[4]), // Templated
.so (scan_data_1 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[4]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_0 )); // Templated
bw_u1_soffasr_2x spare_ff_3_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[3]), // Templated
.so (scan_data_2 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[3]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_1 )); // Templated
bw_u1_soffasr_2x spare_ff_2_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[2]), // Templated
.so (scan_data_3 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[2]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_2 )); // Templated
bw_u1_soffasr_2x spare_ff_1_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[1]), // Templated
.so (scan_data_4 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[1]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_3 )); // Templated
bw_u1_soffasr_2x spare_ff_0_
(
/*AUTOINST*/
// Outputs
.q (sparc_out[0]), // Templated
.so (scan_data_5 ), // Templated
// Inputs
.ck (clk ), // Templated
.d (spare_in[0]), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se),
.sd (scan_data_4 )); // Templated
/* bw_u1_soffasr_2x AUTO_TEMPLATE (
.q (cken_out[@] ),
.d (cken_in[@] ),
.ck (clk ),
.r_l (agrst_l ),
.s_l (1'b1),
.se (1'b0),
.sd (1'b0),
.so (),
); */
bw_u1_soffasr_2x cken_ff_25_
( /*AUTOINST*/
// Outputs
.q (cken_out[25] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[25] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_24_
( /*AUTOINST*/
// Outputs
.q (cken_out[24] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[24] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_23_
( /*AUTOINST*/
// Outputs
.q (cken_out[23] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[23] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_22_
( /*AUTOINST*/
// Outputs
.q (cken_out[22] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[22] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_21_
( /*AUTOINST*/
// Outputs
.q (cken_out[21] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[21] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_20_
( /*AUTOINST*/
// Outputs
.q (cken_out[20] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[20] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_19_
( /*AUTOINST*/
// Outputs
.q (cken_out[19] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[19] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_18_
( /*AUTOINST*/
// Outputs
.q (cken_out[18] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[18] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_17_
( /*AUTOINST*/
// Outputs
.q (cken_out[17] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[17] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_16_
( /*AUTOINST*/
// Outputs
.q (cken_out[16] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[16] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_15_
( /*AUTOINST*/
// Outputs
.q (cken_out[15] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[15] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_14_
( /*AUTOINST*/
// Outputs
.q (cken_out[14] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[14] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_13_
( /*AUTOINST*/
// Outputs
.q (cken_out[13] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[13] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_12_
( /*AUTOINST*/
// Outputs
.q (cken_out[12] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[12] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_11_
( /*AUTOINST*/
// Outputs
.q (cken_out[11] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[11] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_10_
( /*AUTOINST*/
// Outputs
.q (cken_out[10] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[10] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_9_
( /*AUTOINST*/
// Outputs
.q (cken_out[9] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[9] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_8_
( /*AUTOINST*/
// Outputs
.q (cken_out[8] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[8] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_7_
( /*AUTOINST*/
// Outputs
.q (cken_out[7] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[7] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_6_
( /*AUTOINST*/
// Outputs
.q (cken_out[6] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[6] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_5_
( /*AUTOINST*/
// Outputs
.q (cken_out[5] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[5] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_4_
( /*AUTOINST*/
// Outputs
.q (cken_out[4] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[4] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_3_
( /*AUTOINST*/
// Outputs
.q (cken_out[3] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[3] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_2_
( /*AUTOINST*/
// Outputs
.q (cken_out[2] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[2] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_1_
( /*AUTOINST*/
// Outputs
.q (cken_out[1] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[1] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
bw_u1_soffasr_2x cken_ff_0_
( /*AUTOINST*/
// Outputs
.q (cken_out[0] ), // Templated
.so (), // Templated
// Inputs
.ck (clk ), // Templated
.d (cken_in[0] ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (1'b0), // Templated
.sd (1'b0)); // Templated
/* bw_u1_soffasr_2x AUTO_TEMPLATE (
.ck (clk ),
.r_l (agrst_l ),
.s_l (1'b1),
.se (se ),
); */
bw_u1_soffasr_2x ddrsync1_ff
(
// Outputs
.q (ddrsync1_out ),
.so (scan_data_9 ),
// Inputs
.d (ddrsync1_in ),
.sd (scan_data_8 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x ddrsync2_ff
(
// Outputs
.q (ddrsync2_out ),
.so (scan_data_8 ),
// Inputs
.d (ddrsync2_in ),
.sd (scan_data_7 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x jbussync1_ff
(
// Outputs
.q (jbussync1_out ),
.so (scan_data_7 ),
// Inputs
.d (jbussync1_in ),
.sd (scan_data_6 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x jbussync2_ff
(
// Outputs
.q (jbussync2_out ),
.so (scan_data_6 ),
// Inputs
.d (jbussync2_in ),
.sd (scan_data_5 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x gdbginit_ff
(
// Outputs
.q (gdbginit_out ),
.so (scan_data_10 ),
// Inputs
.d (gdbginit_in ),
.sd (scan_data_9 ),
.r_l (adbginit_l),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
bw_u1_soffasr_2x gclk_ff
(
// Outputs
.q (grst_out ),
.so (scan_data_11 ),
// Inputs
.d (grst_in ),
.sd (scan_data_10 ),
/*AUTOINST*/
// Inputs
.ck (clk ), // Templated
.r_l (agrst_l ), // Templated
.s_l (1'b1), // Templated
.se (se )); // Templated
/* bw_u1_scanlg_2x AUTO_TEMPLATE (
.sd (scan_data_11 ),
.ck (clk ),
); */
bw_u1_scanlg_2x scanout_latch
( /*AUTOINST*/
// Outputs
.so (so),
// Inputs
.sd (scan_data_11 ), // Templated
.ck (clk ), // Templated
.se (1'b1));
endmodule
// Local Variables:
// verilog-library-files:("../../../common/rtl/u1.behV" )
// End:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFXBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__SDFXBP_FUNCTIONAL_PP_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sdfxbp (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ms__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFXBP_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_1_V
`define SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_1_V
/**
* lsbuflv2hv_symmetric: Level shifting buffer, Low Voltage to High
* Voltage, Symmetrical.
*
* Verilog wrapper for lsbuflv2hv_symmetric with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__lsbuflv2hv_symmetric.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1 (
X ,
A ,
VPWR ,
VGND ,
LVPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input LVPWR;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__lsbuflv2hv_symmetric base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.LVPWR(LVPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__lsbuflv2hv_symmetric_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 LVPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__lsbuflv2hv_symmetric base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFLV2HV_SYMMETRIC_1_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:26:43 12/10/2012
// Design Name: spim
// Module Name: E:/Documents/FPGA/SPIloop/tb_spim.v
// Project Name: SPIloop
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: spim
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_spim;
// Inputs
reg clk;
reg rst;
reg [7:0] din;
reg wen;
reg wdiv;
// Outputs
wire rdy;
wire SCLK;
wire MOSI;
wire SSbar;
// Instantiate the Unit Under Test (UUT)
spim uut (
.clk(clk),
.rst(rst),
.din(din),
.wen(wen),
.wdiv(wdiv),
.rdy(rdy),
.SCLK(SCLK),
.MOSI(MOSI),
.SSbar(SSbar)
);
initial begin
// Initialize Inputs
clk = 0;
rst = 0;
din = 0;
wen = 0;
wdiv = 0;
// Wait 100 ns for global reset to finish
rst = 1;
#100;
rst = 0;
// Add stimulus here
din = 0;
wdiv = 1;
#40;
wdiv = 0;
#40;
din = 8'h55;
wen = 1;
#40;
wen = 0;
#5000;
din = 8'h45;
wen = 1;
#40;
wen = 0;
end
always begin
#20 clk = ~clk;
end
endmodule
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: dec_table.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dec_table (
address,
clock,
q);
input [7:0] address;
input clock;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({32{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "dec_table.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 256,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 8,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "dec_table.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "dec_table.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL dec_table.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dec_table.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dec_table.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dec_table.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL dec_table_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL dec_table_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
(* -*- coding: utf-8 -*- *)
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2016 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** * Typeclass-based morphism definition and standard, minimal instances
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - University Paris Sud
*)
Require Import Coq.Program.Basics.
Require Import Coq.Program.Tactics.
Require Export Coq.Classes.CRelationClasses.
Generalizable Variables A eqA B C D R RA RB RC m f x y.
Local Obligation Tactic := simpl_crelation.
Set Universe Polymorphism.
Notation hrel A B := (A -> B -> Type).
(** * Morphisms.
We now turn Mto the definition of [Proper] and declare standard instances.
These will be used by the [setoid_rewrite] tactic later. *)
(** A morphism for a relation [R] is a proper element of the relation.
The relation [R] will be instantiated by [respectful] and [A] by an arrow
type for usual morphisms. *)
Class Related {A : Type} {A' : Type} (R : hrel A A') (m : A) (m' : A') :=
related_prf : R m m'.
Notation Proper R m := (Related R m m).
Section Proper.
Context {A : Type}.
(** Every element in the carrier of a reflexive relation is a morphism
for this relation. We use a proxy class for this case which is used
internally to discharge reflexivity constraints. The [Reflexive]
instance will almost always be used, but it won't apply in general to
any kind of [Proper (A -> B) _ _] goal, making proof-search much
slower. A cleaner solution would be to be able to set different
priorities in different hint bases and select a particular hint
database for resolution of a type class constraint. *)
Lemma eq_proper_proxy (x : A) : Proper (@eq A) x.
Proof. firstorder. Qed.
Lemma reflexive_proper_proxy `(Reflexive A R) (x : A) : Proper R x.
Proof. firstorder. Qed.
(** Respectful morphisms. *)
(** The fully dependent version, not used yet. *)
Definition respectful_hetero
(A B : Type)
(C : A -> Type) (D : B -> Type)
(R : hrel A B)
(R' : forall (x : A) (y : B), R x y -> hrel (C x) (D y)) :
hrel (forall x : A, C x) (forall x : B, D x) :=
fun f g => forall x y (X : R x y), R' x y X (f x) (g y).
(** The non-dependent, homogeneous version is an instance
where we forget dependencies. *)
Definition respectful {A' B B'} (R : hrel A A') (R' : hrel B B') : hrel (A -> B) (A' -> B') :=
Eval compute in @respectful_hetero A A' (fun _ => B) (fun _ => B') R (fun _ _ _ => R').
End Proper.
(** We favor the use of Leibniz equality or a declared reflexive crelation
when resolving [Proper], otherwise, if the crelation is given (not an evar),
we fall back to [Proper]. *)
Hint Extern 1 (Proper _ _) =>
class_apply @eq_proper_proxy ||
class_apply @reflexive_proper_proxy : typeclass_instances.
(** Notations reminiscent of the old syntax for declaring morphisms. *)
Delimit Scope signature_scope with signature.
Arguments respectful_hetero {_ _ _ _ _} R'%signature _ _.
Arguments respectful {A A' B B'}%type (R R')%signature _ _.
Module ProperNotations.
Notation " R ++> R' " := (@respectful _ _ _ _ (R%signature) (R'%signature))
(right associativity, at level 55) : signature_scope.
Notation " R ==> R' " := (@respectful _ _ _ _ (R%signature) (R'%signature))
(right associativity, at level 55) : signature_scope.
Notation " R --> R' " := (@respectful _ _ _ _ (flip (R%signature)) (R'%signature))
(right associativity, at level 55) : signature_scope.
Notation "∀ α : R v1 v2 , S" :=
(respectful_hetero (R := R) (fun v1 v2 α => S))
(at level 200, α ident, R at level 7, v1 ident, v2 ident, right associativity)
: signature_scope.
Notation "∀ α : R , S" := (respectful_hetero (R := R) (fun _ _ α => S))
(at level 200, α ident, R at level 7, right associativity)
: signature_scope.
Notation "∀ α , R" := (respectful_hetero (fun _ _ α => R))
(at level 200, α ident, right associativity)
: signature_scope.
End ProperNotations.
Export ProperNotations.
Local Open Scope signature_scope.
(** [solve_proper] try to solve the goal [Proper (?==> ... ==>?) f]
by repeated introductions and setoid rewrites. It should work
fine when [f] is a combination of already known morphisms and
quantifiers. *)
Ltac solve_respectful t :=
match goal with
| |- respectful _ _ _ _ =>
let H := fresh "H" in
intros ? ? H; solve_respectful ltac:(setoid_rewrite H; t)
| _ => t; reflexivity
end.
Ltac solve_proper := unfold Proper; solve_respectful ltac:(idtac).
(** [f_equiv] is a clone of [f_equal] that handles setoid equivalences.
For example, if we know that [f] is a morphism for [E1==>E2==>E],
then the goal [E (f x y) (f x' y')] will be transformed by [f_equiv]
into the subgoals [E1 x x'] and [E2 y y'].
*)
Ltac f_equiv :=
match goal with
| |- ?R (?f ?x) (?f' _) =>
let T := type of x in
let Rx := fresh "R" in
evar (Rx : crelation T);
let H := fresh in
assert (H : (Rx==>R)%signature f f');
unfold Rx in *; clear Rx; [ f_equiv | apply H; clear H; try reflexivity ]
| |- ?R ?f ?f' =>
solve [change (Proper R f); eauto with typeclass_instances | reflexivity ]
| _ => idtac
end.
Section Relations.
Context {A : Type}.
(** [forall_def] reifies the dependent product as a definition. *)
Definition forall_def (P : A -> Type) : Type := forall x : A, P x.
(** Dependent pointwise lifting of a crelation on the range. *)
Definition forall_relation (P : A -> Type)
(sig : forall a, crelation (P a)) : crelation (forall x, P x) :=
fun f g => forall a, sig a (f a) (g a).
(** Non-dependent pointwise lifting *)
Definition pointwise_relation {B} (R : crelation B) : crelation (A -> B) :=
fun f g => forall a, R (f a) (g a).
Lemma pointwise_pointwise {B} (R : crelation B) :
relation_equivalence (pointwise_relation R) (@eq A ==> R).
Proof. intros. split. simpl_crelation. firstorder. Qed.
(** Subcrelations induce a morphism on the identity. *)
Global Instance subrelation_id_proper `(subrelation A RA RA') : Proper (RA ==> RA') id.
Proof. firstorder. Qed.
(** The subrelation property goes through products as usual. *)
Lemma subrelation_respectful `(subl : subrelation A RA' RA, subr : subrelation B RB RB') :
subrelation (RA ==> RB) (RA' ==> RB').
Proof. simpl_crelation. Qed.
(** And of course it is reflexive. *)
Lemma subrelation_refl R : @subrelation A R R.
Proof. simpl_crelation. Qed.
(** [Proper] is itself a covariant morphism for [subrelation].
We use an unconvertible premise to avoid looping.
*)
Lemma subrelation_proper `(mor : Proper R' m)
`(unc : Unconvertible (crelation A) R R')
`(sub : subrelation A R' R) : Proper R m.
Proof.
intros. apply sub. apply mor.
Qed.
Global Instance proper_subrelation_proper_arrow :
Proper (subrelation ++> eq ==> eq ==> arrow) (@Related A A).
Proof. reduce. subst. firstorder. Qed.
Global Instance pointwise_subrelation `(sub : subrelation B R R') :
subrelation (pointwise_relation R) (pointwise_relation R') | 4.
Proof. reduce. unfold pointwise_relation in *. apply sub. auto. Qed.
(** For dependent function types. *)
Lemma forall_subrelation (P : A -> Type) (R S : forall x : A, crelation (P x)) :
(forall a, subrelation (R a) (S a)) ->
subrelation (forall_relation P R) (forall_relation P S).
Proof. reduce. firstorder. Qed.
End Relations.
Typeclasses Opaque respectful pointwise_relation forall_relation.
Arguments forall_relation {A P}%type sig%signature _ _.
Arguments pointwise_relation A%type {B}%type R%signature _ _.
Hint Unfold Reflexive : core.
Hint Unfold Symmetric : core.
Hint Unfold Transitive : core.
(** Resolution with subrelation: favor decomposing products over applying reflexivity
for unconstrained goals. *)
Ltac subrelation_tac T U :=
(is_ground T ; is_ground U ; class_apply @subrelation_refl) ||
class_apply @subrelation_respectful || class_apply @subrelation_refl.
Hint Extern 3 (@subrelation _ ?T ?U) => subrelation_tac T U : typeclass_instances.
CoInductive apply_subrelation : Prop := do_subrelation.
Ltac proper_subrelation :=
match goal with
[ H : apply_subrelation |- _ ] => clear H ; class_apply @subrelation_proper
end.
Hint Extern 5 (@Proper _ ?H _) => proper_subrelation : typeclass_instances.
(** Essential subrelation instances for [iff], [impl] and [pointwise_relation]. *)
Instance iff_impl_subrelation : subrelation iff impl | 2.
Proof. firstorder. Qed.
Instance iff_flip_impl_subrelation : subrelation iff (flip impl) | 2.
Proof. firstorder. Qed.
(** Essential subrelation instances for [iffT] and [arrow]. *)
Instance iffT_arrow_subrelation : subrelation iffT arrow | 2.
Proof. firstorder. Qed.
Instance iffT_flip_arrow_subrelation : subrelation iffT (flip arrow) | 2.
Proof. firstorder. Qed.
(** We use an extern hint to help unification. *)
Hint Extern 4 (subrelation (@forall_relation ?A ?B ?R) (@forall_relation _ _ ?S)) =>
apply (@forall_subrelation A B R S) ; intro : typeclass_instances.
Arguments transitivity {A R Transitive x} y {z} _ _.
Section GenericInstances.
(* Share universes *)
Implicit Types A B C : Type.
(** We can build a PER on the Coq function space if we have PERs on the domain and
codomain. *)
Program Instance respectful_per `(PER A R, PER B R') : PER (R ==> R').
Next Obligation.
Proof with auto.
assert(R x0 x0).
apply (transitivity y0)...
apply symmetry...
apply (transitivity (y x0))...
Qed.
(** The complement of a crelation conserves its proper elements. *)
(** The [flip] too, actually the [flip] instance is a bit more general. *)
Program Definition flip_proper A B C (RA : crelation A) (RB : crelation B)
(RC : crelation C)
`(mor : Proper (RA ==> RB ==> RC) f) :
Proper (RB ==> RA ==> RC) (flip f) := _.
Next Obligation.
Proof.
apply mor ; auto.
Qed.
(** Every Transitive crelation gives rise to a binary morphism on [impl],
contravariant in the first argument, covariant in the second. *)
Global Program
Instance trans_contra_co_type_morphism
`(Transitive A R) : Proper (R --> R ++> arrow) R.
Next Obligation.
Proof with auto.
apply (transitivity x)...
apply (transitivity x0)...
Qed.
(** Proper declarations for partial applications. *)
Global Program
Instance trans_contra_inv_impl_type_morphism
`(Transitive A R) : Proper (R --> flip arrow) (R x) | 3.
Next Obligation.
Proof with eauto.
eapply transitivity...
Qed.
Global Program
Instance trans_co_impl_type_morphism
`(Transitive A R) : Proper (R ++> arrow) (R x) | 3.
Next Obligation.
Proof with eauto.
eapply transitivity...
Qed.
Global Program
Instance trans_sym_co_inv_impl_type_morphism
`(PER A R) : Proper (R ++> flip arrow) (R x) | 3.
Next Obligation.
Proof with auto.
apply (transitivity y)... apply symmetry...
Qed.
Global Program Instance trans_sym_contra_arrow_morphism
`(PER A R) : Proper (R --> arrow) (R x) | 3.
Next Obligation.
Proof with eauto.
eapply transitivity... eapply symmetry...
Qed.
Global Program Instance per_partial_app_type_morphism
`(PER A R) : Proper (R ==> iffT) (R x) | 2.
Next Obligation.
Proof with auto.
split. intros ; apply (transitivity x0)...
intros.
apply (transitivity y)...
apply symmetry...
Qed.
(** Every Transitive crelation induces a morphism by "pushing" an [R x y] on the left of an [R x z] proof to get an [R y z] goal. *)
Global Program
Instance trans_co_eq_inv_arrow_morphism
`(Transitive A R) : Proper (R ==> (@eq A) ==> flip arrow) R | 2.
Next Obligation.
Proof with auto.
apply (transitivity y)...
Qed.
(** Every Symmetric and Transitive crelation gives rise to an equivariant morphism. *)
Global Program
Instance PER_type_morphism `(PER A R) : Proper (R ==> R ==> iffT) R | 1.
Next Obligation.
Proof with eauto.
split ; intros.
eapply transitivity... eapply transitivity... eapply symmetry...
eapply transitivity... eapply transitivity... eapply symmetry...
Qed.
Lemma symmetric_equiv_flip `(Symmetric A R) : relation_equivalence R (flip R).
Proof. firstorder. Qed.
Global Program Instance compose_proper A B C RA RB RC :
Proper ((RB ==> RC) ==> (RA ==> RB) ==> (RA ==> RC)) (@compose A B C).
Next Obligation.
Proof.
simpl_crelation.
unfold compose. firstorder.
Qed.
(** Coq functions are morphisms for Leibniz equality,
applied only if really needed. *)
Global Instance reflexive_eq_dom_reflexive `(Reflexive B R') :
Reflexive (@Logic.eq A ==> R').
Proof. simpl_crelation. Qed.
(** [respectful] is a morphism for crelation equivalence . *)
Global Instance respectful_morphism :
Proper (relation_equivalence ++> relation_equivalence ++> relation_equivalence)
(@respectful A A B B).
Proof.
intros A B R R' HRR' S S' HSS' f g.
unfold respectful , relation_equivalence in *; simpl in *.
split ; intros H x y Hxy.
apply (fst (HSS' _ _)). apply H. now apply (snd (HRR' _ _)).
apply (snd (HSS' _ _)). apply H. now apply (fst (HRR' _ _)).
Qed.
(** [R] is Reflexive, hence we can build the needed proof. *)
Lemma Reflexive_partial_app_morphism A A' (R : crelation A) (R' : crelation A')
`(Proper (R ==> R') m, Proper R x) :
Proper R' (m x).
Proof. simpl_crelation. Qed.
Class Params {A} (of : A) (arity : nat).
Lemma flip_respectful {A B} (R : crelation A) (R' : crelation B) :
relation_equivalence (flip (R ==> R')) (flip R ==> flip R').
Proof.
intros.
unfold flip, respectful.
split ; intros ; intuition.
Qed.
(** Treating flip: can't make them direct instances as we
need at least a [flip] present in the goal. *)
Lemma flip1 `(subrelation A R' R) : subrelation (flip (flip R')) R.
Proof. firstorder. Qed.
Lemma flip2 `(subrelation A R R') : subrelation R (flip (flip R')).
Proof. firstorder. Qed.
(** That's if and only if *)
Lemma eq_subrelation `(Reflexive A R) : subrelation (@eq A) R.
Proof. simpl_crelation. Qed.
(** Once we have normalized, we will apply this instance to simplify the problem. *)
Definition proper_flip_proper A (R : crelation A) `(mor : Proper R m) :
Proper (flip R) m := mor.
End GenericInstances.
Class PartialApplication.
CoInductive normalization_done : Prop := did_normalization.
Ltac partial_application_tactic :=
let rec do_partial_apps H m cont :=
match m with
| ?m' ?x => class_apply @Reflexive_partial_app_morphism ;
[(do_partial_apps H m' ltac:(idtac))|clear H]
| _ => cont
end
in
let rec do_partial H ar m :=
match ar with
| 0%nat => do_partial_apps H m ltac:(fail 1)
| S ?n' =>
match m with
?m' ?x => do_partial H n' m'
end
end
in
let params m sk fk :=
(let m' := fresh in head_of_constr m' m ;
let n := fresh in evar (n:nat) ;
let v := eval compute in n in clear n ;
let H := fresh in
assert(H:Params m' v) by typeclasses eauto ;
let v' := eval compute in v in subst m';
(sk H v' || fail 1))
|| fk
in
let on_morphism m cont :=
params m ltac:(fun H n => do_partial H n m)
ltac:(cont)
in
match goal with
| [ _ : normalization_done |- _ ] => fail 1
| [ _ : @Params _ _ _ |- _ ] => fail 1
| [ |- @Proper ?T _ (?m ?x) ] =>
match goal with
| [ H : PartialApplication |- _ ] =>
class_apply @Reflexive_partial_app_morphism; [|clear H]
| _ => on_morphism (m x)
ltac:(class_apply @Reflexive_partial_app_morphism)
end
end.
(** Bootstrap !!! *)
(* Instance proper_proper : Proper (relation_equivalence ==> eq ==> iffT) (@Proper A). *)
(* Proof. *)
(* intros A R R' HRR' x y <-. red in HRR'. *)
(* split ; red ; intros. *)
(* now apply (fst (HRR' _ _)). *)
(* now apply (snd (HRR' _ _)). *)
(* Qed. *)
(* Ltac proper_reflexive := *)
(* match goal with *)
(* | [ _ : normalization_done |- _ ] => fail 1 *)
(* | _ => class_apply proper_eq || class_apply @reflexive_proper *)
(* end. *)
(* Hint Extern 7 (@Proper _ _ _) => proper_reflexive *)
(* : typeclass_instances. *)
Hint Extern 1 (subrelation (flip _) _) => class_apply @flip1 : typeclass_instances.
Hint Extern 1 (subrelation _ (flip _)) => class_apply @flip2 : typeclass_instances.
(* Hint Extern 1 (Proper _ (complement _)) => apply @complement_proper *)
(* : typeclass_instances. *)
Hint Extern 1 (Proper _ (flip _)) => apply @flip_proper
: typeclass_instances.
Hint Extern 2 (@Proper _ (flip _) _) => class_apply @proper_flip_proper
: typeclass_instances.
Hint Extern 4 (@Proper _ _ _) => partial_application_tactic
: typeclass_instances.
(** Related goals *)
Lemma related_app A (R : crelation A) B (S : crelation B) f f' a a' :
Related (R ==> S)%signature f f' -> Related R a a' ->
Related S (f a) (f' a').
Proof. intros H; intros H'. apply H. apply H'. Defined.
Hint Extern 1 (Related ?S (?f ?a) (?f' ?a')) =>
once match goal with
| [ H : Related ?R ?a ?a' |- _ ] => eapply (@related_app _ R _ S f f' a a'); [|apply H]
| _ => eapply (@related_app _ _ _ S f f' a a')
end : typeclass_instances.
Hint Extern 0 (Related _ _ _) =>
match goal with
|- let _ := _ in _ => let hyp := fresh in intros hyp
end : typeclass_instances.
(** Special-purpose class to do normalization of signatures w.r.t. flip. *)
Section Normalize.
Context (A : Type).
Class Normalizes (m : crelation A) (m' : crelation A) :=
normalizes : relation_equivalence m m'.
(** Current strategy: add [flip] everywhere and reduce using [subrelation]
afterwards. *)
Lemma proper_normalizes_proper `(Normalizes R0 R1, Proper R1 m) : Proper R0 m.
Proof.
red in H, Proper0.
apply H. assumption.
Qed.
Lemma flip_atom R : Normalizes R (flip (flip R)).
Proof.
firstorder.
Qed.
End Normalize.
Lemma flip_arrow {A : Type} {B : Type}
`(NA : Normalizes A R (flip R'''), NB : Normalizes B R' (flip R'')) :
Normalizes (A -> B) (R ==> R') (flip (R''' ==> R'')%signature).
Proof.
(* FIXME should be a rewrite *)
unfold Normalizes in *. intros.
unfold relation_equivalence in *.
unfold iffT in *. simpl in *.
unfold respectful. unfold flip in *.
intros; split; intros.
apply NB. apply X. apply NA. apply X0.
apply NB. apply X. apply NA. apply X0.
Qed.
Ltac normalizes :=
match goal with
| [ |- Normalizes _ (respectful _ _) _ ] => class_apply @flip_arrow
| _ => class_apply @flip_atom
end.
Ltac proper_normalization :=
match goal with
| [ _ : normalization_done |- _ ] => fail 1
| [ _ : apply_subrelation |- @Proper _ ?R _ ] =>
let H := fresh "H" in
set(H:=did_normalization) ; class_apply @proper_normalizes_proper
end.
Hint Extern 1 (Normalizes _ _ _) => normalizes : typeclass_instances.
Hint Extern 6 (@Proper _ _ _) => proper_normalization
: typeclass_instances.
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:10:35 12/16/2015
// Design Name: uart2_tx
// Module Name: H:/Firmware/font5_base_new/font5_base/font5-firmware/uart2_tb.v
// Project Name: font5_base
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: uart2_tx
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module uart2_tb;
// Inputs
reg reset;
reg clk;
reg ld_tx_data;
reg [7:0] tx_data;
reg tx_enable;
// Outputs
wire tx_out;
wire tx_empty;
// Instantiate the Unit Under Test (UUT)
uart2_tx uut (
.reset(reset),
.clk(clk),
.ld_tx_data(ld_tx_data),
.tx_data(tx_data),
.tx_enable(tx_enable),
.tx_out(tx_out),
.tx_empty(tx_empty)
);
initial begin
// Initialize Inputs
reset = 0;
clk = 0;
ld_tx_data = 0;
tx_data = 0;
tx_enable = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21A_2_V
`define SKY130_FD_SC_HD__O21A_2_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog wrapper for o21a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o21a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21a_2 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21a_2 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21A_2_V
|
// bsg_nonsynth_dpi_from_fifo: A FIFO Interface for receiving FIFO data
// in C/C++ via DPI.
//
// Parameters:
//
// width_p: is the bit-width of the FIFO interface. Must be a power
// of 2 and divisible by 8, i.e. a ctype.
//
// debug_p: is the intial value to set on debug_o and to control
// debug messages. The debug() DPI function can be used to control
// messages at runtime, but this allows it to be set in the
// initial block, before any runtime functions can be called.
//
// Functions:
//
// bsg_dpi_init(): Initialize this FIFO DPI Interface. Init must be
// called before any other function
//
// bsg_dpi_debug(input bit): Enable or disable BSG DBGINFO messages
// from this module and set the debug_o output bit.
//
// bsg_dpi_width(): Return the bit-width of data_i
//
// bsg_dpi_fini(): De-Initialize this FIFO DPI Interface. This must
// be called before $finish is called in the testbench.
//
// bsg_dpi_fifo_rx(output bit [width_p-1:0] data_o): Receive width_p
// bits from the FIFO interface through the data_o argument. If
// data is available, yumi_o will be set to 1 before the next
// positive edge of clk_i and this method will return 1. If data
// is not available, this method will return 0 and yumi_o will be
// set to 0 before the next negative edge.
//
// bsg_dpi_fifo_rx() CAN ONLY be called after the positive edge of
// clk_i is evaluated.
//
// bsg_dpi_fifo_rx() CAN ONLY be called only once per cycle.
//
// Violating any of these constraints this will cause $fatal to be
// called to indicate a protocol violation.
//
// For safe operation of this interface use the bsg_nonsynth_dpi_from_fifo
// class provided in bsg_nonsynth_fifo.hpp header.
`include "bsg_defines.v"
module bsg_nonsynth_dpi_from_fifo
#(
parameter `BSG_INV_PARAM(width_p )
,parameter bit debug_p = 0
)
(
input clk_i
, input reset_i
, input v_i
, input [width_p-1:0] data_i
, output logic yumi_o
, output bit debug_o);
// This bit tracks whether initialize has been called. If data is
// sent and recieved before init() is called, then this module will
// call $fatal
bit init_r = 0;
// This bit checks whether bsg_dpi_fifo_rx() has been called multiple
// times in a cycle.
bit rx_r = 0;
// Check if width_p is a ctype width. call $fatal, if not.
if (!(width_p == 32'd8 || width_p == 32'd16 || width_p == 32'd32 || width_p == 32'd64 || width_p == 32'd128)) begin
$fatal(1, "BSG ERROR (%M): width_p of %d is not supported. Must be a power of 2 and divisible by 8", width_p);
end
// Print module parameters to the console and set the intial debug
// value.
initial begin
debug_o = debug_p;
$display("BSG INFO: bsg_nonsynth_dpi_from_fifo (initial begin)");
$display("BSG INFO: Instantiation: %M");
$display("BSG INFO: width_p = %d", width_p);
$display("BSG INFO: debug_p = %d", debug_p);
end
// This checks that fini was called before $finish
final begin
if (init_r === 1)
$fatal(1, "BSG ERROR (%M): fini() was not called before $finish");
end
export "DPI-C" function bsg_dpi_init;
export "DPI-C" function bsg_dpi_fini;
export "DPI-C" function bsg_dpi_debug;
export "DPI-C" function bsg_dpi_width;
export "DPI-C" function bsg_dpi_fifo_rx;
export "DPI-C" function bsg_dpi_fifo_is_window;
// Set or unset the debug_o output bit. If a state change occurs
// (0->1 or 1->0) then module will print DEBUG ENABLED / DEBUG
// DISABLED. No messages are printed if a state change does not
// occur.
function void bsg_dpi_debug(input bit switch_i);
if(!debug_o & switch_i)
$display("BSG DBGINFO (%M@%t): DEBUG ENABLED", $time);
else if (debug_o & !switch_i)
$display("BSG DBGINFO (%M@%t): DEBUG DISABLED", $time);
debug_o = switch_i;
endfunction
// Silly, but useful.
function int bsg_dpi_width();
return width_p;
endfunction
// Initialize this FIFO DPI Interface
function void bsg_dpi_init();
if(debug_o)
$display("BSG DBGINFO (%M@%t): bsg_dpi_init() called", $time);
if(init_r)
$fatal(1, "BSG ERROR (%M): bsg_dpi_init() already called");
init_r = 1;
endfunction
// Terminate this FIFO DPI Interface
function void bsg_dpi_fini();
if(debug_o)
$display("BSG DBGINFO (%M@%t): bsg_dpi_fini() called", $time);
if(~init_r)
$fatal(1, "BSG ERROR (%M): bsg_dpi_fini() already called");
init_r = 0;
endfunction
// bsg_dpi_fifo_rx(output bit [width_p-1:0] data_o) -- Set ready_i and
// read data_i from the FIFO interface. When valid data is
// available (v_i === 1) this function will return 1. When there is
// no valid data available, this function will return 0.
//
// bsg_dpi_fifo_rx() MUST be called after the positive edge of clk_i is
// evaluated. It MUST be called only once per cycle. Failure will
// cause an error and a call to $fatal.
//
// We set yumi_o_n so that we can signal a read to the producer on
// the NEXT positive edge without reading multiple times
logic yumi_o_n;
// We track the "last" v_i and last yumi_o values to detect
// protocol violations. These are captured on the positive edge of
// the clock
reg v_i_r;
reg yumi_o_r;
// We track the polarity of the current edge so that we can notify
// the user of incorrect behavior.
reg edgepol;
always @(posedge clk_i or negedge clk_i) begin
edgepol <= clk_i;
end
function bit bsg_dpi_fifo_rx(output bit [width_p-1:0] data_bo);
if(init_r === 0) begin
$fatal(1,"BSG ERROR (%M): bsg_dpi_fifo_rx() called before init()");
end
if(reset_i === 1) begin
$fatal(1, "BSG ERROR (%M): bsg_dpi_fifo_rx() called while reset_i === 1");
end
if(clk_i === 0) begin
$fatal(1, "BSG ERROR (%M): bsg_dpi_fifo_rx() must be called when clk_i == 1");
end
if(rx_r !== 0) begin
$fatal(1, "BSG ERROR (%M): bsg_dpi_fifo_rx() called multiple times in a clk_i cycle");
end
if(edgepol === 0) begin
$fatal(1, "BSG ERROR (%M): bsg_dpi_fifo_rx() must be called after the positive edge of clk_i has been evaluated");
end
// This will flow to its output on the next negative clock edge.
yumi_o_n = v_i;
data_bo = data_i;
rx_r = 1;
if(debug_o)
$display("BSG DBGINFO (%M@%t): bsg_dpi_fifo_rx() called -- v_i: %b data_i: 0x%x",
$time, v_i, data_i);
return (v_i === 1);
endfunction
// The function bsg_dpi returns true if the interface is in a
// valid time-window to call bsg_dpi_fifo_rx()
function bit bsg_dpi_fifo_is_window();
return (~rx_r & clk_i & edgepol & ~reset_i);
endfunction
// We set yumi_o to 0 on the positive edge of clk_i (after it has
// been seen by the producer) so that we don't trigger negedge
// protocol assertions in the BSG FIFOs. We also need to reset
// yumi_o to 0 after data has been read to ensure that we don't
// "latch" yumi_o ===1 and unintentionally read multiple cycles in
// a row.
//
// To ensure that the correct yumi_o value is read on a positive
// clock edge, we set yumi_o_n ("next yumi") in bsg_dpi_fifo_rx() and
// propogate it to yumi_o on the negative clock edge. The producer
// will see the correct value of yumi_o on the next positive edge.
//
// We also set yumi_o on the negative edge to ensure that it
// changes after the BSG FIFO protocol assertions have
// passed. After yumi_o_n has been read, we pre-emptively set it
// back to 0. If bsg_dpi_fifo_rx() is called again on the next cycle, it
// will set yumi_o_n === 1 to read.
always @ (posedge clk_i or negedge clk_i) begin
if(clk_i)
yumi_o <= 0;
else
yumi_o <= yumi_o_n;
yumi_o_n = '0;
end
// Save the last v_i and yumi_o values for protocol checking
always @(posedge clk_i) begin
v_i_r <= v_i;
yumi_o_r <= yumi_o;
rx_r = 0;
if(debug_o)
$display("BSG DBGINFO (%M@%t): posedge clk_i -- reset_i: %b v_i: %b yumi_o: %b data_i: 0x%x",
$time, reset_i, v_i, yumi_o, data_i);
end
endmodule // bsg_nonsynth_dpi_from_fifo
`BSG_ABSTRACT_MODULE(bsg_nonsynth_dpi_from_fifo)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A21OI_4_V
`define SKY130_FD_SC_HD__A21OI_4_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog wrapper for a21oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a21oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a21oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a21oi_4 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A21OI_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A31O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__A31O_FUNCTIONAL_PP_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a31o (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A31O_FUNCTIONAL_PP_V |
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 00:24:56 05/08/2016
// Design Name:
// Module Name: control_enable_options
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module control_enable_options(
input wire clk,
input wire rst_n,
input wire [7:0] zxuno_addr,
input wire zxuno_regrd,
input wire zxuno_regwr,
input wire [7:0] din,
output reg [7:0] dout,
output reg oe_n,
output wire disable_ay,
output wire disable_turboay,
output wire disable_7ffd,
output wire disable_1ffd,
output wire disable_romsel7f,
output wire disable_romsel1f,
output wire enable_timexmmu,
output wire disable_spisd,
output wire disable_timexscr,
output wire disable_ulaplus,
output wire disable_radas
);
parameter DEVOPTIONS = 8'h0E;
parameter DEVOPTS2 = 8'h0F;
reg [7:0] devoptions = 8'h00; // initial value
reg [7:0] devopts2 = 8'h00; // initial value
assign disable_ay = devoptions[0];
assign disable_turboay = devoptions[1];
assign disable_7ffd = devoptions[2];
assign disable_1ffd = devoptions[3];
assign disable_romsel7f = devoptions[4];
assign disable_romsel1f = devoptions[5];
assign enable_timexmmu = devoptions[6];
assign disable_spisd = devoptions[7];
assign disable_timexscr = devopts2[0];
assign disable_ulaplus = devopts2[1];
assign disable_radas = devopts2[2];
always @(posedge clk) begin
if (rst_n == 1'b0) begin
devoptions <= 8'h00; // or after a hardware reset (not implemented yet)
devopts2 <= 8'h00;
end
else if (zxuno_addr == DEVOPTIONS && zxuno_regwr == 1'b1)
devoptions <= din;
else if (zxuno_addr == DEVOPTS2 && zxuno_regwr == 1'b1)
devopts2 <= din;
end
always @* begin
oe_n = 1'b1;
dout = 8'hFF;
if (zxuno_regrd == 1'b1)
if (zxuno_addr == DEVOPTIONS) begin
oe_n = 1'b0;
dout = devoptions;
end
else if (zxuno_addr == DEVOPTS2) begin
oe_n = 1'b0;
dout = devopts2;
end
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Thu Nov 10 23:14:29 2016
/////////////////////////////////////////////////////////////
module SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
wire n2;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(n2) );
BUFX3TS U1 ( .A(n2), .Y(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_GATED_DW_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_FSM_Mult_Function ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
wire n2;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(n2) );
BUFX4TS U1 ( .A(n2), .Y(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_GATED_DW_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
wire n2;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(n2) );
BUFX4TS U1 ( .A(n2), .Y(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_GATED_DW_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W13 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
wire n2;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(n2) );
BUFX6TS U1 ( .A(n2), .Y(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_GATED_DW_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_GATED_DW_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_GATED_DW_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
wire n2;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(n2) );
BUFX6TS U1 ( .A(n2), .Y(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_GATED_DW_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_GATED_DW_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterMult_W9 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
wire n2;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(n2) );
BUFX4TS U1 ( .A(n2), .Y(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_GATED_DW_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W48 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
wire n2;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(n2) );
BUFX4TS U1 ( .A(n2), .Y(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_GATED_DW_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterMult_W24 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_GATED_DW_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W24 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_GATED_DW_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_GATED_DW_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
wire n2;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(n2) );
CLKBUFX3TS U1 ( .A(n2), .Y(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_GATED_DW_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterMult_W32_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
wire n2;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(n2) );
BUFX6TS U1 ( .A(n2), .Y(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_GATED_DW_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_GATED_DW_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
wire n2;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(n2) );
BUFX6TS U1 ( .A(n2), .Y(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_GATED_DW_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
wire n2;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(n2) );
BUFX3TS U1 ( .A(n2), .Y(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_GATED_DW_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_3 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
wire n2;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(n2) );
BUFX3TS U1 ( .A(n2), .Y(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_GATED_DW_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_GATED_DW_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_GATED_DW_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_3 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_GATED_DW_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_GATED_DW_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_6 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_GATED_DW_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_9 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_GATED_DW_1STAGE_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_FPU_Interface2_W32_EW8_SW23_SWR26_EWR5_1 ( CLK, EN,
ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
wire n2;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(n2) );
CLKBUFX2TS U1 ( .A(n2), .Y(ENCLK) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_GATED_DW_1STAGE_syn.sdf");
endmodule
module FPU_Interface2_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, begin_operation,
ack_operation, operation, region_flag, Data_1, Data_2, r_mode,
overflow_flag, underflow_flag, NaN_flag, operation_ready, op_result,
busy );
input [2:0] operation;
input [1:0] region_flag;
input [31:0] Data_1;
input [31:0] Data_2;
input [1:0] r_mode;
output [31:0] op_result;
input clk, rst, begin_operation, ack_operation;
output overflow_flag, underflow_flag, NaN_flag, operation_ready, busy;
wire NaN_reg, ready_add_subt, enab_cont_iter, underflow_flag_mult,
overflow_flag_addsubt, underflow_flag_addsubt,
FPSENCOS_fmtted_Result_31_, FPSENCOS_enab_d_ff4_Xn,
FPSENCOS_enab_d_ff4_Yn, FPSENCOS_d_ff3_sign_out,
FPSENCOS_d_ff1_operation_out, FPSENCOS_enab_d_ff5_data_out,
FPSENCOS_enab_RB3, FPSENCOS_enab_d_ff_RB1, FPSENCOS_enab_d_ff4_Zn,
FPMULT_FSM_selector_C, FPMULT_FSM_selector_A,
FPMULT_FSM_exp_operation_A_S, FPMULT_FSM_barrel_shifter_load,
FPMULT_FSM_final_result_load, FPMULT_FSM_adder_round_norm_load,
FPMULT_FSM_load_second_step, FPMULT_FSM_exp_operation_load_result,
FPMULT_FSM_first_phase_load, FPMULT_FSM_add_overflow_flag,
FPMULT_zero_flag, FPADDSUB_N60, FPADDSUB_N59, FPADDSUB_OP_FLAG_SFG,
FPADDSUB_SIGN_FLAG_SFG, FPADDSUB__19_net_, FPADDSUB_SIGN_FLAG_NRM,
FPADDSUB_SIGN_FLAG_SHT1SHT2, FPADDSUB_ADD_OVRFLW_NRM2,
FPADDSUB_OP_FLAG_SHT2, FPADDSUB_SIGN_FLAG_SHT2,
FPADDSUB_bit_shift_SHT2, FPADDSUB_left_right_SHT2, FPADDSUB__6_net_,
FPADDSUB_ADD_OVRFLW_NRM, FPADDSUB_OP_FLAG_SHT1,
FPADDSUB_SIGN_FLAG_SHT1, FPADDSUB_OP_FLAG_EXP, FPADDSUB_SIGN_FLAG_EXP,
FPADDSUB_Shift_reg_FLAGS_7_5, FPADDSUB_Shift_reg_FLAGS_7_6,
FPADDSUB_enable_Pipeline_input, FPSENCOS_ITER_CONT_N5,
FPSENCOS_ITER_CONT_N4, FPSENCOS_ITER_CONT_N3,
FPMULT_Exp_module_Overflow_flag_A, FPMULT_Exp_module_Overflow_A,
FPMULT_final_result_ieee_Module_Sign_S_mux,
FPSENCOS_d_ff5_data_out_net5038830,
FPADDSUB_FRMT_STAGE_DATAOUT_net5038542,
FPADDSUB_NRM_STAGE_Raw_mant_net5038578, FPSENCOS_reg_Z0_net5038830,
FPSENCOS_reg_val_muxZ_2stage_net5038830,
FPSENCOS_reg_shift_y_net5038830, FPSENCOS_d_ff4_Xn_net5038830,
FPSENCOS_d_ff4_Yn_net5038830, FPSENCOS_d_ff4_Zn_net5038830,
FPADDSUB_INPUT_STAGE_OPERANDY_net5038542,
FPADDSUB_EXP_STAGE_DMP_net5038596, FPADDSUB_SHT1_STAGE_DMP_net5038596,
FPADDSUB_SHT2_SHIFT_DATA_net5038578,
FPMULT_Exp_module_exp_result_m_net5038776,
FPMULT_Sgf_operation_finalreg_net5038758,
FPMULT_Barrel_Shifter_module_Output_Reg_net5038740,
FPMULT_Adder_M_Add_Subt_Result_net5038722,
FPMULT_Operands_load_reg_XMRegister_net5038794,
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net5038542, n30,
n106, n107, n679, n810, n813, n816, n819, n826, n829, n830, n834,
n842, n843, n844, n846, n848, n849, n850, n851, n852, n853, n854,
n855, n856, n857, n859, n860, n861, n862, n863, n864, n865, n874,
n875, mult_x_69_n779, mult_x_69_n771, mult_x_69_n770, mult_x_69_n769,
mult_x_69_n768, mult_x_69_n767, mult_x_69_n766, mult_x_69_n765,
mult_x_69_n764, mult_x_69_n763, mult_x_69_n762, mult_x_69_n761,
mult_x_69_n760, mult_x_69_n759, mult_x_69_n758, mult_x_69_n757,
mult_x_69_n756, mult_x_69_n755, mult_x_69_n753, mult_x_69_n752,
mult_x_69_n747, mult_x_69_n746, mult_x_69_n745, mult_x_69_n744,
mult_x_69_n743, mult_x_69_n742, mult_x_69_n741, mult_x_69_n740,
mult_x_69_n739, mult_x_69_n738, mult_x_69_n737, mult_x_69_n736,
mult_x_69_n735, mult_x_69_n734, mult_x_69_n733, mult_x_69_n732,
mult_x_69_n731, mult_x_69_n730, mult_x_69_n729, mult_x_69_n728,
mult_x_69_n726, mult_x_69_n725, mult_x_69_n717, mult_x_69_n716,
mult_x_69_n715, mult_x_69_n714, mult_x_69_n713, mult_x_69_n712,
mult_x_69_n711, mult_x_69_n710, mult_x_69_n709, mult_x_69_n708,
mult_x_69_n707, mult_x_69_n706, mult_x_69_n705, mult_x_69_n704,
mult_x_69_n703, mult_x_69_n702, mult_x_69_n701, mult_x_69_n699,
mult_x_69_n698, mult_x_69_n693, mult_x_69_n692, mult_x_69_n691,
mult_x_69_n690, mult_x_69_n689, mult_x_69_n688, mult_x_69_n687,
mult_x_69_n686, mult_x_69_n685, mult_x_69_n684, mult_x_69_n683,
mult_x_69_n682, mult_x_69_n681, mult_x_69_n680, mult_x_69_n679,
mult_x_69_n678, mult_x_69_n677, mult_x_69_n676, mult_x_69_n675,
mult_x_69_n674, mult_x_69_n672, mult_x_69_n671, mult_x_69_n663,
mult_x_69_n662, mult_x_69_n661, mult_x_69_n660, mult_x_69_n659,
mult_x_69_n658, mult_x_69_n657, mult_x_69_n656, mult_x_69_n655,
mult_x_69_n654, mult_x_69_n653, mult_x_69_n652, mult_x_69_n651,
mult_x_69_n650, mult_x_69_n649, mult_x_69_n648, mult_x_69_n647,
mult_x_69_n645, mult_x_69_n644, mult_x_69_n639, mult_x_69_n638,
mult_x_69_n637, mult_x_69_n636, mult_x_69_n635, mult_x_69_n634,
mult_x_69_n633, mult_x_69_n632, mult_x_69_n631, mult_x_69_n630,
mult_x_69_n629, mult_x_69_n628, mult_x_69_n627, mult_x_69_n626,
mult_x_69_n625, mult_x_69_n624, mult_x_69_n623, mult_x_69_n622,
mult_x_69_n621, mult_x_69_n620, mult_x_69_n618, mult_x_69_n617,
mult_x_69_n608, mult_x_69_n607, mult_x_69_n606, mult_x_69_n605,
mult_x_69_n602, mult_x_69_n601, mult_x_69_n600, mult_x_69_n599,
mult_x_69_n597, mult_x_69_n596, mult_x_69_n595, mult_x_69_n594,
mult_x_69_n593, mult_x_69_n474, mult_x_69_n472, mult_x_69_n471,
mult_x_69_n469, mult_x_69_n468, mult_x_69_n467, mult_x_69_n466,
mult_x_69_n464, mult_x_69_n463, mult_x_69_n462, mult_x_69_n461,
mult_x_69_n459, mult_x_69_n458, mult_x_69_n457, mult_x_69_n454,
mult_x_69_n452, mult_x_69_n451, mult_x_69_n450, mult_x_69_n447,
mult_x_69_n445, mult_x_69_n444, mult_x_69_n443, mult_x_69_n441,
mult_x_69_n440, mult_x_69_n439, mult_x_69_n438, mult_x_69_n437,
mult_x_69_n436, mult_x_69_n435, mult_x_69_n433, mult_x_69_n432,
mult_x_69_n431, mult_x_69_n430, mult_x_69_n429, mult_x_69_n428,
mult_x_69_n427, mult_x_69_n425, mult_x_69_n424, mult_x_69_n423,
mult_x_69_n422, mult_x_69_n421, mult_x_69_n420, mult_x_69_n419,
mult_x_69_n417, mult_x_69_n416, mult_x_69_n415, mult_x_69_n414,
mult_x_69_n413, mult_x_69_n412, mult_x_69_n409, mult_x_69_n407,
mult_x_69_n406, mult_x_69_n405, mult_x_69_n404, mult_x_69_n403,
mult_x_69_n402, mult_x_69_n399, mult_x_69_n397, mult_x_69_n396,
mult_x_69_n395, mult_x_69_n394, mult_x_69_n393, mult_x_69_n392,
mult_x_69_n390, mult_x_69_n389, mult_x_69_n388, mult_x_69_n387,
mult_x_69_n386, mult_x_69_n385, mult_x_69_n384, mult_x_69_n383,
mult_x_69_n382, mult_x_69_n381, mult_x_69_n379, mult_x_69_n378,
mult_x_69_n377, mult_x_69_n376, mult_x_69_n375, mult_x_69_n374,
mult_x_69_n373, mult_x_69_n372, mult_x_69_n371, mult_x_69_n370,
mult_x_69_n368, mult_x_69_n367, mult_x_69_n366, mult_x_69_n365,
mult_x_69_n364, mult_x_69_n363, mult_x_69_n362, mult_x_69_n361,
mult_x_69_n360, mult_x_69_n359, mult_x_69_n357, mult_x_69_n356,
mult_x_69_n355, mult_x_69_n354, mult_x_69_n353, mult_x_69_n352,
mult_x_69_n351, mult_x_69_n350, mult_x_69_n349, mult_x_69_n348,
mult_x_69_n346, mult_x_69_n345, mult_x_69_n344, mult_x_69_n343,
mult_x_69_n342, mult_x_69_n341, mult_x_69_n340, mult_x_69_n339,
mult_x_69_n338, mult_x_69_n337, mult_x_69_n336, mult_x_69_n335,
mult_x_69_n334, mult_x_69_n333, mult_x_69_n332, mult_x_69_n331,
mult_x_69_n330, mult_x_69_n329, mult_x_69_n328, mult_x_69_n327,
mult_x_69_n326, mult_x_69_n325, mult_x_69_n324, mult_x_69_n323,
mult_x_69_n322, mult_x_69_n321, mult_x_69_n320, mult_x_69_n319,
mult_x_69_n318, mult_x_69_n317, mult_x_69_n316, mult_x_69_n315,
mult_x_69_n314, mult_x_69_n313, mult_x_69_n312, mult_x_69_n311,
mult_x_69_n310, mult_x_69_n309, mult_x_69_n308, mult_x_69_n307,
mult_x_69_n306, mult_x_69_n305, mult_x_69_n304, mult_x_69_n303,
mult_x_69_n302, mult_x_69_n301, mult_x_69_n300, mult_x_69_n299,
mult_x_69_n298, mult_x_69_n297, mult_x_69_n296, mult_x_69_n295,
mult_x_69_n294, mult_x_69_n293, mult_x_69_n292, mult_x_69_n291,
mult_x_69_n290, mult_x_69_n289, mult_x_69_n288, mult_x_69_n287,
mult_x_69_n286, mult_x_69_n285, mult_x_69_n284, mult_x_69_n283,
mult_x_69_n281, mult_x_69_n280, mult_x_69_n279, mult_x_69_n278,
mult_x_69_n277, mult_x_69_n276, mult_x_69_n275, mult_x_69_n274,
mult_x_69_n273, mult_x_69_n271, mult_x_69_n270, mult_x_69_n269,
mult_x_69_n268, mult_x_69_n267, mult_x_69_n266, mult_x_69_n265,
mult_x_69_n264, mult_x_69_n263, mult_x_69_n262, mult_x_69_n261,
mult_x_69_n260, mult_x_69_n259, mult_x_69_n258, mult_x_69_n257,
mult_x_69_n256, mult_x_69_n255, mult_x_69_n254, mult_x_69_n252,
mult_x_69_n251, mult_x_69_n250, mult_x_69_n249, mult_x_69_n248,
mult_x_69_n247, mult_x_69_n246, mult_x_69_n245, mult_x_69_n243,
mult_x_69_n242, mult_x_69_n241, mult_x_69_n240, mult_x_69_n239,
mult_x_69_n238, mult_x_69_n237, mult_x_69_n236, mult_x_69_n235,
mult_x_69_n234, mult_x_69_n233, mult_x_69_n232, mult_x_69_n231,
mult_x_69_n230, mult_x_69_n229, mult_x_69_n228, mult_x_69_n226,
mult_x_69_n225, mult_x_69_n224, mult_x_69_n223, mult_x_69_n222,
mult_x_69_n221, mult_x_69_n219, mult_x_69_n218, mult_x_69_n217,
mult_x_69_n216, mult_x_69_n215, mult_x_69_n214, mult_x_69_n213,
mult_x_69_n212, mult_x_69_n211, mult_x_69_n210, mult_x_69_n209,
mult_x_69_n208, mult_x_69_n206, mult_x_69_n204, mult_x_69_n203,
mult_x_69_n202, mult_x_69_n200, mult_x_69_n199, mult_x_69_n198,
mult_x_69_n197, mult_x_69_n196, mult_x_69_n195, mult_x_69_n194,
mult_x_69_n193, mult_x_69_n192, mult_x_69_n191, mult_x_69_n189,
mult_x_69_n188, mult_x_69_n187, mult_x_69_n185, mult_x_69_n184,
mult_x_69_n183, mult_x_69_n182, mult_x_69_n181, mult_x_69_n180,
DP_OP_26J196_122_5882_n18, DP_OP_26J196_122_5882_n17,
DP_OP_26J196_122_5882_n16, DP_OP_26J196_122_5882_n15,
DP_OP_26J196_122_5882_n14, DP_OP_26J196_122_5882_n8,
DP_OP_26J196_122_5882_n7, DP_OP_26J196_122_5882_n6,
DP_OP_26J196_122_5882_n5, DP_OP_26J196_122_5882_n4,
DP_OP_26J196_122_5882_n3, DP_OP_26J196_122_5882_n2,
DP_OP_26J196_122_5882_n1, DP_OP_230J196_125_7006_n22,
DP_OP_230J196_125_7006_n21, DP_OP_230J196_125_7006_n20,
DP_OP_230J196_125_7006_n19, DP_OP_230J196_125_7006_n18,
DP_OP_230J196_125_7006_n17, DP_OP_230J196_125_7006_n16,
DP_OP_230J196_125_7006_n15, DP_OP_230J196_125_7006_n9,
DP_OP_230J196_125_7006_n8, DP_OP_230J196_125_7006_n7,
DP_OP_230J196_125_7006_n6, DP_OP_230J196_125_7006_n5,
DP_OP_230J196_125_7006_n4, DP_OP_230J196_125_7006_n3,
DP_OP_230J196_125_7006_n2, DP_OP_230J196_125_7006_n1, n910, n911,
n912, n913, n914, n915, n916, n917, n918, n919, n920, n921, n922,
n923, n924, n925, n926, n927, n928, n929, n930, n931, n932, n933,
n934, n935, n936, n937, n938, n939, n940, n941, n942, n943, n944,
n945, n946, n947, n948, n949, n950, n951, n952, n953, n954, n955,
n956, n957, n958, n959, n960, n961, n962, n963, n964, n965, n966,
n967, n968, n969, n970, n971, n972, n973, n974, n975, n976, n977,
n978, n979, n980, n981, n982, n983, n984, n985, n986, n987, n988,
n989, n990, n991, n992, n993, n994, n995, n996, n997, n998, n999,
n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009,
n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019,
n1020, n1021, n1022, n1023, n1024, n1025, n1027, n1029, n1030, n1031,
n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040, n1041,
n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051,
n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060, n1061,
n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070, n1071,
n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080, n1081,
n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090, n1091,
n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100, n1101,
n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110, n1111,
n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120, n1121,
n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130, n1131,
n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140, n1141,
n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150, n1151,
n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160, n1161,
n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171,
n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180, n1181,
n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191,
n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201,
n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211,
n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221,
n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231,
n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241,
n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251,
n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261,
n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271,
n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281,
n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291,
n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301,
n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311,
n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321,
n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331,
n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341,
n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351,
n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361,
n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371,
n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381,
n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391,
n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401,
n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411,
n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421,
n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431,
n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441,
n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451,
n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461,
n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471,
n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481,
n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491,
n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501,
n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511,
n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521,
n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531,
n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541,
n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551,
n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561,
n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571,
n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581,
n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591,
n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601,
n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611,
n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621,
n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631,
n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641,
n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651,
n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661,
n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671,
n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681,
n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691,
n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701,
n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711,
n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721,
n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731,
n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741,
n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751,
n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761,
n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771,
n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781,
n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791,
n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801,
n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811,
n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821,
n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831,
n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841,
n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851,
n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861,
n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871,
n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881,
n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891,
n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901,
n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911,
n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921,
n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931,
n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941,
n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951,
n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961,
n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971,
n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981,
n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991,
n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001,
n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011,
n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021,
n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031,
n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041,
n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051,
n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061,
n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071,
n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081,
n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091,
n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101,
n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111,
n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121,
n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131,
n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141,
n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151,
n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160, n2161,
n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170, n2171,
n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180, n2181,
n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190, n2191,
n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200, n2201,
n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211,
n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221,
n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231,
n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241,
n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251,
n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261,
n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271,
n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281,
n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291,
n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301,
n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311,
n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321,
n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331,
n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341,
n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351,
n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361,
n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371,
n2372, n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381,
n2382, n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391,
n2392, n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401,
n2402, n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411,
n2412, n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421,
n2422, n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431,
n2432, n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441,
n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451,
n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461,
n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471,
n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481,
n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491,
n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501,
n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511,
n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521,
n2522, n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531,
n2532, n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541,
n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551,
n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561,
n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571,
n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581,
n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591,
n2592, n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601,
n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611,
n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621,
n2622, n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631,
n2632, n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641,
n2642, n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651,
n2652, n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661,
n2662, n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671,
n2672, n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681,
n2682, n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691,
n2692, n2693, n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701,
n2702, n2703, n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711,
n2712, n2713, n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721,
n2722, n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731,
n2732, n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741,
n2742, n2743, n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751,
n2752, n2753, n2754, n2755, n2756, n2757, n2758, n2759, n2760, n2761,
n2762, n2763, n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771,
n2772, n2773, n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781,
n2782, n2783, n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791,
n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801,
n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811,
n2812, n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821,
n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831,
n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841,
n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851,
n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861,
n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871,
n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881,
n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891,
n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901,
n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911,
n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921,
n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931,
n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941,
n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951,
n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961,
n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971,
n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981,
n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991,
n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001,
n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011,
n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021,
n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031,
n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041,
n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051,
n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061,
n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071,
n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081,
n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091,
n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101,
n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111,
n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121,
n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131,
n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141,
n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151,
n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161,
n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171,
n3172, n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181,
n3182, n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191,
n3192, n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201,
n3202, n3203, n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211,
n3212, n3213, n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221,
n3222, n3223, n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231,
n3232, n3233, n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241,
n3242, n3243, n3244, n3245, n3246, n3247, n3248, n3249, n3250, n3251,
n3252, n3253, n3254, n3255, n3256, n3257, n3258, n3259, n3260, n3261,
n3262, n3263, n3264, n3265, n3266, n3267, n3268, n3269, n3270, n3271,
n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280, n3281,
n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290, n3291,
n3292, n3293, n3294, n3295, n3296, n3297, n3298, n3299, n3300, n3301,
n3302, n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310, n3311,
n3312, n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3320, n3321,
n3322, n3323, n3324, n3325, n3326, n3327, n3328, n3329, n3330, n3331,
n3332, n3333, n3334, n3335, n3336, n3337, n3338, n3339, n3340, n3341,
n3342, n3343, n3344, n3345, n3346, n3347, n3348, n3349, n3350, n3351,
n3352, n3353, n3354, n3355, n3356, n3357, n3358, n3359, n3360, n3361,
n3362, n3363, n3364, n3365, n3366, n3367, n3368, n3369, n3370, n3371,
n3372, n3373, n3374, n3375, n3376, n3377, n3378, n3379, n3380, n3381,
n3382, n3383, n3384, n3385, n3386, n3387, n3388, n3389, n3390, n3391,
n3392, n3393, n3394, n3395, n3396, n3397, n3398, n3399, n3400, n3401,
n3402, n3403, n3404, n3406, n3407, n3408, n3409, n3410, n3411, n3412,
n3413, n3414, n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422,
n3423, n3424, n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432,
n3433, n3434, n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442,
n3443, n3444, n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452,
n3453, n3454, n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462,
n3463, n3464, n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472,
n3473, n3474, n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482,
n3483, n3484, n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492,
n3493, n3494, n3495, n3496, n3497, n3499, n3502, n3503, n3504, n3505,
n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513, n3514, n3515,
n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523, n3524, n3525,
n3526, n3527;
wire [1:0] operation_reg;
wire [31:23] dataA;
wire [31:23] dataB;
wire [31:0] add_subt_data1;
wire [30:0] add_subt_data2;
wire [31:0] cordic_result;
wire [31:0] result_add_subt;
wire [31:0] mult_result;
wire [30:0] FPSENCOS_mux_sal;
wire [27:0] FPSENCOS_d_ff3_LUT_out;
wire [31:0] FPSENCOS_d_ff3_sh_y_out;
wire [31:0] FPSENCOS_d_ff3_sh_x_out;
wire [25:4] FPSENCOS_data_out_LUT;
wire [7:0] FPSENCOS_sh_exp_y;
wire [7:0] FPSENCOS_sh_exp_x;
wire [31:0] FPSENCOS_d_ff2_Z;
wire [31:0] FPSENCOS_d_ff2_Y;
wire [31:0] FPSENCOS_d_ff2_X;
wire [31:0] FPSENCOS_first_mux_Z;
wire [31:0] FPSENCOS_d_ff_Zn;
wire [31:0] FPSENCOS_first_mux_Y;
wire [31:0] FPSENCOS_d_ff_Yn;
wire [31:0] FPSENCOS_first_mux_X;
wire [31:0] FPSENCOS_d_ff_Xn;
wire [31:0] FPSENCOS_d_ff1_Z;
wire [1:0] FPSENCOS_d_ff1_shift_region_flag_out;
wire [1:0] FPSENCOS_cont_var_out;
wire [3:0] FPSENCOS_cont_iter_out;
wire [22:0] FPMULT_Sgf_normalized_result;
wire [23:0] FPMULT_Add_result;
wire [8:0] FPMULT_S_Oper_A_exp;
wire [8:0] FPMULT_exp_oper_result;
wire [30:0] FPMULT_Op_MY;
wire [30:0] FPMULT_Op_MX;
wire [1:0] FPMULT_FSM_selector_B;
wire [47:23] FPMULT_P_Sgf;
wire [31:0] FPADDSUB_formatted_number_W;
wire [25:1] FPADDSUB_Raw_mant_SGF;
wire [25:2] FPADDSUB_DmP_mant_SFG_SWR;
wire [30:0] FPADDSUB_DMP_SFG;
wire [7:0] FPADDSUB_exp_rslt_NRM2_EW1;
wire [4:0] FPADDSUB_LZD_output_NRM2_EW;
wire [25:0] FPADDSUB_sftr_odat_SHT2_SWR;
wire [7:0] FPADDSUB_DMP_exp_NRM_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM2_EW;
wire [4:2] FPADDSUB_shift_value_SHT2_EWR;
wire [30:0] FPADDSUB_DMP_SHT2_EWSW;
wire [51:0] FPADDSUB_Data_array_SWR;
wire [25:0] FPADDSUB_Raw_mant_NRM_SWR;
wire [4:2] FPADDSUB_shft_value_mux_o_EWR;
wire [4:0] FPADDSUB_LZD_raw_out_EWR;
wire [4:0] FPADDSUB_Shift_amount_SHT1_EWR;
wire [22:0] FPADDSUB_DmP_mant_SHT1_SW;
wire [30:0] FPADDSUB_DMP_SHT1_EWSW;
wire [4:0] FPADDSUB_Shift_amount_EXP_EW;
wire [27:0] FPADDSUB_DmP_EXP_EWSW;
wire [30:0] FPADDSUB_DMP_EXP_EWSW;
wire [27:0] FPADDSUB_DmP_INIT_EWSW;
wire [30:0] FPADDSUB_DMP_INIT_EWSW;
wire [30:0] FPADDSUB_intDY_EWSW;
wire [31:2] FPADDSUB_intDX_EWSW;
wire [3:0] FPADDSUB_Shift_reg_FLAGS_7;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_next;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_reg;
wire [3:0] FPMULT_FS_Module_state_next;
wire [3:1] FPMULT_FS_Module_state_reg;
wire [8:0] FPMULT_Exp_module_Data_S;
wire [47:23] FPMULT_Sgf_operation_Result;
wire [24:1] FPMULT_Adder_M_result_A_adder;
wire [22:0] FPMULT_final_result_ieee_Module_Sgf_S_mux;
wire [7:0] FPMULT_final_result_ieee_Module_Exp_S_mux;
wire [1:0] FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg;
SNPS_CLOCK_GATE_HIGH_Up_counter_COUNTER_WIDTH4 FPSENCOS_ITER_CONT_clk_gate_temp_reg (
.CLK(n3480), .EN(enab_cont_iter), .ENCLK(n914), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_FSM_Mult_Function FPMULT_FS_Module_clk_gate_state_reg_reg (
.CLK(n3480), .EN(n846), .ENCLK(n911), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_ShiftRegister_W7 FPADDSUB_inst_ShiftRegister_clk_gate_Q_reg (
.CLK(n3480), .EN(n875), .ENCLK(n913), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W13 FPADDSUB_SFT2FRMT_STAGE_VARS_clk_gate_Q_reg (
.CLK(n3480), .EN(n1111), .ENCLK(n915), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_0 FPSENCOS_d_ff5_data_out_clk_gate_Q_reg (
.CLK(n3480), .EN(FPSENCOS_enab_d_ff5_data_out), .ENCLK(
FPSENCOS_d_ff5_data_out_net5038830), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_0 FPADDSUB_FRMT_STAGE_DATAOUT_clk_gate_Q_reg (
.CLK(n3480), .EN(FPADDSUB_Shift_reg_FLAGS_7[0]), .ENCLK(
FPADDSUB_FRMT_STAGE_DATAOUT_net5038542), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_0 FPADDSUB_SGF_STAGE_DMP_clk_gate_Q_reg (
.CLK(n3480), .EN(FPADDSUB__19_net_), .ENCLK(n912), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_0 FPADDSUB_NRM_STAGE_Raw_mant_clk_gate_Q_reg (
.CLK(n3480), .EN(FPADDSUB_Shift_reg_FLAGS_7[2]), .ENCLK(
FPADDSUB_NRM_STAGE_Raw_mant_net5038578), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_9 FPSENCOS_reg_Z0_clk_gate_Q_reg ( .CLK(
n1291), .EN(FPSENCOS_enab_d_ff_RB1), .ENCLK(FPSENCOS_reg_Z0_net5038830), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_6 FPSENCOS_reg_val_muxZ_2stage_clk_gate_Q_reg (
.CLK(n3485), .EN(FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]), .ENCLK(
FPSENCOS_reg_val_muxZ_2stage_net5038830), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_4 FPSENCOS_reg_shift_y_clk_gate_Q_reg (
.CLK(n1291), .EN(FPSENCOS_enab_RB3), .ENCLK(
FPSENCOS_reg_shift_y_net5038830), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_3 FPSENCOS_d_ff4_Xn_clk_gate_Q_reg (
.CLK(n3485), .EN(FPSENCOS_enab_d_ff4_Xn), .ENCLK(
FPSENCOS_d_ff4_Xn_net5038830), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_2 FPSENCOS_d_ff4_Yn_clk_gate_Q_reg (
.CLK(n3479), .EN(FPSENCOS_enab_d_ff4_Yn), .ENCLK(
FPSENCOS_d_ff4_Yn_net5038830), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_1 FPSENCOS_d_ff4_Zn_clk_gate_Q_reg (
.CLK(n3479), .EN(FPSENCOS_enab_d_ff4_Zn), .ENCLK(
FPSENCOS_d_ff4_Zn_net5038830), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_2 FPADDSUB_INPUT_STAGE_OPERANDY_clk_gate_Q_reg (
.CLK(n3481), .EN(FPADDSUB_enable_Pipeline_input), .ENCLK(
FPADDSUB_INPUT_STAGE_OPERANDY_net5038542), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_3 FPADDSUB_EXP_STAGE_DMP_clk_gate_Q_reg (
.CLK(n3479), .EN(FPADDSUB_Shift_reg_FLAGS_7_6), .ENCLK(
FPADDSUB_EXP_STAGE_DMP_net5038596), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_2 FPADDSUB_SHT1_STAGE_DMP_clk_gate_Q_reg (
.CLK(n3479), .EN(FPADDSUB_Shift_reg_FLAGS_7_5), .ENCLK(
FPADDSUB_SHT1_STAGE_DMP_net5038596), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_1 FPADDSUB_SHT2_STAGE_DMP_clk_gate_Q_reg (
.CLK(n3479), .EN(busy), .ENCLK(n917), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_0_2 FPADDSUB_SHT2_SHIFT_DATA_clk_gate_Q_reg (
.CLK(n3483), .EN(FPADDSUB__6_net_), .ENCLK(
FPADDSUB_SHT2_SHIFT_DATA_net5038578), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterMult_W9 FPMULT_Exp_module_exp_result_m_clk_gate_Q_reg (
.CLK(n3480), .EN(FPMULT_FSM_exp_operation_load_result), .ENCLK(
FPMULT_Exp_module_exp_result_m_net5038776), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W48 FPMULT_Sgf_operation_finalreg_clk_gate_Q_reg (
.CLK(n3483), .EN(FPMULT_FSM_load_second_step), .ENCLK(
FPMULT_Sgf_operation_finalreg_net5038758), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterMult_W24 FPMULT_Barrel_Shifter_module_Output_Reg_clk_gate_Q_reg (
.CLK(n3483), .EN(FPMULT_FSM_barrel_shifter_load), .ENCLK(
FPMULT_Barrel_Shifter_module_Output_Reg_net5038740), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W24 FPMULT_Adder_M_Add_Subt_Result_clk_gate_Q_reg (
.CLK(n3483), .EN(FPMULT_FSM_adder_round_norm_load), .ENCLK(
FPMULT_Adder_M_Add_Subt_Result_net5038722), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterMult_W32_0_1 FPMULT_Operands_load_reg_XMRegister_clk_gate_Q_reg (
.CLK(n3481), .EN(FPMULT_FSM_first_phase_load), .ENCLK(
FPMULT_Operands_load_reg_XMRegister_net5038794), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_1_1 FPMULT_final_result_ieee_Module_Final_Result_IEEE_clk_gate_Q_reg (
.CLK(n3481), .EN(FPMULT_FSM_final_result_load), .ENCLK(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net5038542), .TE(
1'b0) );
SNPS_CLOCK_GATE_HIGH_FPU_Interface2_W32_EW8_SW23_SWR26_EWR5_1 clk_gate_FPMULT_Exp_module_Underflow_m_Q_reg (
.CLK(n3485), .EN(n107), .ENCLK(n916), .TE(1'b0) );
CMPR42X1TS mult_x_69_U292 ( .A(mult_x_69_n471), .B(mult_x_69_n747), .C(
mult_x_69_n474), .D(mult_x_69_n771), .ICI(mult_x_69_n472), .S(
mult_x_69_n469), .ICO(mult_x_69_n467), .CO(mult_x_69_n468) );
CMPR42X1TS mult_x_69_U290 ( .A(mult_x_69_n746), .B(mult_x_69_n466), .C(
mult_x_69_n467), .D(mult_x_69_n770), .ICI(mult_x_69_n468), .S(
mult_x_69_n464), .ICO(mult_x_69_n462), .CO(mult_x_69_n463) );
CMPR42X1TS mult_x_69_U288 ( .A(mult_x_69_n745), .B(mult_x_69_n461), .C(
mult_x_69_n462), .D(mult_x_69_n769), .ICI(mult_x_69_n463), .S(
mult_x_69_n459), .ICO(mult_x_69_n457), .CO(mult_x_69_n458) );
CMPR42X1TS mult_x_69_U285 ( .A(mult_x_69_n744), .B(mult_x_69_n454), .C(
mult_x_69_n457), .D(mult_x_69_n768), .ICI(mult_x_69_n458), .S(
mult_x_69_n452), .ICO(mult_x_69_n450), .CO(mult_x_69_n451) );
CMPR42X1TS mult_x_69_U282 ( .A(mult_x_69_n743), .B(mult_x_69_n447), .C(
mult_x_69_n450), .D(mult_x_69_n767), .ICI(mult_x_69_n451), .S(
mult_x_69_n445), .ICO(mult_x_69_n443), .CO(mult_x_69_n444) );
CMPR42X1TS mult_x_69_U279 ( .A(mult_x_69_n742), .B(mult_x_69_n440), .C(
mult_x_69_n443), .D(mult_x_69_n766), .ICI(mult_x_69_n444), .S(
mult_x_69_n438), .ICO(mult_x_69_n436), .CO(mult_x_69_n437) );
CMPR42X1TS mult_x_69_U277 ( .A(mult_x_69_n435), .B(mult_x_69_n693), .C(
mult_x_69_n441), .D(mult_x_69_n717), .ICI(mult_x_69_n439), .S(
mult_x_69_n433), .ICO(mult_x_69_n431), .CO(mult_x_69_n432) );
CMPR42X1TS mult_x_69_U276 ( .A(mult_x_69_n741), .B(mult_x_69_n433), .C(
mult_x_69_n436), .D(mult_x_69_n765), .ICI(mult_x_69_n437), .S(
mult_x_69_n430), .ICO(mult_x_69_n428), .CO(mult_x_69_n429) );
CMPR42X1TS mult_x_69_U274 ( .A(mult_x_69_n692), .B(mult_x_69_n427), .C(
mult_x_69_n431), .D(mult_x_69_n716), .ICI(mult_x_69_n432), .S(
mult_x_69_n425), .ICO(mult_x_69_n423), .CO(mult_x_69_n424) );
CMPR42X1TS mult_x_69_U273 ( .A(mult_x_69_n740), .B(mult_x_69_n425), .C(
mult_x_69_n428), .D(mult_x_69_n764), .ICI(mult_x_69_n429), .S(
mult_x_69_n422), .ICO(mult_x_69_n420), .CO(mult_x_69_n421) );
CMPR42X1TS mult_x_69_U271 ( .A(mult_x_69_n691), .B(mult_x_69_n419), .C(
mult_x_69_n423), .D(mult_x_69_n715), .ICI(mult_x_69_n424), .S(
mult_x_69_n417), .ICO(mult_x_69_n415), .CO(mult_x_69_n416) );
CMPR42X1TS mult_x_69_U270 ( .A(mult_x_69_n739), .B(mult_x_69_n417), .C(
mult_x_69_n420), .D(mult_x_69_n763), .ICI(mult_x_69_n421), .S(
mult_x_69_n414), .ICO(mult_x_69_n412), .CO(mult_x_69_n413) );
CMPR42X1TS mult_x_69_U267 ( .A(mult_x_69_n690), .B(mult_x_69_n409), .C(
mult_x_69_n415), .D(mult_x_69_n714), .ICI(mult_x_69_n416), .S(
mult_x_69_n407), .ICO(mult_x_69_n405), .CO(mult_x_69_n406) );
CMPR42X1TS mult_x_69_U266 ( .A(mult_x_69_n738), .B(mult_x_69_n407), .C(
mult_x_69_n412), .D(mult_x_69_n762), .ICI(mult_x_69_n413), .S(
mult_x_69_n404), .ICO(mult_x_69_n402), .CO(mult_x_69_n403) );
CMPR42X1TS mult_x_69_U263 ( .A(mult_x_69_n689), .B(mult_x_69_n399), .C(
mult_x_69_n405), .D(mult_x_69_n713), .ICI(mult_x_69_n406), .S(
mult_x_69_n397), .ICO(mult_x_69_n395), .CO(mult_x_69_n396) );
CMPR42X1TS mult_x_69_U262 ( .A(mult_x_69_n397), .B(mult_x_69_n737), .C(
mult_x_69_n402), .D(mult_x_69_n761), .ICI(mult_x_69_n403), .S(
mult_x_69_n394), .ICO(mult_x_69_n392), .CO(mult_x_69_n393) );
CMPR42X1TS mult_x_69_U259 ( .A(mult_x_69_n688), .B(mult_x_69_n389), .C(
mult_x_69_n395), .D(mult_x_69_n712), .ICI(mult_x_69_n396), .S(
mult_x_69_n387), .ICO(mult_x_69_n385), .CO(mult_x_69_n386) );
CMPR42X1TS mult_x_69_U258 ( .A(mult_x_69_n387), .B(mult_x_69_n736), .C(
mult_x_69_n392), .D(mult_x_69_n760), .ICI(mult_x_69_n393), .S(
mult_x_69_n384), .ICO(mult_x_69_n382), .CO(mult_x_69_n383) );
CMPR42X1TS mult_x_69_U256 ( .A(mult_x_69_n381), .B(mult_x_69_n639), .C(
mult_x_69_n390), .D(mult_x_69_n663), .ICI(mult_x_69_n388), .S(
mult_x_69_n379), .ICO(mult_x_69_n377), .CO(mult_x_69_n378) );
CMPR42X1TS mult_x_69_U255 ( .A(mult_x_69_n687), .B(mult_x_69_n379), .C(
mult_x_69_n385), .D(mult_x_69_n711), .ICI(mult_x_69_n386), .S(
mult_x_69_n376), .ICO(mult_x_69_n374), .CO(mult_x_69_n375) );
CMPR42X1TS mult_x_69_U254 ( .A(mult_x_69_n376), .B(mult_x_69_n735), .C(
mult_x_69_n382), .D(mult_x_69_n759), .ICI(mult_x_69_n383), .S(
mult_x_69_n373), .ICO(mult_x_69_n371), .CO(mult_x_69_n372) );
CMPR42X1TS mult_x_69_U252 ( .A(mult_x_69_n370), .B(mult_x_69_n638), .C(
mult_x_69_n377), .D(mult_x_69_n662), .ICI(mult_x_69_n378), .S(
mult_x_69_n368), .ICO(mult_x_69_n366), .CO(mult_x_69_n367) );
CMPR42X1TS mult_x_69_U251 ( .A(mult_x_69_n686), .B(mult_x_69_n368), .C(
mult_x_69_n374), .D(mult_x_69_n710), .ICI(mult_x_69_n375), .S(
mult_x_69_n365), .ICO(mult_x_69_n363), .CO(mult_x_69_n364) );
CMPR42X1TS mult_x_69_U250 ( .A(mult_x_69_n365), .B(mult_x_69_n734), .C(
mult_x_69_n371), .D(mult_x_69_n758), .ICI(mult_x_69_n372), .S(
mult_x_69_n362), .ICO(mult_x_69_n360), .CO(mult_x_69_n361) );
CMPR42X1TS mult_x_69_U248 ( .A(mult_x_69_n359), .B(mult_x_69_n637), .C(
mult_x_69_n366), .D(mult_x_69_n661), .ICI(mult_x_69_n367), .S(
mult_x_69_n357), .ICO(mult_x_69_n355), .CO(mult_x_69_n356) );
CMPR42X1TS mult_x_69_U247 ( .A(mult_x_69_n685), .B(mult_x_69_n357), .C(
mult_x_69_n363), .D(mult_x_69_n709), .ICI(mult_x_69_n364), .S(
mult_x_69_n354), .ICO(mult_x_69_n352), .CO(mult_x_69_n353) );
CMPR42X1TS mult_x_69_U246 ( .A(mult_x_69_n354), .B(mult_x_69_n733), .C(
mult_x_69_n360), .D(mult_x_69_n757), .ICI(mult_x_69_n361), .S(
mult_x_69_n351), .ICO(mult_x_69_n349), .CO(mult_x_69_n350) );
CMPR42X1TS mult_x_69_U244 ( .A(mult_x_69_n348), .B(mult_x_69_n636), .C(
mult_x_69_n355), .D(mult_x_69_n660), .ICI(mult_x_69_n356), .S(
mult_x_69_n346), .ICO(mult_x_69_n344), .CO(mult_x_69_n345) );
CMPR42X1TS mult_x_69_U243 ( .A(mult_x_69_n684), .B(mult_x_69_n346), .C(
mult_x_69_n352), .D(mult_x_69_n708), .ICI(mult_x_69_n353), .S(
mult_x_69_n343), .ICO(mult_x_69_n341), .CO(mult_x_69_n342) );
CMPR42X1TS mult_x_69_U242 ( .A(mult_x_69_n343), .B(mult_x_69_n732), .C(
mult_x_69_n349), .D(mult_x_69_n756), .ICI(mult_x_69_n350), .S(
mult_x_69_n340), .ICO(mult_x_69_n338), .CO(mult_x_69_n339) );
CMPR42X1TS mult_x_69_U240 ( .A(mult_x_69_n337), .B(mult_x_69_n635), .C(
mult_x_69_n344), .D(mult_x_69_n659), .ICI(mult_x_69_n345), .S(
mult_x_69_n335), .ICO(mult_x_69_n333), .CO(mult_x_69_n334) );
CMPR42X1TS mult_x_69_U239 ( .A(mult_x_69_n335), .B(mult_x_69_n683), .C(
mult_x_69_n341), .D(mult_x_69_n707), .ICI(mult_x_69_n342), .S(
mult_x_69_n332), .ICO(mult_x_69_n330), .CO(mult_x_69_n331) );
CMPR42X1TS mult_x_69_U238 ( .A(mult_x_69_n332), .B(mult_x_69_n731), .C(
mult_x_69_n338), .D(mult_x_69_n755), .ICI(mult_x_69_n779), .S(
mult_x_69_n329), .ICO(mult_x_69_n327), .CO(mult_x_69_n328) );
CMPR42X1TS mult_x_69_U236 ( .A(mult_x_69_n326), .B(mult_x_69_n336), .C(
mult_x_69_n634), .D(mult_x_69_n333), .ICI(mult_x_69_n658), .S(
mult_x_69_n324), .ICO(mult_x_69_n322), .CO(mult_x_69_n323) );
CMPR42X1TS mult_x_69_U235 ( .A(mult_x_69_n324), .B(mult_x_69_n334), .C(
mult_x_69_n682), .D(mult_x_69_n330), .ICI(mult_x_69_n706), .S(
mult_x_69_n321), .ICO(mult_x_69_n319), .CO(mult_x_69_n320) );
CMPR42X1TS mult_x_69_U234 ( .A(mult_x_69_n331), .B(mult_x_69_n321), .C(
mult_x_69_n730), .D(mult_x_69_n327), .ICI(mult_x_69_n328), .S(
mult_x_69_n318), .ICO(mult_x_69_n316), .CO(mult_x_69_n317) );
CMPR42X1TS mult_x_69_U232 ( .A(mult_x_69_n325), .B(mult_x_69_n315), .C(
mult_x_69_n322), .D(mult_x_69_n633), .ICI(mult_x_69_n323), .S(
mult_x_69_n313), .ICO(mult_x_69_n311), .CO(mult_x_69_n312) );
CMPR42X1TS mult_x_69_U231 ( .A(mult_x_69_n657), .B(mult_x_69_n313), .C(
mult_x_69_n319), .D(mult_x_69_n681), .ICI(mult_x_69_n320), .S(
mult_x_69_n310), .ICO(mult_x_69_n308), .CO(mult_x_69_n309) );
CMPR42X1TS mult_x_69_U230 ( .A(mult_x_69_n705), .B(mult_x_69_n310), .C(
mult_x_69_n316), .D(mult_x_69_n729), .ICI(mult_x_69_n753), .S(
mult_x_69_n307), .ICO(mult_x_69_n305), .CO(mult_x_69_n306) );
CMPR42X1TS mult_x_69_U228 ( .A(mult_x_69_n314), .B(mult_x_69_n304), .C(
mult_x_69_n311), .D(mult_x_69_n632), .ICI(mult_x_69_n312), .S(
mult_x_69_n302), .ICO(mult_x_69_n300), .CO(mult_x_69_n301) );
CMPR42X1TS mult_x_69_U227 ( .A(mult_x_69_n656), .B(mult_x_69_n302), .C(
mult_x_69_n308), .D(mult_x_69_n680), .ICI(mult_x_69_n309), .S(
mult_x_69_n299), .ICO(mult_x_69_n297), .CO(mult_x_69_n298) );
CMPR42X1TS mult_x_69_U226 ( .A(mult_x_69_n704), .B(mult_x_69_n299), .C(
mult_x_69_n305), .D(mult_x_69_n728), .ICI(mult_x_69_n752), .S(
mult_x_69_n296), .ICO(mult_x_69_n294), .CO(mult_x_69_n295) );
CMPR42X1TS mult_x_69_U224 ( .A(mult_x_69_n293), .B(mult_x_69_n608), .C(
mult_x_69_n303), .D(mult_x_69_n300), .ICI(mult_x_69_n631), .S(
mult_x_69_n291), .ICO(mult_x_69_n289), .CO(mult_x_69_n290) );
CMPR42X1TS mult_x_69_U223 ( .A(mult_x_69_n291), .B(mult_x_69_n301), .C(
mult_x_69_n655), .D(mult_x_69_n297), .ICI(mult_x_69_n679), .S(
mult_x_69_n288), .ICO(mult_x_69_n286), .CO(mult_x_69_n287) );
CMPR42X1TS mult_x_69_U222 ( .A(mult_x_69_n288), .B(mult_x_69_n298), .C(
mult_x_69_n703), .D(mult_x_69_n294), .ICI(mult_x_69_n295), .S(
mult_x_69_n285), .ICO(mult_x_69_n283), .CO(mult_x_69_n284) );
CMPR42X1TS mult_x_69_U220 ( .A(n3227), .B(mult_x_69_n292), .C(mult_x_69_n289), .D(mult_x_69_n607), .ICI(mult_x_69_n630), .S(mult_x_69_n281), .ICO(
mult_x_69_n279), .CO(mult_x_69_n280) );
CMPR42X1TS mult_x_69_U219 ( .A(mult_x_69_n290), .B(mult_x_69_n281), .C(
mult_x_69_n286), .D(mult_x_69_n654), .ICI(mult_x_69_n678), .S(
mult_x_69_n278), .ICO(mult_x_69_n276), .CO(mult_x_69_n277) );
CMPR42X1TS mult_x_69_U218 ( .A(mult_x_69_n287), .B(mult_x_69_n278), .C(
mult_x_69_n283), .D(mult_x_69_n702), .ICI(mult_x_69_n726), .S(
mult_x_69_n275), .ICO(mult_x_69_n273), .CO(mult_x_69_n274) );
CMPR42X1TS mult_x_69_U216 ( .A(FPMULT_Op_MY[6]), .B(n3226), .C(
mult_x_69_n279), .D(mult_x_69_n606), .ICI(mult_x_69_n280), .S(
mult_x_69_n271), .ICO(mult_x_69_n269), .CO(mult_x_69_n270) );
CMPR42X1TS mult_x_69_U215 ( .A(mult_x_69_n629), .B(mult_x_69_n271), .C(
mult_x_69_n276), .D(mult_x_69_n653), .ICI(mult_x_69_n277), .S(
mult_x_69_n268), .ICO(mult_x_69_n266), .CO(mult_x_69_n267) );
CMPR42X1TS mult_x_69_U214 ( .A(mult_x_69_n677), .B(mult_x_69_n268), .C(
mult_x_69_n273), .D(mult_x_69_n701), .ICI(mult_x_69_n725), .S(
mult_x_69_n265), .ICO(mult_x_69_n263), .CO(mult_x_69_n264) );
CMPR42X1TS mult_x_69_U213 ( .A(n3363), .B(FPMULT_Op_MY[8]), .C(
FPMULT_Op_MY[7]), .D(mult_x_69_n269), .ICI(mult_x_69_n605), .S(
mult_x_69_n262), .ICO(mult_x_69_n260), .CO(mult_x_69_n261) );
CMPR42X1TS mult_x_69_U212 ( .A(mult_x_69_n262), .B(mult_x_69_n270), .C(
mult_x_69_n628), .D(mult_x_69_n266), .ICI(mult_x_69_n652), .S(
mult_x_69_n259), .ICO(mult_x_69_n257), .CO(mult_x_69_n258) );
CMPR42X1TS mult_x_69_U211 ( .A(mult_x_69_n259), .B(mult_x_69_n267), .C(
mult_x_69_n676), .D(mult_x_69_n263), .ICI(mult_x_69_n264), .S(
mult_x_69_n256), .ICO(mult_x_69_n254), .CO(mult_x_69_n255) );
CMPR42X1TS mult_x_69_U208 ( .A(mult_x_69_n261), .B(mult_x_69_n252), .C(
mult_x_69_n257), .D(mult_x_69_n627), .ICI(mult_x_69_n651), .S(
mult_x_69_n250), .ICO(mult_x_69_n248), .CO(mult_x_69_n249) );
CMPR42X1TS mult_x_69_U207 ( .A(mult_x_69_n258), .B(mult_x_69_n250), .C(
mult_x_69_n254), .D(mult_x_69_n675), .ICI(mult_x_69_n699), .S(
mult_x_69_n247), .ICO(mult_x_69_n245), .CO(mult_x_69_n246) );
CMPR42X1TS mult_x_69_U204 ( .A(mult_x_69_n251), .B(mult_x_69_n243), .C(
mult_x_69_n248), .D(mult_x_69_n626), .ICI(mult_x_69_n249), .S(
mult_x_69_n241), .ICO(mult_x_69_n239), .CO(mult_x_69_n240) );
CMPR42X1TS mult_x_69_U203 ( .A(mult_x_69_n650), .B(mult_x_69_n241), .C(
mult_x_69_n245), .D(mult_x_69_n674), .ICI(mult_x_69_n698), .S(
mult_x_69_n238), .ICO(mult_x_69_n236), .CO(mult_x_69_n237) );
CMPR42X1TS mult_x_69_U201 ( .A(mult_x_69_n235), .B(mult_x_69_n242), .C(
mult_x_69_n602), .D(mult_x_69_n239), .ICI(mult_x_69_n625), .S(
mult_x_69_n233), .ICO(mult_x_69_n231), .CO(mult_x_69_n232) );
CMPR42X1TS mult_x_69_U200 ( .A(mult_x_69_n233), .B(mult_x_69_n240), .C(
mult_x_69_n649), .D(mult_x_69_n236), .ICI(mult_x_69_n237), .S(
mult_x_69_n230), .ICO(mult_x_69_n228), .CO(mult_x_69_n229) );
CMPR42X1TS mult_x_69_U198 ( .A(n3229), .B(mult_x_69_n234), .C(mult_x_69_n231), .D(mult_x_69_n601), .ICI(mult_x_69_n624), .S(mult_x_69_n226), .ICO(
mult_x_69_n224), .CO(mult_x_69_n225) );
CMPR42X1TS mult_x_69_U197 ( .A(mult_x_69_n232), .B(mult_x_69_n226), .C(
mult_x_69_n228), .D(mult_x_69_n648), .ICI(mult_x_69_n672), .S(
mult_x_69_n223), .ICO(mult_x_69_n221), .CO(mult_x_69_n222) );
CMPR42X1TS mult_x_69_U195 ( .A(FPMULT_Op_MY[12]), .B(n1033), .C(
mult_x_69_n224), .D(mult_x_69_n600), .ICI(mult_x_69_n225), .S(
mult_x_69_n219), .ICO(mult_x_69_n217), .CO(mult_x_69_n218) );
CMPR42X1TS mult_x_69_U194 ( .A(mult_x_69_n623), .B(mult_x_69_n219), .C(
mult_x_69_n221), .D(mult_x_69_n647), .ICI(mult_x_69_n671), .S(
mult_x_69_n216), .ICO(mult_x_69_n214), .CO(mult_x_69_n215) );
CMPR42X1TS mult_x_69_U193 ( .A(n3362), .B(FPMULT_Op_MY[13]), .C(
FPMULT_Op_MY[14]), .D(mult_x_69_n217), .ICI(mult_x_69_n599), .S(
mult_x_69_n213), .ICO(mult_x_69_n211), .CO(mult_x_69_n212) );
CMPR42X1TS mult_x_69_U192 ( .A(mult_x_69_n213), .B(mult_x_69_n218), .C(
mult_x_69_n622), .D(mult_x_69_n214), .ICI(mult_x_69_n215), .S(
mult_x_69_n210), .ICO(mult_x_69_n208), .CO(mult_x_69_n209) );
CMPR42X1TS mult_x_69_U189 ( .A(mult_x_69_n212), .B(mult_x_69_n206), .C(
mult_x_69_n208), .D(mult_x_69_n621), .ICI(mult_x_69_n645), .S(
mult_x_69_n204), .ICO(mult_x_69_n202), .CO(mult_x_69_n203) );
CMPR42X1TS mult_x_69_U186 ( .A(mult_x_69_n597), .B(mult_x_69_n200), .C(
mult_x_69_n202), .D(mult_x_69_n620), .ICI(mult_x_69_n644), .S(
mult_x_69_n198), .ICO(mult_x_69_n196), .CO(mult_x_69_n197) );
CMPR42X1TS mult_x_69_U184 ( .A(mult_x_69_n195), .B(mult_x_69_n199), .C(
mult_x_69_n596), .D(mult_x_69_n196), .ICI(mult_x_69_n197), .S(
mult_x_69_n193), .ICO(mult_x_69_n191), .CO(mult_x_69_n192) );
CMPR42X1TS mult_x_69_U182 ( .A(n1040), .B(mult_x_69_n194), .C(mult_x_69_n191), .D(mult_x_69_n595), .ICI(mult_x_69_n618), .S(mult_x_69_n189), .ICO(
mult_x_69_n187), .CO(mult_x_69_n188) );
CMPR42X1TS mult_x_69_U180 ( .A(FPMULT_Op_MY[19]), .B(n1040), .C(
mult_x_69_n187), .D(mult_x_69_n594), .ICI(mult_x_69_n617), .S(
mult_x_69_n185), .ICO(mult_x_69_n183), .CO(mult_x_69_n184) );
CMPR42X1TS mult_x_69_U179 ( .A(n3361), .B(FPMULT_Op_MY[18]), .C(
FPMULT_Op_MY[20]), .D(mult_x_69_n183), .ICI(mult_x_69_n593), .S(
mult_x_69_n182), .ICO(mult_x_69_n180), .CO(mult_x_69_n181) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_28_ ( .D(
FPSENCOS_first_mux_X[28]), .CK(n3448), .RN(n3355), .Q(
FPSENCOS_d_ff2_X[28]), .QN(n3271) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_28_ ( .D(
FPSENCOS_first_mux_Y[28]), .CK(n3449), .RN(n3353), .Q(
FPSENCOS_d_ff2_Y[28]), .QN(n3270) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(
FPADDSUB_formatted_number_W[0]), .CK(n3471), .RN(n3299), .Q(
result_add_subt[0]), .QN(n3269) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(
FPADDSUB_formatted_number_W[1]), .CK(n3474), .RN(n3300), .Q(
result_add_subt[1]), .QN(n3268) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(
FPADDSUB_formatted_number_W[2]), .CK(n3474), .RN(n3286), .Q(
result_add_subt[2]), .QN(n3267) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(
FPADDSUB_formatted_number_W[3]), .CK(n3473), .RN(n3301), .Q(
result_add_subt[3]), .QN(n3266) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(
FPADDSUB_formatted_number_W[4]), .CK(n3473), .RN(n3289), .Q(
result_add_subt[4]), .QN(n3265) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(
FPADDSUB_formatted_number_W[5]), .CK(n3474), .RN(n3291), .Q(
result_add_subt[5]), .QN(n3264) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(
FPADDSUB_formatted_number_W[6]), .CK(n3471), .RN(n3302), .Q(
result_add_subt[6]), .QN(n3263) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(
FPADDSUB_formatted_number_W[7]), .CK(n3474), .RN(n3303), .Q(
result_add_subt[7]), .QN(n3262) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(
FPADDSUB_formatted_number_W[8]), .CK(n3473), .RN(n3293), .Q(
result_add_subt[8]), .QN(n3261) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(
FPADDSUB_formatted_number_W[9]), .CK(n3473), .RN(n3295), .Q(
result_add_subt[9]), .QN(n3260) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(
FPADDSUB_formatted_number_W[10]), .CK(n3474), .RN(n3294), .Q(
result_add_subt[10]), .QN(n3259) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(
FPADDSUB_formatted_number_W[11]), .CK(n3472), .RN(n3292), .Q(
result_add_subt[11]), .QN(n3258) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(
FPADDSUB_formatted_number_W[12]), .CK(n3471), .RN(n3294), .Q(
result_add_subt[12]), .QN(n3257) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(
FPADDSUB_formatted_number_W[13]), .CK(n3472), .RN(n3291), .Q(
result_add_subt[13]), .QN(n3256) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(
FPADDSUB_formatted_number_W[14]), .CK(n3472), .RN(n3292), .Q(
result_add_subt[14]), .QN(n3255) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(
FPADDSUB_formatted_number_W[15]), .CK(n3472), .RN(n3290), .Q(
result_add_subt[15]), .QN(n3254) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(
FPADDSUB_formatted_number_W[16]), .CK(n3471), .RN(n3287), .Q(
result_add_subt[16]), .QN(n3253) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(
FPADDSUB_formatted_number_W[17]), .CK(n3472), .RN(n3289), .Q(
result_add_subt[17]), .QN(n3252) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(
FPADDSUB_formatted_number_W[18]), .CK(n3473), .RN(n3288), .Q(
result_add_subt[18]), .QN(n3251) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(
FPADDSUB_formatted_number_W[19]), .CK(n3471), .RN(n3285), .Q(
result_add_subt[19]), .QN(n3250) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(
FPADDSUB_formatted_number_W[20]), .CK(n3472), .RN(n3288), .Q(
result_add_subt[20]), .QN(n3249) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(
FPADDSUB_formatted_number_W[21]), .CK(n3473), .RN(n3286), .Q(
result_add_subt[21]), .QN(n3248) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(
FPADDSUB_formatted_number_W[22]), .CK(n3471), .RN(n3285), .Q(
result_add_subt[22]), .QN(n3247) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(
FPADDSUB_formatted_number_W[23]), .CK(n3471), .RN(n3318), .Q(
result_add_subt[23]), .QN(n3246) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(
FPADDSUB_formatted_number_W[24]), .CK(n3474), .RN(n1304), .Q(
result_add_subt[24]), .QN(n3245) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(
FPADDSUB_formatted_number_W[25]), .CK(n3474), .RN(n1302), .Q(
result_add_subt[25]), .QN(n3244) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(
FPADDSUB_formatted_number_W[26]), .CK(n3474), .RN(n1300), .Q(
result_add_subt[26]), .QN(n3243) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(
FPADDSUB_formatted_number_W[27]), .CK(n3473), .RN(n1303), .Q(
result_add_subt[27]), .QN(n3242) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(
FPADDSUB_formatted_number_W[28]), .CK(n3471), .RN(n3315), .Q(
result_add_subt[28]), .QN(n3241) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(
FPADDSUB_formatted_number_W[29]), .CK(n3471), .RN(n3315), .Q(
result_add_subt[29]), .QN(n3240) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(
FPADDSUB_formatted_number_W[30]), .CK(n3471), .RN(n3315), .Q(
result_add_subt[30]), .QN(n3239) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(
FPADDSUB_formatted_number_W[31]), .CK(n3473), .RN(n3295), .Q(
result_add_subt[31]), .QN(n3238) );
DFFRX1TS FPMULT_Sel_B_Q_reg_0_ ( .D(n830), .CK(n911), .RN(n3368), .Q(
FPMULT_FSM_selector_B[0]), .QN(n3237) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(
FPADDSUB_Raw_mant_SGF[16]), .CK(n3463), .RN(n3297), .Q(
FPADDSUB_Raw_mant_NRM_SWR[16]), .QN(n3236) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_21_ ( .D(FPADDSUB_Data_array_SWR[21]), .CK(n3399), .RN(n3285), .Q(FPADDSUB_Data_array_SWR[47]), .QN(n3234) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_20_ ( .D(FPADDSUB_Data_array_SWR[20]), .CK(n3399), .RN(n3286), .Q(FPADDSUB_Data_array_SWR[46]), .QN(n3233) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_26_ ( .D(FPADDSUB_DmP_INIT_EWSW[26]),
.CK(n3413), .RN(n3282), .QN(n3216) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_24_ ( .D(FPADDSUB_DmP_INIT_EWSW[24]),
.CK(n3413), .RN(n3281), .QN(n3215) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_25_ ( .D(FPADDSUB_DmP_INIT_EWSW[25]),
.CK(n3413), .RN(n3281), .QN(n3214) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_8_ ( .D(Data_1[8]), .CK(
n3387), .RN(n3375), .Q(FPMULT_Op_MX[8]), .QN(n3213) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_14_ ( .D(Data_1[14]),
.CK(n3387), .RN(n3370), .Q(FPMULT_Op_MX[14]), .QN(n3212) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_5_ ( .D(Data_1[5]), .CK(
n3386), .RN(n3369), .Q(FPMULT_Op_MX[5]), .QN(n3211) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(FPADDSUB_Raw_mant_SGF[4]),
.CK(n3464), .RN(n3296), .Q(FPADDSUB_Raw_mant_NRM_SWR[4]), .QN(n3209)
);
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(
FPADDSUB_Raw_mant_SGF[25]), .CK(n3464), .RN(n3298), .Q(
FPADDSUB_Raw_mant_NRM_SWR[25]), .QN(n3208) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_23_ ( .D(FPADDSUB_Data_array_SWR[23]), .CK(n3401), .RN(n3299), .Q(FPADDSUB_Data_array_SWR[49]), .QN(n3207) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(
FPADDSUB_shft_value_mux_o_EWR[2]), .CK(n3401), .RN(n3298), .Q(
FPADDSUB_shift_value_SHT2_EWR[2]), .QN(n3206) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(FPADDSUB_Raw_mant_SGF[1]),
.CK(n3463), .RN(n3296), .Q(FPADDSUB_Raw_mant_NRM_SWR[1]), .QN(n3204)
);
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_SHT2_EWSW[12]),
.CK(n3467), .RN(n3304), .Q(FPADDSUB_DMP_SFG[12]), .QN(n3203) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_23_ ( .D(
FPSENCOS_first_mux_X[23]), .CK(n3448), .RN(n3356), .Q(
FPSENCOS_d_ff2_X[23]), .QN(n3202) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_23_ ( .D(
FPSENCOS_first_mux_Y[23]), .CK(n3451), .RN(n3354), .Q(
FPSENCOS_d_ff2_Y[23]), .QN(n3201) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_INIT_EWSW[23]),
.CK(FPADDSUB_EXP_STAGE_DMP_net5038596), .RN(n3282), .Q(
FPADDSUB_DMP_EXP_EWSW[23]), .QN(n3200) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_22_ ( .D(FPADDSUB_Data_array_SWR[22]), .CK(n3399), .RN(n3299), .Q(FPADDSUB_Data_array_SWR[48]), .QN(n3198) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_SHT2_EWSW[17]),
.CK(n3466), .RN(n3308), .Q(FPADDSUB_DMP_SFG[17]), .QN(n3197) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_SHT2_EWSW[13]),
.CK(n3467), .RN(n3307), .Q(FPADDSUB_DMP_SFG[13]), .QN(n3196) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_SHT2_EWSW[7]),
.CK(n3469), .RN(n3303), .Q(FPADDSUB_DMP_SFG[7]), .QN(n3195) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_SHT2_EWSW[3]),
.CK(n3469), .RN(n3302), .Q(FPADDSUB_DMP_SFG[3]), .QN(n3194) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_SHT2_EWSW[1]),
.CK(n1044), .RN(n3301), .Q(FPADDSUB_DMP_SFG[1]), .QN(n3193) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(
FPADDSUB_Raw_mant_SGF[14]), .CK(n3465), .RN(n3297), .Q(
FPADDSUB_Raw_mant_NRM_SWR[14]), .QN(n3191) );
DFFRXLTS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(FPADDSUB_Raw_mant_SGF[6]),
.CK(n3465), .RN(n3296), .Q(FPADDSUB_Raw_mant_NRM_SWR[6]), .QN(n3190)
);
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[22]), .CK(n3467), .RN(n3314), .Q(
FPADDSUB_DmP_mant_SFG_SWR[22]), .QN(n3189) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[20]), .CK(n3466), .RN(n3313), .Q(
FPADDSUB_DmP_mant_SFG_SWR[20]), .QN(n3188) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(
FPADDSUB_Raw_mant_SGF[12]), .CK(n3463), .RN(n3297), .Q(
FPADDSUB_Raw_mant_NRM_SWR[12]), .QN(n3187) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[21]), .CK(n3466), .RN(n3313), .Q(
FPADDSUB_DmP_mant_SFG_SWR[21]), .QN(n3185) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(add_subt_data1[30]),
.CK(n3421), .RN(n3281), .Q(FPADDSUB_intDX_EWSW[30]), .QN(n3184) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(
FPADDSUB_Raw_mant_SGF[22]), .CK(n3465), .RN(n3298), .Q(
FPADDSUB_Raw_mant_NRM_SWR[22]), .QN(n3183) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_7_ ( .D(Data_1[7]), .CK(
n3387), .RN(n3369), .Q(FPMULT_Op_MX[7]), .QN(n3182) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(
FPADDSUB_Raw_mant_SGF[11]), .CK(n3464), .RN(n3297), .Q(
FPADDSUB_Raw_mant_NRM_SWR[11]), .QN(n3181) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(add_subt_data2[18]),
.CK(n3423), .RN(n3288), .Q(FPADDSUB_intDY_EWSW[18]), .QN(n3180) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(add_subt_data1[14]),
.CK(n3421), .RN(n3292), .Q(FPADDSUB_intDX_EWSW[14]), .QN(n3179) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(add_subt_data1[10]),
.CK(n3420), .RN(n3294), .Q(FPADDSUB_intDX_EWSW[10]), .QN(n3178) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(add_subt_data1[9]),
.CK(n3426), .RN(n3295), .Q(FPADDSUB_intDX_EWSW[9]), .QN(n3177) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(add_subt_data2[8]),
.CK(n3423), .RN(n3293), .Q(FPADDSUB_intDY_EWSW[8]), .QN(n3176) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(add_subt_data2[1]),
.CK(n3421), .RN(n3300), .Q(FPADDSUB_intDY_EWSW[1]), .QN(n3175) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(add_subt_data2[0]),
.CK(n3420), .RN(n3299), .Q(FPADDSUB_intDY_EWSW[0]), .QN(n3174) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_4_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7_5), .CK(n913), .RN(n3279), .Q(busy), .QN(
n3173) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_SHT2_EWSW[0]),
.CK(n3466), .RN(n3300), .Q(FPADDSUB_DMP_SFG[0]), .QN(n3172) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_SHT2_EWSW[16]),
.CK(n3467), .RN(n3309), .Q(FPADDSUB_DMP_SFG[16]), .QN(n3171) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_SHT2_EWSW[6]),
.CK(n912), .RN(n3303), .Q(FPADDSUB_DMP_SFG[6]), .QN(n3170) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n3505), .CK(
n3394), .RN(n1019), .Q(FPMULT_Sgf_normalized_result[1]), .QN(n3169) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_SHT2_EWSW[14]),
.CK(n3470), .RN(n3306), .Q(FPADDSUB_DMP_SFG[14]), .QN(n3167) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_SHT2_EWSW[8]),
.CK(n912), .RN(n3305), .Q(FPADDSUB_DMP_SFG[8]), .QN(n3166) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]), .CK(n3485), .RN(n3344),
.Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .QN(n3165) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n3509), .CK(
n3394), .RN(n3376), .QN(n3164) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n3507), .CK(
n3394), .RN(n826), .QN(n3163) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n3525), .CK(
n3393), .RN(n3370), .QN(n3162) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n3523), .CK(
n3394), .RN(n3378), .QN(n3161) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n3521), .CK(
n3393), .RN(n3369), .QN(n3160) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n3519), .CK(
n3394), .RN(n3369), .QN(n3159) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n3517), .CK(
n3393), .RN(n3364), .QN(n3158) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n3515), .CK(
n3393), .RN(n3374), .QN(n3157) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n3513), .CK(
n3394), .RN(n3364), .QN(n3156) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n3511), .CK(
n3392), .RN(n1019), .QN(n3155) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[6]), .CK(n3469), .RN(n3312), .Q(
FPADDSUB_DmP_mant_SFG_SWR[6]), .QN(n3154) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[4]), .CK(n3470), .RN(n3312), .Q(
FPADDSUB_DmP_mant_SFG_SWR[4]), .QN(n3153) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(add_subt_data1[28]),
.CK(n3420), .RN(n3281), .QN(n3152) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_22_ ( .D(Data_1[22]),
.CK(n3388), .RN(n3372), .Q(FPMULT_Op_MX[22]), .QN(n3151) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_SHT2_EWSW[5]),
.CK(n3469), .RN(n3307), .Q(FPADDSUB_DMP_SFG[5]), .QN(n3150) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[17]), .CK(n3469), .RN(n3313), .Q(
FPADDSUB_DmP_mant_SFG_SWR[17]), .QN(n3149) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[11]), .CK(n3466), .RN(n3312), .Q(
FPADDSUB_DmP_mant_SFG_SWR[11]), .QN(n3148) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_SHT2_EWSW[10]),
.CK(n3469), .RN(n3305), .Q(FPADDSUB_DMP_SFG[10]), .QN(n3147) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_SHT2_EWSW[11]),
.CK(n3467), .RN(n3306), .Q(FPADDSUB_DMP_SFG[11]), .QN(n3146) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(add_subt_data2[20]),
.CK(n3423), .RN(n3288), .Q(FPADDSUB_intDY_EWSW[20]), .QN(n3145) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(add_subt_data2[21]),
.CK(n3426), .RN(n3286), .Q(FPADDSUB_intDY_EWSW[21]), .QN(n3144) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(add_subt_data1[19]),
.CK(n3425), .RN(n3285), .Q(FPADDSUB_intDX_EWSW[19]), .QN(n3143) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(add_subt_data1[11]),
.CK(n3425), .RN(n3293), .Q(FPADDSUB_intDX_EWSW[11]), .QN(n3142) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(add_subt_data2[27]),
.CK(n3421), .RN(n3282), .Q(FPADDSUB_intDY_EWSW[27]), .QN(n3141) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(add_subt_data2[16]),
.CK(n3426), .RN(n3287), .Q(FPADDSUB_intDY_EWSW[16]), .QN(n3140) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(add_subt_data2[4]),
.CK(n3424), .RN(n3290), .Q(FPADDSUB_intDY_EWSW[4]), .QN(n3139) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(add_subt_data2[26]),
.CK(n3420), .RN(n3281), .Q(FPADDSUB_intDY_EWSW[26]), .QN(n3138) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(add_subt_data1[24]),
.CK(n3422), .RN(n3280), .Q(FPADDSUB_intDX_EWSW[24]), .QN(n3137) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(add_subt_data1[2]),
.CK(n3426), .RN(n3287), .Q(FPADDSUB_intDX_EWSW[2]), .QN(n3136) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_13_ ( .D(Data_1[13]),
.CK(n3387), .RN(n3369), .Q(FPMULT_Op_MX[13]), .QN(n3135) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(add_subt_data1[5]),
.CK(n3425), .RN(n3291), .Q(FPADDSUB_intDX_EWSW[5]), .QN(n3134) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(add_subt_data2[25]),
.CK(n3425), .RN(n3281), .Q(FPADDSUB_intDY_EWSW[25]), .QN(n3133) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(add_subt_data2[13]),
.CK(n3424), .RN(n3291), .Q(FPADDSUB_intDY_EWSW[13]), .QN(n3132) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(add_subt_data1[23]),
.CK(n3423), .RN(n3280), .Q(FPADDSUB_intDX_EWSW[23]), .QN(n3131) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(add_subt_data1[3]),
.CK(n3422), .RN(n3301), .Q(FPADDSUB_intDX_EWSW[3]), .QN(n3130) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(add_subt_data2[22]),
.CK(n3426), .RN(n3285), .Q(FPADDSUB_intDY_EWSW[22]), .QN(n3129) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(add_subt_data2[12]),
.CK(n3424), .RN(n3294), .Q(FPADDSUB_intDY_EWSW[12]), .QN(n3128) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(add_subt_data1[15]),
.CK(n3422), .RN(n3290), .Q(FPADDSUB_intDX_EWSW[15]), .QN(n3127) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(add_subt_data2[6]),
.CK(n3426), .RN(n3302), .Q(FPADDSUB_intDY_EWSW[6]), .QN(n3126) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(add_subt_data1[17]),
.CK(n3423), .RN(n3289), .Q(FPADDSUB_intDX_EWSW[17]), .QN(n3125) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_1_ ( .D(
FPMULT_FS_Module_state_next[1]), .CK(n911), .RN(n3339), .Q(
FPMULT_FS_Module_state_reg[1]), .QN(n3124) );
DFFRX1TS FPADDSUB_Ready_reg_Q_reg_0_ ( .D(FPADDSUB_Shift_reg_FLAGS_7[0]),
.CK(n3483), .RN(n3279), .Q(ready_add_subt), .QN(n3123) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(n3503), .CK(
n3485), .RN(n3279), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]),
.QN(n3121) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(add_subt_data1[7]),
.CK(n3425), .RN(n3303), .Q(FPADDSUB_intDX_EWSW[7]), .QN(n3120) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_0_ ( .D(n3119), .CK(n914), .RN(n3344),
.Q(FPSENCOS_cont_iter_out[0]), .QN(n3119) );
DFFRX2TS FPMULT_Sel_B_Q_reg_1_ ( .D(n829), .CK(n911), .RN(n3368), .Q(
FPMULT_FSM_selector_B[1]), .QN(n3117) );
DFFRX1TS FPSENCOS_reg_operation_Q_reg_0_ ( .D(n3502), .CK(n3459), .RN(n3341),
.Q(FPSENCOS_d_ff1_operation_out), .QN(n3113) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(
FPADDSUB_Raw_mant_SGF[20]), .CK(n3463), .RN(n3298), .Q(
FPADDSUB_Raw_mant_NRM_SWR[20]), .QN(n3112) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(
FPADDSUB_Raw_mant_SGF[13]), .CK(n3465), .RN(n3297), .Q(
FPADDSUB_Raw_mant_NRM_SWR[13]), .QN(n3111) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_24_ ( .D(FPADDSUB_Data_array_SWR[24]), .CK(n3400), .RN(n3299), .Q(FPADDSUB_Data_array_SWR[50]), .QN(n3109) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_25_ ( .D(FPADDSUB_Data_array_SWR[25]), .CK(n3401), .RN(n3285), .Q(FPADDSUB_Data_array_SWR[51]), .QN(n3108) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_1_ ( .D(Data_1[1]), .CK(
n3386), .RN(n3377), .Q(FPMULT_Op_MX[1]), .QN(n3107) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(add_subt_data1[29]),
.CK(n3421), .RN(n3281), .QN(n3106) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(add_subt_data1[4]),
.CK(n3421), .RN(n3290), .Q(FPADDSUB_intDX_EWSW[4]), .QN(n3105) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_21_ ( .D(Data_1[21]),
.CK(n3388), .RN(n3367), .Q(FPMULT_Op_MX[21]), .QN(n3104) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_12_ ( .D(Data_1[12]),
.CK(n3387), .RN(n1019), .Q(FPMULT_Op_MX[12]), .QN(n3103) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(add_subt_data1[26]),
.CK(n3420), .RN(n3280), .Q(FPADDSUB_intDX_EWSW[26]), .QN(n3102) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(add_subt_data1[20]),
.CK(n3420), .RN(n3288), .Q(FPADDSUB_intDX_EWSW[20]), .QN(n3101) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(add_subt_data1[6]),
.CK(n3422), .RN(n3302), .Q(FPADDSUB_intDX_EWSW[6]), .QN(n3100) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(add_subt_data2[7]),
.CK(n3423), .RN(n3303), .Q(FPADDSUB_intDY_EWSW[7]), .QN(n3099) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(add_subt_data1[22]),
.CK(n3425), .RN(n3285), .Q(FPADDSUB_intDX_EWSW[22]), .QN(n3098) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n3504), .CK(
n3392), .RN(n3365), .Q(FPMULT_Sgf_normalized_result[0]), .QN(n3097) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_SHT2_EWSW[9]),
.CK(n1044), .RN(n3304), .Q(FPADDSUB_DMP_SFG[9]), .QN(n3096) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_SHT2_EWSW[15]),
.CK(n1044), .RN(n3307), .Q(FPADDSUB_DMP_SFG[15]), .QN(n3095) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[14]), .CK(n1044), .RN(n3313), .Q(
FPADDSUB_DmP_mant_SFG_SWR[14]), .QN(n3094) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_SHT2_EWSW[19]),
.CK(n3466), .RN(n3311), .Q(FPADDSUB_DMP_SFG[19]), .QN(n3093) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[13]), .CK(n912), .RN(n3313), .Q(
FPADDSUB_DmP_mant_SFG_SWR[13]), .QN(n3092) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[7]), .CK(n3470), .RN(n3312), .Q(
FPADDSUB_DmP_mant_SFG_SWR[7]), .QN(n3091) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(add_subt_data2[19]),
.CK(n3420), .RN(n3285), .Q(FPADDSUB_intDY_EWSW[19]), .QN(n3090) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(add_subt_data2[24]),
.CK(n3422), .RN(n3281), .Q(FPADDSUB_intDY_EWSW[24]), .QN(n3089) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(add_subt_data2[5]),
.CK(n3424), .RN(n3291), .Q(FPADDSUB_intDY_EWSW[5]), .QN(n3088) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(add_subt_data1[8]),
.CK(n3421), .RN(n3293), .QN(n3087) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(add_subt_data2[2]),
.CK(n3426), .RN(n3287), .Q(FPADDSUB_intDY_EWSW[2]), .QN(n3086) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(add_subt_data2[23]),
.CK(n3423), .RN(n3281), .Q(FPADDSUB_intDY_EWSW[23]), .QN(n3085) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(add_subt_data1[27]),
.CK(n3422), .RN(n3280), .Q(FPADDSUB_intDX_EWSW[27]), .QN(n3084) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(add_subt_data1[0]),
.CK(n3420), .RN(n3299), .QN(n3083) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_0_ ( .D(n843), .CK(n3483), .RN(n3345),
.Q(FPSENCOS_cont_var_out[0]), .QN(n3082) );
DFFRX2TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n874), .CK(clk), .RN(n3279), .QN(n3081) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_0_ ( .D(region_flag[0]), .CK(n3458),
.RN(n3343), .Q(FPSENCOS_d_ff1_shift_region_flag_out[0]), .QN(n3077) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(add_subt_data1[16]),
.CK(n3426), .RN(n3287), .Q(FPADDSUB_intDX_EWSW[16]), .QN(n3076) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(add_subt_data2[17]),
.CK(n3424), .RN(n3289), .Q(FPADDSUB_intDY_EWSW[17]), .QN(n3075) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(add_subt_data1[13]),
.CK(n3425), .RN(n3291), .Q(FPADDSUB_intDX_EWSW[13]), .QN(n3074) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(add_subt_data1[21]),
.CK(n3422), .RN(n3286), .Q(FPADDSUB_intDX_EWSW[21]), .QN(n3073) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(add_subt_data2[15]),
.CK(n3424), .RN(n3290), .Q(FPADDSUB_intDY_EWSW[15]), .QN(n3072) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(add_subt_data1[25]),
.CK(n3423), .RN(n3280), .Q(FPADDSUB_intDX_EWSW[25]), .QN(n3071) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(add_subt_data2[11]),
.CK(n3424), .RN(n3293), .Q(FPADDSUB_intDY_EWSW[11]), .QN(n3070) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(FPADDSUB_Raw_mant_SGF[5]),
.CK(n3463), .RN(n3296), .Q(FPADDSUB_Raw_mant_NRM_SWR[5]), .QN(n3067)
);
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(add_subt_data2[3]),
.CK(n3421), .RN(n3301), .Q(FPADDSUB_intDY_EWSW[3]), .QN(n3066) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(add_subt_data1[18]),
.CK(n3423), .RN(n3288), .QN(n3065) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(add_subt_data1[1]),
.CK(n3426), .RN(n3300), .QN(n3064) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_2_ ( .D(
FPMULT_FS_Module_state_next[2]), .CK(n911), .RN(n3333), .Q(
FPMULT_FS_Module_state_reg[2]), .QN(n3063) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(add_subt_data1[12]),
.CK(n3425), .RN(n3294), .Q(FPADDSUB_intDX_EWSW[12]), .QN(n3059) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(add_subt_data2[9]),
.CK(n3420), .RN(n3295), .QN(n3058) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(add_subt_data2[14]),
.CK(n3424), .RN(n3292), .QN(n3057) );
DFFRXLTS NaN_dff_Q_reg_0_ ( .D(NaN_reg), .CK(n3483), .RN(n3345), .Q(NaN_flag) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_SHT1_EWSW[0]),
.CK(n3404), .RN(n3300), .Q(FPADDSUB_DMP_SHT2_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_SHT1_EWSW[1]),
.CK(n917), .RN(n3301), .Q(FPADDSUB_DMP_SHT2_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_SHT1_EWSW[3]),
.CK(n917), .RN(n3301), .Q(FPADDSUB_DMP_SHT2_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_SHT1_EWSW[6]),
.CK(n3403), .RN(n3302), .Q(FPADDSUB_DMP_SHT2_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_SHT1_EWSW[7]),
.CK(n3403), .RN(n3303), .Q(FPADDSUB_DMP_SHT2_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_SHT1_EWSW[9]),
.CK(n3403), .RN(n3304), .Q(FPADDSUB_DMP_SHT2_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_SHT1_EWSW[12]),
.CK(n3403), .RN(n3304), .Q(FPADDSUB_DMP_SHT2_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_SHT1_EWSW[10]),
.CK(n3403), .RN(n3305), .Q(FPADDSUB_DMP_SHT2_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_SHT1_EWSW[8]),
.CK(n3403), .RN(n3305), .Q(FPADDSUB_DMP_SHT2_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_SHT1_EWSW[11]),
.CK(n3403), .RN(n3306), .Q(FPADDSUB_DMP_SHT2_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_SHT1_EWSW[14]),
.CK(n3403), .RN(n3306), .Q(FPADDSUB_DMP_SHT2_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_SHT1_EWSW[13]),
.CK(n3403), .RN(n3306), .Q(FPADDSUB_DMP_SHT2_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_SHT1_EWSW[5]),
.CK(n3403), .RN(n3307), .Q(FPADDSUB_DMP_SHT2_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_SHT1_EWSW[15]),
.CK(n3402), .RN(n3307), .Q(FPADDSUB_DMP_SHT2_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_SHT1_EWSW[17]),
.CK(n3402), .RN(n3308), .Q(FPADDSUB_DMP_SHT2_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_SHT1_EWSW[16]),
.CK(n3402), .RN(n3309), .Q(FPADDSUB_DMP_SHT2_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_SHT1_EWSW[19]),
.CK(n3402), .RN(n3311), .Q(FPADDSUB_DMP_SHT2_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_SHT1_EWSW[22]),
.CK(n3402), .RN(n3311), .Q(FPADDSUB_DMP_SHT2_EWSW[22]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_INIT_EWSW[28]),
.CK(n3418), .RN(n3283), .Q(FPADDSUB_DMP_EXP_EWSW[28]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_INIT_EWSW[29]),
.CK(FPADDSUB_EXP_STAGE_DMP_net5038596), .RN(n3283), .Q(
FPADDSUB_DMP_EXP_EWSW[29]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_INIT_EWSW[30]),
.CK(FPADDSUB_EXP_STAGE_DMP_net5038596), .RN(n3283), .Q(
FPADDSUB_DMP_EXP_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_EXP_EWSW[23]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net5038596), .RN(n3283), .Q(
FPADDSUB_DMP_SHT1_EWSW[23]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_EXP_EWSW[24]),
.CK(n3412), .RN(n3283), .Q(FPADDSUB_DMP_SHT1_EWSW[24]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_EXP_EWSW[25]),
.CK(n3411), .RN(n3283), .Q(FPADDSUB_DMP_SHT1_EWSW[25]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_EXP_EWSW[26]),
.CK(n3411), .RN(n3283), .Q(FPADDSUB_DMP_SHT1_EWSW[26]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_EXP_EWSW[27]),
.CK(n3412), .RN(n3283), .Q(FPADDSUB_DMP_SHT1_EWSW[27]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_EXP_EWSW[28]),
.CK(n3411), .RN(n3283), .Q(FPADDSUB_DMP_SHT1_EWSW[28]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_EXP_EWSW[29]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net5038596), .RN(n3284), .Q(
FPADDSUB_DMP_SHT1_EWSW[29]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_EXP_EWSW[30]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net5038596), .RN(n3284), .Q(
FPADDSUB_DMP_SHT1_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_SHT1_EWSW[23]),
.CK(n3404), .RN(n3284), .Q(FPADDSUB_DMP_SHT2_EWSW[23]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_23_ ( .D(FPADDSUB_DMP_SHT2_EWSW[23]),
.CK(n3468), .RN(n3316), .Q(FPADDSUB_DMP_SFG[23]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(FPADDSUB_DMP_SFG[23]),
.CK(n3464), .RN(n3316), .Q(FPADDSUB_DMP_exp_NRM_EW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_SHT1_EWSW[24]),
.CK(n917), .RN(n3284), .Q(FPADDSUB_DMP_SHT2_EWSW[24]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_SHT2_EWSW[24]),
.CK(n1044), .RN(n3316), .Q(FPADDSUB_DMP_SFG[24]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(FPADDSUB_DMP_SFG[24]),
.CK(n3465), .RN(n3316), .Q(FPADDSUB_DMP_exp_NRM_EW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_SHT1_EWSW[25]),
.CK(n3404), .RN(n3284), .Q(FPADDSUB_DMP_SHT2_EWSW[25]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_SHT2_EWSW[25]),
.CK(n3468), .RN(n3316), .Q(FPADDSUB_DMP_SFG[25]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(FPADDSUB_DMP_SFG[25]),
.CK(n3462), .RN(n3316), .Q(FPADDSUB_DMP_exp_NRM_EW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_SHT1_EWSW[26]),
.CK(n917), .RN(n3284), .Q(FPADDSUB_DMP_SHT2_EWSW[26]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_SHT2_EWSW[26]),
.CK(n3468), .RN(n3317), .Q(FPADDSUB_DMP_SFG[26]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(FPADDSUB_DMP_SFG[26]),
.CK(n3462), .RN(n3317), .Q(FPADDSUB_DMP_exp_NRM_EW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_SHT1_EWSW[27]),
.CK(n3404), .RN(n3284), .Q(FPADDSUB_DMP_SHT2_EWSW[27]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_SHT2_EWSW[27]),
.CK(n3468), .RN(n3317), .Q(FPADDSUB_DMP_SFG[27]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(FPADDSUB_DMP_SFG[27]),
.CK(n3462), .RN(n3317), .Q(FPADDSUB_DMP_exp_NRM_EW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_SHT1_EWSW[28]),
.CK(n917), .RN(n3284), .Q(FPADDSUB_DMP_SHT2_EWSW[28]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_28_ ( .D(FPADDSUB_DMP_SHT2_EWSW[28]),
.CK(n3468), .RN(n3317), .Q(FPADDSUB_DMP_SFG[28]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(FPADDSUB_DMP_SFG[28]),
.CK(n3462), .RN(n3317), .Q(FPADDSUB_DMP_exp_NRM_EW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_SHT1_EWSW[29]),
.CK(n917), .RN(n3284), .Q(FPADDSUB_DMP_SHT2_EWSW[29]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_29_ ( .D(FPADDSUB_DMP_SHT2_EWSW[29]),
.CK(n912), .RN(n3318), .Q(FPADDSUB_DMP_SFG[29]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(FPADDSUB_DMP_SFG[29]),
.CK(n3462), .RN(n3318), .Q(FPADDSUB_DMP_exp_NRM_EW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_SHT1_EWSW[30]),
.CK(n917), .RN(n3284), .Q(FPADDSUB_DMP_SHT2_EWSW[30]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_30_ ( .D(FPADDSUB_DMP_SHT2_EWSW[30]),
.CK(n912), .RN(n3318), .Q(FPADDSUB_DMP_SFG[30]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(FPADDSUB_DMP_SFG[30]),
.CK(n3462), .RN(n3318), .Q(FPADDSUB_DMP_exp_NRM_EW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_22_ ( .D(FPADDSUB_DmP_INIT_EWSW[22]),
.CK(n3413), .RN(n3285), .Q(FPADDSUB_DmP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_19_ ( .D(FPADDSUB_DmP_INIT_EWSW[19]),
.CK(n3413), .RN(n3286), .Q(FPADDSUB_DmP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_21_ ( .D(FPADDSUB_DmP_INIT_EWSW[21]),
.CK(n3413), .RN(n3286), .Q(FPADDSUB_DmP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_2_ ( .D(FPADDSUB_DmP_INIT_EWSW[2]),
.CK(n3413), .RN(n3287), .Q(FPADDSUB_DmP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_16_ ( .D(FPADDSUB_DmP_INIT_EWSW[16]),
.CK(n3413), .RN(n3287), .Q(FPADDSUB_DmP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_18_ ( .D(FPADDSUB_DmP_INIT_EWSW[18]),
.CK(n3416), .RN(n3288), .Q(FPADDSUB_DmP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_20_ ( .D(FPADDSUB_DmP_INIT_EWSW[20]),
.CK(n3414), .RN(n3289), .Q(FPADDSUB_DmP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_17_ ( .D(FPADDSUB_DmP_INIT_EWSW[17]),
.CK(n3416), .RN(n3289), .Q(FPADDSUB_DmP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_4_ ( .D(FPADDSUB_DmP_INIT_EWSW[4]),
.CK(n3416), .RN(n3290), .Q(FPADDSUB_DmP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_15_ ( .D(FPADDSUB_DmP_INIT_EWSW[15]),
.CK(n3416), .RN(n3290), .Q(FPADDSUB_DmP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_5_ ( .D(FPADDSUB_DmP_INIT_EWSW[5]),
.CK(n3416), .RN(n3291), .Q(FPADDSUB_DmP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_13_ ( .D(FPADDSUB_DmP_INIT_EWSW[13]),
.CK(n3414), .RN(n3292), .Q(FPADDSUB_DmP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_14_ ( .D(FPADDSUB_DmP_INIT_EWSW[14]),
.CK(n3414), .RN(n3292), .Q(FPADDSUB_DmP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_11_ ( .D(FPADDSUB_DmP_INIT_EWSW[11]),
.CK(n3414), .RN(n3293), .Q(FPADDSUB_DmP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_8_ ( .D(FPADDSUB_DmP_INIT_EWSW[8]),
.CK(n3414), .RN(n3293), .Q(FPADDSUB_DmP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_10_ ( .D(FPADDSUB_DmP_INIT_EWSW[10]),
.CK(n3415), .RN(n3294), .Q(FPADDSUB_DmP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_12_ ( .D(FPADDSUB_DmP_INIT_EWSW[12]),
.CK(n3415), .RN(n3295), .Q(FPADDSUB_DmP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_0_ ( .D(FPADDSUB_DmP_INIT_EWSW[0]),
.CK(n3415), .RN(n3299), .Q(FPADDSUB_DmP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_INIT_EWSW[0]),
.CK(n3419), .RN(n3299), .Q(FPADDSUB_DMP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_0_ ( .D(FPADDSUB_DMP_EXP_EWSW[0]),
.CK(n3412), .RN(n3300), .Q(FPADDSUB_DMP_SHT1_EWSW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_1_ ( .D(FPADDSUB_DmP_INIT_EWSW[1]),
.CK(n3415), .RN(n3300), .Q(FPADDSUB_DmP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_INIT_EWSW[1]),
.CK(n3419), .RN(n3300), .Q(FPADDSUB_DMP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_1_ ( .D(FPADDSUB_DMP_EXP_EWSW[1]),
.CK(n3412), .RN(n3300), .Q(FPADDSUB_DMP_SHT1_EWSW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_3_ ( .D(FPADDSUB_DmP_INIT_EWSW[3]),
.CK(n3415), .RN(n3301), .Q(FPADDSUB_DmP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_INIT_EWSW[3]),
.CK(FPADDSUB_EXP_STAGE_DMP_net5038596), .RN(n3301), .Q(
FPADDSUB_DMP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_3_ ( .D(FPADDSUB_DMP_EXP_EWSW[3]),
.CK(FPADDSUB_SHT1_STAGE_DMP_net5038596), .RN(n3301), .Q(
FPADDSUB_DMP_SHT1_EWSW[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_6_ ( .D(FPADDSUB_DmP_INIT_EWSW[6]),
.CK(n3415), .RN(n3302), .Q(FPADDSUB_DmP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_INIT_EWSW[6]),
.CK(n3417), .RN(n3302), .Q(FPADDSUB_DMP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_6_ ( .D(FPADDSUB_DMP_EXP_EWSW[6]),
.CK(n3410), .RN(n3302), .Q(FPADDSUB_DMP_SHT1_EWSW[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_7_ ( .D(FPADDSUB_DmP_INIT_EWSW[7]),
.CK(n3415), .RN(n3303), .Q(FPADDSUB_DmP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_INIT_EWSW[7]),
.CK(n3417), .RN(n3303), .Q(FPADDSUB_DMP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_7_ ( .D(FPADDSUB_DMP_EXP_EWSW[7]),
.CK(n3410), .RN(n3303), .Q(FPADDSUB_DMP_SHT1_EWSW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_9_ ( .D(FPADDSUB_DmP_INIT_EWSW[9]),
.CK(n3415), .RN(n3304), .Q(FPADDSUB_DmP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_INIT_EWSW[9]),
.CK(n3417), .RN(n3304), .Q(FPADDSUB_DMP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_9_ ( .D(FPADDSUB_DMP_EXP_EWSW[9]),
.CK(n3410), .RN(n3304), .Q(FPADDSUB_DMP_SHT1_EWSW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_INIT_EWSW[12]),
.CK(n3417), .RN(n3304), .Q(FPADDSUB_DMP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_12_ ( .D(FPADDSUB_DMP_EXP_EWSW[12]),
.CK(n3410), .RN(n3304), .Q(FPADDSUB_DMP_SHT1_EWSW[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_INIT_EWSW[10]),
.CK(n3417), .RN(n3305), .Q(FPADDSUB_DMP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_10_ ( .D(FPADDSUB_DMP_EXP_EWSW[10]),
.CK(n3410), .RN(n3305), .Q(FPADDSUB_DMP_SHT1_EWSW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_INIT_EWSW[8]),
.CK(n3417), .RN(n3305), .Q(FPADDSUB_DMP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_8_ ( .D(FPADDSUB_DMP_EXP_EWSW[8]),
.CK(n3410), .RN(n3305), .Q(FPADDSUB_DMP_SHT1_EWSW[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_INIT_EWSW[11]),
.CK(n3417), .RN(n3305), .Q(FPADDSUB_DMP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_11_ ( .D(FPADDSUB_DMP_EXP_EWSW[11]),
.CK(n3410), .RN(n3305), .Q(FPADDSUB_DMP_SHT1_EWSW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_INIT_EWSW[14]),
.CK(n3417), .RN(n3306), .Q(FPADDSUB_DMP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_14_ ( .D(FPADDSUB_DMP_EXP_EWSW[14]),
.CK(n3410), .RN(n3306), .Q(FPADDSUB_DMP_SHT1_EWSW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_INIT_EWSW[13]),
.CK(n3417), .RN(n3306), .Q(FPADDSUB_DMP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_13_ ( .D(FPADDSUB_DMP_EXP_EWSW[13]),
.CK(n3410), .RN(n3306), .Q(FPADDSUB_DMP_SHT1_EWSW[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_INIT_EWSW[5]),
.CK(n3417), .RN(n3307), .Q(FPADDSUB_DMP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_5_ ( .D(FPADDSUB_DMP_EXP_EWSW[5]),
.CK(n3410), .RN(n3307), .Q(FPADDSUB_DMP_SHT1_EWSW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_INIT_EWSW[15]),
.CK(n3416), .RN(n3307), .Q(FPADDSUB_DMP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_15_ ( .D(FPADDSUB_DMP_EXP_EWSW[15]),
.CK(n3409), .RN(n3307), .Q(FPADDSUB_DMP_SHT1_EWSW[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_INIT_EWSW[4]),
.CK(n3414), .RN(n3307), .Q(FPADDSUB_DMP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_EXP_EWSW[4]),
.CK(n3409), .RN(n3308), .Q(FPADDSUB_DMP_SHT1_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_SHT1_EWSW[4]),
.CK(n3402), .RN(n3308), .Q(FPADDSUB_DMP_SHT2_EWSW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_INIT_EWSW[17]),
.CK(n3416), .RN(n3308), .Q(FPADDSUB_DMP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_17_ ( .D(FPADDSUB_DMP_EXP_EWSW[17]),
.CK(n3409), .RN(n3308), .Q(FPADDSUB_DMP_SHT1_EWSW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_INIT_EWSW[20]),
.CK(n3414), .RN(n3308), .Q(FPADDSUB_DMP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_EXP_EWSW[20]),
.CK(n3409), .RN(n3308), .Q(FPADDSUB_DMP_SHT1_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_SHT1_EWSW[20]),
.CK(n3402), .RN(n3308), .Q(FPADDSUB_DMP_SHT2_EWSW[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_INIT_EWSW[18]),
.CK(n3416), .RN(n3309), .Q(FPADDSUB_DMP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_EXP_EWSW[18]),
.CK(n3409), .RN(n3309), .Q(FPADDSUB_DMP_SHT1_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_SHT1_EWSW[18]),
.CK(n3402), .RN(n3309), .Q(FPADDSUB_DMP_SHT2_EWSW[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_INIT_EWSW[16]),
.CK(n3414), .RN(n3309), .Q(FPADDSUB_DMP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_16_ ( .D(FPADDSUB_DMP_EXP_EWSW[16]),
.CK(n3409), .RN(n3309), .Q(FPADDSUB_DMP_SHT1_EWSW[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_INIT_EWSW[2]),
.CK(n3416), .RN(n3310), .Q(FPADDSUB_DMP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_EXP_EWSW[2]),
.CK(n3409), .RN(n3310), .Q(FPADDSUB_DMP_SHT1_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_SHT1_EWSW[2]),
.CK(n3402), .RN(n3310), .Q(FPADDSUB_DMP_SHT2_EWSW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_INIT_EWSW[21]),
.CK(n3414), .RN(n3310), .Q(FPADDSUB_DMP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_EXP_EWSW[21]),
.CK(n3409), .RN(n3310), .Q(FPADDSUB_DMP_SHT1_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_SHT1_EWSW[21]),
.CK(n3402), .RN(n3310), .Q(FPADDSUB_DMP_SHT2_EWSW[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_INIT_EWSW[19]),
.CK(n3416), .RN(n3310), .Q(FPADDSUB_DMP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_19_ ( .D(FPADDSUB_DMP_EXP_EWSW[19]),
.CK(n3409), .RN(n3310), .Q(FPADDSUB_DMP_SHT1_EWSW[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_INIT_EWSW[22]),
.CK(n3414), .RN(n3311), .Q(FPADDSUB_DMP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_EXP_EWSW[22]),
.CK(n3409), .RN(n3311), .Q(FPADDSUB_DMP_SHT1_EWSW[22]) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n3494), .CK(n3415), .RN(
n3314), .Q(FPADDSUB_SIGN_FLAG_EXP) );
DFFRXLTS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_2_ ( .D(FPADDSUB_SIGN_FLAG_SHT2),
.CK(n3466), .RN(n3314), .Q(FPADDSUB_SIGN_FLAG_SFG) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n30), .CK(n3415), .RN(n3314),
.Q(FPADDSUB_OP_FLAG_EXP) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(n3430),
.RN(n3352), .Q(FPSENCOS_d_ff_Zn[23]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(n3430),
.RN(n3352), .Q(FPSENCOS_d_ff_Zn[24]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(n3429),
.RN(n3352), .Q(FPSENCOS_d_ff_Zn[25]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(n3427),
.RN(n3351), .Q(FPSENCOS_d_ff_Zn[26]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(n3429),
.RN(n3351), .Q(FPSENCOS_d_ff_Zn[27]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(n3427),
.RN(n3351), .Q(FPSENCOS_d_ff_Zn[28]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(n3429),
.RN(n3351), .Q(FPSENCOS_d_ff_Zn[29]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(n3427),
.RN(n3351), .Q(FPSENCOS_d_ff_Zn[30]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(n3427),
.RN(n3350), .Q(FPSENCOS_d_ff_Zn[22]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(n3427),
.RN(n3349), .Q(FPSENCOS_d_ff_Zn[19]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(n3427),
.RN(n3348), .Q(FPSENCOS_d_ff_Zn[21]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(n3430),
.RN(n3330), .Q(FPSENCOS_d_ff_Zn[2]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(n3429),
.RN(n3329), .Q(FPSENCOS_d_ff_Zn[16]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(n3430),
.RN(n3328), .Q(FPSENCOS_d_ff_Zn[18]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(n3428),
.RN(n3328), .Q(FPSENCOS_d_ff_Zn[20]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(n3428),
.RN(n3327), .Q(FPSENCOS_d_ff_Zn[17]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(n3428),
.RN(n3326), .Q(FPSENCOS_d_ff_Zn[4]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(n3428),
.RN(n3325), .Q(FPSENCOS_d_ff_Zn[15]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(n3428),
.RN(n3324), .Q(FPSENCOS_d_ff_Zn[5]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(n3428),
.RN(n3323), .Q(FPSENCOS_d_ff_Zn[13]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(n3428),
.RN(n3322), .Q(FPSENCOS_d_ff_Zn[14]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(n3428),
.RN(n3321), .Q(FPSENCOS_d_ff_Zn[11]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(n3427),
.RN(n3320), .Q(FPSENCOS_d_ff_Zn[8]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(n3429),
.RN(n3319), .Q(FPSENCOS_d_ff_Zn[10]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(n3430),
.RN(n3339), .Q(FPSENCOS_d_ff_Zn[12]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(n3427),
.RN(n3360), .Q(FPSENCOS_d_ff_Zn[9]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(n3429),
.RN(n3338), .Q(FPSENCOS_d_ff_Zn[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(n3430),
.RN(n3337), .Q(FPSENCOS_d_ff_Zn[0]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(n3427),
.RN(n3337), .Q(FPSENCOS_d_ff_Zn[1]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(n3429),
.RN(n3336), .Q(FPSENCOS_d_ff_Zn[3]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(n3430),
.RN(n3335), .Q(FPSENCOS_d_ff_Zn[6]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(n3427),
.RN(n3334), .Q(FPSENCOS_d_ff_Zn[7]) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n3495), .CK(n3472), .RN(
n3315), .Q(underflow_flag_addsubt) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n3496), .CK(n3472), .RN(
n3315), .Q(overflow_flag_addsubt) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(
FPADDSUB_LZD_raw_out_EWR[3]), .CK(n941), .RN(n3315), .Q(
FPADDSUB_LZD_output_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(
FPADDSUB_LZD_raw_out_EWR[2]), .CK(n941), .RN(n3315), .Q(
FPADDSUB_LZD_output_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(
FPADDSUB_LZD_raw_out_EWR[1]), .CK(n941), .RN(n3315), .Q(
FPADDSUB_LZD_output_NRM2_EW[1]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(
FPADDSUB_LZD_raw_out_EWR[4]), .CK(n941), .RN(n3316), .Q(
FPADDSUB_LZD_output_NRM2_EW[4]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_0_ ( .D(Data_1[0]), .CK(n3461), .RN(n3341),
.Q(FPSENCOS_d_ff1_Z[0]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_1_ ( .D(Data_1[1]), .CK(n3461), .RN(n3341),
.Q(FPSENCOS_d_ff1_Z[1]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_2_ ( .D(Data_1[2]), .CK(n3458), .RN(n3341),
.Q(FPSENCOS_d_ff1_Z[2]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_3_ ( .D(Data_1[3]), .CK(n3461), .RN(n3341),
.Q(FPSENCOS_d_ff1_Z[3]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_4_ ( .D(Data_1[4]), .CK(n3458), .RN(n3341),
.Q(FPSENCOS_d_ff1_Z[4]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_5_ ( .D(Data_1[5]), .CK(n3461), .RN(n3340),
.Q(FPSENCOS_d_ff1_Z[5]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_6_ ( .D(Data_1[6]), .CK(n3458), .RN(n3340),
.Q(FPSENCOS_d_ff1_Z[6]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_7_ ( .D(Data_1[7]), .CK(n3460), .RN(n3340),
.Q(FPSENCOS_d_ff1_Z[7]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_8_ ( .D(Data_1[8]), .CK(n3460), .RN(n3340),
.Q(FPSENCOS_d_ff1_Z[8]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_9_ ( .D(Data_1[9]), .CK(n3460), .RN(n3340),
.Q(FPSENCOS_d_ff1_Z[9]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_10_ ( .D(Data_1[10]), .CK(n3460), .RN(n3340),
.Q(FPSENCOS_d_ff1_Z[10]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_11_ ( .D(Data_1[11]), .CK(n3460), .RN(n3340),
.Q(FPSENCOS_d_ff1_Z[11]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_12_ ( .D(Data_1[12]), .CK(n3460), .RN(n3340),
.Q(FPSENCOS_d_ff1_Z[12]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_13_ ( .D(Data_1[13]), .CK(n3460), .RN(n3340),
.Q(FPSENCOS_d_ff1_Z[13]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_14_ ( .D(Data_1[14]), .CK(n3460), .RN(n3340),
.Q(FPSENCOS_d_ff1_Z[14]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_15_ ( .D(Data_1[15]), .CK(n3459), .RN(n3339),
.Q(FPSENCOS_d_ff1_Z[15]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_16_ ( .D(Data_1[16]), .CK(n3458), .RN(n3345),
.Q(FPSENCOS_d_ff1_Z[16]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_17_ ( .D(Data_1[17]), .CK(n3461), .RN(n3359),
.Q(FPSENCOS_d_ff1_Z[17]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_18_ ( .D(Data_1[18]), .CK(n3459), .RN(n3359),
.Q(FPSENCOS_d_ff1_Z[18]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_19_ ( .D(Data_1[19]), .CK(n3458), .RN(n3359),
.Q(FPSENCOS_d_ff1_Z[19]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_20_ ( .D(Data_1[20]), .CK(n3461), .RN(n3359),
.Q(FPSENCOS_d_ff1_Z[20]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_21_ ( .D(Data_1[21]), .CK(n3459), .RN(n3359),
.Q(FPSENCOS_d_ff1_Z[21]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_22_ ( .D(Data_1[22]), .CK(n3458), .RN(n3359),
.Q(FPSENCOS_d_ff1_Z[22]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_23_ ( .D(Data_1[23]), .CK(n3459), .RN(n3359),
.Q(FPSENCOS_d_ff1_Z[23]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_24_ ( .D(Data_1[24]), .CK(n3458), .RN(n3358),
.Q(FPSENCOS_d_ff1_Z[24]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_25_ ( .D(Data_1[25]), .CK(n3459), .RN(n3358),
.Q(FPSENCOS_d_ff1_Z[25]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_26_ ( .D(Data_1[26]), .CK(n3458), .RN(n3358),
.Q(FPSENCOS_d_ff1_Z[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_27_ ( .D(Data_1[27]), .CK(n3459), .RN(n3358),
.Q(FPSENCOS_d_ff1_Z[27]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_28_ ( .D(Data_1[28]), .CK(n3459), .RN(n3358),
.Q(FPSENCOS_d_ff1_Z[28]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_29_ ( .D(Data_1[29]), .CK(n3459), .RN(n3358),
.Q(FPSENCOS_d_ff1_Z[29]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_30_ ( .D(Data_1[30]), .CK(n3459), .RN(n3358),
.Q(FPSENCOS_d_ff1_Z[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_31_ ( .D(Data_1[31]), .CK(n3461), .RN(n3358),
.Q(FPSENCOS_d_ff1_Z[31]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(FPADDSUB_SIGN_FLAG_EXP),
.CK(n3407), .RN(n3314), .Q(FPADDSUB_SIGN_FLAG_SHT1) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_1_ ( .D(FPADDSUB_SIGN_FLAG_SFG),
.CK(n3462), .RN(n3314), .Q(FPADDSUB_SIGN_FLAG_NRM) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(FPADDSUB_OP_FLAG_EXP), .CK(
n3408), .RN(n3318), .Q(FPADDSUB_OP_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[4]), .CK(n3406), .RN(n3280), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[3]), .CK(n3406), .RN(n3280), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[2]), .CK(n3406), .RN(n3280), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[2]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(
FPADDSUB_LZD_raw_out_EWR[0]), .CK(n915), .RN(n3315), .Q(
FPADDSUB_LZD_output_NRM2_EW[0]) );
DFFRXLTS FPMULT_Exp_module_Oflow_A_m_Q_reg_0_ ( .D(
FPMULT_Exp_module_Overflow_A), .CK(n3395), .RN(n3366), .Q(
FPMULT_Exp_module_Overflow_flag_A) );
DFFRXLTS reg_dataB_Q_reg_31_ ( .D(Data_2[31]), .CK(n3481), .RN(n3345), .Q(
dataB[31]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_30_ ( .D(FPSENCOS_sh_exp_x[7]), .CK(
n3441), .RN(n3357), .Q(FPSENCOS_d_ff3_sh_x_out[30]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_31_ ( .D(FPSENCOS_d_ff2_X[31]), .CK(
n3443), .RN(n1136), .Q(FPSENCOS_d_ff3_sh_x_out[31]) );
DFFRXLTS reg_dataA_Q_reg_31_ ( .D(Data_1[31]), .CK(n3484), .RN(n3346), .Q(
dataA[31]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_30_ ( .D(FPSENCOS_sh_exp_y[7]), .CK(
n3446), .RN(n3356), .Q(FPSENCOS_d_ff3_sh_y_out[30]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_31_ ( .D(FPSENCOS_d_ff2_Y[31]), .CK(
n3447), .RN(n1138), .Q(FPSENCOS_d_ff3_sh_y_out[31]) );
DFFRXLTS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(add_subt_data2[10]),
.CK(n3424), .RN(n3294), .Q(FPADDSUB_intDY_EWSW[10]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_3_ ( .D(n864), .CK(n3439), .RN(n3343), .Q(
FPSENCOS_d_ff3_LUT_out[3]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_5_ ( .D(n853), .CK(n3439), .RN(n3343), .Q(
FPSENCOS_d_ff3_LUT_out[5]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_7_ ( .D(n859), .CK(n3439), .RN(n3342), .Q(
FPSENCOS_d_ff3_LUT_out[7]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_13_ ( .D(n851), .CK(n3440), .RN(n3342), .Q(
FPSENCOS_d_ff3_LUT_out[13]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_15_ ( .D(n863), .CK(n3441), .RN(n3342), .Q(
FPSENCOS_d_ff3_LUT_out[15]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_19_ ( .D(n865), .CK(n3442), .RN(n3342), .Q(
FPSENCOS_d_ff3_LUT_out[19]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_27_ ( .D(1'b1), .CK(n3442), .RN(n3334), .Q(
FPSENCOS_d_ff3_LUT_out[27]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(
FPADDSUB_DmP_EXP_EWSW[21]), .CK(n3406), .RN(n3286), .Q(
FPADDSUB_DmP_mant_SHT1_SW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(
FPADDSUB_DmP_EXP_EWSW[17]), .CK(n3407), .RN(n3289), .Q(
FPADDSUB_DmP_mant_SHT1_SW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(FPADDSUB_DmP_EXP_EWSW[5]), .CK(n3408), .RN(n3291), .Q(FPADDSUB_DmP_mant_SHT1_SW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(
FPADDSUB_DmP_EXP_EWSW[13]), .CK(n3407), .RN(n3292), .Q(
FPADDSUB_DmP_mant_SHT1_SW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(FPADDSUB_DmP_EXP_EWSW[0]), .CK(n3407), .RN(n3299), .Q(FPADDSUB_DmP_mant_SHT1_SW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(FPADDSUB_DmP_EXP_EWSW[9]), .CK(n3407), .RN(n3304), .Q(FPADDSUB_DmP_mant_SHT1_SW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(
FPADDSUB_DmP_EXP_EWSW[10]), .CK(n3407), .RN(n3294), .Q(
FPADDSUB_DmP_mant_SHT1_SW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(FPADDSUB_DmP_EXP_EWSW[3]), .CK(n3407), .RN(n3301), .Q(FPADDSUB_DmP_mant_SHT1_SW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(
FPADDSUB_DmP_EXP_EWSW[22]), .CK(n3406), .RN(n3285), .Q(
FPADDSUB_DmP_mant_SHT1_SW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(
FPADDSUB_DmP_EXP_EWSW[19]), .CK(n3406), .RN(n3286), .Q(
FPADDSUB_DmP_mant_SHT1_SW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(FPADDSUB_DmP_EXP_EWSW[2]), .CK(n3406), .RN(n3287), .Q(FPADDSUB_DmP_mant_SHT1_SW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(
FPADDSUB_DmP_EXP_EWSW[18]), .CK(n3408), .RN(n3288), .Q(
FPADDSUB_DmP_mant_SHT1_SW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(
FPADDSUB_DmP_EXP_EWSW[15]), .CK(n3407), .RN(n3290), .Q(
FPADDSUB_DmP_mant_SHT1_SW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(
FPADDSUB_DmP_EXP_EWSW[14]), .CK(n3408), .RN(n3292), .Q(
FPADDSUB_DmP_mant_SHT1_SW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(
FPADDSUB_DmP_EXP_EWSW[11]), .CK(n3407), .RN(n3293), .Q(
FPADDSUB_DmP_mant_SHT1_SW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(FPADDSUB_DmP_EXP_EWSW[1]), .CK(n3408), .RN(n3300), .Q(FPADDSUB_DmP_mant_SHT1_SW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(FPADDSUB_DmP_EXP_EWSW[6]), .CK(n3408), .RN(n3302), .Q(FPADDSUB_DmP_mant_SHT1_SW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(FPADDSUB_DmP_EXP_EWSW[7]), .CK(n3408), .RN(n3303), .Q(FPADDSUB_DmP_mant_SHT1_SW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_27_ ( .D(FPADDSUB_DmP_INIT_EWSW[27]),
.CK(n3413), .RN(n3282), .Q(FPADDSUB_DmP_EXP_EWSW[27]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_0_ ( .D(n852), .CK(n3439), .RN(n3343), .Q(
FPSENCOS_d_ff3_LUT_out[0]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_4_ ( .D(FPSENCOS_data_out_LUT[4]), .CK(n3439), .RN(n3343), .Q(FPSENCOS_d_ff3_LUT_out[4]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_8_ ( .D(n3062), .CK(n3439), .RN(n3342), .Q(
FPSENCOS_d_ff3_LUT_out[8]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_9_ ( .D(n861), .CK(n3439), .RN(n3342), .Q(
FPSENCOS_d_ff3_LUT_out[9]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_10_ ( .D(n854), .CK(n3440), .RN(n3342), .Q(
FPSENCOS_d_ff3_LUT_out[10]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_21_ ( .D(n850), .CK(n3441), .RN(n3342), .Q(
FPSENCOS_d_ff3_LUT_out[21]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_23_ ( .D(n849), .CK(n3442), .RN(n3341), .Q(
FPSENCOS_d_ff3_LUT_out[23]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_26_ ( .D(n857), .CK(n3440), .RN(n3341), .Q(
FPSENCOS_d_ff3_LUT_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_24_ ( .D(FPSENCOS_sh_exp_y[1]), .CK(
n3447), .RN(n3357), .Q(FPSENCOS_d_ff3_sh_y_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_25_ ( .D(FPSENCOS_sh_exp_y[2]), .CK(
n3446), .RN(n3357), .Q(FPSENCOS_d_ff3_sh_y_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_27_ ( .D(FPSENCOS_sh_exp_y[4]), .CK(
n3447), .RN(n3356), .Q(FPSENCOS_d_ff3_sh_y_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_28_ ( .D(FPSENCOS_sh_exp_y[5]), .CK(
n3446), .RN(n3356), .Q(FPSENCOS_d_ff3_sh_y_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_29_ ( .D(FPSENCOS_sh_exp_y[6]), .CK(
n3446), .RN(n3356), .Q(FPSENCOS_d_ff3_sh_y_out[29]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_23_ ( .D(
FPSENCOS_first_mux_Z[23]), .CK(n3457), .RN(n3352), .Q(
FPSENCOS_d_ff2_Z[23]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_25_ ( .D(
FPSENCOS_first_mux_Z[25]), .CK(n3456), .RN(n3351), .Q(
FPSENCOS_d_ff2_Z[25]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_26_ ( .D(
FPSENCOS_first_mux_Z[26]), .CK(n3457), .RN(n3351), .Q(
FPSENCOS_d_ff2_Z[26]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_27_ ( .D(
FPSENCOS_first_mux_Z[27]), .CK(n3456), .RN(n3351), .Q(
FPSENCOS_d_ff2_Z[27]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_28_ ( .D(
FPSENCOS_first_mux_Z[28]), .CK(n3457), .RN(n3351), .Q(
FPSENCOS_d_ff2_Z[28]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_29_ ( .D(
FPSENCOS_first_mux_Z[29]), .CK(n3456), .RN(n3351), .Q(
FPSENCOS_d_ff2_Z[29]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_30_ ( .D(
FPSENCOS_first_mux_Z[30]), .CK(n3456), .RN(n3350), .Q(
FPSENCOS_d_ff2_Z[30]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_22_ ( .D(FPSENCOS_d_ff2_Y[22]), .CK(
n3446), .RN(n3350), .Q(FPSENCOS_d_ff3_sh_y_out[22]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_22_ ( .D(
FPSENCOS_first_mux_Z[22]), .CK(n3456), .RN(n3350), .Q(
FPSENCOS_d_ff2_Z[22]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_19_ ( .D(FPSENCOS_d_ff2_Y[19]), .CK(
n3447), .RN(n3349), .Q(FPSENCOS_d_ff3_sh_y_out[19]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_19_ ( .D(
FPSENCOS_first_mux_Z[19]), .CK(n3457), .RN(n3349), .Q(
FPSENCOS_d_ff2_Z[19]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_2_ ( .D(FPADDSUB_Data_array_SWR[2]),
.CK(n3398), .RN(n3286), .Q(FPADDSUB_Data_array_SWR[28]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_2_ ( .D(FPSENCOS_d_ff2_Y[2]), .CK(n3447),
.RN(n3330), .Q(FPSENCOS_d_ff3_sh_y_out[2]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_16_ ( .D(FPSENCOS_d_ff2_Y[16]), .CK(
n3447), .RN(n3330), .Q(FPSENCOS_d_ff3_sh_y_out[16]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_18_ ( .D(FPSENCOS_d_ff2_Y[18]), .CK(
n3447), .RN(n3329), .Q(FPSENCOS_d_ff3_sh_y_out[18]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_18_ ( .D(
FPSENCOS_first_mux_Z[18]), .CK(n3457), .RN(n3328), .Q(
FPSENCOS_d_ff2_Z[18]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_3_ ( .D(FPADDSUB_Data_array_SWR[3]),
.CK(n3398), .RN(n3288), .Q(FPADDSUB_Data_array_SWR[29]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_20_ ( .D(FPSENCOS_d_ff2_Y[20]), .CK(
n3446), .RN(n3328), .Q(FPSENCOS_d_ff3_sh_y_out[20]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_20_ ( .D(
FPSENCOS_first_mux_Z[20]), .CK(n3457), .RN(n3327), .Q(
FPSENCOS_d_ff2_Z[20]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_17_ ( .D(FPSENCOS_d_ff2_Y[17]), .CK(
n3447), .RN(n3327), .Q(FPSENCOS_d_ff3_sh_y_out[17]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_4_ ( .D(FPSENCOS_first_mux_Z[4]),
.CK(n3455), .RN(n3326), .Q(FPSENCOS_d_ff2_Z[4]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_15_ ( .D(FPSENCOS_d_ff2_Y[15]), .CK(
n3445), .RN(n3325), .Q(FPSENCOS_d_ff3_sh_y_out[15]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_15_ ( .D(
FPSENCOS_first_mux_Z[15]), .CK(n3455), .RN(n3325), .Q(
FPSENCOS_d_ff2_Z[15]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_5_ ( .D(FPSENCOS_d_ff2_Y[5]), .CK(n3445),
.RN(n3324), .Q(FPSENCOS_d_ff3_sh_y_out[5]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_5_ ( .D(FPSENCOS_first_mux_Z[5]),
.CK(n3455), .RN(n3324), .Q(FPSENCOS_d_ff2_Z[5]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_13_ ( .D(FPSENCOS_d_ff2_Y[13]), .CK(
n3445), .RN(n3323), .Q(FPSENCOS_d_ff3_sh_y_out[13]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_14_ ( .D(FPSENCOS_d_ff2_Y[14]), .CK(
n3445), .RN(n3322), .Q(FPSENCOS_d_ff3_sh_y_out[14]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_14_ ( .D(
FPSENCOS_first_mux_Z[14]), .CK(n3455), .RN(n3322), .Q(
FPSENCOS_d_ff2_Z[14]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_11_ ( .D(FPSENCOS_d_ff2_Y[11]), .CK(
n3445), .RN(n3321), .Q(FPSENCOS_d_ff3_sh_y_out[11]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_11_ ( .D(
FPSENCOS_first_mux_Z[11]), .CK(n3455), .RN(n3321), .Q(
FPSENCOS_d_ff2_Z[11]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_8_ ( .D(FPSENCOS_first_mux_Z[8]),
.CK(n3455), .RN(n3320), .Q(FPSENCOS_d_ff2_Z[8]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_10_ ( .D(
FPSENCOS_first_mux_Z[10]), .CK(n3455), .RN(n3319), .Q(
FPSENCOS_d_ff2_Z[10]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_12_ ( .D(FPSENCOS_d_ff2_Y[12]), .CK(
n3445), .RN(n3319), .Q(FPSENCOS_d_ff3_sh_y_out[12]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_12_ ( .D(
FPSENCOS_first_mux_Z[12]), .CK(n3455), .RN(n3339), .Q(
FPSENCOS_d_ff2_Z[12]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_1_ ( .D(FPSENCOS_d_ff2_Y[1]), .CK(n3446),
.RN(n3337), .Q(FPSENCOS_d_ff3_sh_y_out[1]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_1_ ( .D(FPSENCOS_first_mux_Z[1]),
.CK(n3457), .RN(n3336), .Q(FPSENCOS_d_ff2_Z[1]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_3_ ( .D(FPSENCOS_d_ff2_Y[3]), .CK(n3444),
.RN(n3336), .Q(FPSENCOS_d_ff3_sh_y_out[3]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_6_ ( .D(FPSENCOS_d_ff2_Y[6]), .CK(n3444),
.RN(n3335), .Q(FPSENCOS_d_ff3_sh_y_out[6]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_6_ ( .D(FPSENCOS_first_mux_Z[6]),
.CK(n3456), .RN(n3335), .Q(FPSENCOS_d_ff2_Z[6]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_7_ ( .D(FPSENCOS_d_ff2_Y[7]), .CK(n3444),
.RN(n3334), .Q(FPSENCOS_d_ff3_sh_y_out[7]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_7_ ( .D(FPSENCOS_first_mux_Z[7]),
.CK(n3454), .RN(n3334), .Q(FPSENCOS_d_ff2_Z[7]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_1_ ( .D(FPADDSUB_Data_array_SWR[1]),
.CK(n3400), .RN(n3311), .Q(FPADDSUB_Data_array_SWR[27]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_0_ ( .D(FPADDSUB_Data_array_SWR[0]),
.CK(n3398), .RN(n3311), .Q(FPADDSUB_Data_array_SWR[26]) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n3097), .CK(n3390),
.RN(n3367), .Q(FPMULT_Add_result[0]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[0]), .CK(n3382), .RN(n3375),
.Q(mult_result[0]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[1]), .CK(n3382), .RN(n3378),
.Q(mult_result[1]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[2]), .CK(n3380), .RN(n826),
.Q(mult_result[2]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[4]), .CK(n3380), .RN(n826),
.Q(mult_result[4]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[6]), .CK(n3380), .RN(n826),
.Q(mult_result[6]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[7]), .CK(n3380), .RN(n826),
.Q(mult_result[7]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[10]), .CK(n3382), .RN(n826),
.Q(mult_result[10]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[11]), .CK(n3382), .RN(n3371),
.Q(mult_result[11]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[12]), .CK(n3381), .RN(n1019),
.Q(mult_result[12]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[13]), .CK(n3380), .RN(n3376),
.Q(mult_result[13]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[14]), .CK(n3382), .RN(n3364),
.Q(mult_result[14]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[15]), .CK(n3381), .RN(n3369),
.Q(mult_result[15]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[16]), .CK(n3380), .RN(n3375),
.Q(mult_result[16]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[17]), .CK(n3381), .RN(n3376),
.Q(mult_result[17]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[18]), .CK(n3380), .RN(n3374),
.Q(mult_result[18]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[19]), .CK(n3381), .RN(n3365),
.Q(mult_result[19]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[20]), .CK(n3380), .RN(n1019),
.Q(mult_result[20]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[21]), .CK(n3381), .RN(n3378),
.Q(mult_result[21]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[22]), .CK(n3381), .RN(n3366),
.Q(mult_result[22]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[0]), .CK(n3382), .RN(n3372),
.Q(mult_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[1]), .CK(n3379), .RN(n3373),
.Q(mult_result[24]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[2]), .CK(n3379), .RN(n3377),
.Q(mult_result[25]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[3]), .CK(n3379), .RN(n3366),
.Q(mult_result[26]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[4]), .CK(n3379), .RN(n3370),
.Q(mult_result[27]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[5]), .CK(n3379), .RN(n3372),
.Q(mult_result[28]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[6]), .CK(n3379), .RN(n3370),
.Q(mult_result[29]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
FPMULT_final_result_ieee_Module_Exp_S_mux[7]), .CK(n3379), .RN(n3373),
.Q(mult_result[30]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(
FPADDSUB_DmP_EXP_EWSW[16]), .CK(n3406), .RN(n3287), .Q(
FPADDSUB_DmP_mant_SHT1_SW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(
FPADDSUB_DmP_EXP_EWSW[12]), .CK(n3408), .RN(n3295), .Q(
FPADDSUB_DmP_mant_SHT1_SW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[1]), .CK(n3406), .RN(n3280), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(FPADDSUB_DmP_EXP_EWSW[4]), .CK(n3408), .RN(n3290), .Q(FPADDSUB_DmP_mant_SHT1_SW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(FPADDSUB_DmP_EXP_EWSW[8]), .CK(n3407), .RN(n3293), .Q(FPADDSUB_DmP_mant_SHT1_SW[8]) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_46_ ( .D(
FPMULT_Sgf_operation_Result[46]), .CK(n3396), .RN(n3333), .Q(
FPMULT_P_Sgf[46]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(
FPADDSUB_Shift_amount_EXP_EW[0]), .CK(n3406), .RN(n3280), .Q(
FPADDSUB_Shift_amount_SHT1_EWR[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(
FPADDSUB_DmP_EXP_EWSW[20]), .CK(n3408), .RN(n3289), .Q(
FPADDSUB_DmP_mant_SHT1_SW[20]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_23_ ( .D(FPSENCOS_sh_exp_x[0]), .CK(
n3440), .RN(n3358), .Q(FPSENCOS_d_ff3_sh_x_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_24_ ( .D(FPSENCOS_sh_exp_x[1]), .CK(
n3441), .RN(n3358), .Q(FPSENCOS_d_ff3_sh_x_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_25_ ( .D(FPSENCOS_sh_exp_x[2]), .CK(
n3442), .RN(n3357), .Q(FPSENCOS_d_ff3_sh_x_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_27_ ( .D(FPSENCOS_sh_exp_x[4]), .CK(
n3440), .RN(n3357), .Q(FPSENCOS_d_ff3_sh_x_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_28_ ( .D(FPSENCOS_sh_exp_x[5]), .CK(
n3441), .RN(n3357), .Q(FPSENCOS_d_ff3_sh_x_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_29_ ( .D(FPSENCOS_sh_exp_x[6]), .CK(
n3442), .RN(n3357), .Q(FPSENCOS_d_ff3_sh_x_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_26_ ( .D(FPSENCOS_sh_exp_y[3]), .CK(
n3447), .RN(n3357), .Q(FPSENCOS_d_ff3_sh_y_out[26]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_23_ ( .D(FPSENCOS_mux_sal[23]), .CK(
n3478), .RN(n3354), .Q(cordic_result[23]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_24_ ( .D(FPSENCOS_mux_sal[24]), .CK(
n3478), .RN(n3354), .Q(cordic_result[24]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_25_ ( .D(FPSENCOS_mux_sal[25]), .CK(
n3476), .RN(n3354), .Q(cordic_result[25]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_26_ ( .D(FPSENCOS_mux_sal[26]), .CK(
n3478), .RN(n3353), .Q(cordic_result[26]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_27_ ( .D(FPSENCOS_mux_sal[27]), .CK(
n3477), .RN(n3353), .Q(cordic_result[27]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_28_ ( .D(FPSENCOS_mux_sal[28]), .CK(
n3477), .RN(n3353), .Q(cordic_result[28]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_29_ ( .D(FPSENCOS_mux_sal[29]), .CK(
n3477), .RN(n3352), .Q(cordic_result[29]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_30_ ( .D(FPSENCOS_mux_sal[30]), .CK(
n3477), .RN(n3352), .Q(cordic_result[30]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_22_ ( .D(FPSENCOS_d_ff2_X[22]), .CK(
n3440), .RN(n3350), .Q(FPSENCOS_d_ff3_sh_x_out[22]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_22_ ( .D(FPSENCOS_mux_sal[22]), .CK(
n3477), .RN(n3350), .Q(cordic_result[22]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_19_ ( .D(FPSENCOS_d_ff2_X[19]), .CK(
n3442), .RN(n3349), .Q(FPSENCOS_d_ff3_sh_x_out[19]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_19_ ( .D(FPSENCOS_mux_sal[19]), .CK(
n3477), .RN(n3349), .Q(cordic_result[19]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_21_ ( .D(FPSENCOS_d_ff2_X[21]), .CK(
n3440), .RN(n3348), .Q(FPSENCOS_d_ff3_sh_x_out[21]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_21_ ( .D(FPSENCOS_mux_sal[21]), .CK(
n3477), .RN(n3348), .Q(cordic_result[21]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_2_ ( .D(FPSENCOS_d_ff2_X[2]), .CK(n3441),
.RN(n3347), .Q(FPSENCOS_d_ff3_sh_x_out[2]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_2_ ( .D(FPSENCOS_mux_sal[2]), .CK(
n3477), .RN(n3330), .Q(cordic_result[2]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_16_ ( .D(FPSENCOS_d_ff2_X[16]), .CK(
n3442), .RN(n3330), .Q(FPSENCOS_d_ff3_sh_x_out[16]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_16_ ( .D(FPSENCOS_mux_sal[16]), .CK(
n3476), .RN(n3329), .Q(cordic_result[16]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_18_ ( .D(FPSENCOS_d_ff2_X[18]), .CK(
n3440), .RN(n3329), .Q(FPSENCOS_d_ff3_sh_x_out[18]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_18_ ( .D(FPSENCOS_mux_sal[18]), .CK(
n3475), .RN(n3329), .Q(cordic_result[18]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_20_ ( .D(FPSENCOS_d_ff2_X[20]), .CK(
n3441), .RN(n3328), .Q(FPSENCOS_d_ff3_sh_x_out[20]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_20_ ( .D(FPSENCOS_mux_sal[20]), .CK(
n3476), .RN(n3328), .Q(cordic_result[20]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_17_ ( .D(FPSENCOS_d_ff2_X[17]), .CK(
n3442), .RN(n3327), .Q(FPSENCOS_d_ff3_sh_x_out[17]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_17_ ( .D(FPSENCOS_mux_sal[17]), .CK(
n3475), .RN(n3327), .Q(cordic_result[17]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_4_ ( .D(FPSENCOS_d_ff2_Y[4]), .CK(n3445),
.RN(n3326), .Q(FPSENCOS_d_ff3_sh_y_out[4]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_4_ ( .D(FPSENCOS_mux_sal[4]), .CK(
n3476), .RN(n3326), .Q(cordic_result[4]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_15_ ( .D(FPSENCOS_d_ff2_X[15]), .CK(
n3440), .RN(n3325), .Q(FPSENCOS_d_ff3_sh_x_out[15]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_15_ ( .D(FPSENCOS_mux_sal[15]), .CK(
n3475), .RN(n3325), .Q(cordic_result[15]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_5_ ( .D(FPSENCOS_d_ff2_X[5]), .CK(n3441),
.RN(n3324), .Q(FPSENCOS_d_ff3_sh_x_out[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_5_ ( .D(FPSENCOS_mux_sal[5]), .CK(
n3475), .RN(n3324), .Q(cordic_result[5]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_13_ ( .D(FPSENCOS_d_ff2_X[13]), .CK(
n3443), .RN(n3323), .Q(FPSENCOS_d_ff3_sh_x_out[13]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_13_ ( .D(FPSENCOS_mux_sal[13]), .CK(
n3475), .RN(n3323), .Q(cordic_result[13]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_14_ ( .D(FPSENCOS_d_ff2_X[14]), .CK(
n3443), .RN(n3323), .Q(FPSENCOS_d_ff3_sh_x_out[14]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_14_ ( .D(FPSENCOS_mux_sal[14]), .CK(
n3475), .RN(n3322), .Q(cordic_result[14]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_11_ ( .D(FPSENCOS_d_ff2_X[11]), .CK(
n3443), .RN(n3322), .Q(FPSENCOS_d_ff3_sh_x_out[11]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_11_ ( .D(FPSENCOS_mux_sal[11]), .CK(
n3478), .RN(n3321), .Q(cordic_result[11]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_8_ ( .D(FPSENCOS_d_ff2_Y[8]), .CK(n3445),
.RN(n3320), .Q(FPSENCOS_d_ff3_sh_y_out[8]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_8_ ( .D(FPSENCOS_mux_sal[8]), .CK(
n3475), .RN(n3320), .Q(cordic_result[8]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_10_ ( .D(FPSENCOS_d_ff2_Y[10]), .CK(
n3445), .RN(n3320), .Q(FPSENCOS_d_ff3_sh_y_out[10]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_10_ ( .D(FPSENCOS_mux_sal[10]), .CK(
n3476), .RN(n3319), .Q(cordic_result[10]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_12_ ( .D(FPSENCOS_d_ff2_X[12]), .CK(
n3443), .RN(n3319), .Q(FPSENCOS_d_ff3_sh_x_out[12]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_12_ ( .D(FPSENCOS_mux_sal[12]), .CK(
n3478), .RN(n3324), .Q(cordic_result[12]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_9_ ( .D(FPSENCOS_d_ff2_Y[9]), .CK(n3445),
.RN(n3339), .Q(FPSENCOS_d_ff3_sh_y_out[9]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_9_ ( .D(FPSENCOS_mux_sal[9]), .CK(
n3475), .RN(n1139), .Q(cordic_result[9]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_31_ ( .D(FPSENCOS_fmtted_Result_31_),
.CK(n3476), .RN(n1137), .Q(cordic_result[31]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_0_ ( .D(FPSENCOS_d_ff2_Y[0]), .CK(n3444),
.RN(n3338), .Q(FPSENCOS_d_ff3_sh_y_out[0]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_0_ ( .D(FPSENCOS_mux_sal[0]), .CK(
n3478), .RN(n3338), .Q(cordic_result[0]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_1_ ( .D(FPSENCOS_d_ff2_X[1]), .CK(n3443),
.RN(n3337), .Q(FPSENCOS_d_ff3_sh_x_out[1]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_1_ ( .D(FPSENCOS_mux_sal[1]), .CK(
n3475), .RN(n3337), .Q(cordic_result[1]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_3_ ( .D(FPSENCOS_d_ff2_X[3]), .CK(n3444),
.RN(n3336), .Q(FPSENCOS_d_ff3_sh_x_out[3]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_3_ ( .D(FPSENCOS_mux_sal[3]), .CK(
n3476), .RN(n3336), .Q(cordic_result[3]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_6_ ( .D(FPSENCOS_d_ff2_X[6]), .CK(n3444),
.RN(n3335), .Q(FPSENCOS_d_ff3_sh_x_out[6]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_6_ ( .D(FPSENCOS_mux_sal[6]), .CK(
n3478), .RN(n3335), .Q(cordic_result[6]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_7_ ( .D(FPSENCOS_d_ff2_X[7]), .CK(n3444),
.RN(n3334), .Q(FPSENCOS_d_ff3_sh_x_out[7]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_7_ ( .D(FPSENCOS_mux_sal[7]), .CK(
n3475), .RN(n3334), .Q(cordic_result[7]) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(
FPMULT_Adder_M_result_A_adder[23]), .CK(n3390), .RN(n3377), .Q(
FPMULT_Add_result[23]) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_23_ ( .D(
FPMULT_Sgf_operation_Result[23]), .CK(n3397), .RN(n3331), .Q(
FPMULT_P_Sgf[23]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_1_ ( .D(n862), .CK(n3439), .RN(n3343), .Q(
FPSENCOS_d_ff3_LUT_out[1]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_2_ ( .D(n856), .CK(n3439), .RN(n3343), .Q(
FPSENCOS_d_ff3_LUT_out[2]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_6_ ( .D(n855), .CK(n3439), .RN(n3342), .Q(
FPSENCOS_d_ff3_LUT_out[6]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_12_ ( .D(n860), .CK(n3441), .RN(n3342), .Q(
FPSENCOS_d_ff3_LUT_out[12]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_24_ ( .D(n848), .CK(n3442), .RN(n3341), .Q(
FPSENCOS_d_ff3_LUT_out[24]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_25_ ( .D(FPSENCOS_data_out_LUT[25]), .CK(
n3440), .RN(n3341), .Q(FPSENCOS_d_ff3_LUT_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_26_ ( .D(FPSENCOS_sh_exp_x[3]), .CK(
n3441), .RN(n3357), .Q(FPSENCOS_d_ff3_sh_x_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_23_ ( .D(FPSENCOS_sh_exp_y[0]), .CK(
n3446), .RN(n3357), .Q(FPSENCOS_d_ff3_sh_y_out[23]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_24_ ( .D(
FPSENCOS_first_mux_Z[24]), .CK(n3456), .RN(n3352), .Q(
FPSENCOS_d_ff2_Z[24]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_21_ ( .D(FPSENCOS_d_ff2_Y[21]), .CK(
n3446), .RN(n3348), .Q(FPSENCOS_d_ff3_sh_y_out[21]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_21_ ( .D(
FPSENCOS_first_mux_Z[21]), .CK(n3457), .RN(n3348), .Q(
FPSENCOS_d_ff2_Z[21]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_2_ ( .D(FPSENCOS_first_mux_Z[2]),
.CK(n3456), .RN(n3330), .Q(FPSENCOS_d_ff2_Z[2]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_16_ ( .D(
FPSENCOS_first_mux_Z[16]), .CK(n3457), .RN(n3329), .Q(
FPSENCOS_d_ff2_Z[16]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_17_ ( .D(
FPSENCOS_first_mux_Z[17]), .CK(n3456), .RN(n3327), .Q(
FPSENCOS_d_ff2_Z[17]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_4_ ( .D(FPSENCOS_d_ff2_X[4]), .CK(n3442),
.RN(n3326), .Q(FPSENCOS_d_ff3_sh_x_out[4]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_13_ ( .D(
FPSENCOS_first_mux_Z[13]), .CK(n3455), .RN(n3323), .Q(
FPSENCOS_d_ff2_Z[13]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_8_ ( .D(FPSENCOS_d_ff2_X[8]), .CK(n3443),
.RN(n3321), .Q(FPSENCOS_d_ff3_sh_x_out[8]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_10_ ( .D(FPSENCOS_d_ff2_X[10]), .CK(
n3443), .RN(n3320), .Q(FPSENCOS_d_ff3_sh_x_out[10]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_9_ ( .D(FPSENCOS_d_ff2_X[9]), .CK(n3443),
.RN(n3339), .Q(FPSENCOS_d_ff3_sh_x_out[9]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_9_ ( .D(FPSENCOS_first_mux_Z[9]),
.CK(n3455), .RN(n1137), .Q(FPSENCOS_d_ff2_Z[9]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_0_ ( .D(FPSENCOS_d_ff2_X[0]), .CK(n3443),
.RN(n3338), .Q(FPSENCOS_d_ff3_sh_x_out[0]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_0_ ( .D(FPSENCOS_first_mux_Z[0]),
.CK(n3454), .RN(n3337), .Q(FPSENCOS_d_ff2_Z[0]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_3_ ( .D(FPSENCOS_first_mux_Z[3]),
.CK(n3454), .RN(n3336), .Q(FPSENCOS_d_ff2_Z[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[0]), .CK(n915), .RN(n3316), .Q(
FPADDSUB_DMP_exp_NRM2_EW[0]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[1]), .CK(n915), .RN(n3316), .Q(
FPADDSUB_DMP_exp_NRM2_EW[1]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[2]), .CK(n915), .RN(n3316), .Q(
FPADDSUB_DMP_exp_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[3]), .CK(n915), .RN(n3317), .Q(
FPADDSUB_DMP_exp_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[4]), .CK(n915), .RN(n3317), .Q(
FPADDSUB_DMP_exp_NRM2_EW[4]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[5]), .CK(n915), .RN(n3317), .Q(
FPADDSUB_DMP_exp_NRM2_EW[5]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[6]), .CK(n915), .RN(n3317), .Q(
FPADDSUB_DMP_exp_NRM2_EW[6]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(
FPADDSUB_DMP_exp_NRM_EW[7]), .CK(n915), .RN(n3318), .Q(
FPADDSUB_DMP_exp_NRM2_EW[7]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n819), .CK(n3398), .RN(
n3314), .Q(FPADDSUB_SIGN_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n813), .CK(n3398), .RN(
n1303), .Q(FPADDSUB_OP_FLAG_SHT2) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_3_ ( .D(busy), .CK(n913), .RN(
n3279), .Q(FPADDSUB_Shift_reg_FLAGS_7[3]) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_5_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7_6), .CK(n913), .RN(n3279), .Q(
FPADDSUB_Shift_reg_FLAGS_7_5) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_2_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7[3]), .CK(n913), .RN(n3279), .Q(
FPADDSUB_Shift_reg_FLAGS_7[2]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(n3434),
.RN(n3354), .Q(FPSENCOS_d_ff_Yn[23]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(n3434),
.RN(n3354), .Q(FPSENCOS_d_ff_Yn[24]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(n3432),
.RN(n3354), .Q(FPSENCOS_d_ff_Yn[25]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(n3434),
.RN(n3354), .Q(FPSENCOS_d_ff_Yn[26]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(n3433),
.RN(n3353), .Q(FPSENCOS_d_ff_Yn[27]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(n3433),
.RN(n3353), .Q(FPSENCOS_d_ff_Yn[28]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(n3433),
.RN(n3353), .Q(FPSENCOS_d_ff_Yn[29]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(n3433),
.RN(n3352), .Q(FPSENCOS_d_ff_Yn[30]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(n3433),
.RN(n3350), .Q(FPSENCOS_d_ff_Yn[22]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(n3433),
.RN(n3349), .Q(FPSENCOS_d_ff_Yn[19]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(n3433),
.RN(n3348), .Q(FPSENCOS_d_ff_Yn[21]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(n3433),
.RN(n3347), .Q(FPSENCOS_d_ff_Yn[2]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(n3432),
.RN(n3330), .Q(FPSENCOS_d_ff_Yn[16]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(n3431),
.RN(n3329), .Q(FPSENCOS_d_ff_Yn[18]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(n3432),
.RN(n3328), .Q(FPSENCOS_d_ff_Yn[20]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(n3431),
.RN(n3327), .Q(FPSENCOS_d_ff_Yn[17]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(n3432),
.RN(n3326), .Q(FPSENCOS_d_ff_Yn[4]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(n3431),
.RN(n3325), .Q(FPSENCOS_d_ff_Yn[15]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(n3431),
.RN(n3324), .Q(FPSENCOS_d_ff_Yn[5]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(n3431),
.RN(n3323), .Q(FPSENCOS_d_ff_Yn[13]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(n3431),
.RN(n3322), .Q(FPSENCOS_d_ff_Yn[14]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(n3434),
.RN(n3322), .Q(FPSENCOS_d_ff_Yn[11]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(n3431),
.RN(n3321), .Q(FPSENCOS_d_ff_Yn[8]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(n3432),
.RN(n3320), .Q(FPSENCOS_d_ff_Yn[10]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(n3434),
.RN(n3319), .Q(FPSENCOS_d_ff_Yn[12]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(n3431),
.RN(n3339), .Q(FPSENCOS_d_ff_Yn[9]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(n3432),
.RN(n3338), .Q(FPSENCOS_d_ff_Yn[0]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(n3434),
.RN(n3337), .Q(FPSENCOS_d_ff_Yn[1]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(n3431),
.RN(n3336), .Q(FPSENCOS_d_ff_Yn[3]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(n3432),
.RN(n3335), .Q(FPSENCOS_d_ff_Yn[6]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(n3434),
.RN(n3334), .Q(FPSENCOS_d_ff_Yn[7]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(n3438),
.RN(n3356), .Q(FPSENCOS_d_ff_Xn[23]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(n3437),
.RN(n3355), .Q(FPSENCOS_d_ff_Xn[30]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(n3435),
.RN(n3350), .Q(FPSENCOS_d_ff_Xn[22]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(n3437),
.RN(n3349), .Q(FPSENCOS_d_ff_Xn[21]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(n3437),
.RN(n3329), .Q(FPSENCOS_d_ff_Xn[18]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(n3438),
.RN(n3326), .Q(FPSENCOS_d_ff_Xn[4]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(n3436),
.RN(n3326), .Q(FPSENCOS_d_ff_Xn[15]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(n3436),
.RN(n3322), .Q(FPSENCOS_d_ff_Xn[11]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(n3435),
.RN(n3321), .Q(FPSENCOS_d_ff_Xn[8]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(n3437),
.RN(n3339), .Q(FPSENCOS_d_ff_Xn[9]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(n3438),
.RN(n3338), .Q(FPSENCOS_d_ff_Xn[0]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n816), .CK(n3398), .RN(
n1301), .Q(FPADDSUB_SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_29_ ( .D(Data_2[29]),
.CK(n3383), .RN(n3364), .Q(FPMULT_Op_MY[29]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_24_ ( .D(Data_2[24]),
.CK(n3383), .RN(n3369), .Q(FPMULT_Op_MY[24]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_26_ ( .D(Data_2[26]),
.CK(n3383), .RN(n3365), .Q(FPMULT_Op_MY[26]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(n3438),
.RN(n3356), .Q(FPSENCOS_d_ff_Xn[24]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(n3435),
.RN(n3356), .Q(FPSENCOS_d_ff_Xn[25]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(n3437),
.RN(n3355), .Q(FPSENCOS_d_ff_Xn[26]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(n3435),
.RN(n3355), .Q(FPSENCOS_d_ff_Xn[27]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(n3435),
.RN(n3355), .Q(FPSENCOS_d_ff_Xn[28]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(n3435),
.RN(n3355), .Q(FPSENCOS_d_ff_Xn[29]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(n3435),
.RN(n3349), .Q(FPSENCOS_d_ff_Xn[19]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(n3438),
.RN(n3348), .Q(FPSENCOS_d_ff_Xn[2]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(n3436),
.RN(n3330), .Q(FPSENCOS_d_ff_Xn[16]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(n3436),
.RN(n3328), .Q(FPSENCOS_d_ff_Xn[20]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(n3436),
.RN(n3327), .Q(FPSENCOS_d_ff_Xn[17]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(n3436),
.RN(n3325), .Q(FPSENCOS_d_ff_Xn[5]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(n3436),
.RN(n3324), .Q(FPSENCOS_d_ff_Xn[13]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(n3436),
.RN(n3323), .Q(FPSENCOS_d_ff_Xn[14]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(n3435),
.RN(n3320), .Q(FPSENCOS_d_ff_Xn[10]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(n3437),
.RN(n3319), .Q(FPSENCOS_d_ff_Xn[12]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(n3438),
.RN(n3337), .Q(FPSENCOS_d_ff_Xn[1]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(n3435),
.RN(n3336), .Q(FPSENCOS_d_ff_Xn[3]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(n3437),
.RN(n3335), .Q(FPSENCOS_d_ff_Xn[6]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(n3438),
.RN(n3335), .Q(FPSENCOS_d_ff_Xn[7]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_28_ ( .D(Data_2[28]),
.CK(n3383), .RN(n3371), .Q(FPMULT_Op_MY[28]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_25_ ( .D(Data_2[25]),
.CK(n3383), .RN(n3369), .Q(FPMULT_Op_MY[25]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_8_ ( .D(
FPMULT_Exp_module_Data_S[8]), .CK(
FPMULT_Exp_module_exp_result_m_net5038776), .RN(n3373), .Q(
FPMULT_exp_oper_result[8]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_27_ ( .D(Data_2[27]),
.CK(n3383), .RN(n3376), .Q(FPMULT_Op_MY[27]) );
DFFRXLTS FPSENCOS_reg_sign_Q_reg_0_ ( .D(FPSENCOS_d_ff2_Z[31]), .CK(n3444),
.RN(n3338), .Q(FPSENCOS_d_ff3_sign_out) );
DFFRXLTS FPMULT_Sgf_operation_finalreg_Q_reg_47_ ( .D(
FPMULT_Sgf_operation_Result[47]), .CK(n3396), .RN(n3334), .Q(
FPMULT_P_Sgf[47]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_23_ ( .D(Data_2[23]),
.CK(n3383), .RN(n3371), .Q(FPMULT_Op_MY[23]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_21_ ( .D(
FPSENCOS_first_mux_X[21]), .CK(n3452), .RN(n3348), .Q(
FPSENCOS_d_ff2_X[21]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_2_ ( .D(FPSENCOS_first_mux_X[2]),
.CK(n3449), .RN(n3348), .Q(FPSENCOS_d_ff2_X[2]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_16_ ( .D(
FPSENCOS_first_mux_X[16]), .CK(n3453), .RN(n3330), .Q(
FPSENCOS_d_ff2_X[16]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_17_ ( .D(
FPSENCOS_first_mux_X[17]), .CK(n3451), .RN(n3327), .Q(
FPSENCOS_d_ff2_X[17]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_13_ ( .D(
FPSENCOS_first_mux_X[13]), .CK(n3452), .RN(n3324), .Q(
FPSENCOS_d_ff2_X[13]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_9_ ( .D(FPSENCOS_first_mux_X[9]),
.CK(n3450), .RN(n3339), .Q(FPSENCOS_d_ff2_X[9]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_31_ ( .D(
FPSENCOS_first_mux_X[31]), .CK(n3450), .RN(n1137), .Q(
FPSENCOS_d_ff2_X[31]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_0_ ( .D(FPSENCOS_first_mux_X[0]),
.CK(n3450), .RN(n3338), .Q(FPSENCOS_d_ff2_X[0]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_3_ ( .D(FPSENCOS_first_mux_X[3]),
.CK(n3450), .RN(n3336), .Q(FPSENCOS_d_ff2_X[3]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_7_ ( .D(
FPMULT_Exp_module_Data_S[7]), .CK(
FPMULT_Exp_module_exp_result_m_net5038776), .RN(n3368), .Q(
FPMULT_exp_oper_result[7]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_6_ ( .D(
FPMULT_Exp_module_Data_S[6]), .CK(
FPMULT_Exp_module_exp_result_m_net5038776), .RN(n3370), .Q(
FPMULT_exp_oper_result[6]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_5_ ( .D(
FPMULT_Exp_module_Data_S[5]), .CK(
FPMULT_Exp_module_exp_result_m_net5038776), .RN(n3378), .Q(
FPMULT_exp_oper_result[5]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_4_ ( .D(
FPMULT_Exp_module_Data_S[4]), .CK(
FPMULT_Exp_module_exp_result_m_net5038776), .RN(n3368), .Q(
FPMULT_exp_oper_result[4]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_3_ ( .D(
FPMULT_Exp_module_Data_S[3]), .CK(
FPMULT_Exp_module_exp_result_m_net5038776), .RN(n3366), .Q(
FPMULT_exp_oper_result[3]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_2_ ( .D(
FPMULT_Exp_module_Data_S[2]), .CK(
FPMULT_Exp_module_exp_result_m_net5038776), .RN(n3367), .Q(
FPMULT_exp_oper_result[2]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_1_ ( .D(
FPMULT_Exp_module_Data_S[1]), .CK(
FPMULT_Exp_module_exp_result_m_net5038776), .RN(n3367), .Q(
FPMULT_exp_oper_result[1]) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_0_ ( .D(
FPMULT_Exp_module_Data_S[0]), .CK(
FPMULT_Exp_module_exp_result_m_net5038776), .RN(n3370), .Q(
FPMULT_exp_oper_result[0]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_30_ ( .D(Data_2[30]),
.CK(n3383), .RN(n3374), .Q(FPMULT_Op_MY[30]) );
DFFRXLTS reg_dataB_Q_reg_27_ ( .D(Data_2[27]), .CK(n1291), .RN(n3345), .Q(
dataB[27]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_27_ ( .D(FPADDSUB_DMP_INIT_EWSW[27]),
.CK(n3419), .RN(n3283), .Q(FPADDSUB_DMP_EXP_EWSW[27]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_23_ ( .D(FPADDSUB_DmP_INIT_EWSW[23]),
.CK(n3413), .RN(n3281), .Q(FPADDSUB_DmP_EXP_EWSW[23]) );
DFFRXLTS reg_dataB_Q_reg_29_ ( .D(Data_2[29]), .CK(n3485), .RN(n3345), .Q(
dataB[29]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_22_ ( .D(
FPSENCOS_first_mux_X[22]), .CK(n3448), .RN(n3350), .Q(
FPSENCOS_d_ff2_X[22]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_19_ ( .D(
FPSENCOS_first_mux_X[19]), .CK(n3448), .RN(n3349), .Q(
FPSENCOS_d_ff2_X[19]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_21_ ( .D(
FPSENCOS_first_mux_Y[21]), .CK(n3453), .RN(n3348), .Q(
FPSENCOS_d_ff2_Y[21]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_2_ ( .D(FPSENCOS_first_mux_Y[2]),
.CK(n3451), .RN(n3353), .Q(FPSENCOS_d_ff2_Y[2]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_16_ ( .D(
FPSENCOS_first_mux_Y[16]), .CK(n3452), .RN(n3330), .Q(
FPSENCOS_d_ff2_Y[16]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_18_ ( .D(
FPSENCOS_first_mux_Y[18]), .CK(n3449), .RN(n3329), .Q(
FPSENCOS_d_ff2_Y[18]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_20_ ( .D(
FPSENCOS_first_mux_Y[20]), .CK(n3453), .RN(n3328), .Q(
FPSENCOS_d_ff2_Y[20]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_17_ ( .D(
FPSENCOS_first_mux_Y[17]), .CK(n3451), .RN(n3327), .Q(
FPSENCOS_d_ff2_Y[17]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_4_ ( .D(FPSENCOS_first_mux_Y[4]),
.CK(n3453), .RN(n3326), .Q(FPSENCOS_d_ff2_Y[4]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_15_ ( .D(
FPSENCOS_first_mux_X[15]), .CK(n3449), .RN(n3325), .Q(
FPSENCOS_d_ff2_X[15]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_5_ ( .D(FPSENCOS_first_mux_X[5]),
.CK(n3453), .RN(n3325), .Q(FPSENCOS_d_ff2_X[5]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_13_ ( .D(
FPSENCOS_first_mux_Y[13]), .CK(n3453), .RN(n3323), .Q(
FPSENCOS_d_ff2_Y[13]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_14_ ( .D(
FPSENCOS_first_mux_X[14]), .CK(n3450), .RN(n3323), .Q(
FPSENCOS_d_ff2_X[14]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_11_ ( .D(
FPSENCOS_first_mux_Y[11]), .CK(n3451), .RN(n3321), .Q(
FPSENCOS_d_ff2_Y[11]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_8_ ( .D(FPSENCOS_first_mux_X[8]),
.CK(n3450), .RN(n3321), .Q(FPSENCOS_d_ff2_X[8]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_10_ ( .D(
FPSENCOS_first_mux_X[10]), .CK(n3450), .RN(n3320), .Q(
FPSENCOS_d_ff2_X[10]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_12_ ( .D(
FPSENCOS_first_mux_X[12]), .CK(n3450), .RN(n3319), .Q(
FPSENCOS_d_ff2_X[12]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_9_ ( .D(FPSENCOS_first_mux_Y[9]),
.CK(n3452), .RN(n3339), .Q(FPSENCOS_d_ff2_Y[9]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_31_ ( .D(
FPSENCOS_first_mux_Y[31]), .CK(n3449), .RN(n1137), .Q(
FPSENCOS_d_ff2_Y[31]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_0_ ( .D(FPSENCOS_first_mux_Y[0]),
.CK(n3453), .RN(n3338), .Q(FPSENCOS_d_ff2_Y[0]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_1_ ( .D(FPSENCOS_first_mux_X[1]),
.CK(n3450), .RN(n3337), .Q(FPSENCOS_d_ff2_X[1]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_3_ ( .D(FPSENCOS_first_mux_Y[3]),
.CK(n3454), .RN(n3336), .Q(FPSENCOS_d_ff2_Y[3]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_6_ ( .D(FPSENCOS_first_mux_Y[6]),
.CK(n3454), .RN(n3335), .Q(FPSENCOS_d_ff2_Y[6]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_7_ ( .D(FPSENCOS_first_mux_X[7]),
.CK(n3452), .RN(n3334), .Q(FPSENCOS_d_ff2_X[7]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_22_ ( .D(
FPSENCOS_first_mux_Y[22]), .CK(n3452), .RN(n3350), .Q(
FPSENCOS_d_ff2_Y[22]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_19_ ( .D(
FPSENCOS_first_mux_Y[19]), .CK(n3449), .RN(n3349), .Q(
FPSENCOS_d_ff2_Y[19]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_18_ ( .D(
FPSENCOS_first_mux_X[18]), .CK(n3451), .RN(n3329), .Q(
FPSENCOS_d_ff2_X[18]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_20_ ( .D(
FPSENCOS_first_mux_X[20]), .CK(n3452), .RN(n3328), .Q(
FPSENCOS_d_ff2_X[20]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_4_ ( .D(FPSENCOS_first_mux_X[4]),
.CK(n3449), .RN(n3326), .Q(FPSENCOS_d_ff2_X[4]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_15_ ( .D(
FPSENCOS_first_mux_Y[15]), .CK(n3451), .RN(n3325), .Q(
FPSENCOS_d_ff2_Y[15]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_5_ ( .D(FPSENCOS_first_mux_Y[5]),
.CK(n3451), .RN(n3324), .Q(FPSENCOS_d_ff2_Y[5]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_14_ ( .D(
FPSENCOS_first_mux_Y[14]), .CK(n3452), .RN(n3322), .Q(
FPSENCOS_d_ff2_Y[14]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_11_ ( .D(
FPSENCOS_first_mux_X[11]), .CK(n3450), .RN(n3322), .Q(
FPSENCOS_d_ff2_X[11]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_8_ ( .D(FPSENCOS_first_mux_Y[8]),
.CK(n3449), .RN(n3321), .Q(FPSENCOS_d_ff2_Y[8]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_10_ ( .D(
FPSENCOS_first_mux_Y[10]), .CK(n3453), .RN(n3320), .Q(
FPSENCOS_d_ff2_Y[10]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_12_ ( .D(
FPSENCOS_first_mux_Y[12]), .CK(n3451), .RN(n3319), .Q(
FPSENCOS_d_ff2_Y[12]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_31_ ( .D(
FPSENCOS_first_mux_Z[31]), .CK(n3454), .RN(n3338), .Q(
FPSENCOS_d_ff2_Z[31]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_1_ ( .D(FPSENCOS_first_mux_Y[1]),
.CK(n3454), .RN(n3337), .Q(FPSENCOS_d_ff2_Y[1]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_6_ ( .D(FPSENCOS_first_mux_X[6]),
.CK(n3449), .RN(n3335), .Q(FPSENCOS_d_ff2_X[6]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_7_ ( .D(FPSENCOS_first_mux_Y[7]),
.CK(n3454), .RN(n3334), .Q(FPSENCOS_d_ff2_Y[7]) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_26_ ( .D(Data_1[26]),
.CK(n3388), .RN(n3372), .Q(FPMULT_Op_MX[26]) );
DFFRX1TS reg_dataA_Q_reg_28_ ( .D(Data_1[28]), .CK(n1291), .RN(n3346), .Q(
dataA[28]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[25]), .CK(n3470), .RN(n3314), .Q(
FPADDSUB_DmP_mant_SFG_SWR[25]) );
DFFRX1TS reg_dataA_Q_reg_27_ ( .D(Data_1[27]), .CK(n3482), .RN(n3346), .Q(
dataA[27]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(n3431),
.RN(n1137), .Q(FPSENCOS_d_ff_Yn[31]) );
DFFRXLTS reg_dataB_Q_reg_25_ ( .D(Data_2[25]), .CK(clk), .RN(n3345), .Q(
dataB[25]) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_25_ ( .D(Data_1[25]),
.CK(n3388), .RN(n3367), .Q(FPMULT_Op_MX[25]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(n3435),
.RN(n1137), .Q(FPSENCOS_d_ff_Xn[31]) );
DFFRX1TS reg_dataA_Q_reg_30_ ( .D(Data_1[30]), .CK(n3485), .RN(n3346), .Q(
dataA[30]) );
DFFRX1TS reg_dataA_Q_reg_29_ ( .D(Data_1[29]), .CK(n3482), .RN(n3346), .Q(
dataA[29]) );
DFFRX1TS reg_dataB_Q_reg_30_ ( .D(Data_2[30]), .CK(n3481), .RN(n3345), .Q(
dataB[30]) );
DFFRX1TS FPMULT_Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n106), .CK(
n916), .RN(n3378), .Q(FPMULT_zero_flag) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_30_ ( .D(
FPSENCOS_first_mux_Y[30]), .CK(n3453), .RN(n3352), .Q(
FPSENCOS_d_ff2_Y[30]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_30_ ( .D(
FPSENCOS_first_mux_X[30]), .CK(n3448), .RN(n3355), .Q(
FPSENCOS_d_ff2_X[30]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_5_ ( .D(FPADDSUB_Data_array_SWR[5]),
.CK(n3401), .RN(n3288), .Q(FPADDSUB_Data_array_SWR[31]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(add_subt_data1[31]),
.CK(n3422), .RN(n3295), .Q(FPADDSUB_intDX_EWSW[31]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(
FPMULT_Adder_M_result_A_adder[22]), .CK(n3389), .RN(n3367), .Q(
FPMULT_Add_result[22]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(
FPMULT_Adder_M_result_A_adder[21]), .CK(n3389), .RN(n3375), .Q(
FPMULT_Add_result[21]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_6_ ( .D(FPADDSUB_Data_array_SWR[6]),
.CK(n3399), .RN(n3289), .Q(FPADDSUB_Data_array_SWR[32]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(
FPMULT_Adder_M_result_A_adder[20]), .CK(n3389), .RN(n3375), .Q(
FPMULT_Add_result[20]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(
FPMULT_Adder_M_result_A_adder[19]), .CK(n3389), .RN(n3375), .Q(
FPMULT_Add_result[19]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_30_ ( .D(
FPMULT_Sgf_operation_Result[30]), .CK(n3395), .RN(n3332), .Q(
FPMULT_P_Sgf[30]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_27_ ( .D(
FPMULT_Sgf_operation_Result[27]), .CK(n3395), .RN(n3331), .Q(
FPMULT_P_Sgf[27]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_25_ ( .D(
FPMULT_Sgf_operation_Result[25]), .CK(n3395), .RN(n3331), .Q(
FPMULT_P_Sgf[25]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_38_ ( .D(
FPMULT_Sgf_operation_Result[38]), .CK(n3397), .RN(n3332), .Q(
FPMULT_P_Sgf[38]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_37_ ( .D(
FPMULT_Sgf_operation_Result[37]), .CK(
FPMULT_Sgf_operation_finalreg_net5038758), .RN(n3332), .Q(
FPMULT_P_Sgf[37]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_36_ ( .D(
FPMULT_Sgf_operation_Result[36]), .CK(n3397), .RN(n3332), .Q(
FPMULT_P_Sgf[36]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_35_ ( .D(
FPMULT_Sgf_operation_Result[35]), .CK(
FPMULT_Sgf_operation_finalreg_net5038758), .RN(n3332), .Q(
FPMULT_P_Sgf[35]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_34_ ( .D(
FPMULT_Sgf_operation_Result[34]), .CK(
FPMULT_Sgf_operation_finalreg_net5038758), .RN(n3332), .Q(
FPMULT_P_Sgf[34]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_33_ ( .D(
FPMULT_Sgf_operation_Result[33]), .CK(
FPMULT_Sgf_operation_finalreg_net5038758), .RN(n3332), .Q(
FPMULT_P_Sgf[33]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_32_ ( .D(
FPMULT_Sgf_operation_Result[32]), .CK(n3397), .RN(n3332), .Q(
FPMULT_P_Sgf[32]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_31_ ( .D(
FPMULT_Sgf_operation_Result[31]), .CK(
FPMULT_Sgf_operation_finalreg_net5038758), .RN(n3332), .Q(
FPMULT_P_Sgf[31]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_29_ ( .D(
FPMULT_Sgf_operation_Result[29]), .CK(
FPMULT_Sgf_operation_finalreg_net5038758), .RN(n3331), .Q(
FPMULT_P_Sgf[29]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_28_ ( .D(
FPMULT_Sgf_operation_Result[28]), .CK(
FPMULT_Sgf_operation_finalreg_net5038758), .RN(n3486), .Q(
FPMULT_P_Sgf[28]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_26_ ( .D(
FPMULT_Sgf_operation_Result[26]), .CK(n3397), .RN(n3486), .Q(
FPMULT_P_Sgf[26]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_24_ ( .D(
FPMULT_Sgf_operation_Result[24]), .CK(
FPMULT_Sgf_operation_finalreg_net5038758), .RN(n3486), .Q(
FPMULT_P_Sgf[24]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_43_ ( .D(
FPMULT_Sgf_operation_Result[43]), .CK(n3396), .RN(n3333), .Q(
FPMULT_P_Sgf[43]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_42_ ( .D(
FPMULT_Sgf_operation_Result[42]), .CK(n3396), .RN(n3333), .Q(
FPMULT_P_Sgf[42]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_41_ ( .D(
FPMULT_Sgf_operation_Result[41]), .CK(n3396), .RN(n3333), .Q(
FPMULT_P_Sgf[41]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_40_ ( .D(
FPMULT_Sgf_operation_Result[40]), .CK(n3396), .RN(n3333), .Q(
FPMULT_P_Sgf[40]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_39_ ( .D(
FPMULT_Sgf_operation_Result[39]), .CK(n3396), .RN(n3332), .Q(
FPMULT_P_Sgf[39]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_7_ ( .D(FPADDSUB_Data_array_SWR[7]),
.CK(n3400), .RN(n3291), .Q(FPADDSUB_Data_array_SWR[33]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_4_ ( .D(FPADDSUB_Data_array_SWR[4]),
.CK(n3401), .RN(n3309), .Q(FPADDSUB_Data_array_SWR[30]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(
FPMULT_Adder_M_result_A_adder[18]), .CK(n3391), .RN(n3374), .Q(
FPMULT_Add_result[18]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(
FPMULT_Adder_M_result_A_adder[17]), .CK(n3391), .RN(n1019), .Q(
FPMULT_Add_result[17]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(
FPMULT_Adder_M_result_A_adder[16]), .CK(n3391), .RN(n3364), .Q(
FPMULT_Add_result[16]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(
FPMULT_Adder_M_result_A_adder[15]), .CK(n3391), .RN(n3376), .Q(
FPMULT_Add_result[15]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(
FPMULT_Adder_M_result_A_adder[14]), .CK(n3391), .RN(n3374), .Q(
FPMULT_Add_result[14]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(
FPMULT_Adder_M_result_A_adder[13]), .CK(n3390), .RN(n3365), .Q(
FPMULT_Add_result[13]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(
FPMULT_Adder_M_result_A_adder[12]), .CK(n3390), .RN(n3365), .Q(
FPMULT_Add_result[12]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(
FPMULT_Adder_M_result_A_adder[11]), .CK(n3390), .RN(n1018), .Q(
FPMULT_Add_result[11]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(
FPMULT_Adder_M_result_A_adder[10]), .CK(n3390), .RN(n3365), .Q(
FPMULT_Add_result[10]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(
FPMULT_Adder_M_result_A_adder[9]), .CK(n3390), .RN(n3364), .Q(
FPMULT_Add_result[9]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(
FPMULT_Adder_M_result_A_adder[8]), .CK(n3389), .RN(n1019), .Q(
FPMULT_Add_result[8]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(
FPMULT_Adder_M_result_A_adder[7]), .CK(n3391), .RN(n3371), .Q(
FPMULT_Add_result[7]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(
FPMULT_Adder_M_result_A_adder[6]), .CK(n3389), .RN(n3376), .Q(
FPMULT_Add_result[6]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(
FPMULT_Adder_M_result_A_adder[5]), .CK(n3391), .RN(n3376), .Q(
FPMULT_Add_result[5]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(
FPMULT_Adder_M_result_A_adder[4]), .CK(n3389), .RN(n3365), .Q(
FPMULT_Add_result[4]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(
FPMULT_Adder_M_result_A_adder[3]), .CK(n3391), .RN(n1018), .Q(
FPMULT_Add_result[3]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(
FPMULT_Adder_M_result_A_adder[2]), .CK(n3389), .RN(n3371), .Q(
FPMULT_Add_result[2]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(
FPMULT_Adder_M_result_A_adder[1]), .CK(n3389), .RN(n3366), .Q(
FPMULT_Add_result[1]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_24_ ( .D(FPADDSUB_DMP_INIT_EWSW[24]),
.CK(n3419), .RN(n3282), .Q(FPADDSUB_DMP_EXP_EWSW[24]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_25_ ( .D(FPADDSUB_DMP_INIT_EWSW[25]),
.CK(n3418), .RN(n3282), .Q(FPADDSUB_DMP_EXP_EWSW[25]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_26_ ( .D(FPADDSUB_DMP_INIT_EWSW[26]),
.CK(n3418), .RN(n3282), .Q(FPADDSUB_DMP_EXP_EWSW[26]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_45_ ( .D(
FPMULT_Sgf_operation_Result[45]), .CK(n3396), .RN(n3333), .Q(
FPMULT_P_Sgf[45]) );
DFFRX1TS FPMULT_Sgf_operation_finalreg_Q_reg_44_ ( .D(
FPMULT_Sgf_operation_Result[44]), .CK(n3396), .RN(n3333), .Q(
FPMULT_P_Sgf[44]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_24_ ( .D(
FPSENCOS_first_mux_X[24]), .CK(n3448), .RN(n3356), .Q(
FPSENCOS_d_ff2_X[24]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_25_ ( .D(
FPSENCOS_first_mux_Y[25]), .CK(n3452), .RN(n3354), .Q(
FPSENCOS_d_ff2_Y[25]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_26_ ( .D(
FPSENCOS_first_mux_Y[26]), .CK(n3451), .RN(n3353), .Q(
FPSENCOS_d_ff2_Y[26]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_25_ ( .D(
FPSENCOS_first_mux_X[25]), .CK(n3448), .RN(n3356), .Q(
FPSENCOS_d_ff2_X[25]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_26_ ( .D(
FPSENCOS_first_mux_X[26]), .CK(n3448), .RN(n3355), .Q(
FPSENCOS_d_ff2_X[26]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_24_ ( .D(
FPSENCOS_first_mux_Y[24]), .CK(n3452), .RN(n3354), .Q(
FPSENCOS_d_ff2_Y[24]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n3508), .CK(
n3392), .RN(n3369), .Q(FPMULT_Sgf_normalized_result[4]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[0]), .CK(n3470), .RN(n3311), .Q(
FPADDSUB_N59) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n3506), .CK(
n3392), .RN(n3374), .Q(FPMULT_Sgf_normalized_result[2]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n3526), .CK(
n3393), .RN(n3373), .Q(FPMULT_Sgf_normalized_result[22]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n3524), .CK(
n3393), .RN(n3373), .Q(FPMULT_Sgf_normalized_result[20]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n3522), .CK(
n3394), .RN(n1018), .Q(FPMULT_Sgf_normalized_result[18]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n3520), .CK(
n3393), .RN(n1018), .Q(FPMULT_Sgf_normalized_result[16]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n3518), .CK(
n3393), .RN(n3375), .Q(FPMULT_Sgf_normalized_result[14]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n3516), .CK(
n3393), .RN(n3371), .Q(FPMULT_Sgf_normalized_result[12]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n3514), .CK(
n3393), .RN(n3375), .Q(FPMULT_Sgf_normalized_result[10]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n3512), .CK(
n3392), .RN(n3374), .Q(FPMULT_Sgf_normalized_result[8]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n3510), .CK(
n3392), .RN(n1018), .Q(FPMULT_Sgf_normalized_result[6]) );
DFFRX1TS FPADDSUB_inst_ShiftRegister_Q_reg_0_ ( .D(n1111), .CK(n913), .RN(
n3279), .Q(FPADDSUB_Shift_reg_FLAGS_7[0]) );
DFFRX1TS operation_dff_Q_reg_1_ ( .D(operation[2]), .CK(n3481), .RN(n3347),
.Q(operation_reg[1]) );
DFFRX1TS FPMULT_Exp_module_Underflow_m_Q_reg_0_ ( .D(n3499), .CK(n916), .RN(
n3368), .Q(underflow_flag_mult) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n953), .CK(n3400), .RN(
n3296), .Q(FPADDSUB_bit_shift_SHT2) );
DFFRX1TS operation_dff_Q_reg_0_ ( .D(n1016), .CK(n3482), .RN(n3319), .Q(
operation_reg[0]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(add_subt_data2[28]),
.CK(n3425), .RN(n3282), .Q(FPADDSUB_intDY_EWSW[28]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(add_subt_data2[29]),
.CK(n3422), .RN(n3282), .Q(FPADDSUB_intDY_EWSW[29]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_29_ ( .D(
FPSENCOS_first_mux_X[29]), .CK(n3448), .RN(n3355), .Q(
FPSENCOS_d_ff2_X[29]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_29_ ( .D(
FPSENCOS_first_mux_Y[29]), .CK(n3449), .RN(n3352), .Q(
FPSENCOS_d_ff2_Y[29]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_11_ ( .D(FPADDSUB_Data_array_SWR[11]), .CK(n3399), .RN(n3294), .Q(FPADDSUB_Data_array_SWR[37]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_8_ ( .D(FPADDSUB_Data_array_SWR[8]),
.CK(n3400), .RN(n3306), .Q(FPADDSUB_Data_array_SWR[34]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_9_ ( .D(FPADDSUB_Data_array_SWR[9]),
.CK(n3399), .RN(n3292), .Q(FPADDSUB_Data_array_SWR[35]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_10_ ( .D(FPADDSUB_Data_array_SWR[10]), .CK(n3400), .RN(n3293), .Q(FPADDSUB_Data_array_SWR[36]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_16_ ( .D(Data_1[16]),
.CK(n3387), .RN(n3368), .Q(FPMULT_Op_MX[16]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_4_ ( .D(Data_1[4]), .CK(
n3386), .RN(n3371), .Q(FPMULT_Op_MX[4]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_6_ ( .D(Data_1[6]), .CK(
n3386), .RN(n3371), .Q(FPMULT_Op_MX[6]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_10_ ( .D(Data_1[10]),
.CK(n3387), .RN(n3376), .Q(FPMULT_Op_MX[10]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]), .CK(n3481), .RN(n3344),
.Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(
FPADDSUB_Raw_mant_SGF[15]), .CK(n3463), .RN(n3297), .Q(
FPADDSUB_Raw_mant_NRM_SWR[15]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_15_ ( .D(Data_1[15]),
.CK(n3387), .RN(n3368), .Q(FPMULT_Op_MX[15]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]), .CK(n3481), .RN(n3344),
.Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(FPADDSUB_Raw_mant_SGF[8]),
.CK(n3464), .RN(n3297), .Q(FPADDSUB_Raw_mant_NRM_SWR[8]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(FPADDSUB_Raw_mant_SGF[7]),
.CK(n3463), .RN(n3296), .Q(FPADDSUB_Raw_mant_NRM_SWR[7]) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_27_ ( .D(
FPSENCOS_first_mux_Y[27]), .CK(n3453), .RN(n3353), .Q(
FPSENCOS_d_ff2_Y[27]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_27_ ( .D(
FPSENCOS_first_mux_X[27]), .CK(n3448), .RN(n3355), .Q(
FPSENCOS_d_ff2_X[27]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(FPADDSUB_Raw_mant_SGF[2]),
.CK(n3463), .RN(n3296), .Q(FPADDSUB_Raw_mant_NRM_SWR[2]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(FPADDSUB_Raw_mant_SGF[9]),
.CK(n3464), .RN(n3297), .Q(FPADDSUB_Raw_mant_NRM_SWR[9]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_19_ ( .D(Data_1[19]),
.CK(n3388), .RN(n3366), .Q(FPMULT_Op_MX[19]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(FPADDSUB_Raw_mant_SGF[3]),
.CK(n3463), .RN(n3296), .Q(FPADDSUB_Raw_mant_NRM_SWR[3]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_18_ ( .D(Data_1[18]),
.CK(n3388), .RN(n3378), .Q(FPMULT_Op_MX[18]) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n844), .CK(
n3484), .RN(n3279), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(
FPADDSUB_Raw_mant_SGF[19]), .CK(n3464), .RN(n3298), .Q(
FPADDSUB_Raw_mant_NRM_SWR[19]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(
FPADDSUB_Raw_mant_SGF[10]), .CK(n3463), .RN(n3297), .Q(
FPADDSUB_Raw_mant_NRM_SWR[10]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(FPADDSUB_N59), .CK(n3465),
.RN(n3296), .Q(FPADDSUB_Raw_mant_NRM_SWR[0]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_14_ ( .D(FPADDSUB_Data_array_SWR[14]), .CK(n3401), .RN(n3295), .Q(FPADDSUB_Data_array_SWR[40]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_19_ ( .D(FPADDSUB_Data_array_SWR[19]), .CK(n3399), .RN(n3289), .Q(FPADDSUB_Data_array_SWR[45]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_16_ ( .D(FPADDSUB_Data_array_SWR[16]), .CK(n3400), .RN(n3290), .Q(FPADDSUB_Data_array_SWR[42]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_15_ ( .D(FPADDSUB_Data_array_SWR[15]), .CK(n3399), .RN(n3291), .Q(FPADDSUB_Data_array_SWR[41]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_18_ ( .D(FPADDSUB_Data_array_SWR[18]), .CK(n3401), .RN(n3287), .Q(FPADDSUB_Data_array_SWR[44]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_17_ ( .D(FPADDSUB_Data_array_SWR[17]), .CK(n3399), .RN(n3302), .Q(FPADDSUB_Data_array_SWR[43]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_13_ ( .D(FPADDSUB_Data_array_SWR[13]), .CK(n3399), .RN(n3292), .Q(FPADDSUB_Data_array_SWR[39]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_12_ ( .D(FPADDSUB_Data_array_SWR[12]), .CK(n3400), .RN(n3294), .Q(FPADDSUB_Data_array_SWR[38]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_20_ ( .D(Data_1[20]),
.CK(n3388), .RN(n3378), .Q(FPMULT_Op_MX[20]), .QN(n3068) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_18_ ( .D(Data_2[18]),
.CK(n3384), .RN(n3369), .Q(FPMULT_Op_MY[18]), .QN(n3220) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[18]), .CK(n3467), .RN(n3313), .Q(
FPADDSUB_DmP_mant_SFG_SWR[18]) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(
FPADDSUB_shft_value_mux_o_EWR[3]), .CK(n3401), .RN(n3298), .Q(
FPADDSUB_shift_value_SHT2_EWR[3]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[2]), .CK(n3467), .RN(n3312), .Q(
FPADDSUB_DmP_mant_SFG_SWR[2]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[10]), .CK(n3469), .RN(n3312), .Q(
FPADDSUB_DmP_mant_SFG_SWR[10]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[16]), .CK(n3470), .RN(n3313), .Q(
FPADDSUB_DmP_mant_SFG_SWR[16]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(
FPADDSUB_Raw_mant_SGF[21]), .CK(n3465), .RN(n3298), .Q(
FPADDSUB_Raw_mant_NRM_SWR[21]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[8]), .CK(n3470), .RN(n3312), .Q(
FPADDSUB_DmP_mant_SFG_SWR[8]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(
FPADDSUB_Raw_mant_SGF[17]), .CK(n3465), .RN(n3297), .Q(
FPADDSUB_Raw_mant_NRM_SWR[17]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[3]), .CK(n1044), .RN(n3312), .Q(
FPADDSUB_DmP_mant_SFG_SWR[3]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[5]), .CK(n3470), .RN(n3312), .Q(
FPADDSUB_DmP_mant_SFG_SWR[5]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_20_ ( .D(FPADDSUB_DMP_SHT2_EWSW[20]),
.CK(n3466), .RN(n3309), .Q(FPADDSUB_DMP_SFG[20]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_18_ ( .D(FPADDSUB_DMP_SHT2_EWSW[18]),
.CK(n3466), .RN(n3309), .Q(FPADDSUB_DMP_SFG[18]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[12]), .CK(n3467), .RN(n3313), .Q(
FPADDSUB_DmP_mant_SFG_SWR[12]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(
FPADDSUB_Raw_mant_SGF[18]), .CK(n3464), .RN(n3298), .Q(
FPADDSUB_Raw_mant_NRM_SWR[18]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_4_ ( .D(FPADDSUB_DMP_SHT2_EWSW[4]),
.CK(n1044), .RN(n3308), .Q(FPADDSUB_DMP_SFG[4]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_2_ ( .D(FPADDSUB_DMP_SHT2_EWSW[2]),
.CK(n3469), .RN(n3310), .Q(FPADDSUB_DMP_SFG[2]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[9]), .CK(n3467), .RN(n3312), .Q(
FPADDSUB_DmP_mant_SFG_SWR[9]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[15]), .CK(n1044), .RN(n3313), .Q(
FPADDSUB_DmP_mant_SFG_SWR[15]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[19]), .CK(n3466), .RN(n3313), .Q(
FPADDSUB_DmP_mant_SFG_SWR[19]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(
FPADDSUB_Raw_mant_SGF[24]), .CK(n3465), .RN(n3298), .Q(
FPADDSUB_Raw_mant_NRM_SWR[24]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_20_ ( .D(Data_2[20]),
.CK(n3384), .RN(n3365), .Q(FPMULT_Op_MY[20]), .QN(n919) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_19_ ( .D(Data_2[19]),
.CK(n3384), .RN(n3365), .Q(FPMULT_Op_MY[19]), .QN(n921) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(
FPADDSUB_Raw_mant_SGF[23]), .CK(n3464), .RN(n3298), .Q(
FPADDSUB_Raw_mant_NRM_SWR[23]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_21_ ( .D(Data_2[21]),
.CK(n3383), .RN(n1019), .Q(FPMULT_Op_MY[21]), .QN(n918) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_3_ ( .D(
FPMULT_FS_Module_state_next[3]), .CK(n911), .RN(n3333), .Q(
FPMULT_FS_Module_state_reg[3]) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_1_ ( .D(n842), .CK(n3481), .RN(n3344),
.Q(FPSENCOS_cont_var_out[1]) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_14_ ( .D(Data_2[14]),
.CK(n3384), .RN(n3364), .Q(FPMULT_Op_MY[14]), .QN(n3115) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_13_ ( .D(Data_2[13]),
.CK(n3384), .RN(n3375), .Q(FPMULT_Op_MY[13]), .QN(n3230) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_1_ ( .D(Data_2[1]), .CK(
n3385), .RN(n3366), .Q(FPMULT_Op_MY[1]), .QN(n3060) );
DFFRX2TS FPMULT_Sel_A_Q_reg_0_ ( .D(1'b1), .CK(n916), .RN(n3370), .Q(
FPMULT_FSM_selector_A) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_17_ ( .D(Data_1[17]),
.CK(n3388), .RN(n3372), .Q(FPMULT_Op_MX[17]), .QN(n3069) );
CMPR32X2TS DP_OP_26J196_122_5882_U8 ( .A(DP_OP_26J196_122_5882_n17), .B(
FPADDSUB_DMP_exp_NRM2_EW[1]), .C(DP_OP_26J196_122_5882_n8), .CO(
DP_OP_26J196_122_5882_n7), .S(FPADDSUB_exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_26J196_122_5882_U7 ( .A(DP_OP_26J196_122_5882_n16), .B(
FPADDSUB_DMP_exp_NRM2_EW[2]), .C(DP_OP_26J196_122_5882_n7), .CO(
DP_OP_26J196_122_5882_n6), .S(FPADDSUB_exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_26J196_122_5882_U6 ( .A(DP_OP_26J196_122_5882_n15), .B(
FPADDSUB_DMP_exp_NRM2_EW[3]), .C(DP_OP_26J196_122_5882_n6), .CO(
DP_OP_26J196_122_5882_n5), .S(FPADDSUB_exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS DP_OP_26J196_122_5882_U5 ( .A(DP_OP_26J196_122_5882_n14), .B(
FPADDSUB_DMP_exp_NRM2_EW[4]), .C(DP_OP_26J196_122_5882_n5), .CO(
DP_OP_26J196_122_5882_n4), .S(FPADDSUB_exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_230J196_125_7006_U9 ( .A(DP_OP_230J196_125_7006_n21), .B(
FPMULT_S_Oper_A_exp[1]), .C(DP_OP_230J196_125_7006_n9), .CO(
DP_OP_230J196_125_7006_n8), .S(FPMULT_Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_230J196_125_7006_U8 ( .A(DP_OP_230J196_125_7006_n20), .B(
FPMULT_S_Oper_A_exp[2]), .C(DP_OP_230J196_125_7006_n8), .CO(
DP_OP_230J196_125_7006_n7), .S(FPMULT_Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_230J196_125_7006_U7 ( .A(DP_OP_230J196_125_7006_n19), .B(
FPMULT_S_Oper_A_exp[3]), .C(DP_OP_230J196_125_7006_n7), .CO(
DP_OP_230J196_125_7006_n6), .S(FPMULT_Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_230J196_125_7006_U6 ( .A(DP_OP_230J196_125_7006_n18), .B(
FPMULT_S_Oper_A_exp[4]), .C(DP_OP_230J196_125_7006_n6), .CO(
DP_OP_230J196_125_7006_n5), .S(FPMULT_Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_230J196_125_7006_U5 ( .A(DP_OP_230J196_125_7006_n17), .B(
FPMULT_S_Oper_A_exp[5]), .C(DP_OP_230J196_125_7006_n5), .CO(
DP_OP_230J196_125_7006_n4), .S(FPMULT_Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_230J196_125_7006_U4 ( .A(DP_OP_230J196_125_7006_n16), .B(
FPMULT_S_Oper_A_exp[6]), .C(DP_OP_230J196_125_7006_n4), .CO(
DP_OP_230J196_125_7006_n3), .S(FPMULT_Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_230J196_125_7006_U3 ( .A(DP_OP_230J196_125_7006_n15), .B(
FPMULT_S_Oper_A_exp[7]), .C(DP_OP_230J196_125_7006_n3), .CO(
DP_OP_230J196_125_7006_n2), .S(FPMULT_Exp_module_Data_S[7]) );
DFFRX4TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n1108), .CK(n3398),
.RN(n3296), .Q(FPADDSUB_left_right_SHT2), .QN(n3078) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_3_ ( .D(Data_1[3]), .CK(
n3386), .RN(n3366), .Q(FPMULT_Op_MX[3]) );
DFFRX1TS R_17 ( .D(n3276), .CK(n3386), .RN(n3373), .Q(n3491) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_2_ ( .D(Data_1[2]), .CK(
n3386), .RN(n3372), .Q(FPMULT_Op_MX[2]), .QN(n3210) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_0_ ( .D(Data_2[0]), .CK(
n3386), .RN(n3373), .Q(FPMULT_Op_MY[0]), .QN(n3217) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_11_ ( .D(Data_1[11]),
.CK(n3387), .RN(n3376), .Q(FPMULT_Op_MX[11]), .QN(n3118) );
DFFRX1TS FPMULT_Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(
FPMULT_Adder_M_result_A_adder[24]), .CK(n3389), .RN(n3377), .Q(
FPMULT_FSM_add_overflow_flag) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_8_ ( .D(Data_2[8]), .CK(
n3385), .RN(n3377), .Q(FPMULT_Op_MY[8]), .QN(n3225) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_6_ ( .D(Data_2[6]), .CK(
n3385), .RN(n3373), .Q(FPMULT_Op_MY[6]), .QN(n3227) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_7_ ( .D(Data_2[7]), .CK(
n3385), .RN(n3366), .Q(FPMULT_Op_MY[7]), .QN(n3226) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_3_ ( .D(Data_2[3]), .CK(
n3385), .RN(n3370), .Q(FPMULT_Op_MY[3]), .QN(n3219) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_9_ ( .D(Data_2[9]), .CK(
n3385), .RN(n3368), .Q(FPMULT_Op_MY[9]), .QN(n3218) );
DFFRX4TS FPSENCOS_ITER_CONT_temp_reg_2_ ( .D(FPSENCOS_ITER_CONT_N4), .CK(
n914), .RN(n3344), .Q(FPSENCOS_cont_iter_out[2]), .QN(n3062) );
DFFRX4TS FPSENCOS_ITER_CONT_temp_reg_3_ ( .D(FPSENCOS_ITER_CONT_N5), .CK(
n914), .RN(n3344), .Q(FPSENCOS_cont_iter_out[3]), .QN(n3080) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[24]), .CK(n1044), .RN(n3314), .Q(
FPADDSUB_DmP_mant_SFG_SWR[24]), .QN(n3114) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[23]), .CK(n3470), .RN(n3314), .Q(
FPADDSUB_DmP_mant_SFG_SWR[23]), .QN(n3205) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_1_ ( .D(region_flag[1]), .CK(n3461),
.RN(n3343), .Q(FPSENCOS_d_ff1_shift_region_flag_out[1]), .QN(n3235) );
DFFRX1TS reg_dataB_Q_reg_26_ ( .D(Data_2[26]), .CK(clk), .RN(n3345), .Q(
dataB[26]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(
FPADDSUB_sftr_odat_SHT2_SWR[1]), .CK(n1044), .RN(n3311), .Q(
FPADDSUB_N60) );
DFFRX1TS reg_dataA_Q_reg_25_ ( .D(Data_1[25]), .CK(n3482), .RN(n1137), .Q(
dataA[25]) );
DFFRX1TS reg_dataB_Q_reg_28_ ( .D(Data_2[28]), .CK(n3484), .RN(n3345), .Q(
dataB[28]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]), .CK(n3485), .RN(n3343),
.Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_2_ ( .D(Data_2[2]), .CK(
n3385), .RN(n3367), .Q(FPMULT_Op_MY[2]), .QN(n3231) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_12_ ( .D(Data_2[12]),
.CK(n3384), .RN(n3371), .Q(FPMULT_Op_MY[12]), .QN(n3229) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_16_ ( .D(Data_2[16]),
.CK(n3384), .RN(n3374), .Q(FPMULT_Op_MY[16]), .QN(n3221) );
DFFRX4TS FPSENCOS_ITER_CONT_temp_reg_1_ ( .D(FPSENCOS_ITER_CONT_N3), .CK(
n914), .RN(n3344), .Q(FPSENCOS_cont_iter_out[1]), .QN(n3056) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_15_ ( .D(Data_2[15]),
.CK(n3384), .RN(n1018), .Q(FPMULT_Op_MY[15]), .QN(n3222) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_11_ ( .D(Data_2[11]),
.CK(n3384), .RN(n3367), .Q(FPMULT_Op_MY[11]), .QN(n3223) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]), .CK(n3484), .RN(n3343),
.Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_9_ ( .D(Data_1[9]), .CK(
n3387), .RN(n1018), .Q(FPMULT_Op_MX[9]) );
DFFRX4TS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n810), .CK(n3400), .RN(
n3315), .Q(FPADDSUB_ADD_OVRFLW_NRM2), .QN(n3116) );
DFFRX4TS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_1_ ( .D(FPADDSUB_OP_FLAG_SHT2), .CK(
n3470), .RN(n3318), .Q(FPADDSUB_OP_FLAG_SFG), .QN(n3232) );
DFFRX1TS R_21 ( .D(n3272), .CK(clk), .RN(n3347), .Q(n3487) );
DFFRX1TS reg_dataB_Q_reg_23_ ( .D(Data_2[23]), .CK(clk), .RN(n3360), .Q(
dataB[23]) );
DFFRX1TS reg_dataA_Q_reg_23_ ( .D(Data_1[23]), .CK(n1291), .RN(n3360), .Q(
dataA[23]) );
DFFRX1TS reg_dataA_Q_reg_24_ ( .D(Data_1[24]), .CK(n1291), .RN(n3360), .Q(
dataA[24]) );
DFFRX1TS reg_dataA_Q_reg_26_ ( .D(Data_1[26]), .CK(n3484), .RN(n3360), .Q(
dataA[26]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_22_ ( .D(FPADDSUB_DMP_SHT2_EWSW[22]),
.CK(n3469), .RN(n3311), .Q(FPADDSUB_DMP_SFG[22]), .QN(n3199) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_28_ ( .D(Data_1[28]),
.CK(FPMULT_Operands_load_reg_XMRegister_net5038794), .RN(n3377), .Q(
FPMULT_Op_MX[28]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_30_ ( .D(Data_1[30]),
.CK(FPMULT_Operands_load_reg_XMRegister_net5038794), .RN(n3368), .Q(
FPMULT_Op_MX[30]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_29_ ( .D(Data_1[29]),
.CK(FPMULT_Operands_load_reg_XMRegister_net5038794), .RN(n3377), .Q(
FPMULT_Op_MX[29]) );
DFFRXLTS R_19 ( .D(n3274), .CK(n3395), .RN(n3331), .Q(n3492) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_5_ ( .D(Data_2[5]), .CK(
n3385), .RN(n3377), .Q(FPMULT_Op_MY[5]), .QN(n3228) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_23_ ( .D(Data_1[23]),
.CK(n3388), .RN(n3378), .Q(FPMULT_Op_MX[23]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_24_ ( .D(Data_1[24]),
.CK(n3388), .RN(n3372), .Q(FPMULT_Op_MX[24]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]), .CK(n3483), .RN(n3344),
.Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]), .CK(n3483), .RN(n3344),
.Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]) );
DFFRX1TS reg_dataB_Q_reg_24_ ( .D(Data_2[24]), .CK(clk), .RN(n1136), .Q(
dataB[24]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_27_ ( .D(Data_1[27]),
.CK(FPMULT_Operands_load_reg_XMRegister_net5038794), .RN(n3377), .Q(
FPMULT_Op_MX[27]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n3527), .CK(
n3392), .RN(n3366), .QN(n3186) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_0_ ( .D(
FPMULT_FS_Module_state_next[0]), .CK(n911), .RN(n3333), .Q(n923), .QN(
n3192) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_1_ ( .D(
FPADDSUB_Shift_reg_FLAGS_7[2]), .CK(n913), .RN(n3318), .Q(
FPADDSUB_Shift_reg_FLAGS_7[1]), .QN(n3079) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(
FPADDSUB_shft_value_mux_o_EWR[4]), .CK(n3398), .RN(n3299), .Q(
FPADDSUB_shift_value_SHT2_EWR[4]), .QN(n922) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_22_ ( .D(Data_2[22]),
.CK(n3383), .RN(n3364), .Q(FPMULT_Op_MY[22]), .QN(n3061) );
DFFSX1TS R_10 ( .D(n3277), .CK(n3482), .SN(n3360), .Q(n3490) );
DFFSX1TS R_18 ( .D(n3275), .CK(n3423), .SN(n3295), .Q(n3493) );
DFFSX1TS R_20 ( .D(n3273), .CK(n3484), .SN(n1139), .Q(n3488) );
DFFRXLTS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(add_subt_data2[30]),
.CK(n3421), .RN(n3282), .Q(FPADDSUB_intDY_EWSW[30]), .QN(n3110) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[3]), .CK(n3382), .RN(n3372),
.Q(mult_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[5]), .CK(n3380), .RN(n3373),
.Q(mult_result[5]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[8]), .CK(n3381), .RN(n3370),
.Q(mult_result[8]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
FPMULT_final_result_ieee_Module_Sgf_S_mux[9]), .CK(n3380), .RN(n3367),
.Q(mult_result[9]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
FPMULT_final_result_ieee_Module_Sign_S_mux), .CK(n3382), .RN(n3372),
.Q(mult_result[31]) );
DFFSX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]), .CK(n1291), .SN(n3359),
.Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_21_ ( .D(FPADDSUB_DMP_SHT2_EWSW[21]),
.CK(n3469), .RN(n3310), .Q(FPADDSUB_DMP_SFG[21]) );
DFFSX1TS R_9 ( .D(n3278), .CK(n3482), .SN(n3346), .Q(n3489) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_6_ ( .D(n3503), .CK(n913), .RN(
n3279), .Q(FPADDSUB_Shift_reg_FLAGS_7_6) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_0_ ( .D(Data_1[0]), .CK(
n3386), .RN(n3377), .Q(FPMULT_Op_MX[0]), .QN(n3168) );
DFFRX1TS FPMULT_Sel_C_Q_reg_0_ ( .D(n834), .CK(n911), .RN(n3378), .Q(
FPMULT_FSM_selector_C), .QN(n3122) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n3497), .CK(n3462), .RN(
n1301), .Q(FPADDSUB_ADD_OVRFLW_NRM) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_4_ ( .D(Data_2[4]), .CK(
n3385), .RN(n3378), .Q(FPMULT_Op_MY[4]), .QN(n920) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_10_ ( .D(Data_2[10]),
.CK(n3385), .RN(n3372), .Q(FPMULT_Op_MY[10]), .QN(n3224) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_17_ ( .D(Data_2[17]),
.CK(n3384), .RN(n1018), .Q(FPMULT_Op_MY[17]), .QN(n910) );
CMPR32X2TS DP_OP_26J196_122_5882_U9 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
n3116), .C(DP_OP_26J196_122_5882_n18), .CO(DP_OP_26J196_122_5882_n8),
.S(FPADDSUB_exp_rslt_NRM2_EW1[0]) );
CMPR32X2TS DP_OP_230J196_125_7006_U10 ( .A(FPMULT_S_Oper_A_exp[0]), .B(
FPMULT_FSM_exp_operation_A_S), .C(DP_OP_230J196_125_7006_n22), .CO(
DP_OP_230J196_125_7006_n9), .S(FPMULT_Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_26J196_122_5882_U4 ( .A(n3116), .B(
FPADDSUB_DMP_exp_NRM2_EW[5]), .C(DP_OP_26J196_122_5882_n4), .CO(
DP_OP_26J196_122_5882_n3), .S(FPADDSUB_exp_rslt_NRM2_EW1[5]) );
CMPR32X2TS DP_OP_26J196_122_5882_U3 ( .A(n3116), .B(
FPADDSUB_DMP_exp_NRM2_EW[6]), .C(DP_OP_26J196_122_5882_n3), .CO(
DP_OP_26J196_122_5882_n2), .S(FPADDSUB_exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS DP_OP_26J196_122_5882_U2 ( .A(n3116), .B(
FPADDSUB_DMP_exp_NRM2_EW[7]), .C(DP_OP_26J196_122_5882_n2), .CO(
DP_OP_26J196_122_5882_n1), .S(FPADDSUB_exp_rslt_NRM2_EW1[7]) );
CMPR32X2TS DP_OP_230J196_125_7006_U2 ( .A(FPMULT_FSM_exp_operation_A_S), .B(
FPMULT_S_Oper_A_exp[8]), .C(DP_OP_230J196_125_7006_n2), .CO(
DP_OP_230J196_125_7006_n1), .S(FPMULT_Exp_module_Data_S[8]) );
AOI222X4TS U1399 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[8]), .A1(
FPADDSUB_DMP_SFG[6]), .B0(FPADDSUB_DmP_mant_SFG_SWR[8]), .B1(n2930),
.C0(FPADDSUB_DMP_SFG[6]), .C1(n2930), .Y(n2934) );
AOI222X4TS U1400 ( .A0(FPADDSUB_DMP_SFG[2]), .A1(n3153), .B0(
FPADDSUB_DMP_SFG[2]), .B1(n1691), .C0(n3153), .C1(n1691), .Y(n2918) );
CMPR32X2TS U1401 ( .A(FPMULT_Op_MY[0]), .B(n2786), .C(n2743), .CO(n2741),
.S(mult_x_69_n348) );
CMPR32X2TS U1402 ( .A(FPMULT_Op_MY[2]), .B(FPMULT_Op_MY[3]), .C(n1354), .CO(
n1347), .S(n2127) );
BUFX6TS U1403 ( .A(n3468), .Y(n1044) );
BUFX6TS U1404 ( .A(n917), .Y(n3402) );
BUFX6TS U1405 ( .A(n912), .Y(n3470) );
BUFX6TS U1406 ( .A(n912), .Y(n3469) );
BUFX6TS U1407 ( .A(n912), .Y(n3466) );
AO22X2TS U1408 ( .A0(FPADDSUB_intDX_EWSW[30]), .A1(n3110), .B0(n2880), .B1(
n2878), .Y(n3016) );
CLKBUFX2TS U1409 ( .A(n2411), .Y(n1023) );
NAND3X2TS U1410 ( .A(n1445), .B(n1029), .C(n1063), .Y(n1720) );
NAND2BX4TS U1411 ( .AN(n1385), .B(n1408), .Y(n2478) );
OAI21X2TS U1412 ( .A0(n3213), .A1(n1798), .B0(n1447), .Y(n934) );
CLKAND2X2TS U1413 ( .A(n1383), .B(n1038), .Y(n2480) );
NAND2BX4TS U1414 ( .AN(n1336), .B(n1335), .Y(n2318) );
OAI21X2TS U1415 ( .A0(n3212), .A1(n2801), .B0(n1397), .Y(n932) );
CLKAND2X2TS U1416 ( .A(n1037), .B(n1039), .Y(n2257) );
CLKBUFX2TS U1417 ( .A(n1382), .Y(n1038) );
NOR2X2TS U1418 ( .A(n1029), .B(n1445), .Y(n1448) );
NAND2BX4TS U1419 ( .AN(n1429), .B(n1428), .Y(n2468) );
AND2X2TS U1420 ( .A(n1429), .B(n1787), .Y(n2470) );
CLKBUFX2TS U1421 ( .A(n1446), .Y(n1029) );
CLKBUFX2TS U1422 ( .A(n1341), .Y(n1039) );
NOR2X2TS U1423 ( .A(n3168), .B(n1727), .Y(n1771) );
CLKBUFX2TS U1424 ( .A(n1322), .Y(n1030) );
CLKAND2X2TS U1425 ( .A(FPMULT_Op_MX[0]), .B(n1727), .Y(n1816) );
AND2X2TS U1426 ( .A(n1385), .B(n1384), .Y(n2479) );
AND2X2TS U1427 ( .A(n1336), .B(n1036), .Y(n2256) );
CLKBUFX2TS U1428 ( .A(FPSENCOS_cont_iter_out[3]), .Y(n943) );
CLKBUFX3TS U1429 ( .A(n3230), .Y(n1033) );
AND3X1TS U1430 ( .A(n3068), .B(n3104), .C(n3151), .Y(n2810) );
CLKBUFX3TS U1431 ( .A(n3078), .Y(n967) );
NOR2X4TS U1432 ( .A(n3037), .B(n3044), .Y(n1146) );
NAND2X4TS U1433 ( .A(n2837), .B(n2783), .Y(n2292) );
OR2X2TS U1434 ( .A(n2783), .B(operation[1]), .Y(n2780) );
AOI222X4TS U1435 ( .A0(n2732), .A1(n2731), .B0(n2732), .B1(n2730), .C0(n2731), .C1(n1070), .Y(n2790) );
AOI2BB2XLTS U1436 ( .B0(FPMULT_Op_MX[6]), .B1(n2472), .A0N(n1464), .A1N(
FPMULT_Op_MX[6]), .Y(n1446) );
AOI2BB2XLTS U1437 ( .B0(FPMULT_Op_MX[10]), .B1(n2482), .A0N(n1619), .A1N(
FPMULT_Op_MX[10]), .Y(n1382) );
AOI2BB2XLTS U1438 ( .B0(FPMULT_Op_MX[16]), .B1(n2261), .A0N(n1045), .A1N(
FPMULT_Op_MX[16]), .Y(n1341) );
AOI2BB2XLTS U1439 ( .B0(FPMULT_Op_MX[15]), .B1(FPMULT_Op_MX[14]), .A0N(
FPMULT_Op_MX[14]), .A1N(FPMULT_Op_MX[15]), .Y(n1342) );
AOI31X1TS U1440 ( .A0(mult_x_69_n471), .A1(FPMULT_Op_MX[11]), .A2(n2126),
.B0(n2125), .Y(mult_x_69_n466) );
OAI31X1TS U1441 ( .A0(n1447), .A1(n1798), .A2(n2725), .B0(n934), .Y(n1802)
);
CLKAND2X2TS U1442 ( .A(n1434), .B(n1430), .Y(n929) );
AO21XLTS U1443 ( .A0(FPMULT_Op_MY[21]), .A1(n1499), .B0(FPMULT_Op_MY[22]),
.Y(n938) );
CLKAND2X2TS U1444 ( .A(n1877), .B(n951), .Y(n936) );
OAI222X1TS U1445 ( .A0(n1034), .A1(n984), .B0(n2756), .B1(n1054), .C0(n1093),
.C1(n2772), .Y(n1765) );
OAI222X1TS U1446 ( .A0(n1734), .A1(n983), .B0(n1024), .B1(n1055), .C0(n1092),
.C1(n918), .Y(n1735) );
OAI222X1TS U1447 ( .A0(n2761), .A1(n983), .B0(n920), .B1(n1054), .C0(n1091),
.C1(n2756), .Y(n1791) );
OAI222X1TS U1448 ( .A0(n2251), .A1(n984), .B0(n2722), .B1(n1055), .C0(n1092),
.C1(n2181), .Y(n1805) );
AOI211X1TS U1449 ( .A0(n1707), .A1(n1821), .B0(n2135), .C0(n1371), .Y(
mult_x_69_n593) );
OAI32X1TS U1450 ( .A0(n3168), .A1(n3107), .A2(n944), .B0(n2322), .B1(n2321),
.Y(mult_x_69_n779) );
INVX2TS U1451 ( .A(n2780), .Y(n2309) );
AO21XLTS U1452 ( .A0(n949), .A1(FPADDSUB_Data_array_SWR[49]), .B0(n1835),
.Y(n933) );
AOI222X4TS U1453 ( .A0(n3079), .A1(FPADDSUB_DmP_mant_SHT1_SW[9]), .B0(n1108),
.B1(FPADDSUB_Raw_mant_NRM_SWR[14]), .C0(FPADDSUB_Raw_mant_NRM_SWR[11]),
.C1(n953), .Y(n1859) );
OAI211XLTS U1454 ( .A0(n2468), .A1(n918), .B0(n1725), .C0(n995), .Y(n1726)
);
OAI211XLTS U1455 ( .A0(n2478), .A1(n918), .B0(n1823), .C0(n1004), .Y(n1824)
);
OAI211XLTS U1456 ( .A0(n2318), .A1(n918), .B0(n1714), .C0(n1001), .Y(n1715)
);
CLKINVX3TS U1457 ( .A(n2784), .Y(FPMULT_FSM_exp_operation_A_S) );
OAI211X1TS U1458 ( .A0(n1025), .A1(n950), .B0(n1651), .C0(n1650), .Y(n2016)
);
AO22XLTS U1459 ( .A0(FPADDSUB_Data_array_SWR[44]), .A1(n960), .B0(
FPADDSUB_Data_array_SWR[40]), .B1(n1102), .Y(n2575) );
AO21XLTS U1460 ( .A0(n949), .A1(FPADDSUB_Data_array_SWR[45]), .B0(n1645),
.Y(n930) );
AOI222X4TS U1461 ( .A0(FPADDSUB_DMP_SFG[8]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[10]), .B0(FPADDSUB_DMP_SFG[8]), .B1(n2940),
.C0(FPADDSUB_DmP_mant_SFG_SWR[10]), .C1(n2940), .Y(n2944) );
OAI211X1TS U1462 ( .A0(n1986), .A1(n950), .B0(n1643), .C0(n1642), .Y(n1703)
);
AOI222X4TS U1463 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[5]), .A1(n2918), .B0(
FPADDSUB_DmP_mant_SFG_SWR[5]), .B1(n3194), .C0(n2918), .C1(n3194), .Y(
n2009) );
OAI31X1TS U1464 ( .A0(n3053), .A1(FPSENCOS_cont_var_out[1]), .A2(n3082),
.B0(n3052), .Y(n842) );
AOI32X1TS U1465 ( .A0(FPSENCOS_cont_iter_out[2]), .A1(n3080), .A2(n3056),
.B0(n3062), .B1(n3049), .Y(n1830) );
AOI32X1TS U1466 ( .A0(n3119), .A1(n3062), .A2(n3080), .B0(
FPSENCOS_cont_iter_out[3]), .B1(FPSENCOS_cont_iter_out[2]), .Y(n851)
);
AOI32X1TS U1467 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n3080), .A2(n3062),
.B0(FPSENCOS_cont_iter_out[2]), .B1(FPSENCOS_cont_iter_out[3]), .Y(
n864) );
NOR3BX2TS U1468 ( .AN(n1231), .B(n1230), .C(n1229), .Y(n3496) );
CLKINVX3TS U1469 ( .A(n826), .Y(n1455) );
XNOR2X1TS U1470 ( .A(n2751), .B(n1467), .Y(n924) );
XNOR2X1TS U1471 ( .A(n2772), .B(n1460), .Y(n925) );
INVX2TS U1472 ( .A(n1361), .Y(n2708) );
NAND2BX2TS U1473 ( .AN(n2730), .B(n2732), .Y(n2771) );
INVX2TS U1474 ( .A(n1717), .Y(n2672) );
INVX2TS U1475 ( .A(n1820), .Y(n1812) );
INVX2TS U1476 ( .A(rst), .Y(n3486) );
OA21XLTS U1477 ( .A0(n3190), .A1(n958), .B0(n1506), .Y(n926) );
OR2X1TS U1478 ( .A(FPMULT_FSM_selector_C), .B(n2602), .Y(n927) );
OR2X1TS U1479 ( .A(n3122), .B(n2602), .Y(n928) );
OA21XLTS U1480 ( .A0(n3068), .A1(n2795), .B0(n1362), .Y(n931) );
INVX2TS U1481 ( .A(n1455), .Y(n3374) );
BUFX3TS U1482 ( .A(n1455), .Y(n1299) );
OR2X1TS U1483 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n935) );
OR2X1TS U1484 ( .A(FPMULT_Op_MX[1]), .B(FPMULT_Op_MX[0]), .Y(n937) );
OR2X1TS U1485 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n1836), .Y(n939) );
OR2X1TS U1486 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n1837), .Y(n940) );
NAND2X1TS U1487 ( .A(FPADDSUB_ADD_OVRFLW_NRM), .B(
FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n2785) );
CLKBUFX3TS U1488 ( .A(n915), .Y(n941) );
INVX2TS U1489 ( .A(n3192), .Y(n942) );
INVX2TS U1490 ( .A(n938), .Y(n944) );
INVX2TS U1491 ( .A(n938), .Y(n945) );
BUFX4TS U1492 ( .A(clk), .Y(n3479) );
BUFX4TS U1493 ( .A(clk), .Y(n3485) );
BUFX4TS U1494 ( .A(clk), .Y(n1291) );
INVX2TS U1495 ( .A(n936), .Y(n946) );
INVX2TS U1496 ( .A(n936), .Y(n947) );
INVX2TS U1497 ( .A(n935), .Y(n948) );
INVX2TS U1498 ( .A(n935), .Y(n949) );
INVX2TS U1499 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .Y(n950) );
INVX2TS U1500 ( .A(n937), .Y(n951) );
INVX2TS U1501 ( .A(n937), .Y(n952) );
INVX2TS U1502 ( .A(n2785), .Y(n953) );
INVX2TS U1503 ( .A(n3061), .Y(n954) );
INVX2TS U1504 ( .A(n954), .Y(n955) );
INVX2TS U1505 ( .A(n2785), .Y(n956) );
INVX2TS U1506 ( .A(n956), .Y(n957) );
INVX2TS U1507 ( .A(n956), .Y(n958) );
INVX2TS U1508 ( .A(n940), .Y(n959) );
INVX2TS U1509 ( .A(n940), .Y(n960) );
INVX2TS U1510 ( .A(n939), .Y(n961) );
INVX2TS U1511 ( .A(n939), .Y(n962) );
INVX2TS U1512 ( .A(n1107), .Y(n963) );
INVX2TS U1513 ( .A(n1109), .Y(n964) );
INVX2TS U1514 ( .A(n3079), .Y(n965) );
INVX2TS U1515 ( .A(n965), .Y(n966) );
INVX2TS U1516 ( .A(n2057), .Y(n968) );
INVX2TS U1517 ( .A(n2057), .Y(n969) );
INVX2TS U1518 ( .A(n2045), .Y(n970) );
INVX2TS U1519 ( .A(n2045), .Y(n971) );
INVX2TS U1520 ( .A(n2810), .Y(n972) );
CLKINVX3TS U1521 ( .A(n2810), .Y(n973) );
INVX2TS U1522 ( .A(n2036), .Y(n974) );
INVX2TS U1523 ( .A(n2036), .Y(n975) );
INVX2TS U1524 ( .A(n928), .Y(n976) );
INVX2TS U1525 ( .A(n928), .Y(n977) );
INVX2TS U1526 ( .A(n928), .Y(n978) );
INVX2TS U1527 ( .A(n927), .Y(n979) );
INVX2TS U1528 ( .A(n927), .Y(n980) );
INVX2TS U1529 ( .A(n927), .Y(n981) );
INVX2TS U1530 ( .A(n1816), .Y(n982) );
INVX2TS U1531 ( .A(n1816), .Y(n983) );
INVX2TS U1532 ( .A(n1816), .Y(n984) );
INVX2TS U1533 ( .A(n2479), .Y(n985) );
INVX2TS U1534 ( .A(n2479), .Y(n986) );
INVX2TS U1535 ( .A(n2479), .Y(n987) );
INVX2TS U1536 ( .A(n2470), .Y(n988) );
INVX2TS U1537 ( .A(n2470), .Y(n989) );
INVX2TS U1538 ( .A(n2470), .Y(n990) );
INVX2TS U1539 ( .A(n2256), .Y(n991) );
INVX2TS U1540 ( .A(n2256), .Y(n992) );
INVX2TS U1541 ( .A(n2256), .Y(n993) );
INVX2TS U1542 ( .A(n929), .Y(n994) );
INVX2TS U1543 ( .A(n929), .Y(n995) );
INVX2TS U1544 ( .A(n929), .Y(n996) );
INVX2TS U1545 ( .A(n1049), .Y(n997) );
INVX2TS U1546 ( .A(n1049), .Y(n998) );
INVX2TS U1547 ( .A(n1049), .Y(n999) );
INVX2TS U1548 ( .A(n2257), .Y(n1000) );
INVX2TS U1549 ( .A(n2257), .Y(n1001) );
INVX2TS U1550 ( .A(n2257), .Y(n1002) );
INVX2TS U1551 ( .A(n2480), .Y(n1003) );
INVX2TS U1552 ( .A(n2480), .Y(n1004) );
INVX2TS U1553 ( .A(n2480), .Y(n1005) );
INVX2TS U1554 ( .A(n1822), .Y(n1006) );
INVX2TS U1555 ( .A(n1822), .Y(n1007) );
INVX2TS U1556 ( .A(n1822), .Y(n1008) );
INVX2TS U1557 ( .A(n1713), .Y(n1009) );
INVX2TS U1558 ( .A(n1713), .Y(n1010) );
INVX2TS U1559 ( .A(n1713), .Y(n1011) );
INVX2TS U1560 ( .A(n1724), .Y(n1012) );
INVX2TS U1561 ( .A(n1724), .Y(n1013) );
INVX2TS U1562 ( .A(n1724), .Y(n1014) );
INVX2TS U1563 ( .A(operation[1]), .Y(n1015) );
INVX2TS U1564 ( .A(n1015), .Y(n1016) );
INVX2TS U1565 ( .A(n1015), .Y(n1017) );
OAI222X1TS U1566 ( .A0(n1091), .A1(n2714), .B0(n2751), .B1(n1055), .C0(n982),
.C1(n2715), .Y(n1813) );
CLKBUFX3TS U1567 ( .A(n3224), .Y(n2751) );
AOI32X1TS U1568 ( .A0(n942), .A1(n2602), .A2(n3063), .B0(n2601), .B1(n2602),
.Y(n3527) );
AOI222X4TS U1569 ( .A0(FPADDSUB_DMP_SFG[20]), .A1(n3189), .B0(
FPADDSUB_DMP_SFG[20]), .B1(n2605), .C0(n3189), .C1(n2605), .Y(n2022)
);
INVX2TS U1570 ( .A(n1455), .Y(n3364) );
CLKINVX3TS U1571 ( .A(n1455), .Y(n3371) );
CLKBUFX3TS U1572 ( .A(n3227), .Y(n2252) );
INVX2TS U1573 ( .A(n1299), .Y(n1018) );
INVX2TS U1574 ( .A(n1299), .Y(n1019) );
CLKBUFX3TS U1575 ( .A(n3229), .Y(n2481) );
OAI22X4TS U1576 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(
FPADDSUB_Shift_amount_SHT1_EWR[0]), .B0(FPADDSUB_LZD_raw_out_EWR[0]),
.B1(n963), .Y(n1638) );
OAI31X4TS U1577 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[7]), .A1(n3190), .A2(n1135),
.B0(n1134), .Y(FPADDSUB_LZD_raw_out_EWR[0]) );
CLKINVX3TS U1578 ( .A(n2644), .Y(n3031) );
CLKINVX3TS U1579 ( .A(n2655), .Y(n3028) );
CLKINVX3TS U1580 ( .A(n2660), .Y(n3029) );
INVX2TS U1581 ( .A(n2708), .Y(n1020) );
INVX2TS U1582 ( .A(n1020), .Y(n1021) );
INVX2TS U1583 ( .A(n1020), .Y(n1022) );
NOR2X2TS U1584 ( .A(FPADDSUB_Raw_mant_NRM_SWR[18]), .B(n1130), .Y(n2639) );
NAND3X1TS U1585 ( .A(n1289), .B(n1288), .C(n3165), .Y(n1453) );
NOR4X2TS U1586 ( .A(FPADDSUB_Raw_mant_NRM_SWR[24]), .B(
FPADDSUB_Raw_mant_NRM_SWR[25]), .C(FPADDSUB_Raw_mant_NRM_SWR[22]), .D(
FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n1679) );
OAI21XLTS U1587 ( .A0(n2410), .A1(n2411), .B0(n1783), .Y(n2425) );
OAI31X1TS U1588 ( .A0(n1023), .A1(n2410), .A2(n2409), .B0(n2408), .Y(n2417)
);
NOR2X2TS U1589 ( .A(n1787), .B(n2731), .Y(n2410) );
CLKINVX3TS U1590 ( .A(FPMULT_Op_MX[2]), .Y(n1785) );
CLKINVX3TS U1591 ( .A(FPMULT_Op_MX[2]), .Y(n2321) );
NOR2X2TS U1592 ( .A(n3080), .B(n2067), .Y(n2068) );
OAI2BB2X2TS U1593 ( .B0(n2933), .B1(n2934), .A0N(FPADDSUB_DMP_SFG[7]), .A1N(
FPADDSUB_DmP_mant_SFG_SWR[9]), .Y(n2940) );
NOR2X2TS U1594 ( .A(n3156), .B(n2827), .Y(n2826) );
NOR2X2TS U1595 ( .A(n3157), .B(n2825), .Y(n2824) );
NOR2X2TS U1596 ( .A(n3158), .B(n2823), .Y(n2822) );
NOR2X2TS U1597 ( .A(n3159), .B(n2821), .Y(n2820) );
NOR2X2TS U1598 ( .A(n3160), .B(n2819), .Y(n2818) );
NOR2X2TS U1599 ( .A(n3161), .B(n2817), .Y(n2816) );
CLKINVX3TS U1600 ( .A(FPMULT_Op_MY[20]), .Y(n1024) );
NOR4X1TS U1601 ( .A(FPMULT_Op_MX[9]), .B(FPMULT_Op_MX[27]), .C(
FPMULT_Op_MX[24]), .D(FPMULT_Op_MX[26]), .Y(n1878) );
NOR4X1TS U1602 ( .A(FPMULT_Op_MX[8]), .B(FPMULT_Op_MX[10]), .C(
FPMULT_Op_MX[5]), .D(FPMULT_Op_MX[23]), .Y(n1879) );
NOR4X1TS U1603 ( .A(n1877), .B(n1046), .C(FPMULT_Op_MX[14]), .D(
FPMULT_Op_MX[11]), .Y(n1880) );
OAI33X1TS U1604 ( .A0(FPMULT_Op_MY[21]), .A1(n954), .A2(n972), .B0(n2809),
.B1(n2808), .B2(n3061), .Y(n2811) );
BUFX3TS U1605 ( .A(n3397), .Y(n3395) );
OAI211X1TS U1606 ( .A0(n1868), .A1(n922), .B0(n1656), .C0(n1655), .Y(n1995)
);
AOI21X2TS U1607 ( .A0(n948), .A1(FPADDSUB_Data_array_SWR[50]), .B0(n1835),
.Y(n1868) );
AOI21X2TS U1608 ( .A0(n948), .A1(FPADDSUB_Data_array_SWR[51]), .B0(n1835),
.Y(n1993) );
NOR2X2TS U1609 ( .A(FPADDSUB_DMP_SFG[22]), .B(FPADDSUB_DmP_mant_SFG_SWR[24]),
.Y(n2630) );
INVX2TS U1610 ( .A(n933), .Y(n1025) );
AOI21X2TS U1611 ( .A0(n948), .A1(FPADDSUB_Data_array_SWR[46]), .B0(n1641),
.Y(n1986) );
OAI21X1TS U1612 ( .A0(n1837), .A1(n3109), .B0(n1653), .Y(n1641) );
OAI211X1TS U1613 ( .A0(n1989), .A1(n922), .B0(n1647), .C0(n1646), .Y(n2001)
);
AOI21X2TS U1614 ( .A0(n948), .A1(FPADDSUB_Data_array_SWR[48]), .B0(n1835),
.Y(n1989) );
CLKINVX3TS U1615 ( .A(FPMULT_Op_MY[21]), .Y(n1027) );
OAI2BB2XLTS U1616 ( .B0(n2710), .B1(FPMULT_Op_MX[19]), .A0N(FPMULT_Op_MX[19]), .A1N(n2166), .Y(n1322) );
INVX2TS U1617 ( .A(n931), .Y(n1031) );
AOI21X2TS U1618 ( .A0(n948), .A1(FPADDSUB_Data_array_SWR[47]), .B0(n1640),
.Y(n1705) );
OAI21X1TS U1619 ( .A0(n1837), .A1(n3108), .B0(n1653), .Y(n1640) );
AOI21X2TS U1620 ( .A0(n948), .A1(FPADDSUB_Data_array_SWR[44]), .B0(n1649),
.Y(n2019) );
OAI21X1TS U1621 ( .A0(n1837), .A1(n3198), .B0(n1653), .Y(n1649) );
INVX2TS U1622 ( .A(n930), .Y(n1032) );
CLKINVX3TS U1623 ( .A(n1785), .Y(n1817) );
OR3X2TS U1624 ( .A(n943), .B(n1079), .C(n3050), .Y(n2660) );
AOI222X4TS U1625 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[19]), .A1(n2987), .B0(
FPADDSUB_DmP_mant_SFG_SWR[19]), .B1(n3197), .C0(n2987), .C1(n3197),
.Y(n2536) );
AOI2BB2X2TS U1626 ( .B0(n2979), .B1(n2012), .A0N(n3171), .A1N(
FPADDSUB_DmP_mant_SFG_SWR[18]), .Y(n2987) );
NOR2BX2TS U1627 ( .AN(FPADDSUB_DMP_SFG[4]), .B(n3154), .Y(n2008) );
NOR2X2TS U1628 ( .A(n1384), .B(n1767), .Y(mult_x_69_n471) );
CLKBUFX3TS U1629 ( .A(n3217), .Y(n1767) );
INVX2TS U1630 ( .A(n2282), .Y(n2287) );
AOI222X4TS U1631 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[3]), .A1(n2647), .B0(
FPADDSUB_DmP_mant_SFG_SWR[3]), .B1(n3193), .C0(n2647), .C1(n3193), .Y(
n1691) );
AOI2BB2X2TS U1632 ( .B0(n2079), .B1(n2076), .A0N(n3172), .A1N(
FPADDSUB_DmP_mant_SFG_SWR[2]), .Y(n2647) );
CLKBUFX3TS U1633 ( .A(n2651), .Y(n2663) );
CLKBUFX3TS U1634 ( .A(n2651), .Y(n2655) );
CLKBUFX3TS U1635 ( .A(n2651), .Y(n2644) );
NOR2X2TS U1636 ( .A(n1036), .B(n1767), .Y(mult_x_69_n435) );
BUFX3TS U1637 ( .A(n1138), .Y(n3360) );
INVX2TS U1638 ( .A(n925), .Y(n1034) );
CLKBUFX3TS U1639 ( .A(n1137), .Y(n3347) );
INVX2TS U1640 ( .A(n924), .Y(n1035) );
CLKBUFX3TS U1641 ( .A(n2765), .Y(n2701) );
CLKXOR2X4TS U1642 ( .A(n1331), .B(FPMULT_Op_MY[11]), .Y(n2715) );
CLKXOR2X4TS U1643 ( .A(FPMULT_Op_MY[14]), .B(n1535), .Y(n2668) );
OAI21X1TS U1644 ( .A0(FPMULT_Op_MY[13]), .A1(n1534), .B0(n1533), .Y(n1535)
);
CLKINVX3TS U1645 ( .A(n1455), .Y(n3369) );
CLKINVX3TS U1646 ( .A(n1299), .Y(n3368) );
CLKINVX3TS U1647 ( .A(n1299), .Y(n3373) );
CLKINVX3TS U1648 ( .A(n3210), .Y(n1877) );
AOI2BB2X2TS U1649 ( .B0(FPMULT_Op_MX[9]), .B1(FPMULT_Op_MX[8]), .A0N(
FPMULT_Op_MX[8]), .A1N(FPMULT_Op_MX[9]), .Y(n1383) );
INVX2TS U1650 ( .A(n1342), .Y(n1036) );
INVX2TS U1651 ( .A(n1036), .Y(n1037) );
CLKINVX3TS U1652 ( .A(n1299), .Y(n3367) );
CLKXOR2X4TS U1653 ( .A(n3220), .B(n1321), .Y(n2244) );
CLKINVX3TS U1654 ( .A(FPMULT_Op_MY[18]), .Y(n1040) );
NOR2X4TS U1655 ( .A(n1638), .B(n2600), .Y(n2057) );
NOR3BX2TS U1656 ( .AN(FPSENCOS_cont_var_out[1]), .B(n3123), .C(
FPSENCOS_cont_var_out[0]), .Y(FPSENCOS_enab_d_ff4_Zn) );
NOR3BX2TS U1657 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .C(n1453), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]) );
NOR3X2TS U1658 ( .A(FPMULT_FS_Module_state_reg[3]), .B(
FPMULT_FS_Module_state_reg[2]), .C(n3035), .Y(n107) );
NAND2X1TS U1659 ( .A(FPMULT_FS_Module_state_reg[1]), .B(n942), .Y(n3035) );
BUFX3TS U1660 ( .A(n1301), .Y(n3318) );
NOR3X2TS U1661 ( .A(FPMULT_FS_Module_state_reg[3]), .B(n942), .C(n3063), .Y(
n1459) );
CLKBUFX3TS U1662 ( .A(n917), .Y(n3404) );
AOI211X4TS U1663 ( .A0(n2127), .A1(n1816), .B0(n1778), .C0(n1777), .Y(n1782)
);
NAND2X2TS U1664 ( .A(FPMULT_FS_Module_state_reg[3]), .B(n3063), .Y(n1661) );
CLKBUFX3TS U1665 ( .A(n1145), .Y(n2512) );
NOR3X1TS U1666 ( .A(FPSENCOS_cont_var_out[1]), .B(n3082), .C(n3037), .Y(
n1145) );
CLKBUFX3TS U1667 ( .A(n3223), .Y(n2714) );
AOI211X4TS U1668 ( .A0(FPADDSUB_Data_array_SWR[43]), .A1(n949), .B0(n2571),
.C0(n1654), .Y(n1997) );
CLKBUFX3TS U1669 ( .A(n3222), .Y(n2469) );
BUFX3TS U1670 ( .A(n3486), .Y(n1137) );
CLKBUFX3TS U1671 ( .A(n3486), .Y(n1138) );
CLKBUFX3TS U1672 ( .A(n3486), .Y(n1139) );
CLKBUFX3TS U1673 ( .A(n1300), .Y(n1303) );
NOR2X4TS U1674 ( .A(n3119), .B(n3056), .Y(n3049) );
BUFX4TS U1675 ( .A(FPADDSUB_INPUT_STAGE_OPERANDY_net5038542), .Y(n3425) );
BUFX4TS U1676 ( .A(FPADDSUB_INPUT_STAGE_OPERANDY_net5038542), .Y(n3422) );
CLKINVX3TS U1677 ( .A(n2583), .Y(n1990) );
NAND3X2TS U1678 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .C(n922), .Y(n2583) );
NOR2X2TS U1679 ( .A(FPMULT_FS_Module_state_reg[3]), .B(n3063), .Y(n3033) );
INVX3TS U1680 ( .A(n1299), .Y(n3378) );
AOI21X2TS U1681 ( .A0(n956), .A1(n3183), .B0(n1662), .Y(n2056) );
AOI21X2TS U1682 ( .A0(n1107), .A1(n3181), .B0(n1847), .Y(n2063) );
INVX2TS U1683 ( .A(n1359), .Y(n1041) );
INVX2TS U1684 ( .A(n1041), .Y(n1042) );
OAI2BB2XLTS U1685 ( .B0(FPMULT_Op_MX[18]), .B1(n1046), .A0N(n1046), .A1N(
FPMULT_Op_MX[18]), .Y(n1359) );
INVX2TS U1686 ( .A(n926), .Y(n1043) );
CLKINVX3TS U1687 ( .A(n1299), .Y(n3370) );
INVX3TS U1688 ( .A(n1299), .Y(n3377) );
INVX3TS U1689 ( .A(n1299), .Y(n3372) );
BUFX3TS U1690 ( .A(clk), .Y(n3484) );
CLKINVX3TS U1691 ( .A(n1455), .Y(n3376) );
CLKINVX3TS U1692 ( .A(n1455), .Y(n3365) );
CLKINVX3TS U1693 ( .A(n1455), .Y(n3375) );
NOR2X2TS U1694 ( .A(FPMULT_FS_Module_state_reg[1]), .B(n942), .Y(n2518) );
BUFX6TS U1695 ( .A(n3411), .Y(n3409) );
BUFX6TS U1696 ( .A(n3411), .Y(n3408) );
BUFX6TS U1697 ( .A(n3418), .Y(n3415) );
BUFX6TS U1698 ( .A(n3418), .Y(n3414) );
BUFX6TS U1699 ( .A(n1293), .Y(n3453) );
BUFX6TS U1700 ( .A(n3454), .Y(n3450) );
BUFX6TS U1701 ( .A(n1293), .Y(n3451) );
BUFX6TS U1702 ( .A(n1293), .Y(n3452) );
BUFX6TS U1703 ( .A(FPSENCOS_reg_val_muxZ_2stage_net5038830), .Y(n3449) );
BUFX6TS U1704 ( .A(n3412), .Y(n3410) );
BUFX6TS U1705 ( .A(n3412), .Y(n3406) );
BUFX6TS U1706 ( .A(n3419), .Y(n3413) );
BUFX6TS U1707 ( .A(n3419), .Y(n3417) );
BUFX6TS U1708 ( .A(n1292), .Y(n3443) );
BUFX6TS U1709 ( .A(n1292), .Y(n3440) );
BUFX6TS U1710 ( .A(n1292), .Y(n3441) );
BUFX6TS U1711 ( .A(n1292), .Y(n3442) );
BUFX4TS U1712 ( .A(FPADDSUB_INPUT_STAGE_OPERANDY_net5038542), .Y(n3426) );
BUFX4TS U1713 ( .A(FPADDSUB_INPUT_STAGE_OPERANDY_net5038542), .Y(n3424) );
BUFX6TS U1714 ( .A(FPADDSUB_INPUT_STAGE_OPERANDY_net5038542), .Y(n3423) );
BUFX4TS U1715 ( .A(FPADDSUB_INPUT_STAGE_OPERANDY_net5038542), .Y(n3421) );
BUFX4TS U1716 ( .A(FPADDSUB_INPUT_STAGE_OPERANDY_net5038542), .Y(n3420) );
BUFX4TS U1717 ( .A(n912), .Y(n3467) );
BUFX4TS U1718 ( .A(n1293), .Y(n3454) );
BUFX4TS U1719 ( .A(n1293), .Y(n3457) );
BUFX4TS U1720 ( .A(n1293), .Y(n3456) );
BUFX4TS U1721 ( .A(n1292), .Y(n3444) );
BUFX4TS U1722 ( .A(n1292), .Y(n3447) );
BUFX4TS U1723 ( .A(FPSENCOS_reg_shift_y_net5038830), .Y(n3446) );
BUFX4TS U1724 ( .A(FPMULT_Adder_M_Add_Subt_Result_net5038722), .Y(n3390) );
BUFX4TS U1725 ( .A(FPMULT_Adder_M_Add_Subt_Result_net5038722), .Y(n3391) );
BUFX4TS U1726 ( .A(FPMULT_Barrel_Shifter_module_Output_Reg_net5038740), .Y(
n3392) );
BUFX4TS U1727 ( .A(FPMULT_Barrel_Shifter_module_Output_Reg_net5038740), .Y(
n3394) );
BUFX6TS U1728 ( .A(n3404), .Y(n3403) );
BUFX4TS U1729 ( .A(FPADDSUB_FRMT_STAGE_DATAOUT_net5038542), .Y(n3472) );
BUFX4TS U1730 ( .A(FPADDSUB_FRMT_STAGE_DATAOUT_net5038542), .Y(n3473) );
BUFX4TS U1731 ( .A(FPADDSUB_FRMT_STAGE_DATAOUT_net5038542), .Y(n3474) );
BUFX4TS U1732 ( .A(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net5038542), .Y(
n3379) );
BUFX4TS U1733 ( .A(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net5038542), .Y(
n3381) );
BUFX4TS U1734 ( .A(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net5038542), .Y(
n3382) );
BUFX4TS U1735 ( .A(FPSENCOS_d_ff4_Yn_net5038830), .Y(n3433) );
BUFX4TS U1736 ( .A(FPSENCOS_d_ff4_Yn_net5038830), .Y(n3432) );
BUFX4TS U1737 ( .A(FPSENCOS_d_ff4_Yn_net5038830), .Y(n3434) );
BUFX4TS U1738 ( .A(FPADDSUB_NRM_STAGE_Raw_mant_net5038578), .Y(n3462) );
BUFX4TS U1739 ( .A(FPADDSUB_NRM_STAGE_Raw_mant_net5038578), .Y(n3464) );
BUFX4TS U1740 ( .A(FPADDSUB_NRM_STAGE_Raw_mant_net5038578), .Y(n3465) );
BUFX4TS U1741 ( .A(FPSENCOS_d_ff4_Xn_net5038830), .Y(n3436) );
BUFX4TS U1742 ( .A(FPSENCOS_d_ff4_Xn_net5038830), .Y(n3437) );
BUFX4TS U1743 ( .A(FPSENCOS_d_ff4_Xn_net5038830), .Y(n3438) );
BUFX4TS U1744 ( .A(FPSENCOS_d_ff5_data_out_net5038830), .Y(n3477) );
BUFX4TS U1745 ( .A(FPSENCOS_d_ff5_data_out_net5038830), .Y(n3476) );
BUFX4TS U1746 ( .A(FPSENCOS_d_ff5_data_out_net5038830), .Y(n3478) );
BUFX4TS U1747 ( .A(FPSENCOS_d_ff4_Zn_net5038830), .Y(n3428) );
BUFX4TS U1748 ( .A(FPSENCOS_d_ff4_Zn_net5038830), .Y(n3429) );
BUFX4TS U1749 ( .A(FPSENCOS_d_ff4_Zn_net5038830), .Y(n3430) );
BUFX4TS U1750 ( .A(FPADDSUB_SHT2_SHIFT_DATA_net5038578), .Y(n3398) );
BUFX4TS U1751 ( .A(FPADDSUB_SHT2_SHIFT_DATA_net5038578), .Y(n3400) );
BUFX4TS U1752 ( .A(FPADDSUB_SHT2_SHIFT_DATA_net5038578), .Y(n3401) );
BUFX4TS U1753 ( .A(FPSENCOS_reg_Z0_net5038830), .Y(n3460) );
BUFX4TS U1754 ( .A(FPSENCOS_reg_Z0_net5038830), .Y(n3458) );
BUFX4TS U1755 ( .A(FPSENCOS_reg_Z0_net5038830), .Y(n3461) );
INVX2TS U1756 ( .A(FPMULT_Op_MX[17]), .Y(n1045) );
INVX2TS U1757 ( .A(n1045), .Y(n1046) );
INVX2TS U1758 ( .A(n2602), .Y(n1152) );
OAI21X4TS U1759 ( .A0(FPMULT_FS_Module_state_reg[2]), .A1(
FPMULT_FSM_add_overflow_flag), .B0(n3192), .Y(n2602) );
BUFX6TS U1760 ( .A(n3479), .Y(n3480) );
BUFX4TS U1761 ( .A(n3479), .Y(n3483) );
BUFX3TS U1762 ( .A(n1291), .Y(n3482) );
INVX2TS U1763 ( .A(FPMULT_Op_MY[4]), .Y(n1047) );
INVX2TS U1764 ( .A(FPMULT_Op_MY[4]), .Y(n1048) );
CLKINVX1TS U1765 ( .A(n1842), .Y(n1049) );
NAND2X4TS U1766 ( .A(FPADDSUB_left_right_SHT2), .B(n922), .Y(n2006) );
NAND2X4TS U1767 ( .A(n3078), .B(n922), .Y(n2018) );
AOI211XLTS U1768 ( .A0(n923), .A1(n3063), .B0(n1152), .C0(n3122), .Y(n1842)
);
INVX2TS U1769 ( .A(n2672), .Y(n1050) );
INVX2TS U1770 ( .A(n1050), .Y(n1051) );
INVX2TS U1771 ( .A(n1050), .Y(n1052) );
INVX2TS U1772 ( .A(n1812), .Y(n1053) );
INVX2TS U1773 ( .A(n1053), .Y(n1054) );
INVX2TS U1774 ( .A(n1053), .Y(n1055) );
INVX2TS U1775 ( .A(n2135), .Y(n1056) );
INVX2TS U1776 ( .A(n2135), .Y(n1057) );
INVX2TS U1777 ( .A(n2135), .Y(n1058) );
AOI2BB2X2TS U1778 ( .B0(FPMULT_Op_MX[4]), .B1(n2472), .A0N(n1464), .A1N(
FPMULT_Op_MX[4]), .Y(n1430) );
INVX2TS U1779 ( .A(n2771), .Y(n1059) );
INVX2TS U1780 ( .A(n1059), .Y(n1060) );
INVX2TS U1781 ( .A(n1059), .Y(n1061) );
INVX2TS U1782 ( .A(n2764), .Y(n1062) );
INVX2TS U1783 ( .A(n1062), .Y(n1063) );
INVX2TS U1784 ( .A(n1062), .Y(n1064) );
NOR2X2TS U1785 ( .A(n1384), .B(n1038), .Y(n1822) );
NOR2X4TS U1786 ( .A(FPADDSUB_left_right_SHT2), .B(n2570), .Y(n2015) );
NAND2X1TS U1787 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(
FPADDSUB_bit_shift_SHT2), .Y(n2570) );
NOR2X2TS U1788 ( .A(n1036), .B(n1039), .Y(n1713) );
NOR2X2TS U1789 ( .A(n1787), .B(n1430), .Y(n1724) );
BUFX6TS U1790 ( .A(FPSENCOS_reg_shift_y_net5038830), .Y(n3439) );
BUFX6TS U1791 ( .A(FPSENCOS_reg_val_muxZ_2stage_net5038830), .Y(n3448) );
BUFX6TS U1792 ( .A(FPMULT_Operands_load_reg_XMRegister_net5038794), .Y(n3387) );
BUFX6TS U1793 ( .A(FPMULT_Operands_load_reg_XMRegister_net5038794), .Y(n3388) );
BUFX6TS U1794 ( .A(FPMULT_Operands_load_reg_XMRegister_net5038794), .Y(n3385) );
BUFX6TS U1795 ( .A(FPMULT_Operands_load_reg_XMRegister_net5038794), .Y(n3384) );
BUFX6TS U1796 ( .A(FPMULT_Operands_load_reg_XMRegister_net5038794), .Y(n3383) );
BUFX3TS U1797 ( .A(FPADDSUB_EXP_STAGE_DMP_net5038596), .Y(n3419) );
BUFX3TS U1798 ( .A(FPMULT_Sgf_operation_finalreg_net5038758), .Y(n3397) );
BUFX3TS U1799 ( .A(FPADDSUB_SHT1_STAGE_DMP_net5038596), .Y(n3412) );
INVX2TS U1800 ( .A(n3115), .Y(n1065) );
INVX2TS U1801 ( .A(n1065), .Y(n1066) );
INVX2TS U1802 ( .A(n1065), .Y(n1067) );
INVX2TS U1803 ( .A(n3060), .Y(n1068) );
INVX2TS U1804 ( .A(n1068), .Y(n1069) );
INVX2TS U1805 ( .A(n1068), .Y(n1070) );
INVX2TS U1806 ( .A(FPMULT_Op_MY[19]), .Y(n1071) );
INVX2TS U1807 ( .A(FPMULT_Op_MY[19]), .Y(n1072) );
OR2X1TS U1808 ( .A(n3496), .B(n3495), .Y(n2592) );
INVX2TS U1809 ( .A(n2592), .Y(n1073) );
INVX2TS U1810 ( .A(n2592), .Y(n1074) );
INVX2TS U1811 ( .A(n2592), .Y(n1075) );
INVX1TS U1812 ( .A(n1676), .Y(n1683) );
NOR2X2TS U1813 ( .A(FPADDSUB_N60), .B(FPADDSUB_N59), .Y(n2079) );
INVX2TS U1814 ( .A(n1448), .Y(n1076) );
INVX2TS U1815 ( .A(n1448), .Y(n1077) );
INVX2TS U1816 ( .A(n1448), .Y(n1078) );
AOI22X2TS U1817 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n1457), .B1(n3121),
.Y(n3503) );
NOR4BX2TS U1818 ( .AN(n1286), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]),
.C(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .D(n1140), .Y(n1454) );
NOR4X1TS U1819 ( .A(Data_2[2]), .B(Data_2[10]), .C(Data_2[12]), .D(
Data_2[14]), .Y(n3278) );
NOR4X1TS U1820 ( .A(Data_2[7]), .B(Data_2[9]), .C(Data_2[11]), .D(Data_2[6]),
.Y(n3277) );
NOR4X1TS U1821 ( .A(Data_2[17]), .B(Data_2[16]), .C(Data_2[8]), .D(n1144),
.Y(n3273) );
NOR2X2TS U1822 ( .A(FPMULT_Op_MY[15]), .B(n1491), .Y(n1472) );
NOR2X2TS U1823 ( .A(n2690), .B(n1472), .Y(n1313) );
NOR2X2TS U1824 ( .A(n3164), .B(n2831), .Y(n2830) );
NOR2X2TS U1825 ( .A(FPMULT_Sgf_normalized_result[4]), .B(n2832), .Y(n2831)
);
NOR2X2TS U1826 ( .A(n3162), .B(n2815), .Y(n2814) );
NOR2X2TS U1827 ( .A(n3155), .B(n2829), .Y(n2828) );
CLKINVX3TS U1828 ( .A(n1016), .Y(n2614) );
NOR2X2TS U1829 ( .A(FPMULT_Op_MY[16]), .B(n1473), .Y(n1312) );
NOR3X6TS U1830 ( .A(n1231), .B(n1228), .C(n1227), .Y(n3495) );
XNOR2X2TS U1831 ( .A(DP_OP_26J196_122_5882_n1), .B(FPADDSUB_ADD_OVRFLW_NRM2),
.Y(n1231) );
NOR4X1TS U1832 ( .A(FPMULT_Op_MX[18]), .B(FPMULT_Op_MX[19]), .C(n1883), .D(
n1882), .Y(n1884) );
OAI33X1TS U1833 ( .A0(FPSENCOS_d_ff1_shift_region_flag_out[0]), .A1(n3235),
.A2(n3113), .B0(n3077), .B1(FPSENCOS_d_ff1_shift_region_flag_out[1]),
.B2(FPSENCOS_d_ff1_operation_out), .Y(n3004) );
AOI21X2TS U1834 ( .A0(FPMULT_Op_MY[13]), .A1(n1534), .B0(FPMULT_Op_MY[14]),
.Y(n1492) );
NOR2X2TS U1835 ( .A(n1492), .B(n2469), .Y(n1473) );
AOI21X2TS U1836 ( .A0(FPMULT_Op_MY[3]), .A1(n1347), .B0(FPMULT_Op_MY[4]),
.Y(n1340) );
NOR2X2TS U1837 ( .A(FPADDSUB_DMP_SFG[21]), .B(n3205), .Y(n2027) );
NOR2BX2TS U1838 ( .AN(FPADDSUB_DMP_SFG[2]), .B(n3153), .Y(n1693) );
AOI222X4TS U1839 ( .A0(FPADDSUB_DMP_SFG[21]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[23]), .B0(FPADDSUB_DMP_SFG[21]), .B1(n2021),
.C0(FPADDSUB_DmP_mant_SFG_SWR[23]), .C1(n2021), .Y(n2631) );
OAI2BB2X2TS U1840 ( .B0(n2603), .B1(n2604), .A0N(FPADDSUB_DMP_SFG[20]),
.A1N(FPADDSUB_DmP_mant_SFG_SWR[22]), .Y(n2021) );
NOR2X2TS U1841 ( .A(n3199), .B(n3114), .Y(n2629) );
NOR2X4TS U1842 ( .A(n3080), .B(n3062), .Y(n3047) );
OAI22X2TS U1843 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[6]), .A1(FPADDSUB_DMP_SFG[4]), .B0(n2008), .B1(n2007), .Y(n2925) );
AOI2BB2X2TS U1844 ( .B0(n1016), .B1(n3038), .A0N(n3036), .A1N(n2305), .Y(
n2082) );
OAI22X2TS U1845 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[13]), .A1(n3146), .B0(n2953),
.B1(n2011), .Y(n2960) );
CLKINVX3TS U1846 ( .A(n1721), .Y(n2762) );
AOI2BB2X2TS U1847 ( .B0(n2928), .B1(n2929), .A0N(n3170), .A1N(
FPADDSUB_DmP_mant_SFG_SWR[8]), .Y(n2935) );
CLKBUFX3TS U1848 ( .A(n2264), .Y(n2204) );
CLKBUFX3TS U1849 ( .A(n3212), .Y(n2264) );
CLKBUFX3TS U1850 ( .A(n2623), .Y(n3001) );
NOR2X4TS U1851 ( .A(n1639), .B(n1638), .Y(n2036) );
NOR2X4TS U1852 ( .A(n2600), .B(n1507), .Y(n2045) );
NAND2X2TS U1853 ( .A(FPADDSUB_bit_shift_SHT2), .B(
FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n1653) );
NOR3X2TS U1854 ( .A(enab_cont_iter), .B(n2626), .C(ready_add_subt), .Y(n3053) );
NOR3BX2TS U1855 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .C(n1453), .Y(n2626) );
NOR3BX2TS U1856 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .C(n1290), .Y(
FPSENCOS_enab_RB3) );
NOR2X2TS U1857 ( .A(n3163), .B(n2833), .Y(n2832) );
NOR3X2TS U1858 ( .A(FPMULT_Sgf_normalized_result[2]), .B(
FPMULT_Sgf_normalized_result[1]), .C(FPMULT_Sgf_normalized_result[0]),
.Y(n2833) );
AOI211X2TS U1859 ( .A0(FPADDSUB_intDY_EWSW[8]), .A1(n3087), .B0(n2845), .C0(
n2844), .Y(n2889) );
AOI22X2TS U1860 ( .A0(FPMULT_Op_MX[8]), .A1(FPMULT_Op_MX[7]), .B0(n3182),
.B1(n2725), .Y(n1445) );
CLKBUFX3TS U1861 ( .A(n3213), .Y(n2725) );
AOI211X4TS U1862 ( .A0(FPADDSUB_Data_array_SWR[42]), .A1(n949), .B0(n2571),
.C0(n1838), .Y(n2000) );
NOR2X2TS U1863 ( .A(n1653), .B(n3206), .Y(n2571) );
AOI222X4TS U1864 ( .A0(FPADDSUB_DMP_SFG[10]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[12]), .B0(FPADDSUB_DMP_SFG[10]), .B1(n2949),
.C0(FPADDSUB_DmP_mant_SFG_SWR[12]), .C1(n2949), .Y(n2954) );
AOI222X4TS U1865 ( .A0(n2944), .A1(n3096), .B0(n2944), .B1(n3148), .C0(n3096), .C1(n3148), .Y(n2949) );
NOR2X2TS U1866 ( .A(n2732), .B(n3151), .Y(n2135) );
AOI22X4TS U1867 ( .A0(FPMULT_Op_MX[20]), .A1(n3104), .B0(FPMULT_Op_MX[21]),
.B1(n3068), .Y(n2732) );
OAI31X2TS U1868 ( .A0(n1782), .A1(n3210), .A2(n1781), .B0(n1780), .Y(n2409)
);
AOI222X4TS U1869 ( .A0(FPADDSUB_DMP_SFG[18]), .A1(n3188), .B0(
FPADDSUB_DMP_SFG[18]), .B1(n2536), .C0(n3188), .C1(n2536), .Y(n2993)
);
AOI222X4TS U1870 ( .A0(FPADDSUB_DMP_SFG[14]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[16]), .B0(FPADDSUB_DMP_SFG[14]), .B1(n2970),
.C0(FPADDSUB_DmP_mant_SFG_SWR[16]), .C1(n2970), .Y(n2975) );
OAI2BB2X2TS U1871 ( .B0(n2963), .B1(n2964), .A0N(FPADDSUB_DMP_SFG[13]),
.A1N(FPADDSUB_DmP_mant_SFG_SWR[15]), .Y(n2970) );
CLKBUFX3TS U1872 ( .A(n2515), .Y(n2835) );
CLKBUFX3TS U1873 ( .A(n2512), .Y(n2515) );
CLKBUFX3TS U1874 ( .A(n3486), .Y(n1136) );
CLKINVX3TS U1875 ( .A(n3014), .Y(n3018) );
CLKBUFX3TS U1876 ( .A(n3012), .Y(n3014) );
NAND3BX1TS U1877 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(n1287),
.C(n3165), .Y(n1290) );
NOR4X2TS U1878 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .Y(n1287) );
CLKBUFX2TS U1879 ( .A(FPSENCOS_cont_iter_out[2]), .Y(n1079) );
OAI32X1TS U1880 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n3048), .A2(n3056),
.B0(FPSENCOS_cont_iter_out[2]), .B1(n3080), .Y(n860) );
INVX2TS U1881 ( .A(n2064), .Y(n1080) );
CLKINVX3TS U1882 ( .A(n2064), .Y(n3021) );
NOR2X4TS U1883 ( .A(n1639), .B(n1507), .Y(n2064) );
INVX3TS U1884 ( .A(n1299), .Y(n3366) );
BUFX6TS U1885 ( .A(FPMULT_Barrel_Shifter_module_Output_Reg_net5038740), .Y(
n3393) );
BUFX6TS U1886 ( .A(n3418), .Y(n3416) );
BUFX3TS U1887 ( .A(FPADDSUB_EXP_STAGE_DMP_net5038596), .Y(n3418) );
BUFX6TS U1888 ( .A(n3411), .Y(n3407) );
BUFX3TS U1889 ( .A(FPADDSUB_SHT1_STAGE_DMP_net5038596), .Y(n3411) );
BUFX6TS U1890 ( .A(FPMULT_Adder_M_Add_Subt_Result_net5038722), .Y(n3389) );
BUFX6TS U1891 ( .A(FPADDSUB_FRMT_STAGE_DATAOUT_net5038542), .Y(n3471) );
BUFX6TS U1892 ( .A(FPADDSUB_SHT2_SHIFT_DATA_net5038578), .Y(n3399) );
BUFX6TS U1893 ( .A(FPADDSUB_NRM_STAGE_Raw_mant_net5038578), .Y(n3463) );
BUFX6TS U1894 ( .A(FPSENCOS_d_ff4_Zn_net5038830), .Y(n3427) );
BUFX6TS U1895 ( .A(FPSENCOS_reg_Z0_net5038830), .Y(n3459) );
BUFX6TS U1896 ( .A(
FPMULT_final_result_ieee_Module_Final_Result_IEEE_net5038542), .Y(
n3380) );
BUFX6TS U1897 ( .A(FPSENCOS_d_ff5_data_out_net5038830), .Y(n3475) );
BUFX6TS U1898 ( .A(FPSENCOS_d_ff4_Yn_net5038830), .Y(n3431) );
BUFX6TS U1899 ( .A(FPSENCOS_d_ff4_Xn_net5038830), .Y(n3435) );
INVX2TS U1900 ( .A(n2485), .Y(n1081) );
OAI22X2TS U1901 ( .A0(n3118), .A1(FPMULT_Op_MX[12]), .B0(n3103), .B1(
FPMULT_Op_MX[11]), .Y(n1379) );
CLKBUFX3TS U1902 ( .A(n1619), .Y(n2485) );
BUFX4TS U1903 ( .A(n3479), .Y(n3481) );
CLKBUFX3TS U1904 ( .A(n1843), .Y(n1082) );
CLKBUFX3TS U1905 ( .A(n1843), .Y(n1083) );
INVX2TS U1906 ( .A(n2731), .Y(n1084) );
AOI222X1TS U1907 ( .A0(n1710), .A1(FPMULT_Op_MY[0]), .B0(n1361), .B1(
FPMULT_Op_MY[1]), .C0(n1709), .C1(n1770), .Y(n1362) );
AOI222X4TS U1908 ( .A0(n1062), .A1(FPMULT_Op_MY[0]), .B0(n1448), .B1(
FPMULT_Op_MY[1]), .C0(n1721), .C1(n1770), .Y(n1447) );
AOI222X4TS U1909 ( .A0(n1820), .A1(n1084), .B0(n1771), .B1(FPMULT_Op_MY[1]),
.C0(n1816), .C1(n1770), .Y(n1772) );
AOI222X4TS U1910 ( .A0(n1380), .A1(FPMULT_Op_MY[1]), .B0(n1717), .B1(n1084),
.C0(n1716), .C1(n1770), .Y(n1397) );
CLKBUFX3TS U1911 ( .A(n3217), .Y(n2731) );
CLKBUFX2TS U1912 ( .A(n1710), .Y(n2709) );
INVX2TS U1913 ( .A(n2709), .Y(n1085) );
INVX2TS U1914 ( .A(n2709), .Y(n1086) );
INVX2TS U1915 ( .A(n2709), .Y(n1087) );
NOR2X4TS U1916 ( .A(rst), .B(enab_cont_iter), .Y(n1300) );
NOR3BX4TS U1917 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .C(n1290), .Y(
enab_cont_iter) );
CLKAND2X2TS U1918 ( .A(n1320), .B(n1319), .Y(n2707) );
INVX2TS U1919 ( .A(n2707), .Y(n1088) );
INVX2TS U1920 ( .A(n2707), .Y(n1089) );
INVX2TS U1921 ( .A(n2707), .Y(n1090) );
INVX2TS U1922 ( .A(n1771), .Y(n1091) );
INVX2TS U1923 ( .A(n1771), .Y(n1092) );
INVX2TS U1924 ( .A(n1771), .Y(n1093) );
CLKBUFX3TS U1925 ( .A(n2318), .Y(n1094) );
CLKBUFX3TS U1926 ( .A(n2318), .Y(n1095) );
CLKBUFX3TS U1927 ( .A(n2478), .Y(n1096) );
CLKBUFX3TS U1928 ( .A(n2478), .Y(n1097) );
CLKBUFX3TS U1929 ( .A(n2468), .Y(n1098) );
CLKBUFX3TS U1930 ( .A(n2468), .Y(n1099) );
BUFX4TS U1931 ( .A(FPMULT_Operands_load_reg_XMRegister_net5038794), .Y(n3386) );
BUFX4TS U1932 ( .A(n3395), .Y(n3396) );
INVX2TS U1933 ( .A(n1380), .Y(n1100) );
INVX2TS U1934 ( .A(n1380), .Y(n1101) );
INVX2TS U1935 ( .A(n1380), .Y(n2673) );
NOR2X2TS U1936 ( .A(n1395), .B(n1376), .Y(n1380) );
CLKBUFX2TS U1937 ( .A(n2581), .Y(n1102) );
INVX2TS U1938 ( .A(n1707), .Y(n1103) );
INVX2TS U1939 ( .A(n1707), .Y(n1104) );
INVX2TS U1940 ( .A(n1707), .Y(n2789) );
NOR2X2TS U1941 ( .A(n2732), .B(FPMULT_Op_MX[22]), .Y(n1707) );
INVX2TS U1942 ( .A(n1716), .Y(n1105) );
INVX2TS U1943 ( .A(n1716), .Y(n1106) );
INVX2TS U1944 ( .A(n1716), .Y(n2674) );
NOR2X2TS U1945 ( .A(n1395), .B(n1373), .Y(n1716) );
BUFX6TS U1946 ( .A(FPSENCOS_reg_val_muxZ_2stage_net5038830), .Y(n3455) );
BUFX6TS U1947 ( .A(FPSENCOS_reg_shift_y_net5038830), .Y(n3445) );
AOI22X1TS U1948 ( .A0(FPMULT_Op_MY[21]), .A1(FPMULT_Op_MY[22]), .B0(n3061),
.B1(n2809), .Y(n2072) );
OR2X1TS U1949 ( .A(FPADDSUB_ADD_OVRFLW_NRM), .B(n3079), .Y(n679) );
INVX2TS U1950 ( .A(n679), .Y(n1107) );
INVX2TS U1951 ( .A(n679), .Y(n1108) );
INVX2TS U1952 ( .A(n679), .Y(n1109) );
OAI31X2TS U1953 ( .A0(n1108), .A1(n1665), .A2(FPADDSUB_DmP_mant_SHT1_SW[3]),
.B0(n1505), .Y(n1983) );
OAI31X2TS U1954 ( .A0(n1109), .A1(n1849), .A2(FPADDSUB_DmP_mant_SHT1_SW[10]),
.B0(n1848), .Y(n2028) );
AOI22X2TS U1955 ( .A0(n1108), .A1(FPADDSUB_LZD_raw_out_EWR[1]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[1]), .B1(n966), .Y(n2600) );
CLKBUFX3TS U1956 ( .A(FPADDSUB_left_right_SHT2), .Y(n1110) );
CLKBUFX3TS U1957 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n1111) );
OAI211XLTS U1958 ( .A0(FPADDSUB_intDX_EWSW[2]), .A1(n3086), .B0(n2896), .C0(
n2846), .Y(n2847) );
OAI21XLTS U1959 ( .A0(n2849), .A1(n2848), .B0(n2847), .Y(n2850) );
OAI211XLTS U1960 ( .A0(FPADDSUB_intDY_EWSW[11]), .A1(n3142), .B0(n2856),
.C0(n2855), .Y(n2857) );
NOR2XLTS U1961 ( .A(n1358), .B(n1357), .Y(n1360) );
OAI21XLTS U1962 ( .A0(n1580), .A1(n1579), .B0(n2258), .Y(n1578) );
OAI21XLTS U1963 ( .A0(n1544), .A1(n1543), .B0(n1619), .Y(n1542) );
OAI21XLTS U1964 ( .A0(n1486), .A1(n1485), .B0(n1553), .Y(n1484) );
OAI21XLTS U1965 ( .A0(n2232), .A1(n2231), .B0(n2264), .Y(n2230) );
NOR2XLTS U1966 ( .A(n1061), .B(n2770), .Y(n2774) );
OAI21XLTS U1967 ( .A0(n2486), .A1(n2484), .B0(n2482), .Y(n2483) );
OAI21XLTS U1968 ( .A0(n2476), .A1(n2474), .B0(n2472), .Y(n2473) );
OAI21XLTS U1969 ( .A0(n2465), .A1(n2464), .B0(n2472), .Y(n2463) );
OAI21XLTS U1970 ( .A0(n2229), .A1(n2228), .B0(n2765), .Y(n2227) );
OAI21XLTS U1971 ( .A0(n2714), .A1(n1061), .B0(n2157), .Y(n2201) );
OAI21XLTS U1972 ( .A0(n2091), .A1(n2090), .B0(n2324), .Y(n2089) );
OAI21XLTS U1973 ( .A0(n1636), .A1(n1635), .B0(n2258), .Y(n1634) );
NOR2XLTS U1974 ( .A(FPADDSUB_intDX_EWSW[23]), .B(n3085), .Y(n2869) );
OAI21XLTS U1975 ( .A0(n1525), .A1(n1524), .B0(n1464), .Y(n1523) );
OAI21XLTS U1976 ( .A0(n1489), .A1(n1488), .B0(n1326), .Y(n1487) );
OAI21XLTS U1977 ( .A0(n1610), .A1(n1609), .B0(n2324), .Y(n1608) );
OAI21XLTS U1978 ( .A0(n1369), .A1(n1368), .B0(n2324), .Y(n1367) );
OAI21XLTS U1979 ( .A0(n2172), .A1(n2171), .B0(n2264), .Y(n2170) );
NOR2XLTS U1980 ( .A(n1587), .B(n1586), .Y(mult_x_69_n607) );
OAI21XLTS U1981 ( .A0(n2693), .A1(n2692), .B0(n2701), .Y(n2691) );
OAI21XLTS U1982 ( .A0(n2268), .A1(n2266), .B0(n2264), .Y(n2265) );
OAI21XLTS U1983 ( .A0(n1745), .A1(n1744), .B0(n1877), .Y(n1743) );
NOR2XLTS U1984 ( .A(n1091), .B(n2757), .Y(n1778) );
OAI21XLTS U1985 ( .A0(n2207), .A1(n2206), .B0(n2204), .Y(n2205) );
OAI21XLTS U1986 ( .A0(n2187), .A1(n2186), .B0(n2324), .Y(n2185) );
OAI21XLTS U1987 ( .A0(n2085), .A1(n2084), .B0(n2701), .Y(n2083) );
OAI21XLTS U1988 ( .A0(n1519), .A1(n1518), .B0(n2701), .Y(n1517) );
OAI21XLTS U1989 ( .A0(n1618), .A1(n1617), .B0(n2482), .Y(n1616) );
OAI21XLTS U1990 ( .A0(n2704), .A1(n2703), .B0(n2701), .Y(n2702) );
OAI21XLTS U1991 ( .A0(n1764), .A1(n1763), .B0(n1817), .Y(n1762) );
OAI21XLTS U1992 ( .A0(n1733), .A1(n1732), .B0(n1877), .Y(n1731) );
OAI211XLTS U1993 ( .A0(n1088), .A1(n918), .B0(n1711), .C0(n1021), .Y(n1712)
);
OAI211XLTS U1994 ( .A0(n2750), .A1(n918), .B0(n1722), .C0(n1076), .Y(n1723)
);
INVX2TS U1995 ( .A(mult_x_69_n209), .Y(n1972) );
INVX2TS U1996 ( .A(mult_x_69_n296), .Y(n1945) );
INVX2TS U1997 ( .A(mult_x_69_n222), .Y(n1912) );
NOR3XLTS U1998 ( .A(dataB[29]), .B(dataB[31]), .C(n2906), .Y(n2903) );
OAI21XLTS U1999 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[5]), .A1(FPADDSUB_DMP_SFG[3]), .B0(n2920), .Y(n2921) );
OAI21XLTS U2000 ( .A0(n3147), .A1(FPADDSUB_DmP_mant_SFG_SWR[12]), .B0(n2948),
.Y(n2952) );
OR2X1TS U2001 ( .A(n1458), .B(n3503), .Y(n875) );
OAI21XLTS U2002 ( .A0(n1080), .A1(n2033), .B0(n2032), .Y(
FPADDSUB_Data_array_SWR[13]) );
OR2X1TS U2003 ( .A(FPSENCOS_d_ff_Xn[27]), .B(n2664), .Y(
FPSENCOS_first_mux_X[27]) );
OAI21XLTS U2004 ( .A0(n1080), .A1(n1979), .B0(n1854), .Y(
FPADDSUB_Data_array_SWR[8]) );
OAI21XLTS U2005 ( .A0(n2601), .A1(n2602), .B0(n1844), .Y(n3526) );
OR2X1TS U2006 ( .A(FPSENCOS_d_ff_Xn[24]), .B(n1864), .Y(
FPSENCOS_first_mux_X[24]) );
OAI21XLTS U2007 ( .A0(n975), .A1(n1983), .B0(n1982), .Y(
FPADDSUB_Data_array_SWR[4]) );
OAI21XLTS U2008 ( .A0(n1080), .A1(n1983), .B0(n1892), .Y(
FPADDSUB_Data_array_SWR[5]) );
OR2X1TS U2009 ( .A(FPSENCOS_d_ff_Xn[20]), .B(n1864), .Y(
FPSENCOS_first_mux_X[20]) );
OR2X1TS U2010 ( .A(FPSENCOS_d_ff_Xn[12]), .B(n1864), .Y(
FPSENCOS_first_mux_X[12]) );
OAI21XLTS U2011 ( .A0(FPADDSUB_DmP_EXP_EWSW[23]), .A1(n3200), .B0(n2643),
.Y(FPADDSUB_Shift_amount_EXP_EW[0]) );
NOR2XLTS U2012 ( .A(n3162), .B(n2020), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[21]) );
NOR2XLTS U2013 ( .A(n3156), .B(n2020), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[9]) );
OAI211XLTS U2014 ( .A0(n2052), .A1(n971), .B0(n2050), .C0(n2042), .Y(
FPADDSUB_Data_array_SWR[0]) );
OAI31X1TS U2015 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .A2(n3081), .B0(n1457),
.Y(n874) );
NOR2XLTS U2016 ( .A(n2599), .B(n1639), .Y(FPADDSUB_Data_array_SWR[25]) );
OAI21XLTS U2017 ( .A0(n1080), .A1(n2059), .B0(n1667), .Y(
FPADDSUB_Data_array_SWR[20]) );
OR2X1TS U2018 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[5]), .B(n3495), .Y(
FPADDSUB_formatted_number_W[28]) );
OAI21XLTS U2019 ( .A0(n2782), .A1(n3269), .B0(n2269), .Y(op_result[0]) );
OAI21XLTS U2020 ( .A0(n2782), .A1(n3264), .B0(n2275), .Y(op_result[5]) );
OAI21XLTS U2021 ( .A0(n2305), .A1(n3249), .B0(n2294), .Y(op_result[20]) );
NOR2X1TS U2022 ( .A(FPADDSUB_Raw_mant_NRM_SWR[11]), .B(
FPADDSUB_Raw_mant_NRM_SWR[10]), .Y(n1121) );
NOR3X1TS U2023 ( .A(FPADDSUB_Raw_mant_NRM_SWR[15]), .B(
FPADDSUB_Raw_mant_NRM_SWR[16]), .C(FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(
n1113) );
NOR3X1TS U2024 ( .A(FPADDSUB_Raw_mant_NRM_SWR[19]), .B(
FPADDSUB_Raw_mant_NRM_SWR[20]), .C(FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(
n1677) );
NAND2X1TS U2025 ( .A(n1677), .B(n1679), .Y(n1130) );
NAND2X1TS U2026 ( .A(n1113), .B(n2639), .Y(n1112) );
NOR2X1TS U2027 ( .A(FPADDSUB_Raw_mant_NRM_SWR[14]), .B(n1112), .Y(n1675) );
NAND2X1TS U2028 ( .A(n1675), .B(n3111), .Y(n1122) );
NOR2X1TS U2029 ( .A(n3191), .B(n1112), .Y(n1133) );
NOR2X1TS U2030 ( .A(FPADDSUB_Raw_mant_NRM_SWR[7]), .B(
FPADDSUB_Raw_mant_NRM_SWR[6]), .Y(n1114) );
NOR2X1TS U2031 ( .A(FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n1281) );
NOR2X1TS U2032 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(
FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(n1685) );
AOI21X1TS U2033 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[10]), .A1(n3181), .B0(
FPADDSUB_Raw_mant_NRM_SWR[12]), .Y(n1123) );
NAND4XLTS U2034 ( .A(n1113), .B(n1685), .C(n1123), .D(n3191), .Y(n2638) );
NOR2BX1TS U2035 ( .AN(n2639), .B(n2638), .Y(n1280) );
NAND2X1TS U2036 ( .A(n1281), .B(n1280), .Y(n1135) );
NOR2X1TS U2037 ( .A(FPADDSUB_Raw_mant_NRM_SWR[2]), .B(
FPADDSUB_Raw_mant_NRM_SWR[3]), .Y(n2641) );
NOR2BX1TS U2038 ( .AN(n1114), .B(n1135), .Y(n1681) );
INVX2TS U2039 ( .A(n1681), .Y(n1126) );
NOR2X1TS U2040 ( .A(FPADDSUB_Raw_mant_NRM_SWR[5]), .B(n1126), .Y(n1282) );
NAND2X1TS U2041 ( .A(n1282), .B(n3209), .Y(n2637) );
OAI22X1TS U2042 ( .A0(n1114), .A1(n1135), .B0(n2641), .B1(n2637), .Y(n1285)
);
NOR2XLTS U2043 ( .A(FPADDSUB_Raw_mant_NRM_SWR[20]), .B(
FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(n1115) );
AOI211X1TS U2044 ( .A0(n1115), .A1(FPADDSUB_Raw_mant_NRM_SWR[19]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[22]), .C0(FPADDSUB_Raw_mant_NRM_SWR[23]),
.Y(n1118) );
NOR2XLTS U2045 ( .A(FPADDSUB_Raw_mant_NRM_SWR[16]), .B(
FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n1116) );
INVX2TS U2046 ( .A(n1130), .Y(n1124) );
AOI32X1TS U2047 ( .A0(n1116), .A1(n1124), .A2(FPADDSUB_Raw_mant_NRM_SWR[15]),
.B0(FPADDSUB_Raw_mant_NRM_SWR[18]), .B1(n1124), .Y(n1117) );
OAI31X1TS U2048 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[24]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[25]), .A2(n1118), .B0(n1117), .Y(n1119) );
NOR3X1TS U2049 ( .A(n1133), .B(n1285), .C(n1119), .Y(n1120) );
OAI31X1TS U2050 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[12]), .A1(n1121), .A2(n1122),
.B0(n1120), .Y(FPADDSUB_LZD_raw_out_EWR[1]) );
NOR4BBX1TS U2051 ( .AN(n1121), .BN(FPADDSUB_Raw_mant_NRM_SWR[8]), .C(
FPADDSUB_Raw_mant_NRM_SWR[9]), .D(n1122), .Y(n1132) );
AOI211X1TS U2052 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(n3204), .B0(
FPADDSUB_Raw_mant_NRM_SWR[2]), .C0(FPADDSUB_Raw_mant_NRM_SWR[4]), .Y(
n1127) );
OAI2BB1X1TS U2053 ( .A0N(FPADDSUB_Raw_mant_NRM_SWR[3]), .A1N(n3209), .B0(
n3067), .Y(n1680) );
AOI2BB2XLTS U2054 ( .B0(n1124), .B1(FPADDSUB_Raw_mant_NRM_SWR[18]), .A0N(
n1123), .A1N(n1122), .Y(n1125) );
OAI31X1TS U2055 ( .A0(n1127), .A1(n1126), .A2(n1680), .B0(n1125), .Y(n1676)
);
OAI32X1TS U2056 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[23]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[21]), .A2(n3112), .B0(n3183), .B1(
FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n1128) );
OAI21XLTS U2057 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[24]), .A1(n1128), .B0(n3208),
.Y(n1129) );
OAI31X1TS U2058 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[17]), .A1(n3236), .A2(n1130),
.B0(n1129), .Y(n1131) );
NOR4X1TS U2059 ( .A(n1133), .B(n1132), .C(n1676), .D(n1131), .Y(n1134) );
BUFX3TS U2060 ( .A(n1139), .Y(n3358) );
NOR2X1TS U2061 ( .A(FPMULT_FS_Module_state_reg[3]), .B(
FPMULT_FS_Module_state_reg[2]), .Y(n3032) );
NAND2X2TS U2062 ( .A(n2518), .B(n3032), .Y(n826) );
BUFX3TS U2063 ( .A(n3486), .Y(n3342) );
BUFX3TS U2064 ( .A(n1139), .Y(n3351) );
BUFX3TS U2065 ( .A(n1138), .Y(n3323) );
BUFX3TS U2066 ( .A(n1138), .Y(n3325) );
BUFX3TS U2067 ( .A(n3360), .Y(n3326) );
BUFX3TS U2068 ( .A(n1136), .Y(n3328) );
BUFX3TS U2069 ( .A(n3347), .Y(n3336) );
BUFX3TS U2070 ( .A(n3347), .Y(n3329) );
BUFX3TS U2071 ( .A(n1137), .Y(n3330) );
BUFX3TS U2072 ( .A(n3360), .Y(n3348) );
BUFX3TS U2073 ( .A(n1139), .Y(n3349) );
BUFX3TS U2074 ( .A(n1138), .Y(n3350) );
BUFX3TS U2075 ( .A(n1136), .Y(n3340) );
CLKBUFX3TS U2076 ( .A(n1137), .Y(n3359) );
BUFX3TS U2077 ( .A(n3347), .Y(n3357) );
BUFX3TS U2078 ( .A(n1136), .Y(n3324) );
BUFX3TS U2079 ( .A(n3360), .Y(n3354) );
BUFX3TS U2080 ( .A(n1138), .Y(n3356) );
CLKBUFX3TS U2081 ( .A(n1300), .Y(n1301) );
BUFX3TS U2082 ( .A(n3318), .Y(n3300) );
BUFX3TS U2083 ( .A(n1136), .Y(n3353) );
BUFX3TS U2084 ( .A(n1139), .Y(n3343) );
BUFX3TS U2085 ( .A(n1139), .Y(n3322) );
BUFX3TS U2086 ( .A(n1138), .Y(n3321) );
BUFX3TS U2087 ( .A(n1138), .Y(n3320) );
BUFX3TS U2088 ( .A(n3359), .Y(n3319) );
BUFX3TS U2089 ( .A(n1139), .Y(n3338) );
BUFX3TS U2090 ( .A(n1136), .Y(n3337) );
BUFX3TS U2091 ( .A(n1139), .Y(n3327) );
BUFX3TS U2092 ( .A(n3347), .Y(n3335) );
BUFX3TS U2093 ( .A(n3360), .Y(n3334) );
BUFX3TS U2094 ( .A(n1300), .Y(n3298) );
BUFX3TS U2095 ( .A(n1138), .Y(n3341) );
BUFX3TS U2096 ( .A(n1136), .Y(n3339) );
CLKBUFX2TS U2097 ( .A(n1136), .Y(n3346) );
BUFX3TS U2098 ( .A(n1138), .Y(n3345) );
BUFX3TS U2099 ( .A(n3347), .Y(n3352) );
BUFX3TS U2100 ( .A(n3486), .Y(n3355) );
CLKBUFX3TS U2101 ( .A(n1300), .Y(n3295) );
BUFX3TS U2102 ( .A(n1300), .Y(n3296) );
BUFX3TS U2103 ( .A(n1300), .Y(n3290) );
BUFX3TS U2104 ( .A(n1300), .Y(n3291) );
BUFX3TS U2105 ( .A(n1136), .Y(n3344) );
CLKBUFX2TS U2106 ( .A(n1139), .Y(n3331) );
BUFX3TS U2107 ( .A(n3331), .Y(n3332) );
BUFX3TS U2108 ( .A(n3347), .Y(n3333) );
NOR2X1TS U2109 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n1286) );
OR2X1TS U2110 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .Y(n1140) );
NAND3BX1TS U2111 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .C(n1454), .Y(n2781) );
NAND2X1TS U2112 ( .A(FPSENCOS_cont_iter_out[2]), .B(n3049), .Y(n2067) );
NAND2X1TS U2113 ( .A(enab_cont_iter), .B(n2068), .Y(n1268) );
NAND2X1TS U2114 ( .A(n2781), .B(n1268), .Y(FPSENCOS_enab_d_ff5_data_out) );
NOR4X1TS U2115 ( .A(Data_2[15]), .B(Data_2[19]), .C(Data_2[13]), .D(
Data_2[21]), .Y(n1143) );
NOR4X1TS U2116 ( .A(Data_2[4]), .B(Data_2[18]), .C(Data_2[20]), .D(Data_2[1]), .Y(n1142) );
NOR4X1TS U2117 ( .A(Data_2[3]), .B(Data_2[5]), .C(Data_2[22]), .D(Data_2[0]),
.Y(n1141) );
NAND3XLTS U2118 ( .A(n1143), .B(n1142), .C(n1141), .Y(n1144) );
INVX2TS U2119 ( .A(n3047), .Y(n865) );
NOR3X2TS U2120 ( .A(n3119), .B(n943), .C(FPSENCOS_cont_iter_out[2]), .Y(
n3048) );
NOR2BX1TS U2121 ( .AN(n864), .B(n3048), .Y(n862) );
AO22XLTS U2122 ( .A0(n3049), .A1(n865), .B0(n3062), .B1(n862), .Y(n854) );
CLKBUFX3TS U2123 ( .A(n2614), .Y(n2837) );
CLKBUFX3TS U2124 ( .A(n2837), .Y(n3037) );
CLKBUFX3TS U2125 ( .A(n2835), .Y(n2546) );
NAND2X1TS U2126 ( .A(FPSENCOS_cont_var_out[0]), .B(FPSENCOS_cont_var_out[1]),
.Y(n3044) );
CLKBUFX3TS U2127 ( .A(n1146), .Y(n2545) );
AOI22X1TS U2128 ( .A0(n2546), .A1(FPSENCOS_d_ff3_sh_y_out[10]), .B0(n2545),
.B1(FPSENCOS_d_ff3_LUT_out[10]), .Y(n1148) );
AND3X2TS U2129 ( .A(FPSENCOS_cont_var_out[1]), .B(n3082), .C(n1016), .Y(
n2615) );
CLKBUFX2TS U2130 ( .A(n2615), .Y(n2609) );
CLKBUFX3TS U2131 ( .A(n2837), .Y(n2550) );
AOI22X1TS U2132 ( .A0(FPSENCOS_d_ff3_sh_x_out[10]), .A1(n2609), .B0(
Data_2[10]), .B1(n2550), .Y(n1147) );
NAND2X1TS U2133 ( .A(n1148), .B(n1147), .Y(add_subt_data2[10]) );
AOI22X1TS U2134 ( .A0(n943), .A1(n3062), .B0(FPSENCOS_cont_iter_out[2]),
.B1(n3080), .Y(n1149) );
OAI21XLTS U2135 ( .A0(n3047), .A1(n3056), .B0(n1149), .Y(n863) );
CLKBUFX3TS U2136 ( .A(n2512), .Y(n2613) );
CLKBUFX3TS U2137 ( .A(n1146), .Y(n2608) );
AOI22X1TS U2138 ( .A0(n2613), .A1(FPSENCOS_d_ff3_sh_y_out[0]), .B0(n2608),
.B1(FPSENCOS_d_ff3_LUT_out[0]), .Y(n1151) );
CLKBUFX3TS U2139 ( .A(n2615), .Y(n2633) );
AOI22X1TS U2140 ( .A0(FPSENCOS_d_ff3_sh_x_out[0]), .A1(n2633), .B0(Data_2[0]), .B1(n2550), .Y(n1150) );
NAND2X1TS U2141 ( .A(n1151), .B(n1150), .Y(add_subt_data2[0]) );
AOI22X1TS U2142 ( .A0(n976), .A1(FPMULT_Add_result[2]), .B0(n979), .B1(
FPMULT_P_Sgf[25]), .Y(n1154) );
AOI211X4TS U2143 ( .A0(n923), .A1(n3063), .B0(FPMULT_FSM_selector_C), .C0(
n1152), .Y(n1843) );
AOI22X1TS U2144 ( .A0(n1843), .A1(FPMULT_P_Sgf[24]), .B0(n998), .B1(
FPMULT_Add_result[1]), .Y(n1153) );
NAND2X1TS U2145 ( .A(n1154), .B(n1153), .Y(n3505) );
AOI22X1TS U2146 ( .A0(n976), .A1(FPMULT_Add_result[6]), .B0(n979), .B1(
FPMULT_P_Sgf[29]), .Y(n1156) );
AOI22X1TS U2147 ( .A0(n1843), .A1(FPMULT_P_Sgf[28]), .B0(n999), .B1(
FPMULT_Add_result[5]), .Y(n1155) );
NAND2X1TS U2148 ( .A(n1156), .B(n1155), .Y(n3509) );
AOI22X1TS U2149 ( .A0(n976), .A1(FPMULT_Add_result[4]), .B0(n979), .B1(
FPMULT_P_Sgf[27]), .Y(n1158) );
AOI22X1TS U2150 ( .A0(n1843), .A1(FPMULT_P_Sgf[26]), .B0(n998), .B1(
FPMULT_Add_result[3]), .Y(n1157) );
NAND2X1TS U2151 ( .A(n1158), .B(n1157), .Y(n3507) );
AOI22X1TS U2152 ( .A0(FPMULT_P_Sgf[45]), .A1(n979), .B0(
FPMULT_Add_result[22]), .B1(n978), .Y(n1160) );
AOI22X1TS U2153 ( .A0(n1843), .A1(FPMULT_P_Sgf[44]), .B0(n999), .B1(
FPMULT_Add_result[21]), .Y(n1159) );
NAND2X1TS U2154 ( .A(n1160), .B(n1159), .Y(n3525) );
AOI22X1TS U2155 ( .A0(n976), .A1(FPMULT_Add_result[20]), .B0(n979), .B1(
FPMULT_P_Sgf[43]), .Y(n1162) );
AOI22X1TS U2156 ( .A0(n1843), .A1(FPMULT_P_Sgf[42]), .B0(n998), .B1(
FPMULT_Add_result[19]), .Y(n1161) );
NAND2X1TS U2157 ( .A(n1162), .B(n1161), .Y(n3523) );
AOI22X1TS U2158 ( .A0(n976), .A1(FPMULT_Add_result[18]), .B0(n979), .B1(
FPMULT_P_Sgf[41]), .Y(n1164) );
AOI22X1TS U2159 ( .A0(n1843), .A1(FPMULT_P_Sgf[40]), .B0(n999), .B1(
FPMULT_Add_result[17]), .Y(n1163) );
NAND2X1TS U2160 ( .A(n1164), .B(n1163), .Y(n3521) );
AOI22X1TS U2161 ( .A0(n976), .A1(FPMULT_Add_result[16]), .B0(n980), .B1(
FPMULT_P_Sgf[39]), .Y(n1166) );
AOI22X1TS U2162 ( .A0(n1843), .A1(FPMULT_P_Sgf[38]), .B0(n997), .B1(
FPMULT_Add_result[15]), .Y(n1165) );
NAND2X1TS U2163 ( .A(n1166), .B(n1165), .Y(n3519) );
AOI22X1TS U2164 ( .A0(n976), .A1(FPMULT_Add_result[14]), .B0(n981), .B1(
FPMULT_P_Sgf[37]), .Y(n1168) );
AOI22X1TS U2165 ( .A0(n1083), .A1(FPMULT_P_Sgf[36]), .B0(n997), .B1(
FPMULT_Add_result[13]), .Y(n1167) );
NAND2X1TS U2166 ( .A(n1168), .B(n1167), .Y(n3517) );
AOI22X1TS U2167 ( .A0(n977), .A1(FPMULT_Add_result[12]), .B0(n980), .B1(
FPMULT_P_Sgf[35]), .Y(n1170) );
AOI22X1TS U2168 ( .A0(n1082), .A1(FPMULT_P_Sgf[34]), .B0(n997), .B1(
FPMULT_Add_result[11]), .Y(n1169) );
NAND2X1TS U2169 ( .A(n1170), .B(n1169), .Y(n3515) );
AOI22X1TS U2170 ( .A0(n978), .A1(FPMULT_Add_result[10]), .B0(n981), .B1(
FPMULT_P_Sgf[33]), .Y(n1172) );
AOI22X1TS U2171 ( .A0(n1083), .A1(FPMULT_P_Sgf[32]), .B0(n997), .B1(
FPMULT_Add_result[9]), .Y(n1171) );
NAND2X1TS U2172 ( .A(n1172), .B(n1171), .Y(n3513) );
AOI22X1TS U2173 ( .A0(n977), .A1(FPMULT_Add_result[8]), .B0(n980), .B1(
FPMULT_P_Sgf[31]), .Y(n1174) );
AOI22X1TS U2174 ( .A0(n1082), .A1(FPMULT_P_Sgf[30]), .B0(n997), .B1(
FPMULT_Add_result[7]), .Y(n1173) );
NAND2X1TS U2175 ( .A(n1174), .B(n1173), .Y(n3511) );
CLKBUFX3TS U2176 ( .A(n2609), .Y(n2549) );
AOI22X1TS U2177 ( .A0(n2549), .A1(FPSENCOS_d_ff2_Y[28]), .B0(n2608), .B1(
FPSENCOS_d_ff2_Z[28]), .Y(n1176) );
CLKBUFX3TS U2178 ( .A(n2512), .Y(n2567) );
AOI22X1TS U2179 ( .A0(FPSENCOS_d_ff2_X[28]), .A1(n2567), .B0(Data_1[28]),
.B1(n3037), .Y(n1175) );
NAND2X1TS U2180 ( .A(n1176), .B(n1175), .Y(add_subt_data1[28]) );
INVX2TS U2181 ( .A(Data_2[20]), .Y(n1178) );
CLKBUFX3TS U2182 ( .A(n2615), .Y(n2542) );
CLKBUFX3TS U2183 ( .A(n2515), .Y(n1234) );
AOI22X1TS U2184 ( .A0(n2542), .A1(FPSENCOS_d_ff3_sh_x_out[20]), .B0(n1234),
.B1(FPSENCOS_d_ff3_sh_y_out[20]), .Y(n1177) );
NAND2X1TS U2185 ( .A(n2545), .B(FPSENCOS_d_ff3_LUT_out[15]), .Y(n1210) );
OAI211XLTS U2186 ( .A0(n1016), .A1(n1178), .B0(n1177), .C0(n1210), .Y(
add_subt_data2[20]) );
INVX2TS U2187 ( .A(Data_2[27]), .Y(n1180) );
CLKBUFX3TS U2188 ( .A(n2615), .Y(n2560) );
AOI22X1TS U2189 ( .A0(n2560), .A1(FPSENCOS_d_ff3_sh_x_out[27]), .B0(n2835),
.B1(FPSENCOS_d_ff3_sh_y_out[27]), .Y(n1179) );
NAND2X1TS U2190 ( .A(n2545), .B(FPSENCOS_d_ff3_LUT_out[27]), .Y(n1265) );
OAI211XLTS U2191 ( .A0(n1016), .A1(n1180), .B0(n1179), .C0(n1265), .Y(
add_subt_data2[27]) );
INVX2TS U2192 ( .A(Data_2[16]), .Y(n1182) );
AOI22X1TS U2193 ( .A0(n2549), .A1(FPSENCOS_d_ff3_sh_x_out[16]), .B0(n1234),
.B1(FPSENCOS_d_ff3_sh_y_out[16]), .Y(n1181) );
NAND2X1TS U2194 ( .A(n1146), .B(FPSENCOS_d_ff3_LUT_out[3]), .Y(n1199) );
OAI211XLTS U2195 ( .A0(n1016), .A1(n1182), .B0(n1181), .C0(n1199), .Y(
add_subt_data2[16]) );
AOI22X1TS U2196 ( .A0(n2546), .A1(FPSENCOS_d_ff3_sh_y_out[4]), .B0(n2545),
.B1(FPSENCOS_d_ff3_LUT_out[4]), .Y(n1184) );
AOI22X1TS U2197 ( .A0(FPSENCOS_d_ff3_sh_x_out[4]), .A1(n2615), .B0(Data_2[4]), .B1(n2550), .Y(n1183) );
NAND2X1TS U2198 ( .A(n1184), .B(n1183), .Y(add_subt_data2[4]) );
CLKBUFX3TS U2199 ( .A(n2615), .Y(n2566) );
AOI22X1TS U2200 ( .A0(n2566), .A1(FPSENCOS_d_ff2_Y[2]), .B0(n2512), .B1(
FPSENCOS_d_ff2_X[2]), .Y(n1186) );
CLKBUFX3TS U2201 ( .A(n1146), .Y(n2541) );
CLKBUFX3TS U2202 ( .A(n2614), .Y(n2557) );
AOI22X1TS U2203 ( .A0(FPSENCOS_d_ff2_Z[2]), .A1(n2541), .B0(Data_1[2]), .B1(
n2557), .Y(n1185) );
NAND2X1TS U2204 ( .A(n1186), .B(n1185), .Y(add_subt_data1[2]) );
AOI22X1TS U2205 ( .A0(n2560), .A1(FPSENCOS_d_ff3_sh_x_out[25]), .B0(n1234),
.B1(FPSENCOS_d_ff3_sh_y_out[25]), .Y(n1188) );
CLKBUFX3TS U2206 ( .A(n1146), .Y(n2634) );
AOI22X1TS U2207 ( .A0(FPSENCOS_d_ff3_LUT_out[25]), .A1(n2634), .B0(
Data_2[25]), .B1(n2557), .Y(n1187) );
NAND2X1TS U2208 ( .A(n1188), .B(n1187), .Y(add_subt_data2[25]) );
INVX2TS U2209 ( .A(Data_2[13]), .Y(n1190) );
AOI22X1TS U2210 ( .A0(n2542), .A1(FPSENCOS_d_ff3_sh_x_out[13]), .B0(n1234),
.B1(FPSENCOS_d_ff3_sh_y_out[13]), .Y(n1189) );
NAND2X1TS U2211 ( .A(n2545), .B(FPSENCOS_d_ff3_LUT_out[13]), .Y(n1235) );
OAI211XLTS U2212 ( .A0(n1016), .A1(n1190), .B0(n1189), .C0(n1235), .Y(
add_subt_data2[13]) );
INVX2TS U2213 ( .A(Data_2[22]), .Y(n1192) );
AOI22X1TS U2214 ( .A0(n2560), .A1(FPSENCOS_d_ff3_sh_x_out[22]), .B0(n1234),
.B1(FPSENCOS_d_ff3_sh_y_out[22]), .Y(n1191) );
NAND2X1TS U2215 ( .A(n2545), .B(FPSENCOS_d_ff3_LUT_out[19]), .Y(n1220) );
OAI211XLTS U2216 ( .A0(n1017), .A1(n1192), .B0(n1191), .C0(n1220), .Y(
add_subt_data2[22]) );
MXI2X1TS U2217 ( .A(r_mode[0]), .B(r_mode[1]), .S0(n3491), .Y(n1193) );
OAI211X1TS U2218 ( .A0(r_mode[0]), .A1(r_mode[1]), .B0(n3492), .C0(n1193),
.Y(n2520) );
NOR3X1TS U2219 ( .A(FPMULT_FS_Module_state_reg[1]), .B(n923), .C(n1661), .Y(
n2521) );
INVX2TS U2220 ( .A(n2521), .Y(n1194) );
OAI21XLTS U2221 ( .A0(n2520), .A1(n1194), .B0(n3122), .Y(n834) );
INVX2TS U2222 ( .A(Data_2[14]), .Y(n1196) );
AOI22X1TS U2223 ( .A0(n2542), .A1(FPSENCOS_d_ff3_sh_x_out[14]), .B0(n1234),
.B1(FPSENCOS_d_ff3_sh_y_out[14]), .Y(n1195) );
NAND2X1TS U2224 ( .A(n1146), .B(FPSENCOS_d_ff3_LUT_out[5]), .Y(n1215) );
OAI211XLTS U2225 ( .A0(operation[1]), .A1(n1196), .B0(n1195), .C0(n1215),
.Y(add_subt_data2[14]) );
AOI22X1TS U2226 ( .A0(n2546), .A1(FPSENCOS_d_ff3_sh_y_out[9]), .B0(n2545),
.B1(FPSENCOS_d_ff3_LUT_out[9]), .Y(n1198) );
CLKBUFX2TS U2227 ( .A(n2609), .Y(n2836) );
AOI22X1TS U2228 ( .A0(FPSENCOS_d_ff3_sh_x_out[9]), .A1(n2836), .B0(Data_2[9]), .B1(n2550), .Y(n1197) );
NAND2X1TS U2229 ( .A(n1198), .B(n1197), .Y(add_subt_data2[9]) );
INVX2TS U2230 ( .A(Data_2[3]), .Y(n1201) );
AOI22X1TS U2231 ( .A0(n2549), .A1(FPSENCOS_d_ff3_sh_x_out[3]), .B0(n2512),
.B1(FPSENCOS_d_ff3_sh_y_out[3]), .Y(n1200) );
OAI211XLTS U2232 ( .A0(n1017), .A1(n1201), .B0(n1200), .C0(n1199), .Y(
add_subt_data2[3]) );
INVX2TS U2233 ( .A(Data_2[11]), .Y(n1203) );
AOI22X1TS U2234 ( .A0(n2542), .A1(FPSENCOS_d_ff3_sh_x_out[11]), .B0(n2515),
.B1(FPSENCOS_d_ff3_sh_y_out[11]), .Y(n1202) );
NAND2X1TS U2235 ( .A(n1146), .B(FPSENCOS_d_ff3_LUT_out[7]), .Y(n1240) );
OAI211XLTS U2236 ( .A0(operation[1]), .A1(n1203), .B0(n1202), .C0(n1240),
.Y(add_subt_data2[11]) );
INVX2TS U2237 ( .A(Data_2[15]), .Y(n1205) );
AOI22X1TS U2238 ( .A0(n2542), .A1(FPSENCOS_d_ff3_sh_x_out[15]), .B0(n1234),
.B1(FPSENCOS_d_ff3_sh_y_out[15]), .Y(n1204) );
OAI211XLTS U2239 ( .A0(n1017), .A1(n1205), .B0(n1204), .C0(n1210), .Y(
add_subt_data2[15]) );
AOI22X1TS U2240 ( .A0(n2566), .A1(FPSENCOS_d_ff2_Y[21]), .B0(n1145), .B1(
FPSENCOS_d_ff2_X[21]), .Y(n1207) );
AOI22X1TS U2241 ( .A0(FPSENCOS_d_ff2_Z[21]), .A1(n2634), .B0(Data_1[21]),
.B1(n2614), .Y(n1206) );
NAND2X1TS U2242 ( .A(n1207), .B(n1206), .Y(add_subt_data1[21]) );
AOI22X1TS U2243 ( .A0(n2633), .A1(FPSENCOS_d_ff2_Y[13]), .B0(n2515), .B1(
FPSENCOS_d_ff2_X[13]), .Y(n1209) );
AOI22X1TS U2244 ( .A0(FPSENCOS_d_ff2_Z[13]), .A1(n2541), .B0(Data_1[13]),
.B1(n2614), .Y(n1208) );
NAND2X1TS U2245 ( .A(n1209), .B(n1208), .Y(add_subt_data1[13]) );
INVX2TS U2246 ( .A(Data_2[17]), .Y(n1212) );
AOI22X1TS U2247 ( .A0(n2542), .A1(FPSENCOS_d_ff3_sh_x_out[17]), .B0(n1234),
.B1(FPSENCOS_d_ff3_sh_y_out[17]), .Y(n1211) );
OAI211XLTS U2248 ( .A0(operation[1]), .A1(n1212), .B0(n1211), .C0(n1210),
.Y(add_subt_data2[17]) );
AOI22X1TS U2249 ( .A0(n2566), .A1(FPSENCOS_d_ff2_Y[16]), .B0(n2512), .B1(
FPSENCOS_d_ff2_X[16]), .Y(n1214) );
CLKBUFX3TS U2250 ( .A(n2614), .Y(n2563) );
AOI22X1TS U2251 ( .A0(FPSENCOS_d_ff2_Z[16]), .A1(n2541), .B0(Data_1[16]),
.B1(n2563), .Y(n1213) );
NAND2X1TS U2252 ( .A(n1214), .B(n1213), .Y(add_subt_data1[16]) );
NAND2X1TS U2253 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B(n3081),
.Y(n1457) );
INVX2TS U2254 ( .A(Data_2[5]), .Y(n1217) );
AOI22X1TS U2255 ( .A0(n2549), .A1(FPSENCOS_d_ff3_sh_x_out[5]), .B0(n2835),
.B1(FPSENCOS_d_ff3_sh_y_out[5]), .Y(n1216) );
OAI211XLTS U2256 ( .A0(n1017), .A1(n1217), .B0(n1216), .C0(n1215), .Y(
add_subt_data2[5]) );
AOI22X1TS U2257 ( .A0(n2542), .A1(FPSENCOS_d_ff3_sh_x_out[24]), .B0(n1234),
.B1(FPSENCOS_d_ff3_sh_y_out[24]), .Y(n1219) );
AOI22X1TS U2258 ( .A0(FPSENCOS_d_ff3_LUT_out[24]), .A1(n2634), .B0(
Data_2[24]), .B1(n2557), .Y(n1218) );
NAND2X1TS U2259 ( .A(n1219), .B(n1218), .Y(add_subt_data2[24]) );
INVX2TS U2260 ( .A(Data_2[19]), .Y(n1222) );
AOI22X1TS U2261 ( .A0(n2542), .A1(FPSENCOS_d_ff3_sh_x_out[19]), .B0(n2515),
.B1(FPSENCOS_d_ff3_sh_y_out[19]), .Y(n1221) );
OAI211XLTS U2262 ( .A0(operation[1]), .A1(n1222), .B0(n1221), .C0(n1220),
.Y(add_subt_data2[19]) );
AOI22X1TS U2263 ( .A0(n978), .A1(FPMULT_Add_result[1]), .B0(n981), .B1(
FPMULT_P_Sgf[24]), .Y(n1224) );
AOI22X1TS U2264 ( .A0(n1083), .A1(FPMULT_P_Sgf[23]), .B0(n997), .B1(
FPMULT_Add_result[0]), .Y(n1223) );
NAND2X1TS U2265 ( .A(n1224), .B(n1223), .Y(n3504) );
AOI22X1TS U2266 ( .A0(n2546), .A1(FPSENCOS_d_ff3_sh_y_out[8]), .B0(n2545),
.B1(FPSENCOS_d_ff3_LUT_out[8]), .Y(n1226) );
AOI22X1TS U2267 ( .A0(FPSENCOS_d_ff3_sh_x_out[8]), .A1(n2836), .B0(Data_2[8]), .B1(n2550), .Y(n1225) );
NAND2X1TS U2268 ( .A(n1226), .B(n1225), .Y(add_subt_data2[8]) );
OR4X2TS U2269 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[7]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[6]), .C(FPADDSUB_exp_rslt_NRM2_EW1[5]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[4]), .Y(n1228) );
OR4X2TS U2270 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[1]), .C(FPADDSUB_exp_rslt_NRM2_EW1[0]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .Y(n1227) );
OR2X1TS U2271 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[0]), .B(n3495), .Y(
FPADDSUB_formatted_number_W[23]) );
OR2X1TS U2272 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[1]), .B(n3495), .Y(
FPADDSUB_formatted_number_W[24]) );
OR2X1TS U2273 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[2]), .B(n3495), .Y(
FPADDSUB_formatted_number_W[25]) );
OR2X1TS U2274 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(n3495), .Y(
FPADDSUB_formatted_number_W[26]) );
OR2X1TS U2275 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[4]), .B(n3495), .Y(
FPADDSUB_formatted_number_W[27]) );
OR2X1TS U2276 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(n3495), .Y(
FPADDSUB_formatted_number_W[29]) );
NAND4XLTS U2277 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[7]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[6]), .C(FPADDSUB_exp_rslt_NRM2_EW1[5]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[4]), .Y(n1230) );
NAND4XLTS U2278 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[1]), .C(FPADDSUB_exp_rslt_NRM2_EW1[0]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .Y(n1229) );
AOI22X1TS U2279 ( .A0(n2549), .A1(FPSENCOS_d_ff2_Y[30]), .B0(n2541), .B1(
FPSENCOS_d_ff2_Z[30]), .Y(n1233) );
AOI22X1TS U2280 ( .A0(FPSENCOS_d_ff2_X[30]), .A1(n2567), .B0(Data_1[30]),
.B1(n3037), .Y(n1232) );
NAND2X1TS U2281 ( .A(n1233), .B(n1232), .Y(add_subt_data1[30]) );
INVX2TS U2282 ( .A(Data_2[18]), .Y(n1237) );
AOI22X1TS U2283 ( .A0(n2542), .A1(FPSENCOS_d_ff3_sh_x_out[18]), .B0(n1234),
.B1(FPSENCOS_d_ff3_sh_y_out[18]), .Y(n1236) );
OAI211XLTS U2284 ( .A0(n1017), .A1(n1237), .B0(n1236), .C0(n1235), .Y(
add_subt_data2[18]) );
AOI22X1TS U2285 ( .A0(n2566), .A1(FPSENCOS_d_ff2_Y[9]), .B0(n2515), .B1(
FPSENCOS_d_ff2_X[9]), .Y(n1239) );
AOI22X1TS U2286 ( .A0(FPSENCOS_d_ff2_Z[9]), .A1(n2541), .B0(Data_1[9]), .B1(
n2614), .Y(n1238) );
NAND2X1TS U2287 ( .A(n1239), .B(n1238), .Y(add_subt_data1[9]) );
INVX2TS U2288 ( .A(Data_2[7]), .Y(n1242) );
AOI22X1TS U2289 ( .A0(n2549), .A1(FPSENCOS_d_ff3_sh_x_out[7]), .B0(n2512),
.B1(FPSENCOS_d_ff3_sh_y_out[7]), .Y(n1241) );
OAI211XLTS U2290 ( .A0(operation[1]), .A1(n1242), .B0(n1241), .C0(n1240),
.Y(add_subt_data2[7]) );
AOI22X1TS U2291 ( .A0(n977), .A1(FPMULT_Add_result[3]), .B0(n980), .B1(
FPMULT_P_Sgf[26]), .Y(n1244) );
AOI22X1TS U2292 ( .A0(n1082), .A1(FPMULT_P_Sgf[25]), .B0(n997), .B1(
FPMULT_Add_result[2]), .Y(n1243) );
NAND2X1TS U2293 ( .A(n1244), .B(n1243), .Y(n3506) );
AOI22X1TS U2294 ( .A0(n978), .A1(FPMULT_Add_result[5]), .B0(n981), .B1(
FPMULT_P_Sgf[28]), .Y(n1246) );
AOI22X1TS U2295 ( .A0(n1083), .A1(FPMULT_P_Sgf[27]), .B0(n998), .B1(
FPMULT_Add_result[4]), .Y(n1245) );
NAND2X1TS U2296 ( .A(n1246), .B(n1245), .Y(n3508) );
AOI22X1TS U2297 ( .A0(FPMULT_P_Sgf[44]), .A1(n979), .B0(
FPMULT_Add_result[21]), .B1(n977), .Y(n1248) );
AOI22X1TS U2298 ( .A0(n1082), .A1(FPMULT_P_Sgf[43]), .B0(n999), .B1(
FPMULT_Add_result[20]), .Y(n1247) );
NAND2X1TS U2299 ( .A(n1248), .B(n1247), .Y(n3524) );
AOI22X1TS U2300 ( .A0(n977), .A1(FPMULT_Add_result[19]), .B0(n980), .B1(
FPMULT_P_Sgf[42]), .Y(n1250) );
AOI22X1TS U2301 ( .A0(n1083), .A1(FPMULT_P_Sgf[41]), .B0(n998), .B1(
FPMULT_Add_result[18]), .Y(n1249) );
NAND2X1TS U2302 ( .A(n1250), .B(n1249), .Y(n3522) );
AOI22X1TS U2303 ( .A0(n978), .A1(FPMULT_Add_result[17]), .B0(n981), .B1(
FPMULT_P_Sgf[40]), .Y(n1252) );
AOI22X1TS U2304 ( .A0(n1082), .A1(FPMULT_P_Sgf[39]), .B0(n999), .B1(
FPMULT_Add_result[16]), .Y(n1251) );
NAND2X1TS U2305 ( .A(n1252), .B(n1251), .Y(n3520) );
AOI22X1TS U2306 ( .A0(n977), .A1(FPMULT_Add_result[15]), .B0(n980), .B1(
FPMULT_P_Sgf[38]), .Y(n1254) );
AOI22X1TS U2307 ( .A0(n1083), .A1(FPMULT_P_Sgf[37]), .B0(n998), .B1(
FPMULT_Add_result[14]), .Y(n1253) );
NAND2X1TS U2308 ( .A(n1254), .B(n1253), .Y(n3518) );
AOI22X1TS U2309 ( .A0(n978), .A1(FPMULT_Add_result[13]), .B0(n981), .B1(
FPMULT_P_Sgf[36]), .Y(n1256) );
AOI22X1TS U2310 ( .A0(n1082), .A1(FPMULT_P_Sgf[35]), .B0(n999), .B1(
FPMULT_Add_result[12]), .Y(n1255) );
NAND2X1TS U2311 ( .A(n1256), .B(n1255), .Y(n3516) );
AOI22X1TS U2312 ( .A0(n977), .A1(FPMULT_Add_result[11]), .B0(n980), .B1(
FPMULT_P_Sgf[34]), .Y(n1258) );
AOI22X1TS U2313 ( .A0(n1083), .A1(FPMULT_P_Sgf[33]), .B0(n998), .B1(
FPMULT_Add_result[10]), .Y(n1257) );
NAND2X1TS U2314 ( .A(n1258), .B(n1257), .Y(n3514) );
AOI22X1TS U2315 ( .A0(n978), .A1(FPMULT_Add_result[9]), .B0(n981), .B1(
FPMULT_P_Sgf[32]), .Y(n1260) );
AOI22X1TS U2316 ( .A0(n1082), .A1(FPMULT_P_Sgf[31]), .B0(n999), .B1(
FPMULT_Add_result[8]), .Y(n1259) );
NAND2X1TS U2317 ( .A(n1260), .B(n1259), .Y(n3512) );
AOI22X1TS U2318 ( .A0(n977), .A1(FPMULT_Add_result[7]), .B0(n980), .B1(
FPMULT_P_Sgf[30]), .Y(n1262) );
AOI22X1TS U2319 ( .A0(n1083), .A1(FPMULT_P_Sgf[29]), .B0(n998), .B1(
FPMULT_Add_result[6]), .Y(n1261) );
NAND2X1TS U2320 ( .A(n1262), .B(n1261), .Y(n3510) );
INVX2TS U2321 ( .A(Data_2[28]), .Y(n1264) );
AOI22X1TS U2322 ( .A0(n2560), .A1(FPSENCOS_d_ff3_sh_x_out[28]), .B0(n2512),
.B1(FPSENCOS_d_ff3_sh_y_out[28]), .Y(n1263) );
OAI211XLTS U2323 ( .A0(n1017), .A1(n1264), .B0(n1263), .C0(n1265), .Y(
add_subt_data2[28]) );
INVX2TS U2324 ( .A(Data_2[29]), .Y(n1267) );
AOI22X1TS U2325 ( .A0(n2560), .A1(FPSENCOS_d_ff3_sh_x_out[29]), .B0(n2835),
.B1(FPSENCOS_d_ff3_sh_y_out[29]), .Y(n1266) );
OAI211XLTS U2326 ( .A0(operation[1]), .A1(n1267), .B0(n1266), .C0(n1265),
.Y(add_subt_data2[29]) );
AO21XLTS U2327 ( .A0(n1017), .A1(ack_operation), .B0(n2781), .Y(n3039) );
NAND2X1TS U2328 ( .A(n3039), .B(n1268), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]) );
NAND2X1TS U2329 ( .A(n1459), .B(n3124), .Y(n2784) );
NOR2XLTS U2330 ( .A(FPMULT_FSM_selector_B[1]), .B(FPMULT_Op_MY[23]), .Y(
n1269) );
NAND2X2TS U2331 ( .A(FPMULT_FSM_selector_B[0]), .B(n3117), .Y(n1276) );
OAI21XLTS U2332 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n1269), .B0(n1276), .Y(
n1270) );
XOR2X1TS U2333 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n1270), .Y(
DP_OP_230J196_125_7006_n22) );
OAI2BB1X1TS U2334 ( .A0N(FPMULT_Op_MY[24]), .A1N(n3117), .B0(n1276), .Y(
n1271) );
XOR2X1TS U2335 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n1271), .Y(
DP_OP_230J196_125_7006_n21) );
OAI2BB1X1TS U2336 ( .A0N(FPMULT_Op_MY[25]), .A1N(n3117), .B0(n1276), .Y(
n1272) );
XOR2X1TS U2337 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n1272), .Y(
DP_OP_230J196_125_7006_n20) );
OAI2BB1X1TS U2338 ( .A0N(FPMULT_Op_MY[26]), .A1N(n3117), .B0(n1276), .Y(
n1273) );
XOR2X1TS U2339 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n1273), .Y(
DP_OP_230J196_125_7006_n19) );
OAI2BB1X1TS U2340 ( .A0N(FPMULT_Op_MY[27]), .A1N(n3117), .B0(n1276), .Y(
n1274) );
XOR2X1TS U2341 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n1274), .Y(
DP_OP_230J196_125_7006_n18) );
OAI2BB1X1TS U2342 ( .A0N(FPMULT_Op_MY[28]), .A1N(n3117), .B0(n1276), .Y(
n1275) );
XOR2X1TS U2343 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n1275), .Y(
DP_OP_230J196_125_7006_n17) );
OAI2BB1X1TS U2344 ( .A0N(FPMULT_Op_MY[29]), .A1N(n3117), .B0(n1276), .Y(
n1277) );
XOR2X1TS U2345 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n1277), .Y(
DP_OP_230J196_125_7006_n16) );
NOR3BX1TS U2346 ( .AN(FPMULT_Op_MY[30]), .B(FPMULT_FSM_selector_B[0]), .C(
FPMULT_FSM_selector_B[1]), .Y(n1278) );
XOR2X1TS U2347 ( .A(FPMULT_FSM_exp_operation_A_S), .B(n1278), .Y(
DP_OP_230J196_125_7006_n15) );
AOI22X1TS U2348 ( .A0(FPMULT_FS_Module_state_reg[1]), .A1(n3033), .B0(n1459),
.B1(FPMULT_zero_flag), .Y(n1279) );
NAND2X1TS U2349 ( .A(n1279), .B(n1661), .Y(FPMULT_FS_Module_state_next[3])
);
OA21XLTS U2350 ( .A0(n1079), .A1(n3049), .B0(n2067), .Y(
FPSENCOS_ITER_CONT_N4) );
OAI2BB1X1TS U2351 ( .A0N(n1281), .A1N(n3067), .B0(n1280), .Y(n1284) );
OAI31X1TS U2352 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[4]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[0]), .A2(FPADDSUB_Raw_mant_NRM_SWR[1]), .B0(
n1282), .Y(n1283) );
NAND3BXLTS U2353 ( .AN(n1285), .B(n1284), .C(n1283), .Y(
FPADDSUB_LZD_raw_out_EWR[4]) );
NAND4X1TS U2354 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(n1287),
.C(n1286), .D(n3165), .Y(n3042) );
NOR3X1TS U2355 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n1288) );
NAND3XLTS U2356 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(n1287),
.C(n1288), .Y(n1860) );
NAND2X1TS U2357 ( .A(n3042), .B(n1860), .Y(FPSENCOS_enab_d_ff_RB1) );
NOR2XLTS U2358 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .Y(n1289) );
BUFX3TS U2359 ( .A(n912), .Y(n3468) );
CLKBUFX2TS U2360 ( .A(FPSENCOS_reg_shift_y_net5038830), .Y(n1292) );
CLKBUFX2TS U2361 ( .A(FPSENCOS_reg_val_muxZ_2stage_net5038830), .Y(n1293) );
OAI22X1TS U2362 ( .A0(n3104), .A1(n3151), .B0(FPMULT_Op_MX[22]), .B1(
FPMULT_Op_MX[21]), .Y(n2730) );
CLKBUFX3TS U2363 ( .A(n3226), .Y(n2722) );
OAI22X1TS U2364 ( .A0(n1060), .A1(n2722), .B0(n972), .B1(n2252), .Y(n1297)
);
CLKBUFX3TS U2365 ( .A(n3225), .Y(n2181) );
CLKBUFX3TS U2366 ( .A(n3228), .Y(n2770) );
CLKBUFX3TS U2367 ( .A(n3231), .Y(n2733) );
AOI21X1TS U2368 ( .A0(n1767), .A1(n2733), .B0(n3060), .Y(n1354) );
OAI21X1TS U2369 ( .A0(FPMULT_Op_MY[3]), .A1(n1347), .B0(FPMULT_Op_MY[4]),
.Y(n1337) );
NOR2X1TS U2370 ( .A(n1340), .B(n2770), .Y(n1294) );
AOI21X1TS U2371 ( .A0(n2770), .A1(n1337), .B0(n1294), .Y(n1460) );
AO21XLTS U2372 ( .A0(FPMULT_Op_MY[6]), .A1(n1460), .B0(n1294), .Y(n1482) );
INVX2TS U2373 ( .A(n1295), .Y(n2251) );
OAI22X1TS U2374 ( .A0(n1057), .A1(n2181), .B0(n2789), .B1(n2251), .Y(n1296)
);
NOR2X1TS U2375 ( .A(n1297), .B(n1296), .Y(mult_x_69_n608) );
CLKBUFX2TS U2376 ( .A(n3212), .Y(n1298) );
CLKBUFX3TS U2377 ( .A(n1298), .Y(n3362) );
INVX2TS U2378 ( .A(FPMULT_Op_MX[20]), .Y(n2710) );
CLKBUFX2TS U2379 ( .A(n2710), .Y(n2166) );
CLKBUFX3TS U2380 ( .A(n2166), .Y(n3361) );
NOR2X1TS U2381 ( .A(n2732), .B(n1767), .Y(mult_x_69_n381) );
CLKBUFX3TS U2382 ( .A(n3213), .Y(n3363) );
INVX2TS U2383 ( .A(n1383), .Y(n1384) );
CLKBUFX3TS U2384 ( .A(n1300), .Y(n1302) );
BUFX3TS U2385 ( .A(n1302), .Y(n3283) );
BUFX3TS U2386 ( .A(n1302), .Y(n3284) );
BUFX3TS U2387 ( .A(n1301), .Y(n3317) );
BUFX3TS U2388 ( .A(n1301), .Y(n3316) );
BUFX3TS U2389 ( .A(n1303), .Y(n3304) );
CLKBUFX3TS U2390 ( .A(n1300), .Y(n1304) );
BUFX3TS U2391 ( .A(n1304), .Y(n3308) );
BUFX3TS U2392 ( .A(n1304), .Y(n3310) );
BUFX3TS U2393 ( .A(n1301), .Y(n3292) );
BUFX3TS U2394 ( .A(n1301), .Y(n3315) );
BUFX3TS U2395 ( .A(n1301), .Y(n3299) );
BUFX3TS U2396 ( .A(n1303), .Y(n3297) );
BUFX3TS U2397 ( .A(n1301), .Y(n3314) );
BUFX3TS U2398 ( .A(n1303), .Y(n3303) );
BUFX3TS U2399 ( .A(n1302), .Y(n3279) );
BUFX3TS U2400 ( .A(n1304), .Y(n3311) );
BUFX3TS U2401 ( .A(n1303), .Y(n3302) );
BUFX3TS U2402 ( .A(n1302), .Y(n3294) );
BUFX3TS U2403 ( .A(n1302), .Y(n3301) );
BUFX3TS U2404 ( .A(n1304), .Y(n3289) );
BUFX3TS U2405 ( .A(n1302), .Y(n3280) );
BUFX3TS U2406 ( .A(n1302), .Y(n3282) );
BUFX3TS U2407 ( .A(n1304), .Y(n3293) );
BUFX3TS U2408 ( .A(n1304), .Y(n3287) );
BUFX3TS U2409 ( .A(n1303), .Y(n3306) );
BUFX3TS U2410 ( .A(n1302), .Y(n3285) );
BUFX3TS U2411 ( .A(n1304), .Y(n3309) );
BUFX3TS U2412 ( .A(n1303), .Y(n3286) );
BUFX3TS U2413 ( .A(n1301), .Y(n3288) );
BUFX3TS U2414 ( .A(n1302), .Y(n3281) );
BUFX3TS U2415 ( .A(n1304), .Y(n3313) );
BUFX3TS U2416 ( .A(n1303), .Y(n3305) );
BUFX3TS U2417 ( .A(n1303), .Y(n3307) );
BUFX3TS U2418 ( .A(n1304), .Y(n3312) );
INVX2TS U2419 ( .A(n972), .Y(n2775) );
CLKBUFX3TS U2420 ( .A(n3221), .Y(n2690) );
NOR2XLTS U2421 ( .A(n2690), .B(n1060), .Y(n1311) );
CLKBUFX3TS U2422 ( .A(n910), .Y(n2191) );
CMPR32X2TS U2423 ( .A(FPMULT_Op_MY[7]), .B(FPMULT_Op_MY[8]), .C(n1305), .CO(
n1477), .S(n1295) );
OAI2BB1X1TS U2424 ( .A0N(FPMULT_Op_MY[9]), .A1N(n1466), .B0(n2751), .Y(n1329) );
NAND2X1TS U2425 ( .A(FPMULT_Op_MY[11]), .B(n1329), .Y(n1307) );
OAI21X1TS U2426 ( .A0(FPMULT_Op_MY[9]), .A1(n1466), .B0(FPMULT_Op_MY[10]),
.Y(n1330) );
INVX2TS U2427 ( .A(n1307), .Y(n1306) );
AOI21X1TS U2428 ( .A0(n2714), .A1(n1330), .B0(n1306), .Y(n1759) );
NAND2X1TS U2429 ( .A(FPMULT_Op_MY[12]), .B(n1759), .Y(n1758) );
NAND2X1TS U2430 ( .A(n1307), .B(n1758), .Y(n1611) );
AOI32X1TS U2431 ( .A0(FPMULT_Op_MY[12]), .A1(FPMULT_Op_MY[14]), .A2(n1611),
.B0(FPMULT_Op_MY[13]), .B1(FPMULT_Op_MY[14]), .Y(n1308) );
INVX2TS U2432 ( .A(n1308), .Y(n1491) );
OAI21XLTS U2433 ( .A0(n1312), .A1(n1313), .B0(n2191), .Y(n1309) );
OAI31X4TS U2434 ( .A0(n1312), .A1(n2191), .A2(n1313), .B0(n1309), .Y(n2699)
);
OAI22X1TS U2435 ( .A0(n2191), .A1(n1056), .B0(n2699), .B1(n1104), .Y(n1310)
);
AOI211X1TS U2436 ( .A0(n2775), .A1(FPMULT_Op_MY[15]), .B0(n1311), .C0(n1310),
.Y(mult_x_69_n599) );
XOR2X1TS U2437 ( .A(FPMULT_Op_MX[15]), .B(FPMULT_Op_MX[16]), .Y(n1336) );
CLKBUFX3TS U2438 ( .A(n1045), .Y(n2199) );
CLKBUFX3TS U2439 ( .A(n1045), .Y(n2261) );
NOR2X1TS U2440 ( .A(n1312), .B(n2191), .Y(n1314) );
AOI2BB1X1TS U2441 ( .A0N(FPMULT_Op_MY[17]), .A1N(n1313), .B0(n1314), .Y(
n1321) );
AO21XLTS U2442 ( .A0(FPMULT_Op_MY[18]), .A1(n1321), .B0(n1314), .Y(n1629) );
INVX2TS U2443 ( .A(n944), .Y(n1815) );
NOR2X1TS U2444 ( .A(n1037), .B(n1039), .Y(n1335) );
OAI2BB2X1TS U2445 ( .B0(n1011), .B1(n1815), .A0N(n1335), .A1N(n954), .Y(
n1316) );
CLKBUFX3TS U2446 ( .A(n1045), .Y(n2258) );
OAI21XLTS U2447 ( .A0(n2256), .A1(n1316), .B0(n2258), .Y(n1315) );
OAI31X1TS U2448 ( .A0(n2256), .A1(n2199), .A2(n1316), .B0(n1315), .Y(
mult_x_69_n645) );
XNOR2X1TS U2449 ( .A(FPMULT_Op_MX[18]), .B(FPMULT_Op_MX[19]), .Y(n1319) );
NOR2X2TS U2450 ( .A(n1319), .B(n1041), .Y(n1710) );
NAND2X2TS U2451 ( .A(n1041), .B(n1030), .Y(n2313) );
INVX2TS U2452 ( .A(n2313), .Y(n1709) );
INVX2TS U2453 ( .A(n1709), .Y(n2216) );
CLKAND2X2TS U2454 ( .A(n1030), .B(n1042), .Y(n1320) );
OAI2BB2X1TS U2455 ( .B0(n2705), .B1(n1815), .A0N(n1320), .A1N(n954), .Y(
n1318) );
OAI21XLTS U2456 ( .A0(n1710), .A1(n1318), .B0(n2166), .Y(n1317) );
OAI31X1TS U2457 ( .A0(n1710), .A1(n3361), .A2(n1318), .B0(n1317), .Y(
mult_x_69_n618) );
OAI22X1TS U2458 ( .A0(n2690), .A1(n1088), .B0(n2244), .B1(n2216), .Y(n1325)
);
CLKBUFX3TS U2459 ( .A(n2166), .Y(n2327) );
CLKBUFX3TS U2460 ( .A(n910), .Y(n2471) );
NOR2X1TS U2461 ( .A(n1042), .B(n1030), .Y(n1361) );
OAI22X1TS U2462 ( .A0(n2471), .A1(n1086), .B0(n1040), .B1(n1022), .Y(n1324)
);
CLKBUFX3TS U2463 ( .A(n2166), .Y(n2324) );
OAI21XLTS U2464 ( .A0(n1325), .A1(n1324), .B0(n2324), .Y(n1323) );
OAI31X1TS U2465 ( .A0(n1325), .A1(n2327), .A2(n1324), .B0(n1323), .Y(
mult_x_69_n624) );
XOR2X1TS U2466 ( .A(FPMULT_Op_MX[3]), .B(FPMULT_Op_MX[4]), .Y(n1429) );
AOI2BB2X2TS U2467 ( .B0(n1817), .B1(FPMULT_Op_MX[3]), .A0N(FPMULT_Op_MX[3]),
.A1N(n1877), .Y(n1434) );
INVX2TS U2468 ( .A(n1434), .Y(n1787) );
CLKBUFX2TS U2469 ( .A(n3211), .Y(n1326) );
CLKBUFX3TS U2470 ( .A(n1326), .Y(n2475) );
CLKBUFX3TS U2471 ( .A(n1326), .Y(n2472) );
NOR2X1TS U2472 ( .A(n1434), .B(n1430), .Y(n1428) );
OAI2BB2X1TS U2473 ( .B0(n1014), .B1(n1815), .A0N(n1428), .A1N(n954), .Y(
n1328) );
OAI21XLTS U2474 ( .A0(n2470), .A1(n1328), .B0(n3211), .Y(n1327) );
OAI31X1TS U2475 ( .A0(n2470), .A1(n2475), .A2(n1328), .B0(n1327), .Y(
mult_x_69_n753) );
CLKBUFX2TS U2476 ( .A(n3218), .Y(n2744) );
INVX2TS U2477 ( .A(n1709), .Y(n2705) );
NAND2X1TS U2478 ( .A(n1330), .B(n1329), .Y(n1331) );
OAI22X1TS U2479 ( .A0(n2744), .A1(n1089), .B0(n2705), .B1(n2715), .Y(n1334)
);
CLKBUFX3TS U2480 ( .A(n3223), .Y(n2451) );
OAI22X1TS U2481 ( .A0(n2451), .A1(n1021), .B0(n3224), .B1(n1086), .Y(n1333)
);
OAI21XLTS U2482 ( .A0(n1334), .A1(n1333), .B0(n2324), .Y(n1332) );
OAI31X1TS U2483 ( .A0(n1334), .A1(n2327), .A2(n1333), .B0(n1332), .Y(
mult_x_69_n631) );
INVX2TS U2484 ( .A(n1337), .Y(n1339) );
OAI21XLTS U2485 ( .A0(n1340), .A1(n1339), .B0(n2770), .Y(n1338) );
OAI31X4TS U2486 ( .A0(n1340), .A1(n2770), .A2(n1339), .B0(n1338), .Y(n2761)
);
OAI22X1TS U2487 ( .A0(n2318), .A1(n3219), .B0(n1009), .B1(n2761), .Y(n1345)
);
CLKBUFX3TS U2488 ( .A(n3228), .Y(n2756) );
OAI22X1TS U2489 ( .A0(n1002), .A1(n2756), .B0(n992), .B1(n1048), .Y(n1344)
);
OAI21XLTS U2490 ( .A0(n1345), .A1(n1344), .B0(n1046), .Y(n1343) );
OAI31X1TS U2491 ( .A0(n1345), .A1(FPMULT_Op_MX[17]), .A2(n1344), .B0(n1343),
.Y(n2142) );
CLKBUFX3TS U2492 ( .A(n3231), .Y(n2737) );
CLKBUFX2TS U2493 ( .A(n3219), .Y(n2757) );
AOI22X1TS U2494 ( .A0(FPMULT_Op_MY[3]), .A1(FPMULT_Op_MY[4]), .B0(n920),
.B1(n2757), .Y(n1346) );
XNOR2X4TS U2495 ( .A(n1347), .B(n1346), .Y(n2727) );
OAI22X1TS U2496 ( .A0(n1095), .A1(n2737), .B0(n1009), .B1(n2727), .Y(n1350)
);
CLKBUFX3TS U2497 ( .A(n3219), .Y(n2706) );
OAI22X1TS U2498 ( .A0(n1001), .A1(n1047), .B0(n993), .B1(n2706), .Y(n1349)
);
OAI21XLTS U2499 ( .A0(n1350), .A1(n1349), .B0(n1046), .Y(n1348) );
OAI31X1TS U2500 ( .A0(n1350), .A1(FPMULT_Op_MX[17]), .A2(n1349), .B0(n1348),
.Y(n2152) );
OAI22X2TS U2501 ( .A0(n3217), .A1(FPMULT_Op_MY[1]), .B0(n1069), .B1(
FPMULT_Op_MY[0]), .Y(n1770) );
INVX2TS U2502 ( .A(n1770), .Y(n2788) );
OAI222X1TS U2503 ( .A0(n2788), .A1(n1011), .B0(n1070), .B1(n1001), .C0(n991),
.C1(n2731), .Y(n2139) );
AOI21X1TS U2504 ( .A0(FPMULT_Op_MX[17]), .A1(mult_x_69_n435), .B0(n2139),
.Y(n2138) );
NOR2X1TS U2505 ( .A(n2138), .B(n3069), .Y(n2798) );
OAI21XLTS U2506 ( .A0(n1084), .A1(n1069), .B0(n2733), .Y(n1351) );
OAI31X4TS U2507 ( .A0(n1084), .A1(n2733), .A2(n1070), .B0(n1351), .Y(n2736)
);
OAI22X1TS U2508 ( .A0(n1002), .A1(n2737), .B0(n1094), .B1(n1767), .Y(n1352)
);
AOI21X1TS U2509 ( .A0(n2256), .A1(FPMULT_Op_MY[1]), .B0(n1352), .Y(n1353) );
OAI21X1TS U2510 ( .A0(n1010), .A1(n2736), .B0(n1353), .Y(n2797) );
NOR2X1TS U2511 ( .A(n2798), .B(n2797), .Y(n2796) );
NOR2X1TS U2512 ( .A(n2796), .B(n3069), .Y(n1358) );
OAI22X1TS U2513 ( .A0(n1001), .A1(n2706), .B0(n993), .B1(n2733), .Y(n1355)
);
AOI21X1TS U2514 ( .A0(n1713), .A1(n2127), .B0(n1355), .Y(n1356) );
OAI21X1TS U2515 ( .A0(n1095), .A1(n1070), .B0(n1356), .Y(n1357) );
XNOR2X1TS U2516 ( .A(n1358), .B(n1357), .Y(n2794) );
NOR3X1TS U2517 ( .A(n1042), .B(n1767), .C(n2794), .Y(n2793) );
AOI21X1TS U2518 ( .A0(n1360), .A1(n1046), .B0(n2793), .Y(n2151) );
NAND2X1TS U2519 ( .A(n1041), .B(FPMULT_Op_MY[0]), .Y(n2795) );
OAI31X1TS U2520 ( .A0(n1362), .A1(n2795), .A2(n3068), .B0(n1031), .Y(n2150)
);
OAI22X1TS U2521 ( .A0(n1085), .A1(n1069), .B0(n2708), .B1(n2737), .Y(n1364)
);
OAI22X1TS U2522 ( .A0(n1089), .A1(n3217), .B0(n2216), .B1(n2736), .Y(n1363)
);
NOR2X1TS U2523 ( .A(n1364), .B(n1363), .Y(n2665) );
NAND2X1TS U2524 ( .A(FPMULT_Op_MX[20]), .B(n1031), .Y(n1365) );
XNOR2X1TS U2525 ( .A(n2665), .B(n1365), .Y(n2140) );
INVX2TS U2526 ( .A(n1366), .Y(mult_x_69_n388) );
OAI22X1TS U2527 ( .A0(n2469), .A1(n1090), .B0(n2699), .B1(n2705), .Y(n1369)
);
OAI22X1TS U2528 ( .A0(n2471), .A1(n1022), .B0(n3221), .B1(n1087), .Y(n1368)
);
OAI31X1TS U2529 ( .A0(n1369), .A1(n3361), .A2(n1368), .B0(n1367), .Y(
mult_x_69_n625) );
AOI21X1TS U2530 ( .A0(FPMULT_Op_MY[20]), .A1(n1510), .B0(FPMULT_Op_MY[21]),
.Y(n1370) );
OAI21X4TS U2531 ( .A0(n1370), .A1(n3061), .B0(n1815), .Y(n1821) );
OAI22X1TS U2532 ( .A0(n1060), .A1(n3061), .B0(n972), .B1(n918), .Y(n1371) );
XNOR2X1TS U2533 ( .A(n3103), .B(n3135), .Y(n1372) );
NOR2X2TS U2534 ( .A(n1372), .B(n1379), .Y(n1717) );
OAI22X1TS U2535 ( .A0(n1298), .A1(n3135), .B0(FPMULT_Op_MX[13]), .B1(
FPMULT_Op_MX[14]), .Y(n1373) );
INVX2TS U2536 ( .A(n1373), .Y(n1376) );
INVX2TS U2537 ( .A(n1379), .Y(n1395) );
NAND3XLTS U2538 ( .A(n1376), .B(n1395), .C(n1372), .Y(n1404) );
CLKBUFX2TS U2539 ( .A(n1404), .Y(n2315) );
CLKBUFX3TS U2540 ( .A(n2315), .Y(n2675) );
OAI22X1TS U2541 ( .A0(n2675), .A1(n3061), .B0(n2674), .B1(n1815), .Y(n1375)
);
OAI21XLTS U2542 ( .A0(n1717), .A1(n1375), .B0(n3212), .Y(n1374) );
OAI31X1TS U2543 ( .A0(n1717), .A1(n3362), .A2(n1375), .B0(n1374), .Y(
mult_x_69_n672) );
OAI22X1TS U2544 ( .A0(n1101), .A1(n2737), .B0(n2672), .B1(n3060), .Y(n1378)
);
OAI22X1TS U2545 ( .A0(n2315), .A1(n2731), .B0(n2674), .B1(n2736), .Y(n1377)
);
NOR2X1TS U2546 ( .A(n1378), .B(n1377), .Y(n2667) );
NAND2X1TS U2547 ( .A(n1379), .B(FPMULT_Op_MY[0]), .Y(n2801) );
NAND2X1TS U2548 ( .A(FPMULT_Op_MX[14]), .B(n932), .Y(n1381) );
XNOR2X1TS U2549 ( .A(n2667), .B(n1381), .Y(n2123) );
XOR2X1TS U2550 ( .A(FPMULT_Op_MX[9]), .B(FPMULT_Op_MX[10]), .Y(n1385) );
INVX2TS U2551 ( .A(FPMULT_Op_MX[11]), .Y(n1553) );
CLKBUFX2TS U2552 ( .A(n1553), .Y(n1619) );
CLKBUFX3TS U2553 ( .A(n2485), .Y(n2482) );
NOR2X1TS U2554 ( .A(n1383), .B(n1038), .Y(n1408) );
OAI22X1TS U2555 ( .A0(n2478), .A1(n2737), .B0(n1006), .B1(n2727), .Y(n1388)
);
OAI22X1TS U2556 ( .A0(n1005), .A1(n1047), .B0(n987), .B1(n2706), .Y(n1387)
);
OAI21XLTS U2557 ( .A0(n1388), .A1(n1387), .B0(n1081), .Y(n1386) );
OAI31X1TS U2558 ( .A0(n1388), .A1(FPMULT_Op_MX[11]), .A2(n1387), .B0(n1386),
.Y(n2118) );
OAI222X1TS U2559 ( .A0(n2788), .A1(n1008), .B0(n3060), .B1(n1004), .C0(n985),
.C1(n2731), .Y(n2126) );
AOI21X1TS U2560 ( .A0(FPMULT_Op_MX[11]), .A1(mult_x_69_n471), .B0(n2126),
.Y(n2125) );
NOR2X1TS U2561 ( .A(n2125), .B(n1619), .Y(n2804) );
OAI22X1TS U2562 ( .A0(n1004), .A1(n2737), .B0(n1096), .B1(n1767), .Y(n1389)
);
AOI21X1TS U2563 ( .A0(n2479), .A1(FPMULT_Op_MY[1]), .B0(n1389), .Y(n1390) );
OAI21X1TS U2564 ( .A0(n1007), .A1(n2736), .B0(n1390), .Y(n2803) );
NOR2X1TS U2565 ( .A(n2804), .B(n2803), .Y(n2802) );
NOR2X1TS U2566 ( .A(n2802), .B(n1553), .Y(n1394) );
OAI22X1TS U2567 ( .A0(n1005), .A1(n2706), .B0(n986), .B1(n2737), .Y(n1391)
);
AOI21X1TS U2568 ( .A0(n1822), .A1(n2127), .B0(n1391), .Y(n1392) );
OAI21X1TS U2569 ( .A0(n1097), .A1(n3060), .B0(n1392), .Y(n1393) );
NOR2XLTS U2570 ( .A(n1394), .B(n1393), .Y(n1396) );
XNOR2X1TS U2571 ( .A(n1394), .B(n1393), .Y(n2800) );
NOR3X1TS U2572 ( .A(n1395), .B(n3217), .C(n2800), .Y(n2799) );
AOI21X1TS U2573 ( .A0(n1396), .A1(FPMULT_Op_MX[11]), .B0(n2799), .Y(n2117)
);
OAI31X1TS U2574 ( .A0(n1397), .A1(n2801), .A2(n1298), .B0(n932), .Y(n2116)
);
OAI22X1TS U2575 ( .A0(n1097), .A1(n2706), .B0(n1006), .B1(n2761), .Y(n1400)
);
OAI22X1TS U2576 ( .A0(n1004), .A1(n3228), .B0(n986), .B1(n920), .Y(n1399) );
OAI21XLTS U2577 ( .A0(n1400), .A1(n1399), .B0(n1081), .Y(n1398) );
OAI31X1TS U2578 ( .A0(n1400), .A1(FPMULT_Op_MX[11]), .A2(n1399), .B0(n1398),
.Y(n2121) );
INVX2TS U2579 ( .A(n1401), .Y(mult_x_69_n439) );
OAI221X4TS U2580 ( .A0(FPMULT_Op_MX[7]), .A1(FPMULT_Op_MX[6]), .B0(n3182),
.B1(n1326), .C0(n1029), .Y(n2764) );
CLKBUFX3TS U2581 ( .A(n1720), .Y(n2763) );
NAND2BX2TS U2582 ( .AN(n1029), .B(n1445), .Y(n2689) );
OAI22X1TS U2583 ( .A0(n2763), .A1(n3061), .B0(n2689), .B1(n1815), .Y(n1403)
);
OAI21XLTS U2584 ( .A0(n1062), .A1(n1403), .B0(n3213), .Y(n1402) );
OAI31X1TS U2585 ( .A0(n1062), .A1(n3363), .A2(n1403), .B0(n1402), .Y(
mult_x_69_n726) );
CLKBUFX3TS U2586 ( .A(n3222), .Y(n2700) );
CLKBUFX3TS U2587 ( .A(n1404), .Y(n2263) );
OAI22X1TS U2588 ( .A0(n2700), .A1(n2263), .B0(n2699), .B1(n1105), .Y(n1407)
);
OAI22X1TS U2589 ( .A0(n2471), .A1(n2673), .B0(n3221), .B1(n1052), .Y(n1406)
);
OAI21XLTS U2590 ( .A0(n1407), .A1(n1406), .B0(n2204), .Y(n1405) );
OAI31X1TS U2591 ( .A0(n1407), .A1(n3362), .A2(n1406), .B0(n1405), .Y(
mult_x_69_n679) );
OAI2BB2X1TS U2592 ( .B0(n1008), .B1(n1815), .A0N(n1408), .A1N(n954), .Y(
n1410) );
OAI21XLTS U2593 ( .A0(n2479), .A1(n1410), .B0(n1553), .Y(n1409) );
OAI31X1TS U2594 ( .A0(n2479), .A1(n3118), .A2(n1410), .B0(n1409), .Y(
mult_x_69_n699) );
CLKBUFX3TS U2595 ( .A(n3218), .Y(n2720) );
OAI22X1TS U2596 ( .A0(n2720), .A1(n1094), .B0(n1009), .B1(n2715), .Y(n1413)
);
OAI22X1TS U2597 ( .A0(n2451), .A1(n1000), .B0(n3224), .B1(n992), .Y(n1412)
);
OAI21XLTS U2598 ( .A0(n1413), .A1(n1412), .B0(n2258), .Y(n1411) );
OAI31X1TS U2599 ( .A0(n1413), .A1(n2261), .A2(n1412), .B0(n1411), .Y(
mult_x_69_n658) );
OAI22X1TS U2600 ( .A0(n2700), .A1(n1096), .B0(n2699), .B1(n1007), .Y(n1416)
);
OAI22X1TS U2601 ( .A0(n910), .A1(n1003), .B0(n3221), .B1(n986), .Y(n1415) );
OAI21XLTS U2602 ( .A0(n1416), .A1(n1415), .B0(n2482), .Y(n1414) );
OAI31X1TS U2603 ( .A0(n1416), .A1(n2485), .A2(n1415), .B0(n1414), .Y(
mult_x_69_n706) );
OAI22X1TS U2604 ( .A0(n2714), .A1(n1056), .B0(n3218), .B1(n973), .Y(n1418)
);
OAI22X1TS U2605 ( .A0(n2751), .A1(n1060), .B0(n2789), .B1(n2715), .Y(n1417)
);
NOR2XLTS U2606 ( .A(n1418), .B(n1417), .Y(mult_x_69_n605) );
OAI22X1TS U2607 ( .A0(n2700), .A1(n1094), .B0(n2699), .B1(n1010), .Y(n1421)
);
OAI22X1TS U2608 ( .A0(n2471), .A1(n1000), .B0(n3221), .B1(n993), .Y(n1420)
);
OAI21XLTS U2609 ( .A0(n1421), .A1(n1420), .B0(n3069), .Y(n1419) );
OAI31X1TS U2610 ( .A0(n1421), .A1(n2261), .A2(n1420), .B0(n1419), .Y(
mult_x_69_n652) );
CLKBUFX3TS U2611 ( .A(n3221), .Y(n2462) );
OAI22X1TS U2612 ( .A0(n2462), .A1(n2263), .B0(n2244), .B1(n1106), .Y(n1424)
);
CLKBUFX3TS U2613 ( .A(n1298), .Y(n2267) );
OAI22X1TS U2614 ( .A0(n2471), .A1(n1052), .B0(n1040), .B1(n1101), .Y(n1423)
);
OAI21XLTS U2615 ( .A0(n1424), .A1(n1423), .B0(n2204), .Y(n1422) );
OAI31X1TS U2616 ( .A0(n1424), .A1(n2267), .A2(n1423), .B0(n1422), .Y(
mult_x_69_n678) );
OAI22X1TS U2617 ( .A0(n2462), .A1(n1094), .B0(n2244), .B1(n1011), .Y(n1427)
);
OAI22X1TS U2618 ( .A0(n2471), .A1(n993), .B0(n1040), .B1(n1002), .Y(n1426)
);
OAI21XLTS U2619 ( .A0(n1427), .A1(n1426), .B0(n1045), .Y(n1425) );
OAI31X1TS U2620 ( .A0(n1427), .A1(n2261), .A2(n1426), .B0(n1425), .Y(
mult_x_69_n651) );
OAI22X1TS U2621 ( .A0(n2468), .A1(n3219), .B0(n1012), .B1(n2761), .Y(n1433)
);
OAI22X1TS U2622 ( .A0(n995), .A1(n2756), .B0(n989), .B1(n1048), .Y(n1432) );
OAI21XLTS U2623 ( .A0(n1433), .A1(n1432), .B0(FPMULT_Op_MX[5]), .Y(n1431) );
OAI31X1TS U2624 ( .A0(n1433), .A1(FPMULT_Op_MX[5]), .A2(n1432), .B0(n1431),
.Y(n1809) );
OAI222X1TS U2625 ( .A0(n2788), .A1(n1014), .B0(n1070), .B1(n995), .C0(n988),
.C1(n3217), .Y(n1789) );
AOI31X1TS U2626 ( .A0(FPMULT_Op_MX[5]), .A1(n1434), .A2(FPMULT_Op_MY[0]),
.B0(n1789), .Y(n1788) );
NOR2X1TS U2627 ( .A(n1788), .B(n3211), .Y(n1795) );
OAI22X1TS U2628 ( .A0(n996), .A1(n3231), .B0(n1098), .B1(n1767), .Y(n1435)
);
AOI21X1TS U2629 ( .A0(n2470), .A1(FPMULT_Op_MY[1]), .B0(n1435), .Y(n1436) );
OAI21X1TS U2630 ( .A0(n1013), .A1(n2736), .B0(n1436), .Y(n1794) );
NOR2X1TS U2631 ( .A(n1795), .B(n1794), .Y(n1793) );
NOR2X1TS U2632 ( .A(n1793), .B(n3211), .Y(n1439) );
OAI22X1TS U2633 ( .A0(n995), .A1(n3219), .B0(n990), .B1(n2733), .Y(n1437) );
AOI21X1TS U2634 ( .A0(n1724), .A1(n2127), .B0(n1437), .Y(n1438) );
OAI21X1TS U2635 ( .A0(n1099), .A1(n1070), .B0(n1438), .Y(n1440) );
NOR2XLTS U2636 ( .A(n1439), .B(n1440), .Y(n1441) );
XNOR2X1TS U2637 ( .A(n1440), .B(n1439), .Y(n1797) );
NOR3X1TS U2638 ( .A(n1029), .B(n1767), .C(n1797), .Y(n1796) );
AOI21X1TS U2639 ( .A0(n1441), .A1(FPMULT_Op_MX[5]), .B0(n1796), .Y(n1804) );
OAI22X1TS U2640 ( .A0(n1099), .A1(n3231), .B0(n1012), .B1(n2727), .Y(n1444)
);
OAI22X1TS U2641 ( .A0(n996), .A1(n1047), .B0(n989), .B1(n2757), .Y(n1443) );
OAI21XLTS U2642 ( .A0(n1444), .A1(n1443), .B0(FPMULT_Op_MX[5]), .Y(n1442) );
OAI31X1TS U2643 ( .A0(n1444), .A1(FPMULT_Op_MX[5]), .A2(n1443), .B0(n1442),
.Y(n1803) );
INVX2TS U2644 ( .A(n2689), .Y(n1721) );
NAND2BX1TS U2645 ( .AN(n1029), .B(FPMULT_Op_MY[0]), .Y(n1798) );
OAI22X1TS U2646 ( .A0(n1063), .A1(n1069), .B0(n1076), .B1(n2733), .Y(n1450)
);
OAI22X1TS U2647 ( .A0(n1720), .A1(n3217), .B0(n2762), .B1(n2736), .Y(n1449)
);
NOR2X1TS U2648 ( .A(n1450), .B(n1449), .Y(n2666) );
NAND2X1TS U2649 ( .A(FPMULT_Op_MX[8]), .B(n934), .Y(n1451) );
XNOR2X1TS U2650 ( .A(n2666), .B(n1451), .Y(n1807) );
INVX2TS U2651 ( .A(n1452), .Y(mult_x_69_n472) );
INVX2TS U2652 ( .A(n2626), .Y(n3045) );
NAND3BX1TS U2653 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .C(n1454), .Y(n3046) );
NAND2X1TS U2654 ( .A(n3045), .B(n3046), .Y(n3038) );
INVX2TS U2655 ( .A(begin_operation), .Y(n3036) );
INVX2TS U2656 ( .A(operation[2]), .Y(n2783) );
CLKBUFX2TS U2657 ( .A(n2292), .Y(n2305) );
AOI22X1TS U2658 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
n1457), .B0(n3081), .B1(n3121), .Y(n1458) );
NOR2XLTS U2659 ( .A(n2082), .B(n1458), .Y(FPADDSUB_enable_Pipeline_input) );
INVX2TS U2660 ( .A(n2780), .Y(n2272) );
NAND3XLTS U2661 ( .A(n2518), .B(FPMULT_FS_Module_state_reg[3]), .C(
FPMULT_FS_Module_state_reg[2]), .Y(n2779) );
AOI21X1TS U2662 ( .A0(ack_operation), .A1(n2306), .B0(n2779), .Y(n1456) );
OAI32X1TS U2663 ( .A0(n1456), .A1(n2780), .A2(n3036), .B0(n1455), .B1(n1456),
.Y(n846) );
NOR2XLTS U2664 ( .A(n1661), .B(n3035), .Y(FPMULT_FSM_final_result_load) );
NOR3X1TS U2665 ( .A(n942), .B(n3124), .C(n1661), .Y(n2329) );
AO21XLTS U2666 ( .A0(FPMULT_FSM_add_overflow_flag), .A1(n2329), .B0(n1459),
.Y(FPMULT_FSM_load_second_step) );
OR2X1TS U2667 ( .A(n107), .B(FPMULT_FSM_load_second_step), .Y(
FPMULT_FSM_exp_operation_load_result) );
CLKBUFX3TS U2668 ( .A(n3227), .Y(n2772) );
OAI22X1TS U2669 ( .A0(n2478), .A1(n1047), .B0(n1006), .B1(n1034), .Y(n1463)
);
OAI22X1TS U2670 ( .A0(n1005), .A1(n3227), .B0(n987), .B1(n2770), .Y(n1462)
);
OAI21XLTS U2671 ( .A0(n1463), .A1(n1462), .B0(n1553), .Y(n1461) );
OAI31X1TS U2672 ( .A0(n1463), .A1(n1553), .A2(n1462), .B0(n1461), .Y(
mult_x_69_n717) );
CLKBUFX3TS U2673 ( .A(n2751), .Y(n2745) );
OAI22X1TS U2674 ( .A0(n2745), .A1(n994), .B0(n3218), .B1(n989), .Y(n1470) );
CLKBUFX2TS U2675 ( .A(n3211), .Y(n1464) );
CLKBUFX3TS U2676 ( .A(n1464), .Y(n2777) );
NOR2XLTS U2677 ( .A(FPMULT_Op_MY[9]), .B(n1466), .Y(n1465) );
AOI21X1TS U2678 ( .A0(n1466), .A1(FPMULT_Op_MY[9]), .B0(n1465), .Y(n1467) );
OAI22X1TS U2679 ( .A0(n2468), .A1(n3225), .B0(n1012), .B1(n1035), .Y(n1469)
);
OAI21XLTS U2680 ( .A0(n1470), .A1(n1469), .B0(n1326), .Y(n1468) );
OAI31X1TS U2681 ( .A0(n1470), .A1(n2777), .A2(n1469), .B0(n1468), .Y(
mult_x_69_n767) );
OAI21XLTS U2682 ( .A0(n1473), .A1(n1472), .B0(n2690), .Y(n1471) );
OAI31X4TS U2683 ( .A0(n1473), .A1(n2690), .A2(n1472), .B0(n1471), .Y(n2688)
);
OAI22X1TS U2684 ( .A0(n1066), .A1(n1096), .B0(n1006), .B1(n2688), .Y(n1476)
);
OAI22X1TS U2685 ( .A0(n2462), .A1(n1003), .B0(n3222), .B1(n987), .Y(n1475)
);
OAI21XLTS U2686 ( .A0(n1476), .A1(n1475), .B0(n2482), .Y(n1474) );
OAI31X1TS U2687 ( .A0(n1476), .A1(n1553), .A2(n1475), .B0(n1474), .Y(
mult_x_69_n707) );
CLKBUFX2TS U2688 ( .A(n3225), .Y(n2719) );
OAI22X1TS U2689 ( .A0(n2720), .A1(n994), .B0(n990), .B1(n2719), .Y(n1481) );
CMPR32X2TS U2690 ( .A(FPMULT_Op_MY[8]), .B(FPMULT_Op_MY[9]), .C(n1477), .CO(
n1466), .S(n1478) );
INVX2TS U2691 ( .A(n1478), .Y(n2721) );
OAI22X1TS U2692 ( .A0(n1099), .A1(n3226), .B0(n1012), .B1(n2721), .Y(n1480)
);
OAI21XLTS U2693 ( .A0(n1481), .A1(n1480), .B0(n3211), .Y(n1479) );
OAI31X1TS U2694 ( .A0(n1481), .A1(n2777), .A2(n1480), .B0(n1479), .Y(
mult_x_69_n768) );
OAI22X1TS U2695 ( .A0(n1004), .A1(n3226), .B0(n985), .B1(n2252), .Y(n1486)
);
CMPR32X2TS U2696 ( .A(FPMULT_Op_MY[6]), .B(FPMULT_Op_MY[7]), .C(n1482), .CO(
n1305), .S(n1483) );
INVX2TS U2697 ( .A(n1483), .Y(n2694) );
OAI22X1TS U2698 ( .A0(n1097), .A1(n3228), .B0(n1006), .B1(n2694), .Y(n1485)
);
OAI31X1TS U2699 ( .A0(n1486), .A1(n1553), .A2(n1485), .B0(n1484), .Y(
mult_x_69_n716) );
OAI22X1TS U2700 ( .A0(n995), .A1(n3226), .B0(n988), .B1(n2252), .Y(n1489) );
OAI22X1TS U2701 ( .A0(n2468), .A1(n2770), .B0(n1012), .B1(n2694), .Y(n1488)
);
OAI31X1TS U2702 ( .A0(n1489), .A1(n2777), .A2(n1488), .B0(n1487), .Y(
mult_x_69_n770) );
CLKBUFX3TS U2703 ( .A(n1033), .Y(n2683) );
OAI21XLTS U2704 ( .A0(n1492), .A1(n1491), .B0(n2469), .Y(n1490) );
OAI31X4TS U2705 ( .A0(n1492), .A1(n2469), .A2(n1491), .B0(n1490), .Y(n2679)
);
OAI22X1TS U2706 ( .A0(n2683), .A1(n2263), .B0(n2674), .B1(n2679), .Y(n1495)
);
OAI22X1TS U2707 ( .A0(n2700), .A1(n2673), .B0(n3115), .B1(n1051), .Y(n1494)
);
OAI21XLTS U2708 ( .A0(n1495), .A1(n1494), .B0(n2204), .Y(n1493) );
OAI31X1TS U2709 ( .A0(n1495), .A1(n2267), .A2(n1494), .B0(n1493), .Y(
mult_x_69_n681) );
OAI22X1TS U2710 ( .A0(n2720), .A1(n1021), .B0(n1085), .B1(n2181), .Y(n1498)
);
OAI22X1TS U2711 ( .A0(n1090), .A1(n2722), .B0(n2705), .B1(n2721), .Y(n1497)
);
OAI21XLTS U2712 ( .A0(n1498), .A1(n1497), .B0(n2324), .Y(n1496) );
OAI31X1TS U2713 ( .A0(n1498), .A1(n3361), .A2(n1497), .B0(n1496), .Y(
mult_x_69_n633) );
OAI22X1TS U2714 ( .A0(n1060), .A1(n1027), .B0(n972), .B1(n919), .Y(n1501) );
CLKBUFX3TS U2715 ( .A(n1027), .Y(n2809) );
XNOR2X4TS U2716 ( .A(n1499), .B(n2072), .Y(n1730) );
OAI22X1TS U2717 ( .A0(n1058), .A1(n955), .B0(n2789), .B1(n1730), .Y(n1500)
);
NOR2XLTS U2718 ( .A(n1501), .B(n1500), .Y(mult_x_69_n594) );
OAI22X1TS U2719 ( .A0(n1099), .A1(n1024), .B0(n1012), .B1(n1730), .Y(n1504)
);
OAI22X1TS U2720 ( .A0(n996), .A1(n3061), .B0(n988), .B1(n2809), .Y(n1503) );
OAI21XLTS U2721 ( .A0(n1504), .A1(n1503), .B0(n3211), .Y(n1502) );
OAI31X1TS U2722 ( .A0(n1504), .A1(n2475), .A2(n1503), .B0(n1502), .Y(
mult_x_69_n755) );
INVX2TS U2723 ( .A(n1638), .Y(n1507) );
NOR2X1TS U2724 ( .A(n966), .B(n3067), .Y(n1665) );
AOI22X1TS U2725 ( .A0(n1109), .A1(n3112), .B0(n956), .B1(n3067), .Y(n1505)
);
AOI22X1TS U2726 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[19]), .A1(n1109), .B0(
FPADDSUB_DmP_mant_SHT1_SW[4]), .B1(n966), .Y(n1506) );
INVX2TS U2727 ( .A(n2600), .Y(n1639) );
OAI222X4TS U2728 ( .A0(n957), .A1(FPADDSUB_Raw_mant_NRM_SWR[4]), .B0(n963),
.B1(FPADDSUB_Raw_mant_NRM_SWR[21]), .C0(FPADDSUB_DmP_mant_SHT1_SW[2]),
.C1(n965), .Y(n2047) );
OAI222X4TS U2729 ( .A0(n957), .A1(FPADDSUB_Raw_mant_NRM_SWR[3]), .B0(n963),
.B1(FPADDSUB_Raw_mant_NRM_SWR[22]), .C0(FPADDSUB_DmP_mant_SHT1_SW[1]),
.C1(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n2048) );
OAI22X1TS U2730 ( .A0(n974), .A1(n2047), .B0(n3021), .B1(n2048), .Y(n1508)
);
AOI21X1TS U2731 ( .A0(n2057), .A1(n1043), .B0(n1508), .Y(n1509) );
OAI21XLTS U2732 ( .A0(n971), .A1(n1983), .B0(n1509), .Y(
FPADDSUB_Data_array_SWR[3]) );
OAI22X1TS U2733 ( .A0(n1061), .A1(n919), .B0(n972), .B1(n921), .Y(n1513) );
CMPR32X2TS U2734 ( .A(FPMULT_Op_MY[20]), .B(FPMULT_Op_MY[21]), .C(n1510),
.CO(n1499), .S(n1511) );
INVX2TS U2735 ( .A(n1511), .Y(n1734) );
OAI22X1TS U2736 ( .A0(n1057), .A1(n1027), .B0(n2789), .B1(n1734), .Y(n1512)
);
NOR2XLTS U2737 ( .A(n1513), .B(n1512), .Y(mult_x_69_n595) );
OAI22X1TS U2738 ( .A0(n2745), .A1(n1000), .B0(n3218), .B1(n992), .Y(n1516)
);
OAI22X1TS U2739 ( .A0(n2318), .A1(n3225), .B0(n1009), .B1(n1035), .Y(n1515)
);
OAI21XLTS U2740 ( .A0(n1516), .A1(n1515), .B0(n2258), .Y(n1514) );
OAI31X1TS U2741 ( .A0(n1516), .A1(n2199), .A2(n1515), .B0(n1514), .Y(
mult_x_69_n659) );
OAI22X1TS U2742 ( .A0(n1063), .A1(n1024), .B0(n1077), .B1(n2809), .Y(n1519)
);
OAI22X1TS U2743 ( .A0(n2763), .A1(n1071), .B0(n2689), .B1(n1734), .Y(n1518)
);
CLKBUFX2TS U2744 ( .A(n3213), .Y(n2765) );
OAI31X1TS U2745 ( .A0(n1519), .A1(n3363), .A2(n1518), .B0(n1517), .Y(
mult_x_69_n729) );
CLKBUFX2TS U2746 ( .A(n3226), .Y(n2226) );
OAI22X1TS U2747 ( .A0(n1005), .A1(n3225), .B0(n985), .B1(n2226), .Y(n1522)
);
OAI22X1TS U2748 ( .A0(n2478), .A1(n3227), .B0(n1006), .B1(n2251), .Y(n1521)
);
OAI21XLTS U2749 ( .A0(n1522), .A1(n1521), .B0(n1619), .Y(n1520) );
OAI31X1TS U2750 ( .A0(n1522), .A1(n3118), .A2(n1521), .B0(n1520), .Y(
mult_x_69_n715) );
OAI22X1TS U2751 ( .A0(n995), .A1(n2719), .B0(n988), .B1(n2226), .Y(n1525) );
OAI22X1TS U2752 ( .A0(n2468), .A1(n3227), .B0(n1012), .B1(n2251), .Y(n1524)
);
OAI31X1TS U2753 ( .A0(n1525), .A1(n2777), .A2(n1524), .B0(n1523), .Y(
mult_x_69_n769) );
OAI22X1TS U2754 ( .A0(n2751), .A1(n1056), .B0(n972), .B1(n2181), .Y(n1527)
);
OAI22X1TS U2755 ( .A0(n2744), .A1(n1060), .B0(n2789), .B1(n1035), .Y(n1526)
);
NOR2XLTS U2756 ( .A(n1527), .B(n1526), .Y(mult_x_69_n606) );
AOI222X4TS U2757 ( .A0(n966), .A1(FPADDSUB_DmP_mant_SHT1_SW[0]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[2]), .B1(n953), .C0(
FPADDSUB_Raw_mant_NRM_SWR[23]), .C1(n1107), .Y(n2052) );
OAI22X1TS U2758 ( .A0(n2052), .A1(n3021), .B0(n974), .B1(n2048), .Y(n1528)
);
AOI2BB1XLTS U2759 ( .A0N(n969), .A1N(n1983), .B0(n1528), .Y(n1529) );
OAI21XLTS U2760 ( .A0(n971), .A1(n2047), .B0(n1529), .Y(
FPADDSUB_Data_array_SWR[2]) );
CLKBUFX2TS U2761 ( .A(n1024), .Y(n2111) );
OAI22X1TS U2762 ( .A0(n996), .A1(n2809), .B0(n988), .B1(n2111), .Y(n1532) );
OAI22X1TS U2763 ( .A0(n1099), .A1(n1071), .B0(n1014), .B1(n1734), .Y(n1531)
);
OAI21XLTS U2764 ( .A0(n1532), .A1(n1531), .B0(n2472), .Y(n1530) );
OAI31X1TS U2765 ( .A0(n1532), .A1(n2475), .A2(n1531), .B0(n1530), .Y(
mult_x_69_n756) );
OAI22X1TS U2766 ( .A0(n1067), .A1(n994), .B0(n1033), .B1(n990), .Y(n1538) );
NAND2X1TS U2767 ( .A(FPMULT_Op_MY[13]), .B(n1534), .Y(n1533) );
OAI22X1TS U2768 ( .A0(n2481), .A1(n1098), .B0(n1013), .B1(n2668), .Y(n1537)
);
OAI21XLTS U2769 ( .A0(n1538), .A1(n1537), .B0(n2472), .Y(n1536) );
OAI31X1TS U2770 ( .A0(n1538), .A1(n2777), .A2(n1537), .B0(n1536), .Y(
mult_x_69_n763) );
OAI22X1TS U2771 ( .A0(n1088), .A1(n919), .B0(n2313), .B1(n1730), .Y(n1541)
);
OAI22X1TS U2772 ( .A0(n1086), .A1(n1027), .B0(n2708), .B1(n955), .Y(n1540)
);
OAI21XLTS U2773 ( .A0(n1541), .A1(n1540), .B0(n2710), .Y(n1539) );
OAI31X1TS U2774 ( .A0(n1541), .A1(n3361), .A2(n1540), .B0(n1539), .Y(
mult_x_69_n620) );
OAI22X1TS U2775 ( .A0(n2720), .A1(n1003), .B0(n985), .B1(n2181), .Y(n1544)
);
OAI22X1TS U2776 ( .A0(n1097), .A1(n2226), .B0(n1006), .B1(n2721), .Y(n1543)
);
OAI31X1TS U2777 ( .A0(n1544), .A1(n3118), .A2(n1543), .B0(n1542), .Y(
mult_x_69_n714) );
OAI22X1TS U2778 ( .A0(n1087), .A1(n919), .B0(n2708), .B1(n918), .Y(n1547) );
OAI22X1TS U2779 ( .A0(n1089), .A1(n1071), .B0(n2313), .B1(n1734), .Y(n1546)
);
OAI21XLTS U2780 ( .A0(n1547), .A1(n1546), .B0(n2166), .Y(n1545) );
OAI31X1TS U2781 ( .A0(n1547), .A1(n2327), .A2(n1546), .B0(n1545), .Y(
mult_x_69_n621) );
OAI22X1TS U2782 ( .A0(n2745), .A1(n1022), .B0(n3218), .B1(n1085), .Y(n1550)
);
OAI22X1TS U2783 ( .A0(n1090), .A1(n2181), .B0(n2216), .B1(n1035), .Y(n1549)
);
OAI21XLTS U2784 ( .A0(n1550), .A1(n1549), .B0(n2324), .Y(n1548) );
OAI31X1TS U2785 ( .A0(n1550), .A1(n2327), .A2(n1549), .B0(n1548), .Y(
mult_x_69_n632) );
OAI22X1TS U2786 ( .A0(n2683), .A1(n1096), .B0(n1008), .B1(n2679), .Y(n1554)
);
OAI22X1TS U2787 ( .A0(n2700), .A1(n1003), .B0(n3115), .B1(n986), .Y(n1552)
);
OAI21XLTS U2788 ( .A0(n1554), .A1(n1552), .B0(n2482), .Y(n1551) );
OAI31X1TS U2789 ( .A0(n1554), .A1(n1553), .A2(n1552), .B0(n1551), .Y(
mult_x_69_n708) );
OAI22X1TS U2790 ( .A0(n2745), .A1(n1003), .B0(n3218), .B1(n987), .Y(n1557)
);
OAI22X1TS U2791 ( .A0(n2478), .A1(n3225), .B0(n1007), .B1(n1035), .Y(n1556)
);
OAI21XLTS U2792 ( .A0(n1557), .A1(n1556), .B0(n2485), .Y(n1555) );
OAI31X1TS U2793 ( .A0(n1557), .A1(n3118), .A2(n1556), .B0(n1555), .Y(
mult_x_69_n713) );
OAI22X1TS U2794 ( .A0(n1066), .A1(n2263), .B0(n2674), .B1(n2688), .Y(n1560)
);
OAI22X1TS U2795 ( .A0(n2462), .A1(n2673), .B0(n3222), .B1(n1052), .Y(n1559)
);
OAI21XLTS U2796 ( .A0(n1560), .A1(n1559), .B0(n2204), .Y(n1558) );
OAI31X1TS U2797 ( .A0(n1560), .A1(n3362), .A2(n1559), .B0(n1558), .Y(
mult_x_69_n680) );
OAI22X1TS U2798 ( .A0(n1095), .A1(n1024), .B0(n1009), .B1(n1730), .Y(n1563)
);
OAI22X1TS U2799 ( .A0(n1002), .A1(n955), .B0(n992), .B1(n2809), .Y(n1562) );
OAI21XLTS U2800 ( .A0(n1563), .A1(n1562), .B0(n1045), .Y(n1561) );
OAI31X1TS U2801 ( .A0(n1563), .A1(n2199), .A2(n1562), .B0(n1561), .Y(
mult_x_69_n647) );
NAND2X2TS U2802 ( .A(n3119), .B(n3056), .Y(n3050) );
CLKBUFX2TS U2803 ( .A(n2660), .Y(n2651) );
INVX2TS U2804 ( .A(n2663), .Y(n3027) );
NOR2XLTS U2805 ( .A(n3047), .B(n3027), .Y(n850) );
NOR2XLTS U2806 ( .A(n2469), .B(n1061), .Y(n1565) );
OAI22X1TS U2807 ( .A0(n2690), .A1(n1056), .B0(n2789), .B1(n2688), .Y(n1564)
);
AOI211X1TS U2808 ( .A0(n2775), .A1(FPMULT_Op_MY[14]), .B0(n1565), .C0(n1564),
.Y(mult_x_69_n600) );
INVX2TS U2809 ( .A(n1721), .Y(n2698) );
OAI22X1TS U2810 ( .A0(n2763), .A1(n1024), .B0(n2698), .B1(n1730), .Y(n1568)
);
OAI22X1TS U2811 ( .A0(n1063), .A1(n2809), .B0(n1078), .B1(n955), .Y(n1567)
);
OAI21XLTS U2812 ( .A0(n1568), .A1(n1567), .B0(n2701), .Y(n1566) );
OAI31X1TS U2813 ( .A0(n1568), .A1(n3363), .A2(n1567), .B0(n1566), .Y(
mult_x_69_n728) );
OAI22X1TS U2814 ( .A0(n2720), .A1(n1096), .B0(n1008), .B1(n2715), .Y(n1571)
);
OAI22X1TS U2815 ( .A0(n2451), .A1(n1004), .B0(n2751), .B1(n986), .Y(n1570)
);
OAI21XLTS U2816 ( .A0(n1571), .A1(n1570), .B0(n2485), .Y(n1569) );
OAI31X1TS U2817 ( .A0(n1571), .A1(n3118), .A2(n1570), .B0(n1569), .Y(
mult_x_69_n712) );
OAI22X1TS U2818 ( .A0(n1001), .A1(n1027), .B0(n991), .B1(n919), .Y(n1574) );
OAI22X1TS U2819 ( .A0(n2318), .A1(n1071), .B0(n1009), .B1(n1734), .Y(n1573)
);
OAI21XLTS U2820 ( .A0(n1574), .A1(n1573), .B0(n3069), .Y(n1572) );
OAI31X1TS U2821 ( .A0(n1574), .A1(n2199), .A2(n1573), .B0(n1572), .Y(
mult_x_69_n648) );
OAI22X1TS U2822 ( .A0(n2720), .A1(n1000), .B0(n991), .B1(n2181), .Y(n1577)
);
OAI22X1TS U2823 ( .A0(n1095), .A1(n2722), .B0(n1009), .B1(n2721), .Y(n1576)
);
OAI21XLTS U2824 ( .A0(n1577), .A1(n1576), .B0(n2258), .Y(n1575) );
OAI31X1TS U2825 ( .A0(n1577), .A1(n2199), .A2(n1576), .B0(n1575), .Y(
mult_x_69_n660) );
OAI22X1TS U2826 ( .A0(n2318), .A1(n1047), .B0(n1011), .B1(n1034), .Y(n1580)
);
OAI22X1TS U2827 ( .A0(n1002), .A1(n3227), .B0(n991), .B1(n2756), .Y(n1579)
);
OAI31X1TS U2828 ( .A0(n1580), .A1(n2199), .A2(n1579), .B0(n1578), .Y(
mult_x_69_n663) );
NOR2XLTS U2829 ( .A(n1066), .B(n2771), .Y(n1582) );
OAI22X1TS U2830 ( .A0(n2469), .A1(n1058), .B0(n2789), .B1(n2679), .Y(n1581)
);
AOI211X1TS U2831 ( .A0(n2775), .A1(FPMULT_Op_MY[13]), .B0(n1582), .C0(n1581),
.Y(mult_x_69_n601) );
NAND2X1TS U2832 ( .A(n865), .B(FPSENCOS_cont_iter_out[0]), .Y(n2619) );
OAI21XLTS U2833 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n865), .B0(n2619), .Y(
n849) );
OAI22X1TS U2834 ( .A0(n2675), .A1(n2111), .B0(n2674), .B1(n1730), .Y(n1585)
);
OAI22X1TS U2835 ( .A0(n1100), .A1(n955), .B0(n2672), .B1(n2809), .Y(n1584)
);
OAI21XLTS U2836 ( .A0(n1585), .A1(n1584), .B0(n2204), .Y(n1583) );
OAI31X1TS U2837 ( .A0(n1585), .A1(n3362), .A2(n1584), .B0(n1583), .Y(
mult_x_69_n674) );
OAI22X1TS U2838 ( .A0(n2771), .A1(n3225), .B0(n973), .B1(n2226), .Y(n1587)
);
OAI22X1TS U2839 ( .A0(n2744), .A1(n1057), .B0(n1104), .B1(n2721), .Y(n1586)
);
OAI22X1TS U2840 ( .A0(n1067), .A1(n1088), .B0(n2705), .B1(n2688), .Y(n1590)
);
OAI22X1TS U2841 ( .A0(n2462), .A1(n1021), .B0(n3222), .B1(n1086), .Y(n1589)
);
OAI21XLTS U2842 ( .A0(n1590), .A1(n1589), .B0(n2324), .Y(n1588) );
OAI31X1TS U2843 ( .A0(n1590), .A1(n3068), .A2(n1589), .B0(n1588), .Y(
mult_x_69_n626) );
OAI22X1TS U2844 ( .A0(n2462), .A1(n1098), .B0(n2244), .B1(n1013), .Y(n1593)
);
OAI22X1TS U2845 ( .A0(n2191), .A1(n990), .B0(n3220), .B1(n996), .Y(n1592) );
OAI21XLTS U2846 ( .A0(n1593), .A1(n1592), .B0(n1464), .Y(n1591) );
OAI31X1TS U2847 ( .A0(n1593), .A1(n2475), .A2(n1592), .B0(n1591), .Y(
mult_x_69_n759) );
OAI22X1TS U2848 ( .A0(n995), .A1(n1024), .B0(n989), .B1(n1072), .Y(n1598) );
CLKBUFX3TS U2849 ( .A(n1040), .Y(n2239) );
CMPR32X2TS U2850 ( .A(FPMULT_Op_MY[19]), .B(FPMULT_Op_MY[20]), .C(n1594),
.CO(n1510), .S(n1595) );
INVX2TS U2851 ( .A(n1595), .Y(n2112) );
OAI22X1TS U2852 ( .A0(n2239), .A1(n1098), .B0(n1014), .B1(n2112), .Y(n1597)
);
OAI21XLTS U2853 ( .A0(n1598), .A1(n1597), .B0(n2472), .Y(n1596) );
OAI31X1TS U2854 ( .A0(n1598), .A1(n2475), .A2(n1597), .B0(n1596), .Y(
mult_x_69_n757) );
OAI22X1TS U2855 ( .A0(n1033), .A1(n1094), .B0(n1010), .B1(n2679), .Y(n1601)
);
OAI22X1TS U2856 ( .A0(n2700), .A1(n1000), .B0(n3115), .B1(n993), .Y(n1600)
);
OAI21XLTS U2857 ( .A0(n1601), .A1(n1600), .B0(n3069), .Y(n1599) );
OAI31X1TS U2858 ( .A0(n1601), .A1(n2261), .A2(n1600), .B0(n1599), .Y(
mult_x_69_n654) );
OAI22X1TS U2859 ( .A0(n1001), .A1(n3226), .B0(n991), .B1(n2772), .Y(n1604)
);
OAI22X1TS U2860 ( .A0(n1095), .A1(n3228), .B0(n1011), .B1(n2694), .Y(n1603)
);
OAI21XLTS U2861 ( .A0(n1604), .A1(n1603), .B0(n2258), .Y(n1602) );
OAI31X1TS U2862 ( .A0(n1604), .A1(n2199), .A2(n1603), .B0(n1602), .Y(
mult_x_69_n662) );
OAI22X1TS U2863 ( .A0(n1101), .A1(n1027), .B0(n2672), .B1(n919), .Y(n1607)
);
OAI22X1TS U2864 ( .A0(n2675), .A1(n1071), .B0(n2674), .B1(n1734), .Y(n1606)
);
OAI21XLTS U2865 ( .A0(n1607), .A1(n1606), .B0(n2204), .Y(n1605) );
OAI31X1TS U2866 ( .A0(n1607), .A1(n3362), .A2(n1606), .B0(n1605), .Y(
mult_x_69_n675) );
OAI22X1TS U2867 ( .A0(n2683), .A1(n1089), .B0(n2313), .B1(n2679), .Y(n1610)
);
OAI22X1TS U2868 ( .A0(n2700), .A1(n1022), .B0(n3115), .B1(n1087), .Y(n1609)
);
OAI31X1TS U2869 ( .A0(n1610), .A1(n3068), .A2(n1609), .B0(n1608), .Y(
mult_x_69_n627) );
OAI22X1TS U2870 ( .A0(n2683), .A1(n1005), .B0(n3229), .B1(n987), .Y(n1615)
);
CMPR32X2TS U2871 ( .A(FPMULT_Op_MY[12]), .B(FPMULT_Op_MY[13]), .C(n1611),
.CO(n1534), .S(n1612) );
INVX2TS U2872 ( .A(n1612), .Y(n2684) );
OAI22X1TS U2873 ( .A0(n2451), .A1(n1096), .B0(n1007), .B1(n2684), .Y(n1614)
);
OAI21XLTS U2874 ( .A0(n1615), .A1(n1614), .B0(n2482), .Y(n1613) );
OAI31X1TS U2875 ( .A0(n1615), .A1(n3118), .A2(n1614), .B0(n1613), .Y(
mult_x_69_n710) );
NAND2X1TS U2876 ( .A(n3201), .B(FPSENCOS_cont_iter_out[0]), .Y(n2659) );
NOR2X1TS U2877 ( .A(FPSENCOS_d_ff2_Y[27]), .B(n2489), .Y(n2488) );
OR3X1TS U2878 ( .A(FPSENCOS_d_ff2_Y[27]), .B(FPSENCOS_d_ff2_Y[28]), .C(n2489), .Y(n3054) );
OAI21XLTS U2879 ( .A0(n2488), .A1(n3270), .B0(n3054), .Y(
FPSENCOS_sh_exp_y[5]) );
OAI22X1TS U2880 ( .A0(n1004), .A1(n1027), .B0(n985), .B1(n919), .Y(n1618) );
OAI22X1TS U2881 ( .A0(n1097), .A1(n1071), .B0(n1008), .B1(n1734), .Y(n1617)
);
OAI31X1TS U2882 ( .A0(n1618), .A1(n3118), .A2(n1617), .B0(n1616), .Y(
mult_x_69_n702) );
OAI22X1TS U2883 ( .A0(n2478), .A1(n2111), .B0(n1007), .B1(n1730), .Y(n1622)
);
OAI22X1TS U2884 ( .A0(n1005), .A1(n955), .B0(n986), .B1(n2809), .Y(n1621) );
OAI21XLTS U2885 ( .A0(n1622), .A1(n1621), .B0(n1619), .Y(n1620) );
OAI31X1TS U2886 ( .A0(n1622), .A1(n2485), .A2(n1621), .B0(n1620), .Y(
mult_x_69_n701) );
OAI22X1TS U2887 ( .A0(n1066), .A1(n1094), .B0(n1010), .B1(n2688), .Y(n1625)
);
OAI22X1TS U2888 ( .A0(n2462), .A1(n1001), .B0(n3222), .B1(n992), .Y(n1624)
);
OAI21XLTS U2889 ( .A0(n1625), .A1(n1624), .B0(n3069), .Y(n1623) );
OAI31X1TS U2890 ( .A0(n1625), .A1(n2261), .A2(n1624), .B0(n1623), .Y(
mult_x_69_n653) );
OAI22X1TS U2891 ( .A0(n1067), .A1(n1003), .B0(n3230), .B1(n986), .Y(n1628)
);
CLKBUFX3TS U2892 ( .A(n3229), .Y(n2752) );
OAI22X1TS U2893 ( .A0(n2752), .A1(n1096), .B0(n1008), .B1(n2668), .Y(n1627)
);
OAI21XLTS U2894 ( .A0(n1628), .A1(n1627), .B0(n2482), .Y(n1626) );
OAI31X1TS U2895 ( .A0(n1628), .A1(n3118), .A2(n1627), .B0(n1626), .Y(
mult_x_69_n709) );
OAI22X1TS U2896 ( .A0(n3220), .A1(n989), .B0(n994), .B1(n921), .Y(n1633) );
CMPR32X2TS U2897 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MY[19]), .C(n1629),
.CO(n1594), .S(n1630) );
INVX2TS U2898 ( .A(n1630), .Y(n2240) );
OAI22X1TS U2899 ( .A0(n910), .A1(n1098), .B0(n1013), .B1(n2240), .Y(n1632)
);
OAI21XLTS U2900 ( .A0(n1633), .A1(n1632), .B0(n2472), .Y(n1631) );
OAI31X1TS U2901 ( .A0(n1633), .A1(n2475), .A2(n1632), .B0(n1631), .Y(
mult_x_69_n758) );
OAI22X1TS U2902 ( .A0(n1002), .A1(n3225), .B0(n992), .B1(n2722), .Y(n1636)
);
OAI22X1TS U2903 ( .A0(n2318), .A1(n2772), .B0(n1011), .B1(n2251), .Y(n1635)
);
OAI31X1TS U2904 ( .A0(n1636), .A1(n2199), .A2(n1635), .B0(n1634), .Y(
mult_x_69_n661) );
INVX2TS U2905 ( .A(n2663), .Y(n2664) );
OR2X1TS U2906 ( .A(FPSENCOS_d_ff_Xn[28]), .B(n2664), .Y(
FPSENCOS_first_mux_X[28]) );
AOI222X1TS U2907 ( .A0(n2837), .A1(Data_2[30]), .B0(n2836), .B1(
FPSENCOS_d_ff3_sh_x_out[30]), .C0(FPSENCOS_d_ff3_sh_y_out[30]), .C1(
n2835), .Y(n1637) );
INVX2TS U2908 ( .A(n1637), .Y(add_subt_data2[30]) );
OAI22X1TS U2909 ( .A0(n1638), .A1(n956), .B0(FPADDSUB_Raw_mant_NRM_SWR[0]),
.B1(n963), .Y(n2599) );
NAND2BX2TS U2910 ( .AN(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n1837) );
NOR2BX4TS U2911 ( .AN(n949), .B(FPADDSUB_shift_value_SHT2_EWR[4]), .Y(n2581)
);
AOI22X1TS U2912 ( .A0(n1990), .A1(FPADDSUB_Data_array_SWR[42]), .B0(n2581),
.B1(FPADDSUB_Data_array_SWR[30]), .Y(n1643) );
NAND2X1TS U2913 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(n3206), .Y(n1836)
);
AOI22X1TS U2914 ( .A0(n959), .A1(FPADDSUB_Data_array_SWR[34]), .B0(n962),
.B1(FPADDSUB_Data_array_SWR[38]), .Y(n1642) );
NOR2X4TS U2915 ( .A(n3078), .B(n2570), .Y(n2003) );
AOI21X1TS U2916 ( .A0(n3078), .A1(n1703), .B0(n2003), .Y(n1644) );
OAI21X1TS U2917 ( .A0(n1705), .A1(n2006), .B0(n1644), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[4]) );
OAI21XLTS U2918 ( .A0(n1837), .A1(n3207), .B0(n1653), .Y(n1645) );
NOR2BX2TS U2919 ( .AN(FPADDSUB_bit_shift_SHT2), .B(n949), .Y(n1835) );
AOI22X1TS U2920 ( .A0(n959), .A1(FPADDSUB_Data_array_SWR[36]), .B0(
FPADDSUB_Data_array_SWR[32]), .B1(n1102), .Y(n1647) );
AOI22X1TS U2921 ( .A0(FPADDSUB_Data_array_SWR[44]), .A1(n1990), .B0(
FPADDSUB_Data_array_SWR[40]), .B1(n962), .Y(n1646) );
AOI21X1TS U2922 ( .A0(n3078), .A1(n2001), .B0(n2003), .Y(n1648) );
OAI21X1TS U2923 ( .A0(n1032), .A1(n2006), .B0(n1648), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[6]) );
AOI22X1TS U2924 ( .A0(n1990), .A1(FPADDSUB_Data_array_SWR[45]), .B0(n960),
.B1(FPADDSUB_Data_array_SWR[37]), .Y(n1651) );
AOI22X1TS U2925 ( .A0(n961), .A1(FPADDSUB_Data_array_SWR[41]), .B0(n2581),
.B1(FPADDSUB_Data_array_SWR[33]), .Y(n1650) );
AOI21X1TS U2926 ( .A0(n3078), .A1(n2016), .B0(n2003), .Y(n1652) );
OAI21X1TS U2927 ( .A0(n2019), .A1(n2006), .B0(n1652), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[7]) );
OAI22X1TS U2928 ( .A0(n1837), .A1(n3234), .B0(n1836), .B1(n3108), .Y(n1654)
);
AOI22X1TS U2929 ( .A0(n1990), .A1(FPADDSUB_Data_array_SWR[46]), .B0(n962),
.B1(FPADDSUB_Data_array_SWR[42]), .Y(n1656) );
AOI22X1TS U2930 ( .A0(n959), .A1(FPADDSUB_Data_array_SWR[38]), .B0(n2581),
.B1(FPADDSUB_Data_array_SWR[34]), .Y(n1655) );
AOI21X1TS U2931 ( .A0(FPADDSUB_left_right_SHT2), .A1(n1995), .B0(n2015), .Y(
n1657) );
OAI21X1TS U2932 ( .A0(n1997), .A1(n2018), .B0(n1657), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[17]) );
AOI22X1TS U2933 ( .A0(n1990), .A1(FPADDSUB_Data_array_SWR[39]), .B0(n960),
.B1(FPADDSUB_Data_array_SWR[31]), .Y(n1659) );
AOI22X1TS U2934 ( .A0(n961), .A1(FPADDSUB_Data_array_SWR[35]), .B0(n2581),
.B1(FPADDSUB_Data_array_SWR[27]), .Y(n1658) );
OAI211X1TS U2935 ( .A0(n1997), .A1(n922), .B0(n1659), .C0(n1658), .Y(n1866)
);
AOI21X1TS U2936 ( .A0(n1110), .A1(n1866), .B0(n2015), .Y(n1660) );
OAI21X1TS U2937 ( .A0(n1868), .A1(n2018), .B0(n1660), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[24]) );
NOR3X1TS U2938 ( .A(FPMULT_FS_Module_state_reg[1]), .B(n3192), .C(n1661),
.Y(FPMULT_FSM_adder_round_norm_load) );
NAND3XLTS U2939 ( .A(n923), .B(n3033), .C(n3124), .Y(n2642) );
NOR2BX1TS U2940 ( .AN(FPMULT_P_Sgf[47]), .B(n2642), .Y(n2530) );
NOR2X1TS U2941 ( .A(n107), .B(FPMULT_FSM_adder_round_norm_load), .Y(n2531)
);
OAI21XLTS U2942 ( .A0(n2530), .A1(n3237), .B0(n2531), .Y(n830) );
AOI222X4TS U2943 ( .A0(n966), .A1(FPADDSUB_DmP_mant_SHT1_SW[21]), .B0(n1107),
.B1(FPADDSUB_Raw_mant_NRM_SWR[2]), .C0(FPADDSUB_Raw_mant_NRM_SWR[23]),
.C1(n953), .Y(n2598) );
OAI22X1TS U2944 ( .A0(n965), .A1(FPADDSUB_DmP_mant_SHT1_SW[20]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[3]), .B1(n963), .Y(n1662) );
OAI222X4TS U2945 ( .A0(n957), .A1(FPADDSUB_Raw_mant_NRM_SWR[24]), .B0(n963),
.B1(FPADDSUB_Raw_mant_NRM_SWR[1]), .C0(FPADDSUB_DmP_mant_SHT1_SW[22]),
.C1(n965), .Y(n3022) );
OAI222X4TS U2946 ( .A0(n957), .A1(FPADDSUB_Raw_mant_NRM_SWR[21]), .B0(n964),
.B1(FPADDSUB_Raw_mant_NRM_SWR[4]), .C0(FPADDSUB_DmP_mant_SHT1_SW[19]),
.C1(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n2053) );
OAI22X1TS U2947 ( .A0(n3022), .A1(n968), .B0(n3021), .B1(n2053), .Y(n1663)
);
AOI21X1TS U2948 ( .A0(n2036), .A1(n2056), .B0(n1663), .Y(n1664) );
OAI21XLTS U2949 ( .A0(n2598), .A1(n971), .B0(n1664), .Y(
FPADDSUB_Data_array_SWR[21]) );
OAI222X4TS U2950 ( .A0(n958), .A1(FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(n964),
.B1(n1665), .C0(FPADDSUB_DmP_mant_SHT1_SW[18]), .C1(n1111), .Y(n2059)
);
OAI22X1TS U2951 ( .A0(n2598), .A1(n968), .B0(n974), .B1(n2053), .Y(n1666) );
AOI21X1TS U2952 ( .A0(n2045), .A1(n2056), .B0(n1666), .Y(n1667) );
OAI22X1TS U2953 ( .A0(n2468), .A1(n1047), .B0(n1014), .B1(n1034), .Y(n1670)
);
OAI22X1TS U2954 ( .A0(n996), .A1(n2252), .B0(n988), .B1(n2756), .Y(n1669) );
OAI21XLTS U2955 ( .A0(n1670), .A1(n1669), .B0(n3211), .Y(n1668) );
OAI31X1TS U2956 ( .A0(n1670), .A1(n2475), .A2(n1669), .B0(n1668), .Y(
mult_x_69_n771) );
NOR2X1TS U2957 ( .A(FPADDSUB_DmP_mant_SFG_SWR[4]), .B(FPADDSUB_DMP_SFG[2]),
.Y(n1674) );
INVX2TS U2958 ( .A(FPADDSUB_OP_FLAG_SFG), .Y(n2991) );
INVX2TS U2959 ( .A(n2991), .Y(n2997) );
NAND2X1TS U2960 ( .A(n3172), .B(FPADDSUB_DmP_mant_SFG_SWR[2]), .Y(n2076) );
NAND2X1TS U2961 ( .A(FPADDSUB_DmP_mant_SFG_SWR[3]), .B(FPADDSUB_DMP_SFG[1]),
.Y(n2648) );
NAND2X1TS U2962 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DmP_mant_SFG_SWR[2]),
.Y(n1671) );
AOI2BB2X1TS U2963 ( .B0(n2648), .B1(n1671), .A0N(
FPADDSUB_DmP_mant_SFG_SWR[3]), .A1N(FPADDSUB_DMP_SFG[1]), .Y(n1692) );
INVX2TS U2964 ( .A(n2991), .Y(n2985) );
AOI2BB2X1TS U2965 ( .B0(n2997), .B1(n1691), .A0N(n1692), .A1N(n2985), .Y(
n1673) );
OAI21XLTS U2966 ( .A0(n1674), .A1(n1693), .B0(n1673), .Y(n1672) );
OAI31X1TS U2967 ( .A0(n1674), .A1(n1673), .A2(n1693), .B0(n1672), .Y(
FPADDSUB_Raw_mant_SGF[4]) );
INVX2TS U2968 ( .A(n1675), .Y(n1684) );
INVX2TS U2969 ( .A(n1677), .Y(n1678) );
AOI22X1TS U2970 ( .A0(n1681), .A1(n1680), .B0(n1679), .B1(n1678), .Y(n1682)
);
OAI211X1TS U2971 ( .A0(n1685), .A1(n1684), .B0(n1683), .C0(n1682), .Y(
FPADDSUB_LZD_raw_out_EWR[2]) );
AOI22X1TS U2972 ( .A0(n961), .A1(FPADDSUB_Data_array_SWR[36]), .B0(n2581),
.B1(FPADDSUB_Data_array_SWR[28]), .Y(n1687) );
AOI22X1TS U2973 ( .A0(n1990), .A1(FPADDSUB_Data_array_SWR[40]), .B0(n960),
.B1(FPADDSUB_Data_array_SWR[32]), .Y(n1686) );
OAI211X1TS U2974 ( .A0(n2019), .A1(n950), .B0(n1687), .C0(n1686), .Y(n2004)
);
AOI21X1TS U2975 ( .A0(n1110), .A1(n2004), .B0(n2015), .Y(n1688) );
OAI21X1TS U2976 ( .A0(n1025), .A1(n2018), .B0(n1688), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[23]) );
OAI22X1TS U2977 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[25]), .A1(n957), .B0(
FPADDSUB_Raw_mant_NRM_SWR[0]), .B1(n963), .Y(n3023) );
OAI22X1TS U2978 ( .A0(n3022), .A1(n970), .B0(n968), .B1(n3023), .Y(n1689) );
AOI21X1TS U2979 ( .A0(n2064), .A1(n2056), .B0(n1689), .Y(n1690) );
OAI21XLTS U2980 ( .A0(n2598), .A1(n975), .B0(n1690), .Y(
FPADDSUB_Data_array_SWR[22]) );
NOR2X1TS U2981 ( .A(FPADDSUB_DmP_mant_SFG_SWR[6]), .B(FPADDSUB_DMP_SFG[4]),
.Y(n1696) );
NAND2X1TS U2982 ( .A(FPADDSUB_DmP_mant_SFG_SWR[5]), .B(FPADDSUB_DMP_SFG[3]),
.Y(n2920) );
OAI22X1TS U2983 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[4]), .A1(FPADDSUB_DMP_SFG[2]), .B0(n1693), .B1(n1692), .Y(n2919) );
AOI2BB2X1TS U2984 ( .B0(n2920), .B1(n2919), .A0N(
FPADDSUB_DmP_mant_SFG_SWR[5]), .A1N(FPADDSUB_DMP_SFG[3]), .Y(n2007) );
AOI2BB2X1TS U2985 ( .B0(n2997), .B1(n2009), .A0N(n2007), .A1N(n2985), .Y(
n1695) );
OAI21XLTS U2986 ( .A0(n1696), .A1(n2008), .B0(n1695), .Y(n1694) );
OAI31X1TS U2987 ( .A0(n1696), .A1(n1695), .A2(n2008), .B0(n1694), .Y(
FPADDSUB_Raw_mant_SGF[6]) );
AOI22X1TS U2988 ( .A0(n1990), .A1(FPADDSUB_Data_array_SWR[41]), .B0(n2581),
.B1(FPADDSUB_Data_array_SWR[29]), .Y(n1698) );
AOI22X1TS U2989 ( .A0(n959), .A1(FPADDSUB_Data_array_SWR[33]), .B0(n962),
.B1(FPADDSUB_Data_array_SWR[37]), .Y(n1697) );
OAI211X1TS U2990 ( .A0(n1032), .A1(n950), .B0(n1698), .C0(n1697), .Y(n1987)
);
AOI21X1TS U2991 ( .A0(n1110), .A1(n1987), .B0(n2015), .Y(n1699) );
OAI21X1TS U2992 ( .A0(n1989), .A1(n2018), .B0(n1699), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[22]) );
AOI22X1TS U2993 ( .A0(n1990), .A1(FPADDSUB_Data_array_SWR[43]), .B0(n962),
.B1(FPADDSUB_Data_array_SWR[39]), .Y(n1701) );
AOI22X1TS U2994 ( .A0(n959), .A1(FPADDSUB_Data_array_SWR[35]), .B0(n2581),
.B1(FPADDSUB_Data_array_SWR[31]), .Y(n1700) );
OAI211X1TS U2995 ( .A0(n1705), .A1(n950), .B0(n1701), .C0(n1700), .Y(n1984)
);
AOI21X1TS U2996 ( .A0(n1110), .A1(n1984), .B0(n2015), .Y(n1702) );
OAI21X1TS U2997 ( .A0(n1986), .A1(n2018), .B0(n1702), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[20]) );
AOI21X1TS U2998 ( .A0(n1110), .A1(n1703), .B0(n2015), .Y(n1704) );
OAI21X1TS U2999 ( .A0(n1705), .A1(n2018), .B0(n1704), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[21]) );
NAND2X1TS U3000 ( .A(n3169), .B(n3097), .Y(n2618) );
OAI21XLTS U3001 ( .A0(n3097), .A1(n3169), .B0(n2618), .Y(
FPMULT_Adder_M_result_A_adder[1]) );
OAI21XLTS U3002 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n3201), .B0(n2659),
.Y(FPSENCOS_sh_exp_y[0]) );
INVX2TS U3003 ( .A(mult_x_69_n181), .Y(n2071) );
OAI21XLTS U3004 ( .A0(n973), .A1(n955), .B0(n2771), .Y(n1706) );
AOI21X1TS U3005 ( .A0(n1707), .A1(n944), .B0(n1706), .Y(n2073) );
INVX2TS U3006 ( .A(n1708), .Y(n2070) );
INVX2TS U3007 ( .A(mult_x_69_n184), .Y(n1828) );
INVX2TS U3008 ( .A(mult_x_69_n182), .Y(n1827) );
INVX2TS U3009 ( .A(mult_x_69_n185), .Y(n1957) );
INVX2TS U3010 ( .A(mult_x_69_n188), .Y(n1956) );
INVX2TS U3011 ( .A(mult_x_69_n189), .Y(n1961) );
INVX2TS U3012 ( .A(mult_x_69_n192), .Y(n1960) );
INVX2TS U3013 ( .A(mult_x_69_n193), .Y(n1965) );
AOI22X1TS U3014 ( .A0(n1710), .A1(FPMULT_Op_MY[22]), .B0(n1709), .B1(n1821),
.Y(n1711) );
XOR2X1TS U3015 ( .A(n3068), .B(n1712), .Y(n1964) );
INVX2TS U3016 ( .A(mult_x_69_n198), .Y(n1969) );
INVX2TS U3017 ( .A(mult_x_69_n203), .Y(n1968) );
INVX2TS U3018 ( .A(mult_x_69_n204), .Y(n1973) );
INVX2TS U3019 ( .A(mult_x_69_n210), .Y(n1909) );
AOI22X1TS U3020 ( .A0(n2256), .A1(FPMULT_Op_MY[22]), .B0(n1713), .B1(n1821),
.Y(n1714) );
XOR2X1TS U3021 ( .A(n2261), .B(n1715), .Y(n1908) );
INVX2TS U3022 ( .A(mult_x_69_n216), .Y(n1913) );
INVX2TS U3023 ( .A(mult_x_69_n223), .Y(n1917) );
INVX2TS U3024 ( .A(mult_x_69_n229), .Y(n1916) );
INVX2TS U3025 ( .A(mult_x_69_n230), .Y(n1921) );
AOI22X1TS U3026 ( .A0(n1717), .A1(FPMULT_Op_MY[22]), .B0(n1716), .B1(n1821),
.Y(n1718) );
OAI211XLTS U3027 ( .A0(n2263), .A1(n918), .B0(n1718), .C0(n1100), .Y(n1719)
);
XOR2X1TS U3028 ( .A(n3212), .B(n1719), .Y(n1920) );
INVX2TS U3029 ( .A(mult_x_69_n238), .Y(n1925) );
INVX2TS U3030 ( .A(mult_x_69_n246), .Y(n1924) );
INVX2TS U3031 ( .A(mult_x_69_n247), .Y(n1929) );
INVX2TS U3032 ( .A(mult_x_69_n255), .Y(n1928) );
INVX2TS U3033 ( .A(mult_x_69_n256), .Y(n1933) );
INVX2TS U3034 ( .A(mult_x_69_n265), .Y(n1937) );
INVX2TS U3035 ( .A(mult_x_69_n274), .Y(n1936) );
INVX2TS U3036 ( .A(mult_x_69_n275), .Y(n1897) );
INVX2TS U3037 ( .A(mult_x_69_n284), .Y(n1896) );
INVX2TS U3038 ( .A(mult_x_69_n285), .Y(n1941) );
CLKBUFX3TS U3039 ( .A(n1720), .Y(n2750) );
AOI22X1TS U3040 ( .A0(n1062), .A1(FPMULT_Op_MY[22]), .B0(n1721), .B1(n1821),
.Y(n1722) );
XOR2X1TS U3041 ( .A(n2725), .B(n1723), .Y(n1940) );
INVX2TS U3042 ( .A(mult_x_69_n306), .Y(n1944) );
INVX2TS U3043 ( .A(mult_x_69_n307), .Y(n1901) );
INVX2TS U3044 ( .A(mult_x_69_n317), .Y(n1900) );
INVX2TS U3045 ( .A(mult_x_69_n318), .Y(n1949) );
AOI22X1TS U3046 ( .A0(n2470), .A1(FPMULT_Op_MY[22]), .B0(n1724), .B1(n1821),
.Y(n1725) );
XOR2X1TS U3047 ( .A(n2472), .B(n1726), .Y(n1948) );
INVX2TS U3048 ( .A(mult_x_69_n339), .Y(n1905) );
INVX2TS U3049 ( .A(mult_x_69_n329), .Y(n1904) );
INVX2TS U3050 ( .A(mult_x_69_n340), .Y(n1953) );
INVX2TS U3051 ( .A(mult_x_69_n351), .Y(n1833) );
NOR2X2TS U3052 ( .A(n3107), .B(FPMULT_Op_MX[0]), .Y(n1820) );
OAI22X1TS U3053 ( .A0(n1785), .A1(FPMULT_Op_MX[1]), .B0(n3107), .B1(n1817),
.Y(n1727) );
AOI22X1TS U3054 ( .A0(n1820), .A1(FPMULT_Op_MY[22]), .B0(n1816), .B1(n1821),
.Y(n1728) );
OAI211XLTS U3055 ( .A0(n947), .A1(n1027), .B0(n1728), .C0(n1093), .Y(n1729)
);
XOR2X1TS U3056 ( .A(n1785), .B(n1729), .Y(n1832) );
INVX2TS U3057 ( .A(mult_x_69_n362), .Y(n2383) );
OAI22X1TS U3058 ( .A0(n1092), .A1(n955), .B0(n983), .B1(n1730), .Y(n1733) );
OAI22X1TS U3059 ( .A0(n1054), .A1(n1027), .B0(n946), .B1(n2111), .Y(n1732)
);
OAI31X1TS U3060 ( .A0(n1733), .A1(FPMULT_Op_MX[2]), .A2(n1732), .B0(n1731),
.Y(n2382) );
INVX2TS U3061 ( .A(mult_x_69_n373), .Y(n2406) );
AOI21X1TS U3062 ( .A0(FPMULT_Op_MY[19]), .A1(n952), .B0(n3210), .Y(n1736) );
MXI2X1TS U3063 ( .A(n1736), .B(n1785), .S0(n1735), .Y(n2405) );
INVX2TS U3064 ( .A(mult_x_69_n384), .Y(n2421) );
OAI22X1TS U3065 ( .A0(n1812), .A1(n1071), .B0(n946), .B1(n3220), .Y(n1739)
);
OAI22X1TS U3066 ( .A0(n1093), .A1(n919), .B0(n984), .B1(n2112), .Y(n1738) );
OAI21XLTS U3067 ( .A0(n1739), .A1(n1738), .B0(n1877), .Y(n1737) );
OAI31X1TS U3068 ( .A0(n1739), .A1(FPMULT_Op_MX[2]), .A2(n1738), .B0(n1737),
.Y(n2420) );
INVX2TS U3069 ( .A(mult_x_69_n394), .Y(n2375) );
OAI22X1TS U3070 ( .A0(n2191), .A1(n947), .B0(n1812), .B1(n1040), .Y(n1742)
);
OAI22X1TS U3071 ( .A0(n1091), .A1(n1072), .B0(n983), .B1(n2240), .Y(n1741)
);
OAI21XLTS U3072 ( .A0(n1742), .A1(n1741), .B0(n1817), .Y(n1740) );
OAI31X1TS U3073 ( .A0(n1742), .A1(n1877), .A2(n1741), .B0(n1740), .Y(n2374)
);
INVX2TS U3074 ( .A(mult_x_69_n404), .Y(n2429) );
OAI22X1TS U3075 ( .A0(n3220), .A1(n1091), .B0(n2244), .B1(n983), .Y(n1745)
);
OAI22X1TS U3076 ( .A0(n2191), .A1(n1812), .B0(n3221), .B1(n947), .Y(n1744)
);
OAI31X1TS U3077 ( .A0(n1745), .A1(FPMULT_Op_MX[2]), .A2(n1744), .B0(n1743),
.Y(n2428) );
INVX2TS U3078 ( .A(mult_x_69_n414), .Y(n2395) );
AOI21X1TS U3079 ( .A0(n951), .A1(FPMULT_Op_MY[15]), .B0(n1785), .Y(n1747) );
OAI222X1TS U3080 ( .A0(n1054), .A1(n2690), .B0(n1093), .B1(n2191), .C0(n982),
.C1(n2699), .Y(n1746) );
MXI2X1TS U3081 ( .A(n1747), .B(n2321), .S0(n1746), .Y(n2394) );
INVX2TS U3082 ( .A(mult_x_69_n422), .Y(n2399) );
AOI21X1TS U3083 ( .A0(n951), .A1(FPMULT_Op_MY[14]), .B0(n1785), .Y(n1749) );
OAI222X1TS U3084 ( .A0(n2690), .A1(n1091), .B0(n2469), .B1(n1054), .C0(n982),
.C1(n2688), .Y(n1748) );
MXI2X1TS U3085 ( .A(n1749), .B(n1785), .S0(n1748), .Y(n2398) );
INVX2TS U3086 ( .A(mult_x_69_n430), .Y(n2371) );
OAI22X1TS U3087 ( .A0(n1092), .A1(n3222), .B0(n984), .B1(n2679), .Y(n1752)
);
OAI22X1TS U3088 ( .A0(n1812), .A1(n1067), .B0(n946), .B1(n3230), .Y(n1751)
);
OAI21XLTS U3089 ( .A0(n1752), .A1(n1751), .B0(n1817), .Y(n1750) );
OAI31X1TS U3090 ( .A0(n1752), .A1(n1817), .A2(n1751), .B0(n1750), .Y(n2370)
);
INVX2TS U3091 ( .A(mult_x_69_n438), .Y(n2343) );
AOI21X1TS U3092 ( .A0(n951), .A1(FPMULT_Op_MY[12]), .B0(n3210), .Y(n1754) );
OAI222X1TS U3093 ( .A0(n1091), .A1(n1067), .B0(n3230), .B1(n1055), .C0(n982),
.C1(n2668), .Y(n1753) );
MXI2X1TS U3094 ( .A(n1754), .B(n2321), .S0(n1753), .Y(n2342) );
INVX2TS U3095 ( .A(mult_x_69_n445), .Y(n2379) );
OAI22X1TS U3096 ( .A0(n1812), .A1(n3229), .B0(n946), .B1(n2714), .Y(n1757)
);
OAI22X1TS U3097 ( .A0(n1093), .A1(n1033), .B0(n983), .B1(n2684), .Y(n1756)
);
OAI21XLTS U3098 ( .A0(n1757), .A1(n1756), .B0(n1817), .Y(n1755) );
OAI31X1TS U3099 ( .A0(n1757), .A1(n1877), .A2(n1756), .B0(n1755), .Y(n2378)
);
INVX2TS U3100 ( .A(mult_x_69_n452), .Y(n2339) );
AOI21X1TS U3101 ( .A0(n951), .A1(FPMULT_Op_MY[10]), .B0(n3210), .Y(n1761) );
OAI21X4TS U3102 ( .A0(FPMULT_Op_MY[12]), .A1(n1759), .B0(n1758), .Y(n2749)
);
OAI222X1TS U3103 ( .A0(n1092), .A1(n2481), .B0(n2714), .B1(n1055), .C0(n982),
.C1(n2749), .Y(n1760) );
MXI2X1TS U3104 ( .A(n1761), .B(n2321), .S0(n1760), .Y(n2338) );
INVX2TS U3105 ( .A(mult_x_69_n459), .Y(n2359) );
INVX2TS U3106 ( .A(mult_x_69_n464), .Y(n2335) );
OAI22X1TS U3107 ( .A0(n1091), .A1(n3224), .B0(n984), .B1(n1035), .Y(n1764)
);
OAI22X1TS U3108 ( .A0(n1812), .A1(n3218), .B0(n946), .B1(n2719), .Y(n1763)
);
OAI31X1TS U3109 ( .A0(n1764), .A1(n1817), .A2(n1763), .B0(n1762), .Y(n2334)
);
INVX2TS U3110 ( .A(mult_x_69_n469), .Y(n2355) );
AOI21X1TS U3111 ( .A0(n951), .A1(FPMULT_Op_MY[4]), .B0(n3210), .Y(n1766) );
MXI2X1TS U3112 ( .A(n1766), .B(n2321), .S0(n1765), .Y(n2363) );
OAI22X1TS U3113 ( .A0(n1055), .A1(n1069), .B0(n946), .B1(n1767), .Y(n1769)
);
OAI22X1TS U3114 ( .A0(n1092), .A1(n3231), .B0(n983), .B1(n2736), .Y(n1768)
);
NOR2XLTS U3115 ( .A(n1769), .B(n1768), .Y(n1776) );
NOR2XLTS U3116 ( .A(n3168), .B(n2731), .Y(n1773) );
NAND2BXLTS U3117 ( .AN(n1773), .B(n1772), .Y(n1774) );
INVX2TS U3118 ( .A(n1774), .Y(n1775) );
NAND2X1TS U3119 ( .A(n1776), .B(n1775), .Y(n2348) );
OAI22X1TS U3120 ( .A0(n1054), .A1(n3231), .B0(n947), .B1(n1070), .Y(n1777)
);
NAND2X1TS U3121 ( .A(n1877), .B(n1782), .Y(n1779) );
NOR2X1TS U3122 ( .A(n2348), .B(n1779), .Y(n2411) );
INVX2TS U3123 ( .A(n2348), .Y(n1781) );
NAND2X1TS U3124 ( .A(n1782), .B(n1785), .Y(n1780) );
INVX2TS U3125 ( .A(n2409), .Y(n1783) );
AOI21X1TS U3126 ( .A0(n952), .A1(FPMULT_Op_MY[2]), .B0(n3210), .Y(n1786) );
OAI222X1TS U3127 ( .A0(n2727), .A1(n984), .B0(n2706), .B1(n1054), .C0(n1047),
.C1(n1092), .Y(n1784) );
MXI2X1TS U3128 ( .A(n1786), .B(n2321), .S0(n1784), .Y(n2424) );
NOR3XLTS U3129 ( .A(n2777), .B(n1787), .C(n3217), .Y(n1790) );
AO21XLTS U3130 ( .A0(n1790), .A1(n1789), .B0(n1788), .Y(n2423) );
AOI21X1TS U3131 ( .A0(n952), .A1(FPMULT_Op_MY[3]), .B0(n1785), .Y(n1792) );
MXI2X1TS U3132 ( .A(n1792), .B(n2321), .S0(n1791), .Y(n2413) );
AO21XLTS U3133 ( .A0(n1795), .A1(n1794), .B0(n1793), .Y(n2412) );
AO21XLTS U3134 ( .A0(n1798), .A1(n1797), .B0(n1796), .Y(n2361) );
OAI22X1TS U3135 ( .A0(n1055), .A1(n2772), .B0(n947), .B1(n2770), .Y(n1801)
);
OAI22X1TS U3136 ( .A0(n1093), .A1(n3226), .B0(n984), .B1(n2694), .Y(n1800)
);
OAI21XLTS U3137 ( .A0(n1801), .A1(n1800), .B0(n1817), .Y(n1799) );
OAI31X1TS U3138 ( .A0(n1801), .A1(FPMULT_Op_MX[2]), .A2(n1800), .B0(n1799),
.Y(n2350) );
CMPR32X2TS U3139 ( .A(n1804), .B(n1803), .C(n1802), .CO(n1808), .S(n2349) );
AOI21X1TS U3140 ( .A0(n952), .A1(FPMULT_Op_MY[6]), .B0(n3210), .Y(n1806) );
MXI2X1TS U3141 ( .A(n1806), .B(n2321), .S0(n1805), .Y(n2390) );
CMPR32X2TS U3142 ( .A(n1809), .B(n1808), .C(n1807), .CO(n1452), .S(n2389) );
AOI21X1TS U3143 ( .A0(FPMULT_Op_MY[7]), .A1(n952), .B0(n1785), .Y(n1811) );
OAI222X1TS U3144 ( .A0(n1093), .A1(n2744), .B0(n2181), .B1(n1054), .C0(n2721), .C1(n983), .Y(n1810) );
MXI2X1TS U3145 ( .A(n1811), .B(n2321), .S0(n1810), .Y(n2353) );
AOI21X1TS U3146 ( .A0(n952), .A1(FPMULT_Op_MY[9]), .B0(n3210), .Y(n1814) );
MXI2X1TS U3147 ( .A(n1814), .B(n2321), .S0(n1813), .Y(n2357) );
OAI22X1TS U3148 ( .A0(n947), .A1(n955), .B0(n982), .B1(n1815), .Y(n1819) );
OAI21XLTS U3149 ( .A0(n1820), .A1(n1819), .B0(n1817), .Y(n1818) );
OAI31X1TS U3150 ( .A0(n1820), .A1(n1877), .A2(n1819), .B0(n1818), .Y(n1951)
);
AOI22X1TS U3151 ( .A0(n2479), .A1(FPMULT_Op_MY[22]), .B0(n1822), .B1(n1821),
.Y(n1823) );
XOR2X1TS U3152 ( .A(n2485), .B(n1824), .Y(n1931) );
INVX2TS U3153 ( .A(n1825), .Y(FPMULT_Sgf_operation_Result[45]) );
NOR2XLTS U3154 ( .A(n3047), .B(FPSENCOS_ITER_CONT_N4), .Y(
FPSENCOS_data_out_LUT[25]) );
CMPR32X2TS U3155 ( .A(n1828), .B(n1827), .C(n1826), .CO(n2069), .S(n1829) );
INVX2TS U3156 ( .A(n1829), .Y(FPMULT_Sgf_operation_Result[44]) );
INVX2TS U3157 ( .A(n2663), .Y(n1864) );
INVX2TS U3158 ( .A(n1830), .Y(n856) );
CMPR32X2TS U3159 ( .A(n1833), .B(n1832), .C(n1831), .CO(n1952), .S(n1834) );
INVX2TS U3160 ( .A(n1834), .Y(FPMULT_Sgf_operation_Result[23]) );
OR2X1TS U3161 ( .A(FPSENCOS_d_ff_Xn[25]), .B(n1864), .Y(
FPSENCOS_first_mux_X[25]) );
OR2X1TS U3162 ( .A(FPSENCOS_d_ff_Xn[26]), .B(n1864), .Y(
FPSENCOS_first_mux_X[26]) );
OAI22X1TS U3163 ( .A0(n1837), .A1(n3233), .B0(n1836), .B1(n3109), .Y(n1838)
);
AOI22X1TS U3164 ( .A0(n1990), .A1(FPADDSUB_Data_array_SWR[38]), .B0(n962),
.B1(FPADDSUB_Data_array_SWR[34]), .Y(n1840) );
AOI22X1TS U3165 ( .A0(n959), .A1(FPADDSUB_Data_array_SWR[30]), .B0(n2581),
.B1(FPADDSUB_Data_array_SWR[26]), .Y(n1839) );
OAI211X1TS U3166 ( .A0(n2000), .A1(n950), .B0(n1840), .C0(n1839), .Y(n1862)
);
AOI21X1TS U3167 ( .A0(n3078), .A1(n1862), .B0(n2003), .Y(n1841) );
OAI21XLTS U3168 ( .A0(n1993), .A1(n2006), .B0(n1841), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[0]) );
AOI22X1TS U3169 ( .A0(FPMULT_FSM_selector_C), .A1(FPMULT_Add_result[23]),
.B0(FPMULT_P_Sgf[46]), .B1(n3122), .Y(n2601) );
AOI22X1TS U3170 ( .A0(n1082), .A1(FPMULT_P_Sgf[45]), .B0(n997), .B1(
FPMULT_Add_result[22]), .Y(n1844) );
AND4X1TS U3171 ( .A(FPMULT_Exp_module_Data_S[6]), .B(
FPMULT_Exp_module_Data_S[2]), .C(FPMULT_Exp_module_Data_S[3]), .D(
FPMULT_Exp_module_Data_S[0]), .Y(n1845) );
AND4X1TS U3172 ( .A(FPMULT_Exp_module_Data_S[1]), .B(
FPMULT_Exp_module_Data_S[4]), .C(FPMULT_Exp_module_Data_S[5]), .D(
n1845), .Y(n1846) );
NOR3XLTS U3173 ( .A(n1846), .B(FPMULT_Exp_module_Data_S[7]), .C(
FPMULT_Exp_module_Data_S[8]), .Y(n3499) );
OR2X1TS U3174 ( .A(FPSENCOS_d_ff_Xn[29]), .B(n2664), .Y(
FPSENCOS_first_mux_X[29]) );
OAI22X1TS U3175 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[14]), .A1(n957), .B0(n965),
.B1(FPADDSUB_DmP_mant_SHT1_SW[12]), .Y(n1847) );
NOR2X1TS U3176 ( .A(n966), .B(n3187), .Y(n1849) );
AOI22X1TS U3177 ( .A0(n1107), .A1(n3111), .B0(n956), .B1(n3187), .Y(n1848)
);
OAI222X4TS U3178 ( .A0(n958), .A1(FPADDSUB_Raw_mant_NRM_SWR[13]), .B0(n964),
.B1(n1849), .C0(FPADDSUB_DmP_mant_SHT1_SW[11]), .C1(n1111), .Y(n2033)
);
OAI22X1TS U3179 ( .A0(n974), .A1(n2028), .B0(n970), .B1(n2033), .Y(n1850) );
AOI21X1TS U3180 ( .A0(n2057), .A1(n2063), .B0(n1850), .Y(n1851) );
OAI21XLTS U3181 ( .A0(n1859), .A1(n1080), .B0(n1851), .Y(
FPADDSUB_Data_array_SWR[11]) );
OAI222X4TS U3182 ( .A0(n958), .A1(FPADDSUB_Raw_mant_NRM_SWR[8]), .B0(n964),
.B1(FPADDSUB_Raw_mant_NRM_SWR[17]), .C0(FPADDSUB_DmP_mant_SHT1_SW[6]),
.C1(n1111), .Y(n1979) );
AOI22X1TS U3183 ( .A0(n956), .A1(FPADDSUB_Raw_mant_NRM_SWR[10]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[8]), .B1(n966), .Y(n1852) );
OAI2BB1X1TS U3184 ( .A0N(n1107), .A1N(FPADDSUB_Raw_mant_NRM_SWR[15]), .B0(
n1852), .Y(n1977) );
OAI222X4TS U3185 ( .A0(n958), .A1(FPADDSUB_Raw_mant_NRM_SWR[9]), .B0(n964),
.B1(FPADDSUB_Raw_mant_NRM_SWR[16]), .C0(FPADDSUB_DmP_mant_SHT1_SW[7]),
.C1(n1111), .Y(n1975) );
OAI22X1TS U3186 ( .A0(n1859), .A1(n969), .B0(n974), .B1(n1975), .Y(n1853) );
AOI21X1TS U3187 ( .A0(n2045), .A1(n1977), .B0(n1853), .Y(n1854) );
OAI22X1TS U3188 ( .A0(n3021), .A1(n1975), .B0(n968), .B1(n2028), .Y(n1855)
);
AOI21X1TS U3189 ( .A0(n2036), .A1(n1977), .B0(n1855), .Y(n1856) );
OAI21XLTS U3190 ( .A0(n1859), .A1(n971), .B0(n1856), .Y(
FPADDSUB_Data_array_SWR[9]) );
OAI22X1TS U3191 ( .A0(n971), .A1(n2028), .B0(n968), .B1(n2033), .Y(n1857) );
AOI21X1TS U3192 ( .A0(n2064), .A1(n1977), .B0(n1857), .Y(n1858) );
OAI21XLTS U3193 ( .A0(n1859), .A1(n975), .B0(n1858), .Y(
FPADDSUB_Data_array_SWR[10]) );
INVX2TS U3194 ( .A(enab_cont_iter), .Y(n1861) );
OAI21XLTS U3195 ( .A0(n2068), .A1(n1861), .B0(n1860), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]) );
INVX2TS U3196 ( .A(n2663), .Y(n1865) );
OR2X1TS U3197 ( .A(FPSENCOS_d_ff_Xn[7]), .B(n1865), .Y(
FPSENCOS_first_mux_X[7]) );
OR2X1TS U3198 ( .A(FPSENCOS_d_ff_Xn[10]), .B(n1865), .Y(
FPSENCOS_first_mux_X[10]) );
OR2X1TS U3199 ( .A(FPSENCOS_d_ff_Xn[14]), .B(n1864), .Y(
FPSENCOS_first_mux_X[14]) );
OR2X1TS U3200 ( .A(FPSENCOS_d_ff_Xn[5]), .B(n1865), .Y(
FPSENCOS_first_mux_X[5]) );
OR2X1TS U3201 ( .A(FPSENCOS_d_ff_Xn[19]), .B(n1864), .Y(
FPSENCOS_first_mux_X[19]) );
OR2X1TS U3202 ( .A(FPSENCOS_d_ff_Xn[6]), .B(n1865), .Y(
FPSENCOS_first_mux_X[6]) );
OR2X1TS U3203 ( .A(FPSENCOS_d_ff_Xn[3]), .B(n1865), .Y(
FPSENCOS_first_mux_X[3]) );
AOI21X1TS U3204 ( .A0(n1110), .A1(n1862), .B0(n2015), .Y(n1863) );
OAI21XLTS U3205 ( .A0(n1993), .A1(n2018), .B0(n1863), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[25]) );
OR2X1TS U3206 ( .A(FPSENCOS_d_ff_Xn[1]), .B(n1865), .Y(
FPSENCOS_first_mux_X[1]) );
OR2X1TS U3207 ( .A(FPSENCOS_d_ff_Xn[13]), .B(n1864), .Y(
FPSENCOS_first_mux_X[13]) );
OR2X1TS U3208 ( .A(FPSENCOS_d_ff_Xn[17]), .B(n1864), .Y(
FPSENCOS_first_mux_X[17]) );
OR2X1TS U3209 ( .A(FPSENCOS_d_ff_Xn[16]), .B(n1864), .Y(
FPSENCOS_first_mux_X[16]) );
OR2X1TS U3210 ( .A(FPSENCOS_d_ff_Xn[2]), .B(n1865), .Y(
FPSENCOS_first_mux_X[2]) );
AOI21X1TS U3211 ( .A0(n3078), .A1(n1866), .B0(n2003), .Y(n1867) );
OAI21XLTS U3212 ( .A0(n1868), .A1(n2006), .B0(n1867), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[1]) );
NOR2XLTS U3213 ( .A(FPMULT_Op_MY[21]), .B(n954), .Y(n1870) );
NOR4X1TS U3214 ( .A(FPMULT_Op_MY[17]), .B(FPMULT_Op_MY[3]), .C(
FPMULT_Op_MY[4]), .D(FPMULT_Op_MY[20]), .Y(n1869) );
NAND4XLTS U3215 ( .A(n1870), .B(n1869), .C(n3230), .D(n2481), .Y(n1890) );
NOR4X1TS U3216 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MY[14]), .C(
FPMULT_Op_MY[19]), .D(FPMULT_Op_MY[8]), .Y(n1871) );
NAND4XLTS U3217 ( .A(n1871), .B(n3217), .C(n3060), .D(n2737), .Y(n1889) );
NOR4X1TS U3218 ( .A(FPMULT_Op_MY[16]), .B(FPMULT_Op_MY[11]), .C(
FPMULT_Op_MY[29]), .D(FPMULT_Op_MY[28]), .Y(n1875) );
NOR4X1TS U3219 ( .A(FPMULT_Op_MY[15]), .B(FPMULT_Op_MY[10]), .C(
FPMULT_Op_MY[9]), .D(FPMULT_Op_MY[5]), .Y(n1874) );
NOR4X1TS U3220 ( .A(FPMULT_Op_MY[6]), .B(FPMULT_Op_MY[7]), .C(
FPMULT_Op_MY[24]), .D(FPMULT_Op_MY[30]), .Y(n1873) );
NOR4X1TS U3221 ( .A(FPMULT_Op_MY[27]), .B(FPMULT_Op_MY[26]), .C(
FPMULT_Op_MY[23]), .D(FPMULT_Op_MY[25]), .Y(n1872) );
NAND4XLTS U3222 ( .A(n1875), .B(n1874), .C(n1873), .D(n1872), .Y(n1888) );
NOR2XLTS U3223 ( .A(FPMULT_Op_MX[15]), .B(FPMULT_Op_MX[16]), .Y(n1886) );
NOR2XLTS U3224 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[7]), .Y(n1885) );
NOR2XLTS U3225 ( .A(FPMULT_Op_MX[3]), .B(FPMULT_Op_MX[4]), .Y(n1876) );
NAND4XLTS U3226 ( .A(n952), .B(n1876), .C(n3135), .D(n3103), .Y(n1883) );
NOR4X1TS U3227 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_Op_MX[30]), .C(
FPMULT_Op_MX[29]), .D(FPMULT_Op_MX[25]), .Y(n1881) );
NAND4XLTS U3228 ( .A(n1881), .B(n1880), .C(n1879), .D(n1878), .Y(n1882) );
NAND4XLTS U3229 ( .A(n1886), .B(n1885), .C(n2775), .D(n1884), .Y(n1887) );
OAI31X1TS U3230 ( .A0(n1890), .A1(n1889), .A2(n1888), .B0(n1887), .Y(n106)
);
AOI222X4TS U3231 ( .A0(n3079), .A1(FPADDSUB_DmP_mant_SHT1_SW[5]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[7]), .B1(n953), .C0(
FPADDSUB_Raw_mant_NRM_SWR[18]), .C1(n1108), .Y(n1980) );
OAI22X1TS U3232 ( .A0(n1980), .A1(n970), .B0(n968), .B1(n1979), .Y(n1891) );
AOI21X1TS U3233 ( .A0(n2036), .A1(n1043), .B0(n1891), .Y(n1892) );
MX2X1TS U3234 ( .A(FPMULT_Op_MX[24]), .B(FPMULT_exp_oper_result[1]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[1]) );
NAND2X1TS U3235 ( .A(FPMULT_Sgf_normalized_result[6]), .B(n2830), .Y(n2829)
);
NAND2X1TS U3236 ( .A(FPMULT_Sgf_normalized_result[8]), .B(n2828), .Y(n2827)
);
NAND2X1TS U3237 ( .A(FPMULT_Sgf_normalized_result[10]), .B(n2826), .Y(n2825)
);
NAND2X1TS U3238 ( .A(FPMULT_Sgf_normalized_result[12]), .B(n2824), .Y(n2823)
);
NAND2X1TS U3239 ( .A(FPMULT_Sgf_normalized_result[14]), .B(n2822), .Y(n2821)
);
NAND2X1TS U3240 ( .A(FPMULT_Sgf_normalized_result[16]), .B(n2820), .Y(n2819)
);
NAND2X1TS U3241 ( .A(FPMULT_Sgf_normalized_result[18]), .B(n2818), .Y(n2817)
);
NAND2X1TS U3242 ( .A(FPMULT_Sgf_normalized_result[20]), .B(n2816), .Y(n2815)
);
NAND2X1TS U3243 ( .A(FPMULT_Sgf_normalized_result[22]), .B(n2814), .Y(n2813)
);
NOR2X1TS U3244 ( .A(n3186), .B(n2813), .Y(FPMULT_Adder_M_result_A_adder[24])
);
OAI22X1TS U3245 ( .A0(n1980), .A1(n974), .B0(n970), .B1(n1979), .Y(n1893) );
AOI21X1TS U3246 ( .A0(n2064), .A1(n1043), .B0(n1893), .Y(n1894) );
OAI21XLTS U3247 ( .A0(n969), .A1(n1975), .B0(n1894), .Y(
FPADDSUB_Data_array_SWR[6]) );
CMPR32X2TS U3248 ( .A(n1897), .B(n1896), .C(n1895), .CO(n1935), .S(n1898) );
INVX2TS U3249 ( .A(n1898), .Y(FPMULT_Sgf_operation_Result[30]) );
CMPR32X2TS U3250 ( .A(n1901), .B(n1900), .C(n1899), .CO(n1943), .S(n1902) );
INVX2TS U3251 ( .A(n1902), .Y(FPMULT_Sgf_operation_Result[27]) );
CMPR32X2TS U3252 ( .A(n1905), .B(n1904), .C(n1903), .CO(n1947), .S(n1906) );
INVX2TS U3253 ( .A(n1906), .Y(FPMULT_Sgf_operation_Result[25]) );
CMPR32X2TS U3254 ( .A(n1909), .B(n1908), .C(n1907), .CO(n1971), .S(n1910) );
INVX2TS U3255 ( .A(n1910), .Y(FPMULT_Sgf_operation_Result[38]) );
CMPR32X2TS U3256 ( .A(n1913), .B(n1912), .C(n1911), .CO(n1907), .S(n1914) );
INVX2TS U3257 ( .A(n1914), .Y(FPMULT_Sgf_operation_Result[37]) );
CMPR32X2TS U3258 ( .A(n1917), .B(n1916), .C(n1915), .CO(n1911), .S(n1918) );
INVX2TS U3259 ( .A(n1918), .Y(FPMULT_Sgf_operation_Result[36]) );
CMPR32X2TS U3260 ( .A(n1921), .B(n1920), .C(n1919), .CO(n1915), .S(n1922) );
INVX2TS U3261 ( .A(n1922), .Y(FPMULT_Sgf_operation_Result[35]) );
CMPR32X2TS U3262 ( .A(n1925), .B(n1924), .C(n1923), .CO(n1919), .S(n1926) );
INVX2TS U3263 ( .A(n1926), .Y(FPMULT_Sgf_operation_Result[34]) );
CMPR32X2TS U3264 ( .A(n1929), .B(n1928), .C(n1927), .CO(n1923), .S(n1930) );
INVX2TS U3265 ( .A(n1930), .Y(FPMULT_Sgf_operation_Result[33]) );
CMPR32X2TS U3266 ( .A(n1933), .B(n1932), .C(n1931), .CO(n1927), .S(n1934) );
INVX2TS U3267 ( .A(n1934), .Y(FPMULT_Sgf_operation_Result[32]) );
CMPR32X2TS U3268 ( .A(n1937), .B(n1936), .C(n1935), .CO(n1932), .S(n1938) );
INVX2TS U3269 ( .A(n1938), .Y(FPMULT_Sgf_operation_Result[31]) );
CMPR32X2TS U3270 ( .A(n1941), .B(n1940), .C(n1939), .CO(n1895), .S(n1942) );
INVX2TS U3271 ( .A(n1942), .Y(FPMULT_Sgf_operation_Result[29]) );
CMPR32X2TS U3272 ( .A(n1945), .B(n1944), .C(n1943), .CO(n1939), .S(n1946) );
INVX2TS U3273 ( .A(n1946), .Y(FPMULT_Sgf_operation_Result[28]) );
CMPR32X2TS U3274 ( .A(n1949), .B(n1948), .C(n1947), .CO(n1899), .S(n1950) );
INVX2TS U3275 ( .A(n1950), .Y(FPMULT_Sgf_operation_Result[26]) );
CMPR32X2TS U3276 ( .A(n1953), .B(n1952), .C(n1951), .CO(n1903), .S(n1954) );
INVX2TS U3277 ( .A(n1954), .Y(FPMULT_Sgf_operation_Result[24]) );
CMPR32X2TS U3278 ( .A(n1957), .B(n1956), .C(n1955), .CO(n1826), .S(n1958) );
INVX2TS U3279 ( .A(n1958), .Y(FPMULT_Sgf_operation_Result[43]) );
CMPR32X2TS U3280 ( .A(n1961), .B(n1960), .C(n1959), .CO(n1955), .S(n1962) );
INVX2TS U3281 ( .A(n1962), .Y(FPMULT_Sgf_operation_Result[42]) );
CMPR32X2TS U3282 ( .A(n1965), .B(n1964), .C(n1963), .CO(n1959), .S(n1966) );
INVX2TS U3283 ( .A(n1966), .Y(FPMULT_Sgf_operation_Result[41]) );
CMPR32X2TS U3284 ( .A(n1969), .B(n1968), .C(n1967), .CO(n1963), .S(n1970) );
INVX2TS U3285 ( .A(n1970), .Y(FPMULT_Sgf_operation_Result[40]) );
CMPR32X2TS U3286 ( .A(n1973), .B(n1972), .C(n1971), .CO(n1967), .S(n1974) );
INVX2TS U3287 ( .A(n1974), .Y(FPMULT_Sgf_operation_Result[39]) );
OAI22X1TS U3288 ( .A0(n1980), .A1(n3021), .B0(n970), .B1(n1975), .Y(n1976)
);
AOI21X1TS U3289 ( .A0(n2057), .A1(n1977), .B0(n1976), .Y(n1978) );
OAI21XLTS U3290 ( .A0(n975), .A1(n1979), .B0(n1978), .Y(
FPADDSUB_Data_array_SWR[7]) );
OAI22X1TS U3291 ( .A0(n1980), .A1(n969), .B0(n3021), .B1(n2047), .Y(n1981)
);
AOI21X1TS U3292 ( .A0(n2045), .A1(n1043), .B0(n1981), .Y(n1982) );
OR2X1TS U3293 ( .A(FPMULT_Exp_module_Overflow_flag_A), .B(
FPMULT_exp_oper_result[8]), .Y(n2778) );
OR2X2TS U3294 ( .A(underflow_flag_mult), .B(n2778), .Y(n3024) );
CLKBUFX3TS U3295 ( .A(n3024), .Y(n2020) );
NOR2XLTS U3296 ( .A(n3157), .B(n2020), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[11]) );
AOI21X1TS U3297 ( .A0(n3078), .A1(n1984), .B0(n2003), .Y(n1985) );
OAI21X1TS U3298 ( .A0(n1986), .A1(n2006), .B0(n1985), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[5]) );
NOR2XLTS U3299 ( .A(n3158), .B(n2020), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[13]) );
AOI21X1TS U3300 ( .A0(n967), .A1(n1987), .B0(n2003), .Y(n1988) );
OAI21X1TS U3301 ( .A0(n1989), .A1(n2006), .B0(n1988), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[3]) );
AOI22X1TS U3302 ( .A0(n1990), .A1(FPADDSUB_Data_array_SWR[47]), .B0(n962),
.B1(FPADDSUB_Data_array_SWR[43]), .Y(n1992) );
AOI22X1TS U3303 ( .A0(n960), .A1(FPADDSUB_Data_array_SWR[39]), .B0(n2581),
.B1(FPADDSUB_Data_array_SWR[35]), .Y(n1991) );
OAI211X1TS U3304 ( .A0(n1993), .A1(n950), .B0(n1992), .C0(n1991), .Y(n1998)
);
AOI21X1TS U3305 ( .A0(n967), .A1(n1998), .B0(n2003), .Y(n1994) );
OAI21X1TS U3306 ( .A0(n2000), .A1(n2006), .B0(n1994), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[9]) );
AOI21X1TS U3307 ( .A0(n967), .A1(n1995), .B0(n2003), .Y(n1996) );
OAI21X1TS U3308 ( .A0(n1997), .A1(n2006), .B0(n1996), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[8]) );
NOR2XLTS U3309 ( .A(n3155), .B(n2020), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[7]) );
NOR2XLTS U3310 ( .A(n3159), .B(n2020), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[15]) );
AOI21X1TS U3311 ( .A0(n1110), .A1(n1998), .B0(n2015), .Y(n1999) );
OAI21X1TS U3312 ( .A0(n2000), .A1(n2018), .B0(n1999), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[16]) );
AOI21X1TS U3313 ( .A0(n1110), .A1(n2001), .B0(n2015), .Y(n2002) );
OAI21X1TS U3314 ( .A0(n1032), .A1(n2018), .B0(n2002), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[19]) );
NOR2XLTS U3315 ( .A(n3160), .B(n2020), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[17]) );
AOI21X1TS U3316 ( .A0(n967), .A1(n2004), .B0(n2003), .Y(n2005) );
OAI21X1TS U3317 ( .A0(n1025), .A1(n2006), .B0(n2005), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[2]) );
NOR2X1TS U3318 ( .A(FPADDSUB_DMP_SFG[20]), .B(FPADDSUB_DmP_mant_SFG_SWR[22]),
.Y(n2603) );
NOR2X1TS U3319 ( .A(n3185), .B(n3093), .Y(n2990) );
NOR2X1TS U3320 ( .A(FPADDSUB_DMP_SFG[18]), .B(FPADDSUB_DmP_mant_SFG_SWR[20]),
.Y(n2534) );
NOR2X1TS U3321 ( .A(FPADDSUB_DMP_SFG[17]), .B(FPADDSUB_DmP_mant_SFG_SWR[19]),
.Y(n2984) );
NOR2X1TS U3322 ( .A(FPADDSUB_DMP_SFG[13]), .B(FPADDSUB_DmP_mant_SFG_SWR[15]),
.Y(n2963) );
NAND2X1TS U3323 ( .A(n3203), .B(n3094), .Y(n2958) );
NOR2X1TS U3324 ( .A(FPADDSUB_DMP_SFG[7]), .B(FPADDSUB_DmP_mant_SFG_SWR[9]),
.Y(n2933) );
AOI222X4TS U3325 ( .A0(n3091), .A1(n3150), .B0(n3091), .B1(n2925), .C0(n3150), .C1(n2925), .Y(n2930) );
AOI222X1TS U3326 ( .A0(n2954), .A1(n3146), .B0(n2954), .B1(n3092), .C0(n3146), .C1(n3092), .Y(n2959) );
AOI22X1TS U3327 ( .A0(FPADDSUB_DMP_SFG[12]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[14]), .B0(n2958), .B1(n2959), .Y(n2964) );
AOI222X4TS U3328 ( .A0(n2975), .A1(n3095), .B0(n2975), .B1(n3149), .C0(n3095), .C1(n3149), .Y(n2980) );
AOI222X1TS U3329 ( .A0(FPADDSUB_DMP_SFG[16]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[18]), .B0(FPADDSUB_DMP_SFG[16]), .B1(n2980),
.C0(FPADDSUB_DmP_mant_SFG_SWR[18]), .C1(n2980), .Y(n2986) );
AOI2BB2X1TS U3330 ( .B0(FPADDSUB_DMP_SFG[17]), .B1(
FPADDSUB_DmP_mant_SFG_SWR[19]), .A0N(n2984), .A1N(n2986), .Y(n2535) );
OAI2BB2X1TS U3331 ( .B0(n2534), .B1(n2535), .A0N(FPADDSUB_DMP_SFG[18]),
.A1N(FPADDSUB_DmP_mant_SFG_SWR[20]), .Y(n2992) );
OAI22X1TS U3332 ( .A0(n2990), .A1(n2992), .B0(FPADDSUB_DmP_mant_SFG_SWR[21]),
.B1(FPADDSUB_DMP_SFG[19]), .Y(n2604) );
NAND2X1TS U3333 ( .A(FPADDSUB_DmP_mant_SFG_SWR[18]), .B(n3171), .Y(n2979) );
NAND2X1TS U3334 ( .A(n3095), .B(FPADDSUB_DmP_mant_SFG_SWR[17]), .Y(n2973) );
NAND2X1TS U3335 ( .A(FPADDSUB_DmP_mant_SFG_SWR[16]), .B(n3167), .Y(n2968) );
NOR2X1TS U3336 ( .A(FPADDSUB_DMP_SFG[11]), .B(n3092), .Y(n2953) );
NAND2X1TS U3337 ( .A(FPADDSUB_DmP_mant_SFG_SWR[12]), .B(n3147), .Y(n2948) );
INVX2TS U3338 ( .A(n2948), .Y(n2010) );
NAND2X1TS U3339 ( .A(n3096), .B(FPADDSUB_DmP_mant_SFG_SWR[11]), .Y(n2943) );
NAND2X1TS U3340 ( .A(FPADDSUB_DmP_mant_SFG_SWR[10]), .B(n3166), .Y(n2938) );
NAND2X1TS U3341 ( .A(FPADDSUB_DmP_mant_SFG_SWR[8]), .B(n3170), .Y(n2928) );
NOR2X1TS U3342 ( .A(FPADDSUB_DMP_SFG[5]), .B(n3091), .Y(n2923) );
AOI222X1TS U3343 ( .A0(FPADDSUB_DMP_SFG[4]), .A1(n3154), .B0(
FPADDSUB_DMP_SFG[4]), .B1(n2009), .C0(n3154), .C1(n2009), .Y(n2924) );
OAI22X1TS U3344 ( .A0(n2923), .A1(n2924), .B0(FPADDSUB_DmP_mant_SFG_SWR[7]),
.B1(n3150), .Y(n2929) );
AOI222X1TS U3345 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[9]), .A1(n2935), .B0(
FPADDSUB_DmP_mant_SFG_SWR[9]), .B1(n3195), .C0(n2935), .C1(n3195), .Y(
n2939) );
OAI2BB2X1TS U3346 ( .B0(n3166), .B1(FPADDSUB_DmP_mant_SFG_SWR[10]), .A0N(
n2938), .A1N(n2939), .Y(n2945) );
AOI22X1TS U3347 ( .A0(n3148), .A1(FPADDSUB_DMP_SFG[9]), .B0(n2943), .B1(
n2945), .Y(n2950) );
OAI22X1TS U3348 ( .A0(n3147), .A1(FPADDSUB_DmP_mant_SFG_SWR[12]), .B0(n2010),
.B1(n2950), .Y(n2955) );
INVX2TS U3349 ( .A(n2955), .Y(n2011) );
AOI222X4TS U3350 ( .A0(FPADDSUB_DMP_SFG[12]), .A1(n3094), .B0(
FPADDSUB_DMP_SFG[12]), .B1(n2960), .C0(n3094), .C1(n2960), .Y(n2965)
);
AOI222X1TS U3351 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[15]), .A1(n2965), .B0(
FPADDSUB_DmP_mant_SFG_SWR[15]), .B1(n3196), .C0(n2965), .C1(n3196),
.Y(n2969) );
OAI2BB2X1TS U3352 ( .B0(n3167), .B1(FPADDSUB_DmP_mant_SFG_SWR[16]), .A0N(
n2968), .A1N(n2969), .Y(n2976) );
AOI22X1TS U3353 ( .A0(n3149), .A1(FPADDSUB_DMP_SFG[15]), .B0(n2973), .B1(
n2976), .Y(n2981) );
INVX2TS U3354 ( .A(n2981), .Y(n2012) );
AOI222X4TS U3355 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[21]), .A1(n2993), .B0(
FPADDSUB_DmP_mant_SFG_SWR[21]), .B1(n3093), .C0(n2993), .C1(n3093),
.Y(n2605) );
NAND2X1TS U3356 ( .A(FPADDSUB_DMP_SFG[21]), .B(n3205), .Y(n2023) );
OAI211X1TS U3357 ( .A0(n2027), .A1(n2022), .B0(n2997), .C0(n2023), .Y(n2998)
);
OAI21X1TS U3358 ( .A0(n2997), .A1(n2631), .B0(n2998), .Y(n2014) );
OAI21XLTS U3359 ( .A0(n2629), .A1(n2630), .B0(n2014), .Y(n2013) );
OAI31X1TS U3360 ( .A0(n2629), .A1(n2014), .A2(n2630), .B0(n2013), .Y(
FPADDSUB_Raw_mant_SGF[24]) );
NOR2XLTS U3361 ( .A(n3164), .B(n2020), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[5]) );
NOR2XLTS U3362 ( .A(n3161), .B(n2020), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[19]) );
AOI21X1TS U3363 ( .A0(n1110), .A1(n2016), .B0(n2015), .Y(n2017) );
OAI21X1TS U3364 ( .A0(n2019), .A1(n2018), .B0(n2017), .Y(
FPADDSUB_sftr_odat_SHT2_SWR[18]) );
NOR2XLTS U3365 ( .A(n3163), .B(n2020), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[3]) );
AOI22X1TS U3366 ( .A0(FPADDSUB_OP_FLAG_SFG), .A1(n2022), .B0(n2021), .B1(
n3232), .Y(n2026) );
INVX2TS U3367 ( .A(n2023), .Y(n2025) );
OAI21XLTS U3368 ( .A0(n2027), .A1(n2025), .B0(n2026), .Y(n2024) );
OAI31X1TS U3369 ( .A0(n2027), .A1(n2026), .A2(n2025), .B0(n2024), .Y(
FPADDSUB_Raw_mant_SGF[23]) );
AOI222X4TS U3370 ( .A0(n3079), .A1(FPADDSUB_DmP_mant_SHT1_SW[13]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[15]), .B1(n953), .C0(
FPADDSUB_Raw_mant_NRM_SWR[10]), .C1(n1109), .Y(n2061) );
OAI22X1TS U3371 ( .A0(n2061), .A1(n969), .B0(n3021), .B1(n2028), .Y(n2029)
);
AOI21X1TS U3372 ( .A0(n2045), .A1(n2063), .B0(n2029), .Y(n2030) );
OAI21XLTS U3373 ( .A0(n975), .A1(n2033), .B0(n2030), .Y(
FPADDSUB_Data_array_SWR[12]) );
OR2X1TS U3374 ( .A(FPMULT_exp_oper_result[0]), .B(n3024), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[0]) );
CLKBUFX2TS U3375 ( .A(n3024), .Y(n3025) );
NOR2XLTS U3376 ( .A(n3169), .B(n3025), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[1]) );
OAI222X4TS U3377 ( .A0(n958), .A1(FPADDSUB_Raw_mant_NRM_SWR[16]), .B0(n964),
.B1(FPADDSUB_Raw_mant_NRM_SWR[9]), .C0(FPADDSUB_DmP_mant_SHT1_SW[14]),
.C1(n1111), .Y(n2060) );
OAI22X1TS U3378 ( .A0(n2061), .A1(n971), .B0(n968), .B1(n2060), .Y(n2031) );
AOI21X1TS U3379 ( .A0(n2036), .A1(n2063), .B0(n2031), .Y(n2032) );
OR2X1TS U3380 ( .A(FPMULT_exp_oper_result[1]), .B(n3025), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[1]) );
AOI222X4TS U3381 ( .A0(n3079), .A1(FPADDSUB_DmP_mant_SHT1_SW[17]), .B0(n1109), .B1(FPADDSUB_Raw_mant_NRM_SWR[6]), .C0(FPADDSUB_Raw_mant_NRM_SWR[19]), .C1(
n953), .Y(n2054) );
OAI22X1TS U3382 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[18]), .A1(n957), .B0(
FPADDSUB_Shift_reg_FLAGS_7[1]), .B1(FPADDSUB_DmP_mant_SHT1_SW[16]),
.Y(n2034) );
AOI2BB1X2TS U3383 ( .A0N(n963), .A1N(FPADDSUB_Raw_mant_NRM_SWR[7]), .B0(
n2034), .Y(n2044) );
OAI222X4TS U3384 ( .A0(n958), .A1(FPADDSUB_Raw_mant_NRM_SWR[17]), .B0(n964),
.B1(FPADDSUB_Raw_mant_NRM_SWR[8]), .C0(FPADDSUB_DmP_mant_SHT1_SW[15]),
.C1(n1111), .Y(n2066) );
OAI22X1TS U3385 ( .A0(n1080), .A1(n2066), .B0(n968), .B1(n2059), .Y(n2035)
);
AOI21X1TS U3386 ( .A0(n2036), .A1(n2044), .B0(n2035), .Y(n2037) );
OAI21XLTS U3387 ( .A0(n2054), .A1(n971), .B0(n2037), .Y(
FPADDSUB_Data_array_SWR[17]) );
OR2X1TS U3388 ( .A(FPMULT_exp_oper_result[2]), .B(n3025), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[2]) );
NOR2XLTS U3389 ( .A(n3097), .B(n3025), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[0]) );
OR2X1TS U3390 ( .A(FPMULT_exp_oper_result[3]), .B(n3025), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[3]) );
OAI22X1TS U3391 ( .A0(n2054), .A1(n974), .B0(n970), .B1(n2059), .Y(n2038) );
AOI21X1TS U3392 ( .A0(n2064), .A1(n2044), .B0(n2038), .Y(n2039) );
OAI21XLTS U3393 ( .A0(n969), .A1(n2053), .B0(n2039), .Y(
FPADDSUB_Data_array_SWR[18]) );
OR2X1TS U3394 ( .A(FPMULT_exp_oper_result[4]), .B(n3025), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[4]) );
OAI22X1TS U3395 ( .A0(n2061), .A1(n3021), .B0(n970), .B1(n2066), .Y(n2040)
);
AOI21X1TS U3396 ( .A0(n2057), .A1(n2044), .B0(n2040), .Y(n2041) );
OAI21XLTS U3397 ( .A0(n975), .A1(n2060), .B0(n2041), .Y(
FPADDSUB_Data_array_SWR[15]) );
OR2X1TS U3398 ( .A(FPMULT_exp_oper_result[5]), .B(n3024), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[5]) );
AOI22X1TS U3399 ( .A0(n1108), .A1(FPADDSUB_Raw_mant_NRM_SWR[24]), .B0(n953),
.B1(FPADDSUB_Raw_mant_NRM_SWR[1]), .Y(n2050) );
OA22X1TS U3400 ( .A0(n964), .A1(n3208), .B0(n969), .B1(n2048), .Y(n2042) );
OR2X1TS U3401 ( .A(FPMULT_exp_oper_result[6]), .B(n3024), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[6]) );
OAI22X1TS U3402 ( .A0(n2054), .A1(n969), .B0(n974), .B1(n2066), .Y(n2043) );
AOI21X1TS U3403 ( .A0(n2045), .A1(n2044), .B0(n2043), .Y(n2046) );
OAI21XLTS U3404 ( .A0(n1080), .A1(n2060), .B0(n2046), .Y(
FPADDSUB_Data_array_SWR[16]) );
OAI22X1TS U3405 ( .A0(n971), .A1(n2048), .B0(n968), .B1(n2047), .Y(n2049) );
AOI2BB1XLTS U3406 ( .A0N(n1080), .A1N(n2050), .B0(n2049), .Y(n2051) );
OAI21XLTS U3407 ( .A0(n2052), .A1(n975), .B0(n2051), .Y(
FPADDSUB_Data_array_SWR[1]) );
OR2X1TS U3408 ( .A(FPMULT_exp_oper_result[7]), .B(n3024), .Y(
FPMULT_final_result_ieee_Module_Exp_S_mux[7]) );
OAI22X1TS U3409 ( .A0(n2054), .A1(n3021), .B0(n970), .B1(n2053), .Y(n2055)
);
AOI21X1TS U3410 ( .A0(n2057), .A1(n2056), .B0(n2055), .Y(n2058) );
OAI21XLTS U3411 ( .A0(n975), .A1(n2059), .B0(n2058), .Y(
FPADDSUB_Data_array_SWR[19]) );
OAI22X1TS U3412 ( .A0(n2061), .A1(n974), .B0(n970), .B1(n2060), .Y(n2062) );
AOI21X1TS U3413 ( .A0(n2064), .A1(n2063), .B0(n2062), .Y(n2065) );
OAI21XLTS U3414 ( .A0(n969), .A1(n2066), .B0(n2065), .Y(
FPADDSUB_Data_array_SWR[14]) );
NOR2BX1TS U3415 ( .AN(n2067), .B(FPSENCOS_cont_iter_out[3]), .Y(n857) );
NOR2XLTS U3416 ( .A(n2068), .B(n857), .Y(FPSENCOS_ITER_CONT_N5) );
CMPR32X2TS U3417 ( .A(n2071), .B(n2070), .C(n2069), .CO(n2807), .S(n1825) );
OAI21X1TS U3418 ( .A0(n944), .A1(n1104), .B0(n973), .Y(n2808) );
XNOR2X1TS U3419 ( .A(n2072), .B(n2808), .Y(n2806) );
CMPR32X2TS U3420 ( .A(n1027), .B(mult_x_69_n180), .C(n2073), .CO(n2074), .S(
n1708) );
INVX2TS U3421 ( .A(n2074), .Y(n2805) );
INVX2TS U3422 ( .A(n2075), .Y(FPMULT_Sgf_operation_Result[46]) );
NAND2X1TS U3423 ( .A(n3200), .B(FPADDSUB_DmP_EXP_EWSW[23]), .Y(n2643) );
NAND2X1TS U3424 ( .A(n3202), .B(FPSENCOS_cont_iter_out[0]), .Y(n2654) );
NOR2X1TS U3425 ( .A(FPSENCOS_d_ff2_X[27]), .B(n2646), .Y(n2645) );
OR3X1TS U3426 ( .A(FPSENCOS_d_ff2_X[27]), .B(FPSENCOS_d_ff2_X[28]), .C(n2646), .Y(n3055) );
OAI21XLTS U3427 ( .A0(n2645), .A1(n3271), .B0(n3055), .Y(
FPSENCOS_sh_exp_x[5]) );
OAI21X1TS U3428 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[2]), .A1(n3172), .B0(n2076),
.Y(n2078) );
INVX2TS U3429 ( .A(FPADDSUB_OP_FLAG_SFG), .Y(n2974) );
OAI21XLTS U3430 ( .A0(n2079), .A1(n2974), .B0(n2078), .Y(n2077) );
OAI31X1TS U3431 ( .A0(n2079), .A1(n2078), .A2(n2991), .B0(n2077), .Y(
FPADDSUB_Raw_mant_SGF[2]) );
OAI21XLTS U3432 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n3202), .B0(n2654),
.Y(FPSENCOS_sh_exp_x[0]) );
OAI21XLTS U3433 ( .A0(n2082), .A1(n3081), .B0(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n2080) );
OAI21XLTS U3434 ( .A0(n3081), .A1(n3121), .B0(n2080), .Y(n2081) );
AOI31XLTS U3435 ( .A0(n2082), .A1(n3081), .A2(n3121), .B0(n2081), .Y(n844)
);
OAI22X1TS U3436 ( .A0(n1064), .A1(n921), .B0(n1076), .B1(n2111), .Y(n2085)
);
OAI22X1TS U3437 ( .A0(n2239), .A1(n2750), .B0(n2698), .B1(n2112), .Y(n2084)
);
OAI31X1TS U3438 ( .A0(n2085), .A1(n3363), .A2(n2084), .B0(n2083), .Y(
mult_x_69_n730) );
OAI22X1TS U3439 ( .A0(n1066), .A1(n1002), .B0(n1033), .B1(n993), .Y(n2088)
);
OAI22X1TS U3440 ( .A0(n2752), .A1(n1094), .B0(n1010), .B1(n2668), .Y(n2087)
);
OAI21XLTS U3441 ( .A0(n2088), .A1(n2087), .B0(n2258), .Y(n2086) );
OAI31X1TS U3442 ( .A0(n2088), .A1(n2261), .A2(n2087), .B0(n2086), .Y(
mult_x_69_n655) );
OAI22X1TS U3443 ( .A0(n1085), .A1(n2722), .B0(n2708), .B1(n2181), .Y(n2091)
);
OAI22X1TS U3444 ( .A0(n1088), .A1(n2772), .B0(n2705), .B1(n2251), .Y(n2090)
);
OAI31X1TS U3445 ( .A0(n2091), .A1(n2327), .A2(n2090), .B0(n2089), .Y(
mult_x_69_n634) );
OAI22X1TS U3446 ( .A0(n3220), .A1(n973), .B0(n1056), .B1(n919), .Y(n2093) );
OAI22X1TS U3447 ( .A0(n1061), .A1(n1072), .B0(n1103), .B1(n2112), .Y(n2092)
);
NOR2X1TS U3448 ( .A(n2093), .B(n2092), .Y(mult_x_69_n596) );
OAI22X1TS U3449 ( .A0(n1100), .A1(n1024), .B0(n2672), .B1(n1072), .Y(n2096)
);
OAI22X1TS U3450 ( .A0(n2239), .A1(n2263), .B0(n2674), .B1(n2112), .Y(n2095)
);
OAI21XLTS U3451 ( .A0(n2096), .A1(n2095), .B0(n2204), .Y(n2094) );
OAI31X1TS U3452 ( .A0(n2096), .A1(n3362), .A2(n2095), .B0(n2094), .Y(
mult_x_69_n676) );
OAI22X1TS U3453 ( .A0(n1001), .A1(n1024), .B0(n991), .B1(n921), .Y(n2099) );
OAI22X1TS U3454 ( .A0(n2239), .A1(n2318), .B0(n1011), .B1(n2112), .Y(n2098)
);
OAI21XLTS U3455 ( .A0(n2099), .A1(n2098), .B0(n3069), .Y(n2097) );
OAI31X1TS U3456 ( .A0(n2099), .A1(n2199), .A2(n2098), .B0(n2097), .Y(
mult_x_69_n649) );
OAI22X1TS U3457 ( .A0(n1067), .A1(n1021), .B0(n1033), .B1(n1085), .Y(n2102)
);
OAI22X1TS U3458 ( .A0(n2752), .A1(n1090), .B0(n2216), .B1(n2668), .Y(n2101)
);
OAI21XLTS U3459 ( .A0(n2102), .A1(n2101), .B0(n2710), .Y(n2100) );
OAI31X1TS U3460 ( .A0(n2102), .A1(n2327), .A2(n2101), .B0(n2100), .Y(
mult_x_69_n628) );
OAI22X1TS U3461 ( .A0(n1066), .A1(n2673), .B0(n3230), .B1(n1051), .Y(n2105)
);
OAI22X1TS U3462 ( .A0(n2752), .A1(n2263), .B0(n1106), .B1(n2668), .Y(n2104)
);
OAI21XLTS U3463 ( .A0(n2105), .A1(n2104), .B0(n2264), .Y(n2103) );
OAI31X1TS U3464 ( .A0(n2105), .A1(n2267), .A2(n2104), .B0(n2103), .Y(
mult_x_69_n682) );
OAI22X1TS U3465 ( .A0(n2683), .A1(n1060), .B0(n3229), .B1(n973), .Y(n2107)
);
OAI22X1TS U3466 ( .A0(n1067), .A1(n1058), .B0(n1104), .B1(n2668), .Y(n2106)
);
NOR2X1TS U3467 ( .A(n2107), .B(n2106), .Y(mult_x_69_n602) );
OAI22X1TS U3468 ( .A0(n1004), .A1(n1024), .B0(n985), .B1(n921), .Y(n2110) );
OAI22X1TS U3469 ( .A0(n2239), .A1(n2478), .B0(n1007), .B1(n2112), .Y(n2109)
);
OAI21XLTS U3470 ( .A0(n2110), .A1(n2109), .B0(n1619), .Y(n2108) );
OAI31X1TS U3471 ( .A0(n2110), .A1(n2485), .A2(n2109), .B0(n2108), .Y(
mult_x_69_n703) );
OAI22X1TS U3472 ( .A0(n1086), .A1(n921), .B0(n2708), .B1(n2111), .Y(n2115)
);
OAI22X1TS U3473 ( .A0(n3220), .A1(n1088), .B0(n2313), .B1(n2112), .Y(n2114)
);
OAI21XLTS U3474 ( .A0(n2115), .A1(n2114), .B0(n2710), .Y(n2113) );
OAI31X1TS U3475 ( .A0(n2115), .A1(n3361), .A2(n2114), .B0(n2113), .Y(
mult_x_69_n622) );
CMPR32X2TS U3476 ( .A(n2118), .B(n2117), .C(n2116), .CO(n2122), .S(n2119) );
INVX2TS U3477 ( .A(n2119), .Y(mult_x_69_n447) );
INVX2TS U3478 ( .A(n2120), .Y(mult_x_69_n234) );
CMPR32X2TS U3479 ( .A(n2123), .B(n2122), .C(n2121), .CO(n1401), .S(n2124) );
INVX2TS U3480 ( .A(n2124), .Y(mult_x_69_n440) );
OAI22X1TS U3481 ( .A0(n2764), .A1(n2733), .B0(n1077), .B1(n2706), .Y(n2130)
);
INVX2TS U3482 ( .A(n2127), .Y(n2738) );
OAI22X1TS U3483 ( .A0(n2763), .A1(n1069), .B0(n2698), .B1(n2738), .Y(n2129)
);
OAI21XLTS U3484 ( .A0(n2130), .A1(n2129), .B0(n3213), .Y(n2128) );
OAI31X1TS U3485 ( .A0(n2130), .A1(n3363), .A2(n2129), .B0(n2128), .Y(
mult_x_69_n747) );
INVX2TS U3486 ( .A(mult_x_69_n211), .Y(n2145) );
OAI22X1TS U3487 ( .A0(n3220), .A1(n1057), .B0(n2244), .B1(n1103), .Y(n2131)
);
AOI21X1TS U3488 ( .A0(FPMULT_Op_MY[16]), .A1(n2775), .B0(n2131), .Y(n2132)
);
OAI21XLTS U3489 ( .A0(n2191), .A1(n2771), .B0(n2132), .Y(n2144) );
INVX2TS U3490 ( .A(n2133), .Y(mult_x_69_n206) );
OAI22X1TS U3491 ( .A0(n2752), .A1(n1060), .B0(n3223), .B1(n973), .Y(n2134)
);
AOI21X1TS U3492 ( .A0(FPMULT_Op_MY[13]), .A1(n2135), .B0(n2134), .Y(n2136)
);
OAI21XLTS U3493 ( .A0(n1103), .A1(n2684), .B0(n2136), .Y(n2154) );
INVX2TS U3494 ( .A(n2137), .Y(mult_x_69_n242) );
AOI31X1TS U3495 ( .A0(FPMULT_Op_MX[17]), .A1(mult_x_69_n435), .A2(n2139),
.B0(n2138), .Y(mult_x_69_n427) );
CMPR32X2TS U3496 ( .A(n2142), .B(n2141), .C(n2140), .CO(n1366), .S(n2143) );
INVX2TS U3497 ( .A(n2143), .Y(mult_x_69_n389) );
CMPR32X2TS U3498 ( .A(n2145), .B(FPMULT_Op_MY[15]), .C(n2144), .CO(n2173),
.S(n2133) );
INVX2TS U3499 ( .A(n2146), .Y(mult_x_69_n200) );
OAI22X1TS U3500 ( .A0(n1087), .A1(n3231), .B0(n2708), .B1(n2706), .Y(n2149)
);
OAI22X1TS U3501 ( .A0(n1089), .A1(n1069), .B0(n2313), .B1(n2738), .Y(n2148)
);
OAI21XLTS U3502 ( .A0(n2149), .A1(n2148), .B0(n2710), .Y(n2147) );
OAI31X1TS U3503 ( .A0(n2149), .A1(n3361), .A2(n2148), .B0(n2147), .Y(
mult_x_69_n639) );
CMPR32X2TS U3504 ( .A(n2152), .B(n2151), .C(n2150), .CO(n2141), .S(n2153) );
INVX2TS U3505 ( .A(n2153), .Y(mult_x_69_n399) );
CMPR32X2TS U3506 ( .A(n3224), .B(FPMULT_Op_MY[9]), .C(n2154), .CO(n2137),
.S(n2155) );
INVX2TS U3507 ( .A(n2155), .Y(mult_x_69_n243) );
INVX2TS U3508 ( .A(mult_x_69_n260), .Y(n2202) );
OAI22X1TS U3509 ( .A0(n2752), .A1(n1058), .B0(n1103), .B1(n2749), .Y(n2156)
);
AOI21X1TS U3510 ( .A0(FPMULT_Op_MY[10]), .A1(n2775), .B0(n2156), .Y(n2157)
);
INVX2TS U3511 ( .A(n2158), .Y(mult_x_69_n252) );
OAI22X1TS U3512 ( .A0(n1085), .A1(n2772), .B0(n1022), .B1(n2722), .Y(n2161)
);
OAI22X1TS U3513 ( .A0(n1090), .A1(n2756), .B0(n2216), .B1(n2694), .Y(n2160)
);
OAI21XLTS U3514 ( .A0(n2161), .A1(n2160), .B0(n2710), .Y(n2159) );
OAI31X1TS U3515 ( .A0(n2161), .A1(n2327), .A2(n2160), .B0(n2159), .Y(
mult_x_69_n635) );
INVX2TS U3516 ( .A(n2162), .Y(mult_x_69_n194) );
OAI22X1TS U3517 ( .A0(n1088), .A1(n2737), .B0(n2705), .B1(n2727), .Y(n2165)
);
OAI22X1TS U3518 ( .A0(n1086), .A1(n3219), .B0(n1021), .B1(n920), .Y(n2164)
);
OAI21XLTS U3519 ( .A0(n2165), .A1(n2164), .B0(n2710), .Y(n2163) );
OAI31X1TS U3520 ( .A0(n2165), .A1(n3361), .A2(n2164), .B0(n2163), .Y(
mult_x_69_n638) );
OAI22X1TS U3521 ( .A0(n1089), .A1(n1048), .B0(n2216), .B1(n1034), .Y(n2169)
);
OAI22X1TS U3522 ( .A0(n1087), .A1(n3228), .B0(n1022), .B1(n2252), .Y(n2168)
);
OAI21XLTS U3523 ( .A0(n2169), .A1(n2168), .B0(n2166), .Y(n2167) );
OAI31X1TS U3524 ( .A0(n2169), .A1(n3361), .A2(n2168), .B0(n2167), .Y(
mult_x_69_n636) );
OAI22X1TS U3525 ( .A0(n2683), .A1(n2673), .B0(n3229), .B1(n1052), .Y(n2172)
);
OAI22X1TS U3526 ( .A0(n2451), .A1(n2263), .B0(n1105), .B1(n2684), .Y(n2171)
);
OAI31X1TS U3527 ( .A0(n2172), .A1(n2267), .A2(n2171), .B0(n2170), .Y(
mult_x_69_n683) );
CMPR32X2TS U3528 ( .A(n3221), .B(FPMULT_Op_MY[15]), .C(n2173), .CO(n2174),
.S(n2146) );
INVX2TS U3529 ( .A(n2174), .Y(mult_x_69_n199) );
OAI22X1TS U3530 ( .A0(n2239), .A1(n1063), .B0(n1078), .B1(n1072), .Y(n2177)
);
OAI22X1TS U3531 ( .A0(n910), .A1(n2763), .B0(n2689), .B1(n2240), .Y(n2176)
);
OAI21XLTS U3532 ( .A0(n2177), .A1(n2176), .B0(n2701), .Y(n2175) );
OAI31X1TS U3533 ( .A0(n2177), .A1(n3363), .A2(n2176), .B0(n2175), .Y(
mult_x_69_n731) );
OAI22X1TS U3534 ( .A0(n2462), .A1(n2750), .B0(n2244), .B1(n2698), .Y(n2180)
);
CLKBUFX3TS U3535 ( .A(n2725), .Y(n2768) );
OAI22X1TS U3536 ( .A0(n910), .A1(n1063), .B0(n1040), .B1(n1078), .Y(n2179)
);
OAI21XLTS U3537 ( .A0(n2180), .A1(n2179), .B0(n2701), .Y(n2178) );
OAI31X1TS U3538 ( .A0(n2180), .A1(n2768), .A2(n2179), .B0(n2178), .Y(
mult_x_69_n732) );
OAI22X1TS U3539 ( .A0(n2720), .A1(n2673), .B0(n2672), .B1(n2181), .Y(n2184)
);
OAI22X1TS U3540 ( .A0(n2675), .A1(n2226), .B0(n1106), .B1(n2721), .Y(n2183)
);
OAI21XLTS U3541 ( .A0(n2184), .A1(n2183), .B0(n2264), .Y(n2182) );
OAI31X1TS U3542 ( .A0(n2184), .A1(n1298), .A2(n2183), .B0(n2182), .Y(
mult_x_69_n687) );
OAI22X1TS U3543 ( .A0(n2239), .A1(n1087), .B0(n1021), .B1(n921), .Y(n2187)
);
OAI22X1TS U3544 ( .A0(n2471), .A1(n1089), .B0(n2705), .B1(n2240), .Y(n2186)
);
OAI31X1TS U3545 ( .A0(n2187), .A1(n2327), .A2(n2186), .B0(n2185), .Y(
mult_x_69_n623) );
OAI22X1TS U3546 ( .A0(n2745), .A1(n1100), .B0(n2744), .B1(n1051), .Y(n2190)
);
OAI22X1TS U3547 ( .A0(n2675), .A1(n3225), .B0(n1105), .B1(n1035), .Y(n2189)
);
OAI21XLTS U3548 ( .A0(n2190), .A1(n2189), .B0(n3212), .Y(n2188) );
OAI31X1TS U3549 ( .A0(n2190), .A1(n2267), .A2(n2189), .B0(n2188), .Y(
mult_x_69_n686) );
OAI22X1TS U3550 ( .A0(n2191), .A1(n973), .B0(n1040), .B1(n1061), .Y(n2193)
);
OAI22X1TS U3551 ( .A0(n1058), .A1(n1072), .B0(n1104), .B1(n2240), .Y(n2192)
);
NOR2X1TS U3552 ( .A(n2193), .B(n2192), .Y(mult_x_69_n597) );
OAI22X1TS U3553 ( .A0(n2315), .A1(n920), .B0(n1106), .B1(n1034), .Y(n2196)
);
OAI22X1TS U3554 ( .A0(n1101), .A1(n3227), .B0(n1051), .B1(n2756), .Y(n2195)
);
OAI21XLTS U3555 ( .A0(n2196), .A1(n2195), .B0(n3212), .Y(n2194) );
OAI31X1TS U3556 ( .A0(n2196), .A1(n2267), .A2(n2195), .B0(n2194), .Y(
mult_x_69_n690) );
OAI22X1TS U3557 ( .A0(n2239), .A1(n992), .B0(n1000), .B1(n1072), .Y(n2200)
);
OAI22X1TS U3558 ( .A0(n2471), .A1(n1095), .B0(n1010), .B1(n2240), .Y(n2198)
);
OAI21XLTS U3559 ( .A0(n2200), .A1(n2198), .B0(n3069), .Y(n2197) );
OAI31X1TS U3560 ( .A0(n2200), .A1(n2199), .A2(n2198), .B0(n2197), .Y(
mult_x_69_n650) );
CMPR32X2TS U3561 ( .A(n2202), .B(FPMULT_Op_MY[9]), .C(n2201), .CO(n2203),
.S(n2158) );
INVX2TS U3562 ( .A(n2203), .Y(mult_x_69_n251) );
OAI22X1TS U3563 ( .A0(n2239), .A1(n1051), .B0(n2673), .B1(n921), .Y(n2207)
);
OAI22X1TS U3564 ( .A0(n2471), .A1(n2675), .B0(n1105), .B1(n2240), .Y(n2206)
);
OAI31X1TS U3565 ( .A0(n2207), .A1(n3362), .A2(n2206), .B0(n2205), .Y(
mult_x_69_n677) );
OAI22X1TS U3566 ( .A0(n2745), .A1(n2263), .B0(n1106), .B1(n2749), .Y(n2210)
);
OAI22X1TS U3567 ( .A0(n2752), .A1(n1101), .B0(n3223), .B1(n1051), .Y(n2209)
);
OAI21XLTS U3568 ( .A0(n2210), .A1(n2209), .B0(n3212), .Y(n2208) );
OAI31X1TS U3569 ( .A0(n2210), .A1(n2267), .A2(n2209), .B0(n2208), .Y(
mult_x_69_n684) );
CMPR32X2TS U3570 ( .A(FPMULT_Op_MX[11]), .B(n3218), .C(n3223), .CO(n2120),
.S(n2211) );
INVX2TS U3571 ( .A(n2211), .Y(mult_x_69_n235) );
CMPR32X2TS U3572 ( .A(FPMULT_Op_MX[17]), .B(n3222), .C(n910), .CO(n2162),
.S(n2212) );
INVX2TS U3573 ( .A(n2212), .Y(mult_x_69_n195) );
OAI22X1TS U3574 ( .A0(n2315), .A1(n3231), .B0(n1105), .B1(n2727), .Y(n2215)
);
OAI22X1TS U3575 ( .A0(n1100), .A1(n1048), .B0(n2672), .B1(n2706), .Y(n2214)
);
OAI21XLTS U3576 ( .A0(n2215), .A1(n2214), .B0(n2264), .Y(n2213) );
OAI31X1TS U3577 ( .A0(n2215), .A1(n3362), .A2(n2214), .B0(n2213), .Y(
mult_x_69_n692) );
OAI22X1TS U3578 ( .A0(n1033), .A1(n1022), .B0(n2481), .B1(n1086), .Y(n2219)
);
OAI22X1TS U3579 ( .A0(n2451), .A1(n1090), .B0(n2216), .B1(n2684), .Y(n2218)
);
OAI21XLTS U3580 ( .A0(n2219), .A1(n2218), .B0(n3068), .Y(n2217) );
OAI31X1TS U3581 ( .A0(n2219), .A1(n2327), .A2(n2218), .B0(n2217), .Y(
mult_x_69_n629) );
OAI22X1TS U3582 ( .A0(n1101), .A1(n3226), .B0(n1052), .B1(n2772), .Y(n2222)
);
OAI22X1TS U3583 ( .A0(n2675), .A1(n3228), .B0(n1106), .B1(n2694), .Y(n2221)
);
OAI21XLTS U3584 ( .A0(n2222), .A1(n2221), .B0(n2264), .Y(n2220) );
OAI31X1TS U3585 ( .A0(n2222), .A1(n2267), .A2(n2221), .B0(n2220), .Y(
mult_x_69_n689) );
OAI22X1TS U3586 ( .A0(n1064), .A1(n3226), .B0(n1076), .B1(n2719), .Y(n2225)
);
OAI22X1TS U3587 ( .A0(n2763), .A1(n3227), .B0(n2762), .B1(n2251), .Y(n2224)
);
OAI21XLTS U3588 ( .A0(n2225), .A1(n2224), .B0(n3213), .Y(n2223) );
OAI31X1TS U3589 ( .A0(n2225), .A1(n2725), .A2(n2224), .B0(n2223), .Y(
mult_x_69_n742) );
OAI22X1TS U3590 ( .A0(n2764), .A1(n3227), .B0(n1077), .B1(n2226), .Y(n2229)
);
OAI22X1TS U3591 ( .A0(n2763), .A1(n3228), .B0(n2762), .B1(n2694), .Y(n2228)
);
OAI31X1TS U3592 ( .A0(n2229), .A1(n2768), .A2(n2228), .B0(n2227), .Y(
mult_x_69_n743) );
OAI22X1TS U3593 ( .A0(n2675), .A1(n3219), .B0(n1105), .B1(n2761), .Y(n2232)
);
OAI22X1TS U3594 ( .A0(n1100), .A1(n3228), .B0(n1051), .B1(n1048), .Y(n2231)
);
OAI31X1TS U3595 ( .A0(n2232), .A1(n2267), .A2(n2231), .B0(n2230), .Y(
mult_x_69_n691) );
OAI22X1TS U3596 ( .A0(n2745), .A1(n2318), .B0(n1011), .B1(n2749), .Y(n2235)
);
OAI22X1TS U3597 ( .A0(n2752), .A1(n1000), .B0(n3223), .B1(n992), .Y(n2234)
);
OAI21XLTS U3598 ( .A0(n2235), .A1(n2234), .B0(n2258), .Y(n2233) );
OAI31X1TS U3599 ( .A0(n2235), .A1(n2261), .A2(n2234), .B0(n2233), .Y(
mult_x_69_n657) );
OAI22X1TS U3600 ( .A0(n1720), .A1(n920), .B0(n2762), .B1(n1034), .Y(n2238)
);
OAI22X1TS U3601 ( .A0(n1064), .A1(n3228), .B0(n1078), .B1(n2252), .Y(n2237)
);
OAI21XLTS U3602 ( .A0(n2238), .A1(n2237), .B0(n3213), .Y(n2236) );
OAI31X1TS U3603 ( .A0(n2238), .A1(n2768), .A2(n2237), .B0(n2236), .Y(
mult_x_69_n744) );
OAI22X1TS U3604 ( .A0(n2239), .A1(n987), .B0(n1003), .B1(n1072), .Y(n2243)
);
OAI22X1TS U3605 ( .A0(n910), .A1(n1097), .B0(n1008), .B1(n2240), .Y(n2242)
);
OAI21XLTS U3606 ( .A0(n2243), .A1(n2242), .B0(n2482), .Y(n2241) );
OAI31X1TS U3607 ( .A0(n2243), .A1(n2485), .A2(n2242), .B0(n2241), .Y(
mult_x_69_n704) );
OAI22X1TS U3608 ( .A0(n2462), .A1(n2478), .B0(n2244), .B1(n1008), .Y(n2247)
);
OAI22X1TS U3609 ( .A0(n910), .A1(n986), .B0(n1040), .B1(n1005), .Y(n2246) );
OAI21XLTS U3610 ( .A0(n2247), .A1(n2246), .B0(n2482), .Y(n2245) );
OAI31X1TS U3611 ( .A0(n2247), .A1(n3118), .A2(n2246), .B0(n2245), .Y(
mult_x_69_n705) );
OAI22X1TS U3612 ( .A0(n2764), .A1(n3219), .B0(n1076), .B1(n920), .Y(n2250)
);
OAI22X1TS U3613 ( .A0(n1720), .A1(n3231), .B0(n2762), .B1(n2727), .Y(n2249)
);
OAI21XLTS U3614 ( .A0(n2250), .A1(n2249), .B0(n2725), .Y(n2248) );
OAI31X1TS U3615 ( .A0(n2250), .A1(n3363), .A2(n2249), .B0(n2248), .Y(
mult_x_69_n746) );
OAI22X1TS U3616 ( .A0(n1101), .A1(n2719), .B0(n1052), .B1(n2722), .Y(n2255)
);
OAI22X1TS U3617 ( .A0(n2675), .A1(n2252), .B0(n1106), .B1(n2251), .Y(n2254)
);
OAI21XLTS U3618 ( .A0(n2255), .A1(n2254), .B0(n3212), .Y(n2253) );
OAI31X1TS U3619 ( .A0(n2255), .A1(n1298), .A2(n2254), .B0(n2253), .Y(
mult_x_69_n688) );
OAI22X1TS U3620 ( .A0(n2683), .A1(n1002), .B0(n3229), .B1(n993), .Y(n2262)
);
OAI22X1TS U3621 ( .A0(n2451), .A1(n1095), .B0(n1010), .B1(n2684), .Y(n2260)
);
OAI21XLTS U3622 ( .A0(n2262), .A1(n2260), .B0(n2258), .Y(n2259) );
OAI31X1TS U3623 ( .A0(n2262), .A1(n2261), .A2(n2260), .B0(n2259), .Y(
mult_x_69_n656) );
OAI22X1TS U3624 ( .A0(n2720), .A1(n2263), .B0(n1105), .B1(n2715), .Y(n2268)
);
OAI22X1TS U3625 ( .A0(n2451), .A1(n1100), .B0(n3224), .B1(n1052), .Y(n2266)
);
OAI31X1TS U3626 ( .A0(n2268), .A1(n2267), .A2(n2266), .B0(n2265), .Y(
mult_x_69_n685) );
CLKBUFX3TS U3627 ( .A(n2292), .Y(n2782) );
OR2X2TS U3628 ( .A(n3037), .B(operation[2]), .Y(n2282) );
INVX2TS U3629 ( .A(n2282), .Y(n2273) );
AOI22X1TS U3630 ( .A0(n2310), .A1(cordic_result[0]), .B0(n2306), .B1(
mult_result[0]), .Y(n2269) );
INVX2TS U3631 ( .A(n2780), .Y(n2286) );
AOI22X1TS U3632 ( .A0(n2287), .A1(cordic_result[2]), .B0(n2272), .B1(
mult_result[2]), .Y(n2270) );
OAI21XLTS U3633 ( .A0(n2782), .A1(n3267), .B0(n2270), .Y(op_result[2]) );
AOI22X1TS U3634 ( .A0(n2310), .A1(cordic_result[3]), .B0(n2286), .B1(
mult_result[3]), .Y(n2271) );
OAI21XLTS U3635 ( .A0(n2782), .A1(n3266), .B0(n2271), .Y(op_result[3]) );
AOI22X1TS U3636 ( .A0(n2273), .A1(cordic_result[1]), .B0(n2309), .B1(
mult_result[1]), .Y(n2274) );
OAI21XLTS U3637 ( .A0(n2782), .A1(n3268), .B0(n2274), .Y(op_result[1]) );
AOI22X1TS U3638 ( .A0(n2273), .A1(cordic_result[5]), .B0(n2306), .B1(
mult_result[5]), .Y(n2275) );
CLKBUFX3TS U3639 ( .A(n2292), .Y(n2312) );
AOI22X1TS U3640 ( .A0(n2287), .A1(cordic_result[6]), .B0(n2309), .B1(
mult_result[6]), .Y(n2276) );
OAI21XLTS U3641 ( .A0(n2312), .A1(n3263), .B0(n2276), .Y(op_result[6]) );
AOI22X1TS U3642 ( .A0(n2310), .A1(cordic_result[4]), .B0(n2272), .B1(
mult_result[4]), .Y(n2277) );
OAI21XLTS U3643 ( .A0(n2782), .A1(n3265), .B0(n2277), .Y(op_result[4]) );
AOI22X1TS U3644 ( .A0(n2273), .A1(cordic_result[8]), .B0(n2286), .B1(
mult_result[8]), .Y(n2278) );
OAI21XLTS U3645 ( .A0(n2782), .A1(n3261), .B0(n2278), .Y(op_result[8]) );
AOI22X1TS U3646 ( .A0(n2287), .A1(cordic_result[9]), .B0(n2306), .B1(
mult_result[9]), .Y(n2279) );
OAI21XLTS U3647 ( .A0(n2312), .A1(n3260), .B0(n2279), .Y(op_result[9]) );
AOI22X1TS U3648 ( .A0(n2310), .A1(cordic_result[10]), .B0(n2309), .B1(
mult_result[10]), .Y(n2280) );
OAI21XLTS U3649 ( .A0(n2312), .A1(n3259), .B0(n2280), .Y(op_result[10]) );
AOI22X1TS U3650 ( .A0(n2273), .A1(cordic_result[11]), .B0(n2272), .B1(
mult_result[11]), .Y(n2281) );
OAI21XLTS U3651 ( .A0(n2312), .A1(n3258), .B0(n2281), .Y(op_result[11]) );
INVX2TS U3652 ( .A(n2282), .Y(n2310) );
AOI22X1TS U3653 ( .A0(n2287), .A1(cordic_result[12]), .B0(n2272), .B1(
mult_result[12]), .Y(n2283) );
OAI21XLTS U3654 ( .A0(n2312), .A1(n3257), .B0(n2283), .Y(op_result[12]) );
AOI22X1TS U3655 ( .A0(n2310), .A1(cordic_result[13]), .B0(n2286), .B1(
mult_result[13]), .Y(n2284) );
OAI21XLTS U3656 ( .A0(n2312), .A1(n3256), .B0(n2284), .Y(op_result[13]) );
AOI22X1TS U3657 ( .A0(n2273), .A1(cordic_result[14]), .B0(n2306), .B1(
mult_result[14]), .Y(n2285) );
OAI21XLTS U3658 ( .A0(n2312), .A1(n3255), .B0(n2285), .Y(op_result[14]) );
AOI22X1TS U3659 ( .A0(n2287), .A1(cordic_result[7]), .B0(n2286), .B1(
mult_result[7]), .Y(n2288) );
OAI21XLTS U3660 ( .A0(n2782), .A1(n3262), .B0(n2288), .Y(op_result[7]) );
AOI22X1TS U3661 ( .A0(n2287), .A1(cordic_result[16]), .B0(n2309), .B1(
mult_result[16]), .Y(n2289) );
OAI21XLTS U3662 ( .A0(n2312), .A1(n3253), .B0(n2289), .Y(op_result[16]) );
AOI22X1TS U3663 ( .A0(n2310), .A1(cordic_result[17]), .B0(n2272), .B1(
mult_result[17]), .Y(n2290) );
OAI21XLTS U3664 ( .A0(n2312), .A1(n3252), .B0(n2290), .Y(op_result[17]) );
AOI22X1TS U3665 ( .A0(n2273), .A1(cordic_result[18]), .B0(n2286), .B1(
mult_result[18]), .Y(n2291) );
OAI21XLTS U3666 ( .A0(n2292), .A1(n3251), .B0(n2291), .Y(op_result[18]) );
AOI22X1TS U3667 ( .A0(n2287), .A1(cordic_result[19]), .B0(n2306), .B1(
mult_result[19]), .Y(n2293) );
OAI21XLTS U3668 ( .A0(n2292), .A1(n3250), .B0(n2293), .Y(op_result[19]) );
AOI22X1TS U3669 ( .A0(n2310), .A1(cordic_result[20]), .B0(n2309), .B1(
mult_result[20]), .Y(n2294) );
AOI22X1TS U3670 ( .A0(n2273), .A1(cordic_result[21]), .B0(n2272), .B1(
mult_result[21]), .Y(n2295) );
OAI21XLTS U3671 ( .A0(n2292), .A1(n3248), .B0(n2295), .Y(op_result[21]) );
INVX2TS U3672 ( .A(n2282), .Y(n2307) );
INVX2TS U3673 ( .A(n2780), .Y(n2306) );
AOI22X1TS U3674 ( .A0(n2307), .A1(cordic_result[22]), .B0(n2306), .B1(
mult_result[22]), .Y(n2296) );
OAI21XLTS U3675 ( .A0(n2305), .A1(n3247), .B0(n2296), .Y(op_result[22]) );
AOI22X1TS U3676 ( .A0(n2307), .A1(cordic_result[23]), .B0(n2309), .B1(
mult_result[23]), .Y(n2297) );
OAI21XLTS U3677 ( .A0(n2292), .A1(n3246), .B0(n2297), .Y(op_result[23]) );
AOI22X1TS U3678 ( .A0(n2307), .A1(cordic_result[24]), .B0(n2272), .B1(
mult_result[24]), .Y(n2298) );
OAI21XLTS U3679 ( .A0(n2305), .A1(n3245), .B0(n2298), .Y(op_result[24]) );
AOI22X1TS U3680 ( .A0(n2307), .A1(cordic_result[25]), .B0(n2286), .B1(
mult_result[25]), .Y(n2299) );
OAI21XLTS U3681 ( .A0(n2292), .A1(n3244), .B0(n2299), .Y(op_result[25]) );
AOI22X1TS U3682 ( .A0(n2307), .A1(cordic_result[26]), .B0(n2306), .B1(
mult_result[26]), .Y(n2300) );
OAI21XLTS U3683 ( .A0(n2292), .A1(n3243), .B0(n2300), .Y(op_result[26]) );
AOI22X1TS U3684 ( .A0(n2307), .A1(cordic_result[27]), .B0(n2309), .B1(
mult_result[27]), .Y(n2301) );
OAI21XLTS U3685 ( .A0(n2292), .A1(n3242), .B0(n2301), .Y(op_result[27]) );
AOI22X1TS U3686 ( .A0(n2307), .A1(cordic_result[28]), .B0(n2272), .B1(
mult_result[28]), .Y(n2302) );
OAI21XLTS U3687 ( .A0(n2305), .A1(n3241), .B0(n2302), .Y(op_result[28]) );
AOI22X1TS U3688 ( .A0(n2307), .A1(cordic_result[29]), .B0(n2286), .B1(
mult_result[29]), .Y(n2303) );
OAI21XLTS U3689 ( .A0(n2305), .A1(n3240), .B0(n2303), .Y(op_result[29]) );
AOI22X1TS U3690 ( .A0(n2310), .A1(cordic_result[30]), .B0(n2306), .B1(
mult_result[30]), .Y(n2304) );
OAI21XLTS U3691 ( .A0(n2305), .A1(n3239), .B0(n2304), .Y(op_result[30]) );
AOI22X1TS U3692 ( .A0(n2273), .A1(cordic_result[31]), .B0(n2309), .B1(
mult_result[31]), .Y(n2308) );
OAI21XLTS U3693 ( .A0(n2782), .A1(n3238), .B0(n2308), .Y(op_result[31]) );
AOI22X1TS U3694 ( .A0(n2287), .A1(cordic_result[15]), .B0(n2286), .B1(
mult_result[15]), .Y(n2311) );
OAI21XLTS U3695 ( .A0(n2312), .A1(n3254), .B0(n2311), .Y(op_result[15]) );
OAI21XLTS U3696 ( .A0(n2313), .A1(n945), .B0(n1089), .Y(n2314) );
XOR2XLTS U3697 ( .A(FPMULT_Op_MX[20]), .B(n2314), .Y(mult_x_69_n617) );
OAI21XLTS U3698 ( .A0(n1105), .A1(n945), .B0(n2315), .Y(n2316) );
XOR2XLTS U3699 ( .A(FPMULT_Op_MX[14]), .B(n2316), .Y(mult_x_69_n671) );
OAI21XLTS U3700 ( .A0(n1013), .A1(n945), .B0(n1099), .Y(n2317) );
XOR2XLTS U3701 ( .A(FPMULT_Op_MX[5]), .B(n2317), .Y(mult_x_69_n752) );
OAI21XLTS U3702 ( .A0(n1010), .A1(n945), .B0(n1095), .Y(n2319) );
XOR2XLTS U3703 ( .A(n1046), .B(n2319), .Y(mult_x_69_n644) );
OAI21XLTS U3704 ( .A0(n1007), .A1(n945), .B0(n1097), .Y(n2320) );
XOR2XLTS U3705 ( .A(FPMULT_Op_MX[11]), .B(n2320), .Y(mult_x_69_n698) );
AOI21X1TS U3706 ( .A0(FPMULT_Op_MX[0]), .A1(n944), .B0(FPMULT_Op_MX[1]), .Y(
n2322) );
OAI21XLTS U3707 ( .A0(n2698), .A1(n945), .B0(n1720), .Y(n2323) );
XOR2XLTS U3708 ( .A(FPMULT_Op_MX[8]), .B(n2323), .Y(mult_x_69_n725) );
OAI22X1TS U3709 ( .A0(n2745), .A1(n1088), .B0(n2705), .B1(n2749), .Y(n2328)
);
OAI22X1TS U3710 ( .A0(n2481), .A1(n1021), .B0(n3223), .B1(n1087), .Y(n2326)
);
OAI21XLTS U3711 ( .A0(n2328), .A1(n2326), .B0(n2324), .Y(n2325) );
OAI31X1TS U3712 ( .A0(n2328), .A1(n2327), .A2(n2326), .B0(n2325), .Y(
mult_x_69_n630) );
AO21XLTS U3713 ( .A0(n3033), .A1(FPMULT_FS_Module_state_reg[1]), .B0(n2329),
.Y(FPMULT_FSM_barrel_shifter_load) );
NAND2X1TS U3714 ( .A(n966), .B(n3173), .Y(FPADDSUB__6_net_) );
OAI22X1TS U3715 ( .A0(n3224), .A1(n1098), .B0(n1013), .B1(n2749), .Y(n2332)
);
OAI22X1TS U3716 ( .A0(n2481), .A1(n994), .B0(n3223), .B1(n989), .Y(n2331) );
OAI21XLTS U3717 ( .A0(n2332), .A1(n2331), .B0(n1326), .Y(n2330) );
OAI31X1TS U3718 ( .A0(n2332), .A1(n2777), .A2(n2331), .B0(n2330), .Y(
mult_x_69_n765) );
CMPR32X2TS U3719 ( .A(n2335), .B(n2334), .C(n2333), .CO(n2358), .S(n2336) );
INVX2TS U3720 ( .A(n2336), .Y(n2347) );
CMPR32X2TS U3721 ( .A(n2339), .B(n2338), .C(n2337), .CO(n2377), .S(n2340) );
INVX2TS U3722 ( .A(n2340), .Y(n2346) );
CMPR32X2TS U3723 ( .A(n2343), .B(n2342), .C(n2341), .CO(n2369), .S(n2344) );
INVX2TS U3724 ( .A(n2344), .Y(n2345) );
NOR4X1TS U3725 ( .A(n2348), .B(n2347), .C(n2346), .D(n2345), .Y(n2440) );
CMPR32X2TS U3726 ( .A(n2351), .B(n2350), .C(n2349), .CO(n2391), .S(n2352) );
INVX2TS U3727 ( .A(n2352), .Y(n2368) );
CMPR32X2TS U3728 ( .A(n2355), .B(n2354), .C(n2353), .CO(n2333), .S(n2356) );
INVX2TS U3729 ( .A(n2356), .Y(n2367) );
CMPR32X2TS U3730 ( .A(n2359), .B(n2358), .C(n2357), .CO(n2337), .S(n2360) );
INVX2TS U3731 ( .A(n2360), .Y(n2366) );
CMPR32X2TS U3732 ( .A(n2363), .B(n2362), .C(n2361), .CO(n2351), .S(n2364) );
INVX2TS U3733 ( .A(n2364), .Y(n2365) );
NOR4X1TS U3734 ( .A(n2368), .B(n2367), .C(n2366), .D(n2365), .Y(n2439) );
CMPR32X2TS U3735 ( .A(n2371), .B(n2370), .C(n2369), .CO(n2397), .S(n2372) );
INVX2TS U3736 ( .A(n2372), .Y(n2388) );
CMPR32X2TS U3737 ( .A(n2375), .B(n2374), .C(n2373), .CO(n2419), .S(n2376) );
INVX2TS U3738 ( .A(n2376), .Y(n2387) );
CMPR32X2TS U3739 ( .A(n2379), .B(n2378), .C(n2377), .CO(n2341), .S(n2380) );
INVX2TS U3740 ( .A(n2380), .Y(n2386) );
CMPR32X2TS U3741 ( .A(n2383), .B(n2382), .C(n2381), .CO(n1831), .S(n2384) );
INVX2TS U3742 ( .A(n2384), .Y(n2385) );
NOR4X1TS U3743 ( .A(n2388), .B(n2387), .C(n2386), .D(n2385), .Y(n2437) );
CMPR32X2TS U3744 ( .A(n2391), .B(n2390), .C(n2389), .CO(n2354), .S(n2392) );
INVX2TS U3745 ( .A(n2392), .Y(n2403) );
CMPR32X2TS U3746 ( .A(n2395), .B(n2394), .C(n2393), .CO(n2427), .S(n2396) );
INVX2TS U3747 ( .A(n2396), .Y(n2402) );
CMPR32X2TS U3748 ( .A(n2399), .B(n2398), .C(n2397), .CO(n2393), .S(n2400) );
INVX2TS U3749 ( .A(n2400), .Y(n2401) );
NOR3XLTS U3750 ( .A(n2403), .B(n2402), .C(n2401), .Y(n2436) );
CMPR32X2TS U3751 ( .A(n2406), .B(n2405), .C(n2404), .CO(n2381), .S(n2407) );
INVX2TS U3752 ( .A(n2407), .Y(n2418) );
OAI21XLTS U3753 ( .A0(n1023), .A1(n2409), .B0(n2410), .Y(n2408) );
CMPR32X2TS U3754 ( .A(n2414), .B(n2413), .C(n2412), .CO(n2362), .S(n2415) );
INVX2TS U3755 ( .A(n2415), .Y(n2416) );
NOR3XLTS U3756 ( .A(n2418), .B(n2417), .C(n2416), .Y(n2435) );
CMPR32X2TS U3757 ( .A(n2421), .B(n2420), .C(n2419), .CO(n2404), .S(n2422) );
INVX2TS U3758 ( .A(n2422), .Y(n2433) );
CMPR32X2TS U3759 ( .A(n2425), .B(n2424), .C(n2423), .CO(n2414), .S(n2426) );
INVX2TS U3760 ( .A(n2426), .Y(n2432) );
CMPR32X2TS U3761 ( .A(n2429), .B(n2428), .C(n2427), .CO(n2373), .S(n2430) );
INVX2TS U3762 ( .A(n2430), .Y(n2431) );
NOR3XLTS U3763 ( .A(n2433), .B(n2432), .C(n2431), .Y(n2434) );
AND4X1TS U3764 ( .A(n2437), .B(n2436), .C(n2435), .D(n2434), .Y(n2438) );
NAND3XLTS U3765 ( .A(n2440), .B(n2439), .C(n2438), .Y(n3274) );
XOR2XLTS U3766 ( .A(Data_2[31]), .B(Data_1[31]), .Y(n3276) );
INVX2TS U3767 ( .A(n2663), .Y(n2656) );
AO22XLTS U3768 ( .A0(n2656), .A1(FPSENCOS_d_ff1_Z[19]), .B0(n2660), .B1(
FPSENCOS_d_ff_Zn[19]), .Y(FPSENCOS_first_mux_Z[19]) );
AO22XLTS U3769 ( .A0(n2656), .A1(FPSENCOS_d_ff1_Z[18]), .B0(n2651), .B1(
FPSENCOS_d_ff_Zn[18]), .Y(FPSENCOS_first_mux_Z[18]) );
OAI22X1TS U3770 ( .A0(n3230), .A1(n994), .B0(n3229), .B1(n990), .Y(n2443) );
OAI22X1TS U3771 ( .A0(n2451), .A1(n1098), .B0(n1014), .B1(n2684), .Y(n2442)
);
OAI21XLTS U3772 ( .A0(n2443), .A1(n2442), .B0(n3211), .Y(n2441) );
OAI31X1TS U3773 ( .A0(n2443), .A1(n2777), .A2(n2442), .B0(n2441), .Y(
mult_x_69_n764) );
NOR4X1TS U3774 ( .A(Data_1[12]), .B(Data_1[11]), .C(Data_1[10]), .D(
Data_1[9]), .Y(n2450) );
NOR4X1TS U3775 ( .A(Data_1[8]), .B(Data_1[7]), .C(Data_1[6]), .D(Data_1[0]),
.Y(n2449) );
NOR4X1TS U3776 ( .A(Data_1[3]), .B(Data_1[16]), .C(Data_1[1]), .D(Data_1[22]), .Y(n2447) );
NOR3XLTS U3777 ( .A(Data_1[2]), .B(Data_1[5]), .C(Data_1[4]), .Y(n2446) );
NOR4X1TS U3778 ( .A(Data_1[21]), .B(Data_1[19]), .C(Data_1[14]), .D(
Data_1[20]), .Y(n2445) );
NOR4X1TS U3779 ( .A(Data_1[13]), .B(Data_1[15]), .C(Data_1[17]), .D(
Data_1[18]), .Y(n2444) );
AND4X1TS U3780 ( .A(n2447), .B(n2446), .C(n2445), .D(n2444), .Y(n2448) );
NAND3XLTS U3781 ( .A(n2450), .B(n2449), .C(n2448), .Y(n3272) );
OAI22X1TS U3782 ( .A0(n3218), .A1(n2468), .B0(n1013), .B1(n2715), .Y(n2454)
);
OAI22X1TS U3783 ( .A0(n2451), .A1(n994), .B0(n3224), .B1(n989), .Y(n2453) );
OAI21XLTS U3784 ( .A0(n2454), .A1(n2453), .B0(n1464), .Y(n2452) );
OAI31X1TS U3785 ( .A0(n2454), .A1(n2777), .A2(n2453), .B0(n2452), .Y(
mult_x_69_n766) );
AO22XLTS U3786 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n851), .B0(n862), .B1(
n3062), .Y(n852) );
AO22XLTS U3787 ( .A0(n2656), .A1(FPSENCOS_d_ff1_Z[20]), .B0(n2660), .B1(
FPSENCOS_d_ff_Zn[20]), .Y(FPSENCOS_first_mux_Z[20]) );
AOI22X1TS U3788 ( .A0(n2613), .A1(FPSENCOS_d_ff2_X[22]), .B0(n2541), .B1(
FPSENCOS_d_ff2_Z[22]), .Y(n2456) );
AOI22X1TS U3789 ( .A0(FPSENCOS_d_ff2_Y[22]), .A1(n2633), .B0(Data_1[22]),
.B1(n2563), .Y(n2455) );
NAND2X1TS U3790 ( .A(n2456), .B(n2455), .Y(add_subt_data1[22]) );
INVX2TS U3791 ( .A(n2663), .Y(n3030) );
AO22XLTS U3792 ( .A0(n3030), .A1(FPSENCOS_d_ff1_Z[22]), .B0(n2655), .B1(
FPSENCOS_d_ff_Zn[22]), .Y(FPSENCOS_first_mux_Z[22]) );
AO22XLTS U3793 ( .A0(n3030), .A1(FPSENCOS_d_ff1_Z[30]), .B0(n2660), .B1(
FPSENCOS_d_ff_Zn[30]), .Y(FPSENCOS_first_mux_Z[30]) );
OAI22X1TS U3794 ( .A0(n2683), .A1(n1099), .B0(n1014), .B1(n2679), .Y(n2459)
);
OAI22X1TS U3795 ( .A0(n2700), .A1(n996), .B0(n3115), .B1(n990), .Y(n2458) );
OAI21XLTS U3796 ( .A0(n2459), .A1(n2458), .B0(n2472), .Y(n2457) );
OAI31X1TS U3797 ( .A0(n2459), .A1(n2475), .A2(n2458), .B0(n2457), .Y(
mult_x_69_n762) );
INVX2TS U3798 ( .A(n2644), .Y(n2661) );
AO22XLTS U3799 ( .A0(n2661), .A1(FPSENCOS_d_ff1_Z[29]), .B0(n2644), .B1(
FPSENCOS_d_ff_Zn[29]), .Y(FPSENCOS_first_mux_Z[29]) );
XNOR2X1TS U3800 ( .A(FPADDSUB_DMP_EXP_EWSW[27]), .B(
FPADDSUB_DmP_EXP_EWSW[27]), .Y(n2460) );
XOR2XLTS U3801 ( .A(n2461), .B(n2460), .Y(FPADDSUB_Shift_amount_EXP_EW[4])
);
AO22XLTS U3802 ( .A0(n2656), .A1(FPSENCOS_d_ff1_Z[28]), .B0(n2651), .B1(
FPSENCOS_d_ff_Zn[28]), .Y(FPSENCOS_first_mux_Z[28]) );
OAI22X1TS U3803 ( .A0(n1066), .A1(n2468), .B0(n1013), .B1(n2688), .Y(n2465)
);
OAI22X1TS U3804 ( .A0(n2462), .A1(n995), .B0(n3222), .B1(n989), .Y(n2464) );
OAI31X1TS U3805 ( .A0(n2465), .A1(n2475), .A2(n2464), .B0(n2463), .Y(
mult_x_69_n761) );
CMPR32X2TS U3806 ( .A(n3216), .B(FPADDSUB_DMP_EXP_EWSW[26]), .C(n2466), .CO(
n2461), .S(FPADDSUB_Shift_amount_EXP_EW[3]) );
AO22XLTS U3807 ( .A0(n3030), .A1(FPSENCOS_d_ff1_Z[27]), .B0(n2655), .B1(
FPSENCOS_d_ff_Zn[27]), .Y(FPSENCOS_first_mux_Z[27]) );
CMPR32X2TS U3808 ( .A(n3214), .B(FPADDSUB_DMP_EXP_EWSW[25]), .C(n2467), .CO(
n2466), .S(FPADDSUB_Shift_amount_EXP_EW[2]) );
OAI22X1TS U3809 ( .A0(n2469), .A1(n1099), .B0(n2699), .B1(n1014), .Y(n2476)
);
OAI22X1TS U3810 ( .A0(n2471), .A1(n996), .B0(n3221), .B1(n990), .Y(n2474) );
OAI31X1TS U3811 ( .A0(n2476), .A1(n2475), .A2(n2474), .B0(n2473), .Y(
mult_x_69_n760) );
AO22XLTS U3812 ( .A0(n2656), .A1(FPSENCOS_d_ff1_Z[26]), .B0(n2660), .B1(
FPSENCOS_d_ff_Zn[26]), .Y(FPSENCOS_first_mux_Z[26]) );
AO22XLTS U3813 ( .A0(n3030), .A1(FPSENCOS_d_ff1_Z[25]), .B0(n2644), .B1(
FPSENCOS_d_ff_Zn[25]), .Y(FPSENCOS_first_mux_Z[25]) );
NOR2XLTS U3814 ( .A(FPSENCOS_d_ff2_X[29]), .B(n3055), .Y(n2477) );
XOR2XLTS U3815 ( .A(FPSENCOS_d_ff2_X[30]), .B(n2477), .Y(
FPSENCOS_sh_exp_x[7]) );
OAI22X1TS U3816 ( .A0(n2745), .A1(n1097), .B0(n1007), .B1(n2749), .Y(n2486)
);
OAI22X1TS U3817 ( .A0(n2481), .A1(n1005), .B0(n3223), .B1(n987), .Y(n2484)
);
OAI31X1TS U3818 ( .A0(n2486), .A1(n2485), .A2(n2484), .B0(n2483), .Y(
mult_x_69_n711) );
AO22XLTS U3819 ( .A0(n2661), .A1(FPSENCOS_d_ff1_Z[23]), .B0(n2663), .B1(
FPSENCOS_d_ff_Zn[23]), .Y(FPSENCOS_first_mux_Z[23]) );
NOR2XLTS U3820 ( .A(FPSENCOS_d_ff2_Y[29]), .B(n3054), .Y(n2487) );
XOR2XLTS U3821 ( .A(FPSENCOS_d_ff2_Y[30]), .B(n2487), .Y(
FPSENCOS_sh_exp_y[7]) );
AO21XLTS U3822 ( .A0(n2489), .A1(FPSENCOS_d_ff2_Y[27]), .B0(n2488), .Y(
FPSENCOS_sh_exp_y[4]) );
AOI21X1TS U3823 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n3048), .B0(n3047),
.Y(n861) );
OA21XLTS U3824 ( .A0(n943), .A1(n3050), .B0(n861), .Y(n853) );
AOI22X1TS U3825 ( .A0(n2549), .A1(FPSENCOS_d_ff3_sh_x_out[1]), .B0(n2835),
.B1(FPSENCOS_d_ff3_sh_y_out[1]), .Y(n2491) );
AOI22X1TS U3826 ( .A0(FPSENCOS_d_ff3_LUT_out[1]), .A1(n2634), .B0(Data_2[1]),
.B1(n2550), .Y(n2490) );
NAND2X1TS U3827 ( .A(n2491), .B(n2490), .Y(add_subt_data2[1]) );
AOI22X1TS U3828 ( .A0(n2560), .A1(FPSENCOS_d_ff3_sh_x_out[21]), .B0(n2545),
.B1(FPSENCOS_d_ff3_LUT_out[21]), .Y(n2493) );
AOI22X1TS U3829 ( .A0(FPSENCOS_d_ff3_sh_y_out[21]), .A1(n2546), .B0(
Data_2[21]), .B1(n2557), .Y(n2492) );
NAND2X1TS U3830 ( .A(n2493), .B(n2492), .Y(add_subt_data2[21]) );
CLKBUFX3TS U3831 ( .A(n1146), .Y(n2612) );
AOI22X1TS U3832 ( .A0(n2613), .A1(FPSENCOS_d_ff2_X[19]), .B0(n2612), .B1(
FPSENCOS_d_ff2_Z[19]), .Y(n2495) );
AOI22X1TS U3833 ( .A0(FPSENCOS_d_ff2_Y[19]), .A1(n2633), .B0(Data_1[19]),
.B1(n2563), .Y(n2494) );
NAND2X1TS U3834 ( .A(n2495), .B(n2494), .Y(add_subt_data1[19]) );
AOI22X1TS U3835 ( .A0(n2633), .A1(FPSENCOS_d_ff2_Y[11]), .B0(n2608), .B1(
FPSENCOS_d_ff2_Z[11]), .Y(n2497) );
AOI22X1TS U3836 ( .A0(FPSENCOS_d_ff2_X[11]), .A1(n2567), .B0(Data_1[11]),
.B1(n2614), .Y(n2496) );
NAND2X1TS U3837 ( .A(n2497), .B(n2496), .Y(add_subt_data1[11]) );
AOI22X1TS U3838 ( .A0(n2546), .A1(FPSENCOS_d_ff3_sh_y_out[26]), .B0(n2612),
.B1(FPSENCOS_d_ff3_LUT_out[26]), .Y(n2499) );
AOI22X1TS U3839 ( .A0(FPSENCOS_d_ff3_sh_x_out[26]), .A1(n2609), .B0(
Data_2[26]), .B1(n2557), .Y(n2498) );
NAND2X1TS U3840 ( .A(n2499), .B(n2498), .Y(add_subt_data2[26]) );
AOI22X1TS U3841 ( .A0(n2566), .A1(FPSENCOS_d_ff2_Y[24]), .B0(n2515), .B1(
FPSENCOS_d_ff2_X[24]), .Y(n2501) );
AOI22X1TS U3842 ( .A0(FPSENCOS_d_ff2_Z[24]), .A1(n2634), .B0(Data_1[24]),
.B1(n2563), .Y(n2500) );
NAND2X1TS U3843 ( .A(n2501), .B(n2500), .Y(add_subt_data1[24]) );
NAND2X1TS U3844 ( .A(n3184), .B(n3110), .Y(FPADDSUB_DMP_INIT_EWSW[30]) );
AOI22X1TS U3845 ( .A0(n2546), .A1(FPSENCOS_d_ff2_X[5]), .B0(n2612), .B1(
FPSENCOS_d_ff2_Z[5]), .Y(n2503) );
AOI22X1TS U3846 ( .A0(FPSENCOS_d_ff2_Y[5]), .A1(n2615), .B0(Data_1[5]), .B1(
n2557), .Y(n2502) );
NAND2X1TS U3847 ( .A(n2503), .B(n2502), .Y(add_subt_data1[5]) );
AOI22X1TS U3848 ( .A0(n2613), .A1(FPSENCOS_d_ff2_X[23]), .B0(n2608), .B1(
FPSENCOS_d_ff2_Z[23]), .Y(n2505) );
AOI22X1TS U3849 ( .A0(FPSENCOS_d_ff2_Y[23]), .A1(n2633), .B0(Data_1[23]),
.B1(n2563), .Y(n2504) );
NAND2X1TS U3850 ( .A(n2505), .B(n2504), .Y(add_subt_data1[23]) );
AOI22X1TS U3851 ( .A0(n2566), .A1(FPSENCOS_d_ff2_Y[3]), .B0(n2515), .B1(
FPSENCOS_d_ff2_X[3]), .Y(n2507) );
AOI22X1TS U3852 ( .A0(FPSENCOS_d_ff2_Z[3]), .A1(n2541), .B0(Data_1[3]), .B1(
n2557), .Y(n2506) );
NAND2X1TS U3853 ( .A(n2507), .B(n2506), .Y(add_subt_data1[3]) );
AOI22X1TS U3854 ( .A0(n2549), .A1(FPSENCOS_d_ff3_sh_x_out[12]), .B0(n2512),
.B1(FPSENCOS_d_ff3_sh_y_out[12]), .Y(n2509) );
AOI22X1TS U3855 ( .A0(FPSENCOS_d_ff3_LUT_out[12]), .A1(n2634), .B0(
Data_2[12]), .B1(n2550), .Y(n2508) );
NAND2X1TS U3856 ( .A(n2509), .B(n2508), .Y(add_subt_data2[12]) );
AOI22X1TS U3857 ( .A0(n2546), .A1(FPSENCOS_d_ff2_X[15]), .B0(n2608), .B1(
FPSENCOS_d_ff2_Z[15]), .Y(n2511) );
AOI22X1TS U3858 ( .A0(FPSENCOS_d_ff2_Y[15]), .A1(n2633), .B0(Data_1[15]),
.B1(n2563), .Y(n2510) );
NAND2X1TS U3859 ( .A(n2511), .B(n2510), .Y(add_subt_data1[15]) );
AOI22X1TS U3860 ( .A0(n2549), .A1(FPSENCOS_d_ff3_sh_x_out[6]), .B0(n2512),
.B1(FPSENCOS_d_ff3_sh_y_out[6]), .Y(n2514) );
AOI22X1TS U3861 ( .A0(FPSENCOS_d_ff3_LUT_out[6]), .A1(n2634), .B0(Data_2[6]),
.B1(n2550), .Y(n2513) );
NAND2X1TS U3862 ( .A(n2514), .B(n2513), .Y(add_subt_data2[6]) );
AOI22X1TS U3863 ( .A0(n2633), .A1(FPSENCOS_d_ff2_Y[17]), .B0(n2515), .B1(
FPSENCOS_d_ff2_X[17]), .Y(n2517) );
AOI22X1TS U3864 ( .A0(FPSENCOS_d_ff2_Z[17]), .A1(n2634), .B0(Data_1[17]),
.B1(n2563), .Y(n2516) );
NAND2X1TS U3865 ( .A(n2517), .B(n2516), .Y(add_subt_data1[17]) );
OAI32X1TS U3866 ( .A0(n2518), .A1(FPMULT_FS_Module_state_reg[1]), .A2(
FPMULT_FS_Module_state_reg[3]), .B0(FPMULT_FS_Module_state_reg[2]),
.B1(n2518), .Y(n2519) );
AO22XLTS U3867 ( .A0(n2521), .A1(n2520), .B0(n2519), .B1(n3035), .Y(
FPMULT_FS_Module_state_next[1]) );
AOI22X1TS U3868 ( .A0(n2613), .A1(FPSENCOS_d_ff2_X[12]), .B0(n2608), .B1(
FPSENCOS_d_ff2_Z[12]), .Y(n2523) );
AOI22X1TS U3869 ( .A0(FPSENCOS_d_ff2_Y[12]), .A1(n2836), .B0(Data_1[12]),
.B1(n2837), .Y(n2522) );
NAND2X1TS U3870 ( .A(n2523), .B(n2522), .Y(add_subt_data1[12]) );
AOI22X1TS U3871 ( .A0(n2613), .A1(FPSENCOS_d_ff2_X[7]), .B0(n2612), .B1(
FPSENCOS_d_ff2_Z[7]), .Y(n2525) );
AOI22X1TS U3872 ( .A0(FPSENCOS_d_ff2_Y[7]), .A1(n2836), .B0(Data_1[7]), .B1(
n2614), .Y(n2524) );
NAND2X1TS U3873 ( .A(n2525), .B(n2524), .Y(add_subt_data1[7]) );
AOI22X1TS U3874 ( .A0(n2546), .A1(FPSENCOS_d_ff2_X[1]), .B0(n2612), .B1(
FPSENCOS_d_ff2_Z[1]), .Y(n2527) );
AOI22X1TS U3875 ( .A0(FPSENCOS_d_ff2_Y[1]), .A1(n2609), .B0(Data_1[1]), .B1(
n2557), .Y(n2526) );
NAND2X1TS U3876 ( .A(n2527), .B(n2526), .Y(add_subt_data1[1]) );
AOI22X1TS U3877 ( .A0(n2566), .A1(FPSENCOS_d_ff2_Y[18]), .B0(n2608), .B1(
FPSENCOS_d_ff2_Z[18]), .Y(n2529) );
AOI22X1TS U3878 ( .A0(FPSENCOS_d_ff2_X[18]), .A1(n2567), .B0(Data_1[18]),
.B1(n2563), .Y(n2528) );
NAND2X1TS U3879 ( .A(n2529), .B(n2528), .Y(add_subt_data1[18]) );
AO21XLTS U3880 ( .A0(n2531), .A1(FPMULT_FSM_selector_B[1]), .B0(n2530), .Y(
n829) );
AOI22X1TS U3881 ( .A0(n2566), .A1(FPSENCOS_d_ff2_Y[25]), .B0(n2541), .B1(
FPSENCOS_d_ff2_Z[25]), .Y(n2533) );
AOI22X1TS U3882 ( .A0(FPSENCOS_d_ff2_X[25]), .A1(n2567), .B0(Data_1[25]),
.B1(n2563), .Y(n2532) );
NAND2X1TS U3883 ( .A(n2533), .B(n2532), .Y(add_subt_data1[25]) );
AOI21X1TS U3884 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[20]), .A1(
FPADDSUB_DMP_SFG[18]), .B0(n2534), .Y(n2538) );
AOI22X1TS U3885 ( .A0(FPADDSUB_OP_FLAG_SFG), .A1(n2536), .B0(n2535), .B1(
n2991), .Y(n2537) );
XOR2XLTS U3886 ( .A(n2538), .B(n2537), .Y(FPADDSUB_Raw_mant_SGF[20]) );
XOR2XLTS U3887 ( .A(n3053), .B(n3082), .Y(n843) );
AOI22X1TS U3888 ( .A0(n2560), .A1(FPSENCOS_d_ff2_Y[0]), .B0(n2835), .B1(
FPSENCOS_d_ff2_X[0]), .Y(n2540) );
AOI22X1TS U3889 ( .A0(FPSENCOS_d_ff2_Z[0]), .A1(n2541), .B0(Data_1[0]), .B1(
n2557), .Y(n2539) );
NAND2X1TS U3890 ( .A(n2540), .B(n2539), .Y(add_subt_data1[0]) );
AOI22X1TS U3891 ( .A0(n2542), .A1(FPSENCOS_d_ff2_Y[27]), .B0(n2541), .B1(
FPSENCOS_d_ff2_Z[27]), .Y(n2544) );
AOI22X1TS U3892 ( .A0(FPSENCOS_d_ff2_X[27]), .A1(n2567), .B0(Data_1[27]),
.B1(n3037), .Y(n2543) );
NAND2X1TS U3893 ( .A(n2544), .B(n2543), .Y(add_subt_data1[27]) );
AOI22X1TS U3894 ( .A0(n2560), .A1(FPSENCOS_d_ff3_sh_x_out[23]), .B0(n2545),
.B1(FPSENCOS_d_ff3_LUT_out[23]), .Y(n2548) );
AOI22X1TS U3895 ( .A0(FPSENCOS_d_ff3_sh_y_out[23]), .A1(n2546), .B0(
Data_2[23]), .B1(n2550), .Y(n2547) );
NAND2X1TS U3896 ( .A(n2548), .B(n2547), .Y(add_subt_data2[23]) );
AOI22X1TS U3897 ( .A0(n2549), .A1(FPSENCOS_d_ff3_sh_x_out[2]), .B0(n2835),
.B1(FPSENCOS_d_ff3_sh_y_out[2]), .Y(n2552) );
AOI22X1TS U3898 ( .A0(FPSENCOS_d_ff3_LUT_out[2]), .A1(n2634), .B0(Data_2[2]),
.B1(n2550), .Y(n2551) );
NAND2X1TS U3899 ( .A(n2552), .B(n2551), .Y(add_subt_data2[2]) );
AOI22X1TS U3900 ( .A0(n2613), .A1(FPSENCOS_d_ff2_X[8]), .B0(n2612), .B1(
FPSENCOS_d_ff2_Z[8]), .Y(n2554) );
AOI22X1TS U3901 ( .A0(FPSENCOS_d_ff2_Y[8]), .A1(n2609), .B0(Data_1[8]), .B1(
n2837), .Y(n2553) );
NAND2X1TS U3902 ( .A(n2554), .B(n2553), .Y(add_subt_data1[8]) );
AOI22X1TS U3903 ( .A0(n2613), .A1(FPSENCOS_d_ff2_X[29]), .B0(n2612), .B1(
FPSENCOS_d_ff2_Z[29]), .Y(n2556) );
AOI22X1TS U3904 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n2633), .B0(Data_1[29]),
.B1(n3037), .Y(n2555) );
NAND2X1TS U3905 ( .A(n2556), .B(n2555), .Y(add_subt_data1[29]) );
AOI22X1TS U3906 ( .A0(n2560), .A1(FPSENCOS_d_ff2_Y[4]), .B0(n2612), .B1(
FPSENCOS_d_ff2_Z[4]), .Y(n2559) );
AOI22X1TS U3907 ( .A0(FPSENCOS_d_ff2_X[4]), .A1(n2567), .B0(Data_1[4]), .B1(
n2557), .Y(n2558) );
NAND2X1TS U3908 ( .A(n2559), .B(n2558), .Y(add_subt_data1[4]) );
AOI22X1TS U3909 ( .A0(n2560), .A1(FPSENCOS_d_ff2_Y[26]), .B0(n2608), .B1(
FPSENCOS_d_ff2_Z[26]), .Y(n2562) );
AOI22X1TS U3910 ( .A0(FPSENCOS_d_ff2_X[26]), .A1(n2567), .B0(Data_1[26]),
.B1(n3037), .Y(n2561) );
NAND2X1TS U3911 ( .A(n2562), .B(n2561), .Y(add_subt_data1[26]) );
AOI22X1TS U3912 ( .A0(n2566), .A1(FPSENCOS_d_ff2_Y[20]), .B0(n2608), .B1(
FPSENCOS_d_ff2_Z[20]), .Y(n2565) );
AOI22X1TS U3913 ( .A0(FPSENCOS_d_ff2_X[20]), .A1(n2567), .B0(Data_1[20]),
.B1(n2563), .Y(n2564) );
NAND2X1TS U3914 ( .A(n2565), .B(n2564), .Y(add_subt_data1[20]) );
AOI22X1TS U3915 ( .A0(n2566), .A1(FPSENCOS_d_ff2_Y[6]), .B0(n2612), .B1(
FPSENCOS_d_ff2_Z[6]), .Y(n2569) );
AOI22X1TS U3916 ( .A0(FPSENCOS_d_ff2_X[6]), .A1(n2567), .B0(Data_1[6]), .B1(
n2614), .Y(n2568) );
NAND2X1TS U3917 ( .A(n2569), .B(n2568), .Y(add_subt_data1[6]) );
CLKAND2X2TS U3918 ( .A(n1073), .B(FPADDSUB_sftr_odat_SHT2_SWR[2]), .Y(
FPADDSUB_formatted_number_W[0]) );
CLKAND2X2TS U3919 ( .A(n1074), .B(FPADDSUB_sftr_odat_SHT2_SWR[3]), .Y(
FPADDSUB_formatted_number_W[1]) );
CLKAND2X2TS U3920 ( .A(n1075), .B(FPADDSUB_sftr_odat_SHT2_SWR[4]), .Y(
FPADDSUB_formatted_number_W[2]) );
CLKAND2X2TS U3921 ( .A(n1073), .B(FPADDSUB_sftr_odat_SHT2_SWR[5]), .Y(
FPADDSUB_formatted_number_W[3]) );
CLKAND2X2TS U3922 ( .A(n1074), .B(FPADDSUB_sftr_odat_SHT2_SWR[6]), .Y(
FPADDSUB_formatted_number_W[4]) );
CLKAND2X2TS U3923 ( .A(n1075), .B(FPADDSUB_sftr_odat_SHT2_SWR[7]), .Y(
FPADDSUB_formatted_number_W[5]) );
CLKAND2X2TS U3924 ( .A(n1073), .B(FPADDSUB_sftr_odat_SHT2_SWR[8]), .Y(
FPADDSUB_formatted_number_W[6]) );
CLKAND2X2TS U3925 ( .A(n1074), .B(FPADDSUB_sftr_odat_SHT2_SWR[9]), .Y(
FPADDSUB_formatted_number_W[7]) );
INVX2TS U3926 ( .A(n2570), .Y(n2585) );
OR2X1TS U3927 ( .A(n2571), .B(n2585), .Y(n2576) );
AO22XLTS U3928 ( .A0(n962), .A1(FPADDSUB_Data_array_SWR[49]), .B0(n1102),
.B1(FPADDSUB_Data_array_SWR[41]), .Y(n2572) );
AOI211X1TS U3929 ( .A0(n959), .A1(FPADDSUB_Data_array_SWR[45]), .B0(n2576),
.C0(n2572), .Y(n2590) );
AOI22X1TS U3930 ( .A0(FPADDSUB_Data_array_SWR[44]), .A1(n961), .B0(
FPADDSUB_Data_array_SWR[36]), .B1(n1102), .Y(n2573) );
OAI21XLTS U3931 ( .A0(n3198), .A1(n2583), .B0(n2573), .Y(n2574) );
AOI211X1TS U3932 ( .A0(FPADDSUB_Data_array_SWR[40]), .A1(n960), .B0(n2585),
.C0(n2574), .Y(n2591) );
AOI22X1TS U3933 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2590), .B0(n2591),
.B1(n967), .Y(FPADDSUB_sftr_odat_SHT2_SWR[10]) );
CLKAND2X2TS U3934 ( .A(n1075), .B(FPADDSUB_sftr_odat_SHT2_SWR[10]), .Y(
FPADDSUB_formatted_number_W[8]) );
AOI211X1TS U3935 ( .A0(FPADDSUB_Data_array_SWR[48]), .A1(n961), .B0(n2576),
.C0(n2575), .Y(n2588) );
AOI22X1TS U3936 ( .A0(n960), .A1(FPADDSUB_Data_array_SWR[41]), .B0(n1102),
.B1(FPADDSUB_Data_array_SWR[37]), .Y(n2577) );
OAI21XLTS U3937 ( .A0(n2583), .A1(n3207), .B0(n2577), .Y(n2578) );
AOI211X1TS U3938 ( .A0(n961), .A1(FPADDSUB_Data_array_SWR[45]), .B0(n2585),
.C0(n2578), .Y(n2589) );
AOI22X1TS U3939 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2588), .B0(n2589),
.B1(n967), .Y(FPADDSUB_sftr_odat_SHT2_SWR[11]) );
CLKAND2X2TS U3940 ( .A(n1073), .B(FPADDSUB_sftr_odat_SHT2_SWR[11]), .Y(
FPADDSUB_formatted_number_W[9]) );
AOI22X1TS U3941 ( .A0(n960), .A1(FPADDSUB_Data_array_SWR[43]), .B0(n1102),
.B1(FPADDSUB_Data_array_SWR[39]), .Y(n2579) );
OAI21XLTS U3942 ( .A0(n2583), .A1(n3108), .B0(n2579), .Y(n2580) );
AOI211X1TS U3943 ( .A0(n961), .A1(FPADDSUB_Data_array_SWR[47]), .B0(n2585),
.C0(n2580), .Y(n2586) );
AOI22X1TS U3944 ( .A0(n961), .A1(FPADDSUB_Data_array_SWR[46]), .B0(n1102),
.B1(FPADDSUB_Data_array_SWR[38]), .Y(n2582) );
OAI21XLTS U3945 ( .A0(n2583), .A1(n3109), .B0(n2582), .Y(n2584) );
AOI211X1TS U3946 ( .A0(n959), .A1(FPADDSUB_Data_array_SWR[42]), .B0(n2585),
.C0(n2584), .Y(n2587) );
AOI22X1TS U3947 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2586), .B0(n2587),
.B1(n967), .Y(FPADDSUB_sftr_odat_SHT2_SWR[12]) );
CLKAND2X2TS U3948 ( .A(n1074), .B(FPADDSUB_sftr_odat_SHT2_SWR[12]), .Y(
FPADDSUB_formatted_number_W[10]) );
AOI22X1TS U3949 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2587), .B0(n2586),
.B1(n967), .Y(FPADDSUB_sftr_odat_SHT2_SWR[13]) );
CLKAND2X2TS U3950 ( .A(n1075), .B(FPADDSUB_sftr_odat_SHT2_SWR[13]), .Y(
FPADDSUB_formatted_number_W[11]) );
AOI22X1TS U3951 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2589), .B0(n2588),
.B1(n967), .Y(FPADDSUB_sftr_odat_SHT2_SWR[14]) );
CLKAND2X2TS U3952 ( .A(n1073), .B(FPADDSUB_sftr_odat_SHT2_SWR[14]), .Y(
FPADDSUB_formatted_number_W[12]) );
AOI22X1TS U3953 ( .A0(FPADDSUB_left_right_SHT2), .A1(n2591), .B0(n2590),
.B1(n967), .Y(FPADDSUB_sftr_odat_SHT2_SWR[15]) );
CLKAND2X2TS U3954 ( .A(n1074), .B(FPADDSUB_sftr_odat_SHT2_SWR[15]), .Y(
FPADDSUB_formatted_number_W[13]) );
CLKAND2X2TS U3955 ( .A(n1075), .B(FPADDSUB_sftr_odat_SHT2_SWR[16]), .Y(
FPADDSUB_formatted_number_W[14]) );
CLKAND2X2TS U3956 ( .A(n1073), .B(FPADDSUB_sftr_odat_SHT2_SWR[17]), .Y(
FPADDSUB_formatted_number_W[15]) );
CLKAND2X2TS U3957 ( .A(n1074), .B(FPADDSUB_sftr_odat_SHT2_SWR[18]), .Y(
FPADDSUB_formatted_number_W[16]) );
CLKAND2X2TS U3958 ( .A(n1075), .B(FPADDSUB_sftr_odat_SHT2_SWR[19]), .Y(
FPADDSUB_formatted_number_W[17]) );
CLKAND2X2TS U3959 ( .A(n1073), .B(FPADDSUB_sftr_odat_SHT2_SWR[20]), .Y(
FPADDSUB_formatted_number_W[18]) );
CLKAND2X2TS U3960 ( .A(n1074), .B(FPADDSUB_sftr_odat_SHT2_SWR[21]), .Y(
FPADDSUB_formatted_number_W[19]) );
CLKAND2X2TS U3961 ( .A(n1075), .B(FPADDSUB_sftr_odat_SHT2_SWR[22]), .Y(
FPADDSUB_formatted_number_W[20]) );
CLKAND2X2TS U3962 ( .A(n1073), .B(FPADDSUB_sftr_odat_SHT2_SWR[23]), .Y(
FPADDSUB_formatted_number_W[21]) );
CLKAND2X2TS U3963 ( .A(n1074), .B(FPADDSUB_sftr_odat_SHT2_SWR[24]), .Y(
FPADDSUB_formatted_number_W[22]) );
AOI2BB1XLTS U3964 ( .A0N(FPADDSUB_SIGN_FLAG_SHT1SHT2), .A1N(n3495), .B0(
n3496), .Y(FPADDSUB_formatted_number_W[31]) );
OR2X1TS U3965 ( .A(FPADDSUB_ADD_OVRFLW_NRM2), .B(
FPADDSUB_LZD_output_NRM2_EW[0]), .Y(n2593) );
XOR2X1TS U3966 ( .A(n3116), .B(n2593), .Y(DP_OP_26J196_122_5882_n18) );
NOR2BX1TS U3967 ( .AN(FPADDSUB_LZD_output_NRM2_EW[1]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n2594) );
XOR2X1TS U3968 ( .A(n3116), .B(n2594), .Y(DP_OP_26J196_122_5882_n17) );
NOR2BX1TS U3969 ( .AN(FPADDSUB_LZD_output_NRM2_EW[2]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n2595) );
XOR2X1TS U3970 ( .A(n3116), .B(n2595), .Y(DP_OP_26J196_122_5882_n16) );
NOR2BX1TS U3971 ( .AN(FPADDSUB_LZD_output_NRM2_EW[3]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n2596) );
XOR2X1TS U3972 ( .A(n3116), .B(n2596), .Y(DP_OP_26J196_122_5882_n15) );
NOR2BX1TS U3973 ( .AN(FPADDSUB_LZD_output_NRM2_EW[4]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n2597) );
XOR2X1TS U3974 ( .A(n3116), .B(n2597), .Y(DP_OP_26J196_122_5882_n14) );
OAI222X1TS U3975 ( .A0(n3022), .A1(n975), .B0(n2600), .B1(n2599), .C0(n3021),
.C1(n2598), .Y(FPADDSUB_Data_array_SWR[23]) );
AO22XLTS U3976 ( .A0(n1107), .A1(FPADDSUB_LZD_raw_out_EWR[2]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[2]), .B1(n3079), .Y(
FPADDSUB_shft_value_mux_o_EWR[2]) );
AOI21X1TS U3977 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[22]), .A1(
FPADDSUB_DMP_SFG[20]), .B0(n2603), .Y(n2607) );
AOI22X1TS U3978 ( .A0(FPADDSUB_OP_FLAG_SFG), .A1(n2605), .B0(n2604), .B1(
n2991), .Y(n2606) );
XOR2XLTS U3979 ( .A(n2607), .B(n2606), .Y(FPADDSUB_Raw_mant_SGF[22]) );
AOI22X1TS U3980 ( .A0(n2613), .A1(FPSENCOS_d_ff2_X[14]), .B0(n2608), .B1(
FPSENCOS_d_ff2_Z[14]), .Y(n2611) );
AOI22X1TS U3981 ( .A0(FPSENCOS_d_ff2_Y[14]), .A1(n2609), .B0(Data_1[14]),
.B1(n2837), .Y(n2610) );
NAND2X1TS U3982 ( .A(n2611), .B(n2610), .Y(add_subt_data1[14]) );
AOI22X1TS U3983 ( .A0(n2613), .A1(FPSENCOS_d_ff2_X[10]), .B0(n2612), .B1(
FPSENCOS_d_ff2_Z[10]), .Y(n2617) );
AOI22X1TS U3984 ( .A0(FPSENCOS_d_ff2_Y[10]), .A1(n2615), .B0(Data_1[10]),
.B1(n2614), .Y(n2616) );
NAND2X1TS U3985 ( .A(n2617), .B(n2616), .Y(add_subt_data1[10]) );
AO22XLTS U3986 ( .A0(busy), .A1(FPADDSUB_OP_FLAG_SHT1), .B0(n3173), .B1(
FPADDSUB_OP_FLAG_SHT2), .Y(n813) );
AO22XLTS U3987 ( .A0(busy), .A1(FPADDSUB_SIGN_FLAG_SHT1), .B0(n3173), .B1(
FPADDSUB_SIGN_FLAG_SHT2), .Y(n819) );
AO22XLTS U3988 ( .A0(n2664), .A1(FPSENCOS_d_ff1_Z[3]), .B0(n2655), .B1(
FPSENCOS_d_ff_Zn[3]), .Y(FPSENCOS_first_mux_Z[3]) );
OA21XLTS U3989 ( .A0(FPMULT_Sgf_normalized_result[8]), .A1(n2828), .B0(n2827), .Y(FPMULT_Adder_M_result_A_adder[8]) );
AO22XLTS U3990 ( .A0(n2664), .A1(FPSENCOS_d_ff1_Z[0]), .B0(n2651), .B1(
FPSENCOS_d_ff_Zn[0]), .Y(FPSENCOS_first_mux_Z[0]) );
AO22XLTS U3991 ( .A0(n2661), .A1(FPSENCOS_d_ff1_Z[9]), .B0(n2660), .B1(
FPSENCOS_d_ff_Zn[9]), .Y(FPSENCOS_first_mux_Z[9]) );
OA21XLTS U3992 ( .A0(FPMULT_Sgf_normalized_result[6]), .A1(n2830), .B0(n2829), .Y(FPMULT_Adder_M_result_A_adder[6]) );
AO21XLTS U3993 ( .A0(n2832), .A1(FPMULT_Sgf_normalized_result[4]), .B0(n2831), .Y(FPMULT_Adder_M_result_A_adder[4]) );
AO22XLTS U3994 ( .A0(n2656), .A1(FPSENCOS_d_ff1_Z[13]), .B0(n2655), .B1(
FPSENCOS_d_ff_Zn[13]), .Y(FPSENCOS_first_mux_Z[13]) );
AO22XLTS U3995 ( .A0(n2656), .A1(FPSENCOS_d_ff1_Z[17]), .B0(n2660), .B1(
FPSENCOS_d_ff_Zn[17]), .Y(FPSENCOS_first_mux_Z[17]) );
AO21XLTS U3996 ( .A0(FPMULT_Sgf_normalized_result[2]), .A1(n2618), .B0(n2833), .Y(FPMULT_Adder_M_result_A_adder[2]) );
AO22XLTS U3997 ( .A0(n2661), .A1(FPSENCOS_d_ff1_Z[16]), .B0(n2655), .B1(
FPSENCOS_d_ff_Zn[16]), .Y(FPSENCOS_first_mux_Z[16]) );
AO22XLTS U3998 ( .A0(n2664), .A1(FPSENCOS_d_ff1_Z[2]), .B0(n2644), .B1(
FPSENCOS_d_ff_Zn[2]), .Y(FPSENCOS_first_mux_Z[2]) );
AO22XLTS U3999 ( .A0(n2656), .A1(FPSENCOS_d_ff1_Z[21]), .B0(n2644), .B1(
FPSENCOS_d_ff_Zn[21]), .Y(FPSENCOS_first_mux_Z[21]) );
AO22XLTS U4000 ( .A0(n3030), .A1(FPSENCOS_d_ff1_Z[24]), .B0(n2655), .B1(
FPSENCOS_d_ff_Zn[24]), .Y(FPSENCOS_first_mux_Z[24]) );
AO22XLTS U4001 ( .A0(n865), .A1(n3049), .B0(n3056), .B1(n2619), .Y(n848) );
XOR2XLTS U4002 ( .A(n3077), .B(FPSENCOS_d_ff1_shift_region_flag_out[1]), .Y(
n2620) );
XOR2XLTS U4003 ( .A(n3113), .B(n2620), .Y(n2621) );
CLKBUFX2TS U4004 ( .A(n2621), .Y(n2623) );
CLKBUFX2TS U4005 ( .A(n2623), .Y(n2627) );
INVX2TS U4006 ( .A(n2627), .Y(n2622) );
CLKBUFX3TS U4007 ( .A(n2623), .Y(n2624) );
AO22XLTS U4008 ( .A0(n2622), .A1(FPSENCOS_d_ff_Xn[7]), .B0(n2624), .B1(
FPSENCOS_d_ff_Yn[7]), .Y(FPSENCOS_mux_sal[7]) );
AO22XLTS U4009 ( .A0(n2622), .A1(FPSENCOS_d_ff_Xn[6]), .B0(n3001), .B1(
FPSENCOS_d_ff_Yn[6]), .Y(FPSENCOS_mux_sal[6]) );
INVX2TS U4010 ( .A(n2623), .Y(n2625) );
AO22XLTS U4011 ( .A0(n2625), .A1(FPSENCOS_d_ff_Xn[3]), .B0(n3001), .B1(
FPSENCOS_d_ff_Yn[3]), .Y(FPSENCOS_mux_sal[3]) );
AO22XLTS U4012 ( .A0(n2625), .A1(FPSENCOS_d_ff_Xn[1]), .B0(n3001), .B1(
FPSENCOS_d_ff_Yn[1]), .Y(FPSENCOS_mux_sal[1]) );
AO22XLTS U4013 ( .A0(n2625), .A1(FPSENCOS_d_ff_Xn[0]), .B0(n2623), .B1(
FPSENCOS_d_ff_Yn[0]), .Y(FPSENCOS_mux_sal[0]) );
OA21XLTS U4014 ( .A0(FPMULT_Sgf_normalized_result[10]), .A1(n2826), .B0(
n2825), .Y(FPMULT_Adder_M_result_A_adder[10]) );
INVX2TS U4015 ( .A(n2627), .Y(n2628) );
AO22XLTS U4016 ( .A0(n2628), .A1(FPSENCOS_d_ff_Xn[9]), .B0(n2624), .B1(
FPSENCOS_d_ff_Yn[9]), .Y(FPSENCOS_mux_sal[9]) );
AO22XLTS U4017 ( .A0(n2628), .A1(FPSENCOS_d_ff_Xn[12]), .B0(n2624), .B1(
FPSENCOS_d_ff_Yn[12]), .Y(FPSENCOS_mux_sal[12]) );
AO22XLTS U4018 ( .A0(n2628), .A1(FPSENCOS_d_ff_Xn[10]), .B0(n2624), .B1(
FPSENCOS_d_ff_Yn[10]), .Y(FPSENCOS_mux_sal[10]) );
INVX2TS U4019 ( .A(n3001), .Y(n3002) );
AO22XLTS U4020 ( .A0(n3002), .A1(FPSENCOS_d_ff_Xn[8]), .B0(n2624), .B1(
FPSENCOS_d_ff_Yn[8]), .Y(FPSENCOS_mux_sal[8]) );
AO22XLTS U4021 ( .A0(n2628), .A1(FPSENCOS_d_ff_Xn[11]), .B0(n2624), .B1(
FPSENCOS_d_ff_Yn[11]), .Y(FPSENCOS_mux_sal[11]) );
AO22XLTS U4022 ( .A0(n2628), .A1(FPSENCOS_d_ff_Xn[14]), .B0(n2624), .B1(
FPSENCOS_d_ff_Yn[14]), .Y(FPSENCOS_mux_sal[14]) );
AO22XLTS U4023 ( .A0(n2628), .A1(FPSENCOS_d_ff_Xn[13]), .B0(n2624), .B1(
FPSENCOS_d_ff_Yn[13]), .Y(FPSENCOS_mux_sal[13]) );
AO22XLTS U4024 ( .A0(n2625), .A1(FPSENCOS_d_ff_Xn[5]), .B0(n3001), .B1(
FPSENCOS_d_ff_Yn[5]), .Y(FPSENCOS_mux_sal[5]) );
AO22XLTS U4025 ( .A0(n2625), .A1(FPSENCOS_d_ff_Xn[15]), .B0(n2624), .B1(
FPSENCOS_d_ff_Yn[15]), .Y(FPSENCOS_mux_sal[15]) );
AO22XLTS U4026 ( .A0(n2625), .A1(FPSENCOS_d_ff_Xn[4]), .B0(n3001), .B1(
FPSENCOS_d_ff_Yn[4]), .Y(FPSENCOS_mux_sal[4]) );
CLKBUFX3TS U4027 ( .A(n2623), .Y(n2662) );
AO22XLTS U4028 ( .A0(n2625), .A1(FPSENCOS_d_ff_Xn[17]), .B0(n2662), .B1(
FPSENCOS_d_ff_Yn[17]), .Y(FPSENCOS_mux_sal[17]) );
AO22XLTS U4029 ( .A0(n3002), .A1(FPSENCOS_d_ff_Xn[20]), .B0(n2662), .B1(
FPSENCOS_d_ff_Yn[20]), .Y(FPSENCOS_mux_sal[20]) );
AO22XLTS U4030 ( .A0(n2625), .A1(FPSENCOS_d_ff_Xn[18]), .B0(n2662), .B1(
FPSENCOS_d_ff_Yn[18]), .Y(FPSENCOS_mux_sal[18]) );
AO22XLTS U4031 ( .A0(n2625), .A1(FPSENCOS_d_ff_Xn[16]), .B0(n2624), .B1(
FPSENCOS_d_ff_Yn[16]), .Y(FPSENCOS_mux_sal[16]) );
AO22XLTS U4032 ( .A0(n2625), .A1(FPSENCOS_d_ff_Xn[2]), .B0(n3001), .B1(
FPSENCOS_d_ff_Yn[2]), .Y(FPSENCOS_mux_sal[2]) );
AO22XLTS U4033 ( .A0(n3002), .A1(FPSENCOS_d_ff_Xn[21]), .B0(n2662), .B1(
FPSENCOS_d_ff_Yn[21]), .Y(FPSENCOS_mux_sal[21]) );
AO22XLTS U4034 ( .A0(n3002), .A1(FPSENCOS_d_ff_Xn[19]), .B0(n2662), .B1(
FPSENCOS_d_ff_Yn[19]), .Y(FPSENCOS_mux_sal[19]) );
AO22XLTS U4035 ( .A0(n3002), .A1(FPSENCOS_d_ff_Xn[22]), .B0(n2662), .B1(
FPSENCOS_d_ff_Yn[22]), .Y(FPSENCOS_mux_sal[22]) );
AO21XLTS U4036 ( .A0(n2626), .A1(n3044), .B0(FPSENCOS_enab_RB3), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]) );
AO22XLTS U4037 ( .A0(n3002), .A1(FPSENCOS_d_ff_Xn[30]), .B0(n2627), .B1(
FPSENCOS_d_ff_Yn[30]), .Y(FPSENCOS_mux_sal[30]) );
AO22XLTS U4038 ( .A0(n2628), .A1(FPSENCOS_d_ff_Xn[29]), .B0(n2627), .B1(
FPSENCOS_d_ff_Yn[29]), .Y(FPSENCOS_mux_sal[29]) );
AO22XLTS U4039 ( .A0(n2628), .A1(FPSENCOS_d_ff_Xn[28]), .B0(n2627), .B1(
FPSENCOS_d_ff_Yn[28]), .Y(FPSENCOS_mux_sal[28]) );
AO22XLTS U4040 ( .A0(n2628), .A1(FPSENCOS_d_ff_Xn[27]), .B0(n2627), .B1(
FPSENCOS_d_ff_Yn[27]), .Y(FPSENCOS_mux_sal[27]) );
AO22XLTS U4041 ( .A0(n2628), .A1(FPSENCOS_d_ff_Xn[26]), .B0(n2662), .B1(
FPSENCOS_d_ff_Yn[26]), .Y(FPSENCOS_mux_sal[26]) );
AO22XLTS U4042 ( .A0(n3002), .A1(FPSENCOS_d_ff_Xn[25]), .B0(n2662), .B1(
FPSENCOS_d_ff_Yn[25]), .Y(FPSENCOS_mux_sal[25]) );
AO22XLTS U4043 ( .A0(n3002), .A1(FPSENCOS_d_ff_Xn[24]), .B0(n2662), .B1(
FPSENCOS_d_ff_Yn[24]), .Y(FPSENCOS_mux_sal[24]) );
AO22XLTS U4044 ( .A0(n2656), .A1(FPSENCOS_d_ff1_Z[31]), .B0(n2660), .B1(
FPSENCOS_d_ff_Zn[31]), .Y(FPSENCOS_first_mux_Z[31]) );
INVX2TS U4045 ( .A(n2629), .Y(n2632) );
AOI211X1TS U4046 ( .A0(n2632), .A1(n2631), .B0(n2630), .C0(n2997), .Y(n2996)
);
AO21XLTS U4047 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[25]), .A1(n2974), .B0(n2996),
.Y(n3497) );
MX2X1TS U4048 ( .A(FPMULT_Op_MX[23]), .B(FPMULT_exp_oper_result[0]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[0]) );
MX2X1TS U4049 ( .A(FPMULT_Op_MX[25]), .B(FPMULT_exp_oper_result[2]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[2]) );
MX2X1TS U4050 ( .A(FPMULT_Op_MX[26]), .B(FPMULT_exp_oper_result[3]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[3]) );
MX2X1TS U4051 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_exp_oper_result[4]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[4]) );
MX2X1TS U4052 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_exp_oper_result[5]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[5]) );
MX2X1TS U4053 ( .A(FPMULT_Op_MX[29]), .B(FPMULT_exp_oper_result[6]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[6]) );
MX2X1TS U4054 ( .A(FPMULT_Op_MX[30]), .B(FPMULT_exp_oper_result[7]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[7]) );
CLKAND2X2TS U4055 ( .A(FPMULT_exp_oper_result[8]), .B(FPMULT_FSM_selector_A),
.Y(FPMULT_S_Oper_A_exp[8]) );
AOI22X1TS U4056 ( .A0(n2633), .A1(FPSENCOS_d_ff2_Y[31]), .B0(n2515), .B1(
FPSENCOS_d_ff2_X[31]), .Y(n2636) );
AOI22X1TS U4057 ( .A0(FPSENCOS_d_ff2_Z[31]), .A1(n2634), .B0(Data_1[31]),
.B1(n3037), .Y(n2635) );
NAND2X1TS U4058 ( .A(n2636), .B(n2635), .Y(add_subt_data1[31]) );
OA21XLTS U4059 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n2814), .B0(
n2813), .Y(FPMULT_Adder_M_result_A_adder[22]) );
OA21XLTS U4060 ( .A0(FPMULT_Sgf_normalized_result[20]), .A1(n2816), .B0(
n2815), .Y(FPMULT_Adder_M_result_A_adder[20]) );
AO22XLTS U4061 ( .A0(n1111), .A1(FPADDSUB_SIGN_FLAG_NRM), .B0(n3079), .B1(
FPADDSUB_SIGN_FLAG_SHT1SHT2), .Y(n816) );
OA21XLTS U4062 ( .A0(FPMULT_Sgf_normalized_result[18]), .A1(n2818), .B0(
n2817), .Y(FPMULT_Adder_M_result_A_adder[18]) );
OA21XLTS U4063 ( .A0(FPMULT_Sgf_normalized_result[16]), .A1(n2820), .B0(
n2819), .Y(FPMULT_Adder_M_result_A_adder[16]) );
OA21XLTS U4064 ( .A0(FPMULT_Sgf_normalized_result[14]), .A1(n2822), .B0(
n2821), .Y(FPMULT_Adder_M_result_A_adder[14]) );
OA21XLTS U4065 ( .A0(FPMULT_Sgf_normalized_result[12]), .A1(n2824), .B0(
n2823), .Y(FPMULT_Adder_M_result_A_adder[12]) );
NOR2XLTS U4066 ( .A(n2637), .B(n3204), .Y(n2640) );
AO22XLTS U4067 ( .A0(n2641), .A1(n2640), .B0(n2639), .B1(n2638), .Y(
FPADDSUB_LZD_raw_out_EWR[3]) );
AO22XLTS U4068 ( .A0(n1108), .A1(FPADDSUB_LZD_raw_out_EWR[3]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[3]), .B1(n3079), .Y(
FPADDSUB_shft_value_mux_o_EWR[3]) );
AO22XLTS U4069 ( .A0(n2661), .A1(FPSENCOS_d_ff1_Z[7]), .B0(n2644), .B1(
FPSENCOS_d_ff_Zn[7]), .Y(FPSENCOS_first_mux_Z[7]) );
AOI2BB1XLTS U4070 ( .A0N(n3491), .A1N(underflow_flag_mult), .B0(n2778), .Y(
FPMULT_final_result_ieee_Module_Sign_S_mux) );
AO22XLTS U4071 ( .A0(n2661), .A1(FPSENCOS_d_ff1_Z[6]), .B0(n2655), .B1(
FPSENCOS_d_ff_Zn[6]), .Y(FPSENCOS_first_mux_Z[6]) );
OAI222X1TS U4072 ( .A0(n2784), .A1(FPMULT_zero_flag), .B0(n2642), .B1(
FPMULT_P_Sgf[47]), .C0(FPMULT_FS_Module_state_reg[2]), .C1(n923), .Y(
FPMULT_FS_Module_state_next[0]) );
CMPR32X2TS U4073 ( .A(n3215), .B(FPADDSUB_DMP_EXP_EWSW[24]), .C(n2643), .CO(
n2467), .S(FPADDSUB_Shift_amount_EXP_EW[1]) );
AO22XLTS U4074 ( .A0(n2664), .A1(FPSENCOS_d_ff1_Z[1]), .B0(n2644), .B1(
FPSENCOS_d_ff_Zn[1]), .Y(FPSENCOS_first_mux_Z[1]) );
AO22XLTS U4075 ( .A0(n2661), .A1(FPSENCOS_d_ff1_Z[12]), .B0(n2663), .B1(
FPSENCOS_d_ff_Zn[12]), .Y(FPSENCOS_first_mux_Z[12]) );
AO21XLTS U4076 ( .A0(n2646), .A1(FPSENCOS_d_ff2_X[27]), .B0(n2645), .Y(
FPSENCOS_sh_exp_x[4]) );
AOI32X1TS U4077 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[2]), .A1(n2991), .A2(
FPADDSUB_DMP_SFG[0]), .B0(n2647), .B1(n2997), .Y(n2650) );
OAI21XLTS U4078 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[3]), .A1(FPADDSUB_DMP_SFG[1]), .B0(n2648), .Y(n2649) );
XOR2XLTS U4079 ( .A(n2650), .B(n2649), .Y(FPADDSUB_Raw_mant_SGF[3]) );
AO22XLTS U4080 ( .A0(n2661), .A1(FPSENCOS_d_ff1_Z[14]), .B0(n2651), .B1(
FPSENCOS_d_ff_Zn[14]), .Y(FPSENCOS_first_mux_Z[14]) );
AO22XLTS U4081 ( .A0(n2664), .A1(FPSENCOS_d_ff1_Z[5]), .B0(n2663), .B1(
FPSENCOS_d_ff_Zn[5]), .Y(FPSENCOS_first_mux_Z[5]) );
AO22XLTS U4082 ( .A0(n2661), .A1(FPSENCOS_d_ff1_Z[11]), .B0(n2644), .B1(
FPSENCOS_d_ff_Zn[11]), .Y(FPSENCOS_first_mux_Z[11]) );
CMPR32X2TS U4083 ( .A(FPSENCOS_d_ff2_X[26]), .B(n3080), .C(n2652), .CO(n2646), .S(FPSENCOS_sh_exp_x[3]) );
CMPR32X2TS U4084 ( .A(FPSENCOS_d_ff2_X[25]), .B(n3062), .C(n2653), .CO(n2652), .S(FPSENCOS_sh_exp_x[2]) );
CMPR32X2TS U4085 ( .A(n3056), .B(FPSENCOS_d_ff2_X[24]), .C(n2654), .CO(n2653), .S(FPSENCOS_sh_exp_x[1]) );
AO22XLTS U4086 ( .A0(n2656), .A1(FPSENCOS_d_ff1_Z[15]), .B0(n2655), .B1(
FPSENCOS_d_ff_Zn[15]), .Y(FPSENCOS_first_mux_Z[15]) );
AO22XLTS U4087 ( .A0(n1109), .A1(FPADDSUB_LZD_raw_out_EWR[4]), .B0(
FPADDSUB_Shift_amount_SHT1_EWR[4]), .B1(n966), .Y(
FPADDSUB_shft_value_mux_o_EWR[4]) );
AO22XLTS U4088 ( .A0(n2664), .A1(FPSENCOS_d_ff1_Z[8]), .B0(n2644), .B1(
FPSENCOS_d_ff_Zn[8]), .Y(FPSENCOS_first_mux_Z[8]) );
CMPR32X2TS U4089 ( .A(FPSENCOS_d_ff2_Y[26]), .B(n3080), .C(n2657), .CO(n2489), .S(FPSENCOS_sh_exp_y[3]) );
CMPR32X2TS U4090 ( .A(FPSENCOS_d_ff2_Y[25]), .B(n3062), .C(n2658), .CO(n2657), .S(FPSENCOS_sh_exp_y[2]) );
CMPR32X2TS U4091 ( .A(n3056), .B(FPSENCOS_d_ff2_Y[24]), .C(n2659), .CO(n2658), .S(FPSENCOS_sh_exp_y[1]) );
AO22XLTS U4092 ( .A0(n2661), .A1(FPSENCOS_d_ff1_Z[10]), .B0(n2660), .B1(
FPSENCOS_d_ff_Zn[10]), .Y(FPSENCOS_first_mux_Z[10]) );
AO22XLTS U4093 ( .A0(n3002), .A1(FPSENCOS_d_ff_Xn[23]), .B0(n2662), .B1(
FPSENCOS_d_ff_Yn[23]), .Y(FPSENCOS_mux_sal[23]) );
AO22XLTS U4094 ( .A0(n2664), .A1(FPSENCOS_d_ff1_Z[4]), .B0(n2655), .B1(
FPSENCOS_d_ff_Zn[4]), .Y(FPSENCOS_first_mux_Z[4]) );
NOR3BX1TS U4095 ( .AN(n2665), .B(n3068), .C(n1031), .Y(mult_x_69_n390) );
NOR3BX1TS U4096 ( .AN(n2666), .B(n2725), .C(n934), .Y(mult_x_69_n474) );
NOR3BX1TS U4097 ( .AN(n2667), .B(n1298), .C(n932), .Y(mult_x_69_n441) );
OAI22X1TS U4098 ( .A0(n1067), .A1(n1078), .B0(n1033), .B1(n2764), .Y(n2671)
);
OAI22X1TS U4099 ( .A0(n2752), .A1(n2750), .B0(n2689), .B1(n2668), .Y(n2670)
);
OAI21XLTS U4100 ( .A0(n2671), .A1(n2670), .B0(n2765), .Y(n2669) );
OAI31X1TS U4101 ( .A0(n2671), .A1(n2768), .A2(n2670), .B0(n2669), .Y(
mult_x_69_n736) );
OAI22X1TS U4102 ( .A0(n1100), .A1(n2757), .B0(n1051), .B1(n2733), .Y(n2678)
);
OAI22X1TS U4103 ( .A0(n2675), .A1(n1069), .B0(n1106), .B1(n2738), .Y(n2677)
);
OAI21XLTS U4104 ( .A0(n2678), .A1(n2677), .B0(n3212), .Y(n2676) );
OAI31X1TS U4105 ( .A0(n2678), .A1(n3362), .A2(n2677), .B0(n2676), .Y(
mult_x_69_n693) );
OAI22X1TS U4106 ( .A0(n2683), .A1(n2750), .B0(n2698), .B1(n2679), .Y(n2682)
);
OAI22X1TS U4107 ( .A0(n2700), .A1(n1076), .B0(n3115), .B1(n1064), .Y(n2681)
);
OAI21XLTS U4108 ( .A0(n2682), .A1(n2681), .B0(n2701), .Y(n2680) );
OAI31X1TS U4109 ( .A0(n2682), .A1(n2768), .A2(n2681), .B0(n2680), .Y(
mult_x_69_n735) );
OAI22X1TS U4110 ( .A0(n2683), .A1(n1077), .B0(n3229), .B1(n1063), .Y(n2687)
);
OAI22X1TS U4111 ( .A0(n2714), .A1(n2750), .B0(n2689), .B1(n2684), .Y(n2686)
);
OAI21XLTS U4112 ( .A0(n2687), .A1(n2686), .B0(n2765), .Y(n2685) );
OAI31X1TS U4113 ( .A0(n2687), .A1(n2768), .A2(n2686), .B0(n2685), .Y(
mult_x_69_n737) );
OAI22X1TS U4114 ( .A0(n1066), .A1(n2750), .B0(n2689), .B1(n2688), .Y(n2693)
);
OAI22X1TS U4115 ( .A0(n2690), .A1(n1078), .B0(n3222), .B1(n1064), .Y(n2692)
);
OAI31X1TS U4116 ( .A0(n2693), .A1(n3363), .A2(n2692), .B0(n2691), .Y(
mult_x_69_n734) );
OAI22X1TS U4117 ( .A0(n2771), .A1(n2772), .B0(n972), .B1(n2756), .Y(n2696)
);
OAI22X1TS U4118 ( .A0(n1057), .A1(n2722), .B0(n1103), .B1(n2694), .Y(n2695)
);
NOR2XLTS U4119 ( .A(n2696), .B(n2695), .Y(n2697) );
CMPR32X2TS U4120 ( .A(FPMULT_Op_MY[4]), .B(FPMULT_Op_MX[2]), .C(n2697), .CO(
mult_x_69_n303), .S(mult_x_69_n304) );
OAI22X1TS U4121 ( .A0(n2700), .A1(n2750), .B0(n2699), .B1(n2698), .Y(n2704)
);
OAI22X1TS U4122 ( .A0(n910), .A1(n1076), .B0(n3221), .B1(n2764), .Y(n2703)
);
OAI31X1TS U4123 ( .A0(n2704), .A1(n3363), .A2(n2703), .B0(n2702), .Y(
mult_x_69_n733) );
OAI22X1TS U4124 ( .A0(n1090), .A1(n2706), .B0(n2216), .B1(n2761), .Y(n2713)
);
OAI22X1TS U4125 ( .A0(n1085), .A1(n1048), .B0(n1022), .B1(n2770), .Y(n2712)
);
OAI21XLTS U4126 ( .A0(n2713), .A1(n2712), .B0(n2710), .Y(n2711) );
OAI31X1TS U4127 ( .A0(n2713), .A1(n3361), .A2(n2712), .B0(n2711), .Y(
mult_x_69_n637) );
OAI22X1TS U4128 ( .A0(n2714), .A1(n1077), .B0(n3224), .B1(n1064), .Y(n2718)
);
OAI22X1TS U4129 ( .A0(n2720), .A1(n2750), .B0(n2762), .B1(n2715), .Y(n2717)
);
OAI21XLTS U4130 ( .A0(n2718), .A1(n2717), .B0(n2765), .Y(n2716) );
OAI31X1TS U4131 ( .A0(n2718), .A1(n2768), .A2(n2717), .B0(n2716), .Y(
mult_x_69_n739) );
OAI22X1TS U4132 ( .A0(n2720), .A1(n1078), .B0(n1063), .B1(n2719), .Y(n2726)
);
OAI22X1TS U4133 ( .A0(n2763), .A1(n2722), .B0(n2762), .B1(n2721), .Y(n2724)
);
OAI21XLTS U4134 ( .A0(n2726), .A1(n2724), .B0(n2765), .Y(n2723) );
OAI31X1TS U4135 ( .A0(n2726), .A1(n2725), .A2(n2724), .B0(n2723), .Y(
mult_x_69_n741) );
OAI22X1TS U4136 ( .A0(n973), .A1(n3231), .B0(n1056), .B1(n1048), .Y(n2729)
);
OAI22X1TS U4137 ( .A0(n1061), .A1(n2757), .B0(n1104), .B1(n2727), .Y(n2728)
);
NOR2XLTS U4138 ( .A(n2729), .B(n2728), .Y(n2742) );
OAI22X1TS U4139 ( .A0(n2771), .A1(n1070), .B0(n1056), .B1(n2733), .Y(n2734)
);
AOI21X1TS U4140 ( .A0(n2775), .A1(FPMULT_Op_MY[0]), .B0(n2734), .Y(n2735) );
OAI21X1TS U4141 ( .A0(n1103), .A1(n2736), .B0(n2735), .Y(n2787) );
NOR2X1TS U4142 ( .A(n2790), .B(n2787), .Y(n2786) );
OAI22X1TS U4143 ( .A0(n1061), .A1(n2737), .B0(n972), .B1(n3060), .Y(n2740)
);
OAI22X1TS U4144 ( .A0(n1058), .A1(n3219), .B0(n1103), .B1(n2738), .Y(n2739)
);
NOR2XLTS U4145 ( .A(n2740), .B(n2739), .Y(n2743) );
CMPR32X2TS U4146 ( .A(FPMULT_Op_MY[1]), .B(n2742), .C(n2741), .CO(
mult_x_69_n336), .S(mult_x_69_n337) );
OAI22X1TS U4147 ( .A0(n2745), .A1(n1076), .B0(n2744), .B1(n2764), .Y(n2748)
);
OAI22X1TS U4148 ( .A0(n2763), .A1(n3225), .B0(n2762), .B1(n1035), .Y(n2747)
);
OAI21XLTS U4149 ( .A0(n2748), .A1(n2747), .B0(n3213), .Y(n2746) );
OAI31X1TS U4150 ( .A0(n2748), .A1(n2768), .A2(n2747), .B0(n2746), .Y(
mult_x_69_n740) );
OAI22X1TS U4151 ( .A0(n2751), .A1(n2750), .B0(n2762), .B1(n2749), .Y(n2755)
);
OAI22X1TS U4152 ( .A0(n2752), .A1(n1077), .B0(n3223), .B1(n1064), .Y(n2754)
);
OAI21XLTS U4153 ( .A0(n2755), .A1(n2754), .B0(n3213), .Y(n2753) );
OAI31X1TS U4154 ( .A0(n2755), .A1(n2768), .A2(n2754), .B0(n2753), .Y(
mult_x_69_n738) );
OAI22X1TS U4155 ( .A0(n1057), .A1(n2756), .B0(n1104), .B1(n2761), .Y(n2759)
);
OAI22X1TS U4156 ( .A0(n2771), .A1(n920), .B0(n973), .B1(n2757), .Y(n2758) );
NOR2XLTS U4157 ( .A(n2759), .B(n2758), .Y(n2760) );
CMPR32X2TS U4158 ( .A(FPMULT_Op_MY[2]), .B(FPMULT_Op_MX[2]), .C(n2760), .CO(
mult_x_69_n325), .S(mult_x_69_n326) );
OAI22X1TS U4159 ( .A0(n2763), .A1(n3219), .B0(n2762), .B1(n2761), .Y(n2769)
);
OAI22X1TS U4160 ( .A0(n1064), .A1(n1048), .B0(n1077), .B1(n2770), .Y(n2767)
);
OAI21XLTS U4161 ( .A0(n2769), .A1(n2767), .B0(n2765), .Y(n2766) );
OAI31X1TS U4162 ( .A0(n2769), .A1(n2768), .A2(n2767), .B0(n2766), .Y(
mult_x_69_n745) );
OAI22X1TS U4163 ( .A0(n1058), .A1(n2772), .B0(n1103), .B1(n1034), .Y(n2773)
);
AOI211X1TS U4164 ( .A0(FPMULT_Op_MY[4]), .A1(n2775), .B0(n2774), .C0(n2773),
.Y(n2776) );
CMPR32X2TS U4165 ( .A(FPMULT_Op_MY[3]), .B(FPMULT_Op_MX[2]), .C(n2776), .CO(
mult_x_69_n314), .S(mult_x_69_n315) );
CMPR32X2TS U4166 ( .A(n2777), .B(FPMULT_Op_MY[5]), .C(n3210), .CO(
mult_x_69_n292), .S(mult_x_69_n293) );
AO22XLTS U4167 ( .A0(operation[2]), .A1(n2778), .B0(n2783), .B1(
overflow_flag_addsubt), .Y(overflow_flag) );
OAI222X1TS U4168 ( .A0(n2782), .A1(n3123), .B0(n2282), .B1(n2781), .C0(n2780), .C1(n2779), .Y(operation_ready) );
AO22XLTS U4169 ( .A0(operation[2]), .A1(underflow_flag_mult), .B0(n2783),
.B1(underflow_flag_addsubt), .Y(underflow_flag) );
XNOR2X1TS U4170 ( .A(DP_OP_230J196_125_7006_n1), .B(n2784), .Y(
FPMULT_Exp_module_Overflow_A) );
OAI21XLTS U4171 ( .A0(n1111), .A1(n3116), .B0(n958), .Y(n810) );
NOR2BX1TS U4172 ( .AN(FPADDSUB_exp_rslt_NRM2_EW1[7]), .B(n3496), .Y(
FPADDSUB_formatted_number_W[30]) );
AOI21X1TS U4173 ( .A0(n2790), .A1(n2787), .B0(n2786), .Y(mult_x_69_n359) );
OAI22X1TS U4174 ( .A0(n1057), .A1(n3060), .B0(n1104), .B1(n2788), .Y(n2792)
);
INVX2TS U4175 ( .A(n2790), .Y(n2791) );
AOI21X1TS U4176 ( .A0(mult_x_69_n381), .A1(n2792), .B0(n2791), .Y(
mult_x_69_n370) );
AOI21X1TS U4177 ( .A0(n2795), .A1(n2794), .B0(n2793), .Y(mult_x_69_n409) );
AOI21X1TS U4178 ( .A0(n2798), .A1(n2797), .B0(n2796), .Y(mult_x_69_n419) );
AOI21X1TS U4179 ( .A0(n2801), .A1(n2800), .B0(n2799), .Y(mult_x_69_n454) );
AOI21X1TS U4180 ( .A0(n2804), .A1(n2803), .B0(n2802), .Y(mult_x_69_n461) );
CMPR32X2TS U4181 ( .A(n2807), .B(n2806), .C(n2805), .CO(n2812), .S(n2075) );
XNOR2X1TS U4182 ( .A(n2812), .B(n2811), .Y(FPMULT_Sgf_operation_Result[47])
);
AOI21X1TS U4183 ( .A0(n2813), .A1(n3186), .B0(
FPMULT_Adder_M_result_A_adder[24]), .Y(
FPMULT_Adder_M_result_A_adder[23]) );
AOI21X1TS U4184 ( .A0(n3162), .A1(n2815), .B0(n2814), .Y(
FPMULT_Adder_M_result_A_adder[21]) );
AOI21X1TS U4185 ( .A0(n3161), .A1(n2817), .B0(n2816), .Y(
FPMULT_Adder_M_result_A_adder[19]) );
AOI21X1TS U4186 ( .A0(n3160), .A1(n2819), .B0(n2818), .Y(
FPMULT_Adder_M_result_A_adder[17]) );
AOI21X1TS U4187 ( .A0(n3159), .A1(n2821), .B0(n2820), .Y(
FPMULT_Adder_M_result_A_adder[15]) );
AOI21X1TS U4188 ( .A0(n3158), .A1(n2823), .B0(n2822), .Y(
FPMULT_Adder_M_result_A_adder[13]) );
AOI21X1TS U4189 ( .A0(n3157), .A1(n2825), .B0(n2824), .Y(
FPMULT_Adder_M_result_A_adder[11]) );
AOI21X1TS U4190 ( .A0(n3156), .A1(n2827), .B0(n2826), .Y(
FPMULT_Adder_M_result_A_adder[9]) );
AOI21X1TS U4191 ( .A0(n3155), .A1(n2829), .B0(n2828), .Y(
FPMULT_Adder_M_result_A_adder[7]) );
AOI21X1TS U4192 ( .A0(n2831), .A1(n3164), .B0(n2830), .Y(
FPMULT_Adder_M_result_A_adder[5]) );
AOI21X1TS U4193 ( .A0(n2833), .A1(n3163), .B0(n2832), .Y(
FPMULT_Adder_M_result_A_adder[3]) );
NOR2BX1TS U4194 ( .AN(operation[0]), .B(n2837), .Y(n3502) );
AOI2BB2XLTS U4195 ( .B0(FPSENCOS_cont_var_out[0]), .B1(
FPSENCOS_d_ff3_sign_out), .A0N(FPSENCOS_d_ff3_sign_out), .A1N(
FPSENCOS_cont_var_out[0]), .Y(n2834) );
AO22XLTS U4196 ( .A0(n1017), .A1(n2834), .B0(n2837), .B1(operation[0]), .Y(
n2840) );
AOI222X1TS U4197 ( .A0(n2837), .A1(Data_2[31]), .B0(n2836), .B1(
FPSENCOS_d_ff3_sh_x_out[31]), .C0(FPSENCOS_d_ff3_sh_y_out[31]), .C1(
n2835), .Y(n2838) );
INVX2TS U4198 ( .A(n2838), .Y(n2839) );
XNOR2X1TS U4199 ( .A(n2840), .B(n2839), .Y(n3275) );
AOI22X1TS U4200 ( .A0(FPADDSUB_intDY_EWSW[29]), .A1(n3106), .B0(
FPADDSUB_intDY_EWSW[30]), .B1(n3184), .Y(n2880) );
NAND2X1TS U4201 ( .A(FPADDSUB_intDY_EWSW[27]), .B(n3084), .Y(n2875) );
AOI22X1TS U4202 ( .A0(FPADDSUB_intDX_EWSW[23]), .A1(n3085), .B0(
FPADDSUB_intDX_EWSW[22]), .B1(n3129), .Y(n2868) );
NOR2X1TS U4203 ( .A(FPADDSUB_intDX_EWSW[21]), .B(n3144), .Y(n2884) );
AOI22X1TS U4204 ( .A0(FPADDSUB_intDY_EWSW[22]), .A1(n3098), .B0(
FPADDSUB_intDY_EWSW[23]), .B1(n3131), .Y(n2866) );
OAI22X1TS U4205 ( .A0(FPADDSUB_intDY_EWSW[21]), .A1(n3073), .B0(
FPADDSUB_intDY_EWSW[20]), .B1(n3101), .Y(n2865) );
OA21XLTS U4206 ( .A0(n3145), .A1(FPADDSUB_intDX_EWSW[20]), .B0(n2866), .Y(
n2888) );
NOR2XLTS U4207 ( .A(FPADDSUB_intDX_EWSW[19]), .B(n3090), .Y(n2863) );
INVX2TS U4208 ( .A(FPADDSUB_intDY_EWSW[10]), .Y(n3010) );
OAI22X1TS U4209 ( .A0(n3010), .A1(FPADDSUB_intDX_EWSW[10]), .B0(n3070), .B1(
FPADDSUB_intDX_EWSW[11]), .Y(n2844) );
INVX2TS U4210 ( .A(n2844), .Y(n2843) );
NOR2X1TS U4211 ( .A(FPADDSUB_intDX_EWSW[9]), .B(n3058), .Y(n2845) );
AOI22X1TS U4212 ( .A0(FPADDSUB_intDX_EWSW[10]), .A1(n3010), .B0(
FPADDSUB_intDX_EWSW[9]), .B1(n3058), .Y(n2841) );
OAI31X1TS U4213 ( .A0(FPADDSUB_intDY_EWSW[8]), .A1(n2845), .A2(n3087), .B0(
n2841), .Y(n2842) );
AOI22X1TS U4214 ( .A0(n2843), .A1(n2842), .B0(FPADDSUB_intDX_EWSW[12]), .B1(
n3128), .Y(n2856) );
NAND2X1TS U4215 ( .A(FPADDSUB_intDY_EWSW[7]), .B(n3120), .Y(n2854) );
OAI22X1TS U4216 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n3120), .B0(
FPADDSUB_intDY_EWSW[6]), .B1(n3100), .Y(n2853) );
NOR2XLTS U4217 ( .A(FPADDSUB_intDX_EWSW[3]), .B(n3066), .Y(n2849) );
AOI22X1TS U4218 ( .A0(FPADDSUB_intDX_EWSW[3]), .A1(n3066), .B0(
FPADDSUB_intDX_EWSW[2]), .B1(n3086), .Y(n2848) );
AOI22X1TS U4219 ( .A0(FPADDSUB_intDY_EWSW[1]), .A1(n3064), .B0(
FPADDSUB_intDY_EWSW[3]), .B1(n3130), .Y(n2896) );
OAI22X1TS U4220 ( .A0(FPADDSUB_intDY_EWSW[1]), .A1(n3064), .B0(
FPADDSUB_intDY_EWSW[0]), .B1(n3083), .Y(n2846) );
NAND2X1TS U4221 ( .A(FPADDSUB_intDY_EWSW[4]), .B(n3105), .Y(n2882) );
AOI222X1TS U4222 ( .A0(n2850), .A1(n2882), .B0(n3088), .B1(
FPADDSUB_intDX_EWSW[5]), .C0(n3139), .C1(FPADDSUB_intDX_EWSW[4]), .Y(
n2851) );
OAI22X1TS U4223 ( .A0(FPADDSUB_intDX_EWSW[7]), .A1(n3099), .B0(
FPADDSUB_intDX_EWSW[6]), .B1(n3126), .Y(n2897) );
AOI211X1TS U4224 ( .A0(FPADDSUB_intDY_EWSW[5]), .A1(n3134), .B0(n2851), .C0(
n2897), .Y(n2852) );
AOI32X1TS U4225 ( .A0(n2854), .A1(n2889), .A2(n2853), .B0(n2852), .B1(n2889),
.Y(n2855) );
AOI22X1TS U4226 ( .A0(FPADDSUB_intDY_EWSW[12]), .A1(n3059), .B0(
FPADDSUB_intDY_EWSW[13]), .B1(n3074), .Y(n2894) );
AOI222X1TS U4227 ( .A0(n3057), .A1(FPADDSUB_intDX_EWSW[14]), .B0(n3132),
.B1(FPADDSUB_intDX_EWSW[13]), .C0(n2857), .C1(n2894), .Y(n2858) );
OAI22X1TS U4228 ( .A0(FPADDSUB_intDX_EWSW[15]), .A1(n3072), .B0(
FPADDSUB_intDX_EWSW[14]), .B1(n3057), .Y(n2893) );
OAI22X1TS U4229 ( .A0(n2858), .A1(n2893), .B0(FPADDSUB_intDY_EWSW[15]), .B1(
n3127), .Y(n2859) );
NAND2X1TS U4230 ( .A(FPADDSUB_intDY_EWSW[16]), .B(n3076), .Y(n2883) );
AOI222X1TS U4231 ( .A0(n2859), .A1(n2883), .B0(n3075), .B1(
FPADDSUB_intDX_EWSW[17]), .C0(n3140), .C1(FPADDSUB_intDX_EWSW[16]),
.Y(n2861) );
AOI22X1TS U4232 ( .A0(FPADDSUB_intDY_EWSW[17]), .A1(n3125), .B0(
FPADDSUB_intDY_EWSW[18]), .B1(n3065), .Y(n2860) );
OAI21X1TS U4233 ( .A0(FPADDSUB_intDX_EWSW[19]), .A1(n3090), .B0(n2860), .Y(
n2890) );
OA22X1TS U4234 ( .A0(n3143), .A1(FPADDSUB_intDY_EWSW[19]), .B0(n2861), .B1(
n2890), .Y(n2862) );
OAI31X1TS U4235 ( .A0(n2863), .A1(FPADDSUB_intDY_EWSW[18]), .A2(n3065), .B0(
n2862), .Y(n2864) );
AOI22X1TS U4236 ( .A0(n2866), .A1(n2865), .B0(n2888), .B1(n2864), .Y(n2867)
);
OAI22X1TS U4237 ( .A0(n2869), .A1(n2868), .B0(n2884), .B1(n2867), .Y(n2871)
);
NAND2X1TS U4238 ( .A(FPADDSUB_intDY_EWSW[24]), .B(n3137), .Y(n2870) );
AOI222X1TS U4239 ( .A0(n2871), .A1(n2870), .B0(n3133), .B1(
FPADDSUB_intDX_EWSW[25]), .C0(n3089), .C1(FPADDSUB_intDX_EWSW[24]),
.Y(n2873) );
AOI22X1TS U4240 ( .A0(FPADDSUB_intDY_EWSW[25]), .A1(n3071), .B0(
FPADDSUB_intDY_EWSW[26]), .B1(n3102), .Y(n2872) );
OAI21X1TS U4241 ( .A0(FPADDSUB_intDX_EWSW[27]), .A1(n3141), .B0(n2872), .Y(
n2898) );
OAI22X1TS U4242 ( .A0(n2873), .A1(n2898), .B0(FPADDSUB_intDY_EWSW[27]), .B1(
n3084), .Y(n2874) );
AOI31XLTS U4243 ( .A0(FPADDSUB_intDX_EWSW[26]), .A1(n2875), .A2(n3138), .B0(
n2874), .Y(n2877) );
NAND2X1TS U4244 ( .A(FPADDSUB_intDY_EWSW[28]), .B(n3152), .Y(n2879) );
INVX2TS U4245 ( .A(n2879), .Y(n2876) );
OAI222X1TS U4246 ( .A0(n3106), .A1(FPADDSUB_intDY_EWSW[29]), .B0(n3152),
.B1(FPADDSUB_intDY_EWSW[28]), .C0(n2877), .C1(n2876), .Y(n2878) );
INVX2TS U4247 ( .A(n3016), .Y(n3020) );
OAI211XLTS U4248 ( .A0(FPADDSUB_intDX_EWSW[24]), .A1(n3089), .B0(n2880),
.C0(n2879), .Y(n2892) );
NOR2XLTS U4249 ( .A(FPADDSUB_intDX_EWSW[5]), .B(n3088), .Y(n2886) );
NAND2X1TS U4250 ( .A(FPADDSUB_intDY_EWSW[2]), .B(n3136), .Y(n2881) );
NAND4BXLTS U4251 ( .AN(n2884), .B(n2883), .C(n2882), .D(n2881), .Y(n2885) );
AOI211XLTS U4252 ( .A0(FPADDSUB_intDY_EWSW[0]), .A1(n3083), .B0(n2886), .C0(
n2885), .Y(n2887) );
NAND4BXLTS U4253 ( .AN(n2890), .B(n2889), .C(n2888), .D(n2887), .Y(n2891) );
NOR4BX1TS U4254 ( .AN(n2894), .B(n2893), .C(n2892), .D(n2891), .Y(n2895) );
NAND4BBX1TS U4255 ( .AN(n2898), .BN(n2897), .C(n2896), .D(n2895), .Y(n2899)
);
AOI21X1TS U4256 ( .A0(n2899), .A1(n3013), .B0(FPADDSUB_intDX_EWSW[31]), .Y(
n2900) );
AOI21X1TS U4257 ( .A0(n3493), .A1(n3019), .B0(n2900), .Y(n3494) );
AOI22X1TS U4260 ( .A0(n943), .A1(n3056), .B0(FPSENCOS_cont_iter_out[2]),
.B1(n3050), .Y(FPSENCOS_data_out_LUT[4]) );
NOR4BX1TS U4261 ( .AN(operation_reg[1]), .B(dataB[28]), .C(operation_reg[0]),
.D(dataB[23]), .Y(n2905) );
NOR4X1TS U4262 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[25]),
.Y(n2904) );
NAND4XLTS U4263 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n2902) );
NAND4XLTS U4264 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n2901) );
OR3X1TS U4265 ( .A(n3487), .B(n2902), .C(n2901), .Y(n2906) );
AOI31XLTS U4266 ( .A0(n2905), .A1(n2904), .A2(n2903), .B0(dataB[27]), .Y(
n2916) );
NOR4X1TS U4267 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n2909) );
NOR4X1TS U4268 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n2908) );
NOR4BX1TS U4269 ( .AN(operation_reg[1]), .B(operation_reg[0]), .C(dataA[31]),
.D(n3487), .Y(n2907) );
NOR2X1TS U4270 ( .A(operation_reg[1]), .B(n2906), .Y(n2914) );
AOI31XLTS U4271 ( .A0(n2909), .A1(n2908), .A2(n2907), .B0(n2914), .Y(n2912)
);
NAND3XLTS U4272 ( .A(dataB[28]), .B(dataB[23]), .C(dataB[29]), .Y(n2911) );
NAND4XLTS U4273 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[25]),
.Y(n2910) );
OAI31X1TS U4274 ( .A0(n2912), .A1(n2911), .A2(n2910), .B0(dataB[27]), .Y(
n2913) );
NAND4XLTS U4275 ( .A(n3490), .B(n3489), .C(n3488), .D(n2913), .Y(n2915) );
OAI2BB2XLTS U4276 ( .B0(n2916), .B1(n2915), .A0N(n2914), .A1N(
operation_reg[0]), .Y(NaN_reg) );
NAND2X1TS U4277 ( .A(FPADDSUB_N59), .B(n2997), .Y(n2917) );
XNOR2X1TS U4278 ( .A(n2917), .B(FPADDSUB_N60), .Y(FPADDSUB_Raw_mant_SGF[1])
);
AOI2BB2XLTS U4279 ( .B0(n2919), .B1(n2991), .A0N(n3232), .A1N(n2918), .Y(
n2922) );
XNOR2X1TS U4280 ( .A(n2922), .B(n2921), .Y(FPADDSUB_Raw_mant_SGF[5]) );
AOI21X1TS U4281 ( .A0(n3091), .A1(FPADDSUB_DMP_SFG[5]), .B0(n2923), .Y(n2927) );
AOI2BB2XLTS U4282 ( .B0(n2925), .B1(n3232), .A0N(n3232), .A1N(n2924), .Y(
n2926) );
XNOR2X1TS U4283 ( .A(n2927), .B(n2926), .Y(FPADDSUB_Raw_mant_SGF[7]) );
OAI21XLTS U4284 ( .A0(n3170), .A1(FPADDSUB_DmP_mant_SFG_SWR[8]), .B0(n2928),
.Y(n2932) );
AOI2BB2XLTS U4285 ( .B0(n2930), .B1(n3232), .A0N(n2974), .A1N(n2929), .Y(
n2931) );
XNOR2X1TS U4286 ( .A(n2932), .B(n2931), .Y(FPADDSUB_Raw_mant_SGF[8]) );
AOI21X1TS U4287 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[9]), .A1(FPADDSUB_DMP_SFG[7]), .B0(n2933), .Y(n2937) );
AOI2BB2XLTS U4288 ( .B0(n2985), .B1(n2935), .A0N(n2934), .A1N(n2985), .Y(
n2936) );
XNOR2X1TS U4289 ( .A(n2937), .B(n2936), .Y(FPADDSUB_Raw_mant_SGF[9]) );
OAI21XLTS U4290 ( .A0(n3166), .A1(FPADDSUB_DmP_mant_SFG_SWR[10]), .B0(n2938),
.Y(n2942) );
AOI2BB2XLTS U4291 ( .B0(n2940), .B1(n3232), .A0N(n3232), .A1N(n2939), .Y(
n2941) );
XNOR2X1TS U4292 ( .A(n2942), .B(n2941), .Y(FPADDSUB_Raw_mant_SGF[10]) );
OA21XLTS U4293 ( .A0(n3096), .A1(FPADDSUB_DmP_mant_SFG_SWR[11]), .B0(n2943),
.Y(n2947) );
AOI22X1TS U4294 ( .A0(n2997), .A1(n2945), .B0(n2944), .B1(n3232), .Y(n2946)
);
XNOR2X1TS U4295 ( .A(n2947), .B(n2946), .Y(FPADDSUB_Raw_mant_SGF[11]) );
AOI22X1TS U4296 ( .A0(FPADDSUB_OP_FLAG_SFG), .A1(n2950), .B0(n2949), .B1(
n2974), .Y(n2951) );
XNOR2X1TS U4297 ( .A(n2952), .B(n2951), .Y(FPADDSUB_Raw_mant_SGF[12]) );
AOI21X1TS U4298 ( .A0(n3092), .A1(FPADDSUB_DMP_SFG[11]), .B0(n2953), .Y(
n2957) );
AOI22X1TS U4299 ( .A0(FPADDSUB_OP_FLAG_SFG), .A1(n2955), .B0(n2954), .B1(
n2974), .Y(n2956) );
XNOR2X1TS U4300 ( .A(n2957), .B(n2956), .Y(FPADDSUB_Raw_mant_SGF[13]) );
OAI21XLTS U4301 ( .A0(n3094), .A1(n3203), .B0(n2958), .Y(n2962) );
AOI2BB2XLTS U4302 ( .B0(n2985), .B1(n2960), .A0N(n2959), .A1N(n2985), .Y(
n2961) );
XNOR2X1TS U4303 ( .A(n2962), .B(n2961), .Y(FPADDSUB_Raw_mant_SGF[14]) );
AOI21X1TS U4304 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[15]), .A1(
FPADDSUB_DMP_SFG[13]), .B0(n2963), .Y(n2967) );
AOI2BB2XLTS U4305 ( .B0(n2985), .B1(n2965), .A0N(n2964), .A1N(n2985), .Y(
n2966) );
XNOR2X1TS U4306 ( .A(n2967), .B(n2966), .Y(FPADDSUB_Raw_mant_SGF[15]) );
OAI21XLTS U4307 ( .A0(n3167), .A1(FPADDSUB_DmP_mant_SFG_SWR[16]), .B0(n2968),
.Y(n2972) );
AOI2BB2XLTS U4308 ( .B0(n2970), .B1(n3232), .A0N(n2991), .A1N(n2969), .Y(
n2971) );
XNOR2X1TS U4309 ( .A(n2972), .B(n2971), .Y(FPADDSUB_Raw_mant_SGF[16]) );
OA21XLTS U4310 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[17]), .A1(n3095), .B0(n2973),
.Y(n2978) );
AOI22X1TS U4311 ( .A0(FPADDSUB_OP_FLAG_SFG), .A1(n2976), .B0(n2975), .B1(
n2974), .Y(n2977) );
XNOR2X1TS U4312 ( .A(n2978), .B(n2977), .Y(FPADDSUB_Raw_mant_SGF[17]) );
OAI21XLTS U4313 ( .A0(n3171), .A1(FPADDSUB_DmP_mant_SFG_SWR[18]), .B0(n2979),
.Y(n2983) );
AOI22X1TS U4314 ( .A0(FPADDSUB_OP_FLAG_SFG), .A1(n2981), .B0(n2980), .B1(
n3232), .Y(n2982) );
XNOR2X1TS U4315 ( .A(n2983), .B(n2982), .Y(FPADDSUB_Raw_mant_SGF[18]) );
AOI21X1TS U4316 ( .A0(FPADDSUB_DMP_SFG[17]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[19]), .B0(n2984), .Y(n2989) );
AOI2BB2XLTS U4317 ( .B0(n2985), .B1(n2987), .A0N(n2986), .A1N(n2985), .Y(
n2988) );
XNOR2X1TS U4318 ( .A(n2989), .B(n2988), .Y(FPADDSUB_Raw_mant_SGF[19]) );
AOI21X1TS U4319 ( .A0(n3185), .A1(n3093), .B0(n2990), .Y(n2995) );
AOI22X1TS U4320 ( .A0(FPADDSUB_OP_FLAG_SFG), .A1(n2993), .B0(n2992), .B1(
n2991), .Y(n2994) );
XNOR2X1TS U4321 ( .A(n2995), .B(n2994), .Y(FPADDSUB_Raw_mant_SGF[21]) );
AOI31X1TS U4322 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[24]), .A1(n2997), .A2(n3199),
.B0(n2996), .Y(n2999) );
AOI32X1TS U4323 ( .A0(FPADDSUB_DMP_SFG[22]), .A1(n2999), .A2(n3114), .B0(
n2998), .B1(n2999), .Y(n3000) );
XNOR2X1TS U4324 ( .A(FPADDSUB_DmP_mant_SFG_SWR[25]), .B(n3000), .Y(
FPADDSUB_Raw_mant_SGF[25]) );
AOI22X1TS U4325 ( .A0(n3002), .A1(FPSENCOS_d_ff_Xn[31]), .B0(
FPSENCOS_d_ff_Yn[31]), .B1(n3001), .Y(n3003) );
XNOR2X1TS U4326 ( .A(n3004), .B(n3003), .Y(FPSENCOS_fmtted_Result_31_) );
CLKBUFX2TS U4327 ( .A(n3016), .Y(n3015) );
CLKBUFX2TS U4328 ( .A(n3015), .Y(n3012) );
AOI22X1TS U4329 ( .A0(n3013), .A1(n3083), .B0(n3174), .B1(n3014), .Y(
FPADDSUB_DmP_INIT_EWSW[0]) );
AOI22X1TS U4330 ( .A0(n3019), .A1(n3064), .B0(n3175), .B1(n3014), .Y(
FPADDSUB_DmP_INIT_EWSW[1]) );
AOI22X1TS U4331 ( .A0(n3011), .A1(n3136), .B0(n3086), .B1(n3014), .Y(
FPADDSUB_DmP_INIT_EWSW[2]) );
AOI22X1TS U4332 ( .A0(n3020), .A1(n3130), .B0(n3066), .B1(n3014), .Y(
FPADDSUB_DmP_INIT_EWSW[3]) );
AOI22X1TS U4333 ( .A0(n3005), .A1(n3105), .B0(n3139), .B1(n3014), .Y(
FPADDSUB_DmP_INIT_EWSW[4]) );
INVX2TS U4334 ( .A(n3016), .Y(n3005) );
AOI22X1TS U4335 ( .A0(n3011), .A1(n3134), .B0(n3088), .B1(n3014), .Y(
FPADDSUB_DmP_INIT_EWSW[5]) );
AOI22X1TS U4336 ( .A0(n3007), .A1(n3100), .B0(n3126), .B1(n3014), .Y(
FPADDSUB_DmP_INIT_EWSW[6]) );
CLKBUFX3TS U4337 ( .A(n3015), .Y(n3006) );
AOI22X1TS U4338 ( .A0(n3020), .A1(n3120), .B0(n3099), .B1(n3006), .Y(
FPADDSUB_DmP_INIT_EWSW[7]) );
AOI22X1TS U4339 ( .A0(n3005), .A1(n3087), .B0(n3176), .B1(n3006), .Y(
FPADDSUB_DmP_INIT_EWSW[8]) );
AOI22X1TS U4340 ( .A0(n3007), .A1(n3177), .B0(n3058), .B1(n3006), .Y(
FPADDSUB_DmP_INIT_EWSW[9]) );
AOI22X1TS U4341 ( .A0(n3013), .A1(n3178), .B0(n3010), .B1(n3006), .Y(
FPADDSUB_DmP_INIT_EWSW[10]) );
AOI22X1TS U4342 ( .A0(n3019), .A1(n3142), .B0(n3070), .B1(n3006), .Y(
FPADDSUB_DmP_INIT_EWSW[11]) );
AOI22X1TS U4343 ( .A0(n3011), .A1(n3059), .B0(n3128), .B1(n3006), .Y(
FPADDSUB_DmP_INIT_EWSW[12]) );
AOI22X1TS U4344 ( .A0(n3020), .A1(n3074), .B0(n3132), .B1(n3006), .Y(
FPADDSUB_DmP_INIT_EWSW[13]) );
AOI22X1TS U4345 ( .A0(n3005), .A1(n3179), .B0(n3057), .B1(n3006), .Y(
FPADDSUB_DmP_INIT_EWSW[14]) );
AOI22X1TS U4346 ( .A0(n3007), .A1(n3127), .B0(n3072), .B1(n3006), .Y(
FPADDSUB_DmP_INIT_EWSW[15]) );
INVX2TS U4347 ( .A(n3016), .Y(n3007) );
AOI22X1TS U4348 ( .A0(n3005), .A1(n3076), .B0(n3140), .B1(n3006), .Y(
FPADDSUB_DmP_INIT_EWSW[16]) );
CLKBUFX3TS U4349 ( .A(n3012), .Y(n3008) );
AOI22X1TS U4350 ( .A0(n3007), .A1(n3125), .B0(n3075), .B1(n3008), .Y(
FPADDSUB_DmP_INIT_EWSW[17]) );
AOI22X1TS U4351 ( .A0(n3013), .A1(n3065), .B0(n3180), .B1(n3008), .Y(
FPADDSUB_DmP_INIT_EWSW[18]) );
AOI22X1TS U4352 ( .A0(n3019), .A1(n3143), .B0(n3090), .B1(n3008), .Y(
FPADDSUB_DmP_INIT_EWSW[19]) );
AOI22X1TS U4353 ( .A0(n3011), .A1(n3101), .B0(n3145), .B1(n3008), .Y(
FPADDSUB_DmP_INIT_EWSW[20]) );
AOI22X1TS U4354 ( .A0(n3020), .A1(n3073), .B0(n3144), .B1(n3008), .Y(
FPADDSUB_DmP_INIT_EWSW[21]) );
AOI22X1TS U4355 ( .A0(n3005), .A1(n3098), .B0(n3129), .B1(n3008), .Y(
FPADDSUB_DmP_INIT_EWSW[22]) );
AOI22X1TS U4356 ( .A0(n3007), .A1(n3131), .B0(n3085), .B1(n3008), .Y(
FPADDSUB_DmP_INIT_EWSW[23]) );
AOI22X1TS U4357 ( .A0(n3013), .A1(n3137), .B0(n3089), .B1(n3008), .Y(
FPADDSUB_DmP_INIT_EWSW[24]) );
AOI22X1TS U4358 ( .A0(n3019), .A1(n3071), .B0(n3133), .B1(n3008), .Y(
FPADDSUB_DmP_INIT_EWSW[25]) );
INVX2TS U4359 ( .A(n3016), .Y(n3013) );
AOI22X1TS U4360 ( .A0(n3013), .A1(n3102), .B0(n3138), .B1(n3008), .Y(
FPADDSUB_DmP_INIT_EWSW[26]) );
CLKBUFX3TS U4361 ( .A(n3012), .Y(n3009) );
AOI22X1TS U4362 ( .A0(n3019), .A1(n3084), .B0(n3141), .B1(n3009), .Y(
FPADDSUB_DmP_INIT_EWSW[27]) );
AOI22X1TS U4363 ( .A0(n3011), .A1(n3174), .B0(n3083), .B1(n3009), .Y(
FPADDSUB_DMP_INIT_EWSW[0]) );
AOI22X1TS U4364 ( .A0(n3020), .A1(n3175), .B0(n3064), .B1(n3009), .Y(
FPADDSUB_DMP_INIT_EWSW[1]) );
AOI22X1TS U4365 ( .A0(n3005), .A1(n3086), .B0(n3136), .B1(n3009), .Y(
FPADDSUB_DMP_INIT_EWSW[2]) );
AOI22X1TS U4366 ( .A0(n3007), .A1(n3066), .B0(n3130), .B1(n3009), .Y(
FPADDSUB_DMP_INIT_EWSW[3]) );
AOI22X1TS U4367 ( .A0(n3013), .A1(n3139), .B0(n3105), .B1(n3009), .Y(
FPADDSUB_DMP_INIT_EWSW[4]) );
AOI22X1TS U4368 ( .A0(n3019), .A1(n3088), .B0(n3134), .B1(n3009), .Y(
FPADDSUB_DMP_INIT_EWSW[5]) );
AOI22X1TS U4369 ( .A0(n3011), .A1(n3126), .B0(n3100), .B1(n3009), .Y(
FPADDSUB_DMP_INIT_EWSW[6]) );
INVX2TS U4370 ( .A(n3016), .Y(n3011) );
AOI22X1TS U4371 ( .A0(n3011), .A1(n3099), .B0(n3120), .B1(n3009), .Y(
FPADDSUB_DMP_INIT_EWSW[7]) );
AOI22X1TS U4372 ( .A0(n3020), .A1(n3176), .B0(n3087), .B1(n3009), .Y(
FPADDSUB_DMP_INIT_EWSW[8]) );
AOI22X1TS U4373 ( .A0(n3005), .A1(n3058), .B0(n3177), .B1(n3016), .Y(
FPADDSUB_DMP_INIT_EWSW[9]) );
AOI22X1TS U4374 ( .A0(n3007), .A1(n3010), .B0(n3178), .B1(n3015), .Y(
FPADDSUB_DMP_INIT_EWSW[10]) );
AOI22X1TS U4375 ( .A0(n3013), .A1(n3070), .B0(n3142), .B1(n3012), .Y(
FPADDSUB_DMP_INIT_EWSW[11]) );
AOI22X1TS U4376 ( .A0(n3019), .A1(n3128), .B0(n3059), .B1(n3015), .Y(
FPADDSUB_DMP_INIT_EWSW[12]) );
AOI22X1TS U4377 ( .A0(n3011), .A1(n3132), .B0(n3074), .B1(n3012), .Y(
FPADDSUB_DMP_INIT_EWSW[13]) );
AOI22X1TS U4378 ( .A0(n3020), .A1(n3057), .B0(n3179), .B1(n3015), .Y(
FPADDSUB_DMP_INIT_EWSW[14]) );
AOI22X1TS U4379 ( .A0(n3005), .A1(n3072), .B0(n3127), .B1(n3012), .Y(
FPADDSUB_DMP_INIT_EWSW[15]) );
AOI22X1TS U4380 ( .A0(n3007), .A1(n3140), .B0(n3076), .B1(n3015), .Y(
FPADDSUB_DMP_INIT_EWSW[16]) );
AOI22X1TS U4381 ( .A0(n3020), .A1(n3075), .B0(n3125), .B1(n3012), .Y(
FPADDSUB_DMP_INIT_EWSW[17]) );
AOI22X1TS U4382 ( .A0(n3018), .A1(n3180), .B0(n3065), .B1(n3015), .Y(
FPADDSUB_DMP_INIT_EWSW[18]) );
CLKBUFX3TS U4383 ( .A(n3016), .Y(n3017) );
AOI22X1TS U4384 ( .A0(n3018), .A1(n3090), .B0(n3143), .B1(n3017), .Y(
FPADDSUB_DMP_INIT_EWSW[19]) );
AOI22X1TS U4385 ( .A0(n3018), .A1(n3145), .B0(n3101), .B1(n3017), .Y(
FPADDSUB_DMP_INIT_EWSW[20]) );
AOI22X1TS U4386 ( .A0(n3018), .A1(n3144), .B0(n3073), .B1(n3017), .Y(
FPADDSUB_DMP_INIT_EWSW[21]) );
AOI22X1TS U4387 ( .A0(n3018), .A1(n3129), .B0(n3098), .B1(n3017), .Y(
FPADDSUB_DMP_INIT_EWSW[22]) );
AOI22X1TS U4388 ( .A0(n3018), .A1(n3085), .B0(n3131), .B1(n3017), .Y(
FPADDSUB_DMP_INIT_EWSW[23]) );
AOI22X1TS U4389 ( .A0(n3018), .A1(n3089), .B0(n3137), .B1(n3017), .Y(
FPADDSUB_DMP_INIT_EWSW[24]) );
AOI22X1TS U4390 ( .A0(n3018), .A1(n3133), .B0(n3071), .B1(n3017), .Y(
FPADDSUB_DMP_INIT_EWSW[25]) );
AOI22X1TS U4391 ( .A0(n3018), .A1(n3138), .B0(n3102), .B1(n3017), .Y(
FPADDSUB_DMP_INIT_EWSW[26]) );
AOI22X1TS U4392 ( .A0(n3018), .A1(n3141), .B0(n3084), .B1(n3017), .Y(
FPADDSUB_DMP_INIT_EWSW[27]) );
INVX2TS U4393 ( .A(n3016), .Y(n3019) );
OAI2BB2XLTS U4394 ( .B0(n3011), .B1(n3152), .A0N(n3005), .A1N(
FPADDSUB_intDY_EWSW[28]), .Y(FPADDSUB_DMP_INIT_EWSW[28]) );
OAI2BB2XLTS U4395 ( .B0(n3020), .B1(n3106), .A0N(n3007), .A1N(
FPADDSUB_intDY_EWSW[29]), .Y(FPADDSUB_DMP_INIT_EWSW[29]) );
OAI22X1TS U4396 ( .A0(n975), .A1(n3023), .B0(n3022), .B1(n1080), .Y(
FPADDSUB_Data_array_SWR[24]) );
CLKBUFX3TS U4397 ( .A(n3024), .Y(n3026) );
NOR2BX1TS U4398 ( .AN(FPMULT_Sgf_normalized_result[2]), .B(n3026), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[2]) );
NOR2BX1TS U4399 ( .AN(FPMULT_Sgf_normalized_result[4]), .B(n3025), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[4]) );
NOR2BX1TS U4400 ( .AN(FPMULT_Sgf_normalized_result[6]), .B(n3026), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[6]) );
NOR2BX1TS U4401 ( .AN(FPMULT_Sgf_normalized_result[8]), .B(n3026), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[8]) );
NOR2BX1TS U4402 ( .AN(FPMULT_Sgf_normalized_result[10]), .B(n3026), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[10]) );
NOR2BX1TS U4403 ( .AN(FPMULT_Sgf_normalized_result[12]), .B(n3026), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[12]) );
NOR2BX1TS U4404 ( .AN(FPMULT_Sgf_normalized_result[14]), .B(n3026), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[14]) );
NOR2BX1TS U4405 ( .AN(FPMULT_Sgf_normalized_result[16]), .B(n3026), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[16]) );
NOR2BX1TS U4406 ( .AN(FPMULT_Sgf_normalized_result[18]), .B(n3026), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[18]) );
NOR2BX1TS U4407 ( .AN(FPMULT_Sgf_normalized_result[20]), .B(n3026), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[20]) );
NOR2BX1TS U4408 ( .AN(FPMULT_Sgf_normalized_result[22]), .B(n3026), .Y(
FPMULT_final_result_ieee_Module_Sgf_S_mux[22]) );
NOR2BX1TS U4409 ( .AN(FPSENCOS_d_ff_Xn[0]), .B(n3027), .Y(
FPSENCOS_first_mux_X[0]) );
NOR2BX1TS U4410 ( .AN(FPSENCOS_d_ff_Xn[4]), .B(n3027), .Y(
FPSENCOS_first_mux_X[4]) );
NOR2BX1TS U4411 ( .AN(FPSENCOS_d_ff_Xn[8]), .B(n3027), .Y(
FPSENCOS_first_mux_X[8]) );
NOR2BX1TS U4412 ( .AN(FPSENCOS_d_ff_Xn[9]), .B(n3027), .Y(
FPSENCOS_first_mux_X[9]) );
NOR2BX1TS U4413 ( .AN(FPSENCOS_d_ff_Xn[11]), .B(n3027), .Y(
FPSENCOS_first_mux_X[11]) );
NOR2BX1TS U4414 ( .AN(FPSENCOS_d_ff_Xn[15]), .B(n3027), .Y(
FPSENCOS_first_mux_X[15]) );
NOR2BX1TS U4415 ( .AN(FPSENCOS_d_ff_Xn[18]), .B(n3028), .Y(
FPSENCOS_first_mux_X[18]) );
NOR2BX1TS U4416 ( .AN(FPSENCOS_d_ff_Xn[21]), .B(n3027), .Y(
FPSENCOS_first_mux_X[21]) );
NOR2BX1TS U4417 ( .AN(FPSENCOS_d_ff_Xn[22]), .B(n3028), .Y(
FPSENCOS_first_mux_X[22]) );
NOR2BX1TS U4418 ( .AN(FPSENCOS_d_ff_Xn[23]), .B(n3028), .Y(
FPSENCOS_first_mux_X[23]) );
NOR2BX1TS U4419 ( .AN(FPSENCOS_d_ff_Xn[30]), .B(n3029), .Y(
FPSENCOS_first_mux_X[30]) );
NOR2BX1TS U4420 ( .AN(FPSENCOS_d_ff_Xn[31]), .B(n3028), .Y(
FPSENCOS_first_mux_X[31]) );
NOR2BX1TS U4421 ( .AN(FPSENCOS_d_ff_Yn[0]), .B(n3029), .Y(
FPSENCOS_first_mux_Y[0]) );
NOR2BX1TS U4422 ( .AN(FPSENCOS_d_ff_Yn[1]), .B(n3028), .Y(
FPSENCOS_first_mux_Y[1]) );
NOR2BX1TS U4423 ( .AN(FPSENCOS_d_ff_Yn[2]), .B(n3029), .Y(
FPSENCOS_first_mux_Y[2]) );
NOR2BX1TS U4424 ( .AN(FPSENCOS_d_ff_Yn[3]), .B(n3028), .Y(
FPSENCOS_first_mux_Y[3]) );
NOR2BX1TS U4425 ( .AN(FPSENCOS_d_ff_Yn[4]), .B(n3029), .Y(
FPSENCOS_first_mux_Y[4]) );
NOR2BX1TS U4426 ( .AN(FPSENCOS_d_ff_Yn[5]), .B(n3028), .Y(
FPSENCOS_first_mux_Y[5]) );
NOR2BX1TS U4427 ( .AN(FPSENCOS_d_ff_Yn[6]), .B(n3027), .Y(
FPSENCOS_first_mux_Y[6]) );
NOR2BX1TS U4428 ( .AN(FPSENCOS_d_ff_Yn[7]), .B(n3028), .Y(
FPSENCOS_first_mux_Y[7]) );
NOR2BX1TS U4429 ( .AN(FPSENCOS_d_ff_Yn[8]), .B(n3029), .Y(
FPSENCOS_first_mux_Y[8]) );
NOR2BX1TS U4430 ( .AN(FPSENCOS_d_ff_Yn[9]), .B(n3027), .Y(
FPSENCOS_first_mux_Y[9]) );
NOR2BX1TS U4431 ( .AN(FPSENCOS_d_ff_Yn[10]), .B(n3031), .Y(
FPSENCOS_first_mux_Y[10]) );
NOR2BX1TS U4432 ( .AN(FPSENCOS_d_ff_Yn[11]), .B(n3029), .Y(
FPSENCOS_first_mux_Y[11]) );
NOR2BX1TS U4433 ( .AN(FPSENCOS_d_ff_Yn[12]), .B(n3031), .Y(
FPSENCOS_first_mux_Y[12]) );
NOR2BX1TS U4434 ( .AN(FPSENCOS_d_ff_Yn[13]), .B(n3028), .Y(
FPSENCOS_first_mux_Y[13]) );
NOR2BX1TS U4435 ( .AN(FPSENCOS_d_ff_Yn[14]), .B(n3031), .Y(
FPSENCOS_first_mux_Y[14]) );
NOR2BX1TS U4436 ( .AN(FPSENCOS_d_ff_Yn[15]), .B(n3029), .Y(
FPSENCOS_first_mux_Y[15]) );
NOR2BX1TS U4437 ( .AN(FPSENCOS_d_ff_Yn[16]), .B(n3031), .Y(
FPSENCOS_first_mux_Y[16]) );
NOR2BX1TS U4438 ( .AN(FPSENCOS_d_ff_Yn[17]), .B(n3029), .Y(
FPSENCOS_first_mux_Y[17]) );
NOR2BX1TS U4439 ( .AN(FPSENCOS_d_ff_Yn[18]), .B(n3031), .Y(
FPSENCOS_first_mux_Y[18]) );
NOR2BX1TS U4440 ( .AN(FPSENCOS_d_ff_Yn[19]), .B(n3029), .Y(
FPSENCOS_first_mux_Y[19]) );
NOR2BX1TS U4441 ( .AN(FPSENCOS_d_ff_Yn[20]), .B(n3031), .Y(
FPSENCOS_first_mux_Y[20]) );
NOR2BX1TS U4442 ( .AN(FPSENCOS_d_ff_Yn[21]), .B(n3031), .Y(
FPSENCOS_first_mux_Y[21]) );
NOR2BX1TS U4443 ( .AN(FPSENCOS_d_ff_Yn[22]), .B(n3030), .Y(
FPSENCOS_first_mux_Y[22]) );
NOR2BX1TS U4444 ( .AN(FPSENCOS_d_ff_Yn[23]), .B(n3028), .Y(
FPSENCOS_first_mux_Y[23]) );
NOR2BX1TS U4445 ( .AN(FPSENCOS_d_ff_Yn[24]), .B(n3030), .Y(
FPSENCOS_first_mux_Y[24]) );
NOR2BX1TS U4446 ( .AN(FPSENCOS_d_ff_Yn[25]), .B(n3029), .Y(
FPSENCOS_first_mux_Y[25]) );
NOR2BX1TS U4447 ( .AN(FPSENCOS_d_ff_Yn[26]), .B(n3030), .Y(
FPSENCOS_first_mux_Y[26]) );
NOR2BX1TS U4448 ( .AN(FPSENCOS_d_ff_Yn[27]), .B(n3031), .Y(
FPSENCOS_first_mux_Y[27]) );
NOR2BX1TS U4449 ( .AN(FPSENCOS_d_ff_Yn[28]), .B(n3030), .Y(
FPSENCOS_first_mux_Y[28]) );
NOR2BX1TS U4450 ( .AN(FPSENCOS_d_ff_Yn[29]), .B(n3031), .Y(
FPSENCOS_first_mux_Y[29]) );
NOR2BX1TS U4451 ( .AN(FPSENCOS_d_ff_Yn[30]), .B(n3030), .Y(
FPSENCOS_first_mux_Y[30]) );
NOR2BX1TS U4452 ( .AN(FPSENCOS_d_ff_Yn[31]), .B(n3031), .Y(
FPSENCOS_first_mux_Y[31]) );
AND3X1TS U4453 ( .A(n3032), .B(n3124), .C(n923), .Y(
FPMULT_FSM_first_phase_load) );
INVX2TS U4454 ( .A(n3033), .Y(n3034) );
AOI22X1TS U4455 ( .A0(FPMULT_FS_Module_state_reg[1]), .A1(
FPMULT_FS_Module_state_reg[2]), .B0(n3035), .B1(n3034), .Y(
FPMULT_FS_Module_state_next[2]) );
NOR3XLTS U4456 ( .A(FPSENCOS_cont_var_out[0]), .B(FPSENCOS_cont_var_out[1]),
.C(n3123), .Y(FPSENCOS_enab_d_ff4_Xn) );
NOR3XLTS U4457 ( .A(FPSENCOS_cont_var_out[1]), .B(n3082), .C(n3123), .Y(
FPSENCOS_enab_d_ff4_Yn) );
NOR2X1TS U4458 ( .A(n3037), .B(n3036), .Y(n3043) );
NOR4X1TS U4459 ( .A(enab_cont_iter), .B(FPSENCOS_enab_RB3), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[3]), .D(n3038), .Y(n3040) );
NAND2X1TS U4460 ( .A(n3040), .B(n3039), .Y(n3041) );
OAI22X1TS U4461 ( .A0(n3043), .A1(n3042), .B0(n3041), .B1(
FPSENCOS_enab_d_ff_RB1), .Y(FPSENCOS_inst_CORDIC_FSM_v3_state_next[0])
);
NOR2BX1TS U4462 ( .AN(n3043), .B(n3042), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]) );
OAI22X1TS U4463 ( .A0(FPSENCOS_enab_d_ff4_Zn), .A1(n3046), .B0(n3045), .B1(
n3044), .Y(FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]) );
NOR2BX1TS U4464 ( .AN(FPSENCOS_enab_d_ff4_Zn), .B(n3046), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]) );
NOR2BX1TS U4465 ( .AN(n3050), .B(n3049), .Y(FPSENCOS_ITER_CONT_N3) );
AOI21X1TS U4466 ( .A0(n3048), .A1(n3056), .B0(n3047), .Y(n859) );
OAI21XLTS U4467 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n3049), .B0(n3050),
.Y(n3051) );
OAI22X1TS U4468 ( .A0(FPSENCOS_cont_iter_out[2]), .A1(n3051), .B0(n943),
.B1(n3050), .Y(n855) );
OAI21XLTS U4469 ( .A0(n3053), .A1(n3082), .B0(FPSENCOS_cont_var_out[1]), .Y(
n3052) );
XNOR2X1TS U4470 ( .A(FPADDSUB_intDX_EWSW[31]), .B(n3493), .Y(n30) );
NOR2BX1TS U4471 ( .AN(FPADDSUB_Shift_reg_FLAGS_7[3]), .B(
FPADDSUB_Shift_reg_FLAGS_7[0]), .Y(FPADDSUB__19_net_) );
XNOR2X1TS U4472 ( .A(FPSENCOS_d_ff2_Y[29]), .B(n3054), .Y(
FPSENCOS_sh_exp_y[6]) );
XNOR2X1TS U4473 ( .A(FPSENCOS_d_ff2_X[29]), .B(n3055), .Y(
FPSENCOS_sh_exp_x[6]) );
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_GATED_DW_1STAGE_syn.sdf");
endmodule
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