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/*
* mem_arbiter.v - switches between each memory conduit
*
* This module decides on which request is satisfied next, based on
* order of priority and an 8 clock cycle.
*
* Part of the CPC2 project: http://intelligenttoasters.blog
*
* Copyright (C)2017 [email protected]
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, you can find a copy here:
* https://www.gnu.org/licenses/gpl-3.0.en.html
*
*/
`timescale 1ns/1ns
module mem_arbiter (
// Control
input clock_i,
input reset_i,
// Output port
output reg [22:0] adr_o,
output [15:0] dat_o,
output [1:0] dm_o,
output reg rd_o,
output reg wr_o,
output reg enable_o,
input busy_i,
input valid_i,
// Port 1
input req1_i,
output reg ack1_o,
input [22:0] adr1_i,
input [15:0] dat1_i,
input [1:0] dm1_i,
input rd1_i,
input wr1_i,
// Port 2
input req2_i,
output reg ack2_o,
input [22:0] adr2_i,
input [15:0] dat2_i,
input [1:0] dm2_i,
input rd2_i,
input wr2_i,
// Port 3
input req3_i,
output reg ack3_o,
input [22:0] adr3_i,
input [15:0] dat3_i,
input [1:0] dm3_i,
input rd3_i,
input wr3_i,
// Port 4
input req4_i,
output reg ack4_o,
input [22:0] adr4_i,
input [15:0] dat4_i,
input [1:0] dm4_i,
input rd4_i,
input wr4_i
);
// Parameters / constants
parameter IDLE = 0, ACTIVE = 1, INCYCLE = 2;
// Wire definitions ===========================================================================
// Registers ==================================================================================
reg [2:0] state = IDLE, last_state = IDLE;
reg [2:0] cntr = 0;
reg rd = 0, wr = 0;
reg ack1 = 0, ack2 = 0, ack3 = 0, ack4 = 0;
// Assignments ================================================================================
assign dat_o = (ack1_o) ? dat1_i : (ack2_o) ? dat2_i : (ack3_o) ? dat3_i : (ack4_o) ? dat4_i : 16'd0;
assign dm_o = (ack1_o) ? dm1_i : (ack2_o) ? dm2_i : (ack3_o) ? dm3_i : (ack4_o) ? dm4_i : 2'd0;
// Module connections =========================================================================
// Simulation branches and control ============================================================
// Other logic ================================================================================
always @(posedge clock_i)
if( reset_i ) state <= IDLE;
else case( state )
// Cant process if still waiting for old cycle to finish
IDLE : if( ~valid_i ) begin
if( req1_i & (rd1_i | wr1_i) ) begin
state <= ACTIVE;
ack1 <= 1'b1;
adr_o <= adr1_i;
// Sanitise read/write signals - can't be both!
if( rd1_i ) begin
rd <= 1'b1;
wr <= 1'b0;
end
else begin
rd <= 1'b0;
if( wr1_i ) wr <= 1'b1;
else wr <= 1'b0;
end
end
else
if( req2_i & (rd2_i | wr2_i) ) begin
state <= ACTIVE;
adr_o <= adr2_i;
ack2 <= 1'b1;
// Sanitise read/write signals - can't be both!
if( rd2_i ) begin
rd <= 1'b1;
wr <= 1'b0;
end
else begin
rd <= 1'b0;
if( wr2_i ) wr <= 1'b1;
else wr <= 1'b0;
end
end
else
if( req3_i & (rd3_i | wr3_i) ) begin
state <= ACTIVE;
adr_o <= adr3_i;
ack3 <= 1'b1;
// Sanitise read/write signals - can't be both!
if( rd3_i ) begin
rd <= 1'b1;
wr <= 1'b0;
end
else begin
rd <= 1'b0;
if( wr3_i ) wr <= 1'b1;
else wr <= 1'b0;
end
end
else
if( req4_i & (rd4_i | wr4_i) ) begin
state <= ACTIVE;
adr_o <= adr4_i;
ack4 <= 1'b1;
// Sanitise read/write signals - can't be both!
if( rd4_i ) begin
rd <= 1'b1;
wr <= 1'b0;
end
else begin
rd <= 1'b0;
if( wr4_i ) wr <= 1'b1;
else wr <= 1'b0;
end
end
end
ACTIVE : if( valid_i ) begin
state <= INCYCLE;
cntr <= 3'd7; // Ensures all 8 words are visible for the duration of the tSU+tH
end
INCYCLE : begin
ack1 <= 0;
ack2 <= 0;
ack3 <= 0;
ack4 <= 0;
if( cntr == 0 ) state <= IDLE;
else cntr <= cntr - 1'b1;
end
default: state <= IDLE;
endcase
reg pending_acknowledgement = 0;
// Change RAM signals
always @(negedge clock_i)
begin
case( state )
IDLE: begin
ack1_o <= 0;
ack2_o <= 0;
ack3_o <= 0;
ack4_o <= 0;
rd_o <= 0;
wr_o <= 0;
enable_o <= 0;
last_state <= IDLE;
pending_acknowledgement <= 1'b1;
end
ACTIVE: begin // It remains in this state until the valid_i signal goes active indicating an active in/out
if( pending_acknowledgement ) begin
ack1_o <= ack1;
ack2_o <= ack2;
ack3_o <= ack3;
ack4_o <= ack4;
rd_o <= rd;
wr_o <= wr;
enable_o <= 1;
// If the SDRAM controller accepted our command, then reset the control lines
if( busy_i ) pending_acknowledgement <= 1'b0;
end
else
begin
enable_o <= 0;
rd_o <= 0;
wr_o <= 0;
end
end
INCYCLE : begin
enable_o <= 0;
rd_o <= 0;
wr_o <= 0;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111O_0_V
`define SKY130_FD_SC_LP__A2111O_0_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111o with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a2111o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2111o_0 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2111o_0 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111O_0_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_slave #(
parameter ACCEPTANCE = 3,
parameter MIN_LATENCY = 16,
parameter MAX_LATENCY = 32
) (
input clk,
input reset,
input valid,
output ready,
input [31:0] addr,
input [7:0] len,
input [2:0] size,
input [1:0] burst,
input [2:0] prot,
input [3:0] cache,
output beat_stb,
input beat_ack,
output [31:0] beat_addr,
output beat_last
);
reg [31:0] timestamp = 'h00;
always @(posedge clk) begin
if (reset == 1'b1) begin
timestamp <= 'h00;
end else begin
timestamp <= timestamp + 1'b1;
end
end
reg [32+32+8-1:0] req_fifo[0:15];
reg [3:0] req_fifo_rd = 'h00;
reg [3:0] req_fifo_wr = 'h00;
wire [3:0] req_fifo_level = req_fifo_wr - req_fifo_rd;
assign ready = req_fifo_level < ACCEPTANCE;
always @(posedge clk) begin
if (reset == 1'b1) begin
req_fifo_wr <= 'h00;
end else begin
if (valid == 1'b1 && ready == 1'b1) begin
req_fifo[req_fifo_wr][71:40] <= timestamp + {$random} % (MAX_LATENCY - MIN_LATENCY + 1) + MIN_LATENCY;
req_fifo[req_fifo_wr][39:0] <= {addr,len};
req_fifo_wr <= req_fifo_wr + 1'b1;
end
end
end
reg [7:0] beat_counter = 'h00;
assign beat_stb = req_fifo_level != 0 && timestamp > req_fifo[req_fifo_rd][71:40];
assign beat_last = beat_stb ? beat_counter == req_fifo[req_fifo_rd][0+:8] : 1'b0;
assign beat_addr = req_fifo[req_fifo_rd][8+:32] + beat_counter * 4;
always @(posedge clk) begin
if (reset == 1'b1) begin
beat_counter <= 'h00;
req_fifo_rd <= 'h00;
end else begin
if (beat_ack == 1'b1) begin
if (beat_last == 1'b1) begin
beat_counter <= 'h00;
req_fifo_rd <= req_fifo_rd + 1'b1;
end else begin
beat_counter <= beat_counter + 1'b1;
end
end
end
end
endmodule
|
`include "timescale.v"
`include "defines.v"
module clk_rst(
clk_sys_o,
clk_adc_o,
clk_adc2x_o,
clk_100mhz_o,
clk_200mhz_o,
rstn_o
);
// Defaults parameters
parameter CLK_SYS_PERIOD = `CLK_SYS_PERIOD;
parameter CLK_ADC_PERIOD = `CLK_ADC_PERIOD;
parameter CLK_ADC_2X_PERIOD = `CLK_ADC_2X_PERIOD;
localparam CLK_100MHZ_PERIOD = `CLK_100MHZ_PERIOD;
localparam CLK_200MHZ_PERIOD = `CLK_200MHZ_PERIOD;
// Output Clocks
output reg
clk_sys_o,
clk_adc_o,
clk_adc2x_o,
clk_100mhz_o,
clk_200mhz_o;
// Output Reset
output reg rstn_o;
// Reset generate
initial
begin
clk_sys_o = 0;
clk_adc_o = 0;
clk_adc2x_o = 0;
clk_100mhz_o = 0;
clk_200mhz_o = 0;
rstn_o = 0;
#(`RST_SYS_DELAY)
rstn_o = 1;
end
// Clock Generation
always #(CLK_SYS_PERIOD/2) clk_sys_o <= ~clk_sys_o;
always #(CLK_ADC_PERIOD/2) clk_adc_o <= ~clk_adc_o;
always #(CLK_ADC_2X_PERIOD/2) clk_adc2x_o <= ~clk_adc2x_o;
always #(CLK_100MHZ_PERIOD/2) clk_100mhz_o <= ~clk_100mhz_o;
always #(CLK_200MHZ_PERIOD/2) clk_200mhz_o <= ~clk_200mhz_o;
endmodule
|
(* src = "../../verilog/slowadt7410.v:1", top = 1 *)
module SlowADT7410 (
(* intersynth_port = "Reset_n_i", src = "../../verilog/slowadt7410.v:3" *)
input Reset_n_i,
(* intersynth_port = "Clk_i", src = "../../verilog/slowadt7410.v:5" *)
input Clk_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIn_s", src = "../../verilog/slowadt7410.v:7" *)
input Enable_i,
(* intersynth_conntype = "Bit", intersynth_port = "ReconfModuleIRQs_s", src = "../../verilog/slowadt7410.v:9" *)
output CpuIntr_o,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_ReceiveSend_n", src = "../../verilog/slowadt7410.v:11" *)
output I2C_ReceiveSend_n_o,
(* intersynth_conntype = "Byte", intersynth_port = "I2C_ReadCount", src = "../../verilog/slowadt7410.v:13" *)
output[7:0] I2C_ReadCount_o,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_StartProcess", src = "../../verilog/slowadt7410.v:15" *)
output I2C_StartProcess_o,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_Busy", src = "../../verilog/slowadt7410.v:17" *)
input I2C_Busy_i,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_FIFOReadNext", src = "../../verilog/slowadt7410.v:19" *)
output I2C_FIFOReadNext_o,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_FIFOWrite", src = "../../verilog/slowadt7410.v:21" *)
output I2C_FIFOWrite_o,
(* intersynth_conntype = "Byte", intersynth_port = "I2C_DataIn", src = "../../verilog/slowadt7410.v:23" *)
output[7:0] I2C_Data_o,
(* intersynth_conntype = "Byte", intersynth_port = "I2C_DataOut", src = "../../verilog/slowadt7410.v:25" *)
input[7:0] I2C_Data_i,
(* intersynth_conntype = "Bit", intersynth_port = "I2C_Error", src = "../../verilog/slowadt7410.v:27" *)
input I2C_Error_i,
(* intersynth_conntype = "Word", intersynth_param = "PeriodCounterPresetH_i", src = "../../verilog/slowadt7410.v:29" *)
input[15:0] PeriodCounterPresetH_i,
(* intersynth_conntype = "Word", intersynth_param = "PeriodCounterPresetL_i", src = "../../verilog/slowadt7410.v:31" *)
input[15:0] PeriodCounterPresetL_i,
(* intersynth_conntype = "Word", intersynth_param = "SensorValue_o", src = "../../verilog/slowadt7410.v:33" *)
output[15:0] SensorValue_o,
(* intersynth_conntype = "Word", intersynth_param = "Threshold_i", src = "../../verilog/slowadt7410.v:35" *)
input[15:0] Threshold_i,
(* intersynth_conntype = "Word", intersynth_param = "WaitCounterPresetH_i", src = "../../verilog/slowadt7410.v:37" *)
input[15:0] WaitCounterPresetH_i,
(* intersynth_conntype = "Word", intersynth_param = "WaitCounterPresetL_i", src = "../../verilog/slowadt7410.v:39" *)
input[15:0] WaitCounterPresetL_i
);
wire \$techmap\I2CFSM_1.$auto$opt_reduce.cc:126:opt_mux$2832 ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:12" *)
wire [15:0] \$techmap\I2CFSM_1.$extract$\Counter32_RV1_Timer$2903.DH_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:13" *)
wire [15:0] \$techmap\I2CFSM_1.$extract$\Counter32_RV1_Timer$2903.DL_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:14" *)
wire \$techmap\I2CFSM_1.$extract$\Counter32_RV1_Timer$2903.Overflow_s ;
wire \$techmap\I2CFSM_1.$procmux$1156_CMP ;
wire \$techmap\I2CFSM_1.$procmux$1168_CMP ;
wire \$techmap\I2CFSM_1.$procmux$1169_CMP ;
wire [7:0] \$techmap\I2CFSM_1.$techmap$procmux$1425.$procmux$2880_Y ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:8" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Carry_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:7" *)
wire [15:0] \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.D_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:11" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Overflow_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:10" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Sign_s ;
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:9" *)
wire \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Zero_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:12" *)
wire [15:0] \$techmap\SensorFSM_1.$extract$\Counter32_RV1_Timer$2902.DH_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:13" *)
wire [15:0] \$techmap\SensorFSM_1.$extract$\Counter32_RV1_Timer$2902.DL_s ;
(* src = "../../../../counter32/verilog/counter32_rv1.v:14" *)
wire \$techmap\SensorFSM_1.$extract$\Counter32_RV1_Timer$2902.Overflow_s ;
(* src = "../../verilog/i2cfsm.v:10" *)
wire [7:0] \I2CFSM_1.Byte0_o ;
(* src = "../../verilog/i2cfsm.v:11" *)
wire [7:0] \I2CFSM_1.Byte1_o ;
(* src = "../../verilog/i2cfsm.v:8" *)
wire \I2CFSM_1.Done_o ;
(* src = "../../verilog/i2cfsm.v:9" *)
wire \I2CFSM_1.Error_o ;
(* src = "../../verilog/i2cfsm.v:78" *)
wire \I2CFSM_1.I2C_FSM_TimerEnable ;
(* src = "../../verilog/i2cfsm.v:76" *)
wire \I2CFSM_1.I2C_FSM_TimerOvfl ;
(* src = "../../verilog/i2cfsm.v:77" *)
wire \I2CFSM_1.I2C_FSM_TimerPreset ;
(* src = "../../verilog/i2cfsm.v:80" *)
wire \I2CFSM_1.I2C_FSM_Wr0 ;
(* src = "../../verilog/i2cfsm.v:79" *)
wire \I2CFSM_1.I2C_FSM_Wr1 ;
(* src = "../../verilog/i2cfsm.v:7" *)
wire \I2CFSM_1.Start_i ;
(* src = "../../verilog/sensorfsm.v:42" *)
wire [15:0] \SensorFSM_1.AbsDiffResult ;
(* src = "../../verilog/sensorfsm.v:36" *)
wire \SensorFSM_1.SensorFSM_StoreNewValue ;
(* src = "../../verilog/sensorfsm.v:34" *)
wire \SensorFSM_1.SensorFSM_TimerEnable ;
(* src = "../../verilog/sensorfsm.v:32" *)
wire \SensorFSM_1.SensorFSM_TimerOvfl ;
(* src = "../../verilog/sensorfsm.v:33" *)
wire \SensorFSM_1.SensorFSM_TimerPreset ;
(* src = "../../verilog/sensorfsm.v:40" *)
wire [15:0] \SensorFSM_1.SensorValue ;
wire TRFSM1_1_Out14_s;
wire TRFSM1_1_CfgMode_s;
wire TRFSM1_1_CfgClk_s;
wire TRFSM1_1_CfgShift_s;
wire TRFSM1_1_CfgDataIn_s;
wire TRFSM1_1_CfgDataOut_s;
wire TRFSM0_1_Out5_s;
wire TRFSM0_1_Out6_s;
wire TRFSM0_1_Out7_s;
wire TRFSM0_1_Out8_s;
wire TRFSM0_1_Out9_s;
wire TRFSM0_1_CfgMode_s;
wire TRFSM0_1_CfgClk_s;
wire TRFSM0_1_CfgShift_s;
wire TRFSM0_1_CfgDataIn_s;
wire TRFSM0_1_CfgDataOut_s;
Byte2Word \$extract$\Byte2Word$2915 (
.H_i(\I2CFSM_1.Byte1_o ),
.L_i(\I2CFSM_1.Byte0_o ),
.Y_o(\SensorFSM_1.SensorValue )
);
ByteMuxDual \$techmap\I2CFSM_1.$extract$\ByteMuxDual$2910 (
.A_i(8'b00000000),
.B_i(8'b00000010),
.S_i(I2C_ReceiveSend_n_o),
.Y_o(I2C_ReadCount_o)
);
ByteMuxDual \$techmap\I2CFSM_1.$extract$\ByteMuxDual$2911 (
.A_i(\$techmap\I2CFSM_1.$techmap$procmux$1425.$procmux$2880_Y ),
.B_i(8'b00000011),
.S_i(\$techmap\I2CFSM_1.$procmux$1169_CMP ),
.Y_o(I2C_Data_o)
);
ByteMuxQuad \$techmap\I2CFSM_1.$extract$\ByteMuxQuad$2909 (
.A_i(8'b00000000),
.B_i(8'b10010001),
.C_i(8'b10010000),
.D_i(8'b00100000),
.SAB_i(\$techmap\I2CFSM_1.$procmux$1156_CMP ),
.SC_i(\$techmap\I2CFSM_1.$auto$opt_reduce.cc:126:opt_mux$2832 ),
.SD_i(\$techmap\I2CFSM_1.$procmux$1168_CMP ),
.Y_o(\$techmap\I2CFSM_1.$techmap$procmux$1425.$procmux$2880_Y )
);
ByteRegister \$techmap\I2CFSM_1.$extract$\ByteRegister$2906 (
.Clk_i(Clk_i),
.D_i(I2C_Data_i),
.Enable_i(\I2CFSM_1.I2C_FSM_Wr0 ),
.Q_o(\I2CFSM_1.Byte0_o ),
.Reset_n_i(Reset_n_i)
);
ByteRegister \$techmap\I2CFSM_1.$extract$\ByteRegister$2907 (
.Clk_i(Clk_i),
.D_i(I2C_Data_i),
.Enable_i(\I2CFSM_1.I2C_FSM_Wr1 ),
.Q_o(\I2CFSM_1.Byte1_o ),
.Reset_n_i(Reset_n_i)
);
(* src = "../../../../counter32/verilog/counter32_rv1.v:19" *)
Counter32 \$techmap\I2CFSM_1.$extract$\Counter32_RV1_Timer$2903.ThisCounter (
.Clk_i(Clk_i),
.DH_o(\$techmap\I2CFSM_1.$extract$\Counter32_RV1_Timer$2903.DH_s ),
.DL_o(\$techmap\I2CFSM_1.$extract$\Counter32_RV1_Timer$2903.DL_s ),
.Direction_i(1'b1),
.Enable_i(\I2CFSM_1.I2C_FSM_TimerEnable ),
.Overflow_o(\$techmap\I2CFSM_1.$extract$\Counter32_RV1_Timer$2903.Overflow_s ),
.PresetValH_i(WaitCounterPresetH_i),
.PresetValL_i(WaitCounterPresetL_i),
.Preset_i(\I2CFSM_1.I2C_FSM_TimerPreset ),
.ResetSig_i(1'b0),
.Reset_n_i(Reset_n_i),
.Zero_o(\I2CFSM_1.I2C_FSM_TimerOvfl )
);
TRFSM1 TRFSM1_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.In0_i(I2C_Busy_i),
.In1_i(I2C_Error_i),
.In2_i(\I2CFSM_1.I2C_FSM_TimerOvfl ),
.In3_i(\I2CFSM_1.Start_i ),
.In4_i(1'b0),
.In5_i(1'b0),
.In6_i(1'b0),
.In7_i(1'b0),
.In8_i(1'b0),
.In9_i(1'b0),
.Out0_o(\$techmap\I2CFSM_1.$procmux$1156_CMP ),
.Out1_o(\$techmap\I2CFSM_1.$procmux$1168_CMP ),
.Out2_o(\$techmap\I2CFSM_1.$procmux$1169_CMP ),
.Out3_o(\I2CFSM_1.Done_o ),
.Out4_o(\I2CFSM_1.I2C_FSM_Wr0 ),
.Out5_o(I2C_ReceiveSend_n_o),
.Out6_o(I2C_StartProcess_o),
.Out7_o(\$techmap\I2CFSM_1.$auto$opt_reduce.cc:126:opt_mux$2832 ),
.Out8_o(\I2CFSM_1.Error_o ),
.Out9_o(\I2CFSM_1.I2C_FSM_Wr1 ),
.Out10_o(I2C_FIFOReadNext_o),
.Out11_o(\I2CFSM_1.I2C_FSM_TimerEnable ),
.Out12_o(\I2CFSM_1.I2C_FSM_TimerPreset ),
.Out13_o(I2C_FIFOWrite_o),
.Out14_o(TRFSM1_1_Out14_s),
.CfgMode_i(TRFSM1_1_CfgMode_s),
.CfgClk_i(TRFSM1_1_CfgClk_s),
.CfgShift_i(TRFSM1_1_CfgShift_s),
.CfgDataIn_i(TRFSM1_1_CfgDataIn_s),
.CfgDataOut_o(TRFSM1_1_CfgDataOut_s)
);
AbsDiff \$techmap\SensorFSM_1.$extract$\AbsDiff$2904 (
.A_i(\SensorFSM_1.SensorValue ),
.B_i(SensorValue_o),
.D_o(\SensorFSM_1.AbsDiffResult )
);
(* src = "../../../../addsubcmp/verilog/addsubcmp_greater.v:13" *)
AddSubCmp \$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.ThisAddSubCmp (
.A_i(\SensorFSM_1.AbsDiffResult ),
.AddOrSub_i(1'b1),
.B_i(Threshold_i),
.Carry_i(1'b0),
.Carry_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Carry_s ),
.D_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.D_s ),
.Overflow_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Overflow_s ),
.Sign_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Sign_s ),
.Zero_o(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Zero_s )
);
(* src = "../../../../counter32/verilog/counter32_rv1.v:19" *)
Counter32 \$techmap\SensorFSM_1.$extract$\Counter32_RV1_Timer$2902.ThisCounter (
.Clk_i(Clk_i),
.DH_o(\$techmap\SensorFSM_1.$extract$\Counter32_RV1_Timer$2902.DH_s ),
.DL_o(\$techmap\SensorFSM_1.$extract$\Counter32_RV1_Timer$2902.DL_s ),
.Direction_i(1'b1),
.Enable_i(\SensorFSM_1.SensorFSM_TimerEnable ),
.Overflow_o(\$techmap\SensorFSM_1.$extract$\Counter32_RV1_Timer$2902.Overflow_s ),
.PresetValH_i(PeriodCounterPresetH_i),
.PresetValL_i(PeriodCounterPresetL_i),
.Preset_i(\SensorFSM_1.SensorFSM_TimerPreset ),
.ResetSig_i(1'b0),
.Reset_n_i(Reset_n_i),
.Zero_o(\SensorFSM_1.SensorFSM_TimerOvfl )
);
WordRegister \$techmap\SensorFSM_1.$extract$\WordRegister$2905 (
.Clk_i(Clk_i),
.D_i(\SensorFSM_1.SensorValue ),
.Enable_i(\SensorFSM_1.SensorFSM_StoreNewValue ),
.Q_o(SensorValue_o),
.Reset_n_i(Reset_n_i)
);
TRFSM0 TRFSM0_1 (
.Reset_n_i(Reset_n_i),
.Clk_i(Clk_i),
.In0_i(Enable_i),
.In1_i(\I2CFSM_1.Done_o ),
.In2_i(\I2CFSM_1.Error_o ),
.In3_i(\SensorFSM_1.SensorFSM_TimerOvfl ),
.In4_i(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Carry_s ),
.In5_i(\$techmap\SensorFSM_1.$extract$\AddSubCmp_Greater_Direct$2908.Zero_s ),
.Out0_o(\I2CFSM_1.Start_i ),
.Out1_o(\SensorFSM_1.SensorFSM_StoreNewValue ),
.Out2_o(CpuIntr_o),
.Out3_o(\SensorFSM_1.SensorFSM_TimerEnable ),
.Out4_o(\SensorFSM_1.SensorFSM_TimerPreset ),
.Out5_o(TRFSM0_1_Out5_s),
.Out6_o(TRFSM0_1_Out6_s),
.Out7_o(TRFSM0_1_Out7_s),
.Out8_o(TRFSM0_1_Out8_s),
.Out9_o(TRFSM0_1_Out9_s),
.CfgMode_i(TRFSM0_1_CfgMode_s),
.CfgClk_i(TRFSM0_1_CfgClk_s),
.CfgShift_i(TRFSM0_1_CfgShift_s),
.CfgDataIn_i(TRFSM0_1_CfgDataIn_s),
.CfgDataOut_o(TRFSM0_1_CfgDataOut_s)
);
assign TRFSM1_1_CfgMode_s = 1'b0;
assign TRFSM1_1_CfgClk_s = 1'b0;
assign TRFSM1_1_CfgShift_s = 1'b0;
assign TRFSM1_1_CfgDataIn_s = 1'b0;
assign TRFSM0_1_CfgMode_s = 1'b0;
assign TRFSM0_1_CfgClk_s = 1'b0;
assign TRFSM0_1_CfgShift_s = 1'b0;
assign TRFSM0_1_CfgDataIn_s = 1'b0;
endmodule
|
`timescale 1ns / 1ps
module TimeCounter(
input clk, // Basys3µÄ100MHzÂö³å
input clk_5000_0000,
input clk_500_0000,
input clk_50_0000,
input clk_5_0000,
input clk_5000,
input clk_500,
input clk_50,
input clk_5,
input btn_show, // Button Right, Çл»ÏÔʾµÄÄÚÈÝ
input btn_set, //
input btn_add, //
output reg [3:0] show_state, // Á´½Ó4¸öLEDµÆ, ÌáʾĿǰÏÔʾÄÚÈÝ
output reg set_led,
output reg add_led,
output wire [7:0] display, // ¶ÎÑ¡¶Ë
output wire [3:0] an // λѡ¶Î
);
reg base_clk;
reg [15:0] num;
// Öµ
wire [7:0] sec, min, hour, day, month, year;
// ½øλ
wire tc_sec_to_min, tc_min_to_hour, tc_hour_to_day,
tc_day_to_month, tc_month_to_year, nil;
reg [1:0] show_signal; // 2'B00 => min, sec
// 2'B01 => hour, min
// 2'B10 => month, day
// 2'B11 => year
reg [2:0] set_signal; // 3'B000 => normal
// 3'B001 => sec
// 3'B010 => min
// 3'B011 => hour
// 3'B100 => day
// 3'B101 => month
// 3'B110 => year
// 3'B111 => return normal
reg [5:0] set_state; // {year, month, day, hour, min, sec}
reg [5:0] add_state; // {year, month, day, hour, min, sec}
reg btn_show_state, btn_set_state, btn_add_state;
reg [31:0] counter;
reg [3:0] flash;
reg [31:0] MAX_COUNTER = 32'D5000_0000;
CommonCounter sec_cc(
.mclk(clk),
.en((base_clk & ~set_led) | add_state[0]),
.s(8'H00),
.e(8'H60),
.init(8'H00),
.num(sec),
.tc(tc_sec_to_min)
);
CommonCounter min_cc(
.mclk(clk),
.en((tc_sec_to_min & ~set_led) | add_state[1]),
.s(8'H00),
.e(8'H60),
.init(8'H20),
.num(min),
.tc(tc_min_to_hour)
);
CommonCounter hour_cc(
.mclk(clk),
.en((tc_min_to_hour & ~set_led) | add_state[2]),
.s(8'H00),
.e(8'H24),
.init(8'H14),
.num(hour),
.tc(tc_hour_to_day)
);
CommonCounter day_cc(
.mclk(clk),
.en((tc_hour_to_day & ~set_led) | add_state[3]),
.s(8'H01),
.e(8'H31),
.init(8'H19),
.num(day),
.tc(tc_day_to_month)
);
CommonCounter month_cc(
.mclk(clk),
.en((tc_day_to_month & ~set_led) | add_state[4]),
.s(8'H01),
.e(8'H13),
.init(8'H12),
.num(month),
.tc(tc_month_to_year)
);
CommonCounter year_cc(
.mclk(clk),
.en((tc_month_to_year & ~set_led) | add_state[5]),
.s(8'H00),
.e(8'Ha0),
.init(8'H17),
.num(year),
.tc(nil)
);
Print print(.clk(clk), .num(num), .flash(flash), .display(display), .an(an));
initial begin
base_clk = 0;
counter = 0;
flash = 0;
show_signal = 0;
set_signal = 0;
btn_show_state = 0;
btn_set_state = 0;
btn_add_state = 0;
set_led = 0;
add_led = 0;
MAX_COUNTER = 32'D5000_0000;
end
always@(posedge clk) begin
// Ä£ÄâbuttonµÄposedge״̬, state´¢´æµÄÊÇÇ°Ò»¸ö״̬
add_state = 0;
if(btn_show != btn_show_state && !btn_show_state) begin
show_signal = show_signal + 1;
end
if(btn_set != btn_set_state && !btn_set_state) begin
set_signal = set_signal + 1;
end
if(btn_add != btn_add_state && !btn_add_state) begin
if(set_signal != 0) begin
case(set_signal)
3'B001: add_state[0] = 1; // sec
3'B010: add_state[1] = 1; // min
3'B011: add_state[2] = 1; // hour
3'B100: add_state[3] = 1; // day
3'B101: add_state[4] = 1; // month
3'B110: add_state[5] = 1; // year
endcase
end
end
btn_show_state = btn_show;
btn_set_state = btn_set;
btn_add_state = btn_add;
counter = counter + 1;
if(counter >= MAX_COUNTER) begin
counter = 0;
base_clk = ~base_clk;
end
case(show_signal)
2'B00: begin num = {min, sec}; show_state = 4'B0001; end
2'B01: begin num = {hour, min}; show_state = 4'B0010; end
2'B10: begin num = {month, day}; show_state = 4'B0100; end
2'B11: begin num = {8'H20, year}; show_state = 4'B1000; end
endcase
case(set_signal)
3'B000: begin set_state = 6'B000000; flash = 4'B0000; end
3'B001: begin set_state = 6'B000001; flash = 4'B0011; show_signal = 2'B00; end
3'B010: begin set_state = 6'B000010; flash = 4'B1100; show_signal = 2'B00; end
3'B011: begin set_state = 6'B000100; flash = 4'B1100; show_signal = 2'B01; end
3'B100: begin set_state = 6'B001000; flash = 4'B0011; show_signal = 2'B10; end
3'B101: begin set_state = 6'B010000; flash = 4'B1100; show_signal = 2'B10; end
3'B110: begin set_state = 6'B100000; flash = 4'B1111; show_signal = 2'B11; end
3'B111: begin set_state = 6'B000000; flash = 4'B0000; show_signal = 2'B00; set_signal = 3'B000; end
endcase
if(set_state == 0) set_led = 0;
else set_led = 1;
if(add_state == 0) add_led = 0;
else add_led = 1;
end
always@(clk_5000_0000, clk_500_0000, clk_50_0000, clk_5_0000,
clk_5000, clk_500, clk_50, clk_5) begin
if(clk_5000_0000) MAX_COUNTER = 5000_0000;
else if(clk_500_0000) MAX_COUNTER = 500_0000;
else if(clk_50_0000) MAX_COUNTER = 50_0000;
else if(clk_5_0000) MAX_COUNTER = 5_0000;
else if(clk_5000) MAX_COUNTER = 5000;
else if(clk_500) MAX_COUNTER = 500;
else if(clk_50) MAX_COUNTER = 50;
else if(clk_5) MAX_COUNTER = 5;
else MAX_COUNTER = 5000_0000;
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XNOR2_2_V
`define SKY130_FD_SC_LS__XNOR2_2_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog wrapper for xnor2 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__xnor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__xnor2_2 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__xnor2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__xnor2_2 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__xnor2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__XNOR2_2_V
|
// note XOR mask starts at bit 0; which may
// be shifted from mathematician's notation.
`include "bsg_defines.v"
module bsg_lfsr #(parameter `BSG_INV_PARAM(width_p)
, init_val_p = 1 // an initial value of zero is typically the null point for LFSR's.
, xor_mask_p = 0)
(input clk
, input reset_i
, input yumi_i
, output logic [width_p-1:0] o
);
logic [width_p-1:0] o_r, o_n, xor_mask;
assign o = o_r;
// auto mask value
if (xor_mask_p == 0)
begin : automask
// fixme fill this in: http://www.eej.ulst.ac.uk/~ian/modules/EEE515/files/old_files/lfsr/lfsr_table.pdf
case (width_p)
32:
assign xor_mask = (1 << 31) | (1 << 29) | (1 << 26) | (1 << 25);
60:
assign xor_mask = (1 << 59) | (1 << 58);
64:
assign xor_mask = (1 << 63) | (1 << 62) | (1 << 60) | (1 << 59);
default:
initial assert(width_p==-1)
else
begin
$display("unhandled default mask for width %d in bsg_lfsr",width_p); $finish();
end
endcase // case (width_p)
end
else
begin: fi
assign xor_mask = xor_mask_p;
end
always @(posedge clk)
begin
if (reset_i)
o_r <= (width_p) ' (init_val_p);
else if (yumi_i)
o_r <= o_n;
end
assign o_n = (o_r >> 1) ^ ({width_p {o_r[0]}} & xor_mask);
endmodule // bsg_lfsr
`BSG_ABSTRACT_MODULE(bsg_lfsr)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXTP_1_V
`define SKY130_FD_SC_LS__DLXTP_1_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog wrapper for dlxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlxtp_1 (
Q ,
D ,
GATE,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input D ;
input GATE;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dlxtp base (
.Q(Q),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlxtp_1 (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dlxtp base (
.Q(Q),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXTP_1_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_slow_rptr.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sctag_slow_rptr(/*AUTOARG*/
// Outputs
areset_l_0_buf, areset_l_1_buf, greset_l_0_buf, greset_l_1_buf,
scan_enable_0_buf, scan_enable_1_buf, sehold_0_buf, sehold_1_buf,
mux_drive_disable_0_buf, mux_drive_disable_1_buf,
mem_write_disable_0_buf, mem_write_disable_1_buf, sig0_buf,
sig1_buf, sig2_buf, sig3_buf,
// Inputs
areset_l_0, areset_l_1, greset_l_0, greset_l_1, scan_enable_0,
scan_enable_1, sehold_0, sehold_1, mux_drive_disable_0,
mux_drive_disable_1, mem_write_disable_0, mem_write_disable_1,
sig0, sig1, sig2, sig3
);
input areset_l_0;
input areset_l_1;
input greset_l_0;
input greset_l_1;
input scan_enable_0;
input scan_enable_1;
input sehold_0;
input sehold_1;
input mux_drive_disable_0;
input mux_drive_disable_1;
input mem_write_disable_0;
input mem_write_disable_1;
input sig0;
input sig1;
input sig2;
input sig3;
output areset_l_0_buf;
output areset_l_1_buf;
output greset_l_0_buf;
output greset_l_1_buf;
output scan_enable_0_buf;
output scan_enable_1_buf;
output sehold_0_buf;
output sehold_1_buf;
output mux_drive_disable_0_buf;
output mux_drive_disable_1_buf;
output mem_write_disable_0_buf;
output mem_write_disable_1_buf;
output sig0_buf;
output sig1_buf;
output sig2_buf;
output sig3_buf;
assign areset_l_0_buf=areset_l_0;
assign areset_l_1_buf=areset_l_1;
assign greset_l_0_buf=greset_l_0;
assign greset_l_1_buf=greset_l_1;
assign scan_enable_0_buf=scan_enable_0;
assign scan_enable_1_buf=scan_enable_1;
assign sehold_0_buf=sehold_0;
assign sehold_1_buf=sehold_1;
assign mux_drive_disable_0_buf=mux_drive_disable_0;
assign mux_drive_disable_1_buf=mux_drive_disable_1;
assign mem_write_disable_0_buf=mem_write_disable_0;
assign mem_write_disable_1_buf=mem_write_disable_1;
assign sig0_buf=sig0;
assign sig1_buf=sig1;
assign sig2_buf=sig2;
assign sig3_buf=sig3;
endmodule
|
`timescale 1ns / 1ps
/*
* Simple Brainfuck CPU in Verilog.
* Copyright (C) 2011 Sergey Gridasov <[email protected]>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`include "pack.v"
module BrainfuckCPU(
CLK, RESET,
IA, IDIN, IEN,
DA, DDIN, DDOUT, DEN, DWE,
CIN, COUT, CRDA, CACK, CWR, CRDY
);
parameter FAST_LOOPEND = 1;
parameter IA_WIDTH = 11;
parameter DA_WIDTH = 11;
parameter DD_WIDTH = 8;
parameter STACK_DEPTH_POW = 7;
input CLK;
input RESET;
// Instruction bus
output reg [IA_WIDTH - 1:0] IA;
input [7:0] IDIN;
output reg IEN;
// Data bus
output [DA_WIDTH - 1:0] DA;
input [DD_WIDTH - 1:0] DDIN;
output [DD_WIDTH - 1:0] DDOUT;
output reg DEN;
output reg DWE;
// Console interface
input [7:0] CIN;
output reg [7:0] COUT;
input CRDA;
output reg CACK;
output reg CWR;
input CRDY;
reg [3:0] STATE;
wire [IA_WIDTH - 1:0] PC;
reg [DA_WIDTH - 1:0] DC;
wire [IA_WIDTH - 1:0] STACK_PC, LOOP_PC;
wire [8:0] DECODED;
wire ZERO;
reg STACK_PUSH, STACK_POP, LOOPSEEK;
reg [STACK_DEPTH_POW - 1:0] LOOP_DEPTH;
wire CONLOAD, PCLOAD;
InstructionDecoder decoder(
.OPCODE(IDIN),
.DECODED(DECODED)
);
GenericCounter #(
.WIDTH(DD_WIDTH)
) dcnt (
.CLK(CLK),
.RESET(RESET),
.D(CONLOAD ? CIN : DDIN),
.Q(DDOUT),
.EN((STATE == `STATE_DFETCH2) || (STATE == `STATE_DUPDATE) || CONLOAD),
.LOAD(STATE == `STATE_DFETCH2 || CONLOAD),
.DOWN(DECODED[`OP_DEC])
);
GenericCounter #(
.WIDTH(IA_WIDTH)
) pcnt (
.CLK(CLK),
.RESET(RESET),
.D(LOOP_PC),
.Q(PC),
.EN((STATE == `STATE_IFETCH) || PCLOAD),
.LOAD(PCLOAD),
.DOWN(1'b0)
);
Stack #(
.WIDTH(IA_WIDTH),
.DEPTH_POW(STACK_DEPTH_POW)
) stack (
.CLK(CLK),
.RESET(RESET),
.PUSH(STACK_PUSH),
.POP(STACK_POP),
.D(PC),
.Q(STACK_PC)
);
always @ (posedge CLK)
if(RESET)
begin
STATE <= `STATE_IFETCH;
IA <= 0;
DC <= 0;
IEN <= 1'b0;
DEN <= 1'b0;
DWE <= 1'b0;
STACK_PUSH <= 1'b0;
STACK_POP <= 1'b0;
LOOPSEEK <= 1'b0;
LOOP_DEPTH <= 0;
COUT <= 8'b0;
CWR <= 1'b0;
CACK <= 1'b0;
end
else
case(STATE)
`STATE_IFETCH:
begin
DEN <= 1'b0;
DWE <= 1'b0;
STACK_PUSH <= 1'b0;
CWR <= 1'b0;
IA <= PC;
IEN <= 1'b1;
STATE <= `STATE_IFETCH2;
end
`STATE_IFETCH2:
begin
IEN <= 1'b0;
if(LOOPSEEK)
STATE <= `STATE_LOOPSEEK;
else
STATE <= `STATE_DECODE;
end
`STATE_DECODE:
begin
if(DECODED[`OP_ILLEGAL])
STATE <= `STATE_IFETCH;
else if(DECODED[`OP_INC] || DECODED[`OP_DEC] || DECODED[`OP_LOOPBEGIN] ||
(DECODED[`OP_LOOPEND] && FAST_LOOPEND) || DECODED[`OP_COUT])
begin
DEN <= 1'b1;
STATE <= `STATE_DFETCH;
end
else if(!FAST_LOOPEND && DECODED[`OP_LOOPEND])
STATE <= `STATE_LOOPEND;
else if(DECODED[`OP_INCPTR])
begin
DC <= DC + 1;
STATE <= `STATE_IFETCH;
end
else if(DECODED[`OP_DECPTR])
begin
DC <= DC - 1;
STATE <= `STATE_IFETCH;
end
else if(DECODED[`OP_CIN])
STATE <= `STATE_CIN;
else
STATE <= `STATE_DECODE;
end
`STATE_DFETCH:
begin
DEN <= 1'b0;
STATE <= `STATE_DFETCH2;
end
`STATE_DFETCH2:
begin
if(DECODED[`OP_LOOPBEGIN])
STATE <= `STATE_LOOPBEGIN;
else if(DECODED[`OP_LOOPEND])
STATE <= `STATE_LOOPEND;
else if(DECODED[`OP_COUT])
STATE <= `STATE_COUT;
else
STATE <= `STATE_DUPDATE;
end
`STATE_DUPDATE:
begin
STATE <= `STATE_WRITEBACK;
end
`STATE_WRITEBACK:
begin
CACK <= 1'b0;
DEN <= 1'b1;
DWE <= 1'b1;
STATE <= `STATE_IFETCH;
end
`STATE_LOOPBEGIN:
begin
if(ZERO)
begin
LOOPSEEK <= 1'b1;
LOOP_DEPTH <= 1;
end
else
STACK_PUSH <= 1'b1;
STATE <= `STATE_IFETCH;
end
`STATE_LOOPEND:
begin
STACK_POP <= 1'b1;
STATE <= `STATE_LOOPEND2;
end
`STATE_LOOPEND2:
begin
STACK_POP <= 1'b0;
STATE <= `STATE_LOOPEND3;
end
`STATE_LOOPEND3:
begin
STATE <= `STATE_IFETCH;
end
`STATE_LOOPSEEK:
begin
if(DECODED[`OP_LOOPBEGIN])
LOOP_DEPTH <= LOOP_DEPTH + 1;
else if(DECODED[`OP_LOOPEND])
begin
if(LOOP_DEPTH == 1)
LOOPSEEK <= 1'b0;
LOOP_DEPTH <= LOOP_DEPTH - 1;
end
STATE <= `STATE_IFETCH;
end
`STATE_COUT:
begin
if(CRDY)
begin
COUT <= DDOUT;
CWR <= 1'b1;
STATE <= `STATE_IFETCH;
end
else
STATE <= `STATE_COUT;
end
`STATE_CIN:
if(CRDA)
begin
CACK <= 1'b1;
STATE <= `STATE_WRITEBACK;
end
else
STATE <= `STATE_CIN;
endcase
assign DA = DC;
assign CONLOAD = (STATE == `STATE_CIN) && CRDA;
assign PCLOAD = (!ZERO || !FAST_LOOPEND) && STATE == `STATE_LOOPEND3;
assign LOOP_PC = STACK_PC - 1;
assign ZERO = DDOUT == 0;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYGATE4SD2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__DLYGATE4SD2_FUNCTIONAL_PP_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__dlygate4sd2 (
X ,
A ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
// Local signals
wire buf0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYGATE4SD2_FUNCTIONAL_PP_V |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Fri Oct 27 10:20:39 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_xlconstant_0_1/RAT_xlconstant_0_1_sim_netlist.v
// Design : RAT_xlconstant_0_1
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* downgradeipidentifiedwarnings = "yes" *)
(* NotValidForBitStream *)
module RAT_xlconstant_0_1
(dout);
output [1:0]dout;
wire \<const0> ;
assign dout[1] = \<const0> ;
assign dout[0] = \<const0> ;
GND GND
(.G(\<const0> ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module SingleCycleProcessor (
output reg [31:0] PC,
output reg [31:0] datain,
output reg [31:0] address,
output reg MW,
input [31:0] instruction,
input [31:0] dataout,
input clk,
input reset_n
);
reg [31:0] nextPC, counter, nextReg, seIM, zfIM;
reg [31:0] R[0:31];
reg RW;
wire [14:0] IM;
wire [4:0] AA, BA, DA;
wire [6:0] op;
wire [3:0] FS;
parameter NOP = 7'b0000000;
parameter MOVA = 7'b1000000;
parameter ADD = 7'b0000010;
parameter SUB = 7'b0000101;
parameter AND = 7'b0001000;
parameter OR = 7'b0001001;
parameter XOR = 7'b0001010;
parameter NOT = 7'b0001011;
parameter ADI = 7'b0100010;
parameter SBI = 7'b0100101;
parameter ANI = 7'b0101000;
parameter ORI = 7'b0101001;
parameter XRI = 7'b0101010;
parameter AIU = 7'b1000010;
parameter SIU = 7'b1000101;
parameter MOVB = 7'b0001100;
parameter LSR = 7'b0001101;
parameter LSL = 7'b0001110;
parameter LD = 7'b0010000;
parameter ST = 7'b0100000;
parameter JMR = 7'b1110000;
parameter SLT = 7'b1100101;
parameter BZ = 7'b1100000;
parameter BNZ = 7'b1001000;
parameter JMP = 7'b1101000;
parameter JML = 7'b0110000;
integer i;
// PC
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
counter <= 0;
PC <= 0;
for (i = 0; i < 32; i = i + 1) begin
R[i] = 0;
end
end else begin
if (counter == 0) begin
counter <= counter + 1;
PC <= nextPC;
end else begin
counter <= 0;
PC <= nextPC;
if (RW == 1'b1 && DA != 0) begin
R[DA] = nextReg;
end
end
end
end
// Decoder
assign AA = instruction[19:15];
assign BA = instruction[14:10];
assign DA = instruction[24:20];
assign op = instruction[31:25];
assign IM = instruction[14:0];
assign SH = instruction[4:0];
always @(*) begin
if (IM[14] == 1'b0) begin
seIM = {17'd0, IM};
zfIM = {17'd0, IM};
end else begin
seIM = {17'd1, IM};
zfIM = {17'd0, IM};
end
end
always @(*) begin
RW = 1'b0;
MW = 1'b1;
nextReg = 0;
address = 0;
datain = 0;
if (counter == 1) begin
case(op)
MOVA: begin
nextReg = R[AA];
RW = 1'b1;
end
ADD: begin
nextReg = R[AA] + R[BA];
RW = 1'b1;
end
SUB: begin
nextReg = R[AA] + (~R[BA]) + 1;
RW = 1'b1;
end
AND: begin
nextReg = R[AA] & R[BA];
RW = 1'b1;
end
OR: begin
nextReg = R[AA] | R[BA];
RW = 1'b1;
end
XOR: begin
nextReg = R[AA] ^ R[BA];
RW = 1'b1;
end
NOT: begin
nextReg = ~R[AA];
RW = 1'b1;
end
ADI: begin
nextReg = R[AA] + seIM;
RW = 1'b1;
end
SBI: begin
nextReg = R[AA] + (~seIM) + 1;
RW = 1'b1;
end
ANI: begin
nextReg = R[AA] & zfIM;
RW = 1'b1;
end
ORI: begin
nextReg = R[AA] | zfIM;
RW = 1'b1;
end
XRI: begin
nextReg = R[AA] ^ zfIM;
RW = 1'b1;
end
AIU: begin
nextReg = R[AA] + zfIM;
RW = 1'b1;
end
SIU: begin
nextReg = R[AA] + (~zfIM) + 1;
RW = 1'b1;
end
MOVB: begin
nextReg = R[BA];
RW = 1'b1;
end
LSR: begin
nextReg = R[AA] >> SH;
RW = 1'b1;
end
LSL: begin
nextReg = R[AA] << SH;
RW = 1'b1;
end
LD: begin
nextReg = dataout;
RW = 1'b1;
end
ST: begin
address = R[AA];
datain = R[BA];
MW = 1'b0;
end
SLT: begin
if (R[AA] < R[BA]) begin
nextReg = 1;
RW = 1'b1;
end else begin
nextReg = 0;
RW = 1'b1;
end
end
JMR: begin
nextPC = R[AA];
end
JMP: begin
nextPC = PC + 1 + seIM;
end
JML: begin
nextPC = PC + 1 + seIM;
end
BZ: begin
if (R[AA] == 0)
nextPC = PC + 1 + seIM;
else
nextPC = PC + 1;
end
BNZ: begin
if (R[AA] != 0)
nextPC = PC + 1 + seIM;
else
nextPC = PC + 1;
end
default: begin
nextPC = PC + 1;
end
endcase
end else begin
if (op == LD) begin
address = R[AA];
MW = 1'b1;
end
nextPC = PC;
end
end
endmodule
|
`include "defines.v"
module mmu(
input wire clk,
input wire rst,
//Input
//Control from MemControl
input wire[2:0] memOp_i,
input wire[31:0] storeData_i,
input wire[31:0] memAddr_i,
//Data from physical device control
input wire[31:0] sram_ramData_i,
input wire[31:0] rom_ramData_i,
input wire[31:0] flash_ramData_i,
input wire[31:0] serial_ramData_i,
//From CP0
input wire[31:0] cp0_Status_i,
input wire[31:0] cp0_Index_i,
input wire[31:0] cp0_EntryLo0_i,
input wire[31:0] cp0_EntryLo1_i,
input wire[31:0] cp0_EntryHi_i,
//From MEM_WB
input wire[3:0] exception_i,
//Output
//SramControl
output reg[2:0] sram_ramOp_o,
output reg[31:0] sram_storeData_o,
output reg[21:0] sram_ramAddr_o,
//Rom
output reg[15:0] rom_ramAddr_o,
//SerialControl
output reg[2:0] serial_ramOp_o,
output reg serial_mode_o,
output reg[7:0] serial_storeData_o,
//FlashControl
output reg[2:0] flash_ramOp_o,
output reg[22:0] flash_ramAddr_o,
output reg[15:0] flash_storeData_o,
//Data to memcontrol
output reg[31:0] memData_o,
//Exception
output reg[3:0] exceptionMMU_o
);
//Check
wire isAddrUnaligned = ((memOp_i == `MEM_LW_OP || memOp_i == `MEM_SW_OP) && memAddr_i[1:0] != 2'b00);
wire isUnmapped = (memAddr_i[31:30] == 2'b10);
wire isKernelAddr = (memAddr_i[31] == 1'b1);
wire EXL = cp0_Status_i[`Status_EXL];
wire ERL = cp0_Status_i[`Status_ERL];
wire UM = cp0_Status_i[`Status_UM];
wire isUserMode = (UM == 1'b1 && EXL == 1'b0 && ERL == 1'b0);
wire isWrite = (memOp_i == `MEM_SW_OP || memOp_i == `MEM_SB_OP);
//Address Mapping
reg[2:0] destination;
wire[31:0] addr_serial = `COM_ADDR;
always @(*) begin
if (memAddr_i[31:24] == 8'hbe) begin
destination = `MMU_FLASH;
end else if (memAddr_i[31:12] == 20'hbfc00) begin
destination = `MMU_ROM;
end else if (memAddr_i[31:3] == addr_serial[31:3]) begin
destination = `MMU_SERIAL;
end else begin
destination = `MMU_SRAM;
end
end
wire[7:0] curASID = cp0_EntryHi_i[7:0];
wire[18:0] curVPN2 = memAddr_i[31:13];
//TLB defination
reg[18:0] VPN2[0:15]; reg G[0:15]; reg[7:0] ASID[0:15];
reg[19:0] PFN0[0:15]; reg D0[0:15]; reg V0[0:15];
reg[19:0] PFN1[0:15]; reg D1[0:15]; reg V1[0:15];
//TLB lookup
wire[15:0] hitVec; reg hit;
reg[19:0] overPFN0; reg overD0; reg overV0;
reg[19:0] overPFN1; reg overD1; reg overV1;
//match
generate
genvar i;
for (i = 0; i < 16; i = i + 1)
begin: TLB_Lookup
assign hitVec[i] = (curVPN2 == VPN2[i] && (G[i] == 1'b1 || curASID == ASID[i]) && (V0[i] == 1'b1 || V1[i] == 1'b1));
end
endgenerate
//final result
reg isHit; reg[19:0] finalPFN;
reg[31:0] finalAddr;
always @(*) begin
//select
case (hitVec)
16'b0000_0000_0000_0001:begin
overPFN0 = PFN0[0]; overD0 = D0[0]; overV0 = V0[0];
overPFN1 = PFN1[0]; overD1 = D1[0]; overV1 = V1[0];
hit = 1'b1;
end
16'b0000_0000_0000_0010:begin
overPFN0 = PFN0[1]; overD0 = D0[1]; overV0 = V0[1];
overPFN1 = PFN1[1]; overD1 = D1[1]; overV1 = V1[1];
hit = 1'b1;
end
16'b0000_0000_0000_0100:begin
overPFN0 = PFN0[2]; overD0 = D0[2]; overV0 = V0[2];
overPFN1 = PFN1[2]; overD1 = D1[2]; overV1 = V1[2];
hit = 1'b1;
end
16'b0000_0000_0000_1000:begin
overPFN0 = PFN0[3]; overD0 = D0[3]; overV0 = V0[3];
overPFN1 = PFN1[3]; overD1 = D1[3]; overV1 = V1[3];
hit = 1'b1;
end
16'b0000_0000_0001_0000:begin
overPFN0 = PFN0[4]; overD0 = D0[4]; overV0 = V0[4];
overPFN1 = PFN1[4]; overD1 = D1[4]; overV1 = V1[4];
hit = 1'b1;
end
16'b0000_0000_0010_0000:begin
overPFN0 = PFN0[5]; overD0 = D0[5]; overV0 = V0[5];
overPFN1 = PFN1[5]; overD1 = D1[5]; overV1 = V1[5];
hit = 1'b1;
end
16'b0000_0000_0100_0000:begin
overPFN0 = PFN0[6]; overD0 = D0[6]; overV0 = V0[6];
overPFN1 = PFN1[6]; overD1 = D1[6]; overV1 = V1[6];
hit = 1'b1;
end
16'b0000_0000_1000_0000:begin
overPFN0 = PFN0[7]; overD0 = D0[7]; overV0 = V0[7];
overPFN1 = PFN1[7]; overD1 = D1[7]; overV1 = V1[7];
hit = 1'b1;
end
16'b0000_0001_0000_0000:begin
overPFN0 = PFN0[8]; overD0 = D0[8]; overV0 = V0[8];
overPFN1 = PFN1[8]; overD1 = D1[8]; overV1 = V1[8];
hit = 1'b1;
end
16'b0000_0010_0000_0000:begin
overPFN0 = PFN0[9]; overD0 = D0[9]; overV0 = V0[9];
overPFN1 = PFN1[9]; overD1 = D1[9]; overV1 = V1[9];
hit = 1'b1;
end
16'b0000_0100_0000_0000:begin
overPFN0 = PFN0[10]; overD0 = D0[10]; overV0 = V0[10];
overPFN1 = PFN1[10]; overD1 = D1[10]; overV1 = V1[10];
hit = 1'b1;
end
16'b0000_1000_0000_0000:begin
overPFN0 = PFN0[11]; overD0 = D0[11]; overV0 = V0[11];
overPFN1 = PFN1[11]; overD1 = D1[11]; overV1 = V1[11];
hit = 1'b1;
end
16'b0001_0000_0000_0000:begin
overPFN0 = PFN0[12]; overD0 = D0[12]; overV0 = V0[12];
overPFN1 = PFN1[12]; overD1 = D1[12]; overV1 = V1[12];
hit = 1'b1;
end
16'b0010_0000_0000_0000:begin
overPFN0 = PFN0[13]; overD0 = D0[13]; overV0 = V0[13];
overPFN1 = PFN1[13]; overD1 = D1[13]; overV1 = V1[13];
hit = 1'b1;
end
16'b0100_0000_0000_0000:begin
overPFN0 = PFN0[14]; overD0 = D0[14]; overV0 = V0[14];
overPFN1 = PFN1[14]; overD1 = D1[14]; overV1 = V1[14];
hit = 1'b1;
end
16'b1000_0000_0000_0000:begin
overPFN0 = PFN0[15]; overD0 = D0[15]; overV0 = V0[15];
overPFN1 = PFN1[15]; overD1 = D1[15]; overV1 = V1[15];
hit = 1'b1;
end
default: begin
overPFN0 = 20'h0; overD0 = 1'b0; overV0 = 1'b0;
overPFN1 = 20'h0; overD1 = 1'b0; overV1 = 1'b0;
hit = 1'b0;
end
endcase
//check
if (hit == 1'b1) begin
if (memAddr_i[12] == 1'b1) begin
//PFN1
isHit = (overV1 == 1'b1 && (isWrite == 1'b0 || overD1 == 1'b1));
finalPFN = overPFN1;
end else begin
//PFN0
isHit = (overV0 == 1'b1 && (isWrite == 1'b0 || overD0 == 1'b1));
finalPFN = overPFN0;
end
end else begin
isHit = 1'b0;
finalPFN = 20'b0;
end
finalAddr = {finalPFN, memAddr_i[11:0]};
end
//TLB Write
wire[3:0] index = cp0_Index_i[3:0];
always @(posedge clk) begin
if (rst == `Enable) begin : init
integer i;
for (i = 0; i < 16; i = i + 1)
begin
VPN2[i] <= 19'h0; G[i] <= 1'b0; ASID[i] <= 8'h0;
PFN0[i] <= 20'h0; D0[i] <= 1'b0; V0[i] <= 1'b0;
PFN1[i] <= 20'h0; D1[i] <= 1'b0; V1[i] <= 1'b0;
end
end else if (exception_i == `EXC_TLBWI) begin
VPN2[index] <= cp0_EntryHi_i[31:13]; ASID[index] <= cp0_EntryHi_i[7:0];
PFN0[index] <= cp0_EntryLo0_i[25:6]; D0[index] <= cp0_EntryLo0_i[2]; V0[index] <= cp0_EntryLo0_i[1];
PFN1[index] <= cp0_EntryLo1_i[25:6]; D1[index] <= cp0_EntryLo1_i[2]; V1[index] <= cp0_EntryLo1_i[1];
G[index] <= cp0_EntryLo0_i[0] & cp0_EntryLo1_i[0];
end
end
//Exception
always @(*) begin
if ((isAddrUnaligned == 1'b1 && destination != `MMU_SERIAL) || (isUserMode == 1'b1 && isKernelAddr == 1'b1)) begin
exceptionMMU_o = `EXC_ADE;
end else if (isUnmapped == 1'b0 && isHit == 1'b0) begin
case (memOp_i)
`MEM_LW_OP:
exceptionMMU_o = `EXC_TLBL;
`MEM_SW_OP:
exceptionMMU_o = `EXC_TLBS;
default:
exceptionMMU_o = `EXC_NONE;
endcase
end else begin
exceptionMMU_o = `EXC_NONE;
end
end
//Data Fetch
always @(*) begin
//SRAM
sram_ramOp_o = `MEM_NOP_OP;
sram_storeData_o = `ZeroWord;
sram_ramAddr_o = 22'h0;
//ROM
rom_ramAddr_o = `ZeroHalfWord;
//Serial
serial_ramOp_o = `MEM_NOP_OP;
serial_mode_o = `Disable;
serial_storeData_o = `ZeroByte;
//Flash
flash_ramAddr_o = 23'h0;
flash_ramOp_o = `MEM_NOP_OP;
flash_storeData_o = `ZeroHalfWord;
//Data
memData_o = `ZeroWord;
if (exceptionMMU_o == `EXC_NONE) begin
case (destination)
`MMU_NOP: begin
end
`MMU_SRAM: begin
//SRAM
sram_ramOp_o = memOp_i;
sram_storeData_o = storeData_i;
if (isUnmapped == 1'b1) begin
sram_ramAddr_o = memAddr_i[23:2];
end else begin
sram_ramAddr_o = finalAddr[23:2];
end
//Data
memData_o = sram_ramData_i;
end
`MMU_FLASH: begin
//Flash
flash_ramOp_o = memOp_i;
flash_ramAddr_o = {memAddr_i[23:2], memAddr_i[0]};
flash_storeData_o = storeData_i[15:0];
//Data
memData_o = flash_ramData_i;
end
`MMU_ROM: begin
//ROM
rom_ramAddr_o = memAddr_i[15:0];
//Data
memData_o = rom_ramData_i;
end
`MMU_SERIAL: begin
//Serial
serial_ramOp_o = memOp_i;
serial_mode_o = memAddr_i[2];
serial_storeData_o = storeData_i[7:0];
//Data
memData_o = serial_ramData_i;
end
default: begin
end
endcase
end
end
endmodule
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: rom.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rom (
address,
clock,
data,
wren,
q);
input [11:0] address;
input clock;
input [7:0] data;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
`ifdef NO_PLI
altsyncram_component.init_file = "../fware.rif"
`else
altsyncram_component.init_file = "../fware.hex"
`endif
,
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../fware.hex"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "8"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../fware.hex"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL rom.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rom_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:41:59 02/07/2016
// Design Name: bcdAdder
// Module Name: F:/VLSI Lab/bcdAdder/bcdAdderTest.v
// Project Name: bcdAdder
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: bcdAdder
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module bcdAdderTest;
// Inputs
reg [3:0] a;
reg [3:0] b;
reg cin;
// Outputs
wire [3:0] sum;
wire cout;
reg [3:0] i,j;
// Instantiate the Unit Under Test (UUT)
bcdAdder uut (
.a(a),
.b(b),
.cin(cin),
.sum(sum),
.cout(cout)
);
initial begin
a = 4'b0000;
b = 4'b0000;
cin=1'b0;
end
always @(a,b)
begin
for(i=0;i<10;i=i+1)
begin
{a}=i;
for(j=0;j<10;j=j+1)
begin
{b}=j;
#10;
end
end
$stop;
end
endmodule
|
// readStreamTest.v
// Testbench for integration of EBABReadStream and EBABWriteMaster
`timescale 1ns/1ns
module project_top();
reg rst, clk;
wire [31:0] bus_addr; // Avalon address
wire [3:0] bus_byte_enable; // four bit byte read/write mask
wire bus_read; // high when requesting data
wire bus_write; // high when writing data
wire [31:0] bus_write_data; // data to send to Avalog bus
reg bus_ack; // Avalon bus raises this when done
reg [31:0] bus_read_data; // data from Avalon bus
reg [31:0] counter;
wire [31:0] audio_fifo_address = 32'h00003044; // Avalon address +4
wire [31:0] audio_left_address = 32'h00003048; // Avalon address +8
wire [31:0] audio_right_address = 32'h0000304c; // Avalon address +12
// make reset
initial begin
bus_read_data = 32'b0;
counter = 32'b0;
clk = 1'b0;
rst = 1'b0;
#50
rst = 1'b1;
#100
rst = 1'b0;
end
// make clock
always begin
#10
clk = !clk;
end
always @(posedge clk) begin
// fake bus acjs
bus_ack <= bus_write | bus_read;
end
always @(posedge bus_read) begin
// fake bus reads
if (bus_addr == audio_fifo_address) begin
bus_read_data <= (8'd3 << 24) | 8'd2; // allow reads and writes
end
else if ((bus_addr == audio_right_address)) begin
counter <= counter + 1;
bus_read_data <= counter;
end
end
EBABWrapper ebab_wrapper
(
// Outputs
.bus_byte_enable(bus_byte_enable),
.bus_read(bus_read),
.bus_write(bus_write),
.bus_write_data(bus_write_data),
.bus_addr(bus_addr),
// Inputs
.clk(clk),
.rst(rst),
.bus_ack(bus_ack),
.bus_read_data(bus_read_data)
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : mig_7series_v2_0_tempmon.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Jul 25 2012
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Monitors chip temperature via the XADC and adjusts the
// stage 2 tap values as appropriate.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_0_tempmon #
(
parameter TCQ = 100, // Register delay (sim only)
parameter TEMP_MON_CONTROL = "INTERNAL", // XADC or user temperature source
parameter XADC_CLK_PERIOD = 5000, // pS (default to 200 MHz refclk)
parameter tTEMPSAMPLE = 10000000 // ps (10 us)
)
(
input clk, // Fabric clock
input xadc_clk,
input rst, // System reset
input [11:0] device_temp_i, // User device temperature
output [11:0] device_temp // Sampled temperature
);
//***************************************************************************
// Function cdiv
// Description:
// This function performs ceiling division (divide and round-up)
// Inputs:
// num: integer to be divided
// div: divisor
// Outputs:
// cdiv: result of ceiling division (num/div, rounded up)
//***************************************************************************
function integer cdiv (input integer num, input integer div);
begin
// perform division, then add 1 if and only if remainder is non-zero
cdiv = (num/div) + (((num%div)>0) ? 1 : 0);
end
endfunction // cdiv
//***************************************************************************
// Function clogb2
// Description:
// This function performs binary logarithm and rounds up
// Inputs:
// size: integer to perform binary log upon
// Outputs:
// clogb2: result of binary logarithm, rounded up
//***************************************************************************
function integer clogb2 (input integer size);
begin
size = size - 1;
// increment clogb2 from 1 for each bit in size
for (clogb2 = 1; size > 1; clogb2 = clogb2 + 1)
size = size >> 1;
end
endfunction // clogb2
// Synchronization registers
(* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r1;
(* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r2;
(* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r3 /* synthesis syn_srlstyle="registers" */;
(* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r4;
(* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_sync_r5;
// Output register
(* ASYNC_REG = "TRUE" *) reg [11:0] device_temp_r;
wire [11:0] device_temp_lcl;
reg [3:0] sync_cntr = 4'b0000;
reg device_temp_sync_r4_neq_r3;
// (* ASYNC_REG = "TRUE" *) reg rst_r1;
// (* ASYNC_REG = "TRUE" *) reg rst_r2;
// // Synchronization rst to XADC clock domain
// always @(posedge xadc_clk) begin
// rst_r1 <= rst;
// rst_r2 <= rst_r1;
// end
// Synchronization counter
always @(posedge clk) begin
device_temp_sync_r1 <= #TCQ device_temp_lcl;
device_temp_sync_r2 <= #TCQ device_temp_sync_r1;
device_temp_sync_r3 <= #TCQ device_temp_sync_r2;
device_temp_sync_r4 <= #TCQ device_temp_sync_r3;
device_temp_sync_r5 <= #TCQ device_temp_sync_r4;
device_temp_sync_r4_neq_r3 <= #TCQ (device_temp_sync_r4 != device_temp_sync_r3) ? 1'b1 : 1'b0;
end
always @(posedge clk)
if(rst || (device_temp_sync_r4_neq_r3))
sync_cntr <= #TCQ 4'b0000;
else if(~&sync_cntr)
sync_cntr <= #TCQ sync_cntr + 4'b0001;
always @(posedge clk)
if(&sync_cntr)
device_temp_r <= #TCQ device_temp_sync_r5;
assign device_temp = device_temp_r;
generate
if(TEMP_MON_CONTROL == "EXTERNAL") begin : user_supplied_temperature
assign device_temp_lcl = device_temp_i;
end else begin : xadc_supplied_temperature
// calculate polling timer width and limit
localparam nTEMPSAMP = cdiv(tTEMPSAMPLE, XADC_CLK_PERIOD);
localparam nTEMPSAMP_CLKS = nTEMPSAMP;
localparam nTEMPSAMP_CLKS_M6 = nTEMPSAMP - 6;
localparam nTEMPSAMP_CNTR_WIDTH = clogb2(nTEMPSAMP_CLKS);
// Temperature sampler FSM encoding
localparam INIT_IDLE = 2'b00;
localparam REQUEST_READ_TEMP = 2'b01;
localparam WAIT_FOR_READ = 2'b10;
localparam READ = 2'b11;
// polling timer and tick
reg [nTEMPSAMP_CNTR_WIDTH-1:0] sample_timer = {nTEMPSAMP_CNTR_WIDTH{1'b0}};
reg sample_timer_en = 1'b0;
reg sample_timer_clr = 1'b0;
reg sample_en = 1'b0;
// Temperature sampler state
reg [2:0] tempmon_state = INIT_IDLE;
reg [2:0] tempmon_next_state = INIT_IDLE;
// XADC interfacing
reg xadc_den = 1'b0;
wire xadc_drdy;
wire [15:0] xadc_do;
reg xadc_drdy_r = 1'b0;
reg [15:0] xadc_do_r = 1'b0;
// Temperature storage
reg [11:0] temperature = 12'b0;
// Reset sync
(* ASYNC_REG = "TRUE" *) reg rst_r1;
(* ASYNC_REG = "TRUE" *) reg rst_r2;
// Synchronization rst to XADC clock domain
always @(posedge xadc_clk) begin
rst_r1 <= rst;
rst_r2 <= rst_r1;
end
// XADC polling interval timer
always @ (posedge xadc_clk)
if(rst_r2 || sample_timer_clr)
sample_timer <= #TCQ {nTEMPSAMP_CNTR_WIDTH{1'b0}};
else if(sample_timer_en)
sample_timer <= #TCQ sample_timer + 1'b1;
// XADC sampler state transition
always @(posedge xadc_clk)
if(rst_r2)
tempmon_state <= #TCQ INIT_IDLE;
else
tempmon_state <= #TCQ tempmon_next_state;
// Sample enable
always @(posedge xadc_clk)
sample_en <= #TCQ (sample_timer == nTEMPSAMP_CLKS_M6) ? 1'b1 : 1'b0;
// XADC sampler next state transition
always @(tempmon_state or sample_en or xadc_drdy_r) begin
tempmon_next_state = tempmon_state;
case(tempmon_state)
INIT_IDLE:
if(sample_en)
tempmon_next_state = REQUEST_READ_TEMP;
REQUEST_READ_TEMP:
tempmon_next_state = WAIT_FOR_READ;
WAIT_FOR_READ:
if(xadc_drdy_r)
tempmon_next_state = READ;
READ:
tempmon_next_state = INIT_IDLE;
default:
tempmon_next_state = INIT_IDLE;
endcase
end
// Sample timer clear
always @(posedge xadc_clk)
if(rst_r2 || (tempmon_state == WAIT_FOR_READ))
sample_timer_clr <= #TCQ 1'b0;
else if(tempmon_state == REQUEST_READ_TEMP)
sample_timer_clr <= #TCQ 1'b1;
// Sample timer enable
always @(posedge xadc_clk)
if(rst_r2 || (tempmon_state == REQUEST_READ_TEMP))
sample_timer_en <= #TCQ 1'b0;
else if((tempmon_state == INIT_IDLE) || (tempmon_state == READ))
sample_timer_en <= #TCQ 1'b1;
// XADC enable
always @(posedge xadc_clk)
if(rst_r2 || (tempmon_state == WAIT_FOR_READ))
xadc_den <= #TCQ 1'b0;
else if(tempmon_state == REQUEST_READ_TEMP)
xadc_den <= #TCQ 1'b1;
// Register XADC outputs
always @(posedge xadc_clk)
if(rst_r2) begin
xadc_drdy_r <= #TCQ 1'b0;
xadc_do_r <= #TCQ 16'b0;
end
else begin
xadc_drdy_r <= #TCQ xadc_drdy;
xadc_do_r <= #TCQ xadc_do;
end
// Store current read value
always @(posedge xadc_clk)
if(rst_r2)
temperature <= #TCQ 12'b0;
else if(tempmon_state == READ)
temperature <= #TCQ xadc_do_r[15:4];
assign device_temp_lcl = temperature;
// XADC: Dual 12-Bit 1MSPS Analog-to-Digital Converter
// 7 Series
// Xilinx HDL Libraries Guide, version 14.1
XADC #(
// INIT_40 - INIT_42: XADC configuration registers
.INIT_40(16'h1000), // config reg 0
.INIT_41(16'h2fff), // config reg 1
.INIT_42(16'h0800), // config reg 2
// INIT_48 - INIT_4F: Sequence Registers
.INIT_48(16'h0101), // Sequencer channel selection
.INIT_49(16'h0000), // Sequencer channel selection
.INIT_4A(16'h0100), // Sequencer Average selection
.INIT_4B(16'h0000), // Sequencer Average selection
.INIT_4C(16'h0000), // Sequencer Bipolar selection
.INIT_4D(16'h0000), // Sequencer Bipolar selection
.INIT_4E(16'h0000), // Sequencer Acq time selection
.INIT_4F(16'h0000), // Sequencer Acq time selection
// INIT_50 - INIT_58, INIT5C: Alarm Limit Registers
.INIT_50(16'hb5ed), // Temp alarm trigger
.INIT_51(16'h57e4), // Vccint upper alarm limit
.INIT_52(16'ha147), // Vccaux upper alarm limit
.INIT_53(16'hca33), // Temp alarm OT upper
.INIT_54(16'ha93a), // Temp alarm reset
.INIT_55(16'h52c6), // Vccint lower alarm limit
.INIT_56(16'h9555), // Vccaux lower alarm limit
.INIT_57(16'hae4e), // Temp alarm OT reset
.INIT_58(16'h5999), // VBRAM upper alarm limit
.INIT_5C(16'h5111), // VBRAM lower alarm limit
// Simulation attributes: Set for proepr simulation behavior
.SIM_DEVICE("7SERIES") // Select target device (values)
)
XADC_inst (
// ALARMS: 8-bit (each) output: ALM, OT
.ALM(), // 8-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram
.OT(), // 1-bit output: Over-Temperature alarm
// Dynamic Reconfiguration Port (DRP): 16-bit (each) output: Dynamic Reconfiguration Ports
.DO(xadc_do), // 16-bit output: DRP output data bus
.DRDY(xadc_drdy), // 1-bit output: DRP data ready
// STATUS: 1-bit (each) output: XADC status ports
.BUSY(), // 1-bit output: ADC busy output
.CHANNEL(), // 5-bit output: Channel selection outputs
.EOC(), // 1-bit output: End of Conversion
.EOS(), // 1-bit output: End of Sequence
.JTAGBUSY(), // 1-bit output: JTAG DRP transaction in progress output
.JTAGLOCKED(), // 1-bit output: JTAG requested DRP port lock
.JTAGMODIFIED(), // 1-bit output: JTAG Write to the DRP has occurred
.MUXADDR(), // 5-bit output: External MUX channel decode
// Auxiliary Analog-Input Pairs: 16-bit (each) input: VAUXP[15:0], VAUXN[15:0]
.VAUXN(16'b0), // 16-bit input: N-side auxiliary analog input
.VAUXP(16'b0), // 16-bit input: P-side auxiliary analog input
// CONTROL and CLOCK: 1-bit (each) input: Reset, conversion start and clock inputs
.CONVST(1'b0), // 1-bit input: Convert start input
.CONVSTCLK(1'b0), // 1-bit input: Convert start input
.RESET(1'b0), // 1-bit input: Active-high reset
// Dedicated Analog Input Pair: 1-bit (each) input: VP/VN
.VN(1'b0), // 1-bit input: N-side analog input
.VP(1'b0), // 1-bit input: P-side analog input
// Dynamic Reconfiguration Port (DRP): 7-bit (each) input: Dynamic Reconfiguration Ports
.DADDR(7'b0), // 7-bit input: DRP address bus
.DCLK(xadc_clk), // 1-bit input: DRP clock
.DEN(xadc_den), // 1-bit input: DRP enable signal
.DI(16'b0), // 16-bit input: DRP input data bus
.DWE(1'b0) // 1-bit input: DRP write enable
);
// End of XADC_inst instantiation
end
endgenerate
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
//Default depth for this memory model is 2048, do these when
//changing the depth.
//1)Set ARRAY_DEPTH generic/parameter from 2048 to new depth.
//2)Change mem_array depth from 2047 to (new depth - 1).
//3)VHDL only, don't forget the generic in component declaration
module ram_controller_mem_model_ram_module (
// inputs:
data,
rdaddress,
wraddress,
wrclock,
wren,
// outputs:
q
)
;
parameter ARRAY_DEPTH = 2048;
output [ 31: 0] q;
input [ 31: 0] data;
input [ 24: 0] rdaddress;
input [ 24: 0] wraddress;
input wrclock;
input wren;
wire [ 31: 0] aq;
reg [ 57: 0] mem_array [2047: 0];
wire [ 31: 0] q;
assign aq = mem_array[0][31:0];
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
reg [ 32 - 1: 0] out;
integer i;
reg found_valid_data;
reg data_written;
initial
begin
for (i = 0; i < ARRAY_DEPTH; i = i + 1)
mem_array[i][0] <= 1'b0;
data_written <= 1'b0;
end
always @(rdaddress)
begin
found_valid_data <= 1'b0;
for (i = 0; i < ARRAY_DEPTH; i = i + 1)
begin
if (rdaddress == mem_array[i][58 - 1:58 - 25] && mem_array[i][0])
begin
out = mem_array[i][58 - 25 - 1:58 - 25 - 32];
found_valid_data = 1'b1;
end
end
if (!found_valid_data)
out = 32'dX;
end
always @(posedge wrclock)
if (wren)
begin
data_written <= 1'b0;
for (i = 0; i < ARRAY_DEPTH; i = i + 1)
begin
if (wraddress == mem_array[i][58 - 1:58 - 25] && !data_written)
begin
mem_array[i][58 - 25 - 1:58 - 25 - 32] <= data;
mem_array[i][0] <= 1'b1;
data_written = 1'b1;
end
else if (!mem_array[i][0] && !data_written)
begin
mem_array[i] <= {wraddress,data,1'b1};
data_written = 1'b1;
end
end
if (!data_written)
begin
$write($time);
$write(" --- Data could not be written, increase array depth or use full memory model --- ");
$stop;
end
end
assign q = out;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ram_controller_mem_model (
// inputs:
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_clk,
mem_clk_n,
mem_cs_n,
mem_dm,
mem_odt,
mem_ras_n,
mem_we_n,
// outputs:
global_reset_n,
mem_dq,
mem_dqs,
mem_dqs_n
)
;
output global_reset_n;
inout [ 15: 0] mem_dq;
inout [ 1: 0] mem_dqs;
inout [ 1: 0] mem_dqs_n;
input [ 12: 0] mem_addr;
input [ 2: 0] mem_ba;
input mem_cas_n;
input mem_cke;
input mem_clk;
input mem_clk_n;
input mem_cs_n;
input [ 1: 0] mem_dm;
input mem_odt;
input mem_ras_n;
input mem_we_n;
wire [ 23: 0] CODE;
wire [ 12: 0] a;
reg [ 3: 0] additive_latency;
wire [ 8: 0] addr_col;
wire [ 2: 0] ba;
reg [ 2: 0] burstlength;
reg burstmode;
wire cas_n;
wire cke;
wire clk;
wire [ 2: 0] cmd_code;
wire cs_n;
wire [ 2: 0] current_row;
wire [ 1: 0] dm;
reg [ 3: 0] dm_captured;
reg [ 31: 0] dq_captured;
wire [ 15: 0] dq_temp;
wire dq_valid;
wire [ 1: 0] dqs_temp;
wire dqs_valid;
reg dqs_valid_temp;
reg [ 15: 0] first_half_dq;
wire global_reset_n;
wire [ 31: 0] mem_bytes;
wire [ 15: 0] mem_dq;
wire [ 1: 0] mem_dqs;
wire [ 1: 0] mem_dqs_n;
reg [ 12: 0] open_rows [ 7: 0];
wire ras_n;
reg [ 24: 0] rd_addr_pipe_0;
reg [ 24: 0] rd_addr_pipe_1;
reg [ 24: 0] rd_addr_pipe_10;
reg [ 24: 0] rd_addr_pipe_11;
reg [ 24: 0] rd_addr_pipe_12;
reg [ 24: 0] rd_addr_pipe_13;
reg [ 24: 0] rd_addr_pipe_14;
reg [ 24: 0] rd_addr_pipe_15;
reg [ 24: 0] rd_addr_pipe_16;
reg [ 24: 0] rd_addr_pipe_17;
reg [ 24: 0] rd_addr_pipe_18;
reg [ 24: 0] rd_addr_pipe_19;
reg [ 24: 0] rd_addr_pipe_2;
reg [ 24: 0] rd_addr_pipe_20;
reg [ 24: 0] rd_addr_pipe_21;
reg [ 24: 0] rd_addr_pipe_3;
reg [ 24: 0] rd_addr_pipe_4;
reg [ 24: 0] rd_addr_pipe_5;
reg [ 24: 0] rd_addr_pipe_6;
reg [ 24: 0] rd_addr_pipe_7;
reg [ 24: 0] rd_addr_pipe_8;
reg [ 24: 0] rd_addr_pipe_9;
reg [ 24: 0] rd_burst_counter;
reg [ 25: 0] rd_valid_pipe;
wire [ 24: 0] read_addr_delayed;
reg read_cmd;
reg read_cmd_echo;
wire [ 31: 0] read_data;
wire [ 15: 0] read_dq;
reg [ 4: 0] read_latency;
wire read_valid;
reg read_valid_r;
reg read_valid_r2;
reg read_valid_r3;
reg read_valid_r4;
reg reset_n;
wire [ 24: 0] rmw_address;
reg [ 31: 0] rmw_temp;
reg [ 15: 0] second_half_dq;
reg [ 3: 0] tcl;
wire [ 23: 0] txt_code;
wire we_n;
wire [ 24: 0] wr_addr_delayed;
reg [ 24: 0] wr_addr_delayed_r;
reg [ 24: 0] wr_addr_pipe_0;
reg [ 24: 0] wr_addr_pipe_1;
reg [ 24: 0] wr_addr_pipe_10;
reg [ 24: 0] wr_addr_pipe_11;
reg [ 24: 0] wr_addr_pipe_12;
reg [ 24: 0] wr_addr_pipe_13;
reg [ 24: 0] wr_addr_pipe_14;
reg [ 24: 0] wr_addr_pipe_15;
reg [ 24: 0] wr_addr_pipe_16;
reg [ 24: 0] wr_addr_pipe_17;
reg [ 24: 0] wr_addr_pipe_18;
reg [ 24: 0] wr_addr_pipe_2;
reg [ 24: 0] wr_addr_pipe_3;
reg [ 24: 0] wr_addr_pipe_4;
reg [ 24: 0] wr_addr_pipe_5;
reg [ 24: 0] wr_addr_pipe_6;
reg [ 24: 0] wr_addr_pipe_7;
reg [ 24: 0] wr_addr_pipe_8;
reg [ 24: 0] wr_addr_pipe_9;
reg [ 24: 0] wr_burst_counter;
reg [ 25: 0] wr_valid_pipe;
reg [ 25: 0] write_burst_length_pipe;
reg write_cmd;
reg write_cmd_echo;
reg [ 4: 0] write_latency;
wire write_to_ram;
reg write_to_ram_r;
wire write_valid;
reg write_valid_r;
reg write_valid_r2;
reg write_valid_r3;
initial
begin
$write("\n");
$write("**********************************************************************\n");
$write("This testbench includes a generated Altera memory model:\n");
$write("'ram_controller_mem_model.v', to simulate accesses to the DDR2 SDRAM memory.\n");
$write(" \n");
$write("**********************************************************************\n");
end
//Synchronous write when (CODE == 24'h205752 (write))
ram_controller_mem_model_ram_module ram_controller_mem_model_ram
(
.data (rmw_temp),
.q (read_data),
.rdaddress (rmw_address),
.wraddress (wr_addr_delayed_r),
.wrclock (clk),
.wren (write_to_ram_r)
);
assign clk = mem_clk;
assign dm = mem_dm;
assign cke = mem_cke;
assign cs_n = mem_cs_n;
assign ras_n = mem_ras_n;
assign cas_n = mem_cas_n;
assign we_n = mem_we_n;
assign ba = mem_ba;
assign a = mem_addr;
//generate a fake reset inside the memory model
assign global_reset_n = reset_n;
initial
begin
reset_n <= 0;
#100 reset_n <= 1;
end
assign cmd_code = (&cs_n) ? 3'b111 : {ras_n, cas_n, we_n};
assign CODE = (&cs_n) ? 24'h494e48 : txt_code;
assign addr_col = a[9 : 1];
assign current_row = {ba};
// Decode commands into their actions
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
write_cmd_echo <= 0;
read_cmd_echo <= 0;
end
else // No Activity if the clock is
if (cke)
begin
// Checks whether to echo read cmd
if (read_cmd_echo && !read_cmd)
begin
read_cmd <= 1'b1;
read_cmd_echo <= 1'b0;
end
else // This is a read command
if (cmd_code == 3'b101)
begin
read_cmd <= 1'b1;
read_cmd_echo <= 1'b1;
end
else
read_cmd <= 1'b0;
// Checks whether to echo write cmd
if (write_cmd_echo && !write_cmd)
begin
write_cmd <= 1'b1;
write_cmd_echo <= 1'b0;
end
else // This is a write command
if (cmd_code == 3'b100)
begin
write_cmd <= 1'b1;
write_cmd_echo <= 1'b1;
write_burst_length_pipe[0] <= a[0];
end
else
write_cmd <= 1'b0;
// This is an activate - store the chip/row/bank address in the same order as the DDR controller
if (cmd_code == 3'b011)
open_rows[current_row] <= a;
end
end
// Pipes are flushed here
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
wr_addr_pipe_1 <= 0;
wr_addr_pipe_2 <= 0;
wr_addr_pipe_3 <= 0;
wr_addr_pipe_4 <= 0;
wr_addr_pipe_5 <= 0;
wr_addr_pipe_6 <= 0;
wr_addr_pipe_7 <= 0;
wr_addr_pipe_8 <= 0;
wr_addr_pipe_9 <= 0;
wr_addr_pipe_10 <= 0;
wr_addr_pipe_11 <= 0;
wr_addr_pipe_12 <= 0;
wr_addr_pipe_13 <= 0;
wr_addr_pipe_14 <= 0;
wr_addr_pipe_15 <= 0;
wr_addr_pipe_16 <= 0;
wr_addr_pipe_17 <= 0;
wr_addr_pipe_18 <= 0;
rd_addr_pipe_1 <= 0;
rd_addr_pipe_2 <= 0;
rd_addr_pipe_3 <= 0;
rd_addr_pipe_4 <= 0;
rd_addr_pipe_5 <= 0;
rd_addr_pipe_6 <= 0;
rd_addr_pipe_7 <= 0;
rd_addr_pipe_8 <= 0;
rd_addr_pipe_9 <= 0;
rd_addr_pipe_10 <= 0;
rd_addr_pipe_11 <= 0;
rd_addr_pipe_12 <= 0;
rd_addr_pipe_13 <= 0;
rd_addr_pipe_14 <= 0;
rd_addr_pipe_15 <= 0;
rd_addr_pipe_16 <= 0;
rd_addr_pipe_17 <= 0;
rd_addr_pipe_18 <= 0;
rd_addr_pipe_19 <= 0;
rd_addr_pipe_20 <= 0;
rd_addr_pipe_21 <= 0;
end
else // No Activity if the clock is
if (cke)
begin
rd_addr_pipe_21 <= rd_addr_pipe_20;
rd_addr_pipe_20 <= rd_addr_pipe_19;
rd_addr_pipe_19 <= rd_addr_pipe_18;
rd_addr_pipe_18 <= rd_addr_pipe_17;
rd_addr_pipe_17 <= rd_addr_pipe_16;
rd_addr_pipe_16 <= rd_addr_pipe_15;
rd_addr_pipe_15 <= rd_addr_pipe_14;
rd_addr_pipe_14 <= rd_addr_pipe_13;
rd_addr_pipe_13 <= rd_addr_pipe_12;
rd_addr_pipe_12 <= rd_addr_pipe_11;
rd_addr_pipe_11 <= rd_addr_pipe_10;
rd_addr_pipe_10 <= rd_addr_pipe_9;
rd_addr_pipe_9 <= rd_addr_pipe_8;
rd_addr_pipe_8 <= rd_addr_pipe_7;
rd_addr_pipe_7 <= rd_addr_pipe_6;
rd_addr_pipe_6 <= rd_addr_pipe_5;
rd_addr_pipe_5 <= rd_addr_pipe_4;
rd_addr_pipe_4 <= rd_addr_pipe_3;
rd_addr_pipe_3 <= rd_addr_pipe_2;
rd_addr_pipe_2 <= rd_addr_pipe_1;
rd_addr_pipe_1 <= rd_addr_pipe_0;
rd_valid_pipe[25 : 1] <= rd_valid_pipe[24 : 0];
rd_valid_pipe[0] <= cmd_code == 3'b101;
wr_addr_pipe_18 <= wr_addr_pipe_17;
wr_addr_pipe_17 <= wr_addr_pipe_16;
wr_addr_pipe_16 <= wr_addr_pipe_15;
wr_addr_pipe_15 <= wr_addr_pipe_14;
wr_addr_pipe_14 <= wr_addr_pipe_13;
wr_addr_pipe_13 <= wr_addr_pipe_12;
wr_addr_pipe_12 <= wr_addr_pipe_11;
wr_addr_pipe_11 <= wr_addr_pipe_10;
wr_addr_pipe_10 <= wr_addr_pipe_9;
wr_addr_pipe_9 <= wr_addr_pipe_8;
wr_addr_pipe_8 <= wr_addr_pipe_7;
wr_addr_pipe_7 <= wr_addr_pipe_6;
wr_addr_pipe_6 <= wr_addr_pipe_5;
wr_addr_pipe_5 <= wr_addr_pipe_4;
wr_addr_pipe_4 <= wr_addr_pipe_3;
wr_addr_pipe_3 <= wr_addr_pipe_2;
wr_addr_pipe_2 <= wr_addr_pipe_1;
wr_addr_pipe_1 <= wr_addr_pipe_0;
wr_valid_pipe[25 : 1] <= wr_valid_pipe[24 : 0];
wr_valid_pipe[0] <= cmd_code == 3'b100;
wr_addr_delayed_r <= wr_addr_delayed;
write_burst_length_pipe[25 : 1] <= write_burst_length_pipe[24 : 0];
end
end
// Decode CAS Latency from bits a[6:4]
always @(posedge clk)
begin
// No Activity if the clock is disabled
if (cke)
//Load mode register - set CAS latency, burst mode and length
if (cmd_code == 3'b000 && ba == 2'b00)
begin
burstmode <= a[3];
burstlength <= a[2 : 0] << 1;
//CAS Latency = 3.0
if (a[6 : 4] == 3'b011)
tcl <= 4'b0010;
else //CAS Latency = 4.0
if (a[6 : 4] == 3'b100)
tcl <= 4'b0011;
else //CAS Latency = 5.0
if (a[6 : 4] == 3'b101)
tcl <= 4'b0100;
else //CAS Latency = 6.0
if (a[6 : 4] == 3'b110)
tcl <= 4'b0101;
else
tcl <= 4'b0110;
end
else //Get additive latency
if (cmd_code == 3'b000 && ba == 2'b01)
additive_latency <= {1'b0,a[5 : 3]};
end
//Calculate actual write and read latency
always @(additive_latency or tcl)
begin
read_latency = tcl + additive_latency;
write_latency = tcl + additive_latency;
end
// Burst support - make the wr_addr & rd_addr keep counting
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
wr_addr_pipe_0 <= 0;
rd_addr_pipe_0 <= 0;
end
else
begin
// Reset write address otherwise if the first write is partial it breaks!
if (cmd_code == 3'b000 && ba == 2'b00)
begin
wr_addr_pipe_0 <= 0;
wr_burst_counter <= 0;
end
else if (cmd_code == 3'b100)
begin
wr_addr_pipe_0 <= {ba,open_rows[current_row],addr_col};
wr_burst_counter[24 : 2] <= {ba,open_rows[current_row],addr_col[8 : 2]};
wr_burst_counter[1 : 0] <= addr_col[1 : 0] + 1;
end
else if (write_cmd || write_to_ram || write_cmd_echo)
begin
wr_addr_pipe_0 <= wr_burst_counter;
wr_burst_counter[1 : 0] <= wr_burst_counter[1 : 0] + 1;
end
else
wr_addr_pipe_0 <= 0;
// Reset read address otherwise if the first write is partial it breaks!
if (cmd_code == 3'b000 && ba == 2'b00)
rd_addr_pipe_0 <= 0;
else if (cmd_code == 3'b101)
begin
rd_addr_pipe_0 <= {ba,open_rows[current_row],addr_col};
rd_burst_counter[24 : 2] <= {ba,open_rows[current_row],addr_col[8 : 2]};
rd_burst_counter[1 : 0] <= addr_col[1 : 0] + 1;
end
else if (read_cmd || dq_valid || read_valid || read_cmd_echo)
begin
rd_addr_pipe_0 <= rd_burst_counter;
rd_burst_counter[1 : 0] <= rd_burst_counter[1 : 0] + 1;
end
else
rd_addr_pipe_0 <= 0;
end
end
// read data transition from single to double clock rate
always @(posedge clk)
begin
first_half_dq <= read_data[31 : 16];
second_half_dq <= read_data[15 : 0];
end
assign read_dq = clk ? second_half_dq : first_half_dq;
assign dq_temp = dq_valid ? read_dq : {16{1'bz}};
assign dqs_temp = dqs_valid ? {2{clk}} : {2{1'bz}};
assign mem_dqs = dqs_temp;
assign mem_dq = dq_temp;
//Pipelining registers for burst counting
always @(posedge clk)
begin
write_valid_r <= write_valid;
read_valid_r <= read_valid;
write_valid_r2 <= write_valid_r;
write_valid_r3 <= write_valid_r2;
write_to_ram_r <= write_to_ram;
read_valid_r2 <= read_valid_r;
read_valid_r3 <= read_valid_r2;
read_valid_r4 <= read_valid_r3;
end
assign write_to_ram = burstlength[1] ? write_valid || write_valid_r || write_valid_r2 || write_valid_r3 : write_valid || write_valid_r;
assign dq_valid = burstlength[1] ? read_valid_r || read_valid_r2 || read_valid_r3 || read_valid_r4 : read_valid_r || read_valid_r2;
assign dqs_valid = dq_valid || dqs_valid_temp;
//
always @(negedge clk)
begin
dqs_valid_temp <= read_valid;
end
//capture first half of write data with rising edge of DQS, for simulation use only 1 DQS pin
always @(posedge mem_dqs[0])
begin
#0.1 dq_captured[15 : 0] <= mem_dq[15 : 0];
#0.1 dm_captured[1 : 0] <= mem_dm[1 : 0];
end
//capture second half of write data with falling edge of DQS, for simulation use only 1 DQS pin
always @(negedge mem_dqs[0])
begin
#0.1 dq_captured[31 : 16] <= mem_dq[15 : 0];
#0.1 dm_captured[3 : 2] <= mem_dm[1 : 0];
end
//Support for incomplete writes, do a read-modify-write with mem_bytes and the write data
always @(posedge clk)
begin
if (write_to_ram)
rmw_temp[7 : 0] <= dm_captured[0] ? mem_bytes[7 : 0] : dq_captured[7 : 0];
end
always @(posedge clk)
begin
if (write_to_ram)
rmw_temp[15 : 8] <= dm_captured[1] ? mem_bytes[15 : 8] : dq_captured[15 : 8];
end
always @(posedge clk)
begin
if (write_to_ram)
rmw_temp[23 : 16] <= dm_captured[2] ? mem_bytes[23 : 16] : dq_captured[23 : 16];
end
always @(posedge clk)
begin
if (write_to_ram)
rmw_temp[31 : 24] <= dm_captured[3] ? mem_bytes[31 : 24] : dq_captured[31 : 24];
end
//DDR2 has variable write latency too, so use write_latency to select which pipeline stage drives valid
assign write_valid = (write_latency == 0)? wr_valid_pipe[0] :
(write_latency == 1)? wr_valid_pipe[1] :
(write_latency == 2)? wr_valid_pipe[2] :
(write_latency == 3)? wr_valid_pipe[3] :
(write_latency == 4)? wr_valid_pipe[4] :
(write_latency == 5)? wr_valid_pipe[5] :
(write_latency == 6)? wr_valid_pipe[6] :
(write_latency == 7)? wr_valid_pipe[7] :
(write_latency == 8)? wr_valid_pipe[8] :
(write_latency == 9)? wr_valid_pipe[9] :
(write_latency == 10)? wr_valid_pipe[10] :
(write_latency == 11)? wr_valid_pipe[11] :
(write_latency == 12)? wr_valid_pipe[12] :
(write_latency == 13)? wr_valid_pipe[13] :
(write_latency == 14)? wr_valid_pipe[14] :
(write_latency == 15)? wr_valid_pipe[15] :
(write_latency == 16)? wr_valid_pipe[16] :
(write_latency == 17)? wr_valid_pipe[17] :
wr_valid_pipe[18];
//DDR2 has variable write latency too, so use write_latency to select which pipeline stage drives addr
assign wr_addr_delayed = (write_latency == 0)? wr_addr_pipe_0 :
(write_latency == 1)? wr_addr_pipe_1 :
(write_latency == 2)? wr_addr_pipe_2 :
(write_latency == 3)? wr_addr_pipe_3 :
(write_latency == 4)? wr_addr_pipe_4 :
(write_latency == 5)? wr_addr_pipe_5 :
(write_latency == 6)? wr_addr_pipe_6 :
(write_latency == 7)? wr_addr_pipe_7 :
(write_latency == 8)? wr_addr_pipe_8 :
(write_latency == 9)? wr_addr_pipe_9 :
(write_latency == 10)? wr_addr_pipe_10 :
(write_latency == 11)? wr_addr_pipe_11 :
(write_latency == 12)? wr_addr_pipe_12 :
(write_latency == 13)? wr_addr_pipe_13 :
(write_latency == 14)? wr_addr_pipe_14 :
(write_latency == 15)? wr_addr_pipe_15 :
(write_latency == 16)? wr_addr_pipe_16 :
(write_latency == 17)? wr_addr_pipe_17 :
wr_addr_pipe_18;
assign mem_bytes = (rmw_address == wr_addr_delayed_r && write_to_ram_r) ? rmw_temp : read_data;
assign rmw_address = (write_to_ram) ? wr_addr_delayed : read_addr_delayed;
//use read_latency to select which pipeline stage drives addr
assign read_addr_delayed = (read_latency == 0)? rd_addr_pipe_0 :
(read_latency == 1)? rd_addr_pipe_1 :
(read_latency == 2)? rd_addr_pipe_2 :
(read_latency == 3)? rd_addr_pipe_3 :
(read_latency == 4)? rd_addr_pipe_4 :
(read_latency == 5)? rd_addr_pipe_5 :
(read_latency == 6)? rd_addr_pipe_6 :
(read_latency == 7)? rd_addr_pipe_7 :
(read_latency == 8)? rd_addr_pipe_8 :
(read_latency == 9)? rd_addr_pipe_9 :
(read_latency == 10)? rd_addr_pipe_10 :
(read_latency == 11)? rd_addr_pipe_11 :
(read_latency == 12)? rd_addr_pipe_12 :
(read_latency == 13)? rd_addr_pipe_13 :
(read_latency == 14)? rd_addr_pipe_14 :
(read_latency == 15)? rd_addr_pipe_15 :
(read_latency == 16)? rd_addr_pipe_16 :
(read_latency == 17)? rd_addr_pipe_17 :
(read_latency == 18)? rd_addr_pipe_18 :
(read_latency == 19)? rd_addr_pipe_19 :
(read_latency == 20)? rd_addr_pipe_20 :
rd_addr_pipe_21;
//use read_latency to select which pipeline stage drives valid
assign read_valid = (read_latency == 0)? rd_valid_pipe[0] :
(read_latency == 1)? rd_valid_pipe[1] :
(read_latency == 2)? rd_valid_pipe[2] :
(read_latency == 3)? rd_valid_pipe[3] :
(read_latency == 4)? rd_valid_pipe[4] :
(read_latency == 5)? rd_valid_pipe[5] :
(read_latency == 6)? rd_valid_pipe[6] :
(read_latency == 7)? rd_valid_pipe[7] :
(read_latency == 8)? rd_valid_pipe[8] :
(read_latency == 9)? rd_valid_pipe[9] :
(read_latency == 10)? rd_valid_pipe[10] :
(read_latency == 11)? rd_valid_pipe[11] :
(read_latency == 12)? rd_valid_pipe[12] :
(read_latency == 13)? rd_valid_pipe[13] :
(read_latency == 14)? rd_valid_pipe[14] :
(read_latency == 15)? rd_valid_pipe[15] :
(read_latency == 16)? rd_valid_pipe[16] :
(read_latency == 17)? rd_valid_pipe[17] :
(read_latency == 18)? rd_valid_pipe[18] :
(read_latency == 19)? rd_valid_pipe[19] :
(read_latency == 20)? rd_valid_pipe[20] :
rd_valid_pipe[21];
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign txt_code = (cmd_code == 3'h0)? 24'h4c4d52 :
(cmd_code == 3'h1)? 24'h415246 :
(cmd_code == 3'h2)? 24'h505245 :
(cmd_code == 3'h3)? 24'h414354 :
(cmd_code == 3'h4)? 24'h205752 :
(cmd_code == 3'h5)? 24'h205244 :
(cmd_code == 3'h6)? 24'h425354 :
(cmd_code == 3'h7)? 24'h4e4f50 :
24'h424144;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module Loop_loop_height_pro (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
p_rows_assign_cast_loc_dout,
p_rows_assign_cast_loc_empty_n,
p_rows_assign_cast_loc_read,
p_cols_assign_cast_loc_dout,
p_cols_assign_cast_loc_empty_n,
p_cols_assign_cast_loc_read,
img3_data_stream_0_V_din,
img3_data_stream_0_V_full_n,
img3_data_stream_0_V_write,
img3_data_stream_1_V_din,
img3_data_stream_1_V_full_n,
img3_data_stream_1_V_write,
img3_data_stream_2_V_din,
img3_data_stream_2_V_full_n,
img3_data_stream_2_V_write,
gamma_dout,
gamma_empty_n,
gamma_read,
img0_data_stream_0_V_dout,
img0_data_stream_0_V_empty_n,
img0_data_stream_0_V_read,
img0_data_stream_1_V_dout,
img0_data_stream_1_V_empty_n,
img0_data_stream_1_V_read,
img0_data_stream_2_V_dout,
img0_data_stream_2_V_empty_n,
img0_data_stream_2_V_read
);
parameter ap_ST_fsm_state1 = 5'd1;
parameter ap_ST_fsm_state2 = 5'd2;
parameter ap_ST_fsm_state3 = 5'd4;
parameter ap_ST_fsm_pp0_stage0 = 5'd8;
parameter ap_ST_fsm_state9 = 5'd16;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [11:0] p_rows_assign_cast_loc_dout;
input p_rows_assign_cast_loc_empty_n;
output p_rows_assign_cast_loc_read;
input [11:0] p_cols_assign_cast_loc_dout;
input p_cols_assign_cast_loc_empty_n;
output p_cols_assign_cast_loc_read;
output [7:0] img3_data_stream_0_V_din;
input img3_data_stream_0_V_full_n;
output img3_data_stream_0_V_write;
output [7:0] img3_data_stream_1_V_din;
input img3_data_stream_1_V_full_n;
output img3_data_stream_1_V_write;
output [7:0] img3_data_stream_2_V_din;
input img3_data_stream_2_V_full_n;
output img3_data_stream_2_V_write;
input [7:0] gamma_dout;
input gamma_empty_n;
output gamma_read;
input [7:0] img0_data_stream_0_V_dout;
input img0_data_stream_0_V_empty_n;
output img0_data_stream_0_V_read;
input [7:0] img0_data_stream_1_V_dout;
input img0_data_stream_1_V_empty_n;
output img0_data_stream_1_V_read;
input [7:0] img0_data_stream_2_V_dout;
input img0_data_stream_2_V_empty_n;
output img0_data_stream_2_V_read;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg p_rows_assign_cast_loc_read;
reg p_cols_assign_cast_loc_read;
reg img3_data_stream_0_V_write;
reg img3_data_stream_1_V_write;
reg img3_data_stream_2_V_write;
reg gamma_read;
reg img0_data_stream_0_V_read;
reg img0_data_stream_1_V_read;
reg img0_data_stream_2_V_read;
reg ap_done_reg;
(* fsm_encoding = "none" *) reg [4:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
wire [7:0] lut2_2_address0;
reg lut2_2_ce0;
wire [7:0] lut2_2_q0;
wire [7:0] lut2_2_address1;
reg lut2_2_ce1;
wire [7:0] lut2_2_q1;
wire [7:0] lut2_2_address2;
reg lut2_2_ce2;
wire [7:0] lut2_2_q2;
wire [7:0] lut0_4_address0;
reg lut0_4_ce0;
wire [7:0] lut0_4_q0;
wire [7:0] lut0_4_address1;
reg lut0_4_ce1;
wire [7:0] lut0_4_q1;
wire [7:0] lut0_4_address2;
reg lut0_4_ce2;
wire [7:0] lut0_4_q2;
wire [7:0] lut0_2_address0;
reg lut0_2_ce0;
wire [7:0] lut0_2_q0;
wire [7:0] lut0_2_address1;
reg lut0_2_ce1;
wire [7:0] lut0_2_q1;
wire [7:0] lut0_2_address2;
reg lut0_2_ce2;
wire [7:0] lut0_2_q2;
wire [7:0] lut1_2_address0;
reg lut1_2_ce0;
wire [7:0] lut1_2_q0;
wire [7:0] lut1_2_address1;
reg lut1_2_ce1;
wire [7:0] lut1_2_q1;
wire [7:0] lut1_2_address2;
reg lut1_2_ce2;
wire [7:0] lut1_2_q2;
wire [7:0] lut1_4_address0;
reg lut1_4_ce0;
wire [7:0] lut1_4_q0;
wire [7:0] lut1_4_address1;
reg lut1_4_ce1;
wire [7:0] lut1_4_q1;
wire [7:0] lut1_4_address2;
reg lut1_4_ce2;
wire [7:0] lut1_4_q2;
wire [7:0] lut1_6_address0;
reg lut1_6_ce0;
wire [7:0] lut1_6_q0;
wire [7:0] lut1_6_address1;
reg lut1_6_ce1;
wire [7:0] lut1_6_q1;
wire [7:0] lut1_6_address2;
reg lut1_6_ce2;
wire [7:0] lut1_6_q2;
wire [7:0] lut1_8_address0;
reg lut1_8_ce0;
wire [7:0] lut1_8_q0;
wire [7:0] lut1_8_address1;
reg lut1_8_ce1;
wire [7:0] lut1_8_q1;
wire [7:0] lut1_8_address2;
reg lut1_8_ce2;
wire [7:0] lut1_8_q2;
wire [7:0] lut2_0_address0;
reg lut2_0_ce0;
wire [7:0] lut2_0_q0;
wire [7:0] lut2_0_address1;
reg lut2_0_ce1;
wire [7:0] lut2_0_q1;
wire [7:0] lut2_0_address2;
reg lut2_0_ce2;
wire [7:0] lut2_0_q2;
reg p_rows_assign_cast_loc_blk_n;
reg p_cols_assign_cast_loc_blk_n;
reg img3_data_stream_0_V_blk_n;
reg ap_enable_reg_pp0_iter4;
wire ap_block_pp0_stage0;
reg [0:0] exitcond_i_i_i_reg_837;
reg [0:0] ap_reg_pp0_iter3_exitcond_i_i_i_reg_837;
reg img3_data_stream_1_V_blk_n;
reg img3_data_stream_2_V_blk_n;
reg gamma_blk_n;
reg img0_data_stream_0_V_blk_n;
wire ap_CS_fsm_pp0_stage0;
reg ap_enable_reg_pp0_iter1;
reg img0_data_stream_1_V_blk_n;
reg img0_data_stream_2_V_blk_n;
reg [10:0] t_V_2_reg_444;
reg [7:0] gamma_read_reg_750;
reg ap_block_state1;
reg [11:0] p_rows_assign_cast_lo_reg_762;
reg [11:0] p_cols_assign_cast_lo_reg_767;
wire [0:0] sel_tmp2_fu_460_p2;
reg [0:0] sel_tmp2_reg_772;
wire ap_CS_fsm_state2;
wire [0:0] sel_tmp6_fu_470_p2;
reg [0:0] sel_tmp6_reg_779;
wire [0:0] sel_tmp1_fu_480_p2;
reg [0:0] sel_tmp1_reg_786;
wire [0:0] sel_tmp5_fu_490_p2;
reg [0:0] sel_tmp5_reg_793;
wire [0:0] or_cond_fu_495_p2;
reg [0:0] or_cond_reg_800;
wire [0:0] or_cond2_fu_507_p2;
reg [0:0] or_cond2_reg_807;
wire [0:0] or_cond4_fu_519_p2;
reg [0:0] or_cond4_reg_814;
wire [0:0] or_cond6_fu_531_p2;
reg [0:0] or_cond6_reg_821;
wire [0:0] exitcond161_i_i_i_fu_541_p2;
wire ap_CS_fsm_state3;
wire [10:0] i_V_fu_546_p2;
reg [10:0] i_V_reg_832;
wire [0:0] exitcond_i_i_i_fu_556_p2;
wire ap_block_state4_pp0_stage0_iter0;
reg ap_block_state5_pp0_stage0_iter1;
wire ap_block_state6_pp0_stage0_iter2;
wire ap_block_state7_pp0_stage0_iter3;
reg ap_block_state8_pp0_stage0_iter4;
reg ap_block_pp0_stage0_11001;
reg [0:0] ap_reg_pp0_iter1_exitcond_i_i_i_reg_837;
reg [0:0] ap_reg_pp0_iter2_exitcond_i_i_i_reg_837;
wire [10:0] j_V_fu_561_p2;
reg ap_enable_reg_pp0_iter0;
reg [7:0] tmp_9_reg_846;
reg [7:0] ap_reg_pp0_iter2_tmp_9_reg_846;
reg [7:0] ap_reg_pp0_iter3_tmp_9_reg_846;
reg [7:0] tmp_10_reg_852;
reg [7:0] ap_reg_pp0_iter2_tmp_10_reg_852;
reg [7:0] ap_reg_pp0_iter3_tmp_10_reg_852;
reg [7:0] tmp_11_reg_858;
reg [7:0] ap_reg_pp0_iter2_tmp_11_reg_858;
reg [7:0] ap_reg_pp0_iter3_tmp_11_reg_858;
reg [7:0] d_val_0_2_reg_984;
reg ap_enable_reg_pp0_iter3;
reg [7:0] d_val_0_3_reg_989;
reg [7:0] d_val_0_6_reg_994;
reg [7:0] d_val_0_7_reg_999;
wire [7:0] newSel1_fu_600_p3;
reg [7:0] newSel1_reg_1004;
wire [7:0] newSel3_fu_607_p3;
reg [7:0] newSel3_reg_1009;
reg [7:0] d_val_1_2_reg_1014;
reg [7:0] d_val_1_3_reg_1019;
reg [7:0] d_val_1_6_reg_1024;
reg [7:0] d_val_1_7_reg_1029;
wire [7:0] newSel9_fu_614_p3;
reg [7:0] newSel9_reg_1034;
wire [7:0] newSel10_fu_621_p3;
reg [7:0] newSel10_reg_1039;
reg [7:0] d_val_2_2_reg_1044;
reg [7:0] d_val_2_3_reg_1049;
reg [7:0] d_val_2_6_reg_1054;
reg [7:0] d_val_2_7_reg_1059;
wire [7:0] newSel15_fu_628_p3;
reg [7:0] newSel15_reg_1064;
wire [7:0] newSel17_fu_635_p3;
reg [7:0] newSel17_reg_1069;
reg ap_block_pp0_stage0_subdone;
reg ap_condition_pp0_exit_iter0_state4;
reg ap_enable_reg_pp0_iter2;
reg [10:0] t_V_reg_433;
wire ap_CS_fsm_state9;
wire [63:0] tmp_26_i_i_fu_567_p1;
wire [63:0] tmp_26_1_i_i_fu_578_p1;
wire [63:0] tmp_26_2_i_i_fu_589_p1;
reg ap_block_pp0_stage0_01001;
wire [0:0] sel_tmp3_fu_485_p2;
wire [0:0] sel_tmp8_fu_475_p2;
wire [0:0] sel_tmp4_fu_465_p2;
wire [0:0] sel_tmp_fu_455_p2;
wire [0:0] or_cond1_fu_501_p2;
wire [0:0] or_cond3_fu_513_p2;
wire [0:0] or_cond5_fu_525_p2;
wire [11:0] t_V_cast_i_i_fu_537_p1;
wire [11:0] t_V_1_cast_i_i_fu_552_p1;
wire [7:0] newSel_fu_642_p3;
wire [7:0] newSel2_fu_647_p3;
wire [7:0] newSel4_fu_652_p3;
wire [7:0] newSel5_fu_658_p3;
wire [7:0] newSel6_fu_664_p3;
wire [7:0] newSel8_fu_678_p3;
wire [7:0] newSel7_fu_683_p3;
wire [7:0] newSel11_fu_688_p3;
wire [7:0] newSel12_fu_694_p3;
wire [7:0] newSel13_fu_700_p3;
wire [7:0] newSel14_fu_714_p3;
wire [7:0] newSel16_fu_719_p3;
wire [7:0] newSel18_fu_724_p3;
wire [7:0] newSel19_fu_730_p3;
wire [7:0] newSel20_fu_736_p3;
reg [4:0] ap_NS_fsm;
reg ap_idle_pp0;
wire ap_enable_pp0;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 5'd1;
#0 ap_enable_reg_pp0_iter4 = 1'b0;
#0 ap_enable_reg_pp0_iter1 = 1'b0;
#0 ap_enable_reg_pp0_iter0 = 1'b0;
#0 ap_enable_reg_pp0_iter3 = 1'b0;
#0 ap_enable_reg_pp0_iter2 = 1'b0;
end
Loop_loop_height_bkb #(
.DataWidth( 8 ),
.AddressRange( 256 ),
.AddressWidth( 8 ))
lut2_2_U(
.clk(ap_clk),
.reset(ap_rst),
.address0(lut2_2_address0),
.ce0(lut2_2_ce0),
.q0(lut2_2_q0),
.address1(lut2_2_address1),
.ce1(lut2_2_ce1),
.q1(lut2_2_q1),
.address2(lut2_2_address2),
.ce2(lut2_2_ce2),
.q2(lut2_2_q2)
);
Loop_loop_height_cud #(
.DataWidth( 8 ),
.AddressRange( 256 ),
.AddressWidth( 8 ))
lut0_4_U(
.clk(ap_clk),
.reset(ap_rst),
.address0(lut0_4_address0),
.ce0(lut0_4_ce0),
.q0(lut0_4_q0),
.address1(lut0_4_address1),
.ce1(lut0_4_ce1),
.q1(lut0_4_q1),
.address2(lut0_4_address2),
.ce2(lut0_4_ce2),
.q2(lut0_4_q2)
);
Loop_loop_height_dEe #(
.DataWidth( 8 ),
.AddressRange( 256 ),
.AddressWidth( 8 ))
lut0_2_U(
.clk(ap_clk),
.reset(ap_rst),
.address0(lut0_2_address0),
.ce0(lut0_2_ce0),
.q0(lut0_2_q0),
.address1(lut0_2_address1),
.ce1(lut0_2_ce1),
.q1(lut0_2_q1),
.address2(lut0_2_address2),
.ce2(lut0_2_ce2),
.q2(lut0_2_q2)
);
Loop_loop_height_eOg #(
.DataWidth( 8 ),
.AddressRange( 256 ),
.AddressWidth( 8 ))
lut1_2_U(
.clk(ap_clk),
.reset(ap_rst),
.address0(lut1_2_address0),
.ce0(lut1_2_ce0),
.q0(lut1_2_q0),
.address1(lut1_2_address1),
.ce1(lut1_2_ce1),
.q1(lut1_2_q1),
.address2(lut1_2_address2),
.ce2(lut1_2_ce2),
.q2(lut1_2_q2)
);
Loop_loop_height_fYi #(
.DataWidth( 8 ),
.AddressRange( 256 ),
.AddressWidth( 8 ))
lut1_4_U(
.clk(ap_clk),
.reset(ap_rst),
.address0(lut1_4_address0),
.ce0(lut1_4_ce0),
.q0(lut1_4_q0),
.address1(lut1_4_address1),
.ce1(lut1_4_ce1),
.q1(lut1_4_q1),
.address2(lut1_4_address2),
.ce2(lut1_4_ce2),
.q2(lut1_4_q2)
);
Loop_loop_height_g8j #(
.DataWidth( 8 ),
.AddressRange( 256 ),
.AddressWidth( 8 ))
lut1_6_U(
.clk(ap_clk),
.reset(ap_rst),
.address0(lut1_6_address0),
.ce0(lut1_6_ce0),
.q0(lut1_6_q0),
.address1(lut1_6_address1),
.ce1(lut1_6_ce1),
.q1(lut1_6_q1),
.address2(lut1_6_address2),
.ce2(lut1_6_ce2),
.q2(lut1_6_q2)
);
Loop_loop_height_hbi #(
.DataWidth( 8 ),
.AddressRange( 256 ),
.AddressWidth( 8 ))
lut1_8_U(
.clk(ap_clk),
.reset(ap_rst),
.address0(lut1_8_address0),
.ce0(lut1_8_ce0),
.q0(lut1_8_q0),
.address1(lut1_8_address1),
.ce1(lut1_8_ce1),
.q1(lut1_8_q1),
.address2(lut1_8_address2),
.ce2(lut1_8_ce2),
.q2(lut1_8_q2)
);
Loop_loop_height_ibs #(
.DataWidth( 8 ),
.AddressRange( 256 ),
.AddressWidth( 8 ))
lut2_0_U(
.clk(ap_clk),
.reset(ap_rst),
.address0(lut2_0_address0),
.ce0(lut2_0_ce0),
.q0(lut2_0_q0),
.address1(lut2_0_address1),
.ce1(lut2_0_ce1),
.q1(lut2_0_q1),
.address2(lut2_0_address2),
.ce2(lut2_0_ce2),
.q2(lut2_0_q2)
);
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if (((exitcond161_i_i_i_fu_541_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin
ap_done_reg <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter0 <= 1'b0;
end else begin
if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state4) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
ap_enable_reg_pp0_iter0 <= 1'b0;
end else if (((1'b1 == ap_CS_fsm_state3) & (exitcond161_i_i_i_fu_541_p2 == 1'd0))) begin
ap_enable_reg_pp0_iter0 <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter1 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
if ((1'b1 == ap_condition_pp0_exit_iter0_state4)) begin
ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state4);
end else if ((1'b1 == 1'b1)) begin
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter2 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter3 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter4 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end else if (((1'b1 == ap_CS_fsm_state3) & (exitcond161_i_i_i_fu_541_p2 == 1'd0))) begin
ap_enable_reg_pp0_iter4 <= 1'b0;
end
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (exitcond_i_i_i_fu_556_p2 == 1'd0))) begin
t_V_2_reg_444 <= j_V_fu_561_p2;
end else if (((1'b1 == ap_CS_fsm_state3) & (exitcond161_i_i_i_fu_541_p2 == 1'd0))) begin
t_V_2_reg_444 <= 11'd0;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state9)) begin
t_V_reg_433 <= i_V_reg_832;
end else if ((1'b1 == ap_CS_fsm_state2)) begin
t_V_reg_433 <= 11'd0;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
ap_reg_pp0_iter1_exitcond_i_i_i_reg_837 <= exitcond_i_i_i_reg_837;
exitcond_i_i_i_reg_837 <= exitcond_i_i_i_fu_556_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b0 == ap_block_pp0_stage0_11001)) begin
ap_reg_pp0_iter2_exitcond_i_i_i_reg_837 <= ap_reg_pp0_iter1_exitcond_i_i_i_reg_837;
ap_reg_pp0_iter2_tmp_10_reg_852 <= tmp_10_reg_852;
ap_reg_pp0_iter2_tmp_11_reg_858 <= tmp_11_reg_858;
ap_reg_pp0_iter2_tmp_9_reg_846 <= tmp_9_reg_846;
ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 <= ap_reg_pp0_iter2_exitcond_i_i_i_reg_837;
ap_reg_pp0_iter3_tmp_10_reg_852 <= ap_reg_pp0_iter2_tmp_10_reg_852;
ap_reg_pp0_iter3_tmp_11_reg_858 <= ap_reg_pp0_iter2_tmp_11_reg_858;
ap_reg_pp0_iter3_tmp_9_reg_846 <= ap_reg_pp0_iter2_tmp_9_reg_846;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (or_cond6_reg_821 == 1'd1) & (or_cond4_reg_814 == 1'd1) & (or_cond_reg_800 == 1'd1) & (sel_tmp5_reg_793 == 1'd1) & (ap_enable_reg_pp0_iter3 == 1'b1) & (ap_reg_pp0_iter2_exitcond_i_i_i_reg_837 == 1'd0))) begin
d_val_0_2_reg_984 <= lut0_4_q0;
d_val_1_2_reg_1014 <= lut0_4_q1;
d_val_2_2_reg_1044 <= lut0_4_q2;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (or_cond6_reg_821 == 1'd1) & (or_cond4_reg_814 == 1'd1) & (or_cond_reg_800 == 1'd1) & (ap_enable_reg_pp0_iter3 == 1'b1) & (ap_reg_pp0_iter2_exitcond_i_i_i_reg_837 == 1'd0) & (sel_tmp5_reg_793 == 1'd0))) begin
d_val_0_3_reg_989 <= lut0_2_q0;
d_val_1_3_reg_1019 <= lut0_2_q1;
d_val_2_3_reg_1049 <= lut0_2_q2;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (or_cond6_reg_821 == 1'd1) & (or_cond2_reg_807 == 1'd1) & (sel_tmp6_reg_779 == 1'd1) & (ap_enable_reg_pp0_iter3 == 1'b1) & (ap_reg_pp0_iter2_exitcond_i_i_i_reg_837 == 1'd0) & (or_cond4_reg_814 == 1'd0))) begin
d_val_0_6_reg_994 <= lut1_6_q0;
d_val_1_6_reg_1024 <= lut1_6_q1;
d_val_2_6_reg_1054 <= lut1_6_q2;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (or_cond6_reg_821 == 1'd1) & (or_cond2_reg_807 == 1'd1) & (ap_enable_reg_pp0_iter3 == 1'b1) & (ap_reg_pp0_iter2_exitcond_i_i_i_reg_837 == 1'd0) & (or_cond4_reg_814 == 1'd0) & (sel_tmp6_reg_779 == 1'd0))) begin
d_val_0_7_reg_999 <= lut1_8_q0;
d_val_1_7_reg_1029 <= lut1_8_q1;
d_val_2_7_reg_1059 <= lut1_8_q2;
end
end
always @ (posedge ap_clk) begin
if ((~((gamma_empty_n == 1'b0) | (p_cols_assign_cast_loc_empty_n == 1'b0) | (p_rows_assign_cast_loc_empty_n == 1'b0) | (ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
gamma_read_reg_750 <= gamma_dout;
p_cols_assign_cast_lo_reg_767 <= p_cols_assign_cast_loc_dout;
p_rows_assign_cast_lo_reg_762 <= p_rows_assign_cast_loc_dout;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
i_V_reg_832 <= i_V_fu_546_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (or_cond6_reg_821 == 1'd1) & (ap_reg_pp0_iter2_exitcond_i_i_i_reg_837 == 1'd0) & (or_cond4_reg_814 == 1'd0) & (or_cond2_reg_807 == 1'd0))) begin
newSel10_reg_1039 <= newSel10_fu_621_p3;
newSel17_reg_1069 <= newSel17_fu_635_p3;
newSel3_reg_1009 <= newSel3_fu_607_p3;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (or_cond6_reg_821 == 1'd1) & (or_cond4_reg_814 == 1'd1) & (ap_reg_pp0_iter2_exitcond_i_i_i_reg_837 == 1'd0) & (or_cond_reg_800 == 1'd0))) begin
newSel15_reg_1064 <= newSel15_fu_628_p3;
newSel1_reg_1004 <= newSel1_fu_600_p3;
newSel9_reg_1034 <= newSel9_fu_614_p3;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state2)) begin
or_cond2_reg_807 <= or_cond2_fu_507_p2;
or_cond4_reg_814 <= or_cond4_fu_519_p2;
or_cond6_reg_821 <= or_cond6_fu_531_p2;
or_cond_reg_800 <= or_cond_fu_495_p2;
sel_tmp1_reg_786 <= sel_tmp1_fu_480_p2;
sel_tmp2_reg_772 <= sel_tmp2_fu_460_p2;
sel_tmp5_reg_793 <= sel_tmp5_fu_490_p2;
sel_tmp6_reg_779 <= sel_tmp6_fu_470_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (exitcond_i_i_i_reg_837 == 1'd0))) begin
tmp_10_reg_852 <= img0_data_stream_1_V_dout;
tmp_11_reg_858 <= img0_data_stream_2_V_dout;
tmp_9_reg_846 <= img0_data_stream_0_V_dout;
end
end
always @ (*) begin
if ((exitcond_i_i_i_fu_556_p2 == 1'd1)) begin
ap_condition_pp0_exit_iter0_state4 = 1'b1;
end else begin
ap_condition_pp0_exit_iter0_state4 = 1'b0;
end
end
always @ (*) begin
if (((exitcond161_i_i_i_fu_541_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @ (*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0))) begin
ap_idle_pp0 = 1'b1;
end else begin
ap_idle_pp0 = 1'b0;
end
end
always @ (*) begin
if (((exitcond161_i_i_i_fu_541_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
gamma_blk_n = gamma_empty_n;
end else begin
gamma_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((gamma_empty_n == 1'b0) | (p_cols_assign_cast_loc_empty_n == 1'b0) | (p_rows_assign_cast_loc_empty_n == 1'b0) | (ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
gamma_read = 1'b1;
end else begin
gamma_read = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (exitcond_i_i_i_reg_837 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin
img0_data_stream_0_V_blk_n = img0_data_stream_0_V_empty_n;
end else begin
img0_data_stream_0_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (exitcond_i_i_i_reg_837 == 1'd0))) begin
img0_data_stream_0_V_read = 1'b1;
end else begin
img0_data_stream_0_V_read = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (exitcond_i_i_i_reg_837 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin
img0_data_stream_1_V_blk_n = img0_data_stream_1_V_empty_n;
end else begin
img0_data_stream_1_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (exitcond_i_i_i_reg_837 == 1'd0))) begin
img0_data_stream_1_V_read = 1'b1;
end else begin
img0_data_stream_1_V_read = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (exitcond_i_i_i_reg_837 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin
img0_data_stream_2_V_blk_n = img0_data_stream_2_V_empty_n;
end else begin
img0_data_stream_2_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (exitcond_i_i_i_reg_837 == 1'd0))) begin
img0_data_stream_2_V_read = 1'b1;
end else begin
img0_data_stream_2_V_read = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter4 == 1'b1) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin
img3_data_stream_0_V_blk_n = img3_data_stream_0_V_full_n;
end else begin
img3_data_stream_0_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 == 1'd0))) begin
img3_data_stream_0_V_write = 1'b1;
end else begin
img3_data_stream_0_V_write = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter4 == 1'b1) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin
img3_data_stream_1_V_blk_n = img3_data_stream_1_V_full_n;
end else begin
img3_data_stream_1_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 == 1'd0))) begin
img3_data_stream_1_V_write = 1'b1;
end else begin
img3_data_stream_1_V_write = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter4 == 1'b1) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin
img3_data_stream_2_V_blk_n = img3_data_stream_2_V_full_n;
end else begin
img3_data_stream_2_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 == 1'd0))) begin
img3_data_stream_2_V_write = 1'b1;
end else begin
img3_data_stream_2_V_write = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut0_2_ce0 = 1'b1;
end else begin
lut0_2_ce0 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut0_2_ce1 = 1'b1;
end else begin
lut0_2_ce1 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut0_2_ce2 = 1'b1;
end else begin
lut0_2_ce2 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut0_4_ce0 = 1'b1;
end else begin
lut0_4_ce0 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut0_4_ce1 = 1'b1;
end else begin
lut0_4_ce1 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut0_4_ce2 = 1'b1;
end else begin
lut0_4_ce2 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut1_2_ce0 = 1'b1;
end else begin
lut1_2_ce0 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut1_2_ce1 = 1'b1;
end else begin
lut1_2_ce1 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut1_2_ce2 = 1'b1;
end else begin
lut1_2_ce2 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut1_4_ce0 = 1'b1;
end else begin
lut1_4_ce0 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut1_4_ce1 = 1'b1;
end else begin
lut1_4_ce1 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut1_4_ce2 = 1'b1;
end else begin
lut1_4_ce2 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut1_6_ce0 = 1'b1;
end else begin
lut1_6_ce0 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut1_6_ce1 = 1'b1;
end else begin
lut1_6_ce1 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut1_6_ce2 = 1'b1;
end else begin
lut1_6_ce2 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut1_8_ce0 = 1'b1;
end else begin
lut1_8_ce0 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut1_8_ce1 = 1'b1;
end else begin
lut1_8_ce1 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut1_8_ce2 = 1'b1;
end else begin
lut1_8_ce2 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut2_0_ce0 = 1'b1;
end else begin
lut2_0_ce0 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut2_0_ce1 = 1'b1;
end else begin
lut2_0_ce1 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut2_0_ce2 = 1'b1;
end else begin
lut2_0_ce2 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut2_2_ce0 = 1'b1;
end else begin
lut2_2_ce0 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut2_2_ce1 = 1'b1;
end else begin
lut2_2_ce1 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut2_2_ce2 = 1'b1;
end else begin
lut2_2_ce2 = 1'b0;
end
end
always @ (*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_cols_assign_cast_loc_blk_n = p_cols_assign_cast_loc_empty_n;
end else begin
p_cols_assign_cast_loc_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((gamma_empty_n == 1'b0) | (p_cols_assign_cast_loc_empty_n == 1'b0) | (p_rows_assign_cast_loc_empty_n == 1'b0) | (ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_cols_assign_cast_loc_read = 1'b1;
end else begin
p_cols_assign_cast_loc_read = 1'b0;
end
end
always @ (*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_rows_assign_cast_loc_blk_n = p_rows_assign_cast_loc_empty_n;
end else begin
p_rows_assign_cast_loc_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((gamma_empty_n == 1'b0) | (p_cols_assign_cast_loc_empty_n == 1'b0) | (p_rows_assign_cast_loc_empty_n == 1'b0) | (ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_rows_assign_cast_loc_read = 1'b1;
end else begin
p_rows_assign_cast_loc_read = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
if ((~((gamma_empty_n == 1'b0) | (p_cols_assign_cast_loc_empty_n == 1'b0) | (p_rows_assign_cast_loc_empty_n == 1'b0) | (ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_NS_fsm = ap_ST_fsm_state2;
end else begin
ap_NS_fsm = ap_ST_fsm_state1;
end
end
ap_ST_fsm_state2 : begin
ap_NS_fsm = ap_ST_fsm_state3;
end
ap_ST_fsm_state3 : begin
if (((exitcond161_i_i_i_fu_541_p2 == 1'd1) & (1'b1 == ap_CS_fsm_state3))) begin
ap_NS_fsm = ap_ST_fsm_state1;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end
end
ap_ST_fsm_pp0_stage0 : begin
if ((~((1'b0 == ap_block_pp0_stage0_subdone) & (exitcond_i_i_i_fu_556_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) & ~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b1)))) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end else if ((((1'b0 == ap_block_pp0_stage0_subdone) & (exitcond_i_i_i_fu_556_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b1)) | ((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b1)))) begin
ap_NS_fsm = ap_ST_fsm_state9;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end
end
ap_ST_fsm_state9 : begin
ap_NS_fsm = ap_ST_fsm_state3;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd3];
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];
assign ap_CS_fsm_state9 = ap_CS_fsm[32'd4];
assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage0_01001 = (((ap_enable_reg_pp0_iter1 == 1'b1) & (((img0_data_stream_2_V_empty_n == 1'b0) & (exitcond_i_i_i_reg_837 == 1'd0)) | ((img0_data_stream_1_V_empty_n == 1'b0) & (exitcond_i_i_i_reg_837 == 1'd0)) | ((img0_data_stream_0_V_empty_n == 1'b0) & (exitcond_i_i_i_reg_837 == 1'd0)))) | ((ap_enable_reg_pp0_iter4 == 1'b1) & (((img3_data_stream_2_V_full_n == 1'b0) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 == 1'd0)) | ((img3_data_stream_1_V_full_n == 1'b0) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 == 1'd0)) | ((img3_data_stream_0_V_full_n == 1'b0) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 == 1'd0)))));
end
always @ (*) begin
ap_block_pp0_stage0_11001 = (((ap_enable_reg_pp0_iter1 == 1'b1) & (((img0_data_stream_2_V_empty_n == 1'b0) & (exitcond_i_i_i_reg_837 == 1'd0)) | ((img0_data_stream_1_V_empty_n == 1'b0) & (exitcond_i_i_i_reg_837 == 1'd0)) | ((img0_data_stream_0_V_empty_n == 1'b0) & (exitcond_i_i_i_reg_837 == 1'd0)))) | ((ap_enable_reg_pp0_iter4 == 1'b1) & (((img3_data_stream_2_V_full_n == 1'b0) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 == 1'd0)) | ((img3_data_stream_1_V_full_n == 1'b0) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 == 1'd0)) | ((img3_data_stream_0_V_full_n == 1'b0) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 == 1'd0)))));
end
always @ (*) begin
ap_block_pp0_stage0_subdone = (((ap_enable_reg_pp0_iter1 == 1'b1) & (((img0_data_stream_2_V_empty_n == 1'b0) & (exitcond_i_i_i_reg_837 == 1'd0)) | ((img0_data_stream_1_V_empty_n == 1'b0) & (exitcond_i_i_i_reg_837 == 1'd0)) | ((img0_data_stream_0_V_empty_n == 1'b0) & (exitcond_i_i_i_reg_837 == 1'd0)))) | ((ap_enable_reg_pp0_iter4 == 1'b1) & (((img3_data_stream_2_V_full_n == 1'b0) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 == 1'd0)) | ((img3_data_stream_1_V_full_n == 1'b0) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 == 1'd0)) | ((img3_data_stream_0_V_full_n == 1'b0) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 == 1'd0)))));
end
always @ (*) begin
ap_block_state1 = ((gamma_empty_n == 1'b0) | (p_cols_assign_cast_loc_empty_n == 1'b0) | (p_rows_assign_cast_loc_empty_n == 1'b0) | (ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
assign ap_block_state4_pp0_stage0_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state5_pp0_stage0_iter1 = (((img0_data_stream_2_V_empty_n == 1'b0) & (exitcond_i_i_i_reg_837 == 1'd0)) | ((img0_data_stream_1_V_empty_n == 1'b0) & (exitcond_i_i_i_reg_837 == 1'd0)) | ((img0_data_stream_0_V_empty_n == 1'b0) & (exitcond_i_i_i_reg_837 == 1'd0)));
end
assign ap_block_state6_pp0_stage0_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state7_pp0_stage0_iter3 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state8_pp0_stage0_iter4 = (((img3_data_stream_2_V_full_n == 1'b0) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 == 1'd0)) | ((img3_data_stream_1_V_full_n == 1'b0) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 == 1'd0)) | ((img3_data_stream_0_V_full_n == 1'b0) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_837 == 1'd0)));
end
assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
assign exitcond161_i_i_i_fu_541_p2 = ((t_V_cast_i_i_fu_537_p1 == p_rows_assign_cast_lo_reg_762) ? 1'b1 : 1'b0);
assign exitcond_i_i_i_fu_556_p2 = ((t_V_1_cast_i_i_fu_552_p1 == p_cols_assign_cast_lo_reg_767) ? 1'b1 : 1'b0);
assign i_V_fu_546_p2 = (t_V_reg_433 + 11'd1);
assign img3_data_stream_0_V_din = ((or_cond6_reg_821[0:0] === 1'b1) ? newSel6_fu_664_p3 : ap_reg_pp0_iter3_tmp_9_reg_846);
assign img3_data_stream_1_V_din = ((or_cond6_reg_821[0:0] === 1'b1) ? newSel13_fu_700_p3 : ap_reg_pp0_iter3_tmp_10_reg_852);
assign img3_data_stream_2_V_din = ((or_cond6_reg_821[0:0] === 1'b1) ? newSel20_fu_736_p3 : ap_reg_pp0_iter3_tmp_11_reg_858);
assign j_V_fu_561_p2 = (t_V_2_reg_444 + 11'd1);
assign lut0_2_address0 = tmp_26_i_i_fu_567_p1;
assign lut0_2_address1 = tmp_26_1_i_i_fu_578_p1;
assign lut0_2_address2 = tmp_26_2_i_i_fu_589_p1;
assign lut0_4_address0 = tmp_26_i_i_fu_567_p1;
assign lut0_4_address1 = tmp_26_1_i_i_fu_578_p1;
assign lut0_4_address2 = tmp_26_2_i_i_fu_589_p1;
assign lut1_2_address0 = tmp_26_i_i_fu_567_p1;
assign lut1_2_address1 = tmp_26_1_i_i_fu_578_p1;
assign lut1_2_address2 = tmp_26_2_i_i_fu_589_p1;
assign lut1_4_address0 = tmp_26_i_i_fu_567_p1;
assign lut1_4_address1 = tmp_26_1_i_i_fu_578_p1;
assign lut1_4_address2 = tmp_26_2_i_i_fu_589_p1;
assign lut1_6_address0 = tmp_26_i_i_fu_567_p1;
assign lut1_6_address1 = tmp_26_1_i_i_fu_578_p1;
assign lut1_6_address2 = tmp_26_2_i_i_fu_589_p1;
assign lut1_8_address0 = tmp_26_i_i_fu_567_p1;
assign lut1_8_address1 = tmp_26_1_i_i_fu_578_p1;
assign lut1_8_address2 = tmp_26_2_i_i_fu_589_p1;
assign lut2_0_address0 = tmp_26_i_i_fu_567_p1;
assign lut2_0_address1 = tmp_26_1_i_i_fu_578_p1;
assign lut2_0_address2 = tmp_26_2_i_i_fu_589_p1;
assign lut2_2_address0 = tmp_26_i_i_fu_567_p1;
assign lut2_2_address1 = tmp_26_1_i_i_fu_578_p1;
assign lut2_2_address2 = tmp_26_2_i_i_fu_589_p1;
assign newSel10_fu_621_p3 = ((sel_tmp2_reg_772[0:0] === 1'b1) ? lut2_0_q1 : lut2_2_q1);
assign newSel11_fu_688_p3 = ((or_cond_reg_800[0:0] === 1'b1) ? newSel8_fu_678_p3 : newSel9_reg_1034);
assign newSel12_fu_694_p3 = ((or_cond2_reg_807[0:0] === 1'b1) ? newSel7_fu_683_p3 : newSel10_reg_1039);
assign newSel13_fu_700_p3 = ((or_cond4_reg_814[0:0] === 1'b1) ? newSel11_fu_688_p3 : newSel12_fu_694_p3);
assign newSel14_fu_714_p3 = ((sel_tmp5_reg_793[0:0] === 1'b1) ? d_val_2_2_reg_1044 : d_val_2_3_reg_1049);
assign newSel15_fu_628_p3 = ((sel_tmp1_reg_786[0:0] === 1'b1) ? lut1_2_q2 : lut1_4_q2);
assign newSel16_fu_719_p3 = ((sel_tmp6_reg_779[0:0] === 1'b1) ? d_val_2_6_reg_1054 : d_val_2_7_reg_1059);
assign newSel17_fu_635_p3 = ((sel_tmp2_reg_772[0:0] === 1'b1) ? lut2_0_q2 : lut2_2_q2);
assign newSel18_fu_724_p3 = ((or_cond_reg_800[0:0] === 1'b1) ? newSel14_fu_714_p3 : newSel15_reg_1064);
assign newSel19_fu_730_p3 = ((or_cond2_reg_807[0:0] === 1'b1) ? newSel16_fu_719_p3 : newSel17_reg_1069);
assign newSel1_fu_600_p3 = ((sel_tmp1_reg_786[0:0] === 1'b1) ? lut1_2_q0 : lut1_4_q0);
assign newSel20_fu_736_p3 = ((or_cond4_reg_814[0:0] === 1'b1) ? newSel18_fu_724_p3 : newSel19_fu_730_p3);
assign newSel2_fu_647_p3 = ((sel_tmp6_reg_779[0:0] === 1'b1) ? d_val_0_6_reg_994 : d_val_0_7_reg_999);
assign newSel3_fu_607_p3 = ((sel_tmp2_reg_772[0:0] === 1'b1) ? lut2_0_q0 : lut2_2_q0);
assign newSel4_fu_652_p3 = ((or_cond_reg_800[0:0] === 1'b1) ? newSel_fu_642_p3 : newSel1_reg_1004);
assign newSel5_fu_658_p3 = ((or_cond2_reg_807[0:0] === 1'b1) ? newSel2_fu_647_p3 : newSel3_reg_1009);
assign newSel6_fu_664_p3 = ((or_cond4_reg_814[0:0] === 1'b1) ? newSel4_fu_652_p3 : newSel5_fu_658_p3);
assign newSel7_fu_683_p3 = ((sel_tmp6_reg_779[0:0] === 1'b1) ? d_val_1_6_reg_1024 : d_val_1_7_reg_1029);
assign newSel8_fu_678_p3 = ((sel_tmp5_reg_793[0:0] === 1'b1) ? d_val_1_2_reg_1014 : d_val_1_3_reg_1019);
assign newSel9_fu_614_p3 = ((sel_tmp1_reg_786[0:0] === 1'b1) ? lut1_2_q1 : lut1_4_q1);
assign newSel_fu_642_p3 = ((sel_tmp5_reg_793[0:0] === 1'b1) ? d_val_0_2_reg_984 : d_val_0_3_reg_989);
assign or_cond1_fu_501_p2 = (sel_tmp8_fu_475_p2 | sel_tmp1_fu_480_p2);
assign or_cond2_fu_507_p2 = (sel_tmp6_fu_470_p2 | sel_tmp4_fu_465_p2);
assign or_cond3_fu_513_p2 = (sel_tmp_fu_455_p2 | sel_tmp2_fu_460_p2);
assign or_cond4_fu_519_p2 = (or_cond_fu_495_p2 | or_cond1_fu_501_p2);
assign or_cond5_fu_525_p2 = (or_cond3_fu_513_p2 | or_cond2_fu_507_p2);
assign or_cond6_fu_531_p2 = (or_cond5_fu_525_p2 | or_cond4_fu_519_p2);
assign or_cond_fu_495_p2 = (sel_tmp5_fu_490_p2 | sel_tmp3_fu_485_p2);
assign sel_tmp1_fu_480_p2 = ((gamma_read_reg_750 == 8'd3) ? 1'b1 : 1'b0);
assign sel_tmp2_fu_460_p2 = ((gamma_read_reg_750 == 8'd7) ? 1'b1 : 1'b0);
assign sel_tmp3_fu_485_p2 = ((gamma_read_reg_750 == 8'd2) ? 1'b1 : 1'b0);
assign sel_tmp4_fu_465_p2 = ((gamma_read_reg_750 == 8'd6) ? 1'b1 : 1'b0);
assign sel_tmp5_fu_490_p2 = ((gamma_read_reg_750 == 8'd1) ? 1'b1 : 1'b0);
assign sel_tmp6_fu_470_p2 = ((gamma_read_reg_750 == 8'd5) ? 1'b1 : 1'b0);
assign sel_tmp8_fu_475_p2 = ((gamma_read_reg_750 == 8'd4) ? 1'b1 : 1'b0);
assign sel_tmp_fu_455_p2 = ((gamma_read_reg_750 == 8'd8) ? 1'b1 : 1'b0);
assign t_V_1_cast_i_i_fu_552_p1 = t_V_2_reg_444;
assign t_V_cast_i_i_fu_537_p1 = t_V_reg_433;
assign tmp_26_1_i_i_fu_578_p1 = tmp_10_reg_852;
assign tmp_26_2_i_i_fu_589_p1 = tmp_11_reg_858;
assign tmp_26_i_i_fu_567_p1 = tmp_9_reg_846;
endmodule //Loop_loop_height_pro
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFBUF_BEHAVIORAL_V
`define SKY130_FD_SC_LP__BUFBUF_BEHAVIORAL_V
/**
* bufbuf: Double buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__bufbuf (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFBUF_BEHAVIORAL_V |
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: vga_ram.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module vga_ram (
address_a,
address_b,
clock_a,
clock_b,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [11:0] address_a;
input [11:0] address_b;
input clock_a;
input clock_b;
input [7:0] data_a;
input [7:0] data_b;
input wren_a;
input wren_b;
output [7:0] q_a;
output [7:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock_a;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] sub_wire1;
wire [7:0] q_a = sub_wire0[7:0];
wire [7:0] q_b = sub_wire1[7:0];
altsyncram altsyncram_component (
.clock0 (clock_a),
.wren_a (wren_a),
.address_b (address_b),
.clock1 (clock_b),
.data_b (data_b),
.wren_b (wren_b),
.address_a (address_a),
.data_a (data_a),
.q_a (sub_wire0),
.q_b (sub_wire1),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.eccstatus (),
.rden_a (1'b1),
.rden_b (1'b1));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.indata_reg_b = "CLOCK1",
`ifdef NO_PLI
altsyncram_component.init_file = "test_screen.rif"
`else
altsyncram_component.init_file = "test_screen.hex"
`endif
,
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.numwords_b = 4096,
altsyncram_component.operation_mode = "BIDIR_DUAL_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.widthad_a = 12,
altsyncram_component.widthad_b = 12,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1,
altsyncram_component.width_byteena_b = 1,
altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK1";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "5"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "test_screen.hex"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: INIT_FILE STRING "test_screen.hex"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: USED_PORT: address_a 0 0 12 0 INPUT NODEFVAL "address_a[11..0]"
// Retrieval info: USED_PORT: address_b 0 0 12 0 INPUT NODEFVAL "address_b[11..0]"
// Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
// Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
// Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]"
// Retrieval info: USED_PORT: data_b 0 0 8 0 INPUT NODEFVAL "data_b[7..0]"
// Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]"
// Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address_a 0 0 12 0
// Retrieval info: CONNECT: @address_b 0 0 12 0 address_b 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
// Retrieval info: CONNECT: @data_b 0 0 8 0 data_b 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
// Retrieval info: CONNECT: q_b 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL vga_ram.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL vga_ram.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vga_ram.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vga_ram.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vga_ram_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL vga_ram_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright 2010-2012 by Michael A. Morris, dba M. A. Morris & Associates
//
// All rights reserved. The source code contained herein is publicly released
// under the terms and conditions of the GNU Lesser Public License. No part of
// this source code may be reproduced or transmitted in any form or by any
// means, electronic or mechanical, including photocopying, recording, or any
// information storage and retrieval system in violation of the license under
// which the source code is released.
//
// The souce code contained herein is free; it may be redistributed and/or
// modified in accordance with the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either version 2.1 of
// the GNU Lesser General Public License, or any later version.
//
// The souce code contained herein is freely released WITHOUT ANY WARRANTY;
// without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
// PARTICULAR PURPOSE. (Refer to the GNU Lesser General Public License for
// more details.)
//
// A copy of the GNU Lesser General Public License should have been received
// along with the source code contained herein; if not, a copy can be obtained
// by writing to:
//
// Free Software Foundation, Inc.
// 51 Franklin Street, Fifth Floor
// Boston, MA 02110-1301 USA
//
// Further, no use of this source code is permitted in any form or means
// without inclusion of this banner prominently in any derived works.
//
// Michael A. Morris
// Huntsville, AL
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
///////////////////////////////////////////////////////////////////////////////
// Company: M. A. Morris & Associates
// Engineer: Michael A. Morris
//
// Create Date: 19:48:02 07/10/2010
// Design Name: Booth Multiplier
// Module Name: Booth_Multiplier.v
// Project Name: Booth_Multiplier
// Target Devices: Spartan-3AN
// Tool versions: Xilinx ISE 10.1 SP3
//
// Description:
//
// This module implements a parameterized multiplier which uses the Booth
// algorithm for its implementation. The implementation is based on the
// algorithm described in "Computer Organization", Hamacher et al, McGraw-
// Hill Book Company, New York, NY, 1978, ISBN: 0-07-025681-0.
//
// Dependencies:
//
// Revision:
//
// 0.01 10G10 MAM File Created
//
// Additional Comments:
//
///////////////////////////////////////////////////////////////////////////////
module Booth_Multiplier #(
parameter pN = 4 // Width = 2**pN: multiplicand & multiplier
)(
input Rst, // Reset
input Clk, // Clock
input Ld, // Load Registers and Start Multiplier
input [(2**pN - 1):0] M, // Multiplicand
input [(2**pN - 1):0] R, // Multiplier
output reg Valid, // Product Valid
output reg [(2**(pN+1) - 1):0] P // Product <= M * R
);
///////////////////////////////////////////////////////////////////////////////
//
// Local Parameters
//
///////////////////////////////////////////////////////////////////////////////
//
// Declarations
//
reg [2**pN:0] A; // Multiplicand w/ sign guard bit
reg [ pN:0] Cntr; // Operation Counter
reg [2**pN:0] S; // Adder w/ sign guard bit
reg [(2**(pN+1) + 1):0] Prod; // Double length product w/ guard bits
///////////////////////////////////////////////////////////////////////////////
//
// Implementation
//
always @(posedge Clk)
begin
if(Rst)
Cntr <= #1 0;
else if(Ld)
Cntr <= #1 2**pN;
else if(|Cntr)
Cntr <= #1 (Cntr - 1);
end
// Multiplicand Register
// includes an additional bit to guard sign bit in the event the
// most negative value is provided as the multiplicand.
always @(posedge Clk)
begin
if(Rst)
A <= #1 0;
else if(Ld)
A <= #1 {M[2**pN - 1], M};
end
// Compute Upper Partial Product: (2**pN + 1) bits in width
always @(*)
begin
case(Prod[1:0])
2'b01 : S <= Prod[(2**(pN+1) + 1):(2**pN + 1)] + A;
2'b10 : S <= Prod[(2**(pN+1) + 1):(2**pN + 1)] - A;
default : S <= Prod[(2**(pN+1) + 1):(2**pN + 1)];
endcase
end
// Register Partial products and shift rigth arithmetically.
// Product register has guard bits on both ends.
always @(posedge Clk)
begin
if(Rst)
Prod <= #1 0;
else if(Ld)
Prod <= #1 {R, 1'b0};
else if(|Cntr)
Prod <= #1 {S[2**pN], S, Prod[2**pN:1]}; // Arithmetic Shift Right
end
// Assign the product less the two guard bits to the output port
always @(posedge Clk)
begin
if(Rst)
P <= #1 0;
else if(Cntr == 1)
P <= #1 {S[2**pN], S, Prod[2**pN:2]};
end
// Count the number of shifts
// This implementation does not use any optimizations to perform multiple
// bit shifts to skip over runs of 1s or 0s.
always @(posedge Clk)
begin
if(Rst)
Valid <= #1 0;
else
Valid <= #1 (Cntr == 1);
end
endmodule
|
module prometheus_fx3_stream_out(
input rst_n,
input clk_100,
input stream_out_mode_selected,
input i_gpif_in_ch1_rdy_d,
input i_gpif_out_ch1_rdy_d,
input [31:0]stream_out_data_from_fx3,
output o_gpif_re_n_stream_out_,
output o_gpif_oe_n_stream_out_
);
reg [2:0]current_stream_out_state;
reg [2:0]next_stream_out_state;
//parameters for StreamOUT mode state machine
parameter [2:0] stream_out_idle = 3'd0;
parameter [2:0] stream_out_flagc_rcvd = 3'd1;
parameter [2:0] stream_out_wait_flagd = 3'd2;
parameter [2:0] stream_out_read = 3'd3;
parameter [2:0] stream_out_read_rd_and_oe_delay = 3'd4;
parameter [2:0] stream_out_read_oe_delay = 3'd5;
reg [1:0] oe_delay_cnt;
reg rd_oe_delay_cnt;
assign o_gpif_re_n_stream_out_ = ((current_stream_out_state == stream_out_read) | (current_stream_out_state == stream_out_read_rd_and_oe_delay)) ? 1'b0 : 1'b1;
assign o_gpif_oe_n_stream_out_ = ((current_stream_out_state == stream_out_read) | (current_stream_out_state == stream_out_read_rd_and_oe_delay) | (current_stream_out_state == stream_out_read_oe_delay)) ? 1'b0 : 1'b1;
//counter to delay the read and output enable signal
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
rd_oe_delay_cnt <= 1'b0;
end else if(current_stream_out_state == stream_out_read) begin
rd_oe_delay_cnt <= 1'b1;
end else if((current_stream_out_state == stream_out_read_rd_and_oe_delay) & (rd_oe_delay_cnt > 1'b0))begin
rd_oe_delay_cnt <= rd_oe_delay_cnt - 1'b1;
end else begin
rd_oe_delay_cnt <= rd_oe_delay_cnt;
end
end
//Counter to delay the OUTPUT Enable(oe) signal
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
oe_delay_cnt <= 2'd0;
end else if(current_stream_out_state == stream_out_read_rd_and_oe_delay) begin
oe_delay_cnt <= 2'd2;
end else if((current_stream_out_state == stream_out_read_oe_delay) & (oe_delay_cnt > 1'b0))begin
oe_delay_cnt <= oe_delay_cnt - 1'b1;
end else begin
oe_delay_cnt <= oe_delay_cnt;
end
end
//stream_out mode state machine
always @(posedge clk_100, negedge rst_n)begin
if(!rst_n)begin
current_stream_out_state <= stream_out_idle;
end else begin
current_stream_out_state <= next_stream_out_state;
end
end
//steamOUT mode state machine combo
always @(*)begin
next_stream_out_state = current_stream_out_state;
case(current_stream_out_state)
stream_out_idle:begin
if((stream_out_mode_selected) & (i_gpif_in_ch1_rdy_d == 1'b1))begin
next_stream_out_state = stream_out_flagc_rcvd;
end else begin
next_stream_out_state = stream_out_idle;
end
end
stream_out_flagc_rcvd:begin
next_stream_out_state = stream_out_wait_flagd;
end
stream_out_wait_flagd:begin
if(i_gpif_out_ch1_rdy_d == 1'b1)begin
next_stream_out_state = stream_out_read;
end else begin
next_stream_out_state = stream_out_wait_flagd;
end
end
stream_out_read :begin
if(i_gpif_out_ch1_rdy_d == 1'b0)begin
next_stream_out_state = stream_out_read_rd_and_oe_delay;
end else begin
next_stream_out_state = stream_out_read;
end
end
stream_out_read_rd_and_oe_delay : begin
if(rd_oe_delay_cnt == 0)begin
next_stream_out_state = stream_out_read_oe_delay;
end else begin
next_stream_out_state = stream_out_read_rd_and_oe_delay;
end
end
stream_out_read_oe_delay : begin
if(oe_delay_cnt == 0)begin
next_stream_out_state = stream_out_idle;
end else begin
next_stream_out_state = stream_out_read_oe_delay;
end
end
endcase
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
module cf_csc_1 (
// csc inputs
// csc <= c1*d[23:16] + c2*d[15:8] + c3*d[7:0] + c4;
clk,
vs,
hs,
de,
data,
C1,
C2,
C3,
C4,
// these are the delay matched versions of the inputs
csc_vs,
csc_hs,
csc_de,
csc_data_1);
// csc inputs
// csc <= c1*d[23:16] + c2*d[15:8] + c3*d[7:0] + c4;
input clk;
input vs;
input hs;
input de;
input [23:0] data;
input [16:0] C1;
input [16:0] C2;
input [16:0] C3;
input [24:0] C4;
// these are the delay matched versions of the inputs
output csc_vs;
output csc_hs;
output csc_de;
output [ 7:0] csc_data_1;
wire [24:0] data_1_m_s;
wire [ 2:0] ddata_1_m_s;
wire [24:0] data_2_m_s;
wire [ 2:0] ddata_2_m_s;
wire [24:0] data_3_m_s;
wire [ 2:0] ddata_3_m_s;
wire [ 2:0] ddata_m_s;
assign ddata_m_s = ddata_1_m_s & ddata_2_m_s & ddata_3_m_s;
// c1*R
cf_mul #(.DELAY_DATA_WIDTH(3)) i_mul_c1 (
.clk (clk),
.data_a (C1),
.data_b (data[23:16]),
.data_p (data_1_m_s),
.ddata_in ({vs, hs, de}),
.ddata_out (ddata_1_m_s));
// c2*G
cf_mul #(.DELAY_DATA_WIDTH(3)) i_mul_c2 (
.clk (clk),
.data_a (C2),
.data_b (data[15:8]),
.data_p (data_2_m_s),
.ddata_in ({vs, hs, de}),
.ddata_out (ddata_2_m_s));
// c3*B
cf_mul #(.DELAY_DATA_WIDTH(3)) i_mul_c3 (
.clk (clk),
.data_a (C3),
.data_b (data[7:0]),
.data_p (data_3_m_s),
.ddata_in ({vs, hs, de}),
.ddata_out (ddata_3_m_s));
// last stage addition
cf_add #(.DELAY_DATA_WIDTH(3)) i_add_c4 (
.clk (clk),
.data_1 (data_1_m_s),
.data_2 (data_2_m_s),
.data_3 (data_3_m_s),
.data_4 (C4),
.data_p (csc_data_1),
.ddata_in (ddata_m_s),
.ddata_out ({csc_vs, csc_hs, csc_de}));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// Xilinx ip cores are not fifo friendly and require a hard stop on the interface
// valid & data can not change, if ready is deasserted (if they do you will have to
// roll it back).
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad_axis_inf_rx (
// adi interface
clk,
rst,
valid,
last,
data,
// xilinx interface
inf_valid,
inf_last,
inf_data,
inf_ready);
// parameter for data width
parameter DATA_WIDTH = 16;
localparam DW = DATA_WIDTH - 1;
// adi interface
input clk;
input rst;
input valid;
input last;
input [DW:0] data;
// xil interface
output inf_valid;
output inf_last;
output [DW:0] inf_data;
input inf_ready;
// internal registers
reg [ 2:0] wcnt = 'd0;
reg wlast_0 = 'd0;
reg [DW:0] wdata_0 = 'd0;
reg wlast_1 = 'd0;
reg [DW:0] wdata_1 = 'd0;
reg wlast_2 = 'd0;
reg [DW:0] wdata_2 = 'd0;
reg wlast_3 = 'd0;
reg [DW:0] wdata_3 = 'd0;
reg wlast_4 = 'd0;
reg [DW:0] wdata_4 = 'd0;
reg wlast_5 = 'd0;
reg [DW:0] wdata_5 = 'd0;
reg wlast_6 = 'd0;
reg [DW:0] wdata_6 = 'd0;
reg wlast_7 = 'd0;
reg [DW:0] wdata_7 = 'd0;
reg [ 2:0] rcnt = 'd0;
reg inf_valid = 'd0;
reg inf_last = 'd0;
reg [DW:0] inf_data = 'd0;
// write interface
always @(posedge clk) begin
if (rst == 1'b1) begin
wcnt <= 'd0;
end else if (valid == 1'b1) begin
wcnt <= wcnt + 1'b1;
end
if ((wcnt == 3'd0) && (valid == 1'b1)) begin
wlast_0 <= last;
wdata_0 <= data;
end
if ((wcnt == 3'd1) && (valid == 1'b1)) begin
wlast_1 <= last;
wdata_1 <= data;
end
if ((wcnt == 3'd2) && (valid == 1'b1)) begin
wlast_2 <= last;
wdata_2 <= data;
end
if ((wcnt == 3'd3) && (valid == 1'b1)) begin
wlast_3 <= last;
wdata_3 <= data;
end
if ((wcnt == 3'd4) && (valid == 1'b1)) begin
wlast_4 <= last;
wdata_4 <= data;
end
if ((wcnt == 3'd5) && (valid == 1'b1)) begin
wlast_5 <= last;
wdata_5 <= data;
end
if ((wcnt == 3'd6) && (valid == 1'b1)) begin
wlast_6 <= last;
wdata_6 <= data;
end
if ((wcnt == 3'd7) && (valid == 1'b1)) begin
wlast_7 <= last;
wdata_7 <= data;
end
end
// read interface
always @(posedge clk) begin
if (rst == 1'b1) begin
rcnt <= 'd0;
inf_valid <= 'd0;
inf_last <= 'b0;
inf_data <= 'd0;
end else if ((inf_ready == 1'b1) || (inf_valid == 1'b0)) begin
if (rcnt == wcnt) begin
rcnt <= rcnt;
inf_valid <= 1'd0;
inf_last <= 1'b0;
inf_data <= 'd0;
end else begin
rcnt <= rcnt + 1'b1;
inf_valid <= 1'b1;
case (rcnt)
3'd0: begin
inf_last <= wlast_0;
inf_data <= wdata_0;
end
3'd1: begin
inf_last <= wlast_1;
inf_data <= wdata_1;
end
3'd2: begin
inf_last <= wlast_2;
inf_data <= wdata_2;
end
3'd3: begin
inf_last <= wlast_3;
inf_data <= wdata_3;
end
3'd4: begin
inf_last <= wlast_4;
inf_data <= wdata_4;
end
3'd5: begin
inf_last <= wlast_5;
inf_data <= wdata_5;
end
3'd6: begin
inf_last <= wlast_6;
inf_data <= wdata_6;
end
default: begin
inf_last <= wlast_7;
inf_data <= wdata_7;
end
endcase
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// This file is part of the M32632 project
// http://opencores.org/project,m32632
//
// Filename: CACHE_LOGIK.v
// Version: 1.1 bug fix
// History: 1.0 first release of 30 Mai 2015
// Date: 7 October 2015
//
// Copyright (C) 2015 Udo Moeller
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//
// +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// Modules contained in this file:
// 1. DEBUG_AE Debug unit for address compare in data cache
// 2. MMU_UP MMU memory update and initalization controller
// 3. DCA_CONTROL Data cache valid memory update and initalization controller
// 4. MMU_MATCH MMU virtual address match detector
// 5. CA_MATCH Cache tag match detector
// 6. DCACHE_SM Data cache state machine
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 1. DEBUG_AE Debug unit for address compare in data cache
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module DEBUG_AE ( DBG_IN, READ, WRITE, USER, VIRTUELL, ACC_OK, VADR_R, MMU_Q, ENBYTE, DBG_HIT );
input [40:2] DBG_IN;
input READ,WRITE;
input USER;
input VIRTUELL;
input ACC_OK;
input [31:2] VADR_R;
input [19:0] MMU_Q;
input [3:0] ENBYTE;
output DBG_HIT;
wire sd,ud,crd,cwr,vnp;
wire make;
wire virt_adr,real_adr,page_adr;
wire byte_en;
assign sd = DBG_IN[40];
assign ud = DBG_IN[39];
assign crd = DBG_IN[38];
assign cwr = DBG_IN[37];
assign vnp = DBG_IN[36];
assign make = ((ud & USER) | (sd & ~USER)) // compare USER or SUPERVISOR
& (VIRTUELL == vnp) // compare real or virtual address
& ((cwr & WRITE) | (crd & READ)); // compare READ or WRITE
assign virt_adr = (MMU_Q == DBG_IN[31:12]);
assign real_adr = (VADR_R[31:12] == DBG_IN[31:12]);
assign page_adr = (VADR_R[11:2] == DBG_IN[11:2]);
assign byte_en = |(ENBYTE & DBG_IN[35:32]);
assign DBG_HIT = ACC_OK // all valid
& make // selection is valid
& (VIRTUELL ? virt_adr : real_adr) & page_adr // address
& byte_en; // Byte Enable
endmodule
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 2. MMU_UP MMU memory update and initalization controller
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module MMU_UP ( BCLK, BRESET, NEW_PTB, PTB1, IVAR, WR_MRAM, VADR, VADR_R, MVALID, UPDATE,
WE_MV, WADR_MV, RADR_MV, DAT_MV, NEW_PTB_RUN );
input BCLK;
input BRESET;
input NEW_PTB; // the MMU memory is cleared. Pulse of one BCLK cycle, Op-Dec is waiting
input PTB1; // which one
input IVAR;
input WR_MRAM; // BCLK : update MRAM and MMU_VAL
input [19:16] VADR,VADR_R; // For update
input [31:0] MVALID,UPDATE;
output WE_MV; // Write Enable MMU Valid
output [3:0] WADR_MV,RADR_MV;
output [31:0] DAT_MV;
output NEW_PTB_RUN;
reg neue_ptb,wr_flag,old_rst,run_over;
reg [3:0] count;
wire [15:0] new_val;
assign WE_MV = wr_flag | WR_MRAM | IVAR; // write on falling edge BCLK
assign RADR_MV = run_over ? count : VADR;
assign WADR_MV = wr_flag ? (count - 4'b0001) : VADR_R;
assign DAT_MV = wr_flag ? {MVALID[31:16],new_val} : UPDATE; // Only the matching entries are cleared : PTB0/PTB1
// [31:16] Address-Space memory, [15:0] Valid memory
assign new_val = neue_ptb ? (PTB1 ? (MVALID[15:0] & ~MVALID[31:16]) : (MVALID[15:0] & MVALID[31:16])) : 16'h0;
always @(posedge BCLK or negedge BRESET)
if (!BRESET) neue_ptb <= 1'b0;
else neue_ptb <= NEW_PTB | (neue_ptb & run_over);
always @(posedge BCLK) old_rst <= BRESET; // after Reset all will be set to 0
always @(posedge BCLK) run_over <= ((~old_rst | NEW_PTB) | (run_over & (count != 4'hF))) & BRESET;
always @(posedge BCLK) count <= run_over ? count + 4'h1 : 4'h0;
always @(posedge BCLK) wr_flag <= run_over;
assign NEW_PTB_RUN = wr_flag; // Info to Op-Dec
endmodule
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 3. DCA_CONTROL Data cache valid memory update and initalization controller
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module DCA_CONTROL ( BCLK, MCLK, BRESET, CUPDATE, DRAM_ACC, CA_SET, HIT_ALL, WRCFG, VADR_R, UPDATE, INVAL_A, WRITE,
WCTRL, KILL, WRCRAM0, WRCRAM1, WE_CV, WADR_CV, DAT_CV, INIT_CA_RUN, WRSET0, WRSET1 );
input BCLK;
input MCLK;
input BRESET;
input CUPDATE; // State CUPDATE : Cache is filled from DRAM
input DRAM_ACC;
input CA_SET;
input HIT_ALL; // a complete cache hit !
input WRCFG; // static signal : GND or VDD
input [11:7] VADR_R;
input [23:0] UPDATE;
input INVAL_A;
input WRITE;
input [1:0] WCTRL; // [1] : Read Burst Signal from DRAM controller, MCLK aligned. [0] : Cache inhibit
input KILL; // valid Ram must be updated because of collision ... or CINV
output WRCRAM0,WRCRAM1;
output WE_CV;
output [4:0] WADR_CV;
output [23:0] DAT_CV;
output INIT_CA_RUN;
output WRSET0,WRSET1;
reg [1:0] state;
reg [4:0] acount;
reg ca_set_d;
reg dly_bclk,zero,wr_puls;
reg [2:0] count,refer;
wire countf;
// physical address is stored in TAG-RAM
assign WRCRAM0 = (CUPDATE & ~WCTRL[0]) & ~CA_SET;
assign WRCRAM1 = (CUPDATE & ~WCTRL[0]) & CA_SET;
// Load Valid RAM :
assign WE_CV = state[1] | HIT_ALL | (CUPDATE & ~WCTRL[0]) | KILL; // Hit All for "Last" Update
assign WADR_CV = state[1] ? acount : VADR_R;
assign DAT_CV = state[1] ? 24'h0 : UPDATE;
// Clear of Cache-Valid RAMs : 32 clocks of BCLK
assign countf = (acount == 5'h1F);
always @(posedge BCLK)
casex ({BRESET,INVAL_A,countf,state[1:0]})
5'b0xx_xx : state <= 2'b01;
5'b1xx_01 : state <= 2'b10; // start counter
5'b10x_00 : state <= 2'b00; // wait ...
5'b11x_00 : state <= 2'b10;
5'b1x0_10 : state <= 2'b10;
5'b1x1_10 : state <= 2'b00;
default : state <= 2'b0;
endcase
always @(posedge BCLK) if (!state[1]) acount <= 5'h0; else acount <= acount + 5'h01;
assign INIT_CA_RUN = state[1];
always @(posedge BCLK) if (DRAM_ACC) ca_set_d <= CA_SET;
// WRITE Control in data RAMs
assign WRSET0 = ( ~CA_SET & WRITE & HIT_ALL & wr_puls) | (WCTRL[1] & ~ca_set_d);
assign WRSET1 = ( CA_SET & WRITE & HIT_ALL & wr_puls) | (WCTRL[1] & ca_set_d);
// ++++++++++++ Special circuit for Timing of write pulse for data RAM of data cache +++++++++
always @(negedge MCLK) dly_bclk <= BCLK;
always @(negedge MCLK) zero <= BCLK & ~dly_bclk;
always @(posedge MCLK) if (zero) count <= 3'd0; else count <= count + 3'd1;
// count at zero , ref Wert
// 1 : --- always on 5 : 100 001
// 2 : 001 000 6 : 101 010
// 3 : 010 010 7 : 110 011
// 4 : 011 000 8 : 111 100
always @(posedge MCLK) if (zero) refer <= {(count == 3'd7),((count == 3'd5) | (count[1:0] == 2'b10)),(count[2] & ~count[0])};
always @(posedge MCLK) wr_puls <= (count == refer) | WRCFG;
endmodule
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 4. MMU_MATCH MMU virtual address match detector
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module MMU_MATCH ( USER, READ, WRITE, RMW, MCR_FLAGS, MVALID, VADR_R, MMU_VA, IVAR,
VIRTUELL, MMU_HIT , UPDATE, PROT_ERROR, CI, SEL_PTB1 );
input USER;
input READ;
input WRITE;
input RMW;
input [2:0] MCR_FLAGS;
input [31:0] MVALID;
input [31:12] VADR_R;
input [31:16] MMU_VA;
input [1:0] IVAR; // Invalidate Entry
output VIRTUELL; // only for Adress-Mux
output MMU_HIT;
output [31:0] UPDATE;
output reg PROT_ERROR; // if valid must suppress write in Write Buffer and cache
output CI,SEL_PTB1;
reg [15:0] maske;
wire adr_space,as_sorte,match,alles_ok;
wire [15:0] val_bits,as_bits;
wire ena_prot;
wire zugriff;
assign zugriff = READ | WRITE;
always @(VADR_R)
case (VADR_R[15:12])
4'h0 : maske = 16'h0001;
4'h1 : maske = 16'h0002;
4'h2 : maske = 16'h0004;
4'h3 : maske = 16'h0008;
4'h4 : maske = 16'h0010;
4'h5 : maske = 16'h0020;
4'h6 : maske = 16'h0040;
4'h7 : maske = 16'h0080;
4'h8 : maske = 16'h0100;
4'h9 : maske = 16'h0200;
4'hA : maske = 16'h0400;
4'hB : maske = 16'h0800;
4'hC : maske = 16'h1000;
4'hD : maske = 16'h2000;
4'hE : maske = 16'h4000;
4'hF : maske = 16'h8000;
endcase
assign VIRTUELL = USER ? MCR_FLAGS[0] : MCR_FLAGS[1];
assign adr_space = IVAR[1] ? IVAR[0] : (MCR_FLAGS[2] & USER); // adr_space = IVARx ? 1 or 0 : DualSpace & TU
assign as_sorte = ((MVALID[31:16] & maske) != 16'h0);
assign match = (VADR_R[31:20] == MMU_VA[31:20]) & (adr_space == as_sorte) & ((MVALID[15:0] & maske) != 16'h0000);
assign alles_ok = match & ( ~WRITE | MMU_VA[17] ) & ~PROT_ERROR; // Modified - Flag : reload the PTE
// if MMU_HIT = 0 then there is no Write-Buffer access abd no update of cache !
assign MMU_HIT = zugriff ? ( VIRTUELL ? alles_ok : 1'b1 ) : 1'b0 ; // MMU off : then always HIT
assign val_bits = IVAR[1] ? (MVALID[15:0] & (match ? ~maske : 16'hFFFF)) : (MVALID[15:0] | maske);
assign as_bits = IVAR[1] ? MVALID[31:16] : (adr_space ? (MVALID[31:16] | maske) : (MVALID[31:16] & ~maske));
assign UPDATE = {as_bits,val_bits};
assign ena_prot = zugriff & VIRTUELL & match;
// A Protection error must suppress write in WB and cache
always @(ena_prot or MMU_VA or USER or WRITE or RMW)
case ({ena_prot,MMU_VA[19:18]})
3'b100 : PROT_ERROR = USER | WRITE | RMW; // Only Supervisor READ
3'b101 : PROT_ERROR = USER; // no USER access
3'b110 : PROT_ERROR = USER & (WRITE | RMW); // USER only READ
default : PROT_ERROR = 1'b0;
endcase
assign CI = VIRTUELL & MMU_VA[16];
assign SEL_PTB1 = adr_space; // For PTE update
endmodule
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 5. CA_MATCH Cache tag match detector
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module CA_MATCH ( CVALID, IOSEL, ADDR, TAG0, TAG1, CFG, WRITE, MMU_HIT, CI, INVAL_L, KDET, ENDRAM, DC_ILO,
CA_HIT, CA_SET, UPDATE, IO_SPACE, USE_CA, WB_ACC, KILL );
input [23:0] CVALID;
input [3:0] IOSEL;
input [27:4] ADDR;
input [27:12] TAG0,TAG1;
input [1:0] CFG; // LDC , DC
input WRITE;
input MMU_HIT;
input CI;
input INVAL_L; // invalid cache line
input KDET;
input ENDRAM;
input DC_ILO; // CBITI/SBITI special case
output CA_HIT;
output CA_SET; // if no Hit then says SET where to store
output [23:0] UPDATE; // Update Information for CVALID memory
output IO_SPACE;
output USE_CA;
output WB_ACC;
output KILL;
reg [7:0] maske;
wire match_0,match_1;
wire valid_0,valid_1;
wire select;
wire clear;
wire [7:0] update_0,update_1,lastinfo;
wire sel_dram;
always @(ADDR)
case (ADDR[6:4])
3'h0 : maske = 8'h01;
3'h1 : maske = 8'h02;
3'h2 : maske = 8'h04;
3'h3 : maske = 8'h08;
3'h4 : maske = 8'h10;
3'h5 : maske = 8'h20;
3'h6 : maske = 8'h40;
3'h7 : maske = 8'h80;
endcase
assign valid_0 = (( CVALID[7:0] & maske) != 8'h00);
assign valid_1 = ((CVALID[15:8] & maske) != 8'h00);
assign match_0 = ( TAG0 == ADDR[27:12] ); // 4KB
assign match_1 = ( TAG1 == ADDR[27:12] ); // 4KB
assign CA_HIT = ((valid_0 & match_0) | (valid_1 & match_1)) & ~DC_ILO & CFG[0];
// which SET is written in cache miss ? If both are valid the last used is not taken
assign select = (valid_1 & valid_0) ? ~((CVALID[23:16] & maske) != 8'h00) : valid_0; // Last-used field = CVALID[23:16]
assign CA_SET = CA_HIT ? (valid_1 & match_1) : select;
assign clear = INVAL_L | KDET; // INVAL_L is from CINV
assign update_0 = CA_SET ? CVALID[7:0] : (clear ? (CVALID[7:0] & ~maske) : (CVALID[7:0] | maske));
assign update_1 = CA_SET ? (clear ? (CVALID[15:8] & ~maske) : (CVALID[15:8] | maske)) : CVALID[15:8];
assign lastinfo = CA_HIT ? (CA_SET ? (CVALID[23:16] | maske) : (CVALID[23:16] & ~maske)) : CVALID[23:16];
assign UPDATE = {lastinfo,update_1,update_0};
assign KILL = clear & CA_HIT & ~CFG[1]; // only if cache is not locked
assign sel_dram = (IOSEL == 4'b0000) & ENDRAM; // at the moment the first 256 MB of memory
assign IO_SPACE = ~sel_dram; // not DRAM or DRAM ist off
assign USE_CA = ~CI & ~DC_ILO & CFG[0] & ~CFG[1]; // CI ? ILO ? Cache on ? Locked Cache ?
assign WB_ACC = WRITE & MMU_HIT & sel_dram;
endmodule
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//
// 6. DCACHE_SM Data cache state machine
//
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module DCACHE_SM ( BCLK, BRESET, IO_SPACE, MDONE, IO_READY, MMU_HIT, CA_HIT, READ, WRITE, ZTEST, RMW, CAPDAT, VADR_R, IC_VA,
USE_CA, PTB_WR, PTB_SEL, SEL_PTB1, CPU_OUT, USER, PROT_ERROR, WB_ACC, ENWR, ADR_EQU, IC_PREQ, FILLRAM, ICTODC,
RWVAL, VIRTUELL, QWATWO,
DRAM_ACC, DRAM_WR, IO_ACC, IO_RD, IO_WR, PTE_MUX, PD_MUX, PKEEP, PTE_ADR, PTE_DAT, HIT_ALL, ACC_OK,
ABORT, PROTECT, IACC_STAT, ABO_LEVEL1, WR_MRAM, CUPDATE, AUX_DAT, NEW_PTB, PTB_ONE, MMU_DIN, IC_SIGS, KOMUX,
KDET, DMA_MUX, HLDA, RWVFLAG, PTE_STAT );
input BCLK;
input BRESET;
input IO_SPACE;
input MDONE; // Memory Done : feedback from DRAM Controller, BCLK aligned !
input IO_READY;
input MMU_HIT,CA_HIT;
input READ,WRITE,ZTEST,RMW;
input [31:0] CAPDAT;
input [31:12] VADR_R,IC_VA;
input USE_CA;
input PTB_WR,PTB_SEL;
input SEL_PTB1;
input [27:12] CPU_OUT; // used for PTB0/1
input USER;
input PROT_ERROR;
input WB_ACC;
input ENWR; // Enable WRITE from DRAM
input ADR_EQU;
input IC_PREQ;
input FILLRAM;
input [3:0] ICTODC; // multiple signals from ICACHE, especially DMA
input [1:0] RWVAL; // RDVAL+WRVAL Operation
input VIRTUELL; // for RDVAL/WRVAL
input QWATWO;
output reg DRAM_ACC,DRAM_WR;
output IO_ACC,IO_RD,IO_WR;
output PTE_MUX,PD_MUX,PKEEP;
output [27:0] PTE_ADR;
output [19:0] PTE_DAT;
output HIT_ALL;
output ACC_OK;
output ABORT,PROTECT;
output [3:1] IACC_STAT;
output ABO_LEVEL1;
output WR_MRAM;
output CUPDATE;
output AUX_DAT;
output reg NEW_PTB;
output reg PTB_ONE;
output [23:0] MMU_DIN;
output [1:0] IC_SIGS;
output KOMUX;
output KDET; // Signal for detection of collision
output DMA_MUX;
output HLDA; // active low
output RWVFLAG; // RDVAL/WRVAL result
output [1:0] PTE_STAT;
reg IO_WR,IO_RD;
reg [1:0] pl_dat;
reg [6:0] new_state;
reg [2:0] cap_dat; // only for analyse of timing
reg mem_done;
reg rd_done;
reg [2:0] pstate;
reg pte_run_wr;
reg [1:0] prot_level1;
reg card_flag;
reg [27:12] ptb0,ptb1;
reg write_ok;
reg icp_acc;
reg pte_modi;
reg [2:0] ko_state;
reg dma_run;
reg dma_kdet;
reg rwv_bit;
reg prot_i;
reg rd_rdy;
wire [27:12] ptb10;
wire [31:12] virtual_adr;
wire io_busy;
wire dram_go;
wire pte_sel;
wire pte_acc;
wire do_ca_rd,pte_go,do_ic_p;
wire valid,valid_a,refer,modi;
wire level1,level2;
wire rd_level2;
wire wr_req;
wire wr_dram;
wire wr_icmram;
wire rd_ende;
wire pte_dat_8;
wire pte_wr_sig;
wire run_dc;
wire kostart;
wire dma;
wire dma_go;
wire zugriff;
wire mmu_hit_i;
wire do_zt;
wire zt_ok;
wire [1:0] acc_level;
wire user_ptw,wr_ptw;
wire pte_puls;
always @(posedge BCLK) cap_dat <= CAPDAT[2:0];
// if USER not virtual then ZTEST is quickly done
assign zugriff = READ | WRITE | (ZTEST & VIRTUELL);
assign mmu_hit_i = MMU_HIT & ~ZTEST;
// WB_ACC is a successful WRITE access, ICTODC[0] is coherent Logik release : >=3 entries in FIFO
assign wr_req = WB_ACC & ((ENWR & ICTODC[0]) | (DRAM_WR & ADR_EQU)); // release done by DRAM signal ENWR
assign rd_ende = CA_HIT | rd_rdy; // CA_HIT only when Cache activ !
always @( zugriff // READ or WRITE or ZTEST , global control
or PROT_ERROR // must not be
//
or IO_SPACE // access of IO world
or io_busy // is access already running ?
//
or mmu_hit_i // Hit in MMU , now only a READ can happen
or READ
or wr_req
or rd_ende // Cache Hit
//
or DRAM_ACC // DRAM Access : shows an active state
or pte_acc // PTE access is running
//
or IC_PREQ // PTE Request from ICACHE
//
or dma // DMA Request
or dma_run ) // DMA running
// #_# #_# #_# #_#
casex ({zugriff,PROT_ERROR,IO_SPACE,io_busy,mmu_hit_i,READ,wr_req,rd_ende,DRAM_ACC,pte_acc,IC_PREQ,dma,dma_run})
// MMU Miss : PTE load from memory , valid too if WRITE and M=0
13'b10_xx_0xxx_x0_x_x0 : new_state = 7'b0001010; // start PTE access
// IO-Address selected : external access starts if not busy because of WRITE
13'b10_10_1xxx_x0_x_x0 : new_state = 7'b0000001;
// DRAM access : Cache Miss at READ :
13'b10_0x_1100_00_x_x0 : new_state = 7'b0010010;
// DRAM access : WRITE
13'b10_0x_101x_x0_x_x0 : new_state = 7'b0000100;
// PTE Request ICACHE , IO access with WRITE is stored - parallel DRAM access possible
13'b0x_xx_xxxx_x0_1_00 : new_state = 7'b0101010; // no access
13'b10_0x_1101_x0_1_x0 : new_state = 7'b0101010; // if successful READ a PTE access can happen in parallel
// DMA access. Attention : no IO-Write access in background and no ICACHE PTE access !
13'b0x_x0_xxxx_xx_0_10 : new_state = 7'b1000000; // DMA access is started
default : new_state = 7'b0;
endcase
assign IO_ACC = new_state[0]; // to load registers for data, addr und BE, signal one pulse
assign dram_go = new_state[1] | rd_level2 ;
assign wr_dram = new_state[2]; // pulse only
assign pte_go = new_state[3];
assign do_ca_rd = new_state[4];
assign do_ic_p = new_state[5];
assign dma_go = new_state[6];
// ZTEST logic is for the special case when a write access is crossing page boundaries
assign do_zt = ZTEST & ~icp_acc;
// 0 is pass , 1 is blocked. RWVAL[0] is 1 if WRVAL. Level 1 can only be blocked, otherwise ABORT or Level 2 is following.
always @(posedge BCLK) if (mem_done) rwv_bit <= level2 ? ~(cap_dat[2] & (~RWVAL[0] | cap_dat[1])) : 1'b1;
assign RWVFLAG = VIRTUELL & rwv_bit;
assign zt_ok = mem_done & (RWVAL[1] ? (~cap_dat[2] | (RWVAL[0] & ~cap_dat[1]) | level2) // Level 2 always ok
: (cap_dat[0] & ~prot_i & level2) ); // "normal" access
// PTE access logic, normal state machine
// Updates to the PTEs are normal WRITE request to DRAM, therefore no MDONE at Write
assign modi = ~CAPDAT[8] & WRITE & write_ok & ~icp_acc; // is "1" if the Modified Bit must be set
assign refer = CAPDAT[7] | do_zt; // Assumption "R" Bit is set if RDVAL/WRVAL and page border test
assign valid = (do_zt & RWVAL[1]) ? (cap_dat[2] & (cap_dat[1] | ~RWVAL[0]) & cap_dat[0] & level1)
: (cap_dat[0] & ~prot_i);
always @(posedge BCLK) mem_done <= MDONE & pte_acc;
always @(posedge BCLK or negedge BRESET)
if (!BRESET) pstate <= 3'h0;
else
casex ({pte_go,mem_done,valid,refer,modi,pte_run_wr,pstate})
9'b0x_xxxx_000 : pstate <= 3'd0; // nothing to do
9'b1x_xxxx_000 : pstate <= 3'd4; // start
9'bx0_xxxx_100 : pstate <= 3'd4; // wait for Level 1
9'bx1_0xxx_100 : pstate <= 3'd0; // THAT'S ABORT !
9'bx1_11xx_100 : pstate <= 3'd6; // PTE Level 1 was referenced , next is Level 2
9'bx1_10xx_100 : pstate <= 3'd5; // for writing of modified Level 1 : R=1
9'bxx_xxx0_101 : pstate <= 3'd5; // write must wait
9'bxx_xxx1_101 : pstate <= 3'd6; // one wait cycle
9'bx0_xxxx_110 : pstate <= 3'd6; // wait for Level 2
9'bx1_0xxx_110 : pstate <= 3'd0; // THAT'S ABORT !
9'bx1_10xx_110 : pstate <= 3'd7; // Update neccesary : R=0
9'bx1_110x_110 : pstate <= 3'd0; // all ok - end
9'bx1_111x_110 : pstate <= 3'd7; // Update neccesary : M=0
9'bxx_xxx0_111 : pstate <= 3'd7; // write must wait
9'bxx_xxx1_111 : pstate <= 3'd0; // continues to end of DRAM write
default : pstate <= 3'd0;
endcase
assign pte_acc = pstate[2];
assign level1 = ~pstate[1];
assign level2 = pstate[1];
assign valid_a = (ZTEST & RWVAL[1]) ? (cap_dat[2] & (cap_dat[1] | ~RWVAL[0]) & ~cap_dat[0] & level1)
: ~cap_dat[0]; // not do_zt because of icp_acc in ABORT
assign ABORT = mem_done & valid_a & ~icp_acc;
assign PROTECT = ((mem_done & prot_i & ~icp_acc) | PROT_ERROR) & ~(ZTEST & RWVAL[1]); // no Protection-Error at RDVAL/WRVAL
assign IACC_STAT[1] = mem_done & ~cap_dat[0] & icp_acc;
assign IACC_STAT[2] = level1;
assign IACC_STAT[3] = mem_done & prot_i & icp_acc;
assign ABO_LEVEL1 = level1; // is stored in case of ABORT in ADDR_UNIT
assign rd_level2 = (pstate == 3'd5) | (mem_done & (pstate == 3'd4) & refer & valid);
assign WR_MRAM = mem_done & (pstate == 3'd6) & valid & ~icp_acc & ~ZTEST;
assign wr_icmram = mem_done & (pstate == 3'd6) & valid & icp_acc;
// Signals to the Instruction Cache
// pte_acc combined with icp_acc for STATISTIK.
assign IC_SIGS = {(pte_acc & icp_acc),wr_icmram};
assign PTE_MUX = pte_go | (pte_acc & ~pstate[1]);
assign pte_puls = mem_done & pte_acc & ~pstate[1];
assign PTE_STAT = {(pte_puls & icp_acc),(pte_puls & ~icp_acc)}; // only for statistic
assign PD_MUX = ((pstate == 3'd4) & mem_done & valid & ~refer) // switch data-MUX, write level 1 too
| ((pstate == 3'd6) & mem_done & valid & (~refer | modi)) // write level 2
| (((pstate == 3'd5) | (pstate == 3'd7)) & ~pte_run_wr);
assign pte_wr_sig = ENWR & PD_MUX;
always @(posedge BCLK) pte_run_wr <= pte_wr_sig; // Ok-Signal for pstate State-machine
assign PKEEP = (pstate == 3'd6) | ((pstate == 3'd7) & ~pte_run_wr); // keep the DRAM address
// If there is a PTE still in the data cache it must be deleted. If MMU Bits are set by the pte engine a following
// READ would deliver wrong data if cache hit. Therefore access of the Tags.
always @(posedge BCLK or negedge BRESET)
if (!BRESET) ko_state <= 3'b000;
else
casex ({kostart,ko_state})
4'b0_000 : ko_state <= 3'b000;
4'b1_000 : ko_state <= 3'b110;
4'bx_110 : ko_state <= 3'b111;
4'bx_111 : ko_state <= 3'b100;
4'bx_100 : ko_state <= 3'b000;
default : ko_state <= 3'b000;
endcase
assign kostart = pte_go | rd_level2;
// ko_state[2] suppresses ACC_OK at READ
assign run_dc = (~ko_state[2] | QWATWO) & ~dma_run; // Bugfix of 7.10.2015
assign KOMUX = ko_state[1] | DMA_MUX;
assign KDET = ko_state[0] | dma_kdet;
assign HIT_ALL = MMU_HIT & CA_HIT & run_dc & ~pte_acc; // for Update "Last-Set" , MMU_HIT contains ZUGRIFF
always @(posedge BCLK or negedge BRESET)
if (!BRESET) card_flag <= 1'b0;
else card_flag <= (do_ca_rd & ~rd_rdy) | (card_flag & ~MDONE);
assign CUPDATE = card_flag & USE_CA & MDONE;
always @(posedge BCLK) rd_rdy <= card_flag & MDONE;
// The cache RAM can not provide fast enough the data after an Update. In this case a secondary data path is activated
assign AUX_DAT = rd_rdy;
// DRAM interface :
always @(posedge BCLK) DRAM_WR <= wr_dram | pte_wr_sig; // pulse
always @(posedge BCLK) if (dram_go) DRAM_ACC <= 1'b1;
else
DRAM_ACC <= DRAM_ACC & ~MDONE & BRESET;
// IO interface :
always @(posedge BCLK)
begin
if (IO_ACC) IO_RD <= READ; else IO_RD <= IO_RD & ~IO_READY & BRESET;
if (IO_ACC) IO_WR <= WRITE; else IO_WR <= IO_WR & ~IO_READY & BRESET;
end
assign io_busy = IO_RD | IO_WR | rd_done; // access is gone in next clock cycle, therefore blocked with "rd_done"
always @(posedge BCLK) rd_done <= IO_RD & IO_READY; // For READ one clock later for data to come through
assign dma = ICTODC[2]; // external request HOLD after FF in ICACHE
always @(posedge BCLK) dma_run <= (dma_go | (dma_run & dma)) & BRESET; // stops the data access until HOLD becomes inactive
assign HLDA = ~(ICTODC[1] & dma_run); // Signal for system that the CPU has stopped accesses
always @(posedge BCLK) dma_kdet <= FILLRAM;
assign DMA_MUX = FILLRAM | dma_kdet;
// global feedback to ADDR_UNIT, early feedback to Op-Dec : you can continue
assign ACC_OK = ZTEST ? (~VIRTUELL | zt_ok)
: (IO_SPACE ? ((IO_ACC & WRITE) | rd_done) : (wr_dram | (READ & MMU_HIT & rd_ende & run_dc)) );
// PTB1 and PTB0
always @(posedge BCLK) if (PTB_WR && !PTB_SEL) ptb0 <= CPU_OUT[27:12];
always @(posedge BCLK) if (PTB_WR && PTB_SEL) ptb1 <= CPU_OUT[27:12];
always @(posedge BCLK) NEW_PTB <= PTB_WR; // to MMU Update Block
always @(posedge BCLK) if (PTB_WR) PTB_ONE <= PTB_SEL;
assign ptb10 = SEL_PTB1 ? ptb1 : ptb0;
// Address multiplex between ICACHE=1 and DCACHE=0 :
always @(posedge BCLK) if (pte_go) icp_acc <= do_ic_p;
assign pte_sel = pte_go ? do_ic_p : icp_acc;
assign virtual_adr = pte_sel ? IC_VA : VADR_R;
// The 2 Address-LSB's : no full access : USE_CA = 0
assign PTE_ADR = rd_level2 ? {CAPDAT[27:12],virtual_adr[21:12],2'b00} : {ptb10,virtual_adr[31:22],2'b00};
// PTE_DAT[8] is used for update of MMU_RAM.
assign pte_dat_8 = (level2 & WRITE & write_ok & ~icp_acc) | CAPDAT[8];
always @(posedge BCLK) pte_modi = pte_dat_8;
assign PTE_DAT = {4'h3,CAPDAT[15:9],pte_modi,1'b1,CAPDAT[6:0]}; // the top 4 bits are Byte-Enable
// The data for the MMU-RAM : 24 Bits , [6]=Cache Inhibit
assign MMU_DIN = {pl_dat,pte_dat_8,CAPDAT[6],CAPDAT[31:12]};
// Protection field
always @(posedge BCLK) if (mem_done && (pstate[2:0] == 3'd4)) prot_level1 <= cap_dat[2:1];
always @(prot_level1 or cap_dat)
casex ({prot_level1,cap_dat[2]})
3'b11_x : pl_dat = cap_dat[2:1];
3'b10_1 : pl_dat = 2'b10;
3'b10_0 : pl_dat = cap_dat[2:1];
3'b01_1 : pl_dat = 2'b01;
3'b01_0 : pl_dat = cap_dat[2:1];
3'b00_x : pl_dat = 2'b00;
endcase
always @(USER or pl_dat) // is used if no PTE update is neccesary for M-Bit if writing is not allowed
casex ({USER,pl_dat})
3'b1_11 : write_ok = 1'b1;
3'b0_1x : write_ok = 1'b1;
3'b0_01 : write_ok = 1'b1;
default : write_ok = 1'b0;
endcase
assign acc_level = level2 ? pl_dat : cap_dat[2:1];
assign user_ptw = icp_acc ? ICTODC[3] : USER;
assign wr_ptw = ~icp_acc & (WRITE | RMW | (ZTEST & ~RWVAL[1])); // only data cache can write
always @(acc_level or user_ptw or wr_ptw)
case (acc_level)
2'b00 : prot_i = user_ptw | wr_ptw;
2'b01 : prot_i = user_ptw;
2'b10 : prot_i = user_ptw & wr_ptw;
2'b11 : prot_i = 1'b0;
endcase
endmodule
|
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
recFNToFN#(parameter expWidth = 3, parameter sigWidth = 3) (
input [(expWidth + sigWidth):0] in,
output [(expWidth + sigWidth - 1):0] out
);
`include "HardFloat_localFuncs.vi"
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
localparam [expWidth:0] minNormExp = (1<<(expWidth - 1)) + 2;
localparam normDistWidth = clog2(sigWidth);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire isNaN, isInf, isZero, sign;
wire signed [(expWidth + 1):0] sExp;
wire [sigWidth:0] sig;
recFNToRawFN#(expWidth, sigWidth)
recFNToRawFN(in, isNaN, isInf, isZero, sign, sExp, sig);
// FIX provided by John Hauser.
// if the input is recoded infinity with x in sig and exp fields,
// isSubnormal also turns x, and fractOut becomes x.
// wire isSubnormal = (sExp < minNormExp);
wire isSubnormal =
((sExp>>(expWidth - 2) == 'b010) && (sExp[(expWidth - 3):0] <= 1))
|| (sExp>>(expWidth - 1) == 'b00);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire [(normDistWidth - 1):0] denormShiftDist = minNormExp - 1 - sExp;
wire [(expWidth - 1):0] expOut =
(isSubnormal ? 0 : sExp - minNormExp + 1)
| (isNaN || isInf ? {expWidth{1'b1}} : 0);
wire [(sigWidth - 2):0] fractOut =
isSubnormal ? (sig>>1)>>denormShiftDist : isInf ? 0 : sig;
assign out = {sign, expOut, fractOut};
endmodule
|
//--------------------------------------------------------------------------------
//
// gray.v
// Copyright (C) 2011 Ian Davis
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details:
// http://www.dangerousprototypes.com/ols
// http://www.gadgetfactory.net/gf/project/butterflylogic
// http://www.mygizmos.org/ols
//
// These are verilog functions, called from within always blocks elsewhere.
// They compute the "gray" encoding of a binary value. Gray counts increment
// by changing only a single bit, instead of possibly multiple bits as a binary
// counter would. ie:
//
// Binary Gray
// 000 000
// 001 001
// 010 011
// 011 010
// 100 110
// 101 111
// 110 101
// 111 100
//
// The above 3-bit binary count can flip as many as 3-bits simultaneously (on
// wraparound back to zero). The gray counter counter however, never flips
// more than one.
//
//--------------------------------------------------------------------------------
//
// The gray counter increment pattern is VERY valuable when moving multi-bit
// values across asynchronous boundaries -- two clock domains with no relation
// to one another. The async-fifo in this design uses them specifically for that.
//
// There is no way to guarantee a raw multi-bit -binary- value can be synchronized
// across an async boundary. The bits could & would arrive in any order, causing
// the receiving logic to become confused. Bad medicine.
//
// The gray counter however, only ever syncs one bit no matter what. Thus no
// confused receiving logic. A good thing.
//
// One small detail. There must -never- be any combinatorial logic on the
// actual async boundary. ie: flop whatever in the source clock, flop it
// again (more than once) in the destination clock.
//
//--------------------------------------------------------------------------------
//
// Lastly, these functions are parameterizable. Means they can be used for any
// binary width needed by changing the "WIDTH" parameter (which must be
// declared in the calling module). ie:
//
// // Create 42 bit width instance of a binary to gray count convertor...
// module xyz(a,b);
// parameter WIDTH = 42;
// input [WIDTH-1:0] a;
// output [WIDTH-1:0] b;
// `include "gray.v"
// reg [WIDTH-1:0] b;
// always @*
// begin
// b = gray2bin(a);
// end
// endmodule
//
//--------------------------------------------------------------------------------
//
function [WIDTH-1:0] gray2bin;
input [WIDTH-1:0] gray;
integer i;
begin
// 5bit example: gray2bin = {gray[4], ^gray[4:3], ^gray[4:2], ^gray[4:1], ^gray[4:0]}
gray2bin[WIDTH-1] = gray[WIDTH-1];
for (i=WIDTH-2; i>=0; i=i-1) gray2bin[i] = gray2bin[i+1]^gray[i];
end
endfunction
function [WIDTH-1:0] bin2gray;
input [WIDTH-1:0] bin;
integer i;
begin
// 5bit example: bin2gray = {bin[4], ^bin[4:3], ^bin[3:2], ^bin[2:1], ^bin[1:0]}
for (i=0; i<WIDTH-1; i=i+1) bin2gray[i] = bin[i+1] ^ bin[i];
bin2gray[WIDTH-1] = bin[WIDTH-1];
end
endfunction
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (win64) Build 1577090 Thu Jun 2 16:32:40 MDT 2016
// Date : Mon Sep 12 02:36:37 2016
// Host : RDS1 running 64-bit major release (build 9200)
// Command : write_verilog -mode timesim -nolib -sdf_anno true -force -file
// C:/Users/jsequeira/Proyectos/project_1.xpr/project_1/project_1.sim/sim_1/synth/timing/Testbench_FPU_Add_Subt_time_synth.v
// Design : FPU_Add_Subtract_Function
// Purpose : This verilog netlist is a timing simulation representation of the design and should not be modified or
// synthesized. Please ensure that this netlist is used with the corresponding SDF file.
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
`define XIL_TIMING
module Add_Subt
(add_overflow_flag,
D,
\Q_reg[18] ,
\Q_reg[16] ,
\Q_reg[17] ,
\Q_reg[15] ,
Q,
\Q_reg[4] ,
S,
\Q_reg[7] ,
\Q_reg[11] ,
\Q_reg[15]_0 ,
\Q_reg[19] ,
\Q_reg[23] ,
\Q_reg[0] ,
E,
O,
CLK,
AR,
FSM_barrel_shifter_B_S,
\Q_reg[2] ,
\Q_reg[1] ,
\Q_reg[0]_0 ,
FSM_selector_C,
FSM_barrel_shifter_L_R,
\Q_reg[0]_1 ,
\Q_reg[0]_2 ,
FSM_selector_B,
\Q_reg[0]_3 ,
\Q_reg[22] ,
\Q_reg[31] ,
\Q_reg[31]_0 ,
intAS,
\Q_reg[31]_1 ,
\Q_reg[25] ,
FSM_selector_D,
\Q_reg[22]_0 );
output add_overflow_flag;
output [20:0]D;
output \Q_reg[18] ;
output \Q_reg[16] ;
output \Q_reg[17] ;
output \Q_reg[15] ;
output [1:0]Q;
output [4:0]\Q_reg[4] ;
output [3:0]S;
output [3:0]\Q_reg[7] ;
output [3:0]\Q_reg[11] ;
output [3:0]\Q_reg[15]_0 ;
output [3:0]\Q_reg[19] ;
output [3:0]\Q_reg[23] ;
output [1:0]\Q_reg[0] ;
input [0:0]E;
input [2:0]O;
input CLK;
input [0:0]AR;
input FSM_barrel_shifter_B_S;
input \Q_reg[2] ;
input \Q_reg[1] ;
input \Q_reg[0]_0 ;
input FSM_selector_C;
input FSM_barrel_shifter_L_R;
input \Q_reg[0]_1 ;
input [0:0]\Q_reg[0]_2 ;
input [1:0]FSM_selector_B;
input [0:0]\Q_reg[0]_3 ;
input [22:0]\Q_reg[22] ;
input [23:0]\Q_reg[31] ;
input [0:0]\Q_reg[31]_0 ;
input intAS;
input [0:0]\Q_reg[31]_1 ;
input [25:0]\Q_reg[25] ;
input FSM_selector_D;
input [22:0]\Q_reg[22]_0 ;
wire [0:0]AR;
wire CLK;
wire [20:0]D;
wire [0:0]E;
wire FSM_barrel_shifter_B_S;
wire FSM_barrel_shifter_L_R;
wire [1:0]FSM_selector_B;
wire FSM_selector_C;
wire FSM_selector_D;
wire [2:0]O;
wire [1:0]Q;
wire [1:0]\Q_reg[0] ;
wire \Q_reg[0]_0 ;
wire \Q_reg[0]_1 ;
wire [0:0]\Q_reg[0]_2 ;
wire [0:0]\Q_reg[0]_3 ;
wire [3:0]\Q_reg[11] ;
wire \Q_reg[15] ;
wire [3:0]\Q_reg[15]_0 ;
wire \Q_reg[16] ;
wire \Q_reg[17] ;
wire \Q_reg[18] ;
wire [3:0]\Q_reg[19] ;
wire \Q_reg[1] ;
wire [22:0]\Q_reg[22] ;
wire [22:0]\Q_reg[22]_0 ;
wire [3:0]\Q_reg[23] ;
wire [25:0]\Q_reg[25] ;
wire \Q_reg[2] ;
wire [23:0]\Q_reg[31] ;
wire [0:0]\Q_reg[31]_0 ;
wire [0:0]\Q_reg[31]_1 ;
wire [4:0]\Q_reg[4] ;
wire [3:0]\Q_reg[7] ;
wire [3:0]S;
wire add_overflow_flag;
wire intAS;
RegisterAdd__parameterized8 Add_Subt_Result
(.AR(AR),
.CLK(CLK),
.D(D),
.E(E),
.FSM_barrel_shifter_B_S(FSM_barrel_shifter_B_S),
.FSM_barrel_shifter_L_R(FSM_barrel_shifter_L_R),
.FSM_selector_B(FSM_selector_B),
.FSM_selector_C(FSM_selector_C),
.Q(Q),
.\Q_reg[0]_0 (\Q_reg[0]_0 ),
.\Q_reg[0]_1 (\Q_reg[0]_1 ),
.\Q_reg[0]_2 (\Q_reg[0]_2 ),
.\Q_reg[0]_3 (\Q_reg[0]_3 ),
.\Q_reg[15]_0 (\Q_reg[15] ),
.\Q_reg[16]_0 (\Q_reg[16] ),
.\Q_reg[17]_0 (\Q_reg[17] ),
.\Q_reg[18]_0 (\Q_reg[18] ),
.\Q_reg[1]_0 (\Q_reg[1] ),
.\Q_reg[22]_0 (\Q_reg[22] ),
.\Q_reg[2]_0 (\Q_reg[2] ),
.\Q_reg[31] ({O[1:0],\Q_reg[31] }),
.\Q_reg[4]_0 (\Q_reg[4] ));
RegisterAdd_6 Add_overflow_Result
(.AR(AR),
.CLK(CLK),
.E(E),
.O(O[2]),
.add_overflow_flag(add_overflow_flag));
add_sub_carry_out__parameterized0 Sgf_AS
(.FSM_selector_D(FSM_selector_D),
.\Q_reg[0] (\Q_reg[0] ),
.\Q_reg[11] (\Q_reg[11] ),
.\Q_reg[15] (\Q_reg[15]_0 ),
.\Q_reg[19] (\Q_reg[19] ),
.\Q_reg[22] (\Q_reg[22]_0 ),
.\Q_reg[23] (\Q_reg[23] ),
.\Q_reg[25] (\Q_reg[25] ),
.\Q_reg[31] (\Q_reg[31]_0 ),
.\Q_reg[31]_0 (\Q_reg[31]_1 ),
.\Q_reg[7] (\Q_reg[7] ),
.S(S),
.intAS(intAS));
endmodule
module Barrel_Shifter
(\Q_reg[16] ,
Q,
\Q_reg[25] ,
\Q_reg[17] ,
\Q_reg[24] ,
\Q_reg[18] ,
\Q_reg[23] ,
\Q_reg[19] ,
\Q_reg[22] ,
\Q_reg[20] ,
\Q_reg[21] ,
round_flag,
\Q_reg[0] ,
D,
FSM_barrel_shifter_L_R,
\Q_reg[16]_0 ,
FSM_barrel_shifter_B_S,
\Q_reg[4] ,
\Q_reg[3] ,
\Q_reg[17]_0 ,
r_mode_IBUF,
sign_final_result,
E,
CLK,
AR,
\Q_reg[2] ,
\FSM_sequential_state_reg_reg[3] );
output \Q_reg[16] ;
output [15:0]Q;
output \Q_reg[25] ;
output \Q_reg[17] ;
output \Q_reg[24] ;
output \Q_reg[18] ;
output \Q_reg[23] ;
output \Q_reg[19] ;
output \Q_reg[22] ;
output \Q_reg[20] ;
output \Q_reg[21] ;
output round_flag;
output [25:0]\Q_reg[0] ;
input [15:0]D;
input FSM_barrel_shifter_L_R;
input \Q_reg[16]_0 ;
input FSM_barrel_shifter_B_S;
input \Q_reg[4] ;
input \Q_reg[3] ;
input \Q_reg[17]_0 ;
input [1:0]r_mode_IBUF;
input sign_final_result;
input [0:0]E;
input CLK;
input [0:0]AR;
input [25:0]\Q_reg[2] ;
input [0:0]\FSM_sequential_state_reg_reg[3] ;
wire [0:0]AR;
wire CLK;
wire [15:0]D;
wire [25:16]Data_Reg;
wire [0:0]E;
wire FSM_barrel_shifter_B_S;
wire FSM_barrel_shifter_L_R;
wire [0:0]\FSM_sequential_state_reg_reg[3] ;
wire [15:0]Q;
wire [25:0]\Q_reg[0] ;
wire \Q_reg[16] ;
wire \Q_reg[16]_0 ;
wire \Q_reg[17] ;
wire \Q_reg[17]_0 ;
wire \Q_reg[18] ;
wire \Q_reg[19] ;
wire \Q_reg[20] ;
wire \Q_reg[21] ;
wire \Q_reg[22] ;
wire \Q_reg[23] ;
wire \Q_reg[24] ;
wire \Q_reg[25] ;
wire [25:0]\Q_reg[2] ;
wire \Q_reg[3] ;
wire \Q_reg[4] ;
wire [1:0]r_mode_IBUF;
wire round_flag;
wire sign_final_result;
Mux_Array Mux_Array
(.CLK(CLK),
.D(Data_Reg),
.FSM_barrel_shifter_B_S(FSM_barrel_shifter_B_S),
.FSM_barrel_shifter_L_R(FSM_barrel_shifter_L_R),
.\FSM_sequential_state_reg_reg[3] (\FSM_sequential_state_reg_reg[3] ),
.Q(Q),
.\Q_reg[16] (\Q_reg[16] ),
.\Q_reg[16]_0 (\Q_reg[16]_0 ),
.\Q_reg[17] (\Q_reg[17] ),
.\Q_reg[17]_0 (\Q_reg[17]_0 ),
.\Q_reg[18] (\Q_reg[18] ),
.\Q_reg[19] (\Q_reg[19] ),
.\Q_reg[20] (\Q_reg[20] ),
.\Q_reg[21] (\Q_reg[21] ),
.\Q_reg[22] (\Q_reg[22] ),
.\Q_reg[23] (\Q_reg[23] ),
.\Q_reg[24] (\Q_reg[24] ),
.\Q_reg[25] (\Q_reg[25] ),
.\Q_reg[2] (\Q_reg[2] ),
.\Q_reg[3] (\Q_reg[3] ),
.\Q_reg[4] (\Q_reg[4] ));
RegisterAdd__parameterized7 Output_Reg
(.AR(AR),
.CLK(CLK),
.D({Data_Reg,D}),
.E(E),
.\Q_reg[0]_0 (\Q_reg[0] ),
.r_mode_IBUF(r_mode_IBUF),
.round_flag(round_flag),
.sign_final_result(sign_final_result));
endmodule
module Comparator
(CO,
\Q_reg[0] ,
zero_flag,
DI,
S,
\Q_reg[15] ,
\Q_reg[15]_0 ,
\Q_reg[23] ,
\Q_reg[23]_0 ,
\Q_reg[30] ,
\Q_reg[30]_0 ,
\Q_reg[10] ,
\Q_reg[22] ,
\Q_reg[30]_1 ,
Q,
\Q_reg[0]_0 ,
\Q_reg[31] );
output [0:0]CO;
output [0:0]\Q_reg[0] ;
output zero_flag;
input [3:0]DI;
input [3:0]S;
input [3:0]\Q_reg[15] ;
input [3:0]\Q_reg[15]_0 ;
input [3:0]\Q_reg[23] ;
input [3:0]\Q_reg[23]_0 ;
input [3:0]\Q_reg[30] ;
input [3:0]\Q_reg[30]_0 ;
input [3:0]\Q_reg[10] ;
input [3:0]\Q_reg[22] ;
input [2:0]\Q_reg[30]_1 ;
input [0:0]Q;
input \Q_reg[0]_0 ;
input [0:0]\Q_reg[31] ;
wire [0:0]CO;
wire [3:0]DI;
wire [0:0]Q;
wire [0:0]\Q_reg[0] ;
wire \Q_reg[0]_0 ;
wire [3:0]\Q_reg[10] ;
wire [3:0]\Q_reg[15] ;
wire [3:0]\Q_reg[15]_0 ;
wire [3:0]\Q_reg[22] ;
wire [3:0]\Q_reg[23] ;
wire [3:0]\Q_reg[23]_0 ;
wire [3:0]\Q_reg[30] ;
wire [3:0]\Q_reg[30]_0 ;
wire [2:0]\Q_reg[30]_1 ;
wire [0:0]\Q_reg[31] ;
wire [3:0]S;
wire eqXY_o_carry__0_n_0;
wire eqXY_o_carry__0_n_1;
wire eqXY_o_carry__0_n_2;
wire eqXY_o_carry__0_n_3;
wire eqXY_o_carry__1_n_2;
wire eqXY_o_carry__1_n_3;
wire eqXY_o_carry_n_0;
wire eqXY_o_carry_n_1;
wire eqXY_o_carry_n_2;
wire eqXY_o_carry_n_3;
wire gtXY_o_carry__0_n_0;
wire gtXY_o_carry__0_n_1;
wire gtXY_o_carry__0_n_2;
wire gtXY_o_carry__0_n_3;
wire gtXY_o_carry__1_n_0;
wire gtXY_o_carry__1_n_1;
wire gtXY_o_carry__1_n_2;
wire gtXY_o_carry__1_n_3;
wire gtXY_o_carry__2_n_1;
wire gtXY_o_carry__2_n_2;
wire gtXY_o_carry__2_n_3;
wire gtXY_o_carry_n_0;
wire gtXY_o_carry_n_1;
wire gtXY_o_carry_n_2;
wire gtXY_o_carry_n_3;
wire zero_flag;
wire [3:0]NLW_eqXY_o_carry_O_UNCONNECTED;
wire [3:0]NLW_eqXY_o_carry__0_O_UNCONNECTED;
wire [3:3]NLW_eqXY_o_carry__1_CO_UNCONNECTED;
wire [3:0]NLW_eqXY_o_carry__1_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_carry_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_carry__0_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_carry__1_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_carry__2_O_UNCONNECTED;
LUT4 #(
.INIT(16'h8228))
\FSM_sequential_state_reg[2]_i_3
(.I0(\Q_reg[0] ),
.I1(Q),
.I2(\Q_reg[0]_0 ),
.I3(\Q_reg[31] ),
.O(zero_flag));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 eqXY_o_carry
(.CI(1'b0),
.CO({eqXY_o_carry_n_0,eqXY_o_carry_n_1,eqXY_o_carry_n_2,eqXY_o_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_eqXY_o_carry_O_UNCONNECTED[3:0]),
.S(\Q_reg[10] ));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 eqXY_o_carry__0
(.CI(eqXY_o_carry_n_0),
.CO({eqXY_o_carry__0_n_0,eqXY_o_carry__0_n_1,eqXY_o_carry__0_n_2,eqXY_o_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_eqXY_o_carry__0_O_UNCONNECTED[3:0]),
.S(\Q_reg[22] ));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 eqXY_o_carry__1
(.CI(eqXY_o_carry__0_n_0),
.CO({NLW_eqXY_o_carry__1_CO_UNCONNECTED[3],\Q_reg[0] ,eqXY_o_carry__1_n_2,eqXY_o_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_eqXY_o_carry__1_O_UNCONNECTED[3:0]),
.S({1'b0,\Q_reg[30]_1 }));
CARRY4 gtXY_o_carry
(.CI(1'b0),
.CO({gtXY_o_carry_n_0,gtXY_o_carry_n_1,gtXY_o_carry_n_2,gtXY_o_carry_n_3}),
.CYINIT(1'b0),
.DI(DI),
.O(NLW_gtXY_o_carry_O_UNCONNECTED[3:0]),
.S(S));
CARRY4 gtXY_o_carry__0
(.CI(gtXY_o_carry_n_0),
.CO({gtXY_o_carry__0_n_0,gtXY_o_carry__0_n_1,gtXY_o_carry__0_n_2,gtXY_o_carry__0_n_3}),
.CYINIT(1'b0),
.DI(\Q_reg[15] ),
.O(NLW_gtXY_o_carry__0_O_UNCONNECTED[3:0]),
.S(\Q_reg[15]_0 ));
CARRY4 gtXY_o_carry__1
(.CI(gtXY_o_carry__0_n_0),
.CO({gtXY_o_carry__1_n_0,gtXY_o_carry__1_n_1,gtXY_o_carry__1_n_2,gtXY_o_carry__1_n_3}),
.CYINIT(1'b0),
.DI(\Q_reg[23] ),
.O(NLW_gtXY_o_carry__1_O_UNCONNECTED[3:0]),
.S(\Q_reg[23]_0 ));
CARRY4 gtXY_o_carry__2
(.CI(gtXY_o_carry__1_n_0),
.CO({CO,gtXY_o_carry__2_n_1,gtXY_o_carry__2_n_2,gtXY_o_carry__2_n_3}),
.CYINIT(1'b0),
.DI(\Q_reg[30] ),
.O(NLW_gtXY_o_carry__2_O_UNCONNECTED[3:0]),
.S(\Q_reg[30]_0 ));
endmodule
module Exp_Operation
(overflow_flag_OBUF,
underflow_flag_OBUF,
D,
Q,
Data_A,
\Q_reg[0] ,
S,
\Q_reg[3] ,
E,
CLK,
AR,
\Q_reg[0]_0 ,
sign_final_result,
\Q_reg[24] ,
\Q_reg[0]_1 ,
\Q_reg[30] ,
O,
\Q_reg[1] ,
\Q_reg[30]_0 ,
\Q_reg[1]_0 ,
FSM_exp_operation_A_S,
DI,
\Q_reg[26] ,
FSM_selector_B,
\Q_reg[0]_2 );
output overflow_flag_OBUF;
output underflow_flag_OBUF;
output [31:0]D;
output [4:0]Q;
output [0:0]Data_A;
output \Q_reg[0] ;
output [3:0]S;
output [3:0]\Q_reg[3] ;
input [0:0]E;
input CLK;
input [0:0]AR;
input \Q_reg[0]_0 ;
input sign_final_result;
input [22:0]\Q_reg[24] ;
input \Q_reg[0]_1 ;
input [7:0]\Q_reg[30] ;
input [0:0]O;
input [7:0]\Q_reg[1] ;
input [3:0]\Q_reg[30]_0 ;
input \Q_reg[1]_0 ;
input FSM_exp_operation_A_S;
input [0:0]DI;
input [2:0]\Q_reg[26] ;
input [1:0]FSM_selector_B;
input [0:0]\Q_reg[0]_2 ;
wire [0:0]AR;
wire CLK;
wire [31:0]D;
wire [0:0]DI;
wire [0:0]Data_A;
wire [0:0]E;
wire FSM_exp_operation_A_S;
wire [1:0]FSM_selector_B;
wire [0:0]O;
wire [4:0]Q;
wire \Q_reg[0] ;
wire \Q_reg[0]_0 ;
wire \Q_reg[0]_1 ;
wire [0:0]\Q_reg[0]_2 ;
wire [7:0]\Q_reg[1] ;
wire \Q_reg[1]_0 ;
wire [22:0]\Q_reg[24] ;
wire [2:0]\Q_reg[26] ;
wire [7:0]\Q_reg[30] ;
wire [3:0]\Q_reg[30]_0 ;
wire [3:0]\Q_reg[3] ;
wire [3:0]S;
wire exp_result_n_10;
wire exp_result_n_8;
wire exp_result_n_9;
wire overflow_flag_OBUF;
wire sign_final_result;
wire underflow_flag_OBUF;
RegisterAdd_4 Overflow
(.AR(AR),
.CLK(CLK),
.D(D[22:0]),
.E(E),
.O(O),
.\Q_reg[0]_0 (underflow_flag_OBUF),
.\Q_reg[1] (\Q_reg[1] ),
.\Q_reg[22] (overflow_flag_OBUF),
.\Q_reg[24] (\Q_reg[24] ));
RegisterAdd_5 Underflow
(.AR(AR),
.CLK(CLK),
.D(D[31]),
.O(O),
.\Q_reg[0]_0 (\Q_reg[0] ),
.\Q_reg[0]_1 (\Q_reg[0]_0 ),
.\Q_reg[0]_2 (overflow_flag_OBUF),
.\Q_reg[1] ({\Q_reg[1] [7],\Q_reg[1] [4],\Q_reg[1] [2:0]}),
.\Q_reg[31] (underflow_flag_OBUF),
.sign_final_result(sign_final_result));
add_sub_carry_out exp_add_subt
(.DI(DI),
.FSM_exp_operation_A_S(FSM_exp_operation_A_S),
.FSM_selector_B(FSM_selector_B),
.Q({exp_result_n_8,exp_result_n_9,exp_result_n_10,Q[4:1]}),
.\Q_reg[0] (\Q_reg[0]_1 ),
.\Q_reg[0]_0 (\Q_reg[0]_2 ),
.\Q_reg[1] (\Q_reg[1]_0 ),
.\Q_reg[26] (\Q_reg[26] ),
.\Q_reg[30] (\Q_reg[30]_0 ),
.\Q_reg[30]_0 (\Q_reg[30] [7:1]),
.\Q_reg[3] (\Q_reg[3] ),
.S(S));
RegisterAdd__parameterized5 exp_result
(.AR(AR),
.CLK(CLK),
.D(D[30:23]),
.Data_A(Data_A),
.E(E),
.Q({exp_result_n_8,exp_result_n_9,exp_result_n_10,Q}),
.\Q_reg[0]_0 (overflow_flag_OBUF),
.\Q_reg[0]_1 (underflow_flag_OBUF),
.\Q_reg[0]_2 (\Q_reg[0]_1 ),
.\Q_reg[1]_0 (\Q_reg[1] ),
.\Q_reg[23] (\Q_reg[30] [0]));
endmodule
(* EW = "8" *) (* EWR = "5" *) (* SW = "23" *)
(* SWR = "26" *) (* W = "32" *)
(* NotValidForBitStream *)
module FPU_Add_Subtract_Function
(clk,
rst,
beg_FSM,
ack_FSM,
Data_X,
Data_Y,
add_subt,
r_mode,
overflow_flag,
underflow_flag,
ready,
final_result_ieee);
input clk;
input rst;
input beg_FSM;
input ack_FSM;
input [31:0]Data_X;
input [31:0]Data_Y;
input add_subt;
input [1:0]r_mode;
output overflow_flag;
output underflow_flag;
output ready;
output [31:0]final_result_ieee;
wire Add_Subt_Sgf_module_n_22;
wire Add_Subt_Sgf_module_n_23;
wire Add_Subt_Sgf_module_n_24;
wire Add_Subt_Sgf_module_n_25;
wire Add_Subt_Sgf_module_n_26;
wire Add_Subt_Sgf_module_n_27;
wire Add_Subt_Sgf_module_n_33;
wire Add_Subt_Sgf_module_n_34;
wire Add_Subt_Sgf_module_n_35;
wire Add_Subt_Sgf_module_n_36;
wire Add_Subt_Sgf_module_n_37;
wire Add_Subt_Sgf_module_n_38;
wire Add_Subt_Sgf_module_n_39;
wire Add_Subt_Sgf_module_n_40;
wire Add_Subt_Sgf_module_n_41;
wire Add_Subt_Sgf_module_n_42;
wire Add_Subt_Sgf_module_n_43;
wire Add_Subt_Sgf_module_n_44;
wire Add_Subt_Sgf_module_n_45;
wire Add_Subt_Sgf_module_n_46;
wire Add_Subt_Sgf_module_n_47;
wire Add_Subt_Sgf_module_n_48;
wire Add_Subt_Sgf_module_n_49;
wire Add_Subt_Sgf_module_n_50;
wire Add_Subt_Sgf_module_n_51;
wire Add_Subt_Sgf_module_n_52;
wire Add_Subt_Sgf_module_n_53;
wire Add_Subt_Sgf_module_n_54;
wire Add_Subt_Sgf_module_n_55;
wire Add_Subt_Sgf_module_n_56;
wire Add_Subt_Sgf_module_n_57;
wire Add_Subt_Sgf_module_n_58;
wire Barrel_Shifter_module_n_0;
wire Barrel_Shifter_module_n_17;
wire Barrel_Shifter_module_n_18;
wire Barrel_Shifter_module_n_19;
wire Barrel_Shifter_module_n_20;
wire Barrel_Shifter_module_n_21;
wire Barrel_Shifter_module_n_22;
wire Barrel_Shifter_module_n_23;
wire Barrel_Shifter_module_n_24;
wire Barrel_Shifter_module_n_25;
wire Barrel_Shifter_module_n_27;
wire Barrel_Shifter_module_n_28;
wire Barrel_Shifter_module_n_29;
wire Barrel_Shifter_module_n_30;
wire Barrel_Shifter_module_n_31;
wire Barrel_Shifter_module_n_32;
wire Barrel_Shifter_module_n_33;
wire Barrel_Shifter_module_n_34;
wire Barrel_Shifter_module_n_35;
wire Barrel_Shifter_module_n_36;
wire Barrel_Shifter_module_n_37;
wire Barrel_Shifter_module_n_38;
wire Barrel_Shifter_module_n_39;
wire Barrel_Shifter_module_n_40;
wire Barrel_Shifter_module_n_41;
wire Barrel_Shifter_module_n_42;
wire Barrel_Shifter_module_n_43;
wire Barrel_Shifter_module_n_44;
wire Barrel_Shifter_module_n_45;
wire Barrel_Shifter_module_n_46;
wire Barrel_Shifter_module_n_47;
wire Barrel_Shifter_module_n_48;
wire Barrel_Shifter_module_n_49;
wire Barrel_Shifter_module_n_50;
wire [4:0]Codec_to_Reg;
wire [0:0]Data_A;
wire [15:0]Data_Reg;
wire [31:0]Data_X;
wire [31:0]Data_X_IBUF;
wire [31:0]Data_Y;
wire [31:0]Data_Y_IBUF;
wire Exp_Operation_Module_n_10;
wire Exp_Operation_Module_n_11;
wire Exp_Operation_Module_n_12;
wire Exp_Operation_Module_n_13;
wire Exp_Operation_Module_n_14;
wire Exp_Operation_Module_n_15;
wire Exp_Operation_Module_n_16;
wire Exp_Operation_Module_n_17;
wire Exp_Operation_Module_n_18;
wire Exp_Operation_Module_n_19;
wire Exp_Operation_Module_n_20;
wire Exp_Operation_Module_n_21;
wire Exp_Operation_Module_n_22;
wire Exp_Operation_Module_n_23;
wire Exp_Operation_Module_n_24;
wire Exp_Operation_Module_n_25;
wire Exp_Operation_Module_n_26;
wire Exp_Operation_Module_n_27;
wire Exp_Operation_Module_n_28;
wire Exp_Operation_Module_n_29;
wire Exp_Operation_Module_n_3;
wire Exp_Operation_Module_n_30;
wire Exp_Operation_Module_n_31;
wire Exp_Operation_Module_n_32;
wire Exp_Operation_Module_n_33;
wire Exp_Operation_Module_n_4;
wire Exp_Operation_Module_n_40;
wire Exp_Operation_Module_n_41;
wire Exp_Operation_Module_n_42;
wire Exp_Operation_Module_n_43;
wire Exp_Operation_Module_n_44;
wire Exp_Operation_Module_n_45;
wire Exp_Operation_Module_n_46;
wire Exp_Operation_Module_n_47;
wire Exp_Operation_Module_n_48;
wire Exp_Operation_Module_n_5;
wire Exp_Operation_Module_n_6;
wire Exp_Operation_Module_n_7;
wire Exp_Operation_Module_n_8;
wire Exp_Operation_Module_n_9;
wire FSM_Add_Subt_Sgf_load;
wire FSM_LZA_load;
wire FSM_barrel_shifter_B_S;
wire FSM_barrel_shifter_L_R;
wire FSM_barrel_shifter_load;
wire FSM_exp_operation_A_S;
wire FSM_exp_operation_load_diff;
wire FSM_op_start_in_load_a;
wire FSM_op_start_in_load_b;
wire [1:0]FSM_selector_B;
wire FSM_selector_C;
wire FSM_selector_D;
wire FS_Module_n_10;
wire FS_Module_n_11;
wire FS_Module_n_12;
wire FS_Module_n_13;
wire FS_Module_n_2;
wire FS_Module_n_23;
wire FS_Module_n_24;
wire FS_Module_n_25;
wire FS_Module_n_5;
wire FS_Module_n_6;
wire FS_Module_n_7;
wire FS_Module_n_8;
wire FS_Module_n_9;
wire [4:0]LZA_output;
wire [25:0]\Mux_Array/Data_array[3]_0 ;
wire [25:10]\Mux_Array/Data_array[4]_1 ;
wire Oper_Start_in_module_n_10;
wire Oper_Start_in_module_n_11;
wire Oper_Start_in_module_n_12;
wire Oper_Start_in_module_n_13;
wire Oper_Start_in_module_n_14;
wire Oper_Start_in_module_n_15;
wire Oper_Start_in_module_n_16;
wire Oper_Start_in_module_n_17;
wire Oper_Start_in_module_n_18;
wire Oper_Start_in_module_n_19;
wire Oper_Start_in_module_n_20;
wire Oper_Start_in_module_n_21;
wire Oper_Start_in_module_n_22;
wire Oper_Start_in_module_n_23;
wire Oper_Start_in_module_n_24;
wire Oper_Start_in_module_n_25;
wire Oper_Start_in_module_n_26;
wire Oper_Start_in_module_n_27;
wire Oper_Start_in_module_n_28;
wire Oper_Start_in_module_n_29;
wire Oper_Start_in_module_n_3;
wire Oper_Start_in_module_n_33;
wire Oper_Start_in_module_n_34;
wire Oper_Start_in_module_n_35;
wire Oper_Start_in_module_n_36;
wire Oper_Start_in_module_n_37;
wire Oper_Start_in_module_n_38;
wire Oper_Start_in_module_n_39;
wire Oper_Start_in_module_n_4;
wire Oper_Start_in_module_n_40;
wire Oper_Start_in_module_n_41;
wire Oper_Start_in_module_n_42;
wire Oper_Start_in_module_n_43;
wire Oper_Start_in_module_n_44;
wire Oper_Start_in_module_n_45;
wire Oper_Start_in_module_n_46;
wire Oper_Start_in_module_n_47;
wire Oper_Start_in_module_n_48;
wire Oper_Start_in_module_n_49;
wire Oper_Start_in_module_n_5;
wire Oper_Start_in_module_n_50;
wire Oper_Start_in_module_n_51;
wire Oper_Start_in_module_n_52;
wire Oper_Start_in_module_n_53;
wire Oper_Start_in_module_n_54;
wire Oper_Start_in_module_n_55;
wire Oper_Start_in_module_n_56;
wire Oper_Start_in_module_n_57;
wire Oper_Start_in_module_n_58;
wire Oper_Start_in_module_n_59;
wire Oper_Start_in_module_n_6;
wire Oper_Start_in_module_n_60;
wire Oper_Start_in_module_n_61;
wire Oper_Start_in_module_n_62;
wire Oper_Start_in_module_n_63;
wire Oper_Start_in_module_n_64;
wire Oper_Start_in_module_n_65;
wire Oper_Start_in_module_n_66;
wire Oper_Start_in_module_n_67;
wire Oper_Start_in_module_n_68;
wire Oper_Start_in_module_n_69;
wire Oper_Start_in_module_n_7;
wire Oper_Start_in_module_n_70;
wire Oper_Start_in_module_n_71;
wire Oper_Start_in_module_n_72;
wire Oper_Start_in_module_n_73;
wire Oper_Start_in_module_n_74;
wire Oper_Start_in_module_n_75;
wire Oper_Start_in_module_n_76;
wire Oper_Start_in_module_n_77;
wire Oper_Start_in_module_n_78;
wire Oper_Start_in_module_n_79;
wire Oper_Start_in_module_n_8;
wire Oper_Start_in_module_n_80;
wire Oper_Start_in_module_n_81;
wire Oper_Start_in_module_n_82;
wire Oper_Start_in_module_n_83;
wire Oper_Start_in_module_n_84;
wire Oper_Start_in_module_n_85;
wire Oper_Start_in_module_n_86;
wire Oper_Start_in_module_n_87;
wire Oper_Start_in_module_n_88;
wire Oper_Start_in_module_n_89;
wire Oper_Start_in_module_n_9;
wire Oper_Start_in_module_n_90;
wire Oper_Start_in_module_n_91;
wire Oper_Start_in_module_n_92;
wire Oper_Start_in_module_n_93;
wire Oper_Start_in_module_n_94;
wire Oper_Start_in_module_n_95;
wire Sel_A_n_0;
wire Sel_B_n_0;
wire Sel_B_n_1;
wire Sel_B_n_10;
wire Sel_B_n_11;
wire Sel_B_n_12;
wire Sel_B_n_16;
wire Sel_B_n_17;
wire Sel_B_n_2;
wire Sel_B_n_3;
wire Sel_B_n_34;
wire Sel_B_n_35;
wire Sel_B_n_36;
wire Sel_B_n_37;
wire Sel_B_n_4;
wire Sel_B_n_40;
wire Sel_B_n_41;
wire Sel_B_n_5;
wire Sel_B_n_6;
wire Sel_B_n_7;
wire Sel_B_n_8;
wire Sel_B_n_9;
wire Sel_D_n_1;
wire [1:0]Sgf_normalized_result;
wire Sign_S_mux;
wire ack_FSM;
wire ack_FSM_IBUF;
wire add_overflow_flag;
wire add_subt;
wire add_subt_IBUF;
wire beg_FSM;
wire beg_FSM_IBUF;
wire clk;
wire clk_IBUF;
wire clk_IBUF_BUFG;
wire eqXY;
wire [4:0]exp_oper_result;
wire [31:0]final_result_ieee;
wire [31:0]final_result_ieee_OBUF;
wire intAS;
wire [31:31]intDX;
wire [31:31]intDY;
wire overflow_flag;
wire overflow_flag_OBUF;
wire [1:0]r_mode;
wire [1:0]r_mode_IBUF;
wire ready;
wire ready_OBUF;
wire round_flag;
wire rst;
wire rst_IBUF;
wire rst_int;
wire sign_final_result;
wire underflow_flag;
wire underflow_flag_OBUF;
wire zero_flag;
initial begin
$sdf_annotate("Testbench_FPU_Add_Subt_time_synth.sdf",,,,"tool_control");
end
Add_Subt Add_Subt_Sgf_module
(.AR(FS_Module_n_25),
.CLK(clk_IBUF_BUFG),
.D(\Mux_Array/Data_array[3]_0 [20:0]),
.E(FSM_Add_Subt_Sgf_load),
.FSM_barrel_shifter_B_S(FSM_barrel_shifter_B_S),
.FSM_barrel_shifter_L_R(FSM_barrel_shifter_L_R),
.FSM_selector_B(FSM_selector_B),
.FSM_selector_C(FSM_selector_C),
.FSM_selector_D(FSM_selector_D),
.O({Oper_Start_in_module_n_27,Oper_Start_in_module_n_28,Oper_Start_in_module_n_29}),
.Q({Add_Subt_Sgf_module_n_26,Add_Subt_Sgf_module_n_27}),
.\Q_reg[0] ({Add_Subt_Sgf_module_n_57,Add_Subt_Sgf_module_n_58}),
.\Q_reg[0]_0 (FS_Module_n_2),
.\Q_reg[0]_1 (Sel_B_n_40),
.\Q_reg[0]_2 (LZA_output[0]),
.\Q_reg[0]_3 (exp_oper_result[0]),
.\Q_reg[11] ({Add_Subt_Sgf_module_n_41,Add_Subt_Sgf_module_n_42,Add_Subt_Sgf_module_n_43,Add_Subt_Sgf_module_n_44}),
.\Q_reg[15] (Add_Subt_Sgf_module_n_25),
.\Q_reg[15]_0 ({Add_Subt_Sgf_module_n_45,Add_Subt_Sgf_module_n_46,Add_Subt_Sgf_module_n_47,Add_Subt_Sgf_module_n_48}),
.\Q_reg[16] (Add_Subt_Sgf_module_n_23),
.\Q_reg[17] (Add_Subt_Sgf_module_n_24),
.\Q_reg[18] (Add_Subt_Sgf_module_n_22),
.\Q_reg[19] ({Add_Subt_Sgf_module_n_49,Add_Subt_Sgf_module_n_50,Add_Subt_Sgf_module_n_51,Add_Subt_Sgf_module_n_52}),
.\Q_reg[1] (Sel_B_n_17),
.\Q_reg[22] ({Oper_Start_in_module_n_73,Oper_Start_in_module_n_74,Oper_Start_in_module_n_75,Oper_Start_in_module_n_76,Oper_Start_in_module_n_77,Oper_Start_in_module_n_78,Oper_Start_in_module_n_79,Oper_Start_in_module_n_80,Oper_Start_in_module_n_81,Oper_Start_in_module_n_82,Oper_Start_in_module_n_83,Oper_Start_in_module_n_84,Oper_Start_in_module_n_85,Oper_Start_in_module_n_86,Oper_Start_in_module_n_87,Oper_Start_in_module_n_88,Oper_Start_in_module_n_89,Oper_Start_in_module_n_90,Oper_Start_in_module_n_91,Oper_Start_in_module_n_92,Oper_Start_in_module_n_93,Oper_Start_in_module_n_94,Oper_Start_in_module_n_95}),
.\Q_reg[22]_0 ({Oper_Start_in_module_n_42,Oper_Start_in_module_n_43,Oper_Start_in_module_n_44,Oper_Start_in_module_n_45,Oper_Start_in_module_n_46,Oper_Start_in_module_n_47,Oper_Start_in_module_n_48,Oper_Start_in_module_n_49,Oper_Start_in_module_n_50,Oper_Start_in_module_n_51,Oper_Start_in_module_n_52,Oper_Start_in_module_n_53,Oper_Start_in_module_n_54,Oper_Start_in_module_n_55,Oper_Start_in_module_n_56,Oper_Start_in_module_n_57,Oper_Start_in_module_n_58,Oper_Start_in_module_n_59,Oper_Start_in_module_n_60,Oper_Start_in_module_n_61,Oper_Start_in_module_n_62,Oper_Start_in_module_n_63,Oper_Start_in_module_n_64}),
.\Q_reg[23] ({Add_Subt_Sgf_module_n_53,Add_Subt_Sgf_module_n_54,Add_Subt_Sgf_module_n_55,Add_Subt_Sgf_module_n_56}),
.\Q_reg[25] ({Barrel_Shifter_module_n_27,Barrel_Shifter_module_n_28,Barrel_Shifter_module_n_29,Barrel_Shifter_module_n_30,Barrel_Shifter_module_n_31,Barrel_Shifter_module_n_32,Barrel_Shifter_module_n_33,Barrel_Shifter_module_n_34,Barrel_Shifter_module_n_35,Barrel_Shifter_module_n_36,Barrel_Shifter_module_n_37,Barrel_Shifter_module_n_38,Barrel_Shifter_module_n_39,Barrel_Shifter_module_n_40,Barrel_Shifter_module_n_41,Barrel_Shifter_module_n_42,Barrel_Shifter_module_n_43,Barrel_Shifter_module_n_44,Barrel_Shifter_module_n_45,Barrel_Shifter_module_n_46,Barrel_Shifter_module_n_47,Barrel_Shifter_module_n_48,Barrel_Shifter_module_n_49,Barrel_Shifter_module_n_50,Sgf_normalized_result}),
.\Q_reg[2] (Sel_B_n_16),
.\Q_reg[31] ({Oper_Start_in_module_n_3,Oper_Start_in_module_n_4,Oper_Start_in_module_n_5,Oper_Start_in_module_n_6,Oper_Start_in_module_n_7,Oper_Start_in_module_n_8,Oper_Start_in_module_n_9,Oper_Start_in_module_n_10,Oper_Start_in_module_n_11,Oper_Start_in_module_n_12,Oper_Start_in_module_n_13,Oper_Start_in_module_n_14,Oper_Start_in_module_n_15,Oper_Start_in_module_n_16,Oper_Start_in_module_n_17,Oper_Start_in_module_n_18,Oper_Start_in_module_n_19,Oper_Start_in_module_n_20,Oper_Start_in_module_n_21,Oper_Start_in_module_n_22,Oper_Start_in_module_n_23,Oper_Start_in_module_n_24,Oper_Start_in_module_n_25,Oper_Start_in_module_n_26}),
.\Q_reg[31]_0 (intDY),
.\Q_reg[31]_1 (intDX),
.\Q_reg[4] (Codec_to_Reg),
.\Q_reg[7] ({Add_Subt_Sgf_module_n_37,Add_Subt_Sgf_module_n_38,Add_Subt_Sgf_module_n_39,Add_Subt_Sgf_module_n_40}),
.S({Add_Subt_Sgf_module_n_33,Add_Subt_Sgf_module_n_34,Add_Subt_Sgf_module_n_35,Add_Subt_Sgf_module_n_36}),
.add_overflow_flag(add_overflow_flag),
.intAS(intAS));
Barrel_Shifter Barrel_Shifter_module
(.AR(FS_Module_n_25),
.CLK(clk_IBUF_BUFG),
.D(Data_Reg),
.E(FSM_barrel_shifter_load),
.FSM_barrel_shifter_B_S(FSM_barrel_shifter_B_S),
.FSM_barrel_shifter_L_R(FSM_barrel_shifter_L_R),
.\FSM_sequential_state_reg_reg[3] (FS_Module_n_24),
.Q(\Mux_Array/Data_array[4]_1 ),
.\Q_reg[0] ({Barrel_Shifter_module_n_27,Barrel_Shifter_module_n_28,Barrel_Shifter_module_n_29,Barrel_Shifter_module_n_30,Barrel_Shifter_module_n_31,Barrel_Shifter_module_n_32,Barrel_Shifter_module_n_33,Barrel_Shifter_module_n_34,Barrel_Shifter_module_n_35,Barrel_Shifter_module_n_36,Barrel_Shifter_module_n_37,Barrel_Shifter_module_n_38,Barrel_Shifter_module_n_39,Barrel_Shifter_module_n_40,Barrel_Shifter_module_n_41,Barrel_Shifter_module_n_42,Barrel_Shifter_module_n_43,Barrel_Shifter_module_n_44,Barrel_Shifter_module_n_45,Barrel_Shifter_module_n_46,Barrel_Shifter_module_n_47,Barrel_Shifter_module_n_48,Barrel_Shifter_module_n_49,Barrel_Shifter_module_n_50,Sgf_normalized_result}),
.\Q_reg[16] (Barrel_Shifter_module_n_0),
.\Q_reg[16]_0 (Sel_B_n_34),
.\Q_reg[17] (Barrel_Shifter_module_n_18),
.\Q_reg[17]_0 (Sel_B_n_37),
.\Q_reg[18] (Barrel_Shifter_module_n_20),
.\Q_reg[19] (Barrel_Shifter_module_n_22),
.\Q_reg[20] (Barrel_Shifter_module_n_24),
.\Q_reg[21] (Barrel_Shifter_module_n_25),
.\Q_reg[22] (Barrel_Shifter_module_n_23),
.\Q_reg[23] (Barrel_Shifter_module_n_21),
.\Q_reg[24] (Barrel_Shifter_module_n_19),
.\Q_reg[25] (Barrel_Shifter_module_n_17),
.\Q_reg[2] (\Mux_Array/Data_array[3]_0 ),
.\Q_reg[3] (Sel_B_n_36),
.\Q_reg[4] (Sel_B_n_35),
.r_mode_IBUF(r_mode_IBUF),
.round_flag(round_flag),
.sign_final_result(sign_final_result));
IBUF \Data_X_IBUF[0]_inst
(.I(Data_X[0]),
.O(Data_X_IBUF[0]));
IBUF \Data_X_IBUF[10]_inst
(.I(Data_X[10]),
.O(Data_X_IBUF[10]));
IBUF \Data_X_IBUF[11]_inst
(.I(Data_X[11]),
.O(Data_X_IBUF[11]));
IBUF \Data_X_IBUF[12]_inst
(.I(Data_X[12]),
.O(Data_X_IBUF[12]));
IBUF \Data_X_IBUF[13]_inst
(.I(Data_X[13]),
.O(Data_X_IBUF[13]));
IBUF \Data_X_IBUF[14]_inst
(.I(Data_X[14]),
.O(Data_X_IBUF[14]));
IBUF \Data_X_IBUF[15]_inst
(.I(Data_X[15]),
.O(Data_X_IBUF[15]));
IBUF \Data_X_IBUF[16]_inst
(.I(Data_X[16]),
.O(Data_X_IBUF[16]));
IBUF \Data_X_IBUF[17]_inst
(.I(Data_X[17]),
.O(Data_X_IBUF[17]));
IBUF \Data_X_IBUF[18]_inst
(.I(Data_X[18]),
.O(Data_X_IBUF[18]));
IBUF \Data_X_IBUF[19]_inst
(.I(Data_X[19]),
.O(Data_X_IBUF[19]));
IBUF \Data_X_IBUF[1]_inst
(.I(Data_X[1]),
.O(Data_X_IBUF[1]));
IBUF \Data_X_IBUF[20]_inst
(.I(Data_X[20]),
.O(Data_X_IBUF[20]));
IBUF \Data_X_IBUF[21]_inst
(.I(Data_X[21]),
.O(Data_X_IBUF[21]));
IBUF \Data_X_IBUF[22]_inst
(.I(Data_X[22]),
.O(Data_X_IBUF[22]));
IBUF \Data_X_IBUF[23]_inst
(.I(Data_X[23]),
.O(Data_X_IBUF[23]));
IBUF \Data_X_IBUF[24]_inst
(.I(Data_X[24]),
.O(Data_X_IBUF[24]));
IBUF \Data_X_IBUF[25]_inst
(.I(Data_X[25]),
.O(Data_X_IBUF[25]));
IBUF \Data_X_IBUF[26]_inst
(.I(Data_X[26]),
.O(Data_X_IBUF[26]));
IBUF \Data_X_IBUF[27]_inst
(.I(Data_X[27]),
.O(Data_X_IBUF[27]));
IBUF \Data_X_IBUF[28]_inst
(.I(Data_X[28]),
.O(Data_X_IBUF[28]));
IBUF \Data_X_IBUF[29]_inst
(.I(Data_X[29]),
.O(Data_X_IBUF[29]));
IBUF \Data_X_IBUF[2]_inst
(.I(Data_X[2]),
.O(Data_X_IBUF[2]));
IBUF \Data_X_IBUF[30]_inst
(.I(Data_X[30]),
.O(Data_X_IBUF[30]));
IBUF \Data_X_IBUF[31]_inst
(.I(Data_X[31]),
.O(Data_X_IBUF[31]));
IBUF \Data_X_IBUF[3]_inst
(.I(Data_X[3]),
.O(Data_X_IBUF[3]));
IBUF \Data_X_IBUF[4]_inst
(.I(Data_X[4]),
.O(Data_X_IBUF[4]));
IBUF \Data_X_IBUF[5]_inst
(.I(Data_X[5]),
.O(Data_X_IBUF[5]));
IBUF \Data_X_IBUF[6]_inst
(.I(Data_X[6]),
.O(Data_X_IBUF[6]));
IBUF \Data_X_IBUF[7]_inst
(.I(Data_X[7]),
.O(Data_X_IBUF[7]));
IBUF \Data_X_IBUF[8]_inst
(.I(Data_X[8]),
.O(Data_X_IBUF[8]));
IBUF \Data_X_IBUF[9]_inst
(.I(Data_X[9]),
.O(Data_X_IBUF[9]));
IBUF \Data_Y_IBUF[0]_inst
(.I(Data_Y[0]),
.O(Data_Y_IBUF[0]));
IBUF \Data_Y_IBUF[10]_inst
(.I(Data_Y[10]),
.O(Data_Y_IBUF[10]));
IBUF \Data_Y_IBUF[11]_inst
(.I(Data_Y[11]),
.O(Data_Y_IBUF[11]));
IBUF \Data_Y_IBUF[12]_inst
(.I(Data_Y[12]),
.O(Data_Y_IBUF[12]));
IBUF \Data_Y_IBUF[13]_inst
(.I(Data_Y[13]),
.O(Data_Y_IBUF[13]));
IBUF \Data_Y_IBUF[14]_inst
(.I(Data_Y[14]),
.O(Data_Y_IBUF[14]));
IBUF \Data_Y_IBUF[15]_inst
(.I(Data_Y[15]),
.O(Data_Y_IBUF[15]));
IBUF \Data_Y_IBUF[16]_inst
(.I(Data_Y[16]),
.O(Data_Y_IBUF[16]));
IBUF \Data_Y_IBUF[17]_inst
(.I(Data_Y[17]),
.O(Data_Y_IBUF[17]));
IBUF \Data_Y_IBUF[18]_inst
(.I(Data_Y[18]),
.O(Data_Y_IBUF[18]));
IBUF \Data_Y_IBUF[19]_inst
(.I(Data_Y[19]),
.O(Data_Y_IBUF[19]));
IBUF \Data_Y_IBUF[1]_inst
(.I(Data_Y[1]),
.O(Data_Y_IBUF[1]));
IBUF \Data_Y_IBUF[20]_inst
(.I(Data_Y[20]),
.O(Data_Y_IBUF[20]));
IBUF \Data_Y_IBUF[21]_inst
(.I(Data_Y[21]),
.O(Data_Y_IBUF[21]));
IBUF \Data_Y_IBUF[22]_inst
(.I(Data_Y[22]),
.O(Data_Y_IBUF[22]));
IBUF \Data_Y_IBUF[23]_inst
(.I(Data_Y[23]),
.O(Data_Y_IBUF[23]));
IBUF \Data_Y_IBUF[24]_inst
(.I(Data_Y[24]),
.O(Data_Y_IBUF[24]));
IBUF \Data_Y_IBUF[25]_inst
(.I(Data_Y[25]),
.O(Data_Y_IBUF[25]));
IBUF \Data_Y_IBUF[26]_inst
(.I(Data_Y[26]),
.O(Data_Y_IBUF[26]));
IBUF \Data_Y_IBUF[27]_inst
(.I(Data_Y[27]),
.O(Data_Y_IBUF[27]));
IBUF \Data_Y_IBUF[28]_inst
(.I(Data_Y[28]),
.O(Data_Y_IBUF[28]));
IBUF \Data_Y_IBUF[29]_inst
(.I(Data_Y[29]),
.O(Data_Y_IBUF[29]));
IBUF \Data_Y_IBUF[2]_inst
(.I(Data_Y[2]),
.O(Data_Y_IBUF[2]));
IBUF \Data_Y_IBUF[30]_inst
(.I(Data_Y[30]),
.O(Data_Y_IBUF[30]));
IBUF \Data_Y_IBUF[31]_inst
(.I(Data_Y[31]),
.O(Data_Y_IBUF[31]));
IBUF \Data_Y_IBUF[3]_inst
(.I(Data_Y[3]),
.O(Data_Y_IBUF[3]));
IBUF \Data_Y_IBUF[4]_inst
(.I(Data_Y[4]),
.O(Data_Y_IBUF[4]));
IBUF \Data_Y_IBUF[5]_inst
(.I(Data_Y[5]),
.O(Data_Y_IBUF[5]));
IBUF \Data_Y_IBUF[6]_inst
(.I(Data_Y[6]),
.O(Data_Y_IBUF[6]));
IBUF \Data_Y_IBUF[7]_inst
(.I(Data_Y[7]),
.O(Data_Y_IBUF[7]));
IBUF \Data_Y_IBUF[8]_inst
(.I(Data_Y[8]),
.O(Data_Y_IBUF[8]));
IBUF \Data_Y_IBUF[9]_inst
(.I(Data_Y[9]),
.O(Data_Y_IBUF[9]));
Exp_Operation Exp_Operation_Module
(.AR(FS_Module_n_25),
.CLK(clk_IBUF_BUFG),
.D({Sign_S_mux,Exp_Operation_Module_n_3,Exp_Operation_Module_n_4,Exp_Operation_Module_n_5,Exp_Operation_Module_n_6,Exp_Operation_Module_n_7,Exp_Operation_Module_n_8,Exp_Operation_Module_n_9,Exp_Operation_Module_n_10,Exp_Operation_Module_n_11,Exp_Operation_Module_n_12,Exp_Operation_Module_n_13,Exp_Operation_Module_n_14,Exp_Operation_Module_n_15,Exp_Operation_Module_n_16,Exp_Operation_Module_n_17,Exp_Operation_Module_n_18,Exp_Operation_Module_n_19,Exp_Operation_Module_n_20,Exp_Operation_Module_n_21,Exp_Operation_Module_n_22,Exp_Operation_Module_n_23,Exp_Operation_Module_n_24,Exp_Operation_Module_n_25,Exp_Operation_Module_n_26,Exp_Operation_Module_n_27,Exp_Operation_Module_n_28,Exp_Operation_Module_n_29,Exp_Operation_Module_n_30,Exp_Operation_Module_n_31,Exp_Operation_Module_n_32,Exp_Operation_Module_n_33}),
.DI(Sel_B_n_11),
.Data_A(Data_A),
.E(FSM_exp_operation_load_diff),
.FSM_exp_operation_A_S(FSM_exp_operation_A_S),
.FSM_selector_B(FSM_selector_B),
.O(Sel_B_n_12),
.Q(exp_oper_result),
.\Q_reg[0] (Exp_Operation_Module_n_40),
.\Q_reg[0]_0 (FS_Module_n_13),
.\Q_reg[0]_1 (Sel_A_n_0),
.\Q_reg[0]_2 (LZA_output[0]),
.\Q_reg[1] ({Sel_B_n_0,Sel_B_n_1,Sel_B_n_2,Sel_B_n_3,Sel_B_n_4,Sel_B_n_5,Sel_B_n_6,Sel_B_n_7}),
.\Q_reg[1]_0 (Sel_B_n_41),
.\Q_reg[24] ({Barrel_Shifter_module_n_28,Barrel_Shifter_module_n_29,Barrel_Shifter_module_n_30,Barrel_Shifter_module_n_31,Barrel_Shifter_module_n_32,Barrel_Shifter_module_n_33,Barrel_Shifter_module_n_34,Barrel_Shifter_module_n_35,Barrel_Shifter_module_n_36,Barrel_Shifter_module_n_37,Barrel_Shifter_module_n_38,Barrel_Shifter_module_n_39,Barrel_Shifter_module_n_40,Barrel_Shifter_module_n_41,Barrel_Shifter_module_n_42,Barrel_Shifter_module_n_43,Barrel_Shifter_module_n_44,Barrel_Shifter_module_n_45,Barrel_Shifter_module_n_46,Barrel_Shifter_module_n_47,Barrel_Shifter_module_n_48,Barrel_Shifter_module_n_49,Barrel_Shifter_module_n_50}),
.\Q_reg[26] ({Sel_B_n_8,Sel_B_n_9,Sel_B_n_10}),
.\Q_reg[30] ({Oper_Start_in_module_n_34,Oper_Start_in_module_n_35,Oper_Start_in_module_n_36,Oper_Start_in_module_n_37,Oper_Start_in_module_n_38,Oper_Start_in_module_n_39,Oper_Start_in_module_n_40,Oper_Start_in_module_n_41}),
.\Q_reg[30]_0 ({Oper_Start_in_module_n_65,Oper_Start_in_module_n_66,Oper_Start_in_module_n_67,Oper_Start_in_module_n_72}),
.\Q_reg[3] ({Exp_Operation_Module_n_45,Exp_Operation_Module_n_46,Exp_Operation_Module_n_47,Exp_Operation_Module_n_48}),
.S({Exp_Operation_Module_n_41,Exp_Operation_Module_n_42,Exp_Operation_Module_n_43,Exp_Operation_Module_n_44}),
.overflow_flag_OBUF(overflow_flag_OBUF),
.sign_final_result(sign_final_result),
.underflow_flag_OBUF(underflow_flag_OBUF));
FSM_Add_Subtract FS_Module
(.AR(rst_int),
.CLK(clk_IBUF_BUFG),
.CO(eqXY),
.E(FS_Module_n_12),
.FSM_barrel_shifter_B_S(FSM_barrel_shifter_B_S),
.FSM_barrel_shifter_L_R(FSM_barrel_shifter_L_R),
.FSM_exp_operation_A_S(FSM_exp_operation_A_S),
.FSM_selector_C(FSM_selector_C),
.FSM_selector_D(FSM_selector_D),
.Q({Add_Subt_Sgf_module_n_26,Add_Subt_Sgf_module_n_27}),
.\Q_reg[0] (FS_Module_n_5),
.\Q_reg[0]_0 (FS_Module_n_10),
.\Q_reg[0]_1 (FS_Module_n_11),
.\Q_reg[0]_10 (Add_Subt_Sgf_module_n_24),
.\Q_reg[0]_11 (Sel_B_n_40),
.\Q_reg[0]_12 (Sel_A_n_0),
.\Q_reg[0]_13 (Exp_Operation_Module_n_40),
.\Q_reg[0]_2 (FS_Module_n_13),
.\Q_reg[0]_3 (FSM_exp_operation_load_diff),
.\Q_reg[0]_4 (FSM_Add_Subt_Sgf_load),
.\Q_reg[0]_5 (FSM_op_start_in_load_a),
.\Q_reg[0]_6 (FSM_op_start_in_load_b),
.\Q_reg[0]_7 (FSM_barrel_shifter_load),
.\Q_reg[0]_8 (FSM_LZA_load),
.\Q_reg[0]_9 (Add_Subt_Sgf_module_n_25),
.\Q_reg[1] (Sel_B_n_17),
.\Q_reg[1]_0 ({Sel_B_n_1,Sel_B_n_2,Sel_B_n_4}),
.\Q_reg[21] (FS_Module_n_2),
.\Q_reg[23] ({\Mux_Array/Data_array[3]_0 [23],\Mux_Array/Data_array[3]_0 [21]}),
.\Q_reg[2] (Sel_B_n_16),
.\Q_reg[31] ({FS_Module_n_24,FS_Module_n_25}),
.\Q_reg[31]_0 (Oper_Start_in_module_n_33),
.S(FS_Module_n_23),
.ack_FSM_IBUF(ack_FSM_IBUF),
.add_overflow_flag(add_overflow_flag),
.beg_FSM_IBUF(beg_FSM_IBUF),
.in1(rst_IBUF),
.out({FS_Module_n_6,FS_Module_n_7,FS_Module_n_8,FS_Module_n_9}),
.ready_OBUF(ready_OBUF),
.round_flag(round_flag),
.underflow_flag_OBUF(underflow_flag_OBUF),
.zero_flag(zero_flag));
LZD Leading_Zero_Detector_Module
(.CLK(clk_IBUF_BUFG),
.D(Codec_to_Reg),
.E(FSM_LZA_load),
.\FSM_sequential_state_reg_reg[3] (FS_Module_n_25),
.Q(LZA_output));
Oper_Start_In Oper_Start_in_module
(.AR(rst_int),
.CLK(clk_IBUF_BUFG),
.CO(eqXY),
.D(Data_Y_IBUF),
.\Data_X[31] (Data_X_IBUF),
.E(FSM_op_start_in_load_a),
.FSM_selector_D(FSM_selector_D),
.\FSM_sequential_state_reg_reg[3] (Oper_Start_in_module_n_33),
.\FSM_sequential_state_reg_reg[3]_0 (FSM_op_start_in_load_b),
.\FSM_sequential_state_reg_reg[3]_1 ({FS_Module_n_24,FS_Module_n_25}),
.O({Oper_Start_in_module_n_27,Oper_Start_in_module_n_28,Oper_Start_in_module_n_29}),
.Q(intDY),
.\Q_reg[0] (intDX),
.\Q_reg[0]_0 (Sel_D_n_1),
.\Q_reg[23] ({Oper_Start_in_module_n_3,Oper_Start_in_module_n_4,Oper_Start_in_module_n_5,Oper_Start_in_module_n_6,Oper_Start_in_module_n_7,Oper_Start_in_module_n_8,Oper_Start_in_module_n_9,Oper_Start_in_module_n_10,Oper_Start_in_module_n_11,Oper_Start_in_module_n_12,Oper_Start_in_module_n_13,Oper_Start_in_module_n_14,Oper_Start_in_module_n_15,Oper_Start_in_module_n_16,Oper_Start_in_module_n_17,Oper_Start_in_module_n_18,Oper_Start_in_module_n_19,Oper_Start_in_module_n_20,Oper_Start_in_module_n_21,Oper_Start_in_module_n_22,Oper_Start_in_module_n_23,Oper_Start_in_module_n_24,Oper_Start_in_module_n_25,Oper_Start_in_module_n_26}),
.\Q_reg[25] ({Barrel_Shifter_module_n_27,Barrel_Shifter_module_n_28,Barrel_Shifter_module_n_29,Barrel_Shifter_module_n_30,Barrel_Shifter_module_n_31,Barrel_Shifter_module_n_32,Barrel_Shifter_module_n_33,Barrel_Shifter_module_n_34,Barrel_Shifter_module_n_35,Barrel_Shifter_module_n_36,Barrel_Shifter_module_n_37,Barrel_Shifter_module_n_38,Barrel_Shifter_module_n_39,Barrel_Shifter_module_n_40,Barrel_Shifter_module_n_41,Barrel_Shifter_module_n_42,Barrel_Shifter_module_n_43,Barrel_Shifter_module_n_44,Barrel_Shifter_module_n_45,Barrel_Shifter_module_n_46,Barrel_Shifter_module_n_47,Barrel_Shifter_module_n_48,Barrel_Shifter_module_n_49,Barrel_Shifter_module_n_50,Sgf_normalized_result[1]}),
.\Q_reg[31] ({Add_Subt_Sgf_module_n_37,Add_Subt_Sgf_module_n_38,Add_Subt_Sgf_module_n_39,Add_Subt_Sgf_module_n_40}),
.\Q_reg[31]_0 ({Add_Subt_Sgf_module_n_41,Add_Subt_Sgf_module_n_42,Add_Subt_Sgf_module_n_43,Add_Subt_Sgf_module_n_44}),
.\Q_reg[31]_1 ({Add_Subt_Sgf_module_n_45,Add_Subt_Sgf_module_n_46,Add_Subt_Sgf_module_n_47,Add_Subt_Sgf_module_n_48}),
.\Q_reg[31]_2 ({Add_Subt_Sgf_module_n_49,Add_Subt_Sgf_module_n_50,Add_Subt_Sgf_module_n_51,Add_Subt_Sgf_module_n_52}),
.\Q_reg[31]_3 ({Add_Subt_Sgf_module_n_53,Add_Subt_Sgf_module_n_54,Add_Subt_Sgf_module_n_55,Add_Subt_Sgf_module_n_56}),
.\Q_reg[31]_4 ({Add_Subt_Sgf_module_n_57,Add_Subt_Sgf_module_n_58}),
.\Q_reg[7] ({Oper_Start_in_module_n_34,Oper_Start_in_module_n_35,Oper_Start_in_module_n_36,Oper_Start_in_module_n_37,Oper_Start_in_module_n_38,Oper_Start_in_module_n_39,Oper_Start_in_module_n_40,Oper_Start_in_module_n_41,Oper_Start_in_module_n_42,Oper_Start_in_module_n_43,Oper_Start_in_module_n_44,Oper_Start_in_module_n_45,Oper_Start_in_module_n_46,Oper_Start_in_module_n_47,Oper_Start_in_module_n_48,Oper_Start_in_module_n_49,Oper_Start_in_module_n_50,Oper_Start_in_module_n_51,Oper_Start_in_module_n_52,Oper_Start_in_module_n_53,Oper_Start_in_module_n_54,Oper_Start_in_module_n_55,Oper_Start_in_module_n_56,Oper_Start_in_module_n_57,Oper_Start_in_module_n_58,Oper_Start_in_module_n_59,Oper_Start_in_module_n_60,Oper_Start_in_module_n_61,Oper_Start_in_module_n_62,Oper_Start_in_module_n_63,Oper_Start_in_module_n_64}),
.\Q_reg[7]_0 ({Oper_Start_in_module_n_65,Oper_Start_in_module_n_66,Oper_Start_in_module_n_67,Oper_Start_in_module_n_68,Oper_Start_in_module_n_69,Oper_Start_in_module_n_70,Oper_Start_in_module_n_71,Oper_Start_in_module_n_72,Oper_Start_in_module_n_73,Oper_Start_in_module_n_74,Oper_Start_in_module_n_75,Oper_Start_in_module_n_76,Oper_Start_in_module_n_77,Oper_Start_in_module_n_78,Oper_Start_in_module_n_79,Oper_Start_in_module_n_80,Oper_Start_in_module_n_81,Oper_Start_in_module_n_82,Oper_Start_in_module_n_83,Oper_Start_in_module_n_84,Oper_Start_in_module_n_85,Oper_Start_in_module_n_86,Oper_Start_in_module_n_87,Oper_Start_in_module_n_88,Oper_Start_in_module_n_89,Oper_Start_in_module_n_90,Oper_Start_in_module_n_91,Oper_Start_in_module_n_92,Oper_Start_in_module_n_93,Oper_Start_in_module_n_94,Oper_Start_in_module_n_95}),
.S({Add_Subt_Sgf_module_n_33,Add_Subt_Sgf_module_n_34,Add_Subt_Sgf_module_n_35,Add_Subt_Sgf_module_n_36}),
.add_subt_IBUF(add_subt_IBUF),
.intAS(intAS),
.sign_final_result(sign_final_result),
.zero_flag(zero_flag));
RegisterAdd Sel_A
(.CLK(clk_IBUF_BUFG),
.\FSM_sequential_state_reg_reg[0] (FS_Module_n_11),
.\FSM_sequential_state_reg_reg[3] (FS_Module_n_25),
.\Q_reg[0]_0 (Sel_A_n_0));
RegisterAdd__parameterized0 Sel_B
(.CLK(clk_IBUF_BUFG),
.D(Data_Reg),
.DI(Sel_B_n_11),
.Data_A(Data_A),
.FSM_barrel_shifter_B_S(FSM_barrel_shifter_B_S),
.FSM_barrel_shifter_L_R(FSM_barrel_shifter_L_R),
.FSM_exp_operation_A_S(FSM_exp_operation_A_S),
.FSM_selector_B(FSM_selector_B),
.\FSM_sequential_state_reg_reg[3] (FS_Module_n_25),
.O(Sel_B_n_12),
.Q(\Mux_Array/Data_array[4]_1 ),
.\Q_reg[0]_0 (Sel_B_n_35),
.\Q_reg[0]_1 (Sel_B_n_36),
.\Q_reg[0]_2 (FS_Module_n_23),
.\Q_reg[0]_3 (FS_Module_n_2),
.\Q_reg[0]_4 (Add_Subt_Sgf_module_n_22),
.\Q_reg[0]_5 (Add_Subt_Sgf_module_n_23),
.\Q_reg[16] (Barrel_Shifter_module_n_17),
.\Q_reg[17] (Barrel_Shifter_module_n_19),
.\Q_reg[18] (Barrel_Shifter_module_n_21),
.\Q_reg[19] (Barrel_Shifter_module_n_23),
.\Q_reg[20] (Barrel_Shifter_module_n_25),
.\Q_reg[21] (Sel_B_n_40),
.\Q_reg[21]_0 (Barrel_Shifter_module_n_24),
.\Q_reg[22] (Barrel_Shifter_module_n_22),
.\Q_reg[23] (Barrel_Shifter_module_n_20),
.\Q_reg[24] (Barrel_Shifter_module_n_18),
.\Q_reg[25] ({\Mux_Array/Data_array[3]_0 [25:24],\Mux_Array/Data_array[3]_0 [22]}),
.\Q_reg[25]_0 (Sel_B_n_16),
.\Q_reg[25]_1 (Sel_B_n_17),
.\Q_reg[25]_2 (Barrel_Shifter_module_n_0),
.\Q_reg[26] ({Exp_Operation_Module_n_45,Exp_Operation_Module_n_46,Exp_Operation_Module_n_47,Exp_Operation_Module_n_48}),
.\Q_reg[30] ({Oper_Start_in_module_n_65,Oper_Start_in_module_n_66,Oper_Start_in_module_n_67,Oper_Start_in_module_n_68,Oper_Start_in_module_n_69,Oper_Start_in_module_n_70,Oper_Start_in_module_n_71}),
.\Q_reg[3] ({Sel_B_n_8,Sel_B_n_9,Sel_B_n_10}),
.\Q_reg[4] (LZA_output),
.\Q_reg[4]_0 (exp_oper_result),
.\Q_reg[7] ({Sel_B_n_0,Sel_B_n_1,Sel_B_n_2,Sel_B_n_3,Sel_B_n_4,Sel_B_n_5,Sel_B_n_6,Sel_B_n_7}),
.\Q_reg[7]_0 (Sel_B_n_41),
.\Q_reg[8] (Sel_B_n_37),
.\Q_reg[9] (Sel_B_n_34),
.S({Exp_Operation_Module_n_41,Exp_Operation_Module_n_42,Exp_Operation_Module_n_43,Exp_Operation_Module_n_44}),
.add_overflow_flag(add_overflow_flag),
.out({FS_Module_n_6,FS_Module_n_7,FS_Module_n_8,FS_Module_n_9}));
RegisterAdd_0 Sel_C
(.CLK(clk_IBUF_BUFG),
.FSM_selector_C(FSM_selector_C),
.\FSM_sequential_state_reg_reg[3] (FS_Module_n_5),
.\FSM_sequential_state_reg_reg[3]_0 (FS_Module_n_25));
RegisterAdd_1 Sel_D
(.CLK(clk_IBUF_BUFG),
.FSM_selector_D(FSM_selector_D),
.\FSM_sequential_state_reg_reg[0] (FS_Module_n_10),
.\FSM_sequential_state_reg_reg[3] (FS_Module_n_25),
.\Q_reg[0]_0 (Sgf_normalized_result[0]),
.\Q_reg[3] (Sel_D_n_1));
IBUF ack_FSM_IBUF_inst
(.I(ack_FSM),
.O(ack_FSM_IBUF));
IBUF add_subt_IBUF_inst
(.I(add_subt),
.O(add_subt_IBUF));
IBUF beg_FSM_IBUF_inst
(.I(beg_FSM),
.O(beg_FSM_IBUF));
BUFG clk_IBUF_BUFG_inst
(.I(clk_IBUF),
.O(clk_IBUF_BUFG));
IBUF clk_IBUF_inst
(.I(clk),
.O(clk_IBUF));
Tenth_Phase final_result_ieee_Module
(.AR(rst_int),
.CLK(clk_IBUF_BUFG),
.D({Sign_S_mux,Exp_Operation_Module_n_3,Exp_Operation_Module_n_4,Exp_Operation_Module_n_5,Exp_Operation_Module_n_6,Exp_Operation_Module_n_7,Exp_Operation_Module_n_8,Exp_Operation_Module_n_9,Exp_Operation_Module_n_10,Exp_Operation_Module_n_11,Exp_Operation_Module_n_12,Exp_Operation_Module_n_13,Exp_Operation_Module_n_14,Exp_Operation_Module_n_15,Exp_Operation_Module_n_16,Exp_Operation_Module_n_17,Exp_Operation_Module_n_18,Exp_Operation_Module_n_19,Exp_Operation_Module_n_20,Exp_Operation_Module_n_21,Exp_Operation_Module_n_22,Exp_Operation_Module_n_23,Exp_Operation_Module_n_24,Exp_Operation_Module_n_25,Exp_Operation_Module_n_26,Exp_Operation_Module_n_27,Exp_Operation_Module_n_28,Exp_Operation_Module_n_29,Exp_Operation_Module_n_30,Exp_Operation_Module_n_31,Exp_Operation_Module_n_32,Exp_Operation_Module_n_33}),
.E(FS_Module_n_12),
.Q(final_result_ieee_OBUF));
OBUF \final_result_ieee_OBUF[0]_inst
(.I(final_result_ieee_OBUF[0]),
.O(final_result_ieee[0]));
OBUF \final_result_ieee_OBUF[10]_inst
(.I(final_result_ieee_OBUF[10]),
.O(final_result_ieee[10]));
OBUF \final_result_ieee_OBUF[11]_inst
(.I(final_result_ieee_OBUF[11]),
.O(final_result_ieee[11]));
OBUF \final_result_ieee_OBUF[12]_inst
(.I(final_result_ieee_OBUF[12]),
.O(final_result_ieee[12]));
OBUF \final_result_ieee_OBUF[13]_inst
(.I(final_result_ieee_OBUF[13]),
.O(final_result_ieee[13]));
OBUF \final_result_ieee_OBUF[14]_inst
(.I(final_result_ieee_OBUF[14]),
.O(final_result_ieee[14]));
OBUF \final_result_ieee_OBUF[15]_inst
(.I(final_result_ieee_OBUF[15]),
.O(final_result_ieee[15]));
OBUF \final_result_ieee_OBUF[16]_inst
(.I(final_result_ieee_OBUF[16]),
.O(final_result_ieee[16]));
OBUF \final_result_ieee_OBUF[17]_inst
(.I(final_result_ieee_OBUF[17]),
.O(final_result_ieee[17]));
OBUF \final_result_ieee_OBUF[18]_inst
(.I(final_result_ieee_OBUF[18]),
.O(final_result_ieee[18]));
OBUF \final_result_ieee_OBUF[19]_inst
(.I(final_result_ieee_OBUF[19]),
.O(final_result_ieee[19]));
OBUF \final_result_ieee_OBUF[1]_inst
(.I(final_result_ieee_OBUF[1]),
.O(final_result_ieee[1]));
OBUF \final_result_ieee_OBUF[20]_inst
(.I(final_result_ieee_OBUF[20]),
.O(final_result_ieee[20]));
OBUF \final_result_ieee_OBUF[21]_inst
(.I(final_result_ieee_OBUF[21]),
.O(final_result_ieee[21]));
OBUF \final_result_ieee_OBUF[22]_inst
(.I(final_result_ieee_OBUF[22]),
.O(final_result_ieee[22]));
OBUF \final_result_ieee_OBUF[23]_inst
(.I(final_result_ieee_OBUF[23]),
.O(final_result_ieee[23]));
OBUF \final_result_ieee_OBUF[24]_inst
(.I(final_result_ieee_OBUF[24]),
.O(final_result_ieee[24]));
OBUF \final_result_ieee_OBUF[25]_inst
(.I(final_result_ieee_OBUF[25]),
.O(final_result_ieee[25]));
OBUF \final_result_ieee_OBUF[26]_inst
(.I(final_result_ieee_OBUF[26]),
.O(final_result_ieee[26]));
OBUF \final_result_ieee_OBUF[27]_inst
(.I(final_result_ieee_OBUF[27]),
.O(final_result_ieee[27]));
OBUF \final_result_ieee_OBUF[28]_inst
(.I(final_result_ieee_OBUF[28]),
.O(final_result_ieee[28]));
OBUF \final_result_ieee_OBUF[29]_inst
(.I(final_result_ieee_OBUF[29]),
.O(final_result_ieee[29]));
OBUF \final_result_ieee_OBUF[2]_inst
(.I(final_result_ieee_OBUF[2]),
.O(final_result_ieee[2]));
OBUF \final_result_ieee_OBUF[30]_inst
(.I(final_result_ieee_OBUF[30]),
.O(final_result_ieee[30]));
OBUF \final_result_ieee_OBUF[31]_inst
(.I(final_result_ieee_OBUF[31]),
.O(final_result_ieee[31]));
OBUF \final_result_ieee_OBUF[3]_inst
(.I(final_result_ieee_OBUF[3]),
.O(final_result_ieee[3]));
OBUF \final_result_ieee_OBUF[4]_inst
(.I(final_result_ieee_OBUF[4]),
.O(final_result_ieee[4]));
OBUF \final_result_ieee_OBUF[5]_inst
(.I(final_result_ieee_OBUF[5]),
.O(final_result_ieee[5]));
OBUF \final_result_ieee_OBUF[6]_inst
(.I(final_result_ieee_OBUF[6]),
.O(final_result_ieee[6]));
OBUF \final_result_ieee_OBUF[7]_inst
(.I(final_result_ieee_OBUF[7]),
.O(final_result_ieee[7]));
OBUF \final_result_ieee_OBUF[8]_inst
(.I(final_result_ieee_OBUF[8]),
.O(final_result_ieee[8]));
OBUF \final_result_ieee_OBUF[9]_inst
(.I(final_result_ieee_OBUF[9]),
.O(final_result_ieee[9]));
OBUF overflow_flag_OBUF_inst
(.I(overflow_flag_OBUF),
.O(overflow_flag));
IBUF \r_mode_IBUF[0]_inst
(.I(r_mode[0]),
.O(r_mode_IBUF[0]));
IBUF \r_mode_IBUF[1]_inst
(.I(r_mode[1]),
.O(r_mode_IBUF[1]));
OBUF ready_OBUF_inst
(.I(ready_OBUF),
.O(ready));
IBUF rst_IBUF_inst
(.I(rst),
.O(rst_IBUF));
OBUF underflow_flag_OBUF_inst
(.I(underflow_flag_OBUF),
.O(underflow_flag));
endmodule
module FSM_Add_Subtract
(\Q_reg[23] ,
\Q_reg[21] ,
FSM_barrel_shifter_B_S,
FSM_barrel_shifter_L_R,
\Q_reg[0] ,
out,
\Q_reg[0]_0 ,
\Q_reg[0]_1 ,
E,
\Q_reg[0]_2 ,
FSM_exp_operation_A_S,
ready_OBUF,
\Q_reg[0]_3 ,
\Q_reg[0]_4 ,
\Q_reg[0]_5 ,
\Q_reg[0]_6 ,
AR,
\Q_reg[0]_7 ,
\Q_reg[0]_8 ,
S,
\Q_reg[31] ,
\Q_reg[2] ,
\Q_reg[0]_9 ,
\Q_reg[1] ,
\Q_reg[0]_10 ,
\Q_reg[0]_11 ,
Q,
FSM_selector_C,
round_flag,
FSM_selector_D,
\Q_reg[0]_12 ,
\Q_reg[1]_0 ,
\Q_reg[0]_13 ,
underflow_flag_OBUF,
CLK,
in1,
add_overflow_flag,
zero_flag,
beg_FSM_IBUF,
ack_FSM_IBUF,
CO,
\Q_reg[31]_0 );
output [1:0]\Q_reg[23] ;
output \Q_reg[21] ;
output FSM_barrel_shifter_B_S;
output FSM_barrel_shifter_L_R;
output \Q_reg[0] ;
output [3:0]out;
output \Q_reg[0]_0 ;
output \Q_reg[0]_1 ;
output [0:0]E;
output \Q_reg[0]_2 ;
output FSM_exp_operation_A_S;
output ready_OBUF;
output [0:0]\Q_reg[0]_3 ;
output [0:0]\Q_reg[0]_4 ;
output [0:0]\Q_reg[0]_5 ;
output [0:0]\Q_reg[0]_6 ;
output [0:0]AR;
output [0:0]\Q_reg[0]_7 ;
output [0:0]\Q_reg[0]_8 ;
output [0:0]S;
output [1:0]\Q_reg[31] ;
input \Q_reg[2] ;
input \Q_reg[0]_9 ;
input \Q_reg[1] ;
input \Q_reg[0]_10 ;
input \Q_reg[0]_11 ;
input [1:0]Q;
input FSM_selector_C;
input round_flag;
input FSM_selector_D;
input \Q_reg[0]_12 ;
input [2:0]\Q_reg[1]_0 ;
input \Q_reg[0]_13 ;
input underflow_flag_OBUF;
input CLK;
input in1;
input add_overflow_flag;
input zero_flag;
input beg_FSM_IBUF;
input ack_FSM_IBUF;
input [0:0]CO;
input \Q_reg[31]_0 ;
wire [0:0]AR;
wire CLK;
wire [0:0]CO;
wire [0:0]E;
wire FSM_barrel_shifter_B_S;
wire FSM_barrel_shifter_L_R;
wire FSM_exp_operation_A_S;
wire FSM_exp_operation_load_OU;
wire FSM_selector_C;
wire FSM_selector_D;
wire \FSM_sequential_state_reg[0]_i_1_n_0 ;
wire \FSM_sequential_state_reg[1]_i_1_n_0 ;
wire \FSM_sequential_state_reg[2]_i_1_n_0 ;
wire \FSM_sequential_state_reg[3]_i_1_n_0 ;
wire \FSM_sequential_state_reg[3]_i_2_n_0 ;
wire \FSM_sequential_state_reg[3]_i_3_n_0 ;
wire [1:0]Q;
wire \Q_reg[0] ;
wire \Q_reg[0]_0 ;
wire \Q_reg[0]_1 ;
wire \Q_reg[0]_10 ;
wire \Q_reg[0]_11 ;
wire \Q_reg[0]_12 ;
wire \Q_reg[0]_13 ;
wire \Q_reg[0]_2 ;
wire [0:0]\Q_reg[0]_3 ;
wire [0:0]\Q_reg[0]_4 ;
wire [0:0]\Q_reg[0]_5 ;
wire [0:0]\Q_reg[0]_6 ;
wire [0:0]\Q_reg[0]_7 ;
wire [0:0]\Q_reg[0]_8 ;
wire \Q_reg[0]_9 ;
wire \Q_reg[1] ;
wire [2:0]\Q_reg[1]_0 ;
wire \Q_reg[21] ;
wire [1:0]\Q_reg[23] ;
wire \Q_reg[2] ;
wire [1:0]\Q_reg[31] ;
wire \Q_reg[31]_0 ;
wire [0:0]S;
wire ack_FSM_IBUF;
wire add_overflow_flag;
wire beg_FSM_IBUF;
wire in1;
(* RTL_KEEP = "yes" *) wire [3:0]out;
wire ready_OBUF;
wire round_flag;
wire underflow_flag_OBUF;
wire zero_flag;
LUT6 #(
.INIT(64'h0055005557115755))
\FSM_sequential_state_reg[0]_i_1
(.I0(out[0]),
.I1(out[1]),
.I2(FSM_selector_C),
.I3(out[2]),
.I4(zero_flag),
.I5(out[3]),
.O(\FSM_sequential_state_reg[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000FBFB3C3F0000))
\FSM_sequential_state_reg[1]_i_1
(.I0(FSM_selector_C),
.I1(out[2]),
.I2(out[3]),
.I3(zero_flag),
.I4(out[1]),
.I5(out[0]),
.O(\FSM_sequential_state_reg[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h3CC03CC02FF02CF0))
\FSM_sequential_state_reg[2]_i_1
(.I0(round_flag),
.I1(out[0]),
.I2(out[2]),
.I3(out[1]),
.I4(zero_flag),
.I5(out[3]),
.O(\FSM_sequential_state_reg[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7777FFFFFFDDFEFE))
\FSM_sequential_state_reg[3]_i_1
(.I0(out[3]),
.I1(out[0]),
.I2(beg_FSM_IBUF),
.I3(ack_FSM_IBUF),
.I4(out[2]),
.I5(out[1]),
.O(\FSM_sequential_state_reg[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFA2F000F0A2F0))
\FSM_sequential_state_reg[3]_i_2
(.I0(out[0]),
.I1(FSM_selector_C),
.I2(out[3]),
.I3(out[2]),
.I4(out[1]),
.I5(\FSM_sequential_state_reg[3]_i_3_n_0 ),
.O(\FSM_sequential_state_reg[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h4050405041514050))
\FSM_sequential_state_reg[3]_i_3
(.I0(out[3]),
.I1(out[0]),
.I2(out[2]),
.I3(round_flag),
.I4(CO),
.I5(\Q_reg[31]_0 ),
.O(\FSM_sequential_state_reg[3]_i_3_n_0 ));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[0]
(.C(CLK),
.CE(\FSM_sequential_state_reg[3]_i_1_n_0 ),
.CLR(in1),
.D(\FSM_sequential_state_reg[0]_i_1_n_0 ),
.Q(out[0]));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[1]
(.C(CLK),
.CE(\FSM_sequential_state_reg[3]_i_1_n_0 ),
.CLR(in1),
.D(\FSM_sequential_state_reg[1]_i_1_n_0 ),
.Q(out[1]));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[2]
(.C(CLK),
.CE(\FSM_sequential_state_reg[3]_i_1_n_0 ),
.CLR(in1),
.D(\FSM_sequential_state_reg[2]_i_1_n_0 ),
.Q(out[2]));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[3]
(.C(CLK),
.CE(\FSM_sequential_state_reg[3]_i_1_n_0 ),
.CLR(in1),
.D(\FSM_sequential_state_reg[3]_i_2_n_0 ),
.Q(out[3]));
LUT4 #(
.INIT(16'h2800))
\Q[0]_i_1
(.I0(out[0]),
.I1(out[1]),
.I2(out[3]),
.I3(out[2]),
.O(\Q_reg[0]_4 ));
LUT4 #(
.INIT(16'h0001))
\Q[0]_i_1__0
(.I0(out[3]),
.I1(out[2]),
.I2(out[0]),
.I3(out[1]),
.O(AR));
LUT6 #(
.INIT(64'hFFFFFFFF00002000))
\Q[0]_i_1__10
(.I0(round_flag),
.I1(out[0]),
.I2(out[2]),
.I3(out[1]),
.I4(out[3]),
.I5(FSM_selector_D),
.O(\Q_reg[0]_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF00002000))
\Q[0]_i_1__11
(.I0(round_flag),
.I1(out[0]),
.I2(out[2]),
.I3(out[1]),
.I4(out[3]),
.I5(\Q_reg[0]_12 ),
.O(\Q_reg[0]_1 ));
LUT6 #(
.INIT(64'h0001FFFF00010000))
\Q[0]_i_1__12
(.I0(\Q_reg[1]_0 [0]),
.I1(\Q_reg[1]_0 [2]),
.I2(\Q_reg[1]_0 [1]),
.I3(\Q_reg[0]_13 ),
.I4(FSM_exp_operation_load_OU),
.I5(underflow_flag_OBUF),
.O(\Q_reg[0]_2 ));
LUT5 #(
.INIT(32'hFFFF0800))
\Q[0]_i_1__9
(.I0(out[3]),
.I1(out[0]),
.I2(out[1]),
.I3(out[2]),
.I4(FSM_selector_C),
.O(\Q_reg[0] ));
LUT5 #(
.INIT(32'h00300200))
\Q[0]_i_3
(.I0(FSM_selector_C),
.I1(out[1]),
.I2(out[3]),
.I3(out[2]),
.I4(out[0]),
.O(FSM_exp_operation_load_OU));
LUT6 #(
.INIT(64'h0FFFFF5FFFFFF7FF))
\Q[0]_i_4
(.I0(add_overflow_flag),
.I1(FSM_selector_C),
.I2(out[0]),
.I3(out[2]),
.I4(out[1]),
.I5(out[3]),
.O(S));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[21]_i_1
(.I0(\Q_reg[21] ),
.I1(FSM_barrel_shifter_B_S),
.I2(\Q_reg[2] ),
.I3(\Q_reg[0]_9 ),
.I4(\Q_reg[1] ),
.I5(\Q_reg[0]_10 ),
.O(\Q_reg[23] [0]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[23]_i_1__0
(.I0(FSM_barrel_shifter_B_S),
.I1(\Q_reg[2] ),
.I2(\Q_reg[0]_10 ),
.I3(\Q_reg[1] ),
.I4(\Q_reg[21] ),
.O(\Q_reg[23] [1]));
LUT4 #(
.INIT(16'h0420))
\Q[25]_i_1
(.I0(out[3]),
.I1(out[2]),
.I2(out[1]),
.I3(out[0]),
.O(\Q_reg[0]_7 ));
LUT6 #(
.INIT(64'hB888B888BBBB88BB))
\Q[25]_i_3
(.I0(FSM_barrel_shifter_B_S),
.I1(\Q_reg[0]_11 ),
.I2(Q[0]),
.I3(FSM_selector_C),
.I4(Q[1]),
.I5(FSM_barrel_shifter_L_R),
.O(\Q_reg[21] ));
LUT5 #(
.INIT(32'h00001000))
\Q[25]_i_4
(.I0(out[1]),
.I1(out[3]),
.I2(out[2]),
.I3(FSM_selector_C),
.I4(add_overflow_flag),
.O(FSM_barrel_shifter_L_R));
LUT6 #(
.INIT(64'h00080C000008C000))
\Q[25]_i_7
(.I0(FSM_selector_C),
.I1(add_overflow_flag),
.I2(out[1]),
.I3(out[3]),
.I4(out[2]),
.I5(out[0]),
.O(FSM_barrel_shifter_B_S));
LUT4 #(
.INIT(16'h0010))
\Q[30]_i_1
(.I0(out[3]),
.I1(out[2]),
.I2(out[1]),
.I3(out[0]),
.O(\Q_reg[0]_6 ));
LUT4 #(
.INIT(16'h0010))
\Q[31]_i_1
(.I0(out[3]),
.I1(out[2]),
.I2(out[0]),
.I3(out[1]),
.O(\Q_reg[0]_5 ));
LUT4 #(
.INIT(16'h4000))
\Q[31]_i_1__0
(.I0(out[2]),
.I1(out[3]),
.I2(out[0]),
.I3(out[1]),
.O(E));
LUT4 #(
.INIT(16'h0001))
\Q[31]_i_2
(.I0(out[3]),
.I1(out[2]),
.I2(out[0]),
.I3(out[1]),
.O(\Q_reg[31] [1]));
LUT6 #(
.INIT(64'h0FFFFF5FFFFFF7FF))
\Q[3]_i_6
(.I0(add_overflow_flag),
.I1(FSM_selector_C),
.I2(out[0]),
.I3(out[2]),
.I4(out[1]),
.I5(out[3]),
.O(FSM_exp_operation_A_S));
LUT4 #(
.INIT(16'h2000))
\Q[4]_i_1
(.I0(out[2]),
.I1(out[0]),
.I2(out[3]),
.I3(out[1]),
.O(\Q_reg[0]_8 ));
LUT4 #(
.INIT(16'h0224))
\Q[7]_i_1
(.I0(out[0]),
.I1(out[2]),
.I2(out[3]),
.I3(out[1]),
.O(\Q_reg[0]_3 ));
LUT4 #(
.INIT(16'h0001))
\Q[7]_i_2
(.I0(out[3]),
.I1(out[2]),
.I2(out[0]),
.I3(out[1]),
.O(\Q_reg[31] [0]));
LUT4 #(
.INIT(16'h1000))
ready_OBUF_inst_i_1
(.I0(out[0]),
.I1(out[1]),
.I2(out[3]),
.I3(out[2]),
.O(ready_OBUF));
endmodule
module LZD
(Q,
E,
D,
CLK,
\FSM_sequential_state_reg_reg[3] );
output [4:0]Q;
input [0:0]E;
input [4:0]D;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[3] ;
wire CLK;
wire [4:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[3] ;
wire [4:0]Q;
RegisterAdd__parameterized9 Output_Reg
(.CLK(CLK),
.D(D),
.E(E),
.\FSM_sequential_state_reg_reg[3] (\FSM_sequential_state_reg_reg[3] ),
.Q(Q));
endmodule
module Mux_Array
(D,
\Q_reg[16] ,
Q,
\Q_reg[25] ,
\Q_reg[17] ,
\Q_reg[24] ,
\Q_reg[18] ,
\Q_reg[23] ,
\Q_reg[19] ,
\Q_reg[22] ,
\Q_reg[20] ,
\Q_reg[21] ,
FSM_barrel_shifter_L_R,
\Q_reg[16]_0 ,
FSM_barrel_shifter_B_S,
\Q_reg[4] ,
\Q_reg[3] ,
\Q_reg[17]_0 ,
\Q_reg[2] ,
CLK,
\FSM_sequential_state_reg_reg[3] );
output [9:0]D;
output \Q_reg[16] ;
output [15:0]Q;
output \Q_reg[25] ;
output \Q_reg[17] ;
output \Q_reg[24] ;
output \Q_reg[18] ;
output \Q_reg[23] ;
output \Q_reg[19] ;
output \Q_reg[22] ;
output \Q_reg[20] ;
output \Q_reg[21] ;
input FSM_barrel_shifter_L_R;
input \Q_reg[16]_0 ;
input FSM_barrel_shifter_B_S;
input \Q_reg[4] ;
input \Q_reg[3] ;
input \Q_reg[17]_0 ;
input [25:0]\Q_reg[2] ;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[3] ;
wire CLK;
wire [9:0]D;
wire FSM_barrel_shifter_B_S;
wire FSM_barrel_shifter_L_R;
wire [0:0]\FSM_sequential_state_reg_reg[3] ;
wire [15:0]Q;
wire \Q_reg[16] ;
wire \Q_reg[16]_0 ;
wire \Q_reg[17] ;
wire \Q_reg[17]_0 ;
wire \Q_reg[18] ;
wire \Q_reg[19] ;
wire \Q_reg[20] ;
wire \Q_reg[21] ;
wire \Q_reg[22] ;
wire \Q_reg[23] ;
wire \Q_reg[24] ;
wire \Q_reg[25] ;
wire [25:0]\Q_reg[2] ;
wire \Q_reg[3] ;
wire \Q_reg[4] ;
RegisterAdd__parameterized6 Mid_Reg
(.CLK(CLK),
.D(D),
.FSM_barrel_shifter_B_S(FSM_barrel_shifter_B_S),
.FSM_barrel_shifter_L_R(FSM_barrel_shifter_L_R),
.\FSM_sequential_state_reg_reg[3] (\FSM_sequential_state_reg_reg[3] ),
.Q(Q),
.\Q_reg[16]_0 (\Q_reg[16] ),
.\Q_reg[16]_1 (\Q_reg[16]_0 ),
.\Q_reg[17]_0 (\Q_reg[17] ),
.\Q_reg[17]_1 (\Q_reg[17]_0 ),
.\Q_reg[18]_0 (\Q_reg[18] ),
.\Q_reg[19]_0 (\Q_reg[19] ),
.\Q_reg[20]_0 (\Q_reg[20] ),
.\Q_reg[21]_0 (\Q_reg[21] ),
.\Q_reg[22]_0 (\Q_reg[22] ),
.\Q_reg[23]_0 (\Q_reg[23] ),
.\Q_reg[24]_0 (\Q_reg[24] ),
.\Q_reg[25]_0 (\Q_reg[25] ),
.\Q_reg[2]_0 (\Q_reg[2] ),
.\Q_reg[3]_0 (\Q_reg[3] ),
.\Q_reg[4]_0 (\Q_reg[4] ));
endmodule
module Oper_Start_In
(intAS,
sign_final_result,
CO,
\Q_reg[23] ,
O,
zero_flag,
Q,
\Q_reg[0] ,
\FSM_sequential_state_reg_reg[3] ,
\Q_reg[7] ,
\Q_reg[7]_0 ,
E,
add_subt_IBUF,
CLK,
AR,
\FSM_sequential_state_reg_reg[3]_0 ,
\FSM_sequential_state_reg_reg[3]_1 ,
\Q_reg[0]_0 ,
S,
\Q_reg[31] ,
\Q_reg[31]_0 ,
\Q_reg[31]_1 ,
\Q_reg[31]_2 ,
\Q_reg[31]_3 ,
\Q_reg[31]_4 ,
FSM_selector_D,
\Q_reg[25] ,
D,
\Data_X[31] );
output intAS;
output sign_final_result;
output [0:0]CO;
output [23:0]\Q_reg[23] ;
output [2:0]O;
output zero_flag;
output [0:0]Q;
output [0:0]\Q_reg[0] ;
output \FSM_sequential_state_reg_reg[3] ;
output [30:0]\Q_reg[7] ;
output [30:0]\Q_reg[7]_0 ;
input [0:0]E;
input add_subt_IBUF;
input CLK;
input [0:0]AR;
input [0:0]\FSM_sequential_state_reg_reg[3]_0 ;
input [1:0]\FSM_sequential_state_reg_reg[3]_1 ;
input \Q_reg[0]_0 ;
input [3:0]S;
input [3:0]\Q_reg[31] ;
input [3:0]\Q_reg[31]_0 ;
input [3:0]\Q_reg[31]_1 ;
input [3:0]\Q_reg[31]_2 ;
input [3:0]\Q_reg[31]_3 ;
input [1:0]\Q_reg[31]_4 ;
input FSM_selector_D;
input [24:0]\Q_reg[25] ;
input [31:0]D;
input [31:0]\Data_X[31] ;
wire [0:0]AR;
wire CLK;
wire [0:0]CO;
wire [31:0]D;
wire [31:0]\Data_X[31] ;
wire [0:0]E;
wire FSM_selector_D;
wire \FSM_sequential_state_reg_reg[3] ;
wire [0:0]\FSM_sequential_state_reg_reg[3]_0 ;
wire [1:0]\FSM_sequential_state_reg_reg[3]_1 ;
wire [2:0]O;
wire [0:0]Q;
wire [0:0]\Q_reg[0] ;
wire \Q_reg[0]_0 ;
wire [23:0]\Q_reg[23] ;
wire [24:0]\Q_reg[25] ;
wire [3:0]\Q_reg[31] ;
wire [3:0]\Q_reg[31]_0 ;
wire [3:0]\Q_reg[31]_1 ;
wire [3:0]\Q_reg[31]_2 ;
wire [3:0]\Q_reg[31]_3 ;
wire [1:0]\Q_reg[31]_4 ;
wire [30:0]\Q_reg[7] ;
wire [30:0]\Q_reg[7]_0 ;
wire [3:0]S;
wire XRegister_n_10;
wire XRegister_n_100;
wire XRegister_n_101;
wire XRegister_n_102;
wire XRegister_n_103;
wire XRegister_n_104;
wire XRegister_n_105;
wire XRegister_n_106;
wire XRegister_n_107;
wire XRegister_n_108;
wire XRegister_n_109;
wire XRegister_n_11;
wire XRegister_n_110;
wire XRegister_n_111;
wire XRegister_n_112;
wire XRegister_n_113;
wire XRegister_n_114;
wire XRegister_n_115;
wire XRegister_n_116;
wire XRegister_n_117;
wire XRegister_n_118;
wire XRegister_n_119;
wire XRegister_n_12;
wire XRegister_n_120;
wire XRegister_n_121;
wire XRegister_n_122;
wire XRegister_n_123;
wire XRegister_n_124;
wire XRegister_n_125;
wire XRegister_n_126;
wire XRegister_n_127;
wire XRegister_n_128;
wire XRegister_n_129;
wire XRegister_n_13;
wire XRegister_n_130;
wire XRegister_n_131;
wire XRegister_n_132;
wire XRegister_n_133;
wire XRegister_n_134;
wire XRegister_n_135;
wire XRegister_n_136;
wire XRegister_n_137;
wire XRegister_n_138;
wire XRegister_n_139;
wire XRegister_n_14;
wire XRegister_n_140;
wire XRegister_n_141;
wire XRegister_n_142;
wire XRegister_n_143;
wire XRegister_n_144;
wire XRegister_n_145;
wire XRegister_n_15;
wire XRegister_n_16;
wire XRegister_n_17;
wire XRegister_n_18;
wire XRegister_n_19;
wire XRegister_n_2;
wire XRegister_n_20;
wire XRegister_n_21;
wire XRegister_n_22;
wire XRegister_n_23;
wire XRegister_n_24;
wire XRegister_n_25;
wire XRegister_n_26;
wire XRegister_n_27;
wire XRegister_n_28;
wire XRegister_n_29;
wire XRegister_n_3;
wire XRegister_n_30;
wire XRegister_n_31;
wire XRegister_n_32;
wire XRegister_n_33;
wire XRegister_n_34;
wire XRegister_n_35;
wire XRegister_n_36;
wire XRegister_n_37;
wire XRegister_n_38;
wire XRegister_n_39;
wire XRegister_n_4;
wire XRegister_n_40;
wire XRegister_n_41;
wire XRegister_n_42;
wire XRegister_n_43;
wire XRegister_n_44;
wire XRegister_n_45;
wire XRegister_n_46;
wire XRegister_n_47;
wire XRegister_n_48;
wire XRegister_n_49;
wire XRegister_n_5;
wire XRegister_n_50;
wire XRegister_n_51;
wire XRegister_n_52;
wire XRegister_n_53;
wire XRegister_n_54;
wire XRegister_n_55;
wire XRegister_n_56;
wire XRegister_n_57;
wire XRegister_n_58;
wire XRegister_n_59;
wire XRegister_n_6;
wire XRegister_n_60;
wire XRegister_n_61;
wire XRegister_n_62;
wire XRegister_n_63;
wire XRegister_n_64;
wire XRegister_n_65;
wire XRegister_n_66;
wire XRegister_n_67;
wire XRegister_n_68;
wire XRegister_n_69;
wire XRegister_n_7;
wire XRegister_n_70;
wire XRegister_n_71;
wire XRegister_n_72;
wire XRegister_n_73;
wire XRegister_n_74;
wire XRegister_n_75;
wire XRegister_n_76;
wire XRegister_n_77;
wire XRegister_n_78;
wire XRegister_n_79;
wire XRegister_n_8;
wire XRegister_n_80;
wire XRegister_n_81;
wire XRegister_n_82;
wire XRegister_n_83;
wire XRegister_n_84;
wire XRegister_n_85;
wire XRegister_n_86;
wire XRegister_n_87;
wire XRegister_n_88;
wire XRegister_n_89;
wire XRegister_n_9;
wire XRegister_n_90;
wire XRegister_n_91;
wire XRegister_n_92;
wire XRegister_n_93;
wire XRegister_n_94;
wire XRegister_n_95;
wire XRegister_n_96;
wire XRegister_n_97;
wire XRegister_n_98;
wire XRegister_n_99;
wire YRegister_n_28;
wire YRegister_n_29;
wire YRegister_n_30;
wire YRegister_n_31;
wire YRegister_n_32;
wire YRegister_n_33;
wire YRegister_n_34;
wire YRegister_n_35;
wire YRegister_n_36;
wire YRegister_n_37;
wire YRegister_n_38;
wire YRegister_n_39;
wire YRegister_n_40;
wire YRegister_n_41;
wire YRegister_n_42;
wire YRegister_n_43;
wire YRegister_n_44;
wire YRegister_n_45;
wire YRegister_n_46;
wire YRegister_n_47;
wire YRegister_n_48;
wire YRegister_n_49;
wire YRegister_n_50;
wire YRegister_n_51;
wire YRegister_n_52;
wire YRegister_n_53;
wire YRegister_n_54;
wire YRegister_n_55;
wire YRegister_n_56;
wire YRegister_n_57;
wire YRegister_n_58;
wire YRegister_n_59;
wire YRegister_n_60;
wire YRegister_n_61;
wire YRegister_n_62;
wire YRegister_n_63;
wire YRegister_n_64;
wire YRegister_n_65;
wire YRegister_n_66;
wire YRegister_n_67;
wire YRegister_n_68;
wire YRegister_n_69;
wire YRegister_n_70;
wire YRegister_n_71;
wire YRegister_n_72;
wire YRegister_n_73;
wire YRegister_n_74;
wire YRegister_n_75;
wire add_subt_IBUF;
wire gtXY;
wire intAS;
wire sign_final_result;
wire sign_result;
wire zero_flag;
RegisterAdd_2 ASRegister
(.AR(AR),
.CLK(CLK),
.E(E),
.\Q_reg[0]_0 (intAS),
.add_subt_IBUF(add_subt_IBUF));
RegisterAdd__parameterized3 MRegister
(.CLK(CLK),
.D({XRegister_n_59,XRegister_n_60,XRegister_n_61,XRegister_n_62,XRegister_n_63,XRegister_n_64,XRegister_n_65,XRegister_n_66,XRegister_n_67,XRegister_n_68,XRegister_n_69,XRegister_n_70,XRegister_n_71,XRegister_n_72,XRegister_n_73,XRegister_n_74,XRegister_n_75,XRegister_n_76,XRegister_n_77,XRegister_n_78,XRegister_n_79,XRegister_n_80,XRegister_n_81,XRegister_n_82,XRegister_n_83,XRegister_n_84,XRegister_n_85,XRegister_n_86,XRegister_n_87,XRegister_n_88,XRegister_n_89}),
.\FSM_sequential_state_reg_reg[3] (\FSM_sequential_state_reg_reg[3]_0 ),
.\FSM_sequential_state_reg_reg[3]_0 (\FSM_sequential_state_reg_reg[3]_1 ),
.\Q_reg[7]_0 (\Q_reg[7] ));
Comparator Magnitude_Comparator
(.CO(gtXY),
.DI({XRegister_n_37,XRegister_n_38,XRegister_n_39,XRegister_n_40}),
.Q(Q),
.\Q_reg[0] (CO),
.\Q_reg[0]_0 (intAS),
.\Q_reg[10] ({XRegister_n_33,XRegister_n_34,XRegister_n_35,XRegister_n_36}),
.\Q_reg[15] ({XRegister_n_41,XRegister_n_42,XRegister_n_43,XRegister_n_44}),
.\Q_reg[15]_0 ({YRegister_n_63,YRegister_n_64,YRegister_n_65,YRegister_n_66}),
.\Q_reg[22] ({XRegister_n_45,XRegister_n_46,XRegister_n_47,XRegister_n_48}),
.\Q_reg[23] ({XRegister_n_49,XRegister_n_50,XRegister_n_51,XRegister_n_52}),
.\Q_reg[23]_0 ({YRegister_n_67,YRegister_n_68,YRegister_n_69,YRegister_n_70}),
.\Q_reg[30] ({XRegister_n_55,XRegister_n_56,XRegister_n_57,XRegister_n_58}),
.\Q_reg[30]_0 ({YRegister_n_71,YRegister_n_72,YRegister_n_73,YRegister_n_74}),
.\Q_reg[30]_1 ({YRegister_n_75,XRegister_n_53,XRegister_n_54}),
.\Q_reg[31] (\Q_reg[0] ),
.S({YRegister_n_59,YRegister_n_60,YRegister_n_61,YRegister_n_62}),
.zero_flag(zero_flag));
RegisterAdd_3 SignRegister
(.CLK(CLK),
.\FSM_sequential_state_reg_reg[3] (\FSM_sequential_state_reg_reg[3]_0 ),
.\FSM_sequential_state_reg_reg[3]_0 (\FSM_sequential_state_reg_reg[3]_1 [0]),
.sign_final_result(sign_final_result),
.sign_result(sign_result));
RegisterAdd__parameterized1 XRegister
(.CLK(CLK),
.CO(CO),
.D({XRegister_n_59,XRegister_n_60,XRegister_n_61,XRegister_n_62,XRegister_n_63,XRegister_n_64,XRegister_n_65,XRegister_n_66,XRegister_n_67,XRegister_n_68,XRegister_n_69,XRegister_n_70,XRegister_n_71,XRegister_n_72,XRegister_n_73,XRegister_n_74,XRegister_n_75,XRegister_n_76,XRegister_n_77,XRegister_n_78,XRegister_n_79,XRegister_n_80,XRegister_n_81,XRegister_n_82,XRegister_n_83,XRegister_n_84,XRegister_n_85,XRegister_n_86,XRegister_n_87,XRegister_n_88,XRegister_n_89}),
.DI({XRegister_n_37,XRegister_n_38,XRegister_n_39,XRegister_n_40}),
.\Data_X[31] (\Data_X[31] ),
.E(E),
.FSM_selector_D(FSM_selector_D),
.\FSM_sequential_state_reg_reg[3] (\FSM_sequential_state_reg_reg[3] ),
.\FSM_sequential_state_reg_reg[3]_0 (\FSM_sequential_state_reg_reg[3]_1 [1]),
.Q({\Q_reg[0] ,XRegister_n_2,XRegister_n_3,XRegister_n_4,XRegister_n_5,XRegister_n_6,XRegister_n_7,XRegister_n_8,XRegister_n_9,XRegister_n_10,XRegister_n_11,XRegister_n_12,XRegister_n_13,XRegister_n_14,XRegister_n_15,XRegister_n_16,XRegister_n_17,XRegister_n_18,XRegister_n_19,XRegister_n_20,XRegister_n_21,XRegister_n_22,XRegister_n_23,XRegister_n_24,XRegister_n_25,XRegister_n_26,XRegister_n_27,XRegister_n_28,XRegister_n_29,XRegister_n_30,XRegister_n_31,XRegister_n_32}),
.\Q_reg[0]_0 ({XRegister_n_33,XRegister_n_34,XRegister_n_35,XRegister_n_36}),
.\Q_reg[0]_1 ({XRegister_n_41,XRegister_n_42,XRegister_n_43,XRegister_n_44}),
.\Q_reg[0]_2 ({XRegister_n_45,XRegister_n_46,XRegister_n_47,XRegister_n_48}),
.\Q_reg[0]_3 ({XRegister_n_49,XRegister_n_50,XRegister_n_51,XRegister_n_52}),
.\Q_reg[0]_4 ({XRegister_n_53,XRegister_n_54}),
.\Q_reg[0]_5 ({XRegister_n_55,XRegister_n_56,XRegister_n_57,XRegister_n_58}),
.\Q_reg[0]_6 ({XRegister_n_144,XRegister_n_145}),
.\Q_reg[0]_7 (intAS),
.\Q_reg[11]_0 ({XRegister_n_128,XRegister_n_129,XRegister_n_130,XRegister_n_131}),
.\Q_reg[15]_0 ({XRegister_n_132,XRegister_n_133,XRegister_n_134,XRegister_n_135}),
.\Q_reg[19]_0 ({XRegister_n_136,XRegister_n_137,XRegister_n_138,XRegister_n_139}),
.\Q_reg[23]_0 ({XRegister_n_140,XRegister_n_141,XRegister_n_142,XRegister_n_143}),
.\Q_reg[25]_0 (\Q_reg[25] ),
.\Q_reg[30]_0 ({XRegister_n_90,XRegister_n_91,XRegister_n_92,XRegister_n_93,XRegister_n_94,XRegister_n_95,XRegister_n_96,XRegister_n_97,XRegister_n_98,XRegister_n_99,XRegister_n_100,XRegister_n_101,XRegister_n_102,XRegister_n_103,XRegister_n_104,XRegister_n_105,XRegister_n_106,XRegister_n_107,XRegister_n_108,XRegister_n_109,XRegister_n_110,XRegister_n_111,XRegister_n_112,XRegister_n_113,XRegister_n_114,XRegister_n_115,XRegister_n_116,XRegister_n_117,XRegister_n_118,XRegister_n_119,XRegister_n_120}),
.\Q_reg[30]_1 (gtXY),
.\Q_reg[31]_0 ({Q,YRegister_n_28,YRegister_n_29,YRegister_n_30,YRegister_n_31,YRegister_n_32,YRegister_n_33,YRegister_n_34,YRegister_n_35,YRegister_n_36,YRegister_n_37,YRegister_n_38,YRegister_n_39,YRegister_n_40,YRegister_n_41,YRegister_n_42,YRegister_n_43,YRegister_n_44,YRegister_n_45,YRegister_n_46,YRegister_n_47,YRegister_n_48,YRegister_n_49,YRegister_n_50,YRegister_n_51,YRegister_n_52,YRegister_n_53,YRegister_n_54,YRegister_n_55,YRegister_n_56,YRegister_n_57,YRegister_n_58}),
.\Q_reg[3]_0 ({XRegister_n_121,XRegister_n_122,XRegister_n_123}),
.\Q_reg[7]_0 ({XRegister_n_124,XRegister_n_125,XRegister_n_126,XRegister_n_127}),
.sign_result(sign_result));
RegisterAdd__parameterized2 YRegister
(.CLK(CLK),
.D(D),
.E(E),
.FSM_selector_D(FSM_selector_D),
.\FSM_sequential_state_reg_reg[3] (\FSM_sequential_state_reg_reg[3]_1 [1]),
.O(O),
.Q({Q,YRegister_n_28,YRegister_n_29,YRegister_n_30,YRegister_n_31,YRegister_n_32,YRegister_n_33,YRegister_n_34,YRegister_n_35,YRegister_n_36,YRegister_n_37,YRegister_n_38,YRegister_n_39,YRegister_n_40,YRegister_n_41,YRegister_n_42,YRegister_n_43,YRegister_n_44,YRegister_n_45,YRegister_n_46,YRegister_n_47,YRegister_n_48,YRegister_n_49,YRegister_n_50,YRegister_n_51,YRegister_n_52,YRegister_n_53,YRegister_n_54,YRegister_n_55,YRegister_n_56,YRegister_n_57,YRegister_n_58}),
.\Q_reg[0]_0 ({YRegister_n_59,YRegister_n_60,YRegister_n_61,YRegister_n_62}),
.\Q_reg[0]_1 ({YRegister_n_63,YRegister_n_64,YRegister_n_65,YRegister_n_66}),
.\Q_reg[0]_2 ({YRegister_n_67,YRegister_n_68,YRegister_n_69,YRegister_n_70}),
.\Q_reg[0]_3 ({YRegister_n_71,YRegister_n_72,YRegister_n_73,YRegister_n_74}),
.\Q_reg[0]_4 (YRegister_n_75),
.\Q_reg[0]_5 (\Q_reg[0]_0 ),
.\Q_reg[0]_6 (intAS),
.\Q_reg[23]_0 (\Q_reg[23] ),
.\Q_reg[31]_0 ({XRegister_n_121,XRegister_n_122,XRegister_n_123}),
.\Q_reg[31]_1 ({XRegister_n_124,XRegister_n_125,XRegister_n_126,XRegister_n_127}),
.\Q_reg[31]_10 (\Q_reg[31]_3 ),
.\Q_reg[31]_11 ({XRegister_n_144,XRegister_n_145}),
.\Q_reg[31]_12 (\Q_reg[31]_4 ),
.\Q_reg[31]_13 ({\Q_reg[0] ,XRegister_n_2,XRegister_n_3,XRegister_n_4,XRegister_n_5,XRegister_n_6,XRegister_n_7,XRegister_n_8,XRegister_n_9,XRegister_n_10,XRegister_n_11,XRegister_n_12,XRegister_n_13,XRegister_n_14,XRegister_n_15,XRegister_n_16,XRegister_n_17,XRegister_n_18,XRegister_n_19,XRegister_n_20,XRegister_n_21,XRegister_n_22,XRegister_n_23,XRegister_n_24,XRegister_n_25,XRegister_n_26,XRegister_n_27,XRegister_n_28,XRegister_n_29,XRegister_n_30,XRegister_n_31,XRegister_n_32}),
.\Q_reg[31]_2 (\Q_reg[31] ),
.\Q_reg[31]_3 ({XRegister_n_128,XRegister_n_129,XRegister_n_130,XRegister_n_131}),
.\Q_reg[31]_4 (\Q_reg[31]_0 ),
.\Q_reg[31]_5 ({XRegister_n_132,XRegister_n_133,XRegister_n_134,XRegister_n_135}),
.\Q_reg[31]_6 (\Q_reg[31]_1 ),
.\Q_reg[31]_7 ({XRegister_n_136,XRegister_n_137,XRegister_n_138,XRegister_n_139}),
.\Q_reg[31]_8 (\Q_reg[31]_2 ),
.\Q_reg[31]_9 ({XRegister_n_140,XRegister_n_141,XRegister_n_142,XRegister_n_143}),
.S(S));
RegisterAdd__parameterized4 mRegister
(.CLK(CLK),
.D({XRegister_n_90,XRegister_n_91,XRegister_n_92,XRegister_n_93,XRegister_n_94,XRegister_n_95,XRegister_n_96,XRegister_n_97,XRegister_n_98,XRegister_n_99,XRegister_n_100,XRegister_n_101,XRegister_n_102,XRegister_n_103,XRegister_n_104,XRegister_n_105,XRegister_n_106,XRegister_n_107,XRegister_n_108,XRegister_n_109,XRegister_n_110,XRegister_n_111,XRegister_n_112,XRegister_n_113,XRegister_n_114,XRegister_n_115,XRegister_n_116,XRegister_n_117,XRegister_n_118,XRegister_n_119,XRegister_n_120}),
.\FSM_sequential_state_reg_reg[3] (\FSM_sequential_state_reg_reg[3]_0 ),
.\FSM_sequential_state_reg_reg[3]_0 (\FSM_sequential_state_reg_reg[3]_1 [0]),
.\Q_reg[7]_0 (\Q_reg[7]_0 ));
endmodule
module RegisterAdd
(\Q_reg[0]_0 ,
\FSM_sequential_state_reg_reg[0] ,
CLK,
\FSM_sequential_state_reg_reg[3] );
output \Q_reg[0]_0 ;
input \FSM_sequential_state_reg_reg[0] ;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[3] ;
wire CLK;
wire \FSM_sequential_state_reg_reg[0] ;
wire [0:0]\FSM_sequential_state_reg_reg[3] ;
wire \Q_reg[0]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\FSM_sequential_state_reg_reg[0] ),
.Q(\Q_reg[0]_0 ));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd_0
(FSM_selector_C,
\FSM_sequential_state_reg_reg[3] ,
CLK,
\FSM_sequential_state_reg_reg[3]_0 );
output FSM_selector_C;
input \FSM_sequential_state_reg_reg[3] ;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[3]_0 ;
wire CLK;
wire FSM_selector_C;
wire \FSM_sequential_state_reg_reg[3] ;
wire [0:0]\FSM_sequential_state_reg_reg[3]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\FSM_sequential_state_reg_reg[3] ),
.Q(FSM_selector_C));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd_1
(FSM_selector_D,
\Q_reg[3] ,
\FSM_sequential_state_reg_reg[0] ,
CLK,
\FSM_sequential_state_reg_reg[3] ,
\Q_reg[0]_0 );
output FSM_selector_D;
output \Q_reg[3] ;
input \FSM_sequential_state_reg_reg[0] ;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[3] ;
input [0:0]\Q_reg[0]_0 ;
wire CLK;
wire FSM_selector_D;
wire \FSM_sequential_state_reg_reg[0] ;
wire [0:0]\FSM_sequential_state_reg_reg[3] ;
wire [0:0]\Q_reg[0]_0 ;
wire \Q_reg[3] ;
LUT2 #(
.INIT(4'h8))
\Q[3]_i_2__0
(.I0(FSM_selector_D),
.I1(\Q_reg[0]_0 ),
.O(\Q_reg[3] ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\FSM_sequential_state_reg_reg[0] ),
.Q(FSM_selector_D));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd_2
(\Q_reg[0]_0 ,
E,
add_subt_IBUF,
CLK,
AR);
output \Q_reg[0]_0 ;
input [0:0]E;
input add_subt_IBUF;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]E;
wire \Q_reg[0]_0 ;
wire add_subt_IBUF;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(add_subt_IBUF),
.Q(\Q_reg[0]_0 ));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd_3
(sign_final_result,
\FSM_sequential_state_reg_reg[3] ,
sign_result,
CLK,
\FSM_sequential_state_reg_reg[3]_0 );
output sign_final_result;
input [0:0]\FSM_sequential_state_reg_reg[3] ;
input sign_result;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[3]_0 ;
wire CLK;
wire [0:0]\FSM_sequential_state_reg_reg[3] ;
wire [0:0]\FSM_sequential_state_reg_reg[3]_0 ;
wire sign_final_result;
wire sign_result;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(sign_result),
.Q(sign_final_result));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd_4
(\Q_reg[22] ,
D,
E,
CLK,
AR,
\Q_reg[24] ,
\Q_reg[0]_0 ,
O,
\Q_reg[1] );
output \Q_reg[22] ;
output [22:0]D;
input [0:0]E;
input CLK;
input [0:0]AR;
input [22:0]\Q_reg[24] ;
input \Q_reg[0]_0 ;
input [0:0]O;
input [7:0]\Q_reg[1] ;
wire [0:0]AR;
wire CLK;
wire [22:0]D;
wire [0:0]E;
wire [0:0]O;
wire \Q[0]_i_1__8_n_0 ;
wire \Q[0]_i_3__1_n_0 ;
wire \Q_reg[0]_0 ;
wire [7:0]\Q_reg[1] ;
wire \Q_reg[22] ;
wire [22:0]\Q_reg[24] ;
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'h02))
\Q[0]_i_1__5
(.I0(\Q_reg[24] [0]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[0]));
LUT6 #(
.INIT(64'hBAAAAAAAAAAAAAAA))
\Q[0]_i_1__8
(.I0(O),
.I1(\Q[0]_i_3__1_n_0 ),
.I2(\Q_reg[1] [6]),
.I3(\Q_reg[1] [4]),
.I4(\Q_reg[1] [7]),
.I5(\Q_reg[1] [5]),
.O(\Q[0]_i_1__8_n_0 ));
LUT4 #(
.INIT(16'h7FFF))
\Q[0]_i_3__1
(.I0(\Q_reg[1] [1]),
.I1(\Q_reg[1] [3]),
.I2(\Q_reg[1] [2]),
.I3(\Q_reg[1] [0]),
.O(\Q[0]_i_3__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'h02))
\Q[10]_i_1__1
(.I0(\Q_reg[24] [10]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[10]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'h02))
\Q[11]_i_1__1
(.I0(\Q_reg[24] [11]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[11]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h02))
\Q[12]_i_1__1
(.I0(\Q_reg[24] [12]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[12]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h02))
\Q[13]_i_1__1
(.I0(\Q_reg[24] [13]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[13]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'h02))
\Q[14]_i_1__1
(.I0(\Q_reg[24] [14]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[14]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'h02))
\Q[15]_i_1__1
(.I0(\Q_reg[24] [15]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[15]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h02))
\Q[16]_i_1__1
(.I0(\Q_reg[24] [16]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[16]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h02))
\Q[17]_i_1__1
(.I0(\Q_reg[24] [17]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[17]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h02))
\Q[18]_i_1__1
(.I0(\Q_reg[24] [18]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[18]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h02))
\Q[19]_i_1__1
(.I0(\Q_reg[24] [19]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[19]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'h02))
\Q[1]_i_1__2
(.I0(\Q_reg[24] [1]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'h02))
\Q[20]_i_1__1
(.I0(\Q_reg[24] [20]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[20]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'h02))
\Q[21]_i_1__1
(.I0(\Q_reg[24] [21]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[21]));
LUT3 #(
.INIT(8'h02))
\Q[22]_i_1__1
(.I0(\Q_reg[24] [22]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[22]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h02))
\Q[2]_i_1__2
(.I0(\Q_reg[24] [2]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h02))
\Q[3]_i_1__2
(.I0(\Q_reg[24] [3]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'h02))
\Q[4]_i_1__2
(.I0(\Q_reg[24] [4]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'h02))
\Q[5]_i_1__1
(.I0(\Q_reg[24] [5]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h02))
\Q[6]_i_1__1
(.I0(\Q_reg[24] [6]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h02))
\Q[7]_i_1__2
(.I0(\Q_reg[24] [7]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[7]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h02))
\Q[8]_i_1__1
(.I0(\Q_reg[24] [8]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[8]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h02))
\Q[9]_i_1__1
(.I0(\Q_reg[24] [9]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[9]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q[0]_i_1__8_n_0 ),
.Q(\Q_reg[22] ));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd_5
(\Q_reg[31] ,
D,
\Q_reg[0]_0 ,
\Q_reg[0]_1 ,
CLK,
AR,
sign_final_result,
\Q_reg[0]_2 ,
O,
\Q_reg[1] );
output \Q_reg[31] ;
output [0:0]D;
output \Q_reg[0]_0 ;
input \Q_reg[0]_1 ;
input CLK;
input [0:0]AR;
input sign_final_result;
input \Q_reg[0]_2 ;
input [0:0]O;
input [4:0]\Q_reg[1] ;
wire [0:0]AR;
wire CLK;
wire [0:0]D;
wire [0:0]O;
wire \Q_reg[0]_0 ;
wire \Q_reg[0]_1 ;
wire \Q_reg[0]_2 ;
wire [4:0]\Q_reg[1] ;
wire \Q_reg[31] ;
wire sign_final_result;
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\Q[0]_i_2__1
(.I0(O),
.I1(\Q_reg[1] [1]),
.I2(\Q_reg[1] [3]),
.I3(\Q_reg[1] [4]),
.I4(\Q_reg[1] [0]),
.I5(\Q_reg[1] [2]),
.O(\Q_reg[0]_0 ));
LUT3 #(
.INIT(8'h0E))
\Q[31]_i_2__0
(.I0(sign_final_result),
.I1(\Q_reg[31] ),
.I2(\Q_reg[0]_2 ),
.O(D));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg[0]_1 ),
.Q(\Q_reg[31] ));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd_6
(add_overflow_flag,
E,
O,
CLK,
AR);
output add_overflow_flag;
input [0:0]E;
input [0:0]O;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]E;
wire [0:0]O;
wire add_overflow_flag;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(O),
.Q(add_overflow_flag));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized0
(\Q_reg[7] ,
\Q_reg[3] ,
DI,
O,
\Q_reg[25] ,
\Q_reg[25]_0 ,
\Q_reg[25]_1 ,
D,
\Q_reg[9] ,
\Q_reg[0]_0 ,
\Q_reg[0]_1 ,
\Q_reg[8] ,
FSM_selector_B,
\Q_reg[21] ,
\Q_reg[7]_0 ,
Data_A,
FSM_exp_operation_A_S,
\Q_reg[26] ,
S,
\Q_reg[0]_2 ,
\Q_reg[0]_3 ,
FSM_barrel_shifter_B_S,
\Q_reg[0]_4 ,
FSM_barrel_shifter_L_R,
\Q_reg[25]_2 ,
Q,
\Q_reg[16] ,
\Q_reg[24] ,
\Q_reg[17] ,
\Q_reg[23] ,
\Q_reg[18] ,
\Q_reg[22] ,
\Q_reg[19] ,
\Q_reg[21]_0 ,
\Q_reg[20] ,
\Q_reg[0]_5 ,
\Q_reg[4] ,
\Q_reg[4]_0 ,
\Q_reg[30] ,
add_overflow_flag,
out,
CLK,
\FSM_sequential_state_reg_reg[3] );
output [7:0]\Q_reg[7] ;
output [2:0]\Q_reg[3] ;
output [0:0]DI;
output [0:0]O;
output [2:0]\Q_reg[25] ;
output \Q_reg[25]_0 ;
output \Q_reg[25]_1 ;
output [15:0]D;
output \Q_reg[9] ;
output \Q_reg[0]_0 ;
output \Q_reg[0]_1 ;
output \Q_reg[8] ;
output [1:0]FSM_selector_B;
output \Q_reg[21] ;
output \Q_reg[7]_0 ;
input [0:0]Data_A;
input FSM_exp_operation_A_S;
input [3:0]\Q_reg[26] ;
input [3:0]S;
input [0:0]\Q_reg[0]_2 ;
input \Q_reg[0]_3 ;
input FSM_barrel_shifter_B_S;
input \Q_reg[0]_4 ;
input FSM_barrel_shifter_L_R;
input \Q_reg[25]_2 ;
input [15:0]Q;
input \Q_reg[16] ;
input \Q_reg[24] ;
input \Q_reg[17] ;
input \Q_reg[23] ;
input \Q_reg[18] ;
input \Q_reg[22] ;
input \Q_reg[19] ;
input \Q_reg[21]_0 ;
input \Q_reg[20] ;
input \Q_reg[0]_5 ;
input [4:0]\Q_reg[4] ;
input [4:0]\Q_reg[4]_0 ;
input [6:0]\Q_reg[30] ;
input add_overflow_flag;
input [3:0]out;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[3] ;
wire CLK;
wire [15:0]D;
wire [0:0]DI;
wire [0:0]Data_A;
wire FSM_barrel_shifter_B_S;
wire FSM_barrel_shifter_L_R;
wire FSM_exp_operation_A_S;
wire [1:0]FSM_selector_B;
wire [0:0]\FSM_sequential_state_reg_reg[3] ;
wire [0:0]O;
wire [15:0]Q;
wire \Q[0]_i_1_n_0 ;
wire \Q[13]_i_2_n_0 ;
wire \Q[13]_i_3_n_0 ;
wire \Q[14]_i_2_n_0 ;
wire \Q[14]_i_3_n_0 ;
wire \Q[15]_i_2_n_0 ;
wire \Q[15]_i_3_n_0 ;
wire \Q[1]_i_1__0_n_0 ;
wire \Q[7]_i_3__0_n_0 ;
wire \Q[7]_i_4_n_0 ;
wire \Q[7]_i_5_n_0 ;
wire \Q_reg[0]_0 ;
wire \Q_reg[0]_1 ;
wire [0:0]\Q_reg[0]_2 ;
wire \Q_reg[0]_3 ;
wire \Q_reg[0]_4 ;
wire \Q_reg[0]_5 ;
wire \Q_reg[16] ;
wire \Q_reg[17] ;
wire \Q_reg[18] ;
wire \Q_reg[19] ;
wire \Q_reg[20] ;
wire \Q_reg[21] ;
wire \Q_reg[21]_0 ;
wire \Q_reg[22] ;
wire \Q_reg[23] ;
wire \Q_reg[24] ;
wire [2:0]\Q_reg[25] ;
wire \Q_reg[25]_0 ;
wire \Q_reg[25]_1 ;
wire \Q_reg[25]_2 ;
wire [3:0]\Q_reg[26] ;
wire [6:0]\Q_reg[30] ;
wire [2:0]\Q_reg[3] ;
wire \Q_reg[3]_i_1__0_n_0 ;
wire \Q_reg[3]_i_1__0_n_1 ;
wire \Q_reg[3]_i_1__0_n_2 ;
wire \Q_reg[3]_i_1__0_n_3 ;
wire [4:0]\Q_reg[4] ;
wire [4:0]\Q_reg[4]_0 ;
wire [7:0]\Q_reg[7] ;
wire \Q_reg[7]_0 ;
wire \Q_reg[7]_i_2_n_0 ;
wire \Q_reg[7]_i_2_n_1 ;
wire \Q_reg[7]_i_2_n_2 ;
wire \Q_reg[7]_i_2_n_3 ;
wire \Q_reg[8] ;
wire \Q_reg[9] ;
wire [3:0]S;
wire add_overflow_flag;
wire [3:0]out;
wire [3:0]\NLW_Q_reg[0]_i_2__0_CO_UNCONNECTED ;
wire [3:1]\NLW_Q_reg[0]_i_2__0_O_UNCONNECTED ;
LUT6 #(
.INIT(64'hDFFFFFDF10000010))
\Q[0]_i_1
(.I0(add_overflow_flag),
.I1(out[0]),
.I2(out[3]),
.I3(out[1]),
.I4(out[2]),
.I5(FSM_selector_B[0]),
.O(\Q[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hEF40FFFFEF400000))
\Q[0]_i_1__1
(.I0(\Q_reg[0]_0 ),
.I1(Q[15]),
.I2(\Q_reg[0]_1 ),
.I3(FSM_barrel_shifter_B_S),
.I4(FSM_barrel_shifter_L_R),
.I5(\Q_reg[16] ),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\Q[10]_i_1
(.I0(\Q[15]_i_3_n_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q[15]_i_2_n_0 ),
.O(D[10]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\Q[11]_i_1
(.I0(\Q[14]_i_3_n_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q[14]_i_2_n_0 ),
.O(D[11]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\Q[12]_i_1
(.I0(\Q[13]_i_3_n_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q[13]_i_2_n_0 ),
.O(D[12]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\Q[13]_i_1
(.I0(\Q[13]_i_2_n_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q[13]_i_3_n_0 ),
.O(D[13]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[13]_i_2
(.I0(FSM_barrel_shifter_B_S),
.I1(\Q_reg[0]_0 ),
.I2(Q[2]),
.I3(\Q_reg[0]_1 ),
.I4(Q[10]),
.O(\Q[13]_i_2_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[13]_i_3
(.I0(FSM_barrel_shifter_B_S),
.I1(\Q_reg[0]_0 ),
.I2(Q[3]),
.I3(\Q_reg[0]_1 ),
.I4(Q[11]),
.O(\Q[13]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\Q[14]_i_1
(.I0(\Q[14]_i_2_n_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q[14]_i_3_n_0 ),
.O(D[14]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[14]_i_2
(.I0(FSM_barrel_shifter_B_S),
.I1(\Q_reg[0]_0 ),
.I2(Q[1]),
.I3(\Q_reg[0]_1 ),
.I4(Q[9]),
.O(\Q[14]_i_2_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[14]_i_3
(.I0(FSM_barrel_shifter_B_S),
.I1(\Q_reg[0]_0 ),
.I2(Q[4]),
.I3(\Q_reg[0]_1 ),
.I4(Q[12]),
.O(\Q[14]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\Q[15]_i_1
(.I0(\Q[15]_i_2_n_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q[15]_i_3_n_0 ),
.O(D[15]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[15]_i_2
(.I0(FSM_barrel_shifter_B_S),
.I1(\Q_reg[0]_0 ),
.I2(Q[0]),
.I3(\Q_reg[0]_1 ),
.I4(Q[8]),
.O(\Q[15]_i_2_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[15]_i_3
(.I0(FSM_barrel_shifter_B_S),
.I1(\Q_reg[0]_0 ),
.I2(Q[5]),
.I3(\Q_reg[0]_1 ),
.I4(Q[13]),
.O(\Q[15]_i_3_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[16]_i_3
(.I0(FSM_barrel_shifter_B_S),
.I1(\Q_reg[0]_0 ),
.I2(Q[6]),
.I3(\Q_reg[0]_1 ),
.I4(Q[14]),
.O(\Q_reg[9] ));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[17]_i_3
(.I0(FSM_barrel_shifter_B_S),
.I1(\Q_reg[0]_0 ),
.I2(Q[7]),
.I3(\Q_reg[0]_1 ),
.I4(Q[15]),
.O(\Q_reg[8] ));
LUT6 #(
.INIT(64'hEF40FFFFEF400000))
\Q[1]_i_1
(.I0(\Q_reg[0]_0 ),
.I1(Q[14]),
.I2(\Q_reg[0]_1 ),
.I3(FSM_barrel_shifter_B_S),
.I4(FSM_barrel_shifter_L_R),
.I5(\Q_reg[17] ),
.O(D[1]));
LUT6 #(
.INIT(64'hEFFFFFFF20000030))
\Q[1]_i_1__0
(.I0(add_overflow_flag),
.I1(out[0]),
.I2(out[3]),
.I3(out[1]),
.I4(out[2]),
.I5(FSM_selector_B[1]),
.O(\Q[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT5 #(
.INIT(32'hB8BBB888))
\Q[22]_i_1__0
(.I0(FSM_barrel_shifter_B_S),
.I1(\Q_reg[25]_0 ),
.I2(\Q_reg[0]_5 ),
.I3(\Q_reg[25]_1 ),
.I4(\Q_reg[0]_4 ),
.O(\Q_reg[25] [0]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT4 #(
.INIT(16'hEF40))
\Q[24]_i_1
(.I0(\Q_reg[25]_0 ),
.I1(\Q_reg[0]_4 ),
.I2(\Q_reg[25]_1 ),
.I3(FSM_barrel_shifter_B_S),
.O(\Q_reg[25] [1]));
LUT4 #(
.INIT(16'hEF40))
\Q[25]_i_1__0
(.I0(\Q_reg[25]_0 ),
.I1(\Q_reg[0]_3 ),
.I2(\Q_reg[25]_1 ),
.I3(FSM_barrel_shifter_B_S),
.O(\Q_reg[25] [2]));
LUT4 #(
.INIT(16'h2320))
\Q[25]_i_2__0
(.I0(\Q_reg[4] [2]),
.I1(FSM_selector_B[1]),
.I2(FSM_selector_B[0]),
.I3(\Q_reg[4]_0 [2]),
.O(\Q_reg[25]_0 ));
LUT4 #(
.INIT(16'hDCDF))
\Q[25]_i_4__0
(.I0(\Q_reg[4] [1]),
.I1(FSM_selector_B[1]),
.I2(FSM_selector_B[0]),
.I3(\Q_reg[4]_0 [1]),
.O(\Q_reg[25]_1 ));
LUT4 #(
.INIT(16'h2320))
\Q[25]_i_5
(.I0(\Q_reg[4] [4]),
.I1(FSM_selector_B[1]),
.I2(FSM_selector_B[0]),
.I3(\Q_reg[4]_0 [4]),
.O(\Q_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT4 #(
.INIT(16'h22FC))
\Q[25]_i_5__0
(.I0(\Q_reg[4] [0]),
.I1(FSM_selector_B[1]),
.I2(\Q_reg[4]_0 [0]),
.I3(FSM_selector_B[0]),
.O(\Q_reg[21] ));
LUT4 #(
.INIT(16'hDCDF))
\Q[25]_i_6
(.I0(\Q_reg[4] [3]),
.I1(FSM_selector_B[1]),
.I2(FSM_selector_B[0]),
.I3(\Q_reg[4]_0 [3]),
.O(\Q_reg[0]_1 ));
LUT6 #(
.INIT(64'hEF40FFFFEF400000))
\Q[2]_i_1
(.I0(\Q_reg[0]_0 ),
.I1(Q[13]),
.I2(\Q_reg[0]_1 ),
.I3(FSM_barrel_shifter_B_S),
.I4(FSM_barrel_shifter_L_R),
.I5(\Q_reg[18] ),
.O(D[2]));
LUT6 #(
.INIT(64'hEF40FFFFEF400000))
\Q[3]_i_1
(.I0(\Q_reg[0]_0 ),
.I1(Q[12]),
.I2(\Q_reg[0]_1 ),
.I3(FSM_barrel_shifter_B_S),
.I4(FSM_barrel_shifter_L_R),
.I5(\Q_reg[19] ),
.O(D[3]));
LUT5 #(
.INIT(32'hAA56AAA6))
\Q[3]_i_3__0
(.I0(FSM_exp_operation_A_S),
.I1(\Q_reg[30] [2]),
.I2(FSM_selector_B[0]),
.I3(FSM_selector_B[1]),
.I4(\Q_reg[4] [3]),
.O(\Q_reg[3] [2]));
LUT5 #(
.INIT(32'hAA56AAA6))
\Q[3]_i_4
(.I0(FSM_exp_operation_A_S),
.I1(\Q_reg[30] [1]),
.I2(FSM_selector_B[0]),
.I3(FSM_selector_B[1]),
.I4(\Q_reg[4] [2]),
.O(\Q_reg[3] [1]));
LUT5 #(
.INIT(32'hAA56AAA6))
\Q[3]_i_5
(.I0(FSM_exp_operation_A_S),
.I1(\Q_reg[30] [0]),
.I2(FSM_selector_B[0]),
.I3(FSM_selector_B[1]),
.I4(\Q_reg[4] [1]),
.O(\Q_reg[3] [0]));
LUT6 #(
.INIT(64'hEF40FFFFEF400000))
\Q[4]_i_1__0
(.I0(\Q_reg[0]_0 ),
.I1(Q[11]),
.I2(\Q_reg[0]_1 ),
.I3(FSM_barrel_shifter_B_S),
.I4(FSM_barrel_shifter_L_R),
.I5(\Q_reg[20] ),
.O(D[4]));
LUT6 #(
.INIT(64'hEF40FFFFEF400000))
\Q[5]_i_1
(.I0(\Q_reg[0]_0 ),
.I1(Q[10]),
.I2(\Q_reg[0]_1 ),
.I3(FSM_barrel_shifter_B_S),
.I4(FSM_barrel_shifter_L_R),
.I5(\Q_reg[21]_0 ),
.O(D[5]));
LUT6 #(
.INIT(64'hEF40FFFFEF400000))
\Q[6]_i_1
(.I0(\Q_reg[0]_0 ),
.I1(Q[9]),
.I2(\Q_reg[0]_1 ),
.I3(FSM_barrel_shifter_B_S),
.I4(FSM_barrel_shifter_L_R),
.I5(\Q_reg[22] ),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT2 #(
.INIT(4'hE))
\Q[7]_i_11
(.I0(FSM_selector_B[1]),
.I1(FSM_selector_B[0]),
.O(\Q_reg[7]_0 ));
LUT6 #(
.INIT(64'hEF40FFFFEF400000))
\Q[7]_i_1__0
(.I0(\Q_reg[0]_0 ),
.I1(Q[8]),
.I2(\Q_reg[0]_1 ),
.I3(FSM_barrel_shifter_B_S),
.I4(FSM_barrel_shifter_L_R),
.I5(\Q_reg[23] ),
.O(D[7]));
LUT4 #(
.INIT(16'hA9AA))
\Q[7]_i_3__0
(.I0(FSM_exp_operation_A_S),
.I1(FSM_selector_B[1]),
.I2(FSM_selector_B[0]),
.I3(\Q_reg[30] [6]),
.O(\Q[7]_i_3__0_n_0 ));
LUT4 #(
.INIT(16'hA9AA))
\Q[7]_i_4
(.I0(FSM_exp_operation_A_S),
.I1(FSM_selector_B[1]),
.I2(FSM_selector_B[0]),
.I3(\Q_reg[30] [5]),
.O(\Q[7]_i_4_n_0 ));
LUT4 #(
.INIT(16'hA9AA))
\Q[7]_i_5
(.I0(FSM_exp_operation_A_S),
.I1(FSM_selector_B[1]),
.I2(FSM_selector_B[0]),
.I3(\Q_reg[30] [4]),
.O(\Q[7]_i_5_n_0 ));
LUT5 #(
.INIT(32'hAA56AAA6))
\Q[7]_i_6
(.I0(FSM_exp_operation_A_S),
.I1(\Q_reg[30] [3]),
.I2(FSM_selector_B[0]),
.I3(FSM_selector_B[1]),
.I4(\Q_reg[4] [4]),
.O(DI));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\Q[8]_i_1
(.I0(\Q_reg[8] ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q_reg[24] ),
.O(D[8]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\Q[9]_i_1
(.I0(\Q_reg[9] ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q_reg[25]_2 ),
.O(D[9]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q[0]_i_1_n_0 ),
.Q(FSM_selector_B[0]));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Q_reg[0]_i_2__0
(.CI(\Q_reg[7]_i_2_n_0 ),
.CO(\NLW_Q_reg[0]_i_2__0_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_Q_reg[0]_i_2__0_O_UNCONNECTED [3:1],O}),
.S({1'b0,1'b0,1'b0,\Q_reg[0]_2 }));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q[1]_i_1__0_n_0 ),
.Q(FSM_selector_B[1]));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Q_reg[3]_i_1__0
(.CI(1'b0),
.CO({\Q_reg[3]_i_1__0_n_0 ,\Q_reg[3]_i_1__0_n_1 ,\Q_reg[3]_i_1__0_n_2 ,\Q_reg[3]_i_1__0_n_3 }),
.CYINIT(Data_A),
.DI({\Q_reg[3] ,FSM_exp_operation_A_S}),
.O(\Q_reg[7] [3:0]),
.S(\Q_reg[26] ));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Q_reg[7]_i_2
(.CI(\Q_reg[3]_i_1__0_n_0 ),
.CO({\Q_reg[7]_i_2_n_0 ,\Q_reg[7]_i_2_n_1 ,\Q_reg[7]_i_2_n_2 ,\Q_reg[7]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({\Q[7]_i_3__0_n_0 ,\Q[7]_i_4_n_0 ,\Q[7]_i_5_n_0 ,DI}),
.O(\Q_reg[7] [7:4]),
.S(S));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized1
(sign_result,
Q,
\Q_reg[0]_0 ,
DI,
\Q_reg[0]_1 ,
\Q_reg[0]_2 ,
\Q_reg[0]_3 ,
\Q_reg[0]_4 ,
\Q_reg[0]_5 ,
D,
\Q_reg[30]_0 ,
\Q_reg[3]_0 ,
\Q_reg[7]_0 ,
\Q_reg[11]_0 ,
\Q_reg[15]_0 ,
\Q_reg[19]_0 ,
\Q_reg[23]_0 ,
\Q_reg[0]_6 ,
\FSM_sequential_state_reg_reg[3] ,
CO,
\Q_reg[31]_0 ,
\Q_reg[0]_7 ,
\Q_reg[30]_1 ,
FSM_selector_D,
\Q_reg[25]_0 ,
E,
\Data_X[31] ,
CLK,
\FSM_sequential_state_reg_reg[3]_0 );
output sign_result;
output [31:0]Q;
output [3:0]\Q_reg[0]_0 ;
output [3:0]DI;
output [3:0]\Q_reg[0]_1 ;
output [3:0]\Q_reg[0]_2 ;
output [3:0]\Q_reg[0]_3 ;
output [1:0]\Q_reg[0]_4 ;
output [3:0]\Q_reg[0]_5 ;
output [30:0]D;
output [30:0]\Q_reg[30]_0 ;
output [2:0]\Q_reg[3]_0 ;
output [3:0]\Q_reg[7]_0 ;
output [3:0]\Q_reg[11]_0 ;
output [3:0]\Q_reg[15]_0 ;
output [3:0]\Q_reg[19]_0 ;
output [3:0]\Q_reg[23]_0 ;
output [1:0]\Q_reg[0]_6 ;
output \FSM_sequential_state_reg_reg[3] ;
input [0:0]CO;
input [31:0]\Q_reg[31]_0 ;
input \Q_reg[0]_7 ;
input [0:0]\Q_reg[30]_1 ;
input FSM_selector_D;
input [24:0]\Q_reg[25]_0 ;
input [0:0]E;
input [31:0]\Data_X[31] ;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[3]_0 ;
wire CLK;
wire [0:0]CO;
wire [30:0]D;
wire [3:0]DI;
wire [31:0]\Data_X[31] ;
wire [0:0]E;
wire FSM_selector_D;
wire \FSM_sequential_state_reg_reg[3] ;
wire [0:0]\FSM_sequential_state_reg_reg[3]_0 ;
wire [31:0]Q;
wire [3:0]\Q_reg[0]_0 ;
wire [3:0]\Q_reg[0]_1 ;
wire [3:0]\Q_reg[0]_2 ;
wire [3:0]\Q_reg[0]_3 ;
wire [1:0]\Q_reg[0]_4 ;
wire [3:0]\Q_reg[0]_5 ;
wire [1:0]\Q_reg[0]_6 ;
wire \Q_reg[0]_7 ;
wire [3:0]\Q_reg[11]_0 ;
wire [3:0]\Q_reg[15]_0 ;
wire [3:0]\Q_reg[19]_0 ;
wire [3:0]\Q_reg[23]_0 ;
wire [24:0]\Q_reg[25]_0 ;
wire [30:0]\Q_reg[30]_0 ;
wire [0:0]\Q_reg[30]_1 ;
wire [31:0]\Q_reg[31]_0 ;
wire [2:0]\Q_reg[3]_0 ;
wire [3:0]\Q_reg[7]_0 ;
wire sign_result;
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'h69))
\FSM_sequential_state_reg[3]_i_4
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.O(\FSM_sequential_state_reg_reg[3] ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT5 #(
.INIT(32'hCCCC0DD0))
\Q[0]_i_1__3
(.I0(CO),
.I1(Q[31]),
.I2(\Q_reg[31]_0 [31]),
.I3(\Q_reg[0]_7 ),
.I4(\Q_reg[30]_1 ),
.O(sign_result));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\Q[0]_i_1__6
(.I0(Q[0]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [0]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\Q[0]_i_1__7
(.I0(\Q_reg[31]_0 [0]),
.I1(\Q_reg[30]_1 ),
.I2(Q[0]),
.O(\Q_reg[30]_0 [0]));
LUT5 #(
.INIT(32'h00690096))
\Q[0]_i_3__2
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [24]),
.O(\Q_reg[0]_6 [1]));
LUT5 #(
.INIT(32'h00690096))
\Q[0]_i_4__1
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [23]),
.O(\Q_reg[0]_6 [0]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\Q[10]_i_1__2
(.I0(Q[10]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [10]),
.O(D[10]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\Q[10]_i_1__3
(.I0(\Q_reg[31]_0 [10]),
.I1(\Q_reg[30]_1 ),
.I2(Q[10]),
.O(\Q_reg[30]_0 [10]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\Q[11]_i_1__2
(.I0(Q[11]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [11]),
.O(D[11]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\Q[11]_i_1__3
(.I0(\Q_reg[31]_0 [11]),
.I1(\Q_reg[30]_1 ),
.I2(Q[11]),
.O(\Q_reg[30]_0 [11]));
LUT5 #(
.INIT(32'h00690096))
\Q[11]_i_2__0
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [10]),
.O(\Q_reg[11]_0 [3]));
LUT5 #(
.INIT(32'h00690096))
\Q[11]_i_3__0
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [9]),
.O(\Q_reg[11]_0 [2]));
LUT5 #(
.INIT(32'h00690096))
\Q[11]_i_4__0
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [8]),
.O(\Q_reg[11]_0 [1]));
LUT5 #(
.INIT(32'h00690096))
\Q[11]_i_5
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [7]),
.O(\Q_reg[11]_0 [0]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\Q[12]_i_1__2
(.I0(Q[12]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [12]),
.O(D[12]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\Q[12]_i_1__3
(.I0(\Q_reg[31]_0 [12]),
.I1(\Q_reg[30]_1 ),
.I2(Q[12]),
.O(\Q_reg[30]_0 [12]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\Q[13]_i_1__2
(.I0(Q[13]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [13]),
.O(D[13]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\Q[13]_i_1__3
(.I0(\Q_reg[31]_0 [13]),
.I1(\Q_reg[30]_1 ),
.I2(Q[13]),
.O(\Q_reg[30]_0 [13]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\Q[14]_i_1__2
(.I0(Q[14]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [14]),
.O(D[14]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\Q[14]_i_1__3
(.I0(\Q_reg[31]_0 [14]),
.I1(\Q_reg[30]_1 ),
.I2(Q[14]),
.O(\Q_reg[30]_0 [14]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\Q[15]_i_1__2
(.I0(Q[15]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [15]),
.O(D[15]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\Q[15]_i_1__3
(.I0(\Q_reg[31]_0 [15]),
.I1(\Q_reg[30]_1 ),
.I2(Q[15]),
.O(\Q_reg[30]_0 [15]));
LUT5 #(
.INIT(32'h00690096))
\Q[15]_i_2__1
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [14]),
.O(\Q_reg[15]_0 [3]));
LUT5 #(
.INIT(32'h00690096))
\Q[15]_i_3__1
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [13]),
.O(\Q_reg[15]_0 [2]));
LUT5 #(
.INIT(32'h00690096))
\Q[15]_i_4
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [12]),
.O(\Q_reg[15]_0 [1]));
LUT5 #(
.INIT(32'h00690096))
\Q[15]_i_5
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [11]),
.O(\Q_reg[15]_0 [0]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\Q[16]_i_1__2
(.I0(Q[16]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [16]),
.O(D[16]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\Q[16]_i_1__3
(.I0(\Q_reg[31]_0 [16]),
.I1(\Q_reg[30]_1 ),
.I2(Q[16]),
.O(\Q_reg[30]_0 [16]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\Q[17]_i_1__2
(.I0(Q[17]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [17]),
.O(D[17]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\Q[17]_i_1__3
(.I0(\Q_reg[31]_0 [17]),
.I1(\Q_reg[30]_1 ),
.I2(Q[17]),
.O(\Q_reg[30]_0 [17]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\Q[18]_i_1__2
(.I0(Q[18]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [18]),
.O(D[18]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\Q[18]_i_1__3
(.I0(\Q_reg[31]_0 [18]),
.I1(\Q_reg[30]_1 ),
.I2(Q[18]),
.O(\Q_reg[30]_0 [18]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\Q[19]_i_1__2
(.I0(Q[19]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [19]),
.O(D[19]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\Q[19]_i_1__3
(.I0(\Q_reg[31]_0 [19]),
.I1(\Q_reg[30]_1 ),
.I2(Q[19]),
.O(\Q_reg[30]_0 [19]));
LUT5 #(
.INIT(32'h00690096))
\Q[19]_i_2__1
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [18]),
.O(\Q_reg[19]_0 [3]));
LUT5 #(
.INIT(32'h00690096))
\Q[19]_i_3__0
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [17]),
.O(\Q_reg[19]_0 [2]));
LUT5 #(
.INIT(32'h00690096))
\Q[19]_i_4
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [16]),
.O(\Q_reg[19]_0 [1]));
LUT5 #(
.INIT(32'h00690096))
\Q[19]_i_5
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [15]),
.O(\Q_reg[19]_0 [0]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\Q[1]_i_1__3
(.I0(Q[1]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [1]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\Q[1]_i_1__4
(.I0(\Q_reg[31]_0 [1]),
.I1(\Q_reg[30]_1 ),
.I2(Q[1]),
.O(\Q_reg[30]_0 [1]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\Q[20]_i_1__2
(.I0(Q[20]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [20]),
.O(D[20]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\Q[20]_i_1__3
(.I0(\Q_reg[31]_0 [20]),
.I1(\Q_reg[30]_1 ),
.I2(Q[20]),
.O(\Q_reg[30]_0 [20]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\Q[21]_i_1__2
(.I0(Q[21]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [21]),
.O(D[21]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\Q[21]_i_1__3
(.I0(\Q_reg[31]_0 [21]),
.I1(\Q_reg[30]_1 ),
.I2(Q[21]),
.O(\Q_reg[30]_0 [21]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\Q[22]_i_1__2
(.I0(Q[22]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [22]),
.O(D[22]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\Q[22]_i_1__3
(.I0(\Q_reg[31]_0 [22]),
.I1(\Q_reg[30]_1 ),
.I2(Q[22]),
.O(\Q_reg[30]_0 [22]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\Q[23]_i_1__2
(.I0(Q[23]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [23]),
.O(D[23]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\Q[23]_i_1__3
(.I0(\Q_reg[31]_0 [23]),
.I1(\Q_reg[30]_1 ),
.I2(Q[23]),
.O(\Q_reg[30]_0 [23]));
LUT5 #(
.INIT(32'h00690096))
\Q[23]_i_2__1
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [22]),
.O(\Q_reg[23]_0 [3]));
LUT5 #(
.INIT(32'h00690096))
\Q[23]_i_3__0
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [21]),
.O(\Q_reg[23]_0 [2]));
LUT5 #(
.INIT(32'h00690096))
\Q[23]_i_4
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [20]),
.O(\Q_reg[23]_0 [1]));
LUT5 #(
.INIT(32'h00690096))
\Q[23]_i_5
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [19]),
.O(\Q_reg[23]_0 [0]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\Q[24]_i_1__2
(.I0(Q[24]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [24]),
.O(D[24]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\Q[24]_i_1__3
(.I0(\Q_reg[31]_0 [24]),
.I1(\Q_reg[30]_1 ),
.I2(Q[24]),
.O(\Q_reg[30]_0 [24]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\Q[25]_i_1__2
(.I0(Q[25]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [25]),
.O(D[25]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\Q[25]_i_1__3
(.I0(\Q_reg[31]_0 [25]),
.I1(\Q_reg[30]_1 ),
.I2(Q[25]),
.O(\Q_reg[30]_0 [25]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\Q[26]_i_1__0
(.I0(Q[26]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [26]),
.O(D[26]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\Q[26]_i_1__1
(.I0(\Q_reg[31]_0 [26]),
.I1(\Q_reg[30]_1 ),
.I2(Q[26]),
.O(\Q_reg[30]_0 [26]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\Q[27]_i_1__0
(.I0(Q[27]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [27]),
.O(D[27]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\Q[27]_i_1__1
(.I0(\Q_reg[31]_0 [27]),
.I1(\Q_reg[30]_1 ),
.I2(Q[27]),
.O(\Q_reg[30]_0 [27]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\Q[28]_i_1__0
(.I0(Q[28]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [28]),
.O(D[28]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\Q[28]_i_1__1
(.I0(\Q_reg[31]_0 [28]),
.I1(\Q_reg[30]_1 ),
.I2(Q[28]),
.O(\Q_reg[30]_0 [28]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\Q[29]_i_1__0
(.I0(Q[29]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [29]),
.O(D[29]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\Q[29]_i_1__1
(.I0(\Q_reg[31]_0 [29]),
.I1(\Q_reg[30]_1 ),
.I2(Q[29]),
.O(\Q_reg[30]_0 [29]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\Q[2]_i_1__3
(.I0(Q[2]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [2]),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\Q[2]_i_1__4
(.I0(\Q_reg[31]_0 [2]),
.I1(\Q_reg[30]_1 ),
.I2(Q[2]),
.O(\Q_reg[30]_0 [2]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\Q[30]_i_1__1
(.I0(\Q_reg[31]_0 [30]),
.I1(\Q_reg[30]_1 ),
.I2(Q[30]),
.O(\Q_reg[30]_0 [30]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\Q[30]_i_2
(.I0(Q[30]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [30]),
.O(D[30]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\Q[3]_i_1__3
(.I0(Q[3]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [3]),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\Q[3]_i_1__4
(.I0(\Q_reg[31]_0 [3]),
.I1(\Q_reg[30]_1 ),
.I2(Q[3]),
.O(\Q_reg[30]_0 [3]));
LUT5 #(
.INIT(32'h00690096))
\Q[3]_i_3__1
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [2]),
.O(\Q_reg[3]_0 [2]));
LUT5 #(
.INIT(32'hFFFF6996))
\Q[3]_i_4__0
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(\Q_reg[25]_0 [1]),
.I4(FSM_selector_D),
.O(\Q_reg[3]_0 [1]));
LUT5 #(
.INIT(32'h00690096))
\Q[3]_i_5__0
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [0]),
.O(\Q_reg[3]_0 [0]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\Q[4]_i_1__3
(.I0(Q[4]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [4]),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\Q[4]_i_1__4
(.I0(\Q_reg[31]_0 [4]),
.I1(\Q_reg[30]_1 ),
.I2(Q[4]),
.O(\Q_reg[30]_0 [4]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\Q[5]_i_1__2
(.I0(Q[5]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [5]),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\Q[5]_i_1__3
(.I0(\Q_reg[31]_0 [5]),
.I1(\Q_reg[30]_1 ),
.I2(Q[5]),
.O(\Q_reg[30]_0 [5]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\Q[6]_i_1__2
(.I0(Q[6]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [6]),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\Q[6]_i_1__3
(.I0(\Q_reg[31]_0 [6]),
.I1(\Q_reg[30]_1 ),
.I2(Q[6]),
.O(\Q_reg[30]_0 [6]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\Q[7]_i_1__3
(.I0(Q[7]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [7]),
.O(D[7]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\Q[7]_i_1__4
(.I0(\Q_reg[31]_0 [7]),
.I1(\Q_reg[30]_1 ),
.I2(Q[7]),
.O(\Q_reg[30]_0 [7]));
LUT5 #(
.INIT(32'h00690096))
\Q[7]_i_2__1
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [6]),
.O(\Q_reg[7]_0 [3]));
LUT5 #(
.INIT(32'h00690096))
\Q[7]_i_3__1
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [5]),
.O(\Q_reg[7]_0 [2]));
LUT5 #(
.INIT(32'h00690096))
\Q[7]_i_4__0
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [4]),
.O(\Q_reg[7]_0 [1]));
LUT5 #(
.INIT(32'h00690096))
\Q[7]_i_5__0
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [3]),
.O(\Q_reg[7]_0 [0]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\Q[8]_i_1__2
(.I0(Q[8]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [8]),
.O(D[8]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\Q[8]_i_1__3
(.I0(\Q_reg[31]_0 [8]),
.I1(\Q_reg[30]_1 ),
.I2(Q[8]),
.O(\Q_reg[30]_0 [8]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\Q[9]_i_1__2
(.I0(Q[9]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [9]),
.O(D[9]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\Q[9]_i_1__3
(.I0(\Q_reg[31]_0 [9]),
.I1(\Q_reg[30]_1 ),
.I2(Q[9]),
.O(\Q_reg[30]_0 [9]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [9]),
.Q(Q[9]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__0_i_1
(.I0(Q[22]),
.I1(\Q_reg[31]_0 [22]),
.I2(Q[23]),
.I3(\Q_reg[31]_0 [23]),
.I4(\Q_reg[31]_0 [21]),
.I5(Q[21]),
.O(\Q_reg[0]_2 [3]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__0_i_2
(.I0(Q[18]),
.I1(\Q_reg[31]_0 [18]),
.I2(Q[19]),
.I3(\Q_reg[31]_0 [19]),
.I4(\Q_reg[31]_0 [20]),
.I5(Q[20]),
.O(\Q_reg[0]_2 [2]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__0_i_3
(.I0(Q[16]),
.I1(\Q_reg[31]_0 [16]),
.I2(Q[17]),
.I3(\Q_reg[31]_0 [17]),
.I4(\Q_reg[31]_0 [15]),
.I5(Q[15]),
.O(\Q_reg[0]_2 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__0_i_4
(.I0(Q[12]),
.I1(\Q_reg[31]_0 [12]),
.I2(Q[13]),
.I3(\Q_reg[31]_0 [13]),
.I4(\Q_reg[31]_0 [14]),
.I5(Q[14]),
.O(\Q_reg[0]_2 [0]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__1_i_2
(.I0(Q[28]),
.I1(\Q_reg[31]_0 [28]),
.I2(Q[29]),
.I3(\Q_reg[31]_0 [29]),
.I4(\Q_reg[31]_0 [27]),
.I5(Q[27]),
.O(\Q_reg[0]_4 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__1_i_3
(.I0(Q[24]),
.I1(\Q_reg[31]_0 [24]),
.I2(Q[25]),
.I3(\Q_reg[31]_0 [25]),
.I4(\Q_reg[31]_0 [26]),
.I5(Q[26]),
.O(\Q_reg[0]_4 [0]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry_i_1
(.I0(Q[10]),
.I1(\Q_reg[31]_0 [10]),
.I2(Q[11]),
.I3(\Q_reg[31]_0 [11]),
.I4(\Q_reg[31]_0 [9]),
.I5(Q[9]),
.O(\Q_reg[0]_0 [3]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry_i_2
(.I0(Q[6]),
.I1(\Q_reg[31]_0 [6]),
.I2(Q[7]),
.I3(\Q_reg[31]_0 [7]),
.I4(\Q_reg[31]_0 [8]),
.I5(Q[8]),
.O(\Q_reg[0]_0 [2]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry_i_3
(.I0(Q[4]),
.I1(\Q_reg[31]_0 [4]),
.I2(Q[5]),
.I3(\Q_reg[31]_0 [5]),
.I4(\Q_reg[31]_0 [3]),
.I5(Q[3]),
.O(\Q_reg[0]_0 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry_i_4
(.I0(Q[0]),
.I1(\Q_reg[31]_0 [0]),
.I2(Q[1]),
.I3(\Q_reg[31]_0 [1]),
.I4(\Q_reg[31]_0 [2]),
.I5(Q[2]),
.O(\Q_reg[0]_0 [0]));
LUT4 #(
.INIT(16'h22B2))
gtXY_o_carry__0_i_1
(.I0(Q[15]),
.I1(\Q_reg[31]_0 [15]),
.I2(Q[14]),
.I3(\Q_reg[31]_0 [14]),
.O(\Q_reg[0]_1 [3]));
LUT4 #(
.INIT(16'h22B2))
gtXY_o_carry__0_i_2
(.I0(Q[13]),
.I1(\Q_reg[31]_0 [13]),
.I2(Q[12]),
.I3(\Q_reg[31]_0 [12]),
.O(\Q_reg[0]_1 [2]));
LUT4 #(
.INIT(16'h22B2))
gtXY_o_carry__0_i_3
(.I0(Q[11]),
.I1(\Q_reg[31]_0 [11]),
.I2(Q[10]),
.I3(\Q_reg[31]_0 [10]),
.O(\Q_reg[0]_1 [1]));
LUT4 #(
.INIT(16'h22B2))
gtXY_o_carry__0_i_4
(.I0(Q[9]),
.I1(\Q_reg[31]_0 [9]),
.I2(Q[8]),
.I3(\Q_reg[31]_0 [8]),
.O(\Q_reg[0]_1 [0]));
LUT4 #(
.INIT(16'h22B2))
gtXY_o_carry__1_i_1
(.I0(Q[23]),
.I1(\Q_reg[31]_0 [23]),
.I2(Q[22]),
.I3(\Q_reg[31]_0 [22]),
.O(\Q_reg[0]_3 [3]));
LUT4 #(
.INIT(16'h22B2))
gtXY_o_carry__1_i_2
(.I0(Q[21]),
.I1(\Q_reg[31]_0 [21]),
.I2(Q[20]),
.I3(\Q_reg[31]_0 [20]),
.O(\Q_reg[0]_3 [2]));
LUT4 #(
.INIT(16'h22B2))
gtXY_o_carry__1_i_3
(.I0(Q[19]),
.I1(\Q_reg[31]_0 [19]),
.I2(Q[18]),
.I3(\Q_reg[31]_0 [18]),
.O(\Q_reg[0]_3 [1]));
LUT4 #(
.INIT(16'h22B2))
gtXY_o_carry__1_i_4
(.I0(Q[17]),
.I1(\Q_reg[31]_0 [17]),
.I2(Q[16]),
.I3(\Q_reg[31]_0 [16]),
.O(\Q_reg[0]_3 [0]));
LUT2 #(
.INIT(4'h2))
gtXY_o_carry__2_i_1
(.I0(Q[30]),
.I1(\Q_reg[31]_0 [30]),
.O(\Q_reg[0]_5 [3]));
LUT4 #(
.INIT(16'h22B2))
gtXY_o_carry__2_i_2
(.I0(Q[29]),
.I1(\Q_reg[31]_0 [29]),
.I2(Q[28]),
.I3(\Q_reg[31]_0 [28]),
.O(\Q_reg[0]_5 [2]));
LUT4 #(
.INIT(16'h22B2))
gtXY_o_carry__2_i_3
(.I0(Q[27]),
.I1(\Q_reg[31]_0 [27]),
.I2(Q[26]),
.I3(\Q_reg[31]_0 [26]),
.O(\Q_reg[0]_5 [1]));
LUT4 #(
.INIT(16'h22B2))
gtXY_o_carry__2_i_4
(.I0(Q[25]),
.I1(\Q_reg[31]_0 [25]),
.I2(Q[24]),
.I3(\Q_reg[31]_0 [24]),
.O(\Q_reg[0]_5 [0]));
LUT4 #(
.INIT(16'h22B2))
gtXY_o_carry_i_1
(.I0(Q[7]),
.I1(\Q_reg[31]_0 [7]),
.I2(Q[6]),
.I3(\Q_reg[31]_0 [6]),
.O(DI[3]));
LUT4 #(
.INIT(16'h22B2))
gtXY_o_carry_i_2
(.I0(Q[5]),
.I1(\Q_reg[31]_0 [5]),
.I2(Q[4]),
.I3(\Q_reg[31]_0 [4]),
.O(DI[2]));
LUT4 #(
.INIT(16'h22B2))
gtXY_o_carry_i_3
(.I0(Q[3]),
.I1(\Q_reg[31]_0 [3]),
.I2(Q[2]),
.I3(\Q_reg[31]_0 [2]),
.O(DI[1]));
LUT4 #(
.INIT(16'h22B2))
gtXY_o_carry_i_4
(.I0(Q[1]),
.I1(\Q_reg[31]_0 [1]),
.I2(Q[0]),
.I3(\Q_reg[31]_0 [0]),
.O(DI[0]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized10
(Q,
E,
D,
CLK,
AR);
output [31:0]Q;
input [0:0]E;
input [31:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [31:0]Q;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized2
(\Q_reg[23]_0 ,
O,
Q,
\Q_reg[0]_0 ,
\Q_reg[0]_1 ,
\Q_reg[0]_2 ,
\Q_reg[0]_3 ,
\Q_reg[0]_4 ,
\Q_reg[0]_5 ,
\Q_reg[31]_0 ,
S,
\Q_reg[31]_1 ,
\Q_reg[31]_2 ,
\Q_reg[31]_3 ,
\Q_reg[31]_4 ,
\Q_reg[31]_5 ,
\Q_reg[31]_6 ,
\Q_reg[31]_7 ,
\Q_reg[31]_8 ,
\Q_reg[31]_9 ,
\Q_reg[31]_10 ,
\Q_reg[31]_11 ,
\Q_reg[31]_12 ,
FSM_selector_D,
\Q_reg[0]_6 ,
\Q_reg[31]_13 ,
E,
D,
CLK,
\FSM_sequential_state_reg_reg[3] );
output [23:0]\Q_reg[23]_0 ;
output [2:0]O;
output [31:0]Q;
output [3:0]\Q_reg[0]_0 ;
output [3:0]\Q_reg[0]_1 ;
output [3:0]\Q_reg[0]_2 ;
output [3:0]\Q_reg[0]_3 ;
output [0:0]\Q_reg[0]_4 ;
input \Q_reg[0]_5 ;
input [2:0]\Q_reg[31]_0 ;
input [3:0]S;
input [3:0]\Q_reg[31]_1 ;
input [3:0]\Q_reg[31]_2 ;
input [3:0]\Q_reg[31]_3 ;
input [3:0]\Q_reg[31]_4 ;
input [3:0]\Q_reg[31]_5 ;
input [3:0]\Q_reg[31]_6 ;
input [3:0]\Q_reg[31]_7 ;
input [3:0]\Q_reg[31]_8 ;
input [3:0]\Q_reg[31]_9 ;
input [3:0]\Q_reg[31]_10 ;
input [1:0]\Q_reg[31]_11 ;
input [1:0]\Q_reg[31]_12 ;
input FSM_selector_D;
input \Q_reg[0]_6 ;
input [31:0]\Q_reg[31]_13 ;
input [0:0]E;
input [31:0]D;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[3] ;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire FSM_selector_D;
wire [0:0]\FSM_sequential_state_reg_reg[3] ;
wire [2:0]O;
wire [31:0]Q;
wire \Q[3]_i_6__0_n_0 ;
wire [3:0]\Q_reg[0]_0 ;
wire [3:0]\Q_reg[0]_1 ;
wire [3:0]\Q_reg[0]_2 ;
wire [3:0]\Q_reg[0]_3 ;
wire [0:0]\Q_reg[0]_4 ;
wire \Q_reg[0]_5 ;
wire \Q_reg[0]_6 ;
wire \Q_reg[0]_i_2_n_2 ;
wire \Q_reg[0]_i_2_n_3 ;
wire \Q_reg[11]_i_1_n_0 ;
wire \Q_reg[11]_i_1_n_1 ;
wire \Q_reg[11]_i_1_n_2 ;
wire \Q_reg[11]_i_1_n_3 ;
wire \Q_reg[15]_i_1_n_0 ;
wire \Q_reg[15]_i_1_n_1 ;
wire \Q_reg[15]_i_1_n_2 ;
wire \Q_reg[15]_i_1_n_3 ;
wire \Q_reg[19]_i_1_n_0 ;
wire \Q_reg[19]_i_1_n_1 ;
wire \Q_reg[19]_i_1_n_2 ;
wire \Q_reg[19]_i_1_n_3 ;
wire [23:0]\Q_reg[23]_0 ;
wire \Q_reg[23]_i_1_n_0 ;
wire \Q_reg[23]_i_1_n_1 ;
wire \Q_reg[23]_i_1_n_2 ;
wire \Q_reg[23]_i_1_n_3 ;
wire [2:0]\Q_reg[31]_0 ;
wire [3:0]\Q_reg[31]_1 ;
wire [3:0]\Q_reg[31]_10 ;
wire [1:0]\Q_reg[31]_11 ;
wire [1:0]\Q_reg[31]_12 ;
wire [31:0]\Q_reg[31]_13 ;
wire [3:0]\Q_reg[31]_2 ;
wire [3:0]\Q_reg[31]_3 ;
wire [3:0]\Q_reg[31]_4 ;
wire [3:0]\Q_reg[31]_5 ;
wire [3:0]\Q_reg[31]_6 ;
wire [3:0]\Q_reg[31]_7 ;
wire [3:0]\Q_reg[31]_8 ;
wire [3:0]\Q_reg[31]_9 ;
wire \Q_reg[3]_i_1_n_0 ;
wire \Q_reg[3]_i_1_n_1 ;
wire \Q_reg[3]_i_1_n_2 ;
wire \Q_reg[3]_i_1_n_3 ;
wire \Q_reg[7]_i_1_n_0 ;
wire \Q_reg[7]_i_1_n_1 ;
wire \Q_reg[7]_i_1_n_2 ;
wire \Q_reg[7]_i_1_n_3 ;
wire [3:0]S;
wire S_A_S_op;
wire [3:2]\NLW_Q_reg[0]_i_2_CO_UNCONNECTED ;
wire [3:3]\NLW_Q_reg[0]_i_2_O_UNCONNECTED ;
LUT4 #(
.INIT(16'h4114))
\Q[0]_i_5
(.I0(FSM_selector_D),
.I1(Q[31]),
.I2(\Q_reg[0]_6 ),
.I3(\Q_reg[31]_13 [31]),
.O(S_A_S_op));
LUT4 #(
.INIT(16'h4114))
\Q[3]_i_6__0
(.I0(FSM_selector_D),
.I1(Q[31]),
.I2(\Q_reg[0]_6 ),
.I3(\Q_reg[31]_13 [31]),
.O(\Q[3]_i_6__0_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[0]),
.Q(Q[0]));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Q_reg[0]_i_2
(.CI(\Q_reg[23]_i_1_n_0 ),
.CO({\NLW_Q_reg[0]_i_2_CO_UNCONNECTED [3:2],\Q_reg[0]_i_2_n_2 ,\Q_reg[0]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,\Q_reg[31]_11 }),
.O({\NLW_Q_reg[0]_i_2_O_UNCONNECTED [3],O}),
.S({1'b0,S_A_S_op,\Q_reg[31]_12 }));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[11]),
.Q(Q[11]));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Q_reg[11]_i_1
(.CI(\Q_reg[7]_i_1_n_0 ),
.CO({\Q_reg[11]_i_1_n_0 ,\Q_reg[11]_i_1_n_1 ,\Q_reg[11]_i_1_n_2 ,\Q_reg[11]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(\Q_reg[31]_3 ),
.O(\Q_reg[23]_0 [11:8]),
.S(\Q_reg[31]_4 ));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[15]),
.Q(Q[15]));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Q_reg[15]_i_1
(.CI(\Q_reg[11]_i_1_n_0 ),
.CO({\Q_reg[15]_i_1_n_0 ,\Q_reg[15]_i_1_n_1 ,\Q_reg[15]_i_1_n_2 ,\Q_reg[15]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(\Q_reg[31]_5 ),
.O(\Q_reg[23]_0 [15:12]),
.S(\Q_reg[31]_6 ));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[19]),
.Q(Q[19]));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Q_reg[19]_i_1
(.CI(\Q_reg[15]_i_1_n_0 ),
.CO({\Q_reg[19]_i_1_n_0 ,\Q_reg[19]_i_1_n_1 ,\Q_reg[19]_i_1_n_2 ,\Q_reg[19]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(\Q_reg[31]_7 ),
.O(\Q_reg[23]_0 [19:16]),
.S(\Q_reg[31]_8 ));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[23]),
.Q(Q[23]));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Q_reg[23]_i_1
(.CI(\Q_reg[19]_i_1_n_0 ),
.CO({\Q_reg[23]_i_1_n_0 ,\Q_reg[23]_i_1_n_1 ,\Q_reg[23]_i_1_n_2 ,\Q_reg[23]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(\Q_reg[31]_9 ),
.O(\Q_reg[23]_0 [23:20]),
.S(\Q_reg[31]_10 ));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[3]),
.Q(Q[3]));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Q_reg[3]_i_1
(.CI(1'b0),
.CO({\Q_reg[3]_i_1_n_0 ,\Q_reg[3]_i_1_n_1 ,\Q_reg[3]_i_1_n_2 ,\Q_reg[3]_i_1_n_3 }),
.CYINIT(\Q_reg[0]_5 ),
.DI({\Q_reg[31]_0 ,\Q[3]_i_6__0_n_0 }),
.O(\Q_reg[23]_0 [3:0]),
.S(S));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[7]),
.Q(Q[7]));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Q_reg[7]_i_1
(.CI(\Q_reg[3]_i_1_n_0 ),
.CO({\Q_reg[7]_i_1_n_0 ,\Q_reg[7]_i_1_n_1 ,\Q_reg[7]_i_1_n_2 ,\Q_reg[7]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(\Q_reg[31]_1 ),
.O(\Q_reg[23]_0 [7:4]),
.S(\Q_reg[31]_2 ));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[9]),
.Q(Q[9]));
LUT2 #(
.INIT(4'h9))
eqXY_o_carry__1_i_1
(.I0(Q[30]),
.I1(\Q_reg[31]_13 [30]),
.O(\Q_reg[0]_4 ));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__0_i_5
(.I0(Q[15]),
.I1(\Q_reg[31]_13 [15]),
.I2(Q[14]),
.I3(\Q_reg[31]_13 [14]),
.O(\Q_reg[0]_1 [3]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__0_i_6
(.I0(Q[13]),
.I1(\Q_reg[31]_13 [13]),
.I2(Q[12]),
.I3(\Q_reg[31]_13 [12]),
.O(\Q_reg[0]_1 [2]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__0_i_7
(.I0(Q[11]),
.I1(\Q_reg[31]_13 [11]),
.I2(Q[10]),
.I3(\Q_reg[31]_13 [10]),
.O(\Q_reg[0]_1 [1]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__0_i_8
(.I0(Q[9]),
.I1(\Q_reg[31]_13 [9]),
.I2(Q[8]),
.I3(\Q_reg[31]_13 [8]),
.O(\Q_reg[0]_1 [0]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__1_i_5
(.I0(Q[23]),
.I1(\Q_reg[31]_13 [23]),
.I2(Q[22]),
.I3(\Q_reg[31]_13 [22]),
.O(\Q_reg[0]_2 [3]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__1_i_6
(.I0(Q[21]),
.I1(\Q_reg[31]_13 [21]),
.I2(Q[20]),
.I3(\Q_reg[31]_13 [20]),
.O(\Q_reg[0]_2 [2]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__1_i_7
(.I0(Q[19]),
.I1(\Q_reg[31]_13 [19]),
.I2(Q[18]),
.I3(\Q_reg[31]_13 [18]),
.O(\Q_reg[0]_2 [1]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__1_i_8
(.I0(Q[17]),
.I1(\Q_reg[31]_13 [17]),
.I2(Q[16]),
.I3(\Q_reg[31]_13 [16]),
.O(\Q_reg[0]_2 [0]));
LUT2 #(
.INIT(4'h9))
gtXY_o_carry__2_i_5
(.I0(Q[30]),
.I1(\Q_reg[31]_13 [30]),
.O(\Q_reg[0]_3 [3]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__2_i_6
(.I0(Q[29]),
.I1(\Q_reg[31]_13 [29]),
.I2(Q[28]),
.I3(\Q_reg[31]_13 [28]),
.O(\Q_reg[0]_3 [2]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__2_i_7
(.I0(Q[27]),
.I1(\Q_reg[31]_13 [27]),
.I2(Q[26]),
.I3(\Q_reg[31]_13 [26]),
.O(\Q_reg[0]_3 [1]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__2_i_8
(.I0(Q[25]),
.I1(\Q_reg[31]_13 [25]),
.I2(Q[24]),
.I3(\Q_reg[31]_13 [24]),
.O(\Q_reg[0]_3 [0]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry_i_5
(.I0(Q[7]),
.I1(\Q_reg[31]_13 [7]),
.I2(Q[6]),
.I3(\Q_reg[31]_13 [6]),
.O(\Q_reg[0]_0 [3]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry_i_6
(.I0(Q[5]),
.I1(\Q_reg[31]_13 [5]),
.I2(Q[4]),
.I3(\Q_reg[31]_13 [4]),
.O(\Q_reg[0]_0 [2]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry_i_7
(.I0(Q[3]),
.I1(\Q_reg[31]_13 [3]),
.I2(Q[2]),
.I3(\Q_reg[31]_13 [2]),
.O(\Q_reg[0]_0 [1]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry_i_8
(.I0(Q[1]),
.I1(\Q_reg[31]_13 [1]),
.I2(Q[0]),
.I3(\Q_reg[31]_13 [0]),
.O(\Q_reg[0]_0 [0]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized3
(\Q_reg[7]_0 ,
\FSM_sequential_state_reg_reg[3] ,
D,
CLK,
\FSM_sequential_state_reg_reg[3]_0 );
output [30:0]\Q_reg[7]_0 ;
input [0:0]\FSM_sequential_state_reg_reg[3] ;
input [30:0]D;
input CLK;
input [1:0]\FSM_sequential_state_reg_reg[3]_0 ;
wire CLK;
wire [30:0]D;
wire [0:0]\FSM_sequential_state_reg_reg[3] ;
wire [1:0]\FSM_sequential_state_reg_reg[3]_0 ;
wire [30:0]\Q_reg[7]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [0]),
.D(D[0]),
.Q(\Q_reg[7]_0 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[10]),
.Q(\Q_reg[7]_0 [10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[11]),
.Q(\Q_reg[7]_0 [11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[12]),
.Q(\Q_reg[7]_0 [12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[13]),
.Q(\Q_reg[7]_0 [13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[14]),
.Q(\Q_reg[7]_0 [14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[15]),
.Q(\Q_reg[7]_0 [15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[16]),
.Q(\Q_reg[7]_0 [16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[17]),
.Q(\Q_reg[7]_0 [17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[18]),
.Q(\Q_reg[7]_0 [18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[19]),
.Q(\Q_reg[7]_0 [19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [0]),
.D(D[1]),
.Q(\Q_reg[7]_0 [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[20]),
.Q(\Q_reg[7]_0 [20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[21]),
.Q(\Q_reg[7]_0 [21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[22]),
.Q(\Q_reg[7]_0 [22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[23]),
.Q(\Q_reg[7]_0 [23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[24]),
.Q(\Q_reg[7]_0 [24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[25]),
.Q(\Q_reg[7]_0 [25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[26]),
.Q(\Q_reg[7]_0 [26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[27]),
.Q(\Q_reg[7]_0 [27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[28]),
.Q(\Q_reg[7]_0 [28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[29]),
.Q(\Q_reg[7]_0 [29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [0]),
.D(D[2]),
.Q(\Q_reg[7]_0 [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[30]),
.Q(\Q_reg[7]_0 [30]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [0]),
.D(D[3]),
.Q(\Q_reg[7]_0 [3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [0]),
.D(D[4]),
.Q(\Q_reg[7]_0 [4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [0]),
.D(D[5]),
.Q(\Q_reg[7]_0 [5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [0]),
.D(D[6]),
.Q(\Q_reg[7]_0 [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [0]),
.D(D[7]),
.Q(\Q_reg[7]_0 [7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[8]),
.Q(\Q_reg[7]_0 [8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[9]),
.Q(\Q_reg[7]_0 [9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized4
(\Q_reg[7]_0 ,
\FSM_sequential_state_reg_reg[3] ,
D,
CLK,
\FSM_sequential_state_reg_reg[3]_0 );
output [30:0]\Q_reg[7]_0 ;
input [0:0]\FSM_sequential_state_reg_reg[3] ;
input [30:0]D;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[3]_0 ;
wire CLK;
wire [30:0]D;
wire [0:0]\FSM_sequential_state_reg_reg[3] ;
wire [0:0]\FSM_sequential_state_reg_reg[3]_0 ;
wire [30:0]\Q_reg[7]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[0]),
.Q(\Q_reg[7]_0 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[10]),
.Q(\Q_reg[7]_0 [10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[11]),
.Q(\Q_reg[7]_0 [11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[12]),
.Q(\Q_reg[7]_0 [12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[13]),
.Q(\Q_reg[7]_0 [13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[14]),
.Q(\Q_reg[7]_0 [14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[15]),
.Q(\Q_reg[7]_0 [15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[16]),
.Q(\Q_reg[7]_0 [16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[17]),
.Q(\Q_reg[7]_0 [17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[18]),
.Q(\Q_reg[7]_0 [18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[19]),
.Q(\Q_reg[7]_0 [19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[1]),
.Q(\Q_reg[7]_0 [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[20]),
.Q(\Q_reg[7]_0 [20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[21]),
.Q(\Q_reg[7]_0 [21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[22]),
.Q(\Q_reg[7]_0 [22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[23]),
.Q(\Q_reg[7]_0 [23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[24]),
.Q(\Q_reg[7]_0 [24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[25]),
.Q(\Q_reg[7]_0 [25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[26]),
.Q(\Q_reg[7]_0 [26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[27]),
.Q(\Q_reg[7]_0 [27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[28]),
.Q(\Q_reg[7]_0 [28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[29]),
.Q(\Q_reg[7]_0 [29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[2]),
.Q(\Q_reg[7]_0 [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[30]),
.Q(\Q_reg[7]_0 [30]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[3]),
.Q(\Q_reg[7]_0 [3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[4]),
.Q(\Q_reg[7]_0 [4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[5]),
.Q(\Q_reg[7]_0 [5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[6]),
.Q(\Q_reg[7]_0 [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[7]),
.Q(\Q_reg[7]_0 [7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[8]),
.Q(\Q_reg[7]_0 [8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[9]),
.Q(\Q_reg[7]_0 [9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized5
(D,
Q,
Data_A,
\Q_reg[0]_0 ,
\Q_reg[0]_1 ,
\Q_reg[0]_2 ,
\Q_reg[23] ,
E,
\Q_reg[1]_0 ,
CLK,
AR);
output [7:0]D;
output [7:0]Q;
output [0:0]Data_A;
input \Q_reg[0]_0 ;
input \Q_reg[0]_1 ;
input \Q_reg[0]_2 ;
input [0:0]\Q_reg[23] ;
input [0:0]E;
input [7:0]\Q_reg[1]_0 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [7:0]D;
wire [0:0]Data_A;
wire [0:0]E;
wire [7:0]Q;
wire \Q_reg[0]_0 ;
wire \Q_reg[0]_1 ;
wire \Q_reg[0]_2 ;
wire [7:0]\Q_reg[1]_0 ;
wire [0:0]\Q_reg[23] ;
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hFE))
\Q[23]_i_1__1
(.I0(Q[0]),
.I1(\Q_reg[0]_0 ),
.I2(\Q_reg[0]_1 ),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hFE))
\Q[24]_i_1__1
(.I0(Q[1]),
.I1(\Q_reg[0]_0 ),
.I2(\Q_reg[0]_1 ),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hFE))
\Q[25]_i_1__1
(.I0(Q[2]),
.I1(\Q_reg[0]_0 ),
.I2(\Q_reg[0]_1 ),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hFE))
\Q[26]_i_1
(.I0(Q[3]),
.I1(\Q_reg[0]_0 ),
.I2(\Q_reg[0]_1 ),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hFE))
\Q[27]_i_1
(.I0(Q[4]),
.I1(\Q_reg[0]_0 ),
.I2(\Q_reg[0]_1 ),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hFE))
\Q[28]_i_1
(.I0(Q[5]),
.I1(\Q_reg[0]_0 ),
.I2(\Q_reg[0]_1 ),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hFE))
\Q[29]_i_1
(.I0(Q[6]),
.I1(\Q_reg[0]_0 ),
.I2(\Q_reg[0]_1 ),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hFE))
\Q[30]_i_1__0
(.I0(Q[7]),
.I1(\Q_reg[0]_0 ),
.I2(\Q_reg[0]_1 ),
.O(D[7]));
LUT3 #(
.INIT(8'hB8))
\Q[3]_i_2__1
(.I0(Q[0]),
.I1(\Q_reg[0]_2 ),
.I2(\Q_reg[23] ),
.O(Data_A));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[1]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[1]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[1]_0 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[1]_0 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[1]_0 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[1]_0 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[1]_0 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[1]_0 [7]),
.Q(Q[7]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized6
(D,
\Q_reg[16]_0 ,
Q,
\Q_reg[25]_0 ,
\Q_reg[17]_0 ,
\Q_reg[24]_0 ,
\Q_reg[18]_0 ,
\Q_reg[23]_0 ,
\Q_reg[19]_0 ,
\Q_reg[22]_0 ,
\Q_reg[20]_0 ,
\Q_reg[21]_0 ,
FSM_barrel_shifter_L_R,
\Q_reg[16]_1 ,
FSM_barrel_shifter_B_S,
\Q_reg[4]_0 ,
\Q_reg[3]_0 ,
\Q_reg[17]_1 ,
\Q_reg[2]_0 ,
CLK,
\FSM_sequential_state_reg_reg[3] );
output [9:0]D;
output \Q_reg[16]_0 ;
output [15:0]Q;
output \Q_reg[25]_0 ;
output \Q_reg[17]_0 ;
output \Q_reg[24]_0 ;
output \Q_reg[18]_0 ;
output \Q_reg[23]_0 ;
output \Q_reg[19]_0 ;
output \Q_reg[22]_0 ;
output \Q_reg[20]_0 ;
output \Q_reg[21]_0 ;
input FSM_barrel_shifter_L_R;
input \Q_reg[16]_1 ;
input FSM_barrel_shifter_B_S;
input \Q_reg[4]_0 ;
input \Q_reg[3]_0 ;
input \Q_reg[17]_1 ;
input [25:0]\Q_reg[2]_0 ;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[3] ;
wire CLK;
wire [9:0]D;
wire [9:0]\Data_array[4]_0 ;
wire FSM_barrel_shifter_B_S;
wire FSM_barrel_shifter_L_R;
wire [0:0]\FSM_sequential_state_reg_reg[3] ;
wire [15:0]Q;
wire \Q_reg[16]_0 ;
wire \Q_reg[16]_1 ;
wire \Q_reg[17]_0 ;
wire \Q_reg[17]_1 ;
wire \Q_reg[18]_0 ;
wire \Q_reg[19]_0 ;
wire \Q_reg[20]_0 ;
wire \Q_reg[21]_0 ;
wire \Q_reg[22]_0 ;
wire \Q_reg[23]_0 ;
wire \Q_reg[24]_0 ;
wire \Q_reg[25]_0 ;
wire [25:0]\Q_reg[2]_0 ;
wire \Q_reg[3]_0 ;
wire \Q_reg[4]_0 ;
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\Q[16]_i_1
(.I0(\Q_reg[16]_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q_reg[16]_1 ),
.O(D[0]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[16]_i_2
(.I0(Q[15]),
.I1(FSM_barrel_shifter_B_S),
.I2(\Q_reg[4]_0 ),
.I3(\Data_array[4]_0 [9]),
.I4(\Q_reg[3]_0 ),
.I5(Q[7]),
.O(\Q_reg[16]_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\Q[17]_i_1
(.I0(\Q_reg[17]_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q_reg[17]_1 ),
.O(D[1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[17]_i_2
(.I0(Q[14]),
.I1(FSM_barrel_shifter_B_S),
.I2(\Q_reg[4]_0 ),
.I3(\Data_array[4]_0 [8]),
.I4(\Q_reg[3]_0 ),
.I5(Q[6]),
.O(\Q_reg[17]_0 ));
LUT6 #(
.INIT(64'hBBB8BBBB8B888888))
\Q[18]_i_1
(.I0(\Q_reg[18]_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q_reg[4]_0 ),
.I3(Q[8]),
.I4(\Q_reg[3]_0 ),
.I5(FSM_barrel_shifter_B_S),
.O(D[2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[18]_i_2
(.I0(Q[13]),
.I1(FSM_barrel_shifter_B_S),
.I2(\Q_reg[4]_0 ),
.I3(\Data_array[4]_0 [7]),
.I4(\Q_reg[3]_0 ),
.I5(Q[5]),
.O(\Q_reg[18]_0 ));
LUT6 #(
.INIT(64'hBBB8BBBB8B888888))
\Q[19]_i_1
(.I0(\Q_reg[19]_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q_reg[4]_0 ),
.I3(Q[9]),
.I4(\Q_reg[3]_0 ),
.I5(FSM_barrel_shifter_B_S),
.O(D[3]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[19]_i_2
(.I0(Q[12]),
.I1(FSM_barrel_shifter_B_S),
.I2(\Q_reg[4]_0 ),
.I3(\Data_array[4]_0 [6]),
.I4(\Q_reg[3]_0 ),
.I5(Q[4]),
.O(\Q_reg[19]_0 ));
LUT6 #(
.INIT(64'hBBB8BBBB8B888888))
\Q[20]_i_1__0
(.I0(\Q_reg[20]_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q_reg[4]_0 ),
.I3(Q[10]),
.I4(\Q_reg[3]_0 ),
.I5(FSM_barrel_shifter_B_S),
.O(D[4]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[20]_i_2
(.I0(Q[11]),
.I1(FSM_barrel_shifter_B_S),
.I2(\Q_reg[4]_0 ),
.I3(\Data_array[4]_0 [5]),
.I4(\Q_reg[3]_0 ),
.I5(Q[3]),
.O(\Q_reg[20]_0 ));
LUT6 #(
.INIT(64'hBBB8BBBB8B888888))
\Q[21]_i_1__0
(.I0(\Q_reg[21]_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q_reg[4]_0 ),
.I3(Q[11]),
.I4(\Q_reg[3]_0 ),
.I5(FSM_barrel_shifter_B_S),
.O(D[5]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[21]_i_2
(.I0(Q[10]),
.I1(FSM_barrel_shifter_B_S),
.I2(\Q_reg[4]_0 ),
.I3(\Data_array[4]_0 [4]),
.I4(\Q_reg[3]_0 ),
.I5(Q[2]),
.O(\Q_reg[21]_0 ));
LUT6 #(
.INIT(64'hBBB8BBBB8B888888))
\Q[22]_i_1
(.I0(\Q_reg[22]_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q_reg[4]_0 ),
.I3(Q[12]),
.I4(\Q_reg[3]_0 ),
.I5(FSM_barrel_shifter_B_S),
.O(D[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[22]_i_2
(.I0(Q[9]),
.I1(FSM_barrel_shifter_B_S),
.I2(\Q_reg[4]_0 ),
.I3(\Data_array[4]_0 [3]),
.I4(\Q_reg[3]_0 ),
.I5(Q[1]),
.O(\Q_reg[22]_0 ));
LUT6 #(
.INIT(64'hBBB8BBBB8B888888))
\Q[23]_i_1
(.I0(\Q_reg[23]_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q_reg[4]_0 ),
.I3(Q[13]),
.I4(\Q_reg[3]_0 ),
.I5(FSM_barrel_shifter_B_S),
.O(D[7]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[23]_i_2
(.I0(Q[8]),
.I1(FSM_barrel_shifter_B_S),
.I2(\Q_reg[4]_0 ),
.I3(\Data_array[4]_0 [2]),
.I4(\Q_reg[3]_0 ),
.I5(Q[0]),
.O(\Q_reg[23]_0 ));
LUT6 #(
.INIT(64'hBBB8BBBB8B888888))
\Q[24]_i_1__0
(.I0(\Q_reg[24]_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q_reg[4]_0 ),
.I3(Q[14]),
.I4(\Q_reg[3]_0 ),
.I5(FSM_barrel_shifter_B_S),
.O(D[8]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[24]_i_2__0
(.I0(Q[7]),
.I1(Q[15]),
.I2(\Q_reg[4]_0 ),
.I3(\Data_array[4]_0 [1]),
.I4(\Q_reg[3]_0 ),
.I5(\Data_array[4]_0 [9]),
.O(\Q_reg[24]_0 ));
LUT6 #(
.INIT(64'hBBB8BBBB8B888888))
\Q[25]_i_2
(.I0(\Q_reg[25]_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q_reg[4]_0 ),
.I3(Q[15]),
.I4(\Q_reg[3]_0 ),
.I5(FSM_barrel_shifter_B_S),
.O(D[9]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[25]_i_3__0
(.I0(Q[6]),
.I1(Q[14]),
.I2(\Q_reg[4]_0 ),
.I3(\Data_array[4]_0 [0]),
.I4(\Q_reg[3]_0 ),
.I5(\Data_array[4]_0 [8]),
.O(\Q_reg[25]_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [0]),
.Q(\Data_array[4]_0 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [10]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [11]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [12]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [13]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [14]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [15]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [16]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [17]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [18]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [19]),
.Q(Q[9]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [1]),
.Q(\Data_array[4]_0 [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [20]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [21]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [22]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [23]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [24]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [25]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [2]),
.Q(\Data_array[4]_0 [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [3]),
.Q(\Data_array[4]_0 [3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [4]),
.Q(\Data_array[4]_0 [4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [5]),
.Q(\Data_array[4]_0 [5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [6]),
.Q(\Data_array[4]_0 [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [7]),
.Q(\Data_array[4]_0 [7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [8]),
.Q(\Data_array[4]_0 [8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [9]),
.Q(\Data_array[4]_0 [9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized7
(round_flag,
\Q_reg[0]_0 ,
r_mode_IBUF,
sign_final_result,
E,
D,
CLK,
AR);
output round_flag;
output [25:0]\Q_reg[0]_0 ;
input [1:0]r_mode_IBUF;
input sign_final_result;
input [0:0]E;
input [25:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [25:0]D;
wire [0:0]E;
wire [25:0]\Q_reg[0]_0 ;
wire [1:0]r_mode_IBUF;
wire round_flag;
wire sign_final_result;
LUT5 #(
.INIT(32'h0E0000E0))
\FSM_sequential_state_reg[2]_i_2
(.I0(\Q_reg[0]_0 [1]),
.I1(\Q_reg[0]_0 [0]),
.I2(r_mode_IBUF[1]),
.I3(sign_final_result),
.I4(r_mode_IBUF[0]),
.O(round_flag));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[0]),
.Q(\Q_reg[0]_0 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[10]),
.Q(\Q_reg[0]_0 [10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[11]),
.Q(\Q_reg[0]_0 [11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[12]),
.Q(\Q_reg[0]_0 [12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[13]),
.Q(\Q_reg[0]_0 [13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[14]),
.Q(\Q_reg[0]_0 [14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[15]),
.Q(\Q_reg[0]_0 [15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[16]),
.Q(\Q_reg[0]_0 [16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[17]),
.Q(\Q_reg[0]_0 [17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[18]),
.Q(\Q_reg[0]_0 [18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[19]),
.Q(\Q_reg[0]_0 [19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[1]),
.Q(\Q_reg[0]_0 [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[20]),
.Q(\Q_reg[0]_0 [20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[21]),
.Q(\Q_reg[0]_0 [21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[22]),
.Q(\Q_reg[0]_0 [22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[23]),
.Q(\Q_reg[0]_0 [23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[24]),
.Q(\Q_reg[0]_0 [24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[25]),
.Q(\Q_reg[0]_0 [25]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[2]),
.Q(\Q_reg[0]_0 [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[3]),
.Q(\Q_reg[0]_0 [3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[4]),
.Q(\Q_reg[0]_0 [4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[5]),
.Q(\Q_reg[0]_0 [5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[6]),
.Q(\Q_reg[0]_0 [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[7]),
.Q(\Q_reg[0]_0 [7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[8]),
.Q(\Q_reg[0]_0 [8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[9]),
.Q(\Q_reg[0]_0 [9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized8
(D,
\Q_reg[18]_0 ,
\Q_reg[16]_0 ,
\Q_reg[17]_0 ,
\Q_reg[15]_0 ,
Q,
\Q_reg[4]_0 ,
FSM_barrel_shifter_B_S,
\Q_reg[2]_0 ,
\Q_reg[1]_0 ,
\Q_reg[0]_0 ,
FSM_selector_C,
FSM_barrel_shifter_L_R,
\Q_reg[0]_1 ,
\Q_reg[0]_2 ,
FSM_selector_B,
\Q_reg[0]_3 ,
\Q_reg[22]_0 ,
E,
\Q_reg[31] ,
CLK,
AR);
output [20:0]D;
output \Q_reg[18]_0 ;
output \Q_reg[16]_0 ;
output \Q_reg[17]_0 ;
output \Q_reg[15]_0 ;
output [1:0]Q;
output [4:0]\Q_reg[4]_0 ;
input FSM_barrel_shifter_B_S;
input \Q_reg[2]_0 ;
input \Q_reg[1]_0 ;
input \Q_reg[0]_0 ;
input FSM_selector_C;
input FSM_barrel_shifter_L_R;
input \Q_reg[0]_1 ;
input [0:0]\Q_reg[0]_2 ;
input [1:0]FSM_selector_B;
input [0:0]\Q_reg[0]_3 ;
input [22:0]\Q_reg[22]_0 ;
input [0:0]E;
input [25:0]\Q_reg[31] ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [20:0]D;
wire [0:0]E;
wire FSM_barrel_shifter_B_S;
wire FSM_barrel_shifter_L_R;
wire [1:0]FSM_selector_B;
wire FSM_selector_C;
wire [1:0]Q;
wire \Q[0]_i_2__0_n_0 ;
wire \Q[0]_i_2_n_0 ;
wire \Q[0]_i_3__0_n_0 ;
wire \Q[0]_i_4__0_n_0 ;
wire \Q[0]_i_5__0_n_0 ;
wire \Q[0]_i_6_n_0 ;
wire \Q[0]_i_7_n_0 ;
wire \Q[0]_i_8_n_0 ;
wire \Q[0]_i_9_n_0 ;
wire \Q[10]_i_2_n_0 ;
wire \Q[10]_i_3_n_0 ;
wire \Q[11]_i_2_n_0 ;
wire \Q[11]_i_3_n_0 ;
wire \Q[11]_i_4_n_0 ;
wire \Q[12]_i_2_n_0 ;
wire \Q[12]_i_3_n_0 ;
wire \Q[13]_i_2__0_n_0 ;
wire \Q[13]_i_3__0_n_0 ;
wire \Q[14]_i_2__0_n_0 ;
wire \Q[14]_i_3__0_n_0 ;
wire \Q[15]_i_2__0_n_0 ;
wire \Q[15]_i_3__0_n_0 ;
wire \Q[16]_i_2__0_n_0 ;
wire \Q[16]_i_3__0_n_0 ;
wire \Q[17]_i_2__0_n_0 ;
wire \Q[17]_i_3__0_n_0 ;
wire \Q[18]_i_2__0_n_0 ;
wire \Q[18]_i_3_n_0 ;
wire \Q[19]_i_2__0_n_0 ;
wire \Q[19]_i_3_n_0 ;
wire \Q[1]_i_2__0_n_0 ;
wire \Q[1]_i_2_n_0 ;
wire \Q[1]_i_3__0_n_0 ;
wire \Q[1]_i_3_n_0 ;
wire \Q[1]_i_4_n_0 ;
wire \Q[1]_i_5_n_0 ;
wire \Q[1]_i_6_n_0 ;
wire \Q[1]_i_7_n_0 ;
wire \Q[20]_i_2__0_n_0 ;
wire \Q[20]_i_3_n_0 ;
wire \Q[21]_i_3_n_0 ;
wire \Q[22]_i_3_n_0 ;
wire \Q[23]_i_3_n_0 ;
wire \Q[24]_i_3_n_0 ;
wire \Q[2]_i_2__0_n_0 ;
wire \Q[2]_i_2_n_0 ;
wire \Q[2]_i_3__0_n_0 ;
wire \Q[2]_i_3_n_0 ;
wire \Q[2]_i_4_n_0 ;
wire \Q[3]_i_2_n_0 ;
wire \Q[3]_i_3_n_0 ;
wire \Q[4]_i_2_n_0 ;
wire \Q[4]_i_3__0_n_0 ;
wire \Q[4]_i_3_n_0 ;
wire \Q[4]_i_4_n_0 ;
wire \Q[4]_i_5_n_0 ;
wire \Q[4]_i_6_n_0 ;
wire \Q[4]_i_7_n_0 ;
wire \Q[4]_i_8_n_0 ;
wire \Q[5]_i_2_n_0 ;
wire \Q[5]_i_3_n_0 ;
wire \Q[6]_i_2_n_0 ;
wire \Q[6]_i_3_n_0 ;
wire \Q[7]_i_2__0_n_0 ;
wire \Q[7]_i_3_n_0 ;
wire \Q[8]_i_2_n_0 ;
wire \Q[8]_i_3_n_0 ;
wire \Q[9]_i_2_n_0 ;
wire \Q[9]_i_3_n_0 ;
wire \Q_reg[0]_0 ;
wire \Q_reg[0]_1 ;
wire [0:0]\Q_reg[0]_2 ;
wire [0:0]\Q_reg[0]_3 ;
wire \Q_reg[15]_0 ;
wire \Q_reg[16]_0 ;
wire \Q_reg[17]_0 ;
wire \Q_reg[18]_0 ;
wire \Q_reg[1]_0 ;
wire [22:0]\Q_reg[22]_0 ;
wire \Q_reg[2]_0 ;
wire [25:0]\Q_reg[31] ;
wire [4:0]\Q_reg[4]_0 ;
wire \Q_reg_n_0_[10] ;
wire \Q_reg_n_0_[11] ;
wire \Q_reg_n_0_[12] ;
wire \Q_reg_n_0_[13] ;
wire \Q_reg_n_0_[14] ;
wire \Q_reg_n_0_[15] ;
wire \Q_reg_n_0_[16] ;
wire \Q_reg_n_0_[17] ;
wire \Q_reg_n_0_[18] ;
wire \Q_reg_n_0_[19] ;
wire \Q_reg_n_0_[1] ;
wire \Q_reg_n_0_[20] ;
wire \Q_reg_n_0_[21] ;
wire \Q_reg_n_0_[22] ;
wire \Q_reg_n_0_[23] ;
wire \Q_reg_n_0_[24] ;
wire \Q_reg_n_0_[2] ;
wire \Q_reg_n_0_[3] ;
wire \Q_reg_n_0_[4] ;
wire \Q_reg_n_0_[5] ;
wire \Q_reg_n_0_[6] ;
wire \Q_reg_n_0_[7] ;
wire \Q_reg_n_0_[8] ;
wire \Q_reg_n_0_[9] ;
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[0]_i_1__2
(.I0(\Q[4]_i_2_n_0 ),
.I1(\Q[6]_i_2_n_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[0]_i_2_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[2]_i_2_n_0 ),
.O(D[0]));
LUT6 #(
.INIT(64'h00000000FFFF00AE))
\Q[0]_i_1__4
(.I0(\Q[0]_i_2__0_n_0 ),
.I1(\Q[0]_i_3__0_n_0 ),
.I2(\Q[0]_i_4__0_n_0 ),
.I3(\Q[0]_i_5__0_n_0 ),
.I4(\Q_reg_n_0_[24] ),
.I5(Q[1]),
.O(\Q_reg[4]_0 [0]));
LUT6 #(
.INIT(64'hB8BBB8BBBB888888))
\Q[0]_i_2
(.I0(\Q[1]_i_3_n_0 ),
.I1(\Q_reg[0]_1 ),
.I2(Q[1]),
.I3(FSM_selector_C),
.I4(Q[0]),
.I5(FSM_barrel_shifter_L_R),
.O(\Q[0]_i_2_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\Q[0]_i_2__0
(.I0(\Q[0]_i_6_n_0 ),
.I1(\Q_reg_n_0_[22] ),
.I2(\Q_reg_n_0_[20] ),
.I3(\Q_reg_n_0_[18] ),
.O(\Q[0]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF44F4))
\Q[0]_i_3__0
(.I0(\Q_reg_n_0_[7] ),
.I1(\Q[0]_i_7_n_0 ),
.I2(\Q_reg_n_0_[10] ),
.I3(\Q_reg_n_0_[11] ),
.I4(\Q_reg_n_0_[8] ),
.I5(\Q_reg_n_0_[12] ),
.O(\Q[0]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'hFEFF))
\Q[0]_i_4__0
(.I0(\Q_reg_n_0_[15] ),
.I1(\Q_reg_n_0_[17] ),
.I2(\Q_reg_n_0_[13] ),
.I3(\Q[0]_i_8_n_0 ),
.O(\Q[0]_i_4__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'hBABBBABA))
\Q[0]_i_5__0
(.I0(\Q_reg_n_0_[23] ),
.I1(\Q_reg_n_0_[22] ),
.I2(\Q_reg_n_0_[21] ),
.I3(\Q_reg_n_0_[20] ),
.I4(\Q_reg_n_0_[19] ),
.O(\Q[0]_i_5__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h00F2))
\Q[0]_i_6
(.I0(\Q_reg_n_0_[14] ),
.I1(\Q_reg_n_0_[15] ),
.I2(\Q_reg_n_0_[16] ),
.I3(\Q_reg_n_0_[17] ),
.O(\Q[0]_i_6_n_0 ));
LUT6 #(
.INIT(64'hCCCCCCCCEFEFEFEE))
\Q[0]_i_7
(.I0(\Q_reg_n_0_[4] ),
.I1(\Q_reg_n_0_[6] ),
.I2(\Q_reg_n_0_[3] ),
.I3(\Q[0]_i_9_n_0 ),
.I4(\Q_reg_n_0_[2] ),
.I5(\Q_reg_n_0_[5] ),
.O(\Q[0]_i_7_n_0 ));
LUT4 #(
.INIT(16'hFF0B))
\Q[0]_i_8
(.I0(\Q_reg_n_0_[10] ),
.I1(\Q_reg_n_0_[9] ),
.I2(\Q_reg_n_0_[11] ),
.I3(\Q_reg_n_0_[12] ),
.O(\Q[0]_i_8_n_0 ));
LUT2 #(
.INIT(4'h2))
\Q[0]_i_9
(.I0(Q[0]),
.I1(\Q_reg_n_0_[1] ),
.O(\Q[0]_i_9_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[10]_i_1__0
(.I0(\Q[14]_i_2__0_n_0 ),
.I1(\Q[16]_i_2__0_n_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[10]_i_2_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[12]_i_2_n_0 ),
.O(D[10]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[10]_i_2
(.I0(\Q[11]_i_4_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[10]_i_3_n_0 ),
.O(\Q[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[10]_i_3
(.I0(\Q_reg_n_0_[15] ),
.I1(\Q_reg[22]_0 [13]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[10] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [8]),
.O(\Q[10]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[11]_i_1__0
(.I0(\Q[15]_i_2__0_n_0 ),
.I1(\Q[17]_i_2__0_n_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[11]_i_2_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[13]_i_2__0_n_0 ),
.O(D[11]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[11]_i_2
(.I0(\Q[11]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[11]_i_4_n_0 ),
.O(\Q[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[11]_i_3
(.I0(\Q_reg_n_0_[13] ),
.I1(\Q_reg[22]_0 [11]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[12] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [10]),
.O(\Q[11]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[11]_i_4
(.I0(\Q_reg_n_0_[14] ),
.I1(\Q_reg[22]_0 [12]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[11] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [9]),
.O(\Q[11]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[12]_i_1__0
(.I0(\Q[16]_i_2__0_n_0 ),
.I1(\Q[18]_i_2__0_n_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[12]_i_2_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[14]_i_2__0_n_0 ),
.O(D[12]));
LUT6 #(
.INIT(64'hEFEADFD545408A80))
\Q[12]_i_2
(.I0(\Q_reg[0]_1 ),
.I1(\Q_reg_n_0_[13] ),
.I2(FSM_selector_C),
.I3(\Q_reg[22]_0 [11]),
.I4(FSM_barrel_shifter_L_R),
.I5(\Q[12]_i_3_n_0 ),
.O(\Q[12]_i_2_n_0 ));
LUT3 #(
.INIT(8'hB8))
\Q[12]_i_3
(.I0(\Q_reg_n_0_[12] ),
.I1(FSM_selector_C),
.I2(\Q_reg[22]_0 [10]),
.O(\Q[12]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[13]_i_1__0
(.I0(\Q[17]_i_2__0_n_0 ),
.I1(\Q[19]_i_2__0_n_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[13]_i_2__0_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[15]_i_2__0_n_0 ),
.O(D[13]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[13]_i_2__0
(.I0(\Q[14]_i_3__0_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[13]_i_3__0_n_0 ),
.O(\Q[13]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[13]_i_3__0
(.I0(\Q_reg_n_0_[12] ),
.I1(\Q_reg[22]_0 [10]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[13] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [11]),
.O(\Q[13]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[14]_i_1__0
(.I0(\Q[18]_i_2__0_n_0 ),
.I1(\Q[20]_i_2__0_n_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[14]_i_2__0_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[16]_i_2__0_n_0 ),
.O(D[14]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[14]_i_2__0
(.I0(\Q[15]_i_3__0_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[14]_i_3__0_n_0 ),
.O(\Q[14]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[14]_i_3__0
(.I0(\Q_reg_n_0_[11] ),
.I1(\Q_reg[22]_0 [9]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[14] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [12]),
.O(\Q[14]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[15]_i_1__0
(.I0(\Q[19]_i_2__0_n_0 ),
.I1(\Q_reg[15]_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[15]_i_2__0_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[17]_i_2__0_n_0 ),
.O(D[15]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[15]_i_2__0
(.I0(\Q[16]_i_3__0_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[15]_i_3__0_n_0 ),
.O(\Q[15]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[15]_i_3__0
(.I0(\Q_reg_n_0_[10] ),
.I1(\Q_reg[22]_0 [8]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[15] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [13]),
.O(\Q[15]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[16]_i_1__0
(.I0(\Q[20]_i_2__0_n_0 ),
.I1(\Q_reg[16]_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[16]_i_2__0_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[18]_i_2__0_n_0 ),
.O(D[16]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[16]_i_2__0
(.I0(\Q[17]_i_3__0_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[16]_i_3__0_n_0 ),
.O(\Q[16]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[16]_i_3__0
(.I0(\Q_reg_n_0_[9] ),
.I1(\Q_reg[22]_0 [7]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[16] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [14]),
.O(\Q[16]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[17]_i_1__0
(.I0(\Q_reg[15]_0 ),
.I1(\Q_reg[17]_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[17]_i_2__0_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[19]_i_2__0_n_0 ),
.O(D[17]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[17]_i_2__0
(.I0(\Q[18]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[17]_i_3__0_n_0 ),
.O(\Q[17]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[17]_i_3__0
(.I0(\Q_reg_n_0_[8] ),
.I1(\Q_reg[22]_0 [6]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[17] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [15]),
.O(\Q[17]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[18]_i_1__0
(.I0(\Q_reg[16]_0 ),
.I1(\Q_reg[18]_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[18]_i_2__0_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[20]_i_2__0_n_0 ),
.O(D[18]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[18]_i_2__0
(.I0(\Q[19]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[18]_i_3_n_0 ),
.O(\Q[18]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[18]_i_3
(.I0(\Q_reg_n_0_[7] ),
.I1(\Q_reg[22]_0 [5]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[18] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [16]),
.O(\Q[18]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[19]_i_1__0
(.I0(\Q_reg[17]_0 ),
.I1(\Q_reg[0]_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[19]_i_2__0_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q_reg[15]_0 ),
.O(D[19]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[19]_i_2__0
(.I0(\Q[20]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[19]_i_3_n_0 ),
.O(\Q[19]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[19]_i_3
(.I0(\Q_reg_n_0_[6] ),
.I1(\Q_reg[22]_0 [4]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[19] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [17]),
.O(\Q[19]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[1]_i_1__0
(.I0(\Q[5]_i_2_n_0 ),
.I1(\Q[7]_i_2__0_n_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[1]_i_2_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[3]_i_2_n_0 ),
.O(D[1]));
LUT6 #(
.INIT(64'h1111111111110010))
\Q[1]_i_1__1
(.I0(Q[1]),
.I1(\Q_reg_n_0_[24] ),
.I2(\Q[1]_i_2__0_n_0 ),
.I3(\Q[1]_i_3__0_n_0 ),
.I4(\Q_reg_n_0_[22] ),
.I5(\Q_reg_n_0_[23] ),
.O(\Q_reg[4]_0 [1]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[1]_i_2
(.I0(\Q[2]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[1]_i_3_n_0 ),
.O(\Q[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h1))
\Q[1]_i_2__0
(.I0(\Q_reg_n_0_[20] ),
.I1(\Q_reg_n_0_[21] ),
.O(\Q[1]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hAFC0A0C0))
\Q[1]_i_3
(.I0(\Q_reg_n_0_[24] ),
.I1(\Q_reg[22]_0 [22]),
.I2(FSM_barrel_shifter_L_R),
.I3(FSM_selector_C),
.I4(\Q_reg_n_0_[1] ),
.O(\Q[1]_i_3_n_0 ));
LUT6 #(
.INIT(64'h1111111111110010))
\Q[1]_i_3__0
(.I0(\Q_reg_n_0_[19] ),
.I1(\Q_reg_n_0_[18] ),
.I2(\Q[1]_i_4_n_0 ),
.I3(\Q[1]_i_5_n_0 ),
.I4(\Q_reg_n_0_[16] ),
.I5(\Q_reg_n_0_[17] ),
.O(\Q[1]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h1))
\Q[1]_i_4
(.I0(\Q_reg_n_0_[14] ),
.I1(\Q_reg_n_0_[15] ),
.O(\Q[1]_i_4_n_0 ));
LUT6 #(
.INIT(64'h1111111111110010))
\Q[1]_i_5
(.I0(\Q_reg_n_0_[13] ),
.I1(\Q_reg_n_0_[12] ),
.I2(\Q[1]_i_6_n_0 ),
.I3(\Q[1]_i_7_n_0 ),
.I4(\Q_reg_n_0_[10] ),
.I5(\Q_reg_n_0_[11] ),
.O(\Q[1]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h1))
\Q[1]_i_6
(.I0(\Q_reg_n_0_[8] ),
.I1(\Q_reg_n_0_[9] ),
.O(\Q[1]_i_6_n_0 ));
LUT6 #(
.INIT(64'h1110111011101111))
\Q[1]_i_7
(.I0(\Q_reg_n_0_[6] ),
.I1(\Q_reg_n_0_[7] ),
.I2(\Q_reg_n_0_[4] ),
.I3(\Q_reg_n_0_[5] ),
.I4(\Q_reg_n_0_[2] ),
.I5(\Q_reg_n_0_[3] ),
.O(\Q[1]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[20]_i_1
(.I0(\Q_reg[18]_0 ),
.I1(FSM_barrel_shifter_B_S),
.I2(\Q_reg[2]_0 ),
.I3(\Q[20]_i_2__0_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q_reg[16]_0 ),
.O(D[20]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[20]_i_2__0
(.I0(\Q[21]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[20]_i_3_n_0 ),
.O(\Q[20]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[20]_i_3
(.I0(\Q_reg_n_0_[5] ),
.I1(\Q_reg[22]_0 [3]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[20] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [18]),
.O(\Q[20]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[21]_i_2__0
(.I0(\Q[22]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[21]_i_3_n_0 ),
.O(\Q_reg[15]_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[21]_i_3
(.I0(\Q_reg_n_0_[4] ),
.I1(\Q_reg[22]_0 [2]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[21] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [19]),
.O(\Q[21]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[22]_i_2__0
(.I0(\Q[23]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[22]_i_3_n_0 ),
.O(\Q_reg[16]_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[22]_i_3
(.I0(\Q_reg_n_0_[3] ),
.I1(\Q_reg[22]_0 [1]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[22] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [20]),
.O(\Q[22]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[23]_i_2__0
(.I0(\Q[24]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[23]_i_3_n_0 ),
.O(\Q_reg[17]_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[23]_i_3
(.I0(\Q_reg_n_0_[2] ),
.I1(\Q_reg[22]_0 [0]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[23] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [21]),
.O(\Q[23]_i_3_n_0 ));
LUT6 #(
.INIT(64'h88F3FFFF88F30000))
\Q[24]_i_2
(.I0(Q[0]),
.I1(FSM_selector_C),
.I2(Q[1]),
.I3(FSM_barrel_shifter_L_R),
.I4(\Q_reg[0]_1 ),
.I5(\Q[24]_i_3_n_0 ),
.O(\Q_reg[18]_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hB833B800))
\Q[24]_i_3
(.I0(\Q_reg_n_0_[1] ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q_reg_n_0_[24] ),
.I3(FSM_selector_C),
.I4(\Q_reg[22]_0 [22]),
.O(\Q[24]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[2]_i_1__0
(.I0(\Q[6]_i_2_n_0 ),
.I1(\Q[8]_i_2_n_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[2]_i_2_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[4]_i_2_n_0 ),
.O(D[2]));
LUT6 #(
.INIT(64'h0001000000010001))
\Q[2]_i_1__1
(.I0(\Q_reg_n_0_[22] ),
.I1(\Q_reg_n_0_[23] ),
.I2(\Q_reg_n_0_[24] ),
.I3(Q[1]),
.I4(\Q[2]_i_2__0_n_0 ),
.I5(\Q[2]_i_3__0_n_0 ),
.O(\Q_reg[4]_0 [2]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[2]_i_2
(.I0(\Q[3]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[2]_i_3_n_0 ),
.O(\Q[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00808888AAAAAAAA))
\Q[2]_i_2__0
(.I0(\Q[4]_i_7_n_0 ),
.I1(\Q[4]_i_4_n_0 ),
.I2(Q[0]),
.I3(\Q_reg_n_0_[1] ),
.I4(\Q[4]_i_3__0_n_0 ),
.I5(\Q[2]_i_4_n_0 ),
.O(\Q[2]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[2]_i_3
(.I0(\Q_reg_n_0_[23] ),
.I1(\Q_reg[22]_0 [21]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[2] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [0]),
.O(\Q[2]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0001))
\Q[2]_i_3__0
(.I0(\Q_reg_n_0_[21] ),
.I1(\Q_reg_n_0_[20] ),
.I2(\Q_reg_n_0_[19] ),
.I3(\Q_reg_n_0_[18] ),
.O(\Q[2]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0001))
\Q[2]_i_4
(.I0(\Q_reg_n_0_[11] ),
.I1(\Q_reg_n_0_[10] ),
.I2(\Q_reg_n_0_[13] ),
.I3(\Q_reg_n_0_[12] ),
.O(\Q[2]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[3]_i_1__0
(.I0(\Q[7]_i_2__0_n_0 ),
.I1(\Q[9]_i_2_n_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[3]_i_2_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[5]_i_2_n_0 ),
.O(D[3]));
LUT5 #(
.INIT(32'h8000AAAA))
\Q[3]_i_1__1
(.I0(\Q[4]_i_6_n_0 ),
.I1(\Q[4]_i_4_n_0 ),
.I2(\Q[4]_i_3__0_n_0 ),
.I3(\Q_reg_n_0_[1] ),
.I4(\Q[4]_i_5_n_0 ),
.O(\Q_reg[4]_0 [3]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[3]_i_2
(.I0(\Q[4]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[3]_i_3_n_0 ),
.O(\Q[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[3]_i_3
(.I0(\Q_reg_n_0_[22] ),
.I1(\Q_reg[22]_0 [20]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[3] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [1]),
.O(\Q[3]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[4]_i_1__1
(.I0(\Q[8]_i_2_n_0 ),
.I1(\Q[10]_i_2_n_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[4]_i_2_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[6]_i_2_n_0 ),
.O(D[4]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[4]_i_2
(.I0(\Q[5]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[4]_i_3_n_0 ),
.O(\Q[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFDFF000000000000))
\Q[4]_i_2__0
(.I0(\Q[4]_i_3__0_n_0 ),
.I1(\Q_reg_n_0_[1] ),
.I2(Q[0]),
.I3(\Q[4]_i_4_n_0 ),
.I4(\Q[4]_i_5_n_0 ),
.I5(\Q[4]_i_6_n_0 ),
.O(\Q_reg[4]_0 [4]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[4]_i_3
(.I0(\Q_reg_n_0_[21] ),
.I1(\Q_reg[22]_0 [19]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[4] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [2]),
.O(\Q[4]_i_3_n_0 ));
LUT4 #(
.INIT(16'h0001))
\Q[4]_i_3__0
(.I0(\Q_reg_n_0_[3] ),
.I1(\Q_reg_n_0_[2] ),
.I2(\Q_reg_n_0_[5] ),
.I3(\Q_reg_n_0_[4] ),
.O(\Q[4]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h0001))
\Q[4]_i_4
(.I0(\Q_reg_n_0_[9] ),
.I1(\Q_reg_n_0_[8] ),
.I2(\Q_reg_n_0_[6] ),
.I3(\Q_reg_n_0_[7] ),
.O(\Q[4]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h00010000))
\Q[4]_i_5
(.I0(\Q_reg_n_0_[12] ),
.I1(\Q_reg_n_0_[13] ),
.I2(\Q_reg_n_0_[10] ),
.I3(\Q_reg_n_0_[11] ),
.I4(\Q[4]_i_7_n_0 ),
.O(\Q[4]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h00010000))
\Q[4]_i_6
(.I0(\Q_reg_n_0_[18] ),
.I1(\Q_reg_n_0_[19] ),
.I2(\Q_reg_n_0_[20] ),
.I3(\Q_reg_n_0_[21] ),
.I4(\Q[4]_i_8_n_0 ),
.O(\Q[4]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h0001))
\Q[4]_i_7
(.I0(\Q_reg_n_0_[17] ),
.I1(\Q_reg_n_0_[16] ),
.I2(\Q_reg_n_0_[15] ),
.I3(\Q_reg_n_0_[14] ),
.O(\Q[4]_i_7_n_0 ));
LUT4 #(
.INIT(16'h0001))
\Q[4]_i_8
(.I0(Q[1]),
.I1(\Q_reg_n_0_[24] ),
.I2(\Q_reg_n_0_[23] ),
.I3(\Q_reg_n_0_[22] ),
.O(\Q[4]_i_8_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[5]_i_1__0
(.I0(\Q[9]_i_2_n_0 ),
.I1(\Q[11]_i_2_n_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[5]_i_2_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[7]_i_2__0_n_0 ),
.O(D[5]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[5]_i_2
(.I0(\Q[6]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[5]_i_3_n_0 ),
.O(\Q[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[5]_i_3
(.I0(\Q_reg_n_0_[20] ),
.I1(\Q_reg[22]_0 [18]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[5] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [3]),
.O(\Q[5]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[6]_i_1__0
(.I0(\Q[10]_i_2_n_0 ),
.I1(\Q[12]_i_2_n_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[6]_i_2_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[8]_i_2_n_0 ),
.O(D[6]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[6]_i_2
(.I0(\Q[7]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[6]_i_3_n_0 ),
.O(\Q[6]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[6]_i_3
(.I0(\Q_reg_n_0_[19] ),
.I1(\Q_reg[22]_0 [17]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[6] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [4]),
.O(\Q[6]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[7]_i_1__1
(.I0(\Q[11]_i_2_n_0 ),
.I1(\Q[13]_i_2__0_n_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[7]_i_2__0_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[9]_i_2_n_0 ),
.O(D[7]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[7]_i_2__0
(.I0(\Q[8]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[7]_i_3_n_0 ),
.O(\Q[7]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[7]_i_3
(.I0(\Q_reg_n_0_[18] ),
.I1(\Q_reg[22]_0 [16]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[7] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [5]),
.O(\Q[7]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[8]_i_1__0
(.I0(\Q[12]_i_2_n_0 ),
.I1(\Q[14]_i_2__0_n_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[8]_i_2_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[10]_i_2_n_0 ),
.O(D[8]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[8]_i_2
(.I0(\Q[9]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[8]_i_3_n_0 ),
.O(\Q[8]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[8]_i_3
(.I0(\Q_reg_n_0_[17] ),
.I1(\Q_reg[22]_0 [15]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[8] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [6]),
.O(\Q[8]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[9]_i_1__0
(.I0(\Q[13]_i_2__0_n_0 ),
.I1(\Q[15]_i_2__0_n_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[9]_i_2_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[11]_i_2_n_0 ),
.O(D[9]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[9]_i_2
(.I0(\Q[10]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[9]_i_3_n_0 ),
.O(\Q[9]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[9]_i_3
(.I0(\Q_reg_n_0_[16] ),
.I1(\Q_reg[22]_0 [14]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[9] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [7]),
.O(\Q[9]_i_3_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [10]),
.Q(\Q_reg_n_0_[10] ));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [11]),
.Q(\Q_reg_n_0_[11] ));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [12]),
.Q(\Q_reg_n_0_[12] ));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [13]),
.Q(\Q_reg_n_0_[13] ));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [14]),
.Q(\Q_reg_n_0_[14] ));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [15]),
.Q(\Q_reg_n_0_[15] ));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [16]),
.Q(\Q_reg_n_0_[16] ));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [17]),
.Q(\Q_reg_n_0_[17] ));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [18]),
.Q(\Q_reg_n_0_[18] ));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [19]),
.Q(\Q_reg_n_0_[19] ));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [1]),
.Q(\Q_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [20]),
.Q(\Q_reg_n_0_[20] ));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [21]),
.Q(\Q_reg_n_0_[21] ));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [22]),
.Q(\Q_reg_n_0_[22] ));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [23]),
.Q(\Q_reg_n_0_[23] ));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [24]),
.Q(\Q_reg_n_0_[24] ));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [25]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [2]),
.Q(\Q_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [3]),
.Q(\Q_reg_n_0_[3] ));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [4]),
.Q(\Q_reg_n_0_[4] ));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [5]),
.Q(\Q_reg_n_0_[5] ));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [6]),
.Q(\Q_reg_n_0_[6] ));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [7]),
.Q(\Q_reg_n_0_[7] ));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [8]),
.Q(\Q_reg_n_0_[8] ));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [9]),
.Q(\Q_reg_n_0_[9] ));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized9
(Q,
E,
D,
CLK,
\FSM_sequential_state_reg_reg[3] );
output [4:0]Q;
input [0:0]E;
input [4:0]D;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[3] ;
wire CLK;
wire [4:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[3] ;
wire [4:0]Q;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[4]),
.Q(Q[4]));
endmodule
module Tenth_Phase
(Q,
E,
D,
CLK,
AR);
output [31:0]Q;
input [0:0]E;
input [31:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [31:0]Q;
RegisterAdd__parameterized10 Final_Result_IEEE
(.AR(AR),
.CLK(CLK),
.D(D),
.E(E),
.Q(Q));
endmodule
module add_sub_carry_out
(S,
\Q_reg[3] ,
\Q_reg[30] ,
\Q_reg[1] ,
FSM_exp_operation_A_S,
\Q_reg[30]_0 ,
\Q_reg[0] ,
Q,
DI,
\Q_reg[26] ,
FSM_selector_B,
\Q_reg[0]_0 );
output [3:0]S;
output [3:0]\Q_reg[3] ;
input [3:0]\Q_reg[30] ;
input \Q_reg[1] ;
input FSM_exp_operation_A_S;
input [6:0]\Q_reg[30]_0 ;
input \Q_reg[0] ;
input [6:0]Q;
input [0:0]DI;
input [2:0]\Q_reg[26] ;
input [1:0]FSM_selector_B;
input [0:0]\Q_reg[0]_0 ;
wire [0:0]DI;
wire FSM_exp_operation_A_S;
wire [1:0]FSM_selector_B;
wire [6:0]Q;
wire \Q_reg[0] ;
wire [0:0]\Q_reg[0]_0 ;
wire \Q_reg[1] ;
wire [2:0]\Q_reg[26] ;
wire [3:0]\Q_reg[30] ;
wire [6:0]\Q_reg[30]_0 ;
wire [3:0]\Q_reg[3] ;
wire [3:0]S;
LUT4 #(
.INIT(16'h3E0E))
\Q[3]_i_10
(.I0(\Q_reg[30] [0]),
.I1(FSM_selector_B[1]),
.I2(FSM_selector_B[0]),
.I3(\Q_reg[0]_0 ),
.O(\Q_reg[3] [0]));
LUT4 #(
.INIT(16'h56A6))
\Q[3]_i_7
(.I0(\Q_reg[26] [2]),
.I1(\Q_reg[30]_0 [2]),
.I2(\Q_reg[0] ),
.I3(Q[2]),
.O(\Q_reg[3] [3]));
LUT4 #(
.INIT(16'h56A6))
\Q[3]_i_8
(.I0(\Q_reg[26] [1]),
.I1(\Q_reg[30]_0 [1]),
.I2(\Q_reg[0] ),
.I3(Q[1]),
.O(\Q_reg[3] [2]));
LUT4 #(
.INIT(16'h56A6))
\Q[3]_i_9
(.I0(\Q_reg[26] [0]),
.I1(\Q_reg[30]_0 [0]),
.I2(\Q_reg[0] ),
.I3(Q[0]),
.O(\Q_reg[3] [1]));
LUT4 #(
.INIT(16'h56A6))
\Q[7]_i_10
(.I0(DI),
.I1(\Q_reg[30]_0 [3]),
.I2(\Q_reg[0] ),
.I3(Q[3]),
.O(S[0]));
LUT6 #(
.INIT(64'h2D2D2DD2D2D22DD2))
\Q[7]_i_7
(.I0(\Q_reg[30] [3]),
.I1(\Q_reg[1] ),
.I2(FSM_exp_operation_A_S),
.I3(\Q_reg[30]_0 [6]),
.I4(\Q_reg[0] ),
.I5(Q[6]),
.O(S[3]));
LUT6 #(
.INIT(64'h2D2D2DD2D2D22DD2))
\Q[7]_i_8
(.I0(\Q_reg[30] [2]),
.I1(\Q_reg[1] ),
.I2(FSM_exp_operation_A_S),
.I3(\Q_reg[30]_0 [5]),
.I4(\Q_reg[0] ),
.I5(Q[5]),
.O(S[2]));
LUT6 #(
.INIT(64'h2D2D2DD2D2D22DD2))
\Q[7]_i_9
(.I0(\Q_reg[30] [1]),
.I1(\Q_reg[1] ),
.I2(FSM_exp_operation_A_S),
.I3(\Q_reg[30]_0 [4]),
.I4(\Q_reg[0] ),
.I5(Q[4]),
.O(S[1]));
endmodule
(* ORIG_REF_NAME = "add_sub_carry_out" *)
module add_sub_carry_out__parameterized0
(S,
\Q_reg[7] ,
\Q_reg[11] ,
\Q_reg[15] ,
\Q_reg[19] ,
\Q_reg[23] ,
\Q_reg[0] ,
\Q_reg[31] ,
intAS,
\Q_reg[31]_0 ,
\Q_reg[25] ,
FSM_selector_D,
\Q_reg[22] );
output [3:0]S;
output [3:0]\Q_reg[7] ;
output [3:0]\Q_reg[11] ;
output [3:0]\Q_reg[15] ;
output [3:0]\Q_reg[19] ;
output [3:0]\Q_reg[23] ;
output [1:0]\Q_reg[0] ;
input [0:0]\Q_reg[31] ;
input intAS;
input [0:0]\Q_reg[31]_0 ;
input [25:0]\Q_reg[25] ;
input FSM_selector_D;
input [22:0]\Q_reg[22] ;
wire FSM_selector_D;
wire [1:0]\Q_reg[0] ;
wire [3:0]\Q_reg[11] ;
wire [3:0]\Q_reg[15] ;
wire [3:0]\Q_reg[19] ;
wire [22:0]\Q_reg[22] ;
wire [3:0]\Q_reg[23] ;
wire [25:0]\Q_reg[25] ;
wire [0:0]\Q_reg[31] ;
wire [0:0]\Q_reg[31]_0 ;
wire [3:0]\Q_reg[7] ;
wire [3:0]S;
wire intAS;
LUT5 #(
.INIT(32'hFF960069))
\Q[0]_i_6
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(FSM_selector_D),
.I4(\Q_reg[25] [25]),
.O(\Q_reg[0] [1]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[0]_i_7
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [22]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [24]),
.O(\Q_reg[0] [0]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[11]_i_6
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [9]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [11]),
.O(\Q_reg[11] [3]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[11]_i_7
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [8]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [10]),
.O(\Q_reg[11] [2]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[11]_i_8
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [7]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [9]),
.O(\Q_reg[11] [1]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[11]_i_9
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [6]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [8]),
.O(\Q_reg[11] [0]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[15]_i_6
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [13]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [15]),
.O(\Q_reg[15] [3]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[15]_i_7
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [12]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [14]),
.O(\Q_reg[15] [2]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[15]_i_8
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [11]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [13]),
.O(\Q_reg[15] [1]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[15]_i_9
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [10]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [12]),
.O(\Q_reg[15] [0]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[19]_i_6
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [17]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [19]),
.O(\Q_reg[19] [3]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[19]_i_7
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [16]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [18]),
.O(\Q_reg[19] [2]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[19]_i_8
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [15]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [17]),
.O(\Q_reg[19] [1]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[19]_i_9
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [14]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [16]),
.O(\Q_reg[19] [0]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[23]_i_6
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [21]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [23]),
.O(\Q_reg[23] [3]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[23]_i_7
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [20]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [22]),
.O(\Q_reg[23] [2]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[23]_i_8
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [19]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [21]),
.O(\Q_reg[23] [1]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[23]_i_9
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [18]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [20]),
.O(\Q_reg[23] [0]));
LUT2 #(
.INIT(4'h2))
\Q[3]_i_10
(.I0(\Q_reg[25] [0]),
.I1(FSM_selector_D),
.O(S[0]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[3]_i_7
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [1]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [3]),
.O(S[3]));
LUT6 #(
.INIT(64'h00009669FFFF6996))
\Q[3]_i_8
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [0]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [2]),
.O(S[2]));
LUT5 #(
.INIT(32'hFF006996))
\Q[3]_i_9
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[25] [1]),
.I4(FSM_selector_D),
.O(S[1]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[7]_i_6
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [5]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [7]),
.O(\Q_reg[7] [3]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[7]_i_7
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [4]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [6]),
.O(\Q_reg[7] [2]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[7]_i_8
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [3]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [5]),
.O(\Q_reg[7] [1]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[7]_i_9
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [2]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [4]),
.O(\Q_reg[7] [0]));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2018 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2018.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Static Dual Port Synchronous RAM 32-Deep by 1-Wide
// /___/ /\ Filename : RAMD32.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 07/02/10 - Initial version.
// 12/13/11 - 524859 - Added `celldefine and `endcelldefine.
// 04/16/13 - 683925 - Add invertible pin support.
// 10/22/14 - 808642 - Added #1 to $finish.
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module RAMD32 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [31:0] INIT = 32'h00000000,
parameter [0:0] IS_CLK_INVERTED = 1'b0
)(
output O,
input CLK,
input I,
input RADR0,
input RADR1,
input RADR2,
input RADR3,
input RADR4,
input WADR0,
input WADR1,
input WADR2,
input WADR3,
input WADR4,
input WE
);
// define constants
localparam MODULE_NAME = "RAMD32";
reg trig_attr;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "RAMD32_dr.v"
`else
reg [31:0] INIT_REG = INIT;
reg [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED;
`endif
`ifdef XIL_XECLIB
reg glblGSR = 1'b0;
`else
tri0 glblGSR = glbl.GSR;
`endif
wire CLK_in;
wire I_in;
wire RADR0_in;
wire RADR1_in;
wire RADR2_in;
wire RADR3_in;
wire RADR4_in;
wire WADR0_in;
wire WADR1_in;
wire WADR2_in;
wire WADR3_in;
wire WADR4_in;
wire WE_in;
`ifdef XIL_TIMING
wire CLK_delay;
wire I_delay;
wire WADR0_delay;
wire WADR1_delay;
wire WADR2_delay;
wire WADR3_delay;
wire WADR4_delay;
wire WE_delay;
`endif
`ifdef XIL_TIMING
assign CLK_in = CLK_delay ^ IS_CLK_INVERTED_REG;
assign I_in = I_delay;
assign WADR0_in = WADR0_delay;
assign WADR1_in = WADR1_delay;
assign WADR2_in = WADR2_delay;
assign WADR3_in = WADR3_delay;
assign WADR4_in = WADR4_delay;
assign WE_in = (WE === 1'bz) || WE_delay; // rv 1
`else
assign CLK_in = CLK ^ IS_CLK_INVERTED_REG;
assign I_in = I;
assign WADR0_in = WADR0;
assign WADR1_in = WADR1;
assign WADR2_in = WADR2;
assign WADR3_in = WADR3;
assign WADR4_in = WADR4;
assign WE_in = (WE === 1'bz) || WE; // rv 1
`endif
assign RADR0_in = RADR0;
assign RADR1_in = RADR1;
assign RADR2_in = RADR2;
assign RADR3_in = RADR3;
assign RADR4_in = RADR4;
`ifndef XIL_XECLIB
initial begin
trig_attr = 1'b0;
#1;
trig_attr = ~trig_attr;
end
`endif
`ifndef XIL_TIMING
initial begin
$display("Error: [Unisim %s-100] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME);
#1 $finish;
end
`endif
`ifdef XIL_TIMING
reg notifier;
`endif
// begin behavioral model
reg [31:0] mem;
reg O_out;
assign O = O_out;
`ifndef XIL_XECLIB
initial begin
mem = INIT;
O_out = mem[{RADR4_in,RADR3_in,RADR2_in,RADR1_in,RADR0_in}];
end
`endif
always @(posedge CLK_in)
if (WE_in == 1'b1) begin
mem[{WADR4_in,WADR3_in,WADR2_in,WADR1_in,WADR0_in}] = I_in;
end
always @ (*) begin
O_out = mem[{RADR4_in,RADR3_in,RADR2_in,RADR1_in,RADR0_in}];
end
`ifdef XIL_TIMING
always @(notifier) mem[{WADR4_in,WADR3_in,WADR2_in,WADR1_in,WADR0_in}] = 1'bx;
`endif
// end behavioral model
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
wire clk_en_n;
wire clk_en_p;
assign clk_en_n = IS_CLK_INVERTED_REG;
assign clk_en_p = ~IS_CLK_INVERTED_REG;
assign we_clk_en_n = WE_in && IS_CLK_INVERTED_REG;
assign we_clk_en_p = WE_in && ~IS_CLK_INVERTED_REG;
`endif
specify
(CLK => O) = (100:100:100, 100:100:100);
(I => O) = (0:0:0, 0:0:0);
(RADR0 => O) = (0:0:0, 0:0:0);
(RADR1 => O) = (0:0:0, 0:0:0);
(RADR2 => O) = (0:0:0, 0:0:0);
(RADR3 => O) = (0:0:0, 0:0:0);
(RADR4 => O) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
$period (negedge CLK &&& WE, 0:0:0, notifier);
$period (posedge CLK &&& WE, 0:0:0, notifier);
$setuphold (negedge CLK, negedge I, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, I_delay);
$setuphold (negedge CLK, negedge WADR0, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR0_delay);
$setuphold (negedge CLK, negedge WADR1, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR1_delay);
$setuphold (negedge CLK, negedge WADR2, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR2_delay);
$setuphold (negedge CLK, negedge WADR3, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR3_delay);
$setuphold (negedge CLK, negedge WADR4, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR4_delay);
$setuphold (negedge CLK, negedge WE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, WE_delay);
$setuphold (negedge CLK, posedge I, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, I_delay);
$setuphold (negedge CLK, posedge WADR0, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR0_delay);
$setuphold (negedge CLK, posedge WADR1, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR1_delay);
$setuphold (negedge CLK, posedge WADR2, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR2_delay);
$setuphold (negedge CLK, posedge WADR3, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR3_delay);
$setuphold (negedge CLK, posedge WADR4, 0:0:0, 0:0:0, notifier, we_clk_en_n, we_clk_en_n, CLK_delay, WADR4_delay);
$setuphold (negedge CLK, posedge WE, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, WE_delay);
$setuphold (posedge CLK, negedge I, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, I_delay);
$setuphold (posedge CLK, negedge WADR0, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR0_delay);
$setuphold (posedge CLK, negedge WADR1, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR1_delay);
$setuphold (posedge CLK, negedge WADR2, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR2_delay);
$setuphold (posedge CLK, negedge WADR3, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR3_delay);
$setuphold (posedge CLK, negedge WADR4, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR4_delay);
$setuphold (posedge CLK, negedge WE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, WE_delay);
$setuphold (posedge CLK, posedge I, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, I_delay);
$setuphold (posedge CLK, posedge WADR0, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR0_delay);
$setuphold (posedge CLK, posedge WADR1, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR1_delay);
$setuphold (posedge CLK, posedge WADR2, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR2_delay);
$setuphold (posedge CLK, posedge WADR3, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR3_delay);
$setuphold (posedge CLK, posedge WADR4, 0:0:0, 0:0:0, notifier, we_clk_en_p, we_clk_en_p, CLK_delay, WADR4_delay);
$setuphold (posedge CLK, posedge WE, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, WE_delay);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : xilinx_pcie_2_1_ep_7x.v
// Version : 1.3
//--
//-- Description: PCI Express Endpoint example FPGA design
//--
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
module xilinx_pcie_2_1_ep_7x # (
parameter PL_FAST_TRAIN = "FALSE", // Simulation Speedup
parameter PCIE_EXT_CLK = "TRUE", // Use External Clocking Module
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // TSTRB width
) (
output [3:0] pci_exp_txp,
output [3:0] pci_exp_txn,
input [3:0] pci_exp_rxp,
input [3:0] pci_exp_rxn,
output led_0,
output led_1,
output led_2,
output led_3,
input sys_clk_p,
input sys_clk_n,
input sys_rst_n
);
localparam TCQ = 1;
reg [25:0] user_clk_heartbeat;
wire user_clk;
wire user_reset;
wire user_lnk_up;
// Tx
wire [5:0] tx_buf_av;
wire tx_cfg_req;
wire tx_err_drop;
wire tx_cfg_gnt;
wire s_axis_tx_tready;
wire [3:0] s_axis_tx_tuser;
wire [C_DATA_WIDTH-1:0] s_axis_tx_tdata;
wire [KEEP_WIDTH-1:0] s_axis_tx_tkeep;
wire s_axis_tx_tlast;
wire s_axis_tx_tvalid;
// Rx
wire [C_DATA_WIDTH-1:0] m_axis_rx_tdata;
wire [KEEP_WIDTH-1:0] m_axis_rx_tkeep;
wire m_axis_rx_tlast;
wire m_axis_rx_tvalid;
wire m_axis_rx_tready;
wire [21:0] m_axis_rx_tuser;
wire rx_np_ok;
wire rx_np_req;
// Flow Control
wire [11:0] fc_cpld;
wire [7:0] fc_cplh;
wire [11:0] fc_npd;
wire [7:0] fc_nph;
wire [11:0] fc_pd;
wire [7:0] fc_ph;
wire [2:0] fc_sel;
//-------------------------------------------------------
// 3. Configuration (CFG) Interface
//-------------------------------------------------------
wire cfg_err_cor;
wire cfg_err_ur;
wire cfg_err_ecrc;
wire cfg_err_cpl_timeout;
wire cfg_err_cpl_abort;
wire cfg_err_cpl_unexpect;
wire cfg_err_posted;
wire cfg_err_locked;
wire [47:0] cfg_err_tlp_cpl_header;
wire cfg_err_cpl_rdy;
wire cfg_interrupt;
wire cfg_interrupt_rdy;
wire cfg_interrupt_assert;
wire [7:0] cfg_interrupt_di;
wire [7:0] cfg_interrupt_do;
wire [2:0] cfg_interrupt_mmenable;
wire cfg_interrupt_msienable;
wire cfg_interrupt_msixenable;
wire cfg_interrupt_msixfm;
wire cfg_interrupt_stat;
wire [4:0] cfg_pciecap_interrupt_msgnum;
wire cfg_turnoff_ok;
wire cfg_to_turnoff;
wire cfg_trn_pending;
wire cfg_pm_halt_aspm_l0s;
wire cfg_pm_halt_aspm_l1;
wire cfg_pm_force_state_en;
wire [1:0] cfg_pm_force_state;
wire cfg_pm_wake;
wire [7:0] cfg_bus_number;
wire [4:0] cfg_device_number;
wire [2:0] cfg_function_number;
wire [15:0] cfg_status;
wire [15:0] cfg_command;
wire [15:0] cfg_dstatus;
wire [15:0] cfg_dcommand;
wire [15:0] cfg_lstatus;
wire [15:0] cfg_lcommand;
wire [15:0] cfg_dcommand2;
wire [2:0] cfg_pcie_link_state;
wire [63:0] cfg_dsn;
wire [127:0] cfg_err_aer_headerlog;
wire [4:0] cfg_aer_interrupt_msgnum;
wire cfg_err_aer_headerlog_set;
wire cfg_aer_ecrc_check_en;
wire cfg_aer_ecrc_gen_en;
wire [31:0] cfg_mgmt_di;
wire [3:0] cfg_mgmt_byte_en;
wire [9:0] cfg_mgmt_dwaddr;
wire cfg_mgmt_wr_en;
wire cfg_mgmt_rd_en;
wire cfg_mgmt_wr_readonly;
//-------------------------------------------------------
// 4. Physical Layer Control and Status (PL) Interface
//-------------------------------------------------------
wire [2:0] pl_initial_link_width;
wire [1:0] pl_lane_reversal_mode;
wire pl_link_gen2_cap;
wire pl_link_partner_gen2_supported;
wire pl_link_upcfg_cap;
wire [5:0] pl_ltssm_state;
wire pl_received_hot_rst;
wire pl_sel_lnk_rate;
wire [1:0] pl_sel_lnk_width;
wire pl_directed_link_auton;
wire [1:0] pl_directed_link_change;
wire pl_directed_link_speed;
wire [1:0] pl_directed_link_width;
wire pl_upstream_prefer_deemph;
wire sys_rst_n_c;
// Wires used for external clocking connectivity
wire PIPE_PCLK_IN;
wire [3:0] PIPE_RXUSRCLK_IN;
wire PIPE_RXOUTCLK_IN;
wire PIPE_DCLK_IN;
wire PIPE_USERCLK1_IN;
wire PIPE_USERCLK2_IN;
wire PIPE_MMCM_LOCK_IN;
wire PIPE_TXOUTCLK_OUT;
wire [3:0] PIPE_RXOUTCLK_OUT;
wire [3:0] PIPE_PCLK_SEL_OUT;
wire PIPE_GEN3_OUT;
localparam USER_CLK_FREQ = 3;
localparam USER_CLK2_DIV2 = "TRUE";
localparam USERCLK2_FREQ = (USER_CLK2_DIV2 == "TRUE") ? (USER_CLK_FREQ == 4) ? 3 : (USER_CLK_FREQ == 3) ? 2 : USER_CLK_FREQ
: USER_CLK_FREQ;
//-------------------------------------------------------
IBUF sys_reset_n_ibuf (.O(sys_rst_n_c), .I(sys_rst_n));
`ifdef SIMULATION
IBUFDS_GTE2 refclk_ibuf (.O(sys_clk), .ODIV2(), .I(sys_clk_p), .CEB(1'b0), .IB(sys_clk_n));
`else
IBUFDS_GTE2 refclk_ibuf (.O(sys_clk), .ODIV2(), .I(sys_clk_p), .IB(sys_clk_n));
`endif
OBUF led_0_obuf (.O(led_0), .I(sys_rst_n_c));
OBUF led_1_obuf (.O(led_1), .I(!user_reset));
OBUF led_2_obuf (.O(led_2), .I(user_lnk_up));
OBUF led_3_obuf (.O(led_3), .I(user_clk_heartbeat[25]));
reg user_reset_q;
reg user_lnk_up_q;
always @(posedge user_clk) begin
user_reset_q <= user_reset;
user_lnk_up_q <= user_lnk_up;
end
// Create a Clock Heartbeat on LED #3
always @(posedge user_clk) begin
if(!sys_rst_n_c) begin
user_clk_heartbeat <= #TCQ 26'd0;
end else begin
user_clk_heartbeat <= #TCQ user_clk_heartbeat + 1'b1;
end
end
// Generate External Clock Module if External Clocking is selected
generate
if (PCIE_EXT_CLK == "TRUE") begin : ext_clk
//---------- PIPE Clock Module -------------------------------------------------
pcie_7x_v1_3_pipe_clock #
(
.PCIE_ASYNC_EN ( "FALSE" ), // PCIe async enable
.PCIE_TXBUF_EN ( "FALSE" ), // PCIe TX buffer enable for Gen1/Gen2 only
.PCIE_LANE ( 6'h04 ), // PCIe number of lanes
`ifdef SIMULATION // PCIe Link Speed
.PCIE_LINK_SPEED ( 2 ),
`else
.PCIE_LINK_SPEED ( 3 ),
`endif
.PCIE_REFCLK_FREQ ( 0 ), // PCIe reference clock frequency
.PCIE_USERCLK1_FREQ ( USER_CLK_FREQ +1 ), // PCIe user clock 1 frequency
.PCIE_USERCLK2_FREQ ( USERCLK2_FREQ +1 ), // PCIe user clock 2 frequency
.PCIE_DEBUG_MODE ( 0 )
)
pipe_clock_i
(
//---------- Input -------------------------------------
.CLK_CLK ( sys_clk ),
.CLK_TXOUTCLK ( PIPE_TXOUTCLK_OUT ), // Reference clock from lane 0
.CLK_RXOUTCLK_IN ( PIPE_RXOUTCLK_OUT ),
.CLK_RST_N ( 1'b1 ),
.CLK_PCLK_SEL ( PIPE_PCLK_SEL_OUT ),
.CLK_GEN3 ( PIPE_GEN3_OUT ),
//---------- Output ------------------------------------
.CLK_PCLK ( PIPE_PCLK_IN ),
.CLK_RXUSRCLK ( PIPE_RXUSRCLK_IN ),
.CLK_RXOUTCLK_OUT ( PIPE_RXOUTCLK_IN ),
.CLK_DCLK ( PIPE_DCLK_IN ),
.CLK_USERCLK1 ( PIPE_USERCLK1_IN ),
.CLK_USERCLK2 ( PIPE_USERCLK2_IN ),
.CLK_MMCM_LOCK ( PIPE_MMCM_LOCK_IN )
);
end
endgenerate
pcie_7x_v1_3 #(
.PL_FAST_TRAIN ( PL_FAST_TRAIN ),
.PCIE_EXT_CLK ( PCIE_EXT_CLK )
) pcie_7x_v1_3_i
(
//----------------------------------------------------------------------------------------------------------------//
// 1. PCI Express (pci_exp) Interface //
//----------------------------------------------------------------------------------------------------------------//
// Tx
.pci_exp_txn ( pci_exp_txn ),
.pci_exp_txp ( pci_exp_txp ),
// Rx
.pci_exp_rxn ( pci_exp_rxn ),
.pci_exp_rxp ( pci_exp_rxp ),
//----------------------------------------------------------------------------------------------------------------//
// 2. Clocking Interface //
//----------------------------------------------------------------------------------------------------------------//
.PIPE_PCLK_IN ( PIPE_PCLK_IN ),
.PIPE_RXUSRCLK_IN ( PIPE_RXUSRCLK_IN ),
.PIPE_RXOUTCLK_IN ( PIPE_RXOUTCLK_IN ),
.PIPE_DCLK_IN ( PIPE_DCLK_IN ),
.PIPE_USERCLK1_IN ( PIPE_USERCLK1_IN ),
.PIPE_OOBCLK_IN ( 1'b0 ),
.PIPE_USERCLK2_IN ( PIPE_USERCLK2_IN ),
.PIPE_MMCM_LOCK_IN ( PIPE_MMCM_LOCK_IN ),
.PIPE_TXOUTCLK_OUT ( PIPE_TXOUTCLK_OUT ),
.PIPE_RXOUTCLK_OUT ( PIPE_RXOUTCLK_OUT ),
.PIPE_PCLK_SEL_OUT ( PIPE_PCLK_SEL_OUT ),
.PIPE_GEN3_OUT ( PIPE_GEN3_OUT ),
//----------------------------------------------------------------------------------------------------------------//
// 3. AXI-S Interface //
//----------------------------------------------------------------------------------------------------------------//
// Common
.user_clk_out ( user_clk ),
.user_reset_out ( user_reset ),
.user_lnk_up ( user_lnk_up ),
// TX
.tx_buf_av ( tx_buf_av ),
.tx_err_drop ( tx_err_drop ),
.tx_cfg_req ( tx_cfg_req ),
.s_axis_tx_tready ( s_axis_tx_tready ),
.s_axis_tx_tdata ( s_axis_tx_tdata ),
.s_axis_tx_tkeep ( s_axis_tx_tkeep ),
.s_axis_tx_tuser ( s_axis_tx_tuser ),
.s_axis_tx_tlast ( s_axis_tx_tlast ),
.s_axis_tx_tvalid ( s_axis_tx_tvalid ),
.tx_cfg_gnt ( tx_cfg_gnt ),
// Rx
.m_axis_rx_tdata ( m_axis_rx_tdata ),
.m_axis_rx_tkeep ( m_axis_rx_tkeep ),
.m_axis_rx_tlast ( m_axis_rx_tlast ),
.m_axis_rx_tvalid ( m_axis_rx_tvalid ),
.m_axis_rx_tready ( m_axis_rx_tready ),
.m_axis_rx_tuser ( m_axis_rx_tuser ),
.rx_np_ok ( rx_np_ok ),
.rx_np_req ( rx_np_req ),
// Flow Control
.fc_cpld ( fc_cpld ),
.fc_cplh ( fc_cplh ),
.fc_npd ( fc_npd ),
.fc_nph ( fc_nph ),
.fc_pd ( fc_pd ),
.fc_ph ( fc_ph ),
.fc_sel ( fc_sel ),
//----------------------------------------------------------------------------------------------------------------//
// 4. Configuration (CFG) Interface //
//----------------------------------------------------------------------------------------------------------------//
//------------------------------------------------//
// EP and RP //
//------------------------------------------------//
.cfg_mgmt_do ( ),
.cfg_mgmt_rd_wr_done ( ),
.cfg_status ( cfg_status ),
.cfg_command ( cfg_command ),
.cfg_dstatus ( cfg_dstatus ),
.cfg_dcommand ( cfg_dcommand ),
.cfg_lstatus ( cfg_lstatus ),
.cfg_lcommand ( cfg_lcommand ),
.cfg_dcommand2 ( cfg_dcommand2 ),
.cfg_pcie_link_state ( cfg_pcie_link_state ),
.cfg_pmcsr_pme_en ( ),
.cfg_pmcsr_powerstate ( ),
.cfg_pmcsr_pme_status ( ),
.cfg_received_func_lvl_rst ( ),
// Management Interface
.cfg_mgmt_di ( cfg_mgmt_di ),
.cfg_mgmt_byte_en ( cfg_mgmt_byte_en ),
.cfg_mgmt_dwaddr ( cfg_mgmt_dwaddr ),
.cfg_mgmt_wr_en ( cfg_mgmt_wr_en ),
.cfg_mgmt_rd_en ( cfg_mgmt_rd_en ),
.cfg_mgmt_wr_readonly ( cfg_mgmt_wr_readonly ),
// Error Reporting Interface
.cfg_err_ecrc ( cfg_err_ecrc ),
.cfg_err_ur ( cfg_err_ur ),
.cfg_err_cpl_timeout ( cfg_err_cpl_timeout ),
.cfg_err_cpl_unexpect ( cfg_err_cpl_unexpect ),
.cfg_err_cpl_abort ( cfg_err_cpl_abort ),
.cfg_err_posted ( cfg_err_posted ),
.cfg_err_cor ( cfg_err_cor ),
.cfg_err_atomic_egress_blocked ( cfg_err_atomic_egress_blocked ),
.cfg_err_internal_cor ( cfg_err_internal_cor ),
.cfg_err_malformed ( cfg_err_malformed ),
.cfg_err_mc_blocked ( cfg_err_mc_blocked ),
.cfg_err_poisoned ( cfg_err_poisoned ),
.cfg_err_norecovery ( cfg_err_norecovery ),
.cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ),
.cfg_err_cpl_rdy ( cfg_err_cpl_rdy ),
.cfg_err_locked ( cfg_err_locked ),
.cfg_err_acs ( cfg_err_acs ),
.cfg_err_internal_uncor ( cfg_err_internal_uncor ),
.cfg_trn_pending ( cfg_trn_pending ),
.cfg_pm_halt_aspm_l0s ( cfg_pm_halt_aspm_l0s ),
.cfg_pm_halt_aspm_l1 ( cfg_pm_halt_aspm_l1 ),
.cfg_pm_force_state_en ( cfg_pm_force_state_en ),
.cfg_pm_force_state ( cfg_pm_force_state ),
.cfg_dsn ( cfg_dsn ),
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
.cfg_interrupt ( cfg_interrupt ),
.cfg_interrupt_rdy ( cfg_interrupt_rdy ),
.cfg_interrupt_assert ( cfg_interrupt_assert ),
.cfg_interrupt_di ( cfg_interrupt_di ),
.cfg_interrupt_do ( cfg_interrupt_do ),
.cfg_interrupt_mmenable ( cfg_interrupt_mmenable ),
.cfg_interrupt_msienable ( cfg_interrupt_msienable ),
.cfg_interrupt_msixenable ( cfg_interrupt_msixenable ),
.cfg_interrupt_msixfm ( cfg_interrupt_msixfm ),
.cfg_interrupt_stat ( cfg_interrupt_stat ),
.cfg_pciecap_interrupt_msgnum ( cfg_pciecap_interrupt_msgnum ),
.cfg_to_turnoff ( cfg_to_turnoff ),
.cfg_turnoff_ok ( cfg_turnoff_ok ),
.cfg_bus_number ( cfg_bus_number ),
.cfg_device_number ( cfg_device_number ),
.cfg_function_number ( cfg_function_number ),
.cfg_pm_wake ( cfg_pm_wake ),
//------------------------------------------------//
// RP Only //
//------------------------------------------------//
.cfg_pm_send_pme_to ( 1'b0 ),
.cfg_ds_bus_number ( 8'b0 ),
.cfg_ds_device_number ( 5'b0 ),
.cfg_ds_function_number ( 3'b0 ),
.cfg_mgmt_wr_rw1c_as_rw ( 1'b0 ),
.cfg_msg_received ( ),
.cfg_msg_data ( ),
.cfg_bridge_serr_en ( ),
.cfg_slot_control_electromech_il_ctl_pulse ( ),
.cfg_root_control_syserr_corr_err_en ( ),
.cfg_root_control_syserr_non_fatal_err_en ( ),
.cfg_root_control_syserr_fatal_err_en ( ),
.cfg_root_control_pme_int_en ( ),
.cfg_aer_rooterr_corr_err_reporting_en ( ),
.cfg_aer_rooterr_non_fatal_err_reporting_en ( ),
.cfg_aer_rooterr_fatal_err_reporting_en ( ),
.cfg_aer_rooterr_corr_err_received ( ),
.cfg_aer_rooterr_non_fatal_err_received ( ),
.cfg_aer_rooterr_fatal_err_received ( ),
.cfg_msg_received_err_cor ( ),
.cfg_msg_received_err_non_fatal ( ),
.cfg_msg_received_err_fatal ( ),
.cfg_msg_received_pm_as_nak ( ),
.cfg_msg_received_pme_to_ack ( ),
.cfg_msg_received_assert_int_a ( ),
.cfg_msg_received_assert_int_b ( ),
.cfg_msg_received_assert_int_c ( ),
.cfg_msg_received_assert_int_d ( ),
.cfg_msg_received_deassert_int_a ( ),
.cfg_msg_received_deassert_int_b ( ),
.cfg_msg_received_deassert_int_c ( ),
.cfg_msg_received_deassert_int_d ( ),
//----------------------------------------------------------------------------------------------------------------//
// 5. Physical Layer Control and Status (PL) Interface //
//----------------------------------------------------------------------------------------------------------------//
.pl_directed_link_change ( pl_directed_link_change ),
.pl_directed_link_width ( pl_directed_link_width ),
.pl_directed_link_speed ( pl_directed_link_speed ),
.pl_directed_link_auton ( pl_directed_link_auton ),
.pl_upstream_prefer_deemph ( pl_upstream_prefer_deemph ),
.pl_sel_lnk_rate ( pl_sel_lnk_rate ),
.pl_sel_lnk_width ( pl_sel_lnk_width ),
.pl_ltssm_state ( pl_ltssm_state ),
.pl_lane_reversal_mode ( pl_lane_reversal_mode ),
.pl_phy_lnk_up ( ),
.pl_tx_pm_state ( ),
.pl_rx_pm_state ( ),
.pl_link_upcfg_cap ( pl_link_upcfg_cap ),
.pl_link_gen2_cap ( pl_link_gen2_cap ),
.pl_link_partner_gen2_supported ( pl_link_partner_gen2_supported ),
.pl_initial_link_width ( pl_initial_link_width ),
.pl_directed_change_done ( ),
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
.pl_received_hot_rst ( pl_received_hot_rst ),
//------------------------------------------------//
// RP Only //
//------------------------------------------------//
.pl_transmit_hot_rst ( 1'b0 ),
.pl_downstream_deemph_source ( 1'b0 ),
//----------------------------------------------------------------------------------------------------------------//
// 6. AER Interface //
//----------------------------------------------------------------------------------------------------------------//
.cfg_err_aer_headerlog ( cfg_err_aer_headerlog ),
.cfg_aer_interrupt_msgnum ( cfg_aer_interrupt_msgnum ),
.cfg_err_aer_headerlog_set ( cfg_err_aer_headerlog_set ),
.cfg_aer_ecrc_check_en ( cfg_aer_ecrc_check_en ),
.cfg_aer_ecrc_gen_en ( cfg_aer_ecrc_gen_en ),
//----------------------------------------------------------------------------------------------------------------//
// 7. VC interface //
//----------------------------------------------------------------------------------------------------------------//
.cfg_vc_tcvc_map ( ),
//----------------------------------------------------------------------------------------------------------------//
// 8. System (SYS) Interface //
//----------------------------------------------------------------------------------------------------------------//
.sys_clk ( sys_clk ),
.sys_reset ( ~sys_rst_n_c )
);
pcie_app_7x #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.TCQ( TCQ )
)app (
//----------------------------------------------------------------------------------------------------------------//
// 1. AXI-S Interface //
//----------------------------------------------------------------------------------------------------------------//
// Common
.user_clk ( user_clk ),
.user_reset ( user_reset_q ),
.user_lnk_up ( user_lnk_up_q ),
// Tx
.tx_buf_av ( tx_buf_av ),
.tx_cfg_req ( tx_cfg_req ),
.tx_err_drop ( tx_err_drop ),
.s_axis_tx_tready ( s_axis_tx_tready ),
.s_axis_tx_tdata ( s_axis_tx_tdata ),
.s_axis_tx_tkeep ( s_axis_tx_tkeep ),
.s_axis_tx_tuser ( s_axis_tx_tuser ),
.s_axis_tx_tlast ( s_axis_tx_tlast ),
.s_axis_tx_tvalid ( s_axis_tx_tvalid ),
.tx_cfg_gnt ( tx_cfg_gnt ),
// Rx
.m_axis_rx_tdata ( m_axis_rx_tdata ),
.m_axis_rx_tkeep ( m_axis_rx_tkeep ),
.m_axis_rx_tlast ( m_axis_rx_tlast ),
.m_axis_rx_tvalid ( m_axis_rx_tvalid ),
.m_axis_rx_tready ( m_axis_rx_tready ),
.m_axis_rx_tuser ( m_axis_rx_tuser ),
.rx_np_ok ( rx_np_ok ),
.rx_np_req ( rx_np_req ),
// Flow Control
.fc_cpld ( fc_cpld ),
.fc_cplh ( fc_cplh ),
.fc_npd ( fc_npd ),
.fc_nph ( fc_nph ),
.fc_pd ( fc_pd ),
.fc_ph ( fc_ph ),
.fc_sel ( fc_sel ),
//----------------------------------------------------------------------------------------------------------------//
// 2. Configuration (CFG) Interface //
//----------------------------------------------------------------------------------------------------------------//
.cfg_err_cor ( cfg_err_cor ),
.cfg_err_atomic_egress_blocked ( cfg_err_atomic_egress_blocked ),
.cfg_err_internal_cor ( cfg_err_internal_cor ),
.cfg_err_malformed ( cfg_err_malformed ),
.cfg_err_mc_blocked ( cfg_err_mc_blocked ),
.cfg_err_poisoned ( cfg_err_poisoned ),
.cfg_err_norecovery ( cfg_err_norecovery ),
.cfg_err_ur ( cfg_err_ur ),
.cfg_err_ecrc ( cfg_err_ecrc ),
.cfg_err_cpl_timeout ( cfg_err_cpl_timeout ),
.cfg_err_cpl_abort ( cfg_err_cpl_abort ),
.cfg_err_cpl_unexpect ( cfg_err_cpl_unexpect ),
.cfg_err_posted ( cfg_err_posted ),
.cfg_err_locked ( cfg_err_locked ),
.cfg_err_acs ( cfg_err_acs ), //1'b0 ),
.cfg_err_internal_uncor ( cfg_err_internal_uncor ), //1'b0 ),
.cfg_err_tlp_cpl_header ( cfg_err_tlp_cpl_header ),
.cfg_err_cpl_rdy ( cfg_err_cpl_rdy ),
.cfg_interrupt ( cfg_interrupt ),
.cfg_interrupt_rdy ( cfg_interrupt_rdy ),
.cfg_interrupt_assert ( cfg_interrupt_assert ),
.cfg_interrupt_di ( cfg_interrupt_di ),
.cfg_interrupt_do ( cfg_interrupt_do ),
.cfg_interrupt_mmenable ( cfg_interrupt_mmenable ),
.cfg_interrupt_msienable ( cfg_interrupt_msienable ),
.cfg_interrupt_msixenable ( cfg_interrupt_msixenable ),
.cfg_interrupt_msixfm ( cfg_interrupt_msixfm ),
.cfg_interrupt_stat ( cfg_interrupt_stat ),
.cfg_pciecap_interrupt_msgnum ( cfg_pciecap_interrupt_msgnum ),
.cfg_turnoff_ok ( cfg_turnoff_ok ),
.cfg_to_turnoff ( cfg_to_turnoff ),
.cfg_trn_pending ( cfg_trn_pending ),
.cfg_pm_halt_aspm_l0s ( cfg_pm_halt_aspm_l0s ),
.cfg_pm_halt_aspm_l1 ( cfg_pm_halt_aspm_l1 ),
.cfg_pm_force_state_en ( cfg_pm_force_state_en ),
.cfg_pm_force_state ( cfg_pm_force_state ),
.cfg_pm_wake ( cfg_pm_wake ),
.cfg_bus_number ( cfg_bus_number ),
.cfg_device_number ( cfg_device_number ),
.cfg_function_number ( cfg_function_number ),
.cfg_status ( cfg_status ),
.cfg_command ( cfg_command ),
.cfg_dstatus ( cfg_dstatus ),
.cfg_dcommand ( cfg_dcommand ),
.cfg_lstatus ( cfg_lstatus ),
.cfg_lcommand ( cfg_lcommand ),
.cfg_dcommand2 ( cfg_dcommand2 ),
.cfg_pcie_link_state ( cfg_pcie_link_state ),
.cfg_dsn ( cfg_dsn ),
//----------------------------------------------------------------------------------------------------------------//
// 3. Management (MGMT) Interface //
//----------------------------------------------------------------------------------------------------------------//
.cfg_mgmt_di ( cfg_mgmt_di ),
.cfg_mgmt_byte_en ( cfg_mgmt_byte_en ),
.cfg_mgmt_dwaddr ( cfg_mgmt_dwaddr ),
.cfg_mgmt_wr_en ( cfg_mgmt_wr_en ),
.cfg_mgmt_rd_en ( cfg_mgmt_rd_en ),
.cfg_mgmt_wr_readonly ( cfg_mgmt_wr_readonly ),
//----------------------------------------------------------------------------------------------------------------//
// 3. Advanced Error Reporting (AER) Interface //
//----------------------------------------------------------------------------------------------------------------//
.cfg_err_aer_headerlog ( cfg_err_aer_headerlog ),
.cfg_aer_interrupt_msgnum ( cfg_aer_interrupt_msgnum ),
.cfg_err_aer_headerlog_set ( cfg_err_aer_headerlog_set ),
.cfg_aer_ecrc_check_en ( cfg_aer_ecrc_check_en ),
.cfg_aer_ecrc_gen_en ( cfg_aer_ecrc_gen_en ),
//----------------------------------------------------------------------------------------------------------------//
// 4. Physical Layer Control and Status (PL) Interface //
//----------------------------------------------------------------------------------------------------------------//
.pl_initial_link_width ( pl_initial_link_width ),
.pl_lane_reversal_mode ( pl_lane_reversal_mode ),
.pl_link_gen2_cap ( pl_link_gen2_cap ),
.pl_link_partner_gen2_supported ( pl_link_partner_gen2_supported ),
.pl_link_upcfg_cap ( pl_link_upcfg_cap ),
.pl_ltssm_state ( pl_ltssm_state ),
.pl_received_hot_rst ( pl_received_hot_rst ),
.pl_sel_lnk_rate ( pl_sel_lnk_rate ),
.pl_sel_lnk_width ( pl_sel_lnk_width ),
.pl_directed_link_auton ( pl_directed_link_auton ),
.pl_directed_link_change ( pl_directed_link_change ),
.pl_directed_link_speed ( pl_directed_link_speed ),
.pl_directed_link_width ( pl_directed_link_width ),
.pl_upstream_prefer_deemph ( pl_upstream_prefer_deemph )
);
endmodule
|
// MBT 7/3/2016
//
// N read-port, M write-port ram
//
// reads are asynchronous
//
//
`include "bsg_defines.v"
module bsg_mem_multiport #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p =0
, parameter write_write_same_addr_p=0
, parameter `BSG_INV_PARAM(read_ports_p )
, parameter `BSG_INV_PARAM(write_ports_p )
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter harden_p=0)
(input w_clk_i
, input w_reset_i
, input [write_ports_p-1:0] w_v_i
, input [write_ports_p-1:0][addr_width_lp-1:0] w_addr_i
, input [write_ports_p-1:0][width_p-1:0] w_data_i
, input [read_ports_p-1:0] r_v_i
, input [read_ports_p-1:0][addr_width_lp-1:0] r_addr_i
, output [read_ports_p-1:0][width_p-1:0] r_data_o
);
logic [width_p-1:0] mem [els_p-1:0];
// this implementation ignores the r_v_i
genvar i,j;
for (i = 0; i < read_ports_p; i=i+1)
begin: rof_r
assign r_data_o[i] = mem[r_addr_i[i]];
end
wire unused = w_reset_i;
for (i = 0; i < write_ports_p; i=i+1)
begin: rof_w
always_ff @(posedge w_clk_i)
begin
if (w_v_i[i])
mem[w_addr_i[i]] <= w_data_i[i];
end
always @(posedge w_clk_i)
begin
assert (w_addr_i[i] < els_p)
else $error("Invalid address %x to %m of size %x\n", w_addr_i[i], els_p);
end
end
for (i = 0; i < write_ports_p; i=i+1)
begin: w2
for (j = 0; j < read_ports_p; j=j+1)
begin: r2
always @(posedge w_clk_i)
assert (~(w_addr_i[i] == r_addr_i[j] && w_v_i[i] && r_v_i[j] && !read_write_same_addr_p))
else $error("%m: Attempt to read and write same address");
end
end
for (i = 0; i < write_ports_p; i=i+1)
begin: w3
for (j = i; j < write_ports_p; j=j+1)
begin: w4
always @(posedge w_clk_i)
assert (~(w_addr_i[i] == w_addr_i[j] && w_v_i[i] && w_v_i[j] && !write_write_same_addr_p))
else $error("%m: Attempt to write same address twice");
end
end
// synopsys translate_off
initial
begin
$display("## bsg_mem_multiport: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d, write_write_same_addr_p=%d harden_p=%d (%m,%L)"
,width_p,els_p,read_write_same_addr_p, write_write_same_addr_p,harden_p);
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_multiport)
|
// Copyright 2018 Google LLC
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// Simple send-only UART
module uart(
input wire clock, // main clock
output reg txd = 1'b1,
input wire [23:0] tx_data,
output reg tx_empty = 1'b1, // '1' when tx_data can take a new byte
input wire transmit // pulse '1' when tx_data is valid
);
// clock divider to get baud rate. 82M / 115.2k = 712, giving 115.169 kb/s
parameter divide_count = 712;
// clock divider, assuming divide_count <= 1023
reg [9:0] divider = 0;
// shift register -- (start bit + 8 data bits + 1 stop bit) x 3 bytes
reg [29:0] shifter;
// how many bits to shift -- counts down from 30
reg [4:0] shift_count = 0;
always @(posedge clock) begin
// trying making this synchronous to debug missing transfers
// that could possibly be to do with the fifo in elk_interface...
// previously this was:
// assign tx_empty = (shift_count == 0) ? 1'b1 : 1'b0;
tx_empty = (shift_count == 0) ? 1'b1 : 1'b0;
// note that we can get slightly lower latency by setting this inside the loop that
// decrements shift_count, but that only happens on divider expiry and this happens
// every clock, so having it out here only slows it down 12 ns!
// accept a new byte to send
if (tx_empty == 1'b1 && transmit == 1'b1) begin
$display("accept new byte from tx_data");
// shifter <= {tx_data, 1'b0}; // 8-bit
shifter <= {1'b1, tx_data[23:16], 1'b0, 1'b1, tx_data[15:8], 1'b0, 1'b1, tx_data[7:0], 1'b0}; // 24-bit
shift_count <= 31;
tx_empty <= 1'b0;
end
// divider divides clock down to the serial bit rate (x 4 for reception?)
if (divider == divide_count) begin
divider <= 1;
// transmit a bit on divider expiry
if (shift_count != 0) begin
txd <= shifter[0];
// shift right
shifter <= {1'b1, shifter[29:1]};
shift_count <= shift_count - 5'd1;
end
end else begin
divider <= divider + 10'd1;
end
end
endmodule
|
Require Export Coq.Program.Tactics.
Require Export Coq.Setoids.Setoid.
Require Export Coq.Classes.Morphisms.
Require Export Coq.Arith.Arith_base.
Require Export Coq.Relations.Relations.
Require Export Coq.Lists.List.
Import EqNotations.
Import ListNotations.
(***
*** Ordered Types = Types with a PreOrder
***)
(* NOTE: The idea with this approach is that each type uniquely determines its
ordered type, but we keep the types separate from the ordered types to make
type inference work properly... *)
Class OTRelation (A:Type) : Type := ot_R : relation A.
Class OType (A:Type) {R:OTRelation A} : Prop :=
{ ot_PreOrder :> PreOrder ot_R }.
Arguments OTRelation A%type.
Arguments OType A%type {R}.
Instance OType_Reflexive A `{OType A} : Reflexive ot_R.
Proof. typeclasses eauto. Qed.
Instance OType_Transitive A `{OType A} : Transitive ot_R.
Proof. typeclasses eauto. Qed.
(* The equivalence relation for an OrderedType *)
Definition ot_equiv {A} `{OTRelation A} : relation A :=
fun x y => ot_R x y /\ ot_R y x.
Instance ot_equiv_Equivalence A `{OType A} : Equivalence ot_equiv.
Proof.
constructor; intro; intros.
{ split; reflexivity. }
{ destruct H0; split; assumption. }
{ destruct H0; destruct H1; split; transitivity y; assumption. }
Qed.
Notation "x <o= y" :=
(ot_R x y) (no associativity, at level 70).
Notation "x =o= y" :=
(ot_equiv x y) (no associativity, at level 70).
(* FIXME: replace "ot_R" below with "<o=" notation *)
(* FIXME: figure out what versions of this we need for rewriting! *)
Instance Proper_ot_R_ot_R A `{OType A}
: Proper (ot_R --> ot_R ==> Basics.impl) (@ot_R A _).
Proof.
intros a1 a2 Ra b1 b2 Rb Rab.
transitivity a1; [ assumption | ]. transitivity b1; assumption.
Qed.
Instance Subrelation_ot_equiv_ot_R A `{OType A} : subrelation (@ot_equiv A _) ot_R.
Proof.
intros a1 a2 Ra; destruct Ra; assumption.
Qed.
Instance Proper_ot_equiv_ot_R A `{OType A} :
Proper (ot_equiv ==> ot_equiv ==> iff) (@ot_R A _).
Proof.
intros x1 x2 Rx y1 y2 Ry; destruct Rx; destruct Ry; split; intro Rxy.
transitivity x1; [ assumption | ]; transitivity y1; assumption.
transitivity x2; [ assumption | ]; transitivity y2; assumption.
Qed.
Instance Proper_ot_equiv A `{OType A} :
Proper (ot_equiv ==> ot_equiv ==> iff) (@ot_equiv A _).
Proof.
intros x1 x2 Rx y1 y2 Ry. rewrite Rx. rewrite Ry. reflexivity.
Qed.
Instance Proper_ot_equiv_partial A `{OType A} a :
Proper (ot_equiv ==> Basics.flip Basics.impl) (@ot_equiv A _ a).
Proof.
intros x1 x2 Rx. rewrite Rx. reflexivity.
Qed.
(***
*** Commonly-Used Ordered Types
***)
(* The ordered type of propositions *)
Instance OTProp_R : OTRelation Prop := Basics.impl.
Instance OTProp : OType Prop.
Proof. repeat constructor; typeclasses eauto. Qed.
(* The discrete ordered type, where things are only related to themselves; we
make this a definition, not an instance, so that it can be instantiated for
particular types. *)
Definition OTdiscrete_R (A:Type) : OTRelation A := eq.
Definition OTdiscrete A : @OType A (OTdiscrete_R A).
repeat constructor. typeclasses eauto.
Qed.
(* The only ordered type over unit is the discrete one *)
Instance OTunit_R : OTRelation unit := OTdiscrete_R unit.
Instance OTunit : OType unit := OTdiscrete unit.
(* The ordered type that flips the ordering of an underlying OType; this becomes
a type itself in Coq *)
Inductive Flip A : Type := flip (a:A).
Definition unflip {A} (f:Flip A) : A := let (x) := f in x.
Instance OTFlip_R A (R:OTRelation A) : OTRelation (Flip A) :=
fun x y => unflip y <o= unflip x.
Instance OTFlip A `{OType A} : OType (Flip A).
Proof.
repeat constructor; intro; intros.
- destruct x; compute; reflexivity.
- destruct x; destruct y; destruct z; compute; transitivity a0; assumption.
Qed.
(* The pointwise relation on pairs *)
Instance OTpair_R A B (RA:OTRelation A) (RB:OTRelation B) : OTRelation (A*B) :=
fun p1 p2 => ot_R (fst p1) (fst p2) /\ ot_R (snd p1) (snd p2).
Instance OTpair A B `(OType A) `(OType B) : OType (A*B).
Proof.
repeat constructor.
- destruct x. reflexivity.
- destruct x. reflexivity.
- destruct x; destruct y; destruct z; destruct H1; destruct H2;
transitivity a0; assumption.
- destruct x; destruct y; destruct z; destruct H1; destruct H2;
transitivity b0; assumption.
Qed.
(* The sort-of pointwise relation on sum types *)
Inductive sumR {A B} (RA:OTRelation A) (RB:OTRelation B) : A+B -> A+B -> Prop :=
| sumR_inl a1 a2 : RA a1 a2 -> sumR RA RB (inl a1) (inl a2)
| sumR_inr b1 b2 : RB b1 b2 -> sumR RA RB (inr b1) (inr b2).
Instance OTsum_R A B (RA:OTRelation A) (RB:OTRelation B) : OTRelation (A+B) :=
sumR RA RB.
Instance OTsum A B `(OType A) `(OType B) : OType (A+B).
Proof.
repeat constructor; intro; intros.
{ destruct x; constructor; reflexivity. }
{ destruct H1; inversion H2.
- constructor; transitivity a2; assumption.
- constructor; transitivity b2; assumption. }
Qed.
(* NOTE: the following definition requires everything above to be polymorphic *)
(* NOTE: The definition we choose for OTType is actually deep: instead of
requiring ot_Type A = ot_Type B, we could just require a coercion function from
ot_Type A to ot_Type B, which would yield something more like HoTT... though
maybe it wouldn't work unless we assumed the HoTT axiom? As it is, we might need
UIP to hold if we want to use the definition given here... *)
(*
Program Definition OTType : OType :=
{|
ot_Type := OType;
ot_R := (fun A B =>
exists (e:ot_Type A = ot_Type B),
forall (x y:A),
ot_R A x y ->
ot_R B (rew [fun A => A] e in x)
(rew [fun A => A] e in y));
|}.
*)
(***
*** Proper Instances for Simple Ordered Types
***)
Instance Proper_pair A B `{OTRelation A} `{OTRelation B} :
Proper (ot_R ==> ot_R ==> ot_R) (pair : A -> B -> A*B).
Proof.
repeat intro; split; assumption.
Qed.
Instance Proper_fst A B `{OTRelation A} `{OTRelation B} :
Proper (ot_R ==> ot_R) (fst : A*B -> A).
Proof.
intros p1 p2 Rp; destruct Rp; assumption.
Qed.
Instance Proper_snd A B `{OTRelation A} `{OTRelation B} :
Proper (ot_R ==> ot_R) (snd : A*B -> B).
Proof.
intros p1 p2 Rp; destruct Rp; assumption.
Qed.
(***
*** The Ordered Type for Functions
***)
(* The type of continuous, i.e. Proper, functions between ordered types *)
Record Pfun A B {RA:OTRelation A} {RB:OTRelation B} :=
{
pfun_app : A -> B;
pfun_Proper : Proper (ot_R ==> ot_R) pfun_app
}.
Arguments pfun_app {_ _ _ _} _ _.
Arguments pfun_Proper [_ _ _ _] _ _ _ _.
Notation "A '-o>' B" :=
(Pfun A B) (right associativity, at level 99).
Notation "x @o@ y" :=
(pfun_app x y) (left associativity, at level 20).
(* The non-dependent function ordered type *)
Instance OTarrow_R A B {RA:OTRelation A} {RB:OTRelation B} : OTRelation (A -o> B) :=
fun f g =>
forall a1 a2, ot_R a1 a2 -> ot_R (pfun_app f a1) (pfun_app g a2).
Instance OTarrow A B `{OType A} `{OType B} : OType (A -o> B).
Proof.
repeat constructor; intro; intros; intro; intros.
{ apply pfun_Proper; assumption. }
{ transitivity (pfun_app y a1).
- apply H1; reflexivity.
- apply H2; assumption. }
Qed.
(* FIXME: could also do a forall type, but need the second type argument, B, to
itself be proper, i.e., to be an element of OTarrow A OType. *)
(* pfun_app is always Proper *)
Instance Proper_pfun_app A B `{OTRelation A} `{OTRelation B} :
Proper (ot_R ==> ot_R ==> ot_R) (@pfun_app A B _ _).
Proof.
intros f1 f2 Rf a1 a2 Ra. apply Rf; assumption.
Qed.
(* pfun_app is always Proper w.r.t. ot_equiv *)
Instance Proper_pfun_app_equiv A B `{OTRelation A} `{OTRelation B} :
Proper (ot_equiv ==> ot_equiv ==> ot_equiv) (@pfun_app A B _ _).
Proof.
intros f1 f2 Rf a1 a2 Ra; destruct Rf; destruct Ra.
split; apply Proper_pfun_app; assumption.
Qed.
Instance Proper_pfun_app_partial A B `{OTRelation A} `{OTRelation B} f :
Proper (ot_R ==> ot_R) (pfun_app (A:=A) (B:=B) f).
Proof.
apply pfun_Proper.
Qed.
Instance Proper_pfun_app_partial_equiv A B `{OTRelation A} `{OTRelation B} f :
Proper (ot_equiv ==> ot_equiv) (@pfun_app A B _ _ f).
Proof.
intros a1 a2 Ra; destruct Ra; split; apply pfun_Proper; assumption.
Qed.
(***
*** Some Useful Pfuns
***)
(* The identity pfun *)
Definition id_pfun {A} `{OTRelation A} : A -o> A :=
{| pfun_app := fun x => x; pfun_Proper := fun x1 x2 Rx => Rx |}.
(* The identity pfun *)
Program Definition compose_pfun {A B C}
`{OTRelation A} `{OTRelation B} `{OTRelation C}
(f:A -o> B) (g:B -o> C) : A -o> C :=
{| pfun_app := fun x => pfun_app g (pfun_app f x);
pfun_Proper := _ |}.
Next Obligation.
intros x1 x2 Rx. apply pfun_Proper. apply pfun_Proper. assumption.
Qed.
Instance Proper_compose_pfun A B C
`{OTRelation A} `{OTRelation B} `{OTRelation C} :
Proper (ot_R ==> ot_R ==> ot_R) (@compose_pfun A B C _ _ _).
intros f1 f2 Rf g1 g2 Rg a1 a2 Ra.
apply Rg. apply Rf. assumption.
Qed.
Instance Proper_compose_pfun_equiv A B C
`{OTRelation A} `{OTRelation B} `{OTRelation C} :
Proper (ot_equiv ==> ot_equiv ==> ot_equiv) (@compose_pfun A B C _ _ _).
Proof.
intros f1 f2 Rf g1 g2 Rg.
split; intros a1 a2 Ra; simpl; apply Rg; apply Rf; apply Ra.
Qed.
(* Category theory laws for Pfuns *)
Lemma id_compose_pfun A B `{OTRelation A} `{OTRelation B} (f: A -o> B) :
ot_equiv (compose_pfun id_pfun f) f.
split; intros a1 a2 Ra; simpl; apply pfun_Proper; assumption.
Qed.
Lemma compose_id_pfun A B `{OTRelation A} `{OTRelation B} (f: A -o> B) :
ot_equiv (compose_pfun f id_pfun) f.
split; intros a1 a2 Ra; simpl; apply pfun_Proper; assumption.
Qed.
Lemma compose_compose_pfun A B C D
`{OTRelation A} `{OTRelation B} `{OTRelation C} `{OTRelation D}
(f: A -o> B) (g: B -o> C) (h: C -o> D) :
ot_equiv (compose_pfun f (compose_pfun g h)) (compose_pfun (compose_pfun f g) h).
split; intros a1 a2 Ra; simpl; repeat apply pfun_Proper; assumption.
Qed.
(* The constant pfun *)
Program Definition const_pfun {A B} `{OTRelation A} `{OType B} b : A -o> B :=
{| pfun_app := fun _ => b; pfun_Proper := fun _ _ _ => ltac:(reflexivity) |}.
(* FIXME: this proper-ness proof should include irrelevance of the OType arg *)
Instance Proper_const_pfun {A B} `{OTRelation A} `{OType B} :
Proper (ot_R ==> ot_R) (const_pfun (A:=A) (B:=B)).
Proof.
intros b1 b2 Rb a1 a2 Ra. apply Rb.
Qed.
Instance Proper_const_pfun_equiv {A B} `{OTRelation A} `{OType B} :
Proper (ot_equiv ==> ot_equiv) (const_pfun (A:=A) (B:=B)).
Proof.
intros b1 b2 Rb; split; intros a1 a2 Ra; apply Rb.
Qed.
(* Composing with the constant pfun on the left *)
Lemma compose_const_pfun_f A B C `{OTRelation A} `{OType B} `{OType C}
b (f : B -o> C) :
ot_equiv (compose_pfun (const_pfun (A:=A) b) f) (const_pfun (pfun_app f b)).
split; intros a1 a2 Ra; reflexivity.
Qed.
(* Composing with the constant pfun on the right *)
Lemma compose_f_const_pfun A B C `{OTRelation A} `{OType B} `{OType C}
(f : A -o> B) c :
ot_equiv (compose_pfun f (const_pfun c)) (const_pfun c).
split; intros a1 a2 Ra; reflexivity.
Qed.
(* Take the pair of the outputs of two pfuns *)
Program Definition pair_pfun {A B C}
`{OTRelation A} `{OTRelation B} `{OTRelation C}
(f: A -o> B) (g: A -o> C) : A -o> (B * C) :=
{| pfun_app := fun a => (pfun_app f a, pfun_app g a) |}.
Next Obligation.
intros a1 a2 Ra; split; apply pfun_Proper; assumption.
Qed.
Instance Proper_pair_pfun A B C `{OTRelation A} `{OTRelation B} `{OTRelation C} :
Proper (ot_R ==> ot_R ==> ot_R) (pair_pfun (A:=A) (B:=B) (C:=C)).
Proof.
intros a1 a2 Ra b1 b2 Rb c1 c2 Rc; simpl; split.
- apply Ra; assumption.
- apply Rb; assumption.
Qed.
Instance Proper_pair_pfun_equiv A B C
`{OTRelation A} `{OTRelation B} `{OTRelation C} :
Proper (ot_equiv ==> ot_equiv ==> ot_equiv)
(pair_pfun (A:=A) (B:=B) (C:=C)).
Proof.
intros a1 a2 Ra b1 b2 Rb.
destruct Ra as [ Ra1 Ra2 ]; destruct Rb as [ Rb1 Rb2 ].
split; intros c1 c2 Rc; split; simpl;
first [ apply Ra1 | apply Ra2 | apply Rb1 | apply Rb2 ]; assumption.
Qed.
(* compose commutes with pair *)
Lemma compose_f_pair_pfun A B C D
`{OTRelation A} `{OTRelation B} `{OTRelation C} `{OTRelation D}
(f: A -o> B) (g: B -o> C) (h: B -o> D) :
ot_equiv (compose_pfun f (pair_pfun g h))
(pair_pfun (compose_pfun f g) (compose_pfun f h)).
split; intros a1 a2 Ra; simpl; split; repeat apply pfun_Proper; assumption.
Qed.
(* The first projection pfun *)
Definition fst_pfun {A B} `{OTRelation A} `{OTRelation B} : A * B -o> A :=
{| pfun_app := fst; pfun_Proper := _ |}.
(* The second projection pfun *)
Definition snd_pfun {A B} `{OTRelation A} `{OTRelation B} : A * B -o> B :=
{| pfun_app := snd; pfun_Proper := _ |}.
(* Composing pair with fst gives the first function in the pair *)
Lemma compose_pair_fst A B C `{OTRelation A} `{OTRelation B} `{OTRelation C}
(f: A -o> B) (g: A -o> C) :
ot_equiv (compose_pfun (pair_pfun f g) fst_pfun) f.
split; intros a1 a2 Ra; simpl; apply pfun_Proper; assumption.
Qed.
(* Composing pair with snd gives the second function in the pair *)
Lemma compose_pair_snd A B C `{OTRelation A} `{OTRelation B} `{OTRelation C}
(f: A -o> B) (g: A -o> C) :
ot_equiv (compose_pfun (pair_pfun f g) snd_pfun) g.
split; intros a1 a2 Ra; simpl; apply pfun_Proper; assumption.
Qed.
(* Taking the pair of fst and snd is the identity *)
Lemma pair_fst_snd_eta A B `{OTRelation A} `{OTRelation B} :
ot_equiv (pair_pfun (fst_pfun (A:=A) (B:=B)) snd_pfun) id_pfun.
split; intros p1 p2 Rp; destruct Rp; split; simpl; assumption.
Qed.
(* Curry a Pfun *)
Program Definition pfun_curry {A B C} `{OType A} `{OTRelation B} `{OTRelation C}
(pfun : (A * B) -o> C)
: A -o> (B -o> C) :=
{| pfun_app :=
fun a =>
{| pfun_app := fun b => pfun_app pfun (a,b);
pfun_Proper := _ |};
pfun_Proper := _ |}.
Next Obligation.
Proof.
intros b1 b2 Rb. apply pfun_Proper.
split; [ reflexivity | assumption ].
Qed.
Next Obligation.
Proof.
intros a1 a2 Ra b1 b2 Rb; simpl.
apply pfun_Proper; split; assumption.
Qed.
(* Uncrry a Pfun *)
Program Definition pfun_uncurry {A B C}
`{OTRelation A} `{OTRelation B} `{OTRelation C}
(pfun : A -o> (B -o> C))
: (A * B) -o> C :=
{| pfun_app :=
fun ab => pfun_app (pfun_app pfun (fst ab)) (snd ab);
pfun_Proper := _ |}.
Next Obligation.
Proof.
intros ab1 ab2 Rab. destruct Rab as [ Ra Rb ].
exact (pfun_Proper pfun (fst ab1) (fst ab2) Ra (snd ab1) (snd ab2) Rb).
Qed.
(* pfun_curry is Proper *)
Instance Proper_pfun_curry A B C `{OType A} `{OTRelation B} `{OTRelation C}
: Proper (ot_R ==> ot_R) (pfun_curry (A:=A) (B:=B) (C:=C)).
Proof.
intros f1 f2 Rf a1 a2 Ra b1 b2 Rb. apply Rf. split; assumption.
Qed.
(* pfun_curry is Proper w.r.t. equivalence *)
Instance Proper_pfun_curry_equiv A B C `{OType A} `{OTRelation B} `{OTRelation C} :
Proper (ot_equiv ==> ot_equiv) (pfun_curry (A:=A) (B:=B) (C:=C)).
Proof.
intros f1 f2 Rf; destruct Rf; split; apply Proper_pfun_curry; assumption.
Qed.
(* FIXME: Proper instance for pfun_uncurry *)
(* Currying and uncurrying of pfuns form an isomorphism: part 1 *)
Lemma pfun_curry_uncurry_eq A B C `{OType A} `{OTRelation B} `{OTRelation C}
(f: (A * B) -o> C) :
pfun_uncurry (pfun_curry f) =o= f.
split; intros ab1 ab2 Rab; simpl; apply pfun_Proper;
destruct Rab; split; assumption.
Qed.
(* Currying and uncurrying of pfuns form an isomorphism: part 2 *)
Lemma pfun_uncurry_curry_eq A B C `{OType A} `{OTRelation B} `{OTRelation C}
(f: A -o> B -o> C) :
pfun_curry (pfun_uncurry f) =o= f.
split; intros a1 a2 Ra b1 b2 Rb; simpl; apply Proper_pfun_app;
try apply pfun_Proper; assumption.
Qed.
(* The S combinator for pfuns (FIXME: do we need this?) *)
Program Definition pfun_S {A B C} `{OTRelation A} `{OTRelation B} `{OTRelation C}
: (A -o> B -o> C) -o> (A -o> B) -o> A -o> C :=
{| pfun_app :=
fun f =>
{| pfun_app :=
fun g =>
{| pfun_app := fun a => pfun_app (pfun_app f a) (pfun_app g a) |}
|}
|}.
Next Obligation.
intros a1 a2 Ra; apply Proper_pfun_app; try apply pfun_Proper; assumption.
Qed.
Next Obligation.
intros g1 g2 Rg a1 a2 Ra. simpl. apply Proper_pfun_app; try assumption.
- apply pfun_Proper; assumption.
- apply Rg; assumption.
Qed.
Next Obligation.
intros f1 f2 Rf g1 g2 Rg a1 a2 Ra. simpl. apply Proper_pfun_app; try assumption.
- apply Rf; assumption.
- apply Rg; assumption.
Qed.
(* This is the S combinator, but partially applied *)
Program Definition pfun_apply {A B C}
`{OTRelation A} `{OTRelation B} `{OTRelation C}
(f: A -o> B -o> C) (g: A -o> B) : A -o> C :=
{| pfun_app := fun a => pfun_app (pfun_app f a) (pfun_app g a) |}.
Next Obligation.
intros a1 a2 Ra; apply Proper_pfun_app; try apply pfun_Proper; assumption.
Qed.
Instance Proper_pfun_apply A B C `{OTRelation A} `{OTRelation B} `{OTRelation C} :
Proper (ot_R ==> ot_R ==> ot_R) (pfun_apply (A:=A) (B:=B) (C:=C)).
Proof.
intros a1 a2 Ra b1 b2 Rb c1 c2 Rc. simpl.
apply Ra; try assumption. apply Rb; try assumption.
Qed.
Instance Proper_pfun_apply_equiv A B C
`{OTRelation A} `{OTRelation B} `{OTRelation C} :
Proper (ot_equiv ==> ot_equiv ==> ot_equiv) (pfun_apply (A:=A) (B:=B) (C:=C)).
Proof.
intros a1 a2 Ra b1 b2 Rb; split; intros c1 c2 Rc; simpl;
apply Ra; try apply Rb; assumption.
Qed.
(* compose commutes with S *)
Lemma compose_pfun_apply A B C D `{OType A} `{OType B} `{OType C} `{OType D}
(f : A -o> B) (g: B -o> C -o> D) h :
compose_pfun f (pfun_apply g h)
=o= pfun_apply (compose_pfun f g) (compose_pfun f h).
split; intros a1 a2 Ra; simpl; rewrite Ra; reflexivity.
Qed.
(* compose commutes with currying *)
Lemma compose_pfun_curry A B C D `{OType A} `{OType B} `{OType C} `{OType D}
(f: A -o> B) (g: B * C -o> D) :
ot_equiv (compose_pfun f (pfun_curry g))
(pfun_curry
(compose_pfun (pair_pfun (compose_pfun fst_pfun f) snd_pfun) g)).
split; intros a1 a2 Ra c1 c2 Rc; simpl; rewrite Ra; rewrite Rc; reflexivity.
Qed.
(* Applying a const is just composition. Note that we add the extra OType
constraint to quantify over all possible proofs that B -o> C is an OType, so
this rule applies independently of this aOType proof. *)
Lemma pfun_apply_const A B C `{OType A} `{OType B} `{OType C}
{OBC: OType (B -o> C)} (f: B -o> C) (g: A -o> B) :
ot_equiv (pfun_apply (A:=A) (const_pfun f) g) (compose_pfun g f).
split; intros a1 a2 Ra; simpl; rewrite Ra; reflexivity.
Qed.
(* We can simplify pfun_S used with pfun_curry *)
Lemma pfun_apply_pfun_curry A B C `{OType A} `{OType B} `{OType C} f g :
ot_equiv (pfun_apply (A:=A) (B:=B) (C:=C) (pfun_curry f) g)
(compose_pfun (pair_pfun id_pfun g) f).
split; intros a1 a2 Ra; simpl; apply pfun_Proper; split;
try apply pfun_Proper; assumption.
Qed.
(* The pair constructor as a pfun *)
Program Definition pair_ctor_pfun {A B} `{OType A} `{OType B}
: A -o> B -o> A * B :=
{| pfun_app := fun a => {| pfun_app := fun b => (a,b) |} |}.
Next Obligation.
intros b1 b2 Rb; rewrite Rb; reflexivity.
Qed.
Next Obligation.
intros a1 a2 Ra b1 b2 Rb; simpl; rewrite Ra; rewrite Rb; reflexivity.
Qed.
(* Applying pair_ctor_pfun yields a pair_pfun *)
Lemma apply_pair_ctor_pfun {A B C} `{OType A} `{OType B} `{OType C}
(f: A -o> B) (g: A -o> C) :
ot_equiv (pfun_apply (pfun_apply (const_pfun pair_ctor_pfun) f) g)
(pair_pfun f g).
split; intros a1 a2 Ra; simpl; rewrite Ra; reflexivity.
Qed.
(***
*** Building Proper Functions
***)
Class ProperPair A `{OTRelation A} (x y:A) : Prop :=
proper_pair_pf : ot_R x y.
Definition ofun {A B} `{OTRelation A} `{OTRelation B} (f: A -> B)
{prp:forall x y, ProperPair A x y -> ProperPair B (f x) (f y)}
: A -o> B :=
{| pfun_app := f; pfun_Proper := prp |}.
Instance ProperPair_refl A `{OType A} (x:A) : ProperPair A x x.
Proof.
unfold ProperPair. reflexivity.
Qed.
Instance ProperPair_pfun_app A B `{OType A} `{OType B}
(fl fr:A -o> B) argl argr
(prpf:ProperPair (A -o> B) fl fr)
(prpa:ProperPair A argl argr)
: ProperPair B (pfun_app fl argl) (pfun_app fr argr).
Proof.
apply prpf; assumption.
Qed.
Instance ProperPair_ofun A B `{OType A} `{OType B} (f g:A -> B) prpl prpr
(pf: forall x y, ProperPair A x y -> ProperPair B (f x) (g y)) :
ProperPair (A -o> B) (@ofun A B _ _ f prpl) (@ofun A B _ _ g prpr).
Proof.
intros xl xr Rx; apply pf; assumption.
Qed.
(***
*** Ordered Terms and ProperPair Instances for Pair Operations
***)
(* Proper function for fst *)
Definition ofst {A B} `{OTRelation A} `{OTRelation B} : A * B -o> A :=
{| pfun_app := fst; pfun_Proper := _ |}.
(* Proper function for snd *)
Definition osnd {A B} `{OTRelation A} `{OTRelation B} : A * B -o> B :=
{| pfun_app := snd; pfun_Proper := _ |}.
(* Proper function for pair *)
Program Definition opair {A B} `{OType A} `{OType B} : A -o> B -o> A * B :=
{| pfun_app :=
fun a => {| pfun_app := fun b => pair a b;
pfun_Proper := _ |};
pfun_Proper := _ |}.
Next Obligation.
intros b1 b2 Rb. split; [ reflexivity | assumption ].
Qed.
Next Obligation.
intros a1 a2 Ra b1 b2 Rb. split; assumption.
Qed.
(* Notation for proper pairs *)
Notation "( x ,o, y )" := (opair @o@ x @o@ y) (at level 0).
(* FIXME: get this notation to work *)
(*
Notation "( x ,o, y ,o, .. ,o, z )" :=
(pfun_app opair .. (pfun_app (pfun_app opair x) y) .. z)
(at level 0).
*)
(*
Instance ProperPair_fst A B `{OType A} `{OType B} (p1 p2: A*B)
(pf: ProperPair (A*B) p1 p2) :
ProperPair A (fst p1) (fst p2).
Proof.
destruct pf; assumption.
Qed.
Instance ProperPair_snd A B `{OType A} `{OType B} (p1 p2: A*B)
(pf: ProperPair (A*B) p1 p2) :
ProperPair B (snd p1) (snd p2).
Proof.
destruct pf; assumption.
Qed.
Instance ProperPair_pair A B `{OType A} `{OType B}
(x1 x2:A) (y1 y2:B) (pfx: ProperPair A x1 x2) (pfy: ProperPair B y1 y2) :
ProperPair (A*B) (pair x1 y1) (pair x2 y2).
Proof.
split; assumption.
Qed.
*)
(***
*** Notations for Ordered Types
***)
(* FIXME: why don't these work?
Notation "'pfun' ( x : A ) =o> t" :=
(@ot_Lambda A _ (fun x => t))
(at level 100, right associativity, x at level 99) : pterm_scope.
Notation "'pfun' x =o> t" :=
(ot_Lambda (fun x => t))
(at level 100, right associativity, x at level 99) : pterm_scope.
*)
(***
*** Ordered Type Functions
***)
(*
Definition ot_fun_app (TF: forall A `{OType A}, Type) A `{OType A} := TF A.
Notation "F @t@ A" :=
(ot_fun_app F A%type) (left associativity, at level 20).
*)
Class OTRelationF (TF: forall A `{OType A}, Type) : Type :=
ot_rel_app : forall A `{OType A}, OTRelation (TF A).
Instance OTRelation_ot_rel_app TF `(OTRelationF TF) A `(OType A) :
OTRelation (TF A _ _) := ot_rel_app A.
Class OTypeF (TF: forall A `{OType A}, Type) `{OTRelationF TF} : Prop :=
otype_app : forall A `{OType A}, OType (TF A).
Instance OType_otype_app TF `(OTypeF TF) A `(OType A) :
OType (TF A _ _) := otype_app A.
(***
*** Examples of Ordered Terms
***)
Module OTExamples.
Definition ex1 : Prop -o> Prop := ofun (fun p => p).
(* Eval compute in (pfun_app ex1 : Prop -> Prop). *)
Definition ex2 {A} `{OType A} : A -o> A := ofun (fun p => p).
(* Eval simpl in (fun A `{OType A} => pfun_app (@ex2 A _ _) : A -> A). *)
Definition ex3 {A} `{OType A} : A -o> A -o> A :=
ofun (fun p1 => ofun (fun p2 => p1)).
(* Eval simpl in (fun (A:OType) x => pfun_app (pfun_app (@ex3 A) x)). *)
Definition ex4 {A B} `{OType A} `{OType B} : (A * B -o> A) :=
ofun (fun p => ofst @o@ p).
(* Eval simpl in (fun {A B} `{OType A} `{OType B} =>
pfun_app ex4 : A * B -> A). *)
Definition ex5 {A B} `{OType A} `{OType B} : A * B -o> B * A :=
ofun (fun p => (osnd @o@ p ,o, ofst @o@ p)).
(* Eval simpl in (fun {A B} `{OType A} `{OType B} =>
pfun_app ex5 : A * B -> B * A). *)
Definition ex6 {A B C} `{OType A} `{OType B} `{OType C} : A * B * C -o> C * A :=
ofun (fun triple => (osnd @o@ triple ,o, ofst @o@ (ofst @o@ triple))).
Definition ex7 {A B C} `{OType A} `{OType B} `{OType C}
: (A * B -o> C) -o> C -o> A -o> B -o> C :=
ofun (fun f =>
ofun
(fun c =>
ofun
(fun a =>
ofun (fun b => f @o@ (a ,o, b))))).
End OTExamples.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXTN_4_V
`define SKY130_FD_SC_HS__DLXTN_4_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog wrapper for dlxtn with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlxtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlxtn_4 (
Q ,
D ,
GATE_N,
VPWR ,
VGND
);
output Q ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
sky130_fd_sc_hs__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__dlxtn_4 (
Q ,
D ,
GATE_N
);
output Q ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXTN_4_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD3_FUNCTIONAL_V
`define SKY130_FD_SC_HD__DLYGATE4SD3_FUNCTIONAL_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__dlygate4sd3 (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD3_FUNCTIONAL_V |
// niosII_system.v
// Generated using ACDS version 13.0sp1 232 at 2016.03.09.00:07:45
`timescale 1 ps / 1 ps
module niosII_system (
input wire clk_clk, // clk.clk
input wire reset_reset_n, // reset.reset_n
output wire [7:0] green_leds_external_connection_export, // green_leds_external_connection.export
input wire [7:0] switches_external_connection_export, // switches_external_connection.export
output wire [11:0] sdram_0_wire_addr, // sdram_0_wire.addr
output wire [1:0] sdram_0_wire_ba, // .ba
output wire sdram_0_wire_cas_n, // .cas_n
output wire sdram_0_wire_cke, // .cke
output wire sdram_0_wire_cs_n, // .cs_n
inout wire [15:0] sdram_0_wire_dq, // .dq
output wire [1:0] sdram_0_wire_dqm, // .dqm
output wire sdram_0_wire_ras_n, // .ras_n
output wire sdram_0_wire_we_n, // .we_n
inout wire [15:0] sram_0_external_interface_DQ, // sram_0_external_interface.DQ
output wire [17:0] sram_0_external_interface_ADDR, // .ADDR
output wire sram_0_external_interface_LB_N, // .LB_N
output wire sram_0_external_interface_UB_N, // .UB_N
output wire sram_0_external_interface_CE_N, // .CE_N
output wire sram_0_external_interface_OE_N, // .OE_N
output wire sram_0_external_interface_WE_N, // .WE_N
output wire altpll_0_c0_clk, // altpll_0_c0.clk
input wire usb_0_external_interface_INT1, // usb_0_external_interface.INT1
inout wire [15:0] usb_0_external_interface_DATA, // .DATA
output wire usb_0_external_interface_RST_N, // .RST_N
output wire [1:0] usb_0_external_interface_ADDR, // .ADDR
output wire usb_0_external_interface_CS_N, // .CS_N
output wire usb_0_external_interface_RD_N, // .RD_N
output wire usb_0_external_interface_WR_N, // .WR_N
input wire usb_0_external_interface_INT0 // .INT0
);
wire altpll_0_c1_clk; // altpll_0:c1 -> [addr_router:clk, addr_router_001:clk, burst_adapter:clk, burst_adapter_001:clk, cmd_xbar_demux:clk, cmd_xbar_demux_001:clk, cmd_xbar_mux:clk, cmd_xbar_mux_001:clk, cmd_xbar_mux_002:clk, cmd_xbar_mux_003:clk, crosser:in_clk, crosser_001:out_clk, green_leds:clk, green_leds_s1_translator:clk, green_leds_s1_translator_avalon_universal_slave_0_agent:clk, green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, id_router:clk, id_router_001:clk, id_router_002:clk, id_router_003:clk, id_router_004:clk, id_router_005:clk, id_router_006:clk, id_router_007:clk, id_router_009:clk, id_router_010:clk, irq_mapper:clk, jtag_uart_0:clk, jtag_uart_0_avalon_jtag_slave_translator:clk, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:clk, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, nios2_qsys_0:clk, nios2_qsys_0_data_master_translator:clk, nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:clk, nios2_qsys_0_instruction_master_translator:clk, nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:clk, nios2_qsys_0_jtag_debug_module_translator:clk, nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:clk, nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, onchip_memory2_0:clk, onchip_memory2_0_s1_translator:clk, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:clk, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, rsp_xbar_demux:clk, rsp_xbar_demux_001:clk, rsp_xbar_demux_002:clk, rsp_xbar_demux_003:clk, rsp_xbar_demux_004:clk, rsp_xbar_demux_005:clk, rsp_xbar_demux_006:clk, rsp_xbar_demux_007:clk, rsp_xbar_demux_009:clk, rsp_xbar_demux_010:clk, rsp_xbar_mux:clk, rsp_xbar_mux_001:clk, rst_controller:clk, sdram_0:clk, sdram_0_s1_translator:clk, sdram_0_s1_translator_avalon_universal_slave_0_agent:clk, sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:clk, sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, sram_0:clk, sram_0_avalon_sram_slave_translator:clk, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:clk, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:clk, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, switches:clk, switches_s1_translator:clk, switches_s1_translator_avalon_universal_slave_0_agent:clk, switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, sysid_qsys_0:clock, sysid_qsys_0_control_slave_translator:clk, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:clk, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, timer_0:clk, timer_0_s1_translator:clk, timer_0_s1_translator_avalon_universal_slave_0_agent:clk, timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, usb_0:clk, usb_0_avalon_usb_slave_translator:clk, usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:clk, usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, width_adapter:clk, width_adapter_001:clk, width_adapter_002:clk, width_adapter_003:clk]
wire nios2_qsys_0_instruction_master_waitrequest; // nios2_qsys_0_instruction_master_translator:av_waitrequest -> nios2_qsys_0:i_waitrequest
wire [24:0] nios2_qsys_0_instruction_master_address; // nios2_qsys_0:i_address -> nios2_qsys_0_instruction_master_translator:av_address
wire nios2_qsys_0_instruction_master_read; // nios2_qsys_0:i_read -> nios2_qsys_0_instruction_master_translator:av_read
wire [31:0] nios2_qsys_0_instruction_master_readdata; // nios2_qsys_0_instruction_master_translator:av_readdata -> nios2_qsys_0:i_readdata
wire nios2_qsys_0_data_master_waitrequest; // nios2_qsys_0_data_master_translator:av_waitrequest -> nios2_qsys_0:d_waitrequest
wire [31:0] nios2_qsys_0_data_master_writedata; // nios2_qsys_0:d_writedata -> nios2_qsys_0_data_master_translator:av_writedata
wire [24:0] nios2_qsys_0_data_master_address; // nios2_qsys_0:d_address -> nios2_qsys_0_data_master_translator:av_address
wire nios2_qsys_0_data_master_write; // nios2_qsys_0:d_write -> nios2_qsys_0_data_master_translator:av_write
wire nios2_qsys_0_data_master_read; // nios2_qsys_0:d_read -> nios2_qsys_0_data_master_translator:av_read
wire [31:0] nios2_qsys_0_data_master_readdata; // nios2_qsys_0_data_master_translator:av_readdata -> nios2_qsys_0:d_readdata
wire nios2_qsys_0_data_master_debugaccess; // nios2_qsys_0:jtag_debug_module_debugaccess_to_roms -> nios2_qsys_0_data_master_translator:av_debugaccess
wire [3:0] nios2_qsys_0_data_master_byteenable; // nios2_qsys_0:d_byteenable -> nios2_qsys_0_data_master_translator:av_byteenable
wire nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest; // nios2_qsys_0:jtag_debug_module_waitrequest -> nios2_qsys_0_jtag_debug_module_translator:av_waitrequest
wire [31:0] nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_writedata; // nios2_qsys_0_jtag_debug_module_translator:av_writedata -> nios2_qsys_0:jtag_debug_module_writedata
wire [8:0] nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_address; // nios2_qsys_0_jtag_debug_module_translator:av_address -> nios2_qsys_0:jtag_debug_module_address
wire nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_write; // nios2_qsys_0_jtag_debug_module_translator:av_write -> nios2_qsys_0:jtag_debug_module_write
wire nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_read; // nios2_qsys_0_jtag_debug_module_translator:av_read -> nios2_qsys_0:jtag_debug_module_read
wire [31:0] nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_readdata; // nios2_qsys_0:jtag_debug_module_readdata -> nios2_qsys_0_jtag_debug_module_translator:av_readdata
wire nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess; // nios2_qsys_0_jtag_debug_module_translator:av_debugaccess -> nios2_qsys_0:jtag_debug_module_debugaccess
wire [3:0] nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_byteenable; // nios2_qsys_0_jtag_debug_module_translator:av_byteenable -> nios2_qsys_0:jtag_debug_module_byteenable
wire sdram_0_s1_translator_avalon_anti_slave_0_waitrequest; // sdram_0:za_waitrequest -> sdram_0_s1_translator:av_waitrequest
wire [15:0] sdram_0_s1_translator_avalon_anti_slave_0_writedata; // sdram_0_s1_translator:av_writedata -> sdram_0:az_data
wire [21:0] sdram_0_s1_translator_avalon_anti_slave_0_address; // sdram_0_s1_translator:av_address -> sdram_0:az_addr
wire sdram_0_s1_translator_avalon_anti_slave_0_chipselect; // sdram_0_s1_translator:av_chipselect -> sdram_0:az_cs
wire sdram_0_s1_translator_avalon_anti_slave_0_write; // sdram_0_s1_translator:av_write -> sdram_0:az_wr_n
wire sdram_0_s1_translator_avalon_anti_slave_0_read; // sdram_0_s1_translator:av_read -> sdram_0:az_rd_n
wire [15:0] sdram_0_s1_translator_avalon_anti_slave_0_readdata; // sdram_0:za_data -> sdram_0_s1_translator:av_readdata
wire sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid; // sdram_0:za_valid -> sdram_0_s1_translator:av_readdatavalid
wire [1:0] sdram_0_s1_translator_avalon_anti_slave_0_byteenable; // sdram_0_s1_translator:av_byteenable -> sdram_0:az_be_n
wire [31:0] onchip_memory2_0_s1_translator_avalon_anti_slave_0_writedata; // onchip_memory2_0_s1_translator:av_writedata -> onchip_memory2_0:writedata
wire [11:0] onchip_memory2_0_s1_translator_avalon_anti_slave_0_address; // onchip_memory2_0_s1_translator:av_address -> onchip_memory2_0:address
wire onchip_memory2_0_s1_translator_avalon_anti_slave_0_chipselect; // onchip_memory2_0_s1_translator:av_chipselect -> onchip_memory2_0:chipselect
wire onchip_memory2_0_s1_translator_avalon_anti_slave_0_clken; // onchip_memory2_0_s1_translator:av_clken -> onchip_memory2_0:clken
wire onchip_memory2_0_s1_translator_avalon_anti_slave_0_write; // onchip_memory2_0_s1_translator:av_write -> onchip_memory2_0:write
wire [31:0] onchip_memory2_0_s1_translator_avalon_anti_slave_0_readdata; // onchip_memory2_0:readdata -> onchip_memory2_0_s1_translator:av_readdata
wire [3:0] onchip_memory2_0_s1_translator_avalon_anti_slave_0_byteenable; // onchip_memory2_0_s1_translator:av_byteenable -> onchip_memory2_0:byteenable
wire [15:0] sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_writedata; // sram_0_avalon_sram_slave_translator:av_writedata -> sram_0:writedata
wire [17:0] sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_address; // sram_0_avalon_sram_slave_translator:av_address -> sram_0:address
wire sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_write; // sram_0_avalon_sram_slave_translator:av_write -> sram_0:write
wire sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_read; // sram_0_avalon_sram_slave_translator:av_read -> sram_0:read
wire [15:0] sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdata; // sram_0:readdata -> sram_0_avalon_sram_slave_translator:av_readdata
wire sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid; // sram_0:readdatavalid -> sram_0_avalon_sram_slave_translator:av_readdatavalid
wire [1:0] sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable; // sram_0_avalon_sram_slave_translator:av_byteenable -> sram_0:byteenable
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest; // jtag_uart_0:av_waitrequest -> jtag_uart_0_avalon_jtag_slave_translator:av_waitrequest
wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata; // jtag_uart_0_avalon_jtag_slave_translator:av_writedata -> jtag_uart_0:av_writedata
wire [0:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address; // jtag_uart_0_avalon_jtag_slave_translator:av_address -> jtag_uart_0:av_address
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect; // jtag_uart_0_avalon_jtag_slave_translator:av_chipselect -> jtag_uart_0:av_chipselect
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write; // jtag_uart_0_avalon_jtag_slave_translator:av_write -> jtag_uart_0:av_write_n
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read; // jtag_uart_0_avalon_jtag_slave_translator:av_read -> jtag_uart_0:av_read_n
wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata; // jtag_uart_0:av_readdata -> jtag_uart_0_avalon_jtag_slave_translator:av_readdata
wire [0:0] sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address; // sysid_qsys_0_control_slave_translator:av_address -> sysid_qsys_0:address
wire [31:0] sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata; // sysid_qsys_0:readdata -> sysid_qsys_0_control_slave_translator:av_readdata
wire [31:0] green_leds_s1_translator_avalon_anti_slave_0_writedata; // green_leds_s1_translator:av_writedata -> green_leds:writedata
wire [1:0] green_leds_s1_translator_avalon_anti_slave_0_address; // green_leds_s1_translator:av_address -> green_leds:address
wire green_leds_s1_translator_avalon_anti_slave_0_chipselect; // green_leds_s1_translator:av_chipselect -> green_leds:chipselect
wire green_leds_s1_translator_avalon_anti_slave_0_write; // green_leds_s1_translator:av_write -> green_leds:write_n
wire [31:0] green_leds_s1_translator_avalon_anti_slave_0_readdata; // green_leds:readdata -> green_leds_s1_translator:av_readdata
wire [1:0] switches_s1_translator_avalon_anti_slave_0_address; // switches_s1_translator:av_address -> switches:address
wire [31:0] switches_s1_translator_avalon_anti_slave_0_readdata; // switches:readdata -> switches_s1_translator:av_readdata
wire [31:0] altpll_0_pll_slave_translator_avalon_anti_slave_0_writedata; // altpll_0_pll_slave_translator:av_writedata -> altpll_0:writedata
wire [1:0] altpll_0_pll_slave_translator_avalon_anti_slave_0_address; // altpll_0_pll_slave_translator:av_address -> altpll_0:address
wire altpll_0_pll_slave_translator_avalon_anti_slave_0_write; // altpll_0_pll_slave_translator:av_write -> altpll_0:write
wire altpll_0_pll_slave_translator_avalon_anti_slave_0_read; // altpll_0_pll_slave_translator:av_read -> altpll_0:read
wire [31:0] altpll_0_pll_slave_translator_avalon_anti_slave_0_readdata; // altpll_0:readdata -> altpll_0_pll_slave_translator:av_readdata
wire [15:0] timer_0_s1_translator_avalon_anti_slave_0_writedata; // timer_0_s1_translator:av_writedata -> timer_0:writedata
wire [2:0] timer_0_s1_translator_avalon_anti_slave_0_address; // timer_0_s1_translator:av_address -> timer_0:address
wire timer_0_s1_translator_avalon_anti_slave_0_chipselect; // timer_0_s1_translator:av_chipselect -> timer_0:chipselect
wire timer_0_s1_translator_avalon_anti_slave_0_write; // timer_0_s1_translator:av_write -> timer_0:write_n
wire [15:0] timer_0_s1_translator_avalon_anti_slave_0_readdata; // timer_0:readdata -> timer_0_s1_translator:av_readdata
wire [15:0] usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_writedata; // usb_0_avalon_usb_slave_translator:av_writedata -> usb_0:writedata
wire [1:0] usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_address; // usb_0_avalon_usb_slave_translator:av_address -> usb_0:address
wire usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_chipselect; // usb_0_avalon_usb_slave_translator:av_chipselect -> usb_0:chipselect
wire usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_write; // usb_0_avalon_usb_slave_translator:av_write -> usb_0:write
wire usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_read; // usb_0_avalon_usb_slave_translator:av_read -> usb_0:read
wire [15:0] usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_readdata; // usb_0:readdata -> usb_0_avalon_usb_slave_translator:av_readdata
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest; // nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_qsys_0_instruction_master_translator:uav_waitrequest
wire [2:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount; // nios2_qsys_0_instruction_master_translator:uav_burstcount -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata; // nios2_qsys_0_instruction_master_translator:uav_writedata -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_writedata
wire [24:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address; // nios2_qsys_0_instruction_master_translator:uav_address -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_address
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock; // nios2_qsys_0_instruction_master_translator:uav_lock -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_lock
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write; // nios2_qsys_0_instruction_master_translator:uav_write -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_write
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read; // nios2_qsys_0_instruction_master_translator:uav_read -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_read
wire [31:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata; // nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_qsys_0_instruction_master_translator:uav_readdata
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess; // nios2_qsys_0_instruction_master_translator:uav_debugaccess -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable; // nios2_qsys_0_instruction_master_translator:uav_byteenable -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_qsys_0_instruction_master_translator:uav_readdatavalid
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest; // nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_qsys_0_data_master_translator:uav_waitrequest
wire [2:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount; // nios2_qsys_0_data_master_translator:uav_burstcount -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_burstcount
wire [31:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata; // nios2_qsys_0_data_master_translator:uav_writedata -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_writedata
wire [24:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_address; // nios2_qsys_0_data_master_translator:uav_address -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_address
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock; // nios2_qsys_0_data_master_translator:uav_lock -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_lock
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_write; // nios2_qsys_0_data_master_translator:uav_write -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_write
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_read; // nios2_qsys_0_data_master_translator:uav_read -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_read
wire [31:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata; // nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_qsys_0_data_master_translator:uav_readdata
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess; // nios2_qsys_0_data_master_translator:uav_debugaccess -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_debugaccess
wire [3:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable; // nios2_qsys_0_data_master_translator:uav_byteenable -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_byteenable
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid; // nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_qsys_0_data_master_translator:uav_readdatavalid
wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest; // nios2_qsys_0_jtag_debug_module_translator:uav_waitrequest -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_burstcount -> nios2_qsys_0_jtag_debug_module_translator:uav_burstcount
wire [31:0] nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_writedata -> nios2_qsys_0_jtag_debug_module_translator:uav_writedata
wire [24:0] nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_address -> nios2_qsys_0_jtag_debug_module_translator:uav_address
wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_write -> nios2_qsys_0_jtag_debug_module_translator:uav_write
wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_lock -> nios2_qsys_0_jtag_debug_module_translator:uav_lock
wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_read -> nios2_qsys_0_jtag_debug_module_translator:uav_read
wire [31:0] nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata; // nios2_qsys_0_jtag_debug_module_translator:uav_readdata -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdata
wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // nios2_qsys_0_jtag_debug_module_translator:uav_readdatavalid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_debugaccess -> nios2_qsys_0_jtag_debug_module_translator:uav_debugaccess
wire [3:0] nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_byteenable -> nios2_qsys_0_jtag_debug_module_translator:uav_byteenable
wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [100:0] nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_ready
wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [100:0] nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_data
wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sdram_0_s1_translator:uav_waitrequest -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [1:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> sdram_0_s1_translator:uav_burstcount
wire [15:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> sdram_0_s1_translator:uav_writedata
wire [24:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> sdram_0_s1_translator:uav_address
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> sdram_0_s1_translator:uav_write
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> sdram_0_s1_translator:uav_lock
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> sdram_0_s1_translator:uav_read
wire [15:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // sdram_0_s1_translator:uav_readdata -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sdram_0_s1_translator:uav_readdatavalid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sdram_0_s1_translator:uav_debugaccess
wire [1:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> sdram_0_s1_translator:uav_byteenable
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [82:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [82:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
wire [17:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [17:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data; // sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // onchip_memory2_0_s1_translator:uav_waitrequest -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> onchip_memory2_0_s1_translator:uav_burstcount
wire [31:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> onchip_memory2_0_s1_translator:uav_writedata
wire [24:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_address; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> onchip_memory2_0_s1_translator:uav_address
wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_write; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> onchip_memory2_0_s1_translator:uav_write
wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_lock; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> onchip_memory2_0_s1_translator:uav_lock
wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_read; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> onchip_memory2_0_s1_translator:uav_read
wire [31:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // onchip_memory2_0_s1_translator:uav_readdata -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // onchip_memory2_0_s1_translator:uav_readdatavalid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> onchip_memory2_0_s1_translator:uav_debugaccess
wire [3:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> onchip_memory2_0_s1_translator:uav_byteenable
wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [100:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [100:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sram_0_avalon_sram_slave_translator:uav_waitrequest -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [1:0] sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> sram_0_avalon_sram_slave_translator:uav_burstcount
wire [15:0] sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> sram_0_avalon_sram_slave_translator:uav_writedata
wire [24:0] sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_address -> sram_0_avalon_sram_slave_translator:uav_address
wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_write -> sram_0_avalon_sram_slave_translator:uav_write
wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_lock -> sram_0_avalon_sram_slave_translator:uav_lock
wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_read -> sram_0_avalon_sram_slave_translator:uav_read
wire [15:0] sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // sram_0_avalon_sram_slave_translator:uav_readdata -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_readdata
wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sram_0_avalon_sram_slave_translator:uav_readdatavalid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sram_0_avalon_sram_slave_translator:uav_debugaccess
wire [1:0] sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> sram_0_avalon_sram_slave_translator:uav_byteenable
wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [82:0] sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [82:0] sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
wire [17:0] sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [17:0] sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // jtag_uart_0_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> jtag_uart_0_avalon_jtag_slave_translator:uav_burstcount
wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> jtag_uart_0_avalon_jtag_slave_translator:uav_writedata
wire [24:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_address -> jtag_uart_0_avalon_jtag_slave_translator:uav_address
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_write -> jtag_uart_0_avalon_jtag_slave_translator:uav_write
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_lock -> jtag_uart_0_avalon_jtag_slave_translator:uav_lock
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_read -> jtag_uart_0_avalon_jtag_slave_translator:uav_read
wire [31:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // jtag_uart_0_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdata
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // jtag_uart_0_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> jtag_uart_0_avalon_jtag_slave_translator:uav_debugaccess
wire [3:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> jtag_uart_0_avalon_jtag_slave_translator:uav_byteenable
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [100:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [100:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // sysid_qsys_0_control_slave_translator:uav_waitrequest -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> sysid_qsys_0_control_slave_translator:uav_burstcount
wire [31:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> sysid_qsys_0_control_slave_translator:uav_writedata
wire [24:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> sysid_qsys_0_control_slave_translator:uav_address
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> sysid_qsys_0_control_slave_translator:uav_write
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> sysid_qsys_0_control_slave_translator:uav_lock
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> sysid_qsys_0_control_slave_translator:uav_read
wire [31:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // sysid_qsys_0_control_slave_translator:uav_readdata -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // sysid_qsys_0_control_slave_translator:uav_readdatavalid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sysid_qsys_0_control_slave_translator:uav_debugaccess
wire [3:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> sysid_qsys_0_control_slave_translator:uav_byteenable
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [100:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [100:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire green_leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // green_leds_s1_translator:uav_waitrequest -> green_leds_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] green_leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // green_leds_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> green_leds_s1_translator:uav_burstcount
wire [31:0] green_leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // green_leds_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> green_leds_s1_translator:uav_writedata
wire [24:0] green_leds_s1_translator_avalon_universal_slave_0_agent_m0_address; // green_leds_s1_translator_avalon_universal_slave_0_agent:m0_address -> green_leds_s1_translator:uav_address
wire green_leds_s1_translator_avalon_universal_slave_0_agent_m0_write; // green_leds_s1_translator_avalon_universal_slave_0_agent:m0_write -> green_leds_s1_translator:uav_write
wire green_leds_s1_translator_avalon_universal_slave_0_agent_m0_lock; // green_leds_s1_translator_avalon_universal_slave_0_agent:m0_lock -> green_leds_s1_translator:uav_lock
wire green_leds_s1_translator_avalon_universal_slave_0_agent_m0_read; // green_leds_s1_translator_avalon_universal_slave_0_agent:m0_read -> green_leds_s1_translator:uav_read
wire [31:0] green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // green_leds_s1_translator:uav_readdata -> green_leds_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // green_leds_s1_translator:uav_readdatavalid -> green_leds_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire green_leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // green_leds_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> green_leds_s1_translator:uav_debugaccess
wire [3:0] green_leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // green_leds_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> green_leds_s1_translator:uav_byteenable
wire green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [100:0] green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [100:0] green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // switches_s1_translator:uav_waitrequest -> switches_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // switches_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> switches_s1_translator:uav_burstcount
wire [31:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // switches_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> switches_s1_translator:uav_writedata
wire [24:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_address; // switches_s1_translator_avalon_universal_slave_0_agent:m0_address -> switches_s1_translator:uav_address
wire switches_s1_translator_avalon_universal_slave_0_agent_m0_write; // switches_s1_translator_avalon_universal_slave_0_agent:m0_write -> switches_s1_translator:uav_write
wire switches_s1_translator_avalon_universal_slave_0_agent_m0_lock; // switches_s1_translator_avalon_universal_slave_0_agent:m0_lock -> switches_s1_translator:uav_lock
wire switches_s1_translator_avalon_universal_slave_0_agent_m0_read; // switches_s1_translator_avalon_universal_slave_0_agent:m0_read -> switches_s1_translator:uav_read
wire [31:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // switches_s1_translator:uav_readdata -> switches_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // switches_s1_translator:uav_readdatavalid -> switches_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // switches_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> switches_s1_translator:uav_debugaccess
wire [3:0] switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // switches_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> switches_s1_translator:uav_byteenable
wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [100:0] switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // switches_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [100:0] switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // altpll_0_pll_slave_translator:uav_waitrequest -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> altpll_0_pll_slave_translator:uav_burstcount
wire [31:0] altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> altpll_0_pll_slave_translator:uav_writedata
wire [24:0] altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_address; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_address -> altpll_0_pll_slave_translator:uav_address
wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_write; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_write -> altpll_0_pll_slave_translator:uav_write
wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_lock; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_lock -> altpll_0_pll_slave_translator:uav_lock
wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_read; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_read -> altpll_0_pll_slave_translator:uav_read
wire [31:0] altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // altpll_0_pll_slave_translator:uav_readdata -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_readdata
wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // altpll_0_pll_slave_translator:uav_readdatavalid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> altpll_0_pll_slave_translator:uav_debugaccess
wire [3:0] altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> altpll_0_pll_slave_translator:uav_byteenable
wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [100:0] altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [100:0] altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid
wire [33:0] altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data
wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready
wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest; // timer_0_s1_translator:uav_waitrequest -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> timer_0_s1_translator:uav_burstcount
wire [31:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> timer_0_s1_translator:uav_writedata
wire [24:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> timer_0_s1_translator:uav_address
wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> timer_0_s1_translator:uav_write
wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> timer_0_s1_translator:uav_lock
wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> timer_0_s1_translator:uav_read
wire [31:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata; // timer_0_s1_translator:uav_readdata -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata
wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // timer_0_s1_translator:uav_readdatavalid -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> timer_0_s1_translator:uav_debugaccess
wire [3:0] timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable; // timer_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> timer_0_s1_translator:uav_byteenable
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid; // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [100:0] timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data; // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready; // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [100:0] timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest; // usb_0_avalon_usb_slave_translator:uav_waitrequest -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest
wire [2:0] usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_burstcount; // usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> usb_0_avalon_usb_slave_translator:uav_burstcount
wire [31:0] usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_writedata; // usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> usb_0_avalon_usb_slave_translator:uav_writedata
wire [24:0] usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_address; // usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_address -> usb_0_avalon_usb_slave_translator:uav_address
wire usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_write; // usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_write -> usb_0_avalon_usb_slave_translator:uav_write
wire usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_lock; // usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_lock -> usb_0_avalon_usb_slave_translator:uav_lock
wire usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_read; // usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_read -> usb_0_avalon_usb_slave_translator:uav_read
wire [31:0] usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_readdata; // usb_0_avalon_usb_slave_translator:uav_readdata -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_readdata
wire usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid; // usb_0_avalon_usb_slave_translator:uav_readdatavalid -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid
wire usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess; // usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> usb_0_avalon_usb_slave_translator:uav_debugaccess
wire [3:0] usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_byteenable; // usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> usb_0_avalon_usb_slave_translator:uav_byteenable
wire usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket; // usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket
wire usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_valid; // usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid
wire usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket; // usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket
wire [100:0] usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_data; // usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data
wire usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_ready; // usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_source_ready
wire usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket; // usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket
wire usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid; // usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid
wire usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket; // usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket
wire [100:0] usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data; // usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_sink_data
wire usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready; // usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready
wire usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid; // usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid
wire [33:0] usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data; // usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data
wire usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready; // usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_valid; // nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket
wire [99:0] nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_data; // nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data
wire nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router:sink_ready -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_ready
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket; // nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_valid; // nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket; // nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket
wire [99:0] nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_data; // nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data
wire nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_ready; // addr_router_001:sink_ready -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_ready
wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket
wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid
wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket
wire [99:0] nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data
wire nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready; // id_router:sink_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_ready
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket
wire [81:0] sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data; // sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data
wire sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_001:sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket
wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_valid; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid
wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket
wire [99:0] onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_data; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data
wire onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_002:sink_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket
wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid
wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket
wire [81:0] sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data
wire sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_003:sink_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_ready
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket
wire [99:0] jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data
wire jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_004:sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_ready
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket
wire [99:0] sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data
wire sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_005:sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_ready
wire green_leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // green_leds_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_006:sink_endofpacket
wire green_leds_s1_translator_avalon_universal_slave_0_agent_rp_valid; // green_leds_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_006:sink_valid
wire green_leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // green_leds_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_006:sink_startofpacket
wire [99:0] green_leds_s1_translator_avalon_universal_slave_0_agent_rp_data; // green_leds_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_006:sink_data
wire green_leds_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_006:sink_ready -> green_leds_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_007:sink_endofpacket
wire switches_s1_translator_avalon_universal_slave_0_agent_rp_valid; // switches_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_007:sink_valid
wire switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // switches_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_007:sink_startofpacket
wire [99:0] switches_s1_translator_avalon_universal_slave_0_agent_rp_data; // switches_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_007:sink_data
wire switches_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_007:sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_008:sink_endofpacket
wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_valid; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_008:sink_valid
wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_008:sink_startofpacket
wire [99:0] altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_data; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_008:sink_data
wire altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_008:sink_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_ready
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_009:sink_endofpacket
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid; // timer_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_009:sink_valid
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket; // timer_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_009:sink_startofpacket
wire [99:0] timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data; // timer_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_009:sink_data
wire timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_009:sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rp_ready
wire usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket; // usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_010:sink_endofpacket
wire usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_valid; // usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_010:sink_valid
wire usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket; // usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_010:sink_startofpacket
wire [99:0] usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_data; // usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_010:sink_data
wire usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_ready; // id_router_010:sink_ready -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rp_ready
wire burst_adapter_source0_endofpacket; // burst_adapter:source0_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire burst_adapter_source0_valid; // burst_adapter:source0_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire burst_adapter_source0_startofpacket; // burst_adapter:source0_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [81:0] burst_adapter_source0_data; // burst_adapter:source0_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_data
wire burst_adapter_source0_ready; // sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter:source0_ready
wire [10:0] burst_adapter_source0_channel; // burst_adapter:source0_channel -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire burst_adapter_001_source0_endofpacket; // burst_adapter_001:source0_endofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire burst_adapter_001_source0_valid; // burst_adapter_001:source0_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_valid
wire burst_adapter_001_source0_startofpacket; // burst_adapter_001:source0_startofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [81:0] burst_adapter_001_source0_data; // burst_adapter_001:source0_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_data
wire burst_adapter_001_source0_ready; // sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter_001:source0_ready
wire [10:0] burst_adapter_001_source0_channel; // burst_adapter_001:source0_channel -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_channel
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [addr_router:reset, addr_router_001:reset, burst_adapter:reset, burst_adapter_001:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_mux:reset, cmd_xbar_mux_001:reset, cmd_xbar_mux_002:reset, cmd_xbar_mux_003:reset, crosser:in_reset, crosser_001:out_reset, green_leds:reset_n, green_leds_s1_translator:reset, green_leds_s1_translator_avalon_universal_slave_0_agent:reset, green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, id_router_006:reset, id_router_007:reset, id_router_009:reset, id_router_010:reset, irq_mapper:reset, jtag_uart_0:rst_n, jtag_uart_0_avalon_jtag_slave_translator:reset, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:reset, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, nios2_qsys_0:reset_n, nios2_qsys_0_data_master_translator:reset, nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:reset, nios2_qsys_0_instruction_master_translator:reset, nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:reset, nios2_qsys_0_jtag_debug_module_translator:reset, nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:reset, nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, onchip_memory2_0:reset, onchip_memory2_0_s1_translator:reset, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:reset, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_demux_006:reset, rsp_xbar_demux_007:reset, rsp_xbar_demux_009:reset, rsp_xbar_demux_010:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset, sdram_0:reset_n, sdram_0_s1_translator:reset, sdram_0_s1_translator_avalon_universal_slave_0_agent:reset, sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:reset, sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sram_0:reset, sram_0_avalon_sram_slave_translator:reset, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:reset, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:reset, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, switches:reset_n, switches_s1_translator:reset, switches_s1_translator_avalon_universal_slave_0_agent:reset, switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sysid_qsys_0:reset_n, sysid_qsys_0_control_slave_translator:reset, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:reset, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, timer_0:reset_n, timer_0_s1_translator:reset, timer_0_s1_translator_avalon_universal_slave_0_agent:reset, timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, usb_0:reset, usb_0_avalon_usb_slave_translator:reset, usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:reset, usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, width_adapter:reset, width_adapter_001:reset, width_adapter_002:reset, width_adapter_003:reset]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> onchip_memory2_0:reset_req
wire nios2_qsys_0_jtag_debug_module_reset_reset; // nios2_qsys_0:jtag_debug_module_resetrequest -> [rst_controller:reset_in1, rst_controller_001:reset_in1]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [altpll_0:reset, altpll_0_pll_slave_translator:reset, altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:reset, altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:reset, altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, crosser:out_reset, crosser_001:in_reset, id_router_008:reset, rsp_xbar_demux_008:reset]
wire cmd_xbar_demux_src0_endofpacket; // cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket
wire cmd_xbar_demux_src0_valid; // cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid
wire cmd_xbar_demux_src0_startofpacket; // cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket
wire [99:0] cmd_xbar_demux_src0_data; // cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data
wire [10:0] cmd_xbar_demux_src0_channel; // cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel
wire cmd_xbar_demux_src0_ready; // cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready
wire cmd_xbar_demux_src1_endofpacket; // cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket
wire cmd_xbar_demux_src1_valid; // cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid
wire cmd_xbar_demux_src1_startofpacket; // cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket
wire [99:0] cmd_xbar_demux_src1_data; // cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data
wire [10:0] cmd_xbar_demux_src1_channel; // cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel
wire cmd_xbar_demux_src1_ready; // cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready
wire cmd_xbar_demux_src2_endofpacket; // cmd_xbar_demux:src2_endofpacket -> cmd_xbar_mux_002:sink0_endofpacket
wire cmd_xbar_demux_src2_valid; // cmd_xbar_demux:src2_valid -> cmd_xbar_mux_002:sink0_valid
wire cmd_xbar_demux_src2_startofpacket; // cmd_xbar_demux:src2_startofpacket -> cmd_xbar_mux_002:sink0_startofpacket
wire [99:0] cmd_xbar_demux_src2_data; // cmd_xbar_demux:src2_data -> cmd_xbar_mux_002:sink0_data
wire [10:0] cmd_xbar_demux_src2_channel; // cmd_xbar_demux:src2_channel -> cmd_xbar_mux_002:sink0_channel
wire cmd_xbar_demux_src2_ready; // cmd_xbar_mux_002:sink0_ready -> cmd_xbar_demux:src2_ready
wire cmd_xbar_demux_src3_endofpacket; // cmd_xbar_demux:src3_endofpacket -> cmd_xbar_mux_003:sink0_endofpacket
wire cmd_xbar_demux_src3_valid; // cmd_xbar_demux:src3_valid -> cmd_xbar_mux_003:sink0_valid
wire cmd_xbar_demux_src3_startofpacket; // cmd_xbar_demux:src3_startofpacket -> cmd_xbar_mux_003:sink0_startofpacket
wire [99:0] cmd_xbar_demux_src3_data; // cmd_xbar_demux:src3_data -> cmd_xbar_mux_003:sink0_data
wire [10:0] cmd_xbar_demux_src3_channel; // cmd_xbar_demux:src3_channel -> cmd_xbar_mux_003:sink0_channel
wire cmd_xbar_demux_src3_ready; // cmd_xbar_mux_003:sink0_ready -> cmd_xbar_demux:src3_ready
wire cmd_xbar_demux_001_src0_endofpacket; // cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket
wire cmd_xbar_demux_001_src0_valid; // cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid
wire cmd_xbar_demux_001_src0_startofpacket; // cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket
wire [99:0] cmd_xbar_demux_001_src0_data; // cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data
wire [10:0] cmd_xbar_demux_001_src0_channel; // cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel
wire cmd_xbar_demux_001_src0_ready; // cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready
wire cmd_xbar_demux_001_src1_endofpacket; // cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket
wire cmd_xbar_demux_001_src1_valid; // cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_001:sink1_valid
wire cmd_xbar_demux_001_src1_startofpacket; // cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket
wire [99:0] cmd_xbar_demux_001_src1_data; // cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_001:sink1_data
wire [10:0] cmd_xbar_demux_001_src1_channel; // cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_001:sink1_channel
wire cmd_xbar_demux_001_src1_ready; // cmd_xbar_mux_001:sink1_ready -> cmd_xbar_demux_001:src1_ready
wire cmd_xbar_demux_001_src2_endofpacket; // cmd_xbar_demux_001:src2_endofpacket -> cmd_xbar_mux_002:sink1_endofpacket
wire cmd_xbar_demux_001_src2_valid; // cmd_xbar_demux_001:src2_valid -> cmd_xbar_mux_002:sink1_valid
wire cmd_xbar_demux_001_src2_startofpacket; // cmd_xbar_demux_001:src2_startofpacket -> cmd_xbar_mux_002:sink1_startofpacket
wire [99:0] cmd_xbar_demux_001_src2_data; // cmd_xbar_demux_001:src2_data -> cmd_xbar_mux_002:sink1_data
wire [10:0] cmd_xbar_demux_001_src2_channel; // cmd_xbar_demux_001:src2_channel -> cmd_xbar_mux_002:sink1_channel
wire cmd_xbar_demux_001_src2_ready; // cmd_xbar_mux_002:sink1_ready -> cmd_xbar_demux_001:src2_ready
wire cmd_xbar_demux_001_src3_endofpacket; // cmd_xbar_demux_001:src3_endofpacket -> cmd_xbar_mux_003:sink1_endofpacket
wire cmd_xbar_demux_001_src3_valid; // cmd_xbar_demux_001:src3_valid -> cmd_xbar_mux_003:sink1_valid
wire cmd_xbar_demux_001_src3_startofpacket; // cmd_xbar_demux_001:src3_startofpacket -> cmd_xbar_mux_003:sink1_startofpacket
wire [99:0] cmd_xbar_demux_001_src3_data; // cmd_xbar_demux_001:src3_data -> cmd_xbar_mux_003:sink1_data
wire [10:0] cmd_xbar_demux_001_src3_channel; // cmd_xbar_demux_001:src3_channel -> cmd_xbar_mux_003:sink1_channel
wire cmd_xbar_demux_001_src3_ready; // cmd_xbar_mux_003:sink1_ready -> cmd_xbar_demux_001:src3_ready
wire cmd_xbar_demux_001_src4_endofpacket; // cmd_xbar_demux_001:src4_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src4_valid; // cmd_xbar_demux_001:src4_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src4_startofpacket; // cmd_xbar_demux_001:src4_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [99:0] cmd_xbar_demux_001_src4_data; // cmd_xbar_demux_001:src4_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_data
wire [10:0] cmd_xbar_demux_001_src4_channel; // cmd_xbar_demux_001:src4_channel -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src5_endofpacket; // cmd_xbar_demux_001:src5_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src5_valid; // cmd_xbar_demux_001:src5_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src5_startofpacket; // cmd_xbar_demux_001:src5_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [99:0] cmd_xbar_demux_001_src5_data; // cmd_xbar_demux_001:src5_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_data
wire [10:0] cmd_xbar_demux_001_src5_channel; // cmd_xbar_demux_001:src5_channel -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src6_endofpacket; // cmd_xbar_demux_001:src6_endofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src6_valid; // cmd_xbar_demux_001:src6_valid -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src6_startofpacket; // cmd_xbar_demux_001:src6_startofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [99:0] cmd_xbar_demux_001_src6_data; // cmd_xbar_demux_001:src6_data -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_data
wire [10:0] cmd_xbar_demux_001_src6_channel; // cmd_xbar_demux_001:src6_channel -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src7_endofpacket; // cmd_xbar_demux_001:src7_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src7_valid; // cmd_xbar_demux_001:src7_valid -> switches_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src7_startofpacket; // cmd_xbar_demux_001:src7_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [99:0] cmd_xbar_demux_001_src7_data; // cmd_xbar_demux_001:src7_data -> switches_s1_translator_avalon_universal_slave_0_agent:cp_data
wire [10:0] cmd_xbar_demux_001_src7_channel; // cmd_xbar_demux_001:src7_channel -> switches_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src9_endofpacket; // cmd_xbar_demux_001:src9_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src9_valid; // cmd_xbar_demux_001:src9_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src9_startofpacket; // cmd_xbar_demux_001:src9_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [99:0] cmd_xbar_demux_001_src9_data; // cmd_xbar_demux_001:src9_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_data
wire [10:0] cmd_xbar_demux_001_src9_channel; // cmd_xbar_demux_001:src9_channel -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src10_endofpacket; // cmd_xbar_demux_001:src10_endofpacket -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_demux_001_src10_valid; // cmd_xbar_demux_001:src10_valid -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_demux_001_src10_startofpacket; // cmd_xbar_demux_001:src10_startofpacket -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [99:0] cmd_xbar_demux_001_src10_data; // cmd_xbar_demux_001:src10_data -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:cp_data
wire [10:0] cmd_xbar_demux_001_src10_channel; // cmd_xbar_demux_001:src10_channel -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:cp_channel
wire rsp_xbar_demux_src0_endofpacket; // rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket
wire rsp_xbar_demux_src0_valid; // rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid
wire rsp_xbar_demux_src0_startofpacket; // rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket
wire [99:0] rsp_xbar_demux_src0_data; // rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data
wire [10:0] rsp_xbar_demux_src0_channel; // rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel
wire rsp_xbar_demux_src0_ready; // rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready
wire rsp_xbar_demux_src1_endofpacket; // rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket
wire rsp_xbar_demux_src1_valid; // rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid
wire rsp_xbar_demux_src1_startofpacket; // rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket
wire [99:0] rsp_xbar_demux_src1_data; // rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data
wire [10:0] rsp_xbar_demux_src1_channel; // rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel
wire rsp_xbar_demux_src1_ready; // rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready
wire rsp_xbar_demux_001_src0_endofpacket; // rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket
wire rsp_xbar_demux_001_src0_valid; // rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid
wire rsp_xbar_demux_001_src0_startofpacket; // rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket
wire [99:0] rsp_xbar_demux_001_src0_data; // rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data
wire [10:0] rsp_xbar_demux_001_src0_channel; // rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel
wire rsp_xbar_demux_001_src0_ready; // rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready
wire rsp_xbar_demux_001_src1_endofpacket; // rsp_xbar_demux_001:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket
wire rsp_xbar_demux_001_src1_valid; // rsp_xbar_demux_001:src1_valid -> rsp_xbar_mux_001:sink1_valid
wire rsp_xbar_demux_001_src1_startofpacket; // rsp_xbar_demux_001:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket
wire [99:0] rsp_xbar_demux_001_src1_data; // rsp_xbar_demux_001:src1_data -> rsp_xbar_mux_001:sink1_data
wire [10:0] rsp_xbar_demux_001_src1_channel; // rsp_xbar_demux_001:src1_channel -> rsp_xbar_mux_001:sink1_channel
wire rsp_xbar_demux_001_src1_ready; // rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_001:src1_ready
wire rsp_xbar_demux_002_src0_endofpacket; // rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux:sink2_endofpacket
wire rsp_xbar_demux_002_src0_valid; // rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux:sink2_valid
wire rsp_xbar_demux_002_src0_startofpacket; // rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux:sink2_startofpacket
wire [99:0] rsp_xbar_demux_002_src0_data; // rsp_xbar_demux_002:src0_data -> rsp_xbar_mux:sink2_data
wire [10:0] rsp_xbar_demux_002_src0_channel; // rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux:sink2_channel
wire rsp_xbar_demux_002_src0_ready; // rsp_xbar_mux:sink2_ready -> rsp_xbar_demux_002:src0_ready
wire rsp_xbar_demux_002_src1_endofpacket; // rsp_xbar_demux_002:src1_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket
wire rsp_xbar_demux_002_src1_valid; // rsp_xbar_demux_002:src1_valid -> rsp_xbar_mux_001:sink2_valid
wire rsp_xbar_demux_002_src1_startofpacket; // rsp_xbar_demux_002:src1_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket
wire [99:0] rsp_xbar_demux_002_src1_data; // rsp_xbar_demux_002:src1_data -> rsp_xbar_mux_001:sink2_data
wire [10:0] rsp_xbar_demux_002_src1_channel; // rsp_xbar_demux_002:src1_channel -> rsp_xbar_mux_001:sink2_channel
wire rsp_xbar_demux_002_src1_ready; // rsp_xbar_mux_001:sink2_ready -> rsp_xbar_demux_002:src1_ready
wire rsp_xbar_demux_003_src0_endofpacket; // rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux:sink3_endofpacket
wire rsp_xbar_demux_003_src0_valid; // rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux:sink3_valid
wire rsp_xbar_demux_003_src0_startofpacket; // rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux:sink3_startofpacket
wire [99:0] rsp_xbar_demux_003_src0_data; // rsp_xbar_demux_003:src0_data -> rsp_xbar_mux:sink3_data
wire [10:0] rsp_xbar_demux_003_src0_channel; // rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux:sink3_channel
wire rsp_xbar_demux_003_src0_ready; // rsp_xbar_mux:sink3_ready -> rsp_xbar_demux_003:src0_ready
wire rsp_xbar_demux_003_src1_endofpacket; // rsp_xbar_demux_003:src1_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket
wire rsp_xbar_demux_003_src1_valid; // rsp_xbar_demux_003:src1_valid -> rsp_xbar_mux_001:sink3_valid
wire rsp_xbar_demux_003_src1_startofpacket; // rsp_xbar_demux_003:src1_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket
wire [99:0] rsp_xbar_demux_003_src1_data; // rsp_xbar_demux_003:src1_data -> rsp_xbar_mux_001:sink3_data
wire [10:0] rsp_xbar_demux_003_src1_channel; // rsp_xbar_demux_003:src1_channel -> rsp_xbar_mux_001:sink3_channel
wire rsp_xbar_demux_003_src1_ready; // rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_003:src1_ready
wire rsp_xbar_demux_004_src0_endofpacket; // rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket
wire rsp_xbar_demux_004_src0_valid; // rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux_001:sink4_valid
wire rsp_xbar_demux_004_src0_startofpacket; // rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket
wire [99:0] rsp_xbar_demux_004_src0_data; // rsp_xbar_demux_004:src0_data -> rsp_xbar_mux_001:sink4_data
wire [10:0] rsp_xbar_demux_004_src0_channel; // rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux_001:sink4_channel
wire rsp_xbar_demux_004_src0_ready; // rsp_xbar_mux_001:sink4_ready -> rsp_xbar_demux_004:src0_ready
wire rsp_xbar_demux_005_src0_endofpacket; // rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket
wire rsp_xbar_demux_005_src0_valid; // rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink5_valid
wire rsp_xbar_demux_005_src0_startofpacket; // rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket
wire [99:0] rsp_xbar_demux_005_src0_data; // rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink5_data
wire [10:0] rsp_xbar_demux_005_src0_channel; // rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink5_channel
wire rsp_xbar_demux_005_src0_ready; // rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_005:src0_ready
wire rsp_xbar_demux_006_src0_endofpacket; // rsp_xbar_demux_006:src0_endofpacket -> rsp_xbar_mux_001:sink6_endofpacket
wire rsp_xbar_demux_006_src0_valid; // rsp_xbar_demux_006:src0_valid -> rsp_xbar_mux_001:sink6_valid
wire rsp_xbar_demux_006_src0_startofpacket; // rsp_xbar_demux_006:src0_startofpacket -> rsp_xbar_mux_001:sink6_startofpacket
wire [99:0] rsp_xbar_demux_006_src0_data; // rsp_xbar_demux_006:src0_data -> rsp_xbar_mux_001:sink6_data
wire [10:0] rsp_xbar_demux_006_src0_channel; // rsp_xbar_demux_006:src0_channel -> rsp_xbar_mux_001:sink6_channel
wire rsp_xbar_demux_006_src0_ready; // rsp_xbar_mux_001:sink6_ready -> rsp_xbar_demux_006:src0_ready
wire rsp_xbar_demux_007_src0_endofpacket; // rsp_xbar_demux_007:src0_endofpacket -> rsp_xbar_mux_001:sink7_endofpacket
wire rsp_xbar_demux_007_src0_valid; // rsp_xbar_demux_007:src0_valid -> rsp_xbar_mux_001:sink7_valid
wire rsp_xbar_demux_007_src0_startofpacket; // rsp_xbar_demux_007:src0_startofpacket -> rsp_xbar_mux_001:sink7_startofpacket
wire [99:0] rsp_xbar_demux_007_src0_data; // rsp_xbar_demux_007:src0_data -> rsp_xbar_mux_001:sink7_data
wire [10:0] rsp_xbar_demux_007_src0_channel; // rsp_xbar_demux_007:src0_channel -> rsp_xbar_mux_001:sink7_channel
wire rsp_xbar_demux_007_src0_ready; // rsp_xbar_mux_001:sink7_ready -> rsp_xbar_demux_007:src0_ready
wire rsp_xbar_demux_009_src0_endofpacket; // rsp_xbar_demux_009:src0_endofpacket -> rsp_xbar_mux_001:sink9_endofpacket
wire rsp_xbar_demux_009_src0_valid; // rsp_xbar_demux_009:src0_valid -> rsp_xbar_mux_001:sink9_valid
wire rsp_xbar_demux_009_src0_startofpacket; // rsp_xbar_demux_009:src0_startofpacket -> rsp_xbar_mux_001:sink9_startofpacket
wire [99:0] rsp_xbar_demux_009_src0_data; // rsp_xbar_demux_009:src0_data -> rsp_xbar_mux_001:sink9_data
wire [10:0] rsp_xbar_demux_009_src0_channel; // rsp_xbar_demux_009:src0_channel -> rsp_xbar_mux_001:sink9_channel
wire rsp_xbar_demux_009_src0_ready; // rsp_xbar_mux_001:sink9_ready -> rsp_xbar_demux_009:src0_ready
wire rsp_xbar_demux_010_src0_endofpacket; // rsp_xbar_demux_010:src0_endofpacket -> rsp_xbar_mux_001:sink10_endofpacket
wire rsp_xbar_demux_010_src0_valid; // rsp_xbar_demux_010:src0_valid -> rsp_xbar_mux_001:sink10_valid
wire rsp_xbar_demux_010_src0_startofpacket; // rsp_xbar_demux_010:src0_startofpacket -> rsp_xbar_mux_001:sink10_startofpacket
wire [99:0] rsp_xbar_demux_010_src0_data; // rsp_xbar_demux_010:src0_data -> rsp_xbar_mux_001:sink10_data
wire [10:0] rsp_xbar_demux_010_src0_channel; // rsp_xbar_demux_010:src0_channel -> rsp_xbar_mux_001:sink10_channel
wire rsp_xbar_demux_010_src0_ready; // rsp_xbar_mux_001:sink10_ready -> rsp_xbar_demux_010:src0_ready
wire addr_router_src_endofpacket; // addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket
wire addr_router_src_valid; // addr_router:src_valid -> cmd_xbar_demux:sink_valid
wire addr_router_src_startofpacket; // addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket
wire [99:0] addr_router_src_data; // addr_router:src_data -> cmd_xbar_demux:sink_data
wire [10:0] addr_router_src_channel; // addr_router:src_channel -> cmd_xbar_demux:sink_channel
wire addr_router_src_ready; // cmd_xbar_demux:sink_ready -> addr_router:src_ready
wire rsp_xbar_mux_src_endofpacket; // rsp_xbar_mux:src_endofpacket -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire rsp_xbar_mux_src_valid; // rsp_xbar_mux:src_valid -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_valid
wire rsp_xbar_mux_src_startofpacket; // rsp_xbar_mux:src_startofpacket -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [99:0] rsp_xbar_mux_src_data; // rsp_xbar_mux:src_data -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_data
wire [10:0] rsp_xbar_mux_src_channel; // rsp_xbar_mux:src_channel -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_channel
wire rsp_xbar_mux_src_ready; // nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux:src_ready
wire addr_router_001_src_endofpacket; // addr_router_001:src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket
wire addr_router_001_src_valid; // addr_router_001:src_valid -> cmd_xbar_demux_001:sink_valid
wire addr_router_001_src_startofpacket; // addr_router_001:src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket
wire [99:0] addr_router_001_src_data; // addr_router_001:src_data -> cmd_xbar_demux_001:sink_data
wire [10:0] addr_router_001_src_channel; // addr_router_001:src_channel -> cmd_xbar_demux_001:sink_channel
wire addr_router_001_src_ready; // cmd_xbar_demux_001:sink_ready -> addr_router_001:src_ready
wire rsp_xbar_mux_001_src_endofpacket; // rsp_xbar_mux_001:src_endofpacket -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket
wire rsp_xbar_mux_001_src_valid; // rsp_xbar_mux_001:src_valid -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_valid
wire rsp_xbar_mux_001_src_startofpacket; // rsp_xbar_mux_001:src_startofpacket -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket
wire [99:0] rsp_xbar_mux_001_src_data; // rsp_xbar_mux_001:src_data -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_data
wire [10:0] rsp_xbar_mux_001_src_channel; // rsp_xbar_mux_001:src_channel -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_channel
wire rsp_xbar_mux_001_src_ready; // nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux_001:src_ready
wire cmd_xbar_mux_src_endofpacket; // cmd_xbar_mux:src_endofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_src_valid; // cmd_xbar_mux:src_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_src_startofpacket; // cmd_xbar_mux:src_startofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [99:0] cmd_xbar_mux_src_data; // cmd_xbar_mux:src_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_data
wire [10:0] cmd_xbar_mux_src_channel; // cmd_xbar_mux:src_channel -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_src_ready; // nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready
wire id_router_src_endofpacket; // id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket
wire id_router_src_valid; // id_router:src_valid -> rsp_xbar_demux:sink_valid
wire id_router_src_startofpacket; // id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket
wire [99:0] id_router_src_data; // id_router:src_data -> rsp_xbar_demux:sink_data
wire [10:0] id_router_src_channel; // id_router:src_channel -> rsp_xbar_demux:sink_channel
wire id_router_src_ready; // rsp_xbar_demux:sink_ready -> id_router:src_ready
wire cmd_xbar_mux_002_src_endofpacket; // cmd_xbar_mux_002:src_endofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire cmd_xbar_mux_002_src_valid; // cmd_xbar_mux_002:src_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_valid
wire cmd_xbar_mux_002_src_startofpacket; // cmd_xbar_mux_002:src_startofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [99:0] cmd_xbar_mux_002_src_data; // cmd_xbar_mux_002:src_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_data
wire [10:0] cmd_xbar_mux_002_src_channel; // cmd_xbar_mux_002:src_channel -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_mux_002_src_ready; // onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_002:src_ready
wire id_router_002_src_endofpacket; // id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket
wire id_router_002_src_valid; // id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid
wire id_router_002_src_startofpacket; // id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket
wire [99:0] id_router_002_src_data; // id_router_002:src_data -> rsp_xbar_demux_002:sink_data
wire [10:0] id_router_002_src_channel; // id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel
wire id_router_002_src_ready; // rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready
wire cmd_xbar_demux_001_src4_ready; // jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src4_ready
wire id_router_004_src_endofpacket; // id_router_004:src_endofpacket -> rsp_xbar_demux_004:sink_endofpacket
wire id_router_004_src_valid; // id_router_004:src_valid -> rsp_xbar_demux_004:sink_valid
wire id_router_004_src_startofpacket; // id_router_004:src_startofpacket -> rsp_xbar_demux_004:sink_startofpacket
wire [99:0] id_router_004_src_data; // id_router_004:src_data -> rsp_xbar_demux_004:sink_data
wire [10:0] id_router_004_src_channel; // id_router_004:src_channel -> rsp_xbar_demux_004:sink_channel
wire id_router_004_src_ready; // rsp_xbar_demux_004:sink_ready -> id_router_004:src_ready
wire cmd_xbar_demux_001_src5_ready; // sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready
wire id_router_005_src_endofpacket; // id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket
wire id_router_005_src_valid; // id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid
wire id_router_005_src_startofpacket; // id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket
wire [99:0] id_router_005_src_data; // id_router_005:src_data -> rsp_xbar_demux_005:sink_data
wire [10:0] id_router_005_src_channel; // id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel
wire id_router_005_src_ready; // rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready
wire cmd_xbar_demux_001_src6_ready; // green_leds_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src6_ready
wire id_router_006_src_endofpacket; // id_router_006:src_endofpacket -> rsp_xbar_demux_006:sink_endofpacket
wire id_router_006_src_valid; // id_router_006:src_valid -> rsp_xbar_demux_006:sink_valid
wire id_router_006_src_startofpacket; // id_router_006:src_startofpacket -> rsp_xbar_demux_006:sink_startofpacket
wire [99:0] id_router_006_src_data; // id_router_006:src_data -> rsp_xbar_demux_006:sink_data
wire [10:0] id_router_006_src_channel; // id_router_006:src_channel -> rsp_xbar_demux_006:sink_channel
wire id_router_006_src_ready; // rsp_xbar_demux_006:sink_ready -> id_router_006:src_ready
wire cmd_xbar_demux_001_src7_ready; // switches_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src7_ready
wire id_router_007_src_endofpacket; // id_router_007:src_endofpacket -> rsp_xbar_demux_007:sink_endofpacket
wire id_router_007_src_valid; // id_router_007:src_valid -> rsp_xbar_demux_007:sink_valid
wire id_router_007_src_startofpacket; // id_router_007:src_startofpacket -> rsp_xbar_demux_007:sink_startofpacket
wire [99:0] id_router_007_src_data; // id_router_007:src_data -> rsp_xbar_demux_007:sink_data
wire [10:0] id_router_007_src_channel; // id_router_007:src_channel -> rsp_xbar_demux_007:sink_channel
wire id_router_007_src_ready; // rsp_xbar_demux_007:sink_ready -> id_router_007:src_ready
wire crosser_out_ready; // altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_ready -> crosser:out_ready
wire id_router_008_src_endofpacket; // id_router_008:src_endofpacket -> rsp_xbar_demux_008:sink_endofpacket
wire id_router_008_src_valid; // id_router_008:src_valid -> rsp_xbar_demux_008:sink_valid
wire id_router_008_src_startofpacket; // id_router_008:src_startofpacket -> rsp_xbar_demux_008:sink_startofpacket
wire [99:0] id_router_008_src_data; // id_router_008:src_data -> rsp_xbar_demux_008:sink_data
wire [10:0] id_router_008_src_channel; // id_router_008:src_channel -> rsp_xbar_demux_008:sink_channel
wire id_router_008_src_ready; // rsp_xbar_demux_008:sink_ready -> id_router_008:src_ready
wire cmd_xbar_demux_001_src9_ready; // timer_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src9_ready
wire id_router_009_src_endofpacket; // id_router_009:src_endofpacket -> rsp_xbar_demux_009:sink_endofpacket
wire id_router_009_src_valid; // id_router_009:src_valid -> rsp_xbar_demux_009:sink_valid
wire id_router_009_src_startofpacket; // id_router_009:src_startofpacket -> rsp_xbar_demux_009:sink_startofpacket
wire [99:0] id_router_009_src_data; // id_router_009:src_data -> rsp_xbar_demux_009:sink_data
wire [10:0] id_router_009_src_channel; // id_router_009:src_channel -> rsp_xbar_demux_009:sink_channel
wire id_router_009_src_ready; // rsp_xbar_demux_009:sink_ready -> id_router_009:src_ready
wire cmd_xbar_demux_001_src10_ready; // usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src10_ready
wire id_router_010_src_endofpacket; // id_router_010:src_endofpacket -> rsp_xbar_demux_010:sink_endofpacket
wire id_router_010_src_valid; // id_router_010:src_valid -> rsp_xbar_demux_010:sink_valid
wire id_router_010_src_startofpacket; // id_router_010:src_startofpacket -> rsp_xbar_demux_010:sink_startofpacket
wire [99:0] id_router_010_src_data; // id_router_010:src_data -> rsp_xbar_demux_010:sink_data
wire [10:0] id_router_010_src_channel; // id_router_010:src_channel -> rsp_xbar_demux_010:sink_channel
wire id_router_010_src_ready; // rsp_xbar_demux_010:sink_ready -> id_router_010:src_ready
wire cmd_xbar_mux_001_src_endofpacket; // cmd_xbar_mux_001:src_endofpacket -> width_adapter:in_endofpacket
wire cmd_xbar_mux_001_src_valid; // cmd_xbar_mux_001:src_valid -> width_adapter:in_valid
wire cmd_xbar_mux_001_src_startofpacket; // cmd_xbar_mux_001:src_startofpacket -> width_adapter:in_startofpacket
wire [99:0] cmd_xbar_mux_001_src_data; // cmd_xbar_mux_001:src_data -> width_adapter:in_data
wire [10:0] cmd_xbar_mux_001_src_channel; // cmd_xbar_mux_001:src_channel -> width_adapter:in_channel
wire cmd_xbar_mux_001_src_ready; // width_adapter:in_ready -> cmd_xbar_mux_001:src_ready
wire width_adapter_src_endofpacket; // width_adapter:out_endofpacket -> burst_adapter:sink0_endofpacket
wire width_adapter_src_valid; // width_adapter:out_valid -> burst_adapter:sink0_valid
wire width_adapter_src_startofpacket; // width_adapter:out_startofpacket -> burst_adapter:sink0_startofpacket
wire [81:0] width_adapter_src_data; // width_adapter:out_data -> burst_adapter:sink0_data
wire width_adapter_src_ready; // burst_adapter:sink0_ready -> width_adapter:out_ready
wire [10:0] width_adapter_src_channel; // width_adapter:out_channel -> burst_adapter:sink0_channel
wire id_router_001_src_endofpacket; // id_router_001:src_endofpacket -> width_adapter_001:in_endofpacket
wire id_router_001_src_valid; // id_router_001:src_valid -> width_adapter_001:in_valid
wire id_router_001_src_startofpacket; // id_router_001:src_startofpacket -> width_adapter_001:in_startofpacket
wire [81:0] id_router_001_src_data; // id_router_001:src_data -> width_adapter_001:in_data
wire [10:0] id_router_001_src_channel; // id_router_001:src_channel -> width_adapter_001:in_channel
wire id_router_001_src_ready; // width_adapter_001:in_ready -> id_router_001:src_ready
wire width_adapter_001_src_endofpacket; // width_adapter_001:out_endofpacket -> rsp_xbar_demux_001:sink_endofpacket
wire width_adapter_001_src_valid; // width_adapter_001:out_valid -> rsp_xbar_demux_001:sink_valid
wire width_adapter_001_src_startofpacket; // width_adapter_001:out_startofpacket -> rsp_xbar_demux_001:sink_startofpacket
wire [99:0] width_adapter_001_src_data; // width_adapter_001:out_data -> rsp_xbar_demux_001:sink_data
wire width_adapter_001_src_ready; // rsp_xbar_demux_001:sink_ready -> width_adapter_001:out_ready
wire [10:0] width_adapter_001_src_channel; // width_adapter_001:out_channel -> rsp_xbar_demux_001:sink_channel
wire cmd_xbar_mux_003_src_endofpacket; // cmd_xbar_mux_003:src_endofpacket -> width_adapter_002:in_endofpacket
wire cmd_xbar_mux_003_src_valid; // cmd_xbar_mux_003:src_valid -> width_adapter_002:in_valid
wire cmd_xbar_mux_003_src_startofpacket; // cmd_xbar_mux_003:src_startofpacket -> width_adapter_002:in_startofpacket
wire [99:0] cmd_xbar_mux_003_src_data; // cmd_xbar_mux_003:src_data -> width_adapter_002:in_data
wire [10:0] cmd_xbar_mux_003_src_channel; // cmd_xbar_mux_003:src_channel -> width_adapter_002:in_channel
wire cmd_xbar_mux_003_src_ready; // width_adapter_002:in_ready -> cmd_xbar_mux_003:src_ready
wire width_adapter_002_src_endofpacket; // width_adapter_002:out_endofpacket -> burst_adapter_001:sink0_endofpacket
wire width_adapter_002_src_valid; // width_adapter_002:out_valid -> burst_adapter_001:sink0_valid
wire width_adapter_002_src_startofpacket; // width_adapter_002:out_startofpacket -> burst_adapter_001:sink0_startofpacket
wire [81:0] width_adapter_002_src_data; // width_adapter_002:out_data -> burst_adapter_001:sink0_data
wire width_adapter_002_src_ready; // burst_adapter_001:sink0_ready -> width_adapter_002:out_ready
wire [10:0] width_adapter_002_src_channel; // width_adapter_002:out_channel -> burst_adapter_001:sink0_channel
wire id_router_003_src_endofpacket; // id_router_003:src_endofpacket -> width_adapter_003:in_endofpacket
wire id_router_003_src_valid; // id_router_003:src_valid -> width_adapter_003:in_valid
wire id_router_003_src_startofpacket; // id_router_003:src_startofpacket -> width_adapter_003:in_startofpacket
wire [81:0] id_router_003_src_data; // id_router_003:src_data -> width_adapter_003:in_data
wire [10:0] id_router_003_src_channel; // id_router_003:src_channel -> width_adapter_003:in_channel
wire id_router_003_src_ready; // width_adapter_003:in_ready -> id_router_003:src_ready
wire width_adapter_003_src_endofpacket; // width_adapter_003:out_endofpacket -> rsp_xbar_demux_003:sink_endofpacket
wire width_adapter_003_src_valid; // width_adapter_003:out_valid -> rsp_xbar_demux_003:sink_valid
wire width_adapter_003_src_startofpacket; // width_adapter_003:out_startofpacket -> rsp_xbar_demux_003:sink_startofpacket
wire [99:0] width_adapter_003_src_data; // width_adapter_003:out_data -> rsp_xbar_demux_003:sink_data
wire width_adapter_003_src_ready; // rsp_xbar_demux_003:sink_ready -> width_adapter_003:out_ready
wire [10:0] width_adapter_003_src_channel; // width_adapter_003:out_channel -> rsp_xbar_demux_003:sink_channel
wire crosser_out_endofpacket; // crosser:out_endofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket
wire crosser_out_valid; // crosser:out_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_valid
wire crosser_out_startofpacket; // crosser:out_startofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket
wire [99:0] crosser_out_data; // crosser:out_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_data
wire [10:0] crosser_out_channel; // crosser:out_channel -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_channel
wire cmd_xbar_demux_001_src8_endofpacket; // cmd_xbar_demux_001:src8_endofpacket -> crosser:in_endofpacket
wire cmd_xbar_demux_001_src8_valid; // cmd_xbar_demux_001:src8_valid -> crosser:in_valid
wire cmd_xbar_demux_001_src8_startofpacket; // cmd_xbar_demux_001:src8_startofpacket -> crosser:in_startofpacket
wire [99:0] cmd_xbar_demux_001_src8_data; // cmd_xbar_demux_001:src8_data -> crosser:in_data
wire [10:0] cmd_xbar_demux_001_src8_channel; // cmd_xbar_demux_001:src8_channel -> crosser:in_channel
wire cmd_xbar_demux_001_src8_ready; // crosser:in_ready -> cmd_xbar_demux_001:src8_ready
wire crosser_001_out_endofpacket; // crosser_001:out_endofpacket -> rsp_xbar_mux_001:sink8_endofpacket
wire crosser_001_out_valid; // crosser_001:out_valid -> rsp_xbar_mux_001:sink8_valid
wire crosser_001_out_startofpacket; // crosser_001:out_startofpacket -> rsp_xbar_mux_001:sink8_startofpacket
wire [99:0] crosser_001_out_data; // crosser_001:out_data -> rsp_xbar_mux_001:sink8_data
wire [10:0] crosser_001_out_channel; // crosser_001:out_channel -> rsp_xbar_mux_001:sink8_channel
wire crosser_001_out_ready; // rsp_xbar_mux_001:sink8_ready -> crosser_001:out_ready
wire rsp_xbar_demux_008_src0_endofpacket; // rsp_xbar_demux_008:src0_endofpacket -> crosser_001:in_endofpacket
wire rsp_xbar_demux_008_src0_valid; // rsp_xbar_demux_008:src0_valid -> crosser_001:in_valid
wire rsp_xbar_demux_008_src0_startofpacket; // rsp_xbar_demux_008:src0_startofpacket -> crosser_001:in_startofpacket
wire [99:0] rsp_xbar_demux_008_src0_data; // rsp_xbar_demux_008:src0_data -> crosser_001:in_data
wire [10:0] rsp_xbar_demux_008_src0_channel; // rsp_xbar_demux_008:src0_channel -> crosser_001:in_channel
wire rsp_xbar_demux_008_src0_ready; // crosser_001:in_ready -> rsp_xbar_demux_008:src0_ready
wire irq_mapper_receiver0_irq; // timer_0:irq -> irq_mapper:receiver0_irq
wire irq_mapper_receiver1_irq; // jtag_uart_0:av_irq -> irq_mapper:receiver1_irq
wire irq_mapper_receiver2_irq; // usb_0:irq -> irq_mapper:receiver2_irq
wire [31:0] nios2_qsys_0_d_irq_irq; // irq_mapper:sender_irq -> nios2_qsys_0:d_irq
niosII_system_nios2_qsys_0 nios2_qsys_0 (
.clk (altpll_0_c1_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset_n.reset_n
.d_address (nios2_qsys_0_data_master_address), // data_master.address
.d_byteenable (nios2_qsys_0_data_master_byteenable), // .byteenable
.d_read (nios2_qsys_0_data_master_read), // .read
.d_readdata (nios2_qsys_0_data_master_readdata), // .readdata
.d_waitrequest (nios2_qsys_0_data_master_waitrequest), // .waitrequest
.d_write (nios2_qsys_0_data_master_write), // .write
.d_writedata (nios2_qsys_0_data_master_writedata), // .writedata
.jtag_debug_module_debugaccess_to_roms (nios2_qsys_0_data_master_debugaccess), // .debugaccess
.i_address (nios2_qsys_0_instruction_master_address), // instruction_master.address
.i_read (nios2_qsys_0_instruction_master_read), // .read
.i_readdata (nios2_qsys_0_instruction_master_readdata), // .readdata
.i_waitrequest (nios2_qsys_0_instruction_master_waitrequest), // .waitrequest
.d_irq (nios2_qsys_0_d_irq_irq), // d_irq.irq
.jtag_debug_module_resetrequest (nios2_qsys_0_jtag_debug_module_reset_reset), // jtag_debug_module_reset.reset
.jtag_debug_module_address (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_address), // jtag_debug_module.address
.jtag_debug_module_byteenable (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable
.jtag_debug_module_debugaccess (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
.jtag_debug_module_read (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_read), // .read
.jtag_debug_module_readdata (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata
.jtag_debug_module_waitrequest (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.jtag_debug_module_write (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write
.jtag_debug_module_writedata (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata
.no_ci_readra () // custom_instruction_master.readra
);
niosII_system_onchip_memory2_0 onchip_memory2_0 (
.clk (altpll_0_c1_clk), // clk1.clk
.address (onchip_memory2_0_s1_translator_avalon_anti_slave_0_address), // s1.address
.clken (onchip_memory2_0_s1_translator_avalon_anti_slave_0_clken), // .clken
.chipselect (onchip_memory2_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.write (onchip_memory2_0_s1_translator_avalon_anti_slave_0_write), // .write
.readdata (onchip_memory2_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.writedata (onchip_memory2_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.byteenable (onchip_memory2_0_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset), // reset1.reset
.reset_req (rst_controller_reset_out_reset_req) // .reset_req
);
niosII_system_sysid_qsys_0 sysid_qsys_0 (
.clock (altpll_0_c1_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.readdata (sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata), // control_slave.readdata
.address (sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address) // .address
);
niosII_system_jtag_uart_0 jtag_uart_0 (
.clk (altpll_0_c1_clk), // clk.clk
.rst_n (~rst_controller_reset_out_reset), // reset.reset_n
.av_chipselect (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect), // avalon_jtag_slave.chipselect
.av_address (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address), // .address
.av_read_n (~jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read), // .read_n
.av_readdata (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_write_n (~jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write), // .write_n
.av_writedata (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_irq (irq_mapper_receiver1_irq) // irq.irq
);
niosII_system_green_leds green_leds (
.clk (altpll_0_c1_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (green_leds_s1_translator_avalon_anti_slave_0_address), // s1.address
.write_n (~green_leds_s1_translator_avalon_anti_slave_0_write), // .write_n
.writedata (green_leds_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.chipselect (green_leds_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.readdata (green_leds_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.out_port (green_leds_external_connection_export) // external_connection.export
);
niosII_system_switches switches (
.clk (altpll_0_c1_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (switches_s1_translator_avalon_anti_slave_0_address), // s1.address
.readdata (switches_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.in_port (switches_external_connection_export) // external_connection.export
);
niosII_system_altpll_0 altpll_0 (
.clk (clk_clk), // inclk_interface.clk
.reset (rst_controller_001_reset_out_reset), // inclk_interface_reset.reset
.read (altpll_0_pll_slave_translator_avalon_anti_slave_0_read), // pll_slave.read
.write (altpll_0_pll_slave_translator_avalon_anti_slave_0_write), // .write
.address (altpll_0_pll_slave_translator_avalon_anti_slave_0_address), // .address
.readdata (altpll_0_pll_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.writedata (altpll_0_pll_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.c0 (altpll_0_c0_clk), // c0.clk
.c1 (altpll_0_c1_clk), // c1.clk
.areset (), // areset_conduit.export
.locked (), // locked_conduit.export
.phasedone () // phasedone_conduit.export
);
niosII_system_sdram_0 sdram_0 (
.clk (altpll_0_c1_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.az_addr (sdram_0_s1_translator_avalon_anti_slave_0_address), // s1.address
.az_be_n (~sdram_0_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable_n
.az_cs (sdram_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.az_data (sdram_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.az_rd_n (~sdram_0_s1_translator_avalon_anti_slave_0_read), // .read_n
.az_wr_n (~sdram_0_s1_translator_avalon_anti_slave_0_write), // .write_n
.za_data (sdram_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.za_valid (sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid
.za_waitrequest (sdram_0_s1_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.zs_addr (sdram_0_wire_addr), // wire.export
.zs_ba (sdram_0_wire_ba), // .export
.zs_cas_n (sdram_0_wire_cas_n), // .export
.zs_cke (sdram_0_wire_cke), // .export
.zs_cs_n (sdram_0_wire_cs_n), // .export
.zs_dq (sdram_0_wire_dq), // .export
.zs_dqm (sdram_0_wire_dqm), // .export
.zs_ras_n (sdram_0_wire_ras_n), // .export
.zs_we_n (sdram_0_wire_we_n) // .export
);
niosII_system_sram_0 sram_0 (
.clk (altpll_0_c1_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.SRAM_DQ (sram_0_external_interface_DQ), // external_interface.export
.SRAM_ADDR (sram_0_external_interface_ADDR), // .export
.SRAM_LB_N (sram_0_external_interface_LB_N), // .export
.SRAM_UB_N (sram_0_external_interface_UB_N), // .export
.SRAM_CE_N (sram_0_external_interface_CE_N), // .export
.SRAM_OE_N (sram_0_external_interface_OE_N), // .export
.SRAM_WE_N (sram_0_external_interface_WE_N), // .export
.address (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_address), // avalon_sram_slave.address
.byteenable (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable), // .byteenable
.read (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_read), // .read
.write (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_write), // .write
.writedata (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.readdata (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.readdatavalid (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid) // .readdatavalid
);
niosII_system_timer_0 timer_0 (
.clk (altpll_0_c1_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (timer_0_s1_translator_avalon_anti_slave_0_address), // s1.address
.writedata (timer_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.readdata (timer_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.chipselect (timer_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.write_n (~timer_0_s1_translator_avalon_anti_slave_0_write), // .write_n
.irq (irq_mapper_receiver0_irq) // irq.irq
);
niosII_system_usb_0 usb_0 (
.clk (altpll_0_c1_clk), // clock_reset.clk
.reset (rst_controller_reset_out_reset), // clock_reset_reset.reset
.address (usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_address), // avalon_usb_slave.address
.chipselect (usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_chipselect), // .chipselect
.read (usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_read), // .read
.write (usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_write), // .write
.writedata (usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.readdata (usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.irq (irq_mapper_receiver2_irq), // interrupt.irq
.OTG_INT1 (usb_0_external_interface_INT1), // external_interface.export
.OTG_DATA (usb_0_external_interface_DATA), // .export
.OTG_RST_N (usb_0_external_interface_RST_N), // .export
.OTG_ADDR (usb_0_external_interface_ADDR), // .export
.OTG_CS_N (usb_0_external_interface_CS_N), // .export
.OTG_RD_N (usb_0_external_interface_RD_N), // .export
.OTG_WR_N (usb_0_external_interface_WR_N), // .export
.OTG_INT0 (usb_0_external_interface_INT0) // .export
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (25),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) nios2_qsys_0_instruction_master_translator (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_qsys_0_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_qsys_0_instruction_master_waitrequest), // .waitrequest
.av_read (nios2_qsys_0_instruction_master_read), // .read
.av_readdata (nios2_qsys_0_instruction_master_readdata), // .readdata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (25),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (1)
) nios2_qsys_0_data_master_translator (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (nios2_qsys_0_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_qsys_0_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_qsys_0_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_qsys_0_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_qsys_0_data_master_waitrequest), // .waitrequest
.av_byteenable (nios2_qsys_0_data_master_byteenable), // .byteenable
.av_read (nios2_qsys_0_data_master_read), // .read
.av_readdata (nios2_qsys_0_data_master_readdata), // .readdata
.av_write (nios2_qsys_0_data_master_write), // .write
.av_writedata (nios2_qsys_0_data_master_writedata), // .writedata
.av_debugaccess (nios2_qsys_0_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) nios2_qsys_0_jtag_debug_module_translator (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_write), // .write
.av_read (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_read), // .read
.av_readdata (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_waitrequest (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_debugaccess (nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (22),
.AV_DATA_W (16),
.UAV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (2),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sdram_0_s1_translator (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sdram_0_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sdram_0_s1_translator_avalon_anti_slave_0_write), // .write
.av_read (sdram_0_s1_translator_avalon_anti_slave_0_read), // .read
.av_readdata (sdram_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sdram_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (sdram_0_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_readdatavalid (sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid
.av_waitrequest (sdram_0_s1_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_chipselect (sdram_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (12),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) onchip_memory2_0_s1_translator (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (onchip_memory2_0_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (onchip_memory2_0_s1_translator_avalon_anti_slave_0_write), // .write
.av_readdata (onchip_memory2_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (onchip_memory2_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (onchip_memory2_0_s1_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_chipselect (onchip_memory2_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_clken (onchip_memory2_0_s1_translator_avalon_anti_slave_0_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (18),
.AV_DATA_W (16),
.UAV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (2),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sram_0_avalon_sram_slave_translator (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_write), // .write
.av_read (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_read), // .read
.av_readdata (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.av_byteenable (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable), // .byteenable
.av_readdatavalid (sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid), // .readdatavalid
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) jtag_uart_0_avalon_jtag_slave_translator (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write), // .write
.av_read (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read), // .read
.av_readdata (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.av_waitrequest (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest), // .waitrequest
.av_chipselect (jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sysid_qsys_0_control_slave_translator (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_readdata (sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) green_leds_s1_translator (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (green_leds_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (green_leds_s1_translator_avalon_anti_slave_0_write), // .write
.av_readdata (green_leds_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (green_leds_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.av_chipselect (green_leds_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) switches_s1_translator (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (switches_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (switches_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (switches_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (switches_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (switches_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_readdata (switches_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) altpll_0_pll_slave_translator (
.clk (clk_clk), // clk.clk
.reset (rst_controller_001_reset_out_reset), // reset.reset
.uav_address (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (altpll_0_pll_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (altpll_0_pll_slave_translator_avalon_anti_slave_0_write), // .write
.av_read (altpll_0_pll_slave_translator_avalon_anti_slave_0_read), // .read
.av_readdata (altpll_0_pll_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (altpll_0_pll_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (16),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) timer_0_s1_translator (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (timer_0_s1_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (timer_0_s1_translator_avalon_anti_slave_0_write), // .write
.av_readdata (timer_0_s1_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (timer_0_s1_translator_avalon_anti_slave_0_writedata), // .writedata
.av_chipselect (timer_0_s1_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (16),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (25),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (5),
.AV_WRITE_WAIT_CYCLES (5),
.AV_SETUP_WAIT_CYCLES (5),
.AV_DATA_HOLD_CYCLES (5)
) usb_0_avalon_usb_slave_translator (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.uav_address (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.uav_read (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.uav_write (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.uav_waitrequest (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.uav_readdata (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.uav_writedata (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.uav_lock (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.uav_debugaccess (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.av_address (usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_address), // avalon_anti_slave_0.address
.av_write (usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_write), // .write
.av_read (usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_read), // .read
.av_readdata (usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_readdata), // .readdata
.av_writedata (usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_writedata), // .writedata
.av_chipselect (usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (93),
.PKT_PROTECTION_L (91),
.PKT_BEGIN_BURST (80),
.PKT_BURSTWRAP_H (72),
.PKT_BURSTWRAP_L (70),
.PKT_BURST_SIZE_H (75),
.PKT_BURST_SIZE_L (73),
.PKT_BURST_TYPE_H (77),
.PKT_BURST_TYPE_L (76),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (67),
.PKT_ADDR_H (60),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (61),
.PKT_TRANS_POSTED (62),
.PKT_TRANS_WRITE (63),
.PKT_TRANS_READ (64),
.PKT_TRANS_LOCK (65),
.PKT_TRANS_EXCLUSIVE (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (85),
.PKT_SRC_ID_L (82),
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (86),
.PKT_THREAD_ID_H (90),
.PKT_THREAD_ID_L (90),
.PKT_CACHE_H (97),
.PKT_CACHE_L (94),
.PKT_DATA_SIDEBAND_H (79),
.PKT_DATA_SIDEBAND_L (79),
.PKT_QOS_H (81),
.PKT_QOS_L (81),
.PKT_ADDR_SIDEBAND_H (78),
.PKT_ADDR_SIDEBAND_L (78),
.PKT_RESPONSE_STATUS_H (99),
.PKT_RESPONSE_STATUS_L (98),
.ST_DATA_W (100),
.ST_CHANNEL_W (11),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (rsp_xbar_mux_src_valid), // rp.valid
.rp_data (rsp_xbar_mux_src_data), // .data
.rp_channel (rsp_xbar_mux_src_channel), // .channel
.rp_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_xbar_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (93),
.PKT_PROTECTION_L (91),
.PKT_BEGIN_BURST (80),
.PKT_BURSTWRAP_H (72),
.PKT_BURSTWRAP_L (70),
.PKT_BURST_SIZE_H (75),
.PKT_BURST_SIZE_L (73),
.PKT_BURST_TYPE_H (77),
.PKT_BURST_TYPE_L (76),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (67),
.PKT_ADDR_H (60),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (61),
.PKT_TRANS_POSTED (62),
.PKT_TRANS_WRITE (63),
.PKT_TRANS_READ (64),
.PKT_TRANS_LOCK (65),
.PKT_TRANS_EXCLUSIVE (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (85),
.PKT_SRC_ID_L (82),
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (86),
.PKT_THREAD_ID_H (90),
.PKT_THREAD_ID_L (90),
.PKT_CACHE_H (97),
.PKT_CACHE_L (94),
.PKT_DATA_SIDEBAND_H (79),
.PKT_DATA_SIDEBAND_L (79),
.PKT_QOS_H (81),
.PKT_QOS_L (81),
.PKT_ADDR_SIDEBAND_H (78),
.PKT_ADDR_SIDEBAND_L (78),
.PKT_RESPONSE_STATUS_H (99),
.PKT_RESPONSE_STATUS_L (98),
.ST_DATA_W (100),
.ST_CHANNEL_W (11),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.av_address (nios2_qsys_0_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_qsys_0_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_qsys_0_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_valid), // cp.valid
.cp_data (nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.cp_startofpacket (nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_ready), // .ready
.rp_valid (rsp_xbar_mux_001_src_valid), // rp.valid
.rp_data (rsp_xbar_mux_001_src_data), // .data
.rp_channel (rsp_xbar_mux_001_src_channel), // .channel
.rp_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
.rp_ready (rsp_xbar_mux_001_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (80),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (60),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (61),
.PKT_TRANS_POSTED (62),
.PKT_TRANS_WRITE (63),
.PKT_TRANS_READ (64),
.PKT_TRANS_LOCK (65),
.PKT_SRC_ID_H (85),
.PKT_SRC_ID_L (82),
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (86),
.PKT_BURSTWRAP_H (72),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (67),
.PKT_PROTECTION_H (93),
.PKT_PROTECTION_L (91),
.PKT_RESPONSE_STATUS_H (99),
.PKT_RESPONSE_STATUS_L (98),
.PKT_BURST_SIZE_H (75),
.PKT_BURST_SIZE_L (73),
.ST_CHANNEL_W (11),
.ST_DATA_W (100),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_src_valid), // .valid
.cp_data (cmd_xbar_mux_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_src_channel), // .channel
.rf_sink_ready (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (101),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (62),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_ADDR_H (42),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (43),
.PKT_TRANS_POSTED (44),
.PKT_TRANS_WRITE (45),
.PKT_TRANS_READ (46),
.PKT_TRANS_LOCK (47),
.PKT_SRC_ID_H (67),
.PKT_SRC_ID_L (64),
.PKT_DEST_ID_H (71),
.PKT_DEST_ID_L (68),
.PKT_BURSTWRAP_H (54),
.PKT_BURSTWRAP_L (52),
.PKT_BYTE_CNT_H (51),
.PKT_BYTE_CNT_L (49),
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (73),
.PKT_RESPONSE_STATUS_H (81),
.PKT_RESPONSE_STATUS_L (80),
.PKT_BURST_SIZE_H (57),
.PKT_BURST_SIZE_L (55),
.ST_CHANNEL_W (11),
.ST_DATA_W (82),
.AVS_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sdram_0_s1_translator_avalon_universal_slave_0_agent (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (burst_adapter_source0_ready), // cp.ready
.cp_valid (burst_adapter_source0_valid), // .valid
.cp_data (burst_adapter_source0_data), // .data
.cp_startofpacket (burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (burst_adapter_source0_channel), // .channel
.rf_sink_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (83),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (18),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // in.data
.in_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.in_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // .ready
.out_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // out.data
.out_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid
.out_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (80),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (60),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (61),
.PKT_TRANS_POSTED (62),
.PKT_TRANS_WRITE (63),
.PKT_TRANS_READ (64),
.PKT_TRANS_LOCK (65),
.PKT_SRC_ID_H (85),
.PKT_SRC_ID_L (82),
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (86),
.PKT_BURSTWRAP_H (72),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (67),
.PKT_PROTECTION_H (93),
.PKT_PROTECTION_L (91),
.PKT_RESPONSE_STATUS_H (99),
.PKT_RESPONSE_STATUS_L (98),
.PKT_BURST_SIZE_H (75),
.PKT_BURST_SIZE_L (73),
.ST_CHANNEL_W (11),
.ST_DATA_W (100),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_mux_002_src_ready), // cp.ready
.cp_valid (cmd_xbar_mux_002_src_valid), // .valid
.cp_data (cmd_xbar_mux_002_src_data), // .data
.cp_startofpacket (cmd_xbar_mux_002_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_mux_002_src_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_mux_002_src_channel), // .channel
.rf_sink_ready (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (101),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (62),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_ADDR_H (42),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (43),
.PKT_TRANS_POSTED (44),
.PKT_TRANS_WRITE (45),
.PKT_TRANS_READ (46),
.PKT_TRANS_LOCK (47),
.PKT_SRC_ID_H (67),
.PKT_SRC_ID_L (64),
.PKT_DEST_ID_H (71),
.PKT_DEST_ID_L (68),
.PKT_BURSTWRAP_H (54),
.PKT_BURSTWRAP_L (52),
.PKT_BYTE_CNT_H (51),
.PKT_BYTE_CNT_L (49),
.PKT_PROTECTION_H (75),
.PKT_PROTECTION_L (73),
.PKT_RESPONSE_STATUS_H (81),
.PKT_RESPONSE_STATUS_L (80),
.PKT_BURST_SIZE_H (57),
.PKT_BURST_SIZE_L (55),
.ST_CHANNEL_W (11),
.ST_DATA_W (82),
.AVS_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (burst_adapter_001_source0_ready), // cp.ready
.cp_valid (burst_adapter_001_source0_valid), // .valid
.cp_data (burst_adapter_001_source0_data), // .data
.cp_startofpacket (burst_adapter_001_source0_startofpacket), // .startofpacket
.cp_endofpacket (burst_adapter_001_source0_endofpacket), // .endofpacket
.cp_channel (burst_adapter_001_source0_channel), // .channel
.rf_sink_ready (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (83),
.FIFO_DEPTH (3),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (18),
.FIFO_DEPTH (3),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // in.data
.in_valid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.in_ready (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // .ready
.out_data (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // out.data
.out_valid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid
.out_ready (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (80),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (60),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (61),
.PKT_TRANS_POSTED (62),
.PKT_TRANS_WRITE (63),
.PKT_TRANS_READ (64),
.PKT_TRANS_LOCK (65),
.PKT_SRC_ID_H (85),
.PKT_SRC_ID_L (82),
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (86),
.PKT_BURSTWRAP_H (72),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (67),
.PKT_PROTECTION_H (93),
.PKT_PROTECTION_L (91),
.PKT_RESPONSE_STATUS_H (99),
.PKT_RESPONSE_STATUS_L (98),
.PKT_BURST_SIZE_H (75),
.PKT_BURST_SIZE_L (73),
.ST_CHANNEL_W (11),
.ST_DATA_W (100),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src4_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src4_valid), // .valid
.cp_data (cmd_xbar_demux_001_src4_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src4_channel), // .channel
.rf_sink_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (101),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (80),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (60),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (61),
.PKT_TRANS_POSTED (62),
.PKT_TRANS_WRITE (63),
.PKT_TRANS_READ (64),
.PKT_TRANS_LOCK (65),
.PKT_SRC_ID_H (85),
.PKT_SRC_ID_L (82),
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (86),
.PKT_BURSTWRAP_H (72),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (67),
.PKT_PROTECTION_H (93),
.PKT_PROTECTION_L (91),
.PKT_RESPONSE_STATUS_H (99),
.PKT_RESPONSE_STATUS_L (98),
.PKT_BURST_SIZE_H (75),
.PKT_BURST_SIZE_L (73),
.ST_CHANNEL_W (11),
.ST_DATA_W (100),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src5_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src5_valid), // .valid
.cp_data (cmd_xbar_demux_001_src5_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src5_channel), // .channel
.rf_sink_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (101),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (80),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (60),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (61),
.PKT_TRANS_POSTED (62),
.PKT_TRANS_WRITE (63),
.PKT_TRANS_READ (64),
.PKT_TRANS_LOCK (65),
.PKT_SRC_ID_H (85),
.PKT_SRC_ID_L (82),
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (86),
.PKT_BURSTWRAP_H (72),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (67),
.PKT_PROTECTION_H (93),
.PKT_PROTECTION_L (91),
.PKT_RESPONSE_STATUS_H (99),
.PKT_RESPONSE_STATUS_L (98),
.PKT_BURST_SIZE_H (75),
.PKT_BURST_SIZE_L (73),
.ST_CHANNEL_W (11),
.ST_DATA_W (100),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) green_leds_s1_translator_avalon_universal_slave_0_agent (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (green_leds_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (green_leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (green_leds_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (green_leds_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (green_leds_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (green_leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src6_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src6_valid), // .valid
.cp_data (cmd_xbar_demux_001_src6_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src6_channel), // .channel
.rf_sink_ready (green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (101),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (80),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (60),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (61),
.PKT_TRANS_POSTED (62),
.PKT_TRANS_WRITE (63),
.PKT_TRANS_READ (64),
.PKT_TRANS_LOCK (65),
.PKT_SRC_ID_H (85),
.PKT_SRC_ID_L (82),
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (86),
.PKT_BURSTWRAP_H (72),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (67),
.PKT_PROTECTION_H (93),
.PKT_PROTECTION_L (91),
.PKT_RESPONSE_STATUS_H (99),
.PKT_RESPONSE_STATUS_L (98),
.PKT_BURST_SIZE_H (75),
.PKT_BURST_SIZE_L (73),
.ST_CHANNEL_W (11),
.ST_DATA_W (100),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) switches_s1_translator_avalon_universal_slave_0_agent (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (switches_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (switches_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (switches_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (switches_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (switches_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (switches_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (switches_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src7_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src7_valid), // .valid
.cp_data (cmd_xbar_demux_001_src7_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src7_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src7_channel), // .channel
.rf_sink_ready (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (101),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (80),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (60),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (61),
.PKT_TRANS_POSTED (62),
.PKT_TRANS_WRITE (63),
.PKT_TRANS_READ (64),
.PKT_TRANS_LOCK (65),
.PKT_SRC_ID_H (85),
.PKT_SRC_ID_L (82),
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (86),
.PKT_BURSTWRAP_H (72),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (67),
.PKT_PROTECTION_H (93),
.PKT_PROTECTION_L (91),
.PKT_RESPONSE_STATUS_H (99),
.PKT_RESPONSE_STATUS_L (98),
.PKT_BURST_SIZE_H (75),
.PKT_BURST_SIZE_L (73),
.ST_CHANNEL_W (11),
.ST_DATA_W (100),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) altpll_0_pll_slave_translator_avalon_universal_slave_0_agent (
.clk (clk_clk), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.m0_address (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (crosser_out_ready), // cp.ready
.cp_valid (crosser_out_valid), // .valid
.cp_data (crosser_out_data), // .data
.cp_startofpacket (crosser_out_startofpacket), // .startofpacket
.cp_endofpacket (crosser_out_endofpacket), // .endofpacket
.cp_channel (crosser_out_channel), // .channel
.rf_sink_ready (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (101),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.in_data (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo (
.clk (clk_clk), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.in_data (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // in.data
.in_valid (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.in_ready (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // .ready
.out_data (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data), // out.data
.out_valid (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid), // .valid
.out_ready (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (80),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (60),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (61),
.PKT_TRANS_POSTED (62),
.PKT_TRANS_WRITE (63),
.PKT_TRANS_READ (64),
.PKT_TRANS_LOCK (65),
.PKT_SRC_ID_H (85),
.PKT_SRC_ID_L (82),
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (86),
.PKT_BURSTWRAP_H (72),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (67),
.PKT_PROTECTION_H (93),
.PKT_PROTECTION_L (91),
.PKT_RESPONSE_STATUS_H (99),
.PKT_RESPONSE_STATUS_L (98),
.PKT_BURST_SIZE_H (75),
.PKT_BURST_SIZE_L (73),
.ST_CHANNEL_W (11),
.ST_DATA_W (100),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) timer_0_s1_translator_avalon_universal_slave_0_agent (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src9_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src9_valid), // .valid
.cp_data (cmd_xbar_demux_001_src9_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src9_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src9_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src9_channel), // .channel
.rf_sink_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (101),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (80),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (60),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (61),
.PKT_TRANS_POSTED (62),
.PKT_TRANS_WRITE (63),
.PKT_TRANS_READ (64),
.PKT_TRANS_LOCK (65),
.PKT_SRC_ID_H (85),
.PKT_SRC_ID_L (82),
.PKT_DEST_ID_H (89),
.PKT_DEST_ID_L (86),
.PKT_BURSTWRAP_H (72),
.PKT_BURSTWRAP_L (70),
.PKT_BYTE_CNT_H (69),
.PKT_BYTE_CNT_L (67),
.PKT_PROTECTION_H (93),
.PKT_PROTECTION_L (91),
.PKT_RESPONSE_STATUS_H (99),
.PKT_RESPONSE_STATUS_L (98),
.PKT_BURST_SIZE_H (75),
.PKT_BURST_SIZE_L (73),
.ST_CHANNEL_W (11),
.ST_DATA_W (100),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.m0_address (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_address), // m0.address
.m0_burstcount (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_burstcount), // .burstcount
.m0_byteenable (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess), // .debugaccess
.m0_lock (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_lock), // .lock
.m0_readdata (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_readdata), // .readdata
.m0_readdatavalid (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_read), // .read
.m0_waitrequest (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_writedata), // .writedata
.m0_write (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_write), // .write
.rp_endofpacket (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_ready), // .ready
.rp_valid (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.rp_data (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.rp_startofpacket (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_xbar_demux_001_src10_ready), // cp.ready
.cp_valid (cmd_xbar_demux_001_src10_valid), // .valid
.cp_data (cmd_xbar_demux_001_src10_data), // .data
.cp_startofpacket (cmd_xbar_demux_001_src10_startofpacket), // .startofpacket
.cp_endofpacket (cmd_xbar_demux_001_src10_endofpacket), // .endofpacket
.cp_channel (cmd_xbar_demux_001_src10_channel), // .channel
.rf_sink_ready (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (101),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_data (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_data), // in.data
.in_valid (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_valid), // .valid
.in_ready (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_ready), // .ready
.in_startofpacket (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket), // .endofpacket
.out_data (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data), // out.data
.out_valid (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid), // .valid
.out_ready (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
niosII_system_addr_router addr_router (
.sink_ready (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_src_ready), // src.ready
.src_valid (addr_router_src_valid), // .valid
.src_data (addr_router_src_data), // .data
.src_channel (addr_router_src_channel), // .channel
.src_startofpacket (addr_router_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_src_endofpacket) // .endofpacket
);
niosII_system_addr_router_001 addr_router_001 (
.sink_ready (nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_ready), // sink.ready
.sink_valid (nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_valid), // .valid
.sink_data (nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_data), // .data
.sink_startofpacket (nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket), // .endofpacket
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (addr_router_001_src_ready), // src.ready
.src_valid (addr_router_001_src_valid), // .valid
.src_data (addr_router_001_src_data), // .data
.src_channel (addr_router_001_src_channel), // .channel
.src_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (addr_router_001_src_endofpacket) // .endofpacket
);
niosII_system_id_router id_router (
.sink_ready (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_src_ready), // src.ready
.src_valid (id_router_src_valid), // .valid
.src_data (id_router_src_data), // .data
.src_channel (id_router_src_channel), // .channel
.src_startofpacket (id_router_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_src_endofpacket) // .endofpacket
);
niosII_system_id_router_001 id_router_001 (
.sink_ready (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_001_src_ready), // src.ready
.src_valid (id_router_001_src_valid), // .valid
.src_data (id_router_001_src_data), // .data
.src_channel (id_router_001_src_channel), // .channel
.src_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_001_src_endofpacket) // .endofpacket
);
niosII_system_id_router id_router_002 (
.sink_ready (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_002_src_ready), // src.ready
.src_valid (id_router_002_src_valid), // .valid
.src_data (id_router_002_src_data), // .data
.src_channel (id_router_002_src_channel), // .channel
.src_startofpacket (id_router_002_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_002_src_endofpacket) // .endofpacket
);
niosII_system_id_router_001 id_router_003 (
.sink_ready (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_003_src_ready), // src.ready
.src_valid (id_router_003_src_valid), // .valid
.src_data (id_router_003_src_data), // .data
.src_channel (id_router_003_src_channel), // .channel
.src_startofpacket (id_router_003_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_003_src_endofpacket) // .endofpacket
);
niosII_system_id_router_004 id_router_004 (
.sink_ready (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_004_src_ready), // src.ready
.src_valid (id_router_004_src_valid), // .valid
.src_data (id_router_004_src_data), // .data
.src_channel (id_router_004_src_channel), // .channel
.src_startofpacket (id_router_004_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_004_src_endofpacket) // .endofpacket
);
niosII_system_id_router_004 id_router_005 (
.sink_ready (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_005_src_ready), // src.ready
.src_valid (id_router_005_src_valid), // .valid
.src_data (id_router_005_src_data), // .data
.src_channel (id_router_005_src_channel), // .channel
.src_startofpacket (id_router_005_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_005_src_endofpacket) // .endofpacket
);
niosII_system_id_router_004 id_router_006 (
.sink_ready (green_leds_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (green_leds_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (green_leds_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (green_leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (green_leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_006_src_ready), // src.ready
.src_valid (id_router_006_src_valid), // .valid
.src_data (id_router_006_src_data), // .data
.src_channel (id_router_006_src_channel), // .channel
.src_startofpacket (id_router_006_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_006_src_endofpacket) // .endofpacket
);
niosII_system_id_router_004 id_router_007 (
.sink_ready (switches_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (switches_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (switches_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_007_src_ready), // src.ready
.src_valid (id_router_007_src_valid), // .valid
.src_data (id_router_007_src_data), // .data
.src_channel (id_router_007_src_channel), // .channel
.src_startofpacket (id_router_007_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_007_src_endofpacket) // .endofpacket
);
niosII_system_id_router_004 id_router_008 (
.sink_ready (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.src_ready (id_router_008_src_ready), // src.ready
.src_valid (id_router_008_src_valid), // .valid
.src_data (id_router_008_src_data), // .data
.src_channel (id_router_008_src_channel), // .channel
.src_startofpacket (id_router_008_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_008_src_endofpacket) // .endofpacket
);
niosII_system_id_router_004 id_router_009 (
.sink_ready (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_009_src_ready), // src.ready
.src_valid (id_router_009_src_valid), // .valid
.src_data (id_router_009_src_data), // .data
.src_channel (id_router_009_src_channel), // .channel
.src_startofpacket (id_router_009_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_009_src_endofpacket) // .endofpacket
);
niosII_system_id_router_004 id_router_010 (
.sink_ready (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_ready), // sink.ready
.sink_valid (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_valid), // .valid
.sink_data (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_data), // .data
.sink_startofpacket (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (id_router_010_src_ready), // src.ready
.src_valid (id_router_010_src_valid), // .valid
.src_data (id_router_010_src_data), // .data
.src_channel (id_router_010_src_channel), // .channel
.src_startofpacket (id_router_010_src_startofpacket), // .startofpacket
.src_endofpacket (id_router_010_src_endofpacket) // .endofpacket
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (42),
.PKT_ADDR_L (18),
.PKT_BEGIN_BURST (62),
.PKT_BYTE_CNT_H (51),
.PKT_BYTE_CNT_L (49),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_BURST_SIZE_H (57),
.PKT_BURST_SIZE_L (55),
.PKT_BURST_TYPE_H (59),
.PKT_BURST_TYPE_L (58),
.PKT_BURSTWRAP_H (54),
.PKT_BURSTWRAP_L (52),
.PKT_TRANS_COMPRESSED_READ (43),
.PKT_TRANS_WRITE (45),
.PKT_TRANS_READ (46),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (82),
.ST_CHANNEL_W (11),
.OUT_BYTE_CNT_H (50),
.OUT_BURSTWRAP_H (54),
.COMPRESSED_READ_SUPPORT (0),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (3),
.BURSTWRAP_CONST_VALUE (3)
) burst_adapter (
.clk (altpll_0_c1_clk), // cr0.clk
.reset (rst_controller_reset_out_reset), // cr0_reset.reset
.sink0_valid (width_adapter_src_valid), // sink0.valid
.sink0_data (width_adapter_src_data), // .data
.sink0_channel (width_adapter_src_channel), // .channel
.sink0_startofpacket (width_adapter_src_startofpacket), // .startofpacket
.sink0_endofpacket (width_adapter_src_endofpacket), // .endofpacket
.sink0_ready (width_adapter_src_ready), // .ready
.source0_valid (burst_adapter_source0_valid), // source0.valid
.source0_data (burst_adapter_source0_data), // .data
.source0_channel (burst_adapter_source0_channel), // .channel
.source0_startofpacket (burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (42),
.PKT_ADDR_L (18),
.PKT_BEGIN_BURST (62),
.PKT_BYTE_CNT_H (51),
.PKT_BYTE_CNT_L (49),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_BURST_SIZE_H (57),
.PKT_BURST_SIZE_L (55),
.PKT_BURST_TYPE_H (59),
.PKT_BURST_TYPE_L (58),
.PKT_BURSTWRAP_H (54),
.PKT_BURSTWRAP_L (52),
.PKT_TRANS_COMPRESSED_READ (43),
.PKT_TRANS_WRITE (45),
.PKT_TRANS_READ (46),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (82),
.ST_CHANNEL_W (11),
.OUT_BYTE_CNT_H (50),
.OUT_BURSTWRAP_H (54),
.COMPRESSED_READ_SUPPORT (0),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (3),
.BURSTWRAP_CONST_VALUE (3)
) burst_adapter_001 (
.clk (altpll_0_c1_clk), // cr0.clk
.reset (rst_controller_reset_out_reset), // cr0_reset.reset
.sink0_valid (width_adapter_002_src_valid), // sink0.valid
.sink0_data (width_adapter_002_src_data), // .data
.sink0_channel (width_adapter_002_src_channel), // .channel
.sink0_startofpacket (width_adapter_002_src_startofpacket), // .startofpacket
.sink0_endofpacket (width_adapter_002_src_endofpacket), // .endofpacket
.sink0_ready (width_adapter_002_src_ready), // .ready
.source0_valid (burst_adapter_001_source0_valid), // source0.valid
.source0_data (burst_adapter_001_source0_data), // .data
.source0_channel (burst_adapter_001_source0_channel), // .channel
.source0_startofpacket (burst_adapter_001_source0_startofpacket), // .startofpacket
.source0_endofpacket (burst_adapter_001_source0_endofpacket), // .endofpacket
.source0_ready (burst_adapter_001_source0_ready) // .ready
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (nios2_qsys_0_jtag_debug_module_reset_reset), // reset_in1.reset
.clk (altpll_0_c1_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.reset_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0)
) rst_controller_001 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (nios2_qsys_0_jtag_debug_module_reset_reset), // reset_in1.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_in15 (1'b0) // (terminated)
);
niosII_system_cmd_xbar_demux cmd_xbar_demux (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (addr_router_src_ready), // sink.ready
.sink_channel (addr_router_src_channel), // .channel
.sink_data (addr_router_src_data), // .data
.sink_startofpacket (addr_router_src_startofpacket), // .startofpacket
.sink_endofpacket (addr_router_src_endofpacket), // .endofpacket
.sink_valid (addr_router_src_valid), // .valid
.src0_ready (cmd_xbar_demux_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_src0_valid), // .valid
.src0_data (cmd_xbar_demux_src0_data), // .data
.src0_channel (cmd_xbar_demux_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_src1_valid), // .valid
.src1_data (cmd_xbar_demux_src1_data), // .data
.src1_channel (cmd_xbar_demux_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_xbar_demux_src2_ready), // src2.ready
.src2_valid (cmd_xbar_demux_src2_valid), // .valid
.src2_data (cmd_xbar_demux_src2_data), // .data
.src2_channel (cmd_xbar_demux_src2_channel), // .channel
.src2_startofpacket (cmd_xbar_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_xbar_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_xbar_demux_src3_ready), // src3.ready
.src3_valid (cmd_xbar_demux_src3_valid), // .valid
.src3_data (cmd_xbar_demux_src3_data), // .data
.src3_channel (cmd_xbar_demux_src3_channel), // .channel
.src3_startofpacket (cmd_xbar_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_xbar_demux_src3_endofpacket) // .endofpacket
);
niosII_system_cmd_xbar_demux_001 cmd_xbar_demux_001 (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (addr_router_001_src_ready), // sink.ready
.sink_channel (addr_router_001_src_channel), // .channel
.sink_data (addr_router_001_src_data), // .data
.sink_startofpacket (addr_router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (addr_router_001_src_endofpacket), // .endofpacket
.sink_valid (addr_router_001_src_valid), // .valid
.src0_ready (cmd_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_xbar_demux_001_src0_valid), // .valid
.src0_data (cmd_xbar_demux_001_src0_data), // .data
.src0_channel (cmd_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_xbar_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_xbar_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_xbar_demux_001_src1_valid), // .valid
.src1_data (cmd_xbar_demux_001_src1_data), // .data
.src1_channel (cmd_xbar_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_xbar_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_xbar_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_xbar_demux_001_src2_valid), // .valid
.src2_data (cmd_xbar_demux_001_src2_data), // .data
.src2_channel (cmd_xbar_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_xbar_demux_001_src2_endofpacket), // .endofpacket
.src3_ready (cmd_xbar_demux_001_src3_ready), // src3.ready
.src3_valid (cmd_xbar_demux_001_src3_valid), // .valid
.src3_data (cmd_xbar_demux_001_src3_data), // .data
.src3_channel (cmd_xbar_demux_001_src3_channel), // .channel
.src3_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_xbar_demux_001_src3_endofpacket), // .endofpacket
.src4_ready (cmd_xbar_demux_001_src4_ready), // src4.ready
.src4_valid (cmd_xbar_demux_001_src4_valid), // .valid
.src4_data (cmd_xbar_demux_001_src4_data), // .data
.src4_channel (cmd_xbar_demux_001_src4_channel), // .channel
.src4_startofpacket (cmd_xbar_demux_001_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_xbar_demux_001_src4_endofpacket), // .endofpacket
.src5_ready (cmd_xbar_demux_001_src5_ready), // src5.ready
.src5_valid (cmd_xbar_demux_001_src5_valid), // .valid
.src5_data (cmd_xbar_demux_001_src5_data), // .data
.src5_channel (cmd_xbar_demux_001_src5_channel), // .channel
.src5_startofpacket (cmd_xbar_demux_001_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_xbar_demux_001_src5_endofpacket), // .endofpacket
.src6_ready (cmd_xbar_demux_001_src6_ready), // src6.ready
.src6_valid (cmd_xbar_demux_001_src6_valid), // .valid
.src6_data (cmd_xbar_demux_001_src6_data), // .data
.src6_channel (cmd_xbar_demux_001_src6_channel), // .channel
.src6_startofpacket (cmd_xbar_demux_001_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_xbar_demux_001_src6_endofpacket), // .endofpacket
.src7_ready (cmd_xbar_demux_001_src7_ready), // src7.ready
.src7_valid (cmd_xbar_demux_001_src7_valid), // .valid
.src7_data (cmd_xbar_demux_001_src7_data), // .data
.src7_channel (cmd_xbar_demux_001_src7_channel), // .channel
.src7_startofpacket (cmd_xbar_demux_001_src7_startofpacket), // .startofpacket
.src7_endofpacket (cmd_xbar_demux_001_src7_endofpacket), // .endofpacket
.src8_ready (cmd_xbar_demux_001_src8_ready), // src8.ready
.src8_valid (cmd_xbar_demux_001_src8_valid), // .valid
.src8_data (cmd_xbar_demux_001_src8_data), // .data
.src8_channel (cmd_xbar_demux_001_src8_channel), // .channel
.src8_startofpacket (cmd_xbar_demux_001_src8_startofpacket), // .startofpacket
.src8_endofpacket (cmd_xbar_demux_001_src8_endofpacket), // .endofpacket
.src9_ready (cmd_xbar_demux_001_src9_ready), // src9.ready
.src9_valid (cmd_xbar_demux_001_src9_valid), // .valid
.src9_data (cmd_xbar_demux_001_src9_data), // .data
.src9_channel (cmd_xbar_demux_001_src9_channel), // .channel
.src9_startofpacket (cmd_xbar_demux_001_src9_startofpacket), // .startofpacket
.src9_endofpacket (cmd_xbar_demux_001_src9_endofpacket), // .endofpacket
.src10_ready (cmd_xbar_demux_001_src10_ready), // src10.ready
.src10_valid (cmd_xbar_demux_001_src10_valid), // .valid
.src10_data (cmd_xbar_demux_001_src10_data), // .data
.src10_channel (cmd_xbar_demux_001_src10_channel), // .channel
.src10_startofpacket (cmd_xbar_demux_001_src10_startofpacket), // .startofpacket
.src10_endofpacket (cmd_xbar_demux_001_src10_endofpacket) // .endofpacket
);
niosII_system_cmd_xbar_mux cmd_xbar_mux (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_src_ready), // src.ready
.src_valid (cmd_xbar_mux_src_valid), // .valid
.src_data (cmd_xbar_mux_src_data), // .data
.src_channel (cmd_xbar_mux_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src0_valid), // .valid
.sink0_channel (cmd_xbar_demux_src0_channel), // .channel
.sink0_data (cmd_xbar_demux_src0_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src0_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src0_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src0_endofpacket) // .endofpacket
);
niosII_system_cmd_xbar_mux cmd_xbar_mux_001 (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_001_src_ready), // src.ready
.src_valid (cmd_xbar_mux_001_src_valid), // .valid
.src_data (cmd_xbar_mux_001_src_data), // .data
.src_channel (cmd_xbar_mux_001_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src1_valid), // .valid
.sink0_channel (cmd_xbar_demux_src1_channel), // .channel
.sink0_data (cmd_xbar_demux_src1_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src1_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src1_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src1_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src1_endofpacket) // .endofpacket
);
niosII_system_cmd_xbar_mux cmd_xbar_mux_002 (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_002_src_ready), // src.ready
.src_valid (cmd_xbar_mux_002_src_valid), // .valid
.src_data (cmd_xbar_mux_002_src_data), // .data
.src_channel (cmd_xbar_mux_002_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src2_valid), // .valid
.sink0_channel (cmd_xbar_demux_src2_channel), // .channel
.sink0_data (cmd_xbar_demux_src2_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src2_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src2_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src2_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src2_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src2_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src2_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src2_endofpacket) // .endofpacket
);
niosII_system_cmd_xbar_mux cmd_xbar_mux_003 (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (cmd_xbar_mux_003_src_ready), // src.ready
.src_valid (cmd_xbar_mux_003_src_valid), // .valid
.src_data (cmd_xbar_mux_003_src_data), // .data
.src_channel (cmd_xbar_mux_003_src_channel), // .channel
.src_startofpacket (cmd_xbar_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_xbar_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_xbar_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_xbar_demux_src3_valid), // .valid
.sink0_channel (cmd_xbar_demux_src3_channel), // .channel
.sink0_data (cmd_xbar_demux_src3_data), // .data
.sink0_startofpacket (cmd_xbar_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_xbar_demux_src3_endofpacket), // .endofpacket
.sink1_ready (cmd_xbar_demux_001_src3_ready), // sink1.ready
.sink1_valid (cmd_xbar_demux_001_src3_valid), // .valid
.sink1_channel (cmd_xbar_demux_001_src3_channel), // .channel
.sink1_data (cmd_xbar_demux_001_src3_data), // .data
.sink1_startofpacket (cmd_xbar_demux_001_src3_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_xbar_demux_001_src3_endofpacket) // .endofpacket
);
niosII_system_rsp_xbar_demux rsp_xbar_demux (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_src_ready), // sink.ready
.sink_channel (id_router_src_channel), // .channel
.sink_data (id_router_src_data), // .data
.sink_startofpacket (id_router_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_src_endofpacket), // .endofpacket
.sink_valid (id_router_src_valid), // .valid
.src0_ready (rsp_xbar_demux_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_src0_valid), // .valid
.src0_data (rsp_xbar_demux_src0_data), // .data
.src0_channel (rsp_xbar_demux_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_src1_valid), // .valid
.src1_data (rsp_xbar_demux_src1_data), // .data
.src1_channel (rsp_xbar_demux_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_src1_endofpacket) // .endofpacket
);
niosII_system_rsp_xbar_demux rsp_xbar_demux_001 (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (width_adapter_001_src_ready), // sink.ready
.sink_channel (width_adapter_001_src_channel), // .channel
.sink_data (width_adapter_001_src_data), // .data
.sink_startofpacket (width_adapter_001_src_startofpacket), // .startofpacket
.sink_endofpacket (width_adapter_001_src_endofpacket), // .endofpacket
.sink_valid (width_adapter_001_src_valid), // .valid
.src0_ready (rsp_xbar_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_001_src0_valid), // .valid
.src0_data (rsp_xbar_demux_001_src0_data), // .data
.src0_channel (rsp_xbar_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_001_src1_valid), // .valid
.src1_data (rsp_xbar_demux_001_src1_data), // .data
.src1_channel (rsp_xbar_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_001_src1_endofpacket) // .endofpacket
);
niosII_system_rsp_xbar_demux rsp_xbar_demux_002 (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_002_src_ready), // sink.ready
.sink_channel (id_router_002_src_channel), // .channel
.sink_data (id_router_002_src_data), // .data
.sink_startofpacket (id_router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_002_src_endofpacket), // .endofpacket
.sink_valid (id_router_002_src_valid), // .valid
.src0_ready (rsp_xbar_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_002_src0_valid), // .valid
.src0_data (rsp_xbar_demux_002_src0_data), // .data
.src0_channel (rsp_xbar_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_002_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_002_src1_valid), // .valid
.src1_data (rsp_xbar_demux_002_src1_data), // .data
.src1_channel (rsp_xbar_demux_002_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_002_src1_endofpacket) // .endofpacket
);
niosII_system_rsp_xbar_demux rsp_xbar_demux_003 (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (width_adapter_003_src_ready), // sink.ready
.sink_channel (width_adapter_003_src_channel), // .channel
.sink_data (width_adapter_003_src_data), // .data
.sink_startofpacket (width_adapter_003_src_startofpacket), // .startofpacket
.sink_endofpacket (width_adapter_003_src_endofpacket), // .endofpacket
.sink_valid (width_adapter_003_src_valid), // .valid
.src0_ready (rsp_xbar_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_003_src0_valid), // .valid
.src0_data (rsp_xbar_demux_003_src0_data), // .data
.src0_channel (rsp_xbar_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_003_src0_endofpacket), // .endofpacket
.src1_ready (rsp_xbar_demux_003_src1_ready), // src1.ready
.src1_valid (rsp_xbar_demux_003_src1_valid), // .valid
.src1_data (rsp_xbar_demux_003_src1_data), // .data
.src1_channel (rsp_xbar_demux_003_src1_channel), // .channel
.src1_startofpacket (rsp_xbar_demux_003_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_xbar_demux_003_src1_endofpacket) // .endofpacket
);
niosII_system_rsp_xbar_demux_004 rsp_xbar_demux_004 (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_004_src_ready), // sink.ready
.sink_channel (id_router_004_src_channel), // .channel
.sink_data (id_router_004_src_data), // .data
.sink_startofpacket (id_router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_004_src_endofpacket), // .endofpacket
.sink_valid (id_router_004_src_valid), // .valid
.src0_ready (rsp_xbar_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_004_src0_valid), // .valid
.src0_data (rsp_xbar_demux_004_src0_data), // .data
.src0_channel (rsp_xbar_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_004_src0_endofpacket) // .endofpacket
);
niosII_system_rsp_xbar_demux_004 rsp_xbar_demux_005 (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_005_src_ready), // sink.ready
.sink_channel (id_router_005_src_channel), // .channel
.sink_data (id_router_005_src_data), // .data
.sink_startofpacket (id_router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_005_src_endofpacket), // .endofpacket
.sink_valid (id_router_005_src_valid), // .valid
.src0_ready (rsp_xbar_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_005_src0_valid), // .valid
.src0_data (rsp_xbar_demux_005_src0_data), // .data
.src0_channel (rsp_xbar_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_005_src0_endofpacket) // .endofpacket
);
niosII_system_rsp_xbar_demux_004 rsp_xbar_demux_006 (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_006_src_ready), // sink.ready
.sink_channel (id_router_006_src_channel), // .channel
.sink_data (id_router_006_src_data), // .data
.sink_startofpacket (id_router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_006_src_endofpacket), // .endofpacket
.sink_valid (id_router_006_src_valid), // .valid
.src0_ready (rsp_xbar_demux_006_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_006_src0_valid), // .valid
.src0_data (rsp_xbar_demux_006_src0_data), // .data
.src0_channel (rsp_xbar_demux_006_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_006_src0_endofpacket) // .endofpacket
);
niosII_system_rsp_xbar_demux_004 rsp_xbar_demux_007 (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_007_src_ready), // sink.ready
.sink_channel (id_router_007_src_channel), // .channel
.sink_data (id_router_007_src_data), // .data
.sink_startofpacket (id_router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_007_src_endofpacket), // .endofpacket
.sink_valid (id_router_007_src_valid), // .valid
.src0_ready (rsp_xbar_demux_007_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_007_src0_valid), // .valid
.src0_data (rsp_xbar_demux_007_src0_data), // .data
.src0_channel (rsp_xbar_demux_007_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_007_src0_endofpacket) // .endofpacket
);
niosII_system_rsp_xbar_demux_004 rsp_xbar_demux_008 (
.clk (clk_clk), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_008_src_ready), // sink.ready
.sink_channel (id_router_008_src_channel), // .channel
.sink_data (id_router_008_src_data), // .data
.sink_startofpacket (id_router_008_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_008_src_endofpacket), // .endofpacket
.sink_valid (id_router_008_src_valid), // .valid
.src0_ready (rsp_xbar_demux_008_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_008_src0_valid), // .valid
.src0_data (rsp_xbar_demux_008_src0_data), // .data
.src0_channel (rsp_xbar_demux_008_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_008_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_008_src0_endofpacket) // .endofpacket
);
niosII_system_rsp_xbar_demux_004 rsp_xbar_demux_009 (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_009_src_ready), // sink.ready
.sink_channel (id_router_009_src_channel), // .channel
.sink_data (id_router_009_src_data), // .data
.sink_startofpacket (id_router_009_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_009_src_endofpacket), // .endofpacket
.sink_valid (id_router_009_src_valid), // .valid
.src0_ready (rsp_xbar_demux_009_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_009_src0_valid), // .valid
.src0_data (rsp_xbar_demux_009_src0_data), // .data
.src0_channel (rsp_xbar_demux_009_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_009_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_009_src0_endofpacket) // .endofpacket
);
niosII_system_rsp_xbar_demux_004 rsp_xbar_demux_010 (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.sink_ready (id_router_010_src_ready), // sink.ready
.sink_channel (id_router_010_src_channel), // .channel
.sink_data (id_router_010_src_data), // .data
.sink_startofpacket (id_router_010_src_startofpacket), // .startofpacket
.sink_endofpacket (id_router_010_src_endofpacket), // .endofpacket
.sink_valid (id_router_010_src_valid), // .valid
.src0_ready (rsp_xbar_demux_010_src0_ready), // src0.ready
.src0_valid (rsp_xbar_demux_010_src0_valid), // .valid
.src0_data (rsp_xbar_demux_010_src0_data), // .data
.src0_channel (rsp_xbar_demux_010_src0_channel), // .channel
.src0_startofpacket (rsp_xbar_demux_010_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_xbar_demux_010_src0_endofpacket) // .endofpacket
);
niosII_system_rsp_xbar_mux rsp_xbar_mux (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_src_ready), // src.ready
.src_valid (rsp_xbar_mux_src_valid), // .valid
.src_data (rsp_xbar_mux_src_data), // .data
.src_channel (rsp_xbar_mux_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src0_valid), // .valid
.sink0_channel (rsp_xbar_demux_src0_channel), // .channel
.sink0_data (rsp_xbar_demux_src0_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_xbar_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_xbar_demux_001_src0_valid), // .valid
.sink1_channel (rsp_xbar_demux_001_src0_channel), // .channel
.sink1_data (rsp_xbar_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_xbar_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_xbar_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_xbar_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_xbar_demux_002_src0_valid), // .valid
.sink2_channel (rsp_xbar_demux_002_src0_channel), // .channel
.sink2_data (rsp_xbar_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_xbar_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_xbar_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_xbar_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_xbar_demux_003_src0_valid), // .valid
.sink3_channel (rsp_xbar_demux_003_src0_channel), // .channel
.sink3_data (rsp_xbar_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_xbar_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_xbar_demux_003_src0_endofpacket) // .endofpacket
);
niosII_system_rsp_xbar_mux_001 rsp_xbar_mux_001 (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.src_ready (rsp_xbar_mux_001_src_ready), // src.ready
.src_valid (rsp_xbar_mux_001_src_valid), // .valid
.src_data (rsp_xbar_mux_001_src_data), // .data
.src_channel (rsp_xbar_mux_001_src_channel), // .channel
.src_startofpacket (rsp_xbar_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_xbar_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_xbar_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_xbar_demux_src1_valid), // .valid
.sink0_channel (rsp_xbar_demux_src1_channel), // .channel
.sink0_data (rsp_xbar_demux_src1_data), // .data
.sink0_startofpacket (rsp_xbar_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_xbar_demux_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_xbar_demux_001_src1_ready), // sink1.ready
.sink1_valid (rsp_xbar_demux_001_src1_valid), // .valid
.sink1_channel (rsp_xbar_demux_001_src1_channel), // .channel
.sink1_data (rsp_xbar_demux_001_src1_data), // .data
.sink1_startofpacket (rsp_xbar_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_xbar_demux_001_src1_endofpacket), // .endofpacket
.sink2_ready (rsp_xbar_demux_002_src1_ready), // sink2.ready
.sink2_valid (rsp_xbar_demux_002_src1_valid), // .valid
.sink2_channel (rsp_xbar_demux_002_src1_channel), // .channel
.sink2_data (rsp_xbar_demux_002_src1_data), // .data
.sink2_startofpacket (rsp_xbar_demux_002_src1_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_xbar_demux_002_src1_endofpacket), // .endofpacket
.sink3_ready (rsp_xbar_demux_003_src1_ready), // sink3.ready
.sink3_valid (rsp_xbar_demux_003_src1_valid), // .valid
.sink3_channel (rsp_xbar_demux_003_src1_channel), // .channel
.sink3_data (rsp_xbar_demux_003_src1_data), // .data
.sink3_startofpacket (rsp_xbar_demux_003_src1_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_xbar_demux_003_src1_endofpacket), // .endofpacket
.sink4_ready (rsp_xbar_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_xbar_demux_004_src0_valid), // .valid
.sink4_channel (rsp_xbar_demux_004_src0_channel), // .channel
.sink4_data (rsp_xbar_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_xbar_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_xbar_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_xbar_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_xbar_demux_005_src0_valid), // .valid
.sink5_channel (rsp_xbar_demux_005_src0_channel), // .channel
.sink5_data (rsp_xbar_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_xbar_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_xbar_demux_005_src0_endofpacket), // .endofpacket
.sink6_ready (rsp_xbar_demux_006_src0_ready), // sink6.ready
.sink6_valid (rsp_xbar_demux_006_src0_valid), // .valid
.sink6_channel (rsp_xbar_demux_006_src0_channel), // .channel
.sink6_data (rsp_xbar_demux_006_src0_data), // .data
.sink6_startofpacket (rsp_xbar_demux_006_src0_startofpacket), // .startofpacket
.sink6_endofpacket (rsp_xbar_demux_006_src0_endofpacket), // .endofpacket
.sink7_ready (rsp_xbar_demux_007_src0_ready), // sink7.ready
.sink7_valid (rsp_xbar_demux_007_src0_valid), // .valid
.sink7_channel (rsp_xbar_demux_007_src0_channel), // .channel
.sink7_data (rsp_xbar_demux_007_src0_data), // .data
.sink7_startofpacket (rsp_xbar_demux_007_src0_startofpacket), // .startofpacket
.sink7_endofpacket (rsp_xbar_demux_007_src0_endofpacket), // .endofpacket
.sink8_ready (crosser_001_out_ready), // sink8.ready
.sink8_valid (crosser_001_out_valid), // .valid
.sink8_channel (crosser_001_out_channel), // .channel
.sink8_data (crosser_001_out_data), // .data
.sink8_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.sink8_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.sink9_ready (rsp_xbar_demux_009_src0_ready), // sink9.ready
.sink9_valid (rsp_xbar_demux_009_src0_valid), // .valid
.sink9_channel (rsp_xbar_demux_009_src0_channel), // .channel
.sink9_data (rsp_xbar_demux_009_src0_data), // .data
.sink9_startofpacket (rsp_xbar_demux_009_src0_startofpacket), // .startofpacket
.sink9_endofpacket (rsp_xbar_demux_009_src0_endofpacket), // .endofpacket
.sink10_ready (rsp_xbar_demux_010_src0_ready), // sink10.ready
.sink10_valid (rsp_xbar_demux_010_src0_valid), // .valid
.sink10_channel (rsp_xbar_demux_010_src0_channel), // .channel
.sink10_data (rsp_xbar_demux_010_src0_data), // .data
.sink10_startofpacket (rsp_xbar_demux_010_src0_startofpacket), // .startofpacket
.sink10_endofpacket (rsp_xbar_demux_010_src0_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (60),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (69),
.IN_PKT_BYTE_CNT_L (67),
.IN_PKT_TRANS_COMPRESSED_READ (61),
.IN_PKT_BURSTWRAP_H (72),
.IN_PKT_BURSTWRAP_L (70),
.IN_PKT_BURST_SIZE_H (75),
.IN_PKT_BURST_SIZE_L (73),
.IN_PKT_RESPONSE_STATUS_H (99),
.IN_PKT_RESPONSE_STATUS_L (98),
.IN_PKT_TRANS_EXCLUSIVE (66),
.IN_PKT_BURST_TYPE_H (77),
.IN_PKT_BURST_TYPE_L (76),
.IN_ST_DATA_W (100),
.OUT_PKT_ADDR_H (42),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (51),
.OUT_PKT_BYTE_CNT_L (49),
.OUT_PKT_TRANS_COMPRESSED_READ (43),
.OUT_PKT_BURST_SIZE_H (57),
.OUT_PKT_BURST_SIZE_L (55),
.OUT_PKT_RESPONSE_STATUS_H (81),
.OUT_PKT_RESPONSE_STATUS_L (80),
.OUT_PKT_TRANS_EXCLUSIVE (48),
.OUT_PKT_BURST_TYPE_H (59),
.OUT_PKT_BURST_TYPE_L (58),
.OUT_ST_DATA_W (82),
.ST_CHANNEL_W (11),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0)
) width_adapter (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_valid (cmd_xbar_mux_001_src_valid), // sink.valid
.in_channel (cmd_xbar_mux_001_src_channel), // .channel
.in_startofpacket (cmd_xbar_mux_001_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_xbar_mux_001_src_endofpacket), // .endofpacket
.in_ready (cmd_xbar_mux_001_src_ready), // .ready
.in_data (cmd_xbar_mux_001_src_data), // .data
.out_endofpacket (width_adapter_src_endofpacket), // src.endofpacket
.out_data (width_adapter_src_data), // .data
.out_channel (width_adapter_src_channel), // .channel
.out_valid (width_adapter_src_valid), // .valid
.out_ready (width_adapter_src_ready), // .ready
.out_startofpacket (width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (42),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (51),
.IN_PKT_BYTE_CNT_L (49),
.IN_PKT_TRANS_COMPRESSED_READ (43),
.IN_PKT_BURSTWRAP_H (54),
.IN_PKT_BURSTWRAP_L (52),
.IN_PKT_BURST_SIZE_H (57),
.IN_PKT_BURST_SIZE_L (55),
.IN_PKT_RESPONSE_STATUS_H (81),
.IN_PKT_RESPONSE_STATUS_L (80),
.IN_PKT_TRANS_EXCLUSIVE (48),
.IN_PKT_BURST_TYPE_H (59),
.IN_PKT_BURST_TYPE_L (58),
.IN_ST_DATA_W (82),
.OUT_PKT_ADDR_H (60),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (69),
.OUT_PKT_BYTE_CNT_L (67),
.OUT_PKT_TRANS_COMPRESSED_READ (61),
.OUT_PKT_BURST_SIZE_H (75),
.OUT_PKT_BURST_SIZE_L (73),
.OUT_PKT_RESPONSE_STATUS_H (99),
.OUT_PKT_RESPONSE_STATUS_L (98),
.OUT_PKT_TRANS_EXCLUSIVE (66),
.OUT_PKT_BURST_TYPE_H (77),
.OUT_PKT_BURST_TYPE_L (76),
.OUT_ST_DATA_W (100),
.ST_CHANNEL_W (11),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1)
) width_adapter_001 (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_valid (id_router_001_src_valid), // sink.valid
.in_channel (id_router_001_src_channel), // .channel
.in_startofpacket (id_router_001_src_startofpacket), // .startofpacket
.in_endofpacket (id_router_001_src_endofpacket), // .endofpacket
.in_ready (id_router_001_src_ready), // .ready
.in_data (id_router_001_src_data), // .data
.out_endofpacket (width_adapter_001_src_endofpacket), // src.endofpacket
.out_data (width_adapter_001_src_data), // .data
.out_channel (width_adapter_001_src_channel), // .channel
.out_valid (width_adapter_001_src_valid), // .valid
.out_ready (width_adapter_001_src_ready), // .ready
.out_startofpacket (width_adapter_001_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (60),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (69),
.IN_PKT_BYTE_CNT_L (67),
.IN_PKT_TRANS_COMPRESSED_READ (61),
.IN_PKT_BURSTWRAP_H (72),
.IN_PKT_BURSTWRAP_L (70),
.IN_PKT_BURST_SIZE_H (75),
.IN_PKT_BURST_SIZE_L (73),
.IN_PKT_RESPONSE_STATUS_H (99),
.IN_PKT_RESPONSE_STATUS_L (98),
.IN_PKT_TRANS_EXCLUSIVE (66),
.IN_PKT_BURST_TYPE_H (77),
.IN_PKT_BURST_TYPE_L (76),
.IN_ST_DATA_W (100),
.OUT_PKT_ADDR_H (42),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (51),
.OUT_PKT_BYTE_CNT_L (49),
.OUT_PKT_TRANS_COMPRESSED_READ (43),
.OUT_PKT_BURST_SIZE_H (57),
.OUT_PKT_BURST_SIZE_L (55),
.OUT_PKT_RESPONSE_STATUS_H (81),
.OUT_PKT_RESPONSE_STATUS_L (80),
.OUT_PKT_TRANS_EXCLUSIVE (48),
.OUT_PKT_BURST_TYPE_H (59),
.OUT_PKT_BURST_TYPE_L (58),
.OUT_ST_DATA_W (82),
.ST_CHANNEL_W (11),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0)
) width_adapter_002 (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_valid (cmd_xbar_mux_003_src_valid), // sink.valid
.in_channel (cmd_xbar_mux_003_src_channel), // .channel
.in_startofpacket (cmd_xbar_mux_003_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_xbar_mux_003_src_endofpacket), // .endofpacket
.in_ready (cmd_xbar_mux_003_src_ready), // .ready
.in_data (cmd_xbar_mux_003_src_data), // .data
.out_endofpacket (width_adapter_002_src_endofpacket), // src.endofpacket
.out_data (width_adapter_002_src_data), // .data
.out_channel (width_adapter_002_src_channel), // .channel
.out_valid (width_adapter_002_src_valid), // .valid
.out_ready (width_adapter_002_src_ready), // .ready
.out_startofpacket (width_adapter_002_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (42),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (51),
.IN_PKT_BYTE_CNT_L (49),
.IN_PKT_TRANS_COMPRESSED_READ (43),
.IN_PKT_BURSTWRAP_H (54),
.IN_PKT_BURSTWRAP_L (52),
.IN_PKT_BURST_SIZE_H (57),
.IN_PKT_BURST_SIZE_L (55),
.IN_PKT_RESPONSE_STATUS_H (81),
.IN_PKT_RESPONSE_STATUS_L (80),
.IN_PKT_TRANS_EXCLUSIVE (48),
.IN_PKT_BURST_TYPE_H (59),
.IN_PKT_BURST_TYPE_L (58),
.IN_ST_DATA_W (82),
.OUT_PKT_ADDR_H (60),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (69),
.OUT_PKT_BYTE_CNT_L (67),
.OUT_PKT_TRANS_COMPRESSED_READ (61),
.OUT_PKT_BURST_SIZE_H (75),
.OUT_PKT_BURST_SIZE_L (73),
.OUT_PKT_RESPONSE_STATUS_H (99),
.OUT_PKT_RESPONSE_STATUS_L (98),
.OUT_PKT_TRANS_EXCLUSIVE (66),
.OUT_PKT_BURST_TYPE_H (77),
.OUT_PKT_BURST_TYPE_L (76),
.OUT_ST_DATA_W (100),
.ST_CHANNEL_W (11),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1)
) width_adapter_003 (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.in_valid (id_router_003_src_valid), // sink.valid
.in_channel (id_router_003_src_channel), // .channel
.in_startofpacket (id_router_003_src_startofpacket), // .startofpacket
.in_endofpacket (id_router_003_src_endofpacket), // .endofpacket
.in_ready (id_router_003_src_ready), // .ready
.in_data (id_router_003_src_data), // .data
.out_endofpacket (width_adapter_003_src_endofpacket), // src.endofpacket
.out_data (width_adapter_003_src_data), // .data
.out_channel (width_adapter_003_src_channel), // .channel
.out_valid (width_adapter_003_src_valid), // .valid
.out_ready (width_adapter_003_src_ready), // .ready
.out_startofpacket (width_adapter_003_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (100),
.BITS_PER_SYMBOL (100),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (11),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser (
.in_clk (altpll_0_c1_clk), // in_clk.clk
.in_reset (rst_controller_reset_out_reset), // in_clk_reset.reset
.out_clk (clk_clk), // out_clk.clk
.out_reset (rst_controller_001_reset_out_reset), // out_clk_reset.reset
.in_ready (cmd_xbar_demux_001_src8_ready), // in.ready
.in_valid (cmd_xbar_demux_001_src8_valid), // .valid
.in_startofpacket (cmd_xbar_demux_001_src8_startofpacket), // .startofpacket
.in_endofpacket (cmd_xbar_demux_001_src8_endofpacket), // .endofpacket
.in_channel (cmd_xbar_demux_001_src8_channel), // .channel
.in_data (cmd_xbar_demux_001_src8_data), // .data
.out_ready (crosser_out_ready), // out.ready
.out_valid (crosser_out_valid), // .valid
.out_startofpacket (crosser_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_out_endofpacket), // .endofpacket
.out_channel (crosser_out_channel), // .channel
.out_data (crosser_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (100),
.BITS_PER_SYMBOL (100),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (11),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_001 (
.in_clk (clk_clk), // in_clk.clk
.in_reset (rst_controller_001_reset_out_reset), // in_clk_reset.reset
.out_clk (altpll_0_c1_clk), // out_clk.clk
.out_reset (rst_controller_reset_out_reset), // out_clk_reset.reset
.in_ready (rsp_xbar_demux_008_src0_ready), // in.ready
.in_valid (rsp_xbar_demux_008_src0_valid), // .valid
.in_startofpacket (rsp_xbar_demux_008_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_xbar_demux_008_src0_endofpacket), // .endofpacket
.in_channel (rsp_xbar_demux_008_src0_channel), // .channel
.in_data (rsp_xbar_demux_008_src0_data), // .data
.out_ready (crosser_001_out_ready), // out.ready
.out_valid (crosser_001_out_valid), // .valid
.out_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.out_channel (crosser_001_out_channel), // .channel
.out_data (crosser_001_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
niosII_system_irq_mapper irq_mapper (
.clk (altpll_0_c1_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq
.receiver2_irq (irq_mapper_receiver2_irq), // receiver2.irq
.sender_irq (nios2_qsys_0_d_irq_irq) // sender.irq
);
endmodule
|
/*
* Copyright (c) Atomic Rules LLC, Auburn NH., 2009-2010
*
* Atomic Rules LLC
* 287 Chester Road
* Auburn, NH 03032
* United States of America
* Telephone 603-483-0994
*
* This file is part of OpenCPI (www.opencpi.org).
* ____ __________ ____
* / __ \____ ___ ____ / ____/ __ \ / _/ ____ _________ _
* / / / / __ \/ _ \/ __ \/ / / /_/ / / / / __ \/ ___/ __ `/
* / /_/ / /_/ / __/ / / / /___/ ____/_/ / _/ /_/ / / / /_/ /
* \____/ .___/\___/_/ /_/\____/_/ /___/(_)____/_/ \__, /
* /_/ /____/
*
* OpenCPI is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published
* by the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* OpenCPI is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with OpenCPI. If not, see <http://www.gnu.org/licenses/>.
*/
// arSRLFIFOD.v
//
// 2009-05-10 ssiegel Creation in VHDL
// 2009-11-01 ssiegel Converted to Verilog from VHDL
// 2009-11-14 ssiegel Add D flop at back end for greater Fmax
module arSRLFIFOD (CLK,RST_N,ENQ,DEQ,FULL_N,EMPTY_N,D_IN,D_OUT,CLR);
parameter width = 128;
parameter l2depth = 5;
parameter depth = 2**l2depth;
input CLK;
input RST_N;
input CLR;
input ENQ;
input DEQ;
output FULL_N;
output EMPTY_N;
input[width-1:0] D_IN;
output[width-1:0] D_OUT;
reg[l2depth-1:0] pos; // head position
reg[width-1:0] dat[depth-1:0]; // SRL and output DFFs wed together
reg[width-1:0] dreg; // Ouput register
reg sempty, sfull, dempty;
integer i;
always@(posedge CLK) begin
if(!RST_N || CLR) begin
pos <= 1'b0;
sempty <= 1'b1;
sfull <= 1'b0;
dempty <= 1'b1;
end else begin
if (!ENQ && DEQ) pos <= pos - 1;
if ( ENQ && !DEQ) pos <= pos + 1;
if (ENQ) begin
for(i=depth-1;i>0;i=i-1) dat[i] <= dat[i-1];
dat[0] <= D_IN;
end
sempty <= (pos==0 || (pos==1 && (DEQ&&!ENQ)));
sfull <= (pos==(depth-1) || (pos==(depth-2) && (ENQ&&!DEQ)));
// Advance to the dreg whenever we can...
if ((dempty && !sempty) || (!dempty && DEQ && !sempty)) begin
dreg <= dat[pos-1];
dempty <= 1'b0;
end
if (DEQ && sempty) dempty <= 1'b1;
end
end
assign FULL_N = !sfull;
assign EMPTY_N = !dempty;
assign D_OUT = dreg;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05:06:37 04/14/2015
// Design Name:
// Module Name: vga_driver
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module vga_driver(clk_50MHz, vs_vga, hs_vga, RED, GREEN, BLUE, CURX, CURY, COLOR, CLK_DATA, RESET);
input clk_50MHz;
output vs_vga;
output hs_vga;
output [2:0] RED;
output [2:0] GREEN;
output [1:0] BLUE;
reg VS = 0;
reg HS = 0;
input RESET;
//current client data
input [7:0] COLOR;
output CLK_DATA;
output [9:0] CURX;
output [8:0] CURY;
//##### Module constants (http://tinyvga.com/vga-timing/640x480@60Hz)
parameter HDisplayArea = 640; // horizontal display area
parameter HLimit = 800; // maximum horizontal amount (limit)
parameter HFrontPorch = 16; // h. front porch
parameter HBackPorch = 48; // h. back porch
parameter HSyncWidth = 96; // h. pulse width
parameter VDisplayArea = 480; // vertical display area
parameter VLimit = 525; // maximum vertical amount (limit)
parameter VFrontPorch = 10; // v. front porch
parameter VBackPorch = 33; // v. back porch
parameter VSyncWidth = 2; // v. pulse width
//##### Local variables
wire clk_25MHz;
reg [9:0] CurHPos = 0; //maximum of HLimit (2^10 - 1 = 1023)
reg [9:0] CurVPos = 0; //maximum of VLimit
reg HBlank_reg, VBlank_reg, Blank = 0;
reg [9:0] CurrentX = 0; //maximum of HDisplayArea
reg [8:0] CurrentY = 0; //maximum of VDisplayArea (2^9 - 1 = 511)
//##### Submodule declaration
clock_divider clk_div(.clk_in(clk_50MHz), .clk_out(clk_25MHz));
//shifts the clock by half a period (negates it)
//see timing diagrams for a better understanding of the reason for this
clock_shift clk_shift(.clk_in(clk_25MHz), .clk_out(CLK_DATA));
//simulate the vertical and horizontal positions
always @(posedge clk_25MHz) begin
if(CurHPos < HLimit-1) begin
CurHPos <= CurHPos + 1;
end
else begin
CurHPos <= 0;
if(CurVPos < VLimit-1)
CurVPos <= CurVPos + 1;
else
CurVPos <= 0;
end
if(RESET) begin
CurHPos <= 0;
CurVPos <= 0;
end
end
//##### VGA Logic (http://tinyvga.com/vga-timing/640x480@60Hz)
//HSync logic
always @(posedge clk_25MHz)
if((CurHPos < HSyncWidth) && ~RESET)
HS <= 1;
else
HS <= 0;
//VSync logic
always @(posedge clk_25MHz)
if((CurVPos < VSyncWidth) && ~RESET)
VS <= 1;
else
VS <= 0;
//Horizontal logic
always @(posedge clk_25MHz)
if((CurHPos >= HSyncWidth + HFrontPorch) && (CurHPos < HSyncWidth + HFrontPorch + HDisplayArea) || RESET)
HBlank_reg <= 0;
else
HBlank_reg <= 1;
//Vertical logic
always @(posedge clk_25MHz)
if((CurVPos >= VSyncWidth + VFrontPorch) && (CurVPos < VSyncWidth + VFrontPorch + VDisplayArea) || RESET)
VBlank_reg <= 0;
else
VBlank_reg <= 1;
//Do not output any color information when we are in the vertical
//or horizontal blanking areas. Set a boolean to keep track of this.
always @(posedge clk_25MHz)
if((HBlank_reg || VBlank_reg) && ~RESET)
Blank <= 1;
else
Blank <= 0;
//Keep track of the current "real" X position. This is the actual current X
//pixel location abstracted away from all the timing details
always @(posedge clk_25MHz)
if(HBlank_reg && ~RESET)
CurrentX <= 0;
else
CurrentX <= CurHPos - HSyncWidth - HFrontPorch;
//Keep track of the current "real" Y position. This is the actual current Y
//pixel location abstracted away from all the timing details
always @(posedge clk_25MHz)
if(VBlank_reg && ~RESET)
CurrentY <= 0;
else
CurrentY <= CurVPos - VSyncWidth - VFrontPorch;
assign CURX = CurrentX;
assign CURY = CurrentY;
assign hs_vga = HS;
assign vs_vga = VS;
//Respects VGA Blanking areas
assign RED = (Blank) ? 3'b000 : COLOR[7:5];
assign GREEN = (Blank) ? 3'b000 : COLOR[4:2];
assign BLUE = (Blank) ? 2'b00 : COLOR[1:0];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR3_TB_V
`define SKY130_FD_SC_HDLL__OR3_TB_V
/**
* or3: 3-input OR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__or3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_hdll__or3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR3_TB_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Wed Mar 01 09:53:17 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_rgb565_to_rgb888_0_0 -prefix
// system_rgb565_to_rgb888_0_0_ system_rgb565_to_rgb888_1_0_sim_netlist.v
// Design : system_rgb565_to_rgb888_1_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_rgb565_to_rgb888_1_0,rgb565_to_rgb888,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "rgb565_to_rgb888,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_rgb565_to_rgb888_0_0
(rgb_565,
rgb_888);
input [15:0]rgb_565;
output [23:0]rgb_888;
wire \<const0> ;
wire [15:0]rgb_565;
assign rgb_888[23:19] = rgb_565[15:11];
assign rgb_888[18:16] = rgb_565[15:13];
assign rgb_888[15:10] = rgb_565[10:5];
assign rgb_888[9:8] = rgb_565[10:9];
assign rgb_888[7:3] = rgb_565[4:0];
assign rgb_888[2] = \<const0> ;
assign rgb_888[1] = \<const0> ;
assign rgb_888[0] = \<const0> ;
GND GND
(.G(\<const0> ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module sync_data #(
parameter NUM_OF_BITS = 1,
parameter ASYNC_CLK = 1
) (
input in_clk,
input [NUM_OF_BITS-1:0] in_data,
input out_clk,
output reg [NUM_OF_BITS-1:0] out_data
);
generate
if (ASYNC_CLK == 1) begin
wire out_toggle;
wire in_toggle;
reg out_toggle_d1 = 1'b0;
reg in_toggle_d1 = 1'b0;
reg [NUM_OF_BITS-1:0] cdc_hold;
sync_bits i_sync_out (
.in(in_toggle_d1),
.out_clk(out_clk),
.out_resetn(1'b1),
.out(out_toggle)
);
sync_bits i_sync_in (
.in(out_toggle_d1),
.out_clk(in_clk),
.out_resetn(1'b1),
.out(in_toggle)
);
wire in_load = in_toggle == in_toggle_d1;
wire out_load = out_toggle ^ out_toggle_d1;
always @(posedge in_clk) begin
if (in_load == 1'b1) begin
cdc_hold <= in_data;
in_toggle_d1 <= ~in_toggle_d1;
end
end
always @(posedge out_clk) begin
if (out_load == 1'b1) begin
out_data <= cdc_hold;
end
out_toggle_d1 <= out_toggle;
end
end else begin
always @(*) begin
out_data <= in_data;
end
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O311A_BEHAVIORAL_V
`define SKY130_FD_SC_LS__O311A_BEHAVIORAL_V
/**
* o311a: 3-input OR into 3-input AND.
*
* X = ((A1 | A2 | A3) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__o311a (
X ,
A1,
A2,
A3,
B1,
C1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
and and0 (and0_out_X, or0_out, B1, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O311A_BEHAVIORAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: NTHU
// Engineer: Y.J Shih
//
// Create Date: 2015/05/27 11:15:54
// Design Name: PS/2 interface
// Module Name: Ps2Interface
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// Original VHDL version is create by Ulrich Zolt.
//
//////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// ps2interface.vhd
////////////////////////////////////////////////////////////////////////
// Author : Ulrich Zolt
// Copyright 2006 Digilent, Inc.
////////////////////////////////////////////////////////////////////////
// This file contains the implementation of a generic bidirectional
// ps/2 interface.
////////////////////////////////////////////////////////////////////////
// Behavioral description
////////////////////////////////////////////////////////////////////////
// Please read the following article on the web for understanding how
// the ps/2 protocol works.
// http://www.computer/engineering.org/ps2protocol/
// This module implements a generic bidirectional ps/2 interface. It can
// be used with any ps/2 compatible device. It offers its clients a
// convenient way to exchange data with the device. The interface
// transparently wraps the byte to be sent into a ps/2 frame, generates
// parity for byte and sends the frame one bit at a time to the device.
// Similarly, when receiving data from the ps2 device, the interface
// receives the frame, checks for parity, and extract the usefull data
// and forwards it to the client. If an error occurs during receiving
// or sending a byte, the client is informed by settings the err output
// line high. This way, the client can resend the data or can issue
// a resend command to the device.
// The physical ps/2 interface uses 4 lines
// For the 6/pin connector pins are assigned as follows:
// 1 - Data
// 2 - Not Implemented
// 3 - Ground
// 4 - Vcc (+5V)
// 5 - Clock
// 6 - Not Implemented
// The clock line carries the device generated clock which has a
// frequency in range 10 / 16.7 kHz (30 to 50us). When line is idle
// it is placed in high impedance. The clock is only generated when
// device is sending or receiving data.
// The Data and Clock lines are both open/collector with pullup
// resistors to Vcc. An "open/collector" interface has two possible
// states: low('0') or high impedance('Z').
// When device wants to send a byte, it pulls the clock line low and the
// host(i.e. this interfaces) recognizes that the device is sending data
// When the host wants to send data, it maeks a request to send. This
// is done by holding the clock line low for at least 100us, then with
// the clock line low, the data line is brought low. Next the clock line
// is released (placed in high impedance). The devices begins generating
// clock signal on clock line.
// When receiving data, bits are read from the data line (ps2_data) on
// the falling edge of the clock (ps2_clk). When sending data, the
// device reads the bits from the data line on the rising edge of the
// clock.
// A frame for sending a byte is comprised of 11 bits as shown bellow:
// bits 10 9 8 7 6 5 4 3 2 1 0
// -------------------------------------------------------------
// | STOP| PAR | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | START |
// -------------------------------------------------------------
// STOP - stop bit, always '1'
// PAR - parity bit, odd parity for the 8 data bits.
// - select in such way that the number of bits of '1' in the data
// - bits together with parity bit is odd.
// D0/7 - data bits.
// START - start bit, always '0'
//
// Frame is sent bit by bit starting with the least significant bit
// (starting bit) and is received the same way. This is done, when
// receiving, by shifting the frame register to the left when a bit
// is available and placing the bit on data line on the most significant
// bit. This way the first bit sent will reach the least significant bit
// of the frame when all the bits have been received. When sending data
// the least significant bit of the frame is placed on the data line
// and the frame is shifted to the right when another bit needs to be
// sent. During the request to send, when releasing the clock line,
// the device reads the data line and interprets the data on it as the
// first bit of the frame. Data line is low at that time, at this is the
// way the start bit('0') is sent. Because of this, when sending, only
// 10 shifts of the frame will be made.
// While the interface is sending or receiving data, the busy output
// signal goes high. When interface is idle, busy is low.
// After sending all the bits in the frame, the device must acknowledge
// the data sent. This is done by the host releasing and data line
// (clock line is already released) after the last bit is sent. The
// devices brings the data line and the clock line low, in this order,
// to acknowledge the data. If data line is high when clock line goes
// low after last bit, the device did not acknowledge the data and
// err output is set.
// A FSM is used to manage the transitions the set all the command
// signals. States that begin with "rx_" are used to receive data
// from device and states begining with "tx_" are used to send data
// to the device.
// For the parity bit, a ROM holds the parity bit for all possible
// data (256 possible values, since 8 bits of data). The ROM has
// dimensions 256x1bit. For obtaining the parity bit of a value,
// the bit at the data value address is read. Ex: to find the parity
// bit of 174, the bit at address 174 is read.
// For generating the necessary delay, counters are used. For example,
// to generate the 100us delay a 14 bit counter is used that has the
// upper limit for counting 10000. The interface is designed to run
// at 100MHz. Thus, 10000x10ns = 100us.
///////////////////////////////////////////////////////////////////////
// If using the interface at different frequency than 100MHz, adjusting
// the delay counters is necessary!!!
///////////////////////////////////////////////////////////////////////
// Clock line(ps2_clk) and data line(ps2_data) are passed through a
// debouncer for the transitions of the clock and data to be clean.
// Also, ps2_clk_s and ps2_data_s hold the debounced and synchronized
// value of the clock and data line to the system clock(clk).
////////////////////////////////////////////////////////////////////////
// Port definitions
////////////////////////////////////////////////////////////////////////
// ps2_clk - inout pin, clock line of the ps/2 interface
// ps2_data - inout pin, data line of the ps/2 interface
// clk - input pin, system clock signal
// rst - input pin, system reset signal
// tx_data - input pin, 8 bits, from client
// - data to be sent to the device
// tx_valid - input pin, from client
// - should be active for one clock period when then
// - client wants to send data to the device and
// - data to be sent is valid on tx_data
// rx_data - output pin, 8 bits, to client
// - data received from device
// read - output pin, to client
// - active for one clock period when new data is
// - available from device
// busy - output pin, to client
// - active while sending or receiving data.
// err - output pin, to client
// - active for one clock period when an error occurred
// - during sending or receiving.
////////////////////////////////////////////////////////////////////////
// Revision History:
// 09/18/2006(UlrichZ): created
////////////////////////////////////////////////////////////////////////
module Ps2Interface#(
parameter SYSCLK_FREQUENCY_HZ = 100000000
)(
ps2_clk,
ps2_data,
clk,
rst,
tx_data,
tx_valid,
rx_data,
rx_valid,
busy,
err
);
inout ps2_clk, ps2_data;
input clk, rst;
input [7:0] tx_data;
input tx_valid;
output reg [7:0] rx_data;
output reg rx_valid;
output busy;
output reg err;
parameter CLOCK_CNT_100US = (100*1000) / (1000000000/SYSCLK_FREQUENCY_HZ);
parameter CLOCK_CNT_20US = (20*1000) / (1000000000/SYSCLK_FREQUENCY_HZ);
parameter DEBOUNCE_DELAY = 15;
parameter BITS_NUM = 11;
parameter [0:0] parity_table [0:255] = { //(odd) parity bit table, used instead of logic because this way speed is far greater
1'b1,1'b0,1'b0,1'b1,1'b0,1'b1,1'b1,1'b0,
1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b0,1'b1,
1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b0,1'b1,
1'b1,1'b0,1'b0,1'b1,1'b0,1'b1,1'b1,1'b0,
1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b0,1'b1,
1'b1,1'b0,1'b0,1'b1,1'b0,1'b1,1'b1,1'b0,
1'b1,1'b0,1'b0,1'b1,1'b0,1'b1,1'b1,1'b0,
1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b0,1'b1,
1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b0,1'b1,
1'b1,1'b0,1'b0,1'b1,1'b0,1'b1,1'b1,1'b0,
1'b1,1'b0,1'b0,1'b1,1'b0,1'b1,1'b1,1'b0,
1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b0,1'b1,
1'b1,1'b0,1'b0,1'b1,1'b0,1'b1,1'b1,1'b0,
1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b0,1'b1,
1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b0,1'b1,
1'b1,1'b0,1'b0,1'b1,1'b0,1'b1,1'b1,1'b0,
1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b0,1'b1,
1'b1,1'b0,1'b0,1'b1,1'b0,1'b1,1'b1,1'b0,
1'b1,1'b0,1'b0,1'b1,1'b0,1'b1,1'b1,1'b0,
1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b0,1'b1,
1'b1,1'b0,1'b0,1'b1,1'b0,1'b1,1'b1,1'b0,
1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b0,1'b1,
1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b0,1'b1,
1'b1,1'b0,1'b0,1'b1,1'b0,1'b1,1'b1,1'b0,
1'b1,1'b0,1'b0,1'b1,1'b0,1'b1,1'b1,1'b0,
1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b0,1'b1,
1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b0,1'b1,
1'b1,1'b0,1'b0,1'b1,1'b0,1'b1,1'b1,1'b0,
1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b0,1'b1,
1'b1,1'b0,1'b0,1'b1,1'b0,1'b1,1'b1,1'b0,
1'b1,1'b0,1'b0,1'b1,1'b0,1'b1,1'b1,1'b0,
1'b0,1'b1,1'b1,1'b0,1'b1,1'b0,1'b0,1'b1
};
parameter IDLE = 4'd0;
parameter RX_NEG_EDGE = 4'd1;
parameter RX_CLK_LOW = 4'd2;
parameter RX_CLK_HIGH = 4'd3;
parameter TX_FORCE_CLK_LOW = 4'd4;
parameter TX_BRING_DATA_LOW = 4'd5;
parameter TX_RELEASE_CLK = 4'd6;
parameter TX_WAIT_FIRTS_NEG_EDGE = 4'd7;
parameter TX_CLK_LOW = 4'd8;
parameter TX_WAIT_POS_EDGE = 4'd9;
parameter TX_CLK_HIGH = 4'd10;
parameter TX_WAIT_POS_EDGE_BEFORE_ACK = 4'd11;
parameter TX_WAIT_ACK = 4'd12;
parameter TX_RECEIVED_ACK = 4'd13;
parameter TX_ERROR_NO_ACK = 4'd14;
reg [10:0] frame;
wire rx_parity;
wire ps2_clk_in, ps2_data_in;
reg clk_inter, ps2_clk_s, data_inter, ps2_data_s;
reg [3:0] clk_count, data_count;
reg ps2_clk_en, ps2_clk_en_next, ps2_data_en, ps2_data_en_next;
reg ps2_clk_out, ps2_clk_out_next, ps2_data_out, ps2_data_out_next;
reg err_next;
reg [3:0] state, state_next;
reg rx_finish;
reg [3:0] bits_count;
reg [13:0] counter, counter_next;
IOBUF IOBUF_inst_0(
.O(ps2_clk_in),
.IO(ps2_clk),
.I(ps2_clk_out),
.T(~ps2_clk_en)
);
IOBUF IOBUF_inst_1(
.O(ps2_data_in),
.IO(ps2_data),
.I(ps2_data_out),
.T(~ps2_data_en)
);
//assign ps2_clk = (ps2_clk_en)?ps2_clk_out:1'bz;
//assign ps2_data = (ps2_data_en)?ps2_data_out:1'bz;
assign busy = (state==IDLE)?1'b0:1'b1;
always @ (posedge clk, posedge rst)begin
if(rst)begin
rx_data <= 0;
rx_valid <= 1'b0;
end else if(rx_finish==1'b1)begin // set read signal for the client to know
rx_data <= frame[8:1]; // a new byte was received and is available on rx_data
rx_valid <= 1'b1;
end else begin
rx_data <= rx_data;
rx_valid <= 1'b0;
end
end
assign rx_parity = parity_table[frame[8:1]];
assign tx_parity = parity_table[tx_data];
always @ (posedge clk, posedge rst)begin
if(rst)
frame <= 0;
else if(tx_valid==1'b1 && state==IDLE) begin
frame[0] <= 1'b0; //start bit
frame[8:1] <= tx_data; //data
frame[9] <= tx_parity; //parity bit
frame[10] <= 1'b1; //stop bit
end else if(state==RX_NEG_EDGE || state==TX_CLK_LOW)
frame <= {ps2_data_s, frame[10:1]};
else
frame <= frame;
end
// Debouncer
always @ (posedge clk, posedge rst) begin
if(rst)begin
ps2_clk_s <= 1'b1;
clk_inter <= 1'b1;
clk_count <= 0;
end else if(ps2_clk_in != clk_inter)begin
ps2_clk_s <= ps2_clk_s;
clk_inter <= ps2_clk_in;
clk_count <= 0;
end else if(clk_count == DEBOUNCE_DELAY) begin
ps2_clk_s <= clk_inter;
clk_inter <= clk_inter;
clk_count <= clk_count;
end else begin
ps2_clk_s <= ps2_clk_s;
clk_inter <= clk_inter;
clk_count <= clk_count + 1'b1;
end
end
always @ (posedge clk, posedge rst) begin
if(rst)begin
ps2_data_s <= 1'b1;
data_inter <= 1'b1;
data_count <= 0;
end else if(ps2_data_in != data_inter)begin
ps2_data_s <= ps2_data_s;
data_inter <= ps2_data_in;
data_count <= 0;
end else if(data_count == DEBOUNCE_DELAY) begin
ps2_data_s <= data_inter;
data_inter <= data_inter;
data_count <= data_count;
end else begin
ps2_data_s <= ps2_data_s;
data_inter <= data_inter;
data_count <= data_count + 1'b1;
end
end
// FSM
always @ (posedge clk, posedge rst)begin
if(rst)begin
state <= IDLE;
ps2_clk_en <= 1'b0;
ps2_clk_out <= 1'b0;
ps2_data_en <= 1'b0;
ps2_data_out <= 1'b0;
err <= 1'b0;
counter <= 0;
end else begin
state <= state_next;
ps2_clk_en <= ps2_clk_en_next;
ps2_clk_out <= ps2_clk_out_next;
ps2_data_en <= ps2_data_en_next;
ps2_data_out <= ps2_data_out_next;
err <= err_next;
counter <= counter_next;
end
end
always @ * begin
state_next = IDLE; // default values for these signals
ps2_clk_en_next = 1'b0; // ensures signals are reset to default value
ps2_clk_out_next = 1'b1; // when conditions for their activation are no
ps2_data_en_next = 1'b0; // longer applied (transition to other state,
ps2_data_out_next = 1'b1; // where signal should not be active)
err_next = 1'b0; // Idle value for ps2_clk and ps2_data is 'Z'
rx_finish = 1'b0;
counter_next = 0;
case(state)
IDLE:begin // wait for the device to begin a transmission
if(tx_valid == 1'b1)begin // by pulling the clock line low and go to state
state_next = TX_FORCE_CLK_LOW; // RX_NEG_EDGE or, if write is high, the
end else if(ps2_clk_s == 1'b0)begin // client of this interface wants to send a byte
state_next = RX_NEG_EDGE; // to the device and a transition is made to state
end else begin // TX_FORCE_CLK_LOW
state_next = IDLE;
end
end
RX_NEG_EDGE:begin // data must be read into frame in this state
state_next = RX_CLK_LOW; // the ps2_clk just transitioned from high to low
end
RX_CLK_LOW:begin // ps2_clk line is low, wait for it to go high
if(ps2_clk_s == 1'b1)begin
state_next = RX_CLK_HIGH;
end else begin
state_next = RX_CLK_LOW;
end
end
RX_CLK_HIGH:begin // ps2_clk is high, check if all the bits have been read
if(bits_count == BITS_NUM)begin // if, last bit read, check parity, and if parity ok
if(rx_parity != frame[9])begin // load received data into rx_data.
err_next = 1'b1; // else if more bits left, then wait for the ps2_clk to
state_next = IDLE; // go low
end else begin
rx_finish = 1'b1;
state_next = IDLE;
end
end else if(ps2_clk_s == 1'b0)begin
state_next = RX_NEG_EDGE;
end else begin
state_next = RX_CLK_HIGH;
end
end
TX_FORCE_CLK_LOW:begin // the client wishes to transmit a byte to the device
ps2_clk_en_next = 1'b1; // this is done by holding ps2_clk down for at least 100us
ps2_clk_out_next = 1'b0; // bringing down ps2_data, wait 20us and then releasing
if(counter == CLOCK_CNT_100US)begin // the ps2_clk.
state_next = TX_BRING_DATA_LOW; // This constitutes a request to send command.
counter_next = 0; // In this state, the ps2_clk line is held down and
end else begin // the counter for waiting 100us is enabled.
state_next = TX_FORCE_CLK_LOW; // when the counter reached upper limit, transition
counter_next = counter + 1'b1; // to TX_BRING_DATA_LOW
end
end
TX_BRING_DATA_LOW:begin // with the ps2_clk line low bring ps2_data low
ps2_clk_en_next = 1'b1; // wait for 20us and then go to TX_RELEASE_CLK
ps2_clk_out_next = 1'b0;
// set data line low
// when clock is released in the next state
// the device will read bit 0 on data line
// and this bit represents the start bit.
ps2_data_en_next = 1'b1;
ps2_data_out_next = 1'b0;
if(counter == CLOCK_CNT_20US)begin
state_next = TX_RELEASE_CLK;
counter_next = 0;
end else begin
state_next = TX_BRING_DATA_LOW;
counter_next = counter + 1'b1;
end
end
TX_RELEASE_CLK:begin // release the ps2_clk line
ps2_clk_en_next = 1'b0; // keep holding data line low
ps2_data_en_next = 1'b1;
ps2_data_out_next = 1'b0;
state_next = TX_WAIT_FIRTS_NEG_EDGE;
end
TX_WAIT_FIRTS_NEG_EDGE:begin // state is necessary because the clock signal
ps2_data_en_next = 1'b1; // is not released instantaneously and, because of debounce,
ps2_data_out_next = 1'b0; // delay is even greater.
if(counter == 14'd63)begin // Wait 63 clock periods for the clock line to release
if(ps2_clk_s == 1'b0)begin // then if clock is low then go to tx_clk_l
state_next = TX_CLK_LOW; // else wait until ps2_clk goes low.
counter_next = 0;
end else begin
state_next = TX_WAIT_FIRTS_NEG_EDGE;
counter_next = counter;
end
end else begin
state_next = TX_WAIT_FIRTS_NEG_EDGE;
counter_next = counter + 1'b1;
end
end
TX_CLK_LOW:begin // place the least significant bit from frame
ps2_data_en_next = 1'b1; // on the data line
ps2_data_out_next = frame[0]; // During this state the frame is shifted one
state_next = TX_WAIT_POS_EDGE; // bit to the right
end
TX_WAIT_POS_EDGE:begin // wait for the clock to go high
ps2_data_en_next = 1'b1; // this is the edge on which the device reads the data
ps2_data_out_next = frame[0]; // on ps2_data.
if(bits_count == BITS_NUM-1)begin // keep holding ps2_data on frame(0) because else
ps2_data_en_next = 1'b0; // will be released by default value.
state_next = TX_WAIT_POS_EDGE_BEFORE_ACK; // Check if sent the last bit and if so, release data line
end else if(ps2_clk_s == 1'b1)begin // and go to state that wait for acknowledge
state_next = TX_CLK_HIGH;
end else begin
state_next = TX_WAIT_POS_EDGE;
end
end
TX_CLK_HIGH:begin // ps2_clk is released, wait for down edge
ps2_data_en_next = 1'b1; // and go to tx_clk_l when arrived
ps2_data_out_next = frame[0];
if(ps2_clk_s == 1'b0)begin
state_next = TX_CLK_LOW;
end else begin
state_next = TX_CLK_HIGH;
end
end
TX_WAIT_POS_EDGE_BEFORE_ACK:begin // release ps2_data and wait for rising edge of ps2_clk
if(ps2_clk_s == 1'b1)begin // once this occurs, transition to tx_wait_ack
state_next = TX_WAIT_ACK;
end else begin
state_next = TX_WAIT_POS_EDGE_BEFORE_ACK;
end
end
TX_WAIT_ACK:begin // wait for the falling edge of the clock line
if(ps2_clk_s == 1'b0)begin // if data line is low when this occurs, the
if(ps2_data_s == 1'b0) begin // ack is received
state_next = TX_RECEIVED_ACK; // else if data line is high, the device did not
end else begin // acknowledge the transimission
state_next = TX_ERROR_NO_ACK;
end
end else begin
state_next = TX_WAIT_ACK;
end
end
TX_RECEIVED_ACK:begin // wait for ps2_clk to be released together with ps2_data
if(ps2_clk_s == 1'b1 && ps2_clk_s == 1'b1)begin // (bus to be idle) and go back to idle state
state_next = IDLE;
end else begin
state_next = TX_RECEIVED_ACK;
end
end
TX_ERROR_NO_ACK:begin
if(ps2_clk_s == 1'b1 && ps2_clk_s == 1'b1)begin // wait for ps2_clk to be released together with ps2_data
err_next = 1'b1; // (bus to be idle) and go back to idle state
state_next = IDLE; // signal error for not receiving ack
end else begin
state_next = TX_ERROR_NO_ACK;
end
end
default:begin // if invalid transition occurred, signal error and
err_next = 1'b1; // go back to idle state
state_next = IDLE;
end
endcase
end
always @ (posedge clk, posedge rst)begin
if(rst)
bits_count <= 0;
else if(state==IDLE)
bits_count <= 0;
else if(state==RX_NEG_EDGE || state==TX_CLK_LOW)
bits_count <= bits_count + 1'b1;
else
bits_count <= bits_count;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYMETAL6S2S_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__DLYMETAL6S2S_BEHAVIORAL_PP_V
/**
* dlymetal6s2s: 6-inverter delay with output from 2nd stage on
* horizontal route.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__dlymetal6s2s (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, VPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYMETAL6S2S_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SEDFXBP_TB_V
`define SKY130_FD_SC_MS__SEDFXBP_TB_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sedfxbp.v"
module top();
// Inputs are registered
reg D;
reg DE;
reg SCD;
reg SCE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
DE = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 DE = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 DE = 1'b1;
#220 SCD = 1'b1;
#240 SCE = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 DE = 1'b0;
#380 SCD = 1'b0;
#400 SCE = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SCE = 1'b1;
#600 SCD = 1'b1;
#620 DE = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SCE = 1'bx;
#760 SCD = 1'bx;
#780 DE = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ms__sedfxbp dut (.D(D), .DE(DE), .SCD(SCD), .SCE(SCE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SEDFXBP_TB_V
|
module mult_wrap (
input ck,
input [63:0] i_a, i_b,
input i_vld,
output [63:0] o_res,
output o_vld
);
// Wires & Registers
wire [63:0] r_t19_res;
reg r_t2_vld, r_t3_vld, r_t4_vld, r_t5_vld, r_t6_vld, r_t7_vld, r_t8_vld, r_t9_vld, r_t10_vld, r_t11_vld, r_t12_vld, r_t13_vld, r_t14_vld, r_t15_vld, r_t16_vld, r_t17_vld, r_t18_vld, r_t19_vld;
// The following example uses a fixed-length pipeline,
// but could be used with any length or a variable length pipeline.
always @(posedge ck) begin
r_t2_vld <= i_vld;
r_t3_vld <= r_t2_vld;
r_t4_vld <= r_t3_vld;
r_t5_vld <= r_t4_vld;
r_t6_vld <= r_t5_vld;
r_t7_vld <= r_t6_vld;
r_t8_vld <= r_t7_vld;
r_t9_vld <= r_t8_vld;
r_t10_vld <= r_t9_vld;
r_t11_vld <= r_t10_vld;
r_t12_vld <= r_t11_vld;
r_t13_vld <= r_t12_vld;
r_t14_vld <= r_t13_vld;
r_t15_vld <= r_t14_vld;
r_t16_vld <= r_t15_vld;
r_t17_vld <= r_t16_vld;
r_t18_vld <= r_t17_vld;
r_t19_vld <= r_t18_vld;
end
// Black box instantiation
mul_64b_int multiplier (.clk(ck), .a(i_a), .b(i_b), .p(r_t19_res));
// Outputs
assign o_res = r_t19_res;
assign o_vld = r_t19_vld;
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFXTP_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__DFXTP_PP_BLACKBOX_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dfxtp (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFXTP_PP_BLACKBOX_V
|
`default_nettype none
//---------------------------------------------------------------------
//-- --
//-- Company: University of Bonn --
//-- Engineer: John Bieling --
//-- --
//---------------------------------------------------------------------
//-- --
//-- Copyright (C) 2015 John Bieling --
//-- --
//-- This program is free software; you can redistribute it and/or --
//-- modify it under the terms of the GNU General Public License as --
//-- published by the Free Software Foundation; either version 3 of --
//-- the License, or (at your option) any later version. --
//-- --
//-- This program is distributed in the hope that it will be useful, --
//-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
//-- GNU General Public License for more details. --
//-- --
//-- You should have received a copy of the GNU General Public --
//-- License along with this program; if not, see --
//-- <http://www.gnu.org/licenses>. --
//-- --
//---------------------------------------------------------------------
//-- The module can be configured with these parameters (defaults given in braces):
//--
//-- clip_count(1) : sets if the count signal should be clipped.
//-- clip_reset(1) : sets if the reset signal should be clipped.
module dsp_multioption_counter (countClock, count, reset, countout);
parameter clip_count = 1;
parameter clip_reset = 1;
input countClock;
input count;
input reset;
output [31:0] countout;
wire [47:0] DSPOUT;
wire CARRYOUT;
wire [1:0] OPMODE_X = 2'b11; // send {D,A,B} to postadder
wire [1:0] OPMODE_Z = 2'b10; // send P to postadder
wire final_count;
wire final_reset;
//same clip stage as with slimfast_counter
generate
if (clip_count == 0) assign final_count = count; else
if (clip_count == 1)
begin
wire clipped_count;
signal_clipper countclip ( .sig(count), .CLK(countClock), .clipped_sig(clipped_count));
assign final_count = clipped_count;
end else begin // I added this, so that one could switch from "clipped" to "not clipped" without changing the number of flip flop stages
reg piped_count;
always@(posedge countClock)
begin
piped_count <= count;
end
assign final_count = piped_count;
end
if (clip_reset == 0) assign final_reset = reset; else
begin
wire clipped_reset;
signal_clipper resetclip ( .sig(reset), .CLK(countClock), .clipped_sig(clipped_reset));
assign final_reset = clipped_reset;
end
endgenerate
DSP48A1 #(
.A0REG ( 0 ),
.A1REG ( 0 ),
.B0REG ( 0 ),
.B1REG ( 0 ),
.CARRYINREG ( 0 ),
.CARRYINSEL ( "OPMODE5" ),
.CREG ( 0 ),
.DREG ( 0 ),
.MREG ( 0 ),
.OPMODEREG ( 0 ),
.PREG ( 1 ),
.RSTTYPE ( "SYNC" ),
.CARRYOUTREG ( 0 ))
DSP48A1_SLICE (
.CLK(countClock),
//inputs
.A(18'b0),
//counter (31bit) should count in the upper range [47:17] to use the real overflow bit of the DSP
.B(18'b10_00000000_00000000),
.C(48'b0),
.D(18'b0),
//CE
.CEA(1'b0),
.CEB(1'b0),
.CEC(1'b0),
.CED(1'b0),
.CEM(1'b0),
.CEP(final_count),
.CEOPMODE(1'b0),
.CECARRYIN(1'b0),
//resets
.RSTA(1'b0),
.RSTB(1'b0),
.RSTC(1'b0),
.RSTD(1'b0),
.RSTM(1'b0),
.RSTP(final_reset),
.RSTOPMODE(1'b0),
.RSTCARRYIN(1'b0),
//carry inputs
.CARRYIN(1'b0),
.PCIN(48'b0),
//outputs
.CARRYOUTF(CARRYOUT),
.CARRYOUT(), //unconnected
.BCOUT(), //unconnected
.PCOUT(), //unconnected
.M(), //unconnected
.P(DSPOUT),
//OPMODE
.OPMODE({4'b0000,OPMODE_Z,OPMODE_X})
);
//overflow is in phase with DSPOUT (DSPOUT has an internal REG)
reg overflow;
always@(posedge countClock)
begin
if (final_reset == 1'b1) overflow <= 0;
else overflow <= overflow || CARRYOUT;
end
assign countout[30:0] = DSPOUT[47:17];
assign countout[31] = overflow;
endmodule
|
module word(
input [4:0] row, col,
input [1:0] select,
output word
);
reg [19:0] data;
always @(row,col,select,data[19:0])
begin
case (select)
2'b00: case(row) // waiting to start.
5'b00000: data = 20'b00000000000000000000;
5'b00001: data = 20'b00000111111111100000;
5'b00010: data = 20'b00011000000000011000;
5'b00011: data = 20'b00100000000000000100;
5'b00100: data = 20'b01000111000011100010;
5'b00101: data = 20'b01001000100100010010;
5'b00110: data = 20'b01000000000000000010;
5'b00111: data = 20'b01000100000000100010;
5'b01000: data = 20'b00100011111111000100;
5'b01001: data = 20'b00011000000000011000;
5'b01010: data = 20'b00000111111111100000;
5'b01011: data = 20'b00000000000000000000;
5'b01100: data = 20'b00000000000000000000;
5'b01101: data = 20'b00011111000011110000;
5'b01110: data = 20'b00100000000100001000;
5'b01111: data = 20'b00100000001000000100;
5'b10000: data = 20'b00100111101000000100;
5'b10001: data = 20'b00100011000100001000;
5'b10010: data = 20'b00011110000011110000;
5'b10011: data = 20'b00000000000000000000;
default: data = 20'bxxxxxxxxxxxxxxxxxxxx;
endcase
2'b01: case(row) // lose
5'b00000: data = 20'b00000000000000000000;
5'b00001: data = 20'b00100011101110111000;
5'b00010: data = 20'b00100010101000100000;
5'b00011: data = 20'b00100010101110111000;
5'b00100: data = 20'b00100010100010100000;
5'b00101: data = 20'b00111011101110111000;
5'b00110: data = 20'b00000000000000000000;
5'b00111: data = 20'b00001110000001110000;
5'b01000: data = 20'b00011111000011111000;
5'b01001: data = 20'b00011111110001111000;
5'b01010: data = 20'b00001111100111110000;
5'b01011: data = 20'b00000011110001100000;
5'b01100: data = 20'b00000001100001000000;
5'b01101: data = 20'b00000000100000000000;
5'b01110: data = 20'b00011110000000000000;
5'b01111: data = 20'b00100000111100100100;
5'b10000: data = 20'b00011100100010100100;
5'b10001: data = 20'b00000010111100011100;
5'b10010: data = 20'b00000010100010000100;
5'b10011: data = 20'b00111100100010011000;
default: data = 20'bxxxxxxxxxxxxxxxxxxxx;
endcase
2'b10: case(row) // nothing
default: data = 20'bxxxxxxxxxxxxxxxxxxxx;
endcase
2'b11: case(row) // win
5'b00000: data = 20'b00000000000000101010;
5'b00001: data = 20'b00001000010000101010;
5'b00010: data = 20'b00111100111100110110;
5'b00011: data = 20'b01100111100110000000;
5'b00100: data = 20'b01000011000110011100;
5'b00101: data = 20'b00110000001100001000;
5'b00110: data = 20'b00011100111000011100;
5'b00111: data = 20'b00000111100000000000;
5'b01000: data = 20'b00000011000000110100;
5'b01001: data = 20'b00000010000000101100;
5'b01010: data = 20'b00000000000000100100;
5'b01011: data = 20'b00111000001110000001;
5'b01100: data = 20'b01000100010001000001;
5'b01101: data = 20'b01000100010001000010;
5'b01110: data = 20'b01000100010001000010;
5'b01111: data = 20'b01000100010001000100;
5'b10000: data = 20'b01000100010001000100;
5'b10001: data = 20'b01000100010001001000;
5'b10010: data = 20'b01000100010001001000;
5'b10011: data = 20'b00111001001110010000;
default: data = 20'bxxxxxxxxxxxxxxxxxxxx;
endcase
default: data = 20'bxxxxxxxxxxxxxxxxxxxx;
endcase
end
assign word = data[19-col];
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_min_wrtrk.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
//
//
// Top level Module: jbi_min_wrtrk
// Where Instantiated: jbi_min
//
// Description: WRI Tracker
//
// The WRI Tracker keeps count of the number of outstanding WRI (received by
// JBI but not yet acknowledged by SCTAG) and the oldest WRI in JBI. This block
// contains 3 counters: one WRI pending counter and two tag counters.
//
// The wri_pend counter is incremented when a WRI is inserted into a
// MemReqQ and decremented when SCTAG gives an acknowledgement (sends Write Ack packet).
// Because no more than one port can have outstanding WRI (issued WRI waiting for ack),
// only one counter is necessary for 4 SCTAGs.
//
// There are two 6-bit tag counters (upper bit to resolve wrap ambiguity):
// new_wri_tag[5:0] increments with each new WRI* received from Jbus (all WRI*
// are assigned a tag #) and oldest_wri_tag is incremented with each WrAck
// received from the SCTAGs.
//
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "jbi.h"
module jbi_min_wrtrk (/*AUTOARG*/
// Outputs
min_oldest_wri_tag, min_pre_wri_tag, wrtrk_new_wri_tag,
wrtrk_rq0_oldest_wri_tag, wrtrk_rq1_oldest_wri_tag,
wrtrk_rq2_oldest_wri_tag, wrtrk_rq3_oldest_wri_tag,
// Inputs
clk, rst_l, cpu_clk, cpu_rst_l, io_jbi_j_ad_ff, parse_wdq_push,
parse_hdr, parse_rw, parse_wrm, parse_subline_req, wdq_wr_vld,
mout_scb0_jbus_wr_ack, mout_scb1_jbus_wr_ack, mout_scb2_jbus_wr_ack,
mout_scb3_jbus_wr_ack
);
input clk;
input rst_l;
input cpu_clk;
input cpu_rst_l;
// Parse Block Interface
input [127:64] io_jbi_j_ad_ff;
input parse_wdq_push;
input parse_hdr;
input parse_rw;
input parse_wrm;
input parse_subline_req;
// Write Decomposition Interface
input wdq_wr_vld; // pushed write txn to a rhq
// Memory Outbound Interface - cpu clock domain
input mout_scb0_jbus_wr_ack;
input mout_scb1_jbus_wr_ack;
input mout_scb2_jbus_wr_ack;
input mout_scb3_jbus_wr_ack;
// To Non-Cache IO
output [`JBI_WRI_TAG_WIDTH-1:0] min_oldest_wri_tag; // same as wrtrk_oldest_wri_tag
output [`JBI_WRI_TAG_WIDTH-1:0] min_pre_wri_tag;
// Request Queue Interface
output [`JBI_WRI_TAG_WIDTH-1:0] wrtrk_new_wri_tag;
output [`JBI_WRI_TAG_WIDTH-1:0] wrtrk_rq0_oldest_wri_tag;
output [`JBI_WRI_TAG_WIDTH-1:0] wrtrk_rq1_oldest_wri_tag;
output [`JBI_WRI_TAG_WIDTH-1:0] wrtrk_rq2_oldest_wri_tag;
output [`JBI_WRI_TAG_WIDTH-1:0] wrtrk_rq3_oldest_wri_tag;
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
wire [`JBI_WRI_TAG_WIDTH-1:0] min_oldest_wri_tag;
wire [`JBI_WRI_TAG_WIDTH-1:0] min_pre_wri_tag;
wire [`JBI_WRI_TAG_WIDTH-1:0] wrtrk_new_wri_tag;
wire [`JBI_WRI_TAG_WIDTH-1:0] wrtrk_rq0_oldest_wri_tag;
wire [`JBI_WRI_TAG_WIDTH-1:0] wrtrk_rq1_oldest_wri_tag;
wire [`JBI_WRI_TAG_WIDTH-1:0] wrtrk_rq2_oldest_wri_tag;
wire [`JBI_WRI_TAG_WIDTH-1:0] wrtrk_rq3_oldest_wri_tag;
////////////////////////////////////////////////////////////////////////
// Local signal declarations
////////////////////////////////////////////////////////////////////////
//
// Code start here
//
wire [`JBI_WRI_TAG_WIDTH-1:0] wrtrk_oldest_wri_tag;
reg [`JBI_WRI_TAG_WIDTH-1:0] next_wrtrk_new_wri_tag;
reg [`JBI_WRI_TAG_WIDTH-1:0] next_wrtrk_oldest_wri_tag;
reg [`JBI_WRI_TAG_WIDTH-1:0] next_min_pre_wri_tag;
wire incr_wrtrk_new_wri_tag;
wire incr_wrtrk_oldest_wri_tag;
wire [5:0] pre_tag_incr;
reg [63:0] be;
//*******************************************************************************
// New WRI Tag (JBUS CLK)
// - assigned to a txn as it exits WDQ
//*******************************************************************************
assign incr_wrtrk_new_wri_tag = wdq_wr_vld;
always @ ( /*AUTOSENSE*/incr_wrtrk_new_wri_tag or wrtrk_new_wri_tag) begin
if (incr_wrtrk_new_wri_tag)
next_wrtrk_new_wri_tag = wrtrk_new_wri_tag + 1'b1;
else
next_wrtrk_new_wri_tag = wrtrk_new_wri_tag;
end
//*******************************************************************************
// Predicted WRI Tag (JBUS CLK)
// - computed as a txn enters WDQ
// - predicts what new_wri_tag would be by calculating the number of WR8 txns
// a WRM will expand to (from right to left, look for 0<-1 transitions in groups
// of 8-bit BE)
// - used for PIO read returns and Mondos
//*******************************************************************************
always @ ( /*AUTOSENSE*/io_jbi_j_ad_ff or parse_wrm) begin
if (parse_wrm)
be = io_jbi_j_ad_ff[127:64];
else
be = { io_jbi_j_ad_ff[127:112], {48{1'b0}} };
end
jbi_min_wrtrk_ptag_sum u_wrtrk_ptag_sum
(.io_jbi_j_ad_ff(be[63:0]),
.pre_tag_incr(pre_tag_incr[5:0])
);
always @ ( /*AUTOSENSE*/min_pre_wri_tag or parse_hdr or parse_rw
or parse_subline_req or parse_wdq_push or parse_wrm
or pre_tag_incr) begin
if (parse_wdq_push & parse_hdr & ~parse_rw) begin
if (parse_wrm | parse_subline_req)
next_min_pre_wri_tag = min_pre_wri_tag
+ {{`JBI_WRI_TAG_WIDTH-6{1'b0}}, pre_tag_incr[5:0]};
else
next_min_pre_wri_tag = min_pre_wri_tag + 1'b1;
end
else
next_min_pre_wri_tag = min_pre_wri_tag;
end
//*******************************************************************************
// Oldest WRI Tag (CPU CLK)
//*******************************************************************************
assign incr_wrtrk_oldest_wri_tag = mout_scb0_jbus_wr_ack
| mout_scb1_jbus_wr_ack
| mout_scb2_jbus_wr_ack
| mout_scb3_jbus_wr_ack;
always @ ( /*AUTOSENSE*/incr_wrtrk_oldest_wri_tag
or wrtrk_oldest_wri_tag) begin
if (incr_wrtrk_oldest_wri_tag)
next_wrtrk_oldest_wri_tag = wrtrk_oldest_wri_tag + 1'b1;
else
next_wrtrk_oldest_wri_tag = wrtrk_oldest_wri_tag;
end
assign min_oldest_wri_tag = wrtrk_oldest_wri_tag;
assign wrtrk_rq0_oldest_wri_tag = wrtrk_oldest_wri_tag;
assign wrtrk_rq1_oldest_wri_tag = wrtrk_oldest_wri_tag;
assign wrtrk_rq2_oldest_wri_tag = wrtrk_oldest_wri_tag;
assign wrtrk_rq3_oldest_wri_tag = wrtrk_oldest_wri_tag;
//*******************************************************************************
// DFFRL Instantiations
//*******************************************************************************
//----------------------
// JBUS CLK
//----------------------
dffrl_ns #(`JBI_WRI_TAG_WIDTH) u_dffrl_wrtrk_new_wri_tag
(.din(next_wrtrk_new_wri_tag),
.clk(clk),
.rst_l(rst_l),
.q(wrtrk_new_wri_tag)
);
dffrl_ns #(`JBI_WRI_TAG_WIDTH) u_dffrl_min_pre_wri_tag
(.din(next_min_pre_wri_tag),
.clk(clk),
.rst_l(rst_l),
.q(min_pre_wri_tag)
);
//----------------------
// CPU CLK
//----------------------
dffrl_ns #(`JBI_WRI_TAG_WIDTH) u_dffrl_wrtrk_oldest_wri_tag
(.din(next_wrtrk_oldest_wri_tag),
.clk(cpu_clk),
.rst_l(cpu_rst_l),
.q(wrtrk_oldest_wri_tag)
);
//*******************************************************************************
// Rule Checks
//*******************************************************************************
//synopsys translate_off
//synopsys translate_on
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-auto-sense-defines-constant:t
// End:
|
module BRD_PACKET_ENGINE (
// input signals
input CLK,
input OUT_TICK,
input ETH_WR_DONE,
input ETH_WR_BUSY,
input ETH_RD_DONE,
input ETH_RD_BUSY,
input ETH_RD_READY,
// input vectors
input [9:0] IN_ETH_STREAM,
input [23:0] PROCESS_TIME,
input [15:0] TEMPERATURE,
input [15:0] V_VCCINT,
input [15:0] V_VCCAUX,
input [7:0] BUTTONS,
input [23:0] ETH_RD_PIX,
input [127:0] USER_STATUS,
// output signals
output ETH_WR_CLK,
output ETH_WR_STB,
output ETH_RD_CLK,
// output vectors
output [9:0] OUT_ETH_STREAM,
// registered output signals
output reg ETH_BUSY,
output reg CTRL_BUSY,
output reg CTRL_STRB,
output reg ETH_WR_GO,
output reg ETH_RD_GO,
output reg ETH_RD_STB,
// registered output vectors
output reg [15:0] CTRL_ENABLES,
output reg [15:0] IMG_SIZE_X,
output reg [15:0] IMG_SIZE_Y,
output reg [399:0] CTRL_COEFF,
output reg [15:0] ETH_WR_START_X,
output reg [15:0] ETH_WR_LINE,
output reg [15:0] ETH_WR_NUM_PIXELS,
output reg [23:0] ETH_WR_PIX,
output reg [15:0] ETH_RD_START_X,
output reg [15:0] ETH_RD_LINE,
output reg [15:0] ETH_RD_NUM_PIXELS,
output reg [7:0] USER_CTRL_EN,
output reg [15:0] USER_CTRL
);
/*******************************************************************
* Parameters
*******************************************************************/
parameter [7:0] FIRMWARE_VERSION = 8'hff;
parameter [39:0] BOARD_TYPE = 40'h53_50_36_30_31;
parameter SERVER_MAC = 48'h00_10_8B_F1_F5_7D;
parameter MY_MAC = 48'h00_10_8B_F1_F5_7E;
parameter OP_CONTROL = 8'h01;
parameter OP_STATUS = 8'h02;
parameter OP_WRITE = 8'h03;
parameter OP_READ = 8'h04;
parameter OP_USER_CONTROL = 8'h05;
parameter MAX_PAYLOAD = 8'd56;
/*******************************************************************
* Local Signal Declarations
*******************************************************************/
// scalar signals
wire in_cke;
wire in_frm;
wire e_rd_stb;
// scalar registers
reg opcode_is_control;
reg snd_ctrl_ack;
reg snd_status_ack;
reg wr_dat_en;
reg snd_wr_ack;
reg rd_rdy_lat;
reg snd_rd_ack;
reg snd_user_ctrl_ack;
reg tx_frm;
// vector signals
wire [7:0] in_dat;
// vector registers
reg [10:0] rx_cnt;
reg [7:0] rx_opcode;
reg [MAX_PAYLOAD:1] pyld_byte_en;
reg [2:0] wr_1_every_3_sr;
reg [10:0] wr_cnt;
reg [15:0] rd_pyld_len;
reg [15:0] rd_tx_cnt;
reg [2:0] rd_1_every_3_sr;
reg [10:0] rd_cnt;
reg [10:0] tx_cnt;
reg [567:0] tx_shift;
/*******************************************************************
* Initial Values
*******************************************************************/
initial begin
rx_cnt = 0;
rx_opcode = 0;
pyld_byte_en = 0;
opcode_is_control = 0;
snd_ctrl_ack = 0;
snd_status_ack = 0;
wr_dat_en = 0;
wr_1_every_3_sr = 0;
wr_cnt = 0;
snd_wr_ack = 0;
rd_pyld_len = 0;
rd_tx_cnt = 0;
rd_rdy_lat = 0;
snd_rd_ack = 0;
rd_1_every_3_sr = 0;
rd_cnt = 0;
snd_user_ctrl_ack = 0;
tx_cnt = 0;
tx_frm = 0;
tx_shift = 0;
end
/*******************************************************************
* Static Assignments
*******************************************************************/
assign ETH_WR_CLK = CLK;
assign ETH_WR_STB = wr_1_every_3_sr[2];
assign ETH_RD_CLK = CLK;
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2016.2
// Copyright (C) 1986-2016 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module sp_find_segment_stn1 (
ph_seg_p_1_1_1_V_read,
th_seg_p_1_1_0_V_read,
th_seg_p_1_1_1_V_read,
cpat_seg_p_1_1_1_V_read,
ap_return_0,
ap_return_1,
ap_return_2,
ap_return_3
);
input [11:0] ph_seg_p_1_1_1_V_read;
input [6:0] th_seg_p_1_1_0_V_read;
input [6:0] th_seg_p_1_1_1_V_read;
input [3:0] cpat_seg_p_1_1_1_V_read;
output [11:0] ap_return_0;
output [3:0] ap_return_1;
output [6:0] ap_return_2;
output [6:0] ap_return_3;
assign ap_return_0 = ph_seg_p_1_1_1_V_read;
assign ap_return_1 = cpat_seg_p_1_1_1_V_read;
assign ap_return_2 = th_seg_p_1_1_0_V_read;
assign ap_return_3 = th_seg_p_1_1_1_V_read;
endmodule //sp_find_segment_stn1
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR4B_PP_SYMBOL_V
`define SKY130_FD_SC_MS__NOR4B_PP_SYMBOL_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nor4b (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D_N ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR4B_PP_SYMBOL_V
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\velocityControlHdl\velocityControlHdl_Transform_ABC_to_dq.v
// Created: 2014-08-25 21:11:09
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: velocityControlHdl_Transform_ABC_to_dq
// Source Path: velocityControlHdl/Transform_ABC_to_dq
// Hierarchy Level: 4
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module velocityControlHdl_Transform_ABC_to_dq
(
phase_currents_0,
phase_currents_1,
sin_coefficient,
cos_coefficient,
d_current,
q_current
);
input signed [17:0] phase_currents_0; // sfix18_En15
input signed [17:0] phase_currents_1; // sfix18_En15
input signed [17:0] sin_coefficient; // sfix18_En16
input signed [17:0] cos_coefficient; // sfix18_En16
output signed [17:0] d_current; // sfix18_En15
output signed [17:0] q_current; // sfix18_En15
wire signed [17:0] Clarke_Transform_out1; // sfix18_En13
wire signed [17:0] Clarke_Transform_out2; // sfix18_En13
wire signed [17:0] Park_Transform_out1; // sfix18_En15
wire signed [17:0] Park_Transform_out2; // sfix18_En15
// <S5>/Clarke_Transform
velocityControlHdl_Clarke_Transform u_Clarke_Transform (.phase_currents_0(phase_currents_0), // sfix18_En15
.phase_currents_1(phase_currents_1), // sfix18_En15
.alpha_current(Clarke_Transform_out1), // sfix18_En13
.beta_current(Clarke_Transform_out2) // sfix18_En13
);
// <S5>/Park_Transform
velocityControlHdl_Park_Transform u_Park_Transform (.sin_coefficient(sin_coefficient), // sfix18_En16
.cos_coefficient(cos_coefficient), // sfix18_En16
.alpha_current(Clarke_Transform_out1), // sfix18_En13
.beta_current(Clarke_Transform_out2), // sfix18_En13
.direct_current(Park_Transform_out1), // sfix18_En15
.quadrature_current(Park_Transform_out2) // sfix18_En15
);
assign d_current = Park_Transform_out1;
assign q_current = Park_Transform_out2;
endmodule // velocityControlHdl_Transform_ABC_to_dq
|
`default_nettype none
module main (input clk,
input sw1,
input sw2,
output c0,
output c1,
output c2,
output c3,
output c4,
output c5,
output c6,
output c7);
//-- Configure the pull-up resistors for clk and rst inputs
wire sw1_p; //-- up input with pull-up
wire sw2_p;
wire up;
wire down;
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 1)
) io_pin (
.PACKAGE_PIN(sw1),
.D_IN_0(sw1_p)
);
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 1)
) io_pin2 (
.PACKAGE_PIN(sw2),
.D_IN_0(sw2_p)
);
debounce d1 (
.clk(clk),
.sw_in(~sw1_p),
.sw_out(up)
);
debounce d2 (
.clk(clk),
.sw_in(~sw2_p),
.sw_out(down)
);
//-- Counter
reg [7:0] counter = 8'h08;
always @(posedge clk) begin
if (up)
counter <= counter + 1;
else
if (down)
counter <= counter - 1;
end
//-- Output the counter's bits
assign {c7,c6,c5,c4,c3,c2,c1,c0} = counter;
endmodule
module debounce(input wire clk,
input wire sw_in,
output wire sw_out);
//------------------------------
//-- CONTROLLER
//------------------------------
//-- fsm states
localparam IDLE = 0; //-- Idle state. Button not pressed
localparam WAIT_1 = 1; //-- Waiting for the stabilization of 1. Butt pressed
localparam PULSE = 2; //-- 1-clk pulse is generated
localparam WAIT_0 = 3; //-- Button released. Waiting for stabilization of 0
//-- Registers for storing the states
reg [1:0] state = IDLE;
reg [1:0] next_state;
//-- Control signals
reg out = 0;
reg timer_ena = 0;
assign sw_out = out;
//-- Transition between states
always @(posedge clk)
state <= next_state;
//-- Control signal generation and next states
always @(*) begin
//-- Default values
next_state = state; //-- Stay in the same state by default
timer_ena = 0;
out = 0;
case (state)
//-- Button not pressed
//-- Remain in this state until the botton is pressed
IDLE: begin
timer_ena = 0;
out = 0;
if (sw_in)
next_state = WAIT_1;
end
//-- Wait until x ms has elapsed
WAIT_1: begin
timer_ena = 1;
out = 0;
if (timer_trig)
next_state = PULSE;
end
PULSE: begin
timer_ena = 0;
out = 1;
next_state = WAIT_0;
end
WAIT_0: begin
timer_ena = 1;
out = 0;
if (timer_trig && sw_in==0)
next_state = IDLE;
end
default: begin
end
endcase
end
assign sw_out = out;
//-- Timer
wire timer_trig;
prescaler #(
.N(16)
) pres0 (
.clk_in(clk),
.ena(timer_ena),
.clk_out(timer_trig)
);
endmodule // debounce
//-- Prescaler N bits
module prescaler(input wire clk_in,
input wire ena,
output wire clk_out);
//-- Bits of the prescaler
parameter N = 22;
//-- N bits counter
reg [N-1:0] count = 0;
//-- The most significant bit is used as output
assign clk_out = count[N-1];
always @(posedge(clk_in)) begin
if (!ena)
count <= 0;
else
count <= count + 1;
end
endmodule /// prescaler
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EDFXBP_TB_V
`define SKY130_FD_SC_LS__EDFXBP_TB_V
/**
* edfxbp: Delay flop with loopback enable, non-inverted clock,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__edfxbp.v"
module top();
// Inputs are registered
reg D;
reg DE;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
DE = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 DE = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 D = 1'b1;
#160 DE = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 D = 1'b0;
#280 DE = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 DE = 1'b1;
#480 D = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 DE = 1'bx;
#600 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ls__edfxbp dut (.D(D), .DE(DE), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__EDFXBP_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_PP_SYMBOL_V
`define SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_PP_SYMBOL_V
/**
* lpflow_clkinvkapwr: Clock tree inverter on keep-alive rail.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_clkinvkapwr (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input KAPWR,
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_CLKINVKAPWR_PP_SYMBOL_V
|
/*
* MBus Copyright 2015 Regents of the University of Michigan
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// Simulation only, not synthesisable
`include "include/mbus_def.v"
module int_action_rom #(
parameter LC_INT_DEPTH = 13
)
(
output [`FUNC_WIDTH*LC_INT_DEPTH-1:0] int_func_id,
output [(`DATA_WIDTH*3)*LC_INT_DEPTH-1:0] int_payload,
output [2*LC_INT_DEPTH-1:0] int_cmd_len
);
wire [`FUNC_WIDTH-1:0] int_func_array [0:LC_INT_DEPTH-1];
wire [(`DATA_WIDTH*3)-1:0] int_payload_array [0:LC_INT_DEPTH-1];
wire [1:0] int_cmd_len_array [0:LC_INT_DEPTH-1];
genvar idx;
generate
for (idx=0; idx<LC_INT_DEPTH; idx=idx+1)
begin: INT_ACTION
assign int_func_id[`FUNC_WIDTH*(idx+1)-1:`FUNC_WIDTH*idx] = int_func_array[idx];
assign int_payload[(`DATA_WIDTH*3)*(idx+1)-1:(`DATA_WIDTH*3)*idx] = int_payload_array[idx];
assign int_cmd_len[2*(idx+1)-1:2*idx] = int_cmd_len_array[idx];
end
endgenerate
/* Interrupt Test case A : RF READ
*
* 1: Read 1 location, write to another layer's RF
* 2: Read 5 locations, write to another layer's RF
* 3: Read 5 locations, stream to another layer's MEM
*
*/
/* Interrupt Test case B : RF WRITE
*
* 1: Write 1 location, length = 1
* 2: Write 3 locations, length = 2
* 3: Write 3 locations, length = 3
*
*/
/* Interrupt Test case C : MEM READ
*
* 1: Read 1 location, write to another layer (MEM)
* 2: Read 10 location, write to another layer (MEM)
* 3: Read 1 location, write to another layer (RF) (length = 2)
* 4: Read 4 location, write to another layer (RF) (length = 2)
* 5: Read 10 location, stream to another layer (MEM), (length = 2)
*
*/
/* Interrupt Test case D: Wake up
* 1: Wake up system only, interrupt length = 0
*/
localparam RF_READ_INT_DEPTH = 3;
localparam RF_WRITE_INT_DEPTH = 3;
localparam MEM_READ_INT_DEPTH = 5;
wire [7:0] rf_read_from [0:RF_READ_INT_DEPTH-1];
wire [7:0] rf_read_length [0:RF_READ_INT_DEPTH-1];
wire [7:0] rf_read_reply_addr[0:RF_READ_INT_DEPTH-1];
wire [7:0] rf_read_reply_loc[0:RF_READ_INT_DEPTH-1];
wire [7:0] rf_write_to [0:5];
wire [23:0] rf_write_data [0:5];
wire [29:0] mem_read_start_addr [0:MEM_READ_INT_DEPTH-1];
wire [7:0] mem_read_reply_addr [0:MEM_READ_INT_DEPTH-1];
wire [19:0] mem_read_length [0:MEM_READ_INT_DEPTH-1];
wire [29:0] mem_read_reply_locs [0:MEM_READ_INT_DEPTH-1];
// RF Read Command Structure, Read RF from this layer and generate something on the MBus
// 8'b Start Addr, 8'b Length, 8'b Reply address (4'b short addr, 4'b functional ID), 8'b Reply location
generate
for (idx=0; idx<RF_READ_INT_DEPTH; idx=idx+1)
begin: RF_READ_INT
assign int_payload_array[idx] = (((rf_read_from[idx]<<24 | rf_read_length[idx]<<16 | rf_read_reply_addr[idx]<<8 | rf_read_reply_loc[idx])<<`DATA_WIDTH*2) | {(`DATA_WIDTH*2){1'b0}});
assign int_cmd_len_array[idx] = 2'b01;
assign int_func_array[idx] = `LC_CMD_RF_READ;
end
endgenerate
// Test Case A1, 1: Read 1 location, write to layer 2's RF
assign rf_read_from[0] = 8'h0; // Read from address 8'h0
assign rf_read_length[0] = 8'h0; // Read 1 loc. (24-bit)
assign rf_read_reply_addr[0] = {4'd4, `LC_CMD_RF_WRITE};// Send to layer 2, with RF write command
assign rf_read_reply_loc[0] = 8'h0; // Send to 8'h0
// Test Case A2, 2: Read 5 locations, write to layer 2's RF
assign rf_read_from[1] = 8'h2; // Read from address 8'h2
assign rf_read_length[1] = 8'h4; // Read 5 loc. (24-bit)
assign rf_read_reply_addr[1] = {4'd4, `LC_CMD_RF_WRITE}; // Send to layer 2, with RF write command
assign rf_read_reply_loc[1] = 8'h2; // Send to 8'h2
// Test Case A3, 3: Read 10 locations, stream to layer 2's MEM
assign rf_read_from[2] = 8'h0; // Read from address 8'h0
assign rf_read_length[2] = 8'd9; // Read 10 loc. (24-bit)
assign rf_read_reply_addr[2] = {4'd4, `LC_CMD_MEM_STREAM, 2'b00};// Stream to layer 2
assign rf_read_reply_loc[2] = 8'd100; // Send to mem location 100
// RF Write Command Structure, Write RF to this layer. No message is generate on the MBus
// 8'b Address, 24'b Data
generate
for (idx=0; idx<RF_WRITE_INT_DEPTH; idx=idx+1)
begin: RF_WRITE_INT
assign int_func_array[RF_READ_INT_DEPTH+idx] = `LC_CMD_RF_WRITE;
end
endgenerate
// Test Case B1, 1: Write 1 location, length = 1
assign rf_write_to[0] = 8'b0; // Write 0xabcdef to address 0
assign rf_write_data[0] = 24'habcdef; //
assign int_cmd_len_array[RF_READ_INT_DEPTH] = 2'b01; // Command length 1
assign int_payload_array[RF_READ_INT_DEPTH] = (((rf_write_to[0]<<24 | rf_write_data[0])<<(`DATA_WIDTH*2)) | {(`DATA_WIDTH*2){1'b0}});
// Test Case B2, 2: Write 3 locations, length = 2
assign rf_write_to[1] = 8'd1; // Write 0x123456 to address 1
assign rf_write_data[1] = 24'h123456; //
assign rf_write_to[2] = 8'd3; // Write 0x987654 to address 3
assign rf_write_data[2] = 24'h987654; //
assign int_cmd_len_array[RF_READ_INT_DEPTH+1] = 2'b10; // Command length 2
assign int_payload_array[RF_READ_INT_DEPTH+1] = (((rf_write_to[1]<<24 | rf_write_data[1])<<(`DATA_WIDTH*2)) | ((rf_write_to[2]<<24 | rf_write_data[2])<<`DATA_WIDTH) | {(`DATA_WIDTH){1'b0}});
// Test Case B3, 3: Write 3 locations, length = 3
assign rf_write_to[3] = 8'd2; // Write 0x123321 to address 2
assign rf_write_data[3] = 24'h123321; //
assign rf_write_to[4] = 8'd4; // Write 0xabccba to address 4
assign rf_write_data[4] = 24'habccba; //
assign rf_write_to[5] = 8'd6; // Write 0x090785 to address 6
assign rf_write_data[5] = 24'h090785; //
assign int_cmd_len_array[RF_READ_INT_DEPTH+2] = 2'b11; // Command length 3
assign int_payload_array[RF_READ_INT_DEPTH+2] = ((rf_write_to[3]<<24 | rf_write_data[3])<<(`DATA_WIDTH*2)) | ((rf_write_to[4]<<24 | rf_write_data[4])<<`DATA_WIDTH) | (rf_write_to[5]<<24 | rf_write_data[5]);
// MEM Read Command Structure, Read MEM to this layer, and generate something on the MBus
// Word 1: 8 bit replay address, 4 bit reserved, 20 bit length
// Word 2: 30 bit start address, 2 bit dont't care
// Word 3: 30 bit destination location, 2 bit don't care
generate
for (idx=0; idx<MEM_READ_INT_DEPTH; idx=idx+1)
begin: MEM_READ_INT
assign int_payload_array[RF_READ_INT_DEPTH + RF_WRITE_INT_DEPTH + idx] = ((((mem_read_reply_addr[idx]<<24) | (4'b0<<20) | mem_read_length[idx])<<(`DATA_WIDTH*2)) | ((mem_read_start_addr[idx]<<2) | 2'b0)<<`DATA_WIDTH) | ((mem_read_reply_locs[idx]<<2) | 2'b0);
assign int_func_array[RF_READ_INT_DEPTH + RF_WRITE_INT_DEPTH + idx] = `LC_CMD_MEM_READ;
end
endgenerate
// Test Case C1, 1: Read 1 location, write to layer 2's MEM
assign mem_read_start_addr[0] = 30'h0; // Read from address 0
assign mem_read_reply_addr[0] = {4'd4, `LC_CMD_MEM_WRITE}; // Write to layer 2's MEM
assign mem_read_length[0] = 20'd0; // Read 1 word
assign mem_read_reply_locs[0] = 30'd1; // Send to address 1
assign int_cmd_len_array[RF_READ_INT_DEPTH+RF_WRITE_INT_DEPTH] = 2'b11;
// Test Case C2, 2: Read 5 location, write to layer 2's MEM
assign mem_read_start_addr[1] = 30'h1; // Read from address 1
assign mem_read_reply_addr[1] = {4'd4, `LC_CMD_MEM_WRITE}; // Write to layer 2's MEM
assign mem_read_length[1] = 20'd4; // Read 5 word
assign mem_read_reply_locs[1] = 30'd2; // Send to address 2
assign int_cmd_len_array[RF_READ_INT_DEPTH+RF_WRITE_INT_DEPTH+1] = 2'b11;
// Test Case C3, 3: Read 1 location, write to layer 1's RF (This should assert from layer 2)
assign mem_read_start_addr[2] = 30'd100; // Read from address 100
assign mem_read_reply_addr[2] = {4'd3, `LC_CMD_RF_WRITE}; // Write to layer 1's RF
assign mem_read_length[2] = 20'd0; // Read 1 word
assign mem_read_reply_locs[2] = 30'd0; // Don't care
assign int_cmd_len_array[RF_READ_INT_DEPTH+RF_WRITE_INT_DEPTH+2] = 2'b10;
// Test Case C4, 4: Read 4 location, write to layer 1'f RF (This should assert from layer 2)
assign mem_read_start_addr[3] = 30'd101; // Read from address 101
assign mem_read_reply_addr[3] = {4'd3, `LC_CMD_RF_WRITE}; // Write to layer 1's RF
assign mem_read_length[3] = 20'd3; // Read 4 word
assign mem_read_reply_locs[3] = 30'd0; // Don't care
assign int_cmd_len_array[RF_READ_INT_DEPTH+RF_WRITE_INT_DEPTH+3] = 2'b10;
// Test Case C5, 5: Read 10 location, stream to layer 2's MEM channel 1
assign mem_read_start_addr[4] = 30'd0; // Read from address 0
assign mem_read_reply_addr[4] = {4'd4, `LC_CMD_MEM_STREAM, 2'b01}; // Write to layer 2, channel 1
assign mem_read_length[4] = 20'd9; // Read 10 word
assign mem_read_reply_locs[4] = 30'd0; // Don't care
assign int_cmd_len_array[RF_READ_INT_DEPTH+RF_WRITE_INT_DEPTH+4] = 2'b10;
// Test case D1, 1: Wake up system only
assign int_cmd_len_array[RF_READ_INT_DEPTH + RF_WRITE_INT_DEPTH + MEM_READ_INT_DEPTH] = 2'b00; // wake up only
assign int_func_array[RF_READ_INT_DEPTH + RF_WRITE_INT_DEPTH + MEM_READ_INT_DEPTH] = 4'b0; // Don't care
assign int_payload_array[RF_READ_INT_DEPTH + RF_WRITE_INT_DEPTH + MEM_READ_INT_DEPTH] = 96'b0; // Don't care
// Test case D2, 2: Invalid interrupt command
assign int_cmd_len_array[RF_READ_INT_DEPTH + RF_WRITE_INT_DEPTH + MEM_READ_INT_DEPTH + 1] = 2'b01;
assign int_func_array[RF_READ_INT_DEPTH + RF_WRITE_INT_DEPTH + MEM_READ_INT_DEPTH + 1] = 4'b1100; // not exist
assign int_payload_array[RF_READ_INT_DEPTH + RF_WRITE_INT_DEPTH + MEM_READ_INT_DEPTH + 1] = 96'b0; // Don't care
endmodule
|
`timescale 1ns / 1ps
// nexys3MIPSSoC is a MIPS implementation originated from COAD projects
// Copyright (C) 2014 @Wenri, @dtopn, @Speed
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module ctrl(clk,
reset,
Inst_in,
zero,
overflow,
MIO_ready,
MemRead,
MemWrite,
ALU_operation,
state_out,
CPU_MIO,
IorD,
IRWrite,
RegDst,
RegWrite,
MemtoReg,
ALUSrcA,
ALUSrcB,
PCSource,
PCWrite,
PCWriteCond,
Beq,
CauseWrite,
IntCause,
EPCWrite,
Co0Write,
Ireq,
Iack,
Enable_i
);
input clk,reset;
input zero,overflow,MIO_ready,Ireq,Enable_i;
input [31:0] Inst_in;
output [2:0] ALU_operation,MemtoReg,PCSource;
output CPU_MIO,MemRead,MemWrite,IorD,IRWrite,RegWrite,ALUSrcA,PCWrite,PCWriteCond,Beq,CauseWrite,IntCause,EPCWrite,Iack,Co0Write;
output [4:0] state_out;
output [1:0] RegDst,ALUSrcB;
wire [4:0] state_out;
wire reset,MIO_ready,Ireq,Enable_i;
reg CPU_MIO,MemRead,MemWrite,IorD,IRWrite,RegWrite,ALUSrcA,PCWrite,PCWriteCond,Beq,CauseWrite,EPCWrite,Iack,Co0Write;
reg [1:0] RegDst,ALUSrcB,IntCause;
reg [2:0] ALU_operation, MemtoReg, PCSource;
reg [4:0] state;
parameter IF = 5'b00000, ID=5'b00001, EX_R= 5'b00010, EX_Mem=5'b00011, EX_I=5'b00100,
Lui_WB=5'b00101, EX_beq=5'b00110, EX_bne= 5'b00111, EX_jr= 5'b01000, EX_JAL=5'b01001,
Exe_J = 5'b01010, MEM_RD=5'b01011, MEM_WD= 5'b01100, WB_R= 5'b01101, WB_I=5'b01110,
WB_LW=5'b01111, EX_jalr=5'b10000, EX_INT=5'b10001, EX_ERET=5'b10010, Error=5'b11111;
parameter AND=3'b000, OR=3'b001, ADD=3'b010, SUB=3'b110, NOR=3'b100, SLT=3'b111, XOR=3'b011, SRL=3'b101;
`define CPU_ctrl_signals {PCSource[2],MemtoReg[2],Co0Write,CauseWrite,EPCWrite,PCWrite,PCWriteCond,IorD,MemRead,MemWrite,IRWrite,MemtoReg[1:0],PCSource[1:0],ALUSrcB,ALUSrcA,RegWrite,RegDst,CPU_MIO}
// EX_INT 0, 1, 1, 0, 0, 0, 0, 0, 00, 11, 01, 0, 0, 00, 0
// EX_ERET 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 00, 00, 11, 0, 0, 00, 0
// EX_JM 1, 0, 0, 0, 0, 0, 00, 10, 11, 0, 0, 00, 0
// IF 1, 0, 0, 1, 0, 1, 00, 00, 01, 0, 0, 00, 1
// IF 0, 0, 0, 0, 0, 0, 00, 00, 11, 0, 0, 00, 0
// 1 0 0 0 0 0 10 10 00 0 0 00 0
//
`define nSignals 22
assign state_out=state;
always @ (posedge clk or posedge reset)
if (reset==1) begin
`CPU_ctrl_signals<=`nSignals'h12821; //12821
ALU_operation<=ADD;
state <= IF;
Iack <= 0;
end
else begin
Iack <= 0;
case (state)
IF: begin
if(MIO_ready) begin
if(Ireq)begin
Iack <= 1;
`CPU_ctrl_signals<=`nSignals'h701A0;
ALU_operation<=SUB;
state <= EX_INT;
end else begin
`CPU_ctrl_signals<=`nSignals'h00060;
ALU_operation<=ADD;
state <= ID;
end
end else begin
state <=IF;
`CPU_ctrl_signals<=`nSignals'h12821;
end
end
ID: if (!Enable_i) begin
`CPU_ctrl_signals<=`nSignals'h00060;
ALU_operation<=ADD;
state <= ID;
end else begin
case (Inst_in[31:26])
6'b000000:begin //R-type OP
`CPU_ctrl_signals<=`nSignals'h00010;
state <= EX_R;
case (Inst_in[5:0])
6'b100000: ALU_operation<=ADD;
6'b100010: ALU_operation<=SUB;
6'b100100: ALU_operation<=AND;
6'b100101: ALU_operation<=OR;
6'b100111: ALU_operation<=NOR;
6'b101010: ALU_operation<=SLT;
6'b000010: ALU_operation<=SRL; //shfit 1bit right
6'b000000: ALU_operation<=XOR;
6'b001000: begin
`CPU_ctrl_signals<=`nSignals'h10010;
ALU_operation<=ADD; state <= EX_jr; end
6'b001001:begin
`CPU_ctrl_signals<=`nSignals'h00208; //rd << current_pc==ori_pc+4
ALU_operation<=ADD; state <=EX_jalr;end
default: ALU_operation <= ADD;
endcase
end
6'b100011:begin //Lw
`CPU_ctrl_signals<=`nSignals'h00050;
ALU_operation<=ADD;
state <= EX_Mem;
end
6'b101011:begin //Sw
`CPU_ctrl_signals<=`nSignals'h00050;
ALU_operation<=ADD;
state <= EX_Mem;
end
6'b000010:begin //Jump
`CPU_ctrl_signals<=`nSignals'h10160;
state <= Exe_J;
end
6'b000100:begin //Beq
`CPU_ctrl_signals<=`nSignals'h08090; Beq<=1;
ALU_operation<= SUB; state <= EX_beq; end
6'b000101:begin //Bne
`CPU_ctrl_signals<=`nSignals'h08090; Beq<=0;
ALU_operation<= SUB; state <= EX_bne; end
6'b000011:begin //Jal
`CPU_ctrl_signals<=`nSignals'h1076c;
state <= EX_JAL;
end
6'b001000:begin //Addi
`CPU_ctrl_signals<=`nSignals'h00050;
ALU_operation <= ADD;
state <= EX_I;
end
6'b001100:begin //Andi
`CPU_ctrl_signals<=`nSignals'h00050;
ALU_operation <= AND;
state <= EX_I;
end
6'b001101:begin //Ori
`CPU_ctrl_signals<=`nSignals'h00050;
ALU_operation <= OR;
state <= EX_I;
end
6'b001110:begin //Xori
`CPU_ctrl_signals<=`nSignals'h00050;
ALU_operation <= XOR;
state <= EX_I;
end
6'b001010:begin //Slti
`CPU_ctrl_signals<=`nSignals'h00050;
ALU_operation <= SLT;
state <= EX_I;
end
6'b001111:begin //Lui
`CPU_ctrl_signals<=`nSignals'h00468;
state <= Lui_WB;
end
6'b010000: if(Inst_in[25]) begin //COP0
case (Inst_in[5:0])
6'b011000: begin
`CPU_ctrl_signals<=`nSignals'h210060;
state <= EX_ERET;
end
default: begin
`CPU_ctrl_signals<=`nSignals'h12821;
state <= Error;
end
endcase
end
default: begin
`CPU_ctrl_signals<=`nSignals'h12821;
state <= Error;
end
endcase
end //end ID
EX_jalr:begin
`CPU_ctrl_signals<=`nSignals'h10018;
ALU_operation<=ADD; state <= EX_jr;
end
EX_Mem:begin
if(Inst_in[31:26]==6'b100011)begin
`CPU_ctrl_signals<=`nSignals'h06051; state <= MEM_RD; end
else if(Inst_in[31:26]==6'b101011)begin
`CPU_ctrl_signals<=`nSignals'h05051; state <= MEM_WD; end
end
MEM_RD:begin
if(MIO_ready)begin
`CPU_ctrl_signals<=`nSignals'h00208; state <= WB_LW; end
else begin
state <=MEM_RD; `CPU_ctrl_signals<=`nSignals'h06050; end
end
MEM_WD:begin
if(MIO_ready)begin
`CPU_ctrl_signals<=`nSignals'h12821;
ALU_operation<=ADD; state <= IF; end
else begin
state <=MEM_WD; `CPU_ctrl_signals<=`nSignals'h05050; end
end
WB_LW:begin
`CPU_ctrl_signals<=`nSignals'h12821;
ALU_operation<=ADD; state <=IF; end
EX_R:begin
`CPU_ctrl_signals<=`nSignals'h0001a; state <= WB_R; end
EX_I:begin
`CPU_ctrl_signals<=`nSignals'h00058; state <= WB_I; end
WB_R:begin
`CPU_ctrl_signals<=`nSignals'h12821;
ALU_operation<=ADD; state <= IF; end
WB_I:begin
`CPU_ctrl_signals<=`nSignals'h12821;
ALU_operation<=ADD; state <= IF; end
Exe_J:begin
`CPU_ctrl_signals<=`nSignals'h12821;
ALU_operation<=ADD; state <= IF; end
EX_bne:begin
`CPU_ctrl_signals<=`nSignals'h12821;
ALU_operation<=ADD; state <= IF; end
EX_beq:begin
`CPU_ctrl_signals<=`nSignals'h12821;
ALU_operation<=ADD; state <= IF; end
EX_jr:begin
`CPU_ctrl_signals<=`nSignals'h12821;
ALU_operation<=ADD; state <= IF; end
EX_JAL:begin
`CPU_ctrl_signals<=`nSignals'h12821;
ALU_operation<=ADD; state <= IF; end
Lui_WB:begin
`CPU_ctrl_signals<=`nSignals'h12821;
ALU_operation<=ADD; state <= IF; end
EX_INT:begin
`CPU_ctrl_signals<=`nSignals'h12821;
ALU_operation<=ADD; state <= IF; end
EX_ERET:begin
`CPU_ctrl_signals<=`nSignals'h12821;
ALU_operation<=ADD; state <= IF; end
Error: state <= Error;
default: begin
`CPU_ctrl_signals<=`nSignals'h12821; Beq<=0;
ALU_operation<=ADD; state <= Error; end
endcase
end
endmodule
|
`timescale 1ns / 1ps
`include "constants.vh"
module tb_Absorb;
reg [263:0] state_in;
reg clk;
reg rst;
reg en;
reg [175:0] data;
wire [263:0] state_out;
wire rdy;
Absorb uut (
.state_in(state_in),
.state_out(state_out),
.clk(clk),
.rst(rst),
.en(en),
.rdy(rdy)
);
integer i;
integer databitlen;
integer counter;
initial begin
databitlen = 176;
data = "Hello WorldHello World";
counter = 0;
state_in = 0;
clk = 0;
rst = 1;
en = 0;
#100;
rst = 0;
$display("[INITIALIZING]");
// for (i=0; i<`nSBox; i=i+1) begin
// state_in = state_in | i<<(i*8);
// end
state_in = 0;
en = 1;
while (databitlen >= `rate) begin
$display("counter %d", counter);
for (i = 0; i < `R_SizeInBytes*8; i = i+8) begin
state_in[i+:8] = state_in[i+:8] ^ data[databitlen - (i+8) +:8];
$display("data: %d %h", databitlen - (i+8), data[databitlen - (i+8) +:8]);
end
$display("state in: %h", state_in);
$display("data: %h", data);
repeat(70*135) begin
#5;
end
if (rdy) begin
state_in = state_out;
$display("state_out: %h", state_out);
counter = counter + 1;
databitlen = databitlen - `rate;
end
end
end
always begin
#5; clk = !clk;
end
always @ (rdy) begin
if (rdy == 1) begin
state_in = state_out;
$display("state_out: %h", state_out);
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21BO_SYMBOL_V
`define SKY130_FD_SC_MS__A21BO_SYMBOL_V
/**
* a21bo: 2-input AND into first input of 2-input OR,
* 2nd input inverted.
*
* X = ((A1 & A2) | (!B1_N))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a21bo (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21BO_SYMBOL_V
|
`include "./Definition.v"
// amin = -86, amax = 98
// bmin = -108, bmax = 94
// 86 + 98 + 1 = 185
// 108 + 94 + 1 = 203
`define SE_a 282 // 1.1 * `ScaleNumber = 281.6
`define SE_b 282 // 1.1 * `ScaleNumber = 281.6
module SaturationEnhancement
(
input signed[ `size_int - 1 : 0 ]CIEa,
input signed[ `size_int - 1 : 0 ]CIEb,
output wire signed[ `size_int - 1 : 0 ]CIEa_out,
output wire signed[ `size_int - 1 : 0 ]CIEb_out
);
assign CIEa_out = ( CIEa * `SE_a ) >> `ScaleBit;
assign CIEb_out = ( CIEb * `SE_b ) >> `ScaleBit;
endmodule
module SaturationEnhancement_testbench;
reg signed[ `size_int - 1 : 0 ]CIEa;
reg signed[ `size_int - 1 : 0 ]CIEb;
wire signed[ `size_int - 1 : 0 ]CIEa_out;
wire signed[ `size_int - 1 : 0 ]CIEb_out;
SaturationEnhancement SaturationEnhancement_test( CIEa, CIEb, CIEa_out, CIEb_out );
initial
begin
// CIEa = 32 * 256 * 6.3496042078727978990068225570775 = 52016
#10 CIEa = 52016;
#10 $display( "old CIEa = %d\tnew CIEa = %d", CIEa, CIEa_out );
// CIEb = 17 * 256 * 6.3496042078727978990068225570775 = 27634
#10 CIEb = 27634;
#10 $display( "old CIEb = %d\tnew CIEb = %d", CIEb, CIEb_out );
#10 $stop;
#10 $finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXTP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__DLXTP_BEHAVIORAL_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dlxtp (
Q ,
D ,
GATE
);
// Module ports
output Q ;
input D ;
input GATE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire GATE_delayed;
wire D_delayed ;
reg notifier ;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N dlatch0 (buf_Q , D_delayed, GATE_delayed, notifier, VPWR, VGND);
buf buf0 (Q , buf_Q );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXTP_BEHAVIORAL_V |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module FIFO_image_filter_img_4_cols_V_shiftReg (
clk,
data,
ce,
a,
q);
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input [DATA_WIDTH-1:0] data;
input ce;
input [ADDR_WIDTH-1:0] a;
output [DATA_WIDTH-1:0] q;
reg[DATA_WIDTH-1:0] SRL_SIG [0:DEPTH-1];
integer i;
always @ (posedge clk)
begin
if (ce)
begin
for (i=0;i<DEPTH-1;i=i+1)
SRL_SIG[i+1] <= SRL_SIG[i];
SRL_SIG[0] <= data;
end
end
assign q = SRL_SIG[a];
endmodule
module FIFO_image_filter_img_4_cols_V (
clk,
reset,
if_empty_n,
if_read_ce,
if_read,
if_dout,
if_full_n,
if_write_ce,
if_write,
if_din);
parameter MEM_STYLE = "shiftreg";
parameter DATA_WIDTH = 32'd12;
parameter ADDR_WIDTH = 32'd2;
parameter DEPTH = 32'd3;
input clk;
input reset;
output if_empty_n;
input if_read_ce;
input if_read;
output[DATA_WIDTH - 1:0] if_dout;
output if_full_n;
input if_write_ce;
input if_write;
input[DATA_WIDTH - 1:0] if_din;
wire[ADDR_WIDTH - 1:0] shiftReg_addr ;
wire[DATA_WIDTH - 1:0] shiftReg_data, shiftReg_q;
reg[ADDR_WIDTH:0] mOutPtr = {(ADDR_WIDTH+1){1'b1}};
reg internal_empty_n = 0, internal_full_n = 1;
assign if_empty_n = internal_empty_n;
assign if_full_n = internal_full_n;
assign shiftReg_data = if_din;
assign if_dout = shiftReg_q;
always @ (posedge clk) begin
if (reset == 1'b1)
begin
mOutPtr <= ~{ADDR_WIDTH+1{1'b0}};
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else begin
if (((if_read & if_read_ce) == 1 & internal_empty_n == 1) &&
((if_write & if_write_ce) == 0 | internal_full_n == 0))
begin
mOutPtr <= mOutPtr -1;
if (mOutPtr == 0)
internal_empty_n <= 1'b0;
internal_full_n <= 1'b1;
end
else if (((if_read & if_read_ce) == 0 | internal_empty_n == 0) &&
((if_write & if_write_ce) == 1 & internal_full_n == 1))
begin
mOutPtr <= mOutPtr +1;
internal_empty_n <= 1'b1;
if (mOutPtr == DEPTH-2)
internal_full_n <= 1'b0;
end
end
end
assign shiftReg_addr = mOutPtr[ADDR_WIDTH] == 1'b0 ? mOutPtr[ADDR_WIDTH-1:0]:{ADDR_WIDTH{1'b0}};
assign shiftReg_ce = (if_write & if_write_ce) & internal_full_n;
FIFO_image_filter_img_4_cols_V_shiftReg
#(
.DATA_WIDTH(DATA_WIDTH),
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH))
U_FIFO_image_filter_img_4_cols_V_ram (
.clk(clk),
.data(shiftReg_data),
.ce(shiftReg_ce),
.a(shiftReg_addr),
.q(shiftReg_q));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAP_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__DECAP_PP_BLACKBOX_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__decap (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAP_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2_LP_V
`define SKY130_FD_SC_LP__NAND2_LP_V
/**
* nand2: 2-input NAND.
*
* Verilog wrapper for nand2 with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand2_lp (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand2_lp (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2_LP_V
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// pe_bhv.v: behavioural description of priority enconder //
// //
// Author: Ameer M. S. Abdelhadi ( [email protected] ; [email protected] ) //
// SRAM-based Modular II-2D-BCAM ; The University of British Columbia , Sep. 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
module pe_bhv
#( parameter OHW = 512 ) // encoder one-hot input width
( input clk , // clock for pipelined priority encoder
input rst , // registers reset for pipelined priority encoder
input [ OHW -1:0] oht , // one-hot input / [ OHW -1:0]
output reg [`log2(OHW)-1:0] bin , // first '1' index/ [`log2(OHW)-1:0]
output reg vld ); // binary is valid if one was found
// behavioural description of priority enconder;
// faster in simulation than the LZD/onehot2bin priority encoder
// first approach; using while loop for for non fixed loop length
// synthesized well with Altera's QuartusII but loop iterations can't exceed 250.
//reg [`log2(OHW)-1:0] binI;
//reg valI ;
always @(*) begin
bin = {`log2(OHW){1'b0}};
vld = oht[bin] ;
while ((!vld) && (bin!=(OHW-1))) begin
bin = bin + 1 ;
vld = oht[bin];
end
end
//assign bin = binI;
//assign vld = vldI;
// second approach; using for loop fixed loop length
// logic inflated if synthesised with Altera's QuartusII
//integer i;
//always @(*) begin
// valid = 1'b0 ;
// binary = {`log2(ONEHOTW){1'b0}};
// for (i=0;i<ONEHOTW;i=i+1) begin
// valid = valid | onehot[i];
// if (!valid) binary = binary + 1;
// end
//end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKBUF_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__CLKBUF_FUNCTIONAL_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__clkbuf (
X,
A
);
// Module ports
output X;
input A;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKBUF_FUNCTIONAL_V |
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_cpu_jtag_debug_module_wrapper (
// inputs:
MonDReg,
break_readreg,
clk,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
// outputs:
jdo,
jrst_n,
st_ready_test_idle,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output jrst_n;
output st_ready_test_idle;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input clk;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
wire [ 37: 0] jdo;
wire jrst_n;
wire [ 37: 0] sr;
wire st_ready_test_idle;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire vji_cdr;
wire [ 1: 0] vji_ir_in;
wire [ 1: 0] vji_ir_out;
wire vji_rti;
wire vji_sdr;
wire vji_tck;
wire vji_tdi;
wire vji_tdo;
wire vji_udr;
wire vji_uir;
//Change the sld_virtual_jtag_basic's defparams to
//switch between a regular Nios II or an internally embedded Nios II.
//For a regular Nios II, sld_mfg_id = 70, sld_type_id = 34.
//For an internally embedded Nios II, slf_mfg_id = 110, sld_type_id = 135.
usb_system_cpu_jtag_debug_module_tck the_usb_system_cpu_jtag_debug_module_tck
(
.MonDReg (MonDReg),
.break_readreg (break_readreg),
.dbrk_hit0_latch (dbrk_hit0_latch),
.dbrk_hit1_latch (dbrk_hit1_latch),
.dbrk_hit2_latch (dbrk_hit2_latch),
.dbrk_hit3_latch (dbrk_hit3_latch),
.debugack (debugack),
.ir_in (vji_ir_in),
.ir_out (vji_ir_out),
.jrst_n (jrst_n),
.jtag_state_rti (vji_rti),
.monitor_error (monitor_error),
.monitor_ready (monitor_ready),
.reset_n (reset_n),
.resetlatch (resetlatch),
.sr (sr),
.st_ready_test_idle (st_ready_test_idle),
.tck (vji_tck),
.tdi (vji_tdi),
.tdo (vji_tdo),
.tracemem_on (tracemem_on),
.tracemem_trcdata (tracemem_trcdata),
.tracemem_tw (tracemem_tw),
.trc_im_addr (trc_im_addr),
.trc_on (trc_on),
.trc_wrap (trc_wrap),
.trigbrktype (trigbrktype),
.trigger_state_1 (trigger_state_1),
.vs_cdr (vji_cdr),
.vs_sdr (vji_sdr),
.vs_uir (vji_uir)
);
usb_system_cpu_jtag_debug_module_sysclk the_usb_system_cpu_jtag_debug_module_sysclk
(
.clk (clk),
.ir_in (vji_ir_in),
.jdo (jdo),
.sr (sr),
.take_action_break_a (take_action_break_a),
.take_action_break_b (take_action_break_b),
.take_action_break_c (take_action_break_c),
.take_action_ocimem_a (take_action_ocimem_a),
.take_action_ocimem_b (take_action_ocimem_b),
.take_action_tracectrl (take_action_tracectrl),
.take_action_tracemem_a (take_action_tracemem_a),
.take_action_tracemem_b (take_action_tracemem_b),
.take_no_action_break_a (take_no_action_break_a),
.take_no_action_break_b (take_no_action_break_b),
.take_no_action_break_c (take_no_action_break_c),
.take_no_action_ocimem_a (take_no_action_ocimem_a),
.take_no_action_tracemem_a (take_no_action_tracemem_a),
.vs_udr (vji_udr),
.vs_uir (vji_uir)
);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign vji_tck = 1'b0;
assign vji_tdi = 1'b0;
assign vji_sdr = 1'b0;
assign vji_cdr = 1'b0;
assign vji_rti = 1'b0;
assign vji_uir = 1'b0;
assign vji_udr = 1'b0;
assign vji_ir_in = 2'b0;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// sld_virtual_jtag_basic usb_system_cpu_jtag_debug_module_phy
// (
// .ir_in (vji_ir_in),
// .ir_out (vji_ir_out),
// .jtag_state_rti (vji_rti),
// .tck (vji_tck),
// .tdi (vji_tdi),
// .tdo (vji_tdo),
// .virtual_state_cdr (vji_cdr),
// .virtual_state_sdr (vji_sdr),
// .virtual_state_udr (vji_udr),
// .virtual_state_uir (vji_uir)
// );
//
// defparam usb_system_cpu_jtag_debug_module_phy.sld_auto_instance_index = "YES",
// usb_system_cpu_jtag_debug_module_phy.sld_instance_index = 0,
// usb_system_cpu_jtag_debug_module_phy.sld_ir_width = 2,
// usb_system_cpu_jtag_debug_module_phy.sld_mfg_id = 70,
// usb_system_cpu_jtag_debug_module_phy.sld_sim_action = "",
// usb_system_cpu_jtag_debug_module_phy.sld_sim_n_scan = 0,
// usb_system_cpu_jtag_debug_module_phy.sld_sim_total_length = 0,
// usb_system_cpu_jtag_debug_module_phy.sld_type_id = 34,
// usb_system_cpu_jtag_debug_module_phy.sld_version = 3;
//
//synthesis read_comments_as_HDL off
endmodule
|
// ghrd_10as066n2_ILC.v
// Generated using ACDS version 17.1 240
`timescale 1 ps / 1 ps
module ghrd_10as066n2_ILC (
input wire [5:0] avmm_addr, // avalon_slave.address
input wire [31:0] avmm_wrdata, // .writedata
input wire avmm_write, // .write
input wire avmm_read, // .read
output wire [31:0] avmm_rddata, // .readdata
input wire clk, // clk.clk
input wire [1:0] irq, // irq.irq
input wire reset_n // reset_n.reset_n
);
interrupt_latency_counter #(
.INTR_TYPE (0),
.CLOCK_RATE (100000000),
.IRQ_PORT_CNT (2)
) ilc (
.reset_n (reset_n), // input, width = 1, reset_n.reset_n
.clk (clk), // input, width = 1, clk.clk
.irq (irq), // input, width = 2, irq.irq
.avmm_addr (avmm_addr), // input, width = 6, avalon_slave.address
.avmm_wrdata (avmm_wrdata), // input, width = 32, .writedata
.avmm_write (avmm_write), // input, width = 1, .write
.avmm_read (avmm_read), // input, width = 1, .read
.avmm_rddata (avmm_rddata) // output, width = 32, .readdata
);
endmodule
|
// Pentevo project (c) NedoPC 2011
//
// NMI generation
`include "../include/tune.v"
module znmi
(
input wire rst_n,
input wire fclk,
input wire zpos,
input wire zneg,
input wire int_start, // when INT starts
input wire [ 1:0] set_nmi, // NMI requests from slavespi and #BF port
input wire imm_nmi, // immediate NMI from breakpoint
input wire clr_nmi, // clear nmi: from zports, pulsed at out to #xxBE
input wire rfsh_n,
input wire m1_n,
input wire mreq_n,
input wire csrom,
input wire [15:0] a,
output reg in_nmi, // when 1, there must be last (#FF) ram page in 0000-3FFF
output wire gen_nmi // NMI generator: when 1, NMI_N=0, otherwise NMI_N=Z
);
reg [1:0] set_nmi_r;
wire set_nmi_now;
reg imm_nmi_r;
wire imm_nmi_now;
reg pending_nmi;
reg in_nmi_2; // active (=1) when NMIed to ROM, after 0066 M1 becomes 0,
// but in_nmi becomes 1 -- ROM switches to #FF RAM
reg [2:0] nmi_count;
reg [1:0] clr_count;
reg pending_clr;
reg last_m1_rom;
reg last_m1_0066;
wire nmi_start;
//remember whether last M1 opcode read was from ROM or RAM
reg m1_n_reg, mreq_n_reg;
reg [1:0] rfsh_n_reg;
always @(posedge fclk) if( zpos )
rfsh_n_reg[0] <= rfsh_n;
always @(posedge fclk)
rfsh_n_reg[1] <= rfsh_n_reg[0];
always @(posedge fclk) if( zpos )
m1_n_reg <= m1_n;
always @(posedge fclk) if( zneg )
mreq_n_reg <= mreq_n;
wire was_m1 = ~(m1_n_reg | mreq_n_reg);
reg was_m1_reg;
always @(posedge fclk)
was_m1_reg <= was_m1;
always @(posedge fclk)
if( was_m1 && (!was_m1_reg) )
last_m1_rom <= csrom && (a[15:14]==2'b00);
always @(posedge fclk)
if( was_m1 && (!was_m1_reg) )
last_m1_0066 <= ( a[15:0]==16'h0066 );
always @(posedge fclk)
set_nmi_r <= set_nmi;
//
assign set_nmi_now = | (set_nmi_r & (~set_nmi) );
always @(posedge fclk)
imm_nmi_r <= imm_nmi;
//
assign imm_nmi_now = | ( (~imm_nmi_r) & imm_nmi );
always @(posedge fclk, negedge rst_n)
if( !rst_n )
pending_nmi <= 1'b0;
else // posedge clk
begin
if( int_start )
pending_nmi <= 1'b0;
else if( set_nmi_now )
pending_nmi <= 1'b1;
end
// actual nmi start
assign nmi_start = (pending_nmi && int_start) || imm_nmi_now;
always @(posedge fclk)
if( clr_nmi )
clr_count <= 2'd3;
else if( rfsh_n_reg[1] && (!rfsh_n_reg[0]) && clr_count[1] )
clr_count <= clr_count - 2'd1;
always @(posedge fclk)
if( clr_nmi )
pending_clr <= 1'b1;
else if( !clr_count[1] )
pending_clr <= 1'b0;
always @(posedge fclk, negedge rst_n)
if( !rst_n )
in_nmi_2 <= 1'b0;
else // posedge fclk
begin
if( nmi_start && (!in_nmi) && last_m1_rom )
in_nmi_2 <= 1'b1;
else if( rfsh_n_reg[1] && (!rfsh_n_reg[0]) && last_m1_0066 )
in_nmi_2 <= 1'b0;
end
always @(posedge fclk, negedge rst_n)
if( !rst_n )
in_nmi <= 1'b0;
else // posedge clk
begin
if( pending_clr && (!clr_count[1]) )
in_nmi <= 1'b0;
else if( (nmi_start && (!in_nmi) && (!last_m1_rom)) ||
(rfsh_n_reg[1] && (!rfsh_n_reg[0]) && last_m1_0066 && in_nmi_2) )
in_nmi <= 1'b1;
end
always @(posedge fclk, negedge rst_n)
if( !rst_n )
nmi_count <= 3'b000;
else if( nmi_start && (!in_nmi) )
nmi_count <= 3'b111;
else if( nmi_count[2] && zpos )
nmi_count <= nmi_count - 3'd1;
assign gen_nmi = nmi_count[2];
endmodule
|
// File : ../RTL/serialInterfaceEngine/usbTxWireArbiter.v
// Generated : 11/10/06 05:37:24
// From : ../RTL/serialInterfaceEngine/usbTxWireArbiter.asf
// By : FSM2VHDL ver. 5.0.0.9
//////////////////////////////////////////////////////////////////////
//// ////
//// usbTxWireArbiter
//// ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/ ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbConstants_h.v"
`include "usbSerialInterfaceEngine_h.v"
module USBTxWireArbiter (SIETxCtrl, SIETxData, SIETxFSRate, SIETxGnt, SIETxReq, SIETxWEn, TxBits, TxCtl, TxFSRate, USBWireRdyIn, USBWireRdyOut, USBWireWEn, clk, prcTxByteCtrl, prcTxByteData, prcTxByteFSRate, prcTxByteGnt, prcTxByteReq, prcTxByteWEn, rst);
input SIETxCtrl;
input [1:0] SIETxData;
input SIETxFSRate;
input SIETxReq;
input SIETxWEn;
input USBWireRdyIn;
input clk;
input prcTxByteCtrl;
input [1:0] prcTxByteData;
input prcTxByteFSRate;
input prcTxByteReq;
input prcTxByteWEn;
input rst;
output SIETxGnt;
output [1:0] TxBits;
output TxCtl;
output TxFSRate;
output USBWireRdyOut;
output USBWireWEn;
output prcTxByteGnt;
wire SIETxCtrl;
wire [1:0] SIETxData;
wire SIETxFSRate;
reg SIETxGnt, next_SIETxGnt;
wire SIETxReq;
wire SIETxWEn;
reg [1:0] TxBits, next_TxBits;
reg TxCtl, next_TxCtl;
reg TxFSRate, next_TxFSRate;
wire USBWireRdyIn;
reg USBWireRdyOut, next_USBWireRdyOut;
reg USBWireWEn, next_USBWireWEn;
wire clk;
wire prcTxByteCtrl;
wire [1:0] prcTxByteData;
wire prcTxByteFSRate;
reg prcTxByteGnt, next_prcTxByteGnt;
wire prcTxByteReq;
wire prcTxByteWEn;
wire rst;
// diagram signals declarations
reg muxSIENotPTXB, next_muxSIENotPTXB;
// BINARY ENCODED state machine: txWireArb
// State codes definitions:
`define START_TARB 2'b00
`define TARB_WAIT_REQ 2'b01
`define PTXB_ACT 2'b10
`define SIE_TX_ACT 2'b11
reg [1:0] CurrState_txWireArb;
reg [1:0] NextState_txWireArb;
// Diagram actions (continuous assignments allowed only: assign ...)
// processTxByte/SIETransmitter mux
always @(USBWireRdyIn)
begin
USBWireRdyOut <= USBWireRdyIn;
end
always @(muxSIENotPTXB or SIETxWEn or SIETxData or
SIETxCtrl or prcTxByteWEn or prcTxByteData or prcTxByteCtrl or
SIETxFSRate or prcTxByteFSRate)
begin
if (muxSIENotPTXB == 1'b1)
begin
USBWireWEn <= SIETxWEn;
TxBits <= SIETxData;
TxCtl <= SIETxCtrl;
TxFSRate <= SIETxFSRate;
end
else
begin
USBWireWEn <= prcTxByteWEn;
TxBits <= prcTxByteData;
TxCtl <= prcTxByteCtrl;
TxFSRate <= prcTxByteFSRate;
end
end
//--------------------------------------------------------------------
// Machine: txWireArb
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (prcTxByteReq or SIETxReq or prcTxByteGnt or muxSIENotPTXB or SIETxGnt or CurrState_txWireArb)
begin : txWireArb_NextState
NextState_txWireArb <= CurrState_txWireArb;
// Set default values for outputs and signals
next_prcTxByteGnt <= prcTxByteGnt;
next_muxSIENotPTXB <= muxSIENotPTXB;
next_SIETxGnt <= SIETxGnt;
case (CurrState_txWireArb)
`START_TARB:
NextState_txWireArb <= `TARB_WAIT_REQ;
`TARB_WAIT_REQ:
if (prcTxByteReq == 1'b1)
begin
NextState_txWireArb <= `PTXB_ACT;
next_prcTxByteGnt <= 1'b1;
next_muxSIENotPTXB <= 1'b0;
end
else if (SIETxReq == 1'b1)
begin
NextState_txWireArb <= `SIE_TX_ACT;
next_SIETxGnt <= 1'b1;
next_muxSIENotPTXB <= 1'b1;
end
`PTXB_ACT:
if (prcTxByteReq == 1'b0)
begin
NextState_txWireArb <= `TARB_WAIT_REQ;
next_prcTxByteGnt <= 1'b0;
end
`SIE_TX_ACT:
if (SIETxReq == 1'b0)
begin
NextState_txWireArb <= `TARB_WAIT_REQ;
next_SIETxGnt <= 1'b0;
end
endcase
end
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : txWireArb_CurrentState
if (rst)
CurrState_txWireArb <= `START_TARB;
else
CurrState_txWireArb <= NextState_txWireArb;
end
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : txWireArb_RegOutput
if (rst)
begin
muxSIENotPTXB <= 1'b0;
prcTxByteGnt <= 1'b0;
SIETxGnt <= 1'b0;
end
else
begin
muxSIENotPTXB <= next_muxSIENotPTXB;
prcTxByteGnt <= next_prcTxByteGnt;
SIETxGnt <= next_SIETxGnt;
end
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DFF_PS_PP_PG_N_SYMBOL_V
`define SKY130_FD_SC_HD__UDP_DFF_PS_PP_PG_N_SYMBOL_V
/**
* udp_dff$PS_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_dff$PS_pp$PG$N (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input NOTIFIER,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DFF_PS_PP_PG_N_SYMBOL_V
|
`include "../include/tune.v"
// Pentevo project (c) NedoPC 2010-2011
//
// mix up border and pixels, add palette and blanks
//
module video_palframe(
input wire clk, // 28MHz clock
input wire hpix,
input wire vpix,
input wire hblank,
input wire vblank,
input wire [ 3:0] pixels,
input wire [ 3:0] border,
input wire atm_palwr,
input wire [ 5:0] atm_paldata,
output reg [ 5:0] palcolor, // just for palette readback
output wire [ 5:0] color
);
wire [ 3:0] zxcolor;
reg win;
reg [3:0] border_r;
// always @(posedge clk)
// win <= hpix & vpix;
//
// always @(posedge clk)
// border_r <= border;
//
// assign zxcolor = win ? pixels : border_r;
assign zxcolor = (hpix&vpix) ? pixels : border;
// palette
reg [5:0] palette [0:15]; // let quartus instantiate it as RAM if needed
always @(posedge clk)
begin
if( atm_palwr )
palette[zxcolor] <= atm_paldata;
palcolor <= palette[zxcolor];
end
assign color = (hblank | vblank) ? 6'd0 : palcolor;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:23:42 10/30/2011
// Design Name: M_uxa_ps2_busctl
// Module Name: /Users/kc5tja/tmp/kestrel/2/nexys2/uxa/ps2io/T_uxa_ps2_busctl.v
// Project Name: ps2io
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: M_uxa_ps2_busctl
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module T_uxa_ps2_busctl;
// Inputs
reg sys_clk_i;
reg sys_reset_i;
reg wb_we_i;
reg wb_stb_i;
reg wb_dat_8_i;
reg wb_dat_9_i;
// Outputs
wire wb_ack_o;
wire rp_inc_o;
wire c_oe_o;
wire d_oe_o;
// Instantiate the Unit Under Test (UUT)
M_uxa_ps2_busctl uut (
.sys_clk_i(sys_clk_i),
.sys_reset_i(sys_reset_i),
.wb_we_i(wb_we_i),
.wb_stb_i(wb_stb_i),
.wb_dat_8_i(wb_dat_8_i),
.wb_dat_9_i(wb_dat_9_i),
.wb_ack_o(wb_ack_o),
.rp_inc_o(rp_inc_o),
.c_oe_o(c_oe_o),
.d_oe_o(d_oe_o)
);
always begin
#40 sys_clk_i = ~sys_clk_i;
end
initial begin
// Initialize Inputs
sys_clk_i = 0;
sys_reset_i = 0;
wb_we_i = 0;
wb_stb_i = 0;
wb_dat_8_i = 0;
wb_dat_9_i = 0;
// Wait 100 ns for global reset to finish
#80; sys_reset_i = 1; #80; sys_reset_i = 0;
#80; if (c_oe_o != 0) begin
$display("clock driver unexpectedly enabled"); $stop;
end
if (d_oe_o != 0) begin
$display("data driver unexpectedly enabled"); $stop;
end
if (wb_ack_o != 0) begin
$display("bus activity detected when there shouldn't be any"); $stop;
end
if (rp_inc_o != 0) begin
$display("FIFO bump control unexpectedly set"); $stop;
end
// Let's try reading from the interface.
wait(~sys_clk_i);
wait(sys_clk_i);
wb_we_i <= 0; wb_stb_i <= 1; #20;
if (wb_ack_o != 1) begin
$display("We expect single-cycle response time from acknowledgement"); $stop;
end
#40;
if (rp_inc_o != 0) begin
$display("Wait for it...wait for it..."); $stop;
end
#20;
if (rp_inc_o != 0) begin
$display("Trick question -- rp_inc_o should never assert for a simple read."); $stop;
end
wb_stb_i <= 0; #80;
// Let's try writing to the interface now. We'll leave the
// data bus inputs set to zero, which should cause our output
// enables to go high. We'll also verify that the FIFO gets
// popped too.
wait(~sys_clk_i);
wait(sys_clk_i);
wb_we_i <= 1; wb_stb_i <= 1; #20;
if (wb_ack_o != 1) begin
$display("We expect single-cycle response time from acknowledgement"); $stop;
end
#40;
if (rp_inc_o != 0) begin
$display("Wait for it...wait for it... (part 2)"); $stop;
end
#20;
if (rp_inc_o != 0) begin
$display("rp_inc should assert for a write, but only after the transaction is logged."); $stop;
end
wb_stb_i <= 0; #80;
// Back-to-back writes should result in repeated FIFO pops.
wait(~sys_clk_i);
wait(sys_clk_i);
wb_we_i <= 1; wb_stb_i <= 1;
wait(~sys_clk_i);
wait(sys_clk_i);
#20;
if (rp_inc_o != 1) begin
$display("First pop should be in progress now."); $stop;
end
wait(~sys_clk_i);
wait(sys_clk_i);
#20;
if (rp_inc_o != 1) begin
$display("Second pop should be in progress now."); $stop;
end
wb_we_i <= 0; wb_stb_i <= 0;
wait(~sys_clk_i);
wait(sys_clk_i);
#20;
if (rp_inc_o != 0) begin
$display("We had two back-to-back writes, not three."); $stop;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__SCHMITTBUF_1_V
`define SKY130_FD_SC_HVL__SCHMITTBUF_1_V
/**
* schmittbuf: Schmitt Trigger Buffer.
*
* Verilog wrapper for schmittbuf with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__schmittbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__schmittbuf_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__schmittbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__schmittbuf_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__schmittbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__SCHMITTBUF_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKBUF_4_V
`define SKY130_FD_SC_MS__CLKBUF_4_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog wrapper for clkbuf with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__clkbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__clkbuf_4 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__clkbuf_4 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__clkbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKBUF_4_V
|
// Double buffering with dual-port RAM
// Uses dual-port RAM to write switches to one section, while reading another to control LEDs.
// Flip SW0 to swap the buffers.
module top (
input clk,
input [15:0] sw,
output [15:0] led,
// not used
input rx,
output tx
);
assign tx = rx; // TODO(#658): Remove this work-around
wire [3:0] addr;
wire ram_out;
wire ram_in;
RAM_SHIFTER #(
.IO_WIDTH(16),
.ADDR_WIDTH(4)
) shifter (
.clk(clk),
.in(sw),
.out(led),
.addr(addr),
.ram_out(ram_out),
.ram_in(ram_in)
);
RAM32X1D #(
.INIT(32'h96A5_96A5)
) ram0 (
.WCLK(clk),
.A4(sw[0]),
.A3(addr[3]),
.A2(addr[2]),
.A1(addr[1]),
.A0(addr[0]),
.DPRA4(~sw[0]),
.DPRA3(addr[3]),
.DPRA2(addr[2]),
.DPRA1(addr[1]),
.DPRA0(addr[0]),
.DPO(ram_out),
.D(ram_in),
.WE(1'b1)
);
endmodule
|
//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
//
//----------------------------------------------------------------------------
//
// *File Name: msp_debug.v
//
// *Module Description:
// MSP430 core debug utility signals
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev: 134 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2012-03-22 21:31:06 +0100 (Don, 22. Mär 2012) $
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module msp_debug (
// OUTPUTs
e_state, // Execution state
i_state, // Instruction fetch state
inst_cycle, // Cycle number within current instruction
inst_full, // Currently executed instruction (full version)
inst_number, // Instruction number since last system reset
inst_pc, // Instruction Program counter
inst_short, // Currently executed instruction (short version)
// INPUTs
mclk, // Main system clock
puc_rst // Main system reset
);
// OUTPUTs
//============
output [8*32-1:0] e_state; // Execution state
output [8*32-1:0] i_state; // Instruction fetch state
output [31:0] inst_cycle; // Cycle number within current instruction
output [8*32-1:0] inst_full; // Currently executed instruction (full version)
output [31:0] inst_number; // Instruction number since last system reset
output [15:0] inst_pc; // Instruction Program counter
output [8*32-1:0] inst_short; // Currently executed instruction (short version)
// INPUTs
//============
input mclk; // Main system clock
input puc_rst; // Main system reset
//=============================================================================
// 1) ASCII FORMATING FUNCTIONS
//=============================================================================
// This function simply concatenates two strings together, ignorning the NULL
// at the end of string2.
// The specified number of space will be inserted between string1 and string2
function [64*8-1:0] myFormat;
input [32*8-1:0] string1;
input [32*8-1:0] string2;
input [3:0] space;
integer i,j;
begin
myFormat = 0;
`ifdef VXL // no +:
`else
j = 0;
for ( i=0; i < 32; i=i+1) // Copy string2
begin
myFormat[8*i +: 8] = string2[8*i +: 8];
if ((string2[8*i +: 8] == 0) && (j == 0)) j=i;
end
for ( i=0; i < space; i=i+1) // Add spaces
myFormat[8*(j+i) +: 8] = " ";
j=j+space;
for ( i=0; i < 32; i=i+1) // Copy string1
myFormat[8*(j+i) +: 8] = string1[8*i +: 8];
`endif
end
endfunction
//=============================================================================
// 2) CONNECTIONS TO MSP430 CORE INTERNALS
//=============================================================================
wire [2:0] i_state_bin = `HIER_MODULE.openMSP430_0.frontend_0.i_state;
wire [3:0] e_state_bin = `HIER_MODULE.openMSP430_0.frontend_0.e_state;
wire decode = `HIER_MODULE.openMSP430_0.frontend_0.decode;
wire [15:0] ir = `HIER_MODULE.openMSP430_0.frontend_0.ir;
wire irq_detect = `HIER_MODULE.openMSP430_0.frontend_0.irq_detect;
wire [3:0] irq_num = `HIER_MODULE.openMSP430_0.frontend_0.irq_num;
wire [15:0] pc = `HIER_MODULE.openMSP430_0.frontend_0.pc;
//=============================================================================
// 3) GENERATE DEBUG SIGNALS
//=============================================================================
// Instruction fetch state
//=========================
reg [8*32-1:0] i_state;
always @(i_state_bin)
case(i_state_bin)
3'h0 : i_state = "IRQ_FETCH";
3'h1 : i_state = "IRQ_DONE";
3'h2 : i_state = "DEC";
3'h3 : i_state = "EXT1";
3'h4 : i_state = "EXT2";
3'h5 : i_state = "IDLE";
default : i_state = "XXXXX";
endcase
// Execution state
//=========================
reg [8*32-1:0] e_state;
always @(e_state_bin)
case(e_state_bin)
4'h2 : e_state = "IRQ_0";
4'h1 : e_state = "IRQ_1";
4'h0 : e_state = "IRQ_2";
4'h3 : e_state = "IRQ_3";
4'h4 : e_state = "IRQ_4";
4'h5 : e_state = "SRC_AD";
4'h6 : e_state = "SRC_RD";
4'h7 : e_state = "SRC_WR";
4'h8 : e_state = "DST_AD";
4'h9 : e_state = "DST_RD";
4'hA : e_state = "DST_WR";
4'hB : e_state = "EXEC";
4'hC : e_state = "JUMP";
4'hD : e_state = "IDLE";
default : e_state = "xxxx";
endcase
// Count instruction number & cycles
//====================================
reg [31:0] inst_number;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) inst_number <= 0;
else if (decode) inst_number <= inst_number+1;
reg [31:0] inst_cycle;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) inst_cycle <= 0;
else if (decode) inst_cycle <= 0;
else inst_cycle <= inst_cycle+1;
// Decode instruction
//====================================
// Buffer opcode
reg [15:0] opcode;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) opcode <= 0;
else if (decode) opcode <= ir;
// Interrupts
reg irq;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) irq <= 1'b1;
else if (decode) irq <= irq_detect;
// Instruction type
reg [8*32-1:0] inst_type;
always @(opcode or irq)
if (irq)
inst_type = "IRQ";
else
case(opcode[15:13])
3'b000 : inst_type = "SIG-OP";
3'b001 : inst_type = "JUMP";
default : inst_type = "TWO-OP";
endcase
// Instructions name
reg [8*32-1:0] inst_name;
always @(opcode or inst_type or irq_num)
if (inst_type=="IRQ")
case(irq_num[3:0])
4'b0000 : inst_name = "IRQ 0";
4'b0001 : inst_name = "IRQ 1";
4'b0010 : inst_name = "IRQ 2";
4'b0011 : inst_name = "IRQ 3";
4'b0100 : inst_name = "IRQ 4";
4'b0101 : inst_name = "IRQ 5";
4'b0110 : inst_name = "IRQ 6";
4'b0111 : inst_name = "IRQ 7";
4'b1000 : inst_name = "IRQ 8";
4'b1001 : inst_name = "IRQ 9";
4'b1010 : inst_name = "IRQ 10";
4'b1011 : inst_name = "IRQ 11";
4'b1100 : inst_name = "IRQ 12";
4'b1101 : inst_name = "IRQ 13";
4'b1110 : inst_name = "NMI";
default : inst_name = "RESET";
endcase
else if (inst_type=="SIG-OP")
case(opcode[15:7])
9'b000100_000 : inst_name = "RRC";
9'b000100_001 : inst_name = "SWPB";
9'b000100_010 : inst_name = "RRA";
9'b000100_011 : inst_name = "SXT";
9'b000100_100 : inst_name = "PUSH";
9'b000100_101 : inst_name = "CALL";
9'b000100_110 : inst_name = "RETI";
default : inst_name = "xxxx";
endcase
else if (inst_type=="JUMP")
case(opcode[15:10])
6'b001_000 : inst_name = "JNE";
6'b001_001 : inst_name = "JEQ";
6'b001_010 : inst_name = "JNC";
6'b001_011 : inst_name = "JC";
6'b001_100 : inst_name = "JN";
6'b001_101 : inst_name = "JGE";
6'b001_110 : inst_name = "JL";
6'b001_111 : inst_name = "JMP";
default : inst_name = "xxxx";
endcase
else if (inst_type=="TWO-OP")
case(opcode[15:12])
4'b0100 : inst_name = "MOV";
4'b0101 : inst_name = "ADD";
4'b0110 : inst_name = "ADDC";
4'b0111 : inst_name = "SUBC";
4'b1000 : inst_name = "SUB";
4'b1001 : inst_name = "CMP";
4'b1010 : inst_name = "DADD";
4'b1011 : inst_name = "BIT";
4'b1100 : inst_name = "BIC";
4'b1101 : inst_name = "BIS";
4'b1110 : inst_name = "XOR";
4'b1111 : inst_name = "AND";
default : inst_name = "xxxx";
endcase
// Instructions byte/word mode
reg [8*32-1:0] inst_bw;
always @(opcode or inst_type)
if (inst_type=="IRQ")
inst_bw = "";
else if (inst_type=="SIG-OP")
inst_bw = opcode[6] ? ".B" : "";
else if (inst_type=="JUMP")
inst_bw = "";
else if (inst_type=="TWO-OP")
inst_bw = opcode[6] ? ".B" : "";
// Source register
reg [8*32-1:0] inst_src;
wire [3:0] src_reg = (inst_type=="SIG-OP") ? opcode[3:0] : opcode[11:8];
always @(src_reg or inst_type)
if (inst_type=="IRQ")
inst_src = "";
else if (inst_type=="JUMP")
inst_src = "";
else if ((inst_type=="SIG-OP") || (inst_type=="TWO-OP"))
case(src_reg)
4'b0000 : inst_src = "r0";
4'b0001 : inst_src = "r1";
4'b0010 : inst_src = "r2";
4'b0011 : inst_src = "r3";
4'b0100 : inst_src = "r4";
4'b0101 : inst_src = "r5";
4'b0110 : inst_src = "r6";
4'b0111 : inst_src = "r7";
4'b1000 : inst_src = "r8";
4'b1001 : inst_src = "r9";
4'b1010 : inst_src = "r10";
4'b1011 : inst_src = "r11";
4'b1100 : inst_src = "r12";
4'b1101 : inst_src = "r13";
4'b1110 : inst_src = "r14";
default : inst_src = "r15";
endcase
// Destination register
reg [8*32-1:0] inst_dst;
always @(opcode or inst_type)
if (inst_type=="IRQ")
inst_dst = "";
else if (inst_type=="SIG-OP")
inst_dst = "";
else if (inst_type=="JUMP")
inst_dst = "";
else if (inst_type=="TWO-OP")
case(opcode[3:0])
4'b0000 : inst_dst = "r0";
4'b0001 : inst_dst = "r1";
4'b0010 : inst_dst = "r2";
4'b0011 : inst_dst = "r3";
4'b0100 : inst_dst = "r4";
4'b0101 : inst_dst = "r5";
4'b0110 : inst_dst = "r6";
4'b0111 : inst_dst = "r7";
4'b1000 : inst_dst = "r8";
4'b1001 : inst_dst = "r9";
4'b1010 : inst_dst = "r10";
4'b1011 : inst_dst = "r11";
4'b1100 : inst_dst = "r12";
4'b1101 : inst_dst = "r13";
4'b1110 : inst_dst = "r14";
default : inst_dst = "r15";
endcase
// Source Addressing mode
reg [8*32-1:0] inst_as;
always @(inst_type or src_reg or opcode or inst_src)
begin
if (inst_type=="IRQ")
inst_as = "";
else if (inst_type=="JUMP")
inst_as = "";
else if (src_reg==4'h3) // Addressing mode using R3
case (opcode[5:4])
2'b11 : inst_as = "#-1";
2'b10 : inst_as = "#2";
2'b01 : inst_as = "#1";
default: inst_as = "#0";
endcase
else if (src_reg==4'h2) // Addressing mode using R2
case (opcode[5:4])
2'b11 : inst_as = "#8";
2'b10 : inst_as = "#4";
2'b01 : inst_as = "&EDE";
default: inst_as = inst_src;
endcase
else if (src_reg==4'h0) // Addressing mode using R0
case (opcode[5:4])
2'b11 : inst_as = "#N";
2'b10 : inst_as = myFormat("@", inst_src, 0);
2'b01 : inst_as = "EDE";
default: inst_as = inst_src;
endcase
else // General Addressing mode
case (opcode[5:4])
2'b11 : begin
inst_as = myFormat("@", inst_src, 0);
inst_as = myFormat(inst_as, "+", 0);
end
2'b10 : inst_as = myFormat("@", inst_src, 0);
2'b01 : begin
inst_as = myFormat("x(", inst_src, 0);
inst_as = myFormat(inst_as, ")", 0);
end
default: inst_as = inst_src;
endcase
end
// Destination Addressing mode
reg [8*32-1:0] inst_ad;
always @(opcode or inst_type or inst_dst)
begin
if (inst_type!="TWO-OP")
inst_ad = "";
else if (opcode[3:0]==4'h2) // Addressing mode using R2
case (opcode[7])
1'b1 : inst_ad = "&EDE";
default: inst_ad = inst_dst;
endcase
else if (opcode[3:0]==4'h0) // Addressing mode using R0
case (opcode[7])
2'b1 : inst_ad = "EDE";
default: inst_ad = inst_dst;
endcase
else // General Addressing mode
case (opcode[7])
2'b1 : begin
inst_ad = myFormat("x(", inst_dst, 0);
inst_ad = myFormat(inst_ad, ")", 0);
end
default: inst_ad = inst_dst;
endcase
end
// Currently executed instruction
//================================
wire [8*32-1:0] inst_short = inst_name;
reg [8*32-1:0] inst_full;
always @(inst_type or inst_name or inst_bw or inst_as or inst_ad)
begin
inst_full = myFormat(inst_name, inst_bw, 0);
inst_full = myFormat(inst_full, inst_as, 1);
if (inst_type=="TWO-OP")
inst_full = myFormat(inst_full, ",", 0);
inst_full = myFormat(inst_full, inst_ad, 1);
if (opcode==16'h4303)
inst_full = "NOP";
if (opcode==`DBG_SWBRK_OP)
inst_full = "SBREAK";
end
// Instruction program counter
//================================
reg [15:0] inst_pc;
always @(posedge mclk or posedge puc_rst)
if (puc_rst) inst_pc <= 16'h0000;
else if (decode) inst_pc <= pc;
endmodule // msp_debug
|
/* This file is part of JT12.
JT12 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 14-2-2016
Based on information posted by Nemesis on:
http://gendev.spritesmind.net/forum/viewtopic.php?t=386&postdays=0&postorder=asc&start=167
Based on jt51_phasegen.v, from JT51
*/
module jt12_top (
input rst, // rst should be at least 6 clk&cen cycles long
input clk, // CPU clock
(* direct_enable *) input cen, // optional clock enable, if not needed leave as 1'b1
input [7:0] din,
input [1:0] addr,
input cs_n,
input wr_n,
output [7:0] dout,
output irq_n,
// Configuration
input en_hifi_pcm, // high to enable PCM interpolation on YM2612 mode
// ADPCM pins
output [19:0] adpcma_addr, // real hardware has 10 pins multiplexed through RMPX pin
output [ 3:0] adpcma_bank,
output adpcma_roe_n, // ADPCM-A ROM output enable
input [ 7:0] adpcma_data, // Data from RAM
output [23:0] adpcmb_addr, // real hardware has 12 pins multiplexed through PMPX pin
input [ 7:0] adpcmb_data,
output adpcmb_roe_n, // ADPCM-B ROM output enable
// I/O pins used by YM2203 embedded YM2149 chip
input [7:0] IOA_in,
input [7:0] IOB_in,
// Separated output
output [ 7:0] psg_A,
output [ 7:0] psg_B,
output [ 7:0] psg_C,
output signed [15:0] fm_snd_left,
output signed [15:0] fm_snd_right,
output signed [15:0] adpcmA_l,
output signed [15:0] adpcmA_r,
output signed [15:0] adpcmB_l,
output signed [15:0] adpcmB_r,
// combined output
output [ 9:0] psg_snd,
output signed [15:0] snd_right, // FM+PSG
output signed [15:0] snd_left, // FM+PSG
output snd_sample,
input [ 7:0] debug_bus,
output [ 7:0] debug_view
);
// parameters to select the features for each chip type
// defaults to YM2612
parameter use_lfo=1, use_ssg=0, num_ch=6, use_pcm=1;
parameter use_adpcm=0;
parameter JT49_DIV=2;
wire flag_A, flag_B, busy;
wire write = !cs_n && !wr_n;
wire clk_en, clk_en_ssg;
// Timers
wire [9:0] value_A;
wire [7:0] value_B;
wire load_A, load_B;
wire enable_irq_A, enable_irq_B;
wire clr_flag_A, clr_flag_B;
wire overflow_A;
wire fast_timers;
wire zero; // Single-clock pulse at the begginig of s1_enters
// LFO
wire [2:0] lfo_freq;
wire lfo_en;
// Operators
wire amsen_IV;
wire [ 2:0] dt1_I;
wire [ 3:0] mul_II;
wire [ 6:0] tl_IV;
wire [ 4:0] keycode_II;
wire [ 4:0] ar_I;
wire [ 4:0] d1r_I;
wire [ 4:0] d2r_I;
wire [ 3:0] rr_I;
wire [ 3:0] sl_I;
wire [ 1:0] ks_II;
// SSG operation
wire ssg_en_I;
wire [2:0] ssg_eg_I;
// envelope operation
wire keyon_I;
wire [9:0] eg_IX;
wire pg_rst_II;
// Channel
wire [10:0] fnum_I;
wire [ 2:0] block_I;
wire [ 1:0] rl;
wire [ 2:0] fb_II;
wire [ 2:0] alg_I;
wire [ 2:0] pms_I;
wire [ 1:0] ams_IV;
// PCM
wire pcm_en, pcm_wr;
wire [ 8:0] pcm;
// Test
wire pg_stop, eg_stop;
wire ch6op;
wire [ 2:0] cur_ch;
wire [ 1:0] cur_op;
// Operator
wire xuse_internal, yuse_internal;
wire xuse_prevprev1, xuse_prev2, yuse_prev1, yuse_prev2;
wire [ 9:0] phase_VIII;
wire s1_enters, s2_enters, s3_enters, s4_enters;
wire rst_int;
// LFO
wire [6:0] lfo_mod;
wire lfo_rst;
// PSG
wire [3:0] psg_addr;
wire [7:0] psg_data, psg_dout;
wire psg_wr_n;
// ADPCM-A
wire [15:0] addr_a;
wire [ 2:0] up_addr, up_lracl;
wire up_start, up_end;
wire [ 7:0] aon_a, lracl;
wire [ 5:0] atl_a; // ADPCM Total Level
wire up_aon;
// APDCM-B
wire acmd_on_b; // Control - Process start, Key On
wire acmd_rep_b; // Control - Repeat
wire acmd_rst_b; // Control - Reset
wire acmd_up_b; // Control - New cmd received
wire [ 1:0] alr_b; // Left / Right
wire [15:0] astart_b; // Start address
wire [15:0] aend_b; // End address
wire [15:0] adeltan_b; // Delta-N
wire [ 7:0] aeg_b; // Envelope Generator Control
wire [ 5:0] adpcma_flags; // ADPMC-A read over flags
wire adpcmb_flag;
wire [ 6:0] flag_ctl;
wire [ 1:0] div_setting;
wire clk_en_2, clk_en_666, clk_en_111, clk_en_55;
assign debug_view = { 4'd0, flag_B, flag_A, div_setting };
generate
if( use_adpcm==1 ) begin: gen_adpcm
wire rst_n;
jt12_rst u_rst(
.rst ( rst ),
.clk ( clk ),
.rst_n ( rst_n )
);
jt10_adpcm_drvA u_adpcm_a(
.rst_n ( rst_n ),
.clk ( clk ),
.cen ( cen ),
.cen6 ( clk_en_666 ), // clk & cen must be 666 kHz
.cen1 ( clk_en_111 ), // clk & cen must be 111 kHz
.addr ( adpcma_addr ), // real hardware has 10 pins multiplexed through RMPX pin
.bank ( adpcma_bank ),
.roe_n ( adpcma_roe_n ), // ADPCM-A ROM output enable
.datain ( adpcma_data ),
// Control Registers
.atl ( atl_a ), // ADPCM Total Level
.addr_in ( addr_a ),
.lracl_in ( lracl ),
.up_start ( up_start ),
.up_end ( up_end ),
.up_addr ( up_addr ),
.up_lracl ( up_lracl ),
.aon_cmd ( aon_a ), // ADPCM ON equivalent to key on for FM
.up_aon ( up_aon ),
// Flags
.flags ( adpcma_flags ),
.clr_flags ( flag_ctl[5:0] ),
.pcm55_l ( adpcmA_l ),
.pcm55_r ( adpcmA_r )
);
/* verilator tracing_on */
jt10_adpcm_drvB u_adpcm_b(
.rst_n ( rst_n ),
.clk ( clk ),
.cen ( cen ),
.cen55 ( clk_en_55 ),
// Control
.acmd_on_b ( acmd_on_b ), // Control - Process start, Key On
.acmd_rep_b ( acmd_rep_b ), // Control - Repeat
.acmd_rst_b ( acmd_rst_b ), // Control - Reset
//.acmd_up_b ( acmd_up_b ), // Control - New command received
.alr_b ( alr_b ), // Left / Right
.astart_b ( astart_b ), // Start address
.aend_b ( aend_b ), // End address
.adeltan_b ( adeltan_b ), // Delta-N
.aeg_b ( aeg_b ), // Envelope Generator Control
// Flag
.flag ( adpcmb_flag ),
.clr_flag ( flag_ctl[6] ),
// memory
.addr ( adpcmb_addr ),
.data ( adpcmb_data ),
.roe_n ( adpcmb_roe_n ),
.pcm55_l ( adpcmB_l ),
.pcm55_r ( adpcmB_r )
);
/* verilator tracing_on */
assign snd_sample = zero;
jt10_acc u_acc(
.clk ( clk ),
.clk_en ( clk_en ),
.op_result ( op_result_hd ),
.rl ( rl ),
.zero ( zero ),
.s1_enters ( s2_enters ),
.s2_enters ( s1_enters ),
.s3_enters ( s4_enters ),
.s4_enters ( s3_enters ),
.cur_ch ( cur_ch ),
.cur_op ( cur_op ),
.alg ( alg_I ),
.adpcmA_l ( adpcmA_l ),
.adpcmA_r ( adpcmA_r ),
.adpcmB_l ( adpcmB_l ),
.adpcmB_r ( adpcmB_r ),
// combined output
.left ( fm_snd_left ),
.right ( fm_snd_right )
);
end else begin : gen_adpcm_no
assign adpcmA_l = 'd0;
assign adpcmA_r = 'd0;
assign adpcmB_l = 'd0;
assign adpcmB_r = 'd0;
assign adpcma_addr = 'd0;
assign adpcma_bank = 'd0;
assign adpcma_roe_n = 'b1;
assign adpcmb_addr = 'd0;
assign adpcmb_roe_n = 'd1;
end
endgenerate
/* verilator tracing_on */
jt12_dout #(.use_ssg(use_ssg),.use_adpcm(use_adpcm)) u_dout(
// .rst_n ( rst_n ),
.clk ( clk ), // CPU clock
.flag_A ( flag_A ),
.flag_B ( flag_B ),
.busy ( busy ),
.adpcma_flags ( adpcma_flags ),
.adpcmb_flag ( adpcmb_flag ),
.psg_dout ( psg_dout ),
.addr ( addr ),
.dout ( dout )
);
/* verilator tracing_on */
jt12_mmr #(.use_ssg(use_ssg),.num_ch(num_ch),.use_pcm(use_pcm), .use_adpcm(use_adpcm))
u_mmr(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ), // external clock enable
.clk_en ( clk_en ), // internal clock enable
.clk_en_2 ( clk_en_2 ), // input cen divided by 2
.clk_en_ssg ( clk_en_ssg), // internal clock enable
.clk_en_666 ( clk_en_666),
.clk_en_111 ( clk_en_111),
.clk_en_55 ( clk_en_55 ),
.din ( din ),
.write ( write ),
.addr ( addr ),
.busy ( busy ),
.ch6op ( ch6op ),
.cur_ch ( cur_ch ),
.cur_op ( cur_op ),
// LFO
.lfo_freq ( lfo_freq ),
.lfo_en ( lfo_en ),
// Timers
.value_A ( value_A ),
.value_B ( value_B ),
.load_A ( load_A ),
.load_B ( load_B ),
.enable_irq_A ( enable_irq_A ),
.enable_irq_B ( enable_irq_B ),
.clr_flag_A ( clr_flag_A ),
.clr_flag_B ( clr_flag_B ),
.flag_A ( flag_A ),
.overflow_A ( overflow_A ),
.fast_timers( fast_timers ),
// PCM
.pcm ( pcm ),
.pcm_en ( pcm_en ),
.pcm_wr ( pcm_wr ),
// ADPCM-A
.aon_a ( aon_a ), // ON
.atl_a ( atl_a ), // TL
.addr_a ( addr_a ), // address latch
.lracl ( lracl ), // L/R ADPCM Channel Level
.up_start ( up_start ), // write enable start address latch
.up_end ( up_end ), // write enable end address latch
.up_addr ( up_addr ), // write enable end address latch
.up_lracl ( up_lracl ),
.up_aon ( up_aon ),
// ADPCM-B
.acmd_on_b ( acmd_on_b ), // Control - Process start, Key On
.acmd_rep_b ( acmd_rep_b ), // Control - Repeat
.acmd_rst_b ( acmd_rst_b ), // Control - Reset
.acmd_up_b ( acmd_up_b ), // Control - New command received
.alr_b ( alr_b ), // Left / Right
.astart_b ( astart_b ), // Start address
.aend_b ( aend_b ), // End address
.adeltan_b ( adeltan_b ), // Delta-N
.aeg_b ( aeg_b ), // Envelope Generator Control
.flag_ctl ( flag_ctl ),
// Operator
.xuse_prevprev1 ( xuse_prevprev1 ),
.xuse_internal ( xuse_internal ),
.yuse_internal ( yuse_internal ),
.xuse_prev2 ( xuse_prev2 ),
.yuse_prev1 ( yuse_prev1 ),
.yuse_prev2 ( yuse_prev2 ),
// PG
.fnum_I ( fnum_I ),
.block_I ( block_I ),
.pg_stop ( pg_stop ),
// EG
.rl ( rl ),
.fb_II ( fb_II ),
.alg_I ( alg_I ),
.pms_I ( pms_I ),
.ams_IV ( ams_IV ),
.amsen_IV ( amsen_IV ),
.dt1_I ( dt1_I ),
.mul_II ( mul_II ),
.tl_IV ( tl_IV ),
.ar_I ( ar_I ),
.d1r_I ( d1r_I ),
.d2r_I ( d2r_I ),
.rr_I ( rr_I ),
.sl_I ( sl_I ),
.ks_II ( ks_II ),
.eg_stop ( eg_stop ),
// SSG operation
.ssg_en_I ( ssg_en_I ),
.ssg_eg_I ( ssg_eg_I ),
.keyon_I ( keyon_I ),
// Operator
.zero ( zero ),
.s1_enters ( s1_enters ),
.s2_enters ( s2_enters ),
.s3_enters ( s3_enters ),
.s4_enters ( s4_enters ),
// PSG interace
.psg_addr ( psg_addr ),
.psg_data ( psg_data ),
.psg_wr_n ( psg_wr_n ),
.debug_bus ( debug_bus ),
.div_setting(div_setting)
);
/* verilator tracing_on */
// YM2203 seems to use a fixed cen/3 clock for the timers, regardless
// of the prescaler setting
wire timer_cen = fast_timers ? cen : clk_en;
jt12_timers #(.num_ch(num_ch)) u_timers (
.clk ( clk ),
.clk_en ( timer_cen ),
.rst ( rst ),
.zero ( zero ),
.value_A ( value_A ),
.value_B ( value_B ),
.load_A ( load_A ),
.load_B ( load_B ),
.enable_irq_A( enable_irq_A ),
.enable_irq_B( enable_irq_B ),
.clr_flag_A ( clr_flag_A ),
.clr_flag_B ( clr_flag_B ),
.flag_A ( flag_A ),
.flag_B ( flag_B ),
.overflow_A ( overflow_A ),
.irq_n ( irq_n )
);
// YM2203 does not have LFO
generate
if( use_lfo== 1) begin : gen_lfo
jt12_lfo u_lfo(
.rst ( rst ),
.clk ( clk ),
.clk_en ( clk_en ),
.zero ( zero ),
`ifdef NOLFO
.lfo_rst ( 1'b1 ),
`else
.lfo_rst ( 1'b0 ),
`endif
.lfo_en ( lfo_en ),
.lfo_freq ( lfo_freq ),
.lfo_mod ( lfo_mod )
);
end else begin : gen_nolfo
assign lfo_mod = 7'd0;
end
endgenerate
// YM2203/YM2610 have a PSG
`ifndef NOSSG
generate
if( use_ssg==1 ) begin : gen_ssg
jt49 #(.COMP(2'b01), .CLKDIV(JT49_DIV))
u_psg( // note that input ports are not multiplexed
.rst_n ( ~rst ),
.clk ( clk ), // signal on positive edge
.clk_en ( clk_en_ssg), // clock enable on negative edge
.addr ( psg_addr ),
.cs_n ( 1'b0 ),
.wr_n ( psg_wr_n ), // write
.din ( psg_data ),
.sound ( psg_snd ), // combined output
.A ( psg_A ),
.B ( psg_B ),
.C ( psg_C ),
.dout ( psg_dout ),
.sel ( 1'b1 ), // half clock speed
// Unused:
.IOA_out ( ),
.IOB_out ( ),
.IOA_in ( IOA_in ),
.IOB_in ( IOB_in ),
.sample ( )
);
assign snd_left = fm_snd_left + { 1'b0, psg_snd[9:0],5'd0};
assign snd_right = fm_snd_right + { 1'b0, psg_snd[9:0],5'd0};
end else begin : gen_nossg
assign psg_snd = 10'd0;
assign snd_left = fm_snd_left;
assign snd_right= fm_snd_right;
assign psg_dout = 8'd0;
assign psg_A = 8'd0;
assign psg_B = 8'd0;
assign psg_C = 8'd0;
end
endgenerate
`else
assign psg_snd = 10'd0;
assign snd_left = fm_snd_left;
assign snd_right= fm_snd_right;
assign psg_dout = 8'd0;
`endif
wire [ 8:0] op_result;
wire [13:0] op_result_hd;
`ifndef NOFM
/* verilator tracing_on */
jt12_pg #(.num_ch(num_ch)) u_pg(
.rst ( rst ),
.clk ( clk ),
.clk_en ( clk_en ),
// Channel frequency
.fnum_I ( fnum_I ),
.block_I ( block_I ),
// Operator multiplying
.mul_II ( mul_II ),
// Operator detuning
.dt1_I ( dt1_I ), // same as JT51's DT1
// Phase modulation by LFO
.lfo_mod ( lfo_mod ),
.pms_I ( pms_I ),
// phase operation
.pg_rst_II ( pg_rst_II ),
.pg_stop ( pg_stop ),
.keycode_II ( keycode_II ),
.phase_VIII ( phase_VIII )
);
wire [9:0] eg_V;
jt12_eg #(.num_ch(num_ch)) u_eg(
.rst ( rst ),
.clk ( clk ),
.clk_en ( clk_en ),
.zero ( zero ),
.eg_stop ( eg_stop ),
// envelope configuration
.keycode_II ( keycode_II ),
.arate_I ( ar_I ), // attack rate
.rate1_I ( d1r_I ), // decay rate
.rate2_I ( d2r_I ), // sustain rate
.rrate_I ( rr_I ), // release rate
.sl_I ( sl_I ), // sustain level
.ks_II ( ks_II ), // key scale
// SSG operation
.ssg_en_I ( ssg_en_I ),
.ssg_eg_I ( ssg_eg_I ),
// envelope operation
.keyon_I ( keyon_I ),
// envelope number
.lfo_mod ( lfo_mod ),
.tl_IV ( tl_IV ),
.ams_IV ( ams_IV ),
.amsen_IV ( amsen_IV ),
.eg_V ( eg_V ),
.pg_rst_II ( pg_rst_II )
);
jt12_sh #(.width(10),.stages(4)) u_egpad(
.clk ( clk ),
.clk_en ( clk_en ),
.din ( eg_V ),
.drop ( eg_IX )
);
jt12_op #(.num_ch(num_ch)) u_op(
.rst ( rst ),
.clk ( clk ),
.clk_en ( clk_en ),
.pg_phase_VIII ( phase_VIII ),
.eg_atten_IX ( eg_IX ),
.fb_II ( fb_II ),
.test_214 ( 1'b0 ),
.s1_enters ( s1_enters ),
.s2_enters ( s2_enters ),
.s3_enters ( s3_enters ),
.s4_enters ( s4_enters ),
.xuse_prevprev1 ( xuse_prevprev1),
.xuse_internal ( xuse_internal ),
.yuse_internal ( yuse_internal ),
.xuse_prev2 ( xuse_prev2 ),
.yuse_prev1 ( yuse_prev1 ),
.yuse_prev2 ( yuse_prev2 ),
.zero ( zero ),
.op_result ( op_result ),
.full_result ( op_result_hd )
);
`else
assign op_result = 'd0;
assign op_result_hd = 'd0;
`endif
/* verilator tracing_on */
generate
if( use_pcm==1 ) begin: gen_pcm_acc // YM2612 accumulator
assign fm_snd_right[3:0] = 4'd0;
assign fm_snd_left [3:0] = 4'd0;
assign snd_sample = zero;
reg signed [8:0] pcm2;
// interpolate PCM samples with automatic sample rate detection
// this feature is not present in original YM2612
// this improves PCM sample sound greatly
/*
jt12_pcm u_pcm(
.rst ( rst ),
.clk ( clk ),
.clk_en ( clk_en ),
.zero ( zero ),
.pcm ( pcm ),
.pcm_wr ( pcm_wr ),
.pcm_resampled ( pcm2 )
);
*/
wire rst_pcm_n;
jt12_rst u_rst_pcm(
.rst ( rst ),
.clk ( clk ),
.rst_n ( rst_pcm_n )
);
`ifndef NOPCMLINEAR
wire signed [10:0] pcm_full;
always @(*)
pcm2 = en_hifi_pcm ? pcm_full[9:1] : pcm;
jt12_pcm_interpol #(.dw(11), .stepw(5)) u_pcm (
.rst_n ( rst_pcm_n ),
.clk ( clk ),
.cen ( clk_en ),
.cen55 ( clk_en_55 ),
.pcm_wr( pcm_wr ),
.pcmin ( {pcm[8],pcm, 1'b0} ),
.pcmout( pcm_full )
);
`else
assign pcm2 = pcm;
`endif
jt12_acc u_acc(
.rst ( rst ),
.clk ( clk ),
.clk_en ( clk_en ),
.op_result ( op_result ),
.rl ( rl ),
// note that the order changes to deal
// with the operator pipeline delay
.zero ( zero ),
.s1_enters ( s2_enters ),
.s2_enters ( s1_enters ),
.s3_enters ( s4_enters ),
.s4_enters ( s3_enters ),
.ch6op ( ch6op ),
.pcm_en ( pcm_en ), // only enabled for channel 6
.pcm ( pcm2 ),
.alg ( alg_I ),
// combined output
.left ( fm_snd_left [15:4] ),
.right ( fm_snd_right[15:4] )
);
end
if( use_pcm==0 && use_adpcm==0 ) begin : gen_2203_acc // YM2203 accumulator
wire signed [15:0] mono_snd;
assign fm_snd_left = mono_snd;
assign fm_snd_right = mono_snd;
assign snd_sample = zero;
jt03_acc u_acc(
.rst ( rst ),
.clk ( clk ),
.clk_en ( clk_en ),
.op_result ( op_result_hd ),
// note that the order changes to deal
// with the operator pipeline delay
.s1_enters ( s1_enters ),
.s2_enters ( s2_enters ),
.s3_enters ( s3_enters ),
.s4_enters ( s4_enters ),
.alg ( alg_I ),
.zero ( zero ),
// combined output
.snd ( mono_snd )
);
end
endgenerate
endmodule
|
/* Copyright (C) 2015-2016 by John Cronin
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
module uart(clk, TxD, TxD_data, TxD_start, TxD_busy, RxD, RxD_data, RxD_ready, RxD_read);
input clk;
input [7:0] TxD_data;
input TxD_start;
output TxD;
output TxD_busy;
input RxD;
output [7:0] RxD_data;
output RxD_ready;
input RxD_read;
parameter Counter = 1302;
localparam Counter8 = Counter >> 3; // 1/8th of a counter tick
reg [7:0] chr = 8'h48;
reg [7:0] state = 0;
reg [12:0] count = 0;
// Transmit circuit
always @(posedge clk)
if(count == 0)
case (state)
8'b00000000: if(TxD_start) { chr, state, count } <= { TxD_data, 8'b11000000, 13'd1 }; else { state, count } <= { 8'd0, 13'd0 };
8'b11000000: { state, count } <= { 8'b10100000, 13'd1 };
8'b10100000: { state, count } <= { 8'b10100001, 13'd1 };
8'b10100001: { state, count } <= { 8'b10100010, 13'd1 };
8'b10100010: { state, count } <= { 8'b10100011, 13'd1 };
8'b10100011: { state, count } <= { 8'b10100100, 13'd1 };
8'b10100100: { state, count } <= { 8'b10100101, 13'd1 };
8'b10100101: { state, count } <= { 8'b10100110, 13'd1 };
8'b10100110: { state, count } <= { 8'b10100111, 13'd1 };
8'b10100111: { state, count } <= { 8'b10010000, 13'd1 };
8'b10010000: { state, count } <= { 8'b10010001, 13'd1 };
default: { state, count } <= { 8'b00000000, 13'd0 };
endcase
else
if(count == Counter)
count <= 13'd0;
else
count <= count + 13'd1;
assign TxD = (state[6:5] == 0) | (state[5] & chr[state[2:0]]);
assign TxD_busy = state != 0;
// Receive circuit
reg [7:0] RxD_data = 8'd0;
reg [3:0] RxD_state = 4'd0;
reg [3:0] RxD_filter = 4'd0;
reg RxD_filtered = 1'b0;
reg [2:0] RxD_filter_idx = 3'd0;
reg [12:0] RxD_count = 13'd0;
reg stop_bit = 1'b0;
/* Filter the incoming data by sampling it 8 times a baud tick and choosing the
middle 4 bits to actually sample
We start our reading once a start bit is read */
// 2 bits set = logic 1 else logic 0
always @(posedge clk)
case(RxD_filter)
4'b0000, 4'b0001, 4'b0010, 4'b0100, 4'b1000: RxD_filtered <= 1'b0;
default: RxD_filtered <= 1'b1;
endcase
always @(posedge clk)
if(~|RxD_state) begin // state 0
if(RxD_read)
stop_bit = 1'b0; // do no further reads when RxD held high
if(~RxD)
{ RxD_state, RxD_count } = { 4'd1, 13'd0 }; // reset count when start bit detected
else
{ RxD_state, RxD_count } = { 4'd0, 13'd0 };
end
else
if(RxD_count == Counter8) begin
{ RxD_count, RxD_filter_idx } = { 13'd0, RxD_filter_idx + 3'd1 };
if(RxD_filter_idx == 3'd0) // one baud tick has passed
case(RxD_state)
4'd1: // start bit
if(RxD_filtered)
RxD_state = 4'd0; // invalid start bit
else
RxD_state = 4'd2;
4'd2: { RxD_data[0], RxD_state } = { RxD_filtered, 4'd3 };
4'd3: { RxD_data[1], RxD_state } = { RxD_filtered, 4'd4 };
4'd4: { RxD_data[2], RxD_state } = { RxD_filtered, 4'd5 };
4'd5: { RxD_data[3], RxD_state } = { RxD_filtered, 4'd6 };
4'd6: { RxD_data[4], RxD_state } = { RxD_filtered, 4'd7 };
4'd7: { RxD_data[5], RxD_state } = { RxD_filtered, 4'd8 };
4'd8: { RxD_data[6], RxD_state } = { RxD_filtered, 4'd9 };
4'd9: { RxD_data[7], RxD_state } = { RxD_filtered, 4'd10 };
4'd10: { stop_bit, RxD_state } = { RxD_filtered, 4'd0 };
default: { stop_bit, RxD_state } = { 1'b0, 4'd0 };
endcase
else if(RxD_filter_idx == 3'd2) RxD_filter[0] = RxD;
else if(RxD_filter_idx == 3'd3) RxD_filter[1] = RxD;
else if(RxD_filter_idx == 3'd4) RxD_filter[2] = RxD;
else if(RxD_filter_idx == 3'd5) RxD_filter[3] = RxD;
end
else
RxD_count = RxD_count + 13'd1;
assign RxD_ready = (~|RxD_state & stop_bit);
endmodule
/* Encapsulates the uart class in a MMIO device
Responds to 4-byte aligned accesses only
Registers:
0 - state (RO)
Bit 0 - If set then cannot accept data
Other bits reserved
4 - char buffer (WO)
Write next character to send - will send when able
*/
module uart_mmio(clk, rst_, TxD, data, addr, cs_, oe_, we_);
input clk;
input rst_;
output TxD;
inout [7:0] data;
input [7:0] addr;
input cs_;
input oe_;
input we_;
parameter Counter = 2604;
localparam REGS = 8;
reg [7:0] r[0:REGS - 1];
reg TxD_start = 0;
wire TxD_busy;
integer i;
assign data = (~cs_ & ~oe_) ? r[addr] : 8'bzzzzzzzz;
uart #(Counter) u(.clk(clk), .TxD(TxD), .TxD_busy(TxD_busy), .TxD_data(r[4]), .TxD_start(TxD_start));
always @(posedge clk)
r[0] = { 7'b0, TxD_busy };
`ifndef USE_RST_LOGIC
initial
for(i = 0; i < REGS; i=i+1) r[i] = 8'd0;
`endif
//always @(posedge clk or negedge rst_)
always @(posedge clk)
`ifdef USE_RST_LOGIC
if(~rst_)
{ r[1], r[2], r[3], r[4], r[5], r[6], r[7], TxD_start } <= { 8'b0, 8'b0, 8'b0, 8'b0, 8'b0, 8'b0, 8'b0, 1'b0 };
else
`endif
if(~cs_ & ~we_)
case(addr)
8'd4:
if(~TxD_busy)
{ r[4], TxD_start } <= { data, 1'b1 };
else
TxD_start <= 1'b0;
default:
TxD_start <= 1'b0;
endcase
else
TxD_start <= 1'b0;
//begin
//r[0] = { 7'b0, TxD_busy };
/*r[1] = 8'b0;
r[2] = 8'b0;
r[3] = 8'b0;
r[5] = 8'b0;
r[6] = 8'b0;
r[7] = 8'b0;*/
/*TxD_start = 1'b0;
if(~cs_ & ~we_)
case(addr)
8'd4:
if(~TxD_busy)
{ r[4], TxD_start } = { data, 1'b1 };
endcase
end*/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD1_SYMBOL_V
`define SKY130_FD_SC_HD__DLYGATE4SD1_SYMBOL_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlygate4sd1 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD1_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4BB_SYMBOL_V
`define SKY130_FD_SC_LP__NOR4BB_SYMBOL_V
/**
* nor4bb: 4-input NOR, first two inputs inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nor4bb (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N,
input D_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4BB_SYMBOL_V
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
// Date : Tue Mar 29 14:16:29 2016
// Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/Users/SKL/Desktop/ECE532/quadencoder/encoder_ip_prj2/encoder_ip_prj.srcs/sources_1/ip/dcfifo_32in_32out_32kb/dcfifo_32in_32out_32kb_funcsim.v
// Design : dcfifo_32in_32out_32kb
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "dcfifo_32in_32out_32kb,fifo_generator_v12_0,{}" *) (* core_generation_info = "dcfifo_32in_32out_32kb,fifo_generator_v12_0,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=10,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=1,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=1,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=1kx36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=1021,C_PROG_FULL_THRESH_NEGATE_VAL=1020,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=3,C_RD_DEPTH=1024,C_RD_FREQ=1,C_RD_PNTR_WIDTH=10,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=2,C_WR_DEPTH=1024,C_WR_FREQ=1,C_WR_PNTR_WIDTH=10,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYPE_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}" *) (* downgradeipidentifiedwarnings = "yes" *)
(* x_core_info = "fifo_generator_v12_0,Vivado 2015.1" *)
(* NotValidForBitStream *)
module dcfifo_32in_32out_32kb
(rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
rd_data_count,
wr_data_count);
input rst;
(* x_interface_info = "xilinx.com:signal:clock:1.0 write_clk CLK" *) input wr_clk;
(* x_interface_info = "xilinx.com:signal:clock:1.0 read_clk CLK" *) input rd_clk;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [31:0]din;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [31:0]dout;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty;
output [2:0]rd_data_count;
output [1:0]wr_data_count;
wire [31:0]din;
wire [31:0]dout;
wire empty;
wire full;
wire rd_clk;
wire [2:0]rd_data_count;
wire rd_en;
wire rst;
wire wr_clk;
wire [1:0]wr_data_count;
wire wr_en;
wire NLW_U0_almost_empty_UNCONNECTED;
wire NLW_U0_almost_full_UNCONNECTED;
wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_overflow_UNCONNECTED;
wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_underflow_UNCONNECTED;
wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_overflow_UNCONNECTED;
wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_underflow_UNCONNECTED;
wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
wire NLW_U0_axi_b_overflow_UNCONNECTED;
wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
wire NLW_U0_axi_b_prog_full_UNCONNECTED;
wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
wire NLW_U0_axi_b_underflow_UNCONNECTED;
wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
wire NLW_U0_axi_r_overflow_UNCONNECTED;
wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
wire NLW_U0_axi_r_prog_full_UNCONNECTED;
wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
wire NLW_U0_axi_r_underflow_UNCONNECTED;
wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
wire NLW_U0_axi_w_overflow_UNCONNECTED;
wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
wire NLW_U0_axi_w_prog_full_UNCONNECTED;
wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
wire NLW_U0_axi_w_underflow_UNCONNECTED;
wire NLW_U0_axis_dbiterr_UNCONNECTED;
wire NLW_U0_axis_overflow_UNCONNECTED;
wire NLW_U0_axis_prog_empty_UNCONNECTED;
wire NLW_U0_axis_prog_full_UNCONNECTED;
wire NLW_U0_axis_sbiterr_UNCONNECTED;
wire NLW_U0_axis_underflow_UNCONNECTED;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_m_axi_arvalid_UNCONNECTED;
wire NLW_U0_m_axi_awvalid_UNCONNECTED;
wire NLW_U0_m_axi_bready_UNCONNECTED;
wire NLW_U0_m_axi_rready_UNCONNECTED;
wire NLW_U0_m_axi_wlast_UNCONNECTED;
wire NLW_U0_m_axi_wvalid_UNCONNECTED;
wire NLW_U0_m_axis_tlast_UNCONNECTED;
wire NLW_U0_m_axis_tvalid_UNCONNECTED;
wire NLW_U0_overflow_UNCONNECTED;
wire NLW_U0_prog_empty_UNCONNECTED;
wire NLW_U0_prog_full_UNCONNECTED;
wire NLW_U0_rd_rst_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_s_axis_tready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire NLW_U0_underflow_UNCONNECTED;
wire NLW_U0_valid_UNCONNECTED;
wire NLW_U0_wr_ack_UNCONNECTED;
wire NLW_U0_wr_rst_busy_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
wire [9:0]NLW_U0_data_count_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "0" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "10" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "32" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "32" *)
(* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "32" *)
(* C_DIN_WIDTH_WDCH = "64" *)
(* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "32" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "artix7" *)
(* C_FULL_FLAGS_RST_VAL = "1" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "1" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "1" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "2" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *)
(* C_PRELOAD_REGS = "0" *)
(* C_PRIM_FIFO_TYPE = "1kx36" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *)
(* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "1021" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "1020" *)
(* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "3" *)
(* C_RD_DEPTH = "1024" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "10" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "2" *)
(* C_WR_DEPTH = "1024" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "10" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
dcfifo_32in_32out_32kb_fifo_generator_v12_0 U0
(.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
.almost_full(NLW_U0_almost_full_UNCONNECTED),
.axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
.axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
.axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
.axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
.axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
.axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
.axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
.axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
.axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
.axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
.axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
.axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
.axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
.axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
.axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
.axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
.axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
.axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
.axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
.axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
.axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
.axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
.axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
.axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
.axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
.axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
.axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
.axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
.axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
.axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
.axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),
.axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
.axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),
.axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
.axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
.axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.data_count(NLW_U0_data_count_UNCONNECTED[9:0]),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
.m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
.m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(1'b0),
.m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
.m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
.m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
.m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(1'b0),
.m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
.m_axi_bid(1'b0),
.m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
.m_axi_bresp({1'b0,1'b0}),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
.m_axi_rresp({1'b0,1'b0}),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
.m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
.m_axi_wready(1'b0),
.m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
.m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
.m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),
.m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
.m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
.m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),
.m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),
.m_axis_tready(1'b0),
.m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),
.m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),
.m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),
.overflow(NLW_U0_overflow_UNCONNECTED),
.prog_empty(NLW_U0_prog_empty_UNCONNECTED),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full(NLW_U0_prog_full_UNCONNECTED),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.rd_rst(1'b0),
.rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
.rst(rst),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot({1'b0,1'b0,1'b0}),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot({1'b0,1'b0,1'b0}),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.srst(1'b0),
.underflow(NLW_U0_underflow_UNCONNECTED),
.valid(NLW_U0_valid_UNCONNECTED),
.wr_ack(NLW_U0_wr_ack_UNCONNECTED),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en),
.wr_rst(1'b0),
.wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module dcfifo_32in_32out_32kb_blk_mem_gen_generic_cstr
(dout,
E,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [31:0]dout;
input [0:0]E;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [31:0]din;
wire [0:0]E;
wire [0:0]Q;
wire [31:0]din;
wire [31:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
dcfifo_32in_32out_32kb_blk_mem_gen_prim_width \ramloop[0].ram.r
(.E(E),
.Q(Q),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module dcfifo_32in_32out_32kb_blk_mem_gen_prim_width
(dout,
E,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [31:0]dout;
input [0:0]E;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [31:0]din;
wire [0:0]E;
wire [0:0]Q;
wire [31:0]din;
wire [31:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
dcfifo_32in_32out_32kb_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.E(E),
.Q(Q),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module dcfifo_32in_32out_32kb_blk_mem_gen_prim_wrapper
(dout,
E,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [31:0]dout;
input [0:0]E;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [31:0]din;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_72 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_73 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_74 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_75 ;
wire [0:0]E;
wire [0:0]Q;
wire [31:0]din;
wire [31:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_42(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\gic0.gc0.count_d2_reg[9] ,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[9] ,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(wr_clk),
.CLKBWRCLK(rd_clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI(din),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO(dout),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_72 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_73 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_74 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_75 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(E),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(Q),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({E,E,E,E}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module dcfifo_32in_32out_32kb_blk_mem_gen_top
(dout,
E,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [31:0]dout;
input [0:0]E;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [31:0]din;
wire [0:0]E;
wire [0:0]Q;
wire [31:0]din;
wire [31:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
dcfifo_32in_32out_32kb_blk_mem_gen_generic_cstr \valid.cstr
(.E(E),
.Q(Q),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_2" *)
module dcfifo_32in_32out_32kb_blk_mem_gen_v8_2
(dout,
E,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [31:0]dout;
input [0:0]E;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [31:0]din;
wire [0:0]E;
wire [0:0]Q;
wire [31:0]din;
wire [31:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
dcfifo_32in_32out_32kb_blk_mem_gen_v8_2_synth inst_blk_mem_gen
(.E(E),
.Q(Q),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_2_synth" *)
module dcfifo_32in_32out_32kb_blk_mem_gen_v8_2_synth
(dout,
E,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [31:0]dout;
input [0:0]E;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [31:0]din;
wire [0:0]E;
wire [0:0]Q;
wire [31:0]din;
wire [31:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
dcfifo_32in_32out_32kb_blk_mem_gen_top \gnativebmg.native_blk_mem_gen
(.E(E),
.Q(Q),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "clk_x_pntrs" *)
module dcfifo_32in_32out_32kb_clk_x_pntrs
(S,
WR_PNTR_RD,
\rd_dc_i_reg[7] ,
\rd_dc_i_reg[7]_0 ,
v1_reg,
v1_reg_0,
RD_PNTR_WR,
v1_reg_1,
ram_full_i,
Q,
\gc0.count_reg[9] ,
\gic0.gc0.count_d1_reg[9] ,
\gic0.gc0.count_reg[9] ,
comp2,
p_1_out,
wr_en,
comp1,
rst_full_gen_i,
\gic0.gc0.count_d2_reg[9] ,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [1:0]S;
output [9:0]WR_PNTR_RD;
output [3:0]\rd_dc_i_reg[7] ;
output [3:0]\rd_dc_i_reg[7]_0 ;
output [4:0]v1_reg;
output [4:0]v1_reg_0;
output [9:0]RD_PNTR_WR;
output [4:0]v1_reg_1;
output ram_full_i;
input [9:0]Q;
input [9:0]\gc0.count_reg[9] ;
input [9:0]\gic0.gc0.count_d1_reg[9] ;
input [9:0]\gic0.gc0.count_reg[9] ;
input comp2;
input p_1_out;
input wr_en;
input comp1;
input rst_full_gen_i;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [9:0]Q;
wire [9:0]RD_PNTR_WR;
wire [1:0]S;
wire [9:0]WR_PNTR_RD;
wire comp1;
wire comp2;
wire [9:0]\gc0.count_reg[9] ;
wire [9:0]\gic0.gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [9:0]\gic0.gc0.count_reg[9] ;
wire \gsync_stage[2].wr_stg_inst_n_1 ;
wire \gsync_stage[2].wr_stg_inst_n_2 ;
wire \gsync_stage[2].wr_stg_inst_n_3 ;
wire \gsync_stage[2].wr_stg_inst_n_4 ;
wire \gsync_stage[2].wr_stg_inst_n_5 ;
wire \gsync_stage[2].wr_stg_inst_n_6 ;
wire \gsync_stage[2].wr_stg_inst_n_7 ;
wire \gsync_stage[2].wr_stg_inst_n_8 ;
wire \gsync_stage[2].wr_stg_inst_n_9 ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire [8:0]p_0_in;
wire [8:0]p_0_in8_out;
wire [9:9]p_0_out;
wire p_1_out;
wire [9:9]p_1_out_0;
wire [9:0]p_2_out;
wire [9:0]p_3_out;
wire ram_full_i;
wire rd_clk;
wire [3:0]\rd_dc_i_reg[7] ;
wire [3:0]\rd_dc_i_reg[7]_0 ;
wire [9:0]rd_pntr_gc;
wire \rd_pntr_gc[0]_i_1_n_0 ;
wire \rd_pntr_gc[1]_i_1_n_0 ;
wire \rd_pntr_gc[2]_i_1_n_0 ;
wire \rd_pntr_gc[3]_i_1_n_0 ;
wire \rd_pntr_gc[4]_i_1_n_0 ;
wire \rd_pntr_gc[5]_i_1_n_0 ;
wire \rd_pntr_gc[6]_i_1_n_0 ;
wire \rd_pntr_gc[7]_i_1_n_0 ;
wire \rd_pntr_gc[8]_i_1_n_0 ;
wire rst_full_gen_i;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
wire [4:0]v1_reg_1;
wire wr_clk;
wire wr_en;
wire [9:0]wr_pntr_gc;
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__0
(.I0(WR_PNTR_RD[1]),
.I1(\gc0.count_reg[9] [1]),
.I2(WR_PNTR_RD[0]),
.I3(\gc0.count_reg[9] [0]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__1
(.I0(RD_PNTR_WR[1]),
.I1(\gic0.gc0.count_d1_reg[9] [1]),
.I2(RD_PNTR_WR[0]),
.I3(\gic0.gc0.count_d1_reg[9] [0]),
.O(v1_reg_0[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__2
(.I0(RD_PNTR_WR[1]),
.I1(\gic0.gc0.count_reg[9] [1]),
.I2(RD_PNTR_WR[0]),
.I3(\gic0.gc0.count_reg[9] [0]),
.O(v1_reg_1[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__0
(.I0(WR_PNTR_RD[3]),
.I1(\gc0.count_reg[9] [3]),
.I2(WR_PNTR_RD[2]),
.I3(\gc0.count_reg[9] [2]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__1
(.I0(RD_PNTR_WR[3]),
.I1(\gic0.gc0.count_d1_reg[9] [3]),
.I2(RD_PNTR_WR[2]),
.I3(\gic0.gc0.count_d1_reg[9] [2]),
.O(v1_reg_0[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__2
(.I0(RD_PNTR_WR[3]),
.I1(\gic0.gc0.count_reg[9] [3]),
.I2(RD_PNTR_WR[2]),
.I3(\gic0.gc0.count_reg[9] [2]),
.O(v1_reg_1[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__0
(.I0(WR_PNTR_RD[5]),
.I1(\gc0.count_reg[9] [5]),
.I2(WR_PNTR_RD[4]),
.I3(\gc0.count_reg[9] [4]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__1
(.I0(RD_PNTR_WR[5]),
.I1(\gic0.gc0.count_d1_reg[9] [5]),
.I2(RD_PNTR_WR[4]),
.I3(\gic0.gc0.count_d1_reg[9] [4]),
.O(v1_reg_0[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__2
(.I0(RD_PNTR_WR[5]),
.I1(\gic0.gc0.count_reg[9] [5]),
.I2(RD_PNTR_WR[4]),
.I3(\gic0.gc0.count_reg[9] [4]),
.O(v1_reg_1[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__0
(.I0(WR_PNTR_RD[7]),
.I1(\gc0.count_reg[9] [7]),
.I2(WR_PNTR_RD[6]),
.I3(\gc0.count_reg[9] [6]),
.O(v1_reg[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__1
(.I0(RD_PNTR_WR[7]),
.I1(\gic0.gc0.count_d1_reg[9] [7]),
.I2(RD_PNTR_WR[6]),
.I3(\gic0.gc0.count_d1_reg[9] [6]),
.O(v1_reg_0[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__2
(.I0(RD_PNTR_WR[7]),
.I1(\gic0.gc0.count_reg[9] [7]),
.I2(RD_PNTR_WR[6]),
.I3(\gic0.gc0.count_reg[9] [6]),
.O(v1_reg_1[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__0
(.I0(WR_PNTR_RD[9]),
.I1(\gc0.count_reg[9] [9]),
.I2(WR_PNTR_RD[8]),
.I3(\gc0.count_reg[9] [8]),
.O(v1_reg[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__1
(.I0(RD_PNTR_WR[9]),
.I1(\gic0.gc0.count_d1_reg[9] [9]),
.I2(RD_PNTR_WR[8]),
.I3(\gic0.gc0.count_d1_reg[9] [8]),
.O(v1_reg_0[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__2
(.I0(RD_PNTR_WR[9]),
.I1(\gic0.gc0.count_reg[9] [9]),
.I2(RD_PNTR_WR[8]),
.I3(\gic0.gc0.count_reg[9] [8]),
.O(v1_reg_1[4]));
dcfifo_32in_32out_32kb_synchronizer_ff \gsync_stage[1].rd_stg_inst
(.D(p_3_out),
.Q(wr_pntr_gc),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.rd_clk(rd_clk));
dcfifo_32in_32out_32kb_synchronizer_ff_3 \gsync_stage[1].wr_stg_inst
(.D(p_2_out),
.Q(rd_pntr_gc),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] (\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.wr_clk(wr_clk));
dcfifo_32in_32out_32kb_synchronizer_ff_4 \gsync_stage[2].rd_stg_inst
(.D(p_0_in),
.\Q_reg_reg[9]_0 (p_3_out),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.out(p_1_out_0),
.rd_clk(rd_clk));
dcfifo_32in_32out_32kb_synchronizer_ff_5 \gsync_stage[2].wr_stg_inst
(.D({\gsync_stage[2].wr_stg_inst_n_1 ,\gsync_stage[2].wr_stg_inst_n_2 ,\gsync_stage[2].wr_stg_inst_n_3 ,\gsync_stage[2].wr_stg_inst_n_4 ,\gsync_stage[2].wr_stg_inst_n_5 ,\gsync_stage[2].wr_stg_inst_n_6 ,\gsync_stage[2].wr_stg_inst_n_7 ,\gsync_stage[2].wr_stg_inst_n_8 ,\gsync_stage[2].wr_stg_inst_n_9 }),
.\Q_reg_reg[9]_0 (p_2_out),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] (\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.out(p_0_out),
.wr_clk(wr_clk));
LUT5 #(
.INIT(32'h0000FF20))
ram_full_i_i_1
(.I0(comp2),
.I1(p_1_out),
.I2(wr_en),
.I3(comp1),
.I4(rst_full_gen_i),
.O(ram_full_i));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[7]_i_10
(.I0(WR_PNTR_RD[0]),
.I1(Q[0]),
.O(\rd_dc_i_reg[7]_0 [0]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[7]_i_3
(.I0(WR_PNTR_RD[7]),
.I1(Q[7]),
.O(\rd_dc_i_reg[7] [3]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[7]_i_4
(.I0(WR_PNTR_RD[6]),
.I1(Q[6]),
.O(\rd_dc_i_reg[7] [2]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[7]_i_5
(.I0(WR_PNTR_RD[5]),
.I1(Q[5]),
.O(\rd_dc_i_reg[7] [1]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[7]_i_6
(.I0(WR_PNTR_RD[4]),
.I1(Q[4]),
.O(\rd_dc_i_reg[7] [0]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[7]_i_7
(.I0(WR_PNTR_RD[3]),
.I1(Q[3]),
.O(\rd_dc_i_reg[7]_0 [3]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[7]_i_8
(.I0(WR_PNTR_RD[2]),
.I1(Q[2]),
.O(\rd_dc_i_reg[7]_0 [2]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[7]_i_9
(.I0(WR_PNTR_RD[1]),
.I1(Q[1]),
.O(\rd_dc_i_reg[7]_0 [1]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[9]_i_2
(.I0(WR_PNTR_RD[9]),
.I1(Q[9]),
.O(S[1]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[9]_i_3
(.I0(WR_PNTR_RD[8]),
.I1(Q[8]),
.O(S[0]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_9 ),
.Q(RD_PNTR_WR[0]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_8 ),
.Q(RD_PNTR_WR[1]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_7 ),
.Q(RD_PNTR_WR[2]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_6 ),
.Q(RD_PNTR_WR[3]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_5 ),
.Q(RD_PNTR_WR[4]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_4 ),
.Q(RD_PNTR_WR[5]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_3 ),
.Q(RD_PNTR_WR[6]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_2 ),
.Q(RD_PNTR_WR[7]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gsync_stage[2].wr_stg_inst_n_1 ),
.Q(RD_PNTR_WR[8]));
FDCE #(
.INIT(1'b0))
\rd_pntr_bin_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_out),
.Q(RD_PNTR_WR[9]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[0]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(\rd_pntr_gc[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[1]_i_1
(.I0(Q[1]),
.I1(Q[2]),
.O(\rd_pntr_gc[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[2]_i_1
(.I0(Q[2]),
.I1(Q[3]),
.O(\rd_pntr_gc[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[3]_i_1
(.I0(Q[3]),
.I1(Q[4]),
.O(\rd_pntr_gc[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[4]_i_1
(.I0(Q[4]),
.I1(Q[5]),
.O(\rd_pntr_gc[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[5]_i_1
(.I0(Q[5]),
.I1(Q[6]),
.O(\rd_pntr_gc[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[6]_i_1
(.I0(Q[6]),
.I1(Q[7]),
.O(\rd_pntr_gc[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[7]_i_1
(.I0(Q[7]),
.I1(Q[8]),
.O(\rd_pntr_gc[7]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\rd_pntr_gc[8]_i_1
(.I0(Q[8]),
.I1(Q[9]),
.O(\rd_pntr_gc[8]_i_1_n_0 ));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[0]_i_1_n_0 ),
.Q(rd_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[1]_i_1_n_0 ),
.Q(rd_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[2]_i_1_n_0 ),
.Q(rd_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[3]_i_1_n_0 ),
.Q(rd_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[4]_i_1_n_0 ),
.Q(rd_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[5]_i_1_n_0 ),
.Q(rd_pntr_gc[5]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[6]_i_1_n_0 ),
.Q(rd_pntr_gc[6]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[7]_i_1_n_0 ),
.Q(rd_pntr_gc[7]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\rd_pntr_gc[8]_i_1_n_0 ),
.Q(rd_pntr_gc[8]));
FDCE #(
.INIT(1'b0))
\rd_pntr_gc_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[9]),
.Q(rd_pntr_gc[9]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[0]),
.Q(WR_PNTR_RD[0]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[1]),
.Q(WR_PNTR_RD[1]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[2]),
.Q(WR_PNTR_RD[2]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[3]),
.Q(WR_PNTR_RD[3]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[4]),
.Q(WR_PNTR_RD[4]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[5]),
.Q(WR_PNTR_RD[5]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[6]),
.Q(WR_PNTR_RD[6]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[7]),
.Q(WR_PNTR_RD[7]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_in[8]),
.Q(WR_PNTR_RD[8]));
FDCE #(
.INIT(1'b0))
\wr_pntr_bin_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_1_out_0),
.Q(WR_PNTR_RD[9]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[0]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [0]),
.I1(\gic0.gc0.count_d2_reg[9] [1]),
.O(p_0_in8_out[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[1]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [1]),
.I1(\gic0.gc0.count_d2_reg[9] [2]),
.O(p_0_in8_out[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[2]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [2]),
.I1(\gic0.gc0.count_d2_reg[9] [3]),
.O(p_0_in8_out[2]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[3]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [3]),
.I1(\gic0.gc0.count_d2_reg[9] [4]),
.O(p_0_in8_out[3]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[4]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [4]),
.I1(\gic0.gc0.count_d2_reg[9] [5]),
.O(p_0_in8_out[4]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[5]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [5]),
.I1(\gic0.gc0.count_d2_reg[9] [6]),
.O(p_0_in8_out[5]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[6]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [6]),
.I1(\gic0.gc0.count_d2_reg[9] [7]),
.O(p_0_in8_out[6]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[7]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [7]),
.I1(\gic0.gc0.count_d2_reg[9] [8]),
.O(p_0_in8_out[7]));
LUT2 #(
.INIT(4'h6))
\wr_pntr_gc[8]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [8]),
.I1(\gic0.gc0.count_d2_reg[9] [9]),
.O(p_0_in8_out[8]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in8_out[0]),
.Q(wr_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in8_out[1]),
.Q(wr_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in8_out[2]),
.Q(wr_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in8_out[3]),
.Q(wr_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in8_out[4]),
.Q(wr_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in8_out[5]),
.Q(wr_pntr_gc[5]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in8_out[6]),
.Q(wr_pntr_gc[6]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in8_out[7]),
.Q(wr_pntr_gc[7]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(p_0_in8_out[8]),
.Q(wr_pntr_gc[8]));
FDCE #(
.INIT(1'b0))
\wr_pntr_gc_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\gic0.gc0.count_d2_reg[9] [9]),
.Q(wr_pntr_gc[9]));
endmodule
(* ORIG_REF_NAME = "compare" *)
module dcfifo_32in_32out_32kb_compare
(comp1,
v1_reg);
output comp1;
input [4:0]v1_reg;
wire comp1;
wire \gmux.gm[3].gms.ms_n_0 ;
wire [4:0]v1_reg;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\gmux.gm[3].gms.ms_n_0 ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\gmux.gm[3].gms.ms_n_0 ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg[4]}));
endmodule
(* ORIG_REF_NAME = "compare" *)
module dcfifo_32in_32out_32kb_compare_0
(comp2,
v1_reg_0);
output comp2;
input [4:0]v1_reg_0;
wire comp2;
wire \gmux.gm[3].gms.ms_n_0 ;
wire [4:0]v1_reg_0;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\gmux.gm[3].gms.ms_n_0 ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_0[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\gmux.gm[3].gms.ms_n_0 ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp2}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg_0[4]}));
endmodule
(* ORIG_REF_NAME = "compare" *)
module dcfifo_32in_32out_32kb_compare_1
(comp0,
v1_reg_0);
output comp0;
input [4:0]v1_reg_0;
wire comp0;
wire \gmux.gm[3].gms.ms_n_0 ;
wire [4:0]v1_reg_0;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\gmux.gm[3].gms.ms_n_0 ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_0[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\gmux.gm[3].gms.ms_n_0 ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp0}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg_0[4]}));
endmodule
(* ORIG_REF_NAME = "compare" *)
module dcfifo_32in_32out_32kb_compare_2
(comp1,
v1_reg);
output comp1;
input [4:0]v1_reg;
wire comp1;
wire \gmux.gm[3].gms.ms_n_0 ;
wire [4:0]v1_reg;
wire [2:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({\gmux.gm[3].gms.ms_n_0 ,\NLW_gmux.gm[0].gm1.m1_CARRY4_CO_UNCONNECTED [2:0]}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(\gmux.gm[3].gms.ms_n_0 ),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg[4]}));
endmodule
(* ORIG_REF_NAME = "fifo_generator_ramfifo" *)
module dcfifo_32in_32out_32kb_fifo_generator_ramfifo
(dout,
empty,
full,
rd_data_count,
wr_data_count,
wr_clk,
rd_clk,
din,
rst,
rd_en,
wr_en);
output [31:0]dout;
output empty;
output full;
output [2:0]rd_data_count;
output [1:0]wr_data_count;
input wr_clk;
input rd_clk;
input [31:0]din;
input rst;
input rd_en;
input wr_en;
wire RD_RST;
wire WR_RST;
wire [31:0]din;
wire [31:0]dout;
wire empty;
wire full;
wire \gntv_or_sync_fifo.gcx.clkx_n_0 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_1 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_12 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_13 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_14 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_15 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_16 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_17 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_18 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_19 ;
wire [4:0]\gras.rsts/c1/v1_reg ;
wire [4:0]\gwas.wsts/c1/v1_reg ;
wire [4:0]\gwas.wsts/c2/v1_reg ;
wire \gwas.wsts/comp1 ;
wire \gwas.wsts/comp2 ;
wire \gwas.wsts/ram_full_i ;
wire [9:0]p_0_out;
wire p_18_out;
wire [9:0]p_1_out;
wire p_1_out_0;
wire [9:0]p_20_out;
wire p_3_out;
wire [9:0]p_8_out;
wire [9:0]p_9_out;
wire rd_clk;
wire [2:0]rd_data_count;
wire rd_en;
wire [9:0]rd_pntr_plus1;
wire [1:0]rd_rst_i;
wire rst;
wire rst_full_ff_i;
wire rst_full_gen_i;
wire tmp_ram_rd_en;
wire wr_clk;
wire [1:0]wr_data_count;
wire wr_en;
wire [9:0]wr_pntr_plus2;
wire [0:0]wr_rst_i;
dcfifo_32in_32out_32kb_clk_x_pntrs \gntv_or_sync_fifo.gcx.clkx
(.Q(p_20_out),
.RD_PNTR_WR(p_0_out),
.S({\gntv_or_sync_fifo.gcx.clkx_n_0 ,\gntv_or_sync_fifo.gcx.clkx_n_1 }),
.WR_PNTR_RD(p_1_out),
.comp1(\gwas.wsts/comp1 ),
.comp2(\gwas.wsts/comp2 ),
.\gc0.count_reg[9] (rd_pntr_plus1),
.\gic0.gc0.count_d1_reg[9] (p_8_out),
.\gic0.gc0.count_d2_reg[9] (p_9_out),
.\gic0.gc0.count_reg[9] (wr_pntr_plus2),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] (wr_rst_i),
.p_1_out(p_1_out_0),
.ram_full_i(\gwas.wsts/ram_full_i ),
.rd_clk(rd_clk),
.\rd_dc_i_reg[7] ({\gntv_or_sync_fifo.gcx.clkx_n_12 ,\gntv_or_sync_fifo.gcx.clkx_n_13 ,\gntv_or_sync_fifo.gcx.clkx_n_14 ,\gntv_or_sync_fifo.gcx.clkx_n_15 }),
.\rd_dc_i_reg[7]_0 ({\gntv_or_sync_fifo.gcx.clkx_n_16 ,\gntv_or_sync_fifo.gcx.clkx_n_17 ,\gntv_or_sync_fifo.gcx.clkx_n_18 ,\gntv_or_sync_fifo.gcx.clkx_n_19 }),
.rst_full_gen_i(rst_full_gen_i),
.v1_reg(\gras.rsts/c1/v1_reg ),
.v1_reg_0(\gwas.wsts/c1/v1_reg ),
.v1_reg_1(\gwas.wsts/c2/v1_reg ),
.wr_clk(wr_clk),
.wr_en(wr_en));
dcfifo_32in_32out_32kb_rd_logic \gntv_or_sync_fifo.gl0.rd
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (p_20_out),
.Q(RD_RST),
.S({\gntv_or_sync_fifo.gcx.clkx_n_0 ,\gntv_or_sync_fifo.gcx.clkx_n_1 }),
.WR_PNTR_RD(p_1_out),
.empty(empty),
.\gc0.count_d1_reg[9] (rd_pntr_plus1),
.p_18_out(p_18_out),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.v1_reg(\gras.rsts/c1/v1_reg ),
.\wr_pntr_bin_reg[3] ({\gntv_or_sync_fifo.gcx.clkx_n_16 ,\gntv_or_sync_fifo.gcx.clkx_n_17 ,\gntv_or_sync_fifo.gcx.clkx_n_18 ,\gntv_or_sync_fifo.gcx.clkx_n_19 }),
.\wr_pntr_bin_reg[7] ({\gntv_or_sync_fifo.gcx.clkx_n_12 ,\gntv_or_sync_fifo.gcx.clkx_n_13 ,\gntv_or_sync_fifo.gcx.clkx_n_14 ,\gntv_or_sync_fifo.gcx.clkx_n_15 }));
dcfifo_32in_32out_32kb_wr_logic \gntv_or_sync_fifo.gl0.wr
(.E(p_3_out),
.Q(p_9_out),
.RD_PNTR_WR(p_0_out),
.comp1(\gwas.wsts/comp1 ),
.comp2(\gwas.wsts/comp2 ),
.full(full),
.\gic0.gc0.count_d1_reg[9] (wr_pntr_plus2),
.\gic0.gc0.count_d2_reg[9] (p_8_out),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] (WR_RST),
.p_1_out(p_1_out_0),
.ram_full_i(\gwas.wsts/ram_full_i ),
.rst_full_ff_i(rst_full_ff_i),
.v1_reg(\gwas.wsts/c1/v1_reg ),
.v1_reg_0(\gwas.wsts/c2/v1_reg ),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en));
dcfifo_32in_32out_32kb_memory \gntv_or_sync_fifo.mem
(.E(p_3_out),
.Q(rd_rst_i[0]),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (p_20_out),
.\gic0.gc0.count_d2_reg[9] (p_9_out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
dcfifo_32in_32out_32kb_reset_blk_ramfifo rstblk
(.Q({RD_RST,rd_rst_i}),
.\gic0.gc0.count_reg[0] ({WR_RST,wr_rst_i}),
.p_18_out(p_18_out),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.rst_full_ff_i(rst_full_ff_i),
.rst_full_gen_i(rst_full_gen_i),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "fifo_generator_top" *)
module dcfifo_32in_32out_32kb_fifo_generator_top
(dout,
empty,
full,
rd_data_count,
wr_data_count,
wr_clk,
rd_clk,
din,
rst,
rd_en,
wr_en);
output [31:0]dout;
output empty;
output full;
output [2:0]rd_data_count;
output [1:0]wr_data_count;
input wr_clk;
input rd_clk;
input [31:0]din;
input rst;
input rd_en;
input wr_en;
wire [31:0]din;
wire [31:0]dout;
wire empty;
wire full;
wire rd_clk;
wire [2:0]rd_data_count;
wire rd_en;
wire rst;
wire wr_clk;
wire [1:0]wr_data_count;
wire wr_en;
dcfifo_32in_32out_32kb_fifo_generator_ramfifo \grf.rf
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en));
endmodule
(* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "10" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "32" *)
(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "32" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "32" *) (* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *) (* C_ERROR_INJECTION_TYPE = "0" *) (* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *) (* C_FAMILY = "artix7" *)
(* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *) (* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *) (* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *) (* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *) (* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *) (* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *) (* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *) (* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *) (* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *) (* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *) (* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *) (* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *) (* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "1" *) (* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *) (* C_HAS_SLAVE_CE = "0" *) (* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *) (* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "1" *) (* C_HAS_WR_RST = "0" *) (* C_IMPLEMENTATION_TYPE = "2" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *) (* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *) (* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *) (* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *) (* C_PRELOAD_LATENCY = "1" *)
(* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "1kx36" *) (* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) (* C_PROG_EMPTY_TYPE = "0" *) (* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *) (* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *) (* C_PROG_FULL_THRESH_ASSERT_VAL = "1021" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "1020" *) (* C_PROG_FULL_TYPE = "0" *) (* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *) (* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *) (* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "3" *) (* C_RD_DEPTH = "1024" *)
(* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "10" *) (* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *) (* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *) (* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *) (* C_USE_DOUT_RST = "1" *) (* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *) (* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *) (* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *) (* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *) (* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *) (* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "2" *) (* C_WR_DEPTH = "1024" *) (* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *) (* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *) (* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "10" *) (* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *) (* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *) (* C_WR_RESPONSE_LATENCY = "1" *) (* ORIG_REF_NAME = "fifo_generator_v12_0" *)
module dcfifo_32in_32out_32kb_fifo_generator_v12_0
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [31:0]din;
input wr_en;
input rd_en;
input [9:0]prog_empty_thresh;
input [9:0]prog_empty_thresh_assert;
input [9:0]prog_empty_thresh_negate;
input [9:0]prog_full_thresh;
input [9:0]prog_full_thresh_assert;
input [9:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [31:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [9:0]data_count;
output [2:0]rd_data_count;
output [1:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [63:0]s_axi_wdata;
input [7:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [63:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [9:0]axi_w_prog_full_thresh;
input [9:0]axi_w_prog_empty_thresh;
output [10:0]axi_w_data_count;
output [10:0]axi_w_wr_data_count;
output [10:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [9:0]axi_r_prog_full_thresh;
input [9:0]axi_r_prog_empty_thresh;
output [10:0]axi_r_data_count;
output [10:0]axi_r_wr_data_count;
output [10:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire \<const1> ;
wire axi_ar_injectdbiterr;
wire axi_ar_injectsbiterr;
wire [3:0]axi_ar_prog_empty_thresh;
wire [3:0]axi_ar_prog_full_thresh;
wire axi_aw_injectdbiterr;
wire axi_aw_injectsbiterr;
wire [3:0]axi_aw_prog_empty_thresh;
wire [3:0]axi_aw_prog_full_thresh;
wire axi_b_injectdbiterr;
wire axi_b_injectsbiterr;
wire [3:0]axi_b_prog_empty_thresh;
wire [3:0]axi_b_prog_full_thresh;
wire axi_r_injectdbiterr;
wire axi_r_injectsbiterr;
wire [9:0]axi_r_prog_empty_thresh;
wire [9:0]axi_r_prog_full_thresh;
wire axi_w_injectdbiterr;
wire axi_w_injectsbiterr;
wire [9:0]axi_w_prog_empty_thresh;
wire [9:0]axi_w_prog_full_thresh;
wire axis_injectdbiterr;
wire axis_injectsbiterr;
wire [9:0]axis_prog_empty_thresh;
wire [9:0]axis_prog_full_thresh;
wire backup;
wire backup_marker;
wire clk;
wire [31:0]din;
wire [31:0]dout;
wire empty;
wire full;
wire injectdbiterr;
wire injectsbiterr;
wire int_clk;
wire m_aclk;
wire m_aclk_en;
wire m_axi_arready;
wire m_axi_awready;
wire [0:0]m_axi_bid;
wire [1:0]m_axi_bresp;
wire [0:0]m_axi_buser;
wire m_axi_bvalid;
wire [63:0]m_axi_rdata;
wire [0:0]m_axi_rid;
wire m_axi_rlast;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_ruser;
wire m_axi_rvalid;
wire m_axi_wready;
wire m_axis_tready;
wire [9:0]prog_empty_thresh;
wire [9:0]prog_empty_thresh_assert;
wire [9:0]prog_empty_thresh_negate;
wire [9:0]prog_full_thresh;
wire [9:0]prog_full_thresh_assert;
wire [9:0]prog_full_thresh_negate;
wire rd_clk;
wire [2:0]rd_data_count;
wire rd_en;
wire rd_rst;
wire rst;
wire s_aclk;
wire s_aclk_en;
wire s_aresetn;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire [0:0]s_axi_aruser;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire [0:0]s_axi_awuser;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_rready;
wire [63:0]s_axi_wdata;
wire [0:0]s_axi_wid;
wire s_axi_wlast;
wire [7:0]s_axi_wstrb;
wire [0:0]s_axi_wuser;
wire s_axi_wvalid;
wire [7:0]s_axis_tdata;
wire [0:0]s_axis_tdest;
wire [0:0]s_axis_tid;
wire [0:0]s_axis_tkeep;
wire s_axis_tlast;
wire [0:0]s_axis_tstrb;
wire [3:0]s_axis_tuser;
wire s_axis_tvalid;
wire srst;
wire wr_clk;
wire [1:0]wr_data_count;
wire wr_en;
wire wr_rst;
assign almost_empty = \<const0> ;
assign almost_full = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const1> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const1> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const1> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[10] = \<const0> ;
assign axi_r_data_count[9] = \<const0> ;
assign axi_r_data_count[8] = \<const0> ;
assign axi_r_data_count[7] = \<const0> ;
assign axi_r_data_count[6] = \<const0> ;
assign axi_r_data_count[5] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const1> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[10] = \<const0> ;
assign axi_r_rd_data_count[9] = \<const0> ;
assign axi_r_rd_data_count[8] = \<const0> ;
assign axi_r_rd_data_count[7] = \<const0> ;
assign axi_r_rd_data_count[6] = \<const0> ;
assign axi_r_rd_data_count[5] = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[10] = \<const0> ;
assign axi_r_wr_data_count[9] = \<const0> ;
assign axi_r_wr_data_count[8] = \<const0> ;
assign axi_r_wr_data_count[7] = \<const0> ;
assign axi_r_wr_data_count[6] = \<const0> ;
assign axi_r_wr_data_count[5] = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[10] = \<const0> ;
assign axi_w_data_count[9] = \<const0> ;
assign axi_w_data_count[8] = \<const0> ;
assign axi_w_data_count[7] = \<const0> ;
assign axi_w_data_count[6] = \<const0> ;
assign axi_w_data_count[5] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const1> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[10] = \<const0> ;
assign axi_w_rd_data_count[9] = \<const0> ;
assign axi_w_rd_data_count[8] = \<const0> ;
assign axi_w_rd_data_count[7] = \<const0> ;
assign axi_w_rd_data_count[6] = \<const0> ;
assign axi_w_rd_data_count[5] = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[10] = \<const0> ;
assign axi_w_wr_data_count[9] = \<const0> ;
assign axi_w_wr_data_count[8] = \<const0> ;
assign axi_w_wr_data_count[7] = \<const0> ;
assign axi_w_wr_data_count[6] = \<const0> ;
assign axi_w_wr_data_count[5] = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const1> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[9] = \<const0> ;
assign data_count[8] = \<const0> ;
assign data_count[7] = \<const0> ;
assign data_count[6] = \<const0> ;
assign data_count[5] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign m_axi_araddr[31] = \<const0> ;
assign m_axi_araddr[30] = \<const0> ;
assign m_axi_araddr[29] = \<const0> ;
assign m_axi_araddr[28] = \<const0> ;
assign m_axi_araddr[27] = \<const0> ;
assign m_axi_araddr[26] = \<const0> ;
assign m_axi_araddr[25] = \<const0> ;
assign m_axi_araddr[24] = \<const0> ;
assign m_axi_araddr[23] = \<const0> ;
assign m_axi_araddr[22] = \<const0> ;
assign m_axi_araddr[21] = \<const0> ;
assign m_axi_araddr[20] = \<const0> ;
assign m_axi_araddr[19] = \<const0> ;
assign m_axi_araddr[18] = \<const0> ;
assign m_axi_araddr[17] = \<const0> ;
assign m_axi_araddr[16] = \<const0> ;
assign m_axi_araddr[15] = \<const0> ;
assign m_axi_araddr[14] = \<const0> ;
assign m_axi_araddr[13] = \<const0> ;
assign m_axi_araddr[12] = \<const0> ;
assign m_axi_araddr[11] = \<const0> ;
assign m_axi_araddr[10] = \<const0> ;
assign m_axi_araddr[9] = \<const0> ;
assign m_axi_araddr[8] = \<const0> ;
assign m_axi_araddr[7] = \<const0> ;
assign m_axi_araddr[6] = \<const0> ;
assign m_axi_araddr[5] = \<const0> ;
assign m_axi_araddr[4] = \<const0> ;
assign m_axi_araddr[3] = \<const0> ;
assign m_axi_araddr[2] = \<const0> ;
assign m_axi_araddr[1] = \<const0> ;
assign m_axi_araddr[0] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[2] = \<const0> ;
assign m_axi_arprot[1] = \<const0> ;
assign m_axi_arprot[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_arvalid = \<const0> ;
assign m_axi_awaddr[31] = \<const0> ;
assign m_axi_awaddr[30] = \<const0> ;
assign m_axi_awaddr[29] = \<const0> ;
assign m_axi_awaddr[28] = \<const0> ;
assign m_axi_awaddr[27] = \<const0> ;
assign m_axi_awaddr[26] = \<const0> ;
assign m_axi_awaddr[25] = \<const0> ;
assign m_axi_awaddr[24] = \<const0> ;
assign m_axi_awaddr[23] = \<const0> ;
assign m_axi_awaddr[22] = \<const0> ;
assign m_axi_awaddr[21] = \<const0> ;
assign m_axi_awaddr[20] = \<const0> ;
assign m_axi_awaddr[19] = \<const0> ;
assign m_axi_awaddr[18] = \<const0> ;
assign m_axi_awaddr[17] = \<const0> ;
assign m_axi_awaddr[16] = \<const0> ;
assign m_axi_awaddr[15] = \<const0> ;
assign m_axi_awaddr[14] = \<const0> ;
assign m_axi_awaddr[13] = \<const0> ;
assign m_axi_awaddr[12] = \<const0> ;
assign m_axi_awaddr[11] = \<const0> ;
assign m_axi_awaddr[10] = \<const0> ;
assign m_axi_awaddr[9] = \<const0> ;
assign m_axi_awaddr[8] = \<const0> ;
assign m_axi_awaddr[7] = \<const0> ;
assign m_axi_awaddr[6] = \<const0> ;
assign m_axi_awaddr[5] = \<const0> ;
assign m_axi_awaddr[4] = \<const0> ;
assign m_axi_awaddr[3] = \<const0> ;
assign m_axi_awaddr[2] = \<const0> ;
assign m_axi_awaddr[1] = \<const0> ;
assign m_axi_awaddr[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[2] = \<const0> ;
assign m_axi_awprot[1] = \<const0> ;
assign m_axi_awprot[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_awvalid = \<const0> ;
assign m_axi_bready = \<const0> ;
assign m_axi_rready = \<const0> ;
assign m_axi_wdata[63] = \<const0> ;
assign m_axi_wdata[62] = \<const0> ;
assign m_axi_wdata[61] = \<const0> ;
assign m_axi_wdata[60] = \<const0> ;
assign m_axi_wdata[59] = \<const0> ;
assign m_axi_wdata[58] = \<const0> ;
assign m_axi_wdata[57] = \<const0> ;
assign m_axi_wdata[56] = \<const0> ;
assign m_axi_wdata[55] = \<const0> ;
assign m_axi_wdata[54] = \<const0> ;
assign m_axi_wdata[53] = \<const0> ;
assign m_axi_wdata[52] = \<const0> ;
assign m_axi_wdata[51] = \<const0> ;
assign m_axi_wdata[50] = \<const0> ;
assign m_axi_wdata[49] = \<const0> ;
assign m_axi_wdata[48] = \<const0> ;
assign m_axi_wdata[47] = \<const0> ;
assign m_axi_wdata[46] = \<const0> ;
assign m_axi_wdata[45] = \<const0> ;
assign m_axi_wdata[44] = \<const0> ;
assign m_axi_wdata[43] = \<const0> ;
assign m_axi_wdata[42] = \<const0> ;
assign m_axi_wdata[41] = \<const0> ;
assign m_axi_wdata[40] = \<const0> ;
assign m_axi_wdata[39] = \<const0> ;
assign m_axi_wdata[38] = \<const0> ;
assign m_axi_wdata[37] = \<const0> ;
assign m_axi_wdata[36] = \<const0> ;
assign m_axi_wdata[35] = \<const0> ;
assign m_axi_wdata[34] = \<const0> ;
assign m_axi_wdata[33] = \<const0> ;
assign m_axi_wdata[32] = \<const0> ;
assign m_axi_wdata[31] = \<const0> ;
assign m_axi_wdata[30] = \<const0> ;
assign m_axi_wdata[29] = \<const0> ;
assign m_axi_wdata[28] = \<const0> ;
assign m_axi_wdata[27] = \<const0> ;
assign m_axi_wdata[26] = \<const0> ;
assign m_axi_wdata[25] = \<const0> ;
assign m_axi_wdata[24] = \<const0> ;
assign m_axi_wdata[23] = \<const0> ;
assign m_axi_wdata[22] = \<const0> ;
assign m_axi_wdata[21] = \<const0> ;
assign m_axi_wdata[20] = \<const0> ;
assign m_axi_wdata[19] = \<const0> ;
assign m_axi_wdata[18] = \<const0> ;
assign m_axi_wdata[17] = \<const0> ;
assign m_axi_wdata[16] = \<const0> ;
assign m_axi_wdata[15] = \<const0> ;
assign m_axi_wdata[14] = \<const0> ;
assign m_axi_wdata[13] = \<const0> ;
assign m_axi_wdata[12] = \<const0> ;
assign m_axi_wdata[11] = \<const0> ;
assign m_axi_wdata[10] = \<const0> ;
assign m_axi_wdata[9] = \<const0> ;
assign m_axi_wdata[8] = \<const0> ;
assign m_axi_wdata[7] = \<const0> ;
assign m_axi_wdata[6] = \<const0> ;
assign m_axi_wdata[5] = \<const0> ;
assign m_axi_wdata[4] = \<const0> ;
assign m_axi_wdata[3] = \<const0> ;
assign m_axi_wdata[2] = \<const0> ;
assign m_axi_wdata[1] = \<const0> ;
assign m_axi_wdata[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const0> ;
assign m_axi_wstrb[7] = \<const0> ;
assign m_axi_wstrb[6] = \<const0> ;
assign m_axi_wstrb[5] = \<const0> ;
assign m_axi_wstrb[4] = \<const0> ;
assign m_axi_wstrb[3] = \<const0> ;
assign m_axi_wstrb[2] = \<const0> ;
assign m_axi_wstrb[1] = \<const0> ;
assign m_axi_wstrb[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign prog_empty = \<const0> ;
assign prog_full = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_wready = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign valid = \<const0> ;
assign wr_ack = \<const0> ;
assign wr_rst_busy = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
dcfifo_32in_32out_32kb_fifo_generator_v12_0_synth inst_fifo_gen
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en));
endmodule
(* ORIG_REF_NAME = "fifo_generator_v12_0_synth" *)
module dcfifo_32in_32out_32kb_fifo_generator_v12_0_synth
(dout,
empty,
full,
rd_data_count,
wr_data_count,
wr_clk,
rd_clk,
din,
rst,
rd_en,
wr_en);
output [31:0]dout;
output empty;
output full;
output [2:0]rd_data_count;
output [1:0]wr_data_count;
input wr_clk;
input rd_clk;
input [31:0]din;
input rst;
input rd_en;
input wr_en;
wire [31:0]din;
wire [31:0]dout;
wire empty;
wire full;
wire rd_clk;
wire [2:0]rd_data_count;
wire rd_en;
wire rst;
wire wr_clk;
wire [1:0]wr_data_count;
wire wr_en;
dcfifo_32in_32out_32kb_fifo_generator_top \gconvfifo.rf
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en));
endmodule
(* ORIG_REF_NAME = "memory" *)
module dcfifo_32in_32out_32kb_memory
(dout,
E,
wr_clk,
tmp_ram_rd_en,
rd_clk,
Q,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [31:0]dout;
input [0:0]E;
input wr_clk;
input tmp_ram_rd_en;
input rd_clk;
input [0:0]Q;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [31:0]din;
wire [0:0]E;
wire [0:0]Q;
wire [31:0]din;
wire [31:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
dcfifo_32in_32out_32kb_blk_mem_gen_v8_2 \gbm.gbmg.gbmga.ngecc.bmg
(.E(E),
.Q(Q),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "rd_bin_cntr" *)
module dcfifo_32in_32out_32kb_rd_bin_cntr
(Q,
ram_empty_i_reg,
v1_reg,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
comp0,
rd_en,
p_18_out,
comp1,
WR_PNTR_RD,
E,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] );
output [9:0]Q;
output ram_empty_i_reg;
output [4:0]v1_reg;
output [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
input comp0;
input rd_en;
input p_18_out;
input comp1;
input [9:0]WR_PNTR_RD;
input [0:0]E;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [0:0]E;
wire [9:0]Q;
wire [9:0]WR_PNTR_RD;
wire comp0;
wire comp1;
wire \gc0.count[9]_i_2_n_0 ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire p_18_out;
wire [9:0]plusOp;
wire ram_empty_i_reg;
wire rd_clk;
wire rd_en;
wire [4:0]v1_reg;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1
(.I0(Q[0]),
.O(plusOp[0]));
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'h6A))
\gc0.count[2]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.O(plusOp[2]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h6AAA))
\gc0.count[3]_i_1
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.O(plusOp[3]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gc0.count[4]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(plusOp[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\gc0.count[5]_i_1
(.I0(Q[5]),
.I1(Q[2]),
.I2(Q[0]),
.I3(Q[1]),
.I4(Q[3]),
.I5(Q[4]),
.O(plusOp[5]));
LUT3 #(
.INIT(8'h6A))
\gc0.count[6]_i_1
(.I0(Q[6]),
.I1(\gc0.count[9]_i_2_n_0 ),
.I2(Q[5]),
.O(plusOp[6]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h6AAA))
\gc0.count[7]_i_1
(.I0(Q[7]),
.I1(Q[5]),
.I2(\gc0.count[9]_i_2_n_0 ),
.I3(Q[6]),
.O(plusOp[7]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\gc0.count[8]_i_1
(.I0(Q[8]),
.I1(Q[6]),
.I2(\gc0.count[9]_i_2_n_0 ),
.I3(Q[5]),
.I4(Q[7]),
.O(plusOp[8]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\gc0.count[9]_i_1
(.I0(Q[9]),
.I1(Q[7]),
.I2(Q[5]),
.I3(\gc0.count[9]_i_2_n_0 ),
.I4(Q[6]),
.I5(Q[8]),
.O(plusOp[9]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'h80000000))
\gc0.count[9]_i_2
(.I0(Q[4]),
.I1(Q[3]),
.I2(Q[1]),
.I3(Q[0]),
.I4(Q[2]),
.O(\gc0.count[9]_i_2_n_0 ));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[0]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[1]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[2]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[3]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[4]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[5]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[5]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[6]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[6]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[7]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[7]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[8]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[8]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[9]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(Q[9]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(rd_clk),
.CE(E),
.D(plusOp[0]),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[5]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[6]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[7]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[8]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[9]
(.C(rd_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.D(plusOp[9]),
.Q(Q[9]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]),
.I1(WR_PNTR_RD[1]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]),
.I3(WR_PNTR_RD[0]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]),
.I1(WR_PNTR_RD[3]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]),
.I3(WR_PNTR_RD[2]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]),
.I1(WR_PNTR_RD[5]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]),
.I3(WR_PNTR_RD[4]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]),
.I1(WR_PNTR_RD[7]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]),
.I3(WR_PNTR_RD[6]),
.O(v1_reg[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]),
.I1(WR_PNTR_RD[9]),
.I2(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]),
.I3(WR_PNTR_RD[8]),
.O(v1_reg[4]));
LUT4 #(
.INIT(16'hAEAA))
ram_empty_i_i_1
(.I0(comp0),
.I1(rd_en),
.I2(p_18_out),
.I3(comp1),
.O(ram_empty_i_reg));
endmodule
(* ORIG_REF_NAME = "rd_dc_as" *)
module dcfifo_32in_32out_32kb_rd_dc_as
(rd_data_count,
rd_clk,
Q,
WR_PNTR_RD,
\wr_pntr_bin_reg[3] ,
\wr_pntr_bin_reg[7] ,
S);
output [2:0]rd_data_count;
input rd_clk;
input [0:0]Q;
input [8:0]WR_PNTR_RD;
input [3:0]\wr_pntr_bin_reg[3] ;
input [3:0]\wr_pntr_bin_reg[7] ;
input [1:0]S;
wire [0:0]Q;
wire [1:0]S;
wire [8:0]WR_PNTR_RD;
wire [9:0]minusOp;
wire rd_clk;
wire [2:0]rd_data_count;
wire \rd_dc_i_reg[7]_i_1_n_0 ;
wire \rd_dc_i_reg[7]_i_1_n_1 ;
wire \rd_dc_i_reg[7]_i_1_n_2 ;
wire \rd_dc_i_reg[7]_i_1_n_3 ;
wire \rd_dc_i_reg[7]_i_2_n_0 ;
wire \rd_dc_i_reg[7]_i_2_n_1 ;
wire \rd_dc_i_reg[7]_i_2_n_2 ;
wire \rd_dc_i_reg[7]_i_2_n_3 ;
wire \rd_dc_i_reg[9]_i_1_n_3 ;
wire [3:0]\wr_pntr_bin_reg[3] ;
wire [3:0]\wr_pntr_bin_reg[7] ;
wire [3:1]\NLW_rd_dc_i_reg[9]_i_1_CO_UNCONNECTED ;
wire [3:2]\NLW_rd_dc_i_reg[9]_i_1_O_UNCONNECTED ;
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q),
.D(minusOp[7]),
.Q(rd_data_count[0]));
CARRY4 \rd_dc_i_reg[7]_i_1
(.CI(\rd_dc_i_reg[7]_i_2_n_0 ),
.CO({\rd_dc_i_reg[7]_i_1_n_0 ,\rd_dc_i_reg[7]_i_1_n_1 ,\rd_dc_i_reg[7]_i_1_n_2 ,\rd_dc_i_reg[7]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(WR_PNTR_RD[7:4]),
.O(minusOp[7:4]),
.S(\wr_pntr_bin_reg[7] ));
CARRY4 \rd_dc_i_reg[7]_i_2
(.CI(1'b0),
.CO({\rd_dc_i_reg[7]_i_2_n_0 ,\rd_dc_i_reg[7]_i_2_n_1 ,\rd_dc_i_reg[7]_i_2_n_2 ,\rd_dc_i_reg[7]_i_2_n_3 }),
.CYINIT(1'b1),
.DI(WR_PNTR_RD[3:0]),
.O(minusOp[3:0]),
.S(\wr_pntr_bin_reg[3] ));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q),
.D(minusOp[8]),
.Q(rd_data_count[1]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(Q),
.D(minusOp[9]),
.Q(rd_data_count[2]));
CARRY4 \rd_dc_i_reg[9]_i_1
(.CI(\rd_dc_i_reg[7]_i_1_n_0 ),
.CO({\NLW_rd_dc_i_reg[9]_i_1_CO_UNCONNECTED [3:1],\rd_dc_i_reg[9]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,WR_PNTR_RD[8]}),
.O({\NLW_rd_dc_i_reg[9]_i_1_O_UNCONNECTED [3:2],minusOp[9:8]}),
.S({1'b0,1'b0,S}));
endmodule
(* ORIG_REF_NAME = "rd_logic" *)
module dcfifo_32in_32out_32kb_rd_logic
(empty,
p_18_out,
\gc0.count_d1_reg[9] ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
rd_data_count,
v1_reg,
rd_clk,
Q,
rd_en,
WR_PNTR_RD,
\wr_pntr_bin_reg[3] ,
\wr_pntr_bin_reg[7] ,
S);
output empty;
output p_18_out;
output [9:0]\gc0.count_d1_reg[9] ;
output [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
output [2:0]rd_data_count;
input [4:0]v1_reg;
input rd_clk;
input [0:0]Q;
input rd_en;
input [9:0]WR_PNTR_RD;
input [3:0]\wr_pntr_bin_reg[3] ;
input [3:0]\wr_pntr_bin_reg[7] ;
input [1:0]S;
wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [0:0]Q;
wire [1:0]S;
wire [9:0]WR_PNTR_RD;
wire [4:0]\c0/v1_reg ;
wire comp0;
wire comp1;
wire empty;
wire [9:0]\gc0.count_d1_reg[9] ;
wire p_14_out;
wire p_18_out;
wire rd_clk;
wire [2:0]rd_data_count;
wire rd_en;
wire rpntr_n_10;
wire [4:0]v1_reg;
wire [3:0]\wr_pntr_bin_reg[3] ;
wire [3:0]\wr_pntr_bin_reg[7] ;
dcfifo_32in_32out_32kb_rd_dc_as \gras.grdc1.rdc
(.Q(Q),
.S(S),
.WR_PNTR_RD(WR_PNTR_RD[8:0]),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.\wr_pntr_bin_reg[3] (\wr_pntr_bin_reg[3] ),
.\wr_pntr_bin_reg[7] (\wr_pntr_bin_reg[7] ));
dcfifo_32in_32out_32kb_rd_status_flags_as \gras.rsts
(.E(p_14_out),
.Q(Q),
.comp0(comp0),
.comp1(comp1),
.empty(empty),
.p_18_out(p_18_out),
.ram_empty_fb_i_reg_0(rpntr_n_10),
.rd_clk(rd_clk),
.rd_en(rd_en),
.v1_reg(v1_reg),
.v1_reg_0(\c0/v1_reg ));
dcfifo_32in_32out_32kb_rd_bin_cntr rpntr
(.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ),
.E(p_14_out),
.Q(\gc0.count_d1_reg[9] ),
.WR_PNTR_RD(WR_PNTR_RD),
.comp0(comp0),
.comp1(comp1),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (Q),
.p_18_out(p_18_out),
.ram_empty_i_reg(rpntr_n_10),
.rd_clk(rd_clk),
.rd_en(rd_en),
.v1_reg(\c0/v1_reg ));
endmodule
(* ORIG_REF_NAME = "rd_status_flags_as" *)
module dcfifo_32in_32out_32kb_rd_status_flags_as
(comp0,
comp1,
empty,
p_18_out,
E,
v1_reg_0,
v1_reg,
ram_empty_fb_i_reg_0,
rd_clk,
Q,
rd_en);
output comp0;
output comp1;
output empty;
output p_18_out;
output [0:0]E;
input [4:0]v1_reg_0;
input [4:0]v1_reg;
input ram_empty_fb_i_reg_0;
input rd_clk;
input [0:0]Q;
input rd_en;
wire [0:0]E;
wire [0:0]Q;
wire comp0;
wire comp1;
wire empty;
wire p_18_out;
wire ram_empty_fb_i_reg_0;
wire rd_clk;
wire rd_en;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
dcfifo_32in_32out_32kb_compare_1 c0
(.comp0(comp0),
.v1_reg_0(v1_reg_0));
dcfifo_32in_32out_32kb_compare_2 c1
(.comp1(comp1),
.v1_reg(v1_reg));
LUT2 #(
.INIT(4'h2))
\gc0.count_d1[9]_i_1
(.I0(rd_en),
.I1(p_18_out),
.O(E));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(ram_empty_fb_i_reg_0),
.PRE(Q),
.Q(p_18_out));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(ram_empty_fb_i_reg_0),
.PRE(Q),
.Q(empty));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module dcfifo_32in_32out_32kb_reset_blk_ramfifo
(rst_full_ff_i,
rst_full_gen_i,
tmp_ram_rd_en,
Q,
\gic0.gc0.count_reg[0] ,
wr_clk,
rst,
rd_clk,
p_18_out,
rd_en);
output rst_full_ff_i;
output rst_full_gen_i;
output tmp_ram_rd_en;
output [2:0]Q;
output [1:0]\gic0.gc0.count_reg[0] ;
input wr_clk;
input rst;
input rd_clk;
input p_18_out;
input rd_en;
wire [2:0]Q;
wire [1:0]\gic0.gc0.count_reg[0] ;
wire \ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0 ;
wire \ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 ;
wire \ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0 ;
wire \ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0 ;
wire p_18_out;
wire rd_clk;
wire rd_en;
wire rd_rst_asreg;
wire rd_rst_asreg_d1;
wire rd_rst_asreg_d2;
wire rst;
wire rst_d1;
wire rst_d2;
wire rst_d3;
wire rst_full_gen_i;
wire rst_rd_reg1;
wire rst_rd_reg2;
wire rst_wr_reg1;
wire rst_wr_reg2;
wire tmp_ram_rd_en;
wire wr_clk;
wire wr_rst_asreg;
wire wr_rst_asreg_d1;
wire wr_rst_asreg_d2;
assign rst_full_ff_i = rst_d2;
LUT3 #(
.INIT(8'hBA))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2
(.I0(Q[0]),
.I1(p_18_out),
.I2(rd_en),
.O(tmp_ram_rd_en));
FDCE #(
.INIT(1'b0))
\grstd1.grst_full.grst_f.RST_FULL_GEN_reg
(.C(wr_clk),
.CE(1'b1),
.CLR(rst),
.D(rst_d3),
.Q(rst_full_gen_i));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst),
.Q(rst_d3));
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d1_reg
(.C(rd_clk),
.CE(1'b1),
.D(rd_rst_asreg),
.Q(rd_rst_asreg_d1),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_d2_reg
(.C(rd_clk),
.CE(1'b1),
.D(rd_rst_asreg_d1),
.Q(rd_rst_asreg_d2),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1
(.I0(rd_rst_asreg),
.I1(rd_rst_asreg_d1),
.O(\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0 ));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(rd_clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1_n_0 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1
(.I0(rd_rst_asreg),
.I1(rd_rst_asreg_d2),
.O(\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 ));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 ),
.Q(Q[0]));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 ),
.Q(Q[1]));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1_n_0 ),
.Q(Q[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(rd_clk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(rst),
.Q(rst_rd_reg2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(rst),
.Q(rst_wr_reg2));
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d1_reg
(.C(wr_clk),
.CE(1'b1),
.D(wr_rst_asreg),
.Q(wr_rst_asreg_d1),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_d2_reg
(.C(wr_clk),
.CE(1'b1),
.D(wr_rst_asreg_d1),
.Q(wr_rst_asreg_d2),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1
(.I0(wr_rst_asreg),
.I1(wr_rst_asreg_d1),
.O(\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0 ));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(wr_clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1_n_0 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1
(.I0(wr_rst_asreg),
.I1(wr_rst_asreg_d2),
.O(\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0 ));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0 ),
.Q(\gic0.gc0.count_reg[0] [0]));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg[1]_i_1_n_0 ),
.Q(\gic0.gc0.count_reg[0] [1]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module dcfifo_32in_32out_32kb_synchronizer_ff
(D,
Q,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [9:0]D;
input [9:0]Q;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [9:0]Q;
wire [9:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire rd_clk;
assign D[9:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[8]),
.Q(Q_reg[8]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[9]),
.Q(Q_reg[9]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module dcfifo_32in_32out_32kb_synchronizer_ff_3
(D,
Q,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] );
output [9:0]D;
input [9:0]Q;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire [9:0]Q;
wire [9:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire wr_clk;
assign D[9:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[8]),
.Q(Q_reg[8]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(Q[9]),
.Q(Q_reg[9]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module dcfifo_32in_32out_32kb_synchronizer_ff_4
(out,
D,
\Q_reg_reg[9]_0 ,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [0:0]out;
output [8:0]D;
input [9:0]\Q_reg_reg[9]_0 ;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [8:0]D;
wire [9:0]Q_reg;
wire [9:0]\Q_reg_reg[9]_0 ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire rd_clk;
assign out[0] = Q_reg[9];
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[9]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[9]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[9]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[9]_0 [3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[9]_0 [4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[9]_0 [5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[9]_0 [6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[9]_0 [7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[9]_0 [8]),
.Q(Q_reg[8]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[9]_0 [9]),
.Q(Q_reg[9]));
LUT5 #(
.INIT(32'h96696996))
\wr_pntr_bin[0]_i_1
(.I0(D[4]),
.I1(Q_reg[3]),
.I2(Q_reg[2]),
.I3(Q_reg[1]),
.I4(Q_reg[0]),
.O(D[0]));
LUT4 #(
.INIT(16'h6996))
\wr_pntr_bin[1]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[1]),
.I2(Q_reg[3]),
.I3(D[4]),
.O(D[1]));
LUT3 #(
.INIT(8'h96))
\wr_pntr_bin[2]_i_1
(.I0(Q_reg[3]),
.I1(D[4]),
.I2(Q_reg[2]),
.O(D[2]));
LUT2 #(
.INIT(4'h6))
\wr_pntr_bin[3]_i_1
(.I0(D[4]),
.I1(Q_reg[3]),
.O(D[3]));
LUT6 #(
.INIT(64'h6996966996696996))
\wr_pntr_bin[4]_i_1
(.I0(Q_reg[5]),
.I1(Q_reg[9]),
.I2(Q_reg[7]),
.I3(Q_reg[8]),
.I4(Q_reg[6]),
.I5(Q_reg[4]),
.O(D[4]));
LUT5 #(
.INIT(32'h96696996))
\wr_pntr_bin[5]_i_1
(.I0(Q_reg[6]),
.I1(Q_reg[8]),
.I2(Q_reg[7]),
.I3(Q_reg[9]),
.I4(Q_reg[5]),
.O(D[5]));
LUT4 #(
.INIT(16'h6996))
\wr_pntr_bin[6]_i_1
(.I0(Q_reg[9]),
.I1(Q_reg[7]),
.I2(Q_reg[8]),
.I3(Q_reg[6]),
.O(D[6]));
LUT3 #(
.INIT(8'h96))
\wr_pntr_bin[7]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[7]),
.I2(Q_reg[9]),
.O(D[7]));
LUT2 #(
.INIT(4'h6))
\wr_pntr_bin[8]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[9]),
.O(D[8]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module dcfifo_32in_32out_32kb_synchronizer_ff_5
(out,
D,
\Q_reg_reg[9]_0 ,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] );
output [0:0]out;
output [8:0]D;
input [9:0]\Q_reg_reg[9]_0 ;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire [8:0]D;
wire [9:0]Q_reg;
wire [9:0]\Q_reg_reg[9]_0 ;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ;
wire wr_clk;
assign out[0] = Q_reg[9];
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\Q_reg_reg[9]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\Q_reg_reg[9]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\Q_reg_reg[9]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\Q_reg_reg[9]_0 [3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\Q_reg_reg[9]_0 [4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\Q_reg_reg[9]_0 [5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\Q_reg_reg[9]_0 [6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\Q_reg_reg[9]_0 [7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\Q_reg_reg[9]_0 [8]),
.Q(Q_reg[8]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0] ),
.D(\Q_reg_reg[9]_0 [9]),
.Q(Q_reg[9]));
LUT5 #(
.INIT(32'h96696996))
\rd_pntr_bin[0]_i_1
(.I0(D[4]),
.I1(Q_reg[3]),
.I2(Q_reg[2]),
.I3(Q_reg[1]),
.I4(Q_reg[0]),
.O(D[0]));
LUT4 #(
.INIT(16'h6996))
\rd_pntr_bin[1]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[1]),
.I2(Q_reg[3]),
.I3(D[4]),
.O(D[1]));
LUT3 #(
.INIT(8'h96))
\rd_pntr_bin[2]_i_1
(.I0(Q_reg[3]),
.I1(D[4]),
.I2(Q_reg[2]),
.O(D[2]));
LUT2 #(
.INIT(4'h6))
\rd_pntr_bin[3]_i_1
(.I0(D[4]),
.I1(Q_reg[3]),
.O(D[3]));
LUT6 #(
.INIT(64'h6996966996696996))
\rd_pntr_bin[4]_i_1
(.I0(Q_reg[5]),
.I1(Q_reg[9]),
.I2(Q_reg[7]),
.I3(Q_reg[8]),
.I4(Q_reg[6]),
.I5(Q_reg[4]),
.O(D[4]));
LUT5 #(
.INIT(32'h96696996))
\rd_pntr_bin[5]_i_1
(.I0(Q_reg[6]),
.I1(Q_reg[8]),
.I2(Q_reg[7]),
.I3(Q_reg[9]),
.I4(Q_reg[5]),
.O(D[5]));
LUT4 #(
.INIT(16'h6996))
\rd_pntr_bin[6]_i_1
(.I0(Q_reg[9]),
.I1(Q_reg[7]),
.I2(Q_reg[8]),
.I3(Q_reg[6]),
.O(D[6]));
LUT3 #(
.INIT(8'h96))
\rd_pntr_bin[7]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[7]),
.I2(Q_reg[9]),
.O(D[7]));
LUT2 #(
.INIT(4'h6))
\rd_pntr_bin[8]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[9]),
.O(D[8]));
endmodule
(* ORIG_REF_NAME = "wr_bin_cntr" *)
module dcfifo_32in_32out_32kb_wr_bin_cntr
(\wr_data_count_i_reg[9] ,
Q,
\wr_data_count_i_reg[9]_0 ,
S,
\gic0.gc0.count_d1_reg[9]_0 ,
\gic0.gc0.count_d2_reg[9]_0 ,
RD_PNTR_WR,
E,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] );
output [1:0]\wr_data_count_i_reg[9] ;
output [9:0]Q;
output [3:0]\wr_data_count_i_reg[9]_0 ;
output [3:0]S;
output [9:0]\gic0.gc0.count_d1_reg[9]_0 ;
output [9:0]\gic0.gc0.count_d2_reg[9]_0 ;
input [9:0]RD_PNTR_WR;
input [0:0]E;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire [0:0]E;
wire [9:0]Q;
wire [9:0]RD_PNTR_WR;
wire [3:0]S;
wire \gic0.gc0.count[9]_i_2_n_0 ;
wire [9:0]\gic0.gc0.count_d1_reg[9]_0 ;
wire [9:0]\gic0.gc0.count_d2_reg[9]_0 ;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire [9:0]plusOp__0;
wire wr_clk;
wire [1:0]\wr_data_count_i_reg[9] ;
wire [3:0]\wr_data_count_i_reg[9]_0 ;
LUT1 #(
.INIT(2'h1))
\gic0.gc0.count[0]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [0]),
.O(plusOp__0[0]));
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[1]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [0]),
.I1(\gic0.gc0.count_d1_reg[9]_0 [1]),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'h6A))
\gic0.gc0.count[2]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [2]),
.I1(\gic0.gc0.count_d1_reg[9]_0 [0]),
.I2(\gic0.gc0.count_d1_reg[9]_0 [1]),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h6AAA))
\gic0.gc0.count[3]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [3]),
.I1(\gic0.gc0.count_d1_reg[9]_0 [1]),
.I2(\gic0.gc0.count_d1_reg[9]_0 [0]),
.I3(\gic0.gc0.count_d1_reg[9]_0 [2]),
.O(plusOp__0[3]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gic0.gc0.count[4]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [2]),
.I1(\gic0.gc0.count_d1_reg[9]_0 [0]),
.I2(\gic0.gc0.count_d1_reg[9]_0 [1]),
.I3(\gic0.gc0.count_d1_reg[9]_0 [3]),
.I4(\gic0.gc0.count_d1_reg[9]_0 [4]),
.O(plusOp__0[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\gic0.gc0.count[5]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [5]),
.I1(\gic0.gc0.count_d1_reg[9]_0 [2]),
.I2(\gic0.gc0.count_d1_reg[9]_0 [0]),
.I3(\gic0.gc0.count_d1_reg[9]_0 [1]),
.I4(\gic0.gc0.count_d1_reg[9]_0 [3]),
.I5(\gic0.gc0.count_d1_reg[9]_0 [4]),
.O(plusOp__0[5]));
LUT3 #(
.INIT(8'h6A))
\gic0.gc0.count[6]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [6]),
.I1(\gic0.gc0.count[9]_i_2_n_0 ),
.I2(\gic0.gc0.count_d1_reg[9]_0 [5]),
.O(plusOp__0[6]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h6AAA))
\gic0.gc0.count[7]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [7]),
.I1(\gic0.gc0.count_d1_reg[9]_0 [5]),
.I2(\gic0.gc0.count[9]_i_2_n_0 ),
.I3(\gic0.gc0.count_d1_reg[9]_0 [6]),
.O(plusOp__0[7]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\gic0.gc0.count[8]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [8]),
.I1(\gic0.gc0.count_d1_reg[9]_0 [6]),
.I2(\gic0.gc0.count[9]_i_2_n_0 ),
.I3(\gic0.gc0.count_d1_reg[9]_0 [5]),
.I4(\gic0.gc0.count_d1_reg[9]_0 [7]),
.O(plusOp__0[8]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\gic0.gc0.count[9]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [9]),
.I1(\gic0.gc0.count_d1_reg[9]_0 [7]),
.I2(\gic0.gc0.count_d1_reg[9]_0 [5]),
.I3(\gic0.gc0.count[9]_i_2_n_0 ),
.I4(\gic0.gc0.count_d1_reg[9]_0 [6]),
.I5(\gic0.gc0.count_d1_reg[9]_0 [8]),
.O(plusOp__0[9]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT5 #(
.INIT(32'h80000000))
\gic0.gc0.count[9]_i_2
(.I0(\gic0.gc0.count_d1_reg[9]_0 [4]),
.I1(\gic0.gc0.count_d1_reg[9]_0 [3]),
.I2(\gic0.gc0.count_d1_reg[9]_0 [1]),
.I3(\gic0.gc0.count_d1_reg[9]_0 [0]),
.I4(\gic0.gc0.count_d1_reg[9]_0 [2]),
.O(\gic0.gc0.count[9]_i_2_n_0 ));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_d1_reg[0]
(.C(wr_clk),
.CE(E),
.D(\gic0.gc0.count_d1_reg[9]_0 [0]),
.PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.Q(\gic0.gc0.count_d2_reg[9]_0 [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[1]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d1_reg[9]_0 [1]),
.Q(\gic0.gc0.count_d2_reg[9]_0 [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d1_reg[9]_0 [2]),
.Q(\gic0.gc0.count_d2_reg[9]_0 [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d1_reg[9]_0 [3]),
.Q(\gic0.gc0.count_d2_reg[9]_0 [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d1_reg[9]_0 [4]),
.Q(\gic0.gc0.count_d2_reg[9]_0 [4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d1_reg[9]_0 [5]),
.Q(\gic0.gc0.count_d2_reg[9]_0 [5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d1_reg[9]_0 [6]),
.Q(\gic0.gc0.count_d2_reg[9]_0 [6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d1_reg[9]_0 [7]),
.Q(\gic0.gc0.count_d2_reg[9]_0 [7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[8]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d1_reg[9]_0 [8]),
.Q(\gic0.gc0.count_d2_reg[9]_0 [8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[9]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d1_reg[9]_0 [9]),
.Q(\gic0.gc0.count_d2_reg[9]_0 [9]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[0]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[9]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[1]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[9]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[9]_0 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[9]_0 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[9]_0 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[9]_0 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[9]_0 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[9]_0 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[8]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[9]_0 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[9]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\gic0.gc0.count_d2_reg[9]_0 [9]),
.Q(Q[9]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[0]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[0]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [0]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_reg[1]
(.C(wr_clk),
.CE(E),
.D(plusOp__0[1]),
.PRE(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.Q(\gic0.gc0.count_d1_reg[9]_0 [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[2]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[3]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[4]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[5]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[6]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[7]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[8]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[8]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[9]
(.C(wr_clk),
.CE(E),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(plusOp__0[9]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [9]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[9]_i_10
(.I0(Q[3]),
.I1(RD_PNTR_WR[3]),
.O(S[3]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[9]_i_11
(.I0(Q[2]),
.I1(RD_PNTR_WR[2]),
.O(S[2]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[9]_i_12
(.I0(Q[1]),
.I1(RD_PNTR_WR[1]),
.O(S[1]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[9]_i_13
(.I0(Q[0]),
.I1(RD_PNTR_WR[0]),
.O(S[0]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[9]_i_3
(.I0(Q[9]),
.I1(RD_PNTR_WR[9]),
.O(\wr_data_count_i_reg[9] [1]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[9]_i_4
(.I0(Q[8]),
.I1(RD_PNTR_WR[8]),
.O(\wr_data_count_i_reg[9] [0]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[9]_i_6
(.I0(Q[7]),
.I1(RD_PNTR_WR[7]),
.O(\wr_data_count_i_reg[9]_0 [3]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[9]_i_7
(.I0(Q[6]),
.I1(RD_PNTR_WR[6]),
.O(\wr_data_count_i_reg[9]_0 [2]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[9]_i_8
(.I0(Q[5]),
.I1(RD_PNTR_WR[5]),
.O(\wr_data_count_i_reg[9]_0 [1]));
LUT2 #(
.INIT(4'h9))
\wr_data_count_i[9]_i_9
(.I0(Q[4]),
.I1(RD_PNTR_WR[4]),
.O(\wr_data_count_i_reg[9]_0 [0]));
endmodule
(* ORIG_REF_NAME = "wr_dc_as" *)
module dcfifo_32in_32out_32kb_wr_dc_as
(wr_data_count,
wr_clk,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ,
Q,
S,
\gic0.gc0.count_d2_reg[7] ,
\gic0.gc0.count_d2_reg[9] );
output [1:0]wr_data_count;
input wr_clk;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
input [8:0]Q;
input [3:0]S;
input [3:0]\gic0.gc0.count_d2_reg[7] ;
input [1:0]\gic0.gc0.count_d2_reg[9] ;
wire [8:0]Q;
wire [3:0]S;
wire [3:0]\gic0.gc0.count_d2_reg[7] ;
wire [1:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire wr_clk;
wire [1:0]wr_data_count;
wire \wr_data_count_i_reg[9]_i_1_n_3 ;
wire \wr_data_count_i_reg[9]_i_1_n_6 ;
wire \wr_data_count_i_reg[9]_i_1_n_7 ;
wire \wr_data_count_i_reg[9]_i_2_n_0 ;
wire \wr_data_count_i_reg[9]_i_2_n_1 ;
wire \wr_data_count_i_reg[9]_i_2_n_2 ;
wire \wr_data_count_i_reg[9]_i_2_n_3 ;
wire \wr_data_count_i_reg[9]_i_2_n_4 ;
wire \wr_data_count_i_reg[9]_i_2_n_5 ;
wire \wr_data_count_i_reg[9]_i_2_n_6 ;
wire \wr_data_count_i_reg[9]_i_2_n_7 ;
wire \wr_data_count_i_reg[9]_i_5_n_0 ;
wire \wr_data_count_i_reg[9]_i_5_n_1 ;
wire \wr_data_count_i_reg[9]_i_5_n_2 ;
wire \wr_data_count_i_reg[9]_i_5_n_3 ;
wire \wr_data_count_i_reg[9]_i_5_n_4 ;
wire \wr_data_count_i_reg[9]_i_5_n_5 ;
wire \wr_data_count_i_reg[9]_i_5_n_6 ;
wire \wr_data_count_i_reg[9]_i_5_n_7 ;
wire [3:1]\NLW_wr_data_count_i_reg[9]_i_1_CO_UNCONNECTED ;
wire [3:2]\NLW_wr_data_count_i_reg[9]_i_1_O_UNCONNECTED ;
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\wr_data_count_i_reg[9]_i_1_n_7 ),
.Q(wr_data_count[0]));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.D(\wr_data_count_i_reg[9]_i_1_n_6 ),
.Q(wr_data_count[1]));
CARRY4 \wr_data_count_i_reg[9]_i_1
(.CI(\wr_data_count_i_reg[9]_i_2_n_0 ),
.CO({\NLW_wr_data_count_i_reg[9]_i_1_CO_UNCONNECTED [3:1],\wr_data_count_i_reg[9]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,Q[8]}),
.O({\NLW_wr_data_count_i_reg[9]_i_1_O_UNCONNECTED [3:2],\wr_data_count_i_reg[9]_i_1_n_6 ,\wr_data_count_i_reg[9]_i_1_n_7 }),
.S({1'b0,1'b0,\gic0.gc0.count_d2_reg[9] }));
CARRY4 \wr_data_count_i_reg[9]_i_2
(.CI(\wr_data_count_i_reg[9]_i_5_n_0 ),
.CO({\wr_data_count_i_reg[9]_i_2_n_0 ,\wr_data_count_i_reg[9]_i_2_n_1 ,\wr_data_count_i_reg[9]_i_2_n_2 ,\wr_data_count_i_reg[9]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(Q[7:4]),
.O({\wr_data_count_i_reg[9]_i_2_n_4 ,\wr_data_count_i_reg[9]_i_2_n_5 ,\wr_data_count_i_reg[9]_i_2_n_6 ,\wr_data_count_i_reg[9]_i_2_n_7 }),
.S(\gic0.gc0.count_d2_reg[7] ));
CARRY4 \wr_data_count_i_reg[9]_i_5
(.CI(1'b0),
.CO({\wr_data_count_i_reg[9]_i_5_n_0 ,\wr_data_count_i_reg[9]_i_5_n_1 ,\wr_data_count_i_reg[9]_i_5_n_2 ,\wr_data_count_i_reg[9]_i_5_n_3 }),
.CYINIT(1'b1),
.DI(Q[3:0]),
.O({\wr_data_count_i_reg[9]_i_5_n_4 ,\wr_data_count_i_reg[9]_i_5_n_5 ,\wr_data_count_i_reg[9]_i_5_n_6 ,\wr_data_count_i_reg[9]_i_5_n_7 }),
.S(S));
endmodule
(* ORIG_REF_NAME = "wr_logic" *)
module dcfifo_32in_32out_32kb_wr_logic
(comp1,
comp2,
full,
p_1_out,
Q,
\gic0.gc0.count_d1_reg[9] ,
E,
\gic0.gc0.count_d2_reg[9] ,
wr_data_count,
v1_reg,
v1_reg_0,
ram_full_i,
wr_clk,
rst_full_ff_i,
RD_PNTR_WR,
wr_en,
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] );
output comp1;
output comp2;
output full;
output p_1_out;
output [9:0]Q;
output [9:0]\gic0.gc0.count_d1_reg[9] ;
output [0:0]E;
output [9:0]\gic0.gc0.count_d2_reg[9] ;
output [1:0]wr_data_count;
input [4:0]v1_reg;
input [4:0]v1_reg_0;
input ram_full_i;
input wr_clk;
input rst_full_ff_i;
input [9:0]RD_PNTR_WR;
input wr_en;
input [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire [0:0]E;
wire [9:0]Q;
wire [9:0]RD_PNTR_WR;
wire comp1;
wire comp2;
wire full;
wire [9:0]\gic0.gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ;
wire p_1_out;
wire ram_full_i;
wire rst_full_ff_i;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
wire wpntr_n_0;
wire wpntr_n_1;
wire wpntr_n_12;
wire wpntr_n_13;
wire wpntr_n_14;
wire wpntr_n_15;
wire wpntr_n_16;
wire wpntr_n_17;
wire wpntr_n_18;
wire wpntr_n_19;
wire wr_clk;
wire [1:0]wr_data_count;
wire wr_en;
dcfifo_32in_32out_32kb_wr_dc_as \gwas.gwdc0.wdc
(.Q(Q[8:0]),
.S({wpntr_n_16,wpntr_n_17,wpntr_n_18,wpntr_n_19}),
.\gic0.gc0.count_d2_reg[7] ({wpntr_n_12,wpntr_n_13,wpntr_n_14,wpntr_n_15}),
.\gic0.gc0.count_d2_reg[9] ({wpntr_n_0,wpntr_n_1}),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count));
dcfifo_32in_32out_32kb_wr_status_flags_as \gwas.wsts
(.E(E),
.comp1(comp1),
.comp2(comp2),
.full(full),
.p_1_out(p_1_out),
.ram_full_i(ram_full_i),
.rst_full_ff_i(rst_full_ff_i),
.v1_reg(v1_reg),
.v1_reg_0(v1_reg_0),
.wr_clk(wr_clk),
.wr_en(wr_en));
dcfifo_32in_32out_32kb_wr_bin_cntr wpntr
(.E(E),
.Q(Q),
.RD_PNTR_WR(RD_PNTR_WR),
.S({wpntr_n_16,wpntr_n_17,wpntr_n_18,wpntr_n_19}),
.\gic0.gc0.count_d1_reg[9]_0 (\gic0.gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9]_0 (\gic0.gc0.count_d2_reg[9] ),
.\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1] ),
.wr_clk(wr_clk),
.\wr_data_count_i_reg[9] ({wpntr_n_0,wpntr_n_1}),
.\wr_data_count_i_reg[9]_0 ({wpntr_n_12,wpntr_n_13,wpntr_n_14,wpntr_n_15}));
endmodule
(* ORIG_REF_NAME = "wr_status_flags_as" *)
module dcfifo_32in_32out_32kb_wr_status_flags_as
(comp1,
comp2,
full,
p_1_out,
E,
v1_reg,
v1_reg_0,
ram_full_i,
wr_clk,
rst_full_ff_i,
wr_en);
output comp1;
output comp2;
output full;
output p_1_out;
output [0:0]E;
input [4:0]v1_reg;
input [4:0]v1_reg_0;
input ram_full_i;
input wr_clk;
input rst_full_ff_i;
input wr_en;
wire [0:0]E;
wire comp1;
wire comp2;
wire full;
wire p_1_out;
wire ram_full_i;
wire rst_full_ff_i;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
wire wr_clk;
wire wr_en;
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1
(.I0(wr_en),
.I1(p_1_out),
.O(E));
dcfifo_32in_32out_32kb_compare c1
(.comp1(comp1),
.v1_reg(v1_reg));
dcfifo_32in_32out_32kb_compare_0 c2
(.comp2(comp2),
.v1_reg_0(v1_reg_0));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(ram_full_i),
.PRE(rst_full_ff_i),
.Q(p_1_out));
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(ram_full_i),
.PRE(rst_full_ff_i),
.Q(full));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A221OI_TB_V
`define SKY130_FD_SC_MS__A221OI_TB_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a221oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 B2 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 B2 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B2 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B2 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_ms__a221oi dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A221OI_TB_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_aa
//
// Generated
// by: wig
// on: Tue Jun 27 05:12:12 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_aa.v,v 1.1 2006/11/15 16:04:10 wig Exp $
// $Date: 2006/11/15 16:04:10 $
// $Log: ent_aa.v,v $
// Revision 1.1 2006/11/15 16:04:10 wig
// Added Files: Testcase for verilog include import
// ent_a.v ent_aa.v ent_ab.v ent_ac.v ent_ad.v ent_ae.v ent_b.v
// ent_ba.v ent_bb.v ent_t.v mix.cfg mix.log vinc_def.i
//
// Revision 1.6 2006/07/04 09:54:11 wig
// Update more testcases, add configuration/cfgfile
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of ent_aa
//
// No user `defines in this module
module ent_aa
//
// Generated Module inst_aa
//
(
port_aa_1, // Use internally test1
port_aa_2, // Use internally test2, no port generated
port_aa_3, // Interhierachy link, will create p_mix_sig_3_go
port_aa_4, // Interhierachy link, will create p_mix_sig_4_gi
port_aa_5, // Bus, single bits go to outside
port_aa_6, // Conflicting definition
sig_07, // Conflicting definition, IN false!
sig_08, // VHDL intermediate needed (port name)
sig_13, // Create internal signal name
sig_14 // Multiline comment 1
// Multiline comment 2
// Multiline comment 3
);
// Generated Module Inputs:
input port_aa_4;
// Generated Module Outputs:
output port_aa_1;
output port_aa_2;
output port_aa_3;
output [3:0] port_aa_5;
output [3:0] port_aa_6;
output [5:0] sig_07;
output [8:2] sig_08;
output [4:0] sig_13;
output [6:0] sig_14;
// Generated Wires:
wire port_aa_1;
wire port_aa_2;
wire port_aa_3;
wire port_aa_4;
wire [3:0] port_aa_5;
wire [3:0] port_aa_6;
wire [5:0] sig_07;
wire [8:2] sig_08;
wire [4:0] sig_13;
wire [6:0] sig_14;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of ent_aa
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module sram_test (
input wire FCLK_IN,
// full speed
inout wire [7:0] BUS_DATA,
input wire [15:0] ADD,
input wire RD_B,
input wire WR_B,
// high speed
inout wire [7:0] FD,
input wire FREAD,
input wire FSTROBE,
input wire FMODE,
//SRAM
output wire [19:0] SRAM_A,
inout wire [15:0] SRAM_IO,
output wire SRAM_BHE_B,
output wire SRAM_BLE_B,
output wire SRAM_CE1_B,
output wire SRAM_OE_B,
output wire SRAM_WE_B,
output wire [4:0] LED,
inout wire SDA,
inout wire SCL
);
assign SDA = 1'bz;
assign SCL = 1'bz;
assign LED = 5'b10110;
wire [15:0] BUS_ADD;
wire BUS_CLK, BUS_RD, BUS_WR, BUS_RST;
// BASIL bus mapping
assign BUS_CLK = FCLK_IN;
fx2_to_bus i_fx2_to_bus (
.ADD(ADD),
.RD_B(RD_B),
.WR_B(WR_B),
.BUS_CLK(BUS_CLK),
.BUS_ADD(BUS_ADD),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.CS_FPGA()
);
reset_gen i_reset_gen(.CLK(BUS_CLK), .RST(BUS_RST));
//MODULE ADREESSES
localparam GPIO_CONTROL_BASEADDR = 16'h0000;
localparam GPIO_CONTROL_HIGHADDR = 16'h000f;
localparam GPIO_PATTERN_BASEADDR = 16'h0010;
localparam GPIO_PATTERN_HIGHADDR = 16'h001f;
localparam FIFO_BASEADDR = 16'h0020;
localparam FIFO_HIGHADDR = 16'h002f;
localparam PULSE_BASEADDR = 32'h0030;
localparam PULSE_HIGHADDR = 32'h003f;
// USER MODULES //
wire [4:0] CONTROL_NOT_USED;
wire PATTERN_EN;
wire COUNTER_EN;
wire COUNTER_DIRECT;
gpio
#(
.BASEADDR(GPIO_CONTROL_BASEADDR),
.HIGHADDR(GPIO_CONTROL_HIGHADDR),
.IO_WIDTH(8),
.IO_DIRECTION(8'hff)
) i_gpio_control
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO({CONTROL_NOT_USED, COUNTER_DIRECT, PATTERN_EN, COUNTER_EN})
);
wire [31:0] PATTERN;
gpio
#(
.BASEADDR(GPIO_PATTERN_BASEADDR),
.HIGHADDR(GPIO_PATTERN_HIGHADDR),
.IO_WIDTH(32),
.IO_DIRECTION(32'hffffffff)
) i_gpio_pattern
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO(PATTERN)
);
wire PULSE;
pulse_gen
#(
.BASEADDR(PULSE_BASEADDR),
.HIGHADDR(PULSE_HIGHADDR)
) i_pulse_gen
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.PULSE_CLK(BUS_CLK),
.EXT_START(1'b0),
.PULSE(PULSE)
);
wire PATTERN_FIFO_READ;
wire PATTERN_FIFO_EMPTY;
wire [31:0] COUNTER_FIFO_DATA;
wire COUNTER_FIFO_EMPTY;
wire COUNTER_FIFO_READ;
wire ARB_READY_OUT, ARB_WRITE_OUT;
wire [31:0] ARB_DATA_OUT;
rrp_arbiter
#(
.WIDTH(2)
) i_rrp_arbiter
(
.RST(BUS_RST),
.CLK(BUS_CLK),
.WRITE_REQ({COUNTER_EN | PULSE, PATTERN_EN}),
.HOLD_REQ({2'b0}),
.DATA_IN({COUNTER_FIFO_DATA, PATTERN}),
.READ_GRANT({COUNTER_FIFO_READ, PATTERN_FIFO_READ}),
.READY_OUT(ARB_READY_OUT),
.WRITE_OUT(ARB_WRITE_OUT),
.DATA_OUT(ARB_DATA_OUT)
);
wire USB_READ;
assign USB_READ = FREAD && FSTROBE;
wire [7:0] FD_SRAM;
sram_fifo
#(
.BASEADDR(FIFO_BASEADDR),
.HIGHADDR(FIFO_HIGHADDR)
) i_out_fifo (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.SRAM_A(SRAM_A),
.SRAM_IO(SRAM_IO),
.SRAM_BHE_B(SRAM_BHE_B),
.SRAM_BLE_B(SRAM_BLE_B),
.SRAM_CE1_B(SRAM_CE1_B),
.SRAM_OE_B(SRAM_OE_B),
.SRAM_WE_B(SRAM_WE_B),
.USB_READ(USB_READ),
.USB_DATA(FD_SRAM),
.FIFO_READ_NEXT_OUT(ARB_READY_OUT),
.FIFO_EMPTY_IN(!ARB_WRITE_OUT),
.FIFO_DATA(ARB_DATA_OUT),
.FIFO_NOT_EMPTY(),
.FIFO_READ_ERROR(),
.FIFO_FULL(),
.FIFO_NEAR_FULL()
);
reg [31:0] count;
always@(posedge BUS_CLK)
if(BUS_RST)
count <= 0;
else if (COUNTER_FIFO_READ)
count <= count + 1;
wire [7:0] count_send [3:0];
assign count_send[0] = count*4;
assign count_send[1] = count*4 + 1;
assign count_send[2] = count*4 + 2;
assign count_send[3] = count*4 + 3;
assign COUNTER_FIFO_DATA = {count_send[3], count_send[2], count_send[1], count_send[0]};
reg [7:0] count_direct;
always@(posedge BUS_CLK)
if(BUS_RST)
count_direct <= 0;
else if (USB_READ)
count_direct <= count_direct + 1;
assign FD = COUNTER_DIRECT ? count_direct: FD_SRAM;
endmodule
|
// --------------------------------------------------------------------------------
//| Avalon Streaming Timing Adapter
// --------------------------------------------------------------------------------
`timescale 1ns / 100ps
module master_0_timing_adt (
// Interface: clk
input clk,
// Interface: reset
input reset_n,
// Interface: in
input in_valid,
input [ 7: 0] in_data,
// Interface: out
output reg out_valid,
output reg [ 7: 0] out_data,
input out_ready
);
// ---------------------------------------------------------------------
//| Signal Declarations
// ---------------------------------------------------------------------
reg [ 7: 0] in_payload;
reg [ 7: 0] out_payload;
reg [ 0: 0] ready;
reg in_ready;
// synthesis translate_off
always @(negedge in_ready) begin
$display("%m: The downstream component is backpressuring by deasserting ready, but the upstream component can't be backpressured.");
end
// synthesis translate_on
// ---------------------------------------------------------------------
//| Payload Mapping
// ---------------------------------------------------------------------
always @* begin
in_payload = {in_data};
{out_data} = out_payload;
end
// ---------------------------------------------------------------------
//| Ready & valid signals.
// ---------------------------------------------------------------------
always @* begin
ready[0] = out_ready;
out_valid = in_valid;
out_payload = in_payload;
in_ready = ready[0];
end
endmodule
|
`define TV80_CORE_PATH tb_top.tv80s_inst.i_tv80_core
module tb_top;
reg clk;
reg reset_n;
reg wait_n;
reg int_n;
reg nmi_n;
reg busrq_n;
wire m1_n;
wire mreq_n;
wire iorq_n;
wire rd_n;
wire wr_n;
wire rfsh_n;
wire halt_n;
wire busak_n;
wire [15:0] A;
wire [7:0] di;
wire [7:0] do;
wire ram_rd_cs, ram_wr_cs, rom_rd_cs;
reg tx_clk;
always
begin
clk = 1;
#5;
clk = 0;
#5;
end
always
begin
tx_clk = 0;
#8;
tx_clk = 1;
#8;
end
assign rom_rd_cs = !mreq_n & !rd_n & !A[15];
assign ram_rd_cs = !mreq_n & !rd_n & A[15];
assign ram_wr_cs = !mreq_n & !wr_n & A[15];
tv80s tv80s_inst
(
// Outputs
.m1_n (m1_n),
.mreq_n (mreq_n),
.iorq_n (iorq_n),
.rd_n (rd_n),
.wr_n (wr_n),
.rfsh_n (rfsh_n),
.halt_n (halt_n),
.busak_n (busak_n),
.A (A[15:0]),
.do (do[7:0]),
// Inputs
.reset_n (reset_n),
.clk (clk),
.wait_n (wait_n),
.int_n (int_n),
.nmi_n (nmi_n),
.busrq_n (busrq_n),
.di (di[7:0]));
async_mem ram
(
// Outputs
.rd_data (di),
// Inputs
.wr_clk (clk),
.wr_data (do),
.wr_cs (ram_wr_cs),
.addr (A[14:0]),
.rd_cs (ram_rd_cs));
async_mem rom
(
// Outputs
.rd_data (di),
// Inputs
.wr_clk (),
.wr_data (),
.wr_cs (1'b0),
.addr (A[14:0]),
.rd_cs (rom_rd_cs));
env_io env_io_inst
(
// Outputs
.DI (di[7:0]),
// Inputs
.clk (clk),
.iorq_n (iorq_n),
.rd_n (rd_n),
.wr_n (wr_n),
.addr (A[7:0]),
.DO (do[7:0]));
//----------------------------------------------------------------------
// UART
//----------------------------------------------------------------------
wire uart_cs_n;
wire [7:0] uart_rd_data;
wire sin;
wire cts_n;
wire dsr_n;
wire ri_n;
wire dcd_n;
wire sout;
wire rts_n;
wire dtr_n;
wire out1_n;
wire out2_n;
wire baudout;
wire intr;
// base address of 0x18 (24dec)
assign uart_cs_n = ~(!iorq_n & (A[7:3] == 5'h3));
assign di = (!uart_cs_n & !rd_n) ? uart_rd_data : 8'bz;
assign sin = sout;
T16450 uart0
(.reset_n (reset_n),
.clk (clk),
.rclk (baudout),
.cs_n (uart_cs_n),
.rd_n (rd_n),
.wr_n (wr_n),
.addr (A[2:0]),
.wr_data (do),
.rd_data (uart_rd_data),
.sin (sin),
.cts_n (cts_n),
.dsr_n (dsr_n),
.ri_n (ri_n),
.dcd_n (dcd_n),
.sout (sout),
.rts_n (rts_n),
.dtr_n (dtr_n),
.out1_n (out1_n),
.out2_n (out2_n),
.baudout (baudout),
.intr (intr));
//----------------------------------------------------------------------
// Network Interface
//----------------------------------------------------------------------
//wire nwintf_sel = !iorq_n & (A[7:3] == 5'b00001);
wire [7:0] rx_data, tx_data;
wire rx_clk, rx_dv, rx_er;
wire tx_dv, tx_er;
wire [7:0] nw_data_out;
wire nwintf_oe;
// loopback config
assign rx_data = tx_data;
assign rx_dv = tx_dv;
assign rx_er = tx_er;
assign rx_clk = tx_clk;
assign di = (nwintf_oe) ? nw_data_out : 8'bz;
simple_gmii_top nwintf
(
// unused outputs
.int_n (),
// Outputs
.tx_dv (tx_dv),
.tx_er (tx_er),
.tx_data (tx_data),
.tx_clk (tx_clk),
.rd_data (nw_data_out),
.doe (nwintf_oe),
// Inputs
.clk (clk),
.reset (!reset_n),
.rx_data (rx_data),
.rx_clk (rx_clk),
.rx_dv (rx_dv),
.rx_er (rx_er),
//.io_select (nwintf_sel),
.iorq_n (iorq_n),
.rd_n (rd_n),
.wr_n (wr_n),
.addr (A[15:0]),
.wr_data (do));
//----------------------------------------------------------------------
// Global Initialization
//----------------------------------------------------------------------
initial
begin
clear_ram;
reset_n = 0;
wait_n = 1;
int_n = 1;
nmi_n = 1;
busrq_n = 1;
$readmemh (`PROGRAM_FILE, tb_top.rom.mem);
repeat (20) @(negedge clk);
reset_n = 1;
end // initial begin
`ifdef DUMP_START
always
begin
if ($time > `DUMP_START)
dumpon;
#100;
end
`endif
/*
always
begin
while (mreq_n) @(posedge clk);
wait_n <= #1 0;
@(posedge clk);
wait_n <= #1 1;
while (!mreq_n) @(posedge clk);
end
*/
`ifdef TV80_INSTRUCTION_DECODE
reg [7:0] state;
initial
state = 0;
always @(posedge clk)
begin : inst_decode
if ((`TV80_CORE_PATH.mcycle[6:0] == 1) &&
(`TV80_CORE_PATH.tstate[6:0] == 8))
begin
op_decode.decode (`TV80_CORE_PATH.IR[7:0], state);
end
else if (`TV80_CORE_PATH.mcycle[6:0] != 1)
state = 0;
end
`endif
`include "env_tasks.v"
endmodule // tb_top
|
`include "uart.vh"
module uart_rx(
input clk_i,
input rx_i,
output [DATA_LENGTH - 1 : 0] tx_o,
output tx_o_v
);
localparam SAMPLE_RATE = `UART_RX_SAMPLE_RATE;
localparam SAMPLE_UPPER = `UART_RX_SAMPLE_UPPER;
localparam SAMPLE_MID = `UART_RX_SAMPLE_MID;
localparam SAMPLE_LOWER = `UART_RX_SAMPLE_LOWER;
localparam SAMPLE_WIDTH = $clog2(SAMPLE_RATE);
localparam PACKET_LENGTH = `UART_PACKET_LENGTH;
localparam PACKET_WIDTH = $clog2(PACKET_LENGTH);
localparam DATA_LENGTH = `UART_DATA_LENGTH;
localparam DATA_WIDTH = $clog2(DATA_LENGTH);
localparam ST_IDLE = 2'd0;
localparam ST_START = 2'd1;
localparam ST_DATA = 2'd2;
localparam ST_STOP = 2'd3;
reg [2 : 0] state = ST_IDLE;
reg rx_i_d = 0;
reg [PACKET_WIDTH - 1 : 0] ctr_bit = 0;
reg [SAMPLE_WIDTH - 1 : 0] ctr_sample = 0;
reg [SAMPLE_RATE - 1 : 0] rx_i_shift = 0;
reg rx_vote = 0;
reg [DATA_LENGTH - 1 : 0] s_tx_o = 0;
assign tx_o = s_tx_o;
assign tx_o_v = state == ST_STOP & rx_vote & ctr_sample == SAMPLE_UPPER;
always @ (posedge clk_i)
begin
if (ctr_sample == SAMPLE_RATE | state == ST_IDLE)
begin
ctr_sample <= 0;
end
else
begin
ctr_sample <= ctr_sample + 1;
end
end
always @ (posedge clk_i)
begin
if (state == ST_IDLE)
begin
ctr_bit <= 0;
end
else if (ctr_sample == SAMPLE_RATE - 1)
begin
ctr_bit <= ctr_bit + 1;
end
end
always @ (posedge clk_i)
begin
rx_i_shift <= { {rx_i_shift[SAMPLE_RATE - 2 : 0]} , {rx_i} };
end
always @ (posedge clk_i)
begin
rx_vote <= (rx_i_shift[SAMPLE_UPPER] & rx_i_shift[SAMPLE_MID])
| (rx_i_shift[SAMPLE_UPPER] & rx_i_shift[SAMPLE_LOWER])
| (rx_i_shift[SAMPLE_MID] & rx_i_shift[SAMPLE_LOWER]);
end
always @ (posedge clk_i)
begin
if (ctr_sample == SAMPLE_RATE - 1)
begin
s_tx_o <= { {rx_vote}, {s_tx_o[DATA_LENGTH - 1 : 1]} };
end
end
always @ (posedge clk_i)
begin
rx_i_d <= rx_i;
end
always @ (posedge clk_i)
begin
case (state)
ST_IDLE:
if (~rx_i & rx_i_d)
begin
state <= ST_START;
end
ST_START:
if (ctr_sample == SAMPLE_RATE - 1)
begin
state <= ST_DATA;
end
ST_DATA:
if (ctr_bit == DATA_LENGTH & ctr_sample == SAMPLE_RATE - 1 )
begin
state <= ST_STOP;
end
ST_STOP:
if (ctr_bit == PACKET_LENGTH - 1 & ctr_sample == SAMPLE_UPPER)
begin
state <= ST_IDLE;
end
endcase // case (state)
end // always @ (posedge clk_rx_i)
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21OI_4_V
`define SKY130_FD_SC_LP__A21OI_4_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog wrapper for a21oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a21oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21oi_4 (
Y ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a21oi_4 (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a21oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21OI_4_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_rxeq_scan.v
// Version : 3.0
//----------------------------------------------------------------------------//
// Filename : pcie3_7x_0_rxeq_scan.v
// Description : PIPE RX Equalization Eye Scan Module for 7 Series Transceiver
// Version : 18.0
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- RXEQ Eye Scan Module ----------------------------------------------
module pcie3_7x_0_rxeq_scan #
(
parameter PCIE_SIM_MODE = "FALSE", // PCIe sim mode
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_RXEQ_MODE_GEN3 = 1, // PCIe RX equalization mode
parameter CONVERGE_MAX = 22'd3125000, // Convergence max count (12ms)
parameter CONVERGE_MAX_BYPASS = 23'd4687500 // Convergence max count for phase2/3 bypass mode (8ms)
)
(
//---------- Input -------------------------------------
input RXEQSCAN_CLK,
input RXEQSCAN_RST_N,
input [ 1:0] RXEQSCAN_CONTROL,
input [ 2:0] RXEQSCAN_PRESET,
input RXEQSCAN_PRESET_VALID,
input [ 3:0] RXEQSCAN_TXPRESET,
input [17:0] RXEQSCAN_TXCOEFF,
input RXEQSCAN_NEW_TXCOEFF_REQ,
input [ 5:0] RXEQSCAN_FS,
input [ 5:0] RXEQSCAN_LF,
//---------- Output ------------------------------------
output RXEQSCAN_PRESET_DONE,
output [17:0] RXEQSCAN_NEW_TXCOEFF,
output RXEQSCAN_NEW_TXCOEFF_DONE,
output RXEQSCAN_LFFS_SEL,
output RXEQSCAN_ADAPT_DONE
);
//---------- Input Register ----------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] preset_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg preset_valid_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txpreset_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] txcoeff_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg new_txcoeff_req_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] fs_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] lf_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 2:0] preset_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg preset_valid_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 3:0] txpreset_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [17:0] txcoeff_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg new_txcoeff_req_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] fs_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 5:0] lf_reg2;
//---------- Internal Signals --------------------------
reg adapt_done_cnt = 1'd0;
//---------- Output Register ---------------------------
reg preset_done = 1'd0;
reg [22:0] converge_cnt = 23'd0;
reg [17:0] new_txcoeff = 18'd0;
reg new_txcoeff_done = 1'd0;
reg lffs_sel = 1'd0;
reg adapt_done = 1'd0;
reg [ 3:0] fsm = 4'd0;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 4'b0001;
localparam FSM_PRESET = 4'b0010;
localparam FSM_CONVERGE = 4'b0100;
localparam FSM_NEW_TXCOEFF_REQ = 4'b1000;
//---------- Simulation Speedup ------------------------
// Gen3: 32 bits / PCLK : 1 million bits / X PCLK
// X =
//------------------------------------------------------
localparam converge_max_cnt = (PCIE_SIM_MODE == "TRUE") ? 22'd1000 : CONVERGE_MAX;
localparam converge_max_bypass_cnt = (PCIE_SIM_MODE == "TRUE") ? 23'd1000 : CONVERGE_MAX_BYPASS;
//---------- Input FF ----------------------------------------------------------
always @ (posedge RXEQSCAN_CLK)
begin
if (!RXEQSCAN_RST_N)
begin
//---------- 1st Stage FF --------------------------
preset_reg1 <= 3'd0;
preset_valid_reg1 <= 1'd0;
txpreset_reg1 <= 4'd0;
txcoeff_reg1 <= 18'd0;
new_txcoeff_req_reg1 <= 1'd0;
fs_reg1 <= 6'd0;
lf_reg1 <= 6'd0;
//---------- 2nd Stage FF --------------------------
preset_reg2 <= 3'd0;
preset_valid_reg2 <= 1'd0;
txpreset_reg2 <= 4'd0;
txcoeff_reg2 <= 18'd0;
new_txcoeff_req_reg2 <= 1'd0;
fs_reg2 <= 6'd0;
lf_reg2 <= 6'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
preset_reg1 <= RXEQSCAN_PRESET;
preset_valid_reg1 <= RXEQSCAN_PRESET_VALID;
txpreset_reg1 <= RXEQSCAN_TXPRESET;
txcoeff_reg1 <= RXEQSCAN_TXCOEFF;
new_txcoeff_req_reg1 <= RXEQSCAN_NEW_TXCOEFF_REQ;
fs_reg1 <= RXEQSCAN_FS;
lf_reg1 <= RXEQSCAN_LF;
//---------- 2nd Stage FF --------------------------
preset_reg2 <= preset_reg1;
preset_valid_reg2 <= preset_valid_reg1;
txpreset_reg2 <= txpreset_reg1;
txcoeff_reg2 <= txcoeff_reg1;
new_txcoeff_req_reg2 <= new_txcoeff_req_reg1;
fs_reg2 <= fs_reg1;
lf_reg2 <= lf_reg1;
end
end
//---------- Eye Scan ----------------------------------------------------------
always @ (posedge RXEQSCAN_CLK)
begin
if (!RXEQSCAN_RST_N)
begin
fsm <= FSM_IDLE;
preset_done <= 1'd0;
converge_cnt <= 22'd0;
new_txcoeff <= 18'd0;
new_txcoeff_done <= 1'd0;
lffs_sel <= 1'd0;
adapt_done <= 1'd0;
adapt_done_cnt <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
//---------- Process RXEQ Preset ---------------
if (preset_valid_reg2)
begin
fsm <= FSM_PRESET;
preset_done <= 1'd1;
converge_cnt <= 22'd0;
new_txcoeff <= new_txcoeff;
new_txcoeff_done <= 1'd0;
lffs_sel <= 1'd0;
adapt_done <= 1'd0;
adapt_done_cnt <= adapt_done_cnt;
end
//---------- Request New TX Coefficient --------
else if (new_txcoeff_req_reg2)
begin
fsm <= FSM_CONVERGE;
preset_done <= 1'd0;
converge_cnt <= 22'd0;
new_txcoeff <= (PCIE_RXEQ_MODE_GEN3 == 0) ? txcoeff_reg2 : 18'd4; // Optimized for Gen3 RX JTOL
//new_txcoeff <= (PCIE_RXEQ_MODE_GEN3 == 0) ? txcoeff_reg2 : (PCIE_GT_DEVICE == "GTX") ? 18'd5 : 18'd4; // Optimized for Gen3 RX JTOL
new_txcoeff_done <= 1'd0;
lffs_sel <= (PCIE_RXEQ_MODE_GEN3 == 0) ? 1'd0 : 1'd1;
adapt_done <= 1'd0;
adapt_done_cnt <= adapt_done_cnt;
end
//---------- Default ---------------------------
else
begin
fsm <= FSM_IDLE;
preset_done <= 1'd0;
converge_cnt <= 22'd0;
new_txcoeff <= new_txcoeff;
new_txcoeff_done <= 1'd0;
lffs_sel <= 1'd0;
adapt_done <= 1'd0;
adapt_done_cnt <= adapt_done_cnt;
end
end
//---------- Process RXEQ Preset -------------------
FSM_PRESET :
begin
fsm <= (!preset_valid_reg2) ? FSM_IDLE : FSM_PRESET;
preset_done <= 1'd1;
converge_cnt <= 22'd0;
new_txcoeff <= new_txcoeff;
new_txcoeff_done <= 1'd0;
lffs_sel <= 1'd0;
adapt_done <= 1'd0;
adapt_done_cnt <= adapt_done_cnt;
end
//---------- Wait for Convergence ------------------
FSM_CONVERGE :
begin
if ((adapt_done_cnt == 1'd0) && (RXEQSCAN_CONTROL == 2'd2))
begin
fsm <= FSM_NEW_TXCOEFF_REQ;
preset_done <= 1'd0;
converge_cnt <= 22'd0;
new_txcoeff <= new_txcoeff;
new_txcoeff_done <= 1'd0;
lffs_sel <= lffs_sel;
adapt_done <= 1'd0;
adapt_done_cnt <= adapt_done_cnt;
end
else
begin
//---------- Phase2/3 ----------------------
if (RXEQSCAN_CONTROL == 2'd2)
fsm <= (converge_cnt == converge_max_cnt) ? FSM_NEW_TXCOEFF_REQ : FSM_CONVERGE;
//---------- Phase2/3 Bypass ---------------
else
fsm <= (converge_cnt == converge_max_bypass_cnt) ? FSM_NEW_TXCOEFF_REQ : FSM_CONVERGE;
preset_done <= 1'd0;
converge_cnt <= converge_cnt + 1'd1;
new_txcoeff <= new_txcoeff;
new_txcoeff_done <= 1'd0;
lffs_sel <= lffs_sel;
adapt_done <= 1'd0;
adapt_done_cnt <= adapt_done_cnt;
end
end
//---------- Request New TX Coefficient ------------
FSM_NEW_TXCOEFF_REQ :
begin
if (!new_txcoeff_req_reg2)
begin
fsm <= FSM_IDLE;
preset_done <= 1'd0;
converge_cnt <= 22'd0;
new_txcoeff <= new_txcoeff;
new_txcoeff_done <= 1'd0;
lffs_sel <= lffs_sel;
adapt_done <= 1'd0;
adapt_done_cnt <= (RXEQSCAN_CONTROL == 2'd3) ? 1'd0 : adapt_done_cnt + 1'd1;
end
else
begin
fsm <= FSM_NEW_TXCOEFF_REQ;
preset_done <= 1'd0;
converge_cnt <= 22'd0;
new_txcoeff <= new_txcoeff;
new_txcoeff_done <= 1'd1;
lffs_sel <= lffs_sel;
adapt_done <= (adapt_done_cnt == 1'd1) || (RXEQSCAN_CONTROL == 2'd3);
adapt_done_cnt <= adapt_done_cnt;
end
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_IDLE;
preset_done <= 1'd0;
converge_cnt <= 22'd0;
new_txcoeff <= 18'd0;
new_txcoeff_done <= 1'd0;
lffs_sel <= 1'd0;
adapt_done <= 1'd0;
adapt_done_cnt <= 1'd0;
end
endcase
end
end
//---------- RXEQ Eye Scan Output ----------------------------------------------
assign RXEQSCAN_PRESET_DONE = preset_done;
assign RXEQSCAN_NEW_TXCOEFF = new_txcoeff;
assign RXEQSCAN_NEW_TXCOEFF_DONE = new_txcoeff_done;
assign RXEQSCAN_LFFS_SEL = lffs_sel;
assign RXEQSCAN_ADAPT_DONE = adapt_done;
endmodule
|
//-----------------------------------------------------------------------------
// Pretend to be an ISO 14443 tag. We will do this by alternately short-
// circuiting and open-circuiting the antenna coil, with the tri-state
// pins.
//
// We communicate over the SSP, as a bitstream (i.e., might as well be
// unframed, though we still generate the word sync signal). The output
// (ARM -> FPGA) tells us whether to modulate or not. The input (FPGA
// -> ARM) is us using the A/D as a fancy comparator; this is with
// (software-added) hysteresis, to undo the high-pass filter.
//
// At this point only Type A is implemented. This means that we are using a
// bit rate of 106 kbit/s, or fc/128. Oversample by 4, which ought to make
// things practical for the ARM (fc/32, 423.8 kbits/s, ~50 kbytes/s)
//
// Jonathan Westhues, October 2006
//-----------------------------------------------------------------------------
module hi_simulate(
ck_1356meg,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
dbg,
mod_type
);
input ck_1356meg;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
output dbg;
input [3:0] mod_type;
// Power amp goes between LOW and tri-state, so pwr_hi (and pwr_lo) can
// always be low.
assign pwr_hi = 1'b0; // HF antenna connected to GND
assign pwr_lo = 1'b0; // LF antenna connected to GND
// This one is all LF, so doesn't matter
assign pwr_oe2 = 1'b0;
assign adc_clk = ck_1356meg;
assign dbg = ssp_frame;
// The comparator with hysteresis on the output from the peak detector.
reg after_hysteresis;
reg [11:0] has_been_low_for;
always @(negedge adc_clk)
begin
if (& adc_d[7:5]) after_hysteresis <= 1'b1; // if (adc_d >= 224)
else if (~(| adc_d[7:5])) after_hysteresis <= 1'b0; // if (adc_d <= 31)
if (adc_d >= 224)
begin
has_been_low_for <= 12'd0;
end
else
begin
if (has_been_low_for == 12'd4095)
begin
has_been_low_for <= 12'd0;
after_hysteresis <= 1'b1;
end
else
begin
has_been_low_for <= has_been_low_for + 1;
end
end
end
// Divide 13.56 MHz to produce various frequencies for SSP_CLK
// and modulation.
reg [8:0] ssp_clk_divider;
always @(negedge adc_clk)
ssp_clk_divider <= (ssp_clk_divider + 1);
reg ssp_clk;
always @(negedge adc_clk)
begin
if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K_8BIT)
// Get bit every at 53KHz (every 8th carrier bit of 424kHz)
ssp_clk <= ~ssp_clk_divider[7];
else if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
// Get next bit at 212kHz
ssp_clk <= ~ssp_clk_divider[5];
else
// Get next bit at 424kHz
ssp_clk <= ~ssp_clk_divider[4];
end
// Produce the byte framing signal; the phase of this signal
// is arbitrary, because it's just a bit stream in this module.
reg ssp_frame;
always @(negedge adc_clk)
begin
if (mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
begin
if (ssp_clk_divider[8:5] == 4'd1)
ssp_frame <= 1'b1;
if (ssp_clk_divider[8:5] == 4'd5)
ssp_frame <= 1'b0;
end
else
begin
if (ssp_clk_divider[7:4] == 4'd1)
ssp_frame <= 1'b1;
if (ssp_clk_divider[7:4] == 4'd5)
ssp_frame <= 1'b0;
end
end
// Synchronize up the after-hysteresis signal, to produce DIN.
reg ssp_din;
always @(posedge ssp_clk)
ssp_din = after_hysteresis;
// Modulating carrier frequency is fc/64 (212kHz) to fc/16 (848kHz). Reuse ssp_clk divider for that.
reg modulating_carrier;
always @(*)
if(mod_type == `FPGA_HF_SIMULATOR_NO_MODULATION)
modulating_carrier <= 1'b0; // no modulation
else if(mod_type == `FPGA_HF_SIMULATOR_MODULATE_BPSK)
modulating_carrier <= ssp_dout ^ ssp_clk_divider[3]; // XOR means BPSK
else if(mod_type == `FPGA_HF_SIMULATOR_MODULATE_212K)
modulating_carrier <= ssp_dout & ssp_clk_divider[5]; // switch 212kHz subcarrier on/off
else if(mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K || mod_type == `FPGA_HF_SIMULATOR_MODULATE_424K_8BIT)
modulating_carrier <= ssp_dout & ssp_clk_divider[4]; // switch 424kHz modulation on/off
else
modulating_carrier <= 1'b0; // yet unused
// Load modulation. Toggle only one of these, since we are already producing much deeper
// modulation than a real tag would.
assign pwr_oe1 = 1'b0; // 33 Ohms Load
assign pwr_oe4 = modulating_carrier; // 33 Ohms Load
// This one is always on, so that we can watch the carrier.
assign pwr_oe3 = 1'b0; // 10k Load
endmodule
|
//*****************************************************************************
// (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : infrastructure.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 07:17:09 $
// \ \ / \ Date Created : Mon Mar 2 2009
// \___\/\___\
//
//Device : Spartan-6
//Design Name : DDR/DDR2/DDR3/LPDDR
//Purpose : Clock generation/distribution and reset synchronization
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ns/1ps
module infrastructure #
(
parameter C_INCLK_PERIOD = 2500,
parameter C_RST_ACT_LOW = 1,
parameter C_INPUT_CLK_TYPE = "DIFFERENTIAL",
parameter C_CLKOUT0_DIVIDE = 1,
parameter C_CLKOUT1_DIVIDE = 1,
parameter C_CLKOUT2_DIVIDE = 16,
parameter C_CLKOUT3_DIVIDE = 8,
parameter C_CLKFBOUT_MULT = 2,
parameter C_DIVCLK_DIVIDE = 1
)
(
input sys_clk_p,
input sys_clk_n,
input sys_clk,
input sys_rst_i,
output clk0,
output rst0,
output async_rst,
output sysclk_2x,
output sysclk_2x_180,
output mcb_drp_clk,
output pll_ce_0,
output pll_ce_90,
output pll_lock
);
// # of clock cycles to delay deassertion of reset. Needs to be a fairly
// high number not so much for metastability protection, but to give time
// for reset (i.e. stable clock cycles) to propagate through all state
// machines and to all control signals (i.e. not all control signals have
// resets, instead they rely on base state logic being reset, and the effect
// of that reset propagating through the logic). Need this because we may not
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on PLL/DCM lock status)
localparam RST_SYNC_NUM = 25;
localparam CLK_PERIOD_NS = C_INCLK_PERIOD / 1000.0;
localparam CLK_PERIOD_INT = C_INCLK_PERIOD/1000;
wire clk_2x_0;
wire clk_2x_180;
wire clk0_bufg;
wire clk0_bufg_in;
wire mcb_drp_clk_bufg_in;
wire clkfbout_clkfbin;
wire locked;
reg [RST_SYNC_NUM-1:0] rst0_sync_r /* synthesis syn_maxfan = 10 */;
wire rst_tmp;
reg powerup_pll_locked;
reg syn_clk0_powerup_pll_locked;
wire sys_rst;
wire bufpll_mcb_locked;
(* KEEP = "TRUE" *) wire sys_clk_ibufg;
assign sys_rst = C_RST_ACT_LOW ? ~sys_rst_i: sys_rst_i;
assign clk0 = clk0_bufg;
assign pll_lock = bufpll_mcb_locked;
assign sys_clk_ibufg = sys_clk;
/*
generate
if (C_INPUT_CLK_TYPE == "DIFFERENTIAL") begin: diff_input_clk
//***********************************************************************
// Differential input clock input buffers
//***********************************************************************
IBUFGDS #
(
.DIFF_TERM ("TRUE")
)
u_ibufg_sys_clk
(
.I (sys_clk_p),
.IB (sys_clk_n),
.O (sys_clk_ibufg)
);
end else if (C_INPUT_CLK_TYPE == "SINGLE_ENDED") begin: se_input_clk
//***********************************************************************
// SINGLE_ENDED input clock input buffers
//***********************************************************************
IBUFG u_ibufg_sys_clk
(
.I (sys_clk),
.O (sys_clk_ibufg)
);
end
endgenerate
*/
//***************************************************************************
// Global clock generation and distribution
//***************************************************************************
PLL_ADV #
(
.BANDWIDTH ("OPTIMIZED"),
.CLKIN1_PERIOD (CLK_PERIOD_NS),
.CLKIN2_PERIOD (CLK_PERIOD_NS),
.CLKOUT0_DIVIDE (C_CLKOUT0_DIVIDE),
.CLKOUT1_DIVIDE (C_CLKOUT1_DIVIDE),
.CLKOUT2_DIVIDE (C_CLKOUT2_DIVIDE),
.CLKOUT3_DIVIDE (C_CLKOUT3_DIVIDE),
.CLKOUT4_DIVIDE (1),
.CLKOUT5_DIVIDE (1),
.CLKOUT0_PHASE (0.000),
.CLKOUT1_PHASE (180.000),
.CLKOUT2_PHASE (0.000),
.CLKOUT3_PHASE (0.000),
.CLKOUT4_PHASE (0.000),
.CLKOUT5_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT4_DUTY_CYCLE (0.500),
.CLKOUT5_DUTY_CYCLE (0.500),
.SIM_DEVICE ("SPARTAN6"),
.COMPENSATION ("INTERNAL"),
.DIVCLK_DIVIDE (C_DIVCLK_DIVIDE),
.CLKFBOUT_MULT (C_CLKFBOUT_MULT),
.CLKFBOUT_PHASE (0.0),
.REF_JITTER (0.005000)
)
u_pll_adv
(
.CLKFBIN (clkfbout_clkfbin),
.CLKINSEL (1'b1),
.CLKIN1 (sys_clk_ibufg),
.CLKIN2 (1'b0),
.DADDR (5'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DWE (1'b0),
.REL (1'b0),
.RST (sys_rst),
.CLKFBDCM (),
.CLKFBOUT (clkfbout_clkfbin),
.CLKOUTDCM0 (),
.CLKOUTDCM1 (),
.CLKOUTDCM2 (),
.CLKOUTDCM3 (),
.CLKOUTDCM4 (),
.CLKOUTDCM5 (),
.CLKOUT0 (clk_2x_0),
.CLKOUT1 (clk_2x_180),
.CLKOUT2 (clk0_bufg_in),
.CLKOUT3 (mcb_drp_clk_bufg_in),
.CLKOUT4 (),
.CLKOUT5 (),
.DO (),
.DRDY (),
.LOCKED (locked)
);
BUFG U_BUFG_CLK0
(
.O (clk0_bufg),
.I (clk0_bufg_in)
);
BUFGCE U_BUFG_CLK1
(
.O (mcb_drp_clk),
.I (mcb_drp_clk_bufg_in),
.CE (locked)
);
always @(posedge mcb_drp_clk , posedge sys_rst)
if(sys_rst)
powerup_pll_locked <= 1'b0;
else if (bufpll_mcb_locked)
powerup_pll_locked <= 1'b1;
always @(posedge clk0_bufg , posedge sys_rst)
if(sys_rst)
syn_clk0_powerup_pll_locked <= 1'b0;
else if (bufpll_mcb_locked)
syn_clk0_powerup_pll_locked <= 1'b1;
//***************************************************************************
// Reset synchronization
// NOTES:
// 1. shut down the whole operation if the PLL hasn't yet locked (and
// by inference, this means that external SYS_RST_IN has been asserted -
// PLL deasserts LOCKED as soon as SYS_RST_IN asserted)
// 2. asynchronously assert reset. This was we can assert reset even if
// there is no clock (needed for things like 3-stating output buffers).
// reset deassertion is synchronous.
// 3. asynchronous reset only look at pll_lock from PLL during power up. After
// power up and pll_lock is asserted, the powerup_pll_locked will be asserted
// forever until sys_rst is asserted again. PLL will lose lock when FPGA
// enters suspend mode. We don't want reset to MCB get
// asserted in the application that needs suspend feature.
//***************************************************************************
assign async_rst = sys_rst | ~powerup_pll_locked;
// synthesis attribute max_fanout of rst0_sync_r is 10
assign rst_tmp = sys_rst | ~syn_clk0_powerup_pll_locked;
always @(posedge clk0_bufg or posedge rst_tmp)
if (rst_tmp)
rst0_sync_r <= {RST_SYNC_NUM{1'b1}};
else
// logical left shift by one (pads with 0)
rst0_sync_r <= rst0_sync_r << 1;
assign rst0 = rst0_sync_r[RST_SYNC_NUM-1];
BUFPLL_MCB BUFPLL_MCB1
( .IOCLK0 (sysclk_2x),
.IOCLK1 (sysclk_2x_180),
.LOCKED (locked),
.GCLK (mcb_drp_clk),
.SERDESSTROBE0 (pll_ce_0),
.SERDESSTROBE1 (pll_ce_90),
.PLLIN0 (clk_2x_0),
.PLLIN1 (clk_2x_180),
.LOCK (bufpll_mcb_locked)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__FILL_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HVL__FILL_BEHAVIORAL_PP_V
/**
* fill: Fill cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__fill (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__FILL_BEHAVIORAL_PP_V |
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA core logic
*/
module fpga_core #
(
parameter TARGET = "GENERIC"
)
(
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T GMII
*/
input wire phy_rx_clk,
input wire [7:0] phy_rxd,
input wire phy_rx_dv,
input wire phy_rx_er,
output wire phy_gtx_clk,
input wire phy_tx_clk,
output wire [7:0] phy_txd,
output wire phy_tx_en,
output wire phy_tx_er,
output wire phy_reset_n,
/*
* UART: 115200 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd
);
// AXI between MAC and Ethernet modules
wire [7:0] rx_axis_tdata;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [7:0] tx_axis_tdata;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [7:0] rx_eth_payload_axis_tdata;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [7:0] tx_eth_payload_axis_tdata;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [7:0] rx_ip_payload_axis_tdata;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [7:0] tx_ip_payload_axis_tdata;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [7:0] rx_udp_payload_axis_tdata;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [7:0] tx_udp_payload_axis_tdata;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [7:0] rx_fifo_udp_payload_axis_tdata;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [7:0] tx_fifo_udp_payload_axis_tdata;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = !match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk) begin
if (rst) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((!match_cond_reg && !no_match_reg) ||
(rx_udp_payload_axis_tvalid && rx_udp_payload_axis_tready && rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid && match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready && match_cond) || no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid && match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready && match_cond_reg) || no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk) begin
if (rst) begin
led_reg <= 0;
end else begin
if (tx_udp_payload_axis_tvalid) begin
if (!valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
valid_last <= 1'b1;
end
if (tx_udp_payload_axis_tlast) begin
valid_last <= 1'b0;
end
end
end
end
//assign led = sw;
assign led = led_reg;
assign phy_reset_n = !rst;
assign uart_txd = 0;
eth_mac_1g_gmii_fifo #(
.TARGET(TARGET),
.IODDR_STYLE("IODDR2"),
.CLOCK_INPUT_STYLE("BUFIO2"),
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.gtx_clk(clk),
.gtx_rst(rst),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.gmii_rx_clk(phy_rx_clk),
.gmii_rxd(phy_rxd),
.gmii_rx_dv(phy_rx_dv),
.gmii_rx_er(phy_rx_er),
.gmii_tx_clk(phy_gtx_clk),
.mii_tx_clk(phy_tx_clk),
.gmii_txd(phy_txd),
.gmii_tx_en(phy_tx_en),
.gmii_tx_er(phy_tx_er),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.speed(),
.ifg_delay(12)
);
eth_axis_rx
eth_axis_rx_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx
eth_axis_tx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete
udp_complete_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(0),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
`resetall
|
`default_nettype none
module l1_data_cache_64entry_4way_line64b_bus_8b_disable_cache(
/********************************
System
********************************/
input wire iCLOCK,
input wire inRESET,
input wire iRESET_SYNC,
//Remove
input wire iREMOVE,
/********************************
Search
********************************/
//Search Request
input wire iRD_REQ,
output wire oRD_BUSY,
input wire [31:0] iRD_ADDR, //Tag:22bit | Index:4bit(4Way*16Entry) | LineSize:6bit(64B)
//Search Output Result
output wire oRD_VALID,
output wire oRD_HIT,
input wire iRD_BUSY,
output wire [31:0] oRD_DATA,
output wire [11:0] oRD_MMU_FLAGS,
/********************************
Upload
********************************/
input wire iUP_REQ,
output wire oUP_BUSY,
input wire [1:0] iUP_ORDER,
input wire [3:0] iUP_MASK,
input wire [31:0] iUP_ADDR,
input wire [31:0] iUP_DATA,
/********************************
Write Request
********************************/
input wire iWR_REQ,
output wire oWR_BUSY,
input wire [31:0] iWR_ADDR, //Tag:22bit | Index:4bit(4Way*16Entry) | LineSize:6bit(64B)
input wire [511:0] iWR_DATA,
input wire [255:0] iWR_MMU_FLAGS
);
assign oRD_BUSY = 1'b0;
assign oRD_MMU_FLAGS = 11'h0;
reg b_req_valid;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
b_req_valid <= 1'b0;
end
else if(iRESET_SYNC)begin
b_req_valid <= 1'b0;
end
else if(iREMOVE)begin
b_req_valid <= 1'b0;
end
else begin
b_req_valid <= iRD_REQ;
end
end
assign oRD_VALID = b_req_valid;
assign oRD_HIT = 1'b0;
assign oRD_DATA = 32'h0;
assign oUP_BUSY = 1'b0;
assign oWR_BUSY = 1'b0;
endmodule
`default_nettype wire
|
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