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// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_ifu_thrcmpl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_ifu_thrcmpl
// Description:
// The thread completion block processes the completion signals fomr
// the different cpu blocks and generates a unified completion
// signal.
*/
module sparc_ifu_thrcmpl(/*AUTOARG*/
// Outputs
completion, wm_imiss, wm_other,
// Inputs
clk, se, si, reset, fcl_ifq_icmiss_s1, erb_dtu_ifeterr_d1,
sw_cond_s, en_spec_g, atr_s, dtu_fcl_thr_active, ifq_dtu_thrrdy,
ifq_dtu_pred_rdy, exu_lop_done, branch_done_d, fixedop_done,
ldmiss, spec_ld_d, trap, retr_thr_wakeup, flush_wake_w2,
ldhit_thr, spec_ld_g, clear_wmo_e, wm_stbwait, stb_retry,
rst_thread, trap_thrrdy, thr_s2, thr_e, thr_s1, fp_thrrdy,
lsu_ifu_ldst_cmplt, sta_done_e, killed_inst_done_e
);
input clk, se, si, reset;
input fcl_ifq_icmiss_s1;
input erb_dtu_ifeterr_d1;
input sw_cond_s;
input en_spec_g;
input atr_s;
input [3:0] dtu_fcl_thr_active;
input [3:0] ifq_dtu_thrrdy, // I$ miss completion
ifq_dtu_pred_rdy,
exu_lop_done, // mul, div, wrpr, sav, rest
branch_done_d,
fixedop_done; // br, rdsr, wrs/pr,
input [3:0] ldmiss,
spec_ld_d,
trap,
retr_thr_wakeup,
flush_wake_w2,
ldhit_thr,
spec_ld_g;
input clear_wmo_e;
input [3:0] wm_stbwait,
stb_retry;
input [3:0] rst_thread,
trap_thrrdy;
input [3:0] thr_s2,
thr_e,
thr_s1;
input [3:0] fp_thrrdy;
input [3:0] lsu_ifu_ldst_cmplt; // sta local, ld and atomic done
input sta_done_e,
killed_inst_done_e; // long lat op was killed
// .. Other completion signals needed
// 1. STA completion from LSU -- real mem done 10/03, local TBD
// 2. Atomic completion -- done
// 3. membar completion (lsu) -- done
// 4. flush completion (lsu)
// 5. FP op completion (ffu)
//
output [3:0] completion;
output [3:0] wm_imiss;
output [3:0] wm_other;
// local signals
wire [3:0] wm_imiss,
wm_other,
wmi_nxt,
wmo_nxt;
wire [3:0] clr_wmo_thr_e;
wire [3:0] ldst_thrrdy,
ld_thrrdy,
sta_thrrdy,
killed_thrrdy,
fp_thrrdy,
pred_ifq_rdy,
imiss_thrrdy,
other_thrrdy;
// wire [3:0] can_imiss;
//----------------------------------------------------------------------
// Code begins here
//----------------------------------------------------------------------
// Thread completion
// Since an imiss can overlap with anything else, have to make sure
// the imiss condition has been cleared.
// Imiss itself has to make sure ALL OTHER conditions have been
// cleared. In this code, I am not checking for branches being
// cleared, since Imiss is assumed to take much longer than a branch.
// -- may not be a valid assumption, since milhits could be faster
// assign can_imiss = fcl_ifq_canthr;
// & (wm_imiss | ({4{fcl_ifq_icmiss_s1}} & thr_s1));
dffr_s #(4) wmi_ff(.din (wmi_nxt),
.clk (clk),
.q (wm_imiss),
.rst (reset),
.se (se), .si(), .so());
dffr_s #(4) wmo_ff(.din (wmo_nxt),
.clk (clk),
.q (wm_other),
.rst (reset),
.se (se), .si(), .so());
assign wmi_nxt = ({4{fcl_ifq_icmiss_s1}} & thr_s1) | // set
({4{erb_dtu_ifeterr_d1}} & thr_e) |
(wm_imiss & ~imiss_thrrdy); // reset
// clear wm_other when we have a retracted store
assign clr_wmo_thr_e = {4{clear_wmo_e}} & thr_e;
assign wmo_nxt = (({4{sw_cond_s}} & thr_s2 & ~clr_wmo_thr_e) |
trap | ldmiss) & dtu_fcl_thr_active |
rst_thread | // set
wm_other & dtu_fcl_thr_active &
~(other_thrrdy | spec_ld_d | clr_wmo_thr_e); // reset
// A load hit signal is always for the load which is being filled
// to the RF. If speculation is enabled, the load would have
// completed even before the hit signal. So need to suppress the
// completions signal.
// load miss, st buf hit, ld/st alternate completion
assign ldst_thrrdy = lsu_ifu_ldst_cmplt & ~spec_ld_g;
assign ld_thrrdy = ldhit_thr & {4{~en_spec_g}};
assign sta_thrrdy = thr_e & {4{sta_done_e}};
assign killed_thrrdy = thr_e & {4{killed_inst_done_e}};
// everthing else
assign other_thrrdy = (ldst_thrrdy | // ld, sta local, atomic
branch_done_d | // br
ld_thrrdy | // load hit without spec
exu_lop_done | // mul, div, win mgmt
fixedop_done | // rdsr, wrspr
killed_thrrdy | // ll op was anulled
retr_thr_wakeup | // retract cond compl
flush_wake_w2 | // wake up after ecc
fp_thrrdy | // fp completion
sta_thrrdy | // sta to real memory
trap_thrrdy); // trap
// Imiss predicted ready
assign pred_ifq_rdy = ifq_dtu_pred_rdy & {4{~atr_s}} & dtu_fcl_thr_active;
assign imiss_thrrdy = pred_ifq_rdy | ifq_dtu_thrrdy;
// assign completion = imiss_thrrdy & (~(wm_other | wm_stbwait) |
// other_thrrdy) | //see C1
// other_thrrdy & (~(wm_imiss | wmi_nxt));
// assign completion = (imiss_thrrdy & ~(wm_other | wm_stbwait) |
// other_thrrdy & ~(wm_stbwait | wm_imiss) |
// stb_retry & ~(wm_other | wm_imiss) |
// imiss_thrrdy & other_thrrdy & ~wm_stbwait |
// imiss_thrrdy & stb_retry & ~wm_other |
// stb_retry & other_thrrdy & ~wm_imiss);
assign completion = ((imiss_thrrdy | ~wm_imiss) &
(other_thrrdy | ~wm_other) &
(stb_retry | ~wm_stbwait) &
(wm_imiss | wm_other | wm_stbwait));
// C1: should we do ~(wm_other | wmo_nxt)??
// When an imiss is pending, we cannot be doing another fetch, so I
// don't think so. It seems nice and symmetric to put it in
// though, unfortunately this results in a timing problem on swc_s
// and trap
endmodule // sparc_ifu_thrcmpl
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:45:55 04/23/2017
// Design Name:
// Module Name: decrypt_tb
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module decrypt_tb ;
reg clk_tb, reset_tb, ack_tb, enable_tb;
wire done_tb;
wire [7:0][7:0] message_tb, DESkey_tb;
wire [7:0][7:0] decrypted_tb;
parameter CLK_PERIOD = 20;
decrypt d(
message_tb,
DESkey_tb,
decrypted_tb,
done_tb,
clk_tb,
reset_tb,
enable_tb,
ack_tb
);
initial
begin : CLK_GENERATOR
clk_tb = 0;
forever
begin
#(CLK_PERIOD / 2) clk_tb = ~clk_tb;
end
end
initial
begin : RESET_GENERATOR
reset_tb = 1;
#(2 * CLK_PERIOD) reset_tb = 1;
end
initial
begin : STIMULUS
message_tb = 8'h0;
DESkey_tb = 8'h0;
enable_tb = 0;
ack_tb = 0;
wait(!reset_tb);
@(posedge clk_tb);
//test 1
@(posedge clk_tb);
#1;
message_tb = "waterbot";
DESkey = "hellodar";
enable_tb = 1;
@(posedge clk_tb);
#5;
enable_tb = 0;
wait(done_tb);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A311OI_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__A311OI_PP_BLACKBOX_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a311oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A311OI_PP_BLACKBOX_V
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: infrastructure.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $
// \ \ / \ Date Created:Tue Jun 30 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Clock generation/distribution and reset synchronization
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: infrastructure.v,v 1.1 2011/06/02 08:34:56 mishra Exp $
**$Date: 2011/06/02 08:34:56 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/clocking/infrastructure.v,v $
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v1_9_infrastructure #
(
parameter SIMULATION = "FALSE", // Should be TRUE during design simulations and
// FALSE during implementations
parameter TCQ = 100, // clk->out delay (sim only)
parameter CLKIN_PERIOD = 3000, // Memory clock period
parameter nCK_PER_CLK = 2, // Fabric clk period:Memory clk period
parameter SYSCLK_TYPE = "DIFFERENTIAL",
// input clock type
// "DIFFERENTIAL","SINGLE_ENDED"
parameter UI_EXTRA_CLOCKS = "FALSE",
// Generates extra clocks as
// 1/2, 1/4 and 1/8 of fabrick clock.
// Valid for DDR2/DDR3 AXI interfaces
// based on GUI selection
parameter CLKFBOUT_MULT = 4, // write PLL VCO multiplier
parameter DIVCLK_DIVIDE = 1, // write PLL VCO divisor
parameter CLKOUT0_PHASE = 45.0, // VCO output divisor for clkout0
parameter CLKOUT0_DIVIDE = 16, // VCO output divisor for PLL clkout0
parameter CLKOUT1_DIVIDE = 4, // VCO output divisor for PLL clkout1
parameter CLKOUT2_DIVIDE = 64, // VCO output divisor for PLL clkout2
parameter CLKOUT3_DIVIDE = 16, // VCO output divisor for PLL clkout3
parameter MMCM_CLKOUT0_EN = "FALSE", // Enabled (or) Disable MMCM clkout0
parameter MMCM_CLKOUT1_EN = "FALSE", // Enabled (or) Disable MMCM clkout1
parameter MMCM_CLKOUT2_EN = "FALSE", // Enabled (or) Disable MMCM clkout2
parameter MMCM_CLKOUT3_EN = "FALSE", // Enabled (or) Disable MMCM clkout3
parameter MMCM_CLKOUT4_EN = "FALSE", // Enabled (or) Disable MMCM clkout4
parameter MMCM_CLKOUT0_DIVIDE = 1, // VCO output divisor for MMCM clkout0
parameter MMCM_CLKOUT1_DIVIDE = 1, // VCO output divisor for MMCM clkout1
parameter MMCM_CLKOUT2_DIVIDE = 1, // VCO output divisor for MMCM clkout2
parameter MMCM_CLKOUT3_DIVIDE = 1, // VCO output divisor for MMCM clkout3
parameter MMCM_CLKOUT4_DIVIDE = 1, // VCO output divisor for MMCM clkout4
parameter RST_ACT_LOW = 1
)
(
// Clock inputs
input mmcm_clk, // System clock diff input
// System reset input
input sys_rst, // core reset from user application
// PLLE2/IDELAYCTRL Lock status
input iodelay_ctrl_rdy, // IDELAYCTRL lock status
// Clock outputs
output clk, // fabric clock freq ; either half rate or quarter rate and is
// determined by PLL parameters settings.
output mem_refclk, // equal to memory clock
output freq_refclk, // freq above 400 MHz: set freq_refclk = mem_refclk
// freq below 400 MHz: set freq_refclk = 2* mem_refclk or 4* mem_refclk;
// to hard PHY for phaser
output sync_pulse, // exactly 1/16 of mem_refclk and the sync pulse is exactly 1 memref_clk wide
output auxout_clk, // IO clk used to clock out Aux_Out ports
output ui_addn_clk_0, // MMCM out0 clk
output ui_addn_clk_1, // MMCM out1 clk
output ui_addn_clk_2, // MMCM out2 clk
output ui_addn_clk_3, // MMCM out3 clk
output ui_addn_clk_4, // MMCM out4 clk
output pll_locked, // locked output from PLLE2_ADV
output mmcm_locked, // locked output from MMCME2_ADV
// Reset outputs
output rstdiv0 // Reset CLK and CLKDIV logic (incl I/O),
,output rst_phaser_ref
,input ref_dll_lock
,output ref_clk
,input rst_tmp_idelay,
input rst_ref
);
// # of clock cycles to delay deassertion of reset. Needs to be a fairly
// high number not so much for metastability protection, but to give time
// for reset (i.e. stable clock cycles) to propagate through all state
// machines and to all control signals (i.e. not all control signals have
// resets, instead they rely on base state logic being reset, and the effect
// of that reset propagating through the logic). Need this because we may not
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on DCM lock status)
localparam RST_SYNC_NUM = 25;
// Round up for clk reset delay to ensure that CLKDIV reset deassertion
// occurs at same time or after CLK reset deassertion (still need to
// consider route delay - add one or two extra cycles to be sure!)
localparam RST_DIV_SYNC_NUM = (RST_SYNC_NUM+1)/2;
// Input clock is assumed to be equal to the memory clock frequency
// User should change the parameter as necessary if a different input
// clock frequency is used
localparam real CLKIN1_PERIOD_NS = CLKIN_PERIOD / 1000.0;
localparam CLKOUT4_DIVIDE = 2 * CLKOUT1_DIVIDE;
localparam integer VCO_PERIOD
= (CLKIN1_PERIOD_NS * DIVCLK_DIVIDE * 1000) / CLKFBOUT_MULT;
localparam CLKOUT0_PERIOD = VCO_PERIOD * CLKOUT0_DIVIDE;
localparam CLKOUT1_PERIOD = VCO_PERIOD * CLKOUT1_DIVIDE;
localparam CLKOUT2_PERIOD = VCO_PERIOD * CLKOUT2_DIVIDE;
localparam CLKOUT3_PERIOD = VCO_PERIOD * CLKOUT3_DIVIDE;
localparam CLKOUT4_PERIOD = VCO_PERIOD * CLKOUT4_DIVIDE;
localparam CLKOUT4_PHASE = (SIMULATION == "TRUE") ? 22.5 : 168.75;
localparam real CLKOUT3_PERIOD_NS = CLKOUT3_PERIOD / 1000.0;
localparam real CLKOUT4_PERIOD_NS = CLKOUT4_PERIOD / 1000.0;
localparam CLKOUT5_DIVIDE = 4;
localparam CLKOUT5_PHASE = 0.000;
//synthesis translate_off
initial begin
$display("############# Write Clocks PLLE2_ADV Parameters #############\n");
$display("nCK_PER_CLK = %7d", nCK_PER_CLK );
$display("CLK_PERIOD = %7d", CLKIN_PERIOD );
$display("CLKIN1_PERIOD = %7.3f", CLKIN1_PERIOD_NS);
$display("DIVCLK_DIVIDE = %7d", DIVCLK_DIVIDE );
$display("CLKFBOUT_MULT = %7d", CLKFBOUT_MULT );
$display("VCO_PERIOD = %7d", VCO_PERIOD );
$display("CLKOUT0_DIVIDE_F = %7d", CLKOUT0_DIVIDE );
$display("CLKOUT1_DIVIDE = %7d", CLKOUT1_DIVIDE );
$display("CLKOUT2_DIVIDE = %7d", CLKOUT2_DIVIDE );
$display("CLKOUT3_DIVIDE = %7d", CLKOUT3_DIVIDE );
$display("CLKOUT0_PERIOD = %7d", CLKOUT0_PERIOD );
$display("CLKOUT1_PERIOD = %7d", CLKOUT1_PERIOD );
$display("CLKOUT2_PERIOD = %7d", CLKOUT2_PERIOD );
$display("CLKOUT3_PERIOD = %7d", CLKOUT3_PERIOD );
$display("CLKOUT4_PERIOD = %7d", CLKOUT4_PERIOD );
$display("############################################################\n");
end
//synthesis translate_on
wire clk_bufg;
wire clk_pll;
wire clkfbout_pll;
wire mmcm_clkfbout;
(* keep = "true", max_fanout = 10 *) wire pll_locked_i
/* synthesis syn_maxfan = 10 */;
reg [RST_DIV_SYNC_NUM-2:0] rstdiv0_sync_r;
wire rst_tmp;
(* keep = "true", max_fanout = 10 *) reg rstdiv0_sync_r1
/* synthesis syn_maxfan = 10 */;
wire sys_rst_act_hi;
wire rst_tmp_phaser_ref;
(* keep = "true", max_fanout = 10 *) reg [RST_DIV_SYNC_NUM-1:0] rst_phaser_ref_sync_r
/* synthesis syn_maxfan = 10 */;
// Instantiation of the MMCM primitive
wire clkfbout;
wire MMCM_Locked_i;
wire mmcm_clkout0;
wire mmcm_clkout1;
wire mmcm_clkout2;
wire mmcm_clkout3;
wire mmcm_clkout4;
wire ref_clk_mmcm_bufg;
assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst: sys_rst;
//***************************************************************************
// Assign global clocks:
// 2. clk : Half rate / Quarter rate(used for majority of internal logic)
//***************************************************************************
assign clk = clk_bufg;
assign pll_locked = pll_locked_i & MMCM_Locked_i;
assign mmcm_locked = MMCM_Locked_i;
assign ref_clk = ref_clk_mmcm_bufg;
//***************************************************************************
// Global base clock generation and distribution
//***************************************************************************
//*****************************************************************
// NOTES ON CALCULTING PROPER VCO FREQUENCY
// 1. VCO frequency =
// 1/((DIVCLK_DIVIDE * CLKIN_PERIOD)/(CLKFBOUT_MULT * nCK_PER_CLK))
// 2. VCO frequency must be in the range [TBD, TBD]
//*****************************************************************
PLLE2_ADV #
(
.BANDWIDTH ("OPTIMIZED"),
.COMPENSATION ("INTERNAL"),
.STARTUP_WAIT ("FALSE"),
.CLKOUT0_DIVIDE (CLKOUT0_DIVIDE), // 4 freq_ref
.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE), // 4 mem_ref
.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE), // 16 sync
.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE), // 16 sysclk
.CLKOUT4_DIVIDE (CLKOUT4_DIVIDE),
.CLKOUT5_DIVIDE (CLKOUT5_DIVIDE),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_PHASE (0.000),
.CLKIN1_PERIOD (CLKIN1_PERIOD_NS),
.CLKIN2_PERIOD (),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_PHASE (CLKOUT0_PHASE),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (1.0/16.0),
.CLKOUT2_PHASE (9.84375), // PHASE shift is required for sync pulse generation.
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT3_PHASE (0.000),
.CLKOUT4_DUTY_CYCLE (0.500),
.CLKOUT4_PHASE (CLKOUT4_PHASE),
.CLKOUT5_DUTY_CYCLE (0.500),
.CLKOUT5_PHASE (CLKOUT5_PHASE),
.REF_JITTER1 (0.010),
.REF_JITTER2 (0.010)
)
plle2_i
(
.CLKFBOUT (pll_clkfbout),
.CLKOUT0 (freq_refclk),
.CLKOUT1 (mem_refclk),
.CLKOUT2 (sync_pulse), // always 1/16 of mem_ref_clk
.CLKOUT3 (pll_clk3),
.CLKOUT4 (auxout_clk_i),
.CLKOUT5 (ref_clk_mmcm),
.DO (),
.DRDY (),
.LOCKED (pll_locked_i),
.CLKFBIN (pll_clkfbout),
.CLKIN1 (mmcm_clk),
.CLKIN2 (),
.CLKINSEL (1'b1),
.DADDR (7'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DWE (1'b0),
.PWRDWN (1'b0),
.RST ( sys_rst_act_hi)
);
BUFH u_bufh_auxout_clk
(
.O (auxout_clk),
.I (auxout_clk_i)
);
BUFG u_bufg_clkdiv0
(
.O (clk_bufg),
.I (clk_pll_i)
);
BUFG u_bufg_refclk
(
.O(ref_clk_mmcm_bufg),
.I(ref_clk_mmcm)
);
localparam integer MMCM_VCO_MIN_FREQ = 600;
localparam integer MMCM_VCO_MAX_FREQ = 1200; // This is the maximum VCO frequency for a -1 part
localparam real MMCM_VCO_MIN_PERIOD = 1000000.0/MMCM_VCO_MAX_FREQ;
localparam real MMCM_VCO_MAX_PERIOD = 1000000.0/MMCM_VCO_MIN_FREQ;
localparam real MMCM_MULT_F_MID = CLKOUT3_PERIOD/(MMCM_VCO_MAX_PERIOD*0.75);
localparam real MMCM_EXPECTED_PERIOD = CLKOUT3_PERIOD / MMCM_MULT_F_MID;
localparam real MMCM_MULT_F = ((MMCM_EXPECTED_PERIOD > MMCM_VCO_MAX_PERIOD) ? MMCM_MULT_F_MID + 1.0 : MMCM_MULT_F_MID);
localparam real MMCM_VCO_FREQ = MMCM_MULT_F / (1 * CLKOUT3_PERIOD_NS);
localparam real MMCM_VCO_PERIOD = (CLKOUT3_PERIOD_NS * 1000) / MMCM_MULT_F;
//synthesis translate_off
initial begin
$display("############# MMCME2_ADV Parameters #############\n");
$display("MMCM_VCO_MIN_PERIOD = %7.3f", MMCM_VCO_MIN_PERIOD);
$display("MMCM_VCO_MAX_PERIOD = %7.3f", MMCM_VCO_MAX_PERIOD);
$display("MMCM_MULT_F_MID = %7.3f", MMCM_MULT_F_MID);
$display("MMCM_EXPECTED_PERIOD = %7.3f", MMCM_EXPECTED_PERIOD);
$display("MMCM_MULT_F = %7.3f", MMCM_MULT_F);
$display("CLKOUT3_PERIOD_NS = %7.3f", CLKOUT3_PERIOD_NS);
$display("MMCM_VCO_FREQ (MHz) = %7.3f", MMCM_VCO_FREQ*1000.0);
$display("MMCM_VCO_PERIOD = %7.3f", MMCM_VCO_PERIOD);
$display("#################################################\n");
end
//synthesis translate_on
generate
if (UI_EXTRA_CLOCKS == "TRUE") begin: gen_ui_extra_clocks
localparam MMCM_CLKOUT0_DIVIDE_CAL = (MMCM_CLKOUT0_EN == "TRUE") ? MMCM_CLKOUT0_DIVIDE : MMCM_MULT_F;
localparam MMCM_CLKOUT1_DIVIDE_CAL = (MMCM_CLKOUT1_EN == "TRUE") ? MMCM_CLKOUT1_DIVIDE : MMCM_MULT_F;
localparam MMCM_CLKOUT2_DIVIDE_CAL = (MMCM_CLKOUT2_EN == "TRUE") ? MMCM_CLKOUT2_DIVIDE : MMCM_MULT_F;
localparam MMCM_CLKOUT3_DIVIDE_CAL = (MMCM_CLKOUT3_EN == "TRUE") ? MMCM_CLKOUT3_DIVIDE : MMCM_MULT_F;
localparam MMCM_CLKOUT4_DIVIDE_CAL = (MMCM_CLKOUT4_EN == "TRUE") ? MMCM_CLKOUT4_DIVIDE : MMCM_MULT_F;
MMCME2_ADV
#(.BANDWIDTH ("HIGH"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("BUF_IN"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (MMCM_MULT_F),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (MMCM_CLKOUT0_DIVIDE_CAL),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (MMCM_CLKOUT1_DIVIDE_CAL),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (MMCM_CLKOUT2_DIVIDE_CAL),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKOUT3_DIVIDE (MMCM_CLKOUT3_DIVIDE_CAL),
.CLKOUT3_PHASE (0.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT3_USE_FINE_PS ("FALSE"),
.CLKOUT4_DIVIDE (MMCM_CLKOUT4_DIVIDE_CAL),
.CLKOUT4_PHASE (0.000),
.CLKOUT4_DUTY_CYCLE (0.500),
.CLKOUT4_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (CLKOUT3_PERIOD_NS),
.REF_JITTER1 (0.000))
mmcm_i
// Output clocks
(.CLKFBOUT (clk_pll_i),
.CLKFBOUTB (),
.CLKOUT0 (mmcm_clkout0),
.CLKOUT0B (),
.CLKOUT1 (mmcm_clkout1),
.CLKOUT1B (),
.CLKOUT2 (mmcm_clkout2),
.CLKOUT2B (),
.CLKOUT3 (mmcm_clkout3),
.CLKOUT3B (),
.CLKOUT4 (mmcm_clkout4),
.CLKOUT5 (),
.CLKOUT6 (),
// Input clock control
.CLKFBIN (clk_bufg), // From BUFH network
.CLKIN1 (pll_clk3), // From PLL
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (),
.DRDY (),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (MMCM_Locked_i),
.CLKINSTOPPED (),
.CLKFBSTOPPED (),
.PWRDWN (1'b0),
.RST (~pll_locked_i));
BUFG u_bufg_ui_addn_clk_0
(
.O (ui_addn_clk_0),
.I (mmcm_clkout0)
);
BUFG u_bufg_ui_addn_clk_1
(
.O (ui_addn_clk_1),
.I (mmcm_clkout1)
);
BUFG u_bufg_ui_addn_clk_2
(
.O (ui_addn_clk_2),
.I (mmcm_clkout2)
);
BUFG u_bufg_ui_addn_clk_3
(
.O (ui_addn_clk_3),
.I (mmcm_clkout3)
);
BUFG u_bufg_ui_addn_clk_4
(
.O (ui_addn_clk_4),
.I (mmcm_clkout4)
);
end else begin: gen_mmcm
MMCME2_ADV
#(.BANDWIDTH ("HIGH"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("BUF_IN"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (MMCM_MULT_F),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (MMCM_MULT_F),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (CLKOUT3_PERIOD_NS),
.REF_JITTER1 (0.000))
mmcm_i
// Output clocks
(.CLKFBOUT (clk_pll_i),
.CLKFBOUTB (),
.CLKOUT0 (),
.CLKOUT0B (),
.CLKOUT1 (),
.CLKOUT1B (),
.CLKOUT2 (),
.CLKOUT2B (),
.CLKOUT3 (),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
// Input clock control
.CLKFBIN (clk_bufg), // From BUFH network
.CLKIN1 (pll_clk3), // From PLL
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (),
.DRDY (),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (MMCM_Locked_i),
.CLKINSTOPPED (),
.CLKFBSTOPPED (),
.PWRDWN (1'b0),
.RST (~pll_locked_i));
end
endgenerate
//***************************************************************************
// RESET SYNCHRONIZATION DESCRIPTION:
// Various resets are generated to ensure that:
// 1. All resets are synchronously deasserted with respect to the clock
// domain they are interfacing to. There are several different clock
// domains - each one will receive a synchronized reset.
// 2. The reset deassertion order starts with deassertion of SYS_RST,
// followed by deassertion of resets for various parts of the design
// (see "RESET ORDER" below) based on the lock status of PLLE2s.
// RESET ORDER:
// 1. User deasserts SYS_RST
// 2. Reset PLLE2 and IDELAYCTRL
// 3. Wait for PLLE2 and IDELAYCTRL to lock
// 4. Release reset for all I/O primitives and internal logic
// OTHER NOTES:
// 1. Asynchronously assert reset. This way we can assert reset even if
// there is no clock (needed for things like 3-stating output buffers
// to prevent initial bus contention). Reset deassertion is synchronous.
//***************************************************************************
//*****************************************************************
// CLKDIV logic reset
//*****************************************************************
// Wait for PLLE2 and IDELAYCTRL to lock before releasing reset
// current O,25.0 unisim phaser_ref never locks. Need to find out why .
assign rst_tmp = sys_rst_act_hi | ~iodelay_ctrl_rdy |
~ref_dll_lock | ~MMCM_Locked_i;
always @(posedge clk_bufg or posedge rst_tmp) begin
if (rst_tmp) begin
rstdiv0_sync_r <= #TCQ {RST_DIV_SYNC_NUM-1{1'b1}};
rstdiv0_sync_r1 <= #TCQ 1'b1 ;
end else begin
rstdiv0_sync_r <= #TCQ rstdiv0_sync_r << 1;
rstdiv0_sync_r1 <= #TCQ rstdiv0_sync_r[RST_DIV_SYNC_NUM-2];
end
end
assign rstdiv0 = rstdiv0_sync_r1 ;
assign rst_tmp_phaser_ref = sys_rst_act_hi | ~pll_locked_i | ~iodelay_ctrl_rdy;
always @(posedge clk_bufg or posedge rst_tmp_phaser_ref)
if (rst_tmp_phaser_ref)
rst_phaser_ref_sync_r <= #TCQ {RST_DIV_SYNC_NUM{1'b1}};
else
rst_phaser_ref_sync_r <= #TCQ rst_phaser_ref_sync_r << 1;
assign rst_phaser_ref = rst_phaser_ref_sync_r[RST_DIV_SYNC_NUM-1];
endmodule
|
//*****************************************************************************
// (c) Copyright 2009-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Application : MIG
// \ \ Filename : traffic_gen_top.v
// / / Date Last Modified : $Date: 2011/06/02 08:37:25 $
// /___/ /\ Date Created : Fri Mar 26 2010
// \ \ / \
// \___\/\___\
//
//Device : Virtex-7
//Design Name : DDR/DDR2/DDR3/LPDDR
//Purpose : This Traffic Gen supports both nCK_PER_CLK x4 mode and nCK_PER_CLK x2 mode for
// 7series MC UI Interface. The user bus datawidth has a equation: 2*nCK_PER_CLK*DQ_WIDTH.
//
//Reference :
//Revision History : 11/17/2011 Adding CMD_GAP_DELAY to allow control of next command generation after current
// completion of burst command in user interface port.
// 1/4/2012 Added vio_percent_write in memc_traffic_gen module to let user specify percentage
// of write commands out of mix write/read commands. User can
// modify this file and bring the signals to top level to use it.
// The value is between 1(10 percent) through 10 (100 percent).
// The signal value is only used if vio_instr_mode_value == 4.
// 5/21/2012 Removed BL_WIDTH parameter and forced internally to 10.
//
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_0_traffic_gen_top #(
parameter TCQ = 100, // SIMULATION tCQ delay.
parameter SIMULATION = "FALSE",
parameter FAMILY = "VIRTEX7", // "VIRTEX6", "VIRTEX7"
parameter MEM_TYPE = "DDR3",
parameter TST_MEM_INSTR_MODE = "R_W_INSTR_MODE", // Spartan6 Available commands:
// "FIXED_INSTR_R_MODE", "FIXED_INSTR_W_MODE"
// "R_W_INSTR_MODE", "RP_WP_INSTR_MODE
// "R_RP_W_WP_INSTR_MODE", "R_RP_W_WP_REF_INSTR_MODE"
// *******************************
// Virtex 6 Available commands:
// "R_W_INSTR_MODE"
// "FIXED_INSTR_R_MODE" - Only Read commands will be generated.
// "FIXED_INSTR_W_MODE" -- Only Write commands will be generated.
// "FIXED_INSTR_R_EYE_MODE" Only Read commands will be generated
// with lower 10 bits address in sequential increment.
// This mode is for Read Eye measurement.
// parameter BL_WIDTH = 10, // Define User Interface Burst length width.
// // For a maximum 128 continuous back_to_back command, set this to 8.
parameter nCK_PER_CLK = 4, // Memory Clock ratio to fabric clock.
parameter NUM_DQ_PINS = 8, // Total number of memory dq pins in the design.
parameter MEM_BURST_LEN = 8, // MEMROY Burst Length
parameter MEM_COL_WIDTH = 10, // Memory component column width.
parameter DATA_WIDTH = NUM_DQ_PINS*2*nCK_PER_CLK, // User Interface Data Width
parameter ADDR_WIDTH = 29, // Command Address Bus width
parameter MASK_SIZE = DATA_WIDTH/8, //
parameter DATA_MODE = 4'b0010, // Default Data mode is set to Address as Data pattern.
// parameters define the address range
parameter BEGIN_ADDRESS = 32'h00000100,
parameter END_ADDRESS = 32'h000002ff,
parameter PRBS_EADDR_MASK_POS = 32'hfffffc00,
// debug parameters
parameter CMDS_GAP_DELAY = 6'd0, // CMDS_GAP_DELAY is used in memc_flow_vcontrol module to insert delay between
// each sucessive burst commands. The maximum delay is 32 clock cycles
// after the last command.
parameter SEL_VICTIM_LINE = NUM_DQ_PINS, // VICTIM LINE is one of the DQ pins is selected to be always asserted when
// DATA MODE is hammer pattern. No VICTIM_LINE will be selected if
// SEL_VICTIM_LINE = NUM_DQ_PINS.
parameter CMD_WDT = 'h3FF,
parameter WR_WDT = 'h1FFF,
parameter RD_WDT = 'hFF,
parameter EYE_TEST = "FALSE",
// S6 Only parameters
parameter PORT_MODE = "BI_MODE",
parameter DATA_PATTERN = "DGEN_ALL", // Default is to generate all data pattern circuits.
parameter CMD_PATTERN = "CGEN_ALL" // Default is to generate all commands pattern circuits.
)
(
input clk,
input rst,
input tg_only_rst,
input manual_clear_error,
input memc_init_done,
input memc_cmd_full,
output memc_cmd_en,
output [2:0] memc_cmd_instr,
output [5:0] memc_cmd_bl,
output [31:0] memc_cmd_addr,
output memc_wr_en,
output memc_wr_end,
output [DATA_WIDTH/8 - 1:0] memc_wr_mask,
output [DATA_WIDTH - 1:0] memc_wr_data,
input memc_wr_full,
output memc_rd_en,
input [DATA_WIDTH - 1:0] memc_rd_data,
input memc_rd_empty,
// interface to qdr interface
output qdr_wr_cmd_o,
output qdr_rd_cmd_o,
// Signal declarations that can be connected to vio module
input vio_pause_traffic, // Pause traffic on the fly.
input vio_modify_enable,
input [3:0] vio_data_mode_value,
input [2:0] vio_addr_mode_value,
input [3:0] vio_instr_mode_value,
input [1:0] vio_bl_mode_value,
input [9:0] vio_fixed_bl_value,
input [2:0] vio_fixed_instr_value, // Allows upper level control write only or read only
// on the fly.
// Set the vio_instr_mode_value to "0001" .
// User has control of the type of commands to be generated
// after memory has been filled with selected data pattern.
// vio_fixed_instr_value = 3'b000: Write command
// vio_fixed_instr_value = 3'b001: Read command
input vio_data_mask_gen, // data_mask generation is only supported
// when data mode = address as data .
//
input [31:0] fixed_addr_i,
// User Specific data pattern interface that used when vio_data_mode vale = 1.4.9.
input [31:0] fixed_data_i,
input [31:0] simple_data0,
input [31:0] simple_data1,
input [31:0] simple_data2,
input [31:0] simple_data3,
input [31:0] simple_data4,
input [31:0] simple_data5,
input [31:0] simple_data6,
input [31:0] simple_data7,
input wdt_en_i,
// BRAM interface.
// bram bus formats:
// Only SP6 has been tested.
input [38:0] bram_cmd_i, // {{bl}, {cmd}, {address[28:2]}}
input bram_valid_i,
output bram_rdy_o, //
// status feedback
output [DATA_WIDTH-1:0] cmp_data,
output cmp_data_valid,
output cmp_error,
output [47:0] wr_data_counts,
output [47:0] rd_data_counts,
output [NUM_DQ_PINS/8 - 1:0] dq_error_bytelane_cmp,
output error, // asserted whenever the read back data is not correct.
output [64 + (2*DATA_WIDTH - 1):0] error_status,
output [NUM_DQ_PINS/8 - 1:0] cumlative_dq_lane_error,
output reg cmd_wdt_err_o,
output reg wr_wdt_err_o,
output reg rd_wdt_err_o,
output mem_pattern_init_done
);
//p0 wire declarations
wire tg_run_traffic;
wire tg_data_mask_gen;
wire run_traffic;
wire [31:0] tg_start_addr;
wire [31:0] tg_end_addr;
wire [31:0] tg_cmd_seed;
wire [31:0] tg_data_seed;
wire tg_load_seed;
wire [2:0] tg_addr_mode;
wire [3:0] tg_instr_mode;
wire [1:0] tg_bl_mode;
wire [3:0] tg_data_mode;
wire tg_mode_load;
wire [9:0] tg_fixed_bl;
wire [2:0] tg_fixed_instr;
wire tg_addr_order;
wire [5:0] cmds_gap_delay_value;
wire tg_memc_wr_en;
wire [63:0] mem_tg_tstpoints;
wire [9:0] lcl_v_fixed_bl_value;
wire single_operation;
wire [3:0] tg_instr_mode_value;
wire [3:0] instr_mode_value;
reg tg_rst;
localparam ADDR_WIDTH_MASK = {{31-ADDR_WIDTH{1'b0}}, {ADDR_WIDTH-1{1'b1}}};
localparam ADDR_WIDTH_MASK_1 = {{30-ADDR_WIDTH{1'b0}}, {ADDR_WIDTH{1'b1}}};
localparam BEGIN_ADDRESS_MASK = ADDR_WIDTH_MASK & BEGIN_ADDRESS;
localparam END_ADDRESS_MASK = ADDR_WIDTH_MASK_1 & END_ADDRESS;
localparam SHIFT_COUNT = (31-ADDR_WIDTH) ;
localparam BEGIN_ADDRESS_INT = (BEGIN_ADDRESS_MASK >= END_ADDRESS_MASK) ? (BEGIN_ADDRESS >> SHIFT_COUNT) : BEGIN_ADDRESS_MASK ;
localparam END_ADDRESS_INT = (BEGIN_ADDRESS_MASK >= END_ADDRESS_MASK) ? (END_ADDRESS >> SHIFT_COUNT) : END_ADDRESS_MASK ;
localparam TG_INIT_DATA_MODE = (DATA_PATTERN == "DGEN_ADDR") ? 4'b0010 :
(DATA_PATTERN == "DGEN_HAMMER") ? 4'b0011 :
(DATA_PATTERN == "DGEN_WALKING1") ? 4'b0101 :
(DATA_PATTERN == "DGEN_WALKING0") ? 4'b0110 :
(DATA_PATTERN == "DGEN_PRBS") ? 4'b0111 :
DATA_MODE ;
assign single_operation = 1'b0; // Disable this for 13.3 release
// cmds_gap_delay_value is used in memc_flow_vcontrol module to insert delay between
// each sucessive burst commands. The maximum delay is 32 clock cycles after the last command.
function integer clogb2 (input integer size);
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction
localparam CMD_WDT_WIDTH = clogb2(CMD_WDT);
localparam RD_WDT_WIDTH = clogb2(RD_WDT);
localparam WR_WDT_WIDTH = clogb2(WR_WDT);
assign cmds_gap_delay_value = CMDS_GAP_DELAY;
localparam TG_FAMILY = ((FAMILY == "VIRTEX6") || (FAMILY == "VIRTEX7") || (FAMILY == "7SERIES")
|| (FAMILY == "KINTEX7") || (FAMILY == "ARTIX7") ) ? "VIRTEX6" : "SPARTAN6";
assign tg_memc_wr_en = (TG_FAMILY == "VIRTEX6") ?memc_cmd_en & ~memc_cmd_full : memc_wr_en ;
assign lcl_v_fixed_bl_value = (vio_data_mode_value == 4) ? 32:vio_fixed_bl_value;
assign tg_run_traffic = (run_traffic & ((vio_modify_enable == 1'b1) ? ~vio_pause_traffic : 1'b1)) ;
assign tg_data_mask_gen = (vio_modify_enable == 1'b1) ? vio_data_mask_gen : 1'b0 ;
assign instr_mode_value = (vio_modify_enable == 1'b1) ? vio_instr_mode_value : 4'b0010;
assign tg_instr_mode_value = (single_operation == 1'b1) ? 4'b0111: instr_mode_value;
reg [CMD_WDT_WIDTH-1 : 0] cmd_wdt;
reg [RD_WDT_WIDTH-1 : 0] rd_wdt;
reg [WR_WDT_WIDTH-1 : 0] wr_wdt;
// The following 'generate' statement activates the traffic generator for
// init_mem_pattern_ctr module instantiation for Port-0
mig_7series_v2_0_init_mem_pattern_ctr #
(
.TCQ (TCQ),
.DWIDTH (DATA_WIDTH),
.TST_MEM_INSTR_MODE (TST_MEM_INSTR_MODE),
.nCK_PER_CLK (nCK_PER_CLK),
.MEM_BURST_LEN (MEM_BURST_LEN),
.NUM_DQ_PINS (NUM_DQ_PINS),
.MEM_TYPE (MEM_TYPE),
.FAMILY (TG_FAMILY),
.BL_WIDTH (10),
.ADDR_WIDTH (ADDR_WIDTH),
.BEGIN_ADDRESS (BEGIN_ADDRESS_INT),
.END_ADDRESS (END_ADDRESS_INT),
.CMD_SEED_VALUE (32'h56456783),
.DATA_SEED_VALUE (32'h12345678),
.DATA_MODE (TG_INIT_DATA_MODE),
.PORT_MODE (PORT_MODE)
)
u_init_mem_pattern_ctr
(
.clk_i (clk),
.rst_i (tg_rst),
.memc_cmd_en_i (memc_cmd_en),
.memc_wr_en_i (tg_memc_wr_en),
.single_write_button (1'b0), // tie off these group of signals for 13.3
.single_read_button (1'b0),
.slow_write_read_button (1'b0),
.single_operation (1'b0),
.vio_modify_enable (vio_modify_enable),
.vio_instr_mode_value (tg_instr_mode_value),
.vio_data_mode_value (vio_data_mode_value),
.vio_addr_mode_value (vio_addr_mode_value),
.vio_bl_mode_value (vio_bl_mode_value), // always set to PRBS_BL mode
.vio_fixed_bl_value (lcl_v_fixed_bl_value), // always set to 64 in order to run PRBS data pattern
.vio_data_mask_gen (vio_data_mask_gen),
.vio_fixed_instr_value (vio_fixed_instr_value),
.memc_init_done_i (memc_init_done),
.cmp_error (error),
.run_traffic_o (run_traffic),
.start_addr_o (tg_start_addr),
.end_addr_o (tg_end_addr),
.cmd_seed_o (tg_cmd_seed),
.data_seed_o (tg_data_seed),
.load_seed_o (tg_load_seed),
.addr_mode_o (tg_addr_mode),
.instr_mode_o (tg_instr_mode),
.bl_mode_o (tg_bl_mode),
.data_mode_o (tg_data_mode),
.mode_load_o (tg_mode_load),
.fixed_bl_o (tg_fixed_bl),
.fixed_instr_o (tg_fixed_instr),
.mem_pattern_init_done_o (mem_pattern_init_done)
);
// traffic generator instantiation for Port-0
mig_7series_v2_0_memc_traffic_gen #
(
.TCQ (TCQ),
.MEM_BURST_LEN (MEM_BURST_LEN),
.MEM_COL_WIDTH (MEM_COL_WIDTH),
.NUM_DQ_PINS (NUM_DQ_PINS),
.nCK_PER_CLK (nCK_PER_CLK),
.PORT_MODE (PORT_MODE),
.DWIDTH (DATA_WIDTH),
.FAMILY (TG_FAMILY),
.MEM_TYPE (MEM_TYPE),
.SIMULATION (SIMULATION),
.DATA_PATTERN (DATA_PATTERN),
.CMD_PATTERN (CMD_PATTERN ),
.ADDR_WIDTH (ADDR_WIDTH),
.BL_WIDTH (10),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.PRBS_SADDR_MASK_POS (BEGIN_ADDRESS_INT),
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS),
.PRBS_SADDR (BEGIN_ADDRESS_INT),
.PRBS_EADDR (END_ADDRESS_INT),
.EYE_TEST (EYE_TEST)
)
u_memc_traffic_gen
(
.clk_i (clk),
.rst_i (tg_rst),
.run_traffic_i (tg_run_traffic),
.manual_clear_error (manual_clear_error),
.cmds_gap_delay_value (cmds_gap_delay_value),
.vio_instr_mode_value (tg_instr_mode_value),
.vio_percent_write ('b0), // bring this to top if want to specify percentage of write commands
// instr_mode_i has to be == 4 if want to use this command pattern
// runtime parameter
.mem_pattern_init_done_i (mem_pattern_init_done),
.single_operation (1'b0),
.start_addr_i (tg_start_addr),
.end_addr_i (tg_end_addr),
.cmd_seed_i (tg_cmd_seed),
.data_seed_i (tg_data_seed),
.load_seed_i (tg_load_seed),
.addr_mode_i (tg_addr_mode),
.instr_mode_i (tg_instr_mode),
.bl_mode_i (tg_bl_mode),
.data_mode_i (tg_data_mode),
.mode_load_i (tg_mode_load),
.wr_data_mask_gen_i (tg_data_mask_gen),
// fixed pattern inputs interface
.fixed_bl_i (tg_fixed_bl),
.fixed_instr_i (tg_fixed_instr),
.fixed_addr_i (fixed_addr_i),
.fixed_data_i (fixed_data_i),
// BRAM interface.
.bram_cmd_i (bram_cmd_i),
// .bram_addr_i (bram_addr_i ),
// .bram_instr_i ( bram_instr_i),
.bram_valid_i (bram_valid_i),
.bram_rdy_o (bram_rdy_o),
// MCB INTERFACE
.memc_cmd_en_o (memc_cmd_en),
.memc_cmd_instr_o (memc_cmd_instr),
.memc_cmd_bl_o (memc_cmd_bl),
.memc_cmd_addr_o (memc_cmd_addr),
.memc_cmd_full_i (memc_cmd_full),
.memc_wr_en_o (memc_wr_en),
.memc_wr_data_end_o (memc_wr_end),
.memc_wr_mask_o (memc_wr_mask),
.memc_wr_data_o (memc_wr_data),
.memc_wr_full_i (memc_wr_full),
.memc_rd_en_o (memc_rd_en),
.memc_rd_data_i (memc_rd_data),
.memc_rd_empty_i (memc_rd_empty),
.qdr_wr_cmd_o (qdr_wr_cmd_o),
.qdr_rd_cmd_o (qdr_rd_cmd_o),
// status feedback
.counts_rst (tg_rst),
.wr_data_counts (wr_data_counts),
.rd_data_counts (rd_data_counts),
.error (error), // asserted whenever the read back data is not correct.
.error_status (error_status), // TBD how signals mapped
.cmp_data (cmp_data),
.cmp_data_valid (cmp_data_valid),
.cmp_error (cmp_error),
.mem_rd_data (),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.dq_error_bytelane_cmp (dq_error_bytelane_cmp),
.cumlative_dq_lane_error (cumlative_dq_lane_error),
.cumlative_dq_r0_bit_error (),
.cumlative_dq_f0_bit_error (),
.cumlative_dq_r1_bit_error (),
.cumlative_dq_f1_bit_error (),
.dq_r0_bit_error_r (),
.dq_f0_bit_error_r (),
.dq_r1_bit_error_r (),
.dq_f1_bit_error_r (),
.dq_r0_read_bit (),
.dq_f0_read_bit (),
.dq_r1_read_bit (),
.dq_f1_read_bit (),
.dq_r0_expect_bit (),
.dq_f0_expect_bit (),
.dq_r1_expect_bit (),
.dq_f1_expect_bit (),
.error_addr ()
);
reg [8:0] wr_cmd_cnt;
reg [8:0] dat_cmd_cnt;
reg rst_remem;
reg [2:0] app_cmd1;
reg [2:0] app_cmd2;
reg [2:0] app_cmd3;
reg [2:0] app_cmd4;
reg [8:0] rst_cntr;
always @(posedge clk) begin
if (rst) begin
rst_remem <= 1'b0;
end else if (tg_only_rst) begin
rst_remem <= 1'b1;
end else if (rst_cntr == 9'h0) begin
rst_remem <= 1'b0;
end
end
always @(posedge clk) begin
if (rst) begin
tg_rst <= 1'b1;
end else begin
tg_rst <= (rst_cntr != 9'h1ff);
end
end
always @ (posedge clk)
begin
if (rst)
rst_cntr <= 9'h1ff;
else if (rst_remem & (wr_cmd_cnt==dat_cmd_cnt) & (app_cmd3==3'h1) & (app_cmd4==3'h0))
rst_cntr <= 9'h0;
else if (rst_cntr != 9'h1ff)
rst_cntr <= rst_cntr + 1'b1;
end
always @(posedge clk) begin
if (rst | tg_rst) begin
wr_cmd_cnt <= 1'b0;
end else if (memc_cmd_en & (!memc_cmd_full)& (memc_cmd_instr == 3'h0)) begin
wr_cmd_cnt <= wr_cmd_cnt + 1'b1;
end
end
always @(posedge clk) begin
if (rst| tg_rst) begin
dat_cmd_cnt <= 1'b0;
end else if (memc_wr_en & (!memc_wr_full)) begin
dat_cmd_cnt <= dat_cmd_cnt + 1'b1;
end
end
always @(posedge clk) begin
if (rst| tg_rst) begin
app_cmd1 <= 'b0;
app_cmd2 <= 'b0;
app_cmd3 <= 'b0;
app_cmd4 <= 'b0;
end else if (memc_cmd_en & (!memc_cmd_full)) begin
app_cmd1 <= memc_cmd_instr;
app_cmd2 <= app_cmd1;
app_cmd3 <= app_cmd2;
app_cmd4 <= app_cmd3;
end
end
always @(posedge clk) begin
if (rst| tg_rst) begin
cmd_wdt <= 1'b0;
end else if (memc_init_done & (cmd_wdt!=CMD_WDT) & (memc_cmd_full | (!memc_cmd_en)) & wdt_en_i) begin
// init_calib_done !app_rdy app_en
cmd_wdt <= cmd_wdt + 1'b1;
// end else if (memc_init_done & (cmd_wdt!=CMD_WDT) & (!memc_cmd_full) & memc_cmd_en & wdt_en_w) begin
end else if ((!memc_cmd_full) & memc_cmd_en) begin
// init_calib_done !app_rdy app_en
cmd_wdt <= 'b0;
end
end
always @(posedge clk) begin
if (rst| tg_rst) begin
rd_wdt <= 1'b0;
end else if (mem_pattern_init_done & (rd_wdt != RD_WDT) & (memc_rd_empty) & wdt_en_i) begin
// !app_rd_data_valid
rd_wdt <= rd_wdt + 1'b1;
end else if (!memc_rd_empty) begin
// !app_rd_data_valid
rd_wdt <= 'b0;
end
end
always @(posedge clk) begin
if (rst| tg_rst) begin
wr_wdt <= 1'b0;
end else if (mem_pattern_init_done & (wr_wdt != WR_WDT) & (!memc_wr_en) & wdt_en_i) begin
// app_wdf_wren
wr_wdt <= wr_wdt + 1'b1;
end else if (memc_wr_en) begin
// app_wdf_wren
wr_wdt <= 'b0;
end
end
always @(posedge clk) begin
if (rst| tg_rst) begin
cmd_wdt_err_o <= 'b0;
rd_wdt_err_o <= 'b0;
wr_wdt_err_o <= 'b0;
end else begin
cmd_wdt_err_o <= cmd_wdt == CMD_WDT;
rd_wdt_err_o <= rd_wdt == RD_WDT;
wr_wdt_err_o <= wr_wdt == WR_WDT;
end
end
//synthesis translate_off
initial
begin
@ (posedge cmd_wdt_err_o);
$display ("ERROR: COMMAND Watch Dog Timer Expired");
repeat (20) @ (posedge clk);
$finish;
end
initial
begin
@ (posedge rd_wdt_err_o);
$display ("ERROR: READ Watch Dog Timer Expired");
repeat (20) @ (posedge clk);
$finish;
end
initial
begin
@ (posedge wr_wdt_err_o)
$display ("ERROR: WRITE Watch Dog Timer Expired");
repeat (20) @ (posedge clk);
$finish;
end
initial
begin
@ (posedge error)
repeat (20) @ (posedge clk);
$finish;
end
//synthesis translate_on
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ctu_clsp_synch_jlcl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//
// Cluster Name: CTU
// Unit Name: ctu_clsp_dramif
//
//-----------------------------------------------------------------------------
`include "sys.h"
`include "ctu.h"
module ctu_clsp_synch_jlcl(/*AUTOARG*/
// Outputs
update_clkctrl_reg_cl, stop_id_vld_cl, sctag3_ctu_tr_cl,
sctag2_ctu_tr_cl, sctag1_ctu_tr_cl, sctag0_ctu_tr_cl,
rstctrl_idle_cl, rstctrl_enclk_cl, rstctrl_disclk_cl,
rd_clkctrl_reg_cl, jbi_ctu_tr_cl, iob_ctu_tr_cl, iob_ctu_l2_tr_cl,
dram_a_grst_cl, dram13_ctu_tr_cl, dram02_ctu_tr_cl, de_grst_cl,
de_dbginit_cl, dbgtrig_dly_cnt_val_cl, ctu_sparc7_cmp_cken_cg,
ctu_sparc6_cmp_cken_cg, ctu_sparc5_cmp_cken_cg,
ctu_sparc4_cmp_cken_cg, ctu_sparc3_cmp_cken_cg,
ctu_sparc2_cmp_cken_cg, ctu_sparc1_cmp_cken_cg,
ctu_sparc0_cmp_cken_cg, ctu_sctag3_cmp_cken_cg,
ctu_sctag2_cmp_cken_cg, ctu_sctag1_cmp_cken_cg,
ctu_sctag0_cmp_cken_cg, ctu_scdata3_cmp_cken_cg,
ctu_scdata2_cmp_cken_cg, ctu_scdata1_cmp_cken_cg,
ctu_scdata0_cmp_cken_cg, ctu_misc_cken_pre_jl, ctu_jbusr_cken_pre_jl,
ctu_jbusl_cken_pre_jl, ctu_jbi_cmp_cken_cg, ctu_jbi_cken_pre_jl,
ctu_iob_cmp_cken_cg, ctu_iob_cken_pre_jl, ctu_io_j_err_jl,
ctu_fpu_cmp_cken_cg, ctu_efc_cken_pre_jl, ctu_dram13_cmp_cken_cg,
ctu_dram13_cken_pre_jl, ctu_dram02_cmp_cken_cg,
ctu_dram02_cken_pre_jl, ctu_dbg_cken_pre_jl, ctu_ccx_cmp_cken_cg,
creg_cken_vld_cl, clsp_ctrl_srarm_pre_jl, clkctrl_dn_jl, a_grst_cl,
a_dbginit_cl, start_clk_cl, update_shadow_cl,
// Inputs
stop_id_vld_jl, sctag3_ctu_tr, sctag2_ctu_tr, sctag1_ctu_tr,
sctag0_ctu_tr, rstctrl_idle_jl, rstctrl_enclk_jl, rstctrl_disclk_jl,
jbus_tx_sync, jbi_ctu_tr_jl, iob_ctu_tr_jl, iob_ctu_l2_tr_jl,
dram_a_grst_jl, dram13_ctu_tr_jl, dram02_ctu_tr_jl, de_grst_jl,
de_dbginit_jl, dbgtrig_dly_cnt_val, ctu_sparc7_cken_cl,
ctu_sparc6_cken_cl, ctu_sparc5_cken_cl, ctu_sparc4_cken_cl,
ctu_sparc3_cken_cl, ctu_sparc2_cken_cl, ctu_sparc1_cken_cl,
ctu_sparc0_cken_cl, ctu_sctag3_cken_cl, ctu_sctag2_cken_cl,
ctu_sctag1_cken_cl, ctu_sctag0_cken_cl, ctu_scdata3_cken_cl,
ctu_scdata2_cken_cl, ctu_scdata1_cken_cl, ctu_scdata0_cken_cl,
ctu_jbi_cken_cl, ctu_iob_cken_cl, ctu_io_j_err_cl, ctu_fpu_cken_cl,
ctu_efc_cken_cl, ctu_dram13_cken_cl, ctu_dram02_cken_cl,
ctu_ccx_cken_cl, creg_cken_vld_jl, cmp_clk, clsp_ctrl_srarm_cl,
clkctrl_dn_cl, a_grst_jl, a_dbginit_jl, jbus_rx_sync, io_pwron_rst_l,
update_shadow_jl, ctu_jbus_rx_sync_cl, ctu_jbusr_cken_cl,
ctu_jbusl_cken_cl, ctu_misc_cken_cl, ctu_dbg_cken_cl,
update_clkctrl_reg_jl, rd_clkctrl_reg_jl, start_clk_early_jl,
jtag_clsp_force_cken_cmp, testmode_l
);
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input a_dbginit_jl; // To u_a_dbginit of dffrle_ns.v
input a_grst_jl; // To u_grst_dis of dffrle_ns.v
input clkctrl_dn_cl; // To u_clkctrl_dn_jl of dffrle_ns.v
input clsp_ctrl_srarm_cl; // To u_clsp_ctrl_srarm_pre_jl of dffrle_ns.v
input cmp_clk; // To u_ctu_sparc0_cmp_cken_cl of ctu_synch_cl_cg.v, ...
input creg_cken_vld_jl; // To u_creg_cken_vld_cl of dffrle_ns.v
input ctu_ccx_cken_cl; // To u_ctu_ccx_cmp_cken_cl of ctu_synch_cl_cg.v
input ctu_dram02_cken_cl; // To u_ctu_dram02_cmp_cken_cl of ctu_synch_cl_cg.v, ...
input ctu_dram13_cken_cl; // To u_ctu_dram13_cmp_cken_cl of ctu_synch_cl_cg.v, ...
input ctu_efc_cken_cl; // To u_ctu_efc_cken_jl of dffrle_ns.v
input ctu_fpu_cken_cl; // To u_ctu_fpu_cmp_cken_cl of ctu_synch_cl_cg.v
input ctu_io_j_err_cl; // To u_ctu_io_j_err_jl of dffrle_ns.v
input ctu_iob_cken_cl; // To u_ctu_iob_cmp_cken_cl of ctu_synch_cl_cg.v, ...
input ctu_jbi_cken_cl; // To u_ctu_jbi_cmp_cken_cl of ctu_synch_cl_cg.v, ...
input ctu_scdata0_cken_cl; // To u_ctu_scdata0_cmp_cken_cl of ctu_synch_cl_cg.v
input ctu_scdata1_cken_cl; // To u_ctu_scdata1_cmp_cken_cl of ctu_synch_cl_cg.v
input ctu_scdata2_cken_cl; // To u_ctu_scdata2_cmp_cken_cl of ctu_synch_cl_cg.v
input ctu_scdata3_cken_cl; // To u_ctu_scdata3_cmp_cken_cl of ctu_synch_cl_cg.v
input ctu_sctag0_cken_cl; // To u_ctu_sctag0_cmp_cken_cl of ctu_synch_cl_cg.v
input ctu_sctag1_cken_cl; // To u_ctu_sctag1_cmp_cken_cl of ctu_synch_cl_cg.v
input ctu_sctag2_cken_cl; // To u_ctu_sctag2_cmp_cken_cl of ctu_synch_cl_cg.v
input ctu_sctag3_cken_cl; // To u_ctu_sctag3_cmp_cken_cl of ctu_synch_cl_cg.v
input ctu_sparc0_cken_cl; // To u_ctu_sparc0_cmp_cken_cl of ctu_synch_cl_cg.v
input ctu_sparc1_cken_cl; // To u_ctu_sparc1_cmp_cken_cl of ctu_synch_cl_cg.v
input ctu_sparc2_cken_cl; // To u_ctu_sparc2_cmp_cken_cl of ctu_synch_cl_cg.v
input ctu_sparc3_cken_cl; // To u_ctu_sparc3_cmp_cken_cl of ctu_synch_cl_cg.v
input ctu_sparc4_cken_cl; // To u_ctu_sparc4_cmp_cken_cl of ctu_synch_cl_cg.v
input ctu_sparc5_cken_cl; // To u_ctu_sparc5_cmp_cken_cl of ctu_synch_cl_cg.v
input ctu_sparc6_cken_cl; // To u_ctu_sparc6_cmp_cken_cl of ctu_synch_cl_cg.v
input ctu_sparc7_cken_cl; // To u_ctu_sparc7_cmp_cken_cl of ctu_synch_cl_cg.v
input [4:0] dbgtrig_dly_cnt_val; // To u_dbgtrig_dly_cnt_val of dffrle_ns.v
input de_dbginit_jl; // To u_de_dbginit of dffrle_ns.v
input de_grst_jl; // To u_grst_en of dffrle_ns.v
input dram02_ctu_tr_jl; // To u_dram02_ctu_tr_cl of dffrle_ns.v
input dram13_ctu_tr_jl; // To u_dram13_ctu_tr_cl of dffrle_ns.v
input dram_a_grst_jl; // To u_dram_grst_dis of dffrle_ns.v
input iob_ctu_l2_tr_jl; // To u_iob_ctu_l2_tr_cl of dffrle_ns.v
input iob_ctu_tr_jl; // To u_iob_ctu_tr_cl of dffrle_ns.v
input jbi_ctu_tr_jl; // To u_jbi_ctu_tr_cl of dffrle_ns.v
input jbus_tx_sync; // To u_clkctrl_dn_jl of dffrle_ns.v, ...
input rstctrl_disclk_jl; // To u_rstctrl_disclk_cl of dffrle_ns.v
input rstctrl_enclk_jl; // To u_rstctrl_enclk_cl of dffrle_ns.v
input rstctrl_idle_jl; // To u_rstctrl_idle_cl of dffrle_ns.v
input sctag0_ctu_tr; // To u_sctag0_ctu_tr_ff of dffrl_ns.v
input sctag1_ctu_tr; // To u_sctag1_ctu_tr_ff of dffrl_ns.v
input sctag2_ctu_tr; // To u_sctag2_ctu_tr_ff of dffrl_ns.v
input sctag3_ctu_tr; // To u_sctag3_ctu_tr_ff of dffrl_ns.v
input stop_id_vld_jl; // To u_stop_id_vld_cl of dffrle_ns.v
// End of automatics
input jbus_rx_sync; // To u_ctu_sparc0_cmp_cken_cl of ctu_synch_cl_cg.v, ...
input io_pwron_rst_l;
input update_shadow_jl; // To u_start_clk_cl of ctu_synch_jl_cl.v
input ctu_jbus_rx_sync_cl;
input ctu_jbusr_cken_cl;
input ctu_jbusl_cken_cl;
input ctu_misc_cken_cl;
input ctu_dbg_cken_cl;
input update_clkctrl_reg_jl;
input rd_clkctrl_reg_jl;
input start_clk_early_jl;
input jtag_clsp_force_cken_cmp;
input testmode_l;
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output a_dbginit_cl; // From u_a_dbginit of dffrle_ns.v
output a_grst_cl; // From u_grst_dis of dffrle_ns.v
output clkctrl_dn_jl; // From u_clkctrl_dn_jl of dffrle_ns.v
output clsp_ctrl_srarm_pre_jl; // From u_clsp_ctrl_srarm_pre_jl of dffrle_ns.v
output creg_cken_vld_cl; // From u_creg_cken_vld_cl of dffrle_ns.v
output ctu_ccx_cmp_cken_cg; // From u_ctu_ccx_cmp_cken_cl of ctu_synch_cl_cg.v
output ctu_dbg_cken_pre_jl; // From u_ctu_dbg_cken_jl of dffsl_async_ns.v
output ctu_dram02_cken_pre_jl; // From u_ctu_dram02_cken_jl of dffrle_ns.v
output ctu_dram02_cmp_cken_cg; // From u_ctu_dram02_cmp_cken_cl of ctu_synch_cl_cg.v
output ctu_dram13_cken_pre_jl; // From u_ctu_dram13_cken_jl of dffrle_ns.v
output ctu_dram13_cmp_cken_cg; // From u_ctu_dram13_cmp_cken_cl of ctu_synch_cl_cg.v
output ctu_efc_cken_pre_jl; // From u_ctu_efc_cken_jl of dffrle_ns.v
output ctu_fpu_cmp_cken_cg; // From u_ctu_fpu_cmp_cken_cl of ctu_synch_cl_cg.v
output ctu_io_j_err_jl; // From u_ctu_io_j_err_jl of dffrle_ns.v
output ctu_iob_cken_pre_jl; // From u_ctu_iob_cken_jl of dffrle_ns.v
output ctu_iob_cmp_cken_cg; // From u_ctu_iob_cmp_cken_cl of ctu_synch_cl_cg.v
output ctu_jbi_cken_pre_jl; // From u_ctu_jbi_cken_jl of dffrle_ns.v
output ctu_jbi_cmp_cken_cg; // From u_ctu_jbi_cmp_cken_cl of ctu_synch_cl_cg.v
output ctu_jbusl_cken_pre_jl; // From u_ctu_jbusl_cken_jl of dffsl_async_ns.v
output ctu_jbusr_cken_pre_jl; // From u_ctu_jbusr_cken_jl of dffsl_async_ns.v
output ctu_misc_cken_pre_jl; // From u_ctu_misc_cken_jl of dffsl_async_ns.v
output ctu_scdata0_cmp_cken_cg;// From u_ctu_scdata0_cmp_cken_cl of ctu_synch_cl_cg.v
output ctu_scdata1_cmp_cken_cg;// From u_ctu_scdata1_cmp_cken_cl of ctu_synch_cl_cg.v
output ctu_scdata2_cmp_cken_cg;// From u_ctu_scdata2_cmp_cken_cl of ctu_synch_cl_cg.v
output ctu_scdata3_cmp_cken_cg;// From u_ctu_scdata3_cmp_cken_cl of ctu_synch_cl_cg.v
output ctu_sctag0_cmp_cken_cg; // From u_ctu_sctag0_cmp_cken_cl of ctu_synch_cl_cg.v
output ctu_sctag1_cmp_cken_cg; // From u_ctu_sctag1_cmp_cken_cl of ctu_synch_cl_cg.v
output ctu_sctag2_cmp_cken_cg; // From u_ctu_sctag2_cmp_cken_cl of ctu_synch_cl_cg.v
output ctu_sctag3_cmp_cken_cg; // From u_ctu_sctag3_cmp_cken_cl of ctu_synch_cl_cg.v
output ctu_sparc0_cmp_cken_cg; // From u_ctu_sparc0_cmp_cken_cl of ctu_synch_cl_cg.v
output ctu_sparc1_cmp_cken_cg; // From u_ctu_sparc1_cmp_cken_cl of ctu_synch_cl_cg.v
output ctu_sparc2_cmp_cken_cg; // From u_ctu_sparc2_cmp_cken_cl of ctu_synch_cl_cg.v
output ctu_sparc3_cmp_cken_cg; // From u_ctu_sparc3_cmp_cken_cl of ctu_synch_cl_cg.v
output ctu_sparc4_cmp_cken_cg; // From u_ctu_sparc4_cmp_cken_cl of ctu_synch_cl_cg.v
output ctu_sparc5_cmp_cken_cg; // From u_ctu_sparc5_cmp_cken_cl of ctu_synch_cl_cg.v
output ctu_sparc6_cmp_cken_cg; // From u_ctu_sparc6_cmp_cken_cl of ctu_synch_cl_cg.v
output ctu_sparc7_cmp_cken_cg; // From u_ctu_sparc7_cmp_cken_cl of ctu_synch_cl_cg.v
output [4:0] dbgtrig_dly_cnt_val_cl; // From u_dbgtrig_dly_cnt_val of dffrle_ns.v
output de_dbginit_cl; // From u_de_dbginit of dffrle_ns.v
output de_grst_cl; // From u_grst_en of dffrle_ns.v
output dram02_ctu_tr_cl; // From u_dram02_ctu_tr_cl of dffrle_ns.v
output dram13_ctu_tr_cl; // From u_dram13_ctu_tr_cl of dffrle_ns.v
output dram_a_grst_cl; // From u_dram_grst_dis of dffrle_ns.v
output iob_ctu_l2_tr_cl; // From u_iob_ctu_l2_tr_cl of dffrle_ns.v
output iob_ctu_tr_cl; // From u_iob_ctu_tr_cl of dffrle_ns.v
output jbi_ctu_tr_cl; // From u_jbi_ctu_tr_cl of dffrle_ns.v
output rd_clkctrl_reg_cl; // From u_rd_clkctrl_reg_jl of dffrl_async_ns.v
output rstctrl_disclk_cl; // From u_rstctrl_disclk_cl of dffrle_ns.v
output rstctrl_enclk_cl; // From u_rstctrl_enclk_cl of dffrle_ns.v
output rstctrl_idle_cl; // From u_rstctrl_idle_cl of dffrle_ns.v
output sctag0_ctu_tr_cl; // From u_sctag0_ctu_tr_cl of dffrl_ns.v
output sctag1_ctu_tr_cl; // From u_sctag1_ctu_tr_cl of dffrl_ns.v
output sctag2_ctu_tr_cl; // From u_sctag2_ctu_tr_cl of dffrl_ns.v
output sctag3_ctu_tr_cl; // From u_sctag3_ctu_tr_cl of dffrl_ns.v
output stop_id_vld_cl; // From u_stop_id_vld_cl of dffrle_ns.v
output update_clkctrl_reg_cl; // From u_update_clkctrl_reg_cl of dffrl_async_ns.v
// End of automatics
output start_clk_cl; // From u_start_clk_cl of ctu_synch_jl_cl.v
output update_shadow_cl; // To u_start_clk_cl of ctu_synch_jl_cl.v
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire sctag0_ctu_tr_ff; // From u_sctag0_ctu_tr_ff of dffrl_ns.v
wire sctag1_ctu_tr_ff; // From u_sctag1_ctu_tr_ff of dffrl_ns.v
wire sctag2_ctu_tr_ff; // From u_sctag2_ctu_tr_ff of dffrl_ns.v
wire sctag3_ctu_tr_ff; // From u_sctag3_ctu_tr_ff of dffrl_ns.v
// End of automatics
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
wire ctu_jbusl_cken_jl_nxt;
wire ctu_jbusr_cken_jl_nxt;
wire ctu_jbusl_cken_pre_jl;
wire ctu_jbusr_cken_pre_jl;
wire update_clkctrl_reg_jl_nxt;
wire rd_clkctrl_reg_jl_nxt;
wire ctu_misc_cken_jl_nxt;
wire ctu_dbg_cken_jl_nxt;
wire start_clk_sync_nxt;
wire start_clk_tmp_nxt;
wire start_clk_tmp;
wire start_clk_dly_nxt;
wire start_clk_dly1;
wire start_clk_dly2;
wire start_clk_dly3;
wire start_clk_dly4;
wire start_clk_dly5;
wire start_clk_dly6;
wire start_clk_dly7;
wire update_shadow_cl_nxt;
wire force_cken ;
assign force_cken = jtag_clsp_force_cken_cmp | ~testmode_l;
// transimit sync pulses are generated ahead of rx
assign start_clk_tmp_nxt = ctu_jbus_rx_sync_cl? 1'b1: start_clk_tmp;
dffrl_async_ns u_start_clk_tmp(
.din (start_clk_tmp_nxt),
.clk (cmp_clk),
.rst_l(io_pwron_rst_l),
.q (start_clk_tmp));
assign start_clk_dly_nxt = ctu_jbus_rx_sync_cl & start_clk_tmp ? 1'b1: start_clk_dly1;
dffrl_async_ns u_start_clk_dly1(
.din (start_clk_dly_nxt),
.clk (cmp_clk),
.rst_l(io_pwron_rst_l),
.q (start_clk_dly1));
dffrl_async_ns u_start_clk_dly2(
.din (start_clk_dly1),
.clk (cmp_clk),
.rst_l(io_pwron_rst_l),
.q (start_clk_dly2));
dffrl_async_ns u_start_clk_dly3(
.din (start_clk_dly2),
.clk (cmp_clk),
.rst_l(io_pwron_rst_l),
.q (start_clk_dly3));
dffrl_async_ns u_start_clk_dly4(
.din (start_clk_dly3),
.clk (cmp_clk),
.rst_l(io_pwron_rst_l),
.q (start_clk_dly4));
dffrl_async_ns u_start_clk_dly5(
.din (start_clk_dly4),
.clk (cmp_clk),
.rst_l(io_pwron_rst_l),
.q (start_clk_dly5));
dffrl_async_ns u_start_clk_dly6(
.din (start_clk_dly5),
.clk (cmp_clk),
.rst_l(io_pwron_rst_l),
.q (start_clk_dly6));
dffrl_async_ns u_start_clk_dly7(
.din (start_clk_dly6),
.clk (cmp_clk),
.rst_l(io_pwron_rst_l),
.q (start_clk_dly7));
// dffrl_async_ns u_start_clk_cl(
// .din (start_clk_dly7),
// .clk (cmp_clk),
// .rst_l(io_pwron_rst_l),
// .q (start_clk_cl));
// de-asset start_clk_cl during warm_rst
assign start_clk_sync_nxt = (jbus_rx_sync ? start_clk_early_jl : start_clk_cl) & start_clk_dly7;
dffrl_async_ns u_start_clk_cl(
.din (start_clk_sync_nxt),
.clk (cmp_clk),
.rst_l(io_pwron_rst_l),
.q (start_clk_cl));
assign update_shadow_cl_nxt = (jbus_rx_sync ? update_shadow_jl : update_shadow_cl) & start_clk_cl;
dffrl_async_ns u_update_shadow_cl(
.din (update_shadow_cl_nxt),
.clk (cmp_clk),
.rst_l(io_pwron_rst_l),
.q (update_shadow_cl));
/* ctu_synch_cl_cg AUTO_TEMPLATE (
.presyncdata (ctu_sparc@_cken_cl),
.syncdata (ctu_sparc@_cmp_cken_cg),
.arst_l(io_pwron_rst_l),
);
*/
ctu_synch_cl_cg u_ctu_sparc0_cmp_cken_cl(
.start_clk_cl(start_clk_cl),
/*AUTOINST*/
// Outputs
.syncdata(ctu_sparc0_cmp_cken_cg), // Templated
// Inputs
.cmp_clk(cmp_clk),
.arst_l(io_pwron_rst_l), // Templated
.force_cken(force_cken),
.presyncdata(ctu_sparc0_cken_cl)); // Templated
ctu_synch_cl_cg u_ctu_sparc1_cmp_cken_cl(
.start_clk_cl(start_clk_cl),
/*AUTOINST*/
// Outputs
.syncdata(ctu_sparc1_cmp_cken_cg), // Templated
// Inputs
.cmp_clk(cmp_clk),
.arst_l(io_pwron_rst_l), // Templated
.force_cken(force_cken),
.presyncdata(ctu_sparc1_cken_cl)); // Templated
ctu_synch_cl_cg u_ctu_sparc2_cmp_cken_cl(
.start_clk_cl(start_clk_cl),
/*AUTOINST*/
// Outputs
.syncdata(ctu_sparc2_cmp_cken_cg), // Templated
// Inputs
.cmp_clk(cmp_clk),
.arst_l(io_pwron_rst_l), // Templated
.force_cken(force_cken),
.presyncdata(ctu_sparc2_cken_cl)); // Templated
ctu_synch_cl_cg u_ctu_sparc3_cmp_cken_cl(
.start_clk_cl(start_clk_cl),
/*AUTOINST*/
// Outputs
.syncdata(ctu_sparc3_cmp_cken_cg), // Templated
// Inputs
.cmp_clk(cmp_clk),
.arst_l(io_pwron_rst_l), // Templated
.force_cken(force_cken),
.presyncdata(ctu_sparc3_cken_cl)); // Templated
ctu_synch_cl_cg u_ctu_sparc4_cmp_cken_cl(
.start_clk_cl(start_clk_cl),
/*AUTOINST*/
// Outputs
.syncdata(ctu_sparc4_cmp_cken_cg), // Templated
// Inputs
.cmp_clk(cmp_clk),
.arst_l(io_pwron_rst_l), // Templated
.force_cken(force_cken),
.presyncdata(ctu_sparc4_cken_cl)); // Templated
ctu_synch_cl_cg u_ctu_sparc5_cmp_cken_cl(
.start_clk_cl(start_clk_cl),
/*AUTOINST*/
// Outputs
.syncdata(ctu_sparc5_cmp_cken_cg), // Templated
// Inputs
.cmp_clk(cmp_clk),
.arst_l(io_pwron_rst_l), // Templated
.force_cken(force_cken),
.presyncdata(ctu_sparc5_cken_cl)); // Templated
ctu_synch_cl_cg u_ctu_sparc6_cmp_cken_cl(
.start_clk_cl(start_clk_cl),
/*AUTOINST*/
// Outputs
.syncdata(ctu_sparc6_cmp_cken_cg), // Templated
// Inputs
.cmp_clk(cmp_clk),
.arst_l(io_pwron_rst_l), // Templated
.force_cken(force_cken),
.presyncdata(ctu_sparc6_cken_cl)); // Templated
ctu_synch_cl_cg u_ctu_sparc7_cmp_cken_cl(
.start_clk_cl(start_clk_cl),
/*AUTOINST*/
// Outputs
.syncdata(ctu_sparc7_cmp_cken_cg), // Templated
// Inputs
.cmp_clk(cmp_clk),
.arst_l(io_pwron_rst_l), // Templated
.force_cken(force_cken),
.presyncdata(ctu_sparc7_cken_cl)); // Templated
/* ctu_synch_cl_cg AUTO_TEMPLATE (
.presyncdata (ctu_scdata@_cken_cl),
.syncdata (ctu_scdata@_cmp_cken_cg),
.arst_l(io_pwron_rst_l),
);
*/
ctu_synch_cl_cg u_ctu_scdata0_cmp_cken_cl(
.start_clk_cl(start_clk_cl),
/*AUTOINST*/
// Outputs
.syncdata(ctu_scdata0_cmp_cken_cg), // Templated
// Inputs
.cmp_clk(cmp_clk),
.arst_l(io_pwron_rst_l), // Templated
.force_cken(force_cken),
.presyncdata(ctu_scdata0_cken_cl)); // Templated
ctu_synch_cl_cg u_ctu_scdata1_cmp_cken_cl(
.start_clk_cl(start_clk_cl),
/*AUTOINST*/
// Outputs
.syncdata(ctu_scdata1_cmp_cken_cg), // Templated
// Inputs
.cmp_clk(cmp_clk),
.arst_l(io_pwron_rst_l), // Templated
.force_cken(force_cken),
.presyncdata(ctu_scdata1_cken_cl)); // Templated
ctu_synch_cl_cg u_ctu_scdata2_cmp_cken_cl(
.start_clk_cl(start_clk_cl),
/*AUTOINST*/
// Outputs
.syncdata(ctu_scdata2_cmp_cken_cg), // Templated
// Inputs
.cmp_clk(cmp_clk),
.arst_l(io_pwron_rst_l), // Templated
.force_cken(force_cken),
.presyncdata(ctu_scdata2_cken_cl)); // Templated
ctu_synch_cl_cg u_ctu_scdata3_cmp_cken_cl(
.start_clk_cl(start_clk_cl),
/*AUTOINST*/
// Outputs
.syncdata(ctu_scdata3_cmp_cken_cg), // Templated
// Inputs
.cmp_clk(cmp_clk),
.arst_l(io_pwron_rst_l), // Templated
.force_cken(force_cken),
.presyncdata(ctu_scdata3_cken_cl)); // Templated
/* ctu_synch_cl_cg AUTO_TEMPLATE (
.presyncdata (ctu_sctag@_cken_cl),
.syncdata (ctu_sctag@_cmp_cken_cg),
.arst_l(io_pwron_rst_l),
);
*/
ctu_synch_cl_cg u_ctu_sctag0_cmp_cken_cl(
.start_clk_cl(start_clk_cl),
/*AUTOINST*/
// Outputs
.syncdata(ctu_sctag0_cmp_cken_cg), // Templated
// Inputs
.cmp_clk(cmp_clk),
.arst_l(io_pwron_rst_l), // Templated
.force_cken(force_cken),
.presyncdata(ctu_sctag0_cken_cl)); // Templated
ctu_synch_cl_cg u_ctu_sctag1_cmp_cken_cl(
.start_clk_cl(start_clk_cl),
/*AUTOINST*/
// Outputs
.syncdata(ctu_sctag1_cmp_cken_cg), // Templated
// Inputs
.cmp_clk(cmp_clk),
.arst_l(io_pwron_rst_l), // Templated
.force_cken(force_cken),
.presyncdata(ctu_sctag1_cken_cl)); // Templated
ctu_synch_cl_cg u_ctu_sctag2_cmp_cken_cl(
.start_clk_cl(start_clk_cl),
/*AUTOINST*/
// Outputs
.syncdata(ctu_sctag2_cmp_cken_cg), // Templated
// Inputs
.cmp_clk(cmp_clk),
.arst_l(io_pwron_rst_l), // Templated
.force_cken(force_cken),
.presyncdata(ctu_sctag2_cken_cl)); // Templated
ctu_synch_cl_cg u_ctu_sctag3_cmp_cken_cl(
.start_clk_cl(start_clk_cl),
/*AUTOINST*/
// Outputs
.syncdata(ctu_sctag3_cmp_cken_cg), // Templated
// Inputs
.cmp_clk(cmp_clk),
.arst_l(io_pwron_rst_l), // Templated
.force_cken(force_cken),
.presyncdata(ctu_sctag3_cken_cl)); // Templated
/* ctu_synch_cl_cg AUTO_TEMPLATE (
.presyncdata (ctu_ccx_cken_cl),
.syncdata (ctu_ccx_cmp_cken_cg),
.arst_l(io_pwron_rst_l),
);
*/
ctu_synch_cl_cg u_ctu_ccx_cmp_cken_cl(
.start_clk_cl(start_clk_cl),
/*AUTOINST*/
// Outputs
.syncdata(ctu_ccx_cmp_cken_cg), // Templated
// Inputs
.cmp_clk(cmp_clk),
.arst_l(io_pwron_rst_l), // Templated
.force_cken(force_cken),
.presyncdata(ctu_ccx_cken_cl)); // Templated
/* ctu_synch_cl_cg AUTO_TEMPLATE (
.presyncdata (ctu_fpu_cken_cl),
.syncdata (ctu_fpu_cmp_cken_cg),
.arst_l(io_pwron_rst_l),
);
*/
ctu_synch_cl_cg u_ctu_fpu_cmp_cken_cl(
.start_clk_cl(start_clk_cl),
/*AUTOINST*/
// Outputs
.syncdata(ctu_fpu_cmp_cken_cg), // Templated
// Inputs
.cmp_clk(cmp_clk),
.arst_l(io_pwron_rst_l), // Templated
.force_cken(force_cken),
.presyncdata(ctu_fpu_cken_cl)); // Templated
/* ctu_synch_cl_cg AUTO_TEMPLATE (
.presyncdata (ctu_iob_cken_cl),
.syncdata (ctu_iob_cmp_cken_cg),
.arst_l(io_pwron_rst_l),
);
*/
ctu_synch_cl_cg u_ctu_iob_cmp_cken_cl(
.start_clk_cl(start_clk_cl),
/*AUTOINST*/
// Outputs
.syncdata(ctu_iob_cmp_cken_cg), // Templated
// Inputs
.cmp_clk(cmp_clk),
.arst_l(io_pwron_rst_l), // Templated
.force_cken(force_cken),
.presyncdata(ctu_iob_cken_cl)); // Templated
/* ctu_synch_cl_cg AUTO_TEMPLATE (
.presyncdata (ctu_jbi_cken_cl),
.syncdata (ctu_jbi_cmp_cken_cg),
.arst_l(io_pwron_rst_l),
);
*/
ctu_synch_cl_cg u_ctu_jbi_cmp_cken_cl(
.start_clk_cl(start_clk_cl),
/*AUTOINST*/
// Outputs
.syncdata(ctu_jbi_cmp_cken_cg), // Templated
// Inputs
.cmp_clk(cmp_clk),
.arst_l(io_pwron_rst_l), // Templated
.force_cken(force_cken),
.presyncdata(ctu_jbi_cken_cl)); // Templated
/* ctu_synch_cl_cg AUTO_TEMPLATE (
.presyncdata (ctu_dram02_cken_cl),
.syncdata (ctu_dram02_cmp_cken_cg),
.arst_l(io_pwron_rst_l),
);
*/
ctu_synch_cl_cg u_ctu_dram02_cmp_cken_cl(
.start_clk_cl(start_clk_cl),
/*AUTOINST*/
// Outputs
.syncdata(ctu_dram02_cmp_cken_cg), // Templated
// Inputs
.cmp_clk(cmp_clk),
.arst_l(io_pwron_rst_l), // Templated
.force_cken(force_cken),
.presyncdata(ctu_dram02_cken_cl)); // Templated
/* ctu_synch_cl_cg AUTO_TEMPLATE (
.presyncdata (ctu_dram13_cken_cl),
.syncdata (ctu_dram13_cmp_cken_cg),
.arst_l(io_pwron_rst_l),
);
*/
ctu_synch_cl_cg u_ctu_dram13_cmp_cken_cl(
.start_clk_cl(start_clk_cl),
/*AUTOINST*/
// Outputs
.syncdata(ctu_dram13_cmp_cken_cg), // Templated
// Inputs
.cmp_clk(cmp_clk),
.arst_l(io_pwron_rst_l), // Templated
.force_cken(force_cken),
.presyncdata(ctu_dram13_cken_cl)); // Templated
/* dffrle_ns AUTO_TEMPLATE (
.din (de_grst_jl),
.q (de_grst_cl),
.en(jbus_rx_sync),
.rst_l(start_clk_cl),
.clk (cmp_clk),
);
*/
dffrle_ns u_grst_en(
.rst_l (start_clk_cl),
/*AUTOINST*/
// Outputs
.q (de_grst_cl), // Templated
// Inputs
.din (de_grst_jl), // Templated
.en (jbus_rx_sync), // Templated
.clk (cmp_clk)); // Templated
/* dffrle_ns AUTO_TEMPLATE (
.din (a_grst_jl),
.q (a_grst_cl),
.en(jbus_rx_sync),
.rst_l(start_clk_cl),
.clk (cmp_clk),
);
*/
dffrle_ns u_grst_dis(
.rst_l (start_clk_cl),
/*AUTOINST*/
// Outputs
.q (a_grst_cl), // Templated
// Inputs
.din (a_grst_jl), // Templated
.en (jbus_rx_sync), // Templated
.clk (cmp_clk)); // Templated
/* dffrle_ns AUTO_TEMPLATE (
.din (dram_a_grst_jl),
.q (dram_a_grst_cl),
.en(jbus_rx_sync),
.rst_l(start_clk_cl),
.clk (cmp_clk),
);
*/
dffrle_ns u_dram_grst_dis(
.rst_l (start_clk_cl),
/*AUTOINST*/
// Outputs
.q (dram_a_grst_cl), // Templated
// Inputs
.din (dram_a_grst_jl), // Templated
.en (jbus_rx_sync), // Templated
.clk (cmp_clk)); // Templated
/* dffrle_ns AUTO_TEMPLATE (
.din(de_dbginit_jl),
.q (de_dbginit_cl),
.en(jbus_rx_sync),
.rst_l(start_clk_cl),
.clk (cmp_clk),
);
*/
dffrle_ns u_de_dbginit(
.rst_l (start_clk_cl),
/*AUTOINST*/
// Outputs
.q (de_dbginit_cl), // Templated
// Inputs
.din (de_dbginit_jl), // Templated
.en (jbus_rx_sync), // Templated
.clk (cmp_clk)); // Templated
/* dffrle_ns AUTO_TEMPLATE (
.din(a_dbginit_jl),
.q (a_dbginit_cl),
.en(jbus_rx_sync),
.rst_l(start_clk_cl),
.clk (cmp_clk),
);
*/
dffrle_ns u_a_dbginit(
.rst_l (start_clk_cl),
/*AUTOINST*/
// Outputs
.q (a_dbginit_cl), // Templated
// Inputs
.din (a_dbginit_jl), // Templated
.en (jbus_rx_sync), // Templated
.clk (cmp_clk)); // Templated
// clkctrl block
/* dffrl_ns AUTO_TEMPLATE (
.din(sctag@_ctu_tr),
.q (sctag@_ctu_tr_ff),
.rst_l(start_clk_cl),
.clk (cmp_clk),
);
*/
dffrl_ns u_sctag0_ctu_tr_ff ( .rst_l (start_clk_cl), /*AUTOINST*/
// Outputs
.q (sctag0_ctu_tr_ff), // Templated
// Inputs
.din (sctag0_ctu_tr), // Templated
.clk (cmp_clk)); // Templated
dffrl_ns u_sctag1_ctu_tr_ff ( .rst_l (start_clk_cl), /*AUTOINST*/
// Outputs
.q (sctag1_ctu_tr_ff), // Templated
// Inputs
.din (sctag1_ctu_tr), // Templated
.clk (cmp_clk)); // Templated
dffrl_ns u_sctag2_ctu_tr_ff ( .rst_l (start_clk_cl), /*AUTOINST*/
// Outputs
.q (sctag2_ctu_tr_ff), // Templated
// Inputs
.din (sctag2_ctu_tr), // Templated
.clk (cmp_clk)); // Templated
dffrl_ns u_sctag3_ctu_tr_ff ( .rst_l (start_clk_cl), /*AUTOINST*/
// Outputs
.q (sctag3_ctu_tr_ff), // Templated
// Inputs
.din (sctag3_ctu_tr), // Templated
.clk (cmp_clk)); // Templated
/* dffrl_ns AUTO_TEMPLATE (
.din(sctag@_ctu_tr_ff),
.q (sctag@_ctu_tr_cl),
.rst_l(start_clk_cl),
.clk (cmp_clk),
);
*/
dffrl_ns u_sctag0_ctu_tr_cl ( .rst_l (start_clk_cl), /*AUTOINST*/
// Outputs
.q (sctag0_ctu_tr_cl), // Templated
// Inputs
.din (sctag0_ctu_tr_ff), // Templated
.clk (cmp_clk)); // Templated
dffrl_ns u_sctag1_ctu_tr_cl ( .rst_l (start_clk_cl), /*AUTOINST*/
// Outputs
.q (sctag1_ctu_tr_cl), // Templated
// Inputs
.din (sctag1_ctu_tr_ff), // Templated
.clk (cmp_clk)); // Templated
dffrl_ns u_sctag2_ctu_tr_cl ( .rst_l (start_clk_cl), /*AUTOINST*/
// Outputs
.q (sctag2_ctu_tr_cl), // Templated
// Inputs
.din (sctag2_ctu_tr_ff), // Templated
.clk (cmp_clk)); // Templated
dffrl_ns u_sctag3_ctu_tr_cl ( .rst_l (start_clk_cl), /*AUTOINST*/
// Outputs
.q (sctag3_ctu_tr_cl), // Templated
// Inputs
.din (sctag3_ctu_tr_ff), // Templated
.clk (cmp_clk)); // Templated
/* dffrle_ns AUTO_TEMPLATE (
.din(creg_cken_vld_jl),
.q (creg_cken_vld_cl),
.en(jbus_rx_sync),
.rst_l(start_clk_cl),
.clk (cmp_clk),
);
*/
dffrle_ns u_creg_cken_vld_cl( .rst_l (start_clk_cl), /*AUTOINST*/
// Outputs
.q (creg_cken_vld_cl), // Templated
// Inputs
.din (creg_cken_vld_jl), // Templated
.en (jbus_rx_sync), // Templated
.clk (cmp_clk)); // Templated
/* dffrle_ns AUTO_TEMPLATE (
.din(rstctrl_idle_jl),
.q (rstctrl_idle_cl),
.en(jbus_rx_sync),
.rst_l(start_clk_cl),
.clk (cmp_clk),
);
*/
dffrle_ns u_rstctrl_idle_cl( .rst_l (start_clk_cl), /*AUTOINST*/
// Outputs
.q (rstctrl_idle_cl), // Templated
// Inputs
.din (rstctrl_idle_jl), // Templated
.en (jbus_rx_sync), // Templated
.clk (cmp_clk)); // Templated
/* dffrle_ns AUTO_TEMPLATE (
.din(rstctrl_disclk_jl),
.q (rstctrl_disclk_cl),
.en(jbus_rx_sync),
.rst_l(start_clk_cl),
.clk (cmp_clk),
);
*/
dffrle_ns u_rstctrl_disclk_cl( .rst_l (start_clk_cl), /*AUTOINST*/
// Outputs
.q (rstctrl_disclk_cl), // Templated
// Inputs
.din (rstctrl_disclk_jl), // Templated
.en (jbus_rx_sync), // Templated
.clk (cmp_clk)); // Templated
/* dffrle_ns AUTO_TEMPLATE (
.din(rstctrl_enclk_jl),
.q (rstctrl_enclk_cl),
.en(jbus_rx_sync),
.rst_l(start_clk_cl),
.clk (cmp_clk),
);
*/
dffrle_ns u_rstctrl_enclk_cl( .rst_l (start_clk_cl), /*AUTOINST*/
// Outputs
.q (rstctrl_enclk_cl), // Templated
// Inputs
.din (rstctrl_enclk_jl), // Templated
.en (jbus_rx_sync), // Templated
.clk (cmp_clk)); // Templated
/* dffrle_ns AUTO_TEMPLATE (
.din(iob_ctu_tr_jl),
.q (iob_ctu_tr_cl),
.en(jbus_rx_sync),
.rst_l(start_clk_cl),
.clk (cmp_clk),
);
*/
dffrle_ns u_iob_ctu_tr_cl( .rst_l (start_clk_cl), /*AUTOINST*/
// Outputs
.q (iob_ctu_tr_cl), // Templated
// Inputs
.din (iob_ctu_tr_jl), // Templated
.en (jbus_rx_sync), // Templated
.clk (cmp_clk)); // Templated
/* dffrle_ns AUTO_TEMPLATE (
.din(dram@_ctu_tr_jl),
.q (dram@_ctu_tr_cl),
.en(jbus_rx_sync),
.rst_l(start_clk_cl),
.clk (cmp_clk),
);
*/
dffrle_ns u_dram02_ctu_tr_cl( .rst_l (start_clk_cl), /*AUTOINST*/
// Outputs
.q (dram02_ctu_tr_cl), // Templated
// Inputs
.din (dram02_ctu_tr_jl), // Templated
.en (jbus_rx_sync), // Templated
.clk (cmp_clk)); // Templated
dffrle_ns u_dram13_ctu_tr_cl( .rst_l (start_clk_cl), /*AUTOINST*/
// Outputs
.q (dram13_ctu_tr_cl), // Templated
// Inputs
.din (dram13_ctu_tr_jl), // Templated
.en (jbus_rx_sync), // Templated
.clk (cmp_clk)); // Templated
/* dffrle_ns AUTO_TEMPLATE (
.din(jbi_ctu_tr_jl),
.q (jbi_ctu_tr_cl),
.en(jbus_rx_sync),
.rst_l(start_clk_cl),
.clk (cmp_clk),
);
*/
dffrle_ns u_jbi_ctu_tr_cl( .rst_l (start_clk_cl), /*AUTOINST*/
// Outputs
.q (jbi_ctu_tr_cl), // Templated
// Inputs
.din (jbi_ctu_tr_jl), // Templated
.en (jbus_rx_sync), // Templated
.clk (cmp_clk)); // Templated
/* dffrle_ns AUTO_TEMPLATE (
.din(iob_ctu_l2_tr_jl),
.q (iob_ctu_l2_tr_cl),
.en(jbus_rx_sync),
.rst_l(start_clk_cl),
.clk (cmp_clk),
);
*/
dffrle_ns u_iob_ctu_l2_tr_cl( .rst_l (start_clk_cl), /*AUTOINST*/
// Outputs
.q (iob_ctu_l2_tr_cl), // Templated
// Inputs
.din (iob_ctu_l2_tr_jl), // Templated
.en (jbus_rx_sync), // Templated
.clk (cmp_clk)); // Templated
/* dffrle_ns AUTO_TEMPLATE (
.din(stop_id_vld_jl),
.q (stop_id_vld_cl),
.en(jbus_rx_sync),
.rst_l(start_clk_cl),
.clk (cmp_clk),
);
*/
dffrle_ns u_stop_id_vld_cl( .rst_l (start_clk_cl), /*AUTOINST*/
// Outputs
.q (stop_id_vld_cl), // Templated
// Inputs
.din (stop_id_vld_jl), // Templated
.en (jbus_rx_sync), // Templated
.clk (cmp_clk)); // Templated
/* dffrle_ns AUTO_TEMPLATE (
.din(stop_id_decoded_jl[`CCTRLSM_MAX_ST-1:0]),
.q (stop_id_decoded_cl[`CCTRLSM_MAX_ST-1:0]),
.en(jbus_rx_sync),
.rst_l(start_clk_cl),
.clk (cmp_clk),
);
*/
//dffrle_ns #(`CCTRLSM_MAX_ST) u_stop_id_decoded_cl( .rst_l (start_clk_cl), /*AUTOINST*/
// // Outputs
// .q(stop_id_decoded_cl[`CCTRLSM_MAX_ST-1:0]),
// // Inputs
// .din(stop_id_decoded_jl[`CCTRLSM_MAX_ST-1:0]),
// .en(jbus_rx_sync),
// .clk(cmp_clk));
/* dffrle_ns AUTO_TEMPLATE (
.din(dbgtrig_dly_cnt_val[4:0]),
.q (dbgtrig_dly_cnt_val_cl[4:0]),
.en(jbus_rx_sync),
.rst_l(start_clk_cl),
.clk (cmp_clk),
);
*/
dffrle_ns #(5) u_dbgtrig_dly_cnt_val ( .rst_l (start_clk_cl), /*AUTOINST*/
// Outputs
.q(dbgtrig_dly_cnt_val_cl[4:0]), // Templated
// Inputs
.din(dbgtrig_dly_cnt_val[4:0]), // Templated
.en(jbus_rx_sync), // Templated
.clk(cmp_clk)); // Templated
/* dffrl_async_ns AUTO_TEMPLATE (
.din(update_clkctrl_reg_jl_nxt ),
.q (update_clkctrl_reg_cl),
.rst_l(io_pwron_rst_l),
.clk (cmp_clk),
);
*/
assign update_clkctrl_reg_jl_nxt = (jbus_rx_sync ? update_clkctrl_reg_jl : update_clkctrl_reg_cl)
& start_clk_cl;
dffrl_async_ns u_update_clkctrl_reg_cl( .din (update_clkctrl_reg_jl_nxt), /*AUTOINST*/
// Outputs
.q(update_clkctrl_reg_cl), // Templated
// Inputs
.clk(cmp_clk), // Templated
.rst_l(io_pwron_rst_l)); // Templated
/* dffrl_async_ns AUTO_TEMPLATE (
.din(rd_clkctrl_reg_jl_nxt ),
.q (rd_clkctrl_reg_cl),
.rst_l(io_pwron_rst_l),
.clk (cmp_clk),
);
*/
assign rd_clkctrl_reg_jl_nxt = (jbus_rx_sync ? rd_clkctrl_reg_jl : rd_clkctrl_reg_cl)
& start_clk_cl;
dffrl_async_ns u_rd_clkctrl_reg_jl( .din (rd_clkctrl_reg_jl_nxt), /*AUTOINST*/
// Outputs
.q(rd_clkctrl_reg_cl), // Templated
// Inputs
.clk(cmp_clk), // Templated
.rst_l(io_pwron_rst_l)); // Templated
/* dffrle_ns AUTO_TEMPLATE (
.din (clkctrl_dn_cl),
.q (clkctrl_dn_jl),
.en(jbus_tx_sync),
.rst_l(start_clk_cl),
.clk (cmp_clk),
);
*/
dffrle_ns u_clkctrl_dn_jl ( .rst_l (start_clk_cl), /*AUTOINST*/
// Outputs
.q (clkctrl_dn_jl), // Templated
// Inputs
.din (clkctrl_dn_cl), // Templated
.en (jbus_tx_sync), // Templated
.clk (cmp_clk)); // Templated
/* dffrle_ns AUTO_TEMPLATE (
.din (ctu_io_j_err_cl),
.q (ctu_io_j_err_jl),
.en(jbus_tx_sync),
.rst_l(start_clk_cl),
.clk (cmp_clk),
);
*/
dffrle_ns u_ctu_io_j_err_jl ( .rst_l (start_clk_cl), /*AUTOINST*/
// Outputs
.q (ctu_io_j_err_jl), // Templated
// Inputs
.din (ctu_io_j_err_cl), // Templated
.en (jbus_tx_sync), // Templated
.clk (cmp_clk)); // Templated
/* dffrle_ns AUTO_TEMPLATE (
.din(ctu_dram@_cken_cl),
.q (ctu_dram@_cken_pre_jl),
.en(jbus_tx_sync),
.rst_l(start_clk_cl),
.clk (cmp_clk),
);
*/
dffrle_ns u_ctu_dram02_cken_jl( .rst_l (start_clk_cl), /*AUTOINST*/
// Outputs
.q (ctu_dram02_cken_pre_jl), // Templated
// Inputs
.din(ctu_dram02_cken_cl), // Templated
.en (jbus_tx_sync), // Templated
.clk(cmp_clk)); // Templated
dffrle_ns u_ctu_dram13_cken_jl( .rst_l (start_clk_cl), /*AUTOINST*/
// Outputs
.q (ctu_dram13_cken_pre_jl), // Templated
// Inputs
.din(ctu_dram13_cken_cl), // Templated
.en (jbus_tx_sync), // Templated
.clk(cmp_clk)); // Templated
/* dffrle_ns AUTO_TEMPLATE (
.din(ctu_iob_cken_cl),
.q (ctu_iob_cken_pre_jl),
.en(jbus_tx_sync),
.rst_l(start_clk_cl),
.clk (cmp_clk),
);
*/
dffrle_ns u_ctu_iob_cken_jl( .rst_l (start_clk_cl), /*AUTOINST*/
// Outputs
.q (ctu_iob_cken_pre_jl), // Templated
// Inputs
.din (ctu_iob_cken_cl), // Templated
.en (jbus_tx_sync), // Templated
.clk (cmp_clk)); // Templated
/* dffrle_ns AUTO_TEMPLATE (
.din(ctu_efc_cken_cl),
.q (ctu_efc_cken_pre_jl),
.en(jbus_tx_sync),
.rst_l(start_clk_cl),
.clk (cmp_clk),
);
*/
dffrle_ns u_ctu_efc_cken_jl( .rst_l (start_clk_cl), /*AUTOINST*/
// Outputs
.q (ctu_efc_cken_pre_jl), // Templated
// Inputs
.din (ctu_efc_cken_cl), // Templated
.en (jbus_tx_sync), // Templated
.clk (cmp_clk)); // Templated
/* dffsl_async_ns AUTO_TEMPLATE (
.din(ctu_jbusl_cken_jl_nxt),
.q (ctu_jbusl_cken_pre_jl),
.set_l(io_pwron_rst_l),
.clk (cmp_clk),
);
*/
assign ctu_jbusl_cken_jl_nxt = start_clk_cl ?
(jbus_rx_sync? ctu_jbusl_cken_cl: ctu_jbusl_cken_pre_jl):
1'b1;
dffsl_async_ns u_ctu_jbusl_cken_jl(
.din (ctu_jbusl_cken_jl_nxt),
/*AUTOINST*/
// Outputs
.q(ctu_jbusl_cken_pre_jl), // Templated
// Inputs
.clk(cmp_clk), // Templated
.set_l(io_pwron_rst_l)); // Templated
/* dffsl_async_ns AUTO_TEMPLATE (
.din(ctu_jbusr_cken_jl_nxt),
.q (ctu_jbusr_cken_pre_jl),
.set_l(io_pwron_rst_l),
.clk (cmp_clk),
);
*/
assign ctu_jbusr_cken_jl_nxt = start_clk_cl ?
(jbus_rx_sync ? ctu_jbusr_cken_cl: ctu_jbusr_cken_pre_jl):
1'b1;
dffsl_async_ns u_ctu_jbusr_cken_jl(
.din (ctu_jbusr_cken_jl_nxt),
/*AUTOINST*/
// Outputs
.q(ctu_jbusr_cken_pre_jl), // Templated
// Inputs
.clk(cmp_clk), // Templated
.set_l(io_pwron_rst_l)); // Templated
/* dffrle_ns AUTO_TEMPLATE (
.din(ctu_jbi_cken_cl),
.q (ctu_jbi_cken_pre_jl),
.en(jbus_tx_sync),
.rst_l(start_clk_cl),
.clk (cmp_clk),
);
*/
dffrle_ns u_ctu_jbi_cken_jl( .rst_l (start_clk_cl), /*AUTOINST*/
// Outputs
.q (ctu_jbi_cken_pre_jl), // Templated
// Inputs
.din (ctu_jbi_cken_cl), // Templated
.en (jbus_tx_sync), // Templated
.clk (cmp_clk)); // Templated
/* dffsl_async_ns AUTO_TEMPLATE (
.din(ctu_dbg_cken_jl_nxt),
.q (ctu_dbg_cken_pre_jl),
.set_l(io_pwron_rst_l),
.clk (cmp_clk),
);
*/
assign ctu_dbg_cken_jl_nxt = start_clk_cl ?
(jbus_rx_sync ? ctu_dbg_cken_cl: ctu_dbg_cken_pre_jl):
1'b1;
dffsl_async_ns u_ctu_dbg_cken_jl( .din (ctu_dbg_cken_jl_nxt),
/*AUTOINST*/
// Outputs
.q(ctu_dbg_cken_pre_jl), // Templated
// Inputs
.clk(cmp_clk), // Templated
.set_l(io_pwron_rst_l)); // Templated
/* dffsl_async_ns AUTO_TEMPLATE (
.din(ctu_misc_cken_jl_nxt),
.q (ctu_misc_cken_pre_jl),
.set_l(io_pwron_rst_l),
.clk (cmp_clk),
);
*/
assign ctu_misc_cken_jl_nxt = start_clk_cl ?
(jbus_rx_sync ? ctu_misc_cken_cl: ctu_misc_cken_pre_jl):
1'b1;
dffsl_async_ns u_ctu_misc_cken_jl( .din (ctu_misc_cken_jl_nxt),
/*AUTOINST*/
// Outputs
.q(ctu_misc_cken_pre_jl), // Templated
// Inputs
.clk(cmp_clk), // Templated
.set_l(io_pwron_rst_l)); // Templated
/* dffrle_ns AUTO_TEMPLATE (
.din(clsp_ctrl_srarm_cl),
.q (clsp_ctrl_srarm_pre_jl),
.en(jbus_tx_sync),
.rst_l(start_clk_cl),
.clk (cmp_clk),
);
*/
dffrle_ns u_clsp_ctrl_srarm_pre_jl( .rst_l (start_clk_cl), /*AUTOINST*/
// Outputs
.q(clsp_ctrl_srarm_pre_jl), // Templated
// Inputs
.din(clsp_ctrl_srarm_cl), // Templated
.en(jbus_tx_sync), // Templated
.clk(cmp_clk)); // Templated
endmodule // ctu_clsp_jl_cl
// Local Variables:
// verilog-library-directories:("." "../common/rtl")
// verilog-library-files:("../common/rtl/ctu_lib.v" "../../common/rtl/swrvr_clib.v")
// verilog-auto-sense-defines-constant:t
// End:
|
//wishbone_interconnect.v
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Thanks Rudolf Usselmann yours was a better implementation than mine
Copyright (C) 2000-2002
Rudolf Usselmann
www.asics.ws
[email protected]
*/
`timescale 1 ns/1 ps
module wishbone_interconnect (
//control signals
input clk,
input rst,
//wishbone master signals
input i_m_we,
input i_m_stb,
input i_m_cyc,
input [3:0] i_m_sel,
input [31:0] i_m_adr,
input [31:0] i_m_dat,
output reg [31:0] o_m_dat,
output reg o_m_ack,
output o_m_int,
//Slave 0
output o_s0_we,
output o_s0_cyc,
output o_s0_stb,
output [3:0] o_s0_sel,
input i_s0_ack,
output [31:0] o_s0_dat,
input [31:0] i_s0_dat,
output [31:0] o_s0_adr,
input i_s0_int,
//Slave 1
output o_s1_we,
output o_s1_cyc,
output o_s1_stb,
output [3:0] o_s1_sel,
input i_s1_ack,
output [31:0] o_s1_dat,
input [31:0] i_s1_dat,
output [31:0] o_s1_adr,
input i_s1_int,
//Slave 2
output o_s2_we,
output o_s2_cyc,
output o_s2_stb,
output [3:0] o_s2_sel,
input i_s2_ack,
output [31:0] o_s2_dat,
input [31:0] i_s2_dat,
output [31:0] o_s2_adr,
input i_s2_int,
//Slave 3
output o_s3_we,
output o_s3_cyc,
output o_s3_stb,
output [3:0] o_s3_sel,
input i_s3_ack,
output [31:0] o_s3_dat,
input [31:0] i_s3_dat,
output [31:0] o_s3_adr,
input i_s3_int,
//Slave 4
output o_s4_we,
output o_s4_cyc,
output o_s4_stb,
output [3:0] o_s4_sel,
input i_s4_ack,
output [31:0] o_s4_dat,
input [31:0] i_s4_dat,
output [31:0] o_s4_adr,
input i_s4_int
);
parameter ADDR_0 = 0;
parameter ADDR_1 = 1;
parameter ADDR_2 = 2;
parameter ADDR_3 = 3;
parameter ADDR_4 = 4;
parameter ADDR_FF = 8'hFF;
//state
//wishbone slave signals
//this should be parameterized
wire [7:0]slave_select;
wire [31:0] interrupts;
assign slave_select = i_m_adr[31:24];
//data in from slave
always @ (slave_select or i_s0_dat or i_s1_dat or i_s2_dat or i_s3_dat or i_s4_dat or interrupts) begin
case (slave_select)
ADDR_0: begin
o_m_dat <= i_s0_dat;
end
ADDR_1: begin
o_m_dat <= i_s1_dat;
end
ADDR_2: begin
o_m_dat <= i_s2_dat;
end
ADDR_3: begin
o_m_dat <= i_s3_dat;
end
ADDR_4: begin
o_m_dat <= i_s4_dat;
end
default: begin
o_m_dat <= interrupts;
end
endcase
end
//ack in from slave
always @ (slave_select or i_s0_ack or i_s1_ack or i_s2_ack or i_s3_ack or i_s4_ack) begin
case (slave_select)
ADDR_0: begin
o_m_ack <= i_s0_ack;
end
ADDR_1: begin
o_m_ack <= i_s1_ack;
end
ADDR_2: begin
o_m_ack <= i_s2_ack;
end
ADDR_3: begin
o_m_ack <= i_s3_ack;
end
ADDR_4: begin
o_m_ack <= i_s4_ack;
end
default: begin
o_m_ack <= 1'h0;
end
endcase
end
//int in from slave
assign interrupts[0] = i_s0_int;
assign interrupts[1] = i_s1_int;
assign interrupts[2] = i_s2_int;
assign interrupts[3] = i_s3_int;
assign interrupts[4] = i_s4_int;
assign interrupts[31:5] = 0;
assign o_m_int = (interrupts != 0);
assign o_s0_we = (slave_select == ADDR_0) ? i_m_we: 1'b0;
assign o_s0_stb = (slave_select == ADDR_0) ? i_m_stb: 1'b0;
assign o_s0_sel = (slave_select == ADDR_0) ? i_m_sel: 4'h0;
assign o_s0_cyc = (slave_select == ADDR_0) ? i_m_cyc: 1'b0;
assign o_s0_adr = (slave_select == ADDR_0) ? {8'h0, i_m_adr[23:0]}: 32'h0;
assign o_s0_dat = (slave_select == ADDR_0) ? i_m_dat: 32'h0;
assign o_s1_we = (slave_select == ADDR_1) ? i_m_we: 1'b0;
assign o_s1_stb = (slave_select == ADDR_1) ? i_m_stb: 1'b0;
assign o_s1_sel = (slave_select == ADDR_1) ? i_m_sel: 4'h0;
assign o_s1_cyc = (slave_select == ADDR_1) ? i_m_cyc: 1'b0;
assign o_s1_adr = (slave_select == ADDR_1) ? {8'h0, i_m_adr[23:0]}: 32'h0;
assign o_s1_dat = (slave_select == ADDR_1) ? i_m_dat: 32'h0;
assign o_s2_we = (slave_select == ADDR_2) ? i_m_we: 1'b0;
assign o_s2_stb = (slave_select == ADDR_2) ? i_m_stb: 1'b0;
assign o_s2_sel = (slave_select == ADDR_2) ? i_m_sel: 4'h0;
assign o_s2_cyc = (slave_select == ADDR_2) ? i_m_cyc: 1'b0;
assign o_s2_adr = (slave_select == ADDR_2) ? {8'h0, i_m_adr[23:0]}: 32'h0;
assign o_s2_dat = (slave_select == ADDR_2) ? i_m_dat: 32'h0;
assign o_s3_we = (slave_select == ADDR_3) ? i_m_we: 1'b0;
assign o_s3_stb = (slave_select == ADDR_3) ? i_m_stb: 1'b0;
assign o_s3_sel = (slave_select == ADDR_3) ? i_m_sel: 4'h0;
assign o_s3_cyc = (slave_select == ADDR_3) ? i_m_cyc: 1'b0;
assign o_s3_adr = (slave_select == ADDR_3) ? {8'h0, i_m_adr[23:0]}: 32'h0;
assign o_s3_dat = (slave_select == ADDR_3) ? i_m_dat: 32'h0;
assign o_s4_we = (slave_select == ADDR_4) ? i_m_we: 1'b0;
assign o_s4_stb = (slave_select == ADDR_4) ? i_m_stb: 1'b0;
assign o_s4_sel = (slave_select == ADDR_4) ? i_m_sel: 4'h0;
assign o_s4_cyc = (slave_select == ADDR_4) ? i_m_cyc: 1'b0;
assign o_s4_adr = (slave_select == ADDR_4) ? {8'h0, i_m_adr[23:0]}: 32'h0;
assign o_s4_dat = (slave_select == ADDR_4) ? i_m_dat: 32'h0;
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ctu_lib.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//
// Cluster Name: CTU
//
//-----------------------------------------------------------------------------
`include "sys.h"
//---------------------------
//
// Lauching clock: raw_clk_out
// Receiving clock : jbus_clk
// Method: Latch for hold time
//
//---------------------------
module ctu_synch_ref_jl(/*AUTOARG*/
// Outputs
syncdata,
// Inputs
pll_raw_clk_out, presyncdata
);
// synopsys template
parameter SIZE = 1;
input pll_raw_clk_out;
input [SIZE-1:0] presyncdata;
output [SIZE-1:0] syncdata;
wire [SIZE-1:0] presyncdata_in;
bw_u1_scanl_2x u_ctu_synch_ref_jl_0 [SIZE-1:0]
(.sd (presyncdata[SIZE-1:0]),
.ck (pll_raw_clk_out),
.so (syncdata[SIZE-1:0])
);
endmodule
//---------------------------
//
// Lauching clock: jbus_clk
// Receiving clock : raw_clk_out
// Method: Latch for hold time
//
//---------------------------
module ctu_synch_jl_ref(/*AUTOARG*/
// Outputs
syncdata,
// Inputs
jbus_clk, presyncdata
);
// synopsys template
parameter SIZE = 1;
input jbus_clk;
input [SIZE-1:0] presyncdata;
output [SIZE-1:0] syncdata;
wire [SIZE-1:0] presyncdata_in;
bw_u1_scanl_2x u_ctu_synch_jl_ref_0 [SIZE-1:0]
(.sd (presyncdata[SIZE-1:0]),
.ck (jbus_clk),
.so (syncdata[SIZE-1:0])
);
endmodule
//---------------------------
//
// Lauching clock: cmp_clk
// Receiving clock : cmp_gclk
//
//---------------------------
// Before re-time with gclk,
// the data needs to be register with local clock
// to garuantee setup
// Since the timing is very tight (200 ps setup skew)
// We move the testmode mux to cmp_clk domain
// before sending it to cmp_gclk
// All clock enable signals
module ctu_synch_cl_cg (/*AUTOARG*/
// Outputs
syncdata,
// Inputs
cmp_clk, start_clk_cl, arst_l, force_cken, presyncdata
);
// synopsys template
parameter SIZE = 1;
input cmp_clk;
input start_clk_cl;
input arst_l;
input force_cken;
input [SIZE-1:0] presyncdata;
output [SIZE-1:0] syncdata;
wire [SIZE-1:0] presyncdata_muxed;
assign presyncdata_muxed = force_cken? { SIZE {1'b1}} : {SIZE {start_clk_cl}} & presyncdata;
dffrl_async_ns #(SIZE) u_synch_jl_cl_ff1_nsr(
.din (presyncdata_muxed[SIZE-1:0]),
.clk (cmp_clk),
.rst_l(arst_l),
.q (syncdata[SIZE-1:0]));
endmodule
//---------------------------
//
// Lauching clock: cmp_clk
// Receiving clock : dram_gclk
// Method: sync pulse (one clock earlier than dram_tx_sync)
// data available on rising edge of dram_clk
// then clocked by dram_gclk on next edge
//
//---------------------------
module ctu_synch_cl_dl(/*AUTOARG*/
// Outputs
syncdata,
// Inputs
cmp_clk, ctu_dram_tx_sync_early, presyncdata
);
// synopsys template
parameter SIZE = 1;
input cmp_clk;
input ctu_dram_tx_sync_early;
input [SIZE-1:0] presyncdata;
output [SIZE-1:0] syncdata;
dffe_ns #(SIZE) u_synch_cl_dl_ff0(
.din (presyncdata[SIZE-1:0]),
.clk (cmp_clk),
.en(ctu_dram_tx_sync_early),
.q (syncdata[SIZE-1:0]));
endmodule
//---------------------------
//
// Lauching clock: jbus_clk
// Receiving clock : pseudo dram_clk (make use of coincident edge)
// Method: jbus_clk -> cmp_clk through coin edges
//
//---------------------------
module ctu_synch_jl_dl (/*AUTOARG*/
// Outputs
syncdata,
// Inputs
cmp_clk, jbus_rx_sync, coin_edge, arst_l, presyncdata
);
// synopsys template
parameter SIZE = 1;
input cmp_clk;
input jbus_rx_sync;
input coin_edge;
input arst_l;
input [SIZE-1:0] presyncdata;
output [SIZE-1:0] syncdata;
wire [SIZE-1:0] presyncdata_in;
wire [SIZE-1:0] presyncdata_in_nxt;
wire [SIZE-1:0] syncdata_nxt;
assign presyncdata_in_nxt = jbus_rx_sync ? presyncdata: presyncdata_in;
dffrl_async_ns #(SIZE) u_synch_cl_dl_ff0(
.din (presyncdata_in_nxt[SIZE-1:0]),
.clk (cmp_clk),
.rst_l(arst_l),
.q (presyncdata_in[SIZE-1:0]));
assign syncdata_nxt = coin_edge ? presyncdata_in : syncdata;
dffrl_async_ns #(SIZE) u_synch_cl_dl_ff2(
.din (syncdata_nxt[SIZE-1:0]),
.clk (cmp_clk),
.rst_l(arst_l),
.q (syncdata[SIZE-1:0]));
endmodule
//---------------------------
//
// Asynchronous interface
//
//---------------------------
module ctu_synchronizer (/*AUTOARG*/
// Outputs
syncdata,
// Inputs
clk, presyncdata
);
// synopsys template
parameter SIZE = 1;
input clk;
input [SIZE-1:0] presyncdata;
output [SIZE-1:0] syncdata;
wire [SIZE-1:0] presyncdata_tmp;
bw_u1_syncff_4x u_synchronizer_syncff [SIZE-1:0](.q(presyncdata_tmp),
.so(),
.ck(clk),
.d(presyncdata),
.sd(),
.se(1'b0)
);
bw_u1_soff_2x u_synchronizer_ff[SIZE-1:0] (.q(syncdata),
.so(),
.ck(clk),
.d(presyncdata_tmp),
.sd(),
.se(1'b0)
);
endmodule
//---------------------------
//
// Asynchronous interface (clock select blocks)
//
//---------------------------
module ctu_clksel_async_synchronizer (/*AUTOARG*/
// Outputs
syncdata,
// Inputs
clk, presyncdata, arst_l, aset_l
);
// synopsys template
parameter SIZE = 1;
input clk;
input [SIZE-1:0] presyncdata;
input arst_l;
input aset_l;
output [SIZE-1:0] syncdata;
wire [SIZE-1:0] presyncdata_in0;
wire [SIZE-1:0] presyncdata_in1;
bw_u1_soffasr_2x u_synchronizer_ff0_nsr[SIZE-1:0] (.q( presyncdata_in0),
.so(),
.ck(clk),
.d(presyncdata),
.sd(),
.se(1'b0),
.r_l (arst_l),
.s_l (aset_l)
);
bw_u1_soffasr_2x u_synchronizer_ff1_nsr[SIZE-1:0] (.q( presyncdata_in1),
.so(),
.ck(clk),
.d(presyncdata_in0),
.sd(),
.se(1'b0),
.r_l (arst_l),
.s_l (aset_l)
);
bw_u1_soffasr_2x u_synchronizer_neg_ff_nsr[SIZE-1:0] (.q( syncdata[SIZE-1:0]),
.so(),
.ck(~clk),
.d(presyncdata_in1[SIZE-1:0]),
.sd(),
.se(1'b0),
.r_l (arst_l),
.s_l (aset_l)
);
endmodule
module ctu_mux21 (d0, d1, s, z);
// synopsys template
parameter SIZE = 1;
input [SIZE-1:0] d0 ; // data in
input [SIZE-1:0] d1 ; // data in
input s; // select
output [SIZE-1:0] z ;
wire [SIZE-1:0] z_pre ;
// assign z = s ? d1 : d0;
bw_u1_muxi21_4x u_muxi21 [SIZE-1:0] (
.z(z_pre), .d0(d0), .d1(d1), .s(s) );
bw_u1_inv_5x u_inv [SIZE-1:0] (
.z(z), .a(z_pre));
endmodule
//---------------------------
//
// clock select components used in jtag
//
//---------------------------
module ctu_jtag_clk_sel_0_0_ff (/*AUTOARG*/
// Outputs
sel_clk,
// Inputs
test_mode_pin, trst, pll_bypass_pin, sel_ff
);
input test_mode_pin;
input trst;
input pll_bypass_pin;
input sel_ff;
output sel_clk;
wire tmp0, tmp1;
bw_u1_oai21_4x u_oai21 (.z(tmp0), .a(test_mode_pin), .b1(trst), .b2(pll_bypass_pin));
bw_u1_nand2_4x u_nand2 (.z(tmp1), .a(tmp0), .b(sel_ff));
bw_u1_inv_8x u_inv (.z(sel_clk), .a(tmp1) );
endmodule
module ctu_jtag_clk_sel_1_0_ff (/*AUTOARG*/
// Outputs
sel_clk,
// Inputs
test_mode_pin, trst, pll_bypass_pin, sel_ff
);
input test_mode_pin;
input trst;
input pll_bypass_pin;
input sel_ff;
output sel_clk;
wire tmp0, tmp1;
bw_u1_nand2_4x u_nand2 (.z(tmp0), .a(test_mode_pin), .b(pll_bypass_pin));
bw_u1_aoi22_4x u_aoi22 (.z(tmp1), .a1(test_mode_pin), .a2(trst), .b1(tmp0), .b2(sel_ff));
bw_u1_inv_8x u_inv (.z(sel_clk), .a(tmp1));
endmodule
module ctu_jtag_clk_sel_0_1_ff (/*AUTOARG*/
// Outputs
sel_clk,
// Inputs
test_mode_pin, trst, pll_bypass_pin, sel_ff
);
input test_mode_pin;
input trst;
input pll_bypass_pin;
input sel_ff;
output sel_clk;
wire tmp;
bw_u1_aoi21_4x u_aoi21_0 (.z(tmp), .a(sel_ff), .b1(test_mode_pin), .b2(pll_bypass_pin));
bw_u1_aoi21_4x u_aoi21_1 (.z(sel_clk), .a(tmp), .b1(test_mode_pin), .b2(trst));
endmodule
//---------------------------
//
// gated clock components
//
//---------------------------
module ctu_and2 (z, a, b);
output z;
input a;
input b;
bw_u1_nand2_4x u_nand2 ( .z(tmp), .a(a), .b(b) );
bw_u1_inv_8x u_inv ( .z(z), .a(tmp) );
endmodule
module ctu_and3 (z, a, b,c);
output z;
input a;
input b;
input c;
bw_u1_nand3_4x u_nand2 ( .z(tmp), .a(a), .b(b), .c(c) );
bw_u1_inv_8x u_inv ( .z(z), .a(tmp) );
endmodule
module ctu_inv (z, a);
output z;
input a;
bw_u1_inv_8x u_inv ( .z(z), .a(a) );
endmodule
module ctu_or2 (z, a, b);
output z;
input a;
input b;
bw_u1_nor2_4x u_nor2 ( .z(tmp), .a(a), .b(b) );
bw_u1_inv_8x u_inv ( .z(z), .a(tmp) );
endmodule
module ctu_nor2 (z, a, b);
output z;
input a;
input b;
bw_u1_nor2_4x u_nor2 ( .z(z), .a(a), .b(b) );
endmodule
|
module Section5_Top(
input DigitalLDir,
input DigitalRDir,
input reset_n,
output [3:0] outputs
/*output Len,
output Ldir,
output Ren,
output Rdir */
);
wire clk; //used for the oscillator's 2.08 MHz clock
wire clk_2; //used for slowed down, 5 Hz clock
//This is an instance of a special, built in module that accesses our chip's oscillator
OSCH #("2.08") osc_int ( //"2.03" specifies the operating frequency, 2.03 MHz. Other clock frequencies can be found in the MachX02's documentation
.STDBY(1'b0), //Specifies active state
.OSC(clk), //Outputs clock signal to 'clk' net
.SEDSTDBY()); //Leaves SEDSTDBY pin unconnected
//This module is instantiated from another file, 'Clock_Counter.v'
//It will take an input clock, slow it down based on parameters set inside of the module, and output the new clock. Reset functionality is also built-in
clock_counter counter_1(
.clk_i(clk),
.reset_n(reset_n),
.clk_o(clk_2));
//This module is instantiated from another file, 'State_Machine.v'
//It contains a Moore state machine that will take a clock and reset, and output LED combinations
Sec5_SM FSM_1(
.DigitalLDir(DigitalLDir),
.DigitalRDir(DigitalRDir),
.clk_i(clk_2),
.reset_n(reset_n),
.outputs(outputs)
/*.Len(Len),
.Ldir(Ldir),
.Ren(Ren),
.Rdir(Rdir)*/
);
endmodule |
module IDELAYE2 (/*AUTOARG*/
// Outputs
CNTVALUEOUT, DATAOUT,
// Inputs
C, CE, CINVCTRL, CNTVALUEIN, DATAIN, IDATAIN, INC, LD, LDPIPEEN,
REGRST
);
parameter CINVCTRL_SEL = "FALSE"; // Enable dynamic clock inversion
parameter DELAY_SRC = "IDATAIN"; // Delay input
parameter HIGH_PERFORMANCE_MODE = "FALSE"; // Reduced jitter
parameter IDELAY_TYPE = "FIXED"; // Type of delay line
parameter integer IDELAY_VALUE = 0; // Input delay tap setting
parameter [0:0] IS_C_INVERTED = 1'b0; //
parameter [0:0] IS_DATAIN_INVERTED = 1'b0; //
parameter [0:0] IS_IDATAIN_INVERTED = 1'b0; //
parameter PIPE_SEL = "FALSE"; // Select pipelined mode
parameter real REFCLK_FREQUENCY = 200.0; // Ref clock frequency
parameter SIGNAL_PATTERN = "DATA"; // Input signal type
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
parameter integer SIM_DELAY_D = 0;
localparam DELAY_D = (IDELAY_TYPE == "VARIABLE") ? SIM_DELAY_D : 0;
`endif // ifdef XIL_TIMING
`ifndef XIL_TIMING
integer DELAY_D=0;
`endif // ifndef XIL_TIMING
output [4:0] CNTVALUEOUT; // count value for monitoring tap value
output DATAOUT; // delayed data
input C; // clock input for variable mode
input CE; // enable increment/decrement function
input CINVCTRL; // dynamically inverts clock polarity
input [4:0] CNTVALUEIN; // counter value for tap delay
input DATAIN; // data input from FGPA logic
input IDATAIN; // data input from IBUF
input INC; // increment tap delay
input LD; // loads the delay primitive
input LDPIPEEN; // enables the pipeline register delay
input REGRST; // reset for pipeline register
assign DATAOUT = IDATAIN;
initial
begin
$display("Delay %d %m",IDELAY_VALUE);
end
endmodule // IDELAYE2
|
module Microfono(clk, reset, rec, play, bclk, lrsel, data_in, data_out, ampSD, rd, wr, emptyLED, fullLED);
input wire clk;
input wire reset;
input wire rec;
input wire play;
output wire bclk;
output wire lrsel;
input wire data_in;
output wire data_out;
output wire ampSD;
output wire rd;
output wire wr;
output wire emptyLED;
output wire fullLED;
wire empty;
wire full;
wire RstN;
wire FClrN;
wire F_LastN;
wire F_SLastN;
wire F_FirstN;
reg [5:0] fifo_counter = 0;
reg fclk = 1'b0;
assign FClrN = 1'b1;
assign emptyLED = ~empty;
assign fullLED = ~full;
always @(posedge bclk) // bclk = 1MHz
begin
if (reset)
begin
fifo_counter = 0;
fclk = 1'b1;
end
else
if (fifo_counter == 2) // fclk = 500KHz
begin
fifo_counter = 1;
fclk = ~fclk;
end
else
begin
fifo_counter = fifo_counter + 1;
fclk = fclk;
end
end
assign lrsel = 1'b0; //mic LRSel
assign ampSD = 1'b1;
DivFreq _DivFreq(
.reset(reset),
.clk(clk),
.bclk(bclk) // reloj de 1MHz
);
fifo _fifo(
.Clk(bclk), // reloj de la fifo
.RstN(~reset),
.Data_In(data_in),
.FClrN(FClrN),
.FInN(~wr),
.FOutN(~rd),
.F_Data(data_out),
.F_FullN(full),
.F_LastN(F_LastN),
.F_SLastN(F_SLastN),
.F_FirstN(F_FirstN),
.F_EmptyN(empty)
);
FSM _FSM(
.reset(reset),
.clk(clk),
.full(~full),
.empty(~empty),
.rec(rec),
.play(play),
.wr(wr),
.rd(rd)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XOR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__XOR2_FUNCTIONAL_PP_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__xor2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , B, A );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__XOR2_FUNCTIONAL_PP_V |
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_sdram_controller_0_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
)
;
output almost_empty;
output almost_full;
output empty;
output full;
output [ 40: 0] rd_data;
input clk;
input rd;
input reset_n;
input wr;
input [ 40: 0] wr_data;
wire almost_empty;
wire almost_full;
wire empty;
reg [ 1: 0] entries;
reg [ 40: 0] entry_0;
reg [ 40: 0] entry_1;
wire full;
reg rd_address;
reg [ 40: 0] rd_data;
wire [ 1: 0] rdwr;
reg wr_address;
assign rdwr = {rd, wr};
assign full = entries == 2;
assign almost_full = entries >= 1;
assign empty = entries == 0;
assign almost_empty = entries <= 1;
always @(entry_0 or entry_1 or rd_address)
begin
case (rd_address) // synthesis parallel_case full_case
1'd0: begin
rd_data = entry_0;
end // 1'd0
1'd1: begin
rd_data = entry_1;
end // 1'd1
default: begin
end // default
endcase // rd_address
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
wr_address <= 0;
rd_address <= 0;
entries <= 0;
end
else
case (rdwr) // synthesis parallel_case full_case
2'd1: begin
// Write data
if (!full)
begin
entries <= entries + 1;
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
end
end // 2'd1
2'd2: begin
// Read data
if (!empty)
begin
entries <= entries - 1;
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end
end // 2'd2
2'd3: begin
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end // 2'd3
default: begin
end // default
endcase // rdwr
end
always @(posedge clk)
begin
//Write data
if (wr & !full)
case (wr_address) // synthesis parallel_case full_case
1'd0: begin
entry_0 <= wr_data;
end // 1'd0
1'd1: begin
entry_1 <= wr_data;
end // 1'd1
default: begin
end // default
endcase // wr_address
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_sdram_controller_0 (
// inputs:
az_addr,
az_be_n,
az_cs,
az_data,
az_rd_n,
az_wr_n,
clk,
reset_n,
// outputs:
za_data,
za_valid,
za_waitrequest,
zs_addr,
zs_ba,
zs_cas_n,
zs_cke,
zs_cs_n,
zs_dq,
zs_dqm,
zs_ras_n,
zs_we_n
)
;
output [ 15: 0] za_data;
output za_valid;
output za_waitrequest;
output [ 11: 0] zs_addr;
output [ 1: 0] zs_ba;
output zs_cas_n;
output zs_cke;
output zs_cs_n;
inout [ 15: 0] zs_dq;
output [ 1: 0] zs_dqm;
output zs_ras_n;
output zs_we_n;
input [ 21: 0] az_addr;
input [ 1: 0] az_be_n;
input az_cs;
input [ 15: 0] az_data;
input az_rd_n;
input az_wr_n;
input clk;
input reset_n;
wire [ 23: 0] CODE;
reg ack_refresh_request;
reg [ 21: 0] active_addr;
wire [ 1: 0] active_bank;
reg active_cs_n;
reg [ 15: 0] active_data;
reg [ 1: 0] active_dqm;
reg active_rnw;
wire almost_empty;
wire almost_full;
wire bank_match;
wire [ 7: 0] cas_addr;
wire clk_en;
wire [ 3: 0] cmd_all;
wire [ 2: 0] cmd_code;
wire cs_n;
wire csn_decode;
wire csn_match;
wire [ 21: 0] f_addr;
wire [ 1: 0] f_bank;
wire f_cs_n;
wire [ 15: 0] f_data;
wire [ 1: 0] f_dqm;
wire f_empty;
reg f_pop;
wire f_rnw;
wire f_select;
wire [ 40: 0] fifo_read_data;
reg [ 11: 0] i_addr;
reg [ 3: 0] i_cmd;
reg [ 2: 0] i_count;
reg [ 2: 0] i_next;
reg [ 2: 0] i_refs;
reg [ 2: 0] i_state;
reg init_done;
reg [ 11: 0] m_addr /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 1: 0] m_bank /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 3: 0] m_cmd /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 2: 0] m_count;
reg [ 15: 0] m_data /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON ; FAST_OUTPUT_ENABLE_REGISTER=ON" */;
reg [ 1: 0] m_dqm /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 8: 0] m_next;
reg [ 8: 0] m_state;
reg oe /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_ENABLE_REGISTER=ON" */;
wire pending;
wire rd_strobe;
reg [ 1: 0] rd_valid;
reg [ 12: 0] refresh_counter;
reg refresh_request;
wire rnw_match;
wire row_match;
wire [ 23: 0] txt_code;
reg za_cannotrefresh;
reg [ 15: 0] za_data /* synthesis ALTERA_ATTRIBUTE = "FAST_INPUT_REGISTER=ON" */;
reg za_valid;
wire za_waitrequest;
wire [ 11: 0] zs_addr;
wire [ 1: 0] zs_ba;
wire zs_cas_n;
wire zs_cke;
wire zs_cs_n;
wire [ 15: 0] zs_dq;
wire [ 1: 0] zs_dqm;
wire zs_ras_n;
wire zs_we_n;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign {zs_cs_n, zs_ras_n, zs_cas_n, zs_we_n} = m_cmd;
assign zs_addr = m_addr;
assign zs_cke = clk_en;
assign zs_dq = oe?m_data:{16{1'bz}};
assign zs_dqm = m_dqm;
assign zs_ba = m_bank;
assign f_select = f_pop & pending;
assign f_cs_n = 1'b0;
assign cs_n = f_select ? f_cs_n : active_cs_n;
assign csn_decode = cs_n;
assign {f_rnw, f_addr, f_dqm, f_data} = fifo_read_data;
NIOS_sdram_controller_0_input_efifo_module the_NIOS_sdram_controller_0_input_efifo_module
(
.almost_empty (almost_empty),
.almost_full (almost_full),
.clk (clk),
.empty (f_empty),
.full (za_waitrequest),
.rd (f_select),
.rd_data (fifo_read_data),
.reset_n (reset_n),
.wr ((~az_wr_n | ~az_rd_n) & !za_waitrequest),
.wr_data ({az_wr_n, az_addr, az_wr_n ? 2'b0 : az_be_n, az_data})
);
assign f_bank = {f_addr[21],f_addr[8]};
// Refresh/init counter.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
refresh_counter <= 8000;
else if (refresh_counter == 0)
refresh_counter <= 1249;
else
refresh_counter <= refresh_counter - 1'b1;
end
// Refresh request signal.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
refresh_request <= 0;
else if (1)
refresh_request <= ((refresh_counter == 0) | refresh_request) & ~ack_refresh_request & init_done;
end
// Generate an Interrupt if two ref_reqs occur before one ack_refresh_request
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_cannotrefresh <= 0;
else if (1)
za_cannotrefresh <= (refresh_counter == 0) & refresh_request;
end
// Initialization-done flag.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
init_done <= 0;
else if (1)
init_done <= init_done | (i_state == 3'b101);
end
// **** Init FSM ****
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
i_state <= 3'b000;
i_next <= 3'b000;
i_cmd <= 4'b1111;
i_addr <= {12{1'b1}};
i_count <= {3{1'b0}};
end
else
begin
i_addr <= {12{1'b1}};
case (i_state) // synthesis parallel_case full_case
3'b000: begin
i_cmd <= 4'b1111;
i_refs <= 3'b0;
//Wait for refresh count-down after reset
if (refresh_counter == 0)
i_state <= 3'b001;
end // 3'b000
3'b001: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h2};
i_count <= 1;
i_next <= 3'b010;
end // 3'b001
3'b010: begin
i_cmd <= {{1{1'b0}},3'h1};
i_refs <= i_refs + 1'b1;
i_state <= 3'b011;
i_count <= 5;
// Count up init_refresh_commands
if (i_refs == 3'h1)
i_next <= 3'b111;
else
i_next <= 3'b010;
end // 3'b010
3'b011: begin
i_cmd <= {{1{1'b0}},3'h7};
//WAIT til safe to Proceed...
if (i_count > 1)
i_count <= i_count - 1'b1;
else
i_state <= i_next;
end // 3'b011
3'b101: begin
i_state <= 3'b101;
end // 3'b101
3'b111: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h0};
i_addr <= {{2{1'b0}},1'b0,2'b00,3'h2,4'h0};
i_count <= 3;
i_next <= 3'b101;
end // 3'b111
default: begin
i_state <= 3'b000;
end // default
endcase // i_state
end
end
assign active_bank = {active_addr[21],active_addr[8]};
assign csn_match = active_cs_n == f_cs_n;
assign rnw_match = active_rnw == f_rnw;
assign bank_match = active_bank == f_bank;
assign row_match = {active_addr[20 : 9]} == {f_addr[20 : 9]};
assign pending = csn_match && rnw_match && bank_match && row_match && !f_empty;
assign cas_addr = f_select ? { {4{1'b0}},f_addr[7 : 0] } : { {4{1'b0}},active_addr[7 : 0] };
// **** Main FSM ****
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= 4'b1111;
m_bank <= 2'b00;
m_addr <= 12'b000000000000;
m_data <= 16'b0000000000000000;
m_dqm <= 2'b00;
m_count <= 3'b000;
ack_refresh_request <= 1'b0;
f_pop <= 1'b0;
oe <= 1'b0;
end
else
begin
f_pop <= 1'b0;
oe <= 1'b0;
case (m_state) // synthesis parallel_case full_case
9'b000000001: begin
//Wait for init-fsm to be done...
if (init_done)
begin
//Hold bus if another cycle ended to arf.
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= 4'b1111;
ack_refresh_request <= 1'b0;
//Wait for a read/write request.
if (refresh_request)
begin
m_state <= 9'b001000000;
m_next <= 9'b010000000;
m_count <= 1;
active_cs_n <= 1'b1;
end
else if (!f_empty)
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
m_state <= 9'b000000010;
end
end
else
begin
m_addr <= i_addr;
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= i_cmd;
end
end // 9'b000000001
9'b000000010: begin
m_state <= 9'b000000100;
m_cmd <= {csn_decode,3'h3};
m_bank <= active_bank;
m_addr <= active_addr[20 : 9];
m_data <= active_data;
m_dqm <= active_dqm;
m_count <= 2;
m_next <= active_rnw ? 9'b000001000 : 9'b000010000;
end // 9'b000000010
9'b000000100: begin
// precharge all if arf, else precharge csn_decode
if (m_next == 9'b010000000)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
m_state <= m_next;
end // 9'b000000100
9'b000001000: begin
m_cmd <= {csn_decode,3'h5};
m_bank <= f_select ? f_bank : active_bank;
m_dqm <= f_select ? f_dqm : active_dqm;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 1;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end RD spin cycle if fifo mt
if (~pending & f_pop)
m_cmd <= {csn_decode,3'h7};
m_state <= 9'b100000000;
end
end // 9'b000001000
9'b000010000: begin
m_cmd <= {csn_decode,3'h4};
oe <= 1'b1;
m_data <= f_select ? f_data : active_data;
m_dqm <= f_select ? f_dqm : active_dqm;
m_bank <= f_select ? f_bank : active_bank;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 2;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end WR spin cycle if fifo empty
if (~pending & f_pop)
begin
m_cmd <= {csn_decode,3'h7};
oe <= 1'b0;
end
m_state <= 9'b100000000;
end
end // 9'b000010000
9'b000100000: begin
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
begin
m_state <= 9'b001000000;
m_count <= 1;
end
end // 9'b000100000
9'b001000000: begin
m_state <= 9'b000000100;
m_addr <= {12{1'b1}};
// precharge all if arf, else precharge csn_decode
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h2};
else
m_cmd <= {csn_decode,3'h2};
end // 9'b001000000
9'b010000000: begin
ack_refresh_request <= 1'b1;
m_state <= 9'b000000100;
m_cmd <= {{1{1'b0}},3'h1};
m_count <= 5;
m_next <= 9'b000000001;
end // 9'b010000000
9'b100000000: begin
m_cmd <= {csn_decode,3'h7};
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 1;
end
else //wait for fifo to have contents
if (!f_empty)
//Are we 'pending' yet?
if (csn_match && rnw_match && bank_match && row_match)
begin
m_state <= f_rnw ? 9'b000001000 : 9'b000010000;
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
else
begin
m_state <= 9'b000100000;
m_next <= 9'b000000001;
m_count <= 1;
end
end // 9'b100000000
// synthesis translate_off
default: begin
m_state <= m_state;
m_cmd <= 4'b1111;
f_pop <= 1'b0;
oe <= 1'b0;
end // default
// synthesis translate_on
endcase // m_state
end
end
assign rd_strobe = m_cmd[2 : 0] == 3'h5;
//Track RD Req's based on cas_latency w/shift reg
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rd_valid <= {2{1'b0}};
else
rd_valid <= (rd_valid << 1) | { {1{1'b0}}, rd_strobe };
end
// Register dq data.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_data <= 0;
else
za_data <= zs_dq;
end
// Delay za_valid to match registered data.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_valid <= 0;
else if (1)
za_valid <= rd_valid[1];
end
assign cmd_code = m_cmd[2 : 0];
assign cmd_all = m_cmd;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
initial
begin
$write("\n");
$write("This reference design requires a vendor simulation model.\n");
$write("To simulate accesses to SDRAM, you must:\n");
$write(" - Download the vendor model\n");
$write(" - Install the model in the system_sim directory\n");
$write(" - `include the vendor model in the the top-level system file,\n");
$write(" - Instantiate sdram simulation models and wire them to testbench signals\n");
$write(" - Be aware that you may have to disable some timing checks in the vendor model\n");
$write(" (because this simulation is zero-delay based)\n");
$write("\n");
end
assign txt_code = (cmd_code == 3'h0)? 24'h4c4d52 :
(cmd_code == 3'h1)? 24'h415246 :
(cmd_code == 3'h2)? 24'h505245 :
(cmd_code == 3'h3)? 24'h414354 :
(cmd_code == 3'h4)? 24'h205752 :
(cmd_code == 3'h5)? 24'h205244 :
(cmd_code == 3'h6)? 24'h425354 :
(cmd_code == 3'h7)? 24'h4e4f50 :
24'h424144;
assign CODE = &(cmd_all|4'h7) ? 24'h494e48 : txt_code;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
// megafunction wizard: %FIFO%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo_32x64a.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module fifo_32x64a (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "64"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "64"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "6"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x64a.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x64a.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x64a.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x64a.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x64a_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x64a_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x64a_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_32x64a_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND3B_4_V
`define SKY130_FD_SC_LP__NAND3B_4_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog wrapper for nand3b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3b_4 (
Y ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand3b_4 (
Y ,
A_N,
B ,
C
);
output Y ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand3b base (
.Y(Y),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND3B_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFSTP_SYMBOL_V
`define SKY130_FD_SC_HS__SDFSTP_SYMBOL_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdfstp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFSTP_SYMBOL_V
|
// soc_system_hps_0_hps_io.v
// This file was auto-generated from altera_hps_io_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 211
`timescale 1 ps / 1 ps
module soc_system_hps_0_hps_io (
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin, // .oct_rzqin
output wire hps_io_emac1_inst_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_io_qspi_inst_IO0, // .hps_io_qspi_inst_IO0
inout wire hps_io_qspi_inst_IO1, // .hps_io_qspi_inst_IO1
inout wire hps_io_qspi_inst_IO2, // .hps_io_qspi_inst_IO2
inout wire hps_io_qspi_inst_IO3, // .hps_io_qspi_inst_IO3
output wire hps_io_qspi_inst_SS0, // .hps_io_qspi_inst_SS0
output wire hps_io_qspi_inst_CLK, // .hps_io_qspi_inst_CLK
inout wire hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
inout wire hps_io_usb1_inst_D0, // .hps_io_usb1_inst_D0
inout wire hps_io_usb1_inst_D1, // .hps_io_usb1_inst_D1
inout wire hps_io_usb1_inst_D2, // .hps_io_usb1_inst_D2
inout wire hps_io_usb1_inst_D3, // .hps_io_usb1_inst_D3
inout wire hps_io_usb1_inst_D4, // .hps_io_usb1_inst_D4
inout wire hps_io_usb1_inst_D5, // .hps_io_usb1_inst_D5
inout wire hps_io_usb1_inst_D6, // .hps_io_usb1_inst_D6
inout wire hps_io_usb1_inst_D7, // .hps_io_usb1_inst_D7
input wire hps_io_usb1_inst_CLK, // .hps_io_usb1_inst_CLK
output wire hps_io_usb1_inst_STP, // .hps_io_usb1_inst_STP
input wire hps_io_usb1_inst_DIR, // .hps_io_usb1_inst_DIR
input wire hps_io_usb1_inst_NXT, // .hps_io_usb1_inst_NXT
output wire hps_io_spim1_inst_CLK, // .hps_io_spim1_inst_CLK
output wire hps_io_spim1_inst_MOSI, // .hps_io_spim1_inst_MOSI
input wire hps_io_spim1_inst_MISO, // .hps_io_spim1_inst_MISO
output wire hps_io_spim1_inst_SS0, // .hps_io_spim1_inst_SS0
input wire hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_io_i2c0_inst_SDA, // .hps_io_i2c0_inst_SDA
inout wire hps_io_i2c0_inst_SCL, // .hps_io_i2c0_inst_SCL
inout wire hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire hps_io_gpio_inst_GPIO09, // .hps_io_gpio_inst_GPIO09
inout wire hps_io_gpio_inst_GPIO35, // .hps_io_gpio_inst_GPIO35
inout wire hps_io_gpio_inst_GPIO40, // .hps_io_gpio_inst_GPIO40
inout wire hps_io_gpio_inst_GPIO48, // .hps_io_gpio_inst_GPIO48
inout wire hps_io_gpio_inst_GPIO53, // .hps_io_gpio_inst_GPIO53
inout wire hps_io_gpio_inst_GPIO54, // .hps_io_gpio_inst_GPIO54
inout wire hps_io_gpio_inst_GPIO61 // .hps_io_gpio_inst_GPIO61
);
soc_system_hps_0_hps_io_border border (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_qspi_inst_IO0 (hps_io_qspi_inst_IO0), // .hps_io_qspi_inst_IO0
.hps_io_qspi_inst_IO1 (hps_io_qspi_inst_IO1), // .hps_io_qspi_inst_IO1
.hps_io_qspi_inst_IO2 (hps_io_qspi_inst_IO2), // .hps_io_qspi_inst_IO2
.hps_io_qspi_inst_IO3 (hps_io_qspi_inst_IO3), // .hps_io_qspi_inst_IO3
.hps_io_qspi_inst_SS0 (hps_io_qspi_inst_SS0), // .hps_io_qspi_inst_SS0
.hps_io_qspi_inst_CLK (hps_io_qspi_inst_CLK), // .hps_io_qspi_inst_CLK
.hps_io_sdio_inst_CMD (hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_usb1_inst_D0 (hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_usb1_inst_D1 (hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_usb1_inst_D2 (hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_usb1_inst_D3 (hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_usb1_inst_D4 (hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_usb1_inst_D5 (hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_usb1_inst_D6 (hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_usb1_inst_D7 (hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_usb1_inst_CLK (hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_usb1_inst_STP (hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_usb1_inst_DIR (hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_usb1_inst_NXT (hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_spim1_inst_CLK (hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_spim1_inst_MOSI (hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_spim1_inst_MISO (hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_spim1_inst_SS0 (hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_uart0_inst_RX (hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c0_inst_SDA (hps_io_i2c0_inst_SDA), // .hps_io_i2c0_inst_SDA
.hps_io_i2c0_inst_SCL (hps_io_i2c0_inst_SCL), // .hps_io_i2c0_inst_SCL
.hps_io_i2c1_inst_SDA (hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_gpio_inst_GPIO09 (hps_io_gpio_inst_GPIO09), // .hps_io_gpio_inst_GPIO09
.hps_io_gpio_inst_GPIO35 (hps_io_gpio_inst_GPIO35), // .hps_io_gpio_inst_GPIO35
.hps_io_gpio_inst_GPIO40 (hps_io_gpio_inst_GPIO40), // .hps_io_gpio_inst_GPIO40
.hps_io_gpio_inst_GPIO48 (hps_io_gpio_inst_GPIO48), // .hps_io_gpio_inst_GPIO48
.hps_io_gpio_inst_GPIO53 (hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.hps_io_gpio_inst_GPIO54 (hps_io_gpio_inst_GPIO54), // .hps_io_gpio_inst_GPIO54
.hps_io_gpio_inst_GPIO61 (hps_io_gpio_inst_GPIO61) // .hps_io_gpio_inst_GPIO61
);
endmodule
|
/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* DMA INTERFACE */
/*---------------------------------------------------------------------------*/
/* Test the DMA interface: */
/* - Check Memory RD/WR features. */
/* */
/* Author(s): */
/* - Olivier Girard, [email protected] */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev$ */
/* $LastChangedBy$ */
/* $LastChangedDate$ */
/*===========================================================================*/
`define VERY_LONG_TIMEOUT
parameter TMPL8B_CNTRL1 = 16'h0090;
parameter TMPL8B_CNTRL2 = 16'h0091;
parameter TMPL8B_CNTRL3 = 16'h0092;
parameter TMPL8B_CNTRL4 = 16'h0093;
integer jj;
integer inst_number_old;
integer inst_number_diff;
initial
begin
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
`ifdef DMA_IF_EN
// Disable automatic DMA verification
#10;
dma_verif_on = 0;
repeat(30) @(posedge mclk);
stimulus_done = 0;
//-------------------------------------------------------------
// LOW/HIGH PRIORITY DMA
//-------------------------------------------------------------
for ( jj=0; jj<=1; jj=jj+1)
begin
if (jj==0)
begin
dma_priority=0;
$display("\n\n---------------------------------------");
$display(" LOW Priority 8B DMA transfer tests");
$display("---------------------------------------\n");
end
else
begin
dma_priority=1;
$display("\n\n---------------------------------------");
$display(" HIGH Priority 8B DMA transfer tests");
$display("---------------------------------------\n");
end
// RD/WR ACCESS: Program memory (8b)
//--------------------------------------------------------
$display("MARCH-X: Program memory 8b:");
// Wait random time until MARCH-X starts
dma_rand_wait = $urandom_range(1,40);
repeat(dma_rand_wait) @(posedge mclk);
// Run MARCH-X on program memory
// (make sure we don't overwrite firmware, i.e. the first 48 bytes)
inst_number_old=inst_number;
march_x_8b(('h10000-`PMEM_SIZE+48), 16'hfffe, 1);
inst_number_diff=inst_number-inst_number_old;
if ( dma_priority & (inst_number_diff>2)) tb_error("CPU is not stopped in high priority mode");
if (~dma_priority & (inst_number_diff<500)) tb_error("CPU is stopped in low priority mode");
// RD/WR ACCESS: Data memory (8b)
//--------------------------------------------------------
$display("\n\nMARCH-X: Data memory 8b:");
// Wait random time until MARCH-X starts
dma_rand_wait = $urandom_range(1,40);
repeat(dma_rand_wait) @(posedge mclk);
// Run MARCH-X on data memory
// (make sure we don't overwrite firmware data, i.e. DMEM_200)
inst_number_old=inst_number;
march_x_8b((`PER_SIZE+2), (`PER_SIZE+`DMEM_SIZE-2), 1);
inst_number_diff=inst_number-inst_number_old;
if ( dma_priority & (inst_number_diff>2)) tb_error("CPU is not stopped in high priority mode");
if (~dma_priority & (inst_number_diff<100)) tb_error("CPU is stopped in low priority mode");
// RD/WR ACCESS: Peripheral memory (8b)
//--------------------------------------------------------
$display("\n\nMARCH-X: Peripheral memory 8b ...");
// Wait random time until MARCH-X starts
dma_rand_wait = $urandom_range(1,40);
repeat(dma_rand_wait) @(posedge mclk);
// Run MARCH-X on 8B template peripheral
inst_number_old=inst_number;
repeat(100) march_x_8b(TMPL8B_CNTRL1, TMPL8B_CNTRL4, 0);
inst_number_diff=inst_number-inst_number_old;
if ( dma_priority & (inst_number_diff>2)) tb_error("CPU is not stopped in high priority mode");
if (~dma_priority & (inst_number_diff<500)) tb_error("CPU is stopped in low priority mode");
end
// End of test
//--------------------------------------------------
$display("\n");
repeat(3000) @(posedge mclk);
dma_write_8b(16'h0000-`PMEM_SIZE, 16'h0001, 1'b0);
@(r15==16'h2000);
if (r10 !== mem200) tb_error("Final Increment counter missmatch... firmware execution failed");
stimulus_done = 1;
`else
tb_skip_finish("| (DMA interface support not included) |");
`endif
end
//-------------------------------------------------------------
// Make sure firmware executes properly during the whole test
//-------------------------------------------------------------
// Make sure there is the right amount of clock cycle between the counter increments
// (low-priority mode only)
integer mclk_cnt;
always @(posedge mclk) mclk_cnt=mclk_cnt+1;
// Check counter increment
initial
begin
// Wait for firmware to start
@(r15==16'h1000);
// Synchronize with first increment
@(mem200); @(negedge mclk);
mclk_cnt=0;
forever
begin
// When register R10 is incremented, make sure DMEM_200 = R10-1
@(r10); @(negedge mclk);
if (r10 !== (mem200+1)) tb_error("R10 Increment counter missmatch... firmware execution failed");
if (~dma_priority & ((mclk_cnt < 4) | (mclk_cnt > 10))) tb_error("DMEM_200 -> R10 exec time error... firmware execution failed");
mclk_cnt=0;
// When DMEM_200 is incremented, make sure DMEM_200 = R10
@(mem200); @(negedge mclk);
if (r10 !== mem200) tb_error("DMEM_200 Increment counter missmatch... firmware execution failed");
if (~dma_priority & ((mclk_cnt < 3) | (mclk_cnt > 9))) tb_error("R10 -> DMEM_200 exec time error... firmware execution failed");
mclk_cnt=0;
end
end
//------------------------------------------------------
// MARCH-X functions
//------------------------------------------------------
task march_x_8b;
input [15:0] addr_start;
input [15:0] addr_end;
input verbose;
integer ii;
begin
// MARCH X : down (w0); up (r0,w1); down (r1,w0); up (r0)
if (verbose) $display(" - down(w0) ... ");
for ( ii=addr_end; ii >= addr_start; ii=ii-1)
begin
dma_write_8b(ii, 8'h00, 1'b0);
end
if (verbose) $display(" - up(r0,w1) ... ");
for ( ii=addr_start; ii <= addr_end; ii=ii+1)
begin
dma_read_8b(ii, 8'h00, 1'b0);
dma_write_8b(ii, 8'hff, 1'b0);
end
if (verbose) $display(" - down(r1,w0) ... ");
for ( ii=addr_end; ii >= addr_start; ii=ii-1)
begin
dma_read_8b(ii, 8'hff, 1'b0);
dma_write_8b(ii, 8'h00, 1'b0);
end
if (verbose) $display(" - up(r0) ... ");
for ( ii=addr_start; ii <= addr_end; ii=ii+1)
begin
dma_read_8b(ii, 8'h00, 1'b0);
end
end
endtask // march_x_8b
|
//////////////////////////////////////////////////////////////////////
//// ////
//// MP3 demo SRAM init ////
//// ////
//// This file is part of the MP3 demo application ////
//// http://www.opencores.org/cores/or1k/mp3/ ////
//// ////
//// Description ////
//// Optional SRAM content initialization (for debugging ////
//// purposes) ////
//// ////
//// To Do: ////
//// - nothing really ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: sram_init.v,v $
// Revision 1.1 2002/03/28 19:59:55 lampret
// Added bench directory
//
// Revision 1.1.1.1 2001/11/04 18:51:07 lampret
// First import.
//
//
`ifdef SRAM_INIT
module sram_init;
reg [7:0] mem [135005:0];
reg [31:0] tmp;
task init_sram;
integer i;
begin
#1;
$display("Initializing SRAM ...");
$readmemh("../src/flash.in", mem);
for (i=0; i < 135000; i=i+4) begin
xess_top.Sram_r1.mem_array[i/4] = mem[i];
xess_top.Sram_r0.mem_array[i/4] = mem[i+1];
xess_top.Sram_l1.mem_array[i/4] = mem[i+2];
xess_top.Sram_l0.mem_array[i/4] = mem[i+3];
end
`ifdef UNUSED
for (i=0; i < 135000; i=i+4) begin
tmp[31:24] = xess_top.Sram_r1.temp_array[i/4];
tmp[23:16] = xess_top.Sram_r0.temp_array[i/4];
tmp[15:8] = xess_top.Sram_l1.temp_array[i/4];
tmp[7:0] = xess_top.Sram_l0.temp_array[i/4];
$display("%h %h", i, tmp);
tmp[31:24] = xess_top.Sram_r1.mem_array[i/4];
tmp[23:16] = xess_top.Sram_r0.mem_array[i/4];
tmp[15:8] = xess_top.Sram_l1.mem_array[i/4];
tmp[7:0] = xess_top.Sram_l0.mem_array[i/4];
$display("%h %h", i, tmp);
end
`endif
end
endtask
endmodule
`endif
|
// megafunction wizard: %ALTPLL%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll_125.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Internal Build 209b 09/24/2009 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module pll_125 (
inclk0,
c0);
input inclk0;
output c0;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "2"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "350.000"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "125.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_125.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk6 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk7 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk8 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk9 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: USING_FBMIMICBIDIR_PORT STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "10"
// Retrieval info: USED_PORT: @clk 0 0 10 0 OUTPUT_CLK_EXT VCC "@clk[9..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_125.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_125.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_125.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_125.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_125.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_125_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_125_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_125_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_125_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/*
* c4puter northbridge - DRAM controller to Wishbone glue
* Copyright (C) 2017 Chris Pavlina
*
* Wishbone to DDR3 glue
* from MicroBlaze MCS to DDR3 glue
* (C) Copyright 2012 Silicon On Inspiration
* www.sioi.com.au
* 86 Longueville Road
* Lane Cove 2066
* New South Wales
* AUSTRALIA
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
* You should have received a copy of the GNU Lesser General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module drac_wb_adapter (
// DRAC interface
output drac_srd_o,
output drac_swr_o,
output [33:5] drac_sa_o,
output [255:0] drac_swdat_o,
output [31:0] drac_smsk_o,
input [255:0] drac_srdat_i,
input drac_srdy_i,
input clk150,
// Wishbone slave
input [35:0] wb_adr_i,
input wb_we_i,
input [3:0] wb_sel_i,
input wb_stb_i,
input wb_cyc_i,
input [31:0] wb_dat_i,
output [31:0] wb_dat_o,
output wb_ack_o,
input clk75,
input reset
);
reg [31:0] rdat;
reg [255:0] wdat;
reg [31:0] msk;
reg [33:2] addr;
reg rdy1 = 1'b0;
reg rdy2 = 1'b0;
reg read = 1'b0;
reg write = 1'b0;
reg wb_stb_delay = 1'b0;
always @(posedge clk75) begin
if (wb_stb_i && !wb_stb_delay && wb_we_i) begin
case (wb_adr_i[2:0])
3'b000: wdat[31:0] <= wb_dat_i;
3'b001: wdat[63:32] <= wb_dat_i;
3'b010: wdat[95:64] <= wb_dat_i;
3'b011: wdat[127:96] <= wb_dat_i;
3'b100: wdat[159:128] <= wb_dat_i;
3'b101: wdat[191:160] <= wb_dat_i;
3'b110: wdat[223:192] <= wb_dat_i;
3'b111: wdat[255:224] <= wb_dat_i;
endcase
case (wb_adr_i[2:0])
3'b000: msk <= 32'hFFFFFFF0;
3'b001: msk <= 32'hFFFFFF0F;
3'b010: msk <= 32'hFFFFF0FF;
3'b011: msk <= 32'hFFFF0FFF;
3'b100: msk <= 32'hFFF0FFFF;
3'b101: msk <= 32'hFF0FFFFF;
3'b110: msk <= 32'hF0FFFFFF;
3'b111: msk <= 32'h0FFFFFFF;
endcase
end
if (wb_stb_i && !wb_stb_delay) begin
addr[33:2] <= wb_adr_i[31:0];
end
end
always @(posedge clk75 or posedge reset) begin
if (reset) begin
read <= 1'b0;
write <= 1'b0;
rdy2 <= 1'b0;
wb_stb_delay <= 1'b0;
end else begin
wb_stb_delay <= wb_stb_i;
if (wb_stb_i && !wb_stb_delay && !wb_we_i) begin
read <= 1'b1;
end else if (wb_stb_i && !wb_stb_delay && wb_we_i) begin
write <= 1'b1;
end
if (rdy1) begin
read <= 1'b0;
write <= 1'b0;
rdy2 <= 1'b1;
end
if (rdy2) begin
rdy2 <= 1'b0;
end
end
end
always @(posedge clk150 or posedge reset) begin
if (reset) begin
rdy1 <= 1'b0;
end else begin
if (drac_srdy_i) begin
rdy1 <= 1'b1;
end
if (rdy2) begin
rdy1 <= 1'b0;
end
if (drac_srdy_i) case (addr[4:2])
3'b000: rdat <= drac_srdat_i[31:0];
3'b001: rdat <= drac_srdat_i[63:32];
3'b010: rdat <= drac_srdat_i[95:64];
3'b011: rdat <= drac_srdat_i[127:96];
3'b100: rdat <= drac_srdat_i[159:128];
3'b101: rdat <= drac_srdat_i[191:160];
3'b110: rdat <= drac_srdat_i[223:192];
3'b111: rdat <= drac_srdat_i[255:224];
endcase
end
end
assign wb_dat_o = rdat;
assign wb_ack_o = rdy2;
assign drac_srd_o = read;
assign drac_swr_o = write;
assign drac_swdat_o = wdat;
assign drac_smsk_o = msk;
assign drac_sa_o = addr[33:5];
endmodule
|
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Based on Sauraen VHDL version of OPN/OPN2, which is based on die shots.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-1-2017
*/
module jt12_op(
input rst,
input clk,
input clk_en /* synthesis direct_enable */,
input [9:0] pg_phase_VIII,
input [9:0] eg_atten_IX, // output from envelope generator
input [2:0] fb_II, // voice feedback
input xuse_prevprev1,
input xuse_prev2,
input xuse_internal,
input yuse_prev1,
input yuse_prev2,
input yuse_internal,
input test_214,
input s1_enters,
input s2_enters,
input s3_enters,
input s4_enters,
input zero,
output signed [ 8:0] op_result,
output signed [13:0] full_result
);
parameter num_ch = 6;
/* enters exits
S1 S2
S3 S4
S2 S1
S4 S3
*/
reg [13:0] op_result_internal, op_XII;
reg [11:0] atten_internal_IX;
assign op_result = op_result_internal[13:5];
assign full_result = op_result_internal;
reg signbit_IX, signbit_X, signbit_XI;
reg [11:0] totalatten_X;
wire [13:0] prev1, prevprev1, prev2;
reg [13:0] prev1_din, prevprev1_din, prev2_din;
always @(*)
if( num_ch==3 ) begin
prev1_din = s1_enters ? op_result_internal : prev1;
prevprev1_din = s3_enters ? op_result_internal : prevprev1;
prev2_din = s2_enters ? op_result_internal : prev2;
end else begin // 6 channels
prev1_din = s2_enters ? op_result_internal : prev1;
prevprev1_din = s2_enters ? prev1 : prevprev1;
prev2_din = s1_enters ? op_result_internal : prev2;
end
jt12_sh #( .width(14), .stages(num_ch)) prev1_buffer(
// .rst ( rst ),
.clk ( clk ),
.clk_en ( clk_en ),
.din ( prev1_din ),
.drop ( prev1 )
);
jt12_sh #( .width(14), .stages(num_ch)) prevprev1_buffer(
// .rst ( rst ),
.clk ( clk ),
.clk_en ( clk_en ),
.din ( prevprev1_din ),
.drop ( prevprev1 )
);
jt12_sh #( .width(14), .stages(num_ch)) prev2_buffer(
// .rst ( rst ),
.clk ( clk ),
.clk_en ( clk_en ),
.din ( prev2_din ),
.drop ( prev2 )
);
reg [10:0] subtresult;
reg [12:0] shifter, shifter_2, shifter_3;
// REGISTER/CYCLE 1
// Creation of phase modulation (FM) feedback signal, before shifting
reg [13:0] x, y;
reg [14:0] xs, ys, pm_preshift_II;
reg s1_II;
always @(*) begin
casez( {xuse_prevprev1, xuse_prev2, xuse_internal })
3'b1??: x = prevprev1;
3'b01?: x = prev2;
3'b001: x = op_result_internal;
default: x = 14'd0;
endcase
casez( {yuse_prev1, yuse_prev2, yuse_internal })
3'b1??: y = prev1;
3'b01?: y = prev2;
3'b001: y = op_result_internal;
default: y = 14'd0;
endcase
xs = { x[13], x }; // sign-extend
ys = { y[13], y }; // sign-extend
end
always @(posedge clk) if( clk_en ) begin
pm_preshift_II <= xs + ys; // carry is discarded
s1_II <= s1_enters;
end
/* REGISTER/CYCLE 2-7 (also YM2612 extra cycles 1-6)
Shifting of FM feedback signal, adding phase from PG to FM phase
In YM2203, phasemod_II is not registered at all, it is latched on the first edge
in add_pg_phase and the second edge is the output of add_pg_phase. In the YM2612, there
are 6 cycles worth of registers between the generated (non-registered) phasemod_II signal
and the input to add_pg_phase. */
reg [9:0] phasemod_II;
wire [9:0] phasemod_VIII;
always @(*) begin
// Shift FM feedback signal
if (!s1_II ) // Not S1
phasemod_II = pm_preshift_II[10:1]; // Bit 0 of pm_preshift_II is never used
else // S1
case( fb_II )
3'd0: phasemod_II = 10'd0;
3'd1: phasemod_II = { {4{pm_preshift_II[14]}}, pm_preshift_II[14:9] };
3'd2: phasemod_II = { {3{pm_preshift_II[14]}}, pm_preshift_II[14:8] };
3'd3: phasemod_II = { {2{pm_preshift_II[14]}}, pm_preshift_II[14:7] };
3'd4: phasemod_II = { pm_preshift_II[14], pm_preshift_II[14:6] };
3'd5: phasemod_II = pm_preshift_II[14:5];
3'd6: phasemod_II = pm_preshift_II[13:4];
3'd7: phasemod_II = pm_preshift_II[12:3];
endcase
end
// REGISTER/CYCLE 2-7
//generate
// if( num_ch==6 )
jt12_sh #( .width(10), .stages(6)) phasemod_sh(
.clk ( clk ),
.clk_en ( clk_en),
.din ( phasemod_II ),
.drop ( phasemod_VIII )
);
// else begin
// assign phasemod_VIII = phasemod_II;
// end
// endgenerate
// REGISTER/CYCLE 8
reg [ 9:0] phase;
// Sets the maximum number of fanouts for a register or combinational
// cell. The Quartus II software will replicate the cell and split
// the fanouts among the duplicates until the fanout of each cell
// is below the maximum.
reg [ 7:0] aux_VIII;
always @(*) begin
phase = phasemod_VIII + pg_phase_VIII;
aux_VIII= phase[7:0] ^ {8{~phase[8]}};
end
always @(posedge clk) if( clk_en ) begin
signbit_IX <= phase[9];
end
wire [11:0] logsin_IX;
jt12_logsin u_logsin (
.clk ( clk ),
.clk_en ( clk_en ),
.addr ( aux_VIII[7:0] ),
.logsin ( logsin_IX )
);
// REGISTER/CYCLE 9
// Sine table
// Main sine table body
always @(*) begin
subtresult = eg_atten_IX + logsin_IX[11:2];
atten_internal_IX = { subtresult[9:0], logsin_IX[1:0] } | {12{subtresult[10]}};
end
wire [9:0] mantissa_X;
reg [9:0] mantissa_XI;
reg [3:0] exponent_X, exponent_XI;
jt12_exprom u_exprom(
.clk ( clk ),
.clk_en ( clk_en ),
.addr ( atten_internal_IX[7:0] ),
.exp ( mantissa_X )
);
always @(posedge clk) if( clk_en ) begin
exponent_X <= atten_internal_IX[11:8];
signbit_X <= signbit_IX;
end
always @(posedge clk) if( clk_en ) begin
mantissa_XI <= mantissa_X;
exponent_XI <= exponent_X;
signbit_XI <= signbit_X;
end
// REGISTER/CYCLE 11
// Introduce test bit as MSB, 2's complement & Carry-out discarded
always @(*) begin
// Floating-point to integer, and incorporating sign bit
// Two-stage shifting of mantissa_XI by exponent_XI
shifter = { 3'b001, mantissa_XI };
case( ~exponent_XI[1:0] )
2'b00: shifter_2 = { 1'b0, shifter[12:1] }; // LSB discarded
2'b01: shifter_2 = shifter;
2'b10: shifter_2 = { shifter[11:0], 1'b0 };
2'b11: shifter_2 = { shifter[10:0], 2'b0 };
endcase
case( ~exponent_XI[3:2] )
2'b00: shifter_3 = {12'b0, shifter_2[12] };
2'b01: shifter_3 = { 8'b0, shifter_2[12:8] };
2'b10: shifter_3 = { 4'b0, shifter_2[12:4] };
2'b11: shifter_3 = shifter_2;
endcase
end
always @(posedge clk) if( clk_en ) begin
// REGISTER CYCLE 11
op_XII <= ({ test_214, shifter_3 } ^ {14{signbit_XI}}) + {13'd0,signbit_XI};
// REGISTER CYCLE 12
// Extra register, take output after here
op_result_internal <= op_XII;
end
`ifdef SIMULATION
reg signed [13:0] op_sep2_0;
reg signed [13:0] op_sep4_0;
reg signed [13:0] op_sep5_0;
reg signed [13:0] op_sep6_0;
reg signed [13:0] op_sep0_0;
reg signed [13:0] op_sep1_0;
reg signed [13:0] op_sep2_1;
reg signed [13:0] op_sep4_1;
reg signed [13:0] op_sep5_1;
reg signed [13:0] op_sep6_1;
reg signed [13:0] op_sep0_1;
reg signed [13:0] op_sep1_1;
reg signed [13:0] op_sep2_2;
reg signed [13:0] op_sep4_2;
reg signed [13:0] op_sep5_2;
reg signed [13:0] op_sep6_2;
reg signed [13:0] op_sep0_2;
reg signed [13:0] op_sep1_2;
reg signed [13:0] op_sep2_3;
reg signed [13:0] op_sep4_3;
reg signed [13:0] op_sep5_3;
reg signed [13:0] op_sep6_3;
reg signed [13:0] op_sep0_3;
reg signed [13:0] op_sep1_3;
reg [ 4:0] sepcnt;
always @(posedge clk) if(clk_en) begin
sepcnt <= zero ? 5'd0 : sepcnt+5'd1;
case( (sepcnt+14)%24 )
0: op_sep0_0 <= op_XII;
1: op_sep1_0 <= op_XII;
2: op_sep2_0 <= op_XII;
3: op_sep4_0 <= op_XII;
4: op_sep5_0 <= op_XII;
5: op_sep6_0 <= op_XII;
6: op_sep0_2 <= op_XII;
7: op_sep1_2 <= op_XII;
8: op_sep2_2 <= op_XII;
9: op_sep4_2 <= op_XII;
10: op_sep5_2 <= op_XII;
11: op_sep6_2 <= op_XII;
12: op_sep0_1 <= op_XII;
13: op_sep1_1 <= op_XII;
14: op_sep2_1 <= op_XII;
15: op_sep4_1 <= op_XII;
16: op_sep5_1 <= op_XII;
17: op_sep6_1 <= op_XII;
18: op_sep0_3 <= op_XII;
19: op_sep1_3 <= op_XII;
20: op_sep2_3 <= op_XII;
21: op_sep4_3 <= op_XII;
22: op_sep5_3 <= op_XII;
23: op_sep6_3 <= op_XII;
endcase
end
`endif
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 09:47:57 2016
/////////////////////////////////////////////////////////////
module FPU_Interface2_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, begin_operation,
ack_operation, operation, region_flag, Data_1, Data_2, r_mode,
overflow_flag, underflow_flag, NaN_flag, operation_ready, op_result,
busy );
input [2:0] operation;
input [1:0] region_flag;
input [31:0] Data_1;
input [31:0] Data_2;
input [1:0] r_mode;
output [31:0] op_result;
input clk, rst, begin_operation, ack_operation;
output overflow_flag, underflow_flag, NaN_flag, operation_ready, busy;
wire NaN_reg, ready_add_subt, overflow_flag_addsubt,
underflow_flag_addsubt, FPSENCOS_d_ff1_operation_out,
FPMULT_FSM_selector_C, FPMULT_FSM_selector_A,
FPMULT_FSM_add_overflow_flag, FPMULT_zero_flag, FPADDSUB_OP_FLAG_SFG,
FPADDSUB_SIGN_FLAG_SFG, FPADDSUB_SIGN_FLAG_NRM,
FPADDSUB_SIGN_FLAG_SHT1SHT2, FPADDSUB_ADD_OVRFLW_NRM2,
FPADDSUB_OP_FLAG_SHT2, FPADDSUB_SIGN_FLAG_SHT2,
FPADDSUB_bit_shift_SHT2, FPADDSUB_left_right_SHT2,
FPADDSUB_ADD_OVRFLW_NRM, FPADDSUB_OP_FLAG_SHT1,
FPADDSUB_SIGN_FLAG_SHT1, FPADDSUB_OP_FLAG_EXP, FPADDSUB_SIGN_FLAG_EXP,
FPADDSUB_intAS, FPADDSUB_Shift_reg_FLAGS_7_6,
FPMULT_Exp_module_Overflow_flag_A,
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N1,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N15,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N14,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N13,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N12,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N1,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N0,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N1,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N0,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N1,
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N0,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N13,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N12,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N1,
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N0,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N1,
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0,
n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189,
n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199,
n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209,
n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219,
n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229,
n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239,
n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249,
n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259,
n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269,
n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279,
n1280, n1281, n1282, n1283, n1284, n1285, n1287, n1288, n1289, n1290,
n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300,
n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310,
n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320,
n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330,
n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340,
n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350,
n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360,
n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370,
n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380,
n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390,
n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400,
n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410,
n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420,
n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430,
n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440,
n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450,
n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460,
n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470,
n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1480, n1481,
n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492,
n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502,
n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512,
n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522,
n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532,
n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542,
n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552,
n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562,
n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572,
n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582,
n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592,
n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602,
n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612,
n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621, n1622,
n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632,
n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1642, n1643,
n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653,
n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663,
n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673,
n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683,
n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693,
n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703,
n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713,
n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723,
n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733,
n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743,
n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753,
n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763,
n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773,
n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783,
n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793,
n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803,
n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813,
n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823,
n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833,
n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843,
n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853,
n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863,
n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873,
n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883,
n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893,
n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903,
n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913,
n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923,
n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933,
n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943,
n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953,
n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963,
n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973,
n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983,
n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993,
n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003,
n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013,
n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023,
n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033,
n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043,
n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053,
n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063,
n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073,
n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083,
n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093,
n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103,
n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113,
n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123,
n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133,
n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2143, n2144,
n2145, n2146, n2147, n2148, n2149, n2191, mult_x_312_n77,
mult_x_312_n72, mult_x_312_n71, mult_x_312_n67, mult_x_312_n59,
mult_x_312_n58, mult_x_312_n53, mult_x_312_n48, mult_x_312_n42,
mult_x_312_n39, mult_x_312_n38, mult_x_312_n37, mult_x_312_n36,
mult_x_312_n35, mult_x_312_n34, mult_x_312_n33, mult_x_312_n32,
mult_x_312_n31, mult_x_312_n30, mult_x_312_n29, mult_x_312_n28,
mult_x_312_n27, mult_x_312_n26, mult_x_312_n25, mult_x_312_n24,
mult_x_312_n23, mult_x_312_n22, mult_x_312_n21, mult_x_312_n20,
mult_x_312_n19, mult_x_312_n18, mult_x_312_n17, mult_x_312_n16,
mult_x_312_n15, mult_x_312_n14, mult_x_312_n13, mult_x_311_n37,
mult_x_311_n36, mult_x_311_n30, mult_x_311_n29, mult_x_311_n23,
mult_x_311_n22, mult_x_311_n18, mult_x_311_n17, mult_x_311_n15,
mult_x_311_n14, mult_x_310_n37, mult_x_310_n36, mult_x_310_n30,
mult_x_310_n29, mult_x_310_n23, mult_x_310_n22, mult_x_310_n18,
mult_x_310_n17, mult_x_310_n15, mult_x_310_n14, mult_x_309_n76,
mult_x_309_n71, mult_x_309_n66, mult_x_309_n65, mult_x_309_n58,
mult_x_309_n52, mult_x_309_n42, mult_x_309_n39, mult_x_309_n38,
mult_x_309_n37, mult_x_309_n36, mult_x_309_n35, mult_x_309_n34,
mult_x_309_n33, mult_x_309_n32, mult_x_309_n31, mult_x_309_n30,
mult_x_309_n29, mult_x_309_n28, mult_x_309_n27, mult_x_309_n26,
mult_x_309_n25, mult_x_309_n24, mult_x_309_n23, mult_x_309_n22,
mult_x_309_n21, mult_x_309_n20, mult_x_309_n19, mult_x_309_n18,
mult_x_309_n17, mult_x_309_n16, mult_x_309_n15, mult_x_309_n14,
mult_x_309_n13, DP_OP_26J224_129_1325_n18, DP_OP_26J224_129_1325_n17,
DP_OP_26J224_129_1325_n16, DP_OP_26J224_129_1325_n15,
DP_OP_26J224_129_1325_n14, DP_OP_26J224_129_1325_n8,
DP_OP_26J224_129_1325_n7, DP_OP_26J224_129_1325_n6,
DP_OP_26J224_129_1325_n5, DP_OP_26J224_129_1325_n4,
DP_OP_26J224_129_1325_n3, DP_OP_26J224_129_1325_n2,
DP_OP_26J224_129_1325_n1, DP_OP_234J224_132_4955_n22,
DP_OP_234J224_132_4955_n21, DP_OP_234J224_132_4955_n20,
DP_OP_234J224_132_4955_n19, DP_OP_234J224_132_4955_n18,
DP_OP_234J224_132_4955_n17, DP_OP_234J224_132_4955_n16,
DP_OP_234J224_132_4955_n15, DP_OP_234J224_132_4955_n9,
DP_OP_234J224_132_4955_n8, DP_OP_234J224_132_4955_n7,
DP_OP_234J224_132_4955_n6, DP_OP_234J224_132_4955_n5,
DP_OP_234J224_132_4955_n4, DP_OP_234J224_132_4955_n3,
DP_OP_234J224_132_4955_n2, DP_OP_234J224_132_4955_n1, intadd_519_A_7_,
intadd_519_A_0_, intadd_519_B_7_, intadd_519_B_6_, intadd_519_B_1_,
intadd_519_B_0_, intadd_519_CI, intadd_519_n8, intadd_519_n7,
intadd_519_n6, intadd_519_n5, intadd_519_n4, intadd_519_n3,
intadd_519_n2, intadd_519_n1, intadd_520_A_7_, intadd_520_A_0_,
intadd_520_B_7_, intadd_520_B_6_, intadd_520_B_1_, intadd_520_B_0_,
intadd_520_CI, intadd_520_n8, intadd_520_n7, intadd_520_n6,
intadd_520_n5, intadd_520_n4, intadd_520_n3, intadd_520_n2,
intadd_520_n1, intadd_521_A_7_, intadd_521_A_0_, intadd_521_B_7_,
intadd_521_B_6_, intadd_521_B_1_, intadd_521_B_0_, intadd_521_CI,
intadd_521_n8, intadd_521_n7, intadd_521_n6, intadd_521_n5,
intadd_521_n4, intadd_521_n3, intadd_521_n2, intadd_521_n1,
intadd_522_A_0_, intadd_522_B_6_, intadd_522_B_1_, intadd_522_B_0_,
intadd_522_CI, intadd_522_n7, intadd_522_n6, intadd_522_n5,
intadd_522_n4, intadd_522_n3, intadd_522_n2, intadd_522_n1,
intadd_523_CI, intadd_523_SUM_2_, intadd_523_SUM_1_,
intadd_523_SUM_0_, intadd_523_n3, intadd_523_n2, intadd_523_n1,
intadd_524_CI, intadd_524_SUM_2_, intadd_524_SUM_1_,
intadd_524_SUM_0_, intadd_524_n3, intadd_524_n2, intadd_524_n1,
intadd_525_CI, intadd_525_SUM_2_, intadd_525_SUM_1_,
intadd_525_SUM_0_, intadd_525_n3, intadd_525_n2, intadd_525_n1,
DP_OP_502J224_128_4510_n76, DP_OP_502J224_128_4510_n75,
DP_OP_502J224_128_4510_n70, DP_OP_502J224_128_4510_n69,
DP_OP_502J224_128_4510_n68, DP_OP_502J224_128_4510_n67,
DP_OP_502J224_128_4510_n66, DP_OP_502J224_128_4510_n63,
DP_OP_502J224_128_4510_n62, DP_OP_502J224_128_4510_n61,
DP_OP_502J224_128_4510_n60, DP_OP_502J224_128_4510_n59,
DP_OP_502J224_128_4510_n57, DP_OP_502J224_128_4510_n56,
DP_OP_502J224_128_4510_n55, DP_OP_502J224_128_4510_n54,
DP_OP_502J224_128_4510_n53, DP_OP_502J224_128_4510_n41,
DP_OP_502J224_128_4510_n38, DP_OP_502J224_128_4510_n37,
DP_OP_502J224_128_4510_n36, DP_OP_502J224_128_4510_n35,
DP_OP_502J224_128_4510_n34, DP_OP_502J224_128_4510_n33,
DP_OP_502J224_128_4510_n32, DP_OP_502J224_128_4510_n31,
DP_OP_502J224_128_4510_n30, DP_OP_502J224_128_4510_n29,
DP_OP_502J224_128_4510_n27, DP_OP_502J224_128_4510_n26,
DP_OP_502J224_128_4510_n25, DP_OP_502J224_128_4510_n24,
DP_OP_502J224_128_4510_n23, DP_OP_502J224_128_4510_n22,
DP_OP_502J224_128_4510_n21, DP_OP_501J224_127_5235_n411,
DP_OP_501J224_127_5235_n236, DP_OP_501J224_127_5235_n235,
DP_OP_501J224_127_5235_n234, DP_OP_501J224_127_5235_n233,
DP_OP_501J224_127_5235_n229, DP_OP_501J224_127_5235_n227,
DP_OP_501J224_127_5235_n226, DP_OP_501J224_127_5235_n220,
DP_OP_501J224_127_5235_n218, DP_OP_501J224_127_5235_n215,
DP_OP_501J224_127_5235_n210, DP_OP_501J224_127_5235_n209,
DP_OP_501J224_127_5235_n207, DP_OP_501J224_127_5235_n206,
DP_OP_501J224_127_5235_n202, DP_OP_501J224_127_5235_n200,
DP_OP_501J224_127_5235_n199, DP_OP_501J224_127_5235_n195,
DP_OP_501J224_127_5235_n194, DP_OP_501J224_127_5235_n193,
DP_OP_501J224_127_5235_n192, DP_OP_501J224_127_5235_n191,
DP_OP_501J224_127_5235_n190, DP_OP_501J224_127_5235_n189,
DP_OP_501J224_127_5235_n188, DP_OP_501J224_127_5235_n186,
DP_OP_501J224_127_5235_n184, DP_OP_501J224_127_5235_n183,
DP_OP_501J224_127_5235_n182, DP_OP_501J224_127_5235_n181,
DP_OP_501J224_127_5235_n179, DP_OP_501J224_127_5235_n171,
DP_OP_501J224_127_5235_n170, DP_OP_501J224_127_5235_n168,
DP_OP_501J224_127_5235_n167, DP_OP_501J224_127_5235_n166,
DP_OP_501J224_127_5235_n163, DP_OP_501J224_127_5235_n162,
DP_OP_501J224_127_5235_n161, DP_OP_501J224_127_5235_n160,
DP_OP_501J224_127_5235_n159, DP_OP_501J224_127_5235_n158,
DP_OP_501J224_127_5235_n156, DP_OP_501J224_127_5235_n155,
DP_OP_501J224_127_5235_n154, DP_OP_501J224_127_5235_n153,
DP_OP_501J224_127_5235_n152, DP_OP_501J224_127_5235_n151,
DP_OP_501J224_127_5235_n150, DP_OP_501J224_127_5235_n148,
DP_OP_501J224_127_5235_n147, DP_OP_501J224_127_5235_n146,
DP_OP_501J224_127_5235_n145, DP_OP_501J224_127_5235_n144,
DP_OP_501J224_127_5235_n143, DP_OP_501J224_127_5235_n142,
DP_OP_501J224_127_5235_n141, DP_OP_501J224_127_5235_n140,
DP_OP_501J224_127_5235_n139, DP_OP_501J224_127_5235_n138,
DP_OP_501J224_127_5235_n137, DP_OP_501J224_127_5235_n136,
DP_OP_501J224_127_5235_n135, DP_OP_501J224_127_5235_n134,
DP_OP_501J224_127_5235_n133, DP_OP_501J224_127_5235_n132,
DP_OP_501J224_127_5235_n131, DP_OP_501J224_127_5235_n130,
DP_OP_501J224_127_5235_n129, DP_OP_501J224_127_5235_n128,
DP_OP_501J224_127_5235_n127, DP_OP_501J224_127_5235_n126,
DP_OP_501J224_127_5235_n125, DP_OP_501J224_127_5235_n124,
DP_OP_501J224_127_5235_n123, DP_OP_501J224_127_5235_n122,
DP_OP_501J224_127_5235_n121, DP_OP_501J224_127_5235_n120,
DP_OP_501J224_127_5235_n119, DP_OP_501J224_127_5235_n118,
DP_OP_501J224_127_5235_n117, DP_OP_501J224_127_5235_n116,
DP_OP_501J224_127_5235_n115, DP_OP_501J224_127_5235_n114,
DP_OP_501J224_127_5235_n113, DP_OP_501J224_127_5235_n112,
DP_OP_501J224_127_5235_n111, DP_OP_501J224_127_5235_n110,
DP_OP_501J224_127_5235_n109, DP_OP_501J224_127_5235_n77,
DP_OP_501J224_127_5235_n72, DP_OP_501J224_127_5235_n71,
DP_OP_501J224_127_5235_n62, DP_OP_501J224_127_5235_n59,
DP_OP_501J224_127_5235_n58, DP_OP_501J224_127_5235_n56,
DP_OP_501J224_127_5235_n55, DP_OP_501J224_127_5235_n54,
DP_OP_501J224_127_5235_n53, DP_OP_501J224_127_5235_n48,
DP_OP_501J224_127_5235_n40, DP_OP_501J224_127_5235_n39,
DP_OP_501J224_127_5235_n37, DP_OP_501J224_127_5235_n36,
DP_OP_501J224_127_5235_n35, DP_OP_501J224_127_5235_n34,
DP_OP_501J224_127_5235_n32, DP_OP_501J224_127_5235_n31,
DP_OP_501J224_127_5235_n30, DP_OP_501J224_127_5235_n29,
DP_OP_501J224_127_5235_n28, DP_OP_501J224_127_5235_n27,
DP_OP_501J224_127_5235_n25, DP_OP_501J224_127_5235_n24,
DP_OP_501J224_127_5235_n23, DP_OP_501J224_127_5235_n22,
DP_OP_501J224_127_5235_n21, DP_OP_501J224_127_5235_n20,
DP_OP_501J224_127_5235_n19, DP_OP_501J224_127_5235_n18,
DP_OP_501J224_127_5235_n17, DP_OP_501J224_127_5235_n16,
DP_OP_501J224_127_5235_n15, DP_OP_501J224_127_5235_n14,
DP_OP_501J224_127_5235_n13, DP_OP_500J224_126_4510_n76,
DP_OP_500J224_126_4510_n75, DP_OP_500J224_126_4510_n70,
DP_OP_500J224_126_4510_n69, DP_OP_500J224_126_4510_n68,
DP_OP_500J224_126_4510_n67, DP_OP_500J224_126_4510_n66,
DP_OP_500J224_126_4510_n63, DP_OP_500J224_126_4510_n62,
DP_OP_500J224_126_4510_n61, DP_OP_500J224_126_4510_n60,
DP_OP_500J224_126_4510_n59, DP_OP_500J224_126_4510_n56,
DP_OP_500J224_126_4510_n55, DP_OP_500J224_126_4510_n54,
DP_OP_500J224_126_4510_n53, DP_OP_500J224_126_4510_n52,
DP_OP_500J224_126_4510_n41, DP_OP_500J224_126_4510_n38,
DP_OP_500J224_126_4510_n37, DP_OP_500J224_126_4510_n36,
DP_OP_500J224_126_4510_n35, DP_OP_500J224_126_4510_n34,
DP_OP_500J224_126_4510_n33, DP_OP_500J224_126_4510_n32,
DP_OP_500J224_126_4510_n31, DP_OP_500J224_126_4510_n30,
DP_OP_500J224_126_4510_n29, DP_OP_500J224_126_4510_n27,
DP_OP_500J224_126_4510_n26, DP_OP_500J224_126_4510_n25,
DP_OP_500J224_126_4510_n24, DP_OP_500J224_126_4510_n23,
DP_OP_500J224_126_4510_n22, DP_OP_500J224_126_4510_n21,
DP_OP_497J224_123_3916_n59, mult_x_313_n76, mult_x_313_n75,
mult_x_313_n74, mult_x_313_n69, mult_x_313_n68, mult_x_313_n67,
mult_x_313_n66, mult_x_313_n65, mult_x_313_n62, mult_x_313_n61,
mult_x_313_n60, mult_x_313_n59, mult_x_313_n58, mult_x_313_n56,
mult_x_313_n55, mult_x_313_n54, mult_x_313_n42, mult_x_313_n39,
mult_x_313_n38, mult_x_313_n37, mult_x_313_n36, mult_x_313_n35,
mult_x_313_n34, mult_x_313_n33, mult_x_313_n32, mult_x_313_n31,
mult_x_313_n30, mult_x_313_n29, mult_x_313_n28, mult_x_313_n27,
mult_x_313_n26, mult_x_313_n25, mult_x_313_n24, mult_x_313_n23,
mult_x_313_n22, mult_x_313_n21, DP_OP_499J224_125_1651_n130,
DP_OP_499J224_125_1651_n119, DP_OP_499J224_125_1651_n118,
DP_OP_499J224_125_1651_n117, DP_OP_499J224_125_1651_n116,
DP_OP_499J224_125_1651_n115, DP_OP_499J224_125_1651_n114,
DP_OP_499J224_125_1651_n113, DP_OP_499J224_125_1651_n112,
DP_OP_499J224_125_1651_n111, DP_OP_499J224_125_1651_n110,
DP_OP_499J224_125_1651_n109, DP_OP_499J224_125_1651_n108,
DP_OP_499J224_125_1651_n107, DP_OP_499J224_125_1651_n106,
DP_OP_499J224_125_1651_n105, DP_OP_499J224_125_1651_n104,
DP_OP_499J224_125_1651_n90, DP_OP_499J224_125_1651_n88,
DP_OP_499J224_125_1651_n87, DP_OP_499J224_125_1651_n86,
DP_OP_499J224_125_1651_n85, DP_OP_499J224_125_1651_n84,
DP_OP_499J224_125_1651_n83, DP_OP_499J224_125_1651_n82,
DP_OP_499J224_125_1651_n81, DP_OP_499J224_125_1651_n80,
DP_OP_499J224_125_1651_n79, DP_OP_499J224_125_1651_n78,
DP_OP_499J224_125_1651_n77, DP_OP_499J224_125_1651_n76,
DP_OP_499J224_125_1651_n75, DP_OP_499J224_125_1651_n74,
DP_OP_499J224_125_1651_n73, DP_OP_499J224_125_1651_n72,
DP_OP_499J224_125_1651_n71, DP_OP_499J224_125_1651_n70,
DP_OP_499J224_125_1651_n69, DP_OP_499J224_125_1651_n68,
DP_OP_499J224_125_1651_n67, DP_OP_499J224_125_1651_n66,
DP_OP_499J224_125_1651_n65, DP_OP_499J224_125_1651_n64,
DP_OP_499J224_125_1651_n63, DP_OP_499J224_125_1651_n62,
DP_OP_499J224_125_1651_n61, DP_OP_499J224_125_1651_n60,
DP_OP_499J224_125_1651_n59, DP_OP_499J224_125_1651_n58,
DP_OP_499J224_125_1651_n57, DP_OP_499J224_125_1651_n56,
DP_OP_499J224_125_1651_n55, DP_OP_499J224_125_1651_n54,
DP_OP_499J224_125_1651_n53, DP_OP_499J224_125_1651_n52,
DP_OP_499J224_125_1651_n51, DP_OP_499J224_125_1651_n50,
DP_OP_499J224_125_1651_n49, DP_OP_499J224_125_1651_n48,
DP_OP_499J224_125_1651_n47, DP_OP_499J224_125_1651_n46,
DP_OP_499J224_125_1651_n45, DP_OP_499J224_125_1651_n44,
DP_OP_499J224_125_1651_n43, DP_OP_499J224_125_1651_n42,
DP_OP_499J224_125_1651_n41, DP_OP_499J224_125_1651_n40, n2194, n2195,
n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205,
n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215,
n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225,
n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235,
n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245,
n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255,
n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265,
n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275,
n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285,
n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295,
n2296, n2297, n2298, n2299, n2301, n2302, n2303, n2304, n2305, n2306,
n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315, n2316,
n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325, n2326,
n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335, n2336,
n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345, n2346,
n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355, n2356,
n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365, n2366,
n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375, n2377,
n2378, n2379, n2380, n2381, n2382, n2383, n2385, n2387, n2388, n2389,
n2390, n2391, n2392, n2393, n2394, n2395, n2396, n2397, n2398, n2399,
n2400, n2401, n2402, n2403, n2404, n2405, n2406, n2407, n2408, n2409,
n2410, n2411, n2413, n2415, n2416, n2417, n2418, n2419, n2420, n2421,
n2422, n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431,
n2432, n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441,
n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451,
n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461,
n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471,
n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481,
n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491,
n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501,
n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511,
n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521,
n2522, n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531,
n2532, n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541,
n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551,
n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561,
n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571,
n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581,
n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591,
n2592, n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601,
n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611,
n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621,
n2622, n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631,
n2632, n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641,
n2642, n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651,
n2652, n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661,
n2662, n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671,
n2672, n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681,
n2682, n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691,
n2692, n2693, n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701,
n2702, n2703, n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712,
n2713, n2714, n2715, n2717, n2718, n2719, n2720, n2721, n2722, n2723,
n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2733, n2734,
n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744,
n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753, n2754,
n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764,
n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774,
n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784,
n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794,
n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804,
n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814,
n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824,
n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834,
n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844,
n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854,
n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864,
n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874,
n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883, n2884,
n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893, n2894,
n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903, n2904,
n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913, n2914,
n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923, n2924,
n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933, n2934,
n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943, n2944,
n2945, n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953, n2954,
n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963, n2964,
n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973, n2974,
n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983, n2984,
n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993, n2994,
n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003, n3004,
n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013, n3014,
n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023, n3024,
n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033, n3034,
n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043, n3044,
n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053, n3054,
n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063, n3064,
n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073, n3074,
n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083, n3084,
n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093, n3094,
n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102, n3103, n3104,
n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113, n3114,
n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123, n3124,
n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133, n3134,
n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143, n3144,
n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153, n3154,
n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163, n3164,
n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173, n3174,
n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183, n3184,
n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193, n3194,
n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203, n3204,
n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213, n3214,
n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223, n3224,
n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233, n3234,
n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243, n3244,
n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3252, n3253, n3254,
n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263, n3264,
n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273, n3274,
n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283, n3284,
n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293, n3294,
n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303, n3304,
n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313, n3314,
n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322, n3323, n3324,
n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333, n3334,
n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343, n3344,
n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353, n3354,
n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363, n3364,
n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373, n3374,
n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383, n3384,
n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393, n3394,
n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403, n3404,
n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413, n3414,
n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423, n3424,
n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433, n3434,
n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443, n3444,
n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453, n3454,
n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463, n3464,
n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473, n3474,
n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483, n3484,
n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493, n3494,
n3495, n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503, n3504,
n3505, n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513, n3514,
n3515, n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523, n3524,
n3525, n3526, n3527, n3528, n3529, n3530, n3531, n3532, n3533, n3534,
n3535, n3536, n3537, n3538, n3539, n3540, n3541, n3542, n3543, n3544,
n3545, n3546, n3547, n3548, n3549, n3550, n3551, n3552, n3553, n3554,
n3555, n3556, n3557, n3558, n3559, n3560, n3561, n3562, n3563, n3564,
n3565, n3566, n3567, n3568, n3569, n3570, n3571, n3572, n3573, n3574,
n3575, n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583, n3584,
n3585, n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593, n3594,
n3595, n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603, n3604,
n3605, n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613, n3614,
n3615, n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623, n3624,
n3625, n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633, n3634,
n3635, n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643, n3644,
n3645, n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653, n3654,
n3655, n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663, n3664,
n3665, n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673, n3674,
n3675, n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683, n3684,
n3685, n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693, n3694,
n3695, n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3703, n3704,
n3705, n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713, n3714,
n3715, n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723, n3724,
n3725, n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733, n3734,
n3735, n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743, n3744,
n3745, n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753, n3754,
n3755, n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763, n3764,
n3765, n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773, n3774,
n3775, n3776, n3778, n3779, n3780, n3781, n3782, n3783, n3784, n3785,
n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793, n3794, n3795,
n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803, n3804, n3805,
n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813, n3814, n3815,
n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823, n3824, n3825,
n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833, n3834, n3835,
n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843, n3844, n3845,
n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853, n3854, n3855,
n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863, n3864, n3865,
n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873, n3874, n3875,
n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883, n3884, n3885,
n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893, n3894, n3895,
n3896, n3897, n3898, n3899, n3900, n3901, n3902, n3903, n3904, n3905,
n3906, n3907, n3908, n3909, n3910, n3911, n3912, n3913, n3914, n3915,
n3916, n3917, n3918, n3919, n3920, n3921, n3922, n3923, n3924, n3925,
n3926, n3927, n3928, n3929, n3930, n3931, n3932, n3933, n3934, n3935,
n3936, n3937, n3938, n3939, n3940, n3941, n3942, n3943, n3944, n3945,
n3946, n3947, n3948, n3949, n3950, n3951, n3952, n3953, n3954, n3955,
n3956, n3957, n3958, n3959, n3960, n3961, n3962, n3963, n3964, n3965,
n3966, n3967, n3968, n3969, n3970, n3971, n3972, n3973, n3974, n3975,
n3976, n3977, n3978, n3979, n3980, n3981, n3982, n3983, n3984, n3985,
n3986, n3987, n3988, n3989, n3990, n3991, n3992, n3993, n3994, n3995,
n3996, n3997, n3998, n3999, n4000, n4001, n4002, n4003, n4004, n4005,
n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013, n4014, n4015,
n4016, n4017, n4018, n4019, n4020, n4021, n4022, n4023, n4024, n4025,
n4026, n4027, n4028, n4029, n4030, n4031, n4032, n4033, n4034, n4035,
n4036, n4037, n4038, n4039, n4040, n4041, n4042, n4043, n4044, n4045,
n4046, n4047, n4048, n4049, n4050, n4051, n4052, n4053, n4054, n4055,
n4056, n4057, n4058, n4059, n4060, n4061, n4062, n4063, n4064, n4065,
n4066, n4067, n4068, n4069, n4070, n4071, n4072, n4073, n4074, n4075,
n4076, n4077, n4078, n4079, n4080, n4081, n4082, n4083, n4084, n4085,
n4086, n4087, n4088, n4089, n4090, n4091, n4092, n4093, n4094, n4095,
n4096, n4097, n4098, n4099, n4100, n4101, n4102, n4103, n4104, n4105,
n4106, n4107, n4108, n4109, n4110, n4111, n4112, n4113, n4114, n4115,
n4116, n4117, n4118, n4119, n4120, n4121, n4122, n4123, n4124, n4125,
n4126, n4127, n4128, n4129, n4130, n4131, n4132, n4133, n4134, n4135,
n4136, n4137, n4138, n4139, n4140, n4141, n4142, n4143, n4144, n4145,
n4146, n4147, n4148, n4149, n4150, n4151, n4152, n4153, n4154, n4155,
n4156, n4157, n4158, n4159, n4160, n4161, n4162, n4163, n4164, n4165,
n4166, n4167, n4168, n4169, n4170, n4171, n4172, n4173, n4174, n4175,
n4176, n4177, n4178, n4179, n4180, n4181, n4182, n4183, n4184, n4185,
n4186, n4187, n4188, n4189, n4190, n4191, n4192, n4193, n4194, n4195,
n4196, n4197, n4198, n4199, n4200, n4201, n4202, n4203, n4204, n4205,
n4206, n4207, n4208, n4209, n4210, n4211, n4212, n4213, n4214, n4215,
n4216, n4217, n4218, n4219, n4220, n4221, n4222, n4223, n4224, n4225,
n4226, n4227, n4228, n4229, n4230, n4231, n4232, n4233, n4234, n4235,
n4236, n4237, n4238, n4239, n4240, n4241, n4242, n4243, n4244, n4245,
n4246, n4247, n4248, n4249, n4250, n4251, n4252, n4253, n4254, n4255,
n4256, n4257, n4258, n4259, n4260, n4261, n4262, n4263, n4264, n4265,
n4266, n4267, n4268, n4269, n4270, n4271, n4272, n4273, n4274, n4275,
n4276, n4277, n4278, n4279, n4280, n4281, n4282, n4283, n4284, n4285,
n4286, n4287, n4288, n4289, n4290, n4291, n4292, n4293, n4294, n4295,
n4296, n4297, n4298, n4299, n4300, n4301, n4302, n4303, n4304, n4305,
n4306, n4307, n4308, n4309, n4310, n4311, n4312, n4313, n4314, n4315,
n4316, n4317, n4318, n4319, n4320, n4321, n4322, n4323, n4324, n4325,
n4326, n4327, n4328, n4329, n4330, n4331, n4332, n4333, n4334, n4335,
n4336, n4337, n4338, n4339, n4340, n4341, n4342, n4343, n4344, n4345,
n4346, n4347, n4348, n4349, n4350, n4351, n4352, n4353, n4354, n4355,
n4356, n4357, n4358, n4359, n4360, n4361, n4362, n4363, n4364, n4365,
n4366, n4367, n4368, n4369, n4370, n4371, n4372, n4373, n4374, n4375,
n4376, n4377, n4378, n4379, n4380, n4381, n4382, n4383, n4384, n4385,
n4386, n4387, n4388, n4389, n4390, n4391, n4392, n4393, n4394, n4395,
n4396, n4397, n4398, n4399, n4400, n4401, n4402, n4403, n4404, n4405,
n4406, n4407, n4408, n4409, n4410, n4411, n4412, n4413, n4414, n4415,
n4416, n4417, n4418, n4419, n4420, n4421, n4422, n4423, n4424, n4425,
n4426, n4427, n4428, n4429, n4430, n4431, n4432, n4433, n4434, n4435,
n4436, n4437, n4438, n4439, n4440, n4441, n4442, n4443, n4444, n4445,
n4446, n4447, n4448, n4449, n4450, n4451, n4452, n4453, n4454, n4455,
n4456, n4457, n4458, n4459, n4460, n4461, n4462, n4463, n4464, n4465,
n4466, n4467, n4468, n4469, n4470, n4471, n4472, n4473, n4474, n4475,
n4476, n4477, n4478, n4479, n4480, n4481, n4482, n4483, n4484, n4485,
n4486, n4487, n4488, n4489, n4490, n4491, n4492, n4493, n4494, n4495,
n4496, n4497, n4498, n4499, n4500, n4501, n4502, n4503, n4504, n4505,
n4506, n4507, n4508, n4509, n4510, n4511, n4512, n4513, n4514, n4515,
n4516, n4517, n4518, n4519, n4520, n4521, n4522, n4523, n4524, n4525,
n4526, n4527, n4528, n4529, n4530, n4531, n4532, n4533, n4534, n4535,
n4536, n4537, n4538, n4539, n4540, n4541, n4542, n4543, n4544, n4545,
n4546, n4547, n4548, n4549, n4550, n4551, n4552, n4553, n4554, n4555,
n4556, n4557, n4558, n4559, n4560, n4561, n4562, n4563, n4564, n4565,
n4566, n4567, n4568, n4569, n4570, n4571, n4572, n4573, n4574, n4575,
n4576, n4577, n4578, n4579, n4580, n4581, n4582, n4583, n4584, n4585,
n4586, n4587, n4588, n4589, n4590, n4591, n4592, n4593, n4594, n4595,
n4596, n4597, n4598, n4599, n4600, n4601, n4602, n4603, n4604, n4605,
n4606, n4607, n4608, n4609, n4610, n4611, n4612, n4613, n4614, n4615,
n4616, n4617, n4618, n4619, n4620, n4621, n4622, n4623, n4624, n4625,
n4626, n4627, n4628, n4629, n4630, n4631, n4632, n4633, n4634, n4635,
n4636, n4637, n4638, n4639, n4640, n4641, n4642, n4643, n4644, n4645,
n4646, n4647, n4648, n4649, n4650, n4651, n4652, n4653, n4654, n4655,
n4656, n4657, n4658, n4659, n4660, n4661, n4662, n4663, n4664, n4665,
n4666, n4667, n4668, n4669, n4670, n4671, n4672, n4673, n4674, n4675,
n4676, n4677, n4678, n4679, n4680, n4681, n4682, n4683, n4684, n4685,
n4686, n4687, n4688, n4689, n4690, n4691, n4692, n4693, n4694, n4695,
n4696, n4697, n4698, n4699, n4700, n4701, n4702, n4703, n4704, n4705,
n4706, n4707, n4708, n4709, n4710, n4711, n4712, n4713, n4714, n4715,
n4716, n4717, n4718, n4719, n4720, n4721, n4722, n4723, n4724, n4725,
n4726, n4727, n4728, n4729, n4730, n4731, n4732, n4733, n4734, n4735,
n4736, n4737, n4738, n4739, n4741, n4743, n4744, n4745, n4746, n4747,
n4748, n4749, n4750, n4751, n4752, n4753, n4754, n4755, n4756, n4757,
n4758, n4759, n4760, n4761, n4762, n4763, n4764, n4765, n4766, n4767,
n4768, n4769, n4770, n4771, n4772, n4773, n4774, n4775, n4776, n4777,
n4778, n4779, n4780, n4781, n4782, n4783, n4784, n4785, n4786, n4787,
n4788, n4789, n4790, n4791, n4792, n4793, n4794, n4795, n4796, n4797,
n4798, n4799, n4800, n4801, n4802, n4803, n4804, n4805, n4806, n4807,
n4808, n4809, n4810, n4811, n4812, n4813, n4814, n4815, n4816, n4817,
n4818, n4819, n4820, n4821, n4822, n4823, n4824, n4825, n4826, n4827,
n4828, n4829, n4830, n4831, n4832, n4833, n4834, n4835, n4836, n4837,
n4838, n4839, n4840, n4841, n4842, n4843, n4844, n4845, n4846, n4847,
n4848, n4849, n4850, n4851, n4852, n4853, n4854, n4855, n4856, n4857,
n4858, n4859, n4860, n4861, n4862, n4863, n4864, n4865, n4866, n4867,
n4868, n4869, n4870, n4871, n4872, n4873, n4874, n4876, n4877, n4878,
n4879, n4880, n4881, n4882, n4883, n4884, n4885, n4886, n4887, n4888,
n4889, n4890, n4891, n4892, n4893, n4894, n4895, n4896, n4897, n4898,
n4899, n4900, n4901, n4902, n4904, n4906, n4907, n4908, n4909, n4910,
n4911, n4912, n4917, n4918, n4919, n4920, n4921, n4922, n4923, n4924,
n4925, n4926, n4927, n4928, n4929, n4930, n4932, n4933, n4934, n4935,
n4936, n4937, n4938, n4939, n4940, n4941, n4942, n4943, n4944, n4945,
n4946, n4947, n4948, n4949, n4950, n4951, n4952, n4953, n4954, n4955,
n4956, n4957, n4958, n4959, n4960, n4961, n4962, n4963, n4964, n4965,
n4966, n4967, n4968, n4969, n4970, n4971, n4972, n4973, n4974, n4975,
n4976, n4977, n4978, n4979, n4980, n4981, n4982, n4983, n4984, n4985,
n4986, n4987, n4988, n4989, n4990, n4991, n4992, n4993, n4994, n4995,
n4996, n4997, n4998, n4999, n5000, n5001, n5002, n5003, n5004, n5005,
n5006, n5007, n5008, n5009, n5010, n5011, n5012, n5013, n5014, n5015,
n5016, n5017, n5018, n5019, n5020, n5021, n5022, n5023, n5024, n5025,
n5026, n5027, n5028, n5029, n5030, n5031, n5032, n5033, n5034, n5036,
n5037, n5038, n5039, n5040, n5041, n5042, n5043, n5044, n5045, n5046,
n5047, n5048, n5049, n5050, n5051, n5052, n5053, n5054, n5055, n5056,
n5057, n5058, n5059, n5060, n5061, n5062, n5063, n5064, n5065, n5066,
n5067, n5068, n5069, n5070, n5071, n5072, n5073, n5074, n5075, n5076,
n5077, n5078, n5079, n5080, n5081, n5082, n5083, n5084, n5085, n5086,
n5087, n5088, n5089, n5090, n5091, n5092, n5093, n5094, n5095, n5096,
n5098, n5099, n5100, n5101, n5102, n5103, n5104, n5105, n5107, n5108,
n5109, n5110, n5111, n5112, n5113, n5114, n5115, n5116, n5117, n5118,
n5119, n5120, n5121, n5122, n5123, n5124, n5125, n5126, n5127, n5128,
n5129, n5130, n5131, n5132, n5133, n5134, n5135, n5136, n5137, n5138,
n5139, n5140, n5141, n5142, n5143, n5144, n5145, n5146, n5147, n5148,
n5149, n5150, n5151, n5152, n5153, n5154, n5155, n5156, n5157, n5158,
n5159, n5160, n5161, n5162, n5163, n5164, n5165, n5166, n5167, n5168,
n5169, n5170, n5171, n5172, n5173, n5174, n5175, n5176, n5177, n5178,
n5179, n5180, n5181, n5182, n5183, n5184, n5185, n5186, n5187, n5188,
n5189, n5190, n5191, n5192, n5193, n5194, n5195, n5196, n5197, n5198,
n5199, n5200, n5201, n5202, n5203, n5204, n5205, n5206, n5207, n5208,
n5209, n5210, n5211, n5212, n5213, n5214, n5215, n5216, n5217, n5218,
n5219, n5220, n5221, n5222, n5223, n5224, n5225, n5226, n5227, n5228,
n5229, n5230, n5231, n5232, n5233, n5234, n5235, n5236, n5237, n5238,
n5239, n5240, n5241, n5242, n5243, n5244, n5245, n5246, n5247, n5248,
n5249, n5250, n5251, n5252, n5253, n5254, n5255, n5256, n5257, n5258,
n5259, n5260, n5261, n5262, n5263, n5264, n5265, n5266, n5267, n5268,
n5269, n5270, n5271, n5272, n5273, n5274, n5275, n5276, n5277, n5278,
n5279, n5280, n5281, n5282, n5283, n5284, n5285, n5286, n5287, n5288,
n5289, n5290, n5291, n5292, n5293, n5294, n5295, n5296, n5297, n5298,
n5299, n5300, n5301, n5302, n5303, n5304, n5305, n5306, n5307, n5308,
n5309, n5310, n5311, n5312, n5313, n5314, n5316, n5317, n5318, n5319,
n5320, n5321, n5322, n5323, n5324, n5325, n5326, n5327, n5328, n5329,
n5330, n5331, n5332, n5333, n5334, n5335, n5336, n5337, n5338, n5339,
n5340, n5341, n5342, n5343, n5344, n5345, n5346, n5347, n5348, n5349,
n5350, n5351, n5352, n5353, n5354, n5355, n5356, n5357, n5358, n5359,
n5360, n5361, n5362, n5363, n5364, n5365, n5366, n5367, n5368, n5369,
n5370, n5371, n5372, n5373, n5374, n5375, n5376, n5377, n5378, n5379,
n5380, n5381, n5382, n5383, n5384, n5385, n5386, n5387, n5388, n5389,
n5390, n5391, n5392, n5393, n5394, n5395, n5396, n5397, n5398, n5399,
n5400, n5401, n5402, n5403, n5404, n5405, n5406, n5407, n5408, n5409,
n5410, n5411, n5412, n5413, n5414, n5415, n5416, n5417, n5418, n5419,
n5420, n5421, n5422, n5423, n5424, n5425, n5426, n5427, n5428, n5429,
n5430, n5431, n5432, n5433, n5434, n5435, n5436, n5437, n5438, n5439,
n5440, n5441, n5442, n5443, n5444, n5445, n5446, n5447, n5448, n5449,
n5450, n5451, n5452, n5453, n5454, n5455, n5456, n5457, n5458, n5459,
n5460, n5461, n5462, n5463, n5464, n5465, n5466, n5467, n5468, n5469,
n5470, n5471, n5472, n5473, n5474, n5475, n5476, n5477, n5478, n5479,
n5480, n5481, n5482, n5483, n5484, n5485, n5486, n5487, n5488, n5489,
n5490, n5491, n5492, n5493, n5494, n5495, n5496, n5497, n5498, n5499,
n5500, n5501, n5502, n5503, n5504, n5505, n5506, n5507, n5508, n5509,
n5510, n5511, n5512, n5513, n5514, n5515, n5517, n5518, n5519, n5520,
n5521, n5522, n5523, n5524, n5525;
wire [1:0] operation_reg;
wire [31:23] dataA;
wire [31:23] dataB;
wire [31:0] cordic_result;
wire [31:0] result_add_subt;
wire [31:0] mult_result;
wire [27:0] FPSENCOS_d_ff3_LUT_out;
wire [31:0] FPSENCOS_d_ff3_sh_y_out;
wire [31:0] FPSENCOS_d_ff3_sh_x_out;
wire [31:0] FPSENCOS_d_ff2_Z;
wire [31:0] FPSENCOS_d_ff2_Y;
wire [30:15] FPSENCOS_d_ff2_X;
wire [31:0] FPSENCOS_d_ff_Zn;
wire [30:0] FPSENCOS_d_ff_Yn;
wire [30:0] FPSENCOS_d_ff_Xn;
wire [31:0] FPSENCOS_d_ff1_Z;
wire [1:0] FPSENCOS_d_ff1_shift_region_flag_out;
wire [1:0] FPSENCOS_cont_var_out;
wire [3:0] FPSENCOS_cont_iter_out;
wire [23:0] FPMULT_Sgf_normalized_result;
wire [23:0] FPMULT_Add_result;
wire [8:0] FPMULT_S_Oper_A_exp;
wire [8:0] FPMULT_exp_oper_result;
wire [31:0] FPMULT_Op_MY;
wire [31:0] FPMULT_Op_MX;
wire [1:0] FPMULT_FSM_selector_B;
wire [47:0] FPMULT_P_Sgf;
wire [25:0] FPADDSUB_DmP_mant_SFG_SWR;
wire [30:0] FPADDSUB_DMP_SFG;
wire [7:0] FPADDSUB_exp_rslt_NRM2_EW1;
wire [4:0] FPADDSUB_LZD_output_NRM2_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM2_EW;
wire [4:2] FPADDSUB_shift_value_SHT2_EWR;
wire [30:0] FPADDSUB_DMP_SHT2_EWSW;
wire [21:0] FPADDSUB_Data_array_SWR;
wire [25:0] FPADDSUB_Raw_mant_NRM_SWR;
wire [4:0] FPADDSUB_Shift_amount_SHT1_EWR;
wire [22:0] FPADDSUB_DmP_mant_SHT1_SW;
wire [30:0] FPADDSUB_DMP_SHT1_EWSW;
wire [27:0] FPADDSUB_DmP_EXP_EWSW;
wire [30:0] FPADDSUB_DMP_EXP_EWSW;
wire [31:0] FPADDSUB_intDY_EWSW;
wire [31:0] FPADDSUB_intDX_EWSW;
wire [2:1] FPADDSUB_Shift_reg_FLAGS_7;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_next;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_reg;
wire [3:0] FPMULT_FS_Module_state_reg;
wire [8:0] FPMULT_Exp_module_Data_S;
wire [5:0] FPMULT_Sgf_operation_Result;
wire [5:0] FPMULT_Sgf_operation_EVEN1_Q_left;
wire [2:0] FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg;
wire [13:0] FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle;
wire [11:6] FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right;
wire [11:0] FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left;
wire [16:1] FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B;
wire [15:0] FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle;
wire [13:0] FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right;
wire [11:0] FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left;
wire [13:0] FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle;
wire [11:6] FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right;
wire [11:0] FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left;
DFFRXLTS reg_dataA_Q_reg_24_ ( .D(Data_1[24]), .CK(clk), .RN(n5484), .Q(
dataA[24]) );
DFFRXLTS reg_dataA_Q_reg_26_ ( .D(Data_1[26]), .CK(clk), .RN(n5484), .Q(
dataA[26]) );
DFFRXLTS reg_dataA_Q_reg_31_ ( .D(Data_1[31]), .CK(clk), .RN(n5471), .Q(
dataA[31]) );
DFFRXLTS reg_dataB_Q_reg_23_ ( .D(Data_2[23]), .CK(clk), .RN(n5482), .Q(
dataB[23]) );
DFFRXLTS reg_dataB_Q_reg_25_ ( .D(Data_2[25]), .CK(clk), .RN(n5476), .Q(
dataB[25]) );
DFFRXLTS reg_dataB_Q_reg_27_ ( .D(Data_2[27]), .CK(clk), .RN(n5502), .Q(
dataB[27]) );
DFFRXLTS reg_dataB_Q_reg_29_ ( .D(Data_2[29]), .CK(clk), .RN(n5478), .Q(
dataB[29]) );
DFFRXLTS reg_dataB_Q_reg_31_ ( .D(Data_2[31]), .CK(clk), .RN(n5476), .Q(
dataB[31]) );
DFFRXLTS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n2149), .CK(
clk), .RN(n5442), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_3_ ( .D(n2145), .CK(clk), .RN(
n5467), .QN(n2239) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_0_ ( .D(n2133), .CK(clk), .RN(n5491), .Q(
FPSENCOS_d_ff3_LUT_out[0]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_4_ ( .D(n2129), .CK(clk), .RN(n5489), .Q(
FPSENCOS_d_ff3_LUT_out[4]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_5_ ( .D(n2128), .CK(clk), .RN(n5471), .Q(
FPSENCOS_d_ff3_LUT_out[5]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_6_ ( .D(n2127), .CK(clk), .RN(n5471), .Q(
FPSENCOS_d_ff3_LUT_out[6]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_7_ ( .D(n2126), .CK(clk), .RN(n5489), .Q(
FPSENCOS_d_ff3_LUT_out[7]), .QN(n5419) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_8_ ( .D(n2125), .CK(clk), .RN(n5492), .Q(
FPSENCOS_d_ff3_LUT_out[8]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_9_ ( .D(n2124), .CK(clk), .RN(n5489), .Q(
FPSENCOS_d_ff3_LUT_out[9]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_10_ ( .D(n2123), .CK(clk), .RN(n5487), .Q(
FPSENCOS_d_ff3_LUT_out[10]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_13_ ( .D(n2121), .CK(clk), .RN(n5484), .Q(
FPSENCOS_d_ff3_LUT_out[13]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_15_ ( .D(n2120), .CK(clk), .RN(n5489), .Q(
FPSENCOS_d_ff3_LUT_out[15]), .QN(n5420) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_19_ ( .D(n2119), .CK(clk), .RN(n5487), .Q(
FPSENCOS_d_ff3_LUT_out[19]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_21_ ( .D(n2118), .CK(clk), .RN(n5488), .Q(
FPSENCOS_d_ff3_LUT_out[21]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_23_ ( .D(n2117), .CK(clk), .RN(n5491), .Q(
FPSENCOS_d_ff3_LUT_out[23]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_25_ ( .D(n2115), .CK(clk), .RN(n5487), .Q(
FPSENCOS_d_ff3_LUT_out[25]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_26_ ( .D(n2114), .CK(clk), .RN(n5491), .Q(
FPSENCOS_d_ff3_LUT_out[26]), .QN(n5418) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_27_ ( .D(n2113), .CK(clk), .RN(n5485), .Q(
FPSENCOS_d_ff3_LUT_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_23_ ( .D(n1853), .CK(clk), .RN(n5487),
.Q(FPSENCOS_d_ff3_sh_y_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_24_ ( .D(n1852), .CK(clk), .RN(n5492),
.Q(FPSENCOS_d_ff3_sh_y_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_25_ ( .D(n1851), .CK(clk), .RN(n5484),
.Q(FPSENCOS_d_ff3_sh_y_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_26_ ( .D(n1850), .CK(clk), .RN(n5491),
.Q(FPSENCOS_d_ff3_sh_y_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_27_ ( .D(n1849), .CK(clk), .RN(n5489),
.Q(FPSENCOS_d_ff3_sh_y_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_28_ ( .D(n1848), .CK(clk), .RN(n5485),
.Q(FPSENCOS_d_ff3_sh_y_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_29_ ( .D(n1847), .CK(clk), .RN(n5491),
.Q(FPSENCOS_d_ff3_sh_y_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_30_ ( .D(n1846), .CK(clk), .RN(n5489),
.Q(FPSENCOS_d_ff3_sh_y_out[30]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_23_ ( .D(n1951), .CK(clk), .RN(n5489),
.Q(FPSENCOS_d_ff3_sh_x_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_24_ ( .D(n1950), .CK(clk), .RN(n5488),
.Q(FPSENCOS_d_ff3_sh_x_out[24]), .QN(n5431) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_25_ ( .D(n1949), .CK(clk), .RN(n5485),
.Q(FPSENCOS_d_ff3_sh_x_out[25]), .QN(n5432) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_26_ ( .D(n1948), .CK(clk), .RN(n5487),
.Q(FPSENCOS_d_ff3_sh_x_out[26]), .QN(n5433) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_27_ ( .D(n1947), .CK(clk), .RN(n5489),
.Q(FPSENCOS_d_ff3_sh_x_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_28_ ( .D(n1946), .CK(clk), .RN(n5484),
.Q(FPSENCOS_d_ff3_sh_x_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_29_ ( .D(n1945), .CK(clk), .RN(n5484),
.Q(FPSENCOS_d_ff3_sh_x_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_30_ ( .D(n1944), .CK(clk), .RN(n5489),
.Q(FPSENCOS_d_ff3_sh_x_out[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_0_ ( .D(n2112), .CK(clk), .RN(n5519), .Q(
FPSENCOS_d_ff1_Z[0]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_1_ ( .D(n2111), .CK(clk), .RN(n5500), .Q(
FPSENCOS_d_ff1_Z[1]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_2_ ( .D(n2110), .CK(clk), .RN(n5499), .Q(
FPSENCOS_d_ff1_Z[2]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_3_ ( .D(n2109), .CK(clk), .RN(n5500), .Q(
FPSENCOS_d_ff1_Z[3]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_4_ ( .D(n2108), .CK(clk), .RN(n5499), .Q(
FPSENCOS_d_ff1_Z[4]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_5_ ( .D(n2107), .CK(clk), .RN(n5499), .Q(
FPSENCOS_d_ff1_Z[5]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_6_ ( .D(n2106), .CK(clk), .RN(n5499), .Q(
FPSENCOS_d_ff1_Z[6]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_7_ ( .D(n2105), .CK(clk), .RN(n5501), .Q(
FPSENCOS_d_ff1_Z[7]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_8_ ( .D(n2104), .CK(clk), .RN(n5501), .Q(
FPSENCOS_d_ff1_Z[8]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_9_ ( .D(n2103), .CK(clk), .RN(n5501), .Q(
FPSENCOS_d_ff1_Z[9]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_10_ ( .D(n2102), .CK(clk), .RN(n5469), .Q(
FPSENCOS_d_ff1_Z[10]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_11_ ( .D(n2101), .CK(clk), .RN(n5500), .Q(
FPSENCOS_d_ff1_Z[11]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_12_ ( .D(n2100), .CK(clk), .RN(n5469), .Q(
FPSENCOS_d_ff1_Z[12]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_13_ ( .D(n2099), .CK(clk), .RN(n5473), .Q(
FPSENCOS_d_ff1_Z[13]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_14_ ( .D(n2098), .CK(clk), .RN(n5501), .Q(
FPSENCOS_d_ff1_Z[14]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_15_ ( .D(n2097), .CK(clk), .RN(n5470), .Q(
FPSENCOS_d_ff1_Z[15]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_16_ ( .D(n2096), .CK(clk), .RN(n5500), .Q(
FPSENCOS_d_ff1_Z[16]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_17_ ( .D(n2095), .CK(clk), .RN(n5501), .Q(
FPSENCOS_d_ff1_Z[17]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_18_ ( .D(n2094), .CK(clk), .RN(n5500), .Q(
FPSENCOS_d_ff1_Z[18]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_19_ ( .D(n2093), .CK(clk), .RN(n5470), .Q(
FPSENCOS_d_ff1_Z[19]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_20_ ( .D(n2092), .CK(clk), .RN(n5470), .Q(
FPSENCOS_d_ff1_Z[20]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_21_ ( .D(n2091), .CK(clk), .RN(n5473), .Q(
FPSENCOS_d_ff1_Z[21]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_22_ ( .D(n2090), .CK(clk), .RN(n5501), .Q(
FPSENCOS_d_ff1_Z[22]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_23_ ( .D(n2089), .CK(clk), .RN(n5473), .Q(
FPSENCOS_d_ff1_Z[23]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_24_ ( .D(n2088), .CK(clk), .RN(n5501), .Q(
FPSENCOS_d_ff1_Z[24]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_25_ ( .D(n2087), .CK(clk), .RN(n5499), .Q(
FPSENCOS_d_ff1_Z[25]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_26_ ( .D(n2086), .CK(clk), .RN(n5473), .Q(
FPSENCOS_d_ff1_Z[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_27_ ( .D(n2085), .CK(clk), .RN(n5473), .Q(
FPSENCOS_d_ff1_Z[27]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_28_ ( .D(n2084), .CK(clk), .RN(n5473), .Q(
FPSENCOS_d_ff1_Z[28]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_29_ ( .D(n2083), .CK(clk), .RN(n5470), .Q(
FPSENCOS_d_ff1_Z[29]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_30_ ( .D(n2082), .CK(clk), .RN(n5470), .Q(
FPSENCOS_d_ff1_Z[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_31_ ( .D(n2081), .CK(clk), .RN(n5469), .Q(
FPSENCOS_d_ff1_Z[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_23_ ( .D(n1786), .CK(clk), .RN(n5499), .Q(
FPSENCOS_d_ff_Zn[23]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_23_ ( .D(n1741), .CK(clk), .RN(
n3388), .Q(FPSENCOS_d_ff2_Z[23]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_23_ ( .D(n1861), .CK(clk), .RN(
n5502), .Q(FPSENCOS_d_ff2_Y[23]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_23_ ( .D(n1703), .CK(clk), .RN(n5469),
.Q(cordic_result[23]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_24_ ( .D(n1783), .CK(clk), .RN(n5482), .Q(
FPSENCOS_d_ff_Zn[24]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_24_ ( .D(n1740), .CK(clk), .RN(
n5492), .Q(FPSENCOS_d_ff2_Z[24]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_24_ ( .D(n1702), .CK(clk), .RN(n5498),
.Q(cordic_result[24]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_25_ ( .D(n1780), .CK(clk), .RN(n5497), .Q(
FPSENCOS_d_ff_Zn[25]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_25_ ( .D(n1739), .CK(clk), .RN(
n5495), .Q(FPSENCOS_d_ff2_Z[25]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_25_ ( .D(n1778), .CK(clk), .RN(n5496), .QN(
n2275) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_25_ ( .D(n1701), .CK(clk), .RN(n5494),
.Q(cordic_result[25]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_26_ ( .D(n1777), .CK(clk), .RN(n5493), .Q(
FPSENCOS_d_ff_Zn[26]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_26_ ( .D(n1738), .CK(clk), .RN(
n5474), .Q(FPSENCOS_d_ff2_Z[26]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_26_ ( .D(n1775), .CK(clk), .RN(n5474), .QN(
n2276) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_26_ ( .D(n1700), .CK(clk), .RN(n5498),
.Q(cordic_result[26]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_27_ ( .D(n1774), .CK(clk), .RN(n5497), .Q(
FPSENCOS_d_ff_Zn[27]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_27_ ( .D(n1737), .CK(clk), .RN(
n5474), .Q(FPSENCOS_d_ff2_Z[27]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_27_ ( .D(n1773), .CK(clk), .RN(n5494), .QN(
n2277) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_27_ ( .D(n1699), .CK(clk), .RN(n5495),
.Q(cordic_result[27]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_28_ ( .D(n1771), .CK(clk), .RN(n5496), .Q(
FPSENCOS_d_ff_Zn[28]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_28_ ( .D(n1736), .CK(clk), .RN(
n5494), .Q(FPSENCOS_d_ff2_Z[28]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_28_ ( .D(n1856), .CK(clk), .RN(
n5495), .Q(FPSENCOS_d_ff2_Y[28]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_28_ ( .D(n1698), .CK(clk), .RN(n5496),
.Q(cordic_result[28]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_29_ ( .D(n1768), .CK(clk), .RN(n5493), .Q(
FPSENCOS_d_ff_Zn[29]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_29_ ( .D(n1735), .CK(clk), .RN(
n5498), .Q(FPSENCOS_d_ff2_Z[29]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_29_ ( .D(n1697), .CK(clk), .RN(n5497),
.Q(cordic_result[29]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_30_ ( .D(n1765), .CK(clk), .RN(n5474), .Q(
FPSENCOS_d_ff_Zn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_30_ ( .D(n1734), .CK(clk), .RN(
n5494), .Q(FPSENCOS_d_ff2_Z[30]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_30_ ( .D(n1696), .CK(clk), .RN(n5495),
.Q(cordic_result[30]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_1_ ( .D(n1788), .CK(clk), .RN(n5440),
.Q(FPADDSUB_Data_array_SWR[1]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_22_ ( .D(n2008), .CK(clk), .RN(n5496), .Q(
FPSENCOS_d_ff_Zn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_22_ ( .D(n1742), .CK(clk), .RN(
n5493), .Q(FPSENCOS_d_ff2_Z[22]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_22_ ( .D(n1863), .CK(clk), .RN(
n5474), .Q(FPSENCOS_d_ff2_Y[22]), .QN(n5406) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_22_ ( .D(n1862), .CK(clk), .RN(n5493),
.Q(FPSENCOS_d_ff3_sh_y_out[22]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_22_ ( .D(n1960), .CK(clk), .RN(n5498),
.Q(FPSENCOS_d_ff3_sh_x_out[22]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_15_ ( .D(n2029), .CK(clk), .RN(n5497), .Q(
FPSENCOS_d_ff_Zn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_15_ ( .D(n1749), .CK(clk), .RN(
n5474), .Q(FPSENCOS_d_ff2_Z[15]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_15_ ( .D(n1877), .CK(clk), .RN(
n5494), .Q(FPSENCOS_d_ff2_Y[15]), .QN(n5399) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_15_ ( .D(n1876), .CK(clk), .RN(n5495),
.Q(FPSENCOS_d_ff3_sh_y_out[15]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_15_ ( .D(n1974), .CK(clk), .RN(n5496),
.Q(FPSENCOS_d_ff3_sh_x_out[15]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_5_ ( .D(n1792), .CK(clk), .RN(n5440),
.QN(n2240) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_18_ ( .D(n2020), .CK(clk), .RN(n5474), .Q(
FPSENCOS_d_ff_Zn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_18_ ( .D(n1746), .CK(clk), .RN(
n5494), .Q(FPSENCOS_d_ff2_Z[18]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_18_ ( .D(n1871), .CK(clk), .RN(
n5495), .Q(FPSENCOS_d_ff2_Y[18]), .QN(n5402) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_18_ ( .D(n1870), .CK(clk), .RN(n5496),
.Q(FPSENCOS_d_ff3_sh_y_out[18]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_18_ ( .D(n1968), .CK(clk), .RN(n5493),
.Q(FPSENCOS_d_ff3_sh_x_out[18]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_2_ ( .D(n1789), .CK(clk), .RN(n5458),
.Q(FPADDSUB_Data_array_SWR[2]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_21_ ( .D(n2011), .CK(clk), .RN(n5498), .Q(
FPSENCOS_d_ff_Zn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_21_ ( .D(n1743), .CK(clk), .RN(
n5497), .Q(FPSENCOS_d_ff2_Z[21]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_21_ ( .D(n1865), .CK(clk), .RN(
n5474), .Q(FPSENCOS_d_ff2_Y[21]), .QN(n5405) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_21_ ( .D(n1864), .CK(clk), .RN(n5486),
.Q(FPSENCOS_d_ff3_sh_y_out[21]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_21_ ( .D(n1963), .CK(clk), .RN(
n5494), .QN(n2265) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_21_ ( .D(n1962), .CK(clk), .RN(n5499),
.Q(FPSENCOS_d_ff3_sh_x_out[21]), .QN(n5430) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_19_ ( .D(n2017), .CK(clk), .RN(n5494), .Q(
FPSENCOS_d_ff_Zn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_19_ ( .D(n1745), .CK(clk), .RN(
n5495), .Q(FPSENCOS_d_ff2_Z[19]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_19_ ( .D(n2016), .CK(clk), .RN(n5496), .QN(
n2273) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_19_ ( .D(n1869), .CK(clk), .RN(
n5493), .Q(FPSENCOS_d_ff2_Y[19]), .QN(n5403) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_19_ ( .D(n1868), .CK(clk), .RN(n5477),
.Q(FPSENCOS_d_ff3_sh_y_out[19]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_19_ ( .D(n1967), .CK(clk), .RN(
n5519), .QN(n2268) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_19_ ( .D(n1966), .CK(clk), .RN(n5501),
.Q(FPSENCOS_d_ff3_sh_x_out[19]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_3_ ( .D(n1790), .CK(clk), .RN(n5449),
.Q(FPADDSUB_Data_array_SWR[3]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_20_ ( .D(n2014), .CK(clk), .RN(n5469), .Q(
FPSENCOS_d_ff_Zn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_20_ ( .D(n1744), .CK(clk), .RN(
n5483), .Q(FPSENCOS_d_ff2_Z[20]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_20_ ( .D(n2013), .CK(clk), .RN(n5482), .QN(
n2274) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_20_ ( .D(n1867), .CK(clk), .RN(
n5476), .Q(FPSENCOS_d_ff2_Y[20]), .QN(n5404) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_20_ ( .D(n1866), .CK(clk), .RN(n5478),
.Q(FPSENCOS_d_ff3_sh_y_out[20]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_20_ ( .D(n1965), .CK(clk), .RN(
n5481), .QN(n2269) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_20_ ( .D(n1964), .CK(clk), .RN(n5479),
.Q(FPSENCOS_d_ff3_sh_x_out[20]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_17_ ( .D(n2023), .CK(clk), .RN(n5487), .Q(
FPSENCOS_d_ff_Zn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_17_ ( .D(n1747), .CK(clk), .RN(
n5490), .Q(FPSENCOS_d_ff2_Z[17]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_17_ ( .D(n2022), .CK(clk), .RN(n5486), .QN(
n2272) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_17_ ( .D(n1873), .CK(clk), .RN(
n5492), .Q(FPSENCOS_d_ff2_Y[17]), .QN(n5401) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_17_ ( .D(n1872), .CK(clk), .RN(n5469),
.Q(FPSENCOS_d_ff3_sh_y_out[17]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_17_ ( .D(n1971), .CK(clk), .RN(
n5519), .QN(n2267) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_17_ ( .D(n1970), .CK(clk), .RN(n5483),
.Q(FPSENCOS_d_ff3_sh_x_out[17]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_4_ ( .D(n2062), .CK(clk), .RN(n5482), .Q(
FPSENCOS_d_ff_Zn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_4_ ( .D(n1760), .CK(clk), .RN(
n5482), .Q(FPSENCOS_d_ff2_Z[4]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_4_ ( .D(n1899), .CK(clk), .RN(
n5472), .Q(FPSENCOS_d_ff2_Y[4]), .QN(n5388) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_4_ ( .D(n1898), .CK(clk), .RN(n5476),
.Q(FPSENCOS_d_ff3_sh_y_out[4]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_4_ ( .D(n2060), .CK(clk), .RN(n5472), .QN(
n2266) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_4_ ( .D(n1997), .CK(clk), .RN(
n5481), .QN(n2213) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_4_ ( .D(n1996), .CK(clk), .RN(n5483),
.Q(FPSENCOS_d_ff3_sh_x_out[4]), .QN(n5424) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_6_ ( .D(n2056), .CK(clk), .RN(n5482), .Q(
FPSENCOS_d_ff_Zn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_6_ ( .D(n1758), .CK(clk), .RN(
n5480), .Q(FPSENCOS_d_ff2_Z[6]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_6_ ( .D(n1895), .CK(clk), .RN(
n5475), .Q(FPSENCOS_d_ff2_Y[6]), .QN(n5390) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_6_ ( .D(n1894), .CK(clk), .RN(n5475),
.Q(FPSENCOS_d_ff3_sh_y_out[6]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_6_ ( .D(n1993), .CK(clk), .RN(
n5475), .QN(n2212) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_6_ ( .D(n1992), .CK(clk), .RN(n5475),
.Q(FPSENCOS_d_ff3_sh_x_out[6]), .QN(n5425) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_13_ ( .D(n2035), .CK(clk), .RN(n5475), .Q(
FPSENCOS_d_ff_Zn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_13_ ( .D(n1751), .CK(clk), .RN(
n5475), .Q(FPSENCOS_d_ff2_Z[13]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_13_ ( .D(n2034), .CK(clk), .RN(n5475), .QN(
n2215) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_13_ ( .D(n1881), .CK(clk), .RN(
n5475), .Q(FPSENCOS_d_ff2_Y[13]), .QN(n5397) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_13_ ( .D(n1880), .CK(clk), .RN(n5475),
.Q(FPSENCOS_d_ff3_sh_y_out[13]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_13_ ( .D(n1979), .CK(clk), .RN(
n5475), .QN(n2214) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_13_ ( .D(n1978), .CK(clk), .RN(n5493),
.Q(FPSENCOS_d_ff3_sh_x_out[13]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_16_ ( .D(n2026), .CK(clk), .RN(n5498), .Q(
FPSENCOS_d_ff_Zn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_16_ ( .D(n1748), .CK(clk), .RN(
n5497), .Q(FPSENCOS_d_ff2_Z[16]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_16_ ( .D(n1875), .CK(clk), .RN(
n5474), .Q(FPSENCOS_d_ff2_Y[16]), .QN(n5400) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_16_ ( .D(n1874), .CK(clk), .RN(n5494),
.Q(FPSENCOS_d_ff3_sh_y_out[16]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_16_ ( .D(n1972), .CK(clk), .RN(n5495),
.Q(FPSENCOS_d_ff3_sh_x_out[16]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_15_ ( .D(n1802), .CK(clk), .RN(n5438), .QN(n2241) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_8_ ( .D(n2050), .CK(clk), .RN(n5496), .Q(
FPSENCOS_d_ff_Zn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_8_ ( .D(n1756), .CK(clk), .RN(
n5493), .Q(FPSENCOS_d_ff2_Z[8]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_8_ ( .D(n1891), .CK(clk), .RN(
n5499), .Q(FPSENCOS_d_ff2_Y[8]), .QN(n5392) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_8_ ( .D(n1890), .CK(clk), .RN(n5500),
.Q(FPSENCOS_d_ff3_sh_y_out[8]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_8_ ( .D(n1989), .CK(clk), .RN(
n5470), .QN(n2263) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_8_ ( .D(n1988), .CK(clk), .RN(n5500),
.Q(FPSENCOS_d_ff3_sh_x_out[8]), .QN(n5426) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_12_ ( .D(n1799), .CK(clk), .RN(n5463), .QN(n2242) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_11_ ( .D(n2041), .CK(clk), .RN(n5469), .Q(
FPSENCOS_d_ff_Zn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_11_ ( .D(n1753), .CK(clk), .RN(
n5469), .Q(FPSENCOS_d_ff2_Z[11]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_11_ ( .D(n1885), .CK(clk), .RN(
n5469), .Q(FPSENCOS_d_ff2_Y[11]), .QN(n5395) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_11_ ( .D(n1884), .CK(clk), .RN(n5501),
.Q(FPSENCOS_d_ff3_sh_y_out[11]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_11_ ( .D(n1983), .CK(clk), .RN(
n5483), .QN(n2256) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_11_ ( .D(n1982), .CK(clk), .RN(n5483),
.Q(FPSENCOS_d_ff3_sh_x_out[11]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_14_ ( .D(n2032), .CK(clk), .RN(n5479), .Q(
FPSENCOS_d_ff_Zn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_14_ ( .D(n1750), .CK(clk), .RN(
n5490), .Q(FPSENCOS_d_ff2_Z[14]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_14_ ( .D(n2031), .CK(clk), .RN(n5482), .QN(
n2271) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_14_ ( .D(n1879), .CK(clk), .RN(
n5472), .Q(FPSENCOS_d_ff2_Y[14]), .QN(n5398) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_14_ ( .D(n1878), .CK(clk), .RN(n5480),
.Q(FPSENCOS_d_ff3_sh_y_out[14]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_14_ ( .D(n1977), .CK(clk), .RN(
n5483), .QN(n2254) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_14_ ( .D(n1976), .CK(clk), .RN(n5480),
.Q(FPSENCOS_d_ff3_sh_x_out[14]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_10_ ( .D(n2044), .CK(clk), .RN(n5480), .Q(
FPSENCOS_d_ff_Zn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_10_ ( .D(n1754), .CK(clk), .RN(
n5480), .Q(FPSENCOS_d_ff2_Z[10]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_10_ ( .D(n1887), .CK(clk), .RN(
n5486), .Q(FPSENCOS_d_ff2_Y[10]), .QN(n5394) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_10_ ( .D(n1886), .CK(clk), .RN(n5492),
.Q(FPSENCOS_d_ff3_sh_y_out[10]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_10_ ( .D(n1985), .CK(clk), .RN(
n5484), .QN(n2260) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_10_ ( .D(n1984), .CK(clk), .RN(n5486),
.Q(FPSENCOS_d_ff3_sh_x_out[10]), .QN(n5428) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_11_ ( .D(n1798), .CK(clk), .RN(n5461), .QN(n2207) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_12_ ( .D(n2038), .CK(clk), .RN(n5492), .Q(
FPSENCOS_d_ff_Zn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_12_ ( .D(n1752), .CK(clk), .RN(
n5486), .Q(FPSENCOS_d_ff2_Z[12]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_12_ ( .D(n1883), .CK(clk), .RN(
n5488), .Q(FPSENCOS_d_ff2_Y[12]), .QN(n5396) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_12_ ( .D(n1882), .CK(clk), .RN(n5487),
.Q(FPSENCOS_d_ff3_sh_y_out[12]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_12_ ( .D(n1981), .CK(clk), .RN(
n5473), .QN(n2261) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_12_ ( .D(n1980), .CK(clk), .RN(n5501),
.Q(FPSENCOS_d_ff3_sh_x_out[12]), .QN(n5429) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_31_ ( .D(n1909), .CK(clk), .RN(n5500), .Q(
FPSENCOS_d_ff_Zn[31]) );
DFFRXLTS FPSENCOS_reg_sign_Q_reg_0_ ( .D(n1732), .CK(clk), .RN(n5500), .QN(
n2249) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_31_ ( .D(n1908), .CK(clk), .RN(n5500), .QN(
n2248) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_31_ ( .D(n1845), .CK(clk), .RN(
n5470), .Q(FPSENCOS_d_ff2_Y[31]), .QN(n5407) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_31_ ( .D(n1844), .CK(clk), .RN(n5469),
.Q(FPSENCOS_d_ff3_sh_y_out[31]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_31_ ( .D(n1727), .CK(clk), .RN(n5470), .QN(
n2209) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_31_ ( .D(n1943), .CK(clk), .RN(
n5501), .QN(n2257) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_31_ ( .D(n1942), .CK(clk), .RN(n5501),
.Q(FPSENCOS_d_ff3_sh_x_out[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_3_ ( .D(n2065), .CK(clk), .RN(n5501), .Q(
FPSENCOS_d_ff_Zn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_3_ ( .D(n1761), .CK(clk), .RN(
n5499), .Q(FPSENCOS_d_ff2_Z[3]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_3_ ( .D(n1901), .CK(clk), .RN(
n5469), .Q(FPSENCOS_d_ff2_Y[3]), .QN(n5387) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_3_ ( .D(n1900), .CK(clk), .RN(n5469),
.Q(FPSENCOS_d_ff3_sh_y_out[3]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_3_ ( .D(n1999), .CK(clk), .RN(
n5500), .QN(n2252) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_3_ ( .D(n1998), .CK(clk), .RN(n5470),
.Q(FPSENCOS_d_ff3_sh_x_out[3]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_3_ ( .D(n1723), .CK(clk), .RN(n5469),
.Q(cordic_result[3]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_2_ ( .D(n2068), .CK(clk), .RN(n5473), .Q(
FPSENCOS_d_ff_Zn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_2_ ( .D(n1762), .CK(clk), .RN(
n5499), .Q(FPSENCOS_d_ff2_Z[2]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_2_ ( .D(n1903), .CK(clk), .RN(
n5499), .Q(FPSENCOS_d_ff2_Y[2]), .QN(n5386) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_2_ ( .D(n1902), .CK(clk), .RN(n5487),
.Q(FPSENCOS_d_ff3_sh_y_out[2]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_2_ ( .D(n2001), .CK(clk), .RN(
n5485), .QN(n2259) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_2_ ( .D(n2000), .CK(clk), .RN(n5484),
.Q(FPSENCOS_d_ff3_sh_x_out[2]), .QN(n5423) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_2_ ( .D(n1724), .CK(clk), .RN(n5488),
.Q(cordic_result[2]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_7_ ( .D(n2053), .CK(clk), .RN(n5488), .Q(
FPSENCOS_d_ff_Zn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_7_ ( .D(n1757), .CK(clk), .RN(
n5486), .Q(FPSENCOS_d_ff2_Z[7]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_7_ ( .D(n1893), .CK(clk), .RN(
n5484), .Q(FPSENCOS_d_ff2_Y[7]), .QN(n5391) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_7_ ( .D(n1892), .CK(clk), .RN(n5491),
.Q(FPSENCOS_d_ff3_sh_y_out[7]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_7_ ( .D(n1991), .CK(clk), .RN(
n5488), .QN(n2255) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_7_ ( .D(n1990), .CK(clk), .RN(n5471),
.Q(FPSENCOS_d_ff3_sh_x_out[7]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_7_ ( .D(n1719), .CK(clk), .RN(n5485),
.Q(cordic_result[7]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_0_ ( .D(n2074), .CK(clk), .RN(n5492), .Q(
FPSENCOS_d_ff_Zn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_0_ ( .D(n1764), .CK(clk), .RN(
n5471), .Q(FPSENCOS_d_ff2_Z[0]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_0_ ( .D(n1907), .CK(clk), .RN(
n5491), .Q(FPSENCOS_d_ff2_Y[0]), .QN(n5384) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_0_ ( .D(n1906), .CK(clk), .RN(n5471),
.Q(FPSENCOS_d_ff3_sh_y_out[0]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_0_ ( .D(n2005), .CK(clk), .RN(
n5491), .QN(n2262) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_0_ ( .D(n2004), .CK(clk), .RN(n5488),
.Q(FPSENCOS_d_ff3_sh_x_out[0]), .QN(n5421) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_0_ ( .D(n1726), .CK(clk), .RN(n5472),
.Q(cordic_result[0]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_1_ ( .D(n2071), .CK(clk), .RN(n5480), .Q(
FPSENCOS_d_ff_Zn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_1_ ( .D(n1763), .CK(clk), .RN(
n5478), .Q(FPSENCOS_d_ff2_Z[1]) );
DFFRXLTS FPSENCOS_d_ff4_Yn_Q_reg_1_ ( .D(n2070), .CK(clk), .RN(n5472), .QN(
n2270) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_1_ ( .D(n1905), .CK(clk), .RN(
n5479), .Q(FPSENCOS_d_ff2_Y[1]), .QN(n5385) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_1_ ( .D(n1904), .CK(clk), .RN(n5490),
.Q(FPSENCOS_d_ff3_sh_y_out[1]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_1_ ( .D(n2003), .CK(clk), .RN(
n5478), .QN(n2258) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_1_ ( .D(n2002), .CK(clk), .RN(n5480),
.Q(FPSENCOS_d_ff3_sh_x_out[1]), .QN(n5422) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_1_ ( .D(n1725), .CK(clk), .RN(n5483),
.Q(cordic_result[1]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_9_ ( .D(n2047), .CK(clk), .RN(n5482), .Q(
FPSENCOS_d_ff_Zn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_9_ ( .D(n1755), .CK(clk), .RN(
n5478), .Q(FPSENCOS_d_ff2_Z[9]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_9_ ( .D(n1889), .CK(clk), .RN(
n5476), .Q(FPSENCOS_d_ff2_Y[9]), .QN(n5393) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_9_ ( .D(n1888), .CK(clk), .RN(n5482),
.Q(FPSENCOS_d_ff3_sh_y_out[9]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_9_ ( .D(n1987), .CK(clk), .RN(
n5481), .QN(n2264) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_9_ ( .D(n1986), .CK(clk), .RN(n5472),
.Q(FPSENCOS_d_ff3_sh_x_out[9]), .QN(n5427) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_9_ ( .D(n1717), .CK(clk), .RN(n5479),
.Q(cordic_result[9]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_5_ ( .D(n2059), .CK(clk), .RN(n5478), .Q(
FPSENCOS_d_ff_Zn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_5_ ( .D(n1759), .CK(clk), .RN(
n5480), .Q(FPSENCOS_d_ff2_Z[5]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_5_ ( .D(n1897), .CK(clk), .RN(
n5483), .Q(FPSENCOS_d_ff2_Y[5]), .QN(n5389) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_5_ ( .D(n1896), .CK(clk), .RN(n5476),
.Q(FPSENCOS_d_ff3_sh_y_out[5]) );
DFFRXLTS FPSENCOS_reg_val_muxX_2stage_Q_reg_5_ ( .D(n1995), .CK(clk), .RN(
n5479), .QN(n2253) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_5_ ( .D(n1994), .CK(clk), .RN(n5483),
.Q(FPSENCOS_d_ff3_sh_x_out[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_5_ ( .D(n1721), .CK(clk), .RN(n5472),
.Q(cordic_result[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_31_ ( .D(n1695), .CK(clk), .RN(n5479),
.Q(cordic_result[31]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_12_ ( .D(n1714), .CK(clk), .RN(n5481),
.Q(cordic_result[12]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_10_ ( .D(n1716), .CK(clk), .RN(n5476),
.Q(cordic_result[10]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_14_ ( .D(n1712), .CK(clk), .RN(n5478),
.Q(cordic_result[14]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_11_ ( .D(n1715), .CK(clk), .RN(n5479),
.Q(cordic_result[11]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_8_ ( .D(n1718), .CK(clk), .RN(n5490),
.Q(cordic_result[8]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_16_ ( .D(n1710), .CK(clk), .RN(n5490),
.Q(cordic_result[16]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_13_ ( .D(n1713), .CK(clk), .RN(n5480),
.Q(cordic_result[13]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_6_ ( .D(n1720), .CK(clk), .RN(n5481),
.Q(cordic_result[6]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_4_ ( .D(n1722), .CK(clk), .RN(n5483),
.Q(cordic_result[4]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_17_ ( .D(n1709), .CK(clk), .RN(n5481),
.Q(cordic_result[17]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_20_ ( .D(n1706), .CK(clk), .RN(n5490),
.Q(cordic_result[20]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_19_ ( .D(n1707), .CK(clk), .RN(n5490),
.Q(cordic_result[19]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_21_ ( .D(n1705), .CK(clk), .RN(n5476),
.Q(cordic_result[21]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_18_ ( .D(n1708), .CK(clk), .RN(n5490),
.Q(cordic_result[18]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_15_ ( .D(n1711), .CK(clk), .RN(n5483),
.Q(cordic_result[15]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_22_ ( .D(n1704), .CK(clk), .RN(n5482),
.Q(cordic_result[22]) );
DFFRXLTS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_0_ ( .D(n1787), .CK(clk), .RN(n3389),
.Q(FPADDSUB_Data_array_SWR[0]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n1624), .CK(clk),
.RN(n5503), .Q(FPMULT_Op_MY[31]) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n1687), .CK(clk),
.RN(n5503), .QN(n2238) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n1681), .CK(clk),
.RN(n5503), .QN(n2227) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n1679), .CK(clk),
.RN(n5503), .Q(FPMULT_Op_MX[21]), .QN(n2391) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n1668), .CK(clk),
.RN(n5512), .Q(FPMULT_Op_MX[10]), .QN(n2377) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n1666), .CK(clk),
.RN(n5504), .Q(FPMULT_Op_MX[8]) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n1661), .CK(clk),
.RN(n5504), .Q(FPMULT_Op_MX[3]) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n1660), .CK(clk),
.RN(n5512), .Q(FPMULT_Op_MX[2]), .QN(n2382) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n1657), .CK(clk),
.RN(n2200), .Q(FPMULT_Op_MX[31]) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n1600), .CK(clk),
.RN(n5505), .Q(FPMULT_Add_result[20]), .QN(n5381) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n1602), .CK(clk),
.RN(n5505), .Q(FPMULT_Add_result[18]), .QN(n5379) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n1604), .CK(clk),
.RN(n5505), .Q(FPMULT_Add_result[16]), .QN(n5380) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n1606), .CK(clk),
.RN(n5505), .QN(n2279) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n1607), .CK(clk),
.RN(n5505), .Q(FPMULT_Add_result[13]) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n1608), .CK(clk),
.RN(n5505), .QN(n2210) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n1609), .CK(clk),
.RN(n5505), .QN(n2251) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n1611), .CK(clk), .RN(
n5505), .QN(n2250) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n1612), .CK(clk), .RN(
n5506), .Q(FPMULT_Add_result[8]), .QN(n5382) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n1614), .CK(clk), .RN(
n5506), .Q(FPMULT_Add_result[6]), .QN(n5383) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n1615), .CK(clk), .RN(
n5506), .QN(n2278) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n1616), .CK(clk), .RN(
n5506), .QN(n2211) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n1618), .CK(clk), .RN(
n5506), .Q(FPMULT_Add_result[2]) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n1620), .CK(clk), .RN(
n5506), .Q(FPMULT_Add_result[0]) );
DFFRXLTS FPMULT_Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n1597), .CK(clk),
.RN(n5506), .Q(FPMULT_Add_result[23]), .QN(n5369) );
DFFRXLTS FPMULT_Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n1596), .CK(clk),
.RN(n5506), .Q(FPMULT_FSM_add_overflow_flag) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n1656), .CK(clk),
.RN(n5506), .QN(n2236) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n1654), .CK(clk),
.RN(n5504), .QN(n2233) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n1652), .CK(clk),
.RN(n5507), .QN(n2231) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n1651), .CK(clk),
.RN(n5507), .QN(n2205) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n1650), .CK(clk),
.RN(n5507), .QN(n2202) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n1646), .CK(clk),
.RN(n5507), .QN(n2392) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n1634), .CK(clk),
.RN(n2200), .Q(FPMULT_Op_MY[8]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n1633), .CK(clk),
.RN(n2200), .Q(FPMULT_Op_MY[7]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n1628), .CK(clk),
.RN(n5508), .QN(n2397) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n1627), .CK(clk),
.RN(n5510), .Q(FPMULT_Op_MY[1]), .QN(n2385) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n1626), .CK(clk),
.RN(n5509), .Q(FPMULT_Op_MY[0]), .QN(n2399) );
DFFRXLTS FPMULT_Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n1625), .CK(
clk), .RN(n5504), .Q(FPMULT_zero_flag), .QN(n5408) );
DFFRXLTS FPMULT_Exp_module_exp_result_m_Q_reg_1_ ( .D(n1593), .CK(clk), .RN(
n5508), .QN(n2230) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_45_ ( .D(n1574), .CK(clk),
.RN(n5472), .Q(FPMULT_P_Sgf[45]), .QN(n5409) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_44_ ( .D(n1573), .CK(clk),
.RN(n5482), .QN(n2394) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_42_ ( .D(n1571), .CK(clk),
.RN(n5479), .Q(FPMULT_P_Sgf[42]), .QN(n5410) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_41_ ( .D(n1570), .CK(clk),
.RN(n5480), .Q(FPMULT_P_Sgf[41]), .QN(n5411) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_40_ ( .D(n1569), .CK(clk),
.RN(n5481), .Q(FPMULT_P_Sgf[40]), .QN(n5412) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_39_ ( .D(n1568), .CK(clk),
.RN(n5490), .Q(FPMULT_P_Sgf[39]), .QN(n5413) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_38_ ( .D(n1567), .CK(clk),
.RN(n5472), .Q(FPMULT_P_Sgf[38]), .QN(n5414) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_37_ ( .D(n1566), .CK(clk),
.RN(n5481), .QN(n2246) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_34_ ( .D(n1563), .CK(clk),
.RN(n5482), .QN(n2208) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_33_ ( .D(n1562), .CK(clk),
.RN(n5478), .QN(n2247) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_31_ ( .D(n1560), .CK(clk),
.RN(n5480), .QN(n2244) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_28_ ( .D(n1557), .CK(clk),
.RN(n5481), .Q(FPMULT_P_Sgf[28]), .QN(n5415) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_26_ ( .D(n1555), .CK(clk),
.RN(n5483), .Q(FPMULT_P_Sgf[26]), .QN(n5416) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_22_ ( .D(n1551), .CK(clk),
.RN(n5477), .Q(FPMULT_P_Sgf[22]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_13_ ( .D(n1542), .CK(clk),
.RN(n5475), .Q(FPMULT_P_Sgf[13]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_9_ ( .D(n1538), .CK(clk),
.RN(n5477), .Q(FPMULT_P_Sgf[9]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_8_ ( .D(n1537), .CK(clk),
.RN(n5477), .Q(FPMULT_P_Sgf[8]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_4_ ( .D(n1533), .CK(clk),
.RN(n5475), .Q(FPMULT_P_Sgf[4]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_2_ ( .D(n1531), .CK(clk),
.RN(n5477), .Q(FPMULT_P_Sgf[2]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_0_ ( .D(n1529), .CK(clk),
.RN(n5477), .Q(FPMULT_P_Sgf[0]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n1525), .CK(
clk), .RN(n5509), .Q(FPMULT_Sgf_normalized_result[20]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n1522), .CK(
clk), .RN(n5509), .QN(n2235) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n1520), .CK(
clk), .RN(n5508), .QN(n2229) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n1519), .CK(
clk), .RN(n5503), .Q(FPMULT_Sgf_normalized_result[14]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n1518), .CK(
clk), .RN(n5508), .QN(n2204) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n1515), .CK(
clk), .RN(n5508), .Q(FPMULT_Sgf_normalized_result[10]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n1513), .CK(
clk), .RN(n5510), .Q(FPMULT_Sgf_normalized_result[8]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n1512), .CK(
clk), .RN(n5509), .QN(n2221) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n1510), .CK(
clk), .RN(n5505), .QN(n2217) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n1509), .CK(
clk), .RN(n5509), .Q(FPMULT_Sgf_normalized_result[4]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n1507), .CK(
clk), .RN(n5506), .QN(n2216) );
DFFRXLTS FPMULT_Exp_module_Underflow_m_Q_reg_0_ ( .D(n1586), .CK(clk), .RN(
n5508), .QN(n2228) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
n1576), .CK(clk), .RN(n5509), .Q(mult_result[31]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
n1584), .CK(clk), .RN(n5508), .Q(mult_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
n1583), .CK(clk), .RN(n5510), .Q(mult_result[24]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
n1582), .CK(clk), .RN(n5505), .Q(mult_result[25]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
n1581), .CK(clk), .RN(n5509), .Q(mult_result[26]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
n1580), .CK(clk), .RN(n5503), .Q(mult_result[27]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
n1579), .CK(clk), .RN(n5508), .Q(mult_result[28]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
n1578), .CK(clk), .RN(n5510), .Q(mult_result[29]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
n1577), .CK(clk), .RN(n5510), .Q(mult_result[30]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(
n1504), .CK(clk), .RN(n5510), .Q(mult_result[0]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(
n1503), .CK(clk), .RN(n5512), .Q(mult_result[1]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(
n1502), .CK(clk), .RN(n5510), .Q(mult_result[2]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(
n1501), .CK(clk), .RN(n5508), .Q(mult_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(
n1500), .CK(clk), .RN(n5513), .Q(mult_result[4]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(
n1499), .CK(clk), .RN(n5510), .Q(mult_result[5]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(
n1498), .CK(clk), .RN(n5513), .Q(mult_result[6]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(
n1497), .CK(clk), .RN(n5511), .Q(mult_result[7]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(
n1496), .CK(clk), .RN(n5513), .Q(mult_result[8]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
n1495), .CK(clk), .RN(n5511), .Q(mult_result[9]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
n1494), .CK(clk), .RN(n5513), .Q(mult_result[10]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
n1493), .CK(clk), .RN(n5511), .Q(mult_result[11]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
n1492), .CK(clk), .RN(n5513), .Q(mult_result[12]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
n1491), .CK(clk), .RN(n5514), .Q(mult_result[13]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
n1490), .CK(clk), .RN(n5514), .Q(mult_result[14]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
n1489), .CK(clk), .RN(n5514), .Q(mult_result[15]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
n1488), .CK(clk), .RN(n5514), .Q(mult_result[16]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
n1487), .CK(clk), .RN(n5514), .Q(mult_result[17]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
n1486), .CK(clk), .RN(n5511), .Q(mult_result[18]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
n1485), .CK(clk), .RN(n5511), .Q(mult_result[19]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
n1484), .CK(clk), .RN(n5513), .Q(mult_result[20]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
n1483), .CK(clk), .RN(n5511), .Q(mult_result[21]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
n1481), .CK(clk), .RN(n5513), .Q(mult_result[22]) );
DFFSX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n5473), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n1478), .CK(clk), .RN(
n5445), .Q(FPADDSUB_Shift_amount_SHT1_EWR[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n1477), .CK(clk), .RN(
n5447), .Q(FPADDSUB_Shift_amount_SHT1_EWR[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n1476), .CK(clk), .RN(
n5462), .Q(FPADDSUB_Shift_amount_SHT1_EWR[1]), .QN(n5337) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n1475), .CK(clk), .RN(
n5463), .Q(FPADDSUB_Shift_amount_SHT1_EWR[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n1474), .CK(clk), .RN(
n5459), .Q(FPADDSUB_Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_27_ ( .D(n1461), .CK(clk), .RN(n5462),
.QN(n2245) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_28_ ( .D(n1460), .CK(clk), .RN(n5443),
.Q(FPADDSUB_DMP_EXP_EWSW[28]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_29_ ( .D(n1459), .CK(clk), .RN(n5461),
.Q(FPADDSUB_DMP_EXP_EWSW[29]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_30_ ( .D(n1458), .CK(clk), .RN(n5460),
.Q(FPADDSUB_DMP_EXP_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1457), .CK(clk), .RN(n5459),
.Q(FPADDSUB_DMP_SHT1_EWSW[23]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1456), .CK(clk), .RN(n5460),
.Q(FPADDSUB_DMP_SHT2_EWSW[23]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_23_ ( .D(n1455), .CK(clk), .RN(n3390),
.Q(FPADDSUB_DMP_SFG[23]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1454), .CK(clk), .RN(
n5442), .Q(FPADDSUB_DMP_exp_NRM_EW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1452), .CK(clk), .RN(n5468),
.Q(FPADDSUB_DMP_SHT1_EWSW[24]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1451), .CK(clk), .RN(n5438),
.Q(FPADDSUB_DMP_SHT2_EWSW[24]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_24_ ( .D(n1450), .CK(clk), .RN(n5457),
.Q(FPADDSUB_DMP_SFG[24]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1449), .CK(clk), .RN(
n5446), .Q(FPADDSUB_DMP_exp_NRM_EW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1447), .CK(clk), .RN(n5445),
.Q(FPADDSUB_DMP_SHT1_EWSW[25]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1446), .CK(clk), .RN(n5441),
.Q(FPADDSUB_DMP_SHT2_EWSW[25]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_25_ ( .D(n1445), .CK(clk), .RN(n5446),
.Q(FPADDSUB_DMP_SFG[25]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1444), .CK(clk), .RN(
n5439), .Q(FPADDSUB_DMP_exp_NRM_EW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1442), .CK(clk), .RN(n3389),
.Q(FPADDSUB_DMP_SHT1_EWSW[26]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1441), .CK(clk), .RN(n3390),
.Q(FPADDSUB_DMP_SHT2_EWSW[26]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_26_ ( .D(n1440), .CK(clk), .RN(n5456),
.Q(FPADDSUB_DMP_SFG[26]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1439), .CK(clk), .RN(
n5465), .Q(FPADDSUB_DMP_exp_NRM_EW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1437), .CK(clk), .RN(n5439),
.Q(FPADDSUB_DMP_SHT1_EWSW[27]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1436), .CK(clk), .RN(n5466),
.Q(FPADDSUB_DMP_SHT2_EWSW[27]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_27_ ( .D(n1435), .CK(clk), .RN(n5468),
.Q(FPADDSUB_DMP_SFG[27]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1434), .CK(clk), .RN(
n5438), .Q(FPADDSUB_DMP_exp_NRM_EW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1432), .CK(clk), .RN(n5446),
.Q(FPADDSUB_DMP_SHT1_EWSW[28]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1431), .CK(clk), .RN(n5468),
.Q(FPADDSUB_DMP_SHT2_EWSW[28]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_28_ ( .D(n1430), .CK(clk), .RN(n5446),
.Q(FPADDSUB_DMP_SFG[28]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1429), .CK(clk), .RN(
n5467), .Q(FPADDSUB_DMP_exp_NRM_EW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1427), .CK(clk), .RN(n5467),
.Q(FPADDSUB_DMP_SHT1_EWSW[29]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1426), .CK(clk), .RN(n5442),
.Q(FPADDSUB_DMP_SHT2_EWSW[29]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_29_ ( .D(n1425), .CK(clk), .RN(n5466),
.Q(FPADDSUB_DMP_SFG[29]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1424), .CK(clk), .RN(
n5467), .Q(FPADDSUB_DMP_exp_NRM_EW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1422), .CK(clk), .RN(n5442),
.Q(FPADDSUB_DMP_SHT1_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1421), .CK(clk), .RN(n5466),
.Q(FPADDSUB_DMP_SHT2_EWSW[30]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_30_ ( .D(n1420), .CK(clk), .RN(n5465),
.Q(FPADDSUB_DMP_SFG[30]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1419), .CK(clk), .RN(
n5442), .Q(FPADDSUB_DMP_exp_NRM_EW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_24_ ( .D(n1416), .CK(clk), .RN(n5465),
.Q(FPADDSUB_DmP_EXP_EWSW[24]), .QN(n5358) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_25_ ( .D(n1415), .CK(clk), .RN(n5441),
.Q(FPADDSUB_DmP_EXP_EWSW[25]), .QN(n5363) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_26_ ( .D(n1414), .CK(clk), .RN(n5450),
.Q(FPADDSUB_DmP_EXP_EWSW[26]), .QN(n5362) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1412), .CK(clk), .RN(n5449), .Q(underflow_flag_addsubt) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1411), .CK(clk), .RN(n5465), .Q(overflow_flag_addsubt) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1409), .CK(clk), .RN(
n5468), .Q(FPADDSUB_LZD_output_NRM2_EW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_22_ ( .D(n1407), .CK(clk), .RN(n5447),
.Q(FPADDSUB_DmP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n1406), .CK(clk), .RN(
n2295), .Q(FPADDSUB_DmP_mant_SHT1_SW[22]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_15_ ( .D(n1404), .CK(clk), .RN(n5451),
.Q(FPADDSUB_DmP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n1403), .CK(clk), .RN(
n5441), .Q(FPADDSUB_DmP_mant_SHT1_SW[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_18_ ( .D(n1401), .CK(clk), .RN(n5449),
.Q(FPADDSUB_DmP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n1400), .CK(clk), .RN(
n5448), .Q(FPADDSUB_DmP_mant_SHT1_SW[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_21_ ( .D(n1398), .CK(clk), .RN(n5447),
.Q(FPADDSUB_DmP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n1397), .CK(clk), .RN(
n5450), .Q(FPADDSUB_DmP_mant_SHT1_SW[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_19_ ( .D(n1395), .CK(clk), .RN(n5452),
.Q(FPADDSUB_DmP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n1394), .CK(clk), .RN(
n5441), .Q(FPADDSUB_DmP_mant_SHT1_SW[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_20_ ( .D(n1392), .CK(clk), .RN(n5449),
.Q(FPADDSUB_DmP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n1391), .CK(clk), .RN(
n5448), .Q(FPADDSUB_DmP_mant_SHT1_SW[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_17_ ( .D(n1389), .CK(clk), .RN(n5447),
.Q(FPADDSUB_DmP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n1388), .CK(clk), .RN(
n2295), .Q(FPADDSUB_DmP_mant_SHT1_SW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_4_ ( .D(n1386), .CK(clk), .RN(n5451),
.Q(FPADDSUB_DmP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1385), .CK(clk), .RN(
n5441), .Q(FPADDSUB_DmP_mant_SHT1_SW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_6_ ( .D(n1383), .CK(clk), .RN(n5449),
.Q(FPADDSUB_DmP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1382), .CK(clk), .RN(
n5448), .Q(FPADDSUB_DmP_mant_SHT1_SW[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_13_ ( .D(n1380), .CK(clk), .RN(n5447),
.Q(FPADDSUB_DmP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n1379), .CK(clk), .RN(
n5450), .Q(FPADDSUB_DmP_mant_SHT1_SW[13]), .QN(n5338) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_16_ ( .D(n1377), .CK(clk), .RN(n5449),
.Q(FPADDSUB_DmP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n1376), .CK(clk), .RN(
n5448), .Q(FPADDSUB_DmP_mant_SHT1_SW[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_8_ ( .D(n1374), .CK(clk), .RN(n5447),
.Q(FPADDSUB_DmP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1373), .CK(clk), .RN(
n5450), .Q(FPADDSUB_DmP_mant_SHT1_SW[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_11_ ( .D(n1371), .CK(clk), .RN(n5452),
.Q(FPADDSUB_DmP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n1370), .CK(clk), .RN(
n5441), .Q(FPADDSUB_DmP_mant_SHT1_SW[11]), .QN(n5339) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_14_ ( .D(n1368), .CK(clk), .RN(n2295),
.Q(FPADDSUB_DmP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1367), .CK(clk), .RN(
n5451), .Q(FPADDSUB_DmP_mant_SHT1_SW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_10_ ( .D(n1365), .CK(clk), .RN(n5452),
.Q(FPADDSUB_DmP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n1364), .CK(clk), .RN(
n2295), .Q(FPADDSUB_DmP_mant_SHT1_SW[10]), .QN(n5340) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1362), .CK(clk), .RN(n5451),
.Q(FPADDSUB_SIGN_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1361), .CK(clk), .RN(n5441), .Q(FPADDSUB_SIGN_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1360), .CK(clk), .RN(n5449), .Q(FPADDSUB_SIGN_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1359), .CK(clk), .RN(n5448),
.Q(FPADDSUB_SIGN_FLAG_SFG) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1358), .CK(clk), .RN(n5447),
.Q(FPADDSUB_SIGN_FLAG_NRM) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1357), .CK(clk), .RN(
n5465), .Q(FPADDSUB_SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1355), .CK(clk), .RN(n5450),
.Q(FPADDSUB_OP_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1354), .CK(clk), .RN(n5452), .Q(FPADDSUB_OP_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1353), .CK(clk), .RN(n5441), .Q(FPADDSUB_OP_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n1330), .CK(clk), .RN(
n5439), .Q(FPADDSUB_LZD_output_NRM2_EW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_3_ ( .D(n1328), .CK(clk), .RN(n5458),
.Q(FPADDSUB_DmP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1327), .CK(clk), .RN(
n5457), .Q(FPADDSUB_DmP_mant_SHT1_SW[3]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_3_ ( .D(n1326), .CK(clk), .RN(n5456),
.Q(FPADDSUB_DMP_EXP_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1325), .CK(clk), .RN(n5453),
.Q(FPADDSUB_DMP_SHT1_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_3_ ( .D(n1324), .CK(clk), .RN(n5454),
.Q(FPADDSUB_DMP_SHT2_EWSW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n1322), .CK(clk), .RN(
n5467), .Q(FPADDSUB_LZD_output_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n1318), .CK(clk), .RN(
n5446), .Q(FPADDSUB_LZD_output_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1314), .CK(clk), .RN(
n5468), .Q(FPADDSUB_LZD_output_NRM2_EW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_2_ ( .D(n1312), .CK(clk), .RN(n5454),
.Q(FPADDSUB_DmP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1311), .CK(clk), .RN(
n5456), .Q(FPADDSUB_DmP_mant_SHT1_SW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_2_ ( .D(n1310), .CK(clk), .RN(n5453),
.Q(FPADDSUB_DMP_EXP_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1309), .CK(clk), .RN(n5440),
.Q(FPADDSUB_DMP_SHT1_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_2_ ( .D(n1308), .CK(clk), .RN(n5456),
.Q(FPADDSUB_DMP_SHT2_EWSW[2]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_7_ ( .D(n1305), .CK(clk), .RN(n5453),
.Q(FPADDSUB_DmP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1304), .CK(clk), .RN(
n5457), .Q(FPADDSUB_DmP_mant_SHT1_SW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_7_ ( .D(n1303), .CK(clk), .RN(n5457),
.Q(FPADDSUB_DMP_EXP_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1302), .CK(clk), .RN(n5440),
.Q(FPADDSUB_DMP_SHT1_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_7_ ( .D(n1301), .CK(clk), .RN(n5454),
.Q(FPADDSUB_DMP_SHT2_EWSW[7]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_0_ ( .D(n1298), .CK(clk), .RN(n5456),
.Q(FPADDSUB_DmP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1297), .CK(clk), .RN(
n5453), .Q(FPADDSUB_DmP_mant_SHT1_SW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_0_ ( .D(n1296), .CK(clk), .RN(n5457),
.Q(FPADDSUB_DMP_EXP_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1295), .CK(clk), .RN(n5454),
.Q(FPADDSUB_DMP_SHT1_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_0_ ( .D(n1294), .CK(clk), .RN(n5458),
.Q(FPADDSUB_DMP_SHT2_EWSW[0]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_1_ ( .D(n1291), .CK(clk), .RN(n5458),
.Q(FPADDSUB_DmP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1290), .CK(clk), .RN(
n5455), .Q(FPADDSUB_DmP_mant_SHT1_SW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_1_ ( .D(n1289), .CK(clk), .RN(n5455),
.Q(FPADDSUB_DMP_EXP_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1288), .CK(clk), .RN(n5454),
.Q(FPADDSUB_DMP_SHT1_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_1_ ( .D(n1287), .CK(clk), .RN(n5458),
.Q(FPADDSUB_DMP_SHT2_EWSW[1]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_9_ ( .D(n1284), .CK(clk), .RN(n5454),
.Q(FPADDSUB_DmP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1283), .CK(clk), .RN(
n5440), .Q(FPADDSUB_DmP_mant_SHT1_SW[9]), .QN(n5341) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_9_ ( .D(n1282), .CK(clk), .RN(n5457),
.Q(FPADDSUB_DMP_EXP_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1281), .CK(clk), .RN(n5453),
.Q(FPADDSUB_DMP_SHT1_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1280), .CK(clk), .RN(n5440),
.Q(FPADDSUB_DMP_SHT2_EWSW[9]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_5_ ( .D(n1277), .CK(clk), .RN(n5458),
.Q(FPADDSUB_DmP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1276), .CK(clk), .RN(
n5458), .Q(FPADDSUB_DmP_mant_SHT1_SW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_5_ ( .D(n1275), .CK(clk), .RN(n5458),
.Q(FPADDSUB_DMP_EXP_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1274), .CK(clk), .RN(n5440),
.Q(FPADDSUB_DMP_SHT1_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_5_ ( .D(n1273), .CK(clk), .RN(n5453),
.Q(FPADDSUB_DMP_SHT2_EWSW[5]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DmP_Q_reg_12_ ( .D(n1271), .CK(clk), .RN(n5453),
.Q(FPADDSUB_DmP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n1270), .CK(clk), .RN(
n5453), .Q(FPADDSUB_DmP_mant_SHT1_SW[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_12_ ( .D(n1269), .CK(clk), .RN(n5457),
.Q(FPADDSUB_DMP_EXP_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1268), .CK(clk), .RN(n5455),
.Q(FPADDSUB_DMP_SHT1_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_12_ ( .D(n1267), .CK(clk), .RN(n5440),
.Q(FPADDSUB_DMP_SHT2_EWSW[12]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_10_ ( .D(n1265), .CK(clk), .RN(n5455),
.Q(FPADDSUB_DMP_EXP_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1264), .CK(clk), .RN(n5454),
.Q(FPADDSUB_DMP_SHT1_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1263), .CK(clk), .RN(n5454),
.Q(FPADDSUB_DMP_SHT2_EWSW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_14_ ( .D(n1261), .CK(clk), .RN(n5464),
.Q(FPADDSUB_DMP_EXP_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1260), .CK(clk), .RN(n5460),
.Q(FPADDSUB_DMP_SHT1_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_14_ ( .D(n1259), .CK(clk), .RN(n5461),
.Q(FPADDSUB_DMP_SHT2_EWSW[14]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_11_ ( .D(n1257), .CK(clk), .RN(n5459),
.Q(FPADDSUB_DMP_EXP_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1256), .CK(clk), .RN(n5462),
.Q(FPADDSUB_DMP_SHT1_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1255), .CK(clk), .RN(n5464),
.Q(FPADDSUB_DMP_SHT2_EWSW[11]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_8_ ( .D(n1253), .CK(clk), .RN(n5444),
.Q(FPADDSUB_DMP_EXP_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1252), .CK(clk), .RN(n5459),
.Q(FPADDSUB_DMP_SHT1_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1251), .CK(clk), .RN(n5463),
.Q(FPADDSUB_DMP_SHT2_EWSW[8]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_16_ ( .D(n1249), .CK(clk), .RN(n5443),
.Q(FPADDSUB_DMP_EXP_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_16_ ( .D(n1248), .CK(clk), .RN(n5462),
.Q(FPADDSUB_DMP_SHT1_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_16_ ( .D(n1247), .CK(clk), .RN(n5443),
.Q(FPADDSUB_DMP_SHT2_EWSW[16]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_13_ ( .D(n1245), .CK(clk), .RN(n5464),
.Q(FPADDSUB_DMP_EXP_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1244), .CK(clk), .RN(n5443),
.Q(FPADDSUB_DMP_SHT1_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_13_ ( .D(n1243), .CK(clk), .RN(n5464),
.Q(FPADDSUB_DMP_SHT2_EWSW[13]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_6_ ( .D(n1241), .CK(clk), .RN(n5444),
.Q(FPADDSUB_DMP_EXP_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1240), .CK(clk), .RN(n5443),
.Q(FPADDSUB_DMP_SHT1_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_6_ ( .D(n1239), .CK(clk), .RN(n5462),
.Q(FPADDSUB_DMP_SHT2_EWSW[6]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_4_ ( .D(n1237), .CK(clk), .RN(n5443),
.Q(FPADDSUB_DMP_EXP_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1236), .CK(clk), .RN(n5461),
.Q(FPADDSUB_DMP_SHT1_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_4_ ( .D(n1235), .CK(clk), .RN(n5459),
.Q(FPADDSUB_DMP_SHT2_EWSW[4]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_17_ ( .D(n1233), .CK(clk), .RN(n5460),
.Q(FPADDSUB_DMP_EXP_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1232), .CK(clk), .RN(n5462),
.Q(FPADDSUB_DMP_SHT1_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1231), .CK(clk), .RN(n5460),
.Q(FPADDSUB_DMP_SHT2_EWSW[17]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_20_ ( .D(n1229), .CK(clk), .RN(n5463),
.Q(FPADDSUB_DMP_EXP_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1228), .CK(clk), .RN(n5461),
.Q(FPADDSUB_DMP_SHT1_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1227), .CK(clk), .RN(n5462),
.Q(FPADDSUB_DMP_SHT2_EWSW[20]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_19_ ( .D(n1225), .CK(clk), .RN(n5461),
.Q(FPADDSUB_DMP_EXP_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_19_ ( .D(n1224), .CK(clk), .RN(n5444),
.Q(FPADDSUB_DMP_SHT1_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_19_ ( .D(n1223), .CK(clk), .RN(n5460),
.Q(FPADDSUB_DMP_SHT2_EWSW[19]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_21_ ( .D(n1221), .CK(clk), .RN(n5459),
.Q(FPADDSUB_DMP_EXP_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1220), .CK(clk), .RN(n5459),
.Q(FPADDSUB_DMP_SHT1_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1219), .CK(clk), .RN(n5463),
.Q(FPADDSUB_DMP_SHT2_EWSW[21]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_18_ ( .D(n1217), .CK(clk), .RN(n5460),
.Q(FPADDSUB_DMP_EXP_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_18_ ( .D(n1216), .CK(clk), .RN(n5444),
.Q(FPADDSUB_DMP_SHT1_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_18_ ( .D(n1215), .CK(clk), .RN(n5444),
.Q(FPADDSUB_DMP_SHT2_EWSW[18]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_15_ ( .D(n1213), .CK(clk), .RN(n5464),
.Q(FPADDSUB_DMP_EXP_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1212), .CK(clk), .RN(n5462),
.Q(FPADDSUB_DMP_SHT1_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_15_ ( .D(n1211), .CK(clk), .RN(n5459),
.Q(FPADDSUB_DMP_SHT2_EWSW[15]) );
DFFRXLTS FPADDSUB_EXP_STAGE_DMP_Q_reg_22_ ( .D(n1209), .CK(clk), .RN(n5444),
.Q(FPADDSUB_DMP_EXP_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1208), .CK(clk), .RN(n5443),
.Q(FPADDSUB_DMP_SHT1_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1207), .CK(clk), .RN(n5462),
.Q(FPADDSUB_DMP_SHT2_EWSW[22]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[1]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[2]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[3]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[4]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[5]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[6]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[7]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[10]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[0]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[1]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[2]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[3]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[4]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[5]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[6]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[7]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[8]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[10])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[11])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[12])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[13])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N0), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[0])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[1])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[2])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[3])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[4])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[5])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[6])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[7])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[8])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[9])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[10])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[11])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N12), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[12])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N13), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[13])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_14_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N14), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[14])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_Data_S_o_reg_15_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N15), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[15])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N0), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[11]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(n5517), .CK(clk), .Q(FPMULT_Sgf_operation_Result[0]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(n5350), .CK(clk), .Q(FPMULT_Sgf_operation_Result[1]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_Result[2]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_Result[3]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_Result[4]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_Result[5]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[6]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[7]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[8]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[10])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(intadd_521_n1), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[11]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(n5518), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[0]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(n5349), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[1]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[2]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[3]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[4]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[5]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[6]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[7]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[10]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(intadd_520_n1), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N0), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_Q_left[0]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_Q_left[1]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_Q_left[2]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_Q_left[3]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_Q_left[4]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_Q_left[5]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[6]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[7]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[8]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[10]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(intadd_519_n1), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[11]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N0), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[0]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[2]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[3]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[4]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[5]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[6]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]) );
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N12), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N13), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[0])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_1_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N1), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[1])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_2_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[2])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_3_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[3])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_4_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[4])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_5_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[5])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_6_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[6])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_7_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[7])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_8_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[8])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_9_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[9])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_10_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[10])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_11_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[11])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_12_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[12])
);
DFFQX1TS FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_Data_S_o_reg_13_ (
.D(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13), .CK(clk), .Q(FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[13])
);
CMPR42X1TS mult_x_312_U22 ( .A(mult_x_312_n77), .B(mult_x_312_n67), .C(
mult_x_312_n72), .D(mult_x_312_n42), .ICI(mult_x_312_n39), .S(
mult_x_312_n37), .ICO(mult_x_312_n35), .CO(mult_x_312_n36) );
CMPR42X1TS mult_x_312_U19 ( .A(mult_x_312_n71), .B(mult_x_312_n38), .C(
mult_x_312_n35), .D(mult_x_312_n34), .ICI(mult_x_312_n32), .S(
mult_x_312_n30), .ICO(mult_x_312_n28), .CO(mult_x_312_n29) );
CMPR42X1TS mult_x_312_U16 ( .A(mult_x_312_n33), .B(mult_x_312_n31), .C(
mult_x_312_n27), .D(mult_x_312_n25), .ICI(mult_x_312_n28), .S(
mult_x_312_n23), .ICO(mult_x_312_n21), .CO(mult_x_312_n22) );
CMPR42X1TS mult_x_312_U14 ( .A(mult_x_312_n59), .B(mult_x_312_n26), .C(
mult_x_312_n24), .D(mult_x_312_n20), .ICI(mult_x_312_n21), .S(
mult_x_312_n18), .ICO(mult_x_312_n16), .CO(mult_x_312_n17) );
CMPR42X1TS mult_x_312_U13 ( .A(mult_x_312_n58), .B(mult_x_312_n48), .C(
mult_x_312_n53), .D(mult_x_312_n19), .ICI(mult_x_312_n16), .S(
mult_x_312_n15), .ICO(mult_x_312_n13), .CO(mult_x_312_n14) );
CMPR42X1TS mult_x_309_U23 ( .A(mult_x_309_n76), .B(mult_x_309_n66), .C(
mult_x_309_n71), .D(mult_x_309_n42), .ICI(mult_x_309_n39), .S(
mult_x_309_n37), .ICO(mult_x_309_n35), .CO(mult_x_309_n36) );
CMPR42X1TS mult_x_309_U20 ( .A(mult_x_309_n65), .B(mult_x_309_n38), .C(
mult_x_309_n35), .D(mult_x_309_n34), .ICI(mult_x_309_n32), .S(
mult_x_309_n30), .ICO(mult_x_309_n28), .CO(mult_x_309_n29) );
CMPR42X1TS mult_x_309_U17 ( .A(mult_x_309_n33), .B(mult_x_309_n27), .C(
mult_x_309_n31), .D(mult_x_309_n25), .ICI(mult_x_309_n28), .S(
mult_x_309_n23), .ICO(mult_x_309_n21), .CO(mult_x_309_n22) );
CMPR42X1TS mult_x_309_U15 ( .A(mult_x_309_n58), .B(mult_x_309_n26), .C(
mult_x_309_n20), .D(mult_x_309_n24), .ICI(mult_x_309_n21), .S(
mult_x_309_n18), .ICO(mult_x_309_n16), .CO(mult_x_309_n17) );
CMPR42X1TS mult_x_309_U14 ( .A(DP_OP_501J224_127_5235_n411), .B(
FPMULT_Op_MY[21]), .C(mult_x_309_n52), .D(mult_x_309_n19), .ICI(
mult_x_309_n16), .S(mult_x_309_n15), .ICO(mult_x_309_n13), .CO(
mult_x_309_n14) );
CMPR32X2TS DP_OP_26J224_129_1325_U9 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
n2195), .C(DP_OP_26J224_129_1325_n18), .CO(DP_OP_26J224_129_1325_n8),
.S(FPADDSUB_exp_rslt_NRM2_EW1[0]) );
CMPR32X2TS DP_OP_234J224_132_4955_U10 ( .A(FPMULT_S_Oper_A_exp[0]), .B(n5437), .C(DP_OP_234J224_132_4955_n22), .CO(DP_OP_234J224_132_4955_n9), .S(
FPMULT_Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_234J224_132_4955_U9 ( .A(DP_OP_234J224_132_4955_n21), .B(
FPMULT_S_Oper_A_exp[1]), .C(DP_OP_234J224_132_4955_n9), .CO(
DP_OP_234J224_132_4955_n8), .S(FPMULT_Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_234J224_132_4955_U8 ( .A(DP_OP_234J224_132_4955_n20), .B(
FPMULT_S_Oper_A_exp[2]), .C(DP_OP_234J224_132_4955_n8), .CO(
DP_OP_234J224_132_4955_n7), .S(FPMULT_Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_234J224_132_4955_U7 ( .A(DP_OP_234J224_132_4955_n19), .B(
FPMULT_S_Oper_A_exp[3]), .C(DP_OP_234J224_132_4955_n7), .CO(
DP_OP_234J224_132_4955_n6), .S(FPMULT_Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_234J224_132_4955_U6 ( .A(DP_OP_234J224_132_4955_n18), .B(
FPMULT_S_Oper_A_exp[4]), .C(DP_OP_234J224_132_4955_n6), .CO(
DP_OP_234J224_132_4955_n5), .S(FPMULT_Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_234J224_132_4955_U5 ( .A(DP_OP_234J224_132_4955_n17), .B(
FPMULT_S_Oper_A_exp[5]), .C(DP_OP_234J224_132_4955_n5), .CO(
DP_OP_234J224_132_4955_n4), .S(FPMULT_Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_234J224_132_4955_U4 ( .A(DP_OP_234J224_132_4955_n16), .B(
FPMULT_S_Oper_A_exp[6]), .C(DP_OP_234J224_132_4955_n4), .CO(
DP_OP_234J224_132_4955_n3), .S(FPMULT_Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_234J224_132_4955_U3 ( .A(DP_OP_234J224_132_4955_n15), .B(
FPMULT_S_Oper_A_exp[7]), .C(DP_OP_234J224_132_4955_n3), .CO(
DP_OP_234J224_132_4955_n2), .S(FPMULT_Exp_module_Data_S[7]) );
CMPR32X2TS intadd_519_U8 ( .A(mult_x_312_n37), .B(intadd_519_B_1_), .C(
intadd_519_n8), .CO(intadd_519_n7), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4) );
CMPR32X2TS intadd_519_U7 ( .A(mult_x_312_n36), .B(mult_x_312_n30), .C(
intadd_519_n7), .CO(intadd_519_n6), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5) );
CMPR32X2TS intadd_519_U6 ( .A(mult_x_312_n29), .B(mult_x_312_n23), .C(
intadd_519_n6), .CO(intadd_519_n5), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6) );
CMPR32X2TS intadd_519_U5 ( .A(mult_x_312_n22), .B(mult_x_312_n18), .C(
intadd_519_n5), .CO(intadd_519_n4), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7) );
CMPR32X2TS intadd_519_U4 ( .A(mult_x_312_n17), .B(mult_x_312_n15), .C(
intadd_519_n4), .CO(intadd_519_n3), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8) );
CMPR32X2TS intadd_519_U3 ( .A(mult_x_312_n14), .B(intadd_519_B_6_), .C(
intadd_519_n3), .CO(intadd_519_n2), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9) );
CMPR32X2TS intadd_520_U9 ( .A(intadd_520_A_0_), .B(intadd_520_B_0_), .C(
intadd_520_CI), .CO(intadd_520_n8), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3) );
CMPR32X2TS intadd_520_U7 ( .A(mult_x_311_n36), .B(mult_x_311_n30), .C(
intadd_520_n7), .CO(intadd_520_n6), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5) );
CMPR32X2TS intadd_520_U6 ( .A(mult_x_311_n29), .B(mult_x_311_n23), .C(
intadd_520_n6), .CO(intadd_520_n5), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6) );
CMPR32X2TS intadd_520_U5 ( .A(mult_x_311_n22), .B(mult_x_311_n18), .C(
intadd_520_n5), .CO(intadd_520_n4), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7) );
CMPR32X2TS intadd_520_U2 ( .A(intadd_520_A_7_), .B(intadd_520_B_7_), .C(
intadd_520_n2), .CO(intadd_520_n1), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10) );
CMPR32X2TS intadd_521_U9 ( .A(intadd_521_A_0_), .B(intadd_521_B_0_), .C(
intadd_521_CI), .CO(intadd_521_n8), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3) );
CMPR32X2TS intadd_521_U7 ( .A(mult_x_310_n36), .B(mult_x_310_n30), .C(
intadd_521_n7), .CO(intadd_521_n6), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N5) );
CMPR32X2TS intadd_521_U6 ( .A(mult_x_310_n29), .B(mult_x_310_n23), .C(
intadd_521_n6), .CO(intadd_521_n5), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N6) );
CMPR32X2TS intadd_521_U5 ( .A(mult_x_310_n22), .B(mult_x_310_n18), .C(
intadd_521_n5), .CO(intadd_521_n4), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N7) );
CMPR32X2TS intadd_521_U2 ( .A(intadd_521_A_7_), .B(intadd_521_B_7_), .C(
intadd_521_n2), .CO(intadd_521_n1), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10) );
CMPR32X2TS intadd_522_U8 ( .A(intadd_522_A_0_), .B(intadd_522_B_0_), .C(
intadd_522_CI), .CO(intadd_522_n7), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N3) );
CMPR32X2TS intadd_522_U7 ( .A(mult_x_309_n37), .B(intadd_522_B_1_), .C(
intadd_522_n7), .CO(intadd_522_n6), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4) );
CMPR32X2TS intadd_522_U6 ( .A(mult_x_309_n36), .B(mult_x_309_n30), .C(
intadd_522_n6), .CO(intadd_522_n5), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N5) );
CMPR32X2TS intadd_522_U5 ( .A(mult_x_309_n29), .B(mult_x_309_n23), .C(
intadd_522_n5), .CO(intadd_522_n4), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N6) );
CMPR32X2TS intadd_522_U4 ( .A(mult_x_309_n22), .B(mult_x_309_n18), .C(
intadd_522_n4), .CO(intadd_522_n3), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N7) );
CMPR32X2TS intadd_522_U3 ( .A(mult_x_309_n17), .B(mult_x_309_n15), .C(
intadd_522_n3), .CO(intadd_522_n2), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8) );
CMPR32X2TS intadd_524_U4 ( .A(FPSENCOS_d_ff2_Y[24]), .B(n5172), .C(
intadd_524_CI), .CO(intadd_524_n3), .S(intadd_524_SUM_0_) );
CMPR32X2TS intadd_524_U3 ( .A(FPSENCOS_d_ff2_Y[25]), .B(n5170), .C(
intadd_524_n3), .CO(intadd_524_n2), .S(intadd_524_SUM_1_) );
CMPR32X2TS intadd_525_U4 ( .A(FPSENCOS_d_ff2_X[24]), .B(n5172), .C(
intadd_525_CI), .CO(intadd_525_n3), .S(intadd_525_SUM_0_) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n1598), .CK(clk),
.RN(n2200), .Q(FPMULT_Add_result[22]), .QN(n5378) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n1603), .CK(clk),
.RN(n5505), .Q(FPMULT_Add_result[17]), .QN(n5365) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n1601), .CK(clk),
.RN(n5505), .Q(FPMULT_Add_result[19]), .QN(n5364) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_8_ ( .D(n1795), .CK(clk), .RN(n5456),
.Q(FPADDSUB_Data_array_SWR[7]), .QN(n5354) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_14_ ( .D(n1801), .CK(clk), .RN(n5465), .Q(FPADDSUB_Data_array_SWR[11]), .QN(n5352) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_30_ ( .D(n1911), .CK(clk), .RN(
n5466), .Q(FPADDSUB_intDX_EWSW[30]), .QN(n5345) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_29_ ( .D(n1912), .CK(clk), .RN(
n5467), .Q(FPADDSUB_intDX_EWSW[29]), .QN(n5344) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_23_ ( .D(n1810), .CK(clk), .RN(n5448), .Q(FPADDSUB_Data_array_SWR[19]), .QN(n5342) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_20_ ( .D(n1807), .CK(clk), .RN(n5450), .Q(FPADDSUB_Data_array_SWR[16]), .QN(n5336) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_26_ ( .D(n1915), .CK(clk), .RN(
n5466), .Q(FPADDSUB_intDX_EWSW[26]), .QN(n5334) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n1812), .CK(clk), .RN(n5439), .Q(FPADDSUB_Data_array_SWR[21]), .QN(n5333) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_24_ ( .D(n1819), .CK(clk), .RN(
n5439), .Q(FPADDSUB_intDY_EWSW[24]), .QN(n5332) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_25_ ( .D(n1916), .CK(clk), .RN(
n5439), .Q(FPADDSUB_intDX_EWSW[25]), .QN(n5331) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_3_ ( .D(n1938), .CK(clk), .RN(
n3389), .Q(FPADDSUB_intDX_EWSW[3]), .QN(n5329) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_8_ ( .D(n1933), .CK(clk), .RN(
n5463), .Q(FPADDSUB_intDX_EWSW[8]), .QN(n5327) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_11_ ( .D(n1930), .CK(clk), .RN(
n5462), .Q(FPADDSUB_intDX_EWSW[11]), .QN(n5326) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_1_ ( .D(n1940), .CK(clk), .RN(
n3389), .Q(FPADDSUB_intDX_EWSW[1]), .QN(n5325) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_2_ ( .D(n1939), .CK(clk), .RN(
n3390), .Q(FPADDSUB_intDX_EWSW[2]), .QN(n5324) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_0_ ( .D(n1941), .CK(clk), .RN(
n5459), .Q(FPADDSUB_intDX_EWSW[0]), .QN(n5323) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_13_ ( .D(n1928), .CK(clk), .RN(
n5438), .Q(FPADDSUB_intDX_EWSW[13]), .QN(n5322) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_15_ ( .D(n1926), .CK(clk), .RN(
n5455), .Q(FPADDSUB_intDX_EWSW[15]), .QN(n5318) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_14_ ( .D(n1927), .CK(clk), .RN(
n5464), .Q(FPADDSUB_intDX_EWSW[14]), .QN(n5317) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_22_ ( .D(n1919), .CK(clk), .RN(
n5456), .Q(FPADDSUB_intDX_EWSW[22]), .QN(n5316) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n1278), .CK(clk), .RN(
n5458), .Q(result_add_subt[5]), .QN(n5311) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n1299), .CK(clk), .RN(
n5453), .Q(result_add_subt[0]), .QN(n5310) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n1306), .CK(clk), .RN(
n5440), .Q(result_add_subt[7]), .QN(n5309) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n1369), .CK(clk), .RN(
n5448), .Q(result_add_subt[14]), .QN(n5308) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n1378), .CK(clk), .RN(
n5448), .Q(result_add_subt[16]), .QN(n5307) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1384), .CK(clk), .RN(
n5449), .Q(result_add_subt[6]), .QN(n5306) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n1390), .CK(clk), .RN(
n5450), .Q(result_add_subt[17]), .QN(n5305) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n1393), .CK(clk), .RN(
n5447), .Q(result_add_subt[20]), .QN(n5304) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n1396), .CK(clk), .RN(
n5452), .Q(result_add_subt[19]), .QN(n5303) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n1402), .CK(clk), .RN(
n5447), .Q(result_add_subt[18]), .QN(n5302) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n1405), .CK(clk), .RN(
n5448), .Q(result_add_subt[15]), .QN(n5301) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1408), .CK(clk), .RN(
n5451), .Q(result_add_subt[22]), .QN(n5300) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n1285), .CK(clk), .RN(
n5454), .Q(result_add_subt[9]), .QN(n5299) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n1363), .CK(clk), .RN(
n5447), .Q(result_add_subt[12]), .QN(n5298) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n1366), .CK(clk), .RN(
n2295), .Q(result_add_subt[10]), .QN(n5297) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n1372), .CK(clk), .RN(
n5441), .Q(result_add_subt[11]), .QN(n5296) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1375), .CK(clk), .RN(
n5449), .Q(result_add_subt[8]), .QN(n5295) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n1381), .CK(clk), .RN(
n2295), .Q(result_add_subt[13]), .QN(n5294) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_30_ ( .D(n1813), .CK(clk), .RN(
n5456), .Q(FPADDSUB_intDY_EWSW[30]), .QN(n5293) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_17_ ( .D(n1826), .CK(clk), .RN(
n5441), .Q(FPADDSUB_intDY_EWSW[17]), .QN(n5283) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_20_ ( .D(n1823), .CK(clk), .RN(
n5450), .Q(FPADDSUB_intDY_EWSW[20]), .QN(n5278) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_11_ ( .D(n1832), .CK(clk), .RN(
n5461), .Q(FPADDSUB_intDY_EWSW[11]), .QN(n5274) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_18_ ( .D(n1331), .CK(clk), .RN(
n5457), .Q(FPADDSUB_Raw_mant_NRM_SWR[18]), .QN(n5272) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_13_ ( .D(n1830), .CK(clk), .RN(
n5467), .Q(FPADDSUB_intDY_EWSW[13]), .QN(n5271) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_16_ ( .D(n1333), .CK(clk), .RN(
n5453), .Q(FPADDSUB_Raw_mant_NRM_SWR[16]), .QN(n5266) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_3_ ( .D(n1840), .CK(clk), .RN(
n5450), .Q(FPADDSUB_intDY_EWSW[3]), .QN(n5265) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_14_ ( .D(n1829), .CK(clk), .RN(
n5460), .Q(FPADDSUB_intDY_EWSW[14]), .QN(n5257) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_8_ ( .D(n1595), .CK(clk), .RN(
n5508), .Q(FPMULT_exp_oper_result[8]), .QN(n5230) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_24_ ( .D(n1811), .CK(clk), .RN(n5445), .Q(FPADDSUB_Data_array_SWR[20]), .QN(n5229) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_17_ ( .D(n1804), .CK(clk), .RN(n5452), .Q(FPADDSUB_Data_array_SWR[13]), .QN(n5226) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_18_ ( .D(n1923), .CK(clk), .RN(
n5455), .Q(FPADDSUB_intDX_EWSW[18]), .QN(n5224) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_19_ ( .D(n1922), .CK(clk), .RN(
n5441), .Q(FPADDSUB_intDX_EWSW[19]), .QN(n5223) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_21_ ( .D(n1920), .CK(clk), .RN(
n5448), .Q(FPADDSUB_intDX_EWSW[21]), .QN(n5221) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_12_ ( .D(n1929), .CK(clk), .RN(
n3390), .Q(FPADDSUB_intDX_EWSW[12]), .QN(n5220) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_9_ ( .D(n1932), .CK(clk), .RN(
n2295), .Q(FPADDSUB_intDX_EWSW[9]), .QN(n5219) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_17_ ( .D(n1924), .CK(clk), .RN(
n5452), .Q(FPADDSUB_intDX_EWSW[17]), .QN(n5217) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_20_ ( .D(n1921), .CK(clk), .RN(
n5449), .Q(FPADDSUB_intDX_EWSW[20]), .QN(n5216) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_27_ ( .D(n1914), .CK(clk), .RN(
n5467), .Q(FPADDSUB_intDX_EWSW[27]), .QN(n5215) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1469), .CK(clk), .RN(
n5438), .Q(result_add_subt[27]), .QN(n5212) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1470), .CK(clk), .RN(
n5468), .Q(result_add_subt[26]), .QN(n5211) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1471), .CK(clk), .RN(
n5442), .Q(result_add_subt[25]), .QN(n5210) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1472), .CK(clk), .RN(
n5442), .Q(result_add_subt[24]), .QN(n5209) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1473), .CK(clk), .RN(
n5468), .Q(result_add_subt[23]), .QN(n5208) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_15_ ( .D(n1334), .CK(clk), .RN(
n5457), .Q(FPADDSUB_Raw_mant_NRM_SWR[15]), .QN(n5207) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n1292), .CK(clk), .RN(
n5458), .Q(result_add_subt[1]), .QN(n5203) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1313), .CK(clk), .RN(
n5454), .Q(result_add_subt[2]), .QN(n5202) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n1329), .CK(clk), .RN(
n5458), .Q(result_add_subt[3]), .QN(n5201) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1387), .CK(clk), .RN(
n5441), .Q(result_add_subt[4]), .QN(n5200) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1399), .CK(clk), .RN(
n5451), .Q(result_add_subt[21]), .QN(n5199) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_29_ ( .D(n1814), .CK(clk), .RN(
n5446), .Q(FPADDSUB_intDY_EWSW[29]), .QN(n5196) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_15_ ( .D(n1828), .CK(clk), .RN(
n5453), .Q(FPADDSUB_intDY_EWSW[15]), .QN(n5190) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_22_ ( .D(n1317), .CK(clk), .RN(
n5456), .Q(FPADDSUB_Raw_mant_NRM_SWR[22]), .QN(n5187) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1336), .CK(clk), .RN(
n5455), .Q(FPADDSUB_Raw_mant_NRM_SWR[13]), .QN(n5186) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1337), .CK(clk), .RN(
n5454), .Q(FPADDSUB_Raw_mant_NRM_SWR[12]), .QN(n5167) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_23_ ( .D(n1316), .CK(clk), .RN(
n5440), .Q(FPADDSUB_Raw_mant_NRM_SWR[23]), .QN(n5165) );
DFFRXLTS NaN_dff_Q_reg_0_ ( .D(NaN_reg), .CK(clk), .RN(n5486), .Q(NaN_flag)
);
CMPR32X2TS intadd_522_U2 ( .A(mult_x_309_n14), .B(intadd_522_B_6_), .C(
intadd_522_n2), .CO(intadd_522_n1), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9) );
CMPR32X2TS intadd_521_U8 ( .A(mult_x_310_n37), .B(intadd_521_B_1_), .C(
intadd_521_n8), .CO(intadd_521_n7), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N4) );
CMPR32X2TS intadd_521_U4 ( .A(mult_x_310_n17), .B(mult_x_310_n15), .C(
intadd_521_n4), .CO(intadd_521_n3), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N8) );
CMPR32X2TS intadd_521_U3 ( .A(mult_x_310_n14), .B(intadd_521_B_6_), .C(
intadd_521_n3), .CO(intadd_521_n2), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N9) );
CMPR32X2TS intadd_520_U8 ( .A(mult_x_311_n37), .B(intadd_520_B_1_), .C(
intadd_520_n8), .CO(intadd_520_n7), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N4) );
CMPR32X2TS intadd_520_U4 ( .A(mult_x_311_n17), .B(mult_x_311_n15), .C(
intadd_520_n4), .CO(intadd_520_n3), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N8) );
CMPR32X2TS intadd_520_U3 ( .A(mult_x_311_n14), .B(intadd_520_B_6_), .C(
intadd_520_n3), .CO(intadd_520_n2), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N9) );
CMPR32X2TS intadd_519_U9 ( .A(intadd_519_A_0_), .B(intadd_519_B_0_), .C(
intadd_519_CI), .CO(intadd_519_n8), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N3) );
CMPR42X1TS DP_OP_502J224_128_4510_U25 ( .A(DP_OP_502J224_128_4510_n70), .B(
DP_OP_502J224_128_4510_n76), .C(DP_OP_502J224_128_4510_n57), .D(
DP_OP_502J224_128_4510_n63), .ICI(DP_OP_502J224_128_4510_n41), .S(
DP_OP_502J224_128_4510_n38), .ICO(DP_OP_502J224_128_4510_n36), .CO(
DP_OP_502J224_128_4510_n37) );
CMPR42X1TS DP_OP_502J224_128_4510_U24 ( .A(DP_OP_502J224_128_4510_n75), .B(
DP_OP_502J224_128_4510_n69), .C(DP_OP_502J224_128_4510_n62), .D(
DP_OP_502J224_128_4510_n56), .ICI(DP_OP_502J224_128_4510_n36), .S(
DP_OP_502J224_128_4510_n35), .ICO(DP_OP_502J224_128_4510_n33), .CO(
DP_OP_502J224_128_4510_n34) );
CMPR42X1TS DP_OP_502J224_128_4510_U22 ( .A(DP_OP_502J224_128_4510_n32), .B(
DP_OP_502J224_128_4510_n68), .C(DP_OP_502J224_128_4510_n61), .D(
DP_OP_502J224_128_4510_n55), .ICI(DP_OP_502J224_128_4510_n33), .S(
DP_OP_502J224_128_4510_n31), .ICO(DP_OP_502J224_128_4510_n29), .CO(
DP_OP_502J224_128_4510_n30) );
CMPR42X1TS DP_OP_502J224_128_4510_U20 ( .A(DP_OP_502J224_128_4510_n32), .B(
DP_OP_502J224_128_4510_n67), .C(DP_OP_502J224_128_4510_n60), .D(
DP_OP_502J224_128_4510_n54), .ICI(DP_OP_502J224_128_4510_n29), .S(
DP_OP_502J224_128_4510_n26), .ICO(DP_OP_502J224_128_4510_n24), .CO(
DP_OP_502J224_128_4510_n25) );
CMPR42X1TS DP_OP_502J224_128_4510_U19 ( .A(n2371), .B(
DP_OP_502J224_128_4510_n66), .C(DP_OP_502J224_128_4510_n59), .D(
DP_OP_502J224_128_4510_n53), .ICI(DP_OP_502J224_128_4510_n24), .S(
DP_OP_502J224_128_4510_n23), .ICO(DP_OP_502J224_128_4510_n21), .CO(
DP_OP_502J224_128_4510_n22) );
CMPR42X1TS DP_OP_501J224_127_5235_U113 ( .A(DP_OP_501J224_127_5235_n229),
.B(DP_OP_501J224_127_5235_n215), .C(DP_OP_501J224_127_5235_n171), .D(
DP_OP_501J224_127_5235_n170), .ICI(DP_OP_501J224_127_5235_n236), .S(
DP_OP_501J224_127_5235_n168), .ICO(DP_OP_501J224_127_5235_n166), .CO(
DP_OP_501J224_127_5235_n167) );
CMPR42X1TS DP_OP_501J224_127_5235_U108 ( .A(DP_OP_501J224_127_5235_n220),
.B(DP_OP_501J224_127_5235_n206), .C(DP_OP_501J224_127_5235_n158), .D(
DP_OP_501J224_127_5235_n227), .ICI(DP_OP_501J224_127_5235_n162), .S(
DP_OP_501J224_127_5235_n156), .ICO(DP_OP_501J224_127_5235_n154), .CO(
DP_OP_501J224_127_5235_n155) );
CMPR42X1TS DP_OP_501J224_127_5235_U104 ( .A(DP_OP_501J224_127_5235_n150),
.B(DP_OP_501J224_127_5235_n154), .C(DP_OP_501J224_127_5235_n233), .D(
DP_OP_501J224_127_5235_n184), .ICI(DP_OP_501J224_127_5235_n155), .S(
DP_OP_501J224_127_5235_n146), .ICO(DP_OP_501J224_127_5235_n144), .CO(
DP_OP_501J224_127_5235_n145) );
CMPR42X1TS DP_OP_501J224_127_5235_U103 ( .A(DP_OP_501J224_127_5235_n191),
.B(DP_OP_501J224_127_5235_n226), .C(DP_OP_501J224_127_5235_n148), .D(
DP_OP_501J224_127_5235_n151), .ICI(DP_OP_501J224_127_5235_n146), .S(
DP_OP_501J224_127_5235_n143), .ICO(DP_OP_501J224_127_5235_n141), .CO(
DP_OP_501J224_127_5235_n142) );
CMPR42X1TS DP_OP_501J224_127_5235_U100 ( .A(DP_OP_501J224_127_5235_n183),
.B(DP_OP_501J224_127_5235_n218), .C(DP_OP_501J224_127_5235_n190), .D(
DP_OP_501J224_127_5235_n140), .ICI(DP_OP_501J224_127_5235_n141), .S(
DP_OP_501J224_127_5235_n136), .ICO(DP_OP_501J224_127_5235_n134), .CO(
DP_OP_501J224_127_5235_n135) );
CMPR42X1TS DP_OP_501J224_127_5235_U99 ( .A(DP_OP_501J224_127_5235_n147), .B(
DP_OP_501J224_127_5235_n144), .C(DP_OP_501J224_127_5235_n138), .D(
DP_OP_501J224_127_5235_n145), .ICI(DP_OP_501J224_127_5235_n136), .S(
DP_OP_501J224_127_5235_n133), .ICO(DP_OP_501J224_127_5235_n131), .CO(
DP_OP_501J224_127_5235_n132) );
CMPR42X1TS DP_OP_501J224_127_5235_U97 ( .A(DP_OP_501J224_127_5235_n182), .B(
DP_OP_501J224_127_5235_n139), .C(DP_OP_501J224_127_5235_n189), .D(
DP_OP_501J224_127_5235_n210), .ICI(DP_OP_501J224_127_5235_n134), .S(
DP_OP_501J224_127_5235_n128), .ICO(DP_OP_501J224_127_5235_n126), .CO(
DP_OP_501J224_127_5235_n127) );
CMPR42X1TS DP_OP_501J224_127_5235_U96 ( .A(DP_OP_501J224_127_5235_n137), .B(
DP_OP_501J224_127_5235_n130), .C(DP_OP_501J224_127_5235_n131), .D(
DP_OP_501J224_127_5235_n135), .ICI(DP_OP_501J224_127_5235_n128), .S(
DP_OP_501J224_127_5235_n125), .ICO(DP_OP_501J224_127_5235_n123), .CO(
DP_OP_501J224_127_5235_n124) );
CMPR42X1TS DP_OP_501J224_127_5235_U95 ( .A(DP_OP_501J224_127_5235_n195), .B(
DP_OP_501J224_127_5235_n209), .C(DP_OP_501J224_127_5235_n181), .D(
DP_OP_501J224_127_5235_n188), .ICI(DP_OP_501J224_127_5235_n202), .S(
DP_OP_501J224_127_5235_n122), .ICO(DP_OP_501J224_127_5235_n120), .CO(
DP_OP_501J224_127_5235_n121) );
CMPR42X1TS DP_OP_501J224_127_5235_U94 ( .A(DP_OP_501J224_127_5235_n129), .B(
DP_OP_501J224_127_5235_n126), .C(DP_OP_501J224_127_5235_n127), .D(
DP_OP_501J224_127_5235_n122), .ICI(DP_OP_501J224_127_5235_n123), .S(
DP_OP_501J224_127_5235_n119), .ICO(DP_OP_501J224_127_5235_n117), .CO(
DP_OP_501J224_127_5235_n118) );
CMPR42X1TS DP_OP_501J224_127_5235_U92 ( .A(DP_OP_501J224_127_5235_n194), .B(
DP_OP_501J224_127_5235_n120), .C(DP_OP_501J224_127_5235_n116), .D(
DP_OP_501J224_127_5235_n121), .ICI(DP_OP_501J224_127_5235_n117), .S(
DP_OP_501J224_127_5235_n114), .ICO(DP_OP_501J224_127_5235_n112), .CO(
DP_OP_501J224_127_5235_n113) );
CMPR42X1TS DP_OP_501J224_127_5235_U91 ( .A(DP_OP_501J224_127_5235_n193), .B(
DP_OP_501J224_127_5235_n179), .C(DP_OP_501J224_127_5235_n186), .D(
DP_OP_501J224_127_5235_n115), .ICI(DP_OP_501J224_127_5235_n112), .S(
DP_OP_501J224_127_5235_n111), .ICO(DP_OP_501J224_127_5235_n109), .CO(
DP_OP_501J224_127_5235_n110) );
CMPR42X1TS DP_OP_501J224_127_5235_U22 ( .A(DP_OP_501J224_127_5235_n72), .B(
DP_OP_501J224_127_5235_n62), .C(DP_OP_501J224_127_5235_n40), .D(
DP_OP_501J224_127_5235_n39), .ICI(DP_OP_501J224_127_5235_n77), .S(
DP_OP_501J224_127_5235_n37), .ICO(DP_OP_501J224_127_5235_n35), .CO(
DP_OP_501J224_127_5235_n36) );
CMPR42X1TS DP_OP_501J224_127_5235_U19 ( .A(DP_OP_501J224_127_5235_n34), .B(
DP_OP_501J224_127_5235_n71), .C(DP_OP_501J224_127_5235_n56), .D(
DP_OP_501J224_127_5235_n32), .ICI(DP_OP_501J224_127_5235_n35), .S(
DP_OP_501J224_127_5235_n30), .ICO(DP_OP_501J224_127_5235_n28), .CO(
DP_OP_501J224_127_5235_n29) );
CMPR42X1TS DP_OP_501J224_127_5235_U16 ( .A(DP_OP_501J224_127_5235_n55), .B(
DP_OP_501J224_127_5235_n31), .C(DP_OP_501J224_127_5235_n27), .D(
DP_OP_501J224_127_5235_n28), .ICI(DP_OP_501J224_127_5235_n25), .S(
DP_OP_501J224_127_5235_n23), .ICO(DP_OP_501J224_127_5235_n21), .CO(
DP_OP_501J224_127_5235_n22) );
CMPR42X1TS DP_OP_501J224_127_5235_U14 ( .A(DP_OP_501J224_127_5235_n59), .B(
DP_OP_501J224_127_5235_n54), .C(DP_OP_501J224_127_5235_n20), .D(
DP_OP_501J224_127_5235_n24), .ICI(DP_OP_501J224_127_5235_n21), .S(
DP_OP_501J224_127_5235_n18), .ICO(DP_OP_501J224_127_5235_n16), .CO(
DP_OP_501J224_127_5235_n17) );
CMPR42X1TS DP_OP_501J224_127_5235_U13 ( .A(DP_OP_501J224_127_5235_n58), .B(
DP_OP_501J224_127_5235_n48), .C(DP_OP_501J224_127_5235_n53), .D(
DP_OP_501J224_127_5235_n19), .ICI(DP_OP_501J224_127_5235_n16), .S(
DP_OP_501J224_127_5235_n15), .ICO(DP_OP_501J224_127_5235_n13), .CO(
DP_OP_501J224_127_5235_n14) );
CMPR42X1TS DP_OP_500J224_126_4510_U25 ( .A(DP_OP_500J224_126_4510_n70), .B(
DP_OP_500J224_126_4510_n56), .C(DP_OP_500J224_126_4510_n76), .D(
DP_OP_500J224_126_4510_n41), .ICI(DP_OP_500J224_126_4510_n63), .S(
DP_OP_500J224_126_4510_n38), .ICO(DP_OP_500J224_126_4510_n36), .CO(
DP_OP_500J224_126_4510_n37) );
CMPR42X1TS DP_OP_500J224_126_4510_U24 ( .A(DP_OP_500J224_126_4510_n75), .B(
DP_OP_500J224_126_4510_n69), .C(DP_OP_500J224_126_4510_n55), .D(
DP_OP_500J224_126_4510_n62), .ICI(DP_OP_500J224_126_4510_n36), .S(
DP_OP_500J224_126_4510_n35), .ICO(DP_OP_500J224_126_4510_n33), .CO(
DP_OP_500J224_126_4510_n34) );
CMPR42X1TS DP_OP_500J224_126_4510_U22 ( .A(DP_OP_500J224_126_4510_n32), .B(
DP_OP_500J224_126_4510_n68), .C(DP_OP_500J224_126_4510_n54), .D(
DP_OP_500J224_126_4510_n61), .ICI(DP_OP_500J224_126_4510_n33), .S(
DP_OP_500J224_126_4510_n31), .ICO(DP_OP_500J224_126_4510_n29), .CO(
DP_OP_500J224_126_4510_n30) );
CMPR42X1TS DP_OP_500J224_126_4510_U20 ( .A(DP_OP_500J224_126_4510_n32), .B(
DP_OP_500J224_126_4510_n67), .C(DP_OP_500J224_126_4510_n53), .D(
DP_OP_500J224_126_4510_n60), .ICI(DP_OP_500J224_126_4510_n29), .S(
DP_OP_500J224_126_4510_n26), .ICO(DP_OP_500J224_126_4510_n24), .CO(
DP_OP_500J224_126_4510_n25) );
CMPR42X1TS DP_OP_500J224_126_4510_U19 ( .A(DP_OP_500J224_126_4510_n27), .B(
DP_OP_500J224_126_4510_n66), .C(DP_OP_500J224_126_4510_n52), .D(
DP_OP_500J224_126_4510_n59), .ICI(DP_OP_500J224_126_4510_n24), .S(
DP_OP_500J224_126_4510_n23), .ICO(DP_OP_500J224_126_4510_n21), .CO(
DP_OP_500J224_126_4510_n22) );
CMPR42X1TS mult_x_313_U25 ( .A(mult_x_313_n56), .B(mult_x_313_n76), .C(
mult_x_313_n69), .D(mult_x_313_n62), .ICI(mult_x_313_n42), .S(
mult_x_313_n39), .ICO(mult_x_313_n37), .CO(mult_x_313_n38) );
CMPR42X1TS mult_x_313_U24 ( .A(mult_x_313_n75), .B(mult_x_313_n55), .C(
mult_x_313_n61), .D(mult_x_313_n68), .ICI(mult_x_313_n37), .S(
mult_x_313_n36), .ICO(mult_x_313_n34), .CO(mult_x_313_n35) );
CMPR42X1TS mult_x_313_U22 ( .A(mult_x_313_n67), .B(mult_x_313_n60), .C(n2370), .D(mult_x_313_n33), .ICI(mult_x_313_n34), .S(mult_x_313_n31), .ICO(
mult_x_313_n29), .CO(mult_x_313_n30) );
CMPR42X1TS mult_x_313_U20 ( .A(mult_x_313_n66), .B(mult_x_313_n32), .C(
mult_x_313_n59), .D(mult_x_313_n28), .ICI(mult_x_313_n29), .S(
mult_x_313_n26), .ICO(mult_x_313_n24), .CO(mult_x_313_n25) );
CMPR42X1TS mult_x_313_U19 ( .A(mult_x_313_n27), .B(mult_x_313_n58), .C(
mult_x_313_n54), .D(mult_x_313_n65), .ICI(mult_x_313_n24), .S(
mult_x_313_n23), .ICO(mult_x_313_n21), .CO(mult_x_313_n22) );
DFFSX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_1_ ( .D(n2410), .CK(clk), .SN(n5457),
.Q(n5525), .QN(FPADDSUB_DMP_SFG[1]) );
DFFSX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n2234), .CK(clk),
.SN(n2200), .Q(n5520), .QN(FPMULT_Op_MY[15]) );
DFFSX2TS R_12_IP ( .D(n2409), .CK(clk), .SN(n5488), .QN(n5521) );
DFFRX2TS FPMULT_Sel_A_Q_reg_0_ ( .D(n1689), .CK(clk), .RN(n5503), .Q(
FPMULT_FSM_selector_A), .QN(n5360) );
DFFRX2TS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n1352), .CK(clk), .RN(n5451),
.Q(FPADDSUB_OP_FLAG_SFG), .QN(n5286) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_3_ ( .D(n1323), .CK(clk), .RN(n5458),
.Q(FPADDSUB_DMP_SFG[3]), .QN(n5236) );
DFFRX2TS FPMULT_Sel_B_Q_reg_1_ ( .D(n1622), .CK(clk), .RN(n5508), .Q(
FPMULT_FSM_selector_B[1]), .QN(n5279) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_20_ ( .D(n1226), .CK(clk), .RN(n5443),
.Q(FPADDSUB_DMP_SFG[20]), .QN(n5288) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_12_ ( .D(n1266), .CK(clk), .RN(n5440),
.Q(FPADDSUB_DMP_SFG[12]), .QN(n5246) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_0_ ( .D(n2141), .CK(clk), .RN(n5478),
.Q(FPSENCOS_cont_iter_out[0]), .QN(n5191) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_2_ ( .D(n2139), .CK(clk), .RN(n5485),
.Q(FPSENCOS_cont_iter_out[2]), .QN(n5170) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1345), .CK(clk), .RN(
n5450), .Q(FPADDSUB_Raw_mant_NRM_SWR[4]), .QN(n5347) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_1_ ( .D(n2140), .CK(clk), .RN(n5489),
.Q(FPSENCOS_cont_iter_out[1]), .QN(n5172) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n1637), .CK(clk),
.RN(n5513), .Q(FPMULT_Op_MY[11]), .QN(n5158) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n1636), .CK(clk),
.RN(n5511), .Q(FPMULT_Op_MY[10]), .QN(n5173) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n1635), .CK(clk),
.RN(n2200), .Q(FPMULT_Op_MY[9]), .QN(n5168) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n1631), .CK(clk),
.RN(n5510), .Q(FPMULT_Op_MY[5]), .QN(n5169) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n1630), .CK(clk),
.RN(n5509), .Q(FPMULT_Op_MY[4]), .QN(n5192) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n1629), .CK(clk),
.RN(n5503), .Q(FPMULT_Op_MY[3]), .QN(n5159) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n1642), .CK(clk),
.RN(n5513), .Q(FPMULT_Op_MY[16]), .QN(n5254) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n1643), .CK(clk),
.RN(n2200), .Q(FPMULT_Op_MY[17]), .QN(n5164) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n1647), .CK(clk),
.RN(n5507), .Q(FPMULT_Op_MY[21]), .QN(n5253) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n1644), .CK(clk),
.RN(n5507), .Q(FPMULT_Op_MY[18]), .QN(n5248) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n1645), .CK(clk),
.RN(n5507), .Q(FPMULT_Op_MY[19]), .QN(n5156) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n1648), .CK(clk),
.RN(n5507), .Q(FPMULT_Op_MY[22]), .QN(n5251) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n1658), .CK(clk),
.RN(n5504), .Q(FPMULT_Op_MX[0]), .QN(n5269) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n1665), .CK(clk),
.RN(n5512), .Q(FPMULT_Op_MX[7]), .QN(n5262) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n1659), .CK(clk),
.RN(n5504), .Q(FPMULT_Op_MX[1]), .QN(n5261) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n1680), .CK(clk),
.RN(n5503), .Q(FPMULT_Op_MX[22]), .QN(n5188) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n1676), .CK(clk),
.RN(n5512), .Q(FPMULT_Op_MX[18]), .QN(n5162) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n1673), .CK(clk),
.RN(n5504), .Q(FPMULT_Op_MX[15]), .QN(n5157) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n1675), .CK(clk),
.RN(n5512), .Q(FPMULT_Op_MX[17]), .QN(n5255) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n1671), .CK(clk),
.RN(n5504), .Q(FPMULT_Op_MX[13]), .QN(n5160) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n1664), .CK(clk),
.RN(n2200), .Q(FPMULT_Op_MX[6]), .QN(n5270) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_0_ ( .D(n2137), .CK(clk), .RN(n5484),
.Q(FPSENCOS_cont_var_out[0]), .QN(n5198) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1198), .CK(clk), .RN(
n5464), .Q(FPADDSUB_DmP_mant_SFG_SWR[7]), .QN(n5182) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n2076), .CK(clk), .RN(
n3389), .Q(FPADDSUB_shift_value_SHT2_EWR[3]), .QN(n5161) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_1_ ( .D(n1691), .CK(clk), .RN(n5491),
.Q(FPMULT_FS_Module_state_reg[1]), .QN(n5195) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_0_ ( .D(n1692), .CK(clk), .RN(n5472),
.Q(FPMULT_FS_Module_state_reg[0]), .QN(n5291) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_2_ ( .D(n1690), .CK(clk), .RN(n5490),
.Q(FPMULT_FS_Module_state_reg[2]), .QN(n5175) );
DFFRX2TS FPMULT_FS_Module_state_reg_reg_3_ ( .D(n1693), .CK(clk), .RN(n5476),
.Q(FPMULT_FS_Module_state_reg[3]), .QN(n5263) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n2077), .CK(clk), .RN(
n3390), .Q(FPADDSUB_shift_value_SHT2_EWR[2]), .QN(n5177) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1335), .CK(clk), .RN(
n5458), .Q(FPADDSUB_Raw_mant_NRM_SWR[14]), .QN(n5189) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_23_ ( .D(n1820), .CK(clk), .RN(
n5467), .Q(FPADDSUB_intDY_EWSW[23]), .QN(n5194) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_26_ ( .D(n1817), .CK(clk), .RN(
n5465), .Q(FPADDSUB_intDY_EWSW[26]), .QN(n5280) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_25_ ( .D(n1818), .CK(clk), .RN(
n5446), .Q(FPADDSUB_intDY_EWSW[25]), .QN(n5273) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_21_ ( .D(n1822), .CK(clk), .RN(
n5453), .Q(FPADDSUB_intDY_EWSW[21]), .QN(n5281) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_12_ ( .D(n1831), .CK(clk), .RN(
n5463), .Q(FPADDSUB_intDY_EWSW[12]), .QN(n5268) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_8_ ( .D(n1835), .CK(clk), .RN(
n5442), .Q(FPADDSUB_intDY_EWSW[8]), .QN(n5285) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_1_ ( .D(n1842), .CK(clk), .RN(
n5445), .Q(FPADDSUB_intDY_EWSW[1]), .QN(n5260) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_16_ ( .D(n1925), .CK(clk), .RN(
n5442), .Q(FPADDSUB_intDX_EWSW[16]), .QN(n5321) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_10_ ( .D(n1931), .CK(clk), .RN(
n5462), .Q(FPADDSUB_intDX_EWSW[10]), .QN(n5320) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_7_ ( .D(n1934), .CK(clk), .RN(
n5447), .Q(FPADDSUB_intDX_EWSW[7]), .QN(n5343) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_5_ ( .D(n1936), .CK(clk), .RN(
n5444), .Q(FPADDSUB_intDX_EWSW[5]), .QN(n5218) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_28_ ( .D(n1913), .CK(clk), .RN(
n5466), .Q(FPADDSUB_intDX_EWSW[28]), .QN(n5346) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_23_ ( .D(n1918), .CK(clk), .RN(
n5439), .Q(FPADDSUB_intDX_EWSW[23]), .QN(n5205) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_6_ ( .D(n1935), .CK(clk), .RN(
n5442), .Q(FPADDSUB_intDX_EWSW[6]), .QN(n5222) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_4_ ( .D(n1937), .CK(clk), .RN(
n5446), .Q(FPADDSUB_intDX_EWSW[4]), .QN(n5328) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_22_ ( .D(n1821), .CK(clk), .RN(
n5440), .Q(FPADDSUB_intDY_EWSW[22]), .QN(n5267) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_19_ ( .D(n1824), .CK(clk), .RN(
n2295), .Q(FPADDSUB_intDY_EWSW[19]), .QN(n5197) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_18_ ( .D(n1825), .CK(clk), .RN(
n5457), .Q(FPADDSUB_intDY_EWSW[18]), .QN(n5284) );
DFFRX1TS FPADDSUB_Ready_reg_Q_reg_0_ ( .D(n2280), .CK(clk), .RN(n5446), .Q(
ready_add_subt), .QN(n5206) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1348), .CK(clk), .RN(
n5451), .Q(FPADDSUB_Raw_mant_NRM_SWR[1]), .QN(n5276) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_5_ ( .D(n1272), .CK(clk), .RN(n5453),
.Q(FPADDSUB_DMP_SFG[5]), .QN(n5240) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_11_ ( .D(n1254), .CK(clk), .RN(n5459),
.Q(FPADDSUB_DMP_SFG[11]), .QN(n5185) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_7_ ( .D(n1300), .CK(clk), .RN(n5454),
.Q(FPADDSUB_DMP_SFG[7]), .QN(n5242) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_10_ ( .D(n1262), .CK(clk), .RN(n5460),
.Q(FPADDSUB_DMP_SFG[10]), .QN(n5183) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n2079), .CK(clk), .RN(
n5460), .Q(FPADDSUB_bit_shift_SHT2), .QN(n5312) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1346), .CK(clk), .RN(
n5448), .Q(FPADDSUB_Raw_mant_NRM_SWR[3]), .QN(n5282) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n5486), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .QN(n5252) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n5471), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .QN(n5314) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_19_ ( .D(n1222), .CK(clk), .RN(n5464),
.Q(FPADDSUB_DMP_SFG[19]), .QN(n5287) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_18_ ( .D(n1214), .CK(clk), .RN(n5443),
.Q(FPADDSUB_DMP_SFG[18]), .QN(n5277) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_17_ ( .D(n1230), .CK(clk), .RN(n5463),
.Q(FPADDSUB_DMP_SFG[17]), .QN(n5292) );
DFFRX1TS FPMULT_Sel_B_Q_reg_0_ ( .D(n1623), .CK(clk), .RN(n5510), .Q(
FPMULT_FSM_selector_B[0]), .QN(n5275) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_1_ ( .D(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk), .RN(n5465),
.Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .QN(n5359) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n1617), .CK(clk), .RN(
n5506), .Q(FPMULT_Add_result[3]), .QN(n5368) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n1619), .CK(clk), .RN(
n5506), .Q(FPMULT_Add_result[1]), .QN(n5367) );
DFFRX1TS FPADDSUB_inst_ShiftRegister_Q_reg_2_ ( .D(n2144), .CK(clk), .RN(
n5446), .Q(FPADDSUB_Shift_reg_FLAGS_7[2]), .QN(n5232) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1188), .CK(clk), .RN(
n5465), .Q(FPADDSUB_DmP_mant_SFG_SWR[17]), .QN(n5155) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1197), .CK(clk), .RN(
n5461), .Q(FPADDSUB_DmP_mant_SFG_SWR[8]), .QN(n5239) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1192), .CK(clk), .RN(
n5461), .Q(FPADDSUB_DmP_mant_SFG_SWR[13]), .QN(n5247) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1193), .CK(clk), .RN(
n5463), .Q(FPADDSUB_DmP_mant_SFG_SWR[12]), .QN(n5244) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1195), .CK(clk), .RN(
n5462), .Q(FPADDSUB_DmP_mant_SFG_SWR[10]), .QN(n5241) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1191), .CK(clk), .RN(
n5443), .Q(FPADDSUB_DmP_mant_SFG_SWR[14]), .QN(n5184) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1194), .CK(clk), .RN(
n5462), .Q(FPADDSUB_DmP_mant_SFG_SWR[11]), .QN(n5243) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1190), .CK(clk), .RN(
n5465), .Q(FPADDSUB_DmP_mant_SFG_SWR[15]), .QN(n5249) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1182), .CK(clk), .RN(
n5465), .Q(FPADDSUB_DmP_mant_SFG_SWR[23]), .QN(n5330) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1183), .CK(clk), .RN(
n5465), .Q(FPADDSUB_DmP_mant_SFG_SWR[22]), .QN(n5204) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1189), .CK(clk), .RN(
n5442), .Q(FPADDSUB_DmP_mant_SFG_SWR[16]), .QN(n5256) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1199), .CK(clk), .RN(
n5444), .Q(FPADDSUB_DmP_mant_SFG_SWR[6]), .QN(n5181) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1344), .CK(clk), .RN(
n5447), .Q(FPADDSUB_Raw_mant_NRM_SWR[5]), .QN(n5193) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1181), .CK(clk), .RN(
n5466), .Q(FPADDSUB_DmP_mant_SFG_SWR[24]), .QN(n5351) );
DFFRX1TS FPSENCOS_VAR_CONT_temp_reg_1_ ( .D(n2136), .CK(clk), .RN(n5484),
.Q(FPSENCOS_cont_var_out[1]), .QN(n5319) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1343), .CK(clk), .RN(
n2295), .Q(FPADDSUB_Raw_mant_NRM_SWR[6]), .QN(n5355) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n1613), .CK(clk), .RN(
n5506), .Q(FPMULT_Add_result[7]), .QN(n5366) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1342), .CK(clk), .RN(
n5449), .Q(FPADDSUB_Raw_mant_NRM_SWR[7]), .QN(n5289) );
DFFRX1TS FPSENCOS_reg_operation_Q_reg_0_ ( .D(n2080), .CK(clk), .RN(n5500),
.Q(FPSENCOS_d_ff1_operation_out), .QN(n5178) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_1_ ( .D(n2134), .CK(clk), .RN(n5485),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[1]), .QN(n5231) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_0_ ( .D(n2135), .CK(clk), .RN(n5492),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[0]), .QN(n5357) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n1514), .CK(
clk), .RN(n5510), .Q(FPMULT_Sgf_normalized_result[9]), .QN(n5371) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n1516), .CK(
clk), .RN(n5510), .Q(FPMULT_Sgf_normalized_result[11]), .QN(n5370) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n1621), .CK(
clk), .RN(n5509), .Q(FPMULT_Sgf_normalized_result[23]), .QN(n5233) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n1467), .CK(clk), .RN(
n5466), .Q(result_add_subt[29]), .QN(n5228) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n1466), .CK(clk), .RN(
n5438), .Q(result_add_subt[30]), .QN(n5214) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_30_ ( .D(n1854), .CK(clk), .RN(
n5493), .Q(FPSENCOS_d_ff2_Y[30]), .QN(n5374) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_29_ ( .D(n1855), .CK(clk), .RN(
n5494), .Q(FPSENCOS_d_ff2_Y[29]), .QN(n5372) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_27_ ( .D(n1857), .CK(clk), .RN(
n5496), .Q(FPSENCOS_d_ff2_Y[27]), .QN(n5373) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1339), .CK(clk), .RN(
n5447), .Q(FPADDSUB_Raw_mant_NRM_SWR[10]), .QN(n5174) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_28_ ( .D(n1954), .CK(clk), .RN(
n5496), .Q(FPSENCOS_d_ff2_X[28]), .QN(n5356) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_26_ ( .D(n1858), .CK(clk), .RN(
n5474), .Q(FPSENCOS_d_ff2_Y[26]), .QN(n5377) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_25_ ( .D(n1859), .CK(clk), .RN(
n5493), .Q(FPSENCOS_d_ff2_Y[25]), .QN(n5376) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_24_ ( .D(n1860), .CK(clk), .RN(
n5470), .Q(FPSENCOS_d_ff2_Y[24]), .QN(n5375) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1338), .CK(clk), .RN(
n5440), .Q(FPADDSUB_Raw_mant_NRM_SWR[11]), .QN(n5166) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n1517), .CK(
clk), .RN(n5509), .Q(FPMULT_Sgf_normalized_result[12]), .QN(n5259) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n1356), .CK(clk), .RN(
n5438), .Q(result_add_subt[31]), .QN(n5227) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n1511), .CK(
clk), .RN(n5508), .Q(FPMULT_Sgf_normalized_result[6]), .QN(n5245) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_23_ ( .D(n1465), .CK(clk), .RN(n5444),
.Q(FPADDSUB_DMP_EXP_EWSW[23]), .QN(n5348) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n1521), .CK(
clk), .RN(n5510), .Q(FPMULT_Sgf_normalized_result[16]), .QN(n5290) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n1523), .CK(
clk), .RN(n5506), .Q(FPMULT_Sgf_normalized_result[18]), .QN(n5335) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n1468), .CK(clk), .RN(
n5439), .Q(result_add_subt[28]), .QN(n5213) );
DFFXLTS FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_Data_S_o_reg_0_ (
.D(mult_x_309_n33), .CK(clk), .Q(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[0]), .QN(
DP_OP_497J224_123_3916_n59) );
DFFSX1TS R_4 ( .D(n5435), .CK(clk), .SN(n5476), .Q(n5524) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_5_ ( .D(n2147), .CK(clk), .RN(
n5468), .Q(n5179), .QN(n5361) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_7_ ( .D(n1836), .CK(clk), .RN(
n5441), .Q(FPADDSUB_intDY_EWSW[7]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_5_ ( .D(n1838), .CK(clk), .RN(
n5445), .Q(FPADDSUB_intDY_EWSW[5]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_17_ ( .D(n1332), .CK(clk), .RN(
n5454), .Q(FPADDSUB_Raw_mant_NRM_SWR[17]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_21_ ( .D(n1319), .CK(clk), .RN(
n5458), .Q(FPADDSUB_Raw_mant_NRM_SWR[21]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_10_ ( .D(n1833), .CK(clk), .RN(
n5443), .Q(FPADDSUB_intDY_EWSW[10]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_16_ ( .D(n1827), .CK(clk), .RN(
n5438), .Q(FPADDSUB_intDY_EWSW[16]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_27_ ( .D(n1816), .CK(clk), .RN(
n5467), .Q(FPADDSUB_intDY_EWSW[27]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_9_ ( .D(n1834), .CK(clk), .RN(
n5448), .Q(FPADDSUB_intDY_EWSW[9]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_24_ ( .D(n1917), .CK(clk), .RN(
n5446), .Q(FPADDSUB_intDX_EWSW[24]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_2_ ( .D(n1841), .CK(clk), .RN(
n3389), .Q(FPADDSUB_intDY_EWSW[2]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_16_ ( .D(n1246), .CK(clk), .RN(n5459),
.Q(FPADDSUB_DMP_SFG[16]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_22_ ( .D(n1206), .CK(clk), .RN(n5460),
.Q(FPADDSUB_DMP_SFG[22]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1340), .CK(clk), .RN(
n5452), .Q(FPADDSUB_Raw_mant_NRM_SWR[9]) );
DFFRX2TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n1505), .CK(
clk), .RN(n5512), .Q(FPMULT_Sgf_normalized_result[0]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_6_ ( .D(n1238), .CK(clk), .RN(n5464),
.Q(FPADDSUB_DMP_SFG[6]) );
DFFRX2TS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n1351), .CK(clk), .RN(n5441),
.Q(FPADDSUB_ADD_OVRFLW_NRM) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1185), .CK(clk), .RN(
n5466), .Q(FPADDSUB_DmP_mant_SFG_SWR[20]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1184), .CK(clk), .RN(
n5468), .Q(FPADDSUB_DmP_mant_SFG_SWR[21]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1201), .CK(clk), .RN(
n5460), .Q(FPADDSUB_DmP_mant_SFG_SWR[4]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_13_ ( .D(n1242), .CK(clk), .RN(n5462),
.Q(FPADDSUB_DMP_SFG[13]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_14_ ( .D(n1258), .CK(clk), .RN(n5444),
.Q(FPADDSUB_DMP_SFG[14]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_21_ ( .D(n1218), .CK(clk), .RN(n5459),
.Q(FPADDSUB_DMP_SFG[21]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1196), .CK(clk), .RN(
n5459), .Q(FPADDSUB_DmP_mant_SFG_SWR[9]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1186), .CK(clk), .RN(
n5467), .Q(FPADDSUB_DmP_mant_SFG_SWR[19]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_19_ ( .D(n1806), .CK(clk), .RN(n5452), .Q(FPADDSUB_Data_array_SWR[15]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_22_ ( .D(n1809), .CK(clk), .RN(n3390), .Q(FPADDSUB_Data_array_SWR[18]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_21_ ( .D(n1808), .CK(clk), .RN(n5455), .Q(FPADDSUB_Data_array_SWR[17]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1347), .CK(clk), .RN(
n5450), .Q(FPADDSUB_Raw_mant_NRM_SWR[2]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1349), .CK(clk), .RN(
n5452), .Q(FPADDSUB_Raw_mant_NRM_SWR[0]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_16_ ( .D(n1803), .CK(clk), .RN(n5465), .Q(FPADDSUB_Data_array_SWR[12]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_13_ ( .D(n1800), .CK(clk), .RN(n5443), .Q(FPADDSUB_Data_array_SWR[10]) );
DFFRX2TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n2191), .CK(
clk), .RN(n5465), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_15_ ( .D(n1210), .CK(clk), .RN(n5461),
.Q(FPADDSUB_DMP_SFG[15]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n1508), .CK(
clk), .RN(n5509), .Q(FPMULT_Sgf_normalized_result[3]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_29_ ( .D(n1953), .CK(clk), .RN(
n5495), .Q(FPSENCOS_d_ff2_X[29]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_27_ ( .D(n1955), .CK(clk), .RN(
n5495), .Q(FPSENCOS_d_ff2_X[27]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n1526), .CK(
clk), .RN(n5504), .Q(FPMULT_Sgf_normalized_result[21]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n5487), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDX_Q_reg_31_ ( .D(n1910), .CK(clk), .RN(
n2295), .Q(FPADDSUB_intDX_EWSW[31]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_23_ ( .D(n1959), .CK(clk), .RN(
n5502), .Q(FPSENCOS_d_ff2_X[23]) );
DFFRX1TS FPMULT_Sel_C_Q_reg_0_ ( .D(n1528), .CK(clk), .RN(n5509), .Q(
FPMULT_FSM_selector_C) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n1527), .CK(
clk), .RN(n5505), .Q(FPMULT_Sgf_normalized_result[22]) );
DFFRX1TS FPMULT_Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n1585), .CK(clk), .RN(
n5512), .Q(FPMULT_Exp_module_Overflow_flag_A) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_30_ ( .D(n1952), .CK(clk), .RN(
n5496), .Q(FPSENCOS_d_ff2_X[30]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1200), .CK(clk), .RN(
n5464), .Q(FPADDSUB_DmP_mant_SFG_SWR[5]), .QN(n5180) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_9_ ( .D(n1279), .CK(clk), .RN(n5440),
.Q(FPADDSUB_DMP_SFG[9]), .QN(n2387) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n2078), .CK(clk), .RN(
n5445), .Q(FPADDSUB_left_right_SHT2), .QN(n2243) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_4_ ( .D(n1234), .CK(clk), .RN(n5462),
.Q(FPADDSUB_DMP_SFG[4]), .QN(n5238) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_26_ ( .D(n1956), .CK(clk), .RN(
n5497), .Q(FPSENCOS_d_ff2_X[26]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_25_ ( .D(n1957), .CK(clk), .RN(
n5494), .Q(FPSENCOS_d_ff2_X[25]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_24_ ( .D(n1958), .CK(clk), .RN(
n5489), .Q(FPSENCOS_d_ff2_X[24]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_25_ ( .D(n1463), .CK(clk), .RN(n5443),
.Q(FPADDSUB_DMP_EXP_EWSW[25]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_24_ ( .D(n1315), .CK(clk), .RN(
n5453), .Q(FPADDSUB_Raw_mant_NRM_SWR[24]), .QN(n5250) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_30_ ( .D(n1559), .CK(clk),
.RN(n5476), .Q(FPMULT_P_Sgf[30]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n5489), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]) );
DFFRX1TS operation_dff_Q_reg_0_ ( .D(operation[1]), .CK(clk), .RN(n5501),
.Q(operation_reg[0]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_29_ ( .D(n1558), .CK(clk),
.RN(n5481), .Q(FPMULT_P_Sgf[29]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_46_ ( .D(n1575), .CK(clk),
.RN(n5477), .Q(FPMULT_P_Sgf[46]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n1662), .CK(clk),
.RN(n5512), .Q(FPMULT_Op_MX[4]), .QN(n2398) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_23_ ( .D(n1417), .CK(clk), .RN(n5446),
.Q(FPADDSUB_DmP_EXP_EWSW[23]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_43_ ( .D(n1572), .CK(clk),
.RN(n5472), .Q(FPMULT_P_Sgf[43]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n1649), .CK(clk),
.RN(n5507), .Q(FPMULT_Op_MY[23]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_25_ ( .D(n1554), .CK(clk),
.RN(n5483), .Q(FPMULT_P_Sgf[25]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_27_ ( .D(n1556), .CK(clk),
.RN(n5482), .Q(FPMULT_P_Sgf[27]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_35_ ( .D(n1564), .CK(clk),
.RN(n5480), .Q(FPMULT_P_Sgf[35]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_36_ ( .D(n1565), .CK(clk),
.RN(n5479), .Q(FPMULT_P_Sgf[36]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_31_ ( .D(n1733), .CK(clk), .RN(
n5501), .Q(FPSENCOS_d_ff2_Z[31]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n1599), .CK(clk),
.RN(n1480), .Q(FPMULT_Add_result[21]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n1610), .CK(clk),
.RN(n5505), .Q(FPMULT_Add_result[10]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_8_ ( .D(n1250), .CK(clk), .RN(n5459),
.Q(FPADDSUB_DMP_SFG[8]), .QN(n2388) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n1605), .CK(clk),
.RN(n5505), .Q(FPMULT_Add_result[15]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n1682), .CK(clk),
.RN(n5503), .Q(FPMULT_Op_MX[24]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1180), .CK(clk), .RN(
n5467), .Q(FPADDSUB_DmP_mant_SFG_SWR[25]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1204), .CK(clk), .RN(
n5460), .Q(FPADDSUB_DmP_mant_SFG_SWR[1]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_7_ ( .D(n1587), .CK(clk), .RN(
n5504), .Q(FPMULT_exp_oper_result[7]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_6_ ( .D(n1588), .CK(clk), .RN(
n5509), .Q(FPMULT_exp_oper_result[6]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_5_ ( .D(n1589), .CK(clk), .RN(
n5506), .Q(FPMULT_exp_oper_result[5]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_32_ ( .D(n1561), .CK(clk),
.RN(n5483), .Q(FPMULT_P_Sgf[32]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_5_ ( .D(n2057), .CK(clk), .RN(n5482), .Q(
FPSENCOS_d_ff_Xn[5]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_1_ ( .D(n2069), .CK(clk), .RN(n5479), .Q(
FPSENCOS_d_ff_Xn[1]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_7_ ( .D(n2051), .CK(clk), .RN(n5485), .Q(
FPSENCOS_d_ff_Xn[7]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_2_ ( .D(n2066), .CK(clk), .RN(n5489), .Q(
FPSENCOS_d_ff_Xn[2]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_3_ ( .D(n2063), .CK(clk), .RN(n5500), .Q(
FPSENCOS_d_ff_Xn[3]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_12_ ( .D(n2036), .CK(clk), .RN(n5471), .Q(
FPSENCOS_d_ff_Xn[12]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_10_ ( .D(n2042), .CK(clk), .RN(n5484), .Q(
FPSENCOS_d_ff_Xn[10]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_14_ ( .D(n2030), .CK(clk), .RN(n5483), .Q(
FPSENCOS_d_ff_Xn[14]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_16_ ( .D(n2024), .CK(clk), .RN(n5498), .Q(
FPSENCOS_d_ff_Xn[16]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_13_ ( .D(n2033), .CK(clk), .RN(n5475), .Q(
FPSENCOS_d_ff_Xn[13]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_6_ ( .D(n2054), .CK(clk), .RN(n5475), .Q(
FPSENCOS_d_ff_Xn[6]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_17_ ( .D(n2021), .CK(clk), .RN(n5497), .Q(
FPSENCOS_d_ff_Xn[17]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_20_ ( .D(n2012), .CK(clk), .RN(n5498), .Q(
FPSENCOS_d_ff_Xn[20]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_19_ ( .D(n2015), .CK(clk), .RN(n5500), .Q(
FPSENCOS_d_ff_Xn[19]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_28_ ( .D(n1769), .CK(clk), .RN(n5497), .Q(
FPSENCOS_d_ff_Xn[28]) );
DFFRX1TS reg_dataB_Q_reg_28_ ( .D(Data_2[28]), .CK(clk), .RN(n5471), .Q(
dataB[28]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_9_ ( .D(n2045), .CK(clk), .RN(n5478), .Q(
FPSENCOS_d_ff_Xn[9]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_0_ ( .D(n2072), .CK(clk), .RN(n5488), .Q(
FPSENCOS_d_ff_Xn[0]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_11_ ( .D(n2039), .CK(clk), .RN(n5499), .Q(
FPSENCOS_d_ff_Xn[11]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_8_ ( .D(n2048), .CK(clk), .RN(n5499), .Q(
FPSENCOS_d_ff_Xn[8]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_21_ ( .D(n2009), .CK(clk), .RN(n5485), .Q(
FPSENCOS_d_ff_Xn[21]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_18_ ( .D(n2018), .CK(clk), .RN(n5494), .Q(
FPSENCOS_d_ff_Xn[18]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_15_ ( .D(n2027), .CK(clk), .RN(n5496), .Q(
FPSENCOS_d_ff_Xn[15]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_22_ ( .D(n2006), .CK(clk), .RN(n5495), .Q(
FPSENCOS_d_ff_Xn[22]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_5_ ( .D(n2058), .CK(clk), .RN(n5472), .Q(
FPSENCOS_d_ff_Yn[5]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_9_ ( .D(n2046), .CK(clk), .RN(n5482), .Q(
FPSENCOS_d_ff_Yn[9]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_0_ ( .D(n2073), .CK(clk), .RN(n5486), .Q(
FPSENCOS_d_ff_Yn[0]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_7_ ( .D(n2052), .CK(clk), .RN(n5485), .Q(
FPSENCOS_d_ff_Yn[7]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_2_ ( .D(n2067), .CK(clk), .RN(n5469), .Q(
FPSENCOS_d_ff_Yn[2]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_3_ ( .D(n2064), .CK(clk), .RN(n5469), .Q(
FPSENCOS_d_ff_Yn[3]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_12_ ( .D(n2037), .CK(clk), .RN(n5471), .Q(
FPSENCOS_d_ff_Yn[12]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_10_ ( .D(n2043), .CK(clk), .RN(n5491), .Q(
FPSENCOS_d_ff_Yn[10]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_11_ ( .D(n2040), .CK(clk), .RN(n5499), .Q(
FPSENCOS_d_ff_Yn[11]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_6_ ( .D(n2055), .CK(clk), .RN(n5481), .Q(
FPSENCOS_d_ff_Yn[6]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_4_ ( .D(n2061), .CK(clk), .RN(n5480), .Q(
FPSENCOS_d_ff_Yn[4]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_26_ ( .D(n1776), .CK(clk), .RN(n5496), .Q(
FPSENCOS_d_ff_Yn[26]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_25_ ( .D(n1779), .CK(clk), .RN(n5495), .Q(
FPSENCOS_d_ff_Yn[25]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_24_ ( .D(n1782), .CK(clk), .RN(n5491), .Q(
FPSENCOS_d_ff_Yn[24]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_23_ ( .D(n1785), .CK(clk), .RN(n3388), .Q(
FPSENCOS_d_ff_Yn[23]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_47_ ( .D(n1694), .CK(clk),
.RN(n5490), .Q(FPMULT_P_Sgf[47]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_6_ ( .D(n1793), .CK(clk), .RN(n5447),
.Q(FPADDSUB_Data_array_SWR[5]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n1653), .CK(clk),
.RN(n5507), .Q(FPMULT_Op_MY[27]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_4_ ( .D(n1590), .CK(clk), .RN(
n5508), .Q(FPMULT_exp_oper_result[4]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_3_ ( .D(n1591), .CK(clk), .RN(
n5508), .Q(FPMULT_exp_oper_result[3]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_2_ ( .D(n1592), .CK(clk), .RN(
n5510), .Q(FPMULT_exp_oper_result[2]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_0_ ( .D(n1594), .CK(clk), .RN(
n5509), .Q(FPMULT_exp_oper_result[0]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n1684), .CK(clk),
.RN(n5503), .Q(FPMULT_Op_MX[26]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n1685), .CK(clk),
.RN(n5503), .Q(FPMULT_Op_MX[27]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n1686), .CK(clk),
.RN(n5503), .Q(FPMULT_Op_MX[28]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n1683), .CK(clk),
.RN(n5503), .Q(FPMULT_Op_MX[25]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_12_ ( .D(n1541), .CK(clk),
.RN(n5477), .Q(FPMULT_P_Sgf[12]) );
DFFSX1TS R_11 ( .D(n5434), .CK(clk), .SN(n5478), .Q(n5522) );
DFFSX1TS R_3 ( .D(n5436), .CK(clk), .SN(n5480), .Q(n5523) );
DFFRX1TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_31_ ( .D(n1728), .CK(clk), .RN(
n5451), .Q(FPADDSUB_intDY_EWSW[31]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1418), .CK(clk), .RN(
n5438), .Q(FPADDSUB_DMP_exp_NRM2_EW[7]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1423), .CK(clk), .RN(
n5468), .Q(FPADDSUB_DMP_exp_NRM2_EW[6]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1428), .CK(clk), .RN(
n5446), .Q(FPADDSUB_DMP_exp_NRM2_EW[5]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1433), .CK(clk), .RN(
n5439), .Q(FPADDSUB_DMP_exp_NRM2_EW[4]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1438), .CK(clk), .RN(
n5467), .Q(FPADDSUB_DMP_exp_NRM2_EW[3]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1443), .CK(clk), .RN(
n5468), .Q(FPADDSUB_DMP_exp_NRM2_EW[2]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1448), .CK(clk), .RN(
n5442), .Q(FPADDSUB_DMP_exp_NRM2_EW[1]) );
DFFRX1TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1453), .CK(clk), .RN(
n5439), .Q(FPADDSUB_DMP_exp_NRM2_EW[0]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n5486), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_20_ ( .D(n1549), .CK(clk),
.RN(n5519), .Q(FPMULT_P_Sgf[20]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_17_ ( .D(n1546), .CK(clk),
.RN(n5519), .Q(FPMULT_P_Sgf[17]) );
DFFRX1TS reg_dataB_Q_reg_30_ ( .D(Data_2[30]), .CK(clk), .RN(n5492), .Q(
dataB[30]) );
DFFRX1TS reg_dataA_Q_reg_30_ ( .D(Data_1[30]), .CK(clk), .RN(n5488), .Q(
dataA[30]) );
DFFRX1TS reg_dataA_Q_reg_29_ ( .D(Data_1[29]), .CK(clk), .RN(n5492), .Q(
dataA[29]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_3_ ( .D(n1532), .CK(clk),
.RN(n5475), .Q(FPMULT_P_Sgf[3]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_23_ ( .D(n1552), .CK(clk),
.RN(n5480), .Q(FPMULT_P_Sgf[23]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_12_ ( .D(n2122), .CK(clk), .RN(n5486), .Q(
FPSENCOS_d_ff3_LUT_out[12]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_6_ ( .D(n1837), .CK(clk), .RN(
n5438), .Q(FPADDSUB_intDY_EWSW[6]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_4_ ( .D(n1839), .CK(clk), .RN(
n5449), .Q(FPADDSUB_intDY_EWSW[4]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_28_ ( .D(n1815), .CK(clk), .RN(
n5439), .Q(FPADDSUB_intDY_EWSW[28]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_19_ ( .D(n1321), .CK(clk), .RN(
n5454), .Q(FPADDSUB_Raw_mant_NRM_SWR[19]) );
DFFRX2TS FPADDSUB_INPUT_STAGE_OPERANDY_Q_reg_0_ ( .D(n1843), .CK(clk), .RN(
n5451), .Q(FPADDSUB_intDY_EWSW[0]) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_18_ ( .D(n1805), .CK(clk), .RN(n5451), .Q(FPADDSUB_Data_array_SWR[14]) );
DFFRX2TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n1506), .CK(
clk), .RN(n5509), .Q(FPMULT_Sgf_normalized_result[1]) );
DFFRX4TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n2075), .CK(clk), .RN(
n5455), .Q(FPADDSUB_shift_value_SHT2_EWR[4]), .QN(n5176) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n1524), .CK(
clk), .RN(n5508), .Q(FPMULT_Sgf_normalized_result[19]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(n2292), .CK(clk),
.RN(n5489), .Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_10_ ( .D(n1797), .CK(clk), .RN(n5445), .Q(FPADDSUB_Data_array_SWR[9]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_9_ ( .D(n1796), .CK(clk), .RN(n5459),
.Q(FPADDSUB_Data_array_SWR[8]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n5487), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_20_ ( .D(n1320), .CK(clk), .RN(
n5456), .Q(FPADDSUB_Raw_mant_NRM_SWR[20]), .QN(n5258) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_26_ ( .D(n1462), .CK(clk), .RN(n5460),
.Q(FPADDSUB_DMP_EXP_EWSW[26]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_7_ ( .D(n1794), .CK(clk), .RN(n5466),
.Q(FPADDSUB_Data_array_SWR[6]) );
DFFRX1TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_4_ ( .D(n1791), .CK(clk), .RN(n5441),
.Q(FPADDSUB_Data_array_SWR[4]) );
DFFRX1TS operation_dff_Q_reg_1_ ( .D(operation[2]), .CK(clk), .RN(n5491),
.Q(operation_reg[1]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_27_ ( .D(n1772), .CK(clk), .RN(n5498), .Q(
FPSENCOS_d_ff_Xn[27]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_29_ ( .D(n1766), .CK(clk), .RN(n5498), .Q(
FPSENCOS_d_ff_Xn[29]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_30_ ( .D(n1729), .CK(clk), .RN(n5495), .Q(
FPSENCOS_d_ff_Xn[30]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_16_ ( .D(n1973), .CK(clk), .RN(
n5494), .Q(FPSENCOS_d_ff2_X[16]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_22_ ( .D(n1961), .CK(clk), .RN(
n5474), .Q(FPSENCOS_d_ff2_X[22]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_15_ ( .D(n1975), .CK(clk), .RN(
n5493), .Q(FPSENCOS_d_ff2_X[15]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_18_ ( .D(n1969), .CK(clk), .RN(
n5496), .Q(FPSENCOS_d_ff2_X[18]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_24_ ( .D(n1781), .CK(clk), .RN(n5472), .Q(
FPSENCOS_d_ff_Xn[24]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_28_ ( .D(n1770), .CK(clk), .RN(n5474), .Q(
FPSENCOS_d_ff_Yn[28]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_29_ ( .D(n1767), .CK(clk), .RN(n5493), .Q(
FPSENCOS_d_ff_Yn[29]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_30_ ( .D(n1730), .CK(clk), .RN(n5474), .Q(
FPSENCOS_d_ff_Yn[30]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_22_ ( .D(n2007), .CK(clk), .RN(n5493), .Q(
FPSENCOS_d_ff_Yn[22]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_15_ ( .D(n2028), .CK(clk), .RN(n5494), .Q(
FPSENCOS_d_ff_Yn[15]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_18_ ( .D(n2019), .CK(clk), .RN(n5495), .Q(
FPSENCOS_d_ff_Yn[18]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_21_ ( .D(n2010), .CK(clk), .RN(n5497), .Q(
FPSENCOS_d_ff_Yn[21]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_16_ ( .D(n2025), .CK(clk), .RN(n5474), .Q(
FPSENCOS_d_ff_Yn[16]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_8_ ( .D(n2049), .CK(clk), .RN(n5493), .Q(
FPSENCOS_d_ff_Yn[8]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_23_ ( .D(n1784), .CK(clk), .RN(n3388), .Q(
FPSENCOS_d_ff_Xn[23]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n1688), .CK(clk),
.RN(n5503), .Q(FPMULT_Op_MX[30]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n1655), .CK(clk),
.RN(n5507), .Q(FPMULT_Op_MY[29]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1187), .CK(clk), .RN(
n5446), .Q(FPADDSUB_DmP_mant_SFG_SWR[18]), .QN(n5154) );
DFFRX4TS FPSENCOS_ITER_CONT_temp_reg_3_ ( .D(n2138), .CK(clk), .RN(n5492),
.Q(FPSENCOS_cont_iter_out[3]), .QN(n5313) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_11_ ( .D(n1540), .CK(clk),
.RN(n5477), .Q(FPMULT_P_Sgf[11]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_19_ ( .D(n1548), .CK(clk),
.RN(n5472), .Q(FPMULT_P_Sgf[19]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_18_ ( .D(n1547), .CK(clk),
.RN(n5493), .Q(FPMULT_P_Sgf[18]) );
DFFRX1TS FPADDSUB_INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1731), .CK(clk), .RN(
n3389), .Q(FPADDSUB_intAS) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_1_ ( .D(n2132), .CK(clk), .RN(n5484), .Q(
FPSENCOS_d_ff3_LUT_out[1]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_21_ ( .D(n1550), .CK(clk),
.RN(n5496), .Q(FPMULT_P_Sgf[21]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_16_ ( .D(n1545), .CK(clk),
.RN(n5495), .Q(FPMULT_P_Sgf[16]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1341), .CK(clk), .RN(
n5448), .Q(FPADDSUB_Raw_mant_NRM_SWR[8]), .QN(n5264) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_1_ ( .D(n1530), .CK(clk),
.RN(n5494), .Q(FPMULT_P_Sgf[1]) );
DFFRX1TS reg_dataA_Q_reg_25_ ( .D(Data_1[25]), .CK(clk), .RN(n5491), .Q(
dataA[25]) );
DFFRX1TS reg_dataA_Q_reg_28_ ( .D(Data_1[28]), .CK(clk), .RN(n5471), .Q(
dataA[28]) );
DFFRX1TS reg_dataB_Q_reg_26_ ( .D(Data_2[26]), .CK(clk), .RN(n5488), .Q(
dataB[26]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_2_ ( .D(n2131), .CK(clk), .RN(n5489), .Q(
FPSENCOS_d_ff3_LUT_out[2]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_24_ ( .D(n2116), .CK(clk), .RN(n5487), .Q(
FPSENCOS_d_ff3_LUT_out[24]) );
DFFRX1TS reg_dataA_Q_reg_23_ ( .D(Data_1[23]), .CK(clk), .RN(n5484), .Q(
dataA[23]) );
DFFRX1TS reg_dataA_Q_reg_27_ ( .D(Data_1[27]), .CK(clk), .RN(n5491), .Q(
dataA[27]) );
DFFRX1TS reg_dataB_Q_reg_24_ ( .D(Data_2[24]), .CK(clk), .RN(n5472), .Q(
dataB[24]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_7_ ( .D(n1536), .CK(clk),
.RN(n5477), .Q(FPMULT_P_Sgf[7]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DmP_Q_reg_27_ ( .D(n1413), .CK(clk), .RN(n5452),
.Q(FPADDSUB_DmP_EXP_EWSW[27]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_6_ ( .D(n1535), .CK(clk),
.RN(n5477), .Q(FPMULT_P_Sgf[6]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_5_ ( .D(n1534), .CK(clk),
.RN(n5474), .Q(FPMULT_P_Sgf[5]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_15_ ( .D(n1544), .CK(clk),
.RN(n5500), .Q(FPMULT_P_Sgf[15]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_14_ ( .D(n1543), .CK(clk),
.RN(n5477), .Q(FPMULT_P_Sgf[14]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_10_ ( .D(n1539), .CK(clk),
.RN(n5477), .Q(FPMULT_P_Sgf[10]) );
DFFRX1TS FPADDSUB_EXP_STAGE_DMP_Q_reg_24_ ( .D(n1464), .CK(clk), .RN(n5443),
.Q(FPADDSUB_DMP_EXP_EWSW[24]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_24_ ( .D(n1553), .CK(clk),
.RN(n5479), .Q(FPMULT_P_Sgf[24]) );
DFFRX1TS FPSENCOS_reg_LUT_Q_reg_3_ ( .D(n2130), .CK(clk), .RN(n5484), .Q(
FPSENCOS_d_ff3_LUT_out[3]) );
DFFSX2TS FPADDSUB_inst_ShiftRegister_Q_reg_0_ ( .D(n2395), .CK(clk), .SN(
n5466), .Q(n5353), .QN(n5515) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_25_ ( .D(n1410), .CK(clk), .RN(
n5448), .Q(FPADDSUB_Raw_mant_NRM_SWR[25]), .QN(n2218) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1205), .CK(clk), .RN(
n5460), .Q(FPADDSUB_DmP_mant_SFG_SWR[0]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_0_ ( .D(n1293), .CK(clk), .RN(n5456),
.Q(FPADDSUB_DMP_SFG[0]), .QN(n5234) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n1640), .CK(clk),
.RN(n2200), .Q(FPMULT_Op_MY[14]), .QN(n5171) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n1638), .CK(clk),
.RN(n5511), .Q(FPMULT_Op_MY[12]), .QN(n5163) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1203), .CK(clk), .RN(
n5444), .Q(FPADDSUB_DmP_mant_SFG_SWR[2]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1202), .CK(clk), .RN(
n5463), .Q(FPADDSUB_DmP_mant_SFG_SWR[3]), .QN(n5235) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n1669), .CK(clk),
.RN(n5512), .QN(n2378) );
ADDFX1TS DP_OP_234J224_132_4955_U2 ( .A(n5437), .B(FPMULT_S_Oper_A_exp[8]),
.CI(DP_OP_234J224_132_4955_n2), .CO(DP_OP_234J224_132_4955_n1), .S(
FPMULT_Exp_module_Data_S[8]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_2_ ( .D(n1307), .CK(clk), .RN(n5455),
.Q(FPADDSUB_DMP_SFG[2]), .QN(n5237) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n1670), .CK(clk),
.RN(n5504), .Q(FPMULT_Op_MX[12]) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n1639), .CK(clk),
.RN(n5511), .Q(n2198) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n1672), .CK(clk),
.RN(n5512), .Q(FPMULT_Op_MX[14]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n1674), .CK(clk),
.RN(n5504), .Q(FPMULT_Op_MX[16]) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n1663), .CK(clk),
.RN(n5512), .Q(FPMULT_Op_MX[5]), .QN(n2383) );
DFFRX2TS FPMULT_Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n1632), .CK(clk),
.RN(n5513), .Q(FPMULT_Op_MY[6]), .QN(n2381) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n1677), .CK(clk),
.RN(n5512), .Q(n2197) );
DFFRX2TS FPMULT_Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n1678), .CK(clk),
.RN(n5504), .Q(FPMULT_Op_MX[20]) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n1667), .CK(clk),
.RN(n5504), .Q(n2196) );
DFFRX4TS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1350), .CK(clk), .RN(
n5442), .Q(FPADDSUB_ADD_OVRFLW_NRM2), .QN(n2195) );
CMPR32X2TS DP_OP_26J224_129_1325_U8 ( .A(DP_OP_26J224_129_1325_n17), .B(
FPADDSUB_DMP_exp_NRM2_EW[1]), .C(DP_OP_26J224_129_1325_n8), .CO(
DP_OP_26J224_129_1325_n7), .S(FPADDSUB_exp_rslt_NRM2_EW1[1]) );
CMPR32X2TS DP_OP_26J224_129_1325_U7 ( .A(DP_OP_26J224_129_1325_n16), .B(
FPADDSUB_DMP_exp_NRM2_EW[2]), .C(DP_OP_26J224_129_1325_n7), .CO(
DP_OP_26J224_129_1325_n6), .S(FPADDSUB_exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_26J224_129_1325_U6 ( .A(DP_OP_26J224_129_1325_n15), .B(
FPADDSUB_DMP_exp_NRM2_EW[3]), .C(DP_OP_26J224_129_1325_n6), .CO(
DP_OP_26J224_129_1325_n5), .S(FPADDSUB_exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS DP_OP_26J224_129_1325_U5 ( .A(DP_OP_26J224_129_1325_n14), .B(
FPADDSUB_DMP_exp_NRM2_EW[4]), .C(DP_OP_26J224_129_1325_n5), .CO(
DP_OP_26J224_129_1325_n4), .S(FPADDSUB_exp_rslt_NRM2_EW1[4]) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_4_ ( .D(n2146), .CK(clk), .RN(
n5446), .Q(n2194), .QN(n5417) );
CMPR32X2TS DP_OP_26J224_129_1325_U4 ( .A(n2195), .B(
FPADDSUB_DMP_exp_NRM2_EW[5]), .C(DP_OP_26J224_129_1325_n4), .CO(
DP_OP_26J224_129_1325_n3), .S(FPADDSUB_exp_rslt_NRM2_EW1[5]) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_1_ ( .D(n2143), .CK(clk), .RN(
n5442), .Q(FPADDSUB_Shift_reg_FLAGS_7[1]) );
CMPR32X2TS DP_OP_26J224_129_1325_U3 ( .A(n2195), .B(
FPADDSUB_DMP_exp_NRM2_EW[6]), .C(DP_OP_26J224_129_1325_n3), .CO(
DP_OP_26J224_129_1325_n2), .S(FPADDSUB_exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS DP_OP_26J224_129_1325_U2 ( .A(n2195), .B(
FPADDSUB_DMP_exp_NRM2_EW[7]), .C(DP_OP_26J224_129_1325_n2), .CO(
DP_OP_26J224_129_1325_n1), .S(FPADDSUB_exp_rslt_NRM2_EW1[7]) );
DFFRX4TS FPADDSUB_inst_ShiftRegister_Q_reg_6_ ( .D(n2148), .CK(clk), .RN(
n5467), .Q(FPADDSUB_Shift_reg_FLAGS_7_6), .QN(n5225) );
CMPR32X2TS intadd_525_U3 ( .A(FPSENCOS_d_ff2_X[25]), .B(n5170), .C(
intadd_525_n3), .CO(intadd_525_n2), .S(intadd_525_SUM_1_) );
CMPR32X2TS intadd_524_U2 ( .A(FPSENCOS_d_ff2_Y[26]), .B(n5313), .C(
intadd_524_n2), .CO(intadd_524_n1), .S(intadd_524_SUM_2_) );
CMPR32X2TS intadd_525_U2 ( .A(FPSENCOS_d_ff2_X[26]), .B(n5313), .C(
intadd_525_n2), .CO(intadd_525_n1), .S(intadd_525_SUM_2_) );
CMPR32X2TS intadd_523_U4 ( .A(n5358), .B(FPADDSUB_DMP_EXP_EWSW[24]), .C(
intadd_523_CI), .CO(intadd_523_n3), .S(intadd_523_SUM_0_) );
CMPR32X2TS intadd_523_U3 ( .A(n5363), .B(FPADDSUB_DMP_EXP_EWSW[25]), .C(
intadd_523_n3), .CO(intadd_523_n2), .S(intadd_523_SUM_1_) );
CMPR32X2TS intadd_523_U2 ( .A(n5362), .B(FPADDSUB_DMP_EXP_EWSW[26]), .C(
intadd_523_n2), .CO(intadd_523_n1), .S(intadd_523_SUM_2_) );
CMPR32X2TS intadd_519_U2 ( .A(intadd_519_A_7_), .B(intadd_519_B_7_), .C(
intadd_519_n2), .CO(intadd_519_n1), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N10) );
CMPR32X2TS U2217 ( .A(DP_OP_501J224_127_5235_n110), .B(n3063), .C(n3062),
.CO(n3064), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N13) );
AOI222X1TS U2218 ( .A0(n3690), .A1(cordic_result[0]), .B0(n3812), .B1(
FPSENCOS_d_ff_Yn[0]), .C0(n3945), .C1(FPSENCOS_d_ff_Xn[0]), .Y(n3811)
);
AOI222X1TS U2219 ( .A0(n3690), .A1(cordic_result[25]), .B0(n3952), .B1(
FPSENCOS_d_ff_Yn[25]), .C0(n3945), .C1(n2318), .Y(n3953) );
AOI222X1TS U2220 ( .A0(n3690), .A1(cordic_result[30]), .B0(n3955), .B1(
FPSENCOS_d_ff_Yn[30]), .C0(n3945), .C1(FPSENCOS_d_ff_Xn[30]), .Y(n3948) );
AOI222X1TS U2221 ( .A0(n3690), .A1(cordic_result[29]), .B0(n3955), .B1(
FPSENCOS_d_ff_Yn[29]), .C0(n3945), .C1(FPSENCOS_d_ff_Xn[29]), .Y(n3950) );
AOI222X1TS U2222 ( .A0(n3690), .A1(cordic_result[27]), .B0(n3955), .B1(n2315), .C0(n3945), .C1(FPSENCOS_d_ff_Xn[27]), .Y(n3954) );
AOI222X1TS U2223 ( .A0(n3690), .A1(cordic_result[26]), .B0(n3955), .B1(
FPSENCOS_d_ff_Yn[26]), .C0(n3945), .C1(n2317), .Y(n3949) );
AOI222X1TS U2224 ( .A0(n3690), .A1(cordic_result[28]), .B0(n3955), .B1(
FPSENCOS_d_ff_Yn[28]), .C0(n3945), .C1(FPSENCOS_d_ff_Xn[28]), .Y(n3956) );
AOI222X1TS U2225 ( .A0(n3690), .A1(cordic_result[20]), .B0(n3952), .B1(n2313), .C0(n3943), .C1(FPSENCOS_d_ff_Xn[20]), .Y(n3941) );
AOI222X1TS U2226 ( .A0(n3690), .A1(cordic_result[21]), .B0(n3952), .B1(
FPSENCOS_d_ff_Yn[21]), .C0(n3943), .C1(FPSENCOS_d_ff_Xn[21]), .Y(n3944) );
AOI222X1TS U2227 ( .A0(n3690), .A1(cordic_result[23]), .B0(n3952), .B1(
FPSENCOS_d_ff_Yn[23]), .C0(n3943), .C1(FPSENCOS_d_ff_Xn[23]), .Y(n3937) );
AOI222X1TS U2228 ( .A0(n3690), .A1(cordic_result[22]), .B0(n3952), .B1(
FPSENCOS_d_ff_Yn[22]), .C0(n3943), .C1(FPSENCOS_d_ff_Xn[22]), .Y(n3932) );
AOI222X1TS U2229 ( .A0(n4780), .A1(FPSENCOS_d_ff2_Z[10]), .B0(n3807), .B1(
FPSENCOS_d_ff_Zn[10]), .C0(n3806), .C1(FPSENCOS_d_ff1_Z[10]), .Y(n3808) );
AOI222X1TS U2230 ( .A0(n4811), .A1(FPSENCOS_d_ff2_Z[4]), .B0(n3807), .B1(
FPSENCOS_d_ff_Zn[4]), .C0(n3792), .C1(FPSENCOS_d_ff1_Z[4]), .Y(n3793)
);
AOI222X1TS U2231 ( .A0(n3946), .A1(cordic_result[9]), .B0(n3955), .B1(
FPSENCOS_d_ff_Yn[9]), .C0(n3774), .C1(FPSENCOS_d_ff_Xn[9]), .Y(n3775)
);
AOI222X1TS U2232 ( .A0(n3946), .A1(cordic_result[10]), .B0(n3955), .B1(
FPSENCOS_d_ff_Yn[10]), .C0(n3774), .C1(FPSENCOS_d_ff_Xn[10]), .Y(n3773) );
AOI222X1TS U2233 ( .A0(n4886), .A1(cordic_result[7]), .B0(n3955), .B1(
FPSENCOS_d_ff_Yn[7]), .C0(n3774), .C1(FPSENCOS_d_ff_Xn[7]), .Y(n3772)
);
AOI222X1TS U2234 ( .A0(n4886), .A1(cordic_result[3]), .B0(n3812), .B1(
FPSENCOS_d_ff_Yn[3]), .C0(n3945), .C1(FPSENCOS_d_ff_Xn[3]), .Y(n3813)
);
AOI222X1TS U2235 ( .A0(n4886), .A1(cordic_result[2]), .B0(n3812), .B1(
FPSENCOS_d_ff_Yn[2]), .C0(n3945), .C1(FPSENCOS_d_ff_Xn[2]), .Y(n3951)
);
AOI222X1TS U2236 ( .A0(n2225), .A1(FPSENCOS_d_ff2_Z[29]), .B0(n3686), .B1(
FPSENCOS_d_ff_Zn[29]), .C0(n3792), .C1(FPSENCOS_d_ff1_Z[29]), .Y(n3687) );
AOI222X1TS U2237 ( .A0(n2225), .A1(FPSENCOS_d_ff2_Z[27]), .B0(n3686), .B1(
FPSENCOS_d_ff_Zn[27]), .C0(n3792), .C1(FPSENCOS_d_ff1_Z[27]), .Y(n3680) );
AOI222X1TS U2238 ( .A0(n2225), .A1(FPSENCOS_d_ff2_Z[26]), .B0(n3686), .B1(
FPSENCOS_d_ff_Zn[26]), .C0(n3792), .C1(FPSENCOS_d_ff1_Z[26]), .Y(n3683) );
AOI222X1TS U2239 ( .A0(n2225), .A1(FPSENCOS_d_ff2_Z[28]), .B0(n3686), .B1(
FPSENCOS_d_ff_Zn[28]), .C0(n3792), .C1(FPSENCOS_d_ff1_Z[28]), .Y(n3679) );
AOI222X1TS U2240 ( .A0(n3946), .A1(cordic_result[24]), .B0(n3952), .B1(
FPSENCOS_d_ff_Yn[24]), .C0(n3945), .C1(FPSENCOS_d_ff_Xn[24]), .Y(n3947) );
AOI222X1TS U2241 ( .A0(n4886), .A1(cordic_result[1]), .B0(n3952), .B1(n2309),
.C0(n3945), .C1(FPSENCOS_d_ff_Xn[1]), .Y(n3809) );
AOI222X1TS U2242 ( .A0(n4780), .A1(FPSENCOS_d_ff2_Z[14]), .B0(n3807), .B1(
FPSENCOS_d_ff_Zn[14]), .C0(n3804), .C1(FPSENCOS_d_ff1_Z[14]), .Y(n3805) );
AOI222X1TS U2243 ( .A0(n4780), .A1(FPSENCOS_d_ff2_Z[16]), .B0(n3807), .B1(
FPSENCOS_d_ff_Zn[16]), .C0(n3804), .C1(FPSENCOS_d_ff1_Z[16]), .Y(n3798) );
AOI222X1TS U2244 ( .A0(n4780), .A1(FPSENCOS_d_ff2_Z[13]), .B0(n3807), .B1(
FPSENCOS_d_ff_Zn[13]), .C0(n3804), .C1(FPSENCOS_d_ff1_Z[13]), .Y(n3796) );
AOI222X1TS U2245 ( .A0(n4780), .A1(FPSENCOS_d_ff2_Z[17]), .B0(n3807), .B1(
FPSENCOS_d_ff_Zn[17]), .C0(n3804), .C1(FPSENCOS_d_ff1_Z[17]), .Y(n3797) );
AOI222X1TS U2246 ( .A0(n4780), .A1(FPSENCOS_d_ff2_Z[18]), .B0(n3807), .B1(
FPSENCOS_d_ff_Zn[18]), .C0(n3804), .C1(FPSENCOS_d_ff1_Z[18]), .Y(n3803) );
AOI222X1TS U2247 ( .A0(n4780), .A1(FPSENCOS_d_ff2_Z[19]), .B0(n3686), .B1(
FPSENCOS_d_ff_Zn[19]), .C0(n3804), .C1(FPSENCOS_d_ff1_Z[19]), .Y(n3672) );
AOI222X1TS U2248 ( .A0(n4780), .A1(FPSENCOS_d_ff2_Z[15]), .B0(n3807), .B1(
FPSENCOS_d_ff_Zn[15]), .C0(n3804), .C1(FPSENCOS_d_ff1_Z[15]), .Y(n3794) );
AOI222X1TS U2249 ( .A0(n4794), .A1(FPSENCOS_d_ff2_Z[30]), .B0(n3686), .B1(
FPSENCOS_d_ff_Zn[30]), .C0(n3792), .C1(FPSENCOS_d_ff1_Z[30]), .Y(n3682) );
AOI222X1TS U2250 ( .A0(n4811), .A1(FPSENCOS_d_ff2_Z[5]), .B0(n4810), .B1(
FPSENCOS_d_ff_Zn[5]), .C0(n3792), .C1(FPSENCOS_d_ff1_Z[5]), .Y(n3681)
);
AOI222X1TS U2251 ( .A0(n4811), .A1(FPSENCOS_d_ff2_Z[3]), .B0(n4810), .B1(
FPSENCOS_d_ff_Zn[3]), .C0(n3792), .C1(FPSENCOS_d_ff1_Z[3]), .Y(n3685)
);
AOI222X1TS U2252 ( .A0(n3946), .A1(cordic_result[11]), .B0(n3955), .B1(
FPSENCOS_d_ff_Yn[11]), .C0(n3945), .C1(FPSENCOS_d_ff_Xn[11]), .Y(n3810) );
OAI32X1TS U2253 ( .A0(n4784), .A1(n4752), .A2(n3985), .B0(
FPSENCOS_d_ff3_LUT_out[6]), .B1(n4805), .Y(n3986) );
AOI222X1TS U2254 ( .A0(n3636), .A1(FPSENCOS_d_ff2_Z[20]), .B0(n3686), .B1(
FPSENCOS_d_ff_Zn[20]), .C0(n3804), .C1(FPSENCOS_d_ff1_Z[20]), .Y(n3675) );
AOI222X1TS U2255 ( .A0(n3636), .A1(FPSENCOS_d_ff2_Z[25]), .B0(n3686), .B1(
FPSENCOS_d_ff_Zn[25]), .C0(n3804), .C1(FPSENCOS_d_ff1_Z[25]), .Y(n3676) );
AOI222X1TS U2256 ( .A0(n3636), .A1(FPSENCOS_d_ff2_Z[24]), .B0(n3686), .B1(
FPSENCOS_d_ff_Zn[24]), .C0(n3804), .C1(FPSENCOS_d_ff1_Z[24]), .Y(n3677) );
AOI222X1TS U2257 ( .A0(n3636), .A1(FPSENCOS_d_ff2_Z[23]), .B0(n3686), .B1(
FPSENCOS_d_ff_Zn[23]), .C0(n3804), .C1(FPSENCOS_d_ff1_Z[23]), .Y(n3674) );
AOI222X1TS U2258 ( .A0(n3636), .A1(FPSENCOS_d_ff2_Z[22]), .B0(n3686), .B1(
FPSENCOS_d_ff_Zn[22]), .C0(n3804), .C1(FPSENCOS_d_ff1_Z[22]), .Y(n3673) );
AOI222X1TS U2259 ( .A0(n3636), .A1(FPSENCOS_d_ff2_Z[21]), .B0(n3686), .B1(
FPSENCOS_d_ff_Zn[21]), .C0(n3804), .C1(FPSENCOS_d_ff1_Z[21]), .Y(n3678) );
AOI222X1TS U2260 ( .A0(n3946), .A1(cordic_result[12]), .B0(n3955), .B1(
FPSENCOS_d_ff_Yn[12]), .C0(n3943), .C1(FPSENCOS_d_ff_Xn[12]), .Y(n3933) );
AOI222X1TS U2261 ( .A0(n3946), .A1(cordic_result[17]), .B0(n3952), .B1(n2312), .C0(n3943), .C1(FPSENCOS_d_ff_Xn[17]), .Y(n3942) );
AOI222X1TS U2262 ( .A0(n3946), .A1(cordic_result[14]), .B0(n3952), .B1(n2310), .C0(n3943), .C1(FPSENCOS_d_ff_Xn[14]), .Y(n3940) );
AOI222X1TS U2263 ( .A0(n3946), .A1(cordic_result[15]), .B0(n3952), .B1(
FPSENCOS_d_ff_Yn[15]), .C0(n3943), .C1(FPSENCOS_d_ff_Xn[15]), .Y(n3939) );
AOI222X1TS U2264 ( .A0(n3946), .A1(cordic_result[16]), .B0(n3952), .B1(
FPSENCOS_d_ff_Yn[16]), .C0(n3943), .C1(FPSENCOS_d_ff_Xn[16]), .Y(n3938) );
AOI222X1TS U2265 ( .A0(n3946), .A1(cordic_result[13]), .B0(n3952), .B1(n2311), .C0(n3943), .C1(FPSENCOS_d_ff_Xn[13]), .Y(n3936) );
AOI222X1TS U2266 ( .A0(n3946), .A1(cordic_result[19]), .B0(n3952), .B1(n2314), .C0(n3943), .C1(FPSENCOS_d_ff_Xn[19]), .Y(n3935) );
AOI222X1TS U2267 ( .A0(n3946), .A1(cordic_result[18]), .B0(n3952), .B1(
FPSENCOS_d_ff_Yn[18]), .C0(n3943), .C1(FPSENCOS_d_ff_Xn[18]), .Y(n3934) );
AOI211X1TS U2268 ( .A0(n4394), .A1(FPADDSUB_Data_array_SWR[0]), .B0(n4285),
.C0(n4284), .Y(n4286) );
ADDHXLTS U2269 ( .A(n4604), .B(n4603), .CO(n4525), .S(n4605) );
BUFX4TS U2270 ( .A(n4154), .Y(n4830) );
NOR2XLTS U2271 ( .A(n2374), .B(n3353), .Y(n3354) );
NAND2X1TS U2272 ( .A(FPMULT_Sgf_normalized_result[21]), .B(n4985), .Y(n4986)
);
CMPR32X2TS U2273 ( .A(DP_OP_501J224_127_5235_n114), .B(
DP_OP_501J224_127_5235_n118), .C(n3008), .CO(n3057), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N11) );
AND2X2TS U2274 ( .A(n4543), .B(n4546), .Y(n3901) );
NAND2X4TS U2275 ( .A(FPADDSUB_Shift_reg_FLAGS_7_6), .B(n3513), .Y(n3814) );
NAND2X1TS U2276 ( .A(n4547), .B(n3404), .Y(n4543) );
NAND2X1TS U2277 ( .A(operation[1]), .B(n4728), .Y(n4735) );
NAND2X1TS U2278 ( .A(operation[2]), .B(n4717), .Y(n4732) );
CMPR32X2TS U2279 ( .A(DP_OP_501J224_127_5235_n133), .B(
DP_OP_501J224_127_5235_n142), .C(n2446), .CO(n2956), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N8) );
NAND2X1TS U2280 ( .A(n2367), .B(n4975), .Y(n4979) );
NAND2BX2TS U2281 ( .AN(n4105), .B(operation[1]), .Y(n4145) );
NAND2X1TS U2282 ( .A(n4736), .B(n4104), .Y(n4105) );
NAND2X1TS U2283 ( .A(n2360), .B(n4973), .Y(n4976) );
OAI2BB2X1TS U2284 ( .B0(n4716), .B1(n4275), .A0N(operation[1]), .A1N(n4714),
.Y(n4736) );
NAND2X1TS U2285 ( .A(DP_OP_499J224_125_1651_n41), .B(n3236), .Y(n3243) );
CLKINVX6TS U2286 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n5034) );
NAND2X1TS U2287 ( .A(n2366), .B(n4967), .Y(n4970) );
NAND3BX1TS U2288 ( .AN(n3393), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]),
.C(n3392), .Y(n4725) );
INVX2TS U2289 ( .A(n2974), .Y(n3061) );
INVX2TS U2290 ( .A(operation[2]), .Y(n4728) );
ADDHXLTS U2291 ( .A(n2980), .B(n2979), .CO(n2966), .S(n2981) );
ADDHXLTS U2292 ( .A(n3010), .B(n3009), .CO(n2974), .S(n3011) );
NAND2X1TS U2293 ( .A(FPMULT_Sgf_normalized_result[11]), .B(n4965), .Y(n4968)
);
NOR2X1TS U2294 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[15]), .B(
n2782), .Y(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[16])
);
CMPR32X4TS U2295 ( .A(FPMULT_Op_MX[5]), .B(FPMULT_Op_MX[17]), .C(n2653),
.CO(n2687), .S(n2986) );
CMPR32X2TS U2296 ( .A(n2973), .B(n2972), .C(n2971), .CO(n2975), .S(n2970) );
NAND2X1TS U2297 ( .A(FPMULT_Sgf_normalized_result[9]), .B(n4960), .Y(n4962)
);
CMPR32X2TS U2298 ( .A(n4906), .B(n4902), .C(n3084), .CO(n3120), .S(n3085) );
CMPR32X4TS U2299 ( .A(n4907), .B(FPMULT_Op_MX[15]), .C(n2433), .CO(n2443),
.S(n2651) );
CMPR32X2TS U2300 ( .A(FPMULT_Op_MY[14]), .B(n4930), .C(n2825), .CO(n2827),
.S(n2875) );
ADDHXLTS U2301 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .B(n3201),
.CO(n3204), .S(n3300) );
CMPR32X2TS U2302 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MX[20]), .C(n2823),
.CO(n2814), .S(n2826) );
CMPR32X2TS U2303 ( .A(n4921), .B(n4924), .C(n3089), .CO(n3091), .S(n3102) );
CMPR32X2TS U2304 ( .A(n4902), .B(FPMULT_Op_MX[22]), .C(n2444), .CO(n2938),
.S(n2926) );
CMPR32X4TS U2305 ( .A(FPMULT_Op_MX[1]), .B(FPMULT_Op_MX[13]), .C(n2418),
.CO(n2416), .S(n2650) );
CMPR32X2TS U2306 ( .A(n2196), .B(DP_OP_501J224_127_5235_n411), .C(n2432),
.CO(n2444), .S(n2921) );
CMPR32X2TS U2307 ( .A(n2812), .B(n2811), .C(n2810), .CO(n2786), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[10]) );
CMPR32X2TS U2308 ( .A(n2615), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[12]), .C(
n2614), .CO(n2613), .S(n3208) );
CMPR32X2TS U2309 ( .A(n4923), .B(n4930), .C(n2427), .CO(n2438), .S(n2923) );
CMPR32X2TS U2310 ( .A(n4924), .B(FPMULT_Op_MY[19]), .C(n2424), .CO(n2427),
.S(n2920) );
CMPR32X2TS U2311 ( .A(n2809), .B(n2808), .C(n2807), .CO(n2783), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[8]) );
CMPR32X2TS U2312 ( .A(n2800), .B(n2799), .C(n2798), .CO(n2807), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[7]) );
CMPR32X2TS U2313 ( .A(n2797), .B(n2796), .C(n2795), .CO(n2798), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[6]) );
CMPR32X2TS U2314 ( .A(FPMULT_Op_MY[4]), .B(FPMULT_Op_MY[16]), .C(n2657),
.CO(n2664), .S(n2972) );
CMPR32X2TS U2315 ( .A(n2794), .B(n2793), .C(n2792), .CO(n2795), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[5]) );
CMPR32X2TS U2316 ( .A(n2791), .B(n2790), .C(n2789), .CO(n2792), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[4]) );
CMPR32X2TS U2317 ( .A(n2571), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[7]), .C(n2570),
.CO(n2569), .S(n4576) );
CMPR32X2TS U2318 ( .A(n2803), .B(n2802), .C(n2801), .CO(n2789), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[3]) );
CMPR32X2TS U2319 ( .A(n3229), .B(n3228), .C(n3227), .CO(
DP_OP_499J224_125_1651_n88), .S(n3277) );
CMPR32X2TS U2320 ( .A(n2766), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[3]), .C(
n2765), .CO(n2790), .S(n2803) );
CMPR32X2TS U2321 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[6]), .B(n3234), .C(n3233), .CO(n3228), .S(n3279) );
CMPR32X2TS U2322 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[5]), .B(n2606), .C(n2464), .CO(n3234), .S(n3282) );
CMPR32X2TS U2323 ( .A(n2768), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[2]), .C(
n2767), .CO(n2802), .S(n2806) );
INVX2TS U2324 ( .A(FPMULT_Op_MY[1]), .Y(n4416) );
NOR2X2TS U2325 ( .A(n4055), .B(n4056), .Y(n4054) );
CMPR32X2TS U2326 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[4]), .B(n2608), .C(n2462), .CO(n3283), .S(n3285) );
CMPR32X2TS U2327 ( .A(n2610), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[3]), .C(n3235), .CO(n2638), .S(n2642) );
CMPR32X2TS U2328 ( .A(n2770), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[0]), .C(
n2769), .CO(n2776), .S(n3195) );
CMPR32X2TS U2329 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[3]), .B(n3235), .C(n2460), .CO(n3286), .S(n3288) );
CMPR32X2TS U2330 ( .A(n2581), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[2]), .C(n2580),
.CO(n2578), .S(n4590) );
CMPR32X2TS U2331 ( .A(n2612), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[2]), .C(n2611), .CO(n2641), .S(n2645) );
AOI21X1TS U2332 ( .A0(n2515), .A1(n2389), .B0(n2486), .Y(n2512) );
CMPR32X2TS U2333 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[2]), .B(n2611), .C(n2454), .CO(n3289), .S(n3291) );
CMPR32X2TS U2334 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[11]), .B(
n2497), .C(n2496), .CO(n2498), .S(n2494) );
AOI2BB2X1TS U2335 ( .B0(n5055), .B1(n5057), .A0N(n5239), .A1N(
FPADDSUB_DMP_SFG[6]), .Y(n3959) );
OAI22X1TS U2336 ( .A0(FPADDSUB_DMP_SFG[5]), .A1(n5182), .B0(n3315), .B1(
n5051), .Y(n5057) );
CMPR32X2TS U2337 ( .A(n2585), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[0]), .C(n2584),
.CO(n2582), .S(n4594) );
CMPR32X2TS U2338 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[9]), .B(
n2488), .C(n2487), .CO(n2489), .S(n2485) );
CMPR32X2TS U2339 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[10]), .B(
n2492), .C(n2491), .CO(n2493), .S(n2490) );
CMPR32X2TS U2340 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[8]), .B(
n2483), .C(n2482), .CO(n2484), .S(n2481) );
CMPR32X2TS U2341 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[7]), .B(
n2479), .C(n2478), .CO(n2480), .S(n2475) );
CMPR32X2TS U2342 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[6]), .B(
n2467), .C(n2466), .CO(n2474), .S(n2472) );
CMPR32X2TS U2343 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[5]), .B(
n2465), .C(n2464), .CO(n2473), .S(n2471) );
INVX2TS U2344 ( .A(n2548), .Y(n2557) );
NAND2X1TS U2345 ( .A(n2556), .B(n2555), .Y(n2558) );
NOR2X2TS U2346 ( .A(n2469), .B(n2468), .Y(n2543) );
NAND2X1TS U2347 ( .A(n2457), .B(n2456), .Y(n2550) );
CMPR32X2TS U2348 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[4]), .B(
n2463), .C(n2462), .CO(n2470), .S(n2469) );
NAND2X1TS U2349 ( .A(n2563), .B(n2562), .Y(n2565) );
NAND2X2TS U2350 ( .A(n2455), .B(n2454), .Y(n2555) );
INVX2TS U2351 ( .A(FPMULT_Sgf_operation_Result[0]), .Y(n3295) );
OR2X2TS U2352 ( .A(n2449), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[1]), .Y(
n2447) );
OAI21XLTS U2353 ( .A0(n2533), .A1(n2525), .B0(n2526), .Y(n2476) );
NOR2XLTS U2354 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[0]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(n3400) );
NAND2X1TS U2355 ( .A(n2485), .B(n2484), .Y(n2513) );
OR2X1TS U2356 ( .A(n2494), .B(n2493), .Y(n2390) );
NOR2X2TS U2357 ( .A(n2457), .B(n2456), .Y(n2549) );
OR2X2TS U2358 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[0]), .B(
n2450), .Y(n2393) );
NAND2X1TS U2359 ( .A(n2469), .B(n2468), .Y(n2544) );
OR2X1TS U2360 ( .A(DP_OP_499J224_125_1651_n41), .B(n3236), .Y(n2379) );
INVX2TS U2361 ( .A(n2537), .Y(n2547) );
NOR2XLTS U2362 ( .A(n2289), .B(n2223), .Y(n2372) );
NOR2XLTS U2363 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .Y(n3363) );
AOI21X2TS U2364 ( .A0(FPADDSUB_DMP_SFG[9]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[11]), .B0(n4054), .Y(n4121) );
NOR2XLTS U2365 ( .A(n3055), .B(n3073), .Y(DP_OP_501J224_127_5235_n202) );
NOR2XLTS U2366 ( .A(n3061), .B(n3013), .Y(n2992) );
NOR2XLTS U2367 ( .A(n3014), .B(n3012), .Y(n3070) );
OAI21X1TS U2368 ( .A0(n2557), .A1(n2554), .B0(n2555), .Y(n2553) );
NOR2XLTS U2369 ( .A(DP_OP_499J224_125_1651_n130), .B(n3353), .Y(n3304) );
NAND2X1TS U2370 ( .A(n3321), .B(n3317), .Y(n3328) );
NOR2XLTS U2371 ( .A(n2374), .B(n4607), .Y(n4610) );
NOR2XLTS U2372 ( .A(n3150), .B(n2362), .Y(n3097) );
OAI21XLTS U2373 ( .A0(n4454), .A1(n4452), .B0(n4451), .Y(n4432) );
NOR2XLTS U2374 ( .A(n3024), .B(n3016), .Y(DP_OP_501J224_127_5235_n200) );
NOR2XLTS U2375 ( .A(n2900), .B(n2880), .Y(n2842) );
XOR2X1TS U2376 ( .A(n3242), .B(n3241), .Y(n4613) );
NAND2X1TS U2377 ( .A(FPMULT_Sgf_normalized_result[19]), .B(n4978), .Y(n4981)
);
INVX2TS U2378 ( .A(n4732), .Y(n4888) );
INVX2TS U2379 ( .A(n4724), .Y(n3639) );
OAI211XLTS U2380 ( .A0(n3331), .A1(n3329), .B0(n3190), .C0(n4355), .Y(n3335)
);
INVX2TS U2381 ( .A(operation[1]), .Y(n4717) );
AND3X1TS U2382 ( .A(FPADDSUB_DmP_mant_SFG_SWR[2]), .B(FPADDSUB_DMP_SFG[0]),
.C(n3189), .Y(n3318) );
OAI21XLTS U2383 ( .A0(n3908), .A1(n5140), .B0(n3901), .Y(n3757) );
NOR2XLTS U2384 ( .A(n3039), .B(n3038), .Y(n3043) );
NOR2XLTS U2385 ( .A(n3026), .B(n2946), .Y(n2936) );
NOR2XLTS U2386 ( .A(n3024), .B(n3073), .Y(n3030) );
INVX1TS U2387 ( .A(FPMULT_Sgf_normalized_result[4]), .Y(n4949) );
INVX1TS U2388 ( .A(FPMULT_Sgf_normalized_result[14]), .Y(n4971) );
NAND2X2TS U2389 ( .A(n4717), .B(n4728), .Y(n4149) );
OAI211XLTS U2390 ( .A0(n4086), .A1(n4021), .B0(n4039), .C0(n4038), .Y(n1791)
);
OAI211XLTS U2391 ( .A0(n2219), .A1(n4143), .B0(n4142), .C0(n4141), .Y(n1794)
);
OAI211XLTS U2392 ( .A0(n2296), .A1(n5425), .B0(n4161), .C0(n4160), .Y(n1837)
);
OAI211XLTS U2393 ( .A0(n4021), .A1(n4037), .B0(n4030), .C0(n4029), .Y(n1793)
);
OAI211XLTS U2394 ( .A0(n4021), .A1(n4137), .B0(n4063), .C0(n4062), .Y(n1800)
);
OAI2BB2XLTS U2395 ( .B0(n5041), .B1(n5078), .A0N(n5232), .A1N(
FPADDSUB_ADD_OVRFLW_NRM), .Y(n1351) );
OAI21XLTS U2396 ( .A0(n3995), .A1(n3582), .B0(n3994), .Y(n1339) );
OAI211XLTS U2397 ( .A0(n2296), .A1(n4785), .B0(n4159), .C0(n4158), .Y(n1820)
);
OAI21XLTS U2398 ( .A0(n5093), .A1(n5165), .B0(n4363), .Y(n1316) );
OAI21XLTS U2399 ( .A0(n5023), .A1(n5200), .B0(n3912), .Y(n1387) );
OAI211XLTS U2400 ( .A0(n4021), .A1(n4078), .B0(n4043), .C0(n4042), .Y(n1804)
);
OAI21XLTS U2401 ( .A0(n2280), .A1(n5300), .B0(n3731), .Y(n1408) );
OAI21XLTS U2402 ( .A0(n5023), .A1(n5308), .B0(n3909), .Y(n1369) );
OAI211XLTS U2403 ( .A0(n4131), .A1(n2219), .B0(n4130), .C0(n4129), .Y(n1807)
);
OAI21XLTS U2404 ( .A0(n5221), .A1(n3771), .B0(n3765), .Y(n1221) );
OAI21XLTS U2405 ( .A0(n5222), .A1(n3771), .B0(n3763), .Y(n1241) );
OAI21XLTS U2406 ( .A0(n5219), .A1(n3966), .B0(n3782), .Y(n1282) );
OAI21XLTS U2407 ( .A0(n5326), .A1(n3976), .B0(n3968), .Y(n1371) );
OAI21XLTS U2408 ( .A0(n4109), .A1(n4987), .B0(n4108), .Y(n1607) );
OAI211XLTS U2409 ( .A0(n4086), .A1(n4071), .B0(n4085), .C0(n4084), .Y(n1792)
);
OAI211XLTS U2410 ( .A0(n4281), .A1(n4071), .B0(n4115), .C0(n4114), .Y(n1788)
);
CLKMX2X2TS U2411 ( .A(n4605), .B(FPMULT_P_Sgf[46]), .S0(n4639), .Y(n1575) );
XOR2X1TS U2412 ( .A(n4525), .B(n4524), .Y(n4526) );
XOR2X1TS U2413 ( .A(FPADDSUB_DmP_mant_SFG_SWR[25]), .B(n5008), .Y(n5009) );
AOI22X1TS U2414 ( .A0(FPADDSUB_OP_FLAG_SFG), .A1(n5007), .B0(n5040), .B1(
n5286), .Y(n5008) );
NOR2X1TS U2415 ( .A(n4608), .B(n3356), .Y(n3357) );
NOR2X1TS U2416 ( .A(n4608), .B(n3359), .Y(n3361) );
AOI21X2TS U2417 ( .A0(FPADDSUB_DMP_SFG[20]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[22]), .B0(n5079), .Y(n4360) );
AOI21X2TS U2418 ( .A0(FPADDSUB_DMP_SFG[19]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[21]), .B0(n4358), .Y(n5080) );
AOI21X2TS U2419 ( .A0(FPADDSUB_DMP_SFG[18]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[20]), .B0(n3330), .Y(n3332) );
OAI22X2TS U2420 ( .A0(FPADDSUB_DMP_SFG[20]), .A1(n5204), .B0(n4356), .B1(
n5083), .Y(n4357) );
AFHCINX2TS U2421 ( .CIN(n4632), .B(n4633), .A(n4634), .S(n4635), .CO(n4628)
);
CLKMX2X2TS U2422 ( .A(n4647), .B(FPMULT_P_Sgf[29]), .S0(n4650), .Y(n1558) );
AO21X1TS U2423 ( .A0(n3343), .A1(n4600), .B0(n3603), .Y(n1557) );
CLKMX2X2TS U2424 ( .A(n4651), .B(FPMULT_P_Sgf[27]), .S0(n4650), .Y(n1556) );
AO21X1TS U2425 ( .A0(n3340), .A1(n3641), .B0(n3632), .Y(n1555) );
OR2X4TS U2426 ( .A(n4338), .B(n3319), .Y(n5070) );
NOR2X2TS U2427 ( .A(n4346), .B(n4345), .Y(n4344) );
AOI211X1TS U2428 ( .A0(n4321), .A1(n4320), .B0(n4319), .C0(n2289), .Y(n4322)
);
NOR2X2TS U2429 ( .A(n4337), .B(n4336), .Y(n4335) );
INVX2TS U2430 ( .A(n4568), .Y(DP_OP_499J224_125_1651_n107) );
ADDHX2TS U2431 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]), .B(n2569),
.CO(n2568), .S(n4568) );
XOR2X1TS U2432 ( .A(n3202), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]), .Y(n4524)
);
NOR2X2TS U2433 ( .A(n4205), .B(n4204), .Y(n4203) );
OR2X2TS U2434 ( .A(n3387), .B(intadd_522_n1), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11) );
NOR2X2TS U2435 ( .A(n4118), .B(n4117), .Y(n4116) );
OAI21X1TS U2436 ( .A0(n3908), .A1(n5145), .B0(n3901), .Y(n3744) );
OAI21X1TS U2437 ( .A0(n3908), .A1(n5142), .B0(n3901), .Y(n3736) );
OAI21X1TS U2438 ( .A0(n3908), .A1(n5141), .B0(n3901), .Y(n3753) );
OAI21X1TS U2439 ( .A0(n3929), .A1(n5124), .B0(n3901), .Y(n3761) );
OAI21X1TS U2440 ( .A0(n3908), .A1(n5143), .B0(n3901), .Y(n3747) );
OAI21X1TS U2441 ( .A0(n3908), .A1(n5139), .B0(n3901), .Y(n3739) );
OAI21X1TS U2442 ( .A0(n3908), .A1(n5146), .B0(n3901), .Y(n3731) );
NOR2X2TS U2443 ( .A(n4053), .B(n4052), .Y(n4051) );
OAI21X1TS U2444 ( .A0(n5327), .A1(n3976), .B0(n3967), .Y(n1374) );
OAI21X1TS U2445 ( .A0(n5321), .A1(n3976), .B0(n3975), .Y(n1377) );
OAI21X1TS U2446 ( .A0(n5322), .A1(n3976), .B0(n3969), .Y(n1380) );
OAI21X1TS U2447 ( .A0(n2727), .A1(n2725), .B0(n2726), .Y(n2724) );
OAI21X1TS U2448 ( .A0(n3161), .A1(n3136), .B0(n3132), .Y(n3131) );
AND2X2TS U2449 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[7]), .B(n3728), .Y(n3730) );
OAI21X1TS U2450 ( .A0(FPADDSUB_ADD_OVRFLW_NRM), .A1(n4535), .B0(n4395), .Y(
n2077) );
OAI21X1TS U2451 ( .A0(n3892), .A1(n3891), .B0(n3890), .Y(mult_x_310_n22) );
OAI21X1TS U2452 ( .A0(n3853), .A1(n3852), .B0(n3851), .Y(mult_x_311_n22) );
OAI21X1TS U2453 ( .A0(n2520), .A1(n2516), .B0(n2517), .Y(n2515) );
ADDFX2TS U2454 ( .A(FPMULT_Op_MX[7]), .B(n2197), .CI(n2417), .CO(n2419), .S(
n2924) );
OAI21XLTS U2455 ( .A0(n2856), .A1(n2884), .B0(n2873), .Y(n2859) );
BUFX3TS U2456 ( .A(n3774), .Y(n3945) );
NAND4BX1TS U2457 ( .AN(FPADDSUB_exp_rslt_NRM2_EW1[4]), .B(n3400), .C(n3399),
.D(n3398), .Y(n3401) );
XNOR2X1TS U2458 ( .A(n2547), .B(n2546), .Y(n2589) );
XNOR2X1TS U2459 ( .A(n2542), .B(n2541), .Y(n2587) );
INVX4TS U2460 ( .A(n2651), .Y(n2718) );
NOR2X6TS U2461 ( .A(operation[1]), .B(n4105), .Y(n4304) );
OAI21X1TS U2462 ( .A0(n2537), .A1(n2543), .B0(n2544), .Y(n2542) );
INVX4TS U2463 ( .A(n2897), .Y(n2884) );
NOR2X6TS U2464 ( .A(n3561), .B(n3366), .Y(n3604) );
NOR2X2TS U2465 ( .A(n3659), .B(n3661), .Y(n3658) );
NAND2BX1TS U2466 ( .AN(n4688), .B(n4689), .Y(mult_x_312_n19) );
AOI211X1TS U2467 ( .A0(n3585), .A1(n3584), .B0(n3583), .C0(n2289), .Y(n3586)
);
OAI21X1TS U2468 ( .A0(n2549), .A1(n2555), .B0(n2550), .Y(n2458) );
OAI21X2TS U2469 ( .A0(n2561), .A1(n2564), .B0(n2562), .Y(n2548) );
NAND3XLTS U2470 ( .A(FPSENCOS_cont_iter_out[2]), .B(n4761), .C(n4745), .Y(
n4747) );
CLKINVX3TS U2471 ( .A(n3366), .Y(n2199) );
BUFX3TS U2472 ( .A(n2201), .Y(n4419) );
NAND3X2TS U2473 ( .A(n4921), .B(n4906), .C(n4493), .Y(n4488) );
CLKINVX3TS U2474 ( .A(n2201), .Y(n4420) );
CLKINVX3TS U2475 ( .A(n2201), .Y(n4529) );
INVX4TS U2476 ( .A(n3396), .Y(n4994) );
CLKBUFX2TS U2477 ( .A(n5078), .Y(n2289) );
NOR2X6TS U2478 ( .A(n3298), .B(n3297), .Y(n3561) );
NAND2X4TS U2479 ( .A(n4720), .B(n4723), .Y(n4769) );
NOR2X4TS U2480 ( .A(n2455), .B(n2454), .Y(n2554) );
OR2X2TS U2481 ( .A(n2485), .B(n2484), .Y(n2389) );
INVX4TS U2482 ( .A(n4415), .Y(n4906) );
INVX4TS U2483 ( .A(n4416), .Y(n4921) );
INVX4TS U2484 ( .A(n2431), .Y(n4902) );
XNOR2X2TS U2485 ( .A(n2449), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[1]), .Y(
n2453) );
INVX2TS U2486 ( .A(n3532), .Y(n4894) );
INVX4TS U2487 ( .A(n4446), .Y(n4924) );
OAI21X1TS U2488 ( .A0(FPADDSUB_DMP_SFG[22]), .A1(n5351), .B0(n5086), .Y(
n5090) );
NOR2X1TS U2489 ( .A(FPADDSUB_DMP_SFG[1]), .B(n5235), .Y(n3312) );
INVX2TS U2490 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[2]), .Y(n2448)
);
NAND4X1TS U2491 ( .A(n2218), .B(n5250), .C(n5165), .D(n5187), .Y(n4391) );
CLKBUFX2TS U2492 ( .A(n5154), .Y(n2299) );
INVX4TS U2493 ( .A(n2378), .Y(n4901) );
NAND2BX1TS U2494 ( .AN(FPADDSUB_intDX_EWSW[13]), .B(FPADDSUB_intDY_EWSW[13]),
.Y(n3437) );
CLKMX2X2TS U2495 ( .A(n4526), .B(FPMULT_P_Sgf[47]), .S0(n3561), .Y(n1694) );
AO21X1TS U2496 ( .A0(n3346), .A1(n4600), .B0(n3613), .Y(n1568) );
AO21X1TS U2497 ( .A0(n3352), .A1(n4600), .B0(n3616), .Y(n1570) );
AO21X1TS U2498 ( .A0(n3355), .A1(n4600), .B0(n3610), .Y(n1573) );
AO21X1TS U2499 ( .A0(n3306), .A1(n4600), .B0(n3625), .Y(n1574) );
AO21X1TS U2500 ( .A0(n3299), .A1(n3641), .B0(n3619), .Y(n1567) );
NOR2X1TS U2501 ( .A(n2374), .B(n3262), .Y(n3345) );
AO21X1TS U2502 ( .A0(n3358), .A1(n4600), .B0(n3622), .Y(n1571) );
AO21X1TS U2503 ( .A0(n3362), .A1(n4600), .B0(n3607), .Y(n1569) );
NOR2X1TS U2504 ( .A(n2374), .B(n3348), .Y(n3351) );
XOR2X1TS U2505 ( .A(n2374), .B(n3262), .Y(n3299) );
INVX6TS U2506 ( .A(n3305), .Y(n2374) );
NAND2X2TS U2507 ( .A(n3305), .B(n3304), .Y(n4522) );
INVX4TS U2508 ( .A(n4608), .Y(n3305) );
CLKMX2X2TS U2509 ( .A(n4615), .B(n2348), .S0(n4639), .Y(n1566) );
NOR2X2TS U2510 ( .A(n4359), .B(n4360), .Y(n5006) );
CLKMX2X2TS U2511 ( .A(n4619), .B(FPMULT_P_Sgf[36]), .S0(n4650), .Y(n1565) );
CLKMX2X2TS U2512 ( .A(n4623), .B(FPMULT_P_Sgf[35]), .S0(n4650), .Y(n1564) );
CLKMX2X2TS U2513 ( .A(n4627), .B(n2347), .S0(n4650), .Y(n1563) );
NOR2X2TS U2514 ( .A(n5080), .B(n5085), .Y(n5079) );
OAI21X1TS U2515 ( .A0(n4359), .A1(n4357), .B0(n5005), .Y(n4362) );
CLKMX2X2TS U2516 ( .A(n4631), .B(n2346), .S0(n4650), .Y(n1562) );
NAND2X2TS U2517 ( .A(n4359), .B(n4357), .Y(n5005) );
CLKMX2X2TS U2518 ( .A(n4635), .B(FPMULT_P_Sgf[32]), .S0(n4650), .Y(n1561) );
CLKMX2X2TS U2519 ( .A(n4640), .B(n2357), .S0(n4639), .Y(n1560) );
OAI21X1TS U2520 ( .A0(n5085), .A1(n5083), .B0(n3190), .Y(n5082) );
CLKMX2X2TS U2521 ( .A(n4644), .B(FPMULT_P_Sgf[30]), .S0(n4650), .Y(n1559) );
NOR2X2TS U2522 ( .A(n4348), .B(n4349), .Y(n4347) );
OAI211X1TS U2523 ( .A0(n3321), .A1(n3317), .B0(n3190), .C0(n3328), .Y(n3325)
);
OAI21X1TS U2524 ( .A0(n5093), .A1(n5266), .B0(n4333), .Y(n1333) );
AOI21X2TS U2525 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[19]), .A1(n5292), .B0(n4344),
.Y(n3317) );
OAI21X1TS U2526 ( .A0(n5042), .A1(n5207), .B0(n4324), .Y(n1334) );
AOI211X1TS U2527 ( .A0(n4330), .A1(n4329), .B0(n4328), .C0(n5078), .Y(n4331)
);
AOI2BB2X2TS U2528 ( .B0(n5071), .B1(n5072), .A0N(n2299), .A1N(
FPADDSUB_DMP_SFG[16]), .Y(n4346) );
NOR2X4TS U2529 ( .A(n4329), .B(n4330), .Y(n4328) );
AFHCINX2TS U2530 ( .CIN(n4655), .B(n4656), .A(
FPMULT_Sgf_operation_EVEN1_Q_left[0]), .S(n4657), .CO(n4652) );
AOI31X1TS U2531 ( .A0(n4354), .A1(n4986), .A2(n4987), .B0(n4353), .Y(n1598)
);
AO22X1TS U2532 ( .A0(n4992), .A1(FPMULT_Sgf_normalized_result[23]), .B0(
FPMULT_FSM_add_overflow_flag), .B1(n4990), .Y(n1596) );
XOR2X2TS U2533 ( .A(n2566), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]), .Y(n4660) );
AO22X1TS U2534 ( .A0(n4418), .A1(FPMULT_Add_result[20]), .B0(n4984), .B1(
n4983), .Y(n1600) );
NOR2X2TS U2535 ( .A(n5063), .B(n5069), .Y(n5062) );
AOI211X1TS U2536 ( .A0(n4208), .A1(n4207), .B0(n4206), .C0(n5078), .Y(n4209)
);
OAI21X1TS U2537 ( .A0(n5364), .A1(n4987), .B0(n4334), .Y(n1601) );
NOR2X1TS U2538 ( .A(FPMULT_Sgf_normalized_result[21]), .B(n4985), .Y(n4989)
);
OR2X2TS U2539 ( .A(n3239), .B(n3238), .Y(n2380) );
ADDHX2TS U2540 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]), .B(n2568),
.CO(n2567), .S(n4580) );
NOR2X1TS U2541 ( .A(n3061), .B(n3012), .Y(n2989) );
NOR2X1TS U2542 ( .A(n3060), .B(n3055), .Y(n3059) );
NOR2X1TS U2543 ( .A(n3055), .B(n3071), .Y(DP_OP_501J224_127_5235_n210) );
OAI211X1TS U2544 ( .A0(FPMULT_Sgf_normalized_result[19]), .A1(n4978), .B0(
n4991), .C0(n4981), .Y(n4334) );
NOR2X4TS U2545 ( .A(n4207), .B(n4208), .Y(n4206) );
AO22X1TS U2546 ( .A0(n4990), .A1(FPMULT_Add_result[18]), .B0(n4984), .B1(
n4980), .Y(n1602) );
NOR2X1TS U2547 ( .A(n3060), .B(n3074), .Y(n2984) );
NOR2X1TS U2548 ( .A(n3024), .B(n3056), .Y(DP_OP_501J224_127_5235_n192) );
NOR2X1TS U2549 ( .A(n3015), .B(n3056), .Y(n2982) );
OAI21X1TS U2550 ( .A0(n5365), .A1(n4987), .B0(n4325), .Y(n1603) );
NOR2X1TS U2551 ( .A(n3015), .B(n3013), .Y(DP_OP_501J224_127_5235_n227) );
NOR2X1TS U2552 ( .A(n3015), .B(n3073), .Y(n2990) );
NOR2X1TS U2553 ( .A(n3074), .B(n3056), .Y(DP_OP_501J224_127_5235_n188) );
AOI211X1TS U2554 ( .A0(n4121), .A1(n4120), .B0(n4119), .C0(n3188), .Y(n4122)
);
NOR2X1TS U2555 ( .A(n3060), .B(n3024), .Y(DP_OP_501J224_127_5235_n184) );
NOR2X1TS U2556 ( .A(n3015), .B(n3071), .Y(n2993) );
OAI21X1TS U2557 ( .A0(n4059), .A1(n3582), .B0(n4058), .Y(n1338) );
NOR2X1TS U2558 ( .A(n3015), .B(n3012), .Y(n2997) );
NOR2X1TS U2559 ( .A(n3074), .B(n3073), .Y(n3078) );
NOR2X1TS U2560 ( .A(n3072), .B(n3016), .Y(n2994) );
NOR2X1TS U2561 ( .A(n3074), .B(n3023), .Y(DP_OP_501J224_127_5235_n236) );
NOR2X1TS U2562 ( .A(n3074), .B(n3013), .Y(n3002) );
NOR2X1TS U2563 ( .A(n3074), .B(n3016), .Y(n2991) );
NOR2X4TS U2564 ( .A(n4120), .B(n4121), .Y(n4119) );
NOR2X1TS U2565 ( .A(n3014), .B(n3016), .Y(n2995) );
OAI21X1TS U2566 ( .A0(n3536), .A1(n5229), .B0(n4070), .Y(n1811) );
OAI211X1TS U2567 ( .A0(n4071), .A1(n4137), .B0(n4093), .C0(n4092), .Y(n1801)
);
OAI211X1TS U2568 ( .A0(n4071), .A1(n4083), .B0(n4082), .C0(n4081), .Y(n1803)
);
OAI211X1TS U2569 ( .A0(n4283), .A1(n4071), .B0(n4089), .C0(n4088), .Y(n1790)
);
OAI211X1TS U2570 ( .A0(n4131), .A1(n2220), .B0(n4096), .C0(n4095), .Y(n1808)
);
OAI211X1TS U2571 ( .A0(n2220), .A1(n4143), .B0(n4103), .C0(n4102), .Y(n1795)
);
OAI21X1TS U2572 ( .A0(n4131), .A1(n4071), .B0(n4075), .Y(n1810) );
OAI211X1TS U2573 ( .A0(n4071), .A1(n4143), .B0(n4098), .C0(n4097), .Y(n1797)
);
OAI211X1TS U2574 ( .A0(n2220), .A1(n4137), .B0(n4101), .C0(n4100), .Y(n1799)
);
OAI21X1TS U2575 ( .A0(n5023), .A1(n5304), .B0(n3902), .Y(n1393) );
OAI211X1TS U2576 ( .A0(n2219), .A1(n4137), .B0(n4136), .C0(n4135), .Y(n1798)
);
OAI211X1TS U2577 ( .A0(n4071), .A1(n4078), .B0(n4077), .C0(n4076), .Y(n1805)
);
AOI211X1TS U2578 ( .A0(n4056), .A1(n4055), .B0(n4054), .C0(n3188), .Y(n4057)
);
NOR2X1TS U2579 ( .A(n3072), .B(n3073), .Y(n3075) );
OAI21X1TS U2580 ( .A0(n5023), .A1(n5203), .B0(n3930), .Y(n1292) );
OAI21X1TS U2581 ( .A0(n5023), .A1(n5309), .B0(n3914), .Y(n1306) );
OAI21X1TS U2582 ( .A0(n5023), .A1(n5310), .B0(n3920), .Y(n1299) );
OAI21X1TS U2583 ( .A0(n5023), .A1(n5202), .B0(n3923), .Y(n1313) );
OAI21X1TS U2584 ( .A0(n5023), .A1(n5311), .B0(n3926), .Y(n1278) );
OAI21X1TS U2585 ( .A0(n5023), .A1(n5201), .B0(n3917), .Y(n1329) );
OAI211X1TS U2586 ( .A0(n4283), .A1(n4021), .B0(n4046), .C0(n4045), .Y(n1789)
);
OAI211X1TS U2587 ( .A0(n4021), .A1(n4083), .B0(n4061), .C0(n4060), .Y(n1802)
);
OAI21X1TS U2588 ( .A0(n3908), .A1(n5144), .B0(n5016), .Y(n3902) );
OAI21X1TS U2589 ( .A0(n5023), .A1(n5303), .B0(n3747), .Y(n1396) );
OAI21X1TS U2590 ( .A0(n5515), .A1(n5302), .B0(n3736), .Y(n1402) );
OAI21X1TS U2591 ( .A0(n5023), .A1(n5305), .B0(n3753), .Y(n1390) );
OAI21X1TS U2592 ( .A0(n5023), .A1(n5306), .B0(n3761), .Y(n1384) );
OAI21X1TS U2593 ( .A0(n5023), .A1(n5307), .B0(n3757), .Y(n1378) );
OAI21X1TS U2594 ( .A0(n5515), .A1(n5301), .B0(n3739), .Y(n1405) );
OAI21X1TS U2595 ( .A0(n3908), .A1(n5138), .B0(n5016), .Y(n3909) );
OAI21X1TS U2596 ( .A0(n3929), .A1(n5125), .B0(n5016), .Y(n3914) );
OAI21X1TS U2597 ( .A0(n3929), .A1(n5117), .B0(n5016), .Y(n3920) );
NOR2X1TS U2598 ( .A(n3072), .B(n3012), .Y(n2999) );
OAI21X1TS U2599 ( .A0(n5515), .A1(n5199), .B0(n3744), .Y(n1399) );
OAI211X1TS U2600 ( .A0(n4021), .A1(n4041), .B0(n4035), .C0(n4034), .Y(n1806)
);
NOR2X1TS U2601 ( .A(n2289), .B(n2224), .Y(n2373) );
OAI21X1TS U2602 ( .A0(n3929), .A1(n5123), .B0(n5016), .Y(n3926) );
OAI211X1TS U2603 ( .A0(n4021), .A1(n4143), .B0(n4067), .C0(n4066), .Y(n1796)
);
OAI21X1TS U2604 ( .A0(n3929), .A1(n5122), .B0(n5016), .Y(n3912) );
OAI21X1TS U2605 ( .A0(n3929), .A1(n5121), .B0(n5016), .Y(n3917) );
OAI21X1TS U2606 ( .A0(n3929), .A1(n5119), .B0(n5016), .Y(n3923) );
OAI211X1TS U2607 ( .A0(n4131), .A1(n4021), .B0(n4050), .C0(n4049), .Y(n1809)
);
NOR2X1TS U2608 ( .A(n3072), .B(n3023), .Y(n3005) );
NOR2X1TS U2609 ( .A(n3072), .B(n3071), .Y(n3068) );
OAI21X1TS U2610 ( .A0(n3929), .A1(n5118), .B0(n5016), .Y(n3930) );
NOR2X1TS U2611 ( .A(n3039), .B(n3025), .Y(n2950) );
NOR2X1TS U2612 ( .A(n3021), .B(n3025), .Y(n2952) );
NOR2X1TS U2613 ( .A(n3021), .B(n2946), .Y(n3045) );
NOR2X1TS U2614 ( .A(n3014), .B(n3071), .Y(n2998) );
NOR2X1TS U2615 ( .A(n3014), .B(n3023), .Y(n2436) );
NOR2X1TS U2616 ( .A(n3038), .B(n3080), .Y(n3037) );
NOR2X1TS U2617 ( .A(n3014), .B(n3013), .Y(n3000) );
NOR2X1TS U2618 ( .A(n3039), .B(n3018), .Y(n2944) );
NOR2X1TS U2619 ( .A(n3039), .B(n2946), .Y(n2941) );
NOR2X1TS U2620 ( .A(n3021), .B(n3022), .Y(n3054) );
NOR2X1TS U2621 ( .A(n3080), .B(n2946), .Y(n2943) );
NOR2X1TS U2622 ( .A(n3017), .B(n3013), .Y(n2437) );
NOR2X1TS U2623 ( .A(n3038), .B(n3026), .Y(n2951) );
NOR2X1TS U2624 ( .A(n3019), .B(n3018), .Y(n2947) );
NOR2X1TS U2625 ( .A(n3019), .B(n3022), .Y(n3046) );
NOR2X1TS U2626 ( .A(n3038), .B(n3019), .Y(n2940) );
NOR2X1TS U2627 ( .A(n3038), .B(n3020), .Y(n3053) );
INVX4TS U2628 ( .A(n4021), .Y(n4068) );
NOR2X1TS U2629 ( .A(n3019), .B(n2946), .Y(n3052) );
NOR2X1TS U2630 ( .A(n3026), .B(n3022), .Y(n2954) );
NOR2X1TS U2631 ( .A(n3017), .B(n3023), .Y(n3047) );
NOR2X1TS U2632 ( .A(n3017), .B(n3012), .Y(n3001) );
NOR2X1TS U2633 ( .A(n3079), .B(n3026), .Y(n2932) );
NOR2X1TS U2634 ( .A(n3019), .B(n3025), .Y(n2927) );
NAND3X1TS U2635 ( .A(n4847), .B(n4846), .C(n4845), .Y(n1823) );
NAND3X1TS U2636 ( .A(n4832), .B(n4831), .C(n4845), .Y(n1828) );
NOR2X1TS U2637 ( .A(n3024), .B(n3023), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N0) );
OAI21X1TS U2638 ( .A0(n5316), .A1(n3771), .B0(n3767), .Y(n1209) );
NOR2X1TS U2639 ( .A(n3024), .B(n3013), .Y(n3048) );
OAI21X1TS U2640 ( .A0(n5224), .A1(n3771), .B0(n3766), .Y(n1217) );
NAND3X1TS U2641 ( .A(n4837), .B(n4836), .C(n4845), .Y(n1826) );
OAI21X1TS U2642 ( .A0(n5318), .A1(n3771), .B0(n3768), .Y(n1213) );
OAI21X1TS U2643 ( .A0(n5223), .A1(n3771), .B0(n3764), .Y(n1225) );
OAI21X1TS U2644 ( .A0(n5216), .A1(n3771), .B0(n3770), .Y(n1229) );
OAI21X1TS U2645 ( .A0(n5325), .A1(n3966), .B0(n3783), .Y(n1289) );
OAI21X1TS U2646 ( .A0(n5217), .A1(n3771), .B0(n3769), .Y(n1233) );
OAI21X1TS U2647 ( .A0(n5328), .A1(n3771), .B0(n3762), .Y(n1237) );
OR2X2TS U2648 ( .A(n4025), .B(n4073), .Y(n2219) );
OAI21X1TS U2649 ( .A0(n5218), .A1(n3966), .B0(n3785), .Y(n1275) );
OAI21X1TS U2650 ( .A0(n5220), .A1(n3966), .B0(n3780), .Y(n1269) );
OAI21X1TS U2651 ( .A0(n5320), .A1(n3966), .B0(n3787), .Y(n1265) );
OAI21X1TS U2652 ( .A0(n5317), .A1(n3966), .B0(n3784), .Y(n1261) );
OAI21X1TS U2653 ( .A0(n5322), .A1(n3966), .B0(n3781), .Y(n1245) );
OAI21X1TS U2654 ( .A0(n5326), .A1(n3966), .B0(n3778), .Y(n1257) );
OAI21X1TS U2655 ( .A0(n5327), .A1(n3966), .B0(n3779), .Y(n1253) );
OAI21X1TS U2656 ( .A0(n5321), .A1(n3966), .B0(n3789), .Y(n1249) );
AOI211X1TS U2657 ( .A0(n3962), .A1(n3961), .B0(n3960), .C0(n5078), .Y(n3963)
);
OAI21X1TS U2658 ( .A0(n2504), .A1(n2500), .B0(n2501), .Y(n2499) );
NOR2X1TS U2659 ( .A(n3020), .B(n2946), .Y(n2948) );
NOR2X1TS U2660 ( .A(n3020), .B(n3018), .Y(n2928) );
NOR2X1TS U2661 ( .A(n3020), .B(n3025), .Y(n3049) );
NOR2X2TS U2662 ( .A(n3990), .B(n3989), .Y(n3988) );
NAND3X1TS U2663 ( .A(n4858), .B(n4857), .C(n4856), .Y(n1814) );
NAND3X1TS U2664 ( .A(n4820), .B(n4819), .C(n4821), .Y(n1836) );
NAND3X1TS U2665 ( .A(n4817), .B(n4816), .C(n4827), .Y(n1838) );
NAND3X1TS U2666 ( .A(n4823), .B(n4822), .C(n4821), .Y(n1832) );
OAI211X1TS U2667 ( .A0(n2296), .A1(n5427), .B0(n4157), .C0(n4156), .Y(n1834)
);
NAND3X1TS U2668 ( .A(n4835), .B(n4834), .C(n4833), .Y(n1827) );
NAND3X1TS U2669 ( .A(n4853), .B(n4852), .C(n4856), .Y(n1816) );
OR2X2TS U2670 ( .A(n4027), .B(n4073), .Y(n2220) );
NAND2X4TS U2671 ( .A(n4022), .B(n4027), .Y(n4021) );
NOR2X2TS U2672 ( .A(n3961), .B(n3962), .Y(n3960) );
OR2X4TS U2673 ( .A(n4027), .B(n4861), .Y(n4071) );
NAND3X1TS U2674 ( .A(n4825), .B(n4824), .C(n4838), .Y(n1830) );
NAND3X1TS U2675 ( .A(n4855), .B(n4854), .C(n4856), .Y(n1815) );
NAND3X1TS U2676 ( .A(n4814), .B(n4813), .C(n4833), .Y(n1840) );
NAND3X1TS U2677 ( .A(n4829), .B(n4828), .C(n4827), .Y(n1829) );
NOR2X1TS U2678 ( .A(n3026), .B(n3018), .Y(n3050) );
NOR2X1TS U2679 ( .A(n3026), .B(n3025), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N0) );
NAND3X1TS U2680 ( .A(n4840), .B(n4839), .C(n4838), .Y(n1825) );
OAI211X1TS U2681 ( .A0(n4239), .A1(n5393), .B0(n4213), .C0(n4212), .Y(n1932)
);
NAND3X1TS U2682 ( .A(n4843), .B(n4842), .C(n4848), .Y(n1824) );
OAI211X1TS U2683 ( .A0(n4290), .A1(n5404), .B0(n4221), .C0(n4220), .Y(n1921)
);
NAND3X1TS U2684 ( .A(n4850), .B(n4849), .C(n4848), .Y(n1821) );
OAI211X1TS U2685 ( .A0(n4310), .A1(n5406), .B0(n4181), .C0(n4180), .Y(n1919)
);
BUFX3TS U2686 ( .A(n2296), .Y(n4290) );
OAI32X4TS U2687 ( .A0(n4006), .A1(FPADDSUB_Raw_mant_NRM_SWR[0]), .A2(n5034),
.B0(n4072), .B1(n4006), .Y(n4862) );
OAI22X1TS U2688 ( .A0(n2694), .A1(n2730), .B0(n2688), .B1(n2725), .Y(
mult_x_313_n32) );
OAI211X1TS U2689 ( .A0(n2296), .A1(n5428), .B0(n4147), .C0(n4146), .Y(n1833)
);
BUFX3TS U2690 ( .A(n2296), .Y(n4310) );
AOI21X2TS U2691 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[9]), .A1(n5242), .B0(n3957),
.Y(n3990) );
BUFX3TS U2692 ( .A(n2296), .Y(n4239) );
NOR2X1TS U2693 ( .A(n2709), .B(n2731), .Y(n2667) );
NOR2X2TS U2694 ( .A(n3959), .B(n3958), .Y(n3957) );
OAI21X1TS U2695 ( .A0(n4503), .A1(n2226), .B0(n4501), .Y(n4483) );
INVX3TS U2696 ( .A(n3814), .Y(n3705) );
NOR2X1TS U2697 ( .A(n3401), .B(FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(n3402) );
AOI21X2TS U2698 ( .A0(FPADDSUB_DMP_SFG[4]), .A1(FPADDSUB_DmP_mant_SFG_SWR[6]), .B0(n3666), .Y(n5050) );
AOI211X1TS U2699 ( .A0(n3668), .A1(n3667), .B0(n3666), .C0(n5078), .Y(n3669)
);
OR2X4TS U2700 ( .A(n3513), .B(n5037), .Y(n3981) );
NOR2XLTS U2701 ( .A(n3554), .B(n3553), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2) );
NOR2X1TS U2702 ( .A(n2900), .B(n2891), .Y(n2902) );
NOR2X4TS U2703 ( .A(n4145), .B(n4724), .Y(n4155) );
INVX3TS U2704 ( .A(n2873), .Y(n2876) );
NOR2X1TS U2705 ( .A(n2731), .B(n2703), .Y(n2685) );
INVX3TS U2706 ( .A(n3564), .Y(n3652) );
INVX3TS U2707 ( .A(n3602), .Y(n3633) );
NOR2X4TS U2708 ( .A(n3690), .B(n4882), .Y(n3812) );
NOR2X4TS U2709 ( .A(n3690), .B(n4881), .Y(n3774) );
OR2X2TS U2710 ( .A(n4759), .B(n4781), .Y(n2203) );
NAND3BX1TS U2711 ( .AN(n3382), .B(n3381), .C(n3379), .Y(n3380) );
NAND3X1TS U2712 ( .A(FPMULT_FSM_selector_C), .B(n3578), .C(n3641), .Y(n3602)
);
OAI21XLTS U2713 ( .A0(n3860), .A1(n3859), .B0(n3858), .Y(mult_x_310_n36) );
NAND3BX1TS U2714 ( .AN(n3460), .B(n3458), .C(n3457), .Y(n3478) );
INVX3TS U2715 ( .A(n4783), .Y(n3807) );
AOI22X1TS U2716 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[6]), .A1(n5238), .B0(n3314),
.B1(n3665), .Y(n5051) );
NAND3X1TS U2717 ( .A(n4907), .B(FPMULT_Op_MY[3]), .C(n3878), .Y(n4475) );
AOI31X1TS U2718 ( .A0(n4011), .A1(FPADDSUB_Raw_mant_NRM_SWR[6]), .A2(n5289),
.B0(n4010), .Y(n4020) );
OAI22X2TS U2719 ( .A0(FPADDSUB_DMP_SFG[3]), .A1(n5180), .B0(n3313), .B1(
n3662), .Y(n3665) );
INVX3TS U2720 ( .A(n3561), .Y(n3641) );
NAND3X1TS U2721 ( .A(n4907), .B(n4925), .C(n3863), .Y(n3884) );
NOR2X6TS U2722 ( .A(n3689), .B(n4746), .Y(n3690) );
NAND3X1TS U2723 ( .A(n2196), .B(FPMULT_Op_MY[9]), .C(n3839), .Y(n4424) );
NAND3BX1TS U2724 ( .AN(n3375), .B(n3374), .C(n3372), .Y(n3373) );
NAND3X1TS U2725 ( .A(n2196), .B(n4923), .C(n3824), .Y(n3845) );
NAND3X1TS U2726 ( .A(FPMULT_Op_MX[5]), .B(n4925), .C(n4492), .Y(n4491) );
NAND3X1TS U2727 ( .A(FPMULT_Op_MX[15]), .B(FPMULT_Op_MY[15]), .C(n3385), .Y(
n4366) );
NAND3X1TS U2728 ( .A(n4901), .B(n4923), .C(n4441), .Y(n4440) );
AND3X2TS U2729 ( .A(n4759), .B(n4761), .C(n4745), .Y(n4746) );
OR2X2TS U2730 ( .A(FPMULT_FSM_selector_C), .B(n2302), .Y(n3366) );
CLKBUFX3TS U2731 ( .A(n3806), .Y(n3801) );
NAND3X1TS U2732 ( .A(FPMULT_Op_MX[15]), .B(FPMULT_Op_MY[14]), .C(n3527), .Y(
n4694) );
NAND3X1TS U2733 ( .A(FPMULT_Op_MX[17]), .B(FPMULT_Op_MY[14]), .C(n4690), .Y(
n4689) );
NAND3X1TS U2734 ( .A(FPMULT_Op_MX[22]), .B(FPMULT_Op_MY[19]), .C(n4679), .Y(
n4678) );
OAI21X1TS U2735 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[14]), .A1(n4018), .B0(n4017),
.Y(n4019) );
INVX3TS U2736 ( .A(n3166), .Y(n3153) );
NAND3X1TS U2737 ( .A(DP_OP_501J224_127_5235_n411), .B(FPMULT_Op_MY[21]), .C(
n3413), .Y(n4676) );
INVX4TS U2738 ( .A(n3326), .Y(n4796) );
OAI21XLTS U2739 ( .A0(n4733), .A1(n5227), .B0(n4245), .Y(op_result[31]) );
OAI21XLTS U2740 ( .A0(n4733), .A1(n5310), .B0(n4277), .Y(op_result[0]) );
OAI21XLTS U2741 ( .A0(n4733), .A1(n5203), .B0(n4268), .Y(op_result[1]) );
OAI21XLTS U2742 ( .A0(n4733), .A1(n5202), .B0(n4280), .Y(op_result[2]) );
OAI21XLTS U2743 ( .A0(n4733), .A1(n5299), .B0(n4255), .Y(op_result[9]) );
OAI21XLTS U2744 ( .A0(n4733), .A1(n5297), .B0(n4271), .Y(op_result[10]) );
OAI21XLTS U2745 ( .A0(n4733), .A1(n5295), .B0(n4276), .Y(op_result[8]) );
OAI21XLTS U2746 ( .A0(n4733), .A1(n5296), .B0(n4270), .Y(op_result[11]) );
OAI21XLTS U2747 ( .A0(n4733), .A1(n5309), .B0(n4267), .Y(op_result[7]) );
OAI21XLTS U2748 ( .A0(n4733), .A1(n5201), .B0(n4269), .Y(op_result[3]) );
INVX4TS U2749 ( .A(n5033), .Y(n3719) );
XNOR2X1TS U2750 ( .A(n2560), .B(n3295), .Y(n3196) );
INVX2TS U2751 ( .A(n4722), .Y(n4745) );
NAND3X1TS U2752 ( .A(n4497), .B(n4518), .C(n2385), .Y(n4516) );
AO21X4TS U2753 ( .A0(n4752), .A1(n5170), .B0(n2225), .Y(n3790) );
OAI211X1TS U2754 ( .A0(n3419), .A1(n3475), .B0(n3418), .C0(n3417), .Y(n3424)
);
NAND3BX1TS U2755 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .C(n3557), .Y(n3326) );
INVX3TS U2756 ( .A(n4418), .Y(n4991) );
INVX3TS U2757 ( .A(DP_OP_500J224_126_4510_n32), .Y(
DP_OP_500J224_126_4510_n27) );
NAND2X4TS U2758 ( .A(n5148), .B(n5176), .Y(n3726) );
AOI22X1TS U2759 ( .A0(n5132), .A1(FPADDSUB_DMP_SFG[1]), .B0(n5136), .B1(
FPADDSUB_DMP_SHT2_EWSW[1]), .Y(n2410) );
NAND2BX1TS U2760 ( .AN(n4896), .B(n4895), .Y(n1690) );
OAI21XLTS U2761 ( .A0(n4733), .A1(n5311), .B0(n4150), .Y(op_result[5]) );
OAI21XLTS U2762 ( .A0(n4733), .A1(n5200), .B0(n4151), .Y(op_result[4]) );
NAND3X1TS U2763 ( .A(FPMULT_Op_MX[12]), .B(FPMULT_Op_MY[15]), .C(n3529), .Y(
n4314) );
OAI211XLTS U2764 ( .A0(FPADDSUB_intDX_EWSW[8]), .A1(n5285), .B0(n3441), .C0(
n3444), .Y(n3455) );
NOR2X1TS U2765 ( .A(n2490), .B(n2489), .Y(n2508) );
NOR2X1TS U2766 ( .A(n4383), .B(n3296), .Y(n3298) );
NAND3BX1TS U2767 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .C(n3559), .Y(n4722) );
NAND2X4TS U2768 ( .A(n2285), .B(n5176), .Y(n3758) );
ADDFHX2TS U2769 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[2]), .B(
n2448), .CI(n2447), .CO(n2456), .S(n2455) );
INVX3TS U2770 ( .A(n4418), .Y(n4987) );
NOR2X4TS U2771 ( .A(n5091), .B(n5286), .Y(n3190) );
OR2X4TS U2772 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .B(n2194), .Y(n3536) );
NOR2X6TS U2773 ( .A(FPADDSUB_ADD_OVRFLW_NRM), .B(n5034), .Y(n3545) );
INVX4TS U2774 ( .A(n3537), .Y(n4006) );
INVX3TS U2775 ( .A(n2285), .Y(n5148) );
OAI211X2TS U2776 ( .A0(FPADDSUB_intDX_EWSW[20]), .A1(n5278), .B0(n3471),
.C0(n3456), .Y(n3465) );
OAI211X2TS U2777 ( .A0(FPADDSUB_intDX_EWSW[12]), .A1(n5268), .B0(n3451),
.C0(n3437), .Y(n3453) );
NAND3X1TS U2778 ( .A(n5280), .B(n3416), .C(FPADDSUB_intDX_EWSW[26]), .Y(
n3418) );
NAND3X1TS U2779 ( .A(n5252), .B(n3194), .C(n3546), .Y(n3558) );
BUFX4TS U2780 ( .A(n1480), .Y(n2200) );
OR3X4TS U2781 ( .A(FPMULT_FS_Module_state_reg[1]), .B(n5291), .C(n3589), .Y(
n4418) );
BUFX3TS U2782 ( .A(n4527), .Y(n2201) );
CLKINVX3TS U2783 ( .A(n5029), .Y(n3723) );
INVX2TS U2784 ( .A(n3589), .Y(n3600) );
NAND2X2TS U2785 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[0]), .B(
n2450), .Y(n2559) );
OAI21X1TS U2786 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[24]), .A1(n4007), .B0(n2218),
.Y(n4008) );
NAND4BX1TS U2787 ( .AN(n4385), .B(n4000), .C(n5189), .D(n5167), .Y(n4001) );
ADDHX2TS U2788 ( .A(FPMULT_Op_MX[12]), .B(FPMULT_Op_MX[0]), .CO(n2418), .S(
n2706) );
BUFX4TS U2789 ( .A(n4149), .Y(n4275) );
AND3X1TS U2790 ( .A(n2408), .B(n2407), .C(n2406), .Y(n2409) );
NAND2BX1TS U2791 ( .AN(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[1]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]), .Y(n2805)
);
NAND2BX1TS U2792 ( .AN(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[13]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]), .Y(
n2781) );
NOR2X1TS U2793 ( .A(FPADDSUB_shift_value_SHT2_EWR[2]), .B(
FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n3718) );
NAND2BX1TS U2794 ( .AN(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[12]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]), .Y(
n2778) );
INVX1TS U2795 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .Y(n4729)
);
NAND2BX1TS U2796 ( .AN(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[1]), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[1]), .Y(n2644)
);
NAND2X1TS U2797 ( .A(FPADDSUB_DmP_mant_SFG_SWR[2]), .B(n5234), .Y(n5046) );
OR3X4TS U2798 ( .A(FPSENCOS_cont_var_out[0]), .B(n5319), .C(n5206), .Y(n4778) );
CLKINVX2TS U2799 ( .A(FPMULT_Sgf_normalized_result[8]), .Y(n4958) );
CLKINVX2TS U2800 ( .A(FPMULT_Sgf_normalized_result[10]), .Y(n4963) );
CLKINVX2TS U2801 ( .A(FPMULT_Sgf_normalized_result[20]), .Y(n4982) );
NOR2X1TS U2802 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n3194) );
CLKINVX2TS U2803 ( .A(FPMULT_Op_MY[7]), .Y(n4446) );
NOR2X1TS U2804 ( .A(FPADDSUB_Raw_mant_NRM_SWR[23]), .B(
FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n3999) );
NAND2BX1TS U2805 ( .AN(FPADDSUB_intDX_EWSW[19]), .B(FPADDSUB_intDY_EWSW[19]),
.Y(n3462) );
NAND2BX1TS U2806 ( .AN(FPADDSUB_intDX_EWSW[21]), .B(FPADDSUB_intDY_EWSW[21]),
.Y(n3456) );
NAND2BX1TS U2807 ( .AN(FPADDSUB_intDY_EWSW[27]), .B(FPADDSUB_intDX_EWSW[27]),
.Y(n3417) );
ADDHX2TS U2808 ( .A(FPMULT_Op_MY[18]), .B(FPMULT_Op_MY[12]), .CO(n2819), .S(
n2836) );
NAND2BX1TS U2809 ( .AN(FPADDSUB_intDX_EWSW[27]), .B(FPADDSUB_intDY_EWSW[27]),
.Y(n3416) );
ADDHX2TS U2810 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[0]), .CO(n3081), .S(
n3165) );
NAND2BX1TS U2811 ( .AN(FPADDSUB_intDX_EWSW[24]), .B(FPADDSUB_intDY_EWSW[24]),
.Y(n3472) );
NOR2X1TS U2812 ( .A(n3074), .B(n3071), .Y(n3076) );
NAND2X2TS U2813 ( .A(n2393), .B(n2559), .Y(n2560) );
AFHCONX4TS U2814 ( .A(n4614), .B(n4613), .CI(n4612), .CON(n4608), .S(n4615)
);
AOI21X2TS U2815 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[10]), .A1(n2388), .B0(n3988),
.Y(n4053) );
AOI21X2TS U2816 ( .A0(FPADDSUB_DMP_SFG[15]), .A1(n5155), .B0(n4335), .Y(
n5071) );
AOI21X4TS U2817 ( .A0(FPADDSUB_DMP_SFG[11]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[13]), .B0(n4206), .Y(n5063) );
AOI21X4TS U2818 ( .A0(FPADDSUB_DMP_SFG[12]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[14]), .B0(n5062), .Y(n4321) );
AOI21X4TS U2819 ( .A0(FPADDSUB_DMP_SFG[14]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[16]), .B0(n4328), .Y(n4340) );
AO21X4TS U2820 ( .A0(FPADDSUB_DMP_SFG[21]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[23]), .B0(n5006), .Y(n5087) );
NOR2X2TS U2821 ( .A(n3667), .B(n3668), .Y(n3666) );
CMPR42X1TS U2822 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]), .B(
DP_OP_499J224_125_1651_n82), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[3]), .D(
DP_OP_499J224_125_1651_n117), .ICI(DP_OP_499J224_125_1651_n83), .S(
DP_OP_499J224_125_1651_n81), .ICO(DP_OP_499J224_125_1651_n79), .CO(
DP_OP_499J224_125_1651_n80) );
INVX2TS U2823 ( .A(n4588), .Y(DP_OP_499J224_125_1651_n117) );
CMPR42X1TS U2824 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[16]), .C(
DP_OP_499J224_125_1651_n43), .D(DP_OP_499J224_125_1651_n104), .ICI(
DP_OP_499J224_125_1651_n44), .S(DP_OP_499J224_125_1651_n42), .ICO(
DP_OP_499J224_125_1651_n40), .CO(DP_OP_499J224_125_1651_n41) );
INVX2TS U2825 ( .A(n4660), .Y(DP_OP_499J224_125_1651_n104) );
NOR2X1TS U2826 ( .A(n2549), .B(n2554), .Y(n2459) );
INVX2TS U2827 ( .A(n4604), .Y(n3249) );
OAI21X1TS U2828 ( .A0(n2512), .A1(n2508), .B0(n2509), .Y(n2507) );
NOR2X2TS U2829 ( .A(n2471), .B(n2470), .Y(n2538) );
ADDHXLTS U2830 ( .A(n3076), .B(n3075), .CO(n3077), .S(
DP_OP_501J224_127_5235_n150) );
ADDHXLTS U2831 ( .A(n2999), .B(n2998), .CO(n3067), .S(n3004) );
INVX2TS U2832 ( .A(n4618), .Y(n3266) );
XOR2X1TS U2833 ( .A(n2512), .B(n2511), .Y(n2577) );
NAND2X1TS U2834 ( .A(n2510), .B(n2509), .Y(n2511) );
INVX2TS U2835 ( .A(n2508), .Y(n2510) );
NAND2X1TS U2836 ( .A(n2471), .B(n2470), .Y(n2539) );
INVX2TS U2837 ( .A(n2978), .Y(n3015) );
INVX2TS U2838 ( .A(n2441), .Y(n3072) );
XOR2X1TS U2839 ( .A(n2529), .B(n2528), .Y(n2583) );
NAND2X1TS U2840 ( .A(n2527), .B(n2526), .Y(n2528) );
AOI21X1TS U2841 ( .A0(n2547), .A1(n2524), .B0(n2523), .Y(n2529) );
INVX2TS U2842 ( .A(n4524), .Y(n3247) );
NAND2X1TS U2843 ( .A(n2545), .B(n2544), .Y(n2546) );
INVX2TS U2844 ( .A(n2543), .Y(n2545) );
XOR2X1TS U2845 ( .A(n2565), .B(n2564), .Y(n3197) );
ADDHXLTS U2846 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]), .B(n3195), .CO(DP_OP_499J224_125_1651_n90), .S(n3229) );
NOR2X2TS U2847 ( .A(n2475), .B(n2474), .Y(n2525) );
CMPR42X1TS U2848 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]), .B(
DP_OP_499J224_125_1651_n76), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[5]), .D(
DP_OP_499J224_125_1651_n115), .ICI(DP_OP_499J224_125_1651_n77), .S(
DP_OP_499J224_125_1651_n75), .ICO(DP_OP_499J224_125_1651_n73), .CO(
DP_OP_499J224_125_1651_n74) );
INVX2TS U2849 ( .A(n4594), .Y(DP_OP_499J224_125_1651_n115) );
INVX2TS U2850 ( .A(n2513), .Y(n2486) );
NAND2X1TS U2851 ( .A(n2494), .B(n2493), .Y(n2505) );
NOR2X2TS U2852 ( .A(n2473), .B(n2472), .Y(n2532) );
INVX2TS U2853 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[5]), .Y(n2465)
);
CMPR42X1TS U2854 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]), .B(
DP_OP_499J224_125_1651_n52), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[13]), .D(
DP_OP_499J224_125_1651_n107), .ICI(DP_OP_499J224_125_1651_n130), .S(
DP_OP_499J224_125_1651_n51), .ICO(DP_OP_499J224_125_1651_n49), .CO(
DP_OP_499J224_125_1651_n50) );
CMPR42X1TS U2855 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]), .B(
DP_OP_499J224_125_1651_n73), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[6]), .D(
DP_OP_499J224_125_1651_n114), .ICI(DP_OP_499J224_125_1651_n74), .S(
DP_OP_499J224_125_1651_n72), .ICO(DP_OP_499J224_125_1651_n70), .CO(
DP_OP_499J224_125_1651_n71) );
INVX2TS U2856 ( .A(n4550), .Y(DP_OP_499J224_125_1651_n114) );
CMPR42X1TS U2857 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]), .B(
DP_OP_499J224_125_1651_n61), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[10]), .D(
DP_OP_499J224_125_1651_n110), .ICI(DP_OP_499J224_125_1651_n62), .S(
DP_OP_499J224_125_1651_n60), .ICO(DP_OP_499J224_125_1651_n58), .CO(
DP_OP_499J224_125_1651_n59) );
INVX2TS U2858 ( .A(n4555), .Y(DP_OP_499J224_125_1651_n110) );
CMPR42X1TS U2859 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]), .B(
DP_OP_499J224_125_1651_n49), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[14]), .D(
DP_OP_499J224_125_1651_n106), .ICI(DP_OP_499J224_125_1651_n50), .S(
DP_OP_499J224_125_1651_n48), .ICO(DP_OP_499J224_125_1651_n46), .CO(
DP_OP_499J224_125_1651_n47) );
INVX2TS U2860 ( .A(n4580), .Y(DP_OP_499J224_125_1651_n106) );
XNOR2X1TS U2861 ( .A(n2515), .B(n2514), .Y(n2579) );
NAND2X1TS U2862 ( .A(n2389), .B(n2513), .Y(n2514) );
XOR2X1TS U2863 ( .A(n2504), .B(n2503), .Y(n2573) );
NAND2X1TS U2864 ( .A(n2502), .B(n2501), .Y(n2503) );
INVX2TS U2865 ( .A(n2500), .Y(n2502) );
INVX2TS U2866 ( .A(n4622), .Y(n3268) );
INVX2TS U2867 ( .A(n2532), .Y(n2534) );
NAND2X1TS U2868 ( .A(n2473), .B(n2472), .Y(n2533) );
OAI21X2TS U2869 ( .A0(n2538), .A1(n2544), .B0(n2539), .Y(n2530) );
NOR2X2TS U2870 ( .A(n2543), .B(n2538), .Y(n2531) );
INVX2TS U2871 ( .A(FPMULT_Op_MX[4]), .Y(n4415) );
NOR2X2TS U2872 ( .A(n3992), .B(n3993), .Y(n3991) );
NOR2X2TS U2873 ( .A(n4320), .B(n4321), .Y(n4319) );
CLKXOR2X2TS U2874 ( .A(FPMULT_Op_MY[11]), .B(n2942), .Y(n3080) );
INVX2TS U2875 ( .A(n2970), .Y(n3074) );
INVX2TS U2876 ( .A(n2430), .Y(n3014) );
INVX2TS U2877 ( .A(n2549), .Y(n2551) );
NAND2X1TS U2878 ( .A(n2540), .B(n2539), .Y(n2541) );
XOR2X1TS U2879 ( .A(n2558), .B(n2557), .Y(n2593) );
NAND2X1TS U2880 ( .A(n2380), .B(n3240), .Y(n3241) );
AOI21X1TS U2881 ( .A0(n3245), .A1(n2379), .B0(n3237), .Y(n3242) );
INVX2TS U2882 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[10]), .Y(
n2751) );
INVX2TS U2883 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]), .Y(n2752) );
AOI222X1TS U2884 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n5328), .B0(n3432), .B1(
n3431), .C0(FPADDSUB_intDY_EWSW[5]), .C1(n5218), .Y(n3434) );
NAND2BXLTS U2885 ( .AN(FPADDSUB_intDY_EWSW[9]), .B(FPADDSUB_intDX_EWSW[9]),
.Y(n3443) );
NAND3XLTS U2886 ( .A(n5285), .B(n3441), .C(FPADDSUB_intDX_EWSW[8]), .Y(n3442) );
NOR2XLTS U2887 ( .A(n3439), .B(FPADDSUB_intDY_EWSW[10]), .Y(n3440) );
OAI21XLTS U2888 ( .A0(FPADDSUB_intDX_EWSW[13]), .A1(n5271), .B0(
FPADDSUB_intDX_EWSW[12]), .Y(n3438) );
INVX2TS U2889 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]), .Y(n2755) );
INVX2TS U2890 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]), .Y(n2753) );
INVX2TS U2891 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[9]), .Y(n2754)
);
INVX2TS U2892 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[8]), .Y(n2482)
);
INVX2TS U2893 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[8]), .Y(n2483) );
INVX2TS U2894 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[9]), .Y(n2487)
);
INVX2TS U2895 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[9]), .Y(n2488) );
INVX2TS U2896 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[10]), .Y(n2491) );
INVX2TS U2897 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[11]), .Y(
n2496) );
INVX2TS U2898 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[11]), .Y(n2497) );
NOR2XLTS U2899 ( .A(n3474), .B(FPADDSUB_intDY_EWSW[24]), .Y(n3415) );
NAND2BXLTS U2900 ( .AN(FPADDSUB_intDX_EWSW[9]), .B(FPADDSUB_intDY_EWSW[9]),
.Y(n3441) );
INVX2TS U2901 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[1]), .Y(n2449)
);
INVX2TS U2902 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[7]), .Y(n2478) );
INVX2TS U2903 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[8]), .Y(n2600)
);
INVX2TS U2904 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[8]), .Y(n2601) );
INVX2TS U2905 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[9]), .Y(n2598)
);
INVX2TS U2906 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .Y(n2599) );
INVX2TS U2907 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[10]), .Y(n2596) );
INVX2TS U2908 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[10]), .Y(n2597)
);
INVX2TS U2909 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[11]), .Y(n2594) );
INVX2TS U2910 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[11]), .Y(n2595)
);
NOR2X1TS U2911 ( .A(n2481), .B(n2480), .Y(n2516) );
NAND2X1TS U2912 ( .A(n2481), .B(n2480), .Y(n2517) );
AOI21X1TS U2913 ( .A0(n2547), .A1(n2401), .B0(n2400), .Y(n2520) );
CLKAND2X2TS U2914 ( .A(n2531), .B(n2477), .Y(n2401) );
AO21XLTS U2915 ( .A0(n2530), .A1(n2477), .B0(n2476), .Y(n2400) );
NOR2X1TS U2916 ( .A(n2532), .B(n2525), .Y(n2477) );
NOR2X1TS U2917 ( .A(n2498), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[12]), .Y(
n2500) );
NAND2X1TS U2918 ( .A(n2498), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[12]), .Y(
n2501) );
AOI21X1TS U2919 ( .A0(n2507), .A1(n2390), .B0(n2495), .Y(n2504) );
INVX2TS U2920 ( .A(n2505), .Y(n2495) );
CMPR42X1TS U2921 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]), .B(
DP_OP_499J224_125_1651_n79), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[4]), .D(
DP_OP_499J224_125_1651_n116), .ICI(DP_OP_499J224_125_1651_n80), .S(
DP_OP_499J224_125_1651_n78), .ICO(DP_OP_499J224_125_1651_n76), .CO(
DP_OP_499J224_125_1651_n77) );
INVX2TS U2922 ( .A(n4602), .Y(DP_OP_499J224_125_1651_n116) );
CMPR42X1TS U2923 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[8]), .B(
DP_OP_499J224_125_1651_n90), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[1]), .D(
DP_OP_499J224_125_1651_n88), .ICI(DP_OP_499J224_125_1651_n119), .S(
DP_OP_499J224_125_1651_n87), .ICO(DP_OP_499J224_125_1651_n85), .CO(
DP_OP_499J224_125_1651_n86) );
INVX2TS U2924 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[6]), .Y(n2466) );
INVX2TS U2925 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[6]), .Y(n2467)
);
CMPR42X1TS U2926 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]), .B(
DP_OP_499J224_125_1651_n67), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[8]), .D(
DP_OP_499J224_125_1651_n112), .ICI(DP_OP_499J224_125_1651_n68), .S(
DP_OP_499J224_125_1651_n66), .ICO(DP_OP_499J224_125_1651_n64), .CO(
DP_OP_499J224_125_1651_n65) );
INVX2TS U2927 ( .A(n4558), .Y(DP_OP_499J224_125_1651_n112) );
CMPR42X1TS U2928 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]), .B(
DP_OP_499J224_125_1651_n58), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[11]), .D(
DP_OP_499J224_125_1651_n109), .ICI(DP_OP_499J224_125_1651_n59), .S(
DP_OP_499J224_125_1651_n57), .ICO(DP_OP_499J224_125_1651_n55), .CO(
DP_OP_499J224_125_1651_n56) );
INVX2TS U2929 ( .A(n4572), .Y(DP_OP_499J224_125_1651_n109) );
ADDFX2TS U2930 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[3]), .B(
n2461), .CI(n2460), .CO(n2468), .S(n2457) );
INVX2TS U2931 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[3]), .Y(n2461)
);
OAI21X1TS U2932 ( .A0(n2522), .A1(n2532), .B0(n2533), .Y(n2523) );
INVX2TS U2933 ( .A(n2530), .Y(n2522) );
NOR2X1TS U2934 ( .A(n2521), .B(n2532), .Y(n2524) );
INVX2TS U2935 ( .A(n2531), .Y(n2521) );
NAND2X1TS U2936 ( .A(n2475), .B(n2474), .Y(n2526) );
INVX2TS U2937 ( .A(n2525), .Y(n2527) );
CMPR42X1TS U2938 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]), .B(
DP_OP_499J224_125_1651_n70), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[7]), .D(
DP_OP_499J224_125_1651_n113), .ICI(DP_OP_499J224_125_1651_n71), .S(
DP_OP_499J224_125_1651_n69), .ICO(DP_OP_499J224_125_1651_n67), .CO(
DP_OP_499J224_125_1651_n68) );
INVX2TS U2939 ( .A(n4590), .Y(DP_OP_499J224_125_1651_n113) );
CMPR42X1TS U2940 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]), .B(
DP_OP_499J224_125_1651_n64), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[9]), .D(
DP_OP_499J224_125_1651_n111), .ICI(DP_OP_499J224_125_1651_n65), .S(
DP_OP_499J224_125_1651_n63), .ICO(DP_OP_499J224_125_1651_n61), .CO(
DP_OP_499J224_125_1651_n62) );
INVX2TS U2941 ( .A(n4563), .Y(DP_OP_499J224_125_1651_n111) );
CMPR42X1TS U2942 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]), .B(
DP_OP_499J224_125_1651_n55), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[12]), .D(
DP_OP_499J224_125_1651_n108), .ICI(DP_OP_499J224_125_1651_n56), .S(
DP_OP_499J224_125_1651_n54), .ICO(DP_OP_499J224_125_1651_n52), .CO(
DP_OP_499J224_125_1651_n53) );
INVX2TS U2943 ( .A(n4576), .Y(DP_OP_499J224_125_1651_n108) );
INVX2TS U2944 ( .A(n4585), .Y(DP_OP_499J224_125_1651_n105) );
ADDHX1TS U2945 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[10]), .B(
DP_OP_499J224_125_1651_n40), .CO(n3239), .S(n3236) );
XOR2X1TS U2946 ( .A(n2520), .B(n2519), .Y(n2581) );
NAND2X1TS U2947 ( .A(n2518), .B(n2517), .Y(n2519) );
INVX2TS U2948 ( .A(n2516), .Y(n2518) );
NOR2X2TS U2949 ( .A(n2453), .B(n2452), .Y(n2561) );
AOI21X2TS U2950 ( .A0(n3295), .A1(n2393), .B0(n2451), .Y(n2564) );
NAND2X1TS U2951 ( .A(n2453), .B(n2452), .Y(n2562) );
XNOR2X1TS U2952 ( .A(n2499), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_middle[13]), .Y(
n2571) );
INVX2TS U2953 ( .A(n2538), .Y(n2540) );
XNOR2X1TS U2954 ( .A(n2507), .B(n2506), .Y(n2575) );
NAND2X1TS U2955 ( .A(n2390), .B(n2505), .Y(n2506) );
INVX2TS U2956 ( .A(n4614), .Y(n3264) );
OAI21XLTS U2957 ( .A0(r_mode[1]), .A1(r_mode[0]), .B0(n3594), .Y(n3595) );
AOI21X1TS U2958 ( .A0(FPADDSUB_DMP_SFG[1]), .A1(FPADDSUB_DmP_mant_SFG_SWR[3]), .B0(n3318), .Y(n3585) );
NOR2X1TS U2959 ( .A(n3584), .B(n3585), .Y(n3583) );
AOI211X1TS U2960 ( .A0(FPADDSUB_Data_array_SWR[8]), .A1(n5107), .B0(n3734),
.C0(n3733), .Y(n3915) );
AOI211X1TS U2961 ( .A0(FPADDSUB_Data_array_SWR[4]), .A1(n3719), .B0(n3746),
.C0(n3745), .Y(n3921) );
AOI211X1TS U2962 ( .A0(FPADDSUB_Data_array_SWR[6]), .A1(n5107), .B0(n3900),
.C0(n3899), .Y(n3927) );
AOI211X1TS U2963 ( .A0(FPADDSUB_Data_array_SWR[9]), .A1(n5107), .B0(n3752),
.C0(n3751), .Y(n3910) );
AOI211X2TS U2964 ( .A0(FPADDSUB_Data_array_SWR[17]), .A1(n3740), .B0(n5014),
.C0(n3722), .Y(n3760) );
AOI211X1TS U2965 ( .A0(FPADDSUB_Data_array_SWR[10]), .A1(n5107), .B0(n3905),
.C0(n3904), .Y(n3913) );
AOI211X2TS U2966 ( .A0(n3907), .A1(FPADDSUB_Data_array_SWR[12]), .B0(n5014),
.C0(n3906), .Y(n5109) );
OAI21XLTS U2967 ( .A0(n4426), .A1(n3842), .B0(n3841), .Y(n3844) );
NOR2XLTS U2968 ( .A(n5188), .B(n5253), .Y(n4675) );
NAND3XLTS U2969 ( .A(n2197), .B(n4930), .C(mult_x_309_n58), .Y(n3411) );
INVX2TS U2970 ( .A(n4626), .Y(n3270) );
INVX2TS U2971 ( .A(n4523), .Y(n3251) );
INVX2TS U2972 ( .A(n3243), .Y(n3237) );
NAND2X1TS U2973 ( .A(n3239), .B(n3238), .Y(n3240) );
NAND2X2TS U2974 ( .A(FPADDSUB_ADD_OVRFLW_NRM), .B(
FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n3537) );
INVX2TS U2975 ( .A(n4735), .Y(n4254) );
XOR2X1TS U2976 ( .A(n2536), .B(n2535), .Y(n2585) );
NAND2X1TS U2977 ( .A(n2534), .B(n2533), .Y(n2535) );
XNOR2X1TS U2978 ( .A(n3245), .B(n3244), .Y(n4617) );
NAND2X1TS U2979 ( .A(n2379), .B(n3243), .Y(n3244) );
OAI222X1TS U2980 ( .A0(FPADDSUB_DmP_mant_SHT1_SW[18]), .A1(
FPADDSUB_Shift_reg_FLAGS_7[1]), .B0(FPADDSUB_Raw_mant_NRM_SWR[20]),
.B1(n4048), .C0(FPADDSUB_Raw_mant_NRM_SWR[5]), .C1(n4065), .Y(n4041)
);
AOI222X2TS U2981 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[8]), .A1(
FPADDSUB_DMP_SFG[6]), .B0(FPADDSUB_DmP_mant_SFG_SWR[8]), .B1(n5056),
.C0(FPADDSUB_DMP_SFG[6]), .C1(n5056), .Y(n3962) );
AOI21X1TS U2982 ( .A0(FPADDSUB_DMP_SFG[3]), .A1(FPADDSUB_DmP_mant_SFG_SWR[5]), .B0(n3658), .Y(n3667) );
NOR2X1TS U2983 ( .A(n3581), .B(n3580), .Y(n3579) );
OR2X1TS U2984 ( .A(FPADDSUB_ADD_OVRFLW_NRM2), .B(
FPADDSUB_LZD_output_NRM2_EW[0]), .Y(n4414) );
OAI32X1TS U2985 ( .A0(n3165), .A1(n3154), .A2(n2371), .B0(n3110), .B1(n3093),
.Y(n3178) );
OAI32X1TS U2986 ( .A0(n2706), .A1(n2976), .A2(n2370), .B0(n2705), .B1(n2658),
.Y(mult_x_313_n76) );
OAI32X1TS U2987 ( .A0(n2706), .A1(n2972), .A2(n2370), .B0(n2665), .B1(n2658),
.Y(n2746) );
NAND3XLTS U2988 ( .A(n4447), .B(n4469), .C(n4446), .Y(n4467) );
OAI21XLTS U2989 ( .A0(n4904), .A1(n3521), .B0(n3549), .Y(n3520) );
OAI21XLTS U2990 ( .A0(n4511), .A1(n4508), .B0(n4509), .Y(n3890) );
OAI21XLTS U2991 ( .A0(n4515), .A1(n4512), .B0(n4513), .Y(n3873) );
OAI21XLTS U2992 ( .A0(n4908), .A1(n3524), .B0(n3539), .Y(n3523) );
NOR2XLTS U2993 ( .A(n3080), .B(n3025), .Y(DP_OP_501J224_127_5235_n77) );
NAND3XLTS U2994 ( .A(FPMULT_Op_MX[20]), .B(mult_x_309_n33), .C(
mult_x_309_n26), .Y(n4667) );
OAI211XLTS U2995 ( .A0(n4392), .A1(n4391), .B0(n4390), .C0(n4389), .Y(n4393)
);
NAND3XLTS U2996 ( .A(n4374), .B(FPADDSUB_Shift_reg_FLAGS_7[1]), .C(n4373),
.Y(n4534) );
NOR2XLTS U2997 ( .A(n5034), .B(n4376), .Y(n4377) );
AOI211X1TS U2998 ( .A0(n3999), .A1(n3998), .B0(FPADDSUB_Raw_mant_NRM_SWR[25]), .C0(FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n4005) );
BUFX4TS U2999 ( .A(n5120), .Y(n5153) );
XNOR2X1TS U3000 ( .A(n2553), .B(n2552), .Y(n2591) );
NAND2X1TS U3001 ( .A(n2551), .B(n2550), .Y(n2552) );
AHHCINX2TS U3002 ( .A(n4523), .CIN(n4522), .S(n3306), .CO(n4603) );
NAND2X1TS U3003 ( .A(n4949), .B(n4950), .Y(n4952) );
NAND2X1TS U3004 ( .A(n2364), .B(n4952), .Y(n4955) );
NAND2X1TS U3005 ( .A(n2365), .B(n4954), .Y(n4957) );
AOI22X1TS U3006 ( .A0(n5061), .A1(n5009), .B0(n2218), .B1(n5091), .Y(n1410)
);
MX2X1TS U3007 ( .A(n4657), .B(FPMULT_P_Sgf[24]), .S0(n3561), .Y(n1553) );
OAI21XLTS U3008 ( .A0(n5332), .A1(n3981), .B0(n3688), .Y(n1464) );
MX2X1TS U3009 ( .A(n4565), .B(FPMULT_P_Sgf[16]), .S0(n4639), .Y(n1545) );
MX2X1TS U3010 ( .A(n4581), .B(FPMULT_P_Sgf[21]), .S0(n4639), .Y(n1550) );
MX2X1TS U3011 ( .A(n4573), .B(FPMULT_P_Sgf[18]), .S0(n4650), .Y(n1547) );
MX2X1TS U3012 ( .A(n4577), .B(FPMULT_P_Sgf[19]), .S0(n4639), .Y(n1548) );
AO22XLTS U3013 ( .A0(Data_2[29]), .A1(n4528), .B0(n4527), .B1(
FPMULT_Op_MY[29]), .Y(n1655) );
AO22XLTS U3014 ( .A0(Data_1[30]), .A1(n4528), .B0(n4419), .B1(
FPMULT_Op_MX[30]), .Y(n1688) );
AO22XLTS U3015 ( .A0(FPSENCOS_d_ff2_X[18]), .A1(n4794), .B0(
FPSENCOS_d_ff_Xn[18]), .B1(n4795), .Y(n1969) );
AO22XLTS U3016 ( .A0(FPSENCOS_d_ff2_X[15]), .A1(n4794), .B0(
FPSENCOS_d_ff_Xn[15]), .B1(n4800), .Y(n1975) );
AO22XLTS U3017 ( .A0(FPSENCOS_d_ff2_X[22]), .A1(n4794), .B0(
FPSENCOS_d_ff_Xn[22]), .B1(n4800), .Y(n1961) );
OAI211XLTS U3018 ( .A0(n3655), .A1(n4945), .B0(n3654), .C0(n3653), .Y(n1506)
);
MX2X1TS U3019 ( .A(n4661), .B(FPMULT_P_Sgf[23]), .S0(n3561), .Y(n1552) );
MX2X1TS U3020 ( .A(n4556), .B(FPMULT_P_Sgf[17]), .S0(n4560), .Y(n1546) );
MX2X1TS U3021 ( .A(n4569), .B(FPMULT_P_Sgf[20]), .S0(n4639), .Y(n1549) );
AO22XLTS U3022 ( .A0(Data_1[25]), .A1(n4529), .B0(n4898), .B1(
FPMULT_Op_MX[25]), .Y(n1683) );
AO22XLTS U3023 ( .A0(Data_1[28]), .A1(n4420), .B0(n4419), .B1(
FPMULT_Op_MX[28]), .Y(n1686) );
AO22XLTS U3024 ( .A0(Data_1[27]), .A1(n4420), .B0(n4419), .B1(
FPMULT_Op_MX[27]), .Y(n1685) );
AO22XLTS U3025 ( .A0(Data_1[26]), .A1(n4420), .B0(n4900), .B1(
FPMULT_Op_MX[26]), .Y(n1684) );
AO22XLTS U3026 ( .A0(Data_2[27]), .A1(n4529), .B0(n4898), .B1(
FPMULT_Op_MY[27]), .Y(n1653) );
MX2X1TS U3027 ( .A(FPMULT_exp_oper_result[5]), .B(
FPMULT_Exp_module_Data_S[5]), .S0(n4530), .Y(n1589) );
MX2X1TS U3028 ( .A(FPMULT_exp_oper_result[6]), .B(
FPMULT_Exp_module_Data_S[6]), .S0(n4530), .Y(n1588) );
MX2X1TS U3029 ( .A(FPMULT_exp_oper_result[7]), .B(
FPMULT_Exp_module_Data_S[7]), .S0(n4530), .Y(n1587) );
AO22XLTS U3030 ( .A0(Data_1[24]), .A1(n4528), .B0(n4527), .B1(
FPMULT_Op_MX[24]), .Y(n1682) );
AO22XLTS U3031 ( .A0(n4987), .A1(n4964), .B0(n4418), .B1(
FPMULT_Add_result[10]), .Y(n1610) );
MX2X1TS U3032 ( .A(n4654), .B(FPMULT_P_Sgf[25]), .S0(n3561), .Y(n1554) );
AO22XLTS U3033 ( .A0(Data_2[23]), .A1(n4529), .B0(n4897), .B1(
FPMULT_Op_MY[23]), .Y(n1649) );
OAI21XLTS U3034 ( .A0(n5331), .A1(n3814), .B0(n3711), .Y(n1463) );
AO22XLTS U3035 ( .A0(FPSENCOS_d_ff2_X[30]), .A1(n4794), .B0(
FPSENCOS_d_ff_Xn[30]), .B1(n4800), .Y(n1952) );
MX2X1TS U3036 ( .A(n4532), .B(FPMULT_Exp_module_Overflow_flag_A), .S0(n4560),
.Y(n1585) );
AO22XLTS U3037 ( .A0(FPSENCOS_d_ff2_X[23]), .A1(n4794), .B0(
FPSENCOS_d_ff_Xn[23]), .B1(n4795), .Y(n1959) );
OAI211XLTS U3038 ( .A0(n5378), .A1(n3655), .B0(n3612), .C0(n3611), .Y(n1526)
);
OAI211XLTS U3039 ( .A0(n3564), .A1(n5368), .B0(n3635), .C0(n3634), .Y(n1508)
);
OAI211XLTS U3040 ( .A0(n3655), .A1(n5367), .B0(n3647), .C0(n3646), .Y(n1505)
);
OAI211XLTS U3041 ( .A0(n5364), .A1(n3655), .B0(n3618), .C0(n3617), .Y(n1523)
);
OAI211XLTS U3042 ( .A0(n5365), .A1(n3655), .B0(n3615), .C0(n3614), .Y(n1521)
);
OAI211XLTS U3043 ( .A0(n5366), .A1(n3655), .B0(n3645), .C0(n3644), .Y(n1511)
);
AO22XLTS U3044 ( .A0(FPSENCOS_d_ff2_Y[24]), .A1(n4801), .B0(
FPSENCOS_d_ff_Yn[24]), .B1(n4797), .Y(n1860) );
AO22XLTS U3045 ( .A0(FPSENCOS_d_ff2_Y[25]), .A1(n4801), .B0(
FPSENCOS_d_ff_Yn[25]), .B1(n4797), .Y(n1859) );
AO22XLTS U3046 ( .A0(FPSENCOS_d_ff2_Y[26]), .A1(n4801), .B0(
FPSENCOS_d_ff_Yn[26]), .B1(n4797), .Y(n1858) );
AO22XLTS U3047 ( .A0(FPSENCOS_d_ff2_Y[27]), .A1(n4801), .B0(n2315), .B1(
n4810), .Y(n1857) );
AO22XLTS U3048 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n4811), .B0(
FPSENCOS_d_ff_Yn[29]), .B1(n4810), .Y(n1855) );
AO22XLTS U3049 ( .A0(FPSENCOS_d_ff2_Y[30]), .A1(n4811), .B0(
FPSENCOS_d_ff_Yn[30]), .B1(n4810), .Y(n1854) );
AO22XLTS U3050 ( .A0(n4546), .A1(FPADDSUB_exp_rslt_NRM2_EW1[7]), .B0(
result_add_subt[30]), .B1(n5353), .Y(n1466) );
OAI211XLTS U3051 ( .A0(n3578), .A1(n5370), .B0(n3568), .C0(n3567), .Y(n1516)
);
OAI211XLTS U3052 ( .A0(n3578), .A1(n5371), .B0(n3577), .C0(n3576), .Y(n1514)
);
OAI31X1TS U3053 ( .A0(n4748), .A1(FPSENCOS_cont_var_out[1]), .A2(n5198),
.B0(n3394), .Y(n2136) );
AO22XLTS U3054 ( .A0(n4741), .A1(n5061), .B0(n4743), .B1(n2306), .Y(n2144)
);
OAI211XLTS U3055 ( .A0(n4290), .A1(n5390), .B0(n4306), .C0(n4305), .Y(n1935)
);
OAI211XLTS U3056 ( .A0(n4239), .A1(n4198), .B0(n4197), .C0(n4196), .Y(n1913)
);
OAI211XLTS U3057 ( .A0(n4290), .A1(n5389), .B0(n4244), .C0(n4243), .Y(n1936)
);
OAI211XLTS U3058 ( .A0(n4239), .A1(n5391), .B0(n4241), .C0(n4240), .Y(n1934)
);
OAI211XLTS U3059 ( .A0(n4239), .A1(n5394), .B0(n4236), .C0(n4235), .Y(n1931)
);
OAI211XLTS U3060 ( .A0(n4239), .A1(n5422), .B0(n4234), .C0(n4233), .Y(n1842)
);
OAI211XLTS U3061 ( .A0(n4290), .A1(n5429), .B0(n4189), .C0(n4188), .Y(n1831)
);
OAI211XLTS U3062 ( .A0(n4290), .A1(n5430), .B0(n4232), .C0(n4231), .Y(n1822)
);
OAI211XLTS U3063 ( .A0(n4290), .A1(n5433), .B0(n4195), .C0(n4194), .Y(n1817)
);
OAI211XLTS U3064 ( .A0(n5195), .A1(n3532), .B0(n3337), .C0(n3589), .Y(n1693)
);
OAI21XLTS U3065 ( .A0(n4124), .A1(n3582), .B0(n4123), .Y(n1337) );
OAI21XLTS U3066 ( .A0(n4211), .A1(n3582), .B0(n4210), .Y(n1336) );
OAI211XLTS U3067 ( .A0(n4290), .A1(n5373), .B0(n4171), .C0(n4170), .Y(n1914)
);
MX2X1TS U3068 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Data_S[8]), .S0(n4530), .Y(n1595) );
OAI211XLTS U3069 ( .A0(n4239), .A1(n5384), .B0(n4309), .C0(n4308), .Y(n1941)
);
OAI211XLTS U3070 ( .A0(n4239), .A1(n5386), .B0(n4294), .C0(n4293), .Y(n1939)
);
OAI211XLTS U3071 ( .A0(n4290), .A1(n5395), .B0(n4219), .C0(n4218), .Y(n1930)
);
OAI211XLTS U3072 ( .A0(n4290), .A1(n5392), .B0(n4292), .C0(n4291), .Y(n1933)
);
OAI211XLTS U3073 ( .A0(n4290), .A1(n5387), .B0(n4298), .C0(n4297), .Y(n1938)
);
OAI211XLTS U3074 ( .A0(n4239), .A1(n5376), .B0(n4173), .C0(n4172), .Y(n1916)
);
OAI211XLTS U3075 ( .A0(n4239), .A1(n5431), .B0(n4177), .C0(n4176), .Y(n1819)
);
OAI211XLTS U3076 ( .A0(n4239), .A1(n5377), .B0(n4187), .C0(n4186), .Y(n1915)
);
OAI211XLTS U3077 ( .A0(n4290), .A1(n5372), .B0(n4179), .C0(n4178), .Y(n1912)
);
OAI211XLTS U3078 ( .A0(n4290), .A1(n5374), .B0(n4175), .C0(n4174), .Y(n1911)
);
OAI21XLTS U3079 ( .A0(n5218), .A1(n3981), .B0(n3984), .Y(n1277) );
OAI21XLTS U3080 ( .A0(n5219), .A1(n3981), .B0(n3974), .Y(n1284) );
OAI21XLTS U3081 ( .A0(n5325), .A1(n3981), .B0(n3972), .Y(n1291) );
OAI21XLTS U3082 ( .A0(n5323), .A1(n3814), .B0(n3712), .Y(n1296) );
OAI21XLTS U3083 ( .A0(n5323), .A1(n3981), .B0(n3973), .Y(n1298) );
OAI21XLTS U3084 ( .A0(n5343), .A1(n3814), .B0(n3715), .Y(n1303) );
OAI21XLTS U3085 ( .A0(n5343), .A1(n3981), .B0(n3980), .Y(n1305) );
OAI21XLTS U3086 ( .A0(n5324), .A1(n3814), .B0(n3713), .Y(n1310) );
OAI21XLTS U3087 ( .A0(n5324), .A1(n3981), .B0(n3977), .Y(n1312) );
OAI21XLTS U3088 ( .A0(n5329), .A1(n3814), .B0(n3709), .Y(n1326) );
OAI21XLTS U3089 ( .A0(n5329), .A1(n3981), .B0(n3970), .Y(n1328) );
AOI2BB1XLTS U3090 ( .A0N(n3981), .A1N(n5036), .B0(n3518), .Y(n1362) );
OAI21XLTS U3091 ( .A0(n5317), .A1(n3981), .B0(n3971), .Y(n1368) );
OAI21XLTS U3092 ( .A0(n5217), .A1(n3976), .B0(n3706), .Y(n1389) );
OAI21XLTS U3093 ( .A0(n5216), .A1(n3976), .B0(n3701), .Y(n1392) );
OAI21XLTS U3094 ( .A0(n5318), .A1(n3976), .B0(n3702), .Y(n1404) );
OAI21XLTS U3095 ( .A0(n5316), .A1(n3976), .B0(n3704), .Y(n1407) );
OAI21XLTS U3096 ( .A0(n5345), .A1(n3814), .B0(n3708), .Y(n1458) );
OAI21XLTS U3097 ( .A0(n5344), .A1(n3814), .B0(n3707), .Y(n1459) );
OAI21XLTS U3098 ( .A0(n5346), .A1(n3814), .B0(n3717), .Y(n1460) );
OAI21XLTS U3099 ( .A0(n5215), .A1(n3814), .B0(n3714), .Y(n1461) );
AO21XLTS U3100 ( .A0(n2358), .A1(n4941), .B0(n4542), .Y(n1586) );
OAI211XLTS U3101 ( .A0(n4945), .A1(n3564), .B0(n3629), .C0(n3628), .Y(n1507)
);
OAI211XLTS U3102 ( .A0(n3578), .A1(n4949), .B0(n3563), .C0(n3562), .Y(n1509)
);
OAI221XLTS U3103 ( .A0(n4560), .A1(FPMULT_P_Sgf[28]), .B0(n3641), .B1(
FPMULT_P_Sgf[27]), .C0(n2199), .Y(n3562) );
OAI211XLTS U3104 ( .A0(n3655), .A1(n5383), .B0(n3606), .C0(n3605), .Y(n1510)
);
OAI211XLTS U3105 ( .A0(n5382), .A1(n3655), .B0(n3643), .C0(n3642), .Y(n1512)
);
OAI211XLTS U3106 ( .A0(n3578), .A1(n4958), .B0(n3566), .C0(n3565), .Y(n1513)
);
OAI211XLTS U3107 ( .A0(n3578), .A1(n4963), .B0(n3570), .C0(n3569), .Y(n1515)
);
OAI211XLTS U3108 ( .A0(n3564), .A1(n4109), .B0(n3631), .C0(n3630), .Y(n1518)
);
OAI211XLTS U3109 ( .A0(n3578), .A1(n4971), .B0(n3575), .C0(n3574), .Y(n1519)
);
OAI211XLTS U3110 ( .A0(n5380), .A1(n3655), .B0(n3621), .C0(n3620), .Y(n1520)
);
OAI211XLTS U3111 ( .A0(n5379), .A1(n3655), .B0(n3609), .C0(n3608), .Y(n1522)
);
OAI211XLTS U3112 ( .A0(n3578), .A1(n4982), .B0(n3573), .C0(n3572), .Y(n1525)
);
MX2X1TS U3113 ( .A(n4586), .B(FPMULT_P_Sgf[22]), .S0(n4639), .Y(n1551) );
AO22XLTS U3114 ( .A0(Data_2[7]), .A1(n4528), .B0(n4419), .B1(FPMULT_Op_MY[7]), .Y(n1633) );
AO22XLTS U3115 ( .A0(Data_2[24]), .A1(n4529), .B0(n4897), .B1(n2316), .Y(
n1650) );
AO22XLTS U3116 ( .A0(Data_2[25]), .A1(n4529), .B0(n4897), .B1(n2320), .Y(
n1651) );
AO22XLTS U3117 ( .A0(Data_2[26]), .A1(n4420), .B0(n4897), .B1(n2319), .Y(
n1652) );
AO22XLTS U3118 ( .A0(Data_2[28]), .A1(n4528), .B0(n4898), .B1(n2304), .Y(
n1654) );
AO22XLTS U3119 ( .A0(Data_2[30]), .A1(n4528), .B0(n4527), .B1(n2345), .Y(
n1656) );
AO22XLTS U3120 ( .A0(n4984), .A1(n4951), .B0(n4418), .B1(n2353), .Y(n1616)
);
OAI211XLTS U3121 ( .A0(FPMULT_Sgf_normalized_result[11]), .A1(n4965), .B0(
n4991), .C0(n4968), .Y(n4966) );
AO22XLTS U3122 ( .A0(n4987), .A1(n4969), .B0(n4418), .B1(n2356), .Y(n1608)
);
AO22XLTS U3123 ( .A0(n4987), .A1(n4972), .B0(n4418), .B1(n2352), .Y(n1606)
);
AO22XLTS U3124 ( .A0(n4990), .A1(FPMULT_Add_result[16]), .B0(n4984), .B1(
n4977), .Y(n1604) );
AO22XLTS U3125 ( .A0(Data_1[23]), .A1(n4528), .B0(n4898), .B1(n2349), .Y(
n1681) );
AO22XLTS U3126 ( .A0(Data_1[29]), .A1(n4528), .B0(n4419), .B1(n2307), .Y(
n1687) );
AO22XLTS U3127 ( .A0(n4808), .A1(n2342), .B0(n4782), .B1(
FPSENCOS_d_ff3_sh_x_out[5]), .Y(n1994) );
AO22XLTS U3128 ( .A0(FPSENCOS_d_ff2_Y[5]), .A1(n4801), .B0(
FPSENCOS_d_ff_Yn[5]), .B1(n4795), .Y(n1897) );
AO22XLTS U3129 ( .A0(n4812), .A1(FPSENCOS_d_ff3_sh_x_out[9]), .B0(n4803),
.B1(n2324), .Y(n1986) );
AO22XLTS U3130 ( .A0(n2324), .A1(n4794), .B0(FPSENCOS_d_ff_Xn[9]), .B1(n4800), .Y(n1987) );
AO22XLTS U3131 ( .A0(FPSENCOS_d_ff2_Y[9]), .A1(n4798), .B0(
FPSENCOS_d_ff_Yn[9]), .B1(n4800), .Y(n1889) );
AO22XLTS U3132 ( .A0(n4781), .A1(FPSENCOS_d_ff3_sh_x_out[1]), .B0(n4808),
.B1(n2330), .Y(n2002) );
AO22XLTS U3133 ( .A0(n4808), .A1(FPSENCOS_d_ff2_Y[1]), .B0(n4868), .B1(
FPSENCOS_d_ff3_sh_y_out[1]), .Y(n1904) );
AO22XLTS U3134 ( .A0(FPSENCOS_d_ff2_Y[1]), .A1(n4798), .B0(n2309), .B1(n4800), .Y(n1905) );
AO22XLTS U3135 ( .A0(n4781), .A1(FPSENCOS_d_ff3_sh_x_out[0]), .B0(n4808),
.B1(n2325), .Y(n2004) );
AO22XLTS U3136 ( .A0(n2325), .A1(n4811), .B0(FPSENCOS_d_ff_Xn[0]), .B1(n4797), .Y(n2005) );
AO22XLTS U3137 ( .A0(n4808), .A1(FPSENCOS_d_ff2_Y[0]), .B0(n4868), .B1(
FPSENCOS_d_ff3_sh_y_out[0]), .Y(n1906) );
AO22XLTS U3138 ( .A0(FPSENCOS_d_ff2_Y[0]), .A1(n4798), .B0(
FPSENCOS_d_ff_Yn[0]), .B1(n4795), .Y(n1907) );
AO22XLTS U3139 ( .A0(FPSENCOS_d_ff2_Y[7]), .A1(n4798), .B0(
FPSENCOS_d_ff_Yn[7]), .B1(n4795), .Y(n1893) );
AO22XLTS U3140 ( .A0(n4781), .A1(FPSENCOS_d_ff3_sh_x_out[2]), .B0(n4808),
.B1(n2331), .Y(n2000) );
AO22XLTS U3141 ( .A0(n4808), .A1(FPSENCOS_d_ff2_Y[2]), .B0(n4868), .B1(
FPSENCOS_d_ff3_sh_y_out[2]), .Y(n1902) );
AO22XLTS U3142 ( .A0(FPSENCOS_d_ff2_Y[2]), .A1(n4798), .B0(
FPSENCOS_d_ff_Yn[2]), .B1(n4800), .Y(n1903) );
AO22XLTS U3143 ( .A0(n4808), .A1(n2343), .B0(n4782), .B1(
FPSENCOS_d_ff3_sh_x_out[3]), .Y(n1998) );
AO22XLTS U3144 ( .A0(FPSENCOS_d_ff2_Y[3]), .A1(n4798), .B0(
FPSENCOS_d_ff_Yn[3]), .B1(n4795), .Y(n1901) );
AO22XLTS U3145 ( .A0(n2335), .A1(n4794), .B0(n4810), .B1(n2329), .Y(n1943)
);
AO22XLTS U3146 ( .A0(FPSENCOS_d_ff2_Y[31]), .A1(n4811), .B0(n4810), .B1(
n2321), .Y(n1845) );
AO22XLTS U3147 ( .A0(n4781), .A1(FPSENCOS_d_ff3_sh_x_out[12]), .B0(n4808),
.B1(n2332), .Y(n1980) );
AO22XLTS U3148 ( .A0(FPSENCOS_d_ff2_Y[12]), .A1(n4798), .B0(
FPSENCOS_d_ff_Yn[12]), .B1(n4795), .Y(n1883) );
AO22XLTS U3149 ( .A0(n4781), .A1(FPSENCOS_d_ff3_sh_x_out[10]), .B0(n4808),
.B1(n2333), .Y(n1984) );
AO22XLTS U3150 ( .A0(FPSENCOS_d_ff2_Y[10]), .A1(n4798), .B0(
FPSENCOS_d_ff_Yn[10]), .B1(n4795), .Y(n1887) );
AO22XLTS U3151 ( .A0(n4808), .A1(n2344), .B0(n4782), .B1(
FPSENCOS_d_ff3_sh_x_out[14]), .Y(n1976) );
AO22XLTS U3152 ( .A0(FPSENCOS_d_ff2_Y[14]), .A1(n4798), .B0(n2310), .B1(
n4800), .Y(n1879) );
AO22XLTS U3153 ( .A0(n2336), .A1(n4794), .B0(FPSENCOS_d_ff_Xn[11]), .B1(
n4795), .Y(n1983) );
AO22XLTS U3154 ( .A0(FPSENCOS_d_ff2_Y[11]), .A1(n4798), .B0(
FPSENCOS_d_ff_Yn[11]), .B1(n4800), .Y(n1885) );
AO22XLTS U3155 ( .A0(n4781), .A1(FPSENCOS_d_ff3_sh_x_out[8]), .B0(n4803),
.B1(n2326), .Y(n1988) );
AO22XLTS U3156 ( .A0(n2326), .A1(n4794), .B0(FPSENCOS_d_ff_Xn[8]), .B1(n4800), .Y(n1989) );
AO22XLTS U3157 ( .A0(n4803), .A1(FPSENCOS_d_ff2_Y[8]), .B0(n4799), .B1(
FPSENCOS_d_ff3_sh_y_out[8]), .Y(n1890) );
AO22XLTS U3158 ( .A0(FPSENCOS_d_ff2_Y[8]), .A1(n4798), .B0(
FPSENCOS_d_ff_Yn[8]), .B1(n4795), .Y(n1891) );
AO22XLTS U3159 ( .A0(FPSENCOS_d_ff2_Y[16]), .A1(n4801), .B0(
FPSENCOS_d_ff_Yn[16]), .B1(n4797), .Y(n1875) );
AO22XLTS U3160 ( .A0(FPSENCOS_d_ff2_Y[13]), .A1(n4798), .B0(n2311), .B1(
n4795), .Y(n1881) );
AO22XLTS U3161 ( .A0(n4781), .A1(FPSENCOS_d_ff3_sh_x_out[6]), .B0(n4803),
.B1(n2334), .Y(n1992) );
AO22XLTS U3162 ( .A0(n4803), .A1(FPSENCOS_d_ff2_Y[6]), .B0(n4868), .B1(
FPSENCOS_d_ff3_sh_y_out[6]), .Y(n1894) );
AO22XLTS U3163 ( .A0(FPSENCOS_d_ff2_Y[6]), .A1(n4798), .B0(
FPSENCOS_d_ff_Yn[6]), .B1(n4800), .Y(n1895) );
AO22XLTS U3164 ( .A0(n4781), .A1(FPSENCOS_d_ff3_sh_x_out[4]), .B0(n4803),
.B1(n2327), .Y(n1996) );
AO22XLTS U3165 ( .A0(n2327), .A1(n4794), .B0(n2308), .B1(n4810), .Y(n1997)
);
AO22XLTS U3166 ( .A0(n4808), .A1(FPSENCOS_d_ff2_Y[4]), .B0(n4868), .B1(
FPSENCOS_d_ff3_sh_y_out[4]), .Y(n1898) );
AO22XLTS U3167 ( .A0(FPSENCOS_d_ff2_Y[4]), .A1(n4798), .B0(
FPSENCOS_d_ff_Yn[4]), .B1(n4800), .Y(n1899) );
AO22XLTS U3168 ( .A0(FPSENCOS_d_ff2_Y[17]), .A1(n4801), .B0(n2312), .B1(
n4797), .Y(n1873) );
AO22XLTS U3169 ( .A0(FPSENCOS_d_ff2_Y[20]), .A1(n4801), .B0(n2313), .B1(
n4797), .Y(n1867) );
AO22XLTS U3170 ( .A0(FPSENCOS_d_ff2_Y[19]), .A1(n4801), .B0(n2314), .B1(
n4797), .Y(n1869) );
AO22XLTS U3171 ( .A0(n4812), .A1(FPSENCOS_d_ff3_sh_x_out[21]), .B0(n4803),
.B1(n2328), .Y(n1962) );
AO22XLTS U3172 ( .A0(n2328), .A1(n4794), .B0(FPSENCOS_d_ff_Xn[21]), .B1(
n4795), .Y(n1963) );
AO22XLTS U3173 ( .A0(FPSENCOS_d_ff2_Y[21]), .A1(n4801), .B0(
FPSENCOS_d_ff_Yn[21]), .B1(n4797), .Y(n1865) );
AO22XLTS U3174 ( .A0(FPSENCOS_d_ff2_Y[18]), .A1(n4801), .B0(
FPSENCOS_d_ff_Yn[18]), .B1(n4797), .Y(n1871) );
AO22XLTS U3175 ( .A0(FPSENCOS_d_ff2_Y[15]), .A1(n4801), .B0(
FPSENCOS_d_ff_Yn[15]), .B1(n4797), .Y(n1877) );
AO22XLTS U3176 ( .A0(FPSENCOS_d_ff2_Y[22]), .A1(n4801), .B0(
FPSENCOS_d_ff_Yn[22]), .B1(n4797), .Y(n1863) );
AOI2BB2XLTS U3177 ( .B0(n4126), .B1(FPADDSUB_Data_array_SWR[1]), .A0N(n2220),
.A1N(n4283), .Y(n4115) );
AO22XLTS U3178 ( .A0(FPSENCOS_d_ff2_Y[28]), .A1(n4811), .B0(
FPSENCOS_d_ff_Yn[28]), .B1(n4810), .Y(n1856) );
AO22XLTS U3179 ( .A0(FPSENCOS_d_ff2_Y[23]), .A1(n4801), .B0(
FPSENCOS_d_ff_Yn[23]), .B1(n4795), .Y(n1861) );
AOI2BB2XLTS U3180 ( .B0(n4805), .B1(n4792), .A0N(FPSENCOS_d_ff3_sh_x_out[29]), .A1N(n4803), .Y(n1945) );
AOI2BB2XLTS U3181 ( .B0(n4805), .B1(n4789), .A0N(FPSENCOS_d_ff3_sh_x_out[27]), .A1N(n4803), .Y(n1947) );
AO22XLTS U3182 ( .A0(n4812), .A1(FPSENCOS_d_ff3_sh_x_out[26]), .B0(n4803),
.B1(intadd_525_SUM_2_), .Y(n1948) );
AO22XLTS U3183 ( .A0(n4812), .A1(FPSENCOS_d_ff3_sh_x_out[25]), .B0(n4803),
.B1(intadd_525_SUM_1_), .Y(n1949) );
AO22XLTS U3184 ( .A0(n4812), .A1(FPSENCOS_d_ff3_sh_x_out[24]), .B0(n4803),
.B1(intadd_525_SUM_0_), .Y(n1950) );
AOI2BB2XLTS U3185 ( .B0(n4869), .B1(n4809), .A0N(FPSENCOS_d_ff3_sh_y_out[29]), .A1N(n4808), .Y(n1847) );
AOI2BB2XLTS U3186 ( .B0(n4805), .B1(n4804), .A0N(FPSENCOS_d_ff3_sh_y_out[27]), .A1N(n4803), .Y(n1849) );
AOI2BB2XLTS U3187 ( .B0(n4869), .B1(n4760), .A0N(FPSENCOS_d_ff3_LUT_out[23]),
.A1N(n4803), .Y(n2117) );
OAI211XLTS U3188 ( .A0(n4869), .A1(n5420), .B0(n4749), .C0(n4153), .Y(n2120)
);
OAI211XLTS U3189 ( .A0(n4869), .A1(n5419), .B0(n4148), .C0(n4153), .Y(n2126)
);
AO22XLTS U3190 ( .A0(n4743), .A1(busy), .B0(n4741), .B1(n2306), .Y(n2145) );
AOI2BB2XLTS U3191 ( .B0(n4736), .B1(n5359), .A0N(n5359), .A1N(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n4739) );
OR2X1TS U3192 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_Op_MX[27]), .Y(n2206) );
OR2X1TS U3193 ( .A(n2372), .B(n2373), .Y(n2222) );
OR2X1TS U3194 ( .A(n3992), .B(n3991), .Y(n2223) );
OR2X1TS U3195 ( .A(n3993), .B(n3991), .Y(n2224) );
OR3X2TS U3196 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(n5314), .C(
n3558), .Y(n2225) );
OAI21X2TS U3197 ( .A0(n4487), .A1(n4488), .B0(n4478), .Y(n2226) );
AOI21X2TS U3198 ( .A0(n4006), .A1(n5355), .B0(n4023), .Y(n2232) );
AOI22X1TS U3199 ( .A0(n4900), .A1(FPMULT_Op_MY[15]), .B0(n4942), .B1(
Data_2[15]), .Y(n2234) );
BUFX3TS U3200 ( .A(n3188), .Y(n5078) );
OR2X1TS U3201 ( .A(FPMULT_Op_MX[26]), .B(FPMULT_Op_MX[25]), .Y(n2237) );
BUFX3TS U3202 ( .A(n3531), .Y(n5445) );
NOR2X2TS U3203 ( .A(rst), .B(n4745), .Y(n3531) );
AOI222X2TS U3204 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[24]), .A1(
FPADDSUB_DMP_SFG[22]), .B0(FPADDSUB_DmP_mant_SFG_SWR[24]), .B1(n5087),
.C0(FPADDSUB_DMP_SFG[22]), .C1(n5087), .Y(n5040) );
INVX4TS U3205 ( .A(n5353), .Y(n2280) );
INVX2TS U3206 ( .A(DP_OP_500J224_126_4510_n32), .Y(n2281) );
INVX2TS U3207 ( .A(n4071), .Y(n2282) );
INVX2TS U3208 ( .A(n4071), .Y(n2283) );
BUFX4TS U3209 ( .A(n4805), .Y(n4869) );
INVX4TS U3210 ( .A(n2201), .Y(n4899) );
INVX2TS U3211 ( .A(FPADDSUB_left_right_SHT2), .Y(n2284) );
INVX2TS U3212 ( .A(n2284), .Y(n2285) );
INVX2TS U3213 ( .A(n2284), .Y(n2286) );
INVX2TS U3214 ( .A(n2220), .Y(n2287) );
INVX4TS U3215 ( .A(n2220), .Y(n2288) );
INVX2TS U3216 ( .A(n2225), .Y(n2290) );
INVX2TS U3217 ( .A(n2225), .Y(n2291) );
INVX2TS U3218 ( .A(n2225), .Y(n2292) );
OAI21XLTS U3219 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n2203), .B0(n4112),
.Y(n2130) );
INVX2TS U3220 ( .A(n2219), .Y(n2293) );
INVX4TS U3221 ( .A(n2219), .Y(n2294) );
AOI21X2TS U3222 ( .A0(n3545), .A1(n5266), .B0(n4026), .Y(n4139) );
AOI21X2TS U3223 ( .A0(n3545), .A1(n5355), .B0(n4031), .Y(n4080) );
AOI21X2TS U3224 ( .A0(n3545), .A1(n5347), .B0(n4033), .Y(n4127) );
AOI21X2TS U3225 ( .A0(n4006), .A1(n5347), .B0(n4036), .Y(n4113) );
CMPR32X4TS U3226 ( .A(FPMULT_Op_MX[5]), .B(n4901), .C(n3120), .CO(n3121),
.S(n3145) );
CLKINVX3TS U3227 ( .A(n4527), .Y(n4942) );
INVX3TS U3228 ( .A(n4527), .Y(n4528) );
INVX2TS U3229 ( .A(n5437), .Y(n4531) );
XOR2X1TS U3230 ( .A(n4497), .B(n3870), .Y(n3857) );
NOR2X2TS U3231 ( .A(n3885), .B(n2382), .Y(n3870) );
OAI21XLTS U3232 ( .A0(n5215), .A1(n3976), .B0(n3703), .Y(n1413) );
OA21X1TS U3233 ( .A0(n4442), .A1(n4441), .B0(n4440), .Y(n4458) );
OA21X1TS U3234 ( .A0(n4493), .A1(n4492), .B0(n4491), .Y(n4507) );
AOI21X4TS U3235 ( .A0(FPADDSUB_DMP_SFG[8]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[10]), .B0(n3991), .Y(n4056) );
AOI21X4TS U3236 ( .A0(FPADDSUB_DMP_SFG[10]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[12]), .B0(n4119), .Y(n4208) );
AOI21X4TS U3237 ( .A0(FPADDSUB_DMP_SFG[13]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[15]), .B0(n4319), .Y(n4330) );
AOI222X4TS U3238 ( .A0(n4780), .A1(FPSENCOS_d_ff2_Z[9]), .B0(n3807), .B1(
FPSENCOS_d_ff_Zn[9]), .C0(n3801), .C1(FPSENCOS_d_ff1_Z[9]), .Y(n3800)
);
AOI222X4TS U3239 ( .A0(n4811), .A1(FPSENCOS_d_ff2_Z[7]), .B0(n3807), .B1(
FPSENCOS_d_ff_Zn[7]), .C0(n3801), .C1(FPSENCOS_d_ff1_Z[7]), .Y(n3802)
);
AOI222X4TS U3240 ( .A0(n4780), .A1(FPSENCOS_d_ff2_Z[12]), .B0(n3807), .B1(
FPSENCOS_d_ff_Zn[12]), .C0(n3801), .C1(FPSENCOS_d_ff1_Z[12]), .Y(n3799) );
AOI222X4TS U3241 ( .A0(n4780), .A1(FPSENCOS_d_ff2_Z[11]), .B0(n3807), .B1(
FPSENCOS_d_ff_Zn[11]), .C0(n3801), .C1(FPSENCOS_d_ff1_Z[11]), .Y(n3795) );
OAI21XLTS U3242 ( .A0(n4145), .A1(n4107), .B0(n4106), .Y(n1731) );
OAI21X1TS U3243 ( .A0(FPADDSUB_DMP_SFG[14]), .A1(n5256), .B0(n4326), .Y(
n4336) );
OAI21X1TS U3244 ( .A0(FPADDSUB_DMP_SFG[21]), .A1(n5330), .B0(n5005), .Y(
n5088) );
NOR2X2TS U3245 ( .A(n5270), .B(n5173), .Y(n3832) );
NOR2X2TS U3246 ( .A(FPSENCOS_d_ff2_Y[29]), .B(n4807), .Y(n4806) );
OAI21X1TS U3247 ( .A0(FPADDSUB_DMP_SFG[13]), .A1(n5249), .B0(n4317), .Y(
n4327) );
CLKINVX1TS U3248 ( .A(n4012), .Y(n4013) );
NOR2X2TS U3249 ( .A(n5269), .B(n3885), .Y(n4518) );
NOR4X2TS U3250 ( .A(n5162), .B(n4677), .C(n4663), .D(n5156), .Y(n4664) );
NOR4X1TS U3251 ( .A(FPMULT_P_Sgf[11]), .B(FPMULT_P_Sgf[6]), .C(
FPMULT_P_Sgf[7]), .D(FPMULT_P_Sgf[8]), .Y(n3590) );
NOR2X2TS U3252 ( .A(n5159), .B(n5261), .Y(n4497) );
NOR2X2TS U3253 ( .A(n5192), .B(n2398), .Y(n4481) );
NOR4X1TS U3254 ( .A(FPMULT_Op_MY[14]), .B(FPMULT_Op_MY[15]), .C(
FPMULT_Op_MY[16]), .D(FPMULT_Op_MY[17]), .Y(n4933) );
NOR2X2TS U3255 ( .A(FPMULT_FS_Module_state_reg[0]), .B(
FPMULT_FS_Module_state_reg[1]), .Y(n3599) );
BUFX4TS U3256 ( .A(n5502), .Y(n5469) );
BUFX4TS U3257 ( .A(n5502), .Y(n5499) );
BUFX4TS U3258 ( .A(n5502), .Y(n5500) );
BUFX4TS U3259 ( .A(n5502), .Y(n5501) );
BUFX4TS U3260 ( .A(n5504), .Y(n5505) );
BUFX4TS U3261 ( .A(n5502), .Y(n5484) );
BUFX4TS U3262 ( .A(n5477), .Y(n5491) );
OAI21X2TS U3263 ( .A0(n4436), .A1(n4437), .B0(n4427), .Y(n4452) );
BUFX4TS U3264 ( .A(n3388), .Y(n5482) );
BUFX4TS U3265 ( .A(n3388), .Y(n5483) );
BUFX4TS U3266 ( .A(n3388), .Y(n5472) );
BUFX4TS U3267 ( .A(n3388), .Y(n5480) );
BUFX4TS U3268 ( .A(n5512), .Y(n5503) );
BUFX4TS U3269 ( .A(n5512), .Y(n5506) );
OAI2BB2XLTS U3270 ( .B0(n2219), .B1(n4283), .A0N(n2287), .A1N(n4282), .Y(
n4284) );
OAI21X2TS U3271 ( .A0(n5165), .A1(n4065), .B0(n4044), .Y(n4282) );
OAI21XLTS U3272 ( .A0(n3832), .A1(n3831), .B0(n4447), .Y(n3830) );
NOR2X2TS U3273 ( .A(n5168), .B(n5262), .Y(n4447) );
NOR2X2TS U3274 ( .A(n5255), .B(n5164), .Y(intadd_519_A_7_) );
BUFX4TS U3275 ( .A(n2200), .Y(n5512) );
BUFX4TS U3276 ( .A(n2200), .Y(n5504) );
BUFX4TS U3277 ( .A(n5511), .Y(n5508) );
BUFX4TS U3278 ( .A(n5511), .Y(n5509) );
BUFX4TS U3279 ( .A(n5513), .Y(n5510) );
BUFX4TS U3280 ( .A(n5417), .Y(n5105) );
BUFX4TS U3281 ( .A(n5442), .Y(n5458) );
BUFX4TS U3282 ( .A(n3389), .Y(n5454) );
BUFX4TS U3283 ( .A(n3390), .Y(n5453) );
BUFX4TS U3284 ( .A(n5467), .Y(n5440) );
NOR2X2TS U3285 ( .A(n5158), .B(n3837), .Y(n4429) );
NOR2X2TS U3286 ( .A(n5169), .B(n3876), .Y(n4480) );
BUFX4TS U3287 ( .A(n5448), .Y(n5462) );
BUFX4TS U3288 ( .A(n5465), .Y(n5443) );
BUFX4TS U3289 ( .A(n3389), .Y(n5460) );
BUFX4TS U3290 ( .A(n3390), .Y(n5459) );
BUFX3TS U3291 ( .A(n5445), .Y(n2295) );
BUFX4TS U3292 ( .A(n5455), .Y(n5447) );
BUFX4TS U3293 ( .A(n2295), .Y(n5441) );
BUFX4TS U3294 ( .A(n5445), .Y(n5448) );
BUFX4TS U3295 ( .A(n5447), .Y(n5449) );
BUFX3TS U3296 ( .A(n3531), .Y(n3390) );
XOR2XLTS U3297 ( .A(n4494), .B(n4519), .Y(n4495) );
AOI21X2TS U3298 ( .A0(n3856), .A1(n3855), .B0(n3881), .Y(n4494) );
BUFX4TS U3299 ( .A(n4794), .Y(n4801) );
BUFX4TS U3300 ( .A(n3389), .Y(n5465) );
BUFX4TS U3301 ( .A(n3390), .Y(n5442) );
BUFX4TS U3302 ( .A(n5461), .Y(n5446) );
BUFX4TS U3303 ( .A(n5445), .Y(n5467) );
AOI21X2TS U3304 ( .A0(n3868), .A1(n3867), .B0(n3866), .Y(n4512) );
INVX2TS U3305 ( .A(n4484), .Y(n3866) );
AOI21X2TS U3306 ( .A0(n3907), .A1(FPADDSUB_Data_array_SWR[20]), .B0(n3903),
.Y(n5115) );
AOI21X2TS U3307 ( .A0(n3907), .A1(FPADDSUB_Data_array_SWR[21]), .B0(n3903),
.Y(n5150) );
AOI21X2TS U3308 ( .A0(FPADDSUB_Data_array_SWR[20]), .A1(n3740), .B0(n3735),
.Y(n3916) );
INVX2TS U3309 ( .A(n4876), .Y(n2296) );
INVX2TS U3310 ( .A(n2296), .Y(n2297) );
AOI21X2TS U3311 ( .A0(n3907), .A1(FPADDSUB_Data_array_SWR[19]), .B0(n3903),
.Y(n3919) );
INVX2TS U3312 ( .A(n2203), .Y(n2298) );
NAND2X2TS U3313 ( .A(n5172), .B(n5313), .Y(n4766) );
BUFX3TS U3314 ( .A(n5519), .Y(n5502) );
BUFX4TS U3315 ( .A(n5519), .Y(n5477) );
BUFX4TS U3316 ( .A(n5519), .Y(n5475) );
BUFX4TS U3317 ( .A(n5473), .Y(n5489) );
OAI21X2TS U3318 ( .A0(n5250), .A1(n4048), .B0(n4047), .Y(n4094) );
BUFX4TS U3319 ( .A(n3537), .Y(n4048) );
OAI21XLTS U3320 ( .A0(n4443), .A1(n4470), .B0(n4445), .Y(n3819) );
AOI21X2TS U3321 ( .A0(n3817), .A1(n3816), .B0(n3842), .Y(n4443) );
AOI31X1TS U3322 ( .A0(n4930), .A1(n2197), .A2(mult_x_309_n58), .B0(n3410),
.Y(n4679) );
NOR2X2TS U3323 ( .A(n2391), .B(n5251), .Y(mult_x_309_n58) );
NOR2X2TS U3324 ( .A(n4669), .B(n4663), .Y(mult_x_309_n66) );
BUFX4TS U3325 ( .A(n4769), .Y(n4771) );
NAND3X2TS U3326 ( .A(n4924), .B(n4902), .C(n4442), .Y(n4437) );
BUFX4TS U3327 ( .A(n4303), .Y(n4873) );
BUFX4TS U3328 ( .A(n4303), .Y(n4818) );
INVX2TS U3329 ( .A(n3366), .Y(n2301) );
NAND2X4TS U3330 ( .A(n3561), .B(n4941), .Y(n4530) );
BUFX4TS U3331 ( .A(n4805), .Y(n4787) );
NOR3BX2TS U3332 ( .AN(n4725), .B(n4745), .C(ready_add_subt), .Y(n4748) );
INVX2TS U3333 ( .A(n3365), .Y(n2302) );
INVX4TS U3334 ( .A(n3578), .Y(n2303) );
BUFX4TS U3335 ( .A(FPADDSUB_Shift_reg_FLAGS_7[2]), .Y(n5093) );
NOR3XLTS U3336 ( .A(n4930), .B(FPMULT_Op_MY[29]), .C(n2304), .Y(n4934) );
INVX2TS U3337 ( .A(n2233), .Y(n2304) );
INVX2TS U3338 ( .A(n2249), .Y(n2305) );
INVX2TS U3339 ( .A(n2239), .Y(n2306) );
NOR3XLTS U3340 ( .A(FPMULT_Op_MX[20]), .B(FPMULT_Op_MX[30]), .C(n2307), .Y(
n4919) );
INVX2TS U3341 ( .A(n2238), .Y(n2307) );
INVX2TS U3342 ( .A(n2266), .Y(n2308) );
INVX2TS U3343 ( .A(n2270), .Y(n2309) );
INVX2TS U3344 ( .A(n2271), .Y(n2310) );
INVX2TS U3345 ( .A(n2215), .Y(n2311) );
INVX2TS U3346 ( .A(n2272), .Y(n2312) );
INVX2TS U3347 ( .A(n2274), .Y(n2313) );
INVX2TS U3348 ( .A(n2273), .Y(n2314) );
INVX2TS U3349 ( .A(n2277), .Y(n2315) );
INVX2TS U3350 ( .A(n2202), .Y(n2316) );
INVX2TS U3351 ( .A(n2276), .Y(n2317) );
INVX2TS U3352 ( .A(n2275), .Y(n2318) );
INVX2TS U3353 ( .A(n2231), .Y(n2319) );
INVX2TS U3354 ( .A(n2205), .Y(n2320) );
INVX2TS U3355 ( .A(n2248), .Y(n2321) );
INVX2TS U3356 ( .A(n2240), .Y(n2322) );
INVX2TS U3357 ( .A(n2230), .Y(n2323) );
INVX2TS U3358 ( .A(n2264), .Y(n2324) );
INVX2TS U3359 ( .A(n2262), .Y(n2325) );
INVX2TS U3360 ( .A(n2263), .Y(n2326) );
INVX2TS U3361 ( .A(n2213), .Y(n2327) );
INVX2TS U3362 ( .A(n2265), .Y(n2328) );
INVX2TS U3363 ( .A(n2209), .Y(n2329) );
INVX2TS U3364 ( .A(n2258), .Y(n2330) );
INVX2TS U3365 ( .A(n2259), .Y(n2331) );
INVX2TS U3366 ( .A(n2261), .Y(n2332) );
INVX2TS U3367 ( .A(n2260), .Y(n2333) );
INVX2TS U3368 ( .A(n2212), .Y(n2334) );
INVX2TS U3369 ( .A(n2257), .Y(n2335) );
INVX2TS U3370 ( .A(n2256), .Y(n2336) );
INVX2TS U3371 ( .A(n2255), .Y(n2337) );
INVX2TS U3372 ( .A(n2214), .Y(n2338) );
INVX2TS U3373 ( .A(n2267), .Y(n2339) );
INVX2TS U3374 ( .A(n2269), .Y(n2340) );
INVX2TS U3375 ( .A(n2268), .Y(n2341) );
INVX2TS U3376 ( .A(n2253), .Y(n2342) );
INVX2TS U3377 ( .A(n2252), .Y(n2343) );
INVX2TS U3378 ( .A(n2254), .Y(n2344) );
INVX2TS U3379 ( .A(n2236), .Y(n2345) );
BUFX4TS U3380 ( .A(n3721), .Y(n5107) );
NOR2XLTS U3381 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n3749), .Y(n3721)
);
INVX2TS U3382 ( .A(n2247), .Y(n2346) );
INVX2TS U3383 ( .A(n2208), .Y(n2347) );
INVX2TS U3384 ( .A(n2246), .Y(n2348) );
INVX2TS U3385 ( .A(n2227), .Y(n2349) );
INVX2TS U3386 ( .A(n2250), .Y(n2350) );
INVX2TS U3387 ( .A(n2251), .Y(n2351) );
INVX2TS U3388 ( .A(n2279), .Y(n2352) );
INVX2TS U3389 ( .A(n2211), .Y(n2353) );
INVX2TS U3390 ( .A(n2245), .Y(n2354) );
INVX2TS U3391 ( .A(n2278), .Y(n2355) );
INVX2TS U3392 ( .A(n2210), .Y(n2356) );
INVX2TS U3393 ( .A(n2244), .Y(n2357) );
NOR4X2TS U3394 ( .A(n4687), .B(n4693), .C(n5520), .D(n5164), .Y(n4688) );
AOI21X2TS U3395 ( .A0(n4006), .A1(n5264), .B0(n4028), .Y(n4140) );
CLKINVX3TS U3396 ( .A(n5361), .Y(n5103) );
AOI21X2TS U3397 ( .A0(n3545), .A1(n5264), .B0(n4040), .Y(n4091) );
BUFX4TS U3398 ( .A(n5225), .Y(n3716) );
BUFX4TS U3399 ( .A(n4888), .Y(n4278) );
AOI21X2TS U3400 ( .A0(n3545), .A1(n5282), .B0(n4032), .Y(n4125) );
BUFX4TS U3401 ( .A(n4155), .Y(n4199) );
BUFX4TS U3402 ( .A(n4874), .Y(n4299) );
BUFX4TS U3403 ( .A(n4874), .Y(n4815) );
BUFX4TS U3404 ( .A(n4254), .Y(n4273) );
BUFX4TS U3405 ( .A(n4304), .Y(n4841) );
BUFX4TS U3406 ( .A(n4650), .Y(n4639) );
CMPR32X4TS U3407 ( .A(FPMULT_Op_MX[15]), .B(DP_OP_501J224_127_5235_n411),
.C(n2814), .CO(n2815), .S(n2897) );
INVX3TS U3408 ( .A(n3790), .Y(n4797) );
INVX3TS U3409 ( .A(n3790), .Y(n4800) );
INVX3TS U3410 ( .A(n3790), .Y(n4795) );
INVX3TS U3411 ( .A(n3545), .Y(n4065) );
INVX3TS U3412 ( .A(n2396), .Y(n4999) );
OR4X4TS U3413 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Overflow_flag_A), .C(n2358), .D(n4994), .Y(n2396) );
CMPR32X4TS U3414 ( .A(FPMULT_Op_MX[13]), .B(n2197), .C(n2813), .CO(n2823),
.S(DP_OP_500J224_126_4510_n32) );
INVX3TS U3415 ( .A(n5361), .Y(n5104) );
INVX3TS U3416 ( .A(n5361), .Y(n5098) );
CLKINVX3TS U3417 ( .A(n5120), .Y(n5132) );
INVX3TS U3418 ( .A(n5120), .Y(n5099) );
INVX3TS U3419 ( .A(n5120), .Y(n5039) );
AOI222X1TS U3420 ( .A0(n2303), .A1(n5233), .B0(n2199), .B1(n3368), .C0(n5369), .C1(n3652), .Y(n1621) );
INVX3TS U3421 ( .A(n4796), .Y(n4799) );
OAI32X1TS U3422 ( .A0(n3165), .A1(n3139), .A2(DP_OP_502J224_128_4510_n27),
.B0(n3094), .B1(n3093), .Y(n3095) );
OAI32X1TS U3423 ( .A0(n3165), .A1(n3164), .A2(n2371), .B0(n3163), .B1(n3093),
.Y(DP_OP_502J224_128_4510_n76) );
NOR3X2TS U3424 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .Y(n3546) );
NOR2X1TS U3425 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .Y(n3392) );
INVX2TS U3426 ( .A(n2228), .Y(n2358) );
INVX2TS U3427 ( .A(n2216), .Y(n2359) );
INVX2TS U3428 ( .A(n2229), .Y(n2360) );
INVX2TS U3429 ( .A(n2207), .Y(n2361) );
INVX2TS U3430 ( .A(n3105), .Y(n2362) );
INVX2TS U3431 ( .A(n2362), .Y(n2363) );
ADDHXLTS U3432 ( .A(FPMULT_Op_MY[6]), .B(n4922), .CO(n3089), .S(n3105) );
INVX2TS U3433 ( .A(n2217), .Y(n2364) );
INVX2TS U3434 ( .A(n2221), .Y(n2365) );
INVX2TS U3435 ( .A(n2204), .Y(n2366) );
INVX2TS U3436 ( .A(n2235), .Y(n2367) );
OAI211XLTS U3437 ( .A0(n5381), .A1(n3655), .B0(n3624), .C0(n3623), .Y(n1524)
);
NAND3X2TS U3438 ( .A(FPADDSUB_shift_value_SHT2_EWR[2]), .B(
FPADDSUB_shift_value_SHT2_EWR[3]), .C(n5176), .Y(n5029) );
NOR2X4TS U3439 ( .A(n5176), .B(n5312), .Y(n5026) );
INVX2TS U3440 ( .A(n2242), .Y(n2368) );
NOR2X1TS U3441 ( .A(FPMULT_Sgf_normalized_result[1]), .B(
FPMULT_Sgf_normalized_result[0]), .Y(n4944) );
INVX2TS U3442 ( .A(n2241), .Y(n2369) );
AOI32X1TS U3443 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[15]), .A1(n3997), .A2(n3996),
.B0(FPADDSUB_Raw_mant_NRM_SWR[19]), .B1(n3997), .Y(n3998) );
NOR3XLTS U3444 ( .A(FPADDSUB_Raw_mant_NRM_SWR[21]), .B(
FPADDSUB_Raw_mant_NRM_SWR[20]), .C(FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(
n4392) );
OAI221XLTS U3445 ( .A0(n5346), .A1(FPADDSUB_intDY_EWSW[28]), .B0(n5324),
.B1(FPADDSUB_intDY_EWSW[2]), .C0(n3483), .Y(n3484) );
OAI211XLTS U3446 ( .A0(n4310), .A1(n5424), .B0(n4167), .C0(n4166), .Y(n1839)
);
OAI221X1TS U3447 ( .A0(n5320), .A1(FPADDSUB_intDY_EWSW[10]), .B0(n5222),
.B1(FPADDSUB_intDY_EWSW[6]), .C0(n3490), .Y(n3493) );
OAI32X1TS U3448 ( .A0(n2706), .A1(n2693), .A2(mult_x_313_n74), .B0(n2669),
.B1(n2658), .Y(n2673) );
OAI32X1TS U3449 ( .A0(n2706), .A1(n2675), .A2(mult_x_313_n74), .B0(n2674),
.B1(n2658), .Y(n2686) );
OAI32X1TS U3450 ( .A0(n2706), .A1(n2968), .A2(mult_x_313_n74), .B0(n2659),
.B1(n2658), .Y(n2668) );
INVX2TS U3451 ( .A(n2650), .Y(n2370) );
OAI21XLTS U3452 ( .A0(n2370), .A1(n2733), .B0(n2651), .Y(mult_x_313_n65) );
INVX2TS U3453 ( .A(n2650), .Y(mult_x_313_n74) );
INVX2TS U3454 ( .A(DP_OP_502J224_128_4510_n32), .Y(n2371) );
OAI32X1TS U3455 ( .A0(n3165), .A1(n3143), .A2(DP_OP_502J224_128_4510_n27),
.B0(n3098), .B1(n3093), .Y(n3107) );
OAI32X1TS U3456 ( .A0(n3165), .A1(n3102), .A2(DP_OP_502J224_128_4510_n27),
.B0(n3101), .B1(n3093), .Y(n3171) );
INVX2TS U3457 ( .A(DP_OP_502J224_128_4510_n32), .Y(
DP_OP_502J224_128_4510_n27) );
OAI221X1TS U3458 ( .A0(n5221), .A1(FPADDSUB_intDY_EWSW[21]), .B0(n5327),
.B1(FPADDSUB_intDY_EWSW[8]), .C0(n3480), .Y(n3487) );
OAI221X1TS U3459 ( .A0(n5344), .A1(FPADDSUB_intDY_EWSW[29]), .B0(n5224),
.B1(FPADDSUB_intDY_EWSW[18]), .C0(n3488), .Y(n3495) );
XOR2X1TS U3460 ( .A(n4447), .B(n3831), .Y(n3818) );
NOR2X2TS U3461 ( .A(n3846), .B(n4421), .Y(n3831) );
NOR2X1TS U3462 ( .A(n3080), .B(n3079), .Y(DP_OP_501J224_127_5235_n53) );
NOR3X1TS U3463 ( .A(n5291), .B(n5195), .C(n3589), .Y(n3395) );
NAND2X2TS U3464 ( .A(FPMULT_FS_Module_state_reg[3]), .B(n5175), .Y(n3589) );
AOI211X1TS U3465 ( .A0(FPADDSUB_Data_array_SWR[1]), .A1(n3719), .B0(n3725),
.C0(n3724), .Y(n5114) );
NOR4X2TS U3466 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n3547) );
INVX2TS U3467 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[10]), .Y(
n2492) );
BUFX4TS U3468 ( .A(n5034), .Y(n4539) );
NOR4X1TS U3469 ( .A(Data_2[2]), .B(Data_2[10]), .C(Data_2[12]), .D(
Data_2[14]), .Y(n5436) );
NOR4X1TS U3470 ( .A(Data_2[17]), .B(Data_2[16]), .C(Data_2[8]), .D(n3310),
.Y(n5434) );
NOR4X1TS U3471 ( .A(Data_2[7]), .B(Data_2[9]), .C(Data_2[11]), .D(Data_2[6]),
.Y(n5435) );
NOR2X2TS U3472 ( .A(n5270), .B(n3846), .Y(n4469) );
OAI21XLTS U3473 ( .A0(n3871), .A1(n3870), .B0(n4497), .Y(n3869) );
NOR2X2TS U3474 ( .A(n5269), .B(n5192), .Y(n3871) );
OAI33X1TS U3475 ( .A0(FPSENCOS_d_ff1_shift_region_flag_out[1]), .A1(
FPSENCOS_d_ff1_operation_out), .A2(n5357), .B0(n5231), .B1(n5178),
.B2(FPSENCOS_d_ff1_shift_region_flag_out[0]), .Y(n4883) );
NOR4X1TS U3476 ( .A(FPMULT_P_Sgf[12]), .B(FPMULT_P_Sgf[10]), .C(
FPMULT_P_Sgf[14]), .D(FPMULT_P_Sgf[9]), .Y(n3591) );
NOR2X2TS U3477 ( .A(FPSENCOS_d_ff2_Y[27]), .B(intadd_524_n1), .Y(n4802) );
NOR2X2TS U3478 ( .A(FPADDSUB_Raw_mant_NRM_SWR[7]), .B(
FPADDSUB_Raw_mant_NRM_SWR[6]), .Y(n4370) );
NOR2XLTS U3479 ( .A(n2206), .B(n2237), .Y(n4920) );
OAI21XLTS U3480 ( .A0(n4429), .A1(n3369), .B0(n4430), .Y(n3370) );
NOR2X2TS U3481 ( .A(n5173), .B(n2431), .Y(n4430) );
NOR2X2TS U3482 ( .A(n4693), .B(n5254), .Y(mult_x_312_n53) );
NOR2X2TS U3483 ( .A(n5188), .B(n5251), .Y(mult_x_309_n52) );
OAI21XLTS U3484 ( .A0(n4466), .A1(n4463), .B0(n4464), .Y(n3834) );
AOI21X2TS U3485 ( .A0(n3829), .A1(n3828), .B0(n3827), .Y(n4463) );
ADDHX1TS U3486 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[10]), .B(n3203),
.CO(n3202), .S(n4604) );
AOI211X1TS U3487 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n5321), .B0(n3465),
.C0(n3466), .Y(n3457) );
ADDFHX2TS U3488 ( .A(n2593), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[8]), .CI(
n2592), .CO(n2590), .S(n4598) );
ADDFHX2TS U3489 ( .A(n2577), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[4]), .CI(n2576), .CO(n2574), .S(n4563) );
INVX2TS U3490 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[4]), .Y(n2463)
);
INVX2TS U3491 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[7]), .Y(n2479)
);
CMPR32X4TS U3492 ( .A(n4907), .B(n2196), .C(n3082), .CO(n3084), .S(n3166) );
NOR2X2TS U3493 ( .A(n4313), .B(n4697), .Y(mult_x_312_n38) );
AOI22X2TS U3494 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[13]), .A1(
FPADDSUB_DMP_SFG[11]), .B0(n5185), .B1(n5247), .Y(n4204) );
NOR2BX2TS U3495 ( .AN(n4680), .B(n4668), .Y(mult_x_309_n38) );
OAI21X1TS U3496 ( .A0(n5342), .A1(n3749), .B0(n3748), .Y(n3750) );
OAI21X1TS U3497 ( .A0(n5333), .A1(n3749), .B0(n3748), .Y(n3732) );
NOR2X2TS U3498 ( .A(n5177), .B(n3748), .Y(n5014) );
NAND2X2TS U3499 ( .A(FPADDSUB_bit_shift_SHT2), .B(
FPADDSUB_shift_value_SHT2_EWR[3]), .Y(n3748) );
OAI211XLTS U3500 ( .A0(n4239), .A1(n5403), .B0(n4230), .C0(n4229), .Y(n1922)
);
OAI211XLTS U3501 ( .A0(n4290), .A1(n5397), .B0(n4227), .C0(n4226), .Y(n1928)
);
OAI211XLTS U3502 ( .A0(n4239), .A1(n5398), .B0(n4225), .C0(n4224), .Y(n1927)
);
OAI211XLTS U3503 ( .A0(n4239), .A1(n5402), .B0(n4217), .C0(n4216), .Y(n1923)
);
OAI211XLTS U3504 ( .A0(n4290), .A1(n5399), .B0(n4215), .C0(n4214), .Y(n1926)
);
OAI211XLTS U3505 ( .A0(n4310), .A1(n5405), .B0(n4185), .C0(n4184), .Y(n1920)
);
OAI211XLTS U3506 ( .A0(n4310), .A1(n5396), .B0(n4183), .C0(n4182), .Y(n1929)
);
OAI211XLTS U3507 ( .A0(n4310), .A1(n5400), .B0(n4238), .C0(n4237), .Y(n1925)
);
OAI211XLTS U3508 ( .A0(n4310), .A1(n4202), .B0(n4201), .C0(n4200), .Y(n1918)
);
OAI211XLTS U3509 ( .A0(n4310), .A1(n5426), .B0(n4193), .C0(n4192), .Y(n1835)
);
OAI211XLTS U3510 ( .A0(n4310), .A1(n5432), .B0(n4191), .C0(n4190), .Y(n1818)
);
NOR3X1TS U3511 ( .A(n3532), .B(FPMULT_FS_Module_state_reg[0]), .C(
FPMULT_FS_Module_state_reg[1]), .Y(n3336) );
NAND2X2TS U3512 ( .A(FPMULT_FS_Module_state_reg[2]), .B(n5263), .Y(n3532) );
AOI222X4TS U3513 ( .A0(n4886), .A1(cordic_result[4]), .B0(n3812), .B1(
FPSENCOS_d_ff_Yn[4]), .C0(n3774), .C1(n2308), .Y(n3692) );
BUFX4TS U3514 ( .A(n5477), .Y(n5494) );
BUFX4TS U3515 ( .A(n5499), .Y(n5474) );
BUFX4TS U3516 ( .A(n5473), .Y(n5493) );
BUFX4TS U3517 ( .A(n5502), .Y(n5496) );
BUFX4TS U3518 ( .A(n5485), .Y(n5495) );
AOI222X4TS U3519 ( .A0(n4886), .A1(cordic_result[6]), .B0(n3812), .B1(
FPSENCOS_d_ff_Yn[6]), .C0(n3774), .C1(FPSENCOS_d_ff_Xn[6]), .Y(n3694)
);
AOI222X4TS U3520 ( .A0(n4886), .A1(cordic_result[5]), .B0(n3812), .B1(
FPSENCOS_d_ff_Yn[5]), .C0(n3774), .C1(FPSENCOS_d_ff_Xn[5]), .Y(n3693)
);
AOI22X2TS U3521 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[12]), .A1(
FPADDSUB_DMP_SFG[10]), .B0(n5183), .B1(n5244), .Y(n4117) );
XOR2X1TS U3522 ( .A(FPADDSUB_DmP_mant_SFG_SWR[1]), .B(n5043), .Y(n5044) );
AOI22X2TS U3523 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[10]), .A1(
FPADDSUB_DMP_SFG[8]), .B0(n2388), .B1(n5241), .Y(n3989) );
NOR2XLTS U3524 ( .A(FPMULT_FSM_selector_B[1]), .B(FPMULT_Op_MY[23]), .Y(
n4408) );
NOR4X2TS U3525 ( .A(n4421), .B(n2377), .C(n5168), .D(n5158), .Y(n4423) );
INVX2TS U3526 ( .A(FPMULT_Op_MX[8]), .Y(n4421) );
NOR4X2TS U3527 ( .A(n2415), .B(n2398), .C(n5159), .D(n5169), .Y(n4474) );
OAI21XLTS U3528 ( .A0(n5222), .A1(n3976), .B0(n3695), .Y(n1383) );
OAI21XLTS U3529 ( .A0(n5220), .A1(n3976), .B0(n3697), .Y(n1271) );
OAI21XLTS U3530 ( .A0(n5223), .A1(n3976), .B0(n3698), .Y(n1395) );
OAI21XLTS U3531 ( .A0(n5221), .A1(n3976), .B0(n3699), .Y(n1398) );
OAI21XLTS U3532 ( .A0(n5224), .A1(n3976), .B0(n3700), .Y(n1401) );
BUFX4TS U3533 ( .A(n3981), .Y(n3976) );
NOR4X2TS U3534 ( .A(n4669), .B(n2411), .C(n5248), .D(n5156), .Y(
mult_x_309_n42) );
NOR4X2TS U3535 ( .A(n4687), .B(n5157), .C(n5163), .D(n4365), .Y(
mult_x_312_n42) );
NOR2X1TS U3536 ( .A(n2731), .B(n2730), .Y(mult_x_313_n56) );
AOI2BB2X4TS U3537 ( .B0(n2980), .B1(n2710), .A0N(n2710), .A1N(n2980), .Y(
n2730) );
NOR2X1TS U3538 ( .A(n2362), .B(n3168), .Y(DP_OP_502J224_128_4510_n57) );
AOI2BB2X4TS U3539 ( .B0(n3121), .B1(n3142), .A0N(n3142), .A1N(n3121), .Y(
n3168) );
BUFX4TS U3540 ( .A(n4155), .Y(n4242) );
BUFX4TS U3541 ( .A(n4888), .Y(n4272) );
AOI22X2TS U3542 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[6]), .A1(n5238), .B0(
FPADDSUB_DMP_SFG[4]), .B1(n5181), .Y(n3668) );
OAI21XLTS U3543 ( .A0(n2893), .A1(n2866), .B0(n2863), .Y(n2862) );
NOR2X4TS U3544 ( .A(FPMULT_Op_MY[17]), .B(n2852), .Y(n2893) );
BUFX4TS U3545 ( .A(n4254), .Y(n4279) );
AOI22X2TS U3546 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[11]), .A1(
FPADDSUB_DMP_SFG[9]), .B0(n2387), .B1(n5243), .Y(n4052) );
AOI22X2TS U3547 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[22]), .A1(n5288), .B0(
FPADDSUB_DMP_SFG[20]), .B1(n5204), .Y(n5085) );
AOI22X2TS U3548 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[5]), .A1(n5236), .B0(
FPADDSUB_DMP_SFG[3]), .B1(n5180), .Y(n3661) );
AOI222X4TS U3549 ( .A0(n3946), .A1(cordic_result[8]), .B0(n3812), .B1(
FPSENCOS_d_ff_Yn[8]), .C0(n3774), .C1(FPSENCOS_d_ff_Xn[8]), .Y(n3776)
);
BUFX4TS U3550 ( .A(n3812), .Y(n3952) );
AOI211X1TS U3551 ( .A0(n5069), .A1(n5063), .B0(n5062), .C0(n5078), .Y(n5064)
);
AOI22X2TS U3552 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[14]), .A1(n5246), .B0(
FPADDSUB_DMP_SFG[12]), .B1(n5184), .Y(n5069) );
AOI222X1TS U3553 ( .A0(n4780), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n3686), .B1(
FPSENCOS_d_ff_Zn[31]), .C0(n3792), .C1(FPSENCOS_d_ff1_Z[31]), .Y(n3684) );
AOI222X4TS U3554 ( .A0(n4780), .A1(FPSENCOS_d_ff2_Z[8]), .B0(n3807), .B1(
FPSENCOS_d_ff_Zn[8]), .C0(n3801), .C1(FPSENCOS_d_ff1_Z[8]), .Y(n3791)
);
BUFX4TS U3555 ( .A(n3636), .Y(n4780) );
INVX3TS U3556 ( .A(n5417), .Y(n5100) );
BUFX3TS U3557 ( .A(n3531), .Y(n3389) );
INVX3TS U3558 ( .A(n5153), .Y(n5147) );
NOR3XLTS U3559 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Overflow_flag_A), .C(n4994), .Y(n4995) );
OAI211XLTS U3560 ( .A0(n5369), .A1(n3655), .B0(n3627), .C0(n3626), .Y(n1527)
);
OAI211XLTS U3561 ( .A0(n4310), .A1(n5407), .B0(n4169), .C0(n4168), .Y(n1910)
);
AOI222X4TS U3562 ( .A0(n4811), .A1(FPSENCOS_d_ff2_Z[0]), .B0(n3801), .B1(
FPSENCOS_d_ff1_Z[0]), .C0(FPSENCOS_d_ff_Zn[0]), .C1(n4810), .Y(n3656)
);
AOI222X4TS U3563 ( .A0(n4811), .A1(FPSENCOS_d_ff2_Z[2]), .B0(n4810), .B1(
FPSENCOS_d_ff_Zn[2]), .C0(n3801), .C1(FPSENCOS_d_ff1_Z[2]), .Y(n3637)
);
AOI222X4TS U3564 ( .A0(n4811), .A1(FPSENCOS_d_ff2_Z[6]), .B0(n4810), .B1(
FPSENCOS_d_ff_Zn[6]), .C0(n3801), .C1(FPSENCOS_d_ff1_Z[6]), .Y(n3638)
);
AOI222X4TS U3565 ( .A0(n4811), .A1(FPSENCOS_d_ff2_Z[1]), .B0(n4810), .B1(
FPSENCOS_d_ff_Zn[1]), .C0(n3801), .C1(FPSENCOS_d_ff1_Z[1]), .Y(n3657)
);
INVX3TS U3566 ( .A(n3790), .Y(n4810) );
NOR2X2TS U3567 ( .A(FPSENCOS_d_ff2_X[27]), .B(intadd_525_n1), .Y(n4788) );
NOR2X2TS U3568 ( .A(FPSENCOS_d_ff2_X[29]), .B(n4791), .Y(n4790) );
NAND2X1TS U3569 ( .A(FPMULT_Sgf_normalized_result[3]), .B(n4947), .Y(n4950)
);
INVX3TS U3570 ( .A(n4808), .Y(n4812) );
NOR2XLTS U3571 ( .A(n4582), .B(FPMULT_P_Sgf[46]), .Y(n3368) );
INVX4TS U3572 ( .A(n3561), .Y(n4582) );
INVX3TS U3573 ( .A(n3536), .Y(n4394) );
INVX4TS U3574 ( .A(n4779), .Y(n4775) );
INVX4TS U3575 ( .A(n4769), .Y(n4768) );
NOR2X2TS U3576 ( .A(n4754), .B(n4761), .Y(n4763) );
NOR2X4TS U3577 ( .A(n5191), .B(n5172), .Y(n4761) );
INVX4TS U3578 ( .A(n2392), .Y(n4930) );
AOI2BB2X2TS U3579 ( .B0(FPADDSUB_DmP_mant_SFG_SWR[17]), .B1(
FPADDSUB_DMP_SFG[15]), .A0N(FPADDSUB_DMP_SFG[15]), .A1N(
FPADDSUB_DmP_mant_SFG_SWR[17]), .Y(n4337) );
AOI211X1TS U3580 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(n5276), .B0(
FPADDSUB_Raw_mant_NRM_SWR[2]), .C0(FPADDSUB_Raw_mant_NRM_SWR[4]), .Y(
n4014) );
AOI21X2TS U3581 ( .A0(FPADDSUB_Data_array_SWR[17]), .A1(n3907), .B0(n3732),
.Y(n3922) );
AOI21X2TS U3582 ( .A0(n3907), .A1(FPADDSUB_Data_array_SWR[18]), .B0(n3903),
.Y(n3928) );
AOI21X2TS U3583 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n3907), .B0(n3750),
.Y(n3911) );
OAI2BB2X2TS U3584 ( .B0(FPADDSUB_DMP_SFG[17]), .B1(
FPADDSUB_DmP_mant_SFG_SWR[19]), .A0N(FPADDSUB_DmP_mant_SFG_SWR[19]),
.A1N(FPADDSUB_DMP_SFG[17]), .Y(n4348) );
AOI21X1TS U3585 ( .A0(FPADDSUB_DMP_SFG[17]), .A1(
FPADDSUB_DmP_mant_SFG_SWR[19]), .B0(n4347), .Y(n3322) );
OAI2BB2X2TS U3586 ( .B0(FPADDSUB_DMP_SFG[7]), .B1(
FPADDSUB_DmP_mant_SFG_SWR[9]), .A0N(FPADDSUB_DmP_mant_SFG_SWR[9]),
.A1N(FPADDSUB_DMP_SFG[7]), .Y(n3961) );
AOI21X1TS U3587 ( .A0(FPADDSUB_DMP_SFG[7]), .A1(FPADDSUB_DmP_mant_SFG_SWR[9]), .B0(n3960), .Y(n3993) );
AOI21X1TS U3588 ( .A0(FPADDSUB_DMP_SFG[2]), .A1(FPADDSUB_DmP_mant_SFG_SWR[4]), .B0(n3583), .Y(n3659) );
OAI21X2TS U3589 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[20]), .A1(n5277), .B0(n3328),
.Y(n3329) );
OAI21XLTS U3590 ( .A0(n3965), .A1(n3582), .B0(n3964), .Y(n1340) );
NOR2BX1TS U3591 ( .AN(FPADDSUB_DMP_SFG[16]), .B(n2299), .Y(n3320) );
OAI22X2TS U3592 ( .A0(n5070), .A1(n3320), .B0(FPADDSUB_DMP_SFG[16]), .B1(
FPADDSUB_DmP_mant_SFG_SWR[18]), .Y(n4349) );
OAI21XLTS U3593 ( .A0(FPADDSUB_DMP_SFG[16]), .A1(n2299), .B0(n5072), .Y(
n5073) );
OAI211XLTS U3594 ( .A0(n4310), .A1(n5423), .B0(n4289), .C0(n4288), .Y(n1841)
);
OAI211XLTS U3595 ( .A0(n4310), .A1(n5375), .B0(n4163), .C0(n4162), .Y(n1917)
);
OAI221X1TS U3596 ( .A0(n5219), .A1(FPADDSUB_intDY_EWSW[9]), .B0(n5325), .B1(
FPADDSUB_intDY_EWSW[1]), .C0(n3482), .Y(n3485) );
OAI221XLTS U3597 ( .A0(n5321), .A1(FPADDSUB_intDY_EWSW[16]), .B0(n5326),
.B1(FPADDSUB_intDY_EWSW[11]), .C0(n3481), .Y(n3486) );
INVX2TS U3598 ( .A(n5361), .Y(n2375) );
INVX2TS U3599 ( .A(n3303), .Y(n3262) );
INVX2TS U3600 ( .A(n3344), .Y(n3260) );
INVX2TS U3601 ( .A(n3349), .Y(n3350) );
INVX2TS U3602 ( .A(n3301), .Y(n3256) );
INVX2TS U3603 ( .A(n4609), .Y(n3254) );
INVX2TS U3604 ( .A(n3300), .Y(DP_OP_499J224_125_1651_n130) );
INVX2TS U3605 ( .A(FPMULT_Op_MX[10]), .Y(n2431) );
INVX2TS U3606 ( .A(FPMULT_Op_MX[2]), .Y(n2415) );
INVX2TS U3607 ( .A(FPMULT_Sgf_operation_Result[1]), .Y(n2452) );
INVX2TS U3608 ( .A(FPMULT_Sgf_operation_Result[5]), .Y(n2464) );
INVX2TS U3609 ( .A(FPMULT_Sgf_operation_Result[2]), .Y(n2454) );
INVX2TS U3610 ( .A(FPMULT_Sgf_operation_Result[3]), .Y(n2460) );
INVX2TS U3611 ( .A(FPMULT_Sgf_operation_Result[4]), .Y(n2462) );
INVX2TS U3612 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[3]), .Y(n3235) );
INVX2TS U3613 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[1]), .Y(n2647) );
INVX2TS U3614 ( .A(FPMULT_Op_MX[21]), .Y(n2411) );
AO22XLTS U3615 ( .A0(n4743), .A1(n5034), .B0(n5353), .B1(n4741), .Y(n2395)
);
INVX2TS U3616 ( .A(FPMULT_Op_MY[0]), .Y(n4417) );
OAI21XLTS U3617 ( .A0(FPADDSUB_intDX_EWSW[1]), .A1(n5260), .B0(
FPADDSUB_intDX_EWSW[0]), .Y(n3427) );
OAI21XLTS U3618 ( .A0(FPADDSUB_intDX_EWSW[15]), .A1(n5190), .B0(
FPADDSUB_intDX_EWSW[14]), .Y(n3447) );
NOR2XLTS U3619 ( .A(n3460), .B(FPADDSUB_intDY_EWSW[16]), .Y(n3461) );
INVX2TS U3620 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[7]), .Y(n2757) );
INVX2TS U3621 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]), .Y(n2756)
);
OAI21XLTS U3622 ( .A0(FPADDSUB_intDX_EWSW[23]), .A1(n5194), .B0(
FPADDSUB_intDX_EWSW[22]), .Y(n3467) );
INVX2TS U3623 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[0]), .Y(n2450)
);
AOI21X1TS U3624 ( .A0(n2547), .A1(n2531), .B0(n2530), .Y(n2536) );
NAND2X1TS U3625 ( .A(n2490), .B(n2489), .Y(n2509) );
INVX2TS U3626 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[11]), .Y(n3238) );
OAI21XLTS U3627 ( .A0(n4477), .A1(n3881), .B0(n3880), .Y(n3883) );
NOR2XLTS U3628 ( .A(FPADDSUB_Raw_mant_NRM_SWR[17]), .B(
FPADDSUB_Raw_mant_NRM_SWR[16]), .Y(n3996) );
INVX2TS U3629 ( .A(n2559), .Y(n2451) );
AOI21X2TS U3630 ( .A0(n2459), .A1(n2548), .B0(n2458), .Y(n2537) );
INVX2TS U3631 ( .A(n4587), .Y(DP_OP_499J224_125_1651_n118) );
NOR2XLTS U3632 ( .A(n5157), .B(n5520), .Y(n3386) );
NOR2XLTS U3633 ( .A(n3837), .B(n5168), .Y(n3840) );
OAI21XLTS U3634 ( .A0(n4480), .A1(n3376), .B0(n4481), .Y(n3377) );
CMPR42X1TS U3635 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[9]), .B(
DP_OP_499J224_125_1651_n85), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[2]), .D(
DP_OP_499J224_125_1651_n86), .ICI(DP_OP_499J224_125_1651_n118), .S(
DP_OP_499J224_125_1651_n84), .ICO(DP_OP_499J224_125_1651_n82), .CO(
DP_OP_499J224_125_1651_n83) );
CMPR42X1TS U3636 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[8]), .B(
DP_OP_499J224_125_1651_n46), .C(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[15]), .D(
DP_OP_499J224_125_1651_n105), .ICI(DP_OP_499J224_125_1651_n47), .S(
DP_OP_499J224_125_1651_n45), .ICO(DP_OP_499J224_125_1651_n43), .CO(
DP_OP_499J224_125_1651_n44) );
OAI21XLTS U3637 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n4408), .B0(n4407), .Y(
n4409) );
AOI21X2TS U3638 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[4]), .A1(n5237), .B0(n3579),
.Y(n3662) );
OAI21XLTS U3639 ( .A0(n3153), .A1(n3125), .B0(n3145), .Y(n3128) );
OAI21XLTS U3640 ( .A0(n2718), .A1(n2717), .B0(n2986), .Y(n2721) );
OAI21XLTS U3641 ( .A0(n4462), .A1(n4459), .B0(n4460), .Y(n3851) );
OAI21XLTS U3642 ( .A0(n5276), .A1(n4378), .B0(n4372), .Y(n4373) );
AOI31XLTS U3643 ( .A0(n3516), .A1(n3515), .A2(n3514), .B0(n3705), .Y(n3517)
);
INVX2TS U3644 ( .A(n3302), .Y(n3360) );
OAI21XLTS U3645 ( .A0(n5067), .A1(n5069), .B0(n3190), .Y(n5066) );
OAI21XLTS U3646 ( .A0(n4312), .A1(n4687), .B0(n4684), .Y(intadd_519_CI) );
CMPR42X1TS U3647 ( .A(DP_OP_501J224_127_5235_n199), .B(
DP_OP_501J224_127_5235_n159), .C(DP_OP_501J224_127_5235_n234), .D(
DP_OP_501J224_127_5235_n192), .ICI(DP_OP_501J224_127_5235_n160), .S(
DP_OP_501J224_127_5235_n153), .ICO(DP_OP_501J224_127_5235_n151), .CO(
DP_OP_501J224_127_5235_n152) );
OAI211XLTS U3648 ( .A0(FPMULT_P_Sgf[43]), .A1(n3641), .B0(n2199), .C0(n3571),
.Y(n3572) );
ADDFHX2TS U3649 ( .A(n2589), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[10]), .CI(
n2588), .CO(n2586), .S(n4588) );
OAI211XLTS U3650 ( .A0(FPMULT_Sgf_normalized_result[9]), .A1(n4960), .B0(
n4991), .C0(n4962), .Y(n4961) );
OAI211XLTS U3651 ( .A0(n4109), .A1(n3655), .B0(n3650), .C0(n3649), .Y(n1517)
);
OAI211XLTS U3652 ( .A0(n4310), .A1(n5388), .B0(n4302), .C0(n4301), .Y(n1937)
);
OAI211XLTS U3653 ( .A0(n4239), .A1(n5401), .B0(n4223), .C0(n4222), .Y(n1924)
);
OAI211XLTS U3654 ( .A0(n4310), .A1(n5385), .B0(n4296), .C0(n4295), .Y(n1940)
);
NOR2XLTS U3655 ( .A(n2731), .B(n2658), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N0) );
OAI21XLTS U3656 ( .A0(n4352), .A1(n3582), .B0(n4351), .Y(n1321) );
OAI21XLTS U3657 ( .A0(n5320), .A1(n3981), .B0(n3978), .Y(n1365) );
OAI21XLTS U3658 ( .A0(n5328), .A1(n3976), .B0(n3696), .Y(n1386) );
OAI21XLTS U3659 ( .A0(n5334), .A1(n3814), .B0(n3710), .Y(n1462) );
OAI211XLTS U3660 ( .A0(n4310), .A1(n5421), .B0(n4165), .C0(n4164), .Y(n1843)
);
OAI21XLTS U3661 ( .A0(n4275), .A1(n5307), .B0(n4261), .Y(op_result[16]) );
NOR4X1TS U3662 ( .A(Data_1[12]), .B(Data_1[11]), .C(Data_1[10]), .D(
Data_1[9]), .Y(n2408) );
NOR4X1TS U3663 ( .A(Data_1[8]), .B(Data_1[7]), .C(Data_1[6]), .D(Data_1[0]),
.Y(n2407) );
NOR4X1TS U3664 ( .A(Data_1[3]), .B(Data_1[16]), .C(Data_1[1]), .D(Data_1[22]), .Y(n2405) );
NOR3XLTS U3665 ( .A(Data_1[2]), .B(Data_1[5]), .C(Data_1[4]), .Y(n2404) );
NOR4X1TS U3666 ( .A(Data_1[21]), .B(Data_1[19]), .C(Data_1[14]), .D(
Data_1[20]), .Y(n2403) );
NOR4X1TS U3667 ( .A(Data_1[13]), .B(Data_1[15]), .C(Data_1[17]), .D(
Data_1[18]), .Y(n2402) );
AND4X1TS U3668 ( .A(n2405), .B(n2404), .C(n2403), .D(n2402), .Y(n2406) );
NAND2X1TS U3669 ( .A(FPMULT_FS_Module_state_reg[0]), .B(n5195), .Y(n4380) );
OR3X2TS U3670 ( .A(FPMULT_FS_Module_state_reg[2]), .B(
FPMULT_FS_Module_state_reg[3]), .C(n4380), .Y(n4527) );
BUFX3TS U3671 ( .A(n4419), .Y(n4900) );
AND2X2TS U3672 ( .A(n2306), .B(n5353), .Y(n5120) );
CLKBUFX3TS U3673 ( .A(n5120), .Y(n5136) );
NOR2X1TS U3674 ( .A(n4729), .B(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]),
.Y(n4737) );
INVX2TS U3675 ( .A(n4737), .Y(n4730) );
NAND2X1TS U3676 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B(n4730),
.Y(n3391) );
OAI32X4TS U3677 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .A2(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B0(n3391), .B1(n4729),
.Y(n4741) );
INVX2TS U3678 ( .A(n4741), .Y(n4743) );
INVX2TS U3679 ( .A(n2411), .Y(DP_OP_501J224_127_5235_n411) );
INVX2TS U3680 ( .A(n4417), .Y(n4922) );
INVX2TS U3681 ( .A(n2397), .Y(n4925) );
ADDHX2TS U3682 ( .A(FPMULT_Op_MY[12]), .B(n4922), .CO(n2423), .S(n2678) );
INVX2TS U3683 ( .A(n2413), .Y(n3024) );
INVX4TS U3684 ( .A(n4421), .Y(n4904) );
INVX2TS U3685 ( .A(FPMULT_Op_MX[3]), .Y(n3876) );
INVX2TS U3686 ( .A(n3876), .Y(n4907) );
INVX4TS U3687 ( .A(n2415), .Y(n4908) );
CMPR32X2TS U3688 ( .A(n4908), .B(FPMULT_Op_MX[14]), .C(n2416), .CO(n2433),
.S(n2656) );
CMPR32X2TS U3689 ( .A(n4904), .B(FPMULT_Op_MX[20]), .C(n2419), .CO(n2432),
.S(n2922) );
INVX2TS U3690 ( .A(n2420), .Y(n3012) );
NOR2X1TS U3691 ( .A(n3024), .B(n3012), .Y(n2962) );
CMPR32X2TS U3692 ( .A(n2421), .B(n2650), .C(n2922), .CO(n2434), .S(n2422) );
INVX2TS U3693 ( .A(n2422), .Y(n3013) );
ADDHXLTS U3694 ( .A(n2678), .B(n2920), .CO(n2429), .S(n2413) );
CMPR32X2TS U3695 ( .A(n4921), .B(n2198), .C(n2423), .CO(n2428), .S(n2675) );
INVX2TS U3696 ( .A(FPMULT_Op_MY[8]), .Y(n3846) );
INVX2TS U3697 ( .A(n3846), .Y(n4923) );
INVX2TS U3698 ( .A(n2425), .Y(n3017) );
ADDHXLTS U3699 ( .A(n2706), .B(n2924), .CO(n2421), .S(n2426) );
INVX2TS U3700 ( .A(n2426), .Y(n3023) );
CMPR32X2TS U3701 ( .A(n4925), .B(FPMULT_Op_MY[14]), .C(n2428), .CO(n2439),
.S(n2693) );
CMPR32X2TS U3702 ( .A(n2429), .B(n2675), .C(n2923), .CO(n2440), .S(n2425) );
CMPR32X2TS U3703 ( .A(n2921), .B(n2656), .C(n2434), .CO(n2442), .S(n2420) );
INVX2TS U3704 ( .A(n2435), .Y(n3071) );
NOR2X1TS U3705 ( .A(n3024), .B(n3071), .Y(n3007) );
ADDHXLTS U3706 ( .A(n2437), .B(n2436), .CO(n3006), .S(n2960) );
CMPR32X2TS U3707 ( .A(FPMULT_Op_MY[9]), .B(FPMULT_Op_MY[21]), .C(n2438),
.CO(n2937), .S(n2925) );
CMPR32X2TS U3708 ( .A(FPMULT_Op_MY[3]), .B(FPMULT_Op_MY[15]), .C(n2439),
.CO(n2657), .S(n2968) );
CMPR32X2TS U3709 ( .A(n2925), .B(n2693), .C(n2440), .CO(n2967), .S(n2430) );
CMPR32X2TS U3710 ( .A(n2926), .B(n2651), .C(n2442), .CO(n2965), .S(n2435) );
CMPR32X2TS U3711 ( .A(n4906), .B(FPMULT_Op_MX[16]), .C(n2443), .CO(n2653),
.S(n2964) );
CLKXOR2X2TS U3712 ( .A(n4901), .B(n2938), .Y(n3079) );
INVX2TS U3713 ( .A(n3079), .Y(n2963) );
INVX2TS U3714 ( .A(n2445), .Y(n3073) );
INVX2TS U3715 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[0]), .Y(n2770)
);
INVX2TS U3716 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[0]), .Y(n2769) );
INVX2TS U3717 ( .A(n2554), .Y(n2556) );
INVX2TS U3718 ( .A(n2561), .Y(n2563) );
ADDHX1TS U3719 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[10]), .B(n2567), .CO(n2566), .S(n4585) );
CMPR32X2TS U3720 ( .A(n2573), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[6]), .C(n2572),
.CO(n2570), .S(n4572) );
CMPR32X2TS U3721 ( .A(n2575), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[5]), .C(n2574),
.CO(n2572), .S(n4555) );
CMPR32X2TS U3722 ( .A(n2579), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[3]), .C(n2578),
.CO(n2576), .S(n4558) );
CMPR32X2TS U3723 ( .A(n2583), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_left[1]), .C(n2582),
.CO(n2580), .S(n4550) );
CMPR32X2TS U3724 ( .A(n2587), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[11]), .C(
n2586), .CO(n2584), .S(n4602) );
CMPR32X2TS U3725 ( .A(n2591), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[9]), .C(n2590), .CO(n2588), .S(n4587) );
INVX2TS U3726 ( .A(n4598), .Y(DP_OP_499J224_125_1651_n119) );
CMPR32X2TS U3727 ( .A(n2595), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[11]), .C(
n2594), .CO(n2615), .S(n2618) );
CMPR32X2TS U3728 ( .A(n2597), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[10]), .C(
n2596), .CO(n2617), .S(n2621) );
CMPR32X2TS U3729 ( .A(n2599), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[9]), .C(n2598), .CO(n2620), .S(n2624) );
CMPR32X2TS U3730 ( .A(n2601), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[8]), .C(n2600), .CO(n2623), .S(n2627) );
INVX2TS U3731 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[7]), .Y(n2603) );
INVX2TS U3732 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[7]), .Y(n2602)
);
CMPR32X2TS U3733 ( .A(n2603), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[7]), .C(n2602), .CO(n2626), .S(n2630) );
INVX2TS U3734 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[6]), .Y(n2605) );
INVX2TS U3735 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[6]), .Y(n2604)
);
CMPR32X2TS U3736 ( .A(n2605), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[6]), .C(n2604), .CO(n2629), .S(n2633) );
INVX2TS U3737 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[5]), .Y(n2607) );
INVX2TS U3738 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[5]), .Y(n2606) );
CMPR32X2TS U3739 ( .A(n2607), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[5]), .C(n2606), .CO(n2632), .S(n2636) );
INVX2TS U3740 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[4]), .Y(n2609) );
INVX2TS U3741 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[4]), .Y(n2608) );
CMPR32X2TS U3742 ( .A(n2609), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[4]), .C(n2608), .CO(n2635), .S(n2639) );
INVX2TS U3743 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[3]), .Y(n2610) );
INVX2TS U3744 ( .A(FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[2]), .Y(n2612) );
INVX2TS U3745 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[2]), .Y(n2611) );
INVX2TS U3746 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[0]), .Y(n2649) );
XOR2X1TS U3747 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[1]), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[1]), .Y(n2646) );
XNOR2X1TS U3748 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[13]), .B(
n2613), .Y(n3206) );
CMPR32X2TS U3749 ( .A(n2618), .B(n2617), .C(n2616), .CO(n2614), .S(n3210) );
CMPR32X2TS U3750 ( .A(n2621), .B(n2620), .C(n2619), .CO(n2616), .S(n3212) );
CMPR32X2TS U3751 ( .A(n2624), .B(n2623), .C(n2622), .CO(n2619), .S(n3214) );
CMPR32X2TS U3752 ( .A(n2627), .B(n2626), .C(n2625), .CO(n2622), .S(n3216) );
CMPR32X2TS U3753 ( .A(n2630), .B(n2629), .C(n2628), .CO(n2625), .S(n3200) );
CMPR32X2TS U3754 ( .A(n2633), .B(n2632), .C(n2631), .CO(n2628), .S(n3218) );
CMPR32X2TS U3755 ( .A(n2636), .B(n2635), .C(n2634), .CO(n2631), .S(n3220) );
CMPR32X2TS U3756 ( .A(n2639), .B(n2638), .C(n2637), .CO(n2634), .S(n3222) );
CMPR32X2TS U3757 ( .A(n2642), .B(n2641), .C(n2640), .CO(n2637), .S(n3224) );
CMPR32X2TS U3758 ( .A(n2645), .B(n2644), .C(n2643), .CO(n2640), .S(n3226) );
CMPR32X2TS U3759 ( .A(n2648), .B(n2647), .C(n2646), .CO(n2643), .S(n3231) );
CMPR32X2TS U3760 ( .A(DP_OP_497J224_123_3916_n59), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_middle[0]), .C(n2649), .CO(n2648), .S(n3232) );
INVX2TS U3761 ( .A(n2964), .Y(n2717) );
AOI22X1TS U3762 ( .A0(n2651), .A1(n2717), .B0(n2964), .B1(n2718), .Y(n2652)
);
BUFX3TS U3763 ( .A(n2652), .Y(n2709) );
INVX2TS U3764 ( .A(n2675), .Y(n2688) );
INVX4TS U3765 ( .A(n2986), .Y(n2710) );
AOI22X1TS U3766 ( .A0(n2986), .A1(n2688), .B0(n2675), .B1(n2710), .Y(n2696)
);
OAI221X4TS U3767 ( .A0(n2964), .A1(n2986), .B0(n2717), .B1(n2710), .C0(n2709), .Y(n2708) );
INVX2TS U3768 ( .A(n2678), .Y(n2731) );
AOI22X1TS U3769 ( .A0(n2986), .A1(n2731), .B0(n2678), .B1(n2710), .Y(n2654)
);
OAI22X1TS U3770 ( .A0(n2709), .A1(n2696), .B0(n2708), .B1(n2654), .Y(n2663)
);
INVX2TS U3771 ( .A(n2656), .Y(n2733) );
AOI22X1TS U3772 ( .A0(n2650), .A1(n2733), .B0(n2656), .B1(mult_x_313_n74),
.Y(n2655) );
BUFX3TS U3773 ( .A(n2655), .Y(n2703) );
INVX2TS U3774 ( .A(n2968), .Y(n2691) );
AOI22X1TS U3775 ( .A0(n2651), .A1(n2691), .B0(n2968), .B1(n2718), .Y(n2700)
);
OAI221X4TS U3776 ( .A0(n2656), .A1(n2651), .B0(n2733), .B1(n2718), .C0(n2703), .Y(n2701) );
INVX2TS U3777 ( .A(n2693), .Y(n2694) );
AOI22X1TS U3778 ( .A0(n2651), .A1(n2694), .B0(n2693), .B1(n2718), .Y(n2660)
);
OAI22X1TS U3779 ( .A0(n2703), .A1(n2700), .B0(n2701), .B1(n2660), .Y(n2662)
);
INVX2TS U3780 ( .A(n2972), .Y(n2711) );
AOI22X1TS U3781 ( .A0(n2650), .A1(n2711), .B0(n2972), .B1(mult_x_313_n74),
.Y(n2659) );
INVX2TS U3782 ( .A(n2706), .Y(n2658) );
AOI22X1TS U3783 ( .A0(n2651), .A1(n2688), .B0(n2675), .B1(n2718), .Y(n2671)
);
OAI22X1TS U3784 ( .A0(n2703), .A1(n2660), .B0(n2701), .B1(n2671), .Y(n2666)
);
CMPR32X2TS U3785 ( .A(n2663), .B(n2662), .C(n2661), .CO(n2683), .S(n2744) );
CMPR32X2TS U3786 ( .A(FPMULT_Op_MY[5]), .B(FPMULT_Op_MY[17]), .C(n2664),
.CO(n2689), .S(n2976) );
INVX2TS U3787 ( .A(n2976), .Y(n2715) );
AOI22X1TS U3788 ( .A0(n2650), .A1(n2715), .B0(n2976), .B1(n2370), .Y(n2665)
);
OAI32X1TS U3789 ( .A0(n2710), .A1(n2678), .A2(n2709), .B0(n2708), .B1(n2710),
.Y(n2745) );
CMPR32X2TS U3790 ( .A(n2668), .B(n2667), .C(n2666), .CO(n2661), .S(n2741) );
AOI22X1TS U3791 ( .A0(n2650), .A1(n2691), .B0(n2968), .B1(mult_x_313_n74),
.Y(n2669) );
AOI22X1TS U3792 ( .A0(n2651), .A1(n2731), .B0(n2678), .B1(n2718), .Y(n2670)
);
OAI22X1TS U3793 ( .A0(n2703), .A1(n2671), .B0(n2701), .B1(n2670), .Y(n2672)
);
ADDHXLTS U3794 ( .A(n2673), .B(n2672), .CO(n2740), .S(n2736) );
OAI32X1TS U3795 ( .A0(n2718), .A1(n2678), .A2(n2703), .B0(n2701), .B1(n2718),
.Y(n2735) );
AOI22X1TS U3796 ( .A0(n2650), .A1(n2694), .B0(n2693), .B1(mult_x_313_n74),
.Y(n2674) );
AOI21X1TS U3797 ( .A0(n2678), .A1(n2706), .B0(mult_x_313_n74), .Y(n2738) );
NAND2X1TS U3798 ( .A(n2650), .B(n2658), .Y(n2677) );
AOI22X1TS U3799 ( .A0(n2650), .A1(n2688), .B0(n2675), .B1(mult_x_313_n74),
.Y(n2676) );
OAI22X1TS U3800 ( .A0(n2678), .A1(n2677), .B0(n2676), .B1(n2658), .Y(n2737)
);
CMPR32X2TS U3801 ( .A(mult_x_313_n26), .B(mult_x_313_n30), .C(n2679), .CO(
n2712), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N9) );
CMPR32X2TS U3802 ( .A(mult_x_313_n31), .B(mult_x_313_n35), .C(n2680), .CO(
n2679), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N8) );
CMPR32X2TS U3803 ( .A(mult_x_313_n36), .B(mult_x_313_n38), .C(n2681), .CO(
n2680), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N7) );
CMPR32X2TS U3804 ( .A(mult_x_313_n39), .B(n2683), .C(n2682), .CO(n2681), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N6) );
CMPR32X2TS U3805 ( .A(n2686), .B(n2685), .C(n2684), .CO(n2734), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N2) );
CMPR32X2TS U3806 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[18]), .C(n2687),
.CO(n2417), .S(n2980) );
NAND2X2TS U3807 ( .A(n2986), .B(n2980), .Y(n2725) );
OAI22X1TS U3808 ( .A0(n2691), .A1(n2730), .B0(n2694), .B1(n2725), .Y(
mult_x_313_n27) );
OAI22X1TS U3809 ( .A0(n2711), .A1(n2730), .B0(n2691), .B1(n2725), .Y(
mult_x_313_n54) );
OAI22X1TS U3810 ( .A0(n2731), .A1(n2725), .B0(n2688), .B1(n2730), .Y(
mult_x_313_n55) );
CMPR32X2TS U3811 ( .A(FPMULT_Op_MY[6]), .B(FPMULT_Op_MY[18]), .C(n2689),
.CO(n2424), .S(n3010) );
INVX2TS U3812 ( .A(n3010), .Y(n2727) );
AOI22X1TS U3813 ( .A0(n2986), .A1(n2727), .B0(n3010), .B1(n2710), .Y(n2707)
);
AOI22X1TS U3814 ( .A0(n2986), .A1(n2715), .B0(n2976), .B1(n2710), .Y(n2690)
);
OAI22X1TS U3815 ( .A0(n2709), .A1(n2707), .B0(n2708), .B1(n2690), .Y(
mult_x_313_n58) );
AOI22X1TS U3816 ( .A0(n2986), .A1(n2711), .B0(n2972), .B1(n2710), .Y(n2692)
);
OAI22X1TS U3817 ( .A0(n2709), .A1(n2690), .B0(n2708), .B1(n2692), .Y(
mult_x_313_n59) );
AOI22X1TS U3818 ( .A0(n2986), .A1(n2691), .B0(n2968), .B1(n2710), .Y(n2695)
);
OAI22X1TS U3819 ( .A0(n2709), .A1(n2692), .B0(n2708), .B1(n2695), .Y(
mult_x_313_n60) );
AOI22X1TS U3820 ( .A0(n2986), .A1(n2694), .B0(n2693), .B1(n2710), .Y(n2697)
);
OAI22X1TS U3821 ( .A0(n2709), .A1(n2695), .B0(n2708), .B1(n2697), .Y(
mult_x_313_n61) );
OAI22X1TS U3822 ( .A0(n2709), .A1(n2697), .B0(n2708), .B1(n2696), .Y(
mult_x_313_n62) );
AOI22X1TS U3823 ( .A0(n2651), .A1(n2727), .B0(n3010), .B1(n2718), .Y(n2698)
);
OAI22X1TS U3824 ( .A0(n2718), .A1(n2703), .B0(n2701), .B1(n2698), .Y(
mult_x_313_n66) );
AOI22X1TS U3825 ( .A0(n2651), .A1(n2715), .B0(n2976), .B1(n2718), .Y(n2699)
);
OAI22X1TS U3826 ( .A0(n2703), .A1(n2698), .B0(n2701), .B1(n2699), .Y(
mult_x_313_n67) );
AOI22X1TS U3827 ( .A0(n2651), .A1(n2711), .B0(n2972), .B1(n2718), .Y(n2702)
);
OAI22X1TS U3828 ( .A0(n2703), .A1(n2699), .B0(n2701), .B1(n2702), .Y(
mult_x_313_n68) );
OAI22X1TS U3829 ( .A0(n2703), .A1(n2702), .B0(n2701), .B1(n2700), .Y(
mult_x_313_n69) );
AOI21X1TS U3830 ( .A0(n3010), .A1(n2658), .B0(n2370), .Y(mult_x_313_n75) );
AOI22X1TS U3831 ( .A0(n3010), .A1(n2370), .B0(n2650), .B1(n2727), .Y(n2705)
);
OAI22X1TS U3832 ( .A0(n2710), .A1(n2709), .B0(n2708), .B1(n2707), .Y(n2722)
);
INVX2TS U3833 ( .A(n2722), .Y(n2714) );
OAI22X1TS U3834 ( .A0(n2715), .A1(n2730), .B0(n2711), .B1(n2725), .Y(n2713)
);
CMPR32X2TS U3835 ( .A(mult_x_313_n23), .B(mult_x_313_n25), .C(n2712), .CO(
n2719), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N10) );
CMPR32X2TS U3836 ( .A(n2714), .B(n2713), .C(mult_x_313_n21), .CO(n2749), .S(
n2720) );
OAI22X1TS U3837 ( .A0(n2727), .A1(n2730), .B0(n2715), .B1(n2725), .Y(n2723)
);
CMPR32X2TS U3838 ( .A(mult_x_313_n22), .B(n2720), .C(n2719), .CO(n2747), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N11) );
CMPR32X2TS U3839 ( .A(n2723), .B(n2722), .C(n2721), .CO(n2726), .S(n2748) );
OAI31X1TS U3840 ( .A0(n2727), .A1(n2726), .A2(n2725), .B0(n2724), .Y(n2728)
);
XNOR2X1TS U3841 ( .A(n2729), .B(n2728), .Y(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N13) );
INVX2TS U3842 ( .A(mult_x_313_n32), .Y(mult_x_313_n33) );
INVX2TS U3843 ( .A(mult_x_313_n27), .Y(mult_x_313_n28) );
CMPR32X2TS U3844 ( .A(n2736), .B(n2735), .C(n2734), .CO(n2739), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N3) );
ADDHXLTS U3845 ( .A(n2738), .B(n2737), .CO(n2684), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N1) );
CMPR32X2TS U3846 ( .A(n2741), .B(n2740), .C(n2739), .CO(n2742), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N4) );
CMPR32X2TS U3847 ( .A(n2744), .B(n2743), .C(n2742), .CO(n2682), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N5) );
ADDHXLTS U3848 ( .A(n2746), .B(n2745), .CO(mult_x_313_n42), .S(n2743) );
CMPR32X2TS U3849 ( .A(n2749), .B(n2748), .C(n2747), .CO(n2729), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_right_GENSTOP_inst_mult_N12) );
XOR2X1TS U3850 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[13]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[13]), .Y(
n2779) );
XOR2X1TS U3851 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[12]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[12]), .Y(
n2773) );
INVX2TS U3852 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[11]), .Y(
n2750) );
CMPR32X2TS U3853 ( .A(n3238), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[11]), .C(
n2750), .CO(n2772), .S(n2788) );
CMPR32X2TS U3854 ( .A(n2752), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[10]), .C(
n2751), .CO(n2787), .S(n2812) );
CMPR32X2TS U3855 ( .A(n2754), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[9]), .C(
n2753), .CO(n2811), .S(n2785) );
CMPR32X2TS U3856 ( .A(n2756), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[8]), .C(
n2755), .CO(n2784), .S(n2809) );
INVX2TS U3857 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[7]), .Y(n2758)
);
CMPR32X2TS U3858 ( .A(n2758), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[7]), .C(
n2757), .CO(n2808), .S(n2800) );
INVX2TS U3859 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[6]), .Y(n2760)
);
INVX2TS U3860 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[6]), .Y(n2759) );
CMPR32X2TS U3861 ( .A(n2760), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[6]), .C(
n2759), .CO(n2799), .S(n2797) );
INVX2TS U3862 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[5]), .Y(n2762)
);
INVX2TS U3863 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[5]), .Y(n2761) );
CMPR32X2TS U3864 ( .A(n2762), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[5]), .C(
n2761), .CO(n2796), .S(n2794) );
INVX2TS U3865 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[4]), .Y(n2764)
);
INVX2TS U3866 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[4]), .Y(n2763) );
CMPR32X2TS U3867 ( .A(n2764), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[4]), .C(
n2763), .CO(n2793), .S(n2791) );
INVX2TS U3868 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[3]), .Y(n2766)
);
INVX2TS U3869 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[3]), .Y(n2765) );
INVX2TS U3870 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[2]), .Y(n2768)
);
INVX2TS U3871 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[2]), .Y(n2767) );
INVX2TS U3872 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]), .Y(n2775) );
XOR2X1TS U3873 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[1]), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_left[1]), .Y(n2774)
);
CMPR32X2TS U3874 ( .A(n2773), .B(n2772), .C(n2771), .CO(n2777), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[12]) );
CMPR32X2TS U3875 ( .A(n2776), .B(n2775), .C(n2774), .CO(n2804), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[1]) );
CMPR32X2TS U3876 ( .A(n2779), .B(n2778), .C(n2777), .CO(n2780), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[13]) );
CMPR32X2TS U3877 ( .A(n2781), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[14]), .C(
n2780), .CO(n2782), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[14]) );
XNOR2X1TS U3878 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_middle[15]), .B(
n2782), .Y(FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[15])
);
CMPR32X2TS U3879 ( .A(n2785), .B(n2784), .C(n2783), .CO(n2810), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[9]) );
CMPR32X2TS U3880 ( .A(n2788), .B(n2787), .C(n2786), .CO(n2771), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[11]) );
CMPR32X2TS U3881 ( .A(n2806), .B(n2805), .C(n2804), .CO(n2801), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_S_B[2]) );
XNOR2X4TS U3882 ( .A(FPMULT_Op_MX[17]), .B(n2851), .Y(n2873) );
INVX2TS U3883 ( .A(n2833), .Y(n2867) );
AOI22X1TS U3884 ( .A0(n2876), .A1(n2833), .B0(n2867), .B1(n2873), .Y(n2879)
);
CMPR32X2TS U3885 ( .A(FPMULT_Op_MX[16]), .B(FPMULT_Op_MX[22]), .C(n2815),
.CO(n2851), .S(n2817) );
INVX2TS U3886 ( .A(n2817), .Y(n2856) );
AOI22X1TS U3887 ( .A0(n2897), .A1(n2856), .B0(n2817), .B1(n2884), .Y(n2816)
);
BUFX3TS U3888 ( .A(n2816), .Y(n2880) );
OAI221X4TS U3889 ( .A0(n2817), .A1(n2873), .B0(n2856), .B1(n2876), .C0(n2880), .Y(n2878) );
INVX2TS U3890 ( .A(n2836), .Y(n2900) );
AOI22X1TS U3891 ( .A0(n2836), .A1(n2876), .B0(n2873), .B1(n2900), .Y(n2818)
);
OAI22X1TS U3892 ( .A0(n2879), .A1(n2880), .B0(n2878), .B1(n2818), .Y(n2845)
);
ADDHX2TS U3893 ( .A(FPMULT_Op_MX[18]), .B(FPMULT_Op_MX[12]), .CO(n2813), .S(
n2896) );
CMPR32X2TS U3894 ( .A(n2198), .B(FPMULT_Op_MY[19]), .C(n2819), .CO(n2825),
.S(n2833) );
CMPR32X2TS U3895 ( .A(FPMULT_Op_MY[16]), .B(FPMULT_Op_MY[22]), .C(n2820),
.CO(n2852), .S(n2885) );
CLKXOR2X2TS U3896 ( .A(FPMULT_Op_MY[17]), .B(n2852), .Y(n2882) );
INVX2TS U3897 ( .A(n2882), .Y(n2895) );
AOI22X1TS U3898 ( .A0(n2882), .A1(DP_OP_500J224_126_4510_n32), .B0(
DP_OP_500J224_126_4510_n27), .B1(n2895), .Y(n2822) );
INVX2TS U3899 ( .A(n2896), .Y(n2821) );
OAI32X1TS U3900 ( .A0(n2896), .A1(n2885), .A2(DP_OP_500J224_126_4510_n27),
.B0(n2822), .B1(n2821), .Y(n2844) );
OAI32X1TS U3901 ( .A0(n2876), .A1(n2836), .A2(n2880), .B0(n2878), .B1(n2876),
.Y(n2843) );
INVX2TS U3902 ( .A(n2826), .Y(n2898) );
AOI22X1TS U3903 ( .A0(DP_OP_500J224_126_4510_n32), .A1(n2898), .B0(n2826),
.B1(n2281), .Y(n2824) );
BUFX3TS U3904 ( .A(n2824), .Y(n2891) );
INVX2TS U3905 ( .A(n2875), .Y(n2874) );
AOI22X1TS U3906 ( .A0(n2897), .A1(n2874), .B0(n2875), .B1(n2884), .Y(n2839)
);
OAI221X4TS U3907 ( .A0(n2826), .A1(n2897), .B0(n2898), .B1(n2884), .C0(n2891), .Y(n2889) );
AOI22X1TS U3908 ( .A0(n2897), .A1(n2867), .B0(n2833), .B1(n2884), .Y(n2831)
);
OAI22X1TS U3909 ( .A0(n2891), .A1(n2839), .B0(n2889), .B1(n2831), .Y(n2841)
);
CMPR32X2TS U3910 ( .A(FPMULT_Op_MY[15]), .B(FPMULT_Op_MY[21]), .C(n2827),
.CO(n2820), .S(n2871) );
INVX2TS U3911 ( .A(n2885), .Y(n2886) );
AOI22X1TS U3912 ( .A0(n2885), .A1(DP_OP_500J224_126_4510_n27), .B0(
DP_OP_500J224_126_4510_n32), .B1(n2886), .Y(n2828) );
OAI32X1TS U3913 ( .A0(n2896), .A1(n2871), .A2(DP_OP_500J224_126_4510_n27),
.B0(n2828), .B1(n2821), .Y(n2840) );
INVX2TS U3914 ( .A(n2871), .Y(n2870) );
AOI22X1TS U3915 ( .A0(n2871), .A1(n2281), .B0(DP_OP_500J224_126_4510_n32),
.B1(n2870), .Y(n2829) );
OAI32X1TS U3916 ( .A0(n2896), .A1(n2875), .A2(DP_OP_500J224_126_4510_n27),
.B0(n2829), .B1(n2821), .Y(n2838) );
AOI22X1TS U3917 ( .A0(n2836), .A1(n2884), .B0(n2897), .B1(n2900), .Y(n2830)
);
OAI22X1TS U3918 ( .A0(n2891), .A1(n2831), .B0(n2889), .B1(n2830), .Y(n2837)
);
OAI32X1TS U3919 ( .A0(n2884), .A1(n2836), .A2(n2891), .B0(n2889), .B1(n2884),
.Y(n2911) );
AOI22X1TS U3920 ( .A0(n2875), .A1(n2281), .B0(DP_OP_500J224_126_4510_n32),
.B1(n2874), .Y(n2832) );
OAI32X1TS U3921 ( .A0(n2896), .A1(n2833), .A2(DP_OP_500J224_126_4510_n27),
.B0(n2832), .B1(n2821), .Y(n2903) );
AOI21X1TS U3922 ( .A0(n2836), .A1(n2896), .B0(DP_OP_500J224_126_4510_n27),
.Y(n2908) );
NAND2X1TS U3923 ( .A(DP_OP_500J224_126_4510_n32), .B(n2821), .Y(n2835) );
AOI22X1TS U3924 ( .A0(n2833), .A1(n2281), .B0(DP_OP_500J224_126_4510_n32),
.B1(n2867), .Y(n2834) );
OAI22X1TS U3925 ( .A0(n2836), .A1(n2835), .B0(n2834), .B1(n2821), .Y(n2907)
);
ADDHXLTS U3926 ( .A(n2838), .B(n2837), .CO(n2913), .S(n2909) );
AOI22X1TS U3927 ( .A0(n2897), .A1(n2870), .B0(n2871), .B1(n2884), .Y(n2888)
);
OAI22X1TS U3928 ( .A0(n2891), .A1(n2888), .B0(n2889), .B1(n2839), .Y(n2916)
);
CMPR32X2TS U3929 ( .A(n2842), .B(n2841), .C(n2840), .CO(n2915), .S(n2914) );
CMPR32X2TS U3930 ( .A(n2845), .B(n2844), .C(n2843), .CO(n2850), .S(n2904) );
CMPR32X2TS U3931 ( .A(DP_OP_500J224_126_4510_n26), .B(
DP_OP_500J224_126_4510_n30), .C(n2846), .CO(n2853), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9) );
CMPR32X2TS U3932 ( .A(DP_OP_500J224_126_4510_n31), .B(
DP_OP_500J224_126_4510_n34), .C(n2847), .CO(n2846), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8) );
CMPR32X2TS U3933 ( .A(DP_OP_500J224_126_4510_n35), .B(
DP_OP_500J224_126_4510_n37), .C(n2848), .CO(n2847), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7) );
CMPR32X2TS U3934 ( .A(DP_OP_500J224_126_4510_n38), .B(n2850), .C(n2849),
.CO(n2848), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6) );
NAND2X2TS U3935 ( .A(FPMULT_Op_MX[17]), .B(n2851), .Y(n2866) );
INVX2TS U3936 ( .A(n2866), .Y(n2899) );
OAI22X1TS U3937 ( .A0(n2866), .A1(n2885), .B0(n2895), .B1(n2899), .Y(n2855)
);
INVX2TS U3938 ( .A(n2893), .Y(n2892) );
AOI22X1TS U3939 ( .A0(n2876), .A1(n2892), .B0(n2893), .B1(n2873), .Y(n2868)
);
OAI22X1TS U3940 ( .A0(n2876), .A1(n2880), .B0(n2878), .B1(n2868), .Y(n2854)
);
CMPR32X2TS U3941 ( .A(DP_OP_500J224_126_4510_n23), .B(
DP_OP_500J224_126_4510_n25), .C(n2853), .CO(n2857), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10) );
CMPR32X2TS U3942 ( .A(n2855), .B(n2854), .C(DP_OP_500J224_126_4510_n21),
.CO(n2919), .S(n2858) );
AOI22X1TS U3943 ( .A0(n2899), .A1(n2882), .B0(n2893), .B1(n2866), .Y(n2861)
);
INVX2TS U3944 ( .A(n2855), .Y(n2860) );
CMPR32X2TS U3945 ( .A(n2858), .B(DP_OP_500J224_126_4510_n22), .C(n2857),
.CO(n2917), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11) );
CMPR32X2TS U3946 ( .A(n2861), .B(n2860), .C(n2859), .CO(n2863), .S(n2918) );
OAI31X1TS U3947 ( .A0(n2893), .A1(n2863), .A2(n2866), .B0(n2862), .Y(n2864)
);
XNOR2X1TS U3948 ( .A(n2865), .B(n2864), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13) );
AOI22X1TS U3949 ( .A0(n2899), .A1(n2870), .B0(n2886), .B1(n2866), .Y(
DP_OP_500J224_126_4510_n52) );
AOI22X1TS U3950 ( .A0(n2899), .A1(n2874), .B0(n2870), .B1(n2866), .Y(
DP_OP_500J224_126_4510_n53) );
AOI22X1TS U3951 ( .A0(n2899), .A1(n2867), .B0(n2874), .B1(n2866), .Y(
DP_OP_500J224_126_4510_n54) );
AOI22X1TS U3952 ( .A0(n2899), .A1(n2900), .B0(n2867), .B1(n2866), .Y(
DP_OP_500J224_126_4510_n55) );
AOI22X1TS U3953 ( .A0(n2876), .A1(n2895), .B0(n2882), .B1(n2873), .Y(n2869)
);
OAI22X1TS U3954 ( .A0(n2880), .A1(n2868), .B0(n2878), .B1(n2869), .Y(
DP_OP_500J224_126_4510_n59) );
AOI22X1TS U3955 ( .A0(n2876), .A1(n2885), .B0(n2886), .B1(n2873), .Y(n2872)
);
OAI22X1TS U3956 ( .A0(n2872), .A1(n2878), .B0(n2880), .B1(n2869), .Y(
DP_OP_500J224_126_4510_n60) );
AOI22X1TS U3957 ( .A0(n2876), .A1(n2871), .B0(n2870), .B1(n2873), .Y(n2877)
);
OAI22X1TS U3958 ( .A0(n2872), .A1(n2880), .B0(n2877), .B1(n2878), .Y(
DP_OP_500J224_126_4510_n61) );
AOI22X1TS U3959 ( .A0(n2876), .A1(n2875), .B0(n2874), .B1(n2873), .Y(n2881)
);
OAI22X1TS U3960 ( .A0(n2877), .A1(n2880), .B0(n2881), .B1(n2878), .Y(
DP_OP_500J224_126_4510_n62) );
OAI22X1TS U3961 ( .A0(n2881), .A1(n2880), .B0(n2879), .B1(n2878), .Y(
DP_OP_500J224_126_4510_n63) );
AOI22X1TS U3962 ( .A0(n2897), .A1(n2893), .B0(n2892), .B1(n2884), .Y(n2883)
);
OAI22X1TS U3963 ( .A0(n2883), .A1(n2889), .B0(n2884), .B1(n2891), .Y(
DP_OP_500J224_126_4510_n67) );
AOI22X1TS U3964 ( .A0(n2897), .A1(n2882), .B0(n2895), .B1(n2884), .Y(n2887)
);
OAI22X1TS U3965 ( .A0(n2883), .A1(n2891), .B0(n2887), .B1(n2889), .Y(
DP_OP_500J224_126_4510_n68) );
AOI22X1TS U3966 ( .A0(n2897), .A1(n2886), .B0(n2885), .B1(n2884), .Y(n2890)
);
OAI22X1TS U3967 ( .A0(n2887), .A1(n2891), .B0(n2889), .B1(n2890), .Y(
DP_OP_500J224_126_4510_n69) );
OAI22X1TS U3968 ( .A0(n2891), .A1(n2890), .B0(n2889), .B1(n2888), .Y(
DP_OP_500J224_126_4510_n70) );
AOI21X1TS U3969 ( .A0(n2892), .A1(n2821), .B0(DP_OP_500J224_126_4510_n27),
.Y(DP_OP_500J224_126_4510_n75) );
AOI22X1TS U3970 ( .A0(n2893), .A1(DP_OP_500J224_126_4510_n32), .B0(
DP_OP_500J224_126_4510_n27), .B1(n2892), .Y(n2894) );
OAI32X1TS U3971 ( .A0(n2896), .A1(n2895), .A2(DP_OP_500J224_126_4510_n27),
.B0(n2894), .B1(n2821), .Y(DP_OP_500J224_126_4510_n76) );
OAI21X1TS U3972 ( .A0(DP_OP_500J224_126_4510_n27), .A1(n2898), .B0(n2897),
.Y(DP_OP_500J224_126_4510_n66) );
NOR2X1TS U3973 ( .A(n2899), .B(n2900), .Y(DP_OP_500J224_126_4510_n56) );
NOR2XLTS U3974 ( .A(n2900), .B(n2821), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0) );
CMPR32X2TS U3975 ( .A(n2903), .B(n2902), .C(n2901), .CO(n2910), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2) );
CMPR32X2TS U3976 ( .A(n2906), .B(n2905), .C(n2904), .CO(n2849), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5) );
ADDHXLTS U3977 ( .A(n2908), .B(n2907), .CO(n2901), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N1) );
CMPR32X2TS U3978 ( .A(n2911), .B(n2910), .C(n2909), .CO(n2912), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3) );
CMPR32X2TS U3979 ( .A(n2914), .B(n2913), .C(n2912), .CO(n2906), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4) );
ADDHXLTS U3980 ( .A(n2916), .B(n2915), .CO(DP_OP_500J224_126_4510_n41), .S(
n2905) );
CMPR32X2TS U3981 ( .A(n2919), .B(n2918), .C(n2917), .CO(n2865), .S(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12) );
INVX2TS U3982 ( .A(n2920), .Y(n3026) );
INVX2TS U3983 ( .A(n2921), .Y(n2946) );
INVX2TS U3984 ( .A(n2922), .Y(n3018) );
INVX2TS U3985 ( .A(n2923), .Y(n3020) );
INVX2TS U3986 ( .A(n2924), .Y(n3025) );
INVX2TS U3987 ( .A(n2925), .Y(n3019) );
INVX2TS U3988 ( .A(n2926), .Y(n3022) );
ADDHXLTS U3989 ( .A(n2928), .B(n2927), .CO(n2953), .S(n2934) );
INVX2TS U3990 ( .A(n2969), .Y(n3021) );
CMPR32X2TS U3991 ( .A(DP_OP_501J224_127_5235_n18), .B(
DP_OP_501J224_127_5235_n22), .C(n2929), .CO(n3035), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N7) );
CMPR32X2TS U3992 ( .A(DP_OP_501J224_127_5235_n23), .B(
DP_OP_501J224_127_5235_n29), .C(n2930), .CO(n2929), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N6) );
CMPR32X2TS U3993 ( .A(DP_OP_501J224_127_5235_n30), .B(
DP_OP_501J224_127_5235_n36), .C(n2931), .CO(n2930), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N5) );
CMPR32X2TS U3994 ( .A(n2933), .B(n2932), .C(DP_OP_501J224_127_5235_n37),
.CO(n2931), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N4) );
CMPR32X2TS U3995 ( .A(n2936), .B(n2935), .C(n2934), .CO(n3034), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N2) );
CMPR32X2TS U3996 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MY[22]), .C(n2937),
.CO(n2942), .S(n2969) );
NOR2X4TS U3997 ( .A(FPMULT_Op_MY[11]), .B(n2942), .Y(n3039) );
NOR2X4TS U3998 ( .A(n4901), .B(n2938), .Y(n3038) );
CMPR32X2TS U3999 ( .A(n2941), .B(n2940), .C(n2939), .CO(
DP_OP_501J224_127_5235_n19), .S(DP_OP_501J224_127_5235_n20) );
CMPR32X2TS U4000 ( .A(n2945), .B(n2944), .C(n2943), .CO(
DP_OP_501J224_127_5235_n24), .S(DP_OP_501J224_127_5235_n25) );
ADDHXLTS U4001 ( .A(n2948), .B(n2947), .CO(n3051), .S(n3033) );
CMPR32X2TS U4002 ( .A(n2951), .B(n2950), .C(n2949), .CO(
DP_OP_501J224_127_5235_n31), .S(DP_OP_501J224_127_5235_n32) );
CMPR32X2TS U4003 ( .A(n2954), .B(n2953), .C(n2952), .CO(
DP_OP_501J224_127_5235_n40), .S(n3032) );
CMPR32X2TS U4004 ( .A(DP_OP_501J224_127_5235_n119), .B(
DP_OP_501J224_127_5235_n124), .C(n2955), .CO(n3008), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N10) );
CMPR32X2TS U4005 ( .A(DP_OP_501J224_127_5235_n125), .B(
DP_OP_501J224_127_5235_n132), .C(n2956), .CO(n2955), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N9) );
CMPR32X2TS U4006 ( .A(DP_OP_501J224_127_5235_n143), .B(
DP_OP_501J224_127_5235_n152), .C(n2957), .CO(n2446), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N7) );
CMPR32X2TS U4007 ( .A(n2958), .B(DP_OP_501J224_127_5235_n156), .C(
DP_OP_501J224_127_5235_n153), .CO(n2957), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N6) );
CMPR32X2TS U4008 ( .A(n2959), .B(DP_OP_501J224_127_5235_n167), .C(
DP_OP_501J224_127_5235_n161), .CO(n2958), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N5) );
CMPR32X2TS U4009 ( .A(n2962), .B(n2961), .C(n2960), .CO(n3029), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N2) );
INVX2TS U4010 ( .A(n3038), .Y(n2987) );
CMPR32X2TS U4011 ( .A(n2965), .B(n2964), .C(n2963), .CO(n2985), .S(n2445) );
INVX2TS U4012 ( .A(n2966), .Y(n3060) );
CMPR32X2TS U4013 ( .A(n2969), .B(n2968), .C(n2967), .CO(n2973), .S(n2441) );
INVX2TS U4014 ( .A(n3080), .Y(n2971) );
INVX2TS U4015 ( .A(n3039), .Y(n2977) );
NOR2X1TS U4016 ( .A(n3061), .B(n3073), .Y(n2983) );
CMPR32X2TS U4017 ( .A(n2977), .B(n2976), .C(n2975), .CO(n3009), .S(n2978) );
INVX2TS U4018 ( .A(n2981), .Y(n3056) );
CMPR32X2TS U4019 ( .A(n2984), .B(n2983), .C(n2982), .CO(
DP_OP_501J224_127_5235_n115), .S(DP_OP_501J224_127_5235_n116) );
CMPR32X2TS U4020 ( .A(n2987), .B(n2986), .C(n2985), .CO(n2979), .S(n2988) );
INVX2TS U4021 ( .A(n2988), .Y(n3016) );
CMPR32X2TS U4022 ( .A(n2991), .B(n2990), .C(n2989), .CO(
DP_OP_501J224_127_5235_n129), .S(DP_OP_501J224_127_5235_n130) );
CMPR32X2TS U4023 ( .A(n2994), .B(n2993), .C(n2992), .CO(
DP_OP_501J224_127_5235_n137), .S(DP_OP_501J224_127_5235_n138) );
CMPR32X2TS U4024 ( .A(n2997), .B(n2996), .C(n2995), .CO(
DP_OP_501J224_127_5235_n147), .S(DP_OP_501J224_127_5235_n148) );
ADDHXLTS U4025 ( .A(n3001), .B(n3000), .CO(n3069), .S(n3028) );
CMPR32X2TS U4026 ( .A(n3004), .B(n3003), .C(n3002), .CO(
DP_OP_501J224_127_5235_n162), .S(DP_OP_501J224_127_5235_n163) );
CMPR32X2TS U4027 ( .A(n3007), .B(n3006), .C(n3005), .CO(
DP_OP_501J224_127_5235_n171), .S(n3027) );
NOR2X1TS U4028 ( .A(n3015), .B(n3023), .Y(DP_OP_501J224_127_5235_n235) );
NOR2X1TS U4029 ( .A(n3061), .B(n3023), .Y(DP_OP_501J224_127_5235_n233) );
NOR2X1TS U4030 ( .A(n3074), .B(n3012), .Y(DP_OP_501J224_127_5235_n220) );
NOR2X1TS U4031 ( .A(n3072), .B(n3013), .Y(DP_OP_501J224_127_5235_n229) );
NOR2X1TS U4032 ( .A(n3061), .B(n3071), .Y(DP_OP_501J224_127_5235_n209) );
INVX2TS U4033 ( .A(n3011), .Y(n3055) );
NOR2X1TS U4034 ( .A(n3055), .B(n3023), .Y(DP_OP_501J224_127_5235_n234) );
NOR2X1TS U4035 ( .A(n3015), .B(n3016), .Y(DP_OP_501J224_127_5235_n195) );
NOR2X1TS U4036 ( .A(n3055), .B(n3012), .Y(DP_OP_501J224_127_5235_n218) );
NOR2X1TS U4037 ( .A(n3055), .B(n3013), .Y(DP_OP_501J224_127_5235_n226) );
NOR2X1TS U4038 ( .A(n3017), .B(n3073), .Y(DP_OP_501J224_127_5235_n207) );
NOR2X1TS U4039 ( .A(n3060), .B(n3017), .Y(DP_OP_501J224_127_5235_n183) );
NOR2X1TS U4040 ( .A(n3014), .B(n3073), .Y(DP_OP_501J224_127_5235_n206) );
NOR2X1TS U4041 ( .A(n3017), .B(n3071), .Y(DP_OP_501J224_127_5235_n215) );
NOR2X1TS U4042 ( .A(n3060), .B(n3014), .Y(DP_OP_501J224_127_5235_n182) );
NOR2X1TS U4043 ( .A(n3060), .B(n3072), .Y(DP_OP_501J224_127_5235_n181) );
NOR2X1TS U4044 ( .A(n3017), .B(n3056), .Y(DP_OP_501J224_127_5235_n191) );
NOR2X1TS U4045 ( .A(n3014), .B(n3056), .Y(DP_OP_501J224_127_5235_n190) );
NOR2X1TS U4046 ( .A(n3061), .B(n3016), .Y(DP_OP_501J224_127_5235_n193) );
NOR2X1TS U4047 ( .A(n3055), .B(n3016), .Y(DP_OP_501J224_127_5235_n194) );
NOR2X1TS U4048 ( .A(n3072), .B(n3056), .Y(DP_OP_501J224_127_5235_n189) );
NOR2X1TS U4049 ( .A(n3060), .B(n3015), .Y(DP_OP_501J224_127_5235_n179) );
NOR2X1TS U4050 ( .A(n3017), .B(n3016), .Y(DP_OP_501J224_127_5235_n199) );
NOR2X1TS U4051 ( .A(n3055), .B(n3056), .Y(DP_OP_501J224_127_5235_n186) );
NOR2X1TS U4052 ( .A(n3021), .B(n3018), .Y(DP_OP_501J224_127_5235_n72) );
NOR2X1TS U4053 ( .A(n3020), .B(n3022), .Y(DP_OP_501J224_127_5235_n62) );
NOR2X1TS U4054 ( .A(n3080), .B(n3018), .Y(DP_OP_501J224_127_5235_n71) );
NOR2X1TS U4055 ( .A(n3079), .B(n3019), .Y(DP_OP_501J224_127_5235_n55) );
NOR2X1TS U4056 ( .A(n3079), .B(n3021), .Y(DP_OP_501J224_127_5235_n54) );
NOR2X1TS U4057 ( .A(n3079), .B(n3020), .Y(DP_OP_501J224_127_5235_n56) );
NOR2X1TS U4058 ( .A(n3039), .B(n3022), .Y(DP_OP_501J224_127_5235_n58) );
NOR2X1TS U4059 ( .A(n3038), .B(n3021), .Y(DP_OP_501J224_127_5235_n48) );
NOR2X1TS U4060 ( .A(n3080), .B(n3022), .Y(DP_OP_501J224_127_5235_n59) );
CMPR32X2TS U4061 ( .A(n3029), .B(n3028), .C(n3027), .CO(n3031), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N3) );
CMPR32X2TS U4062 ( .A(n3031), .B(n3030), .C(DP_OP_501J224_127_5235_n168),
.CO(n2959), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N4) );
CMPR32X2TS U4063 ( .A(n3034), .B(n3033), .C(n3032), .CO(n2933), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N3) );
NOR2X1TS U4064 ( .A(n3039), .B(n3079), .Y(n3036) );
CMPR32X2TS U4065 ( .A(DP_OP_501J224_127_5235_n15), .B(
DP_OP_501J224_127_5235_n17), .C(n3035), .CO(n3040), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N8) );
CMPR32X2TS U4066 ( .A(n3037), .B(n3036), .C(DP_OP_501J224_127_5235_n13),
.CO(n3044), .S(n3041) );
CMPR32X2TS U4067 ( .A(DP_OP_501J224_127_5235_n14), .B(n3041), .C(n3040),
.CO(n3042), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N9) );
CMPR32X2TS U4068 ( .A(n3044), .B(n3043), .C(n3042), .CO(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N11), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N10) );
ADDHXLTS U4069 ( .A(n3046), .B(n3045), .CO(n2945), .S(
DP_OP_501J224_127_5235_n34) );
ADDHXLTS U4070 ( .A(n3048), .B(n3047), .CO(n2961), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N1) );
ADDHXLTS U4071 ( .A(n3050), .B(n3049), .CO(n2935), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_left_GENSTOP_inst_mult_N1) );
ADDHXLTS U4072 ( .A(n3052), .B(n3051), .CO(n2949), .S(
DP_OP_501J224_127_5235_n39) );
ADDHXLTS U4073 ( .A(n3054), .B(n3053), .CO(n2939), .S(
DP_OP_501J224_127_5235_n27) );
NOR2X1TS U4074 ( .A(n3061), .B(n3056), .Y(n3058) );
CMPR32X2TS U4075 ( .A(DP_OP_501J224_127_5235_n113), .B(
DP_OP_501J224_127_5235_n111), .C(n3057), .CO(n3062), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N12) );
CMPR32X2TS U4076 ( .A(n3059), .B(n3058), .C(DP_OP_501J224_127_5235_n109),
.CO(n3066), .S(n3063) );
NOR2X1TS U4077 ( .A(n3061), .B(n3060), .Y(n3065) );
CMPR32X2TS U4078 ( .A(n3066), .B(n3065), .C(n3064), .CO(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N15), .S(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_middle_GENSTOP_inst_mult_N14) );
ADDHXLTS U4079 ( .A(n3068), .B(n3067), .CO(n2996), .S(
DP_OP_501J224_127_5235_n158) );
ADDHXLTS U4080 ( .A(n3070), .B(n3069), .CO(n3003), .S(
DP_OP_501J224_127_5235_n170) );
ADDHXLTS U4081 ( .A(n3078), .B(n3077), .CO(DP_OP_501J224_127_5235_n139), .S(
DP_OP_501J224_127_5235_n140) );
CMPR32X4TS U4082 ( .A(FPMULT_Op_MX[1]), .B(FPMULT_Op_MX[7]), .C(n3081), .CO(
n3087), .S(DP_OP_502J224_128_4510_n32) );
INVX2TS U4083 ( .A(n3085), .Y(n3125) );
AOI22X1TS U4084 ( .A0(n3166), .A1(n3125), .B0(n3085), .B1(n3153), .Y(n3083)
);
BUFX3TS U4085 ( .A(n3083), .Y(n3150) );
INVX2TS U4086 ( .A(n3102), .Y(n3135) );
INVX4TS U4087 ( .A(n3145), .Y(n3142) );
AOI22X1TS U4088 ( .A0(n3145), .A1(n3135), .B0(n3102), .B1(n3142), .Y(n3147)
);
OAI221X4TS U4089 ( .A0(n3085), .A1(n3145), .B0(n3125), .B1(n3142), .C0(n3150), .Y(n3148) );
AOI22X1TS U4090 ( .A0(n3145), .A1(n2362), .B0(n2363), .B1(n3142), .Y(n3086)
);
OAI22X1TS U4091 ( .A0(n3150), .A1(n3147), .B0(n3148), .B1(n3086), .Y(n3113)
);
CMPR32X2TS U4092 ( .A(n4908), .B(n4904), .C(n3087), .CO(n3082), .S(n3090) );
INVX2TS U4093 ( .A(n3090), .Y(n3167) );
AOI22X1TS U4094 ( .A0(DP_OP_502J224_128_4510_n32), .A1(n3167), .B0(n3090),
.B1(DP_OP_502J224_128_4510_n27), .Y(n3088) );
BUFX3TS U4095 ( .A(n3088), .Y(n3160) );
INVX2TS U4096 ( .A(n3143), .Y(n3144) );
AOI22X1TS U4097 ( .A0(n3166), .A1(n3144), .B0(n3143), .B1(n3153), .Y(n3108)
);
OAI221X4TS U4098 ( .A0(n3090), .A1(n3166), .B0(n3167), .B1(n3153), .C0(n3160), .Y(n3158) );
AOI22X1TS U4099 ( .A0(n3166), .A1(n3135), .B0(n3102), .B1(n3153), .Y(n3100)
);
OAI22X1TS U4100 ( .A0(n3160), .A1(n3108), .B0(n3158), .B1(n3100), .Y(n3096)
);
CMPR32X2TS U4101 ( .A(n4925), .B(n4923), .C(n3091), .CO(n3092), .S(n3143) );
CMPR32X2TS U4102 ( .A(FPMULT_Op_MY[3]), .B(FPMULT_Op_MY[9]), .C(n3092), .CO(
n3109), .S(n3139) );
INVX2TS U4103 ( .A(n3154), .Y(n3155) );
AOI22X1TS U4104 ( .A0(DP_OP_502J224_128_4510_n32), .A1(n3155), .B0(n3154),
.B1(DP_OP_502J224_128_4510_n27), .Y(n3094) );
INVX2TS U4105 ( .A(n3165), .Y(n3093) );
OAI32X1TS U4106 ( .A0(n3142), .A1(n2363), .A2(n3150), .B0(n3148), .B1(n3142),
.Y(n3111) );
CMPR32X2TS U4107 ( .A(n3097), .B(n3096), .C(n3095), .CO(n3112), .S(n3184) );
INVX2TS U4108 ( .A(n3139), .Y(n3140) );
AOI22X1TS U4109 ( .A0(DP_OP_502J224_128_4510_n32), .A1(n3140), .B0(n3139),
.B1(DP_OP_502J224_128_4510_n27), .Y(n3098) );
AOI22X1TS U4110 ( .A0(n3166), .A1(n2362), .B0(n2363), .B1(n3153), .Y(n3099)
);
OAI22X1TS U4111 ( .A0(n3160), .A1(n3100), .B0(n3158), .B1(n3099), .Y(n3106)
);
OAI32X1TS U4112 ( .A0(n3153), .A1(n2363), .A2(n3160), .B0(n3158), .B1(n3153),
.Y(n3174) );
AOI22X1TS U4113 ( .A0(DP_OP_502J224_128_4510_n32), .A1(n3144), .B0(n3143),
.B1(DP_OP_502J224_128_4510_n27), .Y(n3101) );
NOR2X1TS U4114 ( .A(n2362), .B(n3160), .Y(n3170) );
AOI21X1TS U4115 ( .A0(n2363), .A1(n3165), .B0(DP_OP_502J224_128_4510_n27),
.Y(n3181) );
NAND2X1TS U4116 ( .A(DP_OP_502J224_128_4510_n32), .B(n3093), .Y(n3104) );
AOI22X1TS U4117 ( .A0(DP_OP_502J224_128_4510_n32), .A1(n3135), .B0(n3102),
.B1(DP_OP_502J224_128_4510_n27), .Y(n3103) );
OAI22X1TS U4118 ( .A0(n2363), .A1(n3104), .B0(n3103), .B1(n3093), .Y(n3180)
);
ADDHXLTS U4119 ( .A(n3107), .B(n3106), .CO(n3183), .S(n3172) );
AOI22X1TS U4120 ( .A0(n3166), .A1(n3140), .B0(n3139), .B1(n3153), .Y(n3157)
);
OAI22X1TS U4121 ( .A0(n3160), .A1(n3157), .B0(n3158), .B1(n3108), .Y(n3179)
);
CMPR32X2TS U4122 ( .A(FPMULT_Op_MY[4]), .B(FPMULT_Op_MY[10]), .C(n3109),
.CO(n3119), .S(n3154) );
INVX2TS U4123 ( .A(n3164), .Y(n3151) );
AOI22X1TS U4124 ( .A0(DP_OP_502J224_128_4510_n32), .A1(n3151), .B0(n3164),
.B1(n2371), .Y(n3110) );
CMPR32X2TS U4125 ( .A(n3113), .B(n3112), .C(n3111), .CO(n3118), .S(n3175) );
CMPR32X2TS U4126 ( .A(DP_OP_502J224_128_4510_n26), .B(
DP_OP_502J224_128_4510_n30), .C(n3114), .CO(n3122), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N9) );
CMPR32X2TS U4127 ( .A(DP_OP_502J224_128_4510_n31), .B(
DP_OP_502J224_128_4510_n34), .C(n3115), .CO(n3114), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N8) );
CMPR32X2TS U4128 ( .A(DP_OP_502J224_128_4510_n35), .B(
DP_OP_502J224_128_4510_n37), .C(n3116), .CO(n3115), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N7) );
CMPR32X2TS U4129 ( .A(DP_OP_502J224_128_4510_n38), .B(n3118), .C(n3117),
.CO(n3116), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N6) );
CMPR32X2TS U4130 ( .A(FPMULT_Op_MY[5]), .B(FPMULT_Op_MY[11]), .C(n3119),
.CO(n3162), .S(n3164) );
INVX2TS U4131 ( .A(n3162), .Y(n3161) );
AOI22X1TS U4132 ( .A0(n3145), .A1(n3161), .B0(n3162), .B1(n3142), .Y(n3137)
);
OAI22X1TS U4133 ( .A0(n3150), .A1(n3142), .B0(n3148), .B1(n3137), .Y(n3129)
);
INVX2TS U4134 ( .A(n3129), .Y(n3124) );
NAND2X2TS U4135 ( .A(n3145), .B(n3121), .Y(n3136) );
OAI22X1TS U4136 ( .A0(n3151), .A1(n3168), .B0(n3155), .B1(n3136), .Y(n3123)
);
CMPR32X2TS U4137 ( .A(DP_OP_502J224_128_4510_n23), .B(
DP_OP_502J224_128_4510_n25), .C(n3122), .CO(n3126), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N10) );
CMPR32X2TS U4138 ( .A(n3124), .B(n3123), .C(DP_OP_502J224_128_4510_n21),
.CO(n3187), .S(n3127) );
OAI22X1TS U4139 ( .A0(n3161), .A1(n3168), .B0(n3151), .B1(n3136), .Y(n3130)
);
CMPR32X2TS U4140 ( .A(n3127), .B(DP_OP_502J224_128_4510_n22), .C(n3126),
.CO(n3185), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N11) );
CMPR32X2TS U4141 ( .A(n3130), .B(n3129), .C(n3128), .CO(n3132), .S(n3186) );
OAI31X1TS U4142 ( .A0(n3161), .A1(n3132), .A2(n3136), .B0(n3131), .Y(n3133)
);
XNOR2X1TS U4143 ( .A(n3134), .B(n3133), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N13) );
OAI22X1TS U4144 ( .A0(n3155), .A1(n3168), .B0(n3140), .B1(n3136), .Y(
DP_OP_502J224_128_4510_n53) );
OAI22X1TS U4145 ( .A0(n3140), .A1(n3168), .B0(n3144), .B1(n3136), .Y(
DP_OP_502J224_128_4510_n54) );
OAI22X1TS U4146 ( .A0(n3144), .A1(n3168), .B0(n3135), .B1(n3136), .Y(
DP_OP_502J224_128_4510_n55) );
OAI22X1TS U4147 ( .A0(n2362), .A1(n3136), .B0(n3135), .B1(n3168), .Y(
DP_OP_502J224_128_4510_n56) );
AOI22X1TS U4148 ( .A0(n3145), .A1(n3151), .B0(n3164), .B1(n3142), .Y(n3138)
);
OAI22X1TS U4149 ( .A0(n3150), .A1(n3137), .B0(n3148), .B1(n3138), .Y(
DP_OP_502J224_128_4510_n59) );
AOI22X1TS U4150 ( .A0(n3145), .A1(n3155), .B0(n3154), .B1(n3142), .Y(n3141)
);
OAI22X1TS U4151 ( .A0(n3150), .A1(n3138), .B0(n3148), .B1(n3141), .Y(
DP_OP_502J224_128_4510_n60) );
AOI22X1TS U4152 ( .A0(n3145), .A1(n3140), .B0(n3139), .B1(n3142), .Y(n3146)
);
OAI22X1TS U4153 ( .A0(n3150), .A1(n3141), .B0(n3148), .B1(n3146), .Y(
DP_OP_502J224_128_4510_n61) );
AOI22X1TS U4154 ( .A0(n3145), .A1(n3144), .B0(n3143), .B1(n3142), .Y(n3149)
);
OAI22X1TS U4155 ( .A0(n3150), .A1(n3146), .B0(n3148), .B1(n3149), .Y(
DP_OP_502J224_128_4510_n62) );
OAI22X1TS U4156 ( .A0(n3150), .A1(n3149), .B0(n3148), .B1(n3147), .Y(
DP_OP_502J224_128_4510_n63) );
AOI22X1TS U4157 ( .A0(n3166), .A1(n3161), .B0(n3162), .B1(n3153), .Y(n3152)
);
OAI22X1TS U4158 ( .A0(n3153), .A1(n3160), .B0(n3158), .B1(n3152), .Y(
DP_OP_502J224_128_4510_n67) );
AOI22X1TS U4159 ( .A0(n3166), .A1(n3151), .B0(n3164), .B1(n3153), .Y(n3156)
);
OAI22X1TS U4160 ( .A0(n3160), .A1(n3152), .B0(n3158), .B1(n3156), .Y(
DP_OP_502J224_128_4510_n68) );
AOI22X1TS U4161 ( .A0(n3166), .A1(n3155), .B0(n3154), .B1(n3153), .Y(n3159)
);
OAI22X1TS U4162 ( .A0(n3160), .A1(n3156), .B0(n3158), .B1(n3159), .Y(
DP_OP_502J224_128_4510_n69) );
OAI22X1TS U4163 ( .A0(n3160), .A1(n3159), .B0(n3158), .B1(n3157), .Y(
DP_OP_502J224_128_4510_n70) );
AOI21X1TS U4164 ( .A0(n3162), .A1(n3093), .B0(n2371), .Y(
DP_OP_502J224_128_4510_n75) );
AOI22X1TS U4165 ( .A0(n3162), .A1(n2371), .B0(DP_OP_502J224_128_4510_n32),
.B1(n3161), .Y(n3163) );
OAI21X1TS U4166 ( .A0(n2371), .A1(n3167), .B0(n3166), .Y(
DP_OP_502J224_128_4510_n66) );
NOR2XLTS U4167 ( .A(n2362), .B(n3093), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N0) );
CMPR32X2TS U4168 ( .A(n3171), .B(n3170), .C(n3169), .CO(n3173), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N2) );
CMPR32X2TS U4169 ( .A(n3174), .B(n3173), .C(n3172), .CO(n3182), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N3) );
CMPR32X2TS U4170 ( .A(n3177), .B(n3176), .C(n3175), .CO(n3117), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N5) );
ADDHXLTS U4171 ( .A(n3179), .B(n3178), .CO(DP_OP_502J224_128_4510_n41), .S(
n3176) );
ADDHXLTS U4172 ( .A(n3181), .B(n3180), .CO(n3169), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N1) );
CMPR32X2TS U4173 ( .A(n3184), .B(n3183), .C(n3182), .CO(n3177), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N4) );
CMPR32X2TS U4174 ( .A(n3187), .B(n3186), .C(n3185), .CO(n3134), .S(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_middle_GENSTOP_inst_mult_N12) );
AOI22X2TS U4175 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[3]), .A1(FPADDSUB_DMP_SFG[1]), .B0(n5525), .B1(n5235), .Y(n3189) );
AOI21X1TS U4176 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[2]), .A1(FPADDSUB_DMP_SFG[0]), .B0(n3189), .Y(n3193) );
NAND2X1TS U4177 ( .A(n5093), .B(n5286), .Y(n3188) );
NOR2X1TS U4178 ( .A(FPADDSUB_DmP_mant_SFG_SWR[1]), .B(
FPADDSUB_DmP_mant_SFG_SWR[0]), .Y(n5045) );
AOI2BB2X2TS U4179 ( .B0(n5045), .B1(n5046), .A0N(n5234), .A1N(
FPADDSUB_DmP_mant_SFG_SWR[2]), .Y(n3311) );
AOI2BB2XLTS U4180 ( .B0(n3311), .B1(n3189), .A0N(n3189), .A1N(n3311), .Y(
n3191) );
CLKBUFX2TS U4181 ( .A(FPADDSUB_Shift_reg_FLAGS_7[2]), .Y(n5042) );
INVX4TS U4182 ( .A(n5042), .Y(n5091) );
AOI22X1TS U4183 ( .A0(n3191), .A1(n3190), .B0(FPADDSUB_Raw_mant_NRM_SWR[3]),
.B1(n5091), .Y(n3192) );
OAI31X1TS U4184 ( .A0(n3318), .A1(n3193), .A2(n5078), .B0(n3192), .Y(n1346)
);
OR2X1TS U4185 ( .A(FPSENCOS_d_ff2_X[23]), .B(n5191), .Y(intadd_525_CI) );
ADDHX1TS U4186 ( .A(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[6]), .B(n3196), .CO(n3198), .S(n4599) );
INVX2TS U4187 ( .A(n4599), .Y(n3233) );
CMPR32X2TS U4188 ( .A(n3198), .B(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_Q_right[7]), .C(n3197), .CO(n2592), .S(n4601) );
INVX2TS U4189 ( .A(n4601), .Y(n3227) );
CMPR32X2TS U4190 ( .A(n3200), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[1]), .C(n3199),
.CO(n3215), .S(n4614) );
ADDHX1TS U4191 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[9]), .B(n3204),
.CO(n3203), .S(n4523) );
CMPR32X2TS U4192 ( .A(n3206), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[7]), .C(n3205),
.CO(n3201), .S(n4609) );
CMPR32X2TS U4193 ( .A(n3208), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[6]), .C(n3207),
.CO(n3205), .S(n3301) );
CMPR32X2TS U4194 ( .A(n3210), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[5]), .C(n3209),
.CO(n3207), .S(n3349) );
CMPR32X2TS U4195 ( .A(n3212), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[4]), .C(n3211),
.CO(n3209), .S(n3302) );
CMPR32X2TS U4196 ( .A(n3214), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[3]), .C(n3213),
.CO(n3211), .S(n3344) );
CMPR32X2TS U4197 ( .A(n3216), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[2]), .C(n3215),
.CO(n3213), .S(n3303) );
CMPR32X2TS U4198 ( .A(n3218), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_left[0]), .C(n3217),
.CO(n3199), .S(n4618) );
CMPR32X2TS U4199 ( .A(n3220), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[11]), .C(n3219), .CO(n3217), .S(n4622) );
CMPR32X2TS U4200 ( .A(n3222), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[10]), .C(n3221), .CO(n3219), .S(n4626) );
CMPR32X2TS U4201 ( .A(n3224), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[9]), .C(n3223),
.CO(n3221), .S(n4630) );
INVX2TS U4202 ( .A(n4630), .Y(n3272) );
CMPR32X2TS U4203 ( .A(n3226), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[8]), .C(n3225),
.CO(n3223), .S(n4634) );
INVX2TS U4204 ( .A(n4634), .Y(n3274) );
CMPR32X2TS U4205 ( .A(n3231), .B(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[7]), .C(n3230),
.CO(n3225), .S(n4638) );
INVX2TS U4206 ( .A(n4638), .Y(n3276) );
ADDHX1TS U4207 ( .A(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_Q_right[6]), .B(n3232),
.CO(n3230), .S(n4643) );
INVX2TS U4208 ( .A(n4643), .Y(n3280) );
OR2X1TS U4209 ( .A(n2647), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]), .Y(n3292) );
XNOR2X1TS U4210 ( .A(n2647), .B(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[1]), .Y(n3294) );
AFHCINX2TS U4211 ( .CIN(n3246), .B(DP_OP_499J224_125_1651_n42), .A(n3247),
.S(n4621), .CO(n3245) );
AFHCONX2TS U4212 ( .A(DP_OP_499J224_125_1651_n45), .B(n3249), .CI(n3248),
.CON(n3246), .S(n4625) );
AFHCINX2TS U4213 ( .CIN(n3250), .B(DP_OP_499J224_125_1651_n48), .A(n3251),
.S(n4629), .CO(n3248) );
AFHCONX2TS U4214 ( .A(DP_OP_499J224_125_1651_n53), .B(
DP_OP_499J224_125_1651_n51), .CI(n3252), .CON(n3250), .S(n4633) );
AFHCINX2TS U4215 ( .CIN(n3253), .B(DP_OP_499J224_125_1651_n54), .A(n3254),
.S(n4637), .CO(n3252) );
AFHCONX2TS U4216 ( .A(n3256), .B(DP_OP_499J224_125_1651_n57), .CI(n3255),
.CON(n3253), .S(n4642) );
AFHCINX2TS U4217 ( .CIN(n3257), .B(DP_OP_499J224_125_1651_n60), .A(n3350),
.S(n4646), .CO(n3255) );
AFHCONX2TS U4218 ( .A(n3360), .B(DP_OP_499J224_125_1651_n63), .CI(n3258),
.CON(n3257), .S(n3342) );
AFHCINX2TS U4219 ( .CIN(n3259), .B(DP_OP_499J224_125_1651_n66), .A(n3260),
.S(n4649), .CO(n3258) );
AFHCONX2TS U4220 ( .A(n3262), .B(DP_OP_499J224_125_1651_n69), .CI(n3261),
.CON(n3259), .S(n3339) );
AFHCINX2TS U4221 ( .CIN(n3263), .B(DP_OP_499J224_125_1651_n72), .A(n3264),
.S(n4653), .CO(n3261) );
AFHCONX2TS U4222 ( .A(n3266), .B(DP_OP_499J224_125_1651_n75), .CI(n3265),
.CON(n3263), .S(n4656) );
AFHCINX2TS U4223 ( .CIN(n3267), .B(DP_OP_499J224_125_1651_n78), .A(n3268),
.S(n4659), .CO(n3265) );
AFHCONX2TS U4224 ( .A(n3270), .B(DP_OP_499J224_125_1651_n81), .CI(n3269),
.CON(n3267), .S(n4584) );
AFHCINX2TS U4225 ( .CIN(n3271), .B(DP_OP_499J224_125_1651_n84), .A(n3272),
.S(n4579), .CO(n3269) );
AFHCONX2TS U4226 ( .A(n3274), .B(n3273), .CI(DP_OP_499J224_125_1651_n87),
.CON(n3271), .S(n4567) );
AFHCINX2TS U4227 ( .CIN(n3275), .B(n3276), .A(n3277), .S(n4575), .CO(n3273)
);
AFHCONX2TS U4228 ( .A(n3280), .B(n3279), .CI(n3278), .CON(n3275), .S(n4571)
);
AFHCINX2TS U4229 ( .CIN(n3281), .B(n3282), .A(n3283), .S(n4554), .CO(n3278)
);
AFHCONX2TS U4230 ( .A(n3286), .B(n3285), .CI(n3284), .CON(n3281), .S(n4564)
);
AFHCINX2TS U4231 ( .CIN(n3287), .B(n3288), .A(n3289), .S(n4559), .CO(n3284)
);
AFHCONX2TS U4232 ( .A(n3292), .B(n3291), .CI(n3290), .CON(n3287), .S(n4591)
);
AFHCINX2TS U4233 ( .CIN(n3293), .B(n3294), .A(n2452), .S(n4551), .CO(n3290)
);
AFHCONX2TS U4234 ( .A(
FPMULT_Sgf_operation_EVEN1_middle_RECURSIVE_ODD1_Q_right[0]), .B(n2649), .CI(n3295), .CON(n3293), .S(n4593) );
NAND2X1TS U4235 ( .A(n4594), .B(n4593), .Y(n4595) );
INVX2TS U4236 ( .A(n4595), .Y(n4549) );
NAND2BX1TS U4237 ( .AN(n3589), .B(n5291), .Y(n4383) );
NAND2X1TS U4238 ( .A(FPMULT_FS_Module_state_reg[1]), .B(
FPMULT_FSM_add_overflow_flag), .Y(n3296) );
NOR2BX1TS U4239 ( .AN(n5291), .B(n3532), .Y(n3297) );
NOR2X1TS U4240 ( .A(n4582), .B(n5414), .Y(n3619) );
NAND2X1TS U4241 ( .A(n3344), .B(n3303), .Y(n3359) );
NOR2X1TS U4242 ( .A(n3360), .B(n3359), .Y(n3347) );
NAND2X1TS U4243 ( .A(n3349), .B(n3347), .Y(n3356) );
NOR2X1TS U4244 ( .A(n3256), .B(n3356), .Y(n4606) );
NAND2X1TS U4245 ( .A(n4609), .B(n4606), .Y(n3353) );
INVX4TS U4246 ( .A(n3561), .Y(n4600) );
NOR2X1TS U4247 ( .A(n4582), .B(n5409), .Y(n3625) );
NOR4X1TS U4248 ( .A(Data_2[15]), .B(Data_2[19]), .C(Data_2[13]), .D(
Data_2[21]), .Y(n3309) );
NOR4X1TS U4249 ( .A(Data_2[4]), .B(Data_2[18]), .C(Data_2[20]), .D(Data_2[1]), .Y(n3308) );
NOR4X1TS U4250 ( .A(Data_2[3]), .B(Data_2[5]), .C(Data_2[22]), .D(Data_2[0]),
.Y(n3307) );
NAND3XLTS U4251 ( .A(n3309), .B(n3308), .C(n3307), .Y(n3310) );
AOI2BB2X2TS U4252 ( .B0(FPADDSUB_DmP_mant_SFG_SWR[20]), .B1(n5277), .A0N(
n5277), .A1N(FPADDSUB_DmP_mant_SFG_SWR[20]), .Y(n3321) );
AOI2BB2X2TS U4253 ( .B0(FPADDSUB_DMP_SFG[14]), .B1(n5256), .A0N(n5256),
.A1N(FPADDSUB_DMP_SFG[14]), .Y(n4329) );
NOR2X1TS U4254 ( .A(FPADDSUB_DmP_mant_SFG_SWR[14]), .B(n5246), .Y(n3316) );
NAND2X1TS U4255 ( .A(FPADDSUB_DMP_SFG[6]), .B(n5239), .Y(n5055) );
NOR2X1TS U4256 ( .A(FPADDSUB_DmP_mant_SFG_SWR[7]), .B(n5240), .Y(n3315) );
NAND2X1TS U4257 ( .A(FPADDSUB_DMP_SFG[4]), .B(n5181), .Y(n3314) );
NOR2X1TS U4258 ( .A(FPADDSUB_DmP_mant_SFG_SWR[5]), .B(n5236), .Y(n3313) );
OAI2BB2X2TS U4259 ( .B0(FPADDSUB_DMP_SFG[2]), .B1(
FPADDSUB_DmP_mant_SFG_SWR[4]), .A0N(FPADDSUB_DmP_mant_SFG_SWR[4]),
.A1N(FPADDSUB_DMP_SFG[2]), .Y(n3584) );
INVX2TS U4260 ( .A(n3584), .Y(n3581) );
OAI22X1TS U4261 ( .A0(n3312), .A1(n3311), .B0(FPADDSUB_DmP_mant_SFG_SWR[3]),
.B1(n5525), .Y(n3580) );
INVX2TS U4262 ( .A(n3961), .Y(n3958) );
AOI21X2TS U4263 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[11]), .A1(n2387), .B0(n4051),
.Y(n4118) );
AOI21X2TS U4264 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[12]), .A1(n5183), .B0(n4116),
.Y(n4205) );
AOI21X2TS U4265 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[13]), .A1(n5185), .B0(n4203),
.Y(n5067) );
OAI22X2TS U4266 ( .A0(FPADDSUB_DMP_SFG[12]), .A1(n5184), .B0(n3316), .B1(
n5067), .Y(n4318) );
AOI2BB2X2TS U4267 ( .B0(FPADDSUB_DMP_SFG[13]), .B1(n5249), .A0N(n5249),
.A1N(FPADDSUB_DMP_SFG[13]), .Y(n4320) );
NAND2X2TS U4268 ( .A(n4318), .B(n4320), .Y(n4317) );
NAND2X2TS U4269 ( .A(n4329), .B(n4327), .Y(n4326) );
NAND2X1TS U4270 ( .A(FPADDSUB_DMP_SFG[16]), .B(n2299), .Y(n5072) );
INVX2TS U4271 ( .A(n4348), .Y(n4345) );
INVX4TS U4272 ( .A(n5042), .Y(n5065) );
INVX2TS U4273 ( .A(n4337), .Y(n4339) );
INVX2TS U4274 ( .A(n4204), .Y(n4207) );
INVX2TS U4275 ( .A(n4117), .Y(n4120) );
INVX2TS U4276 ( .A(n4052), .Y(n4055) );
INVX2TS U4277 ( .A(n3989), .Y(n3992) );
AOI22X1TS U4278 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[7]), .A1(n5240), .B0(
FPADDSUB_DMP_SFG[5]), .B1(n5182), .Y(n5053) );
OAI22X2TS U4279 ( .A0(n5053), .A1(n5050), .B0(n5182), .B1(n5240), .Y(n5056)
);
NOR2X2TS U4280 ( .A(n4339), .B(n4340), .Y(n4338) );
NOR2BX1TS U4281 ( .AN(FPADDSUB_DMP_SFG[15]), .B(n5155), .Y(n3319) );
NOR2X2TS U4282 ( .A(n3321), .B(n3322), .Y(n3330) );
AOI211X1TS U4283 ( .A0(n3322), .A1(n3321), .B0(n3330), .C0(n5078), .Y(n3323)
);
AOI21X1TS U4284 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[20]), .A1(n5065), .B0(n3323),
.Y(n3324) );
NAND2X1TS U4285 ( .A(n3325), .B(n3324), .Y(n1320) );
NOR2X1TS U4286 ( .A(n5160), .B(n5520), .Y(mult_x_312_n72) );
INVX2TS U4287 ( .A(FPMULT_Op_MX[20]), .Y(n4669) );
NAND2X1TS U4288 ( .A(n5252), .B(n3547), .Y(n3393) );
NOR2X1TS U4289 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(n3393),
.Y(n3557) );
INVX4TS U4290 ( .A(n4796), .Y(n4781) );
NOR2X2TS U4291 ( .A(FPSENCOS_cont_iter_out[2]), .B(n4781), .Y(n4754) );
INVX2TS U4292 ( .A(n4754), .Y(n4110) );
INVX4TS U4293 ( .A(n4796), .Y(n4784) );
OAI32X4TS U4294 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n4784), .A2(n5170),
.B0(n4110), .B1(n5313), .Y(n4152) );
AOI21X1TS U4295 ( .A0(n4754), .A1(n5191), .B0(n4152), .Y(n4148) );
NOR2X1TS U4296 ( .A(n4148), .B(n5172), .Y(n4751) );
AOI21X1TS U4297 ( .A0(FPSENCOS_d_ff3_LUT_out[12]), .A1(n4781), .B0(n4751),
.Y(n3327) );
OAI21XLTS U4298 ( .A0(n5313), .A1(n4110), .B0(n3327), .Y(n2122) );
INVX2TS U4299 ( .A(FPMULT_Op_MX[14]), .Y(n4687) );
INVX2TS U4300 ( .A(n2198), .Y(n4365) );
AOI2BB2X2TS U4301 ( .B0(FPADDSUB_DmP_mant_SFG_SWR[21]), .B1(n5287), .A0N(
n5287), .A1N(FPADDSUB_DmP_mant_SFG_SWR[21]), .Y(n3331) );
NAND2X2TS U4302 ( .A(n3331), .B(n3329), .Y(n4355) );
NOR2X2TS U4303 ( .A(n3331), .B(n3332), .Y(n4358) );
AOI211X1TS U4304 ( .A0(n3332), .A1(n3331), .B0(n4358), .C0(n5078), .Y(n3333)
);
AOI21X1TS U4305 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[21]), .A1(n5091), .B0(n3333),
.Y(n3334) );
NAND2X1TS U4306 ( .A(n3335), .B(n3334), .Y(n1319) );
NOR2X1TS U4307 ( .A(n5188), .B(n5156), .Y(n4680) );
NAND2X1TS U4308 ( .A(DP_OP_501J224_127_5235_n411), .B(FPMULT_Op_MY[18]), .Y(
n4668) );
BUFX3TS U4309 ( .A(n3336), .Y(n5437) );
NOR2X1TS U4310 ( .A(n5175), .B(n5263), .Y(n4381) );
NAND2X1TS U4311 ( .A(n3599), .B(n4381), .Y(n4731) );
AOI21X1TS U4312 ( .A0(ack_operation), .A1(n4888), .B0(n4731), .Y(n4896) );
AOI21X1TS U4313 ( .A0(FPMULT_zero_flag), .A1(n5437), .B0(n4896), .Y(n3337)
);
INVX2TS U4314 ( .A(n4930), .Y(n4663) );
INVX2TS U4315 ( .A(FPMULT_Op_MX[16]), .Y(n4693) );
AFHCINX2TS U4316 ( .CIN(n3338), .B(n3339), .A(
FPMULT_Sgf_operation_EVEN1_Q_left[2]), .S(n3340), .CO(n4648) );
NOR2X1TS U4317 ( .A(n4582), .B(n5416), .Y(n3632) );
AFHCINX2TS U4318 ( .CIN(n3341), .B(n3342), .A(
FPMULT_Sgf_operation_EVEN1_Q_left[4]), .S(n3343), .CO(n4645) );
NOR2X1TS U4319 ( .A(n4582), .B(n5415), .Y(n3603) );
XNOR2X1TS U4320 ( .A(n3345), .B(n3260), .Y(n3346) );
NOR2X1TS U4321 ( .A(n4582), .B(n5413), .Y(n3613) );
INVX2TS U4322 ( .A(n3347), .Y(n3348) );
XNOR2X1TS U4323 ( .A(n3351), .B(n3350), .Y(n3352) );
NOR2X1TS U4324 ( .A(n4582), .B(n5411), .Y(n3616) );
XNOR2X1TS U4325 ( .A(n3354), .B(DP_OP_499J224_125_1651_n130), .Y(n3355) );
NOR2X1TS U4326 ( .A(n4582), .B(n2394), .Y(n3610) );
XNOR2X1TS U4327 ( .A(n3357), .B(n3256), .Y(n3358) );
NOR2X1TS U4328 ( .A(n4582), .B(n5410), .Y(n3622) );
XNOR2X1TS U4329 ( .A(n3361), .B(n3360), .Y(n3362) );
NOR2X1TS U4330 ( .A(n4582), .B(n5412), .Y(n3607) );
INVX2TS U4331 ( .A(rst), .Y(n5519) );
AO22XLTS U4332 ( .A0(n5361), .A1(FPADDSUB_Shift_amount_SHT1_EWR[1]), .B0(
n5179), .B1(intadd_523_SUM_0_), .Y(n1476) );
AND3X1TS U4333 ( .A(n5252), .B(n3363), .C(n3546), .Y(n3559) );
CLKAND2X2TS U4334 ( .A(n4761), .B(n4745), .Y(n3364) );
OA21XLTS U4335 ( .A0(FPSENCOS_cont_iter_out[2]), .A1(n3364), .B0(n4747), .Y(
n2139) );
INVX2TS U4336 ( .A(n5417), .Y(busy) );
AOI21X1TS U4337 ( .A0(n3532), .A1(n4383), .B0(n5195), .Y(n3365) );
BUFX3TS U4338 ( .A(n3365), .Y(n3578) );
NAND2X1TS U4339 ( .A(FPMULT_FSM_selector_C), .B(n3578), .Y(n3367) );
OR2X2TS U4340 ( .A(n4582), .B(n3367), .Y(n3564) );
NAND2X1TS U4341 ( .A(FPMULT_Op_MX[15]), .B(FPMULT_Op_MY[12]), .Y(n4313) );
NAND2X1TS U4342 ( .A(FPMULT_Op_MX[16]), .B(n2198), .Y(n4697) );
NOR2X1TS U4343 ( .A(n5270), .B(n2381), .Y(n5518) );
NOR2X1TS U4344 ( .A(n5158), .B(n2378), .Y(intadd_520_A_7_) );
AOI22X1TS U4345 ( .A0(n4902), .A1(FPMULT_Op_MY[11]), .B0(n4901), .B1(
FPMULT_Op_MY[10]), .Y(n3375) );
NAND2X1TS U4346 ( .A(n4901), .B(FPMULT_Op_MY[9]), .Y(n4428) );
INVX2TS U4347 ( .A(n2196), .Y(n3837) );
INVX2TS U4348 ( .A(n4429), .Y(n3371) );
INVX2TS U4349 ( .A(n4428), .Y(n3369) );
OAI21X1TS U4350 ( .A0(n4428), .A1(n3371), .B0(n3370), .Y(n3374) );
NAND2X1TS U4351 ( .A(n4430), .B(intadd_520_A_7_), .Y(n3372) );
NAND2X1TS U4352 ( .A(n3373), .B(n3372), .Y(intadd_520_B_7_) );
OAI2BB2XLTS U4353 ( .B0(intadd_520_B_7_), .B1(n3375), .A0N(n3374), .A1N(
n3373), .Y(intadd_520_B_6_) );
NOR2X1TS U4354 ( .A(n5269), .B(n2399), .Y(n5517) );
NOR2X1TS U4355 ( .A(n5169), .B(n2383), .Y(intadd_521_A_7_) );
AOI22X1TS U4356 ( .A0(n4906), .A1(FPMULT_Op_MY[5]), .B0(FPMULT_Op_MX[5]),
.B1(FPMULT_Op_MY[4]), .Y(n3382) );
NAND2X1TS U4357 ( .A(FPMULT_Op_MX[5]), .B(FPMULT_Op_MY[3]), .Y(n4479) );
INVX2TS U4358 ( .A(n4480), .Y(n3378) );
INVX2TS U4359 ( .A(n4479), .Y(n3376) );
OAI21X1TS U4360 ( .A0(n4479), .A1(n3378), .B0(n3377), .Y(n3381) );
NAND2X1TS U4361 ( .A(n4481), .B(intadd_521_A_7_), .Y(n3379) );
NAND2X1TS U4362 ( .A(n3380), .B(n3379), .Y(intadd_521_B_7_) );
OAI2BB2XLTS U4363 ( .B0(intadd_521_B_7_), .B1(n3382), .A0N(n3381), .A1N(
n3380), .Y(intadd_521_B_6_) );
NOR2X1TS U4364 ( .A(n5160), .B(n5254), .Y(mult_x_312_n71) );
NAND2X2TS U4365 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MY[17]), .Y(n4695) );
INVX2TS U4366 ( .A(n4695), .Y(n3384) );
AOI22X1TS U4367 ( .A0(FPMULT_Op_MX[13]), .A1(FPMULT_Op_MY[17]), .B0(
FPMULT_Op_MX[14]), .B1(FPMULT_Op_MY[16]), .Y(n3383) );
AOI21X1TS U4368 ( .A0(mult_x_312_n71), .A1(n3384), .B0(n3383), .Y(n3385) );
OA21XLTS U4369 ( .A0(n3386), .A1(n3385), .B0(n4366), .Y(mult_x_312_n25) );
OAI2BB1X1TS U4370 ( .A0N(intadd_522_n1), .A1N(n3387), .B0(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N11), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N10) );
NAND3XLTS U4371 ( .A(n3599), .B(n5175), .C(n5263), .Y(n1480) );
BUFX3TS U4372 ( .A(n2200), .Y(n5511) );
BUFX3TS U4373 ( .A(n2200), .Y(n5513) );
BUFX3TS U4374 ( .A(n5502), .Y(n5470) );
BUFX3TS U4375 ( .A(n5470), .Y(n5471) );
BUFX3TS U4376 ( .A(n5491), .Y(n3388) );
BUFX3TS U4377 ( .A(n5502), .Y(n5473) );
BUFX3TS U4378 ( .A(n3388), .Y(n5476) );
BUFX3TS U4379 ( .A(n3388), .Y(n5478) );
BUFX3TS U4380 ( .A(n3388), .Y(n5481) );
BUFX3TS U4381 ( .A(n5445), .Y(n5444) );
BUFX3TS U4382 ( .A(n5498), .Y(n5486) );
BUFX3TS U4383 ( .A(n5445), .Y(n5463) );
BUFX3TS U4384 ( .A(n5463), .Y(n5450) );
BUFX3TS U4385 ( .A(n3389), .Y(n5457) );
BUFX3TS U4386 ( .A(n5497), .Y(n5487) );
BUFX3TS U4387 ( .A(n3531), .Y(n5455) );
BUFX3TS U4388 ( .A(n3390), .Y(n5461) );
BUFX3TS U4389 ( .A(n2200), .Y(n5507) );
BUFX3TS U4390 ( .A(n3389), .Y(n5464) );
BUFX3TS U4391 ( .A(n3388), .Y(n5490) );
BUFX3TS U4392 ( .A(n5454), .Y(n5456) );
BUFX3TS U4393 ( .A(n5464), .Y(n5439) );
BUFX3TS U4394 ( .A(n3388), .Y(n5479) );
BUFX3TS U4395 ( .A(n5478), .Y(n5492) );
BUFX3TS U4396 ( .A(n3390), .Y(n5451) );
BUFX3TS U4397 ( .A(n3531), .Y(n5466) );
BUFX3TS U4398 ( .A(n5457), .Y(n5468) );
BUFX3TS U4399 ( .A(n5440), .Y(n5438) );
BUFX3TS U4400 ( .A(n5453), .Y(n5452) );
BUFX3TS U4401 ( .A(n5502), .Y(n5485) );
BUFX3TS U4402 ( .A(n5470), .Y(n5498) );
BUFX3TS U4403 ( .A(n5473), .Y(n5488) );
BUFX3TS U4404 ( .A(n5488), .Y(n5497) );
AO22XLTS U4405 ( .A0(n5093), .A1(FPADDSUB_DMP_SFG[28]), .B0(n5091), .B1(
FPADDSUB_DMP_exp_NRM_EW[5]), .Y(n1429) );
BUFX3TS U4406 ( .A(n5361), .Y(n5010) );
AO22XLTS U4407 ( .A0(n5104), .A1(intadd_523_SUM_1_), .B0(n5010), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[2]), .Y(n1477) );
BUFX3TS U4408 ( .A(n5361), .Y(n5102) );
AO22XLTS U4409 ( .A0(n5103), .A1(intadd_523_SUM_2_), .B0(n5102), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[3]), .Y(n1478) );
NAND3X1TS U4410 ( .A(n5198), .B(n5319), .C(ready_add_subt), .Y(n4773) );
BUFX3TS U4411 ( .A(n4773), .Y(n4777) );
BUFX3TS U4412 ( .A(n4773), .Y(n4863) );
BUFX3TS U4413 ( .A(n4863), .Y(n4872) );
BUFX3TS U4414 ( .A(n4872), .Y(n4879) );
OAI2BB2XLTS U4415 ( .B0(n4777), .B1(n5203), .A0N(n4879), .A1N(
FPSENCOS_d_ff_Xn[1]), .Y(n2069) );
OAI2BB2XLTS U4416 ( .B0(n4777), .B1(n5200), .A0N(n4879), .A1N(n2308), .Y(
n2060) );
OAI2BB2XLTS U4417 ( .B0(n4777), .B1(n5202), .A0N(n4879), .A1N(
FPSENCOS_d_ff_Xn[2]), .Y(n2066) );
OAI2BB2XLTS U4418 ( .B0(n4777), .B1(n5201), .A0N(n4879), .A1N(
FPSENCOS_d_ff_Xn[3]), .Y(n2063) );
OAI21X1TS U4419 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B0(n3391), .Y(n4104) );
NOR2BX1TS U4420 ( .AN(n4104), .B(n4741), .Y(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_) );
OAI21XLTS U4421 ( .A0(n4748), .A1(n5198), .B0(FPSENCOS_cont_var_out[1]), .Y(
n3394) );
BUFX3TS U4422 ( .A(n3395), .Y(n3396) );
OA22X1TS U4423 ( .A0(n3396), .A1(mult_result[30]), .B0(
FPMULT_exp_oper_result[7]), .B1(n2396), .Y(n1577) );
OA22X1TS U4424 ( .A0(n3396), .A1(mult_result[23]), .B0(
FPMULT_exp_oper_result[0]), .B1(n2396), .Y(n1584) );
OA22X1TS U4425 ( .A0(n3396), .A1(mult_result[28]), .B0(
FPMULT_exp_oper_result[5]), .B1(n2396), .Y(n1579) );
OA22X1TS U4426 ( .A0(n3396), .A1(mult_result[26]), .B0(
FPMULT_exp_oper_result[3]), .B1(n2396), .Y(n1581) );
OA22X1TS U4427 ( .A0(n3396), .A1(mult_result[27]), .B0(
FPMULT_exp_oper_result[4]), .B1(n2396), .Y(n1580) );
OA22X1TS U4428 ( .A0(n3396), .A1(mult_result[24]), .B0(n2323), .B1(n2396),
.Y(n1583) );
OA22X1TS U4429 ( .A0(n3396), .A1(mult_result[29]), .B0(
FPMULT_exp_oper_result[6]), .B1(n2396), .Y(n1578) );
OA22X1TS U4430 ( .A0(n3396), .A1(mult_result[25]), .B0(
FPMULT_exp_oper_result[2]), .B1(n2396), .Y(n1582) );
CLKBUFX2TS U4431 ( .A(n2200), .Y(n5514) );
AO22XLTS U4432 ( .A0(n4796), .A1(intadd_524_SUM_0_), .B0(n4799), .B1(
FPSENCOS_d_ff3_sh_y_out[24]), .Y(n1852) );
AO22XLTS U4433 ( .A0(n4796), .A1(intadd_524_SUM_1_), .B0(n4812), .B1(
FPSENCOS_d_ff3_sh_y_out[25]), .Y(n1851) );
INVX1TS U4434 ( .A(FPSENCOS_d_ff2_Y[23]), .Y(n4202) );
NAND2X1TS U4435 ( .A(FPSENCOS_cont_iter_out[0]), .B(n4202), .Y(intadd_524_CI) );
BUFX3TS U4436 ( .A(n4796), .Y(n4805) );
OAI21XLTS U4437 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n4202), .B0(
intadd_524_CI), .Y(n3397) );
AO22XLTS U4438 ( .A0(n4805), .A1(n3397), .B0(n4812), .B1(
FPSENCOS_d_ff3_sh_y_out[23]), .Y(n1853) );
AO22XLTS U4439 ( .A0(n4805), .A1(intadd_524_SUM_2_), .B0(n4799), .B1(
FPSENCOS_d_ff3_sh_y_out[26]), .Y(n1850) );
INVX2TS U4440 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .Y(n3399) );
INVX2TS U4441 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[2]), .Y(n3398) );
NOR2BX1TS U4442 ( .AN(n3402), .B(FPADDSUB_exp_rslt_NRM2_EW1[7]), .Y(n3403)
);
XNOR2X1TS U4443 ( .A(DP_OP_26J224_129_1325_n1), .B(FPADDSUB_ADD_OVRFLW_NRM2),
.Y(n3729) );
NOR2BX1TS U4444 ( .AN(n3403), .B(n3729), .Y(n4547) );
INVX2TS U4445 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .Y(n3404) );
NAND2X2TS U4446 ( .A(n4543), .B(n5515), .Y(n5004) );
OA22X1TS U4447 ( .A0(n5004), .A1(FPADDSUB_exp_rslt_NRM2_EW1[5]), .B0(n2280),
.B1(result_add_subt[28]), .Y(n1468) );
OA22X1TS U4448 ( .A0(n5004), .A1(FPADDSUB_exp_rslt_NRM2_EW1[4]), .B0(n2280),
.B1(result_add_subt[27]), .Y(n1469) );
OA22X1TS U4449 ( .A0(n5004), .A1(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B0(n2280),
.B1(result_add_subt[26]), .Y(n1470) );
OA22X1TS U4450 ( .A0(n5004), .A1(FPADDSUB_exp_rslt_NRM2_EW1[1]), .B0(n2280),
.B1(result_add_subt[24]), .Y(n1472) );
OA22X1TS U4451 ( .A0(n5004), .A1(FPADDSUB_exp_rslt_NRM2_EW1[0]), .B0(n2280),
.B1(result_add_subt[23]), .Y(n1473) );
OA22X1TS U4452 ( .A0(n5004), .A1(FPADDSUB_exp_rslt_NRM2_EW1[2]), .B0(n2280),
.B1(result_add_subt[25]), .Y(n1471) );
INVX1TS U4453 ( .A(FPSENCOS_d_ff2_Y[28]), .Y(n4198) );
NAND2X1TS U4454 ( .A(n4802), .B(n4198), .Y(n4807) );
AOI2BB2XLTS U4455 ( .B0(FPSENCOS_d_ff2_Y[30]), .B1(n4806), .A0N(n4806),
.A1N(FPSENCOS_d_ff2_Y[30]), .Y(n3405) );
AO22XLTS U4456 ( .A0(n4787), .A1(n3405), .B0(n4812), .B1(
FPSENCOS_d_ff3_sh_y_out[30]), .Y(n1846) );
OAI21XLTS U4457 ( .A0(n4802), .A1(n4198), .B0(n4807), .Y(n3406) );
AO22XLTS U4458 ( .A0(n4869), .A1(n3406), .B0(n4812), .B1(
FPSENCOS_d_ff3_sh_y_out[28]), .Y(n1848) );
NAND2X1TS U4459 ( .A(n4788), .B(n5356), .Y(n4791) );
OAI21XLTS U4460 ( .A0(n4788), .A1(n5356), .B0(n4791), .Y(n3407) );
INVX4TS U4461 ( .A(n4796), .Y(n4868) );
AO22XLTS U4462 ( .A0(n4787), .A1(n3407), .B0(n4868), .B1(
FPSENCOS_d_ff3_sh_x_out[28]), .Y(n1946) );
OAI21X1TS U4463 ( .A0(n5191), .A1(n5170), .B0(n5313), .Y(n4765) );
AOI22X1TS U4464 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(
FPSENCOS_cont_iter_out[2]), .B0(n4765), .B1(n5172), .Y(n3408) );
INVX4TS U4465 ( .A(n4796), .Y(n4782) );
AO22XLTS U4466 ( .A0(n4787), .A1(n3408), .B0(n4782), .B1(
FPSENCOS_d_ff3_LUT_out[4]), .Y(n2129) );
AOI2BB2XLTS U4467 ( .B0(FPSENCOS_d_ff2_X[30]), .B1(n4790), .A0N(n4790),
.A1N(FPSENCOS_d_ff2_X[30]), .Y(n3409) );
AO22XLTS U4468 ( .A0(n4787), .A1(n3409), .B0(n4868), .B1(
FPSENCOS_d_ff3_sh_x_out[30]), .Y(n1944) );
AOI22X1TS U4469 ( .A0(DP_OP_501J224_127_5235_n411), .A1(n4930), .B0(n2197),
.B1(FPMULT_Op_MY[22]), .Y(n3410) );
NAND2X1TS U4470 ( .A(n3411), .B(n4678), .Y(mult_x_309_n31) );
NOR2XLTS U4471 ( .A(n2411), .B(n5253), .Y(n3414) );
AOI22X1TS U4472 ( .A0(FPMULT_Op_MX[20]), .A1(FPMULT_Op_MY[22]), .B0(
FPMULT_Op_MX[22]), .B1(n4930), .Y(n3412) );
AOI21X1TS U4473 ( .A0(mult_x_309_n52), .A1(mult_x_309_n66), .B0(n3412), .Y(
n3413) );
OA21XLTS U4474 ( .A0(n3414), .A1(n3413), .B0(n4676), .Y(mult_x_309_n25) );
NOR2X1TS U4475 ( .A(n5273), .B(FPADDSUB_intDX_EWSW[25]), .Y(n3474) );
AOI22X1TS U4476 ( .A0(FPADDSUB_intDX_EWSW[25]), .A1(n5273), .B0(
FPADDSUB_intDX_EWSW[24]), .B1(n3415), .Y(n3419) );
OAI21X1TS U4477 ( .A0(FPADDSUB_intDX_EWSW[26]), .A1(n5280), .B0(n3416), .Y(
n3475) );
NOR2X1TS U4478 ( .A(n5293), .B(FPADDSUB_intDX_EWSW[30]), .Y(n3422) );
NOR2X1TS U4479 ( .A(n5196), .B(FPADDSUB_intDX_EWSW[29]), .Y(n3420) );
AOI211X1TS U4480 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n5346), .B0(n3422),
.C0(n3420), .Y(n3473) );
NOR3X1TS U4481 ( .A(n5346), .B(n3420), .C(FPADDSUB_intDY_EWSW[28]), .Y(n3421) );
AOI221X1TS U4482 ( .A0(FPADDSUB_intDX_EWSW[30]), .A1(n5293), .B0(
FPADDSUB_intDX_EWSW[29]), .B1(n5196), .C0(n3421), .Y(n3423) );
AOI2BB2X1TS U4483 ( .B0(n3424), .B1(n3473), .A0N(n3423), .A1N(n3422), .Y(
n3479) );
NOR2X1TS U4484 ( .A(n5283), .B(FPADDSUB_intDX_EWSW[17]), .Y(n3460) );
NOR2X1TS U4485 ( .A(n5274), .B(FPADDSUB_intDX_EWSW[11]), .Y(n3439) );
AOI21X1TS U4486 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n5320), .B0(n3439), .Y(
n3444) );
OAI2BB1X1TS U4487 ( .A0N(n5218), .A1N(FPADDSUB_intDY_EWSW[5]), .B0(
FPADDSUB_intDX_EWSW[4]), .Y(n3425) );
OAI22X1TS U4488 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n3425), .B0(n5218), .B1(
FPADDSUB_intDY_EWSW[5]), .Y(n3436) );
OAI2BB1X1TS U4489 ( .A0N(n5343), .A1N(FPADDSUB_intDY_EWSW[7]), .B0(
FPADDSUB_intDX_EWSW[6]), .Y(n3426) );
OAI22X1TS U4490 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n3426), .B0(n5343), .B1(
FPADDSUB_intDY_EWSW[7]), .Y(n3435) );
OAI2BB2XLTS U4491 ( .B0(FPADDSUB_intDY_EWSW[0]), .B1(n3427), .A0N(
FPADDSUB_intDX_EWSW[1]), .A1N(n5260), .Y(n3429) );
NAND2BXLTS U4492 ( .AN(FPADDSUB_intDX_EWSW[2]), .B(FPADDSUB_intDY_EWSW[2]),
.Y(n3428) );
OAI211XLTS U4493 ( .A0(n5265), .A1(FPADDSUB_intDX_EWSW[3]), .B0(n3429), .C0(
n3428), .Y(n3432) );
OAI21XLTS U4494 ( .A0(FPADDSUB_intDX_EWSW[3]), .A1(n5265), .B0(
FPADDSUB_intDX_EWSW[2]), .Y(n3430) );
AOI2BB2XLTS U4495 ( .B0(FPADDSUB_intDX_EWSW[3]), .B1(n5265), .A0N(
FPADDSUB_intDY_EWSW[2]), .A1N(n3430), .Y(n3431) );
AOI22X1TS U4496 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n5343), .B0(
FPADDSUB_intDY_EWSW[6]), .B1(n5222), .Y(n3433) );
OAI32X1TS U4497 ( .A0(n3436), .A1(n3435), .A2(n3434), .B0(n3433), .B1(n3435),
.Y(n3454) );
OA22X1TS U4498 ( .A0(n5257), .A1(FPADDSUB_intDX_EWSW[14]), .B0(n5190), .B1(
FPADDSUB_intDX_EWSW[15]), .Y(n3451) );
OAI2BB2XLTS U4499 ( .B0(FPADDSUB_intDY_EWSW[12]), .B1(n3438), .A0N(
FPADDSUB_intDX_EWSW[13]), .A1N(n5271), .Y(n3450) );
AOI22X1TS U4500 ( .A0(FPADDSUB_intDX_EWSW[11]), .A1(n5274), .B0(
FPADDSUB_intDX_EWSW[10]), .B1(n3440), .Y(n3446) );
AOI21X1TS U4501 ( .A0(n3443), .A1(n3442), .B0(n3453), .Y(n3445) );
OAI2BB2XLTS U4502 ( .B0(n3446), .B1(n3453), .A0N(n3445), .A1N(n3444), .Y(
n3449) );
OAI2BB2XLTS U4503 ( .B0(FPADDSUB_intDY_EWSW[14]), .B1(n3447), .A0N(
FPADDSUB_intDX_EWSW[15]), .A1N(n5190), .Y(n3448) );
AOI211X1TS U4504 ( .A0(n3451), .A1(n3450), .B0(n3449), .C0(n3448), .Y(n3452)
);
OAI31X1TS U4505 ( .A0(n3455), .A1(n3454), .A2(n3453), .B0(n3452), .Y(n3458)
);
OA22X1TS U4506 ( .A0(n5267), .A1(FPADDSUB_intDX_EWSW[22]), .B0(n5194), .B1(
FPADDSUB_intDX_EWSW[23]), .Y(n3471) );
OAI21X1TS U4507 ( .A0(FPADDSUB_intDX_EWSW[18]), .A1(n5284), .B0(n3462), .Y(
n3466) );
OAI21XLTS U4508 ( .A0(FPADDSUB_intDX_EWSW[21]), .A1(n5281), .B0(
FPADDSUB_intDX_EWSW[20]), .Y(n3459) );
OAI2BB2XLTS U4509 ( .B0(FPADDSUB_intDY_EWSW[20]), .B1(n3459), .A0N(
FPADDSUB_intDX_EWSW[21]), .A1N(n5281), .Y(n3470) );
AOI22X1TS U4510 ( .A0(FPADDSUB_intDX_EWSW[17]), .A1(n5283), .B0(
FPADDSUB_intDX_EWSW[16]), .B1(n3461), .Y(n3464) );
AOI32X1TS U4511 ( .A0(n5284), .A1(n3462), .A2(FPADDSUB_intDX_EWSW[18]), .B0(
FPADDSUB_intDX_EWSW[19]), .B1(n5197), .Y(n3463) );
OAI32X1TS U4512 ( .A0(n3466), .A1(n3465), .A2(n3464), .B0(n3463), .B1(n3465),
.Y(n3469) );
OAI2BB2XLTS U4513 ( .B0(FPADDSUB_intDY_EWSW[22]), .B1(n3467), .A0N(
FPADDSUB_intDX_EWSW[23]), .A1N(n5194), .Y(n3468) );
AOI211X1TS U4514 ( .A0(n3471), .A1(n3470), .B0(n3469), .C0(n3468), .Y(n3477)
);
NAND4BBX1TS U4515 ( .AN(n3475), .BN(n3474), .C(n3473), .D(n3472), .Y(n3476)
);
AOI32X1TS U4516 ( .A0(n3479), .A1(n3478), .A2(n3477), .B0(n3476), .B1(n3479),
.Y(n3513) );
BUFX3TS U4517 ( .A(n5225), .Y(n5037) );
CLKXOR2X2TS U4518 ( .A(FPADDSUB_intDY_EWSW[31]), .B(FPADDSUB_intAS), .Y(
n5036) );
AOI22X1TS U4519 ( .A0(n5221), .A1(FPADDSUB_intDY_EWSW[21]), .B0(n5327), .B1(
FPADDSUB_intDY_EWSW[8]), .Y(n3480) );
AOI22X1TS U4520 ( .A0(n5321), .A1(FPADDSUB_intDY_EWSW[16]), .B0(n5326), .B1(
FPADDSUB_intDY_EWSW[11]), .Y(n3481) );
AOI22X1TS U4521 ( .A0(n5219), .A1(FPADDSUB_intDY_EWSW[9]), .B0(n5325), .B1(
FPADDSUB_intDY_EWSW[1]), .Y(n3482) );
AOI22X1TS U4522 ( .A0(n5346), .A1(FPADDSUB_intDY_EWSW[28]), .B0(n5324), .B1(
FPADDSUB_intDY_EWSW[2]), .Y(n3483) );
NOR4X1TS U4523 ( .A(n3487), .B(n3486), .C(n3485), .D(n3484), .Y(n3516) );
AOI22X1TS U4524 ( .A0(n5344), .A1(FPADDSUB_intDY_EWSW[29]), .B0(n5224), .B1(
FPADDSUB_intDY_EWSW[18]), .Y(n3488) );
AOI22X1TS U4525 ( .A0(n5322), .A1(FPADDSUB_intDY_EWSW[13]), .B0(n5328), .B1(
FPADDSUB_intDY_EWSW[4]), .Y(n3489) );
OAI221XLTS U4526 ( .A0(n5322), .A1(FPADDSUB_intDY_EWSW[13]), .B0(n5328),
.B1(FPADDSUB_intDY_EWSW[4]), .C0(n3489), .Y(n3494) );
AOI22X1TS U4527 ( .A0(n5320), .A1(FPADDSUB_intDY_EWSW[10]), .B0(n5222), .B1(
FPADDSUB_intDY_EWSW[6]), .Y(n3490) );
AOI22X1TS U4528 ( .A0(n5334), .A1(FPADDSUB_intDY_EWSW[26]), .B0(n5223), .B1(
FPADDSUB_intDY_EWSW[19]), .Y(n3491) );
OAI221XLTS U4529 ( .A0(n5334), .A1(FPADDSUB_intDY_EWSW[26]), .B0(n5223),
.B1(FPADDSUB_intDY_EWSW[19]), .C0(n3491), .Y(n3492) );
NOR4X1TS U4530 ( .A(n3495), .B(n3494), .C(n3493), .D(n3492), .Y(n3515) );
AOI22X1TS U4531 ( .A0(n5220), .A1(FPADDSUB_intDY_EWSW[12]), .B0(n5329), .B1(
FPADDSUB_intDY_EWSW[3]), .Y(n3496) );
OAI221XLTS U4532 ( .A0(n5220), .A1(FPADDSUB_intDY_EWSW[12]), .B0(n5329),
.B1(FPADDSUB_intDY_EWSW[3]), .C0(n3496), .Y(n3512) );
AOI22X1TS U4533 ( .A0(n5345), .A1(FPADDSUB_intDY_EWSW[30]), .B0(n5205), .B1(
FPADDSUB_intDY_EWSW[23]), .Y(n3497) );
OAI221XLTS U4534 ( .A0(n5345), .A1(FPADDSUB_intDY_EWSW[30]), .B0(n5205),
.B1(FPADDSUB_intDY_EWSW[23]), .C0(n3497), .Y(n3511) );
AOI22X1TS U4535 ( .A0(n5218), .A1(FPADDSUB_intDY_EWSW[5]), .B0(n5323), .B1(
FPADDSUB_intDY_EWSW[0]), .Y(n3498) );
OAI221XLTS U4536 ( .A0(n5218), .A1(FPADDSUB_intDY_EWSW[5]), .B0(n5323), .B1(
FPADDSUB_intDY_EWSW[0]), .C0(n3498), .Y(n3499) );
AOI211XLTS U4537 ( .A0(n5332), .A1(FPADDSUB_intDX_EWSW[24]), .B0(n5225),
.C0(n3499), .Y(n3500) );
OAI21XLTS U4538 ( .A0(n5332), .A1(FPADDSUB_intDX_EWSW[24]), .B0(n3500), .Y(
n3510) );
OAI22X1TS U4539 ( .A0(n5343), .A1(FPADDSUB_intDY_EWSW[7]), .B0(n5316), .B1(
FPADDSUB_intDY_EWSW[22]), .Y(n3501) );
AOI221X1TS U4540 ( .A0(n5343), .A1(FPADDSUB_intDY_EWSW[7]), .B0(
FPADDSUB_intDY_EWSW[22]), .B1(n5316), .C0(n3501), .Y(n3508) );
OAI22X1TS U4541 ( .A0(n5318), .A1(FPADDSUB_intDY_EWSW[15]), .B0(n5216), .B1(
FPADDSUB_intDY_EWSW[20]), .Y(n3502) );
AOI221X1TS U4542 ( .A0(n5318), .A1(FPADDSUB_intDY_EWSW[15]), .B0(
FPADDSUB_intDY_EWSW[20]), .B1(n5216), .C0(n3502), .Y(n3507) );
OAI22X1TS U4543 ( .A0(n5217), .A1(FPADDSUB_intDY_EWSW[17]), .B0(n5331), .B1(
FPADDSUB_intDY_EWSW[25]), .Y(n3503) );
AOI221X1TS U4544 ( .A0(n5217), .A1(FPADDSUB_intDY_EWSW[17]), .B0(
FPADDSUB_intDY_EWSW[25]), .B1(n5331), .C0(n3503), .Y(n3506) );
OAI22X1TS U4545 ( .A0(n5317), .A1(FPADDSUB_intDY_EWSW[14]), .B0(n5215), .B1(
FPADDSUB_intDY_EWSW[27]), .Y(n3504) );
AOI221X1TS U4546 ( .A0(n5317), .A1(FPADDSUB_intDY_EWSW[14]), .B0(
FPADDSUB_intDY_EWSW[27]), .B1(n5215), .C0(n3504), .Y(n3505) );
NAND4XLTS U4547 ( .A(n3508), .B(n3507), .C(n3506), .D(n3505), .Y(n3509) );
NOR4X1TS U4548 ( .A(n3510), .B(n3511), .C(n3509), .D(n3512), .Y(n3514) );
OAI22X1TS U4549 ( .A0(FPADDSUB_intDX_EWSW[31]), .A1(n3517), .B0(
FPADDSUB_Shift_reg_FLAGS_7_6), .B1(FPADDSUB_SIGN_FLAG_EXP), .Y(n3518)
);
NAND2X1TS U4550 ( .A(FPMULT_Op_MX[7]), .B(n4924), .Y(n3519) );
INVX2TS U4551 ( .A(n3519), .Y(n4468) );
NAND2X1TS U4552 ( .A(n4468), .B(n5518), .Y(n4397) );
INVX2TS U4553 ( .A(n4397), .Y(n3521) );
NAND2X1TS U4554 ( .A(n4397), .B(FPMULT_Op_MY[6]), .Y(n3548) );
XNOR2X1TS U4555 ( .A(n4469), .B(n3519), .Y(n3549) );
AOI21X1TS U4556 ( .A0(n4904), .A1(n3548), .B0(n3520), .Y(n3554) );
AO21XLTS U4557 ( .A0(n3521), .A1(n4904), .B0(n3554), .Y(intadd_520_CI) );
NAND2X1TS U4558 ( .A(FPMULT_Op_MX[1]), .B(n4921), .Y(n3522) );
INVX2TS U4559 ( .A(n3522), .Y(n4517) );
NAND2X1TS U4560 ( .A(n4517), .B(n5517), .Y(n4399) );
INVX2TS U4561 ( .A(n4399), .Y(n3524) );
NAND2X1TS U4562 ( .A(n4399), .B(n4922), .Y(n3538) );
INVX2TS U4563 ( .A(n4925), .Y(n3885) );
XNOR2X1TS U4564 ( .A(n4518), .B(n3522), .Y(n3539) );
AOI21X1TS U4565 ( .A0(n4908), .A1(n3538), .B0(n3523), .Y(n3544) );
AO21XLTS U4566 ( .A0(n3524), .A1(n4908), .B0(n3544), .Y(intadd_521_CI) );
NOR2XLTS U4567 ( .A(n5157), .B(n5171), .Y(n3528) );
INVX2TS U4568 ( .A(FPMULT_Op_MX[12]), .Y(n4696) );
NOR3X1TS U4569 ( .A(n4696), .B(n5520), .C(n4695), .Y(n3526) );
NAND2X1TS U4570 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MY[15]), .Y(n3525) );
OAI32X1TS U4571 ( .A0(n3526), .A1(n5164), .A2(n4696), .B0(n3525), .B1(n3526),
.Y(n3527) );
OA21XLTS U4572 ( .A0(n3528), .A1(n3527), .B0(n4694), .Y(mult_x_312_n32) );
NOR2XLTS U4573 ( .A(n4696), .B(n5520), .Y(n3530) );
AOI211X1TS U4574 ( .A0(FPMULT_Op_MX[12]), .A1(n2198), .B0(n5160), .C0(n5171),
.Y(n3529) );
OA21XLTS U4575 ( .A0(n3530), .A1(n3529), .B0(n4314), .Y(intadd_519_A_0_) );
NAND2X1TS U4576 ( .A(FPADDSUB_DmP_EXP_EWSW[23]), .B(n5348), .Y(intadd_523_CI) );
NAND2X1TS U4577 ( .A(FPMULT_FS_Module_state_reg[0]), .B(
FPMULT_FS_Module_state_reg[1]), .Y(n4892) );
NAND3BX2TS U4578 ( .AN(n4892), .B(n5263), .C(n5175), .Y(n4941) );
INVX2TS U4579 ( .A(n4941), .Y(n3533) );
NAND2BXLTS U4580 ( .AN(n4380), .B(n4894), .Y(n4887) );
NAND2BXLTS U4581 ( .AN(n4887), .B(FPMULT_P_Sgf[47]), .Y(n3534) );
OAI31X1TS U4582 ( .A0(n3533), .A1(n4987), .A2(n5279), .B0(n3534), .Y(n1622)
);
AOI211X1TS U4583 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n3534), .B0(n3533),
.C0(n4987), .Y(n3535) );
INVX2TS U4584 ( .A(n3535), .Y(n1623) );
INVX4TS U4585 ( .A(n4539), .Y(n4537) );
OAI21XLTS U4586 ( .A0(n4537), .A1(n2195), .B0(n4048), .Y(n1350) );
OAI21XLTS U4587 ( .A0(n3536), .A1(n5312), .B0(n4048), .Y(n2079) );
INVX2TS U4588 ( .A(n3538), .Y(n3542) );
INVX2TS U4589 ( .A(n3539), .Y(n3540) );
OAI21XLTS U4590 ( .A0(n4908), .A1(n4399), .B0(n3540), .Y(n3541) );
AOI21X1TS U4591 ( .A0(n3542), .A1(n4908), .B0(n3541), .Y(n3543) );
NOR2XLTS U4592 ( .A(n3544), .B(n3543), .Y(
FPMULT_Sgf_operation_EVEN1_right_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2) );
NOR2X1TS U4593 ( .A(n5157), .B(n5164), .Y(mult_x_312_n58) );
OAI21XLTS U4594 ( .A0(n3536), .A1(n2284), .B0(n4065), .Y(n2078) );
NAND3X1TS U4595 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(n3547),
.C(n3546), .Y(n4726) );
BUFX3TS U4596 ( .A(n4778), .Y(n4779) );
NOR2XLTS U4597 ( .A(n4726), .B(n4779), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]) );
INVX2TS U4598 ( .A(n3548), .Y(n3552) );
INVX2TS U4599 ( .A(n3549), .Y(n3550) );
OAI21XLTS U4600 ( .A0(n4904), .A1(n4397), .B0(n3550), .Y(n3551) );
AOI21X1TS U4601 ( .A0(n3552), .A1(n4904), .B0(n3551), .Y(n3553) );
NOR2X1TS U4602 ( .A(n5157), .B(n5254), .Y(mult_x_312_n59) );
NOR2X1TS U4603 ( .A(n4696), .B(n5163), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N0) );
NAND3X1TS U4604 ( .A(FPMULT_Op_MX[13]), .B(n2198), .C(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N0), .Y(n4312) );
INVX2TS U4605 ( .A(n4312), .Y(n4311) );
NAND2X1TS U4606 ( .A(FPMULT_Op_MX[12]), .B(n2198), .Y(n3555) );
OAI32X1TS U4607 ( .A0(n4311), .A1(n5163), .A2(n5160), .B0(n3555), .B1(n4311),
.Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N1) );
NOR2X2TS U4608 ( .A(n5162), .B(n5248), .Y(mult_x_309_n33) );
INVX2TS U4609 ( .A(n2197), .Y(n4677) );
NOR2X2TS U4610 ( .A(n4677), .B(n5156), .Y(mult_x_309_n26) );
NAND2X1TS U4611 ( .A(mult_x_309_n33), .B(mult_x_309_n26), .Y(n4665) );
INVX2TS U4612 ( .A(n4665), .Y(n4666) );
NAND2X1TS U4613 ( .A(FPMULT_Op_MX[18]), .B(FPMULT_Op_MY[19]), .Y(n3556) );
OAI32X1TS U4614 ( .A0(n4666), .A1(n5248), .A2(n4677), .B0(n3556), .B1(n4666),
.Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N1) );
NAND3BX1TS U4615 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .B(n3557),
.C(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .Y(n4734) );
AOI21X1TS U4616 ( .A0(operation[1]), .A1(ack_operation), .B0(n4734), .Y(
n4719) );
NOR2X2TS U4617 ( .A(n5313), .B(n5170), .Y(n4759) );
OR2X1TS U4618 ( .A(n4719), .B(n4746), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]) );
NAND3BX1TS U4619 ( .AN(n3558), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]),
.C(n5314), .Y(n4720) );
NAND3BX1TS U4620 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .C(n3559), .Y(n4723) );
INVX2TS U4621 ( .A(operation[0]), .Y(n3560) );
OAI32X1TS U4622 ( .A0(n4768), .A1(n3560), .A2(n4717), .B0(n5178), .B1(n4771),
.Y(n2080) );
AOI22X1TS U4623 ( .A0(n3633), .A1(n2355), .B0(n3652), .B1(n2353), .Y(n3563)
);
BUFX3TS U4624 ( .A(n3561), .Y(n4560) );
INVX2TS U4625 ( .A(n3564), .Y(n3648) );
AOI22X1TS U4626 ( .A0(n2350), .A1(n3633), .B0(FPMULT_Add_result[8]), .B1(
n3648), .Y(n3566) );
OAI221XLTS U4627 ( .A0(n4560), .A1(FPMULT_P_Sgf[32]), .B0(n3641), .B1(n2357),
.C0(n2301), .Y(n3565) );
AOI22X1TS U4628 ( .A0(n2356), .A1(n3633), .B0(n2351), .B1(n3648), .Y(n3568)
);
OAI221XLTS U4629 ( .A0(n4560), .A1(FPMULT_P_Sgf[35]), .B0(n3641), .B1(n2347),
.C0(n2301), .Y(n3567) );
AOI22X1TS U4630 ( .A0(n2351), .A1(n3633), .B0(FPMULT_Add_result[10]), .B1(
n3652), .Y(n3570) );
OAI221XLTS U4631 ( .A0(n4560), .A1(n2347), .B0(n3641), .B1(n2346), .C0(n2199), .Y(n3569) );
AOI22X1TS U4632 ( .A0(FPMULT_Add_result[21]), .A1(n3633), .B0(
FPMULT_Add_result[20]), .B1(n3652), .Y(n3573) );
NAND2X1TS U4633 ( .A(n4582), .B(n2394), .Y(n3571) );
AOI22X1TS U4634 ( .A0(FPMULT_Add_result[15]), .A1(n3633), .B0(n2352), .B1(
n3652), .Y(n3575) );
OAI221XLTS U4635 ( .A0(n4560), .A1(FPMULT_P_Sgf[38]), .B0(n3641), .B1(n2348),
.C0(n2199), .Y(n3574) );
AOI22X1TS U4636 ( .A0(FPMULT_Add_result[10]), .A1(n3633), .B0(n2350), .B1(
n3652), .Y(n3577) );
OAI221XLTS U4637 ( .A0(n4560), .A1(n2346), .B0(n3641), .B1(FPMULT_P_Sgf[32]),
.C0(n2301), .Y(n3576) );
NOR2X1TS U4638 ( .A(n5162), .B(n5251), .Y(mult_x_309_n76) );
AOI21X1TS U4639 ( .A0(n3581), .A1(n3580), .B0(n3579), .Y(n3588) );
INVX2TS U4640 ( .A(n3190), .Y(n3582) );
AOI21X1TS U4641 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[4]), .A1(n5065), .B0(n3586),
.Y(n3587) );
OAI21XLTS U4642 ( .A0(n3588), .A1(n3582), .B0(n3587), .Y(n1345) );
NOR2X1TS U4643 ( .A(n5255), .B(n5171), .Y(n4691) );
AND3X1TS U4644 ( .A(n4691), .B(FPMULT_Op_MX[16]), .C(n2198), .Y(
mult_x_312_n26) );
NOR4X1TS U4645 ( .A(FPMULT_P_Sgf[16]), .B(FPMULT_P_Sgf[17]), .C(
FPMULT_P_Sgf[15]), .D(FPMULT_P_Sgf[13]), .Y(n3598) );
NOR4X1TS U4646 ( .A(FPMULT_P_Sgf[20]), .B(FPMULT_P_Sgf[18]), .C(
FPMULT_P_Sgf[19]), .D(FPMULT_P_Sgf[21]), .Y(n3597) );
NOR4X1TS U4647 ( .A(FPMULT_P_Sgf[1]), .B(FPMULT_P_Sgf[5]), .C(
FPMULT_P_Sgf[3]), .D(FPMULT_P_Sgf[4]), .Y(n3593) );
NOR3XLTS U4648 ( .A(FPMULT_P_Sgf[22]), .B(FPMULT_P_Sgf[2]), .C(
FPMULT_P_Sgf[0]), .Y(n3592) );
AND4X1TS U4649 ( .A(n3593), .B(n3592), .C(n3591), .D(n3590), .Y(n3596) );
XOR2X1TS U4650 ( .A(FPMULT_Op_MY[31]), .B(FPMULT_Op_MX[31]), .Y(n4996) );
MXI2X1TS U4651 ( .A(r_mode[0]), .B(r_mode[1]), .S0(n4996), .Y(n3594) );
AOI31X1TS U4652 ( .A0(n3598), .A1(n3597), .A2(n3596), .B0(n3595), .Y(n4382)
);
AOI31XLTS U4653 ( .A0(n3600), .A1(n4382), .A2(n3599), .B0(
FPMULT_FSM_selector_C), .Y(n3601) );
INVX2TS U4654 ( .A(n3601), .Y(n1528) );
BUFX3TS U4655 ( .A(n3602), .Y(n3655) );
AOI22X1TS U4656 ( .A0(n2364), .A1(n2303), .B0(n2301), .B1(n3603), .Y(n3606)
);
AOI22X1TS U4657 ( .A0(n3648), .A1(n2355), .B0(n3604), .B1(FPMULT_P_Sgf[29]),
.Y(n3605) );
AOI22X1TS U4658 ( .A0(n2367), .A1(n2303), .B0(n2301), .B1(n3607), .Y(n3609)
);
AOI22X1TS U4659 ( .A0(n3648), .A1(FPMULT_Add_result[17]), .B0(
FPMULT_P_Sgf[41]), .B1(n3604), .Y(n3608) );
AOI22X1TS U4660 ( .A0(FPMULT_Sgf_normalized_result[21]), .A1(n2303), .B0(
n2199), .B1(n3610), .Y(n3612) );
AOI22X1TS U4661 ( .A0(n3652), .A1(FPMULT_Add_result[21]), .B0(
FPMULT_P_Sgf[45]), .B1(n3604), .Y(n3611) );
AOI22X1TS U4662 ( .A0(FPMULT_Sgf_normalized_result[16]), .A1(n2303), .B0(
n2199), .B1(n3613), .Y(n3615) );
AOI22X1TS U4663 ( .A0(n3648), .A1(FPMULT_Add_result[16]), .B0(
FPMULT_P_Sgf[40]), .B1(n3604), .Y(n3614) );
AOI22X1TS U4664 ( .A0(FPMULT_Sgf_normalized_result[18]), .A1(n2303), .B0(
n2301), .B1(n3616), .Y(n3618) );
AOI22X1TS U4665 ( .A0(n3652), .A1(FPMULT_Add_result[18]), .B0(
FPMULT_P_Sgf[42]), .B1(n3604), .Y(n3617) );
AOI22X1TS U4666 ( .A0(n2360), .A1(n2303), .B0(n2199), .B1(n3619), .Y(n3621)
);
AOI22X1TS U4667 ( .A0(FPMULT_Add_result[15]), .A1(n3648), .B0(n3604), .B1(
FPMULT_P_Sgf[39]), .Y(n3620) );
AOI22X1TS U4668 ( .A0(FPMULT_Sgf_normalized_result[19]), .A1(n2302), .B0(
n2301), .B1(n3622), .Y(n3624) );
AOI22X1TS U4669 ( .A0(n3648), .A1(FPMULT_Add_result[19]), .B0(
FPMULT_P_Sgf[43]), .B1(n3604), .Y(n3623) );
AOI22X1TS U4670 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n2303), .B0(
n2199), .B1(n3625), .Y(n3627) );
AOI22X1TS U4671 ( .A0(n3652), .A1(FPMULT_Add_result[22]), .B0(
FPMULT_P_Sgf[46]), .B1(n3604), .Y(n3626) );
INVX2TS U4672 ( .A(FPMULT_Add_result[2]), .Y(n4945) );
AOI22X1TS U4673 ( .A0(n2359), .A1(n2303), .B0(n3633), .B1(
FPMULT_Add_result[3]), .Y(n3629) );
OAI221XLTS U4674 ( .A0(n4560), .A1(FPMULT_P_Sgf[26]), .B0(n3641), .B1(
FPMULT_P_Sgf[25]), .C0(n2199), .Y(n3628) );
INVX2TS U4675 ( .A(FPMULT_Add_result[13]), .Y(n4109) );
AOI22X1TS U4676 ( .A0(n2366), .A1(n2303), .B0(n2352), .B1(n3633), .Y(n3631)
);
OAI221XLTS U4677 ( .A0(n4560), .A1(n2348), .B0(n3641), .B1(FPMULT_P_Sgf[36]),
.C0(n2301), .Y(n3630) );
AOI22X1TS U4678 ( .A0(FPMULT_Sgf_normalized_result[3]), .A1(n2303), .B0(
n2301), .B1(n3632), .Y(n3635) );
AOI22X1TS U4679 ( .A0(n3633), .A1(n2353), .B0(n3604), .B1(FPMULT_P_Sgf[27]),
.Y(n3634) );
INVX2TS U4680 ( .A(n2290), .Y(n3636) );
BUFX3TS U4681 ( .A(n4780), .Y(n4811) );
NOR2X2TS U4682 ( .A(FPSENCOS_cont_iter_out[0]), .B(n4766), .Y(n4752) );
NAND2X1TS U4683 ( .A(n4752), .B(n5170), .Y(n4757) );
NOR2X1TS U4684 ( .A(n2225), .B(n4757), .Y(n3806) );
INVX2TS U4685 ( .A(n3637), .Y(n1762) );
INVX2TS U4686 ( .A(n3638), .Y(n1758) );
NAND2X1TS U4687 ( .A(FPSENCOS_cont_var_out[0]), .B(FPSENCOS_cont_var_out[1]),
.Y(n4724) );
OAI21XLTS U4688 ( .A0(n3639), .A1(n4725), .B0(n4784), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]) );
OR3X1TS U4689 ( .A(n2359), .B(FPMULT_Sgf_normalized_result[1]), .C(
FPMULT_Sgf_normalized_result[0]), .Y(n4947) );
NOR2X2TS U4690 ( .A(n5245), .B(n4955), .Y(n4954) );
OAI211XLTS U4691 ( .A0(n2365), .A1(n4954), .B0(n4991), .C0(n4957), .Y(n3640)
);
OAI21XLTS U4692 ( .A0(n5366), .A1(n4987), .B0(n3640), .Y(n1613) );
NOR2X1TS U4693 ( .A(n4669), .B(n5253), .Y(mult_x_309_n65) );
AOI22X1TS U4694 ( .A0(n2365), .A1(n2303), .B0(FPMULT_Add_result[7]), .B1(
n3652), .Y(n3643) );
NOR2X2TS U4695 ( .A(n3641), .B(n3366), .Y(n3651) );
AOI22X1TS U4696 ( .A0(n3651), .A1(FPMULT_P_Sgf[30]), .B0(n3604), .B1(n2357),
.Y(n3642) );
AOI22X1TS U4697 ( .A0(FPMULT_Sgf_normalized_result[6]), .A1(n2303), .B0(
n3651), .B1(FPMULT_P_Sgf[29]), .Y(n3645) );
AOI22X1TS U4698 ( .A0(n3652), .A1(FPMULT_Add_result[6]), .B0(n3604), .B1(
FPMULT_P_Sgf[30]), .Y(n3644) );
AOI22X1TS U4699 ( .A0(FPMULT_Sgf_normalized_result[0]), .A1(n2303), .B0(
n3604), .B1(FPMULT_P_Sgf[24]), .Y(n3647) );
AOI22X1TS U4700 ( .A0(n3652), .A1(FPMULT_Add_result[0]), .B0(n3651), .B1(
FPMULT_P_Sgf[23]), .Y(n3646) );
AOI22X1TS U4701 ( .A0(FPMULT_Sgf_normalized_result[12]), .A1(n2302), .B0(
n3604), .B1(FPMULT_P_Sgf[36]), .Y(n3650) );
AOI22X1TS U4702 ( .A0(n2356), .A1(n3648), .B0(n3651), .B1(FPMULT_P_Sgf[35]),
.Y(n3649) );
AOI22X1TS U4703 ( .A0(FPMULT_Sgf_normalized_result[1]), .A1(n2303), .B0(
n3651), .B1(FPMULT_P_Sgf[24]), .Y(n3654) );
AOI22X1TS U4704 ( .A0(n3652), .A1(FPMULT_Add_result[1]), .B0(n3604), .B1(
FPMULT_P_Sgf[25]), .Y(n3653) );
INVX2TS U4705 ( .A(n3656), .Y(n1764) );
NOR2X1TS U4706 ( .A(n4687), .B(n5171), .Y(mult_x_312_n67) );
INVX2TS U4707 ( .A(n3657), .Y(n1763) );
AOI211X1TS U4708 ( .A0(n3661), .A1(n3659), .B0(n3658), .C0(n5078), .Y(n3663)
);
AOI21X1TS U4709 ( .A0(n3662), .A1(n3661), .B0(n3582), .Y(n3660) );
OAI32X1TS U4710 ( .A0(n3663), .A1(n3662), .A2(n3661), .B0(n3660), .B1(n3663),
.Y(n3664) );
OAI21XLTS U4711 ( .A0(n5042), .A1(n5193), .B0(n3664), .Y(n1344) );
NOR2X1TS U4712 ( .A(n4696), .B(n5254), .Y(mult_x_312_n77) );
AOI2BB2XLTS U4713 ( .B0(n3668), .B1(n3665), .A0N(n3665), .A1N(n3668), .Y(
n3671) );
AOI21X1TS U4714 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[6]), .A1(n5065), .B0(n3669),
.Y(n3670) );
OAI21XLTS U4715 ( .A0(n3582), .A1(n3671), .B0(n3670), .Y(n1343) );
NOR2X1TS U4716 ( .A(n4677), .B(n5253), .Y(mult_x_309_n71) );
NAND2X1TS U4717 ( .A(FPMULT_Op_MX[17]), .B(n2198), .Y(n4692) );
NOR3X2TS U4718 ( .A(n4693), .B(n5163), .C(n4692), .Y(mult_x_312_n33) );
INVX3TS U4719 ( .A(n3790), .Y(n3686) );
BUFX3TS U4720 ( .A(n3801), .Y(n3804) );
INVX2TS U4721 ( .A(n3672), .Y(n1745) );
INVX2TS U4722 ( .A(n3673), .Y(n1742) );
INVX2TS U4723 ( .A(n3674), .Y(n1741) );
INVX2TS U4724 ( .A(n3675), .Y(n1744) );
INVX2TS U4725 ( .A(n3676), .Y(n1739) );
INVX2TS U4726 ( .A(n3677), .Y(n1740) );
INVX2TS U4727 ( .A(n3678), .Y(n1743) );
CLKBUFX3TS U4728 ( .A(n3801), .Y(n3792) );
INVX2TS U4729 ( .A(n3679), .Y(n1736) );
INVX2TS U4730 ( .A(n3680), .Y(n1737) );
INVX2TS U4731 ( .A(n3681), .Y(n1759) );
INVX2TS U4732 ( .A(n3682), .Y(n1734) );
INVX2TS U4733 ( .A(n3683), .Y(n1738) );
INVX2TS U4734 ( .A(n3684), .Y(n1733) );
INVX2TS U4735 ( .A(n3685), .Y(n1761) );
INVX2TS U4736 ( .A(n3687), .Y(n1735) );
AOI22X1TS U4737 ( .A0(FPADDSUB_intDX_EWSW[24]), .A1(n3705), .B0(
FPADDSUB_DMP_EXP_EWSW[24]), .B1(n5037), .Y(n3688) );
INVX2TS U4738 ( .A(n4734), .Y(n3689) );
CLKBUFX3TS U4739 ( .A(n3690), .Y(n4886) );
XNOR2X1TS U4740 ( .A(FPSENCOS_d_ff1_shift_region_flag_out[1]), .B(
FPSENCOS_d_ff1_operation_out), .Y(n3691) );
CLKXOR2X2TS U4741 ( .A(FPSENCOS_d_ff1_shift_region_flag_out[0]), .B(n3691),
.Y(n4882) );
INVX2TS U4742 ( .A(n4882), .Y(n4881) );
INVX2TS U4743 ( .A(n3692), .Y(n1722) );
INVX2TS U4744 ( .A(n3693), .Y(n1721) );
INVX2TS U4745 ( .A(n3694), .Y(n1720) );
AOI22X1TS U4746 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n3705), .B0(
FPADDSUB_DmP_EXP_EWSW[6]), .B1(n3716), .Y(n3695) );
AOI22X1TS U4747 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n3705), .B0(
FPADDSUB_DmP_EXP_EWSW[4]), .B1(n3716), .Y(n3696) );
BUFX3TS U4748 ( .A(n3716), .Y(n3982) );
AOI22X1TS U4749 ( .A0(FPADDSUB_intDY_EWSW[12]), .A1(n3705), .B0(
FPADDSUB_DmP_EXP_EWSW[12]), .B1(n3982), .Y(n3697) );
AOI22X1TS U4750 ( .A0(FPADDSUB_intDY_EWSW[19]), .A1(n3705), .B0(
FPADDSUB_DmP_EXP_EWSW[19]), .B1(n3716), .Y(n3698) );
AOI22X1TS U4751 ( .A0(FPADDSUB_intDY_EWSW[21]), .A1(n3705), .B0(
FPADDSUB_DmP_EXP_EWSW[21]), .B1(n3716), .Y(n3699) );
AOI22X1TS U4752 ( .A0(FPADDSUB_intDY_EWSW[18]), .A1(n3705), .B0(
FPADDSUB_DmP_EXP_EWSW[18]), .B1(n3716), .Y(n3700) );
AOI22X1TS U4753 ( .A0(FPADDSUB_intDY_EWSW[20]), .A1(n3705), .B0(
FPADDSUB_DmP_EXP_EWSW[20]), .B1(n3716), .Y(n3701) );
AOI22X1TS U4754 ( .A0(FPADDSUB_intDY_EWSW[15]), .A1(n3705), .B0(
FPADDSUB_DmP_EXP_EWSW[15]), .B1(n3716), .Y(n3702) );
AOI22X1TS U4755 ( .A0(FPADDSUB_intDY_EWSW[27]), .A1(n3705), .B0(
FPADDSUB_DmP_EXP_EWSW[27]), .B1(n3716), .Y(n3703) );
AOI22X1TS U4756 ( .A0(FPADDSUB_intDY_EWSW[22]), .A1(n3705), .B0(
FPADDSUB_DmP_EXP_EWSW[22]), .B1(n3716), .Y(n3704) );
AOI22X1TS U4757 ( .A0(FPADDSUB_intDY_EWSW[17]), .A1(n3705), .B0(
FPADDSUB_DmP_EXP_EWSW[17]), .B1(n3716), .Y(n3706) );
INVX4TS U4758 ( .A(n3981), .Y(n3786) );
AOI22X1TS U4759 ( .A0(FPADDSUB_intDY_EWSW[29]), .A1(n3786), .B0(
FPADDSUB_DMP_EXP_EWSW[29]), .B1(n5037), .Y(n3707) );
AOI22X1TS U4760 ( .A0(FPADDSUB_intDY_EWSW[30]), .A1(n3786), .B0(
FPADDSUB_DMP_EXP_EWSW[30]), .B1(n3716), .Y(n3708) );
BUFX3TS U4761 ( .A(n3716), .Y(n3979) );
AOI22X1TS U4762 ( .A0(FPADDSUB_intDY_EWSW[3]), .A1(n3786), .B0(
FPADDSUB_DMP_EXP_EWSW[3]), .B1(n3979), .Y(n3709) );
INVX2TS U4763 ( .A(n3981), .Y(n3896) );
AOI22X1TS U4764 ( .A0(FPADDSUB_intDY_EWSW[26]), .A1(n3896), .B0(
FPADDSUB_DMP_EXP_EWSW[26]), .B1(n5037), .Y(n3710) );
AOI22X1TS U4765 ( .A0(FPADDSUB_intDY_EWSW[25]), .A1(n3896), .B0(
FPADDSUB_DMP_EXP_EWSW[25]), .B1(n5037), .Y(n3711) );
AOI22X1TS U4766 ( .A0(FPADDSUB_intDY_EWSW[0]), .A1(n3786), .B0(
FPADDSUB_DMP_EXP_EWSW[0]), .B1(n3982), .Y(n3712) );
AOI22X1TS U4767 ( .A0(FPADDSUB_intDY_EWSW[2]), .A1(n3786), .B0(
FPADDSUB_DMP_EXP_EWSW[2]), .B1(n3979), .Y(n3713) );
AOI22X1TS U4768 ( .A0(FPADDSUB_intDY_EWSW[27]), .A1(n3786), .B0(n2354), .B1(
n3716), .Y(n3714) );
NOR2X1TS U4769 ( .A(n5255), .B(n5520), .Y(mult_x_312_n48) );
AOI22X1TS U4770 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n3786), .B0(
FPADDSUB_DMP_EXP_EWSW[7]), .B1(n3979), .Y(n3715) );
AOI22X1TS U4771 ( .A0(FPADDSUB_intDY_EWSW[28]), .A1(n3896), .B0(
FPADDSUB_DMP_EXP_EWSW[28]), .B1(n3716), .Y(n3717) );
NOR2XLTS U4772 ( .A(n5230), .B(n5360), .Y(FPMULT_S_Oper_A_exp[8]) );
NAND2X1TS U4773 ( .A(n5148), .B(n5026), .Y(n5137) );
INVX2TS U4774 ( .A(n5137), .Y(n3908) );
BUFX3TS U4775 ( .A(n3718), .Y(n3907) );
NAND2X1TS U4776 ( .A(n5176), .B(n3907), .Y(n5033) );
NOR3X1TS U4777 ( .A(FPADDSUB_shift_value_SHT2_EWR[2]), .B(
FPADDSUB_shift_value_SHT2_EWR[4]), .C(n5161), .Y(n3720) );
BUFX3TS U4778 ( .A(n3720), .Y(n5030) );
NAND2X1TS U4779 ( .A(FPADDSUB_shift_value_SHT2_EWR[2]), .B(n5161), .Y(n3749)
);
AO22XLTS U4780 ( .A0(FPADDSUB_Data_array_SWR[8]), .A1(n5030), .B0(n2322),
.B1(n5107), .Y(n3725) );
INVX2TS U4781 ( .A(n3749), .Y(n3740) );
AOI221X1TS U4782 ( .A0(FPADDSUB_shift_value_SHT2_EWR[3]), .A1(n5333), .B0(
n5161), .B1(n5226), .C0(FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n3722)
);
OAI2BB2XLTS U4783 ( .B0(n3760), .B1(n5176), .A0N(FPADDSUB_Data_array_SWR[10]), .A1N(n3723), .Y(n3724) );
NOR2X2TS U4784 ( .A(n3907), .B(n5312), .Y(n3903) );
OAI22X1TS U4785 ( .A0(n5114), .A1(n5148), .B0(n5115), .B1(n3726), .Y(n5146)
);
AND4X1TS U4786 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(FPADDSUB_exp_rslt_NRM2_EW1[1]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(n3727) );
AND4X1TS U4787 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(
n3727), .Y(n3728) );
OAI2BB1X1TS U4788 ( .A0N(n3730), .A1N(n3729), .B0(n5515), .Y(n4544) );
INVX2TS U4789 ( .A(n4544), .Y(n4546) );
AO22XLTS U4790 ( .A0(FPADDSUB_Data_array_SWR[10]), .A1(n5030), .B0(n2322),
.B1(n3719), .Y(n3734) );
OAI22X1TS U4791 ( .A0(n3922), .A1(n5176), .B0(n5226), .B1(n5029), .Y(n3733)
);
OAI2BB1X1TS U4792 ( .A0N(n3907), .A1N(FPADDSUB_Data_array_SWR[16]), .B0(
n3748), .Y(n3735) );
OAI22X1TS U4793 ( .A0(n3915), .A1(n2243), .B0(n3916), .B1(n3726), .Y(n5142)
);
AO22XLTS U4794 ( .A0(FPADDSUB_Data_array_SWR[12]), .A1(n5030), .B0(n2368),
.B1(n5107), .Y(n3738) );
OAI22X1TS U4795 ( .A0(n5115), .A1(n5176), .B0(n5336), .B1(n5029), .Y(n3737)
);
AOI211X1TS U4796 ( .A0(FPADDSUB_Data_array_SWR[7]), .A1(n3719), .B0(n3738),
.C0(n3737), .Y(n3759) );
OAI22X1TS U4797 ( .A0(n3760), .A1(n3726), .B0(n3759), .B1(n5148), .Y(n5139)
);
AOI22X1TS U4798 ( .A0(FPADDSUB_Data_array_SWR[18]), .A1(n3740), .B0(
FPADDSUB_Data_array_SWR[14]), .B1(n3907), .Y(n3741) );
NAND2X1TS U4799 ( .A(n3741), .B(n3748), .Y(n3754) );
AO22XLTS U4800 ( .A0(FPADDSUB_Data_array_SWR[11]), .A1(n3723), .B0(
FPADDSUB_Data_array_SWR[9]), .B1(n5030), .Y(n3743) );
AO22XLTS U4801 ( .A0(FPADDSUB_Data_array_SWR[5]), .A1(n5107), .B0(
FPADDSUB_Data_array_SWR[2]), .B1(n3719), .Y(n3742) );
AOI211X1TS U4802 ( .A0(FPADDSUB_shift_value_SHT2_EWR[4]), .A1(n3754), .B0(
n3743), .C0(n3742), .Y(n3918) );
OAI22X1TS U4803 ( .A0(n3918), .A1(n5148), .B0(n3919), .B1(n3726), .Y(n5145)
);
INVX4TS U4804 ( .A(n5353), .Y(n5023) );
AO22XLTS U4805 ( .A0(FPADDSUB_Data_array_SWR[12]), .A1(n3723), .B0(n2368),
.B1(n5030), .Y(n3746) );
INVX2TS U4806 ( .A(n5107), .Y(n5013) );
OAI22X1TS U4807 ( .A0(n3916), .A1(n5176), .B0(n5354), .B1(n5013), .Y(n3745)
);
OAI22X1TS U4808 ( .A0(n3922), .A1(n3726), .B0(n3921), .B1(n5148), .Y(n5143)
);
AO22XLTS U4809 ( .A0(FPADDSUB_Data_array_SWR[14]), .A1(n3723), .B0(
FPADDSUB_Data_array_SWR[5]), .B1(n3719), .Y(n3752) );
INVX2TS U4810 ( .A(n5030), .Y(n5108) );
OAI22X1TS U4811 ( .A0(n3928), .A1(n5176), .B0(n5352), .B1(n5108), .Y(n3751)
);
OAI22X1TS U4812 ( .A0(n3911), .A1(n3726), .B0(n3910), .B1(n5148), .Y(n5141)
);
INVX2TS U4813 ( .A(n3754), .Y(n3925) );
AOI22X1TS U4814 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n3723), .B0(
FPADDSUB_Data_array_SWR[6]), .B1(n3719), .Y(n3756) );
AOI22X1TS U4815 ( .A0(n2369), .A1(n5030), .B0(n2361), .B1(n5107), .Y(n3755)
);
OAI211X1TS U4816 ( .A0(n3919), .A1(n5176), .B0(n3756), .C0(n3755), .Y(n3924)
);
OAI2BB2X1TS U4817 ( .B0(n3726), .B1(n3925), .A0N(n2286), .A1N(n3924), .Y(
n5140) );
NAND2X1TS U4818 ( .A(n2285), .B(n5026), .Y(n5112) );
INVX2TS U4819 ( .A(n5112), .Y(n3929) );
OAI22X1TS U4820 ( .A0(n3760), .A1(n3758), .B0(n2286), .B1(n3759), .Y(n5124)
);
CLKBUFX3TS U4821 ( .A(n3814), .Y(n3771) );
INVX4TS U4822 ( .A(n3981), .Y(n3788) );
AOI22X1TS U4823 ( .A0(FPADDSUB_intDY_EWSW[4]), .A1(n3788), .B0(
FPADDSUB_DMP_EXP_EWSW[4]), .B1(n5225), .Y(n3762) );
AOI22X1TS U4824 ( .A0(FPADDSUB_intDY_EWSW[6]), .A1(n3788), .B0(
FPADDSUB_DMP_EXP_EWSW[6]), .B1(n5225), .Y(n3763) );
AOI22X1TS U4825 ( .A0(FPADDSUB_intDY_EWSW[19]), .A1(n3788), .B0(
FPADDSUB_DMP_EXP_EWSW[19]), .B1(n5225), .Y(n3764) );
AOI22X1TS U4826 ( .A0(FPADDSUB_intDY_EWSW[21]), .A1(n3788), .B0(
FPADDSUB_DMP_EXP_EWSW[21]), .B1(n5225), .Y(n3765) );
AOI22X1TS U4827 ( .A0(FPADDSUB_intDY_EWSW[18]), .A1(n3788), .B0(
FPADDSUB_DMP_EXP_EWSW[18]), .B1(n5225), .Y(n3766) );
AOI22X1TS U4828 ( .A0(FPADDSUB_intDY_EWSW[22]), .A1(n3786), .B0(
FPADDSUB_DMP_EXP_EWSW[22]), .B1(n3979), .Y(n3767) );
AOI22X1TS U4829 ( .A0(FPADDSUB_intDY_EWSW[15]), .A1(n3788), .B0(
FPADDSUB_DMP_EXP_EWSW[15]), .B1(n5225), .Y(n3768) );
AOI22X1TS U4830 ( .A0(FPADDSUB_intDY_EWSW[17]), .A1(n3788), .B0(
FPADDSUB_DMP_EXP_EWSW[17]), .B1(n5225), .Y(n3769) );
AOI22X1TS U4831 ( .A0(FPADDSUB_intDY_EWSW[20]), .A1(n3788), .B0(
FPADDSUB_DMP_EXP_EWSW[20]), .B1(n5225), .Y(n3770) );
CLKBUFX3TS U4832 ( .A(n3812), .Y(n3955) );
INVX2TS U4833 ( .A(n3772), .Y(n1719) );
BUFX3TS U4834 ( .A(n3690), .Y(n3946) );
INVX2TS U4835 ( .A(n3773), .Y(n1716) );
INVX2TS U4836 ( .A(n3775), .Y(n1717) );
INVX2TS U4837 ( .A(n3776), .Y(n1718) );
BUFX3TS U4838 ( .A(n3814), .Y(n3966) );
AOI22X1TS U4839 ( .A0(FPADDSUB_intDY_EWSW[11]), .A1(n3788), .B0(
FPADDSUB_DMP_EXP_EWSW[11]), .B1(n3982), .Y(n3778) );
AOI22X1TS U4840 ( .A0(FPADDSUB_intDY_EWSW[8]), .A1(n3788), .B0(
FPADDSUB_DMP_EXP_EWSW[8]), .B1(n5225), .Y(n3779) );
AOI22X1TS U4841 ( .A0(FPADDSUB_intDY_EWSW[12]), .A1(n3786), .B0(
FPADDSUB_DMP_EXP_EWSW[12]), .B1(n3982), .Y(n3780) );
AOI22X1TS U4842 ( .A0(FPADDSUB_intDY_EWSW[13]), .A1(n3788), .B0(
FPADDSUB_DMP_EXP_EWSW[13]), .B1(n5225), .Y(n3781) );
AOI22X1TS U4843 ( .A0(FPADDSUB_intDY_EWSW[9]), .A1(n3786), .B0(
FPADDSUB_DMP_EXP_EWSW[9]), .B1(n3982), .Y(n3782) );
AOI22X1TS U4844 ( .A0(FPADDSUB_intDY_EWSW[1]), .A1(n3786), .B0(
FPADDSUB_DMP_EXP_EWSW[1]), .B1(n3982), .Y(n3783) );
AOI22X1TS U4845 ( .A0(FPADDSUB_intDY_EWSW[14]), .A1(n3788), .B0(
FPADDSUB_DMP_EXP_EWSW[14]), .B1(n3982), .Y(n3784) );
AOI22X1TS U4846 ( .A0(FPADDSUB_intDY_EWSW[5]), .A1(n3786), .B0(
FPADDSUB_DMP_EXP_EWSW[5]), .B1(n3982), .Y(n3785) );
AOI22X1TS U4847 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n3786), .B0(
FPADDSUB_DMP_EXP_EWSW[10]), .B1(n3982), .Y(n3787) );
AOI22X1TS U4848 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n3788), .B0(
FPADDSUB_DMP_EXP_EWSW[16]), .B1(n5225), .Y(n3789) );
BUFX3TS U4849 ( .A(n3790), .Y(n4783) );
INVX2TS U4850 ( .A(n3791), .Y(n1756) );
INVX2TS U4851 ( .A(n3793), .Y(n1760) );
INVX2TS U4852 ( .A(n3794), .Y(n1749) );
INVX2TS U4853 ( .A(n3795), .Y(n1753) );
INVX2TS U4854 ( .A(n3796), .Y(n1751) );
INVX2TS U4855 ( .A(n3797), .Y(n1747) );
INVX2TS U4856 ( .A(n3798), .Y(n1748) );
INVX2TS U4857 ( .A(n3799), .Y(n1752) );
INVX2TS U4858 ( .A(n3800), .Y(n1755) );
INVX2TS U4859 ( .A(n3802), .Y(n1757) );
INVX2TS U4860 ( .A(n3803), .Y(n1746) );
INVX2TS U4861 ( .A(n3805), .Y(n1750) );
INVX2TS U4862 ( .A(n3808), .Y(n1754) );
INVX2TS U4863 ( .A(n3809), .Y(n1725) );
INVX2TS U4864 ( .A(n3810), .Y(n1715) );
INVX2TS U4865 ( .A(n3811), .Y(n1726) );
INVX2TS U4866 ( .A(n3813), .Y(n1723) );
INVX2TS U4867 ( .A(n3814), .Y(n3897) );
AOI222X1TS U4868 ( .A0(n3896), .A1(FPADDSUB_intDY_EWSW[23]), .B0(
FPADDSUB_DMP_EXP_EWSW[23]), .B1(n5037), .C0(FPADDSUB_intDX_EWSW[23]),
.C1(n3897), .Y(n3815) );
INVX2TS U4869 ( .A(n3815), .Y(n1465) );
NAND2X1TS U4870 ( .A(FPMULT_Op_MY[6]), .B(n2196), .Y(n4472) );
NAND2X1TS U4871 ( .A(n4924), .B(n4904), .Y(n4471) );
NOR2X2TS U4872 ( .A(n4472), .B(n4471), .Y(n4470) );
INVX2TS U4873 ( .A(n4470), .Y(n3821) );
NAND2X1TS U4874 ( .A(n4924), .B(n2196), .Y(n3817) );
NAND2X1TS U4875 ( .A(n4902), .B(FPMULT_Op_MY[6]), .Y(n3816) );
NAND2X1TS U4876 ( .A(n4902), .B(n4924), .Y(n3829) );
NOR2X2TS U4877 ( .A(n4472), .B(n3829), .Y(n3842) );
INVX2TS U4878 ( .A(n4443), .Y(n3820) );
XOR2X1TS U4879 ( .A(n3818), .B(n3832), .Y(n4445) );
OAI21X1TS U4880 ( .A0(n3821), .A1(n3820), .B0(n3819), .Y(mult_x_311_n36) );
NOR2XLTS U4881 ( .A(n3837), .B(n3846), .Y(n3825) );
NAND2X1TS U4882 ( .A(n4904), .B(FPMULT_Op_MY[11]), .Y(n4422) );
NOR3X1TS U4883 ( .A(n5270), .B(n5168), .C(n4422), .Y(n3823) );
NAND2X1TS U4884 ( .A(n4904), .B(FPMULT_Op_MY[9]), .Y(n3822) );
OAI32X1TS U4885 ( .A0(n3823), .A1(n5158), .A2(n5270), .B0(n3822), .B1(n3823),
.Y(n3824) );
OA21X1TS U4886 ( .A0(n3825), .A1(n3824), .B0(n3845), .Y(n4466) );
INVX2TS U4887 ( .A(n4466), .Y(n3836) );
NAND2X1TS U4888 ( .A(FPMULT_Op_MY[6]), .B(n4901), .Y(n3828) );
NAND2X1TS U4889 ( .A(n4901), .B(n4924), .Y(n3847) );
INVX2TS U4890 ( .A(n3847), .Y(n3826) );
NAND3X1TS U4891 ( .A(FPMULT_Op_MY[6]), .B(n4902), .C(n3826), .Y(n4433) );
INVX2TS U4892 ( .A(n4433), .Y(n3827) );
INVX2TS U4893 ( .A(n4463), .Y(n3835) );
OAI2BB1X1TS U4894 ( .A0N(n3832), .A1N(n3831), .B0(n3830), .Y(n3841) );
NOR2X2TS U4895 ( .A(n5173), .B(n5262), .Y(n4426) );
XOR2X1TS U4896 ( .A(n4426), .B(n3842), .Y(n3833) );
XOR2X1TS U4897 ( .A(n3841), .B(n3833), .Y(n4464) );
OAI21X1TS U4898 ( .A0(n3836), .A1(n3835), .B0(n3834), .Y(mult_x_311_n29) );
INVX2TS U4899 ( .A(n4422), .Y(n4425) );
AOI22X1TS U4900 ( .A0(FPMULT_Op_MX[7]), .A1(FPMULT_Op_MY[11]), .B0(n4904),
.B1(FPMULT_Op_MY[10]), .Y(n3838) );
AOI21X1TS U4901 ( .A0(n4426), .A1(n4425), .B0(n3838), .Y(n3839) );
OA21X1TS U4902 ( .A0(n3840), .A1(n3839), .B0(n4424), .Y(n4462) );
INVX2TS U4903 ( .A(n4462), .Y(n3853) );
NAND2X1TS U4904 ( .A(n4426), .B(n3842), .Y(n3843) );
NAND2X1TS U4905 ( .A(n3844), .B(n3843), .Y(n4459) );
INVX2TS U4906 ( .A(n4459), .Y(n3852) );
NOR2X1TS U4907 ( .A(n5270), .B(n5168), .Y(n4448) );
OAI2BB1X1TS U4908 ( .A0N(n4448), .A1N(n4425), .B0(n3845), .Y(n4435) );
NOR2X1TS U4909 ( .A(n2378), .B(n3846), .Y(n4442) );
NAND2X1TS U4910 ( .A(n4923), .B(n4902), .Y(n3848) );
NAND2X1TS U4911 ( .A(n3848), .B(n3847), .Y(n3849) );
NAND2X1TS U4912 ( .A(n4437), .B(n3849), .Y(n4434) );
XNOR2X1TS U4913 ( .A(n4434), .B(n4433), .Y(n3850) );
XNOR2X1TS U4914 ( .A(n4435), .B(n3850), .Y(n4460) );
NAND2X1TS U4915 ( .A(FPSENCOS_cont_iter_out[2]), .B(n5313), .Y(n4762) );
AOI22X1TS U4916 ( .A0(n4761), .A1(n4754), .B0(FPSENCOS_d_ff3_LUT_out[2]),
.B1(n4784), .Y(n3854) );
OAI31X1TS U4917 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n4784), .A2(n4762),
.B0(n3854), .Y(n2131) );
NAND2X1TS U4918 ( .A(n4922), .B(n4907), .Y(n4521) );
NAND2X1TS U4919 ( .A(n4921), .B(n4908), .Y(n4520) );
NOR2X2TS U4920 ( .A(n4521), .B(n4520), .Y(n4519) );
INVX2TS U4921 ( .A(n4519), .Y(n3860) );
NAND2X1TS U4922 ( .A(n4921), .B(n4907), .Y(n3856) );
NAND2X1TS U4923 ( .A(n4906), .B(n4922), .Y(n3855) );
NAND2X1TS U4924 ( .A(n4906), .B(n4921), .Y(n3868) );
NOR2X2TS U4925 ( .A(n4521), .B(n3868), .Y(n3881) );
INVX2TS U4926 ( .A(n4494), .Y(n3859) );
XOR2X1TS U4927 ( .A(n3857), .B(n3871), .Y(n4496) );
OAI21XLTS U4928 ( .A0(n4494), .A1(n4519), .B0(n4496), .Y(n3858) );
NOR2XLTS U4929 ( .A(n3876), .B(n3885), .Y(n3864) );
NAND2X1TS U4930 ( .A(n4908), .B(FPMULT_Op_MY[5]), .Y(n4473) );
NOR3X1TS U4931 ( .A(n5269), .B(n5159), .C(n4473), .Y(n3862) );
NAND2X1TS U4932 ( .A(n4908), .B(FPMULT_Op_MY[3]), .Y(n3861) );
OAI32X1TS U4933 ( .A0(n3862), .A1(n5169), .A2(n5269), .B0(n3861), .B1(n3862),
.Y(n3863) );
OA21X1TS U4934 ( .A0(n3864), .A1(n3863), .B0(n3884), .Y(n4515) );
INVX2TS U4935 ( .A(n4515), .Y(n3875) );
NAND2X1TS U4936 ( .A(n4922), .B(FPMULT_Op_MX[5]), .Y(n3867) );
NAND2X1TS U4937 ( .A(FPMULT_Op_MX[5]), .B(n4921), .Y(n3886) );
INVX2TS U4938 ( .A(n3886), .Y(n3865) );
NAND3X1TS U4939 ( .A(n4922), .B(n4906), .C(n3865), .Y(n4484) );
INVX2TS U4940 ( .A(n4512), .Y(n3874) );
OAI2BB1X1TS U4941 ( .A0N(n3871), .A1N(n3870), .B0(n3869), .Y(n3880) );
NOR2X2TS U4942 ( .A(n5192), .B(n5261), .Y(n4477) );
XOR2XLTS U4943 ( .A(n4477), .B(n3881), .Y(n3872) );
XOR2X1TS U4944 ( .A(n3880), .B(n3872), .Y(n4513) );
OAI21X1TS U4945 ( .A0(n3875), .A1(n3874), .B0(n3873), .Y(mult_x_310_n29) );
NOR2XLTS U4946 ( .A(n3876), .B(n5159), .Y(n3879) );
INVX2TS U4947 ( .A(n4473), .Y(n4476) );
AOI22X1TS U4948 ( .A0(FPMULT_Op_MX[1]), .A1(FPMULT_Op_MY[5]), .B0(n4908),
.B1(FPMULT_Op_MY[4]), .Y(n3877) );
AOI21X1TS U4949 ( .A0(n4477), .A1(n4476), .B0(n3877), .Y(n3878) );
OA21X1TS U4950 ( .A0(n3879), .A1(n3878), .B0(n4475), .Y(n4511) );
INVX2TS U4951 ( .A(n4511), .Y(n3892) );
NAND2X1TS U4952 ( .A(n4477), .B(n3881), .Y(n3882) );
NAND2X1TS U4953 ( .A(n3883), .B(n3882), .Y(n4508) );
INVX2TS U4954 ( .A(n4508), .Y(n3891) );
NOR2X1TS U4955 ( .A(n5269), .B(n5159), .Y(n4498) );
OAI2BB1X1TS U4956 ( .A0N(n4498), .A1N(n4476), .B0(n3884), .Y(n4486) );
NOR2X1TS U4957 ( .A(n2383), .B(n3885), .Y(n4493) );
NAND2X1TS U4958 ( .A(n4925), .B(n4906), .Y(n3887) );
NAND2X1TS U4959 ( .A(n3887), .B(n3886), .Y(n3888) );
NAND2X1TS U4960 ( .A(n4488), .B(n3888), .Y(n4485) );
XNOR2X1TS U4961 ( .A(n4485), .B(n4484), .Y(n3889) );
XNOR2X1TS U4962 ( .A(n4486), .B(n3889), .Y(n4509) );
AOI222X1TS U4963 ( .A0(n3897), .A1(FPADDSUB_intDY_EWSW[25]), .B0(
FPADDSUB_DmP_EXP_EWSW[25]), .B1(n5037), .C0(FPADDSUB_intDX_EWSW[25]),
.C1(n3896), .Y(n3893) );
INVX2TS U4964 ( .A(n3893), .Y(n1415) );
AOI222X1TS U4965 ( .A0(n3897), .A1(FPADDSUB_intDY_EWSW[24]), .B0(
FPADDSUB_DmP_EXP_EWSW[24]), .B1(n5037), .C0(FPADDSUB_intDX_EWSW[24]),
.C1(n3896), .Y(n3894) );
INVX2TS U4966 ( .A(n3894), .Y(n1416) );
AOI222X1TS U4967 ( .A0(n3897), .A1(FPADDSUB_intDY_EWSW[26]), .B0(
FPADDSUB_DmP_EXP_EWSW[26]), .B1(n5037), .C0(FPADDSUB_intDX_EWSW[26]),
.C1(n3896), .Y(n3895) );
INVX2TS U4968 ( .A(n3895), .Y(n1414) );
AOI222X1TS U4969 ( .A0(n3897), .A1(FPADDSUB_intDY_EWSW[23]), .B0(
FPADDSUB_DmP_EXP_EWSW[23]), .B1(n5037), .C0(FPADDSUB_intDX_EWSW[23]),
.C1(n3896), .Y(n3898) );
INVX2TS U4970 ( .A(n3898), .Y(n1417) );
AO22XLTS U4971 ( .A0(n2369), .A1(n3723), .B0(FPADDSUB_Data_array_SWR[3]),
.B1(n3719), .Y(n3900) );
OAI2BB2XLTS U4972 ( .B0(n3911), .B1(n5176), .A0N(n2361), .A1N(n5030), .Y(
n3899) );
OAI22X1TS U4973 ( .A0(n3927), .A1(n5148), .B0(n3928), .B1(n3726), .Y(n5144)
);
BUFX3TS U4974 ( .A(n3901), .Y(n5016) );
AO22XLTS U4975 ( .A0(FPADDSUB_Data_array_SWR[17]), .A1(n3723), .B0(
FPADDSUB_Data_array_SWR[8]), .B1(n3719), .Y(n3905) );
OAI22X1TS U4976 ( .A0(n5150), .A1(n5176), .B0(n5226), .B1(n5108), .Y(n3904)
);
OAI33X1TS U4977 ( .A0(FPADDSUB_shift_value_SHT2_EWR[2]), .A1(n5229), .A2(
n5161), .B0(n5177), .B1(n5336), .B2(FPADDSUB_shift_value_SHT2_EWR[3]),
.Y(n3906) );
OAI22X1TS U4978 ( .A0(n3913), .A1(n5148), .B0(n5109), .B1(n3726), .Y(n5138)
);
OAI22X1TS U4979 ( .A0(n3911), .A1(n3758), .B0(n2285), .B1(n3910), .Y(n5122)
);
OAI22X1TS U4980 ( .A0(n2286), .A1(n3913), .B0(n5109), .B1(n3758), .Y(n5125)
);
OAI22X1TS U4981 ( .A0(n3916), .A1(n3758), .B0(n2285), .B1(n3915), .Y(n5121)
);
OAI22X1TS U4982 ( .A0(n3919), .A1(n3758), .B0(FPADDSUB_left_right_SHT2),
.B1(n3918), .Y(n5117) );
OAI22X1TS U4983 ( .A0(n3922), .A1(n3758), .B0(n2286), .B1(n3921), .Y(n5119)
);
OAI2BB2X1TS U4984 ( .B0(n3758), .B1(n3925), .A0N(n5148), .A1N(n3924), .Y(
n5123) );
OAI22X1TS U4985 ( .A0(n3928), .A1(n3758), .B0(n2286), .B1(n3927), .Y(n5118)
);
NOR2X1TS U4986 ( .A(n4759), .B(n5191), .Y(n4758) );
AOI22X1TS U4987 ( .A0(n4761), .A1(n2298), .B0(FPSENCOS_d_ff3_LUT_out[24]),
.B1(n4784), .Y(n3931) );
OAI31X1TS U4988 ( .A0(FPSENCOS_cont_iter_out[1]), .A1(n4758), .A2(n4784),
.B0(n3931), .Y(n2116) );
BUFX3TS U4989 ( .A(n3945), .Y(n3943) );
INVX2TS U4990 ( .A(n3932), .Y(n1704) );
INVX2TS U4991 ( .A(n3933), .Y(n1714) );
INVX2TS U4992 ( .A(n3934), .Y(n1708) );
INVX2TS U4993 ( .A(n3935), .Y(n1707) );
INVX2TS U4994 ( .A(n3936), .Y(n1713) );
INVX2TS U4995 ( .A(n3937), .Y(n1703) );
INVX2TS U4996 ( .A(n3938), .Y(n1710) );
INVX2TS U4997 ( .A(n3939), .Y(n1711) );
INVX2TS U4998 ( .A(n3940), .Y(n1712) );
INVX2TS U4999 ( .A(n3941), .Y(n1706) );
INVX2TS U5000 ( .A(n3942), .Y(n1709) );
INVX2TS U5001 ( .A(n3944), .Y(n1705) );
INVX2TS U5002 ( .A(n3947), .Y(n1702) );
INVX2TS U5003 ( .A(n3948), .Y(n1696) );
INVX2TS U5004 ( .A(n3949), .Y(n1700) );
INVX2TS U5005 ( .A(n3950), .Y(n1697) );
INVX2TS U5006 ( .A(n3951), .Y(n1724) );
INVX2TS U5007 ( .A(n3953), .Y(n1701) );
INVX2TS U5008 ( .A(n3954), .Y(n1699) );
INVX2TS U5009 ( .A(n3956), .Y(n1698) );
AOI21X1TS U5010 ( .A0(n3959), .A1(n3958), .B0(n3957), .Y(n3965) );
AOI21X1TS U5011 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[9]), .A1(n5065), .B0(n3963),
.Y(n3964) );
INVX4TS U5012 ( .A(n3966), .Y(n3983) );
AOI22X1TS U5013 ( .A0(FPADDSUB_intDY_EWSW[8]), .A1(n3983), .B0(
FPADDSUB_DmP_EXP_EWSW[8]), .B1(n3979), .Y(n3967) );
AOI22X1TS U5014 ( .A0(FPADDSUB_intDY_EWSW[11]), .A1(n3983), .B0(
FPADDSUB_DmP_EXP_EWSW[11]), .B1(n3979), .Y(n3968) );
AOI22X1TS U5015 ( .A0(FPADDSUB_intDY_EWSW[13]), .A1(n3983), .B0(
FPADDSUB_DmP_EXP_EWSW[13]), .B1(n3979), .Y(n3969) );
AOI22X1TS U5016 ( .A0(FPADDSUB_intDY_EWSW[3]), .A1(n3983), .B0(
FPADDSUB_DmP_EXP_EWSW[3]), .B1(n3979), .Y(n3970) );
AOI22X1TS U5017 ( .A0(FPADDSUB_intDY_EWSW[14]), .A1(n3983), .B0(
FPADDSUB_DmP_EXP_EWSW[14]), .B1(n3979), .Y(n3971) );
AOI22X1TS U5018 ( .A0(FPADDSUB_intDY_EWSW[1]), .A1(n3983), .B0(
FPADDSUB_DmP_EXP_EWSW[1]), .B1(n3982), .Y(n3972) );
AOI22X1TS U5019 ( .A0(FPADDSUB_intDY_EWSW[0]), .A1(n3983), .B0(
FPADDSUB_DmP_EXP_EWSW[0]), .B1(n3982), .Y(n3973) );
AOI22X1TS U5020 ( .A0(FPADDSUB_intDY_EWSW[9]), .A1(n3983), .B0(
FPADDSUB_DmP_EXP_EWSW[9]), .B1(n3982), .Y(n3974) );
AOI22X1TS U5021 ( .A0(FPADDSUB_intDY_EWSW[16]), .A1(n3983), .B0(
FPADDSUB_DmP_EXP_EWSW[16]), .B1(n3979), .Y(n3975) );
AOI22X1TS U5022 ( .A0(FPADDSUB_intDY_EWSW[2]), .A1(n3983), .B0(
FPADDSUB_DmP_EXP_EWSW[2]), .B1(n3979), .Y(n3977) );
AOI22X1TS U5023 ( .A0(FPADDSUB_intDY_EWSW[10]), .A1(n3983), .B0(
FPADDSUB_DmP_EXP_EWSW[10]), .B1(n3979), .Y(n3978) );
AOI22X1TS U5024 ( .A0(FPADDSUB_intDY_EWSW[7]), .A1(n3983), .B0(
FPADDSUB_DmP_EXP_EWSW[7]), .B1(n3979), .Y(n3980) );
AOI22X1TS U5025 ( .A0(FPADDSUB_intDY_EWSW[5]), .A1(n3983), .B0(
FPADDSUB_DmP_EXP_EWSW[5]), .B1(n3982), .Y(n3984) );
INVX2TS U5026 ( .A(n4766), .Y(n3987) );
NOR3XLTS U5027 ( .A(FPSENCOS_cont_iter_out[2]), .B(n5313), .C(n5172), .Y(
n3985) );
OAI31X1TS U5028 ( .A0(n3987), .A1(n5191), .A2(n4110), .B0(n3986), .Y(n2127)
);
AOI21X1TS U5029 ( .A0(n3990), .A1(n3989), .B0(n3988), .Y(n3995) );
AOI21X1TS U5030 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[10]), .A1(n5065), .B0(n2222),
.Y(n3994) );
OR4X2TS U5031 ( .A(FPADDSUB_Raw_mant_NRM_SWR[21]), .B(
FPADDSUB_Raw_mant_NRM_SWR[20]), .C(FPADDSUB_Raw_mant_NRM_SWR[19]), .D(
n4391), .Y(n4009) );
NOR2X2TS U5032 ( .A(n4009), .B(FPADDSUB_Raw_mant_NRM_SWR[18]), .Y(n4374) );
NOR4BX2TS U5033 ( .AN(n4374), .B(FPADDSUB_Raw_mant_NRM_SWR[17]), .C(
FPADDSUB_Raw_mant_NRM_SWR[16]), .D(FPADDSUB_Raw_mant_NRM_SWR[15]), .Y(
n4017) );
NOR2X1TS U5034 ( .A(FPADDSUB_Raw_mant_NRM_SWR[21]), .B(
FPADDSUB_Raw_mant_NRM_SWR[20]), .Y(n3997) );
NOR2BX1TS U5035 ( .AN(n4017), .B(FPADDSUB_Raw_mant_NRM_SWR[14]), .Y(n4386)
);
NAND2X1TS U5036 ( .A(n4386), .B(n5186), .Y(n4016) );
NAND2X1TS U5037 ( .A(n5186), .B(n5166), .Y(n4385) );
NOR3X1TS U5038 ( .A(FPADDSUB_Raw_mant_NRM_SWR[17]), .B(
FPADDSUB_Raw_mant_NRM_SWR[16]), .C(FPADDSUB_Raw_mant_NRM_SWR[15]), .Y(
n4000) );
NOR2X1TS U5039 ( .A(FPADDSUB_Raw_mant_NRM_SWR[10]), .B(n4001), .Y(n4372) );
NAND2X1TS U5040 ( .A(n4374), .B(n4372), .Y(n4376) );
NOR3X2TS U5041 ( .A(FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
FPADDSUB_Raw_mant_NRM_SWR[8]), .C(n4376), .Y(n4011) );
NOR2X1TS U5042 ( .A(FPADDSUB_Raw_mant_NRM_SWR[2]), .B(
FPADDSUB_Raw_mant_NRM_SWR[3]), .Y(n4368) );
OAI31X1TS U5043 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[5]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[4]), .A2(n4368), .B0(n4370), .Y(n4002) );
OAI32X1TS U5044 ( .A0(n4009), .A1(n5174), .A2(n4001), .B0(n5272), .B1(n4009),
.Y(n4012) );
AOI211X1TS U5045 ( .A0(n4011), .A1(n4002), .B0(n4012), .C0(n5034), .Y(n4003)
);
OAI31X1TS U5046 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[12]), .A1(n5166), .A2(n4016),
.B0(n4003), .Y(n4004) );
AOI211X1TS U5047 ( .A0(n4017), .A1(FPADDSUB_Raw_mant_NRM_SWR[14]), .B0(n4005), .C0(n4004), .Y(n4536) );
AOI211X1TS U5048 ( .A0(n4539), .A1(n5337), .B0(n4536), .C0(n4006), .Y(n4024)
);
INVX4TS U5049 ( .A(n3536), .Y(n4126) );
NOR2X1TS U5050 ( .A(n4024), .B(n4126), .Y(n4022) );
OAI32X1TS U5051 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[23]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[21]), .A2(n5258), .B0(n5187), .B1(
FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n4007) );
OAI31X1TS U5052 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[17]), .A1(n5266), .A2(n4009),
.B0(n4008), .Y(n4010) );
NAND2X1TS U5053 ( .A(n4011), .B(n4370), .Y(n4384) );
OAI21X1TS U5054 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[4]), .A1(n5282), .B0(n5193),
.Y(n4387) );
OAI31X1TS U5055 ( .A0(n4014), .A1(n4384), .A2(n4387), .B0(n4013), .Y(n4015)
);
AOI2BB1X1TS U5056 ( .A0N(n5167), .A1N(n4016), .B0(n4015), .Y(n4390) );
NOR4X1TS U5057 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(
FPADDSUB_Raw_mant_NRM_SWR[11]), .C(FPADDSUB_Raw_mant_NRM_SWR[9]), .D(
n5264), .Y(n4018) );
AOI31X1TS U5058 ( .A0(n4020), .A1(n4390), .A2(n4019), .B0(n5034), .Y(n4538)
);
AOI21X1TS U5059 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[0]), .A1(n4539), .B0(
n4538), .Y(n4072) );
NAND2X2TS U5060 ( .A(n4072), .B(n4048), .Y(n4027) );
OAI222X1TS U5061 ( .A0(FPADDSUB_DmP_mant_SHT1_SW[5]), .A1(
FPADDSUB_Shift_reg_FLAGS_7[1]), .B0(FPADDSUB_Raw_mant_NRM_SWR[18]),
.B1(n4065), .C0(FPADDSUB_Raw_mant_NRM_SWR[7]), .C1(n4048), .Y(n4037)
);
INVX2TS U5062 ( .A(n4022), .Y(n4861) );
OAI22X1TS U5063 ( .A0(n4537), .A1(FPADDSUB_DmP_mant_SHT1_SW[4]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[19]), .B1(n4065), .Y(n4023) );
AOI22X1TS U5064 ( .A0(n4126), .A1(FPADDSUB_Data_array_SWR[5]), .B0(n2282),
.B1(n2232), .Y(n4030) );
INVX2TS U5065 ( .A(n4027), .Y(n4025) );
NAND2X1TS U5066 ( .A(n4024), .B(n3536), .Y(n4073) );
OAI22X1TS U5067 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(
FPADDSUB_DmP_mant_SHT1_SW[7]), .B0(FPADDSUB_Raw_mant_NRM_SWR[9]), .B1(
n4048), .Y(n4026) );
OAI22X1TS U5068 ( .A0(n4537), .A1(FPADDSUB_DmP_mant_SHT1_SW[6]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[17]), .B1(n4065), .Y(n4028) );
AOI22X1TS U5069 ( .A0(n2294), .A1(n4139), .B0(n2287), .B1(n4140), .Y(n4029)
);
OAI22X1TS U5070 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(
FPADDSUB_DmP_mant_SHT1_SW[17]), .B0(FPADDSUB_Raw_mant_NRM_SWR[19]),
.B1(n4048), .Y(n4031) );
AOI22X1TS U5071 ( .A0(n4126), .A1(FPADDSUB_Data_array_SWR[15]), .B0(n2282),
.B1(n4080), .Y(n4035) );
OAI22X1TS U5072 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(
FPADDSUB_DmP_mant_SHT1_SW[20]), .B0(FPADDSUB_Raw_mant_NRM_SWR[22]),
.B1(n4048), .Y(n4032) );
OAI22X1TS U5073 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(
FPADDSUB_DmP_mant_SHT1_SW[19]), .B0(FPADDSUB_Raw_mant_NRM_SWR[21]),
.B1(n4048), .Y(n4033) );
AOI22X1TS U5074 ( .A0(n2294), .A1(n4125), .B0(n2288), .B1(n4127), .Y(n4034)
);
AOI222X4TS U5075 ( .A0(n4539), .A1(FPADDSUB_DmP_mant_SHT1_SW[3]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[5]), .B1(n4006), .C0(
FPADDSUB_Raw_mant_NRM_SWR[20]), .C1(n3545), .Y(n4086) );
OAI22X1TS U5076 ( .A0(n4537), .A1(FPADDSUB_DmP_mant_SHT1_SW[2]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[21]), .B1(n4065), .Y(n4036) );
AOI22X1TS U5077 ( .A0(n4394), .A1(FPADDSUB_Data_array_SWR[4]), .B0(n2283),
.B1(n4113), .Y(n4039) );
INVX2TS U5078 ( .A(n4037), .Y(n4138) );
AOI22X1TS U5079 ( .A0(n2294), .A1(n4138), .B0(n2288), .B1(n2232), .Y(n4038)
);
OAI222X4TS U5080 ( .A0(n4048), .A1(FPADDSUB_Raw_mant_NRM_SWR[18]), .B0(n4065), .B1(FPADDSUB_Raw_mant_NRM_SWR[7]), .C0(FPADDSUB_DmP_mant_SHT1_SW[16]), .C1(
FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n4078) );
OAI22X1TS U5081 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(
FPADDSUB_DmP_mant_SHT1_SW[15]), .B0(FPADDSUB_Raw_mant_NRM_SWR[17]),
.B1(n4048), .Y(n4040) );
AOI22X1TS U5082 ( .A0(n4126), .A1(FPADDSUB_Data_array_SWR[13]), .B0(n2283),
.B1(n4091), .Y(n4043) );
INVX2TS U5083 ( .A(n4041), .Y(n4128) );
AOI22X1TS U5084 ( .A0(n2294), .A1(n4128), .B0(n2288), .B1(n4080), .Y(n4042)
);
AOI222X4TS U5085 ( .A0(n4539), .A1(FPADDSUB_DmP_mant_SHT1_SW[1]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[3]), .B1(n4006), .C0(
FPADDSUB_Raw_mant_NRM_SWR[22]), .C1(n3545), .Y(n4283) );
AOI22X1TS U5086 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[2]), .A1(n4006), .B0(
FPADDSUB_DmP_mant_SHT1_SW[0]), .B1(n5034), .Y(n4044) );
AOI22X1TS U5087 ( .A0(n4394), .A1(FPADDSUB_Data_array_SWR[2]), .B0(n2283),
.B1(n4282), .Y(n4046) );
INVX2TS U5088 ( .A(n4086), .Y(n4087) );
AOI22X1TS U5089 ( .A0(n2294), .A1(n4087), .B0(n2288), .B1(n4113), .Y(n4045)
);
AOI222X4TS U5090 ( .A0(n4539), .A1(FPADDSUB_DmP_mant_SHT1_SW[21]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[2]), .B1(n3545), .C0(
FPADDSUB_Raw_mant_NRM_SWR[23]), .C1(n4006), .Y(n4131) );
AOI22X1TS U5091 ( .A0(n3545), .A1(FPADDSUB_Raw_mant_NRM_SWR[1]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[22]), .B1(n4539), .Y(n4047) );
AOI22X1TS U5092 ( .A0(n4126), .A1(FPADDSUB_Data_array_SWR[18]), .B0(n2288),
.B1(n4094), .Y(n4050) );
OA22X1TS U5093 ( .A0(n4048), .A1(FPADDSUB_Raw_mant_NRM_SWR[25]), .B0(n4065),
.B1(FPADDSUB_Raw_mant_NRM_SWR[0]), .Y(n4069) );
AOI22X1TS U5094 ( .A0(n2294), .A1(n4069), .B0(n2282), .B1(n4125), .Y(n4049)
);
AOI21X1TS U5095 ( .A0(n4053), .A1(n4052), .B0(n4051), .Y(n4059) );
AOI21X1TS U5096 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[11]), .A1(n5065), .B0(n4057),
.Y(n4058) );
OAI222X4TS U5097 ( .A0(n4048), .A1(FPADDSUB_Raw_mant_NRM_SWR[16]), .B0(n4065), .B1(FPADDSUB_Raw_mant_NRM_SWR[9]), .C0(FPADDSUB_DmP_mant_SHT1_SW[14]), .C1(
FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n4083) );
AOI22X1TS U5098 ( .A0(n4126), .A1(n2369), .B0(n2287), .B1(n4091), .Y(n4061)
);
INVX2TS U5099 ( .A(n4078), .Y(n4079) );
AOI222X4TS U5100 ( .A0(n4539), .A1(n5338), .B0(n5207), .B1(n4006), .C0(n5174), .C1(n3545), .Y(n4099) );
AOI22X1TS U5101 ( .A0(n2293), .A1(n4079), .B0(n2282), .B1(n4099), .Y(n4060)
);
OAI222X4TS U5102 ( .A0(n3537), .A1(FPADDSUB_Raw_mant_NRM_SWR[14]), .B0(n4065), .B1(FPADDSUB_Raw_mant_NRM_SWR[11]), .C0(n4537), .C1(
FPADDSUB_DmP_mant_SHT1_SW[12]), .Y(n4137) );
AOI22X1TS U5103 ( .A0(n4126), .A1(FPADDSUB_Data_array_SWR[10]), .B0(n2287),
.B1(n4099), .Y(n4063) );
INVX2TS U5104 ( .A(n4083), .Y(n4090) );
AOI222X4TS U5105 ( .A0(n4539), .A1(n5339), .B0(n5186), .B1(n4006), .C0(n5167), .C1(n3545), .Y(n4132) );
AOI22X1TS U5106 ( .A0(n2293), .A1(n4090), .B0(n2282), .B1(n4132), .Y(n4062)
);
CMPR32X2TS U5107 ( .A(mult_x_309_n13), .B(FPMULT_Op_MX[22]), .C(
FPMULT_Op_MY[22]), .CO(n3387), .S(intadd_522_B_6_) );
NAND2X1TS U5108 ( .A(n2197), .B(n4930), .Y(n4064) );
AOI211X1TS U5109 ( .A0(n5253), .A1(n5156), .B0(n5162), .C0(n4064), .Y(
intadd_522_B_1_) );
OAI222X4TS U5110 ( .A0(n4065), .A1(FPADDSUB_Raw_mant_NRM_SWR[15]), .B0(n3537), .B1(FPADDSUB_Raw_mant_NRM_SWR[10]), .C0(n4537), .C1(
FPADDSUB_DmP_mant_SHT1_SW[8]), .Y(n4143) );
AOI22X1TS U5111 ( .A0(n4394), .A1(FPADDSUB_Data_array_SWR[8]), .B0(n2283),
.B1(n4139), .Y(n4067) );
AOI222X4TS U5112 ( .A0(n4539), .A1(n5340), .B0(n5186), .B1(n3545), .C0(n5167), .C1(n4006), .Y(n4133) );
AOI222X4TS U5113 ( .A0(n5034), .A1(n5341), .B0(n5189), .B1(n3545), .C0(n5166), .C1(n4006), .Y(n4134) );
AOI22X1TS U5114 ( .A0(n2294), .A1(n4133), .B0(n2288), .B1(n4134), .Y(n4066)
);
AOI22X1TS U5115 ( .A0(n4069), .A1(n4068), .B0(n2283), .B1(n4094), .Y(n4070)
);
OAI22X1TS U5116 ( .A0(n4862), .A1(n4073), .B0(n3536), .B1(n5342), .Y(n4074)
);
AOI21X1TS U5117 ( .A0(n4068), .A1(n4094), .B0(n4074), .Y(n4075) );
AOI22X1TS U5118 ( .A0(n4126), .A1(FPADDSUB_Data_array_SWR[14]), .B0(n2287),
.B1(n4128), .Y(n4077) );
AOI22X1TS U5119 ( .A0(n2293), .A1(n4127), .B0(n4068), .B1(n4080), .Y(n4076)
);
AOI22X1TS U5120 ( .A0(n4126), .A1(FPADDSUB_Data_array_SWR[12]), .B0(n2288),
.B1(n4079), .Y(n4082) );
AOI22X1TS U5121 ( .A0(n2294), .A1(n4080), .B0(n4068), .B1(n4091), .Y(n4081)
);
AOI22X1TS U5122 ( .A0(n4394), .A1(n2322), .B0(n2287), .B1(n4138), .Y(n4085)
);
AOI22X1TS U5123 ( .A0(n2293), .A1(n4140), .B0(n4068), .B1(n2232), .Y(n4084)
);
AOI22X1TS U5124 ( .A0(n4394), .A1(FPADDSUB_Data_array_SWR[3]), .B0(n2288),
.B1(n4087), .Y(n4089) );
AOI22X1TS U5125 ( .A0(n2294), .A1(n2232), .B0(n4068), .B1(n4113), .Y(n4088)
);
AOI22X1TS U5126 ( .A0(n4126), .A1(FPADDSUB_Data_array_SWR[11]), .B0(n2288),
.B1(n4090), .Y(n4093) );
AOI22X1TS U5127 ( .A0(n2294), .A1(n4091), .B0(n4068), .B1(n4099), .Y(n4092)
);
AOI22X1TS U5128 ( .A0(n4126), .A1(FPADDSUB_Data_array_SWR[17]), .B0(n2282),
.B1(n4127), .Y(n4096) );
AOI22X1TS U5129 ( .A0(n2294), .A1(n4094), .B0(n4125), .B1(n4068), .Y(n4095)
);
AOI22X1TS U5130 ( .A0(n4394), .A1(FPADDSUB_Data_array_SWR[9]), .B0(n2287),
.B1(n4133), .Y(n4098) );
AOI22X1TS U5131 ( .A0(n2294), .A1(n4132), .B0(n4068), .B1(n4134), .Y(n4097)
);
AOI22X1TS U5132 ( .A0(n4126), .A1(n2368), .B0(n2283), .B1(n4133), .Y(n4101)
);
AOI22X1TS U5133 ( .A0(n2294), .A1(n4099), .B0(n4068), .B1(n4132), .Y(n4100)
);
AOI22X1TS U5134 ( .A0(n4394), .A1(FPADDSUB_Data_array_SWR[7]), .B0(n2283),
.B1(n4140), .Y(n4103) );
AOI22X1TS U5135 ( .A0(n2294), .A1(n4134), .B0(n4068), .B1(n4139), .Y(n4102)
);
INVX2TS U5136 ( .A(begin_operation), .Y(n4716) );
NAND2X1TS U5137 ( .A(n4725), .B(n4726), .Y(n4714) );
AOI2BB2XLTS U5138 ( .B0(n2305), .B1(n5198), .A0N(n5198), .A1N(n2305), .Y(
n4107) );
BUFX3TS U5139 ( .A(n4304), .Y(n4874) );
BUFX4TS U5140 ( .A(n4105), .Y(n4303) );
AOI22X1TS U5141 ( .A0(operation[0]), .A1(n4874), .B0(FPADDSUB_intAS), .B1(
n4873), .Y(n4106) );
NOR2X2TS U5142 ( .A(n4958), .B(n4957), .Y(n4960) );
NOR2X2TS U5143 ( .A(n4963), .B(n4962), .Y(n4965) );
NOR2X2TS U5144 ( .A(n5259), .B(n4968), .Y(n4967) );
OAI211XLTS U5145 ( .A0(n2366), .A1(n4967), .B0(n4991), .C0(n4970), .Y(n4108)
);
NOR3X1TS U5146 ( .A(FPSENCOS_cont_iter_out[0]), .B(FPSENCOS_cont_iter_out[1]), .C(n4110), .Y(n4750) );
AOI211X1TS U5147 ( .A0(FPSENCOS_d_ff3_LUT_out[1]), .A1(n4784), .B0(n4750),
.C0(n4152), .Y(n4111) );
INVX2TS U5148 ( .A(n4111), .Y(n2132) );
AOI21X1TS U5149 ( .A0(n4784), .A1(FPSENCOS_d_ff3_LUT_out[3]), .B0(n4152),
.Y(n4112) );
AOI22X1TS U5150 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[24]), .A1(n3545), .B0(n4006),
.B1(FPADDSUB_Raw_mant_NRM_SWR[1]), .Y(n4281) );
AOI22X1TS U5151 ( .A0(n2294), .A1(n4113), .B0(n4068), .B1(n4282), .Y(n4114)
);
AOI21X1TS U5152 ( .A0(n4118), .A1(n4117), .B0(n4116), .Y(n4124) );
AOI21X1TS U5153 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[12]), .A1(n5065), .B0(n4122),
.Y(n4123) );
AOI22X1TS U5154 ( .A0(n4126), .A1(FPADDSUB_Data_array_SWR[16]), .B0(n4125),
.B1(n2288), .Y(n4130) );
AOI22X1TS U5155 ( .A0(n2282), .A1(n4128), .B0(n4068), .B1(n4127), .Y(n4129)
);
AOI22X1TS U5156 ( .A0(n4394), .A1(n2361), .B0(n2288), .B1(n4132), .Y(n4136)
);
AOI22X1TS U5157 ( .A0(n2282), .A1(n4134), .B0(n4068), .B1(n4133), .Y(n4135)
);
AOI22X1TS U5158 ( .A0(n4394), .A1(FPADDSUB_Data_array_SWR[6]), .B0(n2283),
.B1(n4138), .Y(n4142) );
AOI22X1TS U5159 ( .A0(n4068), .A1(n4140), .B0(n2288), .B1(n4139), .Y(n4141)
);
NOR3X1TS U5160 ( .A(n4145), .B(n5319), .C(FPSENCOS_cont_var_out[0]), .Y(
n4144) );
BUFX4TS U5161 ( .A(n4144), .Y(n4876) );
BUFX3TS U5162 ( .A(n4303), .Y(n4844) );
AOI22X1TS U5163 ( .A0(Data_2[10]), .A1(n4874), .B0(FPADDSUB_intDY_EWSW[10]),
.B1(n4844), .Y(n4147) );
NOR3X1TS U5164 ( .A(FPSENCOS_cont_var_out[1]), .B(n5198), .C(n4145), .Y(
n4154) );
BUFX3TS U5165 ( .A(n4154), .Y(n4826) );
AOI22X1TS U5166 ( .A0(FPSENCOS_d_ff3_LUT_out[10]), .A1(n4155), .B0(n4826),
.B1(FPSENCOS_d_ff3_sh_y_out[10]), .Y(n4146) );
NAND2X1TS U5167 ( .A(FPSENCOS_cont_iter_out[1]), .B(n2298), .Y(n4153) );
BUFX3TS U5168 ( .A(n4149), .Y(n4733) );
AOI22X1TS U5169 ( .A0(n4254), .A1(cordic_result[5]), .B0(n4888), .B1(
mult_result[5]), .Y(n4150) );
AOI22X1TS U5170 ( .A0(n4254), .A1(cordic_result[4]), .B0(n4888), .B1(
mult_result[4]), .Y(n4151) );
INVX2TS U5171 ( .A(n4152), .Y(n4749) );
AOI22X1TS U5172 ( .A0(Data_2[9]), .A1(n4841), .B0(FPADDSUB_intDY_EWSW[9]),
.B1(n4818), .Y(n4157) );
BUFX3TS U5173 ( .A(n4830), .Y(n4287) );
AOI22X1TS U5174 ( .A0(n4287), .A1(FPSENCOS_d_ff3_sh_y_out[9]), .B0(n4155),
.B1(FPSENCOS_d_ff3_LUT_out[9]), .Y(n4156) );
INVX2TS U5175 ( .A(FPSENCOS_d_ff3_sh_x_out[23]), .Y(n4785) );
AOI22X1TS U5176 ( .A0(Data_2[23]), .A1(n4874), .B0(FPADDSUB_intDY_EWSW[23]),
.B1(n4844), .Y(n4159) );
AOI22X1TS U5177 ( .A0(n4287), .A1(FPSENCOS_d_ff3_sh_y_out[23]), .B0(n4155),
.B1(FPSENCOS_d_ff3_LUT_out[23]), .Y(n4158) );
AOI22X1TS U5178 ( .A0(Data_2[6]), .A1(n4815), .B0(FPADDSUB_intDY_EWSW[6]),
.B1(n4818), .Y(n4161) );
AOI22X1TS U5179 ( .A0(n4287), .A1(FPSENCOS_d_ff3_sh_y_out[6]), .B0(n4155),
.B1(FPSENCOS_d_ff3_LUT_out[6]), .Y(n4160) );
BUFX3TS U5180 ( .A(n4844), .Y(n4228) );
AOI22X1TS U5181 ( .A0(Data_1[24]), .A1(n4299), .B0(FPADDSUB_intDX_EWSW[24]),
.B1(n4228), .Y(n4163) );
BUFX3TS U5182 ( .A(n4830), .Y(n4307) );
AOI22X1TS U5183 ( .A0(n4307), .A1(FPSENCOS_d_ff2_X[24]), .B0(n4199), .B1(
FPSENCOS_d_ff2_Z[24]), .Y(n4162) );
AOI22X1TS U5184 ( .A0(Data_2[0]), .A1(n4299), .B0(FPADDSUB_intDY_EWSW[0]),
.B1(n4844), .Y(n4165) );
AOI22X1TS U5185 ( .A0(n4287), .A1(FPSENCOS_d_ff3_sh_y_out[0]), .B0(n4199),
.B1(FPSENCOS_d_ff3_LUT_out[0]), .Y(n4164) );
AOI22X1TS U5186 ( .A0(Data_2[4]), .A1(n4299), .B0(FPADDSUB_intDY_EWSW[4]),
.B1(n4844), .Y(n4167) );
AOI22X1TS U5187 ( .A0(n4287), .A1(FPSENCOS_d_ff3_sh_y_out[4]), .B0(n4155),
.B1(FPSENCOS_d_ff3_LUT_out[4]), .Y(n4166) );
AOI22X1TS U5188 ( .A0(Data_1[31]), .A1(n4299), .B0(FPADDSUB_intDX_EWSW[31]),
.B1(n4844), .Y(n4169) );
AOI22X1TS U5189 ( .A0(n4307), .A1(n2335), .B0(n4199), .B1(
FPSENCOS_d_ff2_Z[31]), .Y(n4168) );
AOI22X1TS U5190 ( .A0(Data_1[27]), .A1(n4815), .B0(FPADDSUB_intDX_EWSW[27]),
.B1(n4228), .Y(n4171) );
AOI22X1TS U5191 ( .A0(n4307), .A1(FPSENCOS_d_ff2_X[27]), .B0(n4199), .B1(
FPSENCOS_d_ff2_Z[27]), .Y(n4170) );
AOI22X1TS U5192 ( .A0(Data_1[25]), .A1(n4815), .B0(FPADDSUB_intDX_EWSW[25]),
.B1(n4228), .Y(n4173) );
AOI22X1TS U5193 ( .A0(n4307), .A1(FPSENCOS_d_ff2_X[25]), .B0(n4199), .B1(
FPSENCOS_d_ff2_Z[25]), .Y(n4172) );
AOI22X1TS U5194 ( .A0(Data_1[30]), .A1(n4815), .B0(FPADDSUB_intDX_EWSW[30]),
.B1(n4873), .Y(n4175) );
AOI22X1TS U5195 ( .A0(n4307), .A1(FPSENCOS_d_ff2_X[30]), .B0(n4199), .B1(
FPSENCOS_d_ff2_Z[30]), .Y(n4174) );
AOI22X1TS U5196 ( .A0(Data_2[24]), .A1(n4874), .B0(FPADDSUB_intDY_EWSW[24]),
.B1(n4818), .Y(n4177) );
AOI22X1TS U5197 ( .A0(n4287), .A1(FPSENCOS_d_ff3_sh_y_out[24]), .B0(n4155),
.B1(FPSENCOS_d_ff3_LUT_out[24]), .Y(n4176) );
AOI22X1TS U5198 ( .A0(Data_1[29]), .A1(n4815), .B0(FPADDSUB_intDX_EWSW[29]),
.B1(n4818), .Y(n4179) );
AOI22X1TS U5199 ( .A0(n4307), .A1(FPSENCOS_d_ff2_X[29]), .B0(n4199), .B1(
FPSENCOS_d_ff2_Z[29]), .Y(n4178) );
AOI22X1TS U5200 ( .A0(Data_1[22]), .A1(n4299), .B0(FPADDSUB_intDX_EWSW[22]),
.B1(n4228), .Y(n4181) );
AOI22X1TS U5201 ( .A0(n4307), .A1(FPSENCOS_d_ff2_X[22]), .B0(n4199), .B1(
FPSENCOS_d_ff2_Z[22]), .Y(n4180) );
AOI22X1TS U5202 ( .A0(Data_1[12]), .A1(n4841), .B0(FPADDSUB_intDX_EWSW[12]),
.B1(n4303), .Y(n4183) );
BUFX3TS U5203 ( .A(n4830), .Y(n4300) );
AOI22X1TS U5204 ( .A0(n4300), .A1(n2332), .B0(n4199), .B1(
FPSENCOS_d_ff2_Z[12]), .Y(n4182) );
AOI22X1TS U5205 ( .A0(Data_1[21]), .A1(n4299), .B0(FPADDSUB_intDX_EWSW[21]),
.B1(n4228), .Y(n4185) );
AOI22X1TS U5206 ( .A0(n4307), .A1(n2328), .B0(n4199), .B1(
FPSENCOS_d_ff2_Z[21]), .Y(n4184) );
AOI22X1TS U5207 ( .A0(Data_1[26]), .A1(n4815), .B0(FPADDSUB_intDX_EWSW[26]),
.B1(n4228), .Y(n4187) );
AOI22X1TS U5208 ( .A0(n4307), .A1(FPSENCOS_d_ff2_X[26]), .B0(n4199), .B1(
FPSENCOS_d_ff2_Z[26]), .Y(n4186) );
AOI22X1TS U5209 ( .A0(Data_2[12]), .A1(n4304), .B0(FPADDSUB_intDY_EWSW[12]),
.B1(n4818), .Y(n4189) );
AOI22X1TS U5210 ( .A0(n4287), .A1(FPSENCOS_d_ff3_sh_y_out[12]), .B0(n4199),
.B1(FPSENCOS_d_ff3_LUT_out[12]), .Y(n4188) );
AOI22X1TS U5211 ( .A0(Data_2[25]), .A1(n4874), .B0(FPADDSUB_intDY_EWSW[25]),
.B1(n4844), .Y(n4191) );
AOI22X1TS U5212 ( .A0(n4287), .A1(FPSENCOS_d_ff3_sh_y_out[25]), .B0(n4155),
.B1(FPSENCOS_d_ff3_LUT_out[25]), .Y(n4190) );
AOI22X1TS U5213 ( .A0(Data_2[8]), .A1(n4874), .B0(FPADDSUB_intDY_EWSW[8]),
.B1(n4844), .Y(n4193) );
AOI22X1TS U5214 ( .A0(n4287), .A1(FPSENCOS_d_ff3_sh_y_out[8]), .B0(n4199),
.B1(FPSENCOS_d_ff3_LUT_out[8]), .Y(n4192) );
AOI22X1TS U5215 ( .A0(Data_2[26]), .A1(n4874), .B0(FPADDSUB_intDY_EWSW[26]),
.B1(n4844), .Y(n4195) );
AOI22X1TS U5216 ( .A0(n4287), .A1(FPSENCOS_d_ff3_sh_y_out[26]), .B0(n4155),
.B1(FPSENCOS_d_ff3_LUT_out[26]), .Y(n4194) );
AOI22X1TS U5217 ( .A0(Data_1[28]), .A1(n4815), .B0(FPADDSUB_intDX_EWSW[28]),
.B1(n4228), .Y(n4197) );
AOI22X1TS U5218 ( .A0(n4307), .A1(FPSENCOS_d_ff2_X[28]), .B0(n4199), .B1(
FPSENCOS_d_ff2_Z[28]), .Y(n4196) );
AOI22X1TS U5219 ( .A0(Data_1[23]), .A1(n4299), .B0(FPADDSUB_intDX_EWSW[23]),
.B1(n4228), .Y(n4201) );
AOI22X1TS U5220 ( .A0(n4307), .A1(FPSENCOS_d_ff2_X[23]), .B0(n4199), .B1(
FPSENCOS_d_ff2_Z[23]), .Y(n4200) );
AOI21X1TS U5221 ( .A0(n4205), .A1(n4204), .B0(n4203), .Y(n4211) );
AOI21X1TS U5222 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[13]), .A1(n5091), .B0(n4209),
.Y(n4210) );
AOI22X1TS U5223 ( .A0(Data_1[9]), .A1(n4815), .B0(FPADDSUB_intDX_EWSW[9]),
.B1(n4303), .Y(n4213) );
AOI22X1TS U5224 ( .A0(n4300), .A1(n2324), .B0(n4242), .B1(
FPSENCOS_d_ff2_Z[9]), .Y(n4212) );
AOI22X1TS U5225 ( .A0(Data_1[15]), .A1(n4299), .B0(FPADDSUB_intDX_EWSW[15]),
.B1(n4303), .Y(n4215) );
AOI22X1TS U5226 ( .A0(n4300), .A1(FPSENCOS_d_ff2_X[15]), .B0(n4242), .B1(
FPSENCOS_d_ff2_Z[15]), .Y(n4214) );
AOI22X1TS U5227 ( .A0(Data_1[18]), .A1(n4299), .B0(FPADDSUB_intDX_EWSW[18]),
.B1(n4228), .Y(n4217) );
AOI22X1TS U5228 ( .A0(n4300), .A1(FPSENCOS_d_ff2_X[18]), .B0(n4242), .B1(
FPSENCOS_d_ff2_Z[18]), .Y(n4216) );
AOI22X1TS U5229 ( .A0(Data_1[11]), .A1(n4304), .B0(FPADDSUB_intDX_EWSW[11]),
.B1(n4303), .Y(n4219) );
AOI22X1TS U5230 ( .A0(n4300), .A1(n2336), .B0(n4242), .B1(
FPSENCOS_d_ff2_Z[11]), .Y(n4218) );
AOI22X1TS U5231 ( .A0(Data_1[20]), .A1(n4299), .B0(FPADDSUB_intDX_EWSW[20]),
.B1(n4228), .Y(n4221) );
AOI22X1TS U5232 ( .A0(n4307), .A1(n2340), .B0(n4242), .B1(
FPSENCOS_d_ff2_Z[20]), .Y(n4220) );
AOI22X1TS U5233 ( .A0(Data_1[17]), .A1(n4299), .B0(FPADDSUB_intDX_EWSW[17]),
.B1(n4228), .Y(n4223) );
AOI22X1TS U5234 ( .A0(n4300), .A1(n2339), .B0(n4242), .B1(
FPSENCOS_d_ff2_Z[17]), .Y(n4222) );
AOI22X1TS U5235 ( .A0(Data_1[14]), .A1(n4815), .B0(FPADDSUB_intDX_EWSW[14]),
.B1(n4303), .Y(n4225) );
AOI22X1TS U5236 ( .A0(n4300), .A1(n2344), .B0(n4242), .B1(
FPSENCOS_d_ff2_Z[14]), .Y(n4224) );
AOI22X1TS U5237 ( .A0(Data_1[13]), .A1(n4299), .B0(FPADDSUB_intDX_EWSW[13]),
.B1(n4303), .Y(n4227) );
AOI22X1TS U5238 ( .A0(n4300), .A1(n2338), .B0(n4242), .B1(
FPSENCOS_d_ff2_Z[13]), .Y(n4226) );
AOI22X1TS U5239 ( .A0(Data_1[19]), .A1(n4815), .B0(FPADDSUB_intDX_EWSW[19]),
.B1(n4228), .Y(n4230) );
AOI22X1TS U5240 ( .A0(n4300), .A1(n2341), .B0(n4242), .B1(
FPSENCOS_d_ff2_Z[19]), .Y(n4229) );
AOI22X1TS U5241 ( .A0(Data_2[21]), .A1(n4874), .B0(FPADDSUB_intDY_EWSW[21]),
.B1(n4873), .Y(n4232) );
AOI22X1TS U5242 ( .A0(n4287), .A1(FPSENCOS_d_ff3_sh_y_out[21]), .B0(n4242),
.B1(FPSENCOS_d_ff3_LUT_out[21]), .Y(n4231) );
AOI22X1TS U5243 ( .A0(Data_2[1]), .A1(n4815), .B0(FPADDSUB_intDY_EWSW[1]),
.B1(n4873), .Y(n4234) );
AOI22X1TS U5244 ( .A0(n4287), .A1(FPSENCOS_d_ff3_sh_y_out[1]), .B0(n4242),
.B1(FPSENCOS_d_ff3_LUT_out[1]), .Y(n4233) );
AOI22X1TS U5245 ( .A0(Data_1[10]), .A1(n4304), .B0(FPADDSUB_intDX_EWSW[10]),
.B1(n4303), .Y(n4236) );
AOI22X1TS U5246 ( .A0(n4300), .A1(n2333), .B0(n4242), .B1(
FPSENCOS_d_ff2_Z[10]), .Y(n4235) );
AOI22X1TS U5247 ( .A0(Data_1[16]), .A1(n4299), .B0(FPADDSUB_intDX_EWSW[16]),
.B1(n4303), .Y(n4238) );
AOI22X1TS U5248 ( .A0(n4300), .A1(FPSENCOS_d_ff2_X[16]), .B0(n4242), .B1(
FPSENCOS_d_ff2_Z[16]), .Y(n4237) );
AOI22X1TS U5249 ( .A0(Data_1[7]), .A1(n4815), .B0(FPADDSUB_intDX_EWSW[7]),
.B1(n4303), .Y(n4241) );
AOI22X1TS U5250 ( .A0(n4826), .A1(n2337), .B0(n4242), .B1(
FPSENCOS_d_ff2_Z[7]), .Y(n4240) );
AOI22X1TS U5251 ( .A0(Data_1[5]), .A1(n4874), .B0(FPADDSUB_intDX_EWSW[5]),
.B1(n4303), .Y(n4244) );
AOI22X1TS U5252 ( .A0(n4826), .A1(n2342), .B0(n4242), .B1(
FPSENCOS_d_ff2_Z[5]), .Y(n4243) );
AOI22X1TS U5253 ( .A0(cordic_result[31]), .A1(n4273), .B0(n4272), .B1(
mult_result[31]), .Y(n4245) );
AOI22X1TS U5254 ( .A0(n4273), .A1(cordic_result[23]), .B0(n4272), .B1(
mult_result[23]), .Y(n4246) );
OAI21XLTS U5255 ( .A0(n4275), .A1(n5208), .B0(n4246), .Y(op_result[23]) );
AOI22X1TS U5256 ( .A0(n4273), .A1(cordic_result[25]), .B0(n4272), .B1(
mult_result[25]), .Y(n4247) );
OAI21XLTS U5257 ( .A0(n4275), .A1(n5210), .B0(n4247), .Y(op_result[25]) );
AOI22X1TS U5258 ( .A0(n4273), .A1(cordic_result[24]), .B0(n4272), .B1(
mult_result[24]), .Y(n4248) );
OAI21XLTS U5259 ( .A0(n4275), .A1(n5209), .B0(n4248), .Y(op_result[24]) );
AOI22X1TS U5260 ( .A0(n4273), .A1(cordic_result[26]), .B0(n4272), .B1(
mult_result[26]), .Y(n4249) );
OAI21XLTS U5261 ( .A0(n4275), .A1(n5211), .B0(n4249), .Y(op_result[26]) );
AOI22X1TS U5262 ( .A0(n4273), .A1(cordic_result[28]), .B0(n4272), .B1(
mult_result[28]), .Y(n4250) );
OAI21XLTS U5263 ( .A0(n4275), .A1(n5213), .B0(n4250), .Y(op_result[28]) );
AOI22X1TS U5264 ( .A0(n4273), .A1(cordic_result[27]), .B0(n4272), .B1(
mult_result[27]), .Y(n4251) );
OAI21XLTS U5265 ( .A0(n4275), .A1(n5212), .B0(n4251), .Y(op_result[27]) );
AOI22X1TS U5266 ( .A0(n4273), .A1(cordic_result[22]), .B0(n4272), .B1(
mult_result[22]), .Y(n4252) );
OAI21XLTS U5267 ( .A0(n4275), .A1(n5300), .B0(n4252), .Y(op_result[22]) );
AOI22X1TS U5268 ( .A0(n4273), .A1(cordic_result[29]), .B0(n4272), .B1(
mult_result[29]), .Y(n4253) );
OAI21XLTS U5269 ( .A0(n4275), .A1(n5228), .B0(n4253), .Y(op_result[29]) );
AOI22X1TS U5270 ( .A0(n4279), .A1(cordic_result[9]), .B0(n4278), .B1(
mult_result[9]), .Y(n4255) );
AOI22X1TS U5271 ( .A0(n4273), .A1(cordic_result[21]), .B0(n4272), .B1(
mult_result[21]), .Y(n4256) );
OAI21XLTS U5272 ( .A0(n4275), .A1(n5199), .B0(n4256), .Y(op_result[21]) );
AOI22X1TS U5273 ( .A0(n4273), .A1(cordic_result[20]), .B0(n4272), .B1(
mult_result[20]), .Y(n4257) );
OAI21XLTS U5274 ( .A0(n4275), .A1(n5304), .B0(n4257), .Y(op_result[20]) );
AOI22X1TS U5275 ( .A0(n4273), .A1(cordic_result[19]), .B0(n4272), .B1(
mult_result[19]), .Y(n4258) );
OAI21XLTS U5276 ( .A0(n4149), .A1(n5303), .B0(n4258), .Y(op_result[19]) );
AOI22X1TS U5277 ( .A0(n4279), .A1(cordic_result[18]), .B0(n4278), .B1(
mult_result[18]), .Y(n4259) );
OAI21XLTS U5278 ( .A0(n4149), .A1(n5302), .B0(n4259), .Y(op_result[18]) );
AOI22X1TS U5279 ( .A0(n4279), .A1(cordic_result[17]), .B0(n4278), .B1(
mult_result[17]), .Y(n4260) );
OAI21XLTS U5280 ( .A0(n4149), .A1(n5305), .B0(n4260), .Y(op_result[17]) );
AOI22X1TS U5281 ( .A0(n4279), .A1(cordic_result[16]), .B0(n4278), .B1(
mult_result[16]), .Y(n4261) );
AOI22X1TS U5282 ( .A0(n4279), .A1(cordic_result[15]), .B0(n4278), .B1(
mult_result[15]), .Y(n4262) );
OAI21XLTS U5283 ( .A0(n4149), .A1(n5301), .B0(n4262), .Y(op_result[15]) );
AOI22X1TS U5284 ( .A0(n4279), .A1(cordic_result[14]), .B0(n4278), .B1(
mult_result[14]), .Y(n4263) );
OAI21XLTS U5285 ( .A0(n4149), .A1(n5308), .B0(n4263), .Y(op_result[14]) );
AOI22X1TS U5286 ( .A0(n4279), .A1(cordic_result[6]), .B0(n4278), .B1(
mult_result[6]), .Y(n4264) );
OAI21XLTS U5287 ( .A0(n4149), .A1(n5306), .B0(n4264), .Y(op_result[6]) );
AOI22X1TS U5288 ( .A0(n4279), .A1(cordic_result[13]), .B0(n4278), .B1(
mult_result[13]), .Y(n4265) );
OAI21XLTS U5289 ( .A0(n4149), .A1(n5294), .B0(n4265), .Y(op_result[13]) );
AOI22X1TS U5290 ( .A0(n4279), .A1(cordic_result[12]), .B0(n4278), .B1(
mult_result[12]), .Y(n4266) );
OAI21XLTS U5291 ( .A0(n4275), .A1(n5298), .B0(n4266), .Y(op_result[12]) );
AOI22X1TS U5292 ( .A0(n4279), .A1(cordic_result[7]), .B0(n4278), .B1(
mult_result[7]), .Y(n4267) );
AOI22X1TS U5293 ( .A0(n4273), .A1(cordic_result[1]), .B0(n4272), .B1(
mult_result[1]), .Y(n4268) );
AOI22X1TS U5294 ( .A0(n4273), .A1(cordic_result[3]), .B0(n4272), .B1(
mult_result[3]), .Y(n4269) );
AOI22X1TS U5295 ( .A0(n4279), .A1(cordic_result[11]), .B0(n4278), .B1(
mult_result[11]), .Y(n4270) );
AOI22X1TS U5296 ( .A0(n4279), .A1(cordic_result[10]), .B0(n4278), .B1(
mult_result[10]), .Y(n4271) );
AOI22X1TS U5297 ( .A0(n4273), .A1(cordic_result[30]), .B0(n4272), .B1(
mult_result[30]), .Y(n4274) );
OAI21XLTS U5298 ( .A0(n4275), .A1(n5214), .B0(n4274), .Y(op_result[30]) );
AOI22X1TS U5299 ( .A0(n4279), .A1(cordic_result[8]), .B0(n4278), .B1(
mult_result[8]), .Y(n4276) );
AOI22X1TS U5300 ( .A0(n4279), .A1(cordic_result[0]), .B0(n4278), .B1(
mult_result[0]), .Y(n4277) );
AOI22X1TS U5301 ( .A0(n4279), .A1(cordic_result[2]), .B0(n4278), .B1(
mult_result[2]), .Y(n4280) );
INVX2TS U5302 ( .A(n4281), .Y(n4285) );
OAI31X1TS U5303 ( .A0(n2218), .A1(n4539), .A2(n4071), .B0(n4286), .Y(n1787)
);
AOI22X1TS U5304 ( .A0(Data_2[2]), .A1(n4299), .B0(FPADDSUB_intDY_EWSW[2]),
.B1(n4844), .Y(n4289) );
BUFX4TS U5305 ( .A(n4155), .Y(n4851) );
AOI22X1TS U5306 ( .A0(n4287), .A1(FPSENCOS_d_ff3_sh_y_out[2]), .B0(n4851),
.B1(FPSENCOS_d_ff3_LUT_out[2]), .Y(n4288) );
AOI22X1TS U5307 ( .A0(Data_1[8]), .A1(n4304), .B0(FPADDSUB_intDX_EWSW[8]),
.B1(n4303), .Y(n4292) );
AOI22X1TS U5308 ( .A0(n4300), .A1(n2326), .B0(n4851), .B1(
FPSENCOS_d_ff2_Z[8]), .Y(n4291) );
AOI22X1TS U5309 ( .A0(Data_1[2]), .A1(n4841), .B0(FPADDSUB_intDX_EWSW[2]),
.B1(n4873), .Y(n4294) );
AOI22X1TS U5310 ( .A0(n4826), .A1(n2331), .B0(n4851), .B1(
FPSENCOS_d_ff2_Z[2]), .Y(n4293) );
AOI22X1TS U5311 ( .A0(Data_1[1]), .A1(n4874), .B0(FPADDSUB_intDX_EWSW[1]),
.B1(n4844), .Y(n4296) );
AOI22X1TS U5312 ( .A0(n4826), .A1(n2330), .B0(n4851), .B1(
FPSENCOS_d_ff2_Z[1]), .Y(n4295) );
AOI22X1TS U5313 ( .A0(Data_1[3]), .A1(n4815), .B0(FPADDSUB_intDX_EWSW[3]),
.B1(n4818), .Y(n4298) );
AOI22X1TS U5314 ( .A0(n4826), .A1(n2343), .B0(n4851), .B1(
FPSENCOS_d_ff2_Z[3]), .Y(n4297) );
AOI22X1TS U5315 ( .A0(Data_1[4]), .A1(n4299), .B0(FPADDSUB_intDX_EWSW[4]),
.B1(n4844), .Y(n4302) );
AOI22X1TS U5316 ( .A0(n4300), .A1(n2327), .B0(n4851), .B1(
FPSENCOS_d_ff2_Z[4]), .Y(n4301) );
AOI22X1TS U5317 ( .A0(Data_1[6]), .A1(n4304), .B0(FPADDSUB_intDX_EWSW[6]),
.B1(n4303), .Y(n4306) );
AOI22X1TS U5318 ( .A0(n4826), .A1(n2334), .B0(n4851), .B1(
FPSENCOS_d_ff2_Z[6]), .Y(n4305) );
AOI22X1TS U5319 ( .A0(n4841), .A1(Data_1[0]), .B0(FPADDSUB_intDX_EWSW[0]),
.B1(n4873), .Y(n4309) );
AOI22X1TS U5320 ( .A0(n4307), .A1(n2325), .B0(FPSENCOS_d_ff2_Z[0]), .B1(
n4851), .Y(n4308) );
OAI32X1TS U5321 ( .A0(n4311), .A1(n4687), .A2(n5163), .B0(FPMULT_Op_MX[14]),
.B1(n4312), .Y(n4686) );
NAND2X1TS U5322 ( .A(FPMULT_Op_MX[13]), .B(n2198), .Y(n4315) );
NAND2X1TS U5323 ( .A(FPMULT_Op_MX[12]), .B(FPMULT_Op_MY[14]), .Y(n4316) );
XOR2X1TS U5324 ( .A(n4315), .B(n4316), .Y(n4685) );
NAND2X1TS U5325 ( .A(n4686), .B(n4685), .Y(n4684) );
OAI32X1TS U5326 ( .A0(mult_x_312_n42), .A1(n4365), .A2(n4687), .B0(n4313),
.B1(mult_x_312_n42), .Y(intadd_519_B_0_) );
OAI21XLTS U5327 ( .A0(n4316), .A1(n4315), .B0(n4314), .Y(intadd_519_B_1_) );
OAI21XLTS U5328 ( .A0(n4320), .A1(n4318), .B0(n4317), .Y(n4323) );
AOI21X1TS U5329 ( .A0(n3190), .A1(n4323), .B0(n4322), .Y(n4324) );
NOR2X2TS U5330 ( .A(n4971), .B(n4970), .Y(n4973) );
NOR2X2TS U5331 ( .A(n5290), .B(n4976), .Y(n4975) );
OAI211XLTS U5332 ( .A0(n2367), .A1(n4975), .B0(n4991), .C0(n4979), .Y(n4325)
);
OAI21XLTS U5333 ( .A0(n4329), .A1(n4327), .B0(n4326), .Y(n4332) );
AOI21X1TS U5334 ( .A0(n3190), .A1(n4332), .B0(n4331), .Y(n4333) );
NOR2X2TS U5335 ( .A(n5335), .B(n4979), .Y(n4978) );
AOI211X1TS U5336 ( .A0(n4337), .A1(n4336), .B0(n4335), .C0(n3582), .Y(n4342)
);
AOI211X1TS U5337 ( .A0(n4340), .A1(n4339), .B0(n4338), .C0(n2289), .Y(n4341)
);
AOI211X1TS U5338 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[17]), .A1(n5091), .B0(n4342), .C0(n4341), .Y(n4343) );
INVX2TS U5339 ( .A(n4343), .Y(n1332) );
AOI21X1TS U5340 ( .A0(n4346), .A1(n4345), .B0(n4344), .Y(n4352) );
AOI211X1TS U5341 ( .A0(n4349), .A1(n4348), .B0(n4347), .C0(n5078), .Y(n4350)
);
AOI21X1TS U5342 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[19]), .A1(n5065), .B0(n4350),
.Y(n4351) );
NAND2X1TS U5343 ( .A(n4987), .B(FPMULT_Sgf_normalized_result[22]), .Y(n4354)
);
NOR2X2TS U5344 ( .A(n4982), .B(n4981), .Y(n4985) );
OAI22X1TS U5345 ( .A0(n4354), .A1(n4986), .B0(n4991), .B1(
FPMULT_Add_result[22]), .Y(n4353) );
AOI2BB2X2TS U5346 ( .B0(FPADDSUB_DMP_SFG[21]), .B1(n5330), .A0N(n5330),
.A1N(FPADDSUB_DMP_SFG[21]), .Y(n4359) );
NOR2X1TS U5347 ( .A(FPADDSUB_DmP_mant_SFG_SWR[22]), .B(n5288), .Y(n4356) );
OAI21X2TS U5348 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[21]), .A1(n5287), .B0(n4355),
.Y(n5083) );
AOI211X1TS U5349 ( .A0(n4360), .A1(n4359), .B0(n5006), .C0(n3188), .Y(n4361)
);
AOI21X1TS U5350 ( .A0(n3190), .A1(n4362), .B0(n4361), .Y(n4363) );
NAND2X1TS U5351 ( .A(FPMULT_Op_MX[16]), .B(FPMULT_Op_MY[12]), .Y(n4364) );
OAI32X1TS U5352 ( .A0(mult_x_312_n38), .A1(n4365), .A2(n5157), .B0(n4364),
.B1(mult_x_312_n38), .Y(mult_x_312_n39) );
OAI31X1TS U5353 ( .A0(n5254), .A1(n5160), .A2(n4695), .B0(n4366), .Y(
mult_x_312_n24) );
NAND2X1TS U5354 ( .A(DP_OP_501J224_127_5235_n411), .B(FPMULT_Op_MY[19]), .Y(
n4367) );
OAI32X1TS U5355 ( .A0(mult_x_309_n38), .A1(n5248), .A2(n5188), .B0(n4367),
.B1(mult_x_309_n38), .Y(mult_x_309_n39) );
NOR2XLTS U5356 ( .A(FPADDSUB_Raw_mant_NRM_SWR[9]), .B(
FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n4371) );
NOR2XLTS U5357 ( .A(FPADDSUB_Raw_mant_NRM_SWR[4]), .B(
FPADDSUB_Raw_mant_NRM_SWR[5]), .Y(n4369) );
NAND4XLTS U5358 ( .A(n4371), .B(n4370), .C(n4369), .D(n4368), .Y(n4378) );
AOI32X1TS U5359 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[3]), .A1(n3536), .A2(
n5034), .B0(FPADDSUB_shift_value_SHT2_EWR[3]), .B1(n4394), .Y(n4375)
);
OAI21XLTS U5360 ( .A0(FPADDSUB_ADD_OVRFLW_NRM), .A1(n4534), .B0(n4375), .Y(
n2076) );
OAI31X1TS U5361 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[1]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[0]), .A2(n4378), .B0(n4377), .Y(n4533) );
AOI32X1TS U5362 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[4]), .A1(n3536), .A2(
n5034), .B0(FPADDSUB_shift_value_SHT2_EWR[4]), .B1(n4394), .Y(n4379)
);
OAI21XLTS U5363 ( .A0(FPADDSUB_ADD_OVRFLW_NRM), .A1(n4533), .B0(n4379), .Y(
n2075) );
NAND2X1TS U5364 ( .A(n5291), .B(n5175), .Y(n4890) );
OAI222X1TS U5365 ( .A0(n5195), .A1(n4890), .B0(n4383), .B1(n4382), .C0(n4381), .C1(n4380), .Y(n1691) );
INVX2TS U5366 ( .A(n4384), .Y(n4388) );
AOI22X1TS U5367 ( .A0(n4388), .A1(n4387), .B0(n4386), .B1(n4385), .Y(n4389)
);
NAND2X1TS U5368 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .B(n4393), .Y(n4535) );
AOI32X1TS U5369 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[2]), .A1(n3536), .A2(
n5034), .B0(FPADDSUB_shift_value_SHT2_EWR[2]), .B1(n4394), .Y(n4395)
);
NAND2X1TS U5370 ( .A(n4924), .B(FPMULT_Op_MX[6]), .Y(n4449) );
OAI21XLTS U5371 ( .A0(n5262), .A1(n2381), .B0(n4449), .Y(n4396) );
CLKAND2X2TS U5372 ( .A(n4397), .B(n4396), .Y(n5349) );
NAND2X1TS U5373 ( .A(n4921), .B(FPMULT_Op_MX[0]), .Y(n4499) );
OAI21XLTS U5374 ( .A0(n5261), .A1(n2399), .B0(n4499), .Y(n4398) );
CLKAND2X2TS U5375 ( .A(n4399), .B(n4398), .Y(n5350) );
NOR3BX1TS U5376 ( .AN(n2345), .B(FPMULT_FSM_selector_B[1]), .C(
FPMULT_FSM_selector_B[0]), .Y(n4400) );
XOR2X1TS U5377 ( .A(n5437), .B(n4400), .Y(DP_OP_234J224_132_4955_n15) );
OR2X2TS U5378 ( .A(FPMULT_FSM_selector_B[1]), .B(n5275), .Y(n4407) );
OAI2BB1X1TS U5379 ( .A0N(FPMULT_Op_MY[29]), .A1N(n5279), .B0(n4407), .Y(
n4401) );
XOR2X1TS U5380 ( .A(n5437), .B(n4401), .Y(DP_OP_234J224_132_4955_n16) );
OAI2BB1X1TS U5381 ( .A0N(n2304), .A1N(n5279), .B0(n4407), .Y(n4402) );
XOR2X1TS U5382 ( .A(n5437), .B(n4402), .Y(DP_OP_234J224_132_4955_n17) );
OAI2BB1X1TS U5383 ( .A0N(FPMULT_Op_MY[27]), .A1N(n5279), .B0(n4407), .Y(
n4403) );
XOR2X1TS U5384 ( .A(n5437), .B(n4403), .Y(DP_OP_234J224_132_4955_n18) );
OAI2BB1X1TS U5385 ( .A0N(n2319), .A1N(n5279), .B0(n4407), .Y(n4404) );
XOR2X1TS U5386 ( .A(n5437), .B(n4404), .Y(DP_OP_234J224_132_4955_n19) );
OAI2BB1X1TS U5387 ( .A0N(n2320), .A1N(n5279), .B0(n4407), .Y(n4405) );
XOR2X1TS U5388 ( .A(n5437), .B(n4405), .Y(DP_OP_234J224_132_4955_n20) );
OAI2BB1X1TS U5389 ( .A0N(n2316), .A1N(n5279), .B0(n4407), .Y(n4406) );
XOR2X1TS U5390 ( .A(n5437), .B(n4406), .Y(DP_OP_234J224_132_4955_n21) );
XOR2X1TS U5391 ( .A(n5437), .B(n4409), .Y(DP_OP_234J224_132_4955_n22) );
NOR2BX1TS U5392 ( .AN(FPADDSUB_LZD_output_NRM2_EW[4]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4410) );
XOR2X1TS U5393 ( .A(n2195), .B(n4410), .Y(DP_OP_26J224_129_1325_n14) );
NOR2BX1TS U5394 ( .AN(FPADDSUB_LZD_output_NRM2_EW[3]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4411) );
XOR2X1TS U5395 ( .A(n2195), .B(n4411), .Y(DP_OP_26J224_129_1325_n15) );
NOR2BX1TS U5396 ( .AN(FPADDSUB_LZD_output_NRM2_EW[2]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4412) );
XOR2X1TS U5397 ( .A(n2195), .B(n4412), .Y(DP_OP_26J224_129_1325_n16) );
NOR2BX1TS U5398 ( .AN(FPADDSUB_LZD_output_NRM2_EW[1]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n4413) );
XOR2X1TS U5399 ( .A(n2195), .B(n4413), .Y(DP_OP_26J224_129_1325_n17) );
XOR2X1TS U5400 ( .A(n2195), .B(n4414), .Y(DP_OP_26J224_129_1325_n18) );
BUFX3TS U5401 ( .A(n2201), .Y(n4898) );
OA22X1TS U5402 ( .A0(Data_1[4]), .A1(n4898), .B0(n4906), .B1(n4899), .Y(
n1662) );
AO22XLTS U5403 ( .A0(Data_2[5]), .A1(n4420), .B0(n2201), .B1(FPMULT_Op_MY[5]), .Y(n1631) );
BUFX3TS U5404 ( .A(n2201), .Y(n4897) );
OA22X1TS U5405 ( .A0(Data_1[5]), .A1(n4897), .B0(n4899), .B1(FPMULT_Op_MX[5]), .Y(n1663) );
AO22XLTS U5406 ( .A0(Data_2[4]), .A1(n4420), .B0(n2201), .B1(FPMULT_Op_MY[4]), .Y(n1630) );
OA22X1TS U5407 ( .A0(Data_1[2]), .A1(n4897), .B0(n4899), .B1(n4908), .Y(
n1660) );
AO22XLTS U5408 ( .A0(Data_2[3]), .A1(n4899), .B0(n2201), .B1(FPMULT_Op_MY[3]), .Y(n1629) );
AO22XLTS U5409 ( .A0(Data_2[2]), .A1(n4529), .B0(n2201), .B1(n4925), .Y(
n1628) );
OA22X1TS U5410 ( .A0(Data_1[1]), .A1(n4897), .B0(n4899), .B1(FPMULT_Op_MX[1]), .Y(n1659) );
OA22X1TS U5411 ( .A0(Data_1[3]), .A1(n4897), .B0(n4899), .B1(n4907), .Y(
n1661) );
AO22XLTS U5412 ( .A0(Data_2[1]), .A1(n4420), .B0(n4419), .B1(n4921), .Y(
n1627) );
OA22X1TS U5413 ( .A0(Data_1[0]), .A1(n4897), .B0(n4899), .B1(FPMULT_Op_MX[0]), .Y(n1658) );
AO22XLTS U5414 ( .A0(Data_2[0]), .A1(n4420), .B0(n4419), .B1(n4922), .Y(
n1626) );
OA22X1TS U5415 ( .A0(Data_1[10]), .A1(n4897), .B0(n4899), .B1(n4902), .Y(
n1668) );
AO22XLTS U5416 ( .A0(Data_2[11]), .A1(n4529), .B0(n2201), .B1(
FPMULT_Op_MY[11]), .Y(n1637) );
OA22X1TS U5417 ( .A0(Data_1[11]), .A1(n4897), .B0(n4899), .B1(n4901), .Y(
n1669) );
AO22XLTS U5418 ( .A0(Data_2[10]), .A1(n4528), .B0(n2201), .B1(
FPMULT_Op_MY[10]), .Y(n1636) );
OA22X1TS U5419 ( .A0(Data_1[8]), .A1(n4897), .B0(n4899), .B1(n4904), .Y(
n1666) );
AO22XLTS U5420 ( .A0(Data_2[9]), .A1(n4528), .B0(n4527), .B1(FPMULT_Op_MY[9]), .Y(n1635) );
AO22XLTS U5421 ( .A0(Data_2[8]), .A1(n4528), .B0(n4900), .B1(n4923), .Y(
n1634) );
OA22X1TS U5422 ( .A0(Data_1[7]), .A1(n4897), .B0(n4899), .B1(FPMULT_Op_MX[7]), .Y(n1665) );
OA22X1TS U5423 ( .A0(Data_1[9]), .A1(n4419), .B0(n4899), .B1(n2196), .Y(
n1667) );
OA22X1TS U5424 ( .A0(Data_1[6]), .A1(n4419), .B0(n4899), .B1(FPMULT_Op_MX[6]), .Y(n1664) );
AO22XLTS U5425 ( .A0(Data_2[6]), .A1(n4528), .B0(n4900), .B1(FPMULT_Op_MY[6]), .Y(n1632) );
NAND2X1TS U5426 ( .A(n4941), .B(n5360), .Y(n1689) );
CLKBUFX3TS U5427 ( .A(n4418), .Y(n4990) );
NOR3BX1TS U5428 ( .AN(FPMULT_Sgf_normalized_result[22]), .B(n4990), .C(n4986), .Y(n4992) );
MX2X1TS U5429 ( .A(FPMULT_Op_MX[30]), .B(FPMULT_exp_oper_result[7]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[7]) );
MX2X1TS U5430 ( .A(n2307), .B(FPMULT_exp_oper_result[6]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[6]) );
MX2X1TS U5431 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_exp_oper_result[5]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[5]) );
MX2X1TS U5432 ( .A(FPMULT_exp_oper_result[4]), .B(
FPMULT_Exp_module_Data_S[4]), .S0(n4530), .Y(n1590) );
MX2X1TS U5433 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_exp_oper_result[4]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[4]) );
MX2X1TS U5434 ( .A(FPMULT_exp_oper_result[3]), .B(
FPMULT_Exp_module_Data_S[3]), .S0(n4530), .Y(n1591) );
MX2X1TS U5435 ( .A(FPMULT_Op_MX[26]), .B(FPMULT_exp_oper_result[3]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[3]) );
MX2X1TS U5436 ( .A(FPMULT_exp_oper_result[2]), .B(
FPMULT_Exp_module_Data_S[2]), .S0(n4530), .Y(n1592) );
MX2X1TS U5437 ( .A(FPMULT_Op_MX[25]), .B(FPMULT_exp_oper_result[2]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[2]) );
MX2X1TS U5438 ( .A(n2323), .B(FPMULT_Exp_module_Data_S[1]), .S0(n4530), .Y(
n1593) );
MX2X1TS U5439 ( .A(FPMULT_Op_MX[24]), .B(n2323), .S0(FPMULT_FSM_selector_A),
.Y(FPMULT_S_Oper_A_exp[1]) );
MX2X1TS U5440 ( .A(FPMULT_exp_oper_result[0]), .B(
FPMULT_Exp_module_Data_S[0]), .S0(n4530), .Y(n1594) );
MX2X1TS U5441 ( .A(n2349), .B(FPMULT_exp_oper_result[0]), .S0(
FPMULT_FSM_selector_A), .Y(FPMULT_S_Oper_A_exp[0]) );
OAI32X1TS U5442 ( .A0(n4423), .A1(n5168), .A2(n2431), .B0(n4422), .B1(n4423),
.Y(n4441) );
NAND2BX1TS U5443 ( .AN(n4423), .B(n4440), .Y(n4454) );
NAND2X1TS U5444 ( .A(FPMULT_Op_MY[10]), .B(n2196), .Y(n4436) );
OAI2BB1X1TS U5445 ( .A0N(n4426), .A1N(n4425), .B0(n4424), .Y(n4439) );
OAI2BB1X1TS U5446 ( .A0N(n4437), .A1N(n4436), .B0(n4439), .Y(n4427) );
XNOR2X1TS U5447 ( .A(n4429), .B(n4428), .Y(n4431) );
XOR2X1TS U5448 ( .A(n4431), .B(n4430), .Y(n4451) );
OAI2BB1X1TS U5449 ( .A0N(n4454), .A1N(n4452), .B0(n4432), .Y(mult_x_311_n14)
);
ACHCINX2TS U5450 ( .CIN(n4435), .A(n4434), .B(n4433), .CO(n4456) );
XNOR2X1TS U5451 ( .A(n4437), .B(n4436), .Y(n4438) );
XNOR2X1TS U5452 ( .A(n4439), .B(n4438), .Y(n4455) );
ACHCINX2TS U5453 ( .CIN(n4456), .A(n4455), .B(n4458), .CO(mult_x_311_n17) );
XOR2XLTS U5454 ( .A(n4443), .B(n4470), .Y(n4444) );
XOR2X1TS U5455 ( .A(n4445), .B(n4444), .Y(mult_x_311_n37) );
AOI31XLTS U5456 ( .A0(n4923), .A1(FPMULT_Op_MX[7]), .A2(n4449), .B0(n4448),
.Y(n4450) );
NOR2BX1TS U5457 ( .AN(n4467), .B(n4450), .Y(intadd_520_A_0_) );
XOR2X1TS U5458 ( .A(n4452), .B(n4451), .Y(n4453) );
XOR2X1TS U5459 ( .A(n4454), .B(n4453), .Y(mult_x_311_n15) );
XNOR2X1TS U5460 ( .A(n4456), .B(n4455), .Y(n4457) );
XOR2X1TS U5461 ( .A(n4458), .B(n4457), .Y(mult_x_311_n18) );
XOR2X1TS U5462 ( .A(n4460), .B(n4459), .Y(n4461) );
XOR2X1TS U5463 ( .A(n4462), .B(n4461), .Y(mult_x_311_n23) );
XOR2X1TS U5464 ( .A(n4464), .B(n4463), .Y(n4465) );
XOR2X1TS U5465 ( .A(n4466), .B(n4465), .Y(mult_x_311_n30) );
OAI2BB1X1TS U5466 ( .A0N(n4469), .A1N(n4468), .B0(n4467), .Y(intadd_520_B_1_) );
AOI21X1TS U5467 ( .A0(n4472), .A1(n4471), .B0(n4470), .Y(intadd_520_B_0_) );
OAI32X1TS U5468 ( .A0(n4474), .A1(n5159), .A2(n4415), .B0(n4473), .B1(n4474),
.Y(n4492) );
NAND2BX1TS U5469 ( .AN(n4474), .B(n4491), .Y(n4503) );
NAND2X1TS U5470 ( .A(FPMULT_Op_MY[4]), .B(n4907), .Y(n4487) );
OAI2BB1X1TS U5471 ( .A0N(n4477), .A1N(n4476), .B0(n4475), .Y(n4490) );
OAI2BB1X1TS U5472 ( .A0N(n4488), .A1N(n4487), .B0(n4490), .Y(n4478) );
XNOR2X1TS U5473 ( .A(n4480), .B(n4479), .Y(n4482) );
XOR2X1TS U5474 ( .A(n4482), .B(n4481), .Y(n4501) );
OAI2BB1X1TS U5475 ( .A0N(n4503), .A1N(n2226), .B0(n4483), .Y(mult_x_310_n14)
);
ACHCINX2TS U5476 ( .CIN(n4486), .A(n4485), .B(n4484), .CO(n4505) );
XNOR2X1TS U5477 ( .A(n4488), .B(n4487), .Y(n4489) );
XNOR2X1TS U5478 ( .A(n4490), .B(n4489), .Y(n4504) );
ACHCINX2TS U5479 ( .CIN(n4505), .A(n4504), .B(n4507), .CO(mult_x_310_n17) );
XOR2X1TS U5480 ( .A(n4496), .B(n4495), .Y(mult_x_310_n37) );
AOI31XLTS U5481 ( .A0(n4925), .A1(FPMULT_Op_MX[1]), .A2(n4499), .B0(n4498),
.Y(n4500) );
NOR2BX1TS U5482 ( .AN(n4516), .B(n4500), .Y(intadd_521_A_0_) );
XOR2X1TS U5483 ( .A(n2226), .B(n4501), .Y(n4502) );
XOR2X1TS U5484 ( .A(n4503), .B(n4502), .Y(mult_x_310_n15) );
XNOR2X1TS U5485 ( .A(n4505), .B(n4504), .Y(n4506) );
XOR2X1TS U5486 ( .A(n4507), .B(n4506), .Y(mult_x_310_n18) );
XOR2X1TS U5487 ( .A(n4509), .B(n4508), .Y(n4510) );
XOR2X1TS U5488 ( .A(n4511), .B(n4510), .Y(mult_x_310_n23) );
XOR2XLTS U5489 ( .A(n4513), .B(n4512), .Y(n4514) );
XOR2X1TS U5490 ( .A(n4515), .B(n4514), .Y(mult_x_310_n30) );
OAI2BB1X1TS U5491 ( .A0N(n4518), .A1N(n4517), .B0(n4516), .Y(intadd_521_B_1_) );
AOI21X1TS U5492 ( .A0(n4521), .A1(n4520), .B0(n4519), .Y(intadd_521_B_0_) );
XNOR2X1TS U5493 ( .A(DP_OP_234J224_132_4955_n1), .B(n4531), .Y(n4532) );
MX2X1TS U5494 ( .A(FPADDSUB_DMP_exp_NRM2_EW[7]), .B(
FPADDSUB_DMP_exp_NRM_EW[7]), .S0(n4537), .Y(n1418) );
MX2X1TS U5495 ( .A(FPADDSUB_DMP_exp_NRM2_EW[6]), .B(
FPADDSUB_DMP_exp_NRM_EW[6]), .S0(n4537), .Y(n1423) );
MX2X1TS U5496 ( .A(FPADDSUB_DMP_exp_NRM2_EW[5]), .B(
FPADDSUB_DMP_exp_NRM_EW[5]), .S0(n4537), .Y(n1428) );
MX2X1TS U5497 ( .A(FPADDSUB_DMP_exp_NRM2_EW[4]), .B(
FPADDSUB_DMP_exp_NRM_EW[4]), .S0(n4537), .Y(n1433) );
MX2X1TS U5498 ( .A(FPADDSUB_DMP_exp_NRM2_EW[3]), .B(
FPADDSUB_DMP_exp_NRM_EW[3]), .S0(n4537), .Y(n1438) );
MX2X1TS U5499 ( .A(FPADDSUB_DMP_exp_NRM2_EW[2]), .B(
FPADDSUB_DMP_exp_NRM_EW[2]), .S0(n4537), .Y(n1443) );
MX2X1TS U5500 ( .A(FPADDSUB_DMP_exp_NRM2_EW[1]), .B(
FPADDSUB_DMP_exp_NRM_EW[1]), .S0(n4537), .Y(n1448) );
MX2X1TS U5501 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
FPADDSUB_DMP_exp_NRM_EW[0]), .S0(n4537), .Y(n1453) );
OAI2BB1X1TS U5502 ( .A0N(FPADDSUB_LZD_output_NRM2_EW[4]), .A1N(n4539), .B0(
n4533), .Y(n1330) );
OAI2BB1X1TS U5503 ( .A0N(FPADDSUB_LZD_output_NRM2_EW[3]), .A1N(n4539), .B0(
n4534), .Y(n1322) );
OAI2BB1X1TS U5504 ( .A0N(FPADDSUB_LZD_output_NRM2_EW[2]), .A1N(n4539), .B0(
n4535), .Y(n1318) );
AOI2BB1XLTS U5505 ( .A0N(FPADDSUB_LZD_output_NRM2_EW[1]), .A1N(n4537), .B0(
n4536), .Y(n1409) );
AO21XLTS U5506 ( .A0(FPADDSUB_LZD_output_NRM2_EW[0]), .A1(n4539), .B0(n4538),
.Y(n1314) );
OA21XLTS U5507 ( .A0(n2280), .A1(overflow_flag_addsubt), .B0(n4544), .Y(
n1411) );
AND4X1TS U5508 ( .A(FPMULT_Exp_module_Data_S[3]), .B(
FPMULT_Exp_module_Data_S[2]), .C(FPMULT_Exp_module_Data_S[1]), .D(
FPMULT_Exp_module_Data_S[0]), .Y(n4540) );
AND4X1TS U5509 ( .A(FPMULT_Exp_module_Data_S[6]), .B(
FPMULT_Exp_module_Data_S[5]), .C(FPMULT_Exp_module_Data_S[4]), .D(
n4540), .Y(n4541) );
NOR4X1TS U5510 ( .A(FPMULT_Exp_module_Data_S[8]), .B(
FPMULT_Exp_module_Data_S[7]), .C(n4541), .D(n4941), .Y(n4542) );
NOR2BX1TS U5511 ( .AN(n4543), .B(FPADDSUB_SIGN_FLAG_SHT1SHT2), .Y(n4545) );
OAI22X1TS U5512 ( .A0(n4545), .A1(n4544), .B0(n2280), .B1(n5227), .Y(n1356)
);
NOR3BX1TS U5513 ( .AN(n5515), .B(n4547), .C(FPADDSUB_exp_rslt_NRM2_EW1[6]),
.Y(n4548) );
AOI21X1TS U5514 ( .A0(n5353), .A1(n5228), .B0(n4548), .Y(n1467) );
AFHCONX2TS U5515 ( .A(n4551), .B(n4550), .CI(n4549), .CON(n4589), .S(n4552)
);
BUFX3TS U5516 ( .A(n3561), .Y(n4650) );
MX2X1TS U5517 ( .A(n4552), .B(FPMULT_P_Sgf[13]), .S0(n4639), .Y(n1542) );
AFHCONX2TS U5518 ( .A(n4555), .B(n4554), .CI(n4553), .CON(n4570), .S(n4556)
);
AFHCONX2TS U5519 ( .A(n4559), .B(n4558), .CI(n4557), .CON(n4562), .S(n4561)
);
MX2X1TS U5520 ( .A(n4561), .B(FPMULT_P_Sgf[15]), .S0(n4560), .Y(n1544) );
AFHCINX2TS U5521 ( .CIN(n4562), .B(n4563), .A(n4564), .S(n4565), .CO(n4553)
);
AFHCINX2TS U5522 ( .CIN(n4566), .B(n4567), .A(n4568), .S(n4569), .CO(n4578)
);
AFHCINX2TS U5523 ( .CIN(n4570), .B(n4571), .A(n4572), .S(n4573), .CO(n4574)
);
AFHCONX2TS U5524 ( .A(n4576), .B(n4575), .CI(n4574), .CON(n4566), .S(n4577)
);
AFHCONX2TS U5525 ( .A(n4580), .B(n4579), .CI(n4578), .CON(n4583), .S(n4581)
);
MX2X1TS U5526 ( .A(FPMULT_P_Sgf[1]), .B(FPMULT_Sgf_operation_Result[1]),
.S0(n4582), .Y(n1530) );
MX2X1TS U5527 ( .A(FPMULT_P_Sgf[5]), .B(FPMULT_Sgf_operation_Result[5]),
.S0(n4600), .Y(n1534) );
MX2X1TS U5528 ( .A(FPMULT_P_Sgf[3]), .B(FPMULT_Sgf_operation_Result[3]),
.S0(n4600), .Y(n1532) );
MX2X1TS U5529 ( .A(FPMULT_P_Sgf[4]), .B(FPMULT_Sgf_operation_Result[4]),
.S0(n4600), .Y(n1533) );
AFHCINX2TS U5530 ( .CIN(n4583), .B(n4584), .A(n4585), .S(n4586), .CO(n4658)
);
MX2X1TS U5531 ( .A(FPMULT_P_Sgf[2]), .B(FPMULT_Sgf_operation_Result[2]),
.S0(n4600), .Y(n1531) );
MX2X1TS U5532 ( .A(FPMULT_P_Sgf[0]), .B(FPMULT_Sgf_operation_Result[0]),
.S0(n4600), .Y(n1529) );
MX2X1TS U5533 ( .A(FPMULT_P_Sgf[9]), .B(n4587), .S0(n4600), .Y(n1538) );
MX2X1TS U5534 ( .A(n4588), .B(FPMULT_P_Sgf[10]), .S0(n4650), .Y(n1539) );
AFHCINX2TS U5535 ( .CIN(n4589), .B(n4590), .A(n4591), .S(n4592), .CO(n4557)
);
MX2X1TS U5536 ( .A(n4592), .B(FPMULT_P_Sgf[14]), .S0(n4639), .Y(n1543) );
OR2X1TS U5537 ( .A(n4594), .B(n4593), .Y(n4596) );
CLKAND2X2TS U5538 ( .A(n4596), .B(n4595), .Y(n4597) );
MX2X1TS U5539 ( .A(n4597), .B(FPMULT_P_Sgf[12]), .S0(n4639), .Y(n1541) );
MX2X1TS U5540 ( .A(n4598), .B(FPMULT_P_Sgf[8]), .S0(n4639), .Y(n1537) );
MX2X1TS U5541 ( .A(FPMULT_P_Sgf[6]), .B(n4599), .S0(n4600), .Y(n1535) );
MX2X1TS U5542 ( .A(FPMULT_P_Sgf[7]), .B(n4601), .S0(n4600), .Y(n1536) );
MX2X1TS U5543 ( .A(n4602), .B(FPMULT_P_Sgf[11]), .S0(n4639), .Y(n1540) );
INVX2TS U5544 ( .A(n4606), .Y(n4607) );
XNOR2X1TS U5545 ( .A(n4610), .B(n3254), .Y(n4611) );
CLKMX2X2TS U5546 ( .A(n4611), .B(FPMULT_P_Sgf[43]), .S0(n4639), .Y(n1572) );
AFHCINX2TS U5547 ( .CIN(n4616), .B(n4617), .A(n4618), .S(n4619), .CO(n4612)
);
AFHCONX2TS U5548 ( .A(n4622), .B(n4621), .CI(n4620), .CON(n4616), .S(n4623)
);
AFHCINX2TS U5549 ( .CIN(n4624), .B(n4625), .A(n4626), .S(n4627), .CO(n4620)
);
AFHCONX2TS U5550 ( .A(n4630), .B(n4629), .CI(n4628), .CON(n4624), .S(n4631)
);
AFHCONX2TS U5551 ( .A(n4638), .B(n4637), .CI(n4636), .CON(n4632), .S(n4640)
);
AFHCINX2TS U5552 ( .CIN(n4641), .B(n4642), .A(n4643), .S(n4644), .CO(n4636)
);
AFHCONX2TS U5553 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[5]), .B(n4646), .CI(
n4645), .CON(n4641), .S(n4647) );
AFHCONX2TS U5554 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[3]), .B(n4649), .CI(
n4648), .CON(n3341), .S(n4651) );
AFHCONX2TS U5555 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[1]), .B(n4653), .CI(
n4652), .CON(n3338), .S(n4654) );
AFHCONX2TS U5556 ( .A(n4660), .B(n4659), .CI(n4658), .CON(n4655), .S(n4661)
);
INVX2TS U5557 ( .A(mult_x_309_n26), .Y(n4662) );
OAI32X1TS U5558 ( .A0(n4664), .A1(n4663), .A2(n5162), .B0(n4662), .B1(n4664),
.Y(n4674) );
OAI32X1TS U5559 ( .A0(n4666), .A1(n4669), .A2(n5248), .B0(FPMULT_Op_MX[20]),
.B1(n4665), .Y(n4673) );
NAND2X1TS U5560 ( .A(n4674), .B(n4673), .Y(n4672) );
NAND2X1TS U5561 ( .A(n4667), .B(n4672), .Y(intadd_522_A_0_) );
OAI32X1TS U5562 ( .A0(mult_x_309_n42), .A1(n5156), .A2(n4669), .B0(n4668),
.B1(mult_x_309_n42), .Y(intadd_522_B_0_) );
NOR2XLTS U5563 ( .A(n5162), .B(n5253), .Y(n4671) );
OAI211XLTS U5564 ( .A0(n5162), .A1(n5156), .B0(n2197), .C0(n4930), .Y(n4670)
);
XNOR2X1TS U5565 ( .A(n4671), .B(n4670), .Y(intadd_522_CI) );
OA21XLTS U5566 ( .A0(n4674), .A1(n4673), .B0(n4672), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_left_GENSTOP_inst_mult_N2) );
CMPR32X2TS U5567 ( .A(FPMULT_Op_MX[20]), .B(n4930), .C(n4675), .CO(
mult_x_309_n19), .S(mult_x_309_n20) );
OAI2BB1X1TS U5568 ( .A0N(mult_x_309_n52), .A1N(mult_x_309_n66), .B0(n4676),
.Y(mult_x_309_n24) );
AOI21X1TS U5569 ( .A0(n4677), .A1(n5156), .B0(mult_x_309_n26), .Y(
mult_x_309_n27) );
OA21XLTS U5570 ( .A0(n4680), .A1(n4679), .B0(n4678), .Y(mult_x_309_n32) );
AOI21X1TS U5571 ( .A0(n5162), .A1(n5248), .B0(mult_x_309_n33), .Y(
mult_x_309_n34) );
AOI22X1TS U5572 ( .A0(FPMULT_Op_MX[16]), .A1(FPMULT_Op_MY[17]), .B0(
FPMULT_Op_MX[17]), .B1(FPMULT_Op_MY[16]), .Y(n4681) );
AOI21X1TS U5573 ( .A0(intadd_519_A_7_), .A1(mult_x_312_n53), .B0(n4681), .Y(
n4683) );
NAND2X1TS U5574 ( .A(n4683), .B(mult_x_312_n13), .Y(n4682) );
OAI2BB1X1TS U5575 ( .A0N(intadd_519_A_7_), .A1N(mult_x_312_n53), .B0(n4682),
.Y(intadd_519_B_7_) );
OA21XLTS U5576 ( .A0(n4683), .A1(mult_x_312_n13), .B0(n4682), .Y(
intadd_519_B_6_) );
OA21XLTS U5577 ( .A0(n4686), .A1(n4685), .B0(n4684), .Y(
FPMULT_Sgf_operation_EVEN1_left_RECURSIVE_EVEN1_right_GENSTOP_inst_mult_N2) );
OAI32X1TS U5578 ( .A0(n4688), .A1(n5520), .A2(n4693), .B0(n4695), .B1(n4688),
.Y(n4690) );
OA21XLTS U5579 ( .A0(n4691), .A1(n4690), .B0(n4689), .Y(mult_x_312_n20) );
OAI32X1TS U5580 ( .A0(mult_x_312_n26), .A1(n5171), .A2(n4693), .B0(n4692),
.B1(mult_x_312_n26), .Y(mult_x_312_n27) );
OAI31X1TS U5581 ( .A0(n5520), .A1(n4696), .A2(n4695), .B0(n4694), .Y(
mult_x_312_n31) );
OAI32X1TS U5582 ( .A0(mult_x_312_n33), .A1(n5163), .A2(n5255), .B0(n4697),
.B1(mult_x_312_n33), .Y(mult_x_312_n34) );
NOR4BX1TS U5583 ( .AN(operation_reg[1]), .B(dataB[28]), .C(operation_reg[0]),
.D(dataB[23]), .Y(n4702) );
NOR4X1TS U5584 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[25]),
.Y(n4701) );
NAND4XLTS U5585 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n4699) );
NAND4XLTS U5586 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n4698) );
OR3X1TS U5587 ( .A(n5521), .B(n4699), .C(n4698), .Y(n4703) );
NOR3XLTS U5588 ( .A(dataB[29]), .B(dataB[31]), .C(n4703), .Y(n4700) );
AOI31XLTS U5589 ( .A0(n4702), .A1(n4701), .A2(n4700), .B0(dataB[27]), .Y(
n4713) );
NOR4X1TS U5590 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n4706) );
NOR4X1TS U5591 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n4705) );
NOR4BX1TS U5592 ( .AN(operation_reg[1]), .B(operation_reg[0]), .C(dataA[31]),
.D(n5521), .Y(n4704) );
NOR2X1TS U5593 ( .A(operation_reg[1]), .B(n4703), .Y(n4711) );
AOI31XLTS U5594 ( .A0(n4706), .A1(n4705), .A2(n4704), .B0(n4711), .Y(n4709)
);
NAND3XLTS U5595 ( .A(dataB[28]), .B(dataB[23]), .C(dataB[29]), .Y(n4708) );
NAND4XLTS U5596 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[25]),
.Y(n4707) );
OAI31X1TS U5597 ( .A0(n4709), .A1(n4708), .A2(n4707), .B0(dataB[27]), .Y(
n4710) );
NAND4XLTS U5598 ( .A(n5524), .B(n5523), .C(n5522), .D(n4710), .Y(n4712) );
OAI2BB2XLTS U5599 ( .B0(n4713), .B1(n4712), .A0N(n4711), .A1N(
operation_reg[0]), .Y(NaN_reg) );
NOR4X1TS U5600 ( .A(n2290), .B(n4745), .C(n4714), .D(n4771), .Y(n4715) );
NAND2X1TS U5601 ( .A(n4784), .B(n4715), .Y(n4718) );
NOR2X1TS U5602 ( .A(n4717), .B(n4716), .Y(n4721) );
OAI22X1TS U5603 ( .A0(n4719), .A1(n4718), .B0(n4721), .B1(n4720), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]) );
NOR2BX1TS U5604 ( .AN(n4721), .B(n4720), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]) );
AOI32X1TS U5605 ( .A0(n4761), .A1(n4723), .A2(n4759), .B0(n4722), .B1(n4723),
.Y(FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]) );
OAI22X1TS U5606 ( .A0(n4775), .A1(n4726), .B0(n4725), .B1(n4724), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]) );
OR2X1TS U5607 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Overflow_flag_A), .Y(n4727) );
AO22XLTS U5608 ( .A0(operation[2]), .A1(n4727), .B0(n4728), .B1(
overflow_flag_addsubt), .Y(overflow_flag) );
AO22XLTS U5609 ( .A0(operation[2]), .A1(n2358), .B0(n4728), .B1(
underflow_flag_addsubt), .Y(underflow_flag) );
NAND3XLTS U5610 ( .A(n4729), .B(n5359), .C(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n4738) );
NAND2X1TS U5611 ( .A(n4730), .B(n4738), .Y(n2191) );
OAI222X1TS U5612 ( .A0(n4735), .A1(n4734), .B0(n5206), .B1(n4733), .C0(n4732), .C1(n4731), .Y(operation_ready) );
AOI21X1TS U5613 ( .A0(n4739), .A1(n4738), .B0(n4737), .Y(n2149) );
AO21XLTS U5614 ( .A0(FPADDSUB_Shift_reg_FLAGS_7_6), .A1(n4741), .B0(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_), .Y(n2148) );
AOI22X1TS U5615 ( .A0(n4743), .A1(n5225), .B0(n5361), .B1(n4741), .Y(n2147)
);
CLKBUFX3TS U5616 ( .A(n5105), .Y(n5077) );
AOI22X1TS U5617 ( .A0(n4743), .A1(n5361), .B0(n5077), .B1(n4741), .Y(n2146)
);
CLKBUFX2TS U5618 ( .A(FPADDSUB_Shift_reg_FLAGS_7[2]), .Y(n5061) );
AOI22X1TS U5619 ( .A0(n4743), .A1(n5091), .B0(n5034), .B1(n4741), .Y(n2143)
);
NAND2X1TS U5620 ( .A(FPSENCOS_cont_iter_out[0]), .B(n4745), .Y(n4744) );
OA21XLTS U5621 ( .A0(FPSENCOS_cont_iter_out[0]), .A1(n4745), .B0(n4744), .Y(
n2141) );
AOI22X1TS U5622 ( .A0(n4745), .A1(n4761), .B0(n5172), .B1(n4744), .Y(n2140)
);
AOI21X1TS U5623 ( .A0(n5313), .A1(n4747), .B0(n4746), .Y(n2138) );
XNOR2X1TS U5624 ( .A(FPSENCOS_cont_var_out[0]), .B(n4748), .Y(n2137) );
AO22XLTS U5625 ( .A0(n4768), .A1(FPSENCOS_d_ff1_shift_region_flag_out[0]),
.B0(n4771), .B1(region_flag[0]), .Y(n2135) );
BUFX3TS U5626 ( .A(n4769), .Y(n4767) );
AO22XLTS U5627 ( .A0(n4768), .A1(FPSENCOS_d_ff1_shift_region_flag_out[1]),
.B0(n4767), .B1(region_flag[1]), .Y(n2134) );
OAI21X1TS U5628 ( .A0(n5191), .A1(n2203), .B0(n4749), .Y(n4756) );
AOI21X1TS U5629 ( .A0(n4766), .A1(n4756), .B0(n4750), .Y(n4755) );
OAI2BB1X1TS U5630 ( .A0N(FPSENCOS_d_ff3_LUT_out[0]), .A1N(n4784), .B0(n4755),
.Y(n2133) );
AOI21X1TS U5631 ( .A0(n2298), .A1(n5172), .B0(n4751), .Y(n4753) );
OAI2BB2XLTS U5632 ( .B0(n4752), .B1(n4753), .A0N(FPSENCOS_d_ff3_LUT_out[5]),
.A1N(n4781), .Y(n2128) );
AO21XLTS U5633 ( .A0(FPSENCOS_d_ff3_LUT_out[8]), .A1(n4868), .B0(n4754), .Y(
n2125) );
OAI2BB1X1TS U5634 ( .A0N(FPSENCOS_d_ff3_LUT_out[9]), .A1N(n4784), .B0(n4753),
.Y(n2124) );
OAI2BB2XLTS U5635 ( .B0(n4763), .B1(n4755), .A0N(FPSENCOS_d_ff3_LUT_out[10]),
.A1N(n4781), .Y(n2123) );
AO21XLTS U5636 ( .A0(FPSENCOS_d_ff3_LUT_out[13]), .A1(n4782), .B0(n4756),
.Y(n2121) );
AO21XLTS U5637 ( .A0(FPSENCOS_d_ff3_LUT_out[19]), .A1(n4782), .B0(n2298),
.Y(n2119) );
AO22XLTS U5638 ( .A0(n2298), .A1(n4757), .B0(FPSENCOS_d_ff3_LUT_out[21]),
.B1(n4782), .Y(n2118) );
AOI21X1TS U5639 ( .A0(n4759), .A1(n5191), .B0(n4758), .Y(n4760) );
BUFX3TS U5640 ( .A(n4787), .Y(n4803) );
OAI32X1TS U5641 ( .A0(n4763), .A1(n4762), .A2(n4784), .B0(n4761), .B1(n4763),
.Y(n4764) );
AO21XLTS U5642 ( .A0(FPSENCOS_d_ff3_LUT_out[25]), .A1(n4782), .B0(n4764),
.Y(n2115) );
AOI32X1TS U5643 ( .A0(n4766), .A1(n4869), .A2(n4765), .B0(n5418), .B1(n4784),
.Y(n2114) );
NAND2BXLTS U5644 ( .AN(FPSENCOS_d_ff3_LUT_out[27]), .B(n4781), .Y(n2113) );
AO22XLTS U5645 ( .A0(n4770), .A1(FPSENCOS_d_ff1_Z[0]), .B0(n4767), .B1(
Data_1[0]), .Y(n2112) );
AO22XLTS U5646 ( .A0(n4768), .A1(FPSENCOS_d_ff1_Z[1]), .B0(n4767), .B1(
Data_1[1]), .Y(n2111) );
AO22XLTS U5647 ( .A0(n4768), .A1(FPSENCOS_d_ff1_Z[2]), .B0(n4767), .B1(
Data_1[2]), .Y(n2110) );
AO22XLTS U5648 ( .A0(n4770), .A1(FPSENCOS_d_ff1_Z[3]), .B0(n4767), .B1(
Data_1[3]), .Y(n2109) );
INVX2TS U5649 ( .A(n4769), .Y(n4772) );
AO22XLTS U5650 ( .A0(n4772), .A1(FPSENCOS_d_ff1_Z[4]), .B0(n4767), .B1(
Data_1[4]), .Y(n2108) );
AO22XLTS U5651 ( .A0(n4772), .A1(FPSENCOS_d_ff1_Z[5]), .B0(n4767), .B1(
Data_1[5]), .Y(n2107) );
AO22XLTS U5652 ( .A0(n4772), .A1(FPSENCOS_d_ff1_Z[6]), .B0(n4767), .B1(
Data_1[6]), .Y(n2106) );
AO22XLTS U5653 ( .A0(n4772), .A1(FPSENCOS_d_ff1_Z[7]), .B0(n4767), .B1(
Data_1[7]), .Y(n2105) );
AO22XLTS U5654 ( .A0(n4772), .A1(FPSENCOS_d_ff1_Z[8]), .B0(n4767), .B1(
Data_1[8]), .Y(n2104) );
AO22XLTS U5655 ( .A0(n4772), .A1(FPSENCOS_d_ff1_Z[9]), .B0(n4767), .B1(
Data_1[9]), .Y(n2103) );
AO22XLTS U5656 ( .A0(n4772), .A1(FPSENCOS_d_ff1_Z[10]), .B0(n4767), .B1(
Data_1[10]), .Y(n2102) );
AO22XLTS U5657 ( .A0(n4772), .A1(FPSENCOS_d_ff1_Z[11]), .B0(n4767), .B1(
Data_1[11]), .Y(n2101) );
AO22XLTS U5658 ( .A0(n4772), .A1(FPSENCOS_d_ff1_Z[12]), .B0(n4771), .B1(
Data_1[12]), .Y(n2100) );
AO22XLTS U5659 ( .A0(n4768), .A1(FPSENCOS_d_ff1_Z[13]), .B0(n4771), .B1(
Data_1[13]), .Y(n2099) );
AO22XLTS U5660 ( .A0(n4768), .A1(FPSENCOS_d_ff1_Z[14]), .B0(n4771), .B1(
Data_1[14]), .Y(n2098) );
AO22XLTS U5661 ( .A0(n4770), .A1(FPSENCOS_d_ff1_Z[15]), .B0(n4771), .B1(
Data_1[15]), .Y(n2097) );
AO22XLTS U5662 ( .A0(n4768), .A1(FPSENCOS_d_ff1_Z[16]), .B0(n4769), .B1(
Data_1[16]), .Y(n2096) );
AO22XLTS U5663 ( .A0(n4768), .A1(FPSENCOS_d_ff1_Z[17]), .B0(n4769), .B1(
Data_1[17]), .Y(n2095) );
AO22XLTS U5664 ( .A0(n4770), .A1(FPSENCOS_d_ff1_Z[18]), .B0(n4769), .B1(
Data_1[18]), .Y(n2094) );
AO22XLTS U5665 ( .A0(n4770), .A1(FPSENCOS_d_ff1_Z[19]), .B0(n4767), .B1(
Data_1[19]), .Y(n2093) );
INVX2TS U5666 ( .A(n4769), .Y(n4770) );
AO22XLTS U5667 ( .A0(n4768), .A1(FPSENCOS_d_ff1_Z[20]), .B0(n4769), .B1(
Data_1[20]), .Y(n2092) );
AO22XLTS U5668 ( .A0(n4770), .A1(FPSENCOS_d_ff1_Z[21]), .B0(n4769), .B1(
Data_1[21]), .Y(n2091) );
AO22XLTS U5669 ( .A0(n4768), .A1(FPSENCOS_d_ff1_Z[22]), .B0(n4771), .B1(
Data_1[22]), .Y(n2090) );
AO22XLTS U5670 ( .A0(n4768), .A1(FPSENCOS_d_ff1_Z[23]), .B0(n4771), .B1(
Data_1[23]), .Y(n2089) );
AO22XLTS U5671 ( .A0(n4770), .A1(FPSENCOS_d_ff1_Z[24]), .B0(n4769), .B1(
Data_1[24]), .Y(n2088) );
AO22XLTS U5672 ( .A0(n4768), .A1(FPSENCOS_d_ff1_Z[25]), .B0(n4771), .B1(
Data_1[25]), .Y(n2087) );
AO22XLTS U5673 ( .A0(n4768), .A1(FPSENCOS_d_ff1_Z[26]), .B0(n4771), .B1(
Data_1[26]), .Y(n2086) );
AO22XLTS U5674 ( .A0(n4772), .A1(FPSENCOS_d_ff1_Z[27]), .B0(n4771), .B1(
Data_1[27]), .Y(n2085) );
AO22XLTS U5675 ( .A0(n4770), .A1(FPSENCOS_d_ff1_Z[28]), .B0(n4771), .B1(
Data_1[28]), .Y(n2084) );
AO22XLTS U5676 ( .A0(n4770), .A1(FPSENCOS_d_ff1_Z[29]), .B0(n4771), .B1(
Data_1[29]), .Y(n2083) );
AO22XLTS U5677 ( .A0(n4768), .A1(FPSENCOS_d_ff1_Z[30]), .B0(n4771), .B1(
Data_1[30]), .Y(n2082) );
AO22XLTS U5678 ( .A0(n4770), .A1(FPSENCOS_d_ff1_Z[31]), .B0(n4769), .B1(
Data_1[31]), .Y(n2081) );
AO22XLTS U5679 ( .A0(n4775), .A1(result_add_subt[0]), .B0(n4866), .B1(
FPSENCOS_d_ff_Zn[0]), .Y(n2074) );
NAND3X1TS U5680 ( .A(n5319), .B(FPSENCOS_cont_var_out[0]), .C(ready_add_subt), .Y(n4774) );
BUFX3TS U5681 ( .A(n4774), .Y(n4776) );
BUFX3TS U5682 ( .A(n4774), .Y(n4871) );
OAI2BB2XLTS U5683 ( .B0(n4776), .B1(n5310), .A0N(n4871), .A1N(
FPSENCOS_d_ff_Yn[0]), .Y(n2073) );
BUFX3TS U5684 ( .A(n4773), .Y(n4880) );
OAI2BB2XLTS U5685 ( .B0(n4777), .B1(n5310), .A0N(n4880), .A1N(
FPSENCOS_d_ff_Xn[0]), .Y(n2072) );
AO22XLTS U5686 ( .A0(n4867), .A1(result_add_subt[1]), .B0(n4866), .B1(
FPSENCOS_d_ff_Zn[1]), .Y(n2071) );
BUFX3TS U5687 ( .A(n4774), .Y(n4865) );
BUFX3TS U5688 ( .A(n4865), .Y(n4870) );
OAI2BB2XLTS U5689 ( .B0(n4776), .B1(n5203), .A0N(n4870), .A1N(n2309), .Y(
n2070) );
AO22XLTS U5690 ( .A0(n4775), .A1(result_add_subt[2]), .B0(n4778), .B1(
FPSENCOS_d_ff_Zn[2]), .Y(n2068) );
OAI2BB2XLTS U5691 ( .B0(n4776), .B1(n5202), .A0N(n4870), .A1N(
FPSENCOS_d_ff_Yn[2]), .Y(n2067) );
AO22XLTS U5692 ( .A0(n4867), .A1(result_add_subt[3]), .B0(n4866), .B1(
FPSENCOS_d_ff_Zn[3]), .Y(n2065) );
OAI2BB2XLTS U5693 ( .B0(n4776), .B1(n5201), .A0N(n4870), .A1N(
FPSENCOS_d_ff_Yn[3]), .Y(n2064) );
AO22XLTS U5694 ( .A0(n4775), .A1(result_add_subt[4]), .B0(n4778), .B1(
FPSENCOS_d_ff_Zn[4]), .Y(n2062) );
OAI2BB2XLTS U5695 ( .B0(n4776), .B1(n5200), .A0N(n4870), .A1N(
FPSENCOS_d_ff_Yn[4]), .Y(n2061) );
AO22XLTS U5696 ( .A0(n4775), .A1(result_add_subt[5]), .B0(n4866), .B1(
FPSENCOS_d_ff_Zn[5]), .Y(n2059) );
BUFX3TS U5697 ( .A(n4871), .Y(n4793) );
OAI2BB2XLTS U5698 ( .B0(n4776), .B1(n5311), .A0N(n4793), .A1N(
FPSENCOS_d_ff_Yn[5]), .Y(n2058) );
OAI2BB2XLTS U5699 ( .B0(n4777), .B1(n5311), .A0N(n4863), .A1N(
FPSENCOS_d_ff_Xn[5]), .Y(n2057) );
AO22XLTS U5700 ( .A0(n4867), .A1(result_add_subt[6]), .B0(n4866), .B1(
FPSENCOS_d_ff_Zn[6]), .Y(n2056) );
OAI2BB2XLTS U5701 ( .B0(n4776), .B1(n5306), .A0N(n4793), .A1N(
FPSENCOS_d_ff_Yn[6]), .Y(n2055) );
OAI2BB2XLTS U5702 ( .B0(n4777), .B1(n5306), .A0N(n4863), .A1N(
FPSENCOS_d_ff_Xn[6]), .Y(n2054) );
AO22XLTS U5703 ( .A0(n4775), .A1(result_add_subt[7]), .B0(n4778), .B1(
FPSENCOS_d_ff_Zn[7]), .Y(n2053) );
OAI2BB2XLTS U5704 ( .B0(n4871), .B1(n5309), .A0N(n4793), .A1N(
FPSENCOS_d_ff_Yn[7]), .Y(n2052) );
OAI2BB2XLTS U5705 ( .B0(n4880), .B1(n5309), .A0N(n4863), .A1N(
FPSENCOS_d_ff_Xn[7]), .Y(n2051) );
AO22XLTS U5706 ( .A0(n4775), .A1(result_add_subt[8]), .B0(n4866), .B1(
FPSENCOS_d_ff_Zn[8]), .Y(n2050) );
OAI2BB2XLTS U5707 ( .B0(n4776), .B1(n5295), .A0N(n4776), .A1N(
FPSENCOS_d_ff_Yn[8]), .Y(n2049) );
OAI2BB2XLTS U5708 ( .B0(n4777), .B1(n5295), .A0N(n4777), .A1N(
FPSENCOS_d_ff_Xn[8]), .Y(n2048) );
AO22XLTS U5709 ( .A0(n4867), .A1(result_add_subt[9]), .B0(n4778), .B1(
FPSENCOS_d_ff_Zn[9]), .Y(n2047) );
OAI2BB2XLTS U5710 ( .B0(n4871), .B1(n5299), .A0N(n4793), .A1N(
FPSENCOS_d_ff_Yn[9]), .Y(n2046) );
OAI2BB2XLTS U5711 ( .B0(n4880), .B1(n5299), .A0N(n4863), .A1N(
FPSENCOS_d_ff_Xn[9]), .Y(n2045) );
AO22XLTS U5712 ( .A0(n4775), .A1(result_add_subt[10]), .B0(n4866), .B1(
FPSENCOS_d_ff_Zn[10]), .Y(n2044) );
OAI2BB2XLTS U5713 ( .B0(n4871), .B1(n5297), .A0N(n4776), .A1N(
FPSENCOS_d_ff_Yn[10]), .Y(n2043) );
OAI2BB2XLTS U5714 ( .B0(n4880), .B1(n5297), .A0N(n4777), .A1N(
FPSENCOS_d_ff_Xn[10]), .Y(n2042) );
AO22XLTS U5715 ( .A0(n4775), .A1(result_add_subt[11]), .B0(n4778), .B1(
FPSENCOS_d_ff_Zn[11]), .Y(n2041) );
OAI2BB2XLTS U5716 ( .B0(n4871), .B1(n5296), .A0N(n4776), .A1N(
FPSENCOS_d_ff_Yn[11]), .Y(n2040) );
OAI2BB2XLTS U5717 ( .B0(n4880), .B1(n5296), .A0N(n4777), .A1N(
FPSENCOS_d_ff_Xn[11]), .Y(n2039) );
AO22XLTS U5718 ( .A0(n4867), .A1(result_add_subt[12]), .B0(n4778), .B1(
FPSENCOS_d_ff_Zn[12]), .Y(n2038) );
OAI2BB2XLTS U5719 ( .B0(n4871), .B1(n5298), .A0N(n4793), .A1N(
FPSENCOS_d_ff_Yn[12]), .Y(n2037) );
OAI2BB2XLTS U5720 ( .B0(n4880), .B1(n5298), .A0N(n4863), .A1N(
FPSENCOS_d_ff_Xn[12]), .Y(n2036) );
INVX2TS U5721 ( .A(n4779), .Y(n4864) );
AO22XLTS U5722 ( .A0(n4864), .A1(result_add_subt[13]), .B0(n4778), .B1(
FPSENCOS_d_ff_Zn[13]), .Y(n2035) );
OAI2BB2XLTS U5723 ( .B0(n4871), .B1(n5294), .A0N(n4776), .A1N(n2311), .Y(
n2034) );
OAI2BB2XLTS U5724 ( .B0(n4880), .B1(n5294), .A0N(n4777), .A1N(
FPSENCOS_d_ff_Xn[13]), .Y(n2033) );
AO22XLTS U5725 ( .A0(n4864), .A1(result_add_subt[14]), .B0(n4778), .B1(
FPSENCOS_d_ff_Zn[14]), .Y(n2032) );
OAI2BB2XLTS U5726 ( .B0(n4871), .B1(n5308), .A0N(n4776), .A1N(n2310), .Y(
n2031) );
OAI2BB2XLTS U5727 ( .B0(n4880), .B1(n5308), .A0N(n4777), .A1N(
FPSENCOS_d_ff_Xn[14]), .Y(n2030) );
AO22XLTS U5728 ( .A0(n4864), .A1(result_add_subt[15]), .B0(n4778), .B1(
FPSENCOS_d_ff_Zn[15]), .Y(n2029) );
OAI2BB2XLTS U5729 ( .B0(n4871), .B1(n5301), .A0N(n4793), .A1N(
FPSENCOS_d_ff_Yn[15]), .Y(n2028) );
OAI2BB2XLTS U5730 ( .B0(n4880), .B1(n5301), .A0N(n4863), .A1N(
FPSENCOS_d_ff_Xn[15]), .Y(n2027) );
AO22XLTS U5731 ( .A0(n4864), .A1(result_add_subt[16]), .B0(n4778), .B1(
FPSENCOS_d_ff_Zn[16]), .Y(n2026) );
OAI2BB2XLTS U5732 ( .B0(n4871), .B1(n5307), .A0N(n4793), .A1N(
FPSENCOS_d_ff_Yn[16]), .Y(n2025) );
OAI2BB2XLTS U5733 ( .B0(n4880), .B1(n5307), .A0N(n4863), .A1N(
FPSENCOS_d_ff_Xn[16]), .Y(n2024) );
CLKBUFX3TS U5734 ( .A(n4778), .Y(n4866) );
AO22XLTS U5735 ( .A0(n4864), .A1(result_add_subt[17]), .B0(n4779), .B1(
FPSENCOS_d_ff_Zn[17]), .Y(n2023) );
OAI2BB2XLTS U5736 ( .B0(n4871), .B1(n5305), .A0N(n4793), .A1N(n2312), .Y(
n2022) );
OAI2BB2XLTS U5737 ( .B0(n4880), .B1(n5305), .A0N(n4863), .A1N(
FPSENCOS_d_ff_Xn[17]), .Y(n2021) );
AO22XLTS U5738 ( .A0(n4864), .A1(result_add_subt[18]), .B0(n4778), .B1(
FPSENCOS_d_ff_Zn[18]), .Y(n2020) );
OAI2BB2XLTS U5739 ( .B0(n4871), .B1(n5302), .A0N(n4793), .A1N(
FPSENCOS_d_ff_Yn[18]), .Y(n2019) );
OAI2BB2XLTS U5740 ( .B0(n4880), .B1(n5302), .A0N(n4863), .A1N(
FPSENCOS_d_ff_Xn[18]), .Y(n2018) );
AO22XLTS U5741 ( .A0(n4864), .A1(result_add_subt[19]), .B0(n4866), .B1(
FPSENCOS_d_ff_Zn[19]), .Y(n2017) );
OAI2BB2XLTS U5742 ( .B0(n4865), .B1(n5303), .A0N(n4793), .A1N(n2314), .Y(
n2016) );
OAI2BB2XLTS U5743 ( .B0(n4872), .B1(n5303), .A0N(n4863), .A1N(
FPSENCOS_d_ff_Xn[19]), .Y(n2015) );
AO22XLTS U5744 ( .A0(n4864), .A1(result_add_subt[20]), .B0(n4866), .B1(
FPSENCOS_d_ff_Zn[20]), .Y(n2014) );
OAI2BB2XLTS U5745 ( .B0(n4865), .B1(n5304), .A0N(n4793), .A1N(n2313), .Y(
n2013) );
OAI2BB2XLTS U5746 ( .B0(n4872), .B1(n5304), .A0N(n4863), .A1N(
FPSENCOS_d_ff_Xn[20]), .Y(n2012) );
AO22XLTS U5747 ( .A0(n4864), .A1(result_add_subt[21]), .B0(n4778), .B1(
FPSENCOS_d_ff_Zn[21]), .Y(n2011) );
OAI2BB2XLTS U5748 ( .B0(n4865), .B1(n5199), .A0N(n4870), .A1N(
FPSENCOS_d_ff_Yn[21]), .Y(n2010) );
OAI2BB2XLTS U5749 ( .B0(n4872), .B1(n5199), .A0N(n4879), .A1N(
FPSENCOS_d_ff_Xn[21]), .Y(n2009) );
AO22XLTS U5750 ( .A0(n4867), .A1(result_add_subt[22]), .B0(n4779), .B1(
FPSENCOS_d_ff_Zn[22]), .Y(n2008) );
OAI2BB2XLTS U5751 ( .B0(n4865), .B1(n5300), .A0N(n4793), .A1N(
FPSENCOS_d_ff_Yn[22]), .Y(n2007) );
OAI2BB2XLTS U5752 ( .B0(n4872), .B1(n5300), .A0N(n4863), .A1N(
FPSENCOS_d_ff_Xn[22]), .Y(n2006) );
BUFX3TS U5753 ( .A(n4787), .Y(n4808) );
OA22X1TS U5754 ( .A0(FPSENCOS_d_ff_Xn[1]), .A1(n3790), .B0(n2330), .B1(n2292), .Y(n2003) );
OA22X1TS U5755 ( .A0(FPSENCOS_d_ff_Xn[2]), .A1(n4783), .B0(n2331), .B1(n2292), .Y(n2001) );
OA22X1TS U5756 ( .A0(FPSENCOS_d_ff_Xn[3]), .A1(n4783), .B0(n2343), .B1(n2291), .Y(n1999) );
BUFX3TS U5757 ( .A(n4780), .Y(n4794) );
OA22X1TS U5758 ( .A0(FPSENCOS_d_ff_Xn[5]), .A1(n4783), .B0(n2342), .B1(n2292), .Y(n1995) );
OA22X1TS U5759 ( .A0(FPSENCOS_d_ff_Xn[6]), .A1(n4783), .B0(n2334), .B1(n2291), .Y(n1993) );
OA22X1TS U5760 ( .A0(FPSENCOS_d_ff_Xn[7]), .A1(n4783), .B0(n2337), .B1(n2292), .Y(n1991) );
AO22XLTS U5761 ( .A0(n4787), .A1(n2337), .B0(n4782), .B1(
FPSENCOS_d_ff3_sh_x_out[7]), .Y(n1990) );
OA22X1TS U5762 ( .A0(FPSENCOS_d_ff_Xn[10]), .A1(n4783), .B0(n2333), .B1(
n2291), .Y(n1985) );
AO22XLTS U5763 ( .A0(n4787), .A1(n2336), .B0(n4782), .B1(
FPSENCOS_d_ff3_sh_x_out[11]), .Y(n1982) );
OA22X1TS U5764 ( .A0(FPSENCOS_d_ff_Xn[12]), .A1(n4783), .B0(n2332), .B1(
n2292), .Y(n1981) );
OA22X1TS U5765 ( .A0(FPSENCOS_d_ff_Xn[13]), .A1(n4783), .B0(n2338), .B1(
n2291), .Y(n1979) );
AO22XLTS U5766 ( .A0(n4787), .A1(n2338), .B0(n4782), .B1(
FPSENCOS_d_ff3_sh_x_out[13]), .Y(n1978) );
OA22X1TS U5767 ( .A0(FPSENCOS_d_ff_Xn[14]), .A1(n4783), .B0(n2344), .B1(
n2292), .Y(n1977) );
AO22XLTS U5768 ( .A0(n4787), .A1(FPSENCOS_d_ff2_X[15]), .B0(n4782), .B1(
FPSENCOS_d_ff3_sh_x_out[15]), .Y(n1974) );
OA22X1TS U5769 ( .A0(FPSENCOS_d_ff_Xn[16]), .A1(n3790), .B0(
FPSENCOS_d_ff2_X[16]), .B1(n2290), .Y(n1973) );
AO22XLTS U5770 ( .A0(n4787), .A1(FPSENCOS_d_ff2_X[16]), .B0(n4782), .B1(
FPSENCOS_d_ff3_sh_x_out[16]), .Y(n1972) );
OA22X1TS U5771 ( .A0(FPSENCOS_d_ff_Xn[17]), .A1(n3790), .B0(n2339), .B1(
n2291), .Y(n1971) );
AO22XLTS U5772 ( .A0(n4787), .A1(n2339), .B0(n4782), .B1(
FPSENCOS_d_ff3_sh_x_out[17]), .Y(n1970) );
AO22XLTS U5773 ( .A0(n4787), .A1(FPSENCOS_d_ff2_X[18]), .B0(n4782), .B1(
FPSENCOS_d_ff3_sh_x_out[18]), .Y(n1968) );
OA22X1TS U5774 ( .A0(FPSENCOS_d_ff_Xn[19]), .A1(n3790), .B0(n2341), .B1(
n2292), .Y(n1967) );
AO22XLTS U5775 ( .A0(n4869), .A1(n2341), .B0(n4868), .B1(
FPSENCOS_d_ff3_sh_x_out[19]), .Y(n1966) );
OA22X1TS U5776 ( .A0(FPSENCOS_d_ff_Xn[20]), .A1(n3790), .B0(n2340), .B1(
n2291), .Y(n1965) );
AO22XLTS U5777 ( .A0(n4869), .A1(n2340), .B0(n4868), .B1(
FPSENCOS_d_ff3_sh_x_out[20]), .Y(n1964) );
AO22XLTS U5778 ( .A0(n4869), .A1(FPSENCOS_d_ff2_X[22]), .B0(n4868), .B1(
FPSENCOS_d_ff3_sh_x_out[22]), .Y(n1960) );
OA22X1TS U5779 ( .A0(FPSENCOS_d_ff_Xn[24]), .A1(n3790), .B0(
FPSENCOS_d_ff2_X[24]), .B1(n2291), .Y(n1958) );
OA22X1TS U5780 ( .A0(n2318), .A1(n3790), .B0(FPSENCOS_d_ff2_X[25]), .B1(
n2292), .Y(n1957) );
OA22X1TS U5781 ( .A0(n2317), .A1(n3790), .B0(FPSENCOS_d_ff2_X[26]), .B1(
n2291), .Y(n1956) );
OA22X1TS U5782 ( .A0(FPSENCOS_d_ff_Xn[27]), .A1(n4783), .B0(
FPSENCOS_d_ff2_X[27]), .B1(n2292), .Y(n1955) );
OA22X1TS U5783 ( .A0(FPSENCOS_d_ff2_X[28]), .A1(n2291), .B0(
FPSENCOS_d_ff_Xn[28]), .B1(n4783), .Y(n1954) );
OA22X1TS U5784 ( .A0(FPSENCOS_d_ff_Xn[29]), .A1(n4783), .B0(
FPSENCOS_d_ff2_X[29]), .B1(n2291), .Y(n1953) );
NAND2X1TS U5785 ( .A(FPSENCOS_d_ff2_X[23]), .B(n5191), .Y(n4786) );
AOI32X1TS U5786 ( .A0(intadd_525_CI), .A1(n4869), .A2(n4786), .B0(n4785),
.B1(n4784), .Y(n1951) );
AOI21X1TS U5787 ( .A0(intadd_525_n1), .A1(FPSENCOS_d_ff2_X[27]), .B0(n4788),
.Y(n4789) );
AOI21X1TS U5788 ( .A0(FPSENCOS_d_ff2_X[29]), .A1(n4791), .B0(n4790), .Y(
n4792) );
AO22XLTS U5789 ( .A0(n4787), .A1(n2335), .B0(n4868), .B1(
FPSENCOS_d_ff3_sh_x_out[31]), .Y(n1942) );
AO22XLTS U5790 ( .A0(n4775), .A1(result_add_subt[31]), .B0(n4866), .B1(
FPSENCOS_d_ff_Zn[31]), .Y(n1909) );
OAI2BB2XLTS U5791 ( .B0(n4865), .B1(n5227), .A0N(n4793), .A1N(n2321), .Y(
n1908) );
BUFX3TS U5792 ( .A(n4801), .Y(n4798) );
AO22XLTS U5793 ( .A0(n4805), .A1(FPSENCOS_d_ff2_Y[3]), .B0(n4868), .B1(
FPSENCOS_d_ff3_sh_y_out[3]), .Y(n1900) );
AO22XLTS U5794 ( .A0(n4796), .A1(FPSENCOS_d_ff2_Y[5]), .B0(n4868), .B1(
FPSENCOS_d_ff3_sh_y_out[5]), .Y(n1896) );
AO22XLTS U5795 ( .A0(n4796), .A1(FPSENCOS_d_ff2_Y[7]), .B0(n4799), .B1(
FPSENCOS_d_ff3_sh_y_out[7]), .Y(n1892) );
AO22XLTS U5796 ( .A0(n4796), .A1(FPSENCOS_d_ff2_Y[9]), .B0(n4799), .B1(
FPSENCOS_d_ff3_sh_y_out[9]), .Y(n1888) );
AO22XLTS U5797 ( .A0(n4796), .A1(FPSENCOS_d_ff2_Y[10]), .B0(n4799), .B1(
FPSENCOS_d_ff3_sh_y_out[10]), .Y(n1886) );
AO22XLTS U5798 ( .A0(n4796), .A1(FPSENCOS_d_ff2_Y[11]), .B0(n4799), .B1(
FPSENCOS_d_ff3_sh_y_out[11]), .Y(n1884) );
AO22XLTS U5799 ( .A0(n4796), .A1(FPSENCOS_d_ff2_Y[12]), .B0(n4799), .B1(
FPSENCOS_d_ff3_sh_y_out[12]), .Y(n1882) );
AO22XLTS U5800 ( .A0(n4796), .A1(FPSENCOS_d_ff2_Y[13]), .B0(n4799), .B1(
FPSENCOS_d_ff3_sh_y_out[13]), .Y(n1880) );
AO22XLTS U5801 ( .A0(n4869), .A1(FPSENCOS_d_ff2_Y[14]), .B0(n4799), .B1(
FPSENCOS_d_ff3_sh_y_out[14]), .Y(n1878) );
AO22XLTS U5802 ( .A0(n4805), .A1(FPSENCOS_d_ff2_Y[15]), .B0(n4799), .B1(
FPSENCOS_d_ff3_sh_y_out[15]), .Y(n1876) );
AO22XLTS U5803 ( .A0(n4805), .A1(FPSENCOS_d_ff2_Y[16]), .B0(n4799), .B1(
FPSENCOS_d_ff3_sh_y_out[16]), .Y(n1874) );
AO22XLTS U5804 ( .A0(n4869), .A1(FPSENCOS_d_ff2_Y[17]), .B0(n4799), .B1(
FPSENCOS_d_ff3_sh_y_out[17]), .Y(n1872) );
AO22XLTS U5805 ( .A0(n4805), .A1(FPSENCOS_d_ff2_Y[18]), .B0(n4812), .B1(
FPSENCOS_d_ff3_sh_y_out[18]), .Y(n1870) );
AO22XLTS U5806 ( .A0(n4805), .A1(FPSENCOS_d_ff2_Y[19]), .B0(n4799), .B1(
FPSENCOS_d_ff3_sh_y_out[19]), .Y(n1868) );
AO22XLTS U5807 ( .A0(n4869), .A1(FPSENCOS_d_ff2_Y[20]), .B0(n4812), .B1(
FPSENCOS_d_ff3_sh_y_out[20]), .Y(n1866) );
AO22XLTS U5808 ( .A0(n4805), .A1(FPSENCOS_d_ff2_Y[21]), .B0(n4812), .B1(
FPSENCOS_d_ff3_sh_y_out[21]), .Y(n1864) );
AO22XLTS U5809 ( .A0(n4869), .A1(FPSENCOS_d_ff2_Y[22]), .B0(n4812), .B1(
FPSENCOS_d_ff3_sh_y_out[22]), .Y(n1862) );
AOI21X1TS U5810 ( .A0(intadd_524_n1), .A1(FPSENCOS_d_ff2_Y[27]), .B0(n4802),
.Y(n4804) );
AOI21X1TS U5811 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n4807), .B0(n4806), .Y(
n4809) );
AO22XLTS U5812 ( .A0(n4869), .A1(FPSENCOS_d_ff2_Y[31]), .B0(n4812), .B1(
FPSENCOS_d_ff3_sh_y_out[31]), .Y(n1844) );
AOI22X1TS U5813 ( .A0(Data_2[3]), .A1(n4815), .B0(FPADDSUB_intDY_EWSW[3]),
.B1(n4873), .Y(n4814) );
AOI22X1TS U5814 ( .A0(n4876), .A1(FPSENCOS_d_ff3_sh_x_out[3]), .B0(n4826),
.B1(FPSENCOS_d_ff3_sh_y_out[3]), .Y(n4813) );
NAND2X1TS U5815 ( .A(n4851), .B(FPSENCOS_d_ff3_LUT_out[3]), .Y(n4833) );
AOI22X1TS U5816 ( .A0(Data_2[5]), .A1(n4815), .B0(FPADDSUB_intDY_EWSW[5]),
.B1(n4818), .Y(n4817) );
AOI22X1TS U5817 ( .A0(n4876), .A1(FPSENCOS_d_ff3_sh_x_out[5]), .B0(n4826),
.B1(FPSENCOS_d_ff3_sh_y_out[5]), .Y(n4816) );
NAND2X1TS U5818 ( .A(FPSENCOS_d_ff3_LUT_out[5]), .B(n4851), .Y(n4827) );
AOI22X1TS U5819 ( .A0(Data_2[7]), .A1(n4304), .B0(FPADDSUB_intDY_EWSW[7]),
.B1(n4873), .Y(n4820) );
AOI22X1TS U5820 ( .A0(n4876), .A1(FPSENCOS_d_ff3_sh_x_out[7]), .B0(n4826),
.B1(FPSENCOS_d_ff3_sh_y_out[7]), .Y(n4819) );
NAND2X1TS U5821 ( .A(n4851), .B(FPSENCOS_d_ff3_LUT_out[7]), .Y(n4821) );
AOI22X1TS U5822 ( .A0(Data_2[11]), .A1(n4841), .B0(FPADDSUB_intDY_EWSW[11]),
.B1(n4873), .Y(n4823) );
AOI22X1TS U5823 ( .A0(n4876), .A1(FPSENCOS_d_ff3_sh_x_out[11]), .B0(n4826),
.B1(FPSENCOS_d_ff3_sh_y_out[11]), .Y(n4822) );
AOI22X1TS U5824 ( .A0(Data_2[13]), .A1(n4841), .B0(FPADDSUB_intDY_EWSW[13]),
.B1(n4818), .Y(n4825) );
AOI22X1TS U5825 ( .A0(n4876), .A1(FPSENCOS_d_ff3_sh_x_out[13]), .B0(n4826),
.B1(FPSENCOS_d_ff3_sh_y_out[13]), .Y(n4824) );
NAND2X1TS U5826 ( .A(n4851), .B(FPSENCOS_d_ff3_LUT_out[13]), .Y(n4838) );
AOI22X1TS U5827 ( .A0(Data_2[14]), .A1(n4841), .B0(FPADDSUB_intDY_EWSW[14]),
.B1(n4873), .Y(n4829) );
AOI22X1TS U5828 ( .A0(n4876), .A1(FPSENCOS_d_ff3_sh_x_out[14]), .B0(n4826),
.B1(FPSENCOS_d_ff3_sh_y_out[14]), .Y(n4828) );
AOI22X1TS U5829 ( .A0(Data_2[15]), .A1(n4841), .B0(FPADDSUB_intDY_EWSW[15]),
.B1(n4818), .Y(n4832) );
AOI22X1TS U5830 ( .A0(n2297), .A1(FPSENCOS_d_ff3_sh_x_out[15]), .B0(n4830),
.B1(FPSENCOS_d_ff3_sh_y_out[15]), .Y(n4831) );
NAND2X1TS U5831 ( .A(n4851), .B(FPSENCOS_d_ff3_LUT_out[15]), .Y(n4845) );
AOI22X1TS U5832 ( .A0(Data_2[16]), .A1(n4841), .B0(FPADDSUB_intDY_EWSW[16]),
.B1(n4818), .Y(n4835) );
AOI22X1TS U5833 ( .A0(n4876), .A1(FPSENCOS_d_ff3_sh_x_out[16]), .B0(n4830),
.B1(FPSENCOS_d_ff3_sh_y_out[16]), .Y(n4834) );
AOI22X1TS U5834 ( .A0(Data_2[17]), .A1(n4304), .B0(FPADDSUB_intDY_EWSW[17]),
.B1(n4873), .Y(n4837) );
AOI22X1TS U5835 ( .A0(n2297), .A1(FPSENCOS_d_ff3_sh_x_out[17]), .B0(n4830),
.B1(FPSENCOS_d_ff3_sh_y_out[17]), .Y(n4836) );
AOI22X1TS U5836 ( .A0(Data_2[18]), .A1(n4841), .B0(FPADDSUB_intDY_EWSW[18]),
.B1(n4818), .Y(n4840) );
AOI22X1TS U5837 ( .A0(n4876), .A1(FPSENCOS_d_ff3_sh_x_out[18]), .B0(n4830),
.B1(FPSENCOS_d_ff3_sh_y_out[18]), .Y(n4839) );
AOI22X1TS U5838 ( .A0(Data_2[19]), .A1(n4304), .B0(FPADDSUB_intDY_EWSW[19]),
.B1(n4873), .Y(n4843) );
AOI22X1TS U5839 ( .A0(n4144), .A1(FPSENCOS_d_ff3_sh_x_out[19]), .B0(n4830),
.B1(FPSENCOS_d_ff3_sh_y_out[19]), .Y(n4842) );
NAND2X1TS U5840 ( .A(n4851), .B(FPSENCOS_d_ff3_LUT_out[19]), .Y(n4848) );
AOI22X1TS U5841 ( .A0(Data_2[20]), .A1(n4841), .B0(FPADDSUB_intDY_EWSW[20]),
.B1(n4818), .Y(n4847) );
AOI22X1TS U5842 ( .A0(n2297), .A1(FPSENCOS_d_ff3_sh_x_out[20]), .B0(n4830),
.B1(FPSENCOS_d_ff3_sh_y_out[20]), .Y(n4846) );
AOI22X1TS U5843 ( .A0(Data_2[22]), .A1(n4304), .B0(FPADDSUB_intDY_EWSW[22]),
.B1(n4873), .Y(n4850) );
AOI22X1TS U5844 ( .A0(n4876), .A1(FPSENCOS_d_ff3_sh_x_out[22]), .B0(n4830),
.B1(FPSENCOS_d_ff3_sh_y_out[22]), .Y(n4849) );
AOI22X1TS U5845 ( .A0(Data_2[27]), .A1(n4841), .B0(FPADDSUB_intDY_EWSW[27]),
.B1(n4873), .Y(n4853) );
AOI22X1TS U5846 ( .A0(n4876), .A1(FPSENCOS_d_ff3_sh_x_out[27]), .B0(n4830),
.B1(FPSENCOS_d_ff3_sh_y_out[27]), .Y(n4852) );
NAND2X1TS U5847 ( .A(n4851), .B(FPSENCOS_d_ff3_LUT_out[27]), .Y(n4856) );
AOI22X1TS U5848 ( .A0(Data_2[28]), .A1(n4841), .B0(FPADDSUB_intDY_EWSW[28]),
.B1(n4818), .Y(n4855) );
AOI22X1TS U5849 ( .A0(n4876), .A1(FPSENCOS_d_ff3_sh_x_out[28]), .B0(n4830),
.B1(FPSENCOS_d_ff3_sh_y_out[28]), .Y(n4854) );
AOI22X1TS U5850 ( .A0(Data_2[29]), .A1(n4841), .B0(FPADDSUB_intDY_EWSW[29]),
.B1(n4818), .Y(n4858) );
AOI22X1TS U5851 ( .A0(n4876), .A1(FPSENCOS_d_ff3_sh_x_out[29]), .B0(n4830),
.B1(FPSENCOS_d_ff3_sh_y_out[29]), .Y(n4857) );
AOI22X1TS U5852 ( .A0(Data_2[30]), .A1(n4841), .B0(FPADDSUB_intDY_EWSW[30]),
.B1(n4873), .Y(n4860) );
AOI22X1TS U5853 ( .A0(n4876), .A1(FPSENCOS_d_ff3_sh_x_out[30]), .B0(n4830),
.B1(FPSENCOS_d_ff3_sh_y_out[30]), .Y(n4859) );
NAND2X1TS U5854 ( .A(n4860), .B(n4859), .Y(n1813) );
OAI22X1TS U5855 ( .A0(n4862), .A1(n4861), .B0(n3536), .B1(n5333), .Y(n1812)
);
AO22XLTS U5856 ( .A0(n4867), .A1(result_add_subt[23]), .B0(n4779), .B1(
FPSENCOS_d_ff_Zn[23]), .Y(n1786) );
OAI2BB2XLTS U5857 ( .B0(n4865), .B1(n5208), .A0N(n4870), .A1N(
FPSENCOS_d_ff_Yn[23]), .Y(n1785) );
OAI2BB2XLTS U5858 ( .B0(n4872), .B1(n5208), .A0N(n4863), .A1N(
FPSENCOS_d_ff_Xn[23]), .Y(n1784) );
AO22XLTS U5859 ( .A0(n4775), .A1(result_add_subt[24]), .B0(n4779), .B1(
FPSENCOS_d_ff_Zn[24]), .Y(n1783) );
OAI2BB2XLTS U5860 ( .B0(n4865), .B1(n5209), .A0N(n4870), .A1N(
FPSENCOS_d_ff_Yn[24]), .Y(n1782) );
OAI2BB2XLTS U5861 ( .B0(n4872), .B1(n5209), .A0N(n4879), .A1N(
FPSENCOS_d_ff_Xn[24]), .Y(n1781) );
AO22XLTS U5862 ( .A0(n4775), .A1(result_add_subt[25]), .B0(n4779), .B1(
FPSENCOS_d_ff_Zn[25]), .Y(n1780) );
OAI2BB2XLTS U5863 ( .B0(n4865), .B1(n5210), .A0N(n4870), .A1N(
FPSENCOS_d_ff_Yn[25]), .Y(n1779) );
OAI2BB2XLTS U5864 ( .B0(n4872), .B1(n5210), .A0N(n4879), .A1N(n2318), .Y(
n1778) );
INVX2TS U5865 ( .A(n4779), .Y(n4867) );
AO22XLTS U5866 ( .A0(n4867), .A1(result_add_subt[26]), .B0(n4779), .B1(
FPSENCOS_d_ff_Zn[26]), .Y(n1777) );
OAI2BB2XLTS U5867 ( .B0(n4865), .B1(n5211), .A0N(n4870), .A1N(
FPSENCOS_d_ff_Yn[26]), .Y(n1776) );
OAI2BB2XLTS U5868 ( .B0(n4872), .B1(n5211), .A0N(n4879), .A1N(n2317), .Y(
n1775) );
AO22XLTS U5869 ( .A0(n4775), .A1(result_add_subt[27]), .B0(n4779), .B1(
FPSENCOS_d_ff_Zn[27]), .Y(n1774) );
OAI2BB2XLTS U5870 ( .B0(n4865), .B1(n5212), .A0N(n4870), .A1N(n2315), .Y(
n1773) );
OAI2BB2XLTS U5871 ( .B0(n4872), .B1(n5212), .A0N(n4879), .A1N(
FPSENCOS_d_ff_Xn[27]), .Y(n1772) );
AO22XLTS U5872 ( .A0(n4775), .A1(result_add_subt[28]), .B0(n4779), .B1(
FPSENCOS_d_ff_Zn[28]), .Y(n1771) );
OAI2BB2XLTS U5873 ( .B0(n4865), .B1(n5213), .A0N(n4870), .A1N(
FPSENCOS_d_ff_Yn[28]), .Y(n1770) );
OAI2BB2XLTS U5874 ( .B0(n4872), .B1(n5213), .A0N(n4879), .A1N(
FPSENCOS_d_ff_Xn[28]), .Y(n1769) );
AO22XLTS U5875 ( .A0(n4867), .A1(result_add_subt[29]), .B0(n4866), .B1(
FPSENCOS_d_ff_Zn[29]), .Y(n1768) );
OAI2BB2XLTS U5876 ( .B0(n4865), .B1(n5228), .A0N(n4870), .A1N(
FPSENCOS_d_ff_Yn[29]), .Y(n1767) );
OAI2BB2XLTS U5877 ( .B0(n4872), .B1(n5228), .A0N(n4879), .A1N(
FPSENCOS_d_ff_Xn[29]), .Y(n1766) );
AO22XLTS U5878 ( .A0(n4775), .A1(result_add_subt[30]), .B0(n4779), .B1(
FPSENCOS_d_ff_Zn[30]), .Y(n1765) );
AO22XLTS U5879 ( .A0(n4787), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n4868), .B1(
n2305), .Y(n1732) );
OAI2BB2XLTS U5880 ( .B0(n4871), .B1(n5214), .A0N(n4870), .A1N(
FPSENCOS_d_ff_Yn[30]), .Y(n1730) );
OAI2BB2XLTS U5881 ( .B0(n4872), .B1(n5214), .A0N(n4879), .A1N(
FPSENCOS_d_ff_Xn[30]), .Y(n1729) );
AOI22X1TS U5882 ( .A0(Data_2[31]), .A1(n4304), .B0(FPADDSUB_intDY_EWSW[31]),
.B1(n4818), .Y(n4878) );
AOI22X1TS U5883 ( .A0(n4876), .A1(FPSENCOS_d_ff3_sh_x_out[31]), .B0(n4830),
.B1(FPSENCOS_d_ff3_sh_y_out[31]), .Y(n4877) );
NAND2X1TS U5884 ( .A(n4878), .B(n4877), .Y(n1728) );
OAI2BB2XLTS U5885 ( .B0(n4880), .B1(n5227), .A0N(n4879), .A1N(n2329), .Y(
n1727) );
AOI22X1TS U5886 ( .A0(n4882), .A1(n2329), .B0(n2321), .B1(n4881), .Y(n4884)
);
XOR2XLTS U5887 ( .A(n4884), .B(n4883), .Y(n4885) );
OAI2BB2XLTS U5888 ( .B0(n4886), .B1(n4885), .A0N(n4886), .A1N(
cordic_result[31]), .Y(n1695) );
AOI2BB2XLTS U5889 ( .B0(n5437), .B1(n5408), .A0N(FPMULT_P_Sgf[47]), .A1N(
n4887), .Y(n4891) );
AOI21X1TS U5890 ( .A0(begin_operation), .A1(n4888), .B0(n5514), .Y(n4889) );
AOI21X1TS U5891 ( .A0(n4891), .A1(n4890), .B0(n4889), .Y(n1692) );
INVX2TS U5892 ( .A(n4892), .Y(n4893) );
OAI22X1TS U5893 ( .A0(n4894), .A1(n4893), .B0(n5195), .B1(n5175), .Y(n4895)
);
OA22X1TS U5894 ( .A0(FPMULT_Op_MX[22]), .A1(n4899), .B0(n4897), .B1(
Data_1[22]), .Y(n1680) );
OA22X1TS U5895 ( .A0(DP_OP_501J224_127_5235_n411), .A1(n4529), .B0(n4898),
.B1(Data_1[21]), .Y(n1679) );
OA22X1TS U5896 ( .A0(FPMULT_Op_MX[20]), .A1(n4529), .B0(n4898), .B1(
Data_1[20]), .Y(n1678) );
OA22X1TS U5897 ( .A0(n2197), .A1(n4420), .B0(n4900), .B1(Data_1[19]), .Y(
n1677) );
OA22X1TS U5898 ( .A0(FPMULT_Op_MX[18]), .A1(n4529), .B0(n4898), .B1(
Data_1[18]), .Y(n1676) );
OA22X1TS U5899 ( .A0(FPMULT_Op_MX[17]), .A1(n4420), .B0(n4898), .B1(
Data_1[17]), .Y(n1675) );
OA22X1TS U5900 ( .A0(FPMULT_Op_MX[16]), .A1(n4529), .B0(n4898), .B1(
Data_1[16]), .Y(n1674) );
OA22X1TS U5901 ( .A0(FPMULT_Op_MX[15]), .A1(n4899), .B0(n4898), .B1(
Data_1[15]), .Y(n1673) );
OA22X1TS U5902 ( .A0(FPMULT_Op_MX[14]), .A1(n4420), .B0(n4898), .B1(
Data_1[14]), .Y(n1672) );
OA22X1TS U5903 ( .A0(FPMULT_Op_MX[13]), .A1(n4529), .B0(n4898), .B1(
Data_1[13]), .Y(n1671) );
OA22X1TS U5904 ( .A0(FPMULT_Op_MX[12]), .A1(n4420), .B0(n4898), .B1(
Data_1[12]), .Y(n1670) );
AO22XLTS U5905 ( .A0(n4942), .A1(Data_1[31]), .B0(n4419), .B1(
FPMULT_Op_MX[31]), .Y(n1657) );
AO22XLTS U5906 ( .A0(n4900), .A1(FPMULT_Op_MY[22]), .B0(n4942), .B1(
Data_2[22]), .Y(n1648) );
AO22XLTS U5907 ( .A0(n4900), .A1(FPMULT_Op_MY[21]), .B0(n4942), .B1(
Data_2[21]), .Y(n1647) );
AO22XLTS U5908 ( .A0(n4900), .A1(n4930), .B0(n4942), .B1(Data_2[20]), .Y(
n1646) );
AO22XLTS U5909 ( .A0(n4900), .A1(FPMULT_Op_MY[19]), .B0(n4942), .B1(
Data_2[19]), .Y(n1645) );
AO22XLTS U5910 ( .A0(n4900), .A1(FPMULT_Op_MY[18]), .B0(n4942), .B1(
Data_2[18]), .Y(n1644) );
AO22XLTS U5911 ( .A0(n4900), .A1(FPMULT_Op_MY[17]), .B0(n4942), .B1(
Data_2[17]), .Y(n1643) );
AO22XLTS U5912 ( .A0(n4900), .A1(FPMULT_Op_MY[16]), .B0(n4942), .B1(
Data_2[16]), .Y(n1642) );
AO22XLTS U5913 ( .A0(n4900), .A1(FPMULT_Op_MY[14]), .B0(n4942), .B1(
Data_2[14]), .Y(n1640) );
AO22XLTS U5914 ( .A0(n4900), .A1(n2198), .B0(n4942), .B1(Data_2[13]), .Y(
n1639) );
AO22XLTS U5915 ( .A0(n4419), .A1(FPMULT_Op_MY[12]), .B0(n4942), .B1(
Data_2[12]), .Y(n1638) );
NOR4X1TS U5916 ( .A(n4902), .B(n4901), .C(FPMULT_Op_MX[0]), .D(
FPMULT_Op_MX[1]), .Y(n4912) );
NOR4X1TS U5917 ( .A(FPMULT_Op_MX[6]), .B(FPMULT_Op_MX[7]), .C(n4904), .D(
n2196), .Y(n4911) );
NOR4X1TS U5918 ( .A(DP_OP_501J224_127_5235_n411), .B(FPMULT_Op_MX[18]), .C(
FPMULT_Op_MX[22]), .D(n2197), .Y(n4910) );
NOR4X1TS U5919 ( .A(n4908), .B(n4907), .C(n4906), .D(FPMULT_Op_MX[5]), .Y(
n4909) );
NAND4XLTS U5920 ( .A(n4912), .B(n4911), .C(n4910), .D(n4909), .Y(n4939) );
NOR4X1TS U5921 ( .A(FPMULT_Op_MX[14]), .B(FPMULT_Op_MX[15]), .C(
FPMULT_Op_MX[16]), .D(FPMULT_Op_MX[17]), .Y(n4918) );
NOR4X1TS U5922 ( .A(FPMULT_Op_MX[24]), .B(n2349), .C(FPMULT_Op_MX[12]), .D(
FPMULT_Op_MX[13]), .Y(n4917) );
NAND4XLTS U5923 ( .A(n4920), .B(n4919), .C(n4918), .D(n4917), .Y(n4938) );
NOR4X1TS U5924 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MY[11]), .C(n4922), .D(
n4921), .Y(n4929) );
NOR4X1TS U5925 ( .A(FPMULT_Op_MY[6]), .B(n4924), .C(n4923), .D(
FPMULT_Op_MY[9]), .Y(n4928) );
NOR4X1TS U5926 ( .A(FPMULT_Op_MY[21]), .B(FPMULT_Op_MY[18]), .C(
FPMULT_Op_MY[22]), .D(FPMULT_Op_MY[19]), .Y(n4927) );
NOR4X1TS U5927 ( .A(n4925), .B(FPMULT_Op_MY[3]), .C(FPMULT_Op_MY[4]), .D(
FPMULT_Op_MY[5]), .Y(n4926) );
NAND4XLTS U5928 ( .A(n4929), .B(n4928), .C(n4927), .D(n4926), .Y(n4937) );
NOR4X1TS U5929 ( .A(FPMULT_Op_MY[27]), .B(n2319), .C(n2320), .D(n2316), .Y(
n4935) );
NOR4X1TS U5930 ( .A(FPMULT_Op_MY[23]), .B(n2345), .C(FPMULT_Op_MY[12]), .D(
n2198), .Y(n4932) );
NAND4XLTS U5931 ( .A(n4935), .B(n4934), .C(n4933), .D(n4932), .Y(n4936) );
OA22X1TS U5932 ( .A0(n4939), .A1(n4938), .B0(n4937), .B1(n4936), .Y(n4940)
);
OAI2BB2XLTS U5933 ( .B0(n4941), .B1(n4940), .A0N(n4941), .A1N(
FPMULT_zero_flag), .Y(n1625) );
AO22XLTS U5934 ( .A0(n4528), .A1(Data_2[31]), .B0(n4419), .B1(
FPMULT_Op_MY[31]), .Y(n1624) );
INVX2TS U5935 ( .A(n4418), .Y(n4984) );
AOI2BB2XLTS U5936 ( .B0(n4987), .B1(FPMULT_Sgf_normalized_result[0]), .A0N(
FPMULT_Add_result[0]), .A1N(n4984), .Y(n1620) );
AOI21X1TS U5937 ( .A0(FPMULT_Sgf_normalized_result[0]), .A1(
FPMULT_Sgf_normalized_result[1]), .B0(n4944), .Y(n4943) );
AOI22X1TS U5938 ( .A0(n4991), .A1(n4943), .B0(n5367), .B1(n4990), .Y(n1619)
);
NAND2BXLTS U5939 ( .AN(n4944), .B(n2359), .Y(n4946) );
AOI32X1TS U5940 ( .A0(n4947), .A1(n4991), .A2(n4946), .B0(n4945), .B1(n4990),
.Y(n1618) );
OAI21XLTS U5941 ( .A0(FPMULT_Sgf_normalized_result[3]), .A1(n4947), .B0(
n4950), .Y(n4948) );
AOI22X1TS U5942 ( .A0(n4991), .A1(n4948), .B0(n5368), .B1(n4990), .Y(n1617)
);
OAI21XLTS U5943 ( .A0(n4950), .A1(n4949), .B0(n4952), .Y(n4951) );
OAI211XLTS U5944 ( .A0(n2364), .A1(n4952), .B0(n4991), .C0(n4955), .Y(n4953)
);
OAI2BB1X1TS U5945 ( .A0N(n2355), .A1N(n4418), .B0(n4953), .Y(n1615) );
AOI21X1TS U5946 ( .A0(n5245), .A1(n4955), .B0(n4954), .Y(n4956) );
AO22XLTS U5947 ( .A0(n4990), .A1(FPMULT_Add_result[6]), .B0(n4984), .B1(
n4956), .Y(n1614) );
AOI21X1TS U5948 ( .A0(n4958), .A1(n4957), .B0(n4960), .Y(n4959) );
AO22XLTS U5949 ( .A0(n4990), .A1(FPMULT_Add_result[8]), .B0(n4984), .B1(
n4959), .Y(n1612) );
OAI2BB1X1TS U5950 ( .A0N(n2350), .A1N(n4418), .B0(n4961), .Y(n1611) );
AOI21X1TS U5951 ( .A0(n4963), .A1(n4962), .B0(n4965), .Y(n4964) );
OAI2BB1X1TS U5952 ( .A0N(n2351), .A1N(n4418), .B0(n4966), .Y(n1609) );
AOI21X1TS U5953 ( .A0(n5259), .A1(n4968), .B0(n4967), .Y(n4969) );
AOI21X1TS U5954 ( .A0(n4971), .A1(n4970), .B0(n4973), .Y(n4972) );
OAI211XLTS U5955 ( .A0(n2360), .A1(n4973), .B0(n4991), .C0(n4976), .Y(n4974)
);
OAI2BB1X1TS U5956 ( .A0N(FPMULT_Add_result[15]), .A1N(n4418), .B0(n4974),
.Y(n1605) );
AOI21X1TS U5957 ( .A0(n5290), .A1(n4976), .B0(n4975), .Y(n4977) );
AOI21X1TS U5958 ( .A0(n5335), .A1(n4979), .B0(n4978), .Y(n4980) );
AOI21X1TS U5959 ( .A0(n4982), .A1(n4981), .B0(n4985), .Y(n4983) );
NAND2X1TS U5960 ( .A(n4987), .B(n4986), .Y(n4988) );
OAI2BB2XLTS U5961 ( .B0(n4989), .B1(n4988), .A0N(FPMULT_Add_result[21]),
.A1N(n4418), .Y(n1599) );
AOI22X1TS U5962 ( .A0(n4991), .A1(FPMULT_Sgf_normalized_result[23]), .B0(
FPMULT_Add_result[23]), .B1(n4990), .Y(n4993) );
MXI2X1TS U5963 ( .A(n4993), .B(FPMULT_Sgf_normalized_result[23]), .S0(n4992),
.Y(n1597) );
BUFX3TS U5964 ( .A(n4994), .Y(n4998) );
OAI21XLTS U5965 ( .A0(n4996), .A1(n2358), .B0(n4995), .Y(n4997) );
OAI2BB1X1TS U5966 ( .A0N(mult_result[31]), .A1N(n4998), .B0(n4997), .Y(n1576) );
AO22XLTS U5967 ( .A0(FPMULT_Sgf_normalized_result[0]), .A1(n4999), .B0(
mult_result[0]), .B1(n4998), .Y(n1504) );
AO22XLTS U5968 ( .A0(FPMULT_Sgf_normalized_result[1]), .A1(n4999), .B0(
mult_result[1]), .B1(n4998), .Y(n1503) );
AO22XLTS U5969 ( .A0(n2359), .A1(n4999), .B0(mult_result[2]), .B1(n4998),
.Y(n1502) );
AO22XLTS U5970 ( .A0(FPMULT_Sgf_normalized_result[3]), .A1(n4999), .B0(
mult_result[3]), .B1(n4998), .Y(n1501) );
AO22XLTS U5971 ( .A0(FPMULT_Sgf_normalized_result[4]), .A1(n4999), .B0(
mult_result[4]), .B1(n4998), .Y(n1500) );
AO22XLTS U5972 ( .A0(n2364), .A1(n4999), .B0(mult_result[5]), .B1(n4998),
.Y(n1499) );
AO22XLTS U5973 ( .A0(FPMULT_Sgf_normalized_result[6]), .A1(n4999), .B0(
mult_result[6]), .B1(n4998), .Y(n1498) );
AO22XLTS U5974 ( .A0(n2365), .A1(n4999), .B0(mult_result[7]), .B1(n4998),
.Y(n1497) );
AO22XLTS U5975 ( .A0(FPMULT_Sgf_normalized_result[8]), .A1(n4999), .B0(
mult_result[8]), .B1(n4998), .Y(n1496) );
AO22XLTS U5976 ( .A0(FPMULT_Sgf_normalized_result[9]), .A1(n4999), .B0(
mult_result[9]), .B1(n4998), .Y(n1495) );
AO22XLTS U5977 ( .A0(FPMULT_Sgf_normalized_result[10]), .A1(n4999), .B0(
mult_result[10]), .B1(n4998), .Y(n1494) );
AO22XLTS U5978 ( .A0(FPMULT_Sgf_normalized_result[11]), .A1(n4999), .B0(
mult_result[11]), .B1(n4994), .Y(n1493) );
AO22XLTS U5979 ( .A0(FPMULT_Sgf_normalized_result[12]), .A1(n4999), .B0(
mult_result[12]), .B1(n4994), .Y(n1492) );
INVX2TS U5980 ( .A(n2396), .Y(n5000) );
AO22XLTS U5981 ( .A0(n2366), .A1(n5000), .B0(mult_result[13]), .B1(n4994),
.Y(n1491) );
AO22XLTS U5982 ( .A0(FPMULT_Sgf_normalized_result[14]), .A1(n5000), .B0(
mult_result[14]), .B1(n4994), .Y(n1490) );
AO22XLTS U5983 ( .A0(n2360), .A1(n5000), .B0(mult_result[15]), .B1(n4994),
.Y(n1489) );
AO22XLTS U5984 ( .A0(FPMULT_Sgf_normalized_result[16]), .A1(n5000), .B0(
mult_result[16]), .B1(n4994), .Y(n1488) );
AO22XLTS U5985 ( .A0(n2367), .A1(n5000), .B0(mult_result[17]), .B1(n4994),
.Y(n1487) );
AO22XLTS U5986 ( .A0(FPMULT_Sgf_normalized_result[18]), .A1(n5000), .B0(
mult_result[18]), .B1(n4994), .Y(n1486) );
AO22XLTS U5987 ( .A0(FPMULT_Sgf_normalized_result[19]), .A1(n5000), .B0(
mult_result[19]), .B1(n4994), .Y(n1485) );
AO22XLTS U5988 ( .A0(FPMULT_Sgf_normalized_result[20]), .A1(n5000), .B0(
mult_result[20]), .B1(n4994), .Y(n1484) );
AO22XLTS U5989 ( .A0(FPMULT_Sgf_normalized_result[21]), .A1(n5000), .B0(
mult_result[21]), .B1(n4994), .Y(n1483) );
AO22XLTS U5990 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n5000), .B0(
mult_result[22]), .B1(n4994), .Y(n1481) );
OAI21XLTS U5991 ( .A0(FPADDSUB_DmP_EXP_EWSW[23]), .A1(n5348), .B0(
intadd_523_CI), .Y(n5001) );
AO22XLTS U5992 ( .A0(n5179), .A1(n5001), .B0(n5010), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[0]), .Y(n1475) );
XNOR2X1TS U5993 ( .A(n2354), .B(FPADDSUB_DmP_EXP_EWSW[27]), .Y(n5002) );
XOR2XLTS U5994 ( .A(intadd_523_n1), .B(n5002), .Y(n5003) );
AO22XLTS U5995 ( .A0(n5179), .A1(n5003), .B0(n5010), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[4]), .Y(n1474) );
AO22XLTS U5996 ( .A0(n5098), .A1(FPADDSUB_DMP_EXP_EWSW[23]), .B0(n5010),
.B1(FPADDSUB_DMP_SHT1_EWSW[23]), .Y(n1457) );
AO22XLTS U5997 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[23]), .B0(n5417),
.B1(FPADDSUB_DMP_SHT2_EWSW[23]), .Y(n1456) );
AO22XLTS U5998 ( .A0(n5153), .A1(FPADDSUB_DMP_SHT2_EWSW[23]), .B0(n5099),
.B1(FPADDSUB_DMP_SFG[23]), .Y(n1455) );
AO22XLTS U5999 ( .A0(n5061), .A1(FPADDSUB_DMP_SFG[23]), .B0(n5232), .B1(
FPADDSUB_DMP_exp_NRM_EW[0]), .Y(n1454) );
AO22XLTS U6000 ( .A0(n5179), .A1(FPADDSUB_DMP_EXP_EWSW[24]), .B0(n5010),
.B1(FPADDSUB_DMP_SHT1_EWSW[24]), .Y(n1452) );
AO22XLTS U6001 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[24]), .B0(n5077),
.B1(FPADDSUB_DMP_SHT2_EWSW[24]), .Y(n1451) );
BUFX3TS U6002 ( .A(n5120), .Y(n5130) );
AO22XLTS U6003 ( .A0(n5130), .A1(FPADDSUB_DMP_SHT2_EWSW[24]), .B0(n5039),
.B1(FPADDSUB_DMP_SFG[24]), .Y(n1450) );
AO22XLTS U6004 ( .A0(n5093), .A1(FPADDSUB_DMP_SFG[24]), .B0(n5232), .B1(
FPADDSUB_DMP_exp_NRM_EW[1]), .Y(n1449) );
AO22XLTS U6005 ( .A0(n5098), .A1(FPADDSUB_DMP_EXP_EWSW[25]), .B0(n5010),
.B1(FPADDSUB_DMP_SHT1_EWSW[25]), .Y(n1447) );
AO22XLTS U6006 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[25]), .B0(n5077),
.B1(FPADDSUB_DMP_SHT2_EWSW[25]), .Y(n1446) );
AO22XLTS U6007 ( .A0(n5130), .A1(FPADDSUB_DMP_SHT2_EWSW[25]), .B0(n5099),
.B1(FPADDSUB_DMP_SFG[25]), .Y(n1445) );
AO22XLTS U6008 ( .A0(n5093), .A1(FPADDSUB_DMP_SFG[25]), .B0(n5232), .B1(
FPADDSUB_DMP_exp_NRM_EW[2]), .Y(n1444) );
AO22XLTS U6009 ( .A0(n5179), .A1(FPADDSUB_DMP_EXP_EWSW[26]), .B0(n5010),
.B1(FPADDSUB_DMP_SHT1_EWSW[26]), .Y(n1442) );
AO22XLTS U6010 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[26]), .B0(n5077),
.B1(FPADDSUB_DMP_SHT2_EWSW[26]), .Y(n1441) );
AO22XLTS U6011 ( .A0(n5130), .A1(FPADDSUB_DMP_SHT2_EWSW[26]), .B0(n5039),
.B1(FPADDSUB_DMP_SFG[26]), .Y(n1440) );
AO22XLTS U6012 ( .A0(n5093), .A1(FPADDSUB_DMP_SFG[26]), .B0(n5065), .B1(
FPADDSUB_DMP_exp_NRM_EW[3]), .Y(n1439) );
AO22XLTS U6013 ( .A0(n5098), .A1(n2354), .B0(n5010), .B1(
FPADDSUB_DMP_SHT1_EWSW[27]), .Y(n1437) );
AO22XLTS U6014 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[27]), .B0(n5077),
.B1(FPADDSUB_DMP_SHT2_EWSW[27]), .Y(n1436) );
AO22XLTS U6015 ( .A0(n5130), .A1(FPADDSUB_DMP_SHT2_EWSW[27]), .B0(n5099),
.B1(FPADDSUB_DMP_SFG[27]), .Y(n1435) );
AO22XLTS U6016 ( .A0(n5093), .A1(FPADDSUB_DMP_SFG[27]), .B0(n5065), .B1(
FPADDSUB_DMP_exp_NRM_EW[4]), .Y(n1434) );
AO22XLTS U6017 ( .A0(n5179), .A1(FPADDSUB_DMP_EXP_EWSW[28]), .B0(n5010),
.B1(FPADDSUB_DMP_SHT1_EWSW[28]), .Y(n1432) );
AO22XLTS U6018 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[28]), .B0(n5077),
.B1(FPADDSUB_DMP_SHT2_EWSW[28]), .Y(n1431) );
AO22XLTS U6019 ( .A0(n5130), .A1(FPADDSUB_DMP_SHT2_EWSW[28]), .B0(n5039),
.B1(FPADDSUB_DMP_SFG[28]), .Y(n1430) );
AO22XLTS U6020 ( .A0(n5098), .A1(FPADDSUB_DMP_EXP_EWSW[29]), .B0(n5010),
.B1(FPADDSUB_DMP_SHT1_EWSW[29]), .Y(n1427) );
AO22XLTS U6021 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[29]), .B0(n5077),
.B1(FPADDSUB_DMP_SHT2_EWSW[29]), .Y(n1426) );
AO22XLTS U6022 ( .A0(n5153), .A1(FPADDSUB_DMP_SHT2_EWSW[29]), .B0(n5099),
.B1(FPADDSUB_DMP_SFG[29]), .Y(n1425) );
AO22XLTS U6023 ( .A0(n5093), .A1(FPADDSUB_DMP_SFG[29]), .B0(n5065), .B1(
FPADDSUB_DMP_exp_NRM_EW[6]), .Y(n1424) );
AO22XLTS U6024 ( .A0(n5179), .A1(FPADDSUB_DMP_EXP_EWSW[30]), .B0(n5010),
.B1(FPADDSUB_DMP_SHT1_EWSW[30]), .Y(n1422) );
AO22XLTS U6025 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[30]), .B0(n5077),
.B1(FPADDSUB_DMP_SHT2_EWSW[30]), .Y(n1421) );
AO22XLTS U6026 ( .A0(n5130), .A1(FPADDSUB_DMP_SHT2_EWSW[30]), .B0(n5039),
.B1(FPADDSUB_DMP_SFG[30]), .Y(n1420) );
AO22XLTS U6027 ( .A0(n5093), .A1(FPADDSUB_DMP_SFG[30]), .B0(n5065), .B1(
FPADDSUB_DMP_exp_NRM_EW[7]), .Y(n1419) );
OA21XLTS U6028 ( .A0(n2280), .A1(underflow_flag_addsubt), .B0(n5004), .Y(
n1412) );
NAND2X1TS U6029 ( .A(FPADDSUB_DMP_SFG[22]), .B(n5351), .Y(n5086) );
AOI2BB2X1TS U6030 ( .B0(n5086), .B1(n5088), .A0N(n5351), .A1N(
FPADDSUB_DMP_SFG[22]), .Y(n5007) );
AO22XLTS U6031 ( .A0(n5098), .A1(FPADDSUB_DmP_EXP_EWSW[22]), .B0(n5010),
.B1(FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n1406) );
AO22XLTS U6032 ( .A0(n5098), .A1(FPADDSUB_DmP_EXP_EWSW[15]), .B0(n5010),
.B1(FPADDSUB_DmP_mant_SHT1_SW[15]), .Y(n1403) );
AO22XLTS U6033 ( .A0(n5102), .A1(FPADDSUB_DmP_mant_SHT1_SW[18]), .B0(n5179),
.B1(FPADDSUB_DmP_EXP_EWSW[18]), .Y(n1400) );
AO22XLTS U6034 ( .A0(n5098), .A1(FPADDSUB_DmP_EXP_EWSW[21]), .B0(n5010),
.B1(FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n1397) );
BUFX3TS U6035 ( .A(n5361), .Y(n5076) );
AO22XLTS U6036 ( .A0(n5098), .A1(FPADDSUB_DmP_EXP_EWSW[19]), .B0(n5076),
.B1(FPADDSUB_DmP_mant_SHT1_SW[19]), .Y(n1394) );
AO22XLTS U6037 ( .A0(n5098), .A1(FPADDSUB_DmP_EXP_EWSW[20]), .B0(n5076),
.B1(FPADDSUB_DmP_mant_SHT1_SW[20]), .Y(n1391) );
AO22XLTS U6038 ( .A0(n5098), .A1(FPADDSUB_DmP_EXP_EWSW[17]), .B0(n5076),
.B1(FPADDSUB_DmP_mant_SHT1_SW[17]), .Y(n1388) );
AO22XLTS U6039 ( .A0(n5098), .A1(FPADDSUB_DmP_EXP_EWSW[4]), .B0(n5076), .B1(
FPADDSUB_DmP_mant_SHT1_SW[4]), .Y(n1385) );
AO22XLTS U6040 ( .A0(n5098), .A1(FPADDSUB_DmP_EXP_EWSW[6]), .B0(n5076), .B1(
FPADDSUB_DmP_mant_SHT1_SW[6]), .Y(n1382) );
AOI21X1TS U6041 ( .A0(FPADDSUB_Data_array_SWR[9]), .A1(n3719), .B0(n5026),
.Y(n5012) );
AOI22X1TS U6042 ( .A0(FPADDSUB_Data_array_SWR[18]), .A1(n3723), .B0(
FPADDSUB_Data_array_SWR[14]), .B1(n5030), .Y(n5011) );
OAI211X1TS U6043 ( .A0(n5352), .A1(n5013), .B0(n5012), .C0(n5011), .Y(n5017)
);
NOR2X1TS U6044 ( .A(n5026), .B(n5014), .Y(n5032) );
AOI22X1TS U6045 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n5107), .B0(n2369),
.B1(n3719), .Y(n5015) );
OAI211X1TS U6046 ( .A0(n5342), .A1(n5108), .B0(n5032), .C0(n5015), .Y(n5018)
);
AOI22X1TS U6047 ( .A0(n2286), .A1(n5017), .B0(n5018), .B1(n5148), .Y(n5135)
);
INVX2TS U6048 ( .A(n5016), .Y(n5096) );
OAI22X1TS U6049 ( .A0(n5023), .A1(n5294), .B0(n5135), .B1(n5096), .Y(n1381)
);
AO22XLTS U6050 ( .A0(n5102), .A1(FPADDSUB_DmP_mant_SHT1_SW[13]), .B0(n5179),
.B1(FPADDSUB_DmP_EXP_EWSW[13]), .Y(n1379) );
AO22XLTS U6051 ( .A0(n5104), .A1(FPADDSUB_DmP_EXP_EWSW[16]), .B0(n5076),
.B1(FPADDSUB_DmP_mant_SHT1_SW[16]), .Y(n1376) );
AOI22X1TS U6052 ( .A0(n2285), .A1(n5018), .B0(n5017), .B1(n2284), .Y(n5127)
);
OAI22X1TS U6053 ( .A0(n2280), .A1(n5295), .B0(n5127), .B1(n5096), .Y(n1375)
);
AO22XLTS U6054 ( .A0(n5104), .A1(FPADDSUB_DmP_EXP_EWSW[8]), .B0(n5076), .B1(
FPADDSUB_DmP_mant_SHT1_SW[8]), .Y(n1373) );
AOI22X1TS U6055 ( .A0(FPADDSUB_Data_array_SWR[16]), .A1(n5030), .B0(
FPADDSUB_Data_array_SWR[20]), .B1(n3723), .Y(n5020) );
AOI22X1TS U6056 ( .A0(FPADDSUB_Data_array_SWR[12]), .A1(n5107), .B0(n2368),
.B1(n3719), .Y(n5019) );
NAND2X1TS U6057 ( .A(n5020), .B(n5019), .Y(n5024) );
AOI22X1TS U6058 ( .A0(FPADDSUB_Data_array_SWR[10]), .A1(n3719), .B0(
FPADDSUB_Data_array_SWR[21]), .B1(n3723), .Y(n5022) );
AOI22X1TS U6059 ( .A0(FPADDSUB_Data_array_SWR[17]), .A1(n5030), .B0(
FPADDSUB_Data_array_SWR[13]), .B1(n5107), .Y(n5021) );
NAND2X1TS U6060 ( .A(n5022), .B(n5021), .Y(n5025) );
AOI221X1TS U6061 ( .A0(FPADDSUB_left_right_SHT2), .A1(n5024), .B0(n2243),
.B1(n5025), .C0(n5026), .Y(n5133) );
OAI22X1TS U6062 ( .A0(n5023), .A1(n5296), .B0(n5133), .B1(n5096), .Y(n1372)
);
AO22XLTS U6063 ( .A0(n5361), .A1(FPADDSUB_DmP_mant_SHT1_SW[11]), .B0(n5179),
.B1(FPADDSUB_DmP_EXP_EWSW[11]), .Y(n1370) );
AO22XLTS U6064 ( .A0(n5104), .A1(FPADDSUB_DmP_EXP_EWSW[14]), .B0(n5076),
.B1(FPADDSUB_DmP_mant_SHT1_SW[14]), .Y(n1367) );
AOI221X1TS U6065 ( .A0(n2286), .A1(n5025), .B0(n2243), .B1(n5024), .C0(n5026), .Y(n5131) );
OAI22X1TS U6066 ( .A0(n2280), .A1(n5297), .B0(n5131), .B1(n5096), .Y(n1366)
);
AO22XLTS U6067 ( .A0(n5102), .A1(FPADDSUB_DmP_mant_SHT1_SW[10]), .B0(n5179),
.B1(FPADDSUB_DmP_EXP_EWSW[10]), .Y(n1364) );
AOI21X1TS U6068 ( .A0(n2369), .A1(n5107), .B0(n5026), .Y(n5028) );
AOI22X1TS U6069 ( .A0(FPADDSUB_Data_array_SWR[15]), .A1(n5030), .B0(n2361),
.B1(n3719), .Y(n5027) );
OAI211X1TS U6070 ( .A0(n5342), .A1(n5029), .B0(n5028), .C0(n5027), .Y(n5094)
);
AOI22X1TS U6071 ( .A0(FPADDSUB_Data_array_SWR[18]), .A1(n5030), .B0(
FPADDSUB_Data_array_SWR[14]), .B1(n5107), .Y(n5031) );
OAI211X1TS U6072 ( .A0(n5352), .A1(n5033), .B0(n5032), .C0(n5031), .Y(n5095)
);
AOI22X1TS U6073 ( .A0(n2286), .A1(n5094), .B0(n5095), .B1(n2284), .Y(n5134)
);
OAI22X1TS U6074 ( .A0(n2280), .A1(n5298), .B0(n5134), .B1(n5096), .Y(n1363)
);
AO22XLTS U6075 ( .A0(n5104), .A1(FPADDSUB_SIGN_FLAG_EXP), .B0(n5076), .B1(
FPADDSUB_SIGN_FLAG_SHT1), .Y(n1361) );
AO22XLTS U6076 ( .A0(n5100), .A1(FPADDSUB_SIGN_FLAG_SHT1), .B0(n5077), .B1(
FPADDSUB_SIGN_FLAG_SHT2), .Y(n1360) );
AO22XLTS U6077 ( .A0(n5130), .A1(FPADDSUB_SIGN_FLAG_SHT2), .B0(n5039), .B1(
FPADDSUB_SIGN_FLAG_SFG), .Y(n1359) );
AO22XLTS U6078 ( .A0(n5093), .A1(FPADDSUB_SIGN_FLAG_SFG), .B0(n5065), .B1(
FPADDSUB_SIGN_FLAG_NRM), .Y(n1358) );
AO22XLTS U6079 ( .A0(FPADDSUB_Shift_reg_FLAGS_7[1]), .A1(
FPADDSUB_SIGN_FLAG_NRM), .B0(n5034), .B1(FPADDSUB_SIGN_FLAG_SHT1SHT2),
.Y(n1357) );
AOI2BB2XLTS U6080 ( .B0(FPADDSUB_intDX_EWSW[31]), .B1(n5036), .A0N(n5036),
.A1N(FPADDSUB_intDX_EWSW[31]), .Y(n5038) );
AO22XLTS U6081 ( .A0(FPADDSUB_Shift_reg_FLAGS_7_6), .A1(n5038), .B0(n5037),
.B1(FPADDSUB_OP_FLAG_EXP), .Y(n1355) );
AO22XLTS U6082 ( .A0(n5104), .A1(FPADDSUB_OP_FLAG_EXP), .B0(n5076), .B1(
FPADDSUB_OP_FLAG_SHT1), .Y(n1354) );
AO22XLTS U6083 ( .A0(n5100), .A1(FPADDSUB_OP_FLAG_SHT1), .B0(n5077), .B1(
FPADDSUB_OP_FLAG_SHT2), .Y(n1353) );
AO22XLTS U6084 ( .A0(n5099), .A1(FPADDSUB_OP_FLAG_SFG), .B0(n5136), .B1(
FPADDSUB_OP_FLAG_SHT2), .Y(n1352) );
NOR2BX1TS U6085 ( .AN(n5040), .B(FPADDSUB_DmP_mant_SFG_SWR[25]), .Y(n5041)
);
OA22X1TS U6086 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(n5042), .B0(n5065),
.B1(FPADDSUB_DmP_mant_SFG_SWR[0]), .Y(n1349) );
NAND2X1TS U6087 ( .A(FPADDSUB_OP_FLAG_SFG), .B(FPADDSUB_DmP_mant_SFG_SWR[0]),
.Y(n5043) );
AOI22X1TS U6088 ( .A0(n5061), .A1(n5044), .B0(n5276), .B1(n5091), .Y(n1348)
);
NOR2XLTS U6089 ( .A(n5045), .B(n5286), .Y(n5048) );
OAI21XLTS U6090 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[2]), .A1(n5234), .B0(n5046),
.Y(n5047) );
XNOR2X1TS U6091 ( .A(n5048), .B(n5047), .Y(n5049) );
AOI2BB2XLTS U6092 ( .B0(n5093), .B1(n5049), .A0N(
FPADDSUB_Raw_mant_NRM_SWR[2]), .A1N(n5061), .Y(n1347) );
AOI22X1TS U6093 ( .A0(FPADDSUB_OP_FLAG_SFG), .A1(n5051), .B0(n5050), .B1(
n5286), .Y(n5052) );
XOR2X1TS U6094 ( .A(n5053), .B(n5052), .Y(n5054) );
AOI22X1TS U6095 ( .A0(n5093), .A1(n5054), .B0(n5289), .B1(n5091), .Y(n1342)
);
OAI21XLTS U6096 ( .A0(FPADDSUB_DMP_SFG[6]), .A1(n5239), .B0(n5055), .Y(n5059) );
AOI22X1TS U6097 ( .A0(FPADDSUB_OP_FLAG_SFG), .A1(n5057), .B0(n5056), .B1(
n5286), .Y(n5058) );
XOR2X1TS U6098 ( .A(n5059), .B(n5058), .Y(n5060) );
AOI22X1TS U6099 ( .A0(n5061), .A1(n5060), .B0(n5264), .B1(n5091), .Y(n1341)
);
AOI21X1TS U6100 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[14]), .A1(n5065), .B0(n5064),
.Y(n5068) );
AOI32X1TS U6101 ( .A0(n5069), .A1(n5068), .A2(n5067), .B0(n5066), .B1(n5068),
.Y(n1335) );
AOI22X1TS U6102 ( .A0(FPADDSUB_OP_FLAG_SFG), .A1(n5071), .B0(n5070), .B1(
n5286), .Y(n5074) );
XOR2X1TS U6103 ( .A(n5074), .B(n5073), .Y(n5075) );
AOI22X1TS U6104 ( .A0(n5093), .A1(n5075), .B0(n5272), .B1(n5091), .Y(n1331)
);
AO22XLTS U6105 ( .A0(n5104), .A1(FPADDSUB_DmP_EXP_EWSW[3]), .B0(n5076), .B1(
FPADDSUB_DmP_mant_SHT1_SW[3]), .Y(n1327) );
AO22XLTS U6106 ( .A0(n5104), .A1(FPADDSUB_DMP_EXP_EWSW[3]), .B0(n5076), .B1(
FPADDSUB_DMP_SHT1_EWSW[3]), .Y(n1325) );
AO22XLTS U6107 ( .A0(n5100), .A1(FPADDSUB_DMP_SHT1_EWSW[3]), .B0(n5077),
.B1(FPADDSUB_DMP_SHT2_EWSW[3]), .Y(n1324) );
AO22XLTS U6108 ( .A0(n5132), .A1(FPADDSUB_DMP_SFG[3]), .B0(n5136), .B1(
FPADDSUB_DMP_SHT2_EWSW[3]), .Y(n1323) );
AOI211X1TS U6109 ( .A0(n5085), .A1(n5080), .B0(n5079), .C0(n5078), .Y(n5081)
);
AOI21X1TS U6110 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[22]), .A1(n5091), .B0(n5081),
.Y(n5084) );
AOI32X1TS U6111 ( .A0(n5085), .A1(n5084), .A2(n5083), .B0(n5082), .B1(n5084),
.Y(n1317) );
AOI22X1TS U6112 ( .A0(FPADDSUB_OP_FLAG_SFG), .A1(n5088), .B0(n5087), .B1(
n5286), .Y(n5089) );
XOR2X1TS U6113 ( .A(n5090), .B(n5089), .Y(n5092) );
AOI22X1TS U6114 ( .A0(n5093), .A1(n5092), .B0(n5250), .B1(n5091), .Y(n1315)
);
AO22XLTS U6115 ( .A0(n5104), .A1(FPADDSUB_DmP_EXP_EWSW[2]), .B0(n5101), .B1(
FPADDSUB_DmP_mant_SHT1_SW[2]), .Y(n1311) );
AO22XLTS U6116 ( .A0(n5104), .A1(FPADDSUB_DMP_EXP_EWSW[2]), .B0(n5102), .B1(
FPADDSUB_DMP_SHT1_EWSW[2]), .Y(n1309) );
AO22XLTS U6117 ( .A0(n5100), .A1(FPADDSUB_DMP_SHT1_EWSW[2]), .B0(n5417),
.B1(FPADDSUB_DMP_SHT2_EWSW[2]), .Y(n1308) );
AO22XLTS U6118 ( .A0(n5039), .A1(FPADDSUB_DMP_SFG[2]), .B0(n5136), .B1(
FPADDSUB_DMP_SHT2_EWSW[2]), .Y(n1307) );
AO22XLTS U6119 ( .A0(n5104), .A1(FPADDSUB_DmP_EXP_EWSW[7]), .B0(n5361), .B1(
FPADDSUB_DmP_mant_SHT1_SW[7]), .Y(n1304) );
AO22XLTS U6120 ( .A0(n5179), .A1(FPADDSUB_DMP_EXP_EWSW[7]), .B0(n5076), .B1(
FPADDSUB_DMP_SHT1_EWSW[7]), .Y(n1302) );
AO22XLTS U6121 ( .A0(n5100), .A1(FPADDSUB_DMP_SHT1_EWSW[7]), .B0(n5417),
.B1(FPADDSUB_DMP_SHT2_EWSW[7]), .Y(n1301) );
AO22XLTS U6122 ( .A0(n5132), .A1(FPADDSUB_DMP_SFG[7]), .B0(n5136), .B1(
FPADDSUB_DMP_SHT2_EWSW[7]), .Y(n1300) );
AO22XLTS U6123 ( .A0(n5179), .A1(FPADDSUB_DmP_EXP_EWSW[0]), .B0(n5101), .B1(
FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n1297) );
AO22XLTS U6124 ( .A0(n2375), .A1(FPADDSUB_DMP_EXP_EWSW[0]), .B0(n5102), .B1(
FPADDSUB_DMP_SHT1_EWSW[0]), .Y(n1295) );
AO22XLTS U6125 ( .A0(n5100), .A1(FPADDSUB_DMP_SHT1_EWSW[0]), .B0(n5417),
.B1(FPADDSUB_DMP_SHT2_EWSW[0]), .Y(n1294) );
AO22XLTS U6126 ( .A0(n5099), .A1(FPADDSUB_DMP_SFG[0]), .B0(n5130), .B1(
FPADDSUB_DMP_SHT2_EWSW[0]), .Y(n1293) );
AO22XLTS U6127 ( .A0(n2375), .A1(FPADDSUB_DmP_EXP_EWSW[1]), .B0(n5076), .B1(
FPADDSUB_DmP_mant_SHT1_SW[1]), .Y(n1290) );
AO22XLTS U6128 ( .A0(n2375), .A1(FPADDSUB_DMP_EXP_EWSW[1]), .B0(n5101), .B1(
FPADDSUB_DMP_SHT1_EWSW[1]), .Y(n1288) );
AO22XLTS U6129 ( .A0(n5100), .A1(FPADDSUB_DMP_SHT1_EWSW[1]), .B0(n5417),
.B1(FPADDSUB_DMP_SHT2_EWSW[1]), .Y(n1287) );
AOI22X1TS U6130 ( .A0(FPADDSUB_left_right_SHT2), .A1(n5095), .B0(n5094),
.B1(n2243), .Y(n5129) );
OAI22X1TS U6131 ( .A0(n2280), .A1(n5299), .B0(n5129), .B1(n5096), .Y(n1285)
);
AO22XLTS U6132 ( .A0(n5102), .A1(FPADDSUB_DmP_mant_SHT1_SW[9]), .B0(n5179),
.B1(FPADDSUB_DmP_EXP_EWSW[9]), .Y(n1283) );
BUFX3TS U6133 ( .A(n5361), .Y(n5101) );
AO22XLTS U6134 ( .A0(n2375), .A1(FPADDSUB_DMP_EXP_EWSW[9]), .B0(n5101), .B1(
FPADDSUB_DMP_SHT1_EWSW[9]), .Y(n1281) );
AO22XLTS U6135 ( .A0(n5100), .A1(FPADDSUB_DMP_SHT1_EWSW[9]), .B0(n5417),
.B1(FPADDSUB_DMP_SHT2_EWSW[9]), .Y(n1280) );
AO22XLTS U6136 ( .A0(n5132), .A1(FPADDSUB_DMP_SFG[9]), .B0(n5130), .B1(
FPADDSUB_DMP_SHT2_EWSW[9]), .Y(n1279) );
AO22XLTS U6137 ( .A0(n5361), .A1(FPADDSUB_DmP_mant_SHT1_SW[5]), .B0(n5179),
.B1(FPADDSUB_DmP_EXP_EWSW[5]), .Y(n1276) );
AO22XLTS U6138 ( .A0(n2375), .A1(FPADDSUB_DMP_EXP_EWSW[5]), .B0(n5101), .B1(
FPADDSUB_DMP_SHT1_EWSW[5]), .Y(n1274) );
AO22XLTS U6139 ( .A0(n5100), .A1(FPADDSUB_DMP_SHT1_EWSW[5]), .B0(n5417),
.B1(FPADDSUB_DMP_SHT2_EWSW[5]), .Y(n1273) );
AO22XLTS U6140 ( .A0(n5132), .A1(FPADDSUB_DMP_SFG[5]), .B0(n5136), .B1(
FPADDSUB_DMP_SHT2_EWSW[5]), .Y(n1272) );
AO22XLTS U6141 ( .A0(n2375), .A1(FPADDSUB_DmP_EXP_EWSW[12]), .B0(n5102),
.B1(FPADDSUB_DmP_mant_SHT1_SW[12]), .Y(n1270) );
AO22XLTS U6142 ( .A0(n2375), .A1(FPADDSUB_DMP_EXP_EWSW[12]), .B0(n5101),
.B1(FPADDSUB_DMP_SHT1_EWSW[12]), .Y(n1268) );
AO22XLTS U6143 ( .A0(n5100), .A1(FPADDSUB_DMP_SHT1_EWSW[12]), .B0(n5417),
.B1(FPADDSUB_DMP_SHT2_EWSW[12]), .Y(n1267) );
BUFX3TS U6144 ( .A(n5130), .Y(n5128) );
AO22XLTS U6145 ( .A0(n5132), .A1(FPADDSUB_DMP_SFG[12]), .B0(n5128), .B1(
FPADDSUB_DMP_SHT2_EWSW[12]), .Y(n1266) );
AO22XLTS U6146 ( .A0(n2375), .A1(FPADDSUB_DMP_EXP_EWSW[10]), .B0(n5101),
.B1(FPADDSUB_DMP_SHT1_EWSW[10]), .Y(n1264) );
AO22XLTS U6147 ( .A0(n5100), .A1(FPADDSUB_DMP_SHT1_EWSW[10]), .B0(n5417),
.B1(FPADDSUB_DMP_SHT2_EWSW[10]), .Y(n1263) );
AO22XLTS U6148 ( .A0(n5132), .A1(FPADDSUB_DMP_SFG[10]), .B0(n5130), .B1(
FPADDSUB_DMP_SHT2_EWSW[10]), .Y(n1262) );
AO22XLTS U6149 ( .A0(n5098), .A1(FPADDSUB_DMP_EXP_EWSW[14]), .B0(n5101),
.B1(FPADDSUB_DMP_SHT1_EWSW[14]), .Y(n1260) );
AO22XLTS U6150 ( .A0(n5100), .A1(FPADDSUB_DMP_SHT1_EWSW[14]), .B0(n5105),
.B1(FPADDSUB_DMP_SHT2_EWSW[14]), .Y(n1259) );
AO22XLTS U6151 ( .A0(n5132), .A1(FPADDSUB_DMP_SFG[14]), .B0(n5128), .B1(
FPADDSUB_DMP_SHT2_EWSW[14]), .Y(n1258) );
AO22XLTS U6152 ( .A0(n5104), .A1(FPADDSUB_DMP_EXP_EWSW[11]), .B0(n5101),
.B1(FPADDSUB_DMP_SHT1_EWSW[11]), .Y(n1256) );
AO22XLTS U6153 ( .A0(n2194), .A1(FPADDSUB_DMP_SHT1_EWSW[11]), .B0(n5105),
.B1(FPADDSUB_DMP_SHT2_EWSW[11]), .Y(n1255) );
AO22XLTS U6154 ( .A0(n5132), .A1(FPADDSUB_DMP_SFG[11]), .B0(n5136), .B1(
FPADDSUB_DMP_SHT2_EWSW[11]), .Y(n1254) );
AO22XLTS U6155 ( .A0(n5103), .A1(FPADDSUB_DMP_EXP_EWSW[8]), .B0(n5101), .B1(
FPADDSUB_DMP_SHT1_EWSW[8]), .Y(n1252) );
AO22XLTS U6156 ( .A0(n2194), .A1(FPADDSUB_DMP_SHT1_EWSW[8]), .B0(n5105),
.B1(FPADDSUB_DMP_SHT2_EWSW[8]), .Y(n1251) );
AO22XLTS U6157 ( .A0(n5099), .A1(FPADDSUB_DMP_SFG[8]), .B0(n5136), .B1(
FPADDSUB_DMP_SHT2_EWSW[8]), .Y(n1250) );
AO22XLTS U6158 ( .A0(n5103), .A1(FPADDSUB_DMP_EXP_EWSW[16]), .B0(n5101),
.B1(FPADDSUB_DMP_SHT1_EWSW[16]), .Y(n1248) );
AO22XLTS U6159 ( .A0(n2194), .A1(FPADDSUB_DMP_SHT1_EWSW[16]), .B0(n5105),
.B1(FPADDSUB_DMP_SHT2_EWSW[16]), .Y(n1247) );
AO22XLTS U6160 ( .A0(n5132), .A1(FPADDSUB_DMP_SFG[16]), .B0(n5128), .B1(
FPADDSUB_DMP_SHT2_EWSW[16]), .Y(n1246) );
AO22XLTS U6161 ( .A0(n5103), .A1(FPADDSUB_DMP_EXP_EWSW[13]), .B0(n5102),
.B1(FPADDSUB_DMP_SHT1_EWSW[13]), .Y(n1244) );
AO22XLTS U6162 ( .A0(n2194), .A1(FPADDSUB_DMP_SHT1_EWSW[13]), .B0(n5105),
.B1(FPADDSUB_DMP_SHT2_EWSW[13]), .Y(n1243) );
AO22XLTS U6163 ( .A0(n5132), .A1(FPADDSUB_DMP_SFG[13]), .B0(n5128), .B1(
FPADDSUB_DMP_SHT2_EWSW[13]), .Y(n1242) );
AO22XLTS U6164 ( .A0(n5103), .A1(FPADDSUB_DMP_EXP_EWSW[6]), .B0(n5102), .B1(
FPADDSUB_DMP_SHT1_EWSW[6]), .Y(n1240) );
AO22XLTS U6165 ( .A0(n2194), .A1(FPADDSUB_DMP_SHT1_EWSW[6]), .B0(n5105),
.B1(FPADDSUB_DMP_SHT2_EWSW[6]), .Y(n1239) );
AO22XLTS U6166 ( .A0(n5099), .A1(FPADDSUB_DMP_SFG[6]), .B0(n5128), .B1(
FPADDSUB_DMP_SHT2_EWSW[6]), .Y(n1238) );
AO22XLTS U6167 ( .A0(n5103), .A1(FPADDSUB_DMP_EXP_EWSW[4]), .B0(n5101), .B1(
FPADDSUB_DMP_SHT1_EWSW[4]), .Y(n1236) );
AO22XLTS U6168 ( .A0(n5100), .A1(FPADDSUB_DMP_SHT1_EWSW[4]), .B0(n5105),
.B1(FPADDSUB_DMP_SHT2_EWSW[4]), .Y(n1235) );
AO22XLTS U6169 ( .A0(n5039), .A1(FPADDSUB_DMP_SFG[4]), .B0(n5130), .B1(
FPADDSUB_DMP_SHT2_EWSW[4]), .Y(n1234) );
AO22XLTS U6170 ( .A0(n5103), .A1(FPADDSUB_DMP_EXP_EWSW[17]), .B0(n5102),
.B1(FPADDSUB_DMP_SHT1_EWSW[17]), .Y(n1232) );
AO22XLTS U6171 ( .A0(n2194), .A1(FPADDSUB_DMP_SHT1_EWSW[17]), .B0(n5105),
.B1(FPADDSUB_DMP_SHT2_EWSW[17]), .Y(n1231) );
AO22XLTS U6172 ( .A0(n5039), .A1(FPADDSUB_DMP_SFG[17]), .B0(n5128), .B1(
FPADDSUB_DMP_SHT2_EWSW[17]), .Y(n1230) );
AO22XLTS U6173 ( .A0(n5103), .A1(FPADDSUB_DMP_EXP_EWSW[20]), .B0(n5102),
.B1(FPADDSUB_DMP_SHT1_EWSW[20]), .Y(n1228) );
AO22XLTS U6174 ( .A0(n2194), .A1(FPADDSUB_DMP_SHT1_EWSW[20]), .B0(n5105),
.B1(FPADDSUB_DMP_SHT2_EWSW[20]), .Y(n1227) );
AO22XLTS U6175 ( .A0(n5039), .A1(FPADDSUB_DMP_SFG[20]), .B0(n5128), .B1(
FPADDSUB_DMP_SHT2_EWSW[20]), .Y(n1226) );
AO22XLTS U6176 ( .A0(n5103), .A1(FPADDSUB_DMP_EXP_EWSW[19]), .B0(n5101),
.B1(FPADDSUB_DMP_SHT1_EWSW[19]), .Y(n1224) );
AO22XLTS U6177 ( .A0(n2194), .A1(FPADDSUB_DMP_SHT1_EWSW[19]), .B0(n5105),
.B1(FPADDSUB_DMP_SHT2_EWSW[19]), .Y(n1223) );
AO22XLTS U6178 ( .A0(n5099), .A1(FPADDSUB_DMP_SFG[19]), .B0(n5128), .B1(
FPADDSUB_DMP_SHT2_EWSW[19]), .Y(n1222) );
AO22XLTS U6179 ( .A0(n5103), .A1(FPADDSUB_DMP_EXP_EWSW[21]), .B0(n5101),
.B1(FPADDSUB_DMP_SHT1_EWSW[21]), .Y(n1220) );
AO22XLTS U6180 ( .A0(n2194), .A1(FPADDSUB_DMP_SHT1_EWSW[21]), .B0(n5105),
.B1(FPADDSUB_DMP_SHT2_EWSW[21]), .Y(n1219) );
AO22XLTS U6181 ( .A0(n5099), .A1(FPADDSUB_DMP_SFG[21]), .B0(n5128), .B1(
FPADDSUB_DMP_SHT2_EWSW[21]), .Y(n1218) );
AO22XLTS U6182 ( .A0(n5103), .A1(FPADDSUB_DMP_EXP_EWSW[18]), .B0(n5102),
.B1(FPADDSUB_DMP_SHT1_EWSW[18]), .Y(n1216) );
AO22XLTS U6183 ( .A0(n2194), .A1(FPADDSUB_DMP_SHT1_EWSW[18]), .B0(n5105),
.B1(FPADDSUB_DMP_SHT2_EWSW[18]), .Y(n1215) );
AO22XLTS U6184 ( .A0(n5039), .A1(FPADDSUB_DMP_SFG[18]), .B0(n5128), .B1(
FPADDSUB_DMP_SHT2_EWSW[18]), .Y(n1214) );
AO22XLTS U6185 ( .A0(n5103), .A1(FPADDSUB_DMP_EXP_EWSW[15]), .B0(n5102),
.B1(FPADDSUB_DMP_SHT1_EWSW[15]), .Y(n1212) );
AO22XLTS U6186 ( .A0(n2194), .A1(FPADDSUB_DMP_SHT1_EWSW[15]), .B0(n5105),
.B1(FPADDSUB_DMP_SHT2_EWSW[15]), .Y(n1211) );
AO22XLTS U6187 ( .A0(n5099), .A1(FPADDSUB_DMP_SFG[15]), .B0(n5136), .B1(
FPADDSUB_DMP_SHT2_EWSW[15]), .Y(n1210) );
AO22XLTS U6188 ( .A0(n5104), .A1(FPADDSUB_DMP_EXP_EWSW[22]), .B0(n5361),
.B1(FPADDSUB_DMP_SHT1_EWSW[22]), .Y(n1208) );
AO22XLTS U6189 ( .A0(n2194), .A1(FPADDSUB_DMP_SHT1_EWSW[22]), .B0(n5105),
.B1(FPADDSUB_DMP_SHT2_EWSW[22]), .Y(n1207) );
AO22XLTS U6190 ( .A0(n5039), .A1(FPADDSUB_DMP_SFG[22]), .B0(n5128), .B1(
FPADDSUB_DMP_SHT2_EWSW[22]), .Y(n1206) );
AO22XLTS U6191 ( .A0(n2368), .A1(n3723), .B0(FPADDSUB_Data_array_SWR[4]),
.B1(n5107), .Y(n5111) );
OAI22X1TS U6192 ( .A0(n5109), .A1(n5176), .B0(n5354), .B1(n5108), .Y(n5110)
);
AOI211X1TS U6193 ( .A0(n3719), .A1(FPADDSUB_Data_array_SWR[0]), .B0(n5111),
.C0(n5110), .Y(n5149) );
OAI22X1TS U6194 ( .A0(n2285), .A1(n5149), .B0(n5150), .B1(n3758), .Y(n5113)
);
NAND2X2TS U6195 ( .A(n5153), .B(n5112), .Y(n5126) );
OA22X1TS U6196 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[0]), .A1(n5153), .B0(n5113),
.B1(n5126), .Y(n1205) );
OAI22X1TS U6197 ( .A0(n5115), .A1(n3758), .B0(n2286), .B1(n5114), .Y(n5116)
);
OA22X1TS U6198 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[1]), .A1(n5153), .B0(n5116),
.B1(n5126), .Y(n1204) );
OA22X1TS U6199 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[2]), .A1(n5153), .B0(n5126),
.B1(n5117), .Y(n1203) );
AOI2BB2XLTS U6200 ( .B0(n5235), .B1(n5147), .A0N(n5126), .A1N(n5118), .Y(
n1202) );
OA22X1TS U6201 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[4]), .A1(n5120), .B0(n5126),
.B1(n5119), .Y(n1201) );
AOI2BB2XLTS U6202 ( .B0(n5180), .B1(n5147), .A0N(n5126), .A1N(n5121), .Y(
n1200) );
AOI2BB2XLTS U6203 ( .B0(n5181), .B1(n5147), .A0N(n5126), .A1N(n5122), .Y(
n1199) );
AOI2BB2XLTS U6204 ( .B0(n5182), .B1(n5147), .A0N(n5126), .A1N(n5123), .Y(
n1198) );
AOI2BB2XLTS U6205 ( .B0(n5239), .B1(n5147), .A0N(n5126), .A1N(n5124), .Y(
n1197) );
OA22X1TS U6206 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[9]), .A1(n5153), .B0(n5126),
.B1(n5125), .Y(n1196) );
AOI22X1TS U6207 ( .A0(n5128), .A1(n5127), .B0(n5241), .B1(n5039), .Y(n1195)
);
AOI22X1TS U6208 ( .A0(n5130), .A1(n5129), .B0(n5243), .B1(n5099), .Y(n1194)
);
AOI22X1TS U6209 ( .A0(n5153), .A1(n5131), .B0(n5244), .B1(n5039), .Y(n1193)
);
AOI22X1TS U6210 ( .A0(n5153), .A1(n5133), .B0(n5247), .B1(n5099), .Y(n1192)
);
AOI22X1TS U6211 ( .A0(n5136), .A1(n5134), .B0(n5184), .B1(n5147), .Y(n1191)
);
AOI22X1TS U6212 ( .A0(n5136), .A1(n5135), .B0(n5249), .B1(n5147), .Y(n1190)
);
NAND2X2TS U6213 ( .A(n5153), .B(n5137), .Y(n5151) );
AOI2BB2XLTS U6214 ( .B0(n5256), .B1(n5147), .A0N(n5151), .A1N(n5138), .Y(
n1189) );
AOI2BB2XLTS U6215 ( .B0(n5155), .B1(n5147), .A0N(n5151), .A1N(n5139), .Y(
n1188) );
AOI2BB2XLTS U6216 ( .B0(n2299), .B1(n5147), .A0N(n5151), .A1N(n5140), .Y(
n1187) );
OA22X1TS U6217 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[19]), .A1(n5153), .B0(n5151),
.B1(n5141), .Y(n1186) );
OA22X1TS U6218 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[20]), .A1(n5153), .B0(n5151),
.B1(n5142), .Y(n1185) );
OA22X1TS U6219 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[21]), .A1(n5153), .B0(n5151),
.B1(n5143), .Y(n1184) );
AOI2BB2XLTS U6220 ( .B0(n5204), .B1(n5147), .A0N(n5151), .A1N(n5144), .Y(
n1183) );
AOI2BB2XLTS U6221 ( .B0(n5330), .B1(n5147), .A0N(n5151), .A1N(n5145), .Y(
n1182) );
AOI2BB2XLTS U6222 ( .B0(n5351), .B1(n5147), .A0N(n5151), .A1N(n5146), .Y(
n1181) );
OAI22X1TS U6223 ( .A0(n5150), .A1(n3726), .B0(n5149), .B1(n2284), .Y(n5152)
);
OA22X1TS U6224 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[25]), .A1(n5153), .B0(n5152),
.B1(n5151), .Y(n1180) );
CMPR42X1TS U6225 ( .A(DP_OP_501J224_127_5235_n207), .B(
DP_OP_501J224_127_5235_n166), .C(DP_OP_501J224_127_5235_n235), .D(
DP_OP_501J224_127_5235_n200), .ICI(DP_OP_501J224_127_5235_n163), .S(
DP_OP_501J224_127_5235_n161), .ICO(DP_OP_501J224_127_5235_n159), .CO(
DP_OP_501J224_127_5235_n160) );
endmodule
|
`timescale 1ns / 1ps
`include "Defintions.v"
module MiniAlu
(
input wire Clock,
input wire Reset,
output wire [7:0] oLed,
output wire oVGA_HSYNC,
output wire oVGA_VSYNC,
output wire [2:0] oVgaRgb
);
wire [15:0] wIP,wIP_temp;
reg rWriteEnable,rBranchTaken,rVgaWriteEnable;
wire [27:0] wInstruction;
wire [7:0] wSourceAddr0Pre;
reg rFlagCALL;
wire [3:0] wOperation, wOperation_Pre;
reg signed [15:0] rResult;
wire [15:0] wResult_Pre;
wire [7:0] wSourceAddr0,wSourceAddr1,wDestination, wDestination_Pre, wDestOpAnterior0, wDestOpAnterior1;
wire [15:0] wSourceData0,wSourceData1,wIPInitialValue,wImmediateValue;
ROM InstructionRom
(
.iAddress( wIP ),
.oInstruction( wInstruction )
);
RAM_DUAL_READ_PORT DataRam
(
.Clock( Clock ),
.iWriteEnable( rWriteEnable ),
.iReadAddress0( wSourceAddr0Pre ),
.iReadAddress1( wInstruction[15:8] ),
.iWriteAddress( wDestination_Pre ),
.iDataIn( wResult_Pre ),
.oDataOut0( wSourceData0 ),
.oDataOut1( wSourceData1 )
);
wire [2:0] wColorReadData;
reg[2:0] rColorWriteData ;
wire [7:0] wCurrentReadColor ;
reg [7:0] rColorWriteAddress ;
RAM_DUAL_READ_PORT VGARam
(
.Clock( Clock ),
.iWriteEnable( rVgaWriteEnable ),
.iReadAddress0( wCurrentReadColor ), //Goes into VGA controller module
.iReadAddress1( 16'b0 ),
.iWriteAddress( rColorWriteAddress ), //From main MiniAlu switch statement
.iDataIn( rColorWriteData ), //From main MiniAlu switch statement
.oDataOut0( wColorReadData )
);
assign wIPInitialValue = (Reset) ? 8'b0 :((wOperation_Pre==`RET) ? wSourceData0 :wDestination);
assign wIP = (rBranchTaken | (wOperation_Pre==`RET)) ? wIPInitialValue : wIP_temp;
assign wResult_Pre = (wOperation==`CALL) ? wIP_temp : rResult ;
assign wSourceAddr0Pre = (wOperation==`RET) ? 8'd7 : wInstruction[7:0];
assign wDestination_Pre = (rFlagCALL) ? 8'd7 : wDestination ; //wDestination_Pre => iWriteAddress
// FF que retiene la instruccion un cicle, la instruccion es igual.
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFDM
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wOperation),
.Q(wOperation_Pre)
);
UPCOUNTER_POSEDGE IP
(
.Clock( Clock ),
.Reset( Reset | rBranchTaken | (wOperation_Pre==`RET)),
.Initial( wIPInitialValue + 1 ),
.Enable( 1'b1 ),
.Q( wIP_temp )
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 4 ) FFD1
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[27:24]),
.Q(wOperation)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD2
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[7:0]),
.Q(wSourceAddr0)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD3
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[15:8]),
.Q(wSourceAddr1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD4
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[23:16]),
.Q(wDestination)
);
reg rFFLedEN;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FF_LEDS
(
.Clock(Clock),
.Reset(Reset),
.Enable( rFFLedEN ),
.D( wSourceData1 ),
.Q( oLed )
);
wire [7:0] rRmul1, rRmux1, rRmux4;
wire [15:0] rRgmul1;
reg[7:0] rLCDData;
reg oSetupReady;
reg oWriteDone;
reg[3:0] oLCD_Data;
reg rDoWrite;
wire oLCD_Enabled,oLCD_RegisterSelect,oLCD_StrataFlashControl, oLCD_ReadWrite;
arrayMUL mul1(wSourceData0,wSourceData1,rRmul1);
arrayMUL_GEN mg1(wSourceData0,wSourceData1,rRgmul1);
muxMUL mx1(wSourceData0,wSourceData1,rRmux1);
multiplicador4bits mx4 (wSourceData0,wSourceData1,rRmux4);
//Module_LCD_Control control1(Clock,Reset,oLCD_Enabled,oLCD_RegisterSelect,oLCD_StrataFlashControl, oLCD_ReadWrite,rDoWrite,rLCDData,oSetupReady,oWriteDone,oLCD_Data);
assign wImmediateValue = {wSourceAddr1,wSourceAddr0};
reg rPreReset;
reg rFlag;
wire [2:0]wClock25Mhz;
always @ (posedge Clock )
begin
if (rFlag)
begin
rPreReset = 1'b0;
end
else
begin
rPreReset = 1'b1;
rFlag = 1'b1;
end
end
UPCOUNTER_POSEDGE #(2) CLOCK25
(
.Clock( Clock ),
.Reset( rPreReset ),
.Initial( 0 ),
.Enable( 1'b1 ),
.Q( wClock25Mhz )
);
/*VGA_controller vga1(
.pixel_Clock(wClock25Mhz[0]),
.pixel_reset(Reset),
.pre_reset(rPreReset),
.oVGA_HSYNC(oVGA_HSYNC),
.oVGA_VSYNC(oVGA_VSYNC),
.oVGA_RGB(oVgaRgb)
);*/
wire [9:0] uselessx,uselessy;
VGA_Controller_Josue c1(
.Clock25(wClock25Mhz[0]),
.Reset(Reset),
//.iColorCuadro(3'b110),
.iRGB( 3'b001),
.H_Sync(oVGA_HSYNC),
.V_Sync(oVGA_VSYNC),
.oRGB(oVgaRgb),
.Cont_X(uselessx),
.Cont_Y(uselessy)
);
always @ ( * )
begin
case (wOperation)
//-------------------------------------
`NOP:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b0;
rFlagCALL <= 1'b0;
rResult <= 0;
end
//-------------------------------------
//-------------------------------------
`LCD:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b0;
rFlagCALL <= 1'b0;
rResult <= 0;
rLCDData=wSourceData1;
rDoWrite=1'b1;
end
//-------------------------------------
`ADD:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rFlagCALL <= 1'b0;
rResult <= wSourceData1 + wSourceData0;
//$display("%dns ADD %h + %h = %h",$time,wSourceData0,wSourceData1,rResult);
end
//-------------------------------------
`CMP:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rFlagCALL <= 1'b0;
rResult <= -wSourceData1;
// $display("%dns CMP %h = %h",$time,wSourceData1,rResult);
end
//-------------------------------------
`STO:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b1;
rBranchTaken <= 1'b0;
rFlagCALL <= 1'b0;
rResult <= wImmediateValue;
end
//-------------------------------------
`BLE:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rFlagCALL <= 1'b0;
rResult <= 0;
if (wSourceData1 <= wSourceData0 )
rBranchTaken <= 1'b1;
else
rBranchTaken <= 1'b0;
end
//-------------------------------------
`BLCD1:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rFlagCALL <= 1'b0;
rResult <= 0;
if (!oSetupReady )
rBranchTaken <= 1'b1;
else
rBranchTaken <= 1'b0;
end
//----------------------
/*`BLCD2:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rFlagCALL <= 1'b0;
rResult <= 0;
if (wpWriteDone )
begin
rDoWrite <=1'b0;
rBranchTaken <= 1'b0;
end
else
rBranchTaken <= 1'b1;
end*/
//------------------------
`JMP:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rFlagCALL <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b1;
end
//-------------------------------------
`LED:
begin
rFFLedEN <= 1'b1;
rWriteEnable <= 1'b0;
rFlagCALL <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
end
//-------------------------------------
`SMUL:
begin
rVgaWriteEnable <= 1'b1;
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b1;
rFlagCALL <= 1'b0;
rResult <= wSourceData0*wSourceData1;
rBranchTaken <= 1'b0;
end
//-------------------------------------
`IMUL:
begin
rVgaWriteEnable <= 1'b1;
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b1;
rFlagCALL <= 1'b0;
rResult <= rRmul1;
// arrayMUL mul1(wSourceData0,wSourceData1,rResult);
rBranchTaken <= 1'b0;
end
//-------------------------------------
`gIMUL:
begin
rVgaWriteEnable <= 1'b1;
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b1;
rFlagCALL <= 1'b0;
rResult <= rRgmul1;
// arrayMUL_GEN mg1(wSourceData0,wSourceData1,rResult);
rBranchTaken <= 1'b0;
$display("%dns gIMUL %h * %h = %h",$time,wSourceData0,wSourceData1,rResult);
end
//-------------------------------------
`IMUL2:
begin
rVgaWriteEnable <= 1'b1;
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rFlagCALL <= 1'b0;
rResult <= rRmux1;
// muxMUL mx1(wSourceData0,wSourceData1,rRmux1);
end
//-------------------------------------
`IMUX4:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rFlagCALL <= 1'b0;
rResult <= rRmux4;
rVgaWriteEnable <= 1'b1;
// multiplicador4bits mx4 (wSourceData0,wSourceData1,rRmux4);
end
//-------------------------------------
`VGA:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= 1'b0;
rVgaWriteEnable <= 1'b1;
rColorWriteData <={wDestination[2],wDestination[1],wDestination[0]};
rColorWriteAddress <= wSourceAddr0;
// multiplicador4bits mx4 (wSourceData0,wSourceData1,rRmux4);
end
//-------------------------------------
`CALL:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= 0;
rFlagCALL <= 1'b1;
rBranchTaken <= 1'b1;
rVgaWriteEnable <= 1'b0;
end
//-------------------------------------
`RET:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rFlagCALL <= 1'b0;
rBranchTaken <= 1'b1;
end
//-------------------------------------
default:
begin
rFFLedEN <= 1'b1;
rWriteEnable <= 1'b0;
rFlagCALL <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
end
//-------------------------------------
endcase
end
endmodule
|
module var20_multi (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, valid);
input A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T;
output valid;
wire [8:0] min_value = 9'd120;
wire [8:0] max_weight = 9'd60;
wire [8:0] max_volume = 9'd60;
wire [8:0] total_value =
A * 9'd4
+ B * 9'd8
+ C * 9'd0
+ D * 9'd20
+ E * 9'd10
+ F * 9'd12
+ G * 9'd18
+ H * 9'd14
+ I * 9'd6
+ J * 9'd15
+ K * 9'd30
+ L * 9'd8
+ M * 9'd16
+ N * 9'd18
+ O * 9'd18
+ P * 9'd14
+ Q * 9'd7
+ R * 9'd7
+ S * 9'd29
+ T * 9'd23;
wire [8:0] total_weight =
A * 9'd28
+ B * 9'd8
+ C * 9'd27
+ D * 9'd18
+ E * 9'd27
+ F * 9'd28
+ G * 9'd6
+ H * 9'd1
+ I * 9'd20
+ J * 9'd0
+ K * 9'd5
+ L * 9'd13
+ M * 9'd8
+ N * 9'd14
+ O * 9'd22
+ P * 9'd12
+ Q * 9'd23
+ R * 9'd26
+ S * 9'd1
+ T * 9'd22;
wire [8:0] total_volume =
A * 9'd27
+ B * 9'd27
+ C * 9'd4
+ D * 9'd4
+ E * 9'd0
+ F * 9'd24
+ G * 9'd4
+ H * 9'd20
+ I * 9'd12
+ J * 9'd15
+ K * 9'd5
+ L * 9'd2
+ M * 9'd9
+ N * 9'd28
+ O * 9'd19
+ P * 9'd18
+ Q * 9'd30
+ R * 9'd12
+ S * 9'd28
+ T * 9'd13;
assign valid = ((total_value >= min_value) && (total_weight <= max_weight) && (total_volume <= max_volume));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A311OI_SYMBOL_V
`define SKY130_FD_SC_LP__A311OI_SYMBOL_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a311oi (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A311OI_SYMBOL_V
|
`define BigEndianCPU 1
module dm_4k (addr, din, byteExt, wEn, clk, dout);
input [11:0] addr;
input [31:0] din;
input [1:0] byteExt;
input [1:0] wEn;
input clk;
output reg [31:0] dout;
reg [31:0] dm [1023:0];// 32-bit*1024;
wire [1:0] byteSel;
wire [9:0] gpAddr;
reg [7:0] byteIn;
reg [31:0] tmpReg;
assign byteSel = addr[1:0] ^ 2'b11;// Big endian.
assign gpAddr = addr[11:2];
always @ ( * ) begin
if (byteExt == 2'b01 || byteExt == 2'b00) begin// Load byte.
case (byteSel)
2'b00: byteIn <= dm[gpAddr][7:0];
2'b01: byteIn <= dm[gpAddr][15:8];
2'b10: byteIn <= dm[gpAddr][23:16];
2'b11: byteIn <= dm[gpAddr][31:24];
endcase
case (byteExt)// Embedded extender.
2'b00: dout <= {{24{1'b0}}, byteIn};// Logical Cal;
2'b01: dout <= {{24{byteIn[7]}}, byteIn};// Arithmetic Cal;
endcase
end else begin
dout = dm[gpAddr][31:0];// Load word.
end
end
always @ ( posedge clk ) begin// Write;
if (wEn == 2'b01) begin
if (byteExt == 2'b10) begin// Store byte.
tmpReg = dm[gpAddr][31:0];
case (byteSel)
2'b00: tmpReg[7:0] = din[7:0];
2'b01: tmpReg[15:8] = din[7:0];
2'b10: tmpReg[23:16] = din[7:0];
2'b11: tmpReg[31:24] = din[7:0];
endcase
dm[gpAddr][31:0] = tmpReg[31:0];
end else begin// Store word.
dm[gpAddr][31:0] = din[31:0];
end
end
end
endmodule // 4K Data Memeory;
|
`timescale 1ns / 1ps
`include "Defintions.v"
module MiniAlu
(
input wire Clock,
input wire Reset,
output wire [7:0] oLed,
output wire [3:0] oLCD_Data,
output wire oLCD_Enabled,
output wire oLCD_RegisterSelect,
output wire oLCD_ReadWrite,
output wire oLCD_StrataFlashControl
);
//************************************************************
//Registros internos necesarios
//************************************************************
reg oLCD_reset; //Reset del LCD_Controller
reg oLCD_writeEN; // Señal de envío de Datos al LCD_Controller
reg [3:0] iLCD_data; //Datos a enviar al LCD
wire iLCD_response;//Respuesta del LCD
wire [15:0] wIP,wIP_temp,IMUL_Result;
wire [7:0] imul_result;
reg Subroutine_Flag;
reg Return_Flag;
wire [15:0] wReturn_Sub;
reg rWriteEnable,rBranchTaken;
wire [27:0] wInstruction;
wire [3:0] wOperation;
reg signed [32:0] rResult;
wire [7:0] wSourceAddr0,wSourceAddr1,wDestination;
wire signed [15:0] wSourceData0,wSourceData1,wImmediateValue;
wire [15:0] wIPInitialValue;
wire [15:0] oIMUL2;
//**********************************************
//Instacia del LCD_Controller
//**********************************************
LCD_controler controller_one(
.clk(Clock),
.iLCD_data(iLCD_data),
.iLCD_reset(Reset),
.iLCD_writeEN(oLCD_writeEN),
.oLCD_response(iLCD_response),
.oLCD_Data(oLCD_Data),
.oLCD_Enabled(oLCD_Enabled),
.oLCD_RegisterSelect(oLCD_RegisterSelect),
.oLCD_ReadWrite(oLCD_ReadWrite),
.oLCD_StrataFlashControl(oLCD_StrataFlashControl)
);
IMUL2 Multiply4(
.iSourceData0(wSourceData0),
.iSourceData1(wSourceData1),
.oResult(oIMUL2)
);
ROM InstructionRom
(
.iAddress( wIP ),
.oInstruction( wInstruction )
);
RAM_DUAL_READ_PORT DataRam
(
.Clock( Clock ),
.iWriteEnable( rWriteEnable ),
.iReadAddress0( wInstruction[7:0] ),
.iReadAddress1( wInstruction[15:8] ),
.iWriteAddress( wDestination ),
.iDataIn( rResult ),
.oDataOut0( wSourceData0 ),
.oDataOut1( wSourceData1 )
);
//assign oLCD_reset = Reset;
assign wIPInitialValue = (Reset) ? 8'b0 : (Return_Flag? wReturn_Sub:wDestination);
UPCOUNTER_POSEDGE IP
(
.Clock( Clock ),
.Reset( Reset | rBranchTaken ),
.Initial( wIPInitialValue + 1 ),
.Enable( 1'b1 ),
.Q( wIP_temp )
);
assign wIP = (rBranchTaken) ? (Return_Flag? wReturn_Sub:wIPInitialValue): wIP_temp;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 4 ) FFD1
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[27:24]),
.Q(wOperation)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD2
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[7:0]),
.Q(wSourceAddr0)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD3
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[15:8]),
.Q(wSourceAddr1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD4
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[23:16]),
.Q(wDestination)
);
reg rFFLedEN;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FF_LEDS
(
.Clock(Clock),
.Reset(Reset),
.Enable( rFFLedEN ),
.D( wSourceData1 ),
.Q( oLed )
);
//***************************** FFD Subroutine **********************************
FFD_POSEDGE_SYNCRONOUS_RESET # ( 16 ) FFDSub
(
.Clock(Subroutine_Flag),
.Reset(Reset),
.Enable(1'b1),
.D(wIP_temp),
.Q(wReturn_Sub)
);
//************************************************************************
//***************************** IMUL16 **********************************
IMUL16 #(16) MULT16
(
.A(wSourceData0),
.B(wSourceData1),
.oResult(IMUL_Result)
);
//************************************************************************
mult imultiplier( .opA(wSourceData0), .opB(wSourceData1), .result(imul_result));
assign wImmediateValue = {wSourceAddr1,wSourceAddr0};
always @ ( * )
begin
case (wOperation)
//-------------------------------------
`NOP:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 1'b0;
oLCD_writeEN <= 1'b0;
Subroutine_Flag <=1'b0;
Return_Flag <=1'b0;
end
//-------------------------------------
`ADD:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
oLCD_writeEN <=1'b0;
rResult <= wSourceData1 + wSourceData0;
Subroutine_Flag <=1'b0;
Return_Flag <=1'b0;
end
//-------------------------------------
`SUB:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
oLCD_writeEN <= 1'b0;
rResult <= wSourceData1 - wSourceData0;
Subroutine_Flag <=1'b0;
Return_Flag <=1'b0;
end
//-------------------------------------
`BRANCH_IF_NSYNC:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
if (iLCD_response)
rBranchTaken <= 1'b1;
else
rBranchTaken <= 1'b0;
oLCD_writeEN <= 1'b1;
end
//-------------------------------------
`LCD: // Juan
begin
rWriteEnable <= 1'b0;
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
iLCD_data <= wSourceData1[7:4];//Manda Parte Alta
oLCD_writeEN <= 1'b1;
rResult <= 1'b0;
end
//-------------------------------------
`SLH: // Juan
begin
rWriteEnable <= 1'b0;
rFFLedEN <= 1'b0;
iLCD_data <= wSourceData1[3:0];//Manda Parte Baja
oLCD_writeEN <= 1'b1;
rBranchTaken <= 1'b0;
rResult <=0;
Subroutine_Flag <=1'b0;
Return_Flag <=1'b0;
end
//-------------------------------------
`STO:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b1;
rBranchTaken <= 1'b0;
oLCD_writeEN <= 1'b0;
rResult <= wImmediateValue;
Subroutine_Flag <=1'b0;
Return_Flag <=1'b0;
end
//-------------------------------------
`BLE:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 1'b0;
oLCD_writeEN <= 1'b0;
Subroutine_Flag <=1'b0;
Return_Flag <=1'b0;
if (wSourceData1 <= wSourceData0 )
rBranchTaken <= 1'b1;
else
rBranchTaken <= 1'b0;
end
//-------------------------------------
`JMP:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
oLCD_writeEN <= 1'b0;
rBranchTaken <= 1'b1;
Subroutine_Flag <=1'b0;
Return_Flag <=1'b0;
end
//-------------------------------------
`LED:
begin
rFFLedEN <= 1'b1;
rWriteEnable <= 1'b0;
rResult <= 0;
oLCD_writeEN <= 1'b0;
rBranchTaken <= 1'b0;
Subroutine_Flag <= 1'b0;
Return_Flag <= 1'b0;
end
//-------------------------------------
`CALL:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b1;
rWriteEnable <= 1'b0;
Subroutine_Flag <=1'b1;
Return_Flag <=1'b0;
rResult <= 0;
oLCD_writeEN <= 1'b0;
end
//-------------------------------------
`RET:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b1;
rWriteEnable <= 1'b0;
Subroutine_Flag <=1'b0;
Return_Flag <=1'b1;
rResult <= 0;
oLCD_writeEN <= 1'b0;
end
//-------------------------------------
`SMUL:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= wSourceData1 * wSourceData0;
oLCD_writeEN <= 1'b0;
end
//-------------------------------------
default:
begin
rFFLedEN <= 1'b1;
rWriteEnable <= 1'b0;
rResult <= 0;
oLCD_writeEN <= 1'b0;
rBranchTaken <= 1'b0;
Subroutine_Flag <=1'b0;
Return_Flag <=1'b0;
end
//-------------------------------------
endcase
end
endmodule
|
// file: CLK_25Mhz.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1____25.185______0.000______50.0______373.434____265.254
// CLK_OUT2____15.111______0.000______50.0______411.007____265.254
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "CLK_25Mhz,clk_wiz_v3_6,{component_name=CLK_25Mhz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=2,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}" *)
module CLK_25Mhz
(// Clock in ports
input CLK_IN,
// Clock out ports
output CLK_OUT,
output CLK_OUTSYS
);
// Input buffering
//------------------------------------
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN));
// Clocking primitive
//------------------------------------
// Instantiation of the PLL primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire locked_unused;
wire clkfbout;
wire clkfbout_buf;
wire clkout2_unused;
wire clkout3_unused;
wire clkout4_unused;
wire clkout5_unused;
PLL_BASE
#(.BANDWIDTH ("OPTIMIZED"),
.CLK_FEEDBACK ("CLKFBOUT"),
.COMPENSATION ("SYSTEM_SYNCHRONOUS"),
.DIVCLK_DIVIDE (5),
.CLKFBOUT_MULT (34),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (27),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DIVIDE (45),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKIN_PERIOD (10.000),
.REF_JITTER (0.010))
pll_base_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKOUT0 (clkout0),
.CLKOUT1 (clkout1),
.CLKOUT2 (clkout2_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.LOCKED (locked_unused),
.RST (1'b0),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN (clkin1));
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf),
.I (clkfbout));
BUFG clkout1_buf
(.O (CLK_OUT),
.I (clkout0));
BUFG clkout2_buf
(.O (CLK_OUTSYS),
.I (clkout1));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR2B_BLACKBOX_V
`define SKY130_FD_SC_LS__OR2B_BLACKBOX_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__or2b (
X ,
A ,
B_N
);
output X ;
input A ;
input B_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR2B_BLACKBOX_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Mon Sep 18 12:05:38 2017
// Host : PC4719 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.v
// Design : ila_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k160tffg676-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[31:0],probe3[31:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [31:0]probe2;
input [31:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [0:0]probe7;
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.58f
// \ \ Application: netgen
// / / Filename: gte_float32_float32_bool.v
// /___/ /\ Timestamp: Wed Jan 27 16:32:30 2016
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/jhegarty/lol/ipcore_dir/tmp/_cg/gte_float32_float32_bool.ngc /home/jhegarty/lol/ipcore_dir/tmp/_cg/gte_float32_float32_bool.v
// Device : 7z100ffg900-2
// Input file : /home/jhegarty/lol/ipcore_dir/tmp/_cg/gte_float32_float32_bool.ngc
// Output file : /home/jhegarty/lol/ipcore_dir/tmp/_cg/gte_float32_float32_bool.v
// # of Modules : 1
// Design Name : gte_float32_float32_bool
// Xilinx : /opt/Xilinx/14.5/ISE_DS/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module gte_float32_float32_bool (
CLK, ce, inp, out
);
parameter INSTANCE_NAME="INST";
input wire CLK;
input wire ce;
input [63 : 0] inp;
output [0:0] out;
wire clk;
assign clk=CLK;
wire [31:0] a;
wire [31:0] b;
wire [0:0] result;
assign a = inp[31:0];
assign b = inp[63:32];
assign out = result;
wire \U0/op_inst/FLT_PT_OP/COMP_OP.SPD.OP/MET_REG/RTL.delay<0>_0 ;
wire sig00000001;
wire sig00000002;
wire sig00000003;
wire sig00000004;
wire sig00000005;
wire sig00000006;
wire sig00000007;
wire sig00000008;
wire sig00000009;
wire sig0000000a;
wire sig0000000b;
wire sig0000000c;
wire sig0000000d;
wire sig0000000e;
wire sig0000000f;
wire sig00000010;
wire sig00000011;
wire sig00000012;
wire sig00000013;
wire sig00000014;
wire sig00000015;
wire sig00000016;
wire sig00000017;
wire sig00000018;
wire sig00000019;
wire sig0000001a;
wire sig0000001b;
wire sig0000001c;
wire sig0000001d;
wire sig0000001e;
wire sig0000001f;
wire sig00000020;
wire sig00000021;
wire sig00000022;
wire sig00000023;
wire sig00000024;
wire sig00000025;
wire sig00000026;
wire sig00000027;
wire sig00000028;
wire sig00000029;
wire sig0000002a;
wire sig0000002b;
wire sig0000002c;
wire sig0000002d;
wire sig0000002e;
wire sig0000002f;
wire sig00000030;
wire sig00000031;
wire sig00000032;
wire sig00000033;
wire sig00000034;
wire sig00000035;
wire sig00000036;
wire sig00000037;
wire sig00000038;
wire sig00000039;
wire sig0000003a;
wire sig0000003b;
wire sig0000003c;
wire sig0000003d;
wire sig0000003e;
wire sig0000003f;
wire sig00000040;
wire sig00000041;
wire sig00000042;
wire sig00000043;
wire sig00000044;
wire sig00000045;
wire sig00000046;
wire sig00000047;
wire sig00000048;
wire sig00000049;
wire sig0000004a;
wire sig0000004b;
wire sig0000004c;
wire sig0000004d;
wire sig0000004e;
wire sig0000004f;
wire sig00000050;
wire sig00000051;
wire sig00000052;
wire sig00000053;
wire sig00000054;
wire sig00000055;
wire sig00000056;
wire sig00000057;
wire sig00000058;
wire sig00000059;
wire sig0000005a;
wire sig0000005b;
wire sig0000005c;
wire sig0000005d;
wire sig0000005e;
wire sig0000005f;
wire sig00000060;
wire sig00000061;
wire sig00000062;
wire sig00000063;
wire sig00000064;
wire sig00000065;
wire sig00000066;
wire sig00000067;
wire sig00000068;
wire sig00000069;
wire sig0000006a;
wire sig0000006b;
wire sig0000006c;
wire sig0000006d;
wire sig0000006e;
wire sig0000006f;
wire sig00000070;
assign
result[0] = \U0/op_inst/FLT_PT_OP/COMP_OP.SPD.OP/MET_REG/RTL.delay<0>_0 ;
VCC blk00000001 (
.P(sig00000001)
);
GND blk00000002 (
.G(sig00000002)
);
FDE #(
.INIT ( 1'b0 ))
blk00000003 (
.C(clk),
.CE(ce),
.D(sig00000006),
.Q(sig00000019)
);
MUXCY blk00000004 (
.CI(sig00000007),
.DI(sig00000002),
.S(sig00000003),
.O(sig00000006)
);
MUXCY blk00000005 (
.CI(sig00000008),
.DI(sig00000002),
.S(sig00000005),
.O(sig00000007)
);
MUXCY blk00000006 (
.CI(sig00000001),
.DI(sig00000002),
.S(sig00000004),
.O(sig00000008)
);
MUXCY blk00000007 (
.CI(sig00000016),
.DI(sig00000002),
.S(sig00000010),
.O(sig00000009)
);
MUXCY blk00000008 (
.CI(sig00000009),
.DI(sig00000002),
.S(sig0000000f),
.O(sig0000000a)
);
MUXCY blk00000009 (
.CI(sig00000018),
.DI(sig00000002),
.S(sig0000000e),
.O(sig0000000b)
);
MUXCY blk0000000a (
.CI(sig0000000b),
.DI(sig00000002),
.S(sig0000000d),
.O(sig0000000c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000000b (
.C(clk),
.CE(ce),
.D(sig00000012),
.Q(sig00000013)
);
FDE #(
.INIT ( 1'b0 ))
blk0000000c (
.C(clk),
.CE(ce),
.D(sig00000011),
.Q(\U0/op_inst/FLT_PT_OP/COMP_OP.SPD.OP/MET_REG/RTL.delay<0>_0 )
);
FDE #(
.INIT ( 1'b0 ))
blk0000000d (
.C(clk),
.CE(ce),
.D(sig0000000a),
.Q(sig00000015)
);
FDE #(
.INIT ( 1'b0 ))
blk0000000e (
.C(clk),
.CE(ce),
.D(sig0000000c),
.Q(sig00000017)
);
FDE #(
.INIT ( 1'b0 ))
blk0000000f (
.C(clk),
.CE(ce),
.D(sig00000001),
.Q(sig0000001a)
);
MUXCY blk00000010 (
.CI(sig00000028),
.DI(sig00000002),
.S(sig0000001c),
.O(sig00000027)
);
MUXCY blk00000011 (
.CI(sig00000029),
.DI(sig00000002),
.S(sig0000001d),
.O(sig00000028)
);
MUXCY blk00000012 (
.CI(sig0000002a),
.DI(sig00000002),
.S(sig0000001e),
.O(sig00000029)
);
MUXCY blk00000013 (
.CI(sig0000002b),
.DI(sig00000002),
.S(sig0000001f),
.O(sig0000002a)
);
MUXCY blk00000014 (
.CI(sig0000002c),
.DI(sig00000002),
.S(sig00000020),
.O(sig0000002b)
);
MUXCY blk00000015 (
.CI(sig0000002d),
.DI(sig00000002),
.S(sig00000021),
.O(sig0000002c)
);
MUXCY blk00000016 (
.CI(sig0000002e),
.DI(sig00000002),
.S(sig00000022),
.O(sig0000002d)
);
MUXCY blk00000017 (
.CI(sig0000002f),
.DI(sig00000002),
.S(sig00000023),
.O(sig0000002e)
);
MUXCY blk00000018 (
.CI(sig00000030),
.DI(sig00000002),
.S(sig00000024),
.O(sig0000002f)
);
MUXCY blk00000019 (
.CI(sig00000031),
.DI(sig00000002),
.S(sig00000025),
.O(sig00000030)
);
MUXCY blk0000001a (
.CI(sig00000001),
.DI(sig00000002),
.S(sig00000026),
.O(sig00000031)
);
FDE #(
.INIT ( 1'b0 ))
blk0000001b (
.C(clk),
.CE(ce),
.D(sig00000027),
.Q(sig0000001b)
);
MUXCY blk0000001c (
.CI(sig00000002),
.DI(sig00000001),
.S(sig00000037),
.O(sig00000032)
);
MUXCY blk0000001d (
.CI(sig00000032),
.DI(sig00000001),
.S(sig00000036),
.O(sig00000033)
);
MUXCY blk0000001e (
.CI(sig00000033),
.DI(sig00000001),
.S(sig00000035),
.O(sig00000034)
);
MUXCY blk0000001f (
.CI(sig00000034),
.DI(sig00000001),
.S(sig00000038),
.O(sig00000016)
);
MUXCY blk00000020 (
.CI(sig00000002),
.DI(sig00000001),
.S(sig0000003e),
.O(sig00000039)
);
MUXCY blk00000021 (
.CI(sig00000039),
.DI(sig00000001),
.S(sig0000003d),
.O(sig0000003a)
);
MUXCY blk00000022 (
.CI(sig0000003a),
.DI(sig00000001),
.S(sig0000003c),
.O(sig0000003b)
);
MUXCY blk00000023 (
.CI(sig0000003b),
.DI(sig00000001),
.S(sig0000003f),
.O(sig00000018)
);
MUXCY blk00000024 (
.CI(sig00000061),
.DI(sig00000040),
.S(sig00000041),
.O(sig00000060)
);
MUXCY blk00000025 (
.CI(sig00000062),
.DI(sig00000042),
.S(sig00000043),
.O(sig00000061)
);
MUXCY blk00000026 (
.CI(sig00000063),
.DI(sig00000044),
.S(sig00000045),
.O(sig00000062)
);
MUXCY blk00000027 (
.CI(sig00000064),
.DI(sig00000046),
.S(sig00000047),
.O(sig00000063)
);
MUXCY blk00000028 (
.CI(sig00000065),
.DI(sig00000048),
.S(sig00000049),
.O(sig00000064)
);
MUXCY blk00000029 (
.CI(sig00000066),
.DI(sig0000004a),
.S(sig0000004b),
.O(sig00000065)
);
MUXCY blk0000002a (
.CI(sig00000067),
.DI(sig0000004c),
.S(sig0000004d),
.O(sig00000066)
);
MUXCY blk0000002b (
.CI(sig00000068),
.DI(sig0000004e),
.S(sig0000004f),
.O(sig00000067)
);
MUXCY blk0000002c (
.CI(sig00000069),
.DI(sig00000050),
.S(sig00000051),
.O(sig00000068)
);
MUXCY blk0000002d (
.CI(sig0000006a),
.DI(sig00000052),
.S(sig00000053),
.O(sig00000069)
);
MUXCY blk0000002e (
.CI(sig0000006b),
.DI(sig00000054),
.S(sig00000055),
.O(sig0000006a)
);
MUXCY blk0000002f (
.CI(sig0000006c),
.DI(sig00000056),
.S(sig00000057),
.O(sig0000006b)
);
MUXCY blk00000030 (
.CI(sig0000006d),
.DI(sig00000058),
.S(sig00000059),
.O(sig0000006c)
);
MUXCY blk00000031 (
.CI(sig0000006e),
.DI(sig0000005a),
.S(sig0000005b),
.O(sig0000006d)
);
MUXCY blk00000032 (
.CI(sig0000006f),
.DI(sig0000005c),
.S(sig0000005d),
.O(sig0000006e)
);
MUXCY blk00000033 (
.CI(sig00000002),
.DI(sig0000005e),
.S(sig0000005f),
.O(sig0000006f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000034 (
.C(clk),
.CE(ce),
.D(sig00000060),
.Q(sig00000014)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000035 (
.I0(a[27]),
.I1(a[28]),
.I2(a[29]),
.I3(a[30]),
.O(sig00000003)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000036 (
.I0(b[23]),
.I1(b[24]),
.I2(b[25]),
.I3(b[26]),
.I4(b[27]),
.I5(b[28]),
.O(sig00000004)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000037 (
.I0(b[29]),
.I1(b[30]),
.I2(a[23]),
.I3(a[24]),
.I4(a[25]),
.I5(a[26]),
.O(sig00000005)
);
LUT2 #(
.INIT ( 4'h8 ))
blk00000038 (
.I0(a[29]),
.I1(a[30]),
.O(sig0000000d)
);
LUT6 #(
.INIT ( 64'h8000000000000000 ))
blk00000039 (
.I0(a[23]),
.I1(a[24]),
.I2(a[25]),
.I3(a[26]),
.I4(a[27]),
.I5(a[28]),
.O(sig0000000e)
);
LUT2 #(
.INIT ( 4'h8 ))
blk0000003a (
.I0(b[29]),
.I1(b[30]),
.O(sig0000000f)
);
LUT6 #(
.INIT ( 64'h8000000000000000 ))
blk0000003b (
.I0(b[23]),
.I1(b[24]),
.I2(b[25]),
.I3(b[26]),
.I4(b[27]),
.I5(b[28]),
.O(sig00000010)
);
LUT2 #(
.INIT ( 4'h8 ))
blk0000003c (
.I0(a[31]),
.I1(b[31]),
.O(sig00000012)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk0000003d (
.I0(a[27]),
.I1(b[27]),
.I2(a[29]),
.I3(b[29]),
.I4(a[28]),
.I5(b[28]),
.O(sig0000001d)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk0000003e (
.I0(a[24]),
.I1(b[24]),
.I2(a[26]),
.I3(b[26]),
.I4(a[25]),
.I5(b[25]),
.O(sig0000001e)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk0000003f (
.I0(a[21]),
.I1(b[21]),
.I2(a[23]),
.I3(b[23]),
.I4(a[22]),
.I5(b[22]),
.O(sig0000001f)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000040 (
.I0(a[18]),
.I1(b[18]),
.I2(a[20]),
.I3(b[20]),
.I4(a[19]),
.I5(b[19]),
.O(sig00000020)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000041 (
.I0(a[15]),
.I1(b[15]),
.I2(a[17]),
.I3(b[17]),
.I4(a[16]),
.I5(b[16]),
.O(sig00000021)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000042 (
.I0(a[12]),
.I1(b[12]),
.I2(a[14]),
.I3(b[14]),
.I4(a[13]),
.I5(b[13]),
.O(sig00000022)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000043 (
.I0(a[10]),
.I1(b[10]),
.I2(a[9]),
.I3(b[9]),
.I4(a[11]),
.I5(b[11]),
.O(sig00000023)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000044 (
.I0(a[6]),
.I1(b[6]),
.I2(a[8]),
.I3(b[8]),
.I4(a[7]),
.I5(b[7]),
.O(sig00000024)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000045 (
.I0(a[3]),
.I1(b[3]),
.I2(a[5]),
.I3(b[5]),
.I4(a[4]),
.I5(b[4]),
.O(sig00000025)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000046 (
.I0(a[31]),
.I1(b[31]),
.I2(a[30]),
.I3(b[30]),
.O(sig0000001c)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000047 (
.I0(a[0]),
.I1(b[0]),
.I2(a[2]),
.I3(b[2]),
.I4(a[1]),
.I5(b[1]),
.O(sig00000026)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000048 (
.I0(b[12]),
.I1(b[13]),
.I2(b[14]),
.I3(b[15]),
.I4(b[16]),
.I5(b[17]),
.O(sig00000035)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000049 (
.I0(b[6]),
.I1(b[7]),
.I2(b[8]),
.I3(b[9]),
.I4(b[10]),
.I5(b[11]),
.O(sig00000036)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000004a (
.I0(b[0]),
.I1(b[1]),
.I2(b[2]),
.I3(b[3]),
.I4(b[4]),
.I5(b[5]),
.O(sig00000037)
);
LUT5 #(
.INIT ( 32'h00000001 ))
blk0000004b (
.I0(b[18]),
.I1(b[19]),
.I2(b[20]),
.I3(b[21]),
.I4(b[22]),
.O(sig00000038)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000004c (
.I0(a[12]),
.I1(a[13]),
.I2(a[14]),
.I3(a[15]),
.I4(a[16]),
.I5(a[17]),
.O(sig0000003c)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000004d (
.I0(a[6]),
.I1(a[7]),
.I2(a[8]),
.I3(a[9]),
.I4(a[10]),
.I5(a[11]),
.O(sig0000003d)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000004e (
.I0(a[0]),
.I1(a[1]),
.I2(a[2]),
.I3(a[3]),
.I4(a[4]),
.I5(a[5]),
.O(sig0000003e)
);
LUT5 #(
.INIT ( 32'h00000001 ))
blk0000004f (
.I0(a[18]),
.I1(a[19]),
.I2(a[20]),
.I3(a[21]),
.I4(a[22]),
.O(sig0000003f)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000050 (
.I0(a[19]),
.I1(b[19]),
.I2(a[18]),
.I3(b[18]),
.O(sig0000004d)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000051 (
.I0(a[17]),
.I1(b[17]),
.I2(a[16]),
.I3(b[16]),
.O(sig0000004f)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000052 (
.I0(a[15]),
.I1(b[15]),
.I2(a[14]),
.I3(b[14]),
.O(sig00000051)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000053 (
.I0(a[13]),
.I1(b[13]),
.I2(a[12]),
.I3(b[12]),
.O(sig00000053)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000054 (
.I0(a[11]),
.I1(b[11]),
.I2(a[10]),
.I3(b[10]),
.O(sig00000055)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000055 (
.I0(a[9]),
.I1(b[9]),
.I2(a[8]),
.I3(b[8]),
.O(sig00000057)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000056 (
.I0(a[7]),
.I1(b[7]),
.I2(a[6]),
.I3(b[6]),
.O(sig00000059)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000057 (
.I0(a[5]),
.I1(b[5]),
.I2(a[4]),
.I3(b[4]),
.O(sig0000005b)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000058 (
.I0(a[3]),
.I1(b[3]),
.I2(a[2]),
.I3(b[2]),
.O(sig0000005d)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000059 (
.I0(a[31]),
.I1(b[31]),
.I2(a[30]),
.I3(b[30]),
.O(sig00000041)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000005a (
.I0(a[29]),
.I1(b[29]),
.I2(a[28]),
.I3(b[28]),
.O(sig00000043)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000005b (
.I0(a[27]),
.I1(b[27]),
.I2(a[26]),
.I3(b[26]),
.O(sig00000045)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000005c (
.I0(a[25]),
.I1(b[25]),
.I2(a[24]),
.I3(b[24]),
.O(sig00000047)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000005d (
.I0(a[23]),
.I1(b[23]),
.I2(a[22]),
.I3(b[22]),
.O(sig00000049)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000005e (
.I0(a[21]),
.I1(b[21]),
.I2(a[20]),
.I3(b[20]),
.O(sig0000004b)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000005f (
.I0(a[1]),
.I1(b[1]),
.I2(a[0]),
.I3(b[0]),
.O(sig0000005f)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk00000060 (
.I0(a[31]),
.I1(b[31]),
.I2(a[30]),
.I3(b[30]),
.O(sig00000040)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk00000061 (
.I0(b[29]),
.I1(a[29]),
.I2(a[28]),
.I3(b[28]),
.O(sig00000042)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk00000062 (
.I0(b[27]),
.I1(a[27]),
.I2(a[26]),
.I3(b[26]),
.O(sig00000044)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk00000063 (
.I0(b[25]),
.I1(a[25]),
.I2(a[24]),
.I3(b[24]),
.O(sig00000046)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk00000064 (
.I0(b[23]),
.I1(a[23]),
.I2(a[22]),
.I3(b[22]),
.O(sig00000048)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk00000065 (
.I0(b[21]),
.I1(a[21]),
.I2(a[20]),
.I3(b[20]),
.O(sig0000004a)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk00000066 (
.I0(b[19]),
.I1(a[19]),
.I2(a[18]),
.I3(b[18]),
.O(sig0000004c)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk00000067 (
.I0(b[17]),
.I1(a[17]),
.I2(a[16]),
.I3(b[16]),
.O(sig0000004e)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk00000068 (
.I0(b[15]),
.I1(a[15]),
.I2(a[14]),
.I3(b[14]),
.O(sig00000050)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk00000069 (
.I0(b[13]),
.I1(a[13]),
.I2(a[12]),
.I3(b[12]),
.O(sig00000052)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk0000006a (
.I0(b[11]),
.I1(a[11]),
.I2(a[10]),
.I3(b[10]),
.O(sig00000054)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk0000006b (
.I0(b[9]),
.I1(a[9]),
.I2(a[8]),
.I3(b[8]),
.O(sig00000056)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk0000006c (
.I0(b[7]),
.I1(a[7]),
.I2(a[6]),
.I3(b[6]),
.O(sig00000058)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk0000006d (
.I0(b[5]),
.I1(a[5]),
.I2(a[4]),
.I3(b[4]),
.O(sig0000005a)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk0000006e (
.I0(b[3]),
.I1(a[3]),
.I2(a[2]),
.I3(b[2]),
.O(sig0000005c)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk0000006f (
.I0(b[1]),
.I1(a[1]),
.I2(a[0]),
.I3(b[0]),
.O(sig0000005e)
);
LUT2 #(
.INIT ( 4'h1 ))
blk00000070 (
.I0(sig00000015),
.I1(sig00000017),
.O(sig00000070)
);
LUT6 #(
.INIT ( 64'hFFBE00000000FFFF ))
blk00000071 (
.I0(sig0000001b),
.I1(sig00000014),
.I2(sig00000013),
.I3(sig00000019),
.I4(sig0000001a),
.I5(sig00000070),
.O(sig00000011)
);
endmodule
|
module MemAlu(
/* verilator lint_off UNUSED */
clk,
mode,
baseAddr,
idxAddr,
idxDisp,
outAddr
);
input clk;
input[2:0] mode;
input[63:0] baseAddr;
input[31:0] idxAddr;
input[31:0] idxDisp;
output[63:0] outAddr;
reg[31:0] tIdxAddr;
reg[63:0] tIdxAddr2;
reg[63:0] tOutAddr;
parameter[2:0] MD_NONE = 3'b000;
parameter[2:0] MD_BYTE = 3'b001;
parameter[2:0] MD_WORD = 3'b010;
parameter[2:0] MD_DWORD = 3'b011;
parameter[2:0] MD_QWORD = 3'b100;
parameter[2:0] MD_OWORD = 3'b101;
parameter[2:0] MD_MOV = 3'b111;
parameter[63:0] NULL_ADDR = 64'h0000_0000_0000_0000;
parameter[63:0] NEG_ADDR = 64'hFFFF_FFFF_0000_0000;
always @ (mode) begin
tIdxAddr = idxAddr+idxDisp;
// tIdxAddr2 = tIdxAddr[31] ?
// (tIdxAddr|NEG_ADDR) :
// (tIdxAddr|NULL_ADDR);
tIdxAddr2[31:0] = tIdxAddr;
tIdxAddr2[63:32] = tIdxAddr[31] ?
32'hFFFF_FFFF :
32'h0000_0000 ;
case(mode)
MD_BYTE: begin
tOutAddr = baseAddr+tIdxAddr2;
end
MD_WORD: begin
tOutAddr = baseAddr+tIdxAddr2*2;
end
MD_DWORD: begin
tOutAddr = baseAddr+tIdxAddr2*4;
end
MD_QWORD: begin
tOutAddr = baseAddr+tIdxAddr2*8;
end
MD_OWORD: begin
tOutAddr = baseAddr+tIdxAddr2*16;
end
MD_MOV: begin
tOutAddr = baseAddr;
end
default: begin
tOutAddr = NULL_ADDR;
end
endcase
outAddr = tOutAddr;
end
//always @ (posedge clk) begin
// outAddr <= tOutAddr;
//end
endmodule
|
//-*- mode: Verilog; verilog-indent-level: 3; indent-tabs-mode: nil; tab-width: 1 -*-
module apl2c_connect(autoinoutmodport_type_intf ctl_i,
/*AUTOINOUTMODPORT("autoinoutmodport_type_intf", "ctl_cb")*/
// Beginning of automatic in/out/inouts (from modport)
input [4:0] inst,
input isel_t isel,
input replay
// End of automatics
);
/*AUTOASSIGNMODPORT("autoinoutmodport_type_intf", "ctl_cb", "ctl_i")*/
// Beginning of automatic assignments from modport
assign ctl_i.inst = inst;
assign ctl_i.isel = isel;
assign ctl_i.replay = replay;
// End of automatics
endmodule
interface autoinoutmodport_type_intf(input logic clk, input logic rst_n);
import uvm_pkg::*;
import ap_defines::*;
logic [4:0] inst;
isel_t isel;
logic replay;
clocking ctl_cb @(posedge clk);
input inst;
input isel;
input replay;
endclocking: ctl_cb
modport ctl_mp(clocking ctl_cb);
endinterface
// Local Variables:
// verilog-typedef-regexp:"_t"
// End:
|
/************************************************************************
dataGeneration.v
Data generation module
Domesday Duplicator - LaserDisc RF sampler
Copyright (C) 2018 Simon Inns
This file is part of Domesday Duplicator.
Domesday Duplicator is free software: you can redistribute it and/or
modify it under the terms of the GNU General Public License as
published by the Free Software Foundation, either version 3 of the
License, or (at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
Email: [email protected]
************************************************************************/
module dataGenerator (
input nReset,
input clock,
input [9:0] adc_databus,
input testModeFlag,
// Outputs
output [9:0] dataOut
);
// Register to store test and ADC data values
reg [9:0] adcData;
reg [9:0] testData;
wire [9:0] adc_databusRead;
// If we are in test-mode use test data,
// otherwise use the actual ADC data
assign dataOut = testModeFlag ? testData : adcData;
// Read the ADC data and generate the test data on the
// negative edge of the clock
//
// Note: The test data is a repeating pattern of incrementing
// values from 0 to 1023.
always @ (posedge clock, negedge nReset) begin
if (!nReset) begin
adcData <= 10'd0;
testData <= 10'd0;
end else begin
// Read the ADC data
adcData <= adc_databus;
// Test mode data generation
testData <= testData + 10'd1;
end
end
endmodule |
// ============================================================================
// Copyright (c) 2010
// ============================================================================
//
// Permission:
//
//
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods.
// ============================================================================
//
// ReConfigurable Computing Group
//
// web: http://www.ecs.umass.edu/ece/tessier/rcg/
//
//
// ============================================================================
// Major Functions/Design Description:
//
//
//
// ============================================================================
// Revision History:
// ============================================================================
// Ver.: |Author: |Mod. Date: |Changes Made:
// V1.0 |RCG |05/10/2011 |
// ============================================================================
//include "NF_2.1_defines.v"
//include "reg_defines_reference_router.v"
module add_rm_hdr
#(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH=DATA_WIDTH/8,
parameter STAGE_NUMBER = 'hff,
parameter PORT_NUMBER = 0
)
(
rx_in_data,
rx_in_ctrl,
rx_in_wr,
rx_in_rdy,
rx_out_data,
rx_out_ctrl,
rx_out_wr,
rx_out_rdy,
tx_in_data,
tx_in_ctrl,
tx_in_wr,
tx_in_rdy,
tx_out_data,
tx_out_ctrl,
tx_out_wr,
tx_out_rdy,
// --- Misc
reset,
clk
);
input [DATA_WIDTH-1:0] rx_in_data;
input [CTRL_WIDTH-1:0] rx_in_ctrl;
input rx_in_wr;
output rx_in_rdy;
output [DATA_WIDTH-1:0] rx_out_data;
output [CTRL_WIDTH-1:0] rx_out_ctrl;
output rx_out_wr;
input rx_out_rdy;
input [DATA_WIDTH-1:0] tx_in_data;
input [CTRL_WIDTH-1:0] tx_in_ctrl;
input tx_in_wr;
output tx_in_rdy;
output [DATA_WIDTH-1:0] tx_out_data;
output [CTRL_WIDTH-1:0] tx_out_ctrl;
output tx_out_wr;
input tx_out_rdy;
// --- Misc
input reset;
input clk;
add_hdr
#(
.DATA_WIDTH (DATA_WIDTH),
.CTRL_WIDTH (CTRL_WIDTH),
.STAGE_NUMBER (STAGE_NUMBER),
.PORT_NUMBER (PORT_NUMBER)
) add_hdr (
.in_data (rx_in_data),
.in_ctrl (rx_in_ctrl),
.in_wr (rx_in_wr),
.in_rdy (rx_in_rdy),
.out_data (rx_out_data),
.out_ctrl (rx_out_ctrl),
.out_wr (rx_out_wr),
.out_rdy (rx_out_rdy),
// --- Misc
.reset (reset),
.clk (clk)
);
rm_hdr
#(
.DATA_WIDTH (DATA_WIDTH),
.CTRL_WIDTH (CTRL_WIDTH)
) rm_hdr (
.in_data (tx_in_data),
.in_ctrl (tx_in_ctrl),
.in_wr (tx_in_wr),
.in_rdy (tx_in_rdy),
.out_data (tx_out_data),
.out_ctrl (tx_out_ctrl),
.out_wr (tx_out_wr),
.out_rdy (tx_out_rdy),
// --- Misc
.reset (reset),
.clk (clk)
);
endmodule // add_rm_hdr
|
`include "xorGate.v"
module xorGateTest ();
// localize variables
wire [31:0] busADD;
wire [31:0] busA, busB;
// declare an instance of the module
xorGate xorGate (busADD, busA, busB);
// Running the GUI part of simulation
xorGatetester tester (busADD, busA, busB);
// file for gtkwave
initial
begin
$dumpfile("xorGatetest.vcd");
$dumpvars(1, xorGate);
end
endmodule
module xorGatetester (busADD, busA, busB);
input [31:0] busADD;
output reg [31:0] busA, busB;
parameter d = 20;
initial // Response
begin
$display("busADD \t busA \t busB \t\t\t ");
#d;
end
reg [31:0] i;
initial // Stimulus
begin
$monitor("%b \t %b \t %b \t ", busADD, busA, busB, $time);
// positive + positive
busA = 32'h01010101; busB = 32'h01010101;
#d;
busA = 32'h7FFFFFFF; busB = 32'h7FFFFFFF; // should overflow
#d;
// positive + negative
busA = 32'h01010101; busB = 32'hFFFFFFFF; // 01010101 + -1
#d;
busA = 32'h00000001; busB = 32'hF0000000;
#d;
// negative + positive
busA = 32'hFFFFFFFF; busB = 32'h01010101;
#d;
busA = 32'hF0000000; busB = 32'h00000001;
#d;
// negative + negative
busA = 32'hFFFFFFFF; busB = 32'hFFFFFFFF; // -1 + -1
#d;
busA = 32'h90000000; busB = 32'h80000000; // should overflow
#d;
#(3*d);
$stop;
$finish;
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYMETAL6S6S_TB_V
`define SKY130_FD_SC_HS__DLYMETAL6S6S_TB_V
/**
* dlymetal6s6s: 6-inverter delay with output from 6th inverter on
* horizontal route.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlymetal6s6s.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 A = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 A = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 A = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 A = 1'bx;
end
sky130_fd_sc_hs__dlymetal6s6s dut (.A(A), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYMETAL6S6S_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB8TO1_SYMBOL_V
`define SKY130_FD_SC_HDLL__MUXB8TO1_SYMBOL_V
/**
* muxb8to1: Buffered 8-input multiplexer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__muxb8to1 (
//# {{data|Data Signals}}
input [7:0] D,
output Z,
//# {{control|Control Signals}}
input [7:0] S
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB8TO1_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SDFXBP_SYMBOL_V
`define SKY130_FD_SC_HD__SDFXBP_SYMBOL_V
/**
* sdfxbp: Scan delay flop, non-inverted clock, complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__sdfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N,
//# {{scanchain|Scan Chain}}
input SCD,
input SCE,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__SDFXBP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__HA_BEHAVIORAL_V
`define SKY130_FD_SC_HD__HA_BEHAVIORAL_V
/**
* ha: Half adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__ha (
COUT,
SUM ,
A ,
B
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out_COUT;
wire xor0_out_SUM ;
// Name Output Other arguments
and and0 (and0_out_COUT, A, B );
buf buf0 (COUT , and0_out_COUT );
xor xor0 (xor0_out_SUM , B, A );
buf buf1 (SUM , xor0_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__HA_BEHAVIORAL_V |
/*
* Copyright (c) 2015-2018 The Ultiparc Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Writeback pipeline stage
*/
`include "uparc_cpu_config.vh"
`include "uparc_cpu_common.vh"
`include "uparc_cpu_const.vh"
/* Writeback stage */
module uparc_writeback(
clk,
nrst,
/* CU signals */
i_exec_stall,
i_mem_stall,
i_fetch_stall,
i_wait_stall,
i_nullify,
/* Data for writeback */
i_rd_no,
i_rd_val,
o_rd_no,
o_rd_val
);
/* Inputs */
input wire clk;
input wire nrst;
/* CU signals */
input wire i_exec_stall;
input wire i_mem_stall;
input wire i_fetch_stall;
input wire i_wait_stall;
input wire i_nullify;
/* Input from memory access stage */
input wire [`UPARC_REGNO_WIDTH-1:0] i_rd_no;
input wire [`UPARC_REG_WIDTH-1:0] i_rd_val;
/* Output for write to register file */
output reg [`UPARC_REGNO_WIDTH-1:0] o_rd_no;
output reg [`UPARC_REG_WIDTH-1:0] o_rd_val;
wire core_stall = i_exec_stall || i_mem_stall || i_fetch_stall || i_wait_stall;
always @(posedge clk or negedge nrst)
begin
if(!nrst)
begin
o_rd_no <= {(`UPARC_REGNO_WIDTH){1'b0}};
o_rd_val <= {(`UPARC_REG_WIDTH){1'b0}};
end
else if(!core_stall)
begin
o_rd_no <= !i_nullify ? i_rd_no : {(`UPARC_REGNO_WIDTH){1'b0}};
o_rd_val <= i_rd_val;
end
end
endmodule /* uparc_writeback */
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXBP_BLACKBOX_V
`define SKY130_FD_SC_LS__DLXBP_BLACKBOX_V
/**
* dlxbp: Delay latch, non-inverted enable, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlxbp (
Q ,
Q_N ,
D ,
GATE
);
output Q ;
output Q_N ;
input D ;
input GATE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXBP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21AI_BLACKBOX_V
`define SKY130_FD_SC_LP__O21AI_BLACKBOX_V
/**
* o21ai: 2-input OR into first input of 2-input NAND.
*
* Y = !((A1 | A2) & B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o21ai (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21AI_BLACKBOX_V
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2017 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2017.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Advanced Mixed Mode Clock Manager (MMCM)
// /___/ /\ Filename : MMCME2_ADV.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 07/07/08 - Initial version.
// 09/19/08 - Change CLKFBOUT_MULT to CLKFBOUT_MULT_F
// CLKOUT0_DIVIDE to CLKOUT0_DIVIDE_F
// 10/03/08 - Initial all signals.
// 10/30/08 - Clock source switching without reset (CR492263).
// 11/18/08 - Add timing check for DADDR[6:5].
// 12/02/08 - Fix bug of Duty cycle calculation (CR498696)
// 12/05/08 - change pll_res according to hardware spreadsheet (CR496137)
// 12/09/08 - Enable output at CLKFBOUT_MULT_F*8 for fraction mode (CR499322)
// 01/08/09 - Add phase and duty cycle checks for fraction divide (CR501181)
// 01/09/09 - make pll_res same for BANDWIDTH=HIGH and OPTIMIZED (CR496137)
// 01/14/09 - Fine phase shift wrap around to 0 after 56 times;
// - PSEN to PSDONE change to 12 PSCLK; RST minpusle to 5ns;
// - add pulldown to PWRDWN pin. (CR503425)
// 01/14/09 - increase clkout_en_time for fraction mode (CR499322)
// 01/21/09 - align CLKFBOUT to CLKIN for fraction mode (CR504602)
// 01/27/09 - update DRP register address (CR505271)
// 01/28/09 - assign clkout_en0 and clkout_en1 to 0 when RST=1 (CR505767)
// 02/03/09 - Fix bug in clkfb fine phase shift.
// - Add delay to clkout_en0_tmp (CR506530).
// 02/05/09 - Add ps_in_ps calculation to clkvco_delay when clkfb_fps_en=1.
// - round clk_ht clk_lt for duty_cycle (CR506531)
// 02/11/09 - Change VCO_FREQ_MAX and MIN to 1601 and 399 to cover the rounded
// error (CR507969)
// 02/25/09 - round clk_ht clk_lt for duty_cycle (509386)
// 02/26/09 - Fix for clkin and clkfbin stop case (CR503425)
// 03/04/09 - Fix for CLOCK_HOLD (CR510820).
// 03/27/09 - set default 1 to CLKINSEL pin (CR516951)
// 04/13/09 - Check vco range when CLKINSEL not connected (CR516951)
// 04/22/09 - Add reset to clkinstopped related signals (CR519102)
// 04/27/09 - Make duty cycle of fraction mode 50/50 (CR519505)
// 05/13/09 - Use period_avg for clkvco_delay calculation (CR521120)
// 07/23/09 - fix bug in clk0_dt (CR527643)
// 07/27/09 - Do divide when period_avg > 0 (CR528090)
// - Change DIVCLK_DIVIDE to 80 (CR525904)
// - Add initial lock setting (CR524523)
// - Update RES CP setting (CR524522)
// 07/31/09 - Add if else to handle the fracion and nonfraction for clkout_en.
// 08/10/09 - Calculate clkin_lost_val after lock_period=1 (CR528520).
// 08/15/09 - Update LFHF (CR524522)
// 08/19/09 - Set clkfb_lost_val initial value (CR531354)
// 08/28/09 - add clkin_period_tmp_t to handle period_avg calculation
// when clkin has jitter (CR528520)
// 09/11/09 - Change CLKIN_FREQ_MIN to 10 Mhz (CR532774)
// 10/01/09 - Change CLKIN_FREQ_MAX to 800Mhz (CR535076)
// Add reset check for clock switchover (CR534900)
// 10/08/09 - Change CLKIN_FREQ MAX & MIN, CLKPFD_FREQ
// MAX & MIN to parameter (CR535828)
// 10/14/09 - Add clkin_chk_t1 and clkin_chk_t2 to handle check (CR535662)
// 10/22/09 - Add period_vco_mf for clkvco_delay calculation (CR536951)
// Add cmpvco to compensate period_vco rounded error (CR537073)
// 12/02/09 - not stop clkvco_lk when jitter (CR538717)
// 01/08/10 - Change minimum RST pulse width from 5 ns to 1.5 ns
// Add 1 ns delay to locked_out_tmp when RST=1 (CR543857)
// 01/19/10 - make change to clkvoc_lk_tmp to handle M=1 case (CR544970)
// 02/09/10 - Add global PLL_LOCKG (CR547918)
// 02/23/10 - Not use edge for locked_out_tmp (CR549667)
// 03/04/10 - Change CLKFBOUT_MULT_F range to 5-64 (CR551618)
// 03/22/10 - Change CLKFBOUT_MULT_F default to 5 (554618)
// 03/24/10 - Add SIM_DEVICE attribute
// 04/07/10 - Generate clkvco_ps_tmp2_en correctly when ps_lock_dly rising
// and clkout_ps=1 case; increase lock_period time to 10 (CR556468)
// 05/07/10 - Use period_vco_half_rm1 to reduce jitter (CR558966)
// 07/28/10 - Update ref parameter values (CR569260)
// 08/17/10 - Add Decay output clocks when input clock stopped (CR555324)
// 09/03/10 - use %f for M_MIN and M_MAX (CR574247)
// 09/09/10 - Change to bus timing.
// 09/26/10 - Add RST to LOCKED timing path (CR567807)
// 02/22/11 - reduce clkin period check resolution to 0.001 (CR594003)
// 03/08/11 - Support fraction mode phase shifting with phase parameter
// setting (CR596402)
// 04/26/11 - Support fraction mode phase shifting with DRP(CR607989)
// 05/24/11 - Set frac_wf_f to 1 when divide=2.125 (CR611840)
// 06/06/11 - set period_vco_half_rm2 to 0 when period_vco=0 (CR613021)
// 06/08/11 - Disable clk0 fraction mode when CLKOUT0_DIVIDE_F in range
// greater than 1 and less than 2. Add DRC check for it (608893)
// 08/03/11 - use clk0_frac instead of clk0_sfrac (CR 618600)
// 10/26/11 - Add DRC check for samples CLKIN period with parameter setting (CR631150)
// Add spectrum attributes.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 02/22/12 - Modify DRC (638094).
// 03/01/12 - fraction enable for m/d (CR 648429)
// 03/07/12 - added vcoflag (CR 638088, CR 636493)
// 04/19/12 - 654951 - rounding issue with clk_out_para_cal
// 05/03/12 - ncsim issue with clkfb_frac_en (CR 655792)
// 05/03/12 - jittery clock (CR 652401)
// 05/03/12 - incorrect period (CR 654951)
// 05/10/12 - fractional divide calculation issue (CR 658151)
// 05/18/12 - fractional divide calculation issue (CR 660657)
// 06/11/12 - update cp and res settings (CR 664278)
// 06/20/12 - modify reset drc (CR 643540)
// 09/06/12 - 655711 - modify displayed MAX on CLK_DUTY_CYCLE
// 12/12/12 - fix clk_osc process for ncsim (CR 676829)
// 04/04/13 - fix clkvco_frac_en for DRP (CR 709093)
// 04/09/13 - Added DRP monitor (CR 695630).
// 05/03/13 - 670208 Fractional clock alignment issue
// 05/31/13 - 720783 - revert clock alignment fix
// 10/22/2014 808642 - Added #1 to $finish
// 11/26/2014 829050 - remove CLKIN -> CLKOUT* timing paths
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module MMCME2_ADV #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
parameter real CLKIN_FREQ_MAX = 1066.000,
parameter real CLKIN_FREQ_MIN = 10.000,
parameter real CLKPFD_FREQ_MAX = 550.000,
parameter real CLKPFD_FREQ_MIN = 10.000,
parameter real VCOCLK_FREQ_MAX = 1600.000,
parameter real VCOCLK_FREQ_MIN = 600.000,
`endif
parameter BANDWIDTH = "OPTIMIZED",
parameter real CLKFBOUT_MULT_F = 5.000,
parameter real CLKFBOUT_PHASE = 0.000,
parameter CLKFBOUT_USE_FINE_PS = "FALSE",
parameter real CLKIN1_PERIOD = 0.000,
parameter real CLKIN2_PERIOD = 0.000,
parameter real CLKOUT0_DIVIDE_F = 1.000,
parameter real CLKOUT0_DUTY_CYCLE = 0.500,
parameter real CLKOUT0_PHASE = 0.000,
parameter CLKOUT0_USE_FINE_PS = "FALSE",
parameter integer CLKOUT1_DIVIDE = 1,
parameter real CLKOUT1_DUTY_CYCLE = 0.500,
parameter real CLKOUT1_PHASE = 0.000,
parameter CLKOUT1_USE_FINE_PS = "FALSE",
parameter integer CLKOUT2_DIVIDE = 1,
parameter real CLKOUT2_DUTY_CYCLE = 0.500,
parameter real CLKOUT2_PHASE = 0.000,
parameter CLKOUT2_USE_FINE_PS = "FALSE",
parameter integer CLKOUT3_DIVIDE = 1,
parameter real CLKOUT3_DUTY_CYCLE = 0.500,
parameter real CLKOUT3_PHASE = 0.000,
parameter CLKOUT3_USE_FINE_PS = "FALSE",
parameter CLKOUT4_CASCADE = "FALSE",
parameter integer CLKOUT4_DIVIDE = 1,
parameter real CLKOUT4_DUTY_CYCLE = 0.500,
parameter real CLKOUT4_PHASE = 0.000,
parameter CLKOUT4_USE_FINE_PS = "FALSE",
parameter integer CLKOUT5_DIVIDE = 1,
parameter real CLKOUT5_DUTY_CYCLE = 0.500,
parameter real CLKOUT5_PHASE = 0.000,
parameter CLKOUT5_USE_FINE_PS = "FALSE",
parameter integer CLKOUT6_DIVIDE = 1,
parameter real CLKOUT6_DUTY_CYCLE = 0.500,
parameter real CLKOUT6_PHASE = 0.000,
parameter CLKOUT6_USE_FINE_PS = "FALSE",
parameter COMPENSATION = "ZHOLD",
parameter integer DIVCLK_DIVIDE = 1,
parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0,
parameter [0:0] IS_PSEN_INVERTED = 1'b0,
parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0,
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter real REF_JITTER1 = 0.010,
parameter real REF_JITTER2 = 0.010,
parameter SS_EN = "FALSE",
parameter SS_MODE = "CENTER_HIGH",
parameter integer SS_MOD_PERIOD = 10000,
parameter STARTUP_WAIT = "FALSE"
)(
output CLKFBOUT,
output CLKFBOUTB,
output CLKFBSTOPPED,
output CLKINSTOPPED,
output CLKOUT0,
output CLKOUT0B,
output CLKOUT1,
output CLKOUT1B,
output CLKOUT2,
output CLKOUT2B,
output CLKOUT3,
output CLKOUT3B,
output CLKOUT4,
output CLKOUT5,
output CLKOUT6,
output [15:0] DO,
output DRDY,
output LOCKED,
output PSDONE,
input CLKFBIN,
input CLKIN1,
input CLKIN2,
input CLKINSEL,
input [6:0] DADDR,
input DCLK,
input DEN,
input [15:0] DI,
input DWE,
input PSCLK,
input PSEN,
input PSINCDEC,
input PWRDWN,
input RST
);
`ifndef XIL_TIMING
localparam real CLKIN_FREQ_MAX = 1066.000;
localparam real CLKIN_FREQ_MIN = 10.000;
localparam real CLKPFD_FREQ_MAX = 550.000;
localparam real CLKPFD_FREQ_MIN = 10.000;
localparam real VCOCLK_FREQ_MAX = 1600.000;
localparam real VCOCLK_FREQ_MIN = 600.000;
`endif
// define constants
localparam MODULE_NAME = "MMCME2_ADV";
// Parameter encodings and registers
localparam BANDWIDTH_HIGH = 1;
localparam BANDWIDTH_LOW = 2;
localparam BANDWIDTH_OPTIMIZED = 0;
localparam CLKFBOUT_USE_FINE_PS_FALSE = 1;
localparam CLKFBOUT_USE_FINE_PS_TRUE = 0;
localparam CLKOUT0_USE_FINE_PS_FALSE = 1;
localparam CLKOUT0_USE_FINE_PS_TRUE = 0;
localparam CLKOUT1_USE_FINE_PS_FALSE = 1;
localparam CLKOUT1_USE_FINE_PS_TRUE = 0;
localparam CLKOUT2_USE_FINE_PS_FALSE = 1;
localparam CLKOUT2_USE_FINE_PS_TRUE = 0;
localparam CLKOUT3_USE_FINE_PS_FALSE = 1;
localparam CLKOUT3_USE_FINE_PS_TRUE = 0;
localparam CLKOUT4_CASCADE_FALSE = 0;
localparam CLKOUT4_CASCADE_TRUE = 1;
localparam CLKOUT4_USE_FINE_PS_FALSE = 1;
localparam CLKOUT4_USE_FINE_PS_TRUE = 0;
localparam CLKOUT5_USE_FINE_PS_FALSE = 1;
localparam CLKOUT5_USE_FINE_PS_TRUE = 0;
localparam CLKOUT6_USE_FINE_PS_FALSE = 1;
localparam CLKOUT6_USE_FINE_PS_TRUE = 0;
localparam COMPENSATION_BUF_IN = 1;
localparam COMPENSATION_EXTERNAL = 2;
localparam COMPENSATION_INTERNAL = 3;
localparam COMPENSATION_ZHOLD = 0;
localparam SS_EN_FALSE = 0;
localparam SS_EN_TRUE = 1;
localparam SS_MODE_CENTER_HIGH = 0;
localparam SS_MODE_CENTER_LOW = 1;
localparam SS_MODE_DOWN_HIGH = 2;
localparam SS_MODE_DOWN_LOW = 3;
localparam STARTUP_WAIT_FALSE = 1;
localparam STARTUP_WAIT_TRUE = 0;
reg trig_attr = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "MMCME2_ADV_dr.v"
`else
localparam [72:1] BANDWIDTH_REG = BANDWIDTH;
localparam real CLKFBOUT_MULT_F_REG = CLKFBOUT_MULT_F;
localparam real CLKFBOUT_PHASE_REG = CLKFBOUT_PHASE;
localparam [40:1] CLKFBOUT_USE_FINE_PS_REG = CLKFBOUT_USE_FINE_PS;
localparam real CLKIN1_PERIOD_REG = CLKIN1_PERIOD;
localparam real CLKIN2_PERIOD_REG = CLKIN2_PERIOD;
localparam real CLKIN_FREQ_MAX_REG = CLKIN_FREQ_MAX;
localparam real CLKIN_FREQ_MIN_REG = CLKIN_FREQ_MIN;
localparam real CLKOUT0_DIVIDE_F_REG = CLKOUT0_DIVIDE_F;
localparam real CLKOUT0_DUTY_CYCLE_REG = CLKOUT0_DUTY_CYCLE;
localparam real CLKOUT0_PHASE_REG = CLKOUT0_PHASE;
localparam [40:1] CLKOUT0_USE_FINE_PS_REG = CLKOUT0_USE_FINE_PS;
localparam [31:0] CLKOUT1_DIVIDE_REG = CLKOUT1_DIVIDE;
localparam real CLKOUT1_DUTY_CYCLE_REG = CLKOUT1_DUTY_CYCLE;
localparam real CLKOUT1_PHASE_REG = CLKOUT1_PHASE;
localparam [40:1] CLKOUT1_USE_FINE_PS_REG = CLKOUT1_USE_FINE_PS;
localparam [31:0] CLKOUT2_DIVIDE_REG = CLKOUT2_DIVIDE;
localparam real CLKOUT2_DUTY_CYCLE_REG = CLKOUT2_DUTY_CYCLE;
localparam real CLKOUT2_PHASE_REG = CLKOUT2_PHASE;
localparam [40:1] CLKOUT2_USE_FINE_PS_REG = CLKOUT2_USE_FINE_PS;
localparam [31:0] CLKOUT3_DIVIDE_REG = CLKOUT3_DIVIDE;
localparam real CLKOUT3_DUTY_CYCLE_REG = CLKOUT3_DUTY_CYCLE;
localparam real CLKOUT3_PHASE_REG = CLKOUT3_PHASE;
localparam [40:1] CLKOUT3_USE_FINE_PS_REG = CLKOUT3_USE_FINE_PS;
localparam [40:1] CLKOUT4_CASCADE_REG = CLKOUT4_CASCADE;
localparam [31:0] CLKOUT4_DIVIDE_REG = CLKOUT4_DIVIDE;
localparam real CLKOUT4_DUTY_CYCLE_REG = CLKOUT4_DUTY_CYCLE;
localparam real CLKOUT4_PHASE_REG = CLKOUT4_PHASE;
localparam [40:1] CLKOUT4_USE_FINE_PS_REG = CLKOUT4_USE_FINE_PS;
localparam [31:0] CLKOUT5_DIVIDE_REG = CLKOUT5_DIVIDE;
localparam real CLKOUT5_DUTY_CYCLE_REG = CLKOUT5_DUTY_CYCLE;
localparam real CLKOUT5_PHASE_REG = CLKOUT5_PHASE;
localparam [40:1] CLKOUT5_USE_FINE_PS_REG = CLKOUT5_USE_FINE_PS;
localparam [31:0] CLKOUT6_DIVIDE_REG = CLKOUT6_DIVIDE;
localparam real CLKOUT6_DUTY_CYCLE_REG = CLKOUT6_DUTY_CYCLE;
localparam real CLKOUT6_PHASE_REG = CLKOUT6_PHASE;
localparam [40:1] CLKOUT6_USE_FINE_PS_REG = CLKOUT6_USE_FINE_PS;
localparam real CLKPFD_FREQ_MAX_REG = CLKPFD_FREQ_MAX;
localparam real CLKPFD_FREQ_MIN_REG = CLKPFD_FREQ_MIN;
localparam [64:1] COMPENSATION_REG = COMPENSATION;
localparam [31:0] DIVCLK_DIVIDE_REG = DIVCLK_DIVIDE;
localparam [0:0] IS_CLKINSEL_INVERTED_REG = IS_CLKINSEL_INVERTED;
localparam [0:0] IS_PSEN_INVERTED_REG = IS_PSEN_INVERTED;
localparam [0:0] IS_PSINCDEC_INVERTED_REG = IS_PSINCDEC_INVERTED;
localparam [0:0] IS_PWRDWN_INVERTED_REG = IS_PWRDWN_INVERTED;
localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED;
localparam real REF_JITTER1_REG = REF_JITTER1;
localparam real REF_JITTER2_REG = REF_JITTER2;
localparam [40:1] SS_EN_REG = SS_EN;
localparam [88:1] SS_MODE_REG = SS_MODE;
localparam [31:0] SS_MOD_PERIOD_REG = SS_MOD_PERIOD;
localparam [40:1] STARTUP_WAIT_REG = STARTUP_WAIT;
localparam real VCOCLK_FREQ_MAX_REG = VCOCLK_FREQ_MAX;
localparam real VCOCLK_FREQ_MIN_REG = VCOCLK_FREQ_MIN;
`endif
`ifdef XIL_XECLIB
wire [1:0] BANDWIDTH_BIN;
wire [63:0] CLKFBOUT_MULT_F_BIN;
wire [63:0] CLKFBOUT_PHASE_BIN;
wire CLKFBOUT_USE_FINE_PS_BIN;
wire [63:0] CLKIN1_PERIOD_BIN;
wire [63:0] CLKIN2_PERIOD_BIN;
wire [63:0] CLKIN_FREQ_MAX_BIN;
wire [63:0] CLKIN_FREQ_MIN_BIN;
wire [63:0] CLKOUT0_DIVIDE_F_BIN;
wire [63:0] CLKOUT0_DUTY_CYCLE_BIN;
wire [63:0] CLKOUT0_PHASE_BIN;
wire CLKOUT0_USE_FINE_PS_BIN;
wire [7:0] CLKOUT1_DIVIDE_BIN;
wire [63:0] CLKOUT1_DUTY_CYCLE_BIN;
wire [63:0] CLKOUT1_PHASE_BIN;
wire CLKOUT1_USE_FINE_PS_BIN;
wire [7:0] CLKOUT2_DIVIDE_BIN;
wire [63:0] CLKOUT2_DUTY_CYCLE_BIN;
wire [63:0] CLKOUT2_PHASE_BIN;
wire CLKOUT2_USE_FINE_PS_BIN;
wire [7:0] CLKOUT3_DIVIDE_BIN;
wire [63:0] CLKOUT3_DUTY_CYCLE_BIN;
wire [63:0] CLKOUT3_PHASE_BIN;
wire CLKOUT3_USE_FINE_PS_BIN;
wire CLKOUT4_CASCADE_BIN;
wire [7:0] CLKOUT4_DIVIDE_BIN;
wire [63:0] CLKOUT4_DUTY_CYCLE_BIN;
wire [63:0] CLKOUT4_PHASE_BIN;
wire CLKOUT4_USE_FINE_PS_BIN;
wire [7:0] CLKOUT5_DIVIDE_BIN;
wire [63:0] CLKOUT5_DUTY_CYCLE_BIN;
wire [63:0] CLKOUT5_PHASE_BIN;
wire CLKOUT5_USE_FINE_PS_BIN;
wire [7:0] CLKOUT6_DIVIDE_BIN;
wire [63:0] CLKOUT6_DUTY_CYCLE_BIN;
wire [63:0] CLKOUT6_PHASE_BIN;
wire CLKOUT6_USE_FINE_PS_BIN;
wire [63:0] CLKPFD_FREQ_MAX_BIN;
wire [63:0] CLKPFD_FREQ_MIN_BIN;
wire [1:0] COMPENSATION_BIN;
wire [6:0] DIVCLK_DIVIDE_BIN;
wire [63:0] REF_JITTER1_BIN;
wire [63:0] REF_JITTER2_BIN;
wire SS_EN_BIN;
wire [1:0] SS_MODE_BIN;
wire [15:0] SS_MOD_PERIOD_BIN;
wire STARTUP_WAIT_BIN;
wire [63:0] VCOCLK_FREQ_MAX_BIN;
wire [63:0] VCOCLK_FREQ_MIN_BIN;
`else
reg [1:0] BANDWIDTH_BIN;
reg [63:0] CLKFBOUT_MULT_F_BIN;
reg [63:0] CLKFBOUT_PHASE_BIN;
reg CLKFBOUT_USE_FINE_PS_BIN;
reg [63:0] CLKIN1_PERIOD_BIN;
reg [63:0] CLKIN2_PERIOD_BIN;
reg [63:0] CLKIN_FREQ_MAX_BIN;
reg [63:0] CLKIN_FREQ_MIN_BIN;
reg [63:0] CLKOUT0_DIVIDE_F_BIN;
reg [63:0] CLKOUT0_DUTY_CYCLE_BIN;
reg [63:0] CLKOUT0_PHASE_BIN;
reg CLKOUT0_USE_FINE_PS_BIN;
reg [7:0] CLKOUT1_DIVIDE_BIN;
reg [63:0] CLKOUT1_DUTY_CYCLE_BIN;
reg [63:0] CLKOUT1_PHASE_BIN;
reg CLKOUT1_USE_FINE_PS_BIN;
reg [7:0] CLKOUT2_DIVIDE_BIN;
reg [63:0] CLKOUT2_DUTY_CYCLE_BIN;
reg [63:0] CLKOUT2_PHASE_BIN;
reg CLKOUT2_USE_FINE_PS_BIN;
reg [7:0] CLKOUT3_DIVIDE_BIN;
reg [63:0] CLKOUT3_DUTY_CYCLE_BIN;
reg [63:0] CLKOUT3_PHASE_BIN;
reg CLKOUT3_USE_FINE_PS_BIN;
reg CLKOUT4_CASCADE_BIN;
reg [7:0] CLKOUT4_DIVIDE_BIN;
reg [63:0] CLKOUT4_DUTY_CYCLE_BIN;
reg [63:0] CLKOUT4_PHASE_BIN;
reg CLKOUT4_USE_FINE_PS_BIN;
reg [7:0] CLKOUT5_DIVIDE_BIN;
reg [63:0] CLKOUT5_DUTY_CYCLE_BIN;
reg [63:0] CLKOUT5_PHASE_BIN;
reg CLKOUT5_USE_FINE_PS_BIN;
reg [7:0] CLKOUT6_DIVIDE_BIN;
reg [63:0] CLKOUT6_DUTY_CYCLE_BIN;
reg [63:0] CLKOUT6_PHASE_BIN;
reg CLKOUT6_USE_FINE_PS_BIN;
reg [63:0] CLKPFD_FREQ_MAX_BIN;
reg [63:0] CLKPFD_FREQ_MIN_BIN;
reg [1:0] COMPENSATION_BIN;
reg [6:0] DIVCLK_DIVIDE_BIN;
reg [63:0] REF_JITTER1_BIN;
reg [63:0] REF_JITTER2_BIN;
reg SS_EN_BIN;
reg [1:0] SS_MODE_BIN;
reg [15:0] SS_MOD_PERIOD_BIN;
reg STARTUP_WAIT_BIN;
reg [63:0] VCOCLK_FREQ_MAX_BIN;
reg [63:0] VCOCLK_FREQ_MIN_BIN;
`endif
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
reg CLKFBOUTB_out;
reg CLKFBOUT_out;
reg CLKFBSTOPPED_out;
reg CLKINSTOPPED_out;
reg CLKOUT0B_out;
reg CLKOUT0_out;
reg CLKOUT1B_out;
reg CLKOUT1_out;
reg CLKOUT2B_out;
reg CLKOUT2_out;
reg CLKOUT3B_out;
reg CLKOUT3_out;
reg CLKOUT4_out;
reg CLKOUT5_out;
reg CLKOUT6_out;
reg DRDY_out;
reg LOCKED_out;
reg PSDONE_out;
reg [15:0] DO_out;
wire CLKFBIN_in;
wire CLKIN1_in;
wire CLKIN2_in;
wire CLKINSEL_in;
wire DCLK_in;
wire DEN_in;
wire DWE_in;
wire PSCLK_in;
wire PSEN_in;
wire PSINCDEC_in;
wire PWRDWN_in;
wire RST_in;
wire [15:0] DI_in;
wire [6:0] DADDR_in;
`ifdef XIL_TIMING
wire DCLK_delay;
wire DEN_delay;
wire DWE_delay;
wire PSCLK_delay;
wire PSEN_delay;
wire PSINCDEC_delay;
wire [15:0] DI_delay;
wire [6:0] DADDR_delay;
`endif
assign CLKFBOUT = CLKFBOUT_out;
assign CLKFBOUTB = CLKFBOUTB_out;
assign CLKFBSTOPPED = CLKFBSTOPPED_out;
assign CLKINSTOPPED = CLKINSTOPPED_out;
assign CLKOUT0 = CLKOUT0_out;
assign CLKOUT0B = CLKOUT0B_out;
assign CLKOUT1 = CLKOUT1_out;
assign CLKOUT1B = CLKOUT1B_out;
assign CLKOUT2 = CLKOUT2_out;
assign CLKOUT2B = CLKOUT2B_out;
assign CLKOUT3 = CLKOUT3_out;
assign CLKOUT3B = CLKOUT3B_out;
assign CLKOUT4 = CLKOUT4_out;
assign CLKOUT5 = CLKOUT5_out;
assign CLKOUT6 = CLKOUT6_out;
assign DO = DO_out;
assign DRDY = DRDY_out;
assign LOCKED = LOCKED_out;
assign PSDONE = PSDONE_out;
`ifdef XIL_TIMING
assign DADDR_in[0] = (DADDR[0] !== 1'bz) && DADDR_delay[0]; // rv 0
assign DADDR_in[1] = (DADDR[1] !== 1'bz) && DADDR_delay[1]; // rv 0
assign DADDR_in[2] = (DADDR[2] !== 1'bz) && DADDR_delay[2]; // rv 0
assign DADDR_in[3] = (DADDR[3] !== 1'bz) && DADDR_delay[3]; // rv 0
assign DADDR_in[4] = (DADDR[4] !== 1'bz) && DADDR_delay[4]; // rv 0
assign DADDR_in[5] = (DADDR[5] !== 1'bz) && DADDR_delay[5]; // rv 0
assign DADDR_in[6] = (DADDR[6] !== 1'bz) && DADDR_delay[6]; // rv 0
assign DCLK_in = (DCLK !== 1'bz) && DCLK_delay; // rv 0
assign DEN_in = (DEN !== 1'bz) && DEN_delay; // rv 0
assign DI_in[0] = (DI[0] !== 1'bz) && DI_delay[0]; // rv 0
assign DI_in[10] = (DI[10] !== 1'bz) && DI_delay[10]; // rv 0
assign DI_in[11] = (DI[11] !== 1'bz) && DI_delay[11]; // rv 0
assign DI_in[12] = (DI[12] !== 1'bz) && DI_delay[12]; // rv 0
assign DI_in[13] = (DI[13] !== 1'bz) && DI_delay[13]; // rv 0
assign DI_in[14] = (DI[14] !== 1'bz) && DI_delay[14]; // rv 0
assign DI_in[15] = (DI[15] !== 1'bz) && DI_delay[15]; // rv 0
assign DI_in[1] = (DI[1] !== 1'bz) && DI_delay[1]; // rv 0
assign DI_in[2] = (DI[2] !== 1'bz) && DI_delay[2]; // rv 0
assign DI_in[3] = (DI[3] !== 1'bz) && DI_delay[3]; // rv 0
assign DI_in[4] = (DI[4] !== 1'bz) && DI_delay[4]; // rv 0
assign DI_in[5] = (DI[5] !== 1'bz) && DI_delay[5]; // rv 0
assign DI_in[6] = (DI[6] !== 1'bz) && DI_delay[6]; // rv 0
assign DI_in[7] = (DI[7] !== 1'bz) && DI_delay[7]; // rv 0
assign DI_in[8] = (DI[8] !== 1'bz) && DI_delay[8]; // rv 0
assign DI_in[9] = (DI[9] !== 1'bz) && DI_delay[9]; // rv 0
assign DWE_in = (DWE !== 1'bz) && DWE_delay; // rv 0
assign PSCLK_in = (PSCLK !== 1'bz) && PSCLK_delay; // rv 0
assign PSEN_in = (PSEN !== 1'bz) && (PSEN_delay ^ IS_PSEN_INVERTED_REG); // rv 0
assign PSINCDEC_in = (PSINCDEC !== 1'bz) && (PSINCDEC_delay ^ IS_PSINCDEC_INVERTED_REG); // rv 0
`else
assign DADDR_in[0] = (DADDR[0] !== 1'bz) && DADDR[0]; // rv 0
assign DADDR_in[1] = (DADDR[1] !== 1'bz) && DADDR[1]; // rv 0
assign DADDR_in[2] = (DADDR[2] !== 1'bz) && DADDR[2]; // rv 0
assign DADDR_in[3] = (DADDR[3] !== 1'bz) && DADDR[3]; // rv 0
assign DADDR_in[4] = (DADDR[4] !== 1'bz) && DADDR[4]; // rv 0
assign DADDR_in[5] = (DADDR[5] !== 1'bz) && DADDR[5]; // rv 0
assign DADDR_in[6] = (DADDR[6] !== 1'bz) && DADDR[6]; // rv 0
assign DCLK_in = (DCLK !== 1'bz) && DCLK; // rv 0
assign DEN_in = (DEN !== 1'bz) && DEN; // rv 0
assign DI_in[0] = (DI[0] !== 1'bz) && DI[0]; // rv 0
assign DI_in[10] = (DI[10] !== 1'bz) && DI[10]; // rv 0
assign DI_in[11] = (DI[11] !== 1'bz) && DI[11]; // rv 0
assign DI_in[12] = (DI[12] !== 1'bz) && DI[12]; // rv 0
assign DI_in[13] = (DI[13] !== 1'bz) && DI[13]; // rv 0
assign DI_in[14] = (DI[14] !== 1'bz) && DI[14]; // rv 0
assign DI_in[15] = (DI[15] !== 1'bz) && DI[15]; // rv 0
assign DI_in[1] = (DI[1] !== 1'bz) && DI[1]; // rv 0
assign DI_in[2] = (DI[2] !== 1'bz) && DI[2]; // rv 0
assign DI_in[3] = (DI[3] !== 1'bz) && DI[3]; // rv 0
assign DI_in[4] = (DI[4] !== 1'bz) && DI[4]; // rv 0
assign DI_in[5] = (DI[5] !== 1'bz) && DI[5]; // rv 0
assign DI_in[6] = (DI[6] !== 1'bz) && DI[6]; // rv 0
assign DI_in[7] = (DI[7] !== 1'bz) && DI[7]; // rv 0
assign DI_in[8] = (DI[8] !== 1'bz) && DI[8]; // rv 0
assign DI_in[9] = (DI[9] !== 1'bz) && DI[9]; // rv 0
assign DWE_in = (DWE !== 1'bz) && DWE; // rv 0
assign PSCLK_in = (PSCLK !== 1'bz) && PSCLK; // rv 0
assign PSEN_in = (PSEN !== 1'bz) && (PSEN ^ IS_PSEN_INVERTED_REG); // rv 0
assign PSINCDEC_in = (PSINCDEC !== 1'bz) && (PSINCDEC ^ IS_PSINCDEC_INVERTED_REG); // rv 0
`endif
assign CLKFBIN_in = (CLKFBIN !== 1'bz) && CLKFBIN; // rv 0
assign CLKIN1_in = (CLKIN1 !== 1'bz) && CLKIN1; // rv 0
assign CLKIN2_in = (CLKIN2 !== 1'bz) && CLKIN2; // rv 0
assign CLKINSEL_in = (CLKINSEL === 1'bz) || (CLKINSEL ^ IS_CLKINSEL_INVERTED_REG); // rv 1
assign PWRDWN_in = (PWRDWN !== 1'bz) && (PWRDWN ^ IS_PWRDWN_INVERTED_REG); // rv 0
assign RST_in = (RST !== 1'bz) && (RST ^ IS_RST_INVERTED_REG); // rv 0
`ifndef XIL_XECLIB
initial begin
#1;
trig_attr = ~trig_attr;
end
`endif
`ifdef XIL_XECLIB
assign BANDWIDTH_BIN =
(BANDWIDTH_REG == "OPTIMIZED") ? BANDWIDTH_OPTIMIZED :
(BANDWIDTH_REG == "HIGH") ? BANDWIDTH_HIGH :
(BANDWIDTH_REG == "LOW") ? BANDWIDTH_LOW :
BANDWIDTH_OPTIMIZED;
assign CLKFBOUT_MULT_F_BIN = CLKFBOUT_MULT_F_REG * 1000;
assign CLKFBOUT_PHASE_BIN = CLKFBOUT_PHASE_REG * 1000;
assign CLKFBOUT_USE_FINE_PS_BIN =
(CLKFBOUT_USE_FINE_PS_REG == "FALSE") ? CLKFBOUT_USE_FINE_PS_FALSE :
(CLKFBOUT_USE_FINE_PS_REG == "TRUE") ? CLKFBOUT_USE_FINE_PS_TRUE :
CLKFBOUT_USE_FINE_PS_TRUE;
assign CLKIN1_PERIOD_BIN = CLKIN1_PERIOD_REG * 1000;
assign CLKIN2_PERIOD_BIN = CLKIN2_PERIOD_REG * 1000;
assign CLKIN_FREQ_MAX_BIN = CLKIN_FREQ_MAX_REG * 1000;
assign CLKIN_FREQ_MIN_BIN = CLKIN_FREQ_MIN_REG * 1000;
assign CLKOUT0_DIVIDE_F_BIN = CLKOUT0_DIVIDE_F_REG * 1000;
assign CLKOUT0_DUTY_CYCLE_BIN = CLKOUT0_DUTY_CYCLE_REG * 1000;
assign CLKOUT0_PHASE_BIN = CLKOUT0_PHASE_REG * 1000;
assign CLKOUT0_USE_FINE_PS_BIN =
(CLKOUT0_USE_FINE_PS_REG == "FALSE") ? CLKOUT0_USE_FINE_PS_FALSE :
(CLKOUT0_USE_FINE_PS_REG == "TRUE") ? CLKOUT0_USE_FINE_PS_TRUE :
CLKOUT0_USE_FINE_PS_TRUE;
assign CLKOUT1_DIVIDE_BIN = CLKOUT1_DIVIDE_REG[7:0];
assign CLKOUT1_DUTY_CYCLE_BIN = CLKOUT1_DUTY_CYCLE_REG * 1000;
assign CLKOUT1_PHASE_BIN = CLKOUT1_PHASE_REG * 1000;
assign CLKOUT1_USE_FINE_PS_BIN =
(CLKOUT1_USE_FINE_PS_REG == "FALSE") ? CLKOUT1_USE_FINE_PS_FALSE :
(CLKOUT1_USE_FINE_PS_REG == "TRUE") ? CLKOUT1_USE_FINE_PS_TRUE :
CLKOUT1_USE_FINE_PS_TRUE;
assign CLKOUT2_DIVIDE_BIN = CLKOUT2_DIVIDE_REG[7:0];
assign CLKOUT2_DUTY_CYCLE_BIN = CLKOUT2_DUTY_CYCLE_REG * 1000;
assign CLKOUT2_PHASE_BIN = CLKOUT2_PHASE_REG * 1000;
assign CLKOUT2_USE_FINE_PS_BIN =
(CLKOUT2_USE_FINE_PS_REG == "FALSE") ? CLKOUT2_USE_FINE_PS_FALSE :
(CLKOUT2_USE_FINE_PS_REG == "TRUE") ? CLKOUT2_USE_FINE_PS_TRUE :
CLKOUT2_USE_FINE_PS_TRUE;
assign CLKOUT3_DIVIDE_BIN = CLKOUT3_DIVIDE_REG[7:0];
assign CLKOUT3_DUTY_CYCLE_BIN = CLKOUT3_DUTY_CYCLE_REG * 1000;
assign CLKOUT3_PHASE_BIN = CLKOUT3_PHASE_REG * 1000;
assign CLKOUT3_USE_FINE_PS_BIN =
(CLKOUT3_USE_FINE_PS_REG == "FALSE") ? CLKOUT3_USE_FINE_PS_FALSE :
(CLKOUT3_USE_FINE_PS_REG == "TRUE") ? CLKOUT3_USE_FINE_PS_TRUE :
CLKOUT3_USE_FINE_PS_TRUE;
assign CLKOUT4_CASCADE_BIN =
(CLKOUT4_CASCADE_REG == "FALSE") ? CLKOUT4_CASCADE_FALSE :
(CLKOUT4_CASCADE_REG == "TRUE") ? CLKOUT4_CASCADE_TRUE :
CLKOUT4_CASCADE_FALSE;
assign CLKOUT4_DIVIDE_BIN = CLKOUT4_DIVIDE_REG[7:0];
assign CLKOUT4_DUTY_CYCLE_BIN = CLKOUT4_DUTY_CYCLE_REG * 1000;
assign CLKOUT4_PHASE_BIN = CLKOUT4_PHASE_REG * 1000;
assign CLKOUT4_USE_FINE_PS_BIN =
(CLKOUT4_USE_FINE_PS_REG == "FALSE") ? CLKOUT4_USE_FINE_PS_FALSE :
(CLKOUT4_USE_FINE_PS_REG == "TRUE") ? CLKOUT4_USE_FINE_PS_TRUE :
CLKOUT4_USE_FINE_PS_TRUE;
assign CLKOUT5_DIVIDE_BIN = CLKOUT5_DIVIDE_REG[7:0];
assign CLKOUT5_DUTY_CYCLE_BIN = CLKOUT5_DUTY_CYCLE_REG * 1000;
assign CLKOUT5_PHASE_BIN = CLKOUT5_PHASE_REG * 1000;
assign CLKOUT5_USE_FINE_PS_BIN =
(CLKOUT5_USE_FINE_PS_REG == "FALSE") ? CLKOUT5_USE_FINE_PS_FALSE :
(CLKOUT5_USE_FINE_PS_REG == "TRUE") ? CLKOUT5_USE_FINE_PS_TRUE :
CLKOUT5_USE_FINE_PS_TRUE;
assign CLKOUT6_DIVIDE_BIN = CLKOUT6_DIVIDE_REG[7:0];
assign CLKOUT6_DUTY_CYCLE_BIN = CLKOUT6_DUTY_CYCLE_REG * 1000;
assign CLKOUT6_PHASE_BIN = CLKOUT6_PHASE_REG * 1000;
assign CLKOUT6_USE_FINE_PS_BIN =
(CLKOUT6_USE_FINE_PS_REG == "FALSE") ? CLKOUT6_USE_FINE_PS_FALSE :
(CLKOUT6_USE_FINE_PS_REG == "TRUE") ? CLKOUT6_USE_FINE_PS_TRUE :
CLKOUT6_USE_FINE_PS_TRUE;
assign CLKPFD_FREQ_MAX_BIN = CLKPFD_FREQ_MAX_REG * 1000;
assign CLKPFD_FREQ_MIN_BIN = CLKPFD_FREQ_MIN_REG * 1000;
assign COMPENSATION_BIN =
(COMPENSATION_REG == "ZHOLD") ? COMPENSATION_ZHOLD :
(COMPENSATION_REG == "BUF_IN") ? COMPENSATION_BUF_IN :
(COMPENSATION_REG == "EXTERNAL") ? COMPENSATION_EXTERNAL :
(COMPENSATION_REG == "INTERNAL") ? COMPENSATION_INTERNAL :
COMPENSATION_ZHOLD;
assign DIVCLK_DIVIDE_BIN = DIVCLK_DIVIDE_REG[6:0];
assign REF_JITTER1_BIN = REF_JITTER1_REG * 1000;
assign REF_JITTER2_BIN = REF_JITTER2_REG * 1000;
assign SS_EN_BIN =
(SS_EN_REG == "FALSE") ? SS_EN_FALSE :
(SS_EN_REG == "TRUE") ? SS_EN_TRUE :
SS_EN_FALSE;
assign SS_MODE_BIN =
(SS_MODE_REG == "CENTER_HIGH") ? SS_MODE_CENTER_HIGH :
(SS_MODE_REG == "CENTER_LOW") ? SS_MODE_CENTER_LOW :
(SS_MODE_REG == "DOWN_HIGH") ? SS_MODE_DOWN_HIGH :
(SS_MODE_REG == "DOWN_LOW") ? SS_MODE_DOWN_LOW :
SS_MODE_CENTER_HIGH;
assign SS_MOD_PERIOD_BIN = SS_MOD_PERIOD_REG[15:0];
assign STARTUP_WAIT_BIN =
(STARTUP_WAIT_REG == "FALSE") ? STARTUP_WAIT_FALSE :
(STARTUP_WAIT_REG == "TRUE") ? STARTUP_WAIT_TRUE :
STARTUP_WAIT_TRUE;
assign VCOCLK_FREQ_MAX_BIN = VCOCLK_FREQ_MAX_REG * 1000;
assign VCOCLK_FREQ_MIN_BIN = VCOCLK_FREQ_MIN_REG * 1000;
`else
always @ (trig_attr) begin
#1;
BANDWIDTH_BIN =
(BANDWIDTH_REG == "OPTIMIZED") ? BANDWIDTH_OPTIMIZED :
(BANDWIDTH_REG == "HIGH") ? BANDWIDTH_HIGH :
(BANDWIDTH_REG == "LOW") ? BANDWIDTH_LOW :
BANDWIDTH_OPTIMIZED;
CLKFBOUT_MULT_F_BIN = CLKFBOUT_MULT_F_REG * 1000;
CLKFBOUT_PHASE_BIN = CLKFBOUT_PHASE_REG * 1000;
CLKFBOUT_USE_FINE_PS_BIN =
(CLKFBOUT_USE_FINE_PS_REG == "FALSE") ? CLKFBOUT_USE_FINE_PS_FALSE :
(CLKFBOUT_USE_FINE_PS_REG == "TRUE") ? CLKFBOUT_USE_FINE_PS_TRUE :
CLKFBOUT_USE_FINE_PS_TRUE;
CLKIN1_PERIOD_BIN = CLKIN1_PERIOD_REG * 1000;
CLKIN2_PERIOD_BIN = CLKIN2_PERIOD_REG * 1000;
CLKIN_FREQ_MAX_BIN = CLKIN_FREQ_MAX_REG * 1000;
CLKIN_FREQ_MIN_BIN = CLKIN_FREQ_MIN_REG * 1000;
CLKOUT0_DIVIDE_F_BIN = CLKOUT0_DIVIDE_F_REG * 1000;
CLKOUT0_DUTY_CYCLE_BIN = CLKOUT0_DUTY_CYCLE_REG * 1000;
CLKOUT0_PHASE_BIN = CLKOUT0_PHASE_REG * 1000;
CLKOUT0_USE_FINE_PS_BIN =
(CLKOUT0_USE_FINE_PS_REG == "FALSE") ? CLKOUT0_USE_FINE_PS_FALSE :
(CLKOUT0_USE_FINE_PS_REG == "TRUE") ? CLKOUT0_USE_FINE_PS_TRUE :
CLKOUT0_USE_FINE_PS_TRUE;
CLKOUT1_DIVIDE_BIN = CLKOUT1_DIVIDE_REG[7:0];
CLKOUT1_DUTY_CYCLE_BIN = CLKOUT1_DUTY_CYCLE_REG * 1000;
CLKOUT1_PHASE_BIN = CLKOUT1_PHASE_REG * 1000;
CLKOUT1_USE_FINE_PS_BIN =
(CLKOUT1_USE_FINE_PS_REG == "FALSE") ? CLKOUT1_USE_FINE_PS_FALSE :
(CLKOUT1_USE_FINE_PS_REG == "TRUE") ? CLKOUT1_USE_FINE_PS_TRUE :
CLKOUT1_USE_FINE_PS_TRUE;
CLKOUT2_DIVIDE_BIN = CLKOUT2_DIVIDE_REG[7:0];
CLKOUT2_DUTY_CYCLE_BIN = CLKOUT2_DUTY_CYCLE_REG * 1000;
CLKOUT2_PHASE_BIN = CLKOUT2_PHASE_REG * 1000;
CLKOUT2_USE_FINE_PS_BIN =
(CLKOUT2_USE_FINE_PS_REG == "FALSE") ? CLKOUT2_USE_FINE_PS_FALSE :
(CLKOUT2_USE_FINE_PS_REG == "TRUE") ? CLKOUT2_USE_FINE_PS_TRUE :
CLKOUT2_USE_FINE_PS_TRUE;
CLKOUT3_DIVIDE_BIN = CLKOUT3_DIVIDE_REG[7:0];
CLKOUT3_DUTY_CYCLE_BIN = CLKOUT3_DUTY_CYCLE_REG * 1000;
CLKOUT3_PHASE_BIN = CLKOUT3_PHASE_REG * 1000;
CLKOUT3_USE_FINE_PS_BIN =
(CLKOUT3_USE_FINE_PS_REG == "FALSE") ? CLKOUT3_USE_FINE_PS_FALSE :
(CLKOUT3_USE_FINE_PS_REG == "TRUE") ? CLKOUT3_USE_FINE_PS_TRUE :
CLKOUT3_USE_FINE_PS_TRUE;
CLKOUT4_CASCADE_BIN =
(CLKOUT4_CASCADE_REG == "FALSE") ? CLKOUT4_CASCADE_FALSE :
(CLKOUT4_CASCADE_REG == "TRUE") ? CLKOUT4_CASCADE_TRUE :
CLKOUT4_CASCADE_FALSE;
CLKOUT4_DIVIDE_BIN = CLKOUT4_DIVIDE_REG[7:0];
CLKOUT4_DUTY_CYCLE_BIN = CLKOUT4_DUTY_CYCLE_REG * 1000;
CLKOUT4_PHASE_BIN = CLKOUT4_PHASE_REG * 1000;
CLKOUT4_USE_FINE_PS_BIN =
(CLKOUT4_USE_FINE_PS_REG == "FALSE") ? CLKOUT4_USE_FINE_PS_FALSE :
(CLKOUT4_USE_FINE_PS_REG == "TRUE") ? CLKOUT4_USE_FINE_PS_TRUE :
CLKOUT4_USE_FINE_PS_TRUE;
CLKOUT5_DIVIDE_BIN = CLKOUT5_DIVIDE_REG[7:0];
CLKOUT5_DUTY_CYCLE_BIN = CLKOUT5_DUTY_CYCLE_REG * 1000;
CLKOUT5_PHASE_BIN = CLKOUT5_PHASE_REG * 1000;
CLKOUT5_USE_FINE_PS_BIN =
(CLKOUT5_USE_FINE_PS_REG == "FALSE") ? CLKOUT5_USE_FINE_PS_FALSE :
(CLKOUT5_USE_FINE_PS_REG == "TRUE") ? CLKOUT5_USE_FINE_PS_TRUE :
CLKOUT5_USE_FINE_PS_TRUE;
CLKOUT6_DIVIDE_BIN = CLKOUT6_DIVIDE_REG[7:0];
CLKOUT6_DUTY_CYCLE_BIN = CLKOUT6_DUTY_CYCLE_REG * 1000;
CLKOUT6_PHASE_BIN = CLKOUT6_PHASE_REG * 1000;
CLKOUT6_USE_FINE_PS_BIN =
(CLKOUT6_USE_FINE_PS_REG == "FALSE") ? CLKOUT6_USE_FINE_PS_FALSE :
(CLKOUT6_USE_FINE_PS_REG == "TRUE") ? CLKOUT6_USE_FINE_PS_TRUE :
CLKOUT6_USE_FINE_PS_TRUE;
CLKPFD_FREQ_MAX_BIN = CLKPFD_FREQ_MAX_REG * 1000;
CLKPFD_FREQ_MIN_BIN = CLKPFD_FREQ_MIN_REG * 1000;
COMPENSATION_BIN =
(COMPENSATION_REG == "ZHOLD") ? COMPENSATION_ZHOLD :
(COMPENSATION_REG == "BUF_IN") ? COMPENSATION_BUF_IN :
(COMPENSATION_REG == "EXTERNAL") ? COMPENSATION_EXTERNAL :
(COMPENSATION_REG == "INTERNAL") ? COMPENSATION_INTERNAL :
COMPENSATION_ZHOLD;
DIVCLK_DIVIDE_BIN = DIVCLK_DIVIDE_REG[6:0];
REF_JITTER1_BIN = REF_JITTER1_REG * 1000;
REF_JITTER2_BIN = REF_JITTER2_REG * 1000;
SS_EN_BIN =
(SS_EN_REG == "FALSE") ? SS_EN_FALSE :
(SS_EN_REG == "TRUE") ? SS_EN_TRUE :
SS_EN_FALSE;
SS_MODE_BIN =
(SS_MODE_REG == "CENTER_HIGH") ? SS_MODE_CENTER_HIGH :
(SS_MODE_REG == "CENTER_LOW") ? SS_MODE_CENTER_LOW :
(SS_MODE_REG == "DOWN_HIGH") ? SS_MODE_DOWN_HIGH :
(SS_MODE_REG == "DOWN_LOW") ? SS_MODE_DOWN_LOW :
SS_MODE_CENTER_HIGH;
SS_MOD_PERIOD_BIN = SS_MOD_PERIOD_REG[15:0];
STARTUP_WAIT_BIN =
(STARTUP_WAIT_REG == "FALSE") ? STARTUP_WAIT_FALSE :
(STARTUP_WAIT_REG == "TRUE") ? STARTUP_WAIT_TRUE :
STARTUP_WAIT_TRUE;
VCOCLK_FREQ_MAX_BIN = VCOCLK_FREQ_MAX_REG * 1000;
VCOCLK_FREQ_MIN_BIN = VCOCLK_FREQ_MIN_REG * 1000;
end
`endif
`ifndef XIL_XECLIB
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((BANDWIDTH_REG != "OPTIMIZED") &&
(BANDWIDTH_REG != "HIGH") &&
(BANDWIDTH_REG != "LOW"))) begin
$display("Error: [Unisim %s-101] BANDWIDTH attribute is set to %s. Legal values for this attribute are OPTIMIZED, HIGH or LOW. Instance: %m", MODULE_NAME, BANDWIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKFBOUT_MULT_F_REG < 2.000 || CLKFBOUT_MULT_F_REG > 64.000)) begin
$display("Error: [Unisim %s-102] CLKFBOUT_MULT_F attribute is set to %f. Legal values for this attribute are 2.000 to 64.000. Instance: %m", MODULE_NAME, CLKFBOUT_MULT_F_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKFBOUT_PHASE_REG < -360.000 || CLKFBOUT_PHASE_REG > 360.000)) begin
$display("Error: [Unisim %s-103] CLKFBOUT_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKFBOUT_PHASE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLKFBOUT_USE_FINE_PS_REG != "TRUE") &&
(CLKFBOUT_USE_FINE_PS_REG != "FALSE"))) begin
$display("Error: [Unisim %s-104] CLKFBOUT_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKFBOUT_USE_FINE_PS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKIN1_PERIOD_REG < 0.000 || CLKIN1_PERIOD_REG > 100.000)) begin
$display("Error: [Unisim %s-105] CLKIN1_PERIOD attribute is set to %f. Legal values for this attribute are 0.000 to 100.000. Instance: %m", MODULE_NAME, CLKIN1_PERIOD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKIN2_PERIOD_REG < 0.000 || CLKIN2_PERIOD_REG > 100.000)) begin
$display("Error: [Unisim %s-106] CLKIN2_PERIOD attribute is set to %f. Legal values for this attribute are 0.000 to 100.000. Instance: %m", MODULE_NAME, CLKIN2_PERIOD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKIN_FREQ_MAX_REG < 800.000 || CLKIN_FREQ_MAX_REG > 1066.000)) begin
$display("Error: [Unisim %s-107] CLKIN_FREQ_MAX attribute is set to %f. Legal values for this attribute are 800.000 to 1066.000. Instance: %m", MODULE_NAME, CLKIN_FREQ_MAX_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKIN_FREQ_MIN_REG < 10.000 || CLKIN_FREQ_MIN_REG > 10.000)) begin
$display("Error: [Unisim %s-108] CLKIN_FREQ_MIN attribute is set to %f. Legal values for this attribute are 10.000 to 10.000. Instance: %m", MODULE_NAME, CLKIN_FREQ_MIN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKOUT0_DIVIDE_F_REG < 1.000 || CLKOUT0_DIVIDE_F_REG > 128.000)) begin
$display("Error: [Unisim %s-109] CLKOUT0_DIVIDE_F attribute is set to %f. Legal values for this attribute are 1.000 to 128.000. Instance: %m", MODULE_NAME, CLKOUT0_DIVIDE_F_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKOUT0_DUTY_CYCLE_REG < 0.001 || CLKOUT0_DUTY_CYCLE_REG > 0.999)) begin
$display("Error: [Unisim %s-110] CLKOUT0_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT0_DUTY_CYCLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKOUT0_PHASE_REG < -360.000 || CLKOUT0_PHASE_REG > 360.000)) begin
$display("Error: [Unisim %s-111] CLKOUT0_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT0_PHASE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLKOUT0_USE_FINE_PS_REG != "TRUE") &&
(CLKOUT0_USE_FINE_PS_REG != "FALSE"))) begin
$display("Error: [Unisim %s-112] CLKOUT0_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKOUT0_USE_FINE_PS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLKOUT1_DIVIDE_REG < 1) || (CLKOUT1_DIVIDE_REG > 128))) begin
$display("Error: [Unisim %s-113] CLKOUT1_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT1_DIVIDE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKOUT1_DUTY_CYCLE_REG < 0.001 || CLKOUT1_DUTY_CYCLE_REG > 0.999)) begin
$display("Error: [Unisim %s-114] CLKOUT1_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT1_DUTY_CYCLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKOUT1_PHASE_REG < -360.000 || CLKOUT1_PHASE_REG > 360.000)) begin
$display("Error: [Unisim %s-115] CLKOUT1_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT1_PHASE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLKOUT1_USE_FINE_PS_REG != "TRUE") &&
(CLKOUT1_USE_FINE_PS_REG != "FALSE"))) begin
$display("Error: [Unisim %s-116] CLKOUT1_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKOUT1_USE_FINE_PS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLKOUT2_DIVIDE_REG < 1) || (CLKOUT2_DIVIDE_REG > 128))) begin
$display("Error: [Unisim %s-117] CLKOUT2_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT2_DIVIDE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKOUT2_DUTY_CYCLE_REG < 0.001 || CLKOUT2_DUTY_CYCLE_REG > 0.999)) begin
$display("Error: [Unisim %s-118] CLKOUT2_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT2_DUTY_CYCLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKOUT2_PHASE_REG < -360.000 || CLKOUT2_PHASE_REG > 360.000)) begin
$display("Error: [Unisim %s-119] CLKOUT2_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT2_PHASE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLKOUT2_USE_FINE_PS_REG != "TRUE") &&
(CLKOUT2_USE_FINE_PS_REG != "FALSE"))) begin
$display("Error: [Unisim %s-120] CLKOUT2_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKOUT2_USE_FINE_PS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLKOUT3_DIVIDE_REG < 1) || (CLKOUT3_DIVIDE_REG > 128))) begin
$display("Error: [Unisim %s-121] CLKOUT3_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT3_DIVIDE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKOUT3_DUTY_CYCLE_REG < 0.001 || CLKOUT3_DUTY_CYCLE_REG > 0.999)) begin
$display("Error: [Unisim %s-122] CLKOUT3_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT3_DUTY_CYCLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKOUT3_PHASE_REG < -360.000 || CLKOUT3_PHASE_REG > 360.000)) begin
$display("Error: [Unisim %s-123] CLKOUT3_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT3_PHASE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLKOUT3_USE_FINE_PS_REG != "TRUE") &&
(CLKOUT3_USE_FINE_PS_REG != "FALSE"))) begin
$display("Error: [Unisim %s-124] CLKOUT3_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKOUT3_USE_FINE_PS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLKOUT4_CASCADE_REG != "FALSE") &&
(CLKOUT4_CASCADE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-125] CLKOUT4_CASCADE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLKOUT4_CASCADE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLKOUT4_DIVIDE_REG < 1) || (CLKOUT4_DIVIDE_REG > 128))) begin
$display("Error: [Unisim %s-126] CLKOUT4_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT4_DIVIDE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKOUT4_DUTY_CYCLE_REG < 0.001 || CLKOUT4_DUTY_CYCLE_REG > 0.999)) begin
$display("Error: [Unisim %s-127] CLKOUT4_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT4_DUTY_CYCLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKOUT4_PHASE_REG < -360.000 || CLKOUT4_PHASE_REG > 360.000)) begin
$display("Error: [Unisim %s-128] CLKOUT4_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT4_PHASE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLKOUT4_USE_FINE_PS_REG != "TRUE") &&
(CLKOUT4_USE_FINE_PS_REG != "FALSE"))) begin
$display("Error: [Unisim %s-129] CLKOUT4_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKOUT4_USE_FINE_PS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLKOUT5_DIVIDE_REG < 1) || (CLKOUT5_DIVIDE_REG > 128))) begin
$display("Error: [Unisim %s-130] CLKOUT5_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT5_DIVIDE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKOUT5_DUTY_CYCLE_REG < 0.001 || CLKOUT5_DUTY_CYCLE_REG > 0.999)) begin
$display("Error: [Unisim %s-131] CLKOUT5_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT5_DUTY_CYCLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKOUT5_PHASE_REG < -360.000 || CLKOUT5_PHASE_REG > 360.000)) begin
$display("Error: [Unisim %s-132] CLKOUT5_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT5_PHASE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLKOUT5_USE_FINE_PS_REG != "TRUE") &&
(CLKOUT5_USE_FINE_PS_REG != "FALSE"))) begin
$display("Error: [Unisim %s-133] CLKOUT5_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKOUT5_USE_FINE_PS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLKOUT6_DIVIDE_REG < 1) || (CLKOUT6_DIVIDE_REG > 128))) begin
$display("Error: [Unisim %s-134] CLKOUT6_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 128. Instance: %m", MODULE_NAME, CLKOUT6_DIVIDE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKOUT6_DUTY_CYCLE_REG < 0.001 || CLKOUT6_DUTY_CYCLE_REG > 0.999)) begin
$display("Error: [Unisim %s-135] CLKOUT6_DUTY_CYCLE attribute is set to %f. Legal values for this attribute are 0.001 to 0.999. Instance: %m", MODULE_NAME, CLKOUT6_DUTY_CYCLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKOUT6_PHASE_REG < -360.000 || CLKOUT6_PHASE_REG > 360.000)) begin
$display("Error: [Unisim %s-136] CLKOUT6_PHASE attribute is set to %f. Legal values for this attribute are -360.000 to 360.000. Instance: %m", MODULE_NAME, CLKOUT6_PHASE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLKOUT6_USE_FINE_PS_REG != "TRUE") &&
(CLKOUT6_USE_FINE_PS_REG != "FALSE"))) begin
$display("Error: [Unisim %s-137] CLKOUT6_USE_FINE_PS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLKOUT6_USE_FINE_PS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKPFD_FREQ_MAX_REG < 450.000 || CLKPFD_FREQ_MAX_REG > 550.000)) begin
$display("Error: [Unisim %s-138] CLKPFD_FREQ_MAX attribute is set to %f. Legal values for this attribute are 450.000 to 550.000. Instance: %m", MODULE_NAME, CLKPFD_FREQ_MAX_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(CLKPFD_FREQ_MIN_REG < 10.000 || CLKPFD_FREQ_MIN_REG > 10.000)) begin
$display("Error: [Unisim %s-139] CLKPFD_FREQ_MIN attribute is set to %f. Legal values for this attribute are 10.000 to 10.000. Instance: %m", MODULE_NAME, CLKPFD_FREQ_MIN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((COMPENSATION_REG != "ZHOLD") &&
(COMPENSATION_REG != "BUF_IN") &&
(COMPENSATION_REG != "EXTERNAL") &&
(COMPENSATION_REG != "INTERNAL"))) begin
$display("Error: [Unisim %s-140] COMPENSATION attribute is set to %s. Legal values for this attribute are ZHOLD, BUF_IN, EXTERNAL or INTERNAL. Instance: %m", MODULE_NAME, COMPENSATION_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DIVCLK_DIVIDE_REG < 1) || (DIVCLK_DIVIDE_REG > 106))) begin
$display("Error: [Unisim %s-141] DIVCLK_DIVIDE attribute is set to %d. Legal values for this attribute are 1 to 106. Instance: %m", MODULE_NAME, DIVCLK_DIVIDE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(REF_JITTER1_REG < 0.000 || REF_JITTER1_REG > 0.999)) begin
$display("Error: [Unisim %s-147] REF_JITTER1 attribute is set to %f. Legal values for this attribute are 0.000 to 0.999. Instance: %m", MODULE_NAME, REF_JITTER1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(REF_JITTER2_REG < 0.000 || REF_JITTER2_REG > 0.999)) begin
$display("Error: [Unisim %s-148] REF_JITTER2 attribute is set to %f. Legal values for this attribute are 0.000 to 0.999. Instance: %m", MODULE_NAME, REF_JITTER2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SS_EN_REG != "FALSE") &&
(SS_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-149] SS_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, SS_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SS_MODE_REG != "CENTER_HIGH") &&
(SS_MODE_REG != "CENTER_LOW") &&
(SS_MODE_REG != "DOWN_HIGH") &&
(SS_MODE_REG != "DOWN_LOW"))) begin
$display("Error: [Unisim %s-150] SS_MODE attribute is set to %s. Legal values for this attribute are CENTER_HIGH, CENTER_LOW, DOWN_HIGH or DOWN_LOW. Instance: %m", MODULE_NAME, SS_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SS_MOD_PERIOD_REG < 4000) || (SS_MOD_PERIOD_REG > 40000))) begin
$display("Error: [Unisim %s-151] SS_MOD_PERIOD attribute is set to %d. Legal values for this attribute are 4000 to 40000. Instance: %m", MODULE_NAME, SS_MOD_PERIOD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((STARTUP_WAIT_REG != "TRUE") &&
(STARTUP_WAIT_REG != "FALSE"))) begin
$display("Error: [Unisim %s-152] STARTUP_WAIT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, STARTUP_WAIT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(VCOCLK_FREQ_MAX_REG < 1200.000 || VCOCLK_FREQ_MAX_REG > 1600.000)) begin
$display("Error: [Unisim %s-153] VCOCLK_FREQ_MAX attribute is set to %f. Legal values for this attribute are 1200.000 to 1600.000. Instance: %m", MODULE_NAME, VCOCLK_FREQ_MAX_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
(VCOCLK_FREQ_MIN_REG < 600.000 || VCOCLK_FREQ_MIN_REG > 600.000)) begin
$display("Error: [Unisim %s-154] VCOCLK_FREQ_MIN attribute is set to %f. Legal values for this attribute are 600.000 to 600.000. Instance: %m", MODULE_NAME, VCOCLK_FREQ_MIN_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
localparam VCOCLK_FREQ_TARGET = 1000;
localparam M_MIN = 2.000;
localparam M_MAX = 64.000;
localparam real VF_MIN = 600.000;
localparam D_MIN = 1;
localparam D_MAX = 106;
localparam O_MIN = 1;
localparam O_MAX = 128;
localparam O_MAX_HT_LT = 64;
localparam REF_CLK_JITTER_MAX = 1000;
localparam REF_CLK_JITTER_SCALE = 0.1;
localparam MAX_FEEDBACK_DELAY = 10.0;
localparam MAX_FEEDBACK_DELAY_SCALE = 1.0;
localparam ps_max = 55;
reg [160:1] clkout_name;
real CLKOUT0_DIVIDE_F_RND;
real CLKFBOUT_MULT_F_RND;
tri1 p_up;
wire glock;
integer pchk_tmp1, pchk_tmp2;
integer clkvco_div_fint;
real clkvco_div_frac;
reg clk0_out;
reg clkfbout_out;
integer clkvco_frac_en;
integer ps_in_init;
reg clk0_fps_en=0, clk1_fps_en=0, clk2_fps_en=0, clk3_fps_en=0;
reg clk4_fps_en=0, clk5_fps_en=0, clk6_fps_en=0, clkfbout_fps_en=0;
reg fps_en=1'b0, fps_clk_en=1'b0;
reg clkinstopped_out1;
reg clkin_hold_f = 0;
reg clkinstopped_out_dly2 = 0, clkin_stop_f = 0;
integer period_avg_stpi = 0, period_avg_stp = 0;
real tmp_stp1, tmp_stp2;
reg pd_stp_p = 0;
reg vco_stp_f = 0;
reg psen_w = 0;
reg clkinstopped_out_dly = 0;
reg clkfbin_stop_tmp, clkfbstopped_out1, clkin_stop_tmp;
reg rst_clkinstopped = 0, rst_clkfbstopped = 0, rst_clkinstopped_tm = 0;
reg rst_clkinstopped_rc = 0;
reg rst_clkinstopped_lk, rst_clkfbstopped_lk;
integer clkin_lost_cnt;
integer clkfbin_lost_cnt;
reg clkinstopped_hold = 0;
integer ps_in_ps, ps_cnt;
integer ps_in_ps_neg, ps_cnt_neg;
reg [6:0] daddr_lat;
reg valid_daddr;
reg drp_lock;
integer drp_lock_lat = 4;
integer drp_lock_lat_cnt;
reg [15:0] dr_sram [127:0];
reg [160:0] tmp_string;
reg rst_int = 1'b0;
reg pwron_int;
wire rst_in_o;
reg clk1_out, clk2_out, clk3_out, clk4_out, clk5_out, clk6_out;
reg clkout_en, clkout_en1, clkout_en0, clkout_en0_tmp, clkout_en0_tmp1;
integer clkout_en_val, clkout_en_t;
integer clkin_lock_cnt;
integer clkout_en_time, locked_en_time, lock_cnt_max;
integer pll_lock_time, lock_period_time;
reg clkvco = 1'b0;
reg clkvco_lk_dly_tmp;
reg clkvco_lk_en;
reg clkvco_lk;
reg fbclk_tmp;
reg clkin_osc, clkin_p;
reg clkfbin_osc, clkfbin_p;
reg clkinstopped_vco_f;
time rst_edge, rst_ht;
reg fb_delay_found=1'b0, fb_delay_found_tmp=1'b0;
reg clkfbout_tst=1'b0;
real fb_delay_max;
time fb_delay=0, clkvco_delay, val_tmp, dly_tmp, fb_comp_delay;
time dly_tmp1, tmp_ps_val2;
integer dly_tmp_int, tmp_ps_val1;
time clkin_edge, delay_edge;
real period_clkin, clkin_period_tmp;
integer clkin_period_tmp_t;
integer clkin_period [4:0];
integer period_vco, period_vco_half, period_vco_half1, period_vco_half_rm;
real period_vco_rl, period_vco_rl_half;
integer period_vco_half_rm1, period_vco_half_rm2;
real cmpvco = 0.0;
real clkvco_pdrm;
integer period_vco_mf;
integer period_vco_tmp;
integer period_vco_rm, period_vco_cmp_cnt, clkvco_rm_cnt;
integer period_vco_cmp_flag;
integer period_vco_max, period_vco_min;
integer period_vco1, period_vco2, period_vco3, period_vco4;
integer period_vco5, period_vco6, period_vco7;
integer period_vco_target, period_vco_target_half;
integer period_fb=100000, period_avg=100000;
integer clk0_frac_lt, clk0_frac_ht;
real clk0_frac_lt_rl, clk0_frac_ht_rl;
integer clk0_frac_rm;
real clk0_frac_rm_rl;
integer clkfbout_frac_lt, clkfbout_frac_ht;
real clkfbout_frac_lt_rl, clkfbout_frac_ht_rl;
integer clkfbout_frac_rm;
real clkfbout_frac_rm_rl;
integer period_ps, period_ps_old;
reg ps_lock, ps_lock_dly;
real clkvco_freq_init_chk, clkfbout_pm_rl;
real tmp_real;
integer ik0, ik1, ik2, ik3, ik4, ib, i, j;
integer md_product, m_product, m_product2;
integer mf_product, clk0f_product;
// integer clkin_lost_val, clkfbin_lost_val, clkin_lost_val_lk;
integer clkin_lost_val;
integer clkfbin_lost_val;
time pll_locked_delay, clkin_dly_t, clkfbin_dly_t;
wire pll_unlock, pll_unlock1;
reg pll_locked_tmp1, pll_locked_tmp2;
reg lock_period;
reg pll_locked_tm, unlock_recover;
reg clkpll_jitter_unlock;
integer clkin_jit, REF_CLK_JITTER_MAX_tmp;
wire init_trig, clkpll_r;
reg clk0in=1'b0,clk1in=1'b0,clk2in=1'b0,clk3in=1'b0;
reg clk4in=1'b0,clk5in=1'b0,clk6in=1'b0;
reg clkpll_tmp1, clkpll;
reg clkfboutin=1'b0;
wire clkfbps_en;
reg chk_ok;
wire clk0ps_en, clk1ps_en, clk2ps_en, clk3ps_en;
wire clk4ps_en, clk5ps_en, clk6ps_en;
reg [3:0] d_rsel, clkfbout_rsel, clk0_rsel;
reg [3:0] d_fsel, clkfbout_fsel, clk0_fsel;
reg [6:0] d_fht, clkfbout_fht, clk0_fht;
reg [6:0] d_flt, clkfbout_flt, clk0_flt;
reg [5:0] clk0_dly_cnt;
reg [5:0] clk1_dly_cnt;
reg [5:0] clk2_dly_cnt;
reg [5:0] clk3_dly_cnt;
reg [5:0] clk4_dly_cnt;
reg [5:0] clk5_dly_cnt;
reg [5:0] clk6_dly_cnt;
real clk0_phase, clk0_duty;
real clk1_phase, clk1_duty;
real clk2_phase, clk2_duty;
real clk3_phase, clk3_duty;
real clk4_phase, clk4_duty;
real clk5_phase, clk5_duty;
real clk6_phase, clk6_duty;
real divclk_phase=0.000, divclk_duty=0.500;
real clkfbout_phase, clkfbout_duty=0.500;
// mem cells
reg [2:0] d_frac, clkfbout_frac, clk0_frac;
reg d_frac_en, clkfbout_frac_en, clk0_frac_en;
reg d_wf_f;
reg clkfbout_wf_f, clk0_wf_f;
reg d_wf_r;
reg clkfbout_wf_r, clk0_wf_r;
reg [2:0] d_mx, clkfbout_mx;
reg [2:0] clk0_mx, clk1_mx, clk2_mx, clk3_mx;
reg [2:0] clk4_mx, clk5_mx, clk6_mx;
reg divclk_e, clkfbin_e;
reg clkfbout_e;
reg clk0_e, clk1_e, clk2_e, clk3_e;
reg clk4_e, clk5_e, clk6_e;
reg divclk_nc, clkfbin_nc;
reg clkfbout_nc;
reg clk0_nc, clk1_nc, clk2_nc, clk3_nc;
reg clk4_nc, clk5_nc, clk6_nc;
reg [5:0] d_dt=0, clkfbout_dt=0;
reg [5:0] clk0_dt=0, clk1_dt=0, clk2_dt=0, clk3_dt=0;
reg [5:0] clk4_dt=0, clk5_dt=0, clk6_dt=0;
reg [2:0] d_pm_f;
reg [2:0] clkfbout_pm_f, clk0_pm_f;
reg [2:0] clkfbout_pm_r, clk0_pm_r;
reg [2:0] d_pm;
reg [2:0] clk1_pm, clk2_pm, clk3_pm;
reg [2:0] clk4_pm, clk5_pm, clk6_pm;
reg divclk_en=1, clkfbout_en=1;
reg clk0_en=1, clk1_en=1, clk2_en=1, clk3_en=1;
reg clk4_en=1, clk5_en=1, clk6_en=1;
reg [5:0] clkfbin_ht;
reg [5:0] clkfbout_ht;
reg [7:0] divclk_ht;
reg [5:0] clk0_ht, clk1_ht, clk2_ht, clk3_ht;
reg [5:0] clk4_ht, clk5_ht, clk6_ht;
reg [5:0] clkfbin_lt;
reg [7:0] divclk_lt;
reg [6:0] clkfbout_lt;
reg [6:0] clk0_lt, clk1_lt, clk2_lt, clk3_lt;
reg [6:0] clk4_lt, clk5_lt, clk6_lt;
//
real clkfbout_f_div=1.0;
real clk0_f_div;
integer d_div, clkfbout_div, clk0_div;
reg [5:0] clkfbout_dly_cnt;
reg [7:0] clkfbout_cnt;
reg [7:0] clk0_cnt;
reg [7:0] clk1_cnt, clk1_div;
reg [7:0] clk2_cnt, clk2_div;
reg [7:0] clk3_cnt, clk3_div;
reg [7:0] clk4_cnt, clk4_div;
reg [7:0] clk5_cnt, clk5_div;
reg [7:0] clk6_cnt, clk6_div;
integer divclk_cnt_max, clkfbout_cnt_max;
integer clk0_cnt_max, clk1_cnt_max, clk2_cnt_max, clk3_cnt_max;
integer clk4_cnt_max, clk5_cnt_max, clk6_cnt_max;
integer divclk_cnt_ht, clkfbout_cnt_ht;
integer clk0_cnt_ht, clk1_cnt_ht, clk2_cnt_ht, clk3_cnt_ht;
integer clk4_cnt_ht, clk5_cnt_ht, clk6_cnt_ht;
reg [7:0] divclk_div=8'b1, divclk_cnt=8'b0;
reg divclk_out, divclk_out_tmp;
reg [3:0] pll_cp, pll_res;
reg [1:0] pll_lfhf;
reg [1:0] pll_cpres = 2'b01;
reg [4:0] drp_lock_ref_dly;
reg [4:0] drp_lock_fb_dly;
reg [9:0] drp_lock_cnt;
reg [9:0] drp_unlock_cnt;
reg [9:0] drp_lock_sat_high;
wire clkinsel_tmp;
real clkin_chk_t1, clkin_chk_t2;
real clkin_chk_t1_r, clkin_chk_t2_r;
integer clkin_chk_t1_i, clkin_chk_t2_i;
reg init_chk;
reg rst_clkinsel_flag = 0;
wire pwrdwn_in1;
reg pwrdwn_in1_h = 0;
reg rst_input_r_h = 0;
reg pchk_clr = 0;
reg psincdec_chg = 0;
reg psincdec_chg_tmp = 0;
wire rst_input;
reg vcoflag = 0;
reg drp_updt = 1'b0;
real halfperiod_sum = 0.0;
integer halfperiod = 0;
reg clkvco_free = 1'b0;
integer ik10=0, ik11=0;
//drp monitor
reg den_r1 = 1'b0;
reg den_r2 = 1'b0;
reg dwe_r1 = 1'b0;
reg dwe_r2 = 1'b0;
reg [1:0] sfsm = 2'b01;
localparam FSM_IDLE = 2'b01;
localparam FSM_WAIT = 2'b10;
always @(posedge DCLK_in)
begin
// pipeline the DEN and DWE
den_r1 <= DEN_in;
dwe_r1 <= DWE_in;
den_r2 <= den_r1;
dwe_r2 <= dwe_r1;
// Check - if DEN or DWE is more than 1 DCLK
if ((den_r1 == 1'b1) && (den_r2 == 1'b1))
begin
$display("DRC Error : DEN is high for more than 1 DCLK. Instance %m");
$finish;
end
if ((dwe_r1 == 1'b1) && (dwe_r2 == 1'b1))
begin
$display("DRC Error : DWE is high for more than 1 DCLK. Instance %m");
$finish;
end
//After the 1st DEN pulse, check the DEN and DRDY.
case (sfsm)
FSM_IDLE:
begin
if(DEN_in == 1'b1)
sfsm <= FSM_WAIT;
end
FSM_WAIT:
begin
// After the 1st DEN, 4 cases can happen
// DEN DRDY NEXT STATE
// 0 0 FSM_WAIT - wait for DRDY
// 0 1 FSM_IDLE - normal operation
// 1 0 FSM_WAIT - display error and wait for DRDY
// 1 1 FSM_WAIT - normal operation. Per UG470, DEN and DRDY can be at the same cycle.
//Add the check for another DPREN pulse
if(DEN_in === 1'b1 && DRDY === 1'b0)
begin
$display("DRC Error : DEN is enabled before DRDY returns. Instance %m");
$finish;
end
//Add the check for another DWE pulse
if ((DWE_in === 1'b1) && (DEN_in === 1'b0))
begin
$display("DRC Error : DWE is enabled before DRDY returns. Instance %m");
$finish;
end
if ((DRDY === 1'b1) && (DEN_in === 1'b0))
begin
sfsm <= FSM_IDLE;
end
if ((DRDY === 1'b1) && (DEN_in === 1'b1))
begin
sfsm <= FSM_WAIT;
end
end
default:
begin
$display("DRC Error : Default state in DRP FSM. Instance %m");
$finish;
end
endcase
end // always @ (posedge DCLK)
//end drp monitor
`ifndef XIL_XECLIB
initial begin
#1;
if ($realtime == 0) begin
$display ("Error: [Unisim %s-1] Simulator resolution is set to a value greater than 1 ps. ", MODULE_NAME);
$display ("The simulator resolution must be set to 1ps or smaller. Instance %m");
#1 $finish;
end
end
`endif
`ifndef XIL_XECLIB
always @ (trig_attr) begin
#1;
if (CLKOUT0_DIVIDE_F_REG > 1.0000 && CLKOUT0_DIVIDE_F_REG < 2.0000) begin
$display("Error: [Unisim %s-2] The Attribute CLKOUT0_DIVIDE_F is set to %f. Values in range of greater than 1 and less than 2 are not allowed. Instance %m", MODULE_NAME, CLKOUT0_DIVIDE_F_REG);
#1 $finish;
end
CLKOUT0_DIVIDE_F_RND = $itor($rtoi((CLKOUT0_DIVIDE_F_REG + 0.0625) * 8.0)) / 8.0;
CLKFBOUT_MULT_F_RND = $itor($rtoi((CLKFBOUT_MULT_F_REG + 0.0625) * 8.0)) / 8.0;
if (CLKFBOUT_MULT_F_RND < CLKFBOUT_MULT_F_REG) begin
$display(" Warning [Unisim %s-35]: CLKFBOUT_MULT_F is not set to a resolution of .125 (%f) and is being rounded down to (%f). Instance %m ", MODULE_NAME, CLKFBOUT_MULT_F_REG, CLKFBOUT_MULT_F_RND);
end
else if (CLKFBOUT_MULT_F_RND > CLKFBOUT_MULT_F_REG) begin
$display(" Warning: [Unisim %s-36]: CLKFBOUT_MULT_F is not set to a resolution of .125 (%f) and is being rounded up to (%f). Instance %m ", MODULE_NAME, CLKFBOUT_MULT_F_REG, CLKFBOUT_MULT_F_RND);
end
if (CLKOUT0_DIVIDE_F_RND < CLKOUT0_DIVIDE_F_REG) begin
$display(" Warning: [Unisim %s-37]: CLKOUT0_DIVIDE_F is not set to a resolution of .125 (%f) and is being rounded down to (%f). Instance %m ", MODULE_NAME, CLKOUT0_DIVIDE_F_REG, CLKOUT0_DIVIDE_F_RND);
end
else if (CLKOUT0_DIVIDE_F_RND > CLKOUT0_DIVIDE_F_REG) begin
$display(" Warning: [Unisim %s-38]: CLKOUT0_DIVIDE_F is not set to a resolution of .125 (%f) and is being rounded up to (%f). Instance %m ", MODULE_NAME, CLKOUT0_DIVIDE_F_REG, CLKOUT0_DIVIDE_F_RND);
end
clkfbout_f_div = CLKFBOUT_MULT_F_RND;
attr_to_mc(clkfbout_pm_f, clkfbout_wf_f, clkfbout_frac, clkfbout_frac_en, clkfbout_wf_r, clkfbout_mx, clkfbout_e, clkfbout_nc, clkfbout_dt, clkfbout_pm_r, clkfbout_en, clkfbout_ht, clkfbout_lt, CLKFBOUT_MULT_F_REG, CLKFBOUT_PHASE_REG, clkfbout_duty);
ht_calc(clkfbout_frac, clkfbout_frac_en, clkfbout_e, clkfbout_ht, clkfbout_lt, clkfbout_f_div, clkfbout_rsel, clkfbout_fsel, clkfbout_fht, clkfbout_flt, clkfbout_cnt_max, clkfbout_cnt_ht, clkfbout_div);
clk0_f_div = CLKOUT0_DIVIDE_F_RND;
attr_to_mc(clk0_pm_f, clk0_wf_f, clk0_frac, clk0_frac_en, clk0_wf_r, clk0_mx, clk0_e, clk0_nc, clk0_dt, clk0_pm_r, clk0_en, clk0_ht, clk0_lt, CLKOUT0_DIVIDE_F_REG, CLKOUT0_PHASE_REG, CLKOUT0_DUTY_CYCLE_REG);
ht_calc(clk0_frac, clk0_frac_en, clk0_e, clk0_ht, clk0_lt, clk0_f_div, clk0_rsel, clk0_fsel, clk0_fht, clk0_flt, clk0_cnt_max, clk0_cnt_ht, clk0_div);
clk1_div = CLKOUT1_DIVIDE_REG;
attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk1_mx, clk1_e, clk1_nc, clk1_dt, clk1_pm, clk1_en, clk1_ht, clk1_lt, CLKOUT1_DIVIDE_REG, CLKOUT1_PHASE_REG, CLKOUT1_DUTY_CYCLE_REG);
ht_calc(3'b0, 1'b0, clk1_e, clk1_ht, clk1_lt, clk1_div, d_rsel, d_fsel, d_fht, d_flt, clk1_cnt_max, clk1_cnt_ht, d_div);
clk2_div = CLKOUT2_DIVIDE_REG;
attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk2_mx, clk2_e, clk2_nc, clk2_dt, clk2_pm, clk2_en, clk2_ht, clk2_lt, CLKOUT2_DIVIDE_REG, CLKOUT2_PHASE_REG, CLKOUT2_DUTY_CYCLE_REG);
ht_calc(3'b0, 1'b0, clk2_e, clk2_ht, clk2_lt, clk2_div, d_rsel, d_fsel, d_fht, d_flt, clk2_cnt_max, clk2_cnt_ht, d_div);
clk3_div = CLKOUT3_DIVIDE_REG;
attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk3_mx, clk3_e, clk3_nc, clk3_dt, clk3_pm, clk3_en, clk3_ht, clk3_lt, CLKOUT3_DIVIDE_REG, CLKOUT3_PHASE_REG, CLKOUT3_DUTY_CYCLE_REG);
ht_calc(3'b0, 1'b0, clk3_e, clk3_ht, clk3_lt, clk3_div, d_rsel, d_fsel, d_fht, d_flt, clk3_cnt_max, clk3_cnt_ht, d_div);
clk4_div = CLKOUT4_DIVIDE_REG;
attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk4_mx, clk4_e, clk4_nc, clk4_dt, clk4_pm, clk4_en, clk4_ht, clk4_lt, CLKOUT4_DIVIDE_REG, CLKOUT4_PHASE_REG, CLKOUT4_DUTY_CYCLE_REG);
ht_calc(3'b0, 1'b0, clk4_e, clk4_ht, clk4_lt, clk4_div, d_rsel, d_fsel, d_fht, d_flt, clk4_cnt_max, clk4_cnt_ht, d_div);
clk5_div = CLKOUT5_DIVIDE_REG;
attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk5_mx, clk5_e, clk5_nc, clk5_dt, clk5_pm, clk5_en, clk5_ht, clk5_lt, CLKOUT5_DIVIDE_REG, CLKOUT5_PHASE_REG, CLKOUT5_DUTY_CYCLE_REG);
ht_calc(3'b0, 1'b0, clk5_e, clk5_ht, clk5_lt, clk5_div, d_rsel, d_fsel, d_fht, d_flt, clk5_cnt_max, clk5_cnt_ht, d_div);
clk6_div = CLKOUT6_DIVIDE_REG;
attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, clk6_mx, clk6_e, clk6_nc, clk6_dt, clk6_pm, clk6_en, clk6_ht, clk6_lt, CLKOUT6_DIVIDE_REG, CLKOUT6_PHASE_REG, CLKOUT6_DUTY_CYCLE_REG);
ht_calc(3'b0, 1'b0, clk6_e, clk6_ht, clk6_lt, clk6_div, d_rsel, d_fsel, d_fht, d_flt, clk6_cnt_max, clk6_cnt_ht, d_div);
divclk_div = DIVCLK_DIVIDE_REG;
attr_to_mc(d_pm_f, d_wf_f, d_frac, d_frac_en, d_wf_r, d_mx, divclk_e, divclk_nc, d_dt, d_pm, divclk_en, divclk_ht, divclk_lt, DIVCLK_DIVIDE_REG, 0.000, 0.500);
ht_calc(3'b0, 1'b0, divclk_e, divclk_ht, divclk_lt, divclk_div, d_rsel, d_fsel, d_fht, d_flt, divclk_cnt_max, divclk_cnt_ht, d_div);
ps_in_init = 0;
ps_in_ps = ps_in_init;
ps_cnt = 0;
clk0_fps_en = (CLKOUT0_USE_FINE_PS_REG == "TRUE");
clk1_fps_en = (CLKOUT1_USE_FINE_PS_REG == "TRUE");
clk2_fps_en = (CLKOUT2_USE_FINE_PS_REG == "TRUE");
clk3_fps_en = (CLKOUT3_USE_FINE_PS_REG == "TRUE");
clk4_fps_en = (CLKOUT4_USE_FINE_PS_REG == "TRUE");
clk5_fps_en = (CLKOUT5_USE_FINE_PS_REG == "TRUE");
clk6_fps_en = (CLKOUT6_USE_FINE_PS_REG == "TRUE");
clkfbout_fps_en = (CLKFBOUT_USE_FINE_PS_REG == "TRUE");
fps_en = clk0_fps_en || clk1_fps_en || clk2_fps_en || clk3_fps_en
|| clk4_fps_en || clk5_fps_en || clk6_fps_en || clkfbout_fps_en;
if (clk0_frac_en == 1'b1) begin
if (CLKOUT0_DUTY_CYCLE_REG != 0.5) begin
$display("Error: [Unisim %s-3] The Attribute CLKOUT0_DUTY_CYCLE is set to %f. This attribute should be set to 0.5 when CLKOUT0_DIVIDE_F has fraction part. Instance %m", MODULE_NAME, CLKOUT0_DUTY_CYCLE_REG);
#1 $finish;
end
end
pll_lfhf = 2'b00;
if (BANDWIDTH_REG === "LOW")
case (clkfbout_div)
1 : begin pll_cp = 4'b0010; pll_res = 4'b1111; end
2 : begin pll_cp = 4'b0010 ; pll_res = 4'b1111 ; end
3 : begin pll_cp = 4'b0010 ; pll_res = 4'b1111 ; end
4 : begin pll_cp = 4'b0010 ; pll_res = 4'b1111 ; end
5 : begin pll_cp = 4'b0010 ; pll_res = 4'b0111 ; end
6 : begin pll_cp = 4'b0010 ; pll_res = 4'b1011 ; end
7 : begin pll_cp = 4'b0010 ; pll_res = 4'b1101 ; end
8 : begin pll_cp = 4'b0010 ; pll_res = 4'b0011 ; end
9 : begin pll_cp = 4'b0010 ; pll_res = 4'b0101 ; end
10 : begin pll_cp = 4'b0010 ; pll_res = 4'b0101 ; end
11 : begin pll_cp = 4'b0010 ; pll_res = 4'b1001 ; end
12 : begin pll_cp = 4'b0010 ; pll_res = 4'b1110 ; end
13 : begin pll_cp = 4'b0010 ; pll_res = 4'b1110 ; end
14 : begin pll_cp = 4'b0010 ; pll_res = 4'b1110 ; end
15 : begin pll_cp = 4'b0010 ; pll_res = 4'b1110 ; end
16 : begin pll_cp = 4'b0010 ; pll_res = 4'b0001 ; end
17 : begin pll_cp = 4'b0010 ; pll_res = 4'b0001 ; end
18 : begin pll_cp = 4'b0010 ; pll_res = 4'b0001 ; end
19 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end
20 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end
21 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end
22 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end
23 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end
24 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end
25 : begin pll_cp = 4'b0010 ; pll_res = 4'b0110 ; end
26 : begin pll_cp = 4'b0010 ; pll_res = 4'b1010 ; end
27 : begin pll_cp = 4'b0010 ; pll_res = 4'b1010 ; end
28 : begin pll_cp = 4'b0010 ; pll_res = 4'b1010 ; end
29 : begin pll_cp = 4'b0010 ; pll_res = 4'b1010 ; end
30 : begin pll_cp = 4'b0010 ; pll_res = 4'b1010 ; end
31 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
32 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
33 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
34 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
35 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
36 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
37 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
38 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
39 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
40 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
41 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
42 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
43 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
44 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
45 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
46 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
47 : begin pll_cp = 4'b0010 ; pll_res = 4'b1100 ; end
48 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
49 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
50 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
51 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
52 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
53 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
54 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
55 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
56 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
57 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
58 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
59 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
60 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
61 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
62 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
63 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
64 : begin pll_cp = 4'b0010 ; pll_res = 4'b0010 ; end
endcase
else if (BANDWIDTH_REG === "HIGH")
case (clkfbout_div)
1 : begin pll_cp = 4'b0010; pll_res = 4'b1111; end
2 : begin pll_cp = 4'b0100 ; pll_res = 4'b1111 ; end
3 : begin pll_cp = 4'b0101 ; pll_res = 4'b1011 ; end
4 : begin pll_cp = 4'b0111 ; pll_res = 4'b0111 ; end
5 : begin pll_cp = 4'b1101 ; pll_res = 4'b0111 ; end
6 : begin pll_cp = 4'b1110 ; pll_res = 4'b1011 ; end
7 : begin pll_cp = 4'b1110 ; pll_res = 4'b1101 ; end
8 : begin pll_cp = 4'b1111 ; pll_res = 4'b0011 ; end
9 : begin pll_cp = 4'b1110 ; pll_res = 4'b0101 ; end
10 : begin pll_cp = 4'b1111 ; pll_res = 4'b0101 ; end
11 : begin pll_cp = 4'b1111 ; pll_res = 4'b1001 ; end
12 : begin pll_cp = 4'b1101 ; pll_res = 4'b0001 ; end
13 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end
14 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end
15 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end
16 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end
17 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end
18 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end
19 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
20 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
21 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
22 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end
23 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end
24 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end
25 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end
26 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
27 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
28 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
29 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
30 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
31 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
32 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
33 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
34 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
35 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
36 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
37 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end
38 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end
39 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end
40 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end
41 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end
42 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end
43 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end
44 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end
45 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end
46 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end
47 : begin pll_cp = 4'b0111 ; pll_res = 4'b0001 ; end
48 : begin pll_cp = 4'b0111 ; pll_res = 4'b0001 ; end
49 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end
50 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end
51 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end
52 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end
53 : begin pll_cp = 4'b0110 ; pll_res = 4'b0001 ; end
54 : begin pll_cp = 4'b0110 ; pll_res = 4'b0001 ; end
55 : begin pll_cp = 4'b0101 ; pll_res = 4'b0110 ; end
56 : begin pll_cp = 4'b0101 ; pll_res = 4'b0110 ; end
57 : begin pll_cp = 4'b0101 ; pll_res = 4'b0110 ; end
58 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end
59 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end
60 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end
61 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end
62 : begin pll_cp = 4'b0100 ; pll_res = 4'b1010 ; end
63 : begin pll_cp = 4'b0011 ; pll_res = 4'b1100 ; end
64 : begin pll_cp = 4'b0011 ; pll_res = 4'b1100 ; end
endcase
else if (BANDWIDTH_REG === "OPTIMIZED")
case (clkfbout_div)
1 : begin pll_cp = 4'b0010; pll_res = 4'b1111; end
2 : begin pll_cp = 4'b0100 ; pll_res = 4'b1111 ; end
3 : begin pll_cp = 4'b0101 ; pll_res = 4'b1011 ; end
4 : begin pll_cp = 4'b0111 ; pll_res = 4'b0111 ; end
5 : begin pll_cp = 4'b1101 ; pll_res = 4'b0111 ; end
6 : begin pll_cp = 4'b1110 ; pll_res = 4'b1011 ; end
7 : begin pll_cp = 4'b1110 ; pll_res = 4'b1101 ; end
8 : begin pll_cp = 4'b1111 ; pll_res = 4'b0011 ; end
9 : begin pll_cp = 4'b1110 ; pll_res = 4'b0101 ; end
10 : begin pll_cp = 4'b1111 ; pll_res = 4'b0101 ; end
11 : begin pll_cp = 4'b1111 ; pll_res = 4'b1001 ; end
12 : begin pll_cp = 4'b1101 ; pll_res = 4'b0001 ; end
13 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end
14 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end
15 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end
16 : begin pll_cp = 4'b1111; pll_res = 4'b1001; end
17 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end
18 : begin pll_cp = 4'b1111; pll_res = 4'b0101; end
19 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
20 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
21 : begin pll_cp = 4'b1100; pll_res = 4'b0001; end
22 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end
23 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end
24 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end
25 : begin pll_cp = 4'b0101; pll_res = 4'b1100; end
26 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
27 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
28 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
29 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
30 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
31 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
32 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
33 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
34 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
35 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
36 : begin pll_cp = 4'b0011; pll_res = 4'b0100; end
37 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end
38 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end
39 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end
40 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end
41 : begin pll_cp = 4'b0011 ; pll_res = 4'b0100 ; end
42 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end
43 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end
44 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end
45 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end
46 : begin pll_cp = 4'b0010 ; pll_res = 4'b1000 ; end
47 : begin pll_cp = 4'b0111 ; pll_res = 4'b0001 ; end
48 : begin pll_cp = 4'b0111 ; pll_res = 4'b0001 ; end
49 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end
50 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end
51 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end
52 : begin pll_cp = 4'b0100 ; pll_res = 4'b1100 ; end
53 : begin pll_cp = 4'b0110 ; pll_res = 4'b0001 ; end
54 : begin pll_cp = 4'b0110 ; pll_res = 4'b0001 ; end
55 : begin pll_cp = 4'b0101 ; pll_res = 4'b0110 ; end
56 : begin pll_cp = 4'b0101 ; pll_res = 4'b0110 ; end
57 : begin pll_cp = 4'b0101 ; pll_res = 4'b0110 ; end
58 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end
59 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end
60 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end
61 : begin pll_cp = 4'b0010 ; pll_res = 4'b0100 ; end
62 : begin pll_cp = 4'b0100 ; pll_res = 4'b1010 ; end
63 : begin pll_cp = 4'b0011 ; pll_res = 4'b1100 ; end
64 : begin pll_cp = 4'b0011 ; pll_res = 4'b1100 ; end
endcase
case (clkfbout_div)
1 : begin drp_lock_ref_dly = 5'd6;
drp_lock_fb_dly = 5'd6;
drp_lock_cnt = 10'd1000;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
2 : begin drp_lock_ref_dly = 5'd6;
drp_lock_fb_dly = 5'd6;
drp_lock_cnt = 10'd1000;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
3 : begin drp_lock_ref_dly = 5'd8;
drp_lock_fb_dly = 5'd8;
drp_lock_cnt = 10'd1000;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
4 : begin drp_lock_ref_dly = 5'd11;
drp_lock_fb_dly = 5'd11;
drp_lock_cnt = 10'd1000;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
5 : begin drp_lock_ref_dly = 5'd14;
drp_lock_fb_dly = 5'd14;
drp_lock_cnt = 10'd1000;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
6 : begin drp_lock_ref_dly = 5'd17;
drp_lock_fb_dly = 5'd17;
drp_lock_cnt = 10'd1000;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
7 : begin drp_lock_ref_dly = 5'd19;
drp_lock_fb_dly = 5'd19;
drp_lock_cnt = 10'd1000;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
8 : begin drp_lock_ref_dly = 5'd22;
drp_lock_fb_dly = 5'd22;
drp_lock_cnt = 10'd1000;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
9 : begin drp_lock_ref_dly = 5'd25;
drp_lock_fb_dly = 5'd25;
drp_lock_cnt = 10'd1000;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
10 : begin drp_lock_ref_dly = 5'd28;
drp_lock_fb_dly = 5'd28;
drp_lock_cnt = 10'd1000;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
11 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd900;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
12 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd825;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
13 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd750;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
14 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd700;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
15 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd650;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
16 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd625;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
17 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd575;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
18 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd550;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
19 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd525;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
20 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd500;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
21 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd475;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
22 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd450;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
23 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd425;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
24 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd400;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
25 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd400;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
26 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd375;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
27 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd350;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
28 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd350;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
29 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd325;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
30 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd325;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
31 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd300;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
32 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd300;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
33 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd300;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
34 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd275;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
35 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd275;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
36 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd275;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
37 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
38 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
39 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
40 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
41 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
42 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
43 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
44 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
45 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
46 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
47 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
48 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
49 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
50 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
51 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
52 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
53 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
54 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
55 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
56 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
57 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
58 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
59 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
60 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
61 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
62 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
63 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
64 : begin drp_lock_ref_dly = 5'd31;
drp_lock_fb_dly = 5'd31;
drp_lock_cnt = 10'd250;
drp_lock_sat_high = 10'd1001;
drp_unlock_cnt = 10'd1; end
endcase
tmp_string = "DIVCLK_DIVIDE";
chk_ok = para_int_range_chk (DIVCLK_DIVIDE_REG, tmp_string, D_MIN, D_MAX);
tmp_string = "CLKFBOUT_MULT_F";
chk_ok = para_real_range_chk (CLKFBOUT_MULT_F_RND, tmp_string, M_MIN, M_MAX);
tmp_string = "CLKOUT6_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT6_DIVIDE_REG, CLKOUT6_DUTY_CYCLE_REG, tmp_string);
if(clk0_frac_en == 1'b0) begin
tmp_string = "CLKOUT0_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT0_DIVIDE_F_RND, CLKOUT0_DUTY_CYCLE_REG, tmp_string);
end
tmp_string = "CLKOUT5_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT5_DIVIDE_REG, CLKOUT5_DUTY_CYCLE_REG, tmp_string);
tmp_string = "CLKOUT1_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT1_DIVIDE_REG, CLKOUT1_DUTY_CYCLE_REG, tmp_string);
tmp_string = "CLKOUT2_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT2_DIVIDE_REG, CLKOUT2_DUTY_CYCLE_REG, tmp_string);
tmp_string = "CLKOUT3_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT3_DIVIDE_REG, CLKOUT3_DUTY_CYCLE_REG, tmp_string);
tmp_string = "CLKOUT4_DUTY_CYCLE";
chk_ok = clkout_duty_chk (CLKOUT4_DIVIDE_REG, CLKOUT4_DUTY_CYCLE_REG, tmp_string);
period_vco_max = 1000000 / VCOCLK_FREQ_MIN_REG;
period_vco_min = 1000000 / VCOCLK_FREQ_MAX_REG;
period_vco_target = 1000000 / VCOCLK_FREQ_TARGET;
period_vco_target_half = period_vco_target / 2;
fb_delay_max = MAX_FEEDBACK_DELAY * MAX_FEEDBACK_DELAY_SCALE;
clk0f_product = CLKOUT0_DIVIDE_F_RND * 8;
pll_lock_time = 12;
lock_period_time = 10;
if (clkfbout_frac_en == 1'b1) begin
md_product = clkfbout_div * DIVCLK_DIVIDE_REG;
m_product = clkfbout_div;
mf_product = CLKFBOUT_MULT_F_RND * 8;
clkout_en_val = mf_product - 1;
m_product2 = clkfbout_div / 2;
clkout_en_time = mf_product + 4 + pll_lock_time;
locked_en_time = md_product + clkout_en_time + 2;
lock_cnt_max = locked_en_time + 16;
end
else begin
md_product = clkfbout_div * DIVCLK_DIVIDE_REG;
m_product = clkfbout_div;
mf_product = CLKFBOUT_MULT_F_RND * 8;
m_product2 = clkfbout_div / 2;
clkout_en_val = m_product;
clkout_en_time = md_product + pll_lock_time;
locked_en_time = md_product + clkout_en_time + 2;
lock_cnt_max = locked_en_time + 16;
end
REF_CLK_JITTER_MAX_tmp = REF_CLK_JITTER_MAX;
ht_calc(clkfbout_frac, clkfbout_frac_en, clkfbout_e, clkfbout_ht, clkfbout_lt, clkfbout_f_div, clkfbout_rsel, clkfbout_fsel, clkfbout_fht, clkfbout_flt, clkfbout_cnt_max, clkfbout_cnt_ht, clkfbout_div);
ht_calc(clk0_frac, clk0_frac_en, clk0_e, clk0_ht, clk0_lt, clk0_f_div, clk0_rsel, clk0_fsel, clk0_fht, clk0_flt, clk0_cnt_max, clk0_cnt_ht, clk0_div);
divclk_div = DIVCLK_DIVIDE_REG;
dr_sram[6] = {clk5_pm[2:0], clk5_en, clk5_ht[5:0], clk5_lt[5:0]};
dr_sram[7] = {2'bx, clk0_pm_f[2:0], clk0_wf_f,
2'b0, clk5_e, clk5_nc, clk5_dt[5:0]};
dr_sram[8] = {clk0_pm_r[2:0], clk0_en, clk0_ht[5:0], clk0_lt[5:0]};
dr_sram[9] = {1'bx, clk0_frac[2:0], clk0_frac_en, clk0_wf_r,
2'b0, clk0_e, clk0_nc, clk0_dt[5:0]};
dr_sram[10] = {clk1_pm[2:0], clk1_en, clk1_ht[5:0], clk1_lt[5:0]};
dr_sram[11] = {6'bx, 2'b0, clk1_e, clk1_nc, clk1_dt[5:0]};
dr_sram[12] = {clk2_pm[2:0], clk2_en, clk2_ht[5:0], clk2_lt[5:0]};
dr_sram[13] = {6'bx, 2'b0, clk2_e, clk2_nc, clk2_dt[5:0]};
dr_sram[14] = {clk3_pm[2:0], clk3_en, clk3_ht[5:0], clk3_lt[5:0]};
dr_sram[15] = {6'bx, 2'b0, clk3_e, clk3_nc, clk3_dt[5:0]};
dr_sram[16] = {clk4_pm[2:0], clk4_en, clk4_ht[5:0], clk4_lt[5:0]};
dr_sram[17] = {6'bx, 2'b0, clk4_e, clk4_nc, clk4_dt[5:0]};
dr_sram[18] = {clk6_pm[2:0], clk6_en, clk6_ht[5:0], clk6_lt[5:0]};
dr_sram[19] = {2'bx, clkfbout_pm_f[2:0], clkfbout_wf_f,
2'b0, clk6_e, clk6_nc, clk6_dt[5:0]};
dr_sram[20] = {clkfbout_pm_r[2:0], clkfbout_en, clkfbout_ht[5:0], clkfbout_lt[5:0]};
dr_sram[21] = {1'bx, clkfbout_frac[2:0], clkfbout_frac_en,
clkfbout_wf_r, 2'b0, clkfbout_e, clkfbout_nc, clkfbout_dt[5:0]};
dr_sram[22] = {2'bx, divclk_e, divclk_nc, divclk_ht[5:0], divclk_lt[5:0]};
dr_sram[23] = {2'bx, clkfbin_e, clkfbin_nc, clkfbin_ht[5:0], clkfbin_lt[5:0]};
dr_sram[24] = {6'bx, drp_lock_cnt};
dr_sram[25] = {1'bx, drp_lock_fb_dly, drp_unlock_cnt};
dr_sram[26] = {1'bx, drp_lock_ref_dly, drp_lock_sat_high};
dr_sram[40] = {1'b1, 2'bx, 2'b11, 2'bx, 2'b11, 2'bx, 2'b11, 2'bx, 1'b1};
dr_sram[78] = {pll_cp[3], 2'bx, pll_cp[2:1], 2'bx, pll_cp[0], 1'b0, 2'bx, pll_cpres, 3'bx};
dr_sram[79] = {pll_res[3], 2'bx, pll_res[2:1], 2'bx, pll_res[0], pll_lfhf[1], 2'bx, pll_lfhf[0], 4'bx};
dr_sram[116] = {5'bx, 6'b0, 5'b00001};
end
`endif
initial begin
clkpll_jitter_unlock = 0;
clkinstopped_vco_f = 0;
rst_clkfbstopped = 0;
rst_clkinstopped = 0;
rst_clkfbstopped_lk = 0;
rst_clkinstopped_lk = 0;
clkfbin_stop_tmp = 0;
clkin_stop_tmp = 0;
clkvco_lk_en = 0;
clkvco_lk_dly_tmp = 0;
clkin_osc = 0;
clkfbin_osc = 0;
clkin_p = 0;
clkfbin_p = 0;
divclk_div = DIVCLK_DIVIDE_REG;
ps_lock = 0;
ps_lock_dly = 0;
PSDONE_out = 1'b0;
rst_int = 0;
CLKINSTOPPED_out = 1'b0;
clkinstopped_out1 = 0;
CLKFBSTOPPED_out = 1'b0;
clkfbstopped_out1 = 0;
clkin_period[0] = 0;
clkin_period[1] = 0;
clkin_period[2] = 0;
clkin_period[3] = 0;
clkin_period[4] = 0;
clkin_period_tmp_t = 0;
period_avg = 100000;
period_fb = 100000;
clkin_lost_val = 2;
clkfbin_lost_val = 2;
fb_delay = 0;
clkvco_delay = 0;
val_tmp = 0;
dly_tmp = 0;
fb_comp_delay = 0;
clkfbout_pm_rl = 0;
period_vco = 0;
period_vco1 = 0;
period_vco2 = 0;
period_vco3 = 0;
period_vco4 = 0;
period_vco5 = 0;
period_vco6 = 0;
period_vco7 = 0;
period_vco_half = 0;
period_vco_half1 = 0;
period_vco_half_rm = 0;
period_vco_half_rm1 = 0;
period_vco_half_rm2 = 0;
period_vco_rm = 0;
period_vco_cmp_cnt = 0;
period_vco_cmp_flag = 0;
period_ps = 0;
period_ps_old = 0;
clkfbout_frac_ht = 0;
clkfbout_frac_lt = 0;
clk0_frac_ht = 0;
clk0_frac_lt = 0;
clk0_frac_ht_rl = 0.0;
clk0_frac_lt_rl = 0.0;
clkvco_rm_cnt = 0;
fb_delay_found = 1'b0;
fb_delay_found_tmp = 1'b0;
clkin_edge = 0;
delay_edge = 0;
fbclk_tmp = 0;
clkfbout_tst = 1'b0;
clkout_en = 0;
clkout_en0 = 0;
clkout_en_t = 0;
clkout_en0_tmp = 0;
clkout_en1 = 0;
pll_locked_tmp1 = 0;
pll_locked_tmp2 = 0;
pll_locked_tm = 0;
pll_locked_delay = 0;
unlock_recover = 0;
clkin_jit = 0;
clkin_lock_cnt = 0;
lock_period = 0;
rst_edge = 0;
rst_ht = 0;
DRDY_out = 1'b0;
LOCKED_out = 1'b0;
DO_out = 16'b0;
drp_lock = 0;
drp_lock_lat_cnt = 0;
clk0_dly_cnt = 6'b0;
clk1_dly_cnt = 6'b0;
clk2_dly_cnt = 6'b0;
clk3_dly_cnt = 6'b0;
clk4_dly_cnt = 6'b0;
clk5_dly_cnt = 6'b0;
clk6_dly_cnt = 6'b0;
clkfbout_dly_cnt = 6'b0;
clk0_cnt = 8'b0;
clk1_cnt = 8'b0;
clk2_cnt = 8'b0;
clk3_cnt = 8'b0;
clk4_cnt = 8'b0;
clk5_cnt = 8'b0;
clk6_cnt = 8'b0;
clkfbout_cnt = 8'b0;
divclk_cnt = 8'b0;
CLKOUT0_out = 1'b0;
CLKOUT0B_out = 1'b1;
CLKOUT1_out = 1'b0;
CLKOUT1B_out = 1'b1;
CLKOUT2_out = 1'b0;
CLKOUT2B_out = 1'b1;
CLKOUT3_out = 1'b0;
CLKOUT3B_out = 1'b1;
CLKOUT4_out = 1'b0;
CLKOUT5_out = 1'b0;
CLKOUT6_out = 1'b0;
clk1_out = 0;
clk2_out = 0;
clk3_out = 0;
clk4_out = 0;
clk5_out = 0;
clk6_out = 0;
CLKFBOUT_out = 1'b0;
CLKFBOUTB_out = 1'b1;
divclk_out = 0;
divclk_out_tmp = 0;
clkin_osc = 0;
clkfbin_osc = 0;
clkin_p = 0;
clkfbin_p = 0;
pwron_int = 1;
#100000 pwron_int = 0;
end
assign #2 clkinsel_tmp = CLKINSEL_in;
assign glock = (STARTUP_WAIT_BIN == STARTUP_WAIT_FALSE) || LOCKED;
assign (weak1, strong0) glbl.PLL_LOCKG = (glock == 0) ? 0 : p_up;
initial begin
init_chk = 0;
#2;
init_chk = 1;
#2;
init_chk = 0;
end
always @(CLKINSEL_in or posedge init_chk ) begin
#1;
if (init_chk == 0 && $time > 3 && rst_int === 0 && (clkinsel_tmp === 0 || clkinsel_tmp === 1)) begin
$display("Error: [Unisim %s-4] Input clock can only be switched when RST=1. CLKINSEL at time %t changed when RST=0. Instance %m", MODULE_NAME, $time);
#1 $finish;
end
clkin_chk_t1_r = 1000.000 / CLKIN_FREQ_MIN_REG;
clkin_chk_t1_i = $rtoi(1000.0 * clkin_chk_t1_r);
clkin_chk_t1 = 0.001 * clkin_chk_t1_i;
clkin_chk_t2_r = 1000.000 / CLKIN_FREQ_MAX_REG;
clkin_chk_t2_i = $rtoi(1000.0 * clkin_chk_t2_r);
clkin_chk_t2 = 0.001 * clkin_chk_t2_i;
if (CLKINSEL_in === 1 && $time > 1 || CLKINSEL_in !== 0 && init_chk == 1) begin
if (CLKIN1_PERIOD_REG * 1000 > clkin_chk_t1_i || CLKIN1_PERIOD_REG * 1000 < clkin_chk_t2_i) begin
$display ("Error: [Unisim %s-5] The attribute CLKIN1_PERIOD is set to %f ns and out of the allowed range %f ns to %f ns set by CLKIN_FREQ_MIN/MAX. Instance %m", MODULE_NAME, CLKIN1_PERIOD_REG, clkin_chk_t2, clkin_chk_t1);
#1 $finish;
end
end
else if (CLKINSEL_in ===0 && $time > 1 || init_chk == 1 && clkinsel_tmp === 0 ) begin
if (CLKIN2_PERIOD_REG * 1000 > clkin_chk_t1_i || CLKIN2_PERIOD_REG * 1000 < clkin_chk_t2_i) begin
$display ("Error: [Unisim %s-6] The attribute CLKIN2_PERIOD is set to %f ns and out of the allowed range %f ns to %f ns set by CLKIN_FREQ_MIN/MAX. Instance %m", MODULE_NAME, CLKIN2_PERIOD_REG, clkin_chk_t2, clkin_chk_t1);
#1 $finish;
end
end
period_clkin = (CLKINSEL_in === 0) ? CLKIN2_PERIOD_REG : CLKIN1_PERIOD_REG;
if (period_clkin == 0) period_clkin = 10;
if (period_clkin < MAX_FEEDBACK_DELAY)
fb_delay_max = period_clkin * MAX_FEEDBACK_DELAY_SCALE;
else
fb_delay_max = MAX_FEEDBACK_DELAY * MAX_FEEDBACK_DELAY_SCALE;
clkvco_freq_init_chk = (1000.0 * CLKFBOUT_MULT_F_RND) / (period_clkin * DIVCLK_DIVIDE_REG);
if (clkvco_freq_init_chk > VCOCLK_FREQ_MAX_REG || clkvco_freq_init_chk < VCOCLK_FREQ_MIN_REG) begin
if (clkinsel_tmp === 0 && $time > 1 || clkinsel_tmp === 0 && init_chk === 1) begin
$display ("Error: [Unisim %s-7] The calculated VCO frequency=%f Mhz. This exceeds the permitted VCO frequency range of %f Mhz to %f Mhz set by VCOCLK_FREQ_MIN/MAX. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT_F / (DIVCLK_DIVIDE * CLKIN2_PERIOD). Please adjust the attributes to the permitted VCO frequency range. Instance %m", MODULE_NAME, clkvco_freq_init_chk, VCOCLK_FREQ_MIN_REG, VCOCLK_FREQ_MAX_REG);
#1 $finish;
end
else if (clkinsel_tmp === 1 && $time > 1 || clkinsel_tmp !== 0 && init_chk === 1) begin
$display ("Error: [Unisim %s-8] The calculated VCO frequency=%f Mhz. This exceeds the permitted VCO frequency range of %f Mhz to %f Mhz set by VCOCLK_FREQ_MIN/MAX. The VCO frequency is calculated with formula: VCO frequency = CLKFBOUT_MULT_F / (DIVCLK_DIVIDE * CLKIN1_PERIOD). Please adjust the attributes to the permitted VCO frequency range. Instance %m", MODULE_NAME, clkvco_freq_init_chk, VCOCLK_FREQ_MIN_REG, VCOCLK_FREQ_MAX_REG);
#1 $finish;
end
end
end
assign init_trig = 1;
assign clkpll_r = (CLKINSEL_in) ? CLKIN1_in : CLKIN2_in;
assign pwrdwn_in1 = (PWRDWN_in === 1) ? 1 : 0;
assign rst_input = (RST_in === 1 | pwrdwn_in1 === 1) ? 1 : 0;
always @(posedge clkpll_r or posedge rst_input)
if (rst_input)
rst_int <= 1;
else
rst_int <= rst_input ;
assign rst_in_o = (rst_int || rst_clkfbstopped || rst_clkinstopped || clkpll_jitter_unlock);
//simprim_rst_h
always @(posedge pwrdwn_in1 or posedge pchk_clr)
if (pwrdwn_in1)
pwrdwn_in1_h <= 1;
else if (pchk_clr)
pwrdwn_in1_h <= 0;
always @(posedge RST_in or posedge pchk_clr)
if (RST_in)
rst_input_r_h <= 1;
else if (pchk_clr)
rst_input_r_h <= 0;
always @(rst_input )
if (rst_input==1) begin
rst_edge = $time;
pchk_clr = 0;
end
else if (rst_input==0 && rst_edge > 1) begin
rst_ht = $time - rst_edge;
if (rst_ht < 1500) begin
if (rst_input_r_h == 1 && pwrdwn_in1_h == 1)
$display("Warning: [Unisim %s-11] RST and PWRDWN at time %t must be asserted at least for 1.5 ns (actual %.3f ns) . Instance %m ", MODULE_NAME, $time, rst_ht/1000.0);
else if (rst_input_r_h == 1 && pwrdwn_in1_h == 0)
$display("Warning: [Unisim %s-12] RST at time %t must be asserted at least for 1.5 ns (actual %.3f ns). Instance %m", MODULE_NAME, $time, rst_ht/1000.0);
else if (rst_input_r_h == 0 && pwrdwn_in1_h == 1)
$display("Warning: [Unisim %s-13] PWRDWN at time %t must be asserted at least for 1.5 ns (actual %.3f ns). Instance %m", MODULE_NAME, $time, rst_ht/1000.0);
end
pchk_clr = 1;
end
//endsimprim_rst_h
//
// DRP port read and write
//
always @ (*) begin
DO_out = dr_sram[daddr_lat];
end
always @(posedge DCLK_in or posedge glblGSR)
if (glblGSR == 1) begin
drp_lock <= 0;
drp_lock_lat_cnt <= 0;
drp_updt <= 1'b0;
end
else begin
if (~RST_in && drp_updt) drp_updt <= 1'b0;
if (DEN_in == 1) begin
valid_daddr = addr_is_valid(DADDR_in);
if (drp_lock == 1) begin
$display("Error: [Unisim %s-14] DEN is high at time %t. Need wait for DRDY signal before next read/write operation through DRP. Instance %m ", MODULE_NAME, $time);
end
else begin
drp_lock <= 1;
drp_lock_lat_cnt <= drp_lock_lat_cnt + 1;
daddr_lat <= DADDR_in;
end
if (~valid_daddr) $display("Warning: [Unisim %s-15] Address DADDR=%b is unsupported at time %t. Instance %m ", MODULE_NAME, DADDR_in, $time);
if (DWE_in == 1) begin // write process
if (rst_input == 1) begin
if (valid_daddr) dr_sram[DADDR_in] <= DI_in;
if (valid_daddr || drp_updt) drp_updt <= 1'b1;
if (DADDR_in == 7'd6)
lower_drp(clk5_pm, clk5_en, clk5_ht, clk5_lt, DI_in);
else if (DADDR_in == 7'd7)
upper_mix_drp(clk0_pm_f, clk0_wf_f, clk5_mx, clk5_e, clk5_nc, clk5_dt, DI_in);
else if (DADDR_in == 7'd8)
lower_drp(clk0_pm_r, clk0_en, clk0_ht, clk0_lt, DI_in);
else if (DADDR_in == 7'd9) begin
upper_frac_drp(clk0_frac, clk0_frac_en, clk0_wf_r, clk0_mx, clk0_e, clk0_nc, clk0_dt, DI_in);
end else if (DADDR_in == 7'd10)
lower_drp(clk1_pm, clk1_en, clk1_ht, clk1_lt, DI_in);
else if (DADDR_in == 7'd11)
upper_drp(clk1_mx, clk1_e, clk1_nc, clk1_dt, DI_in);
else if (DADDR_in == 7'd12)
lower_drp(clk2_pm, clk2_en, clk2_ht, clk2_lt, DI_in);
else if (DADDR_in == 7'd13)
upper_drp(clk2_mx, clk2_e, clk2_nc, clk2_dt, DI_in);
else if (DADDR_in == 7'd14)
lower_drp(clk3_pm, clk3_en, clk3_ht, clk3_lt, DI_in);
else if (DADDR_in == 7'd15)
upper_drp(clk3_mx, clk3_e, clk3_nc, clk3_dt, DI_in);
else if (DADDR_in == 7'd16)
lower_drp(clk4_pm, clk4_en, clk4_ht, clk4_lt, DI_in);
else if (DADDR_in == 7'd17)
upper_drp(clk4_mx, clk4_e, clk4_nc, clk4_dt, DI_in);
else if (DADDR_in == 7'd18)
lower_drp(clk6_pm, clk6_en, clk6_ht, clk6_lt, DI_in);
else if (DADDR_in == 7'd19)
upper_mix_drp(clkfbout_pm_f, clkfbout_wf_f, clk6_mx, clk6_e, clk6_nc, clk6_dt, DI_in);
else if (DADDR_in == 7'd20)
lower_drp(clkfbout_pm_r, clkfbout_en, clkfbout_ht, clkfbout_lt, DI_in);
else if (DADDR_in == 7'd21)
upper_frac_drp(clkfbout_frac, clkfbout_frac_en, clkfbout_wf_r, clkfbout_mx, clkfbout_e, clkfbout_nc, clkfbout_dt, DI_in);
else if (DADDR_in == 7'd22) begin
divclk_e = DI_in[13];
divclk_nc = DI_in[12];
divclk_ht = DI_in[11:6];
divclk_lt = DI_in[5:0];
end
end
else begin
$display("Error: [Unisim %s-18] RST is low at time %t. RST need to be high when changing paramters through DRP. Instance %m", MODULE_NAME, $time);
end
end //DWE
end //DEN
if ( drp_lock == 1) begin
if (drp_lock_lat_cnt < drp_lock_lat) begin
drp_lock_lat_cnt <= drp_lock_lat_cnt + 1;
end
else begin
drp_lock <= 0;
DRDY_out <= 1;
drp_lock_lat_cnt <= 0;
end
end
if (DRDY == 1) DRDY_out <= 0;
end
function addr_is_valid;
input [6:0] daddr_in;
begin
addr_is_valid = 1'b1;
for (i=0; i<=6; i=i+1)
if (daddr_in[i] != 0 && daddr_in[i] != 1) addr_is_valid = 1'b0;
if ((addr_is_valid) &&
((daddr_in >= 7'd06 && daddr_in <= 7'd22) ||
(daddr_in >= 7'd24 && daddr_in <= 7'd26) ||
(daddr_in == 7'd40) ||
(daddr_in == 7'd78) ||
(daddr_in == 7'd79) ||
(daddr_in == 7'd116))) addr_is_valid = 1'b1;
else addr_is_valid = 1'b0;
end
endfunction
// end process drp;
//
// determine clock period
//
always @(posedge clkpll_r or posedge rst_int or posedge rst_clkinsel_flag)
if (rst_int || rst_clkinsel_flag)
begin
clkin_period[0] <= 1000 * period_clkin;
clkin_period[1] <= 1000 * period_clkin;
clkin_period[2] <= 1000 * period_clkin;
clkin_period[3] <= 1000 * period_clkin;
clkin_period[4] <= 1000 * period_clkin;
clkin_jit <= 0;
clkin_lock_cnt <= 0;
pll_locked_tm <= 0;
lock_period <= 0;
pll_locked_tmp1 <= 0;
clkout_en0_tmp <= 0;
unlock_recover <= 0;
clkin_edge <= 0;
end else begin
clkin_edge <= $time;
if (clkin_edge != 0 && clkinstopped_out1 == 0 && rst_clkinsel_flag == 0) begin
clkin_period[4] <= clkin_period[3];
clkin_period[3] <= clkin_period[2];
clkin_period[2] <= clkin_period[1];
clkin_period[1] <= clkin_period[0];
clkin_period[0] <= $time - clkin_edge;
end
if (pll_unlock == 0 && clkin_edge != 0 && clkinstopped_out1 == 0)
clkin_jit <= $time - clkin_edge - clkin_period[0];
else
clkin_jit <= 0;
if ( ~glblGSR && (clkin_lock_cnt < lock_cnt_max) && fb_delay_found && (pll_unlock1 == 0 || unlock_recover == 1))
clkin_lock_cnt <= clkin_lock_cnt + 1;
else if (pll_unlock1 == 1 && pll_locked_tmp1 ==1 ) begin
clkin_lock_cnt <= lock_cnt_max - 6;
unlock_recover <= 1;
pll_locked_tm <= 0;
pll_locked_tmp1 <= 0;
end
if (( clkin_lock_cnt >= pll_lock_time && pll_unlock == 0) ||
(unlock_recover == 1 && clkin_lock_cnt > lock_cnt_max - 2))
pll_locked_tm <= #1 1;
if ( clkin_lock_cnt == lock_period_time )
lock_period <= 1;
if (clkin_lock_cnt >= clkout_en_time && pll_locked_tm == 1) begin
clkout_en0_tmp <= 1;
end
if (clkin_lock_cnt >= locked_en_time && clkout_en == 1)
pll_locked_tmp1 <= 1;
if (unlock_recover ==1 && clkin_lock_cnt >= lock_cnt_max)
unlock_recover <= 0;
end
always @(posedge pll_locked_tmp1)
if (CLKINSEL_in === 0) begin
pchk_tmp1 = CLKIN2_PERIOD_REG * 1100;
pchk_tmp2 = CLKIN2_PERIOD_REG * 900;
if (period_avg > pchk_tmp1 || period_avg < pchk_tmp2) begin
$display("Warning: [Unisim %s-19] Input CLKIN2 period and attribute CLKIN2_PERIOD are not same. Instance %m ", MODULE_NAME);
end
end
else begin
pchk_tmp1 = CLKIN1_PERIOD_REG * 1100;
pchk_tmp2 = CLKIN1_PERIOD_REG * 900;
if (period_avg > pchk_tmp1 || period_avg < pchk_tmp2) begin
$display("Warning: [Unisim %s-20] Input CLKIN1 period and attribute CLKIN1_PERIOD are not same. Instance %m ", MODULE_NAME);
end
end
always @(*)
if (rst_int == 0) begin
if (clkfbout_frac_en == 1'b0) begin
clkout_en_val = m_product;
clkout_en_time = md_product + pll_lock_time;
locked_en_time = md_product + clkout_en_time + 2;
lock_cnt_max = locked_en_time + 16;
end
else begin
clkout_en_val = mf_product - 1;
clkout_en_time = mf_product + 4 + pll_lock_time;
locked_en_time = md_product + clkout_en_time + 2;
lock_cnt_max = locked_en_time + 16;
end
end
always @(clkout_en0_tmp)
clkout_en0_tmp1 <= #1 clkout_en0_tmp;
always @(clkout_en0_tmp1 or clkout_en_t or clkout_en0_tmp )
if (clkout_en0_tmp==0 )
clkout_en0 = 0;
else begin
if (clkfbout_frac_en == 1'b1) begin
if (clkout_en_t > clkout_en_val && clkout_en0_tmp1 == 1)
clkout_en0 <= #period_vco6 clkout_en0_tmp1;
end
else begin
if (clkout_en_t == clkout_en_val && clkout_en0_tmp1 == 1)
clkout_en0 <= #period_vco6 clkout_en0_tmp1;
end
end
always @(clkout_en0 )
clkout_en1 <= #(clkvco_delay) clkout_en0;
always @(clkout_en1 or rst_in_o )
if (rst_in_o)
clkout_en = 0;
else
clkout_en = clkout_en1;
always @(pll_locked_tmp1 )
if (pll_locked_tmp1==0)
pll_locked_tmp2 = pll_locked_tmp1;
else begin
pll_locked_tmp2 <= #pll_locked_delay pll_locked_tmp1;
end
always @(rst_int or glblGSR)
if (rst_int || glblGSR) begin
assign pll_locked_tmp2 = 0;
end
else begin
deassign pll_locked_tmp2;
end
always @(rst_int)
if (rst_int) begin
assign clkout_en0 = 0;
assign clkout_en1 = 0;
end
else begin
deassign clkout_en0;
deassign clkout_en1;
end
always @(rst_int or pll_locked_tm or pll_locked_tmp2 or pll_unlock or unlock_recover) begin
if ((rst_int == 1) && (LOCKED !== 1'b0))
LOCKED_out <= #1000 0;
else if ((pll_locked_tm && pll_locked_tmp2 && ~pll_unlock && ~unlock_recover) === 1'b1)
LOCKED_out <= 1'b1;
else
LOCKED_out <= 1'b0;
end
always @(clkin_period[0] or clkin_period[1] or clkin_period[2] or
clkin_period[3] or clkin_period[4]) begin
if (clkin_period[0] > clkin_period[1])
clkin_period_tmp_t = clkin_period[0] - clkin_period[1];
else
clkin_period_tmp_t = clkin_period[1] - clkin_period[0];
if ( ((clkin_period[0] > 0) && (clkin_period[0] != period_avg)) && (clkin_period[0] < 1.5 * period_avg || clkin_period_tmp_t <= 300) )
period_avg = (clkin_period[0] + clkin_period[1] + clkin_period[2]
+ clkin_period[3] + clkin_period[4])/5;
end
always @(clkinstopped_out1 or clkin_hold_f or rst_int)
if (rst_int)
clkinstopped_hold = 0;
else begin
if (clkinstopped_out1)
clkinstopped_hold <= 1;
else begin
if (clkin_hold_f)
clkinstopped_hold = 0;
end
end
always @(posedge clkinstopped_out1) begin
period_avg_stpi <= period_avg;
pd_stp_p <= #1 1;
@(negedge clkvco)
pd_stp_p <= #1 0;
end
always @(negedge clkvco or posedge rst_int or posedge pd_stp_p)
if (rst_int) begin
period_avg_stp <= 1000;
vco_stp_f <= 0;
end
else if (pd_stp_p)
period_avg_stp <= period_avg_stpi;
else begin
if (clkinstopped_out_dly2 == 1 && clkin_hold_f == 0) begin
if (period_vco > 1739)
vco_stp_f <= 1;
else begin
period_avg_stp <= period_avg_stp + 1;
end
end
end
always @(period_avg or divclk_div or clkfbout_f_div or clkinstopped_hold
or period_avg_stp or posedge rst_clkinstopped_rc)
if (period_avg > 0 ) begin
md_product = divclk_div * clkfbout_f_div;
m_product = clkfbout_f_div;
m_product2 = clkfbout_f_div / 2;
clkvco_div_fint = $rtoi(clkfbout_f_div/divclk_div);
clkvco_div_frac = (clkfbout_f_div/divclk_div) - clkvco_div_fint;
if (clkvco_div_frac > 0.000)
clkvco_frac_en = 1;
else
clkvco_frac_en = 0;
period_fb = period_avg * divclk_div;
period_vco_tmp = period_fb / clkfbout_f_div;
period_vco_rl = 1.0 * period_fb / clkfbout_f_div;
period_vco_rl_half = period_vco_rl / 2.0;
clkvco_pdrm = (period_avg * divclk_div / clkfbout_f_div) - period_vco_tmp;
period_vco_mf = period_avg * 8;
if (clkinstopped_hold == 1) begin
if (clkin_hold_f) begin
period_vco = (20000 * period_vco_tmp) / (20000 - period_vco_tmp);
period_vco_rl = (20000 * period_vco_tmp) / (20000 - period_vco_tmp);
period_vco_rl_half = period_vco_rl / 2.0;
end
else begin
period_vco = period_avg_stp * divclk_div /clkfbout_f_div;
period_vco_rl = period_avg_stp * divclk_div /clkfbout_f_div;
period_vco_rl_half = period_vco_rl / 2.0;
end
end
else
period_vco = period_vco_tmp;
period_vco_rm = period_fb % clkfbout_div;
if (period_vco_rm > 1) begin
if (period_vco_rm > m_product2) begin
period_vco_cmp_cnt = m_product / (m_product - period_vco_rm) - 1;
period_vco_cmp_flag = 2;
end
else begin
period_vco_cmp_cnt = (m_product / period_vco_rm) - 1;
period_vco_cmp_flag = 1;
end
end
else begin
period_vco_cmp_cnt = 0;
period_vco_cmp_flag = 0;
end
period_vco_half = period_vco /2;
period_vco_half_rm = period_vco - period_vco_half;
period_vco_half_rm1 = period_vco_half_rm + 1;
if (period_vco_half_rm < 1)
period_vco_half_rm2 = 0;
else
period_vco_half_rm2 = period_vco_half_rm - 1;
period_vco_half1 = period_vco - period_vco_half + 1;
pll_locked_delay = period_fb * clkfbout_f_div;
clkin_dly_t = period_avg * (divclk_div + 1.25);
clkfbin_dly_t = period_fb * 2.25 ;
period_vco1 = period_vco / 8;
period_vco2 = period_vco / 4;
period_vco3 = period_vco * 3/ 8;
period_vco4 = period_vco / 2;
period_vco5 = period_vco * 5 / 8;
period_vco6 = period_vco *3 / 4;
period_vco7 = period_vco * 7 / 8;
end
always @ (negedge RST_in) begin
if (drp_updt) begin
clkout_name = "CLKFBOUT";
mc_to_attr(clkout_name, clkfbout_pm_f, clkfbout_wf_f, clkfbout_frac, clkfbout_frac_en, clkfbout_wf_r, clkfbout_mx, clkfbout_e, clkfbout_nc, clkfbout_dt, clkfbout_pm_r, clkfbout_en, clkfbout_ht, clkfbout_lt, clkfbout_f_div, clkfbout_phase, clkfbout_duty);
if (((clkfbout_f_div > M_MAX) || (clkfbout_f_div < M_MIN)) && ~clkfbout_nc)
$display("Error : [Unisim %s-38] CLKFBOUT_MULT_F has been programmed through DRP to %f which is over the range of %f to %f. Instance %m at time %t.", MODULE_NAME, clkfbout_f_div, M_MIN, M_MAX, $time);
clkout_name = "CLKOUT0";
mc_to_attr(clkout_name, clk0_pm_f, clk0_wf_f, clk0_frac, clk0_frac_en, clk0_wf_r, clk0_mx, clk0_e, clk0_nc, clk0_dt, clk0_pm_r, clk0_en, clk0_ht, clk0_lt, clk0_f_div, clk0_phase, clk0_duty);
if (((clk0_f_div > O_MAX) || (clk0_f_div < O_MIN)) && ~clk0_nc)
$display("Error : [Unisim %s-37] CLKOUT0_DIVIDE_F has been programmed through DRP to %f which is over the range of %d to %d. Instance %m at time %t.", MODULE_NAME, clk0_f_div, O_MIN, O_MAX, $time);
clkout_name = "CLKOUT1";
mc_to_attr(clkout_name, 3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk1_mx, clk1_e, clk1_nc, clk1_dt, clk1_pm, clk1_en, clk1_ht, clk1_lt, clk1_div, clk1_phase, clk1_duty);
clkout_name = "CLKOUT2";
mc_to_attr(clkout_name, 3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk2_mx, clk2_e, clk2_nc, clk2_dt, clk2_pm, clk2_en, clk2_ht, clk2_lt, clk2_div, clk2_phase, clk2_duty);
clkout_name = "CLKOUT3";
mc_to_attr(clkout_name, 3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk3_mx, clk3_e, clk3_nc, clk3_dt, clk3_pm, clk3_en, clk3_ht, clk3_lt, clk3_div, clk3_phase, clk3_duty);
clkout_name = "CLKOUT4";
mc_to_attr(clkout_name, 3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk4_mx, clk4_e, clk4_nc, clk4_dt, clk4_pm, clk4_en, clk4_ht, clk4_lt, clk4_div, clk4_phase, clk4_duty);
clkout_name = "CLKOUT5";
mc_to_attr(clkout_name, 3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk5_mx, clk5_e, clk5_nc, clk5_dt, clk5_pm, clk5_en, clk5_ht, clk5_lt, clk5_div, clk5_phase, clk5_duty);
clkout_name = "CLKOUT6";
mc_to_attr(clkout_name, 3'b0, 1'b0, 3'b0, 1'b0, 1'b0, clk6_mx, clk6_e, clk6_nc, clk6_dt, clk6_pm, clk6_en, clk6_ht, clk6_lt, clk6_div, clk6_phase, clk6_duty);
clkout_name = "DIVCLK";
mc_to_attr(clkout_name, 3'b0, 1'b0, 3'b0, 1'b0, 1'b0, 2'b0, divclk_e, divclk_nc, 6'b0, 3'b0, divclk_en, divclk_ht, divclk_lt, divclk_div, divclk_phase, divclk_duty);
if (((divclk_div > D_MAX) || (divclk_div < D_MIN)) && ~divclk_nc)
$display("Error : [Unisim %s-34] DIVCLK_DIVIDE has been programmed through DRP to %f which is over the range of %d to %d at time %t. Instance %m", MODULE_NAME, divclk_div, D_MIN, D_MAX, $time);
ht_calc(clkfbout_frac, clkfbout_frac_en, clkfbout_e, clkfbout_ht, clkfbout_lt, clkfbout_f_div, clkfbout_rsel, clkfbout_fsel, clkfbout_fht, clkfbout_flt, clkfbout_cnt_max, clkfbout_cnt_ht, clkfbout_div);
ht_calc(clk0_frac, clk0_frac_en, clk0_e, clk0_ht, clk0_lt, clk0_f_div, clk0_rsel, clk0_fsel, clk0_fht, clk0_flt, clk0_cnt_max, clk0_cnt_ht, clk0_div);
ht_calc(3'b0, 1'b0, clk1_e, clk1_ht, clk1_lt, clk1_div, d_rsel, d_fsel, d_fht, d_flt, clk1_cnt_max, clk1_cnt_ht, d_div);
ht_calc(3'b0, 1'b0, clk2_e, clk2_ht, clk2_lt, clk2_div, d_rsel, d_fsel, d_fht, d_flt, clk2_cnt_max, clk2_cnt_ht, d_div);
ht_calc(3'b0, 1'b0, clk3_e, clk3_ht, clk3_lt, clk3_div, d_rsel, d_fsel, d_fht, d_flt, clk3_cnt_max, clk3_cnt_ht, d_div);
ht_calc(3'b0, 1'b0, clk4_e, clk4_ht, clk4_lt, clk4_div, d_rsel, d_fsel, d_fht, d_flt, clk4_cnt_max, clk4_cnt_ht, d_div);
ht_calc(3'b0, 1'b0, clk5_e, clk5_ht, clk5_lt, clk5_div, d_rsel, d_fsel, d_fht, d_flt, clk5_cnt_max, clk5_cnt_ht, d_div);
ht_calc(3'b0, 1'b0, clk6_e, clk6_ht, clk6_lt, clk6_div, d_rsel, d_fsel, d_fht, d_flt, clk6_cnt_max, clk6_cnt_ht, d_div);
ht_calc(3'b0, 1'b0, divclk_e, divclk_ht, divclk_lt, divclk_div, d_rsel, d_fsel, d_fht, d_flt, divclk_cnt_max, divclk_cnt_ht, d_div);
end
end
always @(clkfbout_f_div) begin
mf_product = clkfbout_f_div * 8;
end
always @(*) begin
if (clkfbout_frac_en) begin
clkfbout_frac_ht_rl = period_vco_rl * clkfbout_fht + (period_vco_rl * clkfbout_rsel) / 8.0;
clkfbout_frac_lt_rl = period_vco_rl * clkfbout_flt + (period_vco_rl * clkfbout_fsel) / 8.0;
clkfbout_frac_ht = $rtoi(clkfbout_frac_ht_rl);
clkfbout_frac_lt = $rtoi(clkfbout_frac_lt_rl);
end
end
always @(*) begin
if (clk0_frac_en) begin
clk0_frac_ht_rl = period_vco_rl * clk0_fht + (period_vco_rl * clk0_rsel) / 8.0;
clk0_frac_lt_rl = period_vco_rl * clk0_flt + (period_vco_rl * clk0_fsel) / 8.0;
clk0_frac_ht = $rtoi(clk0_frac_ht_rl);
clk0_frac_lt = $rtoi(clk0_frac_lt_rl);
end
end
reg ps_wr_to_max = 1'b0;
always @(period_vco or ps_in_ps)
if (fps_en == 1) begin
if (ps_in_ps < 0)
period_ps = period_vco + ps_in_ps * period_vco / 56.0;
else if ((ps_in_ps == 0) && PSINCDEC_in == 0)
period_ps = 0;
else
period_ps = ps_in_ps * period_vco / 56.0;
end
always @( clkpll_r )
clkpll_tmp1 <= #(period_avg) clkpll_r;
always @(clkpll_tmp1)
clkpll <= #(period_avg) clkpll_tmp1;
always @(posedge clkinstopped_out1 or posedge rst_int)
if ( rst_int)
clkinstopped_vco_f <= 0;
else begin
clkinstopped_vco_f <= 1;
@(negedge clkinstopped_out1 or posedge rst_int )
if (rst_int)
clkinstopped_vco_f <= 0;
else begin
@(posedge clkpll);
@(posedge clkpll)
clkinstopped_vco_f <= 0;
end
end
always @(posedge clkinstopped_out1 or posedge rst_int)
if (rst_int)
CLKINSTOPPED_out <= 0;
else begin
CLKINSTOPPED_out <= 1;
if (clkin_hold_f == 1) begin
@(posedge LOCKED or posedge rst_int)
CLKINSTOPPED_out <= 0;
end
else begin
if (CLKINSEL_in == 1)
$display("Warning: [Unisim %s-21] Input CLKIN1 is stopped at time %t. Reset is required when input clock returns. Instance %m ", MODULE_NAME, $time);
else
$display("Warning: [Unisim %s-22] Input CLKIN2 is stopped at time %t. Reset is required when input clock returns. Instance %m ", MODULE_NAME, $time);
end
end
always @(posedge clkfbstopped_out1 or posedge rst_int)
if (rst_int)
CLKFBSTOPPED_out <= 1'b0;
else begin
CLKFBSTOPPED_out <= 1'b1;
@(posedge LOCKED)
CLKFBSTOPPED_out <= 1'b0;
end
always @(clkout_en_t)
if (clkout_en_t >= clkout_en_val -3 && clkout_en_t < clkout_en_val)
rst_clkinstopped_tm = 1;
else
rst_clkinstopped_tm = 0;
always @(negedge clkinstopped_out1 or posedge rst_int)
if (rst_int)
rst_clkinstopped <= 0;
else
if (rst_clkinstopped_lk == 0 && clkin_hold_f == 1) begin
@(posedge rst_clkinstopped_tm)
rst_clkinstopped <= #period_vco4 1;
@(negedge rst_clkinstopped_tm ) begin
rst_clkinstopped <= #period_vco5 0;
rst_clkinstopped_rc <= #period_vco6 1;
rst_clkinstopped_rc <= #period_vco7 0;
end
end
always @(posedge clkinstopped_out1 or posedge rst_int)
if (rst_int)
clkinstopped_out_dly <= 0;
else begin
clkinstopped_out_dly <= 1;
if (clkin_hold_f == 1) begin
@(negedge rst_clkinstopped_rc or posedge rst_int)
clkinstopped_out_dly <= 0;
end
end
always @(clkinstopped_out1 or posedge rst_int)
if (rst_int)
clkinstopped_out_dly2 <= 0;
else
clkinstopped_out_dly2 <= clkinstopped_out1;
always @(negedge rst_clkinstopped or posedge rst_int)
if (rst_int)
rst_clkinstopped_lk <= 0;
else begin
rst_clkinstopped_lk <= 1;
@(posedge LOCKED)
rst_clkinstopped_lk <= 0;
end
always @(clkinstopped_vco_f or CLKINSTOPPED or clkvco_lk or clkvco_free or rst_int)
if (rst_int)
clkvco_lk = 0;
else begin
if (CLKINSTOPPED == 1 && clkin_stop_f == 0)
clkvco_lk <= #(period_vco_half) !clkvco_lk;
else if (clkinstopped_vco_f == 1 && period_vco_half > 0)
clkvco_lk <= #(period_vco_half) !clkvco_lk;
else
clkvco_lk = clkvco_free;
end
// free run vco comp
always @(posedge clkpll)
if (pll_locked_tm == 1 ) begin
clkvco_free = 1'b1;
halfperiod_sum = 0.0;
halfperiod = 0;
if (clkfbout_frac_en == 1'b1 || clkvco_frac_en == 1) begin
if (mf_product > 1) begin
for (ik10=1; ik10 < mf_product; ik10=ik10+1) begin
clkout_en_t <= ik10;
halfperiod_sum = halfperiod_sum + period_vco_rl_half - halfperiod;
halfperiod = $rtoi(halfperiod_sum);
#halfperiod clkvco_free = 1'b0;
halfperiod_sum = halfperiod_sum + period_vco_rl_half - halfperiod;
halfperiod = $rtoi(halfperiod_sum);
#halfperiod clkvco_free = 1'b1;
end
clkout_en_t <= ik10;
end else begin
clkout_en_t <= 1;
end
end else begin
if (m_product > 1) begin
for (ik11=1; ik11 < m_product; ik11=ik11+1) begin
clkout_en_t <= ik11;
halfperiod_sum = halfperiod_sum + period_vco_rl_half - halfperiod;
halfperiod = $rtoi(halfperiod_sum);
#halfperiod clkvco_free = 1'b0;
halfperiod_sum = halfperiod_sum + period_vco_rl_half - halfperiod;
halfperiod = $rtoi(halfperiod_sum);
#halfperiod clkvco_free = 1'b1;
end
clkout_en_t <= ik11;
end else begin
clkout_en_t <= 1;
end
end
halfperiod_sum = halfperiod_sum + period_vco_rl_half - halfperiod;
halfperiod = $rtoi(halfperiod_sum);
#halfperiod clkvco_free = 1'b0;
if (clkfbout_f_div < divclk_div) begin
#(period_vco_rl_half - period_avg/2.0);
end
end
always @(fb_delay or period_vco or period_vco_mf or clkfbout_dt or clkfbout_pm_rl
or lock_period or ps_in_ps )
if (lock_period == 1) begin
if (clkfbout_frac_en == 1'b1) begin
val_tmp = period_avg * DIVCLK_DIVIDE_REG;
fb_comp_delay = period_vco * (clkfbout_dt + clkfbout_pm_rl);
end
else begin
val_tmp = period_avg * DIVCLK_DIVIDE_REG;
fb_comp_delay = period_vco * (clkfbout_dt + clkfbout_pm_rl);
end
dly_tmp1 = fb_delay + fb_comp_delay;
dly_tmp_int = 1;
if (CLKFBOUT_USE_FINE_PS_BIN == CLKFBOUT_USE_FINE_PS_TRUE) begin
if (ps_in_ps < 0) begin
tmp_ps_val1 = -1 * ps_in_ps;
tmp_ps_val2 = tmp_ps_val1 * period_vco / 56.0;
if (tmp_ps_val2 > dly_tmp1 ) begin
dly_tmp_int = -1;
dly_tmp = tmp_ps_val2 - dly_tmp1;
end
else if (tmp_ps_val2 == dly_tmp1 ) begin
dly_tmp_int = 0;
dly_tmp = 0;
end
else begin
dly_tmp_int = 1;
dly_tmp = dly_tmp1 - tmp_ps_val2;
end
end
else
dly_tmp = dly_tmp1 + ps_in_ps * period_vco / 56.0;
end
else
dly_tmp = dly_tmp1;
if (dly_tmp_int < 0)
clkvco_delay = dly_tmp;
else begin
if (clkfbout_frac_en == 1'b1 && dly_tmp == 0)
clkvco_delay = 0;
else if ( dly_tmp < val_tmp)
clkvco_delay = val_tmp - dly_tmp;
else
clkvco_delay = val_tmp - dly_tmp % val_tmp ;
end
end
always @(clkfbout_pm_r)
case (clkfbout_pm_r)
3'b000 : clkfbout_pm_rl = 0.0;
3'b001 : clkfbout_pm_rl = 0.125;
3'b010 : clkfbout_pm_rl = 0.25;
3'b011 : clkfbout_pm_rl = 0.375;
3'b100 : clkfbout_pm_rl = 0.50;
3'b101 : clkfbout_pm_rl = 0.625;
3'b110 : clkfbout_pm_rl = 0.75;
3'b111 : clkfbout_pm_rl = 0.875;
endcase
always @(clkvco_lk)
clkvco_lk_dly_tmp <= #clkvco_delay clkvco_lk;
always @(clkvco_lk_dly_tmp or clkvco_lk or pll_locked_tm)
if ( pll_locked_tm && vco_stp_f == 0) begin
if (dly_tmp == 0)
clkvco = clkvco_lk;
else
clkvco = clkvco_lk_dly_tmp;
end
else
clkvco = 0;
always @(posedge PSCLK_in or posedge rst_int)
if (rst_int) begin
ps_in_ps <= ps_in_init;
ps_cnt <= 0;
psen_w <= 0;
fps_clk_en <= 0;
ps_lock <= 0;
end else if (fps_en == 1) begin
fps_clk_en <= 1;
if (PSEN_in) begin
if (psen_w == 1)
$display("Error: [Unisim %s-23] PSEN is active more than 1 PSCLK period at time %t. PSEN must be active for only one PSCLK period. Instance %m ", MODULE_NAME, $time);
psen_w <= 1;
if (ps_lock == 1)
$display("Warning: [Unisim %s-24] Please wait for PSDONE signal at time %t before adjusting the Phase Shift. Instance %m ", MODULE_NAME, $time);
else if (PSINCDEC_in == 1) begin
if (ps_cnt < ps_max)
ps_cnt <= ps_cnt + 1;
else
ps_cnt <= 0;
if (ps_in_ps < ps_max)
ps_in_ps <= ps_in_ps + 1;
else
ps_in_ps <= 0;
ps_lock <= 1;
end
else if (PSINCDEC_in == 0) begin
ps_cnt_neg = (-1) * ps_cnt;
ps_in_ps_neg = (-1) * ps_in_ps;
if (ps_cnt_neg < ps_max)
ps_cnt <= ps_cnt - 1;
else
ps_cnt <= 0;
if (ps_in_ps_neg < ps_max)
ps_in_ps <= ps_in_ps - 1;
else
ps_in_ps <= 0;
ps_lock <= 1;
end
end
else
psen_w <= 0;
if ( PSDONE == 1'b1)
ps_lock <= 0;
end
always @(posedge ps_lock)
if (fps_en == 1) begin
@(posedge PSCLK_in)
@(posedge PSCLK_in)
@(posedge PSCLK_in)
@(posedge PSCLK_in)
@(posedge PSCLK_in)
@(posedge PSCLK_in)
@(posedge PSCLK_in)
@(posedge PSCLK_in)
@(posedge PSCLK_in)
@(posedge PSCLK_in)
@(posedge PSCLK_in)
begin
PSDONE_out = 1'b1;
@(posedge PSCLK_in);
PSDONE_out = 1'b0;
end
end
always @(rst_clkinstopped)
if (rst_clkinstopped) begin
assign clkfbout_frac_ht = 50;
assign clkfbout_frac_lt = 50;
assign clkfbout_frac_ht_rl = 50.0;
assign clkfbout_frac_lt_rl = 50.0;
end
else begin
deassign clkfbout_frac_ht;
deassign clkfbout_frac_lt;
deassign clkfbout_frac_ht_rl;
deassign clkfbout_frac_lt_rl;
end
integer clk0_delay, clk1_delay, clk2_delay, clk3_delay, clk4_delay, clk5_delay, clk6_delay, clkfbout_delay;
integer clk0_delay_next, clk1_delay_next, clk2_delay_next, clk3_delay_next, clk4_delay_next, clk5_delay_next, clk6_delay_next, clkfbout_delay_next;
always @(*) clk0_delay_next = clk0_pm_r*period_vco/8 + (clk0_fps_en*period_ps);
always @(*) clk1_delay_next = clk1_pm*period_vco/8 + (clk1_fps_en*period_ps);
always @(*) clk2_delay_next = clk2_pm*period_vco/8 + (clk2_fps_en*period_ps);
always @(*) clk3_delay_next = clk3_pm*period_vco/8 + (clk3_fps_en*period_ps);
always @(*) clk4_delay_next = clk4_pm*period_vco/8 + (clk4_fps_en*period_ps);
always @(*) clk5_delay_next = clk5_pm*period_vco/8 + (clk5_fps_en*period_ps);
always @(*) clk6_delay_next = clk6_pm*period_vco/8 + (clk6_fps_en*period_ps);
always @(*) clkfbout_delay_next = clkfbout_pm_r*period_vco/8 + (clkfbout_fps_en*period_ps);
always @ (posedge clkvco) begin
if (ps_lock) begin
if ((period_ps - period_ps_old) > period_vco/2)
ps_wr_to_max <= 1'b1;
else
ps_wr_to_max <= 1'b0;
end
period_ps_old = period_ps;
clk0_delay <= clk0_delay_next;
clk1_delay <= clk1_delay_next;
clk2_delay <= clk2_delay_next;
clk3_delay <= clk3_delay_next;
clk4_delay <= clk4_delay_next;
clk5_delay <= clk5_delay_next;
clk6_delay <= clk6_delay_next;
clkfbout_delay <= clkfbout_delay_next;
end
always @ (clkvco) begin
if (clkout_en && clk0_en)
if (clk0_delay == 0) clk0in = clkvco;
else if (clk0_fps_en && ps_wr_to_max && ~clkvco) begin
clk0in <= #(clk0_delay - period_ps) 1'b0;
clk0in <= #((2 * clk0_delay - period_ps)/2) 1'b1;
clk0in <= #(clk0_delay) 1'b0;
end else begin
clk0in <= #clk0_delay clkvco;
end
else clk0in = 1'b0;
end
always @ (clkvco) begin
if (clkout_en && clk1_en)
if (clk1_delay == 0) clk1in = clkvco;
else if (clk1_fps_en && ps_wr_to_max && ~clkvco) begin
clk1in <= #(clk1_delay - period_ps) 1'b0;
clk1in <= #((2 * clk1_delay - period_ps)/2) 1'b1;
clk1in <= #(clk1_delay) 1'b0;
end else begin
clk1in <= #clk1_delay clkvco;
end
else clk1in = 1'b0;
end
always @ (clkvco) begin
if (clkout_en && clk2_en)
if (clk2_delay == 0) clk2in = clkvco;
else if (clk2_fps_en && ps_wr_to_max && ~clkvco) begin
clk2in <= #(clk2_delay - period_ps) 1'b0;
clk2in <= #((2 * clk2_delay - period_ps)/2) 1'b1;
clk2in <= #(clk2_delay) 1'b0;
end else begin
clk2in <= #clk2_delay clkvco;
end
else clk2in = 1'b0;
end
always @ (clkvco) begin
if (clkout_en && clk3_en)
if (clk3_delay == 0) clk3in = clkvco;
else if (clk3_fps_en && ps_wr_to_max && ~clkvco) begin
clk3in <= #(clk3_delay - period_ps) 1'b0;
clk3in <= #((2 * clk3_delay - period_ps)/2) 1'b1;
clk3in <= #(clk3_delay) 1'b0;
end else begin
clk3in <= #clk3_delay clkvco;
end
else clk3in = 1'b0;
end
always @ (clkvco) begin
if (clkout_en && clk4_en)
if (CLKOUT4_CASCADE_BIN == CLKOUT4_CASCADE_TRUE) clk4in = clk6_out;
else if (clk4_delay == 0) clk4in = clkvco;
else if (clk4_fps_en && ps_wr_to_max && ~clkvco) begin
clk4in <= #(clk4_delay - period_ps) 1'b0;
clk4in <= #((2 * clk4_delay - period_ps)/2) 1'b1;
clk4in <= #(clk4_delay) 1'b0;
end else begin
clk4in <= #clk4_delay clkvco;
end
else clk4in = 1'b0;
end
always @ (clkvco) begin
if (clkout_en && clk5_en)
if (clk5_delay == 0) clk5in = clkvco;
else if (clk5_fps_en && ps_wr_to_max && ~clkvco) begin
clk5in <= #(clk5_delay - period_ps) 1'b0;
clk5in <= #((2 * clk5_delay - period_ps)/2) 1'b1;
clk5in <= #(clk5_delay) 1'b0;
end else begin
clk5in <= #clk5_delay clkvco;
end
else clk5in = 1'b0;
end
always @ (clkvco) begin
if (clkout_en && clk6_en)
if (clk6_delay == 0) clk6in = clkvco;
else if (clk6_fps_en && ps_wr_to_max && ~clkvco) begin
clk6in <= #(clk6_delay - period_ps) 1'b0;
clk6in <= #((2 * clk6_delay - period_ps)/2) 1'b1;
clk6in <= #(clk6_delay) 1'b0;
end else begin
clk6in <= #clk6_delay clkvco;
end
else clk6in = 1'b0;
end
always @ (clkvco) begin
if (clkout_en && clkfbout_en)
if (clkfbout_delay == 0) clkfboutin = clkvco;
else if (clkfbout_fps_en && ps_wr_to_max && ~clkvco) begin
clkfboutin <= #(clkfbout_delay - period_ps) 1'b0;
clkfboutin <= #((2 * clkfbout_delay - period_ps)/2) 1'b1;
clkfboutin <= #(clkfbout_delay) 1'b0;
end else begin
clkfboutin <= #clkfbout_delay clkvco;
end
else clkfboutin = 1'b0;
end
assign clk0ps_en = (clk0_dly_cnt == clk0_dt) & clkout_en;
assign clk1ps_en = (clk1_dly_cnt == clk1_dt) & clkout_en;
assign clk2ps_en = (clk2_dly_cnt == clk2_dt) & clkout_en;
assign clk3ps_en = (clk3_dly_cnt == clk3_dt) & clkout_en;
assign clk4ps_en = (clk4_dly_cnt == clk4_dt) & clkout_en;
assign clk5ps_en = (clk5_dly_cnt == clk5_dt) & clkout_en;
assign clk6ps_en = (clk6_dly_cnt == clk6_dt) & clkout_en;
assign clkfbps_en = (clkfbout_dly_cnt == clkfbout_dt) & clkout_en;
always @(negedge clk0in or posedge rst_in_o)
if (rst_in_o)
clk0_dly_cnt <= 6'b0;
else if (clkout_en == 1 ) begin
if (clk0_dly_cnt < clk0_dt)
clk0_dly_cnt <= clk0_dly_cnt + 1;
end
always @(negedge clk1in or posedge rst_in_o)
if (rst_in_o)
clk1_dly_cnt <= 6'b0;
else
if (clk1_dly_cnt < clk1_dt && clkout_en ==1)
clk1_dly_cnt <= clk1_dly_cnt + 1;
always @(negedge clk2in or posedge rst_in_o)
if (rst_in_o)
clk2_dly_cnt <= 6'b0;
else
if (clk2_dly_cnt < clk2_dt && clkout_en ==1)
clk2_dly_cnt <= clk2_dly_cnt + 1;
always @(negedge clk3in or posedge rst_in_o)
if (rst_in_o)
clk3_dly_cnt <= 6'b0;
else
if (clk3_dly_cnt < clk3_dt && clkout_en ==1)
clk3_dly_cnt <= clk3_dly_cnt + 1;
always @(negedge clk4in or posedge rst_in_o)
if (rst_in_o)
clk4_dly_cnt <= 6'b0;
else
if (clk4_dly_cnt < clk4_dt && clkout_en ==1)
clk4_dly_cnt <= clk4_dly_cnt + 1;
always @(negedge clk5in or posedge rst_in_o)
if (rst_in_o)
clk5_dly_cnt <= 6'b0;
else if (clkout_en == 1 ) begin
if (clk5_dly_cnt < clk5_dt)
clk5_dly_cnt <= clk5_dly_cnt + 1;
end
always @(negedge clk6in or posedge rst_in_o)
if (rst_in_o)
clk6_dly_cnt <= 6'b0;
else if (clkout_en == 1 ) begin
if (clk6_dly_cnt < clk6_dt)
clk6_dly_cnt <= clk6_dly_cnt + 1;
end
always @(negedge clkfboutin or posedge rst_in_o)
if (rst_in_o)
clkfbout_dly_cnt <= 6'b0;
else if (clkout_en == 1 ) begin
if (clkfbout_dly_cnt < clkfbout_dt)
clkfbout_dly_cnt <= clkfbout_dly_cnt + 1;
end
always @(posedge clkfboutin or negedge clkfboutin or posedge rst_in_o)
if (rst_in_o || ~clkfbps_en) begin
clkfbout_cnt <= 8'b0;
clkfbout_out = 0;
end
else if (clkfbout_nc) clkfbout_out = ~clkfbout_out;
else if (~clkfbout_frac_en) begin
if (clkfbout_cnt < clkfbout_cnt_max)
clkfbout_cnt <= clkfbout_cnt + 1;
else
clkfbout_cnt <= 8'b0;
if (clkfbout_cnt < clkfbout_cnt_ht)
clkfbout_out = 1;
else
clkfbout_out = 0;
end
else if (clkfbout_frac_en && clkfboutin) begin
clkfbout_out = 1;
clkfbout_frac_rm_rl = 0.0;
clkfbout_frac_rm = 0;
for (ib=1; ib < 8; ib=ib+1) begin
clkfbout_frac_rm_rl = clkfbout_frac_rm_rl + clkfbout_frac_ht_rl - clkfbout_frac_ht - clkfbout_frac_rm;
clkfbout_frac_rm = $rtoi(clkfbout_frac_rm_rl);
#(clkfbout_frac_ht + clkfbout_frac_rm) clkfbout_out = 0;
clkfbout_frac_rm_rl = clkfbout_frac_rm_rl + clkfbout_frac_lt_rl - clkfbout_frac_lt - clkfbout_frac_rm;
clkfbout_frac_rm = $rtoi(clkfbout_frac_rm_rl);
#(clkfbout_frac_lt + clkfbout_frac_rm) clkfbout_out = 1;
end
#(clkfbout_frac_ht) clkfbout_out = 0;
#(clkfbout_frac_lt - period_vco1);
end
always @(posedge clk0in or negedge clk0in or posedge rst_in_o)
if (rst_in_o || ~clk0ps_en) begin
clk0_cnt <= 8'b0;
clk0_out = 0;
end
else if (clk0_nc) clk0_out = ~clk0_out;
else if (~clk0_frac_en) begin
if (clk0_cnt < clk0_cnt_max)
clk0_cnt <= clk0_cnt + 1;
else
clk0_cnt <= 8'b0;
if (clk0_cnt < clk0_cnt_ht)
clk0_out = 1;
else
clk0_out = 0;
end
else if (clk0_frac_en && clk0in) begin
clk0_out = 1;
clk0_frac_rm_rl = 0.0;
clk0_frac_rm = 0;
for (ik0=1; ik0 < 8; ik0=ik0+1) begin
clk0_frac_rm_rl = clk0_frac_rm_rl + clk0_frac_ht_rl - clk0_frac_ht - clk0_frac_rm;
clk0_frac_rm = $rtoi(clk0_frac_rm_rl);
#(clk0_frac_ht + clk0_frac_rm) clk0_out = 0;
clk0_frac_rm_rl = clk0_frac_rm_rl + clk0_frac_lt_rl - clk0_frac_lt - clk0_frac_rm;
clk0_frac_rm = $rtoi(clk0_frac_rm_rl);
#(clk0_frac_lt + clk0_frac_rm) clk0_out = 1;
end
#(clk0_frac_ht) clk0_out = 0;
#(clk0_frac_lt - period_vco1);
end
always @(posedge clk1in or negedge clk1in or posedge rst_in_o)
if (rst_in_o || ~clk1ps_en) begin
clk1_cnt <= 8'b0;
clk1_out = 0;
end
else if (clk1_nc) clk1_out = ~clk1_out;
else begin
if (clk1_cnt < clk1_cnt_max)
clk1_cnt <= clk1_cnt + 1;
else
clk1_cnt <= 8'b0;
if (clk1_cnt < clk1_cnt_ht)
clk1_out = 1;
else
clk1_out = 0;
end
always @(posedge clk2in or negedge clk2in or posedge rst_in_o)
if (rst_in_o || ~clk2ps_en) begin
clk2_cnt <= 8'b0;
clk2_out = 0;
end
else if (clk2_nc) clk2_out = ~clk2_out;
else begin
if (clk2_cnt < clk2_cnt_max)
clk2_cnt <= clk2_cnt + 1;
else
clk2_cnt <= 8'b0;
if (clk2_cnt < clk2_cnt_ht)
clk2_out = 1;
else
clk2_out = 0;
end
always @(posedge clk3in or negedge clk3in or posedge rst_in_o)
if (rst_in_o || ~clk3ps_en) begin
clk3_cnt <= 8'b0;
clk3_out = 0;
end
else if (clk3_nc) clk3_out = ~clk3_out;
else begin
if (clk3_cnt < clk3_cnt_max)
clk3_cnt <= clk3_cnt + 1;
else
clk3_cnt <= 8'b0;
if (clk3_cnt < clk3_cnt_ht)
clk3_out = 1;
else
clk3_out = 0;
end
always @(posedge clk4in or negedge clk4in or posedge rst_in_o)
if (rst_in_o || ~clk4ps_en) begin
clk4_cnt <= 8'b0;
clk4_out = 0;
end
else if (clk4_nc) clk4_out = ~clk4_out;
else begin
if (clk4_cnt < clk4_cnt_max)
clk4_cnt <= clk4_cnt + 1;
else
clk4_cnt <= 8'b0;
if (clk4_cnt < clk4_cnt_ht)
clk4_out = 1;
else
clk4_out = 0;
end
always @(posedge clk5in or negedge clk5in or posedge rst_in_o)
if (rst_in_o || ~clk5ps_en) begin
clk5_cnt <= 8'b0;
clk5_out = 0;
end
else if (clk5_nc) clk5_out = ~clk5_out;
else begin
if (clk5_cnt < clk5_cnt_max)
clk5_cnt <= clk5_cnt + 1;
else
clk5_cnt <= 8'b0;
if (clk5_cnt < clk5_cnt_ht)
clk5_out = 1;
else
clk5_out = 0;
end
always @(posedge clk6in or negedge clk6in or posedge rst_in_o)
if (rst_in_o || ~clk6ps_en) begin
clk6_cnt <= 8'b0;
clk6_out = 0;
end
else if (clk6_nc) clk6_out = ~clk6_out;
else begin
if (clk6_cnt < clk6_cnt_max)
clk6_cnt <= clk6_cnt + 1;
else
clk6_cnt <= 8'b0;
if (clk6_cnt < clk6_cnt_ht)
clk6_out = 1;
else
clk6_out = 0;
end
always @(clk0_out or clkfbout_tst or fb_delay_found)
if (fb_delay_found == 1'b1) begin
CLKOUT0_out = clk0_out;
CLKOUT0B_out = ~clk0_out;
end else begin
CLKOUT0_out = clkfbout_tst;
CLKOUT0B_out = ~clkfbout_tst;
end
always @(clk1_out or clkfbout_tst or fb_delay_found)
if (fb_delay_found == 1'b1) begin
CLKOUT1_out = clk1_out;
CLKOUT1B_out = ~clk1_out;
end else begin
CLKOUT1_out = clkfbout_tst;
CLKOUT1B_out = ~clkfbout_tst;
end
always @(clk2_out or clkfbout_tst or fb_delay_found)
if (fb_delay_found == 1'b1) begin
CLKOUT2_out = clk2_out;
CLKOUT2B_out = ~clk2_out;
end else begin
CLKOUT2_out = clkfbout_tst;
CLKOUT2B_out = ~clkfbout_tst;
end
always @(clk3_out or clkfbout_tst or fb_delay_found)
if (fb_delay_found == 1'b1) begin
CLKOUT3_out = clk3_out;
CLKOUT3B_out = ~clk3_out;
end else begin
CLKOUT3_out = clkfbout_tst;
CLKOUT3B_out = ~clkfbout_tst;
end
always @(clk4_out or clkfbout_tst or fb_delay_found)
if (fb_delay_found == 1'b1) begin
CLKOUT4_out = clk4_out;
end else begin
CLKOUT4_out = clkfbout_tst;
end
always @(clk5_out or clkfbout_tst or fb_delay_found)
if (fb_delay_found == 1'b1) begin
CLKOUT5_out = clk5_out;
end else begin
CLKOUT5_out = clkfbout_tst;
end
always @(clk6_out or clkfbout_tst or fb_delay_found)
if (fb_delay_found == 1'b1) begin
CLKOUT6_out = clk6_out;
end else begin
CLKOUT6_out = clkfbout_tst;
end
always @(clkfbout_out or clkfbout_tst or fb_delay_found)
if (fb_delay_found == 1'b1)
begin
CLKFBOUT_out = clkfbout_out;
CLKFBOUTB_out = ~clkfbout_out;
end
else
begin
CLKFBOUT_out = clkfbout_tst;
CLKFBOUTB_out = ~clkfbout_tst;
end
//
// determine feedback delay
//
always @(posedge clkpll_r )
if (fb_delay_found) clkfbout_tst = 1'b0;
else clkfbout_tst = ~clkfbout_tst;
always @( posedge clkfbout_tst )
delay_edge = $time;
always @( posedge rst_int )
begin
fb_delay <= 0;
fb_delay_found_tmp <= 0;
end
always @(posedge CLKFBIN_in )
if (fb_delay_found_tmp == 0 ) begin
if ( delay_edge != 0) begin
fb_delay <= ($time - delay_edge);
fb_delay_found_tmp <= 1;
end else begin
fb_delay <= 0;
fb_delay_found_tmp <= 0;
end
end
always @(negedge clkfbout_tst or negedge fb_delay_found_tmp)
fb_delay_found <= fb_delay_found_tmp;
always @(fb_delay or fb_delay_found)
if (rst_int==0 && fb_delay_found==1'b1 && (fb_delay/1000.0 > fb_delay_max)) begin
$display("Warning: [Unisim %s-25] The feedback delay at time %t is %f ns. It is over the maximum value %f ns. Instance %m ", MODULE_NAME, $time, fb_delay / 1000.0, fb_delay_max);
end
//
// generate unlock signal
//
always #(2*period_avg/3+250) clkin_osc = ~rst_int && ~clkin_osc;
always #(2*period_avg*divclk_div/3+250) clkfbin_osc = ~rst_int && ~clkfbin_osc;
always @(posedge clkpll_r or negedge clkpll_r) begin
clkin_p <= 1;
clkin_p <= #100 0;
end
always @(posedge CLKFBIN_in or negedge CLKFBIN_in) begin
clkfbin_p <= 1;
clkfbin_p <= #100 0;
end
always @(posedge clkin_osc or posedge rst_int or posedge clkin_p)
if (rst_int == 1) begin
clkinstopped_out1 <= 0;
clkin_lost_cnt <= 0;
end
else if (clkin_p == 1) begin
if (clkinstopped_out1 == 1) begin
@(posedge clkpll_r) begin
clkinstopped_out1 <= 0;
clkin_lost_cnt <= 0;
end
end
else begin
clkinstopped_out1 <= 0;
clkin_lost_cnt <= 0;
end
end
else if (lock_period) begin
if (clkin_lost_cnt < clkin_lost_val) begin
clkin_lost_cnt <= clkin_lost_cnt + 1;
clkinstopped_out1 <= 0;
end
else
clkinstopped_out1 <= 1;
end
always @(posedge clkfbin_osc or posedge rst_int or posedge clkfbin_p or posedge pll_unlock)
if (rst_int == 1 || clkfbin_p == 1 || pll_unlock == 1) begin
clkfbstopped_out1 <= 0;
clkfbin_lost_cnt <= 0;
end
else if (clkout_en) begin
if (clkfbin_lost_cnt < clkfbin_lost_val) begin
clkfbin_lost_cnt <= clkfbin_lost_cnt + 1;
clkfbstopped_out1 <= 0;
end
else
clkfbstopped_out1 <= 1;
end
always @(clkin_jit or rst_int )
if (rst_int)
clkpll_jitter_unlock = 0;
else
if (pll_locked_tmp2 && clkfbstopped_out1 == 0 && clkinstopped_out1 == 0) begin
if ((clkin_jit > REF_CLK_JITTER_MAX_tmp && clkin_jit != period_avg) ||
(clkin_jit < -REF_CLK_JITTER_MAX_tmp && clkin_jit != -period_avg ))
clkpll_jitter_unlock = 1;
else
clkpll_jitter_unlock = 0;
end
else
clkpll_jitter_unlock = 0;
assign pll_unlock1 = (clkinstopped_out_dly ==1 || clkfbstopped_out1==1 || clkpll_jitter_unlock == 1) ? 1 : 0;
assign pll_unlock = (clkinstopped_out_dly ==1 || clkfbstopped_out1==1 || clkpll_jitter_unlock == 1 || unlock_recover == 1) ? 1 : 0;
// tasks
task mc_to_attr;
input [160:1] clkout_name;
input [2:0] pm_f;
input wf_f;
input [2:0] frac;
input frac_en;
input wf_r;
input [1:0] mx;
input e;
input nc;
input [5:0] dt;
input [2:0] pm_r;
input en;
input [5:0] ht;
input [5:0] lt;
output real div;
output real phase;
output real duty;
integer odd_frac;
reg odd;
real frac_r;
integer div_2;
integer pm_f_c;
real duty_step;
real phase_step;
begin
if (nc == 1'b1) begin
div = 1.0;
duty = 0.5;
end
else if (frac_en == 1'b1) begin
duty =0.50;
if (dt == 6'b0 && pm_r == 3'b0) pm_f_c = pm_f;
else if (pm_f >= pm_r) pm_f_c = pm_f - pm_r;
else pm_f_c = 8 + pm_f - pm_r;
if (pm_f_c < 4) begin
odd = 1'b0;
odd_frac = frac;
end
else begin
odd = 1'b1;
odd_frac = frac + 8;
end
frac_r = frac * 0.125;
if (odd_frac > 9) div_2 = lt;
else div_2 = lt + 1;
div = 2.0 * div_2 + 1.0 * odd + frac_r;
end
else begin
if (ht == 6'b0 && lt == 6'b0) div = 128.0;
else if (ht == 6'b0) div = 64.0 + lt * 1.0;
else if (lt == 6'b0) div = ht * 1.0 + 64.0;
else div = ht * 1.0 + lt * 1.0;
duty_step = 0.5 / div;
duty = (2.0 * ht + e) * duty_step;
end
phase_step = 360.0 / (div * 8.0);
phase = phase_step * (dt*8.0 + pm_r*1.0);
end
endtask
task upper_mix_drp;
output reg [2:0] pm_f;
output reg wf_f;
output reg [1:0] mx;
output reg e;
output reg nc;
output reg [5:0] dt;
input [15:0] DI;
begin
pm_f = DI[13:11];
wf_f = DI[10];
mx = DI[9:8];
e = DI[7];
nc = DI[6];
dt = DI[5:0];
end
endtask
task upper_frac_drp;
output reg [2:0] frac;
output reg frac_en;
output reg wf_r;
output reg [1:0] mx;
output reg e;
output reg nc;
output reg [5:0] dt;
input [15:0] DI;
begin
frac = DI[14:12];
frac_en = DI[11];
wf_r = DI[10];
mx = DI[9:8];
e = DI[7];
nc = DI[6];
dt = DI[5:0];
end
endtask
task upper_drp;
output reg [1:0] mx;
output reg e;
output reg nc;
output reg [5:0] dt;
input [15:0] DI;
begin
mx = DI[9:8];
e = DI[7];
nc = DI[6];
dt = DI[5:0];
end
endtask
task lower_drp;
output reg [2:0] pm_r;
output reg en;
output reg [5:0] ht;
output reg [5:0] lt;
input [15:0] DI;
begin
pm_r = DI[15:13];
en = DI[12];
ht = DI[11:6];
lt = DI[5:0];
end
endtask
//ht_calc( frac, frac_en, e, ht, lt, div_f, clk_rsel, clk_fsel, clk_fht, clk_flt, clk_cnt_max, clk_cnt_ht, clk_div)
task ht_calc;
input [2:0] frac;
input frac_en;
input e;
input [5:0] ht;
input [6:0] lt;
input real f_div;
output [3:0] clk_rsel;
output [3:0] clk_fsel;
output [6:0] clk_fht;
output [6:0] clk_flt;
output integer clk_cnt_max;
output integer clk_cnt_ht;
output integer clk_div_fint;
integer clk_div_fint_odd;
begin
clk_div_fint = $rtoi(f_div);
if (frac_en) begin
clk_fht = clk_div_fint / 2;
clk_flt = clk_div_fint / 2;
clk_div_fint_odd = clk_div_fint - clk_fht - clk_flt;
if (clk_div_fint_odd > 0) begin
clk_rsel = (8 + frac) / 2;
clk_fsel = 8 + frac - clk_rsel;
end
else begin
clk_rsel = frac / 2;
clk_fsel = frac - clk_rsel;
end
end
else begin
if (ht == 6'b0) clk_fht = 64; else clk_fht = ht;
if (lt == 7'b0) clk_flt = 64; else clk_flt = lt;
clk_cnt_max = 2 * (clk_fht + clk_flt) - 1;
clk_cnt_ht = 2 * clk_fht + e;
end
end
endtask
task attr_to_mc;
output reg [2:0] pm_f;
output reg wf_f;
output reg [2:0] frac;
output reg frac_en;
output reg wf_r;
output reg [1:0] mx;
output reg e;
output reg nc;
output reg [5:0] dt;
output reg [2:0] pm_r;
output reg en;
output reg [5:0] ht;
output reg [5:0] lt;
input real div;
input real phase;
input real duty;
integer div_int;
real div_frac;
real div_rnd;
reg [37:0] vector;
begin
// determine frac_en
div_int = $rtoi(div);
div_frac = div - $itor(div_int);
if (div_frac > 0.000) frac_en = 1'b1;
else frac_en = 1'b0;
// rnd frac to nearest 0.125 - may become .000
div_rnd = $itor($rtoi((div + 0.0625) * 8.0)) / 8.0;
// determine int and frac part
div_int = $rtoi(div_rnd);
div_frac = div_rnd - $itor(div_int);
if (frac_en == 1'b1)
vector = mmcm_frac_calc(div_int,phase*1000,duty*100000,div_frac*1000);
else
vector = mmcm_calc(div_int,phase*1000,duty*100000);
if (frac_en == 1'b1) begin
pm_f = vector[35:33];
wf_f = vector[32];
frac = vector[30:28];
frac_en = vector[27];
wf_r = vector[26];
end
else begin
pm_f = 3'b0;
wf_f = 1'b0;
frac = 3'b0;
frac_en = 1'b0;
wf_r = 1'b0;
end
mx = vector[25:24];
e = vector[23];
nc = vector[22];
dt = vector[21:16];
pm_r = vector[15:13];
en = 1'b1;
ht = vector[11:6];
lt = vector[5:0];
end
endtask
`define MMCME2_ADV_FRAC_PRECISION 10
`define MMCME2_ADV_FIXED_WIDTH 32
// This function takes a fixed point number and rounds it to the nearest
// fractional precision bit.
function [`MMCME2_ADV_FIXED_WIDTH:1] round_frac
(
// Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
input [`MMCME2_ADV_FIXED_WIDTH:1] decimal,
// This describes the precision of the fraction, for example a value
// of 1 would modify the fractional so that instead of being a .16
// fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
input [`MMCME2_ADV_FIXED_WIDTH:1] precision
);
begin
// If the fractional precision bit is high then round up
if( decimal[(`MMCME2_ADV_FRAC_PRECISION-precision)] == 1'b1) begin
round_frac = decimal + (1'b1 << (`MMCME2_ADV_FRAC_PRECISION-precision));
end else begin
round_frac = decimal;
end
end
endfunction
// This function calculates high_time, low_time, w_edge, and no_count
// of a non-fractional counter based on the divide and duty cycle
//
// NOTE: high_time and low_time are returned as integers between 0 and 63
// inclusive. 64 should equal 6'b000000 (in other words it is okay to
// ignore the overflow)
function [13:0] mmcm_divider
(
input [7:0] divide, // Max divide is 128
input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
);
reg [`MMCME2_ADV_FIXED_WIDTH:1] duty_cycle_fix;
// High/Low time is initially calculated with a wider integer to prevent a
// calculation error when it overflows to 64.
reg [6:0] high_time;
reg [6:0] low_time;
reg w_edge;
reg no_count;
reg [`MMCME2_ADV_FIXED_WIDTH:1] temp;
begin
// Duty Cycle must be between 0 and 1,000
if(duty_cycle <=0 || duty_cycle >= 100000) begin
$display("ERROR: duty_cycle: %d is invalid", duty_cycle);
$finish;
end
// Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
duty_cycle_fix = (duty_cycle << `MMCME2_ADV_FRAC_PRECISION) / 100_000;
// If the divide is 1 nothing needs to be set except the no_count bit.
// Other values are dummies
if(divide == 7'h01) begin
high_time = 7'h01;
w_edge = 1'b0;
low_time = 7'h01;
no_count = 1'b1;
end else begin
temp = round_frac(duty_cycle_fix*divide, 1);
// comes from above round_frac
high_time = temp[`MMCME2_ADV_FRAC_PRECISION+7:`MMCME2_ADV_FRAC_PRECISION+1];
// If the duty cycle * divide rounded is .5 or greater then this bit
// is set.
w_edge = temp[`MMCME2_ADV_FRAC_PRECISION]; // comes from round_frac
// If the high time comes out to 0, it needs to be set to at least 1
// and w_edge set to 0
if(high_time == 7'h00) begin
high_time = 7'h01;
w_edge = 1'b0;
end
if(high_time == divide) begin
high_time = divide - 1;
w_edge = 1'b1;
end
// Calculate low_time based on the divide setting and set no_count to
// 0 as it is only used when divide is 1.
low_time = divide - high_time;
no_count = 1'b0;
end
// Set the return value.
mmcm_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
end
endfunction
// This function calculates mx, delay_time, and phase_mux
// of a non-fractional counter based on the divide and phase
//
// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
// is used.
function [10:0] mmcm_phase
(
// divide must be an integer (use fractional if not)
// assumed that divide already checked to be valid
input [7:0] divide, // Max divide is 128
// Phase is given in degrees (-360,000 to 360,000)
input signed [31:0] phase
);
reg [`MMCME2_ADV_FIXED_WIDTH:1] phase_in_cycles;
reg [`MMCME2_ADV_FIXED_WIDTH:1] phase_fixed;
reg [1:0] mx;
reg [5:0] delay_time;
reg [2:0] phase_mux;
reg [`MMCME2_ADV_FIXED_WIDTH:1] temp;
begin
if ((phase < -360000) || (phase > 360000)) begin
$display("ERROR: phase of (%d) is not between -360000 and 360000. Instance %m",phase);
$finish;
end
// If phase is less than 0, convert it to a positive phase shift
// Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
if(phase < 0) begin
phase_fixed = ( (phase + 360000) << `MMCME2_ADV_FRAC_PRECISION ) / 1000;
end else begin
phase_fixed = ( phase << `MMCME2_ADV_FRAC_PRECISION ) / 1000;
end
// Put phase in terms of decimal number of vco clock cycles
phase_in_cycles = ( phase_fixed * divide ) / 360;
temp = round_frac(phase_in_cycles, 3);
// set mx to 2'b00 that the phase mux from the VCO is enabled
mx = 2'b00;
phase_mux = temp[`MMCME2_ADV_FRAC_PRECISION:`MMCME2_ADV_FRAC_PRECISION-2];
delay_time = temp[`MMCME2_ADV_FRAC_PRECISION+6:`MMCME2_ADV_FRAC_PRECISION+1];
// Setup the return value
mmcm_phase={mx, phase_mux, delay_time};
end
endfunction
// This function takes in the divide, phase, and duty cycle
// setting to calculate the upper and lower counter registers.
function [37:0] mmcm_calc
(
input [7:0] divide, // Max divide is 128
input signed [31:0] phase,
input [31:0] duty_cycle // Multiplied by 100,000
);
reg [13:0] div_calc;
reg [16:0] phase_calc;
begin
// w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
div_calc = mmcm_divider(divide, duty_cycle);
// mx[10:9], pm[8:6], dt[5:0]
phase_calc = mmcm_phase(divide, phase);
// Return value is the upper and lower address of counter
// Upper address is:
// RESERVED [31:26]
// MX [25:24]
// EDGE [23]
// NOCOUNT [22]
// DELAY_TIME [21:16]
// Lower Address is:
// PHASE_MUX [15:13]
// RESERVED [12]
// HIGH_TIME [11:6]
// LOW_TIME [5:0]
mmcm_calc =
{
// Upper Address
6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
// Lower Address
phase_calc[8:6], 1'b0, div_calc[11:0]
};
end
endfunction
// This function takes in the divide, phase, and duty cycle
// setting to calculate the upper and lower counter registers.
// for fractional multiply/divide functions.
//
//
function [37:0] mmcm_frac_calc
(
input [7:0] divide, // Max divide is 128
input signed [31:0] phase,
input [31:0] duty_cycle, // Multiplied by 100,000
input [9:0] frac // Multiplied by 1000
);
//Required for fractional divide calculations
reg [7:0] lt_frac;
reg [7:0] ht_frac;
reg /*[7:0]*/ wf_fall_frac;
reg /*[7:0]*/ wf_rise_frac;
reg [31:0] a;
reg [7:0] pm_rise_frac_filtered ;
reg [7:0] pm_fall_frac_filtered ;
reg [7:0] clkout0_divide_int;
reg [2:0] clkout0_divide_frac;
reg [7:0] even_part_high;
reg [7:0] even_part_low;
reg [7:0] odd;
reg [7:0] odd_and_frac;
reg [7:0] pm_fall;
reg [7:0] pm_rise;
reg [7:0] dt;
reg [7:0] dt_int;
reg [63:0] dt_calc;
reg [7:0] pm_rise_frac;
reg [7:0] pm_fall_frac;
reg [31:0] a_per_in_octets;
reg [31:0] a_phase_in_cycles;
reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
reg [31: 0] phase_pos;
reg [31: 0] phase_vco;
reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
reg [13:0] div_calc;
reg [16:0] phase_calc;
begin
//convert phase to fixed
if ((phase < -360000) || (phase > 360000)) begin
$display("ERROR: phase of (%d) is not between -360000 and 360000. Instance %m",phase);
// $display("ERROR: phase of $phase is not between -360000 and 360000");
$finish;
end
// Return value is
// Transfer data
// RESERVED [37:36]
// FRAC_TIME [35:33]
// FRAC_WF_FALL [32]
// Upper address is:
// RESERVED [31:26]
// MX [25:24]
// EDGE [23]
// NOCOUNT [22]
// DELAY_TIME [21:16]
// Lower Address is:
// PHASE_MUX [15:13]
// RESERVED [12]
// HIGH_TIME [11:6]
// LOW_TIME [5:0]
clkout0_divide_frac = frac / 125;
clkout0_divide_int = divide;
even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
even_part_low = even_part_high;
odd = clkout0_divide_int - even_part_high - even_part_low;
odd_and_frac = (8*odd) + clkout0_divide_frac;
lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
pm_rise = 0; //0
wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807
wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
//Calculate phase in fractional cycles
a_per_in_octets = (8 * divide) + (frac / 125) ;
a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
dt = dt_calc[7:0];
pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
pm_fall_frac = pm_fall + pm_rise_frac;
pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
div_calc = mmcm_divider(divide, duty_cycle); //Not used since edge and no count are 0 when fractional
phase_calc = mmcm_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
mmcm_frac_calc[37:0] =
{ 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
} ;
end
endfunction
function clkout_duty_chk;
input CLKOUT_DIVIDE;
input CLKOUT_DUTY_CYCLE;
input reg [160:0] CLKOUT_DUTY_CYCLE_N;
integer CLKOUT_DIVIDE, step_tmp;
real CLKOUT_DUTY_CYCLE;
real CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX, CLK_DUTY_CYCLE_CHK, CLK_DUTY_CYCLE_STEP;
real CLK_DUTY_CYCLE_MIN_rnd;
reg clk_duty_tmp_int;
begin
if (CLKOUT_DIVIDE > O_MAX_HT_LT) begin
CLK_DUTY_CYCLE_MIN = 1.0 * (CLKOUT_DIVIDE - O_MAX_HT_LT)/CLKOUT_DIVIDE;
CLK_DUTY_CYCLE_MAX = (O_MAX_HT_LT )/CLKOUT_DIVIDE;
CLK_DUTY_CYCLE_CHK = (O_MAX_HT_LT + 0.5)/CLKOUT_DIVIDE;
CLK_DUTY_CYCLE_MIN_rnd = CLK_DUTY_CYCLE_MIN;
end
else begin
if (CLKOUT_DIVIDE == 1) begin
CLK_DUTY_CYCLE_MIN = 0.0;
CLK_DUTY_CYCLE_MIN_rnd = 0.0;
end
else begin
step_tmp = 1000 / CLKOUT_DIVIDE;
CLK_DUTY_CYCLE_MIN_rnd = step_tmp / 1000.0;
CLK_DUTY_CYCLE_MIN = 1.0 /CLKOUT_DIVIDE;
end
CLK_DUTY_CYCLE_CHK = 1.0;
CLK_DUTY_CYCLE_MAX = 1.0;
end
if (CLKOUT_DUTY_CYCLE > CLK_DUTY_CYCLE_CHK || CLKOUT_DUTY_CYCLE < CLK_DUTY_CYCLE_MIN_rnd) begin
$display("Warning: [Unisim %s-30] %s is set to %f and is not in the allowed range %f to %f. Instance %m ", MODULE_NAME, CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE, CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX );
end
clk_duty_tmp_int = 0;
CLK_DUTY_CYCLE_STEP = 0.5 / CLKOUT_DIVIDE;
for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1)
if (((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) > -0.001 &&
((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) < 0.001)
clk_duty_tmp_int = 1;
if ( clk_duty_tmp_int != 1) begin
$display("Warning: [Unisim %s-31] %s is set to %f and is not an allowed value. Allowed values are:", MODULE_NAME, CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE);
for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1)
$display("%f", CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j);
$display(" Instance %m ");
end
clkout_duty_chk = 1'b1;
end
endfunction
function para_int_range_chk;
input para_in;
input reg [160:0] para_name;
input range_low;
input range_high;
integer para_in;
integer range_low;
integer range_high;
begin
if ( para_in < range_low || para_in > range_high) begin
$display("Error: [Unisim %s-32] The Attribute %s is set to %d. Legal values for this attribute are %d to %d. Instance %m ", MODULE_NAME, para_name, para_in, range_low, range_high);
$finish;
end
para_int_range_chk = 1'b1;
end
endfunction
function para_real_range_chk;
input para_in;
input reg [160:0] para_name;
input range_low;
input range_high;
real para_in;
real range_low;
real range_high;
begin
if ( para_in < range_low || para_in > range_high) begin
$display("Error : [Unisim %s-33] The Attribute %s is set to %f. Legal values for this attribute are %f to %f. Instance %m ", MODULE_NAME, para_name, para_in, range_low, range_high);
$finish;
end
para_real_range_chk = 1'b0;
end
endfunction
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
reg notifier;
`endif
specify
(CLKIN1 => LOCKED) = (100:100:100, 100:100:100);
(CLKIN2 => LOCKED) = (100:100:100, 100:100:100);
(DCLK *> DO) = (100:100:100, 100:100:100);
(DCLK => DRDY) = (100:100:100, 100:100:100);
(PSCLK => PSDONE) = (100:100:100, 100:100:100);
(negedge RST => (CLKFBSTOPPED +: 0)) = (100:100:100, 100:100:100);
(negedge RST => (CLKINSTOPPED +: 0)) = (100:100:100, 100:100:100);
(negedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100);
(posedge RST => (CLKFBSTOPPED +: 0)) = (100:100:100, 100:100:100);
(posedge RST => (CLKINSTOPPED +: 0)) = (100:100:100, 100:100:100);
(posedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge CLKFBIN, 0:0:0, notifier);
$period (negedge CLKFBOUT, 0:0:0, notifier);
$period (negedge CLKFBOUTB, 0:0:0, notifier);
$period (negedge CLKIN1, 0:0:0, notifier);
$period (negedge CLKIN2, 0:0:0, notifier);
$period (negedge CLKOUT0, 0:0:0, notifier);
$period (negedge CLKOUT0B, 0:0:0, notifier);
$period (negedge CLKOUT1, 0:0:0, notifier);
$period (negedge CLKOUT1B, 0:0:0, notifier);
$period (negedge CLKOUT2, 0:0:0, notifier);
$period (negedge CLKOUT2B, 0:0:0, notifier);
$period (negedge CLKOUT3, 0:0:0, notifier);
$period (negedge CLKOUT3B, 0:0:0, notifier);
$period (negedge CLKOUT4, 0:0:0, notifier);
$period (negedge CLKOUT5, 0:0:0, notifier);
$period (negedge CLKOUT6, 0:0:0, notifier);
$period (negedge DCLK, 0:0:0, notifier);
$period (negedge PSCLK, 0:0:0, notifier);
$period (posedge CLKFBIN, 0:0:0, notifier);
$period (posedge CLKFBOUT, 0:0:0, notifier);
$period (posedge CLKFBOUTB, 0:0:0, notifier);
$period (posedge CLKIN1, 0:0:0, notifier);
$period (posedge CLKIN2, 0:0:0, notifier);
$period (posedge CLKOUT0, 0:0:0, notifier);
$period (posedge CLKOUT0B, 0:0:0, notifier);
$period (posedge CLKOUT1, 0:0:0, notifier);
$period (posedge CLKOUT1B, 0:0:0, notifier);
$period (posedge CLKOUT2, 0:0:0, notifier);
$period (posedge CLKOUT2B, 0:0:0, notifier);
$period (posedge CLKOUT3, 0:0:0, notifier);
$period (posedge CLKOUT3B, 0:0:0, notifier);
$period (posedge CLKOUT4, 0:0:0, notifier);
$period (posedge CLKOUT5, 0:0:0, notifier);
$period (posedge CLKOUT6, 0:0:0, notifier);
$period (posedge DCLK, 0:0:0, notifier);
$period (posedge PSCLK, 0:0:0, notifier);
$setuphold (posedge DCLK, negedge DADDR, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DADDR_delay);
$setuphold (posedge DCLK, negedge DEN, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DEN_delay);
$setuphold (posedge DCLK, negedge DI, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DI_delay);
$setuphold (posedge DCLK, negedge DWE, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DWE_delay);
$setuphold (posedge DCLK, posedge DADDR, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DADDR_delay);
$setuphold (posedge DCLK, posedge DEN, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DEN_delay);
$setuphold (posedge DCLK, posedge DI, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DI_delay);
$setuphold (posedge DCLK, posedge DWE, 0:0:0, 0:0:0, notifier,,, DCLK_delay, DWE_delay);
$setuphold (posedge PSCLK, negedge PSEN, 0:0:0, 0:0:0, notifier,,, PSCLK_delay, PSEN_delay);
$setuphold (posedge PSCLK, negedge PSINCDEC, 0:0:0, 0:0:0, notifier,,, PSCLK_delay, PSINCDEC_delay);
$setuphold (posedge PSCLK, posedge PSEN, 0:0:0, 0:0:0, notifier,,, PSCLK_delay, PSEN_delay);
$setuphold (posedge PSCLK, posedge PSINCDEC, 0:0:0, 0:0:0, notifier,,, PSCLK_delay, PSINCDEC_delay);
$width (negedge CLKIN1, 0:0:0, 0, notifier);
$width (negedge CLKIN2, 0:0:0, 0, notifier);
$width (negedge DCLK, 0:0:0, 0, notifier);
$width (negedge PSCLK, 0:0:0, 0, notifier);
$width (negedge PWRDWN, 0:0:0, 0, notifier);
$width (negedge RST, 0:0:0, 0, notifier);
$width (posedge CLKIN1, 0:0:0, 0, notifier);
$width (posedge CLKIN2, 0:0:0, 0, notifier);
$width (posedge DCLK, 0:0:0, 0, notifier);
$width (posedge PSCLK, 0:0:0, 0, notifier);
$width (posedge PWRDWN, 0:0:0, 0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 20 02:54:52 2016
/////////////////////////////////////////////////////////////
module GeAr_N8_R1_P5 ( in1, in2, res );
input [7:0] in1;
input [7:0] in2;
output [8:0] res;
wire intadd_28_CI, intadd_28_n4, intadd_28_n3, intadd_28_n2, intadd_28_n1,
n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18;
CMPR32X2TS intadd_28_U5 ( .A(in2[1]), .B(in1[1]), .C(intadd_28_CI), .CO(
intadd_28_n4), .S(res[1]) );
CMPR32X2TS intadd_28_U4 ( .A(in2[2]), .B(in1[2]), .C(intadd_28_n4), .CO(
intadd_28_n3), .S(res[2]) );
CMPR32X2TS intadd_28_U3 ( .A(in2[3]), .B(in1[3]), .C(intadd_28_n3), .CO(
intadd_28_n2), .S(res[3]) );
CMPR32X2TS intadd_28_U2 ( .A(in2[4]), .B(in1[4]), .C(intadd_28_n2), .CO(
intadd_28_n1), .S(res[4]) );
XOR2XLTS U2 ( .A(in1[6]), .B(in2[6]), .Y(n6) );
AO22XLTS U3 ( .A0(in2[3]), .A1(in1[3]), .B0(in2[2]), .B1(in1[2]), .Y(n10) );
CLKAND2X2TS U4 ( .A(in2[1]), .B(in1[1]), .Y(n2) );
CLKAND2X2TS U5 ( .A(in2[0]), .B(in1[0]), .Y(intadd_28_CI) );
AOI222X4TS U6 ( .A0(n13), .A1(n12), .B0(n13), .B1(n11), .C0(n12), .C1(n11),
.Y(n14) );
AOI2BB2XLTS U7 ( .B0(in1[5]), .B1(n8), .A0N(n8), .A1N(in1[5]), .Y(n9) );
INVX2TS U8 ( .A(in2[5]), .Y(n8) );
CMPR32X2TS U9 ( .A(in1[2]), .B(in2[2]), .C(n2), .CO(n3) );
CMPR32X2TS U10 ( .A(in1[3]), .B(in2[3]), .C(n3), .CO(n4) );
CMPR32X2TS U11 ( .A(in1[4]), .B(in2[4]), .C(n4), .CO(n5) );
CMPR32X2TS U12 ( .A(in1[5]), .B(in2[5]), .C(n5), .CO(n7) );
XOR2XLTS U13 ( .A(n7), .B(n6), .Y(res[6]) );
AOI2BB1XLTS U14 ( .A0N(in2[0]), .A1N(in1[0]), .B0(intadd_28_CI), .Y(res[0])
);
XNOR2X1TS U15 ( .A(intadd_28_n1), .B(n9), .Y(res[5]) );
OAI21X1TS U16 ( .A0(in2[3]), .A1(in1[3]), .B0(n10), .Y(n13) );
INVX2TS U17 ( .A(in2[4]), .Y(n12) );
INVX2TS U18 ( .A(in1[4]), .Y(n11) );
AOI222X1TS U19 ( .A0(in2[5]), .A1(in1[5]), .B0(in2[5]), .B1(n14), .C0(in1[5]), .C1(n14), .Y(n17) );
INVX2TS U20 ( .A(in2[6]), .Y(n16) );
INVX2TS U21 ( .A(in1[6]), .Y(n15) );
AOI222X4TS U22 ( .A0(n17), .A1(n16), .B0(n17), .B1(n15), .C0(n16), .C1(n15),
.Y(n18) );
CMPR32X2TS U23 ( .A(in2[7]), .B(in1[7]), .C(n18), .CO(res[8]), .S(res[7]) );
initial $sdf_annotate("GeAr_N8_R1_P5_syn.sdf");
endmodule
|
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-10-2016
*/
// Pipeline operator
module jt51_op(
`ifdef TEST_SUPPORT
input test_eg,
input test_op0,
`endif
input rst,
input clk,
input cen, // P1
input [9:0] pg_phase_X,
input [2:0] con_I,
input [2:0] fb_II,
// volume
input [9:0] eg_atten_XI,
// modulation
input use_prevprev1,
input use_internal_x,
input use_internal_y,
input use_prev2,
input use_prev1,
input test_214,
input m1_enters,
input c1_enters,
`ifdef SIMULATION
input zero,
`endif
// output data
output signed [13:0] op_XVII
);
/* enters exits
m1 c1
m2 S4
c1 m1
S4 m2
*/
wire signed [13:0] prev1, prevprev1, prev2;
jt51_sh #( .width(14), .stages(8)) prev1_buffer(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.din ( c1_enters ? op_XVII : prev1 ),
.drop ( prev1 )
);
jt51_sh #( .width(14), .stages(8)) prevprev1_buffer(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.din ( c1_enters ? prev1 : prevprev1 ),
.drop ( prevprev1 )
);
jt51_sh #( .width(14), .stages(8)) prev2_buffer(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.din ( m1_enters ? op_XVII : prev2 ),
.drop ( prev2 )
);
// REGISTER/CYCLE 1
// Creation of phase modulation (FM) feedback signal, before shifting
reg [13:0] x, y;
reg [14:0] xs, ys, pm_preshift_II;
reg m1_II;
always @(*) begin
x = ( {14{use_prevprev1}} & prevprev1 ) |
( {14{use_internal_x}} & op_XVII ) |
( {14{use_prev2}} & prev2 );
y = ( {14{use_prev1}} & prev1 ) |
( {14{use_internal_y}} & op_XVII );
xs = { x[13], x }; // sign-extend
ys = { y[13], y }; // sign-extend
end
always @(posedge clk) if(cen) begin
pm_preshift_II <= xs + ys; // carry is discarded
m1_II <= m1_enters;
end
/* REGISTER/CYCLE 2-7 (also YM2612 extra cycles 1-6)
Shifting of FM feedback signal, adding phase from PG to FM phase
In YM2203, phasemod_II is not registered at all, it is latched on the first edge
in add_pg_phase and the second edge is the output of add_pg_phase. In the YM2612, there
are 6 cycles worth of registers between the generated (non-registered) phasemod_II signal
and the input to add_pg_phase. */
reg [9:0] phasemod_II;
wire [9:0] phasemod_X;
always @(*) begin
// Shift FM feedback signal
if (!m1_II ) // Not m1
phasemod_II = pm_preshift_II[10:1]; // Bit 0 of pm_preshift_II is never used
else // m1
case( fb_II )
3'd0: phasemod_II = 10'd0;
3'd1: phasemod_II = { {4{pm_preshift_II[14]}}, pm_preshift_II[14:9] };
3'd2: phasemod_II = { {3{pm_preshift_II[14]}}, pm_preshift_II[14:8] };
3'd3: phasemod_II = { {2{pm_preshift_II[14]}}, pm_preshift_II[14:7] };
3'd4: phasemod_II = { pm_preshift_II[14], pm_preshift_II[14:6] };
3'd5: phasemod_II = pm_preshift_II[14:5];
3'd6: phasemod_II = pm_preshift_II[13:4];
3'd7: phasemod_II = pm_preshift_II[12:3];
default: phasemod_II = 10'dx;
endcase
end
// REGISTER/CYCLE 2-9
jt51_sh #( .width(10), .stages(8)) phasemod_sh(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.din ( phasemod_II ),
.drop ( phasemod_X )
);
// REGISTER/CYCLE 10
reg [ 9:0] phase;
// Sets the maximum number of fanouts for a register or combinational
// cell. The Quartus II software will replicate the cell and split
// the fanouts among the duplicates until the fanout of each cell
// is below the maximum.
reg [ 7:0] phaselo_XI, aux_X;
reg signbit_X;
always @(*) begin
phase = phasemod_X + pg_phase_X;
aux_X = phase[7:0] ^ {8{~phase[8]}};
signbit_X = phase[9];
end
always @(posedge clk) if(cen) begin
phaselo_XI <= aux_X;
end
wire [45:0] sta_XI;
jt51_phrom u_phrom(
.clk ( clk ),
.cen ( cen ),
.addr ( aux_X[5:1]),
.ph ( sta_XI )
);
// REGISTER/CYCLE 11
// Sine table
// Main sine table body
reg [18:0] stb;
reg [10:0] stf, stg;
reg [11:0] logsin;
reg [10:0] subtresult;
reg [11:0] atten_internal_XI;
always @(*) begin
//sta_XI = sinetable[ phaselo_XI[5:1] ];
// 2-bit row chooser
case( phaselo_XI[7:6] )
2'b00: stb = { 10'b0, sta_XI[29], sta_XI[25], 2'b0, sta_XI[18],
sta_XI[14], 1'b0, sta_XI[7] , sta_XI[3] };
2'b01: stb = { 6'b0 , sta_XI[37], sta_XI[34], 2'b0, sta_XI[28],
sta_XI[24], 2'b0, sta_XI[17], sta_XI[13], sta_XI[10], sta_XI[6], sta_XI[2] };
2'b10: stb = { 2'b0, sta_XI[43], sta_XI[41], 2'b0, sta_XI[36],
sta_XI[33], 2'b0, sta_XI[27], sta_XI[23], 1'b0, sta_XI[20],
sta_XI[16], sta_XI[12], sta_XI[9], sta_XI[5], sta_XI[1] };
2'b11: stb = {
sta_XI[45], sta_XI[44], sta_XI[42], sta_XI[40]
, sta_XI[39], sta_XI[38], sta_XI[35], sta_XI[32]
, sta_XI[31], sta_XI[30], sta_XI[26], sta_XI[22]
, sta_XI[21], sta_XI[19], sta_XI[15], sta_XI[11]
, sta_XI[8], sta_XI[4], sta_XI[0] };
default: stb = 19'dx;
endcase
// Fixed value to sum
stf = { stb[18:15], stb[12:11], stb[8:7], stb[4:3], stb[0] };
// Gated value to sum; bit 14 is indeed used twice
if( phaselo_XI[0] )
stg = { 2'b0, stb[14], stb[14:13], stb[10:9], stb[6:5], stb[2:1] };
else
stg = 11'd0;
// Sum to produce final logsin value
logsin = stf + stg; // Carry-out of 11-bit addition becomes 12th bit
// Invert-subtract logsin value from EG attenuation value, with inverted carry
// In the actual chip, the output of the above logsin sum is already inverted.
// The two LSBs go through inverters (so they're non-inverted); the eg_atten_XI signal goes through inverters.
// The adder is normal except the carry-in is 1. It's a 10-bit adder.
// The outputs are inverted outputs, including the carry bit.
//subtresult = not (('0' & not eg_atten_XI) - ('1' & logsin([11:2])));
// After a little pencil-and-paper, turns out this is equivalent to a regular adder!
subtresult = eg_atten_XI + logsin[11:2];
// Place all but carry bit into result; also two LSBs of logsin
// If addition overflowed, make it the largest value (saturate)
atten_internal_XI = { subtresult[9:0], logsin[1:0] } | {12{subtresult[10]}};
end
// Register cycle 12
// Exponential table
wire [44:0] exp_XII;
reg [11:0] totalatten_XII;
reg [12:0] etb;
reg [ 9:0] etf;
reg [ 2:0] etg;
jt51_exprom u_exprom(
.clk ( clk ),
.cen ( cen ),
.addr ( atten_internal_XI[5:1] ),
.exp ( exp_XII )
);
always @(posedge clk) if(cen) begin
totalatten_XII <= atten_internal_XI;
end
//wire [1:0] et_sel = totalatten_XII[7:6];
//wire [4:0] et_fine = totalatten_XII[5:1];
// Main sine table body
always @(*) begin
// 2-bit row chooser
case( totalatten_XII[7:6] )
2'b00: begin
etf = { 1'b1, exp_XII[44:36] };
etg = { 1'b1, exp_XII[35:34] };
end
2'b01: begin
etf = exp_XII[33:24];
etg = { 2'b10, exp_XII[23] };
end
2'b10: begin
etf = { 1'b0, exp_XII[22:14] };
etg = exp_XII[13:11];
end
2'b11: begin
etf = { 2'b00, exp_XII[10:3] };
etg = exp_XII[2:0];
end
endcase
end
reg [9:0] mantissa_XIII;
reg [3:0] exponent_XIII;
always @(posedge clk) if(cen) begin
//RESULT
mantissa_XIII <= etf + { 7'd0, totalatten_XII[0] ? 3'd0 : etg }; //carry-out discarded
exponent_XIII <= totalatten_XII[11:8];
end
// REGISTER/CYCLE 13
// Introduce test bit as MSB, 2's complement & Carry-out discarded
reg [12:0] shifter, shifter_2, shifter_3;
always @(*) begin
// Floating-point to integer, and incorporating sign bit
// Two-stage shifting of mantissa_XIII by exponent_XIII
shifter = { 3'b001, mantissa_XIII };
case( ~exponent_XIII[1:0] )
2'b00: shifter_2 = { 1'b0, shifter[12:1] }; // LSB discarded
2'b01: shifter_2 = shifter;
2'b10: shifter_2 = { shifter[11:0], 1'b0 };
2'b11: shifter_2 = { shifter[10:0], 2'b0 };
endcase
case( ~exponent_XIII[3:2] )
2'b00: shifter_3 = {12'b0, shifter_2[12] };
2'b01: shifter_3 = { 8'b0, shifter_2[12:8] };
2'b10: shifter_3 = { 4'b0, shifter_2[12:4] };
2'b11: shifter_3 = shifter_2;
endcase
end
reg signed [13:0] op_XIII;
wire signbit_XIII;
always @(*) begin
op_XIII = ({ test_214, shifter_3 } ^ {14{signbit_XIII}}) + {13'd0, signbit_XIII};
end
jt51_sh #( .width(14), .stages(4)) out_padding(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.din ( op_XIII ), // note op_XIII was not latched, is a comb output
.drop ( op_XVII )
);
jt51_sh #( .width(1), .stages(3)) shsignbit(
.rst ( rst ),
.clk ( clk ),
.cen ( cen ),
.din ( signbit_X ),
.drop ( signbit_XIII )
);
/////////////////// Debug
`ifdef JT51_DEBUG
`ifdef SIMULATION
/* verilator lint_off PINMISSING */
wire [4:0] cnt;
sep32_cnt u_sep32_cnt (.clk(clk), .cen(cen), .zero(zero), .cnt(cnt));
sep32 #(.width(14),.stg(17)) sep_op(
.clk ( clk ),
.cen ( cen ),
.mixed ( op_XVII ),
.cnt ( cnt )
);
/* verilator lint_on PINMISSING */
`endif
`endif
endmodule
|
/*
* University of Illinois/NCSA
* Open Source License
*
* Copyright (c) 2007-2014,The Board of Trustees of the University of
* Illinois. All rights reserved.
*
* Copyright (c) 2014 Matthew Hicks
*
* Developed by:
*
* Matthew Hicks in the Department of Computer Science
* The University of Illinois at Urbana-Champaign
* http://www.impedimentToProgress.com
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated
* documentation files (the "Software"), to deal with the
* Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute,
* sublicense, and/or sell copies of the Software, and to permit
* persons to whom the Software is furnished to do so, subject
* to the following conditions:
*
* Redistributions of source code must retain the above
* copyright notice, this list of conditions and the
* following disclaimers.
*
* Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the
* following disclaimers in the documentation and/or other
* materials provided with the distribution.
*
* Neither the names of Sam King, the University of Illinois,
* nor the names of its contributors may be used to endorse
* or promote products derived from this Software without
* specific prior written permission.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE CONTRIBUTORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS WITH THE SOFTWARE.
*/
// Make index 1 based, otherwise I would need subtraction
reg [num_cks_max:1] monitor;
wire fire_2state_comb;
always @(posedge clk)
if (`OVL_RESET_SIGNAL == 1'b0)
monitor <= {num_cks_max{1'b0}};
else if(enable)
monitor <= {monitor[num_cks_max-1:1], start_event};
wire fire_gate = `OVL_RESET_SIGNAL & enable;
wire fire_prop = ~test_expr;
wire fire_always = fire_prop;
wire fire_edge = monitor[1] & ~monitor[2] & fire_prop;
wire fire_next = monitor[num_cks] & fire_prop;
wire fire_selected = (select == 2) ? fire_prop : (select == 3) ? fire_always : (select == 0) ? fire_edge : fire_next;
assign fire_2state_comb = fire_gate & fire_selected;
wire fire_xcheck = 1'b0;
wire fire_cover = 1'b0; |
module ram(
input clock ,
input chip_enable ,
input read_enable ,
input [31:0] read_address ,
output reg [31:0] read_data ,
input write_enable ,
input [31:0] write_address,
input [ 3:0] write_select ,
input [31:0] write_data
);
reg [31:0] storage[0:1024];
always @ (*) begin
if (chip_enable == `CHIP_ENABLE && read_enable == `READ_ENABLE) begin
read_data <= storage[read_address[18:2]];
end
else begin
read_data <= 32'b0;
end
end
always @ (negedge clock) begin
if (chip_enable == `CHIP_ENABLE && write_enable == `WRITE_ENABLE) begin
if (write_select[3] == 1'b1) begin
storage[write_address[18:2]][31:24] <= write_data[31:24];
end
if (write_select[2] == 1'b1) begin
storage[write_address[18:2]][23:16] <= write_data[23:16];
end
if (write_select[1] == 1'b1) begin
storage[write_address[18:2]][15:8] <= write_data[15:8];
end
if (write_select[0] == 1'b1) begin
storage[write_address[18:2]][7:0] <= write_data[7:0];
end
end
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLXTP_PP_SYMBOL_V
`define SKY130_FD_SC_HD__DLXTP_PP_SYMBOL_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dlxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLXTP_PP_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A2111OI_SYMBOL_V
`define SKY130_FD_SC_HS__A2111OI_SYMBOL_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a2111oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
input D1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A2111OI_SYMBOL_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Wed Nov 2 09:18:53 2016
/////////////////////////////////////////////////////////////
module FPU_Add_Subtract_Function_W64_EW11_SW52_SWR55_EWR6 ( clk, rst, beg_FSM,
ack_FSM, Data_X, Data_Y, add_subt, r_mode, overflow_flag,
underflow_flag, ready, final_result_ieee );
input [63:0] Data_X;
input [63:0] Data_Y;
input [1:0] r_mode;
output [63:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM, add_subt;
output overflow_flag, underflow_flag, ready;
wire FSM_selector_C, add_overflow_flag, FSM_selector_D, intAS,
sign_final_result, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21,
n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35,
n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49,
n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63,
n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77,
n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91,
n92, n93, n94, n95, n96, n97, n98, n99, n100, n101, n102, n103, n104,
n105, n106, n107, n108, n109, n110, n111, n112, n113, n114, n115,
n116, n117, n118, n119, n120, n121, n122, n123, n124, n125, n126,
n127, n128, n129, n130, n131, n132, n133, n134, n135, n136, n137,
n138, n139, n140, n141, n142, n143, n144, n145, n146, n147, n148,
n149, n150, n151, n152, n153, n154, n155, n156, n157, n158, n159,
n160, n161, n162, n163, n164, n165, n166, n167, n168, n169, n170,
n171, n172, n173, n174, n175, n176, n177, n178, n179, n180, n181,
n182, n183, n184, n185, n186, n187, n188, n189, n190, n191, n192,
n193, n194, n195, n196, n197, n198, n199, n200, n201, n202, n203,
n204, n205, n206, n207, n208, n209, n210, n211, n212, n213, n214,
n215, n216, n217, n218, n219, n220, n221, n222, n223, n224, n225,
n226, n227, n228, n229, n230, n231, n232, n233, n234, n235, n236,
n237, n238, n239, n240, n241, n242, n243, n244, n245, n246, n247,
n248, n249, n250, n251, n252, n253, n254, n255, n256, n257, n258,
n259, n260, n261, n262, n263, n264, n265, n266, n267, n268, n269,
n270, n271, n272, n273, n274, n275, n276, n277, n278, n279, n280,
n281, n282, n283, n284, n285, n286, n287, n288, n289, n290, n291,
n292, n293, n294, n295, n296, n297, n298, n299, n300, n301, n302,
n303, n304, n305, n306, n307, n308, n309, n310, n311, n312, n313,
n314, n315, n316, n317, n318, n319, n320, n321, n322, n323, n324,
n325, n326, n327, n328, n329, n330, n331, n332, n333, n334, n335,
n336, n337, n338, n339, n340, n341, n342, n343, n344, n345, n346,
n347, n348, n349, n350, n351, n352, n353, n354, n355, n356, n357,
n358, n359, n360, n361, n362, n363, n364, n365, n366, n367, n368,
n369, n370, n371, n372, n373, n374, n375, n376, n377, n378, n379,
n380, n381, n382, n383, n384, n385, n386, n387, n388, n389, n390,
n391, n392, n393, n394, n395, n396, n397, n398, n399, n400, n401,
n402, n403, n404, n405, n406, n407, n408, n409, n410, n411, n412,
n413, n414, n415, n416, n417, n418, n419, n420, n421, n422, n423,
n424, n425, n426, n427, n428, n429, n430, n431, n432, n433, n434,
n435, n436, n437, n438, n439, n440, n441, n442, n443, n444, n445,
n446, n447, n448, n449, n450, n451, n452, n453, n454, n455, n456,
n457, n458, n459, n460, n461, n462, n463, n464, n465, n466, n467,
n468, n469, n478, n1334, n1335, n1336, n1337, n1338, n1339, n1340,
n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350,
n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360,
n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370,
n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380,
n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390,
n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400,
n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410,
n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420,
n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430,
n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440,
n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450,
n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460,
n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470,
n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480,
n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490,
n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500,
n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510,
n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520,
n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530,
n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540,
n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550,
n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560,
n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570,
n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580,
n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590,
n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600,
n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610,
n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620,
n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630,
n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640,
n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650,
n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660,
n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670,
n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680,
n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690,
n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700,
n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710,
n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720,
n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730,
n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740,
n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750,
n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760,
n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770,
n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780,
n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790,
n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800,
n1801, n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810,
n1811, n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820,
n1821, n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830,
n1831, n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840,
n1841, n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850,
n1851, n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860,
n1861, n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870,
n1871, n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880,
n1881, n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890,
n1891, n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900,
n1901, n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910,
n1911, n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920,
n1921, n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930,
n1931, n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940,
n1941, n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950,
n1951, n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960,
n1961, n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970,
n1971, n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980,
n1981, n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990,
n1991, n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000,
n2001, n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010,
n2011, n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020,
n2021, n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030,
n2031, n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040,
n2041, n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050,
n2051, n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060,
n2061, n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070,
n2071, n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080,
n2081, n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090,
n2091, n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100,
n2101, n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110,
n2111, n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120,
n2121, n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130,
n2131, n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140,
n2141, n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150,
n2151, n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160,
n2161, n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170,
n2171, n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180,
n2181, n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190,
n2191, n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200,
n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210,
n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220,
n2221, n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230,
n2231, n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240,
n2241, n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250,
n2251, n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260,
n2261, n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270,
n2271, n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280,
n2281, n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290,
n2291, n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300,
n2301, n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310,
n2311, n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320,
n2321, n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330,
n2331, n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340,
n2341, n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350,
n2351, n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360,
n2361, n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370,
n2371, n2372, n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380,
n2381, n2382, n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390,
n2391, n2392, n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400,
n2401, n2402, n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410,
n2411, n2412, n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420,
n2421, n2422, n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430,
n2431, n2432, n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440,
n2441, n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450,
n2451, n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460,
n2461, n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470,
n2471, n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480,
n2481, n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490,
n2491, n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500,
n2501, n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510,
n2511, n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520,
n2521, n2522, n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530,
n2531, n2532, n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540,
n2541, n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550,
n2551, n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560,
n2561, n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570,
n2571, n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580,
n2581, n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2589, n2590,
n2591, n2592, n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600,
n2601, n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610,
n2611, n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620,
n2621, n2622, n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630,
n2631, n2632, n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640,
n2641, n2642, n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650,
n2651, n2652, n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660,
n2661, n2662, n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670,
n2671, n2672, n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2680,
n2681, n2682, n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690,
n2691, n2692, n2693, n2694, n2695, n2696, n2697, n2698, n2699, n2700,
n2701, n2702, n2703, n2704, n2705, n2706, n2707, n2708, n2709, n2710,
n2711, n2712, n2713, n2714, n2715, n2716, n2717, n2718, n2719, n2720,
n2721, n2722, n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730,
n2731, n2732, n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740,
n2741, n2742, n2743, n2744, n2745, n2746, n2747, n2748, n2749, n2750,
n2751, n2752, n2753, n2754, n2755, n2756, n2757, n2758, n2759, n2760,
n2761, n2762, n2763, n2764, n2765, n2766, n2767, n2768, n2769, n2770,
n2771, n2772, n2773, n2774, n2775, n2776, n2777, n2778, n2779, n2780,
n2781, n2782, n2783, n2784, n2785, n2786, n2787, n2788, n2789, n2790,
n2791, n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799, n2800,
n2801, n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809, n2810,
n2811, n2812, n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820,
n2821, n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830,
n2831, n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840,
n2841, n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850,
n2851, n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860,
n2861, n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870,
n2871, n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880,
n2881, n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890,
n2891, n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900,
n2901, n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910,
n2911, n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920,
n2921, n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930,
n2931, n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940,
n2941, n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950,
n2951, n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960,
n2961, n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970,
n2971, n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980,
n2981, n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990,
n2991, n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000,
n3001, n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010,
n3011, n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020,
n3021, n3022, n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030,
n3031, n3032, n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040,
n3041, n3042, n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050,
n3051, n3052, n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060,
n3061, n3062, n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070,
n3071, n3072, n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080,
n3081, n3082, n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090,
n3091, n3092, n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100,
n3101, n3102, n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110,
n3111, n3112, n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120,
n3121, n3122, n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130,
n3131, n3132, n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140,
n3141, n3142, n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150,
n3151, n3152, n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160,
n3161, n3162, n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170,
n3171, n3172, n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180,
n3181, n3182, n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190,
n3191, n3192, n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200,
n3201, n3202, n3203, n3204, n3205, n3206, n3207, n3208, n3209, n3210,
n3211, n3212, n3213, n3214, n3215, n3216, n3217, n3218, n3219, n3220,
n3221, n3222, n3223, n3224, n3225, n3226, n3227, n3228, n3229, n3230,
n3231, n3232, n3233, n3234, n3235, n3236, n3237, n3238, n3239, n3240,
n3241, n3242, n3243, n3244, n3245, n3246, n3247, n3248, n3249, n3250,
n3251, n3252, n3253, n3254, n3255, n3256, n3257, n3258, n3259, n3260,
n3261, n3262, n3263, n3264, n3265, n3266, n3267, n3268, n3269, n3270,
n3271, n3272, n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280,
n3281, n3282, n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290,
n3291, n3292, n3293, n3294, n3295, n3296, n3297, n3298, n3299, n3300,
n3301, n3302, n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310,
n3311, n3312, n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3320,
n3321, n3322, n3323, n3324, n3325, n3326, n3327, n3328, n3329, n3330,
n3331, n3332, n3333, n3334, n3335, n3336, n3337, n3338, n3339, n3340,
n3341, n3342, n3343, n3344, n3345, n3346, n3347, n3348, n3349, n3350,
n3351, n3352, n3353, n3354, n3355, n3356, n3357, n3358, n3359, n3360,
n3361, n3362, n3363, n3364, n3365, n3366, n3367, n3368, n3369, n3370,
n3371, n3372, n3373, n3374, n3375, n3376, n3377, n3378, n3379, n3380,
n3381, n3382, n3383, n3384, n3385, n3386, n3387, n3388, n3389, n3390,
n3391, n3392, n3393, n3394, n3395, n3396, n3397, n3398, n3399, n3400,
n3401, n3402, n3403, n3404, n3405, n3406, n3407, n3408, n3409, n3410,
n3411, n3412, n3413, n3414, n3415, n3416, n3417, n3418, n3419, n3420,
n3421, n3422, n3423, n3424, n3425, n3426, n3427, n3428, n3429, n3430,
n3431, n3432, n3433, n3434, n3435, n3436, n3437, n3438, n3439, n3440,
n3441, n3442, n3443, n3444, n3445, n3446, n3447, n3448, n3449, n3450,
n3451, n3452, n3453, n3454, n3455, n3456, n3457, n3458, n3459, n3460,
n3461, n3462, n3463, n3464, n3465, n3466, n3467, n3468, n3469, n3470,
n3471, n3472, n3473, n3474, n3475, n3476, n3477, n3478, n3479, n3480,
n3481, n3482, n3483, n3484, n3485, n3486, n3487, n3488, n3489, n3490,
n3491, n3492, n3493, n3494, n3495, n3496, n3497, n3498, n3499, n3500,
n3501, n3502, n3503, n3504, n3505, n3506, n3507, n3508, n3509, n3510,
n3511, n3512, n3513, n3514, n3515, n3516, n3517, n3518, n3519, n3520,
n3521, n3522, n3523, n3524, n3525, n3526, n3527, n3528, n3529, n3530,
n3531, n3532, n3533, n3534, n3535, n3536, n3537, n3538, n3539, n3540,
n3541, n3542, n3543, n3544, n3545, n3546, n3547, n3548, n3549, n3550,
n3551, n3552, n3553, n3554, n3555, n3556, n3557, n3558, n3559, n3560,
n3561, n3562, n3563, n3564, n3565, n3566, n3567, n3568, n3569, n3570,
n3571, n3572, n3573, n3574, n3575, n3576, n3577, n3578, n3579, n3580,
n3581, n3582, n3583, n3584, n3585, n3586, n3587, n3588, n3589, n3590,
n3591, n3592, n3593, n3594, n3595, n3596, n3597, n3598, n3599, n3600,
n3601, n3602, n3603, n3604, n3605, n3606, n3607, n3608, n3609, n3610,
n3611, n3612, n3613, n3614, n3615, n3616, n3617, n3618, n3619, n3620,
n3621, n3622, n3623, n3624, n3625, n3626, n3627, n3628, n3629, n3630,
n3631, n3632, n3633, n3634, n3635, n3636, n3637, n3638, n3639, n3640,
n3641, n3642, n3643, n3644, n3645, n3646, n3647, n3648, n3649, n3650,
n3651, n3652, n3653, n3654, n3655, n3656;
wire [1:0] FSM_selector_B;
wire [63:0] intDX;
wire [63:0] intDY;
wire [62:0] DMP;
wire [62:0] DmP;
wire [10:0] exp_oper_result;
wire [5:0] LZA_output;
wire [54:0] Add_Subt_result;
wire [54:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [109:0] Barrel_Shifter_module_Mux_Array_Data_array;
DFFRX4TS Sel_D_Q_reg_0_ ( .D(n466), .CK(clk), .RN(n478), .Q(FSM_selector_D),
.QN(n3518) );
DFFRX4TS FS_Module_state_reg_reg_3_ ( .D(n464), .CK(clk), .RN(n3634), .Q(
FS_Module_state_reg[3]), .QN(n3519) );
DFFRX2TS Add_Subt_Sgf_module_Add_overflow_Result_Q_reg_0_ ( .D(n463), .CK(
clk), .RN(n3656), .Q(add_overflow_flag), .QN(n3481) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_53_ ( .D(n462), .CK(clk),
.RN(n3655), .Q(Add_Subt_result[53]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_52_ ( .D(n461), .CK(clk),
.RN(n3655), .Q(Add_Subt_result[52]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_51_ ( .D(n460), .CK(clk),
.RN(n3655), .Q(Add_Subt_result[51]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_50_ ( .D(n459), .CK(clk),
.RN(n3655), .Q(Add_Subt_result[50]), .QN(n3602) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_49_ ( .D(n458), .CK(clk),
.RN(n3655), .Q(Add_Subt_result[49]), .QN(n3475) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_46_ ( .D(n455), .CK(clk),
.RN(n3655), .Q(Add_Subt_result[46]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_45_ ( .D(n454), .CK(clk),
.RN(n3655), .Q(Add_Subt_result[45]), .QN(n3604) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_54_ ( .D(n408), .CK(clk),
.RN(n3656), .Q(Add_Subt_result[54]), .QN(n3603) );
DFFRX4TS FS_Module_state_reg_reg_0_ ( .D(n407), .CK(clk), .RN(n3634), .Q(
FS_Module_state_reg[0]), .QN(n3450) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_62_ ( .D(n340), .CK(clk), .RN(
n3632), .Q(DmP[62]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_61_ ( .D(n337), .CK(clk), .RN(
n3632), .Q(DmP[61]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_60_ ( .D(n334), .CK(clk), .RN(
n3632), .Q(DmP[60]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_59_ ( .D(n331), .CK(clk), .RN(
n3632), .Q(DmP[59]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_58_ ( .D(n328), .CK(clk), .RN(
n3632), .Q(DmP[58]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_57_ ( .D(n325), .CK(clk), .RN(
n3632), .Q(DmP[57]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_56_ ( .D(n322), .CK(clk), .RN(
n3632), .Q(DmP[56]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_55_ ( .D(n319), .CK(clk), .RN(
n3631), .Q(DmP[55]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_54_ ( .D(n316), .CK(clk), .RN(
n3631), .Q(DmP[54]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_53_ ( .D(n313), .CK(clk), .RN(
n3631), .Q(DmP[53]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_52_ ( .D(n310), .CK(clk), .RN(
n3631), .Q(DmP[52]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_51_ ( .D(n307), .CK(clk), .RN(
n3609), .Q(DmP[51]) );
DFFRXLTS Oper_Start_in_module_mRegister_Q_reg_46_ ( .D(n292), .CK(clk), .RN(
n3610), .Q(DmP[46]), .QN(n3601) );
DFFRXLTS Oper_Start_in_module_SignRegister_Q_reg_0_ ( .D(n151), .CK(clk),
.RN(n3656), .Q(sign_final_result), .QN(n3472) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_3_ ( .D(n137), .CK(
clk), .RN(n3650), .Q(LZA_output[3]) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_2_ ( .D(n136), .CK(
clk), .RN(n3651), .Q(LZA_output[2]) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_1_ ( .D(n135), .CK(
clk), .RN(n3650), .Q(LZA_output[1]) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_0_ ( .D(n134), .CK(
clk), .RN(n3631), .Q(LZA_output[0]) );
DFFRXLTS Leading_Zero_Detector_Module_Output_Reg_Q_reg_5_ ( .D(n133), .CK(
clk), .RN(n3635), .Q(LZA_output[5]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_7_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[7]), .CK(clk), .RN(n3621),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[62]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_3_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[3]), .CK(clk), .RN(n3622),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[58]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_6_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[6]), .CK(clk), .RN(n3622),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[61]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_5_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[5]), .CK(clk), .RN(n3622),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[60]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_1_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[1]), .CK(clk), .RN(n3622),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[56]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_4_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[4]), .CK(clk), .RN(n3622),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[59]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_2_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[2]), .CK(clk), .RN(n3624),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[57]) );
DFFRXLTS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_0_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[0]), .CK(clk), .RN(n3624),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[55]) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n23), .CK(clk), .RN(
n3634), .Q(Sgf_normalized_result[1]), .QN(n3497) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_1_ ( .D(n410), .CK(clk),
.RN(n3650), .Q(Add_Subt_result[1]), .QN(n3596) );
DFFRX1TS XRegister_Q_reg_23_ ( .D(n367), .CK(clk), .RN(n3608), .Q(intDX[23]),
.QN(n3592) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_20_ ( .D(n429), .CK(clk),
.RN(n3656), .Q(Add_Subt_result[20]), .QN(n3591) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_48_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[48]), .CK(clk), .RN(n3626),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[103]), .QN(n3590) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_41_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[41]), .CK(clk), .RN(n3622),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[96]), .QN(n3587) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_45_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[45]), .CK(clk), .RN(n3622),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[100]), .QN(n3584) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_54_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[54]), .CK(clk), .RN(n3650),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[109]), .QN(n3583) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_53_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[53]), .CK(clk), .RN(n3649),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[108]), .QN(n3579) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_52_ ( .D(n25), .CK(clk),
.RN(n3649), .Q(Sgf_normalized_result[52]), .QN(n3578) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_53_ ( .D(n18), .CK(clk),
.RN(n3649), .Q(Sgf_normalized_result[53]), .QN(n3577) );
DFFRX2TS XRegister_Q_reg_40_ ( .D(n384), .CK(clk), .RN(n3608), .Q(intDX[40]),
.QN(n3575) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_11_ ( .D(n420), .CK(clk),
.RN(n3651), .Q(Add_Subt_result[11]), .QN(n3574) );
DFFRX2TS XRegister_Q_reg_15_ ( .D(n359), .CK(clk), .RN(n3640), .Q(intDX[15]),
.QN(n3573) );
DFFRX1TS XRegister_Q_reg_9_ ( .D(n353), .CK(clk), .RN(n3638), .Q(intDX[9]),
.QN(n3571) );
DFFRX2TS XRegister_Q_reg_28_ ( .D(n372), .CK(clk), .RN(n3643), .Q(intDX[28]),
.QN(n3570) );
DFFRX2TS XRegister_Q_reg_20_ ( .D(n364), .CK(clk), .RN(n3641), .Q(intDX[20]),
.QN(n3569) );
DFFRX2TS XRegister_Q_reg_13_ ( .D(n357), .CK(clk), .RN(n3639), .Q(intDX[13]),
.QN(n3568) );
DFFRX2TS XRegister_Q_reg_12_ ( .D(n356), .CK(clk), .RN(n3639), .Q(intDX[12]),
.QN(n3567) );
DFFRX1TS XRegister_Q_reg_2_ ( .D(n346), .CK(clk), .RN(n3636), .Q(intDX[2]),
.QN(n3566) );
DFFRX2TS XRegister_Q_reg_29_ ( .D(n373), .CK(clk), .RN(n3644), .Q(intDX[29]),
.QN(n3565) );
DFFRX2TS XRegister_Q_reg_21_ ( .D(n365), .CK(clk), .RN(n3641), .Q(intDX[21]),
.QN(n3564) );
DFFRX1TS XRegister_Q_reg_4_ ( .D(n348), .CK(clk), .RN(n3636), .Q(intDX[4]),
.QN(n3563) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_12_ ( .D(n421), .CK(clk),
.RN(n3652), .Q(Add_Subt_result[12]), .QN(n3561) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_4_ ( .D(n413), .CK(clk),
.RN(n3651), .Q(Add_Subt_result[4]), .QN(n3559) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_50_ ( .D(n41), .CK(clk),
.RN(n3648), .Q(Sgf_normalized_result[50]), .QN(n3558) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_51_ ( .D(n33), .CK(clk),
.RN(n3649), .Q(Sgf_normalized_result[51]), .QN(n3557) );
DFFRX2TS XRegister_Q_reg_39_ ( .D(n383), .CK(clk), .RN(n3608), .Q(intDX[39]),
.QN(n3556) );
DFFRX2TS XRegister_Q_reg_24_ ( .D(n368), .CK(clk), .RN(n3642), .Q(intDX[24]),
.QN(n3555) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_22_ ( .D(n431), .CK(clk),
.RN(n3652), .Q(Add_Subt_result[22]), .QN(n3554) );
DFFRX2TS XRegister_Q_reg_25_ ( .D(n369), .CK(clk), .RN(n3643), .Q(intDX[25]),
.QN(n3553) );
DFFRX2TS XRegister_Q_reg_17_ ( .D(n361), .CK(clk), .RN(n3640), .Q(intDX[17]),
.QN(n3552) );
DFFRX2TS XRegister_Q_reg_31_ ( .D(n375), .CK(clk), .RN(n3644), .Q(intDX[31]),
.QN(n3551) );
DFFRX2TS XRegister_Q_reg_18_ ( .D(n362), .CK(clk), .RN(n3640), .Q(intDX[18]),
.QN(n3550) );
DFFRX2TS XRegister_Q_reg_11_ ( .D(n355), .CK(clk), .RN(n3638), .Q(intDX[11]),
.QN(n3549) );
DFFRX1TS XRegister_Q_reg_38_ ( .D(n382), .CK(clk), .RN(n3634), .Q(intDX[38]),
.QN(n3548) );
DFFRX2TS XRegister_Q_reg_43_ ( .D(n387), .CK(clk), .RN(n3607), .QN(n3547) );
DFFRX2TS XRegister_Q_reg_51_ ( .D(n395), .CK(clk), .RN(n3607), .Q(intDX[51]),
.QN(n3546) );
DFFRX2TS XRegister_Q_reg_26_ ( .D(n370), .CK(clk), .RN(n3643), .Q(intDX[26]),
.QN(n3544) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_48_ ( .D(n57), .CK(clk),
.RN(n3648), .Q(Sgf_normalized_result[48]), .QN(n3543) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_49_ ( .D(n49), .CK(clk),
.RN(n3648), .Q(Sgf_normalized_result[49]), .QN(n3542) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_7_ ( .D(n416), .CK(clk),
.RN(n3635), .Q(Add_Subt_result[7]), .QN(n3541) );
DFFRX2TS XRegister_Q_reg_35_ ( .D(n379), .CK(clk), .RN(n3646), .Q(intDX[35]),
.QN(n3540) );
DFFRX2TS XRegister_Q_reg_8_ ( .D(n352), .CK(clk), .RN(n3637), .Q(intDX[8]),
.QN(n3539) );
DFFRX2TS XRegister_Q_reg_36_ ( .D(n380), .CK(clk), .RN(n3646), .Q(intDX[36]),
.QN(n3538) );
DFFRX2TS XRegister_Q_reg_33_ ( .D(n377), .CK(clk), .RN(n3645), .Q(intDX[33]),
.QN(n3537) );
DFFRX1TS XRegister_Q_reg_10_ ( .D(n354), .CK(clk), .RN(n3638), .Q(intDX[10]),
.QN(n3536) );
DFFRX1TS XRegister_Q_reg_37_ ( .D(n381), .CK(clk), .RN(n3646), .Q(intDX[37]),
.QN(n3535) );
DFFRX1TS XRegister_Q_reg_32_ ( .D(n376), .CK(clk), .RN(n3645), .Q(intDX[32]),
.QN(n3534) );
DFFRX1TS XRegister_Q_reg_16_ ( .D(n360), .CK(clk), .RN(n3640), .Q(intDX[16]),
.QN(n3533) );
DFFRX2TS XRegister_Q_reg_54_ ( .D(n398), .CK(clk), .RN(n3606), .Q(intDX[54]),
.QN(n3530) );
DFFRX2TS XRegister_Q_reg_52_ ( .D(n396), .CK(clk), .RN(n3607), .Q(intDX[52]),
.QN(n3529) );
DFFRX2TS XRegister_Q_reg_48_ ( .D(n392), .CK(clk), .RN(n3607), .Q(intDX[48]),
.QN(n3528) );
DFFRX2TS XRegister_Q_reg_47_ ( .D(n391), .CK(clk), .RN(n3607), .Q(intDX[47]),
.QN(n3527) );
DFFRX2TS XRegister_Q_reg_45_ ( .D(n389), .CK(clk), .RN(n3607), .QN(n3526) );
DFFRX2TS XRegister_Q_reg_53_ ( .D(n397), .CK(clk), .RN(n3606), .QN(n3523) );
DFFRX2TS XRegister_Q_reg_49_ ( .D(n393), .CK(clk), .RN(n3607), .QN(n3522) );
DFFRX2TS XRegister_Q_reg_46_ ( .D(n390), .CK(clk), .RN(n3607), .Q(intDX[46]),
.QN(n3521) );
DFFRX2TS XRegister_Q_reg_41_ ( .D(n385), .CK(clk), .RN(n3608), .Q(intDX[41]),
.QN(n3520) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_31_ ( .D(n73), .CK(clk),
.RN(n3644), .Q(Sgf_normalized_result[31]), .QN(n3517) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n75), .CK(clk),
.RN(n3641), .Q(Sgf_normalized_result[23]), .QN(n3516) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n16), .CK(clk),
.RN(n3641), .Q(Sgf_normalized_result[22]), .QN(n3515) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n22), .CK(clk),
.RN(n3641), .Q(Sgf_normalized_result[21]), .QN(n3514) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n29), .CK(clk),
.RN(n3640), .Q(Sgf_normalized_result[20]), .QN(n3513) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n37), .CK(clk),
.RN(n3640), .Q(Sgf_normalized_result[19]), .QN(n3512) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n45), .CK(clk),
.RN(n3640), .Q(Sgf_normalized_result[18]), .QN(n3511) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n53), .CK(clk),
.RN(n3639), .Q(Sgf_normalized_result[17]), .QN(n3510) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n91), .CK(clk),
.RN(n3638), .Q(Sgf_normalized_result[13]), .QN(n3509) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n99), .CK(clk),
.RN(n3638), .Q(Sgf_normalized_result[12]), .QN(n3508) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n103), .CK(clk),
.RN(n3638), .Q(Sgf_normalized_result[11]), .QN(n3507) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n95), .CK(clk),
.RN(n3637), .Q(Sgf_normalized_result[10]), .QN(n3506) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n87), .CK(clk), .RN(
n3637), .Q(Sgf_normalized_result[9]), .QN(n3505) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n79), .CK(clk), .RN(
n3637), .Q(Sgf_normalized_result[8]), .QN(n3504) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n71), .CK(clk), .RN(
n3636), .Q(Sgf_normalized_result[7]), .QN(n3503) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n63), .CK(clk), .RN(
n3636), .Q(Sgf_normalized_result[6]), .QN(n3502) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_42_ ( .D(n97), .CK(clk),
.RN(n3647), .Q(Sgf_normalized_result[42]), .QN(n3499) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_41_ ( .D(n89), .CK(clk),
.RN(n3646), .Q(Sgf_normalized_result[41]), .QN(n3498) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_43_ ( .D(n101), .CK(clk),
.RN(n3647), .Q(Sgf_normalized_result[43]), .QN(n3496) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_44_ ( .D(n93), .CK(clk),
.RN(n3647), .Q(Sgf_normalized_result[44]), .QN(n3495) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_45_ ( .D(n85), .CK(clk),
.RN(n3647), .Q(Sgf_normalized_result[45]), .QN(n3494) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_47_ ( .D(n65), .CK(clk),
.RN(n3648), .Q(Sgf_normalized_result[47]), .QN(n3492) );
DFFRX2TS YRegister_Q_reg_23_ ( .D(n224), .CK(clk), .RN(n3642), .Q(intDY[23]),
.QN(n3491) );
DFFRX2TS YRegister_Q_reg_16_ ( .D(n203), .CK(clk), .RN(n3616), .Q(intDY[16]),
.QN(n3488) );
DFFRX2TS YRegister_Q_reg_6_ ( .D(n173), .CK(clk), .RN(n3618), .Q(intDY[6]),
.QN(n3487) );
DFFRX2TS YRegister_Q_reg_5_ ( .D(n170), .CK(clk), .RN(n3618), .Q(intDY[5]),
.QN(n3483) );
DFFRX2TS YRegister_Q_reg_38_ ( .D(n269), .CK(clk), .RN(n3612), .Q(intDY[38]),
.QN(n3480) );
DFFRX2TS YRegister_Q_reg_52_ ( .D(n311), .CK(clk), .RN(n3609), .Q(intDY[52]),
.QN(n3479) );
DFFRX2TS YRegister_Q_reg_48_ ( .D(n299), .CK(clk), .RN(n3610), .Q(intDY[48]),
.QN(n3478) );
DFFRX2TS YRegister_Q_reg_44_ ( .D(n287), .CK(clk), .RN(n3611), .Q(intDY[44]),
.QN(n3477) );
DFFRX2TS YRegister_Q_reg_10_ ( .D(n185), .CK(clk), .RN(n3617), .Q(intDY[10]),
.QN(n3476) );
DFFRX1TS XRegister_Q_reg_0_ ( .D(n344), .CK(clk), .RN(n3635), .Q(intDX[0]),
.QN(n3471) );
DFFRX2TS XRegister_Q_reg_22_ ( .D(n366), .CK(clk), .RN(n3642), .Q(intDX[22]),
.QN(n3470) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_3_ ( .D(n412), .CK(clk),
.RN(n3651), .Q(Add_Subt_result[3]), .QN(n3468) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_6_ ( .D(n415), .CK(clk),
.RN(n3651), .Q(Add_Subt_result[6]), .QN(n3467) );
DFFRX1TS XRegister_Q_reg_6_ ( .D(n350), .CK(clk), .RN(n3637), .Q(intDX[6]),
.QN(n3466) );
DFFRX1TS XRegister_Q_reg_7_ ( .D(n351), .CK(clk), .RN(n3637), .Q(intDX[7]),
.QN(n3465) );
DFFRX1TS YRegister_Q_reg_24_ ( .D(n227), .CK(clk), .RN(n3615), .Q(intDY[24]),
.QN(n3464) );
DFFRX2TS XRegister_Q_reg_30_ ( .D(n374), .CK(clk), .RN(n3644), .Q(intDX[30]),
.QN(n3463) );
DFFRX2TS XRegister_Q_reg_19_ ( .D(n363), .CK(clk), .RN(n3641), .Q(intDX[19]),
.QN(n3462) );
DFFRX1TS XRegister_Q_reg_5_ ( .D(n349), .CK(clk), .RN(n3637), .Q(intDX[5]),
.QN(n3461) );
DFFRX2TS XRegister_Q_reg_34_ ( .D(n378), .CK(clk), .RN(n3645), .Q(intDX[34]),
.QN(n3460) );
DFFRX2TS XRegister_Q_reg_50_ ( .D(n394), .CK(clk), .RN(n3607), .QN(n3459) );
DFFRX2TS XRegister_Q_reg_42_ ( .D(n386), .CK(clk), .RN(n3608), .Q(intDX[42]),
.QN(n3458) );
DFFRX2TS XRegister_Q_reg_55_ ( .D(n399), .CK(clk), .RN(n3606), .QN(n3455) );
DFFRX2TS XRegister_Q_reg_44_ ( .D(n388), .CK(clk), .RN(n3607), .Q(intDX[44]),
.QN(n3454) );
DFFRX2TS XRegister_Q_reg_27_ ( .D(n371), .CK(clk), .RN(n3643), .Q(intDX[27]),
.QN(n3453) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_27_ ( .D(n436), .CK(clk),
.RN(n3653), .Q(Add_Subt_result[27]), .QN(n3452) );
DFFRX2TS YRegister_Q_reg_7_ ( .D(n176), .CK(clk), .RN(n3618), .Q(intDY[7]),
.QN(n3451) );
DFFRX2TS YRegister_Q_reg_4_ ( .D(n167), .CK(clk), .RN(n3618), .Q(intDY[4]),
.QN(n3449) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_46_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[46]), .CK(clk), .RN(n3620),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[101]), .QN(n3588) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_47_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[47]), .CK(clk), .RN(n3620),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[102]), .QN(n3593) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_63_ ( .D(n129),
.CK(clk), .RN(n3624), .Q(final_result_ieee[63]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n114),
.CK(clk), .RN(n3628), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n112),
.CK(clk), .RN(n3628), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n110),
.CK(clk), .RN(n3629), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n108),
.CK(clk), .RN(n3628), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n106),
.CK(clk), .RN(n3629), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n104),
.CK(clk), .RN(n3628), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n82),
.CK(clk), .RN(n3630), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_38_ ( .D(n80),
.CK(clk), .RN(n3627), .Q(final_result_ieee[38]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n68),
.CK(clk), .RN(n3630), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_37_ ( .D(n66),
.CK(clk), .RN(n3627), .Q(final_result_ieee[37]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n60),
.CK(clk), .RN(n3629), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_36_ ( .D(n58),
.CK(clk), .RN(n3627), .Q(final_result_ieee[36]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_35_ ( .D(n50),
.CK(clk), .RN(n3627), .Q(final_result_ieee[35]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_34_ ( .D(n42),
.CK(clk), .RN(n3627), .Q(final_result_ieee[34]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n38), .CK(
clk), .RN(n3631), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_33_ ( .D(n34),
.CK(clk), .RN(n3628), .Q(final_result_ieee[33]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n30), .CK(
clk), .RN(n3631), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_32_ ( .D(n26),
.CK(clk), .RN(n3628), .Q(final_result_ieee[32]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n19),
.CK(clk), .RN(n3628), .Q(final_result_ieee[31]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n13),
.CK(clk), .RN(n3628), .Q(final_result_ieee[30]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_41_ ( .D(n100),
.CK(clk), .RN(n3626), .Q(final_result_ieee[41]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_40_ ( .D(n96),
.CK(clk), .RN(n3626), .Q(final_result_ieee[40]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_42_ ( .D(n92),
.CK(clk), .RN(n3626), .Q(final_result_ieee[42]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_39_ ( .D(n88),
.CK(clk), .RN(n3626), .Q(final_result_ieee[39]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_43_ ( .D(n84),
.CK(clk), .RN(n3626), .Q(final_result_ieee[43]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_44_ ( .D(n76),
.CK(clk), .RN(n3626), .Q(final_result_ieee[44]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_45_ ( .D(n64),
.CK(clk), .RN(n3626), .Q(final_result_ieee[45]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_46_ ( .D(n56),
.CK(clk), .RN(n3626), .Q(final_result_ieee[46]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_47_ ( .D(n48),
.CK(clk), .RN(n3627), .Q(final_result_ieee[47]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_48_ ( .D(n40),
.CK(clk), .RN(n3627), .Q(final_result_ieee[48]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_49_ ( .D(n32),
.CK(clk), .RN(n3627), .Q(final_result_ieee[49]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_50_ ( .D(n24),
.CK(clk), .RN(n3627), .Q(final_result_ieee[50]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_51_ ( .D(n17),
.CK(clk), .RN(n3627), .Q(final_result_ieee[51]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n116),
.CK(clk), .RN(n3628), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_53_ ( .D(n127),
.CK(clk), .RN(n3625), .Q(final_result_ieee[53]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_56_ ( .D(n124),
.CK(clk), .RN(n3625), .Q(final_result_ieee[56]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_58_ ( .D(n122),
.CK(clk), .RN(n3625), .Q(final_result_ieee[58]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_59_ ( .D(n121),
.CK(clk), .RN(n3625), .Q(final_result_ieee[59]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_60_ ( .D(n120),
.CK(clk), .RN(n3625), .Q(final_result_ieee[60]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_61_ ( .D(n119),
.CK(clk), .RN(n3625), .Q(final_result_ieee[61]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_62_ ( .D(n118),
.CK(clk), .RN(n3626), .Q(final_result_ieee[62]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n102),
.CK(clk), .RN(n3630), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n98),
.CK(clk), .RN(n3630), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n94), .CK(
clk), .RN(n3630), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n90),
.CK(clk), .RN(n3630), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n86), .CK(
clk), .RN(n3630), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n78), .CK(
clk), .RN(n3630), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n74),
.CK(clk), .RN(n3629), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n72),
.CK(clk), .RN(n3628), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n70), .CK(
clk), .RN(n3630), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n62), .CK(
clk), .RN(n3630), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n54), .CK(
clk), .RN(n3631), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n52),
.CK(clk), .RN(n3629), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n46), .CK(
clk), .RN(n3631), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n44),
.CK(clk), .RN(n3629), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n36),
.CK(clk), .RN(n3629), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n28),
.CK(clk), .RN(n3629), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n21),
.CK(clk), .RN(n3629), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n15),
.CK(clk), .RN(n3629), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_52_ ( .D(n128),
.CK(clk), .RN(n3625), .Q(final_result_ieee[52]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_54_ ( .D(n126),
.CK(clk), .RN(n3625), .Q(final_result_ieee[54]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_55_ ( .D(n125),
.CK(clk), .RN(n3625), .Q(final_result_ieee[55]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_57_ ( .D(n123),
.CK(clk), .RN(n3625), .Q(final_result_ieee[57]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_42_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[42]), .CK(clk), .RN(n3620),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[97]), .QN(n3586) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_44_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[44]), .CK(clk), .RN(n3622),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[99]), .QN(n3585) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_50_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[50]), .CK(clk), .RN(n3648),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[105]), .QN(n3582) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_52_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[52]), .CK(clk), .RN(n3649),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[107]), .QN(n3581) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_49_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[49]), .CK(clk), .RN(n3648),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[104]), .QN(n3580) );
DFFRXLTS XRegister_Q_reg_58_ ( .D(n402), .CK(clk), .RN(n3606), .Q(intDX[58]),
.QN(n3457) );
DFFRXLTS XRegister_Q_reg_57_ ( .D(n401), .CK(clk), .RN(n3606), .Q(intDX[57]),
.QN(n3531) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_41_ ( .D(n450), .CK(clk),
.RN(n3654), .Q(Add_Subt_result[41]), .QN(n3484) );
DFFRX2TS YRegister_Q_reg_1_ ( .D(n158), .CK(clk), .RN(n3619), .Q(intDY[1]),
.QN(n3474) );
DFFRX2TS XRegister_Q_reg_56_ ( .D(n400), .CK(clk), .RN(n3606), .Q(intDX[56]),
.QN(n3456) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n55), .CK(clk), .RN(
n3636), .Q(Sgf_normalized_result[5]), .QN(n3501) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n47), .CK(clk), .RN(
n3635), .Q(Sgf_normalized_result[4]), .QN(n3500) );
DFFRX1TS XRegister_Q_reg_1_ ( .D(n345), .CK(clk), .RN(n3635), .Q(intDX[1]),
.QN(n3562) );
DFFRX2TS XRegister_Q_reg_14_ ( .D(n358), .CK(clk), .RN(n3639), .Q(intDX[14]),
.QN(n3469) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_28_ ( .D(n437), .CK(clk),
.RN(n3653), .Q(Add_Subt_result[28]), .QN(n3589) );
DFFRX2TS YRegister_Q_reg_3_ ( .D(n164), .CK(clk), .RN(n3619), .Q(intDY[3])
);
DFFRX2TS YRegister_Q_reg_39_ ( .D(n272), .CK(clk), .RN(n3612), .Q(intDY[39])
);
DFFRX2TS YRegister_Q_reg_15_ ( .D(n200), .CK(clk), .RN(n3616), .Q(intDY[15])
);
DFFRX2TS YRegister_Q_reg_41_ ( .D(n278), .CK(clk), .RN(n3611), .Q(intDY[41])
);
DFFRX2TS YRegister_Q_reg_33_ ( .D(n254), .CK(clk), .RN(n3613), .Q(intDY[33])
);
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_44_ ( .D(n453), .CK(clk),
.RN(n3655), .Q(Add_Subt_result[44]), .QN(n3485) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_32_ ( .D(n441), .CK(clk),
.RN(n3654), .Q(Add_Subt_result[32]), .QN(n3600) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_14_ ( .D(n423), .CK(clk),
.RN(n3652), .Q(Add_Subt_result[14]), .QN(n3576) );
DFFRX2TS FS_Module_state_reg_reg_1_ ( .D(n468), .CK(clk), .RN(n3634), .Q(
FS_Module_state_reg[1]), .QN(n1363) );
DFFRX2TS YRegister_Q_reg_53_ ( .D(n314), .CK(clk), .RN(n3609), .Q(intDY[53])
);
DFFRX2TS YRegister_Q_reg_55_ ( .D(n320), .CK(clk), .RN(n3609), .Q(intDY[55])
);
DFFRX2TS YRegister_Q_reg_31_ ( .D(n248), .CK(clk), .RN(n3613), .Q(intDY[31])
);
DFFRX2TS YRegister_Q_reg_13_ ( .D(n194), .CK(clk), .RN(n3617), .Q(intDY[13])
);
DFFRX2TS YRegister_Q_reg_43_ ( .D(n284), .CK(clk), .RN(n3611), .Q(intDY[43])
);
DFFRX2TS YRegister_Q_reg_29_ ( .D(n242), .CK(clk), .RN(n3614), .Q(intDY[29])
);
DFFRX2TS YRegister_Q_reg_35_ ( .D(n260), .CK(clk), .RN(n3612), .Q(intDY[35])
);
DFFRX2TS YRegister_Q_reg_21_ ( .D(n218), .CK(clk), .RN(n3615), .Q(intDY[21])
);
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_5_ ( .D(n414), .CK(clk),
.RN(n3651), .Q(Add_Subt_result[5]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_23_ ( .D(n432), .CK(clk),
.RN(n3653), .Q(Add_Subt_result[23]) );
DFFRX2TS YRegister_Q_reg_11_ ( .D(n188), .CK(clk), .RN(n3617), .Q(intDY[11])
);
DFFRX2TS YRegister_Q_reg_49_ ( .D(n302), .CK(clk), .RN(n3610), .Q(intDY[49])
);
DFFRX2TS YRegister_Q_reg_57_ ( .D(n326), .CK(clk), .RN(n3609), .Q(intDY[57])
);
DFFRX2TS YRegister_Q_reg_45_ ( .D(n290), .CK(clk), .RN(n3610), .Q(intDY[45])
);
DFFRX2TS YRegister_Q_reg_17_ ( .D(n206), .CK(clk), .RN(n3616), .Q(intDY[17])
);
DFFRX2TS YRegister_Q_reg_25_ ( .D(n230), .CK(clk), .RN(n3614), .Q(intDY[25])
);
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_26_ ( .D(n435), .CK(clk),
.RN(n3653), .Q(Add_Subt_result[26]), .QN(n3490) );
DFFRX2TS YRegister_Q_reg_14_ ( .D(n197), .CK(clk), .RN(n3616), .Q(intDY[14])
);
DFFRX2TS YRegister_Q_reg_46_ ( .D(n293), .CK(clk), .RN(n3610), .Q(intDY[46])
);
DFFRX2TS YRegister_Q_reg_12_ ( .D(n191), .CK(clk), .RN(n3617), .Q(intDY[12])
);
DFFRX2TS YRegister_Q_reg_58_ ( .D(n329), .CK(clk), .RN(n3608), .Q(intDY[58])
);
DFFRX2TS YRegister_Q_reg_36_ ( .D(n263), .CK(clk), .RN(n3612), .Q(intDY[36])
);
DFFRX2TS YRegister_Q_reg_18_ ( .D(n209), .CK(clk), .RN(n3616), .Q(intDY[18])
);
DFFRX2TS YRegister_Q_reg_27_ ( .D(n236), .CK(clk), .RN(n3614), .Q(intDY[27])
);
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_10_ ( .D(n419), .CK(clk),
.RN(n3651), .Q(Add_Subt_result[10]) );
DFFRX2TS YRegister_Q_reg_9_ ( .D(n182), .CK(clk), .RN(n3617), .Q(intDY[9])
);
DFFRX2TS YRegister_Q_reg_40_ ( .D(n275), .CK(clk), .RN(n3611), .Q(intDY[40])
);
DFFRX2TS YRegister_Q_reg_2_ ( .D(n161), .CK(clk), .RN(n3619), .Q(intDY[2])
);
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_2_ ( .D(n411), .CK(clk),
.RN(n3650), .Q(Add_Subt_result[2]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_25_ ( .D(n434), .CK(clk),
.RN(n3653), .Q(Add_Subt_result[25]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_15_ ( .D(n424), .CK(clk),
.RN(n3652), .Q(Add_Subt_result[15]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_37_ ( .D(n446), .CK(clk),
.RN(n3653), .Q(Add_Subt_result[37]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_13_ ( .D(n422), .CK(clk),
.RN(n3652), .Q(Add_Subt_result[13]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_17_ ( .D(n426), .CK(clk),
.RN(n3652), .Q(Add_Subt_result[17]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_19_ ( .D(n428), .CK(clk),
.RN(n3652), .Q(Add_Subt_result[19]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_16_ ( .D(n425), .CK(clk),
.RN(n3652), .Q(Add_Subt_result[16]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_34_ ( .D(n443), .CK(clk),
.RN(n3654), .Q(Add_Subt_result[34]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_0_ ( .D(n409), .CK(clk),
.RN(n3656), .Q(Add_Subt_result[0]) );
DFFRX2TS Exp_Operation_Module_exp_result_Q_reg_0_ ( .D(n141), .CK(clk), .RN(
n3631), .Q(exp_oper_result[0]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_40_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[40]), .CK(clk), .RN(n3622),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[95]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_43_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[43]), .CK(clk), .RN(n3622),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[98]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_29_ ( .D(n438), .CK(clk),
.RN(n3653), .Q(Add_Subt_result[29]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_3_ ( .D(n144), .CK(clk), .RN(
n3650), .Q(exp_oper_result[3]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_5_ ( .D(n146), .CK(clk), .RN(
n3634), .Q(exp_oper_result[5]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_4_ ( .D(n145), .CK(clk), .RN(
n3650), .Q(exp_oper_result[4]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_25_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[25]), .CK(clk), .RN(n3624),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[80]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_28_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[28]), .CK(clk), .RN(n3623),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[83]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_29_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[29]), .CK(clk), .RN(n3623),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[84]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_26_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[26]), .CK(clk), .RN(n3620),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[81]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_30_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[30]), .CK(clk), .RN(n3620),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[85]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_31_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[31]), .CK(clk), .RN(n3623),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[86]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_32_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[32]), .CK(clk), .RN(n3623),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[87]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_35_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[35]), .CK(clk), .RN(n3623),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[90]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_2_ ( .D(n143), .CK(clk), .RN(
n3651), .Q(exp_oper_result[2]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_1_ ( .D(n142), .CK(clk), .RN(
n3650), .Q(exp_oper_result[1]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_33_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[33]), .CK(clk), .RN(n3623),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[88]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_36_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[36]), .CK(clk), .RN(n3623),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[91]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_37_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[37]), .CK(clk), .RN(n3623),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[92]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_34_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[34]), .CK(clk), .RN(n3620),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[89]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_38_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[38]), .CK(clk), .RN(n3620),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[93]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n39), .CK(clk), .RN(
n3635), .Q(Sgf_normalized_result[3]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n31), .CK(clk), .RN(
n3635), .Q(Sgf_normalized_result[2]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_30_ ( .D(n105), .CK(clk),
.RN(n3643), .Q(Sgf_normalized_result[30]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(n107), .CK(clk),
.RN(n3641), .Q(Sgf_normalized_result[24]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_29_ ( .D(n109), .CK(clk),
.RN(n3643), .Q(Sgf_normalized_result[29]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(n111), .CK(clk),
.RN(n3642), .Q(Sgf_normalized_result[25]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_28_ ( .D(n113), .CK(clk),
.RN(n3643), .Q(Sgf_normalized_result[28]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_26_ ( .D(n115), .CK(clk),
.RN(n3642), .Q(Sgf_normalized_result[26]) );
DFFRX1TS Exp_Operation_Module_Overflow_Q_reg_0_ ( .D(n139), .CK(clk), .RN(
n3619), .Q(overflow_flag) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n469), .CK(clk),
.RN(n3635), .Q(Sgf_normalized_result[0]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_33_ ( .D(n20), .CK(clk),
.RN(n3644), .Q(Sgf_normalized_result[33]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_34_ ( .D(n27), .CK(clk),
.RN(n3644), .Q(Sgf_normalized_result[34]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_36_ ( .D(n43), .CK(clk),
.RN(n3645), .Q(Sgf_normalized_result[36]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_37_ ( .D(n51), .CK(clk),
.RN(n3645), .Q(Sgf_normalized_result[37]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_38_ ( .D(n59), .CK(clk),
.RN(n3646), .Q(Sgf_normalized_result[38]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n61), .CK(clk),
.RN(n3639), .Q(Sgf_normalized_result[16]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n69), .CK(clk),
.RN(n3639), .Q(Sgf_normalized_result[15]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n83), .CK(clk),
.RN(n3638), .Q(Sgf_normalized_result[14]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_32_ ( .D(n14), .CK(clk),
.RN(n3644), .Q(Sgf_normalized_result[32]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_35_ ( .D(n35), .CK(clk),
.RN(n3645), .Q(Sgf_normalized_result[35]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_40_ ( .D(n81), .CK(clk),
.RN(n3646), .Q(Sgf_normalized_result[40]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_27_ ( .D(n117), .CK(clk),
.RN(n3642), .Q(Sgf_normalized_result[27]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_35_ ( .D(n444), .CK(clk),
.RN(n3654), .Q(Add_Subt_result[35]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_23_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[23]), .CK(clk), .RN(n3624),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[78]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_10_ ( .D(n140), .CK(clk),
.RN(n3634), .Q(exp_oper_result[10]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_6_ ( .D(n147), .CK(clk), .RN(
n3633), .Q(exp_oper_result[6]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_7_ ( .D(n148), .CK(clk), .RN(
n3633), .Q(exp_oper_result[7]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_8_ ( .D(n149), .CK(clk), .RN(
n3633), .Q(exp_oper_result[8]) );
DFFRX1TS Exp_Operation_Module_exp_result_Q_reg_9_ ( .D(n150), .CK(clk), .RN(
n3633), .Q(exp_oper_result[9]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_54_ ( .D(n12), .CK(clk),
.RN(n3650), .Q(Sgf_normalized_result[54]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_39_ ( .D(n448), .CK(clk),
.RN(n3654), .Q(Add_Subt_result[39]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_31_ ( .D(n440), .CK(clk),
.RN(n3653), .Q(Add_Subt_result[31]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_39_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[39]), .CK(clk), .RN(n3623),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[94]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_8_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[8]), .CK(clk), .RN(n3621),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[63]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_11_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[11]), .CK(clk), .RN(n3621),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[66]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_19_ ( .D(n211), .CK(clk), .RN(
n3616), .Q(DmP[19]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_20_ ( .D(n214), .CK(clk), .RN(
n3615), .Q(DmP[20]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_22_ ( .D(n220), .CK(clk), .RN(
n3615), .Q(DmP[22]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_24_ ( .D(n226), .CK(clk), .RN(
n3615), .Q(DmP[24]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_28_ ( .D(n238), .CK(clk), .RN(
n3614), .Q(DmP[28]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_30_ ( .D(n244), .CK(clk), .RN(
n3613), .Q(DmP[30]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_32_ ( .D(n250), .CK(clk), .RN(
n3613), .Q(DmP[32]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_34_ ( .D(n256), .CK(clk), .RN(
n3613), .Q(DmP[34]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_38_ ( .D(n268), .CK(clk), .RN(
n3612), .Q(DmP[38]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_41_ ( .D(n277), .CK(clk), .RN(
n3611), .Q(DmP[41]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_44_ ( .D(n286), .CK(clk), .RN(
n3611), .Q(DmP[44]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_48_ ( .D(n298), .CK(clk), .RN(
n3610), .Q(DmP[48]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_3_ ( .D(n162), .CK(clk), .RN(
n3636), .Q(DMP[3]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_4_ ( .D(n165), .CK(clk), .RN(
n3636), .Q(DMP[4]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_5_ ( .D(n168), .CK(clk), .RN(
n3636), .Q(DMP[5]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_6_ ( .D(n171), .CK(clk), .RN(
n3637), .Q(DMP[6]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_7_ ( .D(n174), .CK(clk), .RN(
n3637), .Q(DMP[7]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_8_ ( .D(n177), .CK(clk), .RN(
n3637), .Q(DMP[8]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_10_ ( .D(n183), .CK(clk), .RN(
n3638), .Q(DMP[10]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_15_ ( .D(n198), .CK(clk), .RN(
n3639), .Q(DMP[15]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_16_ ( .D(n201), .CK(clk), .RN(
n3640), .Q(DMP[16]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_19_ ( .D(n210), .CK(clk), .RN(
n3641), .Q(DMP[19]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_20_ ( .D(n213), .CK(clk), .RN(
n3641), .Q(DMP[20]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_37_ ( .D(n264), .CK(clk), .RN(
n3646), .Q(DMP[37]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_39_ ( .D(n270), .CK(clk), .RN(
n3647), .Q(DMP[39]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_42_ ( .D(n279), .CK(clk), .RN(
n3647), .Q(DMP[42]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_44_ ( .D(n285), .CK(clk), .RN(
n3648), .Q(DMP[44]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_47_ ( .D(n294), .CK(clk), .RN(
n3648), .Q(DMP[47]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_48_ ( .D(n297), .CK(clk), .RN(
n3649), .Q(DMP[48]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_51_ ( .D(n306), .CK(clk), .RN(
n3649), .Q(DMP[51]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_51_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[51]), .CK(clk), .RN(n3649),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[106]), .QN(n1336) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_0_ ( .D(n154), .CK(clk), .RN(
n3619), .Q(DmP[0]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_1_ ( .D(n157), .CK(clk), .RN(
n3619), .Q(DmP[1]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_3_ ( .D(n163), .CK(clk), .RN(
n3619), .Q(DmP[3]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_4_ ( .D(n166), .CK(clk), .RN(
n3619), .Q(DmP[4]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_5_ ( .D(n169), .CK(clk), .RN(
n3618), .Q(DmP[5]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_6_ ( .D(n172), .CK(clk), .RN(
n3618), .Q(DmP[6]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_7_ ( .D(n175), .CK(clk), .RN(
n3618), .Q(DmP[7]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_8_ ( .D(n178), .CK(clk), .RN(
n3618), .Q(DmP[8]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_10_ ( .D(n184), .CK(clk), .RN(
n3617), .Q(DmP[10]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_16_ ( .D(n202), .CK(clk), .RN(
n3616), .Q(DmP[16]) );
DFFRX1TS Leading_Zero_Detector_Module_Output_Reg_Q_reg_4_ ( .D(n138), .CK(
clk), .RN(n3650), .Q(LZA_output[4]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_21_ ( .D(n430), .CK(clk),
.RN(n3652), .Q(Add_Subt_result[21]) );
DFFRX2TS YRegister_Q_reg_60_ ( .D(n335), .CK(clk), .RN(n3608), .Q(intDY[60])
);
DFFRX2TS YRegister_Q_reg_8_ ( .D(n179), .CK(clk), .RN(n3618), .Q(intDY[8])
);
DFFRX2TS YRegister_Q_reg_56_ ( .D(n323), .CK(clk), .RN(n3609), .Q(intDY[56])
);
DFFRX2TS YRegister_Q_reg_54_ ( .D(n317), .CK(clk), .RN(n3609), .Q(intDY[54])
);
DFFRX2TS YRegister_Q_reg_22_ ( .D(n221), .CK(clk), .RN(n3615), .Q(intDY[22])
);
DFFRX2TS YRegister_Q_reg_28_ ( .D(n239), .CK(clk), .RN(n3614), .Q(intDY[28])
);
DFFRX2TS YRegister_Q_reg_20_ ( .D(n215), .CK(clk), .RN(n3615), .Q(intDY[20])
);
DFFRX2TS YRegister_Q_reg_32_ ( .D(n251), .CK(clk), .RN(n3613), .Q(intDY[32])
);
DFFRX2TS YRegister_Q_reg_62_ ( .D(n341), .CK(clk), .RN(n3608), .Q(intDY[62])
);
DFFRX2TS YRegister_Q_reg_34_ ( .D(n257), .CK(clk), .RN(n3613), .Q(intDY[34])
);
DFFRX2TS YRegister_Q_reg_51_ ( .D(n308), .CK(clk), .RN(n3609), .Q(intDY[51])
);
DFFRX2TS YRegister_Q_reg_42_ ( .D(n281), .CK(clk), .RN(n3611), .Q(intDY[42])
);
DFFRX2TS YRegister_Q_reg_30_ ( .D(n245), .CK(clk), .RN(n3613), .Q(intDY[30])
);
DFFRX2TS YRegister_Q_reg_19_ ( .D(n212), .CK(clk), .RN(n3615), .Q(intDY[19])
);
DFFRX2TS YRegister_Q_reg_47_ ( .D(n296), .CK(clk), .RN(n3610), .Q(intDY[47])
);
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_8_ ( .D(n417), .CK(clk),
.RN(n3651), .Q(Add_Subt_result[8]) );
DFFRX2TS YRegister_Q_reg_26_ ( .D(n233), .CK(clk), .RN(n3614), .Q(intDY[26])
);
DFFRX2TS YRegister_Q_reg_0_ ( .D(n155), .CK(clk), .RN(n3619), .Q(intDY[0])
);
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_9_ ( .D(n418), .CK(clk),
.RN(n3651), .Q(Add_Subt_result[9]) );
DFFRX2TS YRegister_Q_reg_37_ ( .D(n266), .CK(clk), .RN(n3612), .Q(intDY[37]),
.QN(n1361) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_27_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[27]), .CK(clk), .RN(n3623),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[82]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_24_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[24]), .CK(clk), .RN(n3624),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[79]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_33_ ( .D(n442), .CK(clk),
.RN(n3654), .Q(Add_Subt_result[33]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_22_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[22]), .CK(clk), .RN(n3620),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[77]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_18_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[18]), .CK(clk), .RN(n3620),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[73]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_17_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[17]), .CK(clk), .RN(n3620),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[72]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_21_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[21]), .CK(clk), .RN(n3624),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[76]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_20_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[20]), .CK(clk), .RN(n3624),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[75]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_19_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[19]), .CK(clk), .RN(n3624),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[74]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_16_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[16]), .CK(clk), .RN(n3621),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[71]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_38_ ( .D(n447), .CK(clk),
.RN(n3653), .Q(Add_Subt_result[38]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_36_ ( .D(n445), .CK(clk),
.RN(n3654), .Q(Add_Subt_result[36]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_42_ ( .D(n451), .CK(clk),
.RN(n3655), .Q(Add_Subt_result[42]) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_30_ ( .D(n439), .CK(clk),
.RN(n3654), .Q(Add_Subt_result[30]) );
DFFRX1TS Exp_Operation_Module_Underflow_Q_reg_0_ ( .D(n130), .CK(clk), .RN(
n3624), .Q(underflow_flag), .QN(n3605) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_25_ ( .D(n229), .CK(clk), .RN(
n3614), .Q(DmP[25]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_15_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[15]), .CK(clk), .RN(n3621),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[70]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_14_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[14]), .CK(clk), .RN(n3621),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[69]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_13_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[13]), .CK(clk), .RN(n3621),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[68]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_12_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[12]), .CK(clk), .RN(n3621),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[67]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_10_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[10]), .CK(clk), .RN(n3621),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[65]) );
DFFRX1TS Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_9_ ( .D(
Barrel_Shifter_module_Mux_Array_Data_array[9]), .CK(clk), .RN(n3621),
.Q(Barrel_Shifter_module_Mux_Array_Data_array[64]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_50_ ( .D(n304), .CK(clk), .RN(
n3609), .Q(DmP[50]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_49_ ( .D(n301), .CK(clk), .RN(
n3610), .Q(DmP[49]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_47_ ( .D(n295), .CK(clk), .RN(
n3610), .Q(DmP[47]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_45_ ( .D(n289), .CK(clk), .RN(
n3610), .Q(DmP[45]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_43_ ( .D(n283), .CK(clk), .RN(
n3611), .Q(DmP[43]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_42_ ( .D(n280), .CK(clk), .RN(
n3611), .Q(DmP[42]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_40_ ( .D(n274), .CK(clk), .RN(
n3611), .Q(DmP[40]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_39_ ( .D(n271), .CK(clk), .RN(
n3612), .Q(DmP[39]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_37_ ( .D(n265), .CK(clk), .RN(
n3612), .Q(DmP[37]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_36_ ( .D(n262), .CK(clk), .RN(
n3612), .Q(DmP[36]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_35_ ( .D(n259), .CK(clk), .RN(
n3612), .Q(DmP[35]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_33_ ( .D(n253), .CK(clk), .RN(
n3613), .Q(DmP[33]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_31_ ( .D(n247), .CK(clk), .RN(
n3613), .Q(DmP[31]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_29_ ( .D(n241), .CK(clk), .RN(
n3614), .Q(DmP[29]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_27_ ( .D(n235), .CK(clk), .RN(
n3614), .Q(DmP[27]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_26_ ( .D(n232), .CK(clk), .RN(
n3614), .Q(DmP[26]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_23_ ( .D(n223), .CK(clk), .RN(
n3615), .Q(DmP[23]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_21_ ( .D(n217), .CK(clk), .RN(
n3615), .Q(DmP[21]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_18_ ( .D(n208), .CK(clk), .RN(
n3616), .Q(DmP[18]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_17_ ( .D(n205), .CK(clk), .RN(
n3616), .Q(DmP[17]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_62_ ( .D(n339), .CK(clk), .RN(
n3634), .Q(DMP[62]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_61_ ( .D(n336), .CK(clk), .RN(
n3634), .Q(DMP[61]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_60_ ( .D(n333), .CK(clk), .RN(
n3633), .Q(DMP[60]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_59_ ( .D(n330), .CK(clk), .RN(
n3633), .Q(DMP[59]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_58_ ( .D(n327), .CK(clk), .RN(
n3633), .Q(DMP[58]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_57_ ( .D(n324), .CK(clk), .RN(
n3633), .Q(DMP[57]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_56_ ( .D(n321), .CK(clk), .RN(
n3633), .Q(DMP[56]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_55_ ( .D(n318), .CK(clk), .RN(
n3633), .Q(DMP[55]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_54_ ( .D(n315), .CK(clk), .RN(
n3632), .Q(DMP[54]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_52_ ( .D(n309), .CK(clk), .RN(
n3632), .Q(DMP[52]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_50_ ( .D(n303), .CK(clk), .RN(
n3649), .Q(DMP[50]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_49_ ( .D(n300), .CK(clk), .RN(
n3649), .Q(DMP[49]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_46_ ( .D(n291), .CK(clk), .RN(
n3648), .Q(DMP[46]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_45_ ( .D(n288), .CK(clk), .RN(
n3648), .Q(DMP[45]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_43_ ( .D(n282), .CK(clk), .RN(
n3647), .Q(DMP[43]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_40_ ( .D(n273), .CK(clk), .RN(
n3647), .Q(DMP[40]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_38_ ( .D(n267), .CK(clk), .RN(
n3646), .Q(DMP[38]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_36_ ( .D(n261), .CK(clk), .RN(
n3646), .Q(DMP[36]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_35_ ( .D(n258), .CK(clk), .RN(
n3645), .Q(DMP[35]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_34_ ( .D(n255), .CK(clk), .RN(
n3645), .Q(DMP[34]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_33_ ( .D(n252), .CK(clk), .RN(
n3645), .Q(DMP[33]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_32_ ( .D(n249), .CK(clk), .RN(
n3645), .Q(DMP[32]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_31_ ( .D(n246), .CK(clk), .RN(
n3644), .Q(DMP[31]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_30_ ( .D(n243), .CK(clk), .RN(
n3644), .Q(DMP[30]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_29_ ( .D(n240), .CK(clk), .RN(
n3644), .Q(DMP[29]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_28_ ( .D(n237), .CK(clk), .RN(
n3643), .Q(DMP[28]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_27_ ( .D(n234), .CK(clk), .RN(
n3643), .Q(DMP[27]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_26_ ( .D(n231), .CK(clk), .RN(
n3643), .Q(DMP[26]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_25_ ( .D(n228), .CK(clk), .RN(
n3642), .Q(DMP[25]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_24_ ( .D(n225), .CK(clk), .RN(
n3642), .Q(DMP[24]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_23_ ( .D(n222), .CK(clk), .RN(
n3642), .Q(DMP[23]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_22_ ( .D(n219), .CK(clk), .RN(
n3642), .Q(DMP[22]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_21_ ( .D(n216), .CK(clk), .RN(
n3641), .Q(DMP[21]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_18_ ( .D(n207), .CK(clk), .RN(
n3640), .Q(DMP[18]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_17_ ( .D(n204), .CK(clk), .RN(
n3640), .Q(DMP[17]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_14_ ( .D(n195), .CK(clk), .RN(
n3639), .Q(DMP[14]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_13_ ( .D(n192), .CK(clk), .RN(
n3639), .Q(DMP[13]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_12_ ( .D(n189), .CK(clk), .RN(
n3639), .Q(DMP[12]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_11_ ( .D(n186), .CK(clk), .RN(
n3638), .Q(DMP[11]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_9_ ( .D(n180), .CK(clk), .RN(
n3638), .Q(DMP[9]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_2_ ( .D(n159), .CK(clk), .RN(
n3636), .Q(DMP[2]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_1_ ( .D(n156), .CK(clk), .RN(
n3635), .Q(DMP[1]) );
DFFRX1TS Oper_Start_in_module_MRegister_Q_reg_0_ ( .D(n153), .CK(clk), .RN(
n3635), .Q(DMP[0]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_15_ ( .D(n199), .CK(clk), .RN(
n3616), .Q(DmP[15]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_14_ ( .D(n196), .CK(clk), .RN(
n3617), .Q(DmP[14]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_13_ ( .D(n193), .CK(clk), .RN(
n3617), .Q(DmP[13]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_12_ ( .D(n190), .CK(clk), .RN(
n3617), .Q(DmP[12]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_11_ ( .D(n187), .CK(clk), .RN(
n3617), .Q(DmP[11]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_9_ ( .D(n181), .CK(clk), .RN(
n3618), .Q(DmP[9]) );
DFFRX1TS Oper_Start_in_module_mRegister_Q_reg_2_ ( .D(n160), .CK(clk), .RN(
n3619), .Q(DmP[2]) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(n467), .CK(clk), .RN(n3634), .Q(
FS_Module_state_reg[2]), .QN(n3448) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_48_ ( .D(n457), .CK(clk),
.RN(n3656), .Q(Add_Subt_result[48]), .QN(n3598) );
DFFRX1TS XRegister_Q_reg_63_ ( .D(n343), .CK(clk), .RN(n3656), .Q(intDX[63]),
.QN(n3486) );
DFFRX1TS YRegister_Q_reg_63_ ( .D(n152), .CK(clk), .RN(n3656), .Q(intDY[63])
);
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_40_ ( .D(n449), .CK(clk),
.RN(n3654), .Q(Add_Subt_result[40]), .QN(n3599) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_43_ ( .D(n452), .CK(clk),
.RN(n3654), .Q(Add_Subt_result[43]), .QN(n3597) );
DFFRX2TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_47_ ( .D(n456), .CK(clk),
.RN(n3655), .Q(Add_Subt_result[47]), .QN(n3595) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_18_ ( .D(n427), .CK(clk),
.RN(n3652), .Q(Add_Subt_result[18]), .QN(n3594) );
DFFRX1TS Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_24_ ( .D(n433), .CK(clk),
.RN(n3653), .Q(Add_Subt_result[24]), .QN(n3560) );
DFFRX2TS XRegister_Q_reg_59_ ( .D(n403), .CK(clk), .RN(n3606), .Q(intDX[59]),
.QN(n3545) );
DFFRX2TS XRegister_Q_reg_62_ ( .D(n406), .CK(clk), .RN(n3606), .Q(intDX[62]),
.QN(n3525) );
DFFRX2TS XRegister_Q_reg_61_ ( .D(n405), .CK(clk), .RN(n3606), .Q(intDX[61]),
.QN(n3524) );
DFFRX2TS Sel_C_Q_reg_0_ ( .D(n465), .CK(clk), .RN(n478), .Q(FSM_selector_C),
.QN(n3489) );
DFFRX2TS Sel_B_Q_reg_0_ ( .D(n132), .CK(clk), .RN(n478), .Q(
FSM_selector_B[0]), .QN(n3482) );
DFFRX2TS YRegister_Q_reg_61_ ( .D(n338), .CK(clk), .RN(n3608), .Q(intDY[61]),
.QN(n3473) );
DFFRXLTS XRegister_Q_reg_60_ ( .D(n404), .CK(clk), .RN(n3606), .Q(intDX[60]),
.QN(n3532) );
DFFRX2TS Sel_B_Q_reg_1_ ( .D(n131), .CK(clk), .RN(n478), .Q(
FSM_selector_B[1]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_39_ ( .D(n67), .CK(clk),
.RN(n3646), .Q(Sgf_normalized_result[39]) );
DFFRX2TS YRegister_Q_reg_50_ ( .D(n305), .CK(clk), .RN(n3609), .Q(intDY[50])
);
DFFRX2TS YRegister_Q_reg_59_ ( .D(n332), .CK(clk), .RN(n3608), .Q(intDY[59])
);
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_46_ ( .D(n77), .CK(clk),
.RN(n3647), .Q(Sgf_normalized_result[46]), .QN(n3493) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_41_ ( .D(n276), .CK(clk), .RN(
n3647), .Q(DMP[41]) );
DFFRXLTS Oper_Start_in_module_MRegister_Q_reg_53_ ( .D(n312), .CK(clk), .RN(
n3632), .Q(DMP[53]) );
DFFRX2TS ASRegister_Q_reg_0_ ( .D(n342), .CK(clk), .RN(n3656), .Q(intAS) );
DFFRX2TS XRegister_Q_reg_3_ ( .D(n347), .CK(clk), .RN(n3636), .Q(intDX[3]),
.QN(n3572) );
OAI21X2TS U1789 ( .A0(n1833), .A1(n3605), .B0(n1634), .Y(n130) );
OAI211X1TS U1790 ( .A0(n2356), .A1(n2074), .B0(n2013), .C0(n1358), .Y(n18)
);
OAI211X1TS U1791 ( .A0(n2364), .A1(n2074), .B0(n2073), .C0(n1358), .Y(n41)
);
OAI211X1TS U1792 ( .A0(n2359), .A1(n1338), .B0(n2007), .C0(n1358), .Y(n49)
);
AOI31X1TS U1793 ( .A0(n2159), .A1(n1357), .A2(n2374), .B0(n3422), .Y(n3125)
);
BUFX3TS U1794 ( .A(n3154), .Y(n1334) );
BUFX3TS U1795 ( .A(n2133), .Y(n1339) );
BUFX3TS U1796 ( .A(n2141), .Y(n2174) );
AOI211X2TS U1797 ( .A0(n1342), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[98]), .B0(n1869), .C0(n2325), .Y(n2372) );
BUFX4TS U1798 ( .A(n2141), .Y(n2275) );
OAI21X1TS U1799 ( .A0(n2737), .A1(n2705), .B0(n2704), .Y(n2722) );
OAI21X1TS U1800 ( .A0(n2801), .A1(n2800), .B0(n2799), .Y(n2814) );
INVX2TS U1801 ( .A(n1357), .Y(n2209) );
CLKBUFX2TS U1802 ( .A(n3441), .Y(n3446) );
INVX2TS U1803 ( .A(n1739), .Y(n3441) );
INVX2TS U1804 ( .A(n2160), .Y(n1357) );
CLKBUFX2TS U1805 ( .A(n3426), .Y(n3420) );
OAI21X1TS U1806 ( .A0(n3100), .A1(n2913), .B0(n2912), .Y(n2934) );
AOI21X1TS U1807 ( .A0(n2904), .A1(n2621), .B0(n2620), .Y(n2862) );
BUFX3TS U1808 ( .A(n2160), .Y(n2296) );
INVX2TS U1809 ( .A(n1742), .Y(n3426) );
OR3X2TS U1810 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[3]), .C(
n1719), .Y(n2160) );
INVX2TS U1811 ( .A(n1756), .Y(n1894) );
NOR2X4TS U1812 ( .A(n3170), .B(n2035), .Y(n2031) );
OAI2BB2XLTS U1813 ( .B0(n1453), .B1(n1452), .A0N(n1451), .A1N(n1450), .Y(
n1454) );
CMPR32X2TS U1814 ( .A(n1611), .B(n1610), .C(n1609), .CO(n1606), .S(n3063) );
NAND2X1TS U1815 ( .A(n1419), .B(n1418), .Y(n1433) );
NAND2X2TS U1816 ( .A(n1755), .B(n1754), .Y(n1859) );
OAI2BB2XLTS U1817 ( .B0(intDX[28]), .B1(n1420), .A0N(intDY[29]), .A1N(n3565),
.Y(n1430) );
OAI2BB2XLTS U1818 ( .B0(intDX[30]), .B1(n1427), .A0N(intDY[31]), .A1N(n3551),
.Y(n1428) );
NOR2X1TS U1819 ( .A(n3119), .B(n1833), .Y(n1834) );
NAND2X1TS U1820 ( .A(n1714), .B(n1740), .Y(n1858) );
CMPR32X2TS U1821 ( .A(n1605), .B(n1353), .C(n1603), .CO(n1600), .S(n1723) );
NOR2X1TS U1822 ( .A(FS_Module_state_reg[1]), .B(n3448), .Y(n1740) );
NAND2X1TS U1823 ( .A(n2768), .B(n2496), .Y(n2498) );
NAND2X1TS U1824 ( .A(n2914), .B(n2431), .Y(n2433) );
NAND2X1TS U1825 ( .A(n2702), .B(n2557), .Y(n2667) );
NAND2X1TS U1826 ( .A(n2941), .B(n2421), .Y(n2913) );
NOR2X1TS U1827 ( .A(n2823), .B(n2769), .Y(n2496) );
NOR2X1TS U1828 ( .A(n2843), .B(n2837), .Y(n2486) );
NOR2X1TS U1829 ( .A(n2918), .B(n2920), .Y(n2431) );
NOR2X1TS U1830 ( .A(n2884), .B(n2905), .Y(n2888) );
NOR2X1TS U1831 ( .A(n2878), .B(n2622), .Y(n2864) );
INVX4TS U1832 ( .A(n1362), .Y(n1849) );
OAI21X1TS U1833 ( .A0(n2817), .A1(n2830), .B0(n2818), .Y(n2767) );
OAI21X1TS U1834 ( .A0(n2755), .A1(n2781), .B0(n2756), .Y(n2798) );
OAI21X1TS U1835 ( .A0(n2850), .A1(n2857), .B0(n2851), .Y(n2835) );
NOR2X1TS U1836 ( .A(FS_Module_state_reg[1]), .B(FS_Module_state_reg[3]), .Y(
n1738) );
AO21X1TS U1837 ( .A0(DmP[52]), .A1(n3482), .B0(n1762), .Y(n1595) );
NAND2X1TS U1838 ( .A(n2551), .B(n2550), .Y(n2729) );
NOR2X1TS U1839 ( .A(n2541), .B(n2540), .Y(n2802) );
NOR2X1TS U1840 ( .A(n2531), .B(n2530), .Y(n2743) );
NAND2X1TS U1841 ( .A(n2391), .B(n2390), .Y(n2993) );
NAND2X1TS U1842 ( .A(n2549), .B(n2548), .Y(n2734) );
NOR2X1TS U1843 ( .A(n2563), .B(n2562), .Y(n2672) );
NOR2X1TS U1844 ( .A(n2553), .B(n2552), .Y(n2706) );
NOR2X1TS U1845 ( .A(n2423), .B(n2422), .Y(n2932) );
NOR2X1TS U1846 ( .A(n2417), .B(n2416), .Y(n2945) );
NOR2X1TS U1847 ( .A(n2549), .B(n2548), .Y(n2725) );
NOR2X2TS U1848 ( .A(n2551), .B(n2550), .Y(n2728) );
XOR2X1TS U1849 ( .A(n2439), .B(n2407), .Y(n2423) );
INVX4TS U1850 ( .A(n2606), .Y(n2525) );
CLKINVX6TS U1851 ( .A(n2606), .Y(n2439) );
CLKINVX6TS U1852 ( .A(n2606), .Y(n2403) );
OAI21XLTS U1853 ( .A0(intDY[3]), .A1(n3572), .B0(intDY[2]), .Y(n1374) );
NOR2XLTS U1854 ( .A(n1401), .B(intDX[16]), .Y(n1402) );
OAI21XLTS U1855 ( .A0(intDY[23]), .A1(n3592), .B0(intDY[22]), .Y(n1408) );
OAI21XLTS U1856 ( .A0(intDY[43]), .A1(n3547), .B0(intDY[42]), .Y(n1461) );
NOR2XLTS U1857 ( .A(n1421), .B(intDX[24]), .Y(n1422) );
OAI21XLTS U1858 ( .A0(intDY[53]), .A1(n3523), .B0(intDY[52]), .Y(n1489) );
OAI21XLTS U1859 ( .A0(n2674), .A1(n2680), .B0(n2675), .Y(n2566) );
OAI21XLTS U1860 ( .A0(n2804), .A1(n2811), .B0(n2805), .Y(n2544) );
NOR2XLTS U1861 ( .A(n2516), .B(n3511), .Y(n2440) );
NOR2XLTS U1862 ( .A(n1491), .B(n1490), .Y(n1504) );
OAI211XLTS U1863 ( .A0(intDX[61]), .A1(n3473), .B0(n1449), .C0(n1448), .Y(
n1450) );
NOR2XLTS U1864 ( .A(n2516), .B(n3510), .Y(n2438) );
CLKINVX3TS U1865 ( .A(n3518), .Y(n2505) );
INVX2TS U1866 ( .A(n3109), .Y(n3010) );
INVX2TS U1867 ( .A(n2998), .Y(n3134) );
NAND2X1TS U1868 ( .A(n1433), .B(n1432), .Y(n1456) );
OAI21XLTS U1869 ( .A0(n2330), .A1(n3579), .B0(n2088), .Y(n2089) );
NAND3X1TS U1870 ( .A(n3073), .B(n1527), .C(n3490), .Y(n1550) );
NOR2XLTS U1871 ( .A(n3450), .B(n1719), .Y(n1720) );
AND2X2TS U1872 ( .A(n1844), .B(n1843), .Y(n1853) );
AND2X2TS U1873 ( .A(n1841), .B(n1840), .Y(n1854) );
NAND2X1TS U1874 ( .A(n2423), .B(n2422), .Y(n2953) );
NAND2X1TS U1875 ( .A(n3519), .B(FS_Module_state_reg[2]), .Y(n1753) );
NOR2XLTS U1876 ( .A(n3042), .B(n3043), .Y(n3040) );
OAI21XLTS U1877 ( .A0(n2816), .A1(n2829), .B0(n2830), .Y(n2821) );
NOR2X1TS U1878 ( .A(n3092), .B(n1859), .Y(n2122) );
NAND2BX2TS U1879 ( .AN(n1728), .B(n1633), .Y(n1634) );
CLKINVX3TS U1880 ( .A(n2220), .Y(n2243) );
CLKINVX3TS U1881 ( .A(n1787), .Y(n2114) );
INVX2TS U1882 ( .A(n2122), .Y(n1902) );
OAI21XLTS U1883 ( .A0(n3566), .A1(n2256), .B0(n2167), .Y(n160) );
OAI21XLTS U1884 ( .A0(n3568), .A1(n2298), .B0(n2149), .Y(n193) );
OAI21XLTS U1885 ( .A0(n2273), .A1(n3592), .B0(n2208), .Y(n222) );
OAI21XLTS U1886 ( .A0(n3547), .A1(n2243), .B0(n2242), .Y(n282) );
OAI21XLTS U1887 ( .A0(n3524), .A1(n2239), .B0(n2231), .Y(n336) );
OAI21XLTS U1888 ( .A0(n3575), .A1(n2295), .B0(n2282), .Y(n274) );
OAI21XLTS U1889 ( .A0(n3533), .A1(n2298), .B0(n2248), .Y(n202) );
OAI21XLTS U1890 ( .A0(n3471), .A1(n2256), .B0(n2255), .Y(n154) );
OAI21XLTS U1891 ( .A0(n3528), .A1(n2279), .B0(n2274), .Y(n298) );
OAI21XLTS U1892 ( .A0(n3470), .A1(n2305), .B0(n2286), .Y(n220) );
OAI211XLTS U1893 ( .A0(n1985), .A1(n3240), .B0(n1969), .C0(n1968), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[23]) );
OAI211XLTS U1894 ( .A0(n3256), .A1(n1945), .B0(n1944), .C0(n1943), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[26]) );
OAI211XLTS U1895 ( .A0(n1761), .A1(n3086), .B0(n1936), .C0(n1935), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[49]) );
OAI211XLTS U1896 ( .A0(n2334), .A1(n1902), .B0(n1964), .C0(n1358), .Y(n89)
);
OAI21XLTS U1897 ( .A0(n3529), .A1(n2279), .B0(n2246), .Y(n310) );
INVX4TS U1898 ( .A(FSM_selector_D), .Y(n2596) );
OAI211X1TS U1899 ( .A0(n3061), .A1(n3104), .B0(n3060), .C0(n3059), .Y(n3062)
);
OAI211X1TS U1900 ( .A0(n3004), .A1(n3134), .B0(n3003), .C0(n3002), .Y(n3005)
);
XNOR2X1TS U1901 ( .A(n2773), .B(n2772), .Y(n2774) );
OAI21X1TS U1902 ( .A0(n3549), .A1(n2178), .B0(n2146), .Y(n187) );
OAI21X1TS U1903 ( .A0(n2062), .A1(n1344), .B0(n2058), .Y(n107) );
OAI21X1TS U1904 ( .A0(n2096), .A1(n1344), .B0(n2091), .Y(n109) );
OAI21X1TS U1905 ( .A0(n2062), .A1(n2367), .B0(n2061), .Y(n105) );
OAI21X1TS U1906 ( .A0(n2096), .A1(n2371), .B0(n2095), .Y(n111) );
OAI21X1TS U1907 ( .A0(n2081), .A1(n1344), .B0(n2080), .Y(n113) );
OAI21X1TS U1908 ( .A0(n2084), .A1(n1344), .B0(n2083), .Y(n115) );
INVX4TS U1909 ( .A(n2220), .Y(n2239) );
INVX4TS U1910 ( .A(n2211), .Y(n2218) );
OAI21X1TS U1911 ( .A0(n3539), .A1(n2178), .B0(n2147), .Y(n178) );
INVX4TS U1912 ( .A(n2211), .Y(n2235) );
INVX2TS U1913 ( .A(n2369), .Y(n2370) );
INVX4TS U1914 ( .A(n2211), .Y(n2237) );
BUFX4TS U1915 ( .A(n2211), .Y(n2279) );
AOI211X1TS U1916 ( .A0(n2094), .A1(Sgf_normalized_result[30]), .B0(n2060),
.C0(n2133), .Y(n2061) );
AOI211X1TS U1917 ( .A0(n2094), .A1(Sgf_normalized_result[29]), .B0(n2090),
.C0(n1339), .Y(n2091) );
AOI211X1TS U1918 ( .A0(n2094), .A1(Sgf_normalized_result[25]), .B0(n2093),
.C0(n1339), .Y(n2095) );
AOI211X1TS U1919 ( .A0(n2094), .A1(Sgf_normalized_result[24]), .B0(n2057),
.C0(n1339), .Y(n2058) );
AOI211X1TS U1920 ( .A0(n2094), .A1(Sgf_normalized_result[28]), .B0(n2079),
.C0(n1339), .Y(n2080) );
INVX4TS U1921 ( .A(n2178), .Y(n2197) );
AOI211X1TS U1922 ( .A0(n2094), .A1(Sgf_normalized_result[26]), .B0(n2082),
.C0(n2133), .Y(n2083) );
BUFX6TS U1923 ( .A(n2178), .Y(n2211) );
INVX4TS U1924 ( .A(n2178), .Y(n2207) );
AOI2BB2X1TS U1925 ( .B0(n3092), .B1(Sgf_normalized_result[2]), .A0N(n3091),
.A1N(n1350), .Y(n3093) );
OAI21X1TS U1926 ( .A0(n2330), .A1(n1336), .B0(n1874), .Y(n1875) );
NAND4X1TS U1927 ( .A(n3266), .B(n3265), .C(n3264), .D(n3263), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[18]) );
NOR2BX4TS U1928 ( .AN(n1511), .B(n1510), .Y(n1512) );
NAND4X1TS U1929 ( .A(n3364), .B(n3363), .C(n3362), .D(n3361), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[4]) );
NAND4X1TS U1930 ( .A(n3344), .B(n3343), .C(n3342), .D(n3341), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[7]) );
NAND4X1TS U1931 ( .A(n3350), .B(n3349), .C(n3348), .D(n3347), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[6]) );
NAND4X1TS U1932 ( .A(n3324), .B(n3323), .C(n3322), .D(n3321), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[10]) );
NAND4X1TS U1933 ( .A(n3331), .B(n3330), .C(n3329), .D(n3328), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[9]) );
NAND4X1TS U1934 ( .A(n3385), .B(n3384), .C(n3383), .D(n3382), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[2]) );
NAND4X1TS U1935 ( .A(n3281), .B(n3280), .C(n3279), .D(n3278), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[16]) );
NAND4X1TS U1936 ( .A(n3393), .B(n3392), .C(n3391), .D(n3390), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[1]) );
NAND4X1TS U1937 ( .A(n3308), .B(n3307), .C(n3306), .D(n3305), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[12]) );
NAND4X1TS U1938 ( .A(n3337), .B(n3336), .C(n3335), .D(n3334), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[8]) );
NAND4X1TS U1939 ( .A(n3179), .B(n3178), .C(n3177), .D(n3176), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[47]) );
NAND4X1TS U1940 ( .A(n3358), .B(n3357), .C(n3356), .D(n3355), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[5]) );
NAND4X1TS U1941 ( .A(n3274), .B(n3273), .C(n3272), .D(n3271), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[17]) );
NAND4X1TS U1942 ( .A(n3190), .B(n3189), .C(n3188), .D(n3187), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[46]) );
NAND4X1TS U1943 ( .A(n3317), .B(n3316), .C(n3315), .D(n3314), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[11]) );
NAND4X1TS U1944 ( .A(n3287), .B(n3286), .C(n3285), .D(n3284), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[15]) );
NAND4X1TS U1945 ( .A(n3300), .B(n3299), .C(n3298), .D(n3297), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[13]) );
NAND4X1TS U1946 ( .A(n3415), .B(n3414), .C(n3413), .D(n3412), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[0]) );
NAND4X1TS U1947 ( .A(n3293), .B(n3292), .C(n3291), .D(n3290), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[14]) );
NAND4X1TS U1948 ( .A(n3245), .B(n3244), .C(n3243), .D(n3242), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[22]) );
NAND4X1TS U1949 ( .A(n3374), .B(n3373), .C(n3372), .D(n3371), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[3]) );
OAI21X1TS U1950 ( .A0(n2330), .A1(n3580), .B0(n2085), .Y(n2086) );
OAI21X1TS U1951 ( .A0(n2330), .A1(n3582), .B0(n2075), .Y(n2076) );
OAI21X1TS U1952 ( .A0(n2330), .A1(n3581), .B0(n2077), .Y(n2078) );
OAI21X1TS U1953 ( .A0(n2330), .A1(n3583), .B0(n2053), .Y(n2054) );
OAI21X1TS U1954 ( .A0(n2330), .A1(n3593), .B0(n2329), .Y(n2332) );
NOR2X1TS U1955 ( .A(Barrel_Shifter_module_Mux_Array_Data_array[94]), .B(
n1908), .Y(n1355) );
OAI21X1TS U1956 ( .A0(n3053), .A1(Add_Subt_result[34]), .B0(n3023), .Y(n3024) );
OAI21X1TS U1957 ( .A0(Add_Subt_result[29]), .A1(n3013), .B0(n1566), .Y(n1567) );
INVX3TS U1958 ( .A(n3165), .Y(n3407) );
INVX3TS U1959 ( .A(n3165), .Y(n3338) );
NAND2X2TS U1960 ( .A(n2132), .B(n2121), .Y(n1860) );
AND2X2TS U1961 ( .A(n3199), .B(n3256), .Y(n1934) );
AND2X2TS U1962 ( .A(n3210), .B(n2114), .Y(n3196) );
INVX3TS U1963 ( .A(n3276), .Y(n3370) );
INVX3TS U1964 ( .A(n3214), .Y(n3352) );
INVX4TS U1965 ( .A(n1902), .Y(n2132) );
OAI2BB1X1TS U1966 ( .A0N(n1399), .A1N(n1398), .B0(n1397), .Y(n1414) );
OAI21X1TS U1967 ( .A0(n2769), .A1(n2824), .B0(n2770), .Y(n2495) );
NOR2X2TS U1968 ( .A(n1879), .B(n1861), .Y(n1852) );
INVX4TS U1969 ( .A(n1772), .Y(n3199) );
INVX2TS U1970 ( .A(n2785), .Y(n2787) );
AND2X2TS U1971 ( .A(n3191), .B(n3256), .Y(n3268) );
OAI211X1TS U1972 ( .A0(n3121), .A1(n3118), .B0(n1743), .C0(n3437), .Y(n1744)
);
CLKXOR2X2TS U1973 ( .A(n2525), .B(n2514), .Y(n2551) );
NOR2X1TS U1974 ( .A(n1721), .B(n1720), .Y(n1722) );
OAI21X1TS U1975 ( .A0(n3121), .A1(n3118), .B0(n2596), .Y(n466) );
OAI2BB2XLTS U1976 ( .B0(n1391), .B1(n1390), .A0N(n1389), .A1N(n1388), .Y(
n1394) );
NAND2X4TS U1977 ( .A(n1859), .B(FSM_selector_C), .Y(n1756) );
NOR2X1TS U1978 ( .A(n3492), .B(n2583), .Y(n2524) );
AOI21X1TS U1979 ( .A0(n1387), .A1(n1386), .B0(n1390), .Y(n1389) );
INVX1TS U1980 ( .A(n1713), .Y(n1635) );
NOR2X1TS U1981 ( .A(n3133), .B(Add_Subt_result[36]), .Y(n1537) );
AOI211X1TS U1982 ( .A0(intDX[52]), .A1(n3479), .B0(n1434), .C0(n1490), .Y(
n1492) );
INVX4TS U1983 ( .A(n2596), .Y(n2516) );
AOI2BB2X1TS U1984 ( .B0(intDY[53]), .B1(n3523), .A0N(intDX[52]), .A1N(n1489),
.Y(n1491) );
NOR2X1TS U1985 ( .A(n1441), .B(intDX[56]), .Y(n1442) );
INVX2TS U1986 ( .A(n1362), .Y(n1842) );
NOR2X1TS U1987 ( .A(n1458), .B(intDX[44]), .Y(n1459) );
CLKINVX2TS U1988 ( .A(n1741), .Y(n1712) );
NAND2BX1TS U1989 ( .AN(intDY[21]), .B(intDX[21]), .Y(n1364) );
NOR2X1TS U1990 ( .A(Add_Subt_result[33]), .B(Add_Subt_result[34]), .Y(n1538)
);
NAND2BXLTS U1991 ( .AN(intDY[2]), .B(intDX[2]), .Y(n1373) );
OAI21X1TS U1992 ( .A0(intDY[55]), .A1(n3455), .B0(intDY[54]), .Y(n1500) );
INVX4TS U1993 ( .A(n3518), .Y(n2445) );
OAI21X1TS U1994 ( .A0(n3149), .A1(n3115), .B0(n3146), .Y(n3116) );
XOR2X2TS U1995 ( .A(n1596), .B(n1354), .Y(n1728) );
OAI21X1TS U1996 ( .A0(n2273), .A1(n3538), .B0(n2272), .Y(n261) );
OAI21X1TS U1997 ( .A0(n3520), .A1(n2243), .B0(n2240), .Y(n276) );
OAI21X1TS U1998 ( .A0(n2827), .A1(n2823), .B0(n2824), .Y(n2773) );
OAI21X1TS U1999 ( .A0(n3523), .A1(n2239), .B0(n1517), .Y(n312) );
OAI21X1TS U2000 ( .A0(n3456), .A1(n2243), .B0(n2225), .Y(n321) );
OAI21X1TS U2001 ( .A0(n2253), .A1(n2285), .B0(n2252), .Y(n328) );
OAI21X1TS U2002 ( .A0(n3551), .A1(n2305), .B0(n2293), .Y(n247) );
OAI21X1TS U2003 ( .A0(n3530), .A1(n2239), .B0(n2232), .Y(n315) );
OAI21X1TS U2004 ( .A0(n3528), .A1(n2216), .B0(n2210), .Y(n297) );
OAI21X1TS U2005 ( .A0(n3537), .A1(n2295), .B0(n2155), .Y(n253) );
OAI21X1TS U2006 ( .A0(n3458), .A1(n2243), .B0(n2226), .Y(n279) );
OAI21X1TS U2007 ( .A0(n3540), .A1(n2295), .B0(n2294), .Y(n259) );
OAI21X1TS U2008 ( .A0(n3444), .A1(n2239), .B0(n2234), .Y(n324) );
OAI21X1TS U2009 ( .A0(n3459), .A1(n2216), .B0(n2215), .Y(n303) );
OAI21X1TS U2010 ( .A0(n2253), .A1(n2243), .B0(n2224), .Y(n327) );
OAI21X1TS U2011 ( .A0(n3538), .A1(n2295), .B0(n2154), .Y(n262) );
OAI21X1TS U2012 ( .A0(n3522), .A1(n2216), .B0(n2214), .Y(n300) );
OAI21X1TS U2013 ( .A0(n3455), .A1(n2239), .B0(n1516), .Y(n318) );
OAI21X1TS U2014 ( .A0(n3456), .A1(n2285), .B0(n2249), .Y(n322) );
OAI21X1TS U2015 ( .A0(n3570), .A1(n2305), .B0(n2290), .Y(n238) );
OAI21X1TS U2016 ( .A0(n3565), .A1(n2305), .B0(n2301), .Y(n241) );
OAI21X1TS U2017 ( .A0(n3521), .A1(n2243), .B0(n2221), .Y(n291) );
OAI21X1TS U2018 ( .A0(n3524), .A1(n2256), .B0(n2247), .Y(n337) );
OAI21X1TS U2019 ( .A0(n3455), .A1(n2285), .B0(n2259), .Y(n319) );
OAI21X1TS U2020 ( .A0(n3535), .A1(n2295), .B0(n2158), .Y(n265) );
OAI21X1TS U2021 ( .A0(n3464), .A1(n2216), .B0(n2213), .Y(n226) );
OAI21X1TS U2022 ( .A0(n3556), .A1(n2295), .B0(n2152), .Y(n271) );
OAI21X1TS U2023 ( .A0(n3526), .A1(n2243), .B0(n2223), .Y(n288) );
OAI21X1TS U2024 ( .A0(n3527), .A1(n2243), .B0(n2222), .Y(n294) );
OAI21X1TS U2025 ( .A0(n3545), .A1(n2243), .B0(n2227), .Y(n330) );
OAI21X1TS U2026 ( .A0(n3529), .A1(n2239), .B0(n2236), .Y(n309) );
OAI21X1TS U2027 ( .A0(n3546), .A1(n2239), .B0(n2233), .Y(n306) );
OAI21X1TS U2028 ( .A0(n3454), .A1(n2243), .B0(n2228), .Y(n285) );
OAI21X1TS U2029 ( .A0(n3569), .A1(n2298), .B0(n2289), .Y(n214) );
OAI21X1TS U2030 ( .A0(n3530), .A1(n2285), .B0(n2250), .Y(n316) );
OAI21X1TS U2031 ( .A0(n2230), .A1(n2239), .B0(n2229), .Y(n333) );
OAI21X1TS U2032 ( .A0(n3564), .A1(n2298), .B0(n2297), .Y(n217) );
OAI21X1TS U2033 ( .A0(n3458), .A1(n2295), .B0(n2153), .Y(n280) );
OAI21X1TS U2034 ( .A0(n3463), .A1(n2305), .B0(n2280), .Y(n244) );
OAI21X1TS U2035 ( .A0(n3523), .A1(n2285), .B0(n2262), .Y(n313) );
OAI21X1TS U2036 ( .A0(n3552), .A1(n2298), .B0(n2288), .Y(n205) );
OAI21X1TS U2037 ( .A0(n3520), .A1(n2295), .B0(n2292), .Y(n277) );
OAI21X1TS U2038 ( .A0(n3544), .A1(n2305), .B0(n2277), .Y(n232) );
OAI21X1TS U2039 ( .A0(n3453), .A1(n2305), .B0(n2283), .Y(n235) );
OAI21X1TS U2040 ( .A0(n3491), .A1(n2216), .B0(n2212), .Y(n223) );
OAI21X1TS U2041 ( .A0(n3548), .A1(n2295), .B0(n2276), .Y(n268) );
OAI21X1TS U2042 ( .A0(n3534), .A1(n2305), .B0(n2304), .Y(n250) );
OAI21X1TS U2043 ( .A0(n3525), .A1(n2239), .B0(n2238), .Y(n339) );
OAI21X1TS U2044 ( .A0(n3527), .A1(n2279), .B0(n2278), .Y(n295) );
OAI21X1TS U2045 ( .A0(n3460), .A1(n2295), .B0(n2281), .Y(n256) );
OAI21X1TS U2046 ( .A0(n3573), .A1(n2298), .B0(n2258), .Y(n199) );
OAI21X1TS U2047 ( .A0(n2239), .A1(n3562), .B0(n2219), .Y(n156) );
OAI21X1TS U2048 ( .A0(n2204), .A1(n3571), .B0(n1513), .Y(n180) );
OAI21X1TS U2049 ( .A0(n3459), .A1(n2285), .B0(n2284), .Y(n304) );
OAI21X1TS U2050 ( .A0(n3553), .A1(n2305), .B0(n2287), .Y(n229) );
OAI21X1TS U2051 ( .A0(n3462), .A1(n2298), .B0(n2169), .Y(n211) );
OAI21X1TS U2052 ( .A0(n3545), .A1(n2285), .B0(n2142), .Y(n331) );
OAI21X1TS U2053 ( .A0(n3536), .A1(n2256), .B0(n2137), .Y(n184) );
OAI21X1TS U2054 ( .A0(n2204), .A1(n3469), .B0(n2182), .Y(n195) );
OAI21X1TS U2055 ( .A0(n3521), .A1(n2279), .B0(n2175), .Y(n292) );
OAI21X1TS U2056 ( .A0(n2204), .A1(n3568), .B0(n2185), .Y(n192) );
OAI21X1TS U2057 ( .A0(n2200), .A1(n3564), .B0(n2187), .Y(n216) );
INVX6TS U2058 ( .A(n2256), .Y(n2271) );
OAI21X1TS U2059 ( .A0(n3546), .A1(n2305), .B0(n2170), .Y(n307) );
OAI21X1TS U2060 ( .A0(n2204), .A1(n3549), .B0(n2190), .Y(n186) );
OAI21X1TS U2061 ( .A0(n3465), .A1(n2256), .B0(n2140), .Y(n175) );
OAI21X1TS U2062 ( .A0(n3466), .A1(n2256), .B0(n2139), .Y(n172) );
OAI21X1TS U2063 ( .A0(n3454), .A1(n2279), .B0(n2151), .Y(n286) );
OAI21X1TS U2064 ( .A0(n3469), .A1(n2298), .B0(n2145), .Y(n196) );
OAI21X1TS U2065 ( .A0(n3563), .A1(n2211), .B0(n2165), .Y(n166) );
OAI21X1TS U2066 ( .A0(n3567), .A1(n2298), .B0(n2148), .Y(n190) );
OAI21X1TS U2067 ( .A0(n3572), .A1(n2285), .B0(n2168), .Y(n163) );
OAI21X1TS U2068 ( .A0(n3525), .A1(n2256), .B0(n2166), .Y(n340) );
OAI21X1TS U2069 ( .A0(n2200), .A1(n3533), .B0(n2198), .Y(n201) );
OAI21X1TS U2070 ( .A0(n3562), .A1(n2285), .B0(n2164), .Y(n157) );
INVX3TS U2071 ( .A(n2687), .Y(n2717) );
OAI21X1TS U2072 ( .A0(n2200), .A1(n3462), .B0(n2179), .Y(n210) );
OAI21X1TS U2073 ( .A0(n3444), .A1(n2256), .B0(n2143), .Y(n325) );
OAI21X1TS U2074 ( .A0(n2230), .A1(n2256), .B0(n2144), .Y(n334) );
AOI21X1TS U2075 ( .A0(n2814), .A1(n2812), .B0(n2803), .Y(n2808) );
OAI21X1TS U2076 ( .A0(n3550), .A1(n2298), .B0(n2171), .Y(n208) );
OAI222X1TS U2077 ( .A0(n2356), .A1(n1349), .B0(n2367), .B1(n2355), .C0(n2361), .C1(n3497), .Y(n23) );
OAI21X1TS U2078 ( .A0(n2266), .A1(n3565), .B0(n2188), .Y(n240) );
OAI21X1TS U2079 ( .A0(n2266), .A1(n3544), .B0(n2177), .Y(n231) );
OAI21X1TS U2080 ( .A0(n3547), .A1(n2279), .B0(n2156), .Y(n283) );
OAI21X1TS U2081 ( .A0(n3526), .A1(n2279), .B0(n2172), .Y(n289) );
OAI21X1TS U2082 ( .A0(n2266), .A1(n3453), .B0(n2181), .Y(n234) );
OAI211X1TS U2083 ( .A0(n2345), .A1(n1337), .B0(n1994), .C0(n1359), .Y(n57)
);
OAI21X1TS U2084 ( .A0(n2273), .A1(n3570), .B0(n2206), .Y(n237) );
OAI211X1TS U2085 ( .A0(n2368), .A1(n1337), .B0(n2124), .C0(n2123), .Y(n14)
);
BUFX3TS U2086 ( .A(n2279), .Y(n2295) );
OAI21X1TS U2087 ( .A0(n3522), .A1(n2279), .B0(n2173), .Y(n301) );
OAI211X1TS U2088 ( .A0(n2372), .A1(n1337), .B0(n2136), .C0(n2135), .Y(n35)
);
OAI21X1TS U2089 ( .A0(n2200), .A1(n3573), .B0(n2192), .Y(n198) );
OAI21X1TS U2090 ( .A0(n2273), .A1(n3463), .B0(n2205), .Y(n243) );
OAI211X1TS U2091 ( .A0(n3091), .A1(n2074), .B0(n2067), .C0(n1359), .Y(n25)
);
OAI21X1TS U2092 ( .A0(n2266), .A1(n3569), .B0(n2183), .Y(n213) );
OAI211XLTS U2093 ( .A0(n2316), .A1(n1338), .B0(n1358), .C0(n1926), .Y(n85)
);
OAI211X1TS U2094 ( .A0(n2319), .A1(n1338), .B0(n1359), .C0(n1956), .Y(n77)
);
OAI211X1TS U2095 ( .A0(n2310), .A1(n1338), .B0(n1359), .C0(n1916), .Y(n101)
);
OAI211X1TS U2096 ( .A0(n2313), .A1(n1337), .B0(n1359), .C0(n1921), .Y(n93)
);
OAI211XLTS U2097 ( .A0(n2350), .A1(n1902), .B0(n2024), .C0(n1358), .Y(n20)
);
OAI211X1TS U2098 ( .A0(n2346), .A1(n1902), .B0(n2019), .C0(n1359), .Y(n27)
);
OAI211XLTS U2099 ( .A0(n2352), .A1(n1902), .B0(n2040), .C0(n1358), .Y(n43)
);
OAI211X1TS U2100 ( .A0(n2348), .A1(n1902), .B0(n2029), .C0(n1359), .Y(n51)
);
OAI211X1TS U2101 ( .A0(n2044), .A1(n1902), .B0(n2043), .C0(n1358), .Y(n59)
);
OAI21X1TS U2102 ( .A0(n2044), .A1(n2363), .B0(n2002), .Y(n61) );
OAI21X1TS U2103 ( .A0(n1335), .A1(n1350), .B0(n1988), .Y(n69) );
OAI211X1TS U2104 ( .A0(n1955), .A1(n1338), .B0(n1882), .C0(n1881), .Y(n81)
);
OAI21X1TS U2105 ( .A0(n1878), .A1(n2134), .B0(n1877), .Y(n117) );
OAI211X1TS U2106 ( .A0(n2336), .A1(n1344), .B0(n1960), .C0(n1359), .Y(n97)
);
OAI21X1TS U2107 ( .A0(n3571), .A1(n2285), .B0(n2150), .Y(n181) );
OAI21X1TS U2108 ( .A0(n2870), .A1(n2869), .B0(n2868), .Y(n2875) );
OAI211X1TS U2109 ( .A0(n2340), .A1(n1337), .B0(n1911), .C0(n1358), .Y(n65)
);
OAI211X1TS U2110 ( .A0(n1335), .A1(n1337), .B0(n1997), .C0(n1996), .Y(n67)
);
OAI21X1TS U2111 ( .A0(n1955), .A1(n1349), .B0(n1868), .Y(n83) );
INVX2TS U2112 ( .A(n2174), .Y(n2200) );
INVX2TS U2113 ( .A(n2174), .Y(n2266) );
INVX2TS U2114 ( .A(n2275), .Y(n2273) );
INVX2TS U2115 ( .A(n2174), .Y(n2204) );
OAI211X1TS U2116 ( .A0(n3217), .A1(n2114), .B0(n2105), .C0(n2104), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[42]) );
OAI211X1TS U2117 ( .A0(n3206), .A1(n2114), .B0(n2052), .C0(n2051), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[43]) );
OAI211X1TS U2118 ( .A0(n3198), .A1(n2114), .B0(n2113), .C0(n2112), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[44]) );
OAI211X1TS U2119 ( .A0(n2120), .A1(n2074), .B0(n1904), .C0(n1358), .Y(n12)
);
OAI211X1TS U2120 ( .A0(n2130), .A1(n2074), .B0(n1907), .C0(n1359), .Y(n33)
);
OAI211X1TS U2121 ( .A0(n3086), .A1(n3199), .B0(n1893), .C0(n1892), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[50]) );
OAI211X1TS U2122 ( .A0(n3170), .A1(n1839), .B0(n1838), .C0(n3086), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[52]) );
NAND3BX1TS U2123 ( .AN(n3252), .B(n3251), .C(n3250), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[21]) );
OAI21X1TS U2124 ( .A0(n2899), .A1(n2895), .B0(n2896), .Y(n2893) );
OAI21X1TS U2125 ( .A0(n2862), .A1(n2878), .B0(n2879), .Y(n2626) );
NAND3BX1TS U2126 ( .AN(n3260), .B(n3259), .C(n3258), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[20]) );
NAND3X1TS U2127 ( .A(n3086), .B(n3085), .C(n3084), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[51]) );
NOR2X1TS U2128 ( .A(n2092), .B(n1344), .Y(n2093) );
NOR2X1TS U2129 ( .A(n2084), .B(n2367), .Y(n2079) );
NOR2X1TS U2130 ( .A(n2092), .B(n2371), .Y(n2090) );
NOR2X1TS U2131 ( .A(n2059), .B(n2371), .Y(n2057) );
NOR2X1TS U2132 ( .A(n2081), .B(n2363), .Y(n2082) );
OAI211X1TS U2133 ( .A0(n3256), .A1(n1951), .B0(n1950), .C0(n1949), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[24]) );
NOR2X1TS U2134 ( .A(n2059), .B(n1344), .Y(n2060) );
AND2X4TS U2135 ( .A(n1512), .B(n1357), .Y(n2141) );
OAI211X1TS U2136 ( .A0(n3170), .A1(n1761), .B0(n1912), .C0(n3086), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[53]) );
OAI211X1TS U2137 ( .A0(n3256), .A1(n1900), .B0(n1899), .C0(n1898), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[25]) );
OR2X4TS U2138 ( .A(n1512), .B(n2296), .Y(n2178) );
NAND3X1TS U2139 ( .A(n3073), .B(Add_Subt_result[25]), .C(n3490), .Y(n3065)
);
NOR2X1TS U2140 ( .A(n2325), .B(n2009), .Y(n2010) );
INVX3TS U2141 ( .A(n3166), .Y(n3378) );
OAI21X1TS U2142 ( .A0(n3048), .A1(n3046), .B0(n1544), .Y(n1545) );
NOR2X1TS U2143 ( .A(n2325), .B(n2037), .Y(n2038) );
INVX3TS U2144 ( .A(n3166), .Y(n3326) );
NOR2X2TS U2145 ( .A(n2695), .B(n2696), .Y(n2575) );
OAI211X1TS U2146 ( .A0(n3256), .A1(n1886), .B0(n1885), .C0(n1884), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[27]) );
AOI21X2TS U2147 ( .A0(n1456), .A1(n1455), .B0(n1454), .Y(n1511) );
NOR2X1TS U2148 ( .A(n2325), .B(n2017), .Y(n2018) );
NOR2X1TS U2149 ( .A(n2325), .B(n2003), .Y(n2004) );
OAI21X1TS U2150 ( .A0(n2991), .A1(n2987), .B0(n2988), .Y(n2977) );
INVX3TS U2151 ( .A(n3160), .Y(n3401) );
INVX3TS U2152 ( .A(n3166), .Y(n3397) );
NOR2X1TS U2153 ( .A(n2325), .B(n1989), .Y(n1990) );
OAI21X1TS U2154 ( .A0(n3100), .A1(n3096), .B0(n3097), .Y(n2963) );
INVX3TS U2155 ( .A(n3160), .Y(n3387) );
INVX3TS U2156 ( .A(n3162), .Y(n3405) );
INVX2TS U2157 ( .A(n3257), .Y(n3399) );
INVX3TS U2158 ( .A(n3165), .Y(n3380) );
INVX3TS U2159 ( .A(n3162), .Y(n3379) );
OAI21X1TS U2160 ( .A0(n3590), .A1(n2330), .B0(n2055), .Y(n2056) );
INVX3TS U2161 ( .A(n3162), .Y(n3309) );
INVX3TS U2162 ( .A(n3214), .Y(n3411) );
NOR2X2TS U2163 ( .A(n2618), .B(n2476), .Y(n2762) );
INVX3TS U2164 ( .A(n3214), .Y(n3368) );
INVX3TS U2165 ( .A(n3214), .Y(n3253) );
INVX1TS U2166 ( .A(n2324), .Y(n2331) );
NOR2X1TS U2167 ( .A(n2913), .B(n2433), .Y(n2435) );
OAI21X2TS U2168 ( .A0(n2619), .A1(n2476), .B0(n2475), .Y(n2761) );
INVX3TS U2169 ( .A(n3276), .Y(n3270) );
NAND3X1TS U2170 ( .A(n3126), .B(n3125), .C(n3124), .Y(n464) );
OAI221X1TS U2171 ( .A0(n1509), .A1(n1508), .B0(n1507), .B1(n1506), .C0(n1505), .Y(n1510) );
INVX3TS U2172 ( .A(n3276), .Y(n3354) );
NAND2BX4TS U2173 ( .AN(n1853), .B(n1876), .Y(n1847) );
NAND2X1TS U2174 ( .A(n2972), .B(n2399), .Y(n2401) );
INVX3TS U2175 ( .A(n3276), .Y(n3408) );
OAI21X1TS U2176 ( .A0(n2871), .A1(n2868), .B0(n2872), .Y(n2473) );
INVX2TS U2177 ( .A(n2728), .Y(n2730) );
OAI21X1TS U2178 ( .A0(n2973), .A1(n2988), .B0(n2974), .Y(n2398) );
INVX2TS U2179 ( .A(n2889), .Y(n2891) );
INVX2TS U2180 ( .A(n2755), .Y(n2757) );
OAI21X1TS U2181 ( .A0(n2920), .A1(n2926), .B0(n2921), .Y(n2430) );
INVX2TS U2182 ( .A(n2920), .Y(n2922) );
INVX2TS U2183 ( .A(n2837), .Y(n2839) );
AOI211X1TS U2184 ( .A0(n3121), .A1(n3120), .B0(n2957), .C0(n3119), .Y(n3126)
);
NOR2X1TS U2185 ( .A(n1756), .B(n3598), .Y(n1817) );
OAI22X2TS U2186 ( .A0(n1756), .A1(Add_Subt_result[54]), .B0(
Add_Subt_result[0]), .B1(n1859), .Y(n3163) );
OR2X2TS U2187 ( .A(n1761), .B(n1937), .Y(n1824) );
AND2X2TS U2188 ( .A(n1761), .B(n1939), .Y(n2097) );
AOI211X1TS U2189 ( .A0(n1431), .A1(n1430), .B0(n1429), .C0(n1428), .Y(n1432)
);
INVX3TS U2190 ( .A(n3447), .Y(n3087) );
INVX3TS U2191 ( .A(n2361), .Y(n2134) );
OAI21X1TS U2192 ( .A0(n1468), .A1(n1467), .B0(n1466), .Y(n1470) );
INVX2TS U2193 ( .A(n3446), .Y(n3437) );
INVX3TS U2194 ( .A(n3446), .Y(n3090) );
INVX3TS U2195 ( .A(n3447), .Y(n3088) );
XOR2X1TS U2196 ( .A(n2403), .B(n2386), .Y(n2391) );
AND2X4TS U2197 ( .A(n1760), .B(n1759), .Y(n1761) );
INVX4TS U2198 ( .A(n2606), .Y(n2451) );
AOI222X1TS U2199 ( .A0(intDX[4]), .A1(n3449), .B0(intDX[5]), .B1(n3483),
.C0(n1376), .C1(n1375), .Y(n1378) );
NOR2X1TS U2200 ( .A(n2583), .B(n3517), .Y(n2503) );
INVX3TS U2201 ( .A(n2876), .Y(n3101) );
INVX3TS U2202 ( .A(n2876), .Y(n2809) );
INVX2TS U2203 ( .A(n1739), .Y(n3429) );
NOR2X1TS U2204 ( .A(n3543), .B(n2583), .Y(n2576) );
NOR2X1TS U2205 ( .A(n3542), .B(n2583), .Y(n2579) );
INVX2TS U2206 ( .A(n1390), .Y(n1368) );
NOR2X1TS U2207 ( .A(n3558), .B(n2583), .Y(n2584) );
NOR2X1TS U2208 ( .A(n2597), .B(n3504), .Y(n2404) );
INVX4TS U2209 ( .A(n3518), .Y(n2513) );
NOR2X1TS U2210 ( .A(n2583), .B(n3498), .Y(n2515) );
NOR4X1TS U2211 ( .A(n1654), .B(n1426), .C(n1417), .D(n1421), .Y(n1418) );
NOR2X1TS U2212 ( .A(n3577), .B(n2601), .Y(n2595) );
NOR2X1TS U2213 ( .A(n3578), .B(n2601), .Y(n2591) );
NOR2X1TS U2214 ( .A(n3557), .B(n2601), .Y(n2587) );
NAND2BX1TS U2215 ( .AN(Sgf_normalized_result[54]), .B(n2601), .Y(n2610) );
INVX3TS U2216 ( .A(n3518), .Y(n2602) );
NAND2X2TS U2217 ( .A(n1363), .B(n1574), .Y(n1713) );
OAI211X2TS U2218 ( .A0(intDY[28]), .A1(n3570), .B0(n1431), .C0(n1416), .Y(
n1426) );
OAI211X2TS U2219 ( .A0(intDY[12]), .A1(n3567), .B0(n1396), .C0(n1366), .Y(
n1390) );
NAND2BX1TS U2220 ( .AN(n1741), .B(n1740), .Y(n1742) );
NAND3X1TS U2221 ( .A(n2230), .B(n1447), .C(intDY[60]), .Y(n1448) );
OAI211X2TS U2222 ( .A0(intDY[20]), .A1(n3569), .B0(n1412), .C0(n1364), .Y(
n1406) );
NAND2X2TS U2223 ( .A(n1738), .B(n1737), .Y(n1739) );
INVX3TS U2224 ( .A(n2596), .Y(n1591) );
MX2X1TS U2225 ( .A(DMP[52]), .B(exp_oper_result[0]), .S0(n2445), .Y(n1605)
);
INVX3TS U2226 ( .A(n2596), .Y(n2601) );
NAND2X2TS U2227 ( .A(n1708), .B(n1738), .Y(n1857) );
NAND2BX1TS U2228 ( .AN(intDY[47]), .B(intDX[47]), .Y(n1457) );
NOR2X1TS U2229 ( .A(n3523), .B(intDY[53]), .Y(n1434) );
NOR2X1TS U2230 ( .A(n3450), .B(FS_Module_state_reg[2]), .Y(n1737) );
NAND2BX1TS U2231 ( .AN(intDX[62]), .B(intDY[62]), .Y(n1449) );
NAND2BX1TS U2232 ( .AN(intDY[29]), .B(intDX[29]), .Y(n1416) );
NAND2BX1TS U2233 ( .AN(intDY[40]), .B(intDX[40]), .Y(n1437) );
NAND2BX1TS U2234 ( .AN(intDY[41]), .B(intDX[41]), .Y(n1438) );
NAND2BX1TS U2235 ( .AN(intDY[32]), .B(intDX[32]), .Y(n1439) );
NAND2BX1TS U2236 ( .AN(intDY[19]), .B(intDX[19]), .Y(n1403) );
NAND2BX1TS U2237 ( .AN(intDY[51]), .B(intDX[51]), .Y(n1495) );
NAND2BX1TS U2238 ( .AN(intDY[59]), .B(intDX[59]), .Y(n1443) );
OAI21X1TS U2239 ( .A0(intDY[31]), .A1(n3551), .B0(intDY[30]), .Y(n1427) );
NAND2BX1TS U2240 ( .AN(intDY[62]), .B(intDX[62]), .Y(n1451) );
ADDFX2TS U2241 ( .A(n1628), .B(n1627), .CI(n1626), .CO(n1596), .S(n3127) );
CLKINVX3TS U2242 ( .A(n1604), .Y(n1354) );
OAI21X1TS U2243 ( .A0(n2847), .A1(n2843), .B0(n2844), .Y(n2841) );
OR2X2TS U2244 ( .A(FSM_selector_B[1]), .B(FSM_selector_B[0]), .Y(n1362) );
NOR2X1TS U2245 ( .A(n2537), .B(n2536), .Y(n2753) );
OA21X1TS U2246 ( .A0(n2031), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[106]), .B0(n2030), .Y(n1905) );
OA21X1TS U2247 ( .A0(n2031), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[109]), .B0(n2030), .Y(n1901) );
NOR3BX4TS U2248 ( .AN(n1632), .B(n3127), .C(n3128), .Y(n1633) );
CLKINVX12TS U2249 ( .A(n1604), .Y(n1353) );
NAND2X2TS U2250 ( .A(n2888), .B(n2464), .Y(n2618) );
NOR2X4TS U2251 ( .A(n1559), .B(n3133), .Y(n3052) );
NOR2X2TS U2252 ( .A(n2791), .B(n2785), .Y(n2739) );
OAI21X4TS U2253 ( .A0(n2694), .A1(n2696), .B0(n2697), .Y(n2574) );
NAND2X8TS U2254 ( .A(n2374), .B(n2596), .Y(n2606) );
CLKXOR2X2TS U2255 ( .A(n2518), .B(n2503), .Y(n2527) );
OAI21X2TS U2256 ( .A0(n2764), .A1(n2498), .B0(n2497), .Y(n2499) );
CLKMX2X2TS U2257 ( .A(Add_Subt_result[38]), .B(n2810), .S0(n2809), .Y(n447)
);
AOI21X2TS U2258 ( .A0(n2942), .A1(n2421), .B0(n2420), .Y(n2912) );
NAND2X2TS U2259 ( .A(n2662), .B(n2571), .Y(n2695) );
NOR2X4TS U2260 ( .A(n2667), .B(n2569), .Y(n2571) );
INVX2TS U2261 ( .A(n1580), .Y(n1604) );
OAI211X1TS U2262 ( .A0(intDY[60]), .A1(n3532), .B0(n1451), .C0(n1447), .Y(
n1453) );
OR3X1TS U2263 ( .A(n1854), .B(n1853), .C(n1879), .Y(n1873) );
MX2X1TS U2264 ( .A(DMP[60]), .B(exp_oper_result[8]), .S0(n1591), .Y(n1617)
);
CLKAND2X2TS U2265 ( .A(n1849), .B(DmP[60]), .Y(n1583) );
NAND4BXLTS U2266 ( .AN(n1724), .B(n3131), .C(n3117), .D(n3063), .Y(n1725) );
NAND4XLTS U2267 ( .A(n3083), .B(n3034), .C(n3045), .D(n3152), .Y(n1724) );
AOI211X2TS U2268 ( .A0(intDX[44]), .A1(n3477), .B0(n1458), .C0(n1467), .Y(
n1465) );
OAI211X1TS U2269 ( .A0(intDY[36]), .A1(n3538), .B0(n1483), .C0(n1472), .Y(
n1474) );
NAND3X1TS U2270 ( .A(n1492), .B(n1501), .C(n1436), .Y(n1509) );
NAND4X1TS U2271 ( .A(n1465), .B(n1463), .C(n1438), .D(n1437), .Y(n1507) );
INVX2TS U2272 ( .A(n1939), .Y(n1937) );
AOI21X2TS U2273 ( .A0(n2911), .A1(n2435), .B0(n2434), .Y(n2617) );
NOR2X1TS U2274 ( .A(n2456), .B(n2455), .Y(n2884) );
INVX2TS U2275 ( .A(n2097), .Y(n1772) );
NAND2X1TS U2276 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[3]),
.Y(n1741) );
MX2X1TS U2277 ( .A(DMP[19]), .B(Sgf_normalized_result[21]), .S0(n2445), .Y(
n2469) );
NAND2X2TS U2278 ( .A(n1851), .B(n1850), .Y(n1879) );
INVX2TS U2279 ( .A(n1772), .Y(n3209) );
INVX2TS U2280 ( .A(n1824), .Y(n3210) );
CLKBUFX2TS U2281 ( .A(n3237), .Y(n1787) );
NAND4XLTS U2282 ( .A(n1531), .B(n3106), .C(n1552), .D(n1530), .Y(n1532) );
NAND3BXLTS U2283 ( .AN(n3064), .B(n1549), .C(Add_Subt_result[7]), .Y(n3069)
);
INVX2TS U2284 ( .A(n2606), .Y(n2604) );
MX2X1TS U2285 ( .A(DMP[58]), .B(exp_oper_result[6]), .S0(n1591), .Y(n1623)
);
CLKAND2X2TS U2286 ( .A(n1849), .B(DmP[58]), .Y(n1585) );
MX2X1TS U2287 ( .A(DMP[61]), .B(exp_oper_result[9]), .S0(n1591), .Y(n1630)
);
CLKAND2X2TS U2288 ( .A(n1842), .B(DmP[61]), .Y(n1582) );
MX2X1TS U2289 ( .A(DMP[54]), .B(exp_oper_result[2]), .S0(n1591), .Y(n1598)
);
CLKAND2X2TS U2290 ( .A(n2602), .B(Sgf_normalized_result[1]), .Y(n2376) );
NOR2XLTS U2291 ( .A(FSM_selector_D), .B(n3497), .Y(n2375) );
NAND2BXLTS U2292 ( .AN(intDX[9]), .B(intDY[9]), .Y(n1386) );
INVX2TS U2293 ( .A(n1381), .Y(n1398) );
NOR2BX1TS U2294 ( .AN(n1368), .B(n1367), .Y(n1399) );
OAI211XLTS U2295 ( .A0(intDY[8]), .A1(n3539), .B0(n1385), .C0(n1388), .Y(
n1367) );
AOI211XLTS U2296 ( .A0(intDX[16]), .A1(n3488), .B0(n1401), .C0(n1407), .Y(
n1365) );
OAI2BB1X1TS U2297 ( .A0N(n1483), .A1N(n1482), .B0(n1481), .Y(n1488) );
NAND3XLTS U2298 ( .A(n3538), .B(n1472), .C(intDY[36]), .Y(n1473) );
OA21XLTS U2299 ( .A0(n1446), .A1(n1445), .B0(n1444), .Y(n1452) );
MX2X1TS U2300 ( .A(DMP[40]), .B(Sgf_normalized_result[42]), .S0(n2519), .Y(
n2554) );
MX2X1TS U2301 ( .A(DMP[34]), .B(Sgf_normalized_result[36]), .S0(n2519), .Y(
n2538) );
MX2X1TS U2302 ( .A(DMP[36]), .B(Sgf_normalized_result[38]), .S0(n2519), .Y(
n2542) );
MX2X1TS U2303 ( .A(DMP[31]), .B(Sgf_normalized_result[33]), .S0(n2519), .Y(
n2530) );
MX2X1TS U2304 ( .A(DMP[7]), .B(Sgf_normalized_result[9]), .S0(n2410), .Y(
n2416) );
NOR2XLTS U2305 ( .A(FSM_selector_D), .B(n3505), .Y(n2405) );
MX2X1TS U2306 ( .A(DMP[6]), .B(Sgf_normalized_result[8]), .S0(n2410), .Y(
n2414) );
MX2X1TS U2307 ( .A(DMP[37]), .B(Sgf_normalized_result[39]), .S0(n2519), .Y(
n2548) );
MX2X1TS U2308 ( .A(DMP[32]), .B(Sgf_normalized_result[34]), .S0(n2519), .Y(
n2532) );
NOR2XLTS U2309 ( .A(FSM_selector_D), .B(n3509), .Y(n2409) );
MX2X1TS U2310 ( .A(DMP[35]), .B(Sgf_normalized_result[37]), .S0(n2519), .Y(
n2540) );
MX2X1TS U2311 ( .A(DMP[13]), .B(Sgf_normalized_result[15]), .S0(n2445), .Y(
n2455) );
MX2X1TS U2312 ( .A(DMP[8]), .B(Sgf_normalized_result[10]), .S0(n2410), .Y(
n2418) );
NOR2XLTS U2313 ( .A(FSM_selector_D), .B(n3506), .Y(n2406) );
MX2X1TS U2314 ( .A(DMP[23]), .B(Sgf_normalized_result[25]), .S0(n2505), .Y(
n2481) );
MX2X1TS U2315 ( .A(DMP[24]), .B(Sgf_normalized_result[26]), .S0(n2505), .Y(
n2483) );
NOR2X1TS U2316 ( .A(n2856), .B(n2850), .Y(n2836) );
NOR2X1TS U2317 ( .A(n2427), .B(n2426), .Y(n2918) );
MX2X1TS U2318 ( .A(DMP[12]), .B(Sgf_normalized_result[14]), .S0(n2445), .Y(
n2428) );
MX2X1TS U2319 ( .A(DMP[42]), .B(Sgf_normalized_result[44]), .S0(n2592), .Y(
n2560) );
NAND2X1TS U2320 ( .A(n1876), .B(n1879), .Y(n2324) );
MX2X1TS U2321 ( .A(DMP[26]), .B(Sgf_normalized_result[28]), .S0(n2505), .Y(
n2489) );
MX2X1TS U2322 ( .A(DMP[39]), .B(Sgf_normalized_result[41]), .S0(n2519), .Y(
n2552) );
MX2X1TS U2323 ( .A(DMP[25]), .B(Sgf_normalized_result[27]), .S0(n2505), .Y(
n2487) );
MX2X1TS U2324 ( .A(DMP[1]), .B(Sgf_normalized_result[3]), .S0(n2602), .Y(
n2390) );
NOR2X1TS U2325 ( .A(n2987), .B(n2973), .Y(n2399) );
NOR2XLTS U2326 ( .A(FSM_selector_D), .B(n3503), .Y(n2402) );
MX2X1TS U2327 ( .A(DMP[20]), .B(Sgf_normalized_result[22]), .S0(n2445), .Y(
n2471) );
NOR2X1TS U2328 ( .A(n2391), .B(n2390), .Y(n2979) );
MX2X1TS U2329 ( .A(DMP[2]), .B(Sgf_normalized_result[4]), .S0(n2410), .Y(
n2392) );
NOR2XLTS U2330 ( .A(FSM_selector_D), .B(n3500), .Y(n2387) );
MX2X1TS U2331 ( .A(DMP[22]), .B(Sgf_normalized_result[24]), .S0(n2505), .Y(
n2479) );
MX2X1TS U2332 ( .A(DMP[10]), .B(Sgf_normalized_result[12]), .S0(n2410), .Y(
n2424) );
NOR3X1TS U2333 ( .A(FS_Module_state_reg[1]), .B(add_overflow_flag), .C(n3365), .Y(n1754) );
MX2X1TS U2334 ( .A(DMP[17]), .B(Sgf_normalized_result[19]), .S0(n2445), .Y(
n2465) );
MX2X1TS U2335 ( .A(DMP[18]), .B(Sgf_normalized_result[20]), .S0(n2445), .Y(
n2467) );
MX2X1TS U2336 ( .A(DMP[15]), .B(Sgf_normalized_result[17]), .S0(n2445), .Y(
n2459) );
MX2X1TS U2337 ( .A(DMP[16]), .B(Sgf_normalized_result[18]), .S0(n2445), .Y(
n2461) );
MX2X1TS U2338 ( .A(DMP[41]), .B(Sgf_normalized_result[43]), .S0(n2592), .Y(
n2558) );
MX2X1TS U2339 ( .A(DMP[38]), .B(Sgf_normalized_result[40]), .S0(n2519), .Y(
n2550) );
INVX2TS U2340 ( .A(n1859), .Y(n3394) );
MX2X1TS U2341 ( .A(DMP[43]), .B(Sgf_normalized_result[45]), .S0(n2592), .Y(
n2562) );
MX2X1TS U2342 ( .A(DMP[44]), .B(Sgf_normalized_result[46]), .S0(n2592), .Y(
n2564) );
MX2X1TS U2343 ( .A(DMP[46]), .B(Sgf_normalized_result[48]), .S0(n2592), .Y(
n2577) );
NOR2X1TS U2344 ( .A(n1345), .B(n2114), .Y(n1948) );
BUFX3TS U2345 ( .A(n2275), .Y(n2302) );
BUFX3TS U2346 ( .A(n2275), .Y(n2299) );
MX2X1TS U2347 ( .A(DMP[53]), .B(exp_oper_result[1]), .S0(n1591), .Y(n1601)
);
MX2X1TS U2348 ( .A(DMP[56]), .B(exp_oper_result[4]), .S0(n1591), .Y(n1610)
);
AND3X1TS U2349 ( .A(n2047), .B(n2046), .C(n2045), .Y(n3206) );
AND2X2TS U2350 ( .A(n1752), .B(n1751), .Y(n3237) );
CLKAND2X2TS U2351 ( .A(n2602), .B(Sgf_normalized_result[0]), .Y(n2380) );
AND3X1TS U2352 ( .A(n2108), .B(n2107), .C(n2106), .Y(n3198) );
AND3X1TS U2353 ( .A(n2100), .B(n2099), .C(n2098), .Y(n3217) );
AND3X1TS U2354 ( .A(n1804), .B(n1803), .C(n1802), .Y(n1974) );
INVX2TS U2355 ( .A(n3196), .Y(n3162) );
INVX2TS U2356 ( .A(n1948), .Y(n3165) );
INVX2TS U2357 ( .A(n1934), .Y(n3166) );
AO22XLTS U2358 ( .A0(n3395), .A1(Add_Subt_result[0]), .B0(
Add_Subt_result[54]), .B1(n3394), .Y(n3396) );
INVX2TS U2359 ( .A(n3318), .Y(n3312) );
INVX2TS U2360 ( .A(n3318), .Y(n3403) );
NAND3XLTS U2361 ( .A(n3132), .B(Add_Subt_result[17]), .C(n3594), .Y(n3144)
);
NAND3XLTS U2362 ( .A(n3109), .B(Add_Subt_result[13]), .C(n3576), .Y(n3103)
);
AO21XLTS U2363 ( .A0(n1526), .A1(n1551), .B0(Add_Subt_result[23]), .Y(n1547)
);
AOI2BB1XLTS U2364 ( .A0N(n3048), .A1N(n3025), .B0(n3024), .Y(n3026) );
OAI21XLTS U2365 ( .A0(n3597), .A1(n3066), .B0(n3065), .Y(n3067) );
OAI21XLTS U2366 ( .A0(Add_Subt_result[6]), .A1(Add_Subt_result[4]), .B0(
n3110), .Y(n3009) );
BUFX3TS U2367 ( .A(n2275), .Y(n2261) );
NAND4XLTS U2368 ( .A(n1659), .B(n1658), .C(n1657), .D(n1656), .Y(n1706) );
NAND4XLTS U2369 ( .A(n1667), .B(n1666), .C(n1665), .D(n1664), .Y(n1705) );
NAND4XLTS U2370 ( .A(n1651), .B(n1650), .C(n1649), .D(n1648), .Y(n1707) );
OR2X1TS U2371 ( .A(n2581), .B(n2580), .Y(n2635) );
OR2X1TS U2372 ( .A(n2589), .B(n2588), .Y(n2651) );
OR2X1TS U2373 ( .A(n2599), .B(n2598), .Y(n2646) );
NAND2X1TS U2374 ( .A(n1858), .B(n1710), .Y(n3119) );
MX2X1TS U2375 ( .A(Add_Subt_result[21]), .B(n2867), .S0(n3101), .Y(n430) );
MX2X1TS U2376 ( .A(Add_Subt_result[35]), .B(n2784), .S0(n1351), .Y(n444) );
OAI2BB1X2TS U2377 ( .A0N(n1729), .A1N(n1728), .B0(n1727), .Y(n139) );
NAND4BXLTS U2378 ( .AN(n1725), .B(n3128), .C(n3129), .D(n3130), .Y(n1726) );
MX2X1TS U2379 ( .A(Add_Subt_result[16]), .B(n2910), .S0(n2930), .Y(n425) );
MX2X1TS U2380 ( .A(Add_Subt_result[2]), .B(n3041), .S0(n2809), .Y(n411) );
MX2X1TS U2381 ( .A(Add_Subt_result[5]), .B(n2992), .S0(n3101), .Y(n414) );
MX2X1TS U2382 ( .A(Add_Subt_result[6]), .B(n2978), .S0(n2723), .Y(n415) );
MX2X1TS U2383 ( .A(Add_Subt_result[47]), .B(n2701), .S0(n3101), .Y(n456) );
OAI21XLTS U2384 ( .A0(n2795), .A1(n2695), .B0(n2694), .Y(n2700) );
AOI2BB2XLTS U2385 ( .B0(intDX[1]), .B1(n3474), .A0N(intDY[0]), .A1N(n1371),
.Y(n1372) );
NOR2XLTS U2386 ( .A(n1383), .B(intDX[10]), .Y(n1384) );
NAND2BXLTS U2387 ( .AN(intDY[9]), .B(intDX[9]), .Y(n1385) );
NAND2BXLTS U2388 ( .AN(intDY[13]), .B(intDX[13]), .Y(n1366) );
NOR2X1TS U2389 ( .A(n3526), .B(intDY[45]), .Y(n1458) );
AOI21X1TS U2390 ( .A0(intDX[38]), .A1(n3480), .B0(n1484), .Y(n1483) );
INVX2TS U2391 ( .A(n1474), .Y(n1480) );
NOR2XLTS U2392 ( .A(n1493), .B(intDX[48]), .Y(n1494) );
OAI2BB1X1TS U2393 ( .A0N(n1415), .A1N(n1414), .B0(n1413), .Y(n1419) );
NOR2BX1TS U2394 ( .AN(n1365), .B(n1406), .Y(n1415) );
NAND2BXLTS U2395 ( .AN(intDY[27]), .B(intDX[27]), .Y(n1423) );
NOR2BX1TS U2396 ( .AN(intDX[39]), .B(intDY[39]), .Y(n1484) );
CLKINVX3TS U2397 ( .A(n2606), .Y(n2518) );
NAND2X1TS U2398 ( .A(n1594), .B(n1593), .Y(n1762) );
NOR2X1TS U2399 ( .A(n2869), .B(n2871), .Y(n2474) );
NAND2X1TS U2400 ( .A(n2864), .B(n2474), .Y(n2476) );
NOR2X1TS U2401 ( .A(n2945), .B(n2947), .Y(n2421) );
NOR2X1TS U2402 ( .A(n2895), .B(n2889), .Y(n2464) );
INVX2TS U2403 ( .A(n2008), .Y(n1861) );
NAND2X2TS U2404 ( .A(n1543), .B(n3452), .Y(n1533) );
MX2X1TS U2405 ( .A(DMP[28]), .B(Sgf_normalized_result[30]), .S0(n2505), .Y(
n2493) );
MX2X1TS U2406 ( .A(DMP[33]), .B(Sgf_normalized_result[35]), .S0(n2519), .Y(
n2536) );
MX2X1TS U2407 ( .A(DmP[25]), .B(Add_Subt_result[27]), .S0(FSM_selector_C),
.Y(n1938) );
NOR2X1TS U2408 ( .A(n2829), .B(n2817), .Y(n2768) );
MX2X1TS U2409 ( .A(DMP[27]), .B(Sgf_normalized_result[29]), .S0(n2505), .Y(
n2491) );
MX2X1TS U2410 ( .A(DMP[14]), .B(Sgf_normalized_result[16]), .S0(n2445), .Y(
n2457) );
MX2X1TS U2411 ( .A(DMP[0]), .B(Sgf_normalized_result[2]), .S0(n2602), .Y(
n2382) );
NOR2X1TS U2412 ( .A(n3096), .B(n2959), .Y(n2941) );
NAND2X1TS U2413 ( .A(n2836), .B(n2486), .Y(n2763) );
OAI21X1TS U2414 ( .A0(n2728), .A1(n2734), .B0(n2729), .Y(n2703) );
MX2X1TS U2415 ( .A(DMP[3]), .B(Sgf_normalized_result[5]), .S0(n2410), .Y(
n2394) );
NOR2XLTS U2416 ( .A(FSM_selector_D), .B(n3501), .Y(n2388) );
MX2X1TS U2417 ( .A(DMP[4]), .B(Sgf_normalized_result[6]), .S0(n2410), .Y(
n2396) );
NOR2X1TS U2418 ( .A(n2979), .B(n2981), .Y(n2972) );
NOR2X1TS U2419 ( .A(n2672), .B(n2674), .Y(n2567) );
MX2X1TS U2420 ( .A(DMP[45]), .B(Sgf_normalized_result[47]), .S0(n2592), .Y(
n2572) );
OAI21X2TS U2421 ( .A0(n2751), .A1(n2547), .B0(n2546), .Y(n2663) );
NOR2X1TS U2422 ( .A(n2752), .B(n2547), .Y(n2662) );
BUFX3TS U2423 ( .A(n3489), .Y(n3365) );
OAI21XLTS U2424 ( .A0(Add_Subt_result[43]), .A1(Add_Subt_result[44]), .B0(
n1560), .Y(n1561) );
NAND2X2TS U2425 ( .A(n3109), .B(n3011), .Y(n1553) );
NOR2XLTS U2426 ( .A(n3133), .B(n1539), .Y(n1540) );
AOI2BB2XLTS U2427 ( .B0(n3075), .B1(Add_Subt_result[47]), .A0N(n3022), .A1N(
n3021), .Y(n3023) );
NAND4XLTS U2428 ( .A(n1703), .B(n1702), .C(n1701), .D(n1700), .Y(n1704) );
NOR2X1TS U2429 ( .A(n2685), .B(n2688), .Y(n2668) );
MX2X1TS U2430 ( .A(DMP[47]), .B(Sgf_normalized_result[49]), .S0(n2592), .Y(
n2580) );
MX2X1TS U2431 ( .A(DMP[48]), .B(Sgf_normalized_result[50]), .S0(n2592), .Y(
n2585) );
MX2X1TS U2432 ( .A(DMP[49]), .B(Sgf_normalized_result[51]), .S0(n2592), .Y(
n2588) );
MX2X1TS U2433 ( .A(DMP[50]), .B(Sgf_normalized_result[52]), .S0(n2592), .Y(
n2593) );
MX2X1TS U2434 ( .A(DMP[51]), .B(Sgf_normalized_result[53]), .S0(n2597), .Y(
n2598) );
NAND2X1TS U2435 ( .A(n1576), .B(n1575), .Y(n1833) );
ADDFHX2TS U2436 ( .A(n1621), .B(n1620), .CI(n1619), .CO(n1616), .S(n3130) );
MX2X1TS U2437 ( .A(DMP[59]), .B(exp_oper_result[7]), .S0(n1591), .Y(n1620)
);
CLKAND2X2TS U2438 ( .A(n1842), .B(DmP[59]), .Y(n1584) );
MX2X1TS U2439 ( .A(DMP[62]), .B(exp_oper_result[10]), .S0(n1591), .Y(n1627)
);
CLKAND2X2TS U2440 ( .A(n1849), .B(DmP[62]), .Y(n1581) );
AND3X1TS U2441 ( .A(n3213), .B(n3212), .C(n3211), .Y(n3236) );
AND3X1TS U2442 ( .A(n1786), .B(n1785), .C(n1784), .Y(n3221) );
AND3X1TS U2443 ( .A(n3203), .B(n3202), .C(n3201), .Y(n3230) );
AND3X1TS U2444 ( .A(n1769), .B(n1768), .C(n1767), .Y(n3229) );
AND3X1TS U2445 ( .A(n1794), .B(n1793), .C(n1792), .Y(n3234) );
MX2X1TS U2446 ( .A(DMP[57]), .B(exp_oper_result[5]), .S0(n1591), .Y(n1607)
);
ADDFHX2TS U2447 ( .A(n1614), .B(n1613), .CI(n1612), .CO(n1609), .S(n3083) );
MX2X1TS U2448 ( .A(DMP[55]), .B(exp_oper_result[3]), .S0(n1591), .Y(n1613)
);
XOR2X1TS U2449 ( .A(n1354), .B(n1588), .Y(n1614) );
AND3X1TS U2450 ( .A(n3195), .B(n3194), .C(n3193), .Y(n3225) );
CLKAND2X2TS U2451 ( .A(n1723), .B(n1340), .Y(n3152) );
INVX2TS U2452 ( .A(n2901), .Y(n2902) );
INVX2TS U2453 ( .A(n2905), .Y(n2907) );
OAI211X1TS U2454 ( .A0(n1335), .A1(n1954), .B0(n1910), .C0(n1909), .Y(n2338)
);
CLKINVX3TS U2455 ( .A(n3429), .Y(n3089) );
AND3X1TS U2456 ( .A(n1815), .B(n1814), .C(n1813), .Y(n3222) );
OAI211XLTS U2457 ( .A0(n3016), .A1(n3015), .B0(n3014), .C0(n3013), .Y(n3017)
);
MX2X1TS U2458 ( .A(Add_Subt_result[42]), .B(n2713), .S0(n2809), .Y(n451) );
MX2X1TS U2459 ( .A(Add_Subt_result[36]), .B(n2760), .S0(n2930), .Y(n445) );
MX2X1TS U2460 ( .A(Add_Subt_result[33]), .B(n2779), .S0(n1351), .Y(n442) );
AOI2BB2XLTS U2461 ( .B0(n1948), .B1(n3262), .A0N(n3255), .A1N(n1947), .Y(
n1949) );
AO22XLTS U2462 ( .A0(n3433), .A1(Data_Y[37]), .B0(n3434), .B1(intDY[37]),
.Y(n266) );
MX2X1TS U2463 ( .A(Add_Subt_result[9]), .B(n2969), .S0(n2930), .Y(n418) );
AO22XLTS U2464 ( .A0(n3435), .A1(Data_Y[0]), .B0(n3437), .B1(intDY[0]), .Y(
n155) );
AO22XLTS U2465 ( .A0(n3431), .A1(Data_Y[26]), .B0(n3427), .B1(intDY[26]),
.Y(n233) );
MX2X1TS U2466 ( .A(Add_Subt_result[8]), .B(n2964), .S0(n1351), .Y(n417) );
AO22XLTS U2467 ( .A0(n3435), .A1(Data_Y[47]), .B0(n3436), .B1(intDY[47]),
.Y(n296) );
AO22XLTS U2468 ( .A0(n3430), .A1(Data_Y[19]), .B0(n3427), .B1(intDY[19]),
.Y(n212) );
AO22XLTS U2469 ( .A0(n3431), .A1(Data_Y[30]), .B0(n3432), .B1(intDY[30]),
.Y(n245) );
AO22XLTS U2470 ( .A0(n3433), .A1(Data_Y[42]), .B0(n3434), .B1(intDY[42]),
.Y(n281) );
AO22XLTS U2471 ( .A0(n3435), .A1(Data_Y[51]), .B0(n3436), .B1(intDY[51]),
.Y(n308) );
AO22XLTS U2472 ( .A0(n3431), .A1(Data_Y[34]), .B0(n3432), .B1(intDY[34]),
.Y(n257) );
AO22XLTS U2473 ( .A0(n3438), .A1(Data_Y[62]), .B0(n3437), .B1(intDY[62]),
.Y(n341) );
AO22XLTS U2474 ( .A0(n3431), .A1(Data_Y[32]), .B0(n3432), .B1(intDY[32]),
.Y(n251) );
AO22XLTS U2475 ( .A0(n3430), .A1(Data_Y[20]), .B0(n3427), .B1(intDY[20]),
.Y(n215) );
AO22XLTS U2476 ( .A0(n3431), .A1(Data_Y[28]), .B0(n3432), .B1(intDY[28]),
.Y(n239) );
AO22XLTS U2477 ( .A0(n3430), .A1(Data_Y[22]), .B0(n3427), .B1(intDY[22]),
.Y(n221) );
AO22XLTS U2478 ( .A0(n3438), .A1(Data_Y[54]), .B0(n3436), .B1(intDY[54]),
.Y(n317) );
AO22XLTS U2479 ( .A0(n3438), .A1(Data_Y[56]), .B0(n3436), .B1(intDY[56]),
.Y(n323) );
AO22XLTS U2480 ( .A0(n3439), .A1(Data_Y[8]), .B0(n3428), .B1(intDY[8]), .Y(
n179) );
AO22XLTS U2481 ( .A0(n3438), .A1(Data_Y[60]), .B0(n3437), .B1(intDY[60]),
.Y(n335) );
MX2X1TS U2482 ( .A(n3062), .B(LZA_output[4]), .S0(n3151), .Y(n138) );
NAND4XLTS U2483 ( .A(n3055), .B(n3054), .C(n3065), .D(n3053), .Y(n3056) );
OAI21XLTS U2484 ( .A0(n2273), .A1(n3535), .B0(n2263), .Y(n264) );
MX2X1TS U2485 ( .A(Add_Subt_result[31]), .B(n2796), .S0(n1351), .Y(n440) );
MX2X1TS U2486 ( .A(Add_Subt_result[39]), .B(n2738), .S0(n2723), .Y(n448) );
MX2X1TS U2487 ( .A(n3128), .B(exp_oper_result[9]), .S0(n3153), .Y(n150) );
MX2X1TS U2488 ( .A(n3129), .B(exp_oper_result[8]), .S0(n3153), .Y(n149) );
MX2X1TS U2489 ( .A(n3130), .B(exp_oper_result[7]), .S0(n3153), .Y(n148) );
MX2X1TS U2490 ( .A(n3131), .B(exp_oper_result[6]), .S0(n1341), .Y(n147) );
MX2X1TS U2491 ( .A(n3127), .B(exp_oper_result[10]), .S0(n3153), .Y(n140) );
MX2X1TS U2492 ( .A(n3045), .B(exp_oper_result[1]), .S0(n3153), .Y(n142) );
MX2X1TS U2493 ( .A(n3034), .B(exp_oper_result[2]), .S0(n3153), .Y(n143) );
AOI2BB2XLTS U2494 ( .B0(n3354), .B1(n1897), .A0N(n3248), .A1N(n1947), .Y(
n1898) );
MX2X1TS U2495 ( .A(n3063), .B(exp_oper_result[4]), .S0(n3153), .Y(n145) );
MX2X1TS U2496 ( .A(n3117), .B(exp_oper_result[5]), .S0(n3153), .Y(n146) );
MX2X1TS U2497 ( .A(n3083), .B(exp_oper_result[3]), .S0(n3153), .Y(n144) );
AND3X1TS U2498 ( .A(n2050), .B(n2049), .C(n2048), .Y(n2051) );
AO21XLTS U2499 ( .A0(n1341), .A1(exp_oper_result[0]), .B0(n3152), .Y(n141)
);
MX2X1TS U2500 ( .A(Add_Subt_result[0]), .B(n2616), .S0(n1351), .Y(n409) );
MX2X1TS U2501 ( .A(Add_Subt_result[34]), .B(n2750), .S0(n1352), .Y(n443) );
MX2X1TS U2502 ( .A(Add_Subt_result[19]), .B(n2883), .S0(n2930), .Y(n428) );
MX2X1TS U2503 ( .A(Add_Subt_result[17]), .B(n2900), .S0(n2723), .Y(n426) );
MX2X1TS U2504 ( .A(Add_Subt_result[13]), .B(n2931), .S0(n2809), .Y(n422) );
MX2X1TS U2505 ( .A(Add_Subt_result[37]), .B(n2815), .S0(n2957), .Y(n446) );
MX2X1TS U2506 ( .A(Add_Subt_result[15]), .B(n2886), .S0(n3101), .Y(n424) );
MX2X1TS U2507 ( .A(Add_Subt_result[25]), .B(n2848), .S0(n2957), .Y(n434) );
AO22XLTS U2508 ( .A0(n3447), .A1(Data_Y[2]), .B0(n3427), .B1(intDY[2]), .Y(
n161) );
AO22XLTS U2509 ( .A0(n3433), .A1(Data_Y[40]), .B0(n3434), .B1(intDY[40]),
.Y(n275) );
AO22XLTS U2510 ( .A0(n3438), .A1(Data_Y[59]), .B0(n3437), .B1(intDY[59]),
.Y(n332) );
AO22XLTS U2511 ( .A0(n3439), .A1(Data_Y[9]), .B0(n3428), .B1(intDY[9]), .Y(
n182) );
MX2X1TS U2512 ( .A(Add_Subt_result[10]), .B(n2952), .S0(n2809), .Y(n419) );
AO22XLTS U2513 ( .A0(n3431), .A1(Data_Y[27]), .B0(n3427), .B1(intDY[27]),
.Y(n236) );
AO22XLTS U2514 ( .A0(n3435), .A1(Data_Y[50]), .B0(n3436), .B1(intDY[50]),
.Y(n305) );
AO22XLTS U2515 ( .A0(n3430), .A1(Data_Y[18]), .B0(n1739), .B1(intDY[18]),
.Y(n209) );
AO22XLTS U2516 ( .A0(n3433), .A1(Data_Y[36]), .B0(n3432), .B1(intDY[36]),
.Y(n263) );
AO22XLTS U2517 ( .A0(n3438), .A1(Data_Y[58]), .B0(n3436), .B1(intDY[58]),
.Y(n329) );
AO22XLTS U2518 ( .A0(n3439), .A1(Data_Y[12]), .B0(n3428), .B1(intDY[12]),
.Y(n191) );
AO22XLTS U2519 ( .A0(n3435), .A1(Data_Y[46]), .B0(n3434), .B1(intDY[46]),
.Y(n293) );
AO22XLTS U2520 ( .A0(n3430), .A1(Data_Y[14]), .B0(n3428), .B1(intDY[14]),
.Y(n197) );
MX2X1TS U2521 ( .A(Add_Subt_result[26]), .B(n2842), .S0(n2957), .Y(n435) );
AO22XLTS U2522 ( .A0(n3431), .A1(Data_Y[25]), .B0(n1739), .B1(intDY[25]),
.Y(n230) );
AO22XLTS U2523 ( .A0(n3430), .A1(Data_Y[17]), .B0(n1739), .B1(intDY[17]),
.Y(n206) );
AO22XLTS U2524 ( .A0(n3435), .A1(Data_Y[45]), .B0(n3434), .B1(intDY[45]),
.Y(n290) );
AO22XLTS U2525 ( .A0(n3438), .A1(Data_Y[57]), .B0(n3437), .B1(intDY[57]),
.Y(n326) );
AO22XLTS U2526 ( .A0(n3435), .A1(Data_Y[49]), .B0(n3436), .B1(intDY[49]),
.Y(n302) );
AO22XLTS U2527 ( .A0(n3439), .A1(Data_Y[11]), .B0(n3428), .B1(intDY[11]),
.Y(n188) );
MX2X1TS U2528 ( .A(Add_Subt_result[23]), .B(n2861), .S0(n2957), .Y(n432) );
AO22XLTS U2529 ( .A0(n3430), .A1(Data_Y[21]), .B0(n1739), .B1(intDY[21]),
.Y(n218) );
AO22XLTS U2530 ( .A0(n3433), .A1(Data_Y[35]), .B0(n3432), .B1(intDY[35]),
.Y(n260) );
AO22XLTS U2531 ( .A0(n3431), .A1(Data_Y[29]), .B0(n3432), .B1(intDY[29]),
.Y(n242) );
AO22XLTS U2532 ( .A0(n3433), .A1(Data_Y[43]), .B0(n3434), .B1(intDY[43]),
.Y(n284) );
AO22XLTS U2533 ( .A0(n3430), .A1(Data_Y[13]), .B0(n3428), .B1(intDY[13]),
.Y(n194) );
AO22XLTS U2534 ( .A0(n3431), .A1(Data_Y[31]), .B0(n3432), .B1(intDY[31]),
.Y(n248) );
AO22XLTS U2535 ( .A0(n3438), .A1(Data_Y[55]), .B0(n3436), .B1(intDY[55]),
.Y(n320) );
AO22XLTS U2536 ( .A0(n3435), .A1(Data_Y[53]), .B0(n3436), .B1(intDY[53]),
.Y(n314) );
AOI211X1TS U2537 ( .A0(FS_Module_state_reg[0]), .A1(n2957), .B0(n1357), .C0(
n1744), .Y(n1745) );
MX2X1TS U2538 ( .A(Add_Subt_result[14]), .B(n2925), .S0(n2809), .Y(n423) );
MX2X1TS U2539 ( .A(Add_Subt_result[32]), .B(n2790), .S0(n1351), .Y(n441) );
OAI21XLTS U2540 ( .A0(n2795), .A1(n2791), .B0(n2792), .Y(n2789) );
MX2X1TS U2541 ( .A(Add_Subt_result[44]), .B(n2693), .S0(n2809), .Y(n453) );
AO22XLTS U2542 ( .A0(n3431), .A1(Data_Y[33]), .B0(n3432), .B1(intDY[33]),
.Y(n254) );
AO22XLTS U2543 ( .A0(n3433), .A1(Data_Y[41]), .B0(n3434), .B1(intDY[41]),
.Y(n278) );
AO22XLTS U2544 ( .A0(n3430), .A1(Data_Y[15]), .B0(n3428), .B1(intDY[15]),
.Y(n200) );
AO22XLTS U2545 ( .A0(n3433), .A1(Data_Y[39]), .B0(n3434), .B1(intDY[39]),
.Y(n272) );
AO22XLTS U2546 ( .A0(n3429), .A1(Data_Y[3]), .B0(n3427), .B1(intDY[3]), .Y(
n164) );
MX2X1TS U2547 ( .A(Data_X[3]), .B(intDX[3]), .S0(n3090), .Y(n347) );
MX2X1TS U2548 ( .A(Add_Subt_result[28]), .B(n2822), .S0(n1352), .Y(n437) );
MX2X1TS U2549 ( .A(Data_X[14]), .B(intDX[14]), .S0(n3089), .Y(n358) );
MX2X1TS U2550 ( .A(Data_X[1]), .B(intDX[1]), .S0(n3090), .Y(n345) );
AO22XLTS U2551 ( .A0(n3429), .A1(Data_Y[1]), .B0(n3427), .B1(intDY[1]), .Y(
n158) );
MX2X1TS U2552 ( .A(Add_Subt_result[41]), .B(n2724), .S0(n1352), .Y(n450) );
NOR2XLTS U2553 ( .A(n3257), .B(n3163), .Y(n1932) );
AND3X1TS U2554 ( .A(n2111), .B(n2110), .C(n2109), .Y(n2112) );
AND3X1TS U2555 ( .A(n2103), .B(n2102), .C(n2101), .Y(n2104) );
AO22XLTS U2556 ( .A0(n3155), .A1(Sgf_normalized_result[27]), .B0(
final_result_ieee[25]), .B1(n3157), .Y(n116) );
AO22XLTS U2557 ( .A0(n3158), .A1(Sgf_normalized_result[32]), .B0(n3156),
.B1(final_result_ieee[30]), .Y(n13) );
AO22XLTS U2558 ( .A0(n3158), .A1(Sgf_normalized_result[33]), .B0(n3156),
.B1(final_result_ieee[31]), .Y(n19) );
AO22XLTS U2559 ( .A0(n3158), .A1(Sgf_normalized_result[34]), .B0(n3156),
.B1(final_result_ieee[32]), .Y(n26) );
AO22XLTS U2560 ( .A0(n1334), .A1(Sgf_normalized_result[2]), .B0(n3156), .B1(
final_result_ieee[0]), .Y(n30) );
AO22XLTS U2561 ( .A0(n3158), .A1(Sgf_normalized_result[35]), .B0(n3156),
.B1(final_result_ieee[33]), .Y(n34) );
AO22XLTS U2562 ( .A0(n1334), .A1(Sgf_normalized_result[3]), .B0(n3416), .B1(
final_result_ieee[1]), .Y(n38) );
AO22XLTS U2563 ( .A0(n3158), .A1(Sgf_normalized_result[36]), .B0(n3156),
.B1(final_result_ieee[34]), .Y(n42) );
AO22XLTS U2564 ( .A0(n3158), .A1(Sgf_normalized_result[37]), .B0(n3156),
.B1(final_result_ieee[35]), .Y(n50) );
AO22XLTS U2565 ( .A0(n3158), .A1(Sgf_normalized_result[38]), .B0(n3156),
.B1(final_result_ieee[36]), .Y(n58) );
AO22XLTS U2566 ( .A0(n3155), .A1(Sgf_normalized_result[16]), .B0(n3416),
.B1(final_result_ieee[14]), .Y(n60) );
AO22XLTS U2567 ( .A0(n3158), .A1(Sgf_normalized_result[39]), .B0(n3156),
.B1(final_result_ieee[37]), .Y(n66) );
AO22XLTS U2568 ( .A0(n3155), .A1(Sgf_normalized_result[15]), .B0(n3416),
.B1(final_result_ieee[13]), .Y(n68) );
AO22XLTS U2569 ( .A0(n3158), .A1(Sgf_normalized_result[40]), .B0(n3157),
.B1(final_result_ieee[38]), .Y(n80) );
AO22XLTS U2570 ( .A0(n1334), .A1(Sgf_normalized_result[14]), .B0(n3416),
.B1(final_result_ieee[12]), .Y(n82) );
AO22XLTS U2571 ( .A0(n3155), .A1(Sgf_normalized_result[30]), .B0(n3156),
.B1(final_result_ieee[28]), .Y(n104) );
AO22XLTS U2572 ( .A0(n3155), .A1(Sgf_normalized_result[24]), .B0(n3416),
.B1(final_result_ieee[22]), .Y(n106) );
AO22XLTS U2573 ( .A0(n3155), .A1(Sgf_normalized_result[29]), .B0(n3416),
.B1(final_result_ieee[27]), .Y(n108) );
AO22XLTS U2574 ( .A0(n3155), .A1(Sgf_normalized_result[25]), .B0(n3416),
.B1(final_result_ieee[23]), .Y(n110) );
AO22XLTS U2575 ( .A0(n3155), .A1(Sgf_normalized_result[28]), .B0(n3416),
.B1(final_result_ieee[26]), .Y(n112) );
AO22XLTS U2576 ( .A0(n3155), .A1(Sgf_normalized_result[26]), .B0(n3416),
.B1(final_result_ieee[24]), .Y(n114) );
AO22XLTS U2577 ( .A0(n3426), .A1(n3425), .B0(n3424), .B1(
final_result_ieee[63]), .Y(n129) );
AO22XLTS U2578 ( .A0(n3439), .A1(Data_Y[4]), .B0(n3427), .B1(intDY[4]), .Y(
n167) );
AO22XLTS U2579 ( .A0(n3439), .A1(Data_Y[7]), .B0(n3428), .B1(intDY[7]), .Y(
n176) );
MX2X1TS U2580 ( .A(Add_Subt_result[27]), .B(n2834), .S0(n1352), .Y(n436) );
MX2X1TS U2581 ( .A(Data_X[27]), .B(intDX[27]), .S0(n3088), .Y(n371) );
MX2X1TS U2582 ( .A(Data_X[34]), .B(intDX[34]), .S0(n3087), .Y(n378) );
MX2X1TS U2583 ( .A(Data_X[5]), .B(intDX[5]), .S0(n3090), .Y(n349) );
MX2X1TS U2584 ( .A(Data_X[19]), .B(intDX[19]), .S0(n3089), .Y(n363) );
MX2X1TS U2585 ( .A(Data_X[30]), .B(intDX[30]), .S0(n3088), .Y(n374) );
MX2X1TS U2586 ( .A(Data_X[7]), .B(intDX[7]), .S0(n3090), .Y(n351) );
MX2X1TS U2587 ( .A(Data_X[6]), .B(intDX[6]), .S0(n3090), .Y(n350) );
MX2X1TS U2588 ( .A(Add_Subt_result[3]), .B(n2997), .S0(n1352), .Y(n412) );
MX2X1TS U2589 ( .A(Data_X[22]), .B(intDX[22]), .S0(n3087), .Y(n366) );
MX2X1TS U2590 ( .A(Data_X[0]), .B(intDX[0]), .S0(n3437), .Y(n344) );
AO22XLTS U2591 ( .A0(n3438), .A1(Data_Y[61]), .B0(n3437), .B1(intDY[61]),
.Y(n338) );
AO22XLTS U2592 ( .A0(n3439), .A1(Data_Y[10]), .B0(n3428), .B1(intDY[10]),
.Y(n185) );
AO22XLTS U2593 ( .A0(n3433), .A1(Data_Y[44]), .B0(n3434), .B1(intDY[44]),
.Y(n287) );
AO22XLTS U2594 ( .A0(n3435), .A1(Data_Y[48]), .B0(n3434), .B1(intDY[48]),
.Y(n299) );
AO22XLTS U2595 ( .A0(n3435), .A1(Data_Y[52]), .B0(n3436), .B1(intDY[52]),
.Y(n311) );
AO22XLTS U2596 ( .A0(n3433), .A1(Data_Y[38]), .B0(n3432), .B1(intDY[38]),
.Y(n269) );
AO22XLTS U2597 ( .A0(n3439), .A1(Data_Y[5]), .B0(n3427), .B1(intDY[5]), .Y(
n170) );
AO22XLTS U2598 ( .A0(n3439), .A1(Data_Y[6]), .B0(n3428), .B1(intDY[6]), .Y(
n173) );
AO22XLTS U2599 ( .A0(n3430), .A1(Data_Y[16]), .B0(n1739), .B1(intDY[16]),
.Y(n203) );
MX2X1TS U2600 ( .A(Data_Y[23]), .B(intDY[23]), .S0(n3087), .Y(n224) );
AOI2BB2XLTS U2601 ( .B0(n3092), .B1(Sgf_normalized_result[41]), .A0N(n2074),
.A1N(n2335), .Y(n1964) );
AOI2BB2XLTS U2602 ( .B0(n3092), .B1(Sgf_normalized_result[42]), .A0N(n2074),
.A1N(n2337), .Y(n1960) );
OAI222X1TS U2603 ( .A0(n3507), .A1(n2373), .B0(n1860), .B1(n2310), .C0(n2363), .C1(n2309), .Y(n103) );
OAI222X1TS U2604 ( .A0(n3510), .A1(n2373), .B0(n1860), .B1(n2349), .C0(n2363), .C1(n2348), .Y(n53) );
OAI222X1TS U2605 ( .A0(n3511), .A1(n2373), .B0(n1350), .B1(n2353), .C0(n2371), .C1(n2352), .Y(n45) );
OAI222X1TS U2606 ( .A0(n3512), .A1(n2373), .B0(n1349), .B1(n2372), .C0(n2367), .C1(n2370), .Y(n37) );
MX2X1TS U2607 ( .A(Data_X[16]), .B(intDX[16]), .S0(n3089), .Y(n360) );
MX2X1TS U2608 ( .A(Data_X[32]), .B(intDX[32]), .S0(n3087), .Y(n376) );
MX2X1TS U2609 ( .A(Data_X[37]), .B(intDX[37]), .S0(n3087), .Y(n381) );
MX2X1TS U2610 ( .A(Data_X[10]), .B(intDX[10]), .S0(n3090), .Y(n354) );
MX2X1TS U2611 ( .A(Data_X[33]), .B(intDX[33]), .S0(n3087), .Y(n377) );
MX2X1TS U2612 ( .A(Data_X[36]), .B(intDX[36]), .S0(n3087), .Y(n380) );
MX2X1TS U2613 ( .A(Data_X[8]), .B(intDX[8]), .S0(n3090), .Y(n352) );
MX2X1TS U2614 ( .A(Data_X[35]), .B(intDX[35]), .S0(n3087), .Y(n379) );
MX2X1TS U2615 ( .A(Add_Subt_result[7]), .B(n3102), .S0(n2930), .Y(n416) );
MX2X1TS U2616 ( .A(Data_X[26]), .B(intDX[26]), .S0(n3088), .Y(n370) );
MX2X1TS U2617 ( .A(Data_X[38]), .B(intDX[38]), .S0(n3437), .Y(n382) );
MX2X1TS U2618 ( .A(Data_X[11]), .B(intDX[11]), .S0(n3089), .Y(n355) );
MX2X1TS U2619 ( .A(Data_X[18]), .B(intDX[18]), .S0(n3089), .Y(n362) );
MX2X1TS U2620 ( .A(Data_X[31]), .B(intDX[31]), .S0(n3087), .Y(n375) );
MX2X1TS U2621 ( .A(Data_X[17]), .B(intDX[17]), .S0(n3089), .Y(n361) );
MX2X1TS U2622 ( .A(Data_X[25]), .B(intDX[25]), .S0(n3088), .Y(n369) );
MX2X1TS U2623 ( .A(Add_Subt_result[22]), .B(n2877), .S0(n2723), .Y(n431) );
MX2X1TS U2624 ( .A(Data_X[24]), .B(intDX[24]), .S0(n3088), .Y(n368) );
MX2X1TS U2625 ( .A(Add_Subt_result[4]), .B(n2986), .S0(n3101), .Y(n413) );
MX2X1TS U2626 ( .A(Add_Subt_result[24]), .B(n2855), .S0(n1351), .Y(n433) );
OAI21XLTS U2627 ( .A0(n2849), .A1(n2856), .B0(n2857), .Y(n2854) );
MX2X1TS U2628 ( .A(Add_Subt_result[12]), .B(n2940), .S0(n3101), .Y(n421) );
MX2X1TS U2629 ( .A(Data_X[4]), .B(intDX[4]), .S0(n3090), .Y(n348) );
MX2X1TS U2630 ( .A(Data_X[21]), .B(intDX[21]), .S0(n3087), .Y(n365) );
MX2X1TS U2631 ( .A(Data_X[29]), .B(intDX[29]), .S0(n3088), .Y(n373) );
MX2X1TS U2632 ( .A(Data_X[2]), .B(intDX[2]), .S0(n3090), .Y(n346) );
MX2X1TS U2633 ( .A(Data_X[12]), .B(intDX[12]), .S0(n3089), .Y(n356) );
MX2X1TS U2634 ( .A(Data_X[13]), .B(intDX[13]), .S0(n3089), .Y(n357) );
MX2X1TS U2635 ( .A(Data_X[20]), .B(intDX[20]), .S0(n3089), .Y(n364) );
MX2X1TS U2636 ( .A(Data_X[28]), .B(intDX[28]), .S0(n3088), .Y(n372) );
MX2X1TS U2637 ( .A(Data_X[9]), .B(intDX[9]), .S0(n3090), .Y(n353) );
MX2X1TS U2638 ( .A(Data_X[15]), .B(intDX[15]), .S0(n3089), .Y(n359) );
MX2X1TS U2639 ( .A(Add_Subt_result[11]), .B(n2958), .S0(n2723), .Y(n420) );
OAI21XLTS U2640 ( .A0(n1974), .A1(n3240), .B0(n1973), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[45]) );
MX2X1TS U2641 ( .A(Add_Subt_result[20]), .B(n2627), .S0(n2930), .Y(n429) );
AO22XLTS U2642 ( .A0(n3438), .A1(Data_X[23]), .B0(n3437), .B1(intDX[23]),
.Y(n367) );
MX2X1TS U2643 ( .A(Add_Subt_result[18]), .B(n2894), .S0(n2809), .Y(n427) );
MX2X1TS U2644 ( .A(Add_Subt_result[1]), .B(n3044), .S0(n1352), .Y(n410) );
MX2X1TS U2645 ( .A(Add_Subt_result[43]), .B(n2718), .S0(n2809), .Y(n452) );
MX2X1TS U2646 ( .A(Add_Subt_result[40]), .B(n2733), .S0(n2957), .Y(n449) );
NAND4XLTS U2647 ( .A(n3114), .B(n3113), .C(n3112), .D(n3111), .Y(n3115) );
NAND4XLTS U2648 ( .A(n3145), .B(n3144), .C(n3143), .D(n3142), .Y(n3147) );
AO21XLTS U2649 ( .A0(LZA_output[1]), .A1(n3151), .B0(n1570), .Y(n135) );
NAND4XLTS U2650 ( .A(n3079), .B(n3078), .C(n3077), .D(n3076), .Y(n3080) );
NAND3XLTS U2651 ( .A(n3075), .B(n3595), .C(n3074), .Y(n3076) );
OAI21XLTS U2652 ( .A0(n2163), .A1(n2162), .B0(n2161), .Y(n151) );
AOI2BB2XLTS U2653 ( .B0(n1357), .B1(intDX[63]), .A0N(n2279), .A1N(n2159),
.Y(n2163) );
MX2X1TS U2654 ( .A(Data_Y[63]), .B(intDY[63]), .S0(n3088), .Y(n152) );
MX2X1TS U2655 ( .A(add_subt), .B(intAS), .S0(n3088), .Y(n342) );
MX2X1TS U2656 ( .A(Data_X[63]), .B(intDX[63]), .S0(n3088), .Y(n343) );
AOI2BB1X1TS U2657 ( .A0N(n1716), .A1N(n1715), .B0(n3123), .Y(n407) );
NAND4BXLTS U2658 ( .AN(n3119), .B(n1743), .C(n1713), .D(n3118), .Y(n1715) );
MX2X1TS U2659 ( .A(Add_Subt_result[54]), .B(n2613), .S0(n3101), .Y(n408) );
MX2X1TS U2660 ( .A(Add_Subt_result[45]), .B(n2684), .S0(n3101), .Y(n454) );
MX2X1TS U2661 ( .A(Add_Subt_result[46]), .B(n2679), .S0(n2930), .Y(n455) );
MX2X1TS U2662 ( .A(Add_Subt_result[48]), .B(n2633), .S0(n2809), .Y(n457) );
MX2X1TS U2663 ( .A(Add_Subt_result[49]), .B(n2638), .S0(n2723), .Y(n458) );
MX2X1TS U2664 ( .A(Add_Subt_result[50]), .B(n2644), .S0(n3101), .Y(n459) );
MX2X1TS U2665 ( .A(Add_Subt_result[51]), .B(n2654), .S0(n1352), .Y(n460) );
MX2X1TS U2666 ( .A(Add_Subt_result[52]), .B(n2660), .S0(n1352), .Y(n461) );
MX2X1TS U2667 ( .A(Add_Subt_result[53]), .B(n2649), .S0(n1351), .Y(n462) );
OAI211XLTS U2668 ( .A0(n3448), .A1(n1750), .B0(n3125), .C0(n1749), .Y(n467)
);
NAND3XLTS U2669 ( .A(n3151), .B(n1858), .C(n3118), .Y(n1747) );
CLKBUFX2TS U2670 ( .A(n1846), .Y(n2039) );
AND2X4TS U2671 ( .A(n1761), .B(n1937), .Y(n3207) );
OR2X1TS U2672 ( .A(n1355), .B(n1356), .Y(n1335) );
INVX2TS U2673 ( .A(n2596), .Y(n2597) );
BUFX3TS U2674 ( .A(n2141), .Y(n2220) );
NOR2X2TS U2675 ( .A(n2324), .B(n3092), .Y(n2133) );
BUFX3TS U2676 ( .A(n2211), .Y(n2256) );
INVX2TS U2677 ( .A(n1873), .Y(n2127) );
BUFX3TS U2678 ( .A(n1722), .Y(n3153) );
INVX2TS U2679 ( .A(n2876), .Y(n2723) );
OAI21X2TS U2680 ( .A0(n2612), .A1(n2605), .B0(n2609), .Y(n2607) );
INVX2TS U2681 ( .A(n2042), .Y(n1337) );
INVX2TS U2682 ( .A(n2042), .Y(n1338) );
INVX2TS U2683 ( .A(n3153), .Y(n1340) );
INVX2TS U2684 ( .A(n1340), .Y(n1341) );
INVX2TS U2685 ( .A(n2039), .Y(n1342) );
INVX2TS U2686 ( .A(n1342), .Y(n1343) );
INVX2TS U2687 ( .A(n2066), .Y(n1344) );
INVX2TS U2688 ( .A(n3207), .Y(n1345) );
INVX2TS U2689 ( .A(n1345), .Y(n1346) );
INVX2TS U2690 ( .A(n1345), .Y(n1347) );
INVX2TS U2691 ( .A(n1860), .Y(n1348) );
INVX2TS U2692 ( .A(n1348), .Y(n1349) );
INVX2TS U2693 ( .A(n1348), .Y(n1350) );
OAI21X1TS U2694 ( .A0(n3590), .A1(n2039), .B0(n1847), .Y(n1864) );
OAI21XLTS U2695 ( .A0(n2200), .A1(n3567), .B0(n2184), .Y(n189) );
OAI21XLTS U2696 ( .A0(n2200), .A1(n3552), .B0(n2189), .Y(n204) );
OAI21XLTS U2697 ( .A0(n2200), .A1(n3550), .B0(n2191), .Y(n207) );
OAI21XLTS U2698 ( .A0(n2200), .A1(n3470), .B0(n2180), .Y(n219) );
OAI21XLTS U2699 ( .A0(n2266), .A1(n3555), .B0(n2176), .Y(n225) );
OAI21XLTS U2700 ( .A0(n2266), .A1(n3553), .B0(n2186), .Y(n228) );
OAI21XLTS U2701 ( .A0(n2266), .A1(n3551), .B0(n1572), .Y(n246) );
OAI21XLTS U2702 ( .A0(n2273), .A1(n3534), .B0(n2268), .Y(n249) );
OAI21XLTS U2703 ( .A0(n2266), .A1(n3537), .B0(n1573), .Y(n252) );
OAI21XLTS U2704 ( .A0(n2266), .A1(n3460), .B0(n2265), .Y(n255) );
OAI21XLTS U2705 ( .A0(n2273), .A1(n3540), .B0(n1571), .Y(n258) );
OAI21XLTS U2706 ( .A0(n2273), .A1(n3575), .B0(n2269), .Y(n273) );
INVX4TS U2707 ( .A(n2596), .Y(n2519) );
AOI221X1TS U2708 ( .A0(n3571), .A1(intDY[9]), .B0(intDY[6]), .B1(n3466),
.C0(n1663), .Y(n1664) );
OAI21XLTS U2709 ( .A0(n2204), .A1(n3566), .B0(n1514), .Y(n159) );
AOI221X1TS U2710 ( .A0(n3572), .A1(intDY[3]), .B0(intDY[2]), .B1(n3566),
.C0(n1662), .Y(n1665) );
INVX2TS U2711 ( .A(n2876), .Y(n1351) );
INVX2TS U2712 ( .A(n2876), .Y(n1352) );
OAI21X2TS U2713 ( .A0(n2031), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[108]), .B0(n2030), .Y(n2356) );
AOI21X2TS U2714 ( .A0(n2008), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[99]), .B0(n1917), .Y(n2313)
);
OAI21X2TS U2715 ( .A0(n2031), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[107]), .B0(n2030), .Y(n3091) );
AOI22X2TS U2716 ( .A0(n1939), .A1(n1938), .B0(n3239), .B1(n1937), .Y(n3248)
);
OAI2BB1X2TS U2717 ( .A0N(Add_Subt_result[28]), .A1N(n1894), .B0(n1822), .Y(
n3239) );
AOI22X2TS U2718 ( .A0(n1939), .A1(n3249), .B0(n1938), .B1(n1937), .Y(n3255)
);
OAI222X1TS U2719 ( .A0(n2345), .A1(n1350), .B0(n2363), .B1(n2344), .C0(n2361), .C1(n3502), .Y(n63) );
OAI21X2TS U2720 ( .A0(n2031), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[103]), .B0(n2030), .Y(n2345) );
OAI222X1TS U2721 ( .A0(n2359), .A1(n1349), .B0(n2371), .B1(n2358), .C0(n2361), .C1(n3501), .Y(n55) );
OAI21X2TS U2722 ( .A0(n2031), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[104]), .B0(n2030), .Y(n2359) );
AOI21X2TS U2723 ( .A0(n2008), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[101]), .B0(n1865), .Y(n2319) );
OAI21X1TS U2724 ( .A0(n1846), .A1(n3583), .B0(n1847), .Y(n1865) );
AOI21X2TS U2725 ( .A0(n2035), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[100]), .B0(n1922), .Y(n2316) );
OAI21X2TS U2726 ( .A0(n2031), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[105]), .B0(n2030), .Y(n2364) );
CLKINVX3TS U2727 ( .A(n2320), .Y(n2072) );
OAI21X2TS U2728 ( .A0(n1846), .A1(n3588), .B0(n1990), .Y(n2041) );
NOR3X1TS U2729 ( .A(Add_Subt_result[33]), .B(Add_Subt_result[34]), .C(
Add_Subt_result[30]), .Y(n1521) );
OAI211XLTS U2730 ( .A0(Add_Subt_result[42]), .A1(Add_Subt_result[40]), .B0(
n3007), .C0(n3597), .Y(n3008) );
OAI211XLTS U2731 ( .A0(n3256), .A1(n1985), .B0(n1984), .C0(n1983), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[19]) );
OAI221X1TS U2732 ( .A0(n2253), .A1(intDY[58]), .B0(n3535), .B1(intDY[37]),
.C0(n1684), .Y(n1691) );
NOR2X1TS U2733 ( .A(Add_Subt_result[9]), .B(Add_Subt_result[8]), .Y(n1549)
);
AOI221X1TS U2734 ( .A0(n3471), .A1(intDY[0]), .B0(intDY[40]), .B1(n3575),
.C0(n1655), .Y(n1656) );
AOI221X1TS U2735 ( .A0(n3453), .A1(intDY[27]), .B0(intDY[26]), .B1(n3544),
.C0(n1654), .Y(n1657) );
AOI32X1TS U2736 ( .A0(n3544), .A1(n1423), .A2(intDY[26]), .B0(intDY[27]),
.B1(n3453), .Y(n1424) );
OAI22X2TS U2737 ( .A0(n3453), .A1(intDY[27]), .B0(n3544), .B1(intDY[26]),
.Y(n1654) );
OAI221XLTS U2738 ( .A0(n3538), .A1(intDY[36]), .B0(n3527), .B1(intDY[47]),
.C0(n1685), .Y(n1690) );
AOI32X1TS U2739 ( .A0(n3550), .A1(n1403), .A2(intDY[18]), .B0(intDY[19]),
.B1(n3462), .Y(n1404) );
OAI221XLTS U2740 ( .A0(n3550), .A1(intDY[18]), .B0(n3462), .B1(intDY[19]),
.C0(n1643), .Y(n1644) );
OAI221XLTS U2741 ( .A0(n3551), .A1(intDY[31]), .B0(n3463), .B1(intDY[30]),
.C0(n1641), .Y(n1646) );
OAI221X1TS U2742 ( .A0(n3521), .A1(intDY[46]), .B0(n3458), .B1(intDY[42]),
.C0(n1694), .Y(n1697) );
AOI32X1TS U2743 ( .A0(n3459), .A1(n1495), .A2(intDY[50]), .B0(intDY[51]),
.B1(n3546), .Y(n1496) );
OAI221X1TS U2744 ( .A0(n3546), .A1(intDY[51]), .B0(n3459), .B1(intDY[50]),
.C0(n1676), .Y(n1683) );
OAI221X1TS U2745 ( .A0(n3460), .A1(intDY[34]), .B0(n3526), .B1(intDY[45]),
.C0(n1692), .Y(n1699) );
OAI221X1TS U2746 ( .A0(n3525), .A1(intDY[62]), .B0(n3444), .B1(intDY[57]),
.C0(n1678), .Y(n1681) );
OAI21XLTS U2747 ( .A0(intDY[33]), .A1(n3537), .B0(intDY[32]), .Y(n1475) );
OAI221XLTS U2748 ( .A0(n3534), .A1(intDY[32]), .B0(n3545), .B1(intDY[59]),
.C0(n1687), .Y(n1688) );
AOI221X1TS U2749 ( .A0(n3569), .A1(intDY[20]), .B0(intDY[21]), .B1(n3564),
.C0(n1639), .Y(n1649) );
AOI221X1TS U2750 ( .A0(n3570), .A1(intDY[28]), .B0(intDY[29]), .B1(n3565),
.C0(n1638), .Y(n1650) );
OA22X1TS U2751 ( .A0(n3470), .A1(intDY[22]), .B0(n3592), .B1(intDY[23]), .Y(
n1412) );
AOI221X1TS U2752 ( .A0(n3470), .A1(intDY[22]), .B0(intDY[12]), .B1(n3567),
.C0(n1661), .Y(n1666) );
OAI221X1TS U2753 ( .A0(n3455), .A1(intDY[55]), .B0(n3530), .B1(intDY[54]),
.C0(n1670), .Y(n1673) );
OAI221XLTS U2754 ( .A0(n3456), .A1(intDY[56]), .B0(n3528), .B1(intDY[48]),
.C0(n1679), .Y(n1680) );
OAI221XLTS U2755 ( .A0(n3522), .A1(intDY[49]), .B0(n3539), .B1(intDY[8]),
.C0(n1671), .Y(n1672) );
OAI221XLTS U2756 ( .A0(n3523), .A1(intDY[53]), .B0(n2230), .B1(intDY[60]),
.C0(n1669), .Y(n1674) );
OAI221X1TS U2757 ( .A0(n3537), .A1(intDY[33]), .B0(n3556), .B1(intDY[39]),
.C0(n1686), .Y(n1689) );
AOI211X1TS U2758 ( .A0(n3123), .A1(FS_Module_state_reg[1]), .B0(n3422), .C0(
n1748), .Y(n1746) );
OAI21XLTS U2759 ( .A0(n2273), .A1(n3556), .B0(n2264), .Y(n270) );
OAI21XLTS U2760 ( .A0(n2266), .A1(n3536), .B0(n2194), .Y(n183) );
OAI21XLTS U2761 ( .A0(n2200), .A1(n3539), .B0(n1515), .Y(n177) );
OAI21XLTS U2762 ( .A0(n2204), .A1(n3465), .B0(n2203), .Y(n174) );
OAI21XLTS U2763 ( .A0(n2204), .A1(n3466), .B0(n2201), .Y(n171) );
OAI21XLTS U2764 ( .A0(n2204), .A1(n3461), .B0(n2195), .Y(n168) );
OAI21XLTS U2765 ( .A0(n2204), .A1(n3563), .B0(n2202), .Y(n165) );
OAI21XLTS U2766 ( .A0(n2204), .A1(n3572), .B0(n2193), .Y(n162) );
OAI211X4TS U2767 ( .A0(sign_final_result), .A1(r_mode[1]), .B0(n1718), .C0(
n1717), .Y(n3121) );
NAND2X1TS U2768 ( .A(n1592), .B(LZA_output[3]), .Y(n1841) );
CLKINVX3TS U2769 ( .A(rst), .Y(n1732) );
OAI222X1TS U2770 ( .A0(n3509), .A1(n2373), .B0(n1349), .B1(n2335), .C0(n2371), .C1(n2334), .Y(n91) );
AOI21X2TS U2771 ( .A0(n2035), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[96]), .B0(n1923), .Y(n2335)
);
OAI222X1TS U2772 ( .A0(n3508), .A1(n2373), .B0(n1350), .B1(n2337), .C0(n2367), .C1(n2336), .Y(n99) );
AOI21X2TS U2773 ( .A0(n2008), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[97]), .B0(n1918), .Y(n2337)
);
NAND2X1TS U2774 ( .A(n1592), .B(LZA_output[0]), .Y(n1594) );
NOR2XLTS U2775 ( .A(n2008), .B(n1908), .Y(n1356) );
AND2X2TS U2776 ( .A(n1854), .B(n1853), .Y(n2008) );
NOR2X2TS U2777 ( .A(n1817), .B(n1816), .Y(n3167) );
OAI222X1TS U2778 ( .A0(n2340), .A1(n1350), .B0(n2367), .B1(n2339), .C0(n2361), .C1(n3503), .Y(n71) );
OAI21X2TS U2779 ( .A0(n2031), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[102]), .B0(n2030), .Y(n2340) );
NOR2X2TS U2780 ( .A(Add_Subt_result[32]), .B(Add_Subt_result[31]), .Y(n3046)
);
OAI2BB1X2TS U2781 ( .A0N(Add_Subt_result[31]), .A1N(n1894), .B0(n1771), .Y(
n1823) );
INVX2TS U2782 ( .A(n1339), .Y(n1358) );
INVX2TS U2783 ( .A(n1339), .Y(n1359) );
NAND2X1TS U2784 ( .A(n1842), .B(exp_oper_result[4]), .Y(n1843) );
NAND2X1TS U2785 ( .A(n1849), .B(exp_oper_result[5]), .Y(n1850) );
NAND2X1TS U2786 ( .A(n1849), .B(exp_oper_result[3]), .Y(n1840) );
OR2X1TS U2787 ( .A(Add_Subt_result[28]), .B(Add_Subt_result[29]), .Y(n1525)
);
OAI31X1TS U2788 ( .A0(Add_Subt_result[28]), .A1(Add_Subt_result[29]), .A2(
Add_Subt_result[26]), .B0(n3049), .Y(n3055) );
AOI21X2TS U2789 ( .A0(n2035), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[98]), .B0(n1913), .Y(n2310)
);
AOI211X4TS U2790 ( .A0(n1342), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[95]), .B0(n1848), .C0(n2325), .Y(n2368) );
AOI21X2TS U2791 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[95]), .A1(
n2035), .B0(n1864), .Y(n1955) );
NAND3BX2TS U2792 ( .AN(n3104), .B(n3061), .C(Add_Subt_result[0]), .Y(n3112)
);
NOR2X2TS U2793 ( .A(n1529), .B(Add_Subt_result[16]), .Y(n3106) );
NOR2X2TS U2794 ( .A(Add_Subt_result[20]), .B(Add_Subt_result[19]), .Y(n1552)
);
NOR3X1TS U2795 ( .A(Add_Subt_result[23]), .B(Add_Subt_result[22]), .C(
Add_Subt_result[15]), .Y(n1530) );
OAI31X1TS U2796 ( .A0(n3560), .A1(Add_Subt_result[26]), .A2(
Add_Subt_result[25]), .B0(n3452), .Y(n1542) );
OAI31X1TS U2797 ( .A0(Add_Subt_result[5]), .A1(Add_Subt_result[6]), .A2(
Add_Subt_result[2]), .B0(n3110), .Y(n3111) );
AOI32X1TS U2798 ( .A0(n2253), .A1(n1443), .A2(intDY[58]), .B0(intDY[59]),
.B1(n3545), .Y(n1444) );
OA22X1TS U2799 ( .A0(n3469), .A1(intDY[14]), .B0(n3573), .B1(intDY[15]), .Y(
n1396) );
OAI21XLTS U2800 ( .A0(intDY[15]), .A1(n3573), .B0(intDY[14]), .Y(n1392) );
OAI21XLTS U2801 ( .A0(Add_Subt_result[26]), .A1(Add_Subt_result[24]), .B0(
n3073), .Y(n3077) );
NOR2X1TS U2802 ( .A(n3553), .B(intDY[25]), .Y(n1421) );
OAI221XLTS U2803 ( .A0(n3548), .A1(intDY[38]), .B0(n3553), .B1(intDY[25]),
.C0(n1636), .Y(n1637) );
NOR2X1TS U2804 ( .A(n3552), .B(intDY[17]), .Y(n1401) );
OAI221X1TS U2805 ( .A0(n3533), .A1(intDY[16]), .B0(n3552), .B1(intDY[17]),
.C0(n1640), .Y(n1647) );
NOR2X1TS U2806 ( .A(n3531), .B(intDY[57]), .Y(n1441) );
NOR2X1TS U2807 ( .A(n3522), .B(intDY[49]), .Y(n1493) );
NOR2X1TS U2808 ( .A(n3549), .B(intDY[11]), .Y(n1383) );
OAI221X1TS U2809 ( .A0(n3549), .A1(intDY[11]), .B0(n3536), .B1(intDY[10]),
.C0(n1668), .Y(n1675) );
OAI21XLTS U2810 ( .A0(intDY[21]), .A1(n3564), .B0(intDY[20]), .Y(n1400) );
OAI21XLTS U2811 ( .A0(intDY[35]), .A1(n3540), .B0(intDY[34]), .Y(n1476) );
OA22X1TS U2812 ( .A0(n3460), .A1(intDY[34]), .B0(n3540), .B1(intDY[35]), .Y(
n1478) );
OAI221XLTS U2813 ( .A0(n3520), .A1(intDY[41]), .B0(n3540), .B1(intDY[35]),
.C0(n1695), .Y(n1696) );
OAI21XLTS U2814 ( .A0(intDY[29]), .A1(n3565), .B0(intDY[28]), .Y(n1420) );
OA22X1TS U2815 ( .A0(n3458), .A1(intDY[42]), .B0(n3547), .B1(intDY[43]), .Y(
n1463) );
OAI221X1TS U2816 ( .A0(n3547), .A1(intDY[43]), .B0(n3491), .B1(intDX[23]),
.C0(n1642), .Y(n1645) );
OAI21XLTS U2817 ( .A0(intDY[13]), .A1(n3568), .B0(intDY[12]), .Y(n1382) );
OA22X1TS U2818 ( .A0(n3463), .A1(intDY[30]), .B0(n3551), .B1(intDY[31]), .Y(
n1431) );
OR2X1TS U2819 ( .A(Add_Subt_result[42]), .B(Add_Subt_result[43]), .Y(n1360)
);
OAI21XLTS U2820 ( .A0(intDX[1]), .A1(n3474), .B0(intDX[0]), .Y(n1371) );
OAI21XLTS U2821 ( .A0(intDY[41]), .A1(n3520), .B0(intDY[40]), .Y(n1460) );
OAI21XLTS U2822 ( .A0(intDX[37]), .A1(n1361), .B0(n1473), .Y(n1482) );
NOR2XLTS U2823 ( .A(n3135), .B(Add_Subt_result[52]), .Y(n3136) );
NOR2XLTS U2824 ( .A(FSM_selector_D), .B(n3502), .Y(n2389) );
NAND2X1TS U2825 ( .A(n2668), .B(n2567), .Y(n2569) );
OAI21XLTS U2826 ( .A0(n3136), .A1(Add_Subt_result[53]), .B0(n3603), .Y(n3137) );
NOR4X1TS U2827 ( .A(n1509), .B(n1474), .C(n1507), .D(n1440), .Y(n1455) );
NOR2X1TS U2828 ( .A(n2706), .B(n2708), .Y(n2557) );
NOR2X1TS U2829 ( .A(n2725), .B(n2728), .Y(n2702) );
INVX2TS U2830 ( .A(n3072), .Y(n3027) );
NAND2X1TS U2831 ( .A(n1592), .B(LZA_output[4]), .Y(n1844) );
NOR2X1TS U2832 ( .A(n2932), .B(n2935), .Y(n2914) );
OAI21X2TS U2833 ( .A0(n2970), .A1(n2401), .B0(n2400), .Y(n2911) );
NAND2X1TS U2834 ( .A(n2456), .B(n2455), .Y(n2901) );
INVX2TS U2835 ( .A(n2745), .Y(n2747) );
INVX2TS U2836 ( .A(n2804), .Y(n2806) );
OAI21X2TS U2837 ( .A0(n2737), .A1(n2667), .B0(n2666), .Y(n2687) );
NOR2X1TS U2838 ( .A(n2578), .B(n2577), .Y(n2628) );
NOR2X1TS U2839 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[3]), .Y(
n1574) );
INVX2TS U2840 ( .A(n2911), .Y(n3100) );
AOI31XLTS U2841 ( .A0(n3132), .A1(n1568), .A2(Add_Subt_result[16]), .B0(
n1567), .Y(n1569) );
BUFX3TS U2842 ( .A(n2141), .Y(n2157) );
INVX2TS U2843 ( .A(n2849), .Y(n2860) );
INVX2TS U2844 ( .A(n2727), .Y(n2737) );
AND3X1TS U2845 ( .A(n1829), .B(n1828), .C(n1827), .Y(n3224) );
BUFX3TS U2846 ( .A(n3237), .Y(n3256) );
OAI21XLTS U2847 ( .A0(n3123), .A1(n3122), .B0(FS_Module_state_reg[3]), .Y(
n3124) );
OAI21XLTS U2848 ( .A0(n2200), .A1(n3471), .B0(n2199), .Y(n153) );
OAI21XLTS U2849 ( .A0(n3461), .A1(n2178), .B0(n2138), .Y(n169) );
OAI21XLTS U2850 ( .A0(n2273), .A1(n3548), .B0(n2244), .Y(n267) );
OAI21X1TS U2851 ( .A0(intDY[18]), .A1(n3550), .B0(n1403), .Y(n1407) );
AOI21X1TS U2852 ( .A0(intDX[10]), .A1(n3476), .B0(n1383), .Y(n1388) );
OAI2BB1X1TS U2853 ( .A0N(n3483), .A1N(intDX[5]), .B0(intDY[4]), .Y(n1369) );
OAI22X1TS U2854 ( .A0(intDX[4]), .A1(n1369), .B0(n3483), .B1(intDX[5]), .Y(
n1380) );
OAI2BB1X1TS U2855 ( .A0N(n3451), .A1N(intDX[7]), .B0(intDY[6]), .Y(n1370) );
OAI22X1TS U2856 ( .A0(intDX[6]), .A1(n1370), .B0(n3451), .B1(intDX[7]), .Y(
n1379) );
OAI211X1TS U2857 ( .A0(n3572), .A1(intDY[3]), .B0(n1373), .C0(n1372), .Y(
n1376) );
AOI2BB2X1TS U2858 ( .B0(intDY[3]), .B1(n3572), .A0N(intDX[2]), .A1N(n1374),
.Y(n1375) );
AOI22X1TS U2859 ( .A0(intDX[7]), .A1(n3451), .B0(intDX[6]), .B1(n3487), .Y(
n1377) );
OAI32X1TS U2860 ( .A0(n1380), .A1(n1379), .A2(n1378), .B0(n1377), .B1(n1379),
.Y(n1381) );
OAI2BB2XLTS U2861 ( .B0(intDX[12]), .B1(n1382), .A0N(intDY[13]), .A1N(n3568),
.Y(n1395) );
AOI22X1TS U2862 ( .A0(intDY[11]), .A1(n3549), .B0(intDY[10]), .B1(n1384),
.Y(n1391) );
NAND3X1TS U2863 ( .A(n3539), .B(n1385), .C(intDY[8]), .Y(n1387) );
OAI2BB2XLTS U2864 ( .B0(intDX[14]), .B1(n1392), .A0N(intDY[15]), .A1N(n3573),
.Y(n1393) );
AOI211X1TS U2865 ( .A0(n1396), .A1(n1395), .B0(n1394), .C0(n1393), .Y(n1397)
);
OAI2BB2XLTS U2866 ( .B0(intDX[20]), .B1(n1400), .A0N(intDY[21]), .A1N(n3564),
.Y(n1411) );
AOI22X1TS U2867 ( .A0(n1402), .A1(intDY[16]), .B0(intDY[17]), .B1(n3552),
.Y(n1405) );
OAI32X1TS U2868 ( .A0(n1407), .A1(n1406), .A2(n1405), .B0(n1404), .B1(n1406),
.Y(n1410) );
OAI2BB2XLTS U2869 ( .B0(intDX[22]), .B1(n1408), .A0N(intDY[23]), .A1N(n3592),
.Y(n1409) );
AOI211X1TS U2870 ( .A0(n1412), .A1(n1411), .B0(n1410), .C0(n1409), .Y(n1413)
);
NOR2BX1TS U2871 ( .AN(intDX[24]), .B(intDY[24]), .Y(n1417) );
AOI22X1TS U2872 ( .A0(n1422), .A1(intDY[24]), .B0(intDY[25]), .B1(n3553),
.Y(n1425) );
OAI32X1TS U2873 ( .A0(n1654), .A1(n1426), .A2(n1425), .B0(n1424), .B1(n1426),
.Y(n1429) );
OAI22X1TS U2874 ( .A0(n3455), .A1(intDY[55]), .B0(intDY[54]), .B1(n3530),
.Y(n1490) );
NOR2BX1TS U2875 ( .AN(intDX[56]), .B(intDY[56]), .Y(n1435) );
NAND2X1TS U2876 ( .A(n3473), .B(intDX[61]), .Y(n1447) );
OAI21X1TS U2877 ( .A0(intDY[58]), .A1(n3457), .B0(n1443), .Y(n1445) );
NOR4X2TS U2878 ( .A(n1435), .B(n1441), .C(n1453), .D(n1445), .Y(n1501) );
OAI21X1TS U2879 ( .A0(intDY[50]), .A1(n3459), .B0(n1495), .Y(n1499) );
AOI211X1TS U2880 ( .A0(intDX[48]), .A1(n3478), .B0(n1493), .C0(n1499), .Y(
n1436) );
NAND2X1TS U2881 ( .A(n1361), .B(intDX[37]), .Y(n1472) );
OAI21X1TS U2882 ( .A0(intDY[46]), .A1(n3521), .B0(n1457), .Y(n1467) );
OAI211X1TS U2883 ( .A0(n3537), .A1(intDY[33]), .B0(n1439), .C0(n1478), .Y(
n1440) );
INVX2TS U2884 ( .A(intDX[57]), .Y(n3444) );
AOI22X1TS U2885 ( .A0(intDY[57]), .A1(n3444), .B0(intDY[56]), .B1(n1442),
.Y(n1446) );
INVX2TS U2886 ( .A(intDX[58]), .Y(n2253) );
INVX2TS U2887 ( .A(intDX[60]), .Y(n2230) );
NOR2BX1TS U2888 ( .AN(n1457), .B(intDX[46]), .Y(n1471) );
AOI22X1TS U2889 ( .A0(intDY[45]), .A1(n3526), .B0(intDY[44]), .B1(n1459),
.Y(n1468) );
OAI2BB2XLTS U2890 ( .B0(intDX[40]), .B1(n1460), .A0N(intDY[41]), .A1N(n3520),
.Y(n1464) );
OAI2BB2XLTS U2891 ( .B0(intDX[42]), .B1(n1461), .A0N(intDY[43]), .A1N(n3547),
.Y(n1462) );
AOI32X1TS U2892 ( .A0(n1465), .A1(n1464), .A2(n1463), .B0(n1462), .B1(n1465),
.Y(n1466) );
NOR2BX1TS U2893 ( .AN(intDY[47]), .B(intDX[47]), .Y(n1469) );
AOI211X1TS U2894 ( .A0(intDY[46]), .A1(n1471), .B0(n1470), .C0(n1469), .Y(
n1508) );
OAI2BB2XLTS U2895 ( .B0(intDX[32]), .B1(n1475), .A0N(intDY[33]), .A1N(n3537),
.Y(n1479) );
OAI2BB2XLTS U2896 ( .B0(intDX[34]), .B1(n1476), .A0N(intDY[35]), .A1N(n3540),
.Y(n1477) );
AOI32X1TS U2897 ( .A0(n1480), .A1(n1479), .A2(n1478), .B0(n1477), .B1(n1480),
.Y(n1481) );
NOR2BX1TS U2898 ( .AN(intDY[39]), .B(intDX[39]), .Y(n1487) );
NOR3X1TS U2899 ( .A(n3480), .B(n1484), .C(intDX[38]), .Y(n1486) );
INVX2TS U2900 ( .A(n1509), .Y(n1485) );
OAI31X1TS U2901 ( .A0(n1488), .A1(n1487), .A2(n1486), .B0(n1485), .Y(n1506)
);
INVX2TS U2902 ( .A(n1492), .Y(n1498) );
AOI22X1TS U2903 ( .A0(intDY[49]), .A1(n3522), .B0(intDY[48]), .B1(n1494),
.Y(n1497) );
OAI32X1TS U2904 ( .A0(n1499), .A1(n1498), .A2(n1497), .B0(n1496), .B1(n1498),
.Y(n1503) );
OAI2BB2XLTS U2905 ( .B0(intDX[54]), .B1(n1500), .A0N(intDY[55]), .A1N(n3455),
.Y(n1502) );
OAI31X1TS U2906 ( .A0(n1504), .A1(n1503), .A2(n1502), .B0(n1501), .Y(n1505)
);
NOR2X2TS U2907 ( .A(n1363), .B(FS_Module_state_reg[2]), .Y(n3122) );
INVX2TS U2908 ( .A(n3122), .Y(n1719) );
BUFX3TS U2909 ( .A(n2209), .Y(n2217) );
AOI22X1TS U2910 ( .A0(n2218), .A1(intDY[9]), .B0(DMP[9]), .B1(n2217), .Y(
n1513) );
AOI22X1TS U2911 ( .A0(n2218), .A1(intDY[2]), .B0(DMP[2]), .B1(n2296), .Y(
n1514) );
AOI22X1TS U2912 ( .A0(n2218), .A1(intDY[8]), .B0(DMP[8]), .B1(n2217), .Y(
n1515) );
BUFX3TS U2913 ( .A(n2209), .Y(n2260) );
AOI22X1TS U2914 ( .A0(n2237), .A1(intDY[55]), .B0(DMP[55]), .B1(n2260), .Y(
n1516) );
AOI22X1TS U2915 ( .A0(n2235), .A1(intDY[53]), .B0(DMP[53]), .B1(n2260), .Y(
n1517) );
NOR2X2TS U2916 ( .A(n3519), .B(FS_Module_state_reg[0]), .Y(n1714) );
NAND2X1TS U2917 ( .A(n1714), .B(n3448), .Y(n3033) );
INVX2TS U2918 ( .A(n3033), .Y(n1518) );
NAND2X2TS U2919 ( .A(n1518), .B(n1363), .Y(n3151) );
NOR2X2TS U2920 ( .A(Add_Subt_result[51]), .B(Add_Subt_result[52]), .Y(n1557)
);
NOR2X2TS U2921 ( .A(Add_Subt_result[54]), .B(Add_Subt_result[53]), .Y(n1565)
);
NAND2X2TS U2922 ( .A(n1557), .B(n1565), .Y(n3015) );
NOR2X1TS U2923 ( .A(Add_Subt_result[50]), .B(Add_Subt_result[48]), .Y(n1519)
);
NAND2X2TS U2924 ( .A(n3475), .B(n1519), .Y(n3012) );
NOR2X4TS U2925 ( .A(n3015), .B(n3012), .Y(n3075) );
NOR2X2TS U2926 ( .A(Add_Subt_result[46]), .B(Add_Subt_result[45]), .Y(n1560)
);
NAND2X2TS U2927 ( .A(n3485), .B(n1560), .Y(n3074) );
NOR2X1TS U2928 ( .A(n3074), .B(Add_Subt_result[47]), .Y(n1520) );
NAND2X2TS U2929 ( .A(n3075), .B(n1520), .Y(n3066) );
NOR2X4TS U2930 ( .A(n3066), .B(n1360), .Y(n2998) );
NAND2X2TS U2931 ( .A(n2998), .B(n3484), .Y(n1559) );
NOR2X1TS U2932 ( .A(Add_Subt_result[40]), .B(Add_Subt_result[39]), .Y(n1558)
);
INVX2TS U2933 ( .A(n1558), .Y(n3133) );
NOR2X1TS U2934 ( .A(Add_Subt_result[38]), .B(Add_Subt_result[37]), .Y(n1536)
);
NAND2X1TS U2935 ( .A(n1536), .B(n1521), .Y(n1523) );
NOR2X1TS U2936 ( .A(Add_Subt_result[36]), .B(Add_Subt_result[35]), .Y(n1539)
);
NAND2X1TS U2937 ( .A(n3046), .B(n1539), .Y(n1522) );
NOR2X1TS U2938 ( .A(n1523), .B(n1522), .Y(n1524) );
NAND2X4TS U2939 ( .A(n3052), .B(n1524), .Y(n3022) );
NOR2X4TS U2940 ( .A(n3022), .B(n1525), .Y(n1543) );
INVX2TS U2941 ( .A(n1533), .Y(n3073) );
NOR2X1TS U2942 ( .A(Add_Subt_result[24]), .B(Add_Subt_result[25]), .Y(n1527)
);
INVX2TS U2943 ( .A(n1550), .Y(n3068) );
INVX2TS U2944 ( .A(n1552), .Y(n1526) );
NOR2X1TS U2945 ( .A(Add_Subt_result[21]), .B(Add_Subt_result[22]), .Y(n1551)
);
INVX2TS U2946 ( .A(n1527), .Y(n1528) );
NOR3X1TS U2947 ( .A(n1528), .B(Add_Subt_result[26]), .C(Add_Subt_result[21]),
.Y(n1531) );
NOR2X1TS U2948 ( .A(Add_Subt_result[18]), .B(Add_Subt_result[17]), .Y(n1568)
);
INVX2TS U2949 ( .A(n1568), .Y(n1529) );
NOR2X4TS U2950 ( .A(n1533), .B(n1532), .Y(n3109) );
NOR2X1TS U2951 ( .A(Add_Subt_result[14]), .B(Add_Subt_result[13]), .Y(n3011)
);
NOR2X4TS U2952 ( .A(n1553), .B(Add_Subt_result[12]), .Y(n3072) );
NOR2X1TS U2953 ( .A(Add_Subt_result[10]), .B(Add_Subt_result[11]), .Y(n1534)
);
NAND2X4TS U2954 ( .A(n3072), .B(n1534), .Y(n3064) );
NAND2X1TS U2955 ( .A(n1549), .B(n3541), .Y(n1535) );
NOR2X4TS U2956 ( .A(n3064), .B(n1535), .Y(n3110) );
NAND2X4TS U2957 ( .A(n3110), .B(n3467), .Y(n2999) );
NOR3X2TS U2958 ( .A(n2999), .B(Add_Subt_result[5]), .C(Add_Subt_result[4]),
.Y(n3006) );
NAND2X2TS U2959 ( .A(n3006), .B(n3468), .Y(n3104) );
NOR2X1TS U2960 ( .A(Add_Subt_result[2]), .B(Add_Subt_result[1]), .Y(n3061)
);
INVX2TS U2961 ( .A(n3112), .Y(n1546) );
INVX2TS U2962 ( .A(n1536), .Y(n3051) );
NOR2X1TS U2963 ( .A(n1559), .B(n3051), .Y(n1541) );
NAND2X1TS U2964 ( .A(n1541), .B(n1537), .Y(n3050) );
NOR2X2TS U2965 ( .A(n3050), .B(Add_Subt_result[35]), .Y(n3020) );
NAND2X1TS U2966 ( .A(n3020), .B(n1538), .Y(n3048) );
AOI22X1TS U2967 ( .A0(n1543), .A1(n1542), .B0(n1541), .B1(n1540), .Y(n1544)
);
AOI211X1TS U2968 ( .A0(n3068), .A1(n1547), .B0(n1546), .C0(n1545), .Y(n3060)
);
AOI211X1TS U2969 ( .A0(n3559), .A1(n3468), .B0(n2999), .C0(
Add_Subt_result[5]), .Y(n1556) );
NOR2XLTS U2970 ( .A(Add_Subt_result[9]), .B(Add_Subt_result[10]), .Y(n1548)
);
AOI211X1TS U2971 ( .A0(n1548), .A1(Add_Subt_result[8]), .B0(
Add_Subt_result[12]), .C0(Add_Subt_result[11]), .Y(n1554) );
NOR2X2TS U2972 ( .A(n1550), .B(Add_Subt_result[23]), .Y(n3058) );
AND3X2TS U2973 ( .A(n3058), .B(n1552), .C(n1551), .Y(n3132) );
NAND3X1TS U2974 ( .A(n3132), .B(n3106), .C(Add_Subt_result[15]), .Y(n3145)
);
OAI211X1TS U2975 ( .A0(n1554), .A1(n1553), .B0(n3069), .C0(n3145), .Y(n1555)
);
NOR2X1TS U2976 ( .A(n1556), .B(n1555), .Y(n3114) );
CLKINVX1TS U2977 ( .A(n3022), .Y(n3049) );
NAND2X1TS U2978 ( .A(n3049), .B(Add_Subt_result[28]), .Y(n3013) );
OAI31X1TS U2979 ( .A0(n3598), .A1(Add_Subt_result[49]), .A2(
Add_Subt_result[50]), .B0(n1557), .Y(n1564) );
NOR2XLTS U2980 ( .A(n1559), .B(n1558), .Y(n1563) );
INVX2TS U2981 ( .A(n3075), .Y(n3138) );
AOI21X1TS U2982 ( .A0(n3595), .A1(n1561), .B0(n3138), .Y(n1562) );
AOI211X1TS U2983 ( .A0(n1565), .A1(n1564), .B0(n1563), .C0(n1562), .Y(n1566)
);
AOI31X1TS U2984 ( .A0(n3060), .A1(n3114), .A2(n1569), .B0(n3151), .Y(n1570)
);
BUFX3TS U2985 ( .A(n2209), .Y(n2270) );
AOI22X1TS U2986 ( .A0(n2271), .A1(intDY[35]), .B0(DMP[35]), .B1(n2270), .Y(
n1571) );
BUFX3TS U2987 ( .A(n2209), .Y(n2267) );
AOI22X1TS U2988 ( .A0(n2271), .A1(intDY[31]), .B0(DMP[31]), .B1(n2267), .Y(
n1572) );
AOI22X1TS U2989 ( .A0(n2271), .A1(intDY[33]), .B0(DMP[33]), .B1(n2270), .Y(
n1573) );
NOR2X4TS U2990 ( .A(n1713), .B(n3448), .Y(n1721) );
NAND2X1TS U2991 ( .A(n1721), .B(FSM_selector_C), .Y(n1576) );
NAND2X1TS U2992 ( .A(n1712), .B(n3122), .Y(n1575) );
INVX2TS U2993 ( .A(n1721), .Y(n1579) );
AOI21X1TS U2994 ( .A0(n3450), .A1(n3448), .B0(n3481), .Y(n1578) );
NAND2X1TS U2995 ( .A(n1713), .B(n3519), .Y(n1577) );
OAI211X1TS U2996 ( .A0(FSM_selector_C), .A1(n1579), .B0(n1578), .C0(n1577),
.Y(n1580) );
XOR2X1TS U2997 ( .A(n1354), .B(n1581), .Y(n1628) );
XOR2X1TS U2998 ( .A(n1354), .B(n1582), .Y(n1631) );
XOR2X1TS U2999 ( .A(n1354), .B(n1583), .Y(n1618) );
XOR2X1TS U3000 ( .A(n1354), .B(n1584), .Y(n1621) );
XOR2X1TS U3001 ( .A(n1354), .B(n1585), .Y(n1624) );
NOR2X4TS U3002 ( .A(n3482), .B(FSM_selector_B[1]), .Y(n1592) );
NAND2X1TS U3003 ( .A(n1592), .B(LZA_output[5]), .Y(n1851) );
OAI2BB1X1TS U3004 ( .A0N(DmP[57]), .A1N(n1842), .B0(n1851), .Y(n1586) );
XOR2X1TS U3005 ( .A(n1354), .B(n1586), .Y(n1608) );
OAI2BB1X1TS U3006 ( .A0N(DmP[56]), .A1N(n1849), .B0(n1844), .Y(n1587) );
XOR2X1TS U3007 ( .A(n1354), .B(n1587), .Y(n1611) );
OAI2BB1X1TS U3008 ( .A0N(DmP[55]), .A1N(n1842), .B0(n1841), .Y(n1588) );
NAND2X1TS U3009 ( .A(n1592), .B(LZA_output[2]), .Y(n1752) );
OAI2BB1X1TS U3010 ( .A0N(DmP[54]), .A1N(n1849), .B0(n1752), .Y(n1589) );
XOR2X1TS U3011 ( .A(n1353), .B(n1589), .Y(n1599) );
NAND2X1TS U3012 ( .A(n1592), .B(LZA_output[1]), .Y(n1760) );
OAI2BB1X1TS U3013 ( .A0N(DmP[53]), .A1N(n1842), .B0(n1760), .Y(n1590) );
XOR2X1TS U3014 ( .A(n1353), .B(n1590), .Y(n1602) );
NAND2X1TS U3015 ( .A(n3482), .B(FSM_selector_B[1]), .Y(n1593) );
XOR2X4TS U3016 ( .A(n1353), .B(n1595), .Y(n1603) );
ADDFHX4TS U3017 ( .A(n1599), .B(n1598), .CI(n1597), .CO(n1612), .S(n3034) );
ADDFHX4TS U3018 ( .A(n1602), .B(n1601), .CI(n1600), .CO(n1597), .S(n3045) );
NOR4BX1TS U3019 ( .AN(n1833), .B(n3034), .C(n3045), .D(n1723), .Y(n1615) );
CMPR32X2TS U3020 ( .A(n1608), .B(n1607), .C(n1606), .CO(n1622), .S(n3117) );
NOR4BX1TS U3021 ( .AN(n1615), .B(n3117), .C(n3063), .D(n3083), .Y(n1625) );
ADDFHX4TS U3022 ( .A(n1618), .B(n1617), .CI(n1616), .CO(n1629), .S(n3129) );
CMPR32X2TS U3023 ( .A(n1624), .B(n1623), .C(n1622), .CO(n1619), .S(n3131) );
NOR4BX1TS U3024 ( .AN(n1625), .B(n3129), .C(n3130), .D(n3131), .Y(n1632) );
ADDFHX4TS U3025 ( .A(n1631), .B(n1630), .CI(n1629), .CO(n1626), .S(n3128) );
NAND2X2TS U3026 ( .A(n1635), .B(n3448), .Y(n478) );
AOI22X1TS U3027 ( .A0(n3548), .A1(intDY[38]), .B0(n3553), .B1(intDY[25]),
.Y(n1636) );
AOI221X1TS U3028 ( .A0(intDX[24]), .A1(n3464), .B0(n3555), .B1(intDY[24]),
.C0(n1637), .Y(n1651) );
OAI22X1TS U3029 ( .A0(n3570), .A1(intDY[28]), .B0(n3565), .B1(intDY[29]),
.Y(n1638) );
OAI22X1TS U3030 ( .A0(n3569), .A1(intDY[20]), .B0(n3564), .B1(intDY[21]),
.Y(n1639) );
AOI22X1TS U3031 ( .A0(n3533), .A1(intDY[16]), .B0(n3552), .B1(intDY[17]),
.Y(n1640) );
AOI22X1TS U3032 ( .A0(n3551), .A1(intDY[31]), .B0(n3463), .B1(intDY[30]),
.Y(n1641) );
AOI22X1TS U3033 ( .A0(n3547), .A1(intDY[43]), .B0(n3491), .B1(intDX[23]),
.Y(n1642) );
AOI22X1TS U3034 ( .A0(n3550), .A1(intDY[18]), .B0(n3462), .B1(intDY[19]),
.Y(n1643) );
NOR4X1TS U3035 ( .A(n1647), .B(n1646), .C(n1645), .D(n1644), .Y(n1648) );
OAI22X1TS U3036 ( .A0(n3465), .A1(intDY[7]), .B0(n3562), .B1(intDY[1]), .Y(
n1652) );
AOI221X1TS U3037 ( .A0(n3465), .A1(intDY[7]), .B0(intDY[1]), .B1(n3562),
.C0(n1652), .Y(n1659) );
OAI22X1TS U3038 ( .A0(n3568), .A1(intDY[13]), .B0(n3563), .B1(intDY[4]), .Y(
n1653) );
AOI221X1TS U3039 ( .A0(n3568), .A1(intDY[13]), .B0(intDY[4]), .B1(n3563),
.C0(n1653), .Y(n1658) );
OAI22X1TS U3040 ( .A0(n3471), .A1(intDY[0]), .B0(n3575), .B1(intDY[40]), .Y(
n1655) );
OAI22X1TS U3041 ( .A0(n3573), .A1(intDY[15]), .B0(n3469), .B1(intDY[14]),
.Y(n1660) );
AOI221X1TS U3042 ( .A0(n3573), .A1(intDY[15]), .B0(intDY[14]), .B1(n3469),
.C0(n1660), .Y(n1667) );
OAI22X1TS U3043 ( .A0(n3470), .A1(intDY[22]), .B0(n3567), .B1(intDY[12]),
.Y(n1661) );
OAI22X1TS U3044 ( .A0(n3572), .A1(intDY[3]), .B0(n3566), .B1(intDY[2]), .Y(
n1662) );
OAI22X1TS U3045 ( .A0(n3571), .A1(intDY[9]), .B0(n3466), .B1(intDY[6]), .Y(
n1663) );
AOI22X1TS U3046 ( .A0(n3549), .A1(intDY[11]), .B0(n3536), .B1(intDY[10]),
.Y(n1668) );
AOI22X1TS U3047 ( .A0(n3523), .A1(intDY[53]), .B0(n2230), .B1(intDY[60]),
.Y(n1669) );
AOI22X1TS U3048 ( .A0(n3455), .A1(intDY[55]), .B0(n3530), .B1(intDY[54]),
.Y(n1670) );
AOI22X1TS U3049 ( .A0(n3522), .A1(intDY[49]), .B0(n3539), .B1(intDY[8]), .Y(
n1671) );
NOR4X1TS U3050 ( .A(n1675), .B(n1674), .C(n1673), .D(n1672), .Y(n1703) );
AOI22X1TS U3051 ( .A0(n3546), .A1(intDY[51]), .B0(n3459), .B1(intDY[50]),
.Y(n1676) );
AOI22X1TS U3052 ( .A0(n3524), .A1(intDY[61]), .B0(n3461), .B1(intDY[5]), .Y(
n1677) );
OAI221XLTS U3053 ( .A0(n3524), .A1(intDY[61]), .B0(n3461), .B1(intDY[5]),
.C0(n1677), .Y(n1682) );
AOI22X1TS U3054 ( .A0(n3525), .A1(intDY[62]), .B0(n3444), .B1(intDY[57]),
.Y(n1678) );
AOI22X1TS U3055 ( .A0(n3456), .A1(intDY[56]), .B0(n3528), .B1(intDY[48]),
.Y(n1679) );
NOR4X1TS U3056 ( .A(n1683), .B(n1682), .C(n1681), .D(n1680), .Y(n1702) );
AOI22X1TS U3057 ( .A0(n2253), .A1(intDY[58]), .B0(n3535), .B1(intDY[37]),
.Y(n1684) );
AOI22X1TS U3058 ( .A0(n3538), .A1(intDY[36]), .B0(n3527), .B1(intDY[47]),
.Y(n1685) );
AOI22X1TS U3059 ( .A0(n3537), .A1(intDY[33]), .B0(n3556), .B1(intDY[39]),
.Y(n1686) );
AOI22X1TS U3060 ( .A0(n3534), .A1(intDY[32]), .B0(n3545), .B1(intDY[59]),
.Y(n1687) );
NOR4X1TS U3061 ( .A(n1691), .B(n1690), .C(n1689), .D(n1688), .Y(n1701) );
AOI22X1TS U3062 ( .A0(n3460), .A1(intDY[34]), .B0(n3526), .B1(intDY[45]),
.Y(n1692) );
AOI22X1TS U3063 ( .A0(n3454), .A1(intDY[44]), .B0(n3529), .B1(intDY[52]),
.Y(n1693) );
OAI221XLTS U3064 ( .A0(n3454), .A1(intDY[44]), .B0(n3529), .B1(intDY[52]),
.C0(n1693), .Y(n1698) );
AOI22X1TS U3065 ( .A0(n3521), .A1(intDY[46]), .B0(n3458), .B1(intDY[42]),
.Y(n1694) );
AOI22X1TS U3066 ( .A0(n3520), .A1(intDY[41]), .B0(n3540), .B1(intDY[35]),
.Y(n1695) );
NOR4X1TS U3067 ( .A(n1699), .B(n1698), .C(n1697), .D(n1696), .Y(n1700) );
NOR4X2TS U3068 ( .A(n1707), .B(n1706), .C(n1705), .D(n1704), .Y(n2159) );
XNOR2X4TS U3069 ( .A(intDY[63]), .B(intAS), .Y(n2162) );
XOR2X4TS U3070 ( .A(n2162), .B(n3486), .Y(n2374) );
AOI21X1TS U3071 ( .A0(n2159), .A1(n2374), .B0(n2296), .Y(n1716) );
NOR2X1TS U3072 ( .A(n3448), .B(n3450), .Y(n1708) );
INVX2TS U3073 ( .A(n1857), .Y(n1709) );
NAND2X1TS U3074 ( .A(n1709), .B(FSM_selector_C), .Y(n1710) );
NAND2X1TS U3075 ( .A(n1714), .B(n3122), .Y(n1743) );
NOR2X1TS U3076 ( .A(FS_Module_state_reg[1]), .B(FS_Module_state_reg[2]), .Y(
n1711) );
NAND2X2TS U3077 ( .A(n1712), .B(n1711), .Y(n3118) );
NAND3X1TS U3078 ( .A(FS_Module_state_reg[1]), .B(FS_Module_state_reg[2]),
.C(n1714), .Y(n1832) );
OAI22X2TS U3079 ( .A0(ack_FSM), .A1(n1832), .B0(beg_FSM), .B1(n478), .Y(
n3123) );
OA22X1TS U3080 ( .A0(r_mode[0]), .A1(n3472), .B0(Sgf_normalized_result[1]),
.B1(Sgf_normalized_result[0]), .Y(n1718) );
NAND2X1TS U3081 ( .A(r_mode[0]), .B(r_mode[1]), .Y(n1717) );
NOR2BX2TS U3082 ( .AN(n3127), .B(n1726), .Y(n1729) );
NAND2X1TS U3083 ( .A(n1341), .B(overflow_flag), .Y(n1727) );
CLKBUFX3TS U3084 ( .A(n1732), .Y(n1734) );
BUFX3TS U3085 ( .A(n1734), .Y(n3621) );
BUFX3TS U3086 ( .A(n1732), .Y(n3623) );
BUFX3TS U3087 ( .A(n1734), .Y(n3655) );
CLKBUFX3TS U3088 ( .A(n1732), .Y(n1730) );
BUFX3TS U3089 ( .A(n1730), .Y(n3652) );
BUFX3TS U3090 ( .A(n1730), .Y(n3650) );
CLKBUFX3TS U3091 ( .A(n1734), .Y(n3656) );
CLKBUFX3TS U3092 ( .A(n1732), .Y(n1731) );
BUFX3TS U3093 ( .A(n1731), .Y(n3633) );
BUFX3TS U3094 ( .A(n1731), .Y(n3632) );
BUFX3TS U3095 ( .A(n1732), .Y(n3614) );
BUFX3TS U3096 ( .A(n1732), .Y(n3613) );
BUFX3TS U3097 ( .A(n1731), .Y(n3616) );
BUFX3TS U3098 ( .A(n1730), .Y(n3647) );
BUFX3TS U3099 ( .A(n1731), .Y(n3612) );
BUFX3TS U3100 ( .A(n1734), .Y(n3609) );
BUFX3TS U3101 ( .A(n1730), .Y(n3610) );
CLKBUFX3TS U3102 ( .A(n1732), .Y(n1735) );
BUFX3TS U3103 ( .A(n1735), .Y(n3611) );
BUFX3TS U3104 ( .A(n1732), .Y(n3617) );
CLKBUFX3TS U3105 ( .A(n1732), .Y(n1733) );
BUFX3TS U3106 ( .A(n1733), .Y(n3642) );
BUFX3TS U3107 ( .A(n1730), .Y(n3651) );
BUFX3TS U3108 ( .A(n1730), .Y(n3622) );
BUFX3TS U3109 ( .A(n1734), .Y(n3615) );
BUFX3TS U3110 ( .A(n1730), .Y(n3649) );
BUFX3TS U3111 ( .A(n1733), .Y(n3641) );
BUFX3TS U3112 ( .A(n1734), .Y(n3608) );
BUFX3TS U3113 ( .A(n1734), .Y(n3654) );
BUFX3TS U3114 ( .A(n1733), .Y(n3644) );
BUFX3TS U3115 ( .A(n1731), .Y(n3634) );
BUFX3TS U3116 ( .A(n1731), .Y(n3631) );
BUFX3TS U3117 ( .A(n1733), .Y(n3643) );
BUFX3TS U3118 ( .A(n1735), .Y(n3639) );
BUFX3TS U3119 ( .A(n1730), .Y(n3648) );
BUFX3TS U3120 ( .A(n1731), .Y(n3630) );
BUFX3TS U3121 ( .A(n1735), .Y(n3637) );
BUFX3TS U3122 ( .A(n1730), .Y(n3627) );
BUFX3TS U3123 ( .A(n1731), .Y(n3629) );
BUFX3TS U3124 ( .A(n1731), .Y(n3626) );
BUFX3TS U3125 ( .A(n1734), .Y(n3624) );
BUFX3TS U3126 ( .A(n1735), .Y(n3638) );
BUFX3TS U3127 ( .A(n1733), .Y(n3628) );
BUFX3TS U3128 ( .A(n1735), .Y(n3640) );
BUFX3TS U3129 ( .A(n1735), .Y(n3635) );
BUFX3TS U3130 ( .A(n1735), .Y(n3620) );
BUFX3TS U3131 ( .A(n1735), .Y(n3636) );
BUFX3TS U3132 ( .A(n1733), .Y(n3645) );
BUFX3TS U3133 ( .A(n1732), .Y(n3618) );
BUFX3TS U3134 ( .A(n1733), .Y(n3606) );
BUFX3TS U3135 ( .A(n1733), .Y(n3646) );
BUFX3TS U3136 ( .A(n1733), .Y(n3619) );
BUFX3TS U3137 ( .A(n1734), .Y(n3653) );
BUFX3TS U3138 ( .A(n1734), .Y(n3607) );
BUFX3TS U3139 ( .A(n1735), .Y(n3625) );
OR2X2TS U3140 ( .A(n1753), .B(n1363), .Y(n2876) );
OAI21XLTS U3141 ( .A0(n2876), .A1(FS_Module_state_reg[0]), .B0(n3489), .Y(
n465) );
INVX2TS U3142 ( .A(n3151), .Y(n3146) );
AOI22X1TS U3143 ( .A0(n3146), .A1(add_overflow_flag), .B0(FSM_selector_B[1]),
.B1(n3033), .Y(n1736) );
NAND2X1TS U3144 ( .A(n1736), .B(n1743), .Y(n131) );
BUFX3TS U3145 ( .A(n3441), .Y(n3439) );
INVX2TS U3146 ( .A(n3429), .Y(n3427) );
INVX2TS U3147 ( .A(n3429), .Y(n3428) );
BUFX3TS U3148 ( .A(n3441), .Y(n3435) );
INVX2TS U3149 ( .A(n3429), .Y(n3434) );
BUFX3TS U3150 ( .A(n3441), .Y(n3433) );
INVX2TS U3151 ( .A(n3429), .Y(n3432) );
INVX2TS U3152 ( .A(n3429), .Y(n3436) );
BUFX3TS U3153 ( .A(n3441), .Y(n3445) );
OAI2BB2XLTS U3154 ( .B0(n3445), .B1(n3545), .A0N(n3446), .A1N(Data_X[59]),
.Y(n403) );
OAI2BB2XLTS U3155 ( .B0(n3445), .B1(n2253), .A0N(n3446), .A1N(Data_X[58]),
.Y(n402) );
OAI2BB2XLTS U3156 ( .B0(n3445), .B1(n2230), .A0N(n3446), .A1N(Data_X[60]),
.Y(n404) );
BUFX3TS U3157 ( .A(n3426), .Y(n3422) );
NOR2X1TS U3158 ( .A(n1857), .B(FSM_selector_C), .Y(n1748) );
NAND2X1TS U3159 ( .A(n1746), .B(n1745), .Y(n468) );
INVX2TS U3160 ( .A(n3123), .Y(n1750) );
NOR3X1TS U3161 ( .A(n1340), .B(n1748), .C(n1747), .Y(n1749) );
NAND2X1TS U3162 ( .A(n1849), .B(exp_oper_result[2]), .Y(n1751) );
BUFX3TS U3163 ( .A(n3256), .Y(n1942) );
INVX2TS U3164 ( .A(n1753), .Y(n1755) );
BUFX3TS U3165 ( .A(n1894), .Y(n3395) );
NAND2X1TS U3166 ( .A(n3395), .B(Add_Subt_result[35]), .Y(n1758) );
BUFX3TS U3167 ( .A(n3394), .Y(n1808) );
BUFX3TS U3168 ( .A(n3489), .Y(n1807) );
AOI22X1TS U3169 ( .A0(n1808), .A1(Add_Subt_result[19]), .B0(DmP[33]), .B1(
n1807), .Y(n1757) );
NAND2X1TS U3170 ( .A(n1758), .B(n1757), .Y(n1821) );
NAND2X1TS U3171 ( .A(n1849), .B(exp_oper_result[1]), .Y(n1759) );
AOI21X4TS U3172 ( .A0(exp_oper_result[0]), .A1(n3482), .B0(n1762), .Y(n1939)
);
NAND2X1TS U3173 ( .A(n1821), .B(n3199), .Y(n1769) );
NAND2X1TS U3174 ( .A(n3395), .B(Add_Subt_result[37]), .Y(n1764) );
AOI22X1TS U3175 ( .A0(n1808), .A1(Add_Subt_result[17]), .B0(DmP[35]), .B1(
n1807), .Y(n1763) );
NAND2X2TS U3176 ( .A(n1764), .B(n1763), .Y(n3232) );
NAND2X1TS U3177 ( .A(n3232), .B(n3210), .Y(n1768) );
NAND2X1TS U3178 ( .A(n3395), .B(Add_Subt_result[36]), .Y(n1766) );
AOI22X1TS U3179 ( .A0(n1808), .A1(Add_Subt_result[18]), .B0(DmP[34]), .B1(
n1807), .Y(n1765) );
NAND2X2TS U3180 ( .A(n1766), .B(n1765), .Y(n1826) );
NAND2X1TS U3181 ( .A(n1826), .B(n3207), .Y(n1767) );
INVX2TS U3182 ( .A(n1787), .Y(n3240) );
AOI22X1TS U3183 ( .A0(n1808), .A1(Add_Subt_result[22]), .B0(DmP[30]), .B1(
n1807), .Y(n1770) );
OAI2BB1X2TS U3184 ( .A0N(Add_Subt_result[32]), .A1N(n1894), .B0(n1770), .Y(
n1897) );
BUFX3TS U3185 ( .A(n3394), .Y(n1977) );
BUFX3TS U3186 ( .A(n3489), .Y(n3375) );
AOI22X1TS U3187 ( .A0(n1977), .A1(Add_Subt_result[23]), .B0(DmP[29]), .B1(
n3375), .Y(n1771) );
AOI22X1TS U3188 ( .A0(n1808), .A1(Add_Subt_result[21]), .B0(DmP[31]), .B1(
n1807), .Y(n1773) );
OAI2BB1X2TS U3189 ( .A0N(Add_Subt_result[33]), .A1N(n1894), .B0(n1773), .Y(
n1941) );
AOI222X1TS U3190 ( .A0(n1897), .A1(n3207), .B0(n1823), .B1(n3209), .C0(n1941), .C1(n3210), .Y(n1886) );
NOR2X4TS U3191 ( .A(n1761), .B(n1939), .Y(n3191) );
INVX2TS U3192 ( .A(n3268), .Y(n3214) );
NAND2X1TS U3193 ( .A(n3395), .B(Add_Subt_result[34]), .Y(n1775) );
AOI22X1TS U3194 ( .A0(n1808), .A1(Add_Subt_result[20]), .B0(DmP[32]), .B1(
n1807), .Y(n1774) );
NAND2X2TS U3195 ( .A(n1775), .B(n1774), .Y(n1883) );
NAND2X2TS U3196 ( .A(n3191), .B(n2114), .Y(n3276) );
NAND2X1TS U3197 ( .A(n3395), .B(Add_Subt_result[38]), .Y(n1777) );
AOI22X1TS U3198 ( .A0(n1808), .A1(Add_Subt_result[16]), .B0(DmP[36]), .B1(
n1807), .Y(n1776) );
NAND2X2TS U3199 ( .A(n1777), .B(n1776), .Y(n3227) );
AOI22X1TS U3200 ( .A0(n3253), .A1(n1883), .B0(n3270), .B1(n3227), .Y(n1778)
);
OAI221XLTS U3201 ( .A0(n1942), .A1(n3229), .B0(n3240), .B1(n1886), .C0(n1778), .Y(Barrel_Shifter_module_Mux_Array_Data_array[31]) );
INVX2TS U3202 ( .A(n1824), .Y(n3200) );
AOI222X1TS U3203 ( .A0(n1883), .A1(n1347), .B0(n1941), .B1(n3209), .C0(n1821), .C1(n3200), .Y(n1791) );
AOI22X1TS U3204 ( .A0(n1977), .A1(Add_Subt_result[24]), .B0(DmP[28]), .B1(
n3375), .Y(n1779) );
OAI2BB1X2TS U3205 ( .A0N(Add_Subt_result[30]), .A1N(n1894), .B0(n1779), .Y(
n1967) );
AOI22X1TS U3206 ( .A0(n1977), .A1(Add_Subt_result[25]), .B0(DmP[27]), .B1(
n3375), .Y(n1780) );
OAI2BB1X2TS U3207 ( .A0N(Add_Subt_result[29]), .A1N(n1894), .B0(n1780), .Y(
n3238) );
AOI222X1TS U3208 ( .A0(n1967), .A1(n3207), .B0(n3238), .B1(n3209), .C0(n1823), .C1(n3210), .Y(n1900) );
AOI22X1TS U3209 ( .A0(n3368), .A1(n1897), .B0(n3270), .B1(n1826), .Y(n1781)
);
OAI221XLTS U3210 ( .A0(n1942), .A1(n1791), .B0(n3240), .B1(n1900), .C0(n1781), .Y(Barrel_Shifter_module_Mux_Array_Data_array[29]) );
NAND2X1TS U3211 ( .A(n3232), .B(n3199), .Y(n1786) );
NAND2X1TS U3212 ( .A(n3227), .B(n1347), .Y(n1785) );
BUFX3TS U3213 ( .A(n1894), .Y(n1927) );
NAND2X1TS U3214 ( .A(n1927), .B(Add_Subt_result[39]), .Y(n1783) );
AOI22X1TS U3215 ( .A0(n1808), .A1(Add_Subt_result[15]), .B0(DmP[37]), .B1(
n1807), .Y(n1782) );
NAND2X1TS U3216 ( .A(n1783), .B(n1782), .Y(n3208) );
NAND2X1TS U3217 ( .A(n3208), .B(n3200), .Y(n1784) );
INVX2TS U3218 ( .A(n1787), .Y(n3235) );
NAND2X1TS U3219 ( .A(n3395), .B(Add_Subt_result[40]), .Y(n1789) );
AOI22X1TS U3220 ( .A0(n1808), .A1(Add_Subt_result[14]), .B0(DmP[38]), .B1(
n1807), .Y(n1788) );
NAND2X2TS U3221 ( .A(n1789), .B(n1788), .Y(n3219) );
AOI22X1TS U3222 ( .A0(n3352), .A1(n1826), .B0(n3270), .B1(n3219), .Y(n1790)
);
OAI221XLTS U3223 ( .A0(n1942), .A1(n3221), .B0(n3235), .B1(n1791), .C0(n1790), .Y(Barrel_Shifter_module_Mux_Array_Data_array[33]) );
NAND2X1TS U3224 ( .A(n1883), .B(n3209), .Y(n1794) );
NAND2X1TS U3225 ( .A(n1821), .B(n1347), .Y(n1793) );
NAND2X1TS U3226 ( .A(n1826), .B(n3200), .Y(n1792) );
AOI222X1TS U3227 ( .A0(n1823), .A1(n1347), .B0(n1967), .B1(n3199), .C0(n1897), .C1(n3200), .Y(n1945) );
AOI22X1TS U3228 ( .A0(n3408), .A1(n3232), .B0(n3411), .B1(n1941), .Y(n1795)
);
OAI221XLTS U3229 ( .A0(n1942), .A1(n3234), .B0(n3240), .B1(n1945), .C0(n1795), .Y(Barrel_Shifter_module_Mux_Array_Data_array[30]) );
NAND2X1TS U3230 ( .A(n1927), .B(Add_Subt_result[46]), .Y(n1797) );
BUFX3TS U3231 ( .A(n3394), .Y(n1929) );
BUFX3TS U3232 ( .A(n3489), .Y(n1928) );
AOI22X1TS U3233 ( .A0(n1929), .A1(Add_Subt_result[8]), .B0(DmP[44]), .B1(
n1928), .Y(n1796) );
NAND2X2TS U3234 ( .A(n1797), .B(n1796), .Y(n3204) );
NAND2X1TS U3235 ( .A(n3204), .B(n1347), .Y(n1804) );
NAND2X1TS U3236 ( .A(n1927), .B(Add_Subt_result[45]), .Y(n1799) );
AOI22X1TS U3237 ( .A0(n1929), .A1(Add_Subt_result[9]), .B0(DmP[43]), .B1(
n1928), .Y(n1798) );
NAND2X2TS U3238 ( .A(n1799), .B(n1798), .Y(n3215) );
NAND2X1TS U3239 ( .A(n3215), .B(n2097), .Y(n1803) );
NAND2X1TS U3240 ( .A(n1927), .B(Add_Subt_result[47]), .Y(n1801) );
AOI22X1TS U3241 ( .A0(n1929), .A1(Add_Subt_result[7]), .B0(DmP[45]), .B1(
n1928), .Y(n1800) );
NAND2X2TS U3242 ( .A(n1801), .B(n1800), .Y(n3183) );
NAND2X1TS U3243 ( .A(n3183), .B(n3200), .Y(n1802) );
NAND2X1TS U3244 ( .A(n1927), .B(Add_Subt_result[42]), .Y(n1806) );
AOI22X1TS U3245 ( .A0(n1929), .A1(Add_Subt_result[12]), .B0(DmP[40]), .B1(
n1928), .Y(n1805) );
NAND2X2TS U3246 ( .A(n1806), .B(n1805), .Y(n3226) );
NAND2X1TS U3247 ( .A(n3226), .B(n1347), .Y(n1815) );
NAND2X1TS U3248 ( .A(n3395), .B(Add_Subt_result[41]), .Y(n1810) );
AOI22X1TS U3249 ( .A0(n1808), .A1(Add_Subt_result[13]), .B0(DmP[39]), .B1(
n1807), .Y(n1809) );
NAND2X2TS U3250 ( .A(n1810), .B(n1809), .Y(n3231) );
NAND2X1TS U3251 ( .A(n3231), .B(n3199), .Y(n1814) );
NAND2X1TS U3252 ( .A(n1927), .B(Add_Subt_result[43]), .Y(n1812) );
AOI22X1TS U3253 ( .A0(n1929), .A1(Add_Subt_result[11]), .B0(DmP[41]), .B1(
n1928), .Y(n1811) );
NAND2X1TS U3254 ( .A(n1812), .B(n1811), .Y(n3192) );
NAND2X1TS U3255 ( .A(n3192), .B(n3210), .Y(n1813) );
OAI22X1TS U3256 ( .A0(n1859), .A1(n3467), .B0(FSM_selector_C), .B1(n3601),
.Y(n1816) );
INVX2TS U3257 ( .A(n3167), .Y(n3184) );
NAND2X1TS U3258 ( .A(n1927), .B(Add_Subt_result[44]), .Y(n1819) );
AOI22X1TS U3259 ( .A0(n1929), .A1(Add_Subt_result[10]), .B0(DmP[42]), .B1(
n1928), .Y(n1818) );
NAND2X2TS U3260 ( .A(n1819), .B(n1818), .Y(n3218) );
AOI22X1TS U3261 ( .A0(n3354), .A1(n3184), .B0(n3411), .B1(n3218), .Y(n1820)
);
OAI221XLTS U3262 ( .A0(n1942), .A1(n1974), .B0(n3240), .B1(n3222), .C0(n1820), .Y(Barrel_Shifter_module_Mux_Array_Data_array[41]) );
AOI222X1TS U3263 ( .A0(n1941), .A1(n3207), .B0(n1897), .B1(n3199), .C0(n1821), .C1(n3191), .Y(n1831) );
AOI22X1TS U3264 ( .A0(n1977), .A1(Add_Subt_result[26]), .B0(DmP[26]), .B1(
n3375), .Y(n1822) );
AOI222X1TS U3265 ( .A0(n3238), .A1(n1347), .B0(n3239), .B1(n3199), .C0(n1823), .C1(n3191), .Y(n1951) );
OR2X2TS U3266 ( .A(n1824), .B(n2114), .Y(n3318) );
INVX2TS U3267 ( .A(n3318), .Y(n3246) );
AOI22X1TS U3268 ( .A0(n3309), .A1(n1883), .B0(n3403), .B1(n1967), .Y(n1825)
);
OAI221XLTS U3269 ( .A0(n1942), .A1(n1831), .B0(n3240), .B1(n1951), .C0(n1825), .Y(Barrel_Shifter_module_Mux_Array_Data_array[28]) );
NAND2X1TS U3270 ( .A(n3232), .B(n1346), .Y(n1829) );
NAND2X1TS U3271 ( .A(n1826), .B(n3209), .Y(n1828) );
NAND2X1TS U3272 ( .A(n3208), .B(n3191), .Y(n1827) );
AOI22X1TS U3273 ( .A0(n3403), .A1(n1883), .B0(n3379), .B1(n3227), .Y(n1830)
);
OAI221XLTS U3274 ( .A0(n1942), .A1(n3224), .B0(n3240), .B1(n1831), .C0(n1830), .Y(Barrel_Shifter_module_Mux_Array_Data_array[32]) );
INVX2TS U3275 ( .A(n1832), .Y(ready) );
NOR2X4TS U3276 ( .A(n1834), .B(n3481), .Y(n1876) );
INVX2TS U3277 ( .A(n1876), .Y(n3170) );
INVX2TS U3278 ( .A(n3191), .Y(n1839) );
INVX2TS U3279 ( .A(n3318), .Y(n3367) );
INVX2TS U3280 ( .A(n3163), .Y(n3175) );
OAI2BB2XLTS U3281 ( .B0(n1859), .B1(n3596), .A0N(DmP[51]), .A1N(n3489), .Y(
n1835) );
AOI21X2TS U3282 ( .A0(n3395), .A1(Add_Subt_result[53]), .B0(n1835), .Y(n3159) );
BUFX3TS U3283 ( .A(n1894), .Y(n3377) );
AOI22X1TS U3284 ( .A0(n1929), .A1(Add_Subt_result[2]), .B0(DmP[50]), .B1(
n1928), .Y(n1836) );
OAI2BB1X2TS U3285 ( .A0N(Add_Subt_result[52]), .A1N(n3377), .B0(n1836), .Y(
n3182) );
INVX2TS U3286 ( .A(n3182), .Y(n3161) );
OAI22X1TS U3287 ( .A0(n3165), .A1(n3159), .B0(n3161), .B1(n3166), .Y(n1837)
);
AOI21X1TS U3288 ( .A0(n3403), .A1(n3175), .B0(n1837), .Y(n1838) );
NAND2X2TS U3289 ( .A(n1876), .B(n2114), .Y(n3086) );
INVX2TS U3290 ( .A(n1854), .Y(n1845) );
NAND2X2TS U3291 ( .A(n1845), .B(n1853), .Y(n1846) );
NAND2BX2TS U3292 ( .AN(n1853), .B(n1854), .Y(n2036) );
INVX4TS U3293 ( .A(n1861), .Y(n2035) );
OAI2BB2XLTS U3294 ( .B0(n2036), .B1(n3590), .A0N(n2035), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[87]), .Y(n1848) );
NOR2X4TS U3295 ( .A(n1854), .B(n1847), .Y(n2325) );
INVX2TS U3296 ( .A(n1879), .Y(n1954) );
BUFX3TS U3297 ( .A(n1852), .Y(n2087) );
NOR2X2TS U3298 ( .A(n1879), .B(n2036), .Y(n2323) );
BUFX3TS U3299 ( .A(n2323), .Y(n2125) );
AOI22X1TS U3300 ( .A0(n2087), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[55]), .B0(n2125), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[71]), .Y(n1856) );
NOR2X4TS U3301 ( .A(n1343), .B(n1879), .Y(n2069) );
INVX2TS U3302 ( .A(n1873), .Y(n1998) );
AOI22X1TS U3303 ( .A0(n2069), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[63]), .B0(n1998), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[79]), .Y(n1855) );
OAI211X1TS U3304 ( .A0(n2368), .A1(n1954), .B0(n1856), .C0(n1855), .Y(n1903)
);
NAND2X2TS U3305 ( .A(n1858), .B(n1857), .Y(n2320) );
BUFX4TS U3306 ( .A(n2320), .Y(n2361) );
AND2X2TS U3307 ( .A(n2361), .B(n1859), .Y(n3095) );
INVX4TS U3308 ( .A(n2361), .Y(n3092) );
BUFX3TS U3309 ( .A(n1954), .Y(n2121) );
INVX2TS U3310 ( .A(n2031), .Y(n1862) );
NAND2X2TS U3311 ( .A(n1862), .B(n1861), .Y(n2030) );
INVX2TS U3312 ( .A(n2361), .Y(n2094) );
AOI222X1TS U3313 ( .A0(n1903), .A1(n3095), .B0(n1348), .B1(n1901), .C0(n2094), .C1(Sgf_normalized_result[0]), .Y(n1863) );
INVX2TS U3314 ( .A(n1863), .Y(n469) );
BUFX3TS U3315 ( .A(n1954), .Y(n2131) );
BUFX3TS U3316 ( .A(n1852), .Y(n2328) );
BUFX3TS U3317 ( .A(n2323), .Y(n2327) );
AOI22X1TS U3318 ( .A0(n2328), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[69]), .B0(n2327), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[85]), .Y(n1867) );
BUFX3TS U3319 ( .A(n2069), .Y(n2321) );
AOI22X1TS U3320 ( .A0(n2321), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[77]), .B0(n1998), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[93]), .Y(n1866) );
OAI211X1TS U3321 ( .A0(n2131), .A1(n2319), .B0(n1867), .C0(n1866), .Y(n1880)
);
AOI22X1TS U3322 ( .A0(n1880), .A1(n3095), .B0(n2134), .B1(
Sgf_normalized_result[14]), .Y(n1868) );
OAI2BB2XLTS U3323 ( .B0(n2036), .B1(n1336), .A0N(n2008), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[90]), .Y(n1869) );
AOI22X1TS U3324 ( .A0(n2069), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[66]), .B0(n1998), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[82]), .Y(n1871) );
BUFX3TS U3325 ( .A(n1852), .Y(n2126) );
BUFX3TS U3326 ( .A(n2323), .Y(n2115) );
AOI22X1TS U3327 ( .A0(n2126), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[58]), .B0(n2115), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[74]), .Y(n1870) );
OAI211X1TS U3328 ( .A0(n2372), .A1(n1954), .B0(n1871), .C0(n1870), .Y(n1906)
);
AOI222X1TS U3329 ( .A0(n1906), .A1(n3095), .B0(n1348), .B1(n1905), .C0(n2094), .C1(Sgf_normalized_result[3]), .Y(n1872) );
INVX2TS U3330 ( .A(n1872), .Y(n39) );
BUFX3TS U3331 ( .A(n1873), .Y(n2330) );
AOI22X1TS U3332 ( .A0(n2328), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[82]), .B0(n2321), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[90]), .Y(n1874) );
AOI21X1TS U3333 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[98]), .A1(
n2115), .B0(n1875), .Y(n1878) );
AOI21X1TS U3334 ( .A0(n2134), .A1(Sgf_normalized_result[27]), .B0(n1339),
.Y(n1877) );
INVX2TS U3335 ( .A(n3095), .Y(n2363) );
OR2X2TS U3336 ( .A(n2363), .B(n1879), .Y(n2074) );
INVX2TS U3337 ( .A(n2074), .Y(n2042) );
AOI21X1TS U3338 ( .A0(n2134), .A1(Sgf_normalized_result[40]), .B0(n1339),
.Y(n1882) );
NAND2X1TS U3339 ( .A(n1880), .B(n2132), .Y(n1881) );
AOI22X1TS U3340 ( .A0(n3368), .A1(n1967), .B0(n3312), .B1(n3238), .Y(n1885)
);
INVX2TS U3341 ( .A(n1761), .Y(n1940) );
NOR2X1TS U3342 ( .A(n1940), .B(n3248), .Y(n1966) );
AOI22X1TS U3343 ( .A0(n1942), .A1(n1966), .B0(n3408), .B1(n1883), .Y(n1884)
);
NAND2X1TS U3344 ( .A(n1927), .B(Add_Subt_result[50]), .Y(n1888) );
AOI22X1TS U3345 ( .A0(n1929), .A1(Add_Subt_result[4]), .B0(DmP[48]), .B1(
n1928), .Y(n1887) );
NAND2X2TS U3346 ( .A(n1888), .B(n1887), .Y(n3180) );
AOI22X1TS U3347 ( .A0(n3312), .A1(n3182), .B0(n3326), .B1(n3180), .Y(n1893)
);
NAND2X1TS U3348 ( .A(n1927), .B(Add_Subt_result[51]), .Y(n1890) );
AOI22X1TS U3349 ( .A0(n1929), .A1(Add_Subt_result[3]), .B0(DmP[49]), .B1(
n1928), .Y(n1889) );
NAND2X2TS U3350 ( .A(n1890), .B(n1889), .Y(n3181) );
AND2X2TS U3351 ( .A(n3209), .B(n2114), .Y(n1970) );
INVX2TS U3352 ( .A(n1970), .Y(n3160) );
OAI22X1TS U3353 ( .A0(n3160), .A1(n3163), .B0(n3214), .B1(n3159), .Y(n1891)
);
AOI21X1TS U3354 ( .A0(n3380), .A1(n3181), .B0(n1891), .Y(n1892) );
BUFX3TS U3355 ( .A(n1894), .Y(n3295) );
AOI22X1TS U3356 ( .A0(n1977), .A1(Add_Subt_result[29]), .B0(DmP[23]), .B1(
n3375), .Y(n1895) );
OAI2BB1X2TS U3357 ( .A0N(Add_Subt_result[25]), .A1N(n3295), .B0(n1895), .Y(
n3262) );
AOI22X1TS U3358 ( .A0(n1977), .A1(Add_Subt_result[28]), .B0(DmP[24]), .B1(
n3375), .Y(n1896) );
OAI2BB1X2TS U3359 ( .A0N(Add_Subt_result[26]), .A1N(n3295), .B0(n1896), .Y(
n3249) );
AOI22X1TS U3360 ( .A0(n3326), .A1(n3262), .B0(n3338), .B1(n3249), .Y(n1899)
);
NAND2X1TS U3361 ( .A(n1942), .B(n1940), .Y(n1947) );
INVX2TS U3362 ( .A(n1901), .Y(n2120) );
INVX2TS U3363 ( .A(n1902), .Y(n2066) );
AOI22X1TS U3364 ( .A0(n2072), .A1(Sgf_normalized_result[54]), .B0(n2066),
.B1(n1903), .Y(n1904) );
INVX2TS U3365 ( .A(n1905), .Y(n2130) );
AOI22X1TS U3366 ( .A0(n2072), .A1(Sgf_normalized_result[51]), .B0(n2066),
.B1(n1906), .Y(n1907) );
OAI21X1TS U3367 ( .A0(n1343), .A1(n3593), .B0(n1847), .Y(n1908) );
AOI22X1TS U3368 ( .A0(n2321), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[70]), .B0(n2127), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[86]), .Y(n1910) );
AOI22X1TS U3369 ( .A0(n2328), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[62]), .B0(n2125), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[78]), .Y(n1909) );
AOI22X1TS U3370 ( .A0(n2072), .A1(Sgf_normalized_result[47]), .B0(n2132),
.B1(n2338), .Y(n1911) );
INVX2TS U3371 ( .A(n3159), .Y(n3186) );
AOI22X1TS U3372 ( .A0(n3186), .A1(n3397), .B0(n3380), .B1(n3175), .Y(n1912)
);
OAI21X1TS U3373 ( .A0(n2039), .A1(n1336), .B0(n1847), .Y(n1913) );
AOI22X1TS U3374 ( .A0(n2087), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[66]), .B0(n2327), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[82]), .Y(n1915) );
AOI22X1TS U3375 ( .A0(n2321), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[74]), .B0(n2127), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[90]), .Y(n1914) );
OAI211X1TS U3376 ( .A0(n2121), .A1(n2310), .B0(n1915), .C0(n1914), .Y(n2308)
);
AOI22X1TS U3377 ( .A0(n2094), .A1(Sgf_normalized_result[43]), .B0(n2066),
.B1(n2308), .Y(n1916) );
OAI21X1TS U3378 ( .A0(n1846), .A1(n3581), .B0(n1847), .Y(n1917) );
OAI21X1TS U3379 ( .A0(n1846), .A1(n3582), .B0(n1847), .Y(n1918) );
AOI22X1TS U3380 ( .A0(n2087), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[65]), .B0(n2125), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[81]), .Y(n1920) );
AOI22X1TS U3381 ( .A0(n2321), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[73]), .B0(n1998), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[89]), .Y(n1919) );
OAI211X1TS U3382 ( .A0(n2121), .A1(n2337), .B0(n1920), .C0(n1919), .Y(n2311)
);
AOI22X1TS U3383 ( .A0(n2072), .A1(Sgf_normalized_result[44]), .B0(n2132),
.B1(n2311), .Y(n1921) );
OAI21X1TS U3384 ( .A0(n2039), .A1(n3579), .B0(n1847), .Y(n1922) );
OAI21X1TS U3385 ( .A0(n1846), .A1(n3580), .B0(n1847), .Y(n1923) );
AOI22X1TS U3386 ( .A0(n2328), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[64]), .B0(n2327), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[80]), .Y(n1925) );
AOI22X1TS U3387 ( .A0(n2321), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[72]), .B0(n2127), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[88]), .Y(n1924) );
OAI211X1TS U3388 ( .A0(n2121), .A1(n2335), .B0(n1925), .C0(n1924), .Y(n2314)
);
AOI22X1TS U3389 ( .A0(n2072), .A1(Sgf_normalized_result[45]), .B0(n2132),
.B1(n2314), .Y(n1926) );
NAND2X1TS U3390 ( .A(n1927), .B(Add_Subt_result[49]), .Y(n1931) );
AOI22X1TS U3391 ( .A0(n1929), .A1(Add_Subt_result[5]), .B0(DmP[47]), .B1(
n1928), .Y(n1930) );
NAND2X2TS U3392 ( .A(n1931), .B(n1930), .Y(n3185) );
OAI22X1TS U3393 ( .A0(n3161), .A1(n3214), .B0(n3160), .B1(n3159), .Y(n1933)
);
NAND2X2TS U3394 ( .A(n1346), .B(n2114), .Y(n3257) );
AOI211X1TS U3395 ( .A0(n1934), .A1(n3185), .B0(n1933), .C0(n1932), .Y(n1936)
);
AOI22X1TS U3396 ( .A0(n3312), .A1(n3181), .B0(n3380), .B1(n3180), .Y(n1935)
);
AOI22X1TS U3397 ( .A0(n3411), .A1(n3238), .B0(n3246), .B1(n3239), .Y(n1944)
);
NOR2X1TS U3398 ( .A(n1940), .B(n3255), .Y(n3241) );
AOI22X1TS U3399 ( .A0(n1942), .A1(n3241), .B0(n3354), .B1(n1941), .Y(n1943)
);
AOI22X1TS U3400 ( .A0(n1977), .A1(Add_Subt_result[30]), .B0(DmP[22]), .B1(
n3375), .Y(n1946) );
OAI21X4TS U3401 ( .A0(n3560), .A1(n1756), .B0(n1946), .Y(n3269) );
AOI22X1TS U3402 ( .A0(n3309), .A1(n1967), .B0(n3378), .B1(n3269), .Y(n1950)
);
CLKBUFX2TS U3403 ( .A(n2069), .Y(n2333) );
AOI22X1TS U3404 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[87]), .A1(
n2116), .B0(Barrel_Shifter_module_Mux_Array_Data_array[71]), .B1(n2333), .Y(n1953) );
AOI22X1TS U3405 ( .A0(n2328), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[63]), .B0(n2327), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[79]), .Y(n1952) );
OAI211X1TS U3406 ( .A0(n1955), .A1(n1954), .B0(n1953), .C0(n1952), .Y(n2317)
);
AOI22X1TS U3407 ( .A0(n2072), .A1(Sgf_normalized_result[46]), .B0(n2066),
.B1(n2317), .Y(n1956) );
AOI22X1TS U3408 ( .A0(n2087), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[67]), .B0(n2327), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[83]), .Y(n1958) );
AOI22X1TS U3409 ( .A0(n2321), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[75]), .B0(n1998), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[91]), .Y(n1957) );
OAI211X1TS U3410 ( .A0(n2121), .A1(n2313), .B0(n1958), .C0(n1957), .Y(n1959)
);
INVX2TS U3411 ( .A(n1959), .Y(n2336) );
AOI22X1TS U3412 ( .A0(n2087), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[68]), .B0(n2327), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[84]), .Y(n1962) );
AOI22X1TS U3413 ( .A0(n2321), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[76]), .B0(n2127), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[92]), .Y(n1961) );
OAI211X1TS U3414 ( .A0(n2131), .A1(n2316), .B0(n1962), .C0(n1961), .Y(n1963)
);
INVX2TS U3415 ( .A(n1963), .Y(n2334) );
AOI22X1TS U3416 ( .A0(n1977), .A1(Add_Subt_result[31]), .B0(DmP[21]), .B1(
n3375), .Y(n1965) );
OAI2BB1X2TS U3417 ( .A0N(Add_Subt_result[23]), .A1N(n3295), .B0(n1965), .Y(
n3277) );
AOI222X1TS U3418 ( .A0(n3269), .A1(n1347), .B0(n3277), .B1(n3209), .C0(n3262), .C1(n3200), .Y(n1985) );
AOI22X1TS U3419 ( .A0(n3352), .A1(n3249), .B0(n3309), .B1(n3238), .Y(n1969)
);
AOI22X1TS U3420 ( .A0(n3354), .A1(n1967), .B0(n1966), .B1(n3240), .Y(n1968)
);
INVX2TS U3421 ( .A(n3180), .Y(n3168) );
INVX2TS U3422 ( .A(n3181), .Y(n3169) );
OAI22X1TS U3423 ( .A0(n3168), .A1(n3257), .B0(n3162), .B1(n3169), .Y(n1972)
);
OAI22X1TS U3424 ( .A0(n3161), .A1(n3276), .B0(n3214), .B1(n3167), .Y(n1971)
);
AOI211X1TS U3425 ( .A0(n1970), .A1(n3185), .B0(n1972), .C0(n1971), .Y(n1973)
);
AOI22X1TS U3426 ( .A0(n1977), .A1(Add_Subt_result[32]), .B0(DmP[20]), .B1(
n3375), .Y(n1975) );
OAI21X4TS U3427 ( .A0(n3554), .A1(n1756), .B0(n1975), .Y(n3283) );
BUFX3TS U3428 ( .A(n3394), .Y(n3310) );
BUFX3TS U3429 ( .A(n3489), .Y(n3302) );
AOI22X1TS U3430 ( .A0(n3310), .A1(Add_Subt_result[34]), .B0(DmP[18]), .B1(
n3302), .Y(n1976) );
OAI21X4TS U3431 ( .A0(n3591), .A1(n1756), .B0(n1976), .Y(n3296) );
AOI22X1TS U3432 ( .A0(n3253), .A1(n3283), .B0(n3338), .B1(n3296), .Y(n1984)
);
AOI22X1TS U3433 ( .A0(n1977), .A1(Add_Subt_result[33]), .B0(DmP[19]), .B1(
n3302), .Y(n1978) );
OAI2BB1X2TS U3434 ( .A0N(Add_Subt_result[21]), .A1N(n3295), .B0(n1978), .Y(
n3289) );
NAND2X1TS U3435 ( .A(n3395), .B(Add_Subt_result[19]), .Y(n1980) );
AOI22X1TS U3436 ( .A0(n3310), .A1(Add_Subt_result[35]), .B0(DmP[17]), .B1(
n3302), .Y(n1979) );
NAND2X2TS U3437 ( .A(n1980), .B(n1979), .Y(n3304) );
INVX2TS U3438 ( .A(n3304), .Y(n1981) );
OAI2BB2XLTS U3439 ( .B0(n1981), .B1(n3166), .A0N(n3249), .A1N(n3270), .Y(
n1982) );
AOI21X1TS U3440 ( .A0(n3367), .A1(n3289), .B0(n1982), .Y(n1983) );
AOI22X1TS U3441 ( .A0(n2328), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[70]), .B0(n2125), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[86]), .Y(n1987) );
AOI22X1TS U3442 ( .A0(n2333), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[78]), .B0(n1998), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[94]), .Y(n1986) );
OAI211X1TS U3443 ( .A0(n2131), .A1(n2340), .B0(n1987), .C0(n1986), .Y(n1995)
);
AOI22X1TS U3444 ( .A0(n1995), .A1(n3095), .B0(n2134), .B1(
Sgf_normalized_result[15]), .Y(n1988) );
OAI2BB2XLTS U3445 ( .B0(n2036), .B1(n3583), .A0N(n2035), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[93]), .Y(n1989) );
INVX2TS U3446 ( .A(n2041), .Y(n1993) );
AOI22X1TS U3447 ( .A0(n2328), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[61]), .B0(n2125), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[77]), .Y(n1992) );
AOI22X1TS U3448 ( .A0(n2069), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[69]), .B0(n1998), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[85]), .Y(n1991) );
OAI211X1TS U3449 ( .A0(n2121), .A1(n1993), .B0(n1992), .C0(n1991), .Y(n2343)
);
AOI22X1TS U3450 ( .A0(n2072), .A1(Sgf_normalized_result[48]), .B0(n2132),
.B1(n2343), .Y(n1994) );
AOI21X1TS U3451 ( .A0(n2134), .A1(Sgf_normalized_result[39]), .B0(n2133),
.Y(n1997) );
NAND2X1TS U3452 ( .A(n1995), .B(n2066), .Y(n1996) );
AOI22X1TS U3453 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[95]), .A1(
n2127), .B0(n2321), .B1(Barrel_Shifter_module_Mux_Array_Data_array[79]), .Y(n2000) );
AOI22X1TS U3454 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[87]), .A1(
n2115), .B0(n1852), .B1(Barrel_Shifter_module_Mux_Array_Data_array[71]), .Y(n1999) );
OAI211X1TS U3455 ( .A0(n2131), .A1(n2345), .B0(n2000), .C0(n1999), .Y(n2001)
);
INVX2TS U3456 ( .A(n2001), .Y(n2044) );
AOI22X1TS U3457 ( .A0(n1348), .A1(n2041), .B0(n2134), .B1(
Sgf_normalized_result[16]), .Y(n2002) );
OAI2BB2XLTS U3458 ( .B0(n2036), .B1(n3579), .A0N(n2008), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[92]), .Y(n2003) );
OAI21X1TS U3459 ( .A0(n1846), .A1(n3584), .B0(n2004), .Y(n2028) );
INVX2TS U3460 ( .A(n2028), .Y(n2349) );
AOI22X1TS U3461 ( .A0(n2126), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[60]), .B0(n2125), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[76]), .Y(n2006) );
AOI22X1TS U3462 ( .A0(n2069), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[68]), .B0(n1998), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[84]), .Y(n2005) );
OAI211X1TS U3463 ( .A0(n2121), .A1(n2349), .B0(n2006), .C0(n2005), .Y(n2357)
);
AOI22X1TS U3464 ( .A0(n2072), .A1(Sgf_normalized_result[49]), .B0(n2066),
.B1(n2357), .Y(n2007) );
OAI2BB2XLTS U3465 ( .B0(n2036), .B1(n3580), .A0N(n2008), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[88]), .Y(n2009) );
OAI21X1TS U3466 ( .A0(n1343), .A1(n3587), .B0(n2010), .Y(n2023) );
INVX2TS U3467 ( .A(n2023), .Y(n2351) );
AOI22X1TS U3468 ( .A0(n2126), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[56]), .B0(n2115), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[72]), .Y(n2012) );
BUFX3TS U3469 ( .A(n2069), .Y(n2117) );
INVX2TS U3470 ( .A(n2330), .Y(n2116) );
AOI22X1TS U3471 ( .A0(n2117), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[64]), .B0(n2116), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[80]), .Y(n2011) );
OAI211X1TS U3472 ( .A0(n2131), .A1(n2351), .B0(n2012), .C0(n2011), .Y(n2354)
);
AOI22X1TS U3473 ( .A0(n2072), .A1(Sgf_normalized_result[53]), .B0(n2132),
.B1(n2354), .Y(n2013) );
AOI22X1TS U3474 ( .A0(n2126), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[75]), .B0(n2115), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[91]), .Y(n2015) );
AOI22X1TS U3475 ( .A0(n2069), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[83]), .B0(n2127), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[99]), .Y(n2014) );
OAI211X1TS U3476 ( .A0(n2131), .A1(n3091), .B0(n2015), .C0(n2014), .Y(n2016)
);
INVX2TS U3477 ( .A(n2016), .Y(n2346) );
OAI2BB2XLTS U3478 ( .B0(n2036), .B1(n3582), .A0N(n2035), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[89]), .Y(n2017) );
OAI21X1TS U3479 ( .A0(n1343), .A1(n3586), .B0(n2018), .Y(n2063) );
AOI22X1TS U3480 ( .A0(n2042), .A1(n2063), .B0(n3092), .B1(
Sgf_normalized_result[34]), .Y(n2019) );
AOI22X1TS U3481 ( .A0(n2126), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[76]), .B0(n2115), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[92]), .Y(n2021) );
AOI22X1TS U3482 ( .A0(n2117), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[84]), .B0(n2116), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[100]), .Y(n2020) );
OAI211X1TS U3483 ( .A0(n2131), .A1(n2356), .B0(n2021), .C0(n2020), .Y(n2022)
);
INVX2TS U3484 ( .A(n2022), .Y(n2350) );
AOI22X1TS U3485 ( .A0(n2042), .A1(n2023), .B0(n3092), .B1(
Sgf_normalized_result[33]), .Y(n2024) );
AOI22X1TS U3486 ( .A0(n2328), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[72]), .B0(n2125), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[88]), .Y(n2026) );
AOI22X1TS U3487 ( .A0(n2333), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[80]), .B0(n2127), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[96]), .Y(n2025) );
OAI211X1TS U3488 ( .A0(n2131), .A1(n2359), .B0(n2026), .C0(n2025), .Y(n2027)
);
INVX2TS U3489 ( .A(n2027), .Y(n2348) );
AOI22X1TS U3490 ( .A0(n2042), .A1(n2028), .B0(n3092), .B1(
Sgf_normalized_result[37]), .Y(n2029) );
AOI22X1TS U3491 ( .A0(n2126), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[73]), .B0(n2125), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[89]), .Y(n2033) );
AOI22X1TS U3492 ( .A0(n2069), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[81]), .B0(n2127), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[97]), .Y(n2032) );
OAI211X1TS U3493 ( .A0(n2131), .A1(n2364), .B0(n2033), .C0(n2032), .Y(n2034)
);
INVX2TS U3494 ( .A(n2034), .Y(n2352) );
OAI2BB2XLTS U3495 ( .B0(n2036), .B1(n3581), .A0N(n2035), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[91]), .Y(n2037) );
OAI21X1TS U3496 ( .A0(n1846), .A1(n3585), .B0(n2038), .Y(n2068) );
AOI22X1TS U3497 ( .A0(n2042), .A1(n2068), .B0(n3092), .B1(
Sgf_normalized_result[36]), .Y(n2040) );
AOI22X1TS U3498 ( .A0(n2042), .A1(n2041), .B0(n3092), .B1(
Sgf_normalized_result[38]), .Y(n2043) );
NAND2X1TS U3499 ( .A(n3218), .B(n3207), .Y(n2047) );
NAND2X1TS U3500 ( .A(n3192), .B(n2097), .Y(n2046) );
NAND2X1TS U3501 ( .A(n3215), .B(n3210), .Y(n2045) );
AOI22X1TS U3502 ( .A0(n3399), .A1(n3184), .B0(n3411), .B1(n3204), .Y(n2052)
);
NAND2X1TS U3503 ( .A(n3387), .B(n3183), .Y(n2050) );
NAND2X1TS U3504 ( .A(n3405), .B(n3185), .Y(n2049) );
NAND2X1TS U3505 ( .A(n3270), .B(n3180), .Y(n2048) );
AOI22X1TS U3506 ( .A0(n2087), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[85]), .B0(n2327), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[101]), .Y(n2053) );
AOI21X1TS U3507 ( .A0(n2117), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[93]), .B0(n2054), .Y(n2062)
);
AOI22X1TS U3508 ( .A0(Barrel_Shifter_module_Mux_Array_Data_array[95]), .A1(
n2115), .B0(n1852), .B1(Barrel_Shifter_module_Mux_Array_Data_array[79]), .Y(n2055) );
AOI21X1TS U3509 ( .A0(n2117), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[87]), .B0(n2056), .Y(n2059)
);
INVX2TS U3510 ( .A(n2063), .Y(n2347) );
AOI22X1TS U3511 ( .A0(n2126), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[57]), .B0(n2115), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[73]), .Y(n2065) );
AOI22X1TS U3512 ( .A0(n2117), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[65]), .B0(n2116), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[81]), .Y(n2064) );
OAI211X1TS U3513 ( .A0(n2121), .A1(n2347), .B0(n2065), .C0(n2064), .Y(n3094)
);
AOI22X1TS U3514 ( .A0(n2134), .A1(Sgf_normalized_result[52]), .B0(n2066),
.B1(n3094), .Y(n2067) );
INVX2TS U3515 ( .A(n2068), .Y(n2353) );
AOI22X1TS U3516 ( .A0(n2126), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[59]), .B0(n2125), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[75]), .Y(n2071) );
AOI22X1TS U3517 ( .A0(n2069), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[67]), .B0(n2127), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[83]), .Y(n2070) );
OAI211X1TS U3518 ( .A0(n2121), .A1(n2353), .B0(n2071), .C0(n2070), .Y(n2360)
);
AOI22X1TS U3519 ( .A0(n2072), .A1(Sgf_normalized_result[50]), .B0(n2132),
.B1(n2360), .Y(n2073) );
AOI22X1TS U3520 ( .A0(n2087), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[81]), .B0(n2115), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[97]), .Y(n2075) );
AOI21X1TS U3521 ( .A0(n2117), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[89]), .B0(n2076), .Y(n2081)
);
AOI22X1TS U3522 ( .A0(n2087), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[83]), .B0(n2327), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[99]), .Y(n2077) );
AOI21X1TS U3523 ( .A0(n2117), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[91]), .B0(n2078), .Y(n2084)
);
AOI22X1TS U3524 ( .A0(n2087), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[80]), .B0(n2323), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[96]), .Y(n2085) );
AOI21X1TS U3525 ( .A0(n2117), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[88]), .B0(n2086), .Y(n2096)
);
AOI22X1TS U3526 ( .A0(n2087), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[84]), .B0(n2327), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[100]), .Y(n2088) );
AOI21X1TS U3527 ( .A0(n2117), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[92]), .B0(n2089), .Y(n2092)
);
NAND2X1TS U3528 ( .A(n3226), .B(n2097), .Y(n2100) );
NAND2X1TS U3529 ( .A(n3192), .B(n3207), .Y(n2099) );
NAND2X1TS U3530 ( .A(n3218), .B(n3200), .Y(n2098) );
AOI22X1TS U3531 ( .A0(n3386), .A1(n3183), .B0(n3253), .B1(n3215), .Y(n2105)
);
NAND2X1TS U3532 ( .A(n3387), .B(n3204), .Y(n2103) );
NAND2X1TS U3533 ( .A(n3405), .B(n3184), .Y(n2102) );
NAND2X1TS U3534 ( .A(n3270), .B(n3185), .Y(n2101) );
NAND2X1TS U3535 ( .A(n3215), .B(n3207), .Y(n2108) );
NAND2X1TS U3536 ( .A(n3218), .B(n3209), .Y(n2107) );
NAND2X1TS U3537 ( .A(n3183), .B(n3191), .Y(n2106) );
AOI22X1TS U3538 ( .A0(n3403), .A1(n3204), .B0(n3379), .B1(n3180), .Y(n2113)
);
NAND2X1TS U3539 ( .A(n3386), .B(n3185), .Y(n2111) );
NAND2X1TS U3540 ( .A(n3387), .B(n3184), .Y(n2110) );
NAND2X1TS U3541 ( .A(n3270), .B(n3181), .Y(n2109) );
AOI22X1TS U3542 ( .A0(n2126), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[77]), .B0(n2115), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[93]), .Y(n2119) );
AOI22X1TS U3543 ( .A0(n2117), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[85]), .B0(n2116), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[101]), .Y(n2118) );
OAI211X1TS U3544 ( .A0(n2121), .A1(n2120), .B0(n2119), .C0(n2118), .Y(n2365)
);
NAND2X1TS U3545 ( .A(n2365), .B(n2122), .Y(n2124) );
AOI21X1TS U3546 ( .A0(n2134), .A1(Sgf_normalized_result[32]), .B0(n1339),
.Y(n2123) );
AOI22X1TS U3547 ( .A0(n2126), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[74]), .B0(n2125), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[90]), .Y(n2129) );
AOI22X1TS U3548 ( .A0(n2333), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[82]), .B0(n1998), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[98]), .Y(n2128) );
OAI211X1TS U3549 ( .A0(n2131), .A1(n2130), .B0(n2129), .C0(n2128), .Y(n2369)
);
NAND2X1TS U3550 ( .A(n2369), .B(n2132), .Y(n2136) );
AOI21X1TS U3551 ( .A0(n2134), .A1(Sgf_normalized_result[35]), .B0(n1339),
.Y(n2135) );
BUFX3TS U3552 ( .A(n2160), .Y(n2254) );
AOI22X1TS U3553 ( .A0(n2220), .A1(intDY[10]), .B0(DmP[10]), .B1(n2254), .Y(
n2137) );
AOI22X1TS U3554 ( .A0(n2220), .A1(intDY[5]), .B0(DmP[5]), .B1(n2254), .Y(
n2138) );
BUFX3TS U3555 ( .A(n2160), .Y(n2257) );
AOI22X1TS U3556 ( .A0(n2174), .A1(intDY[6]), .B0(DmP[6]), .B1(n2257), .Y(
n2139) );
AOI22X1TS U3557 ( .A0(n2220), .A1(intDY[7]), .B0(DmP[7]), .B1(n2254), .Y(
n2140) );
BUFX3TS U3558 ( .A(n2178), .Y(n2285) );
BUFX3TS U3559 ( .A(n2209), .Y(n2251) );
AOI22X1TS U3560 ( .A0(n2157), .A1(intDY[59]), .B0(DmP[59]), .B1(n2251), .Y(
n2142) );
AOI22X1TS U3561 ( .A0(n2157), .A1(intDY[57]), .B0(DmP[57]), .B1(n2260), .Y(
n2143) );
AOI22X1TS U3562 ( .A0(n2157), .A1(intDY[60]), .B0(DmP[60]), .B1(n2251), .Y(
n2144) );
BUFX3TS U3563 ( .A(n2178), .Y(n2298) );
AOI22X1TS U3564 ( .A0(n2220), .A1(intDY[14]), .B0(DmP[14]), .B1(n2254), .Y(
n2145) );
AOI22X1TS U3565 ( .A0(n2141), .A1(intDY[11]), .B0(DmP[11]), .B1(n2257), .Y(
n2146) );
AOI22X1TS U3566 ( .A0(n2141), .A1(intDY[8]), .B0(DmP[8]), .B1(n2257), .Y(
n2147) );
AOI22X1TS U3567 ( .A0(n2220), .A1(intDY[12]), .B0(DmP[12]), .B1(n2257), .Y(
n2148) );
AOI22X1TS U3568 ( .A0(n2141), .A1(intDY[13]), .B0(DmP[13]), .B1(n2254), .Y(
n2149) );
AOI22X1TS U3569 ( .A0(n2141), .A1(intDY[9]), .B0(DmP[9]), .B1(n2257), .Y(
n2150) );
BUFX3TS U3570 ( .A(n2251), .Y(n2303) );
AOI22X1TS U3571 ( .A0(DmP[44]), .A1(n2303), .B0(intDY[44]), .B1(n2157), .Y(
n2151) );
BUFX3TS U3572 ( .A(n2209), .Y(n2291) );
AOI22X1TS U3573 ( .A0(DmP[39]), .A1(n2291), .B0(intDY[39]), .B1(n2157), .Y(
n2152) );
BUFX3TS U3574 ( .A(n2209), .Y(n2300) );
AOI22X1TS U3575 ( .A0(DmP[42]), .A1(n2300), .B0(intDY[42]), .B1(n2157), .Y(
n2153) );
AOI22X1TS U3576 ( .A0(DmP[36]), .A1(n2291), .B0(intDY[36]), .B1(n2157), .Y(
n2154) );
AOI22X1TS U3577 ( .A0(DmP[33]), .A1(n2296), .B0(intDY[33]), .B1(n2157), .Y(
n2155) );
AOI22X1TS U3578 ( .A0(DmP[43]), .A1(n2300), .B0(intDY[43]), .B1(n2157), .Y(
n2156) );
AOI22X1TS U3579 ( .A0(DmP[37]), .A1(n2300), .B0(intDY[37]), .B1(n2157), .Y(
n2158) );
AOI22X1TS U3580 ( .A0(n2275), .A1(intDX[63]), .B0(sign_final_result), .B1(
n2270), .Y(n2161) );
AOI22X1TS U3581 ( .A0(n2275), .A1(intDY[1]), .B0(DmP[1]), .B1(n2254), .Y(
n2164) );
AOI22X1TS U3582 ( .A0(n2275), .A1(intDY[4]), .B0(DmP[4]), .B1(n2254), .Y(
n2165) );
AOI22X1TS U3583 ( .A0(n2275), .A1(intDY[62]), .B0(DmP[62]), .B1(n2254), .Y(
n2166) );
AOI22X1TS U3584 ( .A0(n2275), .A1(intDY[2]), .B0(DmP[2]), .B1(n2300), .Y(
n2167) );
AOI22X1TS U3585 ( .A0(n2275), .A1(intDY[3]), .B0(DmP[3]), .B1(n2257), .Y(
n2168) );
AOI22X1TS U3586 ( .A0(DmP[19]), .A1(n2296), .B0(intDY[19]), .B1(n2174), .Y(
n2169) );
BUFX3TS U3587 ( .A(n2211), .Y(n2305) );
AOI22X1TS U3588 ( .A0(DmP[51]), .A1(n2303), .B0(intDY[51]), .B1(n2174), .Y(
n2170) );
AOI22X1TS U3589 ( .A0(DmP[18]), .A1(n2296), .B0(intDY[18]), .B1(n2174), .Y(
n2171) );
AOI22X1TS U3590 ( .A0(DmP[45]), .A1(n2291), .B0(intDY[45]), .B1(n2174), .Y(
n2172) );
AOI22X1TS U3591 ( .A0(DmP[49]), .A1(n2291), .B0(intDY[49]), .B1(n2174), .Y(
n2173) );
AOI22X1TS U3592 ( .A0(DmP[46]), .A1(n2303), .B0(intDY[46]), .B1(n2174), .Y(
n2175) );
AOI22X1TS U3593 ( .A0(n2207), .A1(intDY[24]), .B0(DMP[24]), .B1(n2267), .Y(
n2176) );
AOI22X1TS U3594 ( .A0(n2207), .A1(intDY[26]), .B0(DMP[26]), .B1(n2267), .Y(
n2177) );
BUFX3TS U3595 ( .A(n2209), .Y(n2196) );
AOI22X1TS U3596 ( .A0(n2197), .A1(intDY[19]), .B0(DMP[19]), .B1(n2196), .Y(
n2179) );
AOI22X1TS U3597 ( .A0(n2207), .A1(intDY[22]), .B0(DMP[22]), .B1(n2196), .Y(
n2180) );
AOI22X1TS U3598 ( .A0(n2207), .A1(intDY[27]), .B0(DMP[27]), .B1(n2267), .Y(
n2181) );
AOI22X1TS U3599 ( .A0(n2197), .A1(intDY[14]), .B0(DMP[14]), .B1(n2196), .Y(
n2182) );
AOI22X1TS U3600 ( .A0(n2197), .A1(intDY[20]), .B0(DMP[20]), .B1(n2196), .Y(
n2183) );
AOI22X1TS U3601 ( .A0(n2197), .A1(intDY[12]), .B0(DMP[12]), .B1(n2217), .Y(
n2184) );
AOI22X1TS U3602 ( .A0(n2197), .A1(intDY[13]), .B0(DMP[13]), .B1(n2196), .Y(
n2185) );
AOI22X1TS U3603 ( .A0(n2207), .A1(intDY[25]), .B0(DMP[25]), .B1(n2267), .Y(
n2186) );
AOI22X1TS U3604 ( .A0(n2207), .A1(intDY[21]), .B0(DMP[21]), .B1(n2196), .Y(
n2187) );
AOI22X1TS U3605 ( .A0(n2207), .A1(intDY[29]), .B0(DMP[29]), .B1(n2267), .Y(
n2188) );
AOI22X1TS U3606 ( .A0(n2197), .A1(intDY[17]), .B0(DMP[17]), .B1(n2196), .Y(
n2189) );
AOI22X1TS U3607 ( .A0(n2197), .A1(intDY[11]), .B0(DMP[11]), .B1(n2217), .Y(
n2190) );
AOI22X1TS U3608 ( .A0(n2197), .A1(intDY[18]), .B0(DMP[18]), .B1(n2196), .Y(
n2191) );
AOI22X1TS U3609 ( .A0(n2197), .A1(intDY[15]), .B0(DMP[15]), .B1(n2196), .Y(
n2192) );
AOI22X1TS U3610 ( .A0(n2218), .A1(intDY[3]), .B0(DMP[3]), .B1(n2217), .Y(
n2193) );
AOI22X1TS U3611 ( .A0(n2218), .A1(intDY[10]), .B0(DMP[10]), .B1(n2217), .Y(
n2194) );
AOI22X1TS U3612 ( .A0(n2218), .A1(intDY[5]), .B0(DMP[5]), .B1(n2217), .Y(
n2195) );
AOI22X1TS U3613 ( .A0(n2197), .A1(intDY[16]), .B0(DMP[16]), .B1(n2196), .Y(
n2198) );
AOI22X1TS U3614 ( .A0(n2237), .A1(intDY[0]), .B0(DMP[0]), .B1(n2296), .Y(
n2199) );
AOI22X1TS U3615 ( .A0(n2218), .A1(intDY[6]), .B0(DMP[6]), .B1(n2217), .Y(
n2201) );
AOI22X1TS U3616 ( .A0(n2218), .A1(intDY[4]), .B0(DMP[4]), .B1(n2267), .Y(
n2202) );
AOI22X1TS U3617 ( .A0(n2218), .A1(intDY[7]), .B0(DMP[7]), .B1(n2217), .Y(
n2203) );
AOI22X1TS U3618 ( .A0(n2207), .A1(intDY[30]), .B0(DMP[30]), .B1(n2267), .Y(
n2205) );
AOI22X1TS U3619 ( .A0(n2207), .A1(intDY[28]), .B0(DMP[28]), .B1(n2267), .Y(
n2206) );
AOI22X1TS U3620 ( .A0(n2207), .A1(intDY[23]), .B0(DMP[23]), .B1(n2270), .Y(
n2208) );
INVX2TS U3621 ( .A(n2220), .Y(n2216) );
BUFX3TS U3622 ( .A(n2209), .Y(n2245) );
AOI22X1TS U3623 ( .A0(n2235), .A1(intDY[48]), .B0(DMP[48]), .B1(n2245), .Y(
n2210) );
INVX2TS U3624 ( .A(n2211), .Y(n2241) );
AOI22X1TS U3625 ( .A0(DmP[23]), .A1(n2291), .B0(intDX[23]), .B1(n2241), .Y(
n2212) );
AOI22X1TS U3626 ( .A0(DmP[24]), .A1(n2296), .B0(intDX[24]), .B1(n2241), .Y(
n2213) );
AOI22X1TS U3627 ( .A0(n2235), .A1(intDY[49]), .B0(DMP[49]), .B1(n2245), .Y(
n2214) );
AOI22X1TS U3628 ( .A0(n2235), .A1(intDY[50]), .B0(DMP[50]), .B1(n2245), .Y(
n2215) );
AOI22X1TS U3629 ( .A0(n2218), .A1(intDY[1]), .B0(DMP[1]), .B1(n2217), .Y(
n2219) );
AOI22X1TS U3630 ( .A0(n2235), .A1(intDY[46]), .B0(DMP[46]), .B1(n2245), .Y(
n2221) );
AOI22X1TS U3631 ( .A0(n2235), .A1(intDY[47]), .B0(DMP[47]), .B1(n2245), .Y(
n2222) );
AOI22X1TS U3632 ( .A0(n2235), .A1(intDY[45]), .B0(DMP[45]), .B1(n2245), .Y(
n2223) );
AOI22X1TS U3633 ( .A0(n2237), .A1(intDY[58]), .B0(DMP[58]), .B1(n2251), .Y(
n2224) );
AOI22X1TS U3634 ( .A0(n2237), .A1(intDY[56]), .B0(DMP[56]), .B1(n2260), .Y(
n2225) );
AOI22X1TS U3635 ( .A0(n2241), .A1(intDY[42]), .B0(DMP[42]), .B1(n2257), .Y(
n2226) );
AOI22X1TS U3636 ( .A0(n2237), .A1(intDY[59]), .B0(DMP[59]), .B1(n2251), .Y(
n2227) );
AOI22X1TS U3637 ( .A0(n2235), .A1(intDY[44]), .B0(DMP[44]), .B1(n2245), .Y(
n2228) );
AOI22X1TS U3638 ( .A0(n2237), .A1(intDY[60]), .B0(DMP[60]), .B1(n2251), .Y(
n2229) );
AOI22X1TS U3639 ( .A0(n2237), .A1(intDY[61]), .B0(DMP[61]), .B1(n2251), .Y(
n2231) );
AOI22X1TS U3640 ( .A0(n2237), .A1(intDY[54]), .B0(DMP[54]), .B1(n2260), .Y(
n2232) );
AOI22X1TS U3641 ( .A0(n2235), .A1(intDY[51]), .B0(DMP[51]), .B1(n2245), .Y(
n2233) );
AOI22X1TS U3642 ( .A0(n2237), .A1(intDY[57]), .B0(DMP[57]), .B1(n2260), .Y(
n2234) );
AOI22X1TS U3643 ( .A0(n2235), .A1(intDY[52]), .B0(DMP[52]), .B1(n2245), .Y(
n2236) );
AOI22X1TS U3644 ( .A0(n2237), .A1(intDY[62]), .B0(DMP[62]), .B1(n2251), .Y(
n2238) );
AOI22X1TS U3645 ( .A0(n2241), .A1(intDY[41]), .B0(DMP[41]), .B1(n2257), .Y(
n2240) );
AOI22X1TS U3646 ( .A0(n2241), .A1(intDY[43]), .B0(DMP[43]), .B1(n2257), .Y(
n2242) );
AOI22X1TS U3647 ( .A0(n2271), .A1(intDY[38]), .B0(DMP[38]), .B1(n2270), .Y(
n2244) );
AOI22X1TS U3648 ( .A0(n2261), .A1(intDY[52]), .B0(DmP[52]), .B1(n2245), .Y(
n2246) );
AOI22X1TS U3649 ( .A0(n2261), .A1(intDY[61]), .B0(DmP[61]), .B1(n2251), .Y(
n2247) );
AOI22X1TS U3650 ( .A0(n2261), .A1(intDY[16]), .B0(DmP[16]), .B1(n2254), .Y(
n2248) );
AOI22X1TS U3651 ( .A0(n2261), .A1(intDY[56]), .B0(DmP[56]), .B1(n2260), .Y(
n2249) );
AOI22X1TS U3652 ( .A0(n2261), .A1(intDY[54]), .B0(DmP[54]), .B1(n2260), .Y(
n2250) );
AOI22X1TS U3653 ( .A0(n2261), .A1(intDY[58]), .B0(DmP[58]), .B1(n2251), .Y(
n2252) );
AOI22X1TS U3654 ( .A0(n2261), .A1(intDY[0]), .B0(DmP[0]), .B1(n2254), .Y(
n2255) );
AOI22X1TS U3655 ( .A0(n2261), .A1(intDY[15]), .B0(DmP[15]), .B1(n2257), .Y(
n2258) );
AOI22X1TS U3656 ( .A0(n2261), .A1(intDY[55]), .B0(DmP[55]), .B1(n2260), .Y(
n2259) );
AOI22X1TS U3657 ( .A0(n2261), .A1(intDY[53]), .B0(DmP[53]), .B1(n2260), .Y(
n2262) );
AOI22X1TS U3658 ( .A0(n2271), .A1(intDY[37]), .B0(DMP[37]), .B1(n2270), .Y(
n2263) );
AOI22X1TS U3659 ( .A0(n2271), .A1(intDY[39]), .B0(DMP[39]), .B1(n2270), .Y(
n2264) );
AOI22X1TS U3660 ( .A0(n2271), .A1(intDY[34]), .B0(DMP[34]), .B1(n2270), .Y(
n2265) );
AOI22X1TS U3661 ( .A0(n2271), .A1(intDY[32]), .B0(DMP[32]), .B1(n2267), .Y(
n2268) );
AOI22X1TS U3662 ( .A0(n2271), .A1(intDY[40]), .B0(DMP[40]), .B1(n2270), .Y(
n2269) );
AOI22X1TS U3663 ( .A0(n2271), .A1(intDY[36]), .B0(DMP[36]), .B1(n2270), .Y(
n2272) );
AOI22X1TS U3664 ( .A0(DmP[48]), .A1(n2291), .B0(intDY[48]), .B1(n2299), .Y(
n2274) );
AOI22X1TS U3665 ( .A0(DmP[38]), .A1(n2300), .B0(intDY[38]), .B1(n2302), .Y(
n2276) );
AOI22X1TS U3666 ( .A0(DmP[26]), .A1(n2291), .B0(intDY[26]), .B1(n2299), .Y(
n2277) );
AOI22X1TS U3667 ( .A0(DmP[47]), .A1(n2303), .B0(intDY[47]), .B1(n2299), .Y(
n2278) );
AOI22X1TS U3668 ( .A0(DmP[30]), .A1(n2291), .B0(intDY[30]), .B1(n2302), .Y(
n2280) );
AOI22X1TS U3669 ( .A0(DmP[34]), .A1(n2300), .B0(intDY[34]), .B1(n2299), .Y(
n2281) );
AOI22X1TS U3670 ( .A0(DmP[40]), .A1(n2300), .B0(intDY[40]), .B1(n2299), .Y(
n2282) );
AOI22X1TS U3671 ( .A0(DmP[27]), .A1(n2303), .B0(intDY[27]), .B1(n2302), .Y(
n2283) );
AOI22X1TS U3672 ( .A0(DmP[50]), .A1(n2296), .B0(intDY[50]), .B1(n2299), .Y(
n2284) );
AOI22X1TS U3673 ( .A0(DmP[22]), .A1(n2303), .B0(intDY[22]), .B1(n2302), .Y(
n2286) );
AOI22X1TS U3674 ( .A0(DmP[25]), .A1(n2291), .B0(intDY[25]), .B1(n2302), .Y(
n2287) );
AOI22X1TS U3675 ( .A0(DmP[17]), .A1(n2303), .B0(intDY[17]), .B1(n2299), .Y(
n2288) );
AOI22X1TS U3676 ( .A0(DmP[20]), .A1(n2303), .B0(intDY[20]), .B1(n2299), .Y(
n2289) );
AOI22X1TS U3677 ( .A0(DmP[28]), .A1(n2303), .B0(intDY[28]), .B1(n2302), .Y(
n2290) );
AOI22X1TS U3678 ( .A0(DmP[41]), .A1(n2291), .B0(intDY[41]), .B1(n2302), .Y(
n2292) );
AOI22X1TS U3679 ( .A0(DmP[31]), .A1(n2300), .B0(intDY[31]), .B1(n2302), .Y(
n2293) );
AOI22X1TS U3680 ( .A0(DmP[35]), .A1(n2300), .B0(intDY[35]), .B1(n2302), .Y(
n2294) );
AOI22X1TS U3681 ( .A0(DmP[21]), .A1(n2296), .B0(intDY[21]), .B1(n2299), .Y(
n2297) );
AOI22X1TS U3682 ( .A0(DmP[29]), .A1(n2300), .B0(intDY[29]), .B1(n2299), .Y(
n2301) );
AOI22X1TS U3683 ( .A0(DmP[32]), .A1(n2303), .B0(intDY[32]), .B1(n2302), .Y(
n2304) );
INVX2TS U3684 ( .A(n3420), .Y(n3424) );
NOR3X1TS U3685 ( .A(overflow_flag), .B(underflow_flag), .C(n3424), .Y(n3154)
);
INVX2TS U3686 ( .A(n1334), .Y(n3419) );
INVX2TS U3687 ( .A(n3420), .Y(n3157) );
OAI2BB2XLTS U3688 ( .B0(n3516), .B1(n3419), .A0N(n3157), .A1N(
final_result_ieee[21]), .Y(n74) );
OAI2BB2XLTS U3689 ( .B0(n3512), .B1(n3419), .A0N(n3157), .A1N(
final_result_ieee[17]), .Y(n36) );
OAI2BB2XLTS U3690 ( .B0(n3515), .B1(n3419), .A0N(n3157), .A1N(
final_result_ieee[20]), .Y(n15) );
OAI2BB2XLTS U3691 ( .B0(n3517), .B1(n3419), .A0N(n3157), .A1N(
final_result_ieee[29]), .Y(n72) );
OAI2BB2XLTS U3692 ( .B0(n3510), .B1(n3419), .A0N(n3157), .A1N(
final_result_ieee[15]), .Y(n52) );
OAI2BB2XLTS U3693 ( .B0(n3511), .B1(n3419), .A0N(n3157), .A1N(
final_result_ieee[16]), .Y(n44) );
OAI2BB2XLTS U3694 ( .B0(n3513), .B1(n3419), .A0N(n3157), .A1N(
final_result_ieee[18]), .Y(n28) );
OAI2BB2XLTS U3695 ( .B0(n3514), .B1(n3419), .A0N(n3157), .A1N(
final_result_ieee[19]), .Y(n21) );
INVX2TS U3696 ( .A(n1334), .Y(n2307) );
INVX2TS U3697 ( .A(n3426), .Y(n2306) );
OAI2BB2XLTS U3698 ( .B0(n3506), .B1(n2307), .A0N(n2306), .A1N(
final_result_ieee[8]), .Y(n94) );
OAI2BB2XLTS U3699 ( .B0(n3504), .B1(n2307), .A0N(n2306), .A1N(
final_result_ieee[6]), .Y(n78) );
OAI2BB2XLTS U3700 ( .B0(n3507), .B1(n2307), .A0N(n2306), .A1N(
final_result_ieee[9]), .Y(n102) );
OAI2BB2XLTS U3701 ( .B0(n3505), .B1(n2307), .A0N(n2306), .A1N(
final_result_ieee[7]), .Y(n86) );
OAI2BB2XLTS U3702 ( .B0(n3500), .B1(n2307), .A0N(n2306), .A1N(
final_result_ieee[2]), .Y(n46) );
OAI2BB2XLTS U3703 ( .B0(n3508), .B1(n2307), .A0N(n2306), .A1N(
final_result_ieee[10]), .Y(n98) );
OAI2BB2XLTS U3704 ( .B0(n3502), .B1(n2307), .A0N(n2306), .A1N(
final_result_ieee[4]), .Y(n62) );
OAI2BB2XLTS U3705 ( .B0(n3509), .B1(n2307), .A0N(n2306), .A1N(
final_result_ieee[11]), .Y(n90) );
OAI2BB2XLTS U3706 ( .B0(n3501), .B1(n2307), .A0N(n2306), .A1N(
final_result_ieee[3]), .Y(n54) );
OAI2BB2XLTS U3707 ( .B0(n3503), .B1(n2307), .A0N(n2306), .A1N(
final_result_ieee[5]), .Y(n70) );
BUFX3TS U3708 ( .A(n2361), .Y(n2373) );
INVX2TS U3709 ( .A(n3095), .Y(n2371) );
INVX2TS U3710 ( .A(n2308), .Y(n2309) );
INVX2TS U3711 ( .A(n3095), .Y(n2367) );
INVX2TS U3712 ( .A(n2311), .Y(n2312) );
OAI222X1TS U3713 ( .A0(n3506), .A1(n2373), .B0(n1349), .B1(n2313), .C0(n2363), .C1(n2312), .Y(n95) );
INVX2TS U3714 ( .A(n2314), .Y(n2315) );
OAI222X1TS U3715 ( .A0(n3505), .A1(n2373), .B0(n1350), .B1(n2316), .C0(n2371), .C1(n2315), .Y(n87) );
INVX2TS U3716 ( .A(n2317), .Y(n2318) );
OAI222X1TS U3717 ( .A0(n3504), .A1(n2373), .B0(n1349), .B1(n2319), .C0(n2367), .C1(n2318), .Y(n79) );
AOI22X1TS U3718 ( .A0(n2328), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[86]), .B0(n2321), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[94]), .Y(n2322) );
OAI2BB1X1TS U3719 ( .A0N(n2323), .A1N(
Barrel_Shifter_module_Mux_Array_Data_array[102]), .B0(n2322), .Y(n2326) );
NOR3X1TS U3720 ( .A(n2326), .B(n2331), .C(n2325), .Y(n2341) );
AOI22X1TS U3721 ( .A0(n2328), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[78]), .B0(n2327), .B1(
Barrel_Shifter_module_Mux_Array_Data_array[94]), .Y(n2329) );
AOI211X1TS U3722 ( .A0(n2333), .A1(
Barrel_Shifter_module_Mux_Array_Data_array[86]), .B0(n2332), .C0(n2331), .Y(n2342) );
OAI222X1TS U3723 ( .A0(n3516), .A1(n2320), .B0(n1344), .B1(n2341), .C0(n2371), .C1(n2342), .Y(n75) );
INVX2TS U3724 ( .A(n2338), .Y(n2339) );
OAI222X1TS U3725 ( .A0(n3517), .A1(n2320), .B0(n1344), .B1(n2342), .C0(n2367), .C1(n2341), .Y(n73) );
INVX2TS U3726 ( .A(n2343), .Y(n2344) );
OAI222X1TS U3727 ( .A0(n3513), .A1(n2373), .B0(n1350), .B1(n2347), .C0(n2363), .C1(n2346), .Y(n29) );
OAI222X1TS U3728 ( .A0(n3514), .A1(n2320), .B0(n1349), .B1(n2351), .C0(n2371), .C1(n2350), .Y(n22) );
INVX2TS U3729 ( .A(n2354), .Y(n2355) );
INVX2TS U3730 ( .A(n2357), .Y(n2358) );
INVX2TS U3731 ( .A(n2360), .Y(n2362) );
OAI222X1TS U3732 ( .A0(n2364), .A1(n1349), .B0(n2363), .B1(n2362), .C0(n2361), .C1(n3500), .Y(n47) );
INVX2TS U3733 ( .A(n2365), .Y(n2366) );
OAI222X1TS U3734 ( .A0(n3515), .A1(n2320), .B0(n1350), .B1(n2368), .C0(n2367), .C1(n2366), .Y(n16) );
BUFX3TS U3735 ( .A(n3441), .Y(n3447) );
XOR2X1TS U3736 ( .A(n2403), .B(n2375), .Y(n2377) );
NOR2X2TS U3737 ( .A(n2377), .B(n2376), .Y(n3043) );
OR2X1TS U3738 ( .A(FSM_selector_D), .B(Sgf_normalized_result[2]), .Y(n2378)
);
XOR2X1TS U3739 ( .A(n2403), .B(n2378), .Y(n2383) );
NOR2X1TS U3740 ( .A(n2383), .B(n2382), .Y(n3036) );
NOR2X1TS U3741 ( .A(n3043), .B(n3036), .Y(n2385) );
NOR2BX1TS U3742 ( .AN(Sgf_normalized_result[0]), .B(n2601), .Y(n2379) );
XOR2X1TS U3743 ( .A(n2604), .B(n2379), .Y(n2614) );
INVX2TS U3744 ( .A(n2614), .Y(n2381) );
NOR2X1TS U3745 ( .A(n2604), .B(n2380), .Y(n2615) );
NOR2X1TS U3746 ( .A(n2381), .B(n2615), .Y(n3035) );
NAND2X1TS U3747 ( .A(n2383), .B(n2382), .Y(n3037) );
INVX2TS U3748 ( .A(n3037), .Y(n2384) );
AOI21X2TS U3749 ( .A0(n2385), .A1(n3035), .B0(n2384), .Y(n2970) );
NOR2BX1TS U3750 ( .AN(Sgf_normalized_result[3]), .B(n2602), .Y(n2386) );
XOR2X1TS U3751 ( .A(n2403), .B(n2387), .Y(n2393) );
INVX4TS U3752 ( .A(n3518), .Y(n2410) );
NOR2X2TS U3753 ( .A(n2393), .B(n2392), .Y(n2981) );
XOR2X1TS U3754 ( .A(n2403), .B(n2388), .Y(n2395) );
NOR2X2TS U3755 ( .A(n2395), .B(n2394), .Y(n2987) );
XOR2X1TS U3756 ( .A(n2403), .B(n2389), .Y(n2397) );
NOR2X2TS U3757 ( .A(n2397), .B(n2396), .Y(n2973) );
NAND2X1TS U3758 ( .A(n2393), .B(n2392), .Y(n2982) );
OAI21X1TS U3759 ( .A0(n2981), .A1(n2993), .B0(n2982), .Y(n2971) );
NAND2X1TS U3760 ( .A(n2395), .B(n2394), .Y(n2988) );
NAND2X1TS U3761 ( .A(n2397), .B(n2396), .Y(n2974) );
AOI21X1TS U3762 ( .A0(n2971), .A1(n2399), .B0(n2398), .Y(n2400) );
XOR2X1TS U3763 ( .A(n2403), .B(n2402), .Y(n2413) );
CLKMX2X2TS U3764 ( .A(DMP[5]), .B(Sgf_normalized_result[7]), .S0(n2410), .Y(
n2412) );
NOR2X2TS U3765 ( .A(n2413), .B(n2412), .Y(n3096) );
XOR2X1TS U3766 ( .A(n2439), .B(n2404), .Y(n2415) );
NOR2X2TS U3767 ( .A(n2415), .B(n2414), .Y(n2959) );
XOR2X1TS U3768 ( .A(n2439), .B(n2405), .Y(n2417) );
XOR2X1TS U3769 ( .A(n2439), .B(n2406), .Y(n2419) );
NOR2X2TS U3770 ( .A(n2419), .B(n2418), .Y(n2947) );
NOR2X1TS U3771 ( .A(n2516), .B(n3507), .Y(n2407) );
CLKMX2X2TS U3772 ( .A(DMP[9]), .B(Sgf_normalized_result[11]), .S0(n2410),
.Y(n2422) );
NOR2X1TS U3773 ( .A(n2516), .B(n3508), .Y(n2408) );
XOR2X1TS U3774 ( .A(n2439), .B(n2408), .Y(n2425) );
NOR2X2TS U3775 ( .A(n2425), .B(n2424), .Y(n2935) );
XOR2X1TS U3776 ( .A(n2439), .B(n2409), .Y(n2427) );
CLKMX2X2TS U3777 ( .A(DMP[11]), .B(Sgf_normalized_result[13]), .S0(n2410),
.Y(n2426) );
NOR2BX1TS U3778 ( .AN(Sgf_normalized_result[14]), .B(n2601), .Y(n2411) );
XOR2X1TS U3779 ( .A(n2439), .B(n2411), .Y(n2429) );
NOR2X2TS U3780 ( .A(n2429), .B(n2428), .Y(n2920) );
NAND2X1TS U3781 ( .A(n2413), .B(n2412), .Y(n3097) );
NAND2X1TS U3782 ( .A(n2415), .B(n2414), .Y(n2960) );
OAI21X1TS U3783 ( .A0(n2959), .A1(n3097), .B0(n2960), .Y(n2942) );
NAND2X1TS U3784 ( .A(n2417), .B(n2416), .Y(n2965) );
NAND2X1TS U3785 ( .A(n2419), .B(n2418), .Y(n2948) );
OAI21X1TS U3786 ( .A0(n2947), .A1(n2965), .B0(n2948), .Y(n2420) );
NAND2X1TS U3787 ( .A(n2425), .B(n2424), .Y(n2936) );
OAI21X1TS U3788 ( .A0(n2935), .A1(n2953), .B0(n2936), .Y(n2915) );
NAND2X1TS U3789 ( .A(n2427), .B(n2426), .Y(n2926) );
NAND2X1TS U3790 ( .A(n2429), .B(n2428), .Y(n2921) );
AOI21X1TS U3791 ( .A0(n2915), .A1(n2431), .B0(n2430), .Y(n2432) );
OAI21X1TS U3792 ( .A0(n2912), .A1(n2433), .B0(n2432), .Y(n2434) );
NOR2BX1TS U3793 ( .AN(Sgf_normalized_result[15]), .B(n2601), .Y(n2436) );
XOR2X1TS U3794 ( .A(n2439), .B(n2436), .Y(n2456) );
NOR2BX1TS U3795 ( .AN(Sgf_normalized_result[16]), .B(n2601), .Y(n2437) );
XOR2X1TS U3796 ( .A(n2439), .B(n2437), .Y(n2458) );
NOR2X2TS U3797 ( .A(n2458), .B(n2457), .Y(n2905) );
XOR2X1TS U3798 ( .A(n2439), .B(n2438), .Y(n2460) );
NOR2X2TS U3799 ( .A(n2460), .B(n2459), .Y(n2895) );
XOR2X1TS U3800 ( .A(n2451), .B(n2440), .Y(n2462) );
NOR2X2TS U3801 ( .A(n2462), .B(n2461), .Y(n2889) );
NOR2X1TS U3802 ( .A(n2516), .B(n3512), .Y(n2441) );
XOR2X1TS U3803 ( .A(n2451), .B(n2441), .Y(n2466) );
NOR2X2TS U3804 ( .A(n2466), .B(n2465), .Y(n2878) );
NOR2X1TS U3805 ( .A(n2516), .B(n3513), .Y(n2442) );
XOR2X1TS U3806 ( .A(n2451), .B(n2442), .Y(n2468) );
NOR2X2TS U3807 ( .A(n2468), .B(n2467), .Y(n2622) );
NOR2X1TS U3808 ( .A(n2516), .B(n3514), .Y(n2443) );
XOR2X1TS U3809 ( .A(n2451), .B(n2443), .Y(n2470) );
NOR2X2TS U3810 ( .A(n2470), .B(n2469), .Y(n2869) );
NOR2X1TS U3811 ( .A(n2516), .B(n3515), .Y(n2444) );
XOR2X1TS U3812 ( .A(n2451), .B(n2444), .Y(n2472) );
NOR2X2TS U3813 ( .A(n2472), .B(n2471), .Y(n2871) );
NOR2X1TS U3814 ( .A(n2516), .B(n3516), .Y(n2446) );
XOR2X1TS U3815 ( .A(n2451), .B(n2446), .Y(n2478) );
CLKMX2X2TS U3816 ( .A(DMP[21]), .B(Sgf_normalized_result[23]), .S0(n2505),
.Y(n2477) );
NOR2X2TS U3817 ( .A(n2478), .B(n2477), .Y(n2856) );
NOR2BX1TS U3818 ( .AN(Sgf_normalized_result[24]), .B(n2601), .Y(n2447) );
XOR2X1TS U3819 ( .A(n2451), .B(n2447), .Y(n2480) );
NOR2X2TS U3820 ( .A(n2480), .B(n2479), .Y(n2850) );
NOR2BX1TS U3821 ( .AN(Sgf_normalized_result[25]), .B(n2513), .Y(n2448) );
XOR2X1TS U3822 ( .A(n2451), .B(n2448), .Y(n2482) );
NOR2X2TS U3823 ( .A(n2482), .B(n2481), .Y(n2843) );
NOR2BX1TS U3824 ( .AN(Sgf_normalized_result[26]), .B(n2601), .Y(n2449) );
XOR2X1TS U3825 ( .A(n2451), .B(n2449), .Y(n2484) );
NOR2X2TS U3826 ( .A(n2484), .B(n2483), .Y(n2837) );
NOR2BX1TS U3827 ( .AN(Sgf_normalized_result[27]), .B(n2513), .Y(n2450) );
XOR2X1TS U3828 ( .A(n2451), .B(n2450), .Y(n2488) );
NOR2X2TS U3829 ( .A(n2488), .B(n2487), .Y(n2829) );
NOR2BX1TS U3830 ( .AN(Sgf_normalized_result[28]), .B(n2513), .Y(n2452) );
XOR2X1TS U3831 ( .A(n2518), .B(n2452), .Y(n2490) );
NOR2X2TS U3832 ( .A(n2490), .B(n2489), .Y(n2817) );
NOR2BX1TS U3833 ( .AN(Sgf_normalized_result[29]), .B(n2602), .Y(n2453) );
XOR2X1TS U3834 ( .A(n2518), .B(n2453), .Y(n2492) );
NOR2X2TS U3835 ( .A(n2492), .B(n2491), .Y(n2823) );
NOR2BX1TS U3836 ( .AN(Sgf_normalized_result[30]), .B(n2513), .Y(n2454) );
XOR2X1TS U3837 ( .A(n2518), .B(n2454), .Y(n2494) );
NOR2X2TS U3838 ( .A(n2494), .B(n2493), .Y(n2769) );
NOR2X4TS U3839 ( .A(n2763), .B(n2498), .Y(n2500) );
NAND2X2TS U3840 ( .A(n2762), .B(n2500), .Y(n2502) );
NAND2X1TS U3841 ( .A(n2458), .B(n2457), .Y(n2906) );
OAI21X1TS U3842 ( .A0(n2905), .A1(n2901), .B0(n2906), .Y(n2887) );
NAND2X1TS U3843 ( .A(n2460), .B(n2459), .Y(n2896) );
NAND2X1TS U3844 ( .A(n2462), .B(n2461), .Y(n2890) );
OAI21X1TS U3845 ( .A0(n2889), .A1(n2896), .B0(n2890), .Y(n2463) );
AOI21X2TS U3846 ( .A0(n2887), .A1(n2464), .B0(n2463), .Y(n2619) );
NAND2X1TS U3847 ( .A(n2466), .B(n2465), .Y(n2879) );
NAND2X1TS U3848 ( .A(n2468), .B(n2467), .Y(n2623) );
OAI21X1TS U3849 ( .A0(n2622), .A1(n2879), .B0(n2623), .Y(n2863) );
NAND2X1TS U3850 ( .A(n2470), .B(n2469), .Y(n2868) );
NAND2X1TS U3851 ( .A(n2472), .B(n2471), .Y(n2872) );
AOI21X1TS U3852 ( .A0(n2863), .A1(n2474), .B0(n2473), .Y(n2475) );
NAND2X1TS U3853 ( .A(n2478), .B(n2477), .Y(n2857) );
NAND2X1TS U3854 ( .A(n2480), .B(n2479), .Y(n2851) );
NAND2X1TS U3855 ( .A(n2482), .B(n2481), .Y(n2844) );
NAND2X1TS U3856 ( .A(n2484), .B(n2483), .Y(n2838) );
OAI21X1TS U3857 ( .A0(n2837), .A1(n2844), .B0(n2838), .Y(n2485) );
AOI21X1TS U3858 ( .A0(n2835), .A1(n2486), .B0(n2485), .Y(n2764) );
NAND2X1TS U3859 ( .A(n2488), .B(n2487), .Y(n2830) );
NAND2X1TS U3860 ( .A(n2490), .B(n2489), .Y(n2818) );
NAND2X1TS U3861 ( .A(n2492), .B(n2491), .Y(n2824) );
NAND2X1TS U3862 ( .A(n2494), .B(n2493), .Y(n2770) );
AOI21X1TS U3863 ( .A0(n2767), .A1(n2496), .B0(n2495), .Y(n2497) );
AOI21X2TS U3864 ( .A0(n2761), .A1(n2500), .B0(n2499), .Y(n2501) );
OAI21X4TS U3865 ( .A0(n2617), .A1(n2502), .B0(n2501), .Y(n2661) );
INVX4TS U3866 ( .A(n2596), .Y(n2583) );
CLKMX2X2TS U3867 ( .A(DMP[29]), .B(Sgf_normalized_result[31]), .S0(n2505),
.Y(n2526) );
NOR2X2TS U3868 ( .A(n2527), .B(n2526), .Y(n2791) );
NOR2BX1TS U3869 ( .AN(Sgf_normalized_result[32]), .B(n2513), .Y(n2504) );
XOR2X1TS U3870 ( .A(n2518), .B(n2504), .Y(n2529) );
CLKMX2X2TS U3871 ( .A(DMP[30]), .B(Sgf_normalized_result[32]), .S0(n2505),
.Y(n2528) );
NOR2X2TS U3872 ( .A(n2529), .B(n2528), .Y(n2785) );
NOR2BX1TS U3873 ( .AN(Sgf_normalized_result[33]), .B(n2602), .Y(n2506) );
XOR2X1TS U3874 ( .A(n2518), .B(n2506), .Y(n2531) );
NOR2BX1TS U3875 ( .AN(Sgf_normalized_result[34]), .B(n2602), .Y(n2507) );
XOR2X1TS U3876 ( .A(n2518), .B(n2507), .Y(n2533) );
NOR2X2TS U3877 ( .A(n2533), .B(n2532), .Y(n2745) );
NOR2X2TS U3878 ( .A(n2743), .B(n2745), .Y(n2535) );
NAND2X2TS U3879 ( .A(n2739), .B(n2535), .Y(n2752) );
NOR2BX1TS U3880 ( .AN(Sgf_normalized_result[35]), .B(n2513), .Y(n2508) );
XOR2X1TS U3881 ( .A(n2518), .B(n2508), .Y(n2537) );
NOR2BX1TS U3882 ( .AN(Sgf_normalized_result[36]), .B(n2513), .Y(n2509) );
XOR2X1TS U3883 ( .A(n2518), .B(n2509), .Y(n2539) );
NOR2X2TS U3884 ( .A(n2539), .B(n2538), .Y(n2755) );
NOR2X2TS U3885 ( .A(n2753), .B(n2755), .Y(n2797) );
NOR2BX1TS U3886 ( .AN(Sgf_normalized_result[37]), .B(n2513), .Y(n2510) );
XOR2X1TS U3887 ( .A(n2525), .B(n2510), .Y(n2541) );
NOR2BX1TS U3888 ( .AN(Sgf_normalized_result[38]), .B(n2602), .Y(n2511) );
XOR2X1TS U3889 ( .A(n2525), .B(n2511), .Y(n2543) );
NOR2X2TS U3890 ( .A(n2543), .B(n2542), .Y(n2804) );
NOR2X2TS U3891 ( .A(n2802), .B(n2804), .Y(n2545) );
NAND2X2TS U3892 ( .A(n2797), .B(n2545), .Y(n2547) );
NOR2BX1TS U3893 ( .AN(Sgf_normalized_result[39]), .B(n2513), .Y(n2512) );
XOR2X1TS U3894 ( .A(n2525), .B(n2512), .Y(n2549) );
NOR2BX1TS U3895 ( .AN(Sgf_normalized_result[40]), .B(n2513), .Y(n2514) );
XOR2X1TS U3896 ( .A(n2525), .B(n2515), .Y(n2553) );
NOR2X1TS U3897 ( .A(n2516), .B(n3499), .Y(n2517) );
XOR2X1TS U3898 ( .A(n2518), .B(n2517), .Y(n2555) );
NOR2X2TS U3899 ( .A(n2555), .B(n2554), .Y(n2708) );
NOR2X1TS U3900 ( .A(n3496), .B(n2583), .Y(n2520) );
XOR2X1TS U3901 ( .A(n2525), .B(n2520), .Y(n2559) );
INVX4TS U3902 ( .A(n2596), .Y(n2592) );
NOR2X1TS U3903 ( .A(n2559), .B(n2558), .Y(n2685) );
NOR2X1TS U3904 ( .A(n3495), .B(n2583), .Y(n2521) );
XOR2X1TS U3905 ( .A(n2525), .B(n2521), .Y(n2561) );
NOR2X2TS U3906 ( .A(n2561), .B(n2560), .Y(n2688) );
NOR2X1TS U3907 ( .A(n3494), .B(n2583), .Y(n2522) );
XOR2X1TS U3908 ( .A(n2525), .B(n2522), .Y(n2563) );
NOR2X1TS U3909 ( .A(n3493), .B(n2583), .Y(n2523) );
XOR2X1TS U3910 ( .A(n2525), .B(n2523), .Y(n2565) );
NOR2X2TS U3911 ( .A(n2565), .B(n2564), .Y(n2674) );
XOR2X1TS U3912 ( .A(n2525), .B(n2524), .Y(n2573) );
NOR2X2TS U3913 ( .A(n2573), .B(n2572), .Y(n2696) );
NAND2X1TS U3914 ( .A(n2527), .B(n2526), .Y(n2792) );
NAND2X1TS U3915 ( .A(n2529), .B(n2528), .Y(n2786) );
OAI21X1TS U3916 ( .A0(n2785), .A1(n2792), .B0(n2786), .Y(n2740) );
NAND2X1TS U3917 ( .A(n2531), .B(n2530), .Y(n2775) );
NAND2X1TS U3918 ( .A(n2533), .B(n2532), .Y(n2746) );
OAI21X1TS U3919 ( .A0(n2745), .A1(n2775), .B0(n2746), .Y(n2534) );
AOI21X2TS U3920 ( .A0(n2740), .A1(n2535), .B0(n2534), .Y(n2751) );
NAND2X1TS U3921 ( .A(n2537), .B(n2536), .Y(n2781) );
NAND2X1TS U3922 ( .A(n2539), .B(n2538), .Y(n2756) );
NAND2X1TS U3923 ( .A(n2541), .B(n2540), .Y(n2811) );
NAND2X1TS U3924 ( .A(n2543), .B(n2542), .Y(n2805) );
AOI21X1TS U3925 ( .A0(n2798), .A1(n2545), .B0(n2544), .Y(n2546) );
NAND2X1TS U3926 ( .A(n2553), .B(n2552), .Y(n2719) );
NAND2X1TS U3927 ( .A(n2555), .B(n2554), .Y(n2709) );
OAI21X1TS U3928 ( .A0(n2708), .A1(n2719), .B0(n2709), .Y(n2556) );
AOI21X1TS U3929 ( .A0(n2703), .A1(n2557), .B0(n2556), .Y(n2666) );
NAND2X1TS U3930 ( .A(n2559), .B(n2558), .Y(n2714) );
NAND2X1TS U3931 ( .A(n2561), .B(n2560), .Y(n2689) );
OAI21X1TS U3932 ( .A0(n2688), .A1(n2714), .B0(n2689), .Y(n2669) );
NAND2X1TS U3933 ( .A(n2563), .B(n2562), .Y(n2680) );
NAND2X1TS U3934 ( .A(n2565), .B(n2564), .Y(n2675) );
AOI21X1TS U3935 ( .A0(n2669), .A1(n2567), .B0(n2566), .Y(n2568) );
OAI21X2TS U3936 ( .A0(n2666), .A1(n2569), .B0(n2568), .Y(n2570) );
AOI21X4TS U3937 ( .A0(n2663), .A1(n2571), .B0(n2570), .Y(n2694) );
NAND2X1TS U3938 ( .A(n2573), .B(n2572), .Y(n2697) );
AOI21X4TS U3939 ( .A0(n2661), .A1(n2575), .B0(n2574), .Y(n2632) );
XOR2X1TS U3940 ( .A(n2604), .B(n2576), .Y(n2578) );
NAND2X1TS U3941 ( .A(n2578), .B(n2577), .Y(n2629) );
OAI21X4TS U3942 ( .A0(n2632), .A1(n2628), .B0(n2629), .Y(n2637) );
XOR2X1TS U3943 ( .A(n2604), .B(n2579), .Y(n2581) );
NAND2X1TS U3944 ( .A(n2581), .B(n2580), .Y(n2634) );
INVX2TS U3945 ( .A(n2634), .Y(n2582) );
AOI21X4TS U3946 ( .A0(n2637), .A1(n2635), .B0(n2582), .Y(n2643) );
XOR2X1TS U3947 ( .A(n2604), .B(n2584), .Y(n2586) );
NOR2X1TS U3948 ( .A(n2586), .B(n2585), .Y(n2639) );
NAND2X1TS U3949 ( .A(n2586), .B(n2585), .Y(n2640) );
OAI21X4TS U3950 ( .A0(n2643), .A1(n2639), .B0(n2640), .Y(n2653) );
XOR2X1TS U3951 ( .A(n2604), .B(n2587), .Y(n2589) );
NAND2X1TS U3952 ( .A(n2589), .B(n2588), .Y(n2650) );
INVX2TS U3953 ( .A(n2650), .Y(n2590) );
AOI21X4TS U3954 ( .A0(n2653), .A1(n2651), .B0(n2590), .Y(n2659) );
XOR2X1TS U3955 ( .A(n2604), .B(n2591), .Y(n2594) );
NOR2X1TS U3956 ( .A(n2594), .B(n2593), .Y(n2655) );
NAND2X1TS U3957 ( .A(n2594), .B(n2593), .Y(n2656) );
OAI21X4TS U3958 ( .A0(n2659), .A1(n2655), .B0(n2656), .Y(n2648) );
XOR2X1TS U3959 ( .A(n2604), .B(n2595), .Y(n2599) );
NAND2X1TS U3960 ( .A(n2599), .B(n2598), .Y(n2645) );
INVX2TS U3961 ( .A(n2645), .Y(n2600) );
AOI21X4TS U3962 ( .A0(n2648), .A1(n2646), .B0(n2600), .Y(n2612) );
INVX2TS U3963 ( .A(n2610), .Y(n2605) );
NOR2BX1TS U3964 ( .AN(Sgf_normalized_result[54]), .B(n2602), .Y(n2603) );
XNOR2X1TS U3965 ( .A(n2604), .B(n2603), .Y(n2609) );
XNOR2X1TS U3966 ( .A(n2607), .B(n2606), .Y(n2608) );
CLKMX2X2TS U3967 ( .A(add_overflow_flag), .B(n2608), .S0(n2930), .Y(n463) );
NAND2X1TS U3968 ( .A(n2610), .B(n2609), .Y(n2611) );
XOR2X1TS U3969 ( .A(n2612), .B(n2611), .Y(n2613) );
XNOR2X1TS U3970 ( .A(n2615), .B(n2614), .Y(n2616) );
INVX4TS U3971 ( .A(n2617), .Y(n2904) );
INVX2TS U3972 ( .A(n2618), .Y(n2621) );
INVX2TS U3973 ( .A(n2619), .Y(n2620) );
INVX2TS U3974 ( .A(n2622), .Y(n2624) );
NAND2X1TS U3975 ( .A(n2624), .B(n2623), .Y(n2625) );
XNOR2X1TS U3976 ( .A(n2626), .B(n2625), .Y(n2627) );
INVX2TS U3977 ( .A(n2628), .Y(n2630) );
NAND2X1TS U3978 ( .A(n2630), .B(n2629), .Y(n2631) );
XOR2X1TS U3979 ( .A(n2632), .B(n2631), .Y(n2633) );
NAND2X1TS U3980 ( .A(n2635), .B(n2634), .Y(n2636) );
XNOR2X1TS U3981 ( .A(n2637), .B(n2636), .Y(n2638) );
INVX2TS U3982 ( .A(n2639), .Y(n2641) );
NAND2X1TS U3983 ( .A(n2641), .B(n2640), .Y(n2642) );
XOR2X1TS U3984 ( .A(n2643), .B(n2642), .Y(n2644) );
NAND2X1TS U3985 ( .A(n2646), .B(n2645), .Y(n2647) );
XNOR2X1TS U3986 ( .A(n2648), .B(n2647), .Y(n2649) );
NAND2X1TS U3987 ( .A(n2651), .B(n2650), .Y(n2652) );
XNOR2X1TS U3988 ( .A(n2653), .B(n2652), .Y(n2654) );
INVX2TS U3989 ( .A(n2655), .Y(n2657) );
NAND2X1TS U3990 ( .A(n2657), .B(n2656), .Y(n2658) );
XOR2X1TS U3991 ( .A(n2659), .B(n2658), .Y(n2660) );
INVX6TS U3992 ( .A(n2661), .Y(n2795) );
INVX2TS U3993 ( .A(n2662), .Y(n2665) );
INVX2TS U3994 ( .A(n2663), .Y(n2664) );
OAI21X4TS U3995 ( .A0(n2795), .A1(n2665), .B0(n2664), .Y(n2727) );
INVX2TS U3996 ( .A(n2668), .Y(n2671) );
INVX2TS U3997 ( .A(n2669), .Y(n2670) );
OAI21X4TS U3998 ( .A0(n2717), .A1(n2671), .B0(n2670), .Y(n2683) );
INVX2TS U3999 ( .A(n2672), .Y(n2681) );
INVX2TS U4000 ( .A(n2680), .Y(n2673) );
AOI21X1TS U4001 ( .A0(n2683), .A1(n2681), .B0(n2673), .Y(n2678) );
INVX2TS U4002 ( .A(n2674), .Y(n2676) );
NAND2X1TS U4003 ( .A(n2676), .B(n2675), .Y(n2677) );
XOR2X1TS U4004 ( .A(n2678), .B(n2677), .Y(n2679) );
NAND2X1TS U4005 ( .A(n2681), .B(n2680), .Y(n2682) );
XNOR2X1TS U4006 ( .A(n2683), .B(n2682), .Y(n2684) );
INVX2TS U4007 ( .A(n2685), .Y(n2715) );
INVX2TS U4008 ( .A(n2714), .Y(n2686) );
AOI21X1TS U4009 ( .A0(n2687), .A1(n2715), .B0(n2686), .Y(n2692) );
INVX2TS U4010 ( .A(n2688), .Y(n2690) );
NAND2X1TS U4011 ( .A(n2690), .B(n2689), .Y(n2691) );
XOR2X1TS U4012 ( .A(n2692), .B(n2691), .Y(n2693) );
INVX2TS U4013 ( .A(n2696), .Y(n2698) );
NAND2X1TS U4014 ( .A(n2698), .B(n2697), .Y(n2699) );
XNOR2X1TS U4015 ( .A(n2700), .B(n2699), .Y(n2701) );
INVX2TS U4016 ( .A(n2702), .Y(n2705) );
INVX2TS U4017 ( .A(n2703), .Y(n2704) );
INVX2TS U4018 ( .A(n2706), .Y(n2720) );
INVX2TS U4019 ( .A(n2719), .Y(n2707) );
AOI21X1TS U4020 ( .A0(n2722), .A1(n2720), .B0(n2707), .Y(n2712) );
INVX2TS U4021 ( .A(n2708), .Y(n2710) );
NAND2X1TS U4022 ( .A(n2710), .B(n2709), .Y(n2711) );
XOR2X1TS U4023 ( .A(n2712), .B(n2711), .Y(n2713) );
NAND2X1TS U4024 ( .A(n2715), .B(n2714), .Y(n2716) );
XOR2X1TS U4025 ( .A(n2717), .B(n2716), .Y(n2718) );
NAND2X1TS U4026 ( .A(n2720), .B(n2719), .Y(n2721) );
XNOR2X1TS U4027 ( .A(n2722), .B(n2721), .Y(n2724) );
INVX2TS U4028 ( .A(n2725), .Y(n2735) );
INVX2TS U4029 ( .A(n2734), .Y(n2726) );
AOI21X1TS U4030 ( .A0(n2727), .A1(n2735), .B0(n2726), .Y(n2732) );
NAND2X1TS U4031 ( .A(n2730), .B(n2729), .Y(n2731) );
XOR2X1TS U4032 ( .A(n2732), .B(n2731), .Y(n2733) );
NAND2X1TS U4033 ( .A(n2735), .B(n2734), .Y(n2736) );
XOR2X1TS U4034 ( .A(n2737), .B(n2736), .Y(n2738) );
INVX2TS U4035 ( .A(n2739), .Y(n2742) );
INVX2TS U4036 ( .A(n2740), .Y(n2741) );
OAI21X1TS U4037 ( .A0(n2795), .A1(n2742), .B0(n2741), .Y(n2778) );
INVX2TS U4038 ( .A(n2743), .Y(n2776) );
INVX2TS U4039 ( .A(n2775), .Y(n2744) );
AOI21X1TS U4040 ( .A0(n2778), .A1(n2776), .B0(n2744), .Y(n2749) );
NAND2X1TS U4041 ( .A(n2747), .B(n2746), .Y(n2748) );
XOR2X1TS U4042 ( .A(n2749), .B(n2748), .Y(n2750) );
OAI21X2TS U4043 ( .A0(n2795), .A1(n2752), .B0(n2751), .Y(n2780) );
INVX2TS U4044 ( .A(n2753), .Y(n2782) );
INVX2TS U4045 ( .A(n2781), .Y(n2754) );
AOI21X1TS U4046 ( .A0(n2780), .A1(n2782), .B0(n2754), .Y(n2759) );
NAND2X1TS U4047 ( .A(n2757), .B(n2756), .Y(n2758) );
XOR2X1TS U4048 ( .A(n2759), .B(n2758), .Y(n2760) );
AOI21X2TS U4049 ( .A0(n2904), .A1(n2762), .B0(n2761), .Y(n2849) );
INVX2TS U4050 ( .A(n2763), .Y(n2766) );
INVX2TS U4051 ( .A(n2764), .Y(n2765) );
AOI21X2TS U4052 ( .A0(n2860), .A1(n2766), .B0(n2765), .Y(n2816) );
INVX2TS U4053 ( .A(n2816), .Y(n2833) );
AOI21X2TS U4054 ( .A0(n2833), .A1(n2768), .B0(n2767), .Y(n2827) );
INVX2TS U4055 ( .A(n2769), .Y(n2771) );
NAND2X1TS U4056 ( .A(n2771), .B(n2770), .Y(n2772) );
CLKMX2X2TS U4057 ( .A(Add_Subt_result[30]), .B(n2774), .S0(n3101), .Y(n439)
);
NAND2X1TS U4058 ( .A(n2776), .B(n2775), .Y(n2777) );
XNOR2X1TS U4059 ( .A(n2778), .B(n2777), .Y(n2779) );
INVX2TS U4060 ( .A(n2780), .Y(n2801) );
NAND2X1TS U4061 ( .A(n2782), .B(n2781), .Y(n2783) );
XOR2X1TS U4062 ( .A(n2801), .B(n2783), .Y(n2784) );
NAND2X1TS U4063 ( .A(n2787), .B(n2786), .Y(n2788) );
XNOR2X1TS U4064 ( .A(n2789), .B(n2788), .Y(n2790) );
INVX2TS U4065 ( .A(n2791), .Y(n2793) );
NAND2X1TS U4066 ( .A(n2793), .B(n2792), .Y(n2794) );
XOR2X1TS U4067 ( .A(n2795), .B(n2794), .Y(n2796) );
INVX2TS U4068 ( .A(n2797), .Y(n2800) );
INVX2TS U4069 ( .A(n2798), .Y(n2799) );
INVX2TS U4070 ( .A(n2802), .Y(n2812) );
INVX2TS U4071 ( .A(n2811), .Y(n2803) );
NAND2X1TS U4072 ( .A(n2806), .B(n2805), .Y(n2807) );
XOR2X1TS U4073 ( .A(n2808), .B(n2807), .Y(n2810) );
NAND2X1TS U4074 ( .A(n2812), .B(n2811), .Y(n2813) );
XNOR2X1TS U4075 ( .A(n2814), .B(n2813), .Y(n2815) );
INVX2TS U4076 ( .A(n2876), .Y(n2930) );
INVX2TS U4077 ( .A(n2817), .Y(n2819) );
NAND2X1TS U4078 ( .A(n2819), .B(n2818), .Y(n2820) );
XNOR2X1TS U4079 ( .A(n2821), .B(n2820), .Y(n2822) );
INVX2TS U4080 ( .A(n2823), .Y(n2825) );
NAND2X1TS U4081 ( .A(n2825), .B(n2824), .Y(n2826) );
XOR2X1TS U4082 ( .A(n2827), .B(n2826), .Y(n2828) );
CLKMX2X2TS U4083 ( .A(Add_Subt_result[29]), .B(n2828), .S0(n2957), .Y(n438)
);
INVX2TS U4084 ( .A(n2829), .Y(n2831) );
NAND2X1TS U4085 ( .A(n2831), .B(n2830), .Y(n2832) );
XNOR2X1TS U4086 ( .A(n2833), .B(n2832), .Y(n2834) );
AOI21X1TS U4087 ( .A0(n2860), .A1(n2836), .B0(n2835), .Y(n2847) );
NAND2X1TS U4088 ( .A(n2839), .B(n2838), .Y(n2840) );
XNOR2X1TS U4089 ( .A(n2841), .B(n2840), .Y(n2842) );
INVX2TS U4090 ( .A(n2843), .Y(n2845) );
NAND2X1TS U4091 ( .A(n2845), .B(n2844), .Y(n2846) );
XOR2X1TS U4092 ( .A(n2847), .B(n2846), .Y(n2848) );
INVX2TS U4093 ( .A(n2850), .Y(n2852) );
NAND2X1TS U4094 ( .A(n2852), .B(n2851), .Y(n2853) );
XNOR2X1TS U4095 ( .A(n2854), .B(n2853), .Y(n2855) );
INVX2TS U4096 ( .A(n2856), .Y(n2858) );
NAND2X1TS U4097 ( .A(n2858), .B(n2857), .Y(n2859) );
XNOR2X1TS U4098 ( .A(n2860), .B(n2859), .Y(n2861) );
INVX2TS U4099 ( .A(n2862), .Y(n2882) );
AOI21X1TS U4100 ( .A0(n2882), .A1(n2864), .B0(n2863), .Y(n2870) );
INVX2TS U4101 ( .A(n2869), .Y(n2865) );
NAND2X1TS U4102 ( .A(n2865), .B(n2868), .Y(n2866) );
XOR2X1TS U4103 ( .A(n2870), .B(n2866), .Y(n2867) );
INVX2TS U4104 ( .A(n2871), .Y(n2873) );
NAND2X1TS U4105 ( .A(n2873), .B(n2872), .Y(n2874) );
XNOR2X1TS U4106 ( .A(n2875), .B(n2874), .Y(n2877) );
INVX2TS U4107 ( .A(n2876), .Y(n2957) );
INVX2TS U4108 ( .A(n2878), .Y(n2880) );
NAND2X1TS U4109 ( .A(n2880), .B(n2879), .Y(n2881) );
XNOR2X1TS U4110 ( .A(n2882), .B(n2881), .Y(n2883) );
INVX2TS U4111 ( .A(n2884), .Y(n2903) );
NAND2X1TS U4112 ( .A(n2903), .B(n2901), .Y(n2885) );
XNOR2X1TS U4113 ( .A(n2904), .B(n2885), .Y(n2886) );
AOI21X1TS U4114 ( .A0(n2904), .A1(n2888), .B0(n2887), .Y(n2899) );
NAND2X1TS U4115 ( .A(n2891), .B(n2890), .Y(n2892) );
XNOR2X1TS U4116 ( .A(n2893), .B(n2892), .Y(n2894) );
INVX2TS U4117 ( .A(n2895), .Y(n2897) );
NAND2X1TS U4118 ( .A(n2897), .B(n2896), .Y(n2898) );
XOR2X1TS U4119 ( .A(n2899), .B(n2898), .Y(n2900) );
AOI21X1TS U4120 ( .A0(n2904), .A1(n2903), .B0(n2902), .Y(n2909) );
NAND2X1TS U4121 ( .A(n2907), .B(n2906), .Y(n2908) );
XOR2X1TS U4122 ( .A(n2909), .B(n2908), .Y(n2910) );
INVX2TS U4123 ( .A(n2934), .Y(n2956) );
INVX2TS U4124 ( .A(n2914), .Y(n2917) );
INVX2TS U4125 ( .A(n2915), .Y(n2916) );
OAI21X1TS U4126 ( .A0(n2956), .A1(n2917), .B0(n2916), .Y(n2929) );
INVX2TS U4127 ( .A(n2918), .Y(n2927) );
INVX2TS U4128 ( .A(n2926), .Y(n2919) );
AOI21X1TS U4129 ( .A0(n2929), .A1(n2927), .B0(n2919), .Y(n2924) );
NAND2X1TS U4130 ( .A(n2922), .B(n2921), .Y(n2923) );
XOR2X1TS U4131 ( .A(n2924), .B(n2923), .Y(n2925) );
NAND2X1TS U4132 ( .A(n2927), .B(n2926), .Y(n2928) );
XNOR2X1TS U4133 ( .A(n2929), .B(n2928), .Y(n2931) );
INVX2TS U4134 ( .A(n2932), .Y(n2954) );
INVX2TS U4135 ( .A(n2953), .Y(n2933) );
AOI21X1TS U4136 ( .A0(n2934), .A1(n2954), .B0(n2933), .Y(n2939) );
INVX2TS U4137 ( .A(n2935), .Y(n2937) );
NAND2X1TS U4138 ( .A(n2937), .B(n2936), .Y(n2938) );
XOR2X1TS U4139 ( .A(n2939), .B(n2938), .Y(n2940) );
INVX2TS U4140 ( .A(n2941), .Y(n2944) );
INVX2TS U4141 ( .A(n2942), .Y(n2943) );
OAI21X1TS U4142 ( .A0(n3100), .A1(n2944), .B0(n2943), .Y(n2968) );
INVX2TS U4143 ( .A(n2945), .Y(n2966) );
INVX2TS U4144 ( .A(n2965), .Y(n2946) );
AOI21X1TS U4145 ( .A0(n2968), .A1(n2966), .B0(n2946), .Y(n2951) );
INVX2TS U4146 ( .A(n2947), .Y(n2949) );
NAND2X1TS U4147 ( .A(n2949), .B(n2948), .Y(n2950) );
XOR2X1TS U4148 ( .A(n2951), .B(n2950), .Y(n2952) );
NAND2X1TS U4149 ( .A(n2954), .B(n2953), .Y(n2955) );
XOR2X1TS U4150 ( .A(n2956), .B(n2955), .Y(n2958) );
INVX2TS U4151 ( .A(n2959), .Y(n2961) );
NAND2X1TS U4152 ( .A(n2961), .B(n2960), .Y(n2962) );
XNOR2X1TS U4153 ( .A(n2963), .B(n2962), .Y(n2964) );
NAND2X1TS U4154 ( .A(n2966), .B(n2965), .Y(n2967) );
XNOR2X1TS U4155 ( .A(n2968), .B(n2967), .Y(n2969) );
INVX2TS U4156 ( .A(n2970), .Y(n2996) );
AOI21X1TS U4157 ( .A0(n2996), .A1(n2972), .B0(n2971), .Y(n2991) );
INVX2TS U4158 ( .A(n2973), .Y(n2975) );
NAND2X1TS U4159 ( .A(n2975), .B(n2974), .Y(n2976) );
XNOR2X1TS U4160 ( .A(n2977), .B(n2976), .Y(n2978) );
INVX2TS U4161 ( .A(n2979), .Y(n2994) );
INVX2TS U4162 ( .A(n2993), .Y(n2980) );
AOI21X1TS U4163 ( .A0(n2996), .A1(n2994), .B0(n2980), .Y(n2985) );
INVX2TS U4164 ( .A(n2981), .Y(n2983) );
NAND2X1TS U4165 ( .A(n2983), .B(n2982), .Y(n2984) );
XOR2X1TS U4166 ( .A(n2985), .B(n2984), .Y(n2986) );
INVX2TS U4167 ( .A(n2987), .Y(n2989) );
NAND2X1TS U4168 ( .A(n2989), .B(n2988), .Y(n2990) );
XOR2X1TS U4169 ( .A(n2991), .B(n2990), .Y(n2992) );
NAND2X1TS U4170 ( .A(n2994), .B(n2993), .Y(n2995) );
XNOR2X1TS U4171 ( .A(n2996), .B(n2995), .Y(n2997) );
AOI21X1TS U4172 ( .A0(n3599), .A1(Add_Subt_result[39]), .B0(
Add_Subt_result[41]), .Y(n3004) );
INVX2TS U4173 ( .A(n2999), .Y(n3000) );
NAND2X1TS U4174 ( .A(n3000), .B(Add_Subt_result[5]), .Y(n3003) );
NOR2BX1TS U4175 ( .AN(Add_Subt_result[19]), .B(Add_Subt_result[20]), .Y(
n3001) );
OAI211XLTS U4176 ( .A0(Add_Subt_result[21]), .A1(n3001), .B0(n3058), .C0(
n3554), .Y(n3002) );
AOI21X1TS U4177 ( .A0(n3006), .A1(Add_Subt_result[3]), .B0(n3005), .Y(n3071)
);
INVX2TS U4178 ( .A(n3071), .Y(n3031) );
INVX2TS U4179 ( .A(n3058), .Y(n3029) );
CLKINVX1TS U4180 ( .A(n3066), .Y(n3007) );
OAI211X1TS U4181 ( .A0(n3029), .A1(n3591), .B0(n3009), .C0(n3008), .Y(n3081)
);
INVX2TS U4182 ( .A(n3048), .Y(n3019) );
AOI21X1TS U4183 ( .A0(n3011), .A1(n3561), .B0(n3010), .Y(n3018) );
INVX2TS U4184 ( .A(n3012), .Y(n3016) );
NAND2X1TS U4185 ( .A(n3020), .B(Add_Subt_result[34]), .Y(n3014) );
AOI211X1TS U4186 ( .A0(n3019), .A1(Add_Subt_result[32]), .B0(n3018), .C0(
n3017), .Y(n3028) );
NAND2X1TS U4187 ( .A(n3600), .B(Add_Subt_result[31]), .Y(n3025) );
NAND2X1TS U4188 ( .A(n3020), .B(Add_Subt_result[33]), .Y(n3053) );
AOI21X1TS U4189 ( .A0(n3589), .A1(Add_Subt_result[27]), .B0(
Add_Subt_result[29]), .Y(n3021) );
OA21XLTS U4190 ( .A0(n3027), .A1(n3574), .B0(n3026), .Y(n3142) );
OAI211X1TS U4191 ( .A0(n3029), .A1(n3554), .B0(n3028), .C0(n3142), .Y(n3030)
);
OAI31X1TS U4192 ( .A0(n3031), .A1(n3081), .A2(n3030), .B0(n3146), .Y(n3032)
);
OAI2BB1X1TS U4193 ( .A0N(LZA_output[2]), .A1N(n3151), .B0(n3032), .Y(n136)
);
MXI2X1TS U4194 ( .A(add_overflow_flag), .B(n3482), .S0(n3033), .Y(n132) );
INVX2TS U4195 ( .A(n3035), .Y(n3042) );
INVX2TS U4196 ( .A(n3036), .Y(n3038) );
NAND2X1TS U4197 ( .A(n3038), .B(n3037), .Y(n3039) );
XNOR2X1TS U4198 ( .A(n3040), .B(n3039), .Y(n3041) );
XOR2X1TS U4199 ( .A(n3043), .B(n3042), .Y(n3044) );
MXI2X1TS U4200 ( .A(n3170), .B(n3163), .S0(n3397), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[54]) );
NAND2X1TS U4201 ( .A(n3046), .B(Add_Subt_result[30]), .Y(n3047) );
AOI2BB2X1TS U4202 ( .B0(n3068), .B1(Add_Subt_result[22]), .A0N(n3048), .A1N(
n3047), .Y(n3078) );
INVX2TS U4203 ( .A(n3078), .Y(n3057) );
INVX2TS U4204 ( .A(n3050), .Y(n3141) );
AOI22X1TS U4205 ( .A0(n3141), .A1(Add_Subt_result[34]), .B0(n3052), .B1(
n3051), .Y(n3054) );
AOI211X1TS U4206 ( .A0(n3058), .A1(Add_Subt_result[21]), .B0(n3057), .C0(
n3056), .Y(n3059) );
NOR2BX1TS U4207 ( .AN(Add_Subt_result[9]), .B(n3064), .Y(n3107) );
AOI211X1TS U4208 ( .A0(n3068), .A1(Add_Subt_result[23]), .B0(n3107), .C0(
n3067), .Y(n3070) );
NAND3X1TS U4209 ( .A(n3071), .B(n3070), .C(n3069), .Y(n3148) );
OAI211XLTS U4210 ( .A0(Add_Subt_result[10]), .A1(Add_Subt_result[8]), .B0(
n3072), .C0(n3574), .Y(n3079) );
OAI31X1TS U4211 ( .A0(n3148), .A1(n3081), .A2(n3080), .B0(n3146), .Y(n3082)
);
OAI2BB1X1TS U4212 ( .A0N(LZA_output[3]), .A1N(n3151), .B0(n3082), .Y(n137)
);
AOI22X1TS U4213 ( .A0(n3186), .A1(n3367), .B0(n3175), .B1(n3253), .Y(n3085)
);
AOI22X1TS U4214 ( .A0(n3407), .A1(n3182), .B0(n3397), .B1(n3181), .Y(n3084)
);
OAI2BB1X1TS U4215 ( .A0N(n3095), .A1N(n3094), .B0(n3093), .Y(n31) );
INVX2TS U4216 ( .A(n3096), .Y(n3098) );
NAND2X1TS U4217 ( .A(n3098), .B(n3097), .Y(n3099) );
XOR2X1TS U4218 ( .A(n3100), .B(n3099), .Y(n3102) );
OAI31X1TS U4219 ( .A0(n3104), .A1(Add_Subt_result[2]), .A2(n3596), .B0(n3103), .Y(n3149) );
INVX2TS U4220 ( .A(n3132), .Y(n3105) );
AOI21X1TS U4221 ( .A0(n3106), .A1(n3576), .B0(n3105), .Y(n3108) );
AOI211X1TS U4222 ( .A0(n3109), .A1(Add_Subt_result[10]), .B0(n3108), .C0(
n3107), .Y(n3113) );
OAI2BB1X1TS U4223 ( .A0N(LZA_output[5]), .A1N(n3151), .B0(n3116), .Y(n133)
);
INVX2TS U4224 ( .A(n3118), .Y(n3120) );
NOR4BX1TS U4225 ( .AN(Add_Subt_result[37]), .B(n3134), .C(
Add_Subt_result[38]), .D(n3133), .Y(n3140) );
AOI21X1TS U4226 ( .A0(n3602), .A1(Add_Subt_result[49]), .B0(
Add_Subt_result[51]), .Y(n3135) );
OAI31X1TS U4227 ( .A0(n3138), .A1(Add_Subt_result[46]), .A2(n3604), .B0(
n3137), .Y(n3139) );
AOI211X1TS U4228 ( .A0(n3141), .A1(Add_Subt_result[35]), .B0(n3140), .C0(
n3139), .Y(n3143) );
OAI31X1TS U4229 ( .A0(n3149), .A1(n3148), .A2(n3147), .B0(n3146), .Y(n3150)
);
OAI2BB1X1TS U4230 ( .A0N(LZA_output[0]), .A1N(n3151), .B0(n3150), .Y(n134)
);
INVX2TS U4231 ( .A(n3426), .Y(n3156) );
INVX2TS U4232 ( .A(n3420), .Y(n3416) );
BUFX3TS U4233 ( .A(n1334), .Y(n3155) );
BUFX3TS U4234 ( .A(n1334), .Y(n3158) );
OAI22X1TS U4235 ( .A0(n3161), .A1(n3160), .B0(n3257), .B1(n3159), .Y(n3174)
);
INVX2TS U4236 ( .A(n3185), .Y(n3164) );
OAI22X1TS U4237 ( .A0(n3165), .A1(n3164), .B0(n3163), .B1(n3162), .Y(n3173)
);
OAI22X1TS U4238 ( .A0(n3318), .A1(n3168), .B0(n3167), .B1(n3166), .Y(n3172)
);
OAI22X1TS U4239 ( .A0(n3170), .A1(n3276), .B0(n3169), .B1(n3214), .Y(n3171)
);
OR4X2TS U4240 ( .A(n3174), .B(n3173), .C(n3172), .D(n3171), .Y(
Barrel_Shifter_module_Mux_Array_Data_array[48]) );
AOI22X1TS U4241 ( .A0(n3386), .A1(n3182), .B0(n3387), .B1(n3181), .Y(n3179)
);
AOI22X1TS U4242 ( .A0(n3186), .A1(n3405), .B0(n3380), .B1(n3184), .Y(n3178)
);
AOI22X1TS U4243 ( .A0(n3246), .A1(n3185), .B0(n3326), .B1(n3183), .Y(n3177)
);
AOI22X1TS U4244 ( .A0(n3175), .A1(n3370), .B0(n3368), .B1(n3180), .Y(n3176)
);
AOI22X1TS U4245 ( .A0(n3399), .A1(n3181), .B0(n3401), .B1(n3180), .Y(n3190)
);
AOI22X1TS U4246 ( .A0(n3407), .A1(n3183), .B0(n3405), .B1(n3182), .Y(n3189)
);
AOI22X1TS U4247 ( .A0(n3312), .A1(n3184), .B0(n3326), .B1(n3204), .Y(n3188)
);
AOI22X1TS U4248 ( .A0(n3186), .A1(n3408), .B0(n3253), .B1(n3185), .Y(n3187)
);
NAND2X1TS U4249 ( .A(n3231), .B(n3207), .Y(n3195) );
NAND2X1TS U4250 ( .A(n3219), .B(n3199), .Y(n3194) );
NAND2X1TS U4251 ( .A(n3192), .B(n3191), .Y(n3193) );
AOI22X1TS U4252 ( .A0(n3312), .A1(n3226), .B0(n3196), .B1(n3204), .Y(n3197)
);
OAI221XLTS U4253 ( .A0(n3237), .A1(n3198), .B0(n3235), .B1(n3225), .C0(n3197), .Y(Barrel_Shifter_module_Mux_Array_Data_array[40]) );
NAND2X1TS U4254 ( .A(n3219), .B(n1347), .Y(n3203) );
NAND2X1TS U4255 ( .A(n3208), .B(n3199), .Y(n3202) );
NAND2X1TS U4256 ( .A(n3231), .B(n3200), .Y(n3201) );
AOI22X1TS U4257 ( .A0(n3368), .A1(n3226), .B0(n3270), .B1(n3204), .Y(n3205)
);
OAI221XLTS U4258 ( .A0(n3237), .A1(n3206), .B0(n3235), .B1(n3230), .C0(n3205), .Y(Barrel_Shifter_module_Mux_Array_Data_array[39]) );
NAND2X1TS U4259 ( .A(n3208), .B(n3207), .Y(n3213) );
NAND2X1TS U4260 ( .A(n3227), .B(n3209), .Y(n3212) );
NAND2X1TS U4261 ( .A(n3219), .B(n3210), .Y(n3211) );
AOI22X1TS U4262 ( .A0(n3253), .A1(n3231), .B0(n3354), .B1(n3215), .Y(n3216)
);
OAI221XLTS U4263 ( .A0(n3237), .A1(n3217), .B0(n3235), .B1(n3236), .C0(n3216), .Y(Barrel_Shifter_module_Mux_Array_Data_array[38]) );
AOI22X1TS U4264 ( .A0(n3368), .A1(n3219), .B0(n3270), .B1(n3218), .Y(n3220)
);
OAI221XLTS U4265 ( .A0(n3237), .A1(n3222), .B0(n3235), .B1(n3221), .C0(n3220), .Y(Barrel_Shifter_module_Mux_Array_Data_array[37]) );
AOI22X1TS U4266 ( .A0(n3367), .A1(n3227), .B0(n3379), .B1(n3226), .Y(n3223)
);
OAI221XLTS U4267 ( .A0(n3237), .A1(n3225), .B0(n3235), .B1(n3224), .C0(n3223), .Y(Barrel_Shifter_module_Mux_Array_Data_array[36]) );
AOI22X1TS U4268 ( .A0(n3352), .A1(n3227), .B0(n3270), .B1(n3226), .Y(n3228)
);
OAI221XLTS U4269 ( .A0(n3237), .A1(n3230), .B0(n3235), .B1(n3229), .C0(n3228), .Y(Barrel_Shifter_module_Mux_Array_Data_array[35]) );
AOI22X1TS U4270 ( .A0(n3411), .A1(n3232), .B0(n3408), .B1(n3231), .Y(n3233)
);
OAI221XLTS U4271 ( .A0(n3237), .A1(n3236), .B0(n3235), .B1(n3234), .C0(n3233), .Y(Barrel_Shifter_module_Mux_Array_Data_array[34]) );
AOI22X1TS U4272 ( .A0(n3368), .A1(n3262), .B0(n3246), .B1(n3269), .Y(n3245)
);
AOI22X1TS U4273 ( .A0(n3370), .A1(n3238), .B0(n3338), .B1(n3277), .Y(n3244)
);
AOI22X1TS U4274 ( .A0(n3309), .A1(n3239), .B0(n3378), .B1(n3283), .Y(n3243)
);
NAND2X1TS U4275 ( .A(n3241), .B(n3240), .Y(n3242) );
AOI22X1TS U4276 ( .A0(n3411), .A1(n3269), .B0(n3246), .B1(n3277), .Y(n3247)
);
OAI31X1TS U4277 ( .A0(n3256), .A1(n1761), .A2(n3248), .B0(n3247), .Y(n3252)
);
INVX2TS U4278 ( .A(n3257), .Y(n3386) );
AOI22X1TS U4279 ( .A0(n3401), .A1(n3262), .B0(n3399), .B1(n3249), .Y(n3251)
);
AOI22X1TS U4280 ( .A0(n3380), .A1(n3283), .B0(n3378), .B1(n3289), .Y(n3250)
);
AOI22X1TS U4281 ( .A0(n3411), .A1(n3277), .B0(n3367), .B1(n3283), .Y(n3254)
);
OAI31X1TS U4282 ( .A0(n3256), .A1(n1761), .A2(n3255), .B0(n3254), .Y(n3260)
);
INVX2TS U4283 ( .A(n3257), .Y(n3301) );
AOI22X1TS U4284 ( .A0(n1970), .A1(n3269), .B0(n3399), .B1(n3262), .Y(n3259)
);
AOI22X1TS U4285 ( .A0(n3380), .A1(n3289), .B0(n3378), .B1(n3296), .Y(n3258)
);
AOI22X1TS U4286 ( .A0(n1970), .A1(n3283), .B0(n3386), .B1(n3277), .Y(n3266)
);
AOI22X1TS U4287 ( .A0(n3309), .A1(n3269), .B0(n3338), .B1(n3304), .Y(n3265)
);
AOI22X1TS U4288 ( .A0(n3310), .A1(Add_Subt_result[36]), .B0(DmP[16]), .B1(
n3302), .Y(n3261) );
OAI2BB1X2TS U4289 ( .A0N(Add_Subt_result[18]), .A1N(n3295), .B0(n3261), .Y(
n3313) );
AOI22X1TS U4290 ( .A0(n3246), .A1(n3296), .B0(n3326), .B1(n3313), .Y(n3264)
);
AOI22X1TS U4291 ( .A0(n3370), .A1(n3262), .B0(n3411), .B1(n3289), .Y(n3263)
);
AOI22X1TS U4292 ( .A0(n1970), .A1(n3289), .B0(n3399), .B1(n3283), .Y(n3274)
);
AOI22X1TS U4293 ( .A0(n3407), .A1(n3313), .B0(n3379), .B1(n3277), .Y(n3273)
);
AOI22X1TS U4294 ( .A0(n3310), .A1(Add_Subt_result[37]), .B0(DmP[15]), .B1(
n3302), .Y(n3267) );
OAI2BB1X2TS U4295 ( .A0N(Add_Subt_result[17]), .A1N(n3295), .B0(n3267), .Y(
n3320) );
AOI22X1TS U4296 ( .A0(n3246), .A1(n3304), .B0(n3378), .B1(n3320), .Y(n3272)
);
AOI22X1TS U4297 ( .A0(n3354), .A1(n3269), .B0(n3268), .B1(n3296), .Y(n3271)
);
AOI22X1TS U4298 ( .A0(n1970), .A1(n3296), .B0(n3301), .B1(n3289), .Y(n3281)
);
AOI22X1TS U4299 ( .A0(n3309), .A1(n3283), .B0(n3338), .B1(n3320), .Y(n3280)
);
AOI22X1TS U4300 ( .A0(n3310), .A1(Add_Subt_result[38]), .B0(DmP[14]), .B1(
n3302), .Y(n3275) );
OAI2BB1X2TS U4301 ( .A0N(Add_Subt_result[16]), .A1N(n3295), .B0(n3275), .Y(
n3327) );
AOI22X1TS U4302 ( .A0(n3367), .A1(n3313), .B0(n3326), .B1(n3327), .Y(n3279)
);
AOI22X1TS U4303 ( .A0(n3408), .A1(n3277), .B0(n3411), .B1(n3304), .Y(n3278)
);
AOI22X1TS U4304 ( .A0(n1970), .A1(n3304), .B0(n3301), .B1(n3296), .Y(n3287)
);
AOI22X1TS U4305 ( .A0(n3309), .A1(n3289), .B0(n3338), .B1(n3327), .Y(n3286)
);
AOI22X1TS U4306 ( .A0(n3310), .A1(Add_Subt_result[39]), .B0(DmP[13]), .B1(
n3302), .Y(n3282) );
OAI2BB1X2TS U4307 ( .A0N(Add_Subt_result[15]), .A1N(n3295), .B0(n3282), .Y(
n3333) );
AOI22X1TS U4308 ( .A0(n3367), .A1(n3320), .B0(n3378), .B1(n3333), .Y(n3285)
);
AOI22X1TS U4309 ( .A0(n3352), .A1(n3313), .B0(n3370), .B1(n3283), .Y(n3284)
);
AOI22X1TS U4310 ( .A0(n3387), .A1(n3313), .B0(n3301), .B1(n3304), .Y(n3293)
);
AOI22X1TS U4311 ( .A0(n3309), .A1(n3296), .B0(n3338), .B1(n3333), .Y(n3292)
);
AOI22X1TS U4312 ( .A0(n3310), .A1(Add_Subt_result[40]), .B0(DmP[12]), .B1(
n3302), .Y(n3288) );
OAI2BB1X2TS U4313 ( .A0N(Add_Subt_result[14]), .A1N(n3295), .B0(n3288), .Y(
n3340) );
AOI22X1TS U4314 ( .A0(n3246), .A1(n3327), .B0(n3378), .B1(n3340), .Y(n3291)
);
AOI22X1TS U4315 ( .A0(n3354), .A1(n3289), .B0(n3253), .B1(n3320), .Y(n3290)
);
AOI22X1TS U4316 ( .A0(n3387), .A1(n3320), .B0(n3399), .B1(n3313), .Y(n3300)
);
AOI22X1TS U4317 ( .A0(n3309), .A1(n3304), .B0(n3338), .B1(n3340), .Y(n3299)
);
AOI22X1TS U4318 ( .A0(n3310), .A1(Add_Subt_result[41]), .B0(DmP[11]), .B1(
n3302), .Y(n3294) );
OAI2BB1X2TS U4319 ( .A0N(Add_Subt_result[13]), .A1N(n3295), .B0(n3294), .Y(
n3346) );
AOI22X1TS U4320 ( .A0(n3312), .A1(n3333), .B0(n3378), .B1(n3346), .Y(n3298)
);
AOI22X1TS U4321 ( .A0(n3354), .A1(n3296), .B0(n3368), .B1(n3327), .Y(n3297)
);
AOI22X1TS U4322 ( .A0(n1970), .A1(n3327), .B0(n3386), .B1(n3320), .Y(n3308)
);
AOI22X1TS U4323 ( .A0(n3407), .A1(n3346), .B0(n3379), .B1(n3313), .Y(n3307)
);
AOI22X1TS U4324 ( .A0(n3310), .A1(Add_Subt_result[42]), .B0(DmP[10]), .B1(
n3302), .Y(n3303) );
OAI2BB1X2TS U4325 ( .A0N(Add_Subt_result[12]), .A1N(n3377), .B0(n3303), .Y(
n3353) );
AOI22X1TS U4326 ( .A0(n3367), .A1(n3340), .B0(n3326), .B1(n3353), .Y(n3306)
);
AOI22X1TS U4327 ( .A0(n3408), .A1(n3304), .B0(n3352), .B1(n3333), .Y(n3305)
);
AOI22X1TS U4328 ( .A0(n3401), .A1(n3333), .B0(n3301), .B1(n3327), .Y(n3317)
);
AOI22X1TS U4329 ( .A0(n3309), .A1(n3320), .B0(n3338), .B1(n3353), .Y(n3316)
);
AOI22X1TS U4330 ( .A0(n3310), .A1(Add_Subt_result[43]), .B0(DmP[9]), .B1(
n3365), .Y(n3311) );
OAI21X4TS U4331 ( .A0(n3574), .A1(n1756), .B0(n3311), .Y(n3360) );
AOI22X1TS U4332 ( .A0(n3403), .A1(n3346), .B0(n3326), .B1(n3360), .Y(n3315)
);
AOI22X1TS U4333 ( .A0(n3368), .A1(n3340), .B0(n3313), .B1(n3354), .Y(n3314)
);
AOI22X1TS U4334 ( .A0(n3401), .A1(n3340), .B0(n3386), .B1(n3333), .Y(n3324)
);
AOI22X1TS U4335 ( .A0(n3407), .A1(n3360), .B0(n3379), .B1(n3327), .Y(n3323)
);
BUFX3TS U4336 ( .A(n3394), .Y(n3388) );
AOI22X1TS U4337 ( .A0(n3388), .A1(Add_Subt_result[44]), .B0(DmP[8]), .B1(
n3365), .Y(n3319) );
OAI2BB1X2TS U4338 ( .A0N(Add_Subt_result[10]), .A1N(n3377), .B0(n3319), .Y(
n3369) );
AOI22X1TS U4339 ( .A0(n3312), .A1(n3353), .B0(n3326), .B1(n3369), .Y(n3322)
);
AOI22X1TS U4340 ( .A0(n3354), .A1(n3320), .B0(n3368), .B1(n3346), .Y(n3321)
);
AOI22X1TS U4341 ( .A0(n3401), .A1(n3346), .B0(n3301), .B1(n3340), .Y(n3331)
);
AOI22X1TS U4342 ( .A0(n3407), .A1(n3369), .B0(n3379), .B1(n3333), .Y(n3330)
);
AOI22X1TS U4343 ( .A0(n3388), .A1(Add_Subt_result[45]), .B0(DmP[7]), .B1(
n3365), .Y(n3325) );
OAI2BB1X2TS U4344 ( .A0N(Add_Subt_result[9]), .A1N(n3377), .B0(n3325), .Y(
n3381) );
AOI22X1TS U4345 ( .A0(n3367), .A1(n3360), .B0(n3326), .B1(n3381), .Y(n3329)
);
AOI22X1TS U4346 ( .A0(n3370), .A1(n3327), .B0(n3352), .B1(n3353), .Y(n3328)
);
AOI22X1TS U4347 ( .A0(n3401), .A1(n3353), .B0(n3399), .B1(n3346), .Y(n3337)
);
AOI22X1TS U4348 ( .A0(n3380), .A1(n3381), .B0(n3405), .B1(n3340), .Y(n3336)
);
AOI22X1TS U4349 ( .A0(n3388), .A1(Add_Subt_result[46]), .B0(DmP[6]), .B1(
n3365), .Y(n3332) );
OAI2BB1X2TS U4350 ( .A0N(Add_Subt_result[8]), .A1N(n3377), .B0(n3332), .Y(
n3389) );
AOI22X1TS U4351 ( .A0(n3246), .A1(n3369), .B0(n3397), .B1(n3389), .Y(n3335)
);
AOI22X1TS U4352 ( .A0(n3408), .A1(n3333), .B0(n3352), .B1(n3360), .Y(n3334)
);
AOI22X1TS U4353 ( .A0(n3386), .A1(n3353), .B0(n3401), .B1(n3360), .Y(n3344)
);
AOI22X1TS U4354 ( .A0(n3379), .A1(n3346), .B0(n3338), .B1(n3389), .Y(n3343)
);
AOI22X1TS U4355 ( .A0(n3388), .A1(Add_Subt_result[47]), .B0(DmP[5]), .B1(
n3365), .Y(n3339) );
OAI2BB1X2TS U4356 ( .A0N(Add_Subt_result[7]), .A1N(n3377), .B0(n3339), .Y(
n3409) );
AOI22X1TS U4357 ( .A0(n3403), .A1(n3381), .B0(n3397), .B1(n3409), .Y(n3342)
);
AOI22X1TS U4358 ( .A0(n3253), .A1(n3369), .B0(n3340), .B1(n3370), .Y(n3341)
);
AOI22X1TS U4359 ( .A0(n3387), .A1(n3369), .B0(n3301), .B1(n3360), .Y(n3350)
);
AOI22X1TS U4360 ( .A0(n3380), .A1(n3409), .B0(n3379), .B1(n3353), .Y(n3349)
);
AOI22X1TS U4361 ( .A0(n3388), .A1(Add_Subt_result[48]), .B0(DmP[4]), .B1(
n3365), .Y(n3345) );
OAI21X4TS U4362 ( .A0(n1756), .A1(n3467), .B0(n3345), .Y(n3404) );
AOI22X1TS U4363 ( .A0(n3367), .A1(n3389), .B0(n3397), .B1(n3404), .Y(n3348)
);
AOI22X1TS U4364 ( .A0(n3253), .A1(n3381), .B0(n3346), .B1(n3408), .Y(n3347)
);
AOI22X1TS U4365 ( .A0(n3387), .A1(n3381), .B0(n3386), .B1(n3369), .Y(n3358)
);
AOI22X1TS U4366 ( .A0(n3380), .A1(n3404), .B0(n3405), .B1(n3360), .Y(n3357)
);
AOI22X1TS U4367 ( .A0(n3388), .A1(Add_Subt_result[49]), .B0(DmP[3]), .B1(
n3365), .Y(n3351) );
OAI2BB1X2TS U4368 ( .A0N(Add_Subt_result[5]), .A1N(n3377), .B0(n3351), .Y(
n3398) );
AOI22X1TS U4369 ( .A0(n3246), .A1(n3409), .B0(n3397), .B1(n3398), .Y(n3356)
);
AOI22X1TS U4370 ( .A0(n3408), .A1(n3353), .B0(n3411), .B1(n3389), .Y(n3355)
);
AOI22X1TS U4371 ( .A0(n3387), .A1(n3389), .B0(n3399), .B1(n3381), .Y(n3364)
);
AOI22X1TS U4372 ( .A0(n3407), .A1(n3398), .B0(n3405), .B1(n3369), .Y(n3363)
);
AOI22X1TS U4373 ( .A0(n3388), .A1(Add_Subt_result[50]), .B0(DmP[2]), .B1(
n3365), .Y(n3359) );
OAI2BB1X2TS U4374 ( .A0N(Add_Subt_result[4]), .A1N(n3377), .B0(n3359), .Y(
n3400) );
AOI22X1TS U4375 ( .A0(n3312), .A1(n3404), .B0(n3397), .B1(n3400), .Y(n3362)
);
AOI22X1TS U4376 ( .A0(n3253), .A1(n3409), .B0(n3370), .B1(n3360), .Y(n3361)
);
AOI22X1TS U4377 ( .A0(n3399), .A1(n3389), .B0(n3401), .B1(n3409), .Y(n3374)
);
AOI22X1TS U4378 ( .A0(n3407), .A1(n3400), .B0(n3405), .B1(n3381), .Y(n3373)
);
AOI22X1TS U4379 ( .A0(n3388), .A1(Add_Subt_result[51]), .B0(DmP[1]), .B1(
n3365), .Y(n3366) );
OAI2BB1X1TS U4380 ( .A0N(Add_Subt_result[3]), .A1N(n3377), .B0(n3366), .Y(
n3410) );
AOI22X1TS U4381 ( .A0(n3403), .A1(n3398), .B0(n3378), .B1(n3410), .Y(n3372)
);
AOI22X1TS U4382 ( .A0(n3370), .A1(n3369), .B0(n3352), .B1(n3404), .Y(n3371)
);
AOI22X1TS U4383 ( .A0(n3301), .A1(n3409), .B0(n3401), .B1(n3404), .Y(n3385)
);
AOI22X1TS U4384 ( .A0(n3388), .A1(Add_Subt_result[52]), .B0(DmP[0]), .B1(
n3375), .Y(n3376) );
OAI2BB1X1TS U4385 ( .A0N(Add_Subt_result[2]), .A1N(n3377), .B0(n3376), .Y(
n3402) );
AOI22X1TS U4386 ( .A0(n3379), .A1(n3389), .B0(n3378), .B1(n3402), .Y(n3384)
);
AOI22X1TS U4387 ( .A0(n3403), .A1(n3400), .B0(n3380), .B1(n3410), .Y(n3383)
);
AOI22X1TS U4388 ( .A0(n3352), .A1(n3398), .B0(n3381), .B1(n3370), .Y(n3382)
);
AOI22X1TS U4389 ( .A0(n3387), .A1(n3398), .B0(n3301), .B1(n3404), .Y(n3393)
);
AOI22X1TS U4390 ( .A0(n3407), .A1(n3402), .B0(n3405), .B1(n3409), .Y(n3392)
);
OAI2BB2X1TS U4391 ( .B0(n3596), .B1(n1756), .A0N(Add_Subt_result[53]), .A1N(
n3388), .Y(n3406) );
AOI22X1TS U4392 ( .A0(n3312), .A1(n3410), .B0(n3397), .B1(n3406), .Y(n3391)
);
AOI22X1TS U4393 ( .A0(n3368), .A1(n3400), .B0(n3389), .B1(n3408), .Y(n3390)
);
AOI22X1TS U4394 ( .A0(n3386), .A1(n3398), .B0(n3397), .B1(n3396), .Y(n3415)
);
AOI22X1TS U4395 ( .A0(n3403), .A1(n3402), .B0(n3401), .B1(n3400), .Y(n3414)
);
AOI22X1TS U4396 ( .A0(n3407), .A1(n3406), .B0(n3405), .B1(n3404), .Y(n3413)
);
AOI22X1TS U4397 ( .A0(n3352), .A1(n3410), .B0(n3409), .B1(n3370), .Y(n3412)
);
INVX2TS U4398 ( .A(n3420), .Y(n3417) );
OAI2BB2XLTS U4399 ( .B0(n3577), .B1(n3419), .A0N(final_result_ieee[51]),
.A1N(n3417), .Y(n17) );
INVX2TS U4400 ( .A(n1334), .Y(n3423) );
OAI2BB2XLTS U4401 ( .B0(n3578), .B1(n3423), .A0N(final_result_ieee[50]),
.A1N(n3416), .Y(n24) );
INVX2TS U4402 ( .A(n1334), .Y(n3418) );
OAI2BB2XLTS U4403 ( .B0(n3557), .B1(n3418), .A0N(final_result_ieee[49]),
.A1N(n3417), .Y(n32) );
OAI2BB2XLTS U4404 ( .B0(n3558), .B1(n3418), .A0N(final_result_ieee[48]),
.A1N(n3417), .Y(n40) );
OAI2BB2XLTS U4405 ( .B0(n3542), .B1(n3418), .A0N(final_result_ieee[47]),
.A1N(n3417), .Y(n48) );
OAI2BB2XLTS U4406 ( .B0(n3543), .B1(n3418), .A0N(final_result_ieee[46]),
.A1N(n3417), .Y(n56) );
OAI2BB2XLTS U4407 ( .B0(n3492), .B1(n3418), .A0N(final_result_ieee[45]),
.A1N(n3417), .Y(n64) );
OAI2BB2XLTS U4408 ( .B0(n3493), .B1(n3418), .A0N(final_result_ieee[44]),
.A1N(n3417), .Y(n76) );
OAI2BB2XLTS U4409 ( .B0(n3494), .B1(n3418), .A0N(final_result_ieee[43]),
.A1N(n3417), .Y(n84) );
OAI2BB2XLTS U4410 ( .B0(n3498), .B1(n3418), .A0N(final_result_ieee[39]),
.A1N(n3417), .Y(n88) );
OAI2BB2XLTS U4411 ( .B0(n3495), .B1(n3418), .A0N(final_result_ieee[42]),
.A1N(n3424), .Y(n92) );
OAI2BB2XLTS U4412 ( .B0(n3499), .B1(n3418), .A0N(final_result_ieee[40]),
.A1N(n3417), .Y(n96) );
OAI2BB2XLTS U4413 ( .B0(n3496), .B1(n3419), .A0N(final_result_ieee[41]),
.A1N(n3424), .Y(n100) );
OA22X1TS U4414 ( .A0(exp_oper_result[10]), .A1(n3423), .B0(n3422), .B1(
final_result_ieee[62]), .Y(n118) );
OA22X1TS U4415 ( .A0(exp_oper_result[9]), .A1(n3423), .B0(n3422), .B1(
final_result_ieee[61]), .Y(n119) );
OA22X1TS U4416 ( .A0(exp_oper_result[8]), .A1(n3423), .B0(n3426), .B1(
final_result_ieee[60]), .Y(n120) );
OA22X1TS U4417 ( .A0(exp_oper_result[7]), .A1(n3423), .B0(n3422), .B1(
final_result_ieee[59]), .Y(n121) );
OA22X1TS U4418 ( .A0(exp_oper_result[6]), .A1(n3423), .B0(n3422), .B1(
final_result_ieee[58]), .Y(n122) );
OA22X1TS U4419 ( .A0(n3420), .A1(final_result_ieee[57]), .B0(
exp_oper_result[5]), .B1(n3423), .Y(n123) );
OA22X1TS U4420 ( .A0(n3423), .A1(exp_oper_result[4]), .B0(n3422), .B1(
final_result_ieee[56]), .Y(n124) );
INVX2TS U4421 ( .A(n1334), .Y(n3421) );
OA22X1TS U4422 ( .A0(n3422), .A1(final_result_ieee[55]), .B0(
exp_oper_result[3]), .B1(n3421), .Y(n125) );
OA22X1TS U4423 ( .A0(n3422), .A1(final_result_ieee[54]), .B0(
exp_oper_result[2]), .B1(n3421), .Y(n126) );
OA22X1TS U4424 ( .A0(n3423), .A1(exp_oper_result[1]), .B0(n3422), .B1(
final_result_ieee[53]), .Y(n127) );
OA22X1TS U4425 ( .A0(n3426), .A1(final_result_ieee[52]), .B0(
exp_oper_result[0]), .B1(n3423), .Y(n128) );
AOI21X1TS U4426 ( .A0(n3472), .A1(n3605), .B0(overflow_flag), .Y(n3425) );
BUFX3TS U4427 ( .A(n3447), .Y(n3430) );
BUFX3TS U4428 ( .A(n3441), .Y(n3440) );
OAI2BB2XLTS U4429 ( .B0(n3447), .B1(n3464), .A0N(n3440), .A1N(Data_Y[24]),
.Y(n227) );
BUFX3TS U4430 ( .A(n3441), .Y(n3431) );
BUFX3TS U4431 ( .A(n3447), .Y(n3438) );
OAI2BB2XLTS U4432 ( .B0(n3439), .B1(n3556), .A0N(n3440), .A1N(Data_X[39]),
.Y(n383) );
BUFX3TS U4433 ( .A(n3447), .Y(n3442) );
OAI2BB2XLTS U4434 ( .B0(n3442), .B1(n3575), .A0N(n3440), .A1N(Data_X[40]),
.Y(n384) );
OAI2BB2XLTS U4435 ( .B0(n3442), .B1(n3520), .A0N(n3440), .A1N(Data_X[41]),
.Y(n385) );
OAI2BB2XLTS U4436 ( .B0(n3442), .B1(n3458), .A0N(n3440), .A1N(Data_X[42]),
.Y(n386) );
OAI2BB2XLTS U4437 ( .B0(n3442), .B1(n3547), .A0N(n3440), .A1N(Data_X[43]),
.Y(n387) );
OAI2BB2XLTS U4438 ( .B0(n3442), .B1(n3454), .A0N(n3440), .A1N(Data_X[44]),
.Y(n388) );
OAI2BB2XLTS U4439 ( .B0(n3442), .B1(n3526), .A0N(n3440), .A1N(Data_X[45]),
.Y(n389) );
OAI2BB2XLTS U4440 ( .B0(n3442), .B1(n3521), .A0N(n3440), .A1N(Data_X[46]),
.Y(n390) );
OAI2BB2XLTS U4441 ( .B0(n3442), .B1(n3527), .A0N(n3440), .A1N(Data_X[47]),
.Y(n391) );
BUFX3TS U4442 ( .A(n3441), .Y(n3443) );
OAI2BB2XLTS U4443 ( .B0(n3442), .B1(n3528), .A0N(n3443), .A1N(Data_X[48]),
.Y(n392) );
OAI2BB2XLTS U4444 ( .B0(n3442), .B1(n3522), .A0N(n3443), .A1N(Data_X[49]),
.Y(n393) );
OAI2BB2XLTS U4445 ( .B0(n3445), .B1(n3459), .A0N(n3443), .A1N(Data_X[50]),
.Y(n394) );
OAI2BB2XLTS U4446 ( .B0(n3445), .B1(n3546), .A0N(n3443), .A1N(Data_X[51]),
.Y(n395) );
OAI2BB2XLTS U4447 ( .B0(n3447), .B1(n3529), .A0N(n3443), .A1N(Data_X[52]),
.Y(n396) );
OAI2BB2XLTS U4448 ( .B0(n3445), .B1(n3523), .A0N(n3443), .A1N(Data_X[53]),
.Y(n397) );
OAI2BB2XLTS U4449 ( .B0(n3445), .B1(n3530), .A0N(n3443), .A1N(Data_X[54]),
.Y(n398) );
OAI2BB2XLTS U4450 ( .B0(n3445), .B1(n3455), .A0N(n3443), .A1N(Data_X[55]),
.Y(n399) );
OAI2BB2XLTS U4451 ( .B0(n3445), .B1(n3456), .A0N(n3443), .A1N(Data_X[56]),
.Y(n400) );
OAI2BB2XLTS U4452 ( .B0(n3445), .B1(n3444), .A0N(n3443), .A1N(Data_X[57]),
.Y(n401) );
OAI2BB2XLTS U4453 ( .B0(n3447), .B1(n3524), .A0N(n3446), .A1N(Data_X[61]),
.Y(n405) );
OAI2BB2XLTS U4454 ( .B0(n3447), .B1(n3525), .A0N(n3446), .A1N(Data_X[62]),
.Y(n406) );
initial $sdf_annotate("FPU_Add_Subtract_Function_syn.sdf");
endmodule
|
//Alan Achtenberg
//Lab 7
//Part 4
module DFF_PC(Q, Qbar, C, D, PREbar, CLRbar, Wen);
input D, C, PREbar, CLRbar, Wen;
output Q, Qbar;
wire clock;
wire databar, clockbar;
wire master_nand1, master_nand2;
wire nand1, nand2;
wire master_q, master_qbar;
and #1 (clock, Wen, C);
not #1 (databar, D);
not #1 (clockbar, clock);
//Master
nand #1 m1(master_nand1,clock, D);
nand #1 m2(master_nand2,clock, databar);
nand #1 m3(master_qbar,master_nand2,master_q, CLRbar); //Clear Master
nand #1 m4(master_q,master_nand1,master_qbar, PREbar);//Clear Slave
//Slave
nand #1 s1(nand1,clockbar, master_q);
nand #1 s2(nand2,clockbar, master_qbar);
nand #1 s3(Qbar,nand2,Q, CLRbar);
nand #1 s4(Q,nand1,Qbar, PREbar);
endmodule
module m555(clock);
parameter InitDelay = 10, Ton = 50, Toff = 50;
output clock;
reg clock;
initial begin
#InitDelay clock = 1;
end
always begin
#Ton clock = ~clock;
#Toff clock = ~clock;
end
endmodule
module testD(q, qbar, clock, data, PREbar, CLRbar, Wen);
input q, qbar, clock;
output data, PREbar, CLRbar, Wen;
reg data, PREbar, CLRbar, Wen;
initial begin
$monitor ($time, " q = %d, qbar = %d, clock = %d, data = %d Wen = %d, PREbar=%d, CLRbar=%d", q, qbar, clock, data, Wen,PREbar, CLRbar);
data = 0; Wen = 1; PREbar = 1; CLRbar = 1;
#25
data = 1;
#100
data = 0;
#50
data = 1;
#50
data = 0;
#100
data = 1;
#50
data = 0;
#50
data = 1;
#100
Wen = 0;
data = 0;
#50
data = 1;
#50
data = 0;
#100
data = 1;
#50
data = 0;
#50
data = 1;
#100
Wen = 1;
data = 0;
#50
data = 1;
#50
data = 0;
#100
data = 1;
#50
data = 0;
#50
data = 1;
#100
CLRbar = 0;
data = 0;
#50
data = 1;
#50
data = 0;
#100
data = 1;
#50
data = 0;
#50
data = 1;
#100
CLRbar = 1;
PREbar = 0;
data = 0;
#50
data = 1;
#50
data = 0;
#100
data = 1;
#50
data = 0;
#50
data = 1;
#100
PREbar = 1;
data = 0;
#50
data = 1;
#50
data = 0;
#100
data = 1;
#50
data = 0;
#50
data = 1;
#100
$finish;
end
endmodule
module testBenchD;
wire clock, q, qbar, data, PREbar, CLRbar, Wen;
m555 clk(clock);
DFF_PC dff(q, qbar, clock, data, PREbar, CLRbar, Wen);
testD td(q, qbar, clock, data, PREbar, CLRbar, Wen);
endmodule
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
///////////////////////////////////////////////////////////////////////////////
// Title : DDR controller wrapper
//
// File : alt_ddrx_controller_wrapper.v
//
// Abstract : This file is a wrapper that configures DDRx controller
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
//
module ddr3_int_alt_ddrx_controller_wrapper (
ctl_clk,
ctl_reset_n,
ctl_half_clk,
ctl_half_clk_reset_n,
local_ready,
local_read_req,
local_write_req,
local_wdata_req,
local_size,
local_burstbegin,
local_addr,
local_rdata_valid,
local_rdata_error,
local_rdata,
local_wdata,
local_be,
local_autopch_req,
local_multicast,
local_init_done,
local_refresh_req,
local_refresh_chip,
local_refresh_ack,
local_self_rfsh_req,
local_self_rfsh_chip,
local_self_rfsh_ack,
local_power_down_ack,
ctl_cal_success,
ctl_cal_fail,
ctl_cal_req,
ctl_mem_clk_disable,
ctl_cal_byte_lane_sel_n,
afi_cke,
afi_cs_n,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_ba,
afi_addr,
afi_odt,
afi_rst_n,
afi_dqs_burst,
afi_wdata_valid,
afi_wdata,
afi_dm,
afi_wlat,
afi_doing_read,
afi_rdata,
afi_rdata_valid,
csr_write_req,
csr_read_req,
csr_addr,
csr_be,
csr_wdata,
csr_waitrequest,
csr_rdata,
csr_rdata_valid,
ecc_interrupt,
bank_information,
bank_open
);
//Inserted Generics
localparam MEM_TYPE = "DDR3";
localparam LOCAL_SIZE_WIDTH = 6;
localparam LOCAL_ADDR_WIDTH = 24;
localparam LOCAL_DATA_WIDTH = 128;
localparam LOCAL_IF_TYPE = "AVALON";
localparam MEM_IF_CS_WIDTH = 1;
localparam MEM_IF_CHIP_BITS = 1;
localparam MEM_IF_CKE_WIDTH = 1;
localparam MEM_IF_ODT_WIDTH = 1;
localparam MEM_IF_ADDR_WIDTH = 13;
localparam MEM_IF_ROW_WIDTH = 13;
localparam MEM_IF_COL_WIDTH = 10;
localparam MEM_IF_BA_WIDTH = 3;
localparam MEM_IF_DQS_WIDTH = 4;
localparam MEM_IF_DQ_WIDTH = 32;
localparam MEM_IF_DM_WIDTH = 4;
localparam MEM_IF_CLK_PAIR_COUNT = 1;
localparam MEM_IF_CS_PER_DIMM = 1;
localparam DWIDTH_RATIO = 4;
localparam CTL_LOOK_AHEAD_DEPTH = 8;
localparam CTL_CMD_QUEUE_DEPTH = 8;
localparam CTL_HRB_ENABLED = 0;
localparam CTL_ECC_ENABLED = 0;
localparam CTL_ECC_RMW_ENABLED = 0;
localparam CTL_ECC_CSR_ENABLED = 0;
localparam CTL_CSR_ENABLED = 0;
localparam CTL_ODT_ENABLED = 1;
localparam CSR_ADDR_WIDTH = 16;
localparam CSR_DATA_WIDTH = 32;
localparam CTL_OUTPUT_REGD = 0;
localparam MEM_CAS_WR_LAT = 7;
localparam MEM_ADD_LAT = 0;
localparam MEM_TCL = 9;
localparam MEM_TRRD = 2;
localparam MEM_TFAW = 10;
localparam MEM_TRFC = 34;
localparam MEM_TREFI = 2341;
localparam MEM_TRCD = 5;
localparam MEM_TRP = 5;
localparam MEM_TWR = 5;
localparam MEM_TWTR = 4;
localparam MEM_TRTP = 3;
localparam MEM_TRAS = 11;
localparam MEM_TRC = 15;
localparam ADDR_ORDER = 0;
localparam MEM_AUTO_PD_CYCLES = 0;
localparam MEM_IF_RD_TO_WR_TURNAROUND_OCT = 2;
localparam MEM_IF_WR_TO_RD_TURNAROUND_OCT = 0;
localparam CTL_ECC_MULTIPLES_40_72 = 0;
localparam CTL_USR_REFRESH = 0;
localparam CTL_REGDIMM_ENABLED = 0;
localparam MULTICAST_WR_EN = 0;
localparam LOW_LATENCY = 0;
localparam CTL_DYNAMIC_BANK_ALLOCATION = 0;
localparam CTL_DYNAMIC_BANK_NUM = 4;
localparam ENABLE_BURST_MERGE = 0;
input ctl_clk;
input ctl_reset_n;
input ctl_half_clk;
input ctl_half_clk_reset_n;
output local_ready;
input local_read_req;
input local_write_req;
output local_wdata_req;
input [LOCAL_SIZE_WIDTH-1:0] local_size;
input local_burstbegin;
input [LOCAL_ADDR_WIDTH-1:0] local_addr;
output local_rdata_valid;
output local_rdata_error;
output [LOCAL_DATA_WIDTH-1:0] local_rdata;
input [LOCAL_DATA_WIDTH-1:0] local_wdata;
input [LOCAL_DATA_WIDTH/8-1:0] local_be;
input local_autopch_req;
input local_multicast;
output local_init_done;
input local_refresh_req;
input [MEM_IF_CS_WIDTH-1:0] local_refresh_chip;
output local_refresh_ack;
input local_self_rfsh_req;
input [MEM_IF_CS_WIDTH-1:0] local_self_rfsh_chip;
output local_self_rfsh_ack;
output local_power_down_ack;
input ctl_cal_success;
input ctl_cal_fail;
output ctl_cal_req;
output [MEM_IF_CLK_PAIR_COUNT - 1:0] ctl_mem_clk_disable;
output [(MEM_IF_DQS_WIDTH*MEM_IF_CS_WIDTH) - 1:0] ctl_cal_byte_lane_sel_n;
output [(MEM_IF_CKE_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_cke;
output [(MEM_IF_CS_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_cs_n;
output [(DWIDTH_RATIO/2) - 1:0] afi_ras_n;
output [(DWIDTH_RATIO/2) - 1:0] afi_cas_n;
output [(DWIDTH_RATIO/2) - 1:0] afi_we_n;
output [(MEM_IF_BA_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_ba;
output [(MEM_IF_ADDR_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_addr;
output [(MEM_IF_ODT_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_odt;
output [(DWIDTH_RATIO/2) - 1:0] afi_rst_n;
output [(MEM_IF_DQS_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_dqs_burst;
output [(MEM_IF_DQS_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_wdata_valid;
output [(MEM_IF_DQ_WIDTH*DWIDTH_RATIO) - 1:0] afi_wdata;
output [(MEM_IF_DM_WIDTH*DWIDTH_RATIO) - 1:0] afi_dm;
input [4:0] afi_wlat;
output [(MEM_IF_DQS_WIDTH * (DWIDTH_RATIO/2)) - 1:0] afi_doing_read;
input [(MEM_IF_DQ_WIDTH * DWIDTH_RATIO) - 1:0] afi_rdata;
input [(DWIDTH_RATIO/2) - 1:0] afi_rdata_valid;
input csr_write_req;
input csr_read_req;
input [CSR_ADDR_WIDTH - 1 : 0] csr_addr;
input [(CSR_DATA_WIDTH / 8) - 1 : 0] csr_be;
input [CSR_DATA_WIDTH - 1 : 0] csr_wdata;
output csr_waitrequest;
output [CSR_DATA_WIDTH - 1 : 0] csr_rdata;
output csr_rdata_valid;
output ecc_interrupt;
output [(MEM_IF_CS_WIDTH * (2 ** MEM_IF_BA_WIDTH) * MEM_IF_ROW_WIDTH) - 1:0] bank_information;
output [(MEM_IF_CS_WIDTH * (2 ** MEM_IF_BA_WIDTH)) - 1:0] bank_open;
alt_ddrx_controller # (
.MEM_TYPE ( MEM_TYPE ),
.LOCAL_SIZE_WIDTH ( LOCAL_SIZE_WIDTH ),
.LOCAL_ADDR_WIDTH ( LOCAL_ADDR_WIDTH ),
.LOCAL_DATA_WIDTH ( LOCAL_DATA_WIDTH ),
.LOCAL_IF_TYPE ( LOCAL_IF_TYPE ),
.MEM_IF_CS_WIDTH ( MEM_IF_CS_WIDTH ),
.MEM_IF_CHIP_BITS ( MEM_IF_CHIP_BITS ),
.MEM_IF_CKE_WIDTH ( MEM_IF_CKE_WIDTH ),
.MEM_IF_ODT_WIDTH ( MEM_IF_ODT_WIDTH ),
.MEM_IF_ADDR_WIDTH ( MEM_IF_ADDR_WIDTH ),
.MEM_IF_ROW_WIDTH ( MEM_IF_ROW_WIDTH ),
.MEM_IF_COL_WIDTH ( MEM_IF_COL_WIDTH ),
.MEM_IF_BA_WIDTH ( MEM_IF_BA_WIDTH ),
.MEM_IF_DQS_WIDTH ( MEM_IF_DQS_WIDTH ),
.MEM_IF_DQ_WIDTH ( MEM_IF_DQ_WIDTH ),
.MEM_IF_DM_WIDTH ( MEM_IF_DM_WIDTH ),
.MEM_IF_CLK_PAIR_COUNT ( MEM_IF_CLK_PAIR_COUNT ),
.MEM_IF_CS_PER_DIMM ( MEM_IF_CS_PER_DIMM ),
.DWIDTH_RATIO ( DWIDTH_RATIO ),
.CTL_LOOK_AHEAD_DEPTH ( CTL_LOOK_AHEAD_DEPTH ),
.CTL_CMD_QUEUE_DEPTH ( CTL_CMD_QUEUE_DEPTH ),
.CTL_HRB_ENABLED ( CTL_HRB_ENABLED ),
.CTL_ECC_ENABLED ( CTL_ECC_ENABLED ),
.CTL_ECC_RMW_ENABLED ( CTL_ECC_RMW_ENABLED ),
.CTL_ECC_CSR_ENABLED ( CTL_ECC_CSR_ENABLED ),
.CTL_ECC_MULTIPLES_40_72 ( CTL_ECC_MULTIPLES_40_72 ),
.CTL_CSR_ENABLED ( CTL_CSR_ENABLED ),
.CTL_ODT_ENABLED ( CTL_ODT_ENABLED ),
.CTL_REGDIMM_ENABLED ( CTL_REGDIMM_ENABLED ),
.CSR_ADDR_WIDTH ( CSR_ADDR_WIDTH ),
.CSR_DATA_WIDTH ( CSR_DATA_WIDTH ),
.CTL_OUTPUT_REGD ( CTL_OUTPUT_REGD ),
.CTL_USR_REFRESH ( CTL_USR_REFRESH ),
.MEM_CAS_WR_LAT ( MEM_CAS_WR_LAT ),
.MEM_ADD_LAT ( MEM_ADD_LAT ),
.MEM_TCL ( MEM_TCL ),
.MEM_TRRD ( MEM_TRRD ),
.MEM_TFAW ( MEM_TFAW ),
.MEM_TRFC ( MEM_TRFC ),
.MEM_TREFI ( MEM_TREFI ),
.MEM_TRCD ( MEM_TRCD ),
.MEM_TRP ( MEM_TRP ),
.MEM_TWR ( MEM_TWR ),
.MEM_TWTR ( MEM_TWTR ),
.MEM_TRTP ( MEM_TRTP ),
.MEM_TRAS ( MEM_TRAS ),
.MEM_TRC ( MEM_TRC ),
.MEM_AUTO_PD_CYCLES ( MEM_AUTO_PD_CYCLES ),
.MEM_IF_RD_TO_WR_TURNAROUND_OCT ( MEM_IF_RD_TO_WR_TURNAROUND_OCT ),
.MEM_IF_WR_TO_RD_TURNAROUND_OCT ( MEM_IF_WR_TO_RD_TURNAROUND_OCT ),
.ADDR_ORDER ( ADDR_ORDER ),
.MULTICAST_WR_EN ( MULTICAST_WR_EN ),
.LOW_LATENCY ( LOW_LATENCY ),
.CTL_DYNAMIC_BANK_ALLOCATION ( CTL_DYNAMIC_BANK_ALLOCATION ),
.CTL_DYNAMIC_BANK_NUM ( CTL_DYNAMIC_BANK_NUM ),
.ENABLE_BURST_MERGE ( ENABLE_BURST_MERGE )
) alt_ddrx_controller_inst (
.ctl_clk ( ctl_clk ),
.ctl_reset_n ( ctl_reset_n ),
.ctl_half_clk ( ctl_half_clk ),
.ctl_half_clk_reset_n ( ctl_half_clk_reset_n ),
.local_ready ( local_ready ),
.local_read_req ( local_read_req ),
.local_write_req ( local_write_req ),
.local_wdata_req ( local_wdata_req ),
.local_size ( local_size ),
.local_burstbegin ( local_burstbegin ),
.local_addr ( local_addr ),
.local_rdata_valid ( local_rdata_valid ),
.local_rdata_error ( local_rdata_error ),
.local_rdata ( local_rdata ),
.local_wdata ( local_wdata ),
.local_be ( local_be ),
.local_autopch_req ( local_autopch_req ),
.local_multicast ( local_multicast ),
.local_init_done ( local_init_done ),
.local_refresh_req ( local_refresh_req ),
.local_refresh_chip ( local_refresh_chip ),
.local_refresh_ack ( local_refresh_ack ),
.local_self_rfsh_req ( local_self_rfsh_req ),
.local_self_rfsh_chip ( local_self_rfsh_chip ),
.local_self_rfsh_ack ( local_self_rfsh_ack ),
.local_power_down_ack ( local_power_down_ack ),
.ctl_cal_success ( ctl_cal_success ),
.ctl_cal_fail ( ctl_cal_fail ),
.ctl_cal_req ( ctl_cal_req ),
.ctl_mem_clk_disable ( ctl_mem_clk_disable ),
.ctl_cal_byte_lane_sel_n ( ctl_cal_byte_lane_sel_n ),
.afi_cke ( afi_cke ),
.afi_cs_n ( afi_cs_n ),
.afi_ras_n ( afi_ras_n ),
.afi_cas_n ( afi_cas_n ),
.afi_we_n ( afi_we_n ),
.afi_ba ( afi_ba ),
.afi_addr ( afi_addr ),
.afi_odt ( afi_odt ),
.afi_rst_n ( afi_rst_n ),
.afi_dqs_burst ( afi_dqs_burst ),
.afi_wdata_valid ( afi_wdata_valid ),
.afi_wdata ( afi_wdata ),
.afi_dm ( afi_dm ),
.afi_wlat ( afi_wlat ),
.afi_doing_read ( afi_doing_read ),
.afi_doing_read_full ( ),
.afi_rdata ( afi_rdata ),
.afi_rdata_valid ( afi_rdata_valid ),
.csr_write_req ( csr_write_req ),
.csr_read_req ( csr_read_req ),
.csr_addr ( csr_addr ),
.csr_be ( csr_be ),
.csr_wdata ( csr_wdata ),
.csr_waitrequest ( csr_waitrequest ),
.csr_rdata ( csr_rdata ),
.csr_rdata_valid ( csr_rdata_valid ),
.ecc_interrupt ( ecc_interrupt ),
.bank_information ( bank_information ),
.bank_open ( bank_open )
);
endmodule
|
module opicorv32_rf (
ra2,
wa,
wr,
resetn,
clk,
d,
ra1,
q1,
q2
);
input [5:0] ra2;
input [5:0] wa;
input wr;
input resetn;
input clk;
input [31:0] d;
input [5:0] ra1;
output [31:0] q1;
output [31:0] q2;
/* signal declarations */
reg [31:0] _2339;
wire _2334;
wire _2335;
wire [31:0] _2337 = 32'b00000000000000000000000000000000;
wire [31:0] _2336 = 32'b00000000000000000000000000000000;
reg [31:0] _2338;
wire _2329;
wire _2330;
wire [31:0] _2332 = 32'b00000000000000000000000000000000;
wire [31:0] _2331 = 32'b00000000000000000000000000000000;
reg [31:0] _2333;
wire _2324;
wire _2325;
wire [31:0] _2327 = 32'b00000000000000000000000000000000;
wire [31:0] _2326 = 32'b00000000000000000000000000000000;
reg [31:0] _2328;
wire _2319;
wire _2320;
wire [31:0] _2322 = 32'b00000000000000000000000000000000;
wire [31:0] _2321 = 32'b00000000000000000000000000000000;
reg [31:0] _2323;
wire _2314;
wire _2315;
wire [31:0] _2317 = 32'b00000000000000000000000000000000;
wire [31:0] _2316 = 32'b00000000000000000000000000000000;
reg [31:0] _2318;
wire _2309;
wire _2310;
wire [31:0] _2312 = 32'b00000000000000000000000000000000;
wire [31:0] _2311 = 32'b00000000000000000000000000000000;
reg [31:0] _2313;
wire _2304;
wire _2305;
wire [31:0] _2307 = 32'b00000000000000000000000000000000;
wire [31:0] _2306 = 32'b00000000000000000000000000000000;
reg [31:0] _2308;
wire _2299;
wire _2300;
wire [31:0] _2302 = 32'b00000000000000000000000000000000;
wire [31:0] _2301 = 32'b00000000000000000000000000000000;
reg [31:0] _2303;
wire _2294;
wire _2295;
wire [31:0] _2297 = 32'b00000000000000000000000000000000;
wire [31:0] _2296 = 32'b00000000000000000000000000000000;
reg [31:0] _2298;
wire _2289;
wire _2290;
wire [31:0] _2292 = 32'b00000000000000000000000000000000;
wire [31:0] _2291 = 32'b00000000000000000000000000000000;
reg [31:0] _2293;
wire _2284;
wire _2285;
wire [31:0] _2287 = 32'b00000000000000000000000000000000;
wire [31:0] _2286 = 32'b00000000000000000000000000000000;
reg [31:0] _2288;
wire _2279;
wire _2280;
wire [31:0] _2282 = 32'b00000000000000000000000000000000;
wire [31:0] _2281 = 32'b00000000000000000000000000000000;
reg [31:0] _2283;
wire _2274;
wire _2275;
wire [31:0] _2277 = 32'b00000000000000000000000000000000;
wire [31:0] _2276 = 32'b00000000000000000000000000000000;
reg [31:0] _2278;
wire _2269;
wire _2270;
wire [31:0] _2272 = 32'b00000000000000000000000000000000;
wire [31:0] _2271 = 32'b00000000000000000000000000000000;
reg [31:0] _2273;
wire _2264;
wire _2265;
wire [31:0] _2267 = 32'b00000000000000000000000000000000;
wire [31:0] _2266 = 32'b00000000000000000000000000000000;
reg [31:0] _2268;
wire _2259;
wire _2260;
wire [31:0] _2262 = 32'b00000000000000000000000000000000;
wire [31:0] _2261 = 32'b00000000000000000000000000000000;
reg [31:0] _2263;
wire _2254;
wire _2255;
wire [31:0] _2257 = 32'b00000000000000000000000000000000;
wire [31:0] _2256 = 32'b00000000000000000000000000000000;
reg [31:0] _2258;
wire _2249;
wire _2250;
wire [31:0] _2252 = 32'b00000000000000000000000000000000;
wire [31:0] _2251 = 32'b00000000000000000000000000000000;
reg [31:0] _2253;
wire _2244;
wire _2245;
wire [31:0] _2247 = 32'b00000000000000000000000000000000;
wire [31:0] _2246 = 32'b00000000000000000000000000000000;
reg [31:0] _2248;
wire _2239;
wire _2240;
wire [31:0] _2242 = 32'b00000000000000000000000000000000;
wire [31:0] _2241 = 32'b00000000000000000000000000000000;
reg [31:0] _2243;
wire _2234;
wire _2235;
wire [31:0] _2237 = 32'b00000000000000000000000000000000;
wire [31:0] _2236 = 32'b00000000000000000000000000000000;
reg [31:0] _2238;
wire _2229;
wire _2230;
wire [31:0] _2232 = 32'b00000000000000000000000000000000;
wire [31:0] _2231 = 32'b00000000000000000000000000000000;
reg [31:0] _2233;
wire _2224;
wire _2225;
wire [31:0] _2227 = 32'b00000000000000000000000000000000;
wire [31:0] _2226 = 32'b00000000000000000000000000000000;
reg [31:0] _2228;
wire _2219;
wire _2220;
wire [31:0] _2222 = 32'b00000000000000000000000000000000;
wire [31:0] _2221 = 32'b00000000000000000000000000000000;
reg [31:0] _2223;
wire _2214;
wire _2215;
wire [31:0] _2217 = 32'b00000000000000000000000000000000;
wire [31:0] _2216 = 32'b00000000000000000000000000000000;
reg [31:0] _2218;
wire _2209;
wire _2210;
wire [31:0] _2212 = 32'b00000000000000000000000000000000;
wire [31:0] _2211 = 32'b00000000000000000000000000000000;
reg [31:0] _2213;
wire _2204;
wire _2205;
wire [31:0] _2207 = 32'b00000000000000000000000000000000;
wire [31:0] _2206 = 32'b00000000000000000000000000000000;
reg [31:0] _2208;
wire _2199;
wire _2200;
wire [31:0] _2202 = 32'b00000000000000000000000000000000;
wire [31:0] _2201 = 32'b00000000000000000000000000000000;
reg [31:0] _2203;
wire _2194;
wire _2195;
wire [31:0] _2197 = 32'b00000000000000000000000000000000;
wire [31:0] _2196 = 32'b00000000000000000000000000000000;
reg [31:0] _2198;
wire _2189;
wire _2190;
wire [31:0] _2192 = 32'b00000000000000000000000000000000;
wire [31:0] _2191 = 32'b00000000000000000000000000000000;
reg [31:0] _2193;
wire _2184;
wire _2185;
wire [31:0] _2187 = 32'b00000000000000000000000000000000;
wire [31:0] _2186 = 32'b00000000000000000000000000000000;
reg [31:0] _2188;
wire _2179;
wire _2180;
wire [31:0] _2182 = 32'b00000000000000000000000000000000;
wire [31:0] _2181 = 32'b00000000000000000000000000000000;
reg [31:0] _2183;
wire _2174;
wire _2175;
wire [31:0] _2177 = 32'b00000000000000000000000000000000;
wire [31:0] _2176 = 32'b00000000000000000000000000000000;
reg [31:0] _2178;
wire _2169;
wire _2170;
wire [31:0] _2172 = 32'b00000000000000000000000000000000;
wire [31:0] _2171 = 32'b00000000000000000000000000000000;
reg [31:0] _2173;
wire _2164;
wire _2165;
wire [31:0] _2167 = 32'b00000000000000000000000000000000;
wire [31:0] _2166 = 32'b00000000000000000000000000000000;
reg [31:0] _2168;
wire _1775;
wire _1778;
wire _1786;
wire _1806;
wire _1854;
wire _1966;
wire _1776;
wire _1777;
wire _1785;
wire _1805;
wire _1853;
wire _1965;
wire _1779;
wire _1781;
wire _1784;
wire _1804;
wire _1852;
wire _1964;
wire _1780;
wire _1782;
wire _1783;
wire _1803;
wire _1851;
wire _1963;
wire _1787;
wire _1790;
wire _1797;
wire _1802;
wire _1850;
wire _1962;
wire _1788;
wire _1789;
wire _1796;
wire _1801;
wire _1849;
wire _1961;
wire _1791;
wire _1793;
wire _1795;
wire _1800;
wire _1848;
wire _1960;
wire _1792;
wire _1794;
wire _1798;
wire _1799;
wire _1847;
wire _1959;
wire _1807;
wire _1810;
wire _1818;
wire _1837;
wire _1846;
wire _1958;
wire _1808;
wire _1809;
wire _1817;
wire _1836;
wire _1845;
wire _1957;
wire _1811;
wire _1813;
wire _1816;
wire _1835;
wire _1844;
wire _1956;
wire _1812;
wire _1814;
wire _1815;
wire _1834;
wire _1843;
wire _1955;
wire _1819;
wire _1822;
wire _1829;
wire _1833;
wire _1842;
wire _1954;
wire _1820;
wire _1821;
wire _1828;
wire _1832;
wire _1841;
wire _1953;
wire _1823;
wire _1825;
wire _1827;
wire _1831;
wire _1840;
wire _1952;
wire _1824;
wire _1826;
wire _1830;
wire _1838;
wire _1839;
wire _1951;
wire _1855;
wire _1858;
wire _1866;
wire _1886;
wire _1933;
wire _1950;
wire _1856;
wire _1857;
wire _1865;
wire _1885;
wire _1932;
wire _1949;
wire _1859;
wire _1861;
wire _1864;
wire _1884;
wire _1931;
wire _1948;
wire _1860;
wire _1862;
wire _1863;
wire _1883;
wire _1930;
wire _1947;
wire _1867;
wire _1870;
wire _1877;
wire _1882;
wire _1929;
wire _1946;
wire _1868;
wire _1869;
wire _1876;
wire _1881;
wire _1928;
wire _1945;
wire _1871;
wire _1873;
wire _1875;
wire _1880;
wire _1927;
wire _1944;
wire _1872;
wire _1874;
wire _1878;
wire _1879;
wire _1926;
wire _1943;
wire _1887;
wire _1890;
wire _1898;
wire _1917;
wire _1925;
wire _1942;
wire _1888;
wire _1889;
wire _1897;
wire _1916;
wire _1924;
wire _1941;
wire _1891;
wire _1893;
wire _1896;
wire _1915;
wire _1923;
wire _1940;
wire _1892;
wire _1894;
wire _1895;
wire _1914;
wire _1922;
wire _1939;
wire _1899;
wire _1902;
wire _1909;
wire _1913;
wire _1921;
wire _1938;
wire _1900;
wire _1901;
wire _1908;
wire _1912;
wire _1920;
wire _1937;
wire _1903;
wire _1905;
wire _1907;
wire _1911;
wire _1919;
wire _1936;
wire _1904;
wire _1906;
wire _1910;
wire _1918;
wire _1934;
wire _1935;
wire _1967;
wire _1970;
wire _1978;
wire _1998;
wire _2046;
wire _2157;
wire _1968;
wire _1969;
wire _1977;
wire _1997;
wire _2045;
wire _2156;
wire _1971;
wire _1973;
wire _1976;
wire _1996;
wire _2044;
wire _2155;
wire _1972;
wire _1974;
wire _1975;
wire _1995;
wire _2043;
wire _2154;
wire _1979;
wire _1982;
wire _1989;
wire _1994;
wire _2042;
wire _2153;
wire _1980;
wire _1981;
wire _1988;
wire _1993;
wire _2041;
wire _2152;
wire _1983;
wire _1985;
wire _1987;
wire _1992;
wire _2040;
wire _2151;
wire _1984;
wire _1986;
wire _1990;
wire _1991;
wire _2039;
wire _2150;
wire _1999;
wire _2002;
wire _2010;
wire _2029;
wire _2038;
wire _2149;
wire _2000;
wire _2001;
wire _2009;
wire _2028;
wire _2037;
wire _2148;
wire _2003;
wire _2005;
wire _2008;
wire _2027;
wire _2036;
wire _2147;
wire _2004;
wire _2006;
wire _2007;
wire _2026;
wire _2035;
wire _2146;
wire _2011;
wire _2014;
wire _2021;
wire _2025;
wire _2034;
wire _2145;
wire _2012;
wire _2013;
wire _2020;
wire _2024;
wire _2033;
wire _2144;
wire _2015;
wire _2017;
wire _2019;
wire _2023;
wire _2032;
wire _2143;
wire _2016;
wire _2018;
wire _2022;
wire _2030;
wire _2031;
wire _2142;
wire _2047;
wire _2050;
wire _2058;
wire _2078;
wire _2125;
wire _2141;
wire _2048;
wire _2049;
wire _2057;
wire _2077;
wire _2124;
wire _2140;
wire _2051;
wire _2053;
wire _2056;
wire _2076;
wire _2123;
wire _2139;
wire _2052;
wire _2054;
wire _2055;
wire _2075;
wire _2122;
wire _2138;
wire _2059;
wire _2062;
wire _2069;
wire _2074;
wire _2121;
wire _2137;
wire _2060;
wire _2061;
wire _2068;
wire _2073;
wire _2120;
wire _2136;
wire _2063;
wire _2065;
wire _2067;
wire _2072;
wire _2119;
wire _2135;
wire _2064;
wire _2066;
wire _2070;
wire _2071;
wire _2118;
wire _2134;
wire _2079;
wire _2082;
wire _2090;
wire _2109;
wire _2117;
wire _2133;
wire _2080;
wire _2081;
wire _2089;
wire _2108;
wire _2116;
wire _2132;
wire _2083;
wire _2085;
wire _2088;
wire _2107;
wire _2115;
wire _2131;
wire _2084;
wire _2086;
wire _2087;
wire _2106;
wire _2114;
wire _2130;
wire _2091;
wire _2094;
wire _2101;
wire _2105;
wire _2113;
wire _2129;
wire _2092;
wire _2093;
wire _2100;
wire _2104;
wire _2112;
wire _2128;
wire _2095;
wire _2097;
wire _2099;
wire _2103;
wire _2111;
wire _2127;
wire _1769;
wire _1770;
wire _2096;
wire _1771;
wire _2098;
wire _1772;
wire _2102;
wire _1773;
wire _2110;
wire _1774;
wire _2126;
wire [63:0] _2158;
wire _2159;
wire _2160;
wire [31:0] _2162 = 32'b00000000000000000000000000000000;
wire gnd = 1'b0;
wire [31:0] _2161 = 32'b00000000000000000000000000000000;
reg [31:0] _2163;
reg [31:0] _2340;
/* logic */
always @* begin
case (ra2)
0: _2339 <= _2163;
1: _2339 <= _2168;
2: _2339 <= _2173;
3: _2339 <= _2178;
4: _2339 <= _2183;
5: _2339 <= _2188;
6: _2339 <= _2193;
7: _2339 <= _2198;
8: _2339 <= _2203;
9: _2339 <= _2208;
10: _2339 <= _2213;
11: _2339 <= _2218;
12: _2339 <= _2223;
13: _2339 <= _2228;
14: _2339 <= _2233;
15: _2339 <= _2238;
16: _2339 <= _2243;
17: _2339 <= _2248;
18: _2339 <= _2253;
19: _2339 <= _2258;
20: _2339 <= _2263;
21: _2339 <= _2268;
22: _2339 <= _2273;
23: _2339 <= _2278;
24: _2339 <= _2283;
25: _2339 <= _2288;
26: _2339 <= _2293;
27: _2339 <= _2298;
28: _2339 <= _2303;
29: _2339 <= _2308;
30: _2339 <= _2313;
31: _2339 <= _2318;
32: _2339 <= _2323;
33: _2339 <= _2328;
34: _2339 <= _2333;
default: _2339 <= _2338;
endcase
end
assign _2334 = _2158[35:35];
assign _2335 = wr & _2334;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2338 <= _2336;
else
if (_2335)
_2338 <= d;
end
assign _2329 = _2158[34:34];
assign _2330 = wr & _2329;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2333 <= _2331;
else
if (_2330)
_2333 <= d;
end
assign _2324 = _2158[33:33];
assign _2325 = wr & _2324;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2328 <= _2326;
else
if (_2325)
_2328 <= d;
end
assign _2319 = _2158[32:32];
assign _2320 = wr & _2319;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2323 <= _2321;
else
if (_2320)
_2323 <= d;
end
assign _2314 = _2158[31:31];
assign _2315 = wr & _2314;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2318 <= _2316;
else
if (_2315)
_2318 <= d;
end
assign _2309 = _2158[30:30];
assign _2310 = wr & _2309;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2313 <= _2311;
else
if (_2310)
_2313 <= d;
end
assign _2304 = _2158[29:29];
assign _2305 = wr & _2304;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2308 <= _2306;
else
if (_2305)
_2308 <= d;
end
assign _2299 = _2158[28:28];
assign _2300 = wr & _2299;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2303 <= _2301;
else
if (_2300)
_2303 <= d;
end
assign _2294 = _2158[27:27];
assign _2295 = wr & _2294;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2298 <= _2296;
else
if (_2295)
_2298 <= d;
end
assign _2289 = _2158[26:26];
assign _2290 = wr & _2289;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2293 <= _2291;
else
if (_2290)
_2293 <= d;
end
assign _2284 = _2158[25:25];
assign _2285 = wr & _2284;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2288 <= _2286;
else
if (_2285)
_2288 <= d;
end
assign _2279 = _2158[24:24];
assign _2280 = wr & _2279;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2283 <= _2281;
else
if (_2280)
_2283 <= d;
end
assign _2274 = _2158[23:23];
assign _2275 = wr & _2274;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2278 <= _2276;
else
if (_2275)
_2278 <= d;
end
assign _2269 = _2158[22:22];
assign _2270 = wr & _2269;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2273 <= _2271;
else
if (_2270)
_2273 <= d;
end
assign _2264 = _2158[21:21];
assign _2265 = wr & _2264;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2268 <= _2266;
else
if (_2265)
_2268 <= d;
end
assign _2259 = _2158[20:20];
assign _2260 = wr & _2259;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2263 <= _2261;
else
if (_2260)
_2263 <= d;
end
assign _2254 = _2158[19:19];
assign _2255 = wr & _2254;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2258 <= _2256;
else
if (_2255)
_2258 <= d;
end
assign _2249 = _2158[18:18];
assign _2250 = wr & _2249;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2253 <= _2251;
else
if (_2250)
_2253 <= d;
end
assign _2244 = _2158[17:17];
assign _2245 = wr & _2244;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2248 <= _2246;
else
if (_2245)
_2248 <= d;
end
assign _2239 = _2158[16:16];
assign _2240 = wr & _2239;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2243 <= _2241;
else
if (_2240)
_2243 <= d;
end
assign _2234 = _2158[15:15];
assign _2235 = wr & _2234;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2238 <= _2236;
else
if (_2235)
_2238 <= d;
end
assign _2229 = _2158[14:14];
assign _2230 = wr & _2229;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2233 <= _2231;
else
if (_2230)
_2233 <= d;
end
assign _2224 = _2158[13:13];
assign _2225 = wr & _2224;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2228 <= _2226;
else
if (_2225)
_2228 <= d;
end
assign _2219 = _2158[12:12];
assign _2220 = wr & _2219;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2223 <= _2221;
else
if (_2220)
_2223 <= d;
end
assign _2214 = _2158[11:11];
assign _2215 = wr & _2214;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2218 <= _2216;
else
if (_2215)
_2218 <= d;
end
assign _2209 = _2158[10:10];
assign _2210 = wr & _2209;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2213 <= _2211;
else
if (_2210)
_2213 <= d;
end
assign _2204 = _2158[9:9];
assign _2205 = wr & _2204;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2208 <= _2206;
else
if (_2205)
_2208 <= d;
end
assign _2199 = _2158[8:8];
assign _2200 = wr & _2199;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2203 <= _2201;
else
if (_2200)
_2203 <= d;
end
assign _2194 = _2158[7:7];
assign _2195 = wr & _2194;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2198 <= _2196;
else
if (_2195)
_2198 <= d;
end
assign _2189 = _2158[6:6];
assign _2190 = wr & _2189;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2193 <= _2191;
else
if (_2190)
_2193 <= d;
end
assign _2184 = _2158[5:5];
assign _2185 = wr & _2184;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2188 <= _2186;
else
if (_2185)
_2188 <= d;
end
assign _2179 = _2158[4:4];
assign _2180 = wr & _2179;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2183 <= _2181;
else
if (_2180)
_2183 <= d;
end
assign _2174 = _2158[3:3];
assign _2175 = wr & _2174;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2178 <= _2176;
else
if (_2175)
_2178 <= d;
end
assign _2169 = _2158[2:2];
assign _2170 = wr & _2169;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2173 <= _2171;
else
if (_2170)
_2173 <= d;
end
assign _2164 = _2158[1:1];
assign _2165 = wr & _2164;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2168 <= _2166;
else
if (_2165)
_2168 <= d;
end
assign _1775 = ~ _1769;
assign _1778 = _1776 & _1775;
assign _1786 = _1782 & _1778;
assign _1806 = _1798 & _1786;
assign _1854 = _1838 & _1806;
assign _1966 = _1934 & _1854;
assign _1776 = ~ _1770;
assign _1777 = _1776 & _1769;
assign _1785 = _1782 & _1777;
assign _1805 = _1798 & _1785;
assign _1853 = _1838 & _1805;
assign _1965 = _1934 & _1853;
assign _1779 = ~ _1769;
assign _1781 = _1770 & _1779;
assign _1784 = _1782 & _1781;
assign _1804 = _1798 & _1784;
assign _1852 = _1838 & _1804;
assign _1964 = _1934 & _1852;
assign _1780 = _1770 & _1769;
assign _1782 = ~ _1771;
assign _1783 = _1782 & _1780;
assign _1803 = _1798 & _1783;
assign _1851 = _1838 & _1803;
assign _1963 = _1934 & _1851;
assign _1787 = ~ _1769;
assign _1790 = _1788 & _1787;
assign _1797 = _1771 & _1790;
assign _1802 = _1798 & _1797;
assign _1850 = _1838 & _1802;
assign _1962 = _1934 & _1850;
assign _1788 = ~ _1770;
assign _1789 = _1788 & _1769;
assign _1796 = _1771 & _1789;
assign _1801 = _1798 & _1796;
assign _1849 = _1838 & _1801;
assign _1961 = _1934 & _1849;
assign _1791 = ~ _1769;
assign _1793 = _1770 & _1791;
assign _1795 = _1771 & _1793;
assign _1800 = _1798 & _1795;
assign _1848 = _1838 & _1800;
assign _1960 = _1934 & _1848;
assign _1792 = _1770 & _1769;
assign _1794 = _1771 & _1792;
assign _1798 = ~ _1772;
assign _1799 = _1798 & _1794;
assign _1847 = _1838 & _1799;
assign _1959 = _1934 & _1847;
assign _1807 = ~ _1769;
assign _1810 = _1808 & _1807;
assign _1818 = _1814 & _1810;
assign _1837 = _1772 & _1818;
assign _1846 = _1838 & _1837;
assign _1958 = _1934 & _1846;
assign _1808 = ~ _1770;
assign _1809 = _1808 & _1769;
assign _1817 = _1814 & _1809;
assign _1836 = _1772 & _1817;
assign _1845 = _1838 & _1836;
assign _1957 = _1934 & _1845;
assign _1811 = ~ _1769;
assign _1813 = _1770 & _1811;
assign _1816 = _1814 & _1813;
assign _1835 = _1772 & _1816;
assign _1844 = _1838 & _1835;
assign _1956 = _1934 & _1844;
assign _1812 = _1770 & _1769;
assign _1814 = ~ _1771;
assign _1815 = _1814 & _1812;
assign _1834 = _1772 & _1815;
assign _1843 = _1838 & _1834;
assign _1955 = _1934 & _1843;
assign _1819 = ~ _1769;
assign _1822 = _1820 & _1819;
assign _1829 = _1771 & _1822;
assign _1833 = _1772 & _1829;
assign _1842 = _1838 & _1833;
assign _1954 = _1934 & _1842;
assign _1820 = ~ _1770;
assign _1821 = _1820 & _1769;
assign _1828 = _1771 & _1821;
assign _1832 = _1772 & _1828;
assign _1841 = _1838 & _1832;
assign _1953 = _1934 & _1841;
assign _1823 = ~ _1769;
assign _1825 = _1770 & _1823;
assign _1827 = _1771 & _1825;
assign _1831 = _1772 & _1827;
assign _1840 = _1838 & _1831;
assign _1952 = _1934 & _1840;
assign _1824 = _1770 & _1769;
assign _1826 = _1771 & _1824;
assign _1830 = _1772 & _1826;
assign _1838 = ~ _1773;
assign _1839 = _1838 & _1830;
assign _1951 = _1934 & _1839;
assign _1855 = ~ _1769;
assign _1858 = _1856 & _1855;
assign _1866 = _1862 & _1858;
assign _1886 = _1878 & _1866;
assign _1933 = _1773 & _1886;
assign _1950 = _1934 & _1933;
assign _1856 = ~ _1770;
assign _1857 = _1856 & _1769;
assign _1865 = _1862 & _1857;
assign _1885 = _1878 & _1865;
assign _1932 = _1773 & _1885;
assign _1949 = _1934 & _1932;
assign _1859 = ~ _1769;
assign _1861 = _1770 & _1859;
assign _1864 = _1862 & _1861;
assign _1884 = _1878 & _1864;
assign _1931 = _1773 & _1884;
assign _1948 = _1934 & _1931;
assign _1860 = _1770 & _1769;
assign _1862 = ~ _1771;
assign _1863 = _1862 & _1860;
assign _1883 = _1878 & _1863;
assign _1930 = _1773 & _1883;
assign _1947 = _1934 & _1930;
assign _1867 = ~ _1769;
assign _1870 = _1868 & _1867;
assign _1877 = _1771 & _1870;
assign _1882 = _1878 & _1877;
assign _1929 = _1773 & _1882;
assign _1946 = _1934 & _1929;
assign _1868 = ~ _1770;
assign _1869 = _1868 & _1769;
assign _1876 = _1771 & _1869;
assign _1881 = _1878 & _1876;
assign _1928 = _1773 & _1881;
assign _1945 = _1934 & _1928;
assign _1871 = ~ _1769;
assign _1873 = _1770 & _1871;
assign _1875 = _1771 & _1873;
assign _1880 = _1878 & _1875;
assign _1927 = _1773 & _1880;
assign _1944 = _1934 & _1927;
assign _1872 = _1770 & _1769;
assign _1874 = _1771 & _1872;
assign _1878 = ~ _1772;
assign _1879 = _1878 & _1874;
assign _1926 = _1773 & _1879;
assign _1943 = _1934 & _1926;
assign _1887 = ~ _1769;
assign _1890 = _1888 & _1887;
assign _1898 = _1894 & _1890;
assign _1917 = _1772 & _1898;
assign _1925 = _1773 & _1917;
assign _1942 = _1934 & _1925;
assign _1888 = ~ _1770;
assign _1889 = _1888 & _1769;
assign _1897 = _1894 & _1889;
assign _1916 = _1772 & _1897;
assign _1924 = _1773 & _1916;
assign _1941 = _1934 & _1924;
assign _1891 = ~ _1769;
assign _1893 = _1770 & _1891;
assign _1896 = _1894 & _1893;
assign _1915 = _1772 & _1896;
assign _1923 = _1773 & _1915;
assign _1940 = _1934 & _1923;
assign _1892 = _1770 & _1769;
assign _1894 = ~ _1771;
assign _1895 = _1894 & _1892;
assign _1914 = _1772 & _1895;
assign _1922 = _1773 & _1914;
assign _1939 = _1934 & _1922;
assign _1899 = ~ _1769;
assign _1902 = _1900 & _1899;
assign _1909 = _1771 & _1902;
assign _1913 = _1772 & _1909;
assign _1921 = _1773 & _1913;
assign _1938 = _1934 & _1921;
assign _1900 = ~ _1770;
assign _1901 = _1900 & _1769;
assign _1908 = _1771 & _1901;
assign _1912 = _1772 & _1908;
assign _1920 = _1773 & _1912;
assign _1937 = _1934 & _1920;
assign _1903 = ~ _1769;
assign _1905 = _1770 & _1903;
assign _1907 = _1771 & _1905;
assign _1911 = _1772 & _1907;
assign _1919 = _1773 & _1911;
assign _1936 = _1934 & _1919;
assign _1904 = _1770 & _1769;
assign _1906 = _1771 & _1904;
assign _1910 = _1772 & _1906;
assign _1918 = _1773 & _1910;
assign _1934 = ~ _1774;
assign _1935 = _1934 & _1918;
assign _1967 = ~ _1769;
assign _1970 = _1968 & _1967;
assign _1978 = _1974 & _1970;
assign _1998 = _1990 & _1978;
assign _2046 = _2030 & _1998;
assign _2157 = _1774 & _2046;
assign _1968 = ~ _1770;
assign _1969 = _1968 & _1769;
assign _1977 = _1974 & _1969;
assign _1997 = _1990 & _1977;
assign _2045 = _2030 & _1997;
assign _2156 = _1774 & _2045;
assign _1971 = ~ _1769;
assign _1973 = _1770 & _1971;
assign _1976 = _1974 & _1973;
assign _1996 = _1990 & _1976;
assign _2044 = _2030 & _1996;
assign _2155 = _1774 & _2044;
assign _1972 = _1770 & _1769;
assign _1974 = ~ _1771;
assign _1975 = _1974 & _1972;
assign _1995 = _1990 & _1975;
assign _2043 = _2030 & _1995;
assign _2154 = _1774 & _2043;
assign _1979 = ~ _1769;
assign _1982 = _1980 & _1979;
assign _1989 = _1771 & _1982;
assign _1994 = _1990 & _1989;
assign _2042 = _2030 & _1994;
assign _2153 = _1774 & _2042;
assign _1980 = ~ _1770;
assign _1981 = _1980 & _1769;
assign _1988 = _1771 & _1981;
assign _1993 = _1990 & _1988;
assign _2041 = _2030 & _1993;
assign _2152 = _1774 & _2041;
assign _1983 = ~ _1769;
assign _1985 = _1770 & _1983;
assign _1987 = _1771 & _1985;
assign _1992 = _1990 & _1987;
assign _2040 = _2030 & _1992;
assign _2151 = _1774 & _2040;
assign _1984 = _1770 & _1769;
assign _1986 = _1771 & _1984;
assign _1990 = ~ _1772;
assign _1991 = _1990 & _1986;
assign _2039 = _2030 & _1991;
assign _2150 = _1774 & _2039;
assign _1999 = ~ _1769;
assign _2002 = _2000 & _1999;
assign _2010 = _2006 & _2002;
assign _2029 = _1772 & _2010;
assign _2038 = _2030 & _2029;
assign _2149 = _1774 & _2038;
assign _2000 = ~ _1770;
assign _2001 = _2000 & _1769;
assign _2009 = _2006 & _2001;
assign _2028 = _1772 & _2009;
assign _2037 = _2030 & _2028;
assign _2148 = _1774 & _2037;
assign _2003 = ~ _1769;
assign _2005 = _1770 & _2003;
assign _2008 = _2006 & _2005;
assign _2027 = _1772 & _2008;
assign _2036 = _2030 & _2027;
assign _2147 = _1774 & _2036;
assign _2004 = _1770 & _1769;
assign _2006 = ~ _1771;
assign _2007 = _2006 & _2004;
assign _2026 = _1772 & _2007;
assign _2035 = _2030 & _2026;
assign _2146 = _1774 & _2035;
assign _2011 = ~ _1769;
assign _2014 = _2012 & _2011;
assign _2021 = _1771 & _2014;
assign _2025 = _1772 & _2021;
assign _2034 = _2030 & _2025;
assign _2145 = _1774 & _2034;
assign _2012 = ~ _1770;
assign _2013 = _2012 & _1769;
assign _2020 = _1771 & _2013;
assign _2024 = _1772 & _2020;
assign _2033 = _2030 & _2024;
assign _2144 = _1774 & _2033;
assign _2015 = ~ _1769;
assign _2017 = _1770 & _2015;
assign _2019 = _1771 & _2017;
assign _2023 = _1772 & _2019;
assign _2032 = _2030 & _2023;
assign _2143 = _1774 & _2032;
assign _2016 = _1770 & _1769;
assign _2018 = _1771 & _2016;
assign _2022 = _1772 & _2018;
assign _2030 = ~ _1773;
assign _2031 = _2030 & _2022;
assign _2142 = _1774 & _2031;
assign _2047 = ~ _1769;
assign _2050 = _2048 & _2047;
assign _2058 = _2054 & _2050;
assign _2078 = _2070 & _2058;
assign _2125 = _1773 & _2078;
assign _2141 = _1774 & _2125;
assign _2048 = ~ _1770;
assign _2049 = _2048 & _1769;
assign _2057 = _2054 & _2049;
assign _2077 = _2070 & _2057;
assign _2124 = _1773 & _2077;
assign _2140 = _1774 & _2124;
assign _2051 = ~ _1769;
assign _2053 = _1770 & _2051;
assign _2056 = _2054 & _2053;
assign _2076 = _2070 & _2056;
assign _2123 = _1773 & _2076;
assign _2139 = _1774 & _2123;
assign _2052 = _1770 & _1769;
assign _2054 = ~ _1771;
assign _2055 = _2054 & _2052;
assign _2075 = _2070 & _2055;
assign _2122 = _1773 & _2075;
assign _2138 = _1774 & _2122;
assign _2059 = ~ _1769;
assign _2062 = _2060 & _2059;
assign _2069 = _1771 & _2062;
assign _2074 = _2070 & _2069;
assign _2121 = _1773 & _2074;
assign _2137 = _1774 & _2121;
assign _2060 = ~ _1770;
assign _2061 = _2060 & _1769;
assign _2068 = _1771 & _2061;
assign _2073 = _2070 & _2068;
assign _2120 = _1773 & _2073;
assign _2136 = _1774 & _2120;
assign _2063 = ~ _1769;
assign _2065 = _1770 & _2063;
assign _2067 = _1771 & _2065;
assign _2072 = _2070 & _2067;
assign _2119 = _1773 & _2072;
assign _2135 = _1774 & _2119;
assign _2064 = _1770 & _1769;
assign _2066 = _1771 & _2064;
assign _2070 = ~ _1772;
assign _2071 = _2070 & _2066;
assign _2118 = _1773 & _2071;
assign _2134 = _1774 & _2118;
assign _2079 = ~ _1769;
assign _2082 = _2080 & _2079;
assign _2090 = _2086 & _2082;
assign _2109 = _1772 & _2090;
assign _2117 = _1773 & _2109;
assign _2133 = _1774 & _2117;
assign _2080 = ~ _1770;
assign _2081 = _2080 & _1769;
assign _2089 = _2086 & _2081;
assign _2108 = _1772 & _2089;
assign _2116 = _1773 & _2108;
assign _2132 = _1774 & _2116;
assign _2083 = ~ _1769;
assign _2085 = _1770 & _2083;
assign _2088 = _2086 & _2085;
assign _2107 = _1772 & _2088;
assign _2115 = _1773 & _2107;
assign _2131 = _1774 & _2115;
assign _2084 = _1770 & _1769;
assign _2086 = ~ _1771;
assign _2087 = _2086 & _2084;
assign _2106 = _1772 & _2087;
assign _2114 = _1773 & _2106;
assign _2130 = _1774 & _2114;
assign _2091 = ~ _1769;
assign _2094 = _2092 & _2091;
assign _2101 = _1771 & _2094;
assign _2105 = _1772 & _2101;
assign _2113 = _1773 & _2105;
assign _2129 = _1774 & _2113;
assign _2092 = ~ _1770;
assign _2093 = _2092 & _1769;
assign _2100 = _1771 & _2093;
assign _2104 = _1772 & _2100;
assign _2112 = _1773 & _2104;
assign _2128 = _1774 & _2112;
assign _2095 = ~ _1769;
assign _2097 = _1770 & _2095;
assign _2099 = _1771 & _2097;
assign _2103 = _1772 & _2099;
assign _2111 = _1773 & _2103;
assign _2127 = _1774 & _2111;
assign _1769 = wa[0:0];
assign _1770 = wa[1:1];
assign _2096 = _1770 & _1769;
assign _1771 = wa[2:2];
assign _2098 = _1771 & _2096;
assign _1772 = wa[3:3];
assign _2102 = _1772 & _2098;
assign _1773 = wa[4:4];
assign _2110 = _1773 & _2102;
assign _1774 = wa[5:5];
assign _2126 = _1774 & _2110;
assign _2158 = { _2126, _2127, _2128, _2129, _2130, _2131, _2132, _2133, _2134, _2135, _2136, _2137, _2138, _2139, _2140, _2141, _2142, _2143, _2144, _2145, _2146, _2147, _2148, _2149, _2150, _2151, _2152, _2153, _2154, _2155, _2156, _2157, _1935, _1936, _1937, _1938, _1939, _1940, _1941, _1942, _1943, _1944, _1945, _1946, _1947, _1948, _1949, _1950, _1951, _1952, _1953, _1954, _1955, _1956, _1957, _1958, _1959, _1960, _1961, _1962, _1963, _1964, _1965, _1966 };
assign _2159 = _2158[0:0];
assign _2160 = wr & _2159;
always @(posedge clk or negedge resetn) begin
if (resetn == 0)
_2163 <= _2161;
else
if (_2160)
_2163 <= d;
end
always @* begin
case (ra1)
0: _2340 <= _2163;
1: _2340 <= _2168;
2: _2340 <= _2173;
3: _2340 <= _2178;
4: _2340 <= _2183;
5: _2340 <= _2188;
6: _2340 <= _2193;
7: _2340 <= _2198;
8: _2340 <= _2203;
9: _2340 <= _2208;
10: _2340 <= _2213;
11: _2340 <= _2218;
12: _2340 <= _2223;
13: _2340 <= _2228;
14: _2340 <= _2233;
15: _2340 <= _2238;
16: _2340 <= _2243;
17: _2340 <= _2248;
18: _2340 <= _2253;
19: _2340 <= _2258;
20: _2340 <= _2263;
21: _2340 <= _2268;
22: _2340 <= _2273;
23: _2340 <= _2278;
24: _2340 <= _2283;
25: _2340 <= _2288;
26: _2340 <= _2293;
27: _2340 <= _2298;
28: _2340 <= _2303;
29: _2340 <= _2308;
30: _2340 <= _2313;
31: _2340 <= _2318;
32: _2340 <= _2323;
33: _2340 <= _2328;
34: _2340 <= _2333;
default: _2340 <= _2338;
endcase
end
/* aliases */
/* output assignments */
assign q1 = _2340;
assign q2 = _2339;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFBBN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__SDFBBN_FUNCTIONAL_PP_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_dfb_setdom_pg/sky130_fd_sc_hs__u_dfb_setdom_pg.v"
`include "../u_mux_2/sky130_fd_sc_hs__u_mux_2.v"
`celldefine
module sky130_fd_sc_hs__sdfbbn (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
not not2 (CLK , CLK_N );
sky130_fd_sc_hs__u_mux_2_1 u_mux_20 (mux_out, D, SCD, SCE );
sky130_fd_sc_hs__u_dfb_setdom_pg `UNIT_DELAY u_dfb_setdom_pg0 (buf_Q , SET, RESET, CLK, mux_out, VPWR, VGND);
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFBBN_FUNCTIONAL_PP_V |
// usb_system_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 200 at 2014.10.01.12:57:26
`timescale 1 ps / 1 ps
module usb_system_mm_interconnect_0 (
input wire clk_clk_clk, // clk_clk.clk
input wire clocks_c0_clk, // clocks_c0.clk
input wire cpu_reset_n_reset_bridge_in_reset_reset, // cpu_reset_n_reset_bridge_in_reset.reset
input wire sdram_reset_reset_bridge_in_reset_reset, // sdram_reset_reset_bridge_in_reset.reset
input wire [28:0] cpu_data_master_address, // cpu_data_master.address
output wire cpu_data_master_waitrequest, // .waitrequest
input wire [3:0] cpu_data_master_byteenable, // .byteenable
input wire cpu_data_master_read, // .read
output wire [31:0] cpu_data_master_readdata, // .readdata
input wire cpu_data_master_write, // .write
input wire [31:0] cpu_data_master_writedata, // .writedata
input wire cpu_data_master_debugaccess, // .debugaccess
input wire [28:0] cpu_instruction_master_address, // cpu_instruction_master.address
output wire cpu_instruction_master_waitrequest, // .waitrequest
input wire cpu_instruction_master_read, // .read
output wire [31:0] cpu_instruction_master_readdata, // .readdata
output wire [21:0] clock_crossing_io_s0_address, // clock_crossing_io_s0.address
output wire clock_crossing_io_s0_write, // .write
output wire clock_crossing_io_s0_read, // .read
input wire [31:0] clock_crossing_io_s0_readdata, // .readdata
output wire [31:0] clock_crossing_io_s0_writedata, // .writedata
output wire [0:0] clock_crossing_io_s0_burstcount, // .burstcount
output wire [3:0] clock_crossing_io_s0_byteenable, // .byteenable
input wire clock_crossing_io_s0_readdatavalid, // .readdatavalid
input wire clock_crossing_io_s0_waitrequest, // .waitrequest
output wire clock_crossing_io_s0_debugaccess, // .debugaccess
output wire [1:0] clocks_pll_slave_address, // clocks_pll_slave.address
output wire clocks_pll_slave_write, // .write
output wire clocks_pll_slave_read, // .read
input wire [31:0] clocks_pll_slave_readdata, // .readdata
output wire [31:0] clocks_pll_slave_writedata, // .writedata
output wire [8:0] cpu_jtag_debug_module_address, // cpu_jtag_debug_module.address
output wire cpu_jtag_debug_module_write, // .write
output wire cpu_jtag_debug_module_read, // .read
input wire [31:0] cpu_jtag_debug_module_readdata, // .readdata
output wire [31:0] cpu_jtag_debug_module_writedata, // .writedata
output wire [3:0] cpu_jtag_debug_module_byteenable, // .byteenable
input wire cpu_jtag_debug_module_waitrequest, // .waitrequest
output wire cpu_jtag_debug_module_debugaccess, // .debugaccess
output wire [0:0] jtag_uart_avalon_jtag_slave_address, // jtag_uart_avalon_jtag_slave.address
output wire jtag_uart_avalon_jtag_slave_write, // .write
output wire jtag_uart_avalon_jtag_slave_read, // .read
input wire [31:0] jtag_uart_avalon_jtag_slave_readdata, // .readdata
output wire [31:0] jtag_uart_avalon_jtag_slave_writedata, // .writedata
input wire jtag_uart_avalon_jtag_slave_waitrequest, // .waitrequest
output wire jtag_uart_avalon_jtag_slave_chipselect, // .chipselect
output wire [1:0] keycode_s1_address, // keycode_s1.address
output wire keycode_s1_write, // .write
input wire [31:0] keycode_s1_readdata, // .readdata
output wire [31:0] keycode_s1_writedata, // .writedata
output wire keycode_s1_chipselect, // .chipselect
output wire [24:0] sdram_s1_address, // sdram_s1.address
output wire sdram_s1_write, // .write
output wire sdram_s1_read, // .read
input wire [31:0] sdram_s1_readdata, // .readdata
output wire [31:0] sdram_s1_writedata, // .writedata
output wire [3:0] sdram_s1_byteenable, // .byteenable
input wire sdram_s1_readdatavalid, // .readdatavalid
input wire sdram_s1_waitrequest, // .waitrequest
output wire sdram_s1_chipselect // .chipselect
);
wire cpu_instruction_master_translator_avalon_universal_master_0_waitrequest; // cpu_instruction_master_agent:av_waitrequest -> cpu_instruction_master_translator:uav_waitrequest
wire [2:0] cpu_instruction_master_translator_avalon_universal_master_0_burstcount; // cpu_instruction_master_translator:uav_burstcount -> cpu_instruction_master_agent:av_burstcount
wire [31:0] cpu_instruction_master_translator_avalon_universal_master_0_writedata; // cpu_instruction_master_translator:uav_writedata -> cpu_instruction_master_agent:av_writedata
wire [28:0] cpu_instruction_master_translator_avalon_universal_master_0_address; // cpu_instruction_master_translator:uav_address -> cpu_instruction_master_agent:av_address
wire cpu_instruction_master_translator_avalon_universal_master_0_lock; // cpu_instruction_master_translator:uav_lock -> cpu_instruction_master_agent:av_lock
wire cpu_instruction_master_translator_avalon_universal_master_0_write; // cpu_instruction_master_translator:uav_write -> cpu_instruction_master_agent:av_write
wire cpu_instruction_master_translator_avalon_universal_master_0_read; // cpu_instruction_master_translator:uav_read -> cpu_instruction_master_agent:av_read
wire [31:0] cpu_instruction_master_translator_avalon_universal_master_0_readdata; // cpu_instruction_master_agent:av_readdata -> cpu_instruction_master_translator:uav_readdata
wire cpu_instruction_master_translator_avalon_universal_master_0_debugaccess; // cpu_instruction_master_translator:uav_debugaccess -> cpu_instruction_master_agent:av_debugaccess
wire [3:0] cpu_instruction_master_translator_avalon_universal_master_0_byteenable; // cpu_instruction_master_translator:uav_byteenable -> cpu_instruction_master_agent:av_byteenable
wire cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid; // cpu_instruction_master_agent:av_readdatavalid -> cpu_instruction_master_translator:uav_readdatavalid
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> cpu_instruction_master_agent:rp_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> cpu_instruction_master_agent:rp_valid
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> cpu_instruction_master_agent:rp_startofpacket
wire [104:0] rsp_mux_src_data; // rsp_mux:src_data -> cpu_instruction_master_agent:rp_data
wire [5:0] rsp_mux_src_channel; // rsp_mux:src_channel -> cpu_instruction_master_agent:rp_channel
wire rsp_mux_src_ready; // cpu_instruction_master_agent:rp_ready -> rsp_mux:src_ready
wire cpu_data_master_translator_avalon_universal_master_0_waitrequest; // cpu_data_master_agent:av_waitrequest -> cpu_data_master_translator:uav_waitrequest
wire [2:0] cpu_data_master_translator_avalon_universal_master_0_burstcount; // cpu_data_master_translator:uav_burstcount -> cpu_data_master_agent:av_burstcount
wire [31:0] cpu_data_master_translator_avalon_universal_master_0_writedata; // cpu_data_master_translator:uav_writedata -> cpu_data_master_agent:av_writedata
wire [28:0] cpu_data_master_translator_avalon_universal_master_0_address; // cpu_data_master_translator:uav_address -> cpu_data_master_agent:av_address
wire cpu_data_master_translator_avalon_universal_master_0_lock; // cpu_data_master_translator:uav_lock -> cpu_data_master_agent:av_lock
wire cpu_data_master_translator_avalon_universal_master_0_write; // cpu_data_master_translator:uav_write -> cpu_data_master_agent:av_write
wire cpu_data_master_translator_avalon_universal_master_0_read; // cpu_data_master_translator:uav_read -> cpu_data_master_agent:av_read
wire [31:0] cpu_data_master_translator_avalon_universal_master_0_readdata; // cpu_data_master_agent:av_readdata -> cpu_data_master_translator:uav_readdata
wire cpu_data_master_translator_avalon_universal_master_0_debugaccess; // cpu_data_master_translator:uav_debugaccess -> cpu_data_master_agent:av_debugaccess
wire [3:0] cpu_data_master_translator_avalon_universal_master_0_byteenable; // cpu_data_master_translator:uav_byteenable -> cpu_data_master_agent:av_byteenable
wire cpu_data_master_translator_avalon_universal_master_0_readdatavalid; // cpu_data_master_agent:av_readdatavalid -> cpu_data_master_translator:uav_readdatavalid
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> cpu_data_master_agent:rp_endofpacket
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> cpu_data_master_agent:rp_valid
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> cpu_data_master_agent:rp_startofpacket
wire [104:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> cpu_data_master_agent:rp_data
wire [5:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> cpu_data_master_agent:rp_channel
wire rsp_mux_001_src_ready; // cpu_data_master_agent:rp_ready -> rsp_mux_001:src_ready
wire cpu_jtag_debug_module_agent_m0_waitrequest; // cpu_jtag_debug_module_translator:uav_waitrequest -> cpu_jtag_debug_module_agent:m0_waitrequest
wire [2:0] cpu_jtag_debug_module_agent_m0_burstcount; // cpu_jtag_debug_module_agent:m0_burstcount -> cpu_jtag_debug_module_translator:uav_burstcount
wire [31:0] cpu_jtag_debug_module_agent_m0_writedata; // cpu_jtag_debug_module_agent:m0_writedata -> cpu_jtag_debug_module_translator:uav_writedata
wire [28:0] cpu_jtag_debug_module_agent_m0_address; // cpu_jtag_debug_module_agent:m0_address -> cpu_jtag_debug_module_translator:uav_address
wire cpu_jtag_debug_module_agent_m0_write; // cpu_jtag_debug_module_agent:m0_write -> cpu_jtag_debug_module_translator:uav_write
wire cpu_jtag_debug_module_agent_m0_lock; // cpu_jtag_debug_module_agent:m0_lock -> cpu_jtag_debug_module_translator:uav_lock
wire cpu_jtag_debug_module_agent_m0_read; // cpu_jtag_debug_module_agent:m0_read -> cpu_jtag_debug_module_translator:uav_read
wire [31:0] cpu_jtag_debug_module_agent_m0_readdata; // cpu_jtag_debug_module_translator:uav_readdata -> cpu_jtag_debug_module_agent:m0_readdata
wire cpu_jtag_debug_module_agent_m0_readdatavalid; // cpu_jtag_debug_module_translator:uav_readdatavalid -> cpu_jtag_debug_module_agent:m0_readdatavalid
wire cpu_jtag_debug_module_agent_m0_debugaccess; // cpu_jtag_debug_module_agent:m0_debugaccess -> cpu_jtag_debug_module_translator:uav_debugaccess
wire [3:0] cpu_jtag_debug_module_agent_m0_byteenable; // cpu_jtag_debug_module_agent:m0_byteenable -> cpu_jtag_debug_module_translator:uav_byteenable
wire cpu_jtag_debug_module_agent_rf_source_endofpacket; // cpu_jtag_debug_module_agent:rf_source_endofpacket -> cpu_jtag_debug_module_agent_rsp_fifo:in_endofpacket
wire cpu_jtag_debug_module_agent_rf_source_valid; // cpu_jtag_debug_module_agent:rf_source_valid -> cpu_jtag_debug_module_agent_rsp_fifo:in_valid
wire cpu_jtag_debug_module_agent_rf_source_startofpacket; // cpu_jtag_debug_module_agent:rf_source_startofpacket -> cpu_jtag_debug_module_agent_rsp_fifo:in_startofpacket
wire [105:0] cpu_jtag_debug_module_agent_rf_source_data; // cpu_jtag_debug_module_agent:rf_source_data -> cpu_jtag_debug_module_agent_rsp_fifo:in_data
wire cpu_jtag_debug_module_agent_rf_source_ready; // cpu_jtag_debug_module_agent_rsp_fifo:in_ready -> cpu_jtag_debug_module_agent:rf_source_ready
wire cpu_jtag_debug_module_agent_rsp_fifo_out_endofpacket; // cpu_jtag_debug_module_agent_rsp_fifo:out_endofpacket -> cpu_jtag_debug_module_agent:rf_sink_endofpacket
wire cpu_jtag_debug_module_agent_rsp_fifo_out_valid; // cpu_jtag_debug_module_agent_rsp_fifo:out_valid -> cpu_jtag_debug_module_agent:rf_sink_valid
wire cpu_jtag_debug_module_agent_rsp_fifo_out_startofpacket; // cpu_jtag_debug_module_agent_rsp_fifo:out_startofpacket -> cpu_jtag_debug_module_agent:rf_sink_startofpacket
wire [105:0] cpu_jtag_debug_module_agent_rsp_fifo_out_data; // cpu_jtag_debug_module_agent_rsp_fifo:out_data -> cpu_jtag_debug_module_agent:rf_sink_data
wire cpu_jtag_debug_module_agent_rsp_fifo_out_ready; // cpu_jtag_debug_module_agent:rf_sink_ready -> cpu_jtag_debug_module_agent_rsp_fifo:out_ready
wire cpu_jtag_debug_module_agent_rdata_fifo_src_valid; // cpu_jtag_debug_module_agent:rdata_fifo_src_valid -> cpu_jtag_debug_module_agent:rdata_fifo_sink_valid
wire [33:0] cpu_jtag_debug_module_agent_rdata_fifo_src_data; // cpu_jtag_debug_module_agent:rdata_fifo_src_data -> cpu_jtag_debug_module_agent:rdata_fifo_sink_data
wire cpu_jtag_debug_module_agent_rdata_fifo_src_ready; // cpu_jtag_debug_module_agent:rdata_fifo_sink_ready -> cpu_jtag_debug_module_agent:rdata_fifo_src_ready
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> cpu_jtag_debug_module_agent:cp_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> cpu_jtag_debug_module_agent:cp_valid
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> cpu_jtag_debug_module_agent:cp_startofpacket
wire [104:0] cmd_mux_src_data; // cmd_mux:src_data -> cpu_jtag_debug_module_agent:cp_data
wire [5:0] cmd_mux_src_channel; // cmd_mux:src_channel -> cpu_jtag_debug_module_agent:cp_channel
wire cmd_mux_src_ready; // cpu_jtag_debug_module_agent:cp_ready -> cmd_mux:src_ready
wire sdram_s1_agent_m0_waitrequest; // sdram_s1_translator:uav_waitrequest -> sdram_s1_agent:m0_waitrequest
wire [2:0] sdram_s1_agent_m0_burstcount; // sdram_s1_agent:m0_burstcount -> sdram_s1_translator:uav_burstcount
wire [31:0] sdram_s1_agent_m0_writedata; // sdram_s1_agent:m0_writedata -> sdram_s1_translator:uav_writedata
wire [28:0] sdram_s1_agent_m0_address; // sdram_s1_agent:m0_address -> sdram_s1_translator:uav_address
wire sdram_s1_agent_m0_write; // sdram_s1_agent:m0_write -> sdram_s1_translator:uav_write
wire sdram_s1_agent_m0_lock; // sdram_s1_agent:m0_lock -> sdram_s1_translator:uav_lock
wire sdram_s1_agent_m0_read; // sdram_s1_agent:m0_read -> sdram_s1_translator:uav_read
wire [31:0] sdram_s1_agent_m0_readdata; // sdram_s1_translator:uav_readdata -> sdram_s1_agent:m0_readdata
wire sdram_s1_agent_m0_readdatavalid; // sdram_s1_translator:uav_readdatavalid -> sdram_s1_agent:m0_readdatavalid
wire sdram_s1_agent_m0_debugaccess; // sdram_s1_agent:m0_debugaccess -> sdram_s1_translator:uav_debugaccess
wire [3:0] sdram_s1_agent_m0_byteenable; // sdram_s1_agent:m0_byteenable -> sdram_s1_translator:uav_byteenable
wire sdram_s1_agent_rf_source_endofpacket; // sdram_s1_agent:rf_source_endofpacket -> sdram_s1_agent_rsp_fifo:in_endofpacket
wire sdram_s1_agent_rf_source_valid; // sdram_s1_agent:rf_source_valid -> sdram_s1_agent_rsp_fifo:in_valid
wire sdram_s1_agent_rf_source_startofpacket; // sdram_s1_agent:rf_source_startofpacket -> sdram_s1_agent_rsp_fifo:in_startofpacket
wire [105:0] sdram_s1_agent_rf_source_data; // sdram_s1_agent:rf_source_data -> sdram_s1_agent_rsp_fifo:in_data
wire sdram_s1_agent_rf_source_ready; // sdram_s1_agent_rsp_fifo:in_ready -> sdram_s1_agent:rf_source_ready
wire sdram_s1_agent_rsp_fifo_out_endofpacket; // sdram_s1_agent_rsp_fifo:out_endofpacket -> sdram_s1_agent:rf_sink_endofpacket
wire sdram_s1_agent_rsp_fifo_out_valid; // sdram_s1_agent_rsp_fifo:out_valid -> sdram_s1_agent:rf_sink_valid
wire sdram_s1_agent_rsp_fifo_out_startofpacket; // sdram_s1_agent_rsp_fifo:out_startofpacket -> sdram_s1_agent:rf_sink_startofpacket
wire [105:0] sdram_s1_agent_rsp_fifo_out_data; // sdram_s1_agent_rsp_fifo:out_data -> sdram_s1_agent:rf_sink_data
wire sdram_s1_agent_rsp_fifo_out_ready; // sdram_s1_agent:rf_sink_ready -> sdram_s1_agent_rsp_fifo:out_ready
wire sdram_s1_agent_rdata_fifo_src_valid; // sdram_s1_agent:rdata_fifo_src_valid -> sdram_s1_agent_rdata_fifo:in_valid
wire [33:0] sdram_s1_agent_rdata_fifo_src_data; // sdram_s1_agent:rdata_fifo_src_data -> sdram_s1_agent_rdata_fifo:in_data
wire sdram_s1_agent_rdata_fifo_src_ready; // sdram_s1_agent_rdata_fifo:in_ready -> sdram_s1_agent:rdata_fifo_src_ready
wire sdram_s1_agent_rdata_fifo_out_valid; // sdram_s1_agent_rdata_fifo:out_valid -> sdram_s1_agent:rdata_fifo_sink_valid
wire [33:0] sdram_s1_agent_rdata_fifo_out_data; // sdram_s1_agent_rdata_fifo:out_data -> sdram_s1_agent:rdata_fifo_sink_data
wire sdram_s1_agent_rdata_fifo_out_ready; // sdram_s1_agent:rdata_fifo_sink_ready -> sdram_s1_agent_rdata_fifo:out_ready
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> sdram_s1_agent:cp_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> sdram_s1_agent:cp_valid
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> sdram_s1_agent:cp_startofpacket
wire [104:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> sdram_s1_agent:cp_data
wire [5:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> sdram_s1_agent:cp_channel
wire cmd_mux_001_src_ready; // sdram_s1_agent:cp_ready -> cmd_mux_001:src_ready
wire clocks_pll_slave_agent_m0_waitrequest; // clocks_pll_slave_translator:uav_waitrequest -> clocks_pll_slave_agent:m0_waitrequest
wire [2:0] clocks_pll_slave_agent_m0_burstcount; // clocks_pll_slave_agent:m0_burstcount -> clocks_pll_slave_translator:uav_burstcount
wire [31:0] clocks_pll_slave_agent_m0_writedata; // clocks_pll_slave_agent:m0_writedata -> clocks_pll_slave_translator:uav_writedata
wire [28:0] clocks_pll_slave_agent_m0_address; // clocks_pll_slave_agent:m0_address -> clocks_pll_slave_translator:uav_address
wire clocks_pll_slave_agent_m0_write; // clocks_pll_slave_agent:m0_write -> clocks_pll_slave_translator:uav_write
wire clocks_pll_slave_agent_m0_lock; // clocks_pll_slave_agent:m0_lock -> clocks_pll_slave_translator:uav_lock
wire clocks_pll_slave_agent_m0_read; // clocks_pll_slave_agent:m0_read -> clocks_pll_slave_translator:uav_read
wire [31:0] clocks_pll_slave_agent_m0_readdata; // clocks_pll_slave_translator:uav_readdata -> clocks_pll_slave_agent:m0_readdata
wire clocks_pll_slave_agent_m0_readdatavalid; // clocks_pll_slave_translator:uav_readdatavalid -> clocks_pll_slave_agent:m0_readdatavalid
wire clocks_pll_slave_agent_m0_debugaccess; // clocks_pll_slave_agent:m0_debugaccess -> clocks_pll_slave_translator:uav_debugaccess
wire [3:0] clocks_pll_slave_agent_m0_byteenable; // clocks_pll_slave_agent:m0_byteenable -> clocks_pll_slave_translator:uav_byteenable
wire clocks_pll_slave_agent_rf_source_endofpacket; // clocks_pll_slave_agent:rf_source_endofpacket -> clocks_pll_slave_agent_rsp_fifo:in_endofpacket
wire clocks_pll_slave_agent_rf_source_valid; // clocks_pll_slave_agent:rf_source_valid -> clocks_pll_slave_agent_rsp_fifo:in_valid
wire clocks_pll_slave_agent_rf_source_startofpacket; // clocks_pll_slave_agent:rf_source_startofpacket -> clocks_pll_slave_agent_rsp_fifo:in_startofpacket
wire [105:0] clocks_pll_slave_agent_rf_source_data; // clocks_pll_slave_agent:rf_source_data -> clocks_pll_slave_agent_rsp_fifo:in_data
wire clocks_pll_slave_agent_rf_source_ready; // clocks_pll_slave_agent_rsp_fifo:in_ready -> clocks_pll_slave_agent:rf_source_ready
wire clocks_pll_slave_agent_rsp_fifo_out_endofpacket; // clocks_pll_slave_agent_rsp_fifo:out_endofpacket -> clocks_pll_slave_agent:rf_sink_endofpacket
wire clocks_pll_slave_agent_rsp_fifo_out_valid; // clocks_pll_slave_agent_rsp_fifo:out_valid -> clocks_pll_slave_agent:rf_sink_valid
wire clocks_pll_slave_agent_rsp_fifo_out_startofpacket; // clocks_pll_slave_agent_rsp_fifo:out_startofpacket -> clocks_pll_slave_agent:rf_sink_startofpacket
wire [105:0] clocks_pll_slave_agent_rsp_fifo_out_data; // clocks_pll_slave_agent_rsp_fifo:out_data -> clocks_pll_slave_agent:rf_sink_data
wire clocks_pll_slave_agent_rsp_fifo_out_ready; // clocks_pll_slave_agent:rf_sink_ready -> clocks_pll_slave_agent_rsp_fifo:out_ready
wire clocks_pll_slave_agent_rdata_fifo_src_valid; // clocks_pll_slave_agent:rdata_fifo_src_valid -> clocks_pll_slave_agent:rdata_fifo_sink_valid
wire [33:0] clocks_pll_slave_agent_rdata_fifo_src_data; // clocks_pll_slave_agent:rdata_fifo_src_data -> clocks_pll_slave_agent:rdata_fifo_sink_data
wire clocks_pll_slave_agent_rdata_fifo_src_ready; // clocks_pll_slave_agent:rdata_fifo_sink_ready -> clocks_pll_slave_agent:rdata_fifo_src_ready
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> clocks_pll_slave_agent:cp_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> clocks_pll_slave_agent:cp_valid
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> clocks_pll_slave_agent:cp_startofpacket
wire [104:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> clocks_pll_slave_agent:cp_data
wire [5:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> clocks_pll_slave_agent:cp_channel
wire cmd_mux_002_src_ready; // clocks_pll_slave_agent:cp_ready -> cmd_mux_002:src_ready
wire keycode_s1_agent_m0_waitrequest; // keycode_s1_translator:uav_waitrequest -> keycode_s1_agent:m0_waitrequest
wire [2:0] keycode_s1_agent_m0_burstcount; // keycode_s1_agent:m0_burstcount -> keycode_s1_translator:uav_burstcount
wire [31:0] keycode_s1_agent_m0_writedata; // keycode_s1_agent:m0_writedata -> keycode_s1_translator:uav_writedata
wire [28:0] keycode_s1_agent_m0_address; // keycode_s1_agent:m0_address -> keycode_s1_translator:uav_address
wire keycode_s1_agent_m0_write; // keycode_s1_agent:m0_write -> keycode_s1_translator:uav_write
wire keycode_s1_agent_m0_lock; // keycode_s1_agent:m0_lock -> keycode_s1_translator:uav_lock
wire keycode_s1_agent_m0_read; // keycode_s1_agent:m0_read -> keycode_s1_translator:uav_read
wire [31:0] keycode_s1_agent_m0_readdata; // keycode_s1_translator:uav_readdata -> keycode_s1_agent:m0_readdata
wire keycode_s1_agent_m0_readdatavalid; // keycode_s1_translator:uav_readdatavalid -> keycode_s1_agent:m0_readdatavalid
wire keycode_s1_agent_m0_debugaccess; // keycode_s1_agent:m0_debugaccess -> keycode_s1_translator:uav_debugaccess
wire [3:0] keycode_s1_agent_m0_byteenable; // keycode_s1_agent:m0_byteenable -> keycode_s1_translator:uav_byteenable
wire keycode_s1_agent_rf_source_endofpacket; // keycode_s1_agent:rf_source_endofpacket -> keycode_s1_agent_rsp_fifo:in_endofpacket
wire keycode_s1_agent_rf_source_valid; // keycode_s1_agent:rf_source_valid -> keycode_s1_agent_rsp_fifo:in_valid
wire keycode_s1_agent_rf_source_startofpacket; // keycode_s1_agent:rf_source_startofpacket -> keycode_s1_agent_rsp_fifo:in_startofpacket
wire [105:0] keycode_s1_agent_rf_source_data; // keycode_s1_agent:rf_source_data -> keycode_s1_agent_rsp_fifo:in_data
wire keycode_s1_agent_rf_source_ready; // keycode_s1_agent_rsp_fifo:in_ready -> keycode_s1_agent:rf_source_ready
wire keycode_s1_agent_rsp_fifo_out_endofpacket; // keycode_s1_agent_rsp_fifo:out_endofpacket -> keycode_s1_agent:rf_sink_endofpacket
wire keycode_s1_agent_rsp_fifo_out_valid; // keycode_s1_agent_rsp_fifo:out_valid -> keycode_s1_agent:rf_sink_valid
wire keycode_s1_agent_rsp_fifo_out_startofpacket; // keycode_s1_agent_rsp_fifo:out_startofpacket -> keycode_s1_agent:rf_sink_startofpacket
wire [105:0] keycode_s1_agent_rsp_fifo_out_data; // keycode_s1_agent_rsp_fifo:out_data -> keycode_s1_agent:rf_sink_data
wire keycode_s1_agent_rsp_fifo_out_ready; // keycode_s1_agent:rf_sink_ready -> keycode_s1_agent_rsp_fifo:out_ready
wire keycode_s1_agent_rdata_fifo_src_valid; // keycode_s1_agent:rdata_fifo_src_valid -> keycode_s1_agent:rdata_fifo_sink_valid
wire [33:0] keycode_s1_agent_rdata_fifo_src_data; // keycode_s1_agent:rdata_fifo_src_data -> keycode_s1_agent:rdata_fifo_sink_data
wire keycode_s1_agent_rdata_fifo_src_ready; // keycode_s1_agent:rdata_fifo_sink_ready -> keycode_s1_agent:rdata_fifo_src_ready
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> keycode_s1_agent:cp_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> keycode_s1_agent:cp_valid
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> keycode_s1_agent:cp_startofpacket
wire [104:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> keycode_s1_agent:cp_data
wire [5:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> keycode_s1_agent:cp_channel
wire cmd_mux_003_src_ready; // keycode_s1_agent:cp_ready -> cmd_mux_003:src_ready
wire jtag_uart_avalon_jtag_slave_agent_m0_waitrequest; // jtag_uart_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_avalon_jtag_slave_agent:m0_waitrequest
wire [2:0] jtag_uart_avalon_jtag_slave_agent_m0_burstcount; // jtag_uart_avalon_jtag_slave_agent:m0_burstcount -> jtag_uart_avalon_jtag_slave_translator:uav_burstcount
wire [31:0] jtag_uart_avalon_jtag_slave_agent_m0_writedata; // jtag_uart_avalon_jtag_slave_agent:m0_writedata -> jtag_uart_avalon_jtag_slave_translator:uav_writedata
wire [28:0] jtag_uart_avalon_jtag_slave_agent_m0_address; // jtag_uart_avalon_jtag_slave_agent:m0_address -> jtag_uart_avalon_jtag_slave_translator:uav_address
wire jtag_uart_avalon_jtag_slave_agent_m0_write; // jtag_uart_avalon_jtag_slave_agent:m0_write -> jtag_uart_avalon_jtag_slave_translator:uav_write
wire jtag_uart_avalon_jtag_slave_agent_m0_lock; // jtag_uart_avalon_jtag_slave_agent:m0_lock -> jtag_uart_avalon_jtag_slave_translator:uav_lock
wire jtag_uart_avalon_jtag_slave_agent_m0_read; // jtag_uart_avalon_jtag_slave_agent:m0_read -> jtag_uart_avalon_jtag_slave_translator:uav_read
wire [31:0] jtag_uart_avalon_jtag_slave_agent_m0_readdata; // jtag_uart_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_avalon_jtag_slave_agent:m0_readdata
wire jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid; // jtag_uart_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_avalon_jtag_slave_agent:m0_readdatavalid
wire jtag_uart_avalon_jtag_slave_agent_m0_debugaccess; // jtag_uart_avalon_jtag_slave_agent:m0_debugaccess -> jtag_uart_avalon_jtag_slave_translator:uav_debugaccess
wire [3:0] jtag_uart_avalon_jtag_slave_agent_m0_byteenable; // jtag_uart_avalon_jtag_slave_agent:m0_byteenable -> jtag_uart_avalon_jtag_slave_translator:uav_byteenable
wire jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket; // jtag_uart_avalon_jtag_slave_agent:rf_source_endofpacket -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_endofpacket
wire jtag_uart_avalon_jtag_slave_agent_rf_source_valid; // jtag_uart_avalon_jtag_slave_agent:rf_source_valid -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_valid
wire jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket; // jtag_uart_avalon_jtag_slave_agent:rf_source_startofpacket -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_startofpacket
wire [105:0] jtag_uart_avalon_jtag_slave_agent_rf_source_data; // jtag_uart_avalon_jtag_slave_agent:rf_source_data -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_data
wire jtag_uart_avalon_jtag_slave_agent_rf_source_ready; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:in_ready -> jtag_uart_avalon_jtag_slave_agent:rf_source_ready
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_endofpacket -> jtag_uart_avalon_jtag_slave_agent:rf_sink_endofpacket
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_valid -> jtag_uart_avalon_jtag_slave_agent:rf_sink_valid
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_startofpacket -> jtag_uart_avalon_jtag_slave_agent:rf_sink_startofpacket
wire [105:0] jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data; // jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_data -> jtag_uart_avalon_jtag_slave_agent:rf_sink_data
wire jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready; // jtag_uart_avalon_jtag_slave_agent:rf_sink_ready -> jtag_uart_avalon_jtag_slave_agent_rsp_fifo:out_ready
wire jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid; // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_valid -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_valid
wire [33:0] jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data; // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_data -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_data
wire jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready; // jtag_uart_avalon_jtag_slave_agent:rdata_fifo_sink_ready -> jtag_uart_avalon_jtag_slave_agent:rdata_fifo_src_ready
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_endofpacket
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> jtag_uart_avalon_jtag_slave_agent:cp_valid
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> jtag_uart_avalon_jtag_slave_agent:cp_startofpacket
wire [104:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> jtag_uart_avalon_jtag_slave_agent:cp_data
wire [5:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> jtag_uart_avalon_jtag_slave_agent:cp_channel
wire cmd_mux_004_src_ready; // jtag_uart_avalon_jtag_slave_agent:cp_ready -> cmd_mux_004:src_ready
wire clock_crossing_io_s0_agent_m0_waitrequest; // clock_crossing_io_s0_translator:uav_waitrequest -> clock_crossing_io_s0_agent:m0_waitrequest
wire [2:0] clock_crossing_io_s0_agent_m0_burstcount; // clock_crossing_io_s0_agent:m0_burstcount -> clock_crossing_io_s0_translator:uav_burstcount
wire [31:0] clock_crossing_io_s0_agent_m0_writedata; // clock_crossing_io_s0_agent:m0_writedata -> clock_crossing_io_s0_translator:uav_writedata
wire [28:0] clock_crossing_io_s0_agent_m0_address; // clock_crossing_io_s0_agent:m0_address -> clock_crossing_io_s0_translator:uav_address
wire clock_crossing_io_s0_agent_m0_write; // clock_crossing_io_s0_agent:m0_write -> clock_crossing_io_s0_translator:uav_write
wire clock_crossing_io_s0_agent_m0_lock; // clock_crossing_io_s0_agent:m0_lock -> clock_crossing_io_s0_translator:uav_lock
wire clock_crossing_io_s0_agent_m0_read; // clock_crossing_io_s0_agent:m0_read -> clock_crossing_io_s0_translator:uav_read
wire [31:0] clock_crossing_io_s0_agent_m0_readdata; // clock_crossing_io_s0_translator:uav_readdata -> clock_crossing_io_s0_agent:m0_readdata
wire clock_crossing_io_s0_agent_m0_readdatavalid; // clock_crossing_io_s0_translator:uav_readdatavalid -> clock_crossing_io_s0_agent:m0_readdatavalid
wire clock_crossing_io_s0_agent_m0_debugaccess; // clock_crossing_io_s0_agent:m0_debugaccess -> clock_crossing_io_s0_translator:uav_debugaccess
wire [3:0] clock_crossing_io_s0_agent_m0_byteenable; // clock_crossing_io_s0_agent:m0_byteenable -> clock_crossing_io_s0_translator:uav_byteenable
wire clock_crossing_io_s0_agent_rf_source_endofpacket; // clock_crossing_io_s0_agent:rf_source_endofpacket -> clock_crossing_io_s0_agent_rsp_fifo:in_endofpacket
wire clock_crossing_io_s0_agent_rf_source_valid; // clock_crossing_io_s0_agent:rf_source_valid -> clock_crossing_io_s0_agent_rsp_fifo:in_valid
wire clock_crossing_io_s0_agent_rf_source_startofpacket; // clock_crossing_io_s0_agent:rf_source_startofpacket -> clock_crossing_io_s0_agent_rsp_fifo:in_startofpacket
wire [105:0] clock_crossing_io_s0_agent_rf_source_data; // clock_crossing_io_s0_agent:rf_source_data -> clock_crossing_io_s0_agent_rsp_fifo:in_data
wire clock_crossing_io_s0_agent_rf_source_ready; // clock_crossing_io_s0_agent_rsp_fifo:in_ready -> clock_crossing_io_s0_agent:rf_source_ready
wire clock_crossing_io_s0_agent_rsp_fifo_out_endofpacket; // clock_crossing_io_s0_agent_rsp_fifo:out_endofpacket -> clock_crossing_io_s0_agent:rf_sink_endofpacket
wire clock_crossing_io_s0_agent_rsp_fifo_out_valid; // clock_crossing_io_s0_agent_rsp_fifo:out_valid -> clock_crossing_io_s0_agent:rf_sink_valid
wire clock_crossing_io_s0_agent_rsp_fifo_out_startofpacket; // clock_crossing_io_s0_agent_rsp_fifo:out_startofpacket -> clock_crossing_io_s0_agent:rf_sink_startofpacket
wire [105:0] clock_crossing_io_s0_agent_rsp_fifo_out_data; // clock_crossing_io_s0_agent_rsp_fifo:out_data -> clock_crossing_io_s0_agent:rf_sink_data
wire clock_crossing_io_s0_agent_rsp_fifo_out_ready; // clock_crossing_io_s0_agent:rf_sink_ready -> clock_crossing_io_s0_agent_rsp_fifo:out_ready
wire clock_crossing_io_s0_agent_rdata_fifo_src_valid; // clock_crossing_io_s0_agent:rdata_fifo_src_valid -> clock_crossing_io_s0_agent:rdata_fifo_sink_valid
wire [33:0] clock_crossing_io_s0_agent_rdata_fifo_src_data; // clock_crossing_io_s0_agent:rdata_fifo_src_data -> clock_crossing_io_s0_agent:rdata_fifo_sink_data
wire clock_crossing_io_s0_agent_rdata_fifo_src_ready; // clock_crossing_io_s0_agent:rdata_fifo_sink_ready -> clock_crossing_io_s0_agent:rdata_fifo_src_ready
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> clock_crossing_io_s0_agent:cp_endofpacket
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> clock_crossing_io_s0_agent:cp_valid
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> clock_crossing_io_s0_agent:cp_startofpacket
wire [104:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> clock_crossing_io_s0_agent:cp_data
wire [5:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> clock_crossing_io_s0_agent:cp_channel
wire cmd_mux_005_src_ready; // clock_crossing_io_s0_agent:cp_ready -> cmd_mux_005:src_ready
wire cpu_instruction_master_agent_cp_endofpacket; // cpu_instruction_master_agent:cp_endofpacket -> router:sink_endofpacket
wire cpu_instruction_master_agent_cp_valid; // cpu_instruction_master_agent:cp_valid -> router:sink_valid
wire cpu_instruction_master_agent_cp_startofpacket; // cpu_instruction_master_agent:cp_startofpacket -> router:sink_startofpacket
wire [104:0] cpu_instruction_master_agent_cp_data; // cpu_instruction_master_agent:cp_data -> router:sink_data
wire cpu_instruction_master_agent_cp_ready; // router:sink_ready -> cpu_instruction_master_agent:cp_ready
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire [104:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire [5:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire cpu_data_master_agent_cp_endofpacket; // cpu_data_master_agent:cp_endofpacket -> router_001:sink_endofpacket
wire cpu_data_master_agent_cp_valid; // cpu_data_master_agent:cp_valid -> router_001:sink_valid
wire cpu_data_master_agent_cp_startofpacket; // cpu_data_master_agent:cp_startofpacket -> router_001:sink_startofpacket
wire [104:0] cpu_data_master_agent_cp_data; // cpu_data_master_agent:cp_data -> router_001:sink_data
wire cpu_data_master_agent_cp_ready; // router_001:sink_ready -> cpu_data_master_agent:cp_ready
wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
wire [104:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
wire [5:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
wire cpu_jtag_debug_module_agent_rp_endofpacket; // cpu_jtag_debug_module_agent:rp_endofpacket -> router_002:sink_endofpacket
wire cpu_jtag_debug_module_agent_rp_valid; // cpu_jtag_debug_module_agent:rp_valid -> router_002:sink_valid
wire cpu_jtag_debug_module_agent_rp_startofpacket; // cpu_jtag_debug_module_agent:rp_startofpacket -> router_002:sink_startofpacket
wire [104:0] cpu_jtag_debug_module_agent_rp_data; // cpu_jtag_debug_module_agent:rp_data -> router_002:sink_data
wire cpu_jtag_debug_module_agent_rp_ready; // router_002:sink_ready -> cpu_jtag_debug_module_agent:rp_ready
wire router_002_src_endofpacket; // router_002:src_endofpacket -> rsp_demux:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> rsp_demux:sink_valid
wire router_002_src_startofpacket; // router_002:src_startofpacket -> rsp_demux:sink_startofpacket
wire [104:0] router_002_src_data; // router_002:src_data -> rsp_demux:sink_data
wire [5:0] router_002_src_channel; // router_002:src_channel -> rsp_demux:sink_channel
wire router_002_src_ready; // rsp_demux:sink_ready -> router_002:src_ready
wire sdram_s1_agent_rp_endofpacket; // sdram_s1_agent:rp_endofpacket -> router_003:sink_endofpacket
wire sdram_s1_agent_rp_valid; // sdram_s1_agent:rp_valid -> router_003:sink_valid
wire sdram_s1_agent_rp_startofpacket; // sdram_s1_agent:rp_startofpacket -> router_003:sink_startofpacket
wire [104:0] sdram_s1_agent_rp_data; // sdram_s1_agent:rp_data -> router_003:sink_data
wire sdram_s1_agent_rp_ready; // router_003:sink_ready -> sdram_s1_agent:rp_ready
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux_001:sink_valid
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire [104:0] router_003_src_data; // router_003:src_data -> rsp_demux_001:sink_data
wire [5:0] router_003_src_channel; // router_003:src_channel -> rsp_demux_001:sink_channel
wire router_003_src_ready; // rsp_demux_001:sink_ready -> router_003:src_ready
wire clocks_pll_slave_agent_rp_endofpacket; // clocks_pll_slave_agent:rp_endofpacket -> router_004:sink_endofpacket
wire clocks_pll_slave_agent_rp_valid; // clocks_pll_slave_agent:rp_valid -> router_004:sink_valid
wire clocks_pll_slave_agent_rp_startofpacket; // clocks_pll_slave_agent:rp_startofpacket -> router_004:sink_startofpacket
wire [104:0] clocks_pll_slave_agent_rp_data; // clocks_pll_slave_agent:rp_data -> router_004:sink_data
wire clocks_pll_slave_agent_rp_ready; // router_004:sink_ready -> clocks_pll_slave_agent:rp_ready
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_002:sink_valid
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire [104:0] router_004_src_data; // router_004:src_data -> rsp_demux_002:sink_data
wire [5:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_002:sink_channel
wire router_004_src_ready; // rsp_demux_002:sink_ready -> router_004:src_ready
wire keycode_s1_agent_rp_endofpacket; // keycode_s1_agent:rp_endofpacket -> router_005:sink_endofpacket
wire keycode_s1_agent_rp_valid; // keycode_s1_agent:rp_valid -> router_005:sink_valid
wire keycode_s1_agent_rp_startofpacket; // keycode_s1_agent:rp_startofpacket -> router_005:sink_startofpacket
wire [104:0] keycode_s1_agent_rp_data; // keycode_s1_agent:rp_data -> router_005:sink_data
wire keycode_s1_agent_rp_ready; // router_005:sink_ready -> keycode_s1_agent:rp_ready
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_003:sink_valid
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire [104:0] router_005_src_data; // router_005:src_data -> rsp_demux_003:sink_data
wire [5:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_003:sink_channel
wire router_005_src_ready; // rsp_demux_003:sink_ready -> router_005:src_ready
wire jtag_uart_avalon_jtag_slave_agent_rp_endofpacket; // jtag_uart_avalon_jtag_slave_agent:rp_endofpacket -> router_006:sink_endofpacket
wire jtag_uart_avalon_jtag_slave_agent_rp_valid; // jtag_uart_avalon_jtag_slave_agent:rp_valid -> router_006:sink_valid
wire jtag_uart_avalon_jtag_slave_agent_rp_startofpacket; // jtag_uart_avalon_jtag_slave_agent:rp_startofpacket -> router_006:sink_startofpacket
wire [104:0] jtag_uart_avalon_jtag_slave_agent_rp_data; // jtag_uart_avalon_jtag_slave_agent:rp_data -> router_006:sink_data
wire jtag_uart_avalon_jtag_slave_agent_rp_ready; // router_006:sink_ready -> jtag_uart_avalon_jtag_slave_agent:rp_ready
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_004:sink_valid
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire [104:0] router_006_src_data; // router_006:src_data -> rsp_demux_004:sink_data
wire [5:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_004:sink_channel
wire router_006_src_ready; // rsp_demux_004:sink_ready -> router_006:src_ready
wire clock_crossing_io_s0_agent_rp_endofpacket; // clock_crossing_io_s0_agent:rp_endofpacket -> router_007:sink_endofpacket
wire clock_crossing_io_s0_agent_rp_valid; // clock_crossing_io_s0_agent:rp_valid -> router_007:sink_valid
wire clock_crossing_io_s0_agent_rp_startofpacket; // clock_crossing_io_s0_agent:rp_startofpacket -> router_007:sink_startofpacket
wire [104:0] clock_crossing_io_s0_agent_rp_data; // clock_crossing_io_s0_agent:rp_data -> router_007:sink_data
wire clock_crossing_io_s0_agent_rp_ready; // router_007:sink_ready -> clock_crossing_io_s0_agent:rp_ready
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_005:sink_valid
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire [104:0] router_007_src_data; // router_007:src_data -> rsp_demux_005:sink_data
wire [5:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_005:sink_channel
wire router_007_src_ready; // rsp_demux_005:sink_ready -> router_007:src_ready
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire [104:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire [5:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire [104:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire [5:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux:sink1_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux:sink1_valid
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux:sink1_startofpacket
wire [104:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux:sink1_data
wire [5:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux:sink1_channel
wire cmd_demux_001_src0_ready; // cmd_mux:sink1_ready -> cmd_demux_001:src0_ready
wire cmd_demux_001_src2_endofpacket; // cmd_demux_001:src2_endofpacket -> cmd_mux_002:sink1_endofpacket
wire cmd_demux_001_src2_valid; // cmd_demux_001:src2_valid -> cmd_mux_002:sink1_valid
wire cmd_demux_001_src2_startofpacket; // cmd_demux_001:src2_startofpacket -> cmd_mux_002:sink1_startofpacket
wire [104:0] cmd_demux_001_src2_data; // cmd_demux_001:src2_data -> cmd_mux_002:sink1_data
wire [5:0] cmd_demux_001_src2_channel; // cmd_demux_001:src2_channel -> cmd_mux_002:sink1_channel
wire cmd_demux_001_src2_ready; // cmd_mux_002:sink1_ready -> cmd_demux_001:src2_ready
wire cmd_demux_001_src3_endofpacket; // cmd_demux_001:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_001_src3_valid; // cmd_demux_001:src3_valid -> cmd_mux_003:sink0_valid
wire cmd_demux_001_src3_startofpacket; // cmd_demux_001:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire [104:0] cmd_demux_001_src3_data; // cmd_demux_001:src3_data -> cmd_mux_003:sink0_data
wire [5:0] cmd_demux_001_src3_channel; // cmd_demux_001:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_001_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux_001:src3_ready
wire cmd_demux_001_src4_endofpacket; // cmd_demux_001:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_001_src4_valid; // cmd_demux_001:src4_valid -> cmd_mux_004:sink0_valid
wire cmd_demux_001_src4_startofpacket; // cmd_demux_001:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire [104:0] cmd_demux_001_src4_data; // cmd_demux_001:src4_data -> cmd_mux_004:sink0_data
wire [5:0] cmd_demux_001_src4_channel; // cmd_demux_001:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_001_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux_001:src4_ready
wire cmd_demux_001_src5_endofpacket; // cmd_demux_001:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
wire cmd_demux_001_src5_valid; // cmd_demux_001:src5_valid -> cmd_mux_005:sink0_valid
wire cmd_demux_001_src5_startofpacket; // cmd_demux_001:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
wire [104:0] cmd_demux_001_src5_data; // cmd_demux_001:src5_data -> cmd_mux_005:sink0_data
wire [5:0] cmd_demux_001_src5_channel; // cmd_demux_001:src5_channel -> cmd_mux_005:sink0_channel
wire cmd_demux_001_src5_ready; // cmd_mux_005:sink0_ready -> cmd_demux_001:src5_ready
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire [104:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire [5:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> rsp_mux_001:sink0_valid
wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire [104:0] rsp_demux_src1_data; // rsp_demux:src1_data -> rsp_mux_001:sink0_data
wire [5:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux:src1_ready
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire [104:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire [5:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire rsp_demux_002_src1_endofpacket; // rsp_demux_002:src1_endofpacket -> rsp_mux_001:sink2_endofpacket
wire rsp_demux_002_src1_valid; // rsp_demux_002:src1_valid -> rsp_mux_001:sink2_valid
wire rsp_demux_002_src1_startofpacket; // rsp_demux_002:src1_startofpacket -> rsp_mux_001:sink2_startofpacket
wire [104:0] rsp_demux_002_src1_data; // rsp_demux_002:src1_data -> rsp_mux_001:sink2_data
wire [5:0] rsp_demux_002_src1_channel; // rsp_demux_002:src1_channel -> rsp_mux_001:sink2_channel
wire rsp_demux_002_src1_ready; // rsp_mux_001:sink2_ready -> rsp_demux_002:src1_ready
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux_001:sink3_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux_001:sink3_valid
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux_001:sink3_startofpacket
wire [104:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux_001:sink3_data
wire [5:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux_001:sink3_channel
wire rsp_demux_003_src0_ready; // rsp_mux_001:sink3_ready -> rsp_demux_003:src0_ready
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux_001:sink4_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux_001:sink4_valid
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux_001:sink4_startofpacket
wire [104:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux_001:sink4_data
wire [5:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux_001:sink4_channel
wire rsp_demux_004_src0_ready; // rsp_mux_001:sink4_ready -> rsp_demux_004:src0_ready
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> rsp_mux_001:sink5_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> rsp_mux_001:sink5_valid
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> rsp_mux_001:sink5_startofpacket
wire [104:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> rsp_mux_001:sink5_data
wire [5:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> rsp_mux_001:sink5_channel
wire rsp_demux_005_src0_ready; // rsp_mux_001:sink5_ready -> rsp_demux_005:src0_ready
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> crosser:in_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> crosser:in_valid
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> crosser:in_startofpacket
wire [104:0] cmd_demux_src1_data; // cmd_demux:src1_data -> crosser:in_data
wire [5:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> crosser:in_channel
wire cmd_demux_src1_ready; // crosser:in_ready -> cmd_demux:src1_ready
wire crosser_out_endofpacket; // crosser:out_endofpacket -> cmd_mux_001:sink0_endofpacket
wire crosser_out_valid; // crosser:out_valid -> cmd_mux_001:sink0_valid
wire crosser_out_startofpacket; // crosser:out_startofpacket -> cmd_mux_001:sink0_startofpacket
wire [104:0] crosser_out_data; // crosser:out_data -> cmd_mux_001:sink0_data
wire [5:0] crosser_out_channel; // crosser:out_channel -> cmd_mux_001:sink0_channel
wire crosser_out_ready; // cmd_mux_001:sink0_ready -> crosser:out_ready
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> crosser_001:in_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> crosser_001:in_valid
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> crosser_001:in_startofpacket
wire [104:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> crosser_001:in_data
wire [5:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> crosser_001:in_channel
wire cmd_demux_001_src1_ready; // crosser_001:in_ready -> cmd_demux_001:src1_ready
wire crosser_001_out_endofpacket; // crosser_001:out_endofpacket -> cmd_mux_001:sink1_endofpacket
wire crosser_001_out_valid; // crosser_001:out_valid -> cmd_mux_001:sink1_valid
wire crosser_001_out_startofpacket; // crosser_001:out_startofpacket -> cmd_mux_001:sink1_startofpacket
wire [104:0] crosser_001_out_data; // crosser_001:out_data -> cmd_mux_001:sink1_data
wire [5:0] crosser_001_out_channel; // crosser_001:out_channel -> cmd_mux_001:sink1_channel
wire crosser_001_out_ready; // cmd_mux_001:sink1_ready -> crosser_001:out_ready
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> crosser_002:in_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> crosser_002:in_valid
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> crosser_002:in_startofpacket
wire [104:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> crosser_002:in_data
wire [5:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> crosser_002:in_channel
wire rsp_demux_001_src0_ready; // crosser_002:in_ready -> rsp_demux_001:src0_ready
wire crosser_002_out_endofpacket; // crosser_002:out_endofpacket -> rsp_mux:sink1_endofpacket
wire crosser_002_out_valid; // crosser_002:out_valid -> rsp_mux:sink1_valid
wire crosser_002_out_startofpacket; // crosser_002:out_startofpacket -> rsp_mux:sink1_startofpacket
wire [104:0] crosser_002_out_data; // crosser_002:out_data -> rsp_mux:sink1_data
wire [5:0] crosser_002_out_channel; // crosser_002:out_channel -> rsp_mux:sink1_channel
wire crosser_002_out_ready; // rsp_mux:sink1_ready -> crosser_002:out_ready
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> crosser_003:in_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> crosser_003:in_valid
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> crosser_003:in_startofpacket
wire [104:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> crosser_003:in_data
wire [5:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> crosser_003:in_channel
wire rsp_demux_001_src1_ready; // crosser_003:in_ready -> rsp_demux_001:src1_ready
wire crosser_003_out_endofpacket; // crosser_003:out_endofpacket -> rsp_mux_001:sink1_endofpacket
wire crosser_003_out_valid; // crosser_003:out_valid -> rsp_mux_001:sink1_valid
wire crosser_003_out_startofpacket; // crosser_003:out_startofpacket -> rsp_mux_001:sink1_startofpacket
wire [104:0] crosser_003_out_data; // crosser_003:out_data -> rsp_mux_001:sink1_data
wire [5:0] crosser_003_out_channel; // crosser_003:out_channel -> rsp_mux_001:sink1_channel
wire crosser_003_out_ready; // rsp_mux_001:sink1_ready -> crosser_003:out_ready
altera_merlin_master_translator #(
.AV_ADDRESS_W (29),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) cpu_instruction_master_translator (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (cpu_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest
.av_read (cpu_instruction_master_read), // .read
.av_readdata (cpu_instruction_master_readdata), // .readdata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (29),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (1)
) cpu_data_master_translator (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (cpu_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (cpu_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (cpu_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (cpu_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (cpu_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (cpu_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (cpu_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (cpu_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (cpu_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (cpu_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (cpu_data_master_waitrequest), // .waitrequest
.av_byteenable (cpu_data_master_byteenable), // .byteenable
.av_read (cpu_data_master_read), // .read
.av_readdata (cpu_data_master_readdata), // .readdata
.av_write (cpu_data_master_write), // .write
.av_writedata (cpu_data_master_writedata), // .writedata
.av_debugaccess (cpu_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) cpu_jtag_debug_module_translator (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (cpu_jtag_debug_module_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (cpu_jtag_debug_module_agent_m0_burstcount), // .burstcount
.uav_read (cpu_jtag_debug_module_agent_m0_read), // .read
.uav_write (cpu_jtag_debug_module_agent_m0_write), // .write
.uav_waitrequest (cpu_jtag_debug_module_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (cpu_jtag_debug_module_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (cpu_jtag_debug_module_agent_m0_byteenable), // .byteenable
.uav_readdata (cpu_jtag_debug_module_agent_m0_readdata), // .readdata
.uav_writedata (cpu_jtag_debug_module_agent_m0_writedata), // .writedata
.uav_lock (cpu_jtag_debug_module_agent_m0_lock), // .lock
.uav_debugaccess (cpu_jtag_debug_module_agent_m0_debugaccess), // .debugaccess
.av_address (cpu_jtag_debug_module_address), // avalon_anti_slave_0.address
.av_write (cpu_jtag_debug_module_write), // .write
.av_read (cpu_jtag_debug_module_read), // .read
.av_readdata (cpu_jtag_debug_module_readdata), // .readdata
.av_writedata (cpu_jtag_debug_module_writedata), // .writedata
.av_byteenable (cpu_jtag_debug_module_byteenable), // .byteenable
.av_waitrequest (cpu_jtag_debug_module_waitrequest), // .waitrequest
.av_debugaccess (cpu_jtag_debug_module_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (25),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) sdram_s1_translator (
.clk (clocks_c0_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (sdram_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (sdram_s1_agent_m0_burstcount), // .burstcount
.uav_read (sdram_s1_agent_m0_read), // .read
.uav_write (sdram_s1_agent_m0_write), // .write
.uav_waitrequest (sdram_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (sdram_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (sdram_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (sdram_s1_agent_m0_readdata), // .readdata
.uav_writedata (sdram_s1_agent_m0_writedata), // .writedata
.uav_lock (sdram_s1_agent_m0_lock), // .lock
.uav_debugaccess (sdram_s1_agent_m0_debugaccess), // .debugaccess
.av_address (sdram_s1_address), // avalon_anti_slave_0.address
.av_write (sdram_s1_write), // .write
.av_read (sdram_s1_read), // .read
.av_readdata (sdram_s1_readdata), // .readdata
.av_writedata (sdram_s1_writedata), // .writedata
.av_byteenable (sdram_s1_byteenable), // .byteenable
.av_readdatavalid (sdram_s1_readdatavalid), // .readdatavalid
.av_waitrequest (sdram_s1_waitrequest), // .waitrequest
.av_chipselect (sdram_s1_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) clocks_pll_slave_translator (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (clocks_pll_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (clocks_pll_slave_agent_m0_burstcount), // .burstcount
.uav_read (clocks_pll_slave_agent_m0_read), // .read
.uav_write (clocks_pll_slave_agent_m0_write), // .write
.uav_waitrequest (clocks_pll_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (clocks_pll_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (clocks_pll_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (clocks_pll_slave_agent_m0_readdata), // .readdata
.uav_writedata (clocks_pll_slave_agent_m0_writedata), // .writedata
.uav_lock (clocks_pll_slave_agent_m0_lock), // .lock
.uav_debugaccess (clocks_pll_slave_agent_m0_debugaccess), // .debugaccess
.av_address (clocks_pll_slave_address), // avalon_anti_slave_0.address
.av_write (clocks_pll_slave_write), // .write
.av_read (clocks_pll_slave_read), // .read
.av_readdata (clocks_pll_slave_readdata), // .readdata
.av_writedata (clocks_pll_slave_writedata), // .writedata
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) keycode_s1_translator (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (keycode_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (keycode_s1_agent_m0_burstcount), // .burstcount
.uav_read (keycode_s1_agent_m0_read), // .read
.uav_write (keycode_s1_agent_m0_write), // .write
.uav_waitrequest (keycode_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (keycode_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (keycode_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (keycode_s1_agent_m0_readdata), // .readdata
.uav_writedata (keycode_s1_agent_m0_writedata), // .writedata
.uav_lock (keycode_s1_agent_m0_lock), // .lock
.uav_debugaccess (keycode_s1_agent_m0_debugaccess), // .debugaccess
.av_address (keycode_s1_address), // avalon_anti_slave_0.address
.av_write (keycode_s1_write), // .write
.av_readdata (keycode_s1_readdata), // .readdata
.av_writedata (keycode_s1_writedata), // .writedata
.av_chipselect (keycode_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) jtag_uart_avalon_jtag_slave_translator (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (jtag_uart_avalon_jtag_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (jtag_uart_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.uav_read (jtag_uart_avalon_jtag_slave_agent_m0_read), // .read
.uav_write (jtag_uart_avalon_jtag_slave_agent_m0_write), // .write
.uav_waitrequest (jtag_uart_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (jtag_uart_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (jtag_uart_avalon_jtag_slave_agent_m0_readdata), // .readdata
.uav_writedata (jtag_uart_avalon_jtag_slave_agent_m0_writedata), // .writedata
.uav_lock (jtag_uart_avalon_jtag_slave_agent_m0_lock), // .lock
.uav_debugaccess (jtag_uart_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.av_address (jtag_uart_avalon_jtag_slave_address), // avalon_anti_slave_0.address
.av_write (jtag_uart_avalon_jtag_slave_write), // .write
.av_read (jtag_uart_avalon_jtag_slave_read), // .read
.av_readdata (jtag_uart_avalon_jtag_slave_readdata), // .readdata
.av_writedata (jtag_uart_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.av_chipselect (jtag_uart_avalon_jtag_slave_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (22),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (29),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) clock_crossing_io_s0_translator (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // reset.reset
.uav_address (clock_crossing_io_s0_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (clock_crossing_io_s0_agent_m0_burstcount), // .burstcount
.uav_read (clock_crossing_io_s0_agent_m0_read), // .read
.uav_write (clock_crossing_io_s0_agent_m0_write), // .write
.uav_waitrequest (clock_crossing_io_s0_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (clock_crossing_io_s0_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (clock_crossing_io_s0_agent_m0_byteenable), // .byteenable
.uav_readdata (clock_crossing_io_s0_agent_m0_readdata), // .readdata
.uav_writedata (clock_crossing_io_s0_agent_m0_writedata), // .writedata
.uav_lock (clock_crossing_io_s0_agent_m0_lock), // .lock
.uav_debugaccess (clock_crossing_io_s0_agent_m0_debugaccess), // .debugaccess
.av_address (clock_crossing_io_s0_address), // avalon_anti_slave_0.address
.av_write (clock_crossing_io_s0_write), // .write
.av_read (clock_crossing_io_s0_read), // .read
.av_readdata (clock_crossing_io_s0_readdata), // .readdata
.av_writedata (clock_crossing_io_s0_writedata), // .writedata
.av_burstcount (clock_crossing_io_s0_burstcount), // .burstcount
.av_byteenable (clock_crossing_io_s0_byteenable), // .byteenable
.av_readdatavalid (clock_crossing_io_s0_readdatavalid), // .readdatavalid
.av_waitrequest (clock_crossing_io_s0_waitrequest), // .waitrequest
.av_debugaccess (clock_crossing_io_s0_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_BEGIN_BURST (84),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_TRANS_LOCK (69),
.PKT_TRANS_EXCLUSIVE (70),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.PKT_THREAD_ID_H (92),
.PKT_THREAD_ID_L (92),
.PKT_CACHE_H (99),
.PKT_CACHE_L (96),
.PKT_DATA_SIDEBAND_H (83),
.PKT_DATA_SIDEBAND_L (83),
.PKT_QOS_H (85),
.PKT_QOS_L (85),
.PKT_ADDR_SIDEBAND_H (82),
.PKT_ADDR_SIDEBAND_L (82),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_ORI_BURST_SIZE_H (104),
.ST_DATA_W (105),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) cpu_instruction_master_agent (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (cpu_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_instruction_master_agent_cp_valid), // cp.valid
.cp_data (cpu_instruction_master_agent_cp_data), // .data
.cp_startofpacket (cpu_instruction_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_instruction_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_instruction_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_BEGIN_BURST (84),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_BURST_TYPE_H (81),
.PKT_BURST_TYPE_L (80),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_TRANS_LOCK (69),
.PKT_TRANS_EXCLUSIVE (70),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.PKT_THREAD_ID_H (92),
.PKT_THREAD_ID_L (92),
.PKT_CACHE_H (99),
.PKT_CACHE_L (96),
.PKT_DATA_SIDEBAND_H (83),
.PKT_DATA_SIDEBAND_L (83),
.PKT_QOS_H (85),
.PKT_QOS_L (85),
.PKT_ADDR_SIDEBAND_H (82),
.PKT_ADDR_SIDEBAND_L (82),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_ORI_BURST_SIZE_H (104),
.ST_DATA_W (105),
.ST_CHANNEL_W (6),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) cpu_data_master_agent (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (cpu_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (cpu_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (cpu_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (cpu_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (cpu_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (cpu_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (cpu_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (cpu_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (cpu_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (cpu_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (cpu_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (cpu_data_master_agent_cp_valid), // cp.valid
.cp_data (cpu_data_master_agent_cp_data), // .data
.cp_startofpacket (cpu_data_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (cpu_data_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (cpu_data_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_001_src_valid), // rp.valid
.rp_data (rsp_mux_001_src_data), // .data
.rp_channel (rsp_mux_001_src_channel), // .channel
.rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_001_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_TRANS_LOCK (69),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_ORI_BURST_SIZE_H (104),
.ST_CHANNEL_W (6),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) cpu_jtag_debug_module_agent (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (cpu_jtag_debug_module_agent_m0_address), // m0.address
.m0_burstcount (cpu_jtag_debug_module_agent_m0_burstcount), // .burstcount
.m0_byteenable (cpu_jtag_debug_module_agent_m0_byteenable), // .byteenable
.m0_debugaccess (cpu_jtag_debug_module_agent_m0_debugaccess), // .debugaccess
.m0_lock (cpu_jtag_debug_module_agent_m0_lock), // .lock
.m0_readdata (cpu_jtag_debug_module_agent_m0_readdata), // .readdata
.m0_readdatavalid (cpu_jtag_debug_module_agent_m0_readdatavalid), // .readdatavalid
.m0_read (cpu_jtag_debug_module_agent_m0_read), // .read
.m0_waitrequest (cpu_jtag_debug_module_agent_m0_waitrequest), // .waitrequest
.m0_writedata (cpu_jtag_debug_module_agent_m0_writedata), // .writedata
.m0_write (cpu_jtag_debug_module_agent_m0_write), // .write
.rp_endofpacket (cpu_jtag_debug_module_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (cpu_jtag_debug_module_agent_rp_ready), // .ready
.rp_valid (cpu_jtag_debug_module_agent_rp_valid), // .valid
.rp_data (cpu_jtag_debug_module_agent_rp_data), // .data
.rp_startofpacket (cpu_jtag_debug_module_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_src_ready), // cp.ready
.cp_valid (cmd_mux_src_valid), // .valid
.cp_data (cmd_mux_src_data), // .data
.cp_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_src_channel), // .channel
.rf_sink_ready (cpu_jtag_debug_module_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (cpu_jtag_debug_module_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (cpu_jtag_debug_module_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (cpu_jtag_debug_module_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (cpu_jtag_debug_module_agent_rsp_fifo_out_data), // .data
.rf_source_ready (cpu_jtag_debug_module_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (cpu_jtag_debug_module_agent_rf_source_valid), // .valid
.rf_source_startofpacket (cpu_jtag_debug_module_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (cpu_jtag_debug_module_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (cpu_jtag_debug_module_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (cpu_jtag_debug_module_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (cpu_jtag_debug_module_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (cpu_jtag_debug_module_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (cpu_jtag_debug_module_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (cpu_jtag_debug_module_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (cpu_jtag_debug_module_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) cpu_jtag_debug_module_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (cpu_jtag_debug_module_agent_rf_source_data), // in.data
.in_valid (cpu_jtag_debug_module_agent_rf_source_valid), // .valid
.in_ready (cpu_jtag_debug_module_agent_rf_source_ready), // .ready
.in_startofpacket (cpu_jtag_debug_module_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (cpu_jtag_debug_module_agent_rf_source_endofpacket), // .endofpacket
.out_data (cpu_jtag_debug_module_agent_rsp_fifo_out_data), // out.data
.out_valid (cpu_jtag_debug_module_agent_rsp_fifo_out_valid), // .valid
.out_ready (cpu_jtag_debug_module_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (cpu_jtag_debug_module_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (cpu_jtag_debug_module_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_TRANS_LOCK (69),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_ORI_BURST_SIZE_H (104),
.ST_CHANNEL_W (6),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) sdram_s1_agent (
.clk (clocks_c0_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (sdram_s1_agent_m0_address), // m0.address
.m0_burstcount (sdram_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (sdram_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (sdram_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (sdram_s1_agent_m0_lock), // .lock
.m0_readdata (sdram_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (sdram_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (sdram_s1_agent_m0_read), // .read
.m0_waitrequest (sdram_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (sdram_s1_agent_m0_writedata), // .writedata
.m0_write (sdram_s1_agent_m0_write), // .write
.rp_endofpacket (sdram_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (sdram_s1_agent_rp_ready), // .ready
.rp_valid (sdram_s1_agent_rp_valid), // .valid
.rp_data (sdram_s1_agent_rp_data), // .data
.rp_startofpacket (sdram_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (sdram_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (sdram_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (sdram_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (sdram_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (sdram_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (sdram_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (sdram_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (sdram_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (sdram_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (sdram_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (sdram_s1_agent_rdata_fifo_out_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (sdram_s1_agent_rdata_fifo_out_valid), // .valid
.rdata_fifo_sink_data (sdram_s1_agent_rdata_fifo_out_data), // .data
.rdata_fifo_src_ready (sdram_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (sdram_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (sdram_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sdram_s1_agent_rsp_fifo (
.clk (clocks_c0_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sdram_s1_agent_rf_source_data), // in.data
.in_valid (sdram_s1_agent_rf_source_valid), // .valid
.in_ready (sdram_s1_agent_rf_source_ready), // .ready
.in_startofpacket (sdram_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (sdram_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (sdram_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (sdram_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (sdram_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (sdram_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (sdram_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) sdram_s1_agent_rdata_fifo (
.clk (clocks_c0_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (sdram_s1_agent_rdata_fifo_src_data), // in.data
.in_valid (sdram_s1_agent_rdata_fifo_src_valid), // .valid
.in_ready (sdram_s1_agent_rdata_fifo_src_ready), // .ready
.out_data (sdram_s1_agent_rdata_fifo_out_data), // out.data
.out_valid (sdram_s1_agent_rdata_fifo_out_valid), // .valid
.out_ready (sdram_s1_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_TRANS_LOCK (69),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_ORI_BURST_SIZE_H (104),
.ST_CHANNEL_W (6),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) clocks_pll_slave_agent (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (clocks_pll_slave_agent_m0_address), // m0.address
.m0_burstcount (clocks_pll_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (clocks_pll_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (clocks_pll_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (clocks_pll_slave_agent_m0_lock), // .lock
.m0_readdata (clocks_pll_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (clocks_pll_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (clocks_pll_slave_agent_m0_read), // .read
.m0_waitrequest (clocks_pll_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (clocks_pll_slave_agent_m0_writedata), // .writedata
.m0_write (clocks_pll_slave_agent_m0_write), // .write
.rp_endofpacket (clocks_pll_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (clocks_pll_slave_agent_rp_ready), // .ready
.rp_valid (clocks_pll_slave_agent_rp_valid), // .valid
.rp_data (clocks_pll_slave_agent_rp_data), // .data
.rp_startofpacket (clocks_pll_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_002_src_ready), // cp.ready
.cp_valid (cmd_mux_002_src_valid), // .valid
.cp_data (cmd_mux_002_src_data), // .data
.cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_002_src_channel), // .channel
.rf_sink_ready (clocks_pll_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (clocks_pll_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (clocks_pll_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (clocks_pll_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (clocks_pll_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (clocks_pll_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (clocks_pll_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (clocks_pll_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (clocks_pll_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (clocks_pll_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (clocks_pll_slave_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (clocks_pll_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (clocks_pll_slave_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (clocks_pll_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (clocks_pll_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (clocks_pll_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) clocks_pll_slave_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (clocks_pll_slave_agent_rf_source_data), // in.data
.in_valid (clocks_pll_slave_agent_rf_source_valid), // .valid
.in_ready (clocks_pll_slave_agent_rf_source_ready), // .ready
.in_startofpacket (clocks_pll_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (clocks_pll_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (clocks_pll_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (clocks_pll_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (clocks_pll_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (clocks_pll_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (clocks_pll_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_TRANS_LOCK (69),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_ORI_BURST_SIZE_H (104),
.ST_CHANNEL_W (6),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) keycode_s1_agent (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (keycode_s1_agent_m0_address), // m0.address
.m0_burstcount (keycode_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (keycode_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (keycode_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (keycode_s1_agent_m0_lock), // .lock
.m0_readdata (keycode_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (keycode_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (keycode_s1_agent_m0_read), // .read
.m0_waitrequest (keycode_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (keycode_s1_agent_m0_writedata), // .writedata
.m0_write (keycode_s1_agent_m0_write), // .write
.rp_endofpacket (keycode_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (keycode_s1_agent_rp_ready), // .ready
.rp_valid (keycode_s1_agent_rp_valid), // .valid
.rp_data (keycode_s1_agent_rp_data), // .data
.rp_startofpacket (keycode_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_003_src_ready), // cp.ready
.cp_valid (cmd_mux_003_src_valid), // .valid
.cp_data (cmd_mux_003_src_data), // .data
.cp_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_003_src_channel), // .channel
.rf_sink_ready (keycode_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (keycode_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (keycode_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (keycode_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (keycode_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (keycode_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (keycode_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (keycode_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (keycode_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (keycode_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (keycode_s1_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (keycode_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (keycode_s1_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (keycode_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (keycode_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (keycode_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) keycode_s1_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (keycode_s1_agent_rf_source_data), // in.data
.in_valid (keycode_s1_agent_rf_source_valid), // .valid
.in_ready (keycode_s1_agent_rf_source_ready), // .ready
.in_startofpacket (keycode_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (keycode_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (keycode_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (keycode_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (keycode_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (keycode_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (keycode_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_TRANS_LOCK (69),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_ORI_BURST_SIZE_H (104),
.ST_CHANNEL_W (6),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) jtag_uart_avalon_jtag_slave_agent (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (jtag_uart_avalon_jtag_slave_agent_m0_address), // m0.address
.m0_burstcount (jtag_uart_avalon_jtag_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (jtag_uart_avalon_jtag_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (jtag_uart_avalon_jtag_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (jtag_uart_avalon_jtag_slave_agent_m0_lock), // .lock
.m0_readdata (jtag_uart_avalon_jtag_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (jtag_uart_avalon_jtag_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (jtag_uart_avalon_jtag_slave_agent_m0_read), // .read
.m0_waitrequest (jtag_uart_avalon_jtag_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (jtag_uart_avalon_jtag_slave_agent_m0_writedata), // .writedata
.m0_write (jtag_uart_avalon_jtag_slave_agent_m0_write), // .write
.rp_endofpacket (jtag_uart_avalon_jtag_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (jtag_uart_avalon_jtag_slave_agent_rp_ready), // .ready
.rp_valid (jtag_uart_avalon_jtag_slave_agent_rp_valid), // .valid
.rp_data (jtag_uart_avalon_jtag_slave_agent_rp_data), // .data
.rp_startofpacket (jtag_uart_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_004_src_ready), // cp.ready
.cp_valid (cmd_mux_004_src_valid), // .valid
.cp_data (cmd_mux_004_src_data), // .data
.cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_004_src_channel), // .channel
.rf_sink_ready (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (jtag_uart_avalon_jtag_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (jtag_uart_avalon_jtag_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (jtag_uart_avalon_jtag_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (jtag_uart_avalon_jtag_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) jtag_uart_avalon_jtag_slave_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (jtag_uart_avalon_jtag_slave_agent_rf_source_data), // in.data
.in_valid (jtag_uart_avalon_jtag_slave_agent_rf_source_valid), // .valid
.in_ready (jtag_uart_avalon_jtag_slave_agent_rf_source_ready), // .ready
.in_startofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (jtag_uart_avalon_jtag_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (jtag_uart_avalon_jtag_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BEGIN_BURST (84),
.PKT_SYMBOL_W (8),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_ADDR_H (64),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (65),
.PKT_TRANS_POSTED (66),
.PKT_TRANS_WRITE (67),
.PKT_TRANS_READ (68),
.PKT_TRANS_LOCK (69),
.PKT_SRC_ID_H (88),
.PKT_SRC_ID_L (86),
.PKT_DEST_ID_H (91),
.PKT_DEST_ID_L (89),
.PKT_BURSTWRAP_H (76),
.PKT_BURSTWRAP_L (74),
.PKT_BYTE_CNT_H (73),
.PKT_BYTE_CNT_L (71),
.PKT_PROTECTION_H (95),
.PKT_PROTECTION_L (93),
.PKT_RESPONSE_STATUS_H (101),
.PKT_RESPONSE_STATUS_L (100),
.PKT_BURST_SIZE_H (79),
.PKT_BURST_SIZE_L (77),
.PKT_ORI_BURST_SIZE_L (102),
.PKT_ORI_BURST_SIZE_H (104),
.ST_CHANNEL_W (6),
.ST_DATA_W (105),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) clock_crossing_io_s0_agent (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (clock_crossing_io_s0_agent_m0_address), // m0.address
.m0_burstcount (clock_crossing_io_s0_agent_m0_burstcount), // .burstcount
.m0_byteenable (clock_crossing_io_s0_agent_m0_byteenable), // .byteenable
.m0_debugaccess (clock_crossing_io_s0_agent_m0_debugaccess), // .debugaccess
.m0_lock (clock_crossing_io_s0_agent_m0_lock), // .lock
.m0_readdata (clock_crossing_io_s0_agent_m0_readdata), // .readdata
.m0_readdatavalid (clock_crossing_io_s0_agent_m0_readdatavalid), // .readdatavalid
.m0_read (clock_crossing_io_s0_agent_m0_read), // .read
.m0_waitrequest (clock_crossing_io_s0_agent_m0_waitrequest), // .waitrequest
.m0_writedata (clock_crossing_io_s0_agent_m0_writedata), // .writedata
.m0_write (clock_crossing_io_s0_agent_m0_write), // .write
.rp_endofpacket (clock_crossing_io_s0_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (clock_crossing_io_s0_agent_rp_ready), // .ready
.rp_valid (clock_crossing_io_s0_agent_rp_valid), // .valid
.rp_data (clock_crossing_io_s0_agent_rp_data), // .data
.rp_startofpacket (clock_crossing_io_s0_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_005_src_ready), // cp.ready
.cp_valid (cmd_mux_005_src_valid), // .valid
.cp_data (cmd_mux_005_src_data), // .data
.cp_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_005_src_channel), // .channel
.rf_sink_ready (clock_crossing_io_s0_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (clock_crossing_io_s0_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (clock_crossing_io_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (clock_crossing_io_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (clock_crossing_io_s0_agent_rsp_fifo_out_data), // .data
.rf_source_ready (clock_crossing_io_s0_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (clock_crossing_io_s0_agent_rf_source_valid), // .valid
.rf_source_startofpacket (clock_crossing_io_s0_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (clock_crossing_io_s0_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (clock_crossing_io_s0_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (clock_crossing_io_s0_agent_rdata_fifo_src_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (clock_crossing_io_s0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_sink_data (clock_crossing_io_s0_agent_rdata_fifo_src_data), // .data
.rdata_fifo_src_ready (clock_crossing_io_s0_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (clock_crossing_io_s0_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (clock_crossing_io_s0_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponserequest (), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (106),
.FIFO_DEPTH (129),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) clock_crossing_io_s0_agent_rsp_fifo (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (clock_crossing_io_s0_agent_rf_source_data), // in.data
.in_valid (clock_crossing_io_s0_agent_rf_source_valid), // .valid
.in_ready (clock_crossing_io_s0_agent_rf_source_ready), // .ready
.in_startofpacket (clock_crossing_io_s0_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (clock_crossing_io_s0_agent_rf_source_endofpacket), // .endofpacket
.out_data (clock_crossing_io_s0_agent_rsp_fifo_out_data), // out.data
.out_valid (clock_crossing_io_s0_agent_rsp_fifo_out_valid), // .valid
.out_ready (clock_crossing_io_s0_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (clock_crossing_io_s0_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (clock_crossing_io_s0_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
usb_system_mm_interconnect_0_router router (
.sink_ready (cpu_instruction_master_agent_cp_ready), // sink.ready
.sink_valid (cpu_instruction_master_agent_cp_valid), // .valid
.sink_data (cpu_instruction_master_agent_cp_data), // .data
.sink_startofpacket (cpu_instruction_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_instruction_master_agent_cp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_router_001 router_001 (
.sink_ready (cpu_data_master_agent_cp_ready), // sink.ready
.sink_valid (cpu_data_master_agent_cp_valid), // .valid
.sink_data (cpu_data_master_agent_cp_data), // .data
.sink_startofpacket (cpu_data_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_data_master_agent_cp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_router_002 router_002 (
.sink_ready (cpu_jtag_debug_module_agent_rp_ready), // sink.ready
.sink_valid (cpu_jtag_debug_module_agent_rp_valid), // .valid
.sink_data (cpu_jtag_debug_module_agent_rp_data), // .data
.sink_startofpacket (cpu_jtag_debug_module_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (cpu_jtag_debug_module_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_router_002 router_003 (
.sink_ready (sdram_s1_agent_rp_ready), // sink.ready
.sink_valid (sdram_s1_agent_rp_valid), // .valid
.sink_data (sdram_s1_agent_rp_data), // .data
.sink_startofpacket (sdram_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (sdram_s1_agent_rp_endofpacket), // .endofpacket
.clk (clocks_c0_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_router_002 router_004 (
.sink_ready (clocks_pll_slave_agent_rp_ready), // sink.ready
.sink_valid (clocks_pll_slave_agent_rp_valid), // .valid
.sink_data (clocks_pll_slave_agent_rp_data), // .data
.sink_startofpacket (clocks_pll_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (clocks_pll_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_router_005 router_005 (
.sink_ready (keycode_s1_agent_rp_ready), // sink.ready
.sink_valid (keycode_s1_agent_rp_valid), // .valid
.sink_data (keycode_s1_agent_rp_data), // .data
.sink_startofpacket (keycode_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (keycode_s1_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_router_005 router_006 (
.sink_ready (jtag_uart_avalon_jtag_slave_agent_rp_ready), // sink.ready
.sink_valid (jtag_uart_avalon_jtag_slave_agent_rp_valid), // .valid
.sink_data (jtag_uart_avalon_jtag_slave_agent_rp_data), // .data
.sink_startofpacket (jtag_uart_avalon_jtag_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (jtag_uart_avalon_jtag_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_router_005 router_007 (
.sink_ready (clock_crossing_io_s0_agent_rp_ready), // sink.ready
.sink_valid (clock_crossing_io_s0_agent_rp_valid), // .valid
.sink_data (clock_crossing_io_s0_agent_rp_data), // .data
.sink_startofpacket (clock_crossing_io_s0_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (clock_crossing_io_s0_agent_rp_endofpacket), // .endofpacket
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_cmd_demux cmd_demux (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_demux_001_src2_valid), // .valid
.src2_data (cmd_demux_001_src2_data), // .data
.src2_channel (cmd_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_001_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_001_src3_ready), // src3.ready
.src3_valid (cmd_demux_001_src3_valid), // .valid
.src3_data (cmd_demux_001_src3_data), // .data
.src3_channel (cmd_demux_001_src3_channel), // .channel
.src3_startofpacket (cmd_demux_001_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_001_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_001_src4_ready), // src4.ready
.src4_valid (cmd_demux_001_src4_valid), // .valid
.src4_data (cmd_demux_001_src4_data), // .data
.src4_channel (cmd_demux_001_src4_channel), // .channel
.src4_startofpacket (cmd_demux_001_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_001_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_001_src5_ready), // src5.ready
.src5_valid (cmd_demux_001_src5_valid), // .valid
.src5_data (cmd_demux_001_src5_data), // .data
.src5_channel (cmd_demux_001_src5_channel), // .channel
.src5_startofpacket (cmd_demux_001_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_001_src5_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_cmd_mux cmd_mux (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_cmd_mux cmd_mux_001 (
.clk (clocks_c0_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (crosser_out_ready), // sink0.ready
.sink0_valid (crosser_out_valid), // .valid
.sink0_channel (crosser_out_channel), // .channel
.sink0_data (crosser_out_data), // .data
.sink0_startofpacket (crosser_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_out_endofpacket), // .endofpacket
.sink1_ready (crosser_001_out_ready), // sink1.ready
.sink1_valid (crosser_001_out_valid), // .valid
.sink1_channel (crosser_001_out_channel), // .channel
.sink1_data (crosser_001_out_data), // .data
.sink1_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.sink1_endofpacket (crosser_001_out_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_cmd_mux cmd_mux_002 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src2_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src2_valid), // .valid
.sink1_channel (cmd_demux_001_src2_channel), // .channel
.sink1_data (cmd_demux_001_src2_data), // .data
.sink1_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_cmd_mux_003 cmd_mux_003 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src3_valid), // .valid
.sink0_channel (cmd_demux_001_src3_channel), // .channel
.sink0_data (cmd_demux_001_src3_data), // .data
.sink0_startofpacket (cmd_demux_001_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src3_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_cmd_mux_003 cmd_mux_004 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src4_valid), // .valid
.sink0_channel (cmd_demux_001_src4_channel), // .channel
.sink0_data (cmd_demux_001_src4_data), // .data
.sink0_startofpacket (cmd_demux_001_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src4_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_cmd_mux_003 cmd_mux_005 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src5_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src5_valid), // .valid
.sink0_channel (cmd_demux_001_src5_channel), // .channel
.sink0_data (cmd_demux_001_src5_data), // .data
.sink0_startofpacket (cmd_demux_001_src5_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src5_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_rsp_demux rsp_demux (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_src1_ready), // src1.ready
.src1_valid (rsp_demux_src1_valid), // .valid
.src1_data (rsp_demux_src1_data), // .data
.src1_channel (rsp_demux_src1_channel), // .channel
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_rsp_demux rsp_demux_001 (
.clk (clocks_c0_clk), // clk.clk
.reset (sdram_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_rsp_demux rsp_demux_002 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_002_src1_ready), // src1.ready
.src1_valid (rsp_demux_002_src1_valid), // .valid
.src1_data (rsp_demux_002_src1_data), // .data
.src1_channel (rsp_demux_002_src1_channel), // .channel
.src1_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_002_src1_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_rsp_demux_003 rsp_demux_003 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_rsp_demux_003 rsp_demux_004 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_rsp_demux_003 rsp_demux_005 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_rsp_mux rsp_mux (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (crosser_002_out_ready), // sink1.ready
.sink1_valid (crosser_002_out_valid), // .valid
.sink1_channel (crosser_002_out_channel), // .channel
.sink1_data (crosser_002_out_data), // .data
.sink1_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.sink1_endofpacket (crosser_002_out_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket
);
usb_system_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
.clk (clk_clk_clk), // clk.clk
.reset (cpu_reset_n_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_src1_valid), // .valid
.sink0_channel (rsp_demux_src1_channel), // .channel
.sink0_data (rsp_demux_src1_data), // .data
.sink0_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
.sink1_ready (crosser_003_out_ready), // sink1.ready
.sink1_valid (crosser_003_out_valid), // .valid
.sink1_channel (crosser_003_out_channel), // .channel
.sink1_data (crosser_003_out_data), // .data
.sink1_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.sink1_endofpacket (crosser_003_out_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src1_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src1_valid), // .valid
.sink2_channel (rsp_demux_002_src1_channel), // .channel
.sink2_data (rsp_demux_002_src1_data), // .data
.sink2_startofpacket (rsp_demux_002_src1_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src1_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_demux_005_src0_valid), // .valid
.sink5_channel (rsp_demux_005_src0_channel), // .channel
.sink5_data (rsp_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (105),
.BITS_PER_SYMBOL (105),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (6),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser (
.in_clk (clk_clk_clk), // in_clk.clk
.in_reset (cpu_reset_n_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clocks_c0_clk), // out_clk.clk
.out_reset (sdram_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src1_ready), // in.ready
.in_valid (cmd_demux_src1_valid), // .valid
.in_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.in_channel (cmd_demux_src1_channel), // .channel
.in_data (cmd_demux_src1_data), // .data
.out_ready (crosser_out_ready), // out.ready
.out_valid (crosser_out_valid), // .valid
.out_startofpacket (crosser_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_out_endofpacket), // .endofpacket
.out_channel (crosser_out_channel), // .channel
.out_data (crosser_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (105),
.BITS_PER_SYMBOL (105),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (6),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_001 (
.in_clk (clk_clk_clk), // in_clk.clk
.in_reset (cpu_reset_n_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clocks_c0_clk), // out_clk.clk
.out_reset (sdram_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_001_src1_ready), // in.ready
.in_valid (cmd_demux_001_src1_valid), // .valid
.in_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.in_channel (cmd_demux_001_src1_channel), // .channel
.in_data (cmd_demux_001_src1_data), // .data
.out_ready (crosser_001_out_ready), // out.ready
.out_valid (crosser_001_out_valid), // .valid
.out_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.out_channel (crosser_001_out_channel), // .channel
.out_data (crosser_001_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (105),
.BITS_PER_SYMBOL (105),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (6),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_002 (
.in_clk (clocks_c0_clk), // in_clk.clk
.in_reset (sdram_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_clk_clk), // out_clk.clk
.out_reset (cpu_reset_n_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_001_src0_ready), // in.ready
.in_valid (rsp_demux_001_src0_valid), // .valid
.in_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_001_src0_channel), // .channel
.in_data (rsp_demux_001_src0_data), // .data
.out_ready (crosser_002_out_ready), // out.ready
.out_valid (crosser_002_out_valid), // .valid
.out_startofpacket (crosser_002_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_002_out_endofpacket), // .endofpacket
.out_channel (crosser_002_out_channel), // .channel
.out_data (crosser_002_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (105),
.BITS_PER_SYMBOL (105),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (6),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_003 (
.in_clk (clocks_c0_clk), // in_clk.clk
.in_reset (sdram_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_clk_clk), // out_clk.clk
.out_reset (cpu_reset_n_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_001_src1_ready), // in.ready
.in_valid (rsp_demux_001_src1_valid), // .valid
.in_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.in_channel (rsp_demux_001_src1_channel), // .channel
.in_data (rsp_demux_001_src1_data), // .data
.out_ready (crosser_003_out_ready), // out.ready
.out_valid (crosser_003_out_valid), // .valid
.out_startofpacket (crosser_003_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_003_out_endofpacket), // .endofpacket
.out_channel (crosser_003_out_channel), // .channel
.out_data (crosser_003_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Spartan-6 Integrated Block for PCI Express
// File : axi_basic_top.v
//----------------------------------------------------------------------------//
// File: axi_basic_top.v //
// //
// Description: //
// TRN/AXI4-S Bridge top level module. Instantiates RX and TX modules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module axi_basic_top #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter STRB_WIDTH = C_DATA_WIDTH / 8 // TKEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [STRB_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [STRB_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output [21:0] m_axis_rx_tuser, // RX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
//---------------------------------------------//
// RX Data Pipeline //
//---------------------------------------------//
axi_basic_rx #(
.C_DATA_WIDTH (C_DATA_WIDTH ),
.C_FAMILY (C_FAMILY ),
.TCQ (TCQ ),
.REM_WIDTH (REM_WIDTH ),
.STRB_WIDTH (STRB_WIDTH )
) rx_inst (
// Outgoing AXI TX
//-----------
.m_axis_rx_tdata (m_axis_rx_tdata ),
.m_axis_rx_tvalid (m_axis_rx_tvalid ),
.m_axis_rx_tready (m_axis_rx_tready ),
.m_axis_rx_tkeep (m_axis_rx_tkeep ),
.m_axis_rx_tlast (m_axis_rx_tlast ),
.m_axis_rx_tuser (m_axis_rx_tuser ),
// Incoming TRN RX
//-----------
.trn_rd (trn_rd ),
.trn_rsof (trn_rsof ),
.trn_reof (trn_reof ),
.trn_rsrc_rdy (trn_rsrc_rdy ),
.trn_rdst_rdy (trn_rdst_rdy ),
.trn_rsrc_dsc (trn_rsrc_dsc ),
.trn_rrem (trn_rrem ),
.trn_rerrfwd (trn_rerrfwd ),
.trn_rbar_hit (trn_rbar_hit ),
.trn_recrc_err (trn_recrc_err ),
// System
//-----------
.np_counter (np_counter ),
.user_clk (user_clk ),
.user_rst (user_rst )
);
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
axi_basic_tx #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.STRB_WIDTH( STRB_WIDTH )
) tx_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tkeep( s_axis_tx_tkeep ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
// User Misc.
//-----------
.user_turnoff_ok( user_turnoff_ok ),
.user_tcfg_gnt( user_tcfg_gnt ),
// Outgoing TRN TX
//-----------
.trn_td( trn_td ),
.trn_tsof( trn_tsof ),
.trn_teof( trn_teof ),
.trn_tsrc_rdy( trn_tsrc_rdy ),
.trn_tdst_rdy( trn_tdst_rdy ),
.trn_tsrc_dsc( trn_tsrc_dsc ),
.trn_trem( trn_trem ),
.trn_terrfwd( trn_terrfwd ),
.trn_tstr( trn_tstr ),
.trn_tbuf_av( trn_tbuf_av ),
.trn_tecrc_gen( trn_tecrc_gen ),
// TRN Misc.
//-----------
.trn_tcfg_req( trn_tcfg_req ),
.trn_tcfg_gnt( trn_tcfg_gnt ),
.trn_lnk_up( trn_lnk_up ),
// 7 Series/Virtex6 PM
//-----------
.cfg_pcie_link_state( cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
.trn_rdllp_data( trn_rdllp_data ),
.trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
// System
//-----------
.user_clk( user_clk ),
.user_rst( user_rst )
);
endmodule
|
module mojo_top(
// 50MHz clock input
input clk,
// Input from reset button (active low)
input rst_n,
output DIO, // Data of YL-3
output RCK, // Latch of YL-3
output SCK // Clock of Yl-3
);
reg [63:0] data;
reg load;
reg [2:0] aidx = 3'b0;
reg [16:0] nxtcnt = 17'b0;
wire [7:0] str [0:5][0:7];
wire rst = ~rst_n; // make reset active high
wire ready;
localparam nxt = 17'd124999;
assign str[0][0] = " ";
assign str[0][1] = " ";
assign str[0][2] = " ";
assign str[0][3] = "H";
assign str[0][4] = "E";
assign str[0][5] = "L";
assign str[0][6] = "L";
assign str[0][7] = "O";
assign str[1][0] = " ";
assign str[1][1] = " ";
assign str[1][2] = "H";
assign str[1][3] = "E";
assign str[1][4] = "L";
assign str[1][5] = "L";
assign str[1][6] = "O";
assign str[1][7] = " ";
assign str[2][0] = " ";
assign str[2][1] = "H";
assign str[2][2] = "E";
assign str[2][3] = "L";
assign str[2][4] = "L";
assign str[2][5] = "O";
assign str[2][6] = " ";
assign str[2][7] = " ";
assign str[3][0] = "H";
assign str[3][1] = "E";
assign str[3][2] = "L";
assign str[3][3] = "L";
assign str[3][4] = "O";
assign str[3][5] = " ";
assign str[3][6] = " ";
assign str[3][7] = " ";
assign str[4][0] = " ";
assign str[4][1] = "H";
assign str[4][2] = "E";
assign str[4][3] = "L";
assign str[4][4] = "L";
assign str[4][5] = "O";
assign str[4][6] = " ";
assign str[4][7] = " ";
assign str[5][0] = " ";
assign str[5][1] = " ";
assign str[5][2] = "H";
assign str[5][3] = "E";
assign str[5][4] = "L";
assign str[5][5] = "L";
assign str[5][6] = "O";
assign str[5][7] = " ";
yl3_interface yl3(
.CLK(clk),
.nRST(rst_n),
.DATA(data),
.LOAD(load),
.SCK(SCK),
.DIO(DIO),
.RCK(RCK),
.READY(ready)
);
always @(posedge clk)
begin
if(ready == 1'b1)
begin
aidx <= (aidx == 3'd6) ? 3'd0 : aidx;
if(nxtcnt == 20'b0)
begin
data <= {str[aidx][0], str[aidx][1], str[aidx][2], str[aidx][3], str[aidx][4], str[aidx][5], str[aidx][6], str[aidx][7]};
aidx <= aidx + 1'b1;
load <= 1'b1;
end
nxtcnt <= (nxtcnt < nxt) ? nxtcnt + 1'b1 : nxtcnt <= 17'b0;
end
else
begin
end
end
endmodule |
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
module Loop_loop_height_pro (
ap_clk,
ap_rst,
ap_start,
ap_done,
ap_continue,
ap_idle,
ap_ready,
p_rows_assign_cast_loc_dout,
p_rows_assign_cast_loc_empty_n,
p_rows_assign_cast_loc_read,
p_cols_assign_cast_loc_dout,
p_cols_assign_cast_loc_empty_n,
p_cols_assign_cast_loc_read,
img2_data_stream_0_V_din,
img2_data_stream_0_V_full_n,
img2_data_stream_0_V_write,
img2_data_stream_1_V_din,
img2_data_stream_1_V_full_n,
img2_data_stream_1_V_write,
img2_data_stream_2_V_din,
img2_data_stream_2_V_full_n,
img2_data_stream_2_V_write,
img1_data_stream_0_V_dout,
img1_data_stream_0_V_empty_n,
img1_data_stream_0_V_read,
img1_data_stream_1_V_dout,
img1_data_stream_1_V_empty_n,
img1_data_stream_1_V_read,
img1_data_stream_2_V_dout,
img1_data_stream_2_V_empty_n,
img1_data_stream_2_V_read,
sat_dout,
sat_empty_n,
sat_read
);
parameter ap_ST_fsm_state1 = 5'd1;
parameter ap_ST_fsm_state2 = 5'd2;
parameter ap_ST_fsm_state3 = 5'd4;
parameter ap_ST_fsm_pp0_stage0 = 5'd8;
parameter ap_ST_fsm_state9 = 5'd16;
input ap_clk;
input ap_rst;
input ap_start;
output ap_done;
input ap_continue;
output ap_idle;
output ap_ready;
input [11:0] p_rows_assign_cast_loc_dout;
input p_rows_assign_cast_loc_empty_n;
output p_rows_assign_cast_loc_read;
input [11:0] p_cols_assign_cast_loc_dout;
input p_cols_assign_cast_loc_empty_n;
output p_cols_assign_cast_loc_read;
output [7:0] img2_data_stream_0_V_din;
input img2_data_stream_0_V_full_n;
output img2_data_stream_0_V_write;
output [7:0] img2_data_stream_1_V_din;
input img2_data_stream_1_V_full_n;
output img2_data_stream_1_V_write;
output [7:0] img2_data_stream_2_V_din;
input img2_data_stream_2_V_full_n;
output img2_data_stream_2_V_write;
input [7:0] img1_data_stream_0_V_dout;
input img1_data_stream_0_V_empty_n;
output img1_data_stream_0_V_read;
input [7:0] img1_data_stream_1_V_dout;
input img1_data_stream_1_V_empty_n;
output img1_data_stream_1_V_read;
input [7:0] img1_data_stream_2_V_dout;
input img1_data_stream_2_V_empty_n;
output img1_data_stream_2_V_read;
input [7:0] sat_dout;
input sat_empty_n;
output sat_read;
reg ap_done;
reg ap_idle;
reg ap_ready;
reg p_rows_assign_cast_loc_read;
reg p_cols_assign_cast_loc_read;
reg img2_data_stream_0_V_write;
reg img2_data_stream_1_V_write;
reg img2_data_stream_2_V_write;
reg img1_data_stream_0_V_read;
reg img1_data_stream_1_V_read;
reg img1_data_stream_2_V_read;
reg sat_read;
reg ap_done_reg;
(* fsm_encoding = "none" *) reg [4:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
wire [7:0] lut_s_1_2_address0;
reg lut_s_1_2_ce0;
wire [7:0] lut_s_1_2_q0;
wire [7:0] lut_s_n0_2_address0;
reg lut_s_n0_2_ce0;
wire [7:0] lut_s_n0_2_q0;
wire [7:0] lut_s_0_2_address0;
reg lut_s_0_2_ce0;
wire [7:0] lut_s_0_2_q0;
wire [7:0] lut_s_0_4_address0;
reg lut_s_0_4_ce0;
wire [7:0] lut_s_0_4_q0;
wire [7:0] lut_s_0_6_address0;
reg lut_s_0_6_ce0;
wire [7:0] lut_s_0_6_q0;
wire [7:0] lut_s_0_8_address0;
reg lut_s_0_8_ce0;
wire [7:0] lut_s_0_8_q0;
wire [7:0] lut_s_1_0_address0;
reg lut_s_1_0_ce0;
wire [7:0] lut_s_1_0_q0;
reg p_rows_assign_cast_loc_blk_n;
reg p_cols_assign_cast_loc_blk_n;
reg img2_data_stream_0_V_blk_n;
reg ap_enable_reg_pp0_iter4;
wire ap_block_pp0_stage0;
reg [0:0] exitcond_i_i_i_reg_478;
reg [0:0] ap_reg_pp0_iter3_exitcond_i_i_i_reg_478;
reg img2_data_stream_1_V_blk_n;
reg img2_data_stream_2_V_blk_n;
reg img1_data_stream_0_V_blk_n;
wire ap_CS_fsm_pp0_stage0;
reg ap_enable_reg_pp0_iter1;
reg img1_data_stream_1_V_blk_n;
reg img1_data_stream_2_V_blk_n;
reg sat_blk_n;
reg [10:0] t_V_2_reg_252;
reg [11:0] p_rows_assign_cast_lo_reg_406;
reg ap_block_state1;
reg [11:0] p_cols_assign_cast_lo_reg_411;
wire [0:0] sel_tmp_fu_263_p2;
reg [0:0] sel_tmp_reg_416;
wire [0:0] sel_tmp2_fu_269_p2;
reg [0:0] sel_tmp2_reg_421;
wire [0:0] sel_tmp4_fu_275_p2;
reg [0:0] sel_tmp4_reg_426;
wire [0:0] sel_tmp6_fu_281_p2;
reg [0:0] sel_tmp6_reg_432;
wire [0:0] sel_tmp8_fu_287_p2;
reg [0:0] sel_tmp8_reg_437;
wire [0:0] sel_tmp1_fu_293_p2;
reg [0:0] sel_tmp1_reg_443;
wire [0:0] sel_tmp3_fu_299_p2;
reg [0:0] sel_tmp3_reg_448;
wire [0:0] or_cond_fu_305_p2;
reg [0:0] or_cond_reg_454;
wire ap_CS_fsm_state2;
wire [0:0] or_cond2_fu_313_p2;
reg [0:0] or_cond2_reg_459;
wire [0:0] or_cond3_fu_317_p2;
reg [0:0] or_cond3_reg_464;
wire [0:0] exitcond51_i_i_i_fu_327_p2;
wire ap_CS_fsm_state3;
wire [10:0] i_V_fu_332_p2;
reg [10:0] i_V_reg_473;
wire [0:0] exitcond_i_i_i_fu_342_p2;
wire ap_block_state4_pp0_stage0_iter0;
reg ap_block_state5_pp0_stage0_iter1;
wire ap_block_state6_pp0_stage0_iter2;
wire ap_block_state7_pp0_stage0_iter3;
reg ap_block_state8_pp0_stage0_iter4;
reg ap_block_pp0_stage0_11001;
reg [0:0] ap_reg_pp0_iter1_exitcond_i_i_i_reg_478;
reg [0:0] ap_reg_pp0_iter2_exitcond_i_i_i_reg_478;
wire [10:0] j_V_fu_347_p2;
reg ap_enable_reg_pp0_iter0;
reg [7:0] tmp_reg_487;
reg [7:0] ap_reg_pp0_iter2_tmp_reg_487;
reg [7:0] ap_reg_pp0_iter3_tmp_reg_487;
reg [7:0] tmp_7_reg_492;
reg [7:0] ap_reg_pp0_iter2_tmp_7_reg_492;
reg [7:0] ap_reg_pp0_iter3_tmp_7_reg_492;
reg [7:0] tmp_9_reg_497;
reg [7:0] ap_reg_pp0_iter2_tmp_9_reg_497;
reg [7:0] d_val_2_2_reg_538;
reg [7:0] d_val_2_3_reg_543;
reg [7:0] d_val_2_6_reg_548;
reg [7:0] d_val_2_7_reg_553;
wire [7:0] newSel1_fu_363_p3;
reg [7:0] newSel1_reg_558;
wire [7:0] newSel3_fu_370_p3;
reg [7:0] newSel3_reg_563;
reg ap_block_pp0_stage0_subdone;
reg ap_condition_pp0_exit_iter0_state4;
reg ap_enable_reg_pp0_iter2;
reg ap_enable_reg_pp0_iter3;
reg [10:0] t_V_reg_241;
wire ap_CS_fsm_state9;
wire [63:0] tmp_5_i_i_fu_353_p1;
reg ap_block_pp0_stage0_01001;
wire [0:0] or_cond1_fu_309_p2;
wire [11:0] t_V_cast_i_i_fu_323_p1;
wire [11:0] t_V_1_cast_i_i_fu_338_p1;
wire [7:0] newSel_fu_376_p3;
wire [7:0] newSel2_fu_381_p3;
wire [7:0] newSel4_fu_386_p3;
wire [7:0] newSel5_fu_392_p3;
reg [4:0] ap_NS_fsm;
reg ap_idle_pp0;
wire ap_enable_pp0;
// power-on initialization
initial begin
#0 ap_done_reg = 1'b0;
#0 ap_CS_fsm = 5'd1;
#0 ap_enable_reg_pp0_iter4 = 1'b0;
#0 ap_enable_reg_pp0_iter1 = 1'b0;
#0 ap_enable_reg_pp0_iter0 = 1'b0;
#0 ap_enable_reg_pp0_iter2 = 1'b0;
#0 ap_enable_reg_pp0_iter3 = 1'b0;
end
Loop_loop_height_fYi #(
.DataWidth( 8 ),
.AddressRange( 256 ),
.AddressWidth( 8 ))
lut_s_1_2_U(
.clk(ap_clk),
.reset(ap_rst),
.address0(lut_s_1_2_address0),
.ce0(lut_s_1_2_ce0),
.q0(lut_s_1_2_q0)
);
Loop_loop_height_g8j #(
.DataWidth( 8 ),
.AddressRange( 256 ),
.AddressWidth( 8 ))
lut_s_n0_2_U(
.clk(ap_clk),
.reset(ap_rst),
.address0(lut_s_n0_2_address0),
.ce0(lut_s_n0_2_ce0),
.q0(lut_s_n0_2_q0)
);
Loop_loop_height_hbi #(
.DataWidth( 8 ),
.AddressRange( 256 ),
.AddressWidth( 8 ))
lut_s_0_2_U(
.clk(ap_clk),
.reset(ap_rst),
.address0(lut_s_0_2_address0),
.ce0(lut_s_0_2_ce0),
.q0(lut_s_0_2_q0)
);
Loop_loop_height_ibs #(
.DataWidth( 8 ),
.AddressRange( 256 ),
.AddressWidth( 8 ))
lut_s_0_4_U(
.clk(ap_clk),
.reset(ap_rst),
.address0(lut_s_0_4_address0),
.ce0(lut_s_0_4_ce0),
.q0(lut_s_0_4_q0)
);
Loop_loop_height_jbC #(
.DataWidth( 8 ),
.AddressRange( 256 ),
.AddressWidth( 8 ))
lut_s_0_6_U(
.clk(ap_clk),
.reset(ap_rst),
.address0(lut_s_0_6_address0),
.ce0(lut_s_0_6_ce0),
.q0(lut_s_0_6_q0)
);
Loop_loop_height_kbM #(
.DataWidth( 8 ),
.AddressRange( 256 ),
.AddressWidth( 8 ))
lut_s_0_8_U(
.clk(ap_clk),
.reset(ap_rst),
.address0(lut_s_0_8_address0),
.ce0(lut_s_0_8_ce0),
.q0(lut_s_0_8_q0)
);
Loop_loop_height_lbW #(
.DataWidth( 8 ),
.AddressRange( 256 ),
.AddressWidth( 8 ))
lut_s_1_0_U(
.clk(ap_clk),
.reset(ap_rst),
.address0(lut_s_1_0_address0),
.ce0(lut_s_1_0_ce0),
.q0(lut_s_1_0_q0)
);
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_done_reg <= 1'b0;
end else begin
if ((ap_continue == 1'b1)) begin
ap_done_reg <= 1'b0;
end else if (((1'b1 == ap_CS_fsm_state3) & (exitcond51_i_i_i_fu_327_p2 == 1'd1))) begin
ap_done_reg <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter0 <= 1'b0;
end else begin
if (((1'b0 == ap_block_pp0_stage0_subdone) & (1'b1 == ap_condition_pp0_exit_iter0_state4) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
ap_enable_reg_pp0_iter0 <= 1'b0;
end else if (((1'b1 == ap_CS_fsm_state3) & (exitcond51_i_i_i_fu_327_p2 == 1'd0))) begin
ap_enable_reg_pp0_iter0 <= 1'b1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter1 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
if ((1'b1 == ap_condition_pp0_exit_iter0_state4)) begin
ap_enable_reg_pp0_iter1 <= (1'b1 ^ ap_condition_pp0_exit_iter0_state4);
end else if ((1'b1 == 1'b1)) begin
ap_enable_reg_pp0_iter1 <= ap_enable_reg_pp0_iter0;
end
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter2 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter3 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter3 <= ap_enable_reg_pp0_iter2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst == 1'b1) begin
ap_enable_reg_pp0_iter4 <= 1'b0;
end else begin
if ((1'b0 == ap_block_pp0_stage0_subdone)) begin
ap_enable_reg_pp0_iter4 <= ap_enable_reg_pp0_iter3;
end else if (((1'b1 == ap_CS_fsm_state3) & (exitcond51_i_i_i_fu_327_p2 == 1'd0))) begin
ap_enable_reg_pp0_iter4 <= 1'b0;
end
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter0 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (exitcond_i_i_i_fu_342_p2 == 1'd0))) begin
t_V_2_reg_252 <= j_V_fu_347_p2;
end else if (((1'b1 == ap_CS_fsm_state3) & (exitcond51_i_i_i_fu_327_p2 == 1'd0))) begin
t_V_2_reg_252 <= 11'd0;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state9)) begin
t_V_reg_241 <= i_V_reg_473;
end else if ((1'b1 == ap_CS_fsm_state2)) begin
t_V_reg_241 <= 11'd0;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0))) begin
ap_reg_pp0_iter1_exitcond_i_i_i_reg_478 <= exitcond_i_i_i_reg_478;
exitcond_i_i_i_reg_478 <= exitcond_i_i_i_fu_342_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b0 == ap_block_pp0_stage0_11001)) begin
ap_reg_pp0_iter2_exitcond_i_i_i_reg_478 <= ap_reg_pp0_iter1_exitcond_i_i_i_reg_478;
ap_reg_pp0_iter2_tmp_7_reg_492 <= tmp_7_reg_492;
ap_reg_pp0_iter2_tmp_9_reg_497 <= tmp_9_reg_497;
ap_reg_pp0_iter2_tmp_reg_487 <= tmp_reg_487;
ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 <= ap_reg_pp0_iter2_exitcond_i_i_i_reg_478;
ap_reg_pp0_iter3_tmp_7_reg_492 <= ap_reg_pp0_iter2_tmp_7_reg_492;
ap_reg_pp0_iter3_tmp_reg_487 <= ap_reg_pp0_iter2_tmp_reg_487;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (or_cond3_reg_464 == 1'd1) & (or_cond_reg_454 == 1'd1) & (sel_tmp3_reg_448 == 1'd1) & (ap_reg_pp0_iter2_exitcond_i_i_i_reg_478 == 1'd0))) begin
d_val_2_2_reg_538 <= lut_s_n0_2_q0;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (or_cond3_reg_464 == 1'd1) & (or_cond_reg_454 == 1'd1) & (ap_reg_pp0_iter2_exitcond_i_i_i_reg_478 == 1'd0) & (sel_tmp3_reg_448 == 1'd0))) begin
d_val_2_3_reg_543 <= lut_s_0_2_q0;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (or_cond2_reg_459 == 1'd1) & (sel_tmp4_reg_426 == 1'd1) & (ap_reg_pp0_iter2_exitcond_i_i_i_reg_478 == 1'd0) & (or_cond3_reg_464 == 1'd0))) begin
d_val_2_6_reg_548 <= lut_s_0_8_q0;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (or_cond2_reg_459 == 1'd1) & (ap_reg_pp0_iter2_exitcond_i_i_i_reg_478 == 1'd0) & (or_cond3_reg_464 == 1'd0) & (sel_tmp4_reg_426 == 1'd0))) begin
d_val_2_7_reg_553 <= lut_s_1_0_q0;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state3)) begin
i_V_reg_473 <= i_V_fu_332_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (or_cond3_reg_464 == 1'd1) & (ap_reg_pp0_iter2_exitcond_i_i_i_reg_478 == 1'd0) & (or_cond_reg_454 == 1'd0))) begin
newSel1_reg_558 <= newSel1_fu_363_p3;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_reg_pp0_iter2_exitcond_i_i_i_reg_478 == 1'd0) & (or_cond3_reg_464 == 1'd0) & (or_cond2_reg_459 == 1'd0))) begin
newSel3_reg_563 <= newSel3_fu_370_p3;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == ap_CS_fsm_state2)) begin
or_cond2_reg_459 <= or_cond2_fu_313_p2;
or_cond3_reg_464 <= or_cond3_fu_317_p2;
or_cond_reg_454 <= or_cond_fu_305_p2;
end
end
always @ (posedge ap_clk) begin
if ((~((sat_empty_n == 1'b0) | (p_cols_assign_cast_loc_empty_n == 1'b0) | (p_rows_assign_cast_loc_empty_n == 1'b0) | (ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_cols_assign_cast_lo_reg_411 <= p_cols_assign_cast_loc_dout;
p_rows_assign_cast_lo_reg_406 <= p_rows_assign_cast_loc_dout;
sel_tmp1_reg_443 <= sel_tmp1_fu_293_p2;
sel_tmp2_reg_421 <= sel_tmp2_fu_269_p2;
sel_tmp3_reg_448 <= sel_tmp3_fu_299_p2;
sel_tmp4_reg_426 <= sel_tmp4_fu_275_p2;
sel_tmp6_reg_432 <= sel_tmp6_fu_281_p2;
sel_tmp8_reg_437 <= sel_tmp8_fu_287_p2;
sel_tmp_reg_416 <= sel_tmp_fu_263_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (1'b1 == ap_CS_fsm_pp0_stage0) & (exitcond_i_i_i_reg_478 == 1'd0))) begin
tmp_7_reg_492 <= img1_data_stream_1_V_dout;
tmp_9_reg_497 <= img1_data_stream_2_V_dout;
tmp_reg_487 <= img1_data_stream_0_V_dout;
end
end
always @ (*) begin
if ((exitcond_i_i_i_fu_342_p2 == 1'd1)) begin
ap_condition_pp0_exit_iter0_state4 = 1'b1;
end else begin
ap_condition_pp0_exit_iter0_state4 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & (exitcond51_i_i_i_fu_327_p2 == 1'd1))) begin
ap_done = 1'b1;
end else begin
ap_done = ap_done_reg;
end
end
always @ (*) begin
if (((ap_start == 1'b0) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter3 == 1'b0) & (ap_enable_reg_pp0_iter2 == 1'b0) & (ap_enable_reg_pp0_iter0 == 1'b0) & (ap_enable_reg_pp0_iter1 == 1'b0) & (ap_enable_reg_pp0_iter4 == 1'b0))) begin
ap_idle_pp0 = 1'b1;
end else begin
ap_idle_pp0 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_state3) & (exitcond51_i_i_i_fu_327_p2 == 1'd1))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (exitcond_i_i_i_reg_478 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin
img1_data_stream_0_V_blk_n = img1_data_stream_0_V_empty_n;
end else begin
img1_data_stream_0_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (exitcond_i_i_i_reg_478 == 1'd0))) begin
img1_data_stream_0_V_read = 1'b1;
end else begin
img1_data_stream_0_V_read = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (exitcond_i_i_i_reg_478 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin
img1_data_stream_1_V_blk_n = img1_data_stream_1_V_empty_n;
end else begin
img1_data_stream_1_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (exitcond_i_i_i_reg_478 == 1'd0))) begin
img1_data_stream_1_V_read = 1'b1;
end else begin
img1_data_stream_1_V_read = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (exitcond_i_i_i_reg_478 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin
img1_data_stream_2_V_blk_n = img1_data_stream_2_V_empty_n;
end else begin
img1_data_stream_2_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter1 == 1'b1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (exitcond_i_i_i_reg_478 == 1'd0))) begin
img1_data_stream_2_V_read = 1'b1;
end else begin
img1_data_stream_2_V_read = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter4 == 1'b1) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin
img2_data_stream_0_V_blk_n = img2_data_stream_0_V_full_n;
end else begin
img2_data_stream_0_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 == 1'd0))) begin
img2_data_stream_0_V_write = 1'b1;
end else begin
img2_data_stream_0_V_write = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter4 == 1'b1) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin
img2_data_stream_1_V_blk_n = img2_data_stream_1_V_full_n;
end else begin
img2_data_stream_1_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 == 1'd0))) begin
img2_data_stream_1_V_write = 1'b1;
end else begin
img2_data_stream_1_V_write = 1'b0;
end
end
always @ (*) begin
if (((ap_enable_reg_pp0_iter4 == 1'b1) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 == 1'd0) & (1'b0 == ap_block_pp0_stage0))) begin
img2_data_stream_2_V_blk_n = img2_data_stream_2_V_full_n;
end else begin
img2_data_stream_2_V_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter4 == 1'b1) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 == 1'd0))) begin
img2_data_stream_2_V_write = 1'b1;
end else begin
img2_data_stream_2_V_write = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut_s_0_2_ce0 = 1'b1;
end else begin
lut_s_0_2_ce0 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut_s_0_4_ce0 = 1'b1;
end else begin
lut_s_0_4_ce0 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut_s_0_6_ce0 = 1'b1;
end else begin
lut_s_0_6_ce0 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut_s_0_8_ce0 = 1'b1;
end else begin
lut_s_0_8_ce0 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut_s_1_0_ce0 = 1'b1;
end else begin
lut_s_1_0_ce0 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut_s_1_2_ce0 = 1'b1;
end else begin
lut_s_1_2_ce0 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_block_pp0_stage0_11001) & (ap_enable_reg_pp0_iter2 == 1'b1))) begin
lut_s_n0_2_ce0 = 1'b1;
end else begin
lut_s_n0_2_ce0 = 1'b0;
end
end
always @ (*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_cols_assign_cast_loc_blk_n = p_cols_assign_cast_loc_empty_n;
end else begin
p_cols_assign_cast_loc_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((sat_empty_n == 1'b0) | (p_cols_assign_cast_loc_empty_n == 1'b0) | (p_rows_assign_cast_loc_empty_n == 1'b0) | (ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_cols_assign_cast_loc_read = 1'b1;
end else begin
p_cols_assign_cast_loc_read = 1'b0;
end
end
always @ (*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_rows_assign_cast_loc_blk_n = p_rows_assign_cast_loc_empty_n;
end else begin
p_rows_assign_cast_loc_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((sat_empty_n == 1'b0) | (p_cols_assign_cast_loc_empty_n == 1'b0) | (p_rows_assign_cast_loc_empty_n == 1'b0) | (ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
p_rows_assign_cast_loc_read = 1'b1;
end else begin
p_rows_assign_cast_loc_read = 1'b0;
end
end
always @ (*) begin
if ((~((ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
sat_blk_n = sat_empty_n;
end else begin
sat_blk_n = 1'b1;
end
end
always @ (*) begin
if ((~((sat_empty_n == 1'b0) | (p_cols_assign_cast_loc_empty_n == 1'b0) | (p_rows_assign_cast_loc_empty_n == 1'b0) | (ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
sat_read = 1'b1;
end else begin
sat_read = 1'b0;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
if ((~((sat_empty_n == 1'b0) | (p_cols_assign_cast_loc_empty_n == 1'b0) | (p_rows_assign_cast_loc_empty_n == 1'b0) | (ap_start == 1'b0) | (ap_done_reg == 1'b1)) & (1'b1 == ap_CS_fsm_state1))) begin
ap_NS_fsm = ap_ST_fsm_state2;
end else begin
ap_NS_fsm = ap_ST_fsm_state1;
end
end
ap_ST_fsm_state2 : begin
ap_NS_fsm = ap_ST_fsm_state3;
end
ap_ST_fsm_state3 : begin
if (((1'b1 == ap_CS_fsm_state3) & (exitcond51_i_i_i_fu_327_p2 == 1'd1))) begin
ap_NS_fsm = ap_ST_fsm_state1;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end
end
ap_ST_fsm_pp0_stage0 : begin
if ((~((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (exitcond_i_i_i_fu_342_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0)) & ~((ap_enable_reg_pp0_iter3 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter4 == 1'b1)))) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end else if ((((1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter0 == 1'b1) & (exitcond_i_i_i_fu_342_p2 == 1'd1) & (ap_enable_reg_pp0_iter1 == 1'b0)) | ((ap_enable_reg_pp0_iter3 == 1'b0) & (1'b0 == ap_block_pp0_stage0_subdone) & (ap_enable_reg_pp0_iter4 == 1'b1)))) begin
ap_NS_fsm = ap_ST_fsm_state9;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end
end
ap_ST_fsm_state9 : begin
ap_NS_fsm = ap_ST_fsm_state3;
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd3];
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_CS_fsm_state2 = ap_CS_fsm[32'd1];
assign ap_CS_fsm_state3 = ap_CS_fsm[32'd2];
assign ap_CS_fsm_state9 = ap_CS_fsm[32'd4];
assign ap_block_pp0_stage0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage0_01001 = (((ap_enable_reg_pp0_iter1 == 1'b1) & (((img1_data_stream_2_V_empty_n == 1'b0) & (exitcond_i_i_i_reg_478 == 1'd0)) | ((img1_data_stream_1_V_empty_n == 1'b0) & (exitcond_i_i_i_reg_478 == 1'd0)) | ((img1_data_stream_0_V_empty_n == 1'b0) & (exitcond_i_i_i_reg_478 == 1'd0)))) | ((ap_enable_reg_pp0_iter4 == 1'b1) & (((img2_data_stream_2_V_full_n == 1'b0) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 == 1'd0)) | ((img2_data_stream_1_V_full_n == 1'b0) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 == 1'd0)) | ((img2_data_stream_0_V_full_n == 1'b0) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 == 1'd0)))));
end
always @ (*) begin
ap_block_pp0_stage0_11001 = (((ap_enable_reg_pp0_iter1 == 1'b1) & (((img1_data_stream_2_V_empty_n == 1'b0) & (exitcond_i_i_i_reg_478 == 1'd0)) | ((img1_data_stream_1_V_empty_n == 1'b0) & (exitcond_i_i_i_reg_478 == 1'd0)) | ((img1_data_stream_0_V_empty_n == 1'b0) & (exitcond_i_i_i_reg_478 == 1'd0)))) | ((ap_enable_reg_pp0_iter4 == 1'b1) & (((img2_data_stream_2_V_full_n == 1'b0) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 == 1'd0)) | ((img2_data_stream_1_V_full_n == 1'b0) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 == 1'd0)) | ((img2_data_stream_0_V_full_n == 1'b0) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 == 1'd0)))));
end
always @ (*) begin
ap_block_pp0_stage0_subdone = (((ap_enable_reg_pp0_iter1 == 1'b1) & (((img1_data_stream_2_V_empty_n == 1'b0) & (exitcond_i_i_i_reg_478 == 1'd0)) | ((img1_data_stream_1_V_empty_n == 1'b0) & (exitcond_i_i_i_reg_478 == 1'd0)) | ((img1_data_stream_0_V_empty_n == 1'b0) & (exitcond_i_i_i_reg_478 == 1'd0)))) | ((ap_enable_reg_pp0_iter4 == 1'b1) & (((img2_data_stream_2_V_full_n == 1'b0) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 == 1'd0)) | ((img2_data_stream_1_V_full_n == 1'b0) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 == 1'd0)) | ((img2_data_stream_0_V_full_n == 1'b0) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 == 1'd0)))));
end
always @ (*) begin
ap_block_state1 = ((sat_empty_n == 1'b0) | (p_cols_assign_cast_loc_empty_n == 1'b0) | (p_rows_assign_cast_loc_empty_n == 1'b0) | (ap_start == 1'b0) | (ap_done_reg == 1'b1));
end
assign ap_block_state4_pp0_stage0_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state5_pp0_stage0_iter1 = (((img1_data_stream_2_V_empty_n == 1'b0) & (exitcond_i_i_i_reg_478 == 1'd0)) | ((img1_data_stream_1_V_empty_n == 1'b0) & (exitcond_i_i_i_reg_478 == 1'd0)) | ((img1_data_stream_0_V_empty_n == 1'b0) & (exitcond_i_i_i_reg_478 == 1'd0)));
end
assign ap_block_state6_pp0_stage0_iter2 = ~(1'b1 == 1'b1);
assign ap_block_state7_pp0_stage0_iter3 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state8_pp0_stage0_iter4 = (((img2_data_stream_2_V_full_n == 1'b0) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 == 1'd0)) | ((img2_data_stream_1_V_full_n == 1'b0) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 == 1'd0)) | ((img2_data_stream_0_V_full_n == 1'b0) & (ap_reg_pp0_iter3_exitcond_i_i_i_reg_478 == 1'd0)));
end
assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
assign exitcond51_i_i_i_fu_327_p2 = ((t_V_cast_i_i_fu_323_p1 == p_rows_assign_cast_lo_reg_406) ? 1'b1 : 1'b0);
assign exitcond_i_i_i_fu_342_p2 = ((t_V_1_cast_i_i_fu_338_p1 == p_cols_assign_cast_lo_reg_411) ? 1'b1 : 1'b0);
assign i_V_fu_332_p2 = (t_V_reg_241 + 11'd1);
assign img2_data_stream_0_V_din = ap_reg_pp0_iter3_tmp_reg_487;
assign img2_data_stream_1_V_din = ap_reg_pp0_iter3_tmp_7_reg_492;
assign img2_data_stream_2_V_din = ((or_cond3_reg_464[0:0] === 1'b1) ? newSel4_fu_386_p3 : newSel5_fu_392_p3);
assign j_V_fu_347_p2 = (t_V_2_reg_252 + 11'd1);
assign lut_s_0_2_address0 = tmp_5_i_i_fu_353_p1;
assign lut_s_0_4_address0 = tmp_5_i_i_fu_353_p1;
assign lut_s_0_6_address0 = tmp_5_i_i_fu_353_p1;
assign lut_s_0_8_address0 = tmp_5_i_i_fu_353_p1;
assign lut_s_1_0_address0 = tmp_5_i_i_fu_353_p1;
assign lut_s_1_2_address0 = tmp_5_i_i_fu_353_p1;
assign lut_s_n0_2_address0 = tmp_5_i_i_fu_353_p1;
assign newSel1_fu_363_p3 = ((sel_tmp8_reg_437[0:0] === 1'b1) ? lut_s_0_4_q0 : lut_s_0_6_q0);
assign newSel2_fu_381_p3 = ((sel_tmp4_reg_426[0:0] === 1'b1) ? d_val_2_6_reg_548 : d_val_2_7_reg_553);
assign newSel3_fu_370_p3 = ((sel_tmp_reg_416[0:0] === 1'b1) ? lut_s_1_2_q0 : ap_reg_pp0_iter2_tmp_9_reg_497);
assign newSel4_fu_386_p3 = ((or_cond_reg_454[0:0] === 1'b1) ? newSel_fu_376_p3 : newSel1_reg_558);
assign newSel5_fu_392_p3 = ((or_cond2_reg_459[0:0] === 1'b1) ? newSel2_fu_381_p3 : newSel3_reg_563);
assign newSel_fu_376_p3 = ((sel_tmp3_reg_448[0:0] === 1'b1) ? d_val_2_2_reg_538 : d_val_2_3_reg_543);
assign or_cond1_fu_309_p2 = (sel_tmp8_reg_437 | sel_tmp6_reg_432);
assign or_cond2_fu_313_p2 = (sel_tmp4_reg_426 | sel_tmp2_reg_421);
assign or_cond3_fu_317_p2 = (or_cond_fu_305_p2 | or_cond1_fu_309_p2);
assign or_cond_fu_305_p2 = (sel_tmp3_reg_448 | sel_tmp1_reg_443);
assign sel_tmp1_fu_293_p2 = ((sat_dout == 8'd2) ? 1'b1 : 1'b0);
assign sel_tmp2_fu_269_p2 = ((sat_dout == 8'd6) ? 1'b1 : 1'b0);
assign sel_tmp3_fu_299_p2 = ((sat_dout == 8'd1) ? 1'b1 : 1'b0);
assign sel_tmp4_fu_275_p2 = ((sat_dout == 8'd5) ? 1'b1 : 1'b0);
assign sel_tmp6_fu_281_p2 = ((sat_dout == 8'd4) ? 1'b1 : 1'b0);
assign sel_tmp8_fu_287_p2 = ((sat_dout == 8'd3) ? 1'b1 : 1'b0);
assign sel_tmp_fu_263_p2 = ((sat_dout == 8'd7) ? 1'b1 : 1'b0);
assign t_V_1_cast_i_i_fu_338_p1 = t_V_2_reg_252;
assign t_V_cast_i_i_fu_323_p1 = t_V_reg_241;
assign tmp_5_i_i_fu_353_p1 = tmp_9_reg_497;
endmodule //Loop_loop_height_pro
|
`include "scmem.vh"
`include "DC_define.v"
`include "logfunc.h"
module DC_1_tagbank #(parameter Width = 15, Size =256, Forward=0)
//tag 10+counter 2 bits [11:10]+states 3 bits[14:12] =>15
(
input clk
,input reset
,input req_valid
//request byte is also important ld 8 byte or store 512assign set_index=req_data[10:6];
,input ack_retry
,input write_1_tagbank //if write enable then no read and outdata=0
,input [7:0] req_pos_tag
,input [Width-1:0] req_data
,output req_retry
,output ack_valid
,output [14:0] ack_data
/////////////////////////////////////////////////////////////
//5bit loadReq
,input coretodc_ld_valid
,output coretodc_ld_retry
,input [4:0] coretodc_ld_req
// 7 bit store Req,atomic,checkpoint
,input coretodc_std_valid
,output coretodc_std_retry
,input [6:0] coretodc_std
//5 bit L2 -> DC ACK
,input l2tol1_snack_valid
// ,output l2tol1_snack_retry
,input [4:0] l2tol1_snack
// 3 bit Displacement
,output l1tol2_disp_valid//
//,input l1tol2_disp_retry//
,output [2:0] l1tol2_disp//
,output[2:0] state_cache
);
logic[14:0] ack_data_from_ram;
logic write = write_1_tagbank;
logic [14:0] req_data_1_tagbank; //15 bits=10+2+3
assign req_data_1_tagbank= req_data;
ram_1port_fast
#(.Width(Width), .Size(Size))
tagbank (
.clk (clk)
,.reset (reset)
,.req_valid (req_valid)
,.req_we (write)//we=0 for read
,.req_data (req_data_1_tagbank)//search for Tag only while reading
,.ack_retry (ack_retry)
,.req_pos (req_pos_tag)//search the set index position
,.req_retry (req_retry)
,.ack_valid (ack_valid)
,.ack_data (ack_data_from_ram)
);
logic [2:0] state_bits;
assign state_bits=ack_data_from_ram[14:12];
logic [2:0] next_state_bits;
assign ack_data=ack_data_from_ram;
always@(coretodc_ld_valid or coretodc_ld_req)begin
if ($bits(coretodc_ld_req)==5) begin
coretodc_ld_retry=0;
case(coretodc_ld_req)//look***********************************************
//Loads Req that changes cache state
`CORE_LOP_L32U:begin if (state_bits==`US) next_state_bits=`US;
else if (state_bits==`UM) next_state_bits=`UM;
else if (state_bits==`S) next_state_bits=`S;
else next_state_bits = state_bits;
end
default:next_state_bits = state_bits;
endcase
write =1'b1;//write enable
req_data_1_tagbank[14:12]=next_state_bits;
end //if end
state_cache=next_state_bits;
end //always
always@( l2tol1_snack or l2tol1_snack_valid )begin
if ($bits(l2tol1_snack)==5) begin
case(l2tol1_snack)//look***********************************************
//Loads Req that changes cache state
`SC_SCMD_ACK_S :begin if (state_bits==`US) next_state_bits=`US;
else if (state_bits==`UM) next_state_bits=`UM;
else if (state_bits==`M) begin next_state_bits=`S; l1tol2_disp=`SC_DCMD_WS;l1tol2_disp_valid=1;end
else if (state_bits==`E) next_state_bits=`S;
else if (state_bits==`S) next_state_bits=`S;
else next_state_bits = state_bits;
end
`SC_SCMD_ACK_E :begin if (state_bits==`US) next_state_bits=`US;
else if (state_bits==`UM) next_state_bits=`UM;
else if (state_bits==`M) begin next_state_bits=`US; l1tol2_disp=`SC_DCMD_WS;end
else if (state_bits==`E) next_state_bits=`US;
else if (state_bits==`S) next_state_bits=`US;
else next_state_bits = state_bits;
end
`SC_SCMD_ACK_M :begin if (state_bits==`I) next_state_bits=`E;
else if (state_bits==`I) next_state_bits=`S;
else next_state_bits = state_bits;
end
default:next_state_bits = state_bits;
endcase
write ='b1;//write enable
req_data_1_tagbank[14:12]=next_state_bits;
end //if end
state_cache=next_state_bits;
end //always
always@(coretodc_std)begin
if ($bits(coretodc_std)==7 && coretodc_std_valid) begin
coretodc_std_retry=0;
case(coretodc_std)//look***********************************************
//Loads Req that changes cache state
`CORE_MOP_S32: begin if (state_bits==`US) next_state_bits=`UM;
else if (state_bits==`S) next_state_bits=`UM;
else if (state_bits==`S) next_state_bits=`M;
else next_state_bits = `M;
end
default:next_state_bits = state_bits;
endcase
end //if
state_cache=next_state_bits;
end //always
//logic [`CACHE_STATE-1:0] cache_state;
// assign cache_state=ack_data[21:23];
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:57:50 08/25/2009
// Design Name:
// Module Name: mcu_cmd
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "config.vh"
module mcu_cmd(
input clk,
input cmd_ready,
input param_ready,
input [7:0] cmd_data,
input [7:0] param_data,
output [3:0] mcu_mapper,
output reg mcu_rrq = 0,
output mcu_write,
output reg mcu_wrq = 0,
input mcu_rq_rdy,
output [7:0] mcu_data_out,
input [7:0] mcu_data_in,
output [7:0] spi_data_out,
input [31:0] spi_byte_cnt,
input [2:0] spi_bit_cnt,
output [23:0] addr_out,
output [23:0] saveram_mask_out,
output [23:0] rom_mask_out,
// SD "DMA" extension
output SD_DMA_EN,
input SD_DMA_STATUS,
input SD_DMA_NEXTADDR,
input [7:0] SD_DMA_SRAM_DATA,
input SD_DMA_SRAM_WE,
output [1:0] SD_DMA_TGT,
output SD_DMA_PARTIAL,
output [10:0] SD_DMA_PARTIAL_START,
output [10:0] SD_DMA_PARTIAL_END,
output reg SD_DMA_START_MID_BLOCK,
output reg SD_DMA_END_MID_BLOCK,
// DAC
output [10:0] dac_addr_out,
input DAC_STATUS,
output reg dac_play_out = 0,
output reg dac_reset_out = 0,
output reg [2:0] dac_vol_select_out = 3'b000,
output reg dac_palmode_out = 0,
output reg [8:0] dac_ptr_out = 0,
// MSU data
output [13:0] msu_addr_out,
input [7:0] MSU_STATUS,
output [5:0] msu_status_reset_out,
output [5:0] msu_status_set_out,
output msu_status_reset_we,
input [31:0] msu_addressrq,
input [15:0] msu_trackrq,
input [7:0] msu_volumerq,
output [13:0] msu_ptr_out,
output msu_reset_out,
input [55:0] rtc_data_in,
output [55:0] rtc_data_out,
output rtc_pgm_we,
output rtc_pgm_rd,
// REG (generic)
// data inputs
input [7:0] sgb_config_data_in,
// data output
output [7:0] reg_group_out,
output [7:0] reg_index_out,
output [7:0] reg_value_out,
output [7:0] reg_invmask_out,
output reg_we_out,
output [7:0] reg_read_out,
// feature enable
output reg [15:0] featurebits_out,
output reg region_out,
// SNES sync/clk
input snes_sysclk,
// snes cmd interface
input [7:0] snescmd_data_in,
output reg [7:0] snescmd_data_out,
output reg [8:0] snescmd_addr_out,
output reg snescmd_we_out,
// cheat configuration
output reg [7:0] cheat_pgm_idx_out,
output reg [31:0] cheat_pgm_data_out,
output reg cheat_pgm_we_out,
// DSP core features
output reg [15:0] dsp_feat_out = 16'h0000,
// SGB core features
output reg [15:0] sgb_feat_out = 16'h0000
);
initial begin
region_out = 0;
SD_DMA_START_MID_BLOCK = 0;
SD_DMA_END_MID_BLOCK = 0;
end
wire [31:0] snes_sysclk_freq;
clk_test snes_clk_test (
.clk(clk),
.sysclk(snes_sysclk),
.snes_sysclk_freq(snes_sysclk_freq)
);
reg [3:0] MAPPER_BUF;
reg [23:0] ADDR_OUT_BUF;
reg [10:0] DAC_ADDR_OUT_BUF;
reg [7:0] DAC_VOL_OUT_BUF;
reg [13:0] MSU_ADDR_OUT_BUF;
reg [13:0] MSU_PTR_OUT_BUF;
reg [5:0] msu_status_set_out_buf;
reg [5:0] msu_status_reset_out_buf;
reg msu_status_reset_we_buf = 0;
reg MSU_RESET_OUT_BUF;
reg [7:0] group_out_buf; initial group_out_buf = 8'hFF;
reg [7:0] index_out_buf; initial index_out_buf = 8'hFF;
reg [7:0] value_out_buf; initial value_out_buf = 8'hFF;
reg [7:0] invmask_out_buf; initial invmask_out_buf = 8'hFF;
reg [7:0] group_read_buf; initial group_read_buf = 8'hFF;
reg [7:0] index_read_buf; initial index_read_buf = 8'hFF;
reg [7:0] temp_read_buf; initial temp_read_buf = 8'hFF;
reg reg_we_buf; initial reg_we_buf = 0;
reg [55:0] rtc_data_in_buf;
reg [55:0] rtc_data_out_buf;
reg rtc_pgm_we_buf;
reg rtc_pgm_rd_buf;
reg [31:0] SNES_SYSCLK_FREQ_BUF;
reg [7:0] MCU_DATA_OUT_BUF;
reg [7:0] MCU_DATA_IN_BUF;
reg [2:0] mcu_nextaddr_buf;
wire mcu_nextaddr;
reg [7:0] feat_tmp;
reg [7:0] sgb_feat_tmp;
reg DAC_STATUSr;
reg SD_DMA_STATUSr;
reg [7:0] MSU_STATUSr;
always @(posedge clk) begin
DAC_STATUSr <= DAC_STATUS;
SD_DMA_STATUSr <= SD_DMA_STATUS;
MSU_STATUSr <= MSU_STATUS;
end
reg SD_DMA_PARTIALr;
assign SD_DMA_PARTIAL = SD_DMA_PARTIALr;
reg SD_DMA_ENr;
assign SD_DMA_EN = SD_DMA_ENr;
reg [1:0] SD_DMA_TGTr;
assign SD_DMA_TGT = SD_DMA_TGTr;
reg [10:0] SD_DMA_PARTIAL_STARTr;
reg [10:0] SD_DMA_PARTIAL_ENDr;
assign SD_DMA_PARTIAL_START = SD_DMA_PARTIAL_STARTr;
assign SD_DMA_PARTIAL_END = SD_DMA_PARTIAL_ENDr;
reg [23:0] SAVERAM_MASK;
reg [23:0] ROM_MASK;
assign spi_data_out = MCU_DATA_IN_BUF;
initial begin
ADDR_OUT_BUF = 0;
DAC_ADDR_OUT_BUF = 0;
MSU_ADDR_OUT_BUF = 0;
SD_DMA_ENr = 0;
MAPPER_BUF = 0;
SD_DMA_PARTIALr = 0;
end
// command interpretation
always @(posedge clk) begin
snescmd_we_out <= 1'b0;
cheat_pgm_we_out <= 1'b0;
dac_reset_out <= 1'b0;
MSU_RESET_OUT_BUF <= 1'b0;
if (cmd_ready) begin
case (cmd_data[7:4])
4'h3: // select mapper
MAPPER_BUF <= cmd_data[3:0];
4'h4: begin// SD DMA
SD_DMA_ENr <= 1;
SD_DMA_TGTr <= cmd_data[1:0];
SD_DMA_PARTIALr <= cmd_data[2];
end
4'h8: SD_DMA_TGTr <= 2'b00;
4'h9: SD_DMA_TGTr <= 2'b00; // cmd_data[1:0]; // not implemented
// 4'hE:
// select memory unit
endcase
end else if (param_ready) begin
casex (cmd_data[7:0])
8'h1x:
case (spi_byte_cnt)
32'h2:
ROM_MASK[23:16] <= param_data;
32'h3:
ROM_MASK[15:8] <= param_data;
32'h4:
ROM_MASK[7:0] <= param_data;
endcase
8'h2x:
case (spi_byte_cnt)
32'h2:
SAVERAM_MASK[23:16] <= param_data;
32'h3:
SAVERAM_MASK[15:8] <= param_data;
32'h4:
SAVERAM_MASK[7:0] <= param_data;
endcase
8'h4x:
SD_DMA_ENr <= 1'b0;
8'h6x:
case (spi_byte_cnt)
32'h2: begin
SD_DMA_START_MID_BLOCK <= param_data[7];
SD_DMA_PARTIAL_STARTr[10:9] <= param_data[1:0];
end
32'h3:
SD_DMA_PARTIAL_STARTr[8:0] <= {param_data, 1'b0};
32'h4: begin
SD_DMA_END_MID_BLOCK <= param_data[7];
SD_DMA_PARTIAL_ENDr[10:9] <= param_data[1:0];
end
32'h5:
SD_DMA_PARTIAL_ENDr[8:0] <= {param_data, 1'b0};
endcase
8'h9x:
MCU_DATA_OUT_BUF <= param_data;
8'hd0:
case (spi_byte_cnt)
32'h2:
snescmd_addr_out[7:0] <= param_data;
32'h3:
snescmd_addr_out[8] <= param_data[0];
endcase
8'hd1:
snescmd_addr_out <= snescmd_addr_out + 1;
8'hd2: begin
case (spi_byte_cnt)
32'h2:
snescmd_we_out <= 1'b1;
32'h3:
snescmd_addr_out <= snescmd_addr_out + 1;
endcase
snescmd_data_out <= param_data;
end
8'hd3: begin
case (spi_byte_cnt)
32'h2:
cheat_pgm_idx_out <= param_data[2:0];
32'h3:
cheat_pgm_data_out[31:24] <= param_data;
32'h4:
cheat_pgm_data_out[23:16] <= param_data;
32'h5:
cheat_pgm_data_out[15:8] <= param_data;
32'h6: begin
cheat_pgm_data_out[7:0] <= param_data;
cheat_pgm_we_out <= 1'b1;
end
endcase
end
8'he0:
case (spi_byte_cnt)
32'h2: begin
msu_status_set_out_buf <= param_data[5:0];
end
32'h3: begin
msu_status_reset_out_buf <= param_data[5:0];
msu_status_reset_we_buf <= 1'b1;
end
32'h4:
msu_status_reset_we_buf <= 1'b0;
endcase
`ifdef MSU_AUDIO
8'he1: // pause DAC
dac_play_out <= 1'b0;
8'he2: // resume DAC
dac_play_out <= 1'b1;
8'he3: // reset DAC (set DAC playback address = 0)
case (spi_byte_cnt)
32'h2:
dac_ptr_out[8] <= param_data[0];
32'h3: begin
dac_ptr_out[7:0] <= param_data;
dac_reset_out <= 1'b1; // reset by default value, see above
end
endcase
`endif
`ifdef MSU_DATA
8'he4: // reset MSU read buffer pointer
case (spi_byte_cnt)
32'h2: begin
MSU_PTR_OUT_BUF[13:8] <= param_data[5:0];
MSU_PTR_OUT_BUF[7:0] <= 8'h0;
end
32'h3: begin
MSU_PTR_OUT_BUF[7:0] <= param_data;
MSU_RESET_OUT_BUF <= 1'b1;
end
endcase
`endif
8'he5:
case (spi_byte_cnt)
32'h2:
rtc_data_out_buf[55:48] <= param_data;
32'h3:
rtc_data_out_buf[47:40] <= param_data;
32'h4:
rtc_data_out_buf[39:32] <= param_data;
32'h5:
rtc_data_out_buf[31:24] <= param_data;
32'h6:
rtc_data_out_buf[23:16] <= param_data;
32'h7:
rtc_data_out_buf[15:8] <= param_data;
32'h8: begin
rtc_data_out_buf[7:0] <= param_data;
rtc_pgm_we_buf <= 1'b1;
end
32'h9:
rtc_pgm_we_buf <= 1'b0;
endcase
`ifdef MSU_AUDIO
8'hec:
begin // set DAC properties
dac_vol_select_out <= param_data[2:0];
dac_palmode_out <= param_data[7];
end
`endif
8'hed:
case (spi_byte_cnt)
32'h2: feat_tmp <= param_data;
32'h3: featurebits_out <= {feat_tmp, param_data};
endcase
8'hee:
region_out <= param_data[0];
8'hef:
case (spi_byte_cnt)
32'h2: sgb_feat_tmp <= param_data[7:0];
32'h3: begin
sgb_feat_out <= {sgb_feat_tmp, param_data[7:0]};
end
endcase
`ifdef SGB_DEBUG
8'hfa: // handles all group, index, value, invmask writes. unit is responsible for decoding group for match
case (spi_byte_cnt)
32'h2: begin
group_out_buf <= param_data;
end
32'h3: begin
index_out_buf <= param_data;
end
32'h4: begin
value_out_buf <= param_data;
end
32'h5: begin
invmask_out_buf <= param_data;
reg_we_buf <= 1;
end
32'h6: begin
reg_we_buf <= 0;
group_out_buf <= 8'hFF;
index_out_buf <= 8'hFF;
value_out_buf <= 8'hFF;
invmask_out_buf <= 8'hFF;
end
endcase
`endif
endcase
end
end
always @(posedge clk) begin
if(param_ready && cmd_data[7:4] == 4'h0) begin
case (cmd_data[1:0])
`ifdef MSU_AUDIO
2'b01: begin
case (spi_byte_cnt)
32'h2: begin
DAC_ADDR_OUT_BUF[10:8] <= param_data[2:0];
DAC_ADDR_OUT_BUF[7:0] <= 8'b0;
end
32'h3:
DAC_ADDR_OUT_BUF[7:0] <= param_data;
endcase
end
`endif
`ifdef MSU_DATA
2'b10: begin
case (spi_byte_cnt)
32'h2: begin
MSU_ADDR_OUT_BUF[13:8] <= param_data[5:0];
MSU_ADDR_OUT_BUF[7:0] <= 8'b0;
end
32'h3: begin
MSU_ADDR_OUT_BUF[7:0] <= param_data;
end
endcase
end
`endif
default:
case (spi_byte_cnt)
32'h2: begin
ADDR_OUT_BUF[23:16] <= param_data;
ADDR_OUT_BUF[15:0] <= 16'b0;
end
32'h3:
ADDR_OUT_BUF[15:8] <= param_data;
32'h4:
ADDR_OUT_BUF[7:0] <= param_data;
endcase
endcase
end
else if (SD_DMA_NEXTADDR | (mcu_nextaddr & (cmd_data[7:5] == 3'h4)
&& (cmd_data[3])
&& (spi_byte_cnt >= (32'h1+cmd_data[4])))
) begin
case (SD_DMA_TGTr)
2'b00: ADDR_OUT_BUF <= ADDR_OUT_BUF + 1;
`ifdef MSU_AUDIO
2'b01: DAC_ADDR_OUT_BUF <= DAC_ADDR_OUT_BUF + 1;
`endif
`ifdef MSU_DATA
2'b10: MSU_ADDR_OUT_BUF <= MSU_ADDR_OUT_BUF + 1;
`endif
endcase
end
end
// value fetch during last SPI bit
always @(posedge clk) begin
if (cmd_data[7:4] == 4'h8 && mcu_nextaddr)
MCU_DATA_IN_BUF <= mcu_data_in;
else if (cmd_ready | param_ready /* bit_cnt == 7 */) begin
if (cmd_data[7:4] == 4'hA)
MCU_DATA_IN_BUF <= snescmd_data_in;
if (cmd_data[7:0] == 8'hE6)
case (spi_byte_cnt)
32'h1: begin
rtc_data_in_buf <= rtc_data_in;
rtc_pgm_rd_buf <= 1;
end
32'h2: begin
MCU_DATA_IN_BUF <= rtc_data_in_buf[55:48];
rtc_pgm_rd_buf <= 0;
end
32'h3:
MCU_DATA_IN_BUF <= rtc_data_in_buf[47:40];
32'h4:
MCU_DATA_IN_BUF <= rtc_data_in_buf[39:32];
32'h5:
MCU_DATA_IN_BUF <= rtc_data_in_buf[31:24];
32'h6:
MCU_DATA_IN_BUF <= rtc_data_in_buf[23:16];
32'h7:
MCU_DATA_IN_BUF <= rtc_data_in_buf[15:8];
32'h8:
MCU_DATA_IN_BUF <= rtc_data_in_buf[7:0];
endcase
else if (cmd_data[7:0] == 8'hF0)
MCU_DATA_IN_BUF <= 8'hA5;
else if (cmd_data[7:0] == 8'hF1)
case (spi_byte_cnt[0])
1'b1: // buffer status (1st byte)
MCU_DATA_IN_BUF <= {SD_DMA_STATUSr, DAC_STATUSr, MSU_STATUSr[7], 5'b0};
1'b0: // control status (2nd byte)
MCU_DATA_IN_BUF <= {1'b0, MSU_STATUSr[6:0]};
endcase
else if (cmd_data[7:0] == 8'hF2)
case (spi_byte_cnt)
32'h1:
MCU_DATA_IN_BUF <= msu_addressrq[31:24];
32'h2:
MCU_DATA_IN_BUF <= msu_addressrq[23:16];
32'h3:
MCU_DATA_IN_BUF <= msu_addressrq[15:8];
32'h4:
MCU_DATA_IN_BUF <= msu_addressrq[7:0];
endcase
else if (cmd_data[7:0] == 8'hF3)
case (spi_byte_cnt)
32'h1:
MCU_DATA_IN_BUF <= msu_trackrq[15:8];
32'h2:
MCU_DATA_IN_BUF <= msu_trackrq[7:0];
endcase
else if (cmd_data[7:0] == 8'hF4)
MCU_DATA_IN_BUF <= msu_volumerq;
else if (cmd_data[7:0] == 8'hFE)
case (spi_byte_cnt)
32'h1:
SNES_SYSCLK_FREQ_BUF <= snes_sysclk_freq;
32'h2:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[31:24];
32'h3:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[23:16];
32'h4:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[15:8];
32'h5:
MCU_DATA_IN_BUF <= SNES_SYSCLK_FREQ_BUF[7:0];
endcase
`ifdef SGB_DEBUG
else if (cmd_data[7:0] == 8'hF9)
case (spi_byte_cnt)
32'h2: begin
group_read_buf <= param_data;
end
32'h3: begin
index_read_buf <= param_data;
end
32'h4: begin
if (group_read_buf == 8'h03) MCU_DATA_IN_BUF <= sgb_config_data_in;
else MCU_DATA_IN_BUF <= 0;
end
endcase
`endif
else if (cmd_data[7:0] == 8'hFF)
MCU_DATA_IN_BUF <= param_data;
else if (cmd_data[7:0] == 8'hD1)
MCU_DATA_IN_BUF <= snescmd_data_in;
end
end
// nextaddr pulse generation
always @(posedge clk) begin
mcu_nextaddr_buf <= {mcu_nextaddr_buf[1:0], mcu_rq_rdy};
end
always @(posedge clk) begin
mcu_rrq <= 1'b0;
if((param_ready | cmd_ready) && cmd_data[7:4] == 4'h8) begin
mcu_rrq <= 1'b1;
end
end
always @(posedge clk) begin
mcu_wrq <= 1'b0;
if(param_ready && cmd_data[7:4] == 4'h9) begin
mcu_wrq <= 1'b1;
end
end
// trigger for nextaddr
assign mcu_nextaddr = mcu_nextaddr_buf == 2'b01;
assign mcu_write = SD_DMA_STATUS
?(SD_DMA_TGTr == 2'b00
? SD_DMA_SRAM_WE
: 1'b1
)
: 1'b1;
assign addr_out = ADDR_OUT_BUF;
assign dac_addr_out = DAC_ADDR_OUT_BUF;
assign msu_addr_out = MSU_ADDR_OUT_BUF;
assign msu_status_reset_we = msu_status_reset_we_buf;
assign msu_status_reset_out = msu_status_reset_out_buf;
assign msu_status_set_out = msu_status_set_out_buf;
assign msu_reset_out = MSU_RESET_OUT_BUF;
assign msu_ptr_out = MSU_PTR_OUT_BUF;
//assign bsx_regs_reset_we = bsx_regs_reset_we_buf;
//assign bsx_regs_reset_out = bsx_regs_reset_out_buf;
//assign bsx_regs_set_out = bsx_regs_set_out_buf;
//
assign rtc_data_out = rtc_data_out_buf;
assign rtc_pgm_we = rtc_pgm_we_buf;
assign rtc_pgm_rd = rtc_pgm_rd_buf;
//
//assign srtc_reset = srtc_reset_buf;
assign mcu_data_out = SD_DMA_STATUS ? SD_DMA_SRAM_DATA : MCU_DATA_OUT_BUF;
assign mcu_mapper = MAPPER_BUF;
assign rom_mask_out = ROM_MASK;
assign saveram_mask_out = SAVERAM_MASK;
assign reg_group_out = group_out_buf;
assign reg_index_out = index_out_buf;
assign reg_value_out = value_out_buf;
assign reg_invmask_out = invmask_out_buf;
assign reg_we_out = reg_we_buf;
assign reg_read_out = index_read_buf;
assign DBG_mcu_nextaddr = mcu_nextaddr;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFLP_BEHAVIORAL_V
`define SKY130_FD_SC_LP__BUFLP_BEHAVIORAL_V
/**
* buflp: Buffer, Low Power.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__buflp (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFLP_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR3_TB_V
`define SKY130_FD_SC_LS__NOR3_TB_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nor3.v"
module top();
// Inputs are registered
reg A;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A = 1'bx;
end
sky130_fd_sc_ls__nor3 dut (.A(A), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR3_TB_V
|
///////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE rev.B2 Wishbone Master model ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/mem_ctrl ////
//// ////
///////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
///////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: wb_master_model.v,v 1.4 2004-02-28 15:40:42 rherveille Exp $
//
// $Date: 2004-02-28 15:40:42 $
// $Revision: 1.4 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
//
`include "timescale.v"
module wb_master_model(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);
parameter dwidth = 32;
parameter awidth = 32;
input clk, rst;
output [awidth -1:0] adr;
input [dwidth -1:0] din;
output [dwidth -1:0] dout;
output cyc, stb;
output we;
output [dwidth/8 -1:0] sel;
input ack, err, rty;
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
reg [awidth -1:0] adr;
reg [dwidth -1:0] dout;
reg cyc, stb;
reg we;
reg [dwidth/8 -1:0] sel;
reg [dwidth -1:0] q;
////////////////////////////////////////////////////////////////////
//
// Memory Logic
//
initial
begin
//adr = 32'hxxxx_xxxx;
//adr = 0;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
cyc = 1'b0;
stb = 1'bx;
we = 1'hx;
sel = {dwidth/8{1'bx}};
#1;
$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
end
////////////////////////////////////////////////////////////////////
//
// Wishbone write cycle
//
task wb_write;
input delay;
integer delay;
input [awidth -1:0] a;
input [dwidth -1:0] d;
begin
// wait initial delay
repeat(delay) @(posedge clk);
// assert wishbone signal
#1;
adr = a;
dout = d;
cyc = 1'b1;
stb = 1'b1;
we = 1'b1;
sel = {dwidth/8{1'b1}};
@(posedge clk);
// wait for acknowledge from slave
while(~ack) @(posedge clk);
// negate wishbone signals
#1;
cyc = 1'b0;
stb = 1'bx;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
we = 1'hx;
sel = {dwidth/8{1'bx}};
end
endtask
////////////////////////////////////////////////////////////////////
//
// Wishbone read cycle
//
task wb_read;
input delay;
integer delay;
input [awidth -1:0] a;
output [dwidth -1:0] d;
begin
// wait initial delay
repeat(delay) @(posedge clk);
// assert wishbone signals
#1;
adr = a;
dout = {dwidth{1'bx}};
cyc = 1'b1;
stb = 1'b1;
we = 1'b0;
sel = {dwidth/8{1'b1}};
@(posedge clk);
// wait for acknowledge from slave
while(~ack) @(posedge clk);
// negate wishbone signals
#1;
cyc = 1'b0;
stb = 1'bx;
adr = {awidth{1'bx}};
dout = {dwidth{1'bx}};
we = 1'hx;
sel = {dwidth/8{1'bx}};
d = din;
end
endtask
////////////////////////////////////////////////////////////////////
//
// Wishbone compare cycle (read data from location and compare with expected data)
//
task wb_cmp;
input delay;
integer delay;
input [awidth -1:0] a;
input [dwidth -1:0] d_exp;
begin
wb_read (delay, a, q);
if (d_exp !== q)
$display("Data compare error. Received %h, expected %h at time %t", q, d_exp, $time);
end
endtask
endmodule
|
// finalproject.v
// Generated using ACDS version 14.1 186 at 2015.04.23.00:32:27
`timescale 1 ps / 1 ps
module finalproject (
input wire clk_clk, // clk.clk
output wire [7:0] keycode_export, // keycode.export
input wire reset_reset_n, // reset.reset_n
output wire sdram_out_clk_clk, // sdram_out_clk.clk
output wire [12:0] sdram_wire_addr, // sdram_wire.addr
output wire [1:0] sdram_wire_ba, // .ba
output wire sdram_wire_cas_n, // .cas_n
output wire sdram_wire_cke, // .cke
output wire sdram_wire_cs_n, // .cs_n
inout wire [31:0] sdram_wire_dq, // .dq
output wire [3:0] sdram_wire_dqm, // .dqm
output wire sdram_wire_ras_n, // .ras_n
output wire sdram_wire_we_n, // .we_n
inout wire [15:0] usb_DATA, // usb.DATA
output wire [1:0] usb_ADDR, // .ADDR
output wire usb_RD_N, // .RD_N
output wire usb_WR_N, // .WR_N
output wire usb_CS_N, // .CS_N
output wire usb_RST_N, // .RST_N
input wire usb_INT, // .INT
output wire usb_out_clk_clk // usb_out_clk.clk
);
wire [31:0] cpu_data_master_readdata; // mm_interconnect_0:cpu_data_master_readdata -> cpu:d_readdata
wire cpu_data_master_waitrequest; // mm_interconnect_0:cpu_data_master_waitrequest -> cpu:d_waitrequest
wire cpu_data_master_debugaccess; // cpu:jtag_debug_module_debugaccess_to_roms -> mm_interconnect_0:cpu_data_master_debugaccess
wire [28:0] cpu_data_master_address; // cpu:d_address -> mm_interconnect_0:cpu_data_master_address
wire [3:0] cpu_data_master_byteenable; // cpu:d_byteenable -> mm_interconnect_0:cpu_data_master_byteenable
wire cpu_data_master_read; // cpu:d_read -> mm_interconnect_0:cpu_data_master_read
wire cpu_data_master_write; // cpu:d_write -> mm_interconnect_0:cpu_data_master_write
wire [31:0] cpu_data_master_writedata; // cpu:d_writedata -> mm_interconnect_0:cpu_data_master_writedata
wire [31:0] cpu_instruction_master_readdata; // mm_interconnect_0:cpu_instruction_master_readdata -> cpu:i_readdata
wire cpu_instruction_master_waitrequest; // mm_interconnect_0:cpu_instruction_master_waitrequest -> cpu:i_waitrequest
wire [28:0] cpu_instruction_master_address; // cpu:i_address -> mm_interconnect_0:cpu_instruction_master_address
wire cpu_instruction_master_read; // cpu:i_read -> mm_interconnect_0:cpu_instruction_master_read
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_chipselect -> jtag_uart:av_chipselect
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata; // jtag_uart:av_readdata -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_readdata
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest; // jtag_uart:av_waitrequest -> mm_interconnect_0:jtag_uart_avalon_jtag_slave_waitrequest
wire [0:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_address; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_address -> jtag_uart:av_address
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_read; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_read -> jtag_uart:av_read_n
wire mm_interconnect_0_jtag_uart_avalon_jtag_slave_write; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_write -> jtag_uart:av_write_n
wire [31:0] mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata; // mm_interconnect_0:jtag_uart_avalon_jtag_slave_writedata -> jtag_uart:av_writedata
wire [31:0] mm_interconnect_0_cpu_jtag_debug_module_readdata; // cpu:jtag_debug_module_readdata -> mm_interconnect_0:cpu_jtag_debug_module_readdata
wire mm_interconnect_0_cpu_jtag_debug_module_waitrequest; // cpu:jtag_debug_module_waitrequest -> mm_interconnect_0:cpu_jtag_debug_module_waitrequest
wire mm_interconnect_0_cpu_jtag_debug_module_debugaccess; // mm_interconnect_0:cpu_jtag_debug_module_debugaccess -> cpu:jtag_debug_module_debugaccess
wire [8:0] mm_interconnect_0_cpu_jtag_debug_module_address; // mm_interconnect_0:cpu_jtag_debug_module_address -> cpu:jtag_debug_module_address
wire mm_interconnect_0_cpu_jtag_debug_module_read; // mm_interconnect_0:cpu_jtag_debug_module_read -> cpu:jtag_debug_module_read
wire [3:0] mm_interconnect_0_cpu_jtag_debug_module_byteenable; // mm_interconnect_0:cpu_jtag_debug_module_byteenable -> cpu:jtag_debug_module_byteenable
wire mm_interconnect_0_cpu_jtag_debug_module_write; // mm_interconnect_0:cpu_jtag_debug_module_write -> cpu:jtag_debug_module_write
wire [31:0] mm_interconnect_0_cpu_jtag_debug_module_writedata; // mm_interconnect_0:cpu_jtag_debug_module_writedata -> cpu:jtag_debug_module_writedata
wire [31:0] mm_interconnect_0_clocks_pll_slave_readdata; // clocks:readdata -> mm_interconnect_0:clocks_pll_slave_readdata
wire [1:0] mm_interconnect_0_clocks_pll_slave_address; // mm_interconnect_0:clocks_pll_slave_address -> clocks:address
wire mm_interconnect_0_clocks_pll_slave_read; // mm_interconnect_0:clocks_pll_slave_read -> clocks:read
wire mm_interconnect_0_clocks_pll_slave_write; // mm_interconnect_0:clocks_pll_slave_write -> clocks:write
wire [31:0] mm_interconnect_0_clocks_pll_slave_writedata; // mm_interconnect_0:clocks_pll_slave_writedata -> clocks:writedata
wire [31:0] mm_interconnect_0_clock_crossing_io_s0_readdata; // clock_crossing_io:s0_readdata -> mm_interconnect_0:clock_crossing_io_s0_readdata
wire mm_interconnect_0_clock_crossing_io_s0_waitrequest; // clock_crossing_io:s0_waitrequest -> mm_interconnect_0:clock_crossing_io_s0_waitrequest
wire mm_interconnect_0_clock_crossing_io_s0_debugaccess; // mm_interconnect_0:clock_crossing_io_s0_debugaccess -> clock_crossing_io:s0_debugaccess
wire [21:0] mm_interconnect_0_clock_crossing_io_s0_address; // mm_interconnect_0:clock_crossing_io_s0_address -> clock_crossing_io:s0_address
wire mm_interconnect_0_clock_crossing_io_s0_read; // mm_interconnect_0:clock_crossing_io_s0_read -> clock_crossing_io:s0_read
wire [3:0] mm_interconnect_0_clock_crossing_io_s0_byteenable; // mm_interconnect_0:clock_crossing_io_s0_byteenable -> clock_crossing_io:s0_byteenable
wire mm_interconnect_0_clock_crossing_io_s0_readdatavalid; // clock_crossing_io:s0_readdatavalid -> mm_interconnect_0:clock_crossing_io_s0_readdatavalid
wire mm_interconnect_0_clock_crossing_io_s0_write; // mm_interconnect_0:clock_crossing_io_s0_write -> clock_crossing_io:s0_write
wire [31:0] mm_interconnect_0_clock_crossing_io_s0_writedata; // mm_interconnect_0:clock_crossing_io_s0_writedata -> clock_crossing_io:s0_writedata
wire [0:0] mm_interconnect_0_clock_crossing_io_s0_burstcount; // mm_interconnect_0:clock_crossing_io_s0_burstcount -> clock_crossing_io:s0_burstcount
wire mm_interconnect_0_keycode_s1_chipselect; // mm_interconnect_0:keycode_s1_chipselect -> keycode:chipselect
wire [31:0] mm_interconnect_0_keycode_s1_readdata; // keycode:readdata -> mm_interconnect_0:keycode_s1_readdata
wire [1:0] mm_interconnect_0_keycode_s1_address; // mm_interconnect_0:keycode_s1_address -> keycode:address
wire mm_interconnect_0_keycode_s1_write; // mm_interconnect_0:keycode_s1_write -> keycode:write_n
wire [31:0] mm_interconnect_0_keycode_s1_writedata; // mm_interconnect_0:keycode_s1_writedata -> keycode:writedata
wire mm_interconnect_0_sdram_s1_chipselect; // mm_interconnect_0:sdram_s1_chipselect -> sdram:az_cs
wire [31:0] mm_interconnect_0_sdram_s1_readdata; // sdram:za_data -> mm_interconnect_0:sdram_s1_readdata
wire mm_interconnect_0_sdram_s1_waitrequest; // sdram:za_waitrequest -> mm_interconnect_0:sdram_s1_waitrequest
wire [24:0] mm_interconnect_0_sdram_s1_address; // mm_interconnect_0:sdram_s1_address -> sdram:az_addr
wire mm_interconnect_0_sdram_s1_read; // mm_interconnect_0:sdram_s1_read -> sdram:az_rd_n
wire [3:0] mm_interconnect_0_sdram_s1_byteenable; // mm_interconnect_0:sdram_s1_byteenable -> sdram:az_be_n
wire mm_interconnect_0_sdram_s1_readdatavalid; // sdram:za_valid -> mm_interconnect_0:sdram_s1_readdatavalid
wire mm_interconnect_0_sdram_s1_write; // mm_interconnect_0:sdram_s1_write -> sdram:az_wr_n
wire [31:0] mm_interconnect_0_sdram_s1_writedata; // mm_interconnect_0:sdram_s1_writedata -> sdram:az_data
wire clock_crossing_io_m0_waitrequest; // mm_interconnect_1:clock_crossing_io_m0_waitrequest -> clock_crossing_io:m0_waitrequest
wire [31:0] clock_crossing_io_m0_readdata; // mm_interconnect_1:clock_crossing_io_m0_readdata -> clock_crossing_io:m0_readdata
wire clock_crossing_io_m0_debugaccess; // clock_crossing_io:m0_debugaccess -> mm_interconnect_1:clock_crossing_io_m0_debugaccess
wire [21:0] clock_crossing_io_m0_address; // clock_crossing_io:m0_address -> mm_interconnect_1:clock_crossing_io_m0_address
wire clock_crossing_io_m0_read; // clock_crossing_io:m0_read -> mm_interconnect_1:clock_crossing_io_m0_read
wire [3:0] clock_crossing_io_m0_byteenable; // clock_crossing_io:m0_byteenable -> mm_interconnect_1:clock_crossing_io_m0_byteenable
wire clock_crossing_io_m0_readdatavalid; // mm_interconnect_1:clock_crossing_io_m0_readdatavalid -> clock_crossing_io:m0_readdatavalid
wire [31:0] clock_crossing_io_m0_writedata; // clock_crossing_io:m0_writedata -> mm_interconnect_1:clock_crossing_io_m0_writedata
wire clock_crossing_io_m0_write; // clock_crossing_io:m0_write -> mm_interconnect_1:clock_crossing_io_m0_write
wire [0:0] clock_crossing_io_m0_burstcount; // clock_crossing_io:m0_burstcount -> mm_interconnect_1:clock_crossing_io_m0_burstcount
wire mm_interconnect_1_cy7c67200_if_0_hpi_chipselect; // mm_interconnect_1:CY7C67200_IF_0_hpi_chipselect -> CY7C67200_IF_0:iCS_N
wire [31:0] mm_interconnect_1_cy7c67200_if_0_hpi_readdata; // CY7C67200_IF_0:oDATA -> mm_interconnect_1:CY7C67200_IF_0_hpi_readdata
wire [1:0] mm_interconnect_1_cy7c67200_if_0_hpi_address; // mm_interconnect_1:CY7C67200_IF_0_hpi_address -> CY7C67200_IF_0:iADDR
wire mm_interconnect_1_cy7c67200_if_0_hpi_read; // mm_interconnect_1:CY7C67200_IF_0_hpi_read -> CY7C67200_IF_0:iRD_N
wire mm_interconnect_1_cy7c67200_if_0_hpi_write; // mm_interconnect_1:CY7C67200_IF_0_hpi_write -> CY7C67200_IF_0:iWR_N
wire [31:0] mm_interconnect_1_cy7c67200_if_0_hpi_writedata; // mm_interconnect_1:CY7C67200_IF_0_hpi_writedata -> CY7C67200_IF_0:iDATA
wire irq_mapper_receiver1_irq; // jtag_uart:av_irq -> irq_mapper:receiver1_irq
wire [31:0] cpu_d_irq_irq; // irq_mapper:sender_irq -> cpu:d_irq
wire irq_mapper_receiver0_irq; // irq_synchronizer:sender_irq -> irq_mapper:receiver0_irq
wire [0:0] irq_synchronizer_receiver_irq; // CY7C67200_IF_0:oINT -> irq_synchronizer:receiver_irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [CY7C67200_IF_0:iRST_N, clock_crossing_io:m0_reset, irq_synchronizer:receiver_reset, mm_interconnect_1:clock_crossing_io_m0_reset_reset_bridge_in_reset_reset]
wire cpu_jtag_debug_module_reset_reset; // cpu:jtag_debug_module_resetrequest -> [rst_controller:reset_in1, rst_controller_001:reset_in1, rst_controller_002:reset_in1]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [clock_crossing_io:s0_reset, clocks:reset, cpu:reset_n, irq_mapper:reset, irq_synchronizer:sender_reset, jtag_uart:rst_n, keycode:reset_n, mm_interconnect_0:cpu_reset_n_reset_bridge_in_reset_reset, rst_translator:in_reset]
wire rst_controller_001_reset_out_reset_req; // rst_controller_001:reset_req -> [cpu:reset_req, rst_translator:reset_req_in]
wire rst_controller_002_reset_out_reset; // rst_controller_002:reset_out -> [mm_interconnect_0:sdram_reset_reset_bridge_in_reset_reset, sdram:reset_n]
CY7C67200_IF cy7c67200_if_0 (
.oDATA (mm_interconnect_1_cy7c67200_if_0_hpi_readdata), // hpi.readdata
.iADDR (mm_interconnect_1_cy7c67200_if_0_hpi_address), // .address
.iRD_N (~mm_interconnect_1_cy7c67200_if_0_hpi_read), // .read_n
.iWR_N (~mm_interconnect_1_cy7c67200_if_0_hpi_write), // .write_n
.iCS_N (~mm_interconnect_1_cy7c67200_if_0_hpi_chipselect), // .chipselect_n
.iDATA (mm_interconnect_1_cy7c67200_if_0_hpi_writedata), // .writedata
.iCLK (usb_out_clk_clk), // clock_sink.clk
.iRST_N (~rst_controller_reset_out_reset), // clock_sink_reset.reset_n
.oINT (irq_synchronizer_receiver_irq), // interrupt_sender.irq
.HPI_DATA (usb_DATA), // conduit_end.export
.HPI_ADDR (usb_ADDR), // .export
.HPI_RD_N (usb_RD_N), // .export
.HPI_WR_N (usb_WR_N), // .export
.HPI_CS_N (usb_CS_N), // .export
.HPI_RST_N (usb_RST_N), // .export
.HPI_INT (usb_INT) // .export
);
altera_avalon_mm_clock_crossing_bridge #(
.DATA_WIDTH (32),
.SYMBOL_WIDTH (8),
.HDL_ADDR_WIDTH (22),
.BURSTCOUNT_WIDTH (1),
.COMMAND_FIFO_DEPTH (32),
.RESPONSE_FIFO_DEPTH (256),
.MASTER_SYNC_DEPTH (3),
.SLAVE_SYNC_DEPTH (3)
) clock_crossing_io (
.m0_clk (usb_out_clk_clk), // m0_clk.clk
.m0_reset (rst_controller_reset_out_reset), // m0_reset.reset
.s0_clk (clk_clk), // s0_clk.clk
.s0_reset (rst_controller_001_reset_out_reset), // s0_reset.reset
.s0_waitrequest (mm_interconnect_0_clock_crossing_io_s0_waitrequest), // s0.waitrequest
.s0_readdata (mm_interconnect_0_clock_crossing_io_s0_readdata), // .readdata
.s0_readdatavalid (mm_interconnect_0_clock_crossing_io_s0_readdatavalid), // .readdatavalid
.s0_burstcount (mm_interconnect_0_clock_crossing_io_s0_burstcount), // .burstcount
.s0_writedata (mm_interconnect_0_clock_crossing_io_s0_writedata), // .writedata
.s0_address (mm_interconnect_0_clock_crossing_io_s0_address), // .address
.s0_write (mm_interconnect_0_clock_crossing_io_s0_write), // .write
.s0_read (mm_interconnect_0_clock_crossing_io_s0_read), // .read
.s0_byteenable (mm_interconnect_0_clock_crossing_io_s0_byteenable), // .byteenable
.s0_debugaccess (mm_interconnect_0_clock_crossing_io_s0_debugaccess), // .debugaccess
.m0_waitrequest (clock_crossing_io_m0_waitrequest), // m0.waitrequest
.m0_readdata (clock_crossing_io_m0_readdata), // .readdata
.m0_readdatavalid (clock_crossing_io_m0_readdatavalid), // .readdatavalid
.m0_burstcount (clock_crossing_io_m0_burstcount), // .burstcount
.m0_writedata (clock_crossing_io_m0_writedata), // .writedata
.m0_address (clock_crossing_io_m0_address), // .address
.m0_write (clock_crossing_io_m0_write), // .write
.m0_read (clock_crossing_io_m0_read), // .read
.m0_byteenable (clock_crossing_io_m0_byteenable), // .byteenable
.m0_debugaccess (clock_crossing_io_m0_debugaccess) // .debugaccess
);
finalproject_clocks clocks (
.clk (clk_clk), // inclk_interface.clk
.reset (rst_controller_001_reset_out_reset), // inclk_interface_reset.reset
.read (mm_interconnect_0_clocks_pll_slave_read), // pll_slave.read
.write (mm_interconnect_0_clocks_pll_slave_write), // .write
.address (mm_interconnect_0_clocks_pll_slave_address), // .address
.readdata (mm_interconnect_0_clocks_pll_slave_readdata), // .readdata
.writedata (mm_interconnect_0_clocks_pll_slave_writedata), // .writedata
.c0 (sdram_out_clk_clk), // c0.clk
.c1 (usb_out_clk_clk), // c1.clk
.areset (), // areset_conduit.export
.locked (), // locked_conduit.export
.phasedone () // phasedone_conduit.export
);
finalproject_cpu cpu (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset_n.reset_n
.reset_req (rst_controller_001_reset_out_reset_req), // .reset_req
.d_address (cpu_data_master_address), // data_master.address
.d_byteenable (cpu_data_master_byteenable), // .byteenable
.d_read (cpu_data_master_read), // .read
.d_readdata (cpu_data_master_readdata), // .readdata
.d_waitrequest (cpu_data_master_waitrequest), // .waitrequest
.d_write (cpu_data_master_write), // .write
.d_writedata (cpu_data_master_writedata), // .writedata
.jtag_debug_module_debugaccess_to_roms (cpu_data_master_debugaccess), // .debugaccess
.i_address (cpu_instruction_master_address), // instruction_master.address
.i_read (cpu_instruction_master_read), // .read
.i_readdata (cpu_instruction_master_readdata), // .readdata
.i_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest
.d_irq (cpu_d_irq_irq), // d_irq.irq
.jtag_debug_module_resetrequest (cpu_jtag_debug_module_reset_reset), // jtag_debug_module_reset.reset
.jtag_debug_module_address (mm_interconnect_0_cpu_jtag_debug_module_address), // jtag_debug_module.address
.jtag_debug_module_byteenable (mm_interconnect_0_cpu_jtag_debug_module_byteenable), // .byteenable
.jtag_debug_module_debugaccess (mm_interconnect_0_cpu_jtag_debug_module_debugaccess), // .debugaccess
.jtag_debug_module_read (mm_interconnect_0_cpu_jtag_debug_module_read), // .read
.jtag_debug_module_readdata (mm_interconnect_0_cpu_jtag_debug_module_readdata), // .readdata
.jtag_debug_module_waitrequest (mm_interconnect_0_cpu_jtag_debug_module_waitrequest), // .waitrequest
.jtag_debug_module_write (mm_interconnect_0_cpu_jtag_debug_module_write), // .write
.jtag_debug_module_writedata (mm_interconnect_0_cpu_jtag_debug_module_writedata), // .writedata
.no_ci_readra () // custom_instruction_master.readra
);
finalproject_jtag_uart jtag_uart (
.clk (clk_clk), // clk.clk
.rst_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.av_chipselect (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect), // avalon_jtag_slave.chipselect
.av_address (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address), // .address
.av_read_n (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_read), // .read_n
.av_readdata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata), // .readdata
.av_write_n (~mm_interconnect_0_jtag_uart_avalon_jtag_slave_write), // .write_n
.av_writedata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.av_irq (irq_mapper_receiver1_irq) // irq.irq
);
finalproject_keycode keycode (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_keycode_s1_address), // s1.address
.write_n (~mm_interconnect_0_keycode_s1_write), // .write_n
.writedata (mm_interconnect_0_keycode_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_keycode_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_keycode_s1_readdata), // .readdata
.out_port (keycode_export) // external_connection.export
);
finalproject_sdram sdram (
.clk (sdram_out_clk_clk), // clk.clk
.reset_n (~rst_controller_002_reset_out_reset), // reset.reset_n
.az_addr (mm_interconnect_0_sdram_s1_address), // s1.address
.az_be_n (~mm_interconnect_0_sdram_s1_byteenable), // .byteenable_n
.az_cs (mm_interconnect_0_sdram_s1_chipselect), // .chipselect
.az_data (mm_interconnect_0_sdram_s1_writedata), // .writedata
.az_rd_n (~mm_interconnect_0_sdram_s1_read), // .read_n
.az_wr_n (~mm_interconnect_0_sdram_s1_write), // .write_n
.za_data (mm_interconnect_0_sdram_s1_readdata), // .readdata
.za_valid (mm_interconnect_0_sdram_s1_readdatavalid), // .readdatavalid
.za_waitrequest (mm_interconnect_0_sdram_s1_waitrequest), // .waitrequest
.zs_addr (sdram_wire_addr), // wire.export
.zs_ba (sdram_wire_ba), // .export
.zs_cas_n (sdram_wire_cas_n), // .export
.zs_cke (sdram_wire_cke), // .export
.zs_cs_n (sdram_wire_cs_n), // .export
.zs_dq (sdram_wire_dq), // .export
.zs_dqm (sdram_wire_dqm), // .export
.zs_ras_n (sdram_wire_ras_n), // .export
.zs_we_n (sdram_wire_we_n) // .export
);
finalproject_mm_interconnect_0 mm_interconnect_0 (
.clk_clk_clk (clk_clk), // clk_clk.clk
.clocks_c0_clk (sdram_out_clk_clk), // clocks_c0.clk
.cpu_reset_n_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // cpu_reset_n_reset_bridge_in_reset.reset
.sdram_reset_reset_bridge_in_reset_reset (rst_controller_002_reset_out_reset), // sdram_reset_reset_bridge_in_reset.reset
.cpu_data_master_address (cpu_data_master_address), // cpu_data_master.address
.cpu_data_master_waitrequest (cpu_data_master_waitrequest), // .waitrequest
.cpu_data_master_byteenable (cpu_data_master_byteenable), // .byteenable
.cpu_data_master_read (cpu_data_master_read), // .read
.cpu_data_master_readdata (cpu_data_master_readdata), // .readdata
.cpu_data_master_write (cpu_data_master_write), // .write
.cpu_data_master_writedata (cpu_data_master_writedata), // .writedata
.cpu_data_master_debugaccess (cpu_data_master_debugaccess), // .debugaccess
.cpu_instruction_master_address (cpu_instruction_master_address), // cpu_instruction_master.address
.cpu_instruction_master_waitrequest (cpu_instruction_master_waitrequest), // .waitrequest
.cpu_instruction_master_read (cpu_instruction_master_read), // .read
.cpu_instruction_master_readdata (cpu_instruction_master_readdata), // .readdata
.clock_crossing_io_s0_address (mm_interconnect_0_clock_crossing_io_s0_address), // clock_crossing_io_s0.address
.clock_crossing_io_s0_write (mm_interconnect_0_clock_crossing_io_s0_write), // .write
.clock_crossing_io_s0_read (mm_interconnect_0_clock_crossing_io_s0_read), // .read
.clock_crossing_io_s0_readdata (mm_interconnect_0_clock_crossing_io_s0_readdata), // .readdata
.clock_crossing_io_s0_writedata (mm_interconnect_0_clock_crossing_io_s0_writedata), // .writedata
.clock_crossing_io_s0_burstcount (mm_interconnect_0_clock_crossing_io_s0_burstcount), // .burstcount
.clock_crossing_io_s0_byteenable (mm_interconnect_0_clock_crossing_io_s0_byteenable), // .byteenable
.clock_crossing_io_s0_readdatavalid (mm_interconnect_0_clock_crossing_io_s0_readdatavalid), // .readdatavalid
.clock_crossing_io_s0_waitrequest (mm_interconnect_0_clock_crossing_io_s0_waitrequest), // .waitrequest
.clock_crossing_io_s0_debugaccess (mm_interconnect_0_clock_crossing_io_s0_debugaccess), // .debugaccess
.clocks_pll_slave_address (mm_interconnect_0_clocks_pll_slave_address), // clocks_pll_slave.address
.clocks_pll_slave_write (mm_interconnect_0_clocks_pll_slave_write), // .write
.clocks_pll_slave_read (mm_interconnect_0_clocks_pll_slave_read), // .read
.clocks_pll_slave_readdata (mm_interconnect_0_clocks_pll_slave_readdata), // .readdata
.clocks_pll_slave_writedata (mm_interconnect_0_clocks_pll_slave_writedata), // .writedata
.cpu_jtag_debug_module_address (mm_interconnect_0_cpu_jtag_debug_module_address), // cpu_jtag_debug_module.address
.cpu_jtag_debug_module_write (mm_interconnect_0_cpu_jtag_debug_module_write), // .write
.cpu_jtag_debug_module_read (mm_interconnect_0_cpu_jtag_debug_module_read), // .read
.cpu_jtag_debug_module_readdata (mm_interconnect_0_cpu_jtag_debug_module_readdata), // .readdata
.cpu_jtag_debug_module_writedata (mm_interconnect_0_cpu_jtag_debug_module_writedata), // .writedata
.cpu_jtag_debug_module_byteenable (mm_interconnect_0_cpu_jtag_debug_module_byteenable), // .byteenable
.cpu_jtag_debug_module_waitrequest (mm_interconnect_0_cpu_jtag_debug_module_waitrequest), // .waitrequest
.cpu_jtag_debug_module_debugaccess (mm_interconnect_0_cpu_jtag_debug_module_debugaccess), // .debugaccess
.jtag_uart_avalon_jtag_slave_address (mm_interconnect_0_jtag_uart_avalon_jtag_slave_address), // jtag_uart_avalon_jtag_slave.address
.jtag_uart_avalon_jtag_slave_write (mm_interconnect_0_jtag_uart_avalon_jtag_slave_write), // .write
.jtag_uart_avalon_jtag_slave_read (mm_interconnect_0_jtag_uart_avalon_jtag_slave_read), // .read
.jtag_uart_avalon_jtag_slave_readdata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_readdata), // .readdata
.jtag_uart_avalon_jtag_slave_writedata (mm_interconnect_0_jtag_uart_avalon_jtag_slave_writedata), // .writedata
.jtag_uart_avalon_jtag_slave_waitrequest (mm_interconnect_0_jtag_uart_avalon_jtag_slave_waitrequest), // .waitrequest
.jtag_uart_avalon_jtag_slave_chipselect (mm_interconnect_0_jtag_uart_avalon_jtag_slave_chipselect), // .chipselect
.keycode_s1_address (mm_interconnect_0_keycode_s1_address), // keycode_s1.address
.keycode_s1_write (mm_interconnect_0_keycode_s1_write), // .write
.keycode_s1_readdata (mm_interconnect_0_keycode_s1_readdata), // .readdata
.keycode_s1_writedata (mm_interconnect_0_keycode_s1_writedata), // .writedata
.keycode_s1_chipselect (mm_interconnect_0_keycode_s1_chipselect), // .chipselect
.sdram_s1_address (mm_interconnect_0_sdram_s1_address), // sdram_s1.address
.sdram_s1_write (mm_interconnect_0_sdram_s1_write), // .write
.sdram_s1_read (mm_interconnect_0_sdram_s1_read), // .read
.sdram_s1_readdata (mm_interconnect_0_sdram_s1_readdata), // .readdata
.sdram_s1_writedata (mm_interconnect_0_sdram_s1_writedata), // .writedata
.sdram_s1_byteenable (mm_interconnect_0_sdram_s1_byteenable), // .byteenable
.sdram_s1_readdatavalid (mm_interconnect_0_sdram_s1_readdatavalid), // .readdatavalid
.sdram_s1_waitrequest (mm_interconnect_0_sdram_s1_waitrequest), // .waitrequest
.sdram_s1_chipselect (mm_interconnect_0_sdram_s1_chipselect) // .chipselect
);
finalproject_mm_interconnect_1 mm_interconnect_1 (
.clocks_c1_clk (usb_out_clk_clk), // clocks_c1.clk
.clock_crossing_io_m0_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // clock_crossing_io_m0_reset_reset_bridge_in_reset.reset
.clock_crossing_io_m0_address (clock_crossing_io_m0_address), // clock_crossing_io_m0.address
.clock_crossing_io_m0_waitrequest (clock_crossing_io_m0_waitrequest), // .waitrequest
.clock_crossing_io_m0_burstcount (clock_crossing_io_m0_burstcount), // .burstcount
.clock_crossing_io_m0_byteenable (clock_crossing_io_m0_byteenable), // .byteenable
.clock_crossing_io_m0_read (clock_crossing_io_m0_read), // .read
.clock_crossing_io_m0_readdata (clock_crossing_io_m0_readdata), // .readdata
.clock_crossing_io_m0_readdatavalid (clock_crossing_io_m0_readdatavalid), // .readdatavalid
.clock_crossing_io_m0_write (clock_crossing_io_m0_write), // .write
.clock_crossing_io_m0_writedata (clock_crossing_io_m0_writedata), // .writedata
.clock_crossing_io_m0_debugaccess (clock_crossing_io_m0_debugaccess), // .debugaccess
.CY7C67200_IF_0_hpi_address (mm_interconnect_1_cy7c67200_if_0_hpi_address), // CY7C67200_IF_0_hpi.address
.CY7C67200_IF_0_hpi_write (mm_interconnect_1_cy7c67200_if_0_hpi_write), // .write
.CY7C67200_IF_0_hpi_read (mm_interconnect_1_cy7c67200_if_0_hpi_read), // .read
.CY7C67200_IF_0_hpi_readdata (mm_interconnect_1_cy7c67200_if_0_hpi_readdata), // .readdata
.CY7C67200_IF_0_hpi_writedata (mm_interconnect_1_cy7c67200_if_0_hpi_writedata), // .writedata
.CY7C67200_IF_0_hpi_chipselect (mm_interconnect_1_cy7c67200_if_0_hpi_chipselect) // .chipselect
);
finalproject_irq_mapper irq_mapper (
.clk (clk_clk), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq
.sender_irq (cpu_d_irq_irq) // sender.irq
);
altera_irq_clock_crosser #(
.IRQ_WIDTH (1)
) irq_synchronizer (
.receiver_clk (usb_out_clk_clk), // receiver_clk.clk
.sender_clk (clk_clk), // sender_clk.clk
.receiver_reset (rst_controller_reset_out_reset), // receiver_clk_reset.reset
.sender_reset (rst_controller_001_reset_out_reset), // sender_clk_reset.reset
.receiver_irq (irq_synchronizer_receiver_irq), // receiver.irq
.sender_irq (irq_mapper_receiver0_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (cpu_jtag_debug_module_reset_reset), // reset_in1.reset
.clk (usb_out_clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (cpu_jtag_debug_module_reset_reset), // reset_in1.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_001_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_002 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (cpu_jtag_debug_module_reset_reset), // reset_in1.reset
.clk (sdram_out_clk_clk), // clk.clk
.reset_out (rst_controller_002_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
// cog_vid
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
// Andy Silverman 20140904 Converted clock signal with logic to Xilinx clock enabled primitive.
// Magnus Karlsson 20140818 Rewrote SystemVerilog code to Verilog2001 style
module cog_vid
(
input clk_cog,
input clk_vid,
input ena,
input setvid,
input setscl,
input [31:0] data,
input [31:0] pixel,
input [31:0] color,
input [7:0] aural,
input carrier,
output ack,
output [31:0] pin_out
);
// configuration
reg [31:0] vid;
reg [31:0] scl;
always @(posedge clk_cog or negedge ena)
if (!ena)
vid <= 32'b0;
else if (setvid)
vid <= data;
always @(posedge clk_cog)
if (setscl)
scl <= data;
// video shifter
reg [7:0] cnts;
reg [7:0] cnt;
reg [11:0] set;
reg [31:0] pixels;
reg [31:0] colors;
wire enable = |vid[30:29];
//wire vclk = clk_vid && enable;
wire vclk;
BUFGCE vclk_buf (.I(clk_vid),.CE(enable),.O(vclk));
wire new_set = set == 1'b1;
wire new_cnt = cnt == 1'b1;
always @(posedge vclk)
if (new_set)
cnts <= scl[19:12];
always @(posedge vclk)
cnt <= new_set ? scl[19:12]
: new_cnt ? cnts
: cnt - 1'b1;
always @(posedge vclk)
set <= new_set ? scl[11:0]
: set - 1'b1;
always @(posedge vclk)
if (new_set || new_cnt)
pixels <= new_set ? pixel
: vid[28] ? {pixels[31:30], pixels[31:2]}
: {pixels[31], pixels[31:1]};
always @(posedge vclk)
if (new_set)
colors <= color;
// capture/acknowledge
reg cap;
reg [1:0] snc;
always @(posedge vclk or posedge snc[1])
if (snc[1])
cap <= 1'b0;
else if (new_set)
cap <= 1'b1;
always @(posedge clk_cog)
if (enable)
snc <= {snc[0], cap};
assign ack = snc[0];
// discrete output
reg [7:0] discrete;
wire [31:0] colorx = colors >> {vid[28] && pixels[1], pixels[0], 3'b000};
always @(posedge vclk)
discrete <= colorx[7:0];
// baseband output
//
// +-------------------------------+
// out 7 ! - + * !
// 6 ! + * - !
// 5 ! + * - !
// 4 ! + * - !
// 3 ! + * - !
// 2 ! + * - !
// 1 ! + * - !
// 0 ! * - + !
// +-------------------------------+
// in 0 1 2 3 4 5 6 7
reg [3:0] phase;
reg [3:0] baseband;
always @(posedge vclk)
phase <= phase + 1'b1;
wire [3:0] colorphs = discrete[7:4] + phase;
wire [2:0] colormod = discrete[2:0] + { discrete[3] && colorphs[3],
discrete[3] && colorphs[3],
discrete[3] };
always @(posedge vclk)
baseband <= {discrete[3] && colorphs[3], vid[26] ? colormod : discrete[2:0]};
// broadcast output
//
// +-------------------------------+
// out 7 ! * !
// 6 ! * * !
// 5 ! * * !
// 4 ! * * !
// 3 ! * * !
// 2 ! * * !
// 1 ! * * !
// 0 ! * * !
// +-------------------------------+
// in 0 1 2 3 4 5 6 7
reg [2:0] composite;
always @(posedge vclk)
composite <= vid[27] ? colormod : discrete[2:0];
wire [63:0] level = 64'b0011_0100_0100_0101_0101_0110_0110_0111_0011_0011_0010_0010_0001_0001_0000_0000;
wire [3:0] broadcast = {carrier ^ aural[vid[25:23]], level[{carrier, composite}*4 +: 3]};
// output pins
wire [7:0] outp = vid[30] ? vid[29] ? {baseband, broadcast}
: {broadcast, baseband}
: discrete;
assign pin_out = enable ? {24'b0, outp & vid[7:0]} << {vid[10:9], 3'b000} : 32'b0;
endmodule
|
`include "elink_regmap.v"
module etx_protocol (/*AUTOARG*/
// Outputs
etx_rd_wait, etx_wr_wait, tx_packet, tx_access, tx_burst,
// Inputs
reset, clk, etx_access, etx_packet, tx_enable, gpio_data,
gpio_enable, tx_io_wait, tx_rd_wait, tx_wr_wait
);
parameter PW = 104;
parameter AW = 32;
parameter DW = 32;
parameter ID = 12'h000;
//Clock/reset
input reset;
input clk;
//System side
input etx_access;
input [PW-1:0] etx_packet;
//Pushback signals
output etx_rd_wait;
output etx_wr_wait;
//Enble transmit
input tx_enable; //transmit enable
input [8:0] gpio_data; //TODO
input gpio_enable; //TODO
//Interface to IO
output [PW-1:0] tx_packet;
output tx_access;
output tx_burst;
input tx_io_wait;
input tx_rd_wait; // The wait signals are passed through
input tx_wr_wait; // to the emesh interfaces
//###################################################################
//# Local regs & wires
//###################################################################
reg tx_burst;
reg tx_access;
reg [PW-1:0] tx_packet;
reg tx_rd_wait_sync;
reg tx_wr_wait_sync;
wire etx_write;
wire [1:0] etx_datamode;
wire [3:0] etx_ctrlmode;
wire [AW-1:0] etx_dstaddr;
wire [DW-1:0] etx_data;
wire last_write;
wire [1:0] last_datamode;
wire [3:0] last_ctrlmode;
wire [AW-1:0] last_dstaddr;
wire etx_valid;
reg etx_io_wait;
wire burst_match;
wire burst_type_match;
wire [31:0] burst_addr;
wire burst_addr_match;
reg etx_rd_wait_reg;
reg etx_wr_wait_reg;
//packet to emesh bundle
packet2emesh p2m0 (.access_out (),
.write_out (etx_write),
.datamode_out (etx_datamode[1:0]),
.ctrlmode_out (etx_ctrlmode[3:0]),
.dstaddr_out (etx_dstaddr[31:0]),
.data_out (),
.srcaddr_out (),
.packet_in (etx_packet[PW-1:0]));//input
//Only set valid if not wait and
assign etx_valid = (tx_enable &
etx_access &
~((etx_dstaddr[31:20]==ID) & (etx_dstaddr[19:16]!=`EGROUP_RR)) &
((etx_write & ~tx_wr_wait_sync) | (~etx_write & ~tx_rd_wait_sync))
);
//Prepare transaction / with burst
always @ (posedge clk)
if(reset)
begin
tx_packet[PW-1:0] <= 'b0;
tx_access <= 1'b0;
end
else if(~tx_io_wait)
begin
tx_packet[PW-1:0] <= etx_packet[PW-1:0];
tx_access <= etx_valid;
end
always @ (posedge clk)
if(reset)
tx_burst <= 1'b0;
else
tx_burst <= (etx_write & //write
(etx_datamode[1:0]==2'b11) & //double only
burst_type_match & //same types
burst_addr_match); //inc by 8
//#############################
//# Burst Detection
//#############################
packet2emesh p2m1 (.access_out (last_access),
.write_out (last_write),
.datamode_out (last_datamode[1:0]),
.ctrlmode_out (last_ctrlmode[3:0]),
.dstaddr_out (last_dstaddr[31:0]),
.data_out (),
.srcaddr_out (),
.packet_in (tx_packet[PW-1:0]));//input
assign burst_addr[31:0] = (last_dstaddr[31:0] + 4'd8);
assign burst_addr_match = (burst_addr[31:0] == etx_dstaddr[31:0]);
assign burst_type_match = {last_ctrlmode[3:0],last_datamode[1:0],last_write}
==
{etx_ctrlmode[3:0],etx_datamode[1:0], etx_write};
//#############################
//# Wait signals (async)
//#############################
/* synchronizer #(.DW(1)) rd_sync (// Outputs
.out (tx_rd_wait_sync),
// Inputs
.in (tx_rd_wait),
.clk (clk),
.reset (reset)
);
synchronizer #(.DW(1)) wr_sync (// Outputs
.out (tx_wr_wait_sync),
// Inputs
.in (tx_wr_wait),
.clk (clk),
.reset (reset)
);
*/
always @ (posedge clk)
if(reset) begin
tx_wr_wait_sync <= 1'b0;
tx_rd_wait_sync <= 1'b0;
end
else begin
tx_wr_wait_sync <= tx_wr_wait;
tx_rd_wait_sync <= tx_rd_wait;
end
//Stall for all etx pipeline
//assign etx_wr_wait = tx_wr_wait_sync | tx_io_wait;
//assign etx_rd_wait = tx_rd_wait_sync | tx_io_wait;
always @ (posedge clk) begin
etx_wr_wait_reg <= tx_wr_wait | tx_io_wait;
etx_rd_wait_reg <= tx_rd_wait | tx_io_wait;
end
assign etx_wr_wait = etx_wr_wait_reg;
assign etx_rd_wait = etx_rd_wait_reg;
endmodule // etx_protocol
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
module adv3224 (
// avalon-bus
input clk,
input reset,
input avs_slave_write,
input avs_slave_read,
input [7:0]avs_slave_writedata,
output [7:0]avs_slave_readdata,
input [2:0]avs_slave_address,
// adv3224
output cps_reset_n,
output cps_ce_n,
output cps_update_n,
output cps_clk,
output cps_datain
);
//
// parameters
//
parameter divider = 5;
//
// regs / wires
//
reg [8:0]clk_counter;
reg div_clk;
reg clk_en;
reg [39:0]shift_buffer;
reg shift_busy;
reg [5:0]shift_counter;
reg [4:0]outputs[0:7];
//
// ip
//
assign cps_reset_n = !reset;
assign cps_ce_n = 0;
assign avs_slave_readdata = shift_busy;
assign cps_clk = clk_en ? div_clk : 1'b1;
assign cps_update_n = (!clk_en && shift_busy) ? !div_clk : 1'b1;
assign cps_datain = shift_buffer[39];
always @(posedge clk or posedge reset)
begin
if(reset)
begin
clk_counter <= 1;
div_clk <= 1;
clk_en <= 0;
shift_busy <= 0;
shift_counter <= 0;
outputs[0] <= 5'b00000;
outputs[1] <= 5'b00000;
outputs[2] <= 5'b00000;
outputs[3] <= 5'b00000;
outputs[4] <= 5'b00000;
outputs[5] <= 5'b00000;
outputs[6] <= 5'b00000;
outputs[7] <= 5'b00000;
end
else
begin // posedge clk
if(shift_busy)
begin
if(clk_counter == (divider/2))
begin
clk_counter <= 1;
div_clk <= !div_clk;
if(!div_clk)
begin
if(!clk_en)
begin
shift_busy <= 0;
end
else
begin
if(shift_counter == 39)
begin
clk_en <= 0;
end
else
begin
shift_counter <= shift_counter + 6'd1;
shift_buffer <= shift_buffer << 1;
end
end
end
end
else
begin
clk_counter = clk_counter + 9'd1;
end
end
else
begin
clk_counter <= 1;
shift_counter <= 0;
div_clk <= 1;
if(avs_slave_write)
begin
if(avs_slave_writedata[7])
begin
shift_buffer <= {outputs[7], outputs[6], outputs[5], outputs[4], outputs[3], outputs[2], outputs[1], outputs[0]};
shift_busy <= 1;
clk_en <= 1;
end
else
begin
outputs[avs_slave_address] <= {!avs_slave_writedata[4], avs_slave_writedata[3:0]};
end
end
end
end
end
endmodule |
module t_sha1();
reg clk;
reg start;
reg eof;
reg [511:0] data_block;
reg [ 63:0] msg_length;
wire [159:0] hash;
wire next_block;
wire done;
integer fpr, bytes_returned;
sha1 uut(
.clk(clk),
.start(start),
.eof(eof),
.data_block(data_block),
.msg_length(msg_length),
.hash(hash),
.next_block(next_block),
.done(done)
);
initial begin
clk = 1'b0;
start = 1'b0;
eof = 1'b0;
data_block = 512'd0;
msg_length = 64'd0;
fpr = $fopen("testvector3.tv", "rb");
bytes_returned = $fread(data_block, fpr);
if (bytes_returned == 0) eof = 1'b1;
msg_length = msg_length + bytes_returned;
pulse_start();
end
always #10 clk = ~clk;
always @ (posedge clk) begin
if (next_block) begin
bytes_returned = $fread(data_block, fpr);
if (bytes_returned == 0) eof = 1'b1;
msg_length = msg_length + bytes_returned;
end
else if (done) end_simulation();
end
task pulse_start;
begin
//Pulse the start signal for next block.
start <= 1'b1;
#20 start <= 1'b0;
end
endtask
task end_simulation;
begin
$display("Hexdigest: %h", hash);
$fclose(fpr);
$stop;
end
endtask
endmodule
|
// Fast Multisource Pulse Registration System
// Module:
// event_tagger
// Pulse Registration and Time Stamping
// (c) Sergey V. Polyakov 2006-forever
module event_tagger(
strobe_channels,
delta_channels,
clk,
reset_counter,
capture_operate, counter_operate,
data,
ready
);
input [3:0] strobe_channels;
input [3:0] delta_channels;
input clk;
input reset_counter;
input capture_operate;
input counter_operate;
output ready;
output [46:0] data;
reg [35:0] timer = 36'b0;
reg [3:0] old_delta = 3'b0;
reg ready = 0;
reg [46:0] data = 47'b0;
always @(posedge clk)
begin
if (delta_channels != old_delta) // First monitor delta inputs
begin
data[35:0] <= timer[35:0];
data[39:36] <= delta_channels;
data[44:40] <= 0; // reserved
data[45] <= 1; // record type
data[46] <= (timer==1'b0) ? 1'b1 : 1'b0; // wraparound
ready <= capture_operate;
old_delta <= delta_channels;
end
else if (strobe_channels != 4'b0 || (timer == 36'b0 && counter_operate))
begin
data[35:0] <= timer[35:0];
data[39:36] <= strobe_channels;
data[44:40] <= 0; // reserved
data[45] <= 0; // record type
data[46] <= (timer==36'b0) ? 1'b1 : 1'b0; // wraparound
ready <= capture_operate;
end
else
begin
ready <= 0;
data <= 47'bX;
end
/*if (reset_counter)
timer <= 0;
else if (counter_operate)
timer <= timer + 1;*/
timer <= reset_counter ? 0 : timer + counter_operate;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR4BB_PP_SYMBOL_V
`define SKY130_FD_SC_LP__OR4BB_PP_SYMBOL_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__or4bb (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N ,
input D_N ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR4BB_PP_SYMBOL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Wed May 31 20:14:25 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/dma_example/dma_example.srcs/sources_1/bd/system/ip/system_xbar_0/system_xbar_0_stub.v
// Design : system_xbar_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_crossbar_v2_1_12_axi_crossbar,Vivado 2016.4" *)
module system_xbar_0(aclk, aresetn, s_axi_awid, s_axi_awaddr,
s_axi_awlen, s_axi_awsize, s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awqos, s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wlast,
s_axi_wvalid, s_axi_wready, s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_arid,
s_axi_araddr, s_axi_arlen, s_axi_arsize, s_axi_arburst, s_axi_arlock, s_axi_arcache,
s_axi_arprot, s_axi_arqos, s_axi_arvalid, s_axi_arready, s_axi_rid, s_axi_rdata, s_axi_rresp,
s_axi_rlast, s_axi_rvalid, s_axi_rready, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot, m_axi_awregion, m_axi_awqos,
m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wlast, m_axi_wvalid,
m_axi_wready, m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_arid, m_axi_araddr,
m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock, m_axi_arcache, m_axi_arprot,
m_axi_arregion, m_axi_arqos, m_axi_arvalid, m_axi_arready, m_axi_rid, m_axi_rdata,
m_axi_rresp, m_axi_rlast, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awid[5:0],s_axi_awaddr[95:0],s_axi_awlen[23:0],s_axi_awsize[8:0],s_axi_awburst[5:0],s_axi_awlock[2:0],s_axi_awcache[11:0],s_axi_awprot[8:0],s_axi_awqos[11:0],s_axi_awvalid[2:0],s_axi_awready[2:0],s_axi_wdata[191:0],s_axi_wstrb[23:0],s_axi_wlast[2:0],s_axi_wvalid[2:0],s_axi_wready[2:0],s_axi_bid[5:0],s_axi_bresp[5:0],s_axi_bvalid[2:0],s_axi_bready[2:0],s_axi_arid[5:0],s_axi_araddr[95:0],s_axi_arlen[23:0],s_axi_arsize[8:0],s_axi_arburst[5:0],s_axi_arlock[2:0],s_axi_arcache[11:0],s_axi_arprot[8:0],s_axi_arqos[11:0],s_axi_arvalid[2:0],s_axi_arready[2:0],s_axi_rid[5:0],s_axi_rdata[191:0],s_axi_rresp[5:0],s_axi_rlast[2:0],s_axi_rvalid[2:0],s_axi_rready[2:0],m_axi_awid[1:0],m_axi_awaddr[31:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[0:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awregion[3:0],m_axi_awqos[3:0],m_axi_awvalid[0:0],m_axi_awready[0:0],m_axi_wdata[63:0],m_axi_wstrb[7:0],m_axi_wlast[0:0],m_axi_wvalid[0:0],m_axi_wready[0:0],m_axi_bid[1:0],m_axi_bresp[1:0],m_axi_bvalid[0:0],m_axi_bready[0:0],m_axi_arid[1:0],m_axi_araddr[31:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[0:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arregion[3:0],m_axi_arqos[3:0],m_axi_arvalid[0:0],m_axi_arready[0:0],m_axi_rid[1:0],m_axi_rdata[63:0],m_axi_rresp[1:0],m_axi_rlast[0:0],m_axi_rvalid[0:0],m_axi_rready[0:0]" */;
input aclk;
input aresetn;
input [5:0]s_axi_awid;
input [95:0]s_axi_awaddr;
input [23:0]s_axi_awlen;
input [8:0]s_axi_awsize;
input [5:0]s_axi_awburst;
input [2:0]s_axi_awlock;
input [11:0]s_axi_awcache;
input [8:0]s_axi_awprot;
input [11:0]s_axi_awqos;
input [2:0]s_axi_awvalid;
output [2:0]s_axi_awready;
input [191:0]s_axi_wdata;
input [23:0]s_axi_wstrb;
input [2:0]s_axi_wlast;
input [2:0]s_axi_wvalid;
output [2:0]s_axi_wready;
output [5:0]s_axi_bid;
output [5:0]s_axi_bresp;
output [2:0]s_axi_bvalid;
input [2:0]s_axi_bready;
input [5:0]s_axi_arid;
input [95:0]s_axi_araddr;
input [23:0]s_axi_arlen;
input [8:0]s_axi_arsize;
input [5:0]s_axi_arburst;
input [2:0]s_axi_arlock;
input [11:0]s_axi_arcache;
input [8:0]s_axi_arprot;
input [11:0]s_axi_arqos;
input [2:0]s_axi_arvalid;
output [2:0]s_axi_arready;
output [5:0]s_axi_rid;
output [191:0]s_axi_rdata;
output [5:0]s_axi_rresp;
output [2:0]s_axi_rlast;
output [2:0]s_axi_rvalid;
input [2:0]s_axi_rready;
output [1:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output [0:0]m_axi_awvalid;
input [0:0]m_axi_awready;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output [0:0]m_axi_wlast;
output [0:0]m_axi_wvalid;
input [0:0]m_axi_wready;
input [1:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_bvalid;
output [0:0]m_axi_bready;
output [1:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output [0:0]m_axi_arvalid;
input [0:0]m_axi_arready;
input [1:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input [0:0]m_axi_rlast;
input [0:0]m_axi_rvalid;
output [0:0]m_axi_rready;
endmodule
|
// niosii.v
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module niosii (
input wire clk_clk, // clk.clk
output wire [7:0] pio_0_external_connection_export, // pio_0_external_connection.export
input wire reset_reset_n, // reset.reset_n
input wire uart_0_rxd, // uart_0.rxd
output wire uart_0_txd // .txd
);
wire [31:0] nios2_gen2_0_data_master_readdata; // mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata
wire nios2_gen2_0_data_master_waitrequest; // mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest
wire nios2_gen2_0_data_master_debugaccess; // nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess
wire [17:0] nios2_gen2_0_data_master_address; // nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address
wire [3:0] nios2_gen2_0_data_master_byteenable; // nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable
wire nios2_gen2_0_data_master_read; // nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read
wire nios2_gen2_0_data_master_write; // nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write
wire [31:0] nios2_gen2_0_data_master_writedata; // nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata
wire [31:0] nios2_gen2_0_instruction_master_readdata; // mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata
wire nios2_gen2_0_instruction_master_waitrequest; // mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest
wire [17:0] nios2_gen2_0_instruction_master_address; // nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address
wire nios2_gen2_0_instruction_master_read; // nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_chipselect -> jtag_uart_0:av_chipselect
wire [31:0] mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata; // jtag_uart_0:av_readdata -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_readdata
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest; // jtag_uart_0:av_waitrequest -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_waitrequest
wire [0:0] mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_address -> jtag_uart_0:av_address
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_read -> jtag_uart_0:av_read_n
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_write -> jtag_uart_0:av_write_n
wire [31:0] mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_writedata -> jtag_uart_0:av_writedata
wire [31:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata; // nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest; // nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess
wire [8:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read
wire [3:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write
wire [31:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata
wire mm_interconnect_0_onchip_memory2_0_s1_chipselect; // mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
wire [31:0] mm_interconnect_0_onchip_memory2_0_s1_readdata; // onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
wire [13:0] mm_interconnect_0_onchip_memory2_0_s1_address; // mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
wire [3:0] mm_interconnect_0_onchip_memory2_0_s1_byteenable; // mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
wire mm_interconnect_0_onchip_memory2_0_s1_write; // mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
wire [31:0] mm_interconnect_0_onchip_memory2_0_s1_writedata; // mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
wire mm_interconnect_0_onchip_memory2_0_s1_clken; // mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
wire mm_interconnect_0_pio_0_s1_chipselect; // mm_interconnect_0:pio_0_s1_chipselect -> pio_0:chipselect
wire [31:0] mm_interconnect_0_pio_0_s1_readdata; // pio_0:readdata -> mm_interconnect_0:pio_0_s1_readdata
wire [1:0] mm_interconnect_0_pio_0_s1_address; // mm_interconnect_0:pio_0_s1_address -> pio_0:address
wire mm_interconnect_0_pio_0_s1_write; // mm_interconnect_0:pio_0_s1_write -> pio_0:write_n
wire [31:0] mm_interconnect_0_pio_0_s1_writedata; // mm_interconnect_0:pio_0_s1_writedata -> pio_0:writedata
wire mm_interconnect_0_uart_0_s1_chipselect; // mm_interconnect_0:uart_0_s1_chipselect -> uart_0:chipselect
wire [15:0] mm_interconnect_0_uart_0_s1_readdata; // uart_0:readdata -> mm_interconnect_0:uart_0_s1_readdata
wire [2:0] mm_interconnect_0_uart_0_s1_address; // mm_interconnect_0:uart_0_s1_address -> uart_0:address
wire mm_interconnect_0_uart_0_s1_read; // mm_interconnect_0:uart_0_s1_read -> uart_0:read_n
wire mm_interconnect_0_uart_0_s1_begintransfer; // mm_interconnect_0:uart_0_s1_begintransfer -> uart_0:begintransfer
wire mm_interconnect_0_uart_0_s1_write; // mm_interconnect_0:uart_0_s1_write -> uart_0:write_n
wire [15:0] mm_interconnect_0_uart_0_s1_writedata; // mm_interconnect_0:uart_0_s1_writedata -> uart_0:writedata
wire irq_mapper_receiver0_irq; // jtag_uart_0:av_irq -> irq_mapper:receiver0_irq
wire irq_mapper_receiver1_irq; // uart_0:irq -> irq_mapper:receiver1_irq
wire [31:0] nios2_gen2_0_irq_irq; // irq_mapper:sender_irq -> nios2_gen2_0:irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [irq_mapper:reset, jtag_uart_0:rst_n, mm_interconnect_0:nios2_gen2_0_reset_reset_bridge_in_reset_reset, nios2_gen2_0:reset_n, onchip_memory2_0:reset, pio_0:reset_n, rst_translator:in_reset, uart_0:reset_n]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [nios2_gen2_0:reset_req, onchip_memory2_0:reset_req, rst_translator:reset_req_in]
niosii_jtag_uart_0 jtag_uart_0 (
.clk (clk_clk), // clk.clk
.rst_n (~rst_controller_reset_out_reset), // reset.reset_n
.av_chipselect (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect), // avalon_jtag_slave.chipselect
.av_address (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address), // .address
.av_read_n (~mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read), // .read_n
.av_readdata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata), // .readdata
.av_write_n (~mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write), // .write_n
.av_writedata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest), // .waitrequest
.av_irq (irq_mapper_receiver0_irq) // irq.irq
);
niosii_nios2_gen2_0 nios2_gen2_0 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.d_address (nios2_gen2_0_data_master_address), // data_master.address
.d_byteenable (nios2_gen2_0_data_master_byteenable), // .byteenable
.d_read (nios2_gen2_0_data_master_read), // .read
.d_readdata (nios2_gen2_0_data_master_readdata), // .readdata
.d_waitrequest (nios2_gen2_0_data_master_waitrequest), // .waitrequest
.d_write (nios2_gen2_0_data_master_write), // .write
.d_writedata (nios2_gen2_0_data_master_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (nios2_gen2_0_data_master_debugaccess), // .debugaccess
.i_address (nios2_gen2_0_instruction_master_address), // instruction_master.address
.i_read (nios2_gen2_0_instruction_master_read), // .read
.i_readdata (nios2_gen2_0_instruction_master_readdata), // .readdata
.i_waitrequest (nios2_gen2_0_instruction_master_waitrequest), // .waitrequest
.irq (nios2_gen2_0_irq_irq), // irq.irq
.debug_reset_request (), // debug_reset_request.reset
.debug_mem_slave_address (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read), // .read
.debug_mem_slave_readdata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write), // .write
.debug_mem_slave_writedata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata), // .writedata
.dummy_ci_port () // custom_instruction_master.readra
);
niosii_onchip_memory2_0 onchip_memory2_0 (
.clk (clk_clk), // clk1.clk
.address (mm_interconnect_0_onchip_memory2_0_s1_address), // s1.address
.clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset), // reset1.reset
.reset_req (rst_controller_reset_out_reset_req) // .reset_req
);
niosii_pio_0 pio_0 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_pio_0_s1_address), // s1.address
.write_n (~mm_interconnect_0_pio_0_s1_write), // .write_n
.writedata (mm_interconnect_0_pio_0_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_pio_0_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_pio_0_s1_readdata), // .readdata
.out_port (pio_0_external_connection_export) // external_connection.export
);
niosii_uart_0 uart_0 (
.clk (clk_clk), // clk.clk
.reset_n (~rst_controller_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_uart_0_s1_address), // s1.address
.begintransfer (mm_interconnect_0_uart_0_s1_begintransfer), // .begintransfer
.chipselect (mm_interconnect_0_uart_0_s1_chipselect), // .chipselect
.read_n (~mm_interconnect_0_uart_0_s1_read), // .read_n
.write_n (~mm_interconnect_0_uart_0_s1_write), // .write_n
.writedata (mm_interconnect_0_uart_0_s1_writedata), // .writedata
.readdata (mm_interconnect_0_uart_0_s1_readdata), // .readdata
.dataavailable (), // .dataavailable
.readyfordata (), // .readyfordata
.rxd (uart_0_rxd), // external_connection.export
.txd (uart_0_txd), // .export
.irq (irq_mapper_receiver1_irq) // irq.irq
);
niosii_mm_interconnect_0 mm_interconnect_0 (
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.nios2_gen2_0_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // nios2_gen2_0_reset_reset_bridge_in_reset.reset
.nios2_gen2_0_data_master_address (nios2_gen2_0_data_master_address), // nios2_gen2_0_data_master.address
.nios2_gen2_0_data_master_waitrequest (nios2_gen2_0_data_master_waitrequest), // .waitrequest
.nios2_gen2_0_data_master_byteenable (nios2_gen2_0_data_master_byteenable), // .byteenable
.nios2_gen2_0_data_master_read (nios2_gen2_0_data_master_read), // .read
.nios2_gen2_0_data_master_readdata (nios2_gen2_0_data_master_readdata), // .readdata
.nios2_gen2_0_data_master_write (nios2_gen2_0_data_master_write), // .write
.nios2_gen2_0_data_master_writedata (nios2_gen2_0_data_master_writedata), // .writedata
.nios2_gen2_0_data_master_debugaccess (nios2_gen2_0_data_master_debugaccess), // .debugaccess
.nios2_gen2_0_instruction_master_address (nios2_gen2_0_instruction_master_address), // nios2_gen2_0_instruction_master.address
.nios2_gen2_0_instruction_master_waitrequest (nios2_gen2_0_instruction_master_waitrequest), // .waitrequest
.nios2_gen2_0_instruction_master_read (nios2_gen2_0_instruction_master_read), // .read
.nios2_gen2_0_instruction_master_readdata (nios2_gen2_0_instruction_master_readdata), // .readdata
.jtag_uart_0_avalon_jtag_slave_address (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address), // jtag_uart_0_avalon_jtag_slave.address
.jtag_uart_0_avalon_jtag_slave_write (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write), // .write
.jtag_uart_0_avalon_jtag_slave_read (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read), // .read
.jtag_uart_0_avalon_jtag_slave_readdata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata), // .readdata
.jtag_uart_0_avalon_jtag_slave_writedata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata), // .writedata
.jtag_uart_0_avalon_jtag_slave_waitrequest (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest), // .waitrequest
.jtag_uart_0_avalon_jtag_slave_chipselect (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect), // .chipselect
.nios2_gen2_0_debug_mem_slave_address (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address), // nios2_gen2_0_debug_mem_slave.address
.nios2_gen2_0_debug_mem_slave_write (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write), // .write
.nios2_gen2_0_debug_mem_slave_read (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read), // .read
.nios2_gen2_0_debug_mem_slave_readdata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata), // .readdata
.nios2_gen2_0_debug_mem_slave_writedata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata), // .writedata
.nios2_gen2_0_debug_mem_slave_byteenable (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable), // .byteenable
.nios2_gen2_0_debug_mem_slave_waitrequest (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest), // .waitrequest
.nios2_gen2_0_debug_mem_slave_debugaccess (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess), // .debugaccess
.onchip_memory2_0_s1_address (mm_interconnect_0_onchip_memory2_0_s1_address), // onchip_memory2_0_s1.address
.onchip_memory2_0_s1_write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.onchip_memory2_0_s1_readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.onchip_memory2_0_s1_writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.onchip_memory2_0_s1_byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.onchip_memory2_0_s1_chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.onchip_memory2_0_s1_clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.pio_0_s1_address (mm_interconnect_0_pio_0_s1_address), // pio_0_s1.address
.pio_0_s1_write (mm_interconnect_0_pio_0_s1_write), // .write
.pio_0_s1_readdata (mm_interconnect_0_pio_0_s1_readdata), // .readdata
.pio_0_s1_writedata (mm_interconnect_0_pio_0_s1_writedata), // .writedata
.pio_0_s1_chipselect (mm_interconnect_0_pio_0_s1_chipselect), // .chipselect
.uart_0_s1_address (mm_interconnect_0_uart_0_s1_address), // uart_0_s1.address
.uart_0_s1_write (mm_interconnect_0_uart_0_s1_write), // .write
.uart_0_s1_read (mm_interconnect_0_uart_0_s1_read), // .read
.uart_0_s1_readdata (mm_interconnect_0_uart_0_s1_readdata), // .readdata
.uart_0_s1_writedata (mm_interconnect_0_uart_0_s1_writedata), // .writedata
.uart_0_s1_begintransfer (mm_interconnect_0_uart_0_s1_begintransfer), // .begintransfer
.uart_0_s1_chipselect (mm_interconnect_0_uart_0_s1_chipselect) // .chipselect
);
niosii_irq_mapper irq_mapper (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.receiver1_irq (irq_mapper_receiver1_irq), // receiver1.irq
.sender_irq (nios2_gen2_0_irq_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.58f
// \ \ Application: netgen
// / / Filename: lte_float32_float32_bool.v
// /___/ /\ Timestamp: Wed Jan 27 16:35:00 2016
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/jhegarty/lol/ipcore_dir/tmp/_cg/lte_float32_float32_bool.ngc /home/jhegarty/lol/ipcore_dir/tmp/_cg/lte_float32_float32_bool.v
// Device : 7z100ffg900-2
// Input file : /home/jhegarty/lol/ipcore_dir/tmp/_cg/lte_float32_float32_bool.ngc
// Output file : /home/jhegarty/lol/ipcore_dir/tmp/_cg/lte_float32_float32_bool.v
// # of Modules : 1
// Design Name : lte_float32_float32_bool
// Xilinx : /opt/Xilinx/14.5/ISE_DS/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
module lte_float32_float32_bool (
CLK, ce, inp, out
);
parameter INSTANCE_NAME="INST";
input wire CLK;
input wire ce;
input [63 : 0] inp;
output [0:0] out;
wire clk;
assign clk=CLK;
wire [31:0] a;
wire [31:0] b;
wire [0:0] result;
assign a = inp[31:0];
assign b = inp[63:32];
assign out = result;
wire \U0/op_inst/FLT_PT_OP/COMP_OP.SPD.OP/MET_REG/RTL.delay<0>_0 ;
wire sig00000001;
wire sig00000002;
wire sig00000003;
wire sig00000004;
wire sig00000005;
wire sig00000006;
wire sig00000007;
wire sig00000008;
wire sig00000009;
wire sig0000000a;
wire sig0000000b;
wire sig0000000c;
wire sig0000000d;
wire sig0000000e;
wire sig0000000f;
wire sig00000010;
wire sig00000011;
wire sig00000012;
wire sig00000013;
wire sig00000014;
wire sig00000015;
wire sig00000016;
wire sig00000017;
wire sig00000018;
wire sig00000019;
wire sig0000001a;
wire sig0000001b;
wire sig0000001c;
wire sig0000001d;
wire sig0000001e;
wire sig0000001f;
wire sig00000020;
wire sig00000021;
wire sig00000022;
wire sig00000023;
wire sig00000024;
wire sig00000025;
wire sig00000026;
wire sig00000027;
wire sig00000028;
wire sig00000029;
wire sig0000002a;
wire sig0000002b;
wire sig0000002c;
wire sig0000002d;
wire sig0000002e;
wire sig0000002f;
wire sig00000030;
wire sig00000031;
wire sig00000032;
wire sig00000033;
wire sig00000034;
wire sig00000035;
wire sig00000036;
wire sig00000037;
wire sig00000038;
wire sig00000039;
wire sig0000003a;
wire sig0000003b;
wire sig0000003c;
wire sig0000003d;
wire sig0000003e;
wire sig0000003f;
wire sig00000040;
wire sig00000041;
wire sig00000042;
wire sig00000043;
wire sig00000044;
wire sig00000045;
wire sig00000046;
wire sig00000047;
wire sig00000048;
wire sig00000049;
wire sig0000004a;
wire sig0000004b;
wire sig0000004c;
wire sig0000004d;
wire sig0000004e;
wire sig0000004f;
wire sig00000050;
wire sig00000051;
wire sig00000052;
wire sig00000053;
wire sig00000054;
wire sig00000055;
wire sig00000056;
wire sig00000057;
wire sig00000058;
wire sig00000059;
wire sig0000005a;
wire sig0000005b;
wire sig0000005c;
wire sig0000005d;
wire sig0000005e;
wire sig0000005f;
wire sig00000060;
wire sig00000061;
wire sig00000062;
wire sig00000063;
wire sig00000064;
wire sig00000065;
wire sig00000066;
wire sig00000067;
wire sig00000068;
wire sig00000069;
wire sig0000006a;
wire sig0000006b;
wire sig0000006c;
wire sig0000006d;
wire sig0000006e;
wire sig0000006f;
wire sig00000070;
assign
result[0] = \U0/op_inst/FLT_PT_OP/COMP_OP.SPD.OP/MET_REG/RTL.delay<0>_0 ;
VCC blk00000001 (
.P(sig00000001)
);
GND blk00000002 (
.G(sig00000002)
);
FDE #(
.INIT ( 1'b0 ))
blk00000003 (
.C(clk),
.CE(ce),
.D(sig00000006),
.Q(sig00000019)
);
MUXCY blk00000004 (
.CI(sig00000007),
.DI(sig00000002),
.S(sig00000003),
.O(sig00000006)
);
MUXCY blk00000005 (
.CI(sig00000008),
.DI(sig00000002),
.S(sig00000005),
.O(sig00000007)
);
MUXCY blk00000006 (
.CI(sig00000001),
.DI(sig00000002),
.S(sig00000004),
.O(sig00000008)
);
MUXCY blk00000007 (
.CI(sig00000016),
.DI(sig00000002),
.S(sig00000010),
.O(sig00000009)
);
MUXCY blk00000008 (
.CI(sig00000009),
.DI(sig00000002),
.S(sig0000000f),
.O(sig0000000a)
);
MUXCY blk00000009 (
.CI(sig00000018),
.DI(sig00000002),
.S(sig0000000e),
.O(sig0000000b)
);
MUXCY blk0000000a (
.CI(sig0000000b),
.DI(sig00000002),
.S(sig0000000d),
.O(sig0000000c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000000b (
.C(clk),
.CE(ce),
.D(sig00000012),
.Q(sig00000013)
);
FDE #(
.INIT ( 1'b0 ))
blk0000000c (
.C(clk),
.CE(ce),
.D(sig00000011),
.Q(\U0/op_inst/FLT_PT_OP/COMP_OP.SPD.OP/MET_REG/RTL.delay<0>_0 )
);
FDE #(
.INIT ( 1'b0 ))
blk0000000d (
.C(clk),
.CE(ce),
.D(sig0000000a),
.Q(sig00000015)
);
FDE #(
.INIT ( 1'b0 ))
blk0000000e (
.C(clk),
.CE(ce),
.D(sig0000000c),
.Q(sig00000017)
);
FDE #(
.INIT ( 1'b0 ))
blk0000000f (
.C(clk),
.CE(ce),
.D(sig00000001),
.Q(sig0000001a)
);
MUXCY blk00000010 (
.CI(sig00000028),
.DI(sig00000002),
.S(sig0000001c),
.O(sig00000027)
);
MUXCY blk00000011 (
.CI(sig00000029),
.DI(sig00000002),
.S(sig0000001d),
.O(sig00000028)
);
MUXCY blk00000012 (
.CI(sig0000002a),
.DI(sig00000002),
.S(sig0000001e),
.O(sig00000029)
);
MUXCY blk00000013 (
.CI(sig0000002b),
.DI(sig00000002),
.S(sig0000001f),
.O(sig0000002a)
);
MUXCY blk00000014 (
.CI(sig0000002c),
.DI(sig00000002),
.S(sig00000020),
.O(sig0000002b)
);
MUXCY blk00000015 (
.CI(sig0000002d),
.DI(sig00000002),
.S(sig00000021),
.O(sig0000002c)
);
MUXCY blk00000016 (
.CI(sig0000002e),
.DI(sig00000002),
.S(sig00000022),
.O(sig0000002d)
);
MUXCY blk00000017 (
.CI(sig0000002f),
.DI(sig00000002),
.S(sig00000023),
.O(sig0000002e)
);
MUXCY blk00000018 (
.CI(sig00000030),
.DI(sig00000002),
.S(sig00000024),
.O(sig0000002f)
);
MUXCY blk00000019 (
.CI(sig00000031),
.DI(sig00000002),
.S(sig00000025),
.O(sig00000030)
);
MUXCY blk0000001a (
.CI(sig00000001),
.DI(sig00000002),
.S(sig00000026),
.O(sig00000031)
);
FDE #(
.INIT ( 1'b0 ))
blk0000001b (
.C(clk),
.CE(ce),
.D(sig00000027),
.Q(sig0000001b)
);
MUXCY blk0000001c (
.CI(sig00000002),
.DI(sig00000001),
.S(sig00000037),
.O(sig00000032)
);
MUXCY blk0000001d (
.CI(sig00000032),
.DI(sig00000001),
.S(sig00000036),
.O(sig00000033)
);
MUXCY blk0000001e (
.CI(sig00000033),
.DI(sig00000001),
.S(sig00000035),
.O(sig00000034)
);
MUXCY blk0000001f (
.CI(sig00000034),
.DI(sig00000001),
.S(sig00000038),
.O(sig00000016)
);
MUXCY blk00000020 (
.CI(sig00000002),
.DI(sig00000001),
.S(sig0000003e),
.O(sig00000039)
);
MUXCY blk00000021 (
.CI(sig00000039),
.DI(sig00000001),
.S(sig0000003d),
.O(sig0000003a)
);
MUXCY blk00000022 (
.CI(sig0000003a),
.DI(sig00000001),
.S(sig0000003c),
.O(sig0000003b)
);
MUXCY blk00000023 (
.CI(sig0000003b),
.DI(sig00000001),
.S(sig0000003f),
.O(sig00000018)
);
MUXCY blk00000024 (
.CI(sig00000061),
.DI(sig00000040),
.S(sig00000041),
.O(sig00000060)
);
MUXCY blk00000025 (
.CI(sig00000062),
.DI(sig00000042),
.S(sig00000043),
.O(sig00000061)
);
MUXCY blk00000026 (
.CI(sig00000063),
.DI(sig00000044),
.S(sig00000045),
.O(sig00000062)
);
MUXCY blk00000027 (
.CI(sig00000064),
.DI(sig00000046),
.S(sig00000047),
.O(sig00000063)
);
MUXCY blk00000028 (
.CI(sig00000065),
.DI(sig00000048),
.S(sig00000049),
.O(sig00000064)
);
MUXCY blk00000029 (
.CI(sig00000066),
.DI(sig0000004a),
.S(sig0000004b),
.O(sig00000065)
);
MUXCY blk0000002a (
.CI(sig00000067),
.DI(sig0000004c),
.S(sig0000004d),
.O(sig00000066)
);
MUXCY blk0000002b (
.CI(sig00000068),
.DI(sig0000004e),
.S(sig0000004f),
.O(sig00000067)
);
MUXCY blk0000002c (
.CI(sig00000069),
.DI(sig00000050),
.S(sig00000051),
.O(sig00000068)
);
MUXCY blk0000002d (
.CI(sig0000006a),
.DI(sig00000052),
.S(sig00000053),
.O(sig00000069)
);
MUXCY blk0000002e (
.CI(sig0000006b),
.DI(sig00000054),
.S(sig00000055),
.O(sig0000006a)
);
MUXCY blk0000002f (
.CI(sig0000006c),
.DI(sig00000056),
.S(sig00000057),
.O(sig0000006b)
);
MUXCY blk00000030 (
.CI(sig0000006d),
.DI(sig00000058),
.S(sig00000059),
.O(sig0000006c)
);
MUXCY blk00000031 (
.CI(sig0000006e),
.DI(sig0000005a),
.S(sig0000005b),
.O(sig0000006d)
);
MUXCY blk00000032 (
.CI(sig0000006f),
.DI(sig0000005c),
.S(sig0000005d),
.O(sig0000006e)
);
MUXCY blk00000033 (
.CI(sig00000002),
.DI(sig0000005e),
.S(sig0000005f),
.O(sig0000006f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000034 (
.C(clk),
.CE(ce),
.D(sig00000060),
.Q(sig00000014)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk00000035 (
.I0(a[27]),
.I1(a[28]),
.I2(a[29]),
.I3(a[30]),
.O(sig00000003)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000036 (
.I0(b[23]),
.I1(b[24]),
.I2(b[25]),
.I3(b[26]),
.I4(b[27]),
.I5(b[28]),
.O(sig00000004)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000037 (
.I0(b[29]),
.I1(b[30]),
.I2(a[23]),
.I3(a[24]),
.I4(a[25]),
.I5(a[26]),
.O(sig00000005)
);
LUT2 #(
.INIT ( 4'h8 ))
blk00000038 (
.I0(a[29]),
.I1(a[30]),
.O(sig0000000d)
);
LUT6 #(
.INIT ( 64'h8000000000000000 ))
blk00000039 (
.I0(a[23]),
.I1(a[24]),
.I2(a[25]),
.I3(a[26]),
.I4(a[27]),
.I5(a[28]),
.O(sig0000000e)
);
LUT2 #(
.INIT ( 4'h8 ))
blk0000003a (
.I0(b[29]),
.I1(b[30]),
.O(sig0000000f)
);
LUT6 #(
.INIT ( 64'h8000000000000000 ))
blk0000003b (
.I0(b[23]),
.I1(b[24]),
.I2(b[25]),
.I3(b[26]),
.I4(b[27]),
.I5(b[28]),
.O(sig00000010)
);
LUT2 #(
.INIT ( 4'h8 ))
blk0000003c (
.I0(a[31]),
.I1(b[31]),
.O(sig00000012)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk0000003d (
.I0(a[27]),
.I1(b[27]),
.I2(a[29]),
.I3(b[29]),
.I4(a[28]),
.I5(b[28]),
.O(sig0000001d)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk0000003e (
.I0(a[24]),
.I1(b[24]),
.I2(a[26]),
.I3(b[26]),
.I4(a[25]),
.I5(b[25]),
.O(sig0000001e)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk0000003f (
.I0(a[21]),
.I1(b[21]),
.I2(a[23]),
.I3(b[23]),
.I4(a[22]),
.I5(b[22]),
.O(sig0000001f)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000040 (
.I0(a[18]),
.I1(b[18]),
.I2(a[20]),
.I3(b[20]),
.I4(a[19]),
.I5(b[19]),
.O(sig00000020)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000041 (
.I0(a[15]),
.I1(b[15]),
.I2(a[17]),
.I3(b[17]),
.I4(a[16]),
.I5(b[16]),
.O(sig00000021)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000042 (
.I0(a[12]),
.I1(b[12]),
.I2(a[14]),
.I3(b[14]),
.I4(a[13]),
.I5(b[13]),
.O(sig00000022)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000043 (
.I0(a[10]),
.I1(b[10]),
.I2(a[9]),
.I3(b[9]),
.I4(a[11]),
.I5(b[11]),
.O(sig00000023)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000044 (
.I0(a[6]),
.I1(b[6]),
.I2(a[8]),
.I3(b[8]),
.I4(a[7]),
.I5(b[7]),
.O(sig00000024)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000045 (
.I0(a[3]),
.I1(b[3]),
.I2(a[5]),
.I3(b[5]),
.I4(a[4]),
.I5(b[4]),
.O(sig00000025)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000046 (
.I0(a[31]),
.I1(b[31]),
.I2(a[30]),
.I3(b[30]),
.O(sig0000001c)
);
LUT6 #(
.INIT ( 64'h9009000000009009 ))
blk00000047 (
.I0(a[0]),
.I1(b[0]),
.I2(a[2]),
.I3(b[2]),
.I4(a[1]),
.I5(b[1]),
.O(sig00000026)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000048 (
.I0(b[12]),
.I1(b[13]),
.I2(b[14]),
.I3(b[15]),
.I4(b[16]),
.I5(b[17]),
.O(sig00000035)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000049 (
.I0(b[6]),
.I1(b[7]),
.I2(b[8]),
.I3(b[9]),
.I4(b[10]),
.I5(b[11]),
.O(sig00000036)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000004a (
.I0(b[0]),
.I1(b[1]),
.I2(b[2]),
.I3(b[3]),
.I4(b[4]),
.I5(b[5]),
.O(sig00000037)
);
LUT5 #(
.INIT ( 32'h00000001 ))
blk0000004b (
.I0(b[18]),
.I1(b[19]),
.I2(b[20]),
.I3(b[21]),
.I4(b[22]),
.O(sig00000038)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000004c (
.I0(a[12]),
.I1(a[13]),
.I2(a[14]),
.I3(a[15]),
.I4(a[16]),
.I5(a[17]),
.O(sig0000003c)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000004d (
.I0(a[6]),
.I1(a[7]),
.I2(a[8]),
.I3(a[9]),
.I4(a[10]),
.I5(a[11]),
.O(sig0000003d)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000004e (
.I0(a[0]),
.I1(a[1]),
.I2(a[2]),
.I3(a[3]),
.I4(a[4]),
.I5(a[5]),
.O(sig0000003e)
);
LUT5 #(
.INIT ( 32'h00000001 ))
blk0000004f (
.I0(a[18]),
.I1(a[19]),
.I2(a[20]),
.I3(a[21]),
.I4(a[22]),
.O(sig0000003f)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000050 (
.I0(a[19]),
.I1(b[19]),
.I2(a[18]),
.I3(b[18]),
.O(sig0000004d)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000051 (
.I0(a[17]),
.I1(b[17]),
.I2(a[16]),
.I3(b[16]),
.O(sig0000004f)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000052 (
.I0(a[15]),
.I1(b[15]),
.I2(a[14]),
.I3(b[14]),
.O(sig00000051)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000053 (
.I0(a[13]),
.I1(b[13]),
.I2(a[12]),
.I3(b[12]),
.O(sig00000053)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000054 (
.I0(a[11]),
.I1(b[11]),
.I2(a[10]),
.I3(b[10]),
.O(sig00000055)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000055 (
.I0(a[9]),
.I1(b[9]),
.I2(a[8]),
.I3(b[8]),
.O(sig00000057)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000056 (
.I0(a[7]),
.I1(b[7]),
.I2(a[6]),
.I3(b[6]),
.O(sig00000059)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000057 (
.I0(a[5]),
.I1(b[5]),
.I2(a[4]),
.I3(b[4]),
.O(sig0000005b)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000058 (
.I0(a[3]),
.I1(b[3]),
.I2(a[2]),
.I3(b[2]),
.O(sig0000005d)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk00000059 (
.I0(a[31]),
.I1(b[31]),
.I2(a[30]),
.I3(b[30]),
.O(sig00000041)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000005a (
.I0(a[29]),
.I1(b[29]),
.I2(a[28]),
.I3(b[28]),
.O(sig00000043)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000005b (
.I0(a[27]),
.I1(b[27]),
.I2(a[26]),
.I3(b[26]),
.O(sig00000045)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000005c (
.I0(a[25]),
.I1(b[25]),
.I2(a[24]),
.I3(b[24]),
.O(sig00000047)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000005d (
.I0(a[23]),
.I1(b[23]),
.I2(a[22]),
.I3(b[22]),
.O(sig00000049)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000005e (
.I0(a[21]),
.I1(b[21]),
.I2(a[20]),
.I3(b[20]),
.O(sig0000004b)
);
LUT4 #(
.INIT ( 16'h9009 ))
blk0000005f (
.I0(a[1]),
.I1(b[1]),
.I2(a[0]),
.I3(b[0]),
.O(sig0000005f)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk00000060 (
.I0(a[31]),
.I1(b[31]),
.I2(a[30]),
.I3(b[30]),
.O(sig00000040)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk00000061 (
.I0(b[29]),
.I1(a[29]),
.I2(a[28]),
.I3(b[28]),
.O(sig00000042)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk00000062 (
.I0(b[27]),
.I1(a[27]),
.I2(a[26]),
.I3(b[26]),
.O(sig00000044)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk00000063 (
.I0(b[25]),
.I1(a[25]),
.I2(a[24]),
.I3(b[24]),
.O(sig00000046)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk00000064 (
.I0(b[23]),
.I1(a[23]),
.I2(a[22]),
.I3(b[22]),
.O(sig00000048)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk00000065 (
.I0(b[21]),
.I1(a[21]),
.I2(a[20]),
.I3(b[20]),
.O(sig0000004a)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk00000066 (
.I0(b[19]),
.I1(a[19]),
.I2(a[18]),
.I3(b[18]),
.O(sig0000004c)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk00000067 (
.I0(b[17]),
.I1(a[17]),
.I2(a[16]),
.I3(b[16]),
.O(sig0000004e)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk00000068 (
.I0(b[15]),
.I1(a[15]),
.I2(a[14]),
.I3(b[14]),
.O(sig00000050)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk00000069 (
.I0(b[13]),
.I1(a[13]),
.I2(a[12]),
.I3(b[12]),
.O(sig00000052)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk0000006a (
.I0(b[11]),
.I1(a[11]),
.I2(a[10]),
.I3(b[10]),
.O(sig00000054)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk0000006b (
.I0(b[9]),
.I1(a[9]),
.I2(a[8]),
.I3(b[8]),
.O(sig00000056)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk0000006c (
.I0(b[7]),
.I1(a[7]),
.I2(a[6]),
.I3(b[6]),
.O(sig00000058)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk0000006d (
.I0(b[5]),
.I1(a[5]),
.I2(a[4]),
.I3(b[4]),
.O(sig0000005a)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk0000006e (
.I0(b[3]),
.I1(a[3]),
.I2(a[2]),
.I3(b[2]),
.O(sig0000005c)
);
LUT4 #(
.INIT ( 16'h44D4 ))
blk0000006f (
.I0(b[1]),
.I1(a[1]),
.I2(a[0]),
.I3(b[0]),
.O(sig0000005e)
);
LUT2 #(
.INIT ( 4'h1 ))
blk00000070 (
.I0(sig00000015),
.I1(sig00000017),
.O(sig00000070)
);
LUT6 #(
.INIT ( 64'hFAEF00000000FFFF ))
blk00000071 (
.I0(sig00000019),
.I1(sig0000001b),
.I2(sig00000013),
.I3(sig00000014),
.I4(sig0000001a),
.I5(sig00000070),
.O(sig00000011)
);
endmodule
|
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-1-2017
*/
module jt12_kon(
input rst,
input clk,
input clk_en /* synthesis direct_enable */,
input [3:0] keyon_op,
input [2:0] keyon_ch,
input [1:0] next_op,
input [2:0] next_ch,
input up_keyon,
input csm,
// input flag_A,
input overflow_A,
output reg keyon_I
);
parameter num_ch=6;
wire csr_out;
generate
if(num_ch==6) begin
// capture overflow signal so it lasts long enough
reg overflow2;
reg [4:0] overflow_cycle;
always @(posedge clk) if( clk_en ) begin
if(overflow_A) begin
overflow2 <= 1'b1;
overflow_cycle <= { next_op, next_ch };
end else begin
if(overflow_cycle == {next_op, next_ch}) overflow2<=1'b0;
end
end
always @(posedge clk) if( clk_en )
keyon_I <= (csm&&next_ch==3'd2&&overflow2) || csr_out;
reg up_keyon_reg;
reg [3:0] tkeyon_op;
reg [2:0] tkeyon_ch;
wire key_upnow;
assign key_upnow = up_keyon_reg && (tkeyon_ch==next_ch) && (next_op == 2'd3);
always @(posedge clk) if( clk_en ) begin
if (rst)
up_keyon_reg <= 1'b0;
if (up_keyon) begin
up_keyon_reg <= 1'b1;
tkeyon_op <= keyon_op;
tkeyon_ch <= keyon_ch; end
else if (key_upnow)
up_keyon_reg <= 1'b0;
end
wire middle1;
wire middle2;
wire middle3;
wire din = key_upnow ? tkeyon_op[3] : csr_out;
wire mid_din2 = key_upnow ? tkeyon_op[1] : middle1;
wire mid_din3 = key_upnow ? tkeyon_op[2] : middle2;
wire mid_din4 = key_upnow ? tkeyon_op[0] : middle3;
jt12_sh_rst #(.width(1),.stages(6),.rstval(1'b0)) u_konch0(
.clk ( clk ),
.clk_en ( clk_en ),
.rst ( rst ),
.din ( din ),
.drop ( middle1 )
);
jt12_sh_rst #(.width(1),.stages(6),.rstval(1'b0)) u_konch1(
.clk ( clk ),
.clk_en ( clk_en ),
.rst ( rst ),
.din ( mid_din2 ),
.drop ( middle2 )
);
jt12_sh_rst #(.width(1),.stages(6),.rstval(1'b0)) u_konch2(
.clk ( clk ),
.clk_en ( clk_en ),
.rst ( rst ),
.din ( mid_din3 ),
.drop ( middle3 )
);
jt12_sh_rst #(.width(1),.stages(6),.rstval(1'b0)) u_konch3(
.clk ( clk ),
.clk_en ( clk_en ),
.rst ( rst ),
.din ( mid_din4 ),
.drop ( csr_out )
);
end
else begin // 3 channels
reg din;
reg [3:0] next_op_hot;
always @(*) begin
case( next_op )
2'd0: next_op_hot = 4'b0001; // S1
2'd1: next_op_hot = 4'b0100; // S3
2'd2: next_op_hot = 4'b0010; // S2
2'd3: next_op_hot = 4'b1000; // S4
endcase
din = keyon_ch[1:0]==next_ch[1:0] && up_keyon ? |(keyon_op&next_op_hot) : csr_out;
end
always @(posedge clk) if( clk_en )
keyon_I <= csr_out; // No CSM for YM2203
jt12_sh_rst #(.width(1),.stages(12),.rstval(1'b0)) u_konch1(
.clk ( clk ),
.clk_en ( clk_en ),
.rst ( rst ),
.din ( din ),
.drop ( csr_out )
);
end
endgenerate
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: PLL1.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altpll bandwidth_type="AUTO" clk0_divide_by=25 clk0_duty_cycle=50 clk0_multiply_by=27 clk0_phase_shift="0" clk1_divide_by=25 clk1_duty_cycle=50 clk1_multiply_by=27 clk1_phase_shift="3805" clk2_divide_by=4000 clk2_duty_cycle=50 clk2_multiply_by=1007 clk2_phase_shift="0" compensate_clock="CLK0" device_family="Cyclone III" inclk0_input_frequency=10000 intended_device_family="Cyclone III" lpm_hint="CBX_MODULE_PREFIX=PLL1" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_USED" port_clk2="PORT_USED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 clk inclk
//VERSION_BEGIN 13.1 cbx_altclkbuf 2013:10:17:09:48:19:SJ cbx_altiobuf_bidir 2013:10:17:09:48:19:SJ cbx_altiobuf_in 2013:10:17:09:48:19:SJ cbx_altiobuf_out 2013:10:17:09:48:19:SJ cbx_altpll 2013:10:17:09:48:19:SJ cbx_cycloneii 2013:10:17:09:48:19:SJ cbx_lpm_add_sub 2013:10:17:09:48:19:SJ cbx_lpm_compare 2013:10:17:09:48:19:SJ cbx_lpm_counter 2013:10:17:09:48:19:SJ cbx_lpm_decode 2013:10:17:09:48:19:SJ cbx_lpm_mux 2013:10:17:09:48:19:SJ cbx_mgl 2013:10:17:09:48:49:SJ cbx_stratix 2013:10:17:09:48:19:SJ cbx_stratixii 2013:10:17:09:48:19:SJ cbx_stratixiii 2013:10:17:09:48:19:SJ cbx_stratixv 2013:10:17:09:48:19:SJ cbx_util_mgl 2013:10:17:09:48:19:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = cycloneiii_pll 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module PLL1_altpll
(
clk,
inclk) /* synthesis synthesis_clearbox=1 */;
output [4:0] clk;
input [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [1:0] inclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [4:0] wire_pll1_clk;
wire wire_pll1_fbout;
cycloneiii_pll pll1
(
.activeclock(),
.clk(wire_pll1_clk),
.clkbad(),
.fbin(wire_pll1_fbout),
.fbout(wire_pll1_fbout),
.inclk(inclk),
.locked(),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll1.bandwidth_type = "auto",
pll1.clk0_divide_by = 25,
pll1.clk0_duty_cycle = 50,
pll1.clk0_multiply_by = 27,
pll1.clk0_phase_shift = "0",
pll1.clk1_divide_by = 25,
pll1.clk1_duty_cycle = 50,
pll1.clk1_multiply_by = 27,
pll1.clk1_phase_shift = "3805",
pll1.clk2_divide_by = 4000,
pll1.clk2_duty_cycle = 50,
pll1.clk2_multiply_by = 1007,
pll1.clk2_phase_shift = "0",
pll1.compensate_clock = "clk0",
pll1.inclk0_input_frequency = 10000,
pll1.operation_mode = "normal",
pll1.pll_type = "auto",
pll1.lpm_type = "cycloneiii_pll";
assign
clk = {wire_pll1_clk[4:0]};
endmodule //PLL1_altpll
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module PLL1 (
inclk0,
c0,
c1,
c2)/* synthesis synthesis_clearbox = 1 */;
input inclk0;
output c0;
output c1;
output c2;
wire [4:0] sub_wire0;
wire [0:0] sub_wire6 = 1'h0;
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [0:0] sub_wire2 = sub_wire0[0:0];
wire [1:1] sub_wire1 = sub_wire0[1:1];
wire c1 = sub_wire1;
wire c0 = sub_wire2;
wire c2 = sub_wire3;
wire sub_wire4 = inclk0;
wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
PLL1_altpll PLL1_altpll_component (
.inclk (sub_wire5),
.clk (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "25"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "108.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "108.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.174999"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "33"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "108.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "108.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "25.17500000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "147.94411800"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "PLL1.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "1"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "25"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "27"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "25"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "27"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "3805"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "4000"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1007"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "10000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL1.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL1.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL1_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL1_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL PLL1_syn.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
//-----------------------------------------------------------------------------
// ISO14443-A support for the Proxmark III
// Gerhard de Koning Gans, April 2008
//-----------------------------------------------------------------------------
// constants for the different modes:
`define MASTER 3'b000
`define SLAVE 3'b001
`define DELAY 3'b010
module relay_test(
pck0, ck_1356meg, ck_1356megb,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
data_in, data_out,
mod_type
);
input pck0, ck_1356meg, ck_1356megb;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input data_in;
output data_out;
input [2:0] mod_type;
reg ssp_clk = 1'b0;
reg ssp_frame = 1'b0;
reg data_out = 1'b0;
reg ssp_din = 1'b0;
reg [6:0] div_counter = 7'b0;
reg [0:0] buf_data_in = 1'b0;
reg [0:0] receive_counter = 1'b0;
reg [31:0] delay_counter = 32'h0;
reg [3:0] counter = 4'b0;
reg [7:0] receive_buffer = 8'b0;
reg sending_started = 1'b0;
reg received_complete = 1'b0;
reg [7:0] received = 8'b0;
reg [3:0] send_buf = 4'b0;
reg [16:0] to_arm_delay = 17'b0;
always @(posedge ck_1356meg)
begin
/*div_counter <= div_counter + 1;
buf_data_in = data_in;
if (div_counter[3:0] == 4'b1000) ssp_clk <= 1'b0;
if (div_counter[3:0] == 4'b0000) ssp_clk <= 1'b1;
if (sending_started == 1'b1 && received_complete == 1'b0) begin
delay_counter = delay_counter + 1;
end
if (div_counter[2:0] == 3'b100) // 1.695MHz
begin
if (mod_type == `MASTER) // Sending from ARM to other Proxmark
begin
receive_counter <= receive_counter + 1;
if (div_counter[6:4] == 3'b000) ssp_frame = 1'b1;
else ssp_frame = 1'b0;
if (receive_counter[0] == 1'b0) begin
data_out = ssp_dout;
send_buf = {send_buf[2:0], ssp_dout};
receive_buffer = {receive_buffer[6:0], buf_data_in};
if (send_buf == 4'ha && sending_started == 1'b0) begin
delay_counter = 32'b0;
sending_started = 1'b1;
end
if (receive_buffer[3:0] == 4'ha && sending_started == 1'b1) begin
receive_buffer = 8'b0;
received_complete = 1'b1;
end
end
counter <= 4'b0;
end
else if (mod_type == `SLAVE) // Sending from other Proxmark to ARM
begin
counter <= counter + 1;
if (counter[0] == 1'b0) begin
receive_buffer = {receive_buffer[6:0], buf_data_in};
data_out = buf_data_in;
ssp_frame = (receive_buffer[7:4] == 4'b1111);
if (receive_buffer[7:4] == 4'b1111) begin
received = receive_buffer;
receive_buffer = 8'b0;
end
ssp_din <= received[7];
received = {received[6:0], 1'b0};
end
receive_counter <= 4'b0;
end
else if (mod_type == `DELAY) // Sending delay to ARM
begin
if (to_arm_delay[16] == 1'b1) begin
sending_started = 1'b0;
received_complete = 1'b0;
counter <= counter + 1;
if (counter[0] == 1'b0) begin
ssp_frame = (counter[3:0] == 4'b0000);
ssp_din <= delay_counter[31];
delay_counter = {delay_counter[30:0], 1'b0};
end
if (counter[3:0] == 4'b1111) begin
to_arm_delay <= 17'b0;
end
end
else begin
to_arm_delay <= to_arm_delay + 1;
end
end
end*/
end
endmodule |
//==================================================================================================
// Filename : rst_generator.v
// Created On : 2015-01-07 21:29:23
// Last Modified : 2015-05-24 23:16:08
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email : [email protected]
//
// Description : Debounce and synchronize the reset input signal.
// The module use a 7-bit counter.
//==================================================================================================
module rst_generator(
input clk, // input clock
input rst_i, // external reset
output reg rst_o // internal reset
);
//--------------------------------------------------------------------------
// registers
//--------------------------------------------------------------------------
reg [6:0] counter_r;
reg rst_i_sync_0;
reg rst_i_sync_1;
//--------------------------------------------------------------------------
// Initialization
//--------------------------------------------------------------------------
initial begin
rst_o <= 1'b0;
counter_r <= 7'b0;
end
//--------------------------------------------------------------------------
// state machine
//--------------------------------------------------------------------------
always @(posedge clk) begin
// sync the input
rst_i_sync_0 <= rst_i;
rst_i_sync_1 <= rst_i_sync_0;
// Wait until stable input.
if (rst_o != rst_i_sync_1) begin
counter_r <= counter_r + 7'b1;
end
else begin
counter_r <= 7'b0;
end
// Timeout: input signal is stable. Change output.
if (counter_r == 7'h7F) begin
rst_o <= ~rst_o;
end
else begin
rst_o <= rst_o;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__LSBUFHV2HV_HL_TB_V
`define SKY130_FD_SC_HVL__LSBUFHV2HV_HL_TB_V
/**
* lsbufhv2hv_hl: Level shifting buffer, High Voltage to High Voltage,
* Higher Voltage to Lower Voltage.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__lsbufhv2hv_hl.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg LOWHVPWR;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
LOWHVPWR = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 LOWHVPWR = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 LOWHVPWR = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 LOWHVPWR = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 LOWHVPWR = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 LOWHVPWR = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hvl__lsbufhv2hv_hl dut (.A(A), .VPWR(VPWR), .VGND(VGND), .LOWHVPWR(LOWHVPWR), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__LSBUFHV2HV_HL_TB_V
|
`timescale 1ns / 1ps
`define intN 8
`define addrN 8
`include "primitives.v"
`include "io_stream_read_write_array.v"
`include "array.v"
module io_stream_read_write_array_tb;
localparam N = 255;
`wire(Array, (`addrN, `intN), arr);
wire `intT res;
integer write_seed = 21;
integer read_seed = 42;
`reg(stream, `intN, sRA);
`wire(stream, `intN, sR);
`reg(stream, `intN, sWA);
`reg(stream, `intN, sW);
`wire(stream, 1, sB);
reg `intT sRA_next;
assign sR_ready = out_ready;
assign sB_ready = out_ready;
`testbench(io_stream_read_write_array_tb, 1000)
array #(.N(N))
array(.clk(clk),
`out(Array, 0, arr));
`in_ready(inst);
`inst_sync(io_stream_read_write_array, inst, #())(
`sync(in_valid, out_ready),
`in(Array, 0, arr),
`in(stream, 1, sRA),
`in(stream, 2, sWA),
`in(stream, 3, sW),
`out(stream, 0, sR),
`out(null_stream, 1, sB));
reg `addrT i;
initial begin
sRA = 0;
sRA_next = 0;
sRA_valid = `true;
sWA = 0;
sWA_valid = `false;
sW = 0;
sW_valid = `false;
`start;
// write some data
for(i = 0; i < N; i = i + 1) begin
sWA = i;
sWA_valid = `true;
sW = (i * 7) & 8'h7f;
sW_valid = `true;
`wait_for(sWA_ready && sW_ready);
if($random(write_seed) & 1) begin
sWA_valid = `false;
sW_valid = `false;
@(posedge clk);
sWA_valid = `true;
sW_valid = `true;
end
end
sWA_valid = `false;
sW_valid = `false;
sWA = N;
`wait_for(sRA == N-1 && sR_valid);
nrst = `false;
#2;
$display("done");
$finish;
end
always @(posedge clk) begin
if(sRA_ready) begin
if(sRA_next < sWA & ($random(read_seed) & 1)) begin
sRA <= sRA_next;
sRA_next <= sRA_next + 1;
end
end
if(sR_valid & sR != ((sRA * 7) & 8'h7f))
$display("MISMATCH arr(%d) = %d", sRA, sR);
end
endmodule // io_stream_read_write_array_tb
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__BUFINV_SYMBOL_V
`define SKY130_FD_SC_MS__BUFINV_SYMBOL_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__bufinv (
//# {{data|Data Signals}}
input A,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__BUFINV_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_HVL__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
/**
* udp_dlatch$P_pp$PG$N: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__udp_dlatch$P_pp$PG$N (
Q ,
D ,
GATE ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input GATE ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_DLATCH_P_PP_PG_N_BLACKBOX_V
|
/* This file is part of JT51.
JT51 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT51 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT51. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 27-10-2016
*/
`timescale 1ns / 1ps
module jt51_reg(
input rst,
input clk, // P1
input [7:0] d_in,
input up_rl,
input up_kc,
input up_kf,
input up_pms,
input up_dt1,
input up_tl,
input up_ks,
input up_amsen,
input up_dt2,
input up_d1l,
input up_keyon,
input [1:0] op, // operator to update
input [2:0] ch, // channel to update
input csm,
input overflow_A,
output reg busy,
output [1:0] rl_I,
output [2:0] fb_II,
output [2:0] con_I,
output [6:0] kc_I,
output [5:0] kf_I,
output [2:0] pms_I,
output [1:0] ams_VII,
output [2:0] dt1_II,
output [3:0] mul_VI,
output [6:0] tl_VII,
output [1:0] ks_III,
output amsen_VII,
output [4:0] arate_II,
output [4:0] rate1_II,
output [4:0] rate2_II,
output [3:0] rrate_II,
output [1:0] dt2_I,
output [3:0] d1l_I,
output keyon_II,
// Pipeline order
output reg zero,
output reg m1_enters,
output reg m2_enters,
output reg c1_enters,
output reg c2_enters,
// Operator
output use_prevprev1,
output use_internal_x,
output use_internal_y,
output use_prev2,
output use_prev1,
output [1:0] cur_op,
output reg op31_no,
output reg op31_acc
);
reg kon, koff;
reg [1:0] csm_state;
reg [4:0] csm_cnt;
wire csm_kon = csm_state[0];
wire csm_koff = csm_state[1];
always @(*) begin
m1_enters = cur_op == 2'b00;
m2_enters = cur_op == 2'b01;
c1_enters = cur_op == 2'b10;
c2_enters = cur_op == 2'b11;
end
wire [1:0] rl_in = d_in[7:6];
wire [2:0] fb_in = d_in[5:3];
wire [2:0] con_in = d_in[2:0];
wire [6:0] kc_in = d_in[6:0];
wire [5:0] kf_in = d_in[7:2];
wire [2:0] pms_in = d_in[6:4];
wire [1:0] ams_in = d_in[1:0];
wire [2:0] dt1_in = d_in[6:4];
wire [3:0] mul_in = d_in[3:0];
wire [6:0] tl_in = d_in[6:0];
wire [1:0] ks_in = d_in[7:6];
wire [4:0] ar_in = d_in[4:0];
wire amsen_in= d_in[7];
wire [4:0] d1r_in = d_in[4:0];
wire [1:0] dt2_in = d_in[7:6];
wire [4:0] d2r_in = d_in[4:0];
wire [3:0] d1l_in = d_in[7:4];
wire [3:0] rr_in = d_in[3:0];
wire up = up_rl | up_kc | up_kf | up_pms | up_dt1 | up_tl |
up_ks | up_amsen | up_dt2 | up_d1l | up_keyon;
reg [4:0] cur;
always @(posedge clk) begin
op31_no <= cur == 5'o10;
op31_acc <= cur == 5'o16;
end
assign cur_op = cur[4:3];
wire [4:0] req_I = { op, ch };
wire [4:0] req_II = req_I + 5'd1;
wire [4:0] req_III = req_II + 5'd1;
wire [4:0] req_IV = req_III + 5'd1;
wire [4:0] req_V = req_IV + 5'd1;
wire [4:0] req_VI = req_V + 5'd1;
wire [4:0] req_VII = req_VI + 5'd1;
wire update_op_I = cur == req_I;
wire update_op_II = cur == req_II;
wire update_op_III = cur == req_III;
wire update_op_IV = cur == req_IV;
wire update_op_V = cur == req_V;
wire update_op_VI = cur == req_VI;
wire update_op_VII = cur == req_VII;
wire up_rl_ch = up_rl & update_op_I;
wire up_fb_ch = up_rl & update_op_II;
wire up_con_ch = up_rl & update_op_I;
wire up_kc_ch = up_kc & update_op_I;
wire up_kf_ch = up_kf & update_op_I;
wire up_pms_ch = up_pms & update_op_I;
wire up_ams_ch = up_pms & update_op_VII;
wire up_dt1_op = up_dt1 & update_op_II; // DT1, MUL
wire up_mul_op = up_dt1 & update_op_VI; // DT1, MUL
wire up_tl_op = up_tl & update_op_VII;
wire up_ks_op = up_ks & update_op_III; // KS, AR
wire up_amsen_op= up_amsen & update_op_VII; // AMS-EN, D1R
wire up_dt2_op = up_dt2 & update_op_I; // DT2, D2R
wire up_d1l_op = up_d1l & update_op_I; // D1L, RR
wire up_ar_op = up_ks & update_op_II; // KS, AR
wire up_d1r_op = up_amsen & update_op_II; // AMS-EN, D1R
wire up_d2r_op = up_dt2 & update_op_II; // DT2, D2R
wire up_rr_op = up_d1l & update_op_II; // D1L, RR
wire [4:0] next = cur+5'd1;
always @(posedge clk) begin : up_counter
if( rst ) begin
cur <= 5'h0;
zero <= 1'b0;
busy <= 1'b0;
end
else begin
cur <= next;
zero <= next== 5'd0;
if( &cur ) busy <= up && !busy;
end
end
wire [2:0] cur_ch = cur[2:0];
wire [3:0] keyon_op = d_in[6:3];
wire [2:0] keyon_ch = d_in[2:0];
jt51_kon u_kon (
.rst (rst ),
.clk (clk ),
.keyon_op (keyon_op ),
.keyon_ch (keyon_ch ),
.cur_op (cur_op ),
.cur_ch (cur_ch ),
.up_keyon (up_keyon && busy ),
.csm (csm ),
.overflow_A(overflow_A),
.keyon_II (keyon_II )
);
jt51_mod u_mod(
.alg_I ( con_I ),
.m1_enters ( m1_enters ),
.m2_enters ( m2_enters ),
.c1_enters ( c1_enters ),
.c2_enters ( c2_enters ),
.use_prevprev1 ( use_prevprev1 ),
.use_internal_x( use_internal_x ),
.use_internal_y( use_internal_y ),
.use_prev2 ( use_prev2 ),
.use_prev1 ( use_prev1 )
);
// memory for OP registers
localparam opreg_w = 42;
reg [opreg_w-1:0] reg_op[31:0];
reg [opreg_w-1:0] reg_out;
integer i;
initial
begin
for (i=0; i<32; i=i+1)
begin
reg_op[i] = ~0;
end
end
assign { dt1_II, mul_VI, tl_VII, ks_III, amsen_VII,
dt2_I, d1l_I, arate_II, rate1_II, rate2_II, rrate_II } = reg_out;
wire [opreg_w-1:0] reg_in = {
up_dt1_op ? dt1_in : dt1_II, // 3
up_mul_op ? mul_in : mul_VI, // 4
up_tl_op ? tl_in : tl_VII, // 7
up_ks_op ? ks_in : ks_III, // 2
up_amsen_op ? amsen_in : amsen_VII, // 1
up_dt2_op ? dt2_in : dt2_I, // 2
up_d1l_op ? d1l_in : d1l_I, // 4
up_ar_op ? ar_in : arate_II, // 5
up_d1r_op ? d1r_in : rate1_II, // 5
up_d2r_op ? d2r_in : rate2_II, // 5
up_rr_op ? rr_in : rrate_II }; // 4
// wire opdata_wr = |{ up_dt1_op, up_mul_op, up_tl_op, up_ks_op, up_amsen_op,
// up_dt2_op, up_d1l_op, up_ar_op , up_d1r_op, up_d2r_op, up_rr_op };
always @(posedge clk) begin
reg_out <= reg_op[next];
if( busy )
reg_op[cur] <= reg_in;
end
// memory for CH registers
localparam chreg_w = 26;
reg [chreg_w-1:0] reg_ch[7:0];
reg [chreg_w-1:0] reg_ch_out;
wire [chreg_w-1:0] reg_ch_in = {
up_rl_ch ? rl_in : rl_I,
up_fb_ch ? fb_in : fb_II,
up_con_ch ? con_in : con_I,
up_kc_ch ? kc_in : kc_I,
up_kf_ch ? kf_in : kf_I,
up_ams_ch ? ams_in : ams_VII,
up_pms_ch ? pms_in : pms_I };
assign { rl_I, fb_II, con_I, kc_I, kf_I, ams_VII, pms_I } = reg_ch_out;
wire [2:0] next_ch = next[2:0];
// wire chdata_wr = |{ up_rl_ch, up_fb_ch, up_con_ch, up_kc_ch, up_kf_ch, up_ams_ch, up_pms_ch };
always @(posedge clk) begin
reg_ch_out <= reg_ch[next_ch];
if( busy )
reg_ch[cur_ch] <= reg_ch_in;
end
`ifdef SIMULATION
/* verilator lint_off PINMISSING */
wire [4:0] cnt_aux;
sep32_cnt u_sep32_cnt (.clk(clk), .zero(zero), .cnt(cnt_aux));
sep32 #(.width(7),.stg(1)) sep_tl(
.clk ( clk ),
.mixed ( tl_VII ),
.cnt ( cnt_aux )
);
sep32 #(.width(5),.stg(1)) sep_ar(
.clk ( clk ),
.mixed ( arate_II ),
.cnt ( cnt_aux )
);
sep32 #(.width(4),.stg(1)) sep_d1l(
.clk ( clk ),
.mixed ( d1l_I ),
.cnt ( cnt_aux )
);
sep32 #(.width(4),.stg(1)) sep_rr(
.clk ( clk ),
.mixed ( rrate_II ),
.cnt ( cnt_aux )
);
sep32 #(.width(1),.stg(1)) sep_amsen(
.clk ( clk ),
.mixed ( amsen_VII ),
.cnt ( cnt_aux )
);
/* verilator lint_on PINMISSING */
`endif
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module unsaved_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
debugaccess,
freeze,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "/home/ferllini13/Desktop/CE-4301-Arqui1/proce/Pruebas mif/test.mif";
output [ 31: 0] readdata;
input [ 4: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input debugaccess;
input freeze;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write & debugaccess;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 32,
the_altsyncram.numwords_a = 32,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.read_during_write_mode_port_a = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 5;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
//--------------------------------------------------------------------------------
//-- Filename: REQ_QUEUE_WRAPPER.v
//--
//-- Description: REQUEST QUEUE WRAPPER Module
//--
//-- The module receives requests from HOST and distinguish read req-
//-- uests from write requests then sends them to corresponded request fifo. Thro-
//-- ugh this module we can fully use the duplex feature of PCIe LINK.
//--------------------------------------------------------------------------------
`timescale 1ns/1ns
module REQ_QUEUE_WRAPPER(
clk,
rst_n,
en,
//receive request queue
rdata_i,
rdata_wr_en_i,
req_queue_av_o,
req_queue_full_o,
//rd request queue
rd_req_empty_o,
rd_req_rd_en_i,
rd_req_data_o,
//wr request queue
wr_req_empty_o,
wr_req_rd_en_i,
wr_req_data_o,
req_cnt_o,
req_unsupported_o
);
parameter REQ_QUEUE_DEPTH = 64;
parameter RD_REQ_QUEUE_DEPTH = 64;
parameter WR_REQ_QUEUE_DEPTH = 64;
parameter RD_REQUEST = 8'h01;
parameter WR_REQUEST = 8'h02;
parameter QUEUE_WRAPPER_RST = 2'b01;
parameter QUEUE_WRAPPER_REQ_XFER = 2'b10;
input clk , rst_n;
input en;
input [127:0] rdata_i;
input rdata_wr_en_i;
output [9:0] req_queue_av_o;
output req_queue_full_o;
output rd_req_empty_o;
input rd_req_rd_en_i;
output [127:0] rd_req_data_o;
output wr_req_empty_o;
input wr_req_rd_en_i;
output [127:0] wr_req_data_o;
output [31:0] req_cnt_o;
output req_unsupported_o;
reg [31:0] req_cnt_o;
reg req_unsupported_o;
wire srst = !rst_n | !en;
wire [9:0] req_queue_data_count;
wire [6:0] req_queue_req_count;
wire [127:0] req_queue_data;
reg req_queue_rd_en;
wire [9:0] rd_req_queue_data_count , wr_req_queue_data_count;
wire [6:0] rd_req_queue_req_count , wr_req_queue_req_count;
wire [9:0] rd_req_queue_av , wr_req_queue_av;
reg rd_req_queue_wr_en , wr_req_queue_wr_en;
reg [3:0] xfer_cnt;
reg [1:0] queue_wrapper_state;
assign req_queue_req_count = req_queue_data_count >> 3;
assign req_queue_av_o = REQ_QUEUE_DEPTH - req_queue_req_count;
assign rd_req_queue_req_count = rd_req_queue_data_count >> 3;
assign wr_req_queue_req_count = wr_req_queue_data_count >> 3;
assign rd_req_queue_av = RD_REQ_QUEUE_DEPTH - rd_req_queue_req_count;
assign wr_req_queue_av = WR_REQ_QUEUE_DEPTH - wr_req_queue_req_count;
assign rd_req_empty_o = ( rd_req_queue_req_count == 0 ) ? 1'b1 : 1'b0;
assign wr_req_empty_o = ( wr_req_queue_req_count == 0 ) ? 1'b1 : 1'b0;
// request queue fifo
// DEPTH: 512
// WIDTH: 128
// REQUEST DEPTH: 64
RECV_REQ_QUEUE REQ_QUEUE (
.clk( clk ), // input clk
.srst( srst ), // input srst
.din( rdata_i ), // input [127 : 0] din
.wr_en( rdata_wr_en_i ), // input wr_en
.rd_en( req_queue_rd_en ), // input rd_en
.dout( req_queue_data ), // output [127 : 0] dout
.full( req_queue_full_o ), // output full
.empty( ), // output empty
.data_count( req_queue_data_count ) // output [9 : 0] data_count
);
// read request queue fifo
// DEPTH: 512
// WIDTH: 128
// REQUEST DEPTH: 64
RECV_REQ_QUEUE RD_REQ_QUEUE (
.clk( clk ), // input clk
.srst( srst ), // input srst
.din( req_queue_data ), // input [127 : 0] din
.wr_en( rd_req_queue_wr_en ), // input wr_en
.rd_en( rd_req_rd_en_i ), // input rd_en
.dout( rd_req_data_o ), // output [127 : 0] dout
.full( ), // output full
.empty( ), // output empty
.data_count( rd_req_queue_data_count ) // output [9 : 0] data_count
);
// write request queue fifo
// DEPTH: 512
// WIDTH: 128
// REQUEST DEPTH: 64
RECV_REQ_QUEUE WR_REQ_QUEUE (
.clk( clk ), // input clk
.srst( srst ), // input srst
.din( req_queue_data ), // input [127 : 0] din
.wr_en( wr_req_queue_wr_en ), // input wr_en
.rd_en( wr_req_rd_en_i ), // input rd_en
.dout( wr_req_data_o ), // output [127 : 0] dout
.full( ), // output full
.empty( ), // output empty
.data_count( wr_req_queue_data_count ) // output [9 : 0] data_count
);
// this state machine gets requests from request fifo and checks requests
// then sends requests to read request fifo or write request fifo.
// NOTICE: Each request is 128 bytes = 8 * 128 bits.
//
always @ ( posedge clk ) begin
if( !rst_n || !en ) begin
req_queue_rd_en <= 1'b0;
rd_req_queue_wr_en <= 1'b0;
wr_req_queue_wr_en <= 1'b0;
xfer_cnt <= 4'b0;
req_cnt_o <= 32'b0;
req_unsupported_o <= 1'b0;
queue_wrapper_state <= QUEUE_WRAPPER_RST;
end
else begin
case ( queue_wrapper_state )
QUEUE_WRAPPER_RST: begin
if( req_queue_req_count != 0 ) begin
case ( req_queue_data[103:96] )
RD_REQUEST: begin
if( rd_req_queue_av != 0 ) begin
req_queue_rd_en <= 1'b1;
rd_req_queue_wr_en <= 1'b1;
xfer_cnt <= 4'b1;
req_cnt_o <= req_cnt_o + 1'b1;
queue_wrapper_state <= QUEUE_WRAPPER_REQ_XFER;
end
end
WR_REQUEST: begin
if( wr_req_queue_av != 0 ) begin
req_queue_rd_en <= 1'b1;
wr_req_queue_wr_en <= 1'b1;
xfer_cnt <= 4'b1;
req_cnt_o <= req_cnt_o + 1'b1;
queue_wrapper_state <= QUEUE_WRAPPER_REQ_XFER;
end
end
default: begin
req_queue_rd_en <= 1'b1;
xfer_cnt <= 4'b1;
req_cnt_o <= req_cnt_o + 1'b1;
req_unsupported_o <= 1'b1;
queue_wrapper_state <= QUEUE_WRAPPER_REQ_XFER;
end
endcase
end // if( req_queue_req_count != 0 )
end
QUEUE_WRAPPER_REQ_XFER: begin
if( xfer_cnt < 8 ) begin
xfer_cnt <= xfer_cnt + 1'b1;
queue_wrapper_state <= QUEUE_WRAPPER_REQ_XFER;
end
else begin
req_queue_rd_en <= 1'b0;
wr_req_queue_wr_en <= 1'b0;
rd_req_queue_wr_en <= 1'b0;
queue_wrapper_state <= QUEUE_WRAPPER_RST;
end
end
default: begin
queue_wrapper_state <= QUEUE_WRAPPER_RST;
end
endcase
end //if( !rst_n || !en )
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFSTP_SYMBOL_V
`define SKY130_FD_SC_LP__SDFSTP_SYMBOL_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__sdfstp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFSTP_SYMBOL_V
|
/**
* bsg_fpu_mul.v
*
* parameterized floating-point multiplier.
*
* @author Tommy Jung
*/
`include "bsg_defines.v"
`include "bsg_fpu_defines.vh"
module bsg_fpu_mul
#(parameter `BSG_INV_PARAM(e_p) // exponent width
, parameter `BSG_INV_PARAM(m_p) // mantissa width
)
(
input clk_i
, input reset_i
, input en_i
, input v_i
, input [e_p+m_p:0] a_i
, input [e_p+m_p:0] b_i
, output logic ready_o
, output logic v_o
, output logic [e_p+m_p:0] z_o
, output logic unimplemented_o
, output logic invalid_o
, output logic overflow_o
, output logic underflow_o
, input yumi_i // when yumi_i is high, en_i also has to be high
);
// pipeline states / signals
logic v_1_r, v_2_r, v_3_r;
logic stall;
assign stall = v_3_r & ~yumi_i;
assign v_o = v_3_r;
assign ready_o = ~stall & en_i;
// preprocessors
logic a_zero, a_nan, a_sig_nan, a_infty, exp_a_zero, man_a_zero,
a_denormal, sign_a;
logic b_zero, b_nan, b_sig_nan, b_infty, exp_b_zero, man_b_zero,
b_denormal, sign_b;
logic [e_p-1:0] exp_a, exp_b;
logic [m_p-1:0] man_a, man_b;
bsg_fpu_preprocess #(
.e_p(e_p)
,.m_p(m_p)
) a_preprocess (
.a_i(a_i)
,.zero_o(a_zero)
,.nan_o(a_nan)
,.sig_nan_o(a_sig_nan)
,.infty_o(a_infty)
,.exp_zero_o(exp_a_zero)
,.man_zero_o(man_a_zero)
,.denormal_o(a_denormal)
,.sign_o(sign_a)
,.exp_o(exp_a)
,.man_o(man_a)
);
bsg_fpu_preprocess #(
.e_p(e_p)
,.m_p(m_p)
) b_preprocess (
.a_i(b_i)
,.zero_o(b_zero)
,.nan_o(b_nan)
,.sig_nan_o(b_sig_nan)
,.infty_o(b_infty)
,.exp_zero_o(exp_b_zero)
,.man_zero_o(man_b_zero)
,.denormal_o(b_denormal)
,.sign_o(sign_b)
,.exp_o(exp_b)
,.man_o(man_b)
);
// final sign
logic final_sign;
assign final_sign = sign_a ^ sign_b;
// add exponents together
logic [e_p:0] exp_sum;
assign exp_sum = {1'b0, exp_a} + {1'b0, exp_b} + 9'b1;
// sum of exp with bias removed
logic [e_p-1:0] exp_sum_unbiased;
assign exp_sum_unbiased = {~exp_sum[e_p-1], exp_sum[e_p-2:0]};
// normalized mantissa
logic [m_p:0] man_a_norm, man_b_norm;
assign man_a_norm = {1'b1, man_a};
assign man_b_norm = {1'b1, man_b};
/////////////// first pipeline stage ///////////////////////////////
//
logic final_sign_1_r;
logic [e_p-1:0] exp_sum_unbiased_1_r;
logic a_sig_nan_1_r, b_sig_nan_1_r;
logic a_nan_1_r, b_nan_1_r;
logic a_infty_1_r, b_infty_1_r;
logic a_zero_1_r, b_zero_1_r;
logic a_denormal_1_r, b_denormal_1_r;
logic [e_p:0] exp_sum_1_r;
logic [m_p:0] man_a_norm_r, man_b_norm_r;
always_ff @ (posedge clk_i) begin
if (reset_i) begin
v_1_r <= 1'b0;
end
else begin
if (~stall & en_i) begin
v_1_r <= v_i;
if (v_i) begin
final_sign_1_r <= final_sign;
exp_sum_unbiased_1_r <= exp_sum_unbiased;
a_sig_nan_1_r <= a_sig_nan;
b_sig_nan_1_r <= b_sig_nan;
a_nan_1_r <= a_nan;
b_nan_1_r <= b_nan;
a_infty_1_r <= a_infty;
b_infty_1_r <= b_infty;
a_zero_1_r <= a_zero;
b_zero_1_r <= b_zero;
a_denormal_1_r <= a_denormal;
b_denormal_1_r <= b_denormal;
exp_sum_1_r <= exp_sum;
man_a_norm_r <= man_a_norm;
man_b_norm_r <= man_b_norm;
end
end
end
end
//////////// second pipeline stage ///////////////////////////////
// for single precision: 24-bit multiplier
logic [((m_p+1)*2)-1:0] man_prod;
bsg_mul_synth #(
.width_p(m_p+1)
) mul_synth (
.a_i(man_a_norm_r)
,.b_i(man_b_norm_r)
,.o(man_prod)
);
logic [((m_p+1)*2)-1:0] man_prod_2_r;
logic [e_p-1:0] exp_sum_unbiased_2_r;
logic a_sig_nan_2_r, b_sig_nan_2_r;
logic a_nan_2_r, b_nan_2_r;
logic a_infty_2_r, b_infty_2_r;
logic a_zero_2_r, b_zero_2_r;
logic a_denormal_2_r, b_denormal_2_r;
logic [e_p:0] exp_sum_2_r;
logic final_sign_2_r;
always_ff @ (posedge clk_i) begin
if (reset_i) begin
v_2_r <= 1'b0;
end
else begin
if (~stall & en_i) begin
v_2_r <= v_1_r;
if (v_1_r) begin
man_prod_2_r <= man_prod;
exp_sum_unbiased_2_r <= exp_sum_unbiased_1_r;
a_sig_nan_2_r <= a_sig_nan_1_r;
b_sig_nan_2_r <= b_sig_nan_1_r;
a_nan_2_r <= a_nan_1_r;
b_nan_2_r <= b_nan_1_r;
a_infty_2_r <= a_infty_1_r;
b_infty_2_r <= b_infty_1_r;
a_zero_2_r <= a_zero_1_r;
b_zero_2_r <= b_zero_1_r;
a_denormal_2_r <= a_denormal_1_r;
b_denormal_2_r <= b_denormal_1_r;
exp_sum_2_r <= exp_sum_1_r;
final_sign_2_r <= final_sign_1_r;
end
end
end
end
// lowers bits
logic sticky, round, guard;
assign sticky = |man_prod_2_r[m_p-2:0];
assign round = man_prod_2_r[m_p-1];
assign guard = man_prod_2_r[m_p];
// round condition
logic round_up;
assign round_up = sticky
? (man_prod_2_r[(2*(m_p+1))-1] ? guard : round)
: (guard & (round | (man_prod_2_r[(2*(m_p+1))-1] & man_prod_2_r[m_p+1])));
// exp with additional carry bit from the product of mantissa added.
logic [e_p:0] final_exp;
assign final_exp = {1'b0, exp_sum_unbiased_2_r} + man_prod_2_r[(2*(m_p+1))-1];
// mantissa also needs to be shifted if the product is larger than 2.
logic [m_p-1:0] shifted_mantissa;
assign shifted_mantissa = man_prod_2_r[(2*(m_p+1))-1]
? man_prod_2_r[(m_p+1)+:m_p]
: man_prod_2_r[m_p+:m_p];
// pre_roundup;
logic [e_p+m_p-1:0] pre_roundup;
assign pre_roundup = {final_exp[e_p-1:0], shifted_mantissa};
//////////// third pipeline stage ///////////////////////////////
logic [e_p+m_p-1:0] pre_roundup_3_r;
logic round_up_3_r;
logic final_sign_3_r;
logic a_sig_nan_3_r, b_sig_nan_3_r;
logic a_nan_3_r, b_nan_3_r;
logic a_infty_3_r, b_infty_3_r;
logic a_zero_3_r, b_zero_3_r;
logic a_denormal_3_r, b_denormal_3_r;
logic [e_p:0] exp_sum_3_r;
logic [e_p:0] final_exp_3_r;
always_ff @ (posedge clk_i) begin
if (reset_i) begin
v_3_r <= 1'b0;
end
else begin
if (~stall & en_i) begin
v_3_r <= v_2_r;
if (v_2_r) begin
pre_roundup_3_r <= pre_roundup;
round_up_3_r <= round_up;
final_sign_3_r <= final_sign_2_r;
a_sig_nan_3_r <= a_sig_nan_2_r;
b_sig_nan_3_r <= b_sig_nan_2_r;
a_nan_3_r <= a_nan_2_r;
b_nan_3_r <= b_nan_2_r ;
a_infty_3_r <= a_infty_2_r;
b_infty_3_r <= b_infty_2_r;
a_zero_3_r <= a_zero_2_r;
b_zero_3_r <= b_zero_2_r;
a_denormal_3_r <= a_denormal_2_r;
b_denormal_3_r <= b_denormal_2_r;
exp_sum_3_r <= exp_sum_2_r;
final_exp_3_r <= final_exp;
end
end
end
end
// carry going into exp when rounding up
// (important for distinguishing between overflow and underflow)
logic carry_into_exp;
assign carry_into_exp = &{round_up_3_r, pre_roundup_3_r[m_p-1:0]};
// round up for the final result.
logic round_overflow;
logic [e_p+m_p-1:0] rounded;
assign {round_overflow, rounded} = pre_roundup_3_r + round_up_3_r;
// final output
logic sgn;
always_comb begin
sgn = final_sign_3_r;
if (a_sig_nan_3_r | b_sig_nan_3_r) begin
unimplemented_o = 1'b0;
invalid_o = 1'b1;
overflow_o = 1'b0;
underflow_o = 1'b0;
z_o = `BSG_FPU_SIGNAN(e_p,m_p); // sig nan
end
else if (a_nan_3_r | b_nan_3_r) begin
unimplemented_o = 1'b0;
invalid_o = 1'b0;
overflow_o = 1'b0;
underflow_o = 1'b0;
z_o = `BSG_FPU_QUIETNAN(e_p,m_p); // quiet nan
end
else if (a_infty_3_r) begin
if (b_zero_3_r) begin
unimplemented_o = 1'b0;
invalid_o = 1'b1;
overflow_o = 1'b0;
underflow_o = 1'b0;
z_o = `BSG_FPU_QUIETNAN(e_p,m_p); // quiet nan
end
else begin
unimplemented_o = 1'b0;
invalid_o = 1'b0;
overflow_o = 1'b0;
underflow_o = 1'b0;
z_o = `BSG_FPU_INFTY(sgn,e_p,m_p); // infty
end
end
else if (b_infty_3_r) begin
if (a_zero_3_r) begin
unimplemented_o = 1'b0;
invalid_o = 1'b1;
overflow_o = 1'b0;
underflow_o = 1'b0;
z_o = `BSG_FPU_QUIETNAN(e_p,m_p); // quiet nan
end
else begin
unimplemented_o = 1'b0;
invalid_o = 1'b0;
overflow_o = 1'b0;
underflow_o = 1'b0;
z_o = `BSG_FPU_INFTY(sgn,e_p,m_p); // infty
end
end
else if (a_zero_3_r | b_zero_3_r) begin
unimplemented_o = 1'b0;
invalid_o = 1'b0;
overflow_o = 1'b0;
underflow_o = 1'b0;
z_o = `BSG_FPU_ZERO(sgn,e_p,m_p); // zero
end
else if (a_denormal_3_r & b_denormal_3_r) begin
unimplemented_o = 1'b0;
invalid_o = 1'b0;
overflow_o = 1'b0;
underflow_o = 1'b1;
z_o = `BSG_FPU_ZERO(sgn,e_p,m_p); // zero
end
else if (a_denormal_3_r | b_denormal_3_r) begin
unimplemented_o = 1'b1;
invalid_o = 1'b0;
overflow_o = 1'b0;
underflow_o = 1'b0;
z_o = `BSG_FPU_QUIETNAN(e_p,m_p); // quiet nan
end
else if (exp_sum_3_r[(e_p-1)+:2] == 2'b0) begin
unimplemented_o = 1'b0;
invalid_o = 1'b0;
overflow_o = 1'b0;
underflow_o = 1'b1;
z_o = `BSG_FPU_ZERO(sgn,e_p,m_p); // zero
end
else if (exp_sum_3_r[(e_p-1)+:2] == 2'b11 | final_exp_3_r[e_p]) begin
unimplemented_o = 1'b0;
invalid_o = 1'b0;
overflow_o = 1'b1;
underflow_o = 1'b0;
z_o = `BSG_FPU_INFTY(sgn,e_p,m_p); // infty
end
else begin
if (pre_roundup_3_r[m_p+:e_p] == {e_p{1'b1}} & (pre_roundup_3_r[m_p] | carry_into_exp)) begin
unimplemented_o = 1'b0;
invalid_o = 1'b0;
overflow_o = 1'b1;
underflow_o = 1'b0;
z_o = `BSG_FPU_INFTY(sgn,e_p,m_p); // infty
end
else if (pre_roundup_3_r[m_p+:e_p] == {e_p{1'b0}} & ~carry_into_exp) begin
unimplemented_o = 1'b0;
invalid_o = 1'b0;
overflow_o = 1'b0;
underflow_o = 1'b1;
z_o = `BSG_FPU_ZERO(sgn,e_p,m_p); // zero
end
else begin
unimplemented_o = 1'b0;
invalid_o = 1'b0;
overflow_o = 1'b0;
underflow_o = 1'b0;
z_o = {sgn, rounded}; // happy case
end
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_fpu_mul)
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module sram_test (
input wire FCLK_IN,
// full speed
inout wire [7:0] BUS_DATA,
input wire [15:0] ADD,
input wire RD_B,
input wire WR_B,
// high speed
inout wire [7:0] FD,
input wire FREAD,
input wire FSTROBE,
input wire FMODE,
//SRAM
output wire [19:0] SRAM_A,
inout wire [15:0] SRAM_IO,
output wire SRAM_BHE_B,
output wire SRAM_BLE_B,
output wire SRAM_CE1_B,
output wire SRAM_OE_B,
output wire SRAM_WE_B,
output wire [4:0] LED,
inout wire SDA,
inout wire SCL
);
assign SDA = 1'bz;
assign SCL = 1'bz;
assign LED = 5'b10110;
wire [15:0] BUS_ADD;
wire BUS_CLK, BUS_RD, BUS_WR, BUS_RST;
// BASIL bus mapping
assign BUS_CLK = FCLK_IN;
fx2_to_bus i_fx2_to_bus (
.ADD(ADD),
.RD_B(RD_B),
.WR_B(WR_B),
.BUS_CLK(BUS_CLK),
.BUS_ADD(BUS_ADD),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.CS_FPGA()
);
reset_gen i_reset_gen (
.CLK(BUS_CLK),
.RST(BUS_RST)
);
//MODULE ADREESSES
localparam GPIO_CONTROL_BASEADDR = 16'h0000;
localparam GPIO_CONTROL_HIGHADDR = 16'h000f;
localparam GPIO_PATTERN_BASEADDR = 16'h0010;
localparam GPIO_PATTERN_HIGHADDR = 16'h001f;
localparam FIFO_BASEADDR = 16'h0020;
localparam FIFO_HIGHADDR = 16'h002f;
localparam PULSE_BASEADDR = 32'h0030;
localparam PULSE_HIGHADDR = 32'h003f;
// USER MODULES //
wire [4:0] CONTROL_NOT_USED;
wire PATTERN_EN;
wire COUNTER_EN;
wire COUNTER_DIRECT;
gpio #(
.BASEADDR(GPIO_CONTROL_BASEADDR),
.HIGHADDR(GPIO_CONTROL_HIGHADDR),
.IO_WIDTH(8),
.IO_DIRECTION(8'hff)
) i_gpio_control (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO({CONTROL_NOT_USED, COUNTER_DIRECT, PATTERN_EN, COUNTER_EN})
);
wire [31:0] PATTERN;
gpio #(
.BASEADDR(GPIO_PATTERN_BASEADDR),
.HIGHADDR(GPIO_PATTERN_HIGHADDR),
.IO_WIDTH(32),
.IO_DIRECTION(32'hffffffff)
) i_gpio_pattern (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO(PATTERN)
);
wire PULSE;
pulse_gen #(
.BASEADDR(PULSE_BASEADDR),
.HIGHADDR(PULSE_HIGHADDR)
) i_pulse_gen (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.PULSE_CLK(BUS_CLK),
.EXT_START(1'b0),
.PULSE(PULSE)
);
wire PATTERN_FIFO_READ;
wire PATTERN_FIFO_EMPTY;
wire [31:0] COUNTER_FIFO_DATA;
wire COUNTER_FIFO_EMPTY;
wire COUNTER_FIFO_READ;
wire ARB_READY_OUT, ARB_WRITE_OUT;
wire [31:0] ARB_DATA_OUT;
rrp_arbiter #(
.WIDTH(2)
) i_rrp_arbiter (
.RST(BUS_RST),
.CLK(BUS_CLK),
.WRITE_REQ({COUNTER_EN | PULSE, PATTERN_EN}),
.HOLD_REQ({2'b0}),
.DATA_IN({COUNTER_FIFO_DATA, PATTERN}),
.READ_GRANT({COUNTER_FIFO_READ, PATTERN_FIFO_READ}),
.READY_OUT(ARB_READY_OUT),
.WRITE_OUT(ARB_WRITE_OUT),
.DATA_OUT(ARB_DATA_OUT)
);
wire USB_READ;
assign USB_READ = FREAD && FSTROBE;
wire [7:0] FD_SRAM;
sram_fifo #(
.BASEADDR(FIFO_BASEADDR),
.HIGHADDR(FIFO_HIGHADDR)
) i_out_fifo (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.SRAM_A(SRAM_A),
.SRAM_IO(SRAM_IO),
.SRAM_BHE_B(SRAM_BHE_B),
.SRAM_BLE_B(SRAM_BLE_B),
.SRAM_CE1_B(SRAM_CE1_B),
.SRAM_OE_B(SRAM_OE_B),
.SRAM_WE_B(SRAM_WE_B),
.USB_READ(USB_READ),
.USB_DATA(FD_SRAM),
.FIFO_READ_NEXT_OUT(ARB_READY_OUT),
.FIFO_EMPTY_IN(!ARB_WRITE_OUT),
.FIFO_DATA(ARB_DATA_OUT),
.FIFO_NOT_EMPTY(),
.FIFO_READ_ERROR(),
.FIFO_FULL(),
.FIFO_NEAR_FULL()
);
reg [31:0] count;
always @(posedge BUS_CLK)
if(BUS_RST)
count <= 0;
else if (COUNTER_FIFO_READ)
count <= count + 1;
wire [7:0] count_send [3:0];
assign count_send[0] = count*4;
assign count_send[1] = count*4 + 1;
assign count_send[2] = count*4 + 2;
assign count_send[3] = count*4 + 3;
assign COUNTER_FIFO_DATA = {count_send[3], count_send[2], count_send[1], count_send[0]};
reg [7:0] count_direct;
always @(posedge BUS_CLK)
if(BUS_RST)
count_direct <= 0;
else if (USB_READ)
count_direct <= count_direct + 1;
assign FD = COUNTER_DIRECT ? count_direct: FD_SRAM;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module is extracted from the original CRTTIMER.
// It consist of adders and substractors common to VRAM and DRAM
// controllers. Speed of everything in this module is really don't care.
// The original CRTTIMER will remain intact if proper port connections are
// made with this module.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 10ps
module crtaddsl
(
hactive_regist,
hblank_regist,
hfporch_regist,
hswidth_regist,
vactive_regist,
vblank_regist,
vfporch_regist,
vswidth_regist,
htotal_add,
hendsync_add,
endequal_add,
halfline_add,
endequalsec_add,
serrlongfp_substr,
serr_substr,
serrsec_substr,
vendsync_add,
vendequal_add,
vtotal_add,
hfpbhs
);
/* vertical parameters max FFF, horizontal parameters max 3FFF */
input [13:0] hactive_regist,
hblank_regist,
hfporch_regist,
hswidth_regist;
input [11:0] vactive_regist,
vblank_regist,
vfporch_regist,
vswidth_regist;
output [13:0] htotal_add,
hendsync_add,
endequal_add,
halfline_add,
endequalsec_add,
serrlongfp_substr,
serr_substr,
serrsec_substr;
output [11:0] vendsync_add,
vendequal_add,
vtotal_add;
output hfpbhs;
wire [13:0] serrshortfp_substr;
/*****
establish horizontal sync end position , equalizing impulse end , half line
and second equalizing end, and htotal.
*****/
assign htotal_add[13:0] = hblank_regist[13:0] + hactive_regist[13:0];
assign hendsync_add[13:0] = hfporch_regist[13:0] +
hswidth_regist[13:0];
assign endequal_add[13:0] = hfporch_regist[13:0] +
hswidth_regist[13:1];
//half sync
assign halfline_add[13:0] = hfporch_regist[13:0] + htotal_add[13:1];
assign endequalsec_add[13:0] = halfline_add[13:0] +
hswidth_regist[13:1];
//half sync
assign serrlongfp_substr[13:0] = hfporch_regist[13:0] -
hswidth_regist[13:0];
assign serrshortfp_substr[13:0] = hswidth_regist[13:0] -
hfporch_regist[13:0];
assign serr_substr[13:0] = halfline_add[13:0] - hswidth_regist[13:0];
assign serrsec_substr[13:0] = htotal_add[13:0] -
serrshortfp_substr[13:0];
/** set points for the vertical-end-sync position and the end of vertical
equalization region */
assign vtotal_add[11:0] = vblank_regist[11:0] + vactive_regist[11:0];
assign vendsync_add[11:0] = vfporch_regist[11:0] +
vswidth_regist[11:0];
assign vendequal_add[11:0] = vfporch_regist[11:0] +
{vswidth_regist[10:0],1'b0};
/*** compare hfporch and width of hsync ***/
assign hfpbhs = (hfporch_regist[13:0] > hswidth_regist[13:0]);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSRECEIVER_0_V
`define SKY130_FD_SC_LP__BUSRECEIVER_0_V
/**
* busreceiver: Bus signal receiver.
*
* Verilog wrapper for busreceiver with size of 0 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__busreceiver.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__busreceiver_0 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__busreceiver base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__busreceiver_0 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__busreceiver base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSRECEIVER_0_V
|
//Legal Notice: (C)2018 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module jaxa_autoStart (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg data_out;
wire out_port;
wire read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {1 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata;
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A32O_BEHAVIORAL_V
`define SKY130_FD_SC_LS__A32O_BEHAVIORAL_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a32o (
X ,
A1,
A2,
A3,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
and and1 (and1_out , B1, B2 );
or or0 (or0_out_X, and1_out, and0_out);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A32O_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A32OI_1_V
`define SKY130_FD_SC_MS__A32OI_1_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a32oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a32oi_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a32oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a32oi_1 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a32oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A32OI_1_V
|
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2000-2011 by Wilson Snyder.
//===========================================================================
// Includes
`include "t_preproc_inc2.vh"
//===========================================================================
// Comments
/* verilator pass_thru comment */
// verilator pass_thru_comment2
//===========================================================================
// Defines
`define DEF_A3
`define DEF_A1
// DEF_A0 set by command line
wire [3:0] q = {
`ifdef DEF_A3 1'b1 `else 1'b0 `endif ,
`ifdef DEF_A2 1'b1 `else 1'b0 `endif ,
`ifdef DEF_A1 1'b1 `else 1'b0 `endif ,
`ifdef DEF_A0 1'b1 `else 1'b0 `endif
};
text.
`define FOOBAR foo /*this */ bar /* this too */
`define FOOBAR2 foobar2 // but not
`FOOBAR
`FOOBAR2
`define MULTILINE first part \
second part \
third part
`define MOREMULTILINE {\
a,\
b,\
c}
/*******COMMENT*****/
`MULTILINE
`MOREMULTILINE
Line_Preproc_Check `__LINE__
//===========================================================================
`define syn_negedge_reset_l or negedge reset_l
`define DEEP deep
`define DEEPER `DEEP `DEEP
`DEEPER
`define nosubst NOT_SUBSTITUTED
`define WITHTICK "`nosubst"
"Inside: `nosubst"
`WITHTICK
`define withparam(a, b) a b LLZZ a b
`withparam(x,y)
`withparam(`withparam(p,q),`withparam ( r , s ))
`withparam(firstline
,
comma","line)
`define withquote(a, bar) a bar LLZZ "a" bar
`withquote( x , y) // Simulators disagree here; some substitute "a" others do not
`define noparam (a,b)
`noparam(a,b)
`define msg(x,y) `"x: `\`"y`\`"`"
$display(`msg(left side, right side))
`define foo(f) f``_suffix
`foo(bar) more
`define zap(which) \
$c("Zap(\"",which,"\");");
`zap(bug1);
`zap("bug2");
/* Define inside comment: `DEEPER and `WITHTICK */
// More commentary: `zap(bug1); `zap("bug2");
//======================================================================
// display passthru
`define ls left_side
`define rs right_side
`define noarg na
`define thru(x) x
`define thruthru `ls `rs // Doesn't expand
`define msg(x,y) `"x: `\`"y`\`"`"
initial begin
//$display(`msg( \`, \`)); // Illegal
$display(`msg(pre `thru(thrupre `thru(thrumid) thrupost) post,right side));
$display(`msg(left side,right side));
$display(`msg( left side , right side ));
$display(`msg( `ls , `rs ));
$display(`msg( `noarg , `rs ));
$display(`msg( prep ( midp1 `ls midp2 ( outp ) ) , `rs ));
$display(`msg(`noarg,`noarg`noarg));
$display(`msg( `thruthru , `thruthru )); // Results vary between simulators
$display(`msg(`thru(),)); // Empty
$display(`msg(`thru(left side),`thru(right side)));
$display(`msg( `thru( left side ) , `thru( right side ) ));
$display(`"standalone`");
// Unspecified when the stringification has multiple lines
`define twoline first \
second
$display(`msg(twoline, `twoline));
//$display(`msg(left side, \ right side \ )); // Not sure \{space} is legal.
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
//======================================================================
// rt.cpan.org bug34429
`define ADD_UP(a,c) \
wire tmp_``a = a; \
wire tmp_``c = tmp_``a + 1; \
assign c = tmp_``c ;
module add1 ( input wire d1, output wire o1);
`ADD_UP(d1,o1) // expansion is OK
endmodule
module add2 ( input wire d2, output wire o2);
`ADD_UP( d2 , o2 ) // expansion is bad
endmodule
`define check(mod, width, flopname, gate, path) \
generate for (i=0; i<(width); i=i+1) begin \
psl cover { path.d[i] & ~path.q[i] & !path.cond & (gate)} report `"fondNoRise: mod.flopname`"; \
psl cover { ~path.d[i] & path.q[i] & !path.cond & (gate)} report `"fondNoFall: mod.flopname`"; \
end endgenerate
// parameterized macro with arguments that are macros
`define MK m5k.f
`define MF `MK .ctl
`define CK_fr (`MF.alive & `MF.alive_m1)
`check(m5kc_fcl, 3, _ctl_mvldx_m1, `CK_fr, `MF._ctl_mvldx_m1) // ignorecmt
//======================================================================
// Quotes are legal in protected blocks. Grr.
module prot();
`protected
I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl)
#nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk]
`endprotected
endmodule
//"
//======================================================================
// macro call with define that has comma
`define REG_H 6
`define REG_L 7
`define _H regs[`REG_H]
`define _L regs[`REG_L]
`define _HL {`_H, `_L}
`define EX_WRITE(ad, da) begin addr <= (ad); wdata <= (da); wr <= 1; end
`define EX_READ(ad) begin addr <= (ad); rd <= 1; end
`EX_READ((`_HL + 1)) and `EX_WRITE((`_HL), rdata)
`EX_READ(`_HL + 1)
`EX_WRITE(`_HL, rdata) more
//======================================================================
// include of parameterized file
`define INCNAME "t_preproc_inc4.vh"
`include `INCNAME
`ifndef T_PREPROC_INC4
`error "No Inc4"
`endif
`undef T_PREPROC_INC4
`ifdef NOT_DEFINED_INC
`include NOT_DEFINED_INC
`endif
//======================================================================
// macro call with , in {}
`define xxerror(logfile, msg) $blah(logfile,msg)
`xxerror("ab,cd","e,f");
`xxerror(this.logfile, vec);
`xxerror(this.logfile, vec[1,2,3]);
`xxerror(this.logfile, {blah.name(), " is not foo"});
//======================================================================
// pragma/default net type
`pragma foo = 1
`default_nettype none
`default_nettype uwire
//======================================================================
// Ifdef
`define EMPTY_TRUE
`ifndef EMPTY_TRUE
`error "Empty is still true"
`endif
Line_Preproc_Check `__LINE__
//======================================================================
// bug84
`define ARGPAR(a, // Hello, comments MIGHT not be legal
/*more,,)cmts*/ b // But newlines ARE legal... who speced THAT?
) (a,b)
`ARGPAR(p,q)
`ARGPAR( //Here
x,
y //Too
)
Line_Preproc_Check `__LINE__
//======================================================================
// defines split arguments
`define BEGIN begin
`define END end
`define BEGINEND `BEGIN`END
`define quoteit(x) `"x`"
`BEGIN`END // 2001 spec doesn't require two tokens, so "beginend" ok
`BEGINEND // 2001 spec doesn't require two tokens, so "beginend" ok
`quoteit(`BEGIN`END) // No space "beginend"
//======================================================================
// bug106
`define \esc`def got_escaped
`ifdef \esc`def
`\esc`def
`endif
Not a \`define
//======================================================================
// misparsed comma in submacro
`define sb bee
`define appease_emacs_paren_matcher (
`define sa(l) x,y)
`define sfoo(q,r) q--r
`sfoo(`sa(el),`sb) submacro has comma paren
//======================================================================
// bug191
`define bug191(bits) $display("bits %d %d", $bits(foo), bits);
`bug191(10)
//======================================================================
// 1800-2009
`define UDALL
`ifndef PREDEF_COMMAND_LINE `error "Test setup error, PREDEF_COMMAND_LINE pre-missing" `endif
`undefineall
`ifdef UDALL `error "undefineall failed" `endif
`ifndef PREDEF_COMMAND_LINE `error "Deleted too much, no PREDEF_COMMAND_LINE" `endif
//======================================================================
// bug202
`define FC_INV3(out, in) \
`ifdef DC \
cell \inv_``out <$typeof(out)> (.a(<in>), .o(<out>)); \
/* multi-line comment \
multi-line comment */ \
`else \
`ifdef MACRO_ATTRIBUTE \
(* macro_attribute = `"INV (out``,in``)`" *) \
`endif \
assign out = ~in ; \
`endif
`FC_INV3(a3,b3)
`define /* multi \
line1*/ \
bug202( i /*multi \
line2*/ \
) \
/* multi \
line 3*/ \
def i \
`bug202(foo)
//======================================================================
`define CMT1 // verilator NOT IN DEFINE
`define CMT2 /* verilator PART OF DEFINE */
`define CMT3 /* verilator NOT PART
OF DEFINE */
`define CMT4 /* verilator PART \
OF DEFINE */
`define CMT5 // CMT NOT \
also in // BUT TEXT IS \
also3 // CMT NOT
1 `CMT1 (nodef)
2 `CMT2 (hasdef)
3 `CMT3 (nodef)
4 `CMT4 (nodef)
5 `CMT5 (nodef)
`define NL HAS a NEW \
LINE
`NL
//======================================================================
`define msg_fatal(log, msg) \
do \
/* synopsys translate_off */ \
`ifdef NEVER \
`error "WTF" \
`else \
if (start(`__FILE__, `__LINE__)) begin \
`endif \
message(msg); \
end \
/* synopsys translate_on */ \
while(0)
`define msg_scen_(cl) cl``_scen
`define MSG_MACRO_TO_STRING(x) `"x`"
EXP: clxx_scen
`msg_scen_(clxx)
EXP: clxx_scen
`MSG_MACRO_TO_STRING(`msg_scen_(clxx))
`define mf(clx) `msg_fatal(this.log, {"Blah-", `MSG_MACRO_TO_STRING(`msg_scen_(clx)), " end"});
EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " end"}); end while(0);
`mf(clx)
//======================================================================
`define makedefine(name) \
`define def_``name This is name \
`define def_``name``_2 This is name``_2 \
`makedefine(fooed)
`ifndef def_fooed `error "No def_fooed" `endif
//`ifndef def_fooed_2 `error "No def_fooed_2" `endif
EXP: This is fooed
`def_fooed
EXP: This is fooed_2
`def_fooed_2
//======================================================================
`define NOPARAM() np
`NOPARAM()
`NOPARAM( )
//======================================================================
// It's unclear if the spec allows this; is text_macro_idenitfier before or after substitution?
`define NODS_DEFINED
`define NODS_INDIRECT(x) x
`ifndef `NODS_INDIRECT(NODS_DEFINED)
`error "Indirect failed"
`endif
`ifdef `NODS_INDIRECT(NODS_UNDEFINED)
`error "Indirect2 failed"
`endif
//======================================================================
// Metaprogramming
`define REPEAT_0(d)
`define REPEAT_1(d) d
`define REPEAT_2(d) `REPEAT_1(d)d
`define REPEAT_3(d) `REPEAT_2(d)d
`define REPEAT_4(d) `REPEAT_3(d)d
`define CONCAT(a, b) a``b
`define REPEATC(n, d) `CONCAT(`REPEAT_, n)(d)
`define REPEATT(n, d) `REPEAT_``n(d)
`REPEATC(3, hello3 )
`REPEATT(4, hello4 )
//======================================================================
// Include from stringification
`undef T_PREPROC_INC4
`define NODS_CONC_VH(m) `"m.vh`"
`include `NODS_CONC_VH(t_preproc_inc4)
`ifndef T_PREPROC_INC4 `error_here `endif
//======================================================================
// Defines doing defines
// Note the newline on the end - required to form the end of a define
`define DEFINEIT(d) d \
`define _DEFIF_Z_0 1
`define DEFIF_NZ(d,n) `undef d `ifndef _DEFIF_Z_``n `DEFINEIT(`define d 1) `endif
`DEFIF_NZ(TEMP,1)
`ifndef TEMP `error "bad" `endif
`DEFIF_NZ(TEMP,0)
`ifdef TEMP `error "bad0" `endif
Line_Preproc_Check `__LINE__
//======================================================================
// Quoted multiline - track line numbers, and insure \\n gets propagated
`define MULQUOTE "FOO \
BAR "
`define MULQUOTE2(mq) `MULQUOTE mq `MULQUOTE
Line_Preproc_Check `__LINE__
`MULQUOTE2("arg_line1 \
arg_line2")
Line_Preproc_Check `__LINE__
//======================================================================
// bug283
`define A a
`define B b
`define C c
// EXP: abc
`define C5 `A``b```C
`C5
`undef A
`undef B
`undef C
`define XTYPE sonet
`define XJOIN(__arg1, __arg2) __arg1``__arg2
`define XACTION `XJOIN(`XTYPE, _frame)
EXP: sonet_frame
`XACTION
//
`define XFRAME frame
`define XACTION2 `XJOIN(sonet_, `XFRAME)
EXP: sonet_frame
`XACTION2
// This result varies between simulators
`define sonet_frame other_frame
`define XACTION3 `XTYPE``_frame
EXP: sonet_frame
`XACTION3
// The existance of non-existance of a base define can make a difference
`define QA_b zzz
`define Q1 `QA``_b
EXP: module zzz ; endmodule
module `Q1 ; endmodule
module `Q1 ; endmodule
`define QA a
EXP: module a_b ; endmodule
module `Q1 ; endmodule
module `Q1 ; endmodule
//======================================================================
// bug311
integer/*NEED_SPACE*/foo;
//======================================================================
// bug441
module t;
//-----
// case provided
// note this does NOT escape as suggested in the mail
`define LEX_CAT(lexem1, lexem2) lexem1``lexem2
`define LEX_ESC(name) \name \
initial begin : `LEX_ESC( `LEX_CAT(a[0],_assignment) ) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) "); end
//-----
// SHOULD(simulator-dependant): Backslash doesn't prevent arguments from
// substituting and the \ staying in the expansion
// Note space after name is important so when substitute it has ending whitespace
`define ESC_CAT(name,name2) \name``_assignment_``name2 \
initial begin : `ESC_CAT( a[0],a[1] ) $write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] "); end
`undef ESC_CAT
//-----
`define CAT(a,b) a``b
`define ESC(name) \`CAT(name,suffix)
// RULE: Ignoring backslash does NOT allow an additional expansion level
// (Because ESC gets expanded then the \ has it's normal escape meaning)
initial begin : `ESC(pp) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(pp,suffix) "); end
`undef CAT `undef ESC
//-----
`define CAT(a,b) a``b
`define ESC(name) \name \
// Similar to above; \ does not allow expansion after substitution
initial begin : `ESC( `CAT(ff,bb) ) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) "); end
`undef CAT `undef ESC
//-----
`define ESC(name) \name \
// MUST: Unknown macro with backslash escape stays as escaped symbol name
initial begin : `ESC( `zzz ) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz "); end
`undef ESC
//-----
`define FOO bar
`define ESC(name) \name \
// SHOULD(simulator-dependant): Known macro with backslash escape expands
initial begin : `ESC( `FOO ) $write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO "); end
// SHOULD(simulator-dependant): Prefix breaks the above
initial begin : `ESC( xx`FOO ) $write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO "); end
`undef FOO `undef ESC
//-----
// MUST: Unknown macro not under call with backslash escape doesn't expand
`undef UNKNOWN
initial begin : \`UNKNOWN $write("GOT%%m='%m' EXP='%s'\n", "t.\\`UNKNOWN "); end
//-----
// MUST: Unknown macro not under call doesn't expand
`define DEF_NO_EXPAND error_dont_expand
initial begin : \`DEF_NO_EXPAND $write("GOT%%m='%m' EXP='%s'\n", "t.\\`DEF_NO_EXPAND "); end
`undef DEF_NO_EXPAND
//-----
// bug441 derivative
// SHOULD(simulator-dependant): Quotes doesn't prevent arguments from expanding (like backslashes above)
`define STR(name) "foo name baz"
initial $write("GOT='%s' EXP='%s'\n", `STR(bar), "foo bar baz");
`undef STR
//-----
// RULE: Because there are quotes after substituting STR, the `A does NOT expand
`define STR(name) "foo name baz"
`define A(name) boo name hiss
initial $write("GOT='%s' EXP='%s'\n", `STR(`A(bar)), "foo `A(bar) baz");
`undef A `undef STR
//----
// bug845
`define SLASHED "1//2.3"
initial $write("Slashed=`%s'\n", `SLASHED);
//----
// bug915
`define BUG915(a,b,c) \
$display("%s%s",a,`"b``c``\n`")
initial `BUG915("a1",b2,c3);
endmodule
//======================================================================
//bug1225
`define X_ITEM(SUB,UNIT) `X_STRING(SUB``UNIT)
`define X_STRING(A) `"A`"
$display(`X_ITEM(RAM,0));
$display(`X_ITEM(CPU,));
`define EMPTY
`define EMPTYP(foo)
`define SOME some
`define SOMEP(foo) foo
`define XXE_FAMILY XXE_```EMPTY
XXE_FAMILY = `XXE_FAMILY
`define XXE_```EMPTY
`ifdef XXE_
$display("XXE_ is defined");
`endif
`define XYE_FAMILY XYE_```EMPTYP(foo)
XYE_FAMILY = `XYE_FAMILY
`define XYE_```EMPTYP(foo)
`ifdef XYE_
$display("XYE_ is defined");
`endif
`define XXS_FAMILY XXS_```SOME
XXS_FAMILY = `XXS_FAMILY
`define XXS_```SOME
`ifdef XXS_some
$display("XXS_some is defined");
`endif
`define XYS_FAMILY XYS_```SOMEP(foo)
XYS_FAMILY = `XYS_FAMILY
`define XYS_```SOMEP(foo)
`ifdef XYS_foo
$display("XYS_foo is defined");
`endif
//====
`ifdef NEVER
`define NXE_FAMILY NXE_```EMPTY
NXE_FAMILY = `NXE_FAMILY
`define NXE_```EMPTY
`ifdef NXE_
$display("NXE_ is defined");
`endif
`define NYE_FAMILY NYE_```EMPTYP(foo)
NYE_FAMILY = `NYE_FAMILY
`define NYE_```EMPTYP(foo)
`ifdef NYE_
$display("NYE_ is defined");
`endif
`define NXS_FAMILY NXS_```SOME
NXS_FAMILY = `NXS_FAMILY
`define NXS_```SOME
`ifdef NXS_some
$display("NXS_some is defined");
`endif
`define NYS_FAMILY NYS_```SOMEP(foo)
NYS_FAMILY = `NYS_FAMILY
`define NYS_```SOMEP(foo)
`ifdef NYS_foo
$display("NYS_foo is defined");
`endif
`include `EMPTY
`endif // NEVER
//bug1227
`define INSTANCE(NAME) (.mySig (myInterface.``NAME),
`INSTANCE(pa5)
//======================================================================
// Stringify bug
`define hack(GRP) `dbg_hdl(UVM_LOW, (`"Functional coverage enabled: GRP`"));
`hack(paramgrp)
`define dbg_hdl(LVL, MSG) $display ("DEBUG : %s [%m]", $sformatf MSG)
`define svfcov_new(GRP) \
initial do begin `dbg_hdl(UVM_LOW, (`"Functional coverage enabled: GRP`")); end while(0)
`define simple_svfcov_clk(LBL, CLK, RST, ARG) \
covergroup LBL @(posedge CLK); \
c: coverpoint ARG iff ((RST) === 1'b1); endgroup \
LBL u_``LBL; `svfcov_new(u_``LBL)
module pcc2_cfg;
generate
`simple_svfcov_clk(a, b, c, d);
endgenerate
endmodule
//======================================================================
// IEEE mandated predefines
`undefineall // undefineall should have no effect on these
predef `SV_COV_START 0
predef `SV_COV_STOP 1
predef `SV_COV_RESET 2
predef `SV_COV_CHECK 3
predef `SV_COV_MODULE 10
predef `SV_COV_HIER 11
predef `SV_COV_ASSERTION 20
predef `SV_COV_FSM_STATE 21
predef `SV_COV_STATEMENT 22
predef `SV_COV_TOGGLE 23
predef `SV_COV_OVERFLOW -2
predef `SV_COV_ERROR -1
predef `SV_COV_NOCOV 0
predef `SV_COV_OK 1
predef `SV_COV_PARTIAL 2
//======================================================================
// After `undefineall above, for testing --dump-defines
`define WITH_ARG(a) (a)(a)
|
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2000-2001 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised
// by a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement
// from Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court 408-826-6000 (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email: [email protected]
// =============================================================================
// FILE DETAILS
// Project : pci_express_top
// File : pci_express_top.v
// Title :
// Dependencies :
// Description : Top level for core.
// =============================================================================
module pcie_eval_top (
// Clock and Reset
input wire refclkp, // 100MHz from board
input wire refclkn, // 100MHz from board
input wire rst_n,
// ASIC side pins for PCSA. These pins must exist for the PCS core.
input wire hdinp0,
input wire hdinn0,
output wire hdoutp0,
output wire hdoutn0,
input wire no_pcie_train, // Disable the training process
// For VC Inputs
input wire tx_req_vc0, // VC0 Request from User
input wire [15:0] tx_data_vc0, // VC0 Input data from user logic
input wire tx_st_vc0, // VC0 start of pkt from user logic.
input wire tx_end_vc0, // VC0 End of pkt from user logic.
input wire tx_nlfy_vc0, // VC0 End of nullified pkt from user logic.
input wire ph_buf_status_vc0, // VC0 Indicate the Full/alm.Full status of the PH buffers
input wire pd_buf_status_vc0, // VC0 Indicate PD Buffer has got space less than Max Pkt size
input wire nph_buf_status_vc0, // VC0 For NPH
input wire npd_buf_status_vc0, // VC0 For NPD
input wire ph_processed_vc0, // VC0 TL has processed one TLP Header - PH Type
input wire pd_processed_vc0, // VC0 TL has processed one TLP Data - PD TYPE
input wire nph_processed_vc0, // VC0 For NPH
input wire npd_processed_vc0, // VC0 For NPD
//---------Outputs------------
output wire tx_rdy_vc0, // VC0 TX ready indicating signal
output wire [8:0] tx_ca_ph_vc0, // VC0 Available credit for Posted Type Headers
output wire [12:0] tx_ca_pd_vc0, // VC0 For Posted - Data
output wire [8:0] tx_ca_nph_vc0, // VC0 For Non-posted - Header
output wire [12:0] tx_ca_npd_vc0, // VC0 For Non-posted - Data
output wire [8:0] tx_ca_cplh_vc0, // VC0 For Completion - Header
output wire [12:0] tx_ca_cpld_vc0, // VC0 For Completion - Data
output wire tx_ca_p_recheck_vc0, //
output wire tx_ca_cpl_recheck_vc0, //
output wire [15:0] rx_data_vc0, // VC0 Receive data
output wire rx_st_vc0, // VC0 Receive data start
output wire rx_end_vc0, // VC0 Receive data end
output wire rx_us_req_vc0 , // VC0 unsupported req received
output wire rx_malf_tlp_vc0 ,// VC0 malformed TLP in received data
// Datal Link Control SM Status
output wire dl_up, // Data Link Layer is UP
output wire sys_clk_125 // 125MHz output clock from core
);
// =============================================================================
// Define Wires & Regs
// =============================================================================
reg [19:0] rstn_cnt;
reg core_rst_n;
wire irst_n ;
wire [1:0] power_down;
wire tx_detect_rx_lb;
wire phy_status;
wire [7:0] txp_data;
wire txp_data_k;
wire txp_elec_idle;
wire txp_compliance;
wire [7:0] rxp_data;
wire rxp_data_k;
wire rxp_valid;
wire rxp_polarity;
wire rxp_elec_idle;
wire [2:0] rxp_status;
wire pclk; //250MHz clk from PCS PIPE for 8 bit data
wire [3:0] phy_ltssm_state;
wire phy_l0;
assign phy_l0 = (phy_ltssm_state == 'd3) ;
// =============================================================================
// Reset management
// =============================================================================
reg sync_rst_n0, sync_rst_n1;
wire sync_rst_n;
always @(posedge sys_clk_125 or negedge rst_n) begin
if (!rst_n) begin
sync_rst_n0 <= 0;
sync_rst_n1 <= 0;
end
else begin
sync_rst_n0 <= rst_n;
sync_rst_n1 <= sync_rst_n0;
end
end
assign sync_rst_n = sync_rst_n1;
always @(posedge sys_clk_125 or negedge sync_rst_n) begin
if (!sync_rst_n) begin
rstn_cnt <= 20'd0 ;
core_rst_n <= 1'b0 ;
end
else begin
if (rstn_cnt[19]) // 4ms in real hardware
core_rst_n <= 1'b1 ;
// synthesis translate_off
else if (rstn_cnt[7]) // 128 clocks
core_rst_n <= 1'b1 ;
// synthesis translate_on
else
rstn_cnt <= rstn_cnt + 1'b1 ;
end
end
//GSR GSR_INST (.GSR(rst_n));
PUR PUR_INST (.PUR(1'b1));
// Connect rst_n pin to GSR, pipe wrapper, core and user logic
// assign irst_n = rst_n ;
// Connect rst_n pin to pipe wrapper, 4ms delayed rst_n to core and user logic
//assign irst_n = core_rst_n ;
// =============================================================================
// SERDES/PCS instantiation in PIPE mode
// =============================================================================
pcs_pipe_top u1_pcs_pipe (
.refclkp ( refclkp ),
.refclkn ( refclkn ),
// .ffc_quad_rst ( ~rst_n ),
.RESET_n ( rst_n ),
.pcie_ip_rstn ( irst_n ),
.hdinp0 ( hdinp0 ),
.hdinn0 ( hdinn0 ),
.hdoutp0 ( hdoutp0 ),
.hdoutn0 ( hdoutn0 ),
.TxData_0 ( txp_data ),
.TxDataK_0 ( txp_data_k ),
.TxCompliance_0 ( txp_compliance ),
.TxElecIdle_0 ( txp_elec_idle ),
.RxData_0 ( rxp_data ),
.RxDataK_0 ( rxp_data_k ),
.RxValid_0 ( rxp_valid ),
.RxPolarity_0 ( rxp_polarity ),
.RxElecIdle_0 ( rxp_elec_idle ),
.RxStatus_0 ( rxp_status ),
.scisel_0 ( 1'b0 ),
.scien_0 ( 1'b0 ),
.sciwritedata ( 8'h0 ),
.sciaddress ( 6'h0 ),
.scireaddata ( ),
.scienaux ( 1'b0 ),
.sciselaux ( 1'b0 ),
.scird ( 1'b0 ),
.sciwstn ( 1'b0 ),
.ffs_plol ( ),
.ffs_rlol_ch0 ( ),
.flip_lanes ( 1'b0 ),
.PCLK ( pclk ),
.PCLK_by_2 ( sys_clk_125 ),
.TxDetectRx_Loopback ( tx_detect_rx_lb ),
.PhyStatus ( phy_status ),
.PowerDown ( power_down ),
.phy_l0 ( phy_l0 ),
.phy_cfgln ( 4'b0000 ), //Not required (unused in X1 mode)
.ctc_disable ( 1'b0 )
);
// =============================================================================
// PCI Express Core
// =============================================================================
pcie u1_dut(
// Clock and Reset
.sys_clk_250 ( pclk ) ,
.sys_clk_125 ( sys_clk_125 ) ,
.rst_n ( irst_n ),
.inta_n ( 1'b1 ),
.msi ( 8'd0 ),
.vendor_id ( 16'd0 ),
.device_id ( 16'd0 ),
.rev_id ( 8'd0 ),
.class_code ( 24'd0 ),
.subsys_ven_id ( 16'd0 ),
.subsys_id ( 16'd0 ),
.load_id ( 1'b1 ),
// Inputs
.force_lsm_active ( 1'b0 ),
.force_rec_ei ( 1'b0 ),
.force_phy_status ( 1'b0 ),
.force_disable_scr ( 1'b0 ),
.hl_snd_beacon ( 1'b0 ),
.hl_disable_scr ( 1'b0 ),
.hl_gto_dis ( 1'b0 ),
.hl_gto_det ( 1'b0 ),
.hl_gto_hrst ( 1'b0 ),
.hl_gto_l0stx ( 1'b0 ),
.hl_gto_l1 ( 1'b0 ),
.hl_gto_l2 ( 1'b0 ),
.hl_gto_l0stxfts ( 1'b0 ),
.hl_gto_lbk ( 1'b0 ),
.hl_gto_rcvry ( 1'b0 ),
.hl_gto_cfg ( 1'b0 ),
.no_pcie_train ( no_pcie_train ),
// Power Management Interface
.tx_dllp_val ( 2'd0 ),
.tx_pmtype ( 3'd0 ),
.tx_vsd_data ( 24'd0 ),
.tx_req_vc0 ( tx_req_vc0 ),
.tx_data_vc0 ( tx_data_vc0 ),
.tx_st_vc0 ( tx_st_vc0 ),
.tx_end_vc0 ( tx_end_vc0 ),
.tx_nlfy_vc0 ( tx_nlfy_vc0 ),
.ph_buf_status_vc0 ( ph_buf_status_vc0 ),
.pd_buf_status_vc0 ( pd_buf_status_vc0 ),
.nph_buf_status_vc0 ( nph_buf_status_vc0 ),
.npd_buf_status_vc0 ( npd_buf_status_vc0 ),
.ph_processed_vc0 ( ph_processed_vc0 ),
.pd_processed_vc0 ( pd_processed_vc0 ),
.nph_processed_vc0 ( nph_processed_vc0 ),
.npd_processed_vc0 ( npd_processed_vc0 ),
.pd_num_vc0 ( 8'd1 ),
.npd_num_vc0 ( 8'd1 ),
// From External PHY (PIPE I/F)
.rxp_data ( rxp_data ),
.rxp_data_k ( rxp_data_k ),
.rxp_valid ( rxp_valid ),
.rxp_elec_idle ( rxp_elec_idle ),
.rxp_status ( rxp_status ),
.phy_status ( phy_status),
// From User logic
.cmpln_tout ( 1'b0 ),
.cmpltr_abort_np ( 1'b0 ),
.cmpltr_abort_p ( 1'b0 ),
.unexp_cmpln ( 1'b0 ),
.ur_np_ext ( 1'b0 ),
.ur_p_ext ( 1'b0 ),
.np_req_pend ( 1'b0 ),
.pme_status ( 1'b0 ),
.tx_lbk_data ( 16'd0 ),
.tx_lbk_kcntl ( 2'd0 ),
.tx_lbk_rdy ( ),
.rx_lbk_data ( ),
.rx_lbk_kcntl ( ),
// Power Management
.tx_dllp_sent ( ),
.rxdp_pmd_type ( ),
.rxdp_vsd_data ( ),
.rxdp_dllp_val ( ),
//-------- Outputs
// To External PHY (PIPE I/F)
.txp_data ( txp_data ),
.txp_data_k ( txp_data_k ),
.txp_elec_idle ( txp_elec_idle ),
.txp_compliance ( txp_compliance ),
.rxp_polarity ( rxp_polarity ),
.txp_detect_rx_lb ( tx_detect_rx_lb ),
.reset_n ( ),
.power_down ( power_down ),
// From TX User Interface
.phy_ltssm_state ( phy_ltssm_state ),
.phy_ltssm_substate ( ),
.phy_pol_compliance ( ),
.tx_rdy_vc0 ( tx_rdy_vc0),
.tx_ca_ph_vc0 ( tx_ca_ph_vc0),
.tx_ca_pd_vc0 ( tx_ca_pd_vc0),
.tx_ca_nph_vc0 ( tx_ca_nph_vc0),
.tx_ca_npd_vc0 ( tx_ca_npd_vc0),
.tx_ca_cplh_vc0 ( tx_ca_cplh_vc0),
.tx_ca_cpld_vc0 ( tx_ca_cpld_vc0),
.tx_ca_p_recheck_vc0 ( tx_ca_p_recheck_vc0 ),
.tx_ca_cpl_recheck_vc0 ( tx_ca_cpl_recheck_vc0 ),
.rx_data_vc0 ( rx_data_vc0),
.rx_st_vc0 ( rx_st_vc0),
.rx_end_vc0 ( rx_end_vc0),
.rx_us_req_vc0 ( rx_us_req_vc0 ),
.rx_malf_tlp_vc0 ( rx_malf_tlp_vc0 ),
.rx_bar_hit ( ),
.mm_enable ( ),
.msi_enable ( ),
// From Config Registers
.bus_num ( ),
.dev_num ( ),
.func_num ( ),
.pm_power_state ( ),
.pme_en ( ),
.cmd_reg_out ( ),
.dev_cntl_out ( ),
.lnk_cntl_out ( ),
// To ASPM implementation outside the IP
.tx_rbuf_empty ( ),
.tx_dllp_pend ( ),
.rx_tlp_rcvd ( ),
// Datal Link Control SM Status
.dl_inactive ( ),
.dl_init ( ),
.dl_active ( ),
.dl_up ( dl_up )
);
endmodule
|
`include "./simple_fifo.v"
`include "./fifo_fwft_adapter.v"
module fifo_fwft # (
parameter DATA_WIDTH = 0,
parameter DEPTH_WIDTH = 0
) (
input wire clk,
input wire rst,
input wire [DATA_WIDTH-1:0] din,
input wire wr_en,
output wire full,
output wire [DATA_WIDTH-1:0] dout,
input wire rd_en,
output wire empty,
output wire valid
);
wire [DATA_WIDTH-1:0] fifo_dout;
wire fifo_empty;
wire fifo_rd_en;
// orig_fifo is just a normal (non-FWFT) synchronous or asynchronous FIFO
simple_fifo # (
.DEPTH_WIDTH (DEPTH_WIDTH),
.DATA_WIDTH (DATA_WIDTH )
) fifo0 (
.clk (clk ),
.rst (rst ),
.rd_en (fifo_rd_en),
.rd_data (fifo_dout ),
.empty (fifo_empty),
.wr_en (wr_en ),
.wr_data (din ),
.full (full )
);
fifo_fwft_adapter # (
.DATA_WIDTH (DATA_WIDTH)
) fwft_adapter (
.clk (clk ),
.rst (rst ),
.rd_en (rd_en ),
.fifo_empty (fifo_empty),
.fifo_rd_en (fifo_rd_en),
.fifo_dout (fifo_dout ),
.dout (dout ),
.empty (empty ),
.valid (valid )
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:32:33 05/12/2015
// Design Name:
// Module Name: IF_ID
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module IF_ID(clk,rst,if_pcplus4, stall, BJ,
if_instr,id_pcplus4, id_instr,if_pc,id_pc
);
input clk,rst,stall, BJ;
input wire [31:0] if_pcplus4,if_instr,if_pc;
output reg [31:0] id_pcplus4,id_instr,id_pc;
always @(posedge clk or posedge rst)
begin
if(rst)
begin
id_pcplus4 <= 4;
id_instr <= 32'b100000;
id_pc<=0;
end
else if(stall | BJ)
begin
id_pcplus4 <= if_pcplus4;
id_instr <= 32'b100000;
id_pc<=if_pc;
end
else
begin
id_pcplus4 <= if_pcplus4;
id_instr <= if_instr;
id_pc<=if_pc;
end
end
endmodule
//module IF_ID(clk,rst,stall,if_pcplus4, if_instr,id_pcplus4, id_instr
// );
// input clk,rst, stall;
// input wire [31:0] if_pcplus4,if_instr;
// output reg [31:0] id_pcplus4,id_instr;
//
// always @(posedge clk or posedge rst)
// begin
// if(rst)
// begin
// id_pcplus4 <= 4;
// id_instr <= 32'b100000;
// end
// else if(stall)
// begin
// id_pcplus4 <= if_pcplus4-4;
// id_instr <= 32'b100000;
// end
// else
// begin
// id_pcplus4 <= if_pcplus4;
// id_instr <= if_instr;
// end
// end
//endmodule
|
// megafunction wizard: %LPM_MUX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_MUX
// ============================================================
// File Name: counterselect.v
// Megafunction Name(s):
// LPM_MUX
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.0 Build 200 06/17/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module counterselect (
data0x,
data1x,
data2x,
data3x,
sel,
result);
input [20:0] data0x;
input [20:0] data1x;
input [20:0] data2x;
input [20:0] data3x;
input [1:0] sel;
output [20:0] result;
wire [20:0] sub_wire5;
wire [20:0] sub_wire4 = data3x[20:0];
wire [20:0] sub_wire3 = data2x[20:0];
wire [20:0] sub_wire2 = data1x[20:0];
wire [20:0] sub_wire0 = data0x[20:0];
wire [83:0] sub_wire1 = {sub_wire4, sub_wire3, sub_wire2, sub_wire0};
wire [20:0] result = sub_wire5[20:0];
lpm_mux LPM_MUX_component (
.data (sub_wire1),
.sel (sel),
.result (sub_wire5)
// synopsys translate_off
,
.aclr (),
.clken (),
.clock ()
// synopsys translate_on
);
defparam
LPM_MUX_component.lpm_size = 4,
LPM_MUX_component.lpm_type = "LPM_MUX",
LPM_MUX_component.lpm_width = 21,
LPM_MUX_component.lpm_widths = 2;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "21"
// Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2"
// Retrieval info: USED_PORT: data0x 0 0 21 0 INPUT NODEFVAL "data0x[20..0]"
// Retrieval info: USED_PORT: data1x 0 0 21 0 INPUT NODEFVAL "data1x[20..0]"
// Retrieval info: USED_PORT: data2x 0 0 21 0 INPUT NODEFVAL "data2x[20..0]"
// Retrieval info: USED_PORT: data3x 0 0 21 0 INPUT NODEFVAL "data3x[20..0]"
// Retrieval info: USED_PORT: result 0 0 21 0 OUTPUT NODEFVAL "result[20..0]"
// Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL "sel[1..0]"
// Retrieval info: CONNECT: @data 0 0 21 0 data0x 0 0 21 0
// Retrieval info: CONNECT: @data 0 0 21 21 data1x 0 0 21 0
// Retrieval info: CONNECT: @data 0 0 21 42 data2x 0 0 21 0
// Retrieval info: CONNECT: @data 0 0 21 63 data3x 0 0 21 0
// Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0
// Retrieval info: CONNECT: result 0 0 21 0 @result 0 0 21 0
// Retrieval info: GEN_FILE: TYPE_NORMAL counterselect.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL counterselect.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL counterselect.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL counterselect.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL counterselect_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL counterselect_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2018 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2018.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / 288K-bit High-Density Base Memory Building Block
// /___/ /\ Filename : URAM288_BASE.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 10/31/2014 - Initial functional version
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module URAM288_BASE #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter integer AUTO_SLEEP_LATENCY = 8,
parameter integer AVG_CONS_INACTIVE_CYCLES = 10,
parameter BWE_MODE_A = "PARITY_INTERLEAVED",
parameter BWE_MODE_B = "PARITY_INTERLEAVED",
parameter EN_AUTO_SLEEP_MODE = "FALSE",
parameter EN_ECC_RD_A = "FALSE",
parameter EN_ECC_RD_B = "FALSE",
parameter EN_ECC_WR_A = "FALSE",
parameter EN_ECC_WR_B = "FALSE",
parameter IREG_PRE_A = "FALSE",
parameter IREG_PRE_B = "FALSE",
parameter [0:0] IS_CLK_INVERTED = 1'b0,
parameter [0:0] IS_EN_A_INVERTED = 1'b0,
parameter [0:0] IS_EN_B_INVERTED = 1'b0,
parameter [0:0] IS_RDB_WR_A_INVERTED = 1'b0,
parameter [0:0] IS_RDB_WR_B_INVERTED = 1'b0,
parameter [0:0] IS_RST_A_INVERTED = 1'b0,
parameter [0:0] IS_RST_B_INVERTED = 1'b0,
parameter OREG_A = "FALSE",
parameter OREG_B = "FALSE",
parameter OREG_ECC_A = "FALSE",
parameter OREG_ECC_B = "FALSE",
parameter RST_MODE_A = "SYNC",
parameter RST_MODE_B = "SYNC",
parameter USE_EXT_CE_A = "FALSE",
parameter USE_EXT_CE_B = "FALSE"
)(
output DBITERR_A,
output DBITERR_B,
output [71:0] DOUT_A,
output [71:0] DOUT_B,
output SBITERR_A,
output SBITERR_B,
input [22:0] ADDR_A,
input [22:0] ADDR_B,
input [8:0] BWE_A,
input [8:0] BWE_B,
input CLK,
input [71:0] DIN_A,
input [71:0] DIN_B,
input EN_A,
input EN_B,
input INJECT_DBITERR_A,
input INJECT_DBITERR_B,
input INJECT_SBITERR_A,
input INJECT_SBITERR_B,
input OREG_CE_A,
input OREG_CE_B,
input OREG_ECC_CE_A,
input OREG_ECC_CE_B,
input RDB_WR_A,
input RDB_WR_B,
input RST_A,
input RST_B,
input SLEEP
);
// define constants
localparam MODULE_NAME = "URAM288_BASE";
// Parameter encodings and registers
localparam BWE_MODE_A_PARITY_INDEPENDENT = 1;
localparam BWE_MODE_A_PARITY_INTERLEAVED = 0;
localparam BWE_MODE_B_PARITY_INDEPENDENT = 1;
localparam BWE_MODE_B_PARITY_INTERLEAVED = 0;
localparam EN_AUTO_SLEEP_MODE_FALSE = 0;
localparam EN_AUTO_SLEEP_MODE_TRUE = 1;
localparam EN_ECC_RD_A_FALSE = 0;
localparam EN_ECC_RD_A_TRUE = 1;
localparam EN_ECC_RD_B_FALSE = 0;
localparam EN_ECC_RD_B_TRUE = 1;
localparam EN_ECC_WR_A_FALSE = 0;
localparam EN_ECC_WR_A_TRUE = 1;
localparam EN_ECC_WR_B_FALSE = 0;
localparam EN_ECC_WR_B_TRUE = 1;
localparam IREG_PRE_A_FALSE = 0;
localparam IREG_PRE_A_TRUE = 1;
localparam IREG_PRE_B_FALSE = 0;
localparam IREG_PRE_B_TRUE = 1;
localparam OREG_A_FALSE = 0;
localparam OREG_A_TRUE = 1;
localparam OREG_B_FALSE = 0;
localparam OREG_B_TRUE = 1;
localparam OREG_ECC_A_FALSE = 0;
localparam OREG_ECC_A_TRUE = 1;
localparam OREG_ECC_B_FALSE = 0;
localparam OREG_ECC_B_TRUE = 1;
localparam RST_MODE_A_ASYNC = 1;
localparam RST_MODE_A_SYNC = 0;
localparam RST_MODE_B_ASYNC = 1;
localparam RST_MODE_B_SYNC = 0;
localparam USE_EXT_CE_A_FALSE = 0;
localparam USE_EXT_CE_A_TRUE = 1;
localparam USE_EXT_CE_B_FALSE = 0;
localparam USE_EXT_CE_B_TRUE = 1;
reg trig_attr;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "URAM288_BASE_dr.v"
`else
reg [31:0] AUTO_SLEEP_LATENCY_REG = AUTO_SLEEP_LATENCY;
reg [31:0] AVG_CONS_INACTIVE_CYCLES_REG = AVG_CONS_INACTIVE_CYCLES;
reg [144:1] BWE_MODE_A_REG = BWE_MODE_A;
reg [144:1] BWE_MODE_B_REG = BWE_MODE_B;
reg [40:1] EN_AUTO_SLEEP_MODE_REG = EN_AUTO_SLEEP_MODE;
reg [40:1] EN_ECC_RD_A_REG = EN_ECC_RD_A;
reg [40:1] EN_ECC_RD_B_REG = EN_ECC_RD_B;
reg [40:1] EN_ECC_WR_A_REG = EN_ECC_WR_A;
reg [40:1] EN_ECC_WR_B_REG = EN_ECC_WR_B;
reg [40:1] IREG_PRE_A_REG = IREG_PRE_A;
reg [40:1] IREG_PRE_B_REG = IREG_PRE_B;
reg [0:0] IS_CLK_INVERTED_REG = IS_CLK_INVERTED;
reg [0:0] IS_EN_A_INVERTED_REG = IS_EN_A_INVERTED;
reg [0:0] IS_EN_B_INVERTED_REG = IS_EN_B_INVERTED;
reg [0:0] IS_RDB_WR_A_INVERTED_REG = IS_RDB_WR_A_INVERTED;
reg [0:0] IS_RDB_WR_B_INVERTED_REG = IS_RDB_WR_B_INVERTED;
reg [0:0] IS_RST_A_INVERTED_REG = IS_RST_A_INVERTED;
reg [0:0] IS_RST_B_INVERTED_REG = IS_RST_B_INVERTED;
reg [40:1] OREG_A_REG = OREG_A;
reg [40:1] OREG_B_REG = OREG_B;
reg [40:1] OREG_ECC_A_REG = OREG_ECC_A;
reg [40:1] OREG_ECC_B_REG = OREG_ECC_B;
reg [40:1] RST_MODE_A_REG = RST_MODE_A;
reg [40:1] RST_MODE_B_REG = RST_MODE_B;
reg [40:1] USE_EXT_CE_A_REG = USE_EXT_CE_A;
reg [40:1] USE_EXT_CE_B_REG = USE_EXT_CE_B;
`endif
`ifdef XIL_XECLIB
wire [3:0] AUTO_SLEEP_LATENCY_BIN;
wire [16:0] AVG_CONS_INACTIVE_CYCLES_BIN;
wire BWE_MODE_A_BIN;
wire BWE_MODE_B_BIN;
wire EN_AUTO_SLEEP_MODE_BIN;
wire EN_ECC_RD_A_BIN;
wire EN_ECC_RD_B_BIN;
wire EN_ECC_WR_A_BIN;
wire EN_ECC_WR_B_BIN;
wire IREG_PRE_A_BIN;
wire IREG_PRE_B_BIN;
wire OREG_A_BIN;
wire OREG_B_BIN;
wire OREG_ECC_A_BIN;
wire OREG_ECC_B_BIN;
wire RST_MODE_A_BIN;
wire RST_MODE_B_BIN;
wire USE_EXT_CE_A_BIN;
wire USE_EXT_CE_B_BIN;
`else
reg [3:0] AUTO_SLEEP_LATENCY_BIN;
reg [16:0] AVG_CONS_INACTIVE_CYCLES_BIN;
reg BWE_MODE_A_BIN;
reg BWE_MODE_B_BIN;
reg EN_AUTO_SLEEP_MODE_BIN;
reg EN_ECC_RD_A_BIN;
reg EN_ECC_RD_B_BIN;
reg EN_ECC_WR_A_BIN;
reg EN_ECC_WR_B_BIN;
reg IREG_PRE_A_BIN;
reg IREG_PRE_B_BIN;
reg OREG_A_BIN;
reg OREG_B_BIN;
reg OREG_ECC_A_BIN;
reg OREG_ECC_B_BIN;
reg RST_MODE_A_BIN;
reg RST_MODE_B_BIN;
reg USE_EXT_CE_A_BIN;
reg USE_EXT_CE_B_BIN;
`endif
`ifdef XIL_XECLIB
reg glblGSR = 1'b0;
`else
tri0 glblGSR = glbl.GSR;
`endif
wire CLK_in;
wire EN_A_in;
wire EN_B_in;
wire INJECT_DBITERR_A_in;
wire INJECT_DBITERR_B_in;
wire INJECT_SBITERR_A_in;
wire INJECT_SBITERR_B_in;
wire OREG_CE_A_in;
wire OREG_CE_B_in;
wire OREG_ECC_CE_A_in;
wire OREG_ECC_CE_B_in;
wire RDB_WR_A_in;
wire RDB_WR_B_in;
wire RST_A_in;
wire RST_B_in;
wire SLEEP_in;
wire [22:0] ADDR_A_in;
wire [22:0] ADDR_B_in;
wire [71:0] DIN_A_in;
wire [71:0] DIN_B_in;
wire [8:0] BWE_A_in;
wire [8:0] BWE_B_in;
`ifdef XIL_TIMING
wire CLK_delay;
wire EN_A_delay;
wire EN_B_delay;
wire INJECT_DBITERR_A_delay;
wire INJECT_DBITERR_B_delay;
wire INJECT_SBITERR_A_delay;
wire INJECT_SBITERR_B_delay;
wire OREG_CE_A_delay;
wire OREG_CE_B_delay;
wire OREG_ECC_CE_A_delay;
wire OREG_ECC_CE_B_delay;
wire RDB_WR_A_delay;
wire RDB_WR_B_delay;
wire RST_A_delay;
wire RST_B_delay;
wire SLEEP_delay;
wire [22:0] ADDR_A_delay;
wire [22:0] ADDR_B_delay;
wire [71:0] DIN_A_delay;
wire [71:0] DIN_B_delay;
wire [8:0] BWE_A_delay;
wire [8:0] BWE_B_delay;
`endif
`ifdef XIL_TIMING
assign ADDR_A_in = ADDR_A_delay;
assign ADDR_B_in = ADDR_B_delay;
assign BWE_A_in = BWE_A_delay;
assign BWE_B_in = BWE_B_delay;
assign CLK_in = (CLK !== 1'bz) && (CLK_delay ^ IS_CLK_INVERTED_REG); // rv 0
assign DIN_A_in = DIN_A_delay;
assign DIN_B_in = DIN_B_delay;
assign EN_A_in = (EN_A !== 1'bz) && (EN_A_delay ^ IS_EN_A_INVERTED_REG); // rv 0
assign EN_B_in = (EN_B !== 1'bz) && (EN_B_delay ^ IS_EN_B_INVERTED_REG); // rv 0
assign INJECT_DBITERR_A_in = (INJECT_DBITERR_A !== 1'bz) && INJECT_DBITERR_A_delay; // rv 0
assign INJECT_DBITERR_B_in = (INJECT_DBITERR_B !== 1'bz) && INJECT_DBITERR_B_delay; // rv 0
assign INJECT_SBITERR_A_in = (INJECT_SBITERR_A !== 1'bz) && INJECT_SBITERR_A_delay; // rv 0
assign INJECT_SBITERR_B_in = (INJECT_SBITERR_B !== 1'bz) && INJECT_SBITERR_B_delay; // rv 0
assign OREG_CE_A_in = (OREG_CE_A === 1'bz) || OREG_CE_A_delay; // rv 1
assign OREG_CE_B_in = (OREG_CE_B === 1'bz) || OREG_CE_B_delay; // rv 1
assign OREG_ECC_CE_A_in = (OREG_ECC_CE_A === 1'bz) || OREG_ECC_CE_A_delay; // rv 1
assign OREG_ECC_CE_B_in = (OREG_ECC_CE_B === 1'bz) || OREG_ECC_CE_B_delay; // rv 1
assign RDB_WR_A_in = (RDB_WR_A !== 1'bz) && (RDB_WR_A_delay ^ IS_RDB_WR_A_INVERTED_REG); // rv 0
assign RDB_WR_B_in = (RDB_WR_B !== 1'bz) && (RDB_WR_B_delay ^ IS_RDB_WR_B_INVERTED_REG); // rv 0
assign RST_A_in = (RST_A !== 1'bz) && (RST_A_delay ^ IS_RST_A_INVERTED_REG); // rv 0
assign RST_B_in = (RST_B !== 1'bz) && (RST_B_delay ^ IS_RST_B_INVERTED_REG); // rv 0
assign SLEEP_in = (SLEEP !== 1'bz) && SLEEP_delay; // rv 0
`else
assign ADDR_A_in = ADDR_A;
assign ADDR_B_in = ADDR_B;
assign BWE_A_in[0] = (BWE_A[0] === 1'bz) || BWE_A[0]; // rv 1
assign BWE_A_in[1] = (BWE_A[1] === 1'bz) || BWE_A[1]; // rv 1
assign BWE_A_in[2] = (BWE_A[2] === 1'bz) || BWE_A[2]; // rv 1
assign BWE_A_in[3] = (BWE_A[3] === 1'bz) || BWE_A[3]; // rv 1
assign BWE_A_in[4] = (BWE_A[4] === 1'bz) || BWE_A[4]; // rv 1
assign BWE_A_in[5] = (BWE_A[5] === 1'bz) || BWE_A[5]; // rv 1
assign BWE_A_in[6] = (BWE_A[6] === 1'bz) || BWE_A[6]; // rv 1
assign BWE_A_in[7] = (BWE_A[7] === 1'bz) || BWE_A[7]; // rv 1
assign BWE_A_in[8] = (BWE_A[8] === 1'bz) || BWE_A[8]; // rv 1
assign BWE_B_in[0] = (BWE_B[0] === 1'bz) || BWE_B[0]; // rv 1
assign BWE_B_in[1] = (BWE_B[1] === 1'bz) || BWE_B[1]; // rv 1
assign BWE_B_in[2] = (BWE_B[2] === 1'bz) || BWE_B[2]; // rv 1
assign BWE_B_in[3] = (BWE_B[3] === 1'bz) || BWE_B[3]; // rv 1
assign BWE_B_in[4] = (BWE_B[4] === 1'bz) || BWE_B[4]; // rv 1
assign BWE_B_in[5] = (BWE_B[5] === 1'bz) || BWE_B[5]; // rv 1
assign BWE_B_in[6] = (BWE_B[6] === 1'bz) || BWE_B[6]; // rv 1
assign BWE_B_in[7] = (BWE_B[7] === 1'bz) || BWE_B[7]; // rv 1
assign BWE_B_in[8] = (BWE_B[8] === 1'bz) || BWE_B[8]; // rv 1
assign CLK_in = (CLK !== 1'bz) && (CLK ^ IS_CLK_INVERTED_REG); // rv 0
assign DIN_A_in = DIN_A;
assign DIN_B_in = DIN_B;
assign EN_A_in = (EN_A !== 1'bz) && (EN_A ^ IS_EN_A_INVERTED_REG); // rv 0
assign EN_B_in = (EN_B !== 1'bz) && (EN_B ^ IS_EN_B_INVERTED_REG); // rv 0
assign INJECT_DBITERR_A_in = (INJECT_DBITERR_A !== 1'bz) && INJECT_DBITERR_A; // rv 0
assign INJECT_DBITERR_B_in = (INJECT_DBITERR_B !== 1'bz) && INJECT_DBITERR_B; // rv 0
assign INJECT_SBITERR_A_in = (INJECT_SBITERR_A !== 1'bz) && INJECT_SBITERR_A; // rv 0
assign INJECT_SBITERR_B_in = (INJECT_SBITERR_B !== 1'bz) && INJECT_SBITERR_B; // rv 0
assign OREG_CE_A_in = (OREG_CE_A === 1'bz) || OREG_CE_A; // rv 1
assign OREG_CE_B_in = (OREG_CE_B === 1'bz) || OREG_CE_B; // rv 1
assign OREG_ECC_CE_A_in = (OREG_ECC_CE_A === 1'bz) || OREG_ECC_CE_A; // rv 1
assign OREG_ECC_CE_B_in = (OREG_ECC_CE_B === 1'bz) || OREG_ECC_CE_B; // rv 1
assign RDB_WR_A_in = (RDB_WR_A !== 1'bz) && (RDB_WR_A ^ IS_RDB_WR_A_INVERTED_REG); // rv 0
assign RDB_WR_B_in = (RDB_WR_B !== 1'bz) && (RDB_WR_B ^ IS_RDB_WR_B_INVERTED_REG); // rv 0
assign RST_A_in = (RST_A !== 1'bz) && (RST_A ^ IS_RST_A_INVERTED_REG); // rv 0
assign RST_B_in = (RST_B !== 1'bz) && (RST_B ^ IS_RST_B_INVERTED_REG); // rv 0
assign SLEEP_in = (SLEEP !== 1'bz) && SLEEP; // rv 0
`endif
`ifndef XIL_XECLIB
reg attr_test;
reg attr_err;
initial begin
trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
attr_test = 1'b1;
`else
attr_test = 1'b0;
`endif
attr_err = 1'b0;
#1;
trig_attr = ~trig_attr;
end
`endif
`ifdef XIL_XECLIB
assign AUTO_SLEEP_LATENCY_BIN = AUTO_SLEEP_LATENCY_REG[3:0];
assign AVG_CONS_INACTIVE_CYCLES_BIN = AVG_CONS_INACTIVE_CYCLES_REG[16:0];
assign BWE_MODE_A_BIN =
(BWE_MODE_A_REG == "PARITY_INTERLEAVED") ? BWE_MODE_A_PARITY_INTERLEAVED :
(BWE_MODE_A_REG == "PARITY_INDEPENDENT") ? BWE_MODE_A_PARITY_INDEPENDENT :
BWE_MODE_A_PARITY_INTERLEAVED;
assign BWE_MODE_B_BIN =
(BWE_MODE_B_REG == "PARITY_INTERLEAVED") ? BWE_MODE_B_PARITY_INTERLEAVED :
(BWE_MODE_B_REG == "PARITY_INDEPENDENT") ? BWE_MODE_B_PARITY_INDEPENDENT :
BWE_MODE_B_PARITY_INTERLEAVED;
assign EN_AUTO_SLEEP_MODE_BIN =
(EN_AUTO_SLEEP_MODE_REG == "FALSE") ? EN_AUTO_SLEEP_MODE_FALSE :
(EN_AUTO_SLEEP_MODE_REG == "TRUE") ? EN_AUTO_SLEEP_MODE_TRUE :
EN_AUTO_SLEEP_MODE_FALSE;
assign EN_ECC_RD_A_BIN =
(EN_ECC_RD_A_REG == "FALSE") ? EN_ECC_RD_A_FALSE :
(EN_ECC_RD_A_REG == "TRUE") ? EN_ECC_RD_A_TRUE :
EN_ECC_RD_A_FALSE;
assign EN_ECC_RD_B_BIN =
(EN_ECC_RD_B_REG == "FALSE") ? EN_ECC_RD_B_FALSE :
(EN_ECC_RD_B_REG == "TRUE") ? EN_ECC_RD_B_TRUE :
EN_ECC_RD_B_FALSE;
assign EN_ECC_WR_A_BIN =
(EN_ECC_WR_A_REG == "FALSE") ? EN_ECC_WR_A_FALSE :
(EN_ECC_WR_A_REG == "TRUE") ? EN_ECC_WR_A_TRUE :
EN_ECC_WR_A_FALSE;
assign EN_ECC_WR_B_BIN =
(EN_ECC_WR_B_REG == "FALSE") ? EN_ECC_WR_B_FALSE :
(EN_ECC_WR_B_REG == "TRUE") ? EN_ECC_WR_B_TRUE :
EN_ECC_WR_B_FALSE;
assign IREG_PRE_A_BIN =
(IREG_PRE_A_REG == "FALSE") ? IREG_PRE_A_FALSE :
(IREG_PRE_A_REG == "TRUE") ? IREG_PRE_A_TRUE :
IREG_PRE_A_FALSE;
assign IREG_PRE_B_BIN =
(IREG_PRE_B_REG == "FALSE") ? IREG_PRE_B_FALSE :
(IREG_PRE_B_REG == "TRUE") ? IREG_PRE_B_TRUE :
IREG_PRE_B_FALSE;
assign OREG_A_BIN =
(OREG_A_REG == "FALSE") ? OREG_A_FALSE :
(OREG_A_REG == "TRUE") ? OREG_A_TRUE :
OREG_A_FALSE;
assign OREG_B_BIN =
(OREG_B_REG == "FALSE") ? OREG_B_FALSE :
(OREG_B_REG == "TRUE") ? OREG_B_TRUE :
OREG_B_FALSE;
assign OREG_ECC_A_BIN =
(OREG_ECC_A_REG == "FALSE") ? OREG_ECC_A_FALSE :
(OREG_ECC_A_REG == "TRUE") ? OREG_ECC_A_TRUE :
OREG_ECC_A_FALSE;
assign OREG_ECC_B_BIN =
(OREG_ECC_B_REG == "FALSE") ? OREG_ECC_B_FALSE :
(OREG_ECC_B_REG == "TRUE") ? OREG_ECC_B_TRUE :
OREG_ECC_B_FALSE;
assign RST_MODE_A_BIN =
(RST_MODE_A_REG == "SYNC") ? RST_MODE_A_SYNC :
(RST_MODE_A_REG == "ASYNC") ? RST_MODE_A_ASYNC :
RST_MODE_A_SYNC;
assign RST_MODE_B_BIN =
(RST_MODE_B_REG == "SYNC") ? RST_MODE_B_SYNC :
(RST_MODE_B_REG == "ASYNC") ? RST_MODE_B_ASYNC :
RST_MODE_B_SYNC;
assign USE_EXT_CE_A_BIN =
(USE_EXT_CE_A_REG == "FALSE") ? USE_EXT_CE_A_FALSE :
(USE_EXT_CE_A_REG == "TRUE") ? USE_EXT_CE_A_TRUE :
USE_EXT_CE_A_FALSE;
assign USE_EXT_CE_B_BIN =
(USE_EXT_CE_B_REG == "FALSE") ? USE_EXT_CE_B_FALSE :
(USE_EXT_CE_B_REG == "TRUE") ? USE_EXT_CE_B_TRUE :
USE_EXT_CE_B_FALSE;
`else
always @ (trig_attr) begin
#1;
AUTO_SLEEP_LATENCY_BIN = AUTO_SLEEP_LATENCY_REG[3:0];
AVG_CONS_INACTIVE_CYCLES_BIN = AVG_CONS_INACTIVE_CYCLES_REG[16:0];
BWE_MODE_A_BIN =
(BWE_MODE_A_REG == "PARITY_INTERLEAVED") ? BWE_MODE_A_PARITY_INTERLEAVED :
(BWE_MODE_A_REG == "PARITY_INDEPENDENT") ? BWE_MODE_A_PARITY_INDEPENDENT :
BWE_MODE_A_PARITY_INTERLEAVED;
BWE_MODE_B_BIN =
(BWE_MODE_B_REG == "PARITY_INTERLEAVED") ? BWE_MODE_B_PARITY_INTERLEAVED :
(BWE_MODE_B_REG == "PARITY_INDEPENDENT") ? BWE_MODE_B_PARITY_INDEPENDENT :
BWE_MODE_B_PARITY_INTERLEAVED;
EN_AUTO_SLEEP_MODE_BIN =
(EN_AUTO_SLEEP_MODE_REG == "FALSE") ? EN_AUTO_SLEEP_MODE_FALSE :
(EN_AUTO_SLEEP_MODE_REG == "TRUE") ? EN_AUTO_SLEEP_MODE_TRUE :
EN_AUTO_SLEEP_MODE_FALSE;
EN_ECC_RD_A_BIN =
(EN_ECC_RD_A_REG == "FALSE") ? EN_ECC_RD_A_FALSE :
(EN_ECC_RD_A_REG == "TRUE") ? EN_ECC_RD_A_TRUE :
EN_ECC_RD_A_FALSE;
EN_ECC_RD_B_BIN =
(EN_ECC_RD_B_REG == "FALSE") ? EN_ECC_RD_B_FALSE :
(EN_ECC_RD_B_REG == "TRUE") ? EN_ECC_RD_B_TRUE :
EN_ECC_RD_B_FALSE;
EN_ECC_WR_A_BIN =
(EN_ECC_WR_A_REG == "FALSE") ? EN_ECC_WR_A_FALSE :
(EN_ECC_WR_A_REG == "TRUE") ? EN_ECC_WR_A_TRUE :
EN_ECC_WR_A_FALSE;
EN_ECC_WR_B_BIN =
(EN_ECC_WR_B_REG == "FALSE") ? EN_ECC_WR_B_FALSE :
(EN_ECC_WR_B_REG == "TRUE") ? EN_ECC_WR_B_TRUE :
EN_ECC_WR_B_FALSE;
IREG_PRE_A_BIN =
(IREG_PRE_A_REG == "FALSE") ? IREG_PRE_A_FALSE :
(IREG_PRE_A_REG == "TRUE") ? IREG_PRE_A_TRUE :
IREG_PRE_A_FALSE;
IREG_PRE_B_BIN =
(IREG_PRE_B_REG == "FALSE") ? IREG_PRE_B_FALSE :
(IREG_PRE_B_REG == "TRUE") ? IREG_PRE_B_TRUE :
IREG_PRE_B_FALSE;
OREG_A_BIN =
(OREG_A_REG == "FALSE") ? OREG_A_FALSE :
(OREG_A_REG == "TRUE") ? OREG_A_TRUE :
OREG_A_FALSE;
OREG_B_BIN =
(OREG_B_REG == "FALSE") ? OREG_B_FALSE :
(OREG_B_REG == "TRUE") ? OREG_B_TRUE :
OREG_B_FALSE;
OREG_ECC_A_BIN =
(OREG_ECC_A_REG == "FALSE") ? OREG_ECC_A_FALSE :
(OREG_ECC_A_REG == "TRUE") ? OREG_ECC_A_TRUE :
OREG_ECC_A_FALSE;
OREG_ECC_B_BIN =
(OREG_ECC_B_REG == "FALSE") ? OREG_ECC_B_FALSE :
(OREG_ECC_B_REG == "TRUE") ? OREG_ECC_B_TRUE :
OREG_ECC_B_FALSE;
RST_MODE_A_BIN =
(RST_MODE_A_REG == "SYNC") ? RST_MODE_A_SYNC :
(RST_MODE_A_REG == "ASYNC") ? RST_MODE_A_ASYNC :
RST_MODE_A_SYNC;
RST_MODE_B_BIN =
(RST_MODE_B_REG == "SYNC") ? RST_MODE_B_SYNC :
(RST_MODE_B_REG == "ASYNC") ? RST_MODE_B_ASYNC :
RST_MODE_B_SYNC;
USE_EXT_CE_A_BIN =
(USE_EXT_CE_A_REG == "FALSE") ? USE_EXT_CE_A_FALSE :
(USE_EXT_CE_A_REG == "TRUE") ? USE_EXT_CE_A_TRUE :
USE_EXT_CE_A_FALSE;
USE_EXT_CE_B_BIN =
(USE_EXT_CE_B_REG == "FALSE") ? USE_EXT_CE_B_FALSE :
(USE_EXT_CE_B_REG == "TRUE") ? USE_EXT_CE_B_TRUE :
USE_EXT_CE_B_FALSE;
end
`endif
`ifndef XIL_XECLIB
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((AUTO_SLEEP_LATENCY_REG != 8) &&
(AUTO_SLEEP_LATENCY_REG != 3) &&
(AUTO_SLEEP_LATENCY_REG != 4) &&
(AUTO_SLEEP_LATENCY_REG != 5) &&
(AUTO_SLEEP_LATENCY_REG != 6) &&
(AUTO_SLEEP_LATENCY_REG != 7) &&
(AUTO_SLEEP_LATENCY_REG != 9) &&
(AUTO_SLEEP_LATENCY_REG != 10) &&
(AUTO_SLEEP_LATENCY_REG != 11) &&
(AUTO_SLEEP_LATENCY_REG != 12) &&
(AUTO_SLEEP_LATENCY_REG != 13) &&
(AUTO_SLEEP_LATENCY_REG != 14) &&
(AUTO_SLEEP_LATENCY_REG != 15))) begin
$display("Error: [Unisim %s-101] AUTO_SLEEP_LATENCY attribute is set to %d. Legal values for this attribute are 8, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14 or 15. Instance: %m", MODULE_NAME, AUTO_SLEEP_LATENCY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((AVG_CONS_INACTIVE_CYCLES_REG < 10) || (AVG_CONS_INACTIVE_CYCLES_REG > 100000))) begin
$display("Error: [Unisim %s-102] AVG_CONS_INACTIVE_CYCLES attribute is set to %d. Legal values for this attribute are 10 to 100000. Instance: %m", MODULE_NAME, AVG_CONS_INACTIVE_CYCLES_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((BWE_MODE_A_REG != "PARITY_INTERLEAVED") &&
(BWE_MODE_A_REG != "PARITY_INDEPENDENT"))) begin
$display("Error: [Unisim %s-103] BWE_MODE_A attribute is set to %s. Legal values for this attribute are PARITY_INTERLEAVED or PARITY_INDEPENDENT. Instance: %m", MODULE_NAME, BWE_MODE_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((BWE_MODE_B_REG != "PARITY_INTERLEAVED") &&
(BWE_MODE_B_REG != "PARITY_INDEPENDENT"))) begin
$display("Error: [Unisim %s-104] BWE_MODE_B attribute is set to %s. Legal values for this attribute are PARITY_INTERLEAVED or PARITY_INDEPENDENT. Instance: %m", MODULE_NAME, BWE_MODE_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EN_AUTO_SLEEP_MODE_REG != "FALSE") &&
(EN_AUTO_SLEEP_MODE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-105] EN_AUTO_SLEEP_MODE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_AUTO_SLEEP_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EN_ECC_RD_A_REG != "FALSE") &&
(EN_ECC_RD_A_REG != "TRUE"))) begin
$display("Error: [Unisim %s-106] EN_ECC_RD_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_RD_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EN_ECC_RD_B_REG != "FALSE") &&
(EN_ECC_RD_B_REG != "TRUE"))) begin
$display("Error: [Unisim %s-107] EN_ECC_RD_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_RD_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EN_ECC_WR_A_REG != "FALSE") &&
(EN_ECC_WR_A_REG != "TRUE"))) begin
$display("Error: [Unisim %s-108] EN_ECC_WR_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_WR_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EN_ECC_WR_B_REG != "FALSE") &&
(EN_ECC_WR_B_REG != "TRUE"))) begin
$display("Error: [Unisim %s-109] EN_ECC_WR_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, EN_ECC_WR_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IREG_PRE_A_REG != "FALSE") &&
(IREG_PRE_A_REG != "TRUE"))) begin
$display("Error: [Unisim %s-110] IREG_PRE_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, IREG_PRE_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IREG_PRE_B_REG != "FALSE") &&
(IREG_PRE_B_REG != "TRUE"))) begin
$display("Error: [Unisim %s-111] IREG_PRE_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, IREG_PRE_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((OREG_A_REG != "FALSE") &&
(OREG_A_REG != "TRUE"))) begin
$display("Error: [Unisim %s-123] OREG_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, OREG_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((OREG_B_REG != "FALSE") &&
(OREG_B_REG != "TRUE"))) begin
$display("Error: [Unisim %s-124] OREG_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, OREG_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((OREG_ECC_A_REG != "FALSE") &&
(OREG_ECC_A_REG != "TRUE"))) begin
$display("Error: [Unisim %s-125] OREG_ECC_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, OREG_ECC_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((OREG_ECC_B_REG != "FALSE") &&
(OREG_ECC_B_REG != "TRUE"))) begin
$display("Error: [Unisim %s-126] OREG_ECC_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, OREG_ECC_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RST_MODE_A_REG != "SYNC") &&
(RST_MODE_A_REG != "ASYNC"))) begin
$display("Error: [Unisim %s-127] RST_MODE_A attribute is set to %s. Legal values for this attribute are SYNC or ASYNC. Instance: %m", MODULE_NAME, RST_MODE_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RST_MODE_B_REG != "SYNC") &&
(RST_MODE_B_REG != "ASYNC"))) begin
$display("Error: [Unisim %s-128] RST_MODE_B attribute is set to %s. Legal values for this attribute are SYNC or ASYNC. Instance: %m", MODULE_NAME, RST_MODE_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USE_EXT_CE_A_REG != "FALSE") &&
(USE_EXT_CE_A_REG != "TRUE"))) begin
$display("Error: [Unisim %s-129] USE_EXT_CE_A attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, USE_EXT_CE_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USE_EXT_CE_B_REG != "FALSE") &&
(USE_EXT_CE_B_REG != "TRUE"))) begin
$display("Error: [Unisim %s-130] USE_EXT_CE_B attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, USE_EXT_CE_B_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
`ifdef XIL_TIMING
reg notifier;
`endif
// begin behavioral model
// define tasks, functions
function [7:0] fn_ecc (
input encode,
input [63:0] d_i,
input [7:0] dp_i
);
reg ecc_7;
begin
fn_ecc[0] = d_i[0] ^ d_i[1] ^ d_i[3] ^ d_i[4] ^ d_i[6] ^
d_i[8] ^ d_i[10] ^ d_i[11] ^ d_i[13] ^ d_i[15] ^
d_i[17] ^ d_i[19] ^ d_i[21] ^ d_i[23] ^ d_i[25] ^
d_i[26] ^ d_i[28] ^ d_i[30] ^ d_i[32] ^ d_i[34] ^
d_i[36] ^ d_i[38] ^ d_i[40] ^ d_i[42] ^ d_i[44] ^
d_i[46] ^ d_i[48] ^ d_i[50] ^ d_i[52] ^ d_i[54] ^
d_i[56] ^ d_i[57] ^ d_i[59] ^ d_i[61] ^ d_i[63];
fn_ecc[1] = d_i[0] ^ d_i[2] ^ d_i[3] ^ d_i[5] ^ d_i[6] ^
d_i[9] ^ d_i[10] ^ d_i[12] ^ d_i[13] ^ d_i[16] ^
d_i[17] ^ d_i[20] ^ d_i[21] ^ d_i[24] ^ d_i[25] ^
d_i[27] ^ d_i[28] ^ d_i[31] ^ d_i[32] ^ d_i[35] ^
d_i[36] ^ d_i[39] ^ d_i[40] ^ d_i[43] ^ d_i[44] ^
d_i[47] ^ d_i[48] ^ d_i[51] ^ d_i[52] ^ d_i[55] ^
d_i[56] ^ d_i[58] ^ d_i[59] ^ d_i[62] ^ d_i[63];
fn_ecc[2] = d_i[1] ^ d_i[2] ^ d_i[3] ^ d_i[7] ^ d_i[8] ^
d_i[9] ^ d_i[10] ^ d_i[14] ^ d_i[15] ^ d_i[16] ^
d_i[17] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^
d_i[29] ^ d_i[30] ^ d_i[31] ^ d_i[32] ^ d_i[37] ^
d_i[38] ^ d_i[39] ^ d_i[40] ^ d_i[45] ^ d_i[46] ^
d_i[47] ^ d_i[48] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56] ^ d_i[60] ^ d_i[61] ^ d_i[62] ^ d_i[63];
fn_ecc[3] = d_i[4] ^ d_i[5] ^ d_i[6] ^ d_i[7] ^ d_i[8] ^
d_i[9] ^ d_i[10] ^ d_i[18] ^ d_i[19] ^ d_i[20] ^
d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^
d_i[33] ^ d_i[34] ^ d_i[35] ^ d_i[36] ^ d_i[37] ^
d_i[38] ^ d_i[39] ^ d_i[40] ^ d_i[49] ^ d_i[50] ^
d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56];
fn_ecc[4] = d_i[11] ^ d_i[12] ^ d_i[13] ^ d_i[14] ^ d_i[15] ^
d_i[16] ^ d_i[17] ^ d_i[18] ^ d_i[19] ^ d_i[20] ^
d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^ d_i[25] ^
d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ d_i[45] ^
d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ d_i[50] ^
d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56];
fn_ecc[5] = d_i[26] ^ d_i[27] ^ d_i[28] ^ d_i[29] ^ d_i[30] ^
d_i[31] ^ d_i[32] ^ d_i[33] ^ d_i[34] ^ d_i[35] ^
d_i[36] ^ d_i[37] ^ d_i[38] ^ d_i[39] ^ d_i[40] ^
d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^ d_i[45] ^
d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^ d_i[50] ^
d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^ d_i[55] ^
d_i[56];
fn_ecc[6] = d_i[57] ^ d_i[58] ^ d_i[59] ^ d_i[60] ^ d_i[61] ^
d_i[62] ^ d_i[63];
ecc_7 = d_i[0] ^ d_i[1] ^ d_i[2] ^ d_i[3] ^ d_i[4] ^
d_i[5] ^ d_i[6] ^ d_i[7] ^ d_i[8] ^ d_i[9] ^
d_i[10] ^ d_i[11] ^ d_i[12] ^ d_i[13] ^ d_i[14] ^
d_i[15] ^ d_i[16] ^ d_i[17] ^ d_i[18] ^ d_i[19] ^
d_i[20] ^ d_i[21] ^ d_i[22] ^ d_i[23] ^ d_i[24] ^
d_i[25] ^ d_i[26] ^ d_i[27] ^ d_i[28] ^ d_i[29] ^
d_i[30] ^ d_i[31] ^ d_i[32] ^ d_i[33] ^ d_i[34] ^
d_i[35] ^ d_i[36] ^ d_i[37] ^ d_i[38] ^ d_i[39] ^
d_i[40] ^ d_i[41] ^ d_i[42] ^ d_i[43] ^ d_i[44] ^
d_i[45] ^ d_i[46] ^ d_i[47] ^ d_i[48] ^ d_i[49] ^
d_i[50] ^ d_i[51] ^ d_i[52] ^ d_i[53] ^ d_i[54] ^
d_i[55] ^ d_i[56] ^ d_i[57] ^ d_i[58] ^ d_i[59] ^
d_i[60] ^ d_i[61] ^ d_i[62] ^ d_i[63];
if (encode) begin
fn_ecc[7] = ecc_7 ^
fn_ecc[0] ^ fn_ecc[1] ^ fn_ecc[2] ^ fn_ecc[3] ^
fn_ecc[4] ^ fn_ecc[5] ^ fn_ecc[6];
end
else begin
fn_ecc[7] = ecc_7 ^
dp_i[0] ^ dp_i[1] ^ dp_i[2] ^ dp_i[3] ^
dp_i[4] ^ dp_i[5] ^ dp_i[6];
end
end
endfunction // fn_ecc
function [71:0] fn_cor_bit (
input [6:0] error_bit,
input [63:0] d_i,
input [7:0] dp_i
);
reg [71:0] cor_int;
begin
cor_int = {d_i[63:57], dp_i[6], d_i[56:26], dp_i[5], d_i[25:11], dp_i[4],
d_i[10:4], dp_i[3], d_i[3:1], dp_i[2], d_i[0], dp_i[1:0],
dp_i[7]};
cor_int[error_bit] = ~cor_int[error_bit];
fn_cor_bit = {cor_int[0], cor_int[64], cor_int[32], cor_int[16],
cor_int[8], cor_int[4], cor_int[2:1], cor_int[71:65],
cor_int[63:33], cor_int[31:17], cor_int[15:9],
cor_int[7:5], cor_int[3]};
end
endfunction // fn_cor_bit
`ifndef XIL_XECLIB
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((EN_AUTO_SLEEP_MODE_REG == "TRUE") &&
(USE_EXT_CE_A_REG == "TRUE"))) begin
$display("Error: [Unisim %s-19] EN_AUTO_SLEEP_MODE attribute is set to %s and USE_EXT_CE_A is set to %s. External OREG CE cannot be used when AUTO_SLEEP_MODE is enabled. Instance: %m", MODULE_NAME, EN_AUTO_SLEEP_MODE_REG, USE_EXT_CE_A_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EN_AUTO_SLEEP_MODE_REG == "TRUE") &&
(USE_EXT_CE_B_REG == "TRUE"))) begin
$display("Error: [Unisim %s-20] EN_AUTO_SLEEP_MODE attribute is set to %s and USE_EXT_CE_B is set to %s. External OREG CE cannot be used when AUTO_SLEEP_MODE is enabled. Instance: %m", MODULE_NAME, EN_AUTO_SLEEP_MODE_REG, USE_EXT_CE_B_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
localparam mem_width = 72;
localparam mem_depth = 4 * 1024;
localparam encode = 1'b1;
localparam decode = 1'b0;
localparam [22:0] ADDR_INIT = 23'b0;
localparam [8:0] BWE_INIT = 9'b0;
localparam [mem_width-1:0] D_INIT = {mem_width{1'b0}};
localparam [mem_width-1:0] D_UNDEF = {mem_width{1'bx}};
reg [mem_width-1 : 0 ] mem [0 : mem_depth-1];
integer wa;
reg [11:0] ram_addr_a;
reg [11:0] ram_addr_b;
reg ram_ce_a;
reg ram_ce_b;
reg DEEPSLEEP_in = 1'b0;
reg SHUTDOWN_in = 1'b0;
reg ram_ce_a_int=0;
reg ram_ce_b_int=0;
reg ram_ce_a_pre=0;
reg ram_ce_b_pre=0;
reg [15:1] ram_ce_a_fifo;
reg [15:1] ram_ce_b_fifo;
reg [71:0] ram_bwe_a;
reg [71:0] ram_bwe_b;
reg ram_we_a;
reg ram_we_b;
reg ram_we_a_event = 1'b0;
reg ram_we_b_event = 1'b0;
reg [71:0] ram_data_a;
reg [71:0] ram_data_b;
// input register stages
// decisions simulate faster than assignments - wider muxes, less busses
reg [22:0] ADDR_A_reg;
reg [22:0] ADDR_B_reg;
reg [8:0] BWE_A_reg;
reg [8:0] BWE_B_reg;
reg [71:0] DIN_A_reg;
reg [71:0] DIN_B_reg;
reg EN_A_reg;
reg EN_B_reg;
reg INJECT_DBITERR_A_reg;
reg INJECT_DBITERR_B_reg;
reg INJECT_SBITERR_A_reg;
reg INJECT_SBITERR_B_reg;
reg RDB_WR_A_reg;
reg RDB_WR_B_reg;
reg [22:0] ADDR_A_int;
reg [22:0] ADDR_B_int;
reg [8:0] BWE_A_int;
reg [8:0] BWE_B_int;
reg [71:0] DIN_A_int;
reg [71:0] DIN_B_int;
reg EN_A_int;
reg EN_B_int;
reg INJECT_DBITERR_A_int;
reg INJECT_DBITERR_B_int;
reg INJECT_SBITERR_A_int;
reg INJECT_SBITERR_B_int;
reg RDB_WR_A_int;
reg RDB_WR_B_int;
reg RST_A_async = 1'b0;
reg RST_B_async = 1'b0;
reg RST_A_sync = 1'b0;
reg RST_B_sync = 1'b0;
integer wake_count;
wire auto_sleep;
reg shut_down;
reg a_sleep;
reg auto_sleep_A;
reg auto_sleep_B;
wire auto_wake_up_A;
wire auto_wake_up_B;
reg DBITERR_A_out;
reg DBITERR_B_out;
reg SBITERR_A_out;
reg SBITERR_B_out;
reg [71:0] DOUT_A_out;
reg [71:0] DOUT_B_out;
assign DBITERR_A = DBITERR_A_out;
assign DBITERR_B = DBITERR_B_out;
assign DOUT_A = DOUT_A_out;
assign DOUT_B = DOUT_B_out;
assign SBITERR_A = SBITERR_A_out;
assign SBITERR_B = SBITERR_B_out;
`ifndef XIL_XECLIB
reg INIT_RAM = 1'b0;
initial begin
#100; INIT_RAM = 1'b1;
end
`endif
always @ (*) begin
if (RST_MODE_A_BIN == RST_MODE_A_ASYNC) begin
RST_A_async = RST_A_in;
end
end
always @ (*) begin
if (RST_MODE_B_BIN == RST_MODE_B_ASYNC) begin
RST_B_async = RST_B_in;
end
end
always @ (posedge CLK_in) begin
if ((RST_MODE_A_BIN == RST_MODE_A_SYNC) && (RST_A_sync !== RST_A_in))
RST_A_sync <= RST_A_in;
if ((RST_MODE_B_BIN == RST_MODE_B_SYNC) && (RST_B_sync !== RST_B_in))
RST_B_sync <= RST_B_in;
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR ||
(IREG_PRE_A_BIN == IREG_PRE_A_FALSE)) begin
ADDR_A_reg <= ADDR_INIT;
EN_A_reg <= 1'b0;
RDB_WR_A_reg <= 1'b0;
BWE_A_reg <= BWE_INIT;
DIN_A_reg <= D_INIT;
INJECT_DBITERR_A_reg <= 1'b0;
INJECT_SBITERR_A_reg <= 1'b0;
end else begin
EN_A_reg <= EN_A_in;
if (EN_A_in) begin
ADDR_A_reg[22:12] <= ADDR_A_in[22:12];
end
if (EN_A_in || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_TRUE)) begin
ADDR_A_reg[11:0] <= ADDR_A_in[11:0];
BWE_A_reg <= BWE_A_in;
DIN_A_reg <= DIN_A_in;
INJECT_DBITERR_A_reg <= INJECT_DBITERR_A_in;
INJECT_SBITERR_A_reg <= INJECT_SBITERR_A_in;
RDB_WR_A_reg <= RDB_WR_A_in;
end
end
end
always @ (*) begin
if (IREG_PRE_A_BIN == IREG_PRE_A_TRUE) begin
ADDR_A_int = ADDR_A_reg;
end else begin
ADDR_A_int = ADDR_A_in;
end
end
always @ (*) begin
if (IREG_PRE_A_BIN == IREG_PRE_A_TRUE) begin
BWE_A_int = BWE_A_reg;
end else begin
BWE_A_int = BWE_A_in;
end
end
always @ (*) begin
if (IREG_PRE_A_BIN == IREG_PRE_A_TRUE) begin
DIN_A_int = DIN_A_reg;
end else begin
DIN_A_int = DIN_A_in;
end
end
always @ (*) begin
if (IREG_PRE_A_BIN == IREG_PRE_A_TRUE) begin
EN_A_int = EN_A_reg;
end else begin
EN_A_int = EN_A_in;
end
end
always @ (*) begin
if (IREG_PRE_A_BIN == IREG_PRE_A_TRUE) begin
INJECT_DBITERR_A_int = INJECT_DBITERR_A_reg;
end else begin
INJECT_DBITERR_A_int = INJECT_DBITERR_A_in;
end
end
always @ (*) begin
if (IREG_PRE_A_BIN == IREG_PRE_A_TRUE) begin
INJECT_SBITERR_A_int = INJECT_SBITERR_A_reg;
end else begin
INJECT_SBITERR_A_int = INJECT_SBITERR_A_in;
end
end
always @ (*) begin
if (IREG_PRE_A_BIN == IREG_PRE_A_TRUE) begin
RDB_WR_A_int = RDB_WR_A_reg;
end else begin
RDB_WR_A_int = RDB_WR_A_in;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR ||
(IREG_PRE_B_BIN == IREG_PRE_B_FALSE)) begin
ADDR_B_reg <= ADDR_INIT;
EN_B_reg <= 1'b0;
RDB_WR_B_reg <= 1'b0;
BWE_B_reg <= BWE_INIT;
DIN_B_reg <= D_INIT;
INJECT_DBITERR_B_reg <= 1'b0;
INJECT_SBITERR_B_reg <= 1'b0;
end else begin
EN_B_reg <= EN_B_in;
if (EN_B_in) begin
ADDR_B_reg[22:12] <= ADDR_B_in[22:12];
end
if (EN_B_in || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_TRUE)) begin
ADDR_B_reg[11:0] <= ADDR_B_in[11:0];
BWE_B_reg <= BWE_B_in;
DIN_B_reg <= DIN_B_in;
INJECT_DBITERR_B_reg <= INJECT_DBITERR_B_in;
INJECT_SBITERR_B_reg <= INJECT_SBITERR_B_in;
RDB_WR_B_reg <= RDB_WR_B_in;
end
end
end
always @ (*) begin
if (IREG_PRE_B_BIN == IREG_PRE_B_TRUE) begin
ADDR_B_int = ADDR_B_reg;
end else begin
ADDR_B_int = ADDR_B_in;
end
end
always @ (*) begin
if (IREG_PRE_B_BIN == IREG_PRE_B_TRUE) begin
BWE_B_int = BWE_B_reg;
end else begin
BWE_B_int = BWE_B_in;
end
end
always @ (*) begin
if (IREG_PRE_B_BIN == IREG_PRE_B_TRUE) begin
DIN_B_int = DIN_B_reg;
end else begin
DIN_B_int = DIN_B_in;
end
end
always @ (*) begin
if (IREG_PRE_B_BIN == IREG_PRE_B_TRUE) begin
EN_B_int = EN_B_reg;
end else begin
EN_B_int = EN_B_in;
end
end
always @ (*) begin
if (IREG_PRE_B_BIN == IREG_PRE_B_TRUE) begin
INJECT_DBITERR_B_int = INJECT_DBITERR_B_reg;
end else begin
INJECT_DBITERR_B_int = INJECT_DBITERR_B_in;
end
end
always @ (*) begin
if (IREG_PRE_B_BIN == IREG_PRE_B_TRUE) begin
INJECT_SBITERR_B_int = INJECT_SBITERR_B_reg;
end else begin
INJECT_SBITERR_B_int = INJECT_SBITERR_B_in;
end
end
always @ (*) begin
if (IREG_PRE_B_BIN == IREG_PRE_B_TRUE) begin
RDB_WR_B_int = RDB_WR_B_reg;
end else begin
RDB_WR_B_int = RDB_WR_B_in;
end
end
reg [71:0] ram_data_a_lat;
reg [71:0] ram_data_a_out;
// reg [71:0] ram_data_a_hold=D_INIT;
reg [71:0] ram_data_a_reg;
reg [71:0] ram_data_a_ecc=72'h000000000000000000;
reg [71:0] ram_data_b_lat;
reg [71:0] ram_data_b_out;
reg [71:0] ram_data_b_reg;
reg [71:0] ram_data_b_ecc=72'h000000000000000000;
reg RDACCESS_A_lat;
// reg RDACCESS_A_hold;
reg RDACCESS_B_lat;
reg RDACCESS_A_int;
reg RDACCESS_B_int;
reg SBITERR_A_ecc=1'b0;
reg DBITERR_A_ecc=1'b0;
reg SBITERR_B_ecc=1'b0;
reg DBITERR_B_ecc=1'b0;
reg DBITERR_A_reg;
reg DBITERR_B_reg;
reg [71:0] DOUT_A_reg;
reg [71:0] DOUT_B_reg;
reg RDACCESS_A_reg;
reg RDACCESS_B_reg;
reg SBITERR_A_reg;
reg SBITERR_B_reg;
reg RDACCESS_A_ecc_reg;
reg RDACCESS_B_ecc_reg;
reg data_A_enable = 1'b0;
reg data_B_enable = 1'b0;
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_A_async) begin
if (RST_A_async || RST_A_in || glblGSR ||
`else
always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin
if (RST_A_in || glblGSR ||
`endif
shut_down || SHUTDOWN_in) begin
RDACCESS_A_int = 1'b0;
end else begin
if (OREG_ECC_A_BIN == OREG_ECC_A_TRUE) begin
if ((USE_EXT_CE_A_BIN == USE_EXT_CE_A_FALSE) || OREG_ECC_CE_A_in) begin
RDACCESS_A_int = RDACCESS_A_ecc_reg;
end else begin
RDACCESS_A_int = 1'b0;
end
end else if (OREG_A_BIN == OREG_A_TRUE) begin
if ((USE_EXT_CE_A_BIN == USE_EXT_CE_A_FALSE) || OREG_CE_A_in) begin
RDACCESS_A_int = RDACCESS_A_reg;
end else begin
RDACCESS_A_int = 1'b0;
end
end else begin
RDACCESS_A_int = RDACCESS_A_lat;
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_B_async) begin
if (RST_B_async || RST_B_in || glblGSR ||
`else
always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin
if (RST_B_in || glblGSR ||
`endif
shut_down || SHUTDOWN_in) begin
RDACCESS_B_int = 1'b0;
end else begin
if (OREG_ECC_B_BIN == OREG_ECC_B_TRUE) begin
if ((USE_EXT_CE_B_BIN == USE_EXT_CE_B_FALSE) || OREG_ECC_CE_B_in) begin
RDACCESS_B_int = RDACCESS_B_ecc_reg;
end else begin
RDACCESS_B_int = 1'b0;
end
end else if (OREG_B_BIN == OREG_B_TRUE) begin
if ((USE_EXT_CE_B_BIN == USE_EXT_CE_B_FALSE) || OREG_CE_B_in) begin
RDACCESS_B_int = RDACCESS_B_reg;
end else begin
RDACCESS_B_int = 1'b0;
end
end else begin
RDACCESS_B_int = RDACCESS_B_lat;
end
end
end
always @ (*) begin
if (RST_A_async || RST_A_sync || shut_down || glblGSR) begin
DBITERR_A_out = 1'b0;
SBITERR_A_out = 1'b0;
end else if (OREG_ECC_A_BIN == OREG_ECC_A_TRUE) begin
DBITERR_A_out = DBITERR_A_reg;
SBITERR_A_out = SBITERR_A_reg;
end else if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin
DBITERR_A_out = DBITERR_A_ecc;
SBITERR_A_out = SBITERR_A_ecc;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_A_async) begin
if (RST_A_async || RST_A_in || auto_sleep || a_sleep || shut_down || SHUTDOWN_in || glblGSR) begin
`else
always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin
if (RST_A_in || auto_sleep || a_sleep || shut_down || SHUTDOWN_in || glblGSR) begin
`endif
data_A_enable <= 1'b0;
end else if ((OREG_A_BIN == OREG_A_TRUE) && ram_ce_a && ~ram_we_a) begin
data_A_enable <= 1'b1;
end else if ((OREG_A_BIN == OREG_A_FALSE) && ram_ce_a_int && ~RDB_WR_A_int) begin
data_A_enable <= 1'b1;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_B_async) begin
if (RST_B_async || RST_B_in || auto_sleep || a_sleep || shut_down || SHUTDOWN_in || glblGSR) begin
`else
always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin
if (RST_B_in || auto_sleep || a_sleep || shut_down || SHUTDOWN_in || glblGSR) begin
`endif
data_B_enable <= 1'b0;
end else if ((OREG_B_BIN == OREG_B_TRUE) && ram_ce_b && ~ram_we_b) begin
data_B_enable <= 1'b1;
end else if ((OREG_B_BIN == OREG_B_FALSE) && ram_ce_b_int && ~RDB_WR_B_int) begin
data_B_enable <= 1'b1;
end
end
always @ (posedge CLK_in) begin
if (ram_ce_a && ~ram_we_a && SLEEP_in && ~a_sleep && (OREG_A_BIN == OREG_A_TRUE)) begin
$display("Warning: [Unisim %s-3] At time (%.3f) ns: Port A READ access at ADDR (%h) just prior to SLEEP with SLEEP asserted and OREG_A attribute set to (%s) will result in READ data getting lost. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_a, OREG_A_REG);
end else if (ram_ce_a && ram_we_a && SLEEP_in && ~a_sleep) begin
$display("Warning: [Unisim %s-4] At time (%.3f) ns: Port A WRITE access at ADDR (%h) just prior to SLEEP with SLEEP asserted will result in WRITE data getting ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_a);
end else if (ram_ce_a_pre && a_sleep && SLEEP_in) begin
$display("Warning: [Unisim %s-5] At time (%.3f) ns: Port A access at ADDR (%h) during SLEEP will be ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_a);
end else if (ram_ce_a_pre && a_sleep && ~SLEEP_in) begin
$display("Warning: [Unisim %s-6] At time (%.3f) ns: Port A access at ADDR (%h) during WAKEUP time will be ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_a);
end
end
always @ (posedge CLK_in) begin
if (ram_ce_b && ~ram_we_b && SLEEP_in && ~a_sleep && (OREG_B_BIN == OREG_B_TRUE)) begin
$display("Warning: [Unisim %s-7] At time (%.3f) ns: Port B READ access at ADDR (%h) just prior to SLEEP with SLEEP asserted and OREG_B attribute set to (%s) will result in READ data getting lost. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_b, OREG_B_REG);
end else if (ram_ce_b && ram_we_b && SLEEP_in && ~a_sleep) begin
$display("Warning: [Unisim %s-8] At time (%.3f) ns: Port B WRITE access at ADDR (%h) just prior to SLEEP with SLEEP asserted will result in WRITE data getting ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_b);
end else if (ram_ce_b_pre && a_sleep && SLEEP_in) begin
$display("Warning: [Unisim %s-9] At time (%.3f) ns: Port B access at ADDR (%h) during SLEEP will be ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_b);
end else if (ram_ce_b_pre && a_sleep && ~SLEEP_in) begin
$display("Warning: [Unisim %s-10] At time (%.3f) ns: Port B access at ADDR (%h) during WAKEUP time will be ignored. Instance: %m", MODULE_NAME, $time/1000.0, ram_addr_b);
end
end
always @ (*) begin
if (RST_A_async || RST_A_sync || glblGSR) begin
DOUT_A_out = D_INIT;
end else if (OREG_ECC_A_BIN == OREG_ECC_A_TRUE) begin
DOUT_A_out = DOUT_A_reg;
end else if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin
DOUT_A_out = ram_data_a_ecc;
end else if (data_A_enable) begin
if (OREG_A_BIN == OREG_A_TRUE) begin
DOUT_A_out = ram_data_a_reg;
end else begin
DOUT_A_out = ram_data_a_lat;
end
end else begin
DOUT_A_out = D_INIT;
end
end
always @ (*) begin
if (RST_B_async || RST_B_sync || shut_down || glblGSR) begin
DBITERR_B_out = 1'b0;
SBITERR_B_out = 1'b0;
end else if (OREG_ECC_B_BIN == OREG_ECC_B_TRUE) begin
DBITERR_B_out = DBITERR_B_reg;
SBITERR_B_out = SBITERR_B_reg;
end else if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin
DBITERR_B_out = DBITERR_B_ecc;
SBITERR_B_out = SBITERR_B_ecc;
end
end
always @ (*) begin
if (RST_B_async || RST_B_sync || glblGSR) begin
DOUT_B_out = D_INIT;
end else if (OREG_ECC_B_BIN == OREG_ECC_B_TRUE) begin
DOUT_B_out = DOUT_B_reg;
end else if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin
DOUT_B_out = ram_data_b_ecc;
end else if (data_B_enable) begin
if (OREG_B_BIN == OREG_B_TRUE) begin
DOUT_B_out = ram_data_b_reg;
end else begin
DOUT_B_out = ram_data_b_lat;
end
end else begin
DOUT_B_out = D_INIT;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_A_async) begin
if (RST_A_async || RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin
`else
always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin
if (RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin
`endif
DBITERR_A_reg <= 1'b0;
SBITERR_A_reg <= 1'b0;
end else if ((~a_sleep && ~shut_down && data_A_enable) &&
(((OREG_A_BIN == OREG_A_TRUE) && (RDACCESS_A_reg || RDACCESS_A_ecc_reg)) ||
((OREG_A_BIN == OREG_A_FALSE) && (RDACCESS_A_lat || RDACCESS_A_ecc_reg)))) begin
if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin
if ((USE_EXT_CE_A_BIN == USE_EXT_CE_A_FALSE) || OREG_ECC_CE_A_in) begin
DBITERR_A_reg <= DBITERR_A_ecc;
SBITERR_A_reg <= SBITERR_A_ecc;
end
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_A_async) begin
if (RST_A_async || RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin
`else
always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin
if (RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin
`endif
DOUT_A_reg <= D_INIT;
end else if (~shut_down && data_A_enable) begin
if (((OREG_A_BIN == OREG_A_TRUE) && (RDACCESS_A_reg || RDACCESS_A_ecc_reg)) ||
((OREG_A_BIN == OREG_A_FALSE) && (RDACCESS_A_lat || RDACCESS_A_ecc_reg))) begin
if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin
DOUT_A_reg <= ram_data_a_ecc;
end else if (OREG_A_BIN == OREG_A_TRUE) begin
DOUT_A_reg <= ram_data_a_reg;
end else begin
DOUT_A_reg <= ram_data_a_lat;
end
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_A_async) begin
if (RST_A_async || RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin
`else
always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin
if (RST_A_in || glblGSR || (OREG_ECC_A_BIN == OREG_ECC_A_FALSE)) begin
`endif
RDACCESS_A_ecc_reg <= 1'b0;
end else begin
if (OREG_A_BIN == OREG_A_TRUE) begin
if ((USE_EXT_CE_A_BIN == USE_EXT_CE_A_FALSE) || OREG_CE_A_in) begin
RDACCESS_A_ecc_reg <= RDACCESS_A_reg;
end
end else begin
RDACCESS_A_ecc_reg <= RDACCESS_A_lat;
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_B_async) begin
if (RST_B_async || RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin
`else
always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin
if (RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin
`endif
DBITERR_B_reg <= 1'b0;
SBITERR_B_reg <= 1'b0;
end else if ((~a_sleep && ~shut_down && data_B_enable) &&
(((OREG_B_BIN == OREG_B_TRUE) && (RDACCESS_B_reg || RDACCESS_B_ecc_reg)) ||
((OREG_B_BIN == OREG_B_FALSE) && (RDACCESS_B_lat || RDACCESS_B_ecc_reg)))) begin
if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin
if ((USE_EXT_CE_B_BIN == USE_EXT_CE_B_FALSE) || OREG_ECC_CE_B_in) begin
DBITERR_B_reg <= DBITERR_B_ecc;
SBITERR_B_reg <= SBITERR_B_ecc;
end
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_B_async) begin
if (RST_B_async || RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin
`else
always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin
if (RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin
`endif
DOUT_B_reg <= D_INIT;
end else if (~shut_down && data_B_enable) begin
if (((OREG_B_BIN == OREG_B_TRUE) && (RDACCESS_B_reg || RDACCESS_B_ecc_reg)) ||
((OREG_B_BIN == OREG_B_FALSE) && (RDACCESS_B_lat || RDACCESS_B_ecc_reg))) begin
if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin
DOUT_B_reg <= ram_data_b_ecc;
end else if (OREG_B_BIN == OREG_B_TRUE) begin
DOUT_B_reg <= ram_data_b_reg;
end else begin
DOUT_B_reg <= ram_data_b_lat;
end
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_B_async) begin
if (RST_B_async || RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin
`else
always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin
if (RST_B_in || glblGSR || (OREG_ECC_B_BIN == OREG_ECC_B_FALSE)) begin
`endif
RDACCESS_B_ecc_reg <= 1'b0;
end else begin
if (OREG_B_BIN == OREG_B_TRUE) begin
if ((USE_EXT_CE_B_BIN == USE_EXT_CE_B_FALSE) || OREG_CE_B_in) begin
RDACCESS_B_ecc_reg <= RDACCESS_B_reg;
end
end else begin
RDACCESS_B_ecc_reg <= RDACCESS_B_lat;
end
end
end
// ram oreg
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_A_async) begin
if (RST_A_async || RST_A_in || shut_down || a_sleep || glblGSR) begin
`else
always @ (posedge CLK_in or posedge RST_A_async or shut_down or glblGSR) begin
if (RST_A_in || shut_down || a_sleep || glblGSR) begin
`endif
RDACCESS_A_reg <= 1'b0;
end else begin
RDACCESS_A_reg <= RDACCESS_A_lat;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_A_async) begin
if (RST_A_async || RST_A_in || shut_down || SLEEP_in || a_sleep || glblGSR || (OREG_A_BIN == OREG_A_FALSE)) begin
`else
always @ (posedge CLK_in or posedge RST_A_async or shut_down or glblGSR) begin
if (RST_A_in || shut_down || SLEEP_in || a_sleep || glblGSR || (OREG_A_BIN == OREG_A_FALSE)) begin
`endif
ram_data_a_reg <= D_INIT;
end else if (USE_EXT_CE_A_BIN == USE_EXT_CE_A_TRUE) begin
if (OREG_CE_A_in) begin
ram_data_a_reg = ram_data_a_lat;
end
end else if (ram_ce_a_int || RDACCESS_A_reg) begin
ram_data_a_reg = ram_data_a_lat;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_B_async) begin
if (RST_B_async || RST_B_in || shut_down || a_sleep || glblGSR) begin
`else
always @ (posedge CLK_in or posedge RST_B_async or shut_down or glblGSR) begin
if (RST_B_in || shut_down || a_sleep || glblGSR) begin
`endif
RDACCESS_B_reg <= 1'b0;
end else begin
RDACCESS_B_reg <= RDACCESS_B_lat;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_B_async) begin
if (RST_B_async || RST_B_in || shut_down || SLEEP_in || a_sleep || glblGSR || (OREG_B_BIN == OREG_B_FALSE)) begin
`else
always @ (posedge CLK_in or posedge RST_B_async or shut_down or glblGSR) begin
if (RST_B_in || shut_down || SLEEP_in || a_sleep || glblGSR || (OREG_B_BIN == OREG_B_FALSE)) begin
`endif
ram_data_b_reg <= D_INIT;
end else if (USE_EXT_CE_B_BIN == USE_EXT_CE_B_TRUE) begin
if (OREG_CE_B_in) begin
ram_data_b_reg = ram_data_b_lat;
end
end else if (ram_ce_b_int || RDACCESS_B_reg) begin
ram_data_b_reg = ram_data_b_lat;
end
end
reg [15:1] ram_ce_a_fifo_in = 15'b0;
always @ (*) begin
ram_ce_a_fifo_in = 15'b0;
ram_ce_a_fifo_in[AUTO_SLEEP_LATENCY_BIN] = EN_A_int;
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE)) begin
ram_ce_a_fifo <= 15'b0;
end else begin
ram_ce_a_fifo <= {1'b0, ram_ce_a_fifo[15:2]} | ram_ce_a_fifo_in;
end
end
always @ (*) begin
if (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE) begin
ram_ce_a_pre = EN_A_int;
end else begin
ram_ce_a_pre = ram_ce_a_fifo[1];
end
end
always @ (*) begin
if (a_sleep || SLEEP_in || auto_sleep) begin
ram_ce_a_int = 1'b0;
end else begin
ram_ce_a_int = ram_ce_a_pre;
end
end
reg [15:1] ram_ce_b_fifo_in = 15'b0;
always @ (*) begin
ram_ce_b_fifo_in = 15'b0;
ram_ce_b_fifo_in[AUTO_SLEEP_LATENCY_BIN] = EN_B_int;
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE)) begin
ram_ce_b_fifo <= 15'b0;
end else begin
ram_ce_b_fifo <= {1'b0, ram_ce_b_fifo[15:2]} | ram_ce_b_fifo_in;
end
end
always @ (*) begin
if (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE) begin
ram_ce_b_pre = EN_B_int;
end else begin
ram_ce_b_pre = ram_ce_b_fifo[1];
end
end
always @ (*) begin
if (a_sleep || SLEEP_in || auto_sleep) begin
ram_ce_b_int = 1'b0;
end else begin
ram_ce_b_int = ram_ce_b_pre;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || ~RDB_WR_A_int || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin
ram_bwe_a <= 72'h00;
end else if (ram_ce_a_int) begin
if (EN_ECC_WR_A_BIN == EN_ECC_WR_A_TRUE) begin
ram_bwe_a <= 72'hFFFFFFFFFFFFFFFFFF;
end else if (BWE_MODE_A_BIN == BWE_MODE_A_PARITY_INTERLEAVED) begin
ram_bwe_a <= {BWE_A_int[7:0],
{8{BWE_A_int[7]}}, {8{BWE_A_int[6]}}, {8{BWE_A_int[5]}}, {8{BWE_A_int[4]}},
{8{BWE_A_int[3]}}, {8{BWE_A_int[2]}}, {8{BWE_A_int[1]}}, {8{BWE_A_int[0]}}};
end else begin
ram_bwe_a <= {{8{BWE_A_int[8]}},
{8{BWE_A_int[7]}}, {8{BWE_A_int[6]}}, {8{BWE_A_int[5]}}, {8{BWE_A_int[4]}},
{8{BWE_A_int[3]}}, {8{BWE_A_int[2]}}, {8{BWE_A_int[1]}}, {8{BWE_A_int[0]}}};
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || ~RDB_WR_B_int || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin
ram_bwe_b <= 72'b0;
end else if (ram_ce_b_int) begin
if (EN_ECC_WR_B_BIN == EN_ECC_WR_B_TRUE) begin
ram_bwe_b <= 72'hFFFFFFFFFFFFFFFFFF;
end else if (BWE_MODE_B_BIN == BWE_MODE_B_PARITY_INTERLEAVED) begin
ram_bwe_b <= {BWE_B_int[7:0],
{8{BWE_B_int[7]}}, {8{BWE_B_int[6]}}, {8{BWE_B_int[5]}}, {8{BWE_B_int[4]}},
{8{BWE_B_int[3]}}, {8{BWE_B_int[2]}}, {8{BWE_B_int[1]}}, {8{BWE_B_int[0]}}};
end else begin
ram_bwe_b <= {{8{BWE_B_int[8]}},
{8{BWE_B_int[7]}}, {8{BWE_B_int[6]}}, {8{BWE_B_int[5]}}, {8{BWE_B_int[4]}},
{8{BWE_B_int[3]}}, {8{BWE_B_int[2]}}, {8{BWE_B_int[1]}}, {8{BWE_B_int[0]}}};
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin
ram_addr_a <= 12'b0;
end else if (ram_ce_a_int) begin
ram_addr_a <= ADDR_A_int[11:0];
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin
ram_addr_b <= 12'b0;
end else if (ram_ce_b_int) begin
ram_addr_b <= ADDR_B_int[11:0];
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_A_async) begin
if (glblGSR || (RST_A_async || RST_A_in) || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin
`else
always @ (posedge CLK_in or posedge RST_A_async or glblGSR) begin
if (glblGSR || RST_A_in || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin
`endif
ram_ce_a <= 1'b0;
end else begin
ram_ce_a <= ram_ce_a_int;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in or posedge RST_B_async) begin
if (glblGSR || (RST_B_async || RST_B_in) || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin
`else
always @ (posedge CLK_in or posedge RST_B_async or glblGSR) begin
if (glblGSR || RST_B_in || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin
`endif
ram_ce_b <= 1'b0;
end else begin
ram_ce_b <= ram_ce_b_int;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in || ~ram_ce_a_int) begin
ram_we_a <= 1'b0;
end else begin
ram_we_a <= RDB_WR_A_int;
if (RDB_WR_A_int) ram_we_a_event <= ~ram_we_a_event;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in || ~ram_ce_b_int) begin
ram_we_b <= 1'b0;
end else begin
ram_we_b <= RDB_WR_B_int;
if (RDB_WR_B_int) ram_we_b_event <= ~ram_we_b_event;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin
ram_data_a <= D_INIT;
end else if (RDB_WR_A_int && ram_ce_a_int) begin
if (EN_ECC_WR_A_BIN == EN_ECC_WR_A_TRUE) begin
ram_data_a[63:0] <= {DIN_A_int[63],
DIN_A_int[62] ^ (INJECT_DBITERR_A_int),
DIN_A_int[61:31],
DIN_A_int[30] ^ (INJECT_DBITERR_A_int || INJECT_SBITERR_A_int),
DIN_A_int[29:0]};
ram_data_a[71:64] <= fn_ecc(encode, DIN_A_int[63:0], DIN_A_int[71:64]);
end else if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin
ram_data_a[63:0] <= {DIN_A_int[63],
DIN_A_int[62] ^ (INJECT_DBITERR_A_int),
DIN_A_int[61:31],
DIN_A_int[30] ^ (INJECT_DBITERR_A_int || INJECT_SBITERR_A_int),
DIN_A_int[29:0]};
ram_data_a[71:64] <= DIN_A_int[71:64];
end else begin
ram_data_a <= DIN_A_int;
end
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || a_sleep || DEEPSLEEP_in || SLEEP_in || auto_sleep || shut_down || SHUTDOWN_in) begin
ram_data_b <= D_INIT;
end else if (RDB_WR_B_int && ram_ce_b_int) begin
if (EN_ECC_WR_B_BIN == EN_ECC_WR_B_TRUE) begin
ram_data_b[63:0] <= {DIN_B_int[63],
DIN_B_int[62] ^ (INJECT_DBITERR_B_int),
DIN_B_int[61:31],
DIN_B_int[30] ^ (INJECT_DBITERR_B_int || INJECT_SBITERR_B_int),
DIN_B_int[29:0]};
ram_data_b[71:64] <= fn_ecc(encode, DIN_B_int[63:0], DIN_B_int[71:64]);
end else if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin
ram_data_b[63:0] <= {DIN_B_int[63],
DIN_B_int[62] ^ (INJECT_DBITERR_B_int),
DIN_B_int[61:31],
DIN_B_int[30] ^ (INJECT_DBITERR_B_int || INJECT_SBITERR_B_int),
DIN_B_int[29:0]};
ram_data_b[71:64] <= DIN_B_int[71:64];
end else begin
ram_data_b <= DIN_B_int;
end
end
end
// ram
always @ (*) begin
if ((auto_sleep || SLEEP_in || SHUTDOWN_in || DEEPSLEEP_in) ||
(((OREG_A_BIN == OREG_A_TRUE) || (OREG_ECC_A_BIN == OREG_ECC_A_TRUE )) &&
(a_sleep || shut_down)))begin
RDACCESS_A_lat <= 1'b0;
end else if ((ram_ce_a_int === 1'b1) && (RDB_WR_A_int === 1'b0)) begin
RDACCESS_A_lat <= 1'b1;
end else begin
RDACCESS_A_lat <= 1'b0;
end
end
always @ (*) begin
if ((auto_sleep || SLEEP_in || SHUTDOWN_in || DEEPSLEEP_in) ||
(((OREG_B_BIN == OREG_B_TRUE) || (OREG_ECC_B_BIN == OREG_ECC_B_TRUE )) &&
(a_sleep || shut_down)))begin
RDACCESS_B_lat <= 1'b0;
end else if ((ram_ce_b_int === 1'b1) && (RDB_WR_B_int === 1'b0)) begin
RDACCESS_B_lat <= 1'b1;
end else begin
RDACCESS_B_lat <= 1'b0;
end
end
`ifndef XIL_XECLIB
// always @ (posedge INIT_RAM or posedge glblGSR) begin
always @ (posedge INIT_RAM) begin
for (wa=0;wa<mem_depth;wa=wa+1) begin
mem[wa] <= D_INIT;
end
end
always @ (posedge shut_down) begin
for (wa=0;wa<mem_depth;wa=wa+1) begin
mem[wa] <= D_UNDEF;
end
end
`endif
always @ (*) begin
if (RST_A_sync || RST_A_async || glblGSR || a_sleep || shut_down) begin
ram_data_a_lat = D_INIT;
end else if (ram_ce_a && ~ram_we_a) begin
ram_data_a_lat = ram_data_a_out;
end
end
always @ (*) begin
if (RST_B_sync || RST_B_async || glblGSR || a_sleep || shut_down) begin
ram_data_b_lat = D_INIT;
end else if (ram_ce_b && ~ram_we_b) begin
ram_data_b_lat = ram_data_b_out;
end
end
`ifdef XIL_XECLIB
always @ (posedge RST_A_async or posedge RST_B_async or posedge CLK_in) begin
`else
always @ (ram_we_a or ram_we_b or ram_ce_a or ram_ce_b or a_sleep or shut_down or ram_addr_a or ram_addr_b or ram_data_a or ram_data_b or ram_bwe_a or ram_bwe_b or ram_we_a_event or ram_we_b_event or posedge RST_A_async or posedge RST_B_async or posedge RST_A_sync or posedge RST_B_sync or glblGSR) begin
`endif
if (RST_A_async || RST_A_sync || shut_down || glblGSR) begin
ram_data_a_out = D_INIT;
end
if (ram_we_a && ~shut_down && ~a_sleep && ~glblGSR) begin
mem [ram_addr_a] = (ram_data_a & ram_bwe_a) | (mem [ram_addr_a] & ~ram_bwe_a);
end
if (ram_ce_a && ~ram_we_a && ~RST_A_in && ~shut_down && ~a_sleep && ~glblGSR) begin
ram_data_a_out = mem[ram_addr_a];
end
if (RST_B_async || RST_B_sync || shut_down || glblGSR) begin
ram_data_b_out = D_INIT;
end
if (ram_we_b && ~shut_down && ~a_sleep && ~glblGSR) begin
mem [ram_addr_b] = (ram_data_b & ram_bwe_b) | (mem [ram_addr_b] & ~ram_bwe_b);
end
if (ram_ce_b && ~ram_we_b && ~RST_B_in && ~shut_down && ~a_sleep && ~glblGSR) begin
ram_data_b_out = mem[ram_addr_b];
end
end
// ecc correction
task ecc_cor;
output [71:0] data_cor; output sbiterr; output dbiterr;
input [71:0] data;
reg [7:0] synd_rd; reg [7:0] synd_ecc; reg decode;
begin
decode = 1'b0;
synd_rd = fn_ecc(decode, data[63:0], data[71:64]);
synd_ecc = synd_rd ^ data[71:64];
sbiterr = (|synd_ecc && synd_ecc[7]);
dbiterr = (|synd_ecc && ~synd_ecc[7]);
if (sbiterr) begin
data_cor = fn_cor_bit(synd_ecc[6:0],data[63:0],data[71:64]);
end else begin
data_cor = data;
end
end
endtask
always @ (*) begin
if (a_sleep || shut_down || glblGSR || (EN_ECC_RD_A_BIN == EN_ECC_RD_A_FALSE)) begin
ram_data_a_ecc <= D_INIT;
end else if (EN_ECC_RD_A_BIN == EN_ECC_RD_A_TRUE) begin
if (OREG_A_BIN == OREG_A_TRUE) begin
ecc_cor(ram_data_a_ecc, SBITERR_A_ecc, DBITERR_A_ecc, ram_data_a_reg);
end else begin
ecc_cor(ram_data_a_ecc, SBITERR_A_ecc, DBITERR_A_ecc, ram_data_a_lat);
end
end
end
always @ (*) begin
if (a_sleep || shut_down || glblGSR || (EN_ECC_RD_B_BIN == EN_ECC_RD_B_FALSE)) begin
ram_data_b_ecc <= D_INIT;
end else if (EN_ECC_RD_B_BIN == EN_ECC_RD_B_TRUE) begin
if (OREG_B_BIN == OREG_B_TRUE) begin
ecc_cor(ram_data_b_ecc, SBITERR_B_ecc, DBITERR_B_ecc, ram_data_b_reg);
end else begin
ecc_cor(ram_data_b_ecc, SBITERR_B_ecc, DBITERR_B_ecc, ram_data_b_lat);
end
end
end
// sleep, deepsleep, shutdown
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR) begin
wake_count <= 0;
end else if (((wake_count > 0) &&
(~(auto_sleep || SLEEP_in || DEEPSLEEP_in || SHUTDOWN_in))) ||
(~(SHUTDOWN_in || DEEPSLEEP_in) && (wake_count > 2)) ||
(~SHUTDOWN_in && (wake_count > 3))) begin
wake_count <= wake_count - 1;
end else if (SHUTDOWN_in) begin
wake_count <= 9;
end else if (DEEPSLEEP_in && (wake_count <= 3)) begin
wake_count <= 3;
end else if (SLEEP_in && (wake_count <= 2)) begin
wake_count <= 2;
end else if (auto_sleep && (wake_count <= 1)) begin
wake_count <= 1;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || (~auto_sleep && wake_count == 1)) begin
a_sleep <= 1'b0;
end else if (DEEPSLEEP_in || SLEEP_in || auto_sleep) begin
a_sleep <= 1'b1;
end
end
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || (wake_count == 1)) begin
shut_down <= 1'b0;
end else if (SHUTDOWN_in) begin
shut_down <= 1'b1;
end
end
assign auto_sleep = auto_sleep_A && auto_sleep_B && ~auto_wake_up_A && ~auto_wake_up_B;
assign auto_wake_up_A = ram_ce_a_fifo[3];
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE)) begin
auto_sleep_A <= 1'b0;
end else if (auto_wake_up_A && auto_sleep_A) begin
auto_sleep_A <= 1'b0;
end else if (~|ram_ce_a_fifo && ~auto_sleep_A) begin
auto_sleep_A <= 1'b1;
end
end
assign auto_wake_up_B = ram_ce_b_fifo[3];
`ifdef XIL_XECLIB
always @ (posedge CLK_in) begin
`else
always @ (posedge CLK_in or glblGSR) begin
`endif
if (glblGSR || (EN_AUTO_SLEEP_MODE_BIN == EN_AUTO_SLEEP_MODE_FALSE)) begin
auto_sleep_B <= 1'b0;
end else if (auto_wake_up_B && auto_sleep_B) begin
auto_sleep_B <= 1'b0;
end else if (~|ram_ce_b_fifo && ~auto_sleep_B) begin
auto_sleep_B <= 1'b1;
end
end
// end behavioral model
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
wire clk_en_n;
wire clk_en_p;
assign clk_en_n = IS_CLK_INVERTED_REG;
assign clk_en_p = ~IS_CLK_INVERTED_REG;
`endif
specify
(CLK *> DOUT_A) = (100:100:100, 100:100:100);
(CLK *> DOUT_B) = (100:100:100, 100:100:100);
(CLK => DBITERR_A) = (100:100:100, 100:100:100);
(CLK => DBITERR_B) = (100:100:100, 100:100:100);
(CLK => SBITERR_A) = (100:100:100, 100:100:100);
(CLK => SBITERR_B) = (100:100:100, 100:100:100);
(negedge RST_A *> (DOUT_A +: 0)) = (100:100:100, 100:100:100);
(negedge RST_A => (DBITERR_A +: 0)) = (100:100:100, 100:100:100);
(negedge RST_A => (SBITERR_A +: 0)) = (100:100:100, 100:100:100);
(negedge RST_B *> (DOUT_B +: 0)) = (100:100:100, 100:100:100);
(negedge RST_B => (DBITERR_B +: 0)) = (100:100:100, 100:100:100);
(negedge RST_B => (SBITERR_B +: 0)) = (100:100:100, 100:100:100);
(posedge RST_A *> (DOUT_A +: 0)) = (100:100:100, 100:100:100);
(posedge RST_A => (DBITERR_A +: 0)) = (100:100:100, 100:100:100);
(posedge RST_A => (SBITERR_A +: 0)) = (100:100:100, 100:100:100);
(posedge RST_B *> (DOUT_B +: 0)) = (100:100:100, 100:100:100);
(posedge RST_B => (DBITERR_B +: 0)) = (100:100:100, 100:100:100);
(posedge RST_B => (SBITERR_B +: 0)) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge CLK, 0:0:0, notifier);
$period (posedge CLK, 0:0:0, notifier);
$recrem (negedge RST_A, negedge CLK, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, RST_A_delay, CLK_delay);
$recrem (negedge RST_A, posedge CLK, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, RST_A_delay, CLK_delay);
$recrem (negedge RST_B, negedge CLK, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, RST_B_delay, CLK_delay);
$recrem (negedge RST_B, posedge CLK, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, RST_B_delay, CLK_delay);
$recrem (posedge RST_A, negedge CLK, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, RST_A_delay, CLK_delay);
$recrem (posedge RST_A, posedge CLK, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, RST_A_delay, CLK_delay);
$recrem (posedge RST_B, negedge CLK, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, RST_B_delay, CLK_delay);
$recrem (posedge RST_B, posedge CLK, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, RST_B_delay, CLK_delay);
$setuphold (negedge CLK, negedge ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ADDR_A_delay);
$setuphold (negedge CLK, negedge ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ADDR_B_delay);
$setuphold (negedge CLK, negedge BWE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, BWE_A_delay);
$setuphold (negedge CLK, negedge BWE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, BWE_B_delay);
$setuphold (negedge CLK, negedge DIN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, DIN_A_delay);
$setuphold (negedge CLK, negedge DIN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, DIN_B_delay);
$setuphold (negedge CLK, negedge EN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, EN_A_delay);
$setuphold (negedge CLK, negedge EN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, EN_B_delay);
$setuphold (negedge CLK, negedge INJECT_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_DBITERR_A_delay);
$setuphold (negedge CLK, negedge INJECT_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_DBITERR_B_delay);
$setuphold (negedge CLK, negedge INJECT_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_SBITERR_A_delay);
$setuphold (negedge CLK, negedge INJECT_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_SBITERR_B_delay);
$setuphold (negedge CLK, negedge OREG_CE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_CE_A_delay);
$setuphold (negedge CLK, negedge OREG_CE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_CE_B_delay);
$setuphold (negedge CLK, negedge OREG_ECC_CE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_ECC_CE_A_delay);
$setuphold (negedge CLK, negedge OREG_ECC_CE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_ECC_CE_B_delay);
$setuphold (negedge CLK, negedge RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RDB_WR_A_delay);
$setuphold (negedge CLK, negedge RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RDB_WR_B_delay);
$setuphold (negedge CLK, negedge RST_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RST_A_delay);
$setuphold (negedge CLK, negedge RST_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RST_B_delay);
$setuphold (negedge CLK, negedge SLEEP, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, SLEEP_delay);
$setuphold (negedge CLK, posedge ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ADDR_A_delay);
$setuphold (negedge CLK, posedge ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, ADDR_B_delay);
$setuphold (negedge CLK, posedge BWE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, BWE_A_delay);
$setuphold (negedge CLK, posedge BWE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, BWE_B_delay);
$setuphold (negedge CLK, posedge DIN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, DIN_A_delay);
$setuphold (negedge CLK, posedge DIN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, DIN_B_delay);
$setuphold (negedge CLK, posedge EN_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, EN_A_delay);
$setuphold (negedge CLK, posedge EN_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, EN_B_delay);
$setuphold (negedge CLK, posedge INJECT_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_DBITERR_A_delay);
$setuphold (negedge CLK, posedge INJECT_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_DBITERR_B_delay);
$setuphold (negedge CLK, posedge INJECT_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_SBITERR_A_delay);
$setuphold (negedge CLK, posedge INJECT_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, INJECT_SBITERR_B_delay);
$setuphold (negedge CLK, posedge OREG_CE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_CE_A_delay);
$setuphold (negedge CLK, posedge OREG_CE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_CE_B_delay);
$setuphold (negedge CLK, posedge OREG_ECC_CE_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_ECC_CE_A_delay);
$setuphold (negedge CLK, posedge OREG_ECC_CE_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, OREG_ECC_CE_B_delay);
$setuphold (negedge CLK, posedge RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RDB_WR_A_delay);
$setuphold (negedge CLK, posedge RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RDB_WR_B_delay);
$setuphold (negedge CLK, posedge RST_A, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RST_A_delay);
$setuphold (negedge CLK, posedge RST_B, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, RST_B_delay);
$setuphold (negedge CLK, posedge SLEEP, 0:0:0, 0:0:0, notifier, clk_en_n, clk_en_n, CLK_delay, SLEEP_delay);
$setuphold (posedge CLK, negedge ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ADDR_A_delay);
$setuphold (posedge CLK, negedge ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ADDR_B_delay);
$setuphold (posedge CLK, negedge BWE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, BWE_A_delay);
$setuphold (posedge CLK, negedge BWE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, BWE_B_delay);
$setuphold (posedge CLK, negedge DIN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, DIN_A_delay);
$setuphold (posedge CLK, negedge DIN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, DIN_B_delay);
$setuphold (posedge CLK, negedge EN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, EN_A_delay);
$setuphold (posedge CLK, negedge EN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, EN_B_delay);
$setuphold (posedge CLK, negedge INJECT_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_DBITERR_A_delay);
$setuphold (posedge CLK, negedge INJECT_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_DBITERR_B_delay);
$setuphold (posedge CLK, negedge INJECT_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_SBITERR_A_delay);
$setuphold (posedge CLK, negedge INJECT_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_SBITERR_B_delay);
$setuphold (posedge CLK, negedge OREG_CE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_CE_A_delay);
$setuphold (posedge CLK, negedge OREG_CE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_CE_B_delay);
$setuphold (posedge CLK, negedge OREG_ECC_CE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_ECC_CE_A_delay);
$setuphold (posedge CLK, negedge OREG_ECC_CE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_ECC_CE_B_delay);
$setuphold (posedge CLK, negedge RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RDB_WR_A_delay);
$setuphold (posedge CLK, negedge RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RDB_WR_B_delay);
$setuphold (posedge CLK, negedge RST_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RST_A_delay);
$setuphold (posedge CLK, negedge RST_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RST_B_delay);
$setuphold (posedge CLK, negedge SLEEP, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, SLEEP_delay);
$setuphold (posedge CLK, posedge ADDR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ADDR_A_delay);
$setuphold (posedge CLK, posedge ADDR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, ADDR_B_delay);
$setuphold (posedge CLK, posedge BWE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, BWE_A_delay);
$setuphold (posedge CLK, posedge BWE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, BWE_B_delay);
$setuphold (posedge CLK, posedge DIN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, DIN_A_delay);
$setuphold (posedge CLK, posedge DIN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, DIN_B_delay);
$setuphold (posedge CLK, posedge EN_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, EN_A_delay);
$setuphold (posedge CLK, posedge EN_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, EN_B_delay);
$setuphold (posedge CLK, posedge INJECT_DBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_DBITERR_A_delay);
$setuphold (posedge CLK, posedge INJECT_DBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_DBITERR_B_delay);
$setuphold (posedge CLK, posedge INJECT_SBITERR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_SBITERR_A_delay);
$setuphold (posedge CLK, posedge INJECT_SBITERR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, INJECT_SBITERR_B_delay);
$setuphold (posedge CLK, posedge OREG_CE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_CE_A_delay);
$setuphold (posedge CLK, posedge OREG_CE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_CE_B_delay);
$setuphold (posedge CLK, posedge OREG_ECC_CE_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_ECC_CE_A_delay);
$setuphold (posedge CLK, posedge OREG_ECC_CE_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, OREG_ECC_CE_B_delay);
$setuphold (posedge CLK, posedge RDB_WR_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RDB_WR_A_delay);
$setuphold (posedge CLK, posedge RDB_WR_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RDB_WR_B_delay);
$setuphold (posedge CLK, posedge RST_A, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RST_A_delay);
$setuphold (posedge CLK, posedge RST_B, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, RST_B_delay);
$setuphold (posedge CLK, posedge SLEEP, 0:0:0, 0:0:0, notifier, clk_en_p, clk_en_p, CLK_delay, SLEEP_delay);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (negedge RST_A, 0:0:0, 0, notifier);
$width (negedge RST_B, 0:0:0, 0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
$width (posedge RST_A, 0:0:0, 0, notifier);
$width (posedge RST_B, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
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