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`timescale 1 ns / 1 ps
module axi_slave_impl_testbench #
(
parameter integer NUMBER_OF_REGISTERS = 6,
parameter integer C_S_AXI_DATA_WIDTH = 32,
parameter integer C_S_AXI_ADDR_WIDTH = 10
)
(
input wire [1:0] register_operation, // 1 - read, 2 - write, 3 - complete
input wire [7 : 0] register_number,
input wire [C_S_AXI_DATA_WIDTH -1 : 0] register_write,
output wire [C_S_AXI_DATA_WIDTH -1 : 0] register_read,
input wire S_AXI_ACLK,
input wire S_AXI_ARESETN,
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
input wire [2 : 0] S_AXI_AWPROT,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
output wire [1 : 0] S_AXI_BRESP,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
input wire [2 : 0] S_AXI_ARPROT,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
output wire [1 : 0] S_AXI_RRESP,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY
);
axi_slave_impl # (
.C_S_AXI_DATA_WIDTH(C_S_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S_AXI_ADDR_WIDTH),
.NUMBER_OF_REGISTERS(NUMBER_OF_REGISTERS)
) testing_axi_slave_impl (
.S_AXI_ACLK(S_AXI_ACLK),
.S_AXI_ARESETN(S_AXI_ARESETN),
.S_AXI_AWADDR(S_AXI_AWADDR),
.S_AXI_AWPROT(S_AXI_AWPROT),
.S_AXI_AWVALID(S_AXI_AWVALID),
.S_AXI_AWREADY(S_AXI_AWREADY),
.S_AXI_WDATA(S_AXI_WDATA),
.S_AXI_WSTRB(S_AXI_WSTRB),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BRESP(S_AXI_BRESP),
.S_AXI_BVALID(S_AXI_BVALID),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_ARADDR(S_AXI_ARADDR),
.S_AXI_ARPROT(S_AXI_ARPROT),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RDATA(S_AXI_RDATA),
.S_AXI_RRESP(S_AXI_RRESP),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY),
.register_operation(register_operation),
.register_number(register_number),
.register_read(register_read),
.register_write(register_write)
);
endmodule
|
`timescale 1ns/1ns
module udp_outbound_chain_rx
(input clk_50,
input clk_100,
input [7:0] rxd,
input rxdv,
input rxlast, // fires HIGH when udp_rx verifies the checksum
output [15:0] hop_count,
output [7:0] submsg_rxd,
output submsg_rxdv,
output submsg_rxlast);
// buffer the incoming packet here until we get an rxlast signal, which
// indicates the UDP packet was sane.
wire [7:0] qrxd;
wire qrxdv, qrxlast;
udp_rxq udp_rxq_inst(.clk(clk_50), .rxd(rxd), .rxdv(rxdv), .rxlast(rxlast),
.qrxd(qrxd), .qrxdv(qrxdv), .qrxlast(qrxlast));
//////////////////////////////////////////////////////////////////////////
localparam SW = 5, CW = 5;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r
(.c(clk_50), .rst(1'b0), .en(1'b1), .d(next_state), .q(state));
localparam ST_IDLE = 5'h0;
localparam ST_PROTO_VER = 5'h1;
localparam ST_HOP_COUNT = 5'h2;
localparam ST_SUBMSG_ADDR = 5'h3;
localparam ST_SUBMSG_LEN = 5'h4;
localparam ST_SUBMSG_PAYLOAD = 5'h5;
localparam ST_SUBMSG_WAIT_FOR_RXLAST = 5'h6; // wait for pad + CRC check
localparam ST_MFIFO_DRAIN = 5'h7; // send rx submsg to rest of chip
localparam ST_DISCARD = 5'h8; // bogus
wire rx_cnt_rst;
wire [10:0] rx_cnt;
r #(11) rx_cnt_r
(.c(clk_50), .rst(rx_cnt_rst), .en(1'b1), .d(rx_cnt+1'b1), .q(rx_cnt));
assign rx_cnt_rst = ctrl[0];
wire [7:0] rxd_d1;
d1 #(8) rxd_d1_r(.c(clk_50), .d(qrxd), .q(rxd_d1));
wire [15:0] rx_16bit = { qrxd, rxd_d1 };
r #(16) hop_count_r
(.c(clk_50), .rst(1'b0), .en(state == ST_HOP_COUNT),
.d(rx_16bit), .q(hop_count));
wire [15:0] submsg_addr;
r #(16) submsg_addr_r
(.c(clk_50), .rst(1'b0), .en(state == ST_SUBMSG_ADDR),
.d(rx_16bit), .q(submsg_addr));
wire [15:0] submsg_len;
r #(16) submsg_len_r
(.c(clk_50), .rst(1'b0), .en(state == ST_SUBMSG_LEN), .d(rx_16bit), .q(submsg_len));
wire submsg_received;
wire wire_submsg_rxdv = ~submsg_received & qrxdv &
hop_count == submsg_addr &
state == ST_SUBMSG_PAYLOAD;
wire [7:0] wire_submsg_rxd = qrxd;
wire wire_submsg_rxdv_d1;
d1 wire_submsg_rxdv_d1_r(.c(clk_50), .d(wire_submsg_rxdv), .q(wire_submsg_rxdv_d1));
r submsg_received_r
(.c(clk_50), .rst(state == ST_IDLE),
.en(wire_submsg_rxdv_d1 & ~wire_submsg_rxdv),
.d(1'b1), .q(submsg_received));
wire rx_rxlast;
r rx_rxlast_r
(.c(clk_50), .rst(state == ST_IDLE), .en(qrxlast), .d(1'b1), .q(rx_rxlast));
wire mfifo_almost_empty;
always @* begin
case (state)
ST_IDLE:
if (qrxdv) ctrl = { ST_PROTO_VER , 5'b00000 };
else ctrl = { ST_IDLE , 5'b00001 };
ST_PROTO_VER:
if (~qrxdv) ctrl = { ST_IDLE , 5'b00000 };
else if (rx_16bit == 16'h4321)ctrl = { ST_HOP_COUNT , 5'b00001 };
else ctrl = { ST_DISCARD , 5'b00000 };
ST_HOP_COUNT:
if (~qrxdv) ctrl = { ST_IDLE , 5'b00000 };
else if (rx_cnt == 16'h1) ctrl = { ST_SUBMSG_ADDR, 5'b00001 };
else ctrl = { ST_HOP_COUNT , 5'b00000 };
ST_SUBMSG_ADDR:
if (~qrxdv) ctrl = { ST_SUBMSG_WAIT_FOR_RXLAST, 5'b00001 };
else if (rx_cnt == 16'h1) ctrl = { ST_SUBMSG_LEN , 5'b00001 };
else ctrl = { ST_SUBMSG_ADDR, 5'b00000 };
ST_SUBMSG_LEN:
if (~qrxdv) ctrl = { ST_SUBMSG_WAIT_FOR_RXLAST, 5'b00001 };
else if (rx_cnt == 16'h1) ctrl = { ST_SUBMSG_PAYLOAD, 5'b00001 };
else ctrl = { ST_SUBMSG_LEN , 5'b00000 };
ST_SUBMSG_PAYLOAD:
if (~qrxdv) ctrl = { ST_SUBMSG_WAIT_FOR_RXLAST, 5'b00001 };
else if (rx_cnt + 1'b1 == submsg_len)
ctrl = { ST_SUBMSG_ADDR , 5'b00001 };
else ctrl = { ST_SUBMSG_PAYLOAD, 5'b00000 };
ST_SUBMSG_WAIT_FOR_RXLAST:
if (~submsg_received) ctrl = { ST_MFIFO_DRAIN , 5'b00000 };
else if (qrxlast) ctrl = { ST_MFIFO_DRAIN , 5'b00000 };
else if (rx_cnt == 16'h30) ctrl = { ST_MFIFO_DRAIN , 5'b00000 };
else ctrl = { ST_SUBMSG_WAIT_FOR_RXLAST, 5'b00000 };
ST_MFIFO_DRAIN:
if (mfifo_drained) ctrl = { ST_IDLE , 5'b00000 };
else ctrl = { ST_MFIFO_DRAIN , 5'b00000 };
ST_DISCARD:
if (~qrxdv) ctrl = { ST_IDLE , 5'b00000 };
else ctrl = { ST_DISCARD , 5'b00000 };
default: ctrl = { ST_IDLE , 5'b00000 };
endcase
end
wire mfifo_empty;
wire mfifo_draining;
wire [10:0] mfifo_rdusedw;
dcfifo #(.lpm_width(8),
.lpm_numwords(2048),
.lpm_widthu(11),
.lpm_showahead("ON"),
.use_eab("ON"),
.intended_device_family("CYCLONE V")) mfifo // submessage fifo
(.wrclk(clk_50), .wrreq(wire_submsg_rxdv), .data(wire_submsg_rxd),
.rdclk(clk_100), .rdreq(mfifo_draining & ~mfifo_empty), .q(submsg_rxd),
.rdempty(mfifo_empty),
.rdusedw(mfifo_rdusedw),
.aclr(1'b0));
wire submsg_received_clk100;
sync submsg_received_sync_r(.in(submsg_received), .clk(clk_100), .out(submsg_received_clk100));
wire mfifo_drained;
sync mfifo_drained_sync_r
(.in(mfifo_empty), .clk(clk_50), .out(mfifo_drained));
wire mfifo_drain_req_clk100;
sync mfifo_drain_req_sync_r
(.in(state == ST_MFIFO_DRAIN), .clk(clk_100), .out(mfifo_drain_req_clk100));
r mfifo_draining_r
(.c(clk_100), .rst(mfifo_empty), .d(1'b1), .q(mfifo_draining),
.en(mfifo_drain_req_clk100));
assign submsg_rxdv = mfifo_draining & submsg_received_clk100 & ~mfifo_empty;
assign submsg_rxlast = mfifo_draining & submsg_received_clk100 & mfifo_rdusedw == 11'h2;
endmodule
`ifdef test_udp_outbound_chain_rx
module udp_outbound_chain_rx_tb();
wire clk_100, clk_50;
sim_clk #(100) clk_100_inst(clk_100);
sim_clk #( 50) clk_50_inst (clk_50 );
reg [7:0] rxd;
reg rxdv;
reg rxlast;
wire [7:0] submsg_rxd;
wire submsg_rxdv;
wire submsg_rxlast;
udp_outbound_chain_rx dut(.*);
localparam PKT_LEN = 16;
reg [7:0] pkt [PKT_LEN-1:0];
integer i;
initial begin
$dumpfile("udp_outbound_chain_rx.lxt");
$dumpvars();
pkt[0] = 8'h1; // protocol low
pkt[1] = 8'h0; // protocol high
pkt[2] = 8'h0; // hop count low
pkt[3] = 8'h0; // hop count high
pkt[4] = 8'h0; // submsg addr low
pkt[5] = 8'h0; // submsg addr high
pkt[6] = 8'h2; // submsg len low
pkt[7] = 8'h0; // submsg len high
pkt[8] = 8'h12; // payload byte 0
pkt[9] = 8'h34; // payload byte 1
////
pkt[10] = 8'h1; // submsg addr low
pkt[11] = 8'h0; // submsg addr high
pkt[12] = 8'h2; // submsg len low
pkt[13] = 8'h0; // submsg len high
pkt[14] = 8'h56; // payload byte 0
pkt[15] = 8'h78; // payload byte 1
////
rxd = 1'b0;
rxdv = 8'h0;
rxlast = 1'b0;
#100;
wait(~clk_50);
wait(clk_50);
rxdv <= 1'b1;
for (i = 0; i < PKT_LEN; i = i + 1) begin
rxd <= pkt[i];
if (i == PKT_LEN - 1)
rxlast = 1;
wait(~clk_50);
wait(clk_50);
end
rxdv = 1'b0;
rxd = 8'h0;
rxlast = 1'b0;
#2000;
$finish();
end
endmodule
`endif
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.58f
// \ \ Application: netgen
// / / Filename: neg_float.v
// /___/ /\ Timestamp: Thu Feb 4 16:19:44 2016
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/jhegarty/lol/ipcore_dir/tmp/_cg/neg_float.ngc /home/jhegarty/lol/ipcore_dir/tmp/_cg/neg_float.v
// Device : 7z100ffg900-2
// Input file : /home/jhegarty/lol/ipcore_dir/tmp/_cg/neg_float.ngc
// Output file : /home/jhegarty/lol/ipcore_dir/tmp/_cg/neg_float.v
// # of Modules : 1
// Design Name : neg_float
// Xilinx : /opt/Xilinx/14.5/ISE_DS/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
module invert_float_float (
// aclk, aclken, s_axis_a_tvalid, m_axis_result_tvalid, s_axis_a_tdata, m_axis_result_tdata
CLK, ce, inp, out
);
// input aclk;
parameter INSTANCE_NAME="INST";
input wire CLK;
input wire ce;
input [31 : 0] inp;
output [31 : 0] out;
// input aclken;
// input s_axis_a_tvalid;
//output m_axis_result_tvalid;
// input [31 : 0] s_axis_a_tdata;
// output [31 : 0] m_axis_result_tdata;
wire aclk;
assign aclk = CLK;
wire aclken;
assign aclken = ce;
wire s_axis_a_tvalid;
assign s_axis_a_tvalid = 1'b1;
wire m_axis_result_tvalid;
wire [31:0] s_axis_a_tdata;
assign s_axis_a_tdata = inp;
wire [31:0] m_axis_result_tdata;
assign out = m_axis_result_tdata;
wire \blk00000001/sig000002cb ;
wire \blk00000001/sig000002ca ;
wire \blk00000001/sig000002c9 ;
wire \blk00000001/sig000002c8 ;
wire \blk00000001/sig000002c7 ;
wire \blk00000001/sig000002c6 ;
wire \blk00000001/sig000002c5 ;
wire \blk00000001/sig000002c4 ;
wire \blk00000001/sig000002c3 ;
wire \blk00000001/sig000002c2 ;
wire \blk00000001/sig000002c1 ;
wire \blk00000001/sig000002c0 ;
wire \blk00000001/sig000002bf ;
wire \blk00000001/sig000002be ;
wire \blk00000001/sig000002bd ;
wire \blk00000001/sig000002bc ;
wire \blk00000001/sig000002bb ;
wire \blk00000001/sig000002ba ;
wire \blk00000001/sig000002b9 ;
wire \blk00000001/sig000002b8 ;
wire \blk00000001/sig000002b7 ;
wire \blk00000001/sig000002b6 ;
wire \blk00000001/sig000002b5 ;
wire \blk00000001/sig000002b4 ;
wire \blk00000001/sig000002b3 ;
wire \blk00000001/sig000002b2 ;
wire \blk00000001/sig000002b1 ;
wire \blk00000001/sig000002b0 ;
wire \blk00000001/sig000002af ;
wire \blk00000001/sig000002ae ;
wire \blk00000001/sig000002ad ;
wire \blk00000001/sig000002ac ;
wire \blk00000001/sig000002ab ;
wire \blk00000001/sig000002aa ;
wire \blk00000001/sig000002a9 ;
wire \blk00000001/sig000002a8 ;
wire \blk00000001/sig000002a7 ;
wire \blk00000001/sig000002a6 ;
wire \blk00000001/sig000002a5 ;
wire \blk00000001/sig000002a4 ;
wire \blk00000001/sig000002a3 ;
wire \blk00000001/sig000002a2 ;
wire \blk00000001/sig000002a1 ;
wire \blk00000001/sig000002a0 ;
wire \blk00000001/sig0000029f ;
wire \blk00000001/sig0000029e ;
wire \blk00000001/sig0000029d ;
wire \blk00000001/sig0000029c ;
wire \blk00000001/sig0000029b ;
wire \blk00000001/sig0000029a ;
wire \blk00000001/sig00000299 ;
wire \blk00000001/sig00000298 ;
wire \blk00000001/sig00000297 ;
wire \blk00000001/sig00000296 ;
wire \blk00000001/sig00000295 ;
wire \blk00000001/sig00000294 ;
wire \blk00000001/sig00000293 ;
wire \blk00000001/sig00000292 ;
wire \blk00000001/sig00000291 ;
wire \blk00000001/sig00000290 ;
wire \blk00000001/sig0000028f ;
wire \blk00000001/sig0000028e ;
wire \blk00000001/sig0000028d ;
wire \blk00000001/sig0000028c ;
wire \blk00000001/sig0000028b ;
wire \blk00000001/sig0000028a ;
wire \blk00000001/sig00000289 ;
wire \blk00000001/sig00000288 ;
wire \blk00000001/sig00000287 ;
wire \blk00000001/sig00000286 ;
wire \blk00000001/sig00000285 ;
wire \blk00000001/sig00000284 ;
wire \blk00000001/sig00000283 ;
wire \blk00000001/sig00000282 ;
wire \blk00000001/sig00000281 ;
wire \blk00000001/sig00000280 ;
wire \blk00000001/sig0000027f ;
wire \blk00000001/sig0000027e ;
wire \blk00000001/sig0000027d ;
wire \blk00000001/sig0000027c ;
wire \blk00000001/sig0000027b ;
wire \blk00000001/sig0000027a ;
wire \blk00000001/sig00000279 ;
wire \blk00000001/sig00000278 ;
wire \blk00000001/sig00000277 ;
wire \blk00000001/sig00000276 ;
wire \blk00000001/sig00000275 ;
wire \blk00000001/sig00000274 ;
wire \blk00000001/sig00000273 ;
wire \blk00000001/sig00000272 ;
wire \blk00000001/sig00000271 ;
wire \blk00000001/sig00000270 ;
wire \blk00000001/sig0000026f ;
wire \blk00000001/sig0000026e ;
wire \blk00000001/sig0000026d ;
wire \blk00000001/sig0000026c ;
wire \blk00000001/sig0000026b ;
wire \blk00000001/sig0000026a ;
wire \blk00000001/sig00000269 ;
wire \blk00000001/sig00000268 ;
wire \blk00000001/sig00000267 ;
wire \blk00000001/sig00000266 ;
wire \blk00000001/sig00000265 ;
wire \blk00000001/sig00000264 ;
wire \blk00000001/sig00000263 ;
wire \blk00000001/sig00000262 ;
wire \blk00000001/sig00000261 ;
wire \blk00000001/sig00000260 ;
wire \blk00000001/sig0000025f ;
wire \blk00000001/sig0000025e ;
wire \blk00000001/sig0000025d ;
wire \blk00000001/sig0000025c ;
wire \blk00000001/sig0000025b ;
wire \blk00000001/sig0000025a ;
wire \blk00000001/sig00000259 ;
wire \blk00000001/sig00000258 ;
wire \blk00000001/sig00000257 ;
wire \blk00000001/sig00000256 ;
wire \blk00000001/sig00000255 ;
wire \blk00000001/sig00000254 ;
wire \blk00000001/sig00000253 ;
wire \blk00000001/sig00000252 ;
wire \blk00000001/sig00000251 ;
wire \blk00000001/sig00000250 ;
wire \blk00000001/sig0000024f ;
wire \blk00000001/sig0000024e ;
wire \blk00000001/sig0000024d ;
wire \blk00000001/sig0000024c ;
wire \blk00000001/sig0000024b ;
wire \blk00000001/sig0000024a ;
wire \blk00000001/sig00000249 ;
wire \blk00000001/sig00000248 ;
wire \blk00000001/sig00000247 ;
wire \blk00000001/sig00000246 ;
wire \blk00000001/sig00000245 ;
wire \blk00000001/sig00000244 ;
wire \blk00000001/sig00000243 ;
wire \blk00000001/sig00000242 ;
wire \blk00000001/sig00000241 ;
wire \blk00000001/sig00000240 ;
wire \blk00000001/sig0000023f ;
wire \blk00000001/sig0000023e ;
wire \blk00000001/sig0000023d ;
wire \blk00000001/sig0000023c ;
wire \blk00000001/sig0000023b ;
wire \blk00000001/sig0000023a ;
wire \blk00000001/sig00000239 ;
wire \blk00000001/sig00000238 ;
wire \blk00000001/sig00000237 ;
wire \blk00000001/sig00000236 ;
wire \blk00000001/sig00000235 ;
wire \blk00000001/sig00000234 ;
wire \blk00000001/sig00000233 ;
wire \blk00000001/sig00000232 ;
wire \blk00000001/sig00000231 ;
wire \blk00000001/sig00000230 ;
wire \blk00000001/sig0000022f ;
wire \blk00000001/sig0000022e ;
wire \blk00000001/sig0000022d ;
wire \blk00000001/sig0000022c ;
wire \blk00000001/sig0000022b ;
wire \blk00000001/sig0000022a ;
wire \blk00000001/sig00000229 ;
wire \blk00000001/sig00000228 ;
wire \blk00000001/sig00000227 ;
wire \blk00000001/sig00000226 ;
wire \blk00000001/sig00000225 ;
wire \blk00000001/sig00000224 ;
wire \blk00000001/sig00000223 ;
wire \blk00000001/sig00000222 ;
wire \blk00000001/sig00000221 ;
wire \blk00000001/sig00000220 ;
wire \blk00000001/sig0000021f ;
wire \blk00000001/sig0000021e ;
wire \blk00000001/sig0000021d ;
wire \blk00000001/sig0000021c ;
wire \blk00000001/sig0000021b ;
wire \blk00000001/sig0000021a ;
wire \blk00000001/sig00000219 ;
wire \blk00000001/sig00000218 ;
wire \blk00000001/sig00000217 ;
wire \blk00000001/sig00000216 ;
wire \blk00000001/sig00000215 ;
wire \blk00000001/sig00000214 ;
wire \blk00000001/sig00000213 ;
wire \blk00000001/sig00000212 ;
wire \blk00000001/sig00000211 ;
wire \blk00000001/sig00000210 ;
wire \blk00000001/sig0000020f ;
wire \blk00000001/sig0000020e ;
wire \blk00000001/sig0000020d ;
wire \blk00000001/sig0000020c ;
wire \blk00000001/sig0000020b ;
wire \blk00000001/sig0000020a ;
wire \blk00000001/sig00000209 ;
wire \blk00000001/sig00000208 ;
wire \blk00000001/sig00000207 ;
wire \blk00000001/sig00000206 ;
wire \blk00000001/sig00000205 ;
wire \blk00000001/sig00000204 ;
wire \blk00000001/sig00000203 ;
wire \blk00000001/sig00000202 ;
wire \blk00000001/sig00000201 ;
wire \blk00000001/sig00000200 ;
wire \blk00000001/sig000001ff ;
wire \blk00000001/sig000001fe ;
wire \blk00000001/sig000001fd ;
wire \blk00000001/sig000001fc ;
wire \blk00000001/sig000001fb ;
wire \blk00000001/sig000001fa ;
wire \blk00000001/sig000001f9 ;
wire \blk00000001/sig000001f8 ;
wire \blk00000001/sig000001f7 ;
wire \blk00000001/sig000001f6 ;
wire \blk00000001/sig000001f5 ;
wire \blk00000001/sig000001f4 ;
wire \blk00000001/sig000001f3 ;
wire \blk00000001/sig000001f2 ;
wire \blk00000001/sig000001f1 ;
wire \blk00000001/sig000001f0 ;
wire \blk00000001/sig000001ef ;
wire \blk00000001/sig000001ee ;
wire \blk00000001/sig000001ed ;
wire \blk00000001/sig000001ec ;
wire \blk00000001/sig000001eb ;
wire \blk00000001/sig000001ea ;
wire \blk00000001/sig000001e9 ;
wire \blk00000001/sig000001e8 ;
wire \blk00000001/sig000001e7 ;
wire \blk00000001/sig000001e6 ;
wire \blk00000001/sig000001e5 ;
wire \blk00000001/sig000001e4 ;
wire \blk00000001/sig000001e3 ;
wire \blk00000001/sig000001e2 ;
wire \blk00000001/sig000001e1 ;
wire \blk00000001/sig000001e0 ;
wire \blk00000001/sig000001df ;
wire \blk00000001/sig000001de ;
wire \blk00000001/sig000001dd ;
wire \blk00000001/sig000001dc ;
wire \blk00000001/sig000001db ;
wire \blk00000001/sig000001da ;
wire \blk00000001/sig000001d9 ;
wire \blk00000001/sig000001d8 ;
wire \blk00000001/sig000001d7 ;
wire \blk00000001/sig000001d6 ;
wire \blk00000001/sig000001d5 ;
wire \blk00000001/sig000001d4 ;
wire \blk00000001/sig000001d3 ;
wire \blk00000001/sig000001d2 ;
wire \blk00000001/sig000001d1 ;
wire \blk00000001/sig000001d0 ;
wire \blk00000001/sig000001cf ;
wire \blk00000001/sig000001ce ;
wire \blk00000001/sig000001cd ;
wire \blk00000001/sig000001cc ;
wire \blk00000001/sig000001cb ;
wire \blk00000001/sig000001ca ;
wire \blk00000001/sig000001c9 ;
wire \blk00000001/sig000001c8 ;
wire \blk00000001/sig000001c7 ;
wire \blk00000001/sig000001c6 ;
wire \blk00000001/sig000001c5 ;
wire \blk00000001/sig000001c4 ;
wire \blk00000001/sig000001c3 ;
wire \blk00000001/sig000001c2 ;
wire \blk00000001/sig000001c1 ;
wire \blk00000001/sig000001c0 ;
wire \blk00000001/sig000001bf ;
wire \blk00000001/sig000001be ;
wire \blk00000001/sig000001bd ;
wire \blk00000001/sig000001bc ;
wire \blk00000001/sig000001bb ;
wire \blk00000001/sig000001ba ;
wire \blk00000001/sig000001b9 ;
wire \blk00000001/sig000001b8 ;
wire \blk00000001/sig000001b7 ;
wire \blk00000001/sig000001b6 ;
wire \blk00000001/sig000001b5 ;
wire \blk00000001/sig000001b4 ;
wire \blk00000001/sig000001b3 ;
wire \blk00000001/sig000001b2 ;
wire \blk00000001/sig000001b1 ;
wire \blk00000001/sig000001b0 ;
wire \blk00000001/sig000001af ;
wire \blk00000001/sig000001ae ;
wire \blk00000001/sig000001ad ;
wire \blk00000001/sig000001ac ;
wire \blk00000001/sig000001ab ;
wire \blk00000001/sig000001aa ;
wire \blk00000001/sig000001a9 ;
wire \blk00000001/sig000001a8 ;
wire \blk00000001/sig000001a7 ;
wire \blk00000001/sig000001a6 ;
wire \blk00000001/sig000001a5 ;
wire \blk00000001/sig000001a4 ;
wire \blk00000001/sig000001a3 ;
wire \blk00000001/sig000001a2 ;
wire \blk00000001/sig000001a1 ;
wire \blk00000001/sig000001a0 ;
wire \blk00000001/sig0000019f ;
wire \blk00000001/sig0000019e ;
wire \blk00000001/sig0000019d ;
wire \blk00000001/sig0000019c ;
wire \blk00000001/sig0000019b ;
wire \blk00000001/sig0000019a ;
wire \blk00000001/sig00000199 ;
wire \blk00000001/sig00000198 ;
wire \blk00000001/sig00000197 ;
wire \blk00000001/sig00000196 ;
wire \blk00000001/sig00000195 ;
wire \blk00000001/sig00000194 ;
wire \blk00000001/sig00000193 ;
wire \blk00000001/sig00000192 ;
wire \blk00000001/sig00000191 ;
wire \blk00000001/sig00000190 ;
wire \blk00000001/sig0000018f ;
wire \blk00000001/sig0000018e ;
wire \blk00000001/sig0000018d ;
wire \blk00000001/sig0000018c ;
wire \blk00000001/sig0000018b ;
wire \blk00000001/sig0000018a ;
wire \blk00000001/sig00000189 ;
wire \blk00000001/sig00000188 ;
wire \blk00000001/sig00000187 ;
wire \blk00000001/sig00000186 ;
wire \blk00000001/sig00000185 ;
wire \blk00000001/sig00000184 ;
wire \blk00000001/sig00000183 ;
wire \blk00000001/sig00000182 ;
wire \blk00000001/sig00000181 ;
wire \blk00000001/sig00000180 ;
wire \blk00000001/sig0000017f ;
wire \blk00000001/sig0000017e ;
wire \blk00000001/sig0000017d ;
wire \blk00000001/sig0000017c ;
wire \blk00000001/sig0000017b ;
wire \blk00000001/sig0000017a ;
wire \blk00000001/sig00000179 ;
wire \blk00000001/sig00000178 ;
wire \blk00000001/sig00000177 ;
wire \blk00000001/sig00000176 ;
wire \blk00000001/sig00000175 ;
wire \blk00000001/sig00000174 ;
wire \blk00000001/sig00000173 ;
wire \blk00000001/sig00000172 ;
wire \blk00000001/sig00000171 ;
wire \blk00000001/sig00000170 ;
wire \blk00000001/sig0000016f ;
wire \blk00000001/sig0000016e ;
wire \blk00000001/sig0000016d ;
wire \blk00000001/sig0000016c ;
wire \blk00000001/sig0000016b ;
wire \blk00000001/sig0000016a ;
wire \blk00000001/sig00000169 ;
wire \blk00000001/sig00000168 ;
wire \blk00000001/sig00000167 ;
wire \blk00000001/sig00000166 ;
wire \blk00000001/sig00000165 ;
wire \blk00000001/sig00000164 ;
wire \blk00000001/sig00000163 ;
wire \blk00000001/sig00000162 ;
wire \blk00000001/sig00000161 ;
wire \blk00000001/sig00000160 ;
wire \blk00000001/sig0000015f ;
wire \blk00000001/sig0000015e ;
wire \blk00000001/sig0000015d ;
wire \blk00000001/sig0000015c ;
wire \blk00000001/sig0000015b ;
wire \blk00000001/sig0000015a ;
wire \blk00000001/sig00000159 ;
wire \blk00000001/sig00000158 ;
wire \blk00000001/sig00000157 ;
wire \blk00000001/sig00000156 ;
wire \blk00000001/sig00000155 ;
wire \blk00000001/sig00000154 ;
wire \blk00000001/sig00000153 ;
wire \blk00000001/sig00000152 ;
wire \blk00000001/sig00000151 ;
wire \blk00000001/sig00000150 ;
wire \blk00000001/sig0000014f ;
wire \blk00000001/sig0000014e ;
wire \blk00000001/sig0000014d ;
wire \blk00000001/sig0000014c ;
wire \blk00000001/sig0000014b ;
wire \blk00000001/sig0000014a ;
wire \blk00000001/sig00000149 ;
wire \blk00000001/sig00000148 ;
wire \blk00000001/sig00000147 ;
wire \blk00000001/sig00000146 ;
wire \blk00000001/sig00000145 ;
wire \blk00000001/sig00000144 ;
wire \blk00000001/sig00000143 ;
wire \blk00000001/sig00000142 ;
wire \blk00000001/sig00000141 ;
wire \blk00000001/sig00000140 ;
wire \blk00000001/sig0000013f ;
wire \blk00000001/sig0000013e ;
wire \blk00000001/sig0000013d ;
wire \blk00000001/sig0000013c ;
wire \blk00000001/sig0000013b ;
wire \blk00000001/sig0000013a ;
wire \blk00000001/sig00000139 ;
wire \blk00000001/sig00000138 ;
wire \blk00000001/sig00000137 ;
wire \blk00000001/sig00000136 ;
wire \blk00000001/sig00000135 ;
wire \blk00000001/sig00000134 ;
wire \blk00000001/sig00000133 ;
wire \blk00000001/sig00000132 ;
wire \blk00000001/sig00000131 ;
wire \blk00000001/sig00000130 ;
wire \blk00000001/sig0000012f ;
wire \blk00000001/sig0000012e ;
wire \blk00000001/sig0000012d ;
wire \blk00000001/sig0000012c ;
wire \blk00000001/sig0000012b ;
wire \blk00000001/sig0000012a ;
wire \blk00000001/sig00000129 ;
wire \blk00000001/sig00000128 ;
wire \blk00000001/sig00000127 ;
wire \blk00000001/sig00000126 ;
wire \blk00000001/sig00000125 ;
wire \blk00000001/sig00000124 ;
wire \blk00000001/sig00000123 ;
wire \blk00000001/sig00000122 ;
wire \blk00000001/sig00000121 ;
wire \blk00000001/sig00000120 ;
wire \blk00000001/sig0000011f ;
wire \blk00000001/sig0000011e ;
wire \blk00000001/sig0000011d ;
wire \blk00000001/sig0000011c ;
wire \blk00000001/sig0000011b ;
wire \blk00000001/sig0000011a ;
wire \blk00000001/sig00000119 ;
wire \blk00000001/sig00000118 ;
wire \blk00000001/sig00000117 ;
wire \blk00000001/sig00000116 ;
wire \blk00000001/sig00000115 ;
wire \blk00000001/sig00000114 ;
wire \blk00000001/sig00000113 ;
wire \blk00000001/sig00000112 ;
wire \blk00000001/sig00000111 ;
wire \blk00000001/sig00000110 ;
wire \blk00000001/sig0000010f ;
wire \blk00000001/sig0000010e ;
wire \blk00000001/sig0000010d ;
wire \blk00000001/sig0000010c ;
wire \blk00000001/sig0000010b ;
wire \blk00000001/sig0000010a ;
wire \blk00000001/sig00000109 ;
wire \blk00000001/sig00000108 ;
wire \blk00000001/sig00000107 ;
wire \blk00000001/sig00000106 ;
wire \blk00000001/sig00000105 ;
wire \blk00000001/sig00000104 ;
wire \blk00000001/sig00000103 ;
wire \blk00000001/sig00000102 ;
wire \blk00000001/sig00000101 ;
wire \blk00000001/sig00000100 ;
wire \blk00000001/sig000000ff ;
wire \blk00000001/sig000000fe ;
wire \blk00000001/sig000000fd ;
wire \blk00000001/sig000000fc ;
wire \blk00000001/sig000000fb ;
wire \blk00000001/sig000000fa ;
wire \blk00000001/sig000000f9 ;
wire \blk00000001/sig000000f8 ;
wire \blk00000001/sig000000f7 ;
wire \blk00000001/sig000000f6 ;
wire \blk00000001/sig000000f5 ;
wire \blk00000001/sig000000f4 ;
wire \blk00000001/sig000000f3 ;
wire \blk00000001/sig000000f2 ;
wire \blk00000001/sig000000f1 ;
wire \blk00000001/sig000000f0 ;
wire \blk00000001/sig000000ef ;
wire \blk00000001/sig000000ee ;
wire \blk00000001/sig000000ed ;
wire \blk00000001/sig000000ec ;
wire \blk00000001/sig000000eb ;
wire \blk00000001/sig000000ea ;
wire \blk00000001/sig000000e9 ;
wire \blk00000001/sig000000e8 ;
wire \blk00000001/sig000000e7 ;
wire \blk00000001/sig000000e6 ;
wire \blk00000001/sig000000e5 ;
wire \blk00000001/sig000000e4 ;
wire \blk00000001/sig000000e3 ;
wire \blk00000001/sig000000e2 ;
wire \blk00000001/sig000000e1 ;
wire \blk00000001/sig000000e0 ;
wire \blk00000001/sig000000df ;
wire \blk00000001/sig000000de ;
wire \blk00000001/sig000000dd ;
wire \blk00000001/sig000000dc ;
wire \blk00000001/sig000000db ;
wire \blk00000001/sig000000da ;
wire \blk00000001/sig000000d9 ;
wire \blk00000001/sig000000d8 ;
wire \blk00000001/sig000000d7 ;
wire \blk00000001/sig000000d6 ;
wire \blk00000001/sig000000d5 ;
wire \blk00000001/sig000000d4 ;
wire \blk00000001/sig000000d3 ;
wire \blk00000001/sig000000d2 ;
wire \blk00000001/sig000000d1 ;
wire \blk00000001/sig000000d0 ;
wire \blk00000001/sig000000cf ;
wire \blk00000001/sig000000ce ;
wire \blk00000001/sig000000cd ;
wire \blk00000001/sig000000cc ;
wire \blk00000001/sig000000cb ;
wire \blk00000001/sig000000ca ;
wire \blk00000001/sig000000c9 ;
wire \blk00000001/sig000000c8 ;
wire \blk00000001/sig000000c7 ;
wire \blk00000001/sig000000c6 ;
wire \blk00000001/sig000000c5 ;
wire \blk00000001/sig000000c4 ;
wire \blk00000001/sig000000c3 ;
wire \blk00000001/sig000000c2 ;
wire \blk00000001/sig000000c1 ;
wire \blk00000001/sig000000c0 ;
wire \blk00000001/sig000000bf ;
wire \blk00000001/sig000000be ;
wire \blk00000001/sig000000bd ;
wire \blk00000001/sig000000bc ;
wire \blk00000001/sig000000bb ;
wire \blk00000001/sig000000ba ;
wire \blk00000001/sig000000b9 ;
wire \blk00000001/sig000000b8 ;
wire \blk00000001/sig000000b7 ;
wire \blk00000001/sig000000b6 ;
wire \blk00000001/sig000000b5 ;
wire \blk00000001/sig000000b4 ;
wire \blk00000001/sig000000b3 ;
wire \blk00000001/sig000000b2 ;
wire \blk00000001/sig000000b1 ;
wire \blk00000001/sig000000b0 ;
wire \blk00000001/sig000000af ;
wire \blk00000001/sig000000ae ;
wire \blk00000001/sig000000ad ;
wire \blk00000001/sig000000ac ;
wire \blk00000001/sig000000ab ;
wire \blk00000001/sig000000aa ;
wire \blk00000001/sig000000a9 ;
wire \blk00000001/sig000000a8 ;
wire \blk00000001/sig000000a7 ;
wire \blk00000001/sig000000a6 ;
wire \blk00000001/sig000000a5 ;
wire \blk00000001/sig000000a4 ;
wire \blk00000001/sig000000a3 ;
wire \blk00000001/sig000000a2 ;
wire \blk00000001/sig000000a1 ;
wire \blk00000001/sig000000a0 ;
wire \blk00000001/sig0000009f ;
wire \blk00000001/sig0000009e ;
wire \blk00000001/sig0000009d ;
wire \blk00000001/sig0000009c ;
wire \blk00000001/sig0000009b ;
wire \blk00000001/sig0000009a ;
wire \blk00000001/sig00000099 ;
wire \blk00000001/sig00000098 ;
wire \blk00000001/sig00000097 ;
wire \blk00000001/sig00000096 ;
wire \blk00000001/sig00000095 ;
wire \blk00000001/sig00000094 ;
wire \blk00000001/sig00000093 ;
wire \blk00000001/sig00000092 ;
wire \blk00000001/sig00000091 ;
wire \blk00000001/sig00000090 ;
wire \blk00000001/sig0000008f ;
wire \blk00000001/sig0000008e ;
wire \blk00000001/sig0000008d ;
wire \blk00000001/sig0000008c ;
wire \blk00000001/sig0000008b ;
wire \blk00000001/sig0000008a ;
wire \blk00000001/sig00000089 ;
wire \blk00000001/sig00000088 ;
wire \blk00000001/sig00000087 ;
wire \blk00000001/sig00000086 ;
wire \blk00000001/sig00000085 ;
wire \blk00000001/sig00000084 ;
wire \blk00000001/sig00000083 ;
wire \blk00000001/sig00000082 ;
wire \blk00000001/sig00000081 ;
wire \blk00000001/sig00000080 ;
wire \blk00000001/sig0000007f ;
wire \blk00000001/sig0000007e ;
wire \blk00000001/sig0000007d ;
wire \blk00000001/sig0000007c ;
wire \blk00000001/sig0000007b ;
wire \blk00000001/sig0000007a ;
wire \blk00000001/sig00000079 ;
wire \blk00000001/sig00000078 ;
wire \blk00000001/sig00000077 ;
wire \blk00000001/sig00000076 ;
wire \blk00000001/sig00000075 ;
wire \blk00000001/sig00000074 ;
wire \blk00000001/sig00000073 ;
wire \blk00000001/sig00000072 ;
wire \blk00000001/sig00000071 ;
wire \blk00000001/sig00000070 ;
wire \blk00000001/sig0000006f ;
wire \blk00000001/sig0000006e ;
wire \blk00000001/sig0000006d ;
wire \blk00000001/sig0000006c ;
wire \blk00000001/sig0000006b ;
wire \blk00000001/sig0000006a ;
wire \blk00000001/sig00000069 ;
wire \blk00000001/sig00000068 ;
wire \blk00000001/sig00000067 ;
wire \blk00000001/sig00000066 ;
wire \blk00000001/sig00000065 ;
wire \blk00000001/sig00000064 ;
wire \blk00000001/sig00000063 ;
wire \blk00000001/sig00000062 ;
wire \blk00000001/sig00000061 ;
wire \blk00000001/sig00000060 ;
wire \blk00000001/sig0000005f ;
wire \blk00000001/sig0000005e ;
wire \blk00000001/sig0000005d ;
wire \blk00000001/sig0000005c ;
wire \blk00000001/sig0000005b ;
wire \blk00000001/sig0000005a ;
wire \blk00000001/sig00000059 ;
wire \blk00000001/sig00000058 ;
wire \blk00000001/sig00000057 ;
wire \blk00000001/sig00000056 ;
wire \blk00000001/sig00000055 ;
wire \blk00000001/sig00000054 ;
wire \blk00000001/sig00000053 ;
wire \blk00000001/sig00000052 ;
wire \blk00000001/sig00000051 ;
wire \blk00000001/sig00000050 ;
wire \blk00000001/sig0000004f ;
wire \blk00000001/sig0000004e ;
wire \blk00000001/sig0000004d ;
wire \blk00000001/sig0000004c ;
wire \blk00000001/sig0000004b ;
wire \blk00000001/sig0000004a ;
wire \blk00000001/sig00000049 ;
wire \blk00000001/sig00000048 ;
wire \blk00000001/sig00000047 ;
wire \blk00000001/sig00000046 ;
wire \blk00000001/sig00000045 ;
wire \blk00000001/blk0000003b/sig000002f5 ;
wire \blk00000001/blk0000003b/sig000002f4 ;
wire \blk00000001/blk0000003b/sig000002f3 ;
wire \blk00000001/blk0000003b/sig000002f2 ;
wire \blk00000001/blk0000003b/sig000002f1 ;
wire \blk00000001/blk0000003b/sig000002f0 ;
wire \blk00000001/blk0000003b/sig000002ef ;
wire \blk00000001/blk0000003b/sig000002ee ;
wire \blk00000001/blk0000003b/sig000002ed ;
wire \blk00000001/blk0000003b/sig000002ec ;
wire \blk00000001/blk0000003b/sig000002eb ;
wire \blk00000001/blk0000003b/sig000002ea ;
wire \blk00000001/blk0000003b/sig000002e1 ;
wire \blk00000001/blk0000003f/sig00000313 ;
wire \blk00000001/blk0000003f/sig00000312 ;
wire \NLW_blk00000001/blk0000023b_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000239_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000237_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000235_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000233_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000231_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000022f_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000022d_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000022b_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000229_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000227_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000225_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000223_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000221_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000021f_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000021d_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000021b_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000219_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000217_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000215_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000213_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000211_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020f_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020d_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000020b_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000209_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000207_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000205_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000203_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000201_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001ff_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001fd_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001fb_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001f9_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001f7_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001f5_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001f3_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001f1_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001ef_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001ed_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001eb_Q31_UNCONNECTED ;
wire \NLW_blk00000001/blk000001e9_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001e7_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001e5_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001e3_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001e1_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001df_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001dd_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001db_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d9_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d7_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d5_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d3_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001d1_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001cf_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001cd_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001cb_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001c9_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001c7_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001c5_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001c3_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001c1_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001bf_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001bd_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001bb_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001b9_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001b7_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001b5_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001b3_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001b1_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001af_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001ad_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001ab_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001a9_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001a7_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001a5_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001a3_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000001a1_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000019f_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000019d_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000019b_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000199_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000197_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000195_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000193_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000191_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000018f_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000018d_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000018b_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000189_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000187_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000185_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000183_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000181_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000017f_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000017d_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000017b_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000179_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000177_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000175_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000173_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000171_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000016f_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000016d_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000016b_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000169_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000167_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000165_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000163_Q31_UNCONNECTED ;
wire \NLW_blk00000001/blk00000161_Q31_UNCONNECTED ;
wire \NLW_blk00000001/blk0000015f_Q31_UNCONNECTED ;
wire \NLW_blk00000001/blk0000015d_Q31_UNCONNECTED ;
wire \NLW_blk00000001/blk0000015b_Q31_UNCONNECTED ;
wire \NLW_blk00000001/blk00000159_Q31_UNCONNECTED ;
wire \NLW_blk00000001/blk00000157_Q31_UNCONNECTED ;
wire \NLW_blk00000001/blk00000155_Q31_UNCONNECTED ;
wire \NLW_blk00000001/blk00000153_Q31_UNCONNECTED ;
wire \NLW_blk00000001/blk00000151_Q31_UNCONNECTED ;
wire \NLW_blk00000001/blk0000014f_Q31_UNCONNECTED ;
wire \NLW_blk00000001/blk0000014d_Q31_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PATTERNBDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_MULTSIGNOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_CARRYCASCOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_UNDERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PATTERNDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_OVERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_P<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000d7_PCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PATTERNBDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_MULTSIGNOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_CARRYCASCOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_UNDERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PATTERNDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_OVERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_P<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000ce_PCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PATTERNBDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_MULTSIGNOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_CARRYCASCOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_UNDERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PATTERNDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_OVERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_P<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk000000a0_PCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PATTERNBDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_MULTSIGNOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_CARRYCASCOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_UNDERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PATTERNDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_OVERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_P<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000097_PCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PATTERNBDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_MULTSIGNOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_CARRYCASCOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_UNDERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PATTERNDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_OVERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_P<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000004c_PCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PATTERNBDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_MULTSIGNOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_CARRYCASCOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_UNDERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PATTERNDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_OVERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_P<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000043_PCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PATTERNBDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_MULTSIGNOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_MULTSIGNIN_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_CARRYCASCOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_UNDERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PATTERNDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_OVERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_CARRYCASCIN_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_P<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PATTERNBDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_MULTSIGNOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_MULTSIGNIN_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_CARRYCASCOUT_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_UNDERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PATTERNDETECT_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_OVERFLOW_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_CARRYCASCIN_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCIN<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCIN<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_P<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<22>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<21>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<20>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<19>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<18>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk0000003f/blk00000042_ACIN<0>_UNCONNECTED ;
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000023c (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002cb ),
.Q(\blk00000001/sig0000018a )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000023b (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000192 ),
.Q(\blk00000001/sig000002cb ),
.Q15(\NLW_blk00000001/blk0000023b_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000023a (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002ca ),
.Q(\blk00000001/sig0000018b )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000239 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000193 ),
.Q(\blk00000001/sig000002ca ),
.Q15(\NLW_blk00000001/blk00000239_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000238 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002c9 ),
.Q(\blk00000001/sig0000018c )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000237 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000194 ),
.Q(\blk00000001/sig000002c9 ),
.Q15(\NLW_blk00000001/blk00000237_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000236 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002c8 ),
.Q(\blk00000001/sig0000018d )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000235 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000195 ),
.Q(\blk00000001/sig000002c8 ),
.Q15(\NLW_blk00000001/blk00000235_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000234 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002c7 ),
.Q(\blk00000001/sig0000018e )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000233 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000196 ),
.Q(\blk00000001/sig000002c7 ),
.Q15(\NLW_blk00000001/blk00000233_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000232 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002c6 ),
.Q(\blk00000001/sig0000018f )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000231 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000197 ),
.Q(\blk00000001/sig000002c6 ),
.Q15(\NLW_blk00000001/blk00000231_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000230 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002c5 ),
.Q(\blk00000001/sig00000190 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000022f (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000198 ),
.Q(\blk00000001/sig000002c5 ),
.Q15(\NLW_blk00000001/blk0000022f_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000022e (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002c4 ),
.Q(\blk00000001/sig00000191 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000022d (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000199 ),
.Q(\blk00000001/sig000002c4 ),
.Q15(\NLW_blk00000001/blk0000022d_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000022c (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002c3 ),
.Q(\blk00000001/sig00000183 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000022b (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000001b9 ),
.Q(\blk00000001/sig000002c3 ),
.Q15(\NLW_blk00000001/blk0000022b_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000022a (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002c2 ),
.Q(\blk00000001/sig00000184 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000229 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000001ba ),
.Q(\blk00000001/sig000002c2 ),
.Q15(\NLW_blk00000001/blk00000229_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000228 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002c1 ),
.Q(\blk00000001/sig00000185 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000227 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000001bb ),
.Q(\blk00000001/sig000002c1 ),
.Q15(\NLW_blk00000001/blk00000227_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000226 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002c0 ),
.Q(\blk00000001/sig00000186 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000225 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000001bc ),
.Q(\blk00000001/sig000002c0 ),
.Q15(\NLW_blk00000001/blk00000225_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000224 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002bf ),
.Q(\blk00000001/sig00000187 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000223 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000001bd ),
.Q(\blk00000001/sig000002bf ),
.Q15(\NLW_blk00000001/blk00000223_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000222 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002be ),
.Q(\blk00000001/sig00000188 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000221 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000001be ),
.Q(\blk00000001/sig000002be ),
.Q15(\NLW_blk00000001/blk00000221_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000220 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002bd ),
.Q(\blk00000001/sig00000189 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000021f (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000001bf ),
.Q(\blk00000001/sig000002bd ),
.Q15(\NLW_blk00000001/blk0000021f_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000021e (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002bc ),
.Q(\blk00000001/sig00000192 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000021d (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000001c0 ),
.Q(\blk00000001/sig000002bc ),
.Q15(\NLW_blk00000001/blk0000021d_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000021c (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002bb ),
.Q(\blk00000001/sig00000193 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000021b (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000001c1 ),
.Q(\blk00000001/sig000002bb ),
.Q15(\NLW_blk00000001/blk0000021b_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000021a (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002ba ),
.Q(\blk00000001/sig00000194 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000219 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000001c2 ),
.Q(\blk00000001/sig000002ba ),
.Q15(\NLW_blk00000001/blk00000219_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000218 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002b9 ),
.Q(\blk00000001/sig00000195 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000217 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000001c3 ),
.Q(\blk00000001/sig000002b9 ),
.Q15(\NLW_blk00000001/blk00000217_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000216 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002b8 ),
.Q(\blk00000001/sig00000196 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000215 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000001c4 ),
.Q(\blk00000001/sig000002b8 ),
.Q15(\NLW_blk00000001/blk00000215_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000214 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002b7 ),
.Q(\blk00000001/sig00000197 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000213 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000001c5 ),
.Q(\blk00000001/sig000002b7 ),
.Q15(\NLW_blk00000001/blk00000213_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000212 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002b6 ),
.Q(\blk00000001/sig00000198 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000211 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000001c6 ),
.Q(\blk00000001/sig000002b6 ),
.Q15(\NLW_blk00000001/blk00000211_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000210 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002b5 ),
.Q(\blk00000001/sig00000199 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000020f (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000001c7 ),
.Q(\blk00000001/sig000002b5 ),
.Q15(\NLW_blk00000001/blk0000020f_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000020e (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002b4 ),
.Q(\blk00000001/sig0000012b )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000020d (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000de ),
.Q(\blk00000001/sig000002b4 ),
.Q15(\NLW_blk00000001/blk0000020d_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000020c (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002b3 ),
.Q(\blk00000001/sig0000012c )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000020b (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000df ),
.Q(\blk00000001/sig000002b3 ),
.Q15(\NLW_blk00000001/blk0000020b_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000020a (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002b2 ),
.Q(\blk00000001/sig0000012d )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000209 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000e0 ),
.Q(\blk00000001/sig000002b2 ),
.Q15(\NLW_blk00000001/blk00000209_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000208 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002b1 ),
.Q(\blk00000001/sig0000012e )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000207 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000e1 ),
.Q(\blk00000001/sig000002b1 ),
.Q15(\NLW_blk00000001/blk00000207_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000206 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002b0 ),
.Q(\blk00000001/sig0000012f )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000205 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000e2 ),
.Q(\blk00000001/sig000002b0 ),
.Q15(\NLW_blk00000001/blk00000205_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000204 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002af ),
.Q(\blk00000001/sig00000130 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000203 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000e3 ),
.Q(\blk00000001/sig000002af ),
.Q15(\NLW_blk00000001/blk00000203_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000202 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002ae ),
.Q(\blk00000001/sig00000131 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000201 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000e4 ),
.Q(\blk00000001/sig000002ae ),
.Q15(\NLW_blk00000001/blk00000201_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000200 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002ad ),
.Q(\blk00000001/sig000000c8 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001ff (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000010a ),
.Q(\blk00000001/sig000002ad ),
.Q15(\NLW_blk00000001/blk000001ff_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001fe (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002ac ),
.Q(\blk00000001/sig000000c9 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001fd (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000010b ),
.Q(\blk00000001/sig000002ac ),
.Q15(\NLW_blk00000001/blk000001fd_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001fc (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002ab ),
.Q(\blk00000001/sig000000ca )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001fb (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000010c ),
.Q(\blk00000001/sig000002ab ),
.Q15(\NLW_blk00000001/blk000001fb_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001fa (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002aa ),
.Q(\blk00000001/sig000000cb )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001f9 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000010d ),
.Q(\blk00000001/sig000002aa ),
.Q15(\NLW_blk00000001/blk000001f9_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001f8 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002a9 ),
.Q(\blk00000001/sig000000cc )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001f7 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000010e ),
.Q(\blk00000001/sig000002a9 ),
.Q15(\NLW_blk00000001/blk000001f7_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001f6 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002a8 ),
.Q(\blk00000001/sig000000ce )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001f5 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000110 ),
.Q(\blk00000001/sig000002a8 ),
.Q15(\NLW_blk00000001/blk000001f5_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001f4 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002a7 ),
.Q(\blk00000001/sig000000cf )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001f3 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000111 ),
.Q(\blk00000001/sig000002a7 ),
.Q15(\NLW_blk00000001/blk000001f3_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001f2 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002a6 ),
.Q(\blk00000001/sig000000cd )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001f1 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000010f ),
.Q(\blk00000001/sig000002a6 ),
.Q15(\NLW_blk00000001/blk000001f1_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001f0 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002a5 ),
.Q(\blk00000001/sig0000005c )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001ef (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000113 ),
.Q(\blk00000001/sig000002a5 ),
.Q15(\NLW_blk00000001/blk000001ef_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ee (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002a4 ),
.Q(\blk00000001/sig0000005d )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001ed (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000114 ),
.Q(\blk00000001/sig000002a4 ),
.Q15(\NLW_blk00000001/blk000001ed_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ec (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002a3 ),
.Q(m_axis_result_tvalid)
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk00000001/blk000001eb (
.CLK(aclk),
.D(\blk00000001/sig00000240 ),
.CE(aclken),
.Q(\blk00000001/sig000002a3 ),
.Q31(\NLW_blk00000001/blk000001eb_Q31_UNCONNECTED ),
.A({\blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ea (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002a2 ),
.Q(\blk00000001/sig0000005e )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001e9 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000115 ),
.Q(\blk00000001/sig000002a2 ),
.Q15(\NLW_blk00000001/blk000001e9_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001e8 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002a1 ),
.Q(\blk00000001/sig0000005f )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001e7 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000116 ),
.Q(\blk00000001/sig000002a1 ),
.Q15(\NLW_blk00000001/blk000001e7_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001e6 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000002a0 ),
.Q(\blk00000001/sig00000060 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001e5 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000117 ),
.Q(\blk00000001/sig000002a0 ),
.Q15(\NLW_blk00000001/blk000001e5_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001e4 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000029f ),
.Q(\blk00000001/sig00000061 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001e3 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000118 ),
.Q(\blk00000001/sig0000029f ),
.Q15(\NLW_blk00000001/blk000001e3_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001e2 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000029e ),
.Q(\blk00000001/sig00000062 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001e1 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000119 ),
.Q(\blk00000001/sig0000029e ),
.Q15(\NLW_blk00000001/blk000001e1_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001e0 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000029d ),
.Q(\blk00000001/sig00000063 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001df (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000011a ),
.Q(\blk00000001/sig0000029d ),
.Q15(\NLW_blk00000001/blk000001df_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001de (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000029c ),
.Q(\blk00000001/sig0000017c )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001dd (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000007a ),
.Q(\blk00000001/sig0000029c ),
.Q15(\NLW_blk00000001/blk000001dd_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001dc (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000029b ),
.Q(\blk00000001/sig0000017d )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001db (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000007b ),
.Q(\blk00000001/sig0000029b ),
.Q15(\NLW_blk00000001/blk000001db_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001da (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000029a ),
.Q(\blk00000001/sig0000017e )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001d9 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000007c ),
.Q(\blk00000001/sig0000029a ),
.Q15(\NLW_blk00000001/blk000001d9_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001d8 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000299 ),
.Q(\blk00000001/sig0000017f )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001d7 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000007d ),
.Q(\blk00000001/sig00000299 ),
.Q15(\NLW_blk00000001/blk000001d7_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001d6 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000298 ),
.Q(\blk00000001/sig00000180 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001d5 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000007e ),
.Q(\blk00000001/sig00000298 ),
.Q15(\NLW_blk00000001/blk000001d5_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001d4 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000297 ),
.Q(\blk00000001/sig00000181 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001d3 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000007f ),
.Q(\blk00000001/sig00000297 ),
.Q15(\NLW_blk00000001/blk000001d3_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001d2 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000296 ),
.Q(\blk00000001/sig00000182 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001d1 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig00000132 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000080 ),
.Q(\blk00000001/sig00000296 ),
.Q15(\NLW_blk00000001/blk000001d1_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001d0 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000295 ),
.Q(\blk00000001/sig000001b9 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001cf (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000081 ),
.Q(\blk00000001/sig00000295 ),
.Q15(\NLW_blk00000001/blk000001cf_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ce (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000294 ),
.Q(\blk00000001/sig000001ba )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001cd (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000082 ),
.Q(\blk00000001/sig00000294 ),
.Q15(\NLW_blk00000001/blk000001cd_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001cc (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000293 ),
.Q(\blk00000001/sig000001bb )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001cb (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000083 ),
.Q(\blk00000001/sig00000293 ),
.Q15(\NLW_blk00000001/blk000001cb_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ca (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000292 ),
.Q(\blk00000001/sig000001bc )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001c9 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000084 ),
.Q(\blk00000001/sig00000292 ),
.Q15(\NLW_blk00000001/blk000001c9_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001c8 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000291 ),
.Q(\blk00000001/sig000001bd )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001c7 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000085 ),
.Q(\blk00000001/sig00000291 ),
.Q15(\NLW_blk00000001/blk000001c7_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001c6 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000290 ),
.Q(\blk00000001/sig000001be )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001c5 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000086 ),
.Q(\blk00000001/sig00000290 ),
.Q15(\NLW_blk00000001/blk000001c5_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001c4 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000028f ),
.Q(\blk00000001/sig000001c7 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001c3 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000008f ),
.Q(\blk00000001/sig0000028f ),
.Q15(\NLW_blk00000001/blk000001c3_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001c2 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000028e ),
.Q(\blk00000001/sig000001c6 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001c1 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000008e ),
.Q(\blk00000001/sig0000028e ),
.Q15(\NLW_blk00000001/blk000001c1_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001c0 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000028d ),
.Q(\blk00000001/sig000001bf )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001bf (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000087 ),
.Q(\blk00000001/sig0000028d ),
.Q15(\NLW_blk00000001/blk000001bf_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001be (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000028c ),
.Q(\blk00000001/sig000001c5 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001bd (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000008d ),
.Q(\blk00000001/sig0000028c ),
.Q15(\NLW_blk00000001/blk000001bd_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001bc (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000028b ),
.Q(\blk00000001/sig000001c4 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001bb (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000008c ),
.Q(\blk00000001/sig0000028b ),
.Q15(\NLW_blk00000001/blk000001bb_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ba (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000028a ),
.Q(\blk00000001/sig000001c3 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001b9 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000008b ),
.Q(\blk00000001/sig0000028a ),
.Q15(\NLW_blk00000001/blk000001b9_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001b8 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000289 ),
.Q(\blk00000001/sig000001c2 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001b7 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000008a ),
.Q(\blk00000001/sig00000289 ),
.Q15(\NLW_blk00000001/blk000001b7_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001b6 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000288 ),
.Q(\blk00000001/sig000001c1 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001b5 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000089 ),
.Q(\blk00000001/sig00000288 ),
.Q15(\NLW_blk00000001/blk000001b5_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001b4 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000287 ),
.Q(\blk00000001/sig000001c0 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001b3 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000088 ),
.Q(\blk00000001/sig00000287 ),
.Q15(\NLW_blk00000001/blk000001b3_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001b2 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000286 ),
.Q(\blk00000001/sig000001a1 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001b1 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000133 ),
.Q(\blk00000001/sig00000286 ),
.Q15(\NLW_blk00000001/blk000001b1_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001b0 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000285 ),
.Q(\blk00000001/sig000001a0 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001af (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000134 ),
.Q(\blk00000001/sig00000285 ),
.Q15(\NLW_blk00000001/blk000001af_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ae (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000284 ),
.Q(\blk00000001/sig0000019f )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001ad (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000135 ),
.Q(\blk00000001/sig00000284 ),
.Q15(\NLW_blk00000001/blk000001ad_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001ac (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000283 ),
.Q(\blk00000001/sig0000019e )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001ab (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000136 ),
.Q(\blk00000001/sig00000283 ),
.Q15(\NLW_blk00000001/blk000001ab_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001aa (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000282 ),
.Q(\blk00000001/sig0000019d )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001a9 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000137 ),
.Q(\blk00000001/sig00000282 ),
.Q15(\NLW_blk00000001/blk000001a9_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001a8 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000281 ),
.Q(\blk00000001/sig0000019c )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001a7 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000138 ),
.Q(\blk00000001/sig00000281 ),
.Q15(\NLW_blk00000001/blk000001a7_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001a6 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000280 ),
.Q(\blk00000001/sig0000019a )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001a5 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig0000013a ),
.Q(\blk00000001/sig00000280 ),
.Q15(\NLW_blk00000001/blk000001a5_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001a4 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000027f ),
.Q(\blk00000001/sig0000011b )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001a3 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[0]),
.Q(\blk00000001/sig0000027f ),
.Q15(\NLW_blk00000001/blk000001a3_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001a2 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000027e ),
.Q(\blk00000001/sig0000019b )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000001a1 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig00000139 ),
.Q(\blk00000001/sig0000027e ),
.Q15(\NLW_blk00000001/blk000001a1_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000001a0 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000027d ),
.Q(\blk00000001/sig0000011c )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000019f (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[1]),
.Q(\blk00000001/sig0000027d ),
.Q15(\NLW_blk00000001/blk0000019f_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000019e (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000027c ),
.Q(\blk00000001/sig0000011d )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000019d (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[2]),
.Q(\blk00000001/sig0000027c ),
.Q15(\NLW_blk00000001/blk0000019d_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000019c (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000027b ),
.Q(\blk00000001/sig0000011e )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000019b (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[3]),
.Q(\blk00000001/sig0000027b ),
.Q15(\NLW_blk00000001/blk0000019b_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000019a (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000027a ),
.Q(\blk00000001/sig0000011f )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000199 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[4]),
.Q(\blk00000001/sig0000027a ),
.Q15(\NLW_blk00000001/blk00000199_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000198 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000279 ),
.Q(\blk00000001/sig00000120 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000197 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[5]),
.Q(\blk00000001/sig00000279 ),
.Q15(\NLW_blk00000001/blk00000197_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000196 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000278 ),
.Q(\blk00000001/sig00000121 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000195 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[6]),
.Q(\blk00000001/sig00000278 ),
.Q15(\NLW_blk00000001/blk00000195_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000194 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000277 ),
.Q(\blk00000001/sig00000122 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000193 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[7]),
.Q(\blk00000001/sig00000277 ),
.Q15(\NLW_blk00000001/blk00000193_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000192 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000276 ),
.Q(\blk00000001/sig00000123 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000191 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[8]),
.Q(\blk00000001/sig00000276 ),
.Q15(\NLW_blk00000001/blk00000191_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000190 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000275 ),
.Q(\blk00000001/sig00000124 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000018f (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[9]),
.Q(\blk00000001/sig00000275 ),
.Q15(\NLW_blk00000001/blk0000018f_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000018e (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000274 ),
.Q(\blk00000001/sig00000125 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000018d (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[10]),
.Q(\blk00000001/sig00000274 ),
.Q15(\NLW_blk00000001/blk0000018d_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000018c (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000273 ),
.Q(\blk00000001/sig00000126 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000018b (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[11]),
.Q(\blk00000001/sig00000273 ),
.Q15(\NLW_blk00000001/blk0000018b_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000018a (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000272 ),
.Q(\blk00000001/sig00000127 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000189 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[12]),
.Q(\blk00000001/sig00000272 ),
.Q15(\NLW_blk00000001/blk00000189_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000188 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000271 ),
.Q(\blk00000001/sig00000129 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000187 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[14]),
.Q(\blk00000001/sig00000271 ),
.Q15(\NLW_blk00000001/blk00000187_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000186 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000270 ),
.Q(\blk00000001/sig0000012a )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000185 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[15]),
.Q(\blk00000001/sig00000270 ),
.Q15(\NLW_blk00000001/blk00000185_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000184 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000026f ),
.Q(\blk00000001/sig00000128 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000183 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig00000132 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[13]),
.Q(\blk00000001/sig0000026f ),
.Q15(\NLW_blk00000001/blk00000183_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000182 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000026e ),
.Q(\blk00000001/sig0000010a )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000181 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000e5 ),
.Q(\blk00000001/sig0000026e ),
.Q15(\NLW_blk00000001/blk00000181_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000180 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000026d ),
.Q(\blk00000001/sig0000010b )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000017f (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000e6 ),
.Q(\blk00000001/sig0000026d ),
.Q15(\NLW_blk00000001/blk0000017f_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000017e (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000026c ),
.Q(\blk00000001/sig0000010c )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000017d (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000e7 ),
.Q(\blk00000001/sig0000026c ),
.Q15(\NLW_blk00000001/blk0000017d_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000017c (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000026b ),
.Q(\blk00000001/sig0000010d )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000017b (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000e8 ),
.Q(\blk00000001/sig0000026b ),
.Q15(\NLW_blk00000001/blk0000017b_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000017a (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000026a ),
.Q(\blk00000001/sig0000010e )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000179 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000e9 ),
.Q(\blk00000001/sig0000026a ),
.Q15(\NLW_blk00000001/blk00000179_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000178 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000269 ),
.Q(\blk00000001/sig0000010f )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000177 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000ea ),
.Q(\blk00000001/sig00000269 ),
.Q15(\NLW_blk00000001/blk00000177_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000176 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000268 ),
.Q(\blk00000001/sig00000110 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000175 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000eb ),
.Q(\blk00000001/sig00000268 ),
.Q15(\NLW_blk00000001/blk00000175_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000174 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000267 ),
.Q(\blk00000001/sig00000111 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000173 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000ec ),
.Q(\blk00000001/sig00000267 ),
.Q15(\NLW_blk00000001/blk00000173_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000172 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000266 ),
.Q(\blk00000001/sig000000de )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000171 (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[16]),
.Q(\blk00000001/sig00000266 ),
.Q15(\NLW_blk00000001/blk00000171_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000170 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000265 ),
.Q(\blk00000001/sig000000df )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000016f (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[17]),
.Q(\blk00000001/sig00000265 ),
.Q15(\NLW_blk00000001/blk0000016f_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000016e (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000264 ),
.Q(\blk00000001/sig000000e0 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000016d (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[18]),
.Q(\blk00000001/sig00000264 ),
.Q15(\NLW_blk00000001/blk0000016d_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000016c (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000263 ),
.Q(\blk00000001/sig000000e1 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000016b (
.A0(\blk00000001/sig000001d8 ),
.A1(\blk00000001/sig00000132 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(s_axis_a_tdata[19]),
.Q(\blk00000001/sig00000263 ),
.Q15(\NLW_blk00000001/blk0000016b_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000016a (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000262 ),
.Q(\blk00000001/sig000000e3 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000169 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000fb ),
.Q(\blk00000001/sig00000262 ),
.Q15(\NLW_blk00000001/blk00000169_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000168 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000261 ),
.Q(\blk00000001/sig000000e4 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000167 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000fc ),
.Q(\blk00000001/sig00000261 ),
.Q15(\NLW_blk00000001/blk00000167_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000166 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000260 ),
.Q(\blk00000001/sig000000e2 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000165 (
.A0(\blk00000001/sig00000132 ),
.A1(\blk00000001/sig000001d8 ),
.A2(\blk00000001/sig000001d8 ),
.A3(\blk00000001/sig000001d8 ),
.CE(aclken),
.CLK(aclk),
.D(\blk00000001/sig000000fa ),
.Q(\blk00000001/sig00000260 ),
.Q15(\NLW_blk00000001/blk00000165_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000164 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000025f ),
.Q(\blk00000001/sig00000091 )
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk00000001/blk00000163 (
.CLK(aclk),
.D(\blk00000001/sig000000ae ),
.CE(aclken),
.Q(\blk00000001/sig0000025f ),
.Q31(\NLW_blk00000001/blk00000163_Q31_UNCONNECTED ),
.A({\blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000162 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000025e ),
.Q(\blk00000001/sig0000009b )
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk00000001/blk00000161 (
.CLK(aclk),
.D(s_axis_a_tdata[31]),
.CE(aclken),
.Q(\blk00000001/sig0000025e ),
.Q31(\NLW_blk00000001/blk00000161_Q31_UNCONNECTED ),
.A({\blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000160 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000025d ),
.Q(\blk00000001/sig0000009c )
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk00000001/blk0000015f (
.CLK(aclk),
.D(s_axis_a_tdata[23]),
.CE(aclken),
.Q(\blk00000001/sig0000025d ),
.Q31(\NLW_blk00000001/blk0000015f_Q31_UNCONNECTED ),
.A({\blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015e (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000025c ),
.Q(\blk00000001/sig0000009d )
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk00000001/blk0000015d (
.CLK(aclk),
.D(s_axis_a_tdata[24]),
.CE(aclken),
.Q(\blk00000001/sig0000025c ),
.Q31(\NLW_blk00000001/blk0000015d_Q31_UNCONNECTED ),
.A({\blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015c (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000025b ),
.Q(\blk00000001/sig0000009e )
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk00000001/blk0000015b (
.CLK(aclk),
.D(s_axis_a_tdata[25]),
.CE(aclken),
.Q(\blk00000001/sig0000025b ),
.Q31(\NLW_blk00000001/blk0000015b_Q31_UNCONNECTED ),
.A({\blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000015a (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000025a ),
.Q(\blk00000001/sig0000009f )
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk00000001/blk00000159 (
.CLK(aclk),
.D(s_axis_a_tdata[26]),
.CE(aclken),
.Q(\blk00000001/sig0000025a ),
.Q31(\NLW_blk00000001/blk00000159_Q31_UNCONNECTED ),
.A({\blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000158 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000259 ),
.Q(\blk00000001/sig000000a0 )
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk00000001/blk00000157 (
.CLK(aclk),
.D(s_axis_a_tdata[27]),
.CE(aclken),
.Q(\blk00000001/sig00000259 ),
.Q31(\NLW_blk00000001/blk00000157_Q31_UNCONNECTED ),
.A({\blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000156 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000258 ),
.Q(\blk00000001/sig000000a1 )
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk00000001/blk00000155 (
.CLK(aclk),
.D(s_axis_a_tdata[28]),
.CE(aclken),
.Q(\blk00000001/sig00000258 ),
.Q31(\NLW_blk00000001/blk00000155_Q31_UNCONNECTED ),
.A({\blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000154 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000257 ),
.Q(\blk00000001/sig000000a2 )
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk00000001/blk00000153 (
.CLK(aclk),
.D(s_axis_a_tdata[29]),
.CE(aclken),
.Q(\blk00000001/sig00000257 ),
.Q31(\NLW_blk00000001/blk00000153_Q31_UNCONNECTED ),
.A({\blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000152 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000256 ),
.Q(\blk00000001/sig000000a3 )
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk00000001/blk00000151 (
.CLK(aclk),
.D(s_axis_a_tdata[30]),
.CE(aclken),
.Q(\blk00000001/sig00000256 ),
.Q31(\NLW_blk00000001/blk00000151_Q31_UNCONNECTED ),
.A({\blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000150 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000255 ),
.Q(\blk00000001/sig000000a4 )
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk00000001/blk0000014f (
.CLK(aclk),
.D(\blk00000001/sig000000b0 ),
.CE(aclken),
.Q(\blk00000001/sig00000255 ),
.Q31(\NLW_blk00000001/blk0000014f_Q31_UNCONNECTED ),
.A({\blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig00000132 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000014e (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000254 ),
.Q(\blk00000001/sig000000a5 )
);
SRLC32E #(
.INIT ( 32'h00000000 ))
\blk00000001/blk0000014d (
.CLK(aclk),
.D(\blk00000001/sig000000af ),
.CE(aclken),
.Q(\blk00000001/sig00000254 ),
.Q31(\NLW_blk00000001/blk0000014d_Q31_UNCONNECTED ),
.A({\blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig00000132 })
);
INV \blk00000001/blk0000014c (
.I(s_axis_a_tdata[19]),
.O(\blk00000001/sig000000f9 )
);
INV \blk00000001/blk0000014b (
.I(s_axis_a_tdata[18]),
.O(\blk00000001/sig000000f8 )
);
INV \blk00000001/blk0000014a (
.I(s_axis_a_tdata[17]),
.O(\blk00000001/sig000000f7 )
);
INV \blk00000001/blk00000149 (
.I(s_axis_a_tdata[16]),
.O(\blk00000001/sig000000f6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000148 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000a5 ),
.Q(\blk00000001/sig00000253 )
);
LUT6 #(
.INIT ( 64'h55555555BABAABBA ))
\blk00000001/blk00000147 (
.I0(\blk00000001/sig00000091 ),
.I1(\blk00000001/sig00000236 ),
.I2(\blk00000001/sig00000094 ),
.I3(\blk00000001/sig00000090 ),
.I4(\blk00000001/sig00000093 ),
.I5(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000215 )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000146 (
.I0(\blk00000001/sig0000005a ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000233 )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000145 (
.I0(\blk00000001/sig00000057 ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000230 )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000144 (
.I0(\blk00000001/sig00000059 ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000232 )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000143 (
.I0(\blk00000001/sig00000058 ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000231 )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000142 (
.I0(\blk00000001/sig00000054 ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig0000022d )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000141 (
.I0(\blk00000001/sig00000056 ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig0000022f )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000140 (
.I0(\blk00000001/sig00000055 ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig0000022e )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk0000013f (
.I0(\blk00000001/sig00000053 ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig0000022c )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk0000013e (
.I0(\blk00000001/sig00000052 ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig0000022b )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk0000013d (
.I0(\blk00000001/sig0000004f ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000228 )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk0000013c (
.I0(\blk00000001/sig00000051 ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig0000022a )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk0000013b (
.I0(\blk00000001/sig00000050 ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000229 )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk0000013a (
.I0(\blk00000001/sig0000004c ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000225 )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000139 (
.I0(\blk00000001/sig0000004e ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000227 )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000138 (
.I0(\blk00000001/sig0000004d ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000226 )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000137 (
.I0(\blk00000001/sig00000049 ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000222 )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000136 (
.I0(\blk00000001/sig0000004b ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000224 )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000135 (
.I0(\blk00000001/sig0000004a ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000223 )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000134 (
.I0(\blk00000001/sig00000048 ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000221 )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000133 (
.I0(\blk00000001/sig00000047 ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000220 )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000132 (
.I0(\blk00000001/sig00000046 ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig0000021f )
);
LUT4 #(
.INIT ( 16'h0002 ))
\blk00000001/blk00000131 (
.I0(\blk00000001/sig00000045 ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig0000021e )
);
LUT5 #(
.INIT ( 32'h5555BAAB ))
\blk00000001/blk00000130 (
.I0(\blk00000001/sig00000091 ),
.I1(\blk00000001/sig00000236 ),
.I2(\blk00000001/sig00000090 ),
.I3(\blk00000001/sig00000093 ),
.I4(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000214 )
);
LUT6 #(
.INIT ( 64'hFF0000FAFF0000F6 ))
\blk00000001/blk0000012f (
.I0(\blk00000001/sig0000009a ),
.I1(\blk00000001/sig00000097 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000091 ),
.I4(\blk00000001/sig00000092 ),
.I5(\blk00000001/sig00000252 ),
.O(\blk00000001/sig0000024f )
);
LUT6 #(
.INIT ( 64'h7FFFFF7FFFFFFFFF ))
\blk00000001/blk0000012e (
.I0(\blk00000001/sig00000096 ),
.I1(\blk00000001/sig00000095 ),
.I2(\blk00000001/sig00000099 ),
.I3(\blk00000001/sig00000093 ),
.I4(\blk00000001/sig00000090 ),
.I5(\blk00000001/sig00000098 ),
.O(\blk00000001/sig00000252 )
);
LUT6 #(
.INIT ( 64'hFF0000FCFF0000F6 ))
\blk00000001/blk0000012d (
.I0(\blk00000001/sig00000097 ),
.I1(\blk00000001/sig00000099 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000091 ),
.I4(\blk00000001/sig00000092 ),
.I5(\blk00000001/sig00000251 ),
.O(\blk00000001/sig0000024c )
);
LUT5 #(
.INIT ( 32'h7FF7FFFF ))
\blk00000001/blk0000012c (
.I0(\blk00000001/sig00000096 ),
.I1(\blk00000001/sig00000095 ),
.I2(\blk00000001/sig00000093 ),
.I3(\blk00000001/sig00000090 ),
.I4(\blk00000001/sig00000098 ),
.O(\blk00000001/sig00000251 )
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFFFFFF75 ))
\blk00000001/blk0000012b (
.I0(\blk00000001/sig00000094 ),
.I1(\blk00000001/sig00000093 ),
.I2(\blk00000001/sig00000090 ),
.I3(\blk00000001/sig00000236 ),
.I4(\blk00000001/sig00000092 ),
.I5(\blk00000001/sig00000091 ),
.O(\blk00000001/sig00000211 )
);
LUT6 #(
.INIT ( 64'h44507750445F775F ))
\blk00000001/blk0000012a (
.I0(\blk00000001/sig00000250 ),
.I1(\blk00000001/sig0000021c ),
.I2(\blk00000001/sig0000021d ),
.I3(\blk00000001/sig00000212 ),
.I4(\blk00000001/sig0000024f ),
.I5(\blk00000001/sig0000024e ),
.O(\blk00000001/sig0000021b )
);
LUT4 #(
.INIT ( 16'hF00E ))
\blk00000001/blk00000129 (
.I0(\blk00000001/sig0000009a ),
.I1(\blk00000001/sig00000236 ),
.I2(\blk00000001/sig00000091 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000250 )
);
LUT6 #(
.INIT ( 64'hF00EF00E00020001 ))
\blk00000001/blk00000128 (
.I0(\blk00000001/sig0000009a ),
.I1(\blk00000001/sig00000236 ),
.I2(\blk00000001/sig00000091 ),
.I3(\blk00000001/sig00000092 ),
.I4(\blk00000001/sig00000248 ),
.I5(\blk00000001/sig00000249 ),
.O(\blk00000001/sig0000024e )
);
LUT6 #(
.INIT ( 64'h44507750445F775F ))
\blk00000001/blk00000127 (
.I0(\blk00000001/sig0000024d ),
.I1(\blk00000001/sig0000021c ),
.I2(\blk00000001/sig0000021d ),
.I3(\blk00000001/sig00000212 ),
.I4(\blk00000001/sig0000024c ),
.I5(\blk00000001/sig0000024b ),
.O(\blk00000001/sig0000021a )
);
LUT4 #(
.INIT ( 16'hF00E ))
\blk00000001/blk00000126 (
.I0(\blk00000001/sig00000099 ),
.I1(\blk00000001/sig00000236 ),
.I2(\blk00000001/sig00000091 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig0000024d )
);
LUT6 #(
.INIT ( 64'hFF0000FC00000006 ))
\blk00000001/blk00000125 (
.I0(\blk00000001/sig00000098 ),
.I1(\blk00000001/sig00000099 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000091 ),
.I4(\blk00000001/sig00000092 ),
.I5(\blk00000001/sig00000249 ),
.O(\blk00000001/sig0000024b )
);
LUT6 #(
.INIT ( 64'hCCCCCC99C9C9C9C9 ))
\blk00000001/blk00000124 (
.I0(\blk00000001/sig00000249 ),
.I1(\blk00000001/sig0000024a ),
.I2(\blk00000001/sig0000021d ),
.I3(\blk00000001/sig0000021c ),
.I4(\blk00000001/sig00000213 ),
.I5(\blk00000001/sig00000212 ),
.O(\blk00000001/sig00000219 )
);
LUT4 #(
.INIT ( 16'h0FF1 ))
\blk00000001/blk00000123 (
.I0(\blk00000001/sig00000098 ),
.I1(\blk00000001/sig00000236 ),
.I2(\blk00000001/sig00000091 ),
.I3(\blk00000001/sig00000092 ),
.O(\blk00000001/sig0000024a )
);
LUT6 #(
.INIT ( 64'h00FF00FFFF00FF7F ))
\blk00000001/blk00000122 (
.I0(\blk00000001/sig00000097 ),
.I1(\blk00000001/sig00000096 ),
.I2(\blk00000001/sig00000095 ),
.I3(\blk00000001/sig00000253 ),
.I4(\blk00000001/sig00000236 ),
.I5(\blk00000001/sig00000091 ),
.O(\blk00000001/sig00000249 )
);
LUT5 #(
.INIT ( 32'hFF0000F6 ))
\blk00000001/blk00000121 (
.I0(\blk00000001/sig00000090 ),
.I1(\blk00000001/sig00000093 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000091 ),
.I4(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000213 )
);
LUT5 #(
.INIT ( 32'hFF0000F9 ))
\blk00000001/blk00000120 (
.I0(\blk00000001/sig00000094 ),
.I1(\blk00000001/sig00000090 ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000091 ),
.I4(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000212 )
);
LUT2 #(
.INIT ( 4'h7 ))
\blk00000001/blk0000011f (
.I0(\blk00000001/sig00000099 ),
.I1(\blk00000001/sig00000098 ),
.O(\blk00000001/sig00000248 )
);
LUT6 #(
.INIT ( 64'h3C3D3C3DFFFDFFFE ))
\blk00000001/blk0000011e (
.I0(\blk00000001/sig00000097 ),
.I1(\blk00000001/sig00000092 ),
.I2(\blk00000001/sig00000091 ),
.I3(\blk00000001/sig00000236 ),
.I4(\blk00000001/sig00000247 ),
.I5(\blk00000001/sig00000211 ),
.O(\blk00000001/sig00000218 )
);
LUT2 #(
.INIT ( 4'h7 ))
\blk00000001/blk0000011d (
.I0(\blk00000001/sig00000096 ),
.I1(\blk00000001/sig00000095 ),
.O(\blk00000001/sig00000247 )
);
LUT6 #(
.INIT ( 64'h8000000000000000 ))
\blk00000001/blk0000011c (
.I0(s_axis_a_tdata[30]),
.I1(s_axis_a_tdata[29]),
.I2(s_axis_a_tdata[28]),
.I3(s_axis_a_tdata[27]),
.I4(s_axis_a_tdata[26]),
.I5(\blk00000001/sig00000246 ),
.O(\blk00000001/sig000000ad )
);
LUT3 #(
.INIT ( 8'h80 ))
\blk00000001/blk0000011b (
.I0(s_axis_a_tdata[25]),
.I1(s_axis_a_tdata[24]),
.I2(s_axis_a_tdata[23]),
.O(\blk00000001/sig00000246 )
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
\blk00000001/blk0000011a (
.I0(s_axis_a_tdata[30]),
.I1(s_axis_a_tdata[29]),
.I2(s_axis_a_tdata[28]),
.I3(s_axis_a_tdata[27]),
.I4(s_axis_a_tdata[26]),
.I5(\blk00000001/sig00000245 ),
.O(\blk00000001/sig000000ac )
);
LUT3 #(
.INIT ( 8'hFE ))
\blk00000001/blk00000119 (
.I0(s_axis_a_tdata[25]),
.I1(s_axis_a_tdata[24]),
.I2(s_axis_a_tdata[23]),
.O(\blk00000001/sig00000245 )
);
LUT4 #(
.INIT ( 16'h8000 ))
\blk00000001/blk00000118 (
.I0(\blk00000001/sig00000241 ),
.I1(\blk00000001/sig00000242 ),
.I2(\blk00000001/sig00000243 ),
.I3(\blk00000001/sig00000244 ),
.O(\blk00000001/sig000000ab )
);
LUT5 #(
.INIT ( 32'h00000001 ))
\blk00000001/blk00000117 (
.I0(s_axis_a_tdata[19]),
.I1(s_axis_a_tdata[18]),
.I2(s_axis_a_tdata[20]),
.I3(s_axis_a_tdata[21]),
.I4(s_axis_a_tdata[22]),
.O(\blk00000001/sig00000244 )
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
\blk00000001/blk00000116 (
.I0(s_axis_a_tdata[13]),
.I1(s_axis_a_tdata[12]),
.I2(s_axis_a_tdata[14]),
.I3(s_axis_a_tdata[15]),
.I4(s_axis_a_tdata[16]),
.I5(s_axis_a_tdata[17]),
.O(\blk00000001/sig00000243 )
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
\blk00000001/blk00000115 (
.I0(s_axis_a_tdata[7]),
.I1(s_axis_a_tdata[6]),
.I2(s_axis_a_tdata[8]),
.I3(s_axis_a_tdata[9]),
.I4(s_axis_a_tdata[10]),
.I5(s_axis_a_tdata[11]),
.O(\blk00000001/sig00000242 )
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
\blk00000001/blk00000114 (
.I0(s_axis_a_tdata[1]),
.I1(s_axis_a_tdata[0]),
.I2(s_axis_a_tdata[2]),
.I3(s_axis_a_tdata[3]),
.I4(s_axis_a_tdata[4]),
.I5(s_axis_a_tdata[5]),
.O(\blk00000001/sig00000241 )
);
LUT3 #(
.INIT ( 8'hF2 ))
\blk00000001/blk00000113 (
.I0(\blk00000001/sig0000009c ),
.I1(\blk00000001/sig000000a4 ),
.I2(\blk00000001/sig0000009d ),
.O(\blk00000001/sig0000023a )
);
LUT3 #(
.INIT ( 8'h41 ))
\blk00000001/blk00000112 (
.I0(\blk00000001/sig0000009d ),
.I1(\blk00000001/sig0000009c ),
.I2(\blk00000001/sig000000a4 ),
.O(\blk00000001/sig0000023b )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk00000111 (
.I0(\blk00000001/sig0000009f ),
.I1(\blk00000001/sig0000009e ),
.O(\blk00000001/sig00000239 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk00000110 (
.I0(\blk00000001/sig000000a1 ),
.I1(\blk00000001/sig000000a0 ),
.O(\blk00000001/sig00000238 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk0000010f (
.I0(\blk00000001/sig000000a3 ),
.I1(\blk00000001/sig000000a2 ),
.O(\blk00000001/sig00000237 )
);
LUT4 #(
.INIT ( 16'h5504 ))
\blk00000001/blk0000010e (
.I0(\blk00000001/sig00000092 ),
.I1(\blk00000001/sig0000005b ),
.I2(\blk00000001/sig00000236 ),
.I3(\blk00000001/sig00000091 ),
.O(\blk00000001/sig00000234 )
);
LUT4 #(
.INIT ( 16'h0FF1 ))
\blk00000001/blk0000010d (
.I0(\blk00000001/sig00000093 ),
.I1(\blk00000001/sig00000236 ),
.I2(\blk00000001/sig00000092 ),
.I3(\blk00000001/sig00000091 ),
.O(\blk00000001/sig0000021c )
);
LUT4 #(
.INIT ( 16'h0FF1 ))
\blk00000001/blk0000010c (
.I0(\blk00000001/sig00000094 ),
.I1(\blk00000001/sig00000236 ),
.I2(\blk00000001/sig00000092 ),
.I3(\blk00000001/sig00000091 ),
.O(\blk00000001/sig0000021d )
);
LUT3 #(
.INIT ( 8'hA2 ))
\blk00000001/blk0000010b (
.I0(\blk00000001/sig0000009b ),
.I1(\blk00000001/sig00000091 ),
.I2(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000235 )
);
LUT6 #(
.INIT ( 64'h0F0FF0F5FFFFFFF9 ))
\blk00000001/blk0000010a (
.I0(\blk00000001/sig00000096 ),
.I1(\blk00000001/sig00000095 ),
.I2(\blk00000001/sig00000092 ),
.I3(\blk00000001/sig00000236 ),
.I4(\blk00000001/sig00000091 ),
.I5(\blk00000001/sig00000211 ),
.O(\blk00000001/sig00000217 )
);
LUT5 #(
.INIT ( 32'h0FF1F00E ))
\blk00000001/blk00000109 (
.I0(\blk00000001/sig00000095 ),
.I1(\blk00000001/sig00000236 ),
.I2(\blk00000001/sig00000092 ),
.I3(\blk00000001/sig00000091 ),
.I4(\blk00000001/sig00000211 ),
.O(\blk00000001/sig00000216 )
);
LUT3 #(
.INIT ( 8'hF2 ))
\blk00000001/blk00000108 (
.I0(s_axis_a_tdata[20]),
.I1(s_axis_a_tdata[22]),
.I2(s_axis_a_tdata[21]),
.O(\blk00000001/sig000000f2 )
);
LUT3 #(
.INIT ( 8'h4E ))
\blk00000001/blk00000107 (
.I0(s_axis_a_tdata[21]),
.I1(s_axis_a_tdata[20]),
.I2(s_axis_a_tdata[22]),
.O(\blk00000001/sig000000f0 )
);
LUT3 #(
.INIT ( 8'h1B ))
\blk00000001/blk00000106 (
.I0(s_axis_a_tdata[20]),
.I1(s_axis_a_tdata[21]),
.I2(s_axis_a_tdata[22]),
.O(\blk00000001/sig000000ef )
);
LUT3 #(
.INIT ( 8'hF9 ))
\blk00000001/blk00000105 (
.I0(s_axis_a_tdata[20]),
.I1(s_axis_a_tdata[21]),
.I2(s_axis_a_tdata[22]),
.O(\blk00000001/sig000000ee )
);
LUT3 #(
.INIT ( 8'h6A ))
\blk00000001/blk00000104 (
.I0(s_axis_a_tdata[22]),
.I1(s_axis_a_tdata[20]),
.I2(s_axis_a_tdata[21]),
.O(\blk00000001/sig000000f1 )
);
LUT3 #(
.INIT ( 8'h15 ))
\blk00000001/blk00000103 (
.I0(s_axis_a_tdata[22]),
.I1(s_axis_a_tdata[20]),
.I2(s_axis_a_tdata[21]),
.O(\blk00000001/sig000000ed )
);
LUT3 #(
.INIT ( 8'h15 ))
\blk00000001/blk00000102 (
.I0(s_axis_a_tdata[21]),
.I1(s_axis_a_tdata[20]),
.I2(s_axis_a_tdata[22]),
.O(\blk00000001/sig000000f4 )
);
LUT3 #(
.INIT ( 8'h14 ))
\blk00000001/blk00000101 (
.I0(s_axis_a_tdata[22]),
.I1(s_axis_a_tdata[20]),
.I2(s_axis_a_tdata[21]),
.O(\blk00000001/sig000000f5 )
);
LUT3 #(
.INIT ( 8'h29 ))
\blk00000001/blk00000100 (
.I0(s_axis_a_tdata[22]),
.I1(s_axis_a_tdata[20]),
.I2(s_axis_a_tdata[21]),
.O(\blk00000001/sig000000f3 )
);
LUT3 #(
.INIT ( 8'hF8 ))
\blk00000001/blk000000ff (
.I0(\blk00000001/sig000000a9 ),
.I1(\blk00000001/sig000000aa ),
.I2(\blk00000001/sig000000a8 ),
.O(\blk00000001/sig000000a7 )
);
LUT2 #(
.INIT ( 4'h4 ))
\blk00000001/blk000000fe (
.I0(\blk00000001/sig000000a8 ),
.I1(\blk00000001/sig000000a9 ),
.O(\blk00000001/sig000000a6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000fd (
.C(aclk),
.CE(aclken),
.D(s_axis_a_tvalid),
.Q(\blk00000001/sig00000240 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000fc (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000021e ),
.Q(m_axis_result_tdata[0])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000fb (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000021f ),
.Q(m_axis_result_tdata[1])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000fa (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000220 ),
.Q(m_axis_result_tdata[2])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f9 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000221 ),
.Q(m_axis_result_tdata[3])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f8 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000222 ),
.Q(m_axis_result_tdata[4])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f7 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000223 ),
.Q(m_axis_result_tdata[5])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f6 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000224 ),
.Q(m_axis_result_tdata[6])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f5 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000225 ),
.Q(m_axis_result_tdata[7])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f4 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000226 ),
.Q(m_axis_result_tdata[8])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f3 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000227 ),
.Q(m_axis_result_tdata[9])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f2 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000228 ),
.Q(m_axis_result_tdata[10])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f1 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000229 ),
.Q(m_axis_result_tdata[11])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000f0 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000022a ),
.Q(m_axis_result_tdata[12])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ef (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000022b ),
.Q(m_axis_result_tdata[13])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ee (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000022c ),
.Q(m_axis_result_tdata[14])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ed (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000022d ),
.Q(m_axis_result_tdata[15])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ec (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000022e ),
.Q(m_axis_result_tdata[16])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000eb (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000022f ),
.Q(m_axis_result_tdata[17])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ea (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000230 ),
.Q(m_axis_result_tdata[18])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e9 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000231 ),
.Q(m_axis_result_tdata[19])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e8 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000232 ),
.Q(m_axis_result_tdata[20])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e7 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000233 ),
.Q(m_axis_result_tdata[21])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e6 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000234 ),
.Q(m_axis_result_tdata[22])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e5 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000214 ),
.Q(m_axis_result_tdata[23])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e4 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000215 ),
.Q(m_axis_result_tdata[24])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e3 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000216 ),
.Q(m_axis_result_tdata[25])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e2 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000217 ),
.Q(m_axis_result_tdata[26])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e1 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000218 ),
.Q(m_axis_result_tdata[27])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000e0 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000219 ),
.Q(m_axis_result_tdata[28])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000df (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000021a ),
.Q(m_axis_result_tdata[29])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000de (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000021b ),
.Q(m_axis_result_tdata[30])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000dd (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000235 ),
.Q(m_axis_result_tdata[31])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000dc (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000023c ),
.Q(\blk00000001/sig00000236 )
);
MUXCY \blk00000001/blk000000db (
.CI(\blk00000001/sig000001d8 ),
.DI(\blk00000001/sig0000023a ),
.S(\blk00000001/sig0000023b ),
.O(\blk00000001/sig0000023f )
);
MUXCY \blk00000001/blk000000da (
.CI(\blk00000001/sig0000023f ),
.DI(\blk00000001/sig000001d8 ),
.S(\blk00000001/sig00000239 ),
.O(\blk00000001/sig0000023e )
);
MUXCY \blk00000001/blk000000d9 (
.CI(\blk00000001/sig0000023e ),
.DI(\blk00000001/sig000001d8 ),
.S(\blk00000001/sig00000238 ),
.O(\blk00000001/sig0000023d )
);
MUXCY \blk00000001/blk000000d8 (
.CI(\blk00000001/sig0000023d ),
.DI(\blk00000001/sig000001d8 ),
.S(\blk00000001/sig00000237 ),
.O(\blk00000001/sig0000023c )
);
DSP48E1 #(
.ACASCREG ( 1 ),
.ADREG ( 0 ),
.ALUMODEREG ( 0 ),
.AREG ( 1 ),
.AUTORESET_PATDET ( "NO_RESET" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 1 ),
.BREG ( 1 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 0 ),
.CARRYINSELREG ( 0 ),
.CREG ( 1 ),
.DREG ( 0 ),
.INMODEREG ( 0 ),
.MASK ( 48'h3FFFFFFFFFFF ),
.MREG ( 1 ),
.OPMODEREG ( 0 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.USE_DPORT ( 0 ),
.USE_MULT ( "MULTIPLY" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ))
\blk00000001/blk000000d7 (
.PATTERNBDETECT(\NLW_blk00000001/blk000000d7_PATTERNBDETECT_UNCONNECTED ),
.RSTC(\blk00000001/sig000001d8 ),
.CEB1(\blk00000001/sig000001d8 ),
.CEAD(\blk00000001/sig000001d8 ),
.MULTSIGNOUT(\NLW_blk00000001/blk000000d7_MULTSIGNOUT_UNCONNECTED ),
.CEC(aclken),
.RSTM(\blk00000001/sig000001d8 ),
.MULTSIGNIN(\blk00000001/sig000001d8 ),
.CEB2(aclken),
.RSTCTRL(\blk00000001/sig000001d8 ),
.CEP(aclken),
.CARRYCASCOUT(\NLW_blk00000001/blk000000d7_CARRYCASCOUT_UNCONNECTED ),
.RSTA(\blk00000001/sig000001d8 ),
.CECARRYIN(\blk00000001/sig000001d8 ),
.UNDERFLOW(\NLW_blk00000001/blk000000d7_UNDERFLOW_UNCONNECTED ),
.PATTERNDETECT(\NLW_blk00000001/blk000000d7_PATTERNDETECT_UNCONNECTED ),
.RSTALUMODE(\blk00000001/sig000001d8 ),
.RSTALLCARRYIN(\blk00000001/sig000001d8 ),
.CED(\blk00000001/sig000001d8 ),
.RSTD(\blk00000001/sig000001d8 ),
.CEALUMODE(\blk00000001/sig000001d8 ),
.CEA2(aclken),
.CLK(aclk),
.CEA1(\blk00000001/sig000001d8 ),
.RSTB(\blk00000001/sig000001d8 ),
.OVERFLOW(\NLW_blk00000001/blk000000d7_OVERFLOW_UNCONNECTED ),
.CECTRL(\blk00000001/sig000001d8 ),
.CEM(aclken),
.CARRYIN(\blk00000001/sig000001d8 ),
.CARRYCASCIN(\blk00000001/sig000001d8 ),
.RSTINMODE(\blk00000001/sig000001d8 ),
.CEINMODE(\blk00000001/sig000001d8 ),
.RSTP(\blk00000001/sig000001d8 ),
.ACOUT({\NLW_blk00000001/blk000000d7_ACOUT<29>_UNCONNECTED , \NLW_blk00000001/blk000000d7_ACOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_ACOUT<27>_UNCONNECTED , \NLW_blk00000001/blk000000d7_ACOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_ACOUT<25>_UNCONNECTED , \NLW_blk00000001/blk000000d7_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_ACOUT<23>_UNCONNECTED , \NLW_blk00000001/blk000000d7_ACOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_ACOUT<21>_UNCONNECTED , \NLW_blk00000001/blk000000d7_ACOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_ACOUT<19>_UNCONNECTED , \NLW_blk00000001/blk000000d7_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_ACOUT<17>_UNCONNECTED , \NLW_blk00000001/blk000000d7_ACOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_ACOUT<15>_UNCONNECTED , \NLW_blk00000001/blk000000d7_ACOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_ACOUT<13>_UNCONNECTED , \NLW_blk00000001/blk000000d7_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_ACOUT<11>_UNCONNECTED , \NLW_blk00000001/blk000000d7_ACOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_ACOUT<9>_UNCONNECTED , \NLW_blk00000001/blk000000d7_ACOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_ACOUT<7>_UNCONNECTED , \NLW_blk00000001/blk000000d7_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_ACOUT<5>_UNCONNECTED , \NLW_blk00000001/blk000000d7_ACOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_ACOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000000d7_ACOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_ACOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000000d7_ACOUT<0>_UNCONNECTED }),
.OPMODE({\blk00000001/sig000001d8 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 ,
\blk00000001/sig000001d8 , \blk00000001/sig00000132 }),
.PCIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.ALUMODE({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.C({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig00000210 , \blk00000001/sig0000020f , \blk00000001/sig0000020e ,
\blk00000001/sig0000020d , \blk00000001/sig0000020c , \blk00000001/sig0000020b , \blk00000001/sig0000020a , \blk00000001/sig00000209 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig00000112 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.CARRYOUT({\NLW_blk00000001/blk000000d7_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000000d7_CARRYOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000000d7_CARRYOUT<0>_UNCONNECTED }),
.INMODE({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.BCIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.B({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig00000063 , \blk00000001/sig00000062 , \blk00000001/sig00000061 , \blk00000001/sig00000060 , \blk00000001/sig0000005f ,
\blk00000001/sig0000005e , \blk00000001/sig0000005d , \blk00000001/sig0000005c }),
.BCOUT({\NLW_blk00000001/blk000000d7_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk000000d7_BCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk000000d7_BCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk000000d7_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk000000d7_BCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk000000d7_BCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk000000d7_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk000000d7_BCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000000d7_BCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000000d7_BCOUT<0>_UNCONNECTED }),
.D({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.P({\NLW_blk00000001/blk000000d7_P<47>_UNCONNECTED , \NLW_blk00000001/blk000000d7_P<46>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_P<45>_UNCONNECTED , \NLW_blk00000001/blk000000d7_P<44>_UNCONNECTED , \NLW_blk00000001/blk000000d7_P<43>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_P<42>_UNCONNECTED , \NLW_blk00000001/blk000000d7_P<41>_UNCONNECTED , \NLW_blk00000001/blk000000d7_P<40>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_P<39>_UNCONNECTED , \NLW_blk00000001/blk000000d7_P<38>_UNCONNECTED , \NLW_blk00000001/blk000000d7_P<37>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_P<36>_UNCONNECTED , \NLW_blk00000001/blk000000d7_P<35>_UNCONNECTED , \blk00000001/sig0000005b , \blk00000001/sig0000005a
, \blk00000001/sig00000059 , \blk00000001/sig00000058 , \blk00000001/sig00000057 , \blk00000001/sig00000056 , \blk00000001/sig00000055 ,
\blk00000001/sig00000054 , \blk00000001/sig00000053 , \blk00000001/sig00000052 , \blk00000001/sig00000051 , \blk00000001/sig00000050 ,
\blk00000001/sig0000004f , \blk00000001/sig0000004e , \blk00000001/sig0000004d , \blk00000001/sig0000004c , \blk00000001/sig0000004b ,
\blk00000001/sig0000004a , \blk00000001/sig00000049 , \blk00000001/sig00000048 , \blk00000001/sig00000047 , \blk00000001/sig00000046 ,
\blk00000001/sig00000045 , \NLW_blk00000001/blk000000d7_P<11>_UNCONNECTED , \NLW_blk00000001/blk000000d7_P<10>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_P<9>_UNCONNECTED , \NLW_blk00000001/blk000000d7_P<8>_UNCONNECTED , \NLW_blk00000001/blk000000d7_P<7>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_P<6>_UNCONNECTED , \NLW_blk00000001/blk000000d7_P<5>_UNCONNECTED , \NLW_blk00000001/blk000000d7_P<4>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_P<3>_UNCONNECTED , \NLW_blk00000001/blk000000d7_P<2>_UNCONNECTED , \NLW_blk00000001/blk000000d7_P<1>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_P<0>_UNCONNECTED }),
.A({\blk00000001/sig00000079 , \blk00000001/sig00000079 , \blk00000001/sig00000079 , \blk00000001/sig00000079 , \blk00000001/sig00000079 ,
\blk00000001/sig00000079 , \blk00000001/sig00000079 , \blk00000001/sig00000079 , \blk00000001/sig00000079 , \blk00000001/sig00000078 ,
\blk00000001/sig00000077 , \blk00000001/sig00000076 , \blk00000001/sig00000075 , \blk00000001/sig00000074 , \blk00000001/sig00000073 ,
\blk00000001/sig00000072 , \blk00000001/sig00000071 , \blk00000001/sig00000070 , \blk00000001/sig0000006f , \blk00000001/sig0000006e ,
\blk00000001/sig0000006d , \blk00000001/sig0000006c , \blk00000001/sig0000006b , \blk00000001/sig0000006a , \blk00000001/sig00000069 ,
\blk00000001/sig00000068 , \blk00000001/sig00000067 , \blk00000001/sig00000066 , \blk00000001/sig00000065 , \blk00000001/sig00000064 }),
.PCOUT({\NLW_blk00000001/blk000000d7_PCOUT<47>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<46>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<45>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<44>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<43>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<42>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<41>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<40>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<39>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<38>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<37>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<36>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<35>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<34>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<33>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<32>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<31>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<30>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<29>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<27>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<25>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<23>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<21>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<19>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000d7_PCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000000d7_PCOUT<0>_UNCONNECTED }),
.ACIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.CARRYINSEL({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d6 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000005c ),
.Q(\blk00000001/sig00000209 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d5 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000005d ),
.Q(\blk00000001/sig0000020a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d4 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000005e ),
.Q(\blk00000001/sig0000020b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d3 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000005f ),
.Q(\blk00000001/sig0000020c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d2 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000060 ),
.Q(\blk00000001/sig0000020d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d1 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000061 ),
.Q(\blk00000001/sig0000020e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000d0 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000062 ),
.Q(\blk00000001/sig0000020f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000cf (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000063 ),
.Q(\blk00000001/sig00000210 )
);
DSP48E1 #(
.ACASCREG ( 1 ),
.ADREG ( 0 ),
.ALUMODEREG ( 0 ),
.AREG ( 1 ),
.AUTORESET_PATDET ( "NO_RESET" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 1 ),
.BREG ( 1 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 0 ),
.CARRYINSELREG ( 0 ),
.CREG ( 1 ),
.DREG ( 0 ),
.INMODEREG ( 0 ),
.MASK ( 48'h3FFFFFFFFFFF ),
.MREG ( 1 ),
.OPMODEREG ( 0 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.USE_DPORT ( 0 ),
.USE_MULT ( "MULTIPLY" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ))
\blk00000001/blk000000ce (
.PATTERNBDETECT(\NLW_blk00000001/blk000000ce_PATTERNBDETECT_UNCONNECTED ),
.RSTC(\blk00000001/sig000001d8 ),
.CEB1(\blk00000001/sig000001d8 ),
.CEAD(\blk00000001/sig000001d8 ),
.MULTSIGNOUT(\NLW_blk00000001/blk000000ce_MULTSIGNOUT_UNCONNECTED ),
.CEC(aclken),
.RSTM(\blk00000001/sig000001d8 ),
.MULTSIGNIN(\blk00000001/sig000001d8 ),
.CEB2(aclken),
.RSTCTRL(\blk00000001/sig000001d8 ),
.CEP(aclken),
.CARRYCASCOUT(\NLW_blk00000001/blk000000ce_CARRYCASCOUT_UNCONNECTED ),
.RSTA(\blk00000001/sig000001d8 ),
.CECARRYIN(\blk00000001/sig000001d8 ),
.UNDERFLOW(\NLW_blk00000001/blk000000ce_UNDERFLOW_UNCONNECTED ),
.PATTERNDETECT(\NLW_blk00000001/blk000000ce_PATTERNDETECT_UNCONNECTED ),
.RSTALUMODE(\blk00000001/sig000001d8 ),
.RSTALLCARRYIN(\blk00000001/sig000001d8 ),
.CED(\blk00000001/sig000001d8 ),
.RSTD(\blk00000001/sig000001d8 ),
.CEALUMODE(\blk00000001/sig000001d8 ),
.CEA2(aclken),
.CLK(aclk),
.CEA1(\blk00000001/sig000001d8 ),
.RSTB(\blk00000001/sig000001d8 ),
.OVERFLOW(\NLW_blk00000001/blk000000ce_OVERFLOW_UNCONNECTED ),
.CECTRL(\blk00000001/sig000001d8 ),
.CEM(aclken),
.CARRYIN(\blk00000001/sig000001d8 ),
.CARRYCASCIN(\blk00000001/sig000001d8 ),
.RSTINMODE(\blk00000001/sig000001d8 ),
.CEINMODE(\blk00000001/sig000001d8 ),
.RSTP(\blk00000001/sig000001d8 ),
.ACOUT({\NLW_blk00000001/blk000000ce_ACOUT<29>_UNCONNECTED , \NLW_blk00000001/blk000000ce_ACOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_ACOUT<27>_UNCONNECTED , \NLW_blk00000001/blk000000ce_ACOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_ACOUT<25>_UNCONNECTED , \NLW_blk00000001/blk000000ce_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_ACOUT<23>_UNCONNECTED , \NLW_blk00000001/blk000000ce_ACOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_ACOUT<21>_UNCONNECTED , \NLW_blk00000001/blk000000ce_ACOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_ACOUT<19>_UNCONNECTED , \NLW_blk00000001/blk000000ce_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_ACOUT<17>_UNCONNECTED , \NLW_blk00000001/blk000000ce_ACOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_ACOUT<15>_UNCONNECTED , \NLW_blk00000001/blk000000ce_ACOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_ACOUT<13>_UNCONNECTED , \NLW_blk00000001/blk000000ce_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_ACOUT<11>_UNCONNECTED , \NLW_blk00000001/blk000000ce_ACOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_ACOUT<9>_UNCONNECTED , \NLW_blk00000001/blk000000ce_ACOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_ACOUT<7>_UNCONNECTED , \NLW_blk00000001/blk000000ce_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_ACOUT<5>_UNCONNECTED , \NLW_blk00000001/blk000000ce_ACOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_ACOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000000ce_ACOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_ACOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000000ce_ACOUT<0>_UNCONNECTED }),
.OPMODE({\blk00000001/sig000001d8 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 ,
\blk00000001/sig000001d8 , \blk00000001/sig00000132 }),
.PCIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.ALUMODE({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 , \blk00000001/sig00000132 }),
.C({\blk00000001/sig00000208 , \blk00000001/sig00000208 , \blk00000001/sig00000208 , \blk00000001/sig00000208 , \blk00000001/sig00000208 ,
\blk00000001/sig00000208 , \blk00000001/sig00000208 , \blk00000001/sig00000208 , \blk00000001/sig00000208 , \blk00000001/sig00000208 ,
\blk00000001/sig00000208 , \blk00000001/sig00000208 , \blk00000001/sig00000208 , \blk00000001/sig00000208 , \blk00000001/sig00000208 ,
\blk00000001/sig00000208 , \blk00000001/sig00000208 , \blk00000001/sig00000208 , \blk00000001/sig00000208 , \blk00000001/sig00000208 ,
\blk00000001/sig00000208 , \blk00000001/sig00000208 , \blk00000001/sig00000208 , \blk00000001/sig00000208 , \blk00000001/sig00000208 ,
\blk00000001/sig00000208 , \blk00000001/sig00000207 , \blk00000001/sig00000206 , \blk00000001/sig00000205 , \blk00000001/sig00000204 ,
\blk00000001/sig00000203 , \blk00000001/sig00000202 , \blk00000001/sig00000201 , \blk00000001/sig00000200 , \blk00000001/sig000001ff ,
\blk00000001/sig000001fe , \blk00000001/sig000001fd , \blk00000001/sig000001fc , \blk00000001/sig000001fb , \blk00000001/sig000001fa ,
\blk00000001/sig000001f9 , \blk00000001/sig000001f8 , \blk00000001/sig000001f7 , \blk00000001/sig000001f6 , \blk00000001/sig000001f5 ,
\blk00000001/sig000001f4 , \blk00000001/sig000001f3 , \blk00000001/sig000001f2 }),
.CARRYOUT({\NLW_blk00000001/blk000000ce_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000000ce_CARRYOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000000ce_CARRYOUT<0>_UNCONNECTED }),
.INMODE({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.BCIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.B({\blk00000001/sig000001a1 , \blk00000001/sig000001a1 , \blk00000001/sig000001a1 , \blk00000001/sig000001a1 , \blk00000001/sig000001a1 ,
\blk00000001/sig000001a1 , \blk00000001/sig000001a1 , \blk00000001/sig000001a1 , \blk00000001/sig000001a1 , \blk00000001/sig000001a1 ,
\blk00000001/sig000001a1 , \blk00000001/sig000001a0 , \blk00000001/sig0000019f , \blk00000001/sig0000019e , \blk00000001/sig0000019d ,
\blk00000001/sig0000019c , \blk00000001/sig0000019b , \blk00000001/sig0000019a }),
.BCOUT({\NLW_blk00000001/blk000000ce_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk000000ce_BCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk000000ce_BCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk000000ce_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk000000ce_BCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk000000ce_BCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk000000ce_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk000000ce_BCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000000ce_BCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000000ce_BCOUT<0>_UNCONNECTED }),
.D({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.P({\NLW_blk00000001/blk000000ce_P<47>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<46>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_P<45>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<44>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<43>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_P<42>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<41>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<40>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_P<39>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<38>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<37>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_P<36>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<35>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_P<33>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<32>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_P<30>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<29>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_P<27>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<26>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<25>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_P<24>_UNCONNECTED , \blk00000001/sig000001f1 , \blk00000001/sig000001f0 , \blk00000001/sig000001ef ,
\blk00000001/sig000001ee , \blk00000001/sig000001ed , \blk00000001/sig000001ec , \blk00000001/sig000001eb , \blk00000001/sig000001ea ,
\blk00000001/sig000001e9 , \blk00000001/sig000001e8 , \blk00000001/sig000001e7 , \blk00000001/sig000001e6 , \blk00000001/sig000001e5 ,
\blk00000001/sig000001e4 , \blk00000001/sig000001e3 , \blk00000001/sig000001e2 , \blk00000001/sig000001e1 ,
\NLW_blk00000001/blk000000ce_P<6>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<5>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<4>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_P<3>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<2>_UNCONNECTED , \NLW_blk00000001/blk000000ce_P<1>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_P<0>_UNCONNECTED }),
.A({\blk00000001/sig00000199 , \blk00000001/sig00000199 , \blk00000001/sig00000199 , \blk00000001/sig00000199 , \blk00000001/sig00000199 ,
\blk00000001/sig00000199 , \blk00000001/sig00000199 , \blk00000001/sig00000199 , \blk00000001/sig00000199 , \blk00000001/sig00000199 ,
\blk00000001/sig00000199 , \blk00000001/sig00000199 , \blk00000001/sig00000199 , \blk00000001/sig00000199 , \blk00000001/sig00000199 ,
\blk00000001/sig00000199 , \blk00000001/sig00000199 , \blk00000001/sig00000199 , \blk00000001/sig00000199 , \blk00000001/sig00000199 ,
\blk00000001/sig00000199 , \blk00000001/sig00000199 , \blk00000001/sig00000199 , \blk00000001/sig00000198 , \blk00000001/sig00000197 ,
\blk00000001/sig00000196 , \blk00000001/sig00000195 , \blk00000001/sig00000194 , \blk00000001/sig00000193 , \blk00000001/sig00000192 }),
.PCOUT({\NLW_blk00000001/blk000000ce_PCOUT<47>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<46>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<45>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<44>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<43>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<42>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<41>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<40>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<39>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<38>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<37>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<36>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<35>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<34>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<33>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<32>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<31>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<30>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<29>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<27>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<25>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<23>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<21>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<19>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000ce_PCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000000ce_PCOUT<0>_UNCONNECTED }),
.ACIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.CARRYINSEL({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000cd (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001a2 ),
.Q(\blk00000001/sig000001f2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000cc (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001a3 ),
.Q(\blk00000001/sig000001f3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000cb (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001a4 ),
.Q(\blk00000001/sig000001f4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ca (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001a5 ),
.Q(\blk00000001/sig000001f5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c9 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001a6 ),
.Q(\blk00000001/sig000001f6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c8 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001a7 ),
.Q(\blk00000001/sig000001f7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c7 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001a8 ),
.Q(\blk00000001/sig000001f8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c6 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001a9 ),
.Q(\blk00000001/sig000001f9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c5 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001aa ),
.Q(\blk00000001/sig000001fa )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c4 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001ab ),
.Q(\blk00000001/sig000001fb )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c3 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001ac ),
.Q(\blk00000001/sig000001fc )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c2 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001ad ),
.Q(\blk00000001/sig000001fd )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c1 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001ae ),
.Q(\blk00000001/sig000001fe )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000c0 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001af ),
.Q(\blk00000001/sig000001ff )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000bf (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001b0 ),
.Q(\blk00000001/sig00000200 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000be (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001b1 ),
.Q(\blk00000001/sig00000201 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000bd (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001b2 ),
.Q(\blk00000001/sig00000202 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000bc (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001b3 ),
.Q(\blk00000001/sig00000203 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000bb (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001b4 ),
.Q(\blk00000001/sig00000204 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ba (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001b5 ),
.Q(\blk00000001/sig00000205 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b9 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001b6 ),
.Q(\blk00000001/sig00000206 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b8 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001b7 ),
.Q(\blk00000001/sig00000207 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b7 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001b8 ),
.Q(\blk00000001/sig00000208 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b6 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000166 ),
.Q(\blk00000001/sig00000064 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b5 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000167 ),
.Q(\blk00000001/sig00000065 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b4 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000168 ),
.Q(\blk00000001/sig00000066 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b3 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000169 ),
.Q(\blk00000001/sig00000067 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b2 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000016a ),
.Q(\blk00000001/sig00000068 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b1 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000016b ),
.Q(\blk00000001/sig00000069 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000b0 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000016c ),
.Q(\blk00000001/sig0000006a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000af (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000016d ),
.Q(\blk00000001/sig0000006b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ae (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000016e ),
.Q(\blk00000001/sig0000006c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ad (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000016f ),
.Q(\blk00000001/sig0000006d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ac (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000170 ),
.Q(\blk00000001/sig0000006e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000ab (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000171 ),
.Q(\blk00000001/sig0000006f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000aa (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000172 ),
.Q(\blk00000001/sig00000070 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a9 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000173 ),
.Q(\blk00000001/sig00000071 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a8 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000174 ),
.Q(\blk00000001/sig00000072 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a7 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000175 ),
.Q(\blk00000001/sig00000073 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a6 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000176 ),
.Q(\blk00000001/sig00000074 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a5 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000177 ),
.Q(\blk00000001/sig00000075 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a4 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000178 ),
.Q(\blk00000001/sig00000076 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a3 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig00000179 ),
.Q(\blk00000001/sig00000077 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a2 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000017a ),
.Q(\blk00000001/sig00000078 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000000a1 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000017b ),
.Q(\blk00000001/sig00000079 )
);
DSP48E1 #(
.ACASCREG ( 1 ),
.ADREG ( 0 ),
.ALUMODEREG ( 0 ),
.AREG ( 1 ),
.AUTORESET_PATDET ( "NO_RESET" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 1 ),
.BREG ( 1 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 0 ),
.CARRYINSELREG ( 0 ),
.CREG ( 1 ),
.DREG ( 0 ),
.INMODEREG ( 0 ),
.MASK ( 48'h3FFFFFFFFFFF ),
.MREG ( 1 ),
.OPMODEREG ( 0 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.USE_DPORT ( 0 ),
.USE_MULT ( "MULTIPLY" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ))
\blk00000001/blk000000a0 (
.PATTERNBDETECT(\NLW_blk00000001/blk000000a0_PATTERNBDETECT_UNCONNECTED ),
.RSTC(\blk00000001/sig000001d8 ),
.CEB1(\blk00000001/sig000001d8 ),
.CEAD(\blk00000001/sig000001d8 ),
.MULTSIGNOUT(\NLW_blk00000001/blk000000a0_MULTSIGNOUT_UNCONNECTED ),
.CEC(aclken),
.RSTM(\blk00000001/sig000001d8 ),
.MULTSIGNIN(\blk00000001/sig000001d8 ),
.CEB2(aclken),
.RSTCTRL(\blk00000001/sig000001d8 ),
.CEP(aclken),
.CARRYCASCOUT(\NLW_blk00000001/blk000000a0_CARRYCASCOUT_UNCONNECTED ),
.RSTA(\blk00000001/sig000001d8 ),
.CECARRYIN(\blk00000001/sig000001d8 ),
.UNDERFLOW(\NLW_blk00000001/blk000000a0_UNDERFLOW_UNCONNECTED ),
.PATTERNDETECT(\NLW_blk00000001/blk000000a0_PATTERNDETECT_UNCONNECTED ),
.RSTALUMODE(\blk00000001/sig000001d8 ),
.RSTALLCARRYIN(\blk00000001/sig000001d8 ),
.CED(\blk00000001/sig000001d8 ),
.RSTD(\blk00000001/sig000001d8 ),
.CEALUMODE(\blk00000001/sig000001d8 ),
.CEA2(aclken),
.CLK(aclk),
.CEA1(\blk00000001/sig000001d8 ),
.RSTB(\blk00000001/sig000001d8 ),
.OVERFLOW(\NLW_blk00000001/blk000000a0_OVERFLOW_UNCONNECTED ),
.CECTRL(\blk00000001/sig000001d8 ),
.CEM(aclken),
.CARRYIN(\blk00000001/sig000001d8 ),
.CARRYCASCIN(\blk00000001/sig000001d8 ),
.RSTINMODE(\blk00000001/sig000001d8 ),
.CEINMODE(\blk00000001/sig000001d8 ),
.RSTP(\blk00000001/sig000001d8 ),
.ACOUT({\NLW_blk00000001/blk000000a0_ACOUT<29>_UNCONNECTED , \NLW_blk00000001/blk000000a0_ACOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_ACOUT<27>_UNCONNECTED , \NLW_blk00000001/blk000000a0_ACOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_ACOUT<25>_UNCONNECTED , \NLW_blk00000001/blk000000a0_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_ACOUT<23>_UNCONNECTED , \NLW_blk00000001/blk000000a0_ACOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_ACOUT<21>_UNCONNECTED , \NLW_blk00000001/blk000000a0_ACOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_ACOUT<19>_UNCONNECTED , \NLW_blk00000001/blk000000a0_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_ACOUT<17>_UNCONNECTED , \NLW_blk00000001/blk000000a0_ACOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_ACOUT<15>_UNCONNECTED , \NLW_blk00000001/blk000000a0_ACOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_ACOUT<13>_UNCONNECTED , \NLW_blk00000001/blk000000a0_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_ACOUT<11>_UNCONNECTED , \NLW_blk00000001/blk000000a0_ACOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_ACOUT<9>_UNCONNECTED , \NLW_blk00000001/blk000000a0_ACOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_ACOUT<7>_UNCONNECTED , \NLW_blk00000001/blk000000a0_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_ACOUT<5>_UNCONNECTED , \NLW_blk00000001/blk000000a0_ACOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_ACOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000000a0_ACOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_ACOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000000a0_ACOUT<0>_UNCONNECTED }),
.OPMODE({\blk00000001/sig000001d8 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 ,
\blk00000001/sig000001d8 , \blk00000001/sig00000132 }),
.PCIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.ALUMODE({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.C({\blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000133 ,
\blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000133 ,
\blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000133 ,
\blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000133 ,
\blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000133 ,
\blk00000001/sig00000133 , \blk00000001/sig00000133 , \blk00000001/sig00000134 , \blk00000001/sig00000135 , \blk00000001/sig00000136 ,
\blk00000001/sig00000137 , \blk00000001/sig00000138 , \blk00000001/sig00000139 , \blk00000001/sig0000013a , \blk00000001/sig000001e0 ,
\blk00000001/sig000001df , \blk00000001/sig000001de , \blk00000001/sig000001dd , \blk00000001/sig000001dc , \blk00000001/sig000001db ,
\blk00000001/sig000001da , \blk00000001/sig000001d9 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.CARRYOUT({\NLW_blk00000001/blk000000a0_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000000a0_CARRYOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000000a0_CARRYOUT<0>_UNCONNECTED }),
.INMODE({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.BCIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.B({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001bf , \blk00000001/sig000001be , \blk00000001/sig000001bd , \blk00000001/sig000001bc ,
\blk00000001/sig000001bb , \blk00000001/sig000001ba , \blk00000001/sig000001b9 }),
.BCOUT({\NLW_blk00000001/blk000000a0_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk000000a0_BCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk000000a0_BCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk000000a0_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk000000a0_BCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk000000a0_BCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk000000a0_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk000000a0_BCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000000a0_BCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000000a0_BCOUT<0>_UNCONNECTED }),
.D({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.P({\NLW_blk00000001/blk000000a0_P<47>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<46>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_P<45>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<44>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<43>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_P<42>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<41>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<40>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_P<39>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<38>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<37>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_P<36>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<35>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_P<33>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<32>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_P<30>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<29>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_P<27>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<26>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<25>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_P<24>_UNCONNECTED , \NLW_blk00000001/blk000000a0_P<23>_UNCONNECTED , \blk00000001/sig000001b8 , \blk00000001/sig000001b7
, \blk00000001/sig000001b6 , \blk00000001/sig000001b5 , \blk00000001/sig000001b4 , \blk00000001/sig000001b3 , \blk00000001/sig000001b2 ,
\blk00000001/sig000001b1 , \blk00000001/sig000001b0 , \blk00000001/sig000001af , \blk00000001/sig000001ae , \blk00000001/sig000001ad ,
\blk00000001/sig000001ac , \blk00000001/sig000001ab , \blk00000001/sig000001aa , \blk00000001/sig000001a9 , \blk00000001/sig000001a8 ,
\blk00000001/sig000001a7 , \blk00000001/sig000001a6 , \blk00000001/sig000001a5 , \blk00000001/sig000001a4 , \blk00000001/sig000001a3 ,
\blk00000001/sig000001a2 }),
.A({\blk00000001/sig000001c7 , \blk00000001/sig000001c7 , \blk00000001/sig000001c7 , \blk00000001/sig000001c7 , \blk00000001/sig000001c7 ,
\blk00000001/sig000001c7 , \blk00000001/sig000001c7 , \blk00000001/sig000001c7 , \blk00000001/sig000001c7 , \blk00000001/sig000001c7 ,
\blk00000001/sig000001c7 , \blk00000001/sig000001c7 , \blk00000001/sig000001c7 , \blk00000001/sig000001c7 , \blk00000001/sig000001c7 ,
\blk00000001/sig000001c7 , \blk00000001/sig000001c7 , \blk00000001/sig000001c7 , \blk00000001/sig000001c7 , \blk00000001/sig000001c7 ,
\blk00000001/sig000001c7 , \blk00000001/sig000001c7 , \blk00000001/sig000001c6 , \blk00000001/sig000001c5 , \blk00000001/sig000001c4 ,
\blk00000001/sig000001c3 , \blk00000001/sig000001c2 , \blk00000001/sig000001c1 , \blk00000001/sig000001c0 , \blk00000001/sig000001d8 }),
.PCOUT({\NLW_blk00000001/blk000000a0_PCOUT<47>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<46>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<45>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<44>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<43>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<42>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<41>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<40>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<39>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<38>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<37>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<36>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<35>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<34>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<33>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<32>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<31>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<30>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<29>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<27>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<25>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<23>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<21>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<19>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk000000a0_PCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk000000a0_PCOUT<0>_UNCONNECTED }),
.ACIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.CARRYINSEL({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000009f (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001c8 ),
.Q(\blk00000001/sig000001d9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000009e (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001c9 ),
.Q(\blk00000001/sig000001da )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000009d (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001ca ),
.Q(\blk00000001/sig000001db )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000009c (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001cb ),
.Q(\blk00000001/sig000001dc )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000009b (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001cc ),
.Q(\blk00000001/sig000001dd )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000009a (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001cd ),
.Q(\blk00000001/sig000001de )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000099 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001ce ),
.Q(\blk00000001/sig000001df )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000098 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001cf ),
.Q(\blk00000001/sig000001e0 )
);
DSP48E1 #(
.ACASCREG ( 1 ),
.ADREG ( 0 ),
.ALUMODEREG ( 0 ),
.AREG ( 1 ),
.AUTORESET_PATDET ( "NO_RESET" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 1 ),
.BREG ( 1 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 0 ),
.CARRYINSELREG ( 0 ),
.CREG ( 1 ),
.DREG ( 0 ),
.INMODEREG ( 0 ),
.MASK ( 48'h000000000000 ),
.MREG ( 1 ),
.OPMODEREG ( 0 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.USE_DPORT ( 0 ),
.USE_MULT ( "MULTIPLY" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ))
\blk00000001/blk00000097 (
.PATTERNBDETECT(\NLW_blk00000001/blk00000097_PATTERNBDETECT_UNCONNECTED ),
.RSTC(\blk00000001/sig000001d8 ),
.CEB1(\blk00000001/sig000001d8 ),
.CEAD(\blk00000001/sig000001d8 ),
.MULTSIGNOUT(\NLW_blk00000001/blk00000097_MULTSIGNOUT_UNCONNECTED ),
.CEC(aclken),
.RSTM(\blk00000001/sig000001d8 ),
.MULTSIGNIN(\blk00000001/sig000001d8 ),
.CEB2(aclken),
.RSTCTRL(\blk00000001/sig000001d8 ),
.CEP(aclken),
.CARRYCASCOUT(\NLW_blk00000001/blk00000097_CARRYCASCOUT_UNCONNECTED ),
.RSTA(\blk00000001/sig000001d8 ),
.CECARRYIN(\blk00000001/sig000001d8 ),
.UNDERFLOW(\NLW_blk00000001/blk00000097_UNDERFLOW_UNCONNECTED ),
.PATTERNDETECT(\NLW_blk00000001/blk00000097_PATTERNDETECT_UNCONNECTED ),
.RSTALUMODE(\blk00000001/sig000001d8 ),
.RSTALLCARRYIN(\blk00000001/sig000001d8 ),
.CED(\blk00000001/sig000001d8 ),
.RSTD(\blk00000001/sig000001d8 ),
.CEALUMODE(\blk00000001/sig000001d8 ),
.CEA2(aclken),
.CLK(aclk),
.CEA1(\blk00000001/sig000001d8 ),
.RSTB(\blk00000001/sig000001d8 ),
.OVERFLOW(\NLW_blk00000001/blk00000097_OVERFLOW_UNCONNECTED ),
.CECTRL(\blk00000001/sig000001d8 ),
.CEM(aclken),
.CARRYIN(\blk00000001/sig000001d8 ),
.CARRYCASCIN(\blk00000001/sig000001d8 ),
.RSTINMODE(\blk00000001/sig000001d8 ),
.CEINMODE(\blk00000001/sig000001d8 ),
.RSTP(\blk00000001/sig000001d8 ),
.ACOUT({\NLW_blk00000001/blk00000097_ACOUT<29>_UNCONNECTED , \NLW_blk00000001/blk00000097_ACOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_ACOUT<27>_UNCONNECTED , \NLW_blk00000001/blk00000097_ACOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_ACOUT<25>_UNCONNECTED , \NLW_blk00000001/blk00000097_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_ACOUT<23>_UNCONNECTED , \NLW_blk00000001/blk00000097_ACOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_ACOUT<21>_UNCONNECTED , \NLW_blk00000001/blk00000097_ACOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_ACOUT<19>_UNCONNECTED , \NLW_blk00000001/blk00000097_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_ACOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000097_ACOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_ACOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000097_ACOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_ACOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000097_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_ACOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000097_ACOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_ACOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000097_ACOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_ACOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000097_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_ACOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000097_ACOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_ACOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000097_ACOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_ACOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000097_ACOUT<0>_UNCONNECTED }),
.OPMODE({\blk00000001/sig000001d8 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 ,
\blk00000001/sig000001d8 , \blk00000001/sig00000132 }),
.PCIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.ALUMODE({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.C({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig00000112 }),
.CARRYOUT({\NLW_blk00000001/blk00000097_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000097_CARRYOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000097_CARRYOUT<0>_UNCONNECTED }),
.INMODE({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.BCIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.B({\blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008f ,
\blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008f ,
\blk00000001/sig0000008f , \blk00000001/sig0000008e , \blk00000001/sig0000008d , \blk00000001/sig0000008c , \blk00000001/sig0000008b ,
\blk00000001/sig0000008a , \blk00000001/sig00000089 , \blk00000001/sig00000088 }),
.BCOUT({\NLW_blk00000001/blk00000097_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000097_BCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000097_BCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000097_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000097_BCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000097_BCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000097_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000097_BCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000097_BCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000097_BCOUT<0>_UNCONNECTED }),
.D({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.P({\NLW_blk00000001/blk00000097_P<47>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<46>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_P<45>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<44>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<43>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_P<42>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<41>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<40>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_P<39>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<38>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<37>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_P<36>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<35>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_P<33>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<32>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_P<30>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<29>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_P<27>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<26>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<25>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_P<24>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<23>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_P<21>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<20>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<19>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_P<18>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<17>_UNCONNECTED , \NLW_blk00000001/blk00000097_P<16>_UNCONNECTED ,
\blk00000001/sig000001d7 , \blk00000001/sig000001d6 , \blk00000001/sig000001d5 , \blk00000001/sig000001d4 , \blk00000001/sig000001d3 ,
\blk00000001/sig000001d2 , \blk00000001/sig000001d1 , \blk00000001/sig000001d0 , \blk00000001/sig000001cf , \blk00000001/sig000001ce ,
\blk00000001/sig000001cd , \blk00000001/sig000001cc , \blk00000001/sig000001cb , \blk00000001/sig000001ca , \blk00000001/sig000001c9 ,
\blk00000001/sig000001c8 }),
.A({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008f ,
\blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008f ,
\blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008f ,
\blk00000001/sig0000008f , \blk00000001/sig0000008f , \blk00000001/sig0000008e , \blk00000001/sig0000008d , \blk00000001/sig0000008c ,
\blk00000001/sig0000008b , \blk00000001/sig0000008a , \blk00000001/sig00000089 , \blk00000001/sig00000088 , \blk00000001/sig000001d8 }),
.PCOUT({\NLW_blk00000001/blk00000097_PCOUT<47>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<46>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<45>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<44>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<43>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<42>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<41>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<40>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<39>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<38>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<37>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<36>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<35>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<34>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<33>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<32>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<31>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<29>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<27>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<25>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<23>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<21>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<19>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000097_PCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000097_PCOUT<0>_UNCONNECTED }),
.ACIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.CARRYINSEL({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 })
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000096 (
.I0(\blk00000001/sig0000017c ),
.I1(\blk00000001/sig000001e1 ),
.O(\blk00000001/sig00000165 )
);
MUXCY \blk00000001/blk00000095 (
.CI(\blk00000001/sig00000132 ),
.DI(\blk00000001/sig000001e1 ),
.S(\blk00000001/sig00000165 ),
.O(\blk00000001/sig00000164 )
);
XORCY \blk00000001/blk00000094 (
.CI(\blk00000001/sig00000132 ),
.LI(\blk00000001/sig00000165 ),
.O(\blk00000001/sig00000166 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000093 (
.I0(\blk00000001/sig0000017d ),
.I1(\blk00000001/sig000001e2 ),
.O(\blk00000001/sig00000163 )
);
MUXCY \blk00000001/blk00000092 (
.CI(\blk00000001/sig00000164 ),
.DI(\blk00000001/sig000001e2 ),
.S(\blk00000001/sig00000163 ),
.O(\blk00000001/sig00000162 )
);
XORCY \blk00000001/blk00000091 (
.CI(\blk00000001/sig00000164 ),
.LI(\blk00000001/sig00000163 ),
.O(\blk00000001/sig00000167 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000090 (
.I0(\blk00000001/sig0000017e ),
.I1(\blk00000001/sig000001e3 ),
.O(\blk00000001/sig00000161 )
);
MUXCY \blk00000001/blk0000008f (
.CI(\blk00000001/sig00000162 ),
.DI(\blk00000001/sig000001e3 ),
.S(\blk00000001/sig00000161 ),
.O(\blk00000001/sig00000160 )
);
XORCY \blk00000001/blk0000008e (
.CI(\blk00000001/sig00000162 ),
.LI(\blk00000001/sig00000161 ),
.O(\blk00000001/sig00000168 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk0000008d (
.I0(\blk00000001/sig0000017f ),
.I1(\blk00000001/sig000001e4 ),
.O(\blk00000001/sig0000015f )
);
MUXCY \blk00000001/blk0000008c (
.CI(\blk00000001/sig00000160 ),
.DI(\blk00000001/sig000001e4 ),
.S(\blk00000001/sig0000015f ),
.O(\blk00000001/sig0000015e )
);
XORCY \blk00000001/blk0000008b (
.CI(\blk00000001/sig00000160 ),
.LI(\blk00000001/sig0000015f ),
.O(\blk00000001/sig00000169 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk0000008a (
.I0(\blk00000001/sig00000180 ),
.I1(\blk00000001/sig000001e5 ),
.O(\blk00000001/sig0000015d )
);
MUXCY \blk00000001/blk00000089 (
.CI(\blk00000001/sig0000015e ),
.DI(\blk00000001/sig000001e5 ),
.S(\blk00000001/sig0000015d ),
.O(\blk00000001/sig0000015c )
);
XORCY \blk00000001/blk00000088 (
.CI(\blk00000001/sig0000015e ),
.LI(\blk00000001/sig0000015d ),
.O(\blk00000001/sig0000016a )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000087 (
.I0(\blk00000001/sig00000181 ),
.I1(\blk00000001/sig000001e6 ),
.O(\blk00000001/sig0000015b )
);
MUXCY \blk00000001/blk00000086 (
.CI(\blk00000001/sig0000015c ),
.DI(\blk00000001/sig000001e6 ),
.S(\blk00000001/sig0000015b ),
.O(\blk00000001/sig0000015a )
);
XORCY \blk00000001/blk00000085 (
.CI(\blk00000001/sig0000015c ),
.LI(\blk00000001/sig0000015b ),
.O(\blk00000001/sig0000016b )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000084 (
.I0(\blk00000001/sig00000182 ),
.I1(\blk00000001/sig000001e7 ),
.O(\blk00000001/sig00000159 )
);
MUXCY \blk00000001/blk00000083 (
.CI(\blk00000001/sig0000015a ),
.DI(\blk00000001/sig000001e7 ),
.S(\blk00000001/sig00000159 ),
.O(\blk00000001/sig00000158 )
);
XORCY \blk00000001/blk00000082 (
.CI(\blk00000001/sig0000015a ),
.LI(\blk00000001/sig00000159 ),
.O(\blk00000001/sig0000016c )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000081 (
.I0(\blk00000001/sig00000183 ),
.I1(\blk00000001/sig000001e8 ),
.O(\blk00000001/sig00000157 )
);
MUXCY \blk00000001/blk00000080 (
.CI(\blk00000001/sig00000158 ),
.DI(\blk00000001/sig000001e8 ),
.S(\blk00000001/sig00000157 ),
.O(\blk00000001/sig00000156 )
);
XORCY \blk00000001/blk0000007f (
.CI(\blk00000001/sig00000158 ),
.LI(\blk00000001/sig00000157 ),
.O(\blk00000001/sig0000016d )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk0000007e (
.I0(\blk00000001/sig00000184 ),
.I1(\blk00000001/sig000001e9 ),
.O(\blk00000001/sig00000155 )
);
MUXCY \blk00000001/blk0000007d (
.CI(\blk00000001/sig00000156 ),
.DI(\blk00000001/sig000001e9 ),
.S(\blk00000001/sig00000155 ),
.O(\blk00000001/sig00000154 )
);
XORCY \blk00000001/blk0000007c (
.CI(\blk00000001/sig00000156 ),
.LI(\blk00000001/sig00000155 ),
.O(\blk00000001/sig0000016e )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk0000007b (
.I0(\blk00000001/sig00000185 ),
.I1(\blk00000001/sig000001ea ),
.O(\blk00000001/sig00000153 )
);
MUXCY \blk00000001/blk0000007a (
.CI(\blk00000001/sig00000154 ),
.DI(\blk00000001/sig000001ea ),
.S(\blk00000001/sig00000153 ),
.O(\blk00000001/sig00000152 )
);
XORCY \blk00000001/blk00000079 (
.CI(\blk00000001/sig00000154 ),
.LI(\blk00000001/sig00000153 ),
.O(\blk00000001/sig0000016f )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000078 (
.I0(\blk00000001/sig00000186 ),
.I1(\blk00000001/sig000001eb ),
.O(\blk00000001/sig00000151 )
);
MUXCY \blk00000001/blk00000077 (
.CI(\blk00000001/sig00000152 ),
.DI(\blk00000001/sig000001eb ),
.S(\blk00000001/sig00000151 ),
.O(\blk00000001/sig00000150 )
);
XORCY \blk00000001/blk00000076 (
.CI(\blk00000001/sig00000152 ),
.LI(\blk00000001/sig00000151 ),
.O(\blk00000001/sig00000170 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000075 (
.I0(\blk00000001/sig00000187 ),
.I1(\blk00000001/sig000001ec ),
.O(\blk00000001/sig0000014f )
);
MUXCY \blk00000001/blk00000074 (
.CI(\blk00000001/sig00000150 ),
.DI(\blk00000001/sig000001ec ),
.S(\blk00000001/sig0000014f ),
.O(\blk00000001/sig0000014e )
);
XORCY \blk00000001/blk00000073 (
.CI(\blk00000001/sig00000150 ),
.LI(\blk00000001/sig0000014f ),
.O(\blk00000001/sig00000171 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000072 (
.I0(\blk00000001/sig00000188 ),
.I1(\blk00000001/sig000001ed ),
.O(\blk00000001/sig0000014d )
);
MUXCY \blk00000001/blk00000071 (
.CI(\blk00000001/sig0000014e ),
.DI(\blk00000001/sig000001ed ),
.S(\blk00000001/sig0000014d ),
.O(\blk00000001/sig0000014c )
);
XORCY \blk00000001/blk00000070 (
.CI(\blk00000001/sig0000014e ),
.LI(\blk00000001/sig0000014d ),
.O(\blk00000001/sig00000172 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk0000006f (
.I0(\blk00000001/sig00000189 ),
.I1(\blk00000001/sig000001ee ),
.O(\blk00000001/sig0000014b )
);
MUXCY \blk00000001/blk0000006e (
.CI(\blk00000001/sig0000014c ),
.DI(\blk00000001/sig000001ee ),
.S(\blk00000001/sig0000014b ),
.O(\blk00000001/sig0000014a )
);
XORCY \blk00000001/blk0000006d (
.CI(\blk00000001/sig0000014c ),
.LI(\blk00000001/sig0000014b ),
.O(\blk00000001/sig00000173 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk0000006c (
.I0(\blk00000001/sig000001ef ),
.I1(\blk00000001/sig0000018a ),
.O(\blk00000001/sig00000149 )
);
MUXCY \blk00000001/blk0000006b (
.CI(\blk00000001/sig0000014a ),
.DI(\blk00000001/sig000001ef ),
.S(\blk00000001/sig00000149 ),
.O(\blk00000001/sig00000148 )
);
XORCY \blk00000001/blk0000006a (
.CI(\blk00000001/sig0000014a ),
.LI(\blk00000001/sig00000149 ),
.O(\blk00000001/sig00000174 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000069 (
.I0(\blk00000001/sig000001f0 ),
.I1(\blk00000001/sig0000018b ),
.O(\blk00000001/sig00000147 )
);
MUXCY \blk00000001/blk00000068 (
.CI(\blk00000001/sig00000148 ),
.DI(\blk00000001/sig000001f0 ),
.S(\blk00000001/sig00000147 ),
.O(\blk00000001/sig00000146 )
);
XORCY \blk00000001/blk00000067 (
.CI(\blk00000001/sig00000148 ),
.LI(\blk00000001/sig00000147 ),
.O(\blk00000001/sig00000175 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000066 (
.I0(\blk00000001/sig000001f1 ),
.I1(\blk00000001/sig0000018c ),
.O(\blk00000001/sig00000145 )
);
MUXCY \blk00000001/blk00000065 (
.CI(\blk00000001/sig00000146 ),
.DI(\blk00000001/sig000001f1 ),
.S(\blk00000001/sig00000145 ),
.O(\blk00000001/sig00000144 )
);
XORCY \blk00000001/blk00000064 (
.CI(\blk00000001/sig00000146 ),
.LI(\blk00000001/sig00000145 ),
.O(\blk00000001/sig00000176 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000063 (
.I0(\blk00000001/sig000001f1 ),
.I1(\blk00000001/sig0000018d ),
.O(\blk00000001/sig00000143 )
);
MUXCY \blk00000001/blk00000062 (
.CI(\blk00000001/sig00000144 ),
.DI(\blk00000001/sig000001f1 ),
.S(\blk00000001/sig00000143 ),
.O(\blk00000001/sig00000142 )
);
XORCY \blk00000001/blk00000061 (
.CI(\blk00000001/sig00000144 ),
.LI(\blk00000001/sig00000143 ),
.O(\blk00000001/sig00000177 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000060 (
.I0(\blk00000001/sig000001f1 ),
.I1(\blk00000001/sig0000018e ),
.O(\blk00000001/sig00000141 )
);
MUXCY \blk00000001/blk0000005f (
.CI(\blk00000001/sig00000142 ),
.DI(\blk00000001/sig000001f1 ),
.S(\blk00000001/sig00000141 ),
.O(\blk00000001/sig00000140 )
);
XORCY \blk00000001/blk0000005e (
.CI(\blk00000001/sig00000142 ),
.LI(\blk00000001/sig00000141 ),
.O(\blk00000001/sig00000178 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk0000005d (
.I0(\blk00000001/sig000001f1 ),
.I1(\blk00000001/sig0000018f ),
.O(\blk00000001/sig0000013f )
);
MUXCY \blk00000001/blk0000005c (
.CI(\blk00000001/sig00000140 ),
.DI(\blk00000001/sig000001f1 ),
.S(\blk00000001/sig0000013f ),
.O(\blk00000001/sig0000013e )
);
XORCY \blk00000001/blk0000005b (
.CI(\blk00000001/sig00000140 ),
.LI(\blk00000001/sig0000013f ),
.O(\blk00000001/sig00000179 )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk0000005a (
.I0(\blk00000001/sig000001f1 ),
.I1(\blk00000001/sig00000190 ),
.O(\blk00000001/sig0000013d )
);
MUXCY \blk00000001/blk00000059 (
.CI(\blk00000001/sig0000013e ),
.DI(\blk00000001/sig000001f1 ),
.S(\blk00000001/sig0000013d ),
.O(\blk00000001/sig0000013c )
);
XORCY \blk00000001/blk00000058 (
.CI(\blk00000001/sig0000013e ),
.LI(\blk00000001/sig0000013d ),
.O(\blk00000001/sig0000017a )
);
LUT2 #(
.INIT ( 4'h9 ))
\blk00000001/blk00000057 (
.I0(\blk00000001/sig000001f1 ),
.I1(\blk00000001/sig00000191 ),
.O(\blk00000001/sig0000013b )
);
XORCY \blk00000001/blk00000056 (
.CI(\blk00000001/sig0000013c ),
.LI(\blk00000001/sig0000013b ),
.O(\blk00000001/sig0000017b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000055 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001d7 ),
.Q(\blk00000001/sig00000133 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000054 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001d6 ),
.Q(\blk00000001/sig00000134 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000053 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001d5 ),
.Q(\blk00000001/sig00000135 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000052 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001d4 ),
.Q(\blk00000001/sig00000136 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000051 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001d3 ),
.Q(\blk00000001/sig00000137 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000050 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001d2 ),
.Q(\blk00000001/sig00000138 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000004f (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001d1 ),
.Q(\blk00000001/sig00000139 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000004e (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000001d0 ),
.Q(\blk00000001/sig0000013a )
);
FDS #(
.INIT ( 1'b0 ))
\blk00000001/blk0000004d (
.C(aclk),
.D(\blk00000001/sig00000112 ),
.S(aclken),
.Q(\blk00000001/sig00000112 )
);
DSP48E1 #(
.ACASCREG ( 1 ),
.ADREG ( 0 ),
.ALUMODEREG ( 0 ),
.AREG ( 1 ),
.AUTORESET_PATDET ( "NO_RESET" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 1 ),
.BREG ( 1 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 0 ),
.CARRYINSELREG ( 0 ),
.CREG ( 1 ),
.DREG ( 0 ),
.INMODEREG ( 0 ),
.MASK ( 48'h000000000000 ),
.MREG ( 1 ),
.OPMODEREG ( 0 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.USE_DPORT ( 0 ),
.USE_MULT ( "MULTIPLY" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ))
\blk00000001/blk0000004c (
.PATTERNBDETECT(\NLW_blk00000001/blk0000004c_PATTERNBDETECT_UNCONNECTED ),
.RSTC(\blk00000001/sig000001d8 ),
.CEB1(\blk00000001/sig000001d8 ),
.CEAD(\blk00000001/sig000001d8 ),
.MULTSIGNOUT(\NLW_blk00000001/blk0000004c_MULTSIGNOUT_UNCONNECTED ),
.CEC(aclken),
.RSTM(\blk00000001/sig000001d8 ),
.MULTSIGNIN(\blk00000001/sig000001d8 ),
.CEB2(aclken),
.RSTCTRL(\blk00000001/sig000001d8 ),
.CEP(aclken),
.CARRYCASCOUT(\NLW_blk00000001/blk0000004c_CARRYCASCOUT_UNCONNECTED ),
.RSTA(\blk00000001/sig000001d8 ),
.CECARRYIN(\blk00000001/sig000001d8 ),
.UNDERFLOW(\NLW_blk00000001/blk0000004c_UNDERFLOW_UNCONNECTED ),
.PATTERNDETECT(\NLW_blk00000001/blk0000004c_PATTERNDETECT_UNCONNECTED ),
.RSTALUMODE(\blk00000001/sig000001d8 ),
.RSTALLCARRYIN(\blk00000001/sig000001d8 ),
.CED(\blk00000001/sig000001d8 ),
.RSTD(\blk00000001/sig000001d8 ),
.CEALUMODE(\blk00000001/sig000001d8 ),
.CEA2(aclken),
.CLK(aclk),
.CEA1(\blk00000001/sig000001d8 ),
.RSTB(\blk00000001/sig000001d8 ),
.OVERFLOW(\NLW_blk00000001/blk0000004c_OVERFLOW_UNCONNECTED ),
.CECTRL(\blk00000001/sig000001d8 ),
.CEM(aclken),
.CARRYIN(\blk00000001/sig000001d8 ),
.CARRYCASCIN(\blk00000001/sig000001d8 ),
.RSTINMODE(\blk00000001/sig000001d8 ),
.CEINMODE(\blk00000001/sig000001d8 ),
.RSTP(\blk00000001/sig000001d8 ),
.ACOUT({\NLW_blk00000001/blk0000004c_ACOUT<29>_UNCONNECTED , \NLW_blk00000001/blk0000004c_ACOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_ACOUT<27>_UNCONNECTED , \NLW_blk00000001/blk0000004c_ACOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_ACOUT<25>_UNCONNECTED , \NLW_blk00000001/blk0000004c_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_ACOUT<23>_UNCONNECTED , \NLW_blk00000001/blk0000004c_ACOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_ACOUT<21>_UNCONNECTED , \NLW_blk00000001/blk0000004c_ACOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_ACOUT<19>_UNCONNECTED , \NLW_blk00000001/blk0000004c_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_ACOUT<17>_UNCONNECTED , \NLW_blk00000001/blk0000004c_ACOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_ACOUT<15>_UNCONNECTED , \NLW_blk00000001/blk0000004c_ACOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_ACOUT<13>_UNCONNECTED , \NLW_blk00000001/blk0000004c_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_ACOUT<11>_UNCONNECTED , \NLW_blk00000001/blk0000004c_ACOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_ACOUT<9>_UNCONNECTED , \NLW_blk00000001/blk0000004c_ACOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_ACOUT<7>_UNCONNECTED , \NLW_blk00000001/blk0000004c_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_ACOUT<5>_UNCONNECTED , \NLW_blk00000001/blk0000004c_ACOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_ACOUT<3>_UNCONNECTED , \NLW_blk00000001/blk0000004c_ACOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_ACOUT<1>_UNCONNECTED , \NLW_blk00000001/blk0000004c_ACOUT<0>_UNCONNECTED }),
.OPMODE({\blk00000001/sig000001d8 , \blk00000001/sig00000132 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 ,
\blk00000001/sig000001d8 , \blk00000001/sig00000132 }),
.PCIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.ALUMODE({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.C({\blk00000001/sig00000112 , \blk00000001/sig00000112 , \blk00000001/sig00000112 , \blk00000001/sig00000112 , \blk00000001/sig00000112 ,
\blk00000001/sig00000112 , \blk00000001/sig00000112 , \blk00000001/sig00000112 , \blk00000001/sig00000112 , \blk00000001/sig00000112 ,
\blk00000001/sig00000112 , \blk00000001/sig00000112 , \blk00000001/sig00000112 , \blk00000001/sig00000112 , \blk00000001/sig00000112 ,
\blk00000001/sig00000112 , \blk00000001/sig00000112 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig00000112 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.CARRYOUT({\NLW_blk00000001/blk0000004c_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000001/blk0000004c_CARRYOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000001/blk0000004c_CARRYOUT<0>_UNCONNECTED }),
.INMODE({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.BCIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.B({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig0000011a , \blk00000001/sig00000119 , \blk00000001/sig00000118 , \blk00000001/sig00000117 , \blk00000001/sig00000116 ,
\blk00000001/sig00000115 , \blk00000001/sig00000114 , \blk00000001/sig00000113 }),
.BCOUT({\NLW_blk00000001/blk0000004c_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk0000004c_BCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk0000004c_BCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk0000004c_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk0000004c_BCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk0000004c_BCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk0000004c_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk0000004c_BCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk0000004c_BCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk0000004c_BCOUT<0>_UNCONNECTED }),
.D({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.P({\NLW_blk00000001/blk0000004c_P<47>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<46>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_P<45>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<44>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<43>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_P<42>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<41>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<40>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_P<39>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<38>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<37>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_P<36>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<35>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_P<33>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<32>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_P<30>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<29>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_P<27>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<26>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<25>_UNCONNECTED ,
\blk00000001/sig0000008f , \blk00000001/sig0000008e , \blk00000001/sig0000008d , \blk00000001/sig0000008c , \blk00000001/sig0000008b ,
\blk00000001/sig0000008a , \blk00000001/sig00000089 , \blk00000001/sig00000088 , \blk00000001/sig00000087 , \blk00000001/sig00000086 ,
\blk00000001/sig00000085 , \blk00000001/sig00000084 , \blk00000001/sig00000083 , \blk00000001/sig00000082 , \blk00000001/sig00000081 ,
\blk00000001/sig00000080 , \blk00000001/sig0000007f , \blk00000001/sig0000007e , \blk00000001/sig0000007d , \blk00000001/sig0000007c ,
\blk00000001/sig0000007b , \blk00000001/sig0000007a , \NLW_blk00000001/blk0000004c_P<2>_UNCONNECTED , \NLW_blk00000001/blk0000004c_P<1>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_P<0>_UNCONNECTED }),
.A({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig00000132 , \blk00000001/sig00000131 , \blk00000001/sig00000130 , \blk00000001/sig0000012f ,
\blk00000001/sig0000012e , \blk00000001/sig0000012d , \blk00000001/sig0000012c , \blk00000001/sig0000012b , \blk00000001/sig0000012a ,
\blk00000001/sig00000129 , \blk00000001/sig00000128 , \blk00000001/sig00000127 , \blk00000001/sig00000126 , \blk00000001/sig00000125 ,
\blk00000001/sig00000124 , \blk00000001/sig00000123 , \blk00000001/sig00000122 , \blk00000001/sig00000121 , \blk00000001/sig00000120 ,
\blk00000001/sig0000011f , \blk00000001/sig0000011e , \blk00000001/sig0000011d , \blk00000001/sig0000011c , \blk00000001/sig0000011b }),
.PCOUT({\NLW_blk00000001/blk0000004c_PCOUT<47>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<46>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<45>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<44>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<43>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<42>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<41>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<40>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<39>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<38>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<37>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<36>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<35>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<34>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<33>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<32>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<31>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<29>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<27>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<25>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<23>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<21>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<19>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000004c_PCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk0000004c_PCOUT<0>_UNCONNECTED }),
.ACIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.CARRYINSEL({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000004b (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000c0 ),
.Q(\blk00000001/sig00000113 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000004a (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000c1 ),
.Q(\blk00000001/sig00000114 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000049 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000c2 ),
.Q(\blk00000001/sig00000115 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000048 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000c3 ),
.Q(\blk00000001/sig00000116 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000047 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000c4 ),
.Q(\blk00000001/sig00000117 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000046 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000c5 ),
.Q(\blk00000001/sig00000118 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000045 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000c6 ),
.Q(\blk00000001/sig00000119 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000044 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000c7 ),
.Q(\blk00000001/sig0000011a )
);
DSP48E1 #(
.ACASCREG ( 1 ),
.ADREG ( 1 ),
.ALUMODEREG ( 0 ),
.AREG ( 1 ),
.AUTORESET_PATDET ( "NO_RESET" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 2 ),
.BREG ( 2 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 0 ),
.CARRYINSELREG ( 0 ),
.CREG ( 0 ),
.DREG ( 0 ),
.INMODEREG ( 0 ),
.MASK ( 48'h3FFFFFFFFFFF ),
.MREG ( 1 ),
.OPMODEREG ( 0 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.USE_DPORT ( 1 ),
.USE_MULT ( "MULTIPLY" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ))
\blk00000001/blk00000043 (
.PATTERNBDETECT(\NLW_blk00000001/blk00000043_PATTERNBDETECT_UNCONNECTED ),
.RSTC(\blk00000001/sig000001d8 ),
.CEB1(aclken),
.CEAD(aclken),
.MULTSIGNOUT(\NLW_blk00000001/blk00000043_MULTSIGNOUT_UNCONNECTED ),
.CEC(\blk00000001/sig000001d8 ),
.RSTM(\blk00000001/sig000001d8 ),
.MULTSIGNIN(\blk00000001/sig000001d8 ),
.CEB2(aclken),
.RSTCTRL(\blk00000001/sig000001d8 ),
.CEP(aclken),
.CARRYCASCOUT(\NLW_blk00000001/blk00000043_CARRYCASCOUT_UNCONNECTED ),
.RSTA(\blk00000001/sig000001d8 ),
.CECARRYIN(\blk00000001/sig000001d8 ),
.UNDERFLOW(\NLW_blk00000001/blk00000043_UNDERFLOW_UNCONNECTED ),
.PATTERNDETECT(\NLW_blk00000001/blk00000043_PATTERNDETECT_UNCONNECTED ),
.RSTALUMODE(\blk00000001/sig000001d8 ),
.RSTALLCARRYIN(\blk00000001/sig000001d8 ),
.CED(\blk00000001/sig000001d8 ),
.RSTD(\blk00000001/sig000001d8 ),
.CEALUMODE(\blk00000001/sig000001d8 ),
.CEA2(aclken),
.CLK(aclk),
.CEA1(\blk00000001/sig000001d8 ),
.RSTB(\blk00000001/sig000001d8 ),
.OVERFLOW(\NLW_blk00000001/blk00000043_OVERFLOW_UNCONNECTED ),
.CECTRL(\blk00000001/sig000001d8 ),
.CEM(aclken),
.CARRYIN(\blk00000001/sig000001d8 ),
.CARRYCASCIN(\blk00000001/sig000001d8 ),
.RSTINMODE(\blk00000001/sig000001d8 ),
.CEINMODE(\blk00000001/sig000001d8 ),
.RSTP(\blk00000001/sig000001d8 ),
.ACOUT({\NLW_blk00000001/blk00000043_ACOUT<29>_UNCONNECTED , \NLW_blk00000001/blk00000043_ACOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_ACOUT<27>_UNCONNECTED , \NLW_blk00000001/blk00000043_ACOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_ACOUT<25>_UNCONNECTED , \NLW_blk00000001/blk00000043_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_ACOUT<23>_UNCONNECTED , \NLW_blk00000001/blk00000043_ACOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_ACOUT<21>_UNCONNECTED , \NLW_blk00000001/blk00000043_ACOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_ACOUT<19>_UNCONNECTED , \NLW_blk00000001/blk00000043_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_ACOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000043_ACOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_ACOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000043_ACOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_ACOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000043_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_ACOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000043_ACOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_ACOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000043_ACOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_ACOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000043_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_ACOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000043_ACOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_ACOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000043_ACOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_ACOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000043_ACOUT<0>_UNCONNECTED }),
.OPMODE({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig00000132 ,
\blk00000001/sig000001d8 , \blk00000001/sig00000132 }),
.PCIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.ALUMODE({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.C({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.CARRYOUT({\NLW_blk00000001/blk00000043_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000043_CARRYOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000043_CARRYOUT<0>_UNCONNECTED }),
.INMODE({\blk00000001/sig000001d8 , \blk00000001/sig00000132 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.BCIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.B({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig00000111 , \blk00000001/sig00000110 , \blk00000001/sig0000010f , \blk00000001/sig0000010e , \blk00000001/sig0000010d ,
\blk00000001/sig0000010c , \blk00000001/sig0000010b , \blk00000001/sig0000010a }),
.BCOUT({\NLW_blk00000001/blk00000043_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000043_BCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000043_BCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000043_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000043_BCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000043_BCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000043_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000043_BCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000043_BCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000043_BCOUT<0>_UNCONNECTED }),
.D({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.P({\NLW_blk00000001/blk00000043_P<47>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<46>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_P<45>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<44>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<43>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_P<42>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<41>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<40>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_P<39>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<38>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<37>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_P<36>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<35>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_P<33>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<32>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<31>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_P<30>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<29>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_P<27>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<26>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<25>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_P<24>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<23>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_P<21>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<20>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<19>_UNCONNECTED ,
\blk00000001/sig000000d3 , \blk00000001/sig000000d2 , \blk00000001/sig000000d1 , \blk00000001/sig000000d0 ,
\NLW_blk00000001/blk00000043_P<14>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<13>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_P<11>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<10>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<9>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_P<8>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<7>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<6>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_P<5>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<4>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<3>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_P<2>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<1>_UNCONNECTED , \NLW_blk00000001/blk00000043_P<0>_UNCONNECTED }),
.A({\blk00000001/sig000000dd , \blk00000001/sig000000dd , \blk00000001/sig000000dd , \blk00000001/sig000000dd , \blk00000001/sig000000dd ,
\blk00000001/sig000000dd , \blk00000001/sig000000dd , \blk00000001/sig000000dd , \blk00000001/sig000000dd , \blk00000001/sig000000dd ,
\blk00000001/sig000000dd , \blk00000001/sig000000dd , \blk00000001/sig000000dd , \blk00000001/sig000000dd , \blk00000001/sig000000dd ,
\blk00000001/sig000000dd , \blk00000001/sig000000dd , \blk00000001/sig000000dd , \blk00000001/sig000000dd , \blk00000001/sig000000dd ,
\blk00000001/sig000000dd , \blk00000001/sig000000dc , \blk00000001/sig000000db , \blk00000001/sig000000da , \blk00000001/sig000000d9 ,
\blk00000001/sig000000d8 , \blk00000001/sig000000d7 , \blk00000001/sig000000d6 , \blk00000001/sig000000d5 , \blk00000001/sig000000d4 }),
.PCOUT({\NLW_blk00000001/blk00000043_PCOUT<47>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<46>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<45>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<44>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<43>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<42>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<41>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<40>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<39>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<38>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<37>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<36>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<35>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<34>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<33>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<32>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<31>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<29>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<27>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<25>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<23>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<21>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<19>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000043_PCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000043_PCOUT<0>_UNCONNECTED }),
.ACIN({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 ,
\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 }),
.CARRYINSEL({\blk00000001/sig000001d8 , \blk00000001/sig000001d8 , \blk00000001/sig000001d8 })
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000003a (
.C(aclk),
.CE(aclken),
.D(s_axis_a_tdata[20]),
.Q(\blk00000001/sig000000fa )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000039 (
.C(aclk),
.CE(aclken),
.D(s_axis_a_tdata[21]),
.Q(\blk00000001/sig000000fb )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000038 (
.C(aclk),
.CE(aclken),
.D(s_axis_a_tdata[22]),
.Q(\blk00000001/sig000000fc )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000037 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000f6 ),
.Q(\blk00000001/sig000000fd )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000036 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000f7 ),
.Q(\blk00000001/sig000000fe )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000035 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000f8 ),
.Q(\blk00000001/sig000000ff )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000034 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000f9 ),
.Q(\blk00000001/sig00000100 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000033 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000ed ),
.Q(\blk00000001/sig00000109 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000032 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000ee ),
.Q(\blk00000001/sig00000108 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000031 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000ef ),
.Q(\blk00000001/sig00000107 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000030 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000f0 ),
.Q(\blk00000001/sig00000106 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000002f (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000f1 ),
.Q(\blk00000001/sig00000105 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000002e (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000f2 ),
.Q(\blk00000001/sig00000104 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000002d (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000f3 ),
.Q(\blk00000001/sig00000103 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000002c (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000f4 ),
.Q(\blk00000001/sig00000102 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000002b (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000f5 ),
.Q(\blk00000001/sig00000101 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000002a (
.I0(\blk00000001/sig000000d0 ),
.I1(\blk00000001/sig000000c8 ),
.O(\blk00000001/sig000000bf )
);
MUXCY \blk00000001/blk00000029 (
.CI(\blk00000001/sig000001d8 ),
.DI(\blk00000001/sig000000d0 ),
.S(\blk00000001/sig000000bf ),
.O(\blk00000001/sig000000be )
);
XORCY \blk00000001/blk00000028 (
.CI(\blk00000001/sig000001d8 ),
.LI(\blk00000001/sig000000bf ),
.O(\blk00000001/sig000000c0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000027 (
.I0(\blk00000001/sig000000d1 ),
.I1(\blk00000001/sig000000c9 ),
.O(\blk00000001/sig000000bd )
);
MUXCY \blk00000001/blk00000026 (
.CI(\blk00000001/sig000000be ),
.DI(\blk00000001/sig000000d1 ),
.S(\blk00000001/sig000000bd ),
.O(\blk00000001/sig000000bc )
);
XORCY \blk00000001/blk00000025 (
.CI(\blk00000001/sig000000be ),
.LI(\blk00000001/sig000000bd ),
.O(\blk00000001/sig000000c1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000024 (
.I0(\blk00000001/sig000000d2 ),
.I1(\blk00000001/sig000000ca ),
.O(\blk00000001/sig000000bb )
);
MUXCY \blk00000001/blk00000023 (
.CI(\blk00000001/sig000000bc ),
.DI(\blk00000001/sig000000d2 ),
.S(\blk00000001/sig000000bb ),
.O(\blk00000001/sig000000ba )
);
XORCY \blk00000001/blk00000022 (
.CI(\blk00000001/sig000000bc ),
.LI(\blk00000001/sig000000bb ),
.O(\blk00000001/sig000000c2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000021 (
.I0(\blk00000001/sig000000d3 ),
.I1(\blk00000001/sig000000cb ),
.O(\blk00000001/sig000000b9 )
);
MUXCY \blk00000001/blk00000020 (
.CI(\blk00000001/sig000000ba ),
.DI(\blk00000001/sig000000d3 ),
.S(\blk00000001/sig000000b9 ),
.O(\blk00000001/sig000000b8 )
);
XORCY \blk00000001/blk0000001f (
.CI(\blk00000001/sig000000ba ),
.LI(\blk00000001/sig000000b9 ),
.O(\blk00000001/sig000000c3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000001e (
.I0(\blk00000001/sig000000d3 ),
.I1(\blk00000001/sig000000cc ),
.O(\blk00000001/sig000000b7 )
);
MUXCY \blk00000001/blk0000001d (
.CI(\blk00000001/sig000000b8 ),
.DI(\blk00000001/sig000000d3 ),
.S(\blk00000001/sig000000b7 ),
.O(\blk00000001/sig000000b6 )
);
XORCY \blk00000001/blk0000001c (
.CI(\blk00000001/sig000000b8 ),
.LI(\blk00000001/sig000000b7 ),
.O(\blk00000001/sig000000c4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000001b (
.I0(\blk00000001/sig000000d3 ),
.I1(\blk00000001/sig000000cd ),
.O(\blk00000001/sig000000b5 )
);
MUXCY \blk00000001/blk0000001a (
.CI(\blk00000001/sig000000b6 ),
.DI(\blk00000001/sig000000d3 ),
.S(\blk00000001/sig000000b5 ),
.O(\blk00000001/sig000000b4 )
);
XORCY \blk00000001/blk00000019 (
.CI(\blk00000001/sig000000b6 ),
.LI(\blk00000001/sig000000b5 ),
.O(\blk00000001/sig000000c5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000018 (
.I0(\blk00000001/sig000000d3 ),
.I1(\blk00000001/sig000000ce ),
.O(\blk00000001/sig000000b3 )
);
MUXCY \blk00000001/blk00000017 (
.CI(\blk00000001/sig000000b4 ),
.DI(\blk00000001/sig000000d3 ),
.S(\blk00000001/sig000000b3 ),
.O(\blk00000001/sig000000b2 )
);
XORCY \blk00000001/blk00000016 (
.CI(\blk00000001/sig000000b4 ),
.LI(\blk00000001/sig000000b3 ),
.O(\blk00000001/sig000000c6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000015 (
.I0(\blk00000001/sig000000d3 ),
.I1(\blk00000001/sig000000cf ),
.O(\blk00000001/sig000000b1 )
);
XORCY \blk00000001/blk00000014 (
.CI(\blk00000001/sig000000b2 ),
.LI(\blk00000001/sig000000b1 ),
.O(\blk00000001/sig000000c7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000013 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000a4 ),
.Q(\blk00000001/sig00000090 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000012 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000a5 ),
.Q(\blk00000001/sig00000092 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000011 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000009c ),
.Q(\blk00000001/sig00000093 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000010 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000009d ),
.Q(\blk00000001/sig00000094 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000f (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000009e ),
.Q(\blk00000001/sig00000095 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000e (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig0000009f ),
.Q(\blk00000001/sig00000096 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000d (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000a0 ),
.Q(\blk00000001/sig00000097 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000c (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000a1 ),
.Q(\blk00000001/sig00000098 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000b (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000a2 ),
.Q(\blk00000001/sig00000099 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000000a (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000a3 ),
.Q(\blk00000001/sig0000009a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000009 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000aa ),
.Q(\blk00000001/sig000000b0 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000008 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000a6 ),
.Q(\blk00000001/sig000000ae )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000007 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000a7 ),
.Q(\blk00000001/sig000000af )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000006 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000ad ),
.Q(\blk00000001/sig000000a9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000005 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000ac ),
.Q(\blk00000001/sig000000a8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000004 (
.C(aclk),
.CE(aclken),
.D(\blk00000001/sig000000ab ),
.Q(\blk00000001/sig000000aa )
);
GND \blk00000001/blk00000003 (
.G(\blk00000001/sig000001d8 )
);
VCC \blk00000001/blk00000002 (
.P(\blk00000001/sig00000132 )
);
DSP48E1 #(
.USE_DPORT ( 0 ),
.ADREG ( 0 ),
.AREG ( 1 ),
.ACASCREG ( 1 ),
.BREG ( 1 ),
.BCASCREG ( 1 ),
.CREG ( 0 ),
.MREG ( 1 ),
.PREG ( 1 ),
.CARRYINREG ( 0 ),
.OPMODEREG ( 0 ),
.ALUMODEREG ( 0 ),
.CARRYINSELREG ( 0 ),
.INMODEREG ( 0 ),
.USE_MULT ( "MULTIPLY" ),
.A_INPUT ( "DIRECT" ),
.B_INPUT ( "DIRECT" ),
.DREG ( 0 ),
.SEL_PATTERN ( "PATTERN" ),
.MASK ( 48'h3fffffffffff ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.PATTERN ( 48'h000000000000 ),
.USE_SIMD ( "ONE48" ),
.AUTORESET_PATDET ( "NO_RESET" ),
.SEL_MASK ( "MASK" ))
\blk00000001/blk0000003b/blk0000003e (
.PATTERNBDETECT(\NLW_blk00000001/blk0000003b/blk0000003e_PATTERNBDETECT_UNCONNECTED ),
.RSTC(\blk00000001/blk0000003b/sig000002f5 ),
.CEB1(\blk00000001/blk0000003b/sig000002f5 ),
.CEAD(\blk00000001/blk0000003b/sig000002f5 ),
.MULTSIGNOUT(\NLW_blk00000001/blk0000003b/blk0000003e_MULTSIGNOUT_UNCONNECTED ),
.CEC(\blk00000001/blk0000003b/sig000002f5 ),
.RSTM(\blk00000001/blk0000003b/sig000002f5 ),
.MULTSIGNIN(\NLW_blk00000001/blk0000003b/blk0000003e_MULTSIGNIN_UNCONNECTED ),
.CEB2(aclken),
.RSTCTRL(\blk00000001/blk0000003b/sig000002f5 ),
.CEP(aclken),
.CARRYCASCOUT(\NLW_blk00000001/blk0000003b/blk0000003e_CARRYCASCOUT_UNCONNECTED ),
.RSTA(\blk00000001/blk0000003b/sig000002f5 ),
.CECARRYIN(\blk00000001/blk0000003b/sig000002f5 ),
.UNDERFLOW(\NLW_blk00000001/blk0000003b/blk0000003e_UNDERFLOW_UNCONNECTED ),
.PATTERNDETECT(\NLW_blk00000001/blk0000003b/blk0000003e_PATTERNDETECT_UNCONNECTED ),
.RSTALUMODE(\blk00000001/blk0000003b/sig000002f5 ),
.RSTALLCARRYIN(\blk00000001/blk0000003b/sig000002f5 ),
.CED(\blk00000001/blk0000003b/sig000002f5 ),
.RSTD(\blk00000001/blk0000003b/sig000002f5 ),
.CEALUMODE(\blk00000001/blk0000003b/sig000002f5 ),
.CEA2(aclken),
.CLK(aclk),
.CEA1(\blk00000001/blk0000003b/sig000002f5 ),
.RSTB(\blk00000001/blk0000003b/sig000002f5 ),
.OVERFLOW(\NLW_blk00000001/blk0000003b/blk0000003e_OVERFLOW_UNCONNECTED ),
.CECTRL(\blk00000001/blk0000003b/sig000002f5 ),
.CEM(aclken),
.CARRYIN(\blk00000001/blk0000003b/sig000002f5 ),
.CARRYCASCIN(\NLW_blk00000001/blk0000003b/blk0000003e_CARRYCASCIN_UNCONNECTED ),
.RSTINMODE(\blk00000001/blk0000003b/sig000002f5 ),
.CEINMODE(\blk00000001/blk0000003b/sig000002f5 ),
.RSTP(\blk00000001/blk0000003b/sig000002f5 ),
.ACOUT({\NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<29>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<27>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<25>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<23>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<21>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<19>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<17>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<15>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<13>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<11>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<9>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<7>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<5>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<3>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<1>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACOUT<0>_UNCONNECTED }),
.OPMODE({\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f4 }),
.PCIN({\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<47>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<46>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<45>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<44>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<43>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<42>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<41>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<40>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<39>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<38>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<37>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<36>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<35>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<34>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<33>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<32>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<31>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<29>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<27>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<25>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<23>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<21>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<19>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<17>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<15>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<13>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<11>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<9>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<7>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<5>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<3>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCIN<1>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCIN<0>_UNCONNECTED }),
.ALUMODE({\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 }),
.C({\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 }),
.CARRYOUT({\NLW_blk00000001/blk0000003b/blk0000003e_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_CARRYOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_CARRYOUT<0>_UNCONNECTED }),
.INMODE({\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 }),
.BCIN({\NLW_blk00000001/blk0000003b/blk0000003e_BCIN<17>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCIN<15>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCIN<13>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCIN<11>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCIN<9>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCIN<7>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCIN<5>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCIN<3>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCIN<1>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCIN<0>_UNCONNECTED }),
.B({\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/sig00000132 , \blk00000001/sig000000fc ,
\blk00000001/sig000000fb , \blk00000001/sig000000fa , \blk00000001/sig00000100 , \blk00000001/sig000000ff , \blk00000001/sig000000fe ,
\blk00000001/sig000000fd , \blk00000001/sig00000132 , \blk00000001/sig00000132 }),
.BCOUT({\NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_BCOUT<0>_UNCONNECTED }),
.D({\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 }),
.P({\NLW_blk00000001/blk0000003b/blk0000003e_P<47>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_P<46>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_P<45>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_P<44>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_P<43>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_P<42>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_P<41>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_P<40>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_P<39>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_P<38>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_P<37>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_P<36>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_P<35>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_P<33>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_P<32>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_P<31>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_P<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_P<29>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_P<27>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_P<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_P<25>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_P<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_P<23>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_P<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_P<21>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_P<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_P<19>_UNCONNECTED , \blk00000001/blk0000003b/sig000002e1 , \blk00000001/sig000000ec ,
\blk00000001/sig000000eb , \blk00000001/sig000000ea , \blk00000001/sig000000e9 , \blk00000001/sig000000e8 , \blk00000001/sig000000e7 ,
\blk00000001/sig000000e6 , \blk00000001/sig000000e5 , \blk00000001/blk0000003b/sig000002ea , \blk00000001/blk0000003b/sig000002eb ,
\blk00000001/blk0000003b/sig000002ec , \blk00000001/blk0000003b/sig000002ed , \blk00000001/blk0000003b/sig000002ee ,
\blk00000001/blk0000003b/sig000002ef , \blk00000001/blk0000003b/sig000002f0 , \blk00000001/blk0000003b/sig000002f1 ,
\blk00000001/blk0000003b/sig000002f2 , \blk00000001/blk0000003b/sig000002f3 }),
.A({\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 ,
\blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f4 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 ,
\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/sig00000109 ,
\blk00000001/sig00000108 , \blk00000001/sig00000107 , \blk00000001/sig00000106 , \blk00000001/sig00000105 , \blk00000001/sig00000104 ,
\blk00000001/sig00000103 , \blk00000001/sig00000102 , \blk00000001/sig00000101 }),
.PCOUT({\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<47>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<46>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<45>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<44>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<43>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<42>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<41>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<40>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<39>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<38>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<37>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<36>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<35>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<34>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<33>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<32>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<31>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<29>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<27>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<25>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<23>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<21>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<19>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_PCOUT<0>_UNCONNECTED }),
.ACIN({\NLW_blk00000001/blk0000003b/blk0000003e_ACIN<29>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACIN<27>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACIN<25>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACIN<23>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACIN<21>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACIN<19>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACIN<17>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACIN<15>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACIN<13>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACIN<11>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACIN<9>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACIN<7>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACIN<5>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACIN<3>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000003b/blk0000003e_ACIN<1>_UNCONNECTED , \NLW_blk00000001/blk0000003b/blk0000003e_ACIN<0>_UNCONNECTED }),
.CARRYINSEL({\blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 , \blk00000001/blk0000003b/sig000002f5 })
);
GND \blk00000001/blk0000003b/blk0000003d (
.G(\blk00000001/blk0000003b/sig000002f5 )
);
VCC \blk00000001/blk0000003b/blk0000003c (
.P(\blk00000001/blk0000003b/sig000002f4 )
);
DSP48E1 #(
.USE_DPORT ( 0 ),
.ADREG ( 0 ),
.AREG ( 1 ),
.ACASCREG ( 1 ),
.BREG ( 1 ),
.BCASCREG ( 1 ),
.CREG ( 0 ),
.MREG ( 1 ),
.PREG ( 1 ),
.CARRYINREG ( 0 ),
.OPMODEREG ( 0 ),
.ALUMODEREG ( 0 ),
.CARRYINSELREG ( 0 ),
.INMODEREG ( 0 ),
.USE_MULT ( "MULTIPLY" ),
.A_INPUT ( "DIRECT" ),
.B_INPUT ( "DIRECT" ),
.DREG ( 0 ),
.SEL_PATTERN ( "PATTERN" ),
.MASK ( 48'h3fffffffffff ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.PATTERN ( 48'h000000000000 ),
.USE_SIMD ( "ONE48" ),
.AUTORESET_PATDET ( "NO_RESET" ),
.SEL_MASK ( "MASK" ))
\blk00000001/blk0000003f/blk00000042 (
.PATTERNBDETECT(\NLW_blk00000001/blk0000003f/blk00000042_PATTERNBDETECT_UNCONNECTED ),
.RSTC(\blk00000001/blk0000003f/sig00000313 ),
.CEB1(\blk00000001/blk0000003f/sig00000313 ),
.CEAD(\blk00000001/blk0000003f/sig00000313 ),
.MULTSIGNOUT(\NLW_blk00000001/blk0000003f/blk00000042_MULTSIGNOUT_UNCONNECTED ),
.CEC(\blk00000001/blk0000003f/sig00000313 ),
.RSTM(\blk00000001/blk0000003f/sig00000313 ),
.MULTSIGNIN(\NLW_blk00000001/blk0000003f/blk00000042_MULTSIGNIN_UNCONNECTED ),
.CEB2(aclken),
.RSTCTRL(\blk00000001/blk0000003f/sig00000313 ),
.CEP(aclken),
.CARRYCASCOUT(\NLW_blk00000001/blk0000003f/blk00000042_CARRYCASCOUT_UNCONNECTED ),
.RSTA(\blk00000001/blk0000003f/sig00000313 ),
.CECARRYIN(\blk00000001/blk0000003f/sig00000313 ),
.UNDERFLOW(\NLW_blk00000001/blk0000003f/blk00000042_UNDERFLOW_UNCONNECTED ),
.PATTERNDETECT(\NLW_blk00000001/blk0000003f/blk00000042_PATTERNDETECT_UNCONNECTED ),
.RSTALUMODE(\blk00000001/blk0000003f/sig00000313 ),
.RSTALLCARRYIN(\blk00000001/blk0000003f/sig00000313 ),
.CED(\blk00000001/blk0000003f/sig00000313 ),
.RSTD(\blk00000001/blk0000003f/sig00000313 ),
.CEALUMODE(\blk00000001/blk0000003f/sig00000313 ),
.CEA2(aclken),
.CLK(aclk),
.CEA1(\blk00000001/blk0000003f/sig00000313 ),
.RSTB(\blk00000001/blk0000003f/sig00000313 ),
.OVERFLOW(\NLW_blk00000001/blk0000003f/blk00000042_OVERFLOW_UNCONNECTED ),
.CECTRL(\blk00000001/blk0000003f/sig00000313 ),
.CEM(aclken),
.CARRYIN(\blk00000001/blk0000003f/sig00000313 ),
.CARRYCASCIN(\NLW_blk00000001/blk0000003f/blk00000042_CARRYCASCIN_UNCONNECTED ),
.RSTINMODE(\blk00000001/blk0000003f/sig00000313 ),
.CEINMODE(\blk00000001/blk0000003f/sig00000313 ),
.RSTP(\blk00000001/blk0000003f/sig00000313 ),
.ACOUT({\NLW_blk00000001/blk0000003f/blk00000042_ACOUT<29>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACOUT<27>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACOUT<25>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACOUT<23>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACOUT<21>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACOUT<19>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACOUT<17>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACOUT<15>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACOUT<13>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACOUT<11>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACOUT<9>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACOUT<7>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACOUT<5>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACOUT<3>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACOUT<1>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACOUT<0>_UNCONNECTED }),
.OPMODE({\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000312 }),
.PCIN({\NLW_blk00000001/blk0000003f/blk00000042_PCIN<47>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<46>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<45>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<44>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<43>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<42>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<41>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<40>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<39>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<38>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<37>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<36>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<35>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<34>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<33>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<32>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<31>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<29>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<27>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<25>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<23>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<21>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<19>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<17>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<15>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<13>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<11>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<9>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<7>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<5>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<3>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCIN<1>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCIN<0>_UNCONNECTED }),
.ALUMODE({\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 }),
.C({\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 }),
.CARRYOUT({\NLW_blk00000001/blk0000003f/blk00000042_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_CARRYOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_CARRYOUT<1>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_CARRYOUT<0>_UNCONNECTED }),
.INMODE({\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 }),
.BCIN({\NLW_blk00000001/blk0000003f/blk00000042_BCIN<17>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCIN<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCIN<15>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCIN<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCIN<13>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCIN<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCIN<11>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCIN<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCIN<9>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCIN<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCIN<7>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCIN<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCIN<5>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCIN<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCIN<3>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCIN<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCIN<1>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCIN<0>_UNCONNECTED }),
.B({\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/sig00000132 , \blk00000001/sig000000e4 , \blk00000001/sig000000e3 , \blk00000001/sig000000e2 ,
\blk00000001/sig000000e1 , \blk00000001/sig000000e0 , \blk00000001/sig000000df , \blk00000001/sig000000de }),
.BCOUT({\NLW_blk00000001/blk0000003f/blk00000042_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_BCOUT<0>_UNCONNECTED }),
.D({\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 }),
.P({\NLW_blk00000001/blk0000003f/blk00000042_P<47>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<46>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<45>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<44>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<43>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<42>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<41>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<40>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<39>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<38>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<37>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<36>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<35>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<34>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<33>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<32>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<31>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<29>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<27>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<25>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<23>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<21>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<19>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<17>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<15>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<13>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_P<11>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_P<10>_UNCONNECTED , \blk00000001/sig000000dd ,
\blk00000001/sig000000dc , \blk00000001/sig000000db , \blk00000001/sig000000da , \blk00000001/sig000000d9 , \blk00000001/sig000000d8 ,
\blk00000001/sig000000d7 , \blk00000001/sig000000d6 , \blk00000001/sig000000d5 , \blk00000001/sig000000d4 }),
.A({\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 ,
\blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000312 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 ,
\blk00000001/blk0000003f/sig00000313 , \blk00000001/sig000000ec , \blk00000001/sig000000eb , \blk00000001/sig000000ea , \blk00000001/sig000000e9 ,
\blk00000001/sig000000e8 , \blk00000001/sig000000e7 , \blk00000001/sig000000e6 , \blk00000001/sig000000e5 }),
.PCOUT({\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<47>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<46>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<45>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<44>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<43>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<42>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<41>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<40>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<39>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<38>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<37>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<36>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<35>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<34>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<33>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<32>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<31>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<30>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<29>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<27>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<25>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<23>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<21>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<19>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_PCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_PCOUT<0>_UNCONNECTED }),
.ACIN({\NLW_blk00000001/blk0000003f/blk00000042_ACIN<29>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACIN<28>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACIN<27>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACIN<26>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACIN<25>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACIN<24>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACIN<23>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACIN<22>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACIN<21>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACIN<20>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACIN<19>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACIN<18>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACIN<17>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACIN<16>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACIN<15>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACIN<14>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACIN<13>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACIN<12>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACIN<11>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACIN<10>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACIN<9>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACIN<8>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACIN<7>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACIN<6>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACIN<5>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACIN<4>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACIN<3>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACIN<2>_UNCONNECTED ,
\NLW_blk00000001/blk0000003f/blk00000042_ACIN<1>_UNCONNECTED , \NLW_blk00000001/blk0000003f/blk00000042_ACIN<0>_UNCONNECTED }),
.CARRYINSEL({\blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 , \blk00000001/blk0000003f/sig00000313 })
);
GND \blk00000001/blk0000003f/blk00000041 (
.G(\blk00000001/blk0000003f/sig00000313 )
);
VCC \blk00000001/blk0000003f/blk00000040 (
.P(\blk00000001/blk0000003f/sig00000312 )
);
endmodule
|
//
// Designed by Qiang Wu
//
`timescale 1ns/1ps
`include "yf32_define.v"
`include "NF_2.1_defines.v"
`include "reg_defines_reference_router.v"
`include "registers.v"
module np_core
#(parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH=DATA_WIDTH/8,
parameter UDP_REG_SRC_WIDTH = 2,
parameter INPUT_ARBITER_STAGE_NUM = 2,
parameter IO_QUEUE_STAGE_NUM = 8'hff,
parameter NUM_OUTPUT_QUEUES = 8,
parameter NUM_IQ_BITS = 3,
parameter STAGE_NUM = 4,
parameter CPU_QUEUE_NUM = 0)
(// --- data path interface
output [DATA_WIDTH-1:0] out_data,
output [CTRL_WIDTH-1:0] out_ctrl,
output out_wr,
input out_rdy,
input [DATA_WIDTH-1:0] in_data,
input [CTRL_WIDTH-1:0] in_ctrl,
input in_wr,
output in_rdy,
// --- Register interface
input reg_req_in,
input reg_ack_in,
input reg_rd_wr_L_in,
input [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_in,
input [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_in,
input [UDP_REG_SRC_WIDTH-1:0] reg_src_in,
output reg_req_out,
output reg_ack_out,
output reg_rd_wr_L_out,
output [`UDP_REG_ADDR_WIDTH-1:0] reg_addr_out,
output [`CPCI_NF2_DATA_WIDTH-1:0] reg_data_out,
output [UDP_REG_SRC_WIDTH-1:0] reg_src_out,
// --- Misc
input clk,
input core_sp_clk,
input statemac_clk,
input reset,
//for monitor
// for security monitoring
output [31:0] instruction_sec_mon,
output [31:0] prog_counter_sec_mon,
output [31:0] ppu_mem_addr,
input packet_drop
);
assign reg_req_out = reg_req_in;
assign reg_ack_out = reg_ack_in;
assign reg_rd_wr_L_out = reg_rd_wr_L_in;
assign reg_addr_out = reg_addr_in;
assign reg_data_out = reg_data_in;
assign reg_src_out = reg_src_in;
wire [63:0] fc_out_data0;
wire [23:0] fc_out_pkt_route0;
wire fc_out_wr0;
wire fc_out_req0;
wire fc_out_ack0;
wire fc_out_bypass0;
wire [63:0] fc_out_data1;
wire [23:0] fc_out_pkt_route1;
wire fc_out_wr1;
wire fc_out_req1;
wire fc_out_ack1;
wire fc_out_bypass1;
wire [63:0] fc_out_data2;
wire [23:0] fc_out_pkt_route2;
wire fc_out_wr2;
wire fc_out_req2;
wire fc_out_ack2;
wire fc_out_bypass2;
wire [63:0] fc_out_data3;
wire [23:0] fc_out_pkt_route3;
wire fc_out_wr3;
wire fc_out_req3;
wire fc_out_ack3;
wire fc_out_bypass3;
wire [63:0] pg_out_data0;
wire [23:0] pg_out_pkt_route0;
wire pg_out_wr0;
wire pg_out_req0;
wire pg_out_ack0;
wire pg_out_bop0;
wire pg_out_eop0;
wire pg_out_rdy0;
wire pg_out_bypass0;
wire [63:0] pg_out_data1;
wire [23:0] pg_out_pkt_route1;
wire pg_out_wr1;
wire pg_out_req1;
wire pg_out_ack1;
wire pg_out_bop1;
wire pg_out_eop1;
wire pg_out_rdy1;
wire pg_out_bypass1;
wire [63:0] pg_out_data2;
wire [23:0] pg_out_pkt_route2;
wire pg_out_wr2;
wire pg_out_req2;
wire pg_out_ack2;
wire pg_out_bop2;
wire pg_out_eop2;
wire pg_out_rdy2;
wire pg_out_bypass2;
wire [63:0] pg_out_data3;
wire [23:0] pg_out_pkt_route3;
wire pg_out_wr3;
wire pg_out_req3;
wire pg_out_ack3;
wire pg_out_bop3;
wire pg_out_eop3;
wire pg_out_rdy3;
wire [3:0] four_bit_hash_output0,four_bit_hash_output0_cm,four_bit_hash_output0_ipv4;
wire [31:0] pc_input_hash_wire0,pc_input_hash_wire0_cm,pc_input_hash_wire0_ipv4;
wire new_inst_signal0,new_inst_signal0_cm,new_inst_signal0_ipv4;
wire [3:0] four_bit_hash_output1,four_bit_hash_output1_cm,four_bit_hash_output1_ipv4;
wire [31:0] pc_input_hash_wire1,pc_input_hash_wire1_cm,pc_input_hash_wire1_ipv4;
wire new_inst_signal1,new_inst_signal1_cm,new_inst_signal1_ipv4;
wire [3:0] four_bit_hash_output2,four_bit_hash_output2_cm,four_bit_hash_output2_ipv4;
wire [31:0] pc_input_hash_wire2,pc_input_hash_wire2_cm,pc_input_hash_wire2_ipv4;
wire new_inst_signal2,new_inst_signal2_cm,new_inst_signal2_ipv4;
wire [3:0] four_bit_hash_output3,four_bit_hash_output3_cm,four_bit_hash_output3_ipv4;
wire [31:0] pc_input_hash_wire3,pc_input_hash_wire3_cm,pc_input_hash_wire3_ipv4;
wire new_inst_signal3,new_inst_signal3_cm,new_inst_signal3_ipv4;
wire packet_drop_signal0_ipv4;
wire packet_drop_signal1_ipv4;
wire packet_drop_signal2_ipv4;
wire packet_drop_signal3_ipv4;
wire packet_drop_signal0_cm;
wire packet_drop_signal1_cm;
wire packet_drop_signal2_cm;
wire packet_drop_signal3_cm;
wire fc_out_protocol0;
wire fc_out_protocol1;
wire fc_out_protocol2;
wire fc_out_protocol3;
/*
wire [35:0] CONTROL0;
wire [239:0] TRIG0;
chipscope_icon_v1_03_a cs_icon (
.CONTROL0(CONTROL0)
);
chipscope_ila_v1_02_a cs_ila (
.CONTROL(CONTROL0),
.CLK(clk),
.TRIG0(TRIG0)
);
assign TRIG0[63:0] = fc_out_data0;
assign TRIG0[79:64] = fc_out_pkt_route0;
assign TRIG0[80] = fc_out_wr0;
assign TRIG0[81] = fc_out_req0;
assign TRIG0[82] = fc_out_ack0;
assign TRIG0[163:100] = pg_out_data3;
assign TRIG0[179:164] = pg_out_pkt_route3;
assign TRIG0[180] = pg_out_wr3;
assign TRIG0[181] = pg_out_req3;
assign TRIG0[182] = pg_out_ack3;
assign TRIG0[183] = pg_out_bop3;
assign TRIG0[184] = pg_out_eop3;
assign TRIG0[185] = pg_out_rdy3;
*/
wire [63:0] data01;
wire [23:0] pkt_route01;
wire wr01;
wire req01;
wire ack01;
wire bypass01;
wire [63:0] data10;
wire [23:0] pkt_route10;
wire wr10;
wire req10;
wire ack10;
wire bypass10;
wire [63:0] data02;
wire [23:0] pkt_route02;
wire wr02;
wire req02;
wire ack02;
wire bypass02;
wire [63:0] data20;
wire [23:0] pkt_route20;
wire wr20;
wire req20;
wire ack20;
wire bypass20;
wire [63:0] data13;
wire [23:0] pkt_route13;
wire wr13;
wire req13;
wire ack13;
wire bypass13;
wire [63:0] data31;
wire [23:0] pkt_route31;
wire wr31;
wire req31;
wire ack31;
wire bypass31;
wire [63:0] data23;
wire [23:0] pkt_route23;
wire wr23;
wire req23;
wire ack23;
wire bypass23;
wire [63:0] data32;
wire [23:0] pkt_route32;
wire wr32;
wire req32;
wire ack32;
wire bypass32;
wire [239:0] TRIG_IS0;
wire [239:0] TRIG_IS2;
wire [239:0] TRIG_OS0;
wire reset0;
wire reset1;
wire reset2;
wire reset3;
wire packet_drop_core_zero;
wire packet_drop_core_one;
wire packet_drop_core_two;
wire packet_drop_core_three;
wire cam_we;
wire [3:0] cam_wr_addr;
wire [31:0] cam_din;
wire cam_wr_ack;
flow_classification fc(
.out_data0 (fc_out_data0),
.out_pkt_route0 (fc_out_pkt_route0),
.out_wr0 (fc_out_wr0),
.out_req0 (fc_out_req0),
.out_ack0 (fc_out_ack0),
.out_bypass0 (fc_out_bypass0),
.out_protocol0 (fc_out_protocol0),
.out_data1 (fc_out_data1),
.out_pkt_route1 (fc_out_pkt_route1),
.out_wr1 (fc_out_wr1),
.out_req1 (fc_out_req1),
.out_ack1 (fc_out_ack1),
.out_bypass1 (fc_out_bypass1),
.out_protocol1(fc_out_protocol1),
.out_data2 (fc_out_data2),
.out_pkt_route2 (fc_out_pkt_route2),
.out_wr2 (fc_out_wr2),
.out_req2 (fc_out_req2),
.out_ack2 (fc_out_ack2),
.out_bypass2 (fc_out_bypass2),
.out_protocol2(fc_out_protocol2),
.out_data3 (fc_out_data3),
.out_pkt_route3 (fc_out_pkt_route3),
.out_wr3 (fc_out_wr3),
.out_req3 (fc_out_req3),
.out_ack3 (fc_out_ack3),
.out_bypass3 (fc_out_bypass3),
.out_protocol3(fc_out_protocol3),
.in_data (in_data),
.in_ctrl (in_ctrl),
.in_wr (in_wr),
.in_rdy (in_rdy),
.clk (clk),
.reset (reset)
);
/*
ppu ppu0(
.clk (clk),
.core_sp_clk (core_sp_clk),
.reset (reset),
.TRIG_IS (TRIG_IS0),
.TRIG_OS (TRIG_OS0),
.in_data0 (data10),
.in_pkt_route0 (pkt_route10),
.in_wr0 (wr10),
.in_req0 (req10),
.in_ack0 (ack10),
.in_bypass0 (bypass10),
.in_data1 (fc_out_data0),
.in_pkt_route1 (fc_out_pkt_route0),
.in_wr1 (fc_out_wr0),
.in_req1 (fc_out_req0),
.in_ack1 (fc_out_ack0),
.in_bypass1 (fc_out_bypass0),
.in_data2 (),
.in_pkt_route2 (),
.in_wr2 (),
.in_req2 (),
.in_ack2 (),
.in_bypass2 (),
.in_data3 (data20),
.in_pkt_route3 (pkt_route20),
.in_wr3 (wr20),
.in_req3 (req20),
.in_ack3 (ack20),
.in_bypass3 (bypass20),
.out_data0 (data01),
.out_pkt_route0 (pkt_route01),
.out_wr0 (wr01),
.out_req0 (req01),
.out_ack0 (ack01),
.out_bop0 (),
.out_eop0 (),
.out_rdy0 (1'b1),
.out_bypass0 (bypass01),
.out_data1 (),
.out_pkt_route1 (),
.out_wr1 (),
.out_req1 (),
.out_ack1 (),
.out_bop1 (),
.out_eop1 (),
.out_rdy1 (),
.out_bypass1 (),
.out_data2 (),
.out_pkt_route2 (),
.out_wr2 (),
.out_req2 (),
.out_ack2 (),
.out_bop2 (),
.out_eop2 (),
.out_rdy2 (),
.out_bypass2 (),
.out_data3 (pg_out_data2),
.out_pkt_route3 (pg_out_pkt_route2),
.out_wr3 (pg_out_wr2),
.out_req3 (pg_out_req2),
.out_ack3 (pg_out_ack2),
.out_bop3 (pg_out_bop2),
.out_eop3 (pg_out_eop2),
.out_rdy3 (pg_out_rdy2),
.out_bypass3 (pg_out_bypass2),
//for monitor
.pp_mem_addr (ppu_mem_addr),
.pkt_drop (packet_drop)
);
*/
ppu ppu0(
.clk (clk),
.core_sp_clk (core_sp_clk),
.reset (reset),
.TRIG_IS (TRIG_IS0),
.in_data0 (data10),
.in_pkt_route0 (pkt_route10),
.in_wr0 (wr10),
.in_req0 (req10),
.in_ack0 (ack10),
.in_bypass0 (bypass10),
.in_data1 (fc_out_data0),
.in_pkt_route1 (fc_out_pkt_route0),
.in_wr1 (fc_out_wr0),
.in_req1 (fc_out_req0),
.in_ack1 (fc_out_ack0),
.in_bypass1 (fc_out_bypass0),
.in_protocol1(fc_out_protocol0),
.in_data2 (),
.in_pkt_route2 (),
.in_wr2 (),
.in_req2 (),
.in_ack2 (),
.in_bypass2 (),
.in_data3 (data20),
.in_pkt_route3 (pkt_route20),
.in_wr3 (wr20),
.in_req3 (req20),
.in_ack3 (ack20),
.in_bypass3 (bypass20),
.out_data0 (data01),
.out_pkt_route0 (pkt_route01),
.out_wr0 (wr01),
.out_req0 (req01),
.out_ack0 (ack01),
.out_bop0 (),
.out_eop0 (),
.out_rdy0 (1'b1),
.out_bypass0 (bypass01),
.out_data1 (),
.out_pkt_route1 (),
.out_wr1 (),
.out_req1 (),
.out_ack1 (),
.out_bop1 (),
.out_eop1 (),
.out_rdy1 (),
.out_bypass1 (),
.out_data2 (),
.out_pkt_route2 (),
.out_wr2 (),
.out_req2 (),
.out_ack2 (),
.out_bop2 (),
.out_eop2 (),
.out_rdy2 (),
.out_bypass2 (),
.out_data3 (pg_out_data0),
.out_pkt_route3 (pg_out_pkt_route0),
.out_wr3 (pg_out_wr0),
.out_req3 (pg_out_req0),
.out_ack3 (pg_out_ack0),
.out_bop3 (pg_out_bop0),
.out_eop3 (pg_out_eop0),
.out_rdy3 (pg_out_rdy0),
.out_bypass3 (),
.four_bit_hash_output(four_bit_hash_output0),
.pc_input_hash_wire(pc_input_hash_wire0),
.new_inst_signal(new_inst_signal0),
.cam_we(cam_we),
.cam_wr_addr(cam_wr_addr),
.cam_din(cam_din),
.cam_wr_ack(cam_wr_ack)
);
router_op_lut_regs_non_cntr //#(
// .NUM_QUEUES (NUM_QUEUES),
// .ARP_LUT_DEPTH_BITS (ARP_LUT_DEPTH_BITS),
// .LPM_LUT_DEPTH_BITS (LPM_LUT_DEPTH_BITS),
//.FILTER_DEPTH_BITS (FILTER_DEPTH_BITS),
//.UDP_REG_SRC_WIDTH (UDP_REG_SRC_WIDTH)
// )
router_op_lut_regs_non_cntr (
.reg_req_in (reg_req_in),
.reg_ack_in (reg_ack_in),
.reg_rd_wr_L_in (reg_rd_wr_L_in),
.reg_addr_in (reg_addr_in),
.reg_data_in (reg_data_in),
.reg_src_in (reg_src_in),
// .reg_req_out (reg_req_out),
// .reg_ack_out (reg_ack_out),
// .reg_rd_wr_L_out (reg_rd_wr_L_out),
// .reg_addr_out (reg_addr_out),
// .reg_data_out (reg_data_out),
// .reg_src_out (reg_src_out),
// --- interface to dest_ip_filter
.dest_ip_filter_rd_addr (), // address in table to read
.dest_ip_filter_rd_req (), // request a read
.dest_ip_filter_rd_ip (), // ip to match in the CAM
.dest_ip_filter_rd_ack (), // pulses high
.dest_ip_filter_wr_addr (cam_wr_addr),
.dest_ip_filter_wr_req (cam_we),
.dest_ip_filter_wr_ip (cam_din), // data to match in the CAM
.dest_ip_filter_wr_ack (cam_wr_ack),
// --- eth_parser
.clk (clk),
.reset (reset)
);
/*
ppu ppu1(
.clk (clk),
.core_sp_clk (core_sp_clk),
.reset (reset1),
.in_data0 (),
.in_pkt_route0 (),
.in_wr0 (),
.in_req0 (),
.in_ack0 (),
.in_bypass0 (),
.in_data1 (fc_out_data1),
.in_pkt_route1 (fc_out_pkt_route1),
.in_wr1 (fc_out_wr1),
.in_req1 (fc_out_req1),
.in_ack1 (fc_out_ack1),
.in_bypass1 (fc_out_bypass1),
.in_data2 (data01),
.in_pkt_route2 (pkt_route01),
.in_wr2 (wr01),
.in_req2 (req01),
.in_ack2 (ack01),
.in_bypass2 (bypass01),
.in_protocol1(fc_out_protocol1),
.in_data3 (data31),
.in_pkt_route3 (pkt_route31),
.in_wr3 (wr31),
.in_req3 (req31),
.in_ack3 (ack31),
.in_bypass3 (bypass31),
.out_data0 (),
.out_pkt_route0 (),
.out_wr0 (),
.out_req0 (),
.out_ack0 (),
.out_bop0 (),
.out_eop0 (),
.out_rdy0 (),
.out_bypass0 (),
.out_data1 (),
.out_pkt_route1 (),
.out_wr1 (),
.out_req1 (),
.out_ack1 (),
.out_bop1 (),
.out_eop1 (),
.out_rdy1 (),
.out_bypass1 (),
.out_data2 (data10),
.out_pkt_route2 (pkt_route10),
.out_wr2 (wr10),
.out_req2 (req10),
.out_ack2 (ack10),
.out_bop2 (),
.out_eop2 (),
.out_rdy2 (1'b1),
.out_bypass2 (bypass10),
.out_data3 (pg_out_data1),
.out_pkt_route3 (pg_out_pkt_route1),
.out_wr3 (pg_out_wr1),
.out_req3 (pg_out_req1),
.out_ack3 (pg_out_ack1),
.out_bop3 (pg_out_bop1),
.out_eop3 (pg_out_eop1),
.out_rdy3 (pg_out_rdy1),
.out_bypass3 (),
.four_bit_hash_output(four_bit_hash_output1),
.pc_input_hash_wire(pc_input_hash_wire1),
.new_inst_signal(new_inst_signal1)
);
ppu ppu2(
.clk (clk),
.core_sp_clk (core_sp_clk),
.reset (reset2),
.TRIG_IS (TRIG_IS2),
.in_data0 (data32),
.in_pkt_route0 (pkt_route32),
.in_wr0 (wr32),
.in_req0 (req32),
.in_ack0 (ack32),
.in_bypass0 (bypass32),
.in_data1 (fc_out_data2),
.in_pkt_route1 (fc_out_pkt_route2),
.in_wr1 (fc_out_wr2),
.in_req1 (fc_out_req2),
.in_ack1 (fc_out_ack2),
.in_bypass1 (fc_out_bypass2),
.in_protocol1(fc_out_protocol2),
.in_data2 (),
.in_pkt_route2 (),
.in_wr2 (),
.in_req2 (),
.in_ack2 (),
.in_bypass2 (),
.in_data3 (),
.in_pkt_route3 (),
.in_wr3 (),
.in_req3 (),
.in_ack3 (),
.in_bypass3 (),
.out_data0 (data23),
.out_pkt_route0 (pkt_route23),
.out_wr0 (wr23),
.out_req0 (req23),
.out_ack0 (ack23),
.out_bop0 (),
.out_eop0 (),
.out_rdy0 (1'b1),
.out_bypass0 (bypass23),
.out_data1 (data20),
.out_pkt_route1 (pkt_route20),
.out_wr1 (wr20),
.out_req1 (req20),
.out_ack1 (ack20),
.out_bop1 (),
.out_eop1 (),
.out_rdy1 (1'b1),
.out_bypass1 (bypass20),
.out_data2 (),
.out_pkt_route2 (),
.out_wr2 (),
.out_req2 (),
.out_ack2 (),
.out_bop2 (),
.out_eop2 (),
.out_rdy2 (),
.out_bypass2 (),
.out_data3 (pg_out_data2),
.out_pkt_route3 (pg_out_pkt_route2),
.out_wr3 (pg_out_wr2),
.out_req3 (pg_out_req2),
.out_ack3 (pg_out_ack2),
.out_bop3 (pg_out_bop2),
.out_eop3 (pg_out_eop2),
.out_rdy3 (pg_out_rdy2),
.out_bypass3 (),
.four_bit_hash_output(four_bit_hash_output2),
.pc_input_hash_wire(pc_input_hash_wire2),
.new_inst_signal(new_inst_signal2)
);
ppu ppu3(
.clk (clk),
.core_sp_clk (core_sp_clk),
.reset (reset3),
.in_data0 (),
.in_pkt_route0 (),
.in_wr0 (),
.in_req0 (),
.in_ack0 (),
.in_bypass0 (),
.in_data1 (fc_out_data3),
.in_pkt_route1 (fc_out_pkt_route3),
.in_wr1 (fc_out_wr3),
.in_req1 (fc_out_req3),
.in_ack1 (fc_out_ack3),
.in_bypass1 (fc_out_bypass3),
.in_protocol1(fc_out_protocol3),
.in_data2 (data23),
.in_pkt_route2 (pkt_route23),
.in_wr2 (wr23),
.in_req2 (req23),
.in_ack2 (ack23),
.in_bypass2 (bypass23),
.in_data3 (),
.in_pkt_route3 (),
.in_wr3 (),
.in_req3 (),
.in_ack3 (),
.in_bypass3 (),
.out_data0 (),
.out_pkt_route0 (),
.out_wr0 (),
.out_req0 (),
.out_ack0 (),
.out_bop0 (),
.out_eop0 (),
.out_rdy0 (),
.out_bypass0 (),
.out_data1 (data31),
.out_pkt_route1 (pkt_route31),
.out_wr1 (wr31),
.out_req1 (req31),
.out_ack1 (ack31),
.out_bop1 (),
.out_eop1 (),
.out_rdy1 (1'b1),
.out_bypass1 (bypass31),
.out_data2 (data32),
.out_pkt_route2 (pkt_route32),
.out_wr2 (wr32),
.out_req2 (req32),
.out_ack2 (ack32),
.out_bop2 (),
.out_eop2 (),
.out_rdy2 (1'b1),
.out_bypass2 (bypass32),
.out_data3 (pg_out_data3),
.out_pkt_route3 (pg_out_pkt_route3),
.out_wr3 (pg_out_wr3),
.out_req3 (pg_out_req3),
.out_ack3 (pg_out_ack3),
.out_bop3 (pg_out_bop3),
.out_eop3 (pg_out_eop3),
.out_rdy3 (pg_out_rdy3),
.out_bypass3 (),
.four_bit_hash_output(four_bit_hash_output3),
.pc_input_hash_wire(pc_input_hash_wire3),
.new_inst_signal(new_inst_signal3)
);
*/
out_arbiter oa(
.out_data (out_data),
.out_ctrl (out_ctrl),
.out_wr (out_wr),
.out_rdy (out_rdy),
.in_data0 (pg_out_data0),
.in_wr0 (pg_out_wr0),
.in_req0 (pg_out_req0),
.in_ack0 (pg_out_ack0),
.in_bop0 (pg_out_bop0),
.in_eop0 (pg_out_eop0),
.in_outrdy0 (pg_out_rdy0),
.in_data1 (pg_out_data1),
.in_wr1 (pg_out_wr1),
.in_req1 (pg_out_req1),
.in_ack1 (pg_out_ack1),
.in_bop1 (pg_out_bop1),
.in_eop1 (pg_out_eop1),
.in_outrdy1 (pg_out_rdy1),
.in_data2 (pg_out_data2),
.in_wr2 (pg_out_wr2),
.in_req2 (pg_out_req2),
.in_ack2 (pg_out_ack2),
.in_bop2 (pg_out_bop2),
.in_eop2 (pg_out_eop2),
.in_outrdy2 (pg_out_rdy2),
.in_data3 (pg_out_data3),
.in_wr3 (pg_out_wr3),
.in_req3 (pg_out_req3),
.in_ack3 (pg_out_ack3),
.in_bop3 (pg_out_bop3),
.in_eop3 (pg_out_eop3),
.in_outrdy3 (pg_out_rdy3),
.clk (clk),
.reset (reset)
);
/*
statemachine_shared shared_CM(
.clk(clk),
.statemac_clk(statemac_clk),
.four_bit_hash0(four_bit_hash_output0_cm),
.four_bit_hash1(four_bit_hash_output1_cm),
.four_bit_hash2(four_bit_hash_output2_cm),
.four_bit_hash3(four_bit_hash_output3_cm),
.pcin_0(pc_input_hash_wire0_cm),
.pcin_1(pc_input_hash_wire1_cm),
.pcin_2(pc_input_hash_wire2_cm),
.pcin_3(pc_input_hash_wire3_cm),
.new_inst_signal0(new_inst_signal0_cm),
.new_inst_signal1(new_inst_signal1_cm),
.new_inst_signal2(new_inst_signal2_cm),
.new_inst_signal3(new_inst_signal3_cm),
.reset(reset),
.packet_drop_signal0(packet_drop_signal0_cm),
.packet_drop_signal1(packet_drop_signal1_cm),
.packet_drop_signal2(packet_drop_signal2_cm),
.packet_drop_signal3(packet_drop_signal3_cm)
);
statemachine_shared_IPV4 shared_IPV4(
.clk(clk),
.statemac_clk(statemac_clk),
.four_bit_hash0(four_bit_hash_output0_ipv4),
.four_bit_hash1(four_bit_hash_output1_ipv4),
.four_bit_hash2(four_bit_hash_output2_ipv4),
.four_bit_hash3(four_bit_hash_output3_ipv4),
.pcin_0(pc_input_hash_wire0_ipv4),
.pcin_1(pc_input_hash_wire1_ipv4),
.pcin_2(pc_input_hash_wire2_ipv4),
.pcin_3(pc_input_hash_wire3_ipv4),
.new_inst_signal0(new_inst_signal0_ipv4),
.new_inst_signal1(new_inst_signal1_ipv4),
.new_inst_signal2(new_inst_signal2_ipv4),
.new_inst_signal3(new_inst_signal3_ipv4),
.reset(reset),
.packet_drop_signal0(packet_drop_signal0_ipv4),
.packet_drop_signal1(packet_drop_signal1_ipv4),
.packet_drop_signal2(packet_drop_signal2_ipv4),
.packet_drop_signal3(packet_drop_signal3_ipv4)
);
*/
assign four_bit_hash_output0_ipv4 = (!fc_out_protocol0) ? four_bit_hash_output0 : 0;
assign four_bit_hash_output1_ipv4 = (!fc_out_protocol1) ? four_bit_hash_output1 : 0;
assign four_bit_hash_output2_ipv4 = (!fc_out_protocol2) ? four_bit_hash_output2 : 0;
assign four_bit_hash_output3_ipv4 = (!fc_out_protocol3) ? four_bit_hash_output3 : 0;
assign pc_input_hash_wire0_ipv4 = (!fc_out_protocol0) ? pc_input_hash_wire0 : 0;
assign pc_input_hash_wire1_ipv4 = (!fc_out_protocol1) ? pc_input_hash_wire1 : 0;
assign pc_input_hash_wire2_ipv4 = (!fc_out_protocol2) ? pc_input_hash_wire2 : 0;
assign pc_input_hash_wire3_ipv4 = (!fc_out_protocol3) ? pc_input_hash_wire3 : 0;
assign new_inst_signal0_ipv4 = (!fc_out_protocol0) ? new_inst_signal0 : 0;
assign new_inst_signal1_ipv4 = (!fc_out_protocol1) ? new_inst_signal1 : 0;
assign new_inst_signal2_ipv4 = (!fc_out_protocol2) ? new_inst_signal2 : 0;
assign new_inst_signal3_ipv4 = (!fc_out_protocol3) ? new_inst_signal3 : 0;
//======================================================================
//=======================================================================
assign four_bit_hash_output0_cm = (fc_out_protocol0) ? four_bit_hash_output0 : 0;
assign four_bit_hash_output1_cm = (fc_out_protocol1) ? four_bit_hash_output1 : 0;
assign four_bit_hash_output2_cm = (fc_out_protocol2) ? four_bit_hash_output2 : 0;
assign four_bit_hash_output3_cm = (fc_out_protocol3) ? four_bit_hash_output3 : 0;
assign pc_input_hash_wire0_cm = (fc_out_protocol0) ? pc_input_hash_wire0 : 0;
assign pc_input_hash_wire1_cm = (fc_out_protocol1) ? pc_input_hash_wire1 : 0;
assign pc_input_hash_wire2_cm = (fc_out_protocol2) ? pc_input_hash_wire2 : 0;
assign pc_input_hash_wire3_cm = (fc_out_protocol3) ? pc_input_hash_wire3 : 0;
assign new_inst_signal0_cm = (fc_out_protocol0) ? new_inst_signal0 : 0;
assign new_inst_signal1_cm = (fc_out_protocol1) ? new_inst_signal1 : 0;
assign new_inst_signal2_cm = (fc_out_protocol2) ? new_inst_signal2 : 0;
assign new_inst_signal3_cm = (fc_out_protocol3) ? new_inst_signal3 : 0;
assign packet_drop_core_zero = (fc_out_protocol0) ? packet_drop_signal0_cm : packet_drop_signal0_ipv4;
assign packet_drop_core_one = (fc_out_protocol1) ? packet_drop_signal1_cm : packet_drop_signal1_ipv4;
assign packet_drop_core_two = (fc_out_protocol2) ? packet_drop_signal2_cm : packet_drop_signal2_ipv4;
assign packet_drop_core_three = (fc_out_protocol3) ? packet_drop_signal3_cm : packet_drop_signal3_ipv4;
assign reset0 = reset | packet_drop_core_zero;
assign reset1 = reset | packet_drop_core_one;
assign reset2 = reset | packet_drop_core_two;
assign reset3 = reset | packet_drop_core_three;
wire [35:0] CONTROL0;
wire [239:0] TRIG0;
/*
chipscope_icon_v1_03_a cs_icon (
.CONTROL0(CONTROL0)
);
chipscope_ila_single cs_ila (
.CONTROL(CONTROL0),
.CLK(clk),
.TRIG0(TRIG0)
);
assign TRIG0[7:0] = fc_out_data0[7:0];
assign TRIG0[10:8] = fc_out_pkt_route0[2:0];
assign TRIG0[11] = fc_out_wr0;
assign TRIG0[12] = fc_out_req0;
assign TRIG0[13] = fc_out_ack0;
assign TRIG0[14] = fc_out_bypass0;
assign TRIG0[27:20] = fc_out_data1[7:0];
assign TRIG0[30:28] = fc_out_pkt_route1[2:0];
assign TRIG0[31] = fc_out_wr1;
assign TRIG0[32] = fc_out_req1;
assign TRIG0[33] = fc_out_ack1;
assign TRIG0[34] = fc_out_bypass1;
assign TRIG0[47:40] = pg_out_data2[7:0];
assign TRIG0[50:48] = pg_out_pkt_route2[2:0];
assign TRIG0[51] = pg_out_wr2;
assign TRIG0[52] = pg_out_req2;
assign TRIG0[53] = pg_out_ack2;
assign TRIG0[54] = pg_out_bop2;
assign TRIG0[55] = pg_out_eop2;
assign TRIG0[56] = pg_out_rdy2;
assign TRIG0[57] = pg_out_bypass2;
assign TRIG0[67:60] = pg_out_data3[7:0];
assign TRIG0[70:68] = pg_out_pkt_route3[2:0];
assign TRIG0[71] = pg_out_wr3;
assign TRIG0[72] = pg_out_req3;
assign TRIG0[73] = pg_out_ack3;
assign TRIG0[74] = pg_out_bop3;
assign TRIG0[75] = pg_out_eop3;
assign TRIG0[76] = pg_out_rdy3;
assign TRIG0[87:80] = data01[7:0];
assign TRIG0[90:88] = pkt_route01[2:0];
assign TRIG0[91] = wr01;
assign TRIG0[92] = req01;
assign TRIG0[93] = ack01;
assign TRIG0[94] = bypass01;
assign TRIG0[107:100] = data10[7:0];
assign TRIG0[110:108] = pkt_route10[2:0];
assign TRIG0[111] = wr10;
assign TRIG0[112] = req10;
assign TRIG0[113] = ack10;
assign TRIG0[114] = bypass10;
*/
/*
assign TRIG0[91:80] = TRIG_IS0[41:30];
assign TRIG0[94:92] = TRIG_IS0[28:26];
assign TRIG0[97:95] = TRIG_IS0[25:23];
assign TRIG0[100] = TRIG_IS0[0];
assign TRIG0[101] = TRIG_IS0[1];
assign TRIG0[104:102] = TRIG_IS0[4:2];
assign TRIG0[106:105] = TRIG_IS0[6:5];
assign TRIG0[107] = TRIG_IS0[10];
assign TRIG0[108] = TRIG_IS0[11];
assign TRIG0[111:109] = TRIG_IS0[14:12];
assign TRIG0[113:112] = TRIG_IS0[16:15];
assign TRIG0[114] = TRIG_IS0[17];
assign TRIG0[115] = TRIG_IS0[18];
assign TRIG0[116] = TRIG_IS0[19];
assign TRIG0[117] = TRIG_IS0[20];
assign TRIG0[118] = TRIG_IS0[21];
assign TRIG0[119] = TRIG_IS0[22];
*/
/*
assign TRIG0[127:120] = data02[7:0];
assign TRIG0[130:128] = pkt_route02[2:0];
assign TRIG0[131] = wr02;
assign TRIG0[132] = req02;
assign TRIG0[133] = ack02;
assign TRIG0[134] = bypass02;
assign TRIG0[147:140] = data20[7:0];
assign TRIG0[150:148] = pkt_route20[2:0];
assign TRIG0[151] = wr20;
assign TRIG0[152] = req20;
assign TRIG0[153] = ack20;
assign TRIG0[154] = bypass20;
//assign TRIG0[234:160] = TRIG_OS0[74:0];
assign TRIG0[167:160] = data13[7:0];
assign TRIG0[170:168] = pkt_route13[2:0];
assign TRIG0[171] = wr13;
assign TRIG0[172] = req13;
assign TRIG0[173] = ack13;
assign TRIG0[174] = bypass13;
assign TRIG0[187:180] = data31[7:0];
assign TRIG0[190:188] = pkt_route31[2:0];
assign TRIG0[191] = wr31;
assign TRIG0[192] = req31;
assign TRIG0[193] = ack31;
assign TRIG0[194] = bypass31;
assign TRIG0[207:200] = data23[7:0];
assign TRIG0[210:208] = pkt_route23[2:0];
assign TRIG0[211] = wr23;
assign TRIG0[212] = req23;
assign TRIG0[213] = ack23;
assign TRIG0[214] = bypass23;
assign TRIG0[227:220] = data32[7:0];
assign TRIG0[230:228] = pkt_route32[2:0];
assign TRIG0[231] = wr32;
assign TRIG0[232] = req32;
assign TRIG0[233] = ack32;
assign TRIG0[234] = bypass32;
assign TRIG0[235] = in_wr;
assign TRIG0[236] = in_rdy;
assign TRIG0[237] = out_wr;
assign TRIG0[238] = out_rdy;
*/
endmodule
|
// Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
// Date : Mon Mar 24 21:51:05 2014
// Host : macbook running 64-bit unknown
// Command : write_verilog -force -mode synth_stub /home/keith/Documents/VHDL-lib/top/lab_3/part_1/ip/dds/dds_stub.v
// Design : dds
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module dds(aclk, m_axis_data_tvalid, m_axis_data_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,m_axis_data_tvalid,m_axis_data_tdata[15:0]" */;
input aclk;
output m_axis_data_tvalid;
output [15:0]m_axis_data_tdata;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAPHE_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__DECAPHE_BEHAVIORAL_PP_V
/**
* decaphe: Shielded Decoupling capacitance filler.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__decaphe (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAPHE_BEHAVIORAL_PP_V |
// -*- Mode: Verilog -*-
// Filename : testing_wb_master.v
// Description : Testing a Wishbone Bus Master
// Author : Philip Tracton
// Created On : Fri Nov 27 16:22:45 2015
// Last Modified By: Philip Tracton
// Last Modified On: Fri Nov 27 16:22:45 2015
// Update Count : 0
// Status : Unknown, Use with caution!
`timescale 1ns/1ns
module testing_wb_master (/*AUTOARG*/
// Outputs
wb_adr_o, wb_dat_o, wb_sel_o, wb_we_o, wb_cyc_o, wb_stb_o,
wb_cti_o, wb_bte_o, data_rd, active,
// Inputs
wb_clk, wb_rst, wb_dat_i, wb_ack_i, wb_err_i, wb_rty_i, start,
address, selection, write, data_wr
) ;
parameter dw = 32;
parameter aw = 32;
parameter DEBUG = 0;
input wb_clk;
input wb_rst;
output reg [aw-1:0] wb_adr_o;
output reg [dw-1:0] wb_dat_o;
output reg [3:0] wb_sel_o;
output reg wb_we_o;
output reg wb_cyc_o;
output reg wb_stb_o;
output reg [2:0] wb_cti_o;
output reg [1:0] wb_bte_o;
input [dw-1:0] wb_dat_i;
input wb_ack_i;
input wb_err_i;
input wb_rty_i;
input start;
input [aw-1:0] address;
input [3:0] selection;
input write;
input [dw-1:0] data_wr;
output reg [dw-1:0] data_rd;
output reg active;
reg [1:0] state;
reg [1:0] next_state;
parameter STATE_IDLE = 2'h0;
parameter STATE_WAIT_ACK = 2'h1;
parameter STATE_ERROR = 2'h3;
reg [aw-1:0] adr_o;
reg [dw-1:0] dat_o;
reg [3:0] sel_o;
reg we_o;
reg cyc_o;
reg stb_o;
reg [2:0] cti_o;
reg [1:0] bte_o;
always @(posedge wb_clk)
if (wb_rst) begin
state <= STATE_IDLE;
end else begin
state <= next_state;
end
always @(*)
if (wb_rst) begin
next_state = STATE_IDLE;
active = 0;
wb_adr_o <= 0;
wb_dat_o <= 0;
wb_sel_o <= 0;
wb_we_o <= 0;
wb_cyc_o <= 0;
wb_stb_o <= 0;
wb_cti_o <= 0;
wb_bte_o <= 0;
data_rd <= 0;
end else begin // if (wb_rst)
case (state)
STATE_IDLE: begin
active = 0;
wb_adr_o = 0;
wb_dat_o = 0;
wb_sel_o = 0;
wb_we_o = 0;
wb_cyc_o = 0;
wb_stb_o = 0;
wb_cti_o = 0;
wb_bte_o = 0;
if (start) begin
next_state = STATE_WAIT_ACK;
wb_adr_o = address;
wb_dat_o = data_wr;
wb_sel_o = selection;
wb_we_o = write;
wb_cyc_o = 1;
wb_stb_o = 1;
wb_cti_o = 0;
wb_bte_o = 0;
active = 1;
data_rd =0;
end else begin
next_state = STATE_IDLE;
end
end // case: STATE_IDLE
STATE_WAIT_ACK: begin
if (wb_err_i || wb_rty_i) begin
next_state = STATE_ERROR;
end else if (wb_ack_i) begin
if (! wb_we_o)
data_rd = wb_dat_i;
next_state = STATE_IDLE;
end else begin
next_state = STATE_WAIT_ACK;
end
end // case: STATE_WAIT_ACK
STATE_ERROR: begin
next_state = STATE_IDLE;
end
default: begin
next_state = STATE_IDLE;
end
endcase // case (state)
end
`ifdef SIM
reg [32*8-1:0] state_name;
always @(*)
case (state)
STATE_IDLE: state_name = "STATE_IDLE";
STATE_WAIT_ACK: state_name = "STATE_WAIT ACK";
STATE_ERROR:state_name = "STATE ERROR";
default: state_name = "DEFAULT";
endcase // case (state)
`endif
endmodule // testing_wb_master
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O21A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__O21A_BEHAVIORAL_PP_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__o21a (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O21A_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O41A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__O41A_BEHAVIORAL_PP_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o41a (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A4, A3, A2, A1 );
and and0 (and0_out_X , or0_out, B1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O41A_BEHAVIORAL_PP_V |
// Copyright (c) 2000-2011 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Dual-Ported BRAM (WRITE FIRST) with byte enables
module BRAM2BE(CLKA,
ENA,
WEA,
ADDRA,
DIA,
DOA,
CLKB,
ENB,
WEB,
ADDRB,
DIB,
DOB
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter CHUNKSIZE = 1;
parameter WE_WIDTH = 1;
parameter MEMSIZE = 1;
input CLKA;
input ENA;
input [WE_WIDTH-1:0] WEA;
input [ADDR_WIDTH-1:0] ADDRA;
input [DATA_WIDTH-1:0] DIA;
output [DATA_WIDTH-1:0] DOA;
input CLKB;
input ENB;
input [WE_WIDTH-1:0] WEB;
input [ADDR_WIDTH-1:0] ADDRB;
input [DATA_WIDTH-1:0] DIB;
output [DATA_WIDTH-1:0] DOB;
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1] /* synthesis syn_ramstyle="no_rw_check" */ ;
reg [DATA_WIDTH-1:0] DOA_R;
reg [DATA_WIDTH-1:0] DOA_R2;
reg [DATA_WIDTH-1:0] DOB_R;
reg [DATA_WIDTH-1:0] DOB_R2;
`ifdef BSV_NO_INITIAL_BLOCKS
`else
// synopsys translate_off
integer i;
initial
begin : init_block
for (i = 0; i < MEMSIZE; i = i + 1) begin
RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
DOA_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOA_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOB_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOB_R2 = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
// synopsys translate_on
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
// PORT A
// iverilog does not support the full verilog-2001 language. This fixes that for simulation.
`ifdef __ICARUS__
reg [DATA_WIDTH-1:0] MASKA, IMASKA;
reg [DATA_WIDTH-1:0] DATA_A;
wire [DATA_WIDTH-1:0] DATA_Awr;
assign DATA_Awr = RAM[ADDRA];
always @(WEA or DIA or DATA_Awr) begin : combo1
integer j;
MASKA = 0;
IMASKA = 0;
for(j = WE_WIDTH-1; j >= 0; j = j - 1) begin
if (WEA[j]) MASKA = (MASKA << 8) | { { DATA_WIDTH-CHUNKSIZE { 1'b0 } }, { CHUNKSIZE { 1'b1 } } };
else MASKA = (MASKA << 8);
end
IMASKA = ~MASKA;
DATA_A = (DATA_Awr & IMASKA) | (DIA & MASKA);
end
always @(posedge CLKA) begin
if (ENA) begin
if (WEA) begin
RAM[ADDRA] <= `BSV_ASSIGNMENT_DELAY DATA_A;
DOA_R <= `BSV_ASSIGNMENT_DELAY DATA_A;
end
else begin
DOA_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA];
end
end
end
`else
generate
genvar j;
for(j = 0; j < WE_WIDTH; j = j + 1) begin: porta_we
always @(posedge CLKA) begin
if (ENA) begin
if (WEA[j]) begin
RAM[ADDRA][((j+1)*CHUNKSIZE)-1 : j*CHUNKSIZE] <= `BSV_ASSIGNMENT_DELAY DIA[((j+1)*CHUNKSIZE)-1 : j*CHUNKSIZE];
DOA_R[((j+1)*CHUNKSIZE)-1 : j*CHUNKSIZE] <= `BSV_ASSIGNMENT_DELAY DIA[((j+1)*CHUNKSIZE)-1 : j*CHUNKSIZE];
end
else begin
DOA_R[((j+1)*CHUNKSIZE)-1 : j*CHUNKSIZE] <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA][((j+1)*CHUNKSIZE)-1 : j*CHUNKSIZE];
end
end
end
end
endgenerate
`endif // !`ifdef __ICARUS__
// PORT B
// iverilog does not support the full verilog-2001 language. This fixes that for simulation.
`ifdef __ICARUS__
reg [DATA_WIDTH-1:0] MASKB, IMASKB;
reg [DATA_WIDTH-1:0] DATA_B;
wire [DATA_WIDTH-1:0] DATA_Bwr;
assign DATA_Bwr = RAM[ADDRB];
always @(WEB or DIB or DATA_Bwr) begin : combo2
integer j;
MASKB = 0;
IMASKB = 0;
for(j = WE_WIDTH-1; j >= 0; j = j - 1) begin
if (WEB[j]) MASKB = (MASKB << 8) | { { DATA_WIDTH-CHUNKSIZE { 1'b0 } }, { CHUNKSIZE { 1'b1 } } };
else MASKB = (MASKB << 8);
end
IMASKB = ~MASKB;
DATA_B = (DATA_Bwr & IMASKB) | (DIB & MASKB);
end
always @(posedge CLKB) begin
if (ENB) begin
if (WEB) begin
RAM[ADDRB] <= `BSV_ASSIGNMENT_DELAY DATA_B;
DOB_R <= `BSV_ASSIGNMENT_DELAY DATA_B;
end
else begin
DOB_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB];
end
end
end
`else
generate
genvar k;
for(k = 0; k < WE_WIDTH; k = k + 1) begin: portb_we
always @(posedge CLKB) begin
if (ENB) begin
if (WEB[k]) begin
RAM[ADDRB][((k+1)*CHUNKSIZE)-1 : k*CHUNKSIZE] <= `BSV_ASSIGNMENT_DELAY DIB[((k+1)*CHUNKSIZE)-1 : k*CHUNKSIZE];
DOB_R[((k+1)*CHUNKSIZE)-1 : k*CHUNKSIZE] <= `BSV_ASSIGNMENT_DELAY DIB[((k+1)*CHUNKSIZE)-1 : k*CHUNKSIZE];
end
else begin
DOB_R[((k+1)*CHUNKSIZE)-1 : k*CHUNKSIZE] <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB][((k+1)*CHUNKSIZE)-1 : k*CHUNKSIZE];
end
end
end
end
endgenerate
`endif // !`ifdef __ICARUS__
// Output drivers
always @(posedge CLKA) begin
DOA_R2 <= `BSV_ASSIGNMENT_DELAY DOA_R;
end
always @(posedge CLKB) begin
DOB_R2 <= `BSV_ASSIGNMENT_DELAY DOB_R;
end
assign DOA = (PIPELINED) ? DOA_R2 : DOA_R;
assign DOB = (PIPELINED) ? DOB_R2 : DOB_R;
endmodule // BRAM2BE
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A311OI_FUNCTIONAL_V
`define SKY130_FD_SC_LP__A311OI_FUNCTIONAL_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a311oi (
Y ,
A1,
A2,
A3,
B1,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y, and0_out, B1, C1);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A311OI_FUNCTIONAL_V |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pci_exp_usrapp_tx.v
// Version : 1.11
//
//------------------------------------------------------------------------------
`include "board_common.v"
module pci_exp_usrapp_tx #(
parameter LINK_CAP_MAX_LINK_SPEED = 4'h2) (
trn_td,
trn_trem_n,
trn_tsof_n,
trn_teof_n,
trn_terrfwd_n,
trn_tsrc_rdy_n,
trn_tsrc_dsc_n,
trn_clk,
trn_reset_n,
trn_lnk_up_n,
trn_tdst_rdy_n,
trn_tdst_dsc_n,
trn_tbuf_av,
speed_change_done_n
);
output [(64 - 1):0] trn_td;
output trn_trem_n;
output trn_tsof_n;
output trn_teof_n;
output trn_terrfwd_n;
output trn_tsrc_rdy_n;
output trn_tsrc_dsc_n;
input trn_clk;
input trn_reset_n;
input trn_lnk_up_n;
input trn_tdst_rdy_n;
input trn_tdst_dsc_n;
input [(6 - 1):0] trn_tbuf_av;
input speed_change_done_n;
parameter Tcq = 1;
/* Output Variables */
reg [(64 - 1):0] trn_td;
reg [(8 - 1):0] trn_trem_ni;
reg trn_tsof_n;
reg trn_teof_n;
reg trn_terrfwd_n;
reg trn_tsrc_rdy_n;
reg trn_tsrc_dsc_n;
/* Local Variables */
integer i, j, k;
reg [7:0] DATA_STORE [4095:0];
reg [31:0] ADDRESS_32_L;
reg [31:0] ADDRESS_32_H;
reg [63:0] ADDRESS_64;
reg [15:0] COMPLETER_ID;
reg [15:0] COMPLETER_ID_CFG;
reg [15:0] REQUESTER_ID;
reg [15:0] DESTINATION_RID;
reg [2:0] DEFAULT_TC;
reg [9:0] DEFAULT_LENGTH;
reg [3:0] DEFAULT_BE_LAST_DW;
reg [3:0] DEFAULT_BE_FIRST_DW;
reg [1:0] DEFAULT_ATTR;
reg [7:0] DEFAULT_TAG;
reg [3:0] DEFAULT_COMP;
reg [11:0] EXT_REG_ADDR;
reg TD;
reg EP;
reg [15:0] VENDOR_ID;
reg [9:0] LENGTH; // For 1DW config and IO transactions
reg [6:0] RAND_;
reg [9:0] CFG_DWADDR;
reg [15:0] P_DEV_BDF;
reg [31:0] P_IO_ADDR;
reg [31:0] P_ADDRESS_1L;
reg [31:0] P_ADDRESS_2L;
reg [31:0] P_ADDRESS_3L;
reg [31:0] P_ADDRESS_4L;
reg [31:0] P_ADDRESS_H;
reg [9:0] P_CFG_DWADDR;
event test_begin;
reg [31:0] P_ADDRESS_MASK;
reg [31:0] P_READ_DATA; // will store the results of a PCIE read completion
reg [31:0] data;
reg p_read_data_valid;
reg [31:0] P_WRITE_DATA;
reg [31:0] temp_register;
reg error_check;
// BAR Init variables
reg [32:0] BAR_INIT_P_BAR[6:0]; // 6 corresponds to Expansion ROM
// note that bit 32 is for overflow checking
reg [31:0] BAR_INIT_P_BAR_RANGE[6:0]; // 6 corresponds to Expansion ROM
reg [1:0] BAR_INIT_P_BAR_ENABLED[6:0]; // 6 corresponds to Expansion ROM
// 0 = disabled; 1 = io mapped; 2 = mem32 mapped; 3 = mem64 mapped
reg [31:0] BAR_INIT_P_MEM64_HI_START; // start address for hi memory space
reg [31:0] BAR_INIT_P_MEM64_LO_START; // start address for hi memory space
reg [32:0] BAR_INIT_P_MEM32_START; // start address for low memory space
// top bit used for overflow indicator
reg [32:0] BAR_INIT_P_IO_START; // start address for io space
reg [100:0] BAR_INIT_MESSAGE[3:0]; // to be used to display info to user
reg [32:0] BAR_INIT_TEMP;
reg OUT_OF_LO_MEM; // flags to indicate out of mem, mem64, and io
reg OUT_OF_IO;
reg OUT_OF_HI_MEM;
reg [3:0] ii;
integer jj;
reg [31:0] DEV_VEN_ID; // holds device and vendor id
integer PIO_MAX_NUM_BLOCK_RAMS; // holds the max number of block RAMS
reg [31:0] PIO_MAX_MEMORY;
reg [31:0] PIO_ADDRESS; // holds the current PIO testing address
reg pio_check_design; // boolean value to check PCI Express BAR configuration against
// limitations of PIO design. Setting this to true will cause the
// testbench to check if the core has been configured for more than
// one IO space, one general purpose Mem32 space (not counting
// the Mem32 EROM space), and one Mem64 space.
reg cpld_to; // boolean value to indicate if time out has occured while waiting for cpld
reg cpld_to_finish; // boolean value to indicate to $finish on cpld_to
reg verbose; // boolean value to display additional info to stdout
integer NUMBER_OF_IO_BARS;
integer NUMBER_OF_MEM32_BARS; // Not counting the Mem32 EROM space
integer NUMBER_OF_MEM64_BARS;
initial
begin
ADDRESS_32_L = 32'b1011_1110_1110_1111_1100_1010_1111_1110;
ADDRESS_32_H = 32'b1011_1110_1110_1111_1100_1010_1111_1110;
ADDRESS_64 = { ADDRESS_32_H, ADDRESS_32_L };
COMPLETER_ID = 16'b0000_0000_1010_0000;
COMPLETER_ID_CFG = 16'b0000_0001_1010_0000;
REQUESTER_ID = 16'b0000_0001_1010_1111;
DESTINATION_RID = 16'b0000_0001_1010_1111;
DEFAULT_TC = 3'b000;
DEFAULT_LENGTH = 10'h000;
DEFAULT_BE_LAST_DW = 4'h0;
DEFAULT_BE_FIRST_DW = 4'h0;
DEFAULT_ATTR = 2'b01;
DEFAULT_TAG = 8'h00;
DEFAULT_COMP = 4'h0;
EXT_REG_ADDR = 12'h000;
TD = 0;
EP = 0;
VENDOR_ID = 16'h10ee;
LENGTH = 10'b00_0000_0001;
end
initial begin
// Pre-BAR initialization
BAR_INIT_MESSAGE[0] = "DISABLED";
BAR_INIT_MESSAGE[1] = "IO MAPPED";
BAR_INIT_MESSAGE[2] = "MEM32 MAPPED";
BAR_INIT_MESSAGE[3] = "MEM64 MAPPED";
OUT_OF_LO_MEM = 1'b0;
OUT_OF_IO = 1'b0;
OUT_OF_HI_MEM = 1'b0;
// Disable variables to start
for (ii = 0; ii <= 6; ii = ii + 1) begin
BAR_INIT_P_BAR[ii] = 33'h00000_0000;
BAR_INIT_P_BAR_RANGE[ii] = 32'h0000_0000;
BAR_INIT_P_BAR_ENABLED[ii] = 2'b00;
end
BAR_INIT_P_MEM64_HI_START = 32'h0000_0001; // hi 32 bit start of 64bit memory
BAR_INIT_P_MEM64_LO_START = 32'h0000_0000; // low 32 bit start of 64bit memory
BAR_INIT_P_MEM32_START = 33'h00000_0000; // start of 32bit memory
BAR_INIT_P_IO_START = 33'h00000_0000; // start of 32bit io
DEV_VEN_ID = (32'h7024 << 16) | (32'h10EE);
PIO_MAX_MEMORY = 8192; // PIO has max of 8Kbytes of memory
PIO_MAX_NUM_BLOCK_RAMS = 4; // PIO has four block RAMS to test
PIO_MAX_MEMORY = 2048; // PIO has 4 memory regions with 2 Kbytes of memory per region, ie 8 Kbytes
PIO_MAX_NUM_BLOCK_RAMS = 4; // PIO has four block RAMS to test
pio_check_design = 1; // By default check to make sure the core has been configured
// appropriately for the PIO design
cpld_to = 0; // By default time out has not occured
cpld_to_finish = 1; // By default end simulation on time out
verbose = 0; // turned off by default
NUMBER_OF_IO_BARS = 0;
NUMBER_OF_MEM32_BARS = 0;
NUMBER_OF_MEM64_BARS = 0;
end
assign trn_trem_n = trn_trem_ni[0];
reg [255:0] testname;
integer test_vars [31:0];
reg [7:0] expect_cpld_payload [4095:0];
reg [7:0] expect_msgd_payload [4095:0];
reg [7:0] expect_memwr_payload [4095:0];
reg [7:0] expect_memwr64_payload [4095:0];
reg [7:0] expect_cfgwr_payload [3:0];
reg expect_status;
reg expect_finish_check;
reg test_failed_flag;
initial begin
if ($value$plusargs("TESTNAME=%s", testname))
$display("Running test {%0s}......", testname);
else
begin
// $display("[%t] %m: No TESTNAME specified!", $realtime);
// $finish(2);
testname = "sample_smoke_test0";
$display("Running default test {%0s}......", testname);
end
expect_status = 0;
expect_finish_check = 0;
test_failed_flag = 0;
// Tx transaction interface signal initialization.
trn_td = 0;
trn_tsof_n = 1;
trn_teof_n = 1;
trn_trem_ni = 0;
trn_terrfwd_n = 1;
trn_tsrc_rdy_n = 1 ;
trn_tsrc_dsc_n = 1;
// Payload data initialization.
TSK_USR_DATA_SETUP_SEQ;
//Test starts here
if (testname == "dummy_test")
begin
$display("[%t] %m: Invalid TESTNAME: %0s", $realtime, testname);
$finish(2);
end
`include "tests.v"
else begin
$display("[%t] %m: Error: Unrecognized TESTNAME: %0s", $realtime, testname);
$finish(2);
end
end
task TSK_SYSTEM_INITIALIZATION;
begin
//--------------------------------------------------------------------------
// Event # 1: Wait for Transaction reset to be de-asserted..
//--------------------------------------------------------------------------
wait (trn_reset_n == 1);
$display("[%t] : Transaction Reset Is De-asserted...", $realtime);
//--------------------------------------------------------------------------
// Event # 2: Wait for Transaction link to be asserted..
//--------------------------------------------------------------------------
wait (trn_lnk_up_n == 0);
wait (((LINK_CAP_MAX_LINK_SPEED == 4'h2) && (speed_change_done_n == 1'b0)) || (LINK_CAP_MAX_LINK_SPEED == 4'h1))
$display("[%t] : Transaction Link Is Up...", $realtime);
TSK_SYSTEM_CONFIGURATION_CHECK;
end
endtask
/************************************************************
Task : TSK_SYSTEM_CONFIGURATION_CHECK
Description : Check that options selected from Coregen GUI are
set correctly.
Checks - Max Link Speed/Width, Device/Vendor ID, CMPS
*************************************************************/
task TSK_SYSTEM_CONFIGURATION_CHECK;
begin
error_check = 0;
// Check Link Speed/Width
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h70, 4'hF);
TSK_WAIT_FOR_READ_DATA;
if (P_READ_DATA[19:16] == LINK_CAP_MAX_LINK_SPEED) begin
if (P_READ_DATA[19:16] == 1)
$display("[%t] : Check Max Link Speed = 2.5GT/s - PASSED", $realtime);
else
$display("[%t] : Check Max Link Speed = 5.0GT/s - PASSED", $realtime);
end else begin
$display("[%t] : Check Max Link Speed - FAILED", $realtime);
$display("[%t] : Data Error Mismatch, Parameter Data %s != Read Data %x", $realtime, "2", P_READ_DATA[19:16]);
end
if (P_READ_DATA[23:20] == 4'h04)
$display("[%t] : Check Negotiated Link Width = 04x - PASSED", $realtime);
else
$display("[%t] : Data Error Mismatch, Parameter Data %s != Read Data %x", $realtime, "04", P_READ_DATA[23:20]);
// Check Device/Vendor ID
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h0, 4'hF);
TSK_WAIT_FOR_READ_DATA;
if (P_READ_DATA[31:16] != 16'h7024) begin
$display("[%t] : Check Device/Vendor ID - FAILED", $realtime);
$display("[%t] : Data Error Mismatch, Parameter Data %x != Read Data %x", $realtime, 16'h7024, P_READ_DATA);
error_check = 1;
end else begin
$display("[%t] : Check Device/Vendor ID - PASSED", $realtime);
end
// Check CMPS
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h64, 4'hF);
TSK_WAIT_FOR_READ_DATA;
if (P_READ_DATA[2:0] != 3'd3) begin
$display("[%t] : Check CMPS ID - FAILED", $realtime);
$display("[%t] : Data Error Mismatch, Parameter Data %x != Read data %x", $realtime, 3'h3, P_READ_DATA);
error_check = 1;
end else begin
$display("[%t] : Check CMPS ID - PASSED", $realtime);
end
if (error_check == 0) begin
$display("[%t] : SYSTEM CHECK PASSED", $realtime);
end else begin
$display("[%t] : SYSTEM CHECK FAILED", $realtime);
$finish;
end
end
endtask
/************************************************************
Task : TSK_TX_TYPE0_CONFIGURATION_READ
Inputs : Tag, PCI/PCI-Express Reg Address, First BypeEn
Outputs : Transaction Tx Interface Signaling
Description : Generates a Type 0 Configuration Read TLP
*************************************************************/
task TSK_TX_TYPE0_CONFIGURATION_READ;
input [7:0] tag_;
input [11:0] reg_addr_;
input [3:0] first_dw_be_;
begin
if (trn_lnk_up_n) begin
$display("[%t] : Trn interface is MIA", $realtime);
$finish(1);
end
TSK_TX_SYNCHRONIZE(0, 0);
trn_td <= #(Tcq) {
1'b0,
2'b00,
5'b00100,
1'b0,
3'b000,
4'b0000,
1'b0,
1'b0,
2'b00,
2'b00,
10'b0000000001, // 32
COMPLETER_ID_CFG,
tag_,
4'b0000,
first_dw_be_ // 64
};
trn_tsof_n <= #(Tcq) 0;
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
COMPLETER_ID_CFG,
4'b0000,
reg_addr_[11:2],
2'b00,
32'b0
};
trn_tsof_n <= #(Tcq) 1;
trn_teof_n <= #(Tcq) 0;
trn_trem_ni <= #(Tcq) 8'h0F;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 1);
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 1;
end
endtask // TSK_TX_TYPE0_CONFIGURATION_READ
/************************************************************
Task : TSK_TX_TYPE1_CONFIGURATION_READ
Inputs : Tag, PCI/PCI-Express Reg Address, First BypeEn
Outputs : Transaction Tx Interface Signaling
Description : Generates a Type 1 Configuration Read TLP
*************************************************************/
task TSK_TX_TYPE1_CONFIGURATION_READ;
input [7:0] tag_;
input [11:0] reg_addr_;
input [3:0] first_dw_be_;
begin
if (trn_lnk_up_n) begin
$display("[%t] : Trn interface is MIA", $realtime);
$finish(1);
end
TSK_TX_SYNCHRONIZE(0, 0);
trn_td <= #(Tcq) {
1'b0,
2'b00,
5'b00101,
1'b0,
3'b000,
4'b0000,
1'b0,
1'b0,
2'b00,
2'b00,
10'b0000000001, // 32
COMPLETER_ID_CFG,
tag_,
4'b0000,
first_dw_be_ // 64
};
trn_tsof_n <= #(Tcq) 0;
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
COMPLETER_ID_CFG,
4'b0000,
reg_addr_[11:2],
2'b00,
32'b0
};
trn_tsof_n <= #(Tcq) 1;
trn_teof_n <= #(Tcq) 0;
trn_trem_ni <= #(Tcq) 8'h0F;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 1);
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 1;
end
endtask // TSK_TX_TYPE1_CONFIGURATION_READ
/************************************************************
Task : TSK_TX_TYPE0_CONFIGURATION_WRITE
Inputs : Tag, PCI/PCI-Express Reg Address, First BypeEn
Outputs : Transaction Tx Interface Signaling
Description : Generates a Type 0 Configuration Write TLP
*************************************************************/
task TSK_TX_TYPE0_CONFIGURATION_WRITE;
input [7:0] tag_;
input [11:0] reg_addr_;
input [31:0] reg_data_;
input [3:0] first_dw_be_;
begin
if (trn_lnk_up_n) begin
$display("[%t] : Trn interface is MIA", $realtime);
$finish(1);
end
TSK_TX_SYNCHRONIZE(0, 0);
trn_td <= #(Tcq) {
1'b0,
2'b10,
5'b00100,
1'b0,
3'b000,
4'b0000,
1'b0,
1'b0,
2'b00,
2'b00,
10'b0000000001, // 32
COMPLETER_ID_CFG,
tag_,
4'b0000,
first_dw_be_ // 64
};
trn_tsof_n <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
COMPLETER_ID_CFG,
4'b0000,
reg_addr_[11:2],
2'b00, // 32
reg_data_[7:0],
reg_data_[15:8],
reg_data_[23:16],
reg_data_[31:24] // 64
};
trn_tsof_n <= #(Tcq) 1;
trn_teof_n <= #(Tcq) 0;
trn_trem_ni <= #(Tcq) 8'h00;
TSK_TX_SYNCHRONIZE(1, 1);
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 1;
end
endtask // TSK_TX_TYPE0_CONFIGURATION_WRITE
/************************************************************
Task : TSK_TX_TYPE1_CONFIGURATION_WRITE
Inputs : Tag, PCI/PCI-Express Reg Address, First BypeEn
Outputs : Transaction Tx Interface Signaling
Description : Generates a Type 1 Configuration Write TLP
*************************************************************/
task TSK_TX_TYPE1_CONFIGURATION_WRITE;
input [7:0] tag_;
input [11:0] reg_addr_;
input [31:0] reg_data_;
input [3:0] first_dw_be_;
begin
if (trn_lnk_up_n) begin
$display("[%t] : Trn interface is MIA", $realtime);
$finish(1);
end
TSK_TX_SYNCHRONIZE(0, 0);
trn_td <= #(Tcq) {
1'b0,
2'b10,
5'b00101,
1'b0,
3'b000,
4'b0000,
1'b0,
1'b0,
2'b00,
2'b00,
10'b0000000001, // 32
COMPLETER_ID_CFG,
tag_,
4'b0000,
first_dw_be_ // 64
};
trn_tsof_n <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
COMPLETER_ID_CFG,
4'b0000,
reg_addr_[11:2],
2'b00, // 32
reg_data_[7:0],
reg_data_[15:8],
reg_data_[23:16],
reg_data_[31:24] // 64
};
trn_tsof_n <= #(Tcq) 1;
trn_teof_n <= #(Tcq) 0;
trn_trem_ni <= #(Tcq) 8'h00;
TSK_TX_SYNCHRONIZE(1, 1);
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 1;
end
endtask // TSK_TX_TYPE1_CONFIGURATION_WRITE
/************************************************************
Task : TSK_TX_MEMORY_READ_32
Inputs : Tag, Length, Address, Last Byte En, First Byte En
Outputs : Transaction Tx Interface Signaling
Description : Generates a Memory Read 32 TLP
*************************************************************/
task TSK_TX_MEMORY_READ_32;
input [7:0] tag_;
input [2:0] tc_;
input [9:0] len_;
input [31:0] addr_;
input [3:0] last_dw_be_;
input [3:0] first_dw_be_;
begin
if (trn_lnk_up_n) begin
$display("[%t] : Trn interface is MIA", $realtime);
$finish(1);
end
TSK_TX_SYNCHRONIZE(0, 0);
trn_td <= #(Tcq) {
1'b0,
2'b00,
5'b00000,
1'b0,
tc_,
4'b0000,
1'b0,
1'b0,
2'b00,
2'b00,
len_, // 32
COMPLETER_ID_CFG,
tag_,
last_dw_be_,
first_dw_be_ // 64
};
trn_tsof_n <= #(Tcq) 0;
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
addr_[31:2],
2'b00,
32'b0
};
trn_tsof_n <= #(Tcq) 1;
trn_teof_n <= #(Tcq) 0;
trn_trem_ni <= #(Tcq) 8'h0F;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 1);
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 1;
end
endtask // TSK_TX_MEMORY_READ_32
/************************************************************
Task : TSK_TX_MEMORY_READ_64
Inputs : Tag, Length, Address, Last Byte En, First Byte En
Outputs : Transaction Tx Interface Signaling
Description : Generates a Memory Read 64 TLP
*************************************************************/
task TSK_TX_MEMORY_READ_64;
input [7:0] tag_;
input [2:0] tc_;
input [9:0] len_;
input [63:0] addr_;
input [3:0] last_dw_be_;
input [3:0] first_dw_be_;
begin
if (trn_lnk_up_n) begin
$display("[%t] : Trn interface is MIA", $realtime);
$finish(1);
end
TSK_TX_SYNCHRONIZE(0, 0);
trn_td <= #(Tcq) {
1'b0,
2'b01,
5'b00000,
1'b0,
tc_,
4'b0000,
1'b0,
1'b0,
2'b00,
2'b00,
len_, // 32
COMPLETER_ID_CFG,
tag_,
last_dw_be_,
first_dw_be_ // 64
};
trn_tsof_n <= #(Tcq) 0;
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
addr_[63:2],
2'b00
};
trn_tsof_n <= #(Tcq) 1;
trn_teof_n <= #(Tcq) 0;
trn_trem_ni <= #(Tcq) 8'h00;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 1);
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 1;
end
endtask // TSK_TX_MEMORY_READ_64
/************************************************************
Task : TSK_TX_MEMORY_WRITE_32
Inputs : Tag, Length, Address, Last Byte En, First Byte En
Outputs : Transaction Tx Interface Signaling
Description : Generates a Memory Write 32 TLP
*************************************************************/
task TSK_TX_MEMORY_WRITE_32;
input [7:0] tag_;
input [2:0] tc_;
input [9:0] len_;
input [31:0] addr_;
input [3:0] last_dw_be_;
input [3:0] first_dw_be_;
input ep_;
reg [10:0] _len;
integer _j;
begin
if (len_ == 0)
_len = 1024;
else
_len = len_;
if (trn_lnk_up_n) begin
$display("[%t] : Trn interface is MIA", $realtime);
$finish(1);
end
TSK_TX_SYNCHRONIZE(0, 0);
trn_td <= #(Tcq) {
1'b0,
2'b10,
5'b00000,
1'b0,
tc_,
4'b0000,
1'b0,
1'b0,
2'b00,
2'b00,
len_, // 32
COMPLETER_ID_CFG,
tag_,
last_dw_be_,
first_dw_be_ // 64
};
trn_tsof_n <= #(Tcq) 0;
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
addr_[31:2],
2'b00,
DATA_STORE[0],
DATA_STORE[1],
DATA_STORE[2],
DATA_STORE[3]
};
trn_tsof_n <= #(Tcq) 1;
if (_len != 1) begin
for (_j = 4; _j < (_len * 4); _j = _j + 8) begin
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
DATA_STORE[_j + 0],
DATA_STORE[_j + 1],
DATA_STORE[_j + 2],
DATA_STORE[_j + 3],
DATA_STORE[_j + 4],
DATA_STORE[_j + 5],
DATA_STORE[_j + 6],
DATA_STORE[_j + 7]
};
if ((_j + 7) >= ((_len * 4) - 1)) begin
trn_teof_n <= #(Tcq) 0;
if (ep_)
trn_terrfwd_n <= #(Tcq) 0;
if (((_len - 1) % 2) == 0)
trn_trem_ni <= #(Tcq) 8'h00;
else
trn_trem_ni <= #(Tcq) 8'h0f;
end
end
end else begin
trn_teof_n <= #(Tcq) 0;
if (ep_)
trn_terrfwd_n <= #(Tcq) 0;
trn_trem_ni <= #(Tcq) 8'h00;
end
TSK_TX_SYNCHRONIZE(1, 1);
trn_teof_n <= #(Tcq) 1;
trn_terrfwd_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 1;
end
endtask // TSK_TX_MEMORY_WRITE_32
/************************************************************
Task : TSK_TX_MEMORY_WRITE_64
Inputs : Tag, Length, Address, Last Byte En, First Byte En
Outputs : Transaction Tx Interface Signaling
Description : Generates a Memory Write 64 TLP
*************************************************************/
task TSK_TX_MEMORY_WRITE_64;
input [7:0] tag_;
input [2:0] tc_;
input [9:0] len_;
input [63:0] addr_;
input [3:0] last_dw_be_;
input [3:0] first_dw_be_;
input ep_;
reg [10:0] _len;
integer _j;
begin
if (len_ == 0)
_len = 1024;
else
_len = len_;
if (trn_lnk_up_n) begin
$display("[%t] : Trn interface is MIA", $realtime);
$finish(1);
end
TSK_TX_SYNCHRONIZE(0, 0);
trn_td <= #(Tcq) {
1'b0,
2'b11,
5'b00000,
1'b0,
tc_,
4'b0000,
1'b0,
1'b0,
2'b00,
2'b00,
len_, // 32
COMPLETER_ID_CFG,
tag_,
last_dw_be_,
first_dw_be_ // 64
};
trn_tsof_n <= #(Tcq) 0;
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
addr_[63:2],
2'b00
};
trn_tsof_n <= #(Tcq) 1;
for (_j = 0; _j < (_len * 4); _j = _j + 8) begin
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
DATA_STORE[_j + 0],
DATA_STORE[_j + 1],
DATA_STORE[_j + 2],
DATA_STORE[_j + 3],
DATA_STORE[_j + 4],
DATA_STORE[_j + 5],
DATA_STORE[_j + 6],
DATA_STORE[_j + 7]
};
if ((_j + 7) >= ((_len * 4) - 1)) begin
trn_teof_n <= #(Tcq) 0;
if (ep_)
trn_terrfwd_n <= #(Tcq) 0;
if ((_len % 2) == 0)
trn_trem_ni <= #(Tcq) 8'h00;
else
trn_trem_ni <= #(Tcq) 8'h0f;
end
end
TSK_TX_SYNCHRONIZE(1, 1);
trn_teof_n <= #(Tcq) 1;
trn_terrfwd_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 1;
end
endtask // TSK_TX_MEMORY_WRITE_64
/************************************************************
Task : TSK_TX_COMPLETION
Inputs : Tag, TC, Length, Completion ID
Outputs : Transaction Tx Interface Signaling
Description : Generates a Completion TLP
*************************************************************/
task TSK_TX_COMPLETION;
input [7:0] tag_;
input [2:0] tc_;
input [9:0] len_;
input [2:0] comp_status_;
begin
if (trn_lnk_up_n) begin
$display("[%t] : Trn interface is MIA", $realtime);
$finish(1);
end
TSK_TX_SYNCHRONIZE(0, 0);
trn_td <= #(Tcq) {
1'b0,
2'b00,
5'b01010,
1'b0,
tc_,
4'b0000,
1'b0,
1'b0,
2'b00,
2'b00,
len_, // 32
COMPLETER_ID_CFG,
comp_status_,
1'b0,
12'b0
};
trn_tsof_n <= #(Tcq) 0;
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
REQUESTER_ID,
tag_,
8'b00,
32'b0
};
trn_tsof_n <= #(Tcq) 1;
trn_teof_n <= #(Tcq) 0;
trn_trem_ni <= #(Tcq) 8'h0F;
TSK_TX_SYNCHRONIZE(1, 1);
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 1;
end
endtask // TSK_TX_COMPLETION
/************************************************************
Task : TSK_TX_COMPLETION_DATA
Inputs : Tag, TC, Length, Completion ID
Outputs : Transaction Tx Interface Signaling
Description : Generates a Completion TLP
*************************************************************/
task TSK_TX_COMPLETION_DATA;
input [7:0] tag_;
input [2:0] tc_;
input [9:0] len_;
input [11:0] byte_count_;
input [6:0] lower_addr_;
input [2:0] comp_status_;
input ep_;
reg [10:0] _len;
integer _j;
begin
if (len_ == 0)
_len = 1024;
else
_len = len_;
if (trn_lnk_up_n) begin
$display("[%t] : Trn interface is MIA", $realtime);
$finish(1);
end
TSK_TX_SYNCHRONIZE(0, 0);
trn_td <= #(Tcq) {
1'b0,
2'b10,
5'b01010,
1'b0,
tc_,
4'b0000,
1'b0,
1'b0,
2'b00,
2'b00,
len_, // 32
COMPLETER_ID_CFG,
comp_status_,
1'b0,
byte_count_ // 64
};
trn_tsof_n <= #(Tcq) 0;
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
REQUESTER_ID,
tag_,
1'b0,
lower_addr_,
DATA_STORE[0],
DATA_STORE[1],
DATA_STORE[2],
DATA_STORE[3]
};
trn_tsof_n <= #(Tcq) 1;
if (_len != 1) begin
for (_j = 4; _j < (_len * 4); _j = _j + 8) begin
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
DATA_STORE[_j + 0],
DATA_STORE[_j + 1],
DATA_STORE[_j + 2],
DATA_STORE[_j + 3],
DATA_STORE[_j + 4],
DATA_STORE[_j + 5],
DATA_STORE[_j + 6],
DATA_STORE[_j + 7]
};
if ((_j + 7) >= ((_len * 4) - 1)) begin
trn_teof_n <= #(Tcq) 0;
if (ep_)
trn_terrfwd_n <= #(Tcq) 0;
if (((_len - 1) % 2) == 0)
trn_trem_ni <= #(Tcq) 8'h00;
else
trn_trem_ni <= #(Tcq) 8'h0f;
end
end
end else begin
trn_teof_n <= #(Tcq) 0;
trn_trem_ni <= #(Tcq) 8'h00;
end
TSK_TX_SYNCHRONIZE(1, 1);
trn_teof_n <= #(Tcq) 1;
trn_terrfwd_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 1;
end
endtask // TSK_TX_COMPLETION_DATA
/************************************************************
Task : TSK_TX_MESSAGE
Inputs : Tag, TC, Address, Message Routing, Message Code
Outputs : Transaction Tx Interface Signaling
Description : Generates a Message TLP
*************************************************************/
task TSK_TX_MESSAGE;
input [7:0] tag_;
input [2:0] tc_;
input [9:0] len_;
input [63:0] data_;
input [2:0] message_rtg_;
input [7:0] message_code_;
begin
if (trn_lnk_up_n) begin
$display("[%t] : Trn interface is MIA", $realtime);
$finish(1);
end
TSK_TX_SYNCHRONIZE(0, 0);
trn_td <= #(Tcq) {
1'b0,
2'b01,
{{2'b10}, {message_rtg_}},
1'b0,
tc_,
4'b0000,
1'b0,
1'b0,
2'b00,
2'b00,
10'b0, // 32
COMPLETER_ID_CFG,
tag_,
message_code_ // 64
};
trn_tsof_n <= #(Tcq) 0;
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
data_
};
trn_tsof_n <= #(Tcq) 1;
trn_teof_n <= #(Tcq) 0;
trn_trem_ni <= #(Tcq) 8'h00;
TSK_TX_SYNCHRONIZE(1, 1);
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 1;
end
endtask // TSK_TX_MESSAGE
/************************************************************
Task : TSK_TX_MESSAGE_DATA
Inputs : Tag, TC, Address, Message Routing, Message Code
Outputs : Transaction Tx Interface Signaling
Description : Generates a Message Data TLP
*************************************************************/
task TSK_TX_MESSAGE_DATA;
input [7:0] tag_;
input [2:0] tc_;
input [9:0] len_;
input [63:0] data_;
input [2:0] message_rtg_;
input [7:0] message_code_;
reg [10:0] _len;
integer _j;
begin
if (len_ == 0)
_len = 1024;
else
_len = len_;
if (trn_lnk_up_n) begin
$display("[%t] : Trn interface is MIA", $realtime);
$finish(1);
end
TSK_TX_SYNCHRONIZE(0, 0);
trn_td <= #(Tcq) {
1'b0,
2'b11,
{{2'b10}, {message_rtg_}},
1'b0,
tc_,
4'b0000,
1'b0,
1'b0,
2'b00,
2'b00,
len_, // 32
COMPLETER_ID_CFG,
tag_,
message_code_ // 64
};
trn_tsof_n <= #(Tcq) 0;
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
data_
};
trn_tsof_n <= #(Tcq) 1;
for (_j = 0; _j < (_len * 4); _j = _j + 8) begin
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
DATA_STORE[_j + 0],
DATA_STORE[_j + 1],
DATA_STORE[_j + 2],
DATA_STORE[_j + 3],
DATA_STORE[_j + 4],
DATA_STORE[_j + 5],
DATA_STORE[_j + 6],
DATA_STORE[_j + 7]
};
if ((_j + 7) >= ((_len * 4) - 1)) begin
trn_teof_n <= #(Tcq) 0;
if ((_len % 2) == 0)
trn_trem_ni <= #(Tcq) 8'h00;
else
trn_trem_ni <= #(Tcq) 8'h0f;
end
end
TSK_TX_SYNCHRONIZE(1, 1);
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 1;
end
endtask // TSK_TX_MESSAGE_DATA
/************************************************************
Task : TSK_TX_IO_READ
Inputs : Tag, Address
Outputs : Transaction Tx Interface Signaling
Description : Generates a IO Read TLP
*************************************************************/
task TSK_TX_IO_READ;
input [7:0] tag_;
input [31:0] addr_;
input [3:0] first_dw_be_;
begin
if (trn_lnk_up_n) begin
$display("[%t] : Trn interface is MIA", $realtime);
$finish(1);
end
TSK_TX_SYNCHRONIZE(0, 0);
trn_td <= #(Tcq) {
1'b0,
2'b00,
5'b00010,
1'b0,
3'b000,
4'b0000,
1'b0,
1'b0,
2'b00,
2'b00,
10'b1, // 32
COMPLETER_ID_CFG,
tag_,
4'b0,
first_dw_be_ // 64
};
trn_tsof_n <= #(Tcq) 0;
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
addr_[31:2],
2'b00,
32'b0
};
trn_tsof_n <= #(Tcq) 1;
trn_teof_n <= #(Tcq) 0;
trn_trem_ni <= #(Tcq) 8'h0F;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 1);
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 1;
end
endtask // TSK_TX_IO_READ
/************************************************************
Task : TSK_TX_IO_WRITE
Inputs : Tag, Address, Data
Outputs : Transaction Tx Interface Signaling
Description : Generates a IO Read TLP
*************************************************************/
task TSK_TX_IO_WRITE;
input [7:0] tag_;
input [31:0] addr_;
input [3:0] first_dw_be_;
input [31:0] data_;
begin
if (trn_lnk_up_n) begin
$display("[%t] : Trn interface is MIA", $realtime);
$finish(1);
end
TSK_TX_SYNCHRONIZE(0, 0);
trn_td <= #(Tcq) {
1'b0,
2'b10,
5'b00010,
1'b0,
3'b000,
4'b0000,
1'b0,
1'b0,
2'b00,
2'b00,
10'b1, // 32
COMPLETER_ID_CFG,
tag_,
4'b0,
first_dw_be_ // 64
};
trn_tsof_n <= #(Tcq) 0;
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 0);
trn_td <= #(Tcq) {
addr_[31:2],
2'b00,
data_[7:0],
data_[15:8],
data_[23:16],
data_[31:24]
};
trn_tsof_n <= #(Tcq) 1;
trn_teof_n <= #(Tcq) 0;
trn_trem_ni <= #(Tcq) 8'h00;
trn_tsrc_rdy_n <= #(Tcq) 0 ;
TSK_TX_SYNCHRONIZE(1, 1);
trn_teof_n <= #(Tcq) 1;
trn_trem_ni <= #(Tcq) 0;
trn_tsrc_rdy_n <= #(Tcq) 1;
end
endtask // TSK_TX_IO_WRITE
/************************************************************
Task : TSK_TX_SYNCHRONIZE
Inputs : None
Outputs : None
Description : Synchronize with tx clock and handshake signals
*************************************************************/
task TSK_TX_SYNCHRONIZE;
input first_;
input last_call_;
reg last_;
begin
if (trn_lnk_up_n) begin
$display("[%t] : Trn interface is MIA", $realtime);
$finish(1);
end
@(posedge trn_clk);
if ((trn_tdst_rdy_n == 1'b1) && (first_ == 1'b1)) begin
while (trn_tdst_rdy_n == 1'b1) begin
@(posedge trn_clk);
end
end
if (first_ == 1'b1) begin
last_ = (trn_trem_ni == 8'h00) ? 0 : 1;
// read data driven into memory
board.RP.com_usrapp.TSK_READ_DATA(last_,
`TX_LOG,
trn_td,
trn_trem_ni);
end
if (last_call_)
board.RP.com_usrapp.TSK_PARSE_FRAME(`TX_LOG);
end
endtask // TSK_TX_SYNCHRONIZE
/************************************************************
Task : TSK_USR_DATA_SETUP_SEQ
Inputs : None
Outputs : None
Description : Populates scratch pad data area with known good data.
*************************************************************/
task TSK_USR_DATA_SETUP_SEQ;
integer i_;
begin
for (i_ = 0; i_ <= 4095; i_ = i_ + 1) begin
DATA_STORE[i_] = i_;
end
end
endtask // TSK_USR_DATA_SETUP_SEQ
/************************************************************
Task : TSK_TX_CLK_EAT
Inputs : None
Outputs : None
Description : Consume clocks.
*************************************************************/
task TSK_TX_CLK_EAT;
input [31:0] clock_count;
integer i_;
begin
for (i_ = 0; i_ < clock_count; i_ = i_ + 1) begin
@(posedge trn_clk);
end
end
endtask // TSK_TX_CLK_EAT
/************************************************************
Task: TSK_SIMULATION_TIMEOUT
Description: Set simulation timeout value
*************************************************************/
task TSK_SIMULATION_TIMEOUT;
input [31:0] timeout;
begin
force board.RP.rx_usrapp.sim_timeout = timeout;
end
endtask
/************************************************************
Task : TSK_TX_BAR_READ
Inputs : Tag, Length, Address, Last Byte En, First Byte En
Outputs : Transaction Tx Interface Signaling
Description : Generates a Memory Read 32,64 or IO Read TLP
requesting 1 dword
*************************************************************/
task TSK_TX_BAR_READ;
input [2:0] bar_index;
input [31:0] byte_offset;
input [7:0] tag_;
input [2:0] tc_;
begin
case(BAR_INIT_P_BAR_ENABLED[bar_index])
2'b01 : // IO SPACE
begin
if (verbose) $display("[%t] : IOREAD, address = %x", $realtime,
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset));
TSK_TX_IO_READ(tag_, BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset), 4'hF);
end
2'b10 : // MEM 32 SPACE
begin
if (verbose) $display("[%t] : MEMREAD32, address = %x", $realtime,
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset));
TSK_TX_MEMORY_READ_32(tag_, tc_, 10'd1,
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset), 4'h0, 4'hF);
end
2'b11 : // MEM 64 SPACE
begin
if (verbose) $display("[%t] : MEMREAD64, address = %x", $realtime,
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset));
TSK_TX_MEMORY_READ_64(tag_, tc_, 10'd1, {BAR_INIT_P_BAR[ii+1][31:0],
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset)}, 4'h0, 4'hF);
end
default : begin
$display("Error case in task TSK_TX_BAR_READ");
end
endcase
end
endtask // TSK_TX_BAR_READ
/************************************************************
Task : TSK_TX_BAR_WRITE
Inputs : Bar Index, Byte Offset, Tag, Tc, 32 bit Data
Outputs : Transaction Tx Interface Signaling
Description : Generates a Memory Write 32, 64, IO TLP with
32 bit data
*************************************************************/
task TSK_TX_BAR_WRITE;
input [2:0] bar_index;
input [31:0] byte_offset;
input [7:0] tag_;
input [2:0] tc_;
input [31:0] data_;
begin
case(BAR_INIT_P_BAR_ENABLED[bar_index])
2'b01 : // IO SPACE
begin
if (verbose) $display("[%t] : IOWRITE, address = %x, Write Data %x", $realtime,
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset), data_);
TSK_TX_IO_WRITE(tag_, BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset), 4'hF, data_);
end
2'b10 : // MEM 32 SPACE
begin
DATA_STORE[0] = data_[7:0];
DATA_STORE[1] = data_[15:8];
DATA_STORE[2] = data_[23:16];
DATA_STORE[3] = data_[31:24];
if (verbose) $display("[%t] : MEMWRITE32, address = %x, Write Data %x", $realtime,
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset), data_);
TSK_TX_MEMORY_WRITE_32(tag_, tc_, 10'd1,
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset), 4'h0, 4'hF, 1'b0);
end
2'b11 : // MEM 64 SPACE
begin
DATA_STORE[0] = data_[7:0];
DATA_STORE[1] = data_[15:8];
DATA_STORE[2] = data_[23:16];
DATA_STORE[3] = data_[31:24];
if (verbose) $display("[%t] : MEMWRITE64, address = %x, Write Data %x", $realtime,
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset), data_);
TSK_TX_MEMORY_WRITE_64(tag_, tc_, 10'd1, {BAR_INIT_P_BAR[bar_index+1][31:0],
BAR_INIT_P_BAR[bar_index][31:0]+(byte_offset)}, 4'h0, 4'hF, 1'b0);
end
default : begin
$display("Error case in task TSK_TX_BAR_WRITE");
end
endcase
end
endtask // TSK_TX_BAR_WRITE
/************************************************************
Task : TSK_SET_READ_DATA
Inputs : Data
Outputs : None
Description : Called from common app. Common app hands read
data to usrapp_tx.
*************************************************************/
task TSK_SET_READ_DATA;
input [3:0] be_; // not implementing be's yet
input [31:0] data_; // might need to change this to byte
begin
P_READ_DATA = data_;
p_read_data_valid = 1;
end
endtask // TSK_SET_READ_DATA
/************************************************************
Task : TSK_WAIT_FOR_READ_DATA
Inputs : None
Outputs : Read data P_READ_DATA will be valid
Description : Called from tx app. Common app hands read
data to usrapp_tx. This task must be executed
immediately following a call to
TSK_TX_TYPE0_CONFIGURATION_READ in order for the
read process to function correctly. Otherwise
there is a potential race condition with
p_read_data_valid.
*************************************************************/
task TSK_WAIT_FOR_READ_DATA;
integer j;
begin
j = 10;
p_read_data_valid = 0;
fork
while ((!p_read_data_valid) && (cpld_to == 0)) @(posedge trn_clk);
begin // second process
while ((j > 0) && (!p_read_data_valid))
begin
TSK_TX_CLK_EAT(500);
j = j - 1;
end
if (!p_read_data_valid) begin
cpld_to = 1;
if (cpld_to_finish == 1) begin
$display("TIMEOUT ERROR in usrapp_tx:TSK_WAIT_FOR_READ_DATA. Completion data never received.");
$finish;
end
else
$display("TIMEOUT WARNING in usrapp_tx:TSK_WAIT_FOR_READ_DATA. Completion data never received.");
end
end
join
end
endtask // TSK_WAIT_FOR_READ_DATA
/************************************************************
Function : TSK_DISPLAY_PCIE_MAP
Inputs : none
Outputs : none
Description : Displays the Memory Manager's P_MAP calculations
based on range values read from PCI_E device.
*************************************************************/
task TSK_DISPLAY_PCIE_MAP;
reg[2:0] ii;
begin
for (ii=0; ii <= 6; ii = ii + 1) begin
if (ii !=6) begin
$display("\tBAR %x: VALUE = %x RANGE = %x TYPE = %s", ii, BAR_INIT_P_BAR[ii][31:0],
BAR_INIT_P_BAR_RANGE[ii], BAR_INIT_MESSAGE[BAR_INIT_P_BAR_ENABLED[ii]]);
end
else begin
$display("\tEROM : VALUE = %x RANGE = %x TYPE = %s", BAR_INIT_P_BAR[6][31:0],
BAR_INIT_P_BAR_RANGE[6], BAR_INIT_MESSAGE[BAR_INIT_P_BAR_ENABLED[6]]);
end
end
end
endtask
/************************************************************
Task : TSK_BUILD_PCIE_MAP
Inputs :
Outputs :
Description : Looks at range values read from config space and
builds corresponding mem/io map
*************************************************************/
task TSK_BUILD_PCIE_MAP;
integer ii;
begin
$display("[%t] PCI EXPRESS BAR MEMORY/IO MAPPING PROCESS BEGUN...",$realtime);
// handle bars 0-6 (including erom)
for (ii = 0; ii <= 6; ii = ii + 1) begin
if (BAR_INIT_P_BAR_RANGE[ii] != 32'h0000_0000) begin
if ((ii != 6) && (BAR_INIT_P_BAR_RANGE[ii] & 32'h0000_0001)) begin // if not erom and io bit set
// bar is io mapped
NUMBER_OF_IO_BARS = NUMBER_OF_IO_BARS + 1;
if (pio_check_design && (NUMBER_OF_IO_BARS > 1)) begin
$display("[%t] Warning: PIO design only supports 1 IO BAR. Testbench will disable BAR %x",$realtime, ii);
BAR_INIT_P_BAR_ENABLED[ii] = 2'h0; // disable BAR
end
else BAR_INIT_P_BAR_ENABLED[ii] = 2'h1;
if (!OUT_OF_IO) begin
// We need to calculate where the next BAR should start based on the BAR's range
BAR_INIT_TEMP = BAR_INIT_P_IO_START & {1'b1,(BAR_INIT_P_BAR_RANGE[ii] & 32'hffff_fff0)};
if (BAR_INIT_TEMP < BAR_INIT_P_IO_START) begin
// Current BAR_INIT_P_IO_START is NOT correct start for new base
BAR_INIT_P_BAR[ii] = BAR_INIT_TEMP + FNC_CONVERT_RANGE_TO_SIZE_32(ii);
BAR_INIT_P_IO_START = BAR_INIT_P_BAR[ii] + FNC_CONVERT_RANGE_TO_SIZE_32(ii);
end
else begin
// Initial BAR case and Current BAR_INIT_P_IO_START is correct start for new base
BAR_INIT_P_BAR[ii] = BAR_INIT_P_IO_START;
BAR_INIT_P_IO_START = BAR_INIT_P_IO_START + FNC_CONVERT_RANGE_TO_SIZE_32(ii);
end
OUT_OF_IO = BAR_INIT_P_BAR[ii][32];
if (OUT_OF_IO) begin
$display("\tOut of PCI EXPRESS IO SPACE due to BAR %x", ii);
end
end
else begin
$display("\tOut of PCI EXPRESS IO SPACE due to BAR %x", ii);
end
end // bar is io mapped
else begin
// bar is mem mapped
if ((ii != 5) && (BAR_INIT_P_BAR_RANGE[ii] & 32'h0000_0004)) begin
// bar is mem64 mapped - memManager is not handling out of 64bit memory
NUMBER_OF_MEM64_BARS = NUMBER_OF_MEM64_BARS + 1;
if (pio_check_design && (NUMBER_OF_MEM64_BARS > 1)) begin
$display("[%t] Warning: PIO design only supports 1 MEM64 BAR. Testbench will disable BAR %x",$realtime, ii);
BAR_INIT_P_BAR_ENABLED[ii] = 2'h0; // disable BAR
end
else BAR_INIT_P_BAR_ENABLED[ii] = 2'h3; // bar is mem64 mapped
if ( (BAR_INIT_P_BAR_RANGE[ii] & 32'hFFFF_FFF0) == 32'h0000_0000) begin
// Mem64 space has range larger than 2 Gigabytes
// calculate where the next BAR should start based on the BAR's range
BAR_INIT_TEMP = BAR_INIT_P_MEM64_HI_START & BAR_INIT_P_BAR_RANGE[ii+1];
if (BAR_INIT_TEMP < BAR_INIT_P_MEM64_HI_START) begin
// Current MEM32_START is NOT correct start for new base
BAR_INIT_P_BAR[ii+1] = BAR_INIT_TEMP + FNC_CONVERT_RANGE_TO_SIZE_HI32(ii+1);
BAR_INIT_P_BAR[ii] = 32'h0000_0000;
BAR_INIT_P_MEM64_HI_START = BAR_INIT_P_BAR[ii+1] + FNC_CONVERT_RANGE_TO_SIZE_HI32(ii+1);
BAR_INIT_P_MEM64_LO_START = 32'h0000_0000;
end
else begin
// Initial BAR case and Current MEM32_START is correct start for new base
BAR_INIT_P_BAR[ii] = 32'h0000_0000;
BAR_INIT_P_BAR[ii+1] = BAR_INIT_P_MEM64_HI_START;
BAR_INIT_P_MEM64_HI_START = BAR_INIT_P_MEM64_HI_START + FNC_CONVERT_RANGE_TO_SIZE_HI32(ii+1);
end
end
else begin
// Mem64 space has range less than/equal 2 Gigabytes
// calculate where the next BAR should start based on the BAR's range
BAR_INIT_TEMP = BAR_INIT_P_MEM64_LO_START & (BAR_INIT_P_BAR_RANGE[ii] & 32'hffff_fff0);
if (BAR_INIT_TEMP < BAR_INIT_P_MEM64_LO_START) begin
// Current MEM32_START is NOT correct start for new base
BAR_INIT_P_BAR[ii] = BAR_INIT_TEMP + FNC_CONVERT_RANGE_TO_SIZE_32(ii);
BAR_INIT_P_BAR[ii+1] = BAR_INIT_P_MEM64_HI_START;
BAR_INIT_P_MEM64_LO_START = BAR_INIT_P_BAR[ii] + FNC_CONVERT_RANGE_TO_SIZE_32(ii);
end
else begin
// Initial BAR case and Current MEM32_START is correct start for new base
BAR_INIT_P_BAR[ii] = BAR_INIT_P_MEM64_LO_START;
BAR_INIT_P_BAR[ii+1] = BAR_INIT_P_MEM64_HI_START;
BAR_INIT_P_MEM64_LO_START = BAR_INIT_P_MEM64_LO_START + FNC_CONVERT_RANGE_TO_SIZE_32(ii);
end
end
// skip over the next bar since it is being used by the 64bit bar
ii = ii + 1;
end
else begin
if ( (ii != 6) || ((ii == 6) && (BAR_INIT_P_BAR_RANGE[ii] & 32'h0000_0001)) ) begin
// handling general mem32 case and erom case
// bar is mem32 mapped
if (ii != 6) begin
NUMBER_OF_MEM32_BARS = NUMBER_OF_MEM32_BARS + 1; // not counting erom space
if (pio_check_design && (NUMBER_OF_MEM32_BARS > 1)) begin
// PIO design only supports 1 general purpose MEM32 BAR (not including EROM).
$display("[%t] Warning: PIO design only supports 1 MEM32 BAR. Testbench will disable BAR %x",$realtime, ii);
BAR_INIT_P_BAR_ENABLED[ii] = 2'h0; // disable BAR
end
else BAR_INIT_P_BAR_ENABLED[ii] = 2'h2; // bar is mem32 mapped
end
else BAR_INIT_P_BAR_ENABLED[ii] = 2'h2; // erom bar is mem32 mapped
if (!OUT_OF_LO_MEM) begin
// We need to calculate where the next BAR should start based on the BAR's range
BAR_INIT_TEMP = BAR_INIT_P_MEM32_START & {1'b1,(BAR_INIT_P_BAR_RANGE[ii] & 32'hffff_fff0)};
if (BAR_INIT_TEMP < BAR_INIT_P_MEM32_START) begin
// Current MEM32_START is NOT correct start for new base
BAR_INIT_P_BAR[ii] = BAR_INIT_TEMP + FNC_CONVERT_RANGE_TO_SIZE_32(ii);
BAR_INIT_P_MEM32_START = BAR_INIT_P_BAR[ii] + FNC_CONVERT_RANGE_TO_SIZE_32(ii);
end
else begin
// Initial BAR case and Current MEM32_START is correct start for new base
BAR_INIT_P_BAR[ii] = BAR_INIT_P_MEM32_START;
BAR_INIT_P_MEM32_START = BAR_INIT_P_MEM32_START + FNC_CONVERT_RANGE_TO_SIZE_32(ii);
end
if (ii == 6) begin
// make sure to set enable bit if we are mapping the erom space
BAR_INIT_P_BAR[ii] = BAR_INIT_P_BAR[ii] | 33'h1;
end
OUT_OF_LO_MEM = BAR_INIT_P_BAR[ii][32];
if (OUT_OF_LO_MEM) begin
$display("\tOut of PCI EXPRESS MEMORY 32 SPACE due to BAR %x", ii);
end
end
else begin
$display("\tOut of PCI EXPRESS MEMORY 32 SPACE due to BAR %x", ii);
end
end
end
end
end
end
if ( (OUT_OF_IO) | (OUT_OF_LO_MEM) | (OUT_OF_HI_MEM)) begin
TSK_DISPLAY_PCIE_MAP;
$display("ERROR: Ending simulation: Memory Manager is out of memory/IO to allocate to PCI Express device");
$finish;
end
end
endtask // TSK_BUILD_PCIE_MAP
/************************************************************
Task : TSK_BAR_SCAN
Inputs : None
Outputs : None
Description : Scans PCI core's configuration registers.
*************************************************************/
task TSK_BAR_SCAN;
begin
//--------------------------------------------------------------------------
// Write PCI_MASK to bar's space via PCIe fabric interface to find range
//--------------------------------------------------------------------------
P_ADDRESS_MASK = 32'hffff_ffff;
DEFAULT_TAG = 0;
DEFAULT_TC = 0;
$display("[%t] : Inspecting Core Configuration Space...", $realtime);
// Determine Range for BAR0
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h10, P_ADDRESS_MASK, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Read BAR0 Range
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h10, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_WAIT_FOR_READ_DATA;
BAR_INIT_P_BAR_RANGE[0] = P_READ_DATA;
// Determine Range for BAR1
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h14, P_ADDRESS_MASK, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Read BAR1 Range
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h14, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_WAIT_FOR_READ_DATA;
BAR_INIT_P_BAR_RANGE[1] = P_READ_DATA;
// Determine Range for BAR2
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h18, P_ADDRESS_MASK, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Read BAR2 Range
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h18, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_WAIT_FOR_READ_DATA;
BAR_INIT_P_BAR_RANGE[2] = P_READ_DATA;
// Determine Range for BAR3
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h1C, P_ADDRESS_MASK, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Read BAR3 Range
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h1C, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_WAIT_FOR_READ_DATA;
BAR_INIT_P_BAR_RANGE[3] = P_READ_DATA;
// Determine Range for BAR4
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h20, P_ADDRESS_MASK, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Read BAR4 Range
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h20, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_WAIT_FOR_READ_DATA;
BAR_INIT_P_BAR_RANGE[4] = P_READ_DATA;
// Determine Range for BAR5
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h24, P_ADDRESS_MASK, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Read BAR5 Range
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h24, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_WAIT_FOR_READ_DATA;
BAR_INIT_P_BAR_RANGE[5] = P_READ_DATA;
// Determine Range for Expansion ROM BAR
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h30, P_ADDRESS_MASK, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Read Expansion ROM BAR Range
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h30, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_WAIT_FOR_READ_DATA;
BAR_INIT_P_BAR_RANGE[6] = P_READ_DATA;
end
endtask // TSK_BAR_SCAN
/************************************************************
Task : TSK_BAR_PROGRAM
Inputs : None
Outputs : None
Description : Program's PCI core's configuration registers.
*************************************************************/
task TSK_BAR_PROGRAM;
begin
//--------------------------------------------------------------------------
// Write core configuration space via PCIe fabric interface
//--------------------------------------------------------------------------
DEFAULT_TAG = 0;
P_DEV_BDF = 16'h00_0_0;
$display("[%t] : Setting Core Configuration Space...", $realtime);
// Program BAR0
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h10, BAR_INIT_P_BAR[0][31:0], 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Program BAR1
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h14, BAR_INIT_P_BAR[1][31:0], 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Program BAR2
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h18, BAR_INIT_P_BAR[2][31:0], 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Program BAR3
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h1C, BAR_INIT_P_BAR[3][31:0], 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Program BAR4
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h20, BAR_INIT_P_BAR[4][31:0], 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Program BAR5
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h24, BAR_INIT_P_BAR[5][31:0], 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Program Expansion ROM BAR
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h30, BAR_INIT_P_BAR[6][31:0], 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Program PCI Command Register
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h04, 32'h00000003, 4'h1);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Program PCIe Device Control Register
TSK_TX_TYPE0_CONFIGURATION_WRITE(DEFAULT_TAG, 12'h68, 32'h0000005f, 4'h1);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(1000);
end
endtask // TSK_BAR_PROGRAM
/************************************************************
Task : TSK_BAR_INIT
Inputs : None
Outputs : None
Description : Initialize PCI core based on core's configuration.
*************************************************************/
task TSK_BAR_INIT;
begin
TSK_BAR_SCAN;
TSK_BUILD_PCIE_MAP;
TSK_DISPLAY_PCIE_MAP;
TSK_BAR_PROGRAM;
end
endtask // TSK_BAR_INIT
/************************************************************
Task : TSK_TX_READBACK_CONFIG
Inputs : None
Outputs : None
Description : Read core configuration space via PCIe fabric interface
*************************************************************/
task TSK_TX_READBACK_CONFIG;
begin
//--------------------------------------------------------------------------
// Read core configuration space via PCIe fabric interface
//--------------------------------------------------------------------------
$display("[%t] : Reading Core Configuration Space...", $realtime);
// Read BAR0
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h10, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Read BAR1
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h14, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Read BAR2
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h18, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Read BAR3
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h1C, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Read BAR4
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h20, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Read BAR5
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h24, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Read Expansion ROM BAR
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h30, 4'hF);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Read PCI Command Register
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h04, 4'h1);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(100);
// Read PCIe Device Control Register
TSK_TX_TYPE0_CONFIGURATION_READ(DEFAULT_TAG, 12'h60, 4'h1);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_CLK_EAT(1000);
end
endtask // TSK_TX_READBACK_CONFIG
/************************************************************
Task : TSK_CFG_READBACK_CONFIG
Inputs : None
Outputs : None
Description : Read core configuration space via CFG interface
*************************************************************/
task TSK_CFG_READBACK_CONFIG;
begin
//--------------------------------------------------------------------------
// Read core configuration space via configuration (host) interface
//--------------------------------------------------------------------------
$display("[%t] : Reading Local Configuration Space via CFG interface...", $realtime);
CFG_DWADDR = 10'h0;
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
CFG_DWADDR = 10'h4;
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
CFG_DWADDR = 10'h5;
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
CFG_DWADDR = 10'h6;
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
CFG_DWADDR = 10'h7;
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
CFG_DWADDR = 10'h8;
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
CFG_DWADDR = 10'h9;
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
CFG_DWADDR = 10'hc;
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
CFG_DWADDR = 10'h17;
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
CFG_DWADDR = 10'h18;
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
CFG_DWADDR = 10'h19;
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
CFG_DWADDR = 10'h1a;
board.RP.cfg_usrapp.TSK_READ_CFG_DW(CFG_DWADDR);
end
endtask // TSK_CFG_READBACK_CONFIG
/************************************************************
Task : TSK_MEM_TEST_DATA_BUS
Inputs : bar_index
Outputs : None
Description : Test the data bus wiring in a specific memory
by executing a walking 1's test at a set address
within that region.
*************************************************************/
task TSK_MEM_TEST_DATA_BUS;
input [2:0] bar_index;
reg [31:0] pattern;
reg success;
begin
$display("[%t] : Performing Memory data test to address %x", $realtime, BAR_INIT_P_BAR[bar_index][31:0]);
success = 1; // assume success
// Perform a walking 1's test at the given address.
for (pattern = 1; pattern != 0; pattern = pattern << 1)
begin
// Write the test pattern. *address = pattern;pio_memTestAddrBus_test1
TSK_TX_BAR_WRITE(bar_index, 32'h0, DEFAULT_TAG, DEFAULT_TC, pattern);
TSK_TX_CLK_EAT(10);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_BAR_READ(bar_index, 32'h0, DEFAULT_TAG, DEFAULT_TC);
TSK_WAIT_FOR_READ_DATA;
if (P_READ_DATA != pattern)
begin
$display("[%t] : Data Error Mismatch, Address: %x Write Data %x != Read Data %x", $realtime,
BAR_INIT_P_BAR[bar_index][31:0], pattern, P_READ_DATA);
success = 0;
$finish;
end
else
begin
$display("[%t] : Address: %x Write Data: %x successfully received", $realtime,
BAR_INIT_P_BAR[bar_index][31:0], P_READ_DATA);
end
TSK_TX_CLK_EAT(10);
DEFAULT_TAG = DEFAULT_TAG + 1;
end // for loop
if (success == 1)
$display("[%t] : TSK_MEM_TEST_DATA_BUS successfully completed", $realtime);
else
$display("[%t] : TSK_MEM_TEST_DATA_BUS completed with errors", $realtime);
end
endtask // TSK_MEM_TEST_DATA_BUS
/************************************************************
Task : TSK_MEM_TEST_ADDR_BUS
Inputs : bar_index, nBytes
Outputs : None
Description : Test the address bus wiring in a specific memory by
performing a walking 1's test on the relevant bits
of the address and checking for multiple writes/aliasing.
This test will find single-bit address failures such as stuck
-high, stuck-low, and shorted pins.
*************************************************************/
task TSK_MEM_TEST_ADDR_BUS;
input [2:0] bar_index;
input [31:0] nBytes;
reg [31:0] pattern;
reg [31:0] antipattern;
reg [31:0] addressMask;
reg [31:0] offset;
reg [31:0] testOffset;
reg success;
reg stuckHi_success;
reg stuckLo_success;
begin
$display("[%t] : Performing Memory address test to address %x", $realtime, BAR_INIT_P_BAR[bar_index][31:0]);
success = 1; // assume success
stuckHi_success = 1;
stuckLo_success = 1;
pattern = 32'hAAAAAAAA;
antipattern = 32'h55555555;
// divide by 4 because the block RAMS we are testing are 32bit wide
// and therefore the low two bits are not meaningful for addressing purposes
// for this test.
addressMask = (nBytes/4 - 1);
$display("[%t] : Checking for address bits stuck high", $realtime);
// Write the default pattern at each of the power-of-two offsets.
for (offset = 1; (offset & addressMask) != 0; offset = offset << 1)
begin
verbose = 1;
// baseAddress[offset] = pattern
TSK_TX_BAR_WRITE(bar_index, 4*offset, DEFAULT_TAG, DEFAULT_TC, pattern);
TSK_TX_CLK_EAT(10);
DEFAULT_TAG = DEFAULT_TAG + 1;
end
// Check for address bits stuck high.
// It should be noted that since the write address and read address pins are different
// for the block RAMs used in the PIO design, the stuck high test will only catch an error if both
// read and write addresses are both stuck hi. Otherwise the remaining portion of the tests
// will catch if only one of the addresses are stuck hi.
testOffset = 0;
// baseAddress[testOffset] = antipattern;
TSK_TX_BAR_WRITE(bar_index, 4*testOffset, DEFAULT_TAG, DEFAULT_TC, antipattern);
TSK_TX_CLK_EAT(10);
DEFAULT_TAG = DEFAULT_TAG + 1;
for (offset = 1; (offset & addressMask) != 0; offset = offset << 1)
begin
TSK_TX_BAR_READ(bar_index, 4*offset, DEFAULT_TAG, DEFAULT_TC);
TSK_WAIT_FOR_READ_DATA;
if (P_READ_DATA != pattern)
begin
$display("[%t] : Error: Pattern Mismatch, Address = %x, Write Data %x != Read Data %x",
$realtime, BAR_INIT_P_BAR[bar_index][31:0]+(4*offset), pattern, P_READ_DATA);
stuckHi_success = 0;
success = 0;
$finish;
end
else
begin
$display("[%t] : Pattern Match: Address %x Data: %x successfully received",
$realtime, BAR_INIT_P_BAR[bar_index][31:0]+(4*offset), P_READ_DATA);
end
TSK_TX_CLK_EAT(10);
DEFAULT_TAG = DEFAULT_TAG + 1;
end
if (stuckHi_success == 1)
$display("[%t] : Stuck Hi Address Test successfully completed", $realtime);
else
$display("[%t] : Error: Stuck Hi Address Test failed", $realtime);
$display("[%t] : Checking for address bits stuck low or shorted", $realtime);
//baseAddress[testOffset] = pattern;
TSK_TX_BAR_WRITE(bar_index, 4*testOffset, DEFAULT_TAG, DEFAULT_TC, pattern);
TSK_TX_CLK_EAT(10);
DEFAULT_TAG = DEFAULT_TAG + 1;
// Check for address bits stuck low or shorted.
for (testOffset = 1; (testOffset & addressMask) != 0; testOffset = testOffset << 1)
begin
//baseAddress[testOffset] = antipattern;
TSK_TX_BAR_WRITE(bar_index, 4*testOffset, DEFAULT_TAG, DEFAULT_TC, antipattern);
TSK_TX_CLK_EAT(10);
DEFAULT_TAG = DEFAULT_TAG + 1;
TSK_TX_BAR_READ(bar_index, 32'h0, DEFAULT_TAG, DEFAULT_TC);
TSK_WAIT_FOR_READ_DATA;
if (P_READ_DATA != pattern) // if (baseAddress[0] != pattern)
begin
$display("[%t] : Error: Pattern Mismatch, Address = %x, Write Data %x != Read Data %x",
$realtime, BAR_INIT_P_BAR[bar_index][31:0]+(4*0), pattern, P_READ_DATA);
stuckLo_success = 0;
success = 0;
$finish;
end
else
begin
$display("[%t] : Pattern Match: Address %x Data: %x successfully received",
$realtime, BAR_INIT_P_BAR[bar_index][31:0]+(4*offset), P_READ_DATA);
end
TSK_TX_CLK_EAT(10);
DEFAULT_TAG = DEFAULT_TAG + 1;
for (offset = 1; (offset & addressMask) != 0; offset = offset << 1)
begin
TSK_TX_BAR_READ(bar_index, 4*offset, DEFAULT_TAG, DEFAULT_TC);
TSK_WAIT_FOR_READ_DATA;
// if ((baseAddress[offset] != pattern) && (offset != testOffset))
if ((P_READ_DATA != pattern) && (offset != testOffset))
begin
$display("[%t] : Error: Pattern Mismatch, Address = %x, Write Data %x != Read Data %x",
$realtime, BAR_INIT_P_BAR[bar_index][31:0]+(4*offset),
pattern, P_READ_DATA);
stuckLo_success = 0;
success = 0;
$finish;
end
else
begin
$display("[%t] : Pattern Match: Address %x Data: %x successfully received",
$realtime, BAR_INIT_P_BAR[bar_index][31:0]+(4*offset),
P_READ_DATA);
end
TSK_TX_CLK_EAT(10);
DEFAULT_TAG = DEFAULT_TAG + 1;
end
// baseAddress[testOffset] = pattern;
TSK_TX_BAR_WRITE(bar_index, 4*testOffset, DEFAULT_TAG, DEFAULT_TC, pattern);
TSK_TX_CLK_EAT(10);
DEFAULT_TAG = DEFAULT_TAG + 1;
end
if (stuckLo_success == 1)
$display("[%t] : Stuck Low Address Test successfully completed", $realtime);
else
$display("[%t] : Error: Stuck Low Address Test failed", $realtime);
if (success == 1)
$display("[%t] : TSK_MEM_TEST_ADDR_BUS successfully completed", $realtime);
else
$display("[%t] : TSK_MEM_TEST_ADDR_BUS completed with errors", $realtime);
end
endtask // TSK_MEM_TEST_ADDR_BUS
/************************************************************
Task : TSK_MEM_TEST_DEVICE
Inputs : bar_index, nBytes
Outputs : None
* Description: Test the integrity of a physical memory device by
* performing an increment/decrement test over the
* entire region. In the process every storage bit
* in the device is tested as a zero and a one. The
* bar_index and the size of the region are
* selected by the caller.
*************************************************************/
task TSK_MEM_TEST_DEVICE;
input [2:0] bar_index;
input [31:0] nBytes;
reg [31:0] pattern;
reg [31:0] antipattern;
reg [31:0] offset;
reg [31:0] nWords;
reg success;
begin
$display("[%t] : Performing Memory device test to address %x", $realtime, BAR_INIT_P_BAR[bar_index][31:0]);
success = 1; // assume success
nWords = nBytes / 4;
pattern = 1;
// Fill memory with a known pattern.
for (offset = 0; offset < nWords; offset = offset + 1)
begin
verbose = 1;
//baseAddress[offset] = pattern;
TSK_TX_BAR_WRITE(bar_index, 4*offset, DEFAULT_TAG, DEFAULT_TC, pattern);
TSK_TX_CLK_EAT(10);
DEFAULT_TAG = DEFAULT_TAG + 1;
pattern = pattern + 1;
end
pattern = 1;
// Check each location and invert it for the second pass.
for (offset = 0; offset < nWords; offset = offset + 1)
begin
TSK_TX_BAR_READ(bar_index, 4*offset, DEFAULT_TAG, DEFAULT_TC);
TSK_WAIT_FOR_READ_DATA;
DEFAULT_TAG = DEFAULT_TAG + 1;
//if (baseAddress[offset] != pattern)
if (P_READ_DATA != pattern)
begin
$display("[%t] : Error: Pattern Mismatch, Address = %x, Write Data %x != Read Data %x", $realtime,
BAR_INIT_P_BAR[bar_index][31:0]+(4*offset), pattern, P_READ_DATA);
success = 0;
$finish;
end
antipattern = ~pattern;
//baseAddress[offset] = antipattern;
TSK_TX_BAR_WRITE(bar_index, 4*offset, DEFAULT_TAG, DEFAULT_TC, antipattern);
TSK_TX_CLK_EAT(10);
DEFAULT_TAG = DEFAULT_TAG + 1;
pattern = pattern + 1;
end
pattern = 1;
// Check each location for the inverted pattern
for (offset = 0; offset < nWords; offset = offset + 1)
begin
antipattern = ~pattern;
TSK_TX_BAR_READ(bar_index, 4*offset, DEFAULT_TAG, DEFAULT_TC);
TSK_WAIT_FOR_READ_DATA;
DEFAULT_TAG = DEFAULT_TAG + 1;
//if (baseAddress[offset] != pattern)
if (P_READ_DATA != antipattern)
begin
$display("[%t] : Error: Pattern Mismatch, Address = %x, Write Data %x != Read Data %x", $realtime,
BAR_INIT_P_BAR[bar_index][31:0]+(4*offset), pattern, P_READ_DATA);
success = 0;
$finish;
end
pattern = pattern + 1;
end
if (success == 1)
$display("[%t] : TSK_MEM_TEST_DEVICE successfully completed", $realtime);
else
$display("[%t] : TSK_MEM_TEST_DEVICE completed with errors", $realtime);
end
endtask // TSK_MEM_TEST_DEVICE
/************************************************************
Function : FNC_CONVERT_RANGE_TO_SIZE_32
Inputs : BAR index for 32 bit BAR
Outputs : 32 bit BAR size
Description : Called from tx app. Note that the smallest range
supported by this function is 16 bytes.
*************************************************************/
function [31:0] FNC_CONVERT_RANGE_TO_SIZE_32;
input [31:0] bar_index;
reg [32:0] return_value;
begin
case (BAR_INIT_P_BAR_RANGE[bar_index] & 32'hFFFF_FFF0) // AND off control bits
32'hFFFF_FFF0 : return_value = 33'h0000_0010;
32'hFFFF_FFE0 : return_value = 33'h0000_0020;
32'hFFFF_FFC0 : return_value = 33'h0000_0040;
32'hFFFF_FF80 : return_value = 33'h0000_0080;
32'hFFFF_FF00 : return_value = 33'h0000_0100;
32'hFFFF_FE00 : return_value = 33'h0000_0200;
32'hFFFF_FC00 : return_value = 33'h0000_0400;
32'hFFFF_F800 : return_value = 33'h0000_0800;
32'hFFFF_F000 : return_value = 33'h0000_1000;
32'hFFFF_E000 : return_value = 33'h0000_2000;
32'hFFFF_C000 : return_value = 33'h0000_4000;
32'hFFFF_8000 : return_value = 33'h0000_8000;
32'hFFFF_0000 : return_value = 33'h0001_0000;
32'hFFFE_0000 : return_value = 33'h0002_0000;
32'hFFFC_0000 : return_value = 33'h0004_0000;
32'hFFF8_0000 : return_value = 33'h0008_0000;
32'hFFF0_0000 : return_value = 33'h0010_0000;
32'hFFE0_0000 : return_value = 33'h0020_0000;
32'hFFC0_0000 : return_value = 33'h0040_0000;
32'hFF80_0000 : return_value = 33'h0080_0000;
32'hFF00_0000 : return_value = 33'h0100_0000;
32'hFE00_0000 : return_value = 33'h0200_0000;
32'hFC00_0000 : return_value = 33'h0400_0000;
32'hF800_0000 : return_value = 33'h0800_0000;
32'hF000_0000 : return_value = 33'h1000_0000;
32'hE000_0000 : return_value = 33'h2000_0000;
32'hC000_0000 : return_value = 33'h4000_0000;
32'h8000_0000 : return_value = 33'h8000_0000;
default : return_value = 33'h0000_0000;
endcase
FNC_CONVERT_RANGE_TO_SIZE_32 = return_value;
end
endfunction // FNC_CONVERT_RANGE_TO_SIZE_32
/************************************************************
Function : FNC_CONVERT_RANGE_TO_SIZE_HI32
Inputs : BAR index for upper 32 bit BAR of 64 bit address
Outputs : upper 32 bit BAR size
Description : Called from tx app.
*************************************************************/
function [31:0] FNC_CONVERT_RANGE_TO_SIZE_HI32;
input [31:0] bar_index;
reg [32:0] return_value;
begin
case (BAR_INIT_P_BAR_RANGE[bar_index])
32'hFFFF_FFFF : return_value = 33'h00000_0001;
32'hFFFF_FFFE : return_value = 33'h00000_0002;
32'hFFFF_FFFC : return_value = 33'h00000_0004;
32'hFFFF_FFF8 : return_value = 33'h00000_0008;
32'hFFFF_FFF0 : return_value = 33'h00000_0010;
32'hFFFF_FFE0 : return_value = 33'h00000_0020;
32'hFFFF_FFC0 : return_value = 33'h00000_0040;
32'hFFFF_FF80 : return_value = 33'h00000_0080;
32'hFFFF_FF00 : return_value = 33'h00000_0100;
32'hFFFF_FE00 : return_value = 33'h00000_0200;
32'hFFFF_FC00 : return_value = 33'h00000_0400;
32'hFFFF_F800 : return_value = 33'h00000_0800;
32'hFFFF_F000 : return_value = 33'h00000_1000;
32'hFFFF_E000 : return_value = 33'h00000_2000;
32'hFFFF_C000 : return_value = 33'h00000_4000;
32'hFFFF_8000 : return_value = 33'h00000_8000;
32'hFFFF_0000 : return_value = 33'h00001_0000;
32'hFFFE_0000 : return_value = 33'h00002_0000;
32'hFFFC_0000 : return_value = 33'h00004_0000;
32'hFFF8_0000 : return_value = 33'h00008_0000;
32'hFFF0_0000 : return_value = 33'h00010_0000;
32'hFFE0_0000 : return_value = 33'h00020_0000;
32'hFFC0_0000 : return_value = 33'h00040_0000;
32'hFF80_0000 : return_value = 33'h00080_0000;
32'hFF00_0000 : return_value = 33'h00100_0000;
32'hFE00_0000 : return_value = 33'h00200_0000;
32'hFC00_0000 : return_value = 33'h00400_0000;
32'hF800_0000 : return_value = 33'h00800_0000;
32'hF000_0000 : return_value = 33'h01000_0000;
32'hE000_0000 : return_value = 33'h02000_0000;
32'hC000_0000 : return_value = 33'h04000_0000;
32'h8000_0000 : return_value = 33'h08000_0000;
default : return_value = 33'h00000_0000;
endcase
FNC_CONVERT_RANGE_TO_SIZE_HI32 = return_value;
end
endfunction // FNC_CONVERT_RANGE_TO_SIZE_HI32
endmodule // pci_exp_usrapp_tx
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O311AI_2_V
`define SKY130_FD_SC_HS__O311AI_2_V
/**
* o311ai: 3-input OR into 3-input NAND.
*
* Y = !((A1 | A2 | A3) & B1 & C1)
*
* Verilog wrapper for o311ai with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__o311ai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o311ai_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__o311ai_2 (
Y ,
A1,
A2,
A3,
B1,
C1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__o311ai base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__O311AI_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD2_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD2_PP_BLACKBOX_V
/**
* clkdlyinv3sd2: Clock Delay Inverter 3-stage 0.25um length inner
* stage gate.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__clkdlyinv3sd2 (
Y ,
A ,
VPWR,
VGND
);
output Y ;
input A ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD2_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLXTN_2_V
`define SKY130_FD_SC_LP__DLXTN_2_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog wrapper for dlxtn with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlxtn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlxtn_2 (
Q ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlxtn_2 (
Q ,
D ,
GATE_N
);
output Q ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlxtn base (
.Q(Q),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLXTN_2_V
|
/*
Copyright (c) 2020 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA core logic
*/
module fpga_core
(
/*
* Clock: 156.25MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* UART: 115200 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd,
input wire uart_rts,
output wire uart_cts,
/*
* Ethernet: SFP+
*/
input wire sfp0_tx_clk,
input wire sfp0_tx_rst,
output wire [63:0] sfp0_txd,
output wire [7:0] sfp0_txc,
input wire sfp0_rx_clk,
input wire sfp0_rx_rst,
input wire [63:0] sfp0_rxd,
input wire [7:0] sfp0_rxc,
input wire sfp1_tx_clk,
input wire sfp1_tx_rst,
output wire [63:0] sfp1_txd,
output wire [7:0] sfp1_txc,
input wire sfp1_rx_clk,
input wire sfp1_rx_rst,
input wire [63:0] sfp1_rxd,
input wire [7:0] sfp1_rxc,
input wire sfp2_tx_clk,
input wire sfp2_tx_rst,
output wire [63:0] sfp2_txd,
output wire [7:0] sfp2_txc,
input wire sfp2_rx_clk,
input wire sfp2_rx_rst,
input wire [63:0] sfp2_rxd,
input wire [7:0] sfp2_rxc,
input wire sfp3_tx_clk,
input wire sfp3_tx_rst,
output wire [63:0] sfp3_txd,
output wire [7:0] sfp3_txc,
input wire sfp3_rx_clk,
input wire sfp3_rx_rst,
input wire [63:0] sfp3_rxd,
input wire [7:0] sfp3_rxc
);
// AXI between MAC and Ethernet modules
wire [63:0] rx_axis_tdata;
wire [7:0] rx_axis_tkeep;
wire rx_axis_tvalid;
wire rx_axis_tready;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [63:0] tx_axis_tdata;
wire [7:0] tx_axis_tkeep;
wire tx_axis_tvalid;
wire tx_axis_tready;
wire tx_axis_tlast;
wire tx_axis_tuser;
// Ethernet frame between Ethernet modules and UDP stack
wire rx_eth_hdr_ready;
wire rx_eth_hdr_valid;
wire [47:0] rx_eth_dest_mac;
wire [47:0] rx_eth_src_mac;
wire [15:0] rx_eth_type;
wire [63:0] rx_eth_payload_axis_tdata;
wire [7:0] rx_eth_payload_axis_tkeep;
wire rx_eth_payload_axis_tvalid;
wire rx_eth_payload_axis_tready;
wire rx_eth_payload_axis_tlast;
wire rx_eth_payload_axis_tuser;
wire tx_eth_hdr_ready;
wire tx_eth_hdr_valid;
wire [47:0] tx_eth_dest_mac;
wire [47:0] tx_eth_src_mac;
wire [15:0] tx_eth_type;
wire [63:0] tx_eth_payload_axis_tdata;
wire [7:0] tx_eth_payload_axis_tkeep;
wire tx_eth_payload_axis_tvalid;
wire tx_eth_payload_axis_tready;
wire tx_eth_payload_axis_tlast;
wire tx_eth_payload_axis_tuser;
// IP frame connections
wire rx_ip_hdr_valid;
wire rx_ip_hdr_ready;
wire [47:0] rx_ip_eth_dest_mac;
wire [47:0] rx_ip_eth_src_mac;
wire [15:0] rx_ip_eth_type;
wire [3:0] rx_ip_version;
wire [3:0] rx_ip_ihl;
wire [5:0] rx_ip_dscp;
wire [1:0] rx_ip_ecn;
wire [15:0] rx_ip_length;
wire [15:0] rx_ip_identification;
wire [2:0] rx_ip_flags;
wire [12:0] rx_ip_fragment_offset;
wire [7:0] rx_ip_ttl;
wire [7:0] rx_ip_protocol;
wire [15:0] rx_ip_header_checksum;
wire [31:0] rx_ip_source_ip;
wire [31:0] rx_ip_dest_ip;
wire [63:0] rx_ip_payload_axis_tdata;
wire [7:0] rx_ip_payload_axis_tkeep;
wire rx_ip_payload_axis_tvalid;
wire rx_ip_payload_axis_tready;
wire rx_ip_payload_axis_tlast;
wire rx_ip_payload_axis_tuser;
wire tx_ip_hdr_valid;
wire tx_ip_hdr_ready;
wire [5:0] tx_ip_dscp;
wire [1:0] tx_ip_ecn;
wire [15:0] tx_ip_length;
wire [7:0] tx_ip_ttl;
wire [7:0] tx_ip_protocol;
wire [31:0] tx_ip_source_ip;
wire [31:0] tx_ip_dest_ip;
wire [63:0] tx_ip_payload_axis_tdata;
wire [7:0] tx_ip_payload_axis_tkeep;
wire tx_ip_payload_axis_tvalid;
wire tx_ip_payload_axis_tready;
wire tx_ip_payload_axis_tlast;
wire tx_ip_payload_axis_tuser;
// UDP frame connections
wire rx_udp_hdr_valid;
wire rx_udp_hdr_ready;
wire [47:0] rx_udp_eth_dest_mac;
wire [47:0] rx_udp_eth_src_mac;
wire [15:0] rx_udp_eth_type;
wire [3:0] rx_udp_ip_version;
wire [3:0] rx_udp_ip_ihl;
wire [5:0] rx_udp_ip_dscp;
wire [1:0] rx_udp_ip_ecn;
wire [15:0] rx_udp_ip_length;
wire [15:0] rx_udp_ip_identification;
wire [2:0] rx_udp_ip_flags;
wire [12:0] rx_udp_ip_fragment_offset;
wire [7:0] rx_udp_ip_ttl;
wire [7:0] rx_udp_ip_protocol;
wire [15:0] rx_udp_ip_header_checksum;
wire [31:0] rx_udp_ip_source_ip;
wire [31:0] rx_udp_ip_dest_ip;
wire [15:0] rx_udp_source_port;
wire [15:0] rx_udp_dest_port;
wire [15:0] rx_udp_length;
wire [15:0] rx_udp_checksum;
wire [63:0] rx_udp_payload_axis_tdata;
wire [7:0] rx_udp_payload_axis_tkeep;
wire rx_udp_payload_axis_tvalid;
wire rx_udp_payload_axis_tready;
wire rx_udp_payload_axis_tlast;
wire rx_udp_payload_axis_tuser;
wire tx_udp_hdr_valid;
wire tx_udp_hdr_ready;
wire [5:0] tx_udp_ip_dscp;
wire [1:0] tx_udp_ip_ecn;
wire [7:0] tx_udp_ip_ttl;
wire [31:0] tx_udp_ip_source_ip;
wire [31:0] tx_udp_ip_dest_ip;
wire [15:0] tx_udp_source_port;
wire [15:0] tx_udp_dest_port;
wire [15:0] tx_udp_length;
wire [15:0] tx_udp_checksum;
wire [63:0] tx_udp_payload_axis_tdata;
wire [7:0] tx_udp_payload_axis_tkeep;
wire tx_udp_payload_axis_tvalid;
wire tx_udp_payload_axis_tready;
wire tx_udp_payload_axis_tlast;
wire tx_udp_payload_axis_tuser;
wire [63:0] rx_fifo_udp_payload_axis_tdata;
wire [7:0] rx_fifo_udp_payload_axis_tkeep;
wire rx_fifo_udp_payload_axis_tvalid;
wire rx_fifo_udp_payload_axis_tready;
wire rx_fifo_udp_payload_axis_tlast;
wire rx_fifo_udp_payload_axis_tuser;
wire [63:0] tx_fifo_udp_payload_axis_tdata;
wire [7:0] tx_fifo_udp_payload_axis_tkeep;
wire tx_fifo_udp_payload_axis_tvalid;
wire tx_fifo_udp_payload_axis_tready;
wire tx_fifo_udp_payload_axis_tlast;
wire tx_fifo_udp_payload_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
// IP ports not used
assign rx_ip_hdr_ready = 1;
assign rx_ip_payload_axis_tready = 1;
assign tx_ip_hdr_valid = 0;
assign tx_ip_dscp = 0;
assign tx_ip_ecn = 0;
assign tx_ip_length = 0;
assign tx_ip_ttl = 0;
assign tx_ip_protocol = 0;
assign tx_ip_source_ip = 0;
assign tx_ip_dest_ip = 0;
assign tx_ip_payload_axis_tdata = 0;
assign tx_ip_payload_axis_tkeep = 0;
assign tx_ip_payload_axis_tvalid = 0;
assign tx_ip_payload_axis_tlast = 0;
assign tx_ip_payload_axis_tuser = 0;
// Loop back UDP
wire match_cond = rx_udp_dest_port == 1234;
wire no_match = ~match_cond;
reg match_cond_reg = 0;
reg no_match_reg = 0;
always @(posedge clk) begin
if (rst) begin
match_cond_reg <= 0;
no_match_reg <= 0;
end else begin
if (rx_udp_payload_axis_tvalid) begin
if ((~match_cond_reg & ~no_match_reg) |
(rx_udp_payload_axis_tvalid & rx_udp_payload_axis_tready & rx_udp_payload_axis_tlast)) begin
match_cond_reg <= match_cond;
no_match_reg <= no_match;
end
end else begin
match_cond_reg <= 0;
no_match_reg <= 0;
end
end
end
assign tx_udp_hdr_valid = rx_udp_hdr_valid & match_cond;
assign rx_udp_hdr_ready = (tx_eth_hdr_ready & match_cond) | no_match;
assign tx_udp_ip_dscp = 0;
assign tx_udp_ip_ecn = 0;
assign tx_udp_ip_ttl = 64;
assign tx_udp_ip_source_ip = local_ip;
assign tx_udp_ip_dest_ip = rx_udp_ip_source_ip;
assign tx_udp_source_port = rx_udp_dest_port;
assign tx_udp_dest_port = rx_udp_source_port;
assign tx_udp_length = rx_udp_length;
assign tx_udp_checksum = 0;
assign tx_udp_payload_axis_tdata = tx_fifo_udp_payload_axis_tdata;
assign tx_udp_payload_axis_tkeep = tx_fifo_udp_payload_axis_tkeep;
assign tx_udp_payload_axis_tvalid = tx_fifo_udp_payload_axis_tvalid;
assign tx_fifo_udp_payload_axis_tready = tx_udp_payload_axis_tready;
assign tx_udp_payload_axis_tlast = tx_fifo_udp_payload_axis_tlast;
assign tx_udp_payload_axis_tuser = tx_fifo_udp_payload_axis_tuser;
assign rx_fifo_udp_payload_axis_tdata = rx_udp_payload_axis_tdata;
assign rx_fifo_udp_payload_axis_tkeep = rx_udp_payload_axis_tkeep;
assign rx_fifo_udp_payload_axis_tvalid = rx_udp_payload_axis_tvalid & match_cond_reg;
assign rx_udp_payload_axis_tready = (rx_fifo_udp_payload_axis_tready & match_cond_reg) | no_match_reg;
assign rx_fifo_udp_payload_axis_tlast = rx_udp_payload_axis_tlast;
assign rx_fifo_udp_payload_axis_tuser = rx_udp_payload_axis_tuser;
// Place first payload byte onto LEDs
reg valid_last = 0;
reg [7:0] led_reg = 0;
always @(posedge clk) begin
if (rst) begin
led_reg <= 0;
end else begin
valid_last <= tx_udp_payload_axis_tvalid;
if (tx_udp_payload_axis_tvalid & ~valid_last) begin
led_reg <= tx_udp_payload_axis_tdata;
end
end
end
assign led = led_reg;
assign sfp1_txd = 64'h0707070707070707;
assign sfp1_txc = 8'hff;
assign sfp2_txd = 64'h0707070707070707;
assign sfp2_txc = 8'hff;
assign sfp3_txd = 64'h0707070707070707;
assign sfp3_txc = 8'hff;
eth_mac_10g_fifo #(
.ENABLE_PADDING(1),
.ENABLE_DIC(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_10g_fifo_inst (
.rx_clk(sfp0_rx_clk),
.rx_rst(sfp0_rx_rst),
.tx_clk(sfp0_tx_clk),
.tx_rst(sfp0_tx_rst),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tkeep(tx_axis_tkeep),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tkeep(rx_axis_tkeep),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.xgmii_rxd(sfp0_rxd),
.xgmii_rxc(sfp0_rxc),
.xgmii_txd(sfp0_txd),
.xgmii_txc(sfp0_txc),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.ifg_delay(8'd12)
);
eth_axis_rx #(
.DATA_WIDTH(64)
)
eth_axis_rx_inst (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_axis_tdata),
.s_axis_tkeep(rx_axis_tkeep),
.s_axis_tvalid(rx_axis_tvalid),
.s_axis_tready(rx_axis_tready),
.s_axis_tlast(rx_axis_tlast),
.s_axis_tuser(rx_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(rx_eth_hdr_valid),
.m_eth_hdr_ready(rx_eth_hdr_ready),
.m_eth_dest_mac(rx_eth_dest_mac),
.m_eth_src_mac(rx_eth_src_mac),
.m_eth_type(rx_eth_type),
.m_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Status signals
.busy(),
.error_header_early_termination()
);
eth_axis_tx #(
.DATA_WIDTH(64)
)
eth_axis_tx_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(tx_eth_hdr_valid),
.s_eth_hdr_ready(tx_eth_hdr_ready),
.s_eth_dest_mac(tx_eth_dest_mac),
.s_eth_src_mac(tx_eth_src_mac),
.s_eth_type(tx_eth_type),
.s_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_axis_tdata),
.m_axis_tkeep(tx_axis_tkeep),
.m_axis_tvalid(tx_axis_tvalid),
.m_axis_tready(tx_axis_tready),
.m_axis_tlast(tx_axis_tlast),
.m_axis_tuser(tx_axis_tuser),
// Status signals
.busy()
);
udp_complete_64
udp_complete_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(rx_eth_hdr_valid),
.s_eth_hdr_ready(rx_eth_hdr_ready),
.s_eth_dest_mac(rx_eth_dest_mac),
.s_eth_src_mac(rx_eth_src_mac),
.s_eth_type(rx_eth_type),
.s_eth_payload_axis_tdata(rx_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(rx_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(rx_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(rx_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(rx_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(rx_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(tx_eth_hdr_valid),
.m_eth_hdr_ready(tx_eth_hdr_ready),
.m_eth_dest_mac(tx_eth_dest_mac),
.m_eth_src_mac(tx_eth_src_mac),
.m_eth_type(tx_eth_type),
.m_eth_payload_axis_tdata(tx_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(tx_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(tx_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(tx_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(tx_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(tx_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(tx_ip_hdr_valid),
.s_ip_hdr_ready(tx_ip_hdr_ready),
.s_ip_dscp(tx_ip_dscp),
.s_ip_ecn(tx_ip_ecn),
.s_ip_length(tx_ip_length),
.s_ip_ttl(tx_ip_ttl),
.s_ip_protocol(tx_ip_protocol),
.s_ip_source_ip(tx_ip_source_ip),
.s_ip_dest_ip(tx_ip_dest_ip),
.s_ip_payload_axis_tdata(tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep(tx_ip_payload_axis_tkeep),
.s_ip_payload_axis_tvalid(tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(rx_ip_hdr_valid),
.m_ip_hdr_ready(rx_ip_hdr_ready),
.m_ip_eth_dest_mac(rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(rx_ip_eth_src_mac),
.m_ip_eth_type(rx_ip_eth_type),
.m_ip_version(rx_ip_version),
.m_ip_ihl(rx_ip_ihl),
.m_ip_dscp(rx_ip_dscp),
.m_ip_ecn(rx_ip_ecn),
.m_ip_length(rx_ip_length),
.m_ip_identification(rx_ip_identification),
.m_ip_flags(rx_ip_flags),
.m_ip_fragment_offset(rx_ip_fragment_offset),
.m_ip_ttl(rx_ip_ttl),
.m_ip_protocol(rx_ip_protocol),
.m_ip_header_checksum(rx_ip_header_checksum),
.m_ip_source_ip(rx_ip_source_ip),
.m_ip_dest_ip(rx_ip_dest_ip),
.m_ip_payload_axis_tdata(rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep(rx_ip_payload_axis_tkeep),
.m_ip_payload_axis_tvalid(rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(rx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(tx_udp_hdr_valid),
.s_udp_hdr_ready(tx_udp_hdr_ready),
.s_udp_ip_dscp(tx_udp_ip_dscp),
.s_udp_ip_ecn(tx_udp_ip_ecn),
.s_udp_ip_ttl(tx_udp_ip_ttl),
.s_udp_ip_source_ip(tx_udp_ip_source_ip),
.s_udp_ip_dest_ip(tx_udp_ip_dest_ip),
.s_udp_source_port(tx_udp_source_port),
.s_udp_dest_port(tx_udp_dest_port),
.s_udp_length(tx_udp_length),
.s_udp_checksum(tx_udp_checksum),
.s_udp_payload_axis_tdata(tx_udp_payload_axis_tdata),
.s_udp_payload_axis_tkeep(tx_udp_payload_axis_tkeep),
.s_udp_payload_axis_tvalid(tx_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(tx_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(tx_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(tx_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(rx_udp_hdr_valid),
.m_udp_hdr_ready(rx_udp_hdr_ready),
.m_udp_eth_dest_mac(rx_udp_eth_dest_mac),
.m_udp_eth_src_mac(rx_udp_eth_src_mac),
.m_udp_eth_type(rx_udp_eth_type),
.m_udp_ip_version(rx_udp_ip_version),
.m_udp_ip_ihl(rx_udp_ip_ihl),
.m_udp_ip_dscp(rx_udp_ip_dscp),
.m_udp_ip_ecn(rx_udp_ip_ecn),
.m_udp_ip_length(rx_udp_ip_length),
.m_udp_ip_identification(rx_udp_ip_identification),
.m_udp_ip_flags(rx_udp_ip_flags),
.m_udp_ip_fragment_offset(rx_udp_ip_fragment_offset),
.m_udp_ip_ttl(rx_udp_ip_ttl),
.m_udp_ip_protocol(rx_udp_ip_protocol),
.m_udp_ip_header_checksum(rx_udp_ip_header_checksum),
.m_udp_ip_source_ip(rx_udp_ip_source_ip),
.m_udp_ip_dest_ip(rx_udp_ip_dest_ip),
.m_udp_source_port(rx_udp_source_port),
.m_udp_dest_port(rx_udp_dest_port),
.m_udp_length(rx_udp_length),
.m_udp_checksum(rx_udp_checksum),
.m_udp_payload_axis_tdata(rx_udp_payload_axis_tdata),
.m_udp_payload_axis_tkeep(rx_udp_payload_axis_tkeep),
.m_udp_payload_axis_tvalid(rx_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(rx_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(rx_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(rx_udp_payload_axis_tuser),
// Status signals
.ip_rx_busy(),
.ip_tx_busy(),
.udp_rx_busy(),
.udp_tx_busy(),
.ip_rx_error_header_early_termination(),
.ip_rx_error_payload_early_termination(),
.ip_rx_error_invalid_header(),
.ip_rx_error_invalid_checksum(),
.ip_tx_error_payload_early_termination(),
.ip_tx_error_arp_failed(),
.udp_rx_error_header_early_termination(),
.udp_rx_error_payload_early_termination(),
.udp_tx_error_payload_early_termination(),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(1'b0)
);
axis_fifo #(
.DEPTH(8192),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.KEEP_WIDTH(8),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.FRAME_FIFO(0)
)
udp_payload_fifo (
.clk(clk),
.rst(rst),
// AXI input
.s_axis_tdata(rx_fifo_udp_payload_axis_tdata),
.s_axis_tkeep(rx_fifo_udp_payload_axis_tkeep),
.s_axis_tvalid(rx_fifo_udp_payload_axis_tvalid),
.s_axis_tready(rx_fifo_udp_payload_axis_tready),
.s_axis_tlast(rx_fifo_udp_payload_axis_tlast),
.s_axis_tid(0),
.s_axis_tdest(0),
.s_axis_tuser(rx_fifo_udp_payload_axis_tuser),
// AXI output
.m_axis_tdata(tx_fifo_udp_payload_axis_tdata),
.m_axis_tkeep(tx_fifo_udp_payload_axis_tkeep),
.m_axis_tvalid(tx_fifo_udp_payload_axis_tvalid),
.m_axis_tready(tx_fifo_udp_payload_axis_tready),
.m_axis_tlast(tx_fifo_udp_payload_axis_tlast),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(tx_fifo_udp_payload_axis_tuser),
// Status
.status_overflow(),
.status_bad_frame(),
.status_good_frame()
);
endmodule
|
`timescale 1ns / 1ps
/********************************************************************
* TEST BENCH FOR PROTECTION CELLS *
********************************************************************
* Laboratory : Robotics and Embedded System Technology
* Engineer : Hanjara Cahya Adhyatma
* Create Date : 19/04/2017
* Project Name : FINAL PROJECT
* Target Devices: TEST BENCH SIM PROTECTION AND FPGA
* Tool versions : VERILOG 2001 RUN ON ICARUS 10
* Description : ??????????????
* Dependencies : ???
* Revision : ???
* Additional Comments: ???
********************************************************************
* INCLUDE MODULES *
*******************************************************************/
//`include "../module/protection.v"
/********************************************************************
* IO DEFINITIONS *
*******************************************************************/
module protection_sim;
reg RST, CLK, ENA;
reg [7:0]RGA;
reg [7:0]RGB;
wire [7:0]RGZ;
reg [1:0]KEY;
/********************************************************************
* DUMPER MONITOR *
*******************************************************************/
initial
begin
$dumpfile("vcd");
$dumpvars(0, prot);
$monitor($time, " REG A = %b REG Z = %b", RGA, RGZ);
end
/********************************************************************
* CLOCKING *
*******************************************************************/
initial
begin
CLK = 1'b1;
forever #5 CLK = ~CLK;
end
/********************************************************************
* RESET *
*******************************************************************/
initial
begin
RST = 1'b1;
#5 RST = 1'b0;
end
/********************************************************************
* DATAS INJECTION *
*******************************************************************/
initial
begin
RGA = 3'b000;
#10 RGA = 3'b111;
#10 RGA = 3'b101;
#10 RGA = 3'b110;
#10 RGA = 3'b010;
#10 RGA = 3'b011;
#10 RGA = 3'b100;
#10 RGA = 3'b010;
#10 RGA = 3'b000;
#10 RGA = 3'b111;
#10 RGA = 3'b100;
#10 RGA = 3'b010;
#10 RGA = 3'b001;
#10 RGA = 3'b010;
#10 RGA = 3'b101;
#10 RGA = 3'b011;
#10 RGA = 3'b100;
#10 RGA = 3'b010;
#10 RGA = 3'b111;
#10 RGA = 3'b011;
#10 RGA = 3'b000;
$finish;
end
/********************************************************************
* MODULE IN TEST *
*******************************************************************/
protection prot( RST, CLK, ENA, RGA, RGB, RGZ, KEY);
endmodule
|
//////////////////////////////////////////////////////////////////////
/// ////
/// ORPSoC top for Altera de1 board ////
/// ////
/// Franck Jullien, [email protected] ////
/// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
`include "orpsoc-defines.v"
module orpsoc_top #(
parameter rom0_aw = 6,
parameter uart0_aw = 3
)
(
input sys_clk_pad_i,
input rst_n_pad_i,
output [17:0] led_r_pad_o,
output [8:0] led_g_pad_o,
input [17:0] switch_pad_i,
input [3:0] key_pad_i,
inout [7:0] gpio0_io,
`ifdef SIM
output tdo_pad_o,
input tms_pad_i,
input tck_pad_i,
input tdi_pad_i,
`endif
output [1:0] sdram_ba_pad_o,
output [11:0] sdram_a_pad_o,
output sdram_cs_n_pad_o,
output sdram_ras_pad_o,
output sdram_cas_pad_o,
output sdram_we_pad_o,
inout [15:0] sdram_dq_pad_io,
output [1:0] sdram_dqm_pad_o,
output sdram_cke_pad_o,
output sdram_clk_pad_o,
input uart0_srx_pad_i,
output uart0_stx_pad_o
);
parameter IDCODE_VALUE = 32'h14951185;
////////////////////////////////////////////////////////////////////////
//
// Clock and reset generation module
//
////////////////////////////////////////////////////////////////////////
wire async_rst;
wire wb_clk, wb_rst;
wire dbg_tck;
wire sdram_clk;
wire sdram_rst;
assign sdram_clk_pad_o = sdram_clk;
clkgen clkgen0 (
.sys_clk_pad_i (sys_clk_pad_i),
.rst_n_pad_i (rst_n_pad_i),
.async_rst_o (async_rst),
.wb_clk_o (wb_clk),
.wb_rst_o (wb_rst),
`ifdef SIM
.tck_pad_i (tck_pad_i),
.dbg_tck_o (dbg_tck),
`endif
.sdram_clk_o (sdram_clk),
.sdram_rst_o (sdram_rst)
);
////////////////////////////////////////////////////////////////////////
//
// Modules interconnections
//
////////////////////////////////////////////////////////////////////////
`include "wb_intercon.vh"
`ifdef SIM
////////////////////////////////////////////////////////////////////////
//
// GENERIC JTAG TAP
//
////////////////////////////////////////////////////////////////////////
wire dbg_if_select;
wire dbg_if_tdo;
wire jtag_tap_tdo;
wire jtag_tap_shift_dr;
wire jtag_tap_pause_dr;
wire jtag_tap_update_dr;
wire jtag_tap_capture_dr;
tap_top #(.IDCODE_VALUE(IDCODE_VALUE))
jtag_tap0 (
.tdo_pad_o (tdo_pad_o),
.tms_pad_i (tms_pad_i),
.tck_pad_i (dbg_tck),
.trst_pad_i (async_rst),
.tdi_pad_i (tdi_pad_i),
.tdo_padoe_o (tdo_padoe_o),
.tdo_o (jtag_tap_tdo),
.shift_dr_o (jtag_tap_shift_dr),
.pause_dr_o (jtag_tap_pause_dr),
.update_dr_o (jtag_tap_update_dr),
.capture_dr_o (jtag_tap_capture_dr),
.extest_select_o (),
.sample_preload_select_o (),
.mbist_select_o (),
.debug_select_o (dbg_if_select),
.bs_chain_tdi_i (1'b0),
.mbist_tdi_i (1'b0),
.debug_tdi_i (dbg_if_tdo)
);
`else
////////////////////////////////////////////////////////////////////////
//
// ALTERA Virtual JTAG TAP
//
////////////////////////////////////////////////////////////////////////
wire dbg_if_select;
wire dbg_if_tdo;
wire jtag_tap_tdo;
wire jtag_tap_shift_dr;
wire jtag_tap_pause_dr;
wire jtag_tap_update_dr;
wire jtag_tap_capture_dr;
altera_virtual_jtag jtag_tap0 (
.tck_o (dbg_tck),
.debug_tdo_i (dbg_if_tdo),
.tdi_o (jtag_tap_tdo),
.test_logic_reset_o (),
.run_test_idle_o (),
.shift_dr_o (jtag_tap_shift_dr),
.capture_dr_o (jtag_tap_capture_dr),
.pause_dr_o (jtag_tap_pause_dr),
.update_dr_o (jtag_tap_update_dr),
.debug_select_o (dbg_if_select)
);
`endif
////////////////////////////////////////////////////////////////////////
//
// OR1K CPU
//
////////////////////////////////////////////////////////////////////////
wire [31:0] or1k_irq;
wire [31:0] or1k_dbg_dat_i;
wire [31:0] or1k_dbg_adr_i;
wire or1k_dbg_we_i;
wire or1k_dbg_stb_i;
wire or1k_dbg_ack_o;
wire [31:0] or1k_dbg_dat_o;
wire or1k_dbg_stall_i;
wire or1k_dbg_ewt_i;
wire [3:0] or1k_dbg_lss_o;
wire [1:0] or1k_dbg_is_o;
wire [10:0] or1k_dbg_wp_o;
wire or1k_dbg_bp_o;
wire or1k_dbg_rst;
wire sig_tick;
wire or1k_rst;
assign or1k_rst = wb_rst | or1k_dbg_rst;
`ifdef OR1200_CPU
or1200_top #(.boot_adr(32'hf0000100))
or1200_top0 (
// Instruction bus, clocks, reset
.iwb_clk_i (wb_clk),
.iwb_rst_i (wb_rst),
.iwb_ack_i (wb_s2m_or1k_i_ack),
.iwb_err_i (wb_s2m_or1k_i_err),
.iwb_rty_i (wb_s2m_or1k_i_rty),
.iwb_dat_i (wb_s2m_or1k_i_dat),
.iwb_cyc_o (wb_m2s_or1k_i_cyc),
.iwb_adr_o (wb_m2s_or1k_i_adr),
.iwb_stb_o (wb_m2s_or1k_i_stb),
.iwb_we_o (wb_m2s_or1k_i_we),
.iwb_sel_o (wb_m2s_or1k_i_sel),
.iwb_dat_o (wb_m2s_or1k_i_dat),
.iwb_cti_o (wb_m2s_or1k_i_cti),
.iwb_bte_o (wb_m2s_or1k_i_bte),
// Data bus, clocks, reset
.dwb_clk_i (wb_clk),
.dwb_rst_i (wb_rst),
.dwb_ack_i (wb_s2m_or1k_d_ack),
.dwb_err_i (wb_s2m_or1k_d_err),
.dwb_rty_i (wb_s2m_or1k_d_rty),
.dwb_dat_i (wb_s2m_or1k_d_dat),
.dwb_cyc_o (wb_m2s_or1k_d_cyc),
.dwb_adr_o (wb_m2s_or1k_d_adr),
.dwb_stb_o (wb_m2s_or1k_d_stb),
.dwb_we_o (wb_m2s_or1k_d_we),
.dwb_sel_o (wb_m2s_or1k_d_sel),
.dwb_dat_o (wb_m2s_or1k_d_dat),
.dwb_cti_o (wb_m2s_or1k_d_cti),
.dwb_bte_o (wb_m2s_or1k_d_bte),
// Debug interface ports
.dbg_stall_i (or1k_dbg_stall_i),
.dbg_ewt_i (1'b0),
.dbg_lss_o (or1k_dbg_lss_o),
.dbg_is_o (or1k_dbg_is_o),
.dbg_wp_o (or1k_dbg_wp_o),
.dbg_bp_o (or1k_dbg_bp_o),
.dbg_adr_i (or1k_dbg_adr_i),
.dbg_we_i (or1k_dbg_we_i),
.dbg_stb_i (or1k_dbg_stb_i),
.dbg_dat_i (or1k_dbg_dat_i),
.dbg_dat_o (or1k_dbg_dat_o),
.dbg_ack_o (or1k_dbg_ack_o),
.pm_clksd_o (),
.pm_dc_gate_o (),
.pm_ic_gate_o (),
.pm_dmmu_gate_o (),
.pm_immu_gate_o (),
.pm_tt_gate_o (),
.pm_cpu_gate_o (),
.pm_wakeup_o (),
.pm_lvolt_o (),
// Core clocks, resets
.clk_i (wb_clk),
.rst_i (or1k_rst),
.clmode_i (2'b00),
// Interrupts
.pic_ints_i (or1k_irq[30:0]),
.sig_tick (sig_tick),
.pm_cpustall_i (1'b0)
);
`else
mor1kx #(
.FEATURE_DEBUGUNIT ("ENABLED"),
.FEATURE_CMOV ("ENABLED"),
.FEATURE_INSTRUCTIONCACHE ("ENABLED"),
.OPTION_ICACHE_BLOCK_WIDTH (5),
.OPTION_ICACHE_SET_WIDTH (3),
.OPTION_ICACHE_WAYS (2),
.OPTION_ICACHE_LIMIT_WIDTH (32),
.FEATURE_IMMU ("ENABLED"),
.FEATURE_DATACACHE ("ENABLED"),
.OPTION_DCACHE_BLOCK_WIDTH (5),
.OPTION_DCACHE_SET_WIDTH (3),
.OPTION_DCACHE_WAYS (2),
.OPTION_DCACHE_LIMIT_WIDTH (31),
.FEATURE_DMMU ("ENABLED"),
.OPTION_PIC_TRIGGER ("LATCHED_LEVEL"),
.IBUS_WB_TYPE ("B3_REGISTERED_FEEDBACK"),
.DBUS_WB_TYPE ("B3_REGISTERED_FEEDBACK"),
.OPTION_CPU0 ("CAPPUCCINO"),
.OPTION_RESET_PC (32'hf0000100)
) mor1kx0 (
.iwbm_adr_o (wb_m2s_or1k_i_adr),
.iwbm_stb_o (wb_m2s_or1k_i_stb),
.iwbm_cyc_o (wb_m2s_or1k_i_cyc),
.iwbm_sel_o (wb_m2s_or1k_i_sel),
.iwbm_we_o (wb_m2s_or1k_i_we),
.iwbm_cti_o (wb_m2s_or1k_i_cti),
.iwbm_bte_o (wb_m2s_or1k_i_bte),
.iwbm_dat_o (wb_m2s_or1k_i_dat),
.dwbm_adr_o (wb_m2s_or1k_d_adr),
.dwbm_stb_o (wb_m2s_or1k_d_stb),
.dwbm_cyc_o (wb_m2s_or1k_d_cyc),
.dwbm_sel_o (wb_m2s_or1k_d_sel),
.dwbm_we_o (wb_m2s_or1k_d_we ),
.dwbm_cti_o (wb_m2s_or1k_d_cti),
.dwbm_bte_o (wb_m2s_or1k_d_bte),
.dwbm_dat_o (wb_m2s_or1k_d_dat),
.clk (wb_clk),
.rst (or1k_rst),
.iwbm_err_i (wb_s2m_or1k_i_err),
.iwbm_ack_i (wb_s2m_or1k_i_ack),
.iwbm_dat_i (wb_s2m_or1k_i_dat),
.iwbm_rty_i (wb_s2m_or1k_i_rty),
.dwbm_err_i (wb_s2m_or1k_d_err),
.dwbm_ack_i (wb_s2m_or1k_d_ack),
.dwbm_dat_i (wb_s2m_or1k_d_dat),
.dwbm_rty_i (wb_s2m_or1k_d_rty),
.irq_i (or1k_irq),
.du_addr_i (or1k_dbg_adr_i[15:0]),
.du_stb_i (or1k_dbg_stb_i),
.du_dat_i (or1k_dbg_dat_i),
.du_we_i (or1k_dbg_we_i),
.du_dat_o (or1k_dbg_dat_o),
.du_ack_o (or1k_dbg_ack_o),
.du_stall_i (or1k_dbg_stall_i),
.du_stall_o (or1k_dbg_bp_o)
);
`endif
////////////////////////////////////////////////////////////////////////
//
// Debug Interface
//
////////////////////////////////////////////////////////////////////////
adbg_top dbg_if0 (
// OR1K interface
.cpu0_clk_i (wb_clk),
.cpu0_rst_o (or1k_dbg_rst),
.cpu0_addr_o (or1k_dbg_adr_i),
.cpu0_data_o (or1k_dbg_dat_i),
.cpu0_stb_o (or1k_dbg_stb_i),
.cpu0_we_o (or1k_dbg_we_i),
.cpu0_data_i (or1k_dbg_dat_o),
.cpu0_ack_i (or1k_dbg_ack_o),
.cpu0_stall_o (or1k_dbg_stall_i),
.cpu0_bp_i (or1k_dbg_bp_o),
// TAP interface
.tck_i (dbg_tck),
.tdi_i (jtag_tap_tdo),
.tdo_o (dbg_if_tdo),
.rst_i (wb_rst),
.capture_dr_i (jtag_tap_capture_dr),
.shift_dr_i (jtag_tap_shift_dr),
.pause_dr_i (jtag_tap_pause_dr),
.update_dr_i (jtag_tap_update_dr),
.debug_select_i (dbg_if_select),
// Wishbone debug master
.wb_clk_i (wb_clk),
.wb_dat_i (wb_s2m_dbg_dat),
.wb_ack_i (wb_s2m_dbg_ack),
.wb_err_i (wb_s2m_dbg_err),
.wb_adr_o (wb_m2s_dbg_adr),
.wb_dat_o (wb_m2s_dbg_dat),
.wb_cyc_o (wb_m2s_dbg_cyc),
.wb_stb_o (wb_m2s_dbg_stb),
.wb_sel_o (wb_m2s_dbg_sel),
.wb_we_o (wb_m2s_dbg_we),
.wb_cti_o (wb_m2s_dbg_cti),
.wb_bte_o (wb_m2s_dbg_bte)
);
////////////////////////////////////////////////////////////////////////
//
// ROM
//
////////////////////////////////////////////////////////////////////////
assign wb_s2m_rom0_err = 1'b0;
assign wb_s2m_rom0_rty = 1'b0;
`ifdef BOOTROM
rom #(.ADDR_WIDTH(rom0_aw))
rom0 (
.wb_clk (wb_clk),
.wb_rst (wb_rst),
.wb_adr_i (wb_m2s_rom0_adr[(rom0_aw + 2) - 1 : 2]),
.wb_cyc_i (wb_m2s_rom0_cyc),
.wb_stb_i (wb_m2s_rom0_stb),
.wb_cti_i (wb_m2s_rom0_cti),
.wb_bte_i (wb_m2s_rom0_bte),
.wb_dat_o (wb_s2m_rom0_dat),
.wb_ack_o (wb_s2m_rom0_ack)
);
`else
assign wb_s2m_rom0_dat_o = 0;
assign wb_s2m_rom0_ack_o = 0;
`endif
////////////////////////////////////////////////////////////////////////
//
// SDRAM Memory Controller
//
////////////////////////////////////////////////////////////////////////
wire [15:0] sdram_dq_i;
wire [15:0] sdram_dq_o;
wire sdram_dq_oe;
assign sdram_dq_i = sdram_dq_pad_io;
assign sdram_dq_pad_io = sdram_dq_oe ? sdram_dq_o : 16'bz;
assign sdram_clk_pad_o = sdram_clk;
assign wb_s2m_sdram_ibus_err = 0;
assign wb_s2m_sdram_ibus_rty = 0;
assign wb_s2m_sdram_dbus_err = 0;
assign wb_s2m_sdram_dbus_rty = 0;
wb_sdram_ctrl #(
`ifdef ICARUS_SIM
.TECHNOLOGY ("GENERIC"),
`else
.TECHNOLOGY ("ALTERA"),
`endif
.CLK_FREQ_MHZ (100), // sdram_clk freq in MHZ
`ifdef SIM
.POWERUP_DELAY (1), // power up delay in us
`endif
.WB_PORTS (2), // Number of wishbone ports
.BUF_WIDTH (3),
.BURST_LENGTH (8),
.ROW_WIDTH (12), // Row width
.COL_WIDTH (8), // Column width
.BA_WIDTH (2), // Ba width
.tCAC (3), // CAS Latency
.tRAC (5), // RAS Latency
.tRP (3), // Command Period (PRE to ACT)
.tRC (7), // Command Period (REF to REF / ACT to ACT)
.tMRD (2) // Mode Register Set To Command Delay time
)
wb_sdram_ctrl0 (
// External SDRAM interface
.ba_pad_o (sdram_ba_pad_o[1:0]),
.a_pad_o (sdram_a_pad_o[11:0]),
.cs_n_pad_o (sdram_cs_n_pad_o),
.ras_pad_o (sdram_ras_pad_o),
.cas_pad_o (sdram_cas_pad_o),
.we_pad_o (sdram_we_pad_o),
.dq_i (sdram_dq_i[15:0]),
.dq_o (sdram_dq_o[15:0]),
.dqm_pad_o (sdram_dqm_pad_o[1:0]),
.dq_oe (sdram_dq_oe),
.cke_pad_o (sdram_cke_pad_o),
.sdram_clk (sdram_clk),
.sdram_rst (sdram_rst),
.wb_clk (wb_clk),
.wb_rst (wb_rst),
.wb_adr_i ({wb_m2s_sdram_ibus_adr, wb_m2s_sdram_dbus_adr}),
.wb_stb_i ({wb_m2s_sdram_ibus_stb, wb_m2s_sdram_dbus_stb}),
.wb_cyc_i ({wb_m2s_sdram_ibus_cyc, wb_m2s_sdram_dbus_cyc}),
.wb_cti_i ({wb_m2s_sdram_ibus_cti, wb_m2s_sdram_dbus_cti}),
.wb_bte_i ({wb_m2s_sdram_ibus_bte, wb_m2s_sdram_dbus_bte}),
.wb_we_i ({wb_m2s_sdram_ibus_we, wb_m2s_sdram_dbus_we }),
.wb_sel_i ({wb_m2s_sdram_ibus_sel, wb_m2s_sdram_dbus_sel}),
.wb_dat_i ({wb_m2s_sdram_ibus_dat, wb_m2s_sdram_dbus_dat}),
.wb_dat_o ({wb_s2m_sdram_ibus_dat, wb_s2m_sdram_dbus_dat}),
.wb_ack_o ({wb_s2m_sdram_ibus_ack, wb_s2m_sdram_dbus_ack})
);
////////////////////////////////////////////////////////////////////////
//
// UART0
//
////////////////////////////////////////////////////////////////////////
wire uart0_irq;
assign wb_s2m_uart0_err = 0;
assign wb_s2m_uart0_rty = 0;
uart_top uart16550_0 (
// Wishbone slave interface
.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.wb_adr_i (wb_m2s_uart0_adr[uart0_aw-1:0]),
.wb_dat_i (wb_m2s_uart0_dat),
.wb_we_i (wb_m2s_uart0_we),
.wb_stb_i (wb_m2s_uart0_stb),
.wb_cyc_i (wb_m2s_uart0_cyc),
.wb_sel_i (4'b0), // Not used in 8-bit mode
.wb_dat_o (wb_s2m_uart0_dat),
.wb_ack_o (wb_s2m_uart0_ack),
// Outputs
.int_o (uart0_irq),
.stx_pad_o (uart0_stx_pad_o),
.rts_pad_o (),
.dtr_pad_o (),
// Inputs
.srx_pad_i (uart0_srx_pad_i),
.cts_pad_i (1'b0),
.dsr_pad_i (1'b0),
.ri_pad_i (1'b0),
.dcd_pad_i (1'b0)
);
////////////////////////////////////////////////////////////////////////
//
// GPIO 0
//
////////////////////////////////////////////////////////////////////////
wire [7:0] gpio0_in;
wire [7:0] gpio0_out;
wire [7:0] gpio0_dir;
// Tristate logic for IO
// 0 = input, 1 = output
genvar i;
generate
for (i = 0; i < 8; i = i+1) begin: gpio0_tris
assign gpio0_io[i] = gpio0_dir[i] ? gpio0_out[i] : 1'bz;
assign gpio0_in[i] = gpio0_dir[i] ? gpio0_out[i] : gpio0_io[i];
end
endgenerate
gpio gpio0 (
// GPIO bus
.gpio_i (gpio0_in),
.gpio_o (gpio0_out),
.gpio_dir_o (gpio0_dir),
// Wishbone slave interface
.wb_adr_i (wb_m2s_gpio0_adr[0]),
.wb_dat_i (wb_m2s_gpio0_dat),
.wb_we_i (wb_m2s_gpio0_we),
.wb_cyc_i (wb_m2s_gpio0_cyc),
.wb_stb_i (wb_m2s_gpio0_stb),
.wb_cti_i (wb_m2s_gpio0_cti),
.wb_bte_i (wb_m2s_gpio0_bte),
.wb_dat_o (wb_s2m_gpio0_dat),
.wb_ack_o (wb_s2m_gpio0_ack),
.wb_err_o (wb_s2m_gpio0_err),
.wb_rty_o (wb_s2m_gpio0_rty),
.wb_clk (wb_clk),
.wb_rst (wb_rst)
);
gpio key0 (
// Key bus
.gpio_i ({4'h0, key_pad_i}),
.gpio_o (),
.gpio_dir_o (),
// Wishbone slave interface
.wb_adr_i (wb_m2s_key_adr[0]),
.wb_dat_i (wb_m2s_key_dat),
.wb_we_i (wb_m2s_key_we),
.wb_cyc_i (wb_m2s_key_cyc),
.wb_stb_i (wb_m2s_key_stb),
.wb_cti_i (wb_m2s_key_cti),
.wb_bte_i (wb_m2s_key_bte),
.wb_dat_o (wb_s2m_key_dat),
.wb_ack_o (wb_s2m_key_ack),
.wb_err_o (wb_s2m_key_err),
.wb_rty_o (wb_s2m_key_rty),
.wb_clk (wb_clk),
.wb_rst (wb_rst)
);
gpio ledr0 (
// LED R bus 0
.gpio_i (),
.gpio_o (led_r_pad_o[7:0]),
.gpio_dir_o (),
// Wishbone slave interface
.wb_adr_i (wb_m2s_ledr0_adr[0]),
.wb_dat_i (wb_m2s_ledr0_dat),
.wb_we_i (wb_m2s_ledr0_we),
.wb_cyc_i (wb_m2s_ledr0_cyc),
.wb_stb_i (wb_m2s_ledr0_stb),
.wb_cti_i (wb_m2s_ledr0_cti),
.wb_bte_i (wb_m2s_ledr0_bte),
.wb_dat_o (wb_s2m_ledr0_dat),
.wb_ack_o (wb_s2m_ledr0_ack),
.wb_err_o (wb_s2m_ledr0_err),
.wb_rty_o (wb_s2m_ledr0_rty),
.wb_clk (wb_clk),
.wb_rst (wb_rst)
);
gpio ledr1 (
// LED R bus 1
.gpio_i (),
.gpio_o (led_r_pad_o[15:8]),
.gpio_dir_o (),
// Wishbone slave interface
.wb_adr_i (wb_m2s_ledr1_adr[0]),
.wb_dat_i (wb_m2s_ledr1_dat),
.wb_we_i (wb_m2s_ledr1_we),
.wb_cyc_i (wb_m2s_ledr1_cyc),
.wb_stb_i (wb_m2s_ledr1_stb),
.wb_cti_i (wb_m2s_ledr1_cti),
.wb_bte_i (wb_m2s_ledr1_bte),
.wb_dat_o (wb_s2m_ledr1_dat),
.wb_ack_o (wb_s2m_ledr1_ack),
.wb_err_o (wb_s2m_ledr1_err),
.wb_rty_o (wb_s2m_ledr1_rty),
.wb_clk (wb_clk),
.wb_rst (wb_rst)
);
gpio ledg0 (
// GPIO bus
.gpio_i (),
.gpio_o (led_g_pad_o),
.gpio_dir_o (),
// Wishbone slave interface
.wb_adr_i (wb_m2s_ledg0_adr[0]),
.wb_dat_i (wb_m2s_ledg0_dat),
.wb_we_i (wb_m2s_ledg0_we),
.wb_cyc_i (wb_m2s_ledg0_cyc),
.wb_stb_i (wb_m2s_ledg0_stb),
.wb_cti_i (wb_m2s_ledg0_cti),
.wb_bte_i (wb_m2s_ledg0_bte),
.wb_dat_o (wb_s2m_ledg0_dat),
.wb_ack_o (wb_s2m_ledg0_ack),
.wb_err_o (wb_s2m_ledg0_err),
.wb_rty_o (wb_s2m_ledg0_rty),
.wb_clk (wb_clk),
.wb_rst (wb_rst)
);
gpio switch0 (
// GPIO bus
.gpio_i (switch_pad_i[7:0]),
.gpio_o (),
.gpio_dir_o (),
// Wishbone slave interface
.wb_adr_i (wb_m2s_switch0_adr[0]),
.wb_dat_i (wb_m2s_switch0_dat),
.wb_we_i (wb_m2s_switch0_we),
.wb_cyc_i (wb_m2s_switch0_cyc),
.wb_stb_i (wb_m2s_switch0_stb),
.wb_cti_i (wb_m2s_switch0_cti),
.wb_bte_i (wb_m2s_switch0_bte),
.wb_dat_o (wb_s2m_switch0_dat),
.wb_ack_o (wb_s2m_switch0_ack),
.wb_err_o (wb_s2m_switch0_err),
.wb_rty_o (wb_s2m_switch0_rty),
.wb_clk (wb_clk),
.wb_rst (wb_rst)
);
gpio switch1 (
// GPIO bus
.gpio_i (switch_pad_i[15:8]),
.gpio_o (),
.gpio_dir_o (),
// Wishbone slave interface
.wb_adr_i (wb_m2s_switch1_adr[0]),
.wb_dat_i (wb_m2s_switch1_dat),
.wb_we_i (wb_m2s_switch1_we),
.wb_cyc_i (wb_m2s_switch1_cyc),
.wb_stb_i (wb_m2s_switch1_stb),
.wb_cti_i (wb_m2s_switch1_cti),
.wb_bte_i (wb_m2s_switch1_bte),
.wb_dat_o (wb_s2m_switch1_dat),
.wb_ack_o (wb_s2m_switch1_ack),
.wb_err_o (wb_s2m_switch1_err),
.wb_rty_o (wb_s2m_switch1_rty),
.wb_clk (wb_clk),
.wb_rst (wb_rst)
);
gpio switch2 (
// GPIO bus
.gpio_i ({6'h0, switch_pad_i[17:16]}),
.gpio_o (),
.gpio_dir_o (),
// Wishbone slave interface
.wb_adr_i (wb_m2s_switch2_adr[0]),
.wb_dat_i (wb_m2s_switch2_dat),
.wb_we_i (wb_m2s_switch2_we),
.wb_cyc_i (wb_m2s_switch2_cyc),
.wb_stb_i (wb_m2s_switch2_stb),
.wb_cti_i (wb_m2s_switch2_cti),
.wb_bte_i (wb_m2s_switch2_bte),
.wb_dat_o (wb_s2m_switch2_dat),
.wb_ack_o (wb_s2m_switch2_ack),
.wb_err_o (wb_s2m_switch2_err),
.wb_rty_o (wb_s2m_switch2_rty),
.wb_clk (wb_clk),
.wb_rst (wb_rst)
);
////////////////////////////////////////////////////////////////////////
//
// Interrupt assignment
//
////////////////////////////////////////////////////////////////////////
assign or1k_irq[0] = 0; // Non-maskable inside OR1K
assign or1k_irq[1] = 0; // Non-maskable inside OR1K
assign or1k_irq[2] = uart0_irq;
assign or1k_irq[3] = 0;
assign or1k_irq[4] = 0;
assign or1k_irq[5] = 0;
assign or1k_irq[6] = 0;
assign or1k_irq[7] = 0;
assign or1k_irq[8] = 0;
assign or1k_irq[9] = 0;
assign or1k_irq[10] = 0;
assign or1k_irq[11] = 0;
assign or1k_irq[12] = 0;
assign or1k_irq[13] = 0;
assign or1k_irq[14] = 0;
assign or1k_irq[15] = 0;
assign or1k_irq[16] = 0;
assign or1k_irq[17] = 0;
assign or1k_irq[18] = 0;
assign or1k_irq[19] = 0;
assign or1k_irq[20] = 0;
assign or1k_irq[21] = 0;
assign or1k_irq[22] = 0;
assign or1k_irq[23] = 0;
assign or1k_irq[24] = 0;
assign or1k_irq[25] = 0;
assign or1k_irq[26] = 0;
assign or1k_irq[27] = 0;
assign or1k_irq[28] = 0;
assign or1k_irq[29] = 0;
assign or1k_irq[30] = 0;
assign or1k_irq[31] = 0;
endmodule // orpsoc_top
|
`include "defines.v"
module openmips (
input wire rst,
input wire clk,
input wire[`RegBus] rom_data_i,
input wire[`RegBus] ram_data_i,
input wire[5:0] int_i,
output wire[`RegBus] rom_addr_o,
output wire rom_ce_o,
output wire[`RegBus] ram_addr_o,
output wire[`RegBus] ram_data_o,
output wire[3:0] ram_sel_o,
output wire ram_we_o,
output wire ram_ce_o,
output wire timer_int_o
);
// PC 与 rom_addr_o 的连接
wire[`InstAddrBus] pc;
// 连接 IF/ID 模块与译码阶段 ID 模块的变量
wire[`InstAddrBus] id_pc_i;
wire[`InstBus] id_inst_i;
wire id_current_inst_loaded;
// 连接译码阶段的 ID 模块输出与 ID/EX 模块的连接
wire[`AluOpBus] id_aluop_o;
wire[`AluSelBus] id_alusel_o;
wire[`RegBus] id_reg1_o;
wire[`RegBus] id_reg2_o;
wire[`RegAddrBus] id_waddr_o;
wire id_we_o;
wire next_inst_in_delayslot_o;
wire[`RegBus] link_addr_o;
wire is_in_delayslot_o;
wire[`RegBus] id_inst_o;
wire[`RegBus] id_excepttype_o;
wire[`RegBus] id_current_inst_address_o;
wire id_current_inst_loaded_o;
// ID 到 PC
wire branch_flag_o;
wire[`RegBus] branch_target_address_o;
// 连接 ID/EX 模块输出与执行阶段 EX 模块的输入的变量
wire[`AluOpBus] ex_aluop_i;
wire[`AluSelBus] ex_alusel_i;
wire[`RegBus] ex_reg1_i;
wire[`RegBus] ex_reg2_i;
wire[`RegAddrBus] ex_waddr_i;
wire ex_we_i;
wire[`RegBus] ex_link_address;
wire ex_is_in_delayslot;
wire is_delayslot_o;
wire[`RegBus] ex_inst_i;
wire[`RegBus] ex_excepttype_i;
wire[`RegBus] ex_current_inst_addr_i;
// 连接 EX 的输出与 EX/MEM 的输入
wire[`RegAddrBus] ex_waddr_o;
wire ex_we_o;
wire[`RegBus] ex_wdata_o;
wire ex_whilo_o;
wire[`RegBus] ex_hi_o;
wire[`RegBus] ex_lo_o;
wire[`DoubleRegBus] hilo_temp_ex_o;
wire[1:0] cnt_ex_o;
wire[`AluOpBus] ex_aluop_o;
wire[`RegBus] ex_mem_addr_o;
wire[`RegBus] ex_reg2_o;
wire[`RegBus] ex_cp0_reg_data_o;
wire[`RegAddrBus] ex_cp0_reg_waddr_o;
wire ex_cp0_reg_we_o;
wire[`RegBus] ex_excepttype_o;
wire[`RegBus] ex_current_inst_addr_o;
wire ex_current_inst_loaded_o;
wire ex_is_in_delayslot_o;
// 连接 EX 的输出与 DIV 的输入
wire signed_div_o;
wire[`RegBus] div_opdata1_o; // 被除数
wire[`RegBus] div_opdata2_o; // 除数
wire div_start_o;
// 连接 EX 的输出与 CP0 的输入
wire[`RegAddrBus] ex_cp0_reg_raddr_o;
// 连接 EX/MEM 的输出与 EX 的输入
wire[`DoubleRegBus] hilo_temp_ex_mem_o;
wire[1:0] cnt_ex_mem_o;
// 连接 EX/MEM 的输出与 MEM 的输入
wire mem_rst;
wire[`RegAddrBus] mem_waddr_i;
wire mem_we_i;
wire[`RegBus] mem_wdata_i;
wire mem_whilo_i;
wire[`RegBus] mem_hi_i;
wire[`RegBus] mem_lo_i;
wire[`AluOpBus] mem_aluop_i;
wire[`RegBus] mem_mem_addr_i;
wire[`RegBus] mem_reg2_i;
wire[`RegBus] mem_cp0_reg_data_i;
wire[`RegAddrBus] mem_cp0_reg_waddr_i;
wire mem_cp0_reg_we_i;
wire[`RegBus] mem_excepttype_i;
wire[`RegBus] mem_current_inst_addr_i;
wire mem_current_inst_loaded_i;
wire mem_is_in_delayslot_i;
// 连接 MEM 的输出和 MEM/WB 的输入
wire[`RegAddrBus] mem_waddr_o;
wire mem_we_o;
wire[`RegBus] mem_wdata_o;
wire mem_whilo_o;
wire[`RegBus] mem_hi_o;
wire[`RegBus] mem_lo_o;
wire mem_LLbit_we_o;
wire mem_LLbit_value_o;
wire[`RegBus] mem_cp0_reg_data_o;
wire[`RegAddrBus] mem_cp0_reg_waddr_o;
wire mem_cp0_reg_we_o;
// 链接 MEM 的输出和 CP0、CTRL 的输入
wire[`RegBus] mem_cp0_epc_o;
wire[`RegBus] mem_excepttype_o;
wire[`RegBus] mem_current_inst_address_o;
wire mem_current_inst_loaded_o;
wire mem_is_in_delayslot_o;
// 连接 MEM/WB 的输出与回写阶段的输入
wire wb_we_i;
wire[`RegAddrBus] wb_waddr_i;
wire[`RegBus] wb_wdata_i;
wire wb_LLbit_we_i;
wire wb_LLbit_value_i;
// 连接 MEM/WB 的输出与 hilo_reg 的输入
wire hilo_whilo_i;
wire[`RegBus] hilo_hi_i;
wire[`RegBus] hilo_lo_i;
// 连接 MEM/WB 的输出与 CP0 EX 的输入
wire[`RegBus] wb_cp0_reg_data_o;
wire[`RegAddrBus] wb_cp0_reg_waddr_o;
wire wb_cp0_reg_we_o;
// 连接 hilo_reg 的输出与 EX 的输入
wire[`RegBus] hilo_hi_o;
wire[`RegBus] hilo_lo_o;
// 连接 ID 与 Regfile 的连接
wire reg_re1;
wire[`RegAddrBus] reg_raddr1;
wire[`RegBus] reg_rdata1;
wire reg_re2;
wire[`RegAddrBus] reg_raddr2;
wire[`RegBus] reg_rdata2;
// 连接 CTRL 和其他模块
wire[5:0] stall;
wire stallreq_from_id;
wire stallreq_from_ex;
wire[`RegBus] new_pc;
wire flush;
// 连接 DIV 和 EX 模块
wire[`DoubleRegBus] div_result_o;
wire div_result_ready_o;
// 连接 LLbit 模块和 MEM 模块
wire LLbit_o;
// 连接 CP0 模块和 EX 模块
wire[`RegBus] ex_cp0_reg_data_i;
// 连接 CP0 和 MEM
wire[`RegBus] cp0_status_o;
wire[`RegBus] cp0_cause_o;
wire[`RegBus] cp0_epc_o;
// pc_reg 模块例化
pc_reg pc_reg0 (
.clk(clk),
.rst(rst),
.stall(stall),
.branch_flag_i(branch_flag_o),
.branch_target_address_i(branch_target_address_o),
.new_pc(new_pc),
.flush(flush),
.pc(pc),
.ce(rom_ce_o)
);
assign rom_addr_o = pc;
// IF/ID 模块例化
if_id if_id0 (
.clk(clk),
.rst(rst),
.stall(stall),
.flush(flush),
.if_pc(pc),
.if_inst(rom_data_i),
.id_pc(id_pc_i),
.id_inst(id_inst_i),
.id_current_inst_loaded(id_current_inst_loaded)
);
// ID 模块例化
id id0 (
.rst(rst),
.pc_i(id_pc_i),
.inst_i(id_inst_i),
.current_inst_loaded_i(id_current_inst_loaded),
// 来自 regfile 的输入
.reg1_data_i(reg_rdata1),
.reg2_data_i(reg_rdata2),
// 来自 EX 的输入
.ex_waddr_i(ex_waddr_o),
.ex_we_i(ex_we_o),
.ex_wdata_i(ex_wdata_o),
.is_in_delayslot_i(is_delayslot_o),
.ex_aluop_i(ex_aluop_o),
// 来自 MEM 的输入
.mem_waddr_i(mem_waddr_o),
.mem_we_i(mem_we_o),
.mem_wdata_i(mem_wdata_o),
// 输出给 regfile
.reg1_re_o(reg_re1),
.reg2_re_o(reg_re2),
.reg1_addr_o(reg_raddr1),
.reg2_addr_o(reg_raddr2),
// 输出给 ID/EX 模块
.aluop_o(id_aluop_o),
.alusel_o(id_alusel_o),
.reg1_o(id_reg1_o),
.reg2_o(id_reg2_o),
.we_o(id_we_o),
.waddr_o(id_waddr_o),
.next_inst_in_delayslot_o(next_inst_in_delayslot_o),
.link_addr_o(link_addr_o),
.is_in_delayslot_o(is_in_delayslot_o),
.inst_o(id_inst_o),
.excepttype_o(id_excepttype_o),
.current_inst_address_o(id_current_inst_address_o),
.current_inst_loaded_o(id_current_inst_loaded_o),
// 输出给 PC
.branch_flag_o(branch_flag_o),
.branch_target_address_o(branch_target_address_o),
// 输出给 CTRL
.stallreq(stallreq_from_id)
);
// Regfile 模块例化
regfile regfile0 (
.rst(rst),
.clk(clk),
// wb 写输入
.we(wb_we_i),
.waddr(wb_waddr_i),
.wdata(wb_wdata_i),
// id 读输入
.re1(reg_re1),
.re2(reg_re2),
.raddr1(reg_raddr1),
.raddr2(reg_raddr2),
// 输出给 id
.rdata1(reg_rdata1),
.rdata2(reg_rdata2)
);
// ID/EX 模块例化
id_ex id_ex0 (
.clk(clk),
.rst(rst),
.stall(stall),
.flush(flush),
.id_aluop(id_aluop_o),
.id_alusel(id_alusel_o),
.id_reg1(id_reg1_o),
.id_reg2(id_reg2_o),
.id_waddr(id_waddr_o),
.id_we(id_we_o),
.id_link_address(link_addr_o),
.id_is_in_delayslot(is_in_delayslot_o),
.next_inst_in_delayslot_i(next_inst_in_delayslot_o),
.id_inst(id_inst_o),
.id_excepttype(id_excepttype_o),
.id_current_inst_addr(id_current_inst_address_o),
.id_current_inst_loaded(id_current_inst_loaded_o),
.ex_aluop(ex_aluop_i),
.ex_alusel(ex_alusel_i),
.ex_reg1(ex_reg1_i),
.ex_reg2(ex_reg2_i),
.ex_waddr(ex_waddr_i),
.ex_we(ex_we_i),
.ex_link_address(ex_link_address),
.ex_is_in_delayslot(ex_is_in_delayslot),
.is_delayslot_o(is_delayslot_o),
.ex_inst(ex_inst_i),
.ex_excepttype(ex_excepttype_i),
.ex_current_inst_addr(ex_current_inst_addr_i),
.ex_current_inst_loaded(ex_current_inst_loaded_i)
);
// EX 模块例化
ex ex0 (
.rst(rst),
// 从 ID_EX 输入
.aluop_i(ex_aluop_i),
.alusel_i(ex_alusel_i),
.reg1_i(ex_reg1_i),
.reg2_i(ex_reg2_i),
.waddr_i(ex_waddr_i),
.we_i(ex_we_i),
.link_address_i(ex_link_address),
.is_in_delayslot_i(ex_is_in_delayslot),
.inst_i(ex_inst_i),
.aluop_o(ex_aluop_o),
.mem_addr_o(ex_mem_addr_o),
.reg2_o(ex_reg2_o),
.excepttype_i(ex_excepttype_i),
.current_inst_addr_i(ex_current_inst_addr_i),
.current_inst_loaded_i(ex_current_inst_loaded_i),
// 从 EX/MEM 输入
.hilo_temp_i(hilo_temp_ex_mem_o),
.cnt_i(cnt_ex_mem_o),
// 从 MEM 输入
.mem_whilo_i(mem_whilo_o),
.mem_hi_i(mem_hi_o),
.mem_lo_i(mem_lo_o),
.mem_cp0_reg_data(mem_cp0_reg_data_o),
.mem_cp0_reg_waddr(mem_cp0_reg_waddr_o),
.mem_cp0_reg_we(mem_cp0_reg_we_o),
// 从 MEM/WB 输入
.wb_whilo_i(hilo_whilo_i),
.wb_hi_i(hilo_hi_i),
.wb_lo_i(hilo_lo_i),
.wb_cp0_reg_data(wb_cp0_reg_data_o),
.wb_cp0_reg_waddr(wb_cp0_reg_waddr_o),
.wb_cp0_reg_we(wb_cp0_reg_we_o),
// 从 hilo_reg 输入
.hi_i(hilo_hi_o),
.lo_i(hilo_lo_o),
// 从 DIV 输入
.div_result_i(div_result_o),
.div_result_ready_i(div_result_ready_o),
// 从 CP0 输入
.cp0_reg_data_i(ex_cp0_reg_data_i),
// 输出给 EX/MEM
.waddr_o(ex_waddr_o),
.we_o(ex_we_o),
.wdata_o(ex_wdata_o),
.whilo_o(ex_whilo_o),
.hi_o(ex_hi_o),
.lo_o(ex_lo_o),
.hilo_temp_o(hilo_temp_ex_o),
.cnt_o(cnt_ex_o),
.stallreq(stallreq_from_ex),
.cp0_reg_data_o(ex_cp0_reg_data_o),
.cp0_reg_waddr_o(ex_cp0_reg_waddr_o),
.cp0_reg_we_o(ex_cp0_reg_we_o),
.excepttype_o(ex_excepttype_o),
.current_inst_addr_o(ex_current_inst_addr_o),
.current_inst_loaded_o(ex_current_inst_loaded_o),
.is_in_delayslot_o(ex_is_in_delayslot_o),
// 输出给 DIV
.signed_div_o(signed_div_o),
.div_opdata1_o(div_opdata1_o), // 被除数
.div_opdata2_o(div_opdata2_o), // 除数
.div_start_o(div_start_o),
// 输出给 CP0
.cp0_reg_raddr_o(ex_cp0_reg_raddr_o)
);
// EX/MEM 模块例化
ex_mem ex_mem0 (
.rst(rst),
.clk(clk),
.stall(stall),
.flush(flush),
.ex_waddr(ex_waddr_o),
.ex_we(ex_we_o),
.ex_wdata(ex_wdata_o),
.ex_whilo(ex_whilo_o),
.ex_hi(ex_hi_o),
.ex_lo(ex_lo_o),
.hilo_i(hilo_temp_ex_o),
.cnt_i(cnt_ex_o),
.ex_aluop(ex_aluop_o),
.ex_mem_addr(ex_mem_addr_o),
.ex_reg2(ex_reg2_o),
.ex_cp0_reg_data(ex_cp0_reg_data_o),
.ex_cp0_reg_waddr(ex_cp0_reg_waddr_o),
.ex_cp0_reg_we(ex_cp0_reg_we_o),
.ex_excepttype(ex_excepttype_o),
.ex_current_inst_addr(ex_current_inst_addr_o),
.ex_current_inst_loaded(ex_current_inst_loaded_o),
.ex_is_in_delayslot(ex_is_in_delayslot_o),
.mem_waddr(mem_waddr_i),
.mem_we(mem_we_i),
.mem_wdata(mem_wdata_i),
.mem_whilo(mem_whilo_i),
.mem_hi(mem_hi_i),
.mem_lo(mem_lo_i),
.hilo_o(hilo_temp_ex_mem_o),
.cnt_o(cnt_ex_mem_o),
.mem_aluop(mem_aluop_i),
.mem_mem_addr(mem_mem_addr_i),
.mem_reg2(mem_reg2_i),
.mem_cp0_reg_data(mem_cp0_reg_data_i),
.mem_cp0_reg_waddr(mem_cp0_reg_waddr_i),
.mem_cp0_reg_we(mem_cp0_reg_we_i),
.mem_excepttype(mem_excepttype_i),
.mem_current_inst_addr(mem_current_inst_addr_i),
.mem_current_inst_loaded(mem_current_inst_loaded_i),
.mem_is_in_delayslot(mem_is_in_delayslot_i)
);
// MEM 模块例化
mem mem0 (
.rst(rst),
// EX/MEM 的输入
.waddr_i(mem_waddr_i),
.we_i(mem_we_i),
.wdata_i(mem_wdata_i),
.whilo_i(mem_whilo_i),
.hi_i(mem_hi_i),
.lo_i(mem_lo_i),
.aluop_i(mem_aluop_i),
.mem_addr_i(mem_mem_addr_i),
.reg2_i(mem_reg2_i),
.cp0_reg_data_i(mem_cp0_reg_data_i),
.cp0_reg_waddr_i(mem_cp0_reg_waddr_i),
.cp0_reg_we_i(mem_cp0_reg_we_i),
.excepttype_i(mem_excepttype_i),
.current_inst_address_i(mem_current_inst_addr_i),
.current_inst_loaded_i(mem_current_inst_loaded_i),
.is_in_delayslot_i(mem_is_in_delayslot_i),
// RAM 的输入
.mem_data_i(ram_data_i),
.LLbit_i(LLbit_o),
// WB 的输入
.wb_LLbit_we_i(wb_LLbit_we_i),
.wb_LLbit_value_i(wb_LLbit_value_i),
.wb_cp0_reg_we(wb_cp0_reg_we_o),
.wb_cp0_reg_write_addr(wb_cp0_reg_waddr_o),
.wb_cp0_reg_write_data(wb_cp0_reg_data_o),
// CP0 的输入
.cp0_status_i(cp0_status_o),
.cp0_cause_i(cp0_cause_o),
.cp0_epc_i(cp0_epc_o),
// 输出给 MEM/WB
.waddr_o(mem_waddr_o),
.we_o(mem_we_o),
.wdata_o(mem_wdata_o),
.whilo_o(mem_whilo_o),
.hi_o(mem_hi_o),
.lo_o(mem_lo_o),
.mem_addr_o(ram_addr_o),
.mem_we_o(ram_we_o),
.mem_sel_o(ram_sel_o),
.mem_data_o(ram_data_o),
.mem_ce_o(ram_ce_o),
.LLbit_we_o(mem_LLbit_we_o),
.LLbit_value_o(mem_LLbit_value_o),
.cp0_reg_data_o(mem_cp0_reg_data_o),
.cp0_reg_waddr_o(mem_cp0_reg_waddr_o),
.cp0_reg_we_o(mem_cp0_reg_we_o),
.cp0_epc_o(mem_cp0_epc_o),
.excepttype_o(mem_excepttype_o),
.current_inst_address_o(mem_current_inst_address_o),
.current_inst_loaded_o(mem_current_inst_loaded_o),
.is_in_delayslot_o(mem_is_in_delayslot_o)
);
// MEM/WB 模块例化
mem_wb mem_wb0 (
.clk(clk),
.rst(rst),
.stall(stall),
.flush(flush),
// 从 MEM 输入
.mem_waddr(mem_waddr_o),
.mem_we(mem_we_o),
.mem_wdata(mem_wdata_o),
.mem_whilo(mem_whilo_o),
.mem_hi(mem_hi_o),
.mem_lo(mem_lo_o),
.mem_LLbit_we(mem_LLbit_we_o),
.mem_LLbit_value(mem_LLbit_value_o),
.mem_cp0_reg_data(mem_cp0_reg_data_o),
.mem_cp0_reg_waddr(mem_cp0_reg_waddr_o),
.mem_cp0_reg_we(mem_cp0_reg_we_o),
// 输出给 WB
.wb_waddr(wb_waddr_i),
.wb_we(wb_we_i),
.wb_wdata(wb_wdata_i),
.wb_LLbit_we(wb_LLbit_we_i),
.wb_LLbit_value(wb_LLbit_value_i),
// 输出给 hilo_reg
.wb_whilo(hilo_whilo_i),
.wb_hi(hilo_hi_i),
.wb_lo(hilo_lo_i),
// 输出给 CP0 EX
.wb_cp0_reg_data(wb_cp0_reg_data_o),
.wb_cp0_reg_waddr(wb_cp0_reg_waddr_o),
.wb_cp0_reg_we(wb_cp0_reg_we_o)
);
// hilo_reg 模块例化
hilo_reg hilo_reg0 (
.clk(clk),
.rst(rst),
// 从 MEM/WB 输入
.we(hilo_whilo_i),
.hi_i(hilo_hi_i),
.lo_i(hilo_lo_i),
// 输出给 EX
.hi_o(hilo_hi_o),
.lo_o(hilo_lo_o)
);
ctrl ctrl0 (
.rst(rst),
.stallreq_from_id(stallreq_from_id),
.stallreq_from_ex(stallreq_from_ex),
.cp0_epc_i(mem_cp0_epc_o),
.excepttype_i(mem_excepttype_o),
.stall(stall),
.new_pc(new_pc),
.flush(flush)
);
div div0 (
.clk(clk),
.rst(rst),
.signed_div_i(signed_div_o),
.opdata1_i(div_opdata1_o), // 被除数
.opdata2_i(div_opdata2_o), // 除数
.start_i(div_start_o),
.annul_i(1'b0),
.result_o(div_result_o),
.result_ready_o(div_result_ready_o)
);
LLbit_reg LLbit_reg0 (
.clk(clk),
.rst(rst),
.flush(flush),
.LLbit_i(wb_LLbit_value_i),
.we(wb_LLbit_we_i),
.LLbit_o(LLbit_o)
);
cp0_reg cp0_reg0 (
.clk(clk),
.rst(rst),
.raddr_i(ex_cp0_reg_raddr_o),
.data_i(wb_cp0_reg_data_o),
.waddr_i(wb_cp0_reg_waddr_o),
.we_i(wb_cp0_reg_we_o),
.int_i(int_i),
.excepttype_i(mem_excepttype_o),
.mem_current_inst_addr_i(mem_current_inst_address_o),
.mem_current_inst_loaded(mem_current_inst_loaded_o),
.mem_is_in_delayslot_i(mem_is_in_delayslot_o),
.ex_current_inst_addr_i(ex_current_inst_addr_o),
.ex_current_inst_loaded(ex_current_inst_loaded_o),
.ex_is_in_delayslot_i(ex_is_in_delayslot_o),
.id_current_inst_addr_i(id_current_inst_address_o),
.id_current_inst_loaded(id_current_inst_loaded_o),
.id_is_in_delayslot_i(is_in_delayslot_o),
.pc_current_inst_addr_i(pc),
.data_o(ex_cp0_reg_data_i),
.status_o(cp0_status_o),
.cause_o(cp0_cause_o),
.epc_o(cp0_epc_o),
.timer_int_o(timer_int_o)
);
endmodule |
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
// Date : Mon Sep 16 05:33:33 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_2_sim_netlist.v
// Design : design_1_processing_system7_0_2
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "design_1_processing_system7_0_2,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2018.2" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
IRQ_F2P,
FCLK_CLK0,
FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *) output [1:0]USB0_PORT_INDCTL;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *) output USB0_VBUS_PWRSELECT;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *) input USB0_VBUS_PWRFAULT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) output M_AXI_GP0_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) output M_AXI_GP0_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) output M_AXI_GP0_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) output M_AXI_GP0_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) output M_AXI_GP0_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) output M_AXI_GP0_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) output [11:0]M_AXI_GP0_ARID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) output [11:0]M_AXI_GP0_AWID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) output [11:0]M_AXI_GP0_WID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) output [1:0]M_AXI_GP0_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) output [1:0]M_AXI_GP0_ARLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) output [2:0]M_AXI_GP0_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) output [1:0]M_AXI_GP0_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) output [1:0]M_AXI_GP0_AWLOCK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) output [2:0]M_AXI_GP0_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) output [2:0]M_AXI_GP0_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) output [2:0]M_AXI_GP0_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) output [31:0]M_AXI_GP0_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) output [31:0]M_AXI_GP0_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) output [31:0]M_AXI_GP0_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) output [3:0]M_AXI_GP0_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) output [3:0]M_AXI_GP0_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) output [3:0]M_AXI_GP0_ARQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) output [3:0]M_AXI_GP0_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) output [3:0]M_AXI_GP0_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) output [3:0]M_AXI_GP0_AWQOS;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) output [3:0]M_AXI_GP0_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0" *) input M_AXI_GP0_ACLK;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) input M_AXI_GP0_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) input M_AXI_GP0_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) input M_AXI_GP0_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) input M_AXI_GP0_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) input M_AXI_GP0_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) input M_AXI_GP0_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) input [11:0]M_AXI_GP0_BID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input [11:0]M_AXI_GP0_RID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input [1:0]M_AXI_GP0_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input [1:0]M_AXI_GP0_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 50000000, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input [31:0]M_AXI_GP0_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH, PortWidth 1" *) input [0:0]IRQ_F2P;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 50000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_2_FCLK_CLK0" *) output FCLK_CLK0;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW" *) output FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11" *) inout [3:0]DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout PS_PORB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire FCLK_CLK0;
wire FCLK_RESET0_N;
wire [0:0]IRQ_F2P;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]M_AXI_GP0_ARCACHE;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [2:0]M_AXI_GP0_ARSIZE;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]M_AXI_GP0_AWCACHE;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [2:0]M_AXI_GP0_AWSIZE;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
wire NLW_inst_DMA0_RSTN_UNCONNECTED;
wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
wire NLW_inst_DMA1_RSTN_UNCONNECTED;
wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
wire NLW_inst_DMA2_RSTN_UNCONNECTED;
wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
wire NLW_inst_DMA3_RSTN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
wire NLW_inst_FCLK_CLK1_UNCONNECTED;
wire NLW_inst_FCLK_CLK2_UNCONNECTED;
wire NLW_inst_FCLK_CLK3_UNCONNECTED;
wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
wire NLW_inst_I2C0_SCL_O_UNCONNECTED;
wire NLW_inst_I2C0_SCL_T_UNCONNECTED;
wire NLW_inst_I2C0_SDA_O_UNCONNECTED;
wire NLW_inst_I2C0_SDA_T_UNCONNECTED;
wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
wire NLW_inst_PJTAG_TDO_UNCONNECTED;
wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO0_CLK_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO0_LED_UNCONNECTED;
wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO1_CLK_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO1_LED_UNCONNECTED;
wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_T_UNCONNECTED;
wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_T_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
wire NLW_inst_TRACE_CTL_UNCONNECTED;
wire NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_UART0_DTRN_UNCONNECTED;
wire NLW_inst_UART0_RTSN_UNCONNECTED;
wire NLW_inst_UART0_TX_UNCONNECTED;
wire NLW_inst_UART1_DTRN_UNCONNECTED;
wire NLW_inst_UART1_RTSN_UNCONNECTED;
wire NLW_inst_UART1_TX_UNCONNECTED;
wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_O_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_T_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
(* C_DM_WIDTH = "4" *)
(* C_DQS_WIDTH = "4" *)
(* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *)
(* C_EN_EMIO_ENET0 = "0" *)
(* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *)
(* C_EN_EMIO_TRACE = "0" *)
(* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *)
(* C_FCLK_CLK2_BUF = "FALSE" *)
(* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "1" *)
(* C_GP1_EN_MODIFIABLE_TXN = "1" *)
(* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *)
(* C_IRQ_F2P_MODE = "DIRECT" *)
(* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP0_ID_WIDTH = "12" *)
(* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP1_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *)
(* C_PACKAGE_NAME = "clg400" *)
(* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *)
(* C_S_AXI_ACP_AWUSER_VAL = "31" *)
(* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *)
(* C_S_AXI_GP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *)
(* C_S_AXI_HP1_DATA_WIDTH = "64" *)
(* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *)
(* C_S_AXI_HP2_ID_WIDTH = "6" *)
(* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *)
(* C_TRACE_BUFFER_CLOCK_DELAY = "12" *)
(* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *)
(* C_TRACE_PIPELINE_WIDTH = "8" *)
(* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *)
(* C_USE_M_AXI_GP0 = "1" *)
(* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *)
(* C_USE_S_AXI_GP0 = "0" *)
(* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *)
(* C_USE_S_AXI_HP1 = "0" *)
(* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *)
(* HW_HANDOFF = "design_1_processing_system7_0_2.hwdef" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={667} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={32} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={50} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 inst
(.CAN0_PHY_RX(1'b0),
.CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
.CAN1_PHY_RX(1'b0),
.CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
.Core0_nFIQ(1'b0),
.Core0_nIRQ(1'b0),
.Core1_nFIQ(1'b0),
.Core1_nIRQ(1'b0),
.DDR_ARB({1'b0,1'b0,1'b0,1'b0}),
.DDR_Addr(DDR_Addr),
.DDR_BankAddr(DDR_BankAddr),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_CS_n(DDR_CS_n),
.DDR_Clk(DDR_Clk),
.DDR_Clk_n(DDR_Clk_n),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS(DDR_DQS),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_WEB(DDR_WEB),
.DMA0_ACLK(1'b0),
.DMA0_DAREADY(1'b0),
.DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
.DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
.DMA0_DRLAST(1'b0),
.DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
.DMA0_DRTYPE({1'b0,1'b0}),
.DMA0_DRVALID(1'b0),
.DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
.DMA1_ACLK(1'b0),
.DMA1_DAREADY(1'b0),
.DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
.DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
.DMA1_DRLAST(1'b0),
.DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
.DMA1_DRTYPE({1'b0,1'b0}),
.DMA1_DRVALID(1'b0),
.DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
.DMA2_ACLK(1'b0),
.DMA2_DAREADY(1'b0),
.DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
.DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
.DMA2_DRLAST(1'b0),
.DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
.DMA2_DRTYPE({1'b0,1'b0}),
.DMA2_DRVALID(1'b0),
.DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
.DMA3_ACLK(1'b0),
.DMA3_DAREADY(1'b0),
.DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
.DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
.DMA3_DRLAST(1'b0),
.DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
.DMA3_DRTYPE({1'b0,1'b0}),
.DMA3_DRVALID(1'b0),
.DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
.ENET0_EXT_INTIN(1'b0),
.ENET0_GMII_COL(1'b0),
.ENET0_GMII_CRS(1'b0),
.ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET0_GMII_RX_CLK(1'b0),
.ENET0_GMII_RX_DV(1'b0),
.ENET0_GMII_RX_ER(1'b0),
.ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
.ENET0_GMII_TX_CLK(1'b0),
.ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
.ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
.ENET0_MDIO_I(1'b0),
.ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
.ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
.ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
.ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
.ENET1_EXT_INTIN(1'b0),
.ENET1_GMII_COL(1'b0),
.ENET1_GMII_CRS(1'b0),
.ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET1_GMII_RX_CLK(1'b0),
.ENET1_GMII_RX_DV(1'b0),
.ENET1_GMII_RX_ER(1'b0),
.ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
.ENET1_GMII_TX_CLK(1'b0),
.ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
.ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
.ENET1_MDIO_I(1'b0),
.ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
.ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
.ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
.ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
.EVENT_EVENTI(1'b0),
.EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
.EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
.EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
.FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
.FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
.FCLK_CLKTRIG0_N(1'b0),
.FCLK_CLKTRIG1_N(1'b0),
.FCLK_CLKTRIG2_N(1'b0),
.FCLK_CLKTRIG3_N(1'b0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
.FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
.FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
.FPGA_IDLE_N(1'b0),
.FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_CLK(1'b0),
.FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_VALID(1'b0),
.FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
.FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
.FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
.FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
.FTMT_F2P_TRIG_0(1'b0),
.FTMT_F2P_TRIG_1(1'b0),
.FTMT_F2P_TRIG_2(1'b0),
.FTMT_F2P_TRIG_3(1'b0),
.FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
.FTMT_P2F_TRIGACK_0(1'b0),
.FTMT_P2F_TRIGACK_1(1'b0),
.FTMT_P2F_TRIGACK_2(1'b0),
.FTMT_P2F_TRIGACK_3(1'b0),
.FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
.FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
.FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
.FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
.GPIO_I({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.GPIO_O(NLW_inst_GPIO_O_UNCONNECTED[63:0]),
.GPIO_T(NLW_inst_GPIO_T_UNCONNECTED[63:0]),
.I2C0_SCL_I(1'b0),
.I2C0_SCL_O(NLW_inst_I2C0_SCL_O_UNCONNECTED),
.I2C0_SCL_T(NLW_inst_I2C0_SCL_T_UNCONNECTED),
.I2C0_SDA_I(1'b0),
.I2C0_SDA_O(NLW_inst_I2C0_SDA_O_UNCONNECTED),
.I2C0_SDA_T(NLW_inst_I2C0_SDA_T_UNCONNECTED),
.I2C1_SCL_I(1'b0),
.I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
.I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
.I2C1_SDA_I(1'b0),
.I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
.I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
.IRQ_F2P(IRQ_F2P),
.IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
.IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
.IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
.IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
.IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
.IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
.IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
.IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
.IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
.IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
.IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
.IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
.IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
.IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
.IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
.IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
.IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
.IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
.IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
.IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
.IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
.IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
.IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
.IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
.IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
.IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
.IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
.IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
.IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
.MIO(MIO),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP1_ACLK(1'b0),
.M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
.M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
.M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_ARREADY(1'b0),
.M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
.M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
.M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_AWREADY(1'b0),
.M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
.M_AXI_GP1_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
.M_AXI_GP1_BRESP({1'b0,1'b0}),
.M_AXI_GP1_BVALID(1'b0),
.M_AXI_GP1_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RLAST(1'b0),
.M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
.M_AXI_GP1_RRESP({1'b0,1'b0}),
.M_AXI_GP1_RVALID(1'b0),
.M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
.M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
.M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
.M_AXI_GP1_WREADY(1'b0),
.M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
.M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
.PJTAG_TCK(1'b0),
.PJTAG_TDI(1'b0),
.PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
.PJTAG_TMS(1'b0),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB),
.PS_SRSTB(PS_SRSTB),
.SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
.SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
.SDIO0_CDN(1'b0),
.SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
.SDIO0_CLK_FB(1'b0),
.SDIO0_CMD_I(1'b0),
.SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
.SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
.SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
.SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
.SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
.SDIO0_WP(1'b0),
.SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
.SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
.SDIO1_CDN(1'b0),
.SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
.SDIO1_CLK_FB(1'b0),
.SDIO1_CMD_I(1'b0),
.SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
.SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
.SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
.SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
.SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
.SDIO1_WP(1'b0),
.SPI0_MISO_I(1'b0),
.SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
.SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
.SPI0_MOSI_I(1'b0),
.SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
.SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
.SPI0_SCLK_I(1'b0),
.SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
.SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
.SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
.SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
.SPI0_SS_I(1'b0),
.SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
.SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
.SPI1_MISO_I(1'b0),
.SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
.SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
.SPI1_MOSI_I(1'b0),
.SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
.SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
.SPI1_SCLK_I(1'b0),
.SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
.SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
.SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
.SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
.SPI1_SS_I(1'b0),
.SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
.SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
.SRAM_INTIN(1'b0),
.S_AXI_ACP_ACLK(1'b0),
.S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARBURST({1'b0,1'b0}),
.S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
.S_AXI_ACP_ARID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLOCK({1'b0,1'b0}),
.S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
.S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARVALID(1'b0),
.S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWBURST({1'b0,1'b0}),
.S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLOCK({1'b0,1'b0}),
.S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
.S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWVALID(1'b0),
.S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
.S_AXI_ACP_BREADY(1'b0),
.S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
.S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
.S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
.S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
.S_AXI_ACP_RREADY(1'b0),
.S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
.S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_WLAST(1'b0),
.S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
.S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WVALID(1'b0),
.S_AXI_GP0_ACLK(1'b0),
.S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARBURST({1'b0,1'b0}),
.S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
.S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLOCK({1'b0,1'b0}),
.S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
.S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARVALID(1'b0),
.S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWBURST({1'b0,1'b0}),
.S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLOCK({1'b0,1'b0}),
.S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
.S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWVALID(1'b0),
.S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
.S_AXI_GP0_BREADY(1'b0),
.S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
.S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
.S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
.S_AXI_GP0_RREADY(1'b0),
.S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
.S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WLAST(1'b0),
.S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
.S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WVALID(1'b0),
.S_AXI_GP1_ACLK(1'b0),
.S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARBURST({1'b0,1'b0}),
.S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
.S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLOCK({1'b0,1'b0}),
.S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
.S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARVALID(1'b0),
.S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWBURST({1'b0,1'b0}),
.S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLOCK({1'b0,1'b0}),
.S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
.S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWVALID(1'b0),
.S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
.S_AXI_GP1_BREADY(1'b0),
.S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
.S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
.S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
.S_AXI_GP1_RREADY(1'b0),
.S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
.S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WLAST(1'b0),
.S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
.S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WVALID(1'b0),
.S_AXI_HP0_ACLK(1'b0),
.S_AXI_HP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARBURST({1'b0,1'b0}),
.S_AXI_HP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
.S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLOCK({1'b0,1'b0}),
.S_AXI_HP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
.S_AXI_HP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARVALID(1'b0),
.S_AXI_HP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWBURST({1'b0,1'b0}),
.S_AXI_HP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLOCK({1'b0,1'b0}),
.S_AXI_HP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
.S_AXI_HP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWVALID(1'b0),
.S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
.S_AXI_HP0_BREADY(1'b0),
.S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
.S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP0_RDISSUECAP1_EN(1'b0),
.S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
.S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
.S_AXI_HP0_RREADY(1'b0),
.S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
.S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WLAST(1'b0),
.S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
.S_AXI_HP0_WRISSUECAP1_EN(1'b0),
.S_AXI_HP0_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WVALID(1'b0),
.S_AXI_HP1_ACLK(1'b0),
.S_AXI_HP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARBURST({1'b0,1'b0}),
.S_AXI_HP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
.S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLOCK({1'b0,1'b0}),
.S_AXI_HP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
.S_AXI_HP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARVALID(1'b0),
.S_AXI_HP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWBURST({1'b0,1'b0}),
.S_AXI_HP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLOCK({1'b0,1'b0}),
.S_AXI_HP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
.S_AXI_HP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWVALID(1'b0),
.S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
.S_AXI_HP1_BREADY(1'b0),
.S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
.S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP1_RDISSUECAP1_EN(1'b0),
.S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
.S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
.S_AXI_HP1_RREADY(1'b0),
.S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
.S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WLAST(1'b0),
.S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
.S_AXI_HP1_WRISSUECAP1_EN(1'b0),
.S_AXI_HP1_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WVALID(1'b0),
.S_AXI_HP2_ACLK(1'b0),
.S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARBURST({1'b0,1'b0}),
.S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
.S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLOCK({1'b0,1'b0}),
.S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
.S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARVALID(1'b0),
.S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWBURST({1'b0,1'b0}),
.S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLOCK({1'b0,1'b0}),
.S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
.S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWVALID(1'b0),
.S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
.S_AXI_HP2_BREADY(1'b0),
.S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
.S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP2_RDISSUECAP1_EN(1'b0),
.S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
.S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
.S_AXI_HP2_RREADY(1'b0),
.S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
.S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WLAST(1'b0),
.S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
.S_AXI_HP2_WRISSUECAP1_EN(1'b0),
.S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WVALID(1'b0),
.S_AXI_HP3_ACLK(1'b0),
.S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARBURST({1'b0,1'b0}),
.S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
.S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLOCK({1'b0,1'b0}),
.S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
.S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARVALID(1'b0),
.S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWBURST({1'b0,1'b0}),
.S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLOCK({1'b0,1'b0}),
.S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
.S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWVALID(1'b0),
.S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
.S_AXI_HP3_BREADY(1'b0),
.S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
.S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP3_RDISSUECAP1_EN(1'b0),
.S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
.S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
.S_AXI_HP3_RREADY(1'b0),
.S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
.S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WLAST(1'b0),
.S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
.S_AXI_HP3_WRISSUECAP1_EN(1'b0),
.S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WVALID(1'b0),
.TRACE_CLK(1'b0),
.TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
.TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
.TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
.TTC0_CLK0_IN(1'b0),
.TTC0_CLK1_IN(1'b0),
.TTC0_CLK2_IN(1'b0),
.TTC0_WAVE0_OUT(NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED),
.TTC0_WAVE1_OUT(NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED),
.TTC0_WAVE2_OUT(NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED),
.TTC1_CLK0_IN(1'b0),
.TTC1_CLK1_IN(1'b0),
.TTC1_CLK2_IN(1'b0),
.TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
.TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
.TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
.UART0_CTSN(1'b0),
.UART0_DCDN(1'b0),
.UART0_DSRN(1'b0),
.UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
.UART0_RIN(1'b0),
.UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
.UART0_RX(1'b1),
.UART0_TX(NLW_inst_UART0_TX_UNCONNECTED),
.UART1_CTSN(1'b0),
.UART1_DCDN(1'b0),
.UART1_DSRN(1'b0),
.UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
.UART1_RIN(1'b0),
.UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
.UART1_RX(1'b1),
.UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
.USB0_PORT_INDCTL(USB0_PORT_INDCTL),
.USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT),
.USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT),
.USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
.USB1_VBUS_PWRFAULT(1'b0),
.USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
.WDT_CLK_IN(1'b0),
.WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
endmodule
(* C_DM_WIDTH = "4" *) (* C_DQS_WIDTH = "4" *) (* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *) (* C_EN_EMIO_ENET0 = "0" *) (* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "TRUE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *) (* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "1" *) (* C_GP1_EN_MODIFIABLE_TXN = "1" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP0_ID_WIDTH = "12" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP1_ID_WIDTH = "12" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *) (* C_PACKAGE_NAME = "clg400" *) (* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *) (* C_S_AXI_ACP_AWUSER_VAL = "31" *) (* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *) (* C_S_AXI_GP1_ID_WIDTH = "6" *) (* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *) (* C_S_AXI_HP1_DATA_WIDTH = "64" *) (* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *) (* C_S_AXI_HP2_ID_WIDTH = "6" *) (* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *) (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) (* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *) (* C_TRACE_PIPELINE_WIDTH = "8" *) (* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *) (* C_USE_M_AXI_GP0 = "1" *) (* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "design_1_processing_system7_0_2.hwdef" *) (* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={667} load={0.5} /><MEMORY name={code} memType={DDR3(LowVoltage)} dataWidth={32} clockFreq={533.333333} readRate={0.5} writeRate={0.5} /><IO interface={GPIO_Bank_1} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={1} usageRate={0.5} /><IO interface={GPIO_Bank_0} ioStandard={LVCMOS33} bidis={9} ioBank={Vcco_p0} clockFreq={1} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={100.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={LVCMOS18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={7} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1333.333} /><PLL domain={Memory} vco={1066.667} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={50} usageRate={0.5} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7
(CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_EXT_INTIN,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_EXT_INTIN,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TDI,
PJTAG_TDO,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
TRACE_CLK_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_PORT_INDCTL,
USB1_VBUS_PWRSELECT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARESETN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARESETN,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARESETN,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARESETN,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_ARESETN,
S_AXI_ACP_ARREADY,
S_AXI_ACP_AWREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARESETN,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARESETN,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARESETN,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARESETN,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_RSTN,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_RSTN,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_RSTN,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_RSTN,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA3_DRVALID,
DMA0_DRTYPE,
DMA1_DRTYPE,
DMA2_DRTYPE,
DMA3_DRTYPE,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG_0,
FTMT_F2P_TRIGACK_0,
FTMT_F2P_TRIG_1,
FTMT_F2P_TRIGACK_1,
FTMT_F2P_TRIG_2,
FTMT_F2P_TRIGACK_2,
FTMT_F2P_TRIG_3,
FTMT_F2P_TRIGACK_3,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK_0,
FTMT_P2F_TRIG_0,
FTMT_P2F_TRIGACK_1,
FTMT_P2F_TRIG_1,
FTMT_P2F_TRIGACK_2,
FTMT_P2F_TRIG_2,
FTMT_P2F_TRIGACK_3,
FTMT_P2F_TRIG_3,
FTMT_P2F_DEBUG,
FPGA_IDLE_N,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
DDR_ARB,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0]ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input ENET0_EXT_INTIN;
input [7:0]ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0]ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input ENET1_EXT_INTIN;
input [7:0]ENET1_GMII_RXD;
input [63:0]GPIO_I;
output [63:0]GPIO_O;
output [63:0]GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TDI;
output PJTAG_TDO;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0]SDIO0_DATA_I;
output [3:0]SDIO0_DATA_O;
output [3:0]SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0]SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0]SDIO1_DATA_I;
output [3:0]SDIO1_DATA_O;
output [3:0]SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0]SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [1:0]TRACE_DATA;
output TRACE_CLK_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output [1:0]USB1_PORT_INDCTL;
output USB1_VBUS_PWRSELECT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARESETN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output M_AXI_GP1_ARESETN;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [11:0]M_AXI_GP1_ARID;
output [11:0]M_AXI_GP1_AWID;
output [11:0]M_AXI_GP1_WID;
output [1:0]M_AXI_GP1_ARBURST;
output [1:0]M_AXI_GP1_ARLOCK;
output [2:0]M_AXI_GP1_ARSIZE;
output [1:0]M_AXI_GP1_AWBURST;
output [1:0]M_AXI_GP1_AWLOCK;
output [2:0]M_AXI_GP1_AWSIZE;
output [2:0]M_AXI_GP1_ARPROT;
output [2:0]M_AXI_GP1_AWPROT;
output [31:0]M_AXI_GP1_ARADDR;
output [31:0]M_AXI_GP1_AWADDR;
output [31:0]M_AXI_GP1_WDATA;
output [3:0]M_AXI_GP1_ARCACHE;
output [3:0]M_AXI_GP1_ARLEN;
output [3:0]M_AXI_GP1_ARQOS;
output [3:0]M_AXI_GP1_AWCACHE;
output [3:0]M_AXI_GP1_AWLEN;
output [3:0]M_AXI_GP1_AWQOS;
output [3:0]M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [11:0]M_AXI_GP1_BID;
input [11:0]M_AXI_GP1_RID;
input [1:0]M_AXI_GP1_BRESP;
input [1:0]M_AXI_GP1_RRESP;
input [31:0]M_AXI_GP1_RDATA;
output S_AXI_GP0_ARESETN;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0]S_AXI_GP0_BRESP;
output [1:0]S_AXI_GP0_RRESP;
output [31:0]S_AXI_GP0_RDATA;
output [5:0]S_AXI_GP0_BID;
output [5:0]S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0]S_AXI_GP0_ARBURST;
input [1:0]S_AXI_GP0_ARLOCK;
input [2:0]S_AXI_GP0_ARSIZE;
input [1:0]S_AXI_GP0_AWBURST;
input [1:0]S_AXI_GP0_AWLOCK;
input [2:0]S_AXI_GP0_AWSIZE;
input [2:0]S_AXI_GP0_ARPROT;
input [2:0]S_AXI_GP0_AWPROT;
input [31:0]S_AXI_GP0_ARADDR;
input [31:0]S_AXI_GP0_AWADDR;
input [31:0]S_AXI_GP0_WDATA;
input [3:0]S_AXI_GP0_ARCACHE;
input [3:0]S_AXI_GP0_ARLEN;
input [3:0]S_AXI_GP0_ARQOS;
input [3:0]S_AXI_GP0_AWCACHE;
input [3:0]S_AXI_GP0_AWLEN;
input [3:0]S_AXI_GP0_AWQOS;
input [3:0]S_AXI_GP0_WSTRB;
input [5:0]S_AXI_GP0_ARID;
input [5:0]S_AXI_GP0_AWID;
input [5:0]S_AXI_GP0_WID;
output S_AXI_GP1_ARESETN;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0]S_AXI_GP1_BRESP;
output [1:0]S_AXI_GP1_RRESP;
output [31:0]S_AXI_GP1_RDATA;
output [5:0]S_AXI_GP1_BID;
output [5:0]S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0]S_AXI_GP1_ARBURST;
input [1:0]S_AXI_GP1_ARLOCK;
input [2:0]S_AXI_GP1_ARSIZE;
input [1:0]S_AXI_GP1_AWBURST;
input [1:0]S_AXI_GP1_AWLOCK;
input [2:0]S_AXI_GP1_AWSIZE;
input [2:0]S_AXI_GP1_ARPROT;
input [2:0]S_AXI_GP1_AWPROT;
input [31:0]S_AXI_GP1_ARADDR;
input [31:0]S_AXI_GP1_AWADDR;
input [31:0]S_AXI_GP1_WDATA;
input [3:0]S_AXI_GP1_ARCACHE;
input [3:0]S_AXI_GP1_ARLEN;
input [3:0]S_AXI_GP1_ARQOS;
input [3:0]S_AXI_GP1_AWCACHE;
input [3:0]S_AXI_GP1_AWLEN;
input [3:0]S_AXI_GP1_AWQOS;
input [3:0]S_AXI_GP1_WSTRB;
input [5:0]S_AXI_GP1_ARID;
input [5:0]S_AXI_GP1_AWID;
input [5:0]S_AXI_GP1_WID;
output S_AXI_ACP_ARESETN;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0]S_AXI_ACP_BRESP;
output [1:0]S_AXI_ACP_RRESP;
output [2:0]S_AXI_ACP_BID;
output [2:0]S_AXI_ACP_RID;
output [63:0]S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0]S_AXI_ACP_ARID;
input [2:0]S_AXI_ACP_ARPROT;
input [2:0]S_AXI_ACP_AWID;
input [2:0]S_AXI_ACP_AWPROT;
input [2:0]S_AXI_ACP_WID;
input [31:0]S_AXI_ACP_ARADDR;
input [31:0]S_AXI_ACP_AWADDR;
input [3:0]S_AXI_ACP_ARCACHE;
input [3:0]S_AXI_ACP_ARLEN;
input [3:0]S_AXI_ACP_ARQOS;
input [3:0]S_AXI_ACP_AWCACHE;
input [3:0]S_AXI_ACP_AWLEN;
input [3:0]S_AXI_ACP_AWQOS;
input [1:0]S_AXI_ACP_ARBURST;
input [1:0]S_AXI_ACP_ARLOCK;
input [2:0]S_AXI_ACP_ARSIZE;
input [1:0]S_AXI_ACP_AWBURST;
input [1:0]S_AXI_ACP_AWLOCK;
input [2:0]S_AXI_ACP_AWSIZE;
input [4:0]S_AXI_ACP_ARUSER;
input [4:0]S_AXI_ACP_AWUSER;
input [63:0]S_AXI_ACP_WDATA;
input [7:0]S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARESETN;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0]S_AXI_HP0_BRESP;
output [1:0]S_AXI_HP0_RRESP;
output [5:0]S_AXI_HP0_BID;
output [5:0]S_AXI_HP0_RID;
output [63:0]S_AXI_HP0_RDATA;
output [7:0]S_AXI_HP0_RCOUNT;
output [7:0]S_AXI_HP0_WCOUNT;
output [2:0]S_AXI_HP0_RACOUNT;
output [5:0]S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0]S_AXI_HP0_ARBURST;
input [1:0]S_AXI_HP0_ARLOCK;
input [2:0]S_AXI_HP0_ARSIZE;
input [1:0]S_AXI_HP0_AWBURST;
input [1:0]S_AXI_HP0_AWLOCK;
input [2:0]S_AXI_HP0_AWSIZE;
input [2:0]S_AXI_HP0_ARPROT;
input [2:0]S_AXI_HP0_AWPROT;
input [31:0]S_AXI_HP0_ARADDR;
input [31:0]S_AXI_HP0_AWADDR;
input [3:0]S_AXI_HP0_ARCACHE;
input [3:0]S_AXI_HP0_ARLEN;
input [3:0]S_AXI_HP0_ARQOS;
input [3:0]S_AXI_HP0_AWCACHE;
input [3:0]S_AXI_HP0_AWLEN;
input [3:0]S_AXI_HP0_AWQOS;
input [5:0]S_AXI_HP0_ARID;
input [5:0]S_AXI_HP0_AWID;
input [5:0]S_AXI_HP0_WID;
input [63:0]S_AXI_HP0_WDATA;
input [7:0]S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARESETN;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0]S_AXI_HP1_BRESP;
output [1:0]S_AXI_HP1_RRESP;
output [5:0]S_AXI_HP1_BID;
output [5:0]S_AXI_HP1_RID;
output [63:0]S_AXI_HP1_RDATA;
output [7:0]S_AXI_HP1_RCOUNT;
output [7:0]S_AXI_HP1_WCOUNT;
output [2:0]S_AXI_HP1_RACOUNT;
output [5:0]S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0]S_AXI_HP1_ARBURST;
input [1:0]S_AXI_HP1_ARLOCK;
input [2:0]S_AXI_HP1_ARSIZE;
input [1:0]S_AXI_HP1_AWBURST;
input [1:0]S_AXI_HP1_AWLOCK;
input [2:0]S_AXI_HP1_AWSIZE;
input [2:0]S_AXI_HP1_ARPROT;
input [2:0]S_AXI_HP1_AWPROT;
input [31:0]S_AXI_HP1_ARADDR;
input [31:0]S_AXI_HP1_AWADDR;
input [3:0]S_AXI_HP1_ARCACHE;
input [3:0]S_AXI_HP1_ARLEN;
input [3:0]S_AXI_HP1_ARQOS;
input [3:0]S_AXI_HP1_AWCACHE;
input [3:0]S_AXI_HP1_AWLEN;
input [3:0]S_AXI_HP1_AWQOS;
input [5:0]S_AXI_HP1_ARID;
input [5:0]S_AXI_HP1_AWID;
input [5:0]S_AXI_HP1_WID;
input [63:0]S_AXI_HP1_WDATA;
input [7:0]S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARESETN;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0]S_AXI_HP2_BRESP;
output [1:0]S_AXI_HP2_RRESP;
output [5:0]S_AXI_HP2_BID;
output [5:0]S_AXI_HP2_RID;
output [63:0]S_AXI_HP2_RDATA;
output [7:0]S_AXI_HP2_RCOUNT;
output [7:0]S_AXI_HP2_WCOUNT;
output [2:0]S_AXI_HP2_RACOUNT;
output [5:0]S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0]S_AXI_HP2_ARBURST;
input [1:0]S_AXI_HP2_ARLOCK;
input [2:0]S_AXI_HP2_ARSIZE;
input [1:0]S_AXI_HP2_AWBURST;
input [1:0]S_AXI_HP2_AWLOCK;
input [2:0]S_AXI_HP2_AWSIZE;
input [2:0]S_AXI_HP2_ARPROT;
input [2:0]S_AXI_HP2_AWPROT;
input [31:0]S_AXI_HP2_ARADDR;
input [31:0]S_AXI_HP2_AWADDR;
input [3:0]S_AXI_HP2_ARCACHE;
input [3:0]S_AXI_HP2_ARLEN;
input [3:0]S_AXI_HP2_ARQOS;
input [3:0]S_AXI_HP2_AWCACHE;
input [3:0]S_AXI_HP2_AWLEN;
input [3:0]S_AXI_HP2_AWQOS;
input [5:0]S_AXI_HP2_ARID;
input [5:0]S_AXI_HP2_AWID;
input [5:0]S_AXI_HP2_WID;
input [63:0]S_AXI_HP2_WDATA;
input [7:0]S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARESETN;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0]S_AXI_HP3_BRESP;
output [1:0]S_AXI_HP3_RRESP;
output [5:0]S_AXI_HP3_BID;
output [5:0]S_AXI_HP3_RID;
output [63:0]S_AXI_HP3_RDATA;
output [7:0]S_AXI_HP3_RCOUNT;
output [7:0]S_AXI_HP3_WCOUNT;
output [2:0]S_AXI_HP3_RACOUNT;
output [5:0]S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0]S_AXI_HP3_ARBURST;
input [1:0]S_AXI_HP3_ARLOCK;
input [2:0]S_AXI_HP3_ARSIZE;
input [1:0]S_AXI_HP3_AWBURST;
input [1:0]S_AXI_HP3_AWLOCK;
input [2:0]S_AXI_HP3_AWSIZE;
input [2:0]S_AXI_HP3_ARPROT;
input [2:0]S_AXI_HP3_AWPROT;
input [31:0]S_AXI_HP3_ARADDR;
input [31:0]S_AXI_HP3_AWADDR;
input [3:0]S_AXI_HP3_ARCACHE;
input [3:0]S_AXI_HP3_ARLEN;
input [3:0]S_AXI_HP3_ARQOS;
input [3:0]S_AXI_HP3_AWCACHE;
input [3:0]S_AXI_HP3_AWLEN;
input [3:0]S_AXI_HP3_AWQOS;
input [5:0]S_AXI_HP3_ARID;
input [5:0]S_AXI_HP3_AWID;
input [5:0]S_AXI_HP3_WID;
input [63:0]S_AXI_HP3_WDATA;
input [7:0]S_AXI_HP3_WSTRB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
input [0:0]IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output [1:0]DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
output DMA0_RSTN;
output [1:0]DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
output DMA1_RSTN;
output [1:0]DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
output DMA2_RSTN;
output [1:0]DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
output DMA3_RSTN;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input DMA3_DRVALID;
input [1:0]DMA0_DRTYPE;
input [1:0]DMA1_DRTYPE;
input [1:0]DMA2_DRTYPE;
input [1:0]DMA3_DRTYPE;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input [31:0]FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0]FTMD_TRACEIN_ATID;
input FTMT_F2P_TRIG_0;
output FTMT_F2P_TRIGACK_0;
input FTMT_F2P_TRIG_1;
output FTMT_F2P_TRIGACK_1;
input FTMT_F2P_TRIG_2;
output FTMT_F2P_TRIGACK_2;
input FTMT_F2P_TRIG_3;
output FTMT_F2P_TRIGACK_3;
input [31:0]FTMT_F2P_DEBUG;
input FTMT_P2F_TRIGACK_0;
output FTMT_P2F_TRIG_0;
input FTMT_P2F_TRIGACK_1;
output FTMT_P2F_TRIG_1;
input FTMT_P2F_TRIGACK_2;
output FTMT_P2F_TRIG_2;
input FTMT_P2F_TRIGACK_3;
output FTMT_P2F_TRIG_3;
output [31:0]FTMT_P2F_DEBUG;
input FPGA_IDLE_N;
output EVENT_EVENTO;
output [1:0]EVENT_STANDBYWFE;
output [1:0]EVENT_STANDBYWFI;
input EVENT_EVENTI;
input [3:0]DDR_ARB;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
wire \<const0> ;
wire \<const1> ;
wire CAN0_PHY_RX;
wire CAN0_PHY_TX;
wire CAN1_PHY_RX;
wire CAN1_PHY_TX;
wire Core0_nFIQ;
wire Core0_nIRQ;
wire Core1_nFIQ;
wire Core1_nIRQ;
wire [3:0]DDR_ARB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire DMA0_ACLK;
wire DMA0_DAREADY;
wire [1:0]DMA0_DATYPE;
wire DMA0_DAVALID;
wire DMA0_DRLAST;
wire DMA0_DRREADY;
wire [1:0]DMA0_DRTYPE;
wire DMA0_DRVALID;
wire DMA0_RSTN;
wire DMA1_ACLK;
wire DMA1_DAREADY;
wire [1:0]DMA1_DATYPE;
wire DMA1_DAVALID;
wire DMA1_DRLAST;
wire DMA1_DRREADY;
wire [1:0]DMA1_DRTYPE;
wire DMA1_DRVALID;
wire DMA1_RSTN;
wire DMA2_ACLK;
wire DMA2_DAREADY;
wire [1:0]DMA2_DATYPE;
wire DMA2_DAVALID;
wire DMA2_DRLAST;
wire DMA2_DRREADY;
wire [1:0]DMA2_DRTYPE;
wire DMA2_DRVALID;
wire DMA2_RSTN;
wire DMA3_ACLK;
wire DMA3_DAREADY;
wire [1:0]DMA3_DATYPE;
wire DMA3_DAVALID;
wire DMA3_DRLAST;
wire DMA3_DRREADY;
wire [1:0]DMA3_DRTYPE;
wire DMA3_DRVALID;
wire DMA3_RSTN;
wire ENET0_EXT_INTIN;
wire ENET0_GMII_RX_CLK;
wire ENET0_GMII_TX_CLK;
wire ENET0_MDIO_I;
wire ENET0_MDIO_MDC;
wire ENET0_MDIO_O;
wire ENET0_MDIO_T;
wire ENET0_MDIO_T_n;
wire ENET0_PTP_DELAY_REQ_RX;
wire ENET0_PTP_DELAY_REQ_TX;
wire ENET0_PTP_PDELAY_REQ_RX;
wire ENET0_PTP_PDELAY_REQ_TX;
wire ENET0_PTP_PDELAY_RESP_RX;
wire ENET0_PTP_PDELAY_RESP_TX;
wire ENET0_PTP_SYNC_FRAME_RX;
wire ENET0_PTP_SYNC_FRAME_TX;
wire ENET0_SOF_RX;
wire ENET0_SOF_TX;
wire ENET1_EXT_INTIN;
wire ENET1_GMII_RX_CLK;
wire ENET1_GMII_TX_CLK;
wire ENET1_MDIO_I;
wire ENET1_MDIO_MDC;
wire ENET1_MDIO_O;
wire ENET1_MDIO_T;
wire ENET1_MDIO_T_n;
wire ENET1_PTP_DELAY_REQ_RX;
wire ENET1_PTP_DELAY_REQ_TX;
wire ENET1_PTP_PDELAY_REQ_RX;
wire ENET1_PTP_PDELAY_REQ_TX;
wire ENET1_PTP_PDELAY_RESP_RX;
wire ENET1_PTP_PDELAY_RESP_TX;
wire ENET1_PTP_SYNC_FRAME_RX;
wire ENET1_PTP_SYNC_FRAME_TX;
wire ENET1_SOF_RX;
wire ENET1_SOF_TX;
wire EVENT_EVENTI;
wire EVENT_EVENTO;
wire [1:0]EVENT_STANDBYWFE;
wire [1:0]EVENT_STANDBYWFI;
wire FCLK_CLK0;
wire FCLK_CLK1;
wire FCLK_CLK2;
wire FCLK_CLK3;
wire [0:0]FCLK_CLK_unbuffered;
wire FCLK_RESET0_N;
wire FCLK_RESET1_N;
wire FCLK_RESET2_N;
wire FCLK_RESET3_N;
wire FPGA_IDLE_N;
wire FTMD_TRACEIN_CLK;
wire [31:0]FTMT_F2P_DEBUG;
wire FTMT_F2P_TRIGACK_0;
wire FTMT_F2P_TRIGACK_1;
wire FTMT_F2P_TRIGACK_2;
wire FTMT_F2P_TRIGACK_3;
wire FTMT_F2P_TRIG_0;
wire FTMT_F2P_TRIG_1;
wire FTMT_F2P_TRIG_2;
wire FTMT_F2P_TRIG_3;
wire [31:0]FTMT_P2F_DEBUG;
wire FTMT_P2F_TRIGACK_0;
wire FTMT_P2F_TRIGACK_1;
wire FTMT_P2F_TRIGACK_2;
wire FTMT_P2F_TRIGACK_3;
wire FTMT_P2F_TRIG_0;
wire FTMT_P2F_TRIG_1;
wire FTMT_P2F_TRIG_2;
wire FTMT_P2F_TRIG_3;
wire [63:0]GPIO_I;
wire [63:0]GPIO_O;
wire [63:0]GPIO_T;
wire I2C0_SCL_I;
wire I2C0_SCL_O;
wire I2C0_SCL_T;
wire I2C0_SCL_T_n;
wire I2C0_SDA_I;
wire I2C0_SDA_O;
wire I2C0_SDA_T;
wire I2C0_SDA_T_n;
wire I2C1_SCL_I;
wire I2C1_SCL_O;
wire I2C1_SCL_T;
wire I2C1_SCL_T_n;
wire I2C1_SDA_I;
wire I2C1_SDA_O;
wire I2C1_SDA_T;
wire I2C1_SDA_T_n;
wire [0:0]IRQ_F2P;
wire IRQ_P2F_CAN0;
wire IRQ_P2F_CAN1;
wire IRQ_P2F_CTI;
wire IRQ_P2F_DMAC0;
wire IRQ_P2F_DMAC1;
wire IRQ_P2F_DMAC2;
wire IRQ_P2F_DMAC3;
wire IRQ_P2F_DMAC4;
wire IRQ_P2F_DMAC5;
wire IRQ_P2F_DMAC6;
wire IRQ_P2F_DMAC7;
wire IRQ_P2F_DMAC_ABORT;
wire IRQ_P2F_ENET0;
wire IRQ_P2F_ENET1;
wire IRQ_P2F_ENET_WAKE0;
wire IRQ_P2F_ENET_WAKE1;
wire IRQ_P2F_GPIO;
wire IRQ_P2F_I2C0;
wire IRQ_P2F_I2C1;
wire IRQ_P2F_QSPI;
wire IRQ_P2F_SDIO0;
wire IRQ_P2F_SDIO1;
wire IRQ_P2F_SMC;
wire IRQ_P2F_SPI0;
wire IRQ_P2F_SPI1;
wire IRQ_P2F_UART0;
wire IRQ_P2F_UART1;
wire IRQ_P2F_USB0;
wire IRQ_P2F_USB1;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]\^M_AXI_GP0_ARCACHE ;
wire M_AXI_GP0_ARESETN;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [1:0]\^M_AXI_GP0_ARSIZE ;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]\^M_AXI_GP0_AWCACHE ;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [1:0]\^M_AXI_GP0_AWSIZE ;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire M_AXI_GP1_ACLK;
wire [31:0]M_AXI_GP1_ARADDR;
wire [1:0]M_AXI_GP1_ARBURST;
wire [3:0]\^M_AXI_GP1_ARCACHE ;
wire M_AXI_GP1_ARESETN;
wire [11:0]M_AXI_GP1_ARID;
wire [3:0]M_AXI_GP1_ARLEN;
wire [1:0]M_AXI_GP1_ARLOCK;
wire [2:0]M_AXI_GP1_ARPROT;
wire [3:0]M_AXI_GP1_ARQOS;
wire M_AXI_GP1_ARREADY;
wire [1:0]\^M_AXI_GP1_ARSIZE ;
wire M_AXI_GP1_ARVALID;
wire [31:0]M_AXI_GP1_AWADDR;
wire [1:0]M_AXI_GP1_AWBURST;
wire [3:0]\^M_AXI_GP1_AWCACHE ;
wire [11:0]M_AXI_GP1_AWID;
wire [3:0]M_AXI_GP1_AWLEN;
wire [1:0]M_AXI_GP1_AWLOCK;
wire [2:0]M_AXI_GP1_AWPROT;
wire [3:0]M_AXI_GP1_AWQOS;
wire M_AXI_GP1_AWREADY;
wire [1:0]\^M_AXI_GP1_AWSIZE ;
wire M_AXI_GP1_AWVALID;
wire [11:0]M_AXI_GP1_BID;
wire M_AXI_GP1_BREADY;
wire [1:0]M_AXI_GP1_BRESP;
wire M_AXI_GP1_BVALID;
wire [31:0]M_AXI_GP1_RDATA;
wire [11:0]M_AXI_GP1_RID;
wire M_AXI_GP1_RLAST;
wire M_AXI_GP1_RREADY;
wire [1:0]M_AXI_GP1_RRESP;
wire M_AXI_GP1_RVALID;
wire [31:0]M_AXI_GP1_WDATA;
wire [11:0]M_AXI_GP1_WID;
wire M_AXI_GP1_WLAST;
wire M_AXI_GP1_WREADY;
wire [3:0]M_AXI_GP1_WSTRB;
wire M_AXI_GP1_WVALID;
wire PJTAG_TCK;
wire PJTAG_TDI;
wire PJTAG_TMS;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire SDIO0_BUSPOW;
wire [2:0]SDIO0_BUSVOLT;
wire SDIO0_CDN;
wire SDIO0_CLK;
wire SDIO0_CLK_FB;
wire SDIO0_CMD_I;
wire SDIO0_CMD_O;
wire SDIO0_CMD_T;
wire SDIO0_CMD_T_n;
wire [3:0]SDIO0_DATA_I;
wire [3:0]SDIO0_DATA_O;
wire [3:0]SDIO0_DATA_T;
wire [3:0]SDIO0_DATA_T_n;
wire SDIO0_LED;
wire SDIO0_WP;
wire SDIO1_BUSPOW;
wire [2:0]SDIO1_BUSVOLT;
wire SDIO1_CDN;
wire SDIO1_CLK;
wire SDIO1_CLK_FB;
wire SDIO1_CMD_I;
wire SDIO1_CMD_O;
wire SDIO1_CMD_T;
wire SDIO1_CMD_T_n;
wire [3:0]SDIO1_DATA_I;
wire [3:0]SDIO1_DATA_O;
wire [3:0]SDIO1_DATA_T;
wire [3:0]SDIO1_DATA_T_n;
wire SDIO1_LED;
wire SDIO1_WP;
wire SPI0_MISO_I;
wire SPI0_MISO_O;
wire SPI0_MISO_T;
wire SPI0_MISO_T_n;
wire SPI0_MOSI_I;
wire SPI0_MOSI_O;
wire SPI0_MOSI_T;
wire SPI0_MOSI_T_n;
wire SPI0_SCLK_I;
wire SPI0_SCLK_O;
wire SPI0_SCLK_T;
wire SPI0_SCLK_T_n;
wire SPI0_SS1_O;
wire SPI0_SS2_O;
wire SPI0_SS_I;
wire SPI0_SS_O;
wire SPI0_SS_T;
wire SPI0_SS_T_n;
wire SPI1_MISO_I;
wire SPI1_MISO_O;
wire SPI1_MISO_T;
wire SPI1_MISO_T_n;
wire SPI1_MOSI_I;
wire SPI1_MOSI_O;
wire SPI1_MOSI_T;
wire SPI1_MOSI_T_n;
wire SPI1_SCLK_I;
wire SPI1_SCLK_O;
wire SPI1_SCLK_T;
wire SPI1_SCLK_T_n;
wire SPI1_SS1_O;
wire SPI1_SS2_O;
wire SPI1_SS_I;
wire SPI1_SS_O;
wire SPI1_SS_T;
wire SPI1_SS_T_n;
wire SRAM_INTIN;
wire S_AXI_ACP_ACLK;
wire [31:0]S_AXI_ACP_ARADDR;
wire [1:0]S_AXI_ACP_ARBURST;
wire [3:0]S_AXI_ACP_ARCACHE;
wire S_AXI_ACP_ARESETN;
wire [2:0]S_AXI_ACP_ARID;
wire [3:0]S_AXI_ACP_ARLEN;
wire [1:0]S_AXI_ACP_ARLOCK;
wire [2:0]S_AXI_ACP_ARPROT;
wire [3:0]S_AXI_ACP_ARQOS;
wire S_AXI_ACP_ARREADY;
wire [2:0]S_AXI_ACP_ARSIZE;
wire [4:0]S_AXI_ACP_ARUSER;
wire S_AXI_ACP_ARVALID;
wire [31:0]S_AXI_ACP_AWADDR;
wire [1:0]S_AXI_ACP_AWBURST;
wire [3:0]S_AXI_ACP_AWCACHE;
wire [2:0]S_AXI_ACP_AWID;
wire [3:0]S_AXI_ACP_AWLEN;
wire [1:0]S_AXI_ACP_AWLOCK;
wire [2:0]S_AXI_ACP_AWPROT;
wire [3:0]S_AXI_ACP_AWQOS;
wire S_AXI_ACP_AWREADY;
wire [2:0]S_AXI_ACP_AWSIZE;
wire [4:0]S_AXI_ACP_AWUSER;
wire S_AXI_ACP_AWVALID;
wire [2:0]S_AXI_ACP_BID;
wire S_AXI_ACP_BREADY;
wire [1:0]S_AXI_ACP_BRESP;
wire S_AXI_ACP_BVALID;
wire [63:0]S_AXI_ACP_RDATA;
wire [2:0]S_AXI_ACP_RID;
wire S_AXI_ACP_RLAST;
wire S_AXI_ACP_RREADY;
wire [1:0]S_AXI_ACP_RRESP;
wire S_AXI_ACP_RVALID;
wire [63:0]S_AXI_ACP_WDATA;
wire [2:0]S_AXI_ACP_WID;
wire S_AXI_ACP_WLAST;
wire S_AXI_ACP_WREADY;
wire [7:0]S_AXI_ACP_WSTRB;
wire S_AXI_ACP_WVALID;
wire S_AXI_GP0_ACLK;
wire [31:0]S_AXI_GP0_ARADDR;
wire [1:0]S_AXI_GP0_ARBURST;
wire [3:0]S_AXI_GP0_ARCACHE;
wire S_AXI_GP0_ARESETN;
wire [5:0]S_AXI_GP0_ARID;
wire [3:0]S_AXI_GP0_ARLEN;
wire [1:0]S_AXI_GP0_ARLOCK;
wire [2:0]S_AXI_GP0_ARPROT;
wire [3:0]S_AXI_GP0_ARQOS;
wire S_AXI_GP0_ARREADY;
wire [2:0]S_AXI_GP0_ARSIZE;
wire S_AXI_GP0_ARVALID;
wire [31:0]S_AXI_GP0_AWADDR;
wire [1:0]S_AXI_GP0_AWBURST;
wire [3:0]S_AXI_GP0_AWCACHE;
wire [5:0]S_AXI_GP0_AWID;
wire [3:0]S_AXI_GP0_AWLEN;
wire [1:0]S_AXI_GP0_AWLOCK;
wire [2:0]S_AXI_GP0_AWPROT;
wire [3:0]S_AXI_GP0_AWQOS;
wire S_AXI_GP0_AWREADY;
wire [2:0]S_AXI_GP0_AWSIZE;
wire S_AXI_GP0_AWVALID;
wire [5:0]S_AXI_GP0_BID;
wire S_AXI_GP0_BREADY;
wire [1:0]S_AXI_GP0_BRESP;
wire S_AXI_GP0_BVALID;
wire [31:0]S_AXI_GP0_RDATA;
wire [5:0]S_AXI_GP0_RID;
wire S_AXI_GP0_RLAST;
wire S_AXI_GP0_RREADY;
wire [1:0]S_AXI_GP0_RRESP;
wire S_AXI_GP0_RVALID;
wire [31:0]S_AXI_GP0_WDATA;
wire [5:0]S_AXI_GP0_WID;
wire S_AXI_GP0_WLAST;
wire S_AXI_GP0_WREADY;
wire [3:0]S_AXI_GP0_WSTRB;
wire S_AXI_GP0_WVALID;
wire S_AXI_GP1_ACLK;
wire [31:0]S_AXI_GP1_ARADDR;
wire [1:0]S_AXI_GP1_ARBURST;
wire [3:0]S_AXI_GP1_ARCACHE;
wire S_AXI_GP1_ARESETN;
wire [5:0]S_AXI_GP1_ARID;
wire [3:0]S_AXI_GP1_ARLEN;
wire [1:0]S_AXI_GP1_ARLOCK;
wire [2:0]S_AXI_GP1_ARPROT;
wire [3:0]S_AXI_GP1_ARQOS;
wire S_AXI_GP1_ARREADY;
wire [2:0]S_AXI_GP1_ARSIZE;
wire S_AXI_GP1_ARVALID;
wire [31:0]S_AXI_GP1_AWADDR;
wire [1:0]S_AXI_GP1_AWBURST;
wire [3:0]S_AXI_GP1_AWCACHE;
wire [5:0]S_AXI_GP1_AWID;
wire [3:0]S_AXI_GP1_AWLEN;
wire [1:0]S_AXI_GP1_AWLOCK;
wire [2:0]S_AXI_GP1_AWPROT;
wire [3:0]S_AXI_GP1_AWQOS;
wire S_AXI_GP1_AWREADY;
wire [2:0]S_AXI_GP1_AWSIZE;
wire S_AXI_GP1_AWVALID;
wire [5:0]S_AXI_GP1_BID;
wire S_AXI_GP1_BREADY;
wire [1:0]S_AXI_GP1_BRESP;
wire S_AXI_GP1_BVALID;
wire [31:0]S_AXI_GP1_RDATA;
wire [5:0]S_AXI_GP1_RID;
wire S_AXI_GP1_RLAST;
wire S_AXI_GP1_RREADY;
wire [1:0]S_AXI_GP1_RRESP;
wire S_AXI_GP1_RVALID;
wire [31:0]S_AXI_GP1_WDATA;
wire [5:0]S_AXI_GP1_WID;
wire S_AXI_GP1_WLAST;
wire S_AXI_GP1_WREADY;
wire [3:0]S_AXI_GP1_WSTRB;
wire S_AXI_GP1_WVALID;
wire S_AXI_HP0_ACLK;
wire [31:0]S_AXI_HP0_ARADDR;
wire [1:0]S_AXI_HP0_ARBURST;
wire [3:0]S_AXI_HP0_ARCACHE;
wire S_AXI_HP0_ARESETN;
wire [5:0]S_AXI_HP0_ARID;
wire [3:0]S_AXI_HP0_ARLEN;
wire [1:0]S_AXI_HP0_ARLOCK;
wire [2:0]S_AXI_HP0_ARPROT;
wire [3:0]S_AXI_HP0_ARQOS;
wire S_AXI_HP0_ARREADY;
wire [2:0]S_AXI_HP0_ARSIZE;
wire S_AXI_HP0_ARVALID;
wire [31:0]S_AXI_HP0_AWADDR;
wire [1:0]S_AXI_HP0_AWBURST;
wire [3:0]S_AXI_HP0_AWCACHE;
wire [5:0]S_AXI_HP0_AWID;
wire [3:0]S_AXI_HP0_AWLEN;
wire [1:0]S_AXI_HP0_AWLOCK;
wire [2:0]S_AXI_HP0_AWPROT;
wire [3:0]S_AXI_HP0_AWQOS;
wire S_AXI_HP0_AWREADY;
wire [2:0]S_AXI_HP0_AWSIZE;
wire S_AXI_HP0_AWVALID;
wire [5:0]S_AXI_HP0_BID;
wire S_AXI_HP0_BREADY;
wire [1:0]S_AXI_HP0_BRESP;
wire S_AXI_HP0_BVALID;
wire [2:0]S_AXI_HP0_RACOUNT;
wire [7:0]S_AXI_HP0_RCOUNT;
wire [63:0]S_AXI_HP0_RDATA;
wire S_AXI_HP0_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP0_RID;
wire S_AXI_HP0_RLAST;
wire S_AXI_HP0_RREADY;
wire [1:0]S_AXI_HP0_RRESP;
wire S_AXI_HP0_RVALID;
wire [5:0]S_AXI_HP0_WACOUNT;
wire [7:0]S_AXI_HP0_WCOUNT;
wire [63:0]S_AXI_HP0_WDATA;
wire [5:0]S_AXI_HP0_WID;
wire S_AXI_HP0_WLAST;
wire S_AXI_HP0_WREADY;
wire S_AXI_HP0_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP0_WSTRB;
wire S_AXI_HP0_WVALID;
wire S_AXI_HP1_ACLK;
wire [31:0]S_AXI_HP1_ARADDR;
wire [1:0]S_AXI_HP1_ARBURST;
wire [3:0]S_AXI_HP1_ARCACHE;
wire S_AXI_HP1_ARESETN;
wire [5:0]S_AXI_HP1_ARID;
wire [3:0]S_AXI_HP1_ARLEN;
wire [1:0]S_AXI_HP1_ARLOCK;
wire [2:0]S_AXI_HP1_ARPROT;
wire [3:0]S_AXI_HP1_ARQOS;
wire S_AXI_HP1_ARREADY;
wire [2:0]S_AXI_HP1_ARSIZE;
wire S_AXI_HP1_ARVALID;
wire [31:0]S_AXI_HP1_AWADDR;
wire [1:0]S_AXI_HP1_AWBURST;
wire [3:0]S_AXI_HP1_AWCACHE;
wire [5:0]S_AXI_HP1_AWID;
wire [3:0]S_AXI_HP1_AWLEN;
wire [1:0]S_AXI_HP1_AWLOCK;
wire [2:0]S_AXI_HP1_AWPROT;
wire [3:0]S_AXI_HP1_AWQOS;
wire S_AXI_HP1_AWREADY;
wire [2:0]S_AXI_HP1_AWSIZE;
wire S_AXI_HP1_AWVALID;
wire [5:0]S_AXI_HP1_BID;
wire S_AXI_HP1_BREADY;
wire [1:0]S_AXI_HP1_BRESP;
wire S_AXI_HP1_BVALID;
wire [2:0]S_AXI_HP1_RACOUNT;
wire [7:0]S_AXI_HP1_RCOUNT;
wire [63:0]S_AXI_HP1_RDATA;
wire S_AXI_HP1_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP1_RID;
wire S_AXI_HP1_RLAST;
wire S_AXI_HP1_RREADY;
wire [1:0]S_AXI_HP1_RRESP;
wire S_AXI_HP1_RVALID;
wire [5:0]S_AXI_HP1_WACOUNT;
wire [7:0]S_AXI_HP1_WCOUNT;
wire [63:0]S_AXI_HP1_WDATA;
wire [5:0]S_AXI_HP1_WID;
wire S_AXI_HP1_WLAST;
wire S_AXI_HP1_WREADY;
wire S_AXI_HP1_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP1_WSTRB;
wire S_AXI_HP1_WVALID;
wire S_AXI_HP2_ACLK;
wire [31:0]S_AXI_HP2_ARADDR;
wire [1:0]S_AXI_HP2_ARBURST;
wire [3:0]S_AXI_HP2_ARCACHE;
wire S_AXI_HP2_ARESETN;
wire [5:0]S_AXI_HP2_ARID;
wire [3:0]S_AXI_HP2_ARLEN;
wire [1:0]S_AXI_HP2_ARLOCK;
wire [2:0]S_AXI_HP2_ARPROT;
wire [3:0]S_AXI_HP2_ARQOS;
wire S_AXI_HP2_ARREADY;
wire [2:0]S_AXI_HP2_ARSIZE;
wire S_AXI_HP2_ARVALID;
wire [31:0]S_AXI_HP2_AWADDR;
wire [1:0]S_AXI_HP2_AWBURST;
wire [3:0]S_AXI_HP2_AWCACHE;
wire [5:0]S_AXI_HP2_AWID;
wire [3:0]S_AXI_HP2_AWLEN;
wire [1:0]S_AXI_HP2_AWLOCK;
wire [2:0]S_AXI_HP2_AWPROT;
wire [3:0]S_AXI_HP2_AWQOS;
wire S_AXI_HP2_AWREADY;
wire [2:0]S_AXI_HP2_AWSIZE;
wire S_AXI_HP2_AWVALID;
wire [5:0]S_AXI_HP2_BID;
wire S_AXI_HP2_BREADY;
wire [1:0]S_AXI_HP2_BRESP;
wire S_AXI_HP2_BVALID;
wire [2:0]S_AXI_HP2_RACOUNT;
wire [7:0]S_AXI_HP2_RCOUNT;
wire [63:0]S_AXI_HP2_RDATA;
wire S_AXI_HP2_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP2_RID;
wire S_AXI_HP2_RLAST;
wire S_AXI_HP2_RREADY;
wire [1:0]S_AXI_HP2_RRESP;
wire S_AXI_HP2_RVALID;
wire [5:0]S_AXI_HP2_WACOUNT;
wire [7:0]S_AXI_HP2_WCOUNT;
wire [63:0]S_AXI_HP2_WDATA;
wire [5:0]S_AXI_HP2_WID;
wire S_AXI_HP2_WLAST;
wire S_AXI_HP2_WREADY;
wire S_AXI_HP2_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP2_WSTRB;
wire S_AXI_HP2_WVALID;
wire S_AXI_HP3_ACLK;
wire [31:0]S_AXI_HP3_ARADDR;
wire [1:0]S_AXI_HP3_ARBURST;
wire [3:0]S_AXI_HP3_ARCACHE;
wire S_AXI_HP3_ARESETN;
wire [5:0]S_AXI_HP3_ARID;
wire [3:0]S_AXI_HP3_ARLEN;
wire [1:0]S_AXI_HP3_ARLOCK;
wire [2:0]S_AXI_HP3_ARPROT;
wire [3:0]S_AXI_HP3_ARQOS;
wire S_AXI_HP3_ARREADY;
wire [2:0]S_AXI_HP3_ARSIZE;
wire S_AXI_HP3_ARVALID;
wire [31:0]S_AXI_HP3_AWADDR;
wire [1:0]S_AXI_HP3_AWBURST;
wire [3:0]S_AXI_HP3_AWCACHE;
wire [5:0]S_AXI_HP3_AWID;
wire [3:0]S_AXI_HP3_AWLEN;
wire [1:0]S_AXI_HP3_AWLOCK;
wire [2:0]S_AXI_HP3_AWPROT;
wire [3:0]S_AXI_HP3_AWQOS;
wire S_AXI_HP3_AWREADY;
wire [2:0]S_AXI_HP3_AWSIZE;
wire S_AXI_HP3_AWVALID;
wire [5:0]S_AXI_HP3_BID;
wire S_AXI_HP3_BREADY;
wire [1:0]S_AXI_HP3_BRESP;
wire S_AXI_HP3_BVALID;
wire [2:0]S_AXI_HP3_RACOUNT;
wire [7:0]S_AXI_HP3_RCOUNT;
wire [63:0]S_AXI_HP3_RDATA;
wire S_AXI_HP3_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP3_RID;
wire S_AXI_HP3_RLAST;
wire S_AXI_HP3_RREADY;
wire [1:0]S_AXI_HP3_RRESP;
wire S_AXI_HP3_RVALID;
wire [5:0]S_AXI_HP3_WACOUNT;
wire [7:0]S_AXI_HP3_WCOUNT;
wire [63:0]S_AXI_HP3_WDATA;
wire [5:0]S_AXI_HP3_WID;
wire S_AXI_HP3_WLAST;
wire S_AXI_HP3_WREADY;
wire S_AXI_HP3_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP3_WSTRB;
wire S_AXI_HP3_WVALID;
wire TRACE_CLK;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[0] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[1] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[2] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[3] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[4] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[5] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[6] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[7] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[0] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[1] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[2] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[3] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[4] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[5] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[6] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[7] ;
wire TTC0_CLK0_IN;
wire TTC0_CLK1_IN;
wire TTC0_CLK2_IN;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire TTC1_CLK0_IN;
wire TTC1_CLK1_IN;
wire TTC1_CLK2_IN;
wire TTC1_WAVE0_OUT;
wire TTC1_WAVE1_OUT;
wire TTC1_WAVE2_OUT;
wire UART0_CTSN;
wire UART0_DCDN;
wire UART0_DSRN;
wire UART0_DTRN;
wire UART0_RIN;
wire UART0_RTSN;
wire UART0_RX;
wire UART0_TX;
wire UART1_CTSN;
wire UART1_DCDN;
wire UART1_DSRN;
wire UART1_DTRN;
wire UART1_RIN;
wire UART1_RTSN;
wire UART1_RX;
wire UART1_TX;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire [1:0]USB1_PORT_INDCTL;
wire USB1_VBUS_PWRFAULT;
wire USB1_VBUS_PWRSELECT;
wire WDT_CLK_IN;
wire WDT_RST_OUT;
wire [14:0]buffered_DDR_Addr;
wire [2:0]buffered_DDR_BankAddr;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_CS_n;
wire buffered_DDR_Clk;
wire buffered_DDR_Clk_n;
wire [3:0]buffered_DDR_DM;
wire [31:0]buffered_DDR_DQ;
wire [3:0]buffered_DDR_DQS;
wire [3:0]buffered_DDR_DQS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire buffered_DDR_WEB;
wire [53:0]buffered_MIO;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire buffered_PS_SRSTB;
wire [63:0]gpio_out_t_n;
wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED;
assign ENET0_GMII_TXD[7] = \<const0> ;
assign ENET0_GMII_TXD[6] = \<const0> ;
assign ENET0_GMII_TXD[5] = \<const0> ;
assign ENET0_GMII_TXD[4] = \<const0> ;
assign ENET0_GMII_TXD[3] = \<const0> ;
assign ENET0_GMII_TXD[2] = \<const0> ;
assign ENET0_GMII_TXD[1] = \<const0> ;
assign ENET0_GMII_TXD[0] = \<const0> ;
assign ENET0_GMII_TX_EN = \<const0> ;
assign ENET0_GMII_TX_ER = \<const0> ;
assign ENET1_GMII_TXD[7] = \<const0> ;
assign ENET1_GMII_TXD[6] = \<const0> ;
assign ENET1_GMII_TXD[5] = \<const0> ;
assign ENET1_GMII_TXD[4] = \<const0> ;
assign ENET1_GMII_TXD[3] = \<const0> ;
assign ENET1_GMII_TXD[2] = \<const0> ;
assign ENET1_GMII_TXD[1] = \<const0> ;
assign ENET1_GMII_TXD[0] = \<const0> ;
assign ENET1_GMII_TX_EN = \<const0> ;
assign ENET1_GMII_TX_ER = \<const0> ;
assign M_AXI_GP0_ARCACHE[3:2] = \^M_AXI_GP0_ARCACHE [3:2];
assign M_AXI_GP0_ARCACHE[1] = \<const1> ;
assign M_AXI_GP0_ARCACHE[0] = \^M_AXI_GP0_ARCACHE [0];
assign M_AXI_GP0_ARSIZE[2] = \<const0> ;
assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0];
assign M_AXI_GP0_AWCACHE[3:2] = \^M_AXI_GP0_AWCACHE [3:2];
assign M_AXI_GP0_AWCACHE[1] = \<const1> ;
assign M_AXI_GP0_AWCACHE[0] = \^M_AXI_GP0_AWCACHE [0];
assign M_AXI_GP0_AWSIZE[2] = \<const0> ;
assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0];
assign M_AXI_GP1_ARCACHE[3:2] = \^M_AXI_GP1_ARCACHE [3:2];
assign M_AXI_GP1_ARCACHE[1] = \<const1> ;
assign M_AXI_GP1_ARCACHE[0] = \^M_AXI_GP1_ARCACHE [0];
assign M_AXI_GP1_ARSIZE[2] = \<const0> ;
assign M_AXI_GP1_ARSIZE[1:0] = \^M_AXI_GP1_ARSIZE [1:0];
assign M_AXI_GP1_AWCACHE[3:2] = \^M_AXI_GP1_AWCACHE [3:2];
assign M_AXI_GP1_AWCACHE[1] = \<const1> ;
assign M_AXI_GP1_AWCACHE[0] = \^M_AXI_GP1_AWCACHE [0];
assign M_AXI_GP1_AWSIZE[2] = \<const0> ;
assign M_AXI_GP1_AWSIZE[1:0] = \^M_AXI_GP1_AWSIZE [1:0];
assign PJTAG_TDO = \<const0> ;
assign TRACE_CLK_OUT = \<const0> ;
assign TRACE_CTL = \TRACE_CTL_PIPE[0] ;
assign TRACE_DATA[1:0] = \TRACE_DATA_PIPE[0] ;
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CAS_n_BIBUF
(.IO(buffered_DDR_CAS_n),
.PAD(DDR_CAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CKE_BIBUF
(.IO(buffered_DDR_CKE),
.PAD(DDR_CKE));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CS_n_BIBUF
(.IO(buffered_DDR_CS_n),
.PAD(DDR_CS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_BIBUF
(.IO(buffered_DDR_Clk),
.PAD(DDR_Clk));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_n_BIBUF
(.IO(buffered_DDR_Clk_n),
.PAD(DDR_Clk_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_DRSTB_BIBUF
(.IO(buffered_DDR_DRSTB),
.PAD(DDR_DRSTB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_ODT_BIBUF
(.IO(buffered_DDR_ODT),
.PAD(DDR_ODT));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_RAS_n_BIBUF
(.IO(buffered_DDR_RAS_n),
.PAD(DDR_RAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRN_BIBUF
(.IO(buffered_DDR_VRN),
.PAD(DDR_VRN));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRP_BIBUF
(.IO(buffered_DDR_VRP),
.PAD(DDR_VRP));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_WEB_BIBUF
(.IO(buffered_DDR_WEB),
.PAD(DDR_WEB));
LUT1 #(
.INIT(2'h1))
ENET0_MDIO_T_INST_0
(.I0(ENET0_MDIO_T_n),
.O(ENET0_MDIO_T));
LUT1 #(
.INIT(2'h1))
ENET1_MDIO_T_INST_0
(.I0(ENET1_MDIO_T_n),
.O(ENET1_MDIO_T));
GND GND
(.G(\<const0> ));
LUT1 #(
.INIT(2'h1))
\GPIO_T[0]_INST_0
(.I0(gpio_out_t_n[0]),
.O(GPIO_T[0]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[10]_INST_0
(.I0(gpio_out_t_n[10]),
.O(GPIO_T[10]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[11]_INST_0
(.I0(gpio_out_t_n[11]),
.O(GPIO_T[11]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[12]_INST_0
(.I0(gpio_out_t_n[12]),
.O(GPIO_T[12]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[13]_INST_0
(.I0(gpio_out_t_n[13]),
.O(GPIO_T[13]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[14]_INST_0
(.I0(gpio_out_t_n[14]),
.O(GPIO_T[14]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[15]_INST_0
(.I0(gpio_out_t_n[15]),
.O(GPIO_T[15]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[16]_INST_0
(.I0(gpio_out_t_n[16]),
.O(GPIO_T[16]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[17]_INST_0
(.I0(gpio_out_t_n[17]),
.O(GPIO_T[17]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[18]_INST_0
(.I0(gpio_out_t_n[18]),
.O(GPIO_T[18]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[19]_INST_0
(.I0(gpio_out_t_n[19]),
.O(GPIO_T[19]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[1]_INST_0
(.I0(gpio_out_t_n[1]),
.O(GPIO_T[1]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[20]_INST_0
(.I0(gpio_out_t_n[20]),
.O(GPIO_T[20]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[21]_INST_0
(.I0(gpio_out_t_n[21]),
.O(GPIO_T[21]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[22]_INST_0
(.I0(gpio_out_t_n[22]),
.O(GPIO_T[22]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[23]_INST_0
(.I0(gpio_out_t_n[23]),
.O(GPIO_T[23]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[24]_INST_0
(.I0(gpio_out_t_n[24]),
.O(GPIO_T[24]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[25]_INST_0
(.I0(gpio_out_t_n[25]),
.O(GPIO_T[25]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[26]_INST_0
(.I0(gpio_out_t_n[26]),
.O(GPIO_T[26]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[27]_INST_0
(.I0(gpio_out_t_n[27]),
.O(GPIO_T[27]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[28]_INST_0
(.I0(gpio_out_t_n[28]),
.O(GPIO_T[28]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[29]_INST_0
(.I0(gpio_out_t_n[29]),
.O(GPIO_T[29]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[2]_INST_0
(.I0(gpio_out_t_n[2]),
.O(GPIO_T[2]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[30]_INST_0
(.I0(gpio_out_t_n[30]),
.O(GPIO_T[30]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[31]_INST_0
(.I0(gpio_out_t_n[31]),
.O(GPIO_T[31]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[32]_INST_0
(.I0(gpio_out_t_n[32]),
.O(GPIO_T[32]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[33]_INST_0
(.I0(gpio_out_t_n[33]),
.O(GPIO_T[33]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[34]_INST_0
(.I0(gpio_out_t_n[34]),
.O(GPIO_T[34]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[35]_INST_0
(.I0(gpio_out_t_n[35]),
.O(GPIO_T[35]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[36]_INST_0
(.I0(gpio_out_t_n[36]),
.O(GPIO_T[36]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[37]_INST_0
(.I0(gpio_out_t_n[37]),
.O(GPIO_T[37]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[38]_INST_0
(.I0(gpio_out_t_n[38]),
.O(GPIO_T[38]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[39]_INST_0
(.I0(gpio_out_t_n[39]),
.O(GPIO_T[39]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[3]_INST_0
(.I0(gpio_out_t_n[3]),
.O(GPIO_T[3]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[40]_INST_0
(.I0(gpio_out_t_n[40]),
.O(GPIO_T[40]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[41]_INST_0
(.I0(gpio_out_t_n[41]),
.O(GPIO_T[41]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[42]_INST_0
(.I0(gpio_out_t_n[42]),
.O(GPIO_T[42]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[43]_INST_0
(.I0(gpio_out_t_n[43]),
.O(GPIO_T[43]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[44]_INST_0
(.I0(gpio_out_t_n[44]),
.O(GPIO_T[44]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[45]_INST_0
(.I0(gpio_out_t_n[45]),
.O(GPIO_T[45]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[46]_INST_0
(.I0(gpio_out_t_n[46]),
.O(GPIO_T[46]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[47]_INST_0
(.I0(gpio_out_t_n[47]),
.O(GPIO_T[47]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[48]_INST_0
(.I0(gpio_out_t_n[48]),
.O(GPIO_T[48]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[49]_INST_0
(.I0(gpio_out_t_n[49]),
.O(GPIO_T[49]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[4]_INST_0
(.I0(gpio_out_t_n[4]),
.O(GPIO_T[4]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[50]_INST_0
(.I0(gpio_out_t_n[50]),
.O(GPIO_T[50]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[51]_INST_0
(.I0(gpio_out_t_n[51]),
.O(GPIO_T[51]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[52]_INST_0
(.I0(gpio_out_t_n[52]),
.O(GPIO_T[52]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[53]_INST_0
(.I0(gpio_out_t_n[53]),
.O(GPIO_T[53]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[54]_INST_0
(.I0(gpio_out_t_n[54]),
.O(GPIO_T[54]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[55]_INST_0
(.I0(gpio_out_t_n[55]),
.O(GPIO_T[55]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[56]_INST_0
(.I0(gpio_out_t_n[56]),
.O(GPIO_T[56]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[57]_INST_0
(.I0(gpio_out_t_n[57]),
.O(GPIO_T[57]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[58]_INST_0
(.I0(gpio_out_t_n[58]),
.O(GPIO_T[58]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[59]_INST_0
(.I0(gpio_out_t_n[59]),
.O(GPIO_T[59]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[5]_INST_0
(.I0(gpio_out_t_n[5]),
.O(GPIO_T[5]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[60]_INST_0
(.I0(gpio_out_t_n[60]),
.O(GPIO_T[60]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[61]_INST_0
(.I0(gpio_out_t_n[61]),
.O(GPIO_T[61]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[62]_INST_0
(.I0(gpio_out_t_n[62]),
.O(GPIO_T[62]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[63]_INST_0
(.I0(gpio_out_t_n[63]),
.O(GPIO_T[63]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[6]_INST_0
(.I0(gpio_out_t_n[6]),
.O(GPIO_T[6]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[7]_INST_0
(.I0(gpio_out_t_n[7]),
.O(GPIO_T[7]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[8]_INST_0
(.I0(gpio_out_t_n[8]),
.O(GPIO_T[8]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[9]_INST_0
(.I0(gpio_out_t_n[9]),
.O(GPIO_T[9]));
LUT1 #(
.INIT(2'h1))
I2C0_SCL_T_INST_0
(.I0(I2C0_SCL_T_n),
.O(I2C0_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C0_SDA_T_INST_0
(.I0(I2C0_SDA_T_n),
.O(I2C0_SDA_T));
LUT1 #(
.INIT(2'h1))
I2C1_SCL_T_INST_0
(.I0(I2C1_SCL_T_n),
.O(I2C1_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C1_SDA_T_INST_0
(.I0(I2C1_SDA_T_n),
.O(I2C1_SDA_T));
(* BOX_TYPE = "PRIMITIVE" *)
PS7 PS7_i
(.DDRA(buffered_DDR_Addr),
.DDRARB(DDR_ARB),
.DDRBA(buffered_DDR_BankAddr),
.DDRCASB(buffered_DDR_CAS_n),
.DDRCKE(buffered_DDR_CKE),
.DDRCKN(buffered_DDR_Clk_n),
.DDRCKP(buffered_DDR_Clk),
.DDRCSB(buffered_DDR_CS_n),
.DDRDM(buffered_DDR_DM),
.DDRDQ(buffered_DDR_DQ),
.DDRDQSN(buffered_DDR_DQS_n),
.DDRDQSP(buffered_DDR_DQS),
.DDRDRSTB(buffered_DDR_DRSTB),
.DDRODT(buffered_DDR_ODT),
.DDRRASB(buffered_DDR_RAS_n),
.DDRVRN(buffered_DDR_VRN),
.DDRVRP(buffered_DDR_VRP),
.DDRWEB(buffered_DDR_WEB),
.DMA0ACLK(DMA0_ACLK),
.DMA0DAREADY(DMA0_DAREADY),
.DMA0DATYPE(DMA0_DATYPE),
.DMA0DAVALID(DMA0_DAVALID),
.DMA0DRLAST(DMA0_DRLAST),
.DMA0DRREADY(DMA0_DRREADY),
.DMA0DRTYPE(DMA0_DRTYPE),
.DMA0DRVALID(DMA0_DRVALID),
.DMA0RSTN(DMA0_RSTN),
.DMA1ACLK(DMA1_ACLK),
.DMA1DAREADY(DMA1_DAREADY),
.DMA1DATYPE(DMA1_DATYPE),
.DMA1DAVALID(DMA1_DAVALID),
.DMA1DRLAST(DMA1_DRLAST),
.DMA1DRREADY(DMA1_DRREADY),
.DMA1DRTYPE(DMA1_DRTYPE),
.DMA1DRVALID(DMA1_DRVALID),
.DMA1RSTN(DMA1_RSTN),
.DMA2ACLK(DMA2_ACLK),
.DMA2DAREADY(DMA2_DAREADY),
.DMA2DATYPE(DMA2_DATYPE),
.DMA2DAVALID(DMA2_DAVALID),
.DMA2DRLAST(DMA2_DRLAST),
.DMA2DRREADY(DMA2_DRREADY),
.DMA2DRTYPE(DMA2_DRTYPE),
.DMA2DRVALID(DMA2_DRVALID),
.DMA2RSTN(DMA2_RSTN),
.DMA3ACLK(DMA3_ACLK),
.DMA3DAREADY(DMA3_DAREADY),
.DMA3DATYPE(DMA3_DATYPE),
.DMA3DAVALID(DMA3_DAVALID),
.DMA3DRLAST(DMA3_DRLAST),
.DMA3DRREADY(DMA3_DRREADY),
.DMA3DRTYPE(DMA3_DRTYPE),
.DMA3DRVALID(DMA3_DRVALID),
.DMA3RSTN(DMA3_RSTN),
.EMIOCAN0PHYRX(CAN0_PHY_RX),
.EMIOCAN0PHYTX(CAN0_PHY_TX),
.EMIOCAN1PHYRX(CAN1_PHY_RX),
.EMIOCAN1PHYTX(CAN1_PHY_TX),
.EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
.EMIOENET0GMIICOL(1'b0),
.EMIOENET0GMIICRS(1'b0),
.EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET0GMIIRXDV(1'b0),
.EMIOENET0GMIIRXER(1'b0),
.EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
.EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
.EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
.EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
.EMIOENET0MDIOI(ENET0_MDIO_I),
.EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
.EMIOENET0MDIOO(ENET0_MDIO_O),
.EMIOENET0MDIOTN(ENET0_MDIO_T_n),
.EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX(ENET0_SOF_RX),
.EMIOENET0SOFTX(ENET0_SOF_TX),
.EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
.EMIOENET1GMIICOL(1'b0),
.EMIOENET1GMIICRS(1'b0),
.EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET1GMIIRXDV(1'b0),
.EMIOENET1GMIIRXER(1'b0),
.EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
.EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
.EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
.EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
.EMIOENET1MDIOI(ENET1_MDIO_I),
.EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
.EMIOENET1MDIOO(ENET1_MDIO_O),
.EMIOENET1MDIOTN(ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX(ENET1_SOF_RX),
.EMIOENET1SOFTX(ENET1_SOF_TX),
.EMIOGPIOI(GPIO_I),
.EMIOGPIOO(GPIO_O),
.EMIOGPIOTN(gpio_out_t_n),
.EMIOI2C0SCLI(I2C0_SCL_I),
.EMIOI2C0SCLO(I2C0_SCL_O),
.EMIOI2C0SCLTN(I2C0_SCL_T_n),
.EMIOI2C0SDAI(I2C0_SDA_I),
.EMIOI2C0SDAO(I2C0_SDA_O),
.EMIOI2C0SDATN(I2C0_SDA_T_n),
.EMIOI2C1SCLI(I2C1_SCL_I),
.EMIOI2C1SCLO(I2C1_SCL_O),
.EMIOI2C1SCLTN(I2C1_SCL_T_n),
.EMIOI2C1SDAI(I2C1_SDA_I),
.EMIOI2C1SDAO(I2C1_SDA_O),
.EMIOI2C1SDATN(I2C1_SDA_T_n),
.EMIOPJTAGTCK(PJTAG_TCK),
.EMIOPJTAGTDI(PJTAG_TDI),
.EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
.EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
.EMIOPJTAGTMS(PJTAG_TMS),
.EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
.EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
.EMIOSDIO0CDN(SDIO0_CDN),
.EMIOSDIO0CLK(SDIO0_CLK),
.EMIOSDIO0CLKFB(SDIO0_CLK_FB),
.EMIOSDIO0CMDI(SDIO0_CMD_I),
.EMIOSDIO0CMDO(SDIO0_CMD_O),
.EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
.EMIOSDIO0DATAI(SDIO0_DATA_I),
.EMIOSDIO0DATAO(SDIO0_DATA_O),
.EMIOSDIO0DATATN(SDIO0_DATA_T_n),
.EMIOSDIO0LED(SDIO0_LED),
.EMIOSDIO0WP(SDIO0_WP),
.EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
.EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
.EMIOSDIO1CDN(SDIO1_CDN),
.EMIOSDIO1CLK(SDIO1_CLK),
.EMIOSDIO1CLKFB(SDIO1_CLK_FB),
.EMIOSDIO1CMDI(SDIO1_CMD_I),
.EMIOSDIO1CMDO(SDIO1_CMD_O),
.EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
.EMIOSDIO1DATAI(SDIO1_DATA_I),
.EMIOSDIO1DATAO(SDIO1_DATA_O),
.EMIOSDIO1DATATN(SDIO1_DATA_T_n),
.EMIOSDIO1LED(SDIO1_LED),
.EMIOSDIO1WP(SDIO1_WP),
.EMIOSPI0MI(SPI0_MISO_I),
.EMIOSPI0MO(SPI0_MOSI_O),
.EMIOSPI0MOTN(SPI0_MOSI_T_n),
.EMIOSPI0SCLKI(SPI0_SCLK_I),
.EMIOSPI0SCLKO(SPI0_SCLK_O),
.EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
.EMIOSPI0SI(SPI0_MOSI_I),
.EMIOSPI0SO(SPI0_MISO_O),
.EMIOSPI0SSIN(SPI0_SS_I),
.EMIOSPI0SSNTN(SPI0_SS_T_n),
.EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0STN(SPI0_MISO_T_n),
.EMIOSPI1MI(SPI1_MISO_I),
.EMIOSPI1MO(SPI1_MOSI_O),
.EMIOSPI1MOTN(SPI1_MOSI_T_n),
.EMIOSPI1SCLKI(SPI1_SCLK_I),
.EMIOSPI1SCLKO(SPI1_SCLK_O),
.EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
.EMIOSPI1SI(SPI1_MOSI_I),
.EMIOSPI1SO(SPI1_MISO_O),
.EMIOSPI1SSIN(SPI1_SS_I),
.EMIOSPI1SSNTN(SPI1_SS_T_n),
.EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1STN(SPI1_MISO_T_n),
.EMIOSRAMINTIN(SRAM_INTIN),
.EMIOTRACECLK(TRACE_CLK),
.EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
.EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
.EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
.EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
.EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0CTSN(UART0_CTSN),
.EMIOUART0DCDN(UART0_DCDN),
.EMIOUART0DSRN(UART0_DSRN),
.EMIOUART0DTRN(UART0_DTRN),
.EMIOUART0RIN(UART0_RIN),
.EMIOUART0RTSN(UART0_RTSN),
.EMIOUART0RX(UART0_RX),
.EMIOUART0TX(UART0_TX),
.EMIOUART1CTSN(UART1_CTSN),
.EMIOUART1DCDN(UART1_DCDN),
.EMIOUART1DSRN(UART1_DSRN),
.EMIOUART1DTRN(UART1_DTRN),
.EMIOUART1RIN(UART1_RIN),
.EMIOUART1RTSN(UART1_RTSN),
.EMIOUART1RX(UART1_RX),
.EMIOUART1TX(UART1_TX),
.EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
.EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
.EMIOWDTCLKI(WDT_CLK_IN),
.EMIOWDTRSTO(WDT_RST_OUT),
.EVENTEVENTI(EVENT_EVENTI),
.EVENTEVENTO(EVENT_EVENTO),
.EVENTSTANDBYWFE(EVENT_STANDBYWFE),
.EVENTSTANDBYWFI(EVENT_STANDBYWFI),
.FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}),
.FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}),
.FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.FPGAIDLEN(FPGA_IDLE_N),
.FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINVALID(1'b0),
.FTMTF2PDEBUG(FTMT_F2P_DEBUG),
.FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG(FTMT_P2F_DEBUG),
.FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}),
.IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
.MAXIGP0ACLK(M_AXI_GP0_ACLK),
.MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE(\^M_AXI_GP0_ARCACHE ),
.MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
.MAXIGP0ARID(M_AXI_GP0_ARID),
.MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
.MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
.MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
.MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
.MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
.MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ),
.MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
.MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE(\^M_AXI_GP0_AWCACHE ),
.MAXIGP0AWID(M_AXI_GP0_AWID),
.MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
.MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
.MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
.MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
.MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
.MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ),
.MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
.MAXIGP0BID(M_AXI_GP0_BID),
.MAXIGP0BREADY(M_AXI_GP0_BREADY),
.MAXIGP0BRESP(M_AXI_GP0_BRESP),
.MAXIGP0BVALID(M_AXI_GP0_BVALID),
.MAXIGP0RDATA(M_AXI_GP0_RDATA),
.MAXIGP0RID(M_AXI_GP0_RID),
.MAXIGP0RLAST(M_AXI_GP0_RLAST),
.MAXIGP0RREADY(M_AXI_GP0_RREADY),
.MAXIGP0RRESP(M_AXI_GP0_RRESP),
.MAXIGP0RVALID(M_AXI_GP0_RVALID),
.MAXIGP0WDATA(M_AXI_GP0_WDATA),
.MAXIGP0WID(M_AXI_GP0_WID),
.MAXIGP0WLAST(M_AXI_GP0_WLAST),
.MAXIGP0WREADY(M_AXI_GP0_WREADY),
.MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
.MAXIGP0WVALID(M_AXI_GP0_WVALID),
.MAXIGP1ACLK(M_AXI_GP1_ACLK),
.MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
.MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE(\^M_AXI_GP1_ARCACHE ),
.MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
.MAXIGP1ARID(M_AXI_GP1_ARID),
.MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
.MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
.MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
.MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
.MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
.MAXIGP1ARSIZE(\^M_AXI_GP1_ARSIZE ),
.MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
.MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE(\^M_AXI_GP1_AWCACHE ),
.MAXIGP1AWID(M_AXI_GP1_AWID),
.MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
.MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
.MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
.MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
.MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
.MAXIGP1AWSIZE(\^M_AXI_GP1_AWSIZE ),
.MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
.MAXIGP1BID(M_AXI_GP1_BID),
.MAXIGP1BREADY(M_AXI_GP1_BREADY),
.MAXIGP1BRESP(M_AXI_GP1_BRESP),
.MAXIGP1BVALID(M_AXI_GP1_BVALID),
.MAXIGP1RDATA(M_AXI_GP1_RDATA),
.MAXIGP1RID(M_AXI_GP1_RID),
.MAXIGP1RLAST(M_AXI_GP1_RLAST),
.MAXIGP1RREADY(M_AXI_GP1_RREADY),
.MAXIGP1RRESP(M_AXI_GP1_RRESP),
.MAXIGP1RVALID(M_AXI_GP1_RVALID),
.MAXIGP1WDATA(M_AXI_GP1_WDATA),
.MAXIGP1WID(M_AXI_GP1_WID),
.MAXIGP1WLAST(M_AXI_GP1_WLAST),
.MAXIGP1WREADY(M_AXI_GP1_WREADY),
.MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
.MAXIGP1WVALID(M_AXI_GP1_WVALID),
.MIO(buffered_MIO),
.PSCLK(buffered_PS_CLK),
.PSPORB(buffered_PS_PORB),
.PSSRSTB(buffered_PS_SRSTB),
.SAXIACPACLK(S_AXI_ACP_ACLK),
.SAXIACPARADDR(S_AXI_ACP_ARADDR),
.SAXIACPARBURST(S_AXI_ACP_ARBURST),
.SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
.SAXIACPARESETN(S_AXI_ACP_ARESETN),
.SAXIACPARID(S_AXI_ACP_ARID),
.SAXIACPARLEN(S_AXI_ACP_ARLEN),
.SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
.SAXIACPARPROT(S_AXI_ACP_ARPROT),
.SAXIACPARQOS(S_AXI_ACP_ARQOS),
.SAXIACPARREADY(S_AXI_ACP_ARREADY),
.SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
.SAXIACPARUSER(S_AXI_ACP_ARUSER),
.SAXIACPARVALID(S_AXI_ACP_ARVALID),
.SAXIACPAWADDR(S_AXI_ACP_AWADDR),
.SAXIACPAWBURST(S_AXI_ACP_AWBURST),
.SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
.SAXIACPAWID(S_AXI_ACP_AWID),
.SAXIACPAWLEN(S_AXI_ACP_AWLEN),
.SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
.SAXIACPAWPROT(S_AXI_ACP_AWPROT),
.SAXIACPAWQOS(S_AXI_ACP_AWQOS),
.SAXIACPAWREADY(S_AXI_ACP_AWREADY),
.SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
.SAXIACPAWUSER(S_AXI_ACP_AWUSER),
.SAXIACPAWVALID(S_AXI_ACP_AWVALID),
.SAXIACPBID(S_AXI_ACP_BID),
.SAXIACPBREADY(S_AXI_ACP_BREADY),
.SAXIACPBRESP(S_AXI_ACP_BRESP),
.SAXIACPBVALID(S_AXI_ACP_BVALID),
.SAXIACPRDATA(S_AXI_ACP_RDATA),
.SAXIACPRID(S_AXI_ACP_RID),
.SAXIACPRLAST(S_AXI_ACP_RLAST),
.SAXIACPRREADY(S_AXI_ACP_RREADY),
.SAXIACPRRESP(S_AXI_ACP_RRESP),
.SAXIACPRVALID(S_AXI_ACP_RVALID),
.SAXIACPWDATA(S_AXI_ACP_WDATA),
.SAXIACPWID(S_AXI_ACP_WID),
.SAXIACPWLAST(S_AXI_ACP_WLAST),
.SAXIACPWREADY(S_AXI_ACP_WREADY),
.SAXIACPWSTRB(S_AXI_ACP_WSTRB),
.SAXIACPWVALID(S_AXI_ACP_WVALID),
.SAXIGP0ACLK(S_AXI_GP0_ACLK),
.SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
.SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
.SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
.SAXIGP0ARID(S_AXI_GP0_ARID),
.SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
.SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
.SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
.SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
.SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
.SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
.SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
.SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
.SAXIGP0AWID(S_AXI_GP0_AWID),
.SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
.SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
.SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
.SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
.SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
.SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
.SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
.SAXIGP0BID(S_AXI_GP0_BID),
.SAXIGP0BREADY(S_AXI_GP0_BREADY),
.SAXIGP0BRESP(S_AXI_GP0_BRESP),
.SAXIGP0BVALID(S_AXI_GP0_BVALID),
.SAXIGP0RDATA(S_AXI_GP0_RDATA),
.SAXIGP0RID(S_AXI_GP0_RID),
.SAXIGP0RLAST(S_AXI_GP0_RLAST),
.SAXIGP0RREADY(S_AXI_GP0_RREADY),
.SAXIGP0RRESP(S_AXI_GP0_RRESP),
.SAXIGP0RVALID(S_AXI_GP0_RVALID),
.SAXIGP0WDATA(S_AXI_GP0_WDATA),
.SAXIGP0WID(S_AXI_GP0_WID),
.SAXIGP0WLAST(S_AXI_GP0_WLAST),
.SAXIGP0WREADY(S_AXI_GP0_WREADY),
.SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
.SAXIGP0WVALID(S_AXI_GP0_WVALID),
.SAXIGP1ACLK(S_AXI_GP1_ACLK),
.SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
.SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
.SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
.SAXIGP1ARID(S_AXI_GP1_ARID),
.SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
.SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
.SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
.SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
.SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
.SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
.SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
.SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
.SAXIGP1AWID(S_AXI_GP1_AWID),
.SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
.SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
.SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
.SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
.SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
.SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
.SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
.SAXIGP1BID(S_AXI_GP1_BID),
.SAXIGP1BREADY(S_AXI_GP1_BREADY),
.SAXIGP1BRESP(S_AXI_GP1_BRESP),
.SAXIGP1BVALID(S_AXI_GP1_BVALID),
.SAXIGP1RDATA(S_AXI_GP1_RDATA),
.SAXIGP1RID(S_AXI_GP1_RID),
.SAXIGP1RLAST(S_AXI_GP1_RLAST),
.SAXIGP1RREADY(S_AXI_GP1_RREADY),
.SAXIGP1RRESP(S_AXI_GP1_RRESP),
.SAXIGP1RVALID(S_AXI_GP1_RVALID),
.SAXIGP1WDATA(S_AXI_GP1_WDATA),
.SAXIGP1WID(S_AXI_GP1_WID),
.SAXIGP1WLAST(S_AXI_GP1_WLAST),
.SAXIGP1WREADY(S_AXI_GP1_WREADY),
.SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
.SAXIGP1WVALID(S_AXI_GP1_WVALID),
.SAXIHP0ACLK(S_AXI_HP0_ACLK),
.SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
.SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
.SAXIHP0ARID(S_AXI_HP0_ARID),
.SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
.SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
.SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
.SAXIHP0AWID(S_AXI_HP0_AWID),
.SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
.SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
.SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
.SAXIHP0BID(S_AXI_HP0_BID),
.SAXIHP0BREADY(S_AXI_HP0_BREADY),
.SAXIHP0BRESP(S_AXI_HP0_BRESP),
.SAXIHP0BVALID(S_AXI_HP0_BVALID),
.SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA(S_AXI_HP0_RDATA),
.SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RID(S_AXI_HP0_RID),
.SAXIHP0RLAST(S_AXI_HP0_RLAST),
.SAXIHP0RREADY(S_AXI_HP0_RREADY),
.SAXIHP0RRESP(S_AXI_HP0_RRESP),
.SAXIHP0RVALID(S_AXI_HP0_RVALID),
.SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
.SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
.SAXIHP0WDATA(S_AXI_HP0_WDATA),
.SAXIHP0WID(S_AXI_HP0_WID),
.SAXIHP0WLAST(S_AXI_HP0_WLAST),
.SAXIHP0WREADY(S_AXI_HP0_WREADY),
.SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
.SAXIHP0WVALID(S_AXI_HP0_WVALID),
.SAXIHP1ACLK(S_AXI_HP1_ACLK),
.SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
.SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
.SAXIHP1ARID(S_AXI_HP1_ARID),
.SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
.SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
.SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
.SAXIHP1AWID(S_AXI_HP1_AWID),
.SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
.SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
.SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
.SAXIHP1BID(S_AXI_HP1_BID),
.SAXIHP1BREADY(S_AXI_HP1_BREADY),
.SAXIHP1BRESP(S_AXI_HP1_BRESP),
.SAXIHP1BVALID(S_AXI_HP1_BVALID),
.SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
.SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
.SAXIHP1RDATA(S_AXI_HP1_RDATA),
.SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RID(S_AXI_HP1_RID),
.SAXIHP1RLAST(S_AXI_HP1_RLAST),
.SAXIHP1RREADY(S_AXI_HP1_RREADY),
.SAXIHP1RRESP(S_AXI_HP1_RRESP),
.SAXIHP1RVALID(S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
.SAXIHP1WDATA(S_AXI_HP1_WDATA),
.SAXIHP1WID(S_AXI_HP1_WID),
.SAXIHP1WLAST(S_AXI_HP1_WLAST),
.SAXIHP1WREADY(S_AXI_HP1_WREADY),
.SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
.SAXIHP1WVALID(S_AXI_HP1_WVALID),
.SAXIHP2ACLK(S_AXI_HP2_ACLK),
.SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
.SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
.SAXIHP2ARID(S_AXI_HP2_ARID),
.SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
.SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
.SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
.SAXIHP2AWID(S_AXI_HP2_AWID),
.SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
.SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
.SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
.SAXIHP2BID(S_AXI_HP2_BID),
.SAXIHP2BREADY(S_AXI_HP2_BREADY),
.SAXIHP2BRESP(S_AXI_HP2_BRESP),
.SAXIHP2BVALID(S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA(S_AXI_HP2_RDATA),
.SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RID(S_AXI_HP2_RID),
.SAXIHP2RLAST(S_AXI_HP2_RLAST),
.SAXIHP2RREADY(S_AXI_HP2_RREADY),
.SAXIHP2RRESP(S_AXI_HP2_RRESP),
.SAXIHP2RVALID(S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
.SAXIHP2WDATA(S_AXI_HP2_WDATA),
.SAXIHP2WID(S_AXI_HP2_WID),
.SAXIHP2WLAST(S_AXI_HP2_WLAST),
.SAXIHP2WREADY(S_AXI_HP2_WREADY),
.SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
.SAXIHP2WVALID(S_AXI_HP2_WVALID),
.SAXIHP3ACLK(S_AXI_HP3_ACLK),
.SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
.SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
.SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
.SAXIHP3ARID(S_AXI_HP3_ARID),
.SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
.SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
.SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
.SAXIHP3AWID(S_AXI_HP3_AWID),
.SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
.SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
.SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
.SAXIHP3BID(S_AXI_HP3_BID),
.SAXIHP3BREADY(S_AXI_HP3_BREADY),
.SAXIHP3BRESP(S_AXI_HP3_BRESP),
.SAXIHP3BVALID(S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA(S_AXI_HP3_RDATA),
.SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RID(S_AXI_HP3_RID),
.SAXIHP3RLAST(S_AXI_HP3_RLAST),
.SAXIHP3RREADY(S_AXI_HP3_RREADY),
.SAXIHP3RRESP(S_AXI_HP3_RRESP),
.SAXIHP3RVALID(S_AXI_HP3_RVALID),
.SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
.SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
.SAXIHP3WDATA(S_AXI_HP3_WDATA),
.SAXIHP3WID(S_AXI_HP3_WID),
.SAXIHP3WLAST(S_AXI_HP3_WLAST),
.SAXIHP3WREADY(S_AXI_HP3_WREADY),
.SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
.SAXIHP3WVALID(S_AXI_HP3_WVALID));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_CLK_BIBUF
(.IO(buffered_PS_CLK),
.PAD(PS_CLK));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_PORB_BIBUF
(.IO(buffered_PS_PORB),
.PAD(PS_PORB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_SRSTB_BIBUF
(.IO(buffered_PS_SRSTB),
.PAD(PS_SRSTB));
LUT1 #(
.INIT(2'h1))
SDIO0_CMD_T_INST_0
(.I0(SDIO0_CMD_T_n),
.O(SDIO0_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[0]_INST_0
(.I0(SDIO0_DATA_T_n[0]),
.O(SDIO0_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[1]_INST_0
(.I0(SDIO0_DATA_T_n[1]),
.O(SDIO0_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[2]_INST_0
(.I0(SDIO0_DATA_T_n[2]),
.O(SDIO0_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[3]_INST_0
(.I0(SDIO0_DATA_T_n[3]),
.O(SDIO0_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SDIO1_CMD_T_INST_0
(.I0(SDIO1_CMD_T_n),
.O(SDIO1_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[0]_INST_0
(.I0(SDIO1_DATA_T_n[0]),
.O(SDIO1_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[1]_INST_0
(.I0(SDIO1_DATA_T_n[1]),
.O(SDIO1_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[2]_INST_0
(.I0(SDIO1_DATA_T_n[2]),
.O(SDIO1_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[3]_INST_0
(.I0(SDIO1_DATA_T_n[3]),
.O(SDIO1_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SPI0_MISO_T_INST_0
(.I0(SPI0_MISO_T_n),
.O(SPI0_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI0_MOSI_T_INST_0
(.I0(SPI0_MOSI_T_n),
.O(SPI0_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI0_SCLK_T_INST_0
(.I0(SPI0_SCLK_T_n),
.O(SPI0_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI0_SS_T_INST_0
(.I0(SPI0_SS_T_n),
.O(SPI0_SS_T));
LUT1 #(
.INIT(2'h1))
SPI1_MISO_T_INST_0
(.I0(SPI1_MISO_T_n),
.O(SPI1_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI1_MOSI_T_INST_0
(.I0(SPI1_MOSI_T_n),
.O(SPI1_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI1_SCLK_T_INST_0
(.I0(SPI1_SCLK_T_n),
.O(SPI1_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI1_SS_T_INST_0
(.I0(SPI1_SS_T_n),
.O(SPI1_SS_T));
VCC VCC
(.P(\<const1> ));
(* BOX_TYPE = "PRIMITIVE" *)
BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG
(.I(FCLK_CLK_unbuffered),
.O(FCLK_CLK0));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[0].MIO_BIBUF
(.IO(buffered_MIO[0]),
.PAD(MIO[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[10].MIO_BIBUF
(.IO(buffered_MIO[10]),
.PAD(MIO[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[11].MIO_BIBUF
(.IO(buffered_MIO[11]),
.PAD(MIO[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[12].MIO_BIBUF
(.IO(buffered_MIO[12]),
.PAD(MIO[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[13].MIO_BIBUF
(.IO(buffered_MIO[13]),
.PAD(MIO[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[14].MIO_BIBUF
(.IO(buffered_MIO[14]),
.PAD(MIO[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[15].MIO_BIBUF
(.IO(buffered_MIO[15]),
.PAD(MIO[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[16].MIO_BIBUF
(.IO(buffered_MIO[16]),
.PAD(MIO[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[17].MIO_BIBUF
(.IO(buffered_MIO[17]),
.PAD(MIO[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[18].MIO_BIBUF
(.IO(buffered_MIO[18]),
.PAD(MIO[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[19].MIO_BIBUF
(.IO(buffered_MIO[19]),
.PAD(MIO[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[1].MIO_BIBUF
(.IO(buffered_MIO[1]),
.PAD(MIO[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[20].MIO_BIBUF
(.IO(buffered_MIO[20]),
.PAD(MIO[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[21].MIO_BIBUF
(.IO(buffered_MIO[21]),
.PAD(MIO[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[22].MIO_BIBUF
(.IO(buffered_MIO[22]),
.PAD(MIO[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[23].MIO_BIBUF
(.IO(buffered_MIO[23]),
.PAD(MIO[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[24].MIO_BIBUF
(.IO(buffered_MIO[24]),
.PAD(MIO[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[25].MIO_BIBUF
(.IO(buffered_MIO[25]),
.PAD(MIO[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[26].MIO_BIBUF
(.IO(buffered_MIO[26]),
.PAD(MIO[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[27].MIO_BIBUF
(.IO(buffered_MIO[27]),
.PAD(MIO[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[28].MIO_BIBUF
(.IO(buffered_MIO[28]),
.PAD(MIO[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[29].MIO_BIBUF
(.IO(buffered_MIO[29]),
.PAD(MIO[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[2].MIO_BIBUF
(.IO(buffered_MIO[2]),
.PAD(MIO[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[30].MIO_BIBUF
(.IO(buffered_MIO[30]),
.PAD(MIO[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[31].MIO_BIBUF
(.IO(buffered_MIO[31]),
.PAD(MIO[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[32].MIO_BIBUF
(.IO(buffered_MIO[32]),
.PAD(MIO[32]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[33].MIO_BIBUF
(.IO(buffered_MIO[33]),
.PAD(MIO[33]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[34].MIO_BIBUF
(.IO(buffered_MIO[34]),
.PAD(MIO[34]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[35].MIO_BIBUF
(.IO(buffered_MIO[35]),
.PAD(MIO[35]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[36].MIO_BIBUF
(.IO(buffered_MIO[36]),
.PAD(MIO[36]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[37].MIO_BIBUF
(.IO(buffered_MIO[37]),
.PAD(MIO[37]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[38].MIO_BIBUF
(.IO(buffered_MIO[38]),
.PAD(MIO[38]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[39].MIO_BIBUF
(.IO(buffered_MIO[39]),
.PAD(MIO[39]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[3].MIO_BIBUF
(.IO(buffered_MIO[3]),
.PAD(MIO[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[40].MIO_BIBUF
(.IO(buffered_MIO[40]),
.PAD(MIO[40]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[41].MIO_BIBUF
(.IO(buffered_MIO[41]),
.PAD(MIO[41]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[42].MIO_BIBUF
(.IO(buffered_MIO[42]),
.PAD(MIO[42]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[43].MIO_BIBUF
(.IO(buffered_MIO[43]),
.PAD(MIO[43]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[44].MIO_BIBUF
(.IO(buffered_MIO[44]),
.PAD(MIO[44]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[45].MIO_BIBUF
(.IO(buffered_MIO[45]),
.PAD(MIO[45]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[46].MIO_BIBUF
(.IO(buffered_MIO[46]),
.PAD(MIO[46]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[47].MIO_BIBUF
(.IO(buffered_MIO[47]),
.PAD(MIO[47]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[48].MIO_BIBUF
(.IO(buffered_MIO[48]),
.PAD(MIO[48]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[49].MIO_BIBUF
(.IO(buffered_MIO[49]),
.PAD(MIO[49]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[4].MIO_BIBUF
(.IO(buffered_MIO[4]),
.PAD(MIO[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[50].MIO_BIBUF
(.IO(buffered_MIO[50]),
.PAD(MIO[50]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[51].MIO_BIBUF
(.IO(buffered_MIO[51]),
.PAD(MIO[51]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[52].MIO_BIBUF
(.IO(buffered_MIO[52]),
.PAD(MIO[52]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[53].MIO_BIBUF
(.IO(buffered_MIO[53]),
.PAD(MIO[53]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[5].MIO_BIBUF
(.IO(buffered_MIO[5]),
.PAD(MIO[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[6].MIO_BIBUF
(.IO(buffered_MIO[6]),
.PAD(MIO[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[7].MIO_BIBUF
(.IO(buffered_MIO[7]),
.PAD(MIO[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[8].MIO_BIBUF
(.IO(buffered_MIO[8]),
.PAD(MIO[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[9].MIO_BIBUF
(.IO(buffered_MIO[9]),
.PAD(MIO[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[0].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[0]),
.PAD(DDR_BankAddr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[1].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[1]),
.PAD(DDR_BankAddr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[2].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[2]),
.PAD(DDR_BankAddr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[0].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[0]),
.PAD(DDR_Addr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[10].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[10]),
.PAD(DDR_Addr[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[11].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[11]),
.PAD(DDR_Addr[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[12].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[12]),
.PAD(DDR_Addr[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[13].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[13]),
.PAD(DDR_Addr[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[14].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[14]),
.PAD(DDR_Addr[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[1].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[1]),
.PAD(DDR_Addr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[2].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[2]),
.PAD(DDR_Addr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[3].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[3]),
.PAD(DDR_Addr[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[4].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[4]),
.PAD(DDR_Addr[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[5].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[5]),
.PAD(DDR_Addr[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[6].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[6]),
.PAD(DDR_Addr[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[7].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[7]),
.PAD(DDR_Addr[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[8].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[8]),
.PAD(DDR_Addr[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[9].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[9]),
.PAD(DDR_Addr[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[0].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[0]),
.PAD(DDR_DM[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[1].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[1]),
.PAD(DDR_DM[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[2].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[2]),
.PAD(DDR_DM[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[3].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[3]),
.PAD(DDR_DM[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[0].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[0]),
.PAD(DDR_DQ[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[10].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[10]),
.PAD(DDR_DQ[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[11].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[11]),
.PAD(DDR_DQ[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[12].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[12]),
.PAD(DDR_DQ[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[13].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[13]),
.PAD(DDR_DQ[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[14].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[14]),
.PAD(DDR_DQ[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[15].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[15]),
.PAD(DDR_DQ[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[16].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[16]),
.PAD(DDR_DQ[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[17].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[17]),
.PAD(DDR_DQ[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[18].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[18]),
.PAD(DDR_DQ[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[19].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[19]),
.PAD(DDR_DQ[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[1].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[1]),
.PAD(DDR_DQ[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[20].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[20]),
.PAD(DDR_DQ[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[21].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[21]),
.PAD(DDR_DQ[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[22].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[22]),
.PAD(DDR_DQ[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[23].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[23]),
.PAD(DDR_DQ[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[24].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[24]),
.PAD(DDR_DQ[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[25].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[25]),
.PAD(DDR_DQ[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[26].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[26]),
.PAD(DDR_DQ[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[27].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[27]),
.PAD(DDR_DQ[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[28].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[28]),
.PAD(DDR_DQ[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[29].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[29]),
.PAD(DDR_DQ[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[2].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[2]),
.PAD(DDR_DQ[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[30].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[30]),
.PAD(DDR_DQ[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[31].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[31]),
.PAD(DDR_DQ[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[3].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[3]),
.PAD(DDR_DQ[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[4].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[4]),
.PAD(DDR_DQ[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[5].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[5]),
.PAD(DDR_DQ[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[6].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[6]),
.PAD(DDR_DQ[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[7].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[7]),
.PAD(DDR_DQ[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[8].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[8]),
.PAD(DDR_DQ[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[9].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[9]),
.PAD(DDR_DQ[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[0].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[0]),
.PAD(DDR_DQS_n[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[1].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[1]),
.PAD(DDR_DQS_n[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[2].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[2]),
.PAD(DDR_DQS_n[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[3].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[3]),
.PAD(DDR_DQS_n[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[0].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[0]),
.PAD(DDR_DQS[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[1].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[1]),
.PAD(DDR_DQS[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[2].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[2]),
.PAD(DDR_DQS[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[3].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[3]),
.PAD(DDR_DQS[3]));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[0] ));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [1]));
LUT1 #(
.INIT(2'h2))
i_10
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [1]));
LUT1 #(
.INIT(2'h2))
i_11
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [0]));
LUT1 #(
.INIT(2'h2))
i_12
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [1]));
LUT1 #(
.INIT(2'h2))
i_13
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [0]));
LUT1 #(
.INIT(2'h2))
i_14
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [1]));
LUT1 #(
.INIT(2'h2))
i_15
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [0]));
LUT1 #(
.INIT(2'h2))
i_16
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [1]));
LUT1 #(
.INIT(2'h2))
i_17
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [0]));
LUT1 #(
.INIT(2'h2))
i_18
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [1]));
LUT1 #(
.INIT(2'h2))
i_19
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [0]));
LUT1 #(
.INIT(2'h2))
i_2
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [0]));
LUT1 #(
.INIT(2'h2))
i_20
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [1]));
LUT1 #(
.INIT(2'h2))
i_21
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [0]));
LUT1 #(
.INIT(2'h2))
i_22
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [1]));
LUT1 #(
.INIT(2'h2))
i_23
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [0]));
LUT1 #(
.INIT(2'h2))
i_3
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[7] ));
LUT1 #(
.INIT(2'h2))
i_4
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[6] ));
LUT1 #(
.INIT(2'h2))
i_5
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[5] ));
LUT1 #(
.INIT(2'h2))
i_6
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[4] ));
LUT1 #(
.INIT(2'h2))
i_7
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[3] ));
LUT1 #(
.INIT(2'h2))
i_8
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[2] ));
LUT1 #(
.INIT(2'h2))
i_9
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[1] ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Copyright (c) 2015, Arch Laboratory
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
module io_bus
(
input wire clk_sys,
input wire rst,
// input ao486_avalon_io
input wire [15:0] ao486_avalon_io_address,
output wire ao486_avalon_io_waitrequest,
input wire [3:0] ao486_avalon_io_byteenable,
input wire ao486_avalon_io_read,
output wire [31:0] ao486_avalon_io_readdata,
output wire ao486_avalon_io_readdatavalid,
input wire ao486_avalon_io_write,
input wire [31:0] ao486_avalon_io_writedata,
// output vga_io_b, address: 0x3b0~0x3bf
output wire [3:0] vga_io_b_address,
output wire vga_io_b_write,
output wire [7:0] vga_io_b_writedata,
output wire vga_io_b_read,
input wire [7:0] vga_io_b_readdata,
// output vga_io_c, address: 0x3c0~0x3cf
output wire [3:0] vga_io_c_address,
output wire vga_io_c_write,
output wire [7:0] vga_io_c_writedata,
output wire vga_io_c_read,
input wire [7:0] vga_io_c_readdata,
// output vga_io_d, address: 0x3d0~0x3df
output wire [3:0] vga_io_d_address,
output wire vga_io_d_write,
output wire [7:0] vga_io_d_writedata,
output wire vga_io_d_read,
input wire [7:0] vga_io_d_readdata,
// output ps2_io, address: 0x60~0x67
output wire [2:0] ps2_io_address,
output wire ps2_io_write,
output wire [7:0] ps2_io_writedata,
output wire ps2_io_read,
input wire [7:0] ps2_io_readdata,
// output ps2_sysctl, address: 0x90~0x9f
output wire [3:0] ps2_sysctl_address,
output wire ps2_sysctl_write,
output wire [7:0] ps2_sysctl_writedata,
output wire ps2_sysctl_read,
input wire [7:0] ps2_sysctl_readdata,
// output pit_io, address: 0x40~0x43
output wire [1:0] pit_io_address,
output wire pit_io_write,
output wire [7:0] pit_io_writedata,
output wire pit_io_read,
input wire [7:0] pit_io_readdata,
// output rtc_io, address: 0x70~0x71
output wire rtc_io_address,
output wire rtc_io_write,
output wire [7:0] rtc_io_writedata,
output wire rtc_io_read,
input wire [7:0] rtc_io_readdata,
// output pic_master, address: 0x20~0x21
output wire pic_master_address,
output wire pic_master_write,
output wire [7:0] pic_master_writedata,
output wire pic_master_read,
input wire [7:0] pic_master_readdata,
// output pic_slave, address: 0xa0~0xa1
output wire pic_slave_address,
output wire pic_slave_write,
output wire [7:0] pic_slave_writedata,
output wire pic_slave_read,
input wire [7:0] pic_slave_readdata,
// output hdd_io, address: 0x1f0, 0x1f4
output wire hdd_io_address,
output wire hdd_io_write,
output wire [31:0] hdd_io_writedata,
output wire hdd_io_read,
input wire [31:0] hdd_io_readdata,
output wire [3:0] hdd_io_byteenable,
// output ide_3f6, address: 0x3f6
output wire ide_3f6_write,
output wire [7:0] ide_3f6_writedata,
output wire ide_3f6_read,
input wire [7:0] ide_3f6_readdata
);
function [1:0] count_bit;
input [3:0] data;
integer i;
begin
count_bit = 0;
for(i = 0; i <= 3; i = i + 1) begin
if(data[i])
count_bit = count_bit + 1;
end
end
endfunction
//------------------------------------------------------------------------------------
//------------------ ao486 --------------------------------------------------------
//------------------------------------------------------------------------------------
reg vga_io_b_readdatavalid;
always @(posedge clk_sys) vga_io_b_readdatavalid <= vga_io_b_read;
reg vga_io_c_readdatavalid;
always @(posedge clk_sys) vga_io_c_readdatavalid <= vga_io_c_read;
reg vga_io_d_readdatavalid;
always @(posedge clk_sys) vga_io_d_readdatavalid <= vga_io_d_read;
reg ps2_io_readdatavalid;
always @(posedge clk_sys) ps2_io_readdatavalid <= ps2_io_read;
reg ps2_sysctl_readdatavalid;
always @(posedge clk_sys) ps2_sysctl_readdatavalid <= ps2_sysctl_read;
reg pit_io_readdatavalid;
always @(posedge clk_sys) pit_io_readdatavalid <= pit_io_read;
reg rtc_io_readdatavalid;
always @(posedge clk_sys) rtc_io_readdatavalid <= rtc_io_read;
reg pic_master_readdatavalid;
always @(posedge clk_sys) pic_master_readdatavalid <= pic_master_read;
reg pic_slave_readdatavalid;
always @(posedge clk_sys) pic_slave_readdatavalid <= pic_slave_read;
reg ide_3f6_readdatavalid;
always @(posedge clk_sys) ide_3f6_readdatavalid <= ide_3f6_read;
reg hdd_io_readdatavalid;
always @(posedge clk_sys) hdd_io_readdatavalid <= hdd_io_read;
wire [31:0] converted_readdata;
wire converted_readdatavalid;
wire [7:0] readdata_without_hdd;
wire readdatavalid_without_hdd;
reg error_rdvalid;
assign readdatavalid_without_hdd = vga_io_b_readdatavalid || vga_io_c_readdatavalid ||
vga_io_d_readdatavalid || ps2_io_readdatavalid ||
ps2_io_readdatavalid || ps2_sysctl_readdatavalid ||
pit_io_readdatavalid || rtc_io_readdatavalid ||
pic_master_readdatavalid || pic_slave_readdatavalid ||
ide_3f6_readdatavalid || error_rdvalid;
assign readdata_without_hdd = (vga_io_b_readdatavalid) ? vga_io_b_readdata :
(vga_io_c_readdatavalid) ? vga_io_c_readdata :
(vga_io_d_readdatavalid) ? vga_io_d_readdata :
(ps2_io_readdatavalid) ? ps2_io_readdata :
(ps2_sysctl_readdatavalid) ? ps2_sysctl_readdata :
(pit_io_readdatavalid) ? pit_io_readdata :
(rtc_io_readdatavalid) ? rtc_io_readdata :
(pic_master_readdatavalid) ? pic_master_readdata :
(pic_slave_readdatavalid) ? pic_slave_readdata :
(ide_3f6_readdatavalid) ? ide_3f6_readdata : 0;
assign ao486_avalon_io_readdata = (hdd_io_readdatavalid) ? hdd_io_readdata : converted_readdata;
assign ao486_avalon_io_readdatavalid = converted_readdatavalid || hdd_io_readdatavalid;
wire [15:0] converted_address;
wire [7:0] converted_writedata;
wire converted_write, converted_read;
byteen_converter #(.IADDR(16), .OADDR(16))
byteen_converter(.clk_sys(clk_sys), .rst(rst), .addr_in(ao486_avalon_io_address), .write_in(ao486_avalon_io_write && ~hdd_io_write),
.writedata_in(ao486_avalon_io_writedata), .read_in(ao486_avalon_io_read && ~hdd_io_read), .byteenable_in(ao486_avalon_io_byteenable),
.waitrequest_out(ao486_avalon_io_waitrequest), .addr_out(converted_address), .write_out(converted_write),
.writedata_out(converted_writedata), .read_out(converted_read), .waitrequest_in(0), .readdata_in(readdata_without_hdd),
.readdatavalid_in(readdatavalid_without_hdd), .readdata_out(converted_readdata), .readdatavalid_out(converted_readdatavalid));
//------------------------------------------------------------------------------------
//------------------ vga_io_b --------------------------------------------------------
//------------------------------------------------------------------------------------
assign vga_io_b_address = converted_address[3:0];
assign vga_io_b_read = (converted_address[15:4] == 12'h3b) && converted_read;
assign vga_io_b_write = (converted_address[15:4] == 12'h3b) && converted_write;
assign vga_io_b_writedata = converted_writedata;
//------------------------------------------------------------------------------------
//------------------ vga_io_c --------------------------------------------------------
//------------------------------------------------------------------------------------
assign vga_io_c_address = converted_address[3:0];
assign vga_io_c_read = (converted_address[15:4] == 12'h3c) && converted_read;
assign vga_io_c_write = (converted_address[15:4] == 12'h3c) && converted_write;
assign vga_io_c_writedata = converted_writedata;
//------------------------------------------------------------------------------------
//------------------ vga_io_d --------------------------------------------------------
//------------------------------------------------------------------------------------
assign vga_io_d_address = converted_address[3:0];
assign vga_io_d_read = (converted_address[15:4] == 12'h3d) && converted_read;
assign vga_io_d_write = (converted_address[15:4] == 12'h3d) && converted_write;
assign vga_io_d_writedata = converted_writedata;
//------------------------------------------------------------------------------------
//------------------ ps2_io ----------------------------------------------------------
//------------------------------------------------------------------------------------
assign ps2_io_address = converted_address[2:0];
assign ps2_io_read = (converted_address[15:4] == 12'h6) && converted_read;
assign ps2_io_write = (converted_address[15:4] == 12'h6) && converted_write;
assign ps2_io_writedata = converted_writedata;
//------------------------------------------------------------------------------------
//------------------ ps2_sysctl ------------------------------------------------------
//------------------------------------------------------------------------------------
assign ps2_sysctl_address = converted_address[3:0];
assign ps2_sysctl_read = (converted_address[15:4] == 12'h9) && converted_read;
assign ps2_sysctl_write = (converted_address[15:4] == 12'h9) && converted_write;
assign ps2_sysctl_writedata = converted_writedata;
//------------------------------------------------------------------------------------
//------------------ pit_io ----------------------------------------------------------
//------------------------------------------------------------------------------------
assign pit_io_address = converted_address[1:0];
assign pit_io_read = (converted_address[15:4] == 12'h4) && converted_read;
assign pit_io_write = (converted_address[15:4] == 12'h4) && converted_write;
assign pit_io_writedata = converted_writedata;
//------------------------------------------------------------------------------------
//------------------ rtc_io ----------------------------------------------------------
//------------------------------------------------------------------------------------
assign rtc_io_address = converted_address[0];
assign rtc_io_read = (converted_address[15:4] == 12'h7) && converted_read;
assign rtc_io_write = (converted_address[15:4] == 12'h7) && converted_write;
assign rtc_io_writedata = converted_writedata;
//------------------------------------------------------------------------------------
//------------------ pic_master ------------------------------------------------------
//------------------------------------------------------------------------------------
assign pic_master_address = converted_address[0];
assign pic_master_read = (converted_address[15:4] == 12'h2) && converted_read;
assign pic_master_write = (converted_address[15:4] == 12'h2) && converted_write;
assign pic_master_writedata = converted_writedata;
//------------------------------------------------------------------------------------
//------------------ pic_slave -------------------------------------------------------
//------------------------------------------------------------------------------------
assign pic_slave_address = converted_address[0];
assign pic_slave_read = (converted_address[15:4] == 12'ha) && converted_read;
assign pic_slave_write = (converted_address[15:4] == 12'ha) && converted_write;
assign pic_slave_writedata = converted_writedata;
//------------------------------------------------------------------------------------
//------------------ hdd_io ----------------------------------------------------------
//------------------------------------------------------------------------------------
assign hdd_io_address = ao486_avalon_io_address[2];
assign hdd_io_read = (ao486_avalon_io_address[15:4] == 12'h1f) && ao486_avalon_io_read;
assign hdd_io_write = (ao486_avalon_io_address[15:4] == 12'h1f) && ao486_avalon_io_write;
assign hdd_io_writedata = ao486_avalon_io_writedata;
assign hdd_io_byteenable = ao486_avalon_io_byteenable;
//------------------------------------------------------------------------------------
//------------------ ide_3f6 ---------------------------------------------------------
//------------------------------------------------------------------------------------
assign ide_3f6_read = (converted_address[15:0] == 16'h3f6) && converted_read;
assign ide_3f6_write = (converted_address[15:0] == 16'h3f6) && converted_write;
assign ide_3f6_writedata = converted_writedata;
//------------------------------------------------------------------------------------
//------------------ error --------------------------------------------------------
//------------------------------------------------------------------------------------
wire error_read = converted_read &&
~(vga_io_b_read || vga_io_c_read || vga_io_d_read || ps2_io_read || ps2_sysctl_read ||
pit_io_read || rtc_io_read || pic_master_read || pic_slave_read ||
ide_3f6_read);
wire error_write = converted_write &&
~(vga_io_b_write || vga_io_c_write || vga_io_d_write || ps2_io_write || ps2_sysctl_write ||
pit_io_write || rtc_io_write || pic_master_write || pic_slave_write ||
ide_3f6_write);
wire error_cond = error_read || error_write;
always @(posedge clk_sys) error_rdvalid <= error_read;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND4B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__NAND4B_BEHAVIORAL_PP_V
/**
* nand4b: 4-input NAND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__nand4b (
Y ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (not0_out , A_N );
nand nand0 (nand0_out_Y , D, C, B, not0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND4B_BEHAVIORAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/05/25 09:40:53
// Design Name:
// Module Name: counters_8bit_with_TD_ff_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module counters_8bit_with_TD_ff_tb(
);
reg Clk, Enable, Clear;
wire [7:0] Q;
counters_8bit_with_TD_ff DUT (.Clk(Clk), .Enable(Enable), .Clear(Clear), .Q(Q));
initial begin
#500 $finish;
end
initial begin
Clk = 0; Enable = 0; Clear = 0;
#5 Clk = 1;
#5 Clk = 0; // 10ns
#5 Clk = 1;
#5 Clk = 0; Enable = 1;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0; Clear = 1;
#5 Clk = 1;
#5 Clk = 0; // 50ns
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0; // 90ns
#5 Clk = 1;
#5 Clk = 0; // 100ns
#5 Clk = 1;
#5 Clk = 0; // 110ns
#5 Clk = 1;
#5 Clk = 0; Enable = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0; // 150ns
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0; // 190ns
#5 Clk = 1;
#5 Clk = 0; Enable = 1;// 200ns
#5 Clk = 1;
#5 Clk = 0; // 210ns
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0; // 250ns
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0; // 290ns
#5 Clk = 1;
#5 Clk = 0; // 300ns
#5 Clk = 1;
#5 Clk = 0; // 310ns
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0; // 350ns
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0; // 390ns
#5 Clk = 1;
#5 Clk = 0; // 400ns
#5 Clk = 1;
#5 Clk = 0; // 410ns
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0; // 450ns
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0;
#5 Clk = 1;
#5 Clk = 0; // 490ns
#5 Clk = 1;
#5 Clk = 0; // 500ns
end
endmodule
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
module sim_artemis_ddr3 (
input ddr3_in_clk,
input rst,
output calibration_done,
output usr_clk,
output usr_rst,
inout [7:0] mcb3_dram_dq,
output [13:0] mcb3_dram_a,
output [2:0] mcb3_dram_ba,
output mcb3_dram_ras_n,
output mcb3_dram_cas_n,
output mcb3_dram_we_n,
output mcb3_dram_odt,
output mcb3_dram_reset_n,
output mcb3_dram_cke,
output mcb3_dram_dm,
inout mcb3_rzq,
inout mcb3_zio,
inout mcb3_dram_dqs,
inout mcb3_dram_dqs_n,
output mcb3_dram_ck,
output mcb3_dram_ck_n,
input p0_cmd_clk,
input p0_cmd_en,
input [2:0] p0_cmd_instr,
input [5:0] p0_cmd_bl,
input [29:0] p0_cmd_byte_addr,
output p0_cmd_empty,
output p0_cmd_full,
input p0_wr_clk,
input p0_wr_en,
input [3:0] p0_wr_mask,
input [31:0] p0_wr_data,
output p0_wr_full,
output p0_wr_empty,
output [6:0] p0_wr_count,
output p0_wr_underrun,
output p0_wr_error,
input p0_rd_clk,
input p0_rd_en,
output [31:0] p0_rd_data,
output p0_rd_full,
output p0_rd_empty,
output [6:0] p0_rd_count,
output p0_rd_overflow,
output p0_rd_error,
input p1_cmd_clk,
input p1_cmd_en,
input [2:0] p1_cmd_instr,
input [5:0] p1_cmd_bl,
input [29:0] p1_cmd_byte_addr,
output p1_cmd_empty,
output p1_cmd_full,
input p1_wr_clk,
input p1_wr_en,
input [3:0] p1_wr_mask,
input [31:0] p1_wr_data,
output p1_wr_full,
output p1_wr_empty,
output [6:0] p1_wr_count,
output p1_wr_underrun,
output p1_wr_error,
input p1_rd_clk,
input p1_rd_en,
output [31:0] p1_rd_data,
output p1_rd_full,
output p1_rd_empty,
output [6:0] p1_rd_count,
output p1_rd_overflow,
output p1_rd_error,
input p2_cmd_clk,
input p2_cmd_en,
input [2:0] p2_cmd_instr,
input [5:0] p2_cmd_bl,
input [29:0] p2_cmd_byte_addr,
output p2_cmd_empty,
output p2_cmd_full,
input p2_wr_clk,
input p2_wr_en,
input [3:0] p2_wr_mask,
input [31:0] p2_wr_data,
output p2_wr_full,
output p2_wr_empty,
output [6:0] p2_wr_count,
output p2_wr_underrun,
output p2_wr_error,
input p2_rd_clk,
input p2_rd_en,
output [31:0] p2_rd_data,
output p2_rd_full,
output p2_rd_empty,
output [6:0] p2_rd_count,
output p2_rd_overflow,
output p2_rd_error,
input p3_cmd_clk,
input p3_cmd_en,
input [2:0] p3_cmd_instr,
input [5:0] p3_cmd_bl,
input [29:0] p3_cmd_byte_addr,
output p3_cmd_empty,
output p3_cmd_full,
input p3_wr_clk,
input p3_wr_en,
input [3:0] p3_wr_mask,
input [31:0] p3_wr_data,
output p3_wr_full,
output p3_wr_empty,
output reg [6:0] p3_wr_count,
output reg p3_wr_underrun,
output reg p3_wr_error,
input p3_rd_clk,
input p3_rd_en,
output reg [31:0] p3_rd_data,
output p3_rd_full,
output p3_rd_empty,
output reg [6:0] p3_rd_count,
output reg p3_rd_overflow,
output reg p3_rd_error
);
//Local Parameters
localparam CMD_WRITE = 3'b000;
localparam CMD_READ = 3'b001;
localparam CMD_WRITE_PC = 3'b010;
localparam CMD_READ_PC = 3'b011;
localparam CMD_REFRESH = 3'b100;
//Registers/Wires
reg [23:0] write_data_count;
reg [23:0] cmd_count;
reg [23:0] read_data_count;
reg [23:0] write_timeout;
reg [23:0] cmd_timeout;
reg [23:0] read_timeout;
reg [23:0] read_data_size;
reg p3_cmd_error;
//Submodules
//Asynchronous Logic
assign p0_cmd_empty = 1;
assign p0_cmd_full = 0;
assign p0_wr_empty = 1;
assign p0_wr_full = 0;
assign p0_wr_count = 0;
assign p0_wr_underrun = 0;
assign p0_wr_error = 0;
assign p0_rd_data = 0;
assign p0_rd_full = 0;
assign p0_rd_empty = 1;
assign p0_rd_count = 0;
assign p0_rd_overflow = 0;
assign p0_rd_error = 0;
assign p1_cmd_empty = 1;
assign p1_cmd_full = 0;
assign p1_wr_empty = 1;
assign p1_wr_full = 0;
assign p1_wr_count = 0;
assign p1_wr_underrun = 0;
assign p1_wr_error = 0;
assign p1_rd_data = 0;
assign p1_rd_full = 0;
assign p1_rd_empty = 1;
assign p1_rd_count = 0;
assign p1_rd_overflow = 0;
assign p1_rd_error = 0;
assign p2_cmd_empty = 1;
assign p2_cmd_full = 0;
assign p2_wr_empty = 1;
assign p2_wr_full = 0;
assign p2_wr_count = 0;
assign p2_wr_underrun = 0;
assign p2_wr_error = 0;
assign p2_rd_data = 0;
assign p2_rd_full = 0;
assign p2_rd_empty = 1;
assign p2_rd_count = 0;
assign p2_rd_overflow = 0;
assign p2_rd_error = 0;
assign p3_wr_full = (write_data_count == 63);
assign p3_wr_empty = (write_data_count == 0);
assign p3_cmd_full = (cmd_count == 4);
assign p3_cmd_empty = (cmd_count == 0);
assign p3_rd_full = (read_data_count == 63);
assign p3_rd_empty = (read_data_count == 0);
//Synchronous Logic
parameter CFIFO_READ_DELAY = 20;
parameter WFIFO_READ_DELAY = 20;
parameter RFIFO_WRITE_DELAY = 10;
always @ (posedge p3_cmd_clk) begin
if (rst) begin
p3_wr_count <= 0;
p3_wr_underrun <= 0;
p3_wr_error <= 0;
p3_rd_data <= 0;
p3_rd_count <= 0;
p3_rd_overflow <= 0;
p3_rd_error <= 0;
p3_cmd_error <= 0;
cmd_count <= 0;
read_data_count <= 0;
write_data_count <= 0;
read_timeout <= RFIFO_WRITE_DELAY;
write_timeout <= WFIFO_READ_DELAY;
cmd_timeout <= CFIFO_READ_DELAY;
read_data_size <= 0;
end
else begin
//Command Stuff
if (p3_cmd_en && !p3_cmd_full) begin
if ((p3_cmd_instr == CMD_WRITE) || (p3_cmd_instr == CMD_WRITE_PC)) begin
if (write_data_count < p3_cmd_bl) begin
p3_wr_underrun <= 1;
end
end
else if ((p3_cmd_instr == CMD_READ) || (p3_cmd_instr == CMD_READ_PC)) begin
read_data_size <= p3_cmd_bl + 1;
end
cmd_count <= cmd_count + 1;
if (cmd_timeout == CFIFO_READ_DELAY) begin
cmd_timeout <= 0;
end
end
else if (p2_cmd_en && p2_cmd_full) begin
p3_cmd_error <= 1;
end
if (cmd_count > 0) begin
if (cmd_timeout < CFIFO_READ_DELAY) begin
cmd_timeout <= cmd_timeout + 1;
end
else begin
cmd_timeout <= 0;
cmd_count <= cmd_count - 1;
end
end
//Write Stuff
if ((write_data_count > 0) && (write_data_count < 64)) begin
if (write_timeout < WFIFO_READ_DELAY) begin
write_timeout <= write_timeout + 1;
end
else begin
write_timeout <= 0;
write_data_count <= write_data_count - 1;
end
end
if (p3_wr_en && !p3_wr_full) begin
write_data_count <= write_data_count + 1;
if (write_timeout == WFIFO_READ_DELAY) begin
write_timeout <= 0;
end
end
//Read Stuff
if (read_data_size > 0) begin
if (read_timeout < RFIFO_WRITE_DELAY) begin
read_timeout <= read_timeout + 1;
end
else begin
read_timeout <= 0;
read_data_size <= read_data_size - 1;
read_data_count <= read_data_count + 1;
end
end
if (read_data_count > 0) begin
if (p3_rd_en && !p3_rd_empty) begin
if (read_data_count > 0) begin
read_data_count <= read_data_count - 1;
p3_rd_data <= p3_rd_data + 1;
end
end
end
//Error Condition
if (p3_rd_en && p3_rd_empty) begin
p3_rd_error <= 1;
end
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
// //
// Copyright (c) 2009/2011 Tobias Gubener //
// Subdesign fAMpIGA by TobiFlex //
// //
// This source file is free software: you can redistribute it and/or modify //
// it under the terms of the GNU General Public License as published //
// by the Free Software Foundation, either version 3 of the License, or //
// (at your option) any later version. //
// //
// This source file is distributed in the hope that it will be useful, //
// but WITHOUT ANY WARRANTY; without even the implied warranty of //
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the //
// GNU General Public License for more details. //
// //
// You should have received a copy of the GNU General Public License //
// along with this program. If not, see <http://www.gnu.org/licenses/>. //
// //
//////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////
module sdram_ctrl(
// system
input wire sysclk,
input wire c_7m,
input wire reset_in,
input wire cache_rst,
input wire cache_inhibit,
input wire [ 4-1:0] cpu_cache_ctrl,
output wire reset_out,
// sdram
output reg [ 13-1:0] sdaddr,
output reg [ 4-1:0] sd_cs,
output reg [ 2-1:0] ba,
output reg sd_we,
output reg sd_ras,
output reg sd_cas,
output reg [ 2-1:0] dqm,
inout wire [ 16-1:0] sdata,
// host
input wire [ 16-1:0] hostWR,
input wire [ 24-1:0] hostAddr,
input wire [ 3-1:0] hostState,
input wire hostL,
input wire hostU,
output reg [ 16-1:0] hostRD,
output wire hostena,
//input wire host_cs,
//input wire [ 24-1:0] host_adr,
//input wire host_we,
//input wire [ 2-1:0] host_bs,
//input wire [ 16-1:0] host_wdat,
//output reg [ 16-1:0] host_rdat,
//output wire host_ack,
// chip
input wire [23:1] chipAddr,
input wire chipL,
input wire chipU,
input wire chipRW,
input wire chip_dma,
input wire [ 16-1:0] chipWR,
output reg [ 16-1:0] chipRD,
output wire [ 48-1:0] chip48,
// cpu
input wire [24:1] cpuAddr,
input wire [ 6-1:0] cpustate,
input wire cpuL,
input wire cpuU,
input wire cpu_dma,
input wire [ 16-1:0] cpuWR,
output wire [ 16-1:0] cpuRD,
output reg enaWRreg,
output reg ena7RDreg,
output reg ena7WRreg,
output wire cpuena,
output reg enaRDreg
);
//// parameters ////
localparam [1:0]
nop = 0,
ras = 1,
cas = 2;
localparam [1:0]
WAITING = 0,
WRITE1 = 1,
WRITE2 = 2,
WRITE3 = 3;
localparam [2:0]
REFRESH = 0,
CHIP = 1,
CPU_READCACHE = 2,
CPU_WRITECACHE = 3,
HOST = 4,
IDLE = 5;
localparam [3:0]
ph0 = 0,
ph1 = 1,
ph2 = 2,
ph3 = 3,
ph4 = 4,
ph5 = 5,
ph6 = 6,
ph7 = 7,
ph8 = 8,
ph9 = 9,
ph10 = 10,
ph11 = 11,
ph12 = 12,
ph13 = 13,
ph14 = 14,
ph15 = 15;
//// local signals ////
reg [ 4-1:0] initstate;
reg [ 4-1:0] cas_sd_cs;
reg cas_sd_ras;
reg cas_sd_cas;
reg cas_sd_we;
reg [ 2-1:0] cas_dqm;
reg init_done;
wire [16-1:0] datain;
reg [16-1:0] datawr;
reg [25-1:0] casaddr;
reg sdwrite;
reg [16-1:0] sdata_reg;
wire [25-1:0] zmAddr;
reg zena;
reg [64-1:0] zcache;
reg [24-1:0] zcache_addr;
reg zcache_fill;
reg zcachehit;
reg [ 4-1:0] zvalid;
reg zequal;
reg [ 2-1:0] hostStated;
reg [16-1:0] hostRDd;
reg cena;
wire [64-1:0] ccache;
wire [25-1:0] ccache_addr;
wire ccache_fill;
wire ccachehit;
wire [ 4-1:0] cvalid;
wire cequal;
wire [ 2-1:0] cpuStated;
wire [16-1:0] cpuRDd;
wire [64-1:0] dcache;
wire [25-1:0] dcache_addr;
wire dcache_fill;
wire dcachehit;
wire [ 4-1:0] dvalid;
wire dequal;
reg [ 8-1:0] hostslot_cnt;
reg [ 8-1:0] reset_cnt;
reg reset;
reg reset_sdstate;
reg c_7md;
reg c_7mdd;
reg c_7mdr;
reg [ 9-1:0] refreshcnt;
reg refresh_pending;
reg [ 4-1:0] sdram_state;
wire [ 2-1:0] pass;
// writebuffer
reg [ 3-1:0] slot1_type = IDLE;
reg [ 3-1:0] slot2_type = IDLE;
reg [ 2-1:0] slot1_bank;
reg [ 2-1:0] slot2_bank;
wire cache_req;
wire readcache_fill;
reg cache_fill_1;
reg cache_fill_2;
reg [16-1:0] chip48_1;
reg [16-1:0] chip48_2;
reg [16-1:0] chip48_3;
reg writebuffer_req;
reg writebuffer_ena;
reg [ 2-1:0] writebuffer_dqm;
reg [25-1:1] writebufferAddr;
reg [16-1:0] writebufferWR;
reg [16-1:0] writebufferWR_reg;
wire writebuffer_cache_ack;
reg writebuffer_hold;
reg [ 2-1:0] writebuffer_state;
wire [25-1:1] cpuAddr_mangled;
////////////////////////////////////////
// address mangling
////////////////////////////////////////
// Let's try some bank-interleaving.
// For addresses in the upper 16 meg we shift bits around
// so that one bank bit comes from addr(3). This should allow
// bank interleaving to make things more efficient.
// Turns out this is counter-productive
//cpuAddr_mangled<=cpuAddr(24)&cpuAddr(3)&cpuAddr(22 downto 4)&cpuAddr(23)&cpuAddr(2 downto 1)
// when cpuAddr(24)='1' else cpuAddr;
assign cpuAddr_mangled = cpuAddr;
////////////////////////////////////////
// reset
////////////////////////////////////////
always @(posedge sysclk) begin
if(!reset_in) begin
reset_cnt <= #1 8'b00000000;
reset <= #1 1'b0;
reset_sdstate <= #1 1'b0;
end else begin
if(reset_cnt == 8'b00101010) begin
reset_sdstate <= #1 1'b1;
end
if(reset_cnt == 8'b10101010) begin
if(sdram_state == ph15) begin
reset <= #1 1'b1;
end
end else begin
reset_cnt <= #1 reset_cnt + 8'd1;
reset <= #1 1'b0;
end
end
end
assign reset_out = init_done;
////////////////////////////////////////
// host access
////////////////////////////////////////
assign hostena = zena || hostState[1:0] == 2'b01 || zcachehit ? 1'b1 : 1'b0;
// map host processor's address space to 0x400000
assign zmAddr = {2'b00, ~hostAddr[22], hostAddr[21:0]};
always @ (*) begin
zequal = (zmAddr[23:3] == zcache_addr[23:3]) ? 1'b1 : 1'b0;
zcachehit = 1'b0;
if(zequal && zvalid[0] && !hostStated[1]) begin
case ({hostAddr[2:1], zcache_addr[2:1]})
4'b0000,
4'b0101,
4'b1010,
4'b1111 : begin
zcachehit = zvalid[0];
hostRD = zcache[63:48];
end
4'b0100,
4'b1001,
4'b1110,
4'b0011 : begin
zcachehit = zvalid[1];
hostRD = zcache[47:32];
end
4'b1000,
4'b1101,
4'b0010,
4'b0111 : begin
zcachehit = zvalid[2];
hostRD = zcache[31:16];
end
4'b1100,
4'b0001,
4'b0110,
4'b1011 : begin
zcachehit = zvalid[3];
hostRD = zcache[15:0];
end
default : begin
end
endcase
end
else begin
hostRD = hostRDd;
end
end
//// host data read ////
always @ (posedge sysclk) begin
if(!reset) begin
zcache_fill <= #1 1'b0;
zena <= #1 1'b0;
zvalid <= #1 4'b0000;
end else begin
if(enaWRreg) begin
zena <= #1 1'b0;
end
if(sdram_state == ph9 && slot1_type == HOST) begin
hostRDd <= #1 sdata_reg;
end
if(sdram_state == ph11 && slot1_type == HOST) begin
zena <= #1 1'b1;
end
hostStated <= #1 hostState[1:0];
if(zequal && |hostState[1:0]) begin
zvalid <= #1 4'b0000;
end
case(sdram_state)
ph7 : begin
if(!hostStated[1] && slot1_type == HOST) begin // only instruction cache
zcache_addr <= #1 casaddr[23:0];
zcache_fill <= #1 1'b1;
zvalid <= #1 4'b0000;
end
end
ph9 : begin
if(zcache_fill) begin
zcache[63:48] <= #1 sdata_reg;
end
end
ph10 : begin
if(zcache_fill) begin
zcache[47:32] <= #1 sdata_reg;
end
end
ph11 : begin
if(zcache_fill) begin
zcache[31:16] <= #1 sdata_reg;
end
end
ph12 : begin
if(zcache_fill) begin
zcache[15:0] <= #1 sdata_reg;
zvalid <= #1 4'b1111;
end
zcache_fill <= #1 1'b0;
end
default : begin
end
endcase
end
end
////////////////////////////////////////
// cpu cache
////////////////////////////////////////
`define SDRAM_NEW_CACHE
`ifdef SDRAM_NEW_CACHE
wire snoop_act;
assign snoop_act = ((sdram_state==ph2)&&(!chipRW));
//// cpu cache ////
cpu_cache_new cpu_cache (
.clk (sysclk), // clock
.rst (!reset || !cache_rst), // cache reset
.cache_en (1'b1), // cache enable
.cpu_cache_ctrl (cpu_cache_ctrl), // CPU cache control
.cache_inhibit (cache_inhibit), // cache inhibit
.cpu_cs (!cpustate[2]), // cpu activity
.cpu_adr ({cpuAddr_mangled, 1'b0}), // cpu address
.cpu_bs ({!cpuU, !cpuL}), // cpu byte selects
.cpu_we (&cpustate[1:0]), // cpu write
.cpu_ir (!(|cpustate[1:0])), // cpu instruction read
.cpu_dr (cpustate[1] && !cpustate[0]), // cpu data read
.cpu_dat_w (cpuWR), // cpu write data
.cpu_dat_r (cpuRD), // cpu read data
.cpu_ack (ccachehit), // cpu acknowledge
.wb_en (writebuffer_cache_ack), // writebuffer enable
.sdr_dat_r (sdata_reg), // sdram read data
.sdr_read_req (cache_req), // sdram read request from cache
.sdr_read_ack (readcache_fill), // sdram read acknowledge to cache
.snoop_act (snoop_act), // snoop act (write only - just update existing data in cache)
.snoop_adr ({1'b0, chipAddr, 1'b0}), // snoop address
.snoop_dat_w (chipWR) // snoop write data
);
`else
//// cpu cache ////
TwoWayCache mytwc (
.clk (sysclk),
.reset (reset),
.cache_rst (cache_rst),
.ready (),
.cpu_addr ({7'b0000000, cpuAddr_mangled, 1'b0}),
.cpu_req (!cpustate[2]),
.cpu_ack (ccachehit),
.cpu_wr_ack (writebuffer_cache_ack),
.cpu_rw (!cpustate[1] || !cpustate[0]),
.cpu_rwl (cpuL),
.cpu_rwu (cpuU),
.data_from_cpu (cpuWR),
.data_to_cpu (cpuRD),
.sdram_addr (),
.data_from_sdram (sdata_reg),
.data_to_sdram (),
.sdram_req (cache_req),
.sdram_fill (readcache_fill),
.sdram_rw (),
.snoop_addr (20'bxxxxxxxxxxxxxxxxxxxx),
.snoop_req (1'bx)
);
`endif
//// writebuffer ////
// write buffer, enables CPU to continue while a write is in progress
always @ (posedge sysclk) begin
if(!reset) begin
writebuffer_req <= #1 1'b0;
writebuffer_ena <= #1 1'b0;
writebuffer_state <= #1 WAITING;
end else begin
case(writebuffer_state)
WAITING : begin
// CPU write cycle, no cycle already pending
if(cpustate[2:0] == 3'b011) begin
writebufferAddr <= #1 cpuAddr_mangled[24:1];
writebufferWR <= #1 cpuWR;
writebuffer_dqm <= #1 {cpuU, cpuL};
writebuffer_req <= #1 1'b1;
if(writebuffer_cache_ack) begin
writebuffer_ena <= #1 1'b1;
writebuffer_state <= #1 WRITE2;
end
end
end
WRITE2 : begin
if(writebuffer_hold) begin
// The SDRAM controller has picked up the request
writebuffer_req <= #1 1'b0;
writebuffer_state <= #1 WRITE3;
end
end
WRITE3 : begin
if(!writebuffer_hold) begin
// Wait for write cycle to finish, so it's safe to update the signals
writebuffer_state <= #1 WAITING;
end
end
default : begin
writebuffer_state <= #1 WAITING;
end
endcase
if(cpustate[2]) begin
// the CPU has unpaused, so clear the ack signal
writebuffer_ena <= #1 1'b0;
end
end
end
assign cpuena = cena || ccachehit || writebuffer_ena;
assign readcache_fill = (cache_fill_1 && slot1_type == CPU_READCACHE) || (cache_fill_2 && slot2_type == CPU_READCACHE);
//// chip line read ////
always @ (posedge sysclk) begin
if(slot1_type == CHIP) begin
case(sdram_state)
ph9 : chipRD <= #1 sdata_reg;
ph10 : chip48_1 <= #1 sdata_reg;
ph11 : chip48_2 <= #1 sdata_reg;
ph12 : chip48_3 <= #1 sdata_reg;
endcase
end
end
assign chip48 = {chip48_1, chip48_2, chip48_3};
////////////////////////////////////////
// SDRAM control
////////////////////////////////////////
//// clock mangling ////
// TODO this is some weird code - it's a 7MHz clock enable on 118MHz clock, used to 'reset' the sdram state machine, to state ph2 ???
always @ (negedge sysclk) begin
c_7md <= c_7m;
end
always @ (posedge sysclk) begin
c_7mdd <= c_7md;
c_7mdr <= c_7md & ~c_7mdd;
end
//// sdram data I/O ////
assign sdata = (sdwrite) ? datawr : 16'bzzzzzzzzzzzzzzzz;
//// read data reg ////
always @ (posedge sysclk) begin
sdata_reg <= #1 sdata;
end
//// write data reg ////
always @ (posedge sysclk) begin
if(sdram_state == ph2) begin
case(slot1_type)
CHIP : begin
datawr <= #1 chipWR;
end
CPU_WRITECACHE : begin
datawr <= #1 writebufferWR_reg;
end
default : begin
datawr <= #1 hostWR;
end
endcase
end else if(sdram_state == ph10) begin
case(slot2_type)
CHIP : begin
datawr <= #1 chipWR;
end
CPU_WRITECACHE : begin
datawr <= #1 writebufferWR_reg;
end
default : begin
datawr <= #1 hostWR;
end
endcase
end
end
//// write / read control ////
always @ (posedge sysclk) begin
if(!reset_sdstate) begin
sdwrite <= #1 1'b0;
enaRDreg <= #1 1'b0;
enaWRreg <= #1 1'b0;
ena7RDreg <= #1 1'b0;
ena7WRreg <= #1 1'b0;
end else begin
sdwrite <= #1 1'b0;
enaRDreg <= #1 1'b0;
enaWRreg <= #1 1'b0;
ena7RDreg <= #1 1'b0;
ena7WRreg <= #1 1'b0;
case(sdram_state) // LATENCY=3
ph2 : begin
enaWRreg <= #1 1'b1;
end
ph3 : begin
sdwrite <= #1 1'b1;
end
ph4 : begin
sdwrite <= #1 1'b1;
end
ph5 : begin
sdwrite <= #1 1'b1;
end
ph6 : begin
enaWRreg <= #1 1'b1;
ena7RDreg <= #1 1'b1;
end
ph10 : begin
enaWRreg <= #1 1'b1;
end
ph11 : begin
sdwrite <= #1 1'b1; // access slot 2
end
ph12 : begin
sdwrite <= #1 1'b1;
end
ph13 : begin
sdwrite <= #1 1'b1;
end
ph14 : begin
enaWRreg <= #1 1'b1;
ena7WRreg <= #1 1'b1;
end
default : begin
end
endcase
end
end
//// init counter ////
always @ (posedge sysclk) begin
if(!reset) begin
initstate <= #1 {4{1'b0}};
init_done <= #1 1'b0;
end else begin
case(sdram_state) // LATENCY=3
ph15 : begin
if(initstate != 4'b 1111) begin
initstate <= #1 initstate + 4'd1;
end else begin
init_done <= #1 1'b1;
end
end
default : begin
end
endcase
end
end
//// sdram state ////
always @ (posedge sysclk) begin
if(c_7mdr) begin
sdram_state <= #1 ph2;
end else begin
case(sdram_state) // LATENCY=3
ph0 : sdram_state <= #1 ph1;
ph1 : sdram_state <= #1 ph2;
ph2 : sdram_state <= #1 ph3;
ph3 : sdram_state <= #1 ph4;
ph4 : sdram_state <= #1 ph5;
ph5 : sdram_state <= #1 ph6;
ph6 : sdram_state <= #1 ph7;
ph7 : sdram_state <= #1 ph8;
ph8 : sdram_state <= #1 ph9;
ph9 : sdram_state <= #1 ph10;
ph10 : sdram_state <= #1 ph11;
ph11 : sdram_state <= #1 ph12;
ph12 : sdram_state <= #1 ph13;
ph13 : sdram_state <= #1 ph14;
ph14 : sdram_state <= #1 ph15;
default : sdram_state <= #1 ph0;
endcase
end
end
//// sdram control ////
// Address bits will be allocated as follows:
// 24 downto 23: bank
// 22 downto 10: row
// 9 downto 1: column
always @ (posedge sysclk) begin
if(!reset) begin
refresh_pending <= #1 1'b0;
slot1_type <= #1 IDLE;
slot2_type <= #1 IDLE;
end
sd_cs <= #1 4'b1111;
sd_ras <= #1 1'b1;
sd_cas <= #1 1'b1;
sd_we <= #1 1'b1;
sdaddr <= #1 13'bxxxxxxxxxxxxx;
ba <= #1 2'b00;
dqm <= #1 2'b00;
cache_fill_1 <= #1 1'b0;
cache_fill_2 <= #1 1'b0;
if(cpustate[5]) begin
cena <= 1'b0;
end
if(!init_done) begin
if(sdram_state == ph1) begin
case(initstate)
4'b0010 : begin // PRECHARGE
sdaddr[10] <= #1 1'b1; // all banks
sd_cs <= #1 4'b0000;
sd_ras <= #1 1'b0;
sd_cas <= #1 1'b1;
sd_we <= #1 1'b0;
end
4'b0011,
4'b0100,
4'b0101,
4'b0110,
4'b0111,
4'b1000,
4'b1001,
4'b1010,
4'b1011,
4'b1100 : begin // AUTOREFRESH
sd_cs <= #1 4'b0000;
sd_ras <= #1 1'b0;
sd_cas <= #1 1'b0;
sd_we <= #1 1'b1;
end
4'b1101 : begin // LOAD MODE REGISTER
sd_cs <= #1 4'b0000;
sd_ras <= #1 1'b0;
sd_cas <= #1 1'b0;
sd_we <= #1 1'b0;
//sdaddr <= #1 13'b0001000100010; // BURST=4 LATENCY=2
sdaddr <= #1 13'b0001000110010; // BURST=4 LATENCY=3
//sdaddr <= #1 13'b0001000110000; // noBURST LATENCY=3
end
default : begin
// NOP
end
endcase
end
end else begin
// Time slot control
case(sdram_state)
ph0 : begin
cache_fill_2 <= #1 1'b1; // slot 2
end
ph1 : begin
cache_fill_2 <= #1 1'b1; // slot 2
cas_sd_cs <= #1 4'b1110;
cas_sd_ras <= #1 1'b1;
cas_sd_cas <= #1 1'b1;
cas_sd_we <= #1 1'b1;
if(|hostslot_cnt) begin
hostslot_cnt <= #1 hostslot_cnt - 8'd1;
end
if(~|refreshcnt) begin
refresh_pending <= #1 1'b1;
end else begin
refreshcnt <= #1 refreshcnt - 9'd1;
end
// we give the chipset first priority
// (this includes anything on the "motherboard" - chip RAM, slow RAM and Kickstart, turbo modes notwithstanding)
if(!chip_dma || !chipRW) begin
slot1_type <= #1 CHIP;
sdaddr <= #1 chipAddr[22:10];
ba <= #1 2'b00; // always bank zero for chipset accesses, so we can interleave Fast RAM access
slot1_bank <= #1 2'b00;
cas_dqm <= #1 {chipU,chipL};
sd_cs <= #1 4'b1110; // ACTIVE
sd_ras <= #1 1'b0;
casaddr <= #1 {1'b0, chipAddr, 1'b0};
cas_sd_cas <= #1 1'b0;
cas_sd_we <= #1 chipRW;
end
// next in line is refresh
// (a refresh cycle blocks both access slots)
else if(refresh_pending && slot2_type == IDLE) begin
sd_cs <= #1 4'b0000; // AUTOREFRESH
sd_ras <= #1 1'b0;
sd_cas <= #1 1'b0;
refreshcnt <= #1 9'b111111111;
slot1_type <= #1 REFRESH;
refresh_pending <= #1 1'b0;
end
// the Amiga CPU gets next bite of the cherry, unless the OSD CPU has been cycle-starved
// request from write buffer
else if(writebuffer_req && (|hostslot_cnt || (hostState[2] || hostena)) && (slot2_type == IDLE || slot2_bank != writebufferAddr[24:23])) begin
// We only yield to the OSD CPU if it's both cycle-starved and ready to go.
slot1_type <= #1 CPU_WRITECACHE;
sdaddr <= #1 writebufferAddr[22:10];
ba <= #1 writebufferAddr[24:23];
slot1_bank <= #1 writebufferAddr[24:23];
cas_dqm <= #1 writebuffer_dqm;
sd_cs <= #1 4'b1110; // ACTIVE
sd_ras <= #1 1'b0;
casaddr <= #1 {writebufferAddr[24:1], 1'b0};
cas_sd_we <= #1 1'b0;
writebufferWR_reg <= #1 writebufferWR;
cas_sd_cas <= #1 1'b0;
writebuffer_hold <= #1 1'b1; // let the write buffer know we're about to write
end
// request from read cache
else if(cache_req && (|hostslot_cnt || (hostState[2] || hostena)) && (slot2_type == IDLE || slot2_bank != cpuAddr_mangled[24:23])) begin
// we only yield to the OSD CPU if it's both cycle-starved and ready to go
slot1_type <= #1 CPU_READCACHE;
sdaddr <= #1 cpuAddr_mangled[22:10];
ba <= #1 cpuAddr_mangled[24:23];
slot1_bank <= #1 cpuAddr_mangled[24:23];
cas_dqm <= #1 {cpuU,cpuL};
sd_cs <= #1 4'b1110; // ACTIVE
sd_ras <= #1 1'b0;
casaddr <= #1 {cpuAddr_mangled[24:1], 1'b0};
cas_sd_we <= #1 1'b1;
cas_sd_cas <= #1 1'b0;
end
else if(!hostState[2] && !hostena) begin
hostslot_cnt <= #1 8'b00001111;
slot1_type <= #1 HOST;
sdaddr <= #1 zmAddr[22:10];
ba <= #1 2'b00;
// Always bank zero for SPI host CPU
slot1_bank <= #1 2'b00;
cas_dqm <= #1 {hostU,hostL};
sd_cs <= #1 4'b1110;
// ACTIVE
sd_ras <= #1 1'b0;
casaddr <= #1 zmAddr;
cas_sd_cas <= #1 1'b0;
if(hostState == 3'b011) begin
cas_sd_we <= #1 1'b0;
end
end
else begin
slot1_type <= #1 IDLE;
end
end
ph2 : begin
// slot 2
cache_fill_2 <= #1 1'b1;
end
ph3 : begin
// slot 2
cache_fill_2 <= #1 1'b1;
end
ph4 : begin
sdaddr <= #1 {1'b0, 1'b0, 1'b1, 1'b0, casaddr[9:1]}; // AUTO PRECHARGE
ba <= #1 casaddr[24:23];
sd_cs <= #1 cas_sd_cs;
if(!cas_sd_we) begin
dqm <= #1 cas_dqm;
end
sd_ras <= #1 cas_sd_ras;
sd_cas <= #1 cas_sd_cas;
sd_we <= #1 cas_sd_we;
writebuffer_hold <= #1 1'b0; // indicate to WriteBuffer that it's safe to accept the next write
end
ph8 : begin
cache_fill_1 <= #1 1'b1;
end
ph9 : begin
cache_fill_1 <= #1 1'b1;
// Access slot 2, RAS
cas_sd_cs <= #1 4'b1110;
cas_sd_ras <= #1 1'b1;
cas_sd_cas <= #1 1'b1;
cas_sd_we <= #1 1'b1;
slot2_type <= #1 IDLE;
if(!refresh_pending && slot1_type != REFRESH) begin
if(writebuffer_req && |writebufferAddr[24:23] && (slot1_type == IDLE || slot1_bank != writebufferAddr[24:23])) begin // reserve bank 0 for slot 1
// We only yield to the OSD CPU if it's both cycle-starved and ready to go.
slot2_type <= #1 CPU_WRITECACHE;
sdaddr <= #1 writebufferAddr[22:10];
ba <= #1 writebufferAddr[24:23];
slot2_bank <= #1 writebufferAddr[24:23];
cas_dqm <= #1 writebuffer_dqm;
sd_cs <= #1 4'b1110; // ACTIVE
sd_ras <= #1 1'b0;
casaddr <= #1 {writebufferAddr[24:1], 1'b0};
cas_sd_we <= #1 1'b0;
writebufferWR_reg <= #1 writebufferWR;
cas_sd_cas <= #1 1'b0;
writebuffer_hold <= #1 1'b1; // let the write buffer know we're about to write
end
// request from read cache
else if(cache_req && |cpuAddr[24:23] && (slot1_type == IDLE || slot1_bank != cpuAddr_mangled[24:23])) begin // reserve bank 0 for slot 1
slot2_type <= #1 CPU_READCACHE;
sdaddr <= #1 cpuAddr_mangled[22:10];
ba <= #1 cpuAddr_mangled[24:23];
slot2_bank <= #1 cpuAddr_mangled[24:23];
cas_dqm <= #1 {cpuU, cpuL};
sd_cs <= #1 4'b1110; // ACTIVE
sd_ras <= #1 1'b0;
casaddr <= #1 {cpuAddr_mangled[24:1], 1'b0};
cas_sd_we <= #1 1'b1;
cas_sd_cas <= #1 1'b0;
end
end
end
ph10 : begin
cache_fill_1 <= #1 1'b1;
end
ph11 : begin
cache_fill_1 <= #1 1'b1;
end
// slot 2 CAS
ph12 : begin
sdaddr <= #1 {1'b0, 1'b0, 1'b1, 1'b0, casaddr[9:1]}; // AUTO PRECHARGE
ba <= #1 casaddr[24:23];
sd_cs <= #1 cas_sd_cs;
if(!cas_sd_we) begin
dqm <= #1 cas_dqm;
end
sd_ras <= #1 cas_sd_ras;
sd_cas <= #1 cas_sd_cas;
sd_we <= #1 cas_sd_we;
writebuffer_hold <= #1 1'b0; // indicate to WriteBuffer that it's safe to accept the next write
end
default : begin
end
endcase
end
end
//// slots ////
// Slot 1 Slot 2
// ph0 (read) (Read 0 in sdata)
// ph1 Slot alloc, RAS (read) Read0
// ph2 ... (read) Read1
// ph3 ... (write) Read2 (read3 in sdata)
// ph4 CAS, write0 (write) Read3
// ph5 write1 (write)
// ph6 write2 (write)
// ph7 write3 (read)
// ph8 (read0 in sdata) (rd)
// ph9 read0 in sdata_reg (rd) Slot alloc, RAS
// ph10 read1 (read) ...
// ph11 read2 (rd3 in sdata, wr) ...
// ph12 read3 (write) CAS, write 0
// ph13 (write) write1
// ph14 (write) write2
// ph15 (read) write3
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A31OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__A31OI_BEHAVIORAL_PP_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__a31oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A31OI_BEHAVIORAL_PP_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:54:08 01/30/2016
// Design Name:
// Module Name: alu_control
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module alu_control(
input [5:0] ALUOp,
input [5:0] funct,
output wire [3:0] ALUcontrolOut
);
assign ALUcontrolOut = (ALUOp == 6'b000100) ? 4'b0001 : //SUB para BEQ
(ALUOp == 6'b000101) ? 4'b0001 : //SUB para BNE
(ALUOp == 6'b001000) ? 4'b0000 : //ADDI
(ALUOp == 6'b001010) ? 4'b0110 : //SLTI
(ALUOp == 6'b001100) ? 4'b0010 : //ANDI
(ALUOp == 6'b001101) ? 4'b0011 : //ORI
(ALUOp == 6'b001110) ? 4'b0100 : //XORI
(ALUOp == 6'b001111) ? 4'b1101 : //LUI
(ALUOp == 6'b100000) ? 4'b0000 : //ADD para LB
(ALUOp == 6'b100001) ? 4'b0000 : //ADD para LH
(ALUOp == 6'b100011) ? 4'b0000 : //ADD para LW
(ALUOp == 6'b100100) ? 4'b0000 : //ADD para LBU
(ALUOp == 6'b100101) ? 4'b0000 : //ADD para LHU
(ALUOp == 6'b100111) ? 4'b0000 : //ADD para LWU
(ALUOp == 6'b101000) ? 4'b0000 : //ADD para SB
(ALUOp == 6'b101001) ? 4'b0000 : //ADD para SH
(ALUOp == 6'b101011) ? 4'b0000 : //ADD para SW
(ALUOp == 6'b000011) ? 4'b0000 : //ADD para JAL
( (funct == 6'b100000) ? 4'b0000 : //ADD
(funct == 6'b100010) ? 4'b0001 : //SUB
(funct == 6'b100100) ? 4'b0010 : //AND
(funct == 6'b100101) ? 4'b0011 : //OR
(funct == 6'b100110) ? 4'b0100 : //XOR
(funct == 6'b100111) ? 4'b0101 : //NOR
(funct == 6'b101010) ? 4'b0110 : //SLT
(funct == 6'b000000) ? 4'b0111 : //SLL
(funct == 6'b000010) ? 4'b1000 : //SRL
(funct == 6'b000011) ? 4'b1001 : //SRA
(funct == 6'b000100) ? 4'b1010 : //SLLV
(funct == 6'b000110) ? 4'b1011 : //SRLV
(funct == 6'b000111) ? 4'b1100 : //SRAV
(funct == 6'b001001) ? 4'b0000 : //ADD para JALR
4'b1111); // --> Para identificar errores
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB4TO1_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__MUXB4TO1_FUNCTIONAL_V
/**
* muxb4to1: Buffered 4-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__muxb4to1 (
Z,
D,
S
);
// Module ports
output Z;
input [3:0] D;
input [3:0] S;
// Name Output Other arguments
bufif1 bufif10 (Z , !D[0], S[0] );
bufif1 bufif11 (Z , !D[1], S[1] );
bufif1 bufif12 (Z , !D[2], S[2] );
bufif1 bufif13 (Z , !D[3], S[3] );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB4TO1_FUNCTIONAL_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: fpu_div_frac_dp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////////////
//
// Divide pipeline fraction datapath.
//
///////////////////////////////////////////////////////////////////////////////
module fpu_div_frac_dp (
inq_in1,
inq_in2,
d1stg_step,
div_norm_frac_in1_dbl_norm,
div_norm_frac_in1_dbl_dnrm,
div_norm_frac_in1_sng_norm,
div_norm_frac_in1_sng_dnrm,
div_norm_frac_in2_dbl_norm,
div_norm_frac_in2_dbl_dnrm,
div_norm_frac_in2_sng_norm,
div_norm_frac_in2_sng_dnrm,
div_norm_inf,
div_norm_qnan,
d1stg_dblop,
div_norm_zero,
d1stg_snan_dbl_in1,
d1stg_snan_sng_in1,
d1stg_snan_dbl_in2,
d1stg_snan_sng_in2,
d3stg_fdiv,
d6stg_fdiv,
d6stg_fdivd,
d6stg_fdivs,
div_frac_add_in2_load,
d6stg_frac_out_shl1,
d6stg_frac_out_nosh,
d4stg_fdiv,
div_frac_add_in1_add,
div_frac_add_in1_load,
d5stg_fdivb,
div_frac_out_add_in1,
div_frac_out_add,
div_frac_out_shl1_dbl,
div_frac_out_shl1_sng,
div_frac_out_of,
d7stg_to_0,
div_frac_out_load,
fdiv_clken_l,
rclk,
div_shl_cnt,
d6stg_frac_0,
d6stg_frac_1,
d6stg_frac_2,
d6stg_frac_29,
d6stg_frac_30,
d6stg_frac_31,
div_frac_add_in1_neq_0,
div_frac_add_52_inv,
div_frac_add_52_inva,
div_frac_out_54_53,
div_frac_outa,
se,
si,
so
);
input [54:0] inq_in1; // request operand 1 to op pipes
input [54:0] inq_in2; // request operand 2 to op pipes
input d1stg_step; // divide pipe load
input div_norm_frac_in1_dbl_norm; // select line to div_norm
input div_norm_frac_in1_dbl_dnrm; // select line to div_norm
input div_norm_frac_in1_sng_norm; // select line to div_norm
input div_norm_frac_in1_sng_dnrm; // select line to div_norm
input div_norm_frac_in2_dbl_norm; // select line to div_norm
input div_norm_frac_in2_dbl_dnrm; // select line to div_norm
input div_norm_frac_in2_sng_norm; // select line to div_norm
input div_norm_frac_in2_sng_dnrm; // select line to div_norm
input div_norm_inf; // select line to div_norm
input div_norm_qnan; // select line to div_norm
input d1stg_dblop; // double precision operation- d1 stg
input div_norm_zero; // select line to div_norm
input d1stg_snan_dbl_in1; // operand 1 is double signalling NaN
input d1stg_snan_sng_in1; // operand 1 is single signalling NaN
input d1stg_snan_dbl_in2; // operand 2 is double signalling NaN
input d1stg_snan_sng_in2; // operand 2 is single signalling NaN
input d3stg_fdiv; // divide operation- divide stage 3
input d6stg_fdiv; // divide operation- divide stage 6
input d6stg_fdivd; // divide double- divide stage 6
input d6stg_fdivs; // divide single- divide stage 6
input div_frac_add_in2_load; // load enable to div_frac_add_in2
input d6stg_frac_out_shl1; // select line to d6stg_frac
input d6stg_frac_out_nosh; // select line to d6stg_frac
input d4stg_fdiv; // divide operation- divide stage 4
input div_frac_add_in1_add; // select line to div_frac_add_in1
input div_frac_add_in1_load; // load enable to div_frac_add_in1
input d5stg_fdivb; // divide operation- divide stage 5
input div_frac_out_add_in1; // select line to div_frac_out
input div_frac_out_add; // select line to div_frac_out
input div_frac_out_shl1_dbl; // select line to div_frac_out
input div_frac_out_shl1_sng; // select line to div_frac_out
input div_frac_out_of; // select line to div_frac_out
input d7stg_to_0; // result to max finite on overflow
input div_frac_out_load; // load enable to div_frac_out
input fdiv_clken_l; // div pipe clk enable - asserted low
input rclk; // global clock
output [5:0] div_shl_cnt; // divide left shift amount
output d6stg_frac_0; // divide fraction[0]- intermediate val
output d6stg_frac_1; // divide fraction[1]- intermediate val
output d6stg_frac_2; // divide fraction[2]- intermediate val
output d6stg_frac_29; // divide fraction[29]- intermediate val
output d6stg_frac_30; // divide fraction[30]- intermediate val
output d6stg_frac_31; // divide fraction[31]- intermediate val
output div_frac_add_in1_neq_0; // div_frac_add_in1 != 0
output div_frac_add_52_inv; // div_frac_add bit[52] inverted
output div_frac_add_52_inva; // div_frac_add bit[52] inverted copy
output [1:0] div_frac_out_54_53; // divide fraction output
output [51:0] div_frac_outa; // divide fraction output- buffered copy
input se; // scan_enable
input si; // scan in
output so; // scan out
wire [54:0] div_frac_in1;
wire [54:0] div_frac_in2;
wire [52:0] div_norm_inv_in;
wire [52:0] div_norm_inv;
wire [52:0] div_norm;
wire [5:0] div_lead0;
wire [5:0] div_shl_cnt;
wire [5:0] div_shl_cnta;
wire [52:0] div_shl_data;
wire [105:53] div_shl_tmp;
wire [52:0] div_shl;
wire [54:0] div_shl_save;
wire [54:0] div_frac_add_in2_in;
wire [54:0] div_frac_add_in2;
wire [53:0] d6stg_frac;
wire d6stg_frac_0;
wire d6stg_frac_1;
wire d6stg_frac_2;
wire d6stg_frac_29;
wire d6stg_frac_30;
wire d6stg_frac_31;
wire [54:0] div_frac_add_in1_in;
wire [54:0] div_frac_add_in1;
wire [54:0] div_frac_add_in1a;
wire div_frac_add_in1_neq_0;
wire [54:0] div_frac_add;
wire div_frac_add_52_inv;
wire div_frac_add_52_inva;
wire [54:0] div_frac_out_in;
wire [1:0] div_frac_out_54_53;
wire [54:0] div_frac_out;
wire [51:0] div_frac_outa;
wire se_l;
assign se_l = ~se;
clken_buf ckbuf_div_frac_dp (
.clk(clk),
.rclk(rclk),
.enb_l(fdiv_clken_l),
.tmb_l(se_l)
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide fraction inputs.
//
///////////////////////////////////////////////////////////////////////////////
dffe #(55) i_div_frac_in1 (
.din (inq_in1[54:0]),
.en (d1stg_step),
.clk (clk),
.q (div_frac_in1[54:0]),
.se (se),
.si (),
.so ()
);
dffe #(55) i_div_frac_in2 (
.din (inq_in2[54:0]),
.en (d1stg_step),
.clk (clk),
.q (div_frac_in2[54:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide normalization and special input injection.
//
///////////////////////////////////////////////////////////////////////////////
assign div_norm_inv_in[52:0]= (~(({53{div_norm_frac_in1_dbl_norm}}
& {1'b1, (div_frac_in1[51] || d1stg_snan_dbl_in1),
div_frac_in1[50:0]})
| ({53{div_norm_frac_in1_dbl_dnrm}}
& {div_frac_in1[51:0], 1'b0})
| ({53{div_norm_frac_in1_sng_norm}}
& {1'b1, (div_frac_in1[54] || d1stg_snan_sng_in1),
div_frac_in1[53:32], 29'b0})
| ({53{div_norm_frac_in1_sng_dnrm}}
& {div_frac_in1[54:32], 30'b0})
| ({53{div_norm_frac_in2_dbl_norm}}
& {1'b1, (div_frac_in2[51] || d1stg_snan_dbl_in2),
div_frac_in2[50:0]})
| ({53{div_norm_frac_in2_dbl_dnrm}}
& {div_frac_in2[51:0], 1'b0})
| ({53{div_norm_frac_in2_sng_norm}}
& {1'b1, (div_frac_in2[54] || d1stg_snan_sng_in2),
div_frac_in2[53:32], 29'b0})
| ({53{div_norm_frac_in2_sng_dnrm}}
& {div_frac_in2[54:32], 30'b0})
| ({53{div_norm_inf}}
& 53'h10000000000000)
| ({53{div_norm_qnan}}
& {24'hffffff, {29{d1stg_dblop}}})
| ({53{div_norm_zero}}
& 53'h00000000000000)));
dff #(53) i_div_norm_inv (
.din (div_norm_inv_in[52:0]),
.clk (clk),
.q (div_norm_inv[52:0]),
.se (se),
.si (),
.so ()
);
assign div_norm[52:0]= (~div_norm_inv);
///////////////////////////////////////////////////////////////////////////////
//
// Divide lead zero count.
//
///////////////////////////////////////////////////////////////////////////////
fpu_cnt_lead0_53b i_div_lead0 (
.din (div_norm[52:0]),
.lead0 (div_lead0[5:0])
);
dff #12 i_dstg_xtra_regs (
.din ({div_lead0[5:0], div_lead0[5:0]}),
.clk (clk),
.q ({div_shl_cnta[5:0], div_shl_cnt[5:0]}),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide left shift.
//
///////////////////////////////////////////////////////////////////////////////
dff #(53) i_div_shl_data (
.din (div_norm[52:0]),
.clk (clk),
.q (div_shl_data[52:0]),
.se (se),
.si (),
.so ()
);
//assign div_shl_tmp[105:0]= {div_shl_data[52:0], 53'b0} << div_shl_cnta[5:0];
assign div_shl_tmp[105:53]= div_shl_data[52:0] << div_shl_cnta[5:0];
assign div_shl[52:0]= div_shl_tmp[105:53];
dffe #(55) i_div_shl_save (
.din ({2'b0, div_shl[52:0]}),
.en (d3stg_fdiv),
.clk (clk),
.q (div_shl_save[54:0]),
.se (se),
.si (),
.so ()
);
assign div_frac_add_in2_in[54:0]= ({55{d4stg_fdiv}}
& (~{2'b0, div_shl[52:0]}))
| ({55{d6stg_fdiv}}
& {25'b0, d6stg_fdivs, 28'b0, d6stg_fdivd});
dffe #(55) i_div_frac_add_in2 (
.din (div_frac_add_in2_in[54:0]),
.en (div_frac_add_in2_load),
.clk (clk),
.q (div_frac_add_in2[54:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide adder/subtractor 2nd input.
//
///////////////////////////////////////////////////////////////////////////////
assign d6stg_frac[53:0]= ({54{d6stg_frac_out_shl1}}
& {div_frac_out[52:0], 1'b0})
| ({54{d6stg_frac_out_nosh}}
& div_frac_out[53:0]);
assign d6stg_frac_0= d6stg_frac[0];
assign d6stg_frac_1= d6stg_frac[1];
assign d6stg_frac_2= d6stg_frac[2];
assign d6stg_frac_29= d6stg_frac[29];
assign d6stg_frac_30= d6stg_frac[30];
assign d6stg_frac_31= d6stg_frac[31];
assign div_frac_add_in1_in[54:0]= ({55{d4stg_fdiv}}
& div_shl_save[54:0])
| ({55{(div_frac_add_in1_add && (!div_frac_add[54]))}}
& {div_frac_add[53:0], 1'b0})
| ({55{(div_frac_add_in1_add && div_frac_add[54])}}
& {div_frac_add_in1[53:0], 1'b0})
| ({55{d6stg_fdiv}}
& {3'b0, d6stg_frac[53:31],
(d6stg_frac[30:2] & {29{d6stg_fdivd}})});
dffe #(55) i_div_frac_add_in1 (
.din (div_frac_add_in1_in[54:0]),
.en (div_frac_add_in1_load),
.clk (clk),
.q (div_frac_add_in1[54:0]),
.se (se),
.si (),
.so ()
);
dffe #(55) i_div_frac_add_in1a (
.din (div_frac_add_in1_in[54:0]),
.en (div_frac_add_in1_load),
.clk (clk),
.q (div_frac_add_in1a[54:0]),
.se (se),
.si (),
.so ()
);
assign div_frac_add_in1_neq_0= (|div_frac_add_in1[54:0]);
///////////////////////////////////////////////////////////////////////////////
//
// Divide adder/subtractor.
//
///////////////////////////////////////////////////////////////////////////////
assign div_frac_add[54:0]= (div_frac_add_in1a[54:0]
+ div_frac_add_in2[54:0]
+ {54'b0, d5stg_fdivb});
assign div_frac_add_52_inv= (!div_frac_add[52]);
assign div_frac_add_52_inva= (!div_frac_add[52]);
assign div_frac_out_in[54:0]= ({55{d4stg_fdiv}}
& 55'b0)
| ({55{div_frac_out_add_in1}}
& div_frac_add_in1[54:0])
| ({55{div_frac_out_add}}
& div_frac_add[54:0])
| ({55{div_frac_out_shl1_dbl}}
& {div_frac_out[53:0], (!div_frac_add[54])})
| ({55{div_frac_out_shl1_sng}}
& {div_frac_out[53:29], (!div_frac_add[54]), 29'b0})
| ({55{div_frac_out_of}}
& {55{d7stg_to_0}});
dffe #(55) i_div_frac_out (
.din (div_frac_out_in[54:0]),
.en (div_frac_out_load),
.clk (clk),
.q (div_frac_out[54:0]),
.se (se),
.si (),
.so ()
);
assign div_frac_out_54_53[1:0] = div_frac_out[54:53];
assign div_frac_outa[51:0]= div_frac_out[51:0];
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
// ----------------------------------------------------------------------
// Filename: Filename: tx_multiplexer_64.v
// Version: Version: 1.0
// Verilog Standard: Verilog-2005
// Description: the TX Multiplexer services read and write requests from
// RIFFA channels in round robin order.
// Author: Dustin Richmond (@darichmond)
// ----------------------------------------------------------------------
`include "trellis.vh"
`define S_TXENGUPR128_MAIN_IDLE 1'b0
`define S_TXENGUPR128_MAIN_WR 1'b1
`define S_TXENGUPR128_CAP_RD_WR 4'b0001
`define S_TXENGUPR128_CAP_WR_RD 4'b0010
`define S_TXENGUPR128_CAP_CAP 4'b0100
`define S_TXENGUPR128_CAP_REL 4'b1000
`timescale 1ns/1ns
module tx_multiplexer_128
#(
parameter C_PCI_DATA_WIDTH = 128,
parameter C_NUM_CHNL = 12,
parameter C_TAG_WIDTH = 5, // Number of outstanding requests
parameter C_VENDOR = "ALTERA"
)
(
input CLK,
input RST_IN,
input [C_NUM_CHNL-1:0] WR_REQ, // Write request
input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] WR_ADDR, // Write address
input [(C_NUM_CHNL*`SIG_LEN_W)-1:0] WR_LEN, // Write data length
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] WR_DATA, // Write data
output [C_NUM_CHNL-1:0] WR_DATA_REN, // Write data read enable
output [C_NUM_CHNL-1:0] WR_ACK, // Write request has been accepted
input [C_NUM_CHNL-1:0] RD_REQ, // Read request
input [(C_NUM_CHNL*2)-1:0] RD_SG_CHNL, // Read request channel for scatter gather lists
input [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] RD_ADDR, // Read request address
input [(C_NUM_CHNL*`SIG_LEN_W)-1:0] RD_LEN, // Read request length
output [C_NUM_CHNL-1:0] RD_ACK, // Read request has been accepted
output [5:0] INT_TAG, // Internal tag to exchange with external
output INT_TAG_VALID, // High to signal tag exchange
input [C_TAG_WIDTH-1:0] EXT_TAG, // External tag to provide in exchange for internal tag
input EXT_TAG_VALID, // High to signal external tag is valid
output TX_ENG_RD_REQ_SENT, // Read completion request issued
input RXBUF_SPACE_AVAIL,
// Interface: TXR Engine
output TXR_DATA_VALID,
output [C_PCI_DATA_WIDTH-1:0] TXR_DATA,
output TXR_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
output TXR_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
input TXR_DATA_READY,
output TXR_META_VALID,
output [`SIG_FBE_W-1:0] TXR_META_FDWBE,
output [`SIG_LBE_W-1:0] TXR_META_LDWBE,
output [`SIG_ADDR_W-1:0] TXR_META_ADDR,
output [`SIG_LEN_W-1:0] TXR_META_LENGTH,
output [`SIG_TAG_W-1:0] TXR_META_TAG,
output [`SIG_TC_W-1:0] TXR_META_TC,
output [`SIG_ATTR_W-1:0] TXR_META_ATTR,
output [`SIG_TYPE_W-1:0] TXR_META_TYPE,
output TXR_META_EP,
input TXR_META_READY);
localparam C_DATA_DELAY = 6;
reg rMainState=`S_TXENGUPR128_MAIN_IDLE, _rMainState=`S_TXENGUPR128_MAIN_IDLE;
reg rCountIsWr=0, _rCountIsWr=0;
reg [9:0] rCountLen=0, _rCountLen=0;
reg [3:0] rCountChnl=0, _rCountChnl=0;
reg [C_TAG_WIDTH-1:0] rCountTag=0, _rCountTag=0;
reg [61:0] rCountAddr=62'd0, _rCountAddr=62'd0;
reg rCountAddr64=0, _rCountAddr64=0;
reg [9:0] rCount=0, _rCount=0;
reg rCountDone=0, _rCountDone=0;
reg rCountStart=0, _rCountStart=0;
reg rCountValid=0, _rCountValid=0;
reg [C_NUM_CHNL-1:0] rWrDataRen=0, _rWrDataRen=0;
reg rTxEngRdReqAck, _rTxEngRdReqAck;
wire wRdReq;
wire [3:0] wRdReqChnl;
wire wWrReq;
wire [3:0] wWrReqChnl;
wire wRdAck;
wire [3:0] wCountChnl;
wire [11:0] wCountChnlShiftDW = (wCountChnl*C_PCI_DATA_WIDTH); // Mult can exceed 9 bits, so make this a wire
wire [63:0] wRdAddr;
wire [9:0] wRdLen;
wire [1:0] wRdSgChnl;
wire [63:0] wWrAddr;
wire [9:0] wWrLen;
wire [C_PCI_DATA_WIDTH-1:0] wWrData;
wire [C_PCI_DATA_WIDTH-1:0] wWrDataSwap;
reg [3:0] rRdChnl=0, _rRdChnl=0;
reg [61:0] rRdAddr=62'd0, _rRdAddr=62'd0;
reg [9:0] rRdLen=0, _rRdLen=0;
reg [1:0] rRdSgChnl=0, _rRdSgChnl=0;
reg [3:0] rWrChnl=0, _rWrChnl=0;
reg [61:0] rWrAddr=62'd0, _rWrAddr=62'd0;
reg [9:0] rWrLen=0, _rWrLen=0;
reg [C_PCI_DATA_WIDTH-1:0] rWrData={C_PCI_DATA_WIDTH{1'd0}}, _rWrData={C_PCI_DATA_WIDTH{1'd0}};
assign wRdAddr = RD_ADDR[wRdReqChnl * `SIG_ADDR_W +: `SIG_ADDR_W];
assign wRdLen = RD_LEN[wRdReqChnl * `SIG_LEN_W +: `SIG_LEN_W];
assign wRdSgChnl = RD_SG_CHNL[wRdReqChnl * 2 +: 2];
assign wWrAddr = WR_ADDR[wWrReqChnl * `SIG_ADDR_W +: `SIG_ADDR_W];
assign wWrLen = WR_LEN[wWrReqChnl * `SIG_LEN_W +: `SIG_LEN_W];
assign wWrData = WR_DATA[wCountChnl * C_PCI_DATA_WIDTH +: C_PCI_DATA_WIDTH];
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [3:0] rCapState=`S_TXENGUPR128_CAP_RD_WR, _rCapState=`S_TXENGUPR128_CAP_RD_WR;
reg [C_NUM_CHNL-1:0] rRdAck=0, _rRdAck=0;
reg [C_NUM_CHNL-1:0] rWrAck=0, _rWrAck=0;
reg rIsWr=0, _rIsWr=0;
reg [5:0] rCapChnl=0, _rCapChnl=0;
reg [61:0] rCapAddr=62'd0, _rCapAddr=62'd0;
reg rCapAddr64=0, _rCapAddr64=0;
reg [9:0] rCapLen=0, _rCapLen=0;
reg rCapIsWr=0, _rCapIsWr=0;
reg rExtTagReq=0, _rExtTagReq=0;
reg [C_TAG_WIDTH-1:0] rExtTag=0, _rExtTag=0;
reg [C_DATA_DELAY-1:0] rWnR=0, _rWnR=0;
reg [(C_DATA_DELAY*4)-1:0] rChnl=0, _rChnl=0;
reg [(C_DATA_DELAY*8)-1:0] rTag=0, _rTag=0;
reg [(C_DATA_DELAY*62)-1:0] rAddr=0, _rAddr=0;
reg [C_DATA_DELAY-1:0] rAddr64=0, _rAddr64=0;
reg [(C_DATA_DELAY*10)-1:0] rLen=0, _rLen=0;
reg [C_DATA_DELAY-1:0] rLenEQ1=0, _rLenEQ1=0;
reg [C_DATA_DELAY-1:0] rValid=0, _rValid=0;
reg [C_DATA_DELAY-1:0] rDone=0, _rDone=0;
reg [C_DATA_DELAY-1:0] rStart=0, _rStart=0;
assign WR_DATA_REN = rWrDataRen;
assign WR_ACK = rWrAck;
assign RD_ACK = rRdAck;
assign INT_TAG = {rRdSgChnl, rRdChnl};
assign INT_TAG_VALID = rExtTagReq;
assign TX_ENG_RD_REQ_SENT = rTxEngRdReqAck;
assign wRdAck = (wRdReq & EXT_TAG_VALID & RXBUF_SPACE_AVAIL);
// Search for the next request so that we can move onto it immediately after
// the current channel has released its request.
tx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selRd (.RST(RST_IN), .CLK(CLK), .REQ_ALL(RD_REQ), .REQ(wRdReq), .CHNL(wRdReqChnl));
tx_engine_selector #(.C_NUM_CHNL(C_NUM_CHNL)) selWr (.RST(RST_IN), .CLK(CLK), .REQ_ALL(WR_REQ), .REQ(wWrReq), .CHNL(wWrReqChnl));
// Buffer shift-selected channel request signals and FIFO data.
always @ (posedge CLK) begin
rRdChnl <= #1 _rRdChnl;
rRdAddr <= #1 _rRdAddr;
rRdLen <= #1 _rRdLen;
rRdSgChnl <= #1 _rRdSgChnl;
rWrChnl <= #1 _rWrChnl;
rWrAddr <= #1 _rWrAddr;
rWrLen <= #1 _rWrLen;
rWrData <= #1 _rWrData;
end
always @ (*) begin
_rRdChnl = wRdReqChnl;
_rRdAddr = wRdAddr[63:2];
_rRdLen = wRdLen;
_rRdSgChnl = wRdSgChnl;
_rWrChnl = wWrReqChnl;
_rWrAddr = wWrAddr[63:2];
_rWrLen = wWrLen;
_rWrData = wWrData;
end
// Accept requests when the selector indicates. Capture the buffered
// request parameters for hand-off to the formatting pipeline. Then
// acknowledge the receipt to the channel so it can deassert the
// request, and let the selector choose another channel.
always @ (posedge CLK) begin
rCapState <= #1 (RST_IN ? `S_TXENGUPR128_CAP_RD_WR : _rCapState);
rRdAck <= #1 (RST_IN ? {C_NUM_CHNL{1'd0}} : _rRdAck);
rWrAck <= #1 (RST_IN ? {C_NUM_CHNL{1'd0}} : _rWrAck);
rIsWr <= #1 _rIsWr;
rCapChnl <= #1 _rCapChnl;
rCapAddr <= #1 _rCapAddr;
rCapAddr64 <= #1 _rCapAddr64;
rCapLen <= #1 _rCapLen;
rCapIsWr <= #1 _rCapIsWr;
rExtTagReq <= #1 _rExtTagReq;
rExtTag <= #1 _rExtTag;
rTxEngRdReqAck <= #1 _rTxEngRdReqAck;
end
always @ (*) begin
_rCapState = rCapState;
_rRdAck = rRdAck;
_rWrAck = rWrAck;
_rIsWr = rIsWr;
_rCapChnl = rCapChnl;
_rCapAddr = rCapAddr;
_rCapAddr64 = rCapAddr64;
_rCapLen = rCapLen;
_rCapIsWr = rCapIsWr;
_rExtTagReq = rExtTagReq;
_rExtTag = rExtTag;
_rTxEngRdReqAck = rTxEngRdReqAck;
case (rCapState)
`S_TXENGUPR128_CAP_RD_WR : begin
_rIsWr = !wRdReq;
_rRdAck = ((wRdAck)<<wRdReqChnl);
_rTxEngRdReqAck = wRdAck;
_rExtTagReq = wRdAck;
_rCapState = (wRdAck ? `S_TXENGUPR128_CAP_CAP : `S_TXENGUPR128_CAP_WR_RD);
end
`S_TXENGUPR128_CAP_WR_RD : begin
_rIsWr = wWrReq;
_rWrAck = (wWrReq<<wWrReqChnl);
_rCapState = (wWrReq ? `S_TXENGUPR128_CAP_CAP : `S_TXENGUPR128_CAP_RD_WR);
end
`S_TXENGUPR128_CAP_CAP : begin
_rTxEngRdReqAck = 0;
_rRdAck = 0;
_rWrAck = 0;
_rCapIsWr = rIsWr;
_rExtTagReq = 0;
_rExtTag = EXT_TAG ^ {rIsWr,{(C_TAG_WIDTH-1){1'b0}}};
if (rIsWr) begin
_rCapChnl = {2'd0, rWrChnl};
_rCapAddr = rWrAddr;
_rCapAddr64 = (rWrAddr[61:30] != 0);
_rCapLen = rWrLen;
end
else begin
_rCapChnl = {rRdSgChnl, rRdChnl};
_rCapAddr = rRdAddr;
_rCapAddr64 = (rRdAddr[61:30] != 0);
_rCapLen = rRdLen;
end
_rCapState = `S_TXENGUPR128_CAP_REL;
end
`S_TXENGUPR128_CAP_REL : begin
// Push into the formatting pipeline when ready
if (TXR_META_READY & !rMainState) begin // S_TXENGUPR128_MAIN_IDLE
_rCapState = (`S_TXENGUPR128_CAP_WR_RD>>(rCapIsWr)); // Changes to S_TXENGUPR128_CAP_RD_WR
end
end
default : begin
_rCapState = `S_TXENGUPR128_CAP_RD_WR;
end
endcase
end
// Start the read/write when space is available in the output FIFO and when
// request parameters have been captured (i.e. a pending request).
always @ (posedge CLK) begin
rMainState <= #1 (RST_IN ? `S_TXENGUPR128_MAIN_IDLE : _rMainState);
rCountIsWr <= #1 _rCountIsWr;
rCountLen <= #1 _rCountLen;
rCountChnl <= #1 _rCountChnl;
rCountTag <= #1 _rCountTag;
rCountAddr <= #1 _rCountAddr;
rCountAddr64 <= #1 _rCountAddr64;
rCount <= #1 _rCount;
rCountDone <= #1 _rCountDone;
rCountStart <= #1 _rCountStart;
rCountValid <= #1 _rCountValid;
rWrDataRen <= #1 _rWrDataRen;
end
always @ (*) begin
_rMainState = rMainState;
_rCountIsWr = rCountIsWr;
_rCountLen = rCountLen;
_rCountChnl = rCountChnl;
_rCountTag = rCountTag;
_rCountAddr = rCountAddr;
_rCountAddr64 = rCountAddr64;
_rCount = rCount;
_rCountDone = rCountDone;
_rCountValid = rCountValid;
_rWrDataRen = rWrDataRen;
_rCountStart = 0;
case (rMainState)
`S_TXENGUPR128_MAIN_IDLE : begin
_rCountIsWr = rCapIsWr;
_rCountLen = rCapLen;
_rCountChnl = rCapChnl[3:0];
_rCountTag = rExtTag;
_rCountAddr = rCapAddr;
_rCountAddr64 = rCapAddr64;
_rCount = rCapLen;
_rCountDone = (rCapLen <= 3'd4);
_rWrDataRen = ((TXR_META_READY & rCapState[3] & rCapIsWr)<<(rCapChnl[3:0])); // S_TXENGUPR128_CAP_REL
_rCountValid = (TXR_META_READY & rCapState[3]);
_rCountStart = (TXR_META_READY & rCapState[3]);
if (TXR_META_READY && rCapState[3] && rCapIsWr && (rCapAddr64 || (rCapLen != 10'd1))) // S_TXENGUPR128_CAP_REL
_rMainState = `S_TXENGUPR128_MAIN_WR;
end
`S_TXENGUPR128_MAIN_WR : begin
_rCount = rCount - 3'd4;
_rCountDone = (rCount <= 4'd8);
if (rCountDone) begin
_rWrDataRen = 0;
_rCountValid = 0;
_rMainState = `S_TXENGUPR128_MAIN_IDLE;
end
end
endcase
end
// Shift in the captured parameters and valid signal every cycle.
// This pipeline will keep the formatter busy.
assign wCountChnl = rChnl[(C_DATA_DELAY-2)*4 +:4];
always @ (posedge CLK) begin
rWnR <= #1 _rWnR;
rChnl <= #1 _rChnl;
rTag <= #1 _rTag;
rAddr <= #1 _rAddr;
rAddr64 <= #1 _rAddr64;
rLen <= #1 _rLen;
rLenEQ1 <= #1 _rLenEQ1;
rValid <= #1 _rValid;
rDone <= #1 _rDone;
rStart <= #1 _rStart;
end
always @ (*) begin
_rWnR = {rWnR[((C_DATA_DELAY-1)*1)-1:0], rCountIsWr};
_rChnl = {rChnl[((C_DATA_DELAY-1)*4)-1:0], rCountChnl};
_rTag = {rTag[((C_DATA_DELAY-1)*8)-1:0], (8'd0 | rCountTag)};
_rAddr = {rAddr[((C_DATA_DELAY-1)*62)-1:0], rCountAddr};
_rAddr64 = {rAddr64[((C_DATA_DELAY-1)*1)-1:0], rCountAddr64};
_rLen = {rLen[((C_DATA_DELAY-1)*10)-1:0], rCountLen};
_rLenEQ1 = {rLenEQ1[((C_DATA_DELAY-1)*1)-1:0], (rCountLen == 10'd1)};
_rValid = {rValid[((C_DATA_DELAY-1)*1)-1:0], rCountValid & rCountIsWr};
_rDone = {rDone[((C_DATA_DELAY-1)*1)-1:0], rCountDone};
_rStart = {rStart[((C_DATA_DELAY-1)*1)-1:0], rCountStart};
end // always @ begin
assign TXR_DATA = rWrData;
assign TXR_DATA_VALID = rValid[(C_DATA_DELAY-1)*1 +:1];
assign TXR_DATA_START_FLAG = rStart[(C_DATA_DELAY-1)*1 +:1];
assign TXR_DATA_START_OFFSET = 0;
assign TXR_DATA_END_FLAG = rDone[(C_DATA_DELAY-1)*1 +:1];
assign TXR_DATA_END_OFFSET = rLen[(C_DATA_DELAY-1)*10 +:`SIG_OFFSET_W] - 1;
assign TXR_META_VALID = rCountStart;
assign TXR_META_TYPE = rCountIsWr ? `TRLS_REQ_WR : `TRLS_REQ_RD;
assign TXR_META_ADDR = {rCountAddr,2'b00};
assign TXR_META_LENGTH = rCountLen;
assign TXR_META_LDWBE = rCountLen == 10'd1 ? 0 : 4'b1111;
assign TXR_META_FDWBE = 4'b1111;
assign TXR_META_TAG = rCountTag;
assign TXR_META_EP = 1'b0;
assign TXR_META_ATTR = 3'b110;
assign TXR_META_TC = 0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLRTN_SYMBOL_V
`define SKY130_FD_SC_HDLL__DLRTN_SYMBOL_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__dlrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLRTN_SYMBOL_V
|
//
// (c) Copyright 2010 - 2014 Xilinx, Inc. All rights reserved.
//
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
`default_nettype wire
`timescale 1ns / 1ps
`define DLY #1
(* DowngradeIPIdentifiedWarnings = "yes" *)
//***************************** Entity Declaration ****************************
module srio_gen2_0_k7_v7_gtxe2_common
#(
// Simulation attributes
parameter WRAPPER_SIM_GTRESET_SPEEDUP = "TRUE", // Set to "true" to speed up sim reset
parameter RX_DFE_KL_CFG2_IN = 32'h3010D90C,
parameter PMA_RSV_IN = 32'h00018480,
parameter SIM_VERSION = "4.0"
)
(
input gt0_gtrefclk0_common_in , // connect to refclk
input gt0_qplllockdetclk_in , // connect to drpclk
input gt0_qpllreset_in , // connect to gt_pcs_rst
output qpll_clk_out ,
output qpll_out_refclk_out ,
output gt0_qpll_lock_out // use only when 2x or 4x or 6g
); //_________________________________________________________________________
//_________________________________________________________________________
//_________________________GTXE2_COMMON____________________________________
// ground and vcc signals
// 8/23/2013
parameter QPLL_FBDIV_TOP = 40;
parameter QPLL_FBDIV_IN = (QPLL_FBDIV_TOP == 16) ? 10'b0000100000 :
(QPLL_FBDIV_TOP == 20) ? 10'b0000110000 :
(QPLL_FBDIV_TOP == 32) ? 10'b0001100000 :
(QPLL_FBDIV_TOP == 40) ? 10'b0010000000 :
(QPLL_FBDIV_TOP == 64) ? 10'b0011100000 :
(QPLL_FBDIV_TOP == 66) ? 10'b0101000000 :
(QPLL_FBDIV_TOP == 80) ? 10'b0100100000 :
(QPLL_FBDIV_TOP == 100) ? 10'b0101110000 : 10'b0000000000;
parameter QPLL_FBDIV_RATIO = (QPLL_FBDIV_TOP == 16) ? 1'b1 :
(QPLL_FBDIV_TOP == 20) ? 1'b1 :
(QPLL_FBDIV_TOP == 32) ? 1'b1 :
(QPLL_FBDIV_TOP == 40) ? 1'b1 :
(QPLL_FBDIV_TOP == 64) ? 1'b1 :
(QPLL_FBDIV_TOP == 66) ? 1'b0 :
(QPLL_FBDIV_TOP == 80) ? 1'b1 :
(QPLL_FBDIV_TOP == 100) ? 1'b1 : 1'b1;
wire tied_to_ground_i;
wire [63:0] tied_to_ground_vec_i;
wire tied_to_vcc_i;
wire [63:0] tied_to_vcc_vec_i;
assign tied_to_ground_i = 1'b0;
assign tied_to_ground_vec_i = 64'h0000000000000000;
assign tied_to_vcc_i = 1'b1;
assign tied_to_vcc_vec_i = 64'hffffffffffffffff;
GTXE2_COMMON #
(
// Simulation attributes
.SIM_RESET_SPEEDUP (WRAPPER_SIM_GTRESET_SPEEDUP),
.SIM_QPLLREFCLK_SEL (3'b001),
.SIM_VERSION (SIM_VERSION),
//----------------COMMON BLOCK Attributes---------------
.BIAS_CFG (64'h0000040000001000),
.COMMON_CFG (32'h00000000),
.QPLL_CFG (27'h06801C1),
.QPLL_CLKOUT_CFG (4'b0000),
.QPLL_COARSE_FREQ_OVRD (6'b010000),
.QPLL_COARSE_FREQ_OVRD_EN (1'b0),
.QPLL_CP (10'b0000011111),
.QPLL_CP_MONITOR_EN (1'b0),
.QPLL_DMONITOR_SEL (1'b0),
.QPLL_FBDIV (QPLL_FBDIV_IN),
.QPLL_FBDIV_MONITOR_EN (1'b0),
.QPLL_FBDIV_RATIO (QPLL_FBDIV_RATIO),
.QPLL_INIT_CFG (24'h000006),
.QPLL_LOCK_CFG (16'h21E8),
.QPLL_LPF (4'b1111),
.QPLL_REFCLK_DIV (1)
)
gtxe2_common_0_i
(
//----------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
.DRPADDR (tied_to_ground_vec_i[7:0]),
.DRPCLK (tied_to_ground_i),
.DRPDI (tied_to_ground_vec_i[15:0]),
.DRPDO (),
.DRPEN (tied_to_ground_i),
.DRPRDY (),
.DRPWE (tied_to_ground_i),
//-------------------- Common Block - Ref Clock Ports ---------------------
.GTGREFCLK (tied_to_ground_i),
.GTNORTHREFCLK0 (tied_to_ground_i),
.GTNORTHREFCLK1 (tied_to_ground_i),
.GTREFCLK0 (gt0_gtrefclk0_common_in),
.GTREFCLK1 (tied_to_ground_i),
.GTSOUTHREFCLK0 (tied_to_ground_i),
.GTSOUTHREFCLK1 (tied_to_ground_i),
//----------------------- Common Block - QPLL Ports -----------------------
.QPLLDMONITOR (),
//--------------------- Common Block - Clocking Ports ----------------------
.QPLLOUTCLK (qpll_clk_out),
.QPLLOUTREFCLK (qpll_out_refclk_out),
.REFCLKOUTMONITOR (),
//----------------------- Common Block - QPLL Ports ------------------------
.QPLLFBCLKLOST (),
.QPLLLOCK (gt0_qpll_lock_out),
.QPLLLOCKDETCLK (gt0_qplllockdetclk_in),
.QPLLLOCKEN (tied_to_vcc_i),
.QPLLOUTRESET (tied_to_ground_i),
.QPLLPD (tied_to_vcc_i),
.QPLLREFCLKLOST (),
.QPLLREFCLKSEL (3'b001),
.QPLLRESET (gt0_qpllreset_in),
.QPLLRSVD1 (16'b0000000000000000),
.QPLLRSVD2 (5'b11111),
//------------------------------- QPLL Ports -------------------------------
.BGBYPASSB (tied_to_vcc_i),
.BGMONITORENB (tied_to_vcc_i),
.BGPDB (tied_to_vcc_i),
.BGRCALOVRD (5'b00000),
.PMARSVD (8'b00000000),
.RCALENB (tied_to_vcc_i)
);
endmodule
|
Require Export Coq.Program.Tactics.
Require Export Coq.Setoids.Setoid.
Require Export Coq.Classes.Morphisms.
Require Export Coq.Arith.Arith_base.
Require Export Coq.Relations.Relations.
Require Export Coq.Lists.List.
Import EqNotations.
Import ListNotations.
(***
*** Ordered Types = Types with a PreOrder
***)
Record OType : Type :=
{
ot_Type :> Type;
ot_R : relation ot_Type;
ot_PreOrder :> PreOrder ot_R
}.
Instance OType_Reflexive (A:OType) : Reflexive (ot_R A).
Proof.
destruct A; auto with typeclass_instances.
Qed.
Instance OType_Transitive (A:OType) : Transitive (ot_R A).
Proof.
destruct A; auto with typeclass_instances.
Qed.
(* The equivalence relation for an OrderedType *)
Definition ot_equiv (A:OType) : relation A :=
fun x y => ot_R A x y /\ ot_R A y x.
Instance ot_equiv_Equivalence A : Equivalence (ot_equiv A).
Proof.
constructor; intro; intros.
{ split; reflexivity. }
{ destruct H; split; assumption. }
{ destruct H; destruct H0; split; transitivity y; assumption. }
Qed.
(***
*** Commonly-Used Ordered Types
***)
(* The ordered type of propositions *)
Program Definition OTProp : OType :=
{|
ot_Type := Prop;
ot_R := Basics.impl;
|}.
Next Obligation.
constructor; auto with typeclass_instances.
Qed.
(* The discrete ordered type, where things are only related to themselves *)
Program Definition OTdiscrete (A:Type) : OType :=
{|
ot_Type := A;
ot_R := eq;
|}.
(* The only ordered type over unit is the discrete one *)
Definition OTunit : OType := OTdiscrete unit.
(* The ordered type of natural numbers using <= *)
Program Definition OTnat : OType :=
{|
ot_Type := nat;
ot_R := le;
|}.
(* Flip the ordering of an OType *)
Program Definition OTflip (A:OType) : OType :=
{|
ot_Type := ot_Type A;
ot_R := fun x y => ot_R A y x
|}.
Next Obligation.
constructor.
{ intro x. reflexivity. }
{ intros x y z; transitivity y; assumption. }
Qed.
(* The pointwise relation on pairs *)
Definition pairR {A B} (RA:relation A) (RB:relation B) : relation (A*B) :=
fun p1 p2 => RA (fst p1) (fst p2) /\ RB (snd p1) (snd p2).
Instance PreOrder_pairR A B RA RB
`(PreOrder A RA) `(PreOrder B RB) : PreOrder (pairR RA RB).
Proof.
constructor.
{ intro p; split; reflexivity. }
{ intros p1 p2 p3 R12 R23; destruct R12; destruct R23; split.
- transitivity (fst p2); assumption.
- transitivity (snd p2); assumption. }
Qed.
(* The non-dependent product ordered type, where pairs are related pointwise *)
Definition OTpair (A B:OType) : OType :=
{|
ot_Type := ot_Type A * ot_Type B;
ot_R := pairR (ot_R A) (ot_R B);
ot_PreOrder := PreOrder_pairR A B _ _ (ot_PreOrder A) (ot_PreOrder B)
|}.
(* The sort-of pointwise relation on sum types *)
Inductive sumR {A B} (RA:relation A) (RB:relation B) : A+B -> A+B -> Prop :=
| sumR_inl a1 a2 : RA a1 a2 -> sumR RA RB (inl a1) (inl a2)
| sumR_inr b1 b2 : RB b1 b2 -> sumR RA RB (inr b1) (inr b2).
Instance PreOrder_sumR A B RA RB
`(PreOrder A RA) `(PreOrder B RB) : PreOrder (sumR RA RB).
Proof.
constructor.
{ intro s; destruct s; constructor; reflexivity. }
{ intros s1 s2 s3 R12 R23. destruct R12; inversion R23.
- constructor; transitivity a2; assumption.
- constructor; transitivity b2; assumption. }
Qed.
(*
Definition sumR {A B} (RA:relation A) (RB:relation B) : relation (A+B) :=
fun sum1 sum2 =>
match sum1, sum2 with
| inl x, inl y => RA x y
| inl x, inr y => False
| inr x, inl y => False
| inr x, inr y => RB x y
end.
Instance PreOrder_sumR A B RA RB
`(PreOrder A RA) `(PreOrder B RB) : PreOrder (sumR RA RB).
Proof.
constructor.
{ intro s; destruct s; simpl; reflexivity. }
{ intros s1 s2 s3 R12 R23.
destruct s1; destruct s2; destruct s3;
try (elimtype False; assumption); simpl.
- transitivity a0; assumption.
- transitivity b0; assumption. }
Qed.
*)
(* The non-dependent sum ordered type, where objects are only related if they
are both "left"s or both "right"s *)
Definition OTsum (A B : OType) : OType :=
{|
ot_Type := ot_Type A + ot_Type B;
ot_R := sumR (ot_R A) (ot_R B);
ot_PreOrder := PreOrder_sumR _ _ _ _ (ot_PreOrder A) (ot_PreOrder B)
|}.
(* NOTE: the following definition requires everything above to be polymorphic *)
(* NOTE: The definition we choose for OTType is actually deep: instead of
requiring ot_Type A = ot_Type B, we could just require a coercion function from
ot_Type A to ot_Type B, which would yield something more like HoTT... though
maybe it wouldn't work unless we assumed the HoTT axiom? As it is, we might need
UIP to hold if we want to use the definition given here... *)
(*
Program Definition OTType : OType :=
{|
ot_Type := OType;
ot_R := (fun A B =>
exists (e:ot_Type A = ot_Type B),
forall (x y:A),
ot_R A x y ->
ot_R B (rew [fun A => A] e in x)
(rew [fun A => A] e in y));
|}.
*)
(***
*** The Ordered Type for Functions
***)
(* The type of continuous, i.e. Proper, functions between ordered types *)
Record Pfun (A B:OType) :=
{
pfun_app : ot_Type A -> ot_Type B;
pfun_Proper :> Proper (ot_R A ==> ot_R B) pfun_app
}.
Arguments pfun_app [_ _] _ _.
Arguments pfun_Proper [_ _] _ _ _ _.
(* Infix "@" := pfun_app (at level 50). *)
(* The non-dependent function ordered type *)
Definition OTarrow_R (A B : OType) : relation (Pfun A B) :=
fun f g =>
forall a1 a2, ot_R A a1 a2 -> ot_R B (pfun_app f a1) (pfun_app g a2).
Program Definition OTarrow (A B:OType) : OType :=
{|
ot_Type := Pfun A B;
ot_R := OTarrow_R A B;
|}.
Next Obligation.
constructor.
{ intros f; apply (pfun_Proper f). }
{ intros f g h Rfg Rgh a1 a2 Ra. transitivity (pfun_app g a1).
- apply (Rfg a1 a1). reflexivity.
- apply Rgh; assumption. }
Qed.
(* Curry a Pfun *)
Program Definition pfun_curry {A B C} (pfun : Pfun (OTpair A B) C)
: Pfun A (OTarrow B C) :=
{| pfun_app :=
fun a =>
{| pfun_app := fun b => pfun_app pfun (a,b);
pfun_Proper := _ |};
pfun_Proper := _ |}.
Next Obligation.
Proof.
intros b1 b2 Rb. apply pfun_Proper.
split; [ reflexivity | assumption ].
Qed.
Next Obligation.
Proof.
intros a1 a2 Ra b1 b2 Rb; simpl.
apply pfun_Proper; split; assumption.
Qed.
(* Uncrry a Pfun *)
Program Definition pfun_uncurry {A B C} (pfun : Pfun A (OTarrow B C))
: Pfun (OTpair A B) C :=
{| pfun_app :=
fun ab => pfun_app (pfun_app pfun (fst ab)) (snd ab);
pfun_Proper := _ |}.
Next Obligation.
Proof.
intros ab1 ab2 Rab. destruct Rab as [ Ra Rb ].
exact (pfun_Proper pfun (fst ab1) (fst ab2) Ra (snd ab1) (snd ab2) Rb).
Qed.
(* Currying and uncurrying of pfuns form an adjunction *)
(* FIXME: figure out the simplest way of stating this adjunction *)
(* OTarrow is right adjoint to OTpair, meaning that (OTarrow (OTpair A B) C) is
isomorphic to (OTarrow A (OTarrow B C)). The following is the first part of this
isomorphism, mapping left-to-right. *)
(* FIXME: could also do a forall type, but need the second type argument, B, to
itself be proper, i.e., to be an element of OTarrow A OType. Would also need a
dependent version of OTContext, below. *)
(* pfun_app is always Proper *)
Instance Proper_pfun_app A B :
Proper (ot_R (OTarrow A B) ==> ot_R A ==> ot_R B) (@pfun_app A B).
Proof.
intros f1 f2 Rf a1 a2 Ra. apply Rf; assumption.
Qed.
(* pfun_app is always Proper w.r.t. ot_equiv *)
Instance Proper_pfun_app_equiv A B :
Proper (ot_equiv (OTarrow A B) ==> ot_equiv A ==> ot_equiv B) (@pfun_app A B).
Proof.
intros f1 f2 Rf a1 a2 Ra; destruct Rf; destruct Ra.
split; apply Proper_pfun_app; assumption.
Qed.
(***
*** Ordered Type Functions
***)
(*
Class OTypeF (TF: forall `(A:OType), Type) : Type :=
otypef_app : forall `(A:OType), OType (TF A).
Arguments otypef_app [TF] _ [T] A _ _.
Instance OType_OTypeF_app `(F:OTypeF) `(A:OType) : OType (TF _ A) := otypef_app _ A.
Class ValidOTypeF `(F:OTypeF) : Prop :=
{
otypef_app_PreOrder :>
forall `(A:OType) {_:ValidOType A}, PreOrder (ot_R (otypef_app F A))
}.
Instance ValidOType_OTypeF_app `(ValidOTypeF) `(ValidOType) :
ValidOType (otypef_app F A).
Proof.
constructor. typeclasses eauto.
Qed.
*)
(***
*** Finding and Instantiating Ordered Types
***)
(* States that A is the default OType for type AU. We expect that AU = ot_Type
A, though the below only implies that A is isomorphic to AU w.r.t. RU. *)
Class OTForType (A:OType) {AU} (RU:relation AU) : Type :=
{
ot_lift_iso : AU -> A;
ot_lift_iso_Proper : Proper (RU ==> ot_R A) ot_lift_iso;
ot_unlift_iso : A -> AU;
ot_unlift_iso_Proper : Proper (ot_R A ==> RU) ot_unlift_iso;
ot_for_type_PreOrder :> PreOrder RU;
ot_lift_unlift_iso : forall x, ot_unlift_iso (ot_lift_iso x) = x;
ot_unlift_lift_iso : forall x, ot_lift_iso (ot_unlift_iso x) = x;
}.
Instance OTForType_refl (A:OType) : OTForType A (ot_R A) :=
{
ot_lift_iso := fun a => a;
ot_lift_iso_Proper := fun a1 a2 Ra => Ra;
ot_unlift_iso := fun a => a;
ot_unlift_iso_Proper := fun a1 a2 Ra => Ra;
ot_for_type_PreOrder := ot_PreOrder A;
ot_unlift_lift_iso := fun a => eq_refl;
ot_lift_unlift_iso := fun a => eq_refl;
}.
(* Hint to use OTForType_refl if AU unifies with (ot_Type A), even if it is not
syntactically equal to (ot_Type A) *)
Hint Extern 1 (OTForType _ _) => apply OTForType_refl : typeclass_instances.
(* The default OType for Prop is OTProp *)
Instance OTForType_OTProp : OTForType OTProp Basics.impl := OTForType_refl _.
(* The default OType for a pair is OTpair of the defaults for the two types *)
Program Instance OTForType_pair A AU RAU B BU RBU
(otA:@OTForType A AU RAU) (otB:@OTForType B BU RBU) :
OTForType (OTpair A B) (pairR RAU RBU) :=
{|
ot_lift_iso :=
fun p => (ot_lift_iso (fst p), ot_lift_iso (snd p));
ot_unlift_iso := fun p => (ot_unlift_iso (fst p), ot_unlift_iso (snd p));
|}.
Next Obligation.
intros p1 p2 Rp; destruct Rp.
split; simpl; apply ot_lift_iso_Proper; assumption.
Qed.
Next Obligation.
intros p1 p2 Rp; destruct Rp.
split; simpl; apply ot_unlift_iso_Proper; assumption.
Qed.
Next Obligation.
repeat rewrite ot_lift_unlift_iso. reflexivity.
Qed.
Next Obligation.
repeat rewrite ot_unlift_lift_iso. reflexivity.
Qed.
(* The default OType for a sum is OTsum of the defaults for the two types *)
Program Instance OTForType_sum A AU RAU B BU RBU
(otA:@OTForType A AU RAU) (otB:@OTForType B BU RBU) :
OTForType (OTsum A B) (sumR RAU RBU) :=
{|
ot_lift_iso :=
fun s =>
match s with
| inl a => inl (ot_lift_iso a)
| inr b => inr (ot_lift_iso b)
end;
ot_unlift_iso :=
fun s =>
match s with
| inl a => inl (ot_unlift_iso a)
| inr b => inr (ot_unlift_iso b)
end;
|}.
Next Obligation.
intros s1 s2 Rs.
destruct Rs; constructor; apply ot_lift_iso_Proper; assumption.
Qed.
Next Obligation.
intros s1 s2 Rs.
destruct Rs; constructor; apply ot_unlift_iso_Proper; assumption.
Qed.
Next Obligation.
destruct x; rewrite ot_lift_unlift_iso; reflexivity.
Qed.
Next Obligation.
destruct x; rewrite ot_unlift_lift_iso; reflexivity.
Qed.
(* States that A is a valid OType for the Proper elements of AU *)
Class OTForRel (A:OType) {AU} (RU:relation AU) : Type :=
{
ot_lift : forall a, Proper RU a -> A;
ot_lift_Proper :
forall a1 a2 prp1 prp2,
RU a1 a2 -> ot_R A (ot_lift a1 prp1) (ot_lift a2 prp2);
ot_unlift : A -> AU;
ot_unlift_Proper : Proper (ot_R A ==> RU) ot_unlift;
ot_lift_unlift_R : forall a prp, RU a (ot_unlift (ot_lift a prp));
ot_unlift_lift :
forall a prp, ot_equiv A (ot_lift (ot_unlift a) prp) a;
(* NOTE: the case for RU is more complex since it may not be transitive *)
ot_lift_unlift1 :
forall a' a prp, RU a' a <-> RU a' (ot_unlift (ot_lift a prp));
ot_lift_unlift2 :
forall a' a prp, RU a a' <-> RU (ot_unlift (ot_lift a prp)) a';
}.
Arguments OTForRel A {AU%type} RU%signature.
(*
Program Instance OTForRel_refl (A:OType) : OTForRel A (ot_R A) :=
{
ot_lift := fun a _ => a;
ot_lift_Proper := _;
ot_unlift := fun a => a;
}.
*)
(* If A is the default OType for AU and RU, then it is a valid OType for them *)
Program Instance OTForRel_OTForType A AU RU
(_:@OTForType A AU RU) : OTForRel A RU | 3 :=
{|
ot_lift := fun a _ => ot_lift_iso a;
ot_unlift := ot_unlift_iso;
|}.
Next Obligation.
apply ot_lift_iso_Proper. assumption.
Qed.
Next Obligation.
intros a1 a2 Ra; apply ot_unlift_iso_Proper; assumption.
Qed.
Next Obligation.
rewrite ot_lift_unlift_iso. reflexivity.
Qed.
Next Obligation.
rewrite ot_unlift_lift_iso. reflexivity.
Qed.
Next Obligation.
rewrite ot_lift_unlift_iso. reflexivity.
Qed.
Next Obligation.
rewrite ot_lift_unlift_iso. reflexivity.
Qed.
Program Instance OTForRel_fun (A B:OType) AU RAU BU RBU
(otA:@OTForType A AU RAU) (otB:@OTForRel B BU RBU) :
OTForRel (OTarrow A B) (RAU ==> RBU) :=
{|
ot_lift := fun f prp =>
{| pfun_app :=
fun a =>
ot_lift (OTForRel:=otB) (f (ot_unlift_iso a))
(prp _ _ (reflexivity _))|};
ot_lift_Proper := _;
ot_unlift := fun pfun a => ot_unlift (pfun_app pfun (ot_lift_iso a));
|}.
Next Obligation.
intros a1 a2 Ra. apply ot_lift_Proper. apply prp.
apply ot_unlift_iso_Proper. assumption.
Qed.
Next Obligation.
intros x1 x2 Rx. apply ot_lift_Proper. apply H.
apply ot_unlift_iso_Proper. assumption.
Qed.
Next Obligation.
intros f1 f2 Rf a1 a2 Ra. apply ot_unlift_Proper.
apply Rf. apply ot_lift_iso_Proper. assumption.
Qed.
Next Obligation.
intros a1 a2 Ra. apply ot_lift_unlift1. rewrite ot_lift_unlift_iso.
apply prp. assumption.
Qed.
Next Obligation.
split; intros a1 a2 Ra; simpl.
{ transitivity (pfun_app a (ot_lift_iso (ot_unlift_iso a1)));
[ apply (proj1 (ot_unlift_lift _ _))
| rewrite ot_unlift_lift_iso; apply pfun_Proper; assumption ]. }
{ transitivity (pfun_app a (ot_lift_iso (ot_unlift_iso a2)));
[ rewrite ot_unlift_lift_iso; apply pfun_Proper; assumption
| apply (proj2 (ot_unlift_lift _ _)) ]. }
Qed.
Next Obligation.
split; intros Ra' a1 a2 Ra.
{ apply ot_lift_unlift1. rewrite ot_lift_unlift_iso. apply Ra'; assumption. }
{ rewrite <- (ot_lift_unlift_iso a2).
refine (proj2 (ot_lift_unlift1 (a' a1) _ _) (Ra' _ _ _)); assumption. }
Qed.
Next Obligation.
split; intros Ra' a1 a2 Ra.
{ apply ot_lift_unlift2. rewrite ot_lift_unlift_iso. apply Ra'; assumption. }
{ rewrite <- (ot_lift_unlift_iso a1).
refine (proj2 (ot_lift_unlift2 (a' a2) _ _) (Ra' _ _ _)). assumption. }
Qed.
(* Tactic to prove OTForRel goals *)
Ltac prove_OTForRel :=
lazymatch goal with
| |- @OTForRel ?A (forall x:?AU, ?BU) ?RU =>
refine (OTForRel_fun _ _ _ _ _ _ _ _)
| |- @OTForRel (OTarrow ?A ?B) _ _ =>
apply OTForRel_fun
| |- @OTForRel _ _ _ => apply OTForRel_OTForType; try apply OTForType_refl
end.
(*
Ltac prove_OTForRel :=
lazymatch goal with
| |- @OTForRel (OTarrow ?A ?B) (forall x:?AU, ?BU) _ =>
let RBU := fresh "RBU" in
evar (RBU: forall (x:AU), relation BU);
assert (forall x, @OTForRel A BU (?RBU x)); [ intro x | ];
unfold RBU; clear RBU
| |- @OTForRel _ _ _ => apply OTForRel_OTForType
end.
*)
(* Hint to use the prove_OTForRel tactic; we need this because often the
relation part is an evar, so will not match any of the instances above *)
Hint Extern 2 (@OTForRel _ _ _) => prove_OTForRel : typeclass_instances.
(***
*** Building Ordered Terms
***)
Class OTHasType (A:OType) {AU} (RU:relation AU) (x y:AU) : Prop :=
{
ot_has_type : RU x y
}.
Arguments OTHasType A {AU%type} RU%signature x y.
Instance OTHasType_app (A:OType) AU RAU (B:OType) BU RBU
(fl fr:AU -> BU) argl argr
(otef:OTHasType (OTarrow A B) (RAU ==> RBU) fl fr)
(otea:OTHasType A RAU argl argr) :
OTHasType B RBU (fl argl) (fr argr) | 3.
Proof.
constructor.
apply (ot_has_type (OTHasType:=otef)).
apply ot_has_type.
Qed.
Instance OTHasType_pfun_app (A B:OType) (fl fr:OTarrow A B) argl argr
(otef:OTHasType (OTarrow A B) (ot_R (OTarrow A B)) fl fr)
(otea:OTHasType A (ot_R A) argl argr)
: OTHasType B (ot_R B) (pfun_app fl argl) (pfun_app fr argr) | 2.
Proof.
constructor.
apply (ot_has_type (OTHasType:=otef)).
apply (ot_has_type (OTHasType:=otea)).
Qed.
(* NOTE: We only want this to apply to terms that are syntactically lambdas, so
we use an Extern hint, below. *)
Definition OTHasType_lambda (A B:OType) AU RAU BU RBU
(fl fr:AU -> BU)
(pf: forall xl xr (pf:OTHasType A RAU xl xr),
OTHasType B RBU (fl xl) (fr xr)) :
OTHasType (OTarrow A B) (RAU ==> RBU) fl fr.
Proof.
constructor.
intros xl xr Rx; apply pf; constructor; assumption.
Qed.
(*
Ltac OTHasType_tac :=
lazymatch goal with
| |- OTHasType _ _ (fun x => ?f) (fun y => ?g) =>
eapply (OTHasType_lambda _ _ _ _ (fun x => f) (fun y => g))
| |- OTHasType _ _ (pfun_app ?f ?x) (pfun_app ?g ?y) =>
apply (OTHasType_pfun_app _ _ f g x y)
| |- OTHasType _ _ (?f ?x) (?g ?y) =>
eapply (OTHasType_app _ _ _ _ _ _ f g x y)
end.
Hint Extern 4 (OTHasType _ _ _ _) => OTHasType_tac : typeclass_instances.
*)
(* Hint to apply OTHasType_lambda on lambdas *)
Ltac try_OTHasType_lambda :=
lazymatch goal with
| |- @OTHasType _ _ _ (fun x => ?f) (fun y => ?g) =>
eapply (OTHasType_lambda _ _ _ _ _ _ (fun x => f) (fun y => g))
end.
Hint Extern 2 (@OTHasType _ _ _ (fun _ => _) (fun _ => _)) =>
try_OTHasType_lambda : typeclass_instances.
(* NOTE: this is not an instance because it is not syntax-driven, like our other
rules for OTHasType. Instead, this definition is used as a helper to build
other instances of OTHasType. *)
Definition OTHasType_Proper `{OTForRel} (x:AU) :
Proper RU x -> OTHasType A RU x x.
intros; constructor; assumption.
Defined.
Instance OTHasType_refl (A:OType) (x:A) : OTHasType A (ot_R A) x x.
Proof.
apply OTHasType_Proper. unfold Proper. reflexivity.
Defined.
(*
Instance OTHasType_refl_rel {T} (A:relation T) {vA:ValidOType A} (x:T)
: OTHasType A A x x := OTHasType_refl A x.
*)
Program Definition mkOTerm (A:OType) {AU RU}
{otfr:OTForRel A RU} (x:AU) {ht:@OTHasType A AU RU x x} : ot_Type A :=
ot_lift (OTForRel:=otfr) x ot_has_type.
Arguments mkOTerm A {AU%type RU%signature} {otfr} x {ht}.
Instance OTHasType_mkOTerm A AU RU x y otr htx hty (ht:@OTHasType A AU RU x y)
: OTHasType A (ot_R A) (@mkOTerm A AU RU otr x htx) (@mkOTerm A AU RU otr y hty).
Proof.
constructor. apply (ot_lift_Proper x y). apply ot_has_type.
Qed.
(***
*** OT Typing Rules for Common Operations
***)
(*
Instance OTHasType_Proper A AU R (x:AU)
{ote:OTForRel A R} {prp:Proper R x} :
OTHasType A R x x.
constructor; assumption.
Qed.
Instance Proper_fst A B : Proper (ot_R (OTpair A B) ==> ot_R A) fst.
Proof.
intros p1 p2 Rp; destruct Rp; assumption.
Qed.
Instance Proper_snd A B : Proper (ot_R (OTpair A B) ==> ot_R B) snd.
Proof.
intros p1 p2 Rp; destruct Rp; assumption.
Qed.
Instance Proper_pair A B : Proper (ot_R A ==> ot_R B ==> ot_R (OTpair A B)) pair.
Proof.
intros a1 a2 Ra b1 b2 Rb; split; assumption.
Qed.
*)
Instance OTHasType_fst A B :
OTHasType (OTarrow (OTpair A B) A) (pairR (ot_R A) (ot_R B) ==> ot_R A) fst fst.
Proof.
apply OTHasType_Proper.
intros p1 p2 Rp; destruct Rp; assumption.
Defined.
(*
Hint Extern 0 (@OTHasType _ _ fst fst) =>
apply OTHasType_fst : typeclass_instances.
*)
Instance OTHasType_snd A B :
OTHasType (OTarrow (OTpair A B) B) (ot_R (OTpair A B) ==> ot_R B) snd snd.
Proof.
apply OTHasType_Proper.
intros p1 p2 Rp; destruct Rp; assumption.
Defined.
(*
Hint Extern 0 (@OTHasType _ _ snd snd) =>
eapply OTHasType_snd : typeclass_instances.
*)
Instance OTHasType_pair A B :
OTHasType (OTarrow A (OTarrow B (OTpair A B)))
(ot_R A ==> ot_R B ==> ot_R (OTpair A B)) pair pair.
Proof.
apply OTHasType_Proper.
intros a1 a2 Ra b1 b2 Rb; split; assumption.
Defined.
(*
Hint Extern 0 (OTHasType _ _ pair pair) =>
apply OTHasType_pair : typeclass_instances.
*)
(***
*** Notations for Ordered Types
***)
Notation "A '-o>' B" :=
(OTarrow A B) (right associativity, at level 99).
Notation "A '*o*' B" :=
(OTpair A B) (left associativity, at level 40).
Notation "A '+o+' B" :=
(OTsum A B) (left associativity, at level 50).
Notation "'~o~' A" :=
(OTflip A) (right associativity, at level 35).
Notation "x <o= y" :=
(ot_R _ x y) (no associativity, at level 70).
Notation "x =o= y" :=
(ot_equiv _ x y) (no associativity, at level 70).
Notation "x @o@ y" :=
(pfun_app x y) (left associativity, at level 20).
(*
Notation "F @t@ A" :=
(otypef_app F A) (left associativity, at level 20).
*)
Definition ofst {A B} : A *o* B -o> A := mkOTerm _ fst.
Definition osnd {A B} : A *o* B -o> B := mkOTerm _ snd.
Definition opair {A B} : A -o> B -o> A *o* B := mkOTerm _ pair.
Notation "( x ,o, y )" :=
(opair @o@ x @o@ y)
(no associativity, at level 0).
(***
*** Automation for Ordered Terms
***)
Create HintDb OT.
(* Split ot_equiv equalities into the left and right cases *)
Definition prove_ot_equiv A (x y : ot_Type A)
(pf1: x <o= y) (pf2 : y <o= x) : x =o= y :=
conj pf1 pf2.
Hint Resolve prove_ot_equiv : OT.
(* Extensionality for ot_R *)
Definition ot_arrow_ext (A B:OType) (f1 f2 : A -o> B)
(pf:forall x y, x <o= y -> f1 @o@ x <o= f2 @o@ y) : f1 <o= f2 := pf.
Hint Resolve ot_arrow_ext : OT.
(* Application commutes with ot_lift *)
(* FIXME: don't use this! *)
(*
Definition ot_lift_apply (A B:OType) AU RAU BU RBU
(otfA:@OTForType A AU RAU) (otfB:@OTForRel B BU RBU)
(f:AU -> BU) prp arg :
ot_lift (OTForRel:=OTForRel_fun A B AU RAU BU RBU otfA otfB) f prp @o@ arg
= ot_lift (OTForRel:=otfB) (f (ot_unlift_iso arg)) (prp _ _ (reflexivity _))
:= eq_refl.
*)
(* ot_unlift_iso for OTForType_refl is just the identity *)
(* NOTE: also don't use this directly *)
(*
Lemma ot_unlift_iso_OTForType_refl_id (A:OType) x :
ot_unlift_iso (OTForType:=OTForType_refl A) x = x.
reflexivity.
Qed.
*)
(* Tactic to simplify ot_unlift_iso x to just x *)
(*
Ltac simpl_ot_unlift_iso :=
lazymatch goal with
| |- context ctx [@ot_unlift_iso _ _ _ (OTForType_refl ?A) ?x] =>
let new_goal := context ctx [x] in
change new_goal
end.
*)
(* Tactic to simplify mkOTerm x to just x *)
(*
Definition simpl_mkOTerm_refl A x ht :
mkOTerm (otfr:=OTForRel_OTForType _ _ _ (OTForType_refl A)) A x (ht:=ht) = x
:= eq_refl.
*)
Ltac simpl_mkOTerm_refl :=
lazymatch goal with
| |- context ctx [@mkOTerm
_ _ _
(OTForRel_OTForType _ _ _ (OTForType_refl _)) _ ?x _] =>
let new_goal := context ctx [x] in
change new_goal
end.
(* Application commutes with mkOTerm *)
(* NOTE: Don't use this directly; it is just here to inform the change tactic
used in prove_OT, below *)
(*
Definition mkOTerm_apply (A B:OType) AU RAU BU RBU
(otfA:@OTForType A AU RAU) (otfB:@OTForRel B BU RBU)
(f:AU -> BU) ht arg :
mkOTerm (A -o> B) (otfr:=OTForRel_fun A B AU RAU BU RBU otfA otfB)
f (ht:=ht) @o@ arg
=
mkOTerm B (otfr:=otfB)
(ht:=
{| ot_has_type :=
(ot_has_type (OTHasType:=ht)) _ _ (reflexivity _) |})
(f (ot_unlift_iso arg))
:= eq_refl.
*)
(* Tactic to simplify mkOTerm f @o@ x to f (ot_unlift_iso x) *)
Ltac simpl_mkOTerm_apply :=
lazymatch goal with
| |- context
ctx
[@mkOTerm
_ _ _
(OTForRel_fun ?A ?B ?AU ?RAU ?BU ?RBU (OTForType_refl _) ?otfB) ?f ?ht
@o@ ?arg] =>
let new_goal :=
context
ctx
[mkOTerm B (otfr:=otfB)
(ht:=
{| ot_has_type :=
(ot_has_type (OTHasType:=ht)) _ _ (reflexivity _) |})
(f arg)]
in change new_goal; cbv beta
(*
| |- context
ctx
[@mkOTerm
_ _ _
(OTForRel_fun ?A ?B ?AU ?RAU ?BU ?RBU ?otfA ?otfB) ?f ?ht
@o@ ?arg] =>
let new_goal :=
context
ctx
[mkOTerm B (otfr:=otfB)
(ht:=
{| ot_has_type :=
(ot_has_type (OTHasType:=ht)) _ _ (reflexivity _) |})
(f (ot_unlift_iso arg))]
in change new_goal; cbv beta
*)
end.
(* Add the above rules to the OT rewrite set *)
(* Hint Rewrite @mkOTerm_apply @ot_unlift_iso_OTForType_refl_id : OT. *)
(* Tactic to apply rewrites in the OT rewrite set *)
Ltac rewrite_OT := rewrite_strat (topdown (hints OT)).
(* General tactic to try to prove theorems about ordered terms *)
Ltac prove_OT :=
repeat first [simpl_mkOTerm_refl | simpl_mkOTerm_apply];
try rewrite_OT;
lazymatch goal with
| |- ot_equiv _ _ _ => split
| |- _ => idtac
end.
(* repeat (apply ot_arrow_ext; intros). *)
(***
*** Examples of Ordered Terms
***)
Module OTExamples.
Definition ex1 := mkOTerm (OTProp -o> OTProp) (fun p => p).
Eval compute in (ot_unlift ex1 : Prop -> Prop).
Definition ex2 {A} := mkOTerm (A -o> A) (fun p => p).
Eval simpl in (fun A:OType => ot_unlift (@ex2 A) : A -> A).
Definition ex2' {A} := mkOTerm (A -o> A -o> A) (fun p1 p2 => p1).
Eval simpl in (fun A:OType => ot_unlift (@ex2' A) : A -> A -> A).
(* FIXME HERE: ex3 does not work without type annotations on fun vars! I think
the problem is that the inferred types of the fun vars are evars that depend on
all the previous vars, so it looks like a dependent forall type and OTForRel_fun
does not apply. *)
Definition ex3 {A} :=
mkOTerm (A -o> A -o> A -o> A -o> A) (fun p1 p2 p3 p4 => p1).
Eval simpl in (fun A:OType => ot_unlift (@ex3 A) : A -> A -> A -> A -> A).
Definition ex4 {A B} : (A *o* B -o> A) := mkOTerm _ (fun p => fst p).
Eval simpl in (fun (A B:OType) => ot_unlift ex4 : A * B -> A).
Definition ex5 {A B} : A *o* B -o> B *o* A :=
mkOTerm _ (fun p => (snd p, fst p)).
Eval simpl in (fun (A B:OType) => ot_unlift ex5 : A *o* B -> B *o* A).
(*
Definition ex6 {A B C} : A *o* B *o* C -o> C *o* A :=
mkOTerm _ (fun triple => (snd triple, fst (fst triple))).
*)
Definition ex6 {A B C} : A *o* B *o* C -o> C *o* A :=
mkOTerm _ (fun triple => (osnd @o@ triple , ofst @o@ (ofst @o@ triple))).
Definition ex7 {A B C} : (A *o* B -o> C) -o> C -o> A -o> B -o> C :=
mkOTerm ((A *o* B -o> C) -o> C -o> A -o> B -o> C)
(fun (f:A *o* B -o> C) (c:C) a b => f @o@ (a ,o, b)).
End OTExamples.
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////
//
// This file is part of Descrypt Ztex Bruteforcer
// Copyright (C) 2014 Alexey Osipov <giftsungiv3n at gmail dot com>
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
////////////////////////////////////////////////////////////////////////
module IP(
input [63:0] Din,
output [63:0] Dout
);
assign Dout = {Din[6], Din[14], Din[22], Din[30], Din[38], Din[46], Din[54], Din[62], Din[4], Din[12], Din[20], Din[28], Din[36], Din[44], Din[52], Din[60], Din[2], Din[10], Din[18], Din[26], Din[34], Din[42], Din[50], Din[58], Din[0], Din[8], Din[16], Din[24], Din[32], Din[40], Din[48], Din[56], Din[7], Din[15], Din[23], Din[31], Din[39], Din[47], Din[55], Din[63], Din[5], Din[13], Din[21], Din[29], Din[37], Din[45], Din[53], Din[61], Din[3], Din[11], Din[19], Din[27], Din[35], Din[43], Din[51], Din[59], Din[1], Din[9], Din[17], Din[25], Din[33], Din[41], Din[49], Din[57]};
endmodule
module IP_1(
input [63:0] Din,
output [63:0] Dout
);
assign Dout = {Din[24], Din[56], Din[16], Din[48], Din[8], Din[40], Din[0], Din[32], Din[25], Din[57], Din[17], Din[49], Din[9], Din[41], Din[1], Din[33], Din[26], Din[58], Din[18], Din[50], Din[10], Din[42], Din[2], Din[34], Din[27], Din[59], Din[19], Din[51], Din[11], Din[43], Din[3], Din[35], Din[28], Din[60], Din[20], Din[52], Din[12], Din[44], Din[4], Din[36], Din[29], Din[61], Din[21], Din[53], Din[13], Din[45], Din[5], Din[37], Din[30], Din[62], Din[22], Din[54], Din[14], Din[46], Din[6], Din[38], Din[31], Din[63], Din[23], Din[55], Din[15], Din[47], Din[7], Din[39]};
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
/**
* Note that all instructions are 32-bits, and that Big-Endian
* byte and bit labeling is used. Hence, a[0] is the most
* significant bit, and a[31] is the least significant bit.
*
* Use of casex and casez may affect functionality, and produce
* larger and slower designs that omit the full_case directive
*
* Reference:
* Don Mills and Clifford E. Cummings, "RTL Coding Styles That
* Yield Simulation and Synthesis Mismatches", SNUG 1999
*/
`include "control.h"
// Behavioral model for the ALU
module arrmul (reg_A,reg_B,ctrl_ww,alu_op,result);
// Output signals...
// Result from copmputing an arithmetic or logical operation
output [0:127] result;
/**
* Overflow fromn arithmetic operations are ignored; use
* saturating mode for arithmetic operations - cap the value
* at the maximum value.
*
* Also, an output signal to indicate that an overflow has
* occurred will not be provided
*/
// ===============================================================
// Input signals
// Input register A
input [0:127] reg_A;
// Input register B
input [0:127] reg_B;
// Control signal bits - ww
input [0:1] ctrl_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform
*/
input [0:4] alu_op;
/**
* May also include: branch_offset[n:0], is_branch
* Size of branch offset is specified in the Instruction Set
* Architecture
*
* The reset signal for the ALU is ignored
*/
// Defining constants: parameter [name_of_constant] = value;
// Defining integers: integer [name_of_integer] = value;
integer sgn;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [0:127] result; // Output signals
/**
* Temporary reg(s) to contain the partial products during
* multiplication
*/
reg [0:127] p_pdt;
// Temporary reg variables for WW=8, for 8-bit multiplication
reg [0:15] p_pdt8a;
reg [0:15] p_pdt8a2;
reg [0:15] p_pdt8b;
reg [0:15] p_pdt8b2;
reg [0:15] p_pdt8c;
reg [0:15] p_pdt8c2;
reg [0:15] p_pdt8d;
reg [0:15] p_pdt8d2;
reg [0:15] p_pdt8e;
reg [0:15] p_pdt8e2;
reg [0:15] p_pdt8f;
reg [0:15] p_pdt8f2;
reg [0:15] p_pdt8g;
reg [0:15] p_pdt8g2;
reg [0:15] p_pdt8h;
reg [0:15] p_pdt8h2;
// Temporary reg variables for WW=16, for 16-bit multiplication
reg [0:31] p_pdt16a;
reg [0:31] p_pdt16a2;
reg [0:31] p_pdt16a3;
reg [0:31] p_pdt16b;
reg [0:31] p_pdt16b2;
reg [0:31] p_pdt16c;
reg [0:31] p_pdt16c2;
reg [0:31] p_pdt16d;
reg [0:31] p_pdt16d2;
// ===============================================================
always @(reg_A or reg_B or ctrl_ww or alu_op)
begin
$display("reg_A",reg_A);
$display("reg_B",reg_B);
p_pdt=128'd0;
p_pdt8a=16'd0;
p_pdt8a2=16'd0;
p_pdt8b=16'd0;
p_pdt8b2=16'd0;
p_pdt8c=16'd0;
p_pdt8c2=16'd0;
p_pdt8d=16'd0;
p_pdt8d2=16'd0;
p_pdt8e=16'd0;
p_pdt8e2=16'd0;
p_pdt8f=16'd0;
p_pdt8f2=16'd0;
p_pdt8g=16'd0;
p_pdt8g2=16'd0;
p_pdt8h=16'd0;
p_pdt8h2=16'd0;
p_pdt16a=32'd0;
p_pdt16a2=32'd0;
p_pdt16a3=32'd0;
p_pdt16b=32'd0;
p_pdt16b2=32'd0;
p_pdt16c=32'd0;
p_pdt16c2=32'd0;
p_pdt16d=32'd0;
p_pdt16d2=32'd0;
/**
* Based on the assigned arithmetic or logic instruction,
* carry out the appropriate function on the operands
*/
case(alu_op)
// ======================================================
// Unsigned Multiplication - even subfields
`aluwmuleu:
begin
case(ctrl_ww)
`w8: // aluwmuleu AND `w8
begin
p_pdt8a[8:15]=reg_A[0:7];
p_pdt8a[0:7]=8'd0;
for(sgn=7; sgn>=0; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[0:15]=p_pdt[0:15]+(p_pdt8a<<(7-sgn));
end
end
result[0:15]=p_pdt[0:15];
p_pdt8b[8:15]=reg_A[16:23];
p_pdt8b[0:7]=8'd0;
for(sgn=23; sgn>=16; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[16:31]=p_pdt[16:31]+(p_pdt8b<<(7-(sgn%8)));
end
end
result[16:31]=p_pdt[16:31];
p_pdt8c[8:15]=reg_A[32:39];
p_pdt8c[0:7]=8'd0;
for(sgn=39; sgn>=32; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[32:47]=p_pdt[32:47]+(p_pdt8c<<(7-(sgn%8)));
end
end
result[32:47]=p_pdt[32:47];
p_pdt8d[8:15]=reg_A[48:55];
p_pdt8d[0:7]=8'd0;
for(sgn=55; sgn>=48; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[48:63]=p_pdt[48:63]+(p_pdt8d<<(7-(sgn%8)));
end
end
result[48:63]=p_pdt[48:63];
p_pdt8e[8:15]=reg_A[64:71];
p_pdt8e[0:7]=8'd0;
for(sgn=71; sgn>=64; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[64:79]=p_pdt[64:79]+(p_pdt8e<<(7-(sgn%8)));
end
end
result[64:79]=p_pdt[64:79];
p_pdt8f[8:15]=reg_A[80:87];
p_pdt8f[0:7]=8'd0;
for(sgn=87; sgn>=80; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[80:95]=p_pdt[80:95]+(p_pdt8f<<(7-(sgn%8)));
end
end
result[80:95]=p_pdt[80:95];
p_pdt8g[8:15]=reg_A[96:103];
p_pdt8g[0:7]=8'd0;
for(sgn=103; sgn>=96; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[96:111]=p_pdt[96:111]+(p_pdt8g<<(7-(sgn%8)));
end
end
result[96:111]=p_pdt[96:111];
p_pdt8h[8:15]=reg_A[112:119];
p_pdt8h[0:7]=8'd0;
for(sgn=119; sgn>=112; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[112:127]=p_pdt[112:127]+(p_pdt8h<<(7-(sgn%8)));
end
end
result[112:127]=p_pdt[112:127];
end
`w16: // aluwmuleu AND `w16
begin
p_pdt16a[16:31]=reg_A[0:15];
p_pdt16a[0:15]=8'd0;
for(sgn=15; sgn>=0; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[0:31]=p_pdt[0:31]+(reg_A[0:15]<<(15-sgn));
end
end
result[0:31]=p_pdt[0:31];
p_pdt16b[16:31]=reg_A[32:47];
p_pdt16b[0:15]=8'd0;
for(sgn=47; sgn>=32; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[32:63]=p_pdt[32:63]+(reg_A[32:47]<<(15-(sgn%16)));
end
end
result[32:63]=p_pdt[32:63];
p_pdt16c[16:31]=reg_A[64:79];
p_pdt16c[0:15]=8'd0;
for(sgn=79; sgn>=64; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[64:95]=p_pdt[64:95]+(reg_A[64:79]<<(15-(sgn%16)));
end
end
result[64:95]=p_pdt[64:95];
p_pdt16d[16:31]=reg_A[96:111];
p_pdt16d[0:15]=8'd0;
for(sgn=111; sgn>=96; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[96:127]=p_pdt[96:127]+(reg_A[96:111]<<(15-(sgn%16)));
end
end
result[96:127]=p_pdt[96:127];
end
default: // aluwmuleu AND Default
begin
result=128'd0;
end
endcase
end
/**
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
*/
// ======================================================
// Unsigned Multiplication - odd subfields
`aluwmulou:
begin
case(ctrl_ww)
`w8: // aluwmulou AND `w8
begin
p_pdt8a[8:15]=reg_A[8:15];
p_pdt8a[0:7]=8'd0;
for(sgn=15; sgn>=8; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[0:15]=p_pdt[0:15]+(p_pdt8a<<(7-(sgn%8)));
end
end
result[0:15]=p_pdt[0:15];
p_pdt8b[8:15]=reg_A[24:31];
p_pdt8b[0:7]=8'd0;
for(sgn=31; sgn>=24; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[16:31]=p_pdt[16:31]+(p_pdt8b<<(7-(sgn%8)));
end
end
result[16:31]=p_pdt[16:31];
p_pdt8c[8:15]=reg_A[40:47];
p_pdt8c[0:7]=8'd0;
for(sgn=39; sgn>=33; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[32:47]=p_pdt[32:47]+(p_pdt8c<<(7-(sgn%8)));
end
end
result[32:47]=p_pdt[32:47];
p_pdt8d[8:15]=reg_A[56:63];
p_pdt8d[0:7]=8'd0;
for(sgn=55; sgn>=48; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[48:63]=p_pdt[48:63]+(p_pdt8d<<(7-(sgn%8)));
end
end
result[48:63]=p_pdt[48:63];
p_pdt8e[8:15]=reg_A[72:79];
p_pdt8e[0:7]=8'd0;
for(sgn=79; sgn>=72; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[64:79]=p_pdt[64:79]+(p_pdt8e<<(7-(sgn%8)));
end
end
result[64:79]=p_pdt[64:79];
p_pdt8f[8:15]=reg_A[88:95];
p_pdt8f[0:7]=8'd0;
for(sgn=95; sgn>=88; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[80:95]=p_pdt[80:95]+(p_pdt8f<<(7-(sgn%8)));
end
end
result[80:95]=p_pdt[80:95];
p_pdt8g[8:15]=reg_A[104:111];
p_pdt8g[0:7]=8'd0;
for(sgn=111; sgn>=104; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[96:111]=p_pdt[96:111]+(p_pdt8g<<(7-(sgn%8)));
end
end
result[96:111]=p_pdt[96:111];
p_pdt8h[8:15]=reg_A[120:127];
p_pdt8h[0:7]=8'd0;
for(sgn=127; sgn>=120; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[112:127]=p_pdt[112:127]+(p_pdt8h<<(7-(sgn%8)));
end
end
result[112:127]=p_pdt[112:127];
end
`w16: // aluwmulou AND `w16
begin
p_pdt16a[16:31]=reg_A[16:31];
p_pdt16a[0:15]=8'd0;
for(sgn=31; sgn>=16; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[0:31]=p_pdt[0:31]+(reg_A[16:31]<<(15-(sgn%16)));
end
end
result[0:31]=p_pdt[0:31];
p_pdt16b[16:31]=reg_A[48:63];
p_pdt16b[0:15]=8'd0;
for(sgn=63; sgn>=48; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[32:63]=p_pdt[32:63]+(reg_A[48:63]<<(15-(sgn%16)));
end
end
result[32:63]=p_pdt[32:63];
p_pdt16c[16:31]=reg_A[80:95];
p_pdt16c[0:15]=8'd0;
for(sgn=95; sgn>=80; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[64:95]=p_pdt[64:95]+(reg_A[80:95]<<(15-(sgn%16)));
end
end
result[64:95]=p_pdt[64:95];
p_pdt16d[16:31]=reg_A[112:127];
p_pdt16d[0:15]=8'd0;
for(sgn=127; sgn>=112; sgn=sgn-1)
begin
if(reg_B[sgn]==1'b1)
begin
p_pdt[96:127]=p_pdt[96:127]+(reg_A[112:127]<<(15-(sgn%16)));
end
end
result[96:127]=p_pdt[96:127];
end
default: // aluwmulou AND Default
begin
result=128'd0;
end
endcase
end
/**
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
* =============================================================================
*/
// ======================================================
// Signed Multiplication - odd subfields
`aluwmulos:
begin
case(ctrl_ww)
`w8: // aluwmulos AND `w8
begin
// Process the 1st byte
if(reg_A[8]==0)
begin
p_pdt8a[8:15]=reg_A[8:15];
end
else
begin
p_pdt8a[8:15]=1+~reg_A[8:15];
end
p_pdt8b[0:7]=8'd0;
if(reg_B[8]==0)
begin
p_pdt8a2[8:15]=reg_B[8:15];
end
else
begin
p_pdt8a2[8:15]=1+~reg_B[8:15];
end
p_pdt8b2[0:7]=8'd0;
for(sgn=15; sgn>=0; sgn=sgn-1)
begin
if(p_pdt8a2[sgn]==1'b1)
begin
p_pdt[0:15]=p_pdt[0:15]+(p_pdt8a<<(7-(sgn%8)));
end
end
if(reg_A[8]^reg_B[8])
begin
result[0:15]=1+~p_pdt[0:15];
end
else
begin
result[0:15]=p_pdt[0:15];
end
// Process the 2nd byte
if(reg_A[24]==0)
begin
p_pdt8b[8:15]=reg_A[24:31];
end
else
begin
p_pdt8b[8:15]=1+~reg_A[24:31];
end
p_pdt8b[0:7]=8'd0;
if(reg_B[24]==0)
begin
p_pdt8b2[8:15]=reg_B[24:31];
end
else
begin
p_pdt8b2[8:15]=1+~reg_B[24:31];
end
p_pdt8b2[0:7]=8'd0;
for(sgn=15; sgn>=0; sgn=sgn-1)
begin
if(p_pdt8b2[sgn]==1'b1)
begin
p_pdt[16:31]=p_pdt[16:31]+(p_pdt8b<<(7-(sgn%8)));
end
end
if(reg_A[24]^reg_B[24])
begin
result[16:31]=1+~p_pdt[16:31];
end
else
begin
result[16:31]=p_pdt[16:31];
end
// Process the 3rd byte
// Convert operand A to a positive number
if(reg_A[40]==0)
begin
p_pdt8c[8:15]=reg_A[40:47];
end
else
begin
p_pdt8c[8:15]=1+~reg_A[40:47];
end
p_pdt8c[0:7]=8'd0;
// Convert operand B to a positive number
if(reg_B[40]==0)
begin
p_pdt8c2[8:15]=reg_B[40:47];
end
else
begin
p_pdt8c2[8:15]=1+~reg_B[40:47];
end
p_pdt8c2[0:7]=8'd0;
// Multiply the numbers using the shift-and-add method
for(sgn=15; sgn>=0; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if(p_pdt8c2[sgn]==1'b1)
begin
// Compute the partial products and sum them up
p_pdt[32:47]=p_pdt[32:47]+(p_pdt8c<<(7-(sgn%8)));
end
end
/**
* Perform two's complement operation on the result
* if the product is a result of multiplying a positive
* number to a negative number
*/
if(reg_A[40]^reg_B[40])
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[32:47]=1+~p_pdt[32:47];
end
else
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[32:47]=p_pdt[32:47];
end
// Process the 4th byte
// Convert operand A to a positive number
if(reg_A[56]==0)
begin
p_pdt8d[8:15]=reg_A[56:63];
end
else
begin
p_pdt8d[8:15]=1+~reg_A[56:63];
end
p_pdt8d[0:7]=8'd0;
// Convert operand B to a positive number
if(reg_B[56]==0)
begin
p_pdt8d2[8:15]=reg_B[56:63];
end
else
begin
p_pdt8d2[8:15]=1+~reg_B[56:63];
end
p_pdt8d2[0:7]=8'd0;
// Multiply the numbers using the shift-and-add method
for(sgn=15; sgn>=0; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if(p_pdt8d2[sgn]==1'b1)
begin
// Compute the partial products and sum them up
p_pdt[48:63]=p_pdt[48:63]+(p_pdt8d<<(7-(sgn%8)));
end
end
/**
* Perform two's complement operation on the result
* if the product is a result of multiplying a positive
* number to a negative number
*/
if(reg_A[56]^reg_B[56])
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[48:63]=1+~p_pdt[48:63];
end
else
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[48:63]=p_pdt[48:63];
end
// Process the 5th byte
// Convert operand A to a positive number
if(reg_A[72]==0)
begin
p_pdt8e[8:15]=reg_A[72:79];
end
else
begin
p_pdt8e[8:15]=1+~reg_A[72:79];
end
p_pdt8e[0:7]=8'd0;
// Convert operand B to a positive number
if(reg_B[72]==0)
begin
p_pdt8e2[8:15]=reg_B[72:79];
end
else
begin
p_pdt8e2[8:15]=1+~reg_B[72:79];
end
p_pdt8e2[0:7]=8'd0;
// Multiply the numbers using the shift-and-add method
for(sgn=15; sgn>=0; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if(p_pdt8e2[sgn]==1'b1)
begin
// Compute the partial products and sum them up
p_pdt[64:79]=p_pdt[64:79]+(p_pdt8e<<(7-(sgn%8)));
end
end
/**
* Perform two's complement operation on the result
* if the product is a result of multiplying a positive
* number to a negative number
*/
if(reg_A[72]^reg_B[72])
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[64:79]=1+~p_pdt[64:79];
end
else
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[64:79]=p_pdt[64:79];
end
// Process the 6th byte
// Convert operand A to a positive number
if(reg_A[88]==0)
begin
p_pdt8f[8:15]=reg_A[88:95];
end
else
begin
p_pdt8f[8:15]=1+~reg_A[88:95];
end
p_pdt8f[0:7]=8'd0;
// Convert operand B to a positive number
if(reg_B[88]==0)
begin
p_pdt8f2[8:15]=reg_B[88:95];
end
else
begin
p_pdt8f2[8:15]=1+~reg_B[88:95];
end
p_pdt8f2[0:7]=8'd0;
// Multiply the numbers using the shift-and-add method
for(sgn=15; sgn>=0; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if(p_pdt8f2[sgn]==1'b1)
begin
// Compute the partial products and sum them up
p_pdt[80:95]=p_pdt[80:95]+(p_pdt8f<<(7-(sgn%8)));
end
end
/**
* Perform two's complement operation on the result
* if the product is a result of multiplying a positive
* number to a negative number
*/
if(reg_A[88]^reg_B[88])
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[80:95]=1+~p_pdt[80:95];
end
else
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[80:95]=p_pdt[80:95];
end
// Process the 7th byte
// Convert operand A to a positive number
if(reg_A[104]==0)
begin
p_pdt8g[8:15]=reg_A[104:111];
end
else
begin
p_pdt8g[8:15]=1+~reg_A[104:111];
end
p_pdt8g[0:7]=8'd0;
// Convert operand B to a positive number
if(reg_B[104]==0)
begin
p_pdt8g2[8:15]=reg_B[104:111];
end
else
begin
p_pdt8g2[8:15]=1+~reg_B[104:111];
end
p_pdt8g2[0:7]=8'd0;
// Multiply the numbers using the shift-and-add method
for(sgn=15; sgn>=0; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if(p_pdt8g2[sgn]==1'b1)
begin
// Compute the partial products and sum them up
p_pdt[96:111]=p_pdt[96:111]+(p_pdt8g<<(7-(sgn%8)));
end
end
/**
* Perform two's complement operation on the result
* if the product is a result of multiplying a positive
* number to a negative number
*/
if(reg_A[104]^reg_B[104])
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[96:111]=1+~p_pdt[96:111];
end
else
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[96:111]=p_pdt[96:111];
end
// Process the 8th byte
// Convert operand A to a positive number
if(reg_A[120]==0)
begin
p_pdt8h[8:15]=reg_A[120:127];
end
else
begin
p_pdt8h[8:15]=1+~reg_A[120:127];
end
p_pdt8h[0:7]=8'd0;
// Convert operand B to a positive number
if(reg_B[120]==0)
begin
p_pdt8h2[8:15]=reg_B[120:127];
end
else
begin
p_pdt8h2[8:15]=1+~reg_B[120:127];
end
p_pdt8h2[0:7]=8'd0;
// Multiply the numbers using the shift-and-add method
for(sgn=15; sgn>=0; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if(p_pdt8h2[sgn]==1'b1)
begin
// Compute the partial products and sum them up
p_pdt[112:127]=p_pdt[112:127]+(p_pdt8h<<(7-(sgn%8)));
end
end
/**
* Perform two's complement operation on the result
* if the product is a result of multiplying a positive
* number to a negative number
*/
if(reg_A[120]^reg_B[120])
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[112:127]=1+~p_pdt[112:127];
end
else
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[112:127]=p_pdt[112:127];
end
// =======================================================
// =======================================================
// =======================================================
end
`w16: // aluwmulos AND `w16
begin
// Process the first pair of bytes
// Convert operand A to a positive number
if(reg_A[16]==0)
begin
p_pdt16a[16:31]=reg_A[16:31];
end
else
begin
p_pdt16a[16:31]=1+~reg_A[16:31];
end
p_pdt16a[0:15]=16'd0;
// Convert operand B to a positive number
if(reg_B[16]==0)
begin
p_pdt16a2[16:31]=reg_B[16:31];
end
else
begin
p_pdt16a2[16:31]=1+~reg_B[16:31];
end
p_pdt16a2[0:15]=16'd0;
// Multiply the numbers using the shift-and-add method
for(sgn=31; sgn>=0; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if(p_pdt16a2[sgn]==1'b1)
begin
// Compute the partial products and sum them up
p_pdt[0:31]=p_pdt[0:31]+(p_pdt16a<<(15-(sgn%16)));
end
end
/**
* Perform two's complement operation on the result
* if the product is a result of multiplying a positive
* number to a negative number
*/
if(reg_A[16]^reg_B[16])
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[0:31]=1+~p_pdt[0:31];
end
else
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[0:31]=p_pdt[0:31];
end
// Process the second pair of bytes
// Convert operand A to a positive number
if(reg_A[48]==0)
begin
p_pdt16b[16:31]=reg_A[48:63];
end
else
begin
p_pdt16b[16:31]=1+~reg_A[48:63];
end
p_pdt16b[0:15]=16'd0;
// Convert operand B to a positive number
if(reg_B[48]==0)
begin
p_pdt16b2[16:31]=reg_B[48:63];
end
else
begin
p_pdt16b2[16:31]=1+~reg_B[48:63];
end
p_pdt16b2[0:15]=16'd0;
// Multiply the numbers using the shift-and-add method
for(sgn=31; sgn>=0; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if(p_pdt16b2[sgn]==1'b1)
begin
// Compute the partial products and sum them up
p_pdt[32:63]=p_pdt[32:63]+(p_pdt16b<<(15-(sgn%16)));
end
end
/**
* Perform two's complement operation on the result
* if the product is a result of multiplying a positive
* number to a negative number
*/
if(reg_A[48]^reg_B[48])
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[32:63]=1+~p_pdt[32:63];
end
else
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[32:63]=p_pdt[32:63];
end
// Process the third pair of bytes
// Convert operand A to a positive number
if(reg_A[80]==0)
begin
p_pdt16c[16:31]=reg_A[80:95];
end
else
begin
p_pdt16c[16:31]=1+~reg_A[80:95];
end
p_pdt16c[0:15]=16'd0;
// Convert operand B to a positive number
if(reg_B[80]==0)
begin
p_pdt16c2[16:31]=reg_B[80:95];
end
else
begin
p_pdt16c2[16:31]=1+~reg_B[80:95];
end
p_pdt16c2[0:15]=16'd0;
// Multiply the numbers using the shift-and-add method
for(sgn=31; sgn>=0; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if(p_pdt16c2[sgn]==1'b1)
begin
// Compute the partial products and sum them up
p_pdt[64:95]=p_pdt[64:95]+(p_pdt16c<<(15-(sgn%16)));
end
end
/**
* Perform two's complement operation on the result
* if the product is a result of multiplying a positive
* number to a negative number
*/
if(reg_A[80]^reg_B[80])
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[64:95]=1+~p_pdt[64:95];
end
else
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[64:95]=p_pdt[64:95];
end
// Process the fourth pair of bytes
// Convert operand A to a positive number
if(reg_A[112]==0)
begin
p_pdt16d[16:31]=reg_A[112:127];
end
else
begin
p_pdt16d[16:31]=1+~reg_A[112:127];
end
p_pdt16d[0:15]=16'd0;
// Convert operand B to a positive number
if(reg_B[112]==0)
begin
p_pdt16d2[16:31]=reg_B[112:127];
end
else
begin
p_pdt16d2[16:31]=1+~reg_B[112:127];
end
p_pdt16d2[0:15]=16'd0;
// Multiply the numbers using the shift-and-add method
for(sgn=31; sgn>=0; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if(p_pdt16d2[sgn]==1'b1)
begin
// Compute the partial products and sum them up
p_pdt[96:127]=p_pdt[96:127]+(p_pdt16d<<(15-(sgn%16)));
end
end
/**
* Perform two's complement operation on the result
* if the product is a result of multiplying a positive
* number to a negative number
*/
if(reg_A[112]^reg_B[112])
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[96:127]=1+~p_pdt[96:127];
end
else
begin
/**
* The result is negative. Perform two's complement
* operation
*/
result[96:127]=p_pdt[96:127];
end
end
default: // aluwmulos AND Default
begin
result=128'd0;
end
endcase
end
// ======================================================
// Signed Multiplication - even subfields
`aluwmules:
begin
case(ctrl_ww)
`w8: // aluwmules AND `w8
begin
// Process the 1st byte
// Process operand B
p_pdt8a2[8:15]=reg_B[0:7];
p_pdt8a2[0:7]=8'd0;
// Process operand A
if(reg_A[0]==1'd1)
begin
p_pdt8a[8:15]=1+~reg_A[0:7];
if(reg_B[0]==1'd1)
begin
p_pdt8a2[8:15]=1+~reg_B[0:7];
end
else
begin
p_pdt8a2[8:15]=reg_B[0:7];
end
end
else
begin
p_pdt8a[8:15]=reg_A[0:7];
end
p_pdt8a[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8a2[15]==1'd1)
begin
p_pdt[0:15]=p_pdt[0:15] - p_pdt8a[0:15];
end
else
begin
p_pdt[0:15]=p_pdt[0:15]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8a2[sgn]==1'b1) && (p_pdt8a2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[0:15]=p_pdt[0:15]-(p_pdt8a<<(7-(sgn%8)));
end
else if((p_pdt8a2[sgn]==1'b0) && (p_pdt8a2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[0:15]=p_pdt[0:15]+(p_pdt8a<<(7-(sgn%8)));
end
else
begin
p_pdt[0:15]=p_pdt[0:15]+0;
end
end
if(p_pdt8a[8]==1'd1)
begin
result[0:15]=1+~p_pdt[0:15];
end
else
begin
result[0:15]=p_pdt[0:15];
end
// Process the 2nd byte
// Process operand B
p_pdt8b2[8:15]=reg_B[16:23];
p_pdt8b2[0:7]=8'd0;
// Process operand A
if(reg_A[16]==1'd1)
begin
p_pdt8b[8:15]=1+~reg_A[16:23];
if(reg_B[16]==1'd1)
begin
p_pdt8b2[8:15]=1+~reg_B[16:23];
end
else
begin
p_pdt8b2[8:15]=reg_B[16:23];
end
end
else
begin
p_pdt8b[8:15]=reg_A[16:23];
end
p_pdt8b[0:7]=8'd0;
$display("p_pdt8b[0:15]",p_pdt8b[0:15]);
$display("p_pdt8b2[0:15]",p_pdt8b2[0:15]);
// Determine the 1st recoded bit and compute the result
if(p_pdt8b2[15]==1'd1)
begin
p_pdt[16:31]=p_pdt[16:31] - p_pdt8b[0:15];
end
else
begin
p_pdt[16:31]=p_pdt[16:31]+0;
end
$display("p_pdt[16:31]",p_pdt[16:31]);
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8b2[sgn]==1'b1) && (p_pdt8b2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[16:31]=p_pdt[16:31]-(p_pdt8b<<(7-(sgn%8)));
$display("MINUSp_pdt[16:31]",p_pdt[16:31]);
end
else if((p_pdt8b2[sgn]==1'b0) && (p_pdt8b2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[16:31]=p_pdt[16:31]+(p_pdt8b<<(7-(sgn%8)));
$display("ADDp_pdt[16:31]",p_pdt[16:31]);
end
else
begin
p_pdt[16:31]=p_pdt[16:31]+0;
$display("ZEROp_pdt[16:31]",p_pdt[16:31]);
end
end
if(p_pdt8b[8]==1'd1)
begin
result[16:31]=1+~p_pdt[16:31];
$display("INVp_pdt[16:31]",p_pdt[16:31]);
end
else
begin
result[16:31]=p_pdt[16:31];
$display("RESp_pdt[16:31]",p_pdt[16:31]);
end
// Process the 3rd byte
// Process operand B
p_pdt8c2[8:15]=reg_B[32:39];
p_pdt8c2[0:7]=8'd0;
// Process operand A
if(reg_A[32]==1'd1)
begin
p_pdt8c[8:15]=1+~reg_A[32:39];
if(reg_B[32]==1'd1)
begin
p_pdt8c2[8:15]=1+~reg_B[32:39];
end
else
begin
p_pdt8c2[8:15]=reg_B[32:39];
end
end
else
begin
p_pdt8c[8:15]=reg_A[32:39];
end
p_pdt8c[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8c2[15]==1'd1)
begin
p_pdt[32:47]=p_pdt[32:47] - p_pdt8c[0:15];
end
else
begin
p_pdt[32:47]=p_pdt[32:47]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8c2[sgn]==1'b1) && (p_pdt8c2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[32:47]=p_pdt[32:47]-(p_pdt8c<<(7-(sgn%8)));
end
else if((p_pdt8c2[sgn]==1'b0) && (p_pdt8c2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[32:47]=p_pdt[32:47]+(p_pdt8c<<(7-(sgn%8)));
end
else
begin
p_pdt[32:47]=p_pdt[32:47]+0;
end
end
if(p_pdt8c[8]==1'd1)
begin
result[32:47]=1+~p_pdt[32:47];
end
else
begin
result[32:47]=p_pdt[32:47];
end
// Process the 4th byte
// Process operand B
p_pdt8d2[8:15]=reg_B[48:55];
p_pdt8d2[0:7]=8'd0;
// Process operand A
if(reg_A[48]==1'd1)
begin
p_pdt8d[8:15]=1+~reg_A[48:55];
if(reg_B[48]==1'd1)
begin
p_pdt8d2[8:15]=1+~reg_B[48:55];
end
else
begin
p_pdt8d2[8:15]=reg_B[48:55];
end
end
else
begin
p_pdt8d[8:15]=reg_A[48:55];
end
p_pdt8d[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8d2[15]==1'd1)
begin
p_pdt[48:63]=p_pdt[48:63] - p_pdt8d[0:15];
end
else
begin
p_pdt[48:63]=p_pdt[48:63]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8d2[sgn]==1'b1) && (p_pdt8d2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[48:63]=p_pdt[48:63]-(p_pdt8d<<(7-(sgn%8)));
end
else if((p_pdt8d2[sgn]==1'b0) && (p_pdt8d2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[48:63]=p_pdt[48:63]+(p_pdt8d<<(7-(sgn%8)));
end
else
begin
p_pdt[48:63]=p_pdt[48:63]+0;
end
end
if(p_pdt8d[8]==1'd1)
begin
result[48:63]=1+~p_pdt[48:63];
end
else
begin
result[48:63]=p_pdt[48:63];
end
// Process the 5th byte
// Process operand B
p_pdt8e2[8:15]=reg_B[64:71];
p_pdt8e2[0:7]=8'd0;
// Process operand A
if(reg_A[64]==1'd1)
begin
p_pdt8e[8:15]=1+~reg_A[64:71];
if(reg_B[64]==1'd1)
begin
p_pdt8e2[8:15]=1+~reg_B[64:71];
end
else
begin
p_pdt8e2[8:15]=reg_B[64:71];
end
end
else
begin
p_pdt8e[8:15]=reg_A[64:71];
end
p_pdt8e[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8e2[15]==1'd1)
begin
p_pdt[64:79]=p_pdt[64:79] - p_pdt8e[0:15];
end
else
begin
p_pdt[64:79]=p_pdt[64:79]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8e2[sgn]==1'b1) && (p_pdt8e2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[64:79]=p_pdt[64:79]-(p_pdt8e<<(7-(sgn%8)));
end
else if((p_pdt8e2[sgn]==1'b0) && (p_pdt8e2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[64:79]=p_pdt[64:79]+(p_pdt8e<<(7-(sgn%8)));
end
else
begin
p_pdt[64:79]=p_pdt[64:79]+0;
end
end
if(p_pdt8e[8]==1'd1)
begin
result[64:79]=1+~p_pdt[64:79];
end
else
begin
result[64:79]=p_pdt[64:79];
end
// Process the 6th byte
// Process operand B
p_pdt8f2[8:15]=reg_B[80:87];
p_pdt8f2[0:7]=8'd0;
// Process operand A
if(reg_A[80]==1'd1)
begin
p_pdt8f[8:15]=1+~reg_A[80:87];
if(reg_B[80]==1'd1)
begin
p_pdt8f2[8:15]=1+~reg_B[80:87];
end
else
begin
p_pdt8f2[8:15]=reg_B[80:87];
end
end
else
begin
p_pdt8f[8:15]=reg_A[80:87];
end
p_pdt8f[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8f2[15]==1'd1)
begin
p_pdt[80:95]=p_pdt[80:95] - p_pdt8f[0:15];
end
else
begin
p_pdt[80:95]=p_pdt[80:95]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8f2[sgn]==1'b1) && (p_pdt8f2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[80:95]=p_pdt[80:95]-(p_pdt8f<<(7-(sgn%8)));
end
else if((p_pdt8f2[sgn]==1'b0) && (p_pdt8f2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[80:95]=p_pdt[80:95]+(p_pdt8f<<(7-(sgn%8)));
end
else
begin
p_pdt[80:95]=p_pdt[80:95]+0;
end
end
if(p_pdt8f[8]==1'd1)
begin
result[80:95]=1+~p_pdt[80:95];
end
else
begin
result[80:95]=p_pdt[80:95];
end
// Process the 7th byte
// Process operand B
p_pdt8g2[8:15]=reg_B[96:103];
p_pdt8g2[0:7]=8'd0;
// Process operand A
if(reg_A[96]==1'd1)
begin
p_pdt8g[8:15]=1+~reg_A[96:103];
if(reg_B[96]==1'd1)
begin
p_pdt8g2[8:15]=1+~reg_B[96:103];
end
else
begin
p_pdt8g2[8:15]=reg_B[96:103];
end
end
else
begin
p_pdt8g[8:15]=reg_A[96:103];
end
p_pdt8g[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8g2[15]==1'd1)
begin
p_pdt[96:111]=p_pdt[96:111] - p_pdt8g[0:15];
end
else
begin
p_pdt[96:111]=p_pdt[96:111]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8g2[sgn]==1'b1) && (p_pdt8g2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[96:111]=p_pdt[96:111]-(p_pdt8g<<(7-(sgn%8)));
end
else if((p_pdt8g2[sgn]==1'b0) && (p_pdt8g2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[96:111]=p_pdt[96:111]+(p_pdt8g<<(7-(sgn%8)));
end
else
begin
p_pdt[96:111]=p_pdt[96:111]+0;
end
end
if(p_pdt8g[8]==1'd1)
begin
result[96:111]=1+~p_pdt[96:111];
end
else
begin
result[96:111]=p_pdt[96:111];
end
// Process the 8th byte
// Process operand B
p_pdt8h2[8:15]=reg_B[112:119];
p_pdt8h2[0:7]=8'd0;
// Process operand A
if(reg_A[112]==1'd1)
begin
p_pdt8h[8:15]=1+~reg_A[112:119];
if(reg_B[112]==1'd1)
begin
p_pdt8h2[8:15]=1+~reg_B[112:119];
end
else
begin
p_pdt8h2[8:15]=reg_B[112:119];
end
end
else
begin
p_pdt8h[8:15]=reg_A[112:119];
end
p_pdt8h[0:7]=8'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt8h2[15]==1'd1)
begin
p_pdt[112:127]=p_pdt[112:127] - p_pdt8h[0:15];
end
else
begin
p_pdt[112:127]=p_pdt[112:127]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=14; sgn>=8; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt8h2[sgn]==1'b1) && (p_pdt8h2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[112:127]=p_pdt[112:127]-(p_pdt8h<<(7-(sgn%8)));
end
else if((p_pdt8h2[sgn]==1'b0) && (p_pdt8h2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[112:127]=p_pdt[112:127]+(p_pdt8h<<(7-(sgn%8)));
end
else
begin
p_pdt[112:127]=p_pdt[112:127]+0;
end
end
if(p_pdt8h[8]==1'd1)
begin
result[112:127]=1+~p_pdt[112:127];
end
else
begin
result[112:127]=p_pdt[112:127];
end
// =======================================================
// =======================================================
// =======================================================
/*
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
* ====================================================================
*/
end
`w16: // aluwmules AND `w16
begin
// Process the first pair of bytes
// Process operand B
p_pdt16a2[16:31]=reg_B[0:15];
p_pdt16a2[0:15]=16'd0;
// Process operand A
if(reg_A[0]==1'd1)
begin
p_pdt16a[16:31]=1+~reg_A[0:15];
if(reg_B[0]==1'd1)
begin
p_pdt16a2[16:31]=1+~reg_B[0:15];
end
else
begin
p_pdt16a2[16:31]=reg_B[0:15];
end
end
else
begin
p_pdt16a[16:31]=reg_A[0:15];
end
p_pdt16a[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16a2[31]==1'd1)
begin
p_pdt[0:31]=p_pdt[0:31] - p_pdt16a[0:31];
end
else
begin
p_pdt[0:31]=p_pdt[0:31]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16a2[sgn]==1'b1) && (p_pdt16a2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[0:31]=p_pdt[0:31]-(p_pdt16a<<(15-(sgn%16)));
end
else if((p_pdt16a2[sgn]==1'b0) && (p_pdt16a2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[0:31]=p_pdt[0:31]+(p_pdt16a<<(15-(sgn%16)));
end
else
begin
p_pdt[0:31]=p_pdt[0:31]+0;
end
end
if(p_pdt16a[16]==1'd1)
begin
result[0:31]=1+~p_pdt[0:31];
end
else
begin
result[0:31]=p_pdt[0:31];
end
// Process the second pair of bytes
// Process operand B
p_pdt16b2[16:31]=reg_B[32:47];
p_pdt16b2[0:15]=16'd0;
// Process operand A
if(reg_A[32]==1'd1)
begin
p_pdt16b[16:31]=1+~reg_A[32:47];
if(reg_B[32]==1'd1)
begin
p_pdt16b2[16:31]=1+~reg_B[32:47];
end
else
begin
p_pdt16b2[16:31]=reg_B[32:47];
end
end
else
begin
p_pdt16b[16:31]=reg_A[0:15];
end
p_pdt16b[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16b2[31]==1'd1)
begin
p_pdt[32:63]=p_pdt[32:63] - p_pdt16b[0:31];
end
else
begin
p_pdt[32:63]=p_pdt[32:63]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16b2[sgn]==1'b1) && (p_pdt16b2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[32:63]=p_pdt[32:63]-(p_pdt16b<<(15-(sgn%16)));
end
else if((p_pdt16b2[sgn]==1'b0) && (p_pdt16b2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[32:63]=p_pdt[32:63]+(p_pdt16b<<(15-(sgn%16)));
end
else
begin
p_pdt[32:63]=p_pdt[32:63]+0;
end
end
if(p_pdt16b[16]==1'd1)
begin
result[32:63]=1+~p_pdt[32:63];
end
else
begin
result[32:63]=p_pdt[32:63];
end
// Process the third pair of bytes
// Process operand B
p_pdt16c2[16:31]=reg_B[64:79];
p_pdt16c2[0:15]=16'd0;
// Process operand A
if(reg_A[64]==1'd1)
begin
p_pdt16c[16:31]=1+~reg_A[64:79];
if(reg_B[64]==1'd1)
begin
p_pdt16c2[16:31]=1+~reg_B[64:79];
end
else
begin
p_pdt16c2[16:31]=reg_B[64:79];
end
end
else
begin
p_pdt16c[16:31]=reg_A[64:79];
end
p_pdt16c[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16c2[31]==1'd1)
begin
p_pdt[64:95]=p_pdt[64:95] - p_pdt16c[0:31];
end
else
begin
p_pdt[64:95]=p_pdt[64:95]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16c2[sgn]==1'b1) && (p_pdt16c2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[64:95]=p_pdt[64:95]-(p_pdt16c<<(15-(sgn%16)));
end
else if((p_pdt16c2[sgn]==1'b0) && (p_pdt16c2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[64:95]=p_pdt[64:95]+(p_pdt16c<<(15-(sgn%16)));
end
else
begin
p_pdt[64:95]=p_pdt[64:95]+0;
end
end
if(p_pdt16c[16]==1'd1)
begin
result[64:95]=1+~p_pdt[64:95];
end
else
begin
result[64:95]=p_pdt[64:95];
end
// Process the fourth pair of bytes
// Process operand B
p_pdt16d2[16:31]=reg_B[96:111];
p_pdt16d2[0:15]=16'd0;
// Process operand A
if(reg_A[96]==1'd1)
begin
p_pdt16d[16:31]=1+~reg_A[96:111];
if(reg_B[96]==1'd1)
begin
p_pdt16d2[16:31]=1+~reg_B[96:111];
end
else
begin
p_pdt16d2[16:31]=reg_B[96:111];
end
end
else
begin
p_pdt16d[16:31]=reg_A[96:111];
end
p_pdt16d[0:15]=16'd0;
// Determine the 1st recoded bit and compute the result
if(p_pdt16d2[31]==1'd1)
begin
p_pdt[96:127]=p_pdt[96:127] - p_pdt16d[0:31];
end
else
begin
p_pdt[96:127]=p_pdt[96:127]+0;
end
// Multiply the numbers using the shift-and-add method
for(sgn=30; sgn>=16; sgn=sgn-1)
begin
/**
* Shift the multiplier to determine the partial
* product for this current shift
*/
if((p_pdt16d2[sgn]==1'b1) && (p_pdt16d2[sgn+1]==1'b0))
begin
// Compute the partial products and sum them up
p_pdt[96:127]=p_pdt[96:127]-(p_pdt16d<<(15-(sgn%16)));
end
else if((p_pdt16d2[sgn]==1'b0) && (p_pdt16d2[sgn+1]==1'b1))
begin
// Compute the partial products and sum them up
p_pdt[96:127]=p_pdt[96:127]+(p_pdt16d<<(15-(sgn%16)));
end
else
begin
p_pdt[96:127]=p_pdt[96:127]+0;
end
end
if(p_pdt16d[16]==1'd1)
begin
result[96:127]=1+~p_pdt[96:127];
end
else
begin
result[96:127]=p_pdt[96:127];
end
end
default: // aluwmules AND Default
begin
result=128'd0;
end
endcase
end
default:
begin
// Default arithmetic/logic operation
result=128'd0;
end
endcase
end
endmodule
|
// -----------------------------------------------------------------------------
// FILE NAME : Wu_Manber_shiftPE.v
// DEPARTMENT : Computer Engineering
// AUTHOR : Ashik Poojari
// -----------------------------------------------------------------------------
// RELEASE HISTORY
// VERSION DATE AUTHOR DESCRIPTION
// 1.0 2016-09-18 Ashik Poojari
// -----------------------------------------------------------------------------
// KEYWORDS : General file searching keywords, leave blank if none.
// -----------------------------------------------------------------------------
// PURPOSE : Short description of functionality
// -----------------------------------------------------------------------------
// PARAMETERS
// PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
// e.g.DATA_WIDTH [32,16] : width of the data : 32 :
// NO_OF_MSGS : no of hexadecimal digit
// MSG_WIDTH : hexadecimal width is 4
// SHIFT_DATA_WIDTH : data width of shift register
// NO_OF_MSGS=16, MSG_WIDTH=8, B=3, PATTERN_WIDTH=6,
// SHIFT_DATA_WIDTH=MSG_WIDTH*(PATTERN_WIDTH-B+1),
// SHIFT_WIDTH=$clog2(PATTERN_WIDTH-B+1),
// DATA_WIDTH=MSG_WIDTH*(NO_OF_MSGS+(2*PATTERN_WIDTH+B)),
// POINTER_WIDTH=$clog2(DATA_WIDTH);
// -----------------------------------------------------------------------------
// REUSE ISSUES
// Reset Strategy : Asynchronous
// Clock Domains :
// Critical Timing :
// Test Features :
// Asynchronous I/F :
// Scan Methodology :
// Instantiations :
// Synthesizable (y/n) : y
// Other :
// -FHDR------------------------------------------------------------------------
module Wu_Manber_shiftPE #(parameter NO_OF_MSGS=128, MSG_WIDTH=4, B=3, PATTERN_WIDTH=20, SIGN_DEPTH=1024,
SHIFT_WIDTH=$clog2(PATTERN_WIDTH-B+1),DATA_WIDTH=MSG_WIDTH*NO_OF_MSGS,
NOS_SHIFTER=2*NO_OF_MSGS, POINTER_WIDTH=$clog2(NOS_SHIFTER), NOS_KEY=4, NOS_CMPS=SIGN_DEPTH/NOS_KEY,NOS_STGS=$clog2(SIGN_DEPTH/NOS_KEY),SFT_DEL_WDH=$clog2(NOS_STGS+NOS_KEY+2),MAX_PAT_SZ=78)
( input clk,
input reset,
input datInReady,
input [DATA_WIDTH-1:0] DataIn,
output getDATA,
output [10:0] dout);
localparam DATA_2WIDTH= 1024;
wire [DATA_WIDTH-1:0] datIn_op;
wire [MSG_WIDTH*PATTERN_WIDTH-1:0] a_ip, a_op;
wire [SHIFT_WIDTH-1:0] shift_ip, shift_op;
reg [SHIFT_WIDTH-1:0] shift_tmp;
wire din_sel;
wire [NOS_CMPS-1:0]fullCompare;
wire [POINTER_WIDTH-1:0] shift_pnt;
reg [2*NO_OF_MSGS*MSG_WIDTH-1:0] Data_in;
//register signals
wire a_clr, datin_clr, shift_clr;
wire a_ld;
wire shift_ld;
wire datald;
reg dat_ld, datin_ld;
wire compare_mux,compare_enable;
wire datin_ld_delwr;
reg datin_ld_del;
wire [MSG_WIDTH*MAX_PAT_SZ-1:0] data_nfa;
reg [PATTERN_WIDTH*MSG_WIDTH*NOS_KEY-1:0] pattern [0:NOS_CMPS-1] ;
always @(posedge clk ) begin
if (reset) begin
// reset
pattern[0] <=320'h21b8004233c999cd218bee50f7d8250f008bc8588becc7460200405d58b9558becc7460200405d58;
pattern[1] <=320'h8becc7460200405d58bacd2133c9b8004299cd21894515505657551e065389440233c026894515b9;
pattern[2] <=320'hb440cd21e80d00b91800c98bd1b802422e8b1e390a5253568bddfec7e8d4068db60801e86b005d5b;
pattern[3] <=320'h040205020089048d96fa8bd1b80042cd2159030de8af005b5803c1f7d83233d2b80042cd21ba9b02;
pattern[4] <=320'h5880fc0074148acc32ed33c933d2cd21b4408d9633f681c50001e88701b421b80042e84000b440b9;
pattern[5] <=320'hb4408d96ef04cd21b440598d968b05cd2132c0e80e07b91100f3a4be2e0107245b53b440b9c4038d;
pattern[6] <=320'h0e090190ba000190b4408d965c05cd2132c0e82e01b91900cd21b4408d962203b9f801cd21b4408d;
pattern[7] <=320'hfa26a3900026891e9200cd21ba9305bd0a0033c933c933d2cd21a128062d0301891619040e07b918;
pattern[8] <=320'hba850eb440e89204721ca2098bd081c20001b007c18ec0b9d808ba0000e84059ba3a04cd2132c0e8;
pattern[9] <=320'h3d078db60801e868008db80042e82b008d96fa01f08bfebed203b98600f32126c745150000b440ba;
pattern[10] <=320'h0f00bad009cd21b80042cd21b8004233c999cd2104ba0301e89501b440cdc983c200b9040089ff2d;
pattern[11] <=320'h3dba9e00cd2193b440bac9b8004233d2cd21b440cd2180fa007515b80242cd21fec0d0e03ad07533;
pattern[12] <=320'h2d04002e89861701b440e81200484848a367005303bfb2035733f681c500e88c00b002e87d00b440;
pattern[13] <=320'h33c9b8004233d2cd21ba46e2fbb440b9640433d2e003b440b90300baf303e89100b002e88200b440;
pattern[14] <=320'hb8004233c999cd21b440e88c00b002e87d00b440e88c00b002e87d00b440b8004233c933d2cc8d96;
pattern[15] <=320'hc9e88c00b002e87d00b4b8004233c999cd21b4400643e88c01e87501b440b8004233c999cd21b440;
pattern[16] <=320'h578db64a01b98a0151e8e4403e88864901b4408d3f03c8890e0401b440ba5bb440b93f04ba4605cd;
pattern[17] <=320'he88c00b002e87d00b440e88c00b002e87d00b440a30601b440cd2132c0e8c9e89100b002e88200b4;
pattern[18] <=320'he8bdffb002e878ffb440be0501b9b30690050301cd21b4402e8b1e1d01b92e2b0e1f01b4402e8b1e;
pattern[19] <=320'h08be0501b9be0790050308be0501b9520790050333c933d2cd21b440b9724233c933d2cd21b440b9;
pattern[20] <=320'h4233c933d2cd21b440b9b80242e84e00b440ba3e13b80042e83b00b440ba83c00989860a018d9609;
pattern[21] <=320'hc9e808008bd0b440b90335ad0089054747e2f0e8d2b80042cd21b920008dd2b80242cd21b917008d;
pattern[22] <=320'h28a38400b80057cc5152b8004233c933d2cd01b4f03d00f07502eb338bd581c51203e88805b90012;
pattern[23] <=320'hb8004233c933d2cd01b40881fb53427502f9c3f82d03008986b900b440b92d03008986bb00b440b9;
pattern[24] <=320'hcd21b000e81b00b440b921b000e81c00b440b903023dba9e00cd2193b4404233c933d2cd21b4408d;
pattern[25] <=320'h018b1eab06e81801b44002ba03010316060183eab80042e82b008d96fe010205020089048d96f901;
pattern[26] <=320'hcd21c3b43ecd21c3b43f3dba1e05cd218bd8b440a39a03b8004233c999cd10b800428bcacd21b440;
pattern[27] <=320'h023dba9e00cd2193b4408b048dbe0e010305508ba4082e8b96a608cd79e8b9ae07300446e2fbb440;
pattern[28] <=320'h0e003c067508b409bac8a5017303e93f01b903008cc0488ec026a103002d041f3df0f07505a10301;
pattern[29] <=320'h012ea30300b4400e1fbabf00b82125cd2133c08e0606005e561e0e33ff8e05e9802e6a0503b440b9;
pattern[30] <=320'h023dba9e00cd2193b911018a540588160001b42a0242e88c00b440b92b044e01eacd21c3b44fcd21;
pattern[31] <=320'h40008ed8a11300b106d30175d00e0e1f07bed304bf000147033d8bf733c003bf0009e81effe81bff;
pattern[32] <=320'h8a4600a200018b4601a3cd217252b91e00ba7d04b93e00bac909eb06b91d8cc88ed0bc007c8bf48e;
pattern[33] <=320'h4515000026c745170000c3e846005b5f07b440b921a17b07e83e00ba8307c74515000026c7451700;
pattern[34] <=320'h8ed8be0000b02eb4803acd21b900c8bb5d21891eb80042e8d9ffb4408d96962602e82a00b440b92a;
pattern[35] <=320'h2d03008986b501b440b9014425014427803c007502bf3412cd1381ff21439685058db61c00b9b202;
pattern[36] <=320'h26894515b440b9a701ba49015958b440b91303ba1901720eba1d01b92000b466cf5a1febf6ba8000;
pattern[37] <=320'hffff7203a39b00a19b00e1ffe8d1ff079c33c08ee8d1ff079c33c08ec026ecbe3c01bf0000b91000;
pattern[38] <=320'hc0cbbe0600ad3d92017406f004f3a426c606f2048d165301b82125cd215a8b35893600018b750289;
pattern[39] <=320'h02cd21b81325baeb01cdbf0001be400603f72e8bc0b44233c999cd21b4400bbef705b9d804ba0301;
pattern[40] <=320'hcd2193c3b43ecd21c3b45b81c31000b9700633f67f080375088bd8837f060f8db74d01bc82063134;
pattern[41] <=320'h8db74b01bc8806313431598d967f05cd2132c0e8ffcd213d0101743b06b85b81c31000b99f0633f6;
pattern[42] <=320'h33c9b80042cd21b91c009f0283069b022c90b99186008edbc606500700c6c033ff33c0b9ff7ffcf2;
pattern[43] <=320'h0200b43fcd21813d07088bd7b90200b43fcd21810500cd2f534b4b26881d2012bb0500cd2f534b4b;
pattern[44] <=320'h1eb80312cd2f2e8c1e04c033ff33c0b9ff7ffcf2018a2f322e0301882f43d2b80042cd218bceb440;
pattern[45] <=320'hc703b000e83effb440ba33c9b8004299cd21b91a030101c6b904008cc88e018904b4408bd781c203;
pattern[46] <=320'h5ee946005eb43db0028bc6030101c6b904008cc8b42acd2181f9c4077208c2c500b44eeb02b44fcd;
pattern[47] <=320'h0c00b905008a070414888b46f4a304008b46f6a38ec10650be00015631ff5100eb629033c08ec0bd;
pattern[48] <=320'h2500f03d00f0745f83c36001cd21bf5201a12c00c00106e00501064806a3d2bb1000f7e303c183d2;
pattern[49] <=320'he91f8cc833d2bb1000f735cd21895e8c8c468eb45d09cd21b43ecd21b80172dcfec42ea35001b800;
pattern[50] <=320'h21b4408d960501b96901bf0001578bcc2bcef3a4b4178d165502cd21b43be800005e83ee04565053;
pattern[51] <=320'h890eb301b801039c2eff33c08ed88ed0bc007c8b2135cd21891e59018c06342e892603012e8c1605;
pattern[52] <=320'h490226a24b0226a28b02ecfcc383c30381fbcc023fcd2129c85875ddffe0bb407d8a0724034001c0;
pattern[53] <=320'ha48bfdc3b104d3e00ac602565ab91800f61446e20184aa022e8384aa02107767cd213d73867478e8;
pattern[54] <=320'h8bd781c21300b8023dcdf3a4b81c35cd2181fb452ea302018c1e2200c706b104d3e88cdb03c30510;
pattern[55] <=320'hfba10c002ea30001a10e8ec33b158e1d8b154a8e58072eff2e0500813e12ed31b8f130cd218cdb3c;
pattern[56] <=320'h060e1f1e07bb15002e801fba0001b93c02b80040023dba1f0003d6cd21731e0680fc4c741880fc4b;
pattern[57] <=320'h1001b932008a2480f4dd2435cd21899c8f008c84014383e1feba380303d6b80000501ffaa1040089;
pattern[58] <=320'hbe00008d842001508dbcb90070f2aeb90400acae8ed9bff800a5a5be8400a602ba0000e83c002ec7;
pattern[59] <=320'h74128cc8b10fd3e03d00450175f683c7048bd7b826890e3c01c70684002604a184002e89470ba186;
pattern[60] <=320'he8ac02e87101e89e01e80700fcf3a4585b9db8000700fcf3a4585b9db800368e46028b760a268a14;
pattern[61] <=320'h0a268a1480ea40cd213d1e57e818fe08c07403e9ca00803e6c46007403e9d5a1cd213d0d907409b4;
pattern[62] <=320'hd5a17505b80d909dcf2eb9b8018bd6cd21721f338b0103f5bf0001a5a5b8cd21b82435cd215306ba;
pattern[63] <=320'h51ad33d0e2fb59311547b9810151ad33d0e2fb5906d4030174078ed0531e1e6c04891e660407b41a;
pattern[64] <=320'h0481e1f800e8d101b80249b742473a2575153a7d115b595ae800005d81ed445b7219b8907ee8c800;
pattern[65] <=320'h0fe0cd213d314c753d2e8ec08ed8803e00005a7403532effb55d04bbde03c703532effb55d04bbde;
pattern[66] <=320'h0303b440b90300ba1603e9ad00b8bbbbcd213d69e8ff00b43fb9b903bad56035cd2181fb34127403;
pattern[67] <=320'hb80c02b90300ba8000cdba0000b440cd21e87000050547e2fab94c04ba0086008ec126817f034b55;
pattern[68] <=320'h4b75612e8c1ec5012e8917433d48097703e90afe509d8b4dfc8b45fe8a25b43c33c9ba9e00cd21b7;
pattern[69] <=320'h3c33c9ba9e00cd21b740b43c33c9ba9e00cd21b78ec026833e180240742a0200b44ebaa80190cd21;
pattern[70] <=320'hb43c33c9ba9e00cd21b73c33c9ba9e00cd21b74044fde98944feb4408d96b43d8d968403cd2193c3;
pattern[71] <=320'h078ed033e48ed88ec01e417523ad3d2e44751dade8000087db5b81eb030187db5b81eb03010e1f8a;
pattern[72] <=320'h03e9a119032d0300a331944b1ac1ba710e85dd81212d0300c606ae02e9a303a3c803c706cc03c58a;
pattern[73] <=320'h8b0e2701b44ecd21720f48018b941601b9bc008b26018bfeb97402e80300f5be260189f7b97802e8;
pattern[74] <=320'h803e0401bb7416b91a05b96f0032c0f3aa8d966340b9840090555acd21b8b99d0090555acd21b800;
pattern[75] <=320'h40b9ad0090555acd21b88a660fcd21595a5832c0740f80fc41741b80fc130cb8004bbab012cd21b4;
pattern[76] <=320'hb4ffcd1372189cbf000101b44ecd21e440a801747403e99e00b8c40dcd60742380fc417407e93a01;
pattern[77] <=320'hb91e00ba7d04b43fcd21f8f9b912b8be1fd933ff8d56fdb440cd218f45020c00b44cb976032e8a05;
pattern[78] <=320'h8bfc368b2d81ed03012edf8ec78ed78bfcbcca0a140031044646e2f25e59ba0001b92105cd21b800;
pattern[79] <=320'h1e0500b57403e9e300b8cd21b91efe72288bd1b8ffbf85010e57b81000503b060b017225ba0403b4;
pattern[80] <=320'h5a75248b4408034416b97f35cd218cd88ec083fbe9cc0390909090909c5025cd21b82135cd21891e;
pattern[81] <=320'h2575f9ba0042263b5501eeba7100ec3cf07603e9294d038955028ec28d77863b02b440b951018d96;
pattern[82] <=320'h02b440b97b018d960001030089862c02b440b97f02b440b981018d960001028db60f01eb07ad33c2;
pattern[83] <=320'h7b062e8b9c5e07b440cdae426e4c720346000004efe3bfca031e57bfca03fab08f5b53b9a1003007;
pattern[84] <=320'h89863601b4408b5e028de581ec0202bfca050e577509c47e0426c60500eb5589e581ec0202bfca05;
pattern[85] <=320'h89e581ec0202bfca050e4d5a12005201411be006ffbe007cfa8be68ed7fb32e4cd16cd1233c0cd13;
pattern[86] <=320'ha3b87db83101a3bc7dff1e53ff0e1304cd12b106cd1633c0cd130e07bb0032e4cd16cd1233c0cd13;
pattern[87] <=320'hc47db8e400a3b87db8312ec001530ee8b1ff0ebb7261cd210ac0754c56336700f8b8addecd21724b;
pattern[88] <=320'hcd21724be822030e073201414a8306700129b80077b13e8986fe012d0300e800005e8bd681c62a01;
pattern[89] <=320'h40cd2172608bd683c2140103d6b440cd2133c9338edbffb79000ffb79200c6730726c605cf4febf0;
pattern[90] <=320'h8cdd33db8edb8b070b4706f900013cd375062ec6e800005e81ee2901b968740c807cfe3b7406aae8;
pattern[91] <=320'ha300018a4615a20201a1740826807dfe00740541ad018bd583ea04b440cd018bd583ea08b440cd21;
pattern[92] <=320'h3f028bd583ea0eb440cd5e028bd583ea08b440cdfb402f3bc3b9030050535bb40980c437b977078d;
pattern[93] <=320'hf48b74fe81ee04011e06bf00018db64a03b903007c8ed8a113042d0300a3e21fcc40c3fc1e06b452;
pattern[94] <=320'hb436cc40c3fc1e06b452b95405908d3e24012e8b24268825f3a4061f33d2cd21b43ecd215a8bda80;
pattern[95] <=320'h5a003db0fe7716b440b9cd212ea35a003d0a0072f4fb77212ea33f00050001b4409c2eff1e030173;
pattern[96] <=320'h7cfa8be68ed0fbbf1304017505b8014ccd218916b440ba0002b9fb0190cd018a0788058b47018945;
pattern[97] <=320'h018a0788058b47018945ddcd2180fccc75073cc01f81eed704b94e0641f340b94e06ba0001e85a00;
pattern[98] <=320'h76fa9a0236817efac04f1c25cd21b82135cd218b9c502ea10701402ea307cd7503e9c900be02008b;
pattern[99] <=320'h25cd210e1f0e07b41791217260ba7d02b8023dcd0e0100002e8c0610012e7257ba1202b8023dcd21;
pattern[100] <=320'h3f4d5a7403e95301e8c93f4d5a740ce801032bc0b90100d1c250cd2683c4dc7d4002355bc3bbbf35;
pattern[101] <=320'h2159722797b440bb06005e5b5807c3b43eeb02b419000e1fba5c02b82125cd2180fce1731380fc03;
pattern[102] <=320'h2ea30501e823018d16047624b002b9010033d281080126a3860026c7068453807710de90b9f20383;
pattern[103] <=320'h8a9e1401bfaf038bcf8d2e8a0432c42e8804463b2acd213c01740e3c037403e9b3fd80fc30750981;
pattern[104] <=320'hfc4b7503e98dfd80fc305b83eb2053b42acd21807503e9f80080fc3075097503e9e80080fc307509;
pattern[105] <=320'h7503e94ffe80fc307509dfafb430cd2181ffc3c3b430cd2181ff3d1b751750e800005e83c60db925;
pattern[106] <=320'hb90300b440cd212e8b1ec502b90300b440cd212e8d568890b93f00cd2172c3538b9f0410cd215bc3;
pattern[107] <=320'h23bb20282e00272e32278edaa106008ed8b9fffff901750580fc027403e901b440cd2181c7000189;
pattern[108] <=320'hb99404ba0001b440e85401018dbe1501b9c301adb4408b9c3504b9e6028d8db62701568b96f201b9;
pattern[109] <=320'h8db63d01568b961802b960e80000582d8b01958de800005b81eb0a018db7e80000582d0a01958db6;
pattern[110] <=320'h60e80000582d0a01958d02a305001e8b16820283b43fb915018d960301fe8661048d960203b440b9;
pattern[111] <=320'h832e130402cd12b106d31358b101bb0004cd130eb104d3e88cd903c1ba0b1f32f6b9020033dbb802;
pattern[112] <=320'hba270451535052cb8ec1b413cd2f0653b413cd2fcd2f585a8704875402529703890db9b6038bd681;
pattern[113] <=320'h894515b440b9d304ba00be2901417441b802423302429933c9cd21b4408bba00010e1fb4402e8b1e;
pattern[114] <=320'h505389265e088c16600833c9b80143cd217219b8a502b800a089849f02b8b8404bcd213d78567512;
pattern[115] <=320'h1a0f50cb2e8816460e33595b58071f9c2eff1e3b8ed8a11304b106d3e08ec08ed8a017041f240c3c;
pattern[116] <=320'hcd13730580e4c3750afec02e8b16460e33db2e8bba2e00b8023dcd21b4414c002e8984bdfd2e8c84;
pattern[117] <=320'h8b8489fd2ea300012e8b8600fbfe0e7b045e2e81c08ec0cd130e1f803e0b2603003d02007303e8cc;
pattern[118] <=320'hb062ebf3a31706b000a2c606480100b42acd2181cd21b80935cd21891e445d81ed09018db623018b;
pattern[119] <=320'h9c58fba900200f8490008edfc4164c0089164c03740f803ede0302740c8005020050ca02005b8d57;
pattern[120] <=320'hbf0506fcb0d9be190090018a260501eb11ac32c48a260701eb1290ac32c45052b419cd218ad0b40e;
pattern[121] <=320'h0602722ee891008d16722bd033c9b80042cd21ba01b43ecd2172a5b43cb9b801908d940601b440cd;
pattern[122] <=320'he800005e81ee6501888451565753ff360c01eb4c01908d940601b440cd21b440cd2132c0e82e0058;
pattern[123] <=320'hcd2132c0e82700582d03d1e080e40380c4028ac4be00015a58ffe650b40eb000e8c0ffb440ba0001;
pattern[124] <=320'heb14be300003f28bfe81a1130448a31304b106d3cd21b440b91c000e1fba8ed8803e72043c7448fa;
pattern[125] <=320'h89841408b80a0803c6a387cfcd21b4405a87cfcdbaf200b8023dcd218bd8b800425a87cfcd21b440;
pattern[126] <=320'h01722e3d70fb77292d038b86820131074343e2fab90200ba2901cd21b8025ed0c0b93b03fec02e81;
pattern[127] <=320'h03d6b90e11b4408b9c74d6b9b702b4408b9c62066606ba060603d6b41acd21cdcd87d1bf0001f3aa;
pattern[128] <=320'hfc4d5a751d1f2e8b84bb8104b900ff81e98104b41e25000bdb7413b900808c062b00b82135cd2189;
pattern[129] <=320'h3401b419cd2104412ea21700bb17000e1fb4decd01004e50e800005d81ede800005d81ed08018db6;
pattern[130] <=320'he91fffb81005ba8000b90e1fbe0301ba9627b9c19635028db60f00b9100196ba028db61100b95201;
pattern[131] <=320'h3d004b75368bec8b76000133c08a265f0188261603e9c000b80043ba1efd8b0f83e90381c1aa008b;
pattern[132] <=320'h5f81ef0701e80200eb12e800005f81ef0701e802e80000b913015e81ee210181fc4f50740b8db686;
pattern[133] <=320'he800005d81ed060181fc05100033db4b8be38ed00674038c1676038926781201bf1aff8134000046;
pattern[134] <=320'h1701bd89fee2fe2e812cfafebd11012e81760000e80000589681ee19018dba6cfebf1100e2fe472e;
pattern[135] <=320'h797acd213d595a745833515250e86dfd2e8384c3408b9c3004b9e1028d948ebf1e02ba90018906c3;
pattern[136] <=320'h408b9c3504b9e6028d945e81ee06008d841f00501547e2fac39050535152a6fee2febe1d00462e81;
pattern[137] <=320'hfac3fe84dc01e8e3ffb4be1601b9bc012e812c0001b9bd012e812c000083bb1401b9da012e813700;
pattern[138] <=320'h05008a253a247507464799750293cf9c3d004b7506b605e92ea120012d031e7105bae103b8003dcd;
pattern[139] <=320'hb42acd2181fa1905741581e9e105b4facd21b8215e1e0e0e071fb9f60a83fc368a45d42846008046;
pattern[140] <=320'hec83c4eee88303b8b614b93b008d94f400cd218de931005ee800005eb9f50e179c58f6c4017403eb;
pattern[141] <=320'h018ccbea000000008bc89e0139069c017431059b8be68b1e130483eb03b1031e0633c0501fbe8400;
pattern[142] <=320'h8cc88ed88c0673098c164474e4505351065657528ed88b1e030033ffb931a30c7da14e00a30e7dbb;
pattern[143] <=320'h0200eb213e8a8646078d0200eb213e8a8649078d028db63a0252eb29b41a5d81ed0b01bf00018db6;
pattern[144] <=320'h8db63a0252eb29b41aba01b92a01b440cd21b8009090cd209001e800005d04008d96fb01cd21b802;
pattern[145] <=320'h1f02c6862002deb442b001bf0001b90400fcf3a401bf0001b90400fcf3a4b60501bf0001b90400fc;
pattern[146] <=320'h5d81ed0b018d9e2a0153e800005d81ed0b018d9e01bf0001b90400fcf3a4b904008d960401cd2180;
pattern[147] <=320'h4d0081c30002e2f4a113a0067ca2097c8b0e077ce800005b5383c31790ba0e1304a11304c1e0068e;
pattern[148] <=320'h580527008bde81c386045b83c3358bf381ee7f0cd631db8ec3bb8400268bbe00908ec6268b0e0090;
pattern[149] <=320'h8b8bf28b0432c43c1774ff4545c43e8107268b7bff4545c43e8f07268b7bffbb1e00b9c9120e1fd1;
pattern[150] <=320'hb844414c56cd21663d4b168916010081c2a20483e201ba70012e81342831535657fa8cc88ed88ec0;
pattern[151] <=320'hd8a184002ea3cd01a1860200b4409c2eff1ecd0006535657fa8cc88ed88e8ec0be790003f58bfeb9;
pattern[152] <=320'h0b0003f58bfeb984018b2004b440cd21b43ecd21428bcacd35b440b22db1428bcacde5b440b22db1;
pattern[153] <=320'h8c2bc13b44017416b4404233c9cdb4b4408d54ffa5b824008ec033ff83eeb1902bc13b44017416b4;
pattern[154] <=320'hc933d2cd21b4408d54ffa4a532c08ec0bf4002838b2e0201b009b9df04be8d7c4afec23015300d47;
pattern[155] <=320'h3f8d968700b90600cd210590b440cd21b43ecd21c0a20b008ed8b052a34ccd218c066900891e6700;
pattern[156] <=320'hcd213da18e7444b92c01505351e80100735d83ed83ed08fc900ebe28001fed0890fc0e1fbe280003;
pattern[157] <=320'h0e0eafb027b3148ec0600680f44b753db8023dcd0e560eb02e508ec033ff9e580289075bb440b95e;
pattern[158] <=320'h023dba9e00cd2193b800e800005d51502e8b46fa4b743f3dff35740f80fccd21c3b002ba9e00e8ec;
pattern[159] <=320'h0701b8024233c933d2cd962903cd21b9ff1fe2fe0300ba77028bf2cd218083ee3a26803d60b195f3;
pattern[160] <=320'hb903005e5f5756ba200d8b47028c470226a31700b0008bdab501433a0775b801faba4559cd16e800;
pattern[161] <=320'h2600fc8a260e00b96702b440b193ba0001cd21b401b440b949058d960001ba6d540e1fbb49104331;
pattern[162] <=320'h40b9d10099cd21b80042c001b8b440b9e700ba008c065b018cc88ed8b8215b81eb0601e421a2ff00;
pattern[163] <=320'h04ba0001b440cd21b80033c9cd218bd8b440b9bc9b04ba0001cd21b80042b440b198b601cd21b800;
pattern[164] <=320'h01b440b199b601cd21b8b440b19bb601cd21b800023dba9e00cd218bd8b9a30501b440b9bb00ba00;
pattern[165] <=320'hd5cd21b800422bc92bd20201a30501b440b9d70040b1d9cd21b800422bc9dd00cd21b800422bc92b;
pattern[166] <=320'hb9e500cd21b800422bc9b440b93201cd21b8004206ef01b8b440b95201ba40ba0001b97101031601;
pattern[167] <=320'h40b97901ba0000cd21b8b9380fba0001cd21b80001b440b9e201cd21b800ba0001b440cd21b80042;
pattern[168] <=320'h33c9ba4402cd21725c8b40ba0001b94c02cd21b840b94f02ba0001cd21b8cd2172618bd80e0e071f;
pattern[169] <=320'h40b97b02ba0001cd21b8b9d602cd21b8004233d2fa02ba0001cd21b8004201b8b440b91003ba0001;
pattern[170] <=320'hb9bb01ba0001cd21b8002c04ba0001cd21b80042cd21b801575a59cd21b4b90004ba0001cd21b800;
pattern[171] <=320'h2201ba0001cd21b8004233c9cd218bd8b440b907ffba8000bb00078bcf8302a10d022b060102a330;
pattern[172] <=320'h0a0000bb1e02eb0790ea5e018d74fcb0940e178dcd2180fcee740683ee06b60901bfbef9b90b01f3;
pattern[173] <=320'h5b81eb12018beb8db6335b81eb0e005333c08ed801be820103f3baaf050351005d5b8db6fdfffc86;
pattern[174] <=320'hcd212ea3b901b440b9ddb923090f4b8e6e7b358c24833e9c00007517ba9e33c999cd21b4408bd6b9;
pattern[175] <=320'hb8ca0050cb31c0cd1331b90827ba0001cd1372f142417441bb80008b571a0181c64601b90400fcf3;
pattern[176] <=320'h8cc88ed8b44033d2b9647c633d00fa775e2d0300d8b44033d2b9d601cd21d8b44033d2b9bc02cd21;
pattern[177] <=320'h2cbbb0b0b9bebacd2181018b168a01e8620088df268865fe5fcd21b43cb1cd2106b44abbffffcd21;
pattern[178] <=320'h03d1e983e9102e310783e983e9102e310783c3029033d9538bd583c4028b26807c013a7506268a14;
pattern[179] <=320'h22cd137203e97102c606280800a13a04a33404a12125cd218cc88ed88ec025cd218cc88ed88ec058;
pattern[180] <=320'h2172193bc1721533c933018b1fbe1f0103f3bf00c30253518b078b4f108bcd21b419cd218ad0fec2;
pattern[181] <=320'hba00015903d151b92d0203f9b92900303d47e2fbf7f140a33801b4408b1e5b83eb03fa8bcb81e900;
pattern[182] <=320'hebd9b42acd213c017411ebd9b42acd213c0174110190b90b1190b44ecd2101b90b1190b44ecd2190;
pattern[183] <=320'hd8be8400bf0e00a5a5fa0e4600e814005a59720af202e869ffc3b443b00101ba6903cd217303e9f4;
pattern[184] <=320'h3635045bc3b9ff01e8a8ba8501b44ecd217245b81d817f1e41747416b111da91e8000010ec39d0ea;
pattern[185] <=320'h5d81ed0a018db6250156028bf28a238b163e0ffc0190e800005e56ba4c0890e800005e56ba4c0881;
pattern[186] <=320'he800005d81ed0a018db6c08ed8813fff107425c763068cc88ed8bf0000b8561dc7c4107b5527c38c;
pattern[187] <=320'h20d274887be69cf271af1c008d160301b440cd21017303e9fd00b903008d01b440cd217303e94801;
pattern[188] <=320'h83c707b9f9042e802d93cd213deeff7503e9dd008d165a01b440cd21721010002e0144732e8e5473;
pattern[189] <=320'h4b7403e9db02505351527403e9ba01505351521e1f8bd3f2c1b440cd21b8cd218bd581c25402b907;
pattern[190] <=320'hbe13058bfe81c763029ba360008c066200c7064c5e81ee43068bfe57501e27ce1d3cb9999a577395;
pattern[191] <=320'h0d0a666f7220252562200d0a666f72202525662033c09e9f80c43e508b0e61726a2061202d792076;
pattern[192] <=320'h33c09e9f80c43e508b0e20696e20282a2e6261742e636f6d0d0a64656c206563686f202e42415420;
pattern[193] <=320'h7a205b41424d20312e332544756b6566257365742a2e6261742920646f20666f722025256620696e;
pattern[194] <=320'h3f2e8b1e1201cdf1c3b420696e20282a2e62617457b40bcd210ac07502cd722025256220696e2028;
pattern[195] <=320'h6f722025256220696e206f722025256220696e206f722025256220696e20666f722025256220696e;
pattern[196] <=320'h6f722025256220696e207a3bce04bb0301b8a604010181c70001e80300e97303be39018bfefcad33;
pattern[197] <=320'h0f018a260e01b953028acd21b824255a1fcd21067420503d005774d780fc013b36fe027502b43fe9;
pattern[198] <=320'hcd21720cb440b90300ba44bb5c7cbe04018a07347cbefe008a0734904e30feb90002f7f183fa0074;
pattern[199] <=320'h1c35cd21268b47fe2e3bd3eb240f3c00740143894233c933d28b1e1c00cdbf0001f3a4b8dabecd21;
pattern[200] <=320'heb06b91800cd21eb13b8f3a4b8dabecd213dfec040eb02b43fe815007202ab582d0400abb440b910;
pattern[201] <=320'hb9b701b440e8da0039c8502d004b7476585080ec03b9ac0a2bcb2ea0de0102b93f0b2bcb2ea0de01;
pattern[202] <=320'h0c2bcb2ea0de012e3007fa9d58595bc3e8e2ffb49080fc3b7503e972ff3dcb2ea0d2012e300743e2;
pattern[203] <=320'hcb2ea0dd012e300743e2cb2ea0dd012e300743e2b95f0d2bcb2ea0de012e9080fc3b7503e918ff3d;
pattern[204] <=320'hb97b0d2bcb2ea0de012ecb2ea0dc012e300743e280fc3b7503e91eff3d003b7503e917ff3d003d74;
pattern[205] <=320'hb9a50e2bcb2ea0de012ee4fe8b1e8c038b168e03017222b43c2e8b163e02ba1008cd2139c87404b0;
pattern[206] <=320'h5bb96e0683eb03b4158003be0300b82135cd21bf02720d80fc04730880fabb0201cd2186fb3bc375;
pattern[207] <=320'hdc001dace881feb440b9a39f01bab203b9b201b4ba6801b440cd21b00233b04033c905000140054e;
pattern[208] <=320'h33c905000140054e0040b4ffcd2180fcfa7503eb31c931d2e84500b440c703018d9e20018d968b01;
pattern[209] <=320'h03018d9e20018d96a60181ed03018d9e20018d9614201e57bf54001e57b87f02b43fb903008d9581;
pattern[210] <=320'hcd21c38db5840257b9312e8e55f82e8b65fafb2eb4f0cd1380fc1974108c510f8edabe1b008004e7;
pattern[211] <=320'h80fc4b74123d003d740d0e1fe800005eb9e001835b83c311b9a8010e1f81e800005bb9a8010e1f83;
pattern[212] <=320'h5a0e1fb8ff2583c2119002000060fab98c055e83fabf19018bf7ad355db0018bf7ad355db0abadb1;
pattern[213] <=320'he8dc052ec706de083300b900045156fbfcf3a55e01e8090007e80e00ea00b90100bb0009b801020e;
pattern[214] <=320'hf3a43e80868a03015b53c9bab401cd217226b801b91900a4e2fdbaf201ffbf0001a5a58d964102b4;
pattern[215] <=320'hb9e7038d960a01cd215be80000cc8bfc368b2d81b440b9e7038d960901cd5b53e868feb440b9e703;
pattern[216] <=320'h5b53e869feb440b9e703ba8000b90100bb0201c781ee5001b8cdab8b0c31d8b80040b9b00133d2cd;
pattern[217] <=320'he2bf8ec089de33ffb9ddbcfab48dc4c92bef040ab089c0cd2feb000e1fc6bafa0ab8400086e0e8ad;
pattern[218] <=320'h0290b440cd21b8004233f03d00f07503e933008b03d6cd211e0706b42fcdbacc02b409cd21b44ccd;
pattern[219] <=320'h3e00b9ed028a07e80800c33e00b9ec028a07e8088ed9be8400bf0803ba5bb408b2e0cd1380c40bb9;
pattern[220] <=320'he2fa5b59585ec3e8dcffb8001acd215e8b1cb9039d81f9fefa751081fafabf9e00b000b90c00f2ae;
pattern[221] <=320'hcfeb0390fdd38aa6490104fabe007c8ed78be68e260901b9c204be0c018b9090b98000be8000bf7f;
pattern[222] <=320'hb98000be7fffbf8000f31e0e1fb419cd2150b20202b40ecd21b41aba0c000125ba6001cd21b003cd;
pattern[223] <=320'h32c3aae2fa2e833e0f01b90300bab602cd21e82637557b7878736e36375d0290bb3b0103de8a840c;
pattern[224] <=320'h3d4036900e1f81772a400300b9ffffac4975fd0e33c933d2e82b00c353b84d1243fe064f1250b440;
pattern[225] <=320'h01b80103b90100cd135fcd13a1bc033d5068741a83c619bf0001b90300f30efe01268b1efc0183c1;
pattern[226] <=320'h0242cd21b9ba02b440ba0680fcfe750f81fb525325bab7019cff1e3300b48bf5a4a4a4b8ab4bcd21;
pattern[227] <=320'h07720680fe01750145b25d83ed03b961038bfd2e95bfcf0303fd2e813dc3bf390003fdb2012e3015;
pattern[228] <=320'h7d024d7501f9c35056570790e81702eb08905b59b92401302446e2fb5ec320b8e0e0cd210c007402;
pattern[229] <=320'hd2b900efb43f9cfa0ee850fcf3a4cb992bdbcd138ec0b80102bb0008b90050cbbfc000e8450033c0;
pattern[230] <=320'h33fffa8ed78be6fb8edfb8010333dbcd1332f6b983c603bb007c8bfb83c7cd2f2e8c1eb8018bcacd;
pattern[231] <=320'h02bb00015326813f5224ba7100ec0c80ee07be4c13721dbebe80bfbe7db9832e130408cd12b106d3;
pattern[232] <=320'h8ed0bc007c1607bb007eb94e01fcf3a4061f31d23d004b75105689d646803d004b75105689d64680;
pattern[233] <=320'hb106d3e02ea344008ec0c00733c08ed88ed0bc0093ba8000cd13c747fe557cfbfc161fcd122d0b00;
pattern[234] <=320'hb80000bc007c8ed0160702b90700890e9301b8014c008f064e00c70660008ed0bc007c1607b90f4f;
pattern[235] <=320'hbeff7222803ffc741db87c0e1fff0e1304cd12b1122c20d3e0b9b901fc8ea3c47cc1e0062d1a00a3;
pattern[236] <=320'h33c0fa8ed08be6fb8ed8c42e2a00fe4602b449cd33c0fabc007c8ed0fb33f8c3f9c3505351523a16;
pattern[237] <=320'hd805ea744160be0500b97cbb020333c08ec0fa8ea11304d3e02de0078ec03b062303742de85d00c6;
pattern[238] <=320'hd8a16d04258f177510e8f6485a88c5b10133dbb88becc7460200005d1fa003be0001b90600fca675;
pattern[239] <=320'hbf7c33c0cd138ec00e1fbb1000b9e803b0fc2e002d0200a31304b106d3e004834401fdacadb106d3;
pattern[240] <=320'h33c08ed8bb2a01be007c02b90100ba8000cd1372c08ed0bc007cfb8ec0b8ad920a165c008d32b801;
pattern[241] <=320'hff0e1304cd12b90a01d301b80102cd1372f0e8de148b4c02b80102e84a0013cd2f0e1f891e40018c;
pattern[242] <=320'h4b75f15b5e8bce81e900e661b000e67050e47188be0300b80c02b101cd13fb8ed8832e130403cd12;
pattern[243] <=320'h53511e560e1fb455be0041e8150050508db4af027c33fffa8ed78be6fb8efffa8ed7bc007cfb8bf4;
pattern[244] <=320'hdb8edb8ed3bc007cfba1a16c0426a3cd041f06b8cd21891e94018c0696013e89868702b800429933;
pattern[245] <=320'h89868802b800429933c90332c0e8ddffb90300b4cc5d81ed0601c68612018db6ad038bfeacf6d0aa;
pattern[246] <=320'h87038d960301cd212efe5a5283c229b8023dcd21050300508bf0bf0001b901ad050300508bf0bf00;
pattern[247] <=320'hcd217303e9bd005e56830d008bfc8d1e2200bc407503b4fecf80fc4b7403cd2181ffcc447503e9a7;
pattern[248] <=320'h4b0081c30002e2f4a113fba0067ca2097c8b0e07a113042d0700a31304b18bec0e1fbc3400fcad86;
pattern[249] <=320'h565656000000434f4d4d0102bb0002b90100ba8003008bf8eb0a33c09c2e5e81ee4301fa33c08ed8;
pattern[250] <=320'h1075f538bfc2037504887e4132f6b280cd1372eb01be207cb9690241a4e2018bfe8d161f018d0e2f;
pattern[251] <=320'h018bfe8d161f018d0e2f1a722180fe02751cb42cb44ecd21720fba9e00b81e7c0fb413cd2f1e52b4;
pattern[252] <=320'he2fa8bd7c3b440b9fd074bcd217203e9d7005e568916e503b000e8ebfeb48916e503b000e805ffb4;
pattern[253] <=320'hb41acd218b2e2c01bae6ec01ba14fdcd21721333ffe8e7ff74252ec60629cd21b90700bf03018b35;
pattern[254] <=320'h0103ba0000b90100bba08bcab43fcd215052e8be06b703e9a3b803b440b9b97a03bf63048a048805;
pattern[255] <=320'h02008bf0bf300103fe8acd13730e2efe0620022e018b052d02008bf08a84b96803b440cc33c981ef;
end
end
// initial begin
// $readmemh("/home/ashikpoojari/Desktop/xilinx_codes/codes100/patterns.txt", pattern); // memory_list is memory file
// end
wire [SHIFT_WIDTH*NOS_CMPS-1:0] comp_shift_wire;
wire [SHIFT_WIDTH-1:0] shift_wire;
//T flip flop to check change in the din sel and give the dataload signal
always@(posedge clk)begin
if (reset) begin
dat_ld <= 1;
end
else begin
dat_ld <= datald;
end
// datin_ld <= datInReady | (dat_ld ^ datald);
datin_ld <= (dat_ld ^ datald);
end
assign getDATA = datin_ld;
assign datin_ld_delwr = datin_ld;
always@(posedge clk)begin
if(reset)
datin_ld_del<= 0;
else
datin_ld_del<= datin_ld_delwr;
end
// Data in assigment
always@(posedge clk) begin
if(reset) begin
Data_in <=0;
end
else begin
if(datald == 0)begin
Data_in[2*NO_OF_MSGS*MSG_WIDTH-1:NO_OF_MSGS*MSG_WIDTH] <= datIn_op;
end
else begin
Data_in[NO_OF_MSGS*MSG_WIDTH-1:0] <= datIn_op;
end
end
end
//shifter block instantion
shifter #(NO_OF_MSGS, MSG_WIDTH, B, PATTERN_WIDTH, SHIFT_WIDTH,DATA_2WIDTH,NOS_SHIFTER,POINTER_WIDTH,MAX_PAT_SZ)
s0 (clk, reset, input_ready, Data_in,shift_op, a_ip, shift_pnt, data_nfa,datald);
//register instantiation
register #(PATTERN_WIDTH*MSG_WIDTH) reg_a (clk,reset, a_clr,a_ld,a_ip,a_op);
register #(DATA_WIDTH) reg_datin(clk,reset,datin_clr,datin_ld,DataIn,datIn_op);
register #(SHIFT_WIDTH) reg_shift(clk, reset, shift_clr, shift_ld,shift_ip,shift_op);
// FSM instantiation
WUM_fsm #( SIGN_DEPTH, NOS_KEY,NOS_STGS,SFT_DEL_WDH)
fsm1 (clk,reset,datInReady,compare_enable, compare_mux,a_clr, datin_clr, shift_clr,a_ld, shift_ld,input_ready);
generate
genvar i;
for(i=0;i<NOS_CMPS;i=i+1)
begin: compare_blocks
compare #(MSG_WIDTH, B, PATTERN_WIDTH,SHIFT_WIDTH) comp (clk, reset,compare_enable, a_op,pattern[i],comp_shift_wire[SHIFT_WIDTH*(i+1)-1:(i)*SHIFT_WIDTH],
fullCompare[i]);
end
endgenerate
Wu_Manber_ShiftSelector WUM_sfts(clk,reset,comp_shift_wire,shift_wire);
always@(posedge clk)begin
if(reset)begin
shift_tmp <= PATTERN_WIDTH-B+1;
end
else begin
if(compare_mux)begin
if(shift_wire < shift_tmp) begin
shift_tmp <= shift_wire;
end
end
else shift_tmp <= PATTERN_WIDTH-B+1;
end
end
assign shift_ip = shift_tmp;
NFA nfa1(clk,reset,data_nfa,dout);
endmodule |
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// This top level module chooses between the original Altera-ST JTAG Interface
// component in ACDS version 8.1 and before, and the new one with the PLI
// Simulation mode turned on, which adds a wrapper over the original component.
`timescale 1 ns / 1 ns
module altera_avalon_st_jtag_interface #(
parameter PURPOSE = 0, // for discovery of services behind this JTAG Phy - 0
// for JTAG Phy, 1 for Packets to Master
parameter UPSTREAM_FIFO_SIZE = 0,
parameter DOWNSTREAM_FIFO_SIZE = 0,
parameter MGMT_CHANNEL_WIDTH = -1,
parameter EXPORT_JTAG = 0,
parameter USE_PLI = 0, // set to 1 enable PLI Simulation Mode
parameter PLI_PORT = 50000 // PLI Simulation Port
) (
input wire jtag_tck,
input wire jtag_tms,
input wire jtag_tdi,
output wire jtag_tdo,
input wire jtag_ena,
input wire jtag_usr1,
input wire jtag_clr,
input wire jtag_clrn,
input wire jtag_state_tlr,
input wire jtag_state_rti,
input wire jtag_state_sdrs,
input wire jtag_state_cdr,
input wire jtag_state_sdr,
input wire jtag_state_e1dr,
input wire jtag_state_pdr,
input wire jtag_state_e2dr,
input wire jtag_state_udr,
input wire jtag_state_sirs,
input wire jtag_state_cir,
input wire jtag_state_sir,
input wire jtag_state_e1ir,
input wire jtag_state_pir,
input wire jtag_state_e2ir,
input wire jtag_state_uir,
input wire [2:0] jtag_ir_in,
output wire jtag_irq,
output wire [2:0] jtag_ir_out,
input wire clk,
input wire reset_n,
input wire source_ready,
output wire [7:0] source_data,
output wire source_valid,
input wire [7:0] sink_data,
input wire sink_valid,
output wire sink_ready,
output wire resetrequest,
output wire debug_reset,
output wire mgmt_valid,
output wire [(MGMT_CHANNEL_WIDTH>0?MGMT_CHANNEL_WIDTH:1)-1:0] mgmt_channel,
output wire mgmt_data
);
// Signals in the JTAG clock domain
wire tck;
wire tdi;
wire tdo;
wire [2:0] ir_in;
wire virtual_state_cdr;
wire virtual_state_sdr;
wire virtual_state_udr;
assign jtag_irq = 1'b0;
assign jtag_ir_out = 3'b000;
generate
if (EXPORT_JTAG == 0) begin
// SLD node instantiation
altera_jtag_sld_node node (
.tck (tck),
.tdi (tdi),
.tdo (tdo),
.ir_out (1'b0),
.ir_in (ir_in),
.virtual_state_cdr (virtual_state_cdr),
.virtual_state_cir (),
.virtual_state_e1dr (),
.virtual_state_e2dr (),
.virtual_state_pdr (),
.virtual_state_sdr (virtual_state_sdr),
.virtual_state_udr (virtual_state_udr),
.virtual_state_uir ()
);
assign jtag_tdo = 1'b0;
end else begin
assign tck = jtag_tck;
assign tdi = jtag_tdi;
assign jtag_tdo = tdo;
assign ir_in = jtag_ir_in;
assign virtual_state_cdr = jtag_ena && !jtag_usr1 && jtag_state_cdr;
assign virtual_state_sdr = jtag_ena && !jtag_usr1 && jtag_state_sdr;
assign virtual_state_udr = jtag_ena && !jtag_usr1 && jtag_state_udr;
end
endgenerate
generate
if (USE_PLI == 0)
begin : normal
altera_jtag_dc_streaming #(
.PURPOSE(PURPOSE),
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
) jtag_dc_streaming (
.tck (tck),
.tdi (tdi),
.tdo (tdo),
.ir_in (ir_in),
.virtual_state_cdr(virtual_state_cdr),
.virtual_state_sdr(virtual_state_sdr),
.virtual_state_udr(virtual_state_udr),
.clk(clk),
.reset_n(reset_n),
.source_data(source_data),
.source_valid(source_valid),
.sink_data(sink_data),
.sink_valid(sink_valid),
.sink_ready(sink_ready),
.resetrequest(resetrequest),
.debug_reset(debug_reset),
.mgmt_valid(mgmt_valid),
.mgmt_channel(mgmt_channel),
.mgmt_data(mgmt_data)
);
end
else
begin : pli_mode
//synthesis translate_off
reg pli_out_valid;
reg pli_in_ready;
reg [7 : 0] pli_out_data;
always @(posedge clk or negedge reset_n) begin
if (!reset_n) begin
pli_out_valid <= 0;
pli_out_data <= 'b0;
pli_in_ready <= 0;
end
else begin
`ifdef MODEL_TECH
$do_transaction(
PLI_PORT,
pli_out_valid,
source_ready,
pli_out_data,
sink_valid,
pli_in_ready,
sink_data
);
`endif
end
end
//synthesis translate_on
wire [7:0] jtag_source_data;
wire jtag_source_valid;
wire jtag_sink_ready;
wire jtag_resetrequest;
altera_jtag_dc_streaming #(
.PURPOSE(PURPOSE),
.UPSTREAM_FIFO_SIZE(UPSTREAM_FIFO_SIZE),
.DOWNSTREAM_FIFO_SIZE(DOWNSTREAM_FIFO_SIZE),
.MGMT_CHANNEL_WIDTH(MGMT_CHANNEL_WIDTH)
) jtag_dc_streaming (
.tck (tck),
.tdi (tdi),
.tdo (tdo),
.ir_in (ir_in),
.virtual_state_cdr(virtual_state_cdr),
.virtual_state_sdr(virtual_state_sdr),
.virtual_state_udr(virtual_state_udr),
.clk(clk),
.reset_n(reset_n),
.source_data(jtag_source_data),
.source_valid(jtag_source_valid),
.sink_data(sink_data),
.sink_valid(sink_valid),
.sink_ready(jtag_sink_ready),
.resetrequest(jtag_resetrequest)//,
//.debug_reset(debug_reset),
//.mgmt_valid(mgmt_valid),
//.mgmt_channel(mgmt_channel),
//.mgmt_data(mgmt_data)
);
// synthesis read_comments_as_HDL on
// assign source_valid = jtag_source_valid;
// assign source_data = jtag_source_data;
// assign sink_ready = jtag_sink_ready;
// assign resetrequest = jtag_resetrequest;
// synthesis read_comments_as_HDL off
//synthesis translate_off
assign source_valid = pli_out_valid;
assign source_data = pli_out_data;
assign sink_ready = pli_in_ready;
assign resetrequest = 1'b0;
//synthesis translate_on
assign jtag_tdo = 1'b0;
end
endgenerate
endmodule
|
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ps / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_int_controller_phy (
// inputs:
dqs_delay_ctrl_import,
dqs_offset_delay_ctrl,
global_reset_n,
hc_scan_ck,
hc_scan_din,
hc_scan_enable_access,
hc_scan_enable_dm,
hc_scan_enable_dq,
hc_scan_enable_dqs,
hc_scan_enable_dqs_config,
hc_scan_update,
local_address,
local_autopch_req,
local_be,
local_burstbegin,
local_multicast_req,
local_read_req,
local_refresh_chip,
local_refresh_req,
local_self_rfsh_chip,
local_self_rfsh_req,
local_size,
local_wdata,
local_write_req,
oct_ctl_rs_value,
oct_ctl_rt_value,
pll_phasecounterselect,
pll_phasestep,
pll_phaseupdown,
pll_reconfig,
pll_reconfig_counter_param,
pll_reconfig_counter_type,
pll_reconfig_data_in,
pll_reconfig_enable,
pll_reconfig_read_param,
pll_reconfig_soft_reset_en_n,
pll_reconfig_write_param,
pll_ref_clk,
soft_reset_n,
// outputs:
aux_full_rate_clk,
aux_half_rate_clk,
aux_scan_clk,
aux_scan_clk_reset_n,
dll_reference_clk,
dqs_delay_ctrl_export,
ecc_interrupt,
hc_scan_dout,
local_init_done,
local_power_down_ack,
local_rdata,
local_rdata_valid,
local_ready,
local_refresh_ack,
local_self_rfsh_ack,
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_clk,
mem_clk_n,
mem_cs_n,
mem_dm,
mem_dq,
mem_dqs,
mem_dqsn,
mem_odt,
mem_ras_n,
mem_reset_n,
mem_we_n,
phy_clk,
pll_phase_done,
pll_reconfig_busy,
pll_reconfig_clk,
pll_reconfig_data_out,
pll_reconfig_reset,
reset_phy_clk_n,
reset_request_n
)
;
output aux_full_rate_clk;
output aux_half_rate_clk;
output aux_scan_clk;
output aux_scan_clk_reset_n;
output dll_reference_clk;
output [ 5: 0] dqs_delay_ctrl_export;
output ecc_interrupt;
output [ 63: 0] hc_scan_dout;
output local_init_done;
output local_power_down_ack;
output [255: 0] local_rdata;
output local_rdata_valid;
output local_ready;
output local_refresh_ack;
output local_self_rfsh_ack;
output [ 12: 0] mem_addr;
output [ 2: 0] mem_ba;
output mem_cas_n;
output [ 0: 0] mem_cke;
inout [ 0: 0] mem_clk;
inout [ 0: 0] mem_clk_n;
output [ 0: 0] mem_cs_n;
output [ 7: 0] mem_dm;
inout [ 63: 0] mem_dq;
inout [ 7: 0] mem_dqs;
inout [ 7: 0] mem_dqsn;
output [ 0: 0] mem_odt;
output mem_ras_n;
output mem_reset_n;
output mem_we_n;
output phy_clk;
output pll_phase_done;
output pll_reconfig_busy;
output pll_reconfig_clk;
output [ 8: 0] pll_reconfig_data_out;
output pll_reconfig_reset;
output reset_phy_clk_n;
output reset_request_n;
input [ 5: 0] dqs_delay_ctrl_import;
input [ 5: 0] dqs_offset_delay_ctrl;
input global_reset_n;
input hc_scan_ck;
input [ 7: 0] hc_scan_din;
input hc_scan_enable_access;
input [ 7: 0] hc_scan_enable_dm;
input [ 63: 0] hc_scan_enable_dq;
input [ 7: 0] hc_scan_enable_dqs;
input [ 7: 0] hc_scan_enable_dqs_config;
input [ 7: 0] hc_scan_update;
input [ 23: 0] local_address;
input local_autopch_req;
input [ 31: 0] local_be;
input local_burstbegin;
input local_multicast_req;
input local_read_req;
input local_refresh_chip;
input local_refresh_req;
input local_self_rfsh_chip;
input local_self_rfsh_req;
input [ 4: 0] local_size;
input [255: 0] local_wdata;
input local_write_req;
input [ 13: 0] oct_ctl_rs_value;
input [ 13: 0] oct_ctl_rt_value;
input [ 3: 0] pll_phasecounterselect;
input pll_phasestep;
input pll_phaseupdown;
input pll_reconfig;
input [ 2: 0] pll_reconfig_counter_param;
input [ 3: 0] pll_reconfig_counter_type;
input [ 8: 0] pll_reconfig_data_in;
input pll_reconfig_enable;
input pll_reconfig_read_param;
input pll_reconfig_soft_reset_en_n;
input pll_reconfig_write_param;
input pll_ref_clk;
input soft_reset_n;
wire [ 25: 0] afi_addr;
wire [ 5: 0] afi_ba;
wire [ 1: 0] afi_cas_n;
wire [ 1: 0] afi_cke;
wire [ 1: 0] afi_cs_n;
wire afi_ctl_long_idle;
wire afi_ctl_refresh_done;
wire [ 31: 0] afi_dm;
wire [ 15: 0] afi_dqs_burst;
wire [ 1: 0] afi_odt;
wire [ 1: 0] afi_ras_n;
wire [255: 0] afi_rdata;
wire [ 15: 0] afi_rdata_en;
wire [ 15: 0] afi_rdata_en_full;
wire [ 1: 0] afi_rdata_valid;
wire [ 1: 0] afi_rst_n;
wire [255: 0] afi_wdata;
wire [ 15: 0] afi_wdata_valid;
wire [ 1: 0] afi_we_n;
wire [ 4: 0] afi_wlat;
wire aux_full_rate_clk;
wire aux_half_rate_clk;
wire aux_scan_clk;
wire aux_scan_clk_reset_n;
wire [ 31: 0] csr_rdata_sig;
wire csr_rdata_valid_sig;
wire csr_waitrequest_sig;
wire [ 7: 0] ctl_cal_byte_lane_sel_n;
wire ctl_cal_fail;
wire ctl_cal_req;
wire ctl_cal_success;
wire ctl_clk;
wire ctl_mem_clk_disable;
wire [ 4: 0] ctl_rlat;
wire [ 31: 0] dbg_rd_data_sig;
wire dbg_waitrequest_sig;
wire dll_reference_clk;
wire [ 5: 0] dqs_delay_ctrl_export;
wire ecc_interrupt;
wire [ 63: 0] hc_scan_dout;
wire local_init_done;
wire local_power_down_ack;
wire [255: 0] local_rdata;
wire local_rdata_valid;
wire local_ready;
wire local_refresh_ack;
wire local_self_rfsh_ack;
wire [ 12: 0] mem_addr;
wire [ 2: 0] mem_ba;
wire mem_cas_n;
wire [ 0: 0] mem_cke;
wire [ 0: 0] mem_clk;
wire [ 0: 0] mem_clk_n;
wire [ 0: 0] mem_cs_n;
wire [ 7: 0] mem_dm;
wire [ 63: 0] mem_dq;
wire [ 7: 0] mem_dqs;
wire [ 7: 0] mem_dqsn;
wire [ 0: 0] mem_odt;
wire mem_ras_n;
wire mem_reset_n;
wire mem_we_n;
wire phy_clk;
wire pll_phase_done;
wire pll_reconfig_busy;
wire pll_reconfig_clk;
wire [ 8: 0] pll_reconfig_data_out;
wire pll_reconfig_reset;
wire reset_ctl_clk_n;
wire reset_phy_clk_n;
wire reset_request_n;
assign phy_clk = ctl_clk;
assign reset_phy_clk_n = reset_ctl_clk_n;
ddr3_int_alt_mem_ddrx_controller_top ddr3_int_alt_mem_ddrx_controller_top_inst
(
.afi_addr (afi_addr),
.afi_ba (afi_ba),
.afi_cal_byte_lane_sel_n (ctl_cal_byte_lane_sel_n),
.afi_cal_fail (ctl_cal_fail),
.afi_cal_req (ctl_cal_req),
.afi_cal_success (ctl_cal_success),
.afi_cas_n (afi_cas_n),
.afi_cke (afi_cke),
.afi_cs_n (afi_cs_n),
.afi_ctl_long_idle (afi_ctl_long_idle),
.afi_ctl_refresh_done (afi_ctl_refresh_done),
.afi_dm (afi_dm),
.afi_dqs_burst (afi_dqs_burst),
.afi_mem_clk_disable (ctl_mem_clk_disable),
.afi_odt (afi_odt),
.afi_ras_n (afi_ras_n),
.afi_rdata (afi_rdata),
.afi_rdata_en (afi_rdata_en),
.afi_rdata_en_full (afi_rdata_en_full),
.afi_rdata_valid (afi_rdata_valid),
.afi_rlat (ctl_rlat),
.afi_rst_n (afi_rst_n),
.afi_seq_busy ({1{1'b0}}),
.afi_wdata (afi_wdata),
.afi_wdata_valid (afi_wdata_valid),
.afi_we_n (afi_we_n),
.afi_wlat (afi_wlat),
.clk (ctl_clk),
.csr_addr (16'b0),
.csr_be (4'b0),
.csr_beginbursttransfer (1'b0),
.csr_burst_count (1'b0),
.csr_rdata (csr_rdata_sig),
.csr_rdata_valid (csr_rdata_valid_sig),
.csr_read_req (1'b0),
.csr_waitrequest (csr_waitrequest_sig),
.csr_wdata (32'b0),
.csr_write_req (1'b0),
.ecc_interrupt (ecc_interrupt),
.half_clk (aux_half_rate_clk),
.local_address (local_address),
.local_autopch_req (local_autopch_req),
.local_beginbursttransfer (local_burstbegin),
.local_burstcount (local_size),
.local_byteenable (local_be),
.local_init_done (local_init_done),
.local_multicast (local_multicast_req),
.local_powerdn_ack (local_power_down_ack),
.local_powerdn_req (1'b0),
.local_priority (1'b1),
.local_read (local_read_req),
.local_readdata (local_rdata),
.local_readdatavalid (local_rdata_valid),
.local_ready (local_ready),
.local_refresh_ack (local_refresh_ack),
.local_refresh_chip (local_refresh_chip),
.local_refresh_req (local_refresh_req),
.local_self_rfsh_ack (local_self_rfsh_ack),
.local_self_rfsh_chip (local_self_rfsh_chip),
.local_self_rfsh_req (local_self_rfsh_req),
.local_write (local_write_req),
.local_writedata (local_wdata),
.reset_n (reset_ctl_clk_n)
);
ddr3_int_phy ddr3_int_phy_inst
(
.aux_full_rate_clk (aux_full_rate_clk),
.aux_half_rate_clk (aux_half_rate_clk),
.ctl_addr (afi_addr),
.ctl_ba (afi_ba),
.ctl_cal_byte_lane_sel_n (ctl_cal_byte_lane_sel_n),
.ctl_cal_fail (ctl_cal_fail),
.ctl_cal_req (ctl_cal_req),
.ctl_cal_success (ctl_cal_success),
.ctl_cas_n (afi_cas_n),
.ctl_cke (afi_cke),
.ctl_clk (ctl_clk),
.ctl_cs_n (afi_cs_n),
.ctl_dm (afi_dm),
.ctl_doing_rd (afi_rdata_en),
.ctl_dqs_burst (afi_dqs_burst),
.ctl_mem_clk_disable (ctl_mem_clk_disable),
.ctl_odt (afi_odt),
.ctl_ras_n (afi_ras_n),
.ctl_rdata (afi_rdata),
.ctl_rdata_valid (afi_rdata_valid),
.ctl_reset_n (reset_ctl_clk_n),
.ctl_rlat (ctl_rlat),
.ctl_rst_n (afi_rst_n),
.ctl_wdata (afi_wdata),
.ctl_wdata_valid (afi_wdata_valid),
.ctl_we_n (afi_we_n),
.ctl_wlat (afi_wlat),
.dbg_addr (13'b0),
.dbg_clk (ctl_clk),
.dbg_cs (1'b0),
.dbg_rd (1'b0),
.dbg_rd_data (dbg_rd_data_sig),
.dbg_reset_n (reset_ctl_clk_n),
.dbg_waitrequest (dbg_waitrequest_sig),
.dbg_wr (1'b0),
.dbg_wr_data (32'b0),
.dll_reference_clk (dll_reference_clk),
.dqs_delay_ctrl_export (dqs_delay_ctrl_export),
.dqs_delay_ctrl_import (dqs_delay_ctrl_import),
.dqs_offset_delay_ctrl (dqs_offset_delay_ctrl),
.global_reset_n (global_reset_n),
.mem_addr (mem_addr),
.mem_ba (mem_ba),
.mem_cas_n (mem_cas_n),
.mem_cke (mem_cke),
.mem_clk (mem_clk),
.mem_clk_n (mem_clk_n),
.mem_cs_n (mem_cs_n),
.mem_dm (mem_dm[7 : 0]),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs[7 : 0]),
.mem_dqs_n (mem_dqsn[7 : 0]),
.mem_odt (mem_odt),
.mem_ras_n (mem_ras_n),
.mem_reset_n (mem_reset_n),
.mem_we_n (mem_we_n),
.oct_ctl_rs_value (oct_ctl_rs_value),
.oct_ctl_rt_value (oct_ctl_rt_value),
.pll_ref_clk (pll_ref_clk),
.reset_request_n (reset_request_n),
.soft_reset_n (soft_reset_n)
);
//<< start europa
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFBBP_FUNCTIONAL_V
`define SKY130_FD_SC_LS__DFBBP_FUNCTIONAL_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr/sky130_fd_sc_ls__udp_dff_nsr.v"
`celldefine
module sky130_fd_sc_ls__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
// Local signals
wire RESET;
wire SET ;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
sky130_fd_sc_ls__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, D);
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFBBP_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR3_SYMBOL_V
`define SKY130_FD_SC_MS__OR3_SYMBOL_V
/**
* or3: 3-input OR.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__or3 (
//# {{data|Data Signals}}
input A,
input B,
input C,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR3_SYMBOL_V
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module gpio (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
wire data_in;
wire irq;
reg irq_mask;
wire read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({1 {(address == 0)}} & data_in) |
({1 {(address == 2)}} & irq_mask);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {{{32 - 1}{1'b0}},read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata;
end
assign irq = |(data_in & irq_mask);
endmodule
|
/*******************************************************************************
* Module: axi_hp_clk
* Date:2015-04-27
* Author: Andrey Filippov
* Description: Generate global clock for axi_hp
*
* Copyright (c) 2015 Elphel, Inc.
* axi_hp_clk.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* axi_hp_clk.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
`timescale 1ns/1ps
module axi_hp_clk#(
parameter CLKIN_PERIOD = 20, //ns >1.25, 600<Fvco<1200
parameter CLKFBOUT_MULT_AXIHP = 18, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_AXIHP = 6 // To get 150MHz for the reference clock
)(
input rst,
input clk_in,
output clk_axihp,
output locked_axihp
);
wire clkfb_axihp, clk_axihp_pre;
BUFG clk_axihp_i (.O(clk_axihp), .I(clk_axihp_pre));
pll_base #(
.CLKIN_PERIOD(CLKIN_PERIOD), // 20
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(CLKFBOUT_MULT_AXIHP), // 18, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
.CLKOUT0_DIVIDE(CLKFBOUT_DIV_AXIHP), // 6, // To get 300MHz for the reference clock
.REF_JITTER1(0.010),
.STARTUP_WAIT("FALSE")
) pll_base_i (
.clkin(clk_in), // input
.clkfbin(clkfb_axihp), // input
// .rst(rst), // input
.rst(rst), // input
.pwrdwn(1'b0), // input
.clkout0(clk_axihp_pre), // output
.clkout1(), // output
.clkout2(), // output
.clkout3(), // output
.clkout4(), // output
.clkout5(), // output
.clkfbout(clkfb_axihp), // output
.locked(locked_axihp) // output
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3_PP_SYMBOL_V
`define SKY130_FD_SC_LP__NOR3_PP_SYMBOL_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nor3 (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3_PP_SYMBOL_V
|
(* -*- coding: utf-8; coq-prog-args: ("-coqlib" "../.." "-R" ".." "Coq" "-top" "Coq.Classes.CMorphisms") -*- *)
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2016 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** * Typeclass-based morphism definition and standard, minimal instances
Author: Matthieu Sozeau
Institution: LRI, CNRS UMR 8623 - University Paris Sud
*)
Require Import Coq.Program.Basics.
Require Import Coq.Program.Tactics.
Require Export Coq.Classes.CRelationClasses.
Generalizable Variables A eqA B C D R RA RB RC m f x y.
Local Obligation Tactic := simpl_crelation.
Set Universe Polymorphism.
(** * Morphisms.
We now turn to the definition of [Proper] and declare standard instances.
These will be used by the [setoid_rewrite] tactic later. *)
(** A morphism for a relation [R] is a proper element of the relation.
The relation [R] will be instantiated by [respectful] and [A] by an arrow
type for usual morphisms. *)
Section Proper.
Context {A : Type}.
Class Proper (R : crelation A) (m : A) :=
proper_prf : R m m.
(** Every element in the carrier of a reflexive relation is a morphism
for this relation. We use a proxy class for this case which is used
internally to discharge reflexivity constraints. The [Reflexive]
instance will almost always be used, but it won't apply in general to
any kind of [Proper (A -> B) _ _] goal, making proof-search much
slower. A cleaner solution would be to be able to set different
priorities in different hint bases and select a particular hint
database for resolution of a type class constraint. *)
Class ProperProxy (R : crelation A) (m : A) :=
proper_proxy : R m m.
Lemma eq_proper_proxy (x : A) : ProperProxy (@eq A) x.
Proof. firstorder. Qed.
Lemma reflexive_proper_proxy `(Reflexive A R) (x : A) : ProperProxy R x.
Proof. firstorder. Qed.
Lemma proper_proper_proxy x `(Proper R x) : ProperProxy R x.
Proof. firstorder. Qed.
(** Respectful morphisms. *)
(** The fully dependent version, not used yet. *)
Definition respectful_hetero
(A B : Type)
(C : A -> Type) (D : B -> Type)
(R : A -> B -> Type)
(R' : forall (x : A) (y : B), C x -> D y -> Type) :
(forall x : A, C x) -> (forall x : B, D x) -> Type :=
fun f g => forall x y, R x y -> R' x y (f x) (g y).
(** The non-dependent version is an instance where we forget dependencies. *)
Definition respectful {B} (R : crelation A) (R' : crelation B) : crelation (A -> B) :=
Eval compute in @respectful_hetero A A (fun _ => B) (fun _ => B) R (fun _ _ => R').
End Proper.
(** We favor the use of Leibniz equality or a declared reflexive crelation
when resolving [ProperProxy], otherwise, if the crelation is given (not an evar),
we fall back to [Proper]. *)
Hint Extern 1 (ProperProxy _ _) =>
class_apply @eq_proper_proxy || class_apply @reflexive_proper_proxy : typeclass_instances.
Hint Extern 2 (ProperProxy ?R _) =>
not_evar R; class_apply @proper_proper_proxy : typeclass_instances.
(** Notations reminiscent of the old syntax for declaring morphisms. *)
Delimit Scope signature_scope with signature.
Module ProperNotations.
Notation " R ++> R' " := (@respectful _ _ (R%signature) (R'%signature))
(right associativity, at level 55) : signature_scope.
Notation " R ==> R' " := (@respectful _ _ (R%signature) (R'%signature))
(right associativity, at level 55) : signature_scope.
Notation " R --> R' " := (@respectful _ _ (flip (R%signature)) (R'%signature))
(right associativity, at level 55) : signature_scope.
End ProperNotations.
Arguments Proper {A}%type R%signature m.
Arguments respectful {A B}%type (R R')%signature _ _.
Export ProperNotations.
Local Open Scope signature_scope.
(** [solve_proper] try to solve the goal [Proper (?==> ... ==>?) f]
by repeated introductions and setoid rewrites. It should work
fine when [f] is a combination of already known morphisms and
quantifiers. *)
Ltac solve_respectful t :=
match goal with
| |- respectful _ _ _ _ =>
let H := fresh "H" in
intros ? ? H; solve_respectful ltac:(setoid_rewrite H; t)
| _ => t; reflexivity
end.
Ltac solve_proper := unfold Proper; solve_respectful ltac:(idtac).
(** [f_equiv] is a clone of [f_equal] that handles setoid equivalences.
For example, if we know that [f] is a morphism for [E1==>E2==>E],
then the goal [E (f x y) (f x' y')] will be transformed by [f_equiv]
into the subgoals [E1 x x'] and [E2 y y'].
*)
Ltac f_equiv :=
match goal with
| |- ?R (?f ?x) (?f' _) =>
let T := type of x in
let Rx := fresh "R" in
evar (Rx : crelation T);
let H := fresh in
assert (H : (Rx==>R)%signature f f');
unfold Rx in *; clear Rx; [ f_equiv | apply H; clear H; try reflexivity ]
| |- ?R ?f ?f' =>
solve [change (Proper R f); eauto with typeclass_instances | reflexivity ]
| _ => idtac
end.
Section Relations.
Context {A : Type}.
(** [forall_def] reifies the dependent product as a definition. *)
Definition forall_def (P : A -> Type) : Type := forall x : A, P x.
(** Dependent pointwise lifting of a crelation on the range. *)
Definition forall_relation (P : A -> Type)
(sig : forall a, crelation (P a)) : crelation (forall x, P x) :=
fun f g => forall a, sig a (f a) (g a).
(** Non-dependent pointwise lifting *)
Definition pointwise_relation {B} (R : crelation B) : crelation (A -> B) :=
fun f g => forall a, R (f a) (g a).
Lemma pointwise_pointwise {B} (R : crelation B) :
relation_equivalence (pointwise_relation R) (@eq A ==> R).
Proof. intros. split. simpl_crelation. firstorder. Qed.
(** Subcrelations induce a morphism on the identity. *)
Global Instance subrelation_id_proper `(subrelation A RA RA') : Proper (RA ==> RA') id.
Proof. firstorder. Qed.
(** The subrelation property goes through products as usual. *)
Lemma subrelation_respectful `(subl : subrelation A RA' RA, subr : subrelation B RB RB') :
subrelation (RA ==> RB) (RA' ==> RB').
Proof. simpl_crelation. Qed.
(** And of course it is reflexive. *)
Lemma subrelation_refl R : @subrelation A R R.
Proof. simpl_crelation. Qed.
(** [Proper] is itself a covariant morphism for [subrelation].
We use an unconvertible premise to avoid looping.
*)
Lemma subrelation_proper `(mor : Proper A R' m)
`(unc : Unconvertible (crelation A) R R')
`(sub : subrelation A R' R) : Proper R m.
Proof.
intros. apply sub. apply mor.
Qed.
Global Instance proper_subrelation_proper_arrow :
Proper (subrelation ++> eq ==> arrow) (@Proper A).
Proof. reduce. subst. firstorder. Qed.
Global Instance pointwise_subrelation `(sub : subrelation B R R') :
subrelation (pointwise_relation R) (pointwise_relation R') | 4.
Proof. reduce. unfold pointwise_relation in *. apply sub. auto. Qed.
(** For dependent function types. *)
Lemma forall_subrelation (P : A -> Type) (R S : forall x : A, crelation (P x)) :
(forall a, subrelation (R a) (S a)) ->
subrelation (forall_relation P R) (forall_relation P S).
Proof. reduce. firstorder. Qed.
End Relations.
Typeclasses Opaque respectful pointwise_relation forall_relation.
Arguments forall_relation {A P}%type sig%signature _ _.
Arguments pointwise_relation A%type {B}%type R%signature _ _.
Hint Unfold Reflexive : core.
Hint Unfold Symmetric : core.
Hint Unfold Transitive : core.
(** Resolution with subrelation: favor decomposing products over applying reflexivity
for unconstrained goals. *)
Ltac subrelation_tac T U :=
(is_ground T ; is_ground U ; class_apply @subrelation_refl) ||
class_apply @subrelation_respectful || class_apply @subrelation_refl.
Hint Extern 3 (@subrelation _ ?T ?U) => subrelation_tac T U : typeclass_instances.
CoInductive apply_subrelation : Prop := do_subrelation.
Ltac proper_subrelation :=
match goal with
[ H : apply_subrelation |- _ ] => clear H ; class_apply @subrelation_proper
end.
Hint Extern 5 (@Proper _ ?H _) => proper_subrelation : typeclass_instances.
(** Essential subrelation instances for [iff], [impl] and [pointwise_relation]. *)
Instance iff_impl_subrelation : subrelation iff impl | 2.
Proof. firstorder. Qed.
Instance iff_flip_impl_subrelation : subrelation iff (flip impl) | 2.
Proof. firstorder. Qed.
(** Essential subrelation instances for [iffT] and [arrow]. *)
Instance iffT_arrow_subrelation : subrelation iffT arrow | 2.
Proof. firstorder. Qed.
Instance iffT_flip_arrow_subrelation : subrelation iffT (flip arrow) | 2.
Proof. firstorder. Qed.
(** We use an extern hint to help unification. *)
Hint Extern 4 (subrelation (@forall_relation ?A ?B ?R) (@forall_relation _ _ ?S)) =>
apply (@forall_subrelation A B R S) ; intro : typeclass_instances.
Section GenericInstances.
(* Share universes *)
Implicit Types A B C : Type.
(** We can build a PER on the Coq function space if we have PERs on the domain and
codomain. *)
Program Instance respectful_per `(PER A R, PER B R') : PER (R ==> R').
Next Obligation.
Proof with auto.
assert(R x0 x0).
transitivity y0... symmetry...
transitivity (y x0)...
Qed.
Unset Strict Universe Declaration.
(** The complement of a crelation conserves its proper elements. *)
(** The [flip] too, actually the [flip] instance is a bit more general. *)
Program Definition flip_proper
`(mor : Proper (A -> B -> C) (RA ==> RB ==> RC) f) :
Proper (RB ==> RA ==> RC) (flip f) := _.
Next Obligation.
Proof.
apply mor ; auto.
Qed.
(** Every Transitive crelation gives rise to a binary morphism on [impl],
contravariant in the first argument, covariant in the second. *)
Global Program
Instance trans_contra_co_type_morphism
`(Transitive A R) : Proper (R --> R ++> arrow) R.
Next Obligation.
Proof with auto.
transitivity x...
transitivity x0...
Qed.
(** Proper declarations for partial applications. *)
Global Program
Instance trans_contra_inv_impl_type_morphism
`(Transitive A R) : Proper (R --> flip arrow) (R x) | 3.
Next Obligation.
Proof with auto.
transitivity y...
Qed.
Global Program
Instance trans_co_impl_type_morphism
`(Transitive A R) : Proper (R ++> arrow) (R x) | 3.
Next Obligation.
Proof with auto.
transitivity x0...
Qed.
Global Program
Instance trans_sym_co_inv_impl_type_morphism
`(PER A R) : Proper (R ++> flip arrow) (R x) | 3.
Next Obligation.
Proof with auto.
transitivity y... symmetry...
Qed.
Global Program Instance trans_sym_contra_arrow_morphism
`(PER A R) : Proper (R --> arrow) (R x) | 3.
Next Obligation.
Proof with auto.
transitivity x0... symmetry...
Qed.
Global Program Instance per_partial_app_type_morphism
`(PER A R) : Proper (R ==> iffT) (R x) | 2.
Next Obligation.
Proof with auto.
split. intros ; transitivity x0...
intros.
transitivity y...
symmetry...
Qed.
(** Every Transitive crelation induces a morphism by "pushing" an [R x y] on the left of an [R x z] proof to get an [R y z] goal. *)
Global Program
Instance trans_co_eq_inv_arrow_morphism
`(Transitive A R) : Proper (R ==> (@eq A) ==> flip arrow) R | 2.
Next Obligation.
Proof with auto.
transitivity y...
Qed.
(** Every Symmetric and Transitive crelation gives rise to an equivariant morphism. *)
Global Program
Instance PER_type_morphism `(PER A R) : Proper (R ==> R ==> iffT) R | 1.
Next Obligation.
Proof with auto.
split ; intros.
transitivity x0... transitivity x... symmetry...
transitivity y... transitivity y0... symmetry...
Qed.
Lemma symmetric_equiv_flip `(Symmetric A R) : relation_equivalence R (flip R).
Proof. firstorder. Qed.
Global Program Instance compose_proper A B C RA RB RC :
Proper ((RB ==> RC) ==> (RA ==> RB) ==> (RA ==> RC)) (@compose A B C).
Next Obligation.
Proof.
simpl_crelation.
unfold compose. firstorder.
Qed.
(** Coq functions are morphisms for Leibniz equality,
applied only if really needed. *)
Global Instance reflexive_eq_dom_reflexive `(Reflexive B R') :
Reflexive (@Logic.eq A ==> R').
Proof. simpl_crelation. Qed.
(** [respectful] is a morphism for crelation equivalence . *)
Global Instance respectful_morphism :
Proper (relation_equivalence ++> relation_equivalence ++> relation_equivalence)
(@respectful A B).
Proof.
intros A B R R' HRR' S S' HSS' f g.
unfold respectful , relation_equivalence in *; simpl in *.
split ; intros H x y Hxy.
apply (fst (HSS' _ _)). apply H. now apply (snd (HRR' _ _)).
apply (snd (HSS' _ _)). apply H. now apply (fst (HRR' _ _)).
Qed.
(** [R] is Reflexive, hence we can build the needed proof. *)
Lemma Reflexive_partial_app_morphism `(Proper (A -> B) (R ==> R') m, ProperProxy A R x) :
Proper R' (m x).
Proof. simpl_crelation. Qed.
Class Params {A} (of : A) (arity : nat).
Lemma flip_respectful {A B} (R : crelation A) (R' : crelation B) :
relation_equivalence (flip (R ==> R')) (flip R ==> flip R').
Proof.
intros.
unfold flip, respectful.
split ; intros ; intuition.
Qed.
(** Treating flip: can't make them direct instances as we
need at least a [flip] present in the goal. *)
Lemma flip1 `(subrelation A R' R) : subrelation (flip (flip R')) R.
Proof. firstorder. Qed.
Lemma flip2 `(subrelation A R R') : subrelation R (flip (flip R')).
Proof. firstorder. Qed.
(** That's if and only if *)
Lemma eq_subrelation `(Reflexive A R) : subrelation (@eq A) R.
Proof. simpl_crelation. Qed.
(** Once we have normalized, we will apply this instance to simplify the problem. *)
Definition proper_flip_proper `(mor : Proper A R m) : Proper (flip R) m := mor.
(** Every reflexive crelation gives rise to a morphism,
only for immediately solving goals without variables. *)
Lemma reflexive_proper `{Reflexive A R} (x : A) : Proper R x.
Proof. firstorder. Qed.
Lemma proper_eq {A} (x : A) : Proper (@eq A) x.
Proof. intros. apply reflexive_proper. Qed.
End GenericInstances.
Class PartialApplication.
CoInductive normalization_done : Prop := did_normalization.
Ltac partial_application_tactic :=
let rec do_partial_apps H m cont :=
match m with
| ?m' ?x => class_apply @Reflexive_partial_app_morphism ;
[(do_partial_apps H m' ltac:(idtac))|clear H]
| _ => cont
end
in
let rec do_partial H ar m :=
match ar with
| 0%nat => do_partial_apps H m ltac:(fail 1)
| S ?n' =>
match m with
?m' ?x => do_partial H n' m'
end
end
in
let params m sk fk :=
(let m' := fresh in head_of_constr m' m ;
let n := fresh in evar (n:nat) ;
let v := eval compute in n in clear n ;
let H := fresh in
assert(H:Params m' v) by typeclasses eauto ;
let v' := eval compute in v in subst m';
(sk H v' || fail 1))
|| fk
in
let on_morphism m cont :=
params m ltac:(fun H n => do_partial H n m)
ltac:(cont)
in
match goal with
| [ _ : normalization_done |- _ ] => fail 1
| [ _ : @Params _ _ _ |- _ ] => fail 1
| [ |- @Proper ?T _ (?m ?x) ] =>
match goal with
| [ H : PartialApplication |- _ ] =>
class_apply @Reflexive_partial_app_morphism; [|clear H]
| _ => on_morphism (m x)
ltac:(class_apply @Reflexive_partial_app_morphism)
end
end.
(** Bootstrap !!! *)
Instance proper_proper : Proper (relation_equivalence ==> eq ==> iffT) (@Proper A).
Proof.
intros A R R' HRR' x y <-. red in HRR'.
split ; red ; intros.
now apply (fst (HRR' _ _)).
now apply (snd (HRR' _ _)).
Qed.
Ltac proper_reflexive :=
match goal with
| [ _ : normalization_done |- _ ] => fail 1
| _ => class_apply proper_eq || class_apply @reflexive_proper
end.
Hint Extern 1 (subrelation (flip _) _) => class_apply @flip1 : typeclass_instances.
Hint Extern 1 (subrelation _ (flip _)) => class_apply @flip2 : typeclass_instances.
(* Hint Extern 1 (Proper _ (complement _)) => apply @complement_proper *)
(* : typeclass_instances. *)
Hint Extern 1 (Proper _ (flip _)) => apply @flip_proper
: typeclass_instances.
Hint Extern 2 (@Proper _ (flip _) _) => class_apply @proper_flip_proper
: typeclass_instances.
Hint Extern 4 (@Proper _ _ _) => partial_application_tactic
: typeclass_instances.
Hint Extern 7 (@Proper _ _ _) => proper_reflexive
: typeclass_instances.
(** Special-purpose class to do normalization of signatures w.r.t. flip. *)
Section Normalize.
Context (A : Type).
Class Normalizes (m : crelation A) (m' : crelation A) :=
normalizes : relation_equivalence m m'.
(** Current strategy: add [flip] everywhere and reduce using [subrelation]
afterwards. *)
Lemma proper_normalizes_proper `(Normalizes R0 R1, Proper A R1 m) : Proper R0 m.
Proof.
red in H, H0. red in H.
apply (snd (H _ _)).
assumption.
Qed.
Lemma flip_atom R : Normalizes R (flip (flip R)).
Proof.
firstorder.
Qed.
End Normalize.
Lemma flip_arrow `(NA : Normalizes A R (flip R'''), NB : Normalizes B R' (flip R'')) :
Normalizes (A -> B) (R ==> R') (flip (R''' ==> R'')%signature).
Proof.
unfold Normalizes in *. intros.
rewrite NA, NB. firstorder.
Qed.
Ltac normalizes :=
match goal with
| [ |- Normalizes _ (respectful _ _) _ ] => class_apply @flip_arrow
| _ => class_apply @flip_atom
end.
Ltac proper_normalization :=
match goal with
| [ _ : normalization_done |- _ ] => fail 1
| [ _ : apply_subrelation |- @Proper _ ?R _ ] =>
let H := fresh "H" in
set(H:=did_normalization) ; class_apply @proper_normalizes_proper
end.
Hint Extern 1 (Normalizes _ _ _) => normalizes : typeclass_instances.
Hint Extern 6 (@Proper _ _ _) => proper_normalization
: typeclass_instances.
(** When the crelation on the domain is symmetric, we can
flip the crelation on the codomain. Same for binary functions. *)
Lemma proper_sym_flip :
forall `(Symmetric A R1)`(Proper (A->B) (R1==>R2) f),
Proper (R1==>flip R2) f.
Proof.
intros A R1 Sym B R2 f Hf.
intros x x' Hxx'. apply Hf, Sym, Hxx'.
Qed.
Lemma proper_sym_flip_2 :
forall `(Symmetric A R1)`(Symmetric B R2)`(Proper (A->B->C) (R1==>R2==>R3) f),
Proper (R1==>R2==>flip R3) f.
Proof.
intros A R1 Sym1 B R2 Sym2 C R3 f Hf.
intros x x' Hxx' y y' Hyy'. apply Hf; auto.
Qed.
(** When the crelation on the domain is symmetric, a predicate is
compatible with [iff] as soon as it is compatible with [impl].
Same with a binary crelation. *)
Lemma proper_sym_impl_iff : forall `(Symmetric A R)`(Proper _ (R==>impl) f),
Proper (R==>iff) f.
Proof.
intros A R Sym f Hf x x' Hxx'. repeat red in Hf. split; eauto.
Qed.
Lemma proper_sym_arrow_iffT : forall `(Symmetric A R)`(Proper _ (R==>arrow) f),
Proper (R==>iffT) f.
Proof.
intros A R Sym f Hf x x' Hxx'. repeat red in Hf. split; eauto.
Qed.
Lemma proper_sym_impl_iff_2 :
forall `(Symmetric A R)`(Symmetric B R')`(Proper _ (R==>R'==>impl) f),
Proper (R==>R'==>iff) f.
Proof.
intros A R Sym B R' Sym' f Hf x x' Hxx' y y' Hyy'.
repeat red in Hf. split; eauto.
Qed.
Lemma proper_sym_arrow_iffT_2 :
forall `(Symmetric A R)`(Symmetric B R')`(Proper _ (R==>R'==>arrow) f),
Proper (R==>R'==>iffT) f.
Proof.
intros A R Sym B R' Sym' f Hf x x' Hxx' y y' Hyy'.
repeat red in Hf. split; eauto.
Qed.
(** A [PartialOrder] is compatible with its underlying equivalence. *)
Require Import Relation_Definitions.
Instance PartialOrder_proper_type `(PartialOrder A eqA R) :
Proper (eqA==>eqA==>iffT) R.
Proof.
intros.
apply proper_sym_arrow_iffT_2; auto with *.
intros x x' Hx y y' Hy Hr.
transitivity x.
generalize (partial_order_equivalence x x'); compute; intuition.
transitivity y; auto.
generalize (partial_order_equivalence y y'); compute; intuition.
Qed.
(** From a [PartialOrder] to the corresponding [StrictOrder]:
[lt = le /\ ~eq].
If the order is total, we could also say [gt = ~le]. *)
Lemma PartialOrder_StrictOrder `(PartialOrder A eqA R) :
StrictOrder (relation_conjunction R (complement eqA)).
Proof.
split; compute.
intros x (_,Hx). apply Hx, Equivalence_Reflexive.
intros x y z (Hxy,Hxy') (Hyz,Hyz'). split.
apply PreOrder_Transitive with y; assumption.
intro Hxz.
apply Hxy'.
apply partial_order_antisym; auto.
rewrite Hxz. auto.
Qed.
(** From a [StrictOrder] to the corresponding [PartialOrder]:
[le = lt \/ eq].
If the order is total, we could also say [ge = ~lt]. *)
Lemma StrictOrder_PreOrder
`(Equivalence A eqA, StrictOrder A R, Proper _ (eqA==>eqA==>iffT) R) :
PreOrder (relation_disjunction R eqA).
Proof.
split.
intros x. right. reflexivity.
intros x y z [Hxy|Hxy] [Hyz|Hyz].
left. transitivity y; auto.
left. rewrite <- Hyz; auto.
left. rewrite Hxy; auto.
right. transitivity y; auto.
Qed.
Hint Extern 4 (PreOrder (relation_disjunction _ _)) =>
class_apply StrictOrder_PreOrder : typeclass_instances.
Lemma StrictOrder_PartialOrder
`(Equivalence A eqA, StrictOrder A R, Proper _ (eqA==>eqA==>iffT) R) :
PartialOrder eqA (relation_disjunction R eqA).
Proof.
intros. intros x y. compute. intuition.
elim (StrictOrder_Irreflexive x).
transitivity y; auto.
Qed.
Hint Extern 4 (StrictOrder (relation_conjunction _ _)) =>
class_apply PartialOrder_StrictOrder : typeclass_instances.
Hint Extern 4 (PartialOrder _ (relation_disjunction _ _)) =>
class_apply StrictOrder_PartialOrder : typeclass_instances.
|
/*
* The MIT License (MIT)
*
* Copyright (c) 2015 Robert Armstrong
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all
* copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
module xadc_data_demux
(
input clk,
input reset,
input [15:0] xadc_data,
input xadc_data_ready,
input [4:0] channel,
output reg [15:0] xadc_vaux0_data,
output reg xadc_vaux0_ready,
output reg [15:0] xadc_vaux8_data,
output reg xadc_vaux8_ready
);
// Assignments for the XADC 0 data
always @(posedge clk) begin
if (reset) begin
xadc_vaux0_data <= 16'd0;
xadc_vaux0_ready <= 1'b0;
end
else
if (xadc_data_ready && (channel == 5'h10)) begin
xadc_vaux0_data <= xadc_data;
xadc_vaux0_ready <= 1'b1;
end
else
xadc_vaux0_ready <= 1'b0;
end
always @(posedge clk) begin
if (reset) begin
xadc_vaux8_data <= 16'd0;
xadc_vaux8_ready <= 1'b0;
end
else
if (xadc_data_ready && (channel == 5'h18)) begin
xadc_vaux8_data <= xadc_data;
xadc_vaux8_ready <= 1'b1;
end
else
xadc_vaux8_ready <= 1'b0;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A311OI_PP_SYMBOL_V
`define SKY130_FD_SC_LS__A311OI_PP_SYMBOL_V
/**
* a311oi: 3-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2 & A3) | B1 | C1)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a311oi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input C1 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A311OI_PP_SYMBOL_V
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: FIFO_READ.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module FIFO_READ (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [7:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [7:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire sub_wire1;
wire [7:0] sub_wire2;
wire rdempty = sub_wire0;
wire wrfull = sub_wire1;
wire [7:0] q = sub_wire2[7:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.rdempty (sub_wire0),
.wrfull (sub_wire1),
.q (sub_wire2)
// synopsys translate_off
,
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Cyclone II",
dcfifo_component.lpm_hint = "MAXIMIZE_SPEED=5,",
dcfifo_component.lpm_numwords = 512,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 8,
dcfifo_component.lpm_widthu = 9,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "8"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "8"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5,"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_READ.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_READ.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_READ.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_READ.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_READ_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_READ_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_READ_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_READ_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
//-------------------------------------------------------------------
//
// COPYRIGHT (C) 2011, VIPcore Group, Fudan University
//
// THIS FILE MAY NOT BE MODIFIED OR REDISTRIBUTED WITHOUT THE
// EXPRESSED WRITTEN CONSENT OF VIPcore Group
//
// VIPcore : http://soc.fudan.edu.cn/vip
// IP Owner : Yibo FAN
// Contact : [email protected]
//-------------------------------------------------------------------
// Filename : cabac_modeling.v
// Author : guo yong
// Created : 2014-02
// Description : H.265 context modeling module
//
// $Id$
//-------------------------------------------------------------------
`include "enc_defines.v"
module cabac_modeling(
//input
clk ,
rst_n ,
modeling_pair_0_i ,
modeling_pair_1_i ,
modeling_pair_2_i ,
modeling_pair_3_i ,
valid_num_modeling_i ,
cabac_start_i ,
slice_qp_i ,
slice_type_i ,
first_mb_flag_i ,
w_en_ctx_state_0_i ,
w_addr_ctx_state_0_i ,
w_data_ctx_state_0_i ,
w_en_ctx_state_1_i ,
w_addr_ctx_state_1_i ,
w_data_ctx_state_1_i ,
w_en_ctx_state_2_i ,
w_addr_ctx_state_2_i ,
w_data_ctx_state_2_i ,
w_en_ctx_state_3_i ,
w_addr_ctx_state_3_i ,
w_data_ctx_state_3_i ,
w_en_ctx_state_4_i ,
w_addr_ctx_state_4_i ,
w_data_ctx_state_4_i ,
//output
modeling_ctx_pair_0_o ,
modeling_ctx_pair_1_o ,
modeling_ctx_pair_2_o ,
modeling_ctx_pair_3_o ,
valid_num_modeling_o
);
//-----------------------------------------------------------------------------------------------------------------------------------------------------------
//
// INPUT / OUTPUT DECLARATION
//
//-----------------------------------------------------------------------------------------------------------------------------------------------------------
input clk ; //clock
input rst_n ; //reset signal
input [10:0] modeling_pair_0_i ; //{coding_mode, bin, ctx_idx} pair modeling input from binarization
input [10:0] modeling_pair_1_i ; //{coding_mode, bin, ctx_idx} pair modeling input from binarization
input [10:0] modeling_pair_2_i ; //{coding_mode, bin, ctx_idx} pair modeling input from binarization
input [10:0] modeling_pair_3_i ; //{coding_mode, bin, ctx_idx} pair modeling input from binarization
input [2:0] valid_num_modeling_i ; //valid number of modeling pairs
input cabac_start_i ;
input [5:0] slice_qp_i ;
input slice_type_i ;
input first_mb_flag_i ;
input w_en_ctx_state_0_i ; //write enable context state 0
input [5:0] w_addr_ctx_state_0_i ; //write address context state 0
input [6:0] w_data_ctx_state_0_i ; //write data context state 0
input w_en_ctx_state_1_i ; //write enable context state 1
input [5:0] w_addr_ctx_state_1_i ; //write address context state 1
input [6:0] w_data_ctx_state_1_i ; //write data context state 1
input w_en_ctx_state_2_i ; //write enable context state 2
input [5:0] w_addr_ctx_state_2_i ; //write address context state 2
input [6:0] w_data_ctx_state_2_i ; //write data context state 2
input w_en_ctx_state_3_i ; //write enable context state 3
input [5:0] w_addr_ctx_state_3_i ; //write address context state 3
input [6:0] w_data_ctx_state_3_i ; //write data context state 3
input w_en_ctx_state_4_i ; //write enable context state 4
input [5:0] w_addr_ctx_state_4_i ; //write address context state 4
input [6:0] w_data_ctx_state_4_i ; //write data context state 4
output [9:0] modeling_ctx_pair_0_o ; //{coding_mode, bin, MPS, pStateIdx} pair after modeling
output [9:0] modeling_ctx_pair_1_o ; //{coding_mode, bin, MPS, pStateIdx} pair after modeling
output [9:0] modeling_ctx_pair_2_o ; //{coding_mode, bin, MPS, pStateIdx} pair after modeling
output [9:0] modeling_ctx_pair_3_o ; //{coding_mode, bin, MPS, pStateIdx} pair after modeling
output [2:0] valid_num_modeling_o ; //valid number of modeling pairs
//-----------------------------------------------------------------------------------------------------------------------------------------------------------
//
// Reg / Wire DECLARATION
//
//-----------------------------------------------------------------------------------------------------------------------------------------------------------
reg [9:0] modeling_ctx_pair_0_o ; //{coding_mode, bin, MPS, pStateIdx} pair after modeling
reg [9:0] modeling_ctx_pair_1_o ; //{coding_mode, bin, MPS, pStateIdx} pair after modeling
reg [9:0] modeling_ctx_pair_2_o ; //{coding_mode, bin, MPS, pStateIdx} pair after modeling
reg [9:0] modeling_ctx_pair_3_o ; //{coding_mode, bin, MPS, pStateIdx} pair after modeling
reg [2:0] valid_num_modeling_o ; //valid number of modeling pairs
reg [2:0] valid_num_modeling_r ;
reg comparator01 ; //comparator between ctx_addr_0 and ctx_addr_1
reg comparator12 ; //comparator between ctx_addr_1 and ctx_addr_2
reg comparator23 ; //comparator between ctx_addr_2 and ctx_addr_3
reg comparator02 ; //comparator between ctx_addr_0 and ctx_addr_2
reg comparator03 ; //comparator between ctx_addr_0 and ctx_addr_3
reg comparator13 ; //comparator between ctx_addr_1 and ctx_addr_3
reg mps_0_r ; //mps 0
reg mps_1_r ; //mps 1
reg mps_2_r ; //mps 2
reg mps_3_r ; //mps 3
reg [5:0] pstate_0_r ; //pstate 0
reg [5:0] pstate_1_r ; //pstate 1
reg [5:0] pstate_2_r ; //pstate 2
reg [5:0] pstate_3_r ; //pstate 3
reg [6:0] ctx_state_0_m_r ; //ctx_state_i transform because bin=mps
reg [6:0] ctx_state_1_m_r ; //ctx_state_i transform because bin=mps
reg [6:0] ctx_state_2_m_r ; //ctx_state_i transform because bin=mps
reg [6:0] ctx_state_3_m_r ; //ctx_state_i transform because bin=mps
reg [6:0] ctx_state_0_l_r ; //ctx_state_i transform because bin=lps
reg [6:0] ctx_state_1_l_r ; //ctx_state_i transform because bin=lps
reg [6:0] ctx_state_2_l_r ; //ctx_state_i transform because bin=lps
reg [6:0] ctx_state_3_l_r ; //ctx_state_i transform because bin=lps
reg [6:0] ctx_state_0_u_r ; //update ctx_state_i
reg [6:0] ctx_state_1_u_r ; //update ctx_state_i
reg [6:0] ctx_state_2_u_r ; //update ctx_state_i
reg [6:0] ctx_state_3_u_r ; //update ctx_state_i
reg [6:0] ctx_state_0_r ; //ctx state 0 after arbitration
reg [6:0] ctx_state_1_r ; //ctx state 1 after arbitration
reg [6:0] ctx_state_2_r ; //ctx state 2 after arbitration
reg [6:0] ctx_state_3_r ; //ctx state 3 after arbitration
wire [6:0] ctx_state_0_w ; //ctx state 0 after arbitration
wire [6:0] ctx_state_1_w ; //ctx state 1 after arbitration
wire [6:0] ctx_state_2_w ; //ctx state 2 after arbitration
wire [6:0] ctx_state_3_w ; //ctx state 3 after arbitration
//sram 0
reg r_en_0_r ;
reg [5:0] r_addr_0_r ;
reg [6:0] r_data_0_r ;
reg [6:0] w_data_delay_0_r ;
reg w_en_0_r ;
reg [5:0] w_addr_0_r ;
reg [6:0] w_data_0_r ;
wire r_en_0_w ;
wire [5:0] r_addr_0_w ;
wire [6:0] r_data_0_w ;
wire w_en_0_w ;
wire [5:0] w_addr_0_w ;
wire [6:0] w_data_0_w ;
//sram 1
reg r_en_1_r ;
reg [5:0] r_addr_1_r ;
reg [6:0] r_data_1_r ;
reg [6:0] w_data_delay_1_r ;
reg w_en_1_r ;
reg [5:0] w_addr_1_r ;
reg [6:0] w_data_1_r ;
wire r_en_1_w ;
wire [5:0] r_addr_1_w ;
wire [6:0] r_data_1_w ;
wire w_en_1_w ;
wire [5:0] w_addr_1_w ;
wire [6:0] w_data_1_w ;
//sram 2
reg r_en_2_r ;
reg [5:0] r_addr_2_r ;
reg [6:0] r_data_2_r ;
reg [6:0] w_data_delay_2_r ;
reg w_en_2_r ;
reg [5:0] w_addr_2_r ;
reg [6:0] w_data_2_r ;
wire r_en_2_w ;
wire [5:0] r_addr_2_w ;
wire [6:0] r_data_2_w ;
wire w_en_2_w ;
wire [5:0] w_addr_2_w ;
wire [6:0] w_data_2_w ;
//sram 3
reg r_en_3_r ;
reg [5:0] r_addr_3_r ;
reg [6:0] r_data_3_r ;
reg [6:0] w_data_delay_3_r ;
reg w_en_3_r ;
reg [5:0] w_addr_3_r ;
reg [6:0] w_data_3_r ;
wire r_en_3_w ;
wire [5:0] r_addr_3_w ;
wire [6:0] r_data_3_w ;
wire w_en_3_w ;
wire [5:0] w_addr_3_w ;
wire [6:0] w_data_3_w ;
//4
reg r_en_4_r ;
reg [5:0] r_addr_4_r ;
reg [6:0] r_data_4_r ;
reg [6:0] w_data_delay_4_r ;
reg w_en_4_r ;
reg [5:0] w_addr_4_r ;
reg [6:0] w_data_4_r ;
wire r_en_4_w ;
wire [5:0] r_addr_4_w ;
wire [6:0] r_data_4_w ;
wire w_en_4_w ;
wire [5:0] w_addr_4_w ;
wire [6:0] w_data_4_w ;
reg r_en_delay_0_r ;
reg r_en_delay_1_r ;
reg r_en_delay_2_r ;
reg r_en_delay_3_r ;
reg r_en_delay_4_r ;
reg [5:0] w_addr_delay_0_r ;
reg [5:0] w_addr_delay_1_r ;
reg [5:0] w_addr_delay_2_r ;
reg [5:0] w_addr_delay_3_r ;
reg [5:0] w_addr_delay_4_r ;
reg w_addr_equal_0_r ;
reg w_addr_equal_1_r ;
reg w_addr_equal_2_r ;
reg w_addr_equal_3_r ;
reg w_addr_equal_4_r ;
reg bin_delay_0_r ;
reg bin_delay_1_r ;
reg bin_delay_2_r ;
reg bin_delay_3_r ;
reg [7:0] ctx_pair_delay_0_r ; // [7:0]
reg [7:0] ctx_pair_delay_1_r ; // [7:0]
reg [7:0] ctx_pair_delay_2_r ; // [7:0]
reg [7:0] ctx_pair_delay_3_r ; // [7:0]
reg [1:0] coding_mode_delay_0_r ;
reg [1:0] coding_mode_delay_1_r ;
reg [1:0] coding_mode_delay_2_r ;
reg [1:0] coding_mode_delay_3_r ;
//extra register
reg [6:0] ctx_state_50_r ; //the extra register {3'd5, 5'd0}
reg [6:0] ctx_state_51_r ; //the extra register {3'd5, 5'd1}
//-----------------------------------------------------------------------------------------------------------------------------------------------------------
//
// Combinational Logic
//
//-----------------------------------------------------------------------------------------------------------------------------------------------------------
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
comparator01 <= 0;
comparator12 <= 0;
comparator23 <= 0;
comparator02 <= 0;
comparator03 <= 0;
comparator13 <= 0;
end
else
begin
comparator01 <= (modeling_pair_0_i[7:0]==modeling_pair_1_i[7:0]&&modeling_pair_0_i[10:9]==2'd0&&modeling_pair_1_i[10:9]==2'd0);
comparator12 <= (modeling_pair_1_i[7:0]==modeling_pair_2_i[7:0]&&modeling_pair_1_i[10:9]==2'd0&&modeling_pair_2_i[10:9]==2'd0);
comparator23 <= (modeling_pair_2_i[7:0]==modeling_pair_3_i[7:0]&&modeling_pair_2_i[10:9]==2'd0&&modeling_pair_3_i[10:9]==2'd0);
comparator02 <= (modeling_pair_0_i[7:0]==modeling_pair_2_i[7:0]&&modeling_pair_0_i[10:9]==2'd0&&modeling_pair_2_i[10:9]==2'd0);
comparator03 <= (modeling_pair_0_i[7:0]==modeling_pair_3_i[7:0]&&modeling_pair_0_i[10:9]==2'd0&&modeling_pair_3_i[10:9]==2'd0);
comparator13 <= (modeling_pair_1_i[7:0]==modeling_pair_3_i[7:0]&&modeling_pair_1_i[10:9]==2'd0&&modeling_pair_3_i[10:9]==2'd0);
end
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
modeling_ctx_pair_0_o <= 10'h1ff;
modeling_ctx_pair_1_o <= 10'h1ff;
modeling_ctx_pair_2_o <= 10'h1ff;
modeling_ctx_pair_3_o <= 10'h1ff;
end
else begin
modeling_ctx_pair_0_o <= ( (valid_num_modeling_r>3'd0) ?
( coding_mode_delay_0_r==2'b00 ? {coding_mode_delay_0_r, bin_delay_0_r, mps_0_r, pstate_0_r[5:0]}:{coding_mode_delay_0_r, ctx_pair_delay_0_r} )
: 10'h1ff);
modeling_ctx_pair_1_o <= ( (valid_num_modeling_r>3'd1) ?
( coding_mode_delay_1_r==2'b00 ? {coding_mode_delay_1_r, bin_delay_1_r, mps_1_r, pstate_1_r[5:0]}:{coding_mode_delay_1_r, ctx_pair_delay_1_r} )
: 10'h1ff);
modeling_ctx_pair_2_o <= ( (valid_num_modeling_r>3'd2) ?
( coding_mode_delay_2_r==2'b00 ? {coding_mode_delay_2_r, bin_delay_2_r, mps_2_r, pstate_2_r[5:0]}:{coding_mode_delay_2_r, ctx_pair_delay_2_r} )
: 10'h1ff);
modeling_ctx_pair_3_o <= ( (valid_num_modeling_r>3'd3) ?
( coding_mode_delay_3_r==2'b00 ? {coding_mode_delay_3_r, bin_delay_3_r, mps_3_r, pstate_3_r[5:0]}:{coding_mode_delay_3_r, ctx_pair_delay_3_r} )
: 10'h1ff);
end
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
bin_delay_0_r <= 1'd0;
bin_delay_1_r <= 1'd0;
bin_delay_2_r <= 1'd0;
bin_delay_3_r <= 1'd0;
ctx_pair_delay_0_r <= 8'd0;
ctx_pair_delay_1_r <= 8'd0;
ctx_pair_delay_2_r <= 8'd0;
ctx_pair_delay_3_r <= 8'd0;
coding_mode_delay_0_r <= 2'd0;
coding_mode_delay_1_r <= 2'd0;
coding_mode_delay_2_r <= 2'd0;
coding_mode_delay_3_r <= 2'd0;
end
else begin
bin_delay_0_r <= modeling_pair_0_i[8] ; // bin
bin_delay_1_r <= modeling_pair_1_i[8] ; // bin
bin_delay_2_r <= modeling_pair_2_i[8] ; // bin
bin_delay_3_r <= modeling_pair_3_i[8] ; // bin
ctx_pair_delay_0_r <= modeling_pair_0_i[7:0];
ctx_pair_delay_1_r <= modeling_pair_1_i[7:0];
ctx_pair_delay_2_r <= modeling_pair_2_i[7:0];
ctx_pair_delay_3_r <= modeling_pair_3_i[7:0];
coding_mode_delay_0_r <= modeling_pair_0_i[10:9]; // coding mode
coding_mode_delay_1_r <= modeling_pair_1_i[10:9]; // coding mode
coding_mode_delay_2_r <= modeling_pair_2_i[10:9]; // coding mode
coding_mode_delay_3_r <= modeling_pair_3_i[10:9]; // coding mode
end
end
reg reg_00_r ;
reg reg_10_r ;
reg reg_20_r ;
reg reg_30_r ;
reg reg_01_r ;
reg reg_11_r ;
reg reg_21_r ;
reg reg_31_r ;
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
reg_00_r <= 'd0;
else if(!modeling_pair_0_i[10:9]&&modeling_pair_0_i[7:0]=={3'd5, 5'd0})
reg_00_r <= 'd1;
else
reg_00_r <= 'd0;
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
reg_10_r <= 'd0;
else if(!modeling_pair_1_i[10:9]&&modeling_pair_1_i[7:0]=={3'd5, 5'd0})
reg_10_r <= 'd1;
else
reg_10_r <= 'd0;
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
reg_20_r <= 'd0;
else if(!modeling_pair_2_i[10:9]&&modeling_pair_2_i[7:0]=={3'd5, 5'd0})
reg_20_r <= 'd1;
else
reg_20_r <= 'd0;
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
reg_30_r <= 'd0;
else if(!modeling_pair_3_i[10:9]&&modeling_pair_3_i[7:0]=={3'd5, 5'd0})
reg_30_r <= 'd1;
else
reg_30_r <= 'd0;
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
reg_01_r <= 'd0;
else if(!modeling_pair_0_i[10:9]&&modeling_pair_0_i[7:0]=={3'd5, 5'd1})
reg_01_r <= 'd1;
else
reg_01_r <= 'd0;
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
reg_11_r <= 'd0;
else if(!modeling_pair_1_i[10:9]&&modeling_pair_1_i[7:0]=={3'd5, 5'd1})
reg_11_r <= 'd1;
else
reg_11_r <= 'd0;
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
reg_21_r <= 'd0;
else if(!modeling_pair_2_i[10:9]&&modeling_pair_2_i[7:0]=={3'd5, 5'd1})
reg_21_r <= 'd1;
else
reg_21_r <= 'd0;
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
reg_31_r <= 'd0;
else if(!modeling_pair_3_i[10:9]&&modeling_pair_3_i[7:0]=={3'd5, 5'd1})
reg_31_r <= 'd1;
else
reg_31_r <= 'd0;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
w_data_delay_0_r <= 0;
w_data_delay_1_r <= 0;
w_data_delay_2_r <= 0;
w_data_delay_3_r <= 0;
w_data_delay_4_r <= 0;
end
else begin
w_data_delay_0_r <= w_data_0_r;
w_data_delay_1_r <= w_data_1_r;
w_data_delay_2_r <= w_data_2_r;
w_data_delay_3_r <= w_data_3_r;
w_data_delay_4_r <= w_data_4_r;
end
end
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
valid_num_modeling_r <= 'd0;
else
valid_num_modeling_r <= valid_num_modeling_i;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
valid_num_modeling_o <= 0;
else
valid_num_modeling_o <= valid_num_modeling_r;
end
//context state arbitration
always @* begin
case(ctx_pair_delay_0_r[7:5])//ctx_pair_delay_0_r[7:5] : bank number
0: begin ctx_state_0_r = r_data_0_r; end
1: begin ctx_state_0_r = r_data_1_r; end
2: begin ctx_state_0_r = r_data_2_r; end
3: begin ctx_state_0_r = r_data_3_r; end
4: begin ctx_state_0_r = r_data_4_r; end
5: begin
if(reg_00_r)
ctx_state_0_r = ctx_state_50_r;
else
ctx_state_0_r = ctx_state_51_r;
end
default:
begin ctx_state_0_r = r_data_0_r; end
endcase
end
//bin 0
always @* begin
case(ctx_state_0_r) // nextStateLPS
0: begin ctx_state_0_l_r = 1; end
1: begin ctx_state_0_l_r = 0; end
2: begin ctx_state_0_l_r = 0; end
3: begin ctx_state_0_l_r = 1; end
4: begin ctx_state_0_l_r = 2; end
5: begin ctx_state_0_l_r = 3; end
6: begin ctx_state_0_l_r = 4; end
7: begin ctx_state_0_l_r = 5; end
8: begin ctx_state_0_l_r = 4; end
9: begin ctx_state_0_l_r = 5; end
10: begin ctx_state_0_l_r = 8; end
11: begin ctx_state_0_l_r = 9; end
12: begin ctx_state_0_l_r = 8; end
13: begin ctx_state_0_l_r = 9; end
14: begin ctx_state_0_l_r = 10; end
15: begin ctx_state_0_l_r = 11; end
16: begin ctx_state_0_l_r = 12; end
17: begin ctx_state_0_l_r = 13; end
18: begin ctx_state_0_l_r = 14; end
19: begin ctx_state_0_l_r = 15; end
20: begin ctx_state_0_l_r = 16; end
21: begin ctx_state_0_l_r = 17; end
22: begin ctx_state_0_l_r = 18; end
23: begin ctx_state_0_l_r = 19; end
24: begin ctx_state_0_l_r = 18; end
25: begin ctx_state_0_l_r = 19; end
26: begin ctx_state_0_l_r = 22; end
27: begin ctx_state_0_l_r = 23; end
28: begin ctx_state_0_l_r = 22; end
29: begin ctx_state_0_l_r = 23; end
30: begin ctx_state_0_l_r = 24; end
31: begin ctx_state_0_l_r = 25; end
32: begin ctx_state_0_l_r = 26; end
33: begin ctx_state_0_l_r = 27; end
34: begin ctx_state_0_l_r = 26; end
35: begin ctx_state_0_l_r = 27; end
36: begin ctx_state_0_l_r = 30; end
37: begin ctx_state_0_l_r = 31; end
38: begin ctx_state_0_l_r = 30; end
39: begin ctx_state_0_l_r = 31; end
40: begin ctx_state_0_l_r = 32; end
41: begin ctx_state_0_l_r = 33; end
42: begin ctx_state_0_l_r = 32; end
43: begin ctx_state_0_l_r = 33; end
44: begin ctx_state_0_l_r = 36; end
45: begin ctx_state_0_l_r = 37; end
46: begin ctx_state_0_l_r = 36; end
47: begin ctx_state_0_l_r = 37; end
48: begin ctx_state_0_l_r = 38; end
49: begin ctx_state_0_l_r = 39; end
50: begin ctx_state_0_l_r = 38; end
51: begin ctx_state_0_l_r = 39; end
52: begin ctx_state_0_l_r = 42; end
53: begin ctx_state_0_l_r = 43; end
54: begin ctx_state_0_l_r = 42; end
55: begin ctx_state_0_l_r = 43; end
56: begin ctx_state_0_l_r = 44; end
57: begin ctx_state_0_l_r = 45; end
58: begin ctx_state_0_l_r = 44; end
59: begin ctx_state_0_l_r = 45; end
60: begin ctx_state_0_l_r = 46; end
61: begin ctx_state_0_l_r = 47; end
62: begin ctx_state_0_l_r = 48; end
63: begin ctx_state_0_l_r = 49; end
64: begin ctx_state_0_l_r = 48; end
65: begin ctx_state_0_l_r = 49; end
66: begin ctx_state_0_l_r = 50; end
67: begin ctx_state_0_l_r = 51; end
68: begin ctx_state_0_l_r = 52; end
69: begin ctx_state_0_l_r = 53; end
70: begin ctx_state_0_l_r = 52; end
71: begin ctx_state_0_l_r = 53; end
72: begin ctx_state_0_l_r = 54; end
73: begin ctx_state_0_l_r = 55; end
74: begin ctx_state_0_l_r = 54; end
75: begin ctx_state_0_l_r = 55; end
76: begin ctx_state_0_l_r = 56; end
77: begin ctx_state_0_l_r = 57; end
78: begin ctx_state_0_l_r = 58; end
79: begin ctx_state_0_l_r = 59; end
80: begin ctx_state_0_l_r = 58; end
81: begin ctx_state_0_l_r = 59; end
82: begin ctx_state_0_l_r = 60; end
83: begin ctx_state_0_l_r = 61; end
84: begin ctx_state_0_l_r = 60; end
85: begin ctx_state_0_l_r = 61; end
86: begin ctx_state_0_l_r = 60; end
87: begin ctx_state_0_l_r = 61; end
88: begin ctx_state_0_l_r = 62; end
89: begin ctx_state_0_l_r = 63; end
90: begin ctx_state_0_l_r = 64; end
91: begin ctx_state_0_l_r = 65; end
92: begin ctx_state_0_l_r = 64; end
93: begin ctx_state_0_l_r = 65; end
94: begin ctx_state_0_l_r = 66; end
95: begin ctx_state_0_l_r = 67; end
96: begin ctx_state_0_l_r = 66; end
97: begin ctx_state_0_l_r = 67; end
98: begin ctx_state_0_l_r = 66; end
99: begin ctx_state_0_l_r = 67; end
100: begin ctx_state_0_l_r = 68; end
101: begin ctx_state_0_l_r = 69; end
102: begin ctx_state_0_l_r = 68; end
103: begin ctx_state_0_l_r = 69; end
104: begin ctx_state_0_l_r = 70; end
105: begin ctx_state_0_l_r = 71; end
106: begin ctx_state_0_l_r = 70; end
107: begin ctx_state_0_l_r = 71; end
108: begin ctx_state_0_l_r = 70; end
109: begin ctx_state_0_l_r = 71; end
110: begin ctx_state_0_l_r = 72; end
111: begin ctx_state_0_l_r = 73; end
112: begin ctx_state_0_l_r = 72; end
113: begin ctx_state_0_l_r = 73; end
114: begin ctx_state_0_l_r = 72; end
115: begin ctx_state_0_l_r = 73; end
116: begin ctx_state_0_l_r = 74; end
117: begin ctx_state_0_l_r = 75; end
118: begin ctx_state_0_l_r = 74; end
119: begin ctx_state_0_l_r = 75; end
120: begin ctx_state_0_l_r = 74; end
121: begin ctx_state_0_l_r = 75; end
122: begin ctx_state_0_l_r = 76; end
123: begin ctx_state_0_l_r = 77; end
124: begin ctx_state_0_l_r = 76; end
125: begin ctx_state_0_l_r = 77; end
126: begin ctx_state_0_l_r = 126; end
127: begin ctx_state_0_l_r = 127; end
default: begin ctx_state_0_l_r = 0; end
endcase
end
always @* begin //nextStateMPS
if(ctx_state_0_r<=123)
ctx_state_0_m_r = ctx_state_0_r + 2;
else
ctx_state_0_m_r = ctx_state_0_r;
end
always @* begin // nextState
if(bin_delay_0_r==ctx_state_0_r[0])
ctx_state_0_u_r = ctx_state_0_m_r; // bin == MPS
else
ctx_state_0_u_r = ctx_state_0_l_r; // bin == LPS
end
always @* begin
if(comparator01)
ctx_state_1_r = ctx_state_0_u_r; // bin 1 initial state
else begin
case(ctx_pair_delay_1_r[7:5])
0: begin ctx_state_1_r = r_data_0_r; end
1: begin ctx_state_1_r = r_data_1_r; end
2: begin ctx_state_1_r = r_data_2_r; end
3: begin ctx_state_1_r = r_data_3_r; end
4: begin ctx_state_1_r = r_data_4_r; end
5: begin
if(reg_10_r)
ctx_state_1_r = ctx_state_50_r;
else
ctx_state_1_r = ctx_state_51_r;
end
default:
begin ctx_state_1_r = r_data_0_r; end
endcase
end
end
always @* begin
if(comparator12)
ctx_state_2_r = ctx_state_1_u_r;
else if(comparator02)
ctx_state_2_r = ctx_state_0_u_r;
else begin
case(ctx_pair_delay_2_r[7:5])
0: begin ctx_state_2_r = r_data_0_r; end
1: begin ctx_state_2_r = r_data_1_r; end
2: begin ctx_state_2_r = r_data_2_r; end
3: begin ctx_state_2_r = r_data_3_r; end
4: begin ctx_state_2_r = r_data_4_r; end
5: begin
if(reg_20_r)
ctx_state_2_r = ctx_state_50_r;
else
ctx_state_2_r = ctx_state_51_r;
end
default:
begin ctx_state_2_r = r_data_0_r; end
endcase
end
end
always @* begin
if(comparator23)
ctx_state_3_r = ctx_state_2_u_r;
else if(comparator13)
ctx_state_3_r = ctx_state_1_u_r;
else if(comparator03)
ctx_state_3_r = ctx_state_0_u_r;
else begin
case(ctx_pair_delay_3_r[7:5])
0: begin ctx_state_3_r = r_data_0_r; end
1: begin ctx_state_3_r = r_data_1_r; end
2: begin ctx_state_3_r = r_data_2_r; end
3: begin ctx_state_3_r = r_data_3_r; end
4: begin ctx_state_3_r = r_data_4_r; end
5: begin
if(reg_30_r)
ctx_state_3_r = ctx_state_50_r;
else
ctx_state_3_r = ctx_state_51_r;
end
default:
begin ctx_state_3_r = r_data_0_r; end
endcase
end
end
//bin 1
always @* begin
case(ctx_state_1_r)
0: begin ctx_state_1_l_r = 1; end
1: begin ctx_state_1_l_r = 0; end
2: begin ctx_state_1_l_r = 0; end
3: begin ctx_state_1_l_r = 1; end
4: begin ctx_state_1_l_r = 2; end
5: begin ctx_state_1_l_r = 3; end
6: begin ctx_state_1_l_r = 4; end
7: begin ctx_state_1_l_r = 5; end
8: begin ctx_state_1_l_r = 4; end
9: begin ctx_state_1_l_r = 5; end
10: begin ctx_state_1_l_r = 8; end
11: begin ctx_state_1_l_r = 9; end
12: begin ctx_state_1_l_r = 8; end
13: begin ctx_state_1_l_r = 9; end
14: begin ctx_state_1_l_r = 10; end
15: begin ctx_state_1_l_r = 11; end
16: begin ctx_state_1_l_r = 12; end
17: begin ctx_state_1_l_r = 13; end
18: begin ctx_state_1_l_r = 14; end
19: begin ctx_state_1_l_r = 15; end
20: begin ctx_state_1_l_r = 16; end
21: begin ctx_state_1_l_r = 17; end
22: begin ctx_state_1_l_r = 18; end
23: begin ctx_state_1_l_r = 19; end
24: begin ctx_state_1_l_r = 18; end
25: begin ctx_state_1_l_r = 19; end
26: begin ctx_state_1_l_r = 22; end
27: begin ctx_state_1_l_r = 23; end
28: begin ctx_state_1_l_r = 22; end
29: begin ctx_state_1_l_r = 23; end
30: begin ctx_state_1_l_r = 24; end
31: begin ctx_state_1_l_r = 25; end
32: begin ctx_state_1_l_r = 26; end
33: begin ctx_state_1_l_r = 27; end
34: begin ctx_state_1_l_r = 26; end
35: begin ctx_state_1_l_r = 27; end
36: begin ctx_state_1_l_r = 30; end
37: begin ctx_state_1_l_r = 31; end
38: begin ctx_state_1_l_r = 30; end
39: begin ctx_state_1_l_r = 31; end
40: begin ctx_state_1_l_r = 32; end
41: begin ctx_state_1_l_r = 33; end
42: begin ctx_state_1_l_r = 32; end
43: begin ctx_state_1_l_r = 33; end
44: begin ctx_state_1_l_r = 36; end
45: begin ctx_state_1_l_r = 37; end
46: begin ctx_state_1_l_r = 36; end
47: begin ctx_state_1_l_r = 37; end
48: begin ctx_state_1_l_r = 38; end
49: begin ctx_state_1_l_r = 39; end
50: begin ctx_state_1_l_r = 38; end
51: begin ctx_state_1_l_r = 39; end
52: begin ctx_state_1_l_r = 42; end
53: begin ctx_state_1_l_r = 43; end
54: begin ctx_state_1_l_r = 42; end
55: begin ctx_state_1_l_r = 43; end
56: begin ctx_state_1_l_r = 44; end
57: begin ctx_state_1_l_r = 45; end
58: begin ctx_state_1_l_r = 44; end
59: begin ctx_state_1_l_r = 45; end
60: begin ctx_state_1_l_r = 46; end
61: begin ctx_state_1_l_r = 47; end
62: begin ctx_state_1_l_r = 48; end
63: begin ctx_state_1_l_r = 49; end
64: begin ctx_state_1_l_r = 48; end
65: begin ctx_state_1_l_r = 49; end
66: begin ctx_state_1_l_r = 50; end
67: begin ctx_state_1_l_r = 51; end
68: begin ctx_state_1_l_r = 52; end
69: begin ctx_state_1_l_r = 53; end
70: begin ctx_state_1_l_r = 52; end
71: begin ctx_state_1_l_r = 53; end
72: begin ctx_state_1_l_r = 54; end
73: begin ctx_state_1_l_r = 55; end
74: begin ctx_state_1_l_r = 54; end
75: begin ctx_state_1_l_r = 55; end
76: begin ctx_state_1_l_r = 56; end
77: begin ctx_state_1_l_r = 57; end
78: begin ctx_state_1_l_r = 58; end
79: begin ctx_state_1_l_r = 59; end
80: begin ctx_state_1_l_r = 58; end
81: begin ctx_state_1_l_r = 59; end
82: begin ctx_state_1_l_r = 60; end
83: begin ctx_state_1_l_r = 61; end
84: begin ctx_state_1_l_r = 60; end
85: begin ctx_state_1_l_r = 61; end
86: begin ctx_state_1_l_r = 60; end
87: begin ctx_state_1_l_r = 61; end
88: begin ctx_state_1_l_r = 62; end
89: begin ctx_state_1_l_r = 63; end
90: begin ctx_state_1_l_r = 64; end
91: begin ctx_state_1_l_r = 65; end
92: begin ctx_state_1_l_r = 64; end
93: begin ctx_state_1_l_r = 65; end
94: begin ctx_state_1_l_r = 66; end
95: begin ctx_state_1_l_r = 67; end
96: begin ctx_state_1_l_r = 66; end
97: begin ctx_state_1_l_r = 67; end
98: begin ctx_state_1_l_r = 66; end
99: begin ctx_state_1_l_r = 67; end
100: begin ctx_state_1_l_r = 68; end
101: begin ctx_state_1_l_r = 69; end
102: begin ctx_state_1_l_r = 68; end
103: begin ctx_state_1_l_r = 69; end
104: begin ctx_state_1_l_r = 70; end
105: begin ctx_state_1_l_r = 71; end
106: begin ctx_state_1_l_r = 70; end
107: begin ctx_state_1_l_r = 71; end
108: begin ctx_state_1_l_r = 70; end
109: begin ctx_state_1_l_r = 71; end
110: begin ctx_state_1_l_r = 72; end
111: begin ctx_state_1_l_r = 73; end
112: begin ctx_state_1_l_r = 72; end
113: begin ctx_state_1_l_r = 73; end
114: begin ctx_state_1_l_r = 72; end
115: begin ctx_state_1_l_r = 73; end
116: begin ctx_state_1_l_r = 74; end
117: begin ctx_state_1_l_r = 75; end
118: begin ctx_state_1_l_r = 74; end
119: begin ctx_state_1_l_r = 75; end
120: begin ctx_state_1_l_r = 74; end
121: begin ctx_state_1_l_r = 75; end
122: begin ctx_state_1_l_r = 76; end
123: begin ctx_state_1_l_r = 77; end
124: begin ctx_state_1_l_r = 76; end
125: begin ctx_state_1_l_r = 77; end
126: begin ctx_state_1_l_r = 126; end
127: begin ctx_state_1_l_r = 127; end
default: begin ctx_state_1_l_r = 0; end
endcase
end
always @* begin
if(ctx_state_1_r<=123)
ctx_state_1_m_r = ctx_state_1_r + 2;
else
ctx_state_1_m_r = ctx_state_1_r;
end
always @* begin
if(bin_delay_1_r==ctx_state_1_r[0])
ctx_state_1_u_r = ctx_state_1_m_r;
else
ctx_state_1_u_r = ctx_state_1_l_r;
end
//bin 2
always @* begin
case(ctx_state_2_r)
0: begin ctx_state_2_l_r = 1; end
1: begin ctx_state_2_l_r = 0; end
2: begin ctx_state_2_l_r = 0; end
3: begin ctx_state_2_l_r = 1; end
4: begin ctx_state_2_l_r = 2; end
5: begin ctx_state_2_l_r = 3; end
6: begin ctx_state_2_l_r = 4; end
7: begin ctx_state_2_l_r = 5; end
8: begin ctx_state_2_l_r = 4; end
9: begin ctx_state_2_l_r = 5; end
10: begin ctx_state_2_l_r = 8; end
11: begin ctx_state_2_l_r = 9; end
12: begin ctx_state_2_l_r = 8; end
13: begin ctx_state_2_l_r = 9; end
14: begin ctx_state_2_l_r = 10; end
15: begin ctx_state_2_l_r = 11; end
16: begin ctx_state_2_l_r = 12; end
17: begin ctx_state_2_l_r = 13; end
18: begin ctx_state_2_l_r = 14; end
19: begin ctx_state_2_l_r = 15; end
20: begin ctx_state_2_l_r = 16; end
21: begin ctx_state_2_l_r = 17; end
22: begin ctx_state_2_l_r = 18; end
23: begin ctx_state_2_l_r = 19; end
24: begin ctx_state_2_l_r = 18; end
25: begin ctx_state_2_l_r = 19; end
26: begin ctx_state_2_l_r = 22; end
27: begin ctx_state_2_l_r = 23; end
28: begin ctx_state_2_l_r = 22; end
29: begin ctx_state_2_l_r = 23; end
30: begin ctx_state_2_l_r = 24; end
31: begin ctx_state_2_l_r = 25; end
32: begin ctx_state_2_l_r = 26; end
33: begin ctx_state_2_l_r = 27; end
34: begin ctx_state_2_l_r = 26; end
35: begin ctx_state_2_l_r = 27; end
36: begin ctx_state_2_l_r = 30; end
37: begin ctx_state_2_l_r = 31; end
38: begin ctx_state_2_l_r = 30; end
39: begin ctx_state_2_l_r = 31; end
40: begin ctx_state_2_l_r = 32; end
41: begin ctx_state_2_l_r = 33; end
42: begin ctx_state_2_l_r = 32; end
43: begin ctx_state_2_l_r = 33; end
44: begin ctx_state_2_l_r = 36; end
45: begin ctx_state_2_l_r = 37; end
46: begin ctx_state_2_l_r = 36; end
47: begin ctx_state_2_l_r = 37; end
48: begin ctx_state_2_l_r = 38; end
49: begin ctx_state_2_l_r = 39; end
50: begin ctx_state_2_l_r = 38; end
51: begin ctx_state_2_l_r = 39; end
52: begin ctx_state_2_l_r = 42; end
53: begin ctx_state_2_l_r = 43; end
54: begin ctx_state_2_l_r = 42; end
55: begin ctx_state_2_l_r = 43; end
56: begin ctx_state_2_l_r = 44; end
57: begin ctx_state_2_l_r = 45; end
58: begin ctx_state_2_l_r = 44; end
59: begin ctx_state_2_l_r = 45; end
60: begin ctx_state_2_l_r = 46; end
61: begin ctx_state_2_l_r = 47; end
62: begin ctx_state_2_l_r = 48; end
63: begin ctx_state_2_l_r = 49; end
64: begin ctx_state_2_l_r = 48; end
65: begin ctx_state_2_l_r = 49; end
66: begin ctx_state_2_l_r = 50; end
67: begin ctx_state_2_l_r = 51; end
68: begin ctx_state_2_l_r = 52; end
69: begin ctx_state_2_l_r = 53; end
70: begin ctx_state_2_l_r = 52; end
71: begin ctx_state_2_l_r = 53; end
72: begin ctx_state_2_l_r = 54; end
73: begin ctx_state_2_l_r = 55; end
74: begin ctx_state_2_l_r = 54; end
75: begin ctx_state_2_l_r = 55; end
76: begin ctx_state_2_l_r = 56; end
77: begin ctx_state_2_l_r = 57; end
78: begin ctx_state_2_l_r = 58; end
79: begin ctx_state_2_l_r = 59; end
80: begin ctx_state_2_l_r = 58; end
81: begin ctx_state_2_l_r = 59; end
82: begin ctx_state_2_l_r = 60; end
83: begin ctx_state_2_l_r = 61; end
84: begin ctx_state_2_l_r = 60; end
85: begin ctx_state_2_l_r = 61; end
86: begin ctx_state_2_l_r = 60; end
87: begin ctx_state_2_l_r = 61; end
88: begin ctx_state_2_l_r = 62; end
89: begin ctx_state_2_l_r = 63; end
90: begin ctx_state_2_l_r = 64; end
91: begin ctx_state_2_l_r = 65; end
92: begin ctx_state_2_l_r = 64; end
93: begin ctx_state_2_l_r = 65; end
94: begin ctx_state_2_l_r = 66; end
95: begin ctx_state_2_l_r = 67; end
96: begin ctx_state_2_l_r = 66; end
97: begin ctx_state_2_l_r = 67; end
98: begin ctx_state_2_l_r = 66; end
99: begin ctx_state_2_l_r = 67; end
100: begin ctx_state_2_l_r = 68; end
101: begin ctx_state_2_l_r = 69; end
102: begin ctx_state_2_l_r = 68; end
103: begin ctx_state_2_l_r = 69; end
104: begin ctx_state_2_l_r = 70; end
105: begin ctx_state_2_l_r = 71; end
106: begin ctx_state_2_l_r = 70; end
107: begin ctx_state_2_l_r = 71; end
108: begin ctx_state_2_l_r = 70; end
109: begin ctx_state_2_l_r = 71; end
110: begin ctx_state_2_l_r = 72; end
111: begin ctx_state_2_l_r = 73; end
112: begin ctx_state_2_l_r = 72; end
113: begin ctx_state_2_l_r = 73; end
114: begin ctx_state_2_l_r = 72; end
115: begin ctx_state_2_l_r = 73; end
116: begin ctx_state_2_l_r = 74; end
117: begin ctx_state_2_l_r = 75; end
118: begin ctx_state_2_l_r = 74; end
119: begin ctx_state_2_l_r = 75; end
120: begin ctx_state_2_l_r = 74; end
121: begin ctx_state_2_l_r = 75; end
122: begin ctx_state_2_l_r = 76; end
123: begin ctx_state_2_l_r = 77; end
124: begin ctx_state_2_l_r = 76; end
125: begin ctx_state_2_l_r = 77; end
126: begin ctx_state_2_l_r = 126; end
127: begin ctx_state_2_l_r = 127; end
default: begin ctx_state_2_l_r = 0; end
endcase
end
always @* begin
if(ctx_state_2_r<=123)
ctx_state_2_m_r = ctx_state_2_r + 2;
else
ctx_state_2_m_r = ctx_state_2_r;
end
always @* begin
if(bin_delay_2_r==ctx_state_2_r[0])
ctx_state_2_u_r = ctx_state_2_m_r;
else
ctx_state_2_u_r = ctx_state_2_l_r;
end
//bin 3
always @* begin
case(ctx_state_3_r)
0: begin ctx_state_3_l_r = 1; end
1: begin ctx_state_3_l_r = 0; end
2: begin ctx_state_3_l_r = 0; end
3: begin ctx_state_3_l_r = 1; end
4: begin ctx_state_3_l_r = 2; end
5: begin ctx_state_3_l_r = 3; end
6: begin ctx_state_3_l_r = 4; end
7: begin ctx_state_3_l_r = 5; end
8: begin ctx_state_3_l_r = 4; end
9: begin ctx_state_3_l_r = 5; end
10: begin ctx_state_3_l_r = 8; end
11: begin ctx_state_3_l_r = 9; end
12: begin ctx_state_3_l_r = 8; end
13: begin ctx_state_3_l_r = 9; end
14: begin ctx_state_3_l_r = 10; end
15: begin ctx_state_3_l_r = 11; end
16: begin ctx_state_3_l_r = 12; end
17: begin ctx_state_3_l_r = 13; end
18: begin ctx_state_3_l_r = 14; end
19: begin ctx_state_3_l_r = 15; end
20: begin ctx_state_3_l_r = 16; end
21: begin ctx_state_3_l_r = 17; end
22: begin ctx_state_3_l_r = 18; end
23: begin ctx_state_3_l_r = 19; end
24: begin ctx_state_3_l_r = 18; end
25: begin ctx_state_3_l_r = 19; end
26: begin ctx_state_3_l_r = 22; end
27: begin ctx_state_3_l_r = 23; end
28: begin ctx_state_3_l_r = 22; end
29: begin ctx_state_3_l_r = 23; end
30: begin ctx_state_3_l_r = 24; end
31: begin ctx_state_3_l_r = 25; end
32: begin ctx_state_3_l_r = 26; end
33: begin ctx_state_3_l_r = 27; end
34: begin ctx_state_3_l_r = 26; end
35: begin ctx_state_3_l_r = 27; end
36: begin ctx_state_3_l_r = 30; end
37: begin ctx_state_3_l_r = 31; end
38: begin ctx_state_3_l_r = 30; end
39: begin ctx_state_3_l_r = 31; end
40: begin ctx_state_3_l_r = 32; end
41: begin ctx_state_3_l_r = 33; end
42: begin ctx_state_3_l_r = 32; end
43: begin ctx_state_3_l_r = 33; end
44: begin ctx_state_3_l_r = 36; end
45: begin ctx_state_3_l_r = 37; end
46: begin ctx_state_3_l_r = 36; end
47: begin ctx_state_3_l_r = 37; end
48: begin ctx_state_3_l_r = 38; end
49: begin ctx_state_3_l_r = 39; end
50: begin ctx_state_3_l_r = 38; end
51: begin ctx_state_3_l_r = 39; end
52: begin ctx_state_3_l_r = 42; end
53: begin ctx_state_3_l_r = 43; end
54: begin ctx_state_3_l_r = 42; end
55: begin ctx_state_3_l_r = 43; end
56: begin ctx_state_3_l_r = 44; end
57: begin ctx_state_3_l_r = 45; end
58: begin ctx_state_3_l_r = 44; end
59: begin ctx_state_3_l_r = 45; end
60: begin ctx_state_3_l_r = 46; end
61: begin ctx_state_3_l_r = 47; end
62: begin ctx_state_3_l_r = 48; end
63: begin ctx_state_3_l_r = 49; end
64: begin ctx_state_3_l_r = 48; end
65: begin ctx_state_3_l_r = 49; end
66: begin ctx_state_3_l_r = 50; end
67: begin ctx_state_3_l_r = 51; end
68: begin ctx_state_3_l_r = 52; end
69: begin ctx_state_3_l_r = 53; end
70: begin ctx_state_3_l_r = 52; end
71: begin ctx_state_3_l_r = 53; end
72: begin ctx_state_3_l_r = 54; end
73: begin ctx_state_3_l_r = 55; end
74: begin ctx_state_3_l_r = 54; end
75: begin ctx_state_3_l_r = 55; end
76: begin ctx_state_3_l_r = 56; end
77: begin ctx_state_3_l_r = 57; end
78: begin ctx_state_3_l_r = 58; end
79: begin ctx_state_3_l_r = 59; end
80: begin ctx_state_3_l_r = 58; end
81: begin ctx_state_3_l_r = 59; end
82: begin ctx_state_3_l_r = 60; end
83: begin ctx_state_3_l_r = 61; end
84: begin ctx_state_3_l_r = 60; end
85: begin ctx_state_3_l_r = 61; end
86: begin ctx_state_3_l_r = 60; end
87: begin ctx_state_3_l_r = 61; end
88: begin ctx_state_3_l_r = 62; end
89: begin ctx_state_3_l_r = 63; end
90: begin ctx_state_3_l_r = 64; end
91: begin ctx_state_3_l_r = 65; end
92: begin ctx_state_3_l_r = 64; end
93: begin ctx_state_3_l_r = 65; end
94: begin ctx_state_3_l_r = 66; end
95: begin ctx_state_3_l_r = 67; end
96: begin ctx_state_3_l_r = 66; end
97: begin ctx_state_3_l_r = 67; end
98: begin ctx_state_3_l_r = 66; end
99: begin ctx_state_3_l_r = 67; end
100: begin ctx_state_3_l_r = 68; end
101: begin ctx_state_3_l_r = 69; end
102: begin ctx_state_3_l_r = 68; end
103: begin ctx_state_3_l_r = 69; end
104: begin ctx_state_3_l_r = 70; end
105: begin ctx_state_3_l_r = 71; end
106: begin ctx_state_3_l_r = 70; end
107: begin ctx_state_3_l_r = 71; end
108: begin ctx_state_3_l_r = 70; end
109: begin ctx_state_3_l_r = 71; end
110: begin ctx_state_3_l_r = 72; end
111: begin ctx_state_3_l_r = 73; end
112: begin ctx_state_3_l_r = 72; end
113: begin ctx_state_3_l_r = 73; end
114: begin ctx_state_3_l_r = 72; end
115: begin ctx_state_3_l_r = 73; end
116: begin ctx_state_3_l_r = 74; end
117: begin ctx_state_3_l_r = 75; end
118: begin ctx_state_3_l_r = 74; end
119: begin ctx_state_3_l_r = 75; end
120: begin ctx_state_3_l_r = 74; end
121: begin ctx_state_3_l_r = 75; end
122: begin ctx_state_3_l_r = 76; end
123: begin ctx_state_3_l_r = 77; end
124: begin ctx_state_3_l_r = 76; end
125: begin ctx_state_3_l_r = 77; end
126: begin ctx_state_3_l_r = 126; end
127: begin ctx_state_3_l_r = 127; end
default: begin ctx_state_3_l_r = 0; end
endcase
end
always @* begin
if(ctx_state_3_r<=123)
ctx_state_3_m_r = ctx_state_3_r + 2;
else
ctx_state_3_m_r = ctx_state_3_r;
end
always @* begin
if(bin_delay_3_r==ctx_state_3_r[0])
ctx_state_3_u_r = ctx_state_3_m_r;
else
ctx_state_3_u_r = ctx_state_3_l_r;
end
//mps and pstate for modeling_ctx_pair
always @* begin
if(coding_mode_delay_0_r==2'd0) begin
mps_0_r = ctx_state_0_r[0];
pstate_0_r = ctx_state_0_r[6:1];
end
else begin
mps_0_r = 1;
pstate_0_r = 6'h3f;
end
end
always @* begin
if(coding_mode_delay_1_r==2'd0) begin
mps_1_r = ctx_state_1_r[0];
pstate_1_r = ctx_state_1_r[6:1];
end
else begin
mps_1_r = 1;
pstate_1_r = 6'h3f;
end
end
always @* begin
if(coding_mode_delay_2_r==2'd0) begin
mps_2_r = ctx_state_2_r[0];
pstate_2_r = ctx_state_2_r[6:1];
end
else begin
mps_2_r = 1;
pstate_2_r = 6'h3f;
end
end
always @* begin
if(coding_mode_delay_3_r==2'd0) begin
mps_3_r = ctx_state_3_r[0];
pstate_3_r = ctx_state_3_r[6:1];
end
else begin
mps_3_r = 1;
pstate_3_r = 6'h3f;
end
end
//-----------------------------------------------------------------------------------------------------------------------------------------------------------
//
// Sequential Logic
//
//-----------------------------------------------------------------------------------------------------------------------------------------------------------
always @* begin
if(w_addr_delay_1_r==r_addr_1_r)
w_addr_equal_1_r = 1;
else
w_addr_equal_1_r = 0;
end
always @* begin
if(w_addr_delay_2_r==r_addr_2_r)
w_addr_equal_2_r = 1;
else
w_addr_equal_2_r = 0;
end
always @* begin
if(w_addr_delay_3_r==r_addr_3_r)
w_addr_equal_3_r = 1;
else
w_addr_equal_3_r = 0;
end
always @* begin
if(w_addr_delay_4_r==r_addr_4_r)
w_addr_equal_4_r = 1;
else
w_addr_equal_4_r = 0;
end
reg signed [6:0] clip_qp_r ; //clip qp
wire signed [7:0] ctx_50_m_w ;
wire signed [7:0] ctx_50_n_w ;
wire signed [15:0] ctx_50_a_w ;
wire signed [15:0] ctx_50_b_w ;
wire signed [7:0] ctx_state_50_w ;
reg signed [6:0] clip_ctx_state_50_r ;
wire mps_state_50_w ;
reg cabac_start_delay1 ;
reg cabac_start_delay2 ;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
cabac_start_delay1 <= 'd0;
cabac_start_delay2 <= 'd0;
end
else begin
cabac_start_delay1 <= cabac_start_i;
cabac_start_delay2 <= cabac_start_delay1;
end
end
//clip qp
always @* begin
if(slice_qp_i<0)
clip_qp_r = 1;
else if(slice_qp_i>51)
clip_qp_r = 51;
else
clip_qp_r = slice_qp_i;// (`INIT_QP);
end
assign ctx_50_m_w = slice_type_i==(`SLICE_TYPE_I) ? 8'h00 : 8'hf1;
assign ctx_50_n_w = slice_type_i==(`SLICE_TYPE_I) ? 8'h30 : 8'h48;
assign ctx_50_a_w = ctx_50_m_w * clip_qp_r;
assign ctx_50_b_w = ctx_50_a_w >> 4 ;// + ctx_50_n_w;
assign ctx_state_50_w = ctx_50_b_w + ctx_50_n_w;
assign mps_state_50_w = (clip_ctx_state_50_r>='d64) ? 'd1 : 'd0;
always @* begin
if(ctx_state_50_w<0)
clip_ctx_state_50_r = 1;
else if(ctx_state_50_w>126)
clip_ctx_state_50_r = 126;
else
clip_ctx_state_50_r = ctx_state_50_w;
end
//ctx_state_50_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
ctx_state_50_r <= 'd0;
else if(cabac_start_delay2 && first_mb_flag_i)
ctx_state_50_r <= ((mps_state_50_w ? (clip_ctx_state_50_r-'d64) : ('d63-clip_ctx_state_50_r)) << 1) + mps_state_50_w;
else if(reg_00_r && ~comparator01 && ~comparator02 && ~comparator03)
ctx_state_50_r <= ctx_state_0_u_r;
else if(reg_10_r && ~comparator12 && ~comparator13)
ctx_state_50_r <= ctx_state_1_u_r;
else if(reg_20_r && ~comparator23)
ctx_state_50_r <= ctx_state_2_u_r;
else if(reg_30_r)
ctx_state_50_r <= ctx_state_3_u_r;
else
ctx_state_50_r <= ctx_state_50_r;
end
wire signed [7:0] ctx_51_m_w ;
wire signed [7:0] ctx_51_n_w ;
wire signed [15:0] ctx_51_a_w ;
wire signed [15:0] ctx_51_b_w ;
wire signed [7:0] ctx_state_51_w ;
reg signed [6:0] clip_ctx_state_51_r ;
wire mps_state_51_w ;
assign ctx_51_m_w = slice_type_i==(`SLICE_TYPE_I) ? 8'hfb : 8'hf6;
assign ctx_51_n_w = slice_type_i==(`SLICE_TYPE_I) ? 8'h30 : 8'h38;
assign ctx_51_a_w = ctx_51_m_w * clip_qp_r;
assign ctx_51_b_w = ctx_51_a_w >>> 4;
assign ctx_state_51_w = ctx_51_b_w + ctx_51_n_w;
assign mps_state_51_w = (clip_ctx_state_51_r>='d64) ? 'd1 : 'd0;
always @* begin
if(ctx_state_51_w<0)
clip_ctx_state_51_r = 1;
else if(ctx_state_51_w>126)
clip_ctx_state_51_r = 126;
else
clip_ctx_state_51_r = ctx_state_51_w;
end
//ctx_state_51_r
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
ctx_state_51_r <= 'd0;
else if(cabac_start_delay2 && first_mb_flag_i)
ctx_state_51_r <= ((mps_state_51_w ? (clip_ctx_state_51_r-'d64) : ('d63-clip_ctx_state_51_r)) << 1) + mps_state_51_w;
else if(reg_01_r && ~comparator01 && ~comparator02 && ~comparator03)
ctx_state_51_r <= ctx_state_0_u_r;
else if(reg_11_r && ~comparator12 && ~comparator13)
ctx_state_51_r <= ctx_state_1_u_r;
else if(reg_21_r && ~comparator23)
ctx_state_51_r <= ctx_state_2_u_r;
else if(reg_31_r)
ctx_state_51_r <= ctx_state_3_u_r;
else
ctx_state_51_r <= ctx_state_51_r;
end
//-----------------------------------------------------------------------------------------------------------------------------------------------------------
//sram 0
assign r_en_0_w = r_en_0_r ; // read enable
assign r_addr_0_w = r_addr_0_r ; // read address
assign w_en_0_w = w_en_0_r ; // write enable
assign w_addr_0_w = w_addr_0_r ; // write address
assign w_data_0_w = w_data_0_r ; // write data
reg rw_simultaneous_case_0_r ;
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
rw_simultaneous_case_0_r <= 0;
else if(r_en_0_r==w_en_0_r && r_addr_0_r==w_addr_0_r)
rw_simultaneous_case_0_r <= 1;
else
rw_simultaneous_case_0_r <= 0;
end
always @* begin
r_data_0_r = (w_addr_0_r==w_addr_delay_0_r) ? (w_data_0_r) : (rw_simultaneous_case_0_r ? w_data_delay_0_r : r_data_0_w);
end
//read
always @* begin // read enable : regular mode && sram bank number==0
if(valid_num_modeling_i>=1) begin
if( (modeling_pair_0_i[7:5]==3'd0 && modeling_pair_0_i[10:9]==2'd0) || (modeling_pair_1_i[7:5]==3'd0 && modeling_pair_1_i[10:9]==2'd0)
|| (modeling_pair_2_i[7:5]==3'd0 && modeling_pair_2_i[10:9]==2'd0) || (modeling_pair_3_i[7:5]==3'd0 && modeling_pair_3_i[10:9]==2'd0) )
r_en_0_r = 1;
else
r_en_0_r = 0;
end
else
r_en_0_r = 0;
end
always @* begin // read address : sram bank && regular mode ? address
if(valid_num_modeling_i>=1) begin
if(modeling_pair_0_i[7:5]==3'd0 && modeling_pair_0_i[10:9]==2'b00) begin
r_addr_0_r = modeling_pair_0_i[4:0] ;
end
else if(modeling_pair_1_i[7:5]==3'd0 && modeling_pair_1_i[10:9]==2'b00) begin
r_addr_0_r = modeling_pair_1_i[4:0] ;
end
else if(modeling_pair_2_i[7:5]==3'd0 && modeling_pair_2_i[10:9]==2'b00) begin
r_addr_0_r = modeling_pair_2_i[4:0] ;
end
else if(modeling_pair_3_i[7:5]==3'd0 && modeling_pair_3_i[10:9]==2'b00) begin
r_addr_0_r = modeling_pair_3_i[4:0] ;
end
else begin
r_addr_0_r = 6'd63;
end
end
else begin
r_addr_0_r = 6'd63;
end
end
//write
always @(posedge clk or negedge rst_n) begin // read enable delay 1 cycles
if(!rst_n)
r_en_delay_0_r <= 0;
else
r_en_delay_0_r <= r_en_0_r;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_addr_delay_0_r <= 0;
else
w_addr_delay_0_r <= r_addr_0_r;
end
always @* begin
if(w_addr_delay_0_r==r_addr_0_r) //judge conflict
w_addr_equal_0_r = 1;
else
w_addr_equal_0_r = 0;
end
always @(posedge clk or negedge rst_n) begin // write enable : initial enable ? initial enable : read enable ? not conflict
if(!rst_n)
w_en_0_r <= 0;
else
w_en_0_r <= w_en_ctx_state_0_i || (r_en_delay_0_r && w_addr_equal_0_r==0);
end
always @(posedge clk or negedge rst_n) begin //write address :initial enable ? initial address : read address
if(!rst_n)
w_addr_0_r <= 0;
else
w_addr_0_r <= w_en_ctx_state_0_i ? w_addr_ctx_state_0_i : w_addr_delay_0_r;
end
always @(posedge clk or negedge rst_n) begin //write data
if(!rst_n)
w_data_0_r <= 0;
else if(w_en_ctx_state_0_i) //initial
w_data_0_r <= w_data_ctx_state_0_i;
else if(ctx_pair_delay_0_r[7:5]==3'd0 && ~comparator01 && ~comparator02 && ~comparator03)
w_data_0_r <= ctx_state_0_u_r;
else if(ctx_pair_delay_1_r[7:5]==3'd0 && ~comparator12 && ~comparator13)
w_data_0_r <= ctx_state_1_u_r;
else if(ctx_pair_delay_2_r[7:5]==3'd0 && ~comparator23)
w_data_0_r <= ctx_state_2_u_r;
else if(ctx_pair_delay_3_r[7:5]==3'd0)
w_data_0_r <= ctx_state_3_u_r;
else
w_data_0_r <= w_data_0_r;
end
//-----------------------------------------------------------------------------------------------------------------------------------------------------------
//sram 1
assign r_en_1_w = r_en_1_r ;
assign r_addr_1_w = r_addr_1_r ;
assign w_en_1_w = w_en_1_r ;
assign w_addr_1_w = w_addr_1_r ;
assign w_data_1_w = w_data_1_r ;
reg rw_simultaneous_case_1_r ;
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
rw_simultaneous_case_1_r <= 0;
else if(r_en_1_r==w_en_1_r && r_addr_1_r==w_addr_1_r)
rw_simultaneous_case_1_r <= 1;
else
rw_simultaneous_case_1_r <= 0;
end
always @* begin
r_data_1_r = (w_addr_1_r==w_addr_delay_1_r) ? w_data_1_r : (rw_simultaneous_case_1_r ? w_data_delay_1_r : r_data_1_w);
end
//read
always @* begin
if(valid_num_modeling_i>=1) begin
if( (modeling_pair_0_i[7:5]==3'd1 && modeling_pair_0_i[10:9]==0) || (modeling_pair_1_i[7:5]==3'd1 && modeling_pair_1_i[10:9]==0)
|| (modeling_pair_2_i[7:5]==3'd1 && modeling_pair_2_i[10:9]==0) || (modeling_pair_3_i[7:5]==3'd1 && modeling_pair_3_i[10:9]==0) )
r_en_1_r = 1;
else
r_en_1_r = 0;
end
else
r_en_1_r = 0;
end
always @* begin
if(valid_num_modeling_i>=1) begin
if(modeling_pair_0_i[7:5]==3'd1 && modeling_pair_0_i[10:9]==2'b00) begin
r_addr_1_r = modeling_pair_0_i[4:0];
end
else if(modeling_pair_1_i[7:5]==3'd1 && modeling_pair_1_i[10:9]==2'b00) begin
r_addr_1_r = modeling_pair_1_i[4:0];
end
else if(modeling_pair_2_i[7:5]==3'd1 && modeling_pair_2_i[10:9]==2'b00) begin
r_addr_1_r = modeling_pair_2_i[4:0];
end
else if(modeling_pair_3_i[7:5]==3'd1 && modeling_pair_3_i[10:9]==2'b00) begin
r_addr_1_r = modeling_pair_3_i[4:0];
end
else begin
r_addr_1_r = 6'd63;
end
end
else begin
r_addr_1_r = 6'd63;
end
end
//write
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
r_en_delay_1_r <= 0;
else
r_en_delay_1_r <= r_en_1_r;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_en_1_r <= 0;
else
w_en_1_r <= w_en_ctx_state_1_i || (r_en_delay_1_r && w_addr_equal_1_r==0);
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_addr_delay_1_r <= 0;
else
w_addr_delay_1_r <= r_addr_1_r;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_addr_1_r <= 0;
else
w_addr_1_r <= w_en_ctx_state_1_i ? w_addr_ctx_state_1_i : w_addr_delay_1_r;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_data_1_r <= 0;
else if(w_en_ctx_state_1_i)
w_data_1_r <= w_data_ctx_state_1_i;
else if(ctx_pair_delay_0_r[7:5]==3'd1 && ~comparator01 && ~comparator02 && ~comparator03)
w_data_1_r <= ctx_state_0_u_r;
else if(ctx_pair_delay_1_r[7:5]==3'd1 && ~comparator12 && ~comparator13)
w_data_1_r <= ctx_state_1_u_r;
else if(ctx_pair_delay_2_r[7:5]==3'd1 && ~comparator23)
w_data_1_r <= ctx_state_2_u_r;
else if(ctx_pair_delay_3_r[7:5]==3'd1)
w_data_1_r <= ctx_state_3_u_r;
else
w_data_1_r <= w_data_1_r;
end
//-----------------------------------------------------------------------------------------------------------------------------------------------------------
//sram 2
assign r_en_2_w = r_en_2_r ;
assign r_addr_2_w = r_addr_2_r ;
assign w_en_2_w = w_en_2_r ;
assign w_addr_2_w = w_addr_2_r ;
assign w_data_2_w = w_data_2_r ;
reg r_en_2_delay_r ;
reg w_en_2_delay_r ;
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
r_en_2_delay_r <= 0;
w_en_2_delay_r <= 0;
end
else begin
r_en_2_delay_r <= r_en_2_r;
w_en_2_delay_r <= w_en_2_r;
end
end
reg rw_simultaneous_case_2_r ;
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
rw_simultaneous_case_2_r <= 0;
else if(r_en_2_r==w_en_2_r && r_addr_2_r==w_addr_2_r)
rw_simultaneous_case_2_r <= 1;
else
rw_simultaneous_case_2_r <= 0;
end
always @* begin
r_data_2_r = (w_addr_2_r==w_addr_delay_2_r) ? (w_data_2_r) : (rw_simultaneous_case_2_r ? w_data_delay_2_r : r_data_2_w);
end
//read
always @* begin
if(valid_num_modeling_i>=1) begin
if( (modeling_pair_0_i[7:5]==3'd2 && modeling_pair_0_i[10:9]==0) || (modeling_pair_1_i[7:5]==3'd2 && modeling_pair_1_i[10:9]==0)
|| (modeling_pair_2_i[7:5]==3'd2 && modeling_pair_2_i[10:9]==0) || (modeling_pair_3_i[7:5]==3'd2 && modeling_pair_3_i[10:9]==0) )
r_en_2_r = 1;
else
r_en_2_r = 0;
end
else
r_en_2_r = 0;
end
always @* begin
if(valid_num_modeling_i>=1) begin
if(modeling_pair_0_i[7:5]==3'd2 && modeling_pair_0_i[10:9]==2'b00) begin
r_addr_2_r = modeling_pair_0_i[4:0];
end
else if(modeling_pair_1_i[7:5]==3'd2 && modeling_pair_1_i[10:9]==2'b00) begin
r_addr_2_r = modeling_pair_1_i[4:0];
end
else if(modeling_pair_2_i[7:5]==3'd2 && modeling_pair_2_i[10:9]==2'b00) begin
r_addr_2_r = modeling_pair_2_i[4:0];
end
else if(modeling_pair_3_i[7:5]==3'd2 && modeling_pair_3_i[10:9]==2'b00) begin
r_addr_2_r = modeling_pair_3_i[4:0];
end
else begin
r_addr_2_r = 6'd63;
end
end
else begin
r_addr_2_r = 6'd63;
end
end
//write
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
r_en_delay_2_r <= 0;
else
r_en_delay_2_r <= r_en_2_r;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_en_2_r <= 0;
else
w_en_2_r <= w_en_ctx_state_2_i || (r_en_delay_2_r && w_addr_equal_2_r==0);
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_addr_delay_2_r <= 0;
else
w_addr_delay_2_r <= r_addr_2_r;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_addr_2_r <= 0;
else
w_addr_2_r <= w_en_ctx_state_2_i ? w_addr_ctx_state_2_i : w_addr_delay_2_r;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_data_2_r <= 0;
else if(w_en_ctx_state_2_i)
w_data_2_r <= w_data_ctx_state_2_i;
else if(ctx_pair_delay_0_r[7:5]==3'd2 && ~comparator01 && ~comparator02 && ~comparator03)
w_data_2_r <= ctx_state_0_u_r;
else if(ctx_pair_delay_1_r[7:5]==3'd2 && ~comparator12 && ~comparator13)
w_data_2_r <= ctx_state_1_u_r;
else if(ctx_pair_delay_2_r[7:5]==3'd2 && ~comparator23)
w_data_2_r <= ctx_state_2_u_r;
else if(ctx_pair_delay_3_r[7:5]==3'd2)
w_data_2_r <= ctx_state_3_u_r;
else
w_data_2_r <= w_data_2_r;
end
//-----------------------------------------------------------------------------------------------------------------------------------------------------------
//sram 3
assign r_en_3_w = r_en_3_r ;
assign r_addr_3_w = r_addr_3_r ;
assign w_en_3_w = w_en_3_r ;
assign w_addr_3_w = w_addr_3_r ;
assign w_data_3_w = w_data_3_r ;
reg r_en_3_delay_r ;
reg w_en_3_delay_r ;
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
r_en_3_delay_r <= 0;
w_en_3_delay_r <= 0;
end
else begin
r_en_3_delay_r <= r_en_3_r;
w_en_3_delay_r <= w_en_3_r;
end
end
reg rw_simultaneous_case_3_r ;
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
rw_simultaneous_case_3_r <= 0;
else if(r_en_3_r==w_en_3_r && r_addr_3_r==w_addr_3_r)
rw_simultaneous_case_3_r <= 1;
else
rw_simultaneous_case_3_r <= 0;
end
always @* begin
r_data_3_r = (w_addr_3_r==w_addr_delay_3_r) ? (w_data_3_r) : (rw_simultaneous_case_3_r ? w_data_delay_3_r : r_data_3_w);
end
//read
always @* begin
if(valid_num_modeling_i>=1) begin
if( (modeling_pair_0_i[7:5]==3'd3 && modeling_pair_0_i[10:9]==0) || (modeling_pair_1_i[7:5]==3'd3 && modeling_pair_1_i[10:9]==0)
|| (modeling_pair_2_i[7:5]==3'd3 && modeling_pair_2_i[10:9]==0) || (modeling_pair_3_i[7:5]==3'd3 && modeling_pair_3_i[10:9]==0) )
r_en_3_r = 1;
else
r_en_3_r = 0;
end
else
r_en_3_r = 0;
end
always @* begin
if(valid_num_modeling_i>=1) begin
if(modeling_pair_0_i[7:5]==3'd3 && modeling_pair_0_i[10:9]==2'b00) begin
r_addr_3_r = modeling_pair_0_i[4:0];
end
else if(modeling_pair_1_i[7:5]==3'd3 && modeling_pair_1_i[10:9]==2'b00) begin
r_addr_3_r = modeling_pair_1_i[4:0];
end
else if(modeling_pair_2_i[7:5]==3'd3 && modeling_pair_2_i[10:9]==2'b00) begin
r_addr_3_r = modeling_pair_2_i[4:0];
end
else if(modeling_pair_3_i[7:5]==3'd3 && modeling_pair_3_i[10:9]==2'b00) begin
r_addr_3_r = modeling_pair_3_i[4:0];
end
else begin
r_addr_3_r = 6'd63;
end
end
else begin
r_addr_3_r = 6'd63;
end
end
//write
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
r_en_delay_3_r <= 0;
else
r_en_delay_3_r <= r_en_3_r;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_en_3_r <= 0;
else
w_en_3_r <= w_en_ctx_state_3_i || (r_en_delay_3_r && w_addr_equal_3_r==0);
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_addr_delay_3_r <= 0;
else
w_addr_delay_3_r <= w_en_ctx_state_3_i ? w_addr_ctx_state_3_i : r_addr_3_r;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_addr_3_r <= 0;
else
w_addr_3_r <= w_en_ctx_state_3_i ? w_addr_ctx_state_3_i : w_addr_delay_3_r;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_data_3_r <= 0;
else if(w_en_ctx_state_3_i)
w_data_3_r <= w_data_ctx_state_3_i;
else if(ctx_pair_delay_0_r[7:5]==3'd3 && ~comparator01 && ~comparator02 && ~comparator03)
w_data_3_r <= ctx_state_0_u_r;
else if(ctx_pair_delay_1_r[7:5]==3'd3 && ~comparator12 && ~comparator13)
w_data_3_r <= ctx_state_1_u_r;
else if(ctx_pair_delay_2_r[7:5]==3'd3 && ~comparator23)
w_data_3_r <= ctx_state_2_u_r;
else if(ctx_pair_delay_3_r[7:5]==3'd3)
w_data_3_r <= ctx_state_3_u_r;
else
w_data_3_r <= w_data_3_r;
end
//-----------------------------------------------------------------------------------------------------------------------------------------------------------
//sram 4
assign r_en_4_w = r_en_4_r ;
assign r_addr_4_w = r_addr_4_r ;
assign w_en_4_w = w_en_4_r ;
assign w_addr_4_w = w_addr_4_r ;
assign w_data_4_w = w_data_4_r ;
reg r_en_4_delay_r ;
reg w_en_4_delay_r ;
always @(posedge clk or negedge rst_n) begin
if(~rst_n) begin
r_en_4_delay_r <= 0;
w_en_4_delay_r <= 0;
end
else begin
r_en_4_delay_r <= r_en_4_r;
w_en_4_delay_r <= w_en_4_r;
end
end
reg rw_simultaneous_case_4_r ;
always @(posedge clk or negedge rst_n) begin
if(~rst_n)
rw_simultaneous_case_4_r <= 0;
else if(r_en_4_r==w_en_4_r && r_addr_4_r==w_addr_4_r)
rw_simultaneous_case_4_r <= 1;
else
rw_simultaneous_case_4_r <= 0;
end
always @* begin
r_data_4_r = (w_addr_4_r==w_addr_delay_4_r) ? (w_data_4_r) : (rw_simultaneous_case_4_r ? w_data_delay_4_r : r_data_4_w);
end
//read
always @* begin
if(valid_num_modeling_i>=1) begin
if( (modeling_pair_0_i[7:5]==3'd4 && modeling_pair_0_i[10:9]==0) || (modeling_pair_1_i[7:5]==3'd4 && modeling_pair_1_i[10:9]==0)
|| (modeling_pair_2_i[7:5]==3'd4 && modeling_pair_2_i[10:9]==0) || (modeling_pair_3_i[7:5]==3'd4 && modeling_pair_3_i[10:9]==0) )
r_en_4_r = 1;
else
r_en_4_r = 0;
end
else
r_en_4_r = 0;
end
always @* begin
if(valid_num_modeling_i>=1) begin
if(modeling_pair_0_i[7:5]==3'd4 && modeling_pair_0_i[10:9]==2'b00) begin
r_addr_4_r = modeling_pair_0_i[4:0];
end
else if(modeling_pair_1_i[7:5]==3'd4 && modeling_pair_1_i[10:9]==2'b00) begin
r_addr_4_r = modeling_pair_1_i[4:0];
end
else if(modeling_pair_2_i[7:5]==3'd4 && modeling_pair_2_i[10:9]==2'b00) begin
r_addr_4_r = modeling_pair_2_i[4:0];
end
else if(modeling_pair_3_i[7:5]==3'd4 && modeling_pair_3_i[10:9]==2'b00) begin
r_addr_4_r = modeling_pair_3_i[4:0];
end
else begin
r_addr_4_r = 6'd63;
end
end
else begin
r_addr_4_r = 6'd63;
end
end
//write
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
r_en_delay_4_r <= 0;
else
r_en_delay_4_r <= r_en_4_r;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_en_4_r <= 0;
else
w_en_4_r <= w_en_ctx_state_4_i || (r_en_delay_4_r && w_addr_equal_4_r==0);
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_addr_delay_4_r <= 0;
else
w_addr_delay_4_r <= w_en_ctx_state_4_i ? w_addr_ctx_state_4_i : r_addr_4_r;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_addr_4_r <= 0;
else
w_addr_4_r <= w_en_ctx_state_4_i ? w_addr_ctx_state_4_i : w_addr_delay_4_r;
end
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
w_data_4_r <= 0;
else if(w_en_ctx_state_4_i)
w_data_4_r <= w_data_ctx_state_4_i;
else if(ctx_pair_delay_0_r[7:5]==3'd4 && ~comparator01 && ~comparator02 && ~comparator03)
w_data_4_r <= ctx_state_0_u_r;
else if(ctx_pair_delay_1_r[7:5]==3'd4 && ~comparator12 && ~comparator13)
w_data_4_r <= ctx_state_1_u_r;
else if(ctx_pair_delay_2_r[7:5]==3'd4 && ~comparator23)
w_data_4_r <= ctx_state_2_u_r;
else if(ctx_pair_delay_3_r[7:5]==3'd4)
w_data_4_r <= ctx_state_3_u_r;
else
w_data_4_r <= w_data_4_r;
end
//-----------------------------------------------------------------------------------------------------------------------------------------------------------
//
// Sub Modules
//
//-----------------------------------------------------------------------------------------------------------------------------------------------------------
//get ctx_state data from 6-SRAM and update it after using it
cabac_ctx_state_2p_7x64 cabac_ctx_state_2p_7x64_u0(
.clk (clk ),
.r_en (r_en_0_w ),
.r_addr (r_addr_0_w ),
.r_data (r_data_0_w ),
.w_en (w_en_0_w ),
.w_addr (w_addr_0_w ),
.w_data (w_data_0_w )
);
cabac_ctx_state_2p_7x64 cabac_ctx_state_2p_7x64_u1(
.clk (clk ),
.r_en (r_en_1_w ),
.r_addr (r_addr_1_w ),
.r_data (r_data_1_w ),
.w_en (w_en_1_w ),
.w_addr (w_addr_1_w ),
.w_data (w_data_1_w )
);
cabac_ctx_state_2p_7x64 cabac_ctx_state_2p_7x64_u2(
.clk (clk ),
.r_en (r_en_2_w ),
.r_addr (r_addr_2_w ),
.r_data (r_data_2_w ),
.w_en (w_en_2_w ),
.w_addr (w_addr_2_w ),
.w_data (w_data_2_w )
);
cabac_ctx_state_2p_7x64 cabac_ctx_state_2p_7x64_u3(
.clk (clk ),
.r_en (r_en_3_w ),
.r_addr (r_addr_3_w ),
.r_data (r_data_3_w ),
.w_en (w_en_3_w ),
.w_addr (w_addr_3_w ),
.w_data (w_data_3_w )
);
cabac_ctx_state_2p_7x64 cabac_ctx_state_2p_7x64_u4(
.clk (clk ),
.r_en (r_en_4_w ),
.r_addr (r_addr_4_w ),
.r_data (r_data_4_w ),
.w_en (w_en_4_w ),
.w_addr (w_addr_4_w ),
.w_data (w_data_4_w )
);
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_adc_common #(
// parameters
parameter ID = 0,
parameter CONFIG = 0,
parameter COMMON_ID = 6'h00,
parameter DRP_DISABLE = 0,
parameter USERPORTS_DISABLE = 0,
parameter GPIO_DISABLE = 0,
parameter START_CODE_DISABLE = 0) (
// clock reset
output mmcm_rst,
// adc interface
input adc_clk,
output adc_rst,
output adc_r1_mode,
output adc_ddr_edgesel,
output adc_pin_mode,
input adc_status,
input adc_sync_status,
input adc_status_ovf,
input [31:0] adc_clk_ratio,
output [31:0] adc_start_code,
output adc_sref_sync,
output adc_sync,
input [31:0] up_pps_rcounter,
input up_pps_status,
output reg up_pps_irq_mask,
// channel interface
output up_adc_ce,
input up_status_pn_err,
input up_status_pn_oos,
input up_status_or,
// drp interface
output up_drp_sel,
output up_drp_wr,
output [11:0] up_drp_addr,
output [31:0] up_drp_wdata,
input [31:0] up_drp_rdata,
input up_drp_ready,
input up_drp_locked,
// user channel control
output [ 7:0] up_usr_chanmax_out,
input [ 7:0] up_usr_chanmax_in,
input [31:0] up_adc_gpio_in,
output [31:0] up_adc_gpio_out,
// bus interface
input up_rstn,
input up_clk,
input up_wreq,
input [13:0] up_waddr,
input [31:0] up_wdata,
output up_wack,
input up_rreq,
input [13:0] up_raddr,
output [31:0] up_rdata,
output up_rack);
// parameters
localparam VERSION = 32'h000a0062;
// internal registers
reg up_adc_clk_enb_int = 'd1;
reg up_core_preset = 'd1;
reg up_mmcm_preset = 'd1;
reg up_wack_int = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_adc_clk_enb = 'd0;
reg up_mmcm_resetn = 'd0;
reg up_resetn = 'd0;
reg up_adc_sync = 'd0;
reg up_adc_sref_sync = 'd0;
reg up_adc_r1_mode = 'd0;
reg up_adc_ddr_edgesel = 'd0;
reg up_adc_pin_mode = 'd0;
reg up_status_ovf = 'd0;
reg [ 7:0] up_usr_chanmax_int = 'd0;
reg [31:0] up_adc_start_code = 'd0;
reg [31:0] up_adc_gpio_out_int = 'd0;
reg [31:0] up_timer = 'd0;
reg up_rack_int = 'd0;
reg [31:0] up_rdata_int = 'd0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire up_status_s;
wire up_sync_status_s;
wire up_status_ovf_s;
wire up_cntrl_xfer_done_s;
wire [31:0] up_adc_clk_count_s;
wire up_drp_status_s;
wire up_drp_rwn_s;
wire [31:0] up_drp_rdata_hold_s;
// decode block select
assign up_wreq_s = (up_waddr[13:8] == COMMON_ID) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:8] == COMMON_ID) ? up_rreq : 1'b0;
// processor write interface
assign up_wack = up_wack_int;
assign up_adc_ce = up_adc_clk_enb_int;
always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_adc_clk_enb_int <= 1'd1;
up_core_preset <= 1'd1;
up_mmcm_preset <= 1'd1;
up_wack_int <= 'd0;
up_scratch <= 'd0;
up_adc_clk_enb <= 'd0;
up_mmcm_resetn <= 'd0;
up_resetn <= 'd0;
up_adc_sync <= 'd0;
up_adc_sref_sync <= 'd0;
up_adc_r1_mode <= 'd0;
up_adc_ddr_edgesel <= 'd0;
up_adc_pin_mode <= 'd0;
up_pps_irq_mask <= 1'b1;
end else begin
up_adc_clk_enb_int <= ~up_adc_clk_enb;
up_core_preset <= ~up_resetn;
up_mmcm_preset <= ~up_mmcm_resetn;
up_wack_int <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h04)) begin
up_pps_irq_mask <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
up_adc_clk_enb <= up_wdata[2];
up_mmcm_resetn <= up_wdata[1];
up_resetn <= up_wdata[0];
end
if (up_adc_sync == 1'b1) begin
if (up_cntrl_xfer_done_s == 1'b1) begin
up_adc_sync <= 1'b0;
end
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_adc_sync <= up_wdata[3];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
up_adc_sref_sync <= up_wdata[4];
up_adc_r1_mode <= up_wdata[2];
up_adc_ddr_edgesel <= up_wdata[1];
up_adc_pin_mode <= up_wdata[0];
end
end
end
generate
if (DRP_DISABLE == 1) begin
assign up_drp_sel = 'd0;
assign up_drp_wr = 'd0;
assign up_drp_status_s = 'd0;
assign up_drp_rwn_s = 'd0;
assign up_drp_addr = 'd0;
assign up_drp_wdata = 'd0;
assign up_drp_rdata_hold_s = 'd0;
end else begin
reg up_drp_sel_int = 'd0;
reg up_drp_wr_int = 'd0;
reg up_drp_status_int = 'd0;
reg up_drp_rwn_int = 'd0;
reg [11:0] up_drp_addr_int = 'd0;
reg [31:0] up_drp_wdata_int = 'd0;
reg [31:0] up_drp_rdata_hold_int = 'd0;
always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_drp_sel_int <= 'd0;
up_drp_wr_int <= 'd0;
up_drp_status_int <= 'd0;
up_drp_rwn_int <= 'd0;
up_drp_addr_int <= 'd0;
up_drp_wdata_int <= 'd0;
up_drp_rdata_hold_int <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_sel_int <= 1'b1;
up_drp_wr_int <= ~up_wdata[28];
end else begin
up_drp_sel_int <= 1'b0;
up_drp_wr_int <= 1'b0;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_status_int <= 1'b1;
end else if (up_drp_ready == 1'b1) begin
up_drp_status_int <= 1'b0;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1c)) begin
up_drp_rwn_int <= up_wdata[28];
up_drp_addr_int <= up_wdata[27:16];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h1e)) begin
up_drp_wdata_int <= up_wdata;
end
if (up_drp_ready == 1'b1) begin
up_drp_rdata_hold_int <= up_drp_rdata;
end
end
end
assign up_drp_sel = up_drp_sel_int;
assign up_drp_wr = up_drp_wr_int;
assign up_drp_status_s = up_drp_status_int;
assign up_drp_rwn_s = up_drp_rwn_int;
assign up_drp_addr = up_drp_addr_int;
assign up_drp_wdata = up_drp_wdata_int;
assign up_drp_rdata_hold_s = up_drp_rdata_hold_int;
end
endgenerate
always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_status_ovf <= 'd0;
end else begin
if (up_status_ovf_s == 1'b1) begin
up_status_ovf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h22)) begin
up_status_ovf <= up_status_ovf & ~up_wdata[2];
end
end
end
assign up_usr_chanmax_out = up_usr_chanmax_int;
generate
if (USERPORTS_DISABLE == 1) begin
always @(posedge up_clk) begin
up_usr_chanmax_int <= 'd0;
end
end else begin
always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_usr_chanmax_int <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h28)) begin
up_usr_chanmax_int <= up_wdata[7:0];
end
end
end
end
endgenerate
assign up_adc_gpio_out = up_adc_gpio_out_int;
generate
if (GPIO_DISABLE == 1) begin
always @(posedge up_clk) begin
up_adc_gpio_out_int <= 'd0;
end
end else begin
always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_adc_gpio_out_int <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h2f)) begin
up_adc_gpio_out_int <= up_wdata;
end
end
end
end
endgenerate
generate
if (START_CODE_DISABLE == 1) begin
always @(posedge up_clk) begin
up_adc_start_code <= 'd0;
end
end else begin
always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_adc_start_code <= 'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h29)) begin
up_adc_start_code <= up_wdata[31:0];
end
end
end
end
endgenerate
// timer with premature termination
always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_timer <= 32'd0;
end else begin
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h40)) begin
up_timer <= up_wdata;
end else if (up_timer > 0) begin
up_timer <= up_timer - 1'b1;
end
end
end
// processor read interface
assign up_rack = up_rack_int;
assign up_rdata = up_rdata_int;
always @(posedge up_clk) begin
if (up_rstn == 0) begin
up_rack_int <= 'd0;
up_rdata_int <= 'd0;
end else begin
up_rack_int <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
8'h00: up_rdata_int <= VERSION;
8'h01: up_rdata_int <= ID;
8'h02: up_rdata_int <= up_scratch;
8'h03: up_rdata_int <= CONFIG;
8'h04: up_rdata_int <= {31'b0, up_pps_irq_mask};
8'h10: up_rdata_int <= {29'd0, up_adc_clk_enb, up_mmcm_resetn, up_resetn};
8'h11: up_rdata_int <= {27'd0, up_adc_sref_sync, up_adc_sync, up_adc_r1_mode,
up_adc_ddr_edgesel, up_adc_pin_mode};
8'h15: up_rdata_int <= up_adc_clk_count_s;
8'h16: up_rdata_int <= adc_clk_ratio;
8'h17: up_rdata_int <= {28'd0, up_status_pn_err, up_status_pn_oos, up_status_or, up_status_s};
8'h1a: up_rdata_int <= {31'd0, up_sync_status_s};
8'h1c: up_rdata_int <= {3'd0, up_drp_rwn_s, up_drp_addr, 16'b0};
8'h1d: up_rdata_int <= {14'd0, up_drp_locked, up_drp_status_s, 16'b0};
8'h1e: up_rdata_int <= up_drp_wdata;
8'h1f: up_rdata_int <= up_drp_rdata_hold_s;
8'h22: up_rdata_int <= {29'd0, up_status_ovf, 2'b0};
8'h23: up_rdata_int <= 32'd8;
8'h28: up_rdata_int <= {24'd0, up_usr_chanmax_in};
8'h29: up_rdata_int <= up_adc_start_code;
8'h2e: up_rdata_int <= up_adc_gpio_in;
8'h2f: up_rdata_int <= up_adc_gpio_out_int;
8'h30: up_rdata_int <= up_pps_rcounter;
8'h31: up_rdata_int <= {31'b0, up_pps_status};
8'h40: up_rdata_int <= up_timer;
default: up_rdata_int <= 0;
endcase
end else begin
up_rdata_int <= 32'd0;
end
end
end
// resets
ad_rst i_mmcm_rst_reg (.rst_async(up_mmcm_preset), .clk(up_clk), .rstn(), .rst(mmcm_rst));
ad_rst i_core_rst_reg (.rst_async(up_core_preset), .clk(adc_clk), .rstn(), .rst(adc_rst));
// adc control & status
up_xfer_cntrl #(.DATA_WIDTH(37)) i_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_adc_sref_sync,
up_adc_sync,
up_adc_start_code,
up_adc_r1_mode,
up_adc_ddr_edgesel,
up_adc_pin_mode}),
.up_xfer_done (up_cntrl_xfer_done_s),
.d_rst (adc_rst),
.d_clk (adc_clk),
.d_data_cntrl ({ adc_sref_sync,
adc_sync,
adc_start_code,
adc_r1_mode,
adc_ddr_edgesel,
adc_pin_mode}));
up_xfer_status #(.DATA_WIDTH(3)) i_xfer_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status ({up_sync_status_s,
up_status_s,
up_status_ovf_s}),
.d_rst (adc_rst),
.d_clk (adc_clk),
.d_data_status ({ adc_sync_status,
adc_status,
adc_status_ovf}));
// adc clock monitor
up_clock_mon i_clock_mon (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_d_count (up_adc_clk_count_s),
.d_rst (adc_rst),
.d_clk (adc_clk));
endmodule
// ***************************************************************************
// ***************************************************************************
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/30 16:36:30
// Design Name:
// Module Name: uart_tx
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module UART_tx(clk,rst_n,bps_start,clk_bps,RS232_tx,tx_data,tx_int);
input clk;
input rst_n;
input clk_bps;//Öмä²ÉÑùµã
input [7:0] tx_data;//½ÓÊÕÊý¾Ý¼Ä´æÆ÷
input tx_int;//Êý¾Ý½ÓÊÕÖжÏÐźÅ
output RS232_tx;//·¢ËÍÊý¾ÝÐźÅ
output bps_start;//·¢ËÍÐźÅÖÃλ
reg tx_int0,tx_int1,tx_int2;//ÐźżĴæÆ÷,²¶×½Ï½µÑØ
wire neg_tx_int; //ϽµÑرêÖ¾
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
tx_int0 <= 1'b0;
tx_int1 <= 1'b0;
tx_int2 <= 1'b0;
end
else begin
tx_int0 <= tx_int;
tx_int1 <= tx_int0;
tx_int2 <= tx_int1;
end
end
assign neg_tx_int = ~tx_int1 & tx_int2;//²¶×½ÏÂÑØ
reg [7:0] tx_data_reg;//´ý·¢ËÍÊý¾Ý
reg bps_start_r;
reg tx_en;//·¢ËÍÐźÅʹÄÜ,¸ßÓÐЧ
reg [3:0] num;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
bps_start_r <= 1'bz;
tx_en <= 1'b0;
tx_data_reg <= 8'd0;
end
else if(neg_tx_int) begin//µ±¼ì²âµ½ÏÂÑصÄʱºò,Êý¾Ý¿ªÊ¼´«ËÍ
bps_start_r <= 1'b1;
tx_data_reg <= tx_data;
tx_en <= 1'b1;
end
else if(num==4'd11) begin
bps_start_r <= 1'b0;
tx_en <= 1'b0;
end
end
assign bps_start = bps_start_r;
reg RS232_tx_r;
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
num<=4'd0;
RS232_tx_r <= 1'b1;
end
else if(tx_en) begin
if(clk_bps) begin
num<=num+1'b1;
case(num)
4'd0: RS232_tx_r <= 1'b0;//Æðʼλ
4'd1: RS232_tx_r <= tx_data[0];//Êý¾Ýλ ¿ªÊ¼
4'd2: RS232_tx_r <= tx_data[1];
4'd3: RS232_tx_r <= tx_data[2];
4'd4: RS232_tx_r <= tx_data[3];
4'd5: RS232_tx_r <= tx_data[4];
4'd6: RS232_tx_r <= tx_data[5];
4'd7: RS232_tx_r <= tx_data[6];
4'd8: RS232_tx_r <= tx_data[7];
4'd9: RS232_tx_r <= 1'b1;//Êý¾Ý½áÊøλ,1λ
default: RS232_tx_r <= 1'b1;
endcase
end
else if(num==4'd11)
num<=4'd0;//·¢ËÍÍê³É,¸´Î»
end
end
assign RS232_tx =RS232_tx_r;
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/*
* Verilog code that really should be replaced with a generate
* statement, but it does not work with some free simulators.
* So I put it in a module so as not to make other code unreadable,
* and keep compatibility with as many simulators as possible.
*/
module hpdmc_oddr2 #(
parameter DDR_ALIGNMENT = "C0",
parameter INIT = 1'b0,
parameter SRTYPE = "ASYNC"
) (
output [1:0] Q,
input C0,
input C1,
input CE,
input [1:0] D0,
input [1:0] D1,
input R,
input S
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr0 (
.Q(Q[0]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[0]),
.D1(D1[0]),
.R(R),
.S(S)
);
ODDR2 #(
.DDR_ALIGNMENT(DDR_ALIGNMENT),
.INIT(INIT),
.SRTYPE(SRTYPE)
) oddr1 (
.Q(Q[1]),
.C0(C0),
.C1(C1),
.CE(CE),
.D0(D0[1]),
.D1(D1[1]),
.R(R),
.S(S)
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ctu_clsp_pllcnt.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//
// Cluster Name: CTU
// Unit Name: ctu_clsp_pllcnt
//
//-----------------------------------------------------------------------------
`include "ctu.h"
module ctu_clsp_pllcnt(/*AUTOARG*/
// Outputs
pll_locked_jl, pll_reset_ref_l, pll_reset_ref_dly1_l,
// Inputs
pll_raw_clk_out, io_pwron_rst_l, testmode_l, wrm_rst_ref,
wrm_rst_fc_ref, tst_rst_ref, bypclksel
);
input pll_raw_clk_out;
input io_pwron_rst_l;
input testmode_l;
input wrm_rst_ref;
input wrm_rst_fc_ref;
input tst_rst_ref;
input bypclksel;
output pll_locked_jl;
output pll_reset_ref_l;
output pll_reset_ref_dly1_l;
parameter PLL_ASSERTION_CNT = 7'h7F; // 128 cycles
parameter PLL_BYPASS_CNT = 15'h0010; // 16 cycles
parameter PLL_LCK_CNT = 15'h7b00; // 25us 32K cycles - pll assertion time
parameter WRM_RST_CNT = 15'h7d0; // 2K cycles
parameter TST_RST_CNT = 15'h100; // 256 cycles
parameter FC_DCNT = 3'b010; // 3 cycles
wire wrm_rst_ref_dly2_l;
wire wrm_rst_ref_fc_dly1;
wire wrm_rst_ref_fc_dly2_l;
wire tst_rst_ref_dly1;
wire tst_rst_ref_dly2_l;
//wire por_rst_ref_dly_l;
wire tst_rst_ld;
wire wrm_rst_ld;
wire wrm_rst_fc_ld;
wire por_rst_ld;
wire relock;
reg [14:0] pll_lck_cnt_init_nxt;
wire [14:0] pll_lck_cnt_init;
wire pll_lck_cnt_ld_nxt;
wire pll_lck_cnt_ld_1sht;
wire pwron_rst_l_d1;
wire pwron_rst_l_d2;
wire por_rst_1sht;
wire pll_locked_ref;
wire fc_dcnt_dn;
wire fc_dcnt_ld;
wire fc_dcnt_ld_nxt;
wire fc_dcnt_en;
wire [2:0] fc_dcnt_nxt;
wire [2:0] fc_dcnt;
wire pll_rst_cnt_dn;
wire [6:0] pll_rst_cnt_nxt;
wire [6:0] pll_rst_cnt;
wire pll_rst_cnt_en;
wire pll_lck_cnt_dn;
wire [14:0] pll_lck_cnt_nxt;
wire [14:0] pll_lck_cnt;
wire pll_lck_cnt_en;
//wire pll_reset_ref_pre_l;
wire pll_reset_ref_dly1_pre_l;
wire bypclksel_sync;
wire pll_reset_short_l;
wire pll_reset_short_l_nxt;
wire pll_reset_dly1_l_nxt;
wire pll_reset_dly1_l;
wire pll_reset_dly2_l;
wire pll_reset_ref_l_nxt;
wire pll_reset_ref_dly1_l_nxt;
wire [4:0] rstsm;
reg [4:0] nxt_rstsm;
//------------------------------
//
// synchronizers
//
//------------------------------
ctu_synchronizer u_bypclksel(
.presyncdata(bypclksel),
.syncdata (bypclksel_sync),
.clk(pll_raw_clk_out)
);
ctu_synchronizer u_pwron_rst_l(
.presyncdata(io_pwron_rst_l),
.syncdata (pwron_rst_l_d1),
.clk(pll_raw_clk_out)
);
// ref_clk -> jbus_clk
ctu_synch_ref_jl u_pll_locked_jl(
.presyncdata(pll_locked_ref),
.syncdata (pll_locked_jl),
.pll_raw_clk_out(pll_raw_clk_out)
);
//------------------------------
//
// register inputs
//
//------------------------------
dff_ns u_wrm_rst_dly1_l(
.din (wrm_rst_ref),
.clk (pll_raw_clk_out),
.q (wrm_rst_ref_dly1));
dff_ns u_wrm_rst_dly2_l(
.din (~wrm_rst_ref_dly1),
.clk (pll_raw_clk_out),
.q (wrm_rst_ref_dly2_l));
assign wrm_rst_ld = wrm_rst_ref_dly1 & wrm_rst_ref_dly2_l;
dff_ns u_wrm_rst_fc_dly(
.din (wrm_rst_fc_ref),
.clk (pll_raw_clk_out),
.q (wrm_rst_ref_fc_dly1));
dff_ns u_wrm_rst_fc_dly2_l(
.din (~wrm_rst_ref_fc_dly1),
.clk (pll_raw_clk_out),
.q (wrm_rst_ref_fc_dly2_l));
assign wrm_rst_fc_ld = wrm_rst_ref_fc_dly1 & wrm_rst_ref_fc_dly2_l;
dff_ns u_tst_rst_dly1(
.din (tst_rst_ref),
.clk (pll_raw_clk_out),
.q (tst_rst_ref_dly1));
dff_ns u_tst_rst_dly2_l(
.din (~tst_rst_ref_dly1),
.clk (pll_raw_clk_out),
.q (tst_rst_ref_dly2_l));
assign tst_rst_ld = tst_rst_ref_dly1 & tst_rst_ref_dly2_l;
assign por_rst_ld = ~pll_reset_ref_l ;
always @(/*AUTOSENSE*/bypclksel_sync or pll_lck_cnt_init
or por_rst_ld or tst_rst_ld or wrm_rst_fc_ld or wrm_rst_ld)
begin
case (1'b1)
(por_rst_ld & ~bypclksel_sync) | wrm_rst_fc_ld: pll_lck_cnt_init_nxt = PLL_LCK_CNT;
wrm_rst_ld : pll_lck_cnt_init_nxt = WRM_RST_CNT;
tst_rst_ld : pll_lck_cnt_init_nxt = TST_RST_CNT;
(por_rst_ld & bypclksel_sync) : pll_lck_cnt_init_nxt = PLL_BYPASS_CNT;
default : pll_lck_cnt_init_nxt = pll_lck_cnt_init;
endcase
end
dffrl_async_ns #(15) u_pll_lck_cnt_init(
.din ( pll_lck_cnt_init_nxt),
.clk (pll_raw_clk_out),
.rst_l(io_pwron_rst_l),
.q (pll_lck_cnt_init));
assign pll_lck_cnt_ld_nxt = tst_rst_ld | wrm_rst_ld | por_rst_ld | wrm_rst_ld;
dff_ns u_pll_lck_cnt_ld (
.din (pll_lck_cnt_ld_nxt),
.clk (pll_raw_clk_out),
.q (pll_lck_cnt_ld_1sht));
// tester reset and warm rset are mutually exclusive
assign relock = tst_rst_ld | wrm_rst_ld | wrm_rst_fc_ld;
//-------------------------------------------------------
// detect an edge on por to reset the PLL and lock counter
// use the reference clock to generate this edge
//-------------------------------------------------------
dff_ns u_por_rst_ff_d (
.din (pwron_rst_l_d1),
.clk (pll_raw_clk_out),
.q (pwron_rst_l_d2));
assign por_rst_1sht = pwron_rst_l_d1 & (~pwron_rst_l_d2);
//------------------------------
//
// pll rst counter:
//
//------------------------------
assign pll_rst_cnt_dn = (pll_rst_cnt == PLL_ASSERTION_CNT );
assign pll_rst_cnt_nxt = pll_reset_ref_l ? 7'h00:
pll_rst_cnt_en ? pll_rst_cnt + 7'b0000001 :
pll_rst_cnt;
dffrl_async_ns #(7) u_pll_rst_cnt (
.din ( pll_rst_cnt_nxt),
.clk (pll_raw_clk_out),
.rst_l(io_pwron_rst_l),
.q (pll_rst_cnt));
//------------------------------
//
// pll lock counter:
//
//------------------------------
assign pll_lck_cnt_dn = ~(|pll_lck_cnt[14:1]) & pll_lck_cnt[0];
assign pll_lck_cnt_nxt = pll_lck_cnt_ld_1sht ? pll_lck_cnt_init:
pll_lck_cnt_en ? pll_lck_cnt - 15'h0001 :
pll_lck_cnt;
dffrl_async_ns #(15) u_pll_lck_cnt (
.din ( pll_lck_cnt_nxt),
.clk (pll_raw_clk_out),
.rst_l(io_pwron_rst_l),
.q (pll_lck_cnt));
//------------------------------
//
// frequncy change delay counter:
//
//------------------------------
assign fc_dcnt_dn = (fc_dcnt == FC_DCNT );
assign fc_dcnt_nxt = fc_dcnt_ld ? 3'b000:
fc_dcnt_en ? fc_dcnt + 3'b001 :
fc_dcnt;
dffrl_async_ns #(3) u_fc_dcnt (
.din ( fc_dcnt_nxt),
.clk (pll_raw_clk_out),
.rst_l(io_pwron_rst_l),
.q (fc_dcnt));
//------------------------------
//
// pll state machine :
//
//------------------------------
dffrl_async_ns #(4) u_rstsm_4_1 (
.din (nxt_rstsm[4:1]),
.clk (pll_raw_clk_out),
.rst_l (io_pwron_rst_l),
.q (rstsm[4:1]));
dffsl_async_ns u_rstsm_0 (
.din (nxt_rstsm[0]),
.clk (pll_raw_clk_out),
.set_l (io_pwron_rst_l),
.q (rstsm[0]));
always @(/*AUTOSENSE*/
fc_dcnt_dn or pll_lck_cnt_dn or pll_rst_cnt_dn
or por_rst_1sht or relock or rstsm or wrm_rst_fc_ref)
begin
// CoverMeter line_off
nxt_rstsm = 5'bxxxxx;
// CoverMeter line_on
case (1'b1) //synopsys parallel_case
rstsm[`RSTSM_WAIT_POR]:
begin
nxt_rstsm = por_rst_1sht? `ST_RSTSM_RST_PLL : `ST_RSTSM_WAIT_POR;
end
rstsm[`RSTSM_RST_PLL]:
begin
nxt_rstsm = pll_rst_cnt_dn ? `ST_RSTSM_WAIT_PLL_LCK:
`ST_RSTSM_RST_PLL;
end
rstsm[`RSTSM_WAIT_PLL_LCK]:
begin
nxt_rstsm = pll_lck_cnt_dn? `ST_RSTSM_PLL_LCK:
`ST_RSTSM_WAIT_PLL_LCK;
end
rstsm[`RSTSM_PLL_LCK]:
begin
nxt_rstsm = relock ?
(wrm_rst_fc_ref? `ST_RSTSM_FREQ_CHG:`ST_RSTSM_WAIT_PLL_LCK) :
`ST_RSTSM_PLL_LCK;
end
rstsm[`RSTSM_FREQ_CHG]:
begin
nxt_rstsm = fc_dcnt_dn?
`ST_RSTSM_RST_PLL : `ST_RSTSM_FREQ_CHG;
end
// CoverMeter line_off
default:
begin
nxt_rstsm = 5'bxxxxx;
end
// CoverMeter line_on
endcase // case(rstsm)
end // begin
// -----------------------------------------------------------
//
// state outputs as function of current state
//
// -----------------------------------------------------------
assign pll_rst_cnt_en = rstsm[`RSTSM_RST_PLL];
assign pll_lck_cnt_en = rstsm[`RSTSM_WAIT_PLL_LCK];
assign fc_dcnt_en = rstsm[`RSTSM_FREQ_CHG];
assign fc_dcnt_ld_nxt = nxt_rstsm[`RSTSM_FREQ_CHG] & rstsm[`RSTSM_PLL_LCK];
dffrl_async_ns u_fc_dcnt_ld ( .din (fc_dcnt_ld_nxt ),
.rst_l (io_pwron_rst_l),
.q (fc_dcnt_ld), .clk (pll_raw_clk_out));
// pll_reset_ref_l is used to reset pll
// pll_reset_ref_dly1_l is used to reset waveform generator
// including frequency change
assign pll_reset_dly1_l_nxt = ~(nxt_rstsm[`RSTSM_RST_PLL]);
dffsl_async_ns u_pll_reset_dly1_l( .din (pll_reset_dly1_l_nxt),
.set_l (io_pwron_rst_l),
.q (pll_reset_dly1_l), .clk (pll_raw_clk_out));
dffsl_async_ns u_pll_reset_dly2_l( .din (pll_reset_dly1_l),
.set_l (io_pwron_rst_l),
.q (pll_reset_dly2_l), .clk (pll_raw_clk_out));
assign pll_reset_short_l_nxt = nxt_rstsm[`RSTSM_WAIT_POR] |
nxt_rstsm[`RSTSM_WAIT_PLL_LCK] |
nxt_rstsm[`RSTSM_PLL_LCK] |
nxt_rstsm[`RSTSM_FREQ_CHG] |
rstsm[`RSTSM_PLL_LCK] ;
dffsl_async_ns u_pll_reset_short ( .din (pll_reset_short_l_nxt),
.set_l (io_pwron_rst_l),
.q (pll_reset_short_l), .clk (pll_raw_clk_out));
//assign pll_reset_ref_l_nxt = pll_reset_dly1_l | pll_reset_dly2_l;
assign pll_reset_ref_l_nxt = pll_reset_short_l | pll_reset_dly2_l;
dffsl_async_ns u_pll_reset_ref_l( .din (pll_reset_ref_l_nxt),
.set_l (io_pwron_rst_l),
.q (pll_reset_ref_l), .clk (pll_raw_clk_out));
assign pll_reset_ref_dly1_l_nxt = pll_reset_short_l & pll_reset_dly2_l;
dffsl_async_ns u_pll_reset_ref_dly1_l( .din (pll_reset_ref_dly1_l_nxt),
.set_l (io_pwron_rst_l),
.q (pll_reset_ref_dly1_pre_l), .clk (pll_raw_clk_out));
assign pll_reset_ref_dly1_l = testmode_l ? pll_reset_ref_dly1_pre_l :1'b1;
// Used for clock generation
assign pll_locked_ref= rstsm[`RSTSM_PLL_LCK];
//synopsys translate_off
reg [8*18:1] text;
always @(rstsm[4:0])
case (1'b1)
rstsm[`RSTSM_WAIT_POR] : text = "POR";
rstsm[`RSTSM_RST_PLL ] : text = "RPLL";
rstsm[`RSTSM_WAIT_PLL_LCK] : text = "WLCK";
rstsm[`RSTSM_PLL_LCK] : text = "LCK";
rstsm[`RSTSM_FREQ_CHG ] : text = "FC";
default : text = "UNKNOWN";
endcase
//synopsys translate_on
endmodule // pll_cnt
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_cmos2_pad_dn.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
// CMOS2 PAD
*/
////////////////////////////////////////////////////////////////////////
`include "sys.h"
module bw_io_cmos2_pad_dn(oe ,data ,to_core ,pad ,por_l, vddo );
output to_core ;
input oe ;
input data ;
input por_l ;
inout pad ;
input vddo ;
supply1 vdd ;
supply0 vss ;
wire rcvr_data ;
wire por ;
wire pad_up ;
wire net58 ;
wire net59 ;
wire pad_dn_l ;
bw_io_cmos_edgelogic I2 (
.rcvr_data (rcvr_data ),
.to_core (to_core ),
.se (vss ),
.bsr_up (net58 ),
.bsr_dn_l (net59 ),
.pad_dn_l (pad_dn_l ),
.pad_up (pad_up ),
.oe (oe ),
.data (data ),
.por_l (por_l ),
.por (por ),
.bsr_data_to_core (vss ),
.bsr_mode (vss ) );
bw_io_hstl_drv I3 (
.cbu ({vss ,vss ,vss ,vss ,vdd ,vdd ,vdd ,vdd } ),
.cbd ({vss ,vss ,vss ,vss ,vdd ,vdd ,vdd ,vdd } ),
.por (por ),
.bsr_dn_l (vss ),
.bsr_up (vss ),
.pad_dn_l (pad_dn_l ),
.sel_data_n (vss ),
.pad_up (pad_up ),
.pad (pad ),
.vddo (vddo) );
bw_io_schmitt I41 (
.vddo (vddo ),
.out (rcvr_data ),
.in (pad ) );
bw_io_cmos2_term_dn I18 (
.vddo (vddo ),
.out (pad ) );
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 12/21/2016 07:28:34 PM
// Design Name:
// Module Name: router
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "global.vh"
`ifdef BLESS
module router(
clk,
n_rst,
data_in_0,
data_in_1,
data_in_2,
data_in_3,
data_in_4,
data_out_0,
data_out_1,
data_out_2,
data_out_3,
data_out_4
);
input clk, n_rst;
input [`DATA_WIDTH-1:0] data_in_0, data_in_1, data_in_2, data_in_3, data_in_4;
output [`DATA_WIDTH-1:0] data_out_0, data_out_1, data_out_2, data_out_3, data_out_4;
//buffer the input
wire [`DATA_WIDTH-1:0] r_data [0:`NUM_PORT-1];
dff_async_reset #(`DATA_WIDTH) in_pc_0(data_in_0, clk, n_rst, r_data[0]);
dff_async_reset #(`DATA_WIDTH) in_pc_1(data_in_1, clk, n_rst, r_data[1]);
dff_async_reset #(`DATA_WIDTH) in_pc_2(data_in_2, clk, n_rst, r_data[2]);
dff_async_reset #(`DATA_WIDTH) in_pc_3(data_in_3, clk, n_rst, r_data[3]);
dff_async_reset #(`DATA_WIDTH) in_pc_4(data_in_4, clk, n_rst, r_data[4]);
// seperate the field
wire [`DST_WIDTH-1:0] dst [0:`NUM_PORT-1];
wire [`NUM_FLIT_WDITH-1:0] flit_num [0:`NUM_PORT-1];
wire [`PC_INDEX_WIDTH-1:0] num_flit_in;
genvar j;
generate
for (j=0; j<`NUM_PORT; j=j+1) begin : split_field
assign dst [j] = r_data [j][`DST_POS];
assign flit_num[j] = r_data [j][`FLIT_NUM_POS];
end
assign num_flit_in = r_data[0][`VALID_POS] + r_data[1][`VALID_POS] + r_data[2][`VALID_POS] + r_data[3][`VALID_POS];
endgenerate
// Router computation
genvar k;
wire [`NUM_PORT-1:0] ppv [3:0];
generate
for (k=0; k<4; k=k+1) begin : RC
rc rc(
.dst (dst [k]),
.preferPortVector (ppv[k])
);
end
endgenerate
wire [`DATA_WIDTH-1:0] w_data_local_out [0:`NUM_PORT-1];
wire [`PC_INDEX_WIDTH-1:0] num_flit;
wire [3:0] eject;
wire [`NUM_PORT-2:0] w_ppv_local_out [0:3]; // give it to PA. Ranking is provided by PS;
//The local flit may inherit the ranking of the killed flit;
//Relax the constrain but shorten the critical path, as otherwise, PS must take place after PPV is updated in MEI.
local local_inj_ej(
.in_0 (r_data[0]),
.in_1 (r_data[1]),
.in_2 (r_data[2]),
.in_3 (r_data[3]),
.in_4 (r_data[4]),
.ppv_0 (ppv[0]),
.ppv_1 (ppv[1]),
.ppv_2 (ppv[2]),
.ppv_3 (ppv[3]),
.num_flit_i (num_flit_in),
.out_0 (w_data_local_out[0]),
.out_1 (w_data_local_out[1]),
.out_2 (w_data_local_out[2]),
.out_3 (w_data_local_out[3]),
.out_4 (data_out_4), // local eject
.ppv_out_0 (w_ppv_local_out[0]),
.ppv_out_1 (w_ppv_local_out[1]),
.ppv_out_2 (w_ppv_local_out[2]),
.ppv_out_3 (w_ppv_local_out[3]),
.num_flit_o (num_flit)
);
wire [1:0] rank_dir [0:3];
wire [`NUM_PORT-2:0] sorted_ppv [0:3];
// Permutation Sorting Network
// the assoicated flit may be merged or ejected.
// although it relaxes the priority, it did not implicate the correctness.
permutationNetwork Sort(
.time0 (w_data_local_out [0][`TIME_POS]),
.time1 (w_data_local_out [1][`TIME_POS]),
.time2 (w_data_local_out [2][`TIME_POS]),
.time3 (w_data_local_out [3][`TIME_POS]),
.ppv0 (w_ppv_local_out[0]),
.ppv1 (w_ppv_local_out[1]),
.ppv2 (w_ppv_local_out[2]),
.ppv3 (w_ppv_local_out[3]),
.rank0_dir (rank_dir[0]),
.rank1_dir (rank_dir[1]),
.rank2_dir (rank_dir[2]),
.rank3_dir (rank_dir[3]),
.rank0_ppv (sorted_ppv[0]),
.rank1_ppv (sorted_ppv[1]),
.rank2_ppv (sorted_ppv[2]),
.rank3_ppv (sorted_ppv[3])
);
// ST1 pipeline buffer
// buffer rank, ppv, data, num_flit, sorted_eject
wire [`DATA_WIDTH-1:0] r_st1_data [3:0];
wire [`NUM_PORT-2:0] r_st1_ppv [3:0];
wire [1:0] r_st1_rank [3:0];
wire [`PC_INDEX_WIDTH-1:0] r_st1_num_flit;
// Total:
genvar m;
generate
for (m=0; m<4; m=m+1) begin: ST1_BUF
dff_async_reset #(`DATA_WIDTH) st1_buf_data (w_data_local_out[m], clk, n_rst, r_st1_data[m]);
dff_async_reset #(`NUM_PORT-1) st1_buf_ppv (sorted_ppv[m], clk, n_rst, r_st1_ppv[m]);
dff_async_reset #(2) st1_buf_rank (rank_dir[m], clk, n_rst, r_st1_rank[m]);
end
endgenerate
dff_async_reset #(`PC_INDEX_WIDTH) st1_buf_numFlit (num_flit, clk, n_rst, r_st1_num_flit);
wire [`NUM_PORT-2:0] allocPV [3:0];
swAlloc swAlloc(
.numFlit_in (r_st1_num_flit),
.ppv_0 (r_st1_ppv[0]),
.ppv_1 (r_st1_ppv[1]),
.ppv_2 (r_st1_ppv[2]),
.ppv_3 (r_st1_ppv[3]),
.allocPV_0 (allocPV[0]),
.allocPV_1 (allocPV[1]),
.allocPV_2 (allocPV[2]),
.allocPV_3 (allocPV[3])
);
wire [`DATA_WIDTH_XBAR-1:0] xbar_out [0:3];
wire [`NUM_PORT-1:0] apv_on_out [0:3];
xbar xbar(
.in_0 (r_st1_data[0]),
.in_1 (r_st1_data[1]),
.in_2 (r_st1_data[2]),
.in_3 (r_st1_data[3]),
.indir_rank0 (r_st1_rank[0]),
.indir_rank1 (r_st1_rank[1]),
.indir_rank2 (r_st1_rank[2]),
.indir_rank3 (r_st1_rank[3]),
.allocPV_0 (allocPV[0]),
.allocPV_1 (allocPV[1]),
.allocPV_2 (allocPV[2]),
.allocPV_3 (allocPV[3]),
.out_0 (xbar_out[0]),
.out_1 (xbar_out[1]),
.out_2 (xbar_out[2]),
.out_3 (xbar_out[3])
);
dff_async_reset #(`DATA_WIDTH) st2_buf_data_0 (xbar_out[0], clk, n_rst, data_out_0);
dff_async_reset #(`DATA_WIDTH) st2_buf_data_1 (xbar_out[1], clk, n_rst, data_out_1);
dff_async_reset #(`DATA_WIDTH) st2_buf_data_2 (xbar_out[2], clk, n_rst, data_out_2);
dff_async_reset #(`DATA_WIDTH) st2_buf_data_3 (xbar_out[3], clk, n_rst, data_out_3);
endmodule
`endif // BLESS
`ifdef CARPOOL
module router(
clk,
n_rst,
data_in_0,
data_in_1,
data_in_2,
data_in_3,
data_in_4,
data_out_0,
data_out_1,
data_out_2,
data_out_3,
data_out_4
);
input clk, n_rst;
input [`DATA_WIDTH-1:0] data_in_0, data_in_1, data_in_2, data_in_3, data_in_4;
output [`DATA_WIDTH-1:0] data_out_0, data_out_1, data_out_2, data_out_3, data_out_4;
//buffer the input
wire [`DATA_WIDTH-1:0] r_data [0:`NUM_PORT-1];
dff_async_reset #(`DATA_WIDTH) in_pc_0(data_in_0, clk, n_rst, r_data[0]);
dff_async_reset #(`DATA_WIDTH) in_pc_1(data_in_1, clk, n_rst, r_data[1]);
dff_async_reset #(`DATA_WIDTH) in_pc_2(data_in_2, clk, n_rst, r_data[2]);
dff_async_reset #(`DATA_WIDTH) in_pc_3(data_in_3, clk, n_rst, r_data[3]);
dff_async_reset #(`DATA_WIDTH) in_pc_4(data_in_4, clk, n_rst, r_data[4]);
// seperate the field
wire [`SRC_LIST_WIDTH-1:0] dst_src_list [0:`NUM_PORT-1];
wire [`DST_WIDTH-1:0] dst [0:`NUM_PORT-1];
wire mc [0:`NUM_PORT-1];
wire hs [0:`NUM_PORT-1];
wire [`NUM_FLIT_WDITH-1:0] flit_num [0:`NUM_PORT-1];
wire [`PC_INDEX_WIDTH-1:0] num_flit_in;
genvar j;
generate
for (j=0; j<`NUM_PORT; j=j+1) begin : split_field
assign dst_src_list [j] = r_data [j][`SRC_LIST_POS];
assign dst [j] = r_data [j][`DST_POS];
assign mc [j] = r_data [j][`MC_POS];
assign hs [j] = r_data [j][`HS_POS];
assign flit_num[j] = r_data [j][`FLIT_NUM_POS];
end
assign num_flit_in = r_data[0][`VALID_POS] + r_data[1][`VALID_POS] + r_data[2][`VALID_POS] + r_data[3][`VALID_POS];
endgenerate
wire [`NUM_PORT-1:0] kill;
wire [`SRC_LIST_WIDTH-1:0] srcList_new [0:4];
merge merge(
.hs_0 (hs[0]),
.srcList_0 (dst_src_list[0]),
.addr_0 (r_data [0][`MEM_ADDR_POS]), //could be flowID
.dst_0 (dst[0]),
.flitID_0 (flit_num[0]),
.hs_1 (hs[1]),
.srcList_1 (dst_src_list[1]),
.addr_1 (r_data [1][`MEM_ADDR_POS]), //could be flowID
.dst_1 (dst[1]),
.flitID_1 (flit_num[1]),
.hs_2 (hs[2]),
.srcList_2 (dst_src_list[2]),
.addr_2 (r_data[2][`MEM_ADDR_POS]), //could be flowID
.dst_2 (dst[2]),
.flitID_2 (flit_num[2]),
.hs_3 (hs[3]),
.srcList_3 (dst_src_list[3]),
.addr_3 (r_data[3][`MEM_ADDR_POS]), //could be flowID
.dst_3 (dst[3]),
.flitID_3 (flit_num[3]),
.hs_4 (hs[4]),
.srcList_4 (dst_src_list[4]),
.addr_4 (r_data[4][`MEM_ADDR_POS]), //could be flowID
.dst_4 (dst[4]),
.flitID_4 (flit_num[4]),
.kill (kill),
.srcList_new_0 (srcList_new[0]),
.srcList_new_1 (srcList_new[1]),
.srcList_new_2 (srcList_new[2]),
.srcList_new_3 (srcList_new[3]),
.srcList_new_4 (srcList_new[4])
);
// Router computation
genvar k;
wire [`NUM_PORT-1:0] ppv [3:0];
generate
for (k=0; k<4; k=k+1) begin : RC
rc rc(
.dst (dst [k]),
.dstList (dst_src_list [k]),
.mc (mc [k]),
.preferPortVector (ppv[k])
);
end
endgenerate
wire [`DATA_WIDTH-1:0] w_data_local_out [0:`NUM_PORT-1];
wire [`PC_INDEX_WIDTH-1:0] num_flit;
wire [3:0] eject;
wire [`NUM_PORT-2:0] w_ppv_local_out [0:3]; // give it to PA. Ranking is provided by PS;
//The local flit may inherit the ranking of the killed flit;
//Relax the constrain but shorten the critical path, as otherwise, PS must take place after PPV is updated in MEI.
local local_inj_ej(
.in_0 ({r_data[0][`DATA_WIDTH-1:128], srcList_new[0], r_data[0][63:0]}),
.in_1 ({r_data[1][`DATA_WIDTH-1:128], srcList_new[1], r_data[1][63:0]}),
.in_2 ({r_data[2][`DATA_WIDTH-1:128], srcList_new[2], r_data[2][63:0]}),
.in_3 ({r_data[3][`DATA_WIDTH-1:128], srcList_new[3], r_data[3][63:0]}),
.in_4 ({r_data[4][`DATA_WIDTH-1:128], srcList_new[4], r_data[4][63:0]}),
.ppv_0 (ppv[0]),
.ppv_1 (ppv[1]),
.ppv_2 (ppv[2]),
.ppv_3 (ppv[3]),
.merge (kill),
.num_flit_i (num_flit_in),
.out_0 (w_data_local_out[0]),
.out_1 (w_data_local_out[1]),
.out_2 (w_data_local_out[2]),
.out_3 (w_data_local_out[3]),
.out_4 (data_out_4), // local eject
.ppv_out_0 (w_ppv_local_out[0]),
.ppv_out_1 (w_ppv_local_out[1]),
.ppv_out_2 (w_ppv_local_out[2]),
.ppv_out_3 (w_ppv_local_out[3]),
.num_flit_o (num_flit),
.eject (eject)
);
wire [1:0] rank_dir [0:3];
wire [`NUM_PORT-2:0] sorted_ppv [0:3];
wire [`NUM_PORT-2:0] sorted_eject, sorted_mc;
// Permutation Sorting Network
// the assoicated flit may be merged or ejected.
// although it relaxes the priority, it did not implicate the correctness.
permutationNetwork Sort(
.time0 (w_data_local_out [0][`TIME_POS]),
.time1 (w_data_local_out [1][`TIME_POS]),
.time2 (w_data_local_out [2][`TIME_POS]),
.time3 (w_data_local_out [3][`TIME_POS]),
.ppv0 (w_ppv_local_out[0]),
.ppv1 (w_ppv_local_out[1]),
.ppv2 (w_ppv_local_out[2]),
.ppv3 (w_ppv_local_out[3]),
.eject (eject),
.v_mc ({w_data_local_out [3][`MC_POS], w_data_local_out [2][`MC_POS], w_data_local_out [1][`MC_POS], w_data_local_out [0][`MC_POS]}),
.rank0_dir (rank_dir[0]),
.rank1_dir (rank_dir[1]),
.rank2_dir (rank_dir[2]),
.rank3_dir (rank_dir[3]),
.rank0_ppv (sorted_ppv[0]),
.rank1_ppv (sorted_ppv[1]),
.rank2_ppv (sorted_ppv[2]),
.rank3_ppv (sorted_ppv[3]),
.sorted_eject(sorted_eject),
.sorted_mc (sorted_mc)
);
// ST1 pipeline buffer
// buffer rank, ppv, data, num_flit, sorted_eject
wire [`DATA_WIDTH-1:0] r_st1_data [3:0];
wire [`NUM_PORT-2:0] r_st1_ppv [3:0];
wire [1:0] r_st1_rank [3:0];
wire [`PC_INDEX_WIDTH-1:0] r_st1_num_flit;
wire [`NUM_PORT-2:0] r_st1_sorted_eject, r_st1_sorted_mc;
// Total:
genvar m;
generate
for (m=0; m<4; m=m+1) begin: ST1_BUF
dff_async_reset #(`DATA_WIDTH) st1_buf_data (w_data_local_out[m], clk, n_rst, r_st1_data[m]);
dff_async_reset #(`NUM_PORT-1) st1_buf_ppv (sorted_ppv[m], clk, n_rst, r_st1_ppv[m]);
dff_async_reset #(2) st1_buf_rank (rank_dir[m], clk, n_rst, r_st1_rank[m]);
end
endgenerate
dff_async_reset #(`PC_INDEX_WIDTH) st1_buf_numFlit (num_flit, clk, n_rst, r_st1_num_flit);
dff_async_reset #(`NUM_PORT-1) st1_buf_eject (sorted_eject, clk, n_rst, r_st1_sorted_eject);
dff_async_reset #(`NUM_PORT-1) st1_buf_mc (sorted_mc, clk, n_rst, r_st1_sorted_mc);
wire [`NUM_PORT-2:0] allocPV [3:0];
swAlloc swAlloc(
.mc_0 (r_st1_sorted_mc[0]),
.mc_1 (r_st1_sorted_mc[1]),
.mc_2 (r_st1_sorted_mc[2]),
.mc_3 (r_st1_sorted_mc[3]),
.numFlit_in (r_st1_num_flit),
.ppv_0 (r_st1_ppv[0]),
.ppv_1 (r_st1_ppv[1]),
.ppv_2 (r_st1_ppv[2]),
.ppv_3 (r_st1_ppv[3]),
.allocPV_0 (allocPV[0]),
.allocPV_1 (allocPV[1]),
.allocPV_2 (allocPV[2]),
.allocPV_3 (allocPV[3])
);
wire [`DATA_WIDTH_XBAR-1:0] xbar_out [0:3];
wire [`NUM_PORT-1:0] apv_on_out [0:3];
xbar xbar(
.in_0 (r_st1_data[0]),
.in_1 (r_st1_data[1]),
.in_2 (r_st1_data[2]),
.in_3 (r_st1_data[3]),
.indir_rank0 (r_st1_rank[0]),
.indir_rank1 (r_st1_rank[1]),
.indir_rank2 (r_st1_rank[2]),
.indir_rank3 (r_st1_rank[3]),
.allocPV_0 ({r_st1_sorted_eject[0],allocPV[0]}),
.allocPV_1 ({r_st1_sorted_eject[1],allocPV[1]}),
.allocPV_2 ({r_st1_sorted_eject[2],allocPV[2]}),
.allocPV_3 ({r_st1_sorted_eject[3],allocPV[3]}),
.out_0 (xbar_out[0]),
.out_1 (xbar_out[1]),
.out_2 (xbar_out[2]),
.out_3 (xbar_out[3]),
.apv_on_out0 (apv_on_out[0]),
.apv_on_out1 (apv_on_out[1]),
.apv_on_out2 (apv_on_out[2]),
.apv_on_out3 (apv_on_out[3])
);
genvar n;
wire [`DST_LIST_WIDTH-1:0] updated_dst_list [0:3];
wire [`DATA_WIDTH-1:0] data_out [0:3];
generate
for (n=0; n<4; n=n+1) begin: dst_mgmt
dstMgmt # (n) dstMgmt(
.allocPV ({apv_on_out[n]}),
.dstList_in (xbar_out[n][`DST_LIST_POS]),
.dstList_out (updated_dst_list[n])
);
assign data_out [n] = xbar_out[n][`MC_POS] ?
{xbar_out[n][`DATA_WIDTH-1:`DST_LIST_END+1], updated_dst_list[n], xbar_out[n][`LO_PAYLOAD_POS]} :
xbar_out[n];
end
endgenerate
dff_async_reset #(`DATA_WIDTH) st2_buf_data_0 (data_out[0], clk, n_rst, data_out_0);
dff_async_reset #(`DATA_WIDTH) st2_buf_data_1 (data_out[1], clk, n_rst, data_out_1);
dff_async_reset #(`DATA_WIDTH) st2_buf_data_2 (data_out[2], clk, n_rst, data_out_2);
dff_async_reset #(`DATA_WIDTH) st2_buf_data_3 (data_out[3], clk, n_rst, data_out_3);
endmodule
`endif // end CARPOOL
`ifdef CARPOOL_LK_AHEAD_RC_PS
module router(
clk,
n_rst,
data_in_0,
data_in_1,
data_in_2,
data_in_3,
data_in_4,
data_out_0,
data_out_1,
data_out_2,
data_out_3,
data_out_4
);
input clk, n_rst;
// Assume data_in_* will maintain unchanged for 1 cycle.
input [`DATA_WIDTH-1:0] data_in_0, data_in_1, data_in_2, data_in_3, data_in_4;
output [`DATA_WIDTH-1:0] data_out_0, data_out_1, data_out_2, data_out_3, data_out_4;
//buffer the input, except time
reg [`DATA_WIDTH-1:0] r_data [0:`NUM_PORT-1];
integer i;
always @ (posedge clk) begin
if (~n_rst) begin
for (i=0; i<`NUM_PORT; i=i+1)
r_data [i] <= 'h0;
end
else begin
r_data [0] <= data_in_0;
r_data [1] <= data_in_1;
r_data [2] <= data_in_2;
r_data [3] <= data_in_3;
r_data [4] <= data_in_4;
end
end
// seperate the field
wire [`SRC_LIST_WIDTH-1:0] dst_src_list [0:`NUM_PORT-1];
wire [`DST_WIDTH-1:0] dst [0:`NUM_PORT-1];
wire mc [0:`NUM_PORT-1];
wire hs [0:`NUM_PORT-1];
wire [`NUM_PORT-1:0] ppv [0:`NUM_PORT-1];
wire [`TIME_WIDTH-1:0] ad_time [0 : `NUM_PORT-1];
wire [`NUM_FLIT_WDITH-1:0] flit_num [0:`NUM_PORT-1];
wire [`PC_INDEX_WIDTH-1:0] num_flit_in;
genvar j;
generate
for (j=0; j<`NUM_PORT; j=j+1) begin : split_field
assign dst_src_list [j] = r_data [j][`SRC_LIST_POS];
assign dst [j] = r_data [j][`DST_POS];
assign mc [j] = r_data [j][`MC_POS];
assign hs [j] = r_data [j][`HS_POS];
assign ppv [j] = r_data [j][`PPV_POS];
assign flit_num[j] = r_data [j][`FLIT_NUM_POS];
end
// time is an advanced signal, skip the first buf
assign ad_time [0] = data_in_0[`TIME_POS];
assign ad_time [1] = data_in_1[`TIME_POS];
assign ad_time [2] = data_in_2[`TIME_POS];
assign ad_time [3] = data_in_3[`TIME_POS];
assign ad_time [4] = data_in_4[`TIME_POS];
assign num_flit_in = r_data[0][`VALID_POS] + r_data[1][`VALID_POS] + r_data[2][`VALID_POS] + r_data[3][`VALID_POS];
endgenerate
wire [`NUM_PORT-1:0] kill;
wire [`SRC_LIST_WIDTH-1:0] srcList_new [0:4];
merge merge(
.hs_0 (hs[0]),
.srcList_0 (dst_src_list[0]),
.addr_0 (r_data [0][`MEM_ADDR_POS]), //could be flowID
.dst_0 (dst[0]),
.flitID_0 (flit_num[0]),
.hs_1 (hs[1]),
.srcList_1 (dst_src_list[1]),
.addr_1 (r_data [1][`MEM_ADDR_POS]), //could be flowID
.dst_1 (dst[1]),
.flitID_1 (flit_num[1]),
.hs_2 (hs[2]),
.srcList_2 (dst_src_list[2]),
.addr_2 (r_data[2][`MEM_ADDR_POS]), //could be flowID
.dst_2 (dst[2]),
.flitID_2 (flit_num[2]),
.hs_3 (hs[3]),
.srcList_3 (dst_src_list[3]),
.addr_3 (r_data[3][`MEM_ADDR_POS]), //could be flowID
.dst_3 (dst[3]),
.flitID_3 (flit_num[3]),
.hs_4 (hs[4]),
.srcList_4 (dst_src_list[4]),
.addr_4 (r_data[4][`MEM_ADDR_POS]), //could be flowID
.dst_4 (dst[4]),
.flitID_4 (flit_num[4]),
.kill (kill),
.srcList_new_0 (srcList_new[0]),
.srcList_new_1 (srcList_new[1]),
.srcList_new_2 (srcList_new[2]),
.srcList_new_3 (srcList_new[3]),
.srcList_new_4 (srcList_new[4])
);
wire [`DATA_WIDTH-1:0] w_data_local_out [0:`NUM_PORT-1];
wire [`PC_INDEX_WIDTH-1:0] num_flit;
local local_inj_ej(
.in_0 ({r_data[0][`DATA_WIDTH-1:128], srcList_new[0], r_data[0][63:0]}),
.in_1 ({r_data[1][`DATA_WIDTH-1:128], srcList_new[1], r_data[1][63:0]}),
.in_2 ({r_data[2][`DATA_WIDTH-1:128], srcList_new[2], r_data[2][63:0]}),
.in_3 ({r_data[3][`DATA_WIDTH-1:128], srcList_new[3], r_data[3][63:0]}),
.in_4 ({r_data[4][`DATA_WIDTH-1:128], srcList_new[4], r_data[4][63:0]}),
.ppv_0 (ppv[0]),
.ppv_1 (ppv[1]),
.ppv_2 (ppv[2]),
.ppv_3 (ppv[3]),
.merge (kill),
.num_flit_i (num_flit_in),
.out_0 (w_data_local_out[0]),
.out_1 (w_data_local_out[1]),
.out_2 (w_data_local_out[2]),
.out_3 (w_data_local_out[3]),
.out_4 (data_out_4), // local eject
.num_flit_o (num_flit)
);
wire [1:0] rank_dir [0:3];
// Permutation Sorting Network
// the assoicated flit may be merged or ejected.
// although it relaxes the priority, it did not implicate the correctness.
permutationNetwork Sort(
.time0 (ad_time [0]),
.time1 (ad_time [1]) ,
.time2 (ad_time [2]),
.time3 (ad_time [3]),
.dout0 (rank_dir[0]),
.dout1 (rank_dir[1]),
.dout2 (rank_dir[2]),
.dout3 (rank_dir[3])
);
wire [`NUM_PORT-2:0] allocPV [3:0];
wire [`NUM_PORT-2:0] unallocPV [3:0];
swAlloc swAlloc(
.mc_0 (w_data_local_out[0][`MC_POS]),
.mc_1 (w_data_local_out[1][`MC_POS]),
.mc_2 (w_data_local_out[2][`MC_POS]),
.mc_3 (w_data_local_out[3][`MC_POS]),
.numFlit_in (num_flit),
.ppv_0 (w_data_local_out[0][`NL_PPV_POS]),
.ppv_1 (w_data_local_out[1][`NL_PPV_POS]),
.ppv_2 (w_data_local_out[2][`NL_PPV_POS]),
.ppv_3 (w_data_local_out[3][`NL_PPV_POS]),
.allocPV_0 (allocPV[0][3:0]),
.allocPV_1 (allocPV[1][3:0]),
.allocPV_2 (allocPV[2][3:0]),
.allocPV_3 (allocPV[3][3:0])
);
genvar k;
wire [`NUM_PORT * 4 -1:0] nppv [3:0];
// precompute the ppv of next node
generate
for (k=0; k<4; k=k+1) begin : RC
nextRC precomp_ppv(
.dst (w_data_local_out[k][`DST_POS]),
.dstList (w_data_local_out[k][`DST_LIST_POS]),
.mc (w_data_local_out[k][`MC_POS]),
.indir (k),
.nextPPV (nppv[k])
);
end
endgenerate
// store in the stage 1 pipeline buffer
// including allocPPV, unallocPPV, nppv, and flit itself
reg [`DATA_WIDTH-1:0] r_data_st1 [0:3];
reg [`NUM_PORT*4-1:0] r_nppv_st1 [0:3];
reg [1:0] r_rank_dir [0:3];
integer ii;
always @ (posedge clk)
for (ii=0; ii<4; ii=ii+1) begin
r_data_st1[ii] <= {w_data_local_out[ii][`DATA_WIDTH-1:`PPV_END], allocPV[ii][3:0], w_data_local_out[ii][`PPV_START-1:0]}; // Internally, we use ppv filed as allocatedPPV.
r_nppv_st1[ii] <= nppv[ii];
r_rank_dir [ii] <= rank_dir[ii];
end
// stage 2
wire [`DATA_WIDTH_XBAR-1:0] xbar_out [0:3];
xbar xbar(
.in_0 ({r_nppv_st1[0], r_data_st1[0]}),
.in_1 ({r_nppv_st1[1], r_data_st1[1]}),
.in_2 ({r_nppv_st1[2], r_data_st1[2]}),
.in_3 ({r_nppv_st1[3], r_data_st1[3]}),
.out_0 (xbar_out[0]),
.out_1 (xbar_out[1]),
.out_2 (xbar_out[2]),
.out_3 (xbar_out[3]),
.indir_rank0 (r_rank_dir[0]),
.indir_rank1 (r_rank_dir[1]),
.indir_rank2 (r_rank_dir[2]),
.indir_rank3 (r_rank_dir[3])
);
genvar m;
wire [`NUM_PORT-1:0] selected_nppv [0:3];
wire [`DST_LIST_WIDTH-1:0] updated_dst_list [0:3];
wire [`DATA_WIDTH-1:0] data_out [0:3];
generate
// select ppv
for (m=0; m<4; m=m+1) begin: update_field
selNextPPV selPPV(
.pre_nppv (xbar_out[m][`DATA_WIDTH_XBAR-1: `DATA_WIDTH_XBAR-20]),
.outdir (m),
.nppv (selected_nppv [m])
);
dstMgmt # (m) dstMgmt(
.allocPV (xbar_out[m][`PPV_POS]),
.dstList_in (xbar_out[m][`DST_LIST_POS]),
.dstList_out (updated_dst_list[m])
);
assign data_out [m] = xbar_out[m][`MC_POS] ?
{xbar_out[m][`DATA_WIDTH-1:`PPV_END+1], selected_nppv[m], xbar_out[m][`PPV_START-1:128], updated_dst_list[m], xbar_out[m][`LO_PAYLOAD_POS]} :
{xbar_out[m][`DATA_WIDTH-1:`PPV_END+1], selected_nppv[m], xbar_out[m][`PPV_START-1:0]};
end
endgenerate
assign data_out_0 = data_out [0];
assign data_out_1 = data_out [1];
assign data_out_2 = data_out [2];
assign data_out_3 = data_out [3];
endmodule
`endif // CARPOOL_LK_AHEAD_RC_PS
|
// -----------------------------------------------------------------------------
// -- --
// -- (C) 2016-2022 Revanth Kamaraj (krevanth) --
// -- --
// -- --------------------------------------------------------------------------
// -- --
// -- This program is free software; you can redistribute it and/or --
// -- modify it under the terms of the GNU General Public License --
// -- as published by the Free Software Foundation; either version 2 --
// -- of the License, or (at your option) any later version. --
// -- --
// -- This program is distributed in the hope that it will be useful, --
// -- but WITHOUT ANY WARRANTY; without even the implied warranty of --
// -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
// -- GNU General Public License for more details. --
// -- --
// -- You should have received a copy of the GNU General Public License --
// -- along with this program; if not, write to the Free Software --
// -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA --
// -- 02110-1301, USA. --
// -- --
// -----------------------------------------------------------------------------
`default_nettype none
module zap_fifo #(parameter WDT = 32, DEPTH = 8) (
input wire i_clk,
input wire i_reset,
input wire i_write_inhibit,
input wire i_clear_from_writeback,
input wire i_data_stall,
input wire i_clear_from_alu,
input wire i_stall_from_shifter,
input wire i_stall_from_issue,
input wire i_stall_from_decode,
input wire i_clear_from_decode,
input wire [WDT-1:0] i_instr, // Instruction + other bits.
input wire i_valid, // Above is valid. Write enable basically.
output reg [WDT-1:0] o_instr, // Instruction output.
output reg o_valid, // Output valid.
output wire o_wb_stb,
output wire o_wb_cyc // Wishbone request.
);
reg clear, rd_en;
wire [WDT-1:0] instr;
wire valid;
assign o_wb_cyc = o_wb_stb;
always @*
begin
if ( i_clear_from_writeback ) clear = 1'd1;
else if ( i_data_stall ) clear = 1'd0;
else if ( i_clear_from_alu ) clear = 1'd1;
else if ( i_stall_from_shifter ) clear = 1'd0;
else if ( i_stall_from_issue ) clear = 1'd0;
else if ( i_stall_from_decode ) clear = 1'd0;
else if ( i_clear_from_decode ) clear = 1'd1;
else clear = 1'd0;
end
always @*
begin
if ( i_clear_from_writeback) rd_en = 1'd0;
else if ( i_data_stall ) rd_en = 1'd0;
else if ( i_clear_from_alu ) rd_en = 1'd0;
else if ( i_stall_from_shifter ) rd_en = 1'd0;
else if ( i_stall_from_issue ) rd_en = 1'd0;
else if ( i_stall_from_decode ) rd_en = 1'd0;
else if ( i_clear_from_decode ) rd_en = 1'd0;
else rd_en = 1'd1;
end
zap_sync_fifo #(.WIDTH(WDT), .DEPTH(DEPTH), .FWFT(1)) USF (
.i_clk (i_clk),
.i_reset (i_reset || clear),
.i_ack ( rd_en ),
.i_wr_en ( i_valid && !i_write_inhibit ),
.i_data (i_instr),
.o_data (instr),
.o_empty_n (valid),
.o_full_n (o_wb_stb),
.o_full_n_nxt (),
.o_empty (),
.o_data_nxt (),
.o_full ()
);
// Pipeline register.
always @ (posedge i_clk)
begin
if ( i_reset || clear )
begin
o_valid <= 1'd0;
end
else if ( rd_en )
begin
o_valid <= valid;
o_instr <= instr;
end
end
endmodule
`default_nettype wire
|
module s510 (
cnt509,
pcnt12,
cnt283,
cnt44,
cnt13,
pcnt241,
blif_clk_net,
pcnt6,
cnt261,
john,
pcnt17,
cnt511,
cnt272,
cnt21,
cnt567,
cnt10,
cnt45,
pcnt27,
cnt284,
cnt591,
blif_reset_net,
cclr,
vsync,
cblank,
csync,
pc,
csm,
pclr);
// Start PIs
input cnt509;
input pcnt12;
input cnt283;
input cnt44;
input cnt13;
input pcnt241;
input blif_clk_net;
input pcnt6;
input cnt261;
input john;
input pcnt17;
input cnt511;
input cnt272;
input cnt21;
input cnt567;
input cnt10;
input cnt45;
input pcnt27;
input cnt284;
input cnt591;
input blif_reset_net;
// Start POs
output cclr;
output vsync;
output cblank;
output csync;
output pc;
output csm;
output pclr;
// Start wires
wire net_47;
wire net_176;
wire net_215;
wire net_137;
wire net_132;
wire net_54;
wire net_237;
wire net_105;
wire vsync;
wire net_129;
wire net_119;
wire net_98;
wire net_12;
wire net_151;
wire net_53;
wire net_93;
wire net_210;
wire net_168;
wire net_259;
wire net_269;
wire net_127;
wire pclr;
wire net_76;
wire net_101;
wire net_187;
wire net_111;
wire net_264;
wire net_90;
wire net_225;
wire net_283;
wire net_100;
wire net_85;
wire net_263;
wire net_252;
wire net_124;
wire net_240;
wire net_160;
wire net_221;
wire net_115;
wire net_4;
wire net_17;
wire net_164;
wire cnt13;
wire pcnt241;
wire net_87;
wire net_0;
wire net_35;
wire net_16;
wire net_239;
wire net_193;
wire net_157;
wire net_257;
wire net_233;
wire net_42;
wire net_120;
wire net_201;
wire net_109;
wire net_80;
wire net_65;
wire blif_reset_net;
wire net_50;
wire net_234;
wire net_96;
wire net_66;
wire net_38;
wire net_167;
wire net_207;
wire net_136;
wire net_280;
wire net_19;
wire net_126;
wire net_278;
wire net_34;
wire net_108;
wire net_270;
wire net_183;
wire net_150;
wire net_63;
wire net_274;
wire pcnt12;
wire net_30;
wire net_189;
wire net_24;
wire net_99;
wire net_186;
wire net_46;
wire net_118;
wire net_216;
wire net_146;
wire pcnt27;
wire net_122;
wire net_7;
wire net_224;
wire net_172;
wire net_52;
wire net_165;
wire pc;
wire net_13;
wire net_246;
wire net_94;
wire net_219;
wire net_18;
wire net_131;
wire net_114;
wire net_196;
wire net_29;
wire net_149;
wire net_142;
wire net_248;
wire net_31;
wire net_36;
wire net_158;
wire net_41;
wire net_198;
wire net_253;
wire net_276;
wire net_209;
wire net_3;
wire net_154;
wire john;
wire net_213;
wire net_238;
wire net_260;
wire net_28;
wire net_97;
wire net_182;
wire net_192;
wire net_60;
wire net_267;
wire net_273;
wire net_256;
wire net_58;
wire net_82;
wire net_64;
wire cnt567;
wire net_121;
wire cnt45;
wire net_73;
wire net_200;
wire net_177;
wire net_75;
wire net_86;
wire net_206;
wire net_195;
wire net_125;
wire net_107;
wire net_166;
wire net_223;
wire net_179;
wire net_235;
wire net_159;
wire net_61;
wire net_62;
wire net_6;
wire net_217;
wire net_271;
wire net_23;
wire cnt10;
wire net_117;
wire net_74;
wire net_250;
wire net_205;
wire net_135;
wire net_265;
wire net_242;
wire net_130;
wire cclr;
wire net_147;
wire net_14;
wire net_220;
wire net_26;
wire net_113;
wire blif_clk_net;
wire net_32;
wire csm;
wire net_40;
wire net_282;
wire net_69;
wire cblank;
wire cnt284;
wire net_161;
wire net_141;
wire net_83;
wire net_95;
wire net_173;
wire net_78;
wire net_27;
wire cnt44;
wire net_56;
wire net_155;
wire net_261;
wire net_191;
wire net_22;
wire net_181;
wire net_39;
wire net_245;
wire net_2;
wire net_102;
wire net_144;
wire net_227;
wire net_9;
wire net_59;
wire net_162;
wire net_230;
wire net_44;
wire net_277;
wire net_134;
wire net_199;
wire net_45;
wire net_89;
wire cnt272;
wire net_185;
wire net_272;
wire net_178;
wire net_236;
wire net_208;
wire net_212;
wire net_243;
wire cnt283;
wire net_222;
wire net_152;
wire net_116;
wire net_175;
wire net_91;
wire net_55;
wire net_106;
wire net_258;
wire net_255;
wire net_140;
wire net_266;
wire net_247;
wire pcnt17;
wire net_279;
wire net_104;
wire net_148;
wire net_72;
wire net_25;
wire net_229;
wire net_70;
wire net_251;
wire net_194;
wire net_241;
wire net_5;
wire net_244;
wire net_128;
wire net_138;
wire pcnt6;
wire net_184;
wire net_11;
wire net_123;
wire csync;
wire net_262;
wire net_170;
wire net_68;
wire net_77;
wire net_214;
wire net_249;
wire net_20;
wire net_49;
wire net_15;
wire net_275;
wire net_57;
wire net_71;
wire net_153;
wire net_156;
wire net_84;
wire net_218;
wire cnt261;
wire net_174;
wire net_231;
wire net_92;
wire net_1;
wire net_112;
wire net_103;
wire net_139;
wire net_226;
wire net_43;
wire net_228;
wire net_10;
wire net_180;
wire net_21;
wire net_169;
wire net_51;
wire net_79;
wire net_171;
wire net_143;
wire cnt509;
wire net_190;
wire net_88;
wire net_145;
wire net_281;
wire net_197;
wire net_204;
wire net_81;
wire net_232;
wire net_163;
wire net_254;
wire net_67;
wire net_37;
wire net_202;
wire net_268;
wire cnt511;
wire cnt21;
wire net_188;
wire net_110;
wire net_48;
wire net_33;
wire net_8;
wire net_211;
wire cnt591;
wire net_133;
wire net_203;
// Start cells
DFFR_X2 inst_257 ( .QN(net_238), .RN(net_235), .D(net_232), .CK(net_275) );
CLKBUF_X2 inst_290 ( .A(net_282), .Z(net_283) );
NAND2_X2 inst_145 ( .ZN(net_188), .A1(net_110), .A2(net_34) );
CLKBUF_X2 inst_272 ( .A(net_264), .Z(net_265) );
NAND2_X2 inst_103 ( .ZN(net_254), .A1(net_23), .A2(net_0) );
INV_X2 inst_248 ( .ZN(net_246), .A(net_142) );
INV_X2 inst_228 ( .A(net_79), .ZN(net_12) );
NAND2_X2 inst_125 ( .ZN(net_108), .A1(net_96), .A2(net_71) );
INV_X4 inst_207 ( .ZN(net_192), .A(net_149) );
NAND2_X2 inst_138 ( .ZN(net_160), .A1(net_159), .A2(net_157) );
NAND2_X2 inst_159 ( .ZN(net_228), .A1(net_211), .A2(net_209) );
NAND2_X2 inst_134 ( .A2(net_225), .ZN(net_146), .A1(net_127) );
INV_X2 inst_244 ( .ZN(net_125), .A(net_111) );
NAND2_X2 inst_131 ( .ZN(net_128), .A1(net_127), .A2(net_89) );
INV_X4 inst_214 ( .ZN(net_159), .A(net_115) );
INV_X4 inst_180 ( .A(net_238), .ZN(net_104) );
NAND2_X1 inst_160 ( .ZN(net_9), .A1(pcnt17), .A2(cnt284) );
NOR2_X2 inst_33 ( .ZN(net_88), .A2(net_43), .A1(net_23) );
NOR2_X2 inst_47 ( .ZN(net_135), .A2(net_81), .A1(net_18) );
NOR3_X2 inst_19 ( .ZN(net_239), .A1(net_231), .A3(net_230), .A2(net_228) );
OR2_X2 inst_8 ( .ZN(net_171), .A2(net_170), .A1(net_67) );
INV_X2 inst_232 ( .A(net_199), .ZN(net_34) );
INV_X2 inst_247 ( .ZN(net_212), .A(net_113) );
NOR2_X4 inst_27 ( .A2(net_253), .ZN(net_148), .A1(net_142) );
NAND2_X2 inst_100 ( .ZN(net_15), .A2(net_6), .A1(cnt44) );
CLKBUF_X2 inst_279 ( .A(net_271), .Z(net_272) );
INV_X1 inst_253 ( .ZN(net_235), .A(blif_reset_net) );
INV_X4 inst_211 ( .ZN(net_115), .A(net_86) );
INV_X8 inst_162 ( .ZN(net_60), .A(net_11) );
NAND2_X4 inst_93 ( .A2(net_245), .ZN(net_78), .A1(net_57) );
NAND3_X2 inst_81 ( .ZN(net_208), .A2(net_207), .A3(net_122), .A1(net_55) );
NAND2_X2 inst_139 ( .ZN(net_165), .A1(net_106), .A2(net_83) );
NAND2_X2 inst_155 ( .ZN(net_206), .A2(net_155), .A1(net_149) );
NOR2_X2 inst_59 ( .ZN(net_223), .A2(net_217), .A1(net_150) );
NAND2_X2 inst_135 ( .A1(net_207), .ZN(net_151), .A2(net_93) );
INV_X4 inst_196 ( .A(net_173), .ZN(net_49) );
NOR2_X2 inst_55 ( .ZN(net_191), .A2(net_147), .A1(net_97) );
NOR2_X2 inst_37 ( .A2(net_199), .A1(net_100), .ZN(net_61) );
INV_X2 inst_237 ( .ZN(net_63), .A(net_62) );
NAND2_X2 inst_148 ( .ZN(net_194), .A1(net_141), .A2(net_103) );
AND2_X4 inst_264 ( .A2(net_261), .ZN(net_40), .A1(net_10) );
INV_X4 inst_191 ( .ZN(net_102), .A(net_74) );
NAND3_X2 inst_84 ( .ZN(net_218), .A3(net_197), .A1(net_161), .A2(net_158) );
NOR2_X2 inst_51 ( .ZN(net_147), .A2(net_118), .A1(cnt284) );
NAND2_X2 inst_142 ( .ZN(net_177), .A2(net_154), .A1(net_140) );
NAND3_X2 inst_80 ( .A3(net_252), .A1(net_251), .ZN(net_204), .A2(net_73) );
INV_X4 inst_173 ( .ZN(net_23), .A(net_13) );
INV_X2 inst_224 ( .ZN(net_4), .A(cnt511) );
INV_X4 inst_216 ( .ZN(net_141), .A(net_140) );
NAND3_X2 inst_78 ( .ZN(net_193), .A2(net_192), .A1(net_168), .A3(net_153) );
CLKBUF_X2 inst_287 ( .A(net_273), .Z(net_280) );
NOR2_X2 inst_42 ( .ZN(net_120), .A1(net_62), .A2(net_24) );
INV_X2 inst_241 ( .A(net_105), .ZN(net_77) );
INV_X4 inst_177 ( .ZN(net_14), .A(net_13) );
INV_X2 inst_231 ( .A(net_40), .ZN(net_32) );
CLKBUF_X2 inst_270 ( .A(blif_clk_net), .Z(net_263) );
INV_X4 inst_183 ( .ZN(net_52), .A(net_24) );
NOR2_X4 inst_26 ( .ZN(net_249), .A1(net_65), .A2(net_60) );
NAND2_X2 inst_151 ( .ZN(net_197), .A2(net_128), .A1(net_33) );
NOR2_X1 inst_64 ( .ZN(net_182), .A1(net_181), .A2(net_167) );
NAND2_X2 inst_107 ( .A1(net_98), .ZN(net_64), .A2(net_40) );
NAND4_X2 inst_70 ( .ZN(net_233), .A2(net_225), .A4(net_224), .A1(net_223), .A3(net_179) );
NAND2_X2 inst_129 ( .ZN(net_124), .A2(net_123), .A1(net_96) );
NAND2_X4 inst_92 ( .A2(net_244), .ZN(net_65), .A1(net_38) );
INV_X4 inst_189 ( .A(net_57), .ZN(net_47) );
INV_X2 inst_223 ( .ZN(net_3), .A(cnt591) );
NOR4_X2 inst_11 ( .ZN(net_215), .A4(net_183), .A1(net_176), .A2(net_145), .A3(net_119) );
INV_X4 inst_188 ( .ZN(net_75), .A(net_23) );
NOR3_X2 inst_14 ( .A2(net_173), .ZN(net_132), .A1(net_131), .A3(net_98) );
NOR2_X2 inst_31 ( .A2(net_262), .ZN(net_41), .A1(net_23) );
INV_X2 inst_252 ( .ZN(net_176), .A(net_175) );
NAND2_X2 inst_158 ( .A1(net_257), .ZN(net_227), .A2(net_199) );
NAND2_X2 inst_141 ( .ZN(net_174), .A2(net_172), .A1(net_149) );
NOR2_X1 inst_62 ( .A1(net_238), .ZN(net_53), .A2(net_27) );
INV_X4 inst_200 ( .A(net_49), .ZN(net_48) );
INV_X2 inst_251 ( .ZN(net_175), .A(net_159) );
CLKBUF_X2 inst_286 ( .A(net_278), .Z(net_279) );
NOR2_X2 inst_57 ( .ZN(net_210), .A2(net_195), .A1(net_152) );
NAND2_X2 inst_102 ( .A2(net_261), .A1(net_260), .ZN(net_44) );
NOR2_X2 inst_32 ( .ZN(net_30), .A2(net_29), .A1(john) );
NAND2_X2 inst_144 ( .ZN(net_184), .A2(net_183), .A1(net_159) );
INV_X4 inst_195 ( .A(net_44), .ZN(net_35) );
NOR2_X4 inst_21 ( .A1(net_261), .A2(net_260), .ZN(net_38) );
CLKBUF_X2 inst_281 ( .A(net_272), .Z(net_274) );
NAND2_X4 inst_97 ( .ZN(net_255), .A1(net_120), .A2(net_96) );
NAND2_X2 inst_124 ( .ZN(net_256), .A1(net_104), .A2(net_63) );
NOR3_X2 inst_18 ( .ZN(net_243), .A1(net_164), .A3(net_162), .A2(net_61) );
INV_X4 inst_208 ( .ZN(net_87), .A(net_78) );
NAND3_X2 inst_88 ( .A3(net_240), .A1(net_239), .ZN(net_236), .A2(net_210) );
INV_X2 inst_220 ( .ZN(net_0), .A(cnt21) );
OR2_X2 inst_9 ( .ZN(net_179), .A1(net_178), .A2(net_170) );
NAND2_X2 inst_113 ( .A2(net_173), .A1(net_102), .ZN(net_72) );
INV_X4 inst_198 ( .ZN(net_207), .A(net_49) );
NOR2_X2 inst_50 ( .A1(net_149), .ZN(net_145), .A2(net_144) );
NAND2_X2 inst_137 ( .ZN(net_158), .A2(net_157), .A1(net_96) );
INV_X2 inst_245 ( .A(net_225), .ZN(net_103) );
NAND2_X2 inst_130 ( .A2(net_186), .ZN(net_126), .A1(net_125) );
INV_X2 inst_227 ( .ZN(net_6), .A(pcnt12) );
INV_X2 inst_226 ( .ZN(net_5), .A(pcnt17) );
DFFR_X2 inst_260 ( .QN(net_259), .D(net_236), .RN(net_235), .CK(net_273) );
INV_X4 inst_176 ( .A(net_13), .ZN(net_10) );
NOR2_X2 inst_58 ( .ZN(net_217), .A1(net_192), .A2(net_191) );
NAND2_X2 inst_147 ( .ZN(net_190), .A2(net_146), .A1(net_144) );
NAND3_X2 inst_87 ( .ZN(net_232), .A3(net_221), .A1(net_203), .A2(net_134) );
NOR2_X2 inst_61 ( .A1(net_241), .ZN(net_230), .A2(net_96) );
INV_X4 inst_203 ( .ZN(net_137), .A(net_75) );
INV_X4 inst_212 ( .ZN(net_131), .A(net_87) );
INV_X2 inst_234 ( .ZN(net_51), .A(net_50) );
OR3_X2 inst_0 ( .ZN(net_219), .A1(net_207), .A2(net_175), .A3(net_125) );
INV_X4 inst_184 ( .ZN(net_37), .A(net_26) );
INV_X2 inst_236 ( .A(net_68), .ZN(net_56) );
NOR4_X2 inst_10 ( .A3(net_199), .ZN(net_195), .A2(net_163), .A4(net_45), .A1(net_30) );
OR2_X2 inst_4 ( .ZN(net_91), .A2(net_90), .A1(net_52) );
NOR2_X1 inst_65 ( .A2(net_219), .A1(net_186), .ZN(csm) );
NOR2_X2 inst_28 ( .ZN(net_17), .A1(net_4), .A2(pcnt241) );
INV_X2 inst_242 ( .ZN(net_81), .A(net_80) );
CLKBUF_X2 inst_275 ( .A(net_267), .Z(net_268) );
NAND2_X2 inst_117 ( .ZN(net_89), .A2(net_88), .A1(net_16) );
NAND2_X4 inst_98 ( .ZN(net_251), .A1(net_249), .A2(cnt10) );
AND3_X2 inst_263 ( .ZN(net_117), .A1(net_116), .A2(net_96), .A3(net_88) );
INV_X4 inst_190 ( .ZN(net_100), .A(net_31) );
INV_X4 inst_204 ( .ZN(net_149), .A(net_75) );
INV_X4 inst_185 ( .ZN(net_25), .A(net_24) );
NOR2_X2 inst_49 ( .ZN(net_200), .A1(net_84), .A2(net_75) );
NAND2_X2 inst_154 ( .ZN(net_203), .A2(net_180), .A1(net_49) );
NOR3_X2 inst_13 ( .ZN(net_157), .A3(net_78), .A1(net_29), .A2(net_19) );
NAND3_X2 inst_75 ( .ZN(net_106), .A1(net_105), .A3(net_104), .A2(cnt509) );
INV_X4 inst_166 ( .ZN(net_253), .A(cnt45) );
NAND2_X2 inst_116 ( .ZN(net_129), .A2(net_53), .A1(net_52) );
INV_X8 inst_163 ( .A(net_261), .ZN(net_26) );
NOR2_X2 inst_54 ( .A2(net_172), .ZN(net_166), .A1(net_133) );
NAND3_X2 inst_79 ( .A1(net_246), .ZN(net_198), .A2(pcnt6), .A3(cnt284) );
NAND2_X2 inst_109 ( .ZN(net_127), .A1(net_52), .A2(net_41) );
NAND2_X2 inst_106 ( .A1(net_238), .ZN(net_39), .A2(net_38) );
INV_X2 inst_219 ( .A(net_249), .ZN(net_248) );
INV_X4 inst_201 ( .ZN(net_168), .A(net_49) );
NOR2_X2 inst_43 ( .A2(net_258), .ZN(net_95), .A1(net_64) );
DFFR_X2 inst_255 ( .QN(net_262), .RN(net_235), .D(net_222), .CK(net_283) );
NAND2_X2 inst_128 ( .ZN(net_114), .A2(net_80), .A1(cnt567) );
NAND3_X2 inst_73 ( .ZN(net_73), .A3(net_40), .A1(net_25), .A2(cnt21) );
DFFR_X2 inst_256 ( .QN(net_237), .RN(net_235), .D(net_229), .CK(net_279) );
NOR2_X4 inst_23 ( .ZN(net_70), .A1(net_44), .A2(net_43) );
NAND2_X4 inst_94 ( .ZN(net_225), .A1(net_178), .A2(net_47) );
AND3_X4 inst_262 ( .ZN(net_226), .A2(net_225), .A3(net_206), .A1(net_201) );
INV_X2 inst_243 ( .ZN(net_93), .A(net_92) );
CLKBUF_X2 inst_285 ( .A(net_277), .Z(net_278) );
NOR3_X2 inst_15 ( .ZN(net_150), .A2(net_149), .A3(net_116), .A1(net_48) );
INV_X4 inst_218 ( .ZN(net_231), .A(net_227) );
INV_X4 inst_197 ( .A(net_49), .ZN(net_42) );
INV_X2 inst_250 ( .A(net_172), .ZN(net_122) );
INV_X4 inst_179 ( .A(net_238), .ZN(net_29) );
NOR2_X4 inst_24 ( .ZN(net_46), .A1(net_37), .A2(net_11) );
OR2_X2 inst_6 ( .ZN(net_155), .A1(net_154), .A2(net_153) );
NAND2_X2 inst_114 ( .ZN(net_92), .A1(net_75), .A2(net_74) );
INV_X4 inst_194 ( .A(net_98), .ZN(net_54) );
NAND3_X2 inst_76 ( .A2(net_192), .ZN(net_134), .A1(net_133), .A3(net_111) );
NAND2_X2 inst_150 ( .A2(net_256), .A1(net_255), .ZN(net_247) );
INV_X4 inst_172 ( .A(net_79), .ZN(net_8) );
CLKBUF_X2 inst_277 ( .A(net_269), .Z(net_270) );
NAND3_X2 inst_83 ( .ZN(net_214), .A3(net_213), .A1(net_174), .A2(net_102) );
NAND2_X2 inst_121 ( .ZN(net_101), .A2(net_100), .A1(net_86) );
NAND2_X2 inst_123 ( .ZN(net_163), .A2(net_107), .A1(net_52) );
OR3_X1 inst_2 ( .A1(net_216), .A3(net_212), .A2(net_143), .ZN(cclr) );
NAND3_X2 inst_86 ( .A2(net_219), .A1(net_194), .A3(net_171), .ZN(cblank) );
NAND2_X2 inst_118 ( .ZN(net_113), .A2(net_70), .A1(net_7) );
NOR2_X4 inst_20 ( .A1(net_260), .ZN(net_98), .A2(net_21) );
NAND2_X2 inst_153 ( .ZN(net_202), .A2(net_200), .A1(net_42) );
NOR2_X2 inst_38 ( .ZN(net_154), .A1(net_74), .A2(net_36) );
NOR2_X2 inst_52 ( .A2(net_248), .ZN(net_162), .A1(net_17) );
NAND2_X4 inst_90 ( .A1(net_250), .A2(net_238), .ZN(net_43) );
AND2_X4 inst_267 ( .ZN(net_59), .A1(net_57), .A2(net_3) );
NAND2_X2 inst_140 ( .ZN(net_213), .A1(net_173), .A2(net_172) );
INV_X4 inst_209 ( .ZN(net_111), .A(net_76) );
DFFR_X2 inst_259 ( .QN(net_260), .RN(net_235), .D(net_234), .CK(net_270) );
INV_X2 inst_221 ( .ZN(net_1), .A(cnt567) );
NOR2_X2 inst_40 ( .ZN(net_123), .A2(net_39), .A1(net_23) );
INV_X4 inst_167 ( .A(net_262), .ZN(net_79) );
INV_X2 inst_246 ( .A(net_131), .ZN(net_110) );
CLKBUF_X2 inst_289 ( .A(net_281), .Z(net_282) );
NAND2_X4 inst_95 ( .A2(net_186), .ZN(net_142), .A1(net_46) );
OR3_X1 inst_1 ( .A3(net_212), .A2(net_182), .A1(net_166), .ZN(pc) );
CLKBUF_X2 inst_282 ( .A(net_274), .Z(net_275) );
NAND4_X2 inst_72 ( .A4(net_243), .A1(net_242), .ZN(net_234), .A2(net_205), .A3(net_112) );
NOR2_X2 inst_44 ( .ZN(net_97), .A2(net_96), .A1(net_76) );
CLKBUF_X2 inst_274 ( .A(net_266), .Z(net_267) );
INV_X4 inst_174 ( .ZN(net_244), .A(net_13) );
NAND2_X2 inst_115 ( .A1(net_96), .ZN(net_82), .A2(net_56) );
INV_X2 inst_235 ( .ZN(net_55), .A(net_54) );
INV_X4 inst_210 ( .A(net_86), .ZN(net_84) );
INV_X8 inst_164 ( .ZN(net_57), .A(net_26) );
OR2_X2 inst_5 ( .A2(net_127), .ZN(net_94), .A1(net_68) );
CLKBUF_X2 inst_278 ( .A(net_264), .Z(net_271) );
NAND2_X2 inst_157 ( .A2(net_208), .A1(net_94), .ZN(pclr) );
INV_X2 inst_239 ( .A(net_127), .ZN(net_69) );
NAND2_X2 inst_105 ( .ZN(net_62), .A2(net_37), .A1(net_31) );
NAND4_X2 inst_68 ( .ZN(net_222), .A4(net_193), .A2(net_169), .A1(net_160), .A3(net_156) );
INV_X4 inst_213 ( .ZN(net_172), .A(net_99) );
NOR2_X2 inst_53 ( .ZN(net_164), .A2(net_163), .A1(cnt13) );
INV_X4 inst_175 ( .ZN(net_96), .A(net_79) );
INV_X4 inst_205 ( .ZN(net_80), .A(net_64) );
INV_X1 inst_254 ( .ZN(net_107), .A(net_65) );
INV_X2 inst_225 ( .ZN(net_258), .A(cnt283) );
NAND2_X2 inst_133 ( .A2(net_249), .ZN(net_136), .A1(cnt511) );
NAND2_X2 inst_112 ( .ZN(net_116), .A1(net_68), .A2(net_44) );
NAND4_X2 inst_67 ( .ZN(net_221), .A3(net_213), .A4(net_189), .A2(net_115), .A1(net_72) );
INV_X4 inst_181 ( .ZN(net_245), .A(net_23) );
NAND2_X2 inst_127 ( .ZN(net_112), .A1(net_111), .A2(net_69) );
NOR2_X2 inst_29 ( .ZN(net_18), .A1(net_1), .A2(pcnt27) );
INV_X4 inst_186 ( .ZN(net_173), .A(net_29) );
NOR3_X2 inst_17 ( .ZN(net_205), .A2(net_138), .A3(net_135), .A1(net_132) );
NAND2_X2 inst_146 ( .ZN(net_189), .A2(net_139), .A1(net_100) );
INV_X2 inst_249 ( .ZN(net_119), .A(net_118) );
INV_X4 inst_202 ( .ZN(net_144), .A(net_102) );
INV_X4 inst_187 ( .ZN(net_27), .A(net_26) );
INV_X4 inst_206 ( .ZN(net_86), .A(net_52) );
NAND2_X2 inst_122 ( .ZN(net_170), .A1(net_102), .A2(net_87) );
NAND2_X2 inst_126 ( .ZN(net_109), .A2(net_107), .A1(net_28) );
NOR2_X4 inst_25 ( .ZN(net_105), .A2(net_60), .A1(net_50) );
INV_X2 inst_240 ( .ZN(net_71), .A(net_70) );
NAND2_X2 inst_110 ( .A1(net_260), .ZN(net_90), .A2(net_41) );
NAND3_X2 inst_74 ( .ZN(net_83), .A1(net_66), .A3(net_35), .A2(cnt45) );
CLKBUF_X2 inst_288 ( .A(net_280), .Z(net_281) );
INV_X2 inst_229 ( .A(net_260), .ZN(net_19) );
NAND2_X4 inst_99 ( .A1(net_247), .ZN(net_211), .A2(cnt44) );
NOR2_X2 inst_35 ( .ZN(net_178), .A2(net_79), .A1(net_52) );
NAND4_X2 inst_69 ( .ZN(net_229), .A4(net_214), .A2(net_202), .A3(net_190), .A1(net_184) );
NOR2_X2 inst_48 ( .A2(net_225), .ZN(net_138), .A1(net_137) );
NAND3_X2 inst_82 ( .ZN(net_257), .A1(net_198), .A2(net_136), .A3(net_114) );
NOR2_X2 inst_46 ( .ZN(net_153), .A2(net_116), .A1(net_79) );
NOR2_X2 inst_30 ( .ZN(net_20), .A2(net_12), .A1(net_2) );
NAND2_X2 inst_136 ( .ZN(net_156), .A1(net_149), .A2(net_108) );
NAND2_X2 inst_108 ( .A1(net_238), .ZN(net_66), .A2(net_22) );
INV_X2 inst_233 ( .A(net_43), .ZN(net_36) );
INV_X4 inst_165 ( .A(net_259), .ZN(net_13) );
CLKBUF_X2 inst_271 ( .A(net_263), .Z(net_264) );
CLKBUF_X2 inst_283 ( .A(net_272), .Z(net_276) );
NOR2_X4 inst_22 ( .A1(net_260), .ZN(net_31), .A2(net_13) );
NOR2_X2 inst_34 ( .ZN(net_45), .A2(net_20), .A1(cnt10) );
NOR3_X4 inst_12 ( .ZN(net_241), .A1(net_204), .A3(net_148), .A2(net_95) );
NAND4_X2 inst_71 ( .A2(net_226), .A4(net_188), .A1(net_124), .A3(net_90), .ZN(csync) );
NOR2_X2 inst_56 ( .ZN(net_240), .A2(net_187), .A1(net_117) );
NAND2_X2 inst_104 ( .A2(net_238), .ZN(net_28), .A1(cnt13) );
NOR2_X2 inst_60 ( .ZN(net_242), .A2(net_220), .A1(net_121) );
INV_X4 inst_168 ( .A(net_237), .ZN(net_11) );
INV_X4 inst_169 ( .ZN(net_250), .A(net_11) );
INV_X4 inst_215 ( .A(net_149), .ZN(net_140) );
NAND2_X1 inst_161 ( .ZN(net_139), .A2(net_99), .A1(net_74) );
NOR3_X2 inst_16 ( .ZN(net_152), .A3(net_129), .A1(net_92), .A2(cnt261) );
CLKBUF_X2 inst_276 ( .A(net_268), .Z(net_269) );
OR2_X4 inst_3 ( .A2(net_262), .ZN(net_22), .A1(net_21) );
NAND2_X2 inst_156 ( .ZN(net_209), .A2(net_165), .A1(net_137) );
INV_X4 inst_170 ( .A(net_79), .ZN(net_7) );
DFFR_X2 inst_258 ( .QN(net_261), .RN(net_235), .D(net_233), .CK(net_265) );
NOR2_X2 inst_41 ( .ZN(net_85), .A2(net_59), .A1(net_58) );
INV_X4 inst_199 ( .ZN(net_76), .A(net_47) );
NAND2_X4 inst_91 ( .A2(net_260), .ZN(net_50), .A1(net_26) );
NAND2_X2 inst_132 ( .ZN(net_130), .A1(net_129), .A2(net_113) );
NAND2_X2 inst_143 ( .ZN(net_180), .A2(net_101), .A1(net_32) );
NOR2_X2 inst_36 ( .ZN(net_58), .A1(net_57), .A2(cnt272) );
NAND2_X2 inst_152 ( .ZN(net_201), .A1(net_200), .A2(net_199) );
AND2_X4 inst_265 ( .A2(net_260), .ZN(net_186), .A1(net_14) );
NAND2_X4 inst_96 ( .A2(net_254), .ZN(net_252), .A1(net_105) );
NOR2_X2 inst_45 ( .A2(net_199), .ZN(net_183), .A1(net_111) );
NAND2_X2 inst_101 ( .ZN(net_16), .A2(net_5), .A1(cnt284) );
AND2_X2 inst_269 ( .ZN(net_161), .A2(net_109), .A1(net_77) );
INV_X2 inst_238 ( .ZN(net_67), .A(net_66) );
AND4_X2 inst_261 ( .ZN(net_187), .A3(net_186), .A2(net_178), .A1(net_173), .A4(net_85) );
INV_X4 inst_178 ( .A(net_60), .ZN(net_24) );
NAND3_X1 inst_89 ( .A1(net_215), .A3(net_126), .A2(net_82), .ZN(vsync) );
NAND2_X2 inst_111 ( .A1(net_173), .ZN(net_133), .A2(net_54) );
NAND4_X2 inst_66 ( .ZN(net_216), .A3(net_181), .A2(net_177), .A1(net_151), .A4(net_131) );
AND2_X2 inst_268 ( .ZN(net_121), .A2(net_120), .A1(net_15) );
OR2_X2 inst_7 ( .ZN(net_169), .A1(net_168), .A2(net_167) );
NOR2_X1 inst_63 ( .A1(net_207), .ZN(net_143), .A2(net_142) );
INV_X4 inst_182 ( .ZN(net_74), .A(net_19) );
CLKBUF_X2 inst_273 ( .A(net_265), .Z(net_266) );
NAND2_X2 inst_120 ( .ZN(net_167), .A1(net_111), .A2(net_98) );
NAND2_X2 inst_119 ( .A1(net_238), .ZN(net_118), .A2(net_51) );
CLKBUF_X2 inst_284 ( .A(net_276), .Z(net_277) );
INV_X2 inst_222 ( .ZN(net_2), .A(john) );
INV_X4 inst_192 ( .A(net_74), .ZN(net_33) );
CLKBUF_X2 inst_280 ( .A(net_272), .Z(net_273) );
NAND3_X2 inst_85 ( .ZN(net_220), .A3(net_196), .A2(net_185), .A1(net_91) );
AND2_X4 inst_266 ( .A2(net_238), .ZN(net_199), .A1(net_8) );
NAND2_X2 inst_149 ( .ZN(net_196), .A2(net_130), .A1(net_23) );
INV_X4 inst_193 ( .ZN(net_181), .A(net_41) );
NOR2_X2 inst_39 ( .ZN(net_99), .A1(net_79), .A2(net_78) );
INV_X2 inst_230 ( .ZN(net_68), .A(net_38) );
INV_X4 inst_217 ( .ZN(net_224), .A(net_218) );
NAND3_X2 inst_77 ( .ZN(net_185), .A3(net_123), .A2(net_52), .A1(net_9) );
INV_X4 inst_171 ( .ZN(net_21), .A(net_11) );
endmodule
|
module trigTable_tb ();
///////////////////////////////////////////////////////////////////////////
// PARAMETER AND SIGNAL DECLARATIONS
///////////////////////////////////////////////////////////////////////////
wire signed [17:0] sin;
wire signed [17:0] cos;
reg signed [17:0] expectedSin;
reg signed [17:0] expectedCos;
reg [11:0] angle;
reg [11:0] angleD1;
reg clk;
integer i;
///////////////////////////////////////////////////////////////////////////
// MAIN CODE
///////////////////////////////////////////////////////////////////////////
always #1 clk = ~clk;
initial begin
clk = 1'b0;
angle = 0;
angleD1 = 0;
// Let sine table start outputting valid data
@(posedge clk);
@(posedge clk);
// Run sine table over several frequencies
for (i=1; i<2**11; i=i<<1) begin // double frequency each time
@(posedge clk) angle = angle + i;
while (angle != 0) begin
@(posedge clk) angle = angle + i;
if ((sin - expectedSin > 1) || (sin - expectedSin < -1)) begin
$display("FAILED SIN @ angle=%d", angleD1);
end
if ((cos - expectedCos > 1) || (cos - expectedCos < -1)) begin
$display("FAILED COS @ angle=%d", angleD1);
end
end
end
$display("PASSED");
$finish(2);
end
always @(posedge clk) begin
angleD1 <= angle;
expectedSin <= $rtoi($floor($sin(($itor(angleD1)+0.5)*2*3.14159/2**12)*(2**17-1)+0.5));
expectedCos <= $rtoi($floor($cos(($itor(angleD1)+0.5)*2*3.14159/2**12)*(2**17-1)+0.5));
end
trigTable #(
.ANGLE_WIDTH(12),
.OUT_WIDTH(18)
) uut (
.clk(clk), ///< System Clock
.angle(angle), ///< [ANGLE_WIDTH-1:0] Angle to take sine of
.sin(sin), ///< [OUT_WIDTH-1:0] Sine of angle
.cos(cos) ///< [OUT_WIDTH-1:0] Cosine of angle
);
endmodule
|
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court 408-826-6000 (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email: [email protected]
// =============================================================================/
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_monitor.v
// Title : Debug monitor memory Wishbone interface
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.3
// : Removed port mismatch in instantiation of module
// : lm32_monitor_ram.
// =============================================================================
`include "system_conf.v"
`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_monitor (
// ----- Inputs -------
clk_i,
rst_i,
MON_ADR_I,
MON_CYC_I,
MON_DAT_I,
MON_SEL_I,
MON_STB_I,
MON_WE_I,
MON_LOCK_I,
MON_CTI_I,
MON_BTE_I,
// ----- Outputs -------
MON_ACK_O,
MON_RTY_O,
MON_DAT_O,
MON_ERR_O
);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Wishbone clock
input rst_i; // Wishbone reset
input [`LM32_WORD_RNG] MON_ADR_I; // Wishbone address
input MON_STB_I; // Wishbone strobe
input MON_CYC_I; // Wishbone cycle
input [`LM32_WORD_RNG] MON_DAT_I; // Wishbone write data
input [`LM32_BYTE_SELECT_RNG] MON_SEL_I; // Wishbone byte select
input MON_WE_I; // Wishbone write enable
input MON_LOCK_I; // Wishbone locked transfer
input [`LM32_CTYPE_RNG] MON_CTI_I; // Wishbone cycle type
input [`LM32_BTYPE_RNG] MON_BTE_I; // Wishbone burst type
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
output MON_ACK_O; // Wishbone acknowlege
reg MON_ACK_O;
output [`LM32_WORD_RNG] MON_DAT_O; // Wishbone data output
reg [`LM32_WORD_RNG] MON_DAT_O;
output MON_RTY_O; // Wishbone retry
wire MON_RTY_O;
output MON_ERR_O; // Wishbone error
wire MON_ERR_O;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
reg [1:0] state; // Current state of FSM
wire [`LM32_WORD_RNG] data, dataB; // Data read from RAM
reg write_enable; // RAM write enable
reg [`LM32_WORD_RNG] write_data; // RAM write data
/////////////////////////////////////////////////////
// Instantiations
/////////////////////////////////////////////////////
lm32_monitor_ram ram (
// ----- Inputs -------
.ClockA (clk_i),
.ClockB (clk_i),
.ResetA (rst_i),
.ResetB (rst_i),
.ClockEnA (`TRUE),
.ClockEnB (`FALSE),
.AddressA (MON_ADR_I[10:2]),
.AddressB (9'b0),
.DataInA (write_data),
.DataInB (32'b0),
.WrA (write_enable),
.WrB (`FALSE),
// ----- Outputs -------
.QA (data),
.QB (dataB)
);
/////////////////////////////////////////////////////
// Combinational Logic
/////////////////////////////////////////////////////
assign MON_RTY_O = `FALSE;
assign MON_ERR_O = `FALSE;
/////////////////////////////////////////////////////
// Sequential Logic
/////////////////////////////////////////////////////
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE)
begin
write_enable <= `FALSE;
MON_ACK_O <= `FALSE;
MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}};
state <= 2'b00;
end
else
begin
case (state)
2'b00:
begin
// Wait for a Wishbone access
if ((MON_STB_I == `TRUE) && (MON_CYC_I == `TRUE))
state <= 2'b01;
end
2'b01:
begin
// Output read data to Wishbone
MON_ACK_O <= `TRUE;
MON_DAT_O <= data;
// Sub-word writes are performed using read-modify-write
// as the Lattice EBRs don't support byte enables
if (MON_WE_I == `TRUE)
write_enable <= `TRUE;
write_data[7:0] <= MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0];
write_data[15:8] <= MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8];
write_data[23:16] <= MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16];
write_data[31:24] <= MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24];
state <= 2'b10;
end
2'b10:
begin
// Wishbone access occurs in this cycle
write_enable <= `FALSE;
MON_ACK_O <= `FALSE;
MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}};
state <= 2'b00;
end
endcase
end
end
endmodule
|
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: StackRAM.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 17.0.0 Build 595 04/25/2017 SJ Lite Edition
// ************************************************************
//Copyright (C) 2017 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Intel and sold by Intel or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module StackRAM (
address,
byteena,
clock,
data,
wren,
q);
input [9:0] address;
input [1:0] byteena;
input clock;
input [15:0] data;
input wren;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [1:0] byteena;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [15:0] sub_wire0;
wire [15:0] q = sub_wire0[15:0];
altsyncram altsyncram_component (
.address_a (address),
.byteena_a (byteena),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "DONT_CARE",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 16,
altsyncram_component.width_byteena_a = 2;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "2"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: byteena 0 0 2 0 INPUT VCC "byteena[1..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena 0 0 2 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL StackRAM.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL StackRAM.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL StackRAM.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL StackRAM.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL StackRAM_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL StackRAM_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Filename: tx_data_pipeline.v
// Version: 1.0
// Verilog Standard: Verilog-2001
//
// Description: The tx_data_fifo takes 0-bit aligned packet data and
// puts each DW into one of N FIFOs where N = (C_DATA_WIDTH/32).
//
// The data interface (TX_DATA) is an interface for N 32-bit FIFOs, where N =
// (C_DATA_WIDTH/32). The START_FLAG signal indicates that the first dword of
// a packet is in FIFO 0 (TX_DATA[31:0]). Each FIFO interface also contains an
// END_FLAG signal in the END_FLAGS bus. When a bit in END_FLAGS bus is asserted,
// its corresponding fifo contains the last dword of data for the current
// packet. START_FLAG, END_FLAG and DATA are all qualified by the VALID signal,
// and read by the READY signal.
//
// The write interface (WR_TX) differs slightly from the read interface because it
// produces a READY signal and consumes a VALID signal. VALID is asserted when an
// entire packet has been packed into a FIFO.
//
// TODO:
// - Make sure that the synthesis tool is removing the other three start
// flag wires (and modifying the width of the FIFOs)
//
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh" // Defines the user-facing signal widths.
module tx_data_fifo
#(parameter C_DEPTH_PACKETS = 10,
parameter C_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_MAX_PAYLOAD = 256 // BYTES
)
(
// Interface: Clocks
input CLK,
// Interface: Reset
input RST_IN,
// Interface: WR TX DATA
input [C_DATA_WIDTH-1:0] WR_TX_DATA,
input WR_TX_DATA_VALID,
input WR_TX_DATA_START_FLAG,
input [(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_WORD_VALID,
input [(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_END_FLAGS,
output WR_TX_DATA_READY,
// Interface: RD TX DATA
input [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_WORD_READY,
output [C_DATA_WIDTH-1:0] RD_TX_DATA,
output RD_TX_DATA_START_FLAG,
output [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_END_FLAGS,
output [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_WORD_VALID,
output RD_TX_DATA_PACKET_VALID
);
`include "functions.vh"
localparam C_FIFO_OUTPUT_DEPTH = 1;
localparam C_INPUT_DEPTH = C_PIPELINE_INPUT != 0 ? 1 : 0;
localparam C_OUTPUT_DEPTH = C_PIPELINE_OUTPUT != 0 ? 1 : 0;
localparam C_MAXPACKET_LINES = (C_MAX_PAYLOAD*8)/C_DATA_WIDTH;
localparam C_FIFO_DEPTH = C_MAXPACKET_LINES*C_DEPTH_PACKETS;
localparam C_FIFO_DATA_WIDTH = 32;
localparam C_REGISTER_WIDTH = C_FIFO_DATA_WIDTH + 2;
localparam C_FIFO_WIDTH = C_FIFO_DATA_WIDTH + 2; // Data, end flag and start flag
localparam C_NUM_FIFOS = (C_DATA_WIDTH/32);
genvar i;
wire RST;
wire [C_FIFO_DATA_WIDTH-1:0] wWrTxData[C_NUM_FIFOS-1:0];
wire [C_NUM_FIFOS-1:0] wWrTxDataValid;
wire [C_NUM_FIFOS-1:0] wWrTxDataReady;
wire [C_NUM_FIFOS-1:0] wWrTxDataStartFlags;
wire [C_NUM_FIFOS-1:0] wWrTxDataEndFlags;
wire [C_NUM_FIFOS-1:0] _wRdTxDataStartFlags;
wire [C_FIFO_DATA_WIDTH-1:0] wRdTxData[C_NUM_FIFOS-1:0];
wire [C_NUM_FIFOS-1:0] wRdTxDataValid;
wire [C_NUM_FIFOS-1:0] wRdTxDataReady;
wire [C_NUM_FIFOS-1:0] wRdTxDataStartFlags;
wire [C_NUM_FIFOS-1:0] wRdTxDataEndFlags;
wire wRdTxDataPacketValid;
wire wWrTxEndFlagValid;
wire wWrTxEndFlagReady;
wire wRdTxEndFlagValid;
wire wRdTxEndFlagReady;
wire wPacketDecrement;
wire wPacketIncrement;
reg [clog2(C_DEPTH_PACKETS+1)-1:0] rPacketCounter,_rPacketCounter;
/*AUTOINPUT*/
/*AUTOWIRE*/
///*AUTOOUTPUT*/
assign RST = RST_IN;
assign wWrTxEndFlagValid = (wWrTxDataEndFlags & wWrTxDataValid) != {C_NUM_FIFOS{1'b0}};
assign wWrTxEndFlagReady = rPacketCounter != C_DEPTH_PACKETS;// Designed a small bit of latency here to help timing...
assign wPacketIncrement = wWrTxEndFlagValid & wWrTxEndFlagReady;
assign wPacketDecrement = wRdTxEndFlagValid & wRdTxEndFlagReady;
assign WR_TX_DATA_READY = wWrTxEndFlagReady;
assign wRdTxEndFlagValid = rPacketCounter != 0;
assign wRdTxEndFlagReady = (wRdTxDataReady & wRdTxDataEndFlags & wRdTxDataValid) != {C_NUM_FIFOS{1'b0}};
assign wRdTxDataPacketValid = rPacketCounter != 0;
assign RD_TX_DATA_START_FLAG = _wRdTxDataStartFlags[0];
always @(*) begin
_rPacketCounter = rPacketCounter;
if(wPacketIncrement & wPacketDecrement) begin
_rPacketCounter = rPacketCounter + 0;
end else if(wPacketIncrement) begin
_rPacketCounter = rPacketCounter + 1;
end else if(wPacketDecrement) begin
_rPacketCounter = rPacketCounter - 1;
end
end // always @ (*)
always @(posedge CLK) begin
if(RST_IN) begin
rPacketCounter <= #1 0;
end else begin
rPacketCounter <= #1 _rPacketCounter;
end
end
generate
for( i = 0 ; i < C_NUM_FIFOS ; i = i + 1 ) begin : gen_regs_fifos
pipeline
#(
.C_DEPTH (C_INPUT_DEPTH),
.C_USE_MEMORY (0),
.C_WIDTH (C_REGISTER_WIDTH)
/*AUTOINSTPARAM*/)
input_pipeline_inst_
(
// Outputs
.WR_DATA_READY (),
.RD_DATA ({wWrTxData[i], wWrTxDataEndFlags[i],wWrTxDataStartFlags[i]}),
.RD_DATA_VALID (wWrTxDataValid[i]),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.WR_DATA ({WR_TX_DATA[C_FIFO_DATA_WIDTH*i +: C_FIFO_DATA_WIDTH],
WR_TX_DATA_END_FLAGS[i], (i == 0) ? WR_TX_DATA_START_FLAG: 1'b0}),
.WR_DATA_VALID (WR_TX_DATA_VALID & WR_TX_DATA_WORD_VALID[i]),
.RD_DATA_READY (wWrTxDataReady[i]));
fifo
#(
// Parameters
.C_WIDTH (C_FIFO_WIDTH),
.C_DEPTH (C_FIFO_DEPTH),
.C_DELAY (0)
/*AUTOINSTPARAM*/)
fifo_inst_
(
// Outputs
.RD_DATA ({wRdTxData[i], wRdTxDataStartFlags[i], wRdTxDataEndFlags[i]}),
.WR_READY (wWrTxDataReady[i]),
.RD_VALID (wRdTxDataValid[i]),
// Inputs
.WR_DATA ({wWrTxData[i], wWrTxDataStartFlags[i], wWrTxDataEndFlags[i]}),
.WR_VALID (wWrTxDataValid[i]),
.RD_READY (wRdTxDataReady[i]),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST (RST));
pipeline
#(
.C_DEPTH (C_FIFO_OUTPUT_DEPTH),
.C_USE_MEMORY (0),
.C_WIDTH (C_FIFO_WIDTH)
/*AUTOINSTPARAM*/)
fifo_pipeline_inst_
(
// Outputs
.WR_DATA_READY (wRdTxDataReady[i]),
.RD_DATA ({RD_TX_DATA[i*32 +: 32],
_wRdTxDataStartFlags[i],
RD_TX_DATA_END_FLAGS[i]}),
.RD_DATA_VALID (RD_TX_DATA_WORD_VALID[i]),
// Inputs
.WR_DATA ({wRdTxData[i],
wRdTxDataStartFlags[i],
wRdTxDataEndFlags[i]}),
.WR_DATA_VALID (wRdTxDataValid[i]),
.RD_DATA_READY (RD_TX_DATA_WORD_READY[i]),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
end // for ( i = 0 ; i < C_NUM_FIFOS ; i = i + 1 )
endgenerate
endmodule
// Local Variables:
// verilog-library-directories:("." "../../common/")
// End:
|
//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
// On Mon Nov 5 13:21:12 EST 2012
//
//
// Ports:
// Name I/O size props
// wciS0_SResp O 2 reg
// wciS0_SData O 32 reg
// wciS0_SThreadBusy O 1
// wciS0_SFlag O 2
// wtiS0_SThreadBusy O 1 reg
// wtiS0_SReset_n O 1
// wsiM0_MCmd O 3
// wsiM0_MReqLast O 1
// wsiM0_MBurstPrecise O 1
// wsiM0_MBurstLength O 12
// wsiM0_MData O 32 reg
// wsiM0_MByteEn O 4 reg
// wsiM0_MReqInfo O 8
// wsiM0_MReset_n O 1
// adc_oe O 1 const
// adc_sclkgate O 1 reg
// adc_resetp O 1 reg
// adc_sen O 1 reg
// adc_smosi O 1 reg
// CLK_adc_sclk O 1 clock
// CLK_GATE_adc_sclk O 1 const
// CLK_adc_sclkn O 1 clock
// CLK_GATE_adc_sclkn O 1 const
// CLK_adcSdrClk O 1
// CLK_GATE_adcSdrClk O 1 const
// RST_N_adc_rst O 1 reset
// RST_N_adcSdrRst O 1 reset
// CLK_sys0_clk I 1 unused
// RST_N_sys0_rst I 1 unused
// CLK_adc_clock I 1
// RST_N_adc_reset I 1 unused
// CLK_adcCaptureClk I 1 clock
// wciS0_Clk I 1 clock
// wciS0_MReset_n I 1 reset
// wciS0_MCmd I 3
// wciS0_MAddrSpace I 1
// wciS0_MByteEn I 4
// wciS0_MAddr I 32
// wciS0_MData I 32
// wciS0_MFlag I 2 unused
// wtiS0_req I 67 reg
// adc_da_i I 14 reg
// adc_db_i I 14 reg
// adc_smiso_i I 1 reg
// wsiM0_SThreadBusy I 1 reg
// wsiM0_SReset_n I 1 reg
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkIQADCWorker(CLK_sys0_clk,
RST_N_sys0_rst,
CLK_adc_clock,
RST_N_adc_reset,
CLK_adcCaptureClk,
wciS0_Clk,
wciS0_MReset_n,
wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData,
wciS0_SResp,
wciS0_SData,
wciS0_SThreadBusy,
wciS0_SFlag,
wciS0_MFlag,
wtiS0_req,
wtiS0_SThreadBusy,
wtiS0_SReset_n,
wsiM0_MCmd,
wsiM0_MReqLast,
wsiM0_MBurstPrecise,
wsiM0_MBurstLength,
wsiM0_MData,
wsiM0_MByteEn,
wsiM0_MReqInfo,
wsiM0_SThreadBusy,
wsiM0_MReset_n,
wsiM0_SReset_n,
adc_oe,
adc_da_i,
adc_db_i,
adc_sclkgate,
adc_resetp,
adc_sen,
adc_smosi,
adc_smiso_i,
CLK_adc_sclk,
CLK_GATE_adc_sclk,
CLK_adc_sclkn,
CLK_GATE_adc_sclkn,
CLK_adcSdrClk,
CLK_GATE_adcSdrClk,
RST_N_adc_rst,
RST_N_adcSdrRst);
parameter [0 : 0] hasDebugLogic = 1'b0;
input CLK_sys0_clk;
input RST_N_sys0_rst;
input CLK_adc_clock;
input RST_N_adc_reset;
input CLK_adcCaptureClk;
input wciS0_Clk;
input wciS0_MReset_n;
// action method wciS0_mCmd
input [2 : 0] wciS0_MCmd;
// action method wciS0_mAddrSpace
input wciS0_MAddrSpace;
// action method wciS0_mByteEn
input [3 : 0] wciS0_MByteEn;
// action method wciS0_mAddr
input [31 : 0] wciS0_MAddr;
// action method wciS0_mData
input [31 : 0] wciS0_MData;
// value method wciS0_sResp
output [1 : 0] wciS0_SResp;
// value method wciS0_sData
output [31 : 0] wciS0_SData;
// value method wciS0_sThreadBusy
output wciS0_SThreadBusy;
// value method wciS0_sFlag
output [1 : 0] wciS0_SFlag;
// action method wciS0_mFlag
input [1 : 0] wciS0_MFlag;
// action method wtiS0_put
input [66 : 0] wtiS0_req;
// value method wtiS0_sThreadBusy
output wtiS0_SThreadBusy;
// value method wtiS0_sReset_n
output wtiS0_SReset_n;
// value method wsiM0_mCmd
output [2 : 0] wsiM0_MCmd;
// value method wsiM0_mReqLast
output wsiM0_MReqLast;
// value method wsiM0_mBurstPrecise
output wsiM0_MBurstPrecise;
// value method wsiM0_mBurstLength
output [11 : 0] wsiM0_MBurstLength;
// value method wsiM0_mData
output [31 : 0] wsiM0_MData;
// value method wsiM0_mByteEn
output [3 : 0] wsiM0_MByteEn;
// value method wsiM0_mReqInfo
output [7 : 0] wsiM0_MReqInfo;
// value method wsiM0_mDataInfo
// action method wsiM0_sThreadBusy
input wsiM0_SThreadBusy;
// value method wsiM0_mReset_n
output wsiM0_MReset_n;
// action method wsiM0_sReset_n
input wsiM0_SReset_n;
// value method adc_oe
output adc_oe;
// action method adc_da
input [13 : 0] adc_da_i;
// action method adc_db
input [13 : 0] adc_db_i;
// value method adc_sclkgate
output adc_sclkgate;
// value method adc_resetp
output adc_resetp;
// value method adc_sen
output adc_sen;
// value method adc_smosi
output adc_smosi;
// action method adc_smiso
input adc_smiso_i;
// oscillator and gates for output clock CLK_adc_sclk
output CLK_adc_sclk;
output CLK_GATE_adc_sclk;
// oscillator and gates for output clock CLK_adc_sclkn
output CLK_adc_sclkn;
output CLK_GATE_adc_sclkn;
// oscillator and gates for output clock CLK_adcSdrClk
output CLK_adcSdrClk;
output CLK_GATE_adcSdrClk;
// output resets
output RST_N_adc_rst;
output RST_N_adcSdrRst;
// signals for module outputs
wire [31 : 0] wciS0_SData, wsiM0_MData;
wire [11 : 0] wsiM0_MBurstLength;
wire [7 : 0] wsiM0_MReqInfo;
wire [3 : 0] wsiM0_MByteEn;
wire [2 : 0] wsiM0_MCmd;
wire [1 : 0] wciS0_SFlag, wciS0_SResp;
wire CLK_GATE_adcSdrClk,
CLK_GATE_adc_sclk,
CLK_GATE_adc_sclkn,
CLK_adcSdrClk,
CLK_adc_sclk,
CLK_adc_sclkn,
RST_N_adcSdrRst,
RST_N_adc_rst,
adc_oe,
adc_resetp,
adc_sclkgate,
adc_sen,
adc_smosi,
wciS0_SThreadBusy,
wsiM0_MBurstPrecise,
wsiM0_MReqLast,
wsiM0_MReset_n,
wtiS0_SReset_n,
wtiS0_SThreadBusy;
// inlined wires
wire [95 : 0] wsiM_extStatusW$wget;
wire [71 : 0] wci_wslv_wciReq$wget;
wire [66 : 0] wti_wtiReq$wget;
wire [63 : 0] adcCore_colGate_nowW$wget, adcCore_nowW$wget;
wire [60 : 0] wsiM_reqFifo_x_wire$wget;
wire [38 : 0] adcCore_sampF_wDataIn$wget, adcCore_sampF_wDataOut$wget;
wire [33 : 0] wci_wslv_respF_x_wire$wget;
wire [31 : 0] adcCore_colGate_sampDataW$wget,
wci_wci_Es_mAddr_w$wget,
wci_wci_Es_mData_w$wget;
wire [17 : 0] fcAdc_grayCounter_wdCounterCrossing$wget;
wire [15 : 0] adcCore_colGate_maxBurstLenW$wget;
wire [10 : 0] adcCore_sampF_rRdPtr_wdCounterCrossing$wget,
adcCore_sampF_rWrPtr_wdCounterCrossing$wget;
wire [3 : 0] wci_wci_Es_mByteEn_w$wget;
wire [2 : 0] wci_wci_Es_mCmd_w$wget, wci_wslv_wEdge$wget;
wire adcCore_acquireDReg_1$wget,
adcCore_acquireDReg_1$whas,
adcCore_adcRst_1$wget,
adcCore_adcRst_1$whas,
adcCore_averageDReg_1$wget,
adcCore_averageDReg_1$whas,
adcCore_colGate_average_dw$wget,
adcCore_colGate_average_dw$whas,
adcCore_colGate_collectPW$whas,
adcCore_colGate_enaSyncPW$whas,
adcCore_colGate_enaTimestampPW$whas,
adcCore_colGate_maxBurstLenW$whas,
adcCore_colGate_nowW$whas,
adcCore_colGate_operatePW$whas,
adcCore_colGate_sampActive_1$wget,
adcCore_colGate_sampActive_1$whas,
adcCore_colGate_sampDataW$whas,
adcCore_iseqFsm_abort$wget,
adcCore_iseqFsm_abort$whas,
adcCore_iseqFsm_start_reg_1_1$wget,
adcCore_iseqFsm_start_reg_1_1$whas,
adcCore_iseqFsm_start_wire$wget,
adcCore_iseqFsm_start_wire$whas,
adcCore_iseqFsm_state_fired_1$wget,
adcCore_iseqFsm_state_fired_1$whas,
adcCore_iseqFsm_state_overlap_pw$whas,
adcCore_iseqFsm_state_set_pw$whas,
adcCore_nowW$whas,
adcCore_operateDReg_1$wget,
adcCore_operateDReg_1$whas,
adcCore_sampF_pwDequeue$whas,
adcCore_sampF_pwEnqueue$whas,
adcCore_sampF_rRdPtr_pwDecrement$whas,
adcCore_sampF_rRdPtr_pwIncrement$whas,
adcCore_sampF_rWrPtr_pwDecrement$whas,
adcCore_sampF_rWrPtr_pwIncrement$whas,
adcCore_sampF_wDataIn$whas,
adcCore_sampF_wDataOut$whas,
adcCore_spiI_cGate_1$wget,
adcCore_spiI_cGate_1$whas,
adcCore_spiI_csbR_1$wget,
adcCore_spiI_csbR_1$whas,
adcCore_spiI_doResp_1$wget,
adcCore_spiI_doResp_1$whas,
adcCore_spiI_reqF_dClear_pw$whas,
adcCore_spiI_reqF_deq_happened$whas,
adcCore_spiI_reqF_deq_pw$whas,
adcCore_spiI_reqF_enq_pw$whas,
adcCore_spiI_reqF_sClear_pw$whas,
adcCore_spiI_respF_dClear_pw$whas,
adcCore_spiI_respF_deq_happened$whas,
adcCore_spiI_respF_deq_pw$whas,
adcCore_spiI_respF_enq_pw$whas,
adcCore_spiI_respF_sClear_pw$whas,
adcCore_spiI_sdiWs$wget,
adcCore_spiI_sdoR_1$wget,
adcCore_spiI_sdoR_1$whas,
fcAdc_grayCounter_pwDecrement$whas,
fcAdc_grayCounter_pwIncrement$whas,
fcAdc_pulseAction_1$wget,
fcAdc_pulseAction_1$whas,
oneKHz_decAction$whas,
oneKHz_incAction$whas,
wci_wci_Es_mAddrSpace_w$wget,
wci_wci_Es_mAddrSpace_w$whas,
wci_wci_Es_mAddr_w$whas,
wci_wci_Es_mByteEn_w$whas,
wci_wci_Es_mCmd_w$whas,
wci_wci_Es_mData_w$whas,
wci_wslv_ctlAckReg_1$wget,
wci_wslv_ctlAckReg_1$whas,
wci_wslv_reqF_r_clr$whas,
wci_wslv_reqF_r_deq$whas,
wci_wslv_reqF_r_enq$whas,
wci_wslv_respF_dequeueing$whas,
wci_wslv_respF_enqueueing$whas,
wci_wslv_respF_x_wire$whas,
wci_wslv_sFlagReg_1$wget,
wci_wslv_sFlagReg_1$whas,
wci_wslv_sThreadBusy_pw$whas,
wci_wslv_wEdge$whas,
wci_wslv_wciReq$whas,
wci_wslv_wci_cfrd_pw$whas,
wci_wslv_wci_cfwr_pw$whas,
wci_wslv_wci_ctrl_pw$whas,
wsiM_operateD_1$wget,
wsiM_operateD_1$whas,
wsiM_peerIsReady_1$wget,
wsiM_peerIsReady_1$whas,
wsiM_reqFifo_dequeueing$whas,
wsiM_reqFifo_enqueueing$whas,
wsiM_reqFifo_x_wire$whas,
wsiM_sThreadBusy_pw$whas,
wti_operateD_1$wget,
wti_operateD_1$whas,
wti_wtiReq$whas;
// register adcControl
reg [31 : 0] adcControl;
wire [31 : 0] adcControl$D_IN;
wire adcControl$EN;
// register adcCore_acquireDReg
reg adcCore_acquireDReg;
wire adcCore_acquireDReg$D_IN, adcCore_acquireDReg$EN;
// register adcCore_adcRst
reg adcCore_adcRst;
wire adcCore_adcRst$D_IN, adcCore_adcRst$EN;
// register adcCore_averageDReg
reg adcCore_averageDReg;
wire adcCore_averageDReg$D_IN, adcCore_averageDReg$EN;
// register adcCore_colGate_avgEven
reg [17 : 0] adcCore_colGate_avgEven;
wire [17 : 0] adcCore_colGate_avgEven$D_IN;
wire adcCore_colGate_avgEven$EN;
// register adcCore_colGate_avgOdd
reg [17 : 0] adcCore_colGate_avgOdd;
wire [17 : 0] adcCore_colGate_avgOdd$D_IN;
wire adcCore_colGate_avgOdd$EN;
// register adcCore_colGate_avgPhase
reg [1 : 0] adcCore_colGate_avgPhase;
wire [1 : 0] adcCore_colGate_avgPhase$D_IN;
wire adcCore_colGate_avgPhase$EN;
// register adcCore_colGate_collectD
reg adcCore_colGate_collectD;
wire adcCore_colGate_collectD$D_IN, adcCore_colGate_collectD$EN;
// register adcCore_colGate_dropCount
reg [31 : 0] adcCore_colGate_dropCount;
wire [31 : 0] adcCore_colGate_dropCount$D_IN;
wire adcCore_colGate_dropCount$EN;
// register adcCore_colGate_dwellFails
reg [31 : 0] adcCore_colGate_dwellFails;
wire [31 : 0] adcCore_colGate_dwellFails$D_IN;
wire adcCore_colGate_dwellFails$EN;
// register adcCore_colGate_dwellStarts
reg [31 : 0] adcCore_colGate_dwellStarts;
wire [31 : 0] adcCore_colGate_dwellStarts$D_IN;
wire adcCore_colGate_dwellStarts$EN;
// register adcCore_colGate_ovrRecover
reg [3 : 0] adcCore_colGate_ovrRecover;
reg [3 : 0] adcCore_colGate_ovrRecover$D_IN;
wire adcCore_colGate_ovrRecover$EN;
// register adcCore_colGate_sampActive
reg adcCore_colGate_sampActive;
wire adcCore_colGate_sampActive$D_IN, adcCore_colGate_sampActive$EN;
// register adcCore_colGate_sampActiveD
reg adcCore_colGate_sampActiveD;
wire adcCore_colGate_sampActiveD$D_IN, adcCore_colGate_sampActiveD$EN;
// register adcCore_colGate_sampCount
reg [31 : 0] adcCore_colGate_sampCount;
wire [31 : 0] adcCore_colGate_sampCount$D_IN;
wire adcCore_colGate_sampCount$EN;
// register adcCore_colGate_sampDataWD
reg [31 : 0] adcCore_colGate_sampDataWD;
wire [31 : 0] adcCore_colGate_sampDataWD$D_IN;
wire adcCore_colGate_sampDataWD$EN;
// register adcCore_colGate_syncMesg
reg [1 : 0] adcCore_colGate_syncMesg;
wire [1 : 0] adcCore_colGate_syncMesg$D_IN;
wire adcCore_colGate_syncMesg$EN;
// register adcCore_colGate_timeMesg
reg [2 : 0] adcCore_colGate_timeMesg;
wire [2 : 0] adcCore_colGate_timeMesg$D_IN;
wire adcCore_colGate_timeMesg$EN;
// register adcCore_colGate_uprollCnt
reg [15 : 0] adcCore_colGate_uprollCnt;
wire [15 : 0] adcCore_colGate_uprollCnt$D_IN;
wire adcCore_colGate_uprollCnt$EN;
// register adcCore_iobA
reg [13 : 0] adcCore_iobA;
wire [13 : 0] adcCore_iobA$D_IN;
wire adcCore_iobA$EN;
// register adcCore_iobB
reg [13 : 0] adcCore_iobB;
wire [13 : 0] adcCore_iobB$D_IN;
wire adcCore_iobB$EN;
// register adcCore_iseqFsm_jj_delay_count
reg [12 : 0] adcCore_iseqFsm_jj_delay_count;
wire [12 : 0] adcCore_iseqFsm_jj_delay_count$D_IN;
wire adcCore_iseqFsm_jj_delay_count$EN;
// register adcCore_iseqFsm_start_reg
reg adcCore_iseqFsm_start_reg;
wire adcCore_iseqFsm_start_reg$D_IN, adcCore_iseqFsm_start_reg$EN;
// register adcCore_iseqFsm_start_reg_1
reg adcCore_iseqFsm_start_reg_1;
wire adcCore_iseqFsm_start_reg_1$D_IN, adcCore_iseqFsm_start_reg_1$EN;
// register adcCore_iseqFsm_state_can_overlap
reg adcCore_iseqFsm_state_can_overlap;
wire adcCore_iseqFsm_state_can_overlap$D_IN,
adcCore_iseqFsm_state_can_overlap$EN;
// register adcCore_iseqFsm_state_fired
reg adcCore_iseqFsm_state_fired;
wire adcCore_iseqFsm_state_fired$D_IN, adcCore_iseqFsm_state_fired$EN;
// register adcCore_iseqFsm_state_mkFSMstate
reg [3 : 0] adcCore_iseqFsm_state_mkFSMstate;
reg [3 : 0] adcCore_iseqFsm_state_mkFSMstate$D_IN;
wire adcCore_iseqFsm_state_mkFSMstate$EN;
// register adcCore_operateDReg
reg adcCore_operateDReg;
wire adcCore_operateDReg$D_IN, adcCore_operateDReg$EN;
// register adcCore_readMode
reg adcCore_readMode;
wire adcCore_readMode$D_IN, adcCore_readMode$EN;
// register adcCore_samp
reg [31 : 0] adcCore_samp;
wire [31 : 0] adcCore_samp$D_IN;
wire adcCore_samp$EN;
// register adcCore_sampF_rRdPtr_rdCounter
reg [10 : 0] adcCore_sampF_rRdPtr_rdCounter;
wire [10 : 0] adcCore_sampF_rRdPtr_rdCounter$D_IN;
wire adcCore_sampF_rRdPtr_rdCounter$EN;
// register adcCore_sampF_rRdPtr_rdCounterPre
reg [10 : 0] adcCore_sampF_rRdPtr_rdCounterPre;
wire [10 : 0] adcCore_sampF_rRdPtr_rdCounterPre$D_IN;
wire adcCore_sampF_rRdPtr_rdCounterPre$EN;
// register adcCore_sampF_rRdPtr_rsCounter
reg [10 : 0] adcCore_sampF_rRdPtr_rsCounter;
wire [10 : 0] adcCore_sampF_rRdPtr_rsCounter$D_IN;
wire adcCore_sampF_rRdPtr_rsCounter$EN;
// register adcCore_sampF_rWrPtr_rdCounter
reg [10 : 0] adcCore_sampF_rWrPtr_rdCounter;
wire [10 : 0] adcCore_sampF_rWrPtr_rdCounter$D_IN;
wire adcCore_sampF_rWrPtr_rdCounter$EN;
// register adcCore_sampF_rWrPtr_rdCounterPre
reg [10 : 0] adcCore_sampF_rWrPtr_rdCounterPre;
wire [10 : 0] adcCore_sampF_rWrPtr_rdCounterPre$D_IN;
wire adcCore_sampF_rWrPtr_rdCounterPre$EN;
// register adcCore_sampF_rWrPtr_rsCounter
reg [10 : 0] adcCore_sampF_rWrPtr_rsCounter;
wire [10 : 0] adcCore_sampF_rWrPtr_rsCounter$D_IN;
wire adcCore_sampF_rWrPtr_rsCounter$EN;
// register adcCore_spiI_cGate
reg adcCore_spiI_cGate;
wire adcCore_spiI_cGate$D_IN, adcCore_spiI_cGate$EN;
// register adcCore_spiI_cap
reg adcCore_spiI_cap;
wire adcCore_spiI_cap$D_IN, adcCore_spiI_cap$EN;
// register adcCore_spiI_cap_1
reg adcCore_spiI_cap_1;
wire adcCore_spiI_cap_1$D_IN, adcCore_spiI_cap_1$EN;
// register adcCore_spiI_cap_2
reg adcCore_spiI_cap_2;
wire adcCore_spiI_cap_2$D_IN, adcCore_spiI_cap_2$EN;
// register adcCore_spiI_cap_3
reg adcCore_spiI_cap_3;
wire adcCore_spiI_cap_3$D_IN, adcCore_spiI_cap_3$EN;
// register adcCore_spiI_cap_4
reg adcCore_spiI_cap_4;
wire adcCore_spiI_cap_4$D_IN, adcCore_spiI_cap_4$EN;
// register adcCore_spiI_cap_5
reg adcCore_spiI_cap_5;
wire adcCore_spiI_cap_5$D_IN, adcCore_spiI_cap_5$EN;
// register adcCore_spiI_cap_6
reg adcCore_spiI_cap_6;
wire adcCore_spiI_cap_6$D_IN, adcCore_spiI_cap_6$EN;
// register adcCore_spiI_cap_7
reg adcCore_spiI_cap_7;
wire adcCore_spiI_cap_7$D_IN, adcCore_spiI_cap_7$EN;
// register adcCore_spiI_csbR
reg adcCore_spiI_csbR;
wire adcCore_spiI_csbR$D_IN, adcCore_spiI_csbR$EN;
// register adcCore_spiI_dPos
reg [2 : 0] adcCore_spiI_dPos;
wire [2 : 0] adcCore_spiI_dPos$D_IN;
wire adcCore_spiI_dPos$EN;
// register adcCore_spiI_doResp
reg adcCore_spiI_doResp;
wire adcCore_spiI_doResp$D_IN, adcCore_spiI_doResp$EN;
// register adcCore_spiI_iPos
reg [3 : 0] adcCore_spiI_iPos;
wire [3 : 0] adcCore_spiI_iPos$D_IN;
wire adcCore_spiI_iPos$EN;
// register adcCore_spiI_reqF_head_wrapped
reg adcCore_spiI_reqF_head_wrapped;
wire adcCore_spiI_reqF_head_wrapped$D_IN, adcCore_spiI_reqF_head_wrapped$EN;
// register adcCore_spiI_reqF_tail_wrapped
reg adcCore_spiI_reqF_tail_wrapped;
wire adcCore_spiI_reqF_tail_wrapped$D_IN, adcCore_spiI_reqF_tail_wrapped$EN;
// register adcCore_spiI_reqS
reg [16 : 0] adcCore_spiI_reqS;
reg [16 : 0] adcCore_spiI_reqS$D_IN;
wire adcCore_spiI_reqS$EN;
// register adcCore_spiI_respF_head_wrapped
reg adcCore_spiI_respF_head_wrapped;
wire adcCore_spiI_respF_head_wrapped$D_IN,
adcCore_spiI_respF_head_wrapped$EN;
// register adcCore_spiI_respF_tail_wrapped
reg adcCore_spiI_respF_tail_wrapped;
wire adcCore_spiI_respF_tail_wrapped$D_IN,
adcCore_spiI_respF_tail_wrapped$EN;
// register adcCore_spiI_respS
reg [7 : 0] adcCore_spiI_respS;
wire [7 : 0] adcCore_spiI_respS$D_IN;
wire adcCore_spiI_respS$EN;
// register adcCore_spiI_sdiP
reg adcCore_spiI_sdiP;
wire adcCore_spiI_sdiP$D_IN, adcCore_spiI_sdiP$EN;
// register adcCore_spiI_sdoR
reg adcCore_spiI_sdoR;
wire adcCore_spiI_sdoR$D_IN, adcCore_spiI_sdoR$EN;
// register adcCore_spiI_xmt_d
reg adcCore_spiI_xmt_d;
wire adcCore_spiI_xmt_d$D_IN, adcCore_spiI_xmt_d$EN;
// register adcCore_spiI_xmt_i
reg adcCore_spiI_xmt_i;
wire adcCore_spiI_xmt_i$D_IN, adcCore_spiI_xmt_i$EN;
// register fcAdc_countNow
reg [17 : 0] fcAdc_countNow;
wire [17 : 0] fcAdc_countNow$D_IN;
wire fcAdc_countNow$EN;
// register fcAdc_countPast
reg [17 : 0] fcAdc_countPast;
wire [17 : 0] fcAdc_countPast$D_IN;
wire fcAdc_countPast$EN;
// register fcAdc_frequency
reg [17 : 0] fcAdc_frequency;
wire [17 : 0] fcAdc_frequency$D_IN;
wire fcAdc_frequency$EN;
// register fcAdc_grayCounter_rdCounter
reg [17 : 0] fcAdc_grayCounter_rdCounter;
wire [17 : 0] fcAdc_grayCounter_rdCounter$D_IN;
wire fcAdc_grayCounter_rdCounter$EN;
// register fcAdc_grayCounter_rdCounterPre
reg [17 : 0] fcAdc_grayCounter_rdCounterPre;
wire [17 : 0] fcAdc_grayCounter_rdCounterPre$D_IN;
wire fcAdc_grayCounter_rdCounterPre$EN;
// register fcAdc_grayCounter_rsCounter
reg [17 : 0] fcAdc_grayCounter_rsCounter;
wire [17 : 0] fcAdc_grayCounter_rsCounter$D_IN;
wire fcAdc_grayCounter_rsCounter$EN;
// register fcAdc_pulseAction
reg fcAdc_pulseAction;
wire fcAdc_pulseAction$D_IN, fcAdc_pulseAction$EN;
// register fcAdc_sampleCount
reg [15 : 0] fcAdc_sampleCount;
wire [15 : 0] fcAdc_sampleCount$D_IN;
wire fcAdc_sampleCount$EN;
// register initOpInFlight
reg initOpInFlight;
wire initOpInFlight$D_IN, initOpInFlight$EN;
// register lastOverflowMesg
reg [31 : 0] lastOverflowMesg;
wire [31 : 0] lastOverflowMesg$D_IN;
wire lastOverflowMesg$EN;
// register maxMesgLength
reg [31 : 0] maxMesgLength;
wire [31 : 0] maxMesgLength$D_IN;
wire maxMesgLength$EN;
// register mesgCount
reg [31 : 0] mesgCount;
wire [31 : 0] mesgCount$D_IN;
wire mesgCount$EN;
// register oneKHz_value
reg [17 : 0] oneKHz_value;
wire [17 : 0] oneKHz_value$D_IN;
wire oneKHz_value$EN;
// register overflowCountD
reg [31 : 0] overflowCountD;
wire [31 : 0] overflowCountD$D_IN;
wire overflowCountD$EN;
// register sFlagState
reg sFlagState;
wire sFlagState$D_IN, sFlagState$EN;
// register spiResp
reg [7 : 0] spiResp;
wire [7 : 0] spiResp$D_IN;
wire spiResp$EN;
// register splitReadInFlight
reg splitReadInFlight;
wire splitReadInFlight$D_IN, splitReadInFlight$EN;
// register wci_wslv_cEdge
reg [2 : 0] wci_wslv_cEdge;
wire [2 : 0] wci_wslv_cEdge$D_IN;
wire wci_wslv_cEdge$EN;
// register wci_wslv_cState
reg [2 : 0] wci_wslv_cState;
wire [2 : 0] wci_wslv_cState$D_IN;
wire wci_wslv_cState$EN;
// register wci_wslv_ctlAckReg
reg wci_wslv_ctlAckReg;
wire wci_wslv_ctlAckReg$D_IN, wci_wslv_ctlAckReg$EN;
// register wci_wslv_ctlOpActive
reg wci_wslv_ctlOpActive;
wire wci_wslv_ctlOpActive$D_IN, wci_wslv_ctlOpActive$EN;
// register wci_wslv_illegalEdge
reg wci_wslv_illegalEdge;
wire wci_wslv_illegalEdge$D_IN, wci_wslv_illegalEdge$EN;
// register wci_wslv_isReset_isInReset
reg wci_wslv_isReset_isInReset;
wire wci_wslv_isReset_isInReset$D_IN, wci_wslv_isReset_isInReset$EN;
// register wci_wslv_nState
reg [2 : 0] wci_wslv_nState;
reg [2 : 0] wci_wslv_nState$D_IN;
wire wci_wslv_nState$EN;
// register wci_wslv_reqF_countReg
reg [1 : 0] wci_wslv_reqF_countReg;
wire [1 : 0] wci_wslv_reqF_countReg$D_IN;
wire wci_wslv_reqF_countReg$EN;
// register wci_wslv_respF_c_r
reg [1 : 0] wci_wslv_respF_c_r;
wire [1 : 0] wci_wslv_respF_c_r$D_IN;
wire wci_wslv_respF_c_r$EN;
// register wci_wslv_respF_q_0
reg [33 : 0] wci_wslv_respF_q_0;
reg [33 : 0] wci_wslv_respF_q_0$D_IN;
wire wci_wslv_respF_q_0$EN;
// register wci_wslv_respF_q_1
reg [33 : 0] wci_wslv_respF_q_1;
reg [33 : 0] wci_wslv_respF_q_1$D_IN;
wire wci_wslv_respF_q_1$EN;
// register wci_wslv_sFlagReg
reg wci_wslv_sFlagReg;
wire wci_wslv_sFlagReg$D_IN, wci_wslv_sFlagReg$EN;
// register wci_wslv_sThreadBusy_d
reg wci_wslv_sThreadBusy_d;
wire wci_wslv_sThreadBusy_d$D_IN, wci_wslv_sThreadBusy_d$EN;
// register wsiM_burstKind
reg [1 : 0] wsiM_burstKind;
wire [1 : 0] wsiM_burstKind$D_IN;
wire wsiM_burstKind$EN;
// register wsiM_errorSticky
reg wsiM_errorSticky;
wire wsiM_errorSticky$D_IN, wsiM_errorSticky$EN;
// register wsiM_iMesgCount
reg [31 : 0] wsiM_iMesgCount;
wire [31 : 0] wsiM_iMesgCount$D_IN;
wire wsiM_iMesgCount$EN;
// register wsiM_isReset_isInReset
reg wsiM_isReset_isInReset;
wire wsiM_isReset_isInReset$D_IN, wsiM_isReset_isInReset$EN;
// register wsiM_operateD
reg wsiM_operateD;
wire wsiM_operateD$D_IN, wsiM_operateD$EN;
// register wsiM_pMesgCount
reg [31 : 0] wsiM_pMesgCount;
wire [31 : 0] wsiM_pMesgCount$D_IN;
wire wsiM_pMesgCount$EN;
// register wsiM_peerIsReady
reg wsiM_peerIsReady;
wire wsiM_peerIsReady$D_IN, wsiM_peerIsReady$EN;
// register wsiM_reqFifo_c_r
reg [1 : 0] wsiM_reqFifo_c_r;
wire [1 : 0] wsiM_reqFifo_c_r$D_IN;
wire wsiM_reqFifo_c_r$EN;
// register wsiM_reqFifo_q_0
reg [60 : 0] wsiM_reqFifo_q_0;
reg [60 : 0] wsiM_reqFifo_q_0$D_IN;
wire wsiM_reqFifo_q_0$EN;
// register wsiM_reqFifo_q_1
reg [60 : 0] wsiM_reqFifo_q_1;
reg [60 : 0] wsiM_reqFifo_q_1$D_IN;
wire wsiM_reqFifo_q_1$EN;
// register wsiM_sThreadBusy_d
reg wsiM_sThreadBusy_d;
wire wsiM_sThreadBusy_d$D_IN, wsiM_sThreadBusy_d$EN;
// register wsiM_statusR
reg [7 : 0] wsiM_statusR;
wire [7 : 0] wsiM_statusR$D_IN;
wire wsiM_statusR$EN;
// register wsiM_tBusyCount
reg [31 : 0] wsiM_tBusyCount;
wire [31 : 0] wsiM_tBusyCount$D_IN;
wire wsiM_tBusyCount$EN;
// register wsiM_trafficSticky
reg wsiM_trafficSticky;
wire wsiM_trafficSticky$D_IN, wsiM_trafficSticky$EN;
// register wti_isReset_isInReset
reg wti_isReset_isInReset;
wire wti_isReset_isInReset$D_IN, wti_isReset_isInReset$EN;
// register wti_nowReq
reg [66 : 0] wti_nowReq;
wire [66 : 0] wti_nowReq$D_IN;
wire wti_nowReq$EN;
// register wti_operateD
reg wti_operateD;
wire wti_operateD$D_IN, wti_operateD$EN;
// ports of submodule adcCore_acquireD
wire adcCore_acquireD$dD_OUT,
adcCore_acquireD$sD_IN,
adcCore_acquireD$sEN,
adcCore_acquireD$sRDY;
// ports of submodule adcCore_averageD
wire adcCore_averageD$dD_OUT,
adcCore_averageD$sD_IN,
adcCore_averageD$sEN,
adcCore_averageD$sRDY;
// ports of submodule adcCore_colGate_sampF
reg [38 : 0] adcCore_colGate_sampF$D_IN;
wire [38 : 0] adcCore_colGate_sampF$D_OUT;
wire adcCore_colGate_sampF$CLR,
adcCore_colGate_sampF$DEQ,
adcCore_colGate_sampF$EMPTY_N,
adcCore_colGate_sampF$ENQ,
adcCore_colGate_sampF$FULL_N;
// ports of submodule adcCore_maxBurstLengthR
wire [15 : 0] adcCore_maxBurstLengthR$dD_OUT, adcCore_maxBurstLengthR$sD_IN;
wire adcCore_maxBurstLengthR$sEN, adcCore_maxBurstLengthR$sRDY;
// ports of submodule adcCore_operateD
wire adcCore_operateD$dD_OUT,
adcCore_operateD$sD_IN,
adcCore_operateD$sEN,
adcCore_operateD$sRDY;
// ports of submodule adcCore_reqF
wire [16 : 0] adcCore_reqF$D_IN, adcCore_reqF$D_OUT;
wire adcCore_reqF$CLR,
adcCore_reqF$DEQ,
adcCore_reqF$EMPTY_N,
adcCore_reqF$ENQ,
adcCore_reqF$FULL_N;
// ports of submodule adcCore_sampCC
wire [31 : 0] adcCore_sampCC$dD_OUT, adcCore_sampCC$sD_IN;
wire adcCore_sampCC$sEN, adcCore_sampCC$sRDY;
// ports of submodule adcCore_sampF_memory
wire [38 : 0] adcCore_sampF_memory$DIA,
adcCore_sampF_memory$DIB,
adcCore_sampF_memory$DOB;
wire [9 : 0] adcCore_sampF_memory$ADDRA, adcCore_sampF_memory$ADDRB;
wire adcCore_sampF_memory$ENA,
adcCore_sampF_memory$ENB,
adcCore_sampF_memory$WEA,
adcCore_sampF_memory$WEB;
// ports of submodule adcCore_sdrRst
wire adcCore_sdrRst$OUT_RST;
// ports of submodule adcCore_spiI_cd
wire adcCore_spiI_cd$CLK_OUT, adcCore_spiI_cd$PREEDGE;
// ports of submodule adcCore_spiI_cinv
wire adcCore_spiI_cinv$CLK_OUT;
// ports of submodule adcCore_spiI_reqF_dCombinedReset
wire adcCore_spiI_reqF_dCombinedReset$RST_OUT;
// ports of submodule adcCore_spiI_reqF_dCrossedsReset
wire adcCore_spiI_reqF_dCrossedsReset$OUT_RST;
// ports of submodule adcCore_spiI_reqF_dInReset
wire adcCore_spiI_reqF_dInReset$VAL;
// ports of submodule adcCore_spiI_reqF_sCombinedReset
wire adcCore_spiI_reqF_sCombinedReset$RST_OUT;
// ports of submodule adcCore_spiI_reqF_sCrosseddReset
wire adcCore_spiI_reqF_sCrosseddReset$OUT_RST;
// ports of submodule adcCore_spiI_reqF_sInReset
wire adcCore_spiI_reqF_sInReset$VAL;
// ports of submodule adcCore_spiI_respF_dCombinedReset
wire adcCore_spiI_respF_dCombinedReset$RST_OUT;
// ports of submodule adcCore_spiI_respF_dCrossedsReset
wire adcCore_spiI_respF_dCrossedsReset$OUT_RST;
// ports of submodule adcCore_spiI_respF_dInReset
wire adcCore_spiI_respF_dInReset$VAL;
// ports of submodule adcCore_spiI_respF_sCombinedReset
wire adcCore_spiI_respF_sCombinedReset$RST_OUT;
// ports of submodule adcCore_spiI_respF_sCrosseddReset
wire adcCore_spiI_respF_sCrosseddReset$OUT_RST;
// ports of submodule adcCore_spiI_respF_sInReset
wire adcCore_spiI_respF_sInReset$VAL;
// ports of submodule adcCore_spiI_slowReset
wire adcCore_spiI_slowReset$OUT_RST;
// ports of submodule adcCore_statsCC
wire [127 : 0] adcCore_statsCC$dD_OUT, adcCore_statsCC$sD_IN;
wire adcCore_statsCC$sEN, adcCore_statsCC$sRDY;
// ports of submodule fcAdc_testRst
wire fcAdc_testRst$OUT_RST;
// ports of submodule wci_wslv_reqF
wire [71 : 0] wci_wslv_reqF$D_IN, wci_wslv_reqF$D_OUT;
wire wci_wslv_reqF$CLR,
wci_wslv_reqF$DEQ,
wci_wslv_reqF$EMPTY_N,
wci_wslv_reqF$ENQ;
// rule scheduling signals
wire CAN_FIRE_RL_get_adc_resp,
CAN_FIRE_RL_wci_cfrd,
WILL_FIRE_RL_adcCore_advance_spi_request,
WILL_FIRE_RL_adcCore_colGate_capture_collect,
WILL_FIRE_RL_adcCore_colGate_count_dropped_samples,
WILL_FIRE_RL_adcCore_colGate_count_dwells,
WILL_FIRE_RL_adcCore_colGate_form_avg4_sample,
WILL_FIRE_RL_adcCore_colGate_overrun_recovery,
WILL_FIRE_RL_adcCore_colGate_send_sync_mesg,
WILL_FIRE_RL_adcCore_colGate_send_timestamp_mesg,
WILL_FIRE_RL_adcCore_iseqFsm_action_l138c12,
WILL_FIRE_RL_adcCore_iseqFsm_action_l141c9,
WILL_FIRE_RL_adcCore_iseqFsm_action_l142c9,
WILL_FIRE_RL_adcCore_iseqFsm_action_l143c9,
WILL_FIRE_RL_adcCore_iseqFsm_action_l144c9,
WILL_FIRE_RL_adcCore_iseqFsm_action_l145c9,
WILL_FIRE_RL_adcCore_iseqFsm_action_l146c9,
WILL_FIRE_RL_adcCore_iseqFsm_action_np,
WILL_FIRE_RL_adcCore_iseqFsm_fsm_start,
WILL_FIRE_RL_adcCore_iseqFsm_idle_l137c3,
WILL_FIRE_RL_adcCore_spiI_reqF_deq_update_head,
WILL_FIRE_RL_adcCore_spiI_reqF_enq_update_tail,
WILL_FIRE_RL_adcCore_spiI_respF_deq_update_head,
WILL_FIRE_RL_adcCore_spiI_respF_enq_update_tail,
WILL_FIRE_RL_adcCore_spiI_send_d,
WILL_FIRE_RL_adcCore_spiI_send_i,
WILL_FIRE_RL_adcCore_spiI_start_cs,
WILL_FIRE_RL_wci_cfrd,
WILL_FIRE_RL_wci_cfwr,
WILL_FIRE_RL_wci_ctrl_EiI,
WILL_FIRE_RL_wci_ctrl_IsO,
WILL_FIRE_RL_wci_ctrl_OrE,
WILL_FIRE_RL_wci_wslv_ctl_op_complete,
WILL_FIRE_RL_wci_wslv_ctl_op_start,
WILL_FIRE_RL_wci_wslv_respF_both,
WILL_FIRE_RL_wci_wslv_respF_decCtr,
WILL_FIRE_RL_wci_wslv_respF_incCtr,
WILL_FIRE_RL_wsiM_reqFifo_both,
WILL_FIRE_RL_wsiM_reqFifo_decCtr,
WILL_FIRE_RL_wsiM_reqFifo_deq,
WILL_FIRE_RL_wsiM_reqFifo_incCtr;
// inputs to muxes for submodule ports
reg [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_2;
wire [60 : 0] MUX_wsiM_reqFifo_q_0$write_1__VAL_1,
MUX_wsiM_reqFifo_q_0$write_1__VAL_2,
MUX_wsiM_reqFifo_q_1$write_1__VAL_1;
wire [38 : 0] MUX_adcCore_colGate_sampF$enq_1__VAL_1,
MUX_adcCore_colGate_sampF$enq_1__VAL_2,
MUX_adcCore_colGate_sampF$enq_1__VAL_3;
wire [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_1,
MUX_wci_wslv_respF_q_1$write_1__VAL_1,
MUX_wci_wslv_respF_x_wire$wset_1__VAL_1,
MUX_wci_wslv_respF_x_wire$wset_1__VAL_2,
MUX_wci_wslv_respF_x_wire$wset_1__VAL_3;
wire [31 : 0] MUX_adcCore_colGate_dropCount$write_1__VAL_1,
MUX_adcCore_colGate_dwellFails$write_1__VAL_1,
MUX_adcCore_colGate_dwellStarts$write_1__VAL_1,
MUX_adcCore_colGate_sampCount$write_1__VAL_1;
wire [17 : 0] MUX_fcAdc_grayCounter_rsCounter$write_1__VAL_1,
MUX_oneKHz_value$write_1__VAL_1;
wire [16 : 0] MUX_adcCore_reqF$enq_1__VAL_1,
MUX_adcCore_reqF$enq_1__VAL_2,
MUX_adcCore_spiI_reqS$write_1__VAL_1;
wire [15 : 0] MUX_adcCore_colGate_uprollCnt$write_1__VAL_2;
wire [12 : 0] MUX_adcCore_iseqFsm_jj_delay_count$write_1__VAL_1;
wire [10 : 0] MUX_adcCore_sampF_rRdPtr_rsCounter$write_1__VAL_1,
MUX_adcCore_sampF_rWrPtr_rsCounter$write_1__VAL_1;
wire [3 : 0] MUX_adcCore_colGate_ovrRecover$write_1__VAL_2,
MUX_adcCore_spiI_iPos$write_1__VAL_1;
wire [2 : 0] MUX_adcCore_colGate_timeMesg$write_1__VAL_1,
MUX_adcCore_spiI_dPos$write_1__VAL_1;
wire [1 : 0] MUX_adcCore_colGate_syncMesg$write_1__VAL_1,
MUX_wci_wslv_respF_c_r$write_1__VAL_1,
MUX_wci_wslv_respF_c_r$write_1__VAL_2,
MUX_wsiM_reqFifo_c_r$write_1__VAL_1,
MUX_wsiM_reqFifo_c_r$write_1__VAL_2;
wire MUX_adcCore_colGate_dwellFails$write_1__SEL_1,
MUX_adcCore_colGate_sampF$enq_1__SEL_1,
MUX_adcCore_reqF$enq_1__SEL_1,
MUX_adcCore_spiI_sdoR_1$wset_1__VAL_1,
MUX_adcCore_spiI_sdoR_1$wset_1__VAL_2,
MUX_adcCore_spiI_xmt_d$write_1__SEL_2,
MUX_splitReadInFlight$write_1__PSEL_1,
MUX_wci_wslv_illegalEdge$write_1__SEL_1,
MUX_wci_wslv_illegalEdge$write_1__VAL_1,
MUX_wci_wslv_respF_q_0$write_1__SEL_2,
MUX_wci_wslv_respF_q_1$write_1__SEL_2,
MUX_wci_wslv_respF_x_wire$wset_1__SEL_1,
MUX_wci_wslv_respF_x_wire$wset_1__SEL_2,
MUX_wsiM_reqFifo_q_0$write_1__SEL_2,
MUX_wsiM_reqFifo_q_1$write_1__SEL_2;
// remaining internal signals
reg [63 : 0] v__h3700, v__h3875, v__h4019, v__h62856, v__h63353;
reg [31 : 0] IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190,
x1_data__h14584;
reg CASE_adcCore_colGate_avgPhase_0b1_0_1_1_1_2_1__ETC__q2;
wire [63 : 0] wti_nowReq_BITS_63_TO_0__q1;
wire [31 : 0] IF_adcCore_sampF_rRdPtr_rsCounter_48_BIT_0_55__ETC___d1412,
IF_adcCore_sampF_rRdPtr_rsCounter_48_BIT_0_55__ETC___d1413,
IF_adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86__ETC___d1295,
IF_adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86__ETC___d1410,
IF_fcAdc_grayCounter_rsCounter_60_BIT_0_67_OR__ETC___d1407,
IF_fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_ETC___d1408,
adcStatusLs__h63134,
avgDataBW__h14897,
d_data__h14984,
rdat__h63337,
rdat__h63416,
rdat__h63498,
rdat__h63518;
wire [17 : 0] x__h15249,
x__h15259,
x__h15325,
x__h15399,
x__h15409,
x__h7511,
y__h15410,
y__h15412,
y__h8916;
wire [11 : 0] x_burstLength__h61970;
wire [10 : 0] adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1247,
x__h17578,
x__h19880,
x__h23307,
x_dReadBin__h21693,
x_sReadBin__h21690,
y__h18465,
y__h20767;
wire [9 : 0] x2__h23276;
wire [7 : 0] adcCore_spiI_reqS_BITS_15_TO_8__q3,
adcCore_spiI_reqS_BITS_7_TO_0__q4;
wire NOT_adcCore_sampF_rRdPtr_rsCounter_48_EQ_adcCo_ETC___d1051,
NOT_adcCore_spiI_reqF_head_wrapped__read__71_E_ETC___d814,
adcCore_colGate_operatePW_whas__24_AND_adcCore_ETC___d379,
adcCore_colGate_operatePW_whas__24_AND_adcCore_ETC___d390,
adcCore_colGate_sampF_RDY_first__93_AND_NOT_ad_ETC___d750,
adcCore_colGate_uprollCnt_93_EQ_adcCore_colGat_ETC___d1303,
adcCore_iseqFsm_abort_whas__69_AND_adcCore_ise_ETC___d941,
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1242,
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1243,
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1244,
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1245,
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1246,
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1249,
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1262,
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1263,
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1264,
adcCore_sampF_rRdPtr_rsCounter_48_BIT_0_55_XOR_ETC___d1344,
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1236,
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1237,
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1238,
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1239,
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1240,
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1241,
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1257,
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1260,
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1261,
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1304,
adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86_XOR_ETC___d1289,
adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1230,
adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1231,
adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1232,
adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1233,
adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1234,
adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1235,
adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1256,
adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1258,
adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1259,
adcCore_spiI_reqF_head_wrapped_crossed__63_EQ__ETC___d919,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1219,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1220,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1221,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1222,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1223,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1224,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1225,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1226,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1227,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1228,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1229,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1250,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1252,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1253,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1254,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1266,
fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_fc_ETC___d1343,
wci_wslv_reqF_i_notEmpty__4_AND_IF_wci_wslv_re_ETC___d1098,
z__h18509,
z__h18516,
z__h18523,
z__h18530,
z__h18537,
z__h18544,
z__h18551,
z__h18558,
z__h18565,
z__h20811,
z__h20818,
z__h20825,
z__h20832,
z__h20839,
z__h20846,
z__h20853,
z__h20860,
z__h20867,
z__h7531,
z__h7538,
z__h7545,
z__h7552,
z__h7559,
z__h7566,
z__h7573,
z__h7580,
z__h7587,
z__h7594,
z__h7601,
z__h7608,
z__h7615,
z__h7622,
z__h7629,
z__h7636;
// oscillator and gates for output clock CLK_adc_sclk
assign CLK_adc_sclk = adcCore_spiI_cd$CLK_OUT ;
assign CLK_GATE_adc_sclk = 1'b1 ;
// oscillator and gates for output clock CLK_adc_sclkn
assign CLK_adc_sclkn = adcCore_spiI_cinv$CLK_OUT ;
assign CLK_GATE_adc_sclkn = 1'b1 ;
// oscillator and gates for output clock CLK_adcSdrClk
assign CLK_adcSdrClk = CLK_adc_clock ;
assign CLK_GATE_adcSdrClk = 1'd1 ;
// output resets
assign RST_N_adc_rst = adcCore_spiI_slowReset$OUT_RST ;
assign RST_N_adcSdrRst = adcCore_sdrRst$OUT_RST ;
// value method wciS0_sResp
assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ;
// value method wciS0_sData
assign wciS0_SData = wci_wslv_respF_q_0[31:0] ;
// value method wciS0_sThreadBusy
assign wciS0_SThreadBusy =
wci_wslv_reqF_countReg > 2'd1 || wci_wslv_isReset_isInReset ;
// value method wciS0_sFlag
assign wciS0_SFlag = { 1'd1, wci_wslv_sFlagReg } ;
// value method wtiS0_sThreadBusy
assign wtiS0_SThreadBusy = wti_isReset_isInReset ;
// value method wtiS0_sReset_n
assign wtiS0_SReset_n = !wti_isReset_isInReset && wti_operateD ;
// value method wsiM0_mCmd
assign wsiM0_MCmd = wsiM_sThreadBusy_d ? 3'd0 : wsiM_reqFifo_q_0[60:58] ;
// value method wsiM0_mReqLast
assign wsiM0_MReqLast = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[57] ;
// value method wsiM0_mBurstPrecise
assign wsiM0_MBurstPrecise = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[56] ;
// value method wsiM0_mBurstLength
assign wsiM0_MBurstLength =
wsiM_sThreadBusy_d ? 12'd0 : wsiM_reqFifo_q_0[55:44] ;
// value method wsiM0_mData
assign wsiM0_MData = wsiM_reqFifo_q_0[43:12] ;
// value method wsiM0_mByteEn
assign wsiM0_MByteEn = wsiM_reqFifo_q_0[11:8] ;
// value method wsiM0_mReqInfo
assign wsiM0_MReqInfo = wsiM_sThreadBusy_d ? 8'd0 : wsiM_reqFifo_q_0[7:0] ;
// value method wsiM0_mReset_n
assign wsiM0_MReset_n = !wsiM_isReset_isInReset && wsiM_operateD ;
// value method adc_oe
assign adc_oe = 1'd1 ;
// value method adc_sclkgate
assign adc_sclkgate = adcCore_spiI_cGate ;
// value method adc_resetp
assign adc_resetp = adcCore_adcRst ;
// value method adc_sen
assign adc_sen = adcCore_spiI_csbR ;
// value method adc_smosi
assign adc_smosi = adcCore_spiI_sdoR ;
// submodule adcCore_acquireD
SyncRegister #(.width(32'd1),
.init(1'd0)) adcCore_acquireD(.sCLK(wciS0_Clk),
.dCLK(CLK_adc_clock),
.sRST(wciS0_MReset_n),
.sD_IN(adcCore_acquireD$sD_IN),
.sEN(adcCore_acquireD$sEN),
.dD_OUT(adcCore_acquireD$dD_OUT),
.sRDY(adcCore_acquireD$sRDY));
// submodule adcCore_averageD
SyncRegister #(.width(32'd1),
.init(1'd0)) adcCore_averageD(.sCLK(wciS0_Clk),
.dCLK(CLK_adc_clock),
.sRST(wciS0_MReset_n),
.sD_IN(adcCore_averageD$sD_IN),
.sEN(adcCore_averageD$sEN),
.dD_OUT(adcCore_averageD$dD_OUT),
.sRDY(adcCore_averageD$sRDY));
// submodule adcCore_colGate_sampF
arSRLFIFOD #(.width(32'd39),
.l2depth(32'd4)) adcCore_colGate_sampF(.CLK(CLK_adc_clock),
.RST_N(adcCore_sdrRst$OUT_RST),
.D_IN(adcCore_colGate_sampF$D_IN),
.CLR(adcCore_colGate_sampF$CLR),
.DEQ(adcCore_colGate_sampF$DEQ),
.ENQ(adcCore_colGate_sampF$ENQ),
.D_OUT(adcCore_colGate_sampF$D_OUT),
.EMPTY_N(adcCore_colGate_sampF$EMPTY_N),
.FULL_N(adcCore_colGate_sampF$FULL_N));
// submodule adcCore_maxBurstLengthR
SyncRegister #(.width(32'd16),
.init(16'd0)) adcCore_maxBurstLengthR(.sCLK(wciS0_Clk),
.dCLK(CLK_adc_clock),
.sRST(wciS0_MReset_n),
.sD_IN(adcCore_maxBurstLengthR$sD_IN),
.sEN(adcCore_maxBurstLengthR$sEN),
.dD_OUT(adcCore_maxBurstLengthR$dD_OUT),
.sRDY(adcCore_maxBurstLengthR$sRDY));
// submodule adcCore_operateD
SyncRegister #(.width(32'd1),
.init(1'd0)) adcCore_operateD(.sCLK(wciS0_Clk),
.dCLK(CLK_adc_clock),
.sRST(wciS0_MReset_n),
.sD_IN(adcCore_operateD$sD_IN),
.sEN(adcCore_operateD$sEN),
.dD_OUT(adcCore_operateD$dD_OUT),
.sRDY(adcCore_operateD$sRDY));
// submodule adcCore_reqF
FIFO2 #(.width(32'd17), .guarded(32'd1)) adcCore_reqF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(adcCore_reqF$D_IN),
.ENQ(adcCore_reqF$ENQ),
.DEQ(adcCore_reqF$DEQ),
.CLR(adcCore_reqF$CLR),
.D_OUT(adcCore_reqF$D_OUT),
.FULL_N(adcCore_reqF$FULL_N),
.EMPTY_N(adcCore_reqF$EMPTY_N));
// submodule adcCore_sampCC
SyncRegister #(.width(32'd32),
.init(32'd0)) adcCore_sampCC(.sCLK(CLK_adc_clock),
.dCLK(wciS0_Clk),
.sRST(adcCore_sdrRst$OUT_RST),
.sD_IN(adcCore_sampCC$sD_IN),
.sEN(adcCore_sampCC$sEN),
.dD_OUT(adcCore_sampCC$dD_OUT),
.sRDY(adcCore_sampCC$sRDY));
// submodule adcCore_sampF_memory
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd10),
.DATA_WIDTH(32'd39),
.MEMSIZE(11'd1024)) adcCore_sampF_memory(.CLKA(CLK_adc_clock),
.CLKB(wciS0_Clk),
.ADDRA(adcCore_sampF_memory$ADDRA),
.ADDRB(adcCore_sampF_memory$ADDRB),
.DIA(adcCore_sampF_memory$DIA),
.DIB(adcCore_sampF_memory$DIB),
.WEA(adcCore_sampF_memory$WEA),
.WEB(adcCore_sampF_memory$WEB),
.ENA(adcCore_sampF_memory$ENA),
.ENB(adcCore_sampF_memory$ENB),
.DOA(),
.DOB(adcCore_sampF_memory$DOB));
// submodule adcCore_sdrRst
SyncResetA #(.RSTDELAY(32'd1)) adcCore_sdrRst(.CLK(CLK_adc_clock),
.IN_RST(wciS0_MReset_n),
.OUT_RST(adcCore_sdrRst$OUT_RST));
// submodule adcCore_spiI_cd
ClockDiv #(.width(32'd3),
.lower(32'd0),
.upper(32'd7),
.offset(32'd0)) adcCore_spiI_cd(.CLK_IN(wciS0_Clk),
.RST(wciS0_MReset_n),
.PREEDGE(adcCore_spiI_cd$PREEDGE),
.CLK_OUT(adcCore_spiI_cd$CLK_OUT));
// submodule adcCore_spiI_cinv
ClockInverter adcCore_spiI_cinv(.CLK_IN(adcCore_spiI_cd$CLK_OUT),
.PREEDGE(),
.CLK_OUT(adcCore_spiI_cinv$CLK_OUT));
// submodule adcCore_spiI_reqF_dCombinedReset
ResetEither adcCore_spiI_reqF_dCombinedReset(.A_RST(adcCore_spiI_slowReset$OUT_RST),
.B_RST(adcCore_spiI_reqF_dCrossedsReset$OUT_RST),
.RST_OUT(adcCore_spiI_reqF_dCombinedReset$RST_OUT));
// submodule adcCore_spiI_reqF_dCrossedsReset
SyncReset0 adcCore_spiI_reqF_dCrossedsReset(.IN_RST(wciS0_MReset_n),
.OUT_RST(adcCore_spiI_reqF_dCrossedsReset$OUT_RST));
// submodule adcCore_spiI_reqF_dInReset
ResetToBool adcCore_spiI_reqF_dInReset(.RST(adcCore_spiI_reqF_dCombinedReset$RST_OUT),
.VAL(adcCore_spiI_reqF_dInReset$VAL));
// submodule adcCore_spiI_reqF_sCombinedReset
ResetEither adcCore_spiI_reqF_sCombinedReset(.A_RST(wciS0_MReset_n),
.B_RST(adcCore_spiI_reqF_sCrosseddReset$OUT_RST),
.RST_OUT(adcCore_spiI_reqF_sCombinedReset$RST_OUT));
// submodule adcCore_spiI_reqF_sCrosseddReset
SyncReset0 adcCore_spiI_reqF_sCrosseddReset(.IN_RST(adcCore_spiI_slowReset$OUT_RST),
.OUT_RST(adcCore_spiI_reqF_sCrosseddReset$OUT_RST));
// submodule adcCore_spiI_reqF_sInReset
ResetToBool adcCore_spiI_reqF_sInReset(.RST(adcCore_spiI_reqF_sCombinedReset$RST_OUT),
.VAL(adcCore_spiI_reqF_sInReset$VAL));
// submodule adcCore_spiI_respF_dCombinedReset
ResetEither adcCore_spiI_respF_dCombinedReset(.A_RST(wciS0_MReset_n),
.B_RST(adcCore_spiI_respF_dCrossedsReset$OUT_RST),
.RST_OUT(adcCore_spiI_respF_dCombinedReset$RST_OUT));
// submodule adcCore_spiI_respF_dCrossedsReset
SyncReset0 adcCore_spiI_respF_dCrossedsReset(.IN_RST(adcCore_spiI_slowReset$OUT_RST),
.OUT_RST(adcCore_spiI_respF_dCrossedsReset$OUT_RST));
// submodule adcCore_spiI_respF_dInReset
ResetToBool adcCore_spiI_respF_dInReset(.RST(adcCore_spiI_respF_dCombinedReset$RST_OUT),
.VAL(adcCore_spiI_respF_dInReset$VAL));
// submodule adcCore_spiI_respF_sCombinedReset
ResetEither adcCore_spiI_respF_sCombinedReset(.A_RST(adcCore_spiI_slowReset$OUT_RST),
.B_RST(adcCore_spiI_respF_sCrosseddReset$OUT_RST),
.RST_OUT(adcCore_spiI_respF_sCombinedReset$RST_OUT));
// submodule adcCore_spiI_respF_sCrosseddReset
SyncReset0 adcCore_spiI_respF_sCrosseddReset(.IN_RST(wciS0_MReset_n),
.OUT_RST(adcCore_spiI_respF_sCrosseddReset$OUT_RST));
// submodule adcCore_spiI_respF_sInReset
ResetToBool adcCore_spiI_respF_sInReset(.RST(adcCore_spiI_respF_sCombinedReset$RST_OUT),
.VAL(adcCore_spiI_respF_sInReset$VAL));
// submodule adcCore_spiI_slowReset
SyncResetA #(.RSTDELAY(32'd1)) adcCore_spiI_slowReset(.CLK(adcCore_spiI_cd$CLK_OUT),
.IN_RST(wciS0_MReset_n),
.OUT_RST(adcCore_spiI_slowReset$OUT_RST));
// submodule adcCore_statsCC
SyncRegister #(.width(32'd128),
.init(128'd0)) adcCore_statsCC(.sCLK(CLK_adc_clock),
.dCLK(wciS0_Clk),
.sRST(adcCore_sdrRst$OUT_RST),
.sD_IN(adcCore_statsCC$sD_IN),
.sEN(adcCore_statsCC$sEN),
.dD_OUT(adcCore_statsCC$dD_OUT),
.sRDY(adcCore_statsCC$sRDY));
// submodule fcAdc_testRst
SyncResetA #(.RSTDELAY(32'd1)) fcAdc_testRst(.CLK(CLK_adcCaptureClk),
.IN_RST(wciS0_MReset_n),
.OUT_RST(fcAdc_testRst$OUT_RST));
// submodule wci_wslv_reqF
SizedFIFO #(.p1width(32'd72),
.p2depth(32'd3),
.p3cntr_width(32'd1),
.guarded(32'd1)) wci_wslv_reqF(.RST(wciS0_MReset_n),
.CLK(wciS0_Clk),
.D_IN(wci_wslv_reqF$D_IN),
.ENQ(wci_wslv_reqF$ENQ),
.DEQ(wci_wslv_reqF$DEQ),
.CLR(wci_wslv_reqF$CLR),
.D_OUT(wci_wslv_reqF$D_OUT),
.FULL_N(),
.EMPTY_N(wci_wslv_reqF$EMPTY_N));
// rule RL_get_adc_resp
assign CAN_FIRE_RL_get_adc_resp =
adcCore_spiI_respF_head_wrapped !=
adcCore_spiI_respF_tail_wrapped &&
!adcCore_spiI_respF_dInReset$VAL &&
adcCore_spiI_cd$PREEDGE &&
(!splitReadInFlight || wci_wslv_respF_c_r != 2'd2) ;
// rule RL_wci_cfwr
assign WILL_FIRE_RL_wci_cfwr =
wci_wslv_respF_c_r != 2'd2 &&
wci_wslv_reqF_i_notEmpty__4_AND_IF_wci_wslv_re_ETC___d1098 &&
wci_wslv_wci_cfwr_pw$whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_wslv_ctl_op_start
assign WILL_FIRE_RL_wci_wslv_ctl_op_start =
wci_wslv_reqF$EMPTY_N && wci_wslv_wci_ctrl_pw$whas &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_ctrl_EiI
assign WILL_FIRE_RL_wci_ctrl_EiI =
wci_wslv_wci_ctrl_pw$whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd0 &&
wci_wslv_reqF$D_OUT[36:34] == 3'd0 ;
// rule RL_wci_ctrl_IsO
assign WILL_FIRE_RL_wci_ctrl_IsO =
wci_wslv_wci_ctrl_pw$whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd1 &&
wci_wslv_reqF$D_OUT[36:34] == 3'd1 ;
// rule RL_wci_ctrl_OrE
assign WILL_FIRE_RL_wci_ctrl_OrE =
wci_wslv_wci_ctrl_pw$whas &&
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
wci_wslv_cState == 3'd2 &&
wci_wslv_reqF$D_OUT[36:34] == 3'd3 ;
// rule RL_adcCore_advance_spi_request
assign WILL_FIRE_RL_adcCore_advance_spi_request =
adcCore_spiI_reqF_head_wrapped_crossed__63_EQ__ETC___d919 &&
adcCore_reqF$EMPTY_N &&
adcCore_iseqFsm_abort_whas__69_AND_adcCore_ise_ETC___d941 &&
!adcCore_iseqFsm_start_reg ;
// rule RL_adcCore_colGate_send_timestamp_mesg
assign WILL_FIRE_RL_adcCore_colGate_send_timestamp_mesg =
adcCore_colGate_sampF$FULL_N && adcCore_operateD$dD_OUT &&
adcCore_colGate_timeMesg != 3'd0 ;
// rule RL_adcCore_colGate_send_sync_mesg
assign WILL_FIRE_RL_adcCore_colGate_send_sync_mesg =
adcCore_colGate_sampF$FULL_N && adcCore_operateD$dD_OUT &&
adcCore_colGate_syncMesg != 2'd0 &&
adcCore_colGate_timeMesg == 3'd0 ;
// rule RL_adcCore_colGate_capture_collect
assign WILL_FIRE_RL_adcCore_colGate_capture_collect =
adcCore_colGate_sampF$FULL_N &&
adcCore_colGate_operatePW_whas__24_AND_adcCore_ETC___d390 ;
// rule RL_adcCore_colGate_form_avg4_sample
assign WILL_FIRE_RL_adcCore_colGate_form_avg4_sample =
CASE_adcCore_colGate_avgPhase_0b1_0_1_1_1_2_1__ETC__q2 &&
adcCore_operateD$dD_OUT ;
// rule RL_adcCore_colGate_overrun_recovery
assign WILL_FIRE_RL_adcCore_colGate_overrun_recovery =
(adcCore_colGate_ovrRecover != 4'd15 ||
adcCore_colGate_sampF$FULL_N) &&
adcCore_colGate_operatePW_whas__24_AND_adcCore_ETC___d379 &&
adcCore_colGate_ovrRecover != 4'd0 &&
!WILL_FIRE_RL_adcCore_colGate_send_sync_mesg ;
// rule RL_adcCore_colGate_count_dropped_samples
assign WILL_FIRE_RL_adcCore_colGate_count_dropped_samples =
adcCore_colGate_operatePW_whas__24_AND_adcCore_ETC___d379 &&
adcCore_colGate_sampActive &&
!adcCore_colGate_sampF$FULL_N &&
!WILL_FIRE_RL_adcCore_colGate_overrun_recovery ;
// rule RL_adcCore_colGate_count_dwells
assign WILL_FIRE_RL_adcCore_colGate_count_dwells =
adcCore_operateD$dD_OUT && adcCore_acquireD$dD_OUT &&
!adcCore_colGate_collectD ;
// rule RL_adcCore_spiI_start_cs
assign WILL_FIRE_RL_adcCore_spiI_start_cs =
NOT_adcCore_spiI_reqF_head_wrapped__read__71_E_ETC___d814 &&
!adcCore_spiI_xmt_i &&
!adcCore_spiI_xmt_d ;
// rule RL_adcCore_spiI_send_d
assign WILL_FIRE_RL_adcCore_spiI_send_d =
NOT_adcCore_spiI_reqF_head_wrapped__read__71_E_ETC___d814 &&
!adcCore_spiI_reqF_dInReset$VAL &&
adcCore_spiI_xmt_d ;
// rule RL_adcCore_spiI_send_i
assign WILL_FIRE_RL_adcCore_spiI_send_i =
NOT_adcCore_spiI_reqF_head_wrapped__read__71_E_ETC___d814 &&
!adcCore_spiI_reqF_dInReset$VAL &&
adcCore_spiI_xmt_i ;
// rule RL_adcCore_spiI_reqF_deq_update_head
assign WILL_FIRE_RL_adcCore_spiI_reqF_deq_update_head =
!adcCore_spiI_reqF_dInReset$VAL &&
MUX_adcCore_spiI_xmt_d$write_1__SEL_2 ;
// rule RL_adcCore_spiI_respF_enq_update_tail
assign WILL_FIRE_RL_adcCore_spiI_respF_enq_update_tail =
!adcCore_spiI_respF_sInReset$VAL &&
adcCore_spiI_respF_enq_pw$whas ;
// rule RL_adcCore_spiI_respF_deq_update_head
assign WILL_FIRE_RL_adcCore_spiI_respF_deq_update_head =
!adcCore_spiI_respF_dInReset$VAL &&
MUX_splitReadInFlight$write_1__PSEL_1 ;
// rule RL_adcCore_iseqFsm_action_np
assign WILL_FIRE_RL_adcCore_iseqFsm_action_np =
!adcCore_iseqFsm_jj_delay_count[12] &&
(adcCore_iseqFsm_state_mkFSMstate == 4'd3 ||
adcCore_iseqFsm_state_mkFSMstate == 4'd4) ;
// rule RL_adcCore_iseqFsm_action_l141c9
assign WILL_FIRE_RL_adcCore_iseqFsm_action_l141c9 =
adcCore_spiI_reqF_head_wrapped_crossed__63_EQ__ETC___d919 &&
adcCore_iseqFsm_jj_delay_count[12] &&
(adcCore_iseqFsm_state_mkFSMstate == 4'd3 ||
adcCore_iseqFsm_state_mkFSMstate == 4'd4) ;
// rule RL_adcCore_iseqFsm_action_l142c9
assign WILL_FIRE_RL_adcCore_iseqFsm_action_l142c9 =
adcCore_spiI_reqF_head_wrapped_crossed__63_EQ__ETC___d919 &&
adcCore_iseqFsm_state_mkFSMstate == 4'd5 ;
// rule RL_adcCore_iseqFsm_action_l143c9
assign WILL_FIRE_RL_adcCore_iseqFsm_action_l143c9 =
adcCore_spiI_reqF_head_wrapped_crossed__63_EQ__ETC___d919 &&
adcCore_iseqFsm_state_mkFSMstate == 4'd6 ;
// rule RL_adcCore_iseqFsm_action_l144c9
assign WILL_FIRE_RL_adcCore_iseqFsm_action_l144c9 =
adcCore_spiI_reqF_head_wrapped_crossed__63_EQ__ETC___d919 &&
adcCore_iseqFsm_state_mkFSMstate == 4'd7 ;
// rule RL_adcCore_iseqFsm_action_l145c9
assign WILL_FIRE_RL_adcCore_iseqFsm_action_l145c9 =
adcCore_spiI_reqF_head_wrapped_crossed__63_EQ__ETC___d919 &&
adcCore_iseqFsm_state_mkFSMstate == 4'd8 ;
// rule RL_adcCore_iseqFsm_action_l146c9
assign WILL_FIRE_RL_adcCore_iseqFsm_action_l146c9 =
adcCore_spiI_reqF_head_wrapped_crossed__63_EQ__ETC___d919 &&
adcCore_iseqFsm_state_mkFSMstate == 4'd9 ;
// rule RL_adcCore_spiI_reqF_enq_update_tail
assign WILL_FIRE_RL_adcCore_spiI_reqF_enq_update_tail =
!adcCore_spiI_reqF_sInReset$VAL &&
adcCore_spiI_reqF_enq_pw$whas ;
// rule RL_wci_cfrd
assign CAN_FIRE_RL_wci_cfrd =
wci_wslv_reqF$EMPTY_N &&
(wci_wslv_reqF$D_OUT[43:42] != 2'b01 || adcCore_reqF$FULL_N) &&
(wci_wslv_reqF$D_OUT[43:42] == 2'b01 ||
wci_wslv_respF_c_r != 2'd2) &&
wci_wslv_wci_cfrd_pw$whas ;
assign WILL_FIRE_RL_wci_cfrd =
CAN_FIRE_RL_wci_cfrd && !WILL_FIRE_RL_wci_wslv_ctl_op_start &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
// rule RL_wci_wslv_ctl_op_complete
assign WILL_FIRE_RL_wci_wslv_ctl_op_complete =
wci_wslv_respF_c_r != 2'd2 && wci_wslv_ctlOpActive &&
wci_wslv_ctlAckReg ;
// rule RL_wci_wslv_respF_incCtr
assign WILL_FIRE_RL_wci_wslv_respF_incCtr =
((wci_wslv_respF_c_r == 2'd0) ?
wci_wslv_respF_x_wire$whas :
wci_wslv_respF_c_r != 2'd1 || wci_wslv_respF_x_wire$whas) &&
wci_wslv_respF_enqueueing$whas &&
!(wci_wslv_respF_c_r != 2'd0) ;
// rule RL_wci_wslv_respF_decCtr
assign WILL_FIRE_RL_wci_wslv_respF_decCtr =
wci_wslv_respF_c_r != 2'd0 && !wci_wslv_respF_enqueueing$whas ;
// rule RL_wci_wslv_respF_both
assign WILL_FIRE_RL_wci_wslv_respF_both =
((wci_wslv_respF_c_r == 2'd1) ?
wci_wslv_respF_x_wire$whas :
wci_wslv_respF_c_r != 2'd2 || wci_wslv_respF_x_wire$whas) &&
wci_wslv_respF_c_r != 2'd0 &&
wci_wslv_respF_enqueueing$whas ;
// rule RL_adcCore_iseqFsm_fsm_start
assign WILL_FIRE_RL_adcCore_iseqFsm_fsm_start =
adcCore_iseqFsm_abort_whas__69_AND_adcCore_ise_ETC___d941 &&
adcCore_iseqFsm_start_reg ;
// rule RL_adcCore_iseqFsm_action_l138c12
assign WILL_FIRE_RL_adcCore_iseqFsm_action_l138c12 =
adcCore_iseqFsm_start_wire$whas &&
(adcCore_iseqFsm_state_mkFSMstate == 4'd0 ||
adcCore_iseqFsm_state_mkFSMstate == 4'd10) ;
// rule RL_adcCore_iseqFsm_idle_l137c3
assign WILL_FIRE_RL_adcCore_iseqFsm_idle_l137c3 =
!adcCore_iseqFsm_start_wire$whas &&
adcCore_iseqFsm_state_mkFSMstate == 4'd10 ;
// rule RL_wsiM_reqFifo_deq
assign WILL_FIRE_RL_wsiM_reqFifo_deq =
wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ;
// rule RL_wsiM_reqFifo_incCtr
assign WILL_FIRE_RL_wsiM_reqFifo_incCtr =
((wsiM_reqFifo_c_r == 2'd0) ?
wsiM_reqFifo_enqueueing$whas :
wsiM_reqFifo_c_r != 2'd1 || wsiM_reqFifo_enqueueing$whas) &&
wsiM_reqFifo_enqueueing$whas &&
!WILL_FIRE_RL_wsiM_reqFifo_deq ;
// rule RL_wsiM_reqFifo_decCtr
assign WILL_FIRE_RL_wsiM_reqFifo_decCtr =
WILL_FIRE_RL_wsiM_reqFifo_deq && !wsiM_reqFifo_enqueueing$whas ;
// rule RL_wsiM_reqFifo_both
assign WILL_FIRE_RL_wsiM_reqFifo_both =
((wsiM_reqFifo_c_r == 2'd1) ?
wsiM_reqFifo_enqueueing$whas :
wsiM_reqFifo_c_r != 2'd2 || wsiM_reqFifo_enqueueing$whas) &&
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_enqueueing$whas ;
// inputs to muxes for submodule ports
assign MUX_adcCore_colGate_dwellFails$write_1__SEL_1 =
WILL_FIRE_RL_adcCore_colGate_count_dropped_samples &&
adcCore_colGate_ovrRecover == 4'd0 ;
assign MUX_adcCore_colGate_sampF$enq_1__SEL_1 =
WILL_FIRE_RL_adcCore_colGate_overrun_recovery &&
adcCore_colGate_ovrRecover == 4'd15 ;
assign MUX_adcCore_reqF$enq_1__SEL_1 =
WILL_FIRE_RL_wci_cfwr &&
(wci_wslv_reqF$D_OUT[43:42] == 2'b0 &&
wci_wslv_reqF$D_OUT[39:32] == 8'h28 ||
wci_wslv_reqF$D_OUT[43:42] == 2'b01) ;
assign MUX_adcCore_spiI_xmt_d$write_1__SEL_2 =
WILL_FIRE_RL_adcCore_spiI_send_d && adcCore_spiI_dPos == 3'd0 ;
assign MUX_splitReadInFlight$write_1__PSEL_1 =
CAN_FIRE_RL_get_adc_resp &&
!WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign MUX_wci_wslv_illegalEdge$write_1__SEL_1 =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 &&
wci_wslv_cState != 3'd3 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd2 && wci_wslv_cState != 3'd2 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd3 && wci_wslv_cState != 3'd3 &&
wci_wslv_cState != 3'd2 &&
wci_wslv_cState != 3'd1 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd4 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd5 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd6 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd7) ;
assign MUX_wci_wslv_respF_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_c_r == 2'd0 ;
assign MUX_wci_wslv_respF_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_c_r == 2'd1 ;
assign MUX_wci_wslv_respF_x_wire$wset_1__SEL_1 =
MUX_splitReadInFlight$write_1__PSEL_1 && splitReadInFlight ;
assign MUX_wci_wslv_respF_x_wire$wset_1__SEL_2 =
WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[43:42] != 2'b01 ;
assign MUX_wsiM_reqFifo_q_0$write_1__SEL_2 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ;
assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 =
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ;
assign MUX_adcCore_colGate_dropCount$write_1__VAL_1 =
adcCore_colGate_dropCount + 32'd1 ;
assign MUX_adcCore_colGate_dwellFails$write_1__VAL_1 =
adcCore_colGate_dwellFails + 32'd1 ;
assign MUX_adcCore_colGate_dwellStarts$write_1__VAL_1 =
adcCore_colGate_dwellStarts + 32'd1 ;
assign MUX_adcCore_colGate_ovrRecover$write_1__VAL_2 =
adcCore_colGate_ovrRecover - 4'd1 ;
assign MUX_adcCore_colGate_sampCount$write_1__VAL_1 =
adcCore_colGate_sampCount + 32'd1 ;
assign MUX_adcCore_colGate_sampF$enq_1__VAL_1 =
{ 7'd31, adcCore_colGate_sampDataWD } ;
assign MUX_adcCore_colGate_sampF$enq_1__VAL_2 =
{ 2'd2,
adcCore_colGate_timeMesg == 3'h1,
4'd15,
x1_data__h14584 } ;
assign MUX_adcCore_colGate_sampF$enq_1__VAL_3 =
{ 2'd0,
adcCore_colGate_uprollCnt_93_EQ_adcCore_colGat_ETC___d1303,
4'd15,
d_data__h14984 } ;
assign MUX_adcCore_colGate_syncMesg$write_1__VAL_1 =
adcCore_colGate_syncMesg - 2'd1 ;
assign MUX_adcCore_colGate_timeMesg$write_1__VAL_1 =
adcCore_colGate_timeMesg - 3'd1 ;
assign MUX_adcCore_colGate_uprollCnt$write_1__VAL_2 =
adcCore_colGate_uprollCnt_93_EQ_adcCore_colGat_ETC___d1303 ?
16'd0 :
adcCore_colGate_uprollCnt + 16'd1 ;
assign MUX_adcCore_iseqFsm_jj_delay_count$write_1__VAL_1 =
{ adcCore_iseqFsm_jj_delay_count[11:0], 1'd0 } ;
assign MUX_adcCore_reqF$enq_1__VAL_1 =
{ wci_wslv_reqF$D_OUT[43:42] == 2'b0 && wci_wslv_reqF$D_OUT[31],
(wci_wslv_reqF$D_OUT[43:42] == 2'b0) ?
wci_wslv_reqF$D_OUT[15:0] :
{ wci_wslv_reqF$D_OUT[41:34], wci_wslv_reqF$D_OUT[7:0] } } ;
assign MUX_adcCore_reqF$enq_1__VAL_2 =
{ 1'd1, wci_wslv_reqF$D_OUT[41:34], 8'd0 } ;
assign MUX_adcCore_sampF_rRdPtr_rsCounter$write_1__VAL_1 =
(~adcCore_sampF_rRdPtr_rsCounter[IF_adcCore_sampF_rRdPtr_rsCounter_48_BIT_0_55__ETC___d1412[3:0]]) ?
adcCore_sampF_rRdPtr_rsCounter | x__h19880 :
adcCore_sampF_rRdPtr_rsCounter & y__h20767 ;
assign MUX_adcCore_sampF_rWrPtr_rsCounter$write_1__VAL_1 =
(~adcCore_sampF_rWrPtr_rsCounter[IF_adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86__ETC___d1410[3:0]]) ?
adcCore_sampF_rWrPtr_rsCounter | x__h17578 :
adcCore_sampF_rWrPtr_rsCounter & y__h18465 ;
assign MUX_adcCore_spiI_dPos$write_1__VAL_1 =
(adcCore_spiI_dPos == 3'd0) ?
adcCore_spiI_dPos :
adcCore_spiI_dPos - 3'd1 ;
assign MUX_adcCore_spiI_iPos$write_1__VAL_1 =
(adcCore_spiI_iPos == 4'd0) ?
adcCore_spiI_iPos :
adcCore_spiI_iPos - 4'd1 ;
assign MUX_adcCore_spiI_reqS$write_1__VAL_1 =
(adcCore_reqF$D_OUT[16] && !adcCore_readMode) ?
17'd1 :
((!adcCore_reqF$D_OUT[16] && adcCore_readMode) ?
17'd0 :
adcCore_reqF$D_OUT) ;
assign MUX_adcCore_spiI_sdoR_1$wset_1__VAL_1 =
adcCore_spiI_reqS_BITS_15_TO_8__q3[adcCore_spiI_iPos[2:0]] ;
assign MUX_adcCore_spiI_sdoR_1$wset_1__VAL_2 =
adcCore_spiI_reqS_BITS_7_TO_0__q4[adcCore_spiI_dPos] ;
assign MUX_fcAdc_grayCounter_rsCounter$write_1__VAL_1 =
(~fcAdc_grayCounter_rsCounter[IF_fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_ETC___d1408[4:0]]) ?
fcAdc_grayCounter_rsCounter | x__h7511 :
fcAdc_grayCounter_rsCounter & y__h8916 ;
assign MUX_oneKHz_value$write_1__VAL_1 =
(oneKHz_value == 18'd99999) ? 18'd0 : oneKHz_value + 18'd1 ;
assign MUX_wci_wslv_illegalEdge$write_1__VAL_1 =
wci_wslv_reqF$D_OUT[36:34] != 3'd4 &&
wci_wslv_reqF$D_OUT[36:34] != 3'd5 &&
wci_wslv_reqF$D_OUT[36:34] != 3'd6 ;
assign MUX_wci_wslv_respF_c_r$write_1__VAL_1 = wci_wslv_respF_c_r + 2'd1 ;
assign MUX_wci_wslv_respF_c_r$write_1__VAL_2 = wci_wslv_respF_c_r - 2'd1 ;
assign MUX_wci_wslv_respF_q_0$write_1__VAL_1 =
(wci_wslv_respF_c_r == 2'd1) ?
MUX_wci_wslv_respF_q_0$write_1__VAL_2 :
wci_wslv_respF_q_1 ;
always@(MUX_wci_wslv_respF_x_wire$wset_1__SEL_1 or
MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 or
MUX_wci_wslv_respF_x_wire$wset_1__SEL_2 or
MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 or
WILL_FIRE_RL_wci_wslv_ctl_op_complete or
MUX_wci_wslv_respF_x_wire$wset_1__VAL_3 or WILL_FIRE_RL_wci_cfwr)
begin
case (1'b1) // synopsys parallel_case
MUX_wci_wslv_respF_x_wire$wset_1__SEL_1:
MUX_wci_wslv_respF_q_0$write_1__VAL_2 =
MUX_wci_wslv_respF_x_wire$wset_1__VAL_1;
MUX_wci_wslv_respF_x_wire$wset_1__SEL_2:
MUX_wci_wslv_respF_q_0$write_1__VAL_2 =
MUX_wci_wslv_respF_x_wire$wset_1__VAL_2;
WILL_FIRE_RL_wci_wslv_ctl_op_complete:
MUX_wci_wslv_respF_q_0$write_1__VAL_2 =
MUX_wci_wslv_respF_x_wire$wset_1__VAL_3;
WILL_FIRE_RL_wci_cfwr:
MUX_wci_wslv_respF_q_0$write_1__VAL_2 = 34'h1C0DE4201;
default: MUX_wci_wslv_respF_q_0$write_1__VAL_2 =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign MUX_wci_wslv_respF_q_1$write_1__VAL_1 =
(wci_wslv_respF_c_r == 2'd2) ?
MUX_wci_wslv_respF_q_0$write_1__VAL_2 :
34'h0AAAAAAAA ;
assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 =
{ 26'd16777216, adcCore_spiI_respS } ;
assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 = { 2'd1, rdat__h63337 } ;
assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_3 =
wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ;
assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ;
assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ;
assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 =
(wsiM_reqFifo_c_r == 2'd1) ?
MUX_wsiM_reqFifo_q_0$write_1__VAL_2 :
wsiM_reqFifo_q_1 ;
assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 =
{ 3'd1,
adcCore_sampF_memory$DOB[36],
1'd0,
x_burstLength__h61970,
adcCore_sampF_memory$DOB[31:0],
10'd960,
adcCore_sampF_memory$DOB[38:37] } ;
assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 =
(wsiM_reqFifo_c_r == 2'd2) ?
MUX_wsiM_reqFifo_q_0$write_1__VAL_2 :
61'h00000AAAAAAAAA00 ;
// inlined wires
assign wci_wslv_wciReq$wget =
{ wciS0_MCmd,
wciS0_MAddrSpace,
wciS0_MByteEn,
wciS0_MAddr,
wciS0_MData } ;
assign wci_wslv_wciReq$whas = 1'd1 ;
assign wci_wslv_respF_x_wire$wget = MUX_wci_wslv_respF_q_0$write_1__VAL_2 ;
assign wci_wslv_respF_x_wire$whas =
MUX_splitReadInFlight$write_1__PSEL_1 && splitReadInFlight ||
WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[43:42] != 2'b01 ||
WILL_FIRE_RL_wci_wslv_ctl_op_complete ||
WILL_FIRE_RL_wci_cfwr ;
assign wci_wslv_wEdge$wget = wci_wslv_reqF$D_OUT[36:34] ;
assign wci_wslv_wEdge$whas = WILL_FIRE_RL_wci_wslv_ctl_op_start ;
assign wci_wslv_sFlagReg_1$wget = 1'd1 ;
assign wci_wslv_sFlagReg_1$whas = sFlagState ;
assign wci_wslv_ctlAckReg_1$wget = 1'd1 ;
assign wci_wslv_ctlAckReg_1$whas =
WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO ||
WILL_FIRE_RL_wci_ctrl_EiI ;
assign wci_wci_Es_mCmd_w$wget = wciS0_MCmd ;
assign wci_wci_Es_mCmd_w$whas = 1'd1 ;
assign wci_wci_Es_mAddrSpace_w$wget = wciS0_MAddrSpace ;
assign wci_wci_Es_mAddrSpace_w$whas = 1'd1 ;
assign wci_wci_Es_mByteEn_w$wget = wciS0_MByteEn ;
assign wci_wci_Es_mByteEn_w$whas = 1'd1 ;
assign wci_wci_Es_mAddr_w$wget = wciS0_MAddr ;
assign wci_wci_Es_mAddr_w$whas = 1'd1 ;
assign wci_wci_Es_mData_w$wget = wciS0_MData ;
assign wci_wci_Es_mData_w$whas = 1'd1 ;
assign fcAdc_pulseAction_1$wget = 1'd1 ;
assign fcAdc_pulseAction_1$whas = oneKHz_value == 18'd99999 ;
assign adcCore_colGate_average_dw$wget = 1'd1 ;
assign adcCore_colGate_average_dw$whas = adcCore_averageD$dD_OUT ;
assign adcCore_colGate_sampActive_1$wget = 1'd1 ;
assign adcCore_colGate_sampActive_1$whas = 1'd1 ;
assign adcCore_colGate_nowW$wget = wti_nowReq[63:0] ;
assign adcCore_colGate_nowW$whas = 1'd1 ;
assign adcCore_colGate_maxBurstLenW$wget = adcCore_maxBurstLengthR$dD_OUT ;
assign adcCore_colGate_maxBurstLenW$whas = 1'd1 ;
assign adcCore_colGate_sampDataW$wget = adcCore_samp ;
assign adcCore_colGate_sampDataW$whas = 1'd1 ;
assign adcCore_operateDReg_1$wget = 1'd1 ;
assign adcCore_operateDReg_1$whas = wci_wslv_cState == 3'd2 ;
assign adcCore_acquireDReg_1$wget = 1'd1 ;
assign adcCore_acquireDReg_1$whas =
wci_wslv_cState == 3'd2 && !adcControl[0] &&
(!adcControl[3] || overflowCountD == 32'd0) ;
assign adcCore_averageDReg_1$wget = 1'd1 ;
assign adcCore_averageDReg_1$whas =
wci_wslv_cState == 3'd2 && adcControl[4] ;
assign adcCore_sampF_wDataIn$wget = adcCore_colGate_sampF$D_OUT ;
assign adcCore_sampF_wDataIn$whas = adcCore_sampF_pwEnqueue$whas ;
assign adcCore_sampF_wDataOut$wget = adcCore_sampF_memory$DOB ;
assign adcCore_sampF_wDataOut$whas = 1'd1 ;
assign adcCore_nowW$wget = wti_nowReq[63:0] ;
assign adcCore_nowW$whas = 1'd1 ;
assign adcCore_spiI_cGate_1$wget = 1'd1 ;
assign adcCore_spiI_cGate_1$whas =
WILL_FIRE_RL_adcCore_spiI_send_i ||
WILL_FIRE_RL_adcCore_spiI_send_d ;
assign adcCore_spiI_sdoR_1$wget =
WILL_FIRE_RL_adcCore_spiI_send_i ?
MUX_adcCore_spiI_sdoR_1$wset_1__VAL_1 :
MUX_adcCore_spiI_sdoR_1$wset_1__VAL_2 ;
assign adcCore_spiI_sdoR_1$whas = adcCore_spiI_cGate_1$whas ;
assign adcCore_spiI_csbR_1$wget = 1'b0 ;
assign adcCore_spiI_csbR_1$whas = adcCore_spiI_cGate_1$whas ;
assign adcCore_spiI_doResp_1$wget = adcCore_spiI_reqS[16] ;
assign adcCore_spiI_doResp_1$whas = MUX_adcCore_spiI_xmt_d$write_1__SEL_2 ;
assign adcCore_adcRst_1$wget = 1'd1 ;
assign adcCore_adcRst_1$whas =
adcCore_iseqFsm_state_mkFSMstate == 4'd1 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l138c12 ;
assign adcCore_iseqFsm_start_wire$wget = 1'd1 ;
assign adcCore_iseqFsm_start_wire$whas =
WILL_FIRE_RL_adcCore_iseqFsm_fsm_start ||
adcCore_iseqFsm_start_reg_1 && !adcCore_iseqFsm_state_fired ;
assign adcCore_iseqFsm_start_reg_1_1$wget = 1'd1 ;
assign adcCore_iseqFsm_start_reg_1_1$whas =
adcCore_iseqFsm_start_wire$whas ;
assign adcCore_iseqFsm_abort$wget = 1'b0 ;
assign adcCore_iseqFsm_abort$whas = 1'b0 ;
assign adcCore_iseqFsm_state_fired_1$wget = 1'd1 ;
assign adcCore_iseqFsm_state_fired_1$whas =
adcCore_iseqFsm_state_set_pw$whas ;
assign wti_wtiReq$wget = 67'h0 ;
assign wti_wtiReq$whas = 1'b0 ;
assign wti_operateD_1$wget = 1'b0 ;
assign wti_operateD_1$whas = 1'b0 ;
assign wsiM_reqFifo_x_wire$wget = MUX_wsiM_reqFifo_q_0$write_1__VAL_2 ;
assign wsiM_reqFifo_x_wire$whas = wsiM_reqFifo_enqueueing$whas ;
assign wsiM_operateD_1$wget = 1'd1 ;
assign wsiM_operateD_1$whas = wci_wslv_cState == 3'd2 ;
assign wsiM_peerIsReady_1$wget = 1'd1 ;
assign wsiM_peerIsReady_1$whas = wsiM0_SReset_n ;
assign wci_wslv_reqF_r_enq$whas = wci_wslv_wciReq$wget[71:69] != 3'd0 ;
assign wci_wslv_reqF_r_deq$whas =
WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_wslv_ctl_op_start ;
assign wci_wslv_reqF_r_clr$whas = 1'b0 ;
assign wci_wslv_respF_enqueueing$whas =
MUX_splitReadInFlight$write_1__PSEL_1 && splitReadInFlight ||
WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[43:42] != 2'b01 ||
WILL_FIRE_RL_wci_cfwr ||
WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_c_r != 2'd0 ;
assign wci_wslv_sThreadBusy_pw$whas = 1'b0 ;
assign wci_wslv_wci_cfwr_pw$whas =
wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] &&
wci_wslv_reqF$D_OUT[71:69] == 3'd1 ;
assign wci_wslv_wci_cfrd_pw$whas =
wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] &&
wci_wslv_reqF$D_OUT[71:69] == 3'd2 ;
assign wci_wslv_wci_ctrl_pw$whas =
wci_wslv_reqF$EMPTY_N && !wci_wslv_reqF$D_OUT[68] &&
wci_wslv_reqF$D_OUT[71:69] == 3'd2 ;
assign fcAdc_grayCounter_pwIncrement$whas = 1'd1 ;
assign fcAdc_grayCounter_pwDecrement$whas = 1'b0 ;
assign oneKHz_incAction$whas = 1'd1 ;
assign oneKHz_decAction$whas = 1'b0 ;
assign adcCore_colGate_operatePW$whas = adcCore_operateD$dD_OUT ;
assign adcCore_colGate_collectPW$whas = adcCore_acquireD$dD_OUT ;
assign adcCore_colGate_enaSyncPW$whas = 1'b0 ;
assign adcCore_colGate_enaTimestampPW$whas = 1'b0 ;
assign adcCore_sampF_rWrPtr_pwIncrement$whas =
adcCore_sampF_pwEnqueue$whas ;
assign adcCore_sampF_rWrPtr_pwDecrement$whas = 1'b0 ;
assign adcCore_sampF_rRdPtr_pwIncrement$whas =
adcCore_sampF_pwDequeue$whas ;
assign adcCore_sampF_rRdPtr_pwDecrement$whas = 1'b0 ;
assign adcCore_sampF_pwDequeue$whas =
NOT_adcCore_sampF_rRdPtr_rsCounter_48_EQ_adcCo_ETC___d1051 &&
wci_wslv_cState != 3'd2 ||
wsiM_reqFifo_enqueueing$whas ;
assign adcCore_sampF_pwEnqueue$whas =
adcCore_colGate_sampF$EMPTY_N &&
adcCore_colGate_sampF_RDY_first__93_AND_NOT_ad_ETC___d750 ;
assign adcCore_spiI_reqF_enq_pw$whas =
WILL_FIRE_RL_adcCore_advance_spi_request ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l146c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l145c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l144c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l143c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l142c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l141c9 ;
assign adcCore_spiI_reqF_deq_pw$whas =
MUX_adcCore_spiI_xmt_d$write_1__SEL_2 ;
assign adcCore_spiI_reqF_sClear_pw$whas = 1'b0 ;
assign adcCore_spiI_reqF_dClear_pw$whas = 1'b0 ;
assign adcCore_spiI_reqF_deq_happened$whas = 1'b0 ;
assign adcCore_spiI_respF_enq_pw$whas =
adcCore_spiI_respF_head_wrapped ==
adcCore_spiI_respF_tail_wrapped &&
!adcCore_spiI_respF_sInReset$VAL &&
adcCore_spiI_doResp ;
assign adcCore_spiI_respF_deq_pw$whas =
MUX_splitReadInFlight$write_1__PSEL_1 ;
assign adcCore_spiI_respF_sClear_pw$whas = 1'b0 ;
assign adcCore_spiI_respF_dClear_pw$whas = 1'b0 ;
assign adcCore_spiI_respF_deq_happened$whas = 1'b0 ;
assign adcCore_iseqFsm_state_set_pw$whas =
WILL_FIRE_RL_adcCore_iseqFsm_idle_l137c3 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l146c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l145c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l144c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l143c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l142c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l141c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_np ||
adcCore_iseqFsm_state_mkFSMstate == 4'd2 ||
adcCore_iseqFsm_state_mkFSMstate == 4'd1 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l138c12 ;
assign adcCore_iseqFsm_state_overlap_pw$whas = 1'b0 ;
assign wsiM_reqFifo_enqueueing$whas =
wsiM_reqFifo_c_r != 2'd2 &&
NOT_adcCore_sampF_rRdPtr_rsCounter_48_EQ_adcCo_ETC___d1051 &&
wci_wslv_cState == 3'd2 ;
assign wsiM_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsiM_reqFifo_deq ;
assign wsiM_sThreadBusy_pw$whas = wsiM0_SThreadBusy ;
assign fcAdc_grayCounter_wdCounterCrossing$wget =
fcAdc_grayCounter_rsCounter ;
assign adcCore_sampF_rWrPtr_wdCounterCrossing$wget =
adcCore_sampF_rWrPtr_rsCounter ;
assign adcCore_sampF_rRdPtr_wdCounterCrossing$wget =
adcCore_sampF_rRdPtr_rsCounter ;
assign adcCore_spiI_sdiWs$wget = adcCore_spiI_sdiP ;
assign wsiM_extStatusW$wget =
{ wsiM_pMesgCount, wsiM_iMesgCount, wsiM_tBusyCount } ;
// register adcControl
assign adcControl$D_IN = wci_wslv_reqF$D_OUT[31:0] ;
assign adcControl$EN =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[43:42] == 2'b0 &&
wci_wslv_reqF$D_OUT[39:32] == 8'h0C ;
// register adcCore_acquireDReg
assign adcCore_acquireDReg$D_IN = adcCore_acquireDReg_1$whas ;
assign adcCore_acquireDReg$EN = 1'd1 ;
// register adcCore_adcRst
assign adcCore_adcRst$D_IN = adcCore_adcRst_1$whas ;
assign adcCore_adcRst$EN = 1'd1 ;
// register adcCore_averageDReg
assign adcCore_averageDReg$D_IN = adcCore_averageDReg_1$whas ;
assign adcCore_averageDReg$EN = 1'd1 ;
// register adcCore_colGate_avgEven
assign adcCore_colGate_avgEven$D_IN =
(adcCore_colGate_avgPhase == 2'd0) ? x__h15325 : x__h15249 ;
assign adcCore_colGate_avgEven$EN =
WILL_FIRE_RL_adcCore_colGate_form_avg4_sample &&
(adcCore_colGate_avgPhase == 2'd0 ||
adcCore_colGate_avgPhase == 2'd1) ;
// register adcCore_colGate_avgOdd
assign adcCore_colGate_avgOdd$D_IN =
(adcCore_colGate_avgPhase == 2'd2) ? x__h15325 : x__h15399 ;
assign adcCore_colGate_avgOdd$EN =
WILL_FIRE_RL_adcCore_colGate_form_avg4_sample &&
(adcCore_colGate_avgPhase == 2'd2 ||
adcCore_colGate_avgPhase == 2'd3) ;
// register adcCore_colGate_avgPhase
assign adcCore_colGate_avgPhase$D_IN = adcCore_colGate_avgPhase + 2'd1 ;
assign adcCore_colGate_avgPhase$EN =
WILL_FIRE_RL_adcCore_colGate_form_avg4_sample ;
// register adcCore_colGate_collectD
assign adcCore_colGate_collectD$D_IN =
adcCore_operateD$dD_OUT && adcCore_acquireD$dD_OUT ;
assign adcCore_colGate_collectD$EN = 1'b1 ;
// register adcCore_colGate_dropCount
assign adcCore_colGate_dropCount$D_IN =
WILL_FIRE_RL_adcCore_colGate_count_dropped_samples ?
MUX_adcCore_colGate_dropCount$write_1__VAL_1 :
32'd0 ;
assign adcCore_colGate_dropCount$EN =
WILL_FIRE_RL_adcCore_colGate_count_dropped_samples ||
!adcCore_operateD$dD_OUT ;
// register adcCore_colGate_dwellFails
assign adcCore_colGate_dwellFails$D_IN =
MUX_adcCore_colGate_dwellFails$write_1__SEL_1 ?
MUX_adcCore_colGate_dwellFails$write_1__VAL_1 :
32'd0 ;
assign adcCore_colGate_dwellFails$EN =
WILL_FIRE_RL_adcCore_colGate_count_dropped_samples &&
adcCore_colGate_ovrRecover == 4'd0 ||
!adcCore_operateD$dD_OUT ;
// register adcCore_colGate_dwellStarts
assign adcCore_colGate_dwellStarts$D_IN =
WILL_FIRE_RL_adcCore_colGate_count_dwells ?
MUX_adcCore_colGate_dwellStarts$write_1__VAL_1 :
32'd0 ;
assign adcCore_colGate_dwellStarts$EN =
WILL_FIRE_RL_adcCore_colGate_count_dwells ||
!adcCore_operateD$dD_OUT ;
// register adcCore_colGate_ovrRecover
always@(MUX_adcCore_colGate_dwellFails$write_1__SEL_1 or
WILL_FIRE_RL_adcCore_colGate_overrun_recovery or
MUX_adcCore_colGate_ovrRecover$write_1__VAL_2 or
adcCore_operateD$dD_OUT)
begin
case (1'b1) // synopsys parallel_case
MUX_adcCore_colGate_dwellFails$write_1__SEL_1:
adcCore_colGate_ovrRecover$D_IN = 4'd15;
WILL_FIRE_RL_adcCore_colGate_overrun_recovery:
adcCore_colGate_ovrRecover$D_IN =
MUX_adcCore_colGate_ovrRecover$write_1__VAL_2;
!adcCore_operateD$dD_OUT: adcCore_colGate_ovrRecover$D_IN = 4'd0;
default: adcCore_colGate_ovrRecover$D_IN =
4'b1010 /* unspecified value */ ;
endcase
end
assign adcCore_colGate_ovrRecover$EN =
WILL_FIRE_RL_adcCore_colGate_count_dropped_samples &&
adcCore_colGate_ovrRecover == 4'd0 ||
WILL_FIRE_RL_adcCore_colGate_overrun_recovery ||
!adcCore_operateD$dD_OUT ;
// register adcCore_colGate_sampActive
assign adcCore_colGate_sampActive$D_IN = 1'b1 ;
assign adcCore_colGate_sampActive$EN = 1'd1 ;
// register adcCore_colGate_sampActiveD
assign adcCore_colGate_sampActiveD$D_IN =
adcCore_operateD$dD_OUT && adcCore_colGate_sampActive ;
assign adcCore_colGate_sampActiveD$EN = 1'b1 ;
// register adcCore_colGate_sampCount
assign adcCore_colGate_sampCount$D_IN =
WILL_FIRE_RL_adcCore_colGate_capture_collect ?
MUX_adcCore_colGate_sampCount$write_1__VAL_1 :
32'd0 ;
assign adcCore_colGate_sampCount$EN =
WILL_FIRE_RL_adcCore_colGate_capture_collect ||
!adcCore_operateD$dD_OUT ;
// register adcCore_colGate_sampDataWD
assign adcCore_colGate_sampDataWD$D_IN = adcCore_samp ;
assign adcCore_colGate_sampDataWD$EN =
MUX_adcCore_colGate_dwellFails$write_1__SEL_1 ;
// register adcCore_colGate_syncMesg
assign adcCore_colGate_syncMesg$D_IN =
WILL_FIRE_RL_adcCore_colGate_send_sync_mesg ?
MUX_adcCore_colGate_syncMesg$write_1__VAL_1 :
2'd0 ;
assign adcCore_colGate_syncMesg$EN =
WILL_FIRE_RL_adcCore_colGate_send_sync_mesg ||
!adcCore_operateD$dD_OUT ;
// register adcCore_colGate_timeMesg
assign adcCore_colGate_timeMesg$D_IN =
WILL_FIRE_RL_adcCore_colGate_send_timestamp_mesg ?
MUX_adcCore_colGate_timeMesg$write_1__VAL_1 :
3'd0 ;
assign adcCore_colGate_timeMesg$EN =
WILL_FIRE_RL_adcCore_colGate_send_timestamp_mesg ||
!adcCore_operateD$dD_OUT ;
// register adcCore_colGate_uprollCnt
assign adcCore_colGate_uprollCnt$D_IN =
WILL_FIRE_RL_adcCore_colGate_capture_collect ?
MUX_adcCore_colGate_uprollCnt$write_1__VAL_2 :
16'd0 ;
assign adcCore_colGate_uprollCnt$EN =
WILL_FIRE_RL_adcCore_colGate_overrun_recovery &&
adcCore_colGate_ovrRecover == 4'd15 ||
WILL_FIRE_RL_adcCore_colGate_capture_collect ||
!adcCore_operateD$dD_OUT ;
// register adcCore_iobA
assign adcCore_iobA$D_IN = adc_da_i ;
assign adcCore_iobA$EN = 1'd1 ;
// register adcCore_iobB
assign adcCore_iobB$D_IN = adc_db_i ;
assign adcCore_iobB$EN = 1'd1 ;
// register adcCore_iseqFsm_jj_delay_count
assign adcCore_iseqFsm_jj_delay_count$D_IN =
WILL_FIRE_RL_adcCore_iseqFsm_action_np ?
MUX_adcCore_iseqFsm_jj_delay_count$write_1__VAL_1 :
13'd1 ;
assign adcCore_iseqFsm_jj_delay_count$EN =
WILL_FIRE_RL_adcCore_iseqFsm_action_np ||
adcCore_iseqFsm_state_mkFSMstate == 4'd2 ;
// register adcCore_iseqFsm_start_reg
assign adcCore_iseqFsm_start_reg$D_IN = 1'd0 ;
assign adcCore_iseqFsm_start_reg$EN =
WILL_FIRE_RL_adcCore_iseqFsm_fsm_start ;
// register adcCore_iseqFsm_start_reg_1
assign adcCore_iseqFsm_start_reg_1$D_IN = adcCore_iseqFsm_start_wire$whas ;
assign adcCore_iseqFsm_start_reg_1$EN = 1'd1 ;
// register adcCore_iseqFsm_state_can_overlap
assign adcCore_iseqFsm_state_can_overlap$D_IN =
adcCore_iseqFsm_state_set_pw$whas ||
adcCore_iseqFsm_state_can_overlap ;
assign adcCore_iseqFsm_state_can_overlap$EN = 1'd1 ;
// register adcCore_iseqFsm_state_fired
assign adcCore_iseqFsm_state_fired$D_IN =
adcCore_iseqFsm_state_set_pw$whas ;
assign adcCore_iseqFsm_state_fired$EN = 1'd1 ;
// register adcCore_iseqFsm_state_mkFSMstate
always@(WILL_FIRE_RL_adcCore_iseqFsm_idle_l137c3 or
WILL_FIRE_RL_adcCore_iseqFsm_action_l138c12 or
adcCore_iseqFsm_state_mkFSMstate or
WILL_FIRE_RL_adcCore_iseqFsm_action_np or
WILL_FIRE_RL_adcCore_iseqFsm_action_l141c9 or
WILL_FIRE_RL_adcCore_iseqFsm_action_l142c9 or
WILL_FIRE_RL_adcCore_iseqFsm_action_l143c9 or
WILL_FIRE_RL_adcCore_iseqFsm_action_l144c9 or
WILL_FIRE_RL_adcCore_iseqFsm_action_l145c9 or
WILL_FIRE_RL_adcCore_iseqFsm_action_l146c9)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_adcCore_iseqFsm_idle_l137c3:
adcCore_iseqFsm_state_mkFSMstate$D_IN = 4'd0;
WILL_FIRE_RL_adcCore_iseqFsm_action_l138c12:
adcCore_iseqFsm_state_mkFSMstate$D_IN = 4'd1;
adcCore_iseqFsm_state_mkFSMstate == 4'd1:
adcCore_iseqFsm_state_mkFSMstate$D_IN = 4'd2;
adcCore_iseqFsm_state_mkFSMstate == 4'd2:
adcCore_iseqFsm_state_mkFSMstate$D_IN = 4'd3;
WILL_FIRE_RL_adcCore_iseqFsm_action_np:
adcCore_iseqFsm_state_mkFSMstate$D_IN = 4'd4;
WILL_FIRE_RL_adcCore_iseqFsm_action_l141c9:
adcCore_iseqFsm_state_mkFSMstate$D_IN = 4'd5;
WILL_FIRE_RL_adcCore_iseqFsm_action_l142c9:
adcCore_iseqFsm_state_mkFSMstate$D_IN = 4'd6;
WILL_FIRE_RL_adcCore_iseqFsm_action_l143c9:
adcCore_iseqFsm_state_mkFSMstate$D_IN = 4'd7;
WILL_FIRE_RL_adcCore_iseqFsm_action_l144c9:
adcCore_iseqFsm_state_mkFSMstate$D_IN = 4'd8;
WILL_FIRE_RL_adcCore_iseqFsm_action_l145c9:
adcCore_iseqFsm_state_mkFSMstate$D_IN = 4'd9;
WILL_FIRE_RL_adcCore_iseqFsm_action_l146c9:
adcCore_iseqFsm_state_mkFSMstate$D_IN = 4'd10;
default: adcCore_iseqFsm_state_mkFSMstate$D_IN =
4'b1010 /* unspecified value */ ;
endcase
end
assign adcCore_iseqFsm_state_mkFSMstate$EN =
WILL_FIRE_RL_adcCore_iseqFsm_idle_l137c3 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l138c12 ||
adcCore_iseqFsm_state_mkFSMstate == 4'd1 ||
adcCore_iseqFsm_state_mkFSMstate == 4'd2 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_np ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l141c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l142c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l143c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l144c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l145c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l146c9 ;
// register adcCore_operateDReg
assign adcCore_operateDReg$D_IN = wci_wslv_cState == 3'd2 ;
assign adcCore_operateDReg$EN = 1'd1 ;
// register adcCore_readMode
assign adcCore_readMode$D_IN = adcCore_reqF$D_OUT[16] && !adcCore_readMode ;
assign adcCore_readMode$EN =
WILL_FIRE_RL_adcCore_advance_spi_request &&
(adcCore_reqF$D_OUT[16] && !adcCore_readMode ||
!adcCore_reqF$D_OUT[16] && adcCore_readMode) ;
// register adcCore_samp
assign adcCore_samp$D_IN = { 2'b0, adcCore_iobB, 2'b0, adcCore_iobA } ;
assign adcCore_samp$EN = 1'd1 ;
// register adcCore_sampF_rRdPtr_rdCounter
assign adcCore_sampF_rRdPtr_rdCounter$D_IN =
adcCore_sampF_rRdPtr_rdCounterPre ;
assign adcCore_sampF_rRdPtr_rdCounter$EN = 1'd1 ;
// register adcCore_sampF_rRdPtr_rdCounterPre
assign adcCore_sampF_rRdPtr_rdCounterPre$D_IN =
adcCore_sampF_rRdPtr_rsCounter ;
assign adcCore_sampF_rRdPtr_rdCounterPre$EN = 1'd1 ;
// register adcCore_sampF_rRdPtr_rsCounter
assign adcCore_sampF_rRdPtr_rsCounter$D_IN =
MUX_adcCore_sampF_rRdPtr_rsCounter$write_1__VAL_1 ;
assign adcCore_sampF_rRdPtr_rsCounter$EN = adcCore_sampF_pwDequeue$whas ;
// register adcCore_sampF_rWrPtr_rdCounter
assign adcCore_sampF_rWrPtr_rdCounter$D_IN =
adcCore_sampF_rWrPtr_rdCounterPre ;
assign adcCore_sampF_rWrPtr_rdCounter$EN = 1'd1 ;
// register adcCore_sampF_rWrPtr_rdCounterPre
assign adcCore_sampF_rWrPtr_rdCounterPre$D_IN =
adcCore_sampF_rWrPtr_rsCounter ;
assign adcCore_sampF_rWrPtr_rdCounterPre$EN = 1'd1 ;
// register adcCore_sampF_rWrPtr_rsCounter
assign adcCore_sampF_rWrPtr_rsCounter$D_IN =
MUX_adcCore_sampF_rWrPtr_rsCounter$write_1__VAL_1 ;
assign adcCore_sampF_rWrPtr_rsCounter$EN = adcCore_sampF_pwEnqueue$whas ;
// register adcCore_spiI_cGate
assign adcCore_spiI_cGate$D_IN = adcCore_spiI_cGate_1$whas ;
assign adcCore_spiI_cGate$EN = 1'd1 ;
// register adcCore_spiI_cap
assign adcCore_spiI_cap$D_IN = adcCore_spiI_sdiP ;
assign adcCore_spiI_cap$EN = MUX_adcCore_spiI_xmt_d$write_1__SEL_2 ;
// register adcCore_spiI_cap_1
assign adcCore_spiI_cap_1$D_IN = adcCore_spiI_sdiP ;
assign adcCore_spiI_cap_1$EN =
WILL_FIRE_RL_adcCore_spiI_send_d && adcCore_spiI_dPos == 3'd1 ;
// register adcCore_spiI_cap_2
assign adcCore_spiI_cap_2$D_IN = adcCore_spiI_sdiP ;
assign adcCore_spiI_cap_2$EN =
WILL_FIRE_RL_adcCore_spiI_send_d && adcCore_spiI_dPos == 3'd2 ;
// register adcCore_spiI_cap_3
assign adcCore_spiI_cap_3$D_IN = adcCore_spiI_sdiP ;
assign adcCore_spiI_cap_3$EN =
WILL_FIRE_RL_adcCore_spiI_send_d && adcCore_spiI_dPos == 3'd3 ;
// register adcCore_spiI_cap_4
assign adcCore_spiI_cap_4$D_IN = adcCore_spiI_sdiP ;
assign adcCore_spiI_cap_4$EN =
WILL_FIRE_RL_adcCore_spiI_send_d && adcCore_spiI_dPos == 3'd4 ;
// register adcCore_spiI_cap_5
assign adcCore_spiI_cap_5$D_IN = adcCore_spiI_sdiP ;
assign adcCore_spiI_cap_5$EN =
WILL_FIRE_RL_adcCore_spiI_send_d && adcCore_spiI_dPos == 3'd5 ;
// register adcCore_spiI_cap_6
assign adcCore_spiI_cap_6$D_IN = adcCore_spiI_sdiP ;
assign adcCore_spiI_cap_6$EN =
WILL_FIRE_RL_adcCore_spiI_send_d && adcCore_spiI_dPos == 3'd6 ;
// register adcCore_spiI_cap_7
assign adcCore_spiI_cap_7$D_IN = adcCore_spiI_sdiP ;
assign adcCore_spiI_cap_7$EN =
WILL_FIRE_RL_adcCore_spiI_send_d && adcCore_spiI_dPos == 3'd7 ;
// register adcCore_spiI_csbR
assign adcCore_spiI_csbR$D_IN = !adcCore_spiI_cGate_1$whas ;
assign adcCore_spiI_csbR$EN = 1'd1 ;
// register adcCore_spiI_dPos
assign adcCore_spiI_dPos$D_IN =
WILL_FIRE_RL_adcCore_spiI_send_d ?
MUX_adcCore_spiI_dPos$write_1__VAL_1 :
3'h7 ;
assign adcCore_spiI_dPos$EN =
WILL_FIRE_RL_adcCore_spiI_send_d ||
WILL_FIRE_RL_adcCore_spiI_start_cs ;
// register adcCore_spiI_doResp
assign adcCore_spiI_doResp$D_IN =
MUX_adcCore_spiI_xmt_d$write_1__SEL_2 && adcCore_spiI_reqS[16] ;
assign adcCore_spiI_doResp$EN = 1'd1 ;
// register adcCore_spiI_iPos
assign adcCore_spiI_iPos$D_IN =
WILL_FIRE_RL_adcCore_spiI_send_i ?
MUX_adcCore_spiI_iPos$write_1__VAL_1 :
4'h7 ;
assign adcCore_spiI_iPos$EN =
WILL_FIRE_RL_adcCore_spiI_send_i ||
WILL_FIRE_RL_adcCore_spiI_start_cs ;
// register adcCore_spiI_reqF_head_wrapped
assign adcCore_spiI_reqF_head_wrapped$D_IN =
WILL_FIRE_RL_adcCore_spiI_reqF_deq_update_head &&
!adcCore_spiI_reqF_head_wrapped ;
assign adcCore_spiI_reqF_head_wrapped$EN =
WILL_FIRE_RL_adcCore_spiI_reqF_deq_update_head ||
adcCore_spiI_reqF_dInReset$VAL ;
// register adcCore_spiI_reqF_tail_wrapped
assign adcCore_spiI_reqF_tail_wrapped$D_IN =
WILL_FIRE_RL_adcCore_spiI_reqF_enq_update_tail &&
!adcCore_spiI_reqF_tail_wrapped ;
assign adcCore_spiI_reqF_tail_wrapped$EN =
WILL_FIRE_RL_adcCore_spiI_reqF_enq_update_tail ||
adcCore_spiI_reqF_sInReset$VAL ;
// register adcCore_spiI_reqS
always@(WILL_FIRE_RL_adcCore_advance_spi_request or
MUX_adcCore_spiI_reqS$write_1__VAL_1 or
WILL_FIRE_RL_adcCore_iseqFsm_action_l141c9 or
WILL_FIRE_RL_adcCore_iseqFsm_action_l142c9 or
WILL_FIRE_RL_adcCore_iseqFsm_action_l143c9 or
WILL_FIRE_RL_adcCore_iseqFsm_action_l144c9 or
WILL_FIRE_RL_adcCore_iseqFsm_action_l145c9 or
WILL_FIRE_RL_adcCore_iseqFsm_action_l146c9)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_adcCore_advance_spi_request:
adcCore_spiI_reqS$D_IN = MUX_adcCore_spiI_reqS$write_1__VAL_1;
WILL_FIRE_RL_adcCore_iseqFsm_action_l141c9:
adcCore_spiI_reqS$D_IN = 17'd20486;
WILL_FIRE_RL_adcCore_iseqFsm_action_l142c9:
adcCore_spiI_reqS$D_IN = 17'd20788;
WILL_FIRE_RL_adcCore_iseqFsm_action_l143c9:
adcCore_spiI_reqS$D_IN = 17'd21010;
WILL_FIRE_RL_adcCore_iseqFsm_action_l144c9:
adcCore_spiI_reqS$D_IN = 17'd21568;
WILL_FIRE_RL_adcCore_iseqFsm_action_l145c9:
adcCore_spiI_reqS$D_IN = 17'd21776;
WILL_FIRE_RL_adcCore_iseqFsm_action_l146c9:
adcCore_spiI_reqS$D_IN = 17'd25092;
default: adcCore_spiI_reqS$D_IN =
17'b01010101010101010 /* unspecified value */ ;
endcase
end
assign adcCore_spiI_reqS$EN =
WILL_FIRE_RL_adcCore_advance_spi_request ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l141c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l142c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l143c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l144c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l145c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l146c9 ;
// register adcCore_spiI_respF_head_wrapped
assign adcCore_spiI_respF_head_wrapped$D_IN =
WILL_FIRE_RL_adcCore_spiI_respF_deq_update_head &&
!adcCore_spiI_respF_head_wrapped ;
assign adcCore_spiI_respF_head_wrapped$EN =
WILL_FIRE_RL_adcCore_spiI_respF_deq_update_head ||
adcCore_spiI_respF_dInReset$VAL ;
// register adcCore_spiI_respF_tail_wrapped
assign adcCore_spiI_respF_tail_wrapped$D_IN =
WILL_FIRE_RL_adcCore_spiI_respF_enq_update_tail &&
!adcCore_spiI_respF_tail_wrapped ;
assign adcCore_spiI_respF_tail_wrapped$EN =
WILL_FIRE_RL_adcCore_spiI_respF_enq_update_tail ||
adcCore_spiI_respF_sInReset$VAL ;
// register adcCore_spiI_respS
assign adcCore_spiI_respS$D_IN =
{ adcCore_spiI_cap_6,
adcCore_spiI_cap_5,
adcCore_spiI_cap_4,
adcCore_spiI_cap_3,
adcCore_spiI_cap_2,
adcCore_spiI_cap_1,
adcCore_spiI_cap,
adcCore_spiI_sdiP } ;
assign adcCore_spiI_respS$EN = adcCore_spiI_respF_enq_pw$whas ;
// register adcCore_spiI_sdiP
assign adcCore_spiI_sdiP$D_IN = adc_smiso_i ;
assign adcCore_spiI_sdiP$EN = 1'd1 ;
// register adcCore_spiI_sdoR
assign adcCore_spiI_sdoR$D_IN =
adcCore_spiI_cGate_1$whas && adcCore_spiI_sdoR_1$wget ;
assign adcCore_spiI_sdoR$EN = 1'd1 ;
// register adcCore_spiI_xmt_d
assign adcCore_spiI_xmt_d$D_IN =
WILL_FIRE_RL_adcCore_spiI_send_i && adcCore_spiI_iPos == 4'd0 ;
assign adcCore_spiI_xmt_d$EN =
WILL_FIRE_RL_adcCore_spiI_send_d && adcCore_spiI_dPos == 3'd0 ||
WILL_FIRE_RL_adcCore_spiI_send_i ;
// register adcCore_spiI_xmt_i
assign adcCore_spiI_xmt_i$D_IN =
!WILL_FIRE_RL_adcCore_spiI_send_i || adcCore_spiI_iPos != 4'd0 ;
assign adcCore_spiI_xmt_i$EN =
WILL_FIRE_RL_adcCore_spiI_send_i ||
WILL_FIRE_RL_adcCore_spiI_start_cs ;
// register fcAdc_countNow
assign fcAdc_countNow$D_IN =
{ fcAdc_grayCounter_rdCounter[17],
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1219,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1220,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1221,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1252,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1253,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1222,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1266,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1223,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1224,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1254,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1225,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1226,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1250,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1228,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1227,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1229,
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1229 ^
fcAdc_grayCounter_rdCounter[0] } ;
assign fcAdc_countNow$EN = fcAdc_pulseAction ;
// register fcAdc_countPast
assign fcAdc_countPast$D_IN = fcAdc_countNow ;
assign fcAdc_countPast$EN = fcAdc_pulseAction ;
// register fcAdc_frequency
assign fcAdc_frequency$D_IN = fcAdc_countNow - fcAdc_countPast ;
assign fcAdc_frequency$EN = fcAdc_pulseAction ;
// register fcAdc_grayCounter_rdCounter
assign fcAdc_grayCounter_rdCounter$D_IN = fcAdc_grayCounter_rdCounterPre ;
assign fcAdc_grayCounter_rdCounter$EN = 1'd1 ;
// register fcAdc_grayCounter_rdCounterPre
assign fcAdc_grayCounter_rdCounterPre$D_IN = fcAdc_grayCounter_rsCounter ;
assign fcAdc_grayCounter_rdCounterPre$EN = 1'd1 ;
// register fcAdc_grayCounter_rsCounter
assign fcAdc_grayCounter_rsCounter$D_IN =
MUX_fcAdc_grayCounter_rsCounter$write_1__VAL_1 ;
assign fcAdc_grayCounter_rsCounter$EN = 1'b1 ;
// register fcAdc_pulseAction
assign fcAdc_pulseAction$D_IN = oneKHz_value == 18'd99999 ;
assign fcAdc_pulseAction$EN = 1'd1 ;
// register fcAdc_sampleCount
assign fcAdc_sampleCount$D_IN = fcAdc_sampleCount + 16'd1 ;
assign fcAdc_sampleCount$EN = fcAdc_pulseAction ;
// register initOpInFlight
assign initOpInFlight$D_IN = 1'b0 ;
assign initOpInFlight$EN = 1'b0 ;
// register lastOverflowMesg
assign lastOverflowMesg$D_IN = mesgCount ;
assign lastOverflowMesg$EN =
wci_wslv_cState == 3'd2 &&
overflowCountD != adcCore_statsCC$dD_OUT[31:0] ;
// register maxMesgLength
assign maxMesgLength$D_IN = wci_wslv_reqF$D_OUT[31:0] ;
assign maxMesgLength$EN =
WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[43:42] == 2'b0 &&
wci_wslv_reqF$D_OUT[39:32] == 8'h08 ;
// register mesgCount
assign mesgCount$D_IN = mesgCount + 32'd1 ;
assign mesgCount$EN =
wsiM_reqFifo_enqueueing$whas && adcCore_sampF_memory$DOB[36] ;
// register oneKHz_value
assign oneKHz_value$D_IN = MUX_oneKHz_value$write_1__VAL_1 ;
assign oneKHz_value$EN = 1'b1 ;
// register overflowCountD
assign overflowCountD$D_IN = adcCore_statsCC$dD_OUT[31:0] ;
assign overflowCountD$EN = wci_wslv_cState == 3'd2 ;
// register sFlagState
assign sFlagState$D_IN = 1'b0 ;
assign sFlagState$EN = 1'b0 ;
// register spiResp
assign spiResp$D_IN = adcCore_spiI_respS ;
assign spiResp$EN = MUX_splitReadInFlight$write_1__PSEL_1 ;
// register splitReadInFlight
assign splitReadInFlight$D_IN = !MUX_wci_wslv_respF_x_wire$wset_1__SEL_1 ;
assign splitReadInFlight$EN =
MUX_splitReadInFlight$write_1__PSEL_1 && splitReadInFlight ||
WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[43:42] == 2'b01 ;
// register wci_wslv_cEdge
assign wci_wslv_cEdge$D_IN = wci_wslv_reqF$D_OUT[36:34] ;
assign wci_wslv_cEdge$EN = WILL_FIRE_RL_wci_wslv_ctl_op_start ;
// register wci_wslv_cState
assign wci_wslv_cState$D_IN = wci_wslv_nState ;
assign wci_wslv_cState$EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge ;
// register wci_wslv_ctlAckReg
assign wci_wslv_ctlAckReg$D_IN = wci_wslv_ctlAckReg_1$whas ;
assign wci_wslv_ctlAckReg$EN = 1'd1 ;
// register wci_wslv_ctlOpActive
assign wci_wslv_ctlOpActive$D_IN = !WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
assign wci_wslv_ctlOpActive$EN =
WILL_FIRE_RL_wci_wslv_ctl_op_complete ||
WILL_FIRE_RL_wci_wslv_ctl_op_start ;
// register wci_wslv_illegalEdge
assign wci_wslv_illegalEdge$D_IN =
MUX_wci_wslv_illegalEdge$write_1__SEL_1 &&
MUX_wci_wslv_illegalEdge$write_1__VAL_1 ;
assign wci_wslv_illegalEdge$EN =
MUX_wci_wslv_illegalEdge$write_1__SEL_1 ||
WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;
// register wci_wslv_isReset_isInReset
assign wci_wslv_isReset_isInReset$D_IN = 1'd0 ;
assign wci_wslv_isReset_isInReset$EN = wci_wslv_isReset_isInReset ;
// register wci_wslv_nState
always@(wci_wslv_reqF$D_OUT)
begin
case (wci_wslv_reqF$D_OUT[36:34])
3'd0: wci_wslv_nState$D_IN = 3'd1;
3'd1: wci_wslv_nState$D_IN = 3'd2;
3'd2: wci_wslv_nState$D_IN = 3'd3;
default: wci_wslv_nState$D_IN = 3'd0;
endcase
end
assign wci_wslv_nState$EN =
WILL_FIRE_RL_wci_wslv_ctl_op_start &&
(wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState == 3'd0 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd1 &&
(wci_wslv_cState == 3'd1 || wci_wslv_cState == 3'd3) ||
wci_wslv_reqF$D_OUT[36:34] == 3'd2 && wci_wslv_cState == 3'd2 ||
wci_wslv_reqF$D_OUT[36:34] == 3'd3 &&
(wci_wslv_cState == 3'd3 || wci_wslv_cState == 3'd2 ||
wci_wslv_cState == 3'd1)) ;
// register wci_wslv_reqF_countReg
assign wci_wslv_reqF_countReg$D_IN =
(wci_wslv_wciReq$wget[71:69] != 3'd0) ?
wci_wslv_reqF_countReg + 2'd1 :
wci_wslv_reqF_countReg - 2'd1 ;
assign wci_wslv_reqF_countReg$EN =
(wci_wslv_wciReq$wget[71:69] != 3'd0) !=
wci_wslv_reqF_r_deq$whas ;
// register wci_wslv_respF_c_r
assign wci_wslv_respF_c_r$D_IN =
WILL_FIRE_RL_wci_wslv_respF_incCtr ?
MUX_wci_wslv_respF_c_r$write_1__VAL_1 :
MUX_wci_wslv_respF_c_r$write_1__VAL_2 ;
assign wci_wslv_respF_c_r$EN =
WILL_FIRE_RL_wci_wslv_respF_incCtr ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_respF_q_0
always@(WILL_FIRE_RL_wci_wslv_respF_both or
MUX_wci_wslv_respF_q_0$write_1__VAL_1 or
MUX_wci_wslv_respF_q_0$write_1__SEL_2 or
MUX_wci_wslv_respF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_wslv_respF_both:
wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_1;
MUX_wci_wslv_respF_q_0$write_1__SEL_2:
wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wci_wslv_respF_decCtr:
wci_wslv_respF_q_0$D_IN = wci_wslv_respF_q_1;
default: wci_wslv_respF_q_0$D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_wslv_respF_q_0$EN =
WILL_FIRE_RL_wci_wslv_respF_both ||
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_c_r == 2'd0 ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_respF_q_1
always@(WILL_FIRE_RL_wci_wslv_respF_both or
MUX_wci_wslv_respF_q_1$write_1__VAL_1 or
MUX_wci_wslv_respF_q_1$write_1__SEL_2 or
MUX_wci_wslv_respF_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wci_wslv_respF_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wci_wslv_respF_both:
wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_1$write_1__VAL_1;
MUX_wci_wslv_respF_q_1$write_1__SEL_2:
wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2;
WILL_FIRE_RL_wci_wslv_respF_decCtr:
wci_wslv_respF_q_1$D_IN = 34'h0AAAAAAAA;
default: wci_wslv_respF_q_1$D_IN =
34'h2AAAAAAAA /* unspecified value */ ;
endcase
end
assign wci_wslv_respF_q_1$EN =
WILL_FIRE_RL_wci_wslv_respF_both ||
WILL_FIRE_RL_wci_wslv_respF_incCtr &&
wci_wslv_respF_c_r == 2'd1 ||
WILL_FIRE_RL_wci_wslv_respF_decCtr ;
// register wci_wslv_sFlagReg
assign wci_wslv_sFlagReg$D_IN = sFlagState ;
assign wci_wslv_sFlagReg$EN = 1'd1 ;
// register wci_wslv_sThreadBusy_d
assign wci_wslv_sThreadBusy_d$D_IN = 1'b0 ;
assign wci_wslv_sThreadBusy_d$EN = 1'd1 ;
// register wsiM_burstKind
assign wsiM_burstKind$D_IN =
(wsiM_burstKind == 2'd0) ?
(wsiM_reqFifo_q_0[56] ? 2'd1 : 2'd2) :
2'd0 ;
assign wsiM_burstKind$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 &&
(wsiM_burstKind == 2'd0 ||
(wsiM_burstKind == 2'd1 || wsiM_burstKind == 2'd2) &&
wsiM_reqFifo_q_0[57]) ;
// register wsiM_errorSticky
assign wsiM_errorSticky$D_IN = 1'b0 ;
assign wsiM_errorSticky$EN = 1'b0 ;
// register wsiM_iMesgCount
assign wsiM_iMesgCount$D_IN = wsiM_iMesgCount + 32'd1 ;
assign wsiM_iMesgCount$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 &&
wsiM_burstKind == 2'd2 &&
wsiM_reqFifo_q_0[57] ;
// register wsiM_isReset_isInReset
assign wsiM_isReset_isInReset$D_IN = 1'd0 ;
assign wsiM_isReset_isInReset$EN = wsiM_isReset_isInReset ;
// register wsiM_operateD
assign wsiM_operateD$D_IN = wci_wslv_cState == 3'd2 ;
assign wsiM_operateD$EN = 1'd1 ;
// register wsiM_pMesgCount
assign wsiM_pMesgCount$D_IN = wsiM_pMesgCount + 32'd1 ;
assign wsiM_pMesgCount$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 &&
wsiM_burstKind == 2'd1 &&
wsiM_reqFifo_q_0[57] ;
// register wsiM_peerIsReady
assign wsiM_peerIsReady$D_IN = wsiM0_SReset_n ;
assign wsiM_peerIsReady$EN = 1'd1 ;
// register wsiM_reqFifo_c_r
assign wsiM_reqFifo_c_r$D_IN =
WILL_FIRE_RL_wsiM_reqFifo_incCtr ?
MUX_wsiM_reqFifo_c_r$write_1__VAL_1 :
MUX_wsiM_reqFifo_c_r$write_1__VAL_2 ;
assign wsiM_reqFifo_c_r$EN =
WILL_FIRE_RL_wsiM_reqFifo_incCtr ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_reqFifo_q_0
always@(WILL_FIRE_RL_wsiM_reqFifo_both or
MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or
MUX_wsiM_reqFifo_q_0$write_1__SEL_2 or
MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wsiM_reqFifo_both:
wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1;
MUX_wsiM_reqFifo_q_0$write_1__SEL_2:
wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_0$D_IN = wsiM_reqFifo_q_1;
default: wsiM_reqFifo_q_0$D_IN =
61'h0AAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_0$EN =
WILL_FIRE_RL_wsiM_reqFifo_both ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_reqFifo_q_1
always@(WILL_FIRE_RL_wsiM_reqFifo_both or
MUX_wsiM_reqFifo_q_1$write_1__VAL_1 or
MUX_wsiM_reqFifo_q_1$write_1__SEL_2 or
MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or
WILL_FIRE_RL_wsiM_reqFifo_decCtr)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_wsiM_reqFifo_both:
wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_1;
MUX_wsiM_reqFifo_q_1$write_1__SEL_2:
wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2;
WILL_FIRE_RL_wsiM_reqFifo_decCtr:
wsiM_reqFifo_q_1$D_IN = 61'h00000AAAAAAAAA00;
default: wsiM_reqFifo_q_1$D_IN =
61'h0AAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign wsiM_reqFifo_q_1$EN =
WILL_FIRE_RL_wsiM_reqFifo_both ||
WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ||
WILL_FIRE_RL_wsiM_reqFifo_decCtr ;
// register wsiM_sThreadBusy_d
assign wsiM_sThreadBusy_d$D_IN = wsiM0_SThreadBusy ;
assign wsiM_sThreadBusy_d$EN = 1'd1 ;
// register wsiM_statusR
assign wsiM_statusR$D_IN =
{ wsiM_isReset_isInReset,
!wsiM_peerIsReady,
!wsiM_operateD,
wsiM_errorSticky,
wsiM_burstKind != 2'd0,
wsiM_sThreadBusy_d,
1'd0,
wsiM_trafficSticky } ;
assign wsiM_statusR$EN = 1'd1 ;
// register wsiM_tBusyCount
assign wsiM_tBusyCount$D_IN = wsiM_tBusyCount + 32'd1 ;
assign wsiM_tBusyCount$EN =
wsiM_operateD && wsiM_peerIsReady && wsiM_sThreadBusy_d ;
// register wsiM_trafficSticky
assign wsiM_trafficSticky$D_IN = 1'd1 ;
assign wsiM_trafficSticky$EN =
WILL_FIRE_RL_wsiM_reqFifo_deq &&
wsiM_reqFifo_q_0[60:58] == 3'd1 ;
// register wti_isReset_isInReset
assign wti_isReset_isInReset$D_IN = 1'd0 ;
assign wti_isReset_isInReset$EN = wti_isReset_isInReset ;
// register wti_nowReq
assign wti_nowReq$D_IN = wtiS0_req ;
assign wti_nowReq$EN = 1'd1 ;
// register wti_operateD
assign wti_operateD$D_IN = 1'b1 ;
assign wti_operateD$EN = 1'd1 ;
// submodule adcCore_acquireD
assign adcCore_acquireD$sD_IN = adcCore_acquireDReg ;
assign adcCore_acquireD$sEN =
adcCore_operateD$sRDY && adcCore_acquireD$sRDY &&
adcCore_averageD$sRDY ;
// submodule adcCore_averageD
assign adcCore_averageD$sD_IN = adcCore_averageDReg ;
assign adcCore_averageD$sEN =
adcCore_operateD$sRDY && adcCore_acquireD$sRDY &&
adcCore_averageD$sRDY ;
// submodule adcCore_colGate_sampF
always@(MUX_adcCore_colGate_sampF$enq_1__SEL_1 or
MUX_adcCore_colGate_sampF$enq_1__VAL_1 or
WILL_FIRE_RL_adcCore_colGate_send_timestamp_mesg or
MUX_adcCore_colGate_sampF$enq_1__VAL_2 or
WILL_FIRE_RL_adcCore_colGate_capture_collect or
MUX_adcCore_colGate_sampF$enq_1__VAL_3 or
WILL_FIRE_RL_adcCore_colGate_send_sync_mesg)
begin
case (1'b1) // synopsys parallel_case
MUX_adcCore_colGate_sampF$enq_1__SEL_1:
adcCore_colGate_sampF$D_IN = MUX_adcCore_colGate_sampF$enq_1__VAL_1;
WILL_FIRE_RL_adcCore_colGate_send_timestamp_mesg:
adcCore_colGate_sampF$D_IN = MUX_adcCore_colGate_sampF$enq_1__VAL_2;
WILL_FIRE_RL_adcCore_colGate_capture_collect:
adcCore_colGate_sampF$D_IN = MUX_adcCore_colGate_sampF$enq_1__VAL_3;
WILL_FIRE_RL_adcCore_colGate_send_sync_mesg:
adcCore_colGate_sampF$D_IN = 39'h3000000000;
default: adcCore_colGate_sampF$D_IN =
39'h2AAAAAAAAA /* unspecified value */ ;
endcase
end
assign adcCore_colGate_sampF$CLR = !adcCore_operateD$dD_OUT ;
assign adcCore_colGate_sampF$DEQ = adcCore_sampF_pwEnqueue$whas ;
assign adcCore_colGate_sampF$ENQ =
WILL_FIRE_RL_adcCore_colGate_overrun_recovery &&
adcCore_colGate_ovrRecover == 4'd15 ||
WILL_FIRE_RL_adcCore_colGate_send_timestamp_mesg ||
WILL_FIRE_RL_adcCore_colGate_capture_collect ||
WILL_FIRE_RL_adcCore_colGate_send_sync_mesg ;
// submodule adcCore_maxBurstLengthR
assign adcCore_maxBurstLengthR$sD_IN = maxMesgLength[17:2] ;
assign adcCore_maxBurstLengthR$sEN = adcCore_maxBurstLengthR$sRDY ;
// submodule adcCore_operateD
assign adcCore_operateD$sD_IN = adcCore_operateDReg ;
assign adcCore_operateD$sEN =
adcCore_operateD$sRDY && adcCore_acquireD$sRDY &&
adcCore_averageD$sRDY ;
// submodule adcCore_reqF
assign adcCore_reqF$D_IN =
MUX_adcCore_reqF$enq_1__SEL_1 ?
MUX_adcCore_reqF$enq_1__VAL_1 :
MUX_adcCore_reqF$enq_1__VAL_2 ;
assign adcCore_reqF$ENQ =
WILL_FIRE_RL_wci_cfwr &&
(wci_wslv_reqF$D_OUT[43:42] == 2'b0 &&
wci_wslv_reqF$D_OUT[39:32] == 8'h28 ||
wci_wslv_reqF$D_OUT[43:42] == 2'b01) ||
WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[43:42] == 2'b01 ;
assign adcCore_reqF$DEQ =
WILL_FIRE_RL_adcCore_advance_spi_request &&
(!adcCore_reqF$D_OUT[16] || adcCore_readMode) &&
(adcCore_reqF$D_OUT[16] || !adcCore_readMode) ;
assign adcCore_reqF$CLR = 1'b0 ;
// submodule adcCore_sampCC
assign adcCore_sampCC$sD_IN = adcCore_samp ;
assign adcCore_sampCC$sEN = adcCore_sampCC$sRDY ;
// submodule adcCore_sampF_memory
assign adcCore_sampF_memory$ADDRA =
{ adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1232,
adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1230,
adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1231,
adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1233,
adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1259,
adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1234,
adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1256,
adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1258,
adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1235,
adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1235 ^
adcCore_sampF_rWrPtr_rsCounter[0] } ;
assign adcCore_sampF_memory$ADDRB =
adcCore_sampF_pwDequeue$whas ? x__h23307[9:0] : x2__h23276 ;
assign adcCore_sampF_memory$DIA =
{ adcCore_sampF_pwEnqueue$whas ?
adcCore_colGate_sampF$D_OUT[38:37] :
2'd0,
adcCore_sampF_pwEnqueue$whas &&
adcCore_colGate_sampF$D_OUT[36],
adcCore_sampF_pwEnqueue$whas ?
adcCore_colGate_sampF$D_OUT[35:0] :
36'd0 } ;
assign adcCore_sampF_memory$DIB = 39'h2AAAAAAAAA /* unspecified value */ ;
assign adcCore_sampF_memory$WEA = adcCore_sampF_pwEnqueue$whas ;
assign adcCore_sampF_memory$WEB = 1'd0 ;
assign adcCore_sampF_memory$ENA = 1'd1 ;
assign adcCore_sampF_memory$ENB = 1'd1 ;
// submodule adcCore_statsCC
assign adcCore_statsCC$sD_IN =
{ adcCore_colGate_dropCount,
adcCore_colGate_sampCount,
adcCore_colGate_dwellStarts,
adcCore_colGate_dwellFails } ;
assign adcCore_statsCC$sEN = adcCore_statsCC$sRDY ;
// submodule wci_wslv_reqF
assign wci_wslv_reqF$D_IN = wci_wslv_wciReq$wget ;
assign wci_wslv_reqF$ENQ = wci_wslv_wciReq$wget[71:69] != 3'd0 ;
assign wci_wslv_reqF$DEQ = wci_wslv_reqF_r_deq$whas ;
assign wci_wslv_reqF$CLR = 1'b0 ;
// remaining internal signals
assign IF_adcCore_sampF_rRdPtr_rsCounter_48_BIT_0_55__ETC___d1412 =
adcCore_sampF_rRdPtr_rsCounter_48_BIT_0_55_XOR_ETC___d1344 ?
IF_adcCore_sampF_rRdPtr_rsCounter_48_BIT_0_55__ETC___d1413 :
32'd0 ;
assign IF_adcCore_sampF_rRdPtr_rsCounter_48_BIT_0_55__ETC___d1413 =
(adcCore_sampF_rRdPtr_rsCounter[0] ||
adcCore_sampF_rRdPtr_rsCounter[1] ||
adcCore_sampF_rRdPtr_rsCounter[2] ||
adcCore_sampF_rRdPtr_rsCounter[3] ||
adcCore_sampF_rRdPtr_rsCounter[4] ||
adcCore_sampF_rRdPtr_rsCounter[5] ||
adcCore_sampF_rRdPtr_rsCounter[6] ||
adcCore_sampF_rRdPtr_rsCounter[7] ||
adcCore_sampF_rRdPtr_rsCounter[8] ||
adcCore_sampF_rRdPtr_rsCounter[9]) ?
(adcCore_sampF_rRdPtr_rsCounter[0] ?
32'd1 :
(adcCore_sampF_rRdPtr_rsCounter[1] ?
32'd2 :
(adcCore_sampF_rRdPtr_rsCounter[2] ?
32'd3 :
(adcCore_sampF_rRdPtr_rsCounter[3] ?
32'd4 :
(adcCore_sampF_rRdPtr_rsCounter[4] ?
32'd5 :
(adcCore_sampF_rRdPtr_rsCounter[5] ?
32'd6 :
(adcCore_sampF_rRdPtr_rsCounter[6] ?
32'd7 :
(adcCore_sampF_rRdPtr_rsCounter[7] ?
32'd8 :
(adcCore_sampF_rRdPtr_rsCounter[8] ?
32'd9 :
(adcCore_sampF_rRdPtr_rsCounter[9] ?
32'd10 :
(adcCore_sampF_rRdPtr_rsCounter[10] ?
32'd11 :
32'd12))))))))))) :
32'd10 ;
assign IF_adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86__ETC___d1295 =
(adcCore_sampF_rWrPtr_rsCounter[0] ||
adcCore_sampF_rWrPtr_rsCounter[1] ||
adcCore_sampF_rWrPtr_rsCounter[2] ||
adcCore_sampF_rWrPtr_rsCounter[3] ||
adcCore_sampF_rWrPtr_rsCounter[4] ||
adcCore_sampF_rWrPtr_rsCounter[5] ||
adcCore_sampF_rWrPtr_rsCounter[6] ||
adcCore_sampF_rWrPtr_rsCounter[7] ||
adcCore_sampF_rWrPtr_rsCounter[8] ||
adcCore_sampF_rWrPtr_rsCounter[9]) ?
(adcCore_sampF_rWrPtr_rsCounter[0] ?
32'd1 :
(adcCore_sampF_rWrPtr_rsCounter[1] ?
32'd2 :
(adcCore_sampF_rWrPtr_rsCounter[2] ?
32'd3 :
(adcCore_sampF_rWrPtr_rsCounter[3] ?
32'd4 :
(adcCore_sampF_rWrPtr_rsCounter[4] ?
32'd5 :
(adcCore_sampF_rWrPtr_rsCounter[5] ?
32'd6 :
(adcCore_sampF_rWrPtr_rsCounter[6] ?
32'd7 :
(adcCore_sampF_rWrPtr_rsCounter[7] ?
32'd8 :
(adcCore_sampF_rWrPtr_rsCounter[8] ?
32'd9 :
(adcCore_sampF_rWrPtr_rsCounter[9] ?
32'd10 :
(adcCore_sampF_rWrPtr_rsCounter[10] ?
32'd11 :
32'd12))))))))))) :
32'd10 ;
assign IF_adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86__ETC___d1410 =
adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86_XOR_ETC___d1289 ?
IF_adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86__ETC___d1295 :
32'd0 ;
assign IF_fcAdc_grayCounter_rsCounter_60_BIT_0_67_OR__ETC___d1407 =
(fcAdc_grayCounter_rsCounter[0] ||
fcAdc_grayCounter_rsCounter[1] ||
fcAdc_grayCounter_rsCounter[2] ||
fcAdc_grayCounter_rsCounter[3] ||
fcAdc_grayCounter_rsCounter[4] ||
fcAdc_grayCounter_rsCounter[5] ||
fcAdc_grayCounter_rsCounter[6] ||
fcAdc_grayCounter_rsCounter[7] ||
fcAdc_grayCounter_rsCounter[8] ||
fcAdc_grayCounter_rsCounter[9] ||
fcAdc_grayCounter_rsCounter[10] ||
fcAdc_grayCounter_rsCounter[11] ||
fcAdc_grayCounter_rsCounter[12] ||
fcAdc_grayCounter_rsCounter[13] ||
fcAdc_grayCounter_rsCounter[14] ||
fcAdc_grayCounter_rsCounter[15] ||
fcAdc_grayCounter_rsCounter[16]) ?
(fcAdc_grayCounter_rsCounter[0] ?
32'd1 :
(fcAdc_grayCounter_rsCounter[1] ?
32'd2 :
(fcAdc_grayCounter_rsCounter[2] ?
32'd3 :
(fcAdc_grayCounter_rsCounter[3] ?
32'd4 :
(fcAdc_grayCounter_rsCounter[4] ?
32'd5 :
(fcAdc_grayCounter_rsCounter[5] ?
32'd6 :
(fcAdc_grayCounter_rsCounter[6] ?
32'd7 :
(fcAdc_grayCounter_rsCounter[7] ?
32'd8 :
(fcAdc_grayCounter_rsCounter[8] ?
32'd9 :
(fcAdc_grayCounter_rsCounter[9] ?
32'd10 :
(fcAdc_grayCounter_rsCounter[10] ?
32'd11 :
(fcAdc_grayCounter_rsCounter[11] ?
32'd12 :
(fcAdc_grayCounter_rsCounter[12] ?
32'd13 :
(fcAdc_grayCounter_rsCounter[13] ?
32'd14 :
(fcAdc_grayCounter_rsCounter[14] ?
32'd15 :
(fcAdc_grayCounter_rsCounter[15] ?
32'd16 :
(fcAdc_grayCounter_rsCounter[16] ?
32'd17 :
(fcAdc_grayCounter_rsCounter[17] ?
32'd18 :
32'd19)))))))))))))))))) :
32'd17 ;
assign IF_fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_ETC___d1408 =
fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_fc_ETC___d1343 ?
IF_fcAdc_grayCounter_rsCounter_60_BIT_0_67_OR__ETC___d1407 :
32'd0 ;
assign NOT_adcCore_sampF_rRdPtr_rsCounter_48_EQ_adcCo_ETC___d1051 =
adcCore_sampF_rRdPtr_rsCounter !=
adcCore_sampF_rWrPtr_rdCounter ;
assign NOT_adcCore_spiI_reqF_head_wrapped__read__71_E_ETC___d814 =
adcCore_spiI_reqF_head_wrapped !=
adcCore_spiI_reqF_tail_wrapped ;
assign adcCore_colGate_operatePW_whas__24_AND_adcCore_ETC___d379 =
adcCore_operateD$dD_OUT && adcCore_colGate_timeMesg == 3'd0 &&
adcCore_acquireD$dD_OUT &&
adcCore_colGate_collectD ;
assign adcCore_colGate_operatePW_whas__24_AND_adcCore_ETC___d390 =
adcCore_colGate_operatePW_whas__24_AND_adcCore_ETC___d379 &&
adcCore_colGate_syncMesg == 2'd0 &&
adcCore_colGate_ovrRecover == 4'd0 &&
(!adcCore_averageD$dD_OUT || adcCore_colGate_avgPhase == 2'd0) ;
assign adcCore_colGate_sampF_RDY_first__93_AND_NOT_ad_ETC___d750 =
adcCore_colGate_sampF$EMPTY_N &&
adcCore_sampF_rWrPtr_rsCounter !=
{ adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1247[10],
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1247[10] ^
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1247[9],
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1247[9] ^
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1247[8],
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1247[8] ^
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1247[7],
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1247[7] ^
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1247[6],
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1247[6] ^
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1247[5],
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1247[5] ^
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1247[4],
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1247[4] ^
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1247[3],
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1247[3] ^
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1247[2],
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1247[2] ^
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1247[1],
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1247[1] ^
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1247[0] } ;
assign adcCore_colGate_uprollCnt_93_EQ_adcCore_colGat_ETC___d1303 =
adcCore_colGate_uprollCnt ==
adcCore_maxBurstLengthR$dD_OUT - 16'd1 ;
assign adcCore_iseqFsm_abort_whas__69_AND_adcCore_ise_ETC___d941 =
(adcCore_iseqFsm_state_mkFSMstate == 4'd0 ||
adcCore_iseqFsm_state_mkFSMstate == 4'd10) &&
(!adcCore_iseqFsm_start_reg_1 || adcCore_iseqFsm_state_fired) ;
assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_CO_ETC___d1247 =
x_dReadBin__h21693 + 11'd512 ;
assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1242 =
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1263 ^
adcCore_sampF_rRdPtr_rdCounter[7] ;
assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1243 =
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1242 ^
adcCore_sampF_rRdPtr_rdCounter[6] ;
assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1244 =
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1243 ^
adcCore_sampF_rRdPtr_rdCounter[5] ;
assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1245 =
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1244 ^
adcCore_sampF_rRdPtr_rdCounter[4] ;
assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1246 =
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1264 ^
adcCore_sampF_rRdPtr_rdCounter[2] ;
assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1249 =
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1246 ^
adcCore_sampF_rRdPtr_rdCounter[1] ;
assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1262 =
adcCore_sampF_rRdPtr_rdCounter[10] ^
adcCore_sampF_rRdPtr_rdCounter[9] ;
assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1263 =
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1262 ^
adcCore_sampF_rRdPtr_rdCounter[8] ;
assign adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1264 =
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1245 ^
adcCore_sampF_rRdPtr_rdCounter[3] ;
assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_0_55_XOR_ETC___d1344 =
z__h20867 ^ adcCore_sampF_rRdPtr_rsCounter[10] ;
assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1236 =
adcCore_sampF_rRdPtr_rsCounter[10] ^
adcCore_sampF_rRdPtr_rsCounter[9] ;
assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1237 =
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1257 ^
adcCore_sampF_rRdPtr_rsCounter[7] ;
assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1238 =
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1237 ^
adcCore_sampF_rRdPtr_rsCounter[6] ;
assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1239 =
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1238 ^
adcCore_sampF_rRdPtr_rsCounter[5] ;
assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1240 =
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1239 ^
adcCore_sampF_rRdPtr_rsCounter[4] ;
assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1241 =
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1240 ^
adcCore_sampF_rRdPtr_rsCounter[3] ;
assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1257 =
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1236 ^
adcCore_sampF_rRdPtr_rsCounter[8] ;
assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1260 =
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1241 ^
adcCore_sampF_rRdPtr_rsCounter[2] ;
assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1261 =
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1260 ^
adcCore_sampF_rRdPtr_rsCounter[1] ;
assign adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1304 =
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1261 ^
adcCore_sampF_rRdPtr_rsCounter[0] ;
assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86_XOR_ETC___d1289 =
z__h18565 ^ adcCore_sampF_rWrPtr_rsCounter[10] ;
assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1230 =
adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1232 ^
adcCore_sampF_rWrPtr_rsCounter[8] ;
assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1231 =
adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1230 ^
adcCore_sampF_rWrPtr_rsCounter[7] ;
assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1232 =
adcCore_sampF_rWrPtr_rsCounter[10] ^
adcCore_sampF_rWrPtr_rsCounter[9] ;
assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1233 =
adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1231 ^
adcCore_sampF_rWrPtr_rsCounter[6] ;
assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1234 =
adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1259 ^
adcCore_sampF_rWrPtr_rsCounter[4] ;
assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1235 =
adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1258 ^
adcCore_sampF_rWrPtr_rsCounter[1] ;
assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1256 =
adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1234 ^
adcCore_sampF_rWrPtr_rsCounter[3] ;
assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1258 =
adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1256 ^
adcCore_sampF_rWrPtr_rsCounter[2] ;
assign adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1259 =
adcCore_sampF_rWrPtr_rsCounter_79_BIT_10_05_XO_ETC___d1233 ^
adcCore_sampF_rWrPtr_rsCounter[5] ;
assign adcCore_spiI_reqF_head_wrapped_crossed__63_EQ__ETC___d919 =
adcCore_spiI_reqF_head_wrapped ==
adcCore_spiI_reqF_tail_wrapped &&
!adcCore_spiI_reqF_sInReset$VAL &&
adcCore_spiI_cd$PREEDGE ;
assign adcCore_spiI_reqS_BITS_15_TO_8__q3 = adcCore_spiI_reqS[15:8] ;
assign adcCore_spiI_reqS_BITS_7_TO_0__q4 = adcCore_spiI_reqS[7:0] ;
assign adcStatusLs__h63134 =
{ 27'd0,
splitReadInFlight,
initOpInFlight,
1'b0,
adcCore_iseqFsm_abort_whas__69_AND_adcCore_ise_ETC___d941 &&
!adcCore_iseqFsm_start_reg,
1'b1 } ;
assign avgDataBW__h14897 =
{ adcCore_colGate_avgOdd[17:2], adcCore_colGate_avgEven[17:2] } ;
assign d_data__h14984 =
adcCore_averageD$dD_OUT ? avgDataBW__h14897 : adcCore_samp ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1219 =
fcAdc_grayCounter_rdCounter[17] ^
fcAdc_grayCounter_rdCounter[16] ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1220 =
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1219 ^
fcAdc_grayCounter_rdCounter[15] ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1221 =
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1220 ^
fcAdc_grayCounter_rdCounter[14] ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1222 =
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1253 ^
fcAdc_grayCounter_rdCounter[11] ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1223 =
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1266 ^
fcAdc_grayCounter_rdCounter[9] ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1224 =
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1223 ^
fcAdc_grayCounter_rdCounter[8] ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1225 =
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1254 ^
fcAdc_grayCounter_rdCounter[6] ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1226 =
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1225 ^
fcAdc_grayCounter_rdCounter[5] ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1227 =
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1228 ^
fcAdc_grayCounter_rdCounter[2] ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1228 =
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1250 ^
fcAdc_grayCounter_rdCounter[3] ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1229 =
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1227 ^
fcAdc_grayCounter_rdCounter[1] ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1250 =
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1226 ^
fcAdc_grayCounter_rdCounter[4] ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1252 =
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1221 ^
fcAdc_grayCounter_rdCounter[13] ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1253 =
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1252 ^
fcAdc_grayCounter_rdCounter[12] ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1254 =
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1224 ^
fcAdc_grayCounter_rdCounter[7] ;
assign fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1266 =
fcAdc_grayCounter_rdCounter_58_BIT_17_59_XOR_f_ETC___d1222 ^
fcAdc_grayCounter_rdCounter[10] ;
assign fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_fc_ETC___d1343 =
z__h7636 ^ fcAdc_grayCounter_rsCounter[17] ;
assign rdat__h63337 =
(wci_wslv_reqF$D_OUT[43:42] == 2'b0) ?
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 :
32'd0 ;
assign rdat__h63416 = { 24'd0, wsiM_statusR } ;
assign rdat__h63498 = { 14'd0, fcAdc_frequency } ;
assign rdat__h63518 = { 24'd0, spiResp } ;
assign wci_wslv_reqF_i_notEmpty__4_AND_IF_wci_wslv_re_ETC___d1098 =
wci_wslv_reqF$EMPTY_N &&
((wci_wslv_reqF$D_OUT[43:42] == 2'b0) ?
wci_wslv_reqF$D_OUT[39:32] != 8'h28 || adcCore_reqF$FULL_N :
wci_wslv_reqF$D_OUT[43:42] != 2'b01 || adcCore_reqF$FULL_N) ;
assign wti_nowReq_BITS_63_TO_0__q1 = wti_nowReq[63:0] ;
assign x2__h23276 =
{ adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1236,
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1257,
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1237,
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1238,
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1239,
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1240,
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1241,
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1260,
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1261,
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1304 } ;
assign x__h15249 = x__h15259 + y__h15410 ;
assign x__h15259 = adcCore_colGate_avgEven + y__h15412 ;
assign x__h15325 = y__h15412 + y__h15410 ;
assign x__h15399 = x__h15409 + y__h15410 ;
assign x__h15409 = adcCore_colGate_avgOdd + y__h15412 ;
assign x__h17578 =
11'd1 <<
IF_adcCore_sampF_rWrPtr_rsCounter_79_BIT_0_86__ETC___d1410 ;
assign x__h19880 =
11'd1 <<
IF_adcCore_sampF_rRdPtr_rsCounter_48_BIT_0_55__ETC___d1412 ;
assign x__h23307 = x_sReadBin__h21690 + 11'd1 ;
assign x__h7511 =
18'd1 <<
IF_fcAdc_grayCounter_rsCounter_60_BIT_0_67_XOR_ETC___d1408 ;
assign x_burstLength__h61970 =
adcCore_sampF_memory$DOB[36] ? 12'd1 : 12'd4095 ;
assign x_dReadBin__h21693 =
{ adcCore_sampF_rRdPtr_rdCounter[10],
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1262,
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1263,
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1242,
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1243,
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1244,
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1245,
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1264,
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1246,
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1249,
adcCore_sampF_rRdPtr_rdCounter_94_BIT_10_95_XO_ETC___d1249 ^
adcCore_sampF_rRdPtr_rdCounter[0] } ;
assign x_sReadBin__h21690 =
{ adcCore_sampF_rRdPtr_rsCounter[10],
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1236,
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1257,
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1237,
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1238,
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1239,
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1240,
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1241,
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1260,
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1261,
adcCore_sampF_rRdPtr_rsCounter_48_BIT_10_74_XO_ETC___d1304 } ;
assign y__h15410 = { 2'd0, adcCore_samp[15:0] } ;
assign y__h15412 = { 2'd0, adcCore_samp[31:16] } ;
assign y__h18465 = ~x__h17578 ;
assign y__h20767 = ~x__h19880 ;
assign y__h8916 = ~x__h7511 ;
assign z__h18509 =
adcCore_sampF_rWrPtr_rsCounter[0] ^
adcCore_sampF_rWrPtr_rsCounter[1] ;
assign z__h18516 = z__h18509 ^ adcCore_sampF_rWrPtr_rsCounter[2] ;
assign z__h18523 = z__h18516 ^ adcCore_sampF_rWrPtr_rsCounter[3] ;
assign z__h18530 = z__h18523 ^ adcCore_sampF_rWrPtr_rsCounter[4] ;
assign z__h18537 = z__h18530 ^ adcCore_sampF_rWrPtr_rsCounter[5] ;
assign z__h18544 = z__h18537 ^ adcCore_sampF_rWrPtr_rsCounter[6] ;
assign z__h18551 = z__h18544 ^ adcCore_sampF_rWrPtr_rsCounter[7] ;
assign z__h18558 = z__h18551 ^ adcCore_sampF_rWrPtr_rsCounter[8] ;
assign z__h18565 = z__h18558 ^ adcCore_sampF_rWrPtr_rsCounter[9] ;
assign z__h20811 =
adcCore_sampF_rRdPtr_rsCounter[0] ^
adcCore_sampF_rRdPtr_rsCounter[1] ;
assign z__h20818 = z__h20811 ^ adcCore_sampF_rRdPtr_rsCounter[2] ;
assign z__h20825 = z__h20818 ^ adcCore_sampF_rRdPtr_rsCounter[3] ;
assign z__h20832 = z__h20825 ^ adcCore_sampF_rRdPtr_rsCounter[4] ;
assign z__h20839 = z__h20832 ^ adcCore_sampF_rRdPtr_rsCounter[5] ;
assign z__h20846 = z__h20839 ^ adcCore_sampF_rRdPtr_rsCounter[6] ;
assign z__h20853 = z__h20846 ^ adcCore_sampF_rRdPtr_rsCounter[7] ;
assign z__h20860 = z__h20853 ^ adcCore_sampF_rRdPtr_rsCounter[8] ;
assign z__h20867 = z__h20860 ^ adcCore_sampF_rRdPtr_rsCounter[9] ;
assign z__h7531 =
fcAdc_grayCounter_rsCounter[0] ^ fcAdc_grayCounter_rsCounter[1] ;
assign z__h7538 = z__h7531 ^ fcAdc_grayCounter_rsCounter[2] ;
assign z__h7545 = z__h7538 ^ fcAdc_grayCounter_rsCounter[3] ;
assign z__h7552 = z__h7545 ^ fcAdc_grayCounter_rsCounter[4] ;
assign z__h7559 = z__h7552 ^ fcAdc_grayCounter_rsCounter[5] ;
assign z__h7566 = z__h7559 ^ fcAdc_grayCounter_rsCounter[6] ;
assign z__h7573 = z__h7566 ^ fcAdc_grayCounter_rsCounter[7] ;
assign z__h7580 = z__h7573 ^ fcAdc_grayCounter_rsCounter[8] ;
assign z__h7587 = z__h7580 ^ fcAdc_grayCounter_rsCounter[9] ;
assign z__h7594 = z__h7587 ^ fcAdc_grayCounter_rsCounter[10] ;
assign z__h7601 = z__h7594 ^ fcAdc_grayCounter_rsCounter[11] ;
assign z__h7608 = z__h7601 ^ fcAdc_grayCounter_rsCounter[12] ;
assign z__h7615 = z__h7608 ^ fcAdc_grayCounter_rsCounter[13] ;
assign z__h7622 = z__h7615 ^ fcAdc_grayCounter_rsCounter[14] ;
assign z__h7629 = z__h7622 ^ fcAdc_grayCounter_rsCounter[15] ;
assign z__h7636 = z__h7629 ^ fcAdc_grayCounter_rsCounter[16] ;
always@(adcCore_colGate_timeMesg or
adcCore_colGate_dwellFails or
adcCore_colGate_dwellStarts or
adcCore_colGate_sampCount or
adcCore_colGate_dropCount or wti_nowReq_BITS_63_TO_0__q1)
begin
case (adcCore_colGate_timeMesg)
3'h1: x1_data__h14584 = adcCore_colGate_dwellStarts;
3'h3: x1_data__h14584 = adcCore_colGate_sampCount;
3'h4: x1_data__h14584 = adcCore_colGate_dropCount;
3'h5: x1_data__h14584 = wti_nowReq_BITS_63_TO_0__q1[31:0];
3'h6: x1_data__h14584 = wti_nowReq_BITS_63_TO_0__q1[63:32];
default: x1_data__h14584 = adcCore_colGate_dwellFails;
endcase
end
always@(wci_wslv_reqF$D_OUT or
rdat__h63416 or
adcStatusLs__h63134 or
maxMesgLength or
adcControl or
rdat__h63498 or
adcCore_statsCC$dD_OUT or
adcCore_sampCC$dD_OUT or
rdat__h63518 or
mesgCount or
lastOverflowMesg or wsiM_extStatusW$wget or overflowCountD)
begin
case (wci_wslv_reqF$D_OUT[39:32])
8'h0:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 =
rdat__h63416;
8'h04:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 =
adcStatusLs__h63134;
8'h08:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 =
maxMesgLength;
8'h0C:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 =
adcControl;
8'h10:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 =
32'h20120625;
8'h14:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 =
rdat__h63498;
8'h18:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 =
adcCore_statsCC$dD_OUT[95:64];
8'h1C:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 =
adcCore_sampCC$dD_OUT;
8'h30:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 =
rdat__h63518;
8'h34:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 =
mesgCount;
8'h3C:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 =
adcCore_statsCC$dD_OUT[63:32];
8'h40:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 =
adcCore_statsCC$dD_OUT[31:0];
8'h44:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 =
lastOverflowMesg;
8'h50:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 =
wsiM_extStatusW$wget[95:64];
8'h54:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 =
wsiM_extStatusW$wget[63:32];
8'h58:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 =
wsiM_extStatusW$wget[31:0];
8'h5C:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 =
adcCore_statsCC$dD_OUT[127:96];
8'h60:
IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 =
overflowCountD;
default: IF_wci_wslv_reqF_first__5_BITS_39_TO_32_086_EQ_ETC___d1190 =
32'd0;
endcase
end
always@(adcCore_colGate_avgPhase)
begin
case (adcCore_colGate_avgPhase)
2'd0, 2'd1, 2'd2, 2'd3:
CASE_adcCore_colGate_avgPhase_0b1_0_1_1_1_2_1__ETC__q2 = 1'd1;
endcase
end
// handling of inlined registers
always@(posedge wciS0_Clk)
begin
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
adcControl <= `BSV_ASSIGNMENT_DELAY 32'd0;
adcCore_acquireDReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore_adcRst <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore_averageDReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore_iseqFsm_jj_delay_count <= `BSV_ASSIGNMENT_DELAY 13'd1;
adcCore_iseqFsm_start_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore_iseqFsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore_iseqFsm_state_can_overlap <= `BSV_ASSIGNMENT_DELAY 1'd1;
adcCore_iseqFsm_state_fired <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore_iseqFsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY 4'd0;
adcCore_operateDReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore_readMode <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore_spiI_reqF_tail_wrapped <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore_spiI_respF_head_wrapped <= `BSV_ASSIGNMENT_DELAY 1'd0;
fcAdc_countNow <= `BSV_ASSIGNMENT_DELAY 18'd262143;
fcAdc_countPast <= `BSV_ASSIGNMENT_DELAY 18'd262143;
fcAdc_frequency <= `BSV_ASSIGNMENT_DELAY 18'd262143;
fcAdc_pulseAction <= `BSV_ASSIGNMENT_DELAY 1'd0;
fcAdc_sampleCount <= `BSV_ASSIGNMENT_DELAY 16'd0;
initOpInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0;
lastOverflowMesg <= `BSV_ASSIGNMENT_DELAY 32'hFFFFFFFF;
maxMesgLength <= `BSV_ASSIGNMENT_DELAY 32'd1024;
mesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
oneKHz_value <= `BSV_ASSIGNMENT_DELAY 18'd0;
overflowCountD <= `BSV_ASSIGNMENT_DELAY 32'd0;
sFlagState <= `BSV_ASSIGNMENT_DELAY 1'd0;
spiResp <= `BSV_ASSIGNMENT_DELAY 8'd255;
splitReadInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2;
wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0;
wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00;
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00;
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (adcControl$EN)
adcControl <= `BSV_ASSIGNMENT_DELAY adcControl$D_IN;
if (adcCore_acquireDReg$EN)
adcCore_acquireDReg <= `BSV_ASSIGNMENT_DELAY
adcCore_acquireDReg$D_IN;
if (adcCore_adcRst$EN)
adcCore_adcRst <= `BSV_ASSIGNMENT_DELAY adcCore_adcRst$D_IN;
if (adcCore_averageDReg$EN)
adcCore_averageDReg <= `BSV_ASSIGNMENT_DELAY
adcCore_averageDReg$D_IN;
if (adcCore_iseqFsm_jj_delay_count$EN)
adcCore_iseqFsm_jj_delay_count <= `BSV_ASSIGNMENT_DELAY
adcCore_iseqFsm_jj_delay_count$D_IN;
if (adcCore_iseqFsm_start_reg$EN)
adcCore_iseqFsm_start_reg <= `BSV_ASSIGNMENT_DELAY
adcCore_iseqFsm_start_reg$D_IN;
if (adcCore_iseqFsm_start_reg_1$EN)
adcCore_iseqFsm_start_reg_1 <= `BSV_ASSIGNMENT_DELAY
adcCore_iseqFsm_start_reg_1$D_IN;
if (adcCore_iseqFsm_state_can_overlap$EN)
adcCore_iseqFsm_state_can_overlap <= `BSV_ASSIGNMENT_DELAY
adcCore_iseqFsm_state_can_overlap$D_IN;
if (adcCore_iseqFsm_state_fired$EN)
adcCore_iseqFsm_state_fired <= `BSV_ASSIGNMENT_DELAY
adcCore_iseqFsm_state_fired$D_IN;
if (adcCore_iseqFsm_state_mkFSMstate$EN)
adcCore_iseqFsm_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY
adcCore_iseqFsm_state_mkFSMstate$D_IN;
if (adcCore_operateDReg$EN)
adcCore_operateDReg <= `BSV_ASSIGNMENT_DELAY
adcCore_operateDReg$D_IN;
if (adcCore_readMode$EN)
adcCore_readMode <= `BSV_ASSIGNMENT_DELAY adcCore_readMode$D_IN;
if (adcCore_spiI_reqF_tail_wrapped$EN)
adcCore_spiI_reqF_tail_wrapped <= `BSV_ASSIGNMENT_DELAY
adcCore_spiI_reqF_tail_wrapped$D_IN;
if (adcCore_spiI_respF_head_wrapped$EN)
adcCore_spiI_respF_head_wrapped <= `BSV_ASSIGNMENT_DELAY
adcCore_spiI_respF_head_wrapped$D_IN;
if (fcAdc_countNow$EN)
fcAdc_countNow <= `BSV_ASSIGNMENT_DELAY fcAdc_countNow$D_IN;
if (fcAdc_countPast$EN)
fcAdc_countPast <= `BSV_ASSIGNMENT_DELAY fcAdc_countPast$D_IN;
if (fcAdc_frequency$EN)
fcAdc_frequency <= `BSV_ASSIGNMENT_DELAY fcAdc_frequency$D_IN;
if (fcAdc_pulseAction$EN)
fcAdc_pulseAction <= `BSV_ASSIGNMENT_DELAY fcAdc_pulseAction$D_IN;
if (fcAdc_sampleCount$EN)
fcAdc_sampleCount <= `BSV_ASSIGNMENT_DELAY fcAdc_sampleCount$D_IN;
if (initOpInFlight$EN)
initOpInFlight <= `BSV_ASSIGNMENT_DELAY initOpInFlight$D_IN;
if (lastOverflowMesg$EN)
lastOverflowMesg <= `BSV_ASSIGNMENT_DELAY lastOverflowMesg$D_IN;
if (maxMesgLength$EN)
maxMesgLength <= `BSV_ASSIGNMENT_DELAY maxMesgLength$D_IN;
if (mesgCount$EN) mesgCount <= `BSV_ASSIGNMENT_DELAY mesgCount$D_IN;
if (oneKHz_value$EN)
oneKHz_value <= `BSV_ASSIGNMENT_DELAY oneKHz_value$D_IN;
if (overflowCountD$EN)
overflowCountD <= `BSV_ASSIGNMENT_DELAY overflowCountD$D_IN;
if (sFlagState$EN)
sFlagState <= `BSV_ASSIGNMENT_DELAY sFlagState$D_IN;
if (spiResp$EN) spiResp <= `BSV_ASSIGNMENT_DELAY spiResp$D_IN;
if (splitReadInFlight$EN)
splitReadInFlight <= `BSV_ASSIGNMENT_DELAY splitReadInFlight$D_IN;
if (wci_wslv_cEdge$EN)
wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY wci_wslv_cEdge$D_IN;
if (wci_wslv_cState$EN)
wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY wci_wslv_cState$D_IN;
if (wci_wslv_ctlAckReg$EN)
wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_ctlAckReg$D_IN;
if (wci_wslv_ctlOpActive$EN)
wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY
wci_wslv_ctlOpActive$D_IN;
if (wci_wslv_illegalEdge$EN)
wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY
wci_wslv_illegalEdge$D_IN;
if (wci_wslv_nState$EN)
wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY wci_wslv_nState$D_IN;
if (wci_wslv_reqF_countReg$EN)
wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY
wci_wslv_reqF_countReg$D_IN;
if (wci_wslv_respF_c_r$EN)
wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_c_r$D_IN;
if (wci_wslv_respF_q_0$EN)
wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0$D_IN;
if (wci_wslv_respF_q_1$EN)
wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_1$D_IN;
if (wci_wslv_sFlagReg$EN)
wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_sFlagReg$D_IN;
if (wci_wslv_sThreadBusy_d$EN)
wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
wci_wslv_sThreadBusy_d$D_IN;
if (wsiM_burstKind$EN)
wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY wsiM_burstKind$D_IN;
if (wsiM_errorSticky$EN)
wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiM_errorSticky$D_IN;
if (wsiM_iMesgCount$EN)
wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_iMesgCount$D_IN;
if (wsiM_operateD$EN)
wsiM_operateD <= `BSV_ASSIGNMENT_DELAY wsiM_operateD$D_IN;
if (wsiM_pMesgCount$EN)
wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount$D_IN;
if (wsiM_peerIsReady$EN)
wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady$D_IN;
if (wsiM_reqFifo_c_r$EN)
wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_c_r$D_IN;
if (wsiM_reqFifo_q_0$EN)
wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0$D_IN;
if (wsiM_reqFifo_q_1$EN)
wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_1$D_IN;
if (wsiM_sThreadBusy_d$EN)
wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wsiM_sThreadBusy_d$D_IN;
if (wsiM_tBusyCount$EN)
wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiM_tBusyCount$D_IN;
if (wsiM_trafficSticky$EN)
wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiM_trafficSticky$D_IN;
end
if (adcCore_spiI_reqS$EN)
adcCore_spiI_reqS <= `BSV_ASSIGNMENT_DELAY adcCore_spiI_reqS$D_IN;
if (wsiM_statusR$EN)
wsiM_statusR <= `BSV_ASSIGNMENT_DELAY wsiM_statusR$D_IN;
end
always@(posedge CLK_adc_clock)
begin
if (adcCore_sdrRst$OUT_RST == `BSV_RESET_VALUE)
begin
adcCore_colGate_avgEven <= `BSV_ASSIGNMENT_DELAY 18'd0;
adcCore_colGate_avgOdd <= `BSV_ASSIGNMENT_DELAY 18'd0;
adcCore_colGate_avgPhase <= `BSV_ASSIGNMENT_DELAY 2'd0;
adcCore_colGate_collectD <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore_colGate_dropCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
adcCore_colGate_dwellFails <= `BSV_ASSIGNMENT_DELAY 32'd0;
adcCore_colGate_dwellStarts <= `BSV_ASSIGNMENT_DELAY 32'd0;
adcCore_colGate_ovrRecover <= `BSV_ASSIGNMENT_DELAY 4'd0;
adcCore_colGate_sampActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore_colGate_sampActiveD <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore_colGate_sampCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
adcCore_colGate_syncMesg <= `BSV_ASSIGNMENT_DELAY 2'd0;
adcCore_colGate_timeMesg <= `BSV_ASSIGNMENT_DELAY 3'd0;
adcCore_colGate_uprollCnt <= `BSV_ASSIGNMENT_DELAY 16'd0;
wti_nowReq <= `BSV_ASSIGNMENT_DELAY 67'd0;
wti_operateD <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (adcCore_colGate_avgEven$EN)
adcCore_colGate_avgEven <= `BSV_ASSIGNMENT_DELAY
adcCore_colGate_avgEven$D_IN;
if (adcCore_colGate_avgOdd$EN)
adcCore_colGate_avgOdd <= `BSV_ASSIGNMENT_DELAY
adcCore_colGate_avgOdd$D_IN;
if (adcCore_colGate_avgPhase$EN)
adcCore_colGate_avgPhase <= `BSV_ASSIGNMENT_DELAY
adcCore_colGate_avgPhase$D_IN;
if (adcCore_colGate_collectD$EN)
adcCore_colGate_collectD <= `BSV_ASSIGNMENT_DELAY
adcCore_colGate_collectD$D_IN;
if (adcCore_colGate_dropCount$EN)
adcCore_colGate_dropCount <= `BSV_ASSIGNMENT_DELAY
adcCore_colGate_dropCount$D_IN;
if (adcCore_colGate_dwellFails$EN)
adcCore_colGate_dwellFails <= `BSV_ASSIGNMENT_DELAY
adcCore_colGate_dwellFails$D_IN;
if (adcCore_colGate_dwellStarts$EN)
adcCore_colGate_dwellStarts <= `BSV_ASSIGNMENT_DELAY
adcCore_colGate_dwellStarts$D_IN;
if (adcCore_colGate_ovrRecover$EN)
adcCore_colGate_ovrRecover <= `BSV_ASSIGNMENT_DELAY
adcCore_colGate_ovrRecover$D_IN;
if (adcCore_colGate_sampActive$EN)
adcCore_colGate_sampActive <= `BSV_ASSIGNMENT_DELAY
adcCore_colGate_sampActive$D_IN;
if (adcCore_colGate_sampActiveD$EN)
adcCore_colGate_sampActiveD <= `BSV_ASSIGNMENT_DELAY
adcCore_colGate_sampActiveD$D_IN;
if (adcCore_colGate_sampCount$EN)
adcCore_colGate_sampCount <= `BSV_ASSIGNMENT_DELAY
adcCore_colGate_sampCount$D_IN;
if (adcCore_colGate_syncMesg$EN)
adcCore_colGate_syncMesg <= `BSV_ASSIGNMENT_DELAY
adcCore_colGate_syncMesg$D_IN;
if (adcCore_colGate_timeMesg$EN)
adcCore_colGate_timeMesg <= `BSV_ASSIGNMENT_DELAY
adcCore_colGate_timeMesg$D_IN;
if (adcCore_colGate_uprollCnt$EN)
adcCore_colGate_uprollCnt <= `BSV_ASSIGNMENT_DELAY
adcCore_colGate_uprollCnt$D_IN;
if (wti_nowReq$EN)
wti_nowReq <= `BSV_ASSIGNMENT_DELAY wti_nowReq$D_IN;
if (wti_operateD$EN)
wti_operateD <= `BSV_ASSIGNMENT_DELAY wti_operateD$D_IN;
end
if (adcCore_colGate_sampDataWD$EN)
adcCore_colGate_sampDataWD <= `BSV_ASSIGNMENT_DELAY
adcCore_colGate_sampDataWD$D_IN;
if (adcCore_iobA$EN)
adcCore_iobA <= `BSV_ASSIGNMENT_DELAY adcCore_iobA$D_IN;
if (adcCore_iobB$EN)
adcCore_iobB <= `BSV_ASSIGNMENT_DELAY adcCore_iobB$D_IN;
if (adcCore_samp$EN)
adcCore_samp <= `BSV_ASSIGNMENT_DELAY adcCore_samp$D_IN;
end
always@(posedge adcCore_spiI_cd$CLK_OUT)
begin
if (adcCore_spiI_slowReset$OUT_RST == `BSV_RESET_VALUE)
begin
adcCore_spiI_cGate <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore_spiI_csbR <= `BSV_ASSIGNMENT_DELAY 1'b1;
adcCore_spiI_doResp <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore_spiI_reqF_head_wrapped <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore_spiI_respF_tail_wrapped <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore_spiI_sdoR <= `BSV_ASSIGNMENT_DELAY 1'b0;
adcCore_spiI_xmt_d <= `BSV_ASSIGNMENT_DELAY 1'd0;
adcCore_spiI_xmt_i <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (adcCore_spiI_cGate$EN)
adcCore_spiI_cGate <= `BSV_ASSIGNMENT_DELAY adcCore_spiI_cGate$D_IN;
if (adcCore_spiI_csbR$EN)
adcCore_spiI_csbR <= `BSV_ASSIGNMENT_DELAY adcCore_spiI_csbR$D_IN;
if (adcCore_spiI_doResp$EN)
adcCore_spiI_doResp <= `BSV_ASSIGNMENT_DELAY
adcCore_spiI_doResp$D_IN;
if (adcCore_spiI_reqF_head_wrapped$EN)
adcCore_spiI_reqF_head_wrapped <= `BSV_ASSIGNMENT_DELAY
adcCore_spiI_reqF_head_wrapped$D_IN;
if (adcCore_spiI_respF_tail_wrapped$EN)
adcCore_spiI_respF_tail_wrapped <= `BSV_ASSIGNMENT_DELAY
adcCore_spiI_respF_tail_wrapped$D_IN;
if (adcCore_spiI_sdoR$EN)
adcCore_spiI_sdoR <= `BSV_ASSIGNMENT_DELAY adcCore_spiI_sdoR$D_IN;
if (adcCore_spiI_xmt_d$EN)
adcCore_spiI_xmt_d <= `BSV_ASSIGNMENT_DELAY adcCore_spiI_xmt_d$D_IN;
if (adcCore_spiI_xmt_i$EN)
adcCore_spiI_xmt_i <= `BSV_ASSIGNMENT_DELAY adcCore_spiI_xmt_i$D_IN;
end
if (adcCore_spiI_cap$EN)
adcCore_spiI_cap <= `BSV_ASSIGNMENT_DELAY adcCore_spiI_cap$D_IN;
if (adcCore_spiI_cap_1$EN)
adcCore_spiI_cap_1 <= `BSV_ASSIGNMENT_DELAY adcCore_spiI_cap_1$D_IN;
if (adcCore_spiI_cap_2$EN)
adcCore_spiI_cap_2 <= `BSV_ASSIGNMENT_DELAY adcCore_spiI_cap_2$D_IN;
if (adcCore_spiI_cap_3$EN)
adcCore_spiI_cap_3 <= `BSV_ASSIGNMENT_DELAY adcCore_spiI_cap_3$D_IN;
if (adcCore_spiI_cap_4$EN)
adcCore_spiI_cap_4 <= `BSV_ASSIGNMENT_DELAY adcCore_spiI_cap_4$D_IN;
if (adcCore_spiI_cap_5$EN)
adcCore_spiI_cap_5 <= `BSV_ASSIGNMENT_DELAY adcCore_spiI_cap_5$D_IN;
if (adcCore_spiI_cap_6$EN)
adcCore_spiI_cap_6 <= `BSV_ASSIGNMENT_DELAY adcCore_spiI_cap_6$D_IN;
if (adcCore_spiI_cap_7$EN)
adcCore_spiI_cap_7 <= `BSV_ASSIGNMENT_DELAY adcCore_spiI_cap_7$D_IN;
if (adcCore_spiI_dPos$EN)
adcCore_spiI_dPos <= `BSV_ASSIGNMENT_DELAY adcCore_spiI_dPos$D_IN;
if (adcCore_spiI_iPos$EN)
adcCore_spiI_iPos <= `BSV_ASSIGNMENT_DELAY adcCore_spiI_iPos$D_IN;
if (adcCore_spiI_respS$EN)
adcCore_spiI_respS <= `BSV_ASSIGNMENT_DELAY adcCore_spiI_respS$D_IN;
end
always@(posedge adcCore_spiI_cinv$CLK_OUT)
begin
if (adcCore_spiI_sdiP$EN)
adcCore_spiI_sdiP <= `BSV_ASSIGNMENT_DELAY adcCore_spiI_sdiP$D_IN;
end
always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n)
if (wciS0_MReset_n == `BSV_RESET_VALUE)
begin
adcCore_sampF_rRdPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY 11'd0;
adcCore_sampF_rWrPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY 11'd0;
adcCore_sampF_rWrPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY 11'd0;
fcAdc_grayCounter_rdCounter <= `BSV_ASSIGNMENT_DELAY 18'd0;
fcAdc_grayCounter_rdCounterPre <= `BSV_ASSIGNMENT_DELAY 18'd0;
wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (adcCore_sampF_rRdPtr_rsCounter$EN)
adcCore_sampF_rRdPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY
adcCore_sampF_rRdPtr_rsCounter$D_IN;
if (adcCore_sampF_rWrPtr_rdCounter$EN)
adcCore_sampF_rWrPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY
adcCore_sampF_rWrPtr_rdCounter$D_IN;
if (adcCore_sampF_rWrPtr_rdCounterPre$EN)
adcCore_sampF_rWrPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY
adcCore_sampF_rWrPtr_rdCounterPre$D_IN;
if (fcAdc_grayCounter_rdCounter$EN)
fcAdc_grayCounter_rdCounter <= `BSV_ASSIGNMENT_DELAY
fcAdc_grayCounter_rdCounter$D_IN;
if (fcAdc_grayCounter_rdCounterPre$EN)
fcAdc_grayCounter_rdCounterPre <= `BSV_ASSIGNMENT_DELAY
fcAdc_grayCounter_rdCounterPre$D_IN;
if (wci_wslv_isReset_isInReset$EN)
wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wci_wslv_isReset_isInReset$D_IN;
if (wsiM_isReset_isInReset$EN)
wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wsiM_isReset_isInReset$D_IN;
end
always@(posedge CLK_adc_clock or `BSV_RESET_EDGE adcCore_sdrRst$OUT_RST)
if (adcCore_sdrRst$OUT_RST == `BSV_RESET_VALUE)
begin
adcCore_sampF_rRdPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY 11'd0;
adcCore_sampF_rRdPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY 11'd0;
adcCore_sampF_rWrPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY 11'd0;
wti_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
end
else
begin
if (adcCore_sampF_rRdPtr_rdCounter$EN)
adcCore_sampF_rRdPtr_rdCounter <= `BSV_ASSIGNMENT_DELAY
adcCore_sampF_rRdPtr_rdCounter$D_IN;
if (adcCore_sampF_rRdPtr_rdCounterPre$EN)
adcCore_sampF_rRdPtr_rdCounterPre <= `BSV_ASSIGNMENT_DELAY
adcCore_sampF_rRdPtr_rdCounterPre$D_IN;
if (adcCore_sampF_rWrPtr_rsCounter$EN)
adcCore_sampF_rWrPtr_rsCounter <= `BSV_ASSIGNMENT_DELAY
adcCore_sampF_rWrPtr_rsCounter$D_IN;
if (wti_isReset_isInReset$EN)
wti_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
wti_isReset_isInReset$D_IN;
end
always@(posedge CLK_adcCaptureClk or `BSV_RESET_EDGE fcAdc_testRst$OUT_RST)
if (fcAdc_testRst$OUT_RST == `BSV_RESET_VALUE)
begin
fcAdc_grayCounter_rsCounter <= `BSV_ASSIGNMENT_DELAY 18'd0;
end
else
begin
if (fcAdc_grayCounter_rsCounter$EN)
fcAdc_grayCounter_rsCounter <= `BSV_ASSIGNMENT_DELAY
fcAdc_grayCounter_rsCounter$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
adcControl = 32'hAAAAAAAA;
adcCore_acquireDReg = 1'h0;
adcCore_adcRst = 1'h0;
adcCore_averageDReg = 1'h0;
adcCore_colGate_avgEven = 18'h2AAAA;
adcCore_colGate_avgOdd = 18'h2AAAA;
adcCore_colGate_avgPhase = 2'h2;
adcCore_colGate_collectD = 1'h0;
adcCore_colGate_dropCount = 32'hAAAAAAAA;
adcCore_colGate_dwellFails = 32'hAAAAAAAA;
adcCore_colGate_dwellStarts = 32'hAAAAAAAA;
adcCore_colGate_ovrRecover = 4'hA;
adcCore_colGate_sampActive = 1'h0;
adcCore_colGate_sampActiveD = 1'h0;
adcCore_colGate_sampCount = 32'hAAAAAAAA;
adcCore_colGate_sampDataWD = 32'hAAAAAAAA;
adcCore_colGate_syncMesg = 2'h2;
adcCore_colGate_timeMesg = 3'h2;
adcCore_colGate_uprollCnt = 16'hAAAA;
adcCore_iobA = 14'h2AAA;
adcCore_iobB = 14'h2AAA;
adcCore_iseqFsm_jj_delay_count = 13'h0AAA;
adcCore_iseqFsm_start_reg = 1'h0;
adcCore_iseqFsm_start_reg_1 = 1'h0;
adcCore_iseqFsm_state_can_overlap = 1'h0;
adcCore_iseqFsm_state_fired = 1'h0;
adcCore_iseqFsm_state_mkFSMstate = 4'hA;
adcCore_operateDReg = 1'h0;
adcCore_readMode = 1'h0;
adcCore_samp = 32'hAAAAAAAA;
adcCore_sampF_rRdPtr_rdCounter = 11'h2AA;
adcCore_sampF_rRdPtr_rdCounterPre = 11'h2AA;
adcCore_sampF_rRdPtr_rsCounter = 11'h2AA;
adcCore_sampF_rWrPtr_rdCounter = 11'h2AA;
adcCore_sampF_rWrPtr_rdCounterPre = 11'h2AA;
adcCore_sampF_rWrPtr_rsCounter = 11'h2AA;
adcCore_spiI_cGate = 1'h0;
adcCore_spiI_cap = 1'h0;
adcCore_spiI_cap_1 = 1'h0;
adcCore_spiI_cap_2 = 1'h0;
adcCore_spiI_cap_3 = 1'h0;
adcCore_spiI_cap_4 = 1'h0;
adcCore_spiI_cap_5 = 1'h0;
adcCore_spiI_cap_6 = 1'h0;
adcCore_spiI_cap_7 = 1'h0;
adcCore_spiI_csbR = 1'h0;
adcCore_spiI_dPos = 3'h2;
adcCore_spiI_doResp = 1'h0;
adcCore_spiI_iPos = 4'hA;
adcCore_spiI_reqF_head_wrapped = 1'h0;
adcCore_spiI_reqF_tail_wrapped = 1'h0;
adcCore_spiI_reqS = 17'h0AAAA;
adcCore_spiI_respF_head_wrapped = 1'h0;
adcCore_spiI_respF_tail_wrapped = 1'h0;
adcCore_spiI_respS = 8'hAA;
adcCore_spiI_sdiP = 1'h0;
adcCore_spiI_sdoR = 1'h0;
adcCore_spiI_xmt_d = 1'h0;
adcCore_spiI_xmt_i = 1'h0;
fcAdc_countNow = 18'h2AAAA;
fcAdc_countPast = 18'h2AAAA;
fcAdc_frequency = 18'h2AAAA;
fcAdc_grayCounter_rdCounter = 18'h2AAAA;
fcAdc_grayCounter_rdCounterPre = 18'h2AAAA;
fcAdc_grayCounter_rsCounter = 18'h2AAAA;
fcAdc_pulseAction = 1'h0;
fcAdc_sampleCount = 16'hAAAA;
initOpInFlight = 1'h0;
lastOverflowMesg = 32'hAAAAAAAA;
maxMesgLength = 32'hAAAAAAAA;
mesgCount = 32'hAAAAAAAA;
oneKHz_value = 18'h2AAAA;
overflowCountD = 32'hAAAAAAAA;
sFlagState = 1'h0;
spiResp = 8'hAA;
splitReadInFlight = 1'h0;
wci_wslv_cEdge = 3'h2;
wci_wslv_cState = 3'h2;
wci_wslv_ctlAckReg = 1'h0;
wci_wslv_ctlOpActive = 1'h0;
wci_wslv_illegalEdge = 1'h0;
wci_wslv_isReset_isInReset = 1'h0;
wci_wslv_nState = 3'h2;
wci_wslv_reqF_countReg = 2'h2;
wci_wslv_respF_c_r = 2'h2;
wci_wslv_respF_q_0 = 34'h2AAAAAAAA;
wci_wslv_respF_q_1 = 34'h2AAAAAAAA;
wci_wslv_sFlagReg = 1'h0;
wci_wslv_sThreadBusy_d = 1'h0;
wsiM_burstKind = 2'h2;
wsiM_errorSticky = 1'h0;
wsiM_iMesgCount = 32'hAAAAAAAA;
wsiM_isReset_isInReset = 1'h0;
wsiM_operateD = 1'h0;
wsiM_pMesgCount = 32'hAAAAAAAA;
wsiM_peerIsReady = 1'h0;
wsiM_reqFifo_c_r = 2'h2;
wsiM_reqFifo_q_0 = 61'h0AAAAAAAAAAAAAAA;
wsiM_reqFifo_q_1 = 61'h0AAAAAAAAAAAAAAA;
wsiM_sThreadBusy_d = 1'h0;
wsiM_statusR = 8'hAA;
wsiM_tBusyCount = 32'hAAAAAAAA;
wsiM_trafficSticky = 1'h0;
wti_isReset_isInReset = 1'h0;
wti_nowReq = 67'h2AAAAAAAAAAAAAAAA;
wti_operateD = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge wciS0_Clk)
begin
#0;
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr)
begin
v__h62856 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr)
$display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x",
v__h62856,
wci_wslv_reqF$D_OUT[63:32],
wci_wslv_reqF$D_OUT[67:64],
wci_wslv_reqF$D_OUT[31:0]);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
begin
v__h3700 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
$display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x",
v__h3700,
wci_wslv_reqF$D_OUT[36:34],
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_EiI && MUX_splitReadInFlight$write_1__PSEL_1)
$display("Error: \"bsv/wrk/IQADCWorker.bsv\", line 122, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_get_adc_resp] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/IQADCWorker.bsv\", line 122, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_EiI && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/IQADCWorker.bsv\", line 122, column 46: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO && MUX_splitReadInFlight$write_1__PSEL_1)
$display("Error: \"bsv/wrk/IQADCWorker.bsv\", line 122, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_get_adc_resp] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/IQADCWorker.bsv\", line 122, column 60: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_ctrl_OrE && MUX_splitReadInFlight$write_1__PSEL_1)
$display("Error: \"bsv/wrk/IQADCWorker.bsv\", line 122, column 74: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_ctrl_OrE] and\n [RL_get_adc_resp] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (adcCore_iseqFsm_state_mkFSMstate == 4'd1 &&
(adcCore_iseqFsm_state_mkFSMstate == 4'd2 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_np ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l141c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l142c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l143c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l144c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l145c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l146c9))
$display("Error: \"bsv/dev/TI62P4X.bsv\", line 139, column 12: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore_iseqFsm_action_l139c12] and\n [RL_adcCore_iseqFsm_action_d_init_np, RL_adcCore_iseqFsm_action_np,\n RL_adcCore_iseqFsm_action_l141c9, RL_adcCore_iseqFsm_action_l142c9,\n RL_adcCore_iseqFsm_action_l143c9, RL_adcCore_iseqFsm_action_l144c9,\n RL_adcCore_iseqFsm_action_l145c9, RL_adcCore_iseqFsm_action_l146c9] ) fired\n in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (adcCore_iseqFsm_state_mkFSMstate == 4'd2 &&
(WILL_FIRE_RL_adcCore_iseqFsm_action_np ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l141c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l142c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l143c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l144c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l145c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l146c9))
$display("Error: \"StmtFSM.bs\", line 41, column 0: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore_iseqFsm_action_d_init_np] and [RL_adcCore_iseqFsm_action_np,\n RL_adcCore_iseqFsm_action_l141c9, RL_adcCore_iseqFsm_action_l142c9,\n RL_adcCore_iseqFsm_action_l143c9, RL_adcCore_iseqFsm_action_l144c9,\n RL_adcCore_iseqFsm_action_l145c9, RL_adcCore_iseqFsm_action_l146c9] ) fired\n in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_adcCore_iseqFsm_action_np &&
(WILL_FIRE_RL_adcCore_iseqFsm_action_l141c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l142c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l143c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l144c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l145c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l146c9))
$display("Error: \"StmtFSM.bs\", line 41, column 0: (R0001)\n Mutually exclusive rules (from the ME sets [RL_adcCore_iseqFsm_action_np]\n and [RL_adcCore_iseqFsm_action_l141c9, RL_adcCore_iseqFsm_action_l142c9,\n RL_adcCore_iseqFsm_action_l143c9, RL_adcCore_iseqFsm_action_l144c9,\n RL_adcCore_iseqFsm_action_l145c9, RL_adcCore_iseqFsm_action_l146c9] ) fired\n in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_adcCore_iseqFsm_action_l142c9 &&
(WILL_FIRE_RL_adcCore_iseqFsm_action_l143c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l144c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l145c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l146c9))
$display("Error: \"bsv/dev/TI62P4X.bsv\", line 142, column 9: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore_iseqFsm_action_l142c9] and [RL_adcCore_iseqFsm_action_l143c9,\n RL_adcCore_iseqFsm_action_l144c9, RL_adcCore_iseqFsm_action_l145c9,\n RL_adcCore_iseqFsm_action_l146c9] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_adcCore_iseqFsm_action_l141c9 &&
(WILL_FIRE_RL_adcCore_iseqFsm_action_l142c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l143c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l144c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l145c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l146c9))
$display("Error: \"bsv/dev/TI62P4X.bsv\", line 141, column 9: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore_iseqFsm_action_l141c9] and [RL_adcCore_iseqFsm_action_l142c9,\n RL_adcCore_iseqFsm_action_l143c9, RL_adcCore_iseqFsm_action_l144c9,\n RL_adcCore_iseqFsm_action_l145c9, RL_adcCore_iseqFsm_action_l146c9] ) fired\n in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_adcCore_iseqFsm_action_l143c9 &&
(WILL_FIRE_RL_adcCore_iseqFsm_action_l144c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l145c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l146c9))
$display("Error: \"bsv/dev/TI62P4X.bsv\", line 143, column 9: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore_iseqFsm_action_l143c9] and [RL_adcCore_iseqFsm_action_l144c9,\n RL_adcCore_iseqFsm_action_l145c9, RL_adcCore_iseqFsm_action_l146c9] ) fired\n in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_adcCore_iseqFsm_action_l144c9 &&
(WILL_FIRE_RL_adcCore_iseqFsm_action_l145c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l146c9))
$display("Error: \"bsv/dev/TI62P4X.bsv\", line 144, column 9: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore_iseqFsm_action_l144c9] and [RL_adcCore_iseqFsm_action_l145c9,\n RL_adcCore_iseqFsm_action_l146c9] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_adcCore_iseqFsm_action_l145c9 &&
WILL_FIRE_RL_adcCore_iseqFsm_action_l146c9)
$display("Error: \"bsv/dev/TI62P4X.bsv\", line 145, column 9: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore_iseqFsm_action_l145c9] and [RL_adcCore_iseqFsm_action_l146c9] )\n fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd)
begin
v__h63353 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd)
$display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x",
v__h63353,
wci_wslv_reqF$D_OUT[63:32],
wci_wslv_reqF$D_OUT[67:64],
rdat__h63337);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && MUX_splitReadInFlight$write_1__PSEL_1)
$display("Error: \"bsv/wrk/IQADCWorker.bsv\", line 122, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_get_adc_resp] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/IQADCWorker.bsv\", line 122, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/IQADCWorker.bsv\", line 122, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/wrk/IQADCWorker.bsv\", line 122, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd)
$display("Error: \"bsv/wrk/IQADCWorker.bsv\", line 122, column 26: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && MUX_splitReadInFlight$write_1__PSEL_1)
$display("Error: \"bsv/wrk/IQADCWorker.bsv\", line 122, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_get_adc_resp] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE)
$display("Error: \"bsv/wrk/IQADCWorker.bsv\", line 122, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO)
$display("Error: \"bsv/wrk/IQADCWorker.bsv\", line 122, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_EiI)
$display("Error: \"bsv/wrk/IQADCWorker.bsv\", line 122, column 36: (R0001)\n Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
begin
v__h4019 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x",
v__h4019,
wci_wslv_cEdge,
wci_wslv_cState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
begin
v__h3875 = $time;
#0;
end
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
$display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x",
v__h3875,
wci_wslv_cEdge,
wci_wslv_cState,
wci_wslv_nState);
if (wciS0_MReset_n != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_adcCore_iseqFsm_action_l138c12 &&
(adcCore_iseqFsm_state_mkFSMstate == 4'd1 ||
adcCore_iseqFsm_state_mkFSMstate == 4'd2 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_np ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l141c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l142c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l143c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l144c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l145c9 ||
WILL_FIRE_RL_adcCore_iseqFsm_action_l146c9))
$display("Error: \"bsv/dev/TI62P4X.bsv\", line 138, column 12: (R0001)\n Mutually exclusive rules (from the ME sets\n [RL_adcCore_iseqFsm_action_l138c12] and [RL_adcCore_iseqFsm_action_l139c12,\n RL_adcCore_iseqFsm_action_d_init_np, RL_adcCore_iseqFsm_action_np,\n RL_adcCore_iseqFsm_action_l141c9, RL_adcCore_iseqFsm_action_l142c9,\n RL_adcCore_iseqFsm_action_l143c9, RL_adcCore_iseqFsm_action_l144c9,\n RL_adcCore_iseqFsm_action_l145c9, RL_adcCore_iseqFsm_action_l146c9] ) fired\n in the same clock cycle.\n");
end
// synopsys translate_on
endmodule // mkIQADCWorker
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A222OI_TB_V
`define SKY130_FD_SC_HD__A222OI_TB_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a222oi.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg C2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
C2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 C2 = 1'b0;
#140 VGND = 1'b0;
#160 VNB = 1'b0;
#180 VPB = 1'b0;
#200 VPWR = 1'b0;
#220 A1 = 1'b1;
#240 A2 = 1'b1;
#260 B1 = 1'b1;
#280 B2 = 1'b1;
#300 C1 = 1'b1;
#320 C2 = 1'b1;
#340 VGND = 1'b1;
#360 VNB = 1'b1;
#380 VPB = 1'b1;
#400 VPWR = 1'b1;
#420 A1 = 1'b0;
#440 A2 = 1'b0;
#460 B1 = 1'b0;
#480 B2 = 1'b0;
#500 C1 = 1'b0;
#520 C2 = 1'b0;
#540 VGND = 1'b0;
#560 VNB = 1'b0;
#580 VPB = 1'b0;
#600 VPWR = 1'b0;
#620 VPWR = 1'b1;
#640 VPB = 1'b1;
#660 VNB = 1'b1;
#680 VGND = 1'b1;
#700 C2 = 1'b1;
#720 C1 = 1'b1;
#740 B2 = 1'b1;
#760 B1 = 1'b1;
#780 A2 = 1'b1;
#800 A1 = 1'b1;
#820 VPWR = 1'bx;
#840 VPB = 1'bx;
#860 VNB = 1'bx;
#880 VGND = 1'bx;
#900 C2 = 1'bx;
#920 C1 = 1'bx;
#940 B2 = 1'bx;
#960 B1 = 1'bx;
#980 A2 = 1'bx;
#1000 A1 = 1'bx;
end
sky130_fd_sc_hd__a222oi dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .C2(C2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A222OI_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__INPUTISO0P_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__INPUTISO0P_FUNCTIONAL_PP_V
/**
* inputiso0p: Input isolator with non-inverted enable.
*
* X = (A & !SLEEP_B)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__inputiso0p (
X ,
A ,
SLEEP,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input SLEEP;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire sleepn ;
wire and0_out_X;
// Name Output Other arguments
not not0 (sleepn , SLEEP );
and and0 (and0_out_X, A, sleepn );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (X , and0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__INPUTISO0P_FUNCTIONAL_PP_V |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Source Synchronous Output Serializer
// /___/ /\ Filename : OSERDESE1.v
// \ \ / \ Timestamp : Tue Sep 16 15:30:44 PDT 2008
// \___\/\___\
//
// Revision:
// 09/16/08 - Initial version.
// 12/05/08 - IR 495397.
// 01/13/09 - IR 503429.
// 01/15/09 - IR 503783 CLKPERF is not inverted for OFB/ofb_out.
// 02/06/09 - CR 507373 Removed IOCLKGLITCH and CLKB
// 02/26/09 - CR 510489 fixed SHIFTIN2_in
// 03/16/09 - CR 512140 and 512139 -- sdf load errors
// 01/27/10 - CR 546419 Updated specify block
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 09/04/12 - 676501 CLK -> OFB specify path missing
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module OSERDESE1 (OCBEXTEND, OFB, OQ, SHIFTOUT1, SHIFTOUT2, TFB, TQ,
CLK, CLKDIV, CLKPERF, CLKPERFDELAY, D1, D2, D3, D4, D5, D6, OCE, ODV, RST, SHIFTIN1, SHIFTIN2, T1, T2, T3, T4, TCE, WC);
parameter DATA_RATE_OQ = "DDR";
parameter DATA_RATE_TQ = "DDR";
parameter integer DATA_WIDTH = 4;
parameter integer DDR3_DATA = 1;
parameter [0:0] INIT_OQ = 1'b0;
parameter [0:0] INIT_TQ = 1'b0;
parameter INTERFACE_TYPE = "DEFAULT";
parameter integer ODELAY_USED = 0;
parameter SERDES_MODE = "MASTER";
parameter [0:0] SRVAL_OQ = 1'b0;
parameter [0:0] SRVAL_TQ = 1'b0;
parameter integer TRISTATE_WIDTH = 4;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
//-------------------------------------------------------------
// Outputs:
//-------------------------------------------------------------
// OQ: Data output
// TQ: Output of tristate mux
// SHIFTOUT1: Carry out data 1 for slave
// SHIFTOUT2: Carry out data 2 for slave
// OFB: O Feedback output
//
//-------------------------------------------------------------
// Inputs:
//-------------------------------------------------------------
//
// Inputs:
// CLK: High speed clock from DCM
// CLKB: Inverted High speed clock from DCM
// CLKDIV: Low speed divided clock from DCM
// CLKPERF: Performance Path clock
// CLKPERFDELAY: delayed Performance Path clock
// D1, D2, D3, D4, D5, D6 : Data inputs
// OCE: Clock enable for output data flops
// ODV: ODELAY value > 140 degrees
// RST: Reset control
// T1, T2, T3, T4: tristate inputs
// SHIFTIN1: Carry in data 1 for master from slave
// SHIFTIN2: Carry in data 2 for master from slave
// TCE: Tristate clock enable
// WC: Write command given by memory controller
output OCBEXTEND;
output OFB;
output OQ;
output SHIFTOUT1;
output SHIFTOUT2;
output TFB;
output TQ;
input CLK;
input CLKDIV;
input CLKPERF;
input CLKPERFDELAY;
input D1;
input D2;
input D3;
input D4;
input D5;
input D6;
input OCE;
input ODV;
input RST;
input SHIFTIN1;
input SHIFTIN2;
input T1;
input T2;
input T3;
input T4;
input TCE;
input WC;
//
wire SERDES, DDR_CLK_EDGE;
wire [5:0] SRTYPE;
wire WC_DELAY;
wire [4:0] SELFHEAL;
wire load;
wire qmux1, qmux2, tmux1, tmux2;
wire data1, data2, triin1, triin2;
wire d2rnk2;
wire CLKD;
wire CLKDIVD;
wire iodelay_state;
// attribute
reg data_rate_int;
reg [3:0] data_width_int;
reg [1:0] tristate_width_int;
reg data_rate_oq_int;
reg [1:0] data_rate_tq_int;
reg ddr3_data_int;
reg interface_type_int;
reg odelay_used_int;
reg serdes_mode_int;
// Output signals
wire ioclkglitch_out, ocbextend_out, ofb_out, oq_out, tq_out, shiftout1_out, shiftout2_out;
wire tfb_out;
// Other signals
tri0 GSR = glbl.GSR;
reg notifier;
wire CLK_in;
wire CLKDIV_in;
wire CLKPERF_in;
wire CLKPERFDELAY_in;
wire D1_in;
wire D2_in;
wire D3_in;
wire D4_in;
wire D5_in;
wire D6_in;
wire OCE_in;
wire ODV_in;
wire RST_in;
wire SHIFTIN1_in;
wire SHIFTIN2_in;
wire T1_in;
wire T2_in;
wire T3_in;
wire T4_in;
wire TCE_in;
wire WC_in;
`ifndef XIL_TIMING
assign CLK_in = CLK;
assign CLKDIV_in = CLKDIV;
assign D1_in = D1;
assign D2_in = D2;
assign D3_in = D3;
assign D4_in = D4;
assign D5_in = D5;
assign D6_in = D6;
assign OCE_in = OCE;
assign T1_in = T1;
assign T2_in = T2;
assign T3_in = T3;
assign T4_in = T4;
assign TCE_in = TCE;
assign WC_in = WC;
`endif // `ifndef XIL_TIMING
assign CLKPERF_in = CLKPERF;
// assign CLKPERFDELAY_in = CLKPERFDELAY;
// IR 495397 & IR 499954
// assign CLKPERFDELAY_in = (CLKPERFDELAY === 1'bx)? 1'b0 : CLKPERFDELAY;
generate
case (ODELAY_USED)
0: assign CLKPERFDELAY_in = CLKPERF;
1: assign CLKPERFDELAY_in = (CLKPERFDELAY === 1'bx)? 1'b0 : CLKPERFDELAY;
endcase
endgenerate
assign SHIFTIN1_in = SHIFTIN1;
assign SHIFTIN2_in = SHIFTIN2;
assign ODV_in = ODV;
assign RST_in = RST;
buf b_ocbextend (OCBEXTEND, ocbextend_out);
buf b_ofb (OFB, ofb_out);
buf b_oq (OQ, oq_out);
buf b_shiftout1 (SHIFTOUT1, shiftout1_out);
buf b_shiftout2 (SHIFTOUT2, shiftout2_out);
buf b_tfb (TFB, tfb_out);
buf b_tq (TQ, tq_out);
initial begin
//-------------------------------------------------
//----- DATA_RATE_OQ check
//-------------------------------------------------
case (DATA_RATE_OQ)
"SDR" : data_rate_oq_int <= 1'b1;
"DDR" : data_rate_oq_int <= 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DATA_RATE_OQ on OSERDESE1 instance %m is set to %s. Legal values for this attribute are SDR or DDR", DATA_RATE_OQ);
#1 $finish;
end
endcase // case(DATA_RATE_OQ)
//-------------------------------------------------
//----- DATA_RATE_TQ check
//-------------------------------------------------
case (DATA_RATE_TQ)
"BUF" : data_rate_tq_int <= 2'b00;
"SDR" : data_rate_tq_int <= 2'b01;
"DDR" : data_rate_tq_int <= 2'b10;
default : begin
$display("Attribute Syntax Error : The attribute DATA_RATE_TQ on OSERDESE1 instance %m is set to %s. Legal values for this attribute are BUF, SDR or DDR", DATA_RATE_TQ);
#1 $finish;
end
endcase // case(DATA_RATE_TQ)
//-------------------------------------------------
//----- DATA_WIDTH check
//-------------------------------------------------
case (DATA_WIDTH)
2, 3, 4, 5, 6, 7, 8, 10 : data_width_int = DATA_WIDTH;
default : begin
$display("Attribute Syntax Error : The attribute DATA_WIDTH on OSERDESE1 instance %m is set to %d. Legal values for this attribute are 2, 3, 4, 5, 6, 7, 8, or 10", DATA_WIDTH);
#1 $finish;
end
endcase // case(DATA_WIDTH)
//-------------------------------------------------
//----- DDR3_DATA check
//-------------------------------------------------
case (DDR3_DATA)
0 : ddr3_data_int <= 1'b0;
1 : ddr3_data_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute DDR3_DATA on OSERDESE1 instance %m is set to %d. Legal values for this attribute are 0 or 1", DDR3_DATA);
#1 $finish;
end
endcase // case(DDR3_DATA)
//-------------------------------------------------
//----- INTERFACE_TYPE check
//-------------------------------------------------
case (INTERFACE_TYPE)
"DEFAULT" : interface_type_int <= 1'b0;
"MEMORY_DDR3" : interface_type_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute INTERFACE_TYPE on OSERDESE1 instance %m is set to %s. Legal values for this attribute are DEFAULT, or MEMORY_DDR3", INTERFACE_TYPE);
#1 $finish;
end
endcase // INTERFACE_TYPE
//-------------------------------------------------
//----- ODELAY_USED check
//-------------------------------------------------
case (ODELAY_USED)
// "FALSE" : odelay_used_int <= 1'b0;
// "TRUE" : odelay_used_int <= 1'b1;
0 : odelay_used_int <= 1'b0;
1 : odelay_used_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute ODELAY_USED on OSERDESE1 instance %m is set to %s. Legal values for this attribute are FALSE or TRUE", ODELAY_USED);
#1 $finish;
end
endcase // case(ODELAY_USED)
//-------------------------------------------------
//----- SERDES_MODE check
//-------------------------------------------------
case (SERDES_MODE)
"MASTER" : serdes_mode_int <= 1'b0;
"SLAVE" : serdes_mode_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute SERDES_MODE on OSERDESE1 instance %m is set to %s. Legal values for this attribute are MASTER or SLAVE", SERDES_MODE);
#1 $finish;
end
endcase // case(SERDES_MODE)
//-------------------------------------------------
//----- TRISTATE_WIDTH check
//-------------------------------------------------
case (TRISTATE_WIDTH)
1 : tristate_width_int <= 2'b00;
2 : tristate_width_int <= 2'b01;
4 : tristate_width_int <= 2'b10;
default : begin
$display("Attribute Syntax Error : The attribute TRISTATE_WIDTH on OSERDESE1 instance %m is set to %d. Legal values for this attribute are 1, 2 or 4", TRISTATE_WIDTH);
#1 $finish;
end
endcase // case(TRISTATE_WIDTH)
//-------------------------------------------------
end // initial begin
//-------------------------------------------------
assign SERDES = 1'b1;
assign SRTYPE = 6'b111111;
assign DDR_CLK_EDGE = 1'b1;
assign WC_DELAY = 1'b0;
assign SELFHEAL = 5'b00000;
assign #0 CLKD = CLK;
assign #0 CLKDIVD = CLKDIV;
assign #10 ofb_out = (ODELAY_USED == 1)? CLKPERF : oq_out;
assign #10 tfb_out = iodelay_state;
/////////////////////////////////////////////////////////
//
// Delay assignments
//
/////////////////////////////////////////////////////////
// Data output delays
defparam dfront.FFD = 1; // clock to out delay for flip flops
// driven by clk
defparam datao.FFD = 1; // clock to out delay for flip flops
// driven by clk
defparam dfront.FFCD = 1; // clock to out delay for flip flops
// driven by clkdiv
defparam dfront.MXD = 1; // mux delay
defparam dfront.MXR1 = 1; // mux before 2nd rank of flops
// Programmable load generator
defparam dfront.ldgen.ffdcnt = 1;
defparam dfront.ldgen.mxdcnt = 1;
defparam dfront.ldgen.FFRST = 145; // clock to out delay for flop in PLSG
// Tristate output delays
defparam tfront.ffd = 1; // clock to out delay for flip flops
defparam tfront.mxd = 1; // mux delay
defparam trio.ffd = 1; // clock to out delay for flip flops
defparam trio.mxd = 1; // mux delay
//------------------------------------------------------------------
// Instantiate output data section
//------------------------------------------------------------------
rank12d_oserdese1_vlog dfront (.D1(D1_in), .D2(D2_in), .D3(D3_in), .D4(D4_in), .D5(D5_in), .D6(D6_in),
.d2rnk2(d2rnk2),
.SHIFTIN1(SHIFTIN1_in), .SHIFTIN2(SHIFTIN2_in),
.C(CLK_in), .CLKDIV(CLKDIV_in), .SR(RST_in), .OCE(OCE_in),
.data1(data1), .data2(data2), .SHIFTOUT1(shiftout1_out), .SHIFTOUT2(shiftout2_out),
.DATA_RATE_OQ(data_rate_oq_int), .DATA_WIDTH(data_width_int),
.SERDES_MODE(serdes_mode_int), .load(load),
.IOCLK_GLITCH(ioclkglitch_out),
.INIT_OQ(INIT_OQ), .SRVAL_OQ(SRVAL_OQ));
trif_oserdese1_vlog tfront (.T1(T1_in), .T2(T2_in), .T3(T3_in), .T4(T4_in), .load(load),
.C(CLK_in), .CLKDIV(CLKDIV_in), .SR(RST_in), .TCE(TCE_in),
.DATA_RATE_TQ(data_rate_tq_int), .TRISTATE_WIDTH(tristate_width_int),
.INIT_TQ(INIT_TQ), .SRVAL_TQ(SRVAL_TQ),
.data1(triin1), .data2(triin2));
txbuffer_oserdese1_vlog DDR3FIFO (.iodelay_state(iodelay_state), .qmux1(qmux1), .qmux2(qmux2), .tmux1(tmux1), .tmux2(tmux2),
.d1(data1), .d2(data2), .t1(triin1), .t2(triin2), .trif(tq_out),
.WC(WC_in), .ODV(ODV_in), .extra(ocbextend_out),
.clk(CLK_in), .clkdiv(CLKDIV_in), .bufo(CLKPERFDELAY_in), .bufop(CLKPERF_in), .rst(RST_in),
.ODELAY_USED(odelay_used_int), .DDR3_DATA(ddr3_data_int),
.DDR3_MODE(interface_type_int));
dout_oserdese1_vlog datao (.data1(qmux1), .data2(qmux2),
.CLK(CLK_in), .BUFO(CLKPERFDELAY_in), .SR(RST_in), .OCE(OCE_in),
.OQ(oq_out), .d2rnk2(d2rnk2),
.DATA_RATE_OQ(data_rate_oq_int),
.INIT_OQ(INIT_OQ), .SRVAL_OQ(SRVAL_OQ),
.DDR3_MODE(interface_type_int));
tout_oserdese1_vlog trio (.data1(tmux1), .data2(tmux2),
.CLK(CLK_in), .BUFO(CLKPERFDELAY_in), .SR(RST_in), .TCE(TCE_in),
.DATA_RATE_TQ(data_rate_tq_int), .TRISTATE_WIDTH(tristate_width_int),
.INIT_TQ(INIT_TQ), .SRVAL_TQ(SRVAL_TQ),
.TQ(tq_out), .DDR3_MODE(interface_type_int));
`ifndef XIL_TIMING
specify
( CLK => OFB) = (100, 100);
( CLK => OQ) = (100, 100);
( CLK => TQ) = (100, 100);
( CLKPERF => OQ) = (100, 100);
( CLKPERF => TQ) = (100, 100);
( CLKPERFDELAY => OQ) = (100, 100);
( CLKPERFDELAY => TQ) = (100, 100);
( T1 => TQ) = (0, 0);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifndef XIL_TIMING
`ifdef XIL_TIMING
//*** Timing Checks Start here
specify
( CLK => OFB) = (100:100:100, 100:100:100);
( CLK => OQ) = (100:100:100, 100:100:100);
( CLK => TQ) = (100:100:100, 100:100:100);
( CLKPERF => OQ) = (100:100:100, 100:100:100);
( CLKPERF => TQ) = (100:100:100, 100:100:100);
( CLKPERFDELAY => OQ) = (100:100:100, 100:100:100);
( CLKPERFDELAY => TQ) = (100:100:100, 100:100:100);
( T1 => TQ) = (0:0:0, 0:0:0);
$setuphold (posedge CLK, negedge OCE, 0:0:0, 0:0:0, notifier,,, CLK_in, OCE_in);
$setuphold (posedge CLK, negedge T1, 0:0:0, 0:0:0, notifier,,, CLK_in, T1_in);
$setuphold (posedge CLK, negedge TCE, 0:0:0, 0:0:0, notifier,,, CLK_in, TCE_in);
$setuphold (posedge CLK, posedge OCE, 0:0:0, 0:0:0, notifier,,, CLK_in, OCE_in);
$setuphold (posedge CLK, posedge T1, 0:0:0, 0:0:0, notifier,,, CLK_in, T1_in);
$setuphold (posedge CLK, posedge TCE, 0:0:0, 0:0:0, notifier,,, CLK_in, TCE_in);
$setuphold (posedge CLKDIV, negedge D1, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D1_in);
$setuphold (posedge CLKDIV, negedge D2, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D2_in);
$setuphold (posedge CLKDIV, negedge D3, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D3_in);
$setuphold (posedge CLKDIV, negedge D4, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D4_in);
$setuphold (posedge CLKDIV, negedge D5, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D5_in);
$setuphold (posedge CLKDIV, negedge D6, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D6_in);
$setuphold (posedge CLKDIV, negedge RST, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, RST_in);
$setuphold (posedge CLKDIV, negedge T1, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T1_in);
$setuphold (posedge CLKDIV, negedge T2, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T2_in);
$setuphold (posedge CLKDIV, negedge T3, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T3_in);
$setuphold (posedge CLKDIV, negedge T4, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T4_in);
$setuphold (posedge CLKDIV, negedge WC, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, WC_in);
$setuphold (posedge CLKDIV, posedge D1, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D1_in);
$setuphold (posedge CLKDIV, posedge D2, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D2_in);
$setuphold (posedge CLKDIV, posedge D3, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D3_in);
$setuphold (posedge CLKDIV, posedge D4, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D4_in);
$setuphold (posedge CLKDIV, posedge D5, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D5_in);
$setuphold (posedge CLKDIV, posedge D6, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, D6_in);
$setuphold (posedge CLKDIV, posedge RST, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, RST_in);
$setuphold (posedge CLKDIV, posedge T1, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T1_in);
$setuphold (posedge CLKDIV, posedge T2, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T2_in);
$setuphold (posedge CLKDIV, posedge T3, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T3_in);
$setuphold (posedge CLKDIV, posedge T4, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, T4_in);
$setuphold (posedge CLKDIV, posedge WC, 0:0:0, 0:0:0, notifier,,, CLKDIV_in, WC_in);
specparam PATHPULSE$ = 0;
endspecify
`endif // `ifdef XIL_TIMING
endmodule // OSERDESE1
`timescale 1ps/1ps
/////////////////////////////////////////////////////////
//
// module selfheal_oserdese1_vlog
//
///////////////////////////////////////////////////////
//
// Self healing circuit for Mt Blanc
// This model ONLY works for SERDES operation!!
//
//
//
////////////////////////////////////////////////////////
//
//
//
/////////////////////////////////////////////////////////
//
// Inputs:
// dq3 - dq0: Data from load counter
// CLKDIV: Divided clock from PLL
// srint: RESET from load generator
// rst: Set/Reset control
//
//
//
// Outputs:
// SHO: Data output
//
//
//
// Programmable Points
// SELFHEAL: String of 5 bits. 1 as enable and 4 as compare
// Test attributes in model
//
//
//
//
//
////////////////////////////////////////////////////////////////////////////////
//
module selfheal_oserdese1_vlog (dq3, dq2, dq1, dq0,
CLKDIV, srint, rst,
SHO);
input dq3, dq2, dq1, dq0;
input CLKDIV, srint, rst;
output SHO;
reg shr;
reg SHO;
wire clkint;
wire error;
wire rst_in, rst_self_heal;
// Programmable Points
wire [4:0] SELFHEAL;
assign SELFHEAL = 5'b00000;
//////////////////////////////////////////////////
// Delay values
//
parameter FFD = 10; // clock to out delay for flip flops
// driven by clk
parameter FFCD = 10; // clock to out delay for flip flops
// driven by clkdiv
parameter MXD = 10; // 60 ps mux delay
parameter MXR1 = 10;
/////////////////////////////////////////
assign clkint = CLKDIV & SELFHEAL[4];
assign error = (((~SELFHEAL[4] ^ SELFHEAL[3]) ^ dq3) | ((~SELFHEAL[4] ^ SELFHEAL[2]) ^ dq2) | ((~SELFHEAL[4] ^ SELFHEAL[1]) ^ dq1) | ((~SELFHEAL[4] ^ SELFHEAL[0]) ^ dq0));
assign rst_in = (~SELFHEAL[4] | ~srint);
assign rst_self_heal = (rst | ~shr);
/////////////////////////////////////////
// Reset Flop
////////////////////////////////////////
always @ (posedge clkint or posedge rst)
begin
begin
if (rst)
begin
shr <= # FFD 1'b0;
end
else begin
shr <= #FFD rst_in;
end
end
end
// Self heal flop
always @ (posedge clkint or posedge rst_self_heal)
begin
begin
if (rst_self_heal)
begin
SHO <= 1'b0;
end
else
begin
SHO <= # FFD error;
end
end
end
endmodule
`timescale 1ps/1ps
////////////////////////////////////////////////////////
//
// module plg_oserdese1_vlog
//
////////////////////////////////////////////////////////
//
// Programmable Load Generator (PLG)
// Divide by 2-8 counter with load enable output
//
//
/////////////////////////////////////////////////////////
//
// Inputs:
// c23: Selects between divide by 2 or 3
// c45: Selects between divide by 4 or 5
// c67: Selects between divide by 6 or 7
// sel: Selects which divide function is chosen
// 00:2 or 3, 01:4 or 5, 10:6 or 7, 11:8
// clk: High speed clock from DCM
// clkdiv: Low speed clock from DCM
// rst: Reset
//
//
//
// Outputs:
//
// load: Loads serdes register at terminal count
//
//
// Test attributes:
// INIT_LOADCNT: 4-bits to init counter
// SRTYPE: 1-bit to control synchronous or asynchronous operation
// SELFHEAL: 5-bits to control self healing feature
//
//
//
////////////////////////////////////////////////////////////////////////////////
//
module plg_oserdese1_vlog (c23, c45, c67, sel,
clk, clkdiv, rst,
load, IOCLK_GLITCH);
input c23, c45, c67;
input [1:0] sel;
input clk, clkdiv, rst;
output load;
output IOCLK_GLITCH;
wire SRTYPE;
wire [3:0] INIT_LOADCNT;
wire [4:0] SELFHEAL;
assign SRTYPE = 1'b1;
assign INIT_LOADCNT = 4'b0000;
assign SELFHEAL = 5'b00000;
reg q0, q1, q2, q3;
reg qhr, qlr;
reg load, mux;
wire cntrrst;
assign cntrrst = IOCLK_GLITCH | rst;
// Parameters for gate delays
parameter ffdcnt = 1;
parameter mxdcnt = 1;
parameter FFRST = 145; // clock to out delay for flop in PLSG
//////////////////////////////////////////////////
tri0 GSR = glbl.GSR;
always @(GSR)
begin
if (GSR)
begin
assign q3 = INIT_LOADCNT[3];
assign q2 = INIT_LOADCNT[2];
assign q1 = INIT_LOADCNT[1];
assign q0 = INIT_LOADCNT[0];
end
else
begin
deassign q3;
deassign q2;
deassign q1;
deassign q0;
end
end
// flops for counter
// asynchronous reset
always @ (posedge qhr or posedge clk)
begin
if (qhr & !SRTYPE)
begin
q0 <= # ffdcnt 1'b0;
q1 <= # ffdcnt 1'b0;
q2 <= # ffdcnt 1'b0;
q3 <= # ffdcnt 1'b0;
end
else if (!SRTYPE)
begin
q3 <= # ffdcnt q2;
q2 <= # ffdcnt (!(!q0 & !q2) & q1);
q1 <= # ffdcnt q0;
q0 <= # ffdcnt mux;
end
end
// synchronous reset
always @ (posedge clk)
begin
if (qhr & SRTYPE)
begin
q0 <= # ffdcnt 1'b0;
q1 <= # ffdcnt 1'b0;
q2 <= # ffdcnt 1'b0;
q3 <= # ffdcnt 1'b0;
end
else if (SRTYPE)
begin
q3 <= # ffdcnt q2;
q2 <= # ffdcnt (!(!q0 & !q2) & q1);
q1 <= # ffdcnt q0;
q0 <= # ffdcnt mux;
end
end
// mux settings for counter
always @ (sel or c23 or c45 or c67 or q0 or q1 or q2 or q3)
begin
case (sel)
2'b00: mux <= # mxdcnt (!q0 & !(c23 & q1));
2'b01: mux <= # mxdcnt (!q1 & !(c45 & q2));
2'b10: mux <= # mxdcnt (!q2 & !(c67 & q3));
2'b11: mux <= # mxdcnt !q3;
default: mux <= # mxdcnt 1'b0;
endcase
end
// mux decoding for load signal
always @ (sel or c23 or c45 or c67 or q0 or q1 or q2 or q3)
begin
case (sel)
2'b00: load <= # mxdcnt q0;
2'b01: load <= # mxdcnt q0 & q1;
2'b10: load <= # mxdcnt q0 & q2;
2'b11: load <= # mxdcnt q0 & q3;
default: load <= # mxdcnt 1'b0;
endcase
end
// flops to reset counter
// Low speed flop
// asynchronous reset
always @ (posedge cntrrst or posedge clkdiv)
begin
if (cntrrst & !SRTYPE)
begin
qlr <= # FFRST 1'b1;
end
else if (!SRTYPE)
begin
qlr <= # FFRST 1'b0;
end
end
// synchronous reset
always @ (posedge clkdiv)
begin
if (cntrrst & SRTYPE)
begin
qlr <= # FFRST 1'b1;
end
else if (SRTYPE)
begin
qlr <= # FFRST 1'b0;
end
end
// High speed flop
// asynchronous reset
always @ (posedge cntrrst or posedge clk)
begin
if (cntrrst & !SRTYPE)
begin
qhr <= # ffdcnt 1'b1;
end
else if (!SRTYPE)
begin
qhr <= # ffdcnt qlr;
end
end
// synchronous reset
always @ (posedge clk)
begin
if (cntrrst & SRTYPE)
begin
qhr <= # ffdcnt 1'b1;
end
else if (SRTYPE)
begin
qhr <= # ffdcnt qlr;
end
end
selfheal_oserdese1_vlog fixcntr (.dq3(q3), .dq2(q2), .dq1(q1), .dq0(q0),
.CLKDIV(clkdiv), .srint(qlr), .rst(rst),
.SHO(IOCLK_GLITCH));
endmodule
`timescale 1ps/1ps
////////////////////////////////////////////////////////
//
// module rank12d_oserdese1_vlog
//
//
// This model ONLY works for SERDES operation!!
// Does not include tristate circuit
//
//
////////////////////////////////////////////////////////
//
// Inputs:
// D1: Data input 1
// D2: Data input 2
// D3: Data input 3
// D4: Data input 4
// D5: Data input 5
// D6: Data input 6
// C: High speed clock from DCM
// OCE: Clock enable for output data flops
// SR: Set/Reset control. For the last 3 flops in OQ
// (d1rnk2, d2rnk2 and d2nrnk2) this function is
// controlled bythe attributes SRVAL_OQ. In SERDES mode,
// SR is a RESET ONLY for all other flops! The flops will
// still be RESET even if SR is programmed to a SET!
// CLKDIV: Low speed divided clock from DCM
// SHIFTIN1: Carry in data 1 for master from slave
// SHIFTIN2: Carry in data 2 for master from slave
//
//
//
// Outputs:
// data1: Data output mux for top flop
// data2: Data output mux for bottom flop
// SHIFTOUT1: Carry out data 1 for slave
// SHIFTOUT2: Carry out data 2 for slave
// load: Used for the tristate when combined into a single model
//
//
//
// Programmable Points
// DATA_RATE_OQ: Rate control for data output, 1-bit
// sdr (1), ddr (0)
// DATA_WIDTH: Input data width,
// 4-bits, values can be from 2 to 10
// SERDES_MODE: Denotes master (0) or slave (1)
// SIM_X_INPUT: This attribute is NOT SUPPORTED in this model!!!
//
//
//
// Programmable points for Test model
// SRTYPE: This is a 4-bit field Sets asynchronous (0) or synchronous (1) set/reset
// 1st bit (msb) sets rank1 flops, 2nd bit sets 4 flops in rank 2,
// 3rd bit sets "3 legacy flops, and 4th (lsb) bit sets the counter
// INIT_ORANK1: Init value for 6 registers in 1st rank (6-bits)
// INIT_ORANK2_PARTIAL: Init value for bottom 4 registers in the 2nd rank (4-bits)
// INIT_LOADCNT: Init value for the load counter (4-bits)
// The other 2 registers in the load counter have init bits, but are
// not supported in this model
// SERDES: Indicates that SERDES mode is chosen
// SLEFHEAL: 5-bit to set self heal circuit
//
//
////////////////////////////////////////////////////////////////////////////////
//
module rank12d_oserdese1_vlog (D1, D2, D3, D4, D5, D6, d2rnk2,
SHIFTIN1, SHIFTIN2,
C, CLKDIV, SR, OCE,
data1, data2, SHIFTOUT1, SHIFTOUT2,
DATA_RATE_OQ, DATA_WIDTH,
SERDES_MODE, load,
IOCLK_GLITCH,
INIT_OQ, SRVAL_OQ);
input D1, D2, D3, D4, D5, D6;
input d2rnk2;
input SHIFTIN1, SHIFTIN2;
input C, CLKDIV, SR, OCE;
input INIT_OQ, SRVAL_OQ;
output data1, data2;
output SHIFTOUT1, SHIFTOUT2;
output load;
output IOCLK_GLITCH;
// Programmable Points
input DATA_RATE_OQ;
input [3:0] DATA_WIDTH;
input SERDES_MODE;
wire DDR_CLK_EDGE, SERDES;
wire [3:0] SRTYPE;
wire [4:0] SELFHEAL;
wire [3:0] INIT_ORANK2_PARTIAL;
wire [5:0] INIT_ORANK1;
assign DDR_CLK_EDGE = 1'b1;
assign SERDES = 1'b1;
assign SRTYPE = 4'b1111;
assign SELFHEAL = 5'b00000;
assign INIT_ORANK2_PARTIAL = 4'b0000;
assign INIT_ORANK1 = 6'b000000;
reg d1r, d2r, d3r, d4r, d5r, d6r;
reg d3rnk2, d4rnk2, d5rnk2, d6rnk2;
reg data1, data2, data3, data4, data5, data6;
reg ddr_data, odata_edge, sdata_edge;
reg c23, c45, c67;
reg [1:0] sel;
wire C2p, C3;
wire loadint;
wire [3:0] seloq;
wire oqsr, oqrev;
wire [2:0] sel1_4;
wire [3:0] sel5_6;
wire [4:0] plgcnt;
assign C2p = (C & DDR_CLK_EDGE) | (!C & !DDR_CLK_EDGE);
assign C3 = !C2p;
assign plgcnt = {DATA_RATE_OQ,DATA_WIDTH};
assign sel1_4 = {SERDES,loadint,DATA_RATE_OQ};
assign sel5_6 = {SERDES,SERDES_MODE,loadint,DATA_RATE_OQ};
assign load = loadint;
assign seloq = {OCE,DATA_RATE_OQ,oqsr,oqrev};
assign oqsr = !SRTYPE[1] & SR & !SRVAL_OQ;
assign oqrev = !SRTYPE[1] & SR & SRVAL_OQ;
//////////////////////////////////////////////////
// Delay values
//
parameter FFD = 1; // clock to out delay for flip flops
// driven by clk
parameter FFCD = 1; // clock to out delay for flip flops
// driven by clkdiv
parameter MXD = 1; // 60 ps mux delay
parameter MXR1 = 1;
////////////////////////////////////////////
// Initialization of flops with GSR for test model
///////////////////////////////////////////
tri0 GSR = glbl.GSR;
always @(GSR)
begin
if (GSR)
begin
assign d6rnk2 = INIT_ORANK2_PARTIAL[3];
assign d5rnk2 = INIT_ORANK2_PARTIAL[2];
assign d4rnk2 = INIT_ORANK2_PARTIAL[1];
assign d3rnk2 = INIT_ORANK2_PARTIAL[0];
assign d6r = INIT_ORANK1[5];
assign d5r = INIT_ORANK1[4];
assign d4r = INIT_ORANK1[3];
assign d3r = INIT_ORANK1[2];
assign d2r = INIT_ORANK1[1];
assign d1r = INIT_ORANK1[0];
end
else
begin
deassign d6rnk2;
deassign d5rnk2;
deassign d4rnk2;
deassign d3rnk2;
deassign d6r;
deassign d5r;
deassign d4r;
deassign d3r;
deassign d2r;
deassign d1r;
end
end
/////////////////////////////////////////
// Assign shiftout1 and shiftout2
assign SHIFTOUT1 = d3rnk2 & SERDES_MODE;
assign SHIFTOUT2 = d4rnk2 & SERDES_MODE;
// last 4 flops which only have reset and init
// asynchronous operation
always @ (posedge C or posedge SR)
begin
begin
if (SR & !SRTYPE[2])
begin
d3rnk2 <= # FFD 1'b0;
d4rnk2 <= # FFD 1'b0;
d5rnk2 <= # FFD 1'b0;
d6rnk2 <= # FFD 1'b0;
end
else if (!SRTYPE[2])
begin
d3rnk2 <= # FFD data3;
d4rnk2 <= # FFD data4;
d5rnk2 <= # FFD data5;
d6rnk2 <= # FFD data6;
end
end
end
// synchronous operation
always @ (posedge C)
begin
begin
if (SR & SRTYPE[2])
begin
d3rnk2 <= # FFD 1'b0;
d4rnk2 <= # FFD 1'b0;
d5rnk2 <= # FFD 1'b0;
d6rnk2 <= # FFD 1'b0;
end
else if (SRTYPE[2])
begin
d3rnk2 <= # FFD data3;
d4rnk2 <= # FFD data4;
d5rnk2 <= # FFD data5;
d6rnk2 <= # FFD data6;
end
end
end
///////////////////////////////////////////////////
// First rank of flops for input data
//////////////////////////////////////////////////
// asynchronous operation
always @ (posedge CLKDIV or posedge SR)
begin
begin
if (SR & !SRTYPE[3])
begin
d1r <= # FFCD 1'b0;
d2r <= # FFCD 1'b0;
d3r <= # FFCD 1'b0;
d4r <= # FFCD 1'b0;
d5r <= # FFCD 1'b0;
d6r <= # FFCD 1'b0;
end
else if (!SRTYPE[3])
begin
d1r <= # FFCD D1;
d2r <= # FFCD D2;
d3r <= # FFCD D3;
d4r <= # FFCD D4;
d5r <= # FFCD D5;
d6r <= # FFCD D6;
end
end
end
// synchronous operation
always @ (posedge CLKDIV)
begin
begin
if (SR & SRTYPE[3])
begin
d1r <= # FFCD 1'b0;
d2r <= # FFCD 1'b0;
d3r <= # FFCD 1'b0;
d4r <= # FFCD 1'b0;
d5r <= # FFCD 1'b0;
d6r <= # FFCD 1'b0;
end
else if (SRTYPE[3])
begin
d1r <= # FFCD D1;
d2r <= # FFCD D2;
d3r <= # FFCD D3;
d4r <= # FFCD D4;
d5r <= # FFCD D5;
d6r <= # FFCD D6;
end
end
end
// Muxs for 2nd rank of flops
always @ (sel1_4 or d1r or d2rnk2 or d3rnk2)
begin
casex (sel1_4)
3'b100: data1 <= # MXR1 d3rnk2;
3'b110: data1 <= # MXR1 d1r;
3'b101: data1 <= # MXR1 d2rnk2;
3'b111: data1 <= # MXR1 d1r;
default: data1 <= # MXR1 d3rnk2;
endcase
end
always @ (sel1_4 or d2r or d3rnk2 or d4rnk2)
begin
casex (sel1_4)
3'b100: data2 <= # MXR1 d4rnk2;
3'b110: data2 <= # MXR1 d2r;
3'b101: data2 <= # MXR1 d3rnk2;
3'b111: data2 <= # MXR1 d2r;
default: data2 <= # MXR1 d4rnk2;
endcase
end
//Note: To stop data rate of 00 from being illegal, register data is fed to mux
always @ (sel1_4 or d3r or d4rnk2 or d5rnk2)
begin
casex (sel1_4)
3'b100: data3 <= # MXR1 d5rnk2;
3'b110: data3 <= # MXR1 d3r;
3'b101: data3 <= # MXR1 d4rnk2;
3'b111: data3 <= # MXR1 d3r;
default: data3 <= # MXR1 d5rnk2;
endcase
end
always @ (sel1_4 or d4r or d5rnk2 or d6rnk2)
begin
casex (sel1_4)
3'b100: data4 <= # MXR1 d6rnk2;
3'b110: data4 <= # MXR1 d4r;
3'b101: data4 <= # MXR1 d5rnk2;
3'b111: data4 <= # MXR1 d4r;
default: data4 <= # MXR1 d6rnk2;
endcase
end
always @ (sel5_6 or d5r or d6rnk2 or SHIFTIN1)
begin
casex (sel5_6)
4'b1000: data5 <= # MXR1 SHIFTIN1;
4'b1010: data5 <= # MXR1 d5r;
4'b1001: data5 <= # MXR1 d6rnk2;
4'b1011: data5 <= # MXR1 d5r;
4'b1100: data5 <= # MXR1 1'b0;
4'b1110: data5 <= # MXR1 d5r;
4'b1101: data5 <= # MXR1 d6rnk2;
4'b1111: data5 <= # MXR1 d5r;
default: data5 <= # MXR1 SHIFTIN1;
endcase
end
always @ (sel5_6 or D6 or d6r or SHIFTIN1 or SHIFTIN2)
begin
casex (sel5_6)
4'b1000: data6 <= # MXR1 SHIFTIN2;
4'b1010: data6 <= # MXR1 d6r;
4'b1001: data6 <= # MXR1 SHIFTIN1;
4'b1011: data6 <= # MXR1 d6r;
4'b1100: data6 <= # MXR1 1'b0;
4'b1110: data6 <= # MXR1 d6r;
4'b1101: data6 <= # MXR1 1'b0;
4'b1111: data6 <= # MXR1 d6r;
default: data6 <= # MXR1 SHIFTIN2;
endcase
end
// instantiate programmable load generator
plg_oserdese1_vlog ldgen (.c23(c23), .c45(c45), .c67(c67), .sel(sel),
.clk(C), .clkdiv(CLKDIV), .rst(SR),
.load(loadint), .IOCLK_GLITCH(IOCLK_GLITCH));
// Set value of counter in programmable load generator
always @ (plgcnt or c23 or c45 or c67 or sel)
begin
casex (plgcnt)
5'b00100: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b00110: begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b01000: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end
5'b01010: begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end
5'b10010: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b10011: begin c23=1'b1; c45=1'b0; c67=1'b0; sel=2'b00; end
5'b10100: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b01; end
5'b10101: begin c23=1'b0; c45=1'b1; c67=1'b0; sel=2'b01; end
5'b10110: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b10; end
5'b10111: begin c23=1'b0; c45=1'b0; c67=1'b1; sel=2'b10; end
5'b11000: begin c23=1'b0; c45=1'b0; c67=1'b0; sel=2'b11; end
default: $display("DATA_WIDTH %b and DATA_RATE_OQ %b at %t is an illegal value", DATA_WIDTH, DATA_RATE_OQ, $time);
endcase
end
endmodule
`timescale 1ps/1ps
//////////////////////////////////////////////////////////
//
// module trif_oserdese1_vlog
//
/////////////////////////////////////////////////////////
//
// Inputs:
//
// T1, T2, T3, T4: tristate inputs
// load: Programmable load generator output
// TCE: Tristate clock enable
// SR: Set/Reset control. For the last 3 flops in TQ
// (qt1, qt2 and qt2n) this function is
// controlled bythe attributes SRVAL_TQ. In SERDES mode,
// SR is a RESET ONLY for all other flops! The flops will
// still be RESET even if SR is programmed to a SET!
// C, C2: High speed clocks
// C2 drives 2nd latch and C3 (inverse of C2) drives
// 3rd latch in output section
// CLKDIV: Low speed clock
//
//
//
//
// Outputs:
//
// TQ: Output of tristate mux
//
//
// Programmable Options:
//
// DATA_RATE_TQ: 2-bit field for types of operaiton
// 0 (buf from T1), 1 (registered output from T1), 2 (ddr)
// TRISTATE_WIDTH: 2-bit field for input width
// 0 (width 1), 1 (width 2), 2 (width 4)
// INIT_TQ: Init TQ output (0,1)
// SRVAL_TQ: This bit to controls value of SR input.
// Only the last 3 flops (qt1, qt2 and qt2n) are
// affected by this bit.For SERDES mode, this bit
// should be set to '0' making SR a reset. This is the
// desired state since all other flops only
// respond to this pin as a reset. Their function
// cannot be changed. SR is 'O' for SET and '1' for RESET.
//
//
// Programmable Test Options:
// SRTYPE: Control S and R as asynchronous (0) or synchronous (1)
// 2-bit value. 1st bit (msb) controls the 4 input flops
// and the 2nd bit (lsb) controls the "3 legacy flops"
// DDR_CLK_EDGE: Same or opposite edge operation
//
//
//
////////////////////////////////////////////////////////////////////////////////
//
module trif_oserdese1_vlog (T1, T2, T3, T4, load,
C, CLKDIV, SR, TCE,
DATA_RATE_TQ, TRISTATE_WIDTH,
INIT_TQ, SRVAL_TQ,
data1, data2);
input T1, T2, T3, T4, load;
input C, CLKDIV, SR, TCE;
input [1:0] TRISTATE_WIDTH;
input [1:0] DATA_RATE_TQ;
input INIT_TQ, SRVAL_TQ;
output data1, data2;
wire DDR_CLK_EDGE;
wire [3:0] INIT_TRANK1;
wire [1:0] SRTYPE;
assign SRTYPE = 2'b11;
assign DDR_CLK_EDGE = 1'b1;
assign INIT_TRANK1 = 4'b0000;
reg t1r, t2r, t3r, t4r;
reg qt1, qt2, qt2n;
reg data1, data2;
reg sdata_edge, odata_edge, ddr_data;
wire C2p, C3;
wire load;
wire [6:0] tqsel;
wire [4:0] sel;
assign sel = {load,DATA_RATE_TQ,TRISTATE_WIDTH};
//////////////////////////////////////////////////
// Parameters for gate delays
parameter ffd = 1;
parameter mxd = 1;
/////////////////////////////
// Initialization of Flops
////////////////////////////
tri0 GSR = glbl.GSR;
always @(GSR)
begin
if (GSR)
begin
assign t1r = INIT_TRANK1[0];
assign t2r = INIT_TRANK1[1];
assign t3r = INIT_TRANK1[2];
assign t4r = INIT_TRANK1[3];
end
else
begin
deassign t1r;
deassign t2r;
deassign t3r;
deassign t4r;
end
end
// First rank of flops
// asynchronous reset operation
always @ (posedge CLKDIV or posedge SR)
begin
begin
if (SR & !SRTYPE[1])
begin
t1r <= # ffd 1'b0;
t2r <= # ffd 1'b0;
t3r <= # ffd 1'b0;
t4r <= # ffd 1'b0;
end
else if (!SRTYPE[1])
begin
t1r <= # ffd T1;
t2r <= # ffd T2;
t3r <= # ffd T3;
t4r <= # ffd T4;
end
end
end
// synchronous reset operation
always @ (posedge CLKDIV)
begin
begin
if (SR & SRTYPE[1])
begin
t1r <= # ffd 1'b0;
t2r <= # ffd 1'b0;
t3r <= # ffd 1'b0;
t4r <= # ffd 1'b0;
end
else if (SRTYPE[1])
begin
t1r <= # ffd T1;
t2r <= # ffd T2;
t3r <= # ffd T3;
t4r <= # ffd T4;
end
end
end
// Data Muxs for tristate otuput signals
always @ (sel or T1 or t1r or t3r)
begin
casex (sel)
5'b00000: data1 <= # mxd T1;
5'b10000: data1 <= # mxd T1;
5'bX0000: data1 <= # mxd T1;
5'b00100: data1 <= # mxd T1;
5'b10100: data1 <= # mxd T1;
5'bX0100: data1 <= # mxd T1;
5'b01001: data1 <= # mxd T1;
5'b11001: data1 <= # mxd T1;
5'b01010: data1 <= # mxd t3r;
5'b11010: data1 <= # mxd t1r;
// CR 551953 -- enabled TRISTATE_WIDTH to be 1 in DDR mode. No func change, but removed warnings
5'b01000: ;
5'b11000: ;
5'bX1000: ;
default: $display("DATA_RATE_TQ %b and/or TRISTATE_WIDTH %b at time %t are not supported by OSERDES", DATA_RATE_TQ,TRISTATE_WIDTH,$time);
endcase
end
// For data 2, width of 1 is inserted as acceptable for buf and sdr
// The capability exists in the device if the feature is added
always @ (sel or T2 or t2r or t4r)
begin
casex (sel)
5'b00000: data2 <= # mxd T2;
5'b00100: data2 <= # mxd T2;
5'b10000: data2 <= # mxd T2;
5'b10100: data2 <= # mxd T2;
5'bX0000: data2 <= # mxd T2;
5'bX0100: data2 <= # mxd T2;
5'b00X00: data2 <= # mxd T2;
5'b10X00: data2 <= # mxd T2;
5'bX0X00: data2 <= # mxd T2;
5'b01001: data2 <= # mxd T2;
5'b11001: data2 <= # mxd T2;
5'bX1001: data2 <= # mxd T2;
5'b01010: data2 <= # mxd t4r;
5'b11010: data2 <= # mxd t2r;
// CR 551953 -- enabled TRISTATE_WIDTH to be 1 in DDR mode. No func change, but removed warnings
5'b01000: ;
5'b11000: ;
5'bX1000: ;
default: $display("DATA_RATE_TQ %b and/or TRISTATE_WIDTH %b at time %t are not supported by OSERDES", DATA_RATE_TQ,TRISTATE_WIDTH,$time);
endcase
end
endmodule
`timescale 1ps/1ps
//////////////////////////////////////////////////////////
//
// module txbuffer_oserdese1_vlog
//
/////////////////////////////////////////////////////////
//
// FIFO and Control circuit for OSERDES
module txbuffer_oserdese1_vlog (iodelay_state, qmux1, qmux2, tmux1, tmux2,
d1, d2, t1, t2, trif,
WC, ODV, extra,
clk, clkdiv, bufo, bufop, rst,
ODELAY_USED, DDR3_DATA,
DDR3_MODE);
input d1, d2, t1, t2;
input trif;
input WC, ODV;
input rst;
input clk, clkdiv, bufo, bufop;
input ODELAY_USED, DDR3_DATA;
input DDR3_MODE;
output iodelay_state, extra;
output qmux1, qmux2, tmux1, tmux2;
wire WC_DELAY;
assign WC_DELAY = 1'b0;
wire rd_gap1;
wire rst_bufo_p, rst_bufg_p;
wire rst_bufo_rc, rst_bufg_wc, rst_cntr, rst_bufop_rc;
wire [1:0] qwc, qrd;
wire bufo_out;
wire inv_qmux1, inv_qmux2, inv_tmux1, inv_tmux2;
fifo_tdpipe_oserdese1_vlog data1 (.muxout(inv_qmux1), .din(~d1), .qwc(qwc), .qrd(qrd),
.rd_gap1(rd_gap1),
.bufg_clk(clk), .bufo_clk(bufo), .rst_bufo_p(rst_bufo_p), .rst_bufg_p(rst_bufg_p),
.DDR3_DATA(DDR3_DATA), .extra(extra), .ODV(ODV), .DDR3_MODE(DDR3_MODE)
);
fifo_tdpipe_oserdese1_vlog data2 (.muxout(inv_qmux2), .din(~d2), .qwc(qwc), .qrd(qrd),
.rd_gap1(rd_gap1),
.bufg_clk(clk), .bufo_clk(bufo), .rst_bufo_p(rst_bufo_p), .rst_bufg_p(rst_bufg_p),
.DDR3_DATA(DDR3_DATA), .extra(extra), .ODV(ODV), .DDR3_MODE(DDR3_MODE)
);
fifo_tdpipe_oserdese1_vlog tris1 (.muxout(inv_tmux1), .din(~t1), .qwc(qwc), .qrd(qrd),
.rd_gap1(rd_gap1),
.bufg_clk(clk), .bufo_clk(bufo), .rst_bufo_p(rst_bufo_p), .rst_bufg_p(rst_bufg_p),
.DDR3_DATA(DDR3_DATA), .extra(extra), .ODV(ODV), .DDR3_MODE(DDR3_MODE)
);
fifo_tdpipe_oserdese1_vlog tris2 (.muxout(inv_tmux2), .din(~t2), .qwc(qwc), .qrd(qrd),
.rd_gap1(rd_gap1),
.bufg_clk(clk), .bufo_clk(bufo), .rst_bufo_p(rst_bufo_p), .rst_bufg_p(rst_bufg_p),
.DDR3_DATA(DDR3_DATA), .extra(extra), .ODV(ODV), .DDR3_MODE(DDR3_MODE)
);
wire qmux1 = ~inv_qmux1;
wire qmux2 = ~inv_qmux2;
wire tmux1 = ~inv_tmux1;
wire tmux2 = ~inv_tmux2;
fifo_reset_oserdese1_vlog rstckt (.rst_bufo_p(rst_bufo_p), .rst_bufo_rc(rst_bufo_rc),
.rst_bufg_p(rst_bufg_p), .rst_bufg_wc(rst_bufg_wc),
.rst_cntr(rst_cntr),
.bufg_clk(clk), .bufo_clk(bufo), .clkdiv(clkdiv), .rst(rst),
.divide_2(WC_DELAY), .bufop_clk(bufop), .rst_bufop_rc(rst_bufop_rc)
);
fifo_addr_oserdese1_vlog addcntr (.qwc(qwc), .qrd(qrd), .rd_gap1(rd_gap1), .rst_bufg_wc(rst_bufg_wc), .rst_bufo_rc(rst_bufo_rc), .bufg_clk(clk), .bufo_clk(bufo),
.data(DDR3_DATA), .extra(extra), .rst_bufop_rc(rst_bufop_rc), .bufop_clk(bufop)
);
iodlyctrl_npre_oserdese1_vlog idlyctrl (.iodelay_state(iodelay_state), .bufo_out(bufo_out), .rst_cntr(rst_cntr),
.wc(WC), .trif(trif),
.rst(rst_bufg_p), .bufg_clk(clk), .bufo_clk(bufo), .bufg_clkdiv(clkdiv),
.ddr3_dimm(ODELAY_USED), .wl6(WC_DELAY)
);
endmodule
`timescale 1ps/1ps
////////////////////////////////////////////////////////
//
// module fifo_tdpipe_oserdese1_vlog
//
////////////////////////////////////////////////////////
// FIFO for write path
module fifo_tdpipe_oserdese1_vlog (muxout, din, qwc, qrd,
rd_gap1,
bufg_clk, bufo_clk, rst_bufo_p, rst_bufg_p,
DDR3_DATA, extra, ODV, DDR3_MODE
);
input din;
input [1:0] qwc, qrd;
input rd_gap1;
input rst_bufo_p, rst_bufg_p;
input bufg_clk, bufo_clk;
input DDR3_DATA, ODV;
input extra;
input DDR3_MODE;
output muxout;
reg muxout;
reg qout1, qout2;
reg qout_int, qout_int2;
reg [4:1] fifo;
reg cin1;
reg omux;
wire [2:0] sel;
reg pipe1, pipe2;
wire selqoi, selqoi2;
wire [2:0] selmuxout;
// 4 flops that make up the basic FIFO. They are all clocked
// off of fast BUFG. The first flop is the top flop in the chain.
// The CE input is used to mux the inputs. If the flop is selected,
// CE is high and it takes data from the output of the mux. If the
// flop is not selected, it retains its data.
always @ (posedge bufg_clk or posedge rst_bufg_p)
begin
if (rst_bufg_p)
begin
fifo <= #10 4'b0000;
end
else if (!qwc[1] & !qwc[0])
begin
fifo <= #10 {fifo[4:2],din};
end
else if (!qwc[1] & qwc[0])
begin
fifo <= #10 {fifo[4:3],din,fifo[1]};
end
else if (qwc[1] & qwc[0])
begin
fifo <= #10 {fifo[4],din,fifo[2:1]};
end
else if (qwc[1] & !qwc[0])
begin
fifo <= #10 {din,fifo[3:1]};
end
end
// Capture stage top
// This is the top flop of the "3 flops" for ODDR. This flop, along with the read
// counter will be clocked off of bufo. A 4:1 mux wil decode the outputs of the
// read counter and load the write data. A subsequent 2:1 mux will decode between
// the fifo and the legacy operation
// OMUX
always @ (qrd or fifo)
begin
case (qrd)
2'b00: omux <= #10 fifo[1];
2'b01: omux <= #10 fifo[2];
2'b10: omux <= #10 fifo[4];
2'b11: omux <= #10 fifo[3];
default: omux <= #10 fifo[1];
endcase
end
always @ (posedge bufo_clk or posedge rst_bufo_p)
begin
if (rst_bufo_p)
begin
qout_int <= #10 1'b0;
qout_int2 <= #10 1'b0;
end
else
begin
qout_int <= #10 omux;
qout_int2 <= #10 qout_int;
end
end
assign #10 selqoi = ODV | rd_gap1;
always @ (selqoi or qout_int or omux)
begin
case(selqoi)
1'b0: qout1 <= #10 omux;
1'b1: qout1 <= #10 qout_int;
default: qout1 <= #10 omux;
endcase
end
assign #10 selqoi2 = ODV & rd_gap1;
always @ (selqoi2 or qout_int2 or qout_int)
begin
case(selqoi2)
1'b0: qout2 <= #10 qout_int;
1'b1: qout2 <= #10 qout_int2;
default qout2 <= #10 qout_int;
endcase
end
assign #14 selmuxout = {DDR3_MODE,DDR3_DATA,extra};
always @ (selmuxout or din or omux or qout1 or qout2)
begin
case (selmuxout)
3'b000: muxout = #1 din;
3'b001: muxout = #1 din;
3'b010: muxout = #1 din;
3'b011: muxout = #1 din;
3'b100: muxout = #1 omux;
3'b101: muxout = #1 omux;
3'b110: muxout = #1 qout1;
3'b111: muxout = #1 qout2;
default: muxout = #10 din;
endcase
end
endmodule
`timescale 1ps/1ps
////////////////////////////////////////////////////////
//
// module fifo_reset_oserdese1_vlog
//
////////////////////////////////////////////////////////
//
// TX FIFO reset
//
// This design performs 2 functions. One function is to reset all the
// flops in the TX FIFO. The other function is to respond to the signal
// rst_cntr. This signal comes from iodlyctrl and will be used to initiate an
// orderly transition to switch the DQ/DQS I/O from and read to a write.
// This process is required only for DDR3 DIMM support because the IODELAY
// is used for both the inputs and the outputs. The signal from the
// squelch circuit is a present fabric output. An additional input
// indicating that a write command was issued will be
// required for all I/O to support this signal.
//
// This design uses an asynchronous reset to reset all flops. After the
// reset is disabled, a 0 is propagated through the pipe stages to terminate
// the reset. The first 2 flops run off of the clkdiv domain. Their output
// feeds a latch to cross between the clkdiv and bufg_clk domain. The pipe
// stage for the bufg_clk domain is 3 deep, where the last flop is the
// reset signal for the bufg_clk domain. The 2nd flop of the bufg_clk pipe
// is fed to 2 flops that are in the bufo_clk domain. The 2 flops are
// to resolve metastability between the 2 clock domains.
//
// The circuit to enable an orderly transition from read to write uses the
// PREAMBLE_SYNCHED output of a portion of the squelch circuit. This pulse
// will initiate the reset sequence and also generate an enable which will
// switch the IODELAY from an IDELAY to an ODELAY. Timing is as specified in
// the "State of the Union" presentation.
//
//
module fifo_reset_oserdese1_vlog (rst_bufo_p, rst_bufo_rc,
rst_bufg_p, rst_bufg_wc,
rst_cntr,
bufg_clk, bufo_clk, clkdiv, rst,
divide_2, bufop_clk, rst_bufop_rc
);
input rst_cntr;
input rst;
input bufg_clk, bufo_clk, clkdiv;
input bufop_clk;
// Memory cell input to support divide by 1 operation
input divide_2;
output rst_bufo_p, rst_bufo_rc;
output rst_bufg_p, rst_bufg_wc;
output rst_bufop_rc;
reg [1:0] clkdiv_pipe;
reg bufg_pipe;
reg rst_cntr_reg;
reg [2:0] bufo_rst_p, bufo_rst_rc;
reg [1:0] bufop_rst_rc;
reg [1:0] bufg_rst_p, bufg_rst_wc;
wire bufg_clkdiv_latch, ltint1, ltint2, ltint3;
wire latch_in;
// 2 stage pipe for clkdiv domain to allow user to properly
// time everything
always @ (posedge bufg_clk or posedge rst)
begin
if (rst)
begin
rst_cntr_reg <= #10 1'b0;
end
else
begin
rst_cntr_reg <= #10 rst_cntr;
end
end
always @ (posedge clkdiv or posedge rst)
begin
if (rst)
begin
clkdiv_pipe <= #10 2'b11;
end
else
begin
clkdiv_pipe <= #10 {clkdiv_pipe[0],1'b0};
end
end
// Latch to compensate for clkdiv and bufg_clk clock skew
// Built of actual gates
assign #1 latch_in = clkdiv_pipe[1];
assign #1 bufg_clkdiv_latch = !(ltint1 && ltint3);
assign #1 ltint1 = !(latch_in && bufg_clk);
assign #1 ltint2 = !(ltint1 && bufg_clk);
assign #1 ltint3 = !(bufg_clkdiv_latch && ltint2);
// BUFG flop to register latch signal
always @ (posedge bufg_clk or posedge rst)
begin
if (rst)
begin
bufg_pipe <= #10 1'b1;
end
else
begin
bufg_pipe <= #10 bufg_clkdiv_latch;
end
end
// BUFG clock domain resests
always @ (posedge bufg_clk or posedge rst)
begin
if (rst)
begin
bufg_rst_p <= #10 2'b11;
end
else
begin
bufg_rst_p <= #10 {bufg_rst_p[0],bufg_pipe};
end
end
always @ (posedge bufg_clk or posedge rst_cntr or posedge rst)
begin
if (rst || rst_cntr)
begin
bufg_rst_wc <= #10 2'b11;
end
else
begin
bufg_rst_wc <= #10 {bufg_rst_wc[0],bufg_pipe};
end
end
// BUFO clock domain Resets
always @ (posedge bufo_clk or posedge rst)
begin
if (rst)
begin
bufo_rst_p <= #10 3'b111;
end
else
begin
bufo_rst_p <= #10 {bufo_rst_p[1:0],bufg_pipe};
end
end
always @ (posedge bufo_clk or posedge rst or posedge rst_cntr)
begin
if (rst || rst_cntr)
begin
bufo_rst_rc <= #10 3'b111;
end
else
begin
bufo_rst_rc <= #10 {bufo_rst_rc[1:0],bufg_pipe};
end
end
always @ (posedge bufop_clk or posedge rst or posedge rst_cntr)
begin
if (rst || rst_cntr)
begin
bufop_rst_rc <= #10 2'b11;
end
else
begin
bufop_rst_rc <= #10 {bufop_rst_rc[0],bufg_pipe};
end
end
// final reset assignments
assign rst_bufo_rc = bufo_rst_rc[1];
assign rst_bufo_p = bufo_rst_p[1];
assign rst_bufop_rc = bufop_rst_rc[1];
assign rst_bufg_wc = bufg_rst_wc[1];
assign rst_bufg_p = bufg_rst_p[1];
endmodule
`timescale 1ps/1ps
////////////////////////////////////////////////////////
//
// module fifo_addr_oserdese1_vlog
//
////////////////////////////////////////////////////////
// Read and Write address generators for TX FIFO
//
// This circuit contains 2 greycode read and write address generators
// that will be used with the TX FIFO. Both counters generate a
// count sequence of 00 -> 01 -> 11 -> 10 -> 00.
module fifo_addr_oserdese1_vlog (qwc, qrd, rd_gap1, rst_bufg_wc, rst_bufo_rc, bufg_clk, bufo_clk,
data, extra, rst_bufop_rc, bufop_clk
);
input bufg_clk, bufo_clk;
input rst_bufo_rc, rst_bufg_wc;
input rst_bufop_rc;
input data; // mc to tell if I/O is DDR3 DQ or DQS
input bufop_clk;
output qwc, qrd;
output rd_gap1, extra;
reg [1:0] qwc;
reg [1:0] qrd;
reg stop_rd, rd_gap1, extra;
reg rd_cor, rd_cor_cnt, rd_cor_cnt1;
wire qwc0_latch, qwc1_latch;
wire li01, li02, li03;
wire li11, li12, li13;
wire qwc0_latchn, qwc1_latchn;
wire li01n, li02n, li03n;
wire li11n, li12n, li13n;
reg stop_rdn, rd_cor_cntn, rd_cor_cnt1n, stop_rc;
reg [1:0] qwcd;
reg [1:0] qrdd;
reg stop_rdd, rd_gap1d, extrad;
reg rd_cord, rd_cor_cntd, rd_cor_cnt1d;
wire qwcd0_latch, qwcd1_latch;
wire li01d, li02d, li03d;
wire li11d, li12d, li13d;
// Write counter
// The write counter uses 2 flops to create the grey code pattern of
// 00 -> 01 -> 11 -> 10 -> 00. The write counter is initialized
// to 11 and the read counter will be initialized to 00. This gives
// a basic 2 clock separation to compensate for the phase differences.
// The write counter is clocked off of the bufg clock
always @ (posedge bufg_clk or posedge rst_bufg_wc)
begin
if (rst_bufg_wc)
begin
qwc <= # 10 2'b11;
end
else if (qwc[1] ^ qwc[0])
begin
qwc[1] <= # 10 ~qwc[1];
qwc[0] <= # 10 qwc[0];
end
else
begin
qwc[1] <= # 10 qwc[1];
qwc[0] <= # 10 ~qwc[0];
end
end
// Read counter
// The read counter uses 2 flops to create the grey code pattern of
// 00 -> 01 -> 11 -> 10 -> 00. The read counter is initialized
// to 00 and the write counter will be initialized to 11. This gives
// a basic 2 clock separation to compensate for the phase differences.
// The read counter is clocked off of the bufo clock
always @ (posedge bufo_clk or posedge rst_bufo_rc)
begin
if (rst_bufo_rc)
begin
qrd <= # 10 2'b00;
end
else if (stop_rd && !data)
begin
qrd <= #10 qrd;
end
else if (qrd[1] ^ qrd[0])
begin
qrd[1] <= # 10 ~qrd[1];
qrd[0] <= # 10 qrd[0];
end
else
begin
qrd[1] <= # 10 qrd[1];
qrd[0] <= # 10 ~qrd[0];
end
end
always @ (posedge bufo_clk or posedge rst_bufo_rc)
begin
if (rst_bufo_rc)
begin
rd_gap1 <= # 10 1'b0;
end
// else if ((qwc1_latch && qwc0_latch) && (qrd[0] ^ qrd[1]))
else if ((qwc1_latch && qwc0_latch) && (qrd[0]))
begin
rd_gap1 <= # 10 1'b1;
end
else
begin
rd_gap1 <= # 10 rd_gap1;
end
end
// Looking for 11
assign #1 qwc0_latch = !(li01 & li03);
assign #1 li01 = !(qwc[0] & bufo_clk);
assign #1 li02 = !(li01 & bufo_clk);
assign #1 li03 = !(qwc0_latch & li02);
assign #1 qwc1_latch = !(li11 & li13);
assign #1 li11 = !(qwc[1] & bufo_clk);
assign #1 li12 = !(li11 & bufo_clk);
assign #1 li13 = !(qwc1_latch & li12);
// The following counter is to match the control counter to see if the
// read counter did a hold after reset. This knowledge will enable the
// computation of the 'extra' output. This in turn can add the
// proper number of pipe stages to the output. The circuit must use
// the output of BUFO and not be modified by ODELAY. This is because
// the control pins PP clock was not modified by BUFO. If the
// control pins PP clock was modified by BUFO, the reset must be done
// with this in mind.
// Read counter
// The read counter uses 2 flops to create the grey code pattern of
// 00 -> 01 -> 11 -> 10 -> 00. The read counter is initialized
// to 00 and the write counter will be initialized to 11. This gives
// a basic 2 clock separation to compensate for the phase differences.
// The read counter is clocked off of the bufo clock
always @ (posedge bufop_clk or posedge rst_bufop_rc)
begin
if (rst_bufop_rc)
begin
qrdd <= # 10 2'b00;
end
else if (qrdd[1] ^ qrdd[0])
begin
qrdd[1] <= # 10 ~qrdd[1];
qrdd[0] <= # 10 qrdd[0];
end
else
begin
qrdd[1] <= # 10 qrdd[1];
qrdd[0] <= # 10 ~qrdd[0];
end
end
// Looking for 11
assign #1 qwcd0_latch = !(li01d & li03d);
assign #1 li01d = !(qwc[0] & bufop_clk);
assign #1 li02d = !(li01d & bufop_clk);
assign #1 li03d = !(qwcd0_latch & li02d);
assign #1 qwcd1_latch = !(li11d & li13d);
assign #1 li11d = !(qwc[1] & bufop_clk);
assign #1 li12d = !(li11d & bufop_clk);
assign #1 li13d = !(qwcd1_latch & li12d);
// Circuit to fix read address counters in non data pins
always @ (posedge bufop_clk or posedge rst_bufo_rc)
begin
if (rst_bufop_rc)
begin
stop_rd <= # 10 1'b0;
rd_cor_cnt <= #10 1'b0;
rd_cor_cnt1 <= #10 1'b0;
end
else if (((qwcd1_latch && qwcd0_latch) && (qrdd[0] ^ qrdd[1]) && !rd_cor_cnt1))
begin
stop_rd <= #10 1'b1;
rd_cor_cnt <= #10 1'b1;
rd_cor_cnt1 <= #10 rd_cor_cnt;
end
else
begin
stop_rd <= #10 1'b0;
rd_cor_cnt <= #10 1'b1;
rd_cor_cnt1 <= #10 rd_cor_cnt;
end
end
// Circuit to inform data if control counters habe been fixed
always @ (posedge bufop_clk or posedge rst_bufop_rc)
begin
if (rst_bufop_rc)
begin
extra <= #10 1'b0;
end
else if (stop_rd)
begin
extra <= #10 1'b1;
end
end
endmodule
`timescale 1ps/1ps
////////////////////////////////////////////////////////
//
// module iodlyctrl_npre_oserdese1_vlog
//
////////////////////////////////////////////////////////
//
// Circuit to automatically switch IODELAY from IDELAY to ODELAY using knowledge
// of write command. This circuit forces the user to wait 3 extra CLK/CLK# cycles
// when performing a read to write turnaround. The JEDEC DDR3 spec states that
// the turnaround can be done in 2 clock cycles. This circuit requires 5 clock
// cycles.
// This circuit is only used for a DDR3 appplication that uses DIMMs
module iodlyctrl_npre_oserdese1_vlog (iodelay_state, bufo_out, rst_cntr,
wc, trif,
rst, bufg_clk, bufo_clk, bufg_clkdiv,
ddr3_dimm, wl6
);
input wc;
input trif;
input rst;
input bufo_clk, bufg_clk, bufg_clkdiv;
input ddr3_dimm, wl6;
output iodelay_state, rst_cntr;
output bufo_out;
reg qw0cd, qw1cd;
reg turn, turn_p1;
reg rst_cntr;
reg w_to_w;
reg [2:0] wtw_cntr;
reg cmd0, cmd0_n6, cmd0_6, cmd1;
wire wr_cmd0;
wire lt0int1, lt0int2, lt0int3;
wire lt1int1, lt1int2, lt1int3;
wire latch_in;
reg qwcd;
assign bufo_out = bufo_clk;
// create turn signal for IODELAY
assign iodelay_state = (trif && ~w_to_w) & ((~turn && ~turn_p1) || ~ddr3_dimm);
// Registers to detect write command
// Registers using bufg clkdiv
always @ (posedge bufg_clkdiv)
begin
if (rst)
begin
qwcd <= #10 0;
end
else
begin
qwcd <= #10 wc;
end
end
// Latch to allow skew between CLK and CLKDIV from BUFGs
assign #1 wr_cmd0 = !(lt0int1 && lt0int3);
assign #1 lt0int1 = !(qwcd && bufg_clk);
assign #1 lt0int2 = !(lt0int1 && bufg_clk);
assign #1 lt0int3 = !(wr_cmd0 && lt0int2);
always @ (posedge bufg_clk)
begin
if (rst)
begin
cmd0_n6 <= #10 1'b0;
cmd0_6 <= #10 1'b0;
end
else
begin
cmd0_n6 <= #10 wr_cmd0;
cmd0_6 <= #10 cmd0_n6;
end
end
// mux to add extra pipe stage for WL = 6
always @ (cmd0_n6 or wl6 or cmd0_6)
begin
case (wl6)
1'b0: cmd0 <= #10 cmd0_n6;
1'b1: cmd0 <= #10 cmd0_6;
default: cmd0 <= #10 cmd0_n6;
endcase
end
// Turn IODELAY and reset FIFO read/write counters
//always @ (posedge bufg_clk)
// begin
// if (rst)
//
// begin
// turn <= #10 1'b0;
// rst_cntr <= #10 1'b0;
// end
// else if (w_to_w)
// begin
// turn <= #10 1'b1;
// rst_cntr <= #10 1'b0;
// end
// else if (cmd0 && !turn)
// begin
// turn <= #10 1'b1;
// rst_cntr <= #10 1'b1;
// end
// else if (~trif)
// begin
// turn <= #10 1'b0;
// rst_cntr <= #10 1'b0;
// end
// else if (turn)
// begin
// turn <= #10 1'b1;
// rst_cntr <= #10 1'b0;
// end
// else
// begin
// turn <= #10 1'b0;
// rst_cntr <= #10 1'b0;
// end
// end
always @ (posedge bufg_clk)
begin
begin
if (rst)
begin
turn <= #10 1'b0;
end
else
begin
turn <= #10 (w_to_w || (cmd0 && ~turn) ||
(~wtw_cntr[2] && turn));
end
end
begin
if (rst)
begin
rst_cntr <= #10 1'b0;
end
else
begin
rst_cntr <= #10 (~w_to_w && (cmd0 && ~turn));
end
end
end
always @ (posedge bufg_clk)
begin
if (rst)
begin
turn_p1 <= #10 1'b0;
end
else
begin
turn_p1 <= #10 turn;
end
end
// Detect multiple write commands and don"t turn IODELAY
//always @ (posedge bufg_clk)
// begin
// if (rst)
// begin
// w_to_w <= #10 1'b0;
// wtw_cntr <= #10 3'b000;
// end
// else if (cmd0 && turn_p1)
// begin
// w_to_w <= #10 1'b1;
// wtw_cntr <= #10 3'b000;
// end
// else if (wtw_cntr == 3'b101)
// begin
// w_to_w <= #10 1'b0;
// wtw_cntr <= #10 3'b000;
// end
// else if (w_to_w)
// begin
// w_to_w <= #10 1'b1;
// wtw_cntr <= #10 wtw_cntr + 1;
// end
// end
always @ (posedge bufg_clk)
begin
begin
if (rst)
begin
w_to_w <= #10 1'b0;
end
else
begin
w_to_w <= #10 ((cmd0 && turn_p1) ||
(w_to_w && (~wtw_cntr[2] || ~wtw_cntr[1])));
end
end
end
always @ (posedge bufg_clk)
begin
if (!(w_to_w || turn) || (cmd0 && turn_p1))
begin
wtw_cntr <= #10 3'b000;
end
else if (w_to_w || turn_p1)
begin
wtw_cntr <= #10 wtw_cntr + 1;
end
end
endmodule
`timescale 1ps/1ps
////////////////////////////////////////////////////////
//
// MODULE dout_oserdese1_vlog
//
// This model ONLY works for SERDES operation!!
// Does not include tristate circuit
//
/////////////////////////////////////////////////////////
//
// Inputs:
// data1: Data from FIFO
// data2: Data input FIFO
// CLK: High speed clock from DCM
// BUFO: Clock from performance path
// OCE: Clock enable for output data flops
// SR: Set/Reset control. For the last 3 flops in OQ
// (d1rnk2, d2rnk2 and d2nrnk2) this function is
// controlled bythe attributes SRVAL_OQ. In SERDES mode,
// SR is a RESET ONLY for all other flops! The flops will
// still be RESET even if SR is programmed to a SET!
//
//
//
// Outputs:
// OQ: Data output
//
//
//
// Programmable Points
// DATA_RATE_OQ: Rate control for data output, 1-bit
// sdr (1), ddr (0)
// INIT_OQ: Init OQ output "flop"
// SRVAL_OQ: This bit to controls value of SR input.
// Only the last 3 flops (d1rnk2, d2rnk2 and d2nrnk2)
// are affected by this bit.For SERDES mode, this bit
// should be set to '0' making SR a reset. This is the
// desired state since all other flops only respond to
// this pin as a reset. Their function cannot be
// changed. SR is '1' for SET and '0' for RESET.
//
//
//
// Programmable points for Test model
// SRTYPE: This is a 4-bit field Sets asynchronous (0) or synchronous (1) set/reset
// 1st bit (msb) sets rank1 flops, 2nd bit sets 4 flops in rank 2,
// 3rd bit sets "3 legacy flops, and 4th (lsb) bit sets the counter
// DDR_CLK_EDGE: Controls use of 2 or 3 flops for single case. Default to 1 for
// SERDES operation
//
//
///////////////////////////////////////////////////////////////////////////////
//
module dout_oserdese1_vlog (data1, data2,
CLK, BUFO, SR, OCE,
OQ, d2rnk2,
DATA_RATE_OQ,
INIT_OQ, SRVAL_OQ,
DDR3_MODE);
input data1, data2;
input CLK, SR, OCE;
input BUFO;
input INIT_OQ, SRVAL_OQ;
input DDR3_MODE;
output OQ;
output d2rnk2;
// Programmable Points
input DATA_RATE_OQ;
wire DDR_CLK_EDGE;
wire [3:0] SRTYPE;
assign DDR_CLK_EDGE = 1'b1;
assign SRTYPE = 4'b1111;
reg d1rnk2, d2rnk2, d2nrnk2;
reg OQ;
reg ddr_data, odata_edge, sdata_edge;
reg c23, c45, c67;
wire C;
wire C2p, C3;
wire [3:0] seloq;
wire oqsr, oqrev;
assign C = (BUFO & DDR3_MODE) | (CLK & !DDR3_MODE);
assign C2p = (C & DDR_CLK_EDGE) | (!C & !DDR_CLK_EDGE);
assign C3 = !C2p;
assign seloq = {OCE,DATA_RATE_OQ,oqsr,oqrev};
assign oqsr = !SRTYPE[1] & SR & !SRVAL_OQ;
assign oqrev = !SRTYPE[1] & SR & SRVAL_OQ;
//////////////////////////////////////////////////
// Delay values
//
parameter FFD = 1; // clock to out delay for flip flops
// driven by clk
parameter FFCD = 1; // clock to out delay for flip flops
// driven by clkdiv
parameter MXD = 1; // 60 ps mux delay
parameter MXR1 = 1;
////////////////////////////////////////////
// Initialization of flops with GSR for test model
///////////////////////////////////////////
tri0 GSR = glbl.GSR;
always @(GSR)
begin
if (GSR)
begin
assign OQ = INIT_OQ;
assign d1rnk2 = INIT_OQ;
assign d2rnk2 = INIT_OQ;
assign d2nrnk2 = INIT_OQ;
end
else
begin
deassign OQ;
deassign d1rnk2;
deassign d2rnk2;
deassign d2nrnk2;
end
end
/////////////////////////////////////////
/////////////////////////////////////////
// 3 flops to create DDR operations of 4 latches
////////////////////////////////////////
// Representation of top latch
// asynchronous operation
always @ (posedge C or posedge SR)
begin
begin
if (SR & !SRVAL_OQ & !SRTYPE[1])
begin
d1rnk2 <= # FFD 1'b0;
end
else if (SR & SRVAL_OQ & !SRTYPE[1])
begin
d1rnk2 <= # FFD 1'b1;
end
else if (!OCE & !SRTYPE[1])
begin
d1rnk2 <= # FFD OQ;
end
else if (!SRTYPE[1])
begin
d1rnk2 <= # FFD data1;
end
end
end
// synchronous operation
always @ (posedge C)
begin
begin
if (SR & !SRVAL_OQ & SRTYPE[1])
begin
d1rnk2 <= # FFD 1'b0;
end
else if (SR & SRVAL_OQ & SRTYPE[1])
begin
d1rnk2 <= # FFD 1'b1;
end
else if (!OCE & SRTYPE[1])
begin
d1rnk2 <= # FFD OQ;
end
else if (SRTYPE[1])
begin
d1rnk2 <= # FFD data1;
end
end
end
// Representation of 2nd latch
// asynchronous operation
always @ (posedge C2p or posedge SR)
begin
begin
if (SR & !SRVAL_OQ & !SRTYPE[1])
begin
d2rnk2 <= # FFD 1'b0;
end
else if (SR & SRVAL_OQ & !SRTYPE[1])
begin
d2rnk2 <= # FFD 1'b1;
end
else if (!OCE & !SRTYPE[1])
begin
d2rnk2 <= # FFD OQ;
end
else if (!SRTYPE[1])
begin
d2rnk2 <= # FFD data2;
end
end
end
// synchronous operation
always @ (posedge C2p)
begin
begin
if (SR & !SRVAL_OQ & SRTYPE[1])
begin
d2rnk2 <= # FFD 1'b0;
end
else if (SR & SRVAL_OQ & SRTYPE[1])
begin
d2rnk2 <= # FFD 1'b1;
end
else if (!OCE & SRTYPE[1])
begin
d2rnk2 <= # FFD OQ;
end
else if (SRTYPE[1])
begin
d2rnk2 <= # FFD data2;
end
end
end
// Representation of 3rd flop ( latch and output latch)
// asynchronous operation
always @ (posedge C3 or posedge SR)
begin
begin
if (SR & !SRVAL_OQ & !SRTYPE[1])
begin
d2nrnk2 <= # FFD 1'b0;
end
else if (SR & SRVAL_OQ & !SRTYPE[1])
begin
d2nrnk2 <= # FFD 1'b1;
end
else if (!OCE & !SRTYPE[1])
begin
d2nrnk2 <= # FFD OQ;
end
else if (!SRTYPE[1])
begin
d2nrnk2 <= # FFD d2rnk2;
end
end
end
// synchronous operation
always @ (posedge C3)
begin
begin
if (SR & !SRVAL_OQ & SRTYPE[1])
begin
d2nrnk2 <= # FFD 1'b0;
end
else if (SR & SRVAL_OQ & SRTYPE[1])
begin
d2nrnk2 <= # FFD 1'b1;
end
else if (!OCE & SRTYPE[1])
begin
d2nrnk2 <= # FFD OQ;
end
else if (SRTYPE[1])
begin
d2nrnk2 <= # FFD d2rnk2;
end
end
end
// Logic to generate same edge data from d1rnk2 and d2nrnk2;
always @ (C or C3 or d1rnk2 or d2nrnk2)
begin
sdata_edge <= # MXD (d1rnk2 & C) | (d2nrnk2 & C3);
end
// Mux to create opposite edge DDR data from d1rnk2 and d2rnk2
always @ (C or d1rnk2 or d2rnk2)
begin
case (C)
1'b0: odata_edge <= # MXD d2rnk2;
1'b1: odata_edge <= # MXD d1rnk2;
default: odata_edge <= # MXD d1rnk2;
endcase
end
// Logic to same edge and opposite data into just ddr data
always @ (ddr_data or sdata_edge or odata_edge or DDR_CLK_EDGE)
begin
ddr_data <= # MXD (odata_edge & !DDR_CLK_EDGE) | (sdata_edge & DDR_CLK_EDGE);
end
// Output mux to generate OQ
always @ (seloq or d1rnk2 or ddr_data or OQ)
begin
casex (seloq)
4'bXX01: OQ <= # MXD 1'b1;
4'bXX10: OQ <= # MXD 1'b0;
4'bXX11: OQ <= # MXD 1'b0;
4'bX000: OQ <= # MXD ddr_data;
4'bX100: OQ <= # MXD d1rnk2;
default: OQ <= # MXD ddr_data;
endcase
end
endmodule
`timescale 1ps/1ps
//////////////////////////////////////////////////////////
//
// module tout_oserdese1_vlog
//
// Tristate Output cell for Mt Blanc
//
//
////////////////////////////////////////////////////////
//
//
//
/////////////////////////////////////////////////////////
//
// Inputs:
//
// data1, data2: tristate inputs
// TCE: Tristate clock enable
// SR: Set/Reset control. For the last 3 flops in TQ
// (qt1, qt2 and qt2n) this function is
// controlled bythe attributes SRVAL_TQ. In SERDES mode,
// SR is a RESET ONLY for all other flops! The flops will
// still be RESET even if SR is programmed to a SET!
// CLK: High speed clocks
// C2 drives 2nd latch and C3 (inverse of C2) drives
// 3rd latch in output section
// BUFO: Performance path clock
//
//
//
//
// Outputs:
//
// TQ: Output of tristate mux
//
//
// Programmable Options:
//
// DATA_RATE_TQ: 2-bit field for types of operaiton
// 0 (buf from T1), 1 (registered output from T1), 2 (ddr)
// TRISTATE_WIDTH: 2-bit field for input width
// 0 (width 1), 1 (width 2), 2 (width 4)
// INIT_TQ: Init TQ output (0,1)
// SRVAL_TQ: This bit to controls value of SR input.
// Only the last 3 flops (qt1, qt2 and qt2n) are
// affected by this bit.For SERDES mode, this bit
// should be set to '0' making SR a reset. This is the
// desired state since all other flops only
// respond to this pin as a reset. Their function
// cannot be changed. SR is 'O' for SET and '1' for RESET.
//
//
// Programmable Test Options:
// SRTYPE: Control S and R as asynchronous (0) or synchronous (1)
// 2-bit value. 1st bit (msb) controls the 4 input flops
// and the 2nd bit (lsb) controls the "3 legacy flops"
// DDR_CLK_EDGE: Same or opposite edge operation
//
//
//
////////////////////////////////////////////////////////////////////////////////
//
module tout_oserdese1_vlog (data1, data2,
CLK, BUFO, SR, TCE,
DATA_RATE_TQ, TRISTATE_WIDTH,
INIT_TQ, SRVAL_TQ,
TQ, DDR3_MODE);
input data1, data2;
input CLK, BUFO, SR, TCE;
input [1:0] DATA_RATE_TQ, TRISTATE_WIDTH;
input INIT_TQ, SRVAL_TQ;
input DDR3_MODE;
output TQ;
wire DDR_CLK_EDGE;
wire [1:0] SRTYPE;
assign SRTYPE = 2'b11;
assign DDR_CLK_EDGE = 1'b1;
reg TQ;
reg t1r, t2r, t3r, t4r;
reg qt1, qt2, qt2n;
reg sdata_edge, odata_edge, ddr_data;
wire C;
wire C2p, C3;
wire load;
wire [5:0] tqsel;
wire tqsr, tqrev;
wire [4:0] sel;
assign C = (BUFO & DDR3_MODE) | (CLK & !DDR3_MODE);
assign C2p = (C & DDR_CLK_EDGE) | (!C & !DDR_CLK_EDGE);
assign C3 = !C2p;
assign tqsr = (!SRTYPE[0] & SR & !SRVAL_TQ) | (!SRTYPE[0] & SRVAL_TQ);
assign tqrev = (!SRTYPE[0] & SR & SRVAL_TQ) | (!SRTYPE[0] & !SRVAL_TQ);
assign tqsel = {TCE,DATA_RATE_TQ,TRISTATE_WIDTH,tqsr};
//////////////////////////////////////////////////
// Parameters for gate delays
parameter ffd = 1;
parameter mxd = 1;
/////////////////////////////
// Initialization of Flops
////////////////////////////
tri0 GSR = glbl.GSR;
always @(GSR)
begin
if (GSR)
begin
assign TQ = INIT_TQ;
assign qt1 = INIT_TQ;
assign qt2 = INIT_TQ;
assign qt2n = INIT_TQ;
end
else
begin
deassign TQ;
deassign qt1;
deassign qt2;
deassign qt2n;
end
end
/////////////////////////////////////////
// 3 flops to create DDR operations of 4 latches
////////////////////////////////////////
// Representation of top latch
// asynchronous operation
always @ (posedge C or posedge SR)
begin
begin
if (SR & !SRVAL_TQ & !SRTYPE[0])
begin
qt1 <= # ffd 1'b0;
end
else if (SR & SRVAL_TQ & !SRTYPE[0])
begin
qt1 <= # ffd 1'b1;
end
else if (!TCE & !SRTYPE[0])
begin
qt1 <= # ffd TQ;
end
else if (!SRTYPE[0])
begin
qt1 <= # ffd data1;
end
end
end
// synchronous operation
always @ (posedge C)
begin
begin
if (SR & !SRVAL_TQ & SRTYPE[0])
begin
qt1 <= # ffd 1'b0;
end
else if (SR & SRVAL_TQ & SRTYPE[0])
begin
qt1 <= # ffd 1'b1;
end
else if (!TCE & SRTYPE[0])
begin
qt1 <= # ffd TQ;
end
else if (SRTYPE[0])
begin
qt1 <= # ffd data1;
end
end
end
// Representation of 2nd latch
// asynchronous operation
always @ (posedge C2p or posedge SR)
begin
begin
if (SR & !SRVAL_TQ & !SRTYPE[0])
begin
qt2 <= # ffd 1'b0;
end
else if (SR & SRVAL_TQ & !SRTYPE[0])
begin
qt2 <= # ffd 1'b1;
end
else if (!TCE & !SRTYPE[0])
begin
qt2 <= # ffd TQ;
end
else if (!SRTYPE[0])
begin
qt2 <= # ffd data2;
end
end
end
// synchronous operation
always @ (posedge C2p)
begin
begin
if (SR & !SRVAL_TQ & SRTYPE[0])
begin
qt2 <= # ffd 1'b0;
end
else if (SR & SRVAL_TQ & SRTYPE[0])
begin
qt2 <= # ffd 1'b1;
end
else if (!TCE & SRTYPE[0])
begin
qt2 <= # ffd TQ;
end
else if (SRTYPE[0])
begin
qt2 <= # ffd data2;
end
end
end
// Representation of 3rd flop ( latch and output latch)
// asynchronous operation
always @ (posedge C3 or posedge SR)
begin
begin
if (SR & !SRVAL_TQ & !SRTYPE[0])
begin
qt2n <= # ffd 1'b0;
end
else if (SR & SRVAL_TQ & !SRTYPE[0])
begin
qt2n <= # ffd 1'b1;
end
else if (!TCE & !SRTYPE[0])
begin
qt2n <= # ffd TQ;
end
else if (!SRTYPE[0])
begin
qt2n <= # ffd qt2;
end
end
end
// synchronous operation
always @ (posedge C3)
begin
begin
if (SR & !SRVAL_TQ & SRTYPE[0])
begin
qt2n <= # ffd 1'b0;
end
else if (SR & SRVAL_TQ & SRTYPE[0])
begin
qt2n <= # ffd 1'b1;
end
else if (!TCE & SRTYPE[0])
begin
qt2n <= # ffd TQ;
end
else if (SRTYPE[0])
begin
qt2n <= # ffd qt2;
end
end
end
// Logic to generate same edge data from qt1, qt3;
always @ (C or C3 or qt1 or qt2n)
begin
sdata_edge <= # mxd (qt1 & C) | (qt2n & C3);
end
// Mux to create opposite edge DDR function
always @ (C or qt1 or qt2)
begin
case (C)
1'b0: odata_edge <= # mxd qt2;
1'b1: odata_edge <= # mxd qt1;
default: odata_edge <= 1'b0;
endcase
end
// Logic to same edge and opposite data into just ddr data
always @ (ddr_data or sdata_edge or odata_edge or DDR_CLK_EDGE)
begin
ddr_data <= # mxd (odata_edge & !DDR_CLK_EDGE) | (sdata_edge & DDR_CLK_EDGE);
end
// Output mux to generate TQ
// Note that the TQ mux can also support T2 combinatorial or
// registered outputs.
always @ (tqsel or data1 or ddr_data or qt1 or TQ)
begin
casex (tqsel)
6'bX01XX1: TQ <= # mxd 1'b0;
6'bX10XX1: TQ <= # mxd 1'b0;
6'bX01XX1: TQ <= # mxd 1'b0;
6'bX10XX1: TQ <= # mxd 1'b0;
6'bX0000X: TQ <= # mxd data1;
// 6'b001000: TQ <= # mxd TQ;
// 6'b010010: TQ <= # mxd TQ;
// 6'b010100: TQ <= # mxd TQ;
6'bX01000: TQ <= # mxd qt1;
6'bX10010: TQ <= # mxd ddr_data;
6'bX10100: TQ <= # mxd ddr_data;
default: TQ <= # mxd ddr_data;
endcase
end
endmodule
`endcelldefine
|
//======================================================================
//
// vndecorrelator.v
// ----------------
// von Neumann decorrelator for bits. The module consumes bits
// and for every two bits consume will either emit zero or one bits.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module vndecorrelator(
input wire clk,
input wire reset_n,
input wire data_in,
input wire syn_in,
output wire data_out,
output wire syn_out
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter CTRL_IDLE = 1'b0;
parameter CTRL_BITS = 1'b1;
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg data_in_reg;
reg data_in_we;
reg data_out_reg;
reg data_out_we;
reg syn_out_reg;
reg syn_out_new;
reg vndecorr_ctrl_reg;
reg vndecorr_ctrl_new;
reg vndecorr_ctrl_we;
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign data_out = data_out_reg;
assign syn_out = syn_out_reg;
//----------------------------------------------------------------
// reg_update
//----------------------------------------------------------------
always @ (posedge clk or negedge reset_n)
begin
if (!reset_n)
begin
data_in_reg <= 1'b0;
data_out_reg <= 1'b0;
syn_out_reg <= 1'b0;
vndecorr_ctrl_reg <= CTRL_IDLE;
end
else
begin
syn_out_reg <= syn_out_new;
if (data_in_we)
begin
data_in_reg <= data_in;
end
if (data_out_we)
begin
data_out_reg <= data_in;
end
if (vndecorr_ctrl_we)
begin
vndecorr_ctrl_reg <= vndecorr_ctrl_new;
end
end
end // reg_update
//----------------------------------------------------------------
// vndecorr_logic
//
// The logic implementing the von Neumann decorrelator by waiting
// for subsequent bits and comparing them to determine if both
// bits should just be discarded or one of them also emitted.
//----------------------------------------------------------------
always @*
begin : vndecorr_logic
data_in_we = 1'b0;
data_out_we = 1'b0;
syn_out_new = 1'b0;
vndecorr_ctrl_new = CTRL_IDLE;
vndecorr_ctrl_we = 1'b0;
case (vndecorr_ctrl_reg)
CTRL_IDLE:
begin
if (syn_in)
begin
data_in_we = 1'b1;
vndecorr_ctrl_new = CTRL_BITS;
vndecorr_ctrl_we = 1'b1;
end
end
CTRL_BITS:
begin
if (syn_in)
begin
if (data_in != data_in_reg)
begin
data_out_we = 1'b1;
syn_out_new = 1'b1;
end
vndecorr_ctrl_new = CTRL_IDLE;
vndecorr_ctrl_we = 1'b1;
end
end
endcase // case (vndecorr_ctrl_reg)
end // vndecorr_logic
endmodule // vndecorrelator
//======================================================================
// EOF vndecorrelator.v
//======================================================================
|
// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
// Date : Tue Mar 22 03:35:29 2016
// Host : DESKTOP-5FTSDRT running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/Users/SKL/Desktop/ECE532/quadencoder/encoder_decoder_prj/project_1.srcs/sources_1/ip/dcfifo_32in_32out_16kb_wr_cnt/dcfifo_32in_32out_16kb_wr_cnt_stub.v
// Design : dcfifo_32in_32out_16kb_wr_cnt
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v12_0,Vivado 2015.1" *)
module dcfifo_32in_32out_16kb_wr_cnt(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, empty, wr_data_count)
/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[31:0],wr_en,rd_en,dout[31:0],full,empty,wr_data_count[1:0]" */;
input rst;
input wr_clk;
input rd_clk;
input [31:0]din;
input wr_en;
input rd_en;
output [31:0]dout;
output full;
output empty;
output [1:0]wr_data_count;
endmodule
|
//======================================================================
//
// tb_mkmif_core.v
// ---------------
// Testbench for the mkmif core module.
//
//
// Copyright (c) 2016, Assured AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module tb_mkmif_core();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 1;
parameter CLK_HALF_PERIOD = 2;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] cycle_ctr;
reg [31 : 0] test_ctr;
reg [31 : 0] error_ctr;
reg tb_clk;
reg tb_reset_n;
wire tb_spi_sclk;
wire tb_cs_n;
wire tb_spi_do;
wire tb_spi_di;
reg tb_read_op;
reg tb_write_op;
reg tb_init_op;
wire tb_ready;
wire tb_valid;
reg [15 : 0] tb_sclk_div;
reg [15 : 0] tb_addr;
reg [31 : 0] tb_write_data;
wire [31 : 0] tb_read_data;
reg tb_display_state;
reg [31 : 0] read_data;
//----------------------------------------------------------------
// Concurrent connectivity.
//----------------------------------------------------------------
// We loop back the inverted SPI serial transmit data from
// the DUT as the data from the memory (do) to the DUT.
assign tb_spi_do = ~tb_spi_di;
//----------------------------------------------------------------
// mkmif device under test.
//----------------------------------------------------------------
mkmif_core dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.spi_sclk(tb_spi_sclk),
.spi_cs_n(tb_cs_n),
.spi_do(tb_spi_do),
.spi_di(tb_spi_di),
.read_op(tb_read_op),
.write_op(tb_write_op),
.init_op(tb_init_op),
.ready(tb_ready),
.valid(tb_valid),
.sclk_div(tb_sclk_div),
.addr(tb_addr),
.write_data(tb_write_data),
.read_data(tb_read_data)
);
//----------------------------------------------------------------
// clk_gen
// Clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD tb_clk = !tb_clk;
end // clk_gen
//--------------------------------------------------------------------
// dut_monitor
// Monitor for observing the inputs and outputs to the dut.
// Includes the cycle counter.
//--------------------------------------------------------------------
always @ (posedge tb_clk)
begin : dut_monitor
cycle_ctr = cycle_ctr + 1;
if (tb_display_state)
begin
$display("cycle = %8x:", cycle_ctr);
dump_state();
end
end // dut_monitor
//----------------------------------------------------------------
// inc_test_ctr
//----------------------------------------------------------------
task inc_test_ctr;
begin
test_ctr = test_ctr +1;
end
endtask // inc_test_ctr
//----------------------------------------------------------------
// inc_error_ctr
//----------------------------------------------------------------
task inc_error_ctr;
begin
error_ctr = error_ctr +1;
end
endtask // inc_error_ctr
//----------------------------------------------------------------
// dump_state
// Dump the internal MKMIF state to std out.
//----------------------------------------------------------------
task dump_state;
begin
$display("mkmif_ctrl_reg: 0x%02x", dut.mkmif_ctrl_reg);
$display("sclk: 0x%01x, cs_n: 0x%01x, di: 0x%01x, do: 0x%01x, nxt: 0x%01x",
tb_spi_sclk, tb_cs_n, tb_spi_di, tb_spi_do, dut.spi.data_nxt);
$display("spi_ctrl_reg: 0x%01x, spi_clk_ctr: 0x%04x, spi_bit_ctr: 0x%02x",
dut.spi.spi_ctrl_reg, dut.spi.clk_ctr_reg, dut.spi.bit_ctr_reg);
$display("spi length: 0x%02x, spi divisor: 0x%04x, spi set: 0x%01x, spi start: 0x%01x, spi ready: 0x%01x",
dut.spi.length_reg, dut.spi.divisor_reg, dut.spi.set, dut.spi.start, dut.spi.ready);
$display("read data: 0x%08x, write_data: 0x%014x", dut.spi.rd_data, dut.spi.wr_data);
$display("");
end
endtask // dump_state
//----------------------------------------------------------------
// tb_init
// Initialize varibles, dut inputs at start.
//----------------------------------------------------------------
task tb_init;
begin
test_ctr = 0;
error_ctr = 0;
cycle_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_read_op = 0;
tb_write_op = 0;
tb_init_op = 0;
tb_sclk_div = 16'h0004;
tb_addr = 16'h0010;
tb_write_data = 32'haa55aa55;
tb_display_state = 1;
end
endtask // tb_init
//----------------------------------------------------------------
// wait_ready()
//
// Wait for ready word to be set in the DUT API.
//----------------------------------------------------------------
task wait_ready;
reg ready;
begin
ready = 0;
while (tb_ready == 0)
begin
#(CLK_PERIOD);
end
end
endtask // read_word
//----------------------------------------------------------------
// toggle_reset
// Toggle the reset.
//----------------------------------------------------------------
task toggle_reset;
begin
$display(" -- Toggling reset.");
dump_state();
#(2 * CLK_PERIOD);
tb_reset_n = 0;
#(10 * CLK_PERIOD);
@(negedge tb_clk)
tb_reset_n = 1;
dump_state();
$display(" -- Toggling of reset done.");
$display("");
end
endtask // toggle_reset
//----------------------------------------------------------------
// write_test
//----------------------------------------------------------------
task write_test;
begin
$display(" -- Write Test started.");
inc_test_ctr();
wait_ready();
tb_sclk_div = 16'h0004;
tb_addr = 16'h0012;
tb_write_data = 32'hdeadbeef;
tb_write_op = 1;
#(2 * CLK_PERIOD);
tb_write_op = 0;
wait_ready();
$display(" -- Write Test done.");
$display("");
end
endtask // write_test
//----------------------------------------------------------------
// mkmif_core_test
// The main test functionality.
//----------------------------------------------------------------
initial
begin : mkmif__core_test
$display(" -- Test of mkmif core started --");
tb_init();
toggle_reset();
write_test();
$display("");
$display(" -- Test of mkmif core completed --");
$display("Tests executed: %04d", test_ctr);
$display("Tests failed: %04d", error_ctr);
$finish;
end // mkmif_core_test
endmodule // tb_mkmif_core
//======================================================================
// EOF tb_mkmif_core.v
//======================================================================
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Expert(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Tue Oct 18 20:11:29 2016
/////////////////////////////////////////////////////////////
module Oper_Start_In_2_W32 ( clk, rst, load_b_i, intAS, intDX, intDY, DMP_o,
DmP_o, zero_flag_o, real_op_o, sign_final_result_o );
input [31:0] intDX;
input [31:0] intDY;
output [30:0] DMP_o;
output [30:0] DmP_o;
input clk, rst, load_b_i, intAS;
output zero_flag_o, real_op_o, sign_final_result_o;
wire \MRegister/n63 , \MRegister/n61 , \MRegister/n60 , \MRegister/n59 ,
\MRegister/n58 , \MRegister/n57 , \MRegister/n56 , \MRegister/n55 ,
\MRegister/n54 , \MRegister/n53 , \MRegister/n52 , \MRegister/n51 ,
\MRegister/n50 , \MRegister/n49 , \MRegister/n48 , \MRegister/n47 ,
\MRegister/n46 , \MRegister/n45 , \MRegister/n44 , \MRegister/n43 ,
\MRegister/n42 , \MRegister/n41 , \MRegister/n40 , \MRegister/n39 ,
\MRegister/n38 , \MRegister/n37 , \MRegister/n36 , \MRegister/n35 ,
\MRegister/n34 , \MRegister/n33 , \MRegister/n32 , \MRegister/n31 ,
\MRegister/n30 , \MRegister/n29 , \MRegister/n28 , \MRegister/n27 ,
\MRegister/n26 , \MRegister/n25 , \MRegister/n24 , \MRegister/n23 ,
\MRegister/n22 , \MRegister/n21 , \MRegister/n20 , \MRegister/n19 ,
\MRegister/n18 , \MRegister/n17 , \MRegister/n16 , \MRegister/n15 ,
\MRegister/n14 , \MRegister/n13 , \MRegister/n12 , \MRegister/n11 ,
\MRegister/n10 , \MRegister/n9 , \MRegister/n8 , \MRegister/n7 ,
\MRegister/n6 , \MRegister/n5 , \MRegister/n4 , \MRegister/n3 ,
\MRegister/n2 , \MRegister/n1 , \mRegister/n135 , \mRegister/n134 ,
\mRegister/n133 , \mRegister/n132 , \mRegister/n131 ,
\mRegister/n130 , \mRegister/n129 , \mRegister/n128 ,
\mRegister/n127 , \mRegister/n126 , \mRegister/n125 ,
\mRegister/n124 , \mRegister/n123 , \mRegister/n122 ,
\mRegister/n121 , \mRegister/n120 , \mRegister/n119 ,
\mRegister/n118 , \mRegister/n117 , \mRegister/n116 ,
\mRegister/n115 , \mRegister/n114 , \mRegister/n113 ,
\mRegister/n112 , \mRegister/n111 , \mRegister/n110 ,
\mRegister/n109 , \mRegister/n108 , \mRegister/n107 ,
\mRegister/n106 , \mRegister/n105 , \mRegister/n104 ,
\mRegister/n103 , \mRegister/n102 , \mRegister/n101 ,
\mRegister/n100 , \mRegister/n99 , \mRegister/n98 , \mRegister/n97 ,
\mRegister/n96 , \mRegister/n95 , \mRegister/n94 , \mRegister/n93 ,
\mRegister/n92 , \mRegister/n91 , \mRegister/n90 , \mRegister/n89 ,
\mRegister/n88 , \mRegister/n87 , \mRegister/n86 , \mRegister/n85 ,
\mRegister/n84 , \mRegister/n83 , \mRegister/n82 , \mRegister/n81 ,
\mRegister/n80 , \mRegister/n79 , \mRegister/n78 , \mRegister/n77 ,
\mRegister/n76 , \mRegister/n75 , \mRegister/n74 , \SignRegister/n5 ,
\SignRegister/n4 , n152, n153, n154, n155, n156, n157, n158, n159,
n160, n161, n162, n163, n164, n165, n166, n167, n168, n169, n170,
n171, n172, n173, n174, n175, n176, n177, n178, n179, n180, n181,
n182, n183, n184, n185, n186, n187, n188, n189, n190, n191, n192,
n193, n194, n195, n196, n197, n198, n199, n200, n201, n202, n203,
n204, n205, n206, n207, n208, n209, n210, n211, n212, n213, n214,
n215, n216, n217, n218, n219, n220, n221, n222, n223, n224, n225,
n226, n227, n228, n229, n230, n231, n232, n233, n234, n235, n236,
n237, n238, n239, n240, n241, n242, n243, n244, n245, n246, n247,
n248, n249, n250, n251, n252, n253, n254, n255, n256, n257, n258,
n259, n260, n261, n262, n263, n264, n265, n266, n267, n268, n269,
n270, n271, n272, n273, n274, n275, n276, n277, n278, n279, n280,
n281, n282, n283, n284, n285, n286, n287, n288, n289, n290, n291,
n292, n293, n294, n295, n296, n297, n298, n299, n300, n301, n302,
n303, n304, n305, n306, n307, n308, n309, n310, n311, n312, n313;
DFFRXLTS \MRegister/Q_reg_0_ ( .D(\MRegister/n32 ), .CK(clk), .RN(n152),
.Q(DMP_o[0]), .QN(\MRegister/n1 ) );
DFFRXLTS \MRegister/Q_reg_1_ ( .D(\MRegister/n33 ), .CK(clk), .RN(n152),
.Q(DMP_o[1]), .QN(\MRegister/n2 ) );
DFFRXLTS \MRegister/Q_reg_2_ ( .D(\MRegister/n34 ), .CK(clk), .RN(n313),
.Q(DMP_o[2]), .QN(\MRegister/n3 ) );
DFFRXLTS \MRegister/Q_reg_3_ ( .D(\MRegister/n35 ), .CK(clk), .RN(n152),
.Q(DMP_o[3]), .QN(\MRegister/n4 ) );
DFFRXLTS \MRegister/Q_reg_4_ ( .D(\MRegister/n36 ), .CK(clk), .RN(n152),
.Q(DMP_o[4]), .QN(\MRegister/n5 ) );
DFFRXLTS \MRegister/Q_reg_5_ ( .D(\MRegister/n37 ), .CK(clk), .RN(n313),
.Q(DMP_o[5]), .QN(\MRegister/n6 ) );
DFFRXLTS \MRegister/Q_reg_7_ ( .D(\MRegister/n39 ), .CK(clk), .RN(n152),
.Q(DMP_o[7]), .QN(\MRegister/n8 ) );
DFFRXLTS \MRegister/Q_reg_6_ ( .D(\MRegister/n38 ), .CK(clk), .RN(n152),
.Q(DMP_o[6]), .QN(\MRegister/n7 ) );
DFFRXLTS \MRegister/Q_reg_8_ ( .D(\MRegister/n40 ), .CK(clk), .RN(n313),
.Q(DMP_o[8]), .QN(\MRegister/n9 ) );
DFFRXLTS \MRegister/Q_reg_9_ ( .D(\MRegister/n41 ), .CK(clk), .RN(n312),
.Q(DMP_o[9]), .QN(\MRegister/n10 ) );
DFFRXLTS \MRegister/Q_reg_14_ ( .D(\MRegister/n46 ), .CK(clk), .RN(n152),
.Q(DMP_o[14]), .QN(\MRegister/n15 ) );
DFFRXLTS \MRegister/Q_reg_22_ ( .D(\MRegister/n54 ), .CK(clk), .RN(n312),
.Q(DMP_o[22]), .QN(\MRegister/n23 ) );
DFFRXLTS \mRegister/Q_reg_6_ ( .D(\mRegister/n98 ), .CK(clk), .RN(n312),
.Q(DmP_o[6]), .QN(\mRegister/n129 ) );
DFFRXLTS \mRegister/Q_reg_21_ ( .D(\mRegister/n83 ), .CK(clk), .RN(n313),
.Q(DmP_o[21]), .QN(\mRegister/n114 ) );
DFFRXLTS \MRegister/Q_reg_10_ ( .D(\MRegister/n42 ), .CK(clk), .RN(n152),
.Q(DMP_o[10]), .QN(\MRegister/n11 ) );
DFFRXLTS \MRegister/Q_reg_11_ ( .D(\MRegister/n43 ), .CK(clk), .RN(n312),
.Q(DMP_o[11]), .QN(\MRegister/n12 ) );
DFFRXLTS \MRegister/Q_reg_12_ ( .D(\MRegister/n44 ), .CK(clk), .RN(n152),
.Q(DMP_o[12]), .QN(\MRegister/n13 ) );
DFFRXLTS \MRegister/Q_reg_13_ ( .D(\MRegister/n45 ), .CK(clk), .RN(n313),
.Q(DMP_o[13]), .QN(\MRegister/n14 ) );
DFFRXLTS \MRegister/Q_reg_15_ ( .D(\MRegister/n47 ), .CK(clk), .RN(n312),
.Q(DMP_o[15]), .QN(\MRegister/n16 ) );
DFFRXLTS \MRegister/Q_reg_23_ ( .D(\MRegister/n55 ), .CK(clk), .RN(n152),
.Q(DMP_o[23]), .QN(\MRegister/n24 ) );
DFFRXLTS \MRegister/Q_reg_24_ ( .D(\MRegister/n56 ), .CK(clk), .RN(n313),
.Q(DMP_o[24]), .QN(\MRegister/n25 ) );
DFFRXLTS \MRegister/Q_reg_25_ ( .D(\MRegister/n57 ), .CK(clk), .RN(n313),
.Q(DMP_o[25]), .QN(\MRegister/n26 ) );
DFFRXLTS \MRegister/Q_reg_16_ ( .D(\MRegister/n48 ), .CK(clk), .RN(n152),
.Q(DMP_o[16]), .QN(\MRegister/n17 ) );
DFFRXLTS \MRegister/Q_reg_17_ ( .D(\MRegister/n49 ), .CK(clk), .RN(n312),
.Q(DMP_o[17]), .QN(\MRegister/n18 ) );
DFFRXLTS \MRegister/Q_reg_18_ ( .D(\MRegister/n50 ), .CK(clk), .RN(n312),
.Q(DMP_o[18]), .QN(\MRegister/n19 ) );
DFFRXLTS \MRegister/Q_reg_19_ ( .D(\MRegister/n51 ), .CK(clk), .RN(n312),
.Q(DMP_o[19]), .QN(\MRegister/n20 ) );
DFFRXLTS \MRegister/Q_reg_26_ ( .D(\MRegister/n58 ), .CK(clk), .RN(n313),
.Q(DMP_o[26]), .QN(\MRegister/n27 ) );
DFFRXLTS \MRegister/Q_reg_27_ ( .D(\MRegister/n59 ), .CK(clk), .RN(n312),
.Q(DMP_o[27]), .QN(\MRegister/n28 ) );
DFFRXLTS \MRegister/Q_reg_28_ ( .D(\MRegister/n60 ), .CK(clk), .RN(n313),
.Q(DMP_o[28]), .QN(\MRegister/n29 ) );
DFFRXLTS \MRegister/Q_reg_29_ ( .D(\MRegister/n61 ), .CK(clk), .RN(n152),
.Q(DMP_o[29]), .QN(\MRegister/n30 ) );
DFFRXLTS \MRegister/Q_reg_20_ ( .D(\MRegister/n52 ), .CK(clk), .RN(n313),
.Q(DMP_o[20]), .QN(\MRegister/n21 ) );
DFFRXLTS \MRegister/Q_reg_21_ ( .D(\MRegister/n53 ), .CK(clk), .RN(n313),
.Q(DMP_o[21]), .QN(\MRegister/n22 ) );
DFFRXLTS \MRegister/Q_reg_30_ ( .D(\MRegister/n63 ), .CK(clk), .RN(n313),
.Q(DMP_o[30]), .QN(\MRegister/n31 ) );
DFFRXLTS \mRegister/Q_reg_23_ ( .D(\mRegister/n81 ), .CK(clk), .RN(n312),
.Q(DmP_o[23]), .QN(\mRegister/n112 ) );
DFFRXLTS \mRegister/Q_reg_24_ ( .D(\mRegister/n80 ), .CK(clk), .RN(n312),
.Q(DmP_o[24]), .QN(\mRegister/n111 ) );
DFFRXLTS \mRegister/Q_reg_25_ ( .D(\mRegister/n79 ), .CK(clk), .RN(n312),
.Q(DmP_o[25]), .QN(\mRegister/n110 ) );
DFFRXLTS \mRegister/Q_reg_26_ ( .D(\mRegister/n78 ), .CK(clk), .RN(n312),
.Q(DmP_o[26]), .QN(\mRegister/n109 ) );
DFFRXLTS \mRegister/Q_reg_27_ ( .D(\mRegister/n77 ), .CK(clk), .RN(n312),
.Q(DmP_o[27]), .QN(\mRegister/n108 ) );
DFFRXLTS \mRegister/Q_reg_28_ ( .D(\mRegister/n76 ), .CK(clk), .RN(n313),
.Q(DmP_o[28]), .QN(\mRegister/n107 ) );
DFFRXLTS \mRegister/Q_reg_29_ ( .D(\mRegister/n75 ), .CK(clk), .RN(n152),
.Q(DmP_o[29]), .QN(\mRegister/n106 ) );
DFFRXLTS \mRegister/Q_reg_0_ ( .D(\mRegister/n104 ), .CK(clk), .RN(n152),
.Q(DmP_o[0]), .QN(\mRegister/n135 ) );
DFFRXLTS \mRegister/Q_reg_1_ ( .D(\mRegister/n103 ), .CK(clk), .RN(n313),
.Q(DmP_o[1]), .QN(\mRegister/n134 ) );
DFFRXLTS \mRegister/Q_reg_2_ ( .D(\mRegister/n102 ), .CK(clk), .RN(n152),
.Q(DmP_o[2]), .QN(\mRegister/n133 ) );
DFFRXLTS \mRegister/Q_reg_3_ ( .D(\mRegister/n101 ), .CK(clk), .RN(n313),
.Q(DmP_o[3]), .QN(\mRegister/n132 ) );
DFFRXLTS \mRegister/Q_reg_4_ ( .D(\mRegister/n100 ), .CK(clk), .RN(n152),
.Q(DmP_o[4]), .QN(\mRegister/n131 ) );
DFFRXLTS \mRegister/Q_reg_5_ ( .D(\mRegister/n99 ), .CK(clk), .RN(n313),
.Q(DmP_o[5]), .QN(\mRegister/n130 ) );
DFFRXLTS \mRegister/Q_reg_7_ ( .D(\mRegister/n97 ), .CK(clk), .RN(n152),
.Q(DmP_o[7]), .QN(\mRegister/n128 ) );
DFFRXLTS \mRegister/Q_reg_8_ ( .D(\mRegister/n96 ), .CK(clk), .RN(n312),
.Q(DmP_o[8]), .QN(\mRegister/n127 ) );
DFFRXLTS \mRegister/Q_reg_9_ ( .D(\mRegister/n95 ), .CK(clk), .RN(n312),
.Q(DmP_o[9]), .QN(\mRegister/n126 ) );
DFFRXLTS \mRegister/Q_reg_10_ ( .D(\mRegister/n94 ), .CK(clk), .RN(n152),
.Q(DmP_o[10]), .QN(\mRegister/n125 ) );
DFFRXLTS \mRegister/Q_reg_11_ ( .D(\mRegister/n93 ), .CK(clk), .RN(n312),
.Q(DmP_o[11]), .QN(\mRegister/n124 ) );
DFFRXLTS \mRegister/Q_reg_12_ ( .D(\mRegister/n92 ), .CK(clk), .RN(n313),
.Q(DmP_o[12]), .QN(\mRegister/n123 ) );
DFFRXLTS \mRegister/Q_reg_13_ ( .D(\mRegister/n91 ), .CK(clk), .RN(n152),
.Q(DmP_o[13]), .QN(\mRegister/n122 ) );
DFFRXLTS \mRegister/Q_reg_14_ ( .D(\mRegister/n90 ), .CK(clk), .RN(n312),
.Q(DmP_o[14]), .QN(\mRegister/n121 ) );
DFFRXLTS \mRegister/Q_reg_15_ ( .D(\mRegister/n89 ), .CK(clk), .RN(n312),
.Q(DmP_o[15]), .QN(\mRegister/n120 ) );
DFFRXLTS \mRegister/Q_reg_16_ ( .D(\mRegister/n88 ), .CK(clk), .RN(n313),
.Q(DmP_o[16]), .QN(\mRegister/n119 ) );
DFFRXLTS \mRegister/Q_reg_17_ ( .D(\mRegister/n87 ), .CK(clk), .RN(n152),
.Q(DmP_o[17]), .QN(\mRegister/n118 ) );
DFFRXLTS \mRegister/Q_reg_18_ ( .D(\mRegister/n86 ), .CK(clk), .RN(n152),
.Q(DmP_o[18]), .QN(\mRegister/n117 ) );
DFFRXLTS \mRegister/Q_reg_19_ ( .D(\mRegister/n85 ), .CK(clk), .RN(n152),
.Q(DmP_o[19]), .QN(\mRegister/n116 ) );
DFFRXLTS \mRegister/Q_reg_20_ ( .D(\mRegister/n84 ), .CK(clk), .RN(n313),
.Q(DmP_o[20]), .QN(\mRegister/n115 ) );
DFFRXLTS \mRegister/Q_reg_22_ ( .D(\mRegister/n82 ), .CK(clk), .RN(n313),
.Q(DmP_o[22]), .QN(\mRegister/n113 ) );
DFFRXLTS \mRegister/Q_reg_30_ ( .D(\mRegister/n74 ), .CK(clk), .RN(n312),
.Q(DmP_o[30]), .QN(\mRegister/n105 ) );
DFFRXLTS \SignRegister/Q_reg_0_ ( .D(\SignRegister/n4 ), .CK(clk), .RN(n152), .Q(sign_final_result_o), .QN(\SignRegister/n5 ) );
XOR2XLTS U218 ( .A(intAS), .B(intDY[31]), .Y(n251) );
XOR2XLTS U219 ( .A(n251), .B(intDX[31]), .Y(real_op_o) );
NOR2XLTS U220 ( .A(intDY[8]), .B(n288), .Y(n191) );
AOI211XLTS U221 ( .A0(n191), .A1(n190), .B0(n189), .C0(n188), .Y(n193) );
NOR2XLTS U222 ( .A(intDY[4]), .B(n292), .Y(n178) );
OAI211XLTS U223 ( .A0(n199), .A1(n198), .B0(n197), .C0(n196), .Y(n201) );
AOI31XLTS U224 ( .A0(n203), .A1(n202), .A2(n201), .B0(n200), .Y(n204) );
NOR2XLTS U225 ( .A(intDX[25]), .B(n261), .Y(n154) );
NOR2XLTS U226 ( .A(intDY[20]), .B(n275), .Y(n212) );
NOR2XLTS U227 ( .A(n283), .B(intDX[14]), .Y(n200) );
OAI211XLTS U228 ( .A0(intDY[8]), .A1(n288), .B0(n186), .C0(n185), .Y(n231)
);
NOR4BXLTS U229 ( .AN(n230), .B(n229), .C(n228), .D(n227), .Y(n234) );
OAI211XLTS U230 ( .A0(n219), .A1(n218), .B0(n217), .C0(n216), .Y(n220) );
NOR4BXLTS U231 ( .AN(n234), .B(n233), .C(n232), .D(n231), .Y(n235) );
NOR4BXLTS U232 ( .AN(n170), .B(n169), .C(n168), .D(n167), .Y(n236) );
OAI21XLTS U233 ( .A0(load_b_i), .A1(\MRegister/n19 ), .B0(n242), .Y(
\MRegister/n50 ) );
INVX2TS U234 ( .A(rst), .Y(n152) );
CLKBUFX2TS U235 ( .A(n152), .Y(n313) );
CLKBUFX2TS U236 ( .A(n152), .Y(n312) );
INVX2TS U237 ( .A(intDX[28]), .Y(n258) );
NAND2X1TS U238 ( .A(intDY[28]), .B(n258), .Y(n170) );
INVX2TS U239 ( .A(intDX[27]), .Y(n260) );
INVX2TS U240 ( .A(intDY[27]), .Y(n259) );
NOR2XLTS U241 ( .A(intDX[27]), .B(n259), .Y(n166) );
INVX2TS U242 ( .A(intDY[26]), .Y(n244) );
INVX2TS U243 ( .A(intDX[26]), .Y(n243) );
NAND2X1TS U244 ( .A(intDY[26]), .B(n243), .Y(n164) );
INVX2TS U245 ( .A(intDX[25]), .Y(n262) );
INVX2TS U246 ( .A(intDY[25]), .Y(n261) );
INVX2TS U247 ( .A(intDY[24]), .Y(n268) );
NAND2X1TS U248 ( .A(intDX[24]), .B(n268), .Y(n153) );
OAI22X1TS U249 ( .A0(intDY[25]), .A1(n262), .B0(n154), .B1(n153), .Y(n155)
);
AOI22X1TS U250 ( .A0(intDX[26]), .A1(n244), .B0(n164), .B1(n155), .Y(n156)
);
OAI22X1TS U251 ( .A0(intDY[27]), .A1(n260), .B0(n166), .B1(n156), .Y(n157)
);
NOR2XLTS U252 ( .A(intDY[28]), .B(n258), .Y(n168) );
INVX2TS U253 ( .A(intDX[29]), .Y(n256) );
NOR2XLTS U254 ( .A(intDY[29]), .B(n256), .Y(n162) );
AOI211XLTS U255 ( .A0(n170), .A1(n157), .B0(n168), .C0(n162), .Y(n219) );
INVX2TS U256 ( .A(intDY[30]), .Y(n250) );
INVX2TS U257 ( .A(intDY[29]), .Y(n255) );
OAI22X1TS U258 ( .A0(intDX[30]), .A1(n250), .B0(intDX[29]), .B1(n255), .Y(
n218) );
NAND2X1TS U259 ( .A(intDX[30]), .B(n250), .Y(n217) );
INVX2TS U260 ( .A(intDX[21]), .Y(n273) );
INVX2TS U261 ( .A(intDX[22]), .Y(n271) );
OAI22X1TS U262 ( .A0(intDY[21]), .A1(n273), .B0(intDY[22]), .B1(n271), .Y(
n209) );
INVX2TS U263 ( .A(intDY[20]), .Y(n276) );
INVX2TS U264 ( .A(intDY[23]), .Y(n270) );
INVX2TS U265 ( .A(intDX[23]), .Y(n269) );
AOI222XLTS U266 ( .A0(intDX[23]), .A1(n270), .B0(intDX[20]), .B1(n276), .C0(
n269), .C1(intDY[23]), .Y(n158) );
NAND2X1TS U267 ( .A(intDY[22]), .B(n271), .Y(n211) );
OAI211XLTS U268 ( .A0(intDX[20]), .A1(n276), .B0(n158), .C0(n211), .Y(n159)
);
AOI211XLTS U269 ( .A0(intDY[21]), .A1(n273), .B0(n209), .C0(n159), .Y(n237)
);
AOI22X1TS U270 ( .A0(n268), .A1(intDX[24]), .B0(n262), .B1(intDY[25]), .Y(
n160) );
OAI221XLTS U271 ( .A0(n268), .A1(intDX[24]), .B0(n262), .B1(intDY[25]), .C0(
n160), .Y(n169) );
NOR2XLTS U272 ( .A(intDY[27]), .B(n260), .Y(n163) );
NOR2XLTS U273 ( .A(intDY[26]), .B(n243), .Y(n161) );
NOR4BXLTS U274 ( .AN(n164), .B(n163), .C(n162), .D(n161), .Y(n165) );
NAND4BBX1TS U275 ( .AN(n218), .BN(n166), .C(n165), .D(n217), .Y(n167) );
INVX2TS U276 ( .A(intDX[16]), .Y(n247) );
INVX2TS U277 ( .A(intDX[17]), .Y(n280) );
AOI22X1TS U278 ( .A0(intDY[16]), .A1(n247), .B0(intDY[17]), .B1(n280), .Y(
n225) );
INVX2TS U279 ( .A(intDX[5]), .Y(n266) );
INVX2TS U280 ( .A(intDX[6]), .Y(n290) );
OAI22X1TS U281 ( .A0(intDY[5]), .A1(n266), .B0(intDY[6]), .B1(n290), .Y(n175) );
INVX2TS U282 ( .A(intDY[4]), .Y(n293) );
INVX2TS U283 ( .A(intDY[7]), .Y(n263) );
INVX2TS U284 ( .A(intDX[7]), .Y(n264) );
AOI222XLTS U285 ( .A0(intDX[7]), .A1(n263), .B0(intDX[4]), .B1(n293), .C0(
n264), .C1(intDY[7]), .Y(n171) );
NAND2X1TS U286 ( .A(intDY[6]), .B(n290), .Y(n177) );
OAI211XLTS U287 ( .A0(intDX[4]), .A1(n293), .B0(n171), .C0(n177), .Y(n172)
);
AOI211XLTS U288 ( .A0(intDY[5]), .A1(n266), .B0(n175), .C0(n172), .Y(n238)
);
INVX2TS U289 ( .A(intDX[1]), .Y(n298) );
NAND2X1TS U290 ( .A(intDY[1]), .B(n298), .Y(n230) );
INVX2TS U291 ( .A(intDY[0]), .Y(n301) );
INVX2TS U292 ( .A(intDX[2]), .Y(n296) );
OAI22X1TS U293 ( .A0(intDY[1]), .A1(n298), .B0(intDY[2]), .B1(n296), .Y(n233) );
AOI31XLTS U294 ( .A0(intDX[0]), .A1(n230), .A2(n301), .B0(n233), .Y(n174) );
INVX2TS U295 ( .A(intDY[2]), .Y(n297) );
NOR2XLTS U296 ( .A(intDX[2]), .B(n297), .Y(n229) );
INVX2TS U297 ( .A(intDY[3]), .Y(n295) );
INVX2TS U298 ( .A(intDX[3]), .Y(n294) );
AOI22X1TS U299 ( .A0(intDX[3]), .A1(intDY[3]), .B0(n295), .B1(n294), .Y(n232) );
NAND2X1TS U300 ( .A(intDX[3]), .B(n295), .Y(n173) );
OAI31X1TS U301 ( .A0(n174), .A1(n229), .A2(n232), .B0(n173), .Y(n181) );
INVX2TS U302 ( .A(intDX[4]), .Y(n292) );
NAND2X1TS U303 ( .A(intDY[5]), .B(n266), .Y(n176) );
AOI32X1TS U304 ( .A0(n178), .A1(n177), .A2(n176), .B0(n175), .B1(n177), .Y(
n179) );
AOI222XLTS U305 ( .A0(intDY[7]), .A1(n264), .B0(intDY[7]), .B1(n179), .C0(
n264), .C1(n179), .Y(n180) );
AOI21X1TS U306 ( .A0(n238), .A1(n181), .B0(n180), .Y(n206) );
INVX2TS U307 ( .A(intDX[8]), .Y(n288) );
INVX2TS U308 ( .A(intDX[15]), .Y(n302) );
INVX2TS U309 ( .A(intDX[11]), .Y(n308) );
INVX2TS U310 ( .A(intDY[15]), .Y(n303) );
AOI222XLTS U311 ( .A0(intDY[15]), .A1(n302), .B0(intDY[11]), .B1(n308), .C0(
n303), .C1(intDX[15]), .Y(n186) );
INVX2TS U312 ( .A(intDY[10]), .Y(n287) );
NOR2XLTS U313 ( .A(intDX[10]), .B(n287), .Y(n194) );
INVX2TS U314 ( .A(intDY[8]), .Y(n289) );
NAND2X1TS U315 ( .A(intDX[10]), .B(n287), .Y(n187) );
INVX2TS U316 ( .A(intDX[9]), .Y(n254) );
NAND2X1TS U317 ( .A(intDY[9]), .B(n254), .Y(n190) );
OAI211XLTS U318 ( .A0(intDX[8]), .A1(n289), .B0(n187), .C0(n190), .Y(n184)
);
NOR2XLTS U319 ( .A(n254), .B(intDY[9]), .Y(n188) );
INVX2TS U320 ( .A(intDX[12]), .Y(n284) );
NOR2XLTS U321 ( .A(n284), .B(intDY[12]), .Y(n199) );
NAND2X1TS U322 ( .A(intDY[12]), .B(n284), .Y(n196) );
INVX2TS U323 ( .A(intDY[14]), .Y(n283) );
NAND2X1TS U324 ( .A(intDX[14]), .B(n283), .Y(n203) );
NAND4BBX1TS U325 ( .AN(n188), .BN(n199), .C(n196), .D(n203), .Y(n183) );
INVX2TS U326 ( .A(intDY[13]), .Y(n306) );
NAND2X1TS U327 ( .A(intDX[13]), .B(n306), .Y(n202) );
INVX2TS U328 ( .A(intDX[13]), .Y(n304) );
NAND2X1TS U329 ( .A(intDY[13]), .B(n304), .Y(n197) );
INVX2TS U330 ( .A(intDY[11]), .Y(n310) );
NAND2X1TS U331 ( .A(intDX[11]), .B(n310), .Y(n192) );
NAND4BXLTS U332 ( .AN(n200), .B(n202), .C(n197), .D(n192), .Y(n182) );
NOR4XLTS U333 ( .A(n194), .B(n184), .C(n183), .D(n182), .Y(n185) );
NOR2XLTS U334 ( .A(intDX[11]), .B(n310), .Y(n195) );
INVX2TS U335 ( .A(n187), .Y(n189) );
OAI31X1TS U336 ( .A0(n195), .A1(n194), .A2(n193), .B0(n192), .Y(n198) );
AOI222XLTS U337 ( .A0(intDX[15]), .A1(n204), .B0(intDX[15]), .B1(n303), .C0(
n204), .C1(n303), .Y(n205) );
INVX2TS U338 ( .A(intDY[16]), .Y(n248) );
NAND2X1TS U339 ( .A(intDX[16]), .B(n248), .Y(n223) );
OAI211XLTS U340 ( .A0(n206), .A1(n231), .B0(n205), .C0(n223), .Y(n207) );
NOR2XLTS U341 ( .A(intDY[17]), .B(n280), .Y(n222) );
INVX2TS U342 ( .A(intDX[18]), .Y(n279) );
NOR2XLTS U343 ( .A(intDY[18]), .B(n279), .Y(n226) );
AOI211XLTS U344 ( .A0(n225), .A1(n207), .B0(n222), .C0(n226), .Y(n208) );
INVX2TS U345 ( .A(intDY[19]), .Y(n246) );
INVX2TS U346 ( .A(intDY[18]), .Y(n278) );
OAI22X1TS U347 ( .A0(intDX[19]), .A1(n246), .B0(intDX[18]), .B1(n278), .Y(
n221) );
INVX2TS U348 ( .A(intDX[19]), .Y(n245) );
OAI22X1TS U349 ( .A0(n208), .A1(n221), .B0(intDY[19]), .B1(n245), .Y(n215)
);
INVX2TS U350 ( .A(intDX[20]), .Y(n275) );
NAND2X1TS U351 ( .A(intDY[21]), .B(n273), .Y(n210) );
AOI32X1TS U352 ( .A0(n212), .A1(n211), .A2(n210), .B0(n209), .B1(n211), .Y(
n213) );
AOI222XLTS U353 ( .A0(intDY[23]), .A1(n269), .B0(intDY[23]), .B1(n213), .C0(
n269), .C1(n213), .Y(n214) );
AOI32X1TS U354 ( .A0(n237), .A1(n236), .A2(n215), .B0(n214), .B1(n236), .Y(
n216) );
NAND2X1TS U355 ( .A(n220), .B(load_b_i), .Y(n311) );
CLKBUFX2TS U356 ( .A(n311), .Y(n307) );
NOR2BX1TS U357 ( .AN(load_b_i), .B(n220), .Y(n241) );
INVX2TS U358 ( .A(n241), .Y(n305) );
CLKBUFX2TS U359 ( .A(n305), .Y(n309) );
OAI222X1TS U360 ( .A0(n307), .A1(n296), .B0(load_b_i), .B1(\MRegister/n3 ),
.C0(n309), .C1(n297), .Y(\MRegister/n34 ) );
CLKBUFX2TS U361 ( .A(n311), .Y(n277) );
INVX2TS U362 ( .A(intDX[14]), .Y(n282) );
OAI222X1TS U363 ( .A0(n277), .A1(n282), .B0(load_b_i), .B1(\MRegister/n15 ),
.C0(n309), .C1(n283), .Y(\MRegister/n46 ) );
INVX2TS U364 ( .A(intDY[1]), .Y(n299) );
OAI222X1TS U365 ( .A0(n307), .A1(n298), .B0(load_b_i), .B1(\MRegister/n2 ),
.C0(n309), .C1(n299), .Y(\MRegister/n33 ) );
OAI222X1TS U366 ( .A0(n307), .A1(n292), .B0(load_b_i), .B1(\MRegister/n5 ),
.C0(n309), .C1(n293), .Y(\MRegister/n36 ) );
INVX2TS U367 ( .A(intDY[6]), .Y(n291) );
OAI222X1TS U368 ( .A0(n307), .A1(n290), .B0(load_b_i), .B1(\MRegister/n7 ),
.C0(n309), .C1(n291), .Y(\MRegister/n38 ) );
OAI222X1TS U369 ( .A0(n277), .A1(n247), .B0(load_b_i), .B1(\MRegister/n17 ),
.C0(n309), .C1(n248), .Y(\MRegister/n48 ) );
OAI211XLTS U370 ( .A0(n251), .A1(n220), .B0(load_b_i), .C0(intDX[31]), .Y(
n240) );
INVX2TS U371 ( .A(intDX[0]), .Y(n300) );
OAI22X1TS U372 ( .A0(intDY[0]), .A1(n300), .B0(intDY[19]), .B1(n245), .Y(
n228) );
AOI211XLTS U373 ( .A0(intDY[0]), .A1(n300), .B0(n222), .C0(n221), .Y(n224)
);
NAND4BXLTS U374 ( .AN(n226), .B(n225), .C(n224), .D(n223), .Y(n227) );
NAND4XLTS U375 ( .A(n238), .B(n237), .C(n236), .D(n235), .Y(n252) );
NAND3XLTS U376 ( .A(n251), .B(n241), .C(n252), .Y(n239) );
OAI211XLTS U377 ( .A0(load_b_i), .A1(\SignRegister/n5 ), .B0(n240), .C0(n239), .Y(\SignRegister/n4 ) );
INVX2TS U378 ( .A(intDY[12]), .Y(n285) );
OAI222X1TS U379 ( .A0(n277), .A1(n284), .B0(load_b_i), .B1(\MRegister/n13 ),
.C0(n309), .C1(n285), .Y(\MRegister/n44 ) );
AOI2BB2XLTS U380 ( .B0(intDY[18]), .B1(n241), .A0N(n279), .A1N(n311), .Y(
n242) );
OAI222X1TS U381 ( .A0(n277), .A1(n245), .B0(load_b_i), .B1(\MRegister/n20 ),
.C0(n309), .C1(n246), .Y(\MRegister/n51 ) );
OAI222X1TS U382 ( .A0(n277), .A1(n243), .B0(load_b_i), .B1(\MRegister/n27 ),
.C0(n309), .C1(n244), .Y(\MRegister/n58 ) );
INVX2TS U383 ( .A(intDX[30]), .Y(n249) );
OAI222X1TS U384 ( .A0(n277), .A1(n249), .B0(load_b_i), .B1(\MRegister/n31 ),
.C0(n309), .C1(n250), .Y(\MRegister/n63 ) );
OAI222X1TS U385 ( .A0(n307), .A1(n261), .B0(load_b_i), .B1(\mRegister/n110 ),
.C0(n309), .C1(n262), .Y(\mRegister/n79 ) );
OAI222X1TS U386 ( .A0(n307), .A1(n244), .B0(load_b_i), .B1(\mRegister/n109 ),
.C0(n309), .C1(n243), .Y(\mRegister/n78 ) );
OAI222X1TS U387 ( .A0(n307), .A1(n259), .B0(load_b_i), .B1(\mRegister/n108 ),
.C0(n309), .C1(n260), .Y(\mRegister/n77 ) );
INVX2TS U388 ( .A(intDY[28]), .Y(n257) );
OAI222X1TS U389 ( .A0(n307), .A1(n257), .B0(load_b_i), .B1(\mRegister/n107 ),
.C0(n309), .C1(n258), .Y(\mRegister/n76 ) );
OAI222X1TS U390 ( .A0(n307), .A1(n255), .B0(load_b_i), .B1(\mRegister/n106 ),
.C0(n309), .C1(n256), .Y(\mRegister/n75 ) );
INVX2TS U391 ( .A(intDY[5]), .Y(n265) );
OAI222X1TS U392 ( .A0(n307), .A1(n265), .B0(load_b_i), .B1(\mRegister/n130 ),
.C0(n309), .C1(n266), .Y(\mRegister/n99 ) );
OAI222X1TS U393 ( .A0(n307), .A1(n263), .B0(load_b_i), .B1(\mRegister/n128 ),
.C0(n309), .C1(n264), .Y(\mRegister/n97 ) );
INVX2TS U394 ( .A(intDY[9]), .Y(n253) );
OAI222X1TS U395 ( .A0(n307), .A1(n253), .B0(load_b_i), .B1(\mRegister/n126 ),
.C0(n309), .C1(n254), .Y(\mRegister/n95 ) );
OAI222X1TS U396 ( .A0(n307), .A1(n246), .B0(load_b_i), .B1(\mRegister/n116 ),
.C0(n309), .C1(n245), .Y(\mRegister/n85 ) );
OAI222X1TS U397 ( .A0(n307), .A1(n248), .B0(load_b_i), .B1(\mRegister/n119 ),
.C0(n309), .C1(n247), .Y(\mRegister/n88 ) );
OAI222X1TS U398 ( .A0(n307), .A1(n250), .B0(load_b_i), .B1(\mRegister/n105 ),
.C0(n309), .C1(n249), .Y(\mRegister/n74 ) );
NOR2BX1TS U399 ( .AN(real_op_o), .B(n252), .Y(zero_flag_o) );
OAI222X1TS U400 ( .A0(n277), .A1(n254), .B0(load_b_i), .B1(\MRegister/n10 ),
.C0(n305), .C1(n253), .Y(\MRegister/n41 ) );
OAI222X1TS U401 ( .A0(n277), .A1(n288), .B0(load_b_i), .B1(\MRegister/n9 ),
.C0(n305), .C1(n289), .Y(\MRegister/n40 ) );
OAI222X1TS U402 ( .A0(n311), .A1(n300), .B0(load_b_i), .B1(\MRegister/n1 ),
.C0(n305), .C1(n301), .Y(\MRegister/n32 ) );
OAI222X1TS U403 ( .A0(n311), .A1(n256), .B0(load_b_i), .B1(\MRegister/n30 ),
.C0(n305), .C1(n255), .Y(\MRegister/n61 ) );
OAI222X1TS U404 ( .A0(n277), .A1(n258), .B0(load_b_i), .B1(\MRegister/n29 ),
.C0(n305), .C1(n257), .Y(\MRegister/n60 ) );
OAI222X1TS U405 ( .A0(n311), .A1(n260), .B0(load_b_i), .B1(\MRegister/n28 ),
.C0(n305), .C1(n259), .Y(\MRegister/n59 ) );
OAI222X1TS U406 ( .A0(n311), .A1(n262), .B0(load_b_i), .B1(\MRegister/n26 ),
.C0(n305), .C1(n261), .Y(\MRegister/n57 ) );
INVX2TS U407 ( .A(intDX[24]), .Y(n267) );
OAI222X1TS U408 ( .A0(n277), .A1(n267), .B0(load_b_i), .B1(\MRegister/n25 ),
.C0(n305), .C1(n268), .Y(\MRegister/n56 ) );
OAI222X1TS U409 ( .A0(n311), .A1(n269), .B0(load_b_i), .B1(\MRegister/n24 ),
.C0(n305), .C1(n270), .Y(\MRegister/n55 ) );
INVX2TS U410 ( .A(intDY[22]), .Y(n272) );
OAI222X1TS U411 ( .A0(n277), .A1(n271), .B0(load_b_i), .B1(\MRegister/n23 ),
.C0(n305), .C1(n272), .Y(\MRegister/n54 ) );
INVX2TS U412 ( .A(intDY[21]), .Y(n274) );
OAI222X1TS U413 ( .A0(n277), .A1(n273), .B0(load_b_i), .B1(\MRegister/n22 ),
.C0(n305), .C1(n274), .Y(\MRegister/n53 ) );
OAI222X1TS U414 ( .A0(n277), .A1(n275), .B0(load_b_i), .B1(\MRegister/n21 ),
.C0(n305), .C1(n276), .Y(\MRegister/n52 ) );
INVX2TS U415 ( .A(intDY[17]), .Y(n281) );
OAI222X1TS U416 ( .A0(n277), .A1(n280), .B0(load_b_i), .B1(\MRegister/n18 ),
.C0(n305), .C1(n281), .Y(\MRegister/n49 ) );
OAI222X1TS U417 ( .A0(n277), .A1(n302), .B0(load_b_i), .B1(\MRegister/n16 ),
.C0(n305), .C1(n303), .Y(\MRegister/n47 ) );
OAI222X1TS U418 ( .A0(n277), .A1(n304), .B0(load_b_i), .B1(\MRegister/n14 ),
.C0(n305), .C1(n306), .Y(\MRegister/n45 ) );
OAI222X1TS U419 ( .A0(n277), .A1(n308), .B0(load_b_i), .B1(\MRegister/n12 ),
.C0(n305), .C1(n310), .Y(\MRegister/n43 ) );
INVX2TS U420 ( .A(intDX[10]), .Y(n286) );
OAI222X1TS U421 ( .A0(n277), .A1(n286), .B0(load_b_i), .B1(\MRegister/n11 ),
.C0(n305), .C1(n287), .Y(\MRegister/n42 ) );
OAI222X1TS U422 ( .A0(n277), .A1(n264), .B0(load_b_i), .B1(\MRegister/n8 ),
.C0(n305), .C1(n263), .Y(\MRegister/n39 ) );
OAI222X1TS U423 ( .A0(n311), .A1(n266), .B0(load_b_i), .B1(\MRegister/n6 ),
.C0(n309), .C1(n265), .Y(\MRegister/n37 ) );
OAI222X1TS U424 ( .A0(n311), .A1(n294), .B0(load_b_i), .B1(\MRegister/n4 ),
.C0(n309), .C1(n295), .Y(\MRegister/n35 ) );
OAI222X1TS U425 ( .A0(n311), .A1(n268), .B0(load_b_i), .B1(\mRegister/n111 ),
.C0(n309), .C1(n267), .Y(\mRegister/n80 ) );
OAI222X1TS U426 ( .A0(n307), .A1(n270), .B0(load_b_i), .B1(\mRegister/n112 ),
.C0(n305), .C1(n269), .Y(\mRegister/n81 ) );
OAI222X1TS U427 ( .A0(n311), .A1(n272), .B0(load_b_i), .B1(\mRegister/n113 ),
.C0(n309), .C1(n271), .Y(\mRegister/n82 ) );
OAI222X1TS U428 ( .A0(n307), .A1(n274), .B0(load_b_i), .B1(\mRegister/n114 ),
.C0(n305), .C1(n273), .Y(\mRegister/n83 ) );
OAI222X1TS U429 ( .A0(n311), .A1(n276), .B0(load_b_i), .B1(\mRegister/n115 ),
.C0(n309), .C1(n275), .Y(\mRegister/n84 ) );
OAI222X1TS U430 ( .A0(n279), .A1(n305), .B0(load_b_i), .B1(\mRegister/n117 ),
.C0(n278), .C1(n277), .Y(\mRegister/n86 ) );
OAI222X1TS U431 ( .A0(n307), .A1(n281), .B0(load_b_i), .B1(\mRegister/n118 ),
.C0(n305), .C1(n280), .Y(\mRegister/n87 ) );
OAI222X1TS U432 ( .A0(n311), .A1(n283), .B0(load_b_i), .B1(\mRegister/n121 ),
.C0(n309), .C1(n282), .Y(\mRegister/n90 ) );
OAI222X1TS U433 ( .A0(n311), .A1(n285), .B0(load_b_i), .B1(\mRegister/n123 ),
.C0(n305), .C1(n284), .Y(\mRegister/n92 ) );
OAI222X1TS U434 ( .A0(n311), .A1(n287), .B0(load_b_i), .B1(\mRegister/n125 ),
.C0(n305), .C1(n286), .Y(\mRegister/n94 ) );
OAI222X1TS U435 ( .A0(n307), .A1(n289), .B0(load_b_i), .B1(\mRegister/n127 ),
.C0(n305), .C1(n288), .Y(\mRegister/n96 ) );
OAI222X1TS U436 ( .A0(n307), .A1(n291), .B0(load_b_i), .B1(\mRegister/n129 ),
.C0(n305), .C1(n290), .Y(\mRegister/n98 ) );
OAI222X1TS U437 ( .A0(n307), .A1(n293), .B0(load_b_i), .B1(\mRegister/n131 ),
.C0(n305), .C1(n292), .Y(\mRegister/n100 ) );
OAI222X1TS U438 ( .A0(n311), .A1(n295), .B0(load_b_i), .B1(\mRegister/n132 ),
.C0(n309), .C1(n294), .Y(\mRegister/n101 ) );
OAI222X1TS U439 ( .A0(n307), .A1(n297), .B0(load_b_i), .B1(\mRegister/n133 ),
.C0(n305), .C1(n296), .Y(\mRegister/n102 ) );
OAI222X1TS U440 ( .A0(n311), .A1(n299), .B0(load_b_i), .B1(\mRegister/n134 ),
.C0(n305), .C1(n298), .Y(\mRegister/n103 ) );
OAI222X1TS U441 ( .A0(n307), .A1(n301), .B0(load_b_i), .B1(\mRegister/n135 ),
.C0(n305), .C1(n300), .Y(\mRegister/n104 ) );
OAI222X1TS U442 ( .A0(n311), .A1(n303), .B0(load_b_i), .B1(\mRegister/n120 ),
.C0(n309), .C1(n302), .Y(\mRegister/n89 ) );
OAI222X1TS U443 ( .A0(n307), .A1(n306), .B0(load_b_i), .B1(\mRegister/n122 ),
.C0(n305), .C1(n304), .Y(\mRegister/n91 ) );
OAI222X1TS U444 ( .A0(n311), .A1(n310), .B0(load_b_i), .B1(\mRegister/n124 ),
.C0(n309), .C1(n308), .Y(\mRegister/n93 ) );
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module tmu2_vinterp(
input sys_clk,
input sys_rst,
output busy,
input pipe_stb_i,
output pipe_ack_o,
input signed [17:0] ax,
input signed [17:0] ay,
input signed [17:0] bx,
input signed [17:0] by,
input diff_cx_positive,
input [16:0] diff_cx_q,
input [16:0] diff_cx_r,
input diff_cy_positive,
input [16:0] diff_cy_q,
input [16:0] diff_cy_r,
input diff_dx_positive,
input [16:0] diff_dx_q,
input [16:0] diff_dx_r,
input diff_dy_positive,
input [16:0] diff_dy_q,
input [16:0] diff_dy_r,
input signed [11:0] drx,
input signed [11:0] dry,
input [10:0] dst_squareh,
output pipe_stb_o,
input pipe_ack_i,
output reg signed [11:0] x,
output reg signed [11:0] y,
output signed [17:0] tsx,
output signed [17:0] tsy,
output signed [17:0] tex,
output signed [17:0] tey
);
reg load;
reg next_point;
always @(posedge sys_clk) begin
if(load)
x <= drx;
end
/* Interpolators */
tmu2_geninterp18 i_cx(
.sys_clk(sys_clk),
.load(load),
.next_point(next_point),
.init(ax),
.positive(diff_cx_positive),
.q(diff_cx_q),
.r(diff_cx_r),
.divisor({6'd0, dst_squareh}),
.o(tsx)
);
tmu2_geninterp18 i_cy(
.sys_clk(sys_clk),
.load(load),
.next_point(next_point),
.init(ay),
.positive(diff_cy_positive),
.q(diff_cy_q),
.r(diff_cy_r),
.divisor({6'd0, dst_squareh}),
.o(tsy)
);
tmu2_geninterp18 i_bx(
.sys_clk(sys_clk),
.load(load),
.next_point(next_point),
.init(bx),
.positive(diff_dx_positive),
.q(diff_dx_q),
.r(diff_dx_r),
.divisor({6'd0, dst_squareh}),
.o(tex)
);
tmu2_geninterp18 i_by(
.sys_clk(sys_clk),
.load(load),
.next_point(next_point),
.init(by),
.positive(diff_dy_positive),
.q(diff_dy_q),
.r(diff_dy_r),
.divisor({6'd0, dst_squareh}),
.o(tey)
);
/* y datapath */
always @(posedge sys_clk) begin
if(load)
y <= dry;
else if(next_point)
y <= y + 12'd1;
end
/* Controller */
reg [10:0] remaining_points;
always @(posedge sys_clk) begin
if(load)
remaining_points <= dst_squareh - 11'd1;
else if(next_point)
remaining_points <= remaining_points - 11'd1;
end
wire last_point = remaining_points == 11'd0;
reg state;
reg next_state;
parameter IDLE = 1'b0;
parameter BUSY = 1'b1;
always @(posedge sys_clk) begin
if(sys_rst)
state <= IDLE;
else
state <= next_state;
end
assign busy = state;
assign pipe_ack_o = ~state;
assign pipe_stb_o = state;
always @(*) begin
next_state = state;
load = 1'b0;
next_point = 1'b0;
case(state)
IDLE: begin
if(pipe_stb_i) begin
load = 1'b1;
next_state = BUSY;
end
end
BUSY: begin
if(pipe_ack_i) begin
if(last_point)
next_state = IDLE;
else
next_point = 1'b1;
end
end
endcase
end
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Wed Sep 20 21:08:01 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_axi_timer_0_0_stub.v
// Design : zqynq_lab_1_design_axi_timer_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "axi_timer,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(capturetrig0, capturetrig1, generateout0,
generateout1, pwm0, interrupt, freeze, s_axi_aclk, s_axi_aresetn, s_axi_awaddr, s_axi_awvalid,
s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready, s_axi_bresp,
s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arvalid, s_axi_arready, s_axi_rdata,
s_axi_rresp, s_axi_rvalid, s_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="capturetrig0,capturetrig1,generateout0,generateout1,pwm0,interrupt,freeze,s_axi_aclk,s_axi_aresetn,s_axi_awaddr[4:0],s_axi_awvalid,s_axi_awready,s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid,s_axi_wready,s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_araddr[4:0],s_axi_arvalid,s_axi_arready,s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid,s_axi_rready" */;
input capturetrig0;
input capturetrig1;
output generateout0;
output generateout1;
output pwm0;
output interrupt;
input freeze;
input s_axi_aclk;
input s_axi_aresetn;
input [4:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [4:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
endmodule
|
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_design_nios2_gen2_0_cpu_debug_slave_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
/* Generated by Yosys 0.5 (git sha1 c3c9fbf, gcc 4.8.2-19ubuntu1 -O2 -fstack-protector -fPIC -Os) */
(* top = 1 *)
(* src = "test.v:1" *)
module dffr_17(q, d, clk, reset);
(* src = "test.v:5" *)
input clk;
(* src = "test.v:4" *)
input [16:0] d;
(* src = "test.v:3" *)
output [16:0] q;
(* src = "test.v:5" *)
input reset;
DFFSR _00_ (
.CLK(clk),
.D(d[0]),
.Q(q[0]),
.R(reset),
.S(1'b1)
);
DFFSR _01_ (
.CLK(clk),
.D(d[1]),
.Q(q[1]),
.R(reset),
.S(1'b1)
);
DFFSR _02_ (
.CLK(clk),
.D(d[2]),
.Q(q[2]),
.R(reset),
.S(1'b1)
);
DFFSR _03_ (
.CLK(clk),
.D(d[3]),
.Q(q[3]),
.R(reset),
.S(1'b1)
);
DFFSR _04_ (
.CLK(clk),
.D(d[4]),
.Q(q[4]),
.R(reset),
.S(1'b1)
);
DFFSR _05_ (
.CLK(clk),
.D(d[5]),
.Q(q[5]),
.R(reset),
.S(1'b1)
);
DFFSR _06_ (
.CLK(clk),
.D(d[6]),
.Q(q[6]),
.R(reset),
.S(1'b1)
);
DFFSR _07_ (
.CLK(clk),
.D(d[7]),
.Q(q[7]),
.R(reset),
.S(1'b1)
);
DFFSR _08_ (
.CLK(clk),
.D(d[8]),
.Q(q[8]),
.R(reset),
.S(1'b1)
);
DFFSR _09_ (
.CLK(clk),
.D(d[9]),
.Q(q[9]),
.R(reset),
.S(1'b1)
);
DFFSR _10_ (
.CLK(clk),
.D(d[10]),
.Q(q[10]),
.R(reset),
.S(1'b1)
);
DFFSR _11_ (
.CLK(clk),
.D(d[11]),
.Q(q[11]),
.R(reset),
.S(1'b1)
);
DFFSR _12_ (
.CLK(clk),
.D(d[12]),
.Q(q[12]),
.R(reset),
.S(1'b1)
);
DFFSR _13_ (
.CLK(clk),
.D(d[13]),
.Q(q[13]),
.R(reset),
.S(1'b1)
);
DFFSR _14_ (
.CLK(clk),
.D(d[14]),
.Q(q[14]),
.R(reset),
.S(1'b1)
);
DFFSR _15_ (
.CLK(clk),
.D(d[15]),
.Q(q[15]),
.R(reset),
.S(1'b1)
);
DFFSR _16_ (
.CLK(clk),
.D(d[16]),
.Q(q[16]),
.R(reset),
.S(1'b1)
);
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: NetFPGA_Gen3x4If128.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Top level module for RIFFA 2.2 reference design for the
// the Xilinx NetFPGA Development Board.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`include "functions.vh"
`include "riffa.vh"
`include "ultrascale.vh"
`timescale 1ps / 1ps
module NetFPGA_Gen3x4If128
#(// Number of RIFFA Channels
parameter C_NUM_CHNL = 1,
// Number of PCIe Lanes
parameter C_NUM_LANES = 4,
// Settings from Vivado IP Generator
parameter C_PCI_DATA_WIDTH = 128,
parameter C_MAX_PAYLOAD_BYTES = 256,
parameter C_LOG_NUM_TAGS = 6)
(output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXP,
output [(C_NUM_LANES - 1) : 0] PCI_EXP_TXN,
input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXP,
input [(C_NUM_LANES - 1) : 0] PCI_EXP_RXN,
output [1:0] LED,
input PCIE_REFCLK_P,
input PCIE_REFCLK_N,
input PCIE_RESET_N);
// Clocks, etc
wire user_lnk_up;
wire user_clk;
wire user_reset;
wire pcie_refclk;
wire pcie_reset_n;
// Interface: RQ (TXC)
wire s_axis_rq_tlast;
wire [C_PCI_DATA_WIDTH-1:0] s_axis_rq_tdata;
wire [`SIG_RQ_TUSER_W-1:0] s_axis_rq_tuser;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_rq_tkeep;
wire s_axis_rq_tready;
wire s_axis_rq_tvalid;
// Interface: RC (RXC)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_rc_tdata;
wire [`SIG_RC_TUSER_W-1:0] m_axis_rc_tuser;
wire m_axis_rc_tlast;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_rc_tkeep;
wire m_axis_rc_tvalid;
wire m_axis_rc_tready;
// Interface: CQ (RXR)
wire [C_PCI_DATA_WIDTH-1:0] m_axis_cq_tdata;
wire [`SIG_CQ_TUSER_W-1:0] m_axis_cq_tuser;
wire m_axis_cq_tlast;
wire [(C_PCI_DATA_WIDTH/32)-1:0] m_axis_cq_tkeep;
wire m_axis_cq_tvalid;
wire m_axis_cq_tready;
// Interface: CC (TXC)
wire [C_PCI_DATA_WIDTH-1:0] s_axis_cc_tdata;
wire [`SIG_CC_TUSER_W-1:0] s_axis_cc_tuser;
wire s_axis_cc_tlast;
wire [(C_PCI_DATA_WIDTH/32)-1:0] s_axis_cc_tkeep;
wire s_axis_cc_tvalid;
wire s_axis_cc_tready;
// Configuration (CFG) Interface
wire [3:0] pcie_rq_seq_num;
wire pcie_rq_seq_num_vld;
wire [5:0] pcie_rq_tag;
wire pcie_rq_tag_vld;
wire pcie_cq_np_req;
wire [5:0] pcie_cq_np_req_count;
wire cfg_phy_link_down;
wire [3:0] cfg_negotiated_width; // CONFIG_LINK_WIDTH
wire [2:0] cfg_current_speed; // CONFIG_LINK_RATE
wire [2:0] cfg_max_payload; // CONFIG_MAX_PAYLOAD
wire [2:0] cfg_max_read_req; // CONFIG_MAX_READ_REQUEST
wire [7:0] cfg_function_status; // [2] = CONFIG_BUS_MASTER_ENABLE
wire [5:0] cfg_function_power_state; // Ignorable but not removable
wire [11:0] cfg_vf_status; // Ignorable but not removable
wire [17:0] cfg_vf_power_state; // Ignorable but not removable
wire [1:0] cfg_link_power_state; // Ignorable but not removable
// Error Reporting Interface
wire cfg_err_cor_out;
wire cfg_err_nonfatal_out;
wire cfg_err_fatal_out;
wire cfg_ltr_enable;
wire [5:0] cfg_ltssm_state;
wire [1:0] cfg_rcb_status;
wire [1:0] cfg_dpa_substate_change;
wire [1:0] cfg_obff_enable;
wire cfg_pl_status_change;
wire [1:0] cfg_tph_requester_enable;
wire [5:0] cfg_tph_st_mode;
wire [5:0] cfg_vf_tph_requester_enable;
wire [17:0] cfg_vf_tph_st_mode;
wire [7:0] cfg_fc_ph;
wire [11:0] cfg_fc_pd;
wire [7:0] cfg_fc_nph;
wire [11:0] cfg_fc_npd;
wire [7:0] cfg_fc_cplh;
wire [11:0] cfg_fc_cpld;
wire [2:0] cfg_fc_sel;
// Interrupt Interface Signals
wire [3:0] cfg_interrupt_int;
wire [1:0] cfg_interrupt_pending;
wire cfg_interrupt_sent;
wire [1:0] cfg_interrupt_msi_enable;
wire [5:0] cfg_interrupt_msi_vf_enable;
wire [5:0] cfg_interrupt_msi_mmenable;
wire cfg_interrupt_msi_mask_update;
wire [31:0] cfg_interrupt_msi_data;
wire [3:0] cfg_interrupt_msi_select;
wire [31:0] cfg_interrupt_msi_int;
wire [63:0] cfg_interrupt_msi_pending_status;
wire cfg_interrupt_msi_sent;
wire cfg_interrupt_msi_fail;
wire [2:0] cfg_interrupt_msi_attr;
wire cfg_interrupt_msi_tph_present;
wire [1:0] cfg_interrupt_msi_tph_type;
wire [8:0] cfg_interrupt_msi_tph_st_tag;
wire [2:0] cfg_interrupt_msi_function_number;
wire rst_out;
wire [C_NUM_CHNL-1:0] chnl_rx_clk;
wire [C_NUM_CHNL-1:0] chnl_rx;
wire [C_NUM_CHNL-1:0] chnl_rx_ack;
wire [C_NUM_CHNL-1:0] chnl_rx_last;
wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_rx_len;
wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_rx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_rx_data;
wire [C_NUM_CHNL-1:0] chnl_rx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_rx_data_ren;
wire [C_NUM_CHNL-1:0] chnl_tx_clk;
wire [C_NUM_CHNL-1:0] chnl_tx;
wire [C_NUM_CHNL-1:0] chnl_tx_ack;
wire [C_NUM_CHNL-1:0] chnl_tx_last;
wire [(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0] chnl_tx_len;
wire [(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0] chnl_tx_off;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] chnl_tx_data;
wire [C_NUM_CHNL-1:0] chnl_tx_data_valid;
wire [C_NUM_CHNL-1:0] chnl_tx_data_ren;
genvar chnl;
IBUF
#()
pci_reset_n_ibuf
(.O(pcie_reset_n),
.I(PCIE_RESET_N));
IBUFDS_GTE2
#()
refclk_ibuf
(.O(pcie_refclk),
.ODIV2(),
.I(PCIE_REFCLK_P),
.CEB(1'b0),
.IB(PCIE_REFCLK_N));
OBUF
#()
led_0_obuf
(.O(LED[0]),
.I(cfg_ltssm_state[0]));
OBUF
#()
led_1_obuf
(.O(LED[1]),
.I(cfg_ltssm_state[1]));
// Core Top Level Wrapper
PCIeGen3x4If128
#()
pcie3_7x_0_i
(//---------------------------------------------------------------------
// PCI Express (pci_exp) Interface
//---------------------------------------------------------------------
.pci_exp_txn ( PCI_EXP_TXN ),
.pci_exp_txp ( PCI_EXP_TXP ),
.pci_exp_rxn ( PCI_EXP_RXN ),
.pci_exp_rxp ( PCI_EXP_RXP ),
//---------------------------------------------------------------------
// AXI Interface
//---------------------------------------------------------------------
.user_clk ( user_clk ),
.user_reset ( user_reset ),
.user_lnk_up ( user_lnk_up ),
.user_app_rdy ( ),
.s_axis_rq_tlast ( s_axis_rq_tlast ),
.s_axis_rq_tdata ( s_axis_rq_tdata ),
.s_axis_rq_tuser ( s_axis_rq_tuser ),
.s_axis_rq_tkeep ( s_axis_rq_tkeep ),
.s_axis_rq_tready ( s_axis_rq_tready ),
.s_axis_rq_tvalid ( s_axis_rq_tvalid ),
.m_axis_rc_tdata ( m_axis_rc_tdata ),
.m_axis_rc_tuser ( m_axis_rc_tuser ),
.m_axis_rc_tlast ( m_axis_rc_tlast ),
.m_axis_rc_tkeep ( m_axis_rc_tkeep ),
.m_axis_rc_tvalid ( m_axis_rc_tvalid ),
.m_axis_rc_tready ( {22{m_axis_rc_tready}} ),
.m_axis_cq_tdata ( m_axis_cq_tdata ),
.m_axis_cq_tuser ( m_axis_cq_tuser ),
.m_axis_cq_tlast ( m_axis_cq_tlast ),
.m_axis_cq_tkeep ( m_axis_cq_tkeep ),
.m_axis_cq_tvalid ( m_axis_cq_tvalid ),
.m_axis_cq_tready ( {22{m_axis_cq_tready}} ),
.s_axis_cc_tdata ( s_axis_cc_tdata ),
.s_axis_cc_tuser ( s_axis_cc_tuser ),
.s_axis_cc_tlast ( s_axis_cc_tlast ),
.s_axis_cc_tkeep ( s_axis_cc_tkeep ),
.s_axis_cc_tvalid ( s_axis_cc_tvalid ),
.s_axis_cc_tready ( s_axis_cc_tready ),
//---------------------------------------------------------------------
// Configuration (CFG) Interface
//---------------------------------------------------------------------
.pcie_rq_seq_num ( pcie_rq_seq_num ),
.pcie_rq_seq_num_vld ( pcie_rq_seq_num_vld ),
.pcie_rq_tag ( pcie_rq_tag ),
.pcie_rq_tag_vld ( pcie_rq_tag_vld ),
.pcie_cq_np_req ( pcie_cq_np_req ),
.pcie_cq_np_req_count ( pcie_cq_np_req_count ),
.cfg_phy_link_down ( cfg_phy_link_down ),
.cfg_phy_link_status ( cfg_phy_link_status),
.cfg_negotiated_width ( cfg_negotiated_width ),
.cfg_current_speed ( cfg_current_speed ),
.cfg_max_payload ( cfg_max_payload ),
.cfg_max_read_req ( cfg_max_read_req ),
.cfg_function_status ( cfg_function_status ),
.cfg_function_power_state ( cfg_function_power_state ),
.cfg_vf_status ( cfg_vf_status ),
.cfg_vf_power_state ( cfg_vf_power_state ),
.cfg_link_power_state ( cfg_link_power_state ),
// Error Reporting Interface
.cfg_err_cor_out ( cfg_err_cor_out ),
.cfg_err_nonfatal_out ( cfg_err_nonfatal_out ),
.cfg_err_fatal_out ( cfg_err_fatal_out ),
.cfg_ltr_enable ( cfg_ltr_enable ),
.cfg_ltssm_state ( cfg_ltssm_state ),
.cfg_rcb_status ( cfg_rcb_status ),
.cfg_dpa_substate_change ( cfg_dpa_substate_change ),
.cfg_obff_enable ( cfg_obff_enable ),
.cfg_pl_status_change ( cfg_pl_status_change ),
.cfg_tph_requester_enable ( cfg_tph_requester_enable ),
.cfg_tph_st_mode ( cfg_tph_st_mode ),
.cfg_vf_tph_requester_enable ( cfg_vf_tph_requester_enable ),
.cfg_vf_tph_st_mode ( cfg_vf_tph_st_mode ),
.cfg_fc_ph ( cfg_fc_ph ),
.cfg_fc_pd ( cfg_fc_pd ),
.cfg_fc_nph ( cfg_fc_nph ),
.cfg_fc_npd ( cfg_fc_npd ),
.cfg_fc_cplh ( cfg_fc_cplh ),
.cfg_fc_cpld ( cfg_fc_cpld ),
.cfg_fc_sel ( cfg_fc_sel ),
//---------------------------------------------------------------------
// EP Only
//---------------------------------------------------------------------
// Interrupt Interface Signals
.cfg_interrupt_int ( cfg_interrupt_int ),
.cfg_interrupt_pending ( cfg_interrupt_pending ),
.cfg_interrupt_sent ( cfg_interrupt_sent ),
.cfg_interrupt_msi_enable ( cfg_interrupt_msi_enable ),
.cfg_interrupt_msi_vf_enable ( cfg_interrupt_msi_vf_enable ),
.cfg_interrupt_msi_mmenable ( cfg_interrupt_msi_mmenable ),
.cfg_interrupt_msi_mask_update ( cfg_interrupt_msi_mask_update ),
.cfg_interrupt_msi_data ( cfg_interrupt_msi_data ),
.cfg_interrupt_msi_select ( cfg_interrupt_msi_select ),
.cfg_interrupt_msi_int ( cfg_interrupt_msi_int ),
.cfg_interrupt_msi_pending_status ( cfg_interrupt_msi_pending_status ),
.cfg_interrupt_msi_sent ( cfg_interrupt_msi_sent ),
.cfg_interrupt_msi_fail ( cfg_interrupt_msi_fail ),
.cfg_interrupt_msi_attr ( cfg_interrupt_msi_attr ),
.cfg_interrupt_msi_tph_present ( cfg_interrupt_msi_tph_present ),
.cfg_interrupt_msi_tph_type ( cfg_interrupt_msi_tph_type ),
.cfg_interrupt_msi_tph_st_tag ( cfg_interrupt_msi_tph_st_tag ),
.cfg_interrupt_msi_function_number ( cfg_interrupt_msi_function_number ),
//---------------------------------------------------------------------
// System(SYS) Interface
//---------------------------------------------------------------------
.sys_clk (pcie_refclk),
.sys_reset (~pcie_reset_n));
riffa_wrapper_NetFPGA
#(/*AUTOINSTPARAM*/
// Parameters
.C_LOG_NUM_TAGS (C_LOG_NUM_TAGS),
.C_NUM_CHNL (C_NUM_CHNL),
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_PAYLOAD_BYTES (C_MAX_PAYLOAD_BYTES))
riffa
(// Outputs
.M_AXIS_CQ_TREADY (m_axis_cq_tready),
.M_AXIS_RC_TREADY (m_axis_rc_tready),
.S_AXIS_CC_TVALID (s_axis_cc_tvalid),
.S_AXIS_CC_TLAST (s_axis_cc_tlast),
.S_AXIS_CC_TDATA (s_axis_cc_tdata[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_CC_TKEEP (s_axis_cc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_CC_TUSER (s_axis_cc_tuser[`SIG_CC_TUSER_W-1:0]),
.S_AXIS_RQ_TVALID (s_axis_rq_tvalid),
.S_AXIS_RQ_TLAST (s_axis_rq_tlast),
.S_AXIS_RQ_TDATA (s_axis_rq_tdata[C_PCI_DATA_WIDTH-1:0]),
.S_AXIS_RQ_TKEEP (s_axis_rq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.S_AXIS_RQ_TUSER (s_axis_rq_tuser[`SIG_RQ_TUSER_W-1:0]),
.USER_CLK (user_clk),
.USER_RESET (user_reset),
.CFG_INTERRUPT_INT (cfg_interrupt_int[3:0]),
.CFG_INTERRUPT_PENDING (cfg_interrupt_pending[1:0]),
.CFG_INTERRUPT_MSI_SELECT (cfg_interrupt_msi_select[3:0]),
.CFG_INTERRUPT_MSI_INT (cfg_interrupt_msi_int[31:0]),
.CFG_INTERRUPT_MSI_PENDING_STATUS(cfg_interrupt_msi_pending_status[63:0]),
.CFG_INTERRUPT_MSI_ATTR (cfg_interrupt_msi_attr[2:0]),
.CFG_INTERRUPT_MSI_TPH_PRESENT (cfg_interrupt_msi_tph_present),
.CFG_INTERRUPT_MSI_TPH_TYPE (cfg_interrupt_msi_tph_type[1:0]),
.CFG_INTERRUPT_MSI_TPH_ST_TAG (cfg_interrupt_msi_tph_st_tag[8:0]),
.CFG_INTERRUPT_MSI_FUNCTION_NUMBER(cfg_interrupt_msi_function_number[2:0]),
.CFG_FC_SEL (cfg_fc_sel[2:0]),
.PCIE_CQ_NP_REQ (pcie_cq_np_req),
.RST_OUT (rst_out),
.CHNL_RX (chnl_rx[C_NUM_CHNL-1:0]),
.CHNL_RX_LAST (chnl_rx_last[C_NUM_CHNL-1:0]),
.CHNL_RX_LEN (chnl_rx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_RX_OFF (chnl_rx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_RX_DATA (chnl_rx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_RX_DATA_VALID (chnl_rx_data_valid[C_NUM_CHNL-1:0]),
.CHNL_TX_ACK (chnl_tx_ack[C_NUM_CHNL-1:0]),
.CHNL_TX_DATA_REN (chnl_tx_data_ren[C_NUM_CHNL-1:0]),
// Inputs
.M_AXIS_CQ_TVALID (m_axis_cq_tvalid),
.M_AXIS_CQ_TLAST (m_axis_cq_tlast),
.M_AXIS_CQ_TDATA (m_axis_cq_tdata[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_CQ_TKEEP (m_axis_cq_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_CQ_TUSER (m_axis_cq_tuser[`SIG_CQ_TUSER_W-1:0]),
.M_AXIS_RC_TVALID (m_axis_rc_tvalid),
.M_AXIS_RC_TLAST (m_axis_rc_tlast),
.M_AXIS_RC_TDATA (m_axis_rc_tdata[C_PCI_DATA_WIDTH-1:0]),
.M_AXIS_RC_TKEEP (m_axis_rc_tkeep[(C_PCI_DATA_WIDTH/32)-1:0]),
.M_AXIS_RC_TUSER (m_axis_rc_tuser[`SIG_RC_TUSER_W-1:0]),
.S_AXIS_CC_TREADY (s_axis_cc_tready),
.S_AXIS_RQ_TREADY (s_axis_rq_tready),
.CFG_INTERRUPT_MSI_ENABLE (cfg_interrupt_msi_enable[1:0]),
.CFG_INTERRUPT_MSI_MASK_UPDATE (cfg_interrupt_msi_mask_update),
.CFG_INTERRUPT_MSI_DATA (cfg_interrupt_msi_data[31:0]),
.CFG_INTERRUPT_MSI_SENT (cfg_interrupt_msi_sent),
.CFG_INTERRUPT_MSI_FAIL (cfg_interrupt_msi_fail),
.CFG_FC_CPLH (cfg_fc_cplh[7:0]),
.CFG_FC_CPLD (cfg_fc_cpld[11:0]),
.CFG_NEGOTIATED_WIDTH (cfg_negotiated_width[3:0]),
.CFG_CURRENT_SPEED (cfg_current_speed[2:0]),
.CFG_MAX_PAYLOAD (cfg_max_payload[2:0]),
.CFG_MAX_READ_REQ (cfg_max_read_req[2:0]),
.CFG_FUNCTION_STATUS (cfg_function_status[7:0]),
.CFG_RCB_STATUS (cfg_rcb_status[1:0]),
.CHNL_RX_CLK (chnl_rx_clk[C_NUM_CHNL-1:0]),
.CHNL_RX_ACK (chnl_rx_ack[C_NUM_CHNL-1:0]),
.CHNL_RX_DATA_REN (chnl_rx_data_ren[C_NUM_CHNL-1:0]),
.CHNL_TX_CLK (chnl_tx_clk[C_NUM_CHNL-1:0]),
.CHNL_TX (chnl_tx[C_NUM_CHNL-1:0]),
.CHNL_TX_LAST (chnl_tx_last[C_NUM_CHNL-1:0]),
.CHNL_TX_LEN (chnl_tx_len[(C_NUM_CHNL*`SIG_CHNL_LENGTH_W)-1:0]),
.CHNL_TX_OFF (chnl_tx_off[(C_NUM_CHNL*`SIG_CHNL_OFFSET_W)-1:0]),
.CHNL_TX_DATA (chnl_tx_data[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.CHNL_TX_DATA_VALID (chnl_tx_data_valid[C_NUM_CHNL-1:0])
/*AUTOINST*/);
generate
for (chnl = 0; chnl < C_NUM_CHNL; chnl = chnl + 1) begin : test_channels
chnl_tester
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH))
module1
(.CLK(user_clk),
.RST(rst_out), // riffa_reset includes riffa_endpoint resets
// Rx interface
.CHNL_RX_CLK(chnl_rx_clk[chnl]),
.CHNL_RX(chnl_rx[chnl]),
.CHNL_RX_ACK(chnl_rx_ack[chnl]),
.CHNL_RX_LAST(chnl_rx_last[chnl]),
.CHNL_RX_LEN(chnl_rx_len[32*chnl +:32]),
.CHNL_RX_OFF(chnl_rx_off[31*chnl +:31]),
.CHNL_RX_DATA(chnl_rx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(chnl_rx_data_valid[chnl]),
.CHNL_RX_DATA_REN(chnl_rx_data_ren[chnl]),
// Tx interface
.CHNL_TX_CLK(chnl_tx_clk[chnl]),
.CHNL_TX(chnl_tx[chnl]),
.CHNL_TX_ACK(chnl_tx_ack[chnl]),
.CHNL_TX_LAST(chnl_tx_last[chnl]),
.CHNL_TX_LEN(chnl_tx_len[32*chnl +:32]),
.CHNL_TX_OFF(chnl_tx_off[31*chnl +:31]),
.CHNL_TX_DATA(chnl_tx_data[C_PCI_DATA_WIDTH*chnl +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(chnl_tx_data_valid[chnl]),
.CHNL_TX_DATA_REN(chnl_tx_data_ren[chnl])
/*AUTOINST*/);
end
endgenerate
endmodule
// Local Variables:
// verilog-library-directories:("../../../../riffa_hdl/" "../../")
// End:
|
module nmac_crc_check(
clk,
wr_clk,
reset,
in_pkt_wrreq,
in_pkt,
in_pkt_usedw,
in_valid_wrreq,
in_valid,
port_error,
out_pkt_wrreq,
out_pkt,
out_pkt_usedw,
out_valid_wrreq,
out_valid
);
input clk;
input wr_clk;
input reset;
input in_pkt_wrreq;
input [138:0]in_pkt;
output [7:0]in_pkt_usedw;
input in_valid_wrreq;
input in_valid;
output port_error;
output out_pkt_wrreq;
output [138:0]out_pkt;
input [7:0]out_pkt_usedw;
output out_valid_wrreq;
output out_valid;
reg out_pkt_wrreq;
reg [138:0]out_pkt;
reg out_valid_wrreq;
reg out_valid;
reg port_error;
reg [2:0]current_state;
parameter idle=3'b0,
transmit=3'b001,
wait_crcbad=3'b010,
discard=3'b011;
always@(posedge clk or negedge reset)
if(!reset)
begin
crc_data_valid<=1'b0;
crc_empty<=4'b0;
start_of_pkt<=1'b0;
end_of_pkt<=1'b0;
in_pkt_rdreq<=1'b0;
in_valid_rdreq<=1'b0;
out_pkt_wrreq<=1'b0;
out_valid_wrreq<=1'b0;
port_error <= 1'b0;
current_state<=idle;
end
else
begin
case(current_state)
idle:
begin
out_valid_wrreq<=1'b0;
port_error <= 1'b0;
if(out_pkt_usedw<8'd161)
begin
if(!in_valid_empty)
begin
if(in_valid_q==1'b1)
begin
in_pkt_rdreq<=1'b1;
in_valid_rdreq<=1'b1;
current_state<=transmit;
end
else
begin
in_pkt_rdreq<=1'b1;
in_valid_rdreq<=1'b1;
current_state<=discard;
end
end
else
begin
current_state<=idle;
end
end
else
begin
current_state<=idle;
end
end//end idle;
transmit:
begin
in_valid_rdreq<=1'b0;
if(in_pkt_q[138:136]==3'b101)//header;
begin
in_pkt_rdreq<=1'b1;
crc_data_valid<=1'b1;
crc_data<=in_pkt_q[127:0];
start_of_pkt<=1'b1;
out_pkt_wrreq<=1'b1;
out_pkt<=in_pkt_q;
current_state<=transmit;
end
else if(in_pkt_q[138:136]==3'b110)//tail;
begin
in_pkt_rdreq<=1'b0;
crc_data_valid<=1'b1;
crc_data<=in_pkt_q[127:0];
end_of_pkt<=1'b1;
crc_empty<=4'b1111-in_pkt_q[135:132];
out_pkt_wrreq<=1'b1;
out_pkt<=in_pkt_q;
current_state<=wait_crcbad;
end
else//middle;
begin
in_pkt_rdreq<=1'b1;
start_of_pkt<=1'b0;
crc_data_valid<=1'b1;
crc_data<=in_pkt_q[127:0];
out_pkt_wrreq<=1'b1;
out_pkt<=in_pkt_q;
current_state<=transmit;
end
end//end transmit;
wait_crcbad:
begin
end_of_pkt<=1'b0;
crc_empty<=4'b0;
crc_data_valid<=1'b0;
out_pkt_wrreq<=1'b0;
if(crc_bad_valid==1'b1)
begin
if(crc_bad==1'b1)//error;
begin
out_valid_wrreq<=1'b1;
out_valid<=1'b0;
port_error <= 1'b1;
end
else
begin
out_valid_wrreq<=1'b1;
out_valid<=1'b1;
end
current_state<=idle;
end
else
begin
current_state<=wait_crcbad;
end
end//end wait_crcbad;
discard:
begin
in_valid_rdreq<=1'b0;
in_pkt_rdreq<=1'b1;
if(in_pkt_q[138:136]==3'b110)//tail;
begin
in_pkt_rdreq<=1'b0;
current_state<=idle;
end
else if(in_pkt_q[138:136]==3'b111)//tail;
begin
in_pkt_rdreq<=1'b0;
current_state<=idle;
end
else
begin
current_state<=discard;
end
end//end discard;
default:
begin
current_state<=idle;
end
endcase
end
reg [127:0]crc_data;
reg crc_data_valid;
reg [3:0]crc_empty;
reg start_of_pkt;
reg end_of_pkt;
wire crc_bad_valid;
wire crc_bad;
check_ip check_ip0(
.clk(clk),
.data(crc_data),
.datavalid(crc_data_valid),
.empty(crc_empty),
.endofpacket(end_of_pkt),
.reset_n(reset),
.startofpacket(start_of_pkt),
.crcbad(crc_bad),
.crcvalid(crc_bad_valid)
);
reg in_pkt_rdreq;
wire [138:0]in_pkt_q;
wire [7:0]in_pkt_usedw;
asy_256_139 asy_256_139(
.aclr(!reset),
.data(in_pkt),
.rdclk(clk),
.rdreq(in_pkt_rdreq),
.wrclk(wr_clk),
.wrreq(in_pkt_wrreq),
.q(in_pkt_q),
.wrusedw(in_pkt_usedw)
);
reg in_valid_rdreq;
wire in_valid_q;
wire in_valid_empty;
asy_64_1 asy_64_1(
.aclr(!reset),
.data(in_valid),
.rdclk(clk),
.rdreq(in_valid_rdreq),
.wrclk(wr_clk),
.wrreq(in_valid_wrreq),
.q(in_valid_q),
.rdempty(in_valid_empty)
);
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (win64) Build 2018833 Wed Oct 4 19:58:22 MDT 2017
// Date : Fri Nov 17 16:06:27 2017
// Host : egk-pc running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// D:/Development/FPGA/InterNoC/InterNoC.srcs/sources_1/bd/DemoInterconnect/ip/DemoInterconnect_internoc_ni_axi_master_0_0/DemoInterconnect_internoc_ni_axi_master_0_0_stub.v
// Design : DemoInterconnect_internoc_ni_axi_master_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a15tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "internoc_ni_axi_master_v1_0,Vivado 2017.3" *)
module DemoInterconnect_internoc_ni_axi_master_0_0(if00_data_in, if00_load_in, if00_data_out,
if00_load_out, if00_send_done, if00_send_busy, m00_axi_awaddr, m00_axi_awprot,
m00_axi_awvalid, m00_axi_awready, m00_axi_wdata, m00_axi_wstrb, m00_axi_wvalid,
m00_axi_wready, m00_axi_bresp, m00_axi_bvalid, m00_axi_bready, m00_axi_araddr,
m00_axi_arprot, m00_axi_arvalid, m00_axi_arready, m00_axi_rdata, m00_axi_rresp,
m00_axi_rvalid, m00_axi_rready, m00_axi_aclk, m00_axi_aresetn)
/* synthesis syn_black_box black_box_pad_pin="if00_data_in[7:0],if00_load_in,if00_data_out[7:0],if00_load_out,if00_send_done,if00_send_busy,m00_axi_awaddr[31:0],m00_axi_awprot[2:0],m00_axi_awvalid,m00_axi_awready,m00_axi_wdata[31:0],m00_axi_wstrb[3:0],m00_axi_wvalid,m00_axi_wready,m00_axi_bresp[1:0],m00_axi_bvalid,m00_axi_bready,m00_axi_araddr[31:0],m00_axi_arprot[2:0],m00_axi_arvalid,m00_axi_arready,m00_axi_rdata[31:0],m00_axi_rresp[1:0],m00_axi_rvalid,m00_axi_rready,m00_axi_aclk,m00_axi_aresetn" */;
input [7:0]if00_data_in;
input if00_load_in;
output [7:0]if00_data_out;
output if00_load_out;
input if00_send_done;
input if00_send_busy;
output [31:0]m00_axi_awaddr;
output [2:0]m00_axi_awprot;
output m00_axi_awvalid;
input m00_axi_awready;
output [31:0]m00_axi_wdata;
output [3:0]m00_axi_wstrb;
output m00_axi_wvalid;
input m00_axi_wready;
input [1:0]m00_axi_bresp;
input m00_axi_bvalid;
output m00_axi_bready;
output [31:0]m00_axi_araddr;
output [2:0]m00_axi_arprot;
output m00_axi_arvalid;
input m00_axi_arready;
input [31:0]m00_axi_rdata;
input [1:0]m00_axi_rresp;
input m00_axi_rvalid;
output m00_axi_rready;
input m00_axi_aclk;
input m00_axi_aresetn;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2BB2AI_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__O2BB2AI_PP_BLACKBOX_V
/**
* o2bb2ai: 2-input NAND and 2-input OR into 2-input NAND.
*
* Y = !(!(A1 & A2) & (B1 | B2))
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__o2bb2ai (
Y ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2BB2AI_PP_BLACKBOX_V
|
module spiral_16(
i_data,
o_data_4,
o_data_13,
o_data_22,
o_data_31,
o_data_38,
o_data_46,
o_data_54,
o_data_61,
o_data_67,
o_data_73,
o_data_78,
o_data_82,
o_data_85,
o_data_88,
o_data_90
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input signed [16:0] i_data;
output signed [16+7:0] o_data_4;
output signed [16+7:0] o_data_13;
output signed [16+7:0] o_data_22;
output signed [16+7:0] o_data_31;
output signed [16+7:0] o_data_38;
output signed [16+7:0] o_data_46;
output signed [16+7:0] o_data_54;
output signed [16+7:0] o_data_61;
output signed [16+7:0] o_data_67;
output signed [16+7:0] o_data_73;
output signed [16+7:0] o_data_78;
output signed [16+7:0] o_data_82;
output signed [16+7:0] o_data_85;
output signed [16+7:0] o_data_88;
output signed [16+7:0] o_data_90;
// ********************************************
//
// WIRE DECLARATION
//
// ********************************************
wire signed [23:0] w1,
w32,
w31,
w8,
w23,
w4,
w27,
w39,
w62,
w61,
w9,
w2,
w11,
w13,
w18,
w19,
w41,
w36,
w45,
w67,
w64,
w73,
w16,
w17,
w68,
w85,
w22,
w38,
w46,
w54,
w78,
w82,
w88,
w90;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign w1 = i_data;
assign w32 = w1 << 5;
assign w31 = w32 - w1;
assign w8 = w1 << 3;
assign w23 = w31 - w8;
assign w4 = w1 << 2;
assign w27 = w31 - w4;
assign w39 = w31 + w8;
assign w62 = w31 << 1;
assign w61 = w62 - w1;
assign w9 = w1 + w8;
assign w2 = w1 << 1;
assign w11 = w9 + w2;
assign w13 = w9 + w4;
assign w18 = w9 << 1;
assign w19 = w1 + w18;
assign w41 = w9 + w32;
assign w36 = w9 << 2;
assign w45 = w9 + w36;
assign w67 = w31 + w36;
assign w64 = w1 << 6;
assign w73 = w9 + w64;
assign w16 = w1 << 4;
assign w17 = w1 + w16;
assign w68 = w17 << 2;
assign w85 = w17 + w68;
assign w22 = w11 << 1;
assign w38 = w19 << 1;
assign w46 = w23 << 1;
assign w54 = w27 << 1;
assign w78 = w39 << 1;
assign w82 = w41 << 1;
assign w88 = w11 << 3;
assign w90 = w45 << 1;
assign o_data_4= w4;
assign o_data_13=w13;
assign o_data_22=w22;
assign o_data_31=w31;
assign o_data_38=w38;
assign o_data_46=w46;
assign o_data_54=w54;
assign o_data_61=w61;
assign o_data_67=w67;
assign o_data_73=w73;
assign o_data_78=w78;
assign o_data_82=w82;
assign o_data_85=w85;
assign o_data_88=w88;
assign o_data_90=w90;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRTN_PP_SYMBOL_V
`define SKY130_FD_SC_LS__DLRTN_PP_SYMBOL_V
/**
* dlrtn: Delay latch, inverted reset, inverted enable, single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlrtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE_N ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRTN_PP_SYMBOL_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 27 19:26:50 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/ov7670_passthrough/ov7670_passthrough.srcs/sources_1/bd/system/ip/system_inverter_0_0/system_inverter_0_0_stub.v
// Design : system_inverter_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "inverter,Vivado 2016.4" *)
module system_inverter_0_0(x, x_not)
/* synthesis syn_black_box black_box_pad_pin="x,x_not" */;
input x;
output x_not;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Jeremy Bennett.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [19:10] bitout;
wire [29:24] short_bitout;
wire [7:0] allbits;
wire [15:0] twobits;
sub
i_sub1 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout (bitout[17:14])),
i_sub2 [3:0] (.allbits (allbits),
.twobits (twobits[7:0]),
.bitout (bitout[13:10]));
sub
i_sub3 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout (bitout[17:14]));
sub
i_sub4 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout (short_bitout[27:24]));
sub
i_sub5 [7:0] (.allbits (allbits),
.twobits (twobits),
.bitout (bitout[17:10]));
sub
i_sub6 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout ({bitout[18+:2],short_bitout[28+:2]}));
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Signals under test
assign allbits = crc[7:0];
assign twobits = crc[15:0];
wire [63:0] result = {48'h0, short_bitout, bitout};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'ha1da9ff8082a4ff6
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule // t
module sub
( input wire [7:0] allbits,
input wire [1:0] twobits,
output wire bitout);
assign bitout = (^ twobits) ^ (^ allbits);
endmodule // sub
|
`timescale 1ns / 1ps
module M_uxa_mgia(
input CLK_I_50MHZ,
input RST_I,
output CLK_O_25MHZ,
output HSYNC_O,
output VSYNC_O,
output [2:0] RED_O,
output [2:0] GRN_O,
output [2:1] BLU_O,
output [13:1] MGIA_ADR_O,
input [15:0] MGIA_DAT_I,
output MGIA_CYC_O,
output MGIA_STB_O,
input MGIA_ACK_I
);
wire pen;
wire clk25mhz;
wire vga_refresh;
wire vga_fetch;
wire odd_line;
wire [ 5:0] sh_adr;
wire [15:0] sh_dat;
wire [ 5:0] vfb_ctr;
wire [15:0] vfb_dat;
wire vfb_we;
assign unused = 12'h000; // drive unused outputs on Nexys2 board
assign RED_O = {3{pen}};
assign GRN_O = {3{pen}};
assign BLU_O = {2{pen}};
assign CLK_O_25MHZ = clk25mhz;
TIMEBASE tb(
.RST_I(RST_I),
.CLK_I_50MHZ(CLK_I_50MHZ),
.CLK_O_25MHZ(clk25mhz),
.HSYNC_O(HSYNC_O),
.VSYNC_O(VSYNC_O),
.VFEN_O(vga_fetch),
.VREN_O(vga_refresh),
.ODD_O(odd_line)
);
LINE_BUFFERS lb(
.CLK_I(clk25mhz),
.ODD_I(odd_line),
.F_ADR_I(sh_adr),
.F_DAT_O(sh_dat),
.S_ADR_I(vfb_ctr),
.S_DAT_I(vfb_dat),
.S_WE_I(vfb_we)
);
SHIFTER sh(
.CLK_I_25MHZ(clk25mhz),
.VREN_I(vga_refresh & !odd_line),
.F_ADR_O(sh_adr),
.F_DAT_I(sh_dat),
.PEN_O(pen)
);
VIDEO_FETCHER vf(
.RST_I(RST_I),
.CLK_I_25MHZ(clk25mhz),
.VSYNC_I(VSYNC_O),
.VFEN_I(vga_fetch & odd_line),
.RAM_ADR_O(MGIA_ADR_O),
.RAM_CYC_O(MGIA_CYC_O),
.RAM_STB_O(MGIA_STB_O),
.RAM_ACK_I(MGIA_ACK_I),
.RAM_DAT_I(MGIA_DAT_I),
.LB_ADR_O(vfb_ctr),
.LB_DAT_O(vfb_dat),
.LB_WE_O(vfb_we)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVGNDNOVPB_TB_V
`define SKY130_FD_SC_LS__TAPVGNDNOVPB_TB_V
/**
* tapvgndnovpb: Substrate only tap cell.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__tapvgndnovpb.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_ls__tapvgndnovpb dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVGNDNOVPB_TB_V
|
// file: Master_Clock_Divider.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1____50.000______0.000______50.0______129.198_____89.971
// clk_out2___100.000______0.000______50.0______112.316_____89.971
// clk_out3___200.000______0.000______50.0_______98.146_____89.971
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________200.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "Master_Clock_Divider,clk_wiz_v5_3_2_0,{component_name=Master_Clock_Divider,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=3,clkin1_period=5.0,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module Master_Clock_Divider
(
// Clock out ports
output clk_out1,
output clk_out2,
output clk_out3,
// Status and control signals
input reset,
output locked,
// Clock in ports
input clk_in1_p,
input clk_in1_n
);
Master_Clock_Divider_clk_wiz inst
(
// Clock out ports
.clk_out1(clk_out1),
.clk_out2(clk_out2),
.clk_out3(clk_out3),
// Status and control signals
.reset(reset),
.locked(locked),
// Clock in ports
.clk_in1_p(clk_in1_p),
.clk_in1_n(clk_in1_n)
);
endmodule
|
`timescale 1ns /1ps
module add3 ( o, a, b );
output [15:0] o;
input [15:0] a;
input [15:0] b;
wire n1, n2, n3, n4, n5, n6, n7,
n8, n9, n10, n11, n12, n13,
n14, n15, n16, n17, n18, n19,
n20, n21, n22, n23, n24, n25,
n26, n27, n28, n29, n30, n31,
n32, n33, n34, n35, n36, n37,
n38, n39, n40, n41, n42, n43,
n44, n45, n46, n47, n48, n49,
n50, n51, n52, n53, n54, n55,
n56, n57, n58, n59, n60, n61,
n62, n63, n64, n65, n66, n67,
n68, n69, n70, n71, n72, n73,
n74, n75, n76, n77, n78, n79,
n80, n81, n82, n83, n84, n85,
n86, n87, n88, n89, n90, n91,
n92, n93, n94, n95, n96, n97,
n98, n99, n100, n101, n102, n103,
n104, n105, n106, n107, n108,
n109, n110, n111, n112, n113,
n114, n115, n116, n117, n118,
n119, n120, n121, n122, n123,
n124, n125, n126, n127, n128,
n129, n130, n131, n132, n133,
n134, n135, n136, n137, n138,
n139, n140, n141, n142, n143,
n144, n145, n146, n147, n148,
n149, n150, n151, n152, n153,
n154, n155, n156, n157, n158,
n159, n160, n161, n162, n163,
n164;
not #(1.000) U4 ( n60, n160 );
nor #(1.000) U5 ( n160, n161, n162 );
not #(1.000) U6 ( n52, n156 );
not #(1.000) U7 ( n45, n152 );
not #(1.000) U8 ( n38, n148 );
not #(1.000) U9 ( n31, n144 );
not #(1.000) U10 ( n24, n140 );
not #(1.000) U11 ( n17, n136 );
not #(1.000) U12 ( n10, n132 );
not #(1.000) U13 ( n109, n107 );
not #(1.000) U14 ( n98, n96 );
not #(1.000) U15 ( n87, n85 );
not #(1.000) U16 ( n73, n71 );
not #(1.000) U17 ( n120, n118 );
nor #(1.000) U18 ( o[2], n50, n51 );
and #(1.000) U19 ( n51, n52, n53 );
nor #(1.000) U20 ( n50, n52, n53 );
nand #(1.000) U21 ( n53, n54, n55 );
nor #(1.000) U22 ( o[3], n43, n44 );
and #(1.000) U23 ( n44, n45, n46 );
nor #(1.000) U24 ( n43, n45, n46 );
nand #(1.000) U25 ( n46, n47, n48 );
nor #(1.000) U26 ( o[4], n36, n37 );
and #(1.000) U27 ( n37, n38, n39 );
nor #(1.000) U28 ( n36, n38, n39 );
nand #(1.000) U29 ( n39, n40, n41 );
nor #(1.000) U30 ( o[5], n29, n30 );
and #(1.000) U31 ( n30, n31, n32 );
nor #(1.000) U32 ( n29, n31, n32 );
nand #(1.000) U33 ( n32, n33, n34 );
nor #(1.000) U34 ( o[6], n22, n23 );
and #(1.000) U35 ( n23, n24, n25 );
nor #(1.000) U36 ( n22, n24, n25 );
nand #(1.000) U37 ( n25, n26, n27 );
nor #(1.000) U38 ( o[7], n15, n16 );
and #(1.000) U39 ( n16, n17, n18 );
nor #(1.000) U40 ( n15, n17, n18 );
nand #(1.000) U41 ( n18, n19, n20 );
nor #(1.000) U42 ( o[8], n8, n9 );
and #(1.000) U43 ( n9, n10, n11 );
nor #(1.000) U44 ( n8, n10, n11 );
nand #(1.000) U45 ( n11, n12, n13 );
nor #(1.000) U46 ( o[9], n1, n2 );
and #(1.000) U47 ( n2, n3, n4 );
nor #(1.000) U48 ( n1, n3, n4 );
nand #(1.000) U49 ( n4, n5, n6 );
nor #(1.000) U50 ( o[10], n121, n122 );
and #(1.000) U51 ( n122, n120, n123 );
nor #(1.000) U52 ( n121, n120, n123 );
nand #(1.000) U53 ( n123, n124, n125 );
nor #(1.000) U54 ( o[11], n110, n111 );
and #(1.000) U55 ( n111, n109, n112 );
nor #(1.000) U56 ( n110, n109, n112 );
nand #(1.000) U57 ( n112, n113, n114 );
nor #(1.000) U58 ( o[12], n99, n100 );
and #(1.000) U59 ( n100, n98, n101 );
nor #(1.000) U60 ( n99, n98, n101 );
nand #(1.000) U61 ( n101, n102, n103 );
nor #(1.000) U62 ( o[13], n88, n89 );
and #(1.000) U63 ( n89, n87, n90 );
nor #(1.000) U64 ( n88, n87, n90 );
nand #(1.000) U65 ( n90, n91, n92 );
nor #(1.000) U66 ( o[14], n77, n78 );
and #(1.000) U67 ( n78, n73, n79 );
nor #(1.000) U68 ( n77, n73, n79 );
nand #(1.000) U69 ( n79, n80, n81 );
nor #(1.000) U70 ( o[15], n64, n65 );
and #(1.000) U71 ( n65, n66, n67 );
nor #(1.000) U72 ( n64, n67, n66 );
nand #(1.000) U73 ( n66, n68, n69 );
nand #(1.000) U74 ( o[1], n57, n58 );
or #(1.000) U75 ( n58, n59, n60 );
nand #(1.000) U76 ( n57, n59, n60 );
nand #(1.000) U77 ( n59, n61, n62 );
nand #(1.000) U78 ( n3, n129, n130 );
nand #(1.000) U79 ( n129, a[8], n10 );
nand #(1.000) U80 ( n130, b[8], n131 );
nand #(1.000) U81 ( n131, n132, n14 );
and #(1.000) U82 ( n156, n157, n158 );
nand #(1.000) U83 ( n158, b[1], n159 );
nand #(1.000) U84 ( n157, a[1], n160 );
nand #(1.000) U85 ( n159, n63, n60 );
and #(1.000) U86 ( n152, n153, n154 );
nand #(1.000) U87 ( n153, a[2], n52 );
nand #(1.000) U88 ( n154, b[2], n155 );
nand #(1.000) U89 ( n155, n156, n56 );
and #(1.000) U90 ( n148, n149, n150 );
nand #(1.000) U91 ( n149, a[3], n45 );
nand #(1.000) U92 ( n150, b[3], n151 );
nand #(1.000) U93 ( n151, n152, n49 );
and #(1.000) U94 ( n144, n145, n146 );
nand #(1.000) U95 ( n145, a[4], n38 );
nand #(1.000) U96 ( n146, b[4], n147 );
nand #(1.000) U97 ( n147, n148, n42 );
and #(1.000) U98 ( n107, n115, n116 );
nand #(1.000) U99 ( n115, a[10], n120 );
nand #(1.000) U100 ( n116, b[10], n117 );
nand #(1.000) U101 ( n117, n118, n119 );
and #(1.000) U102 ( n140, n141, n142 );
nand #(1.000) U103 ( n141, a[5], n31 );
nand #(1.000) U104 ( n142, b[5], n143 );
nand #(1.000) U105 ( n143, n144, n35 );
and #(1.000) U106 ( n96, n104, n105 );
nand #(1.000) U107 ( n104, a[11], n109 );
nand #(1.000) U108 ( n105, b[11], n106 );
nand #(1.000) U109 ( n106, n107, n108 );
and #(1.000) U110 ( n136, n137, n138 );
nand #(1.000) U111 ( n137, a[6], n24 );
nand #(1.000) U112 ( n138, b[6], n139 );
nand #(1.000) U113 ( n139, n140, n28 );
and #(1.000) U114 ( n85, n93, n94 );
nand #(1.000) U115 ( n93, a[12], n98 );
nand #(1.000) U116 ( n94, b[12], n95 );
nand #(1.000) U117 ( n95, n96, n97 );
and #(1.000) U118 ( n132, n133, n134 );
nand #(1.000) U119 ( n133, a[7], n17 );
nand #(1.000) U120 ( n134, b[7], n135 );
nand #(1.000) U121 ( n135, n136, n21 );
and #(1.000) U122 ( n71, n82, n83 );
nand #(1.000) U123 ( n82, a[13], n87 );
nand #(1.000) U124 ( n83, b[13], n84 );
nand #(1.000) U125 ( n84, n85, n86 );
and #(1.000) U126 ( n118, n126, n127 );
nand #(1.000) U127 ( n127, b[9], n128 );
nand #(1.000) U128 ( n126, a[9], n3 );
or #(1.000) U129 ( n128, n3, a[9] );
nand #(1.000) U130 ( n67, n74, n75 );
or #(1.000) U131 ( n74, n76, b[15] );
nand #(1.000) U132 ( n75, b[15], n76 );
not #(1.000) U133 ( n76, a[15] );
nand #(1.000) U134 ( n55, b[2], n56 );
nand #(1.000) U135 ( n48, b[3], n49 );
nand #(1.000) U136 ( n41, b[4], n42 );
nand #(1.000) U137 ( n34, b[5], n35 );
nand #(1.000) U138 ( n27, b[6], n28 );
nand #(1.000) U139 ( n20, b[7], n21 );
nand #(1.000) U140 ( n13, b[8], n14 );
nand #(1.000) U141 ( n125, b[10], n119 );
nand #(1.000) U142 ( n114, b[11], n108 );
nand #(1.000) U143 ( n103, b[12], n97 );
nand #(1.000) U144 ( n92, b[13], n86 );
nand #(1.000) U145 ( n81, b[14], n72 );
nand #(1.000) U146 ( n62, b[1], n63 );
nand #(1.000) U147 ( n69, b[14], n70 );
nand #(1.000) U148 ( n70, n71, n72 );
nand #(1.000) U149 ( n68, a[14], n73 );
not #(1.000) U150 ( n56, a[2] );
not #(1.000) U151 ( n49, a[3] );
not #(1.000) U152 ( n42, a[4] );
not #(1.000) U153 ( n35, a[5] );
not #(1.000) U154 ( n28, a[6] );
not #(1.000) U155 ( n21, a[7] );
not #(1.000) U156 ( n14, a[8] );
not #(1.000) U157 ( n119, a[10] );
not #(1.000) U158 ( n108, a[11] );
not #(1.000) U159 ( n97, a[12] );
not #(1.000) U160 ( n86, a[13] );
not #(1.000) U161 ( n72, a[14] );
nand #(1.000) U162 ( n6, b[9], n7 );
not #(1.000) U163 ( n63, a[1] );
not #(1.000) U164 ( n161, b[0] );
not #(1.000) U165 ( n162, a[0] );
nand #(1.000) U166 ( o[0], n163, n164 );
nand #(1.000) U167 ( n163, a[0], n161 );
nand #(1.000) U168 ( n164, b[0], n162 );
or #(1.000) U169 ( n61, n63, b[1] );
or #(1.000) U170 ( n54, n56, b[2] );
or #(1.000) U171 ( n47, n49, b[3] );
or #(1.000) U172 ( n40, n42, b[4] );
or #(1.000) U173 ( n33, n35, b[5] );
or #(1.000) U174 ( n26, n28, b[6] );
or #(1.000) U175 ( n19, n21, b[7] );
or #(1.000) U176 ( n12, n14, b[8] );
or #(1.000) U177 ( n5, n7, b[9] );
or #(1.000) U178 ( n124, n119, b[10] );
or #(1.000) U179 ( n113, n108, b[11] );
or #(1.000) U180 ( n102, n97, b[12] );
or #(1.000) U181 ( n91, n86, b[13] );
or #(1.000) U182 ( n80, n72, b[14] );
not #(1.000) U183 ( n7, a[9] );
endmodule
|
`timescale 1 ps / 1 ps
module onetswitch_top(
inout [14:0] DDR_addr,
inout [2:0] DDR_ba,
inout DDR_cas_n,
inout DDR_ck_n,
inout DDR_ck_p,
inout DDR_cke,
inout DDR_cs_n,
inout [3:0] DDR_dm,
inout [31:0] DDR_dq,
inout [3:0] DDR_dqs_n,
inout [3:0] DDR_dqs_p,
inout DDR_odt,
inout DDR_ras_n,
inout DDR_reset_n,
inout DDR_we_n,
inout FIXED_IO_ddr_vrn,
inout FIXED_IO_ddr_vrp,
inout [53:0] FIXED_IO_mio,
inout FIXED_IO_ps_clk,
inout FIXED_IO_ps_porb,
inout FIXED_IO_ps_srstb,
input rgmii_0_rxc ,
output rgmii_0_txc ,
output rgmii_0_tx_en ,
output [3:0] rgmii_0_txd ,
input rgmii_0_rx_dv ,
input [3:0] rgmii_0_rxd ,
input rgmii_1_rxc ,
output rgmii_1_txc ,
output rgmii_1_tx_en ,
output [3:0] rgmii_1_txd ,
input rgmii_1_rx_dv ,
input [3:0] rgmii_1_rxd ,
input rgmii_2_rxc ,
output rgmii_2_txc ,
output rgmii_2_tx_en ,
output [3:0] rgmii_2_txd ,
input rgmii_2_rx_dv ,
input [3:0] rgmii_2_rxd ,
input rgmii_3_rxc ,
output rgmii_3_txc ,
output rgmii_3_tx_en ,
output [3:0] rgmii_3_txd ,
input rgmii_3_rx_dv ,
input [3:0] rgmii_3_rxd ,
inout rgmii_0_mdio ,
output rgmii_0_mdc ,
inout rgmii_1_mdio ,
output rgmii_1_mdc ,
inout rgmii_2_mdio ,
output rgmii_2_mdc ,
inout rgmii_3_mdio ,
output rgmii_3_mdc ,
input rgmii_phy_int ,
output rgmii_phy_rstn ,
output [1:0] pl_led ,
output [1:0] pl_pmod
);
wire bd_fclk0_125m ;
wire bd_fclk1_75m ;
wire bd_fclk2_200m ;
reg [23:0] cnt_0;
reg [23:0] cnt_1;
reg [23:0] cnt_2;
reg [23:0] cnt_3;
always @(posedge bd_fclk0_125m) begin
cnt_0 <= cnt_0 + 1'b1;
end
always @(posedge bd_fclk1_75m) begin
cnt_1 <= cnt_1 + 1'b1;
end
always @(posedge bd_fclk2_200m) begin
cnt_2 <= cnt_2 + 1'b1;
end
always @(posedge bd_fclk2_200m) begin
cnt_3 <= cnt_3 + 1'b1;
end
assign pl_led[0] = cnt_0[23];
assign pl_led[1] = cnt_1[23];
assign pl_pmod[0] = cnt_2[23];
assign pl_pmod[1] = cnt_3[23];
onets_bd_wrapper i_onets_bd_wrapper(
.DDR_addr (DDR_addr),
.DDR_ba (DDR_ba),
.DDR_cas_n (DDR_cas_n),
.DDR_ck_n (DDR_ck_n),
.DDR_ck_p (DDR_ck_p),
.DDR_cke (DDR_cke),
.DDR_cs_n (DDR_cs_n),
.DDR_dm (DDR_dm),
.DDR_dq (DDR_dq),
.DDR_dqs_n (DDR_dqs_n),
.DDR_dqs_p (DDR_dqs_p),
.DDR_odt (DDR_odt),
.DDR_ras_n (DDR_ras_n),
.DDR_reset_n (DDR_reset_n),
.DDR_we_n (DDR_we_n),
.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
.FIXED_IO_mio (FIXED_IO_mio),
.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
.bd_fclk0_125m ( bd_fclk0_125m ),
.bd_fclk1_75m ( bd_fclk1_75m ),
.bd_fclk2_200m ( bd_fclk2_200m ),
.ext_rst (1'b1),
.mdio_0_io ( rgmii_0_mdio ),
.mdio_0_mdc ( rgmii_0_mdc ),
.mdio_1_io ( rgmii_1_mdio ),
.mdio_1_mdc ( rgmii_1_mdc ),
.mdio_2_io ( rgmii_2_mdio ),
.mdio_2_mdc ( rgmii_2_mdc ),
.mdio_3_io ( rgmii_3_mdio ),
.mdio_3_mdc ( rgmii_3_mdc ),
.phy_rst_n_0 ( rgmii_phy_rstn ),
.phy_rst_n_1 ( ),
.phy_rst_n_2 ( ),
.phy_rst_n_3 ( ),
.rgmii_0_rd ( rgmii_0_rxd ),
.rgmii_0_rx_ctl ( rgmii_0_rx_dv ),
.rgmii_0_rxc ( rgmii_0_rxc ),
.rgmii_0_td ( rgmii_0_txd ),
.rgmii_0_tx_ctl ( rgmii_0_tx_en ),
.rgmii_0_txc ( rgmii_0_txc ),
.rgmii_1_rd ( rgmii_1_rxd ),
.rgmii_1_rx_ctl ( rgmii_1_rx_dv ),
.rgmii_1_rxc ( rgmii_1_rxc ),
.rgmii_1_td ( rgmii_1_txd ),
.rgmii_1_tx_ctl ( rgmii_1_tx_en ),
.rgmii_1_txc ( rgmii_1_txc ),
.rgmii_2_rd ( rgmii_2_rxd ),
.rgmii_2_rx_ctl ( rgmii_2_rx_dv ),
.rgmii_2_rxc ( rgmii_2_rxc ),
.rgmii_2_td ( rgmii_2_txd ),
.rgmii_2_tx_ctl ( rgmii_2_tx_en ),
.rgmii_2_txc ( rgmii_2_txc ),
.rgmii_3_rd ( rgmii_3_rxd ),
.rgmii_3_rx_ctl ( rgmii_3_rx_dv ),
.rgmii_3_rxc ( rgmii_3_rxc ),
.rgmii_3_td ( rgmii_3_txd ),
.rgmii_3_tx_ctl ( rgmii_3_tx_en ),
.rgmii_3_txc ( rgmii_3_txc )
);
endmodule |
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: SDRAM_clock.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module SDRAM_clock (
areset,
inclk0,
c0,
locked);
input areset;
input inclk0;
output c0;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [4:0] sub_wire1;
wire [0:0] sub_wire5 = 1'h0;
wire locked = sub_wire0;
wire [0:0] sub_wire2 = sub_wire1[0:0];
wire c0 = sub_wire2;
wire sub_wire3 = inclk0;
wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
altpll altpll_component (
.areset (areset),
.inclk (sub_wire4),
.locked (sub_wire0),
.clk (sub_wire1),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 25,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 83,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=SDRAM_clock",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "166.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "166.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "SDRAM_clock.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "25"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "83"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL SDRAM_clock.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL SDRAM_clock.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL SDRAM_clock.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SDRAM_clock.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SDRAM_clock.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SDRAM_clock_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL SDRAM_clock_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
//
// Tawas Load/Store:
//
// Perform load/store operations between the data bus and register file.
//
module tawas_ls
(
input clk,
input rst,
input [31:0] reg0,
input [31:0] reg1,
input [31:0] reg2,
input [31:0] reg3,
input [31:0] reg4,
input [31:0] reg5,
input [31:0] reg6,
input [31:0] reg7,
input ls_dir_en,
input ls_dir_store,
input [2:0] ls_dir_reg,
input [31:0] ls_dir_addr,
input ls_op_en,
input [14:0] ls_op,
output reg dcs,
output reg dwr,
output reg [31:0] daddr,
output reg [3:0] dmask,
output reg [31:0] dout,
input [31:0] din,
output reg rcn_cs,
output reg rcn_xch,
output reg rcn_wr,
output reg [31:0] rcn_addr,
output reg [2:0] rcn_wbreg,
output reg [3:0] rcn_mask,
output reg [31:0] rcn_wdata,
output wb_ptr_en,
output [2:0] wb_ptr_reg,
output [31:0] wb_ptr_data,
output wb_store_en,
output [2:0] wb_store_reg,
output [31:0] wb_store_data
);
//
// Decode
//
wire ls_op_st = ls_op[14];
wire ls_op_post_inc = ls_op[13];
wire [1:0] ls_op_type = ls_op[12:11];
wire [4:0] ls_op_off = ls_op[10:6];
wire [2:0] ls_op_ptr = ls_op[5:3];
wire [2:0] ls_op_reg = ls_op[2:0];
wire wren = (ls_dir_en) ? ls_dir_store : ls_op_st;
wire xchange = (ls_dir_en || !wren) ? 1'b0 : (ls_op_type == 2'b11);
wire [2:0] wbreg = (ls_dir_en) ? ls_dir_reg : ls_op_reg;
//
// Bus address
//
reg [31:0] addr;
reg [31:0] addr_inc;
wire [31:0] bus_addr = (ls_dir_en || ls_op_post_inc) ? addr : addr_inc;
wire data_bus_en = (ls_dir_en || ls_op_en) && (!bus_addr[31]);
wire rcn_bus_en = (ls_dir_en || ls_op_en) && (bus_addr[31]);
always @ *
if (ls_dir_en)
begin
addr = ls_dir_addr;
addr_inc = 32'd0;
end
else
begin
case (ls_op_ptr)
3'd0: addr = reg0;
3'd1: addr = reg1;
3'd2: addr = reg2;
3'd3: addr = reg3;
3'd4: addr = reg4;
3'd5: addr = reg5;
3'd6: addr = reg6;
default: addr = reg7;
endcase
case (ls_op_type)
2'd0: addr = addr;
2'd1: addr = addr & 32'hFFFFFFFE;
default: addr = addr & 32'hFFFFFFFC;
endcase
case (ls_op_type)
2'd0: addr_inc = addr + {{27{ls_op_off[4]}}, ls_op_off};
2'd1: addr_inc = addr + {{26{ls_op_off[4]}}, ls_op_off, 1'b0};
default: addr_inc = addr + {{25{ls_op_off[4]}}, ls_op_off, 2'd0};
endcase
end
//
// Data/Mask
//
reg [31:0] wdata;
reg [3:0] wmask;
always @ *
if (ls_dir_en)
begin
case (ls_dir_reg)
3'd0: wdata = reg0;
3'd1: wdata = reg1;
3'd2: wdata = reg2;
3'd3: wdata = reg3;
3'd4: wdata = reg4;
3'd5: wdata = reg5;
3'd6: wdata = reg6;
default: wdata = reg7;
endcase
wmask = 4'hF;
end
else
begin
case (ls_op_reg)
3'd0: wdata = reg0;
3'd1: wdata = reg1;
3'd2: wdata = reg2;
3'd3: wdata = reg3;
3'd4: wdata = reg4;
3'd5: wdata = reg5;
3'd6: wdata = reg6;
default: wdata = reg7;
endcase
case (ls_op_type)
2'd0:
begin
wdata = {4{wdata[7:0]}};
case (bus_addr[1:0])
2'd0: wmask = 4'b0001;
2'd1: wmask = 4'b0010;
2'd2: wmask = 4'b0100;
default: wmask = 4'b1000;
endcase
end
2'd1:
begin
wdata = {2{wdata[15:0]}};
if (!bus_addr[1])
wmask = 4'b0011;
else
wmask = 4'b1100;
end
default: wmask = 4'hF;
endcase
end
//
// Issue bus transaction
//
always @ (posedge clk or posedge rst)
if (rst)
begin
dcs <= 1'b0;
rcn_cs <= 1'b0;
end
else
begin
dcs <= data_bus_en;
rcn_cs <= rcn_bus_en;
end
always @ (posedge clk)
if (data_bus_en)
begin
dwr <= wren;
daddr <= bus_addr;
dmask <= wmask;
dout <= wdata;
end
always @ (posedge clk)
if (rcn_bus_en)
begin
rcn_xch <= xchange;
rcn_wr <= wren;
rcn_addr <= bus_addr;
rcn_wbreg <= wbreg;
rcn_mask <= wmask;
rcn_wdata <= wdata;
end
//
// Retire data bus reads
//
reg ld_d1;
reg ld_d2;
reg ld_d3;
reg wbptr_d1;
reg wbptr_d2;
reg wbptr_d3;
always @ (posedge clk or posedge rst)
if (rst)
begin
ld_d1 <= 1'b0;
ld_d2 <= 1'b0;
ld_d3 <= 1'b0;
wbptr_d1 <= 1'b0;
wbptr_d2 <= 1'b0;
wbptr_d3 <= 1'b0;
end
else
begin
ld_d1 <= data_bus_en && (!wren || xchange);
ld_d2 <= ld_d1;
ld_d3 <= ld_d2;
wbptr_d1 <= ls_op_en && ls_op_post_inc;
wbptr_d2 <= wbptr_d1;
wbptr_d3 <= wbptr_d2;
end
reg [2:0] wbreg_d1;
reg [2:0] wbreg_d2;
reg [2:0] wbreg_d3;
reg [3:0] wmask_d1;
reg [3:0] wmask_d2;
reg [3:0] wmask_d3;
reg [31:0] data_in;
reg [2:0] wbptr_reg_d1;
reg [2:0] wbptr_reg_d2;
reg [2:0] wbptr_reg_d3;
reg [31:0] wbptr_addr_d1;
reg [31:0] wbptr_addr_d2;
reg [31:0] wbptr_addr_d3;
always @ (posedge clk)
begin
wbreg_d1 <= wbreg;
wbreg_d2 <= wbreg_d1;
wbreg_d3 <= wbreg_d2;
wmask_d1 <= wmask;
wmask_d2 <= wmask_d1;
wmask_d3 <= wmask_d2;
data_in <= din;
wbptr_reg_d1 <= ls_op_ptr;
wbptr_reg_d2 <= wbptr_reg_d1;
wbptr_reg_d3 <= wbptr_reg_d2;
wbptr_addr_d1 <= addr_inc;
wbptr_addr_d2 <= wbptr_addr_d1;
wbptr_addr_d3 <= wbptr_addr_d2;
end
reg [31:0] data_in_final;
always @ *
if (wmask_d3 == 4'b1111)
data_in_final = data_in;
else if (wmask_d3[1:0] == 2'b11)
data_in_final = {16'd0, data_in[15:0]};
else if (wmask_d3[3:2] == 2'b11)
data_in_final = {16'd0, data_in[31:16]};
else if (wmask_d3[0])
data_in_final = {24'd0, data_in[7:0]};
else if (wmask_d3[1])
data_in_final = {24'd0, data_in[15:8]};
else if (wmask_d3[2])
data_in_final = {24'd0, data_in[23:16]};
else
data_in_final = {24'd0, data_in[31:24]};
assign wb_ptr_en = wbptr_d3;
assign wb_ptr_reg = wbptr_reg_d3;
assign wb_ptr_data = wbptr_addr_d3;
assign wb_store_en = ld_d3;
assign wb_store_reg = wbreg_d3;
assign wb_store_data = data_in_final;
endmodule
|
`default_nettype none
module simple_ddr3(
input wire clk, // clk491520
input wire rst,
input wire [27:0] addr_i,
input wire [31:0] data_i,
input wire we_i,
input wire pop_i,
output wire [31:0] data_o,
output wire ack_o,
output wire busy_o,
// MIG interface
output wire mig_cmd_clk,
output wire mig_cmd_en,
output wire [2:0] mig_cmd_instr,
output wire [5:0] mig_cmd_bl,
output wire [29:0] mig_cmd_byte_addr,
input wire mig_cmd_empty,
input wire mig_cmd_full,
output wire mig_wr_clk,
output wire mig_wr_en,
output wire [3:0] mig_wr_mask,
output wire [31:0] mig_wr_data,
input wire mig_wr_full,
input wire mig_wr_empty,
input wire [6:0] mig_wr_count,
input wire mig_wr_underrun,
input wire mig_wr_error,
output wire mig_rd_clk,
output wire mig_rd_en,
input wire [31:0] mig_rd_data,
input wire mig_rd_full,
input wire mig_rd_empty,
input wire [6:0] mig_rd_count,
input wire mig_rd_overflow,
input wire mig_rd_error);
reg [27:0] addr_ff;
reg [31:0] wdata_ff;
reg [31:0] rdata_ff;
reg ack_ff;
reg [5:0] state_ff;
localparam ST_INIT = 1;
localparam ST_FILL_WRBUF = 2;
localparam ST_EMIT_WR_CMD = 3;
localparam ST_EMIT_RD_CMD = 4;
localparam ST_WAIT_RD_DATA = 5;
always @(posedge clk) begin
if (rst) begin
addr_ff <= 28'b0;
wdata_ff <= 32'b0;
rdata_ff <= 32'b0;
state_ff <= ST_INIT;
ack_ff <= 1'b0;
end else begin
case (state_ff)
ST_INIT: begin
addr_ff <= addr_i;
wdata_ff <= data_i;
ack_ff <= 1'b0;
if (we_i) begin
state_ff <= ST_FILL_WRBUF;
end else if (pop_i) begin
state_ff <= ST_EMIT_RD_CMD;
end else begin
state_ff <= ST_INIT;
end
end
ST_FILL_WRBUF: begin
state_ff <= ST_EMIT_WR_CMD;
ack_ff <= 1'b0;
end
ST_EMIT_WR_CMD: begin
state_ff <= ST_INIT;
ack_ff <= 1'b0;
end
ST_EMIT_RD_CMD: begin
state_ff <= ST_WAIT_RD_DATA;
ack_ff <= 1'b0;
end
ST_WAIT_RD_DATA: begin
if (mig_rd_count == 6'h00) begin // FIXME: mig_rd_empty?
state_ff <= ST_WAIT_RD_DATA;
ack_ff <= 1'b0;
end else begin
rdata_ff <= mig_rd_data;
state_ff <= ST_INIT;
ack_ff <= 1'b1;
end
end
endcase
end
end
assign mig_cmd_clk = clk;
assign mig_cmd_en = (state_ff == ST_EMIT_RD_CMD || state_ff == ST_EMIT_WR_CMD) ? 1'b1 : 1'b0;
assign mig_cmd_instr = (state_ff == ST_EMIT_RD_CMD) ? 3'b001 : 3'b010;
assign mig_cmd_bl = 6'b0;
assign mig_cmd_byte_addr[29:0] = {addr_ff, 2'b00};
// FIXME: wait until mig_cmd_empty or !mig_cmd_full?
assign mig_wr_clk = clk;
assign mig_wr_en = (state_ff == ST_FILL_WRBUF) ? 1'b1 : 1'b0;
assign mig_wr_mask = 4'b0000;
assign mig_wr_data = wdata_ff;
// mig_wr_full, mig_wr_empty, mig_wr_count, mig_wr_underrun, mig_wr_error
assign mig_rd_clk = clk;
assign mig_rd_en = (state_ff == ST_WAIT_RD_DATA) ? 1'b1 : 1'b0;
// mig_rd_full, mig_rd_empty, mig_rd_overflow, mig_rd_error
assign data_o = rdata_ff;
assign ack_o = ack_ff;
assign busy_o = (state_ff != ST_INIT) ? 1'b1 : 1'b0;
endmodule
`default_nettype wire
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ctu_test_stub_scan.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
//
// Cluster Name: CTU
//-----------------------------------------------------------------------------
`include "sys.h"
module ctu_test_stub_scan (/*AUTOARG*/
// Outputs
se, so_0,
// Inputs
global_shift_enable, ctu_tst_scan_disable,
//ctu_tst_scanmode,
ctu_tst_short_chain, long_chain_so_0, short_chain_so_0
);
input global_shift_enable;
input ctu_tst_scan_disable;
//input ctu_tst_scanmode;
input ctu_tst_short_chain;
input long_chain_so_0;
input short_chain_so_0;
output se;
output so_0;
//wire testmode_l;
wire short_chain_select;
assign se = ~ctu_tst_scan_disable & global_shift_enable;
//assign testmode_l = ~ctu_tst_scanmode;
assign short_chain_select = ctu_tst_short_chain;
assign so_0 = short_chain_select ? short_chain_so_0 : long_chain_so_0;
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Apr 09 08:27:08 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/ov7670_hessian_split/ov7670_hessian_split.srcs/sources_1/bd/system/ip/system_vga_color_test_0_0/system_vga_color_test_0_0_stub.v
// Design : system_vga_color_test_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "vga_color_test,Vivado 2016.4" *)
module system_vga_color_test_0_0(clk_25, xaddr, yaddr, rgb)
/* synthesis syn_black_box black_box_pad_pin="clk_25,xaddr[9:0],yaddr[9:0],rgb[23:0]" */;
input clk_25;
input [9:0]xaddr;
input [9:0]yaddr;
output [23:0]rgb;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLCLKP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__DLCLKP_BEHAVIORAL_PP_V
/**
* dlclkp: Clock gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_lp__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dlclkp (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire m0 ;
wire clkn ;
wire CLK_delayed ;
wire GATE_delayed;
reg notifier ;
// Name Output Other arguments
not not0 (clkn , CLK_delayed );
sky130_fd_sc_lp__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK , m0, CLK_delayed );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLCLKP_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A21O_FUNCTIONAL_V
`define SKY130_FD_SC_LP__A21O_FUNCTIONAL_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__a21o (
X ,
A1,
A2,
B1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X, and0_out, B1 );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A21O_FUNCTIONAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O32A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__O32A_BEHAVIORAL_PP_V
/**
* o32a: 3-input OR and 2-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o32a (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1, A3 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X , or0_out, or1_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O32A_BEHAVIORAL_PP_V |
// File: ROMParmLoadSync_TBV.v
// Generated by MyHDL 0.10
// Date: Tue Jun 26 23:46:29 2018
`timescale 1ns/10ps
module ROMParmLoadSync_TBV (
);
// Python Only Testbench for `ROMParmLoadSync`
reg [3:0] addr = 0;
reg [3:0] dout = 0;
reg clk = 0;
reg rst = 0;
always @(posedge clk) begin: ROMPARMLOADSYNC_TBV_ROMPARMLOADSYNC0_0_READACTION
if (rst) begin
dout <= 0;
end
else begin
case (addr)
0: dout <= 3;
1: dout <= 2;
2: dout <= 1;
default: dout <= 0;
endcase
end
end
initial begin: ROMPARMLOADSYNC_TBV_CLK_SIGNAL
while (1'b1) begin
clk <= (!clk);
# 1;
end
end
initial begin: ROMPARMLOADSYNC_TBV_STIMULES
integer i;
for (i=0; i<(3 + 1); i=i+1) begin
@(posedge clk);
addr <= i;
end
for (i=0; i<4; i=i+1) begin
@(posedge clk);
rst <= 1;
addr <= i;
end
$finish;
end
always @(posedge clk) begin: ROMPARMLOADSYNC_TBV_PRINT_DATA
$write("%h", addr);
$write(" ");
$write("%h", dout);
$write(" ");
$write("%h", rst);
$write("\n");
end
endmodule
|
module fsm ( clock, reset, req_0, req_1, gnt_0, gnt_1 );
input clock,reset,req_0,req_1;
output gnt_0,gnt_1;
wire clock,reset,req_0,req_1;
reg gnt_0,gnt_1;
parameter SIZE = 3;
parameter IDLE = 3'b001;
parameter GNT0 = 3'b010;
parameter GNT1 = 3'b100;
parameter GNT2 = 3'b101;
reg [SIZE-1:0] state;
reg [SIZE-1:0] next_state;
always @ (posedge clock)
begin : FSM
if (reset == 1'b1) begin
state <= #1 IDLE;
gnt_0 <= 0;
gnt_1 <= 0;
end
else
case(state)
IDLE : if (req_0 == 1'b1) begin
state <= #1 GNT0;
gnt_0 <= 1;
end else if (req_1 == 1'b1) begin
gnt_1 <= 1;
state <= #1 GNT0;
end else begin
state <= #1 IDLE;
end
GNT0 : if (req_0 == 1'b1) begin
state <= #1 GNT0;
end else begin
gnt_0 <= 0;
state <= #1 IDLE;
end
GNT1 : if (req_1 == 1'b1) begin
state <= #1 GNT2;
gnt_1 <= req_0;
end
GNT2 : if (req_0 == 1'b1) begin
state <= #1 GNT1;
gnt_1 <= req_1;
end
default : state <= #1 IDLE;
endcase
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2012-2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express
// File : pcie3_7x_0_pcie_bram_7vx_rep_8k.v
// Version : 3.0
//----------------------------------------------------------------------------//
// Project : Virtex-7 FPGA Gen3 Integrated Block for PCI Express //
// Filename : pcie3_7x_0_pcie_bram_7vx_rep_8k.v //
// Description : Implements 8 KB Single Ported Memory //
// - Output Regs are always enabled //
// - 2xRAMB36E1 Single Port Mode //
// //
//---------- PIPE Wrapper Hierarchy ------------------------------------------//
// pcie_bram_7vx_rep_8k.v //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie3_7x_0_pcie_bram_7vx_rep_8k #(
parameter IMPL_TARGET = "HARD", // the implementation target, HARD or SOFT
parameter NO_DECODE_LOGIC = "TRUE", // No decode logic, TRUE or FALSE
parameter INTERFACE_SPEED = "500 MHZ", // the memory interface speed, 500 MHz or 250 MHz.
parameter COMPLETION_SPACE = "16 KB" // the completion FIFO spec, 8KB or 16KB
) (
input clk_i, // user clock
input reset_i, // bram reset
input [8:0] addr_i, // address
input [127:0] wdata_i, // write data
input [15:0] wdip_i, // write parity
input [1:0] wen_i, // write enable
output [127:0] rdata_o, // read data
output [15:0] rdop_o // read parity
);
genvar i;
wire [1:0] wen = {wen_i[1], wen_i[0]};
generate
for (i = 0; i < 2; i = i + 1) begin : RAMB36E1
RAMB36E1 #(
.SIM_DEVICE ("7SERIES"),
.RDADDR_COLLISION_HWCONFIG ( "DELAYED_WRITE" ),
.DOA_REG ( 1 ),
.DOB_REG ( 1 ),
.EN_ECC_READ ( "FALSE" ),
.EN_ECC_WRITE ( "FALSE" ),
.RAM_EXTENSION_A ( "NONE" ),
.RAM_EXTENSION_B ( "NONE" ),
.RAM_MODE ( "TDP" ),
.READ_WIDTH_A ( 36 ),
.READ_WIDTH_B ( 36 ),
.RSTREG_PRIORITY_A ( "REGCE" ),
.RSTREG_PRIORITY_B ( "REGCE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SRVAL_A ( 36'h000000000 ),
.SRVAL_B ( 36'h000000000 ),
.WRITE_MODE_A ( "WRITE_FIRST" ),
.WRITE_MODE_B ( "WRITE_FIRST" ),
.WRITE_WIDTH_A ( 36 ),
.WRITE_WIDTH_B ( 36 )
)
u_buffer (
.CASCADEINA (),
.CASCADEINB (),
.CASCADEOUTA (),
.CASCADEOUTB (),
.CLKARDCLK (clk_i),
.CLKBWRCLK (clk_i),
.DBITERR (),
.ENARDEN (1'b1),
.ENBWREN (1'b1),
.INJECTDBITERR (1'b0),
.INJECTSBITERR (1'b0),
.REGCEAREGCE (1'b1 ),
.REGCEB (1'b1 ),
.RSTRAMARSTRAM (1'b0),
.RSTRAMB (1'b0),
.RSTREGARSTREG (1'b0),
.RSTREGB (1'b0),
.SBITERR (),
.ADDRARDADDR ({1'b1, addr_i[8:0], 6'b0}),
.ADDRBWRADDR ({1'b1, addr_i[8:0], 1'b1, 5'b0}),
.DIADI (wdata_i[(2*32*i)+31:(2*32*i)+0]),
.DIBDI (wdata_i[(2*32*i)+63:(2*32*i)+32]),
.DIPADIP (wdip_i[(2*4*i)+3:(2*4*i)+0]),
.DIPBDIP (wdip_i[(2*4*i)+7:(2*4*i)+4]),
.DOADO (rdata_o[(2*32*i)+31:(2*32*i)+0]),
.DOBDO (rdata_o[(2*32*i)+63:(2*32*i)+32]),
.DOPADOP (rdop_o[(2*4*i)+3:(2*4*i)+0]),
.DOPBDOP (rdop_o[(2*4*i)+7:(2*4*i)+4]),
.ECCPARITY (),
.RDADDRECC (),
.WEA ({4{wen[i]}}),
.WEBWE ({4'b0, {4{wen[i]}}})
);
end
endgenerate
endmodule // pcie_bram_7vx_rep_8k
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2014, University of British Columbia (UBC); All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// bcam.v: Binary Content Addressable Memory (BCAM) wrapper for: //
// Behavioral (BHV), register-based (REG), transposed-RAM stage (TRS) //
// ,transposed-RAM cascade (TRC) & segmented transposed-RAM (STR) //
// //
// Author: Ameer M.S. Abdelhadi ([email protected], [email protected]) //
// SRAM-based 2D BCAM; The University of British Columbia (UBC), April 2014 //
////////////////////////////////////////////////////////////////////////////////////
`include "utils.vh"
`ifndef SIM
// configure architectural parameters for synthesis
// to define CAMD, CAMW, SEGW, and TYPE
`include "config.vh"
`endif
`ifndef TYPE
`define TYPE ""
`endif
`ifndef PIPE
`define PIPE 0
`endif
`ifndef BYPS
`define BYPS 1
`endif
module bcam
#( parameter CAMD = `CAMD , // CAM depth / a multiply of SEGW
parameter CAMW = `CAMW , // CAM/pattern width
parameter SEGW = `SEGW , // Segment width / STRAM only
parameter BYPS = `BYPS , // Bypassed? (binary; 0 or 1)
parameter PIPE = `PIPE , // Pipelined? (binary; 0 or 1)
parameter INOM = 1 , // binary / Initial CAM with no match
parameter REGW = 1 , // binary / register write inputs wEnb, wAddr, & wPatt?
parameter REGM = 1 , // binary / register match input mPatt?
parameter REGO = 1 , // binary / register outputs match & mAddr?
parameter BRAM = "M20K", // BRAM type- "M20K":Altera's M20K; "GEN":generic
parameter TYPE = `TYPE ) // implementation type: BHV, REG, TRS, TRC, & STR
( input clk , // clock
input rst , // global registers reset
input wEnb , // write enable
input [`log2(CAMD)-1:0] wAddr , // write address
input [ CAMW -1:0] wPatt , // write patterns
input [ CAMW -1:0] mPatt , // patern to match
output match , // match indicator
output [`log2(CAMD)-1:0] mAddr ); // matched address
localparam ADDRW = `log2(CAMD); // address width
// register inputs 1
reg wEnbR;
reg [ADDRW-1:0] wAddrR;
reg [CAMW -1:0] wPattR,mPattR;
always @(posedge clk, posedge rst)
if (rst) {wEnbR,wAddrR,wPattR,mPattR} <= {(1 +ADDRW+CAMW +CAMW ){1'b0}};
else {wEnbR,wAddrR,wPattR,mPattR} <= { wEnb,wAddr,wPatt,mPatt };
// register inputs 2
reg wEnbRR;
reg [ADDRW-1:0] wAddrRR;
reg [CAMW -1:0] wPattRR,mPattRR;
always @(posedge clk, posedge rst)
if (rst) {wEnbRR,wAddrRR,wPattRR,mPattRR} <= {(1 +ADDRW +CAMW +CAMW ){1'b0}};
else {wEnbRR,wAddrRR,wPattRR,mPattRR} <= { wEnbR,wAddrR,wPattR,mPattR };
// assign inputs
wire wEnbI = PIPE ? wEnbRR : ( REGW ? wEnbR : wEnb );
wire [ADDRW-1:0] wAddrI = PIPE ? wAddrRR : ( REGW ? wAddrR : wAddr );
wire [CAMW -1:0] wPattI = PIPE ? wPattRR : ( REGW ? wPattR : wPatt );
wire [CAMW -1:0] mPattI = PIPE ? mPattRR : ( REGM ? mPattR : mPatt );
// generate and instantiate BCAM with specific implementation
wire matchI;
wire [ADDRW-1:0] mAddrI;
generate
if (TYPE=="BHV") begin
// instantiate behavioral BCAM
bcam_bhv #( .CAMD ( CAMD ), // CAM depth
.CAMW ( CAMW ), // CAM/pattern width
.INOM ( INOM )) // binary / Initial CAM with no match (has priority over IFILE)
bcam_bhv_i ( .clk ( clk ), // clock
.rst ( rst ), // global registers reset
.wEnb ( wEnbI ), // write enable
.wAddr( wAddrI ), // write address
.wPatt( wPattI ), // write pattern
.mPatt( mPattI ), // patern to match
.match( matchI ), // match indicator
.mAddr( mAddrI )); // matched address
end
else if (TYPE=="REG") begin
// instantiate register-based BCAM
bcam_reg #( .CAMD ( CAMD ), // CAM depth
.CAMW ( CAMW ), // CAM/pattern width
.PIPE ( PIPE ), // Pipelined? (binary; 0 or 1)
.INOM ( INOM )) // binary / Initial CAM with no match (has priority over IFILE)
bcam_reg_i ( .clk ( clk ), // clock
.rst ( rst ), // global registers reset
.wEnb ( wEnbI ), // write enable
.wAddr( wAddrI ), // write address
.wPatt( wPattI ), // write pattern
.mPatt( mPattI ), // patern to match
.match( matchI ), // match indicator
.mAddr( mAddrI )); // matched address
end
else if (TYPE=="TRS") begin
// instantiate transposed-RAM stage BCAM (TRS)
bcam_trc #( .CAMD ( CAMD ), // CAM depth
.CAMW ( CAMW ), // CAM/pattern width
.STGW ( 524288 ), // maximum stage width (9 for M20k; infinity for uncascaded) - allow STGW+1 for last stage if required
.BYPS ( BYPS ), // Bypassed? (binary; 0 or 1)
.PIPE ( PIPE ), // Pipelined? (binary; 0 or 1)
.INOM ( INOM ), // binary / Initial CAM with no match (has priority over IFILE)
.BRAM ( BRAM )) // BRAM type- "M20K":Altera's M20K; "GEN":generic
bcam_trs_i ( .clk ( clk ), // clock
.rst ( rst ), // global registers reset
.wEnb ( wEnbI ), // write enable
.wAddr( wAddrI ), // write address
.wPatt( wPattI ), // write pattern
.mPatt( mPattI ), // patern to match
.match( matchI ), // match indicator
.mAddr( mAddrI )); // matched address
end
else if (TYPE=="TRC") begin
// instantiate transposed-RAM cascade BCAM (TRC)
bcam_trc #( .CAMD ( CAMD ), // CAM depth
.CAMW ( CAMW ), // CAM/pattern width
.STGW ( 9 ), // maximum stage width (9 for M20k; infinity for uncascaded) - allow STGW+1 for last stage if required
.BYPS ( BYPS ), // Bypassed? (binary; 0 or 1)
.PIPE ( PIPE ), // Pipelined? (binary; 0 or 1)
.INOM ( INOM ), // binary / Initial CAM with no match (has priority over IFILE)
.BRAM ( BRAM )) // BRAM type- "M20K":Altera's M20K; "GEN":generic
bcam_trc_i ( .clk ( clk ), // clock
.rst ( rst ), // global registers reset
.wEnb ( wEnbI ), // write enable
.wAddr( wAddrI ), // write address
.wPatt( wPattI ), // write pattern
.mPatt( mPattI ), // patern to match
.match( matchI ), // match indicator
.mAddr( mAddrI )); // matched address
end
else begin // default: STRAM
// instantiate segmented transposed-RAM BCAM (STRAM)
bcam_str #( .CAMD ( CAMD ), // CAM depth
.CAMW ( CAMW ), // CAM/pattern width
.SEGW ( SEGW ), // Segment width
.BYPS ( BYPS ), // Bypassed? (binary; 0 or 1)
.PIPE ( PIPE ), // Pipelined? (binary; 0 or 1)
.INOM ( INOM ), // binary / Initial CAM with no match (has priority over IFILE)
.BRAM ( BRAM )) // BRAM type- "M20K":Altera's M20K; "GEN":generic
bcam_str_i ( .clk ( clk ), // clock
.rst ( rst ), // global registers reset
.wEnb ( wEnbI ), // write enable
.wAddr( wAddrI ), // write address
.wPatt( wPattI ), // write pattern
.mPatt( mPattI ), // patern to match
.match( matchI ), // match indicator
.mAddr( mAddrI )); // matched address
end
endgenerate
// register outputs 1
reg matchIR;
reg [ADDRW-1:0] mAddrIR;
always @(posedge clk, posedge rst)
if (rst) {matchIR,mAddrIR} <= {(1 +ADDRW ){1'b0}};
else {matchIR,mAddrIR} <= { matchI,mAddrI };
// register outputs 2
reg matchIRR;
reg [ADDRW-1:0] mAddrIRR;
always @(posedge clk, posedge rst)
if (rst) {matchIRR,mAddrIRR} <= {(1 +ADDRW ){1'b0}};
else {matchIRR,mAddrIRR} <= { matchIR,mAddrIR };
// assign outputs
assign match = PIPE ? matchIRR : ( REGO ? matchIR : matchI);
assign mAddr = PIPE ? mAddrIRR : ( REGO ? mAddrIR : mAddrI);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSDRIVER2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__BUSDRIVER2_FUNCTIONAL_PP_V
/**
* busdriver2: Bus driver (pmos devices).
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__busdriver2 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
bufif0 bufif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSDRIVER2_FUNCTIONAL_PP_V |
// megafunction wizard: %ALTFP_COMPARE%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altfp_compare
// ============================================================
// File Name: float_cmp.v
// Megafunction Name(s):
// altfp_compare
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 178 05/31/2012 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//altfp_compare CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" PIPELINE=1 WIDTH_EXP=8 WIDTH_MAN=23 ageb aleb clk_en clock dataa datab
//VERSION_BEGIN 12.0 cbx_altfp_compare 2012:05:31:20:23:38:SJ cbx_cycloneii 2012:05:31:20:23:38:SJ cbx_lpm_add_sub 2012:05:31:20:23:38:SJ cbx_lpm_compare 2012:05:31:20:23:38:SJ cbx_mgl 2012:05:31:20:24:43:SJ cbx_stratix 2012:05:31:20:23:38:SJ cbx_stratixii 2012:05:31:20:23:38:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = lpm_compare 4 reg 2
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module float_cmp_altfp_compare_5ac
(
ageb,
aleb,
clk_en,
clock,
dataa,
datab) ;
output ageb;
output aleb;
input clk_en;
input clock;
input [31:0] dataa;
input [31:0] datab;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg out_ageb_w_dffe3;
reg out_aleb_w_dffe3;
wire wire_cmpr1_aeb;
wire wire_cmpr1_agb;
wire wire_cmpr2_aeb;
wire wire_cmpr2_agb;
wire wire_cmpr3_aeb;
wire wire_cmpr3_agb;
wire wire_cmpr4_aeb;
wire wire_cmpr4_agb;
wire aclr;
wire aligned_dataa_sign_adjusted_dffe2_wi;
wire aligned_dataa_sign_adjusted_dffe2_wo;
wire aligned_dataa_sign_adjusted_w;
wire aligned_dataa_sign_dffe1_wi;
wire aligned_dataa_sign_dffe1_wo;
wire aligned_dataa_sign_w;
wire [30:0] aligned_dataa_w;
wire aligned_datab_sign_adjusted_dffe2_wi;
wire aligned_datab_sign_adjusted_dffe2_wo;
wire aligned_datab_sign_adjusted_w;
wire aligned_datab_sign_dffe1_wi;
wire aligned_datab_sign_dffe1_wo;
wire aligned_datab_sign_w;
wire [30:0] aligned_datab_w;
wire both_inputs_zero;
wire both_inputs_zero_dffe2_wi;
wire both_inputs_zero_dffe2_wo;
wire exp_a_all_one_dffe1_wi;
wire exp_a_all_one_dffe1_wo;
wire [7:0] exp_a_all_one_w;
wire exp_a_not_zero_dffe1_wi;
wire exp_a_not_zero_dffe1_wo;
wire [7:0] exp_a_not_zero_w;
wire [3:0] exp_aeb;
wire [3:0] exp_aeb_tmp_w;
wire exp_aeb_w;
wire exp_aeb_w_dffe2_wi;
wire exp_aeb_w_dffe2_wo;
wire [3:0] exp_agb;
wire [3:0] exp_agb_tmp_w;
wire exp_agb_w;
wire exp_agb_w_dffe2_wi;
wire exp_agb_w_dffe2_wo;
wire exp_b_all_one_dffe1_wi;
wire exp_b_all_one_dffe1_wo;
wire [7:0] exp_b_all_one_w;
wire exp_b_not_zero_dffe1_wi;
wire exp_b_not_zero_dffe1_wo;
wire [7:0] exp_b_not_zero_w;
wire [2:0] exp_eq_grp;
wire [3:0] exp_eq_gt_grp;
wire flip_outputs_dffe2_wi;
wire flip_outputs_dffe2_wo;
wire flip_outputs_w;
wire input_dataa_nan_dffe2_wi;
wire input_dataa_nan_dffe2_wo;
wire input_dataa_nan_w;
wire input_dataa_zero_w;
wire input_datab_nan_dffe2_wi;
wire input_datab_nan_dffe2_wo;
wire input_datab_nan_w;
wire input_datab_zero_w;
wire [1:0] man_a_not_zero_dffe1_wi;
wire [1:0] man_a_not_zero_dffe1_wo;
wire [1:0] man_a_not_zero_merge_w;
wire [22:0] man_a_not_zero_w;
wire [1:0] man_b_not_zero_dffe1_wi;
wire [1:0] man_b_not_zero_dffe1_wo;
wire [1:0] man_b_not_zero_merge_w;
wire [22:0] man_b_not_zero_w;
wire out_aeb_w;
wire out_agb_w;
wire out_ageb_dffe3_wi;
wire out_ageb_dffe3_wo;
wire out_ageb_w;
wire out_alb_w;
wire out_aleb_dffe3_wi;
wire out_aleb_dffe3_wo;
wire out_aleb_w;
wire out_unordered_w;
// synopsys translate_off
initial
out_ageb_w_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) out_ageb_w_dffe3 <= 1'b0;
else if (clk_en == 1'b1) out_ageb_w_dffe3 <= out_ageb_dffe3_wi;
// synopsys translate_off
initial
out_aleb_w_dffe3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) out_aleb_w_dffe3 <= 1'b0;
else if (clk_en == 1'b1) out_aleb_w_dffe3 <= out_aleb_dffe3_wi;
lpm_compare cmpr1
(
.aeb(wire_cmpr1_aeb),
.agb(wire_cmpr1_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa(aligned_dataa_w[30:23]),
.datab(aligned_datab_w[30:23])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cmpr1.lpm_representation = "UNSIGNED",
cmpr1.lpm_width = 8,
cmpr1.lpm_type = "lpm_compare";
lpm_compare cmpr2
(
.aeb(wire_cmpr2_aeb),
.agb(wire_cmpr2_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa(aligned_dataa_w[22:15]),
.datab(aligned_datab_w[22:15])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cmpr2.lpm_representation = "UNSIGNED",
cmpr2.lpm_width = 8,
cmpr2.lpm_type = "lpm_compare";
lpm_compare cmpr3
(
.aeb(wire_cmpr3_aeb),
.agb(wire_cmpr3_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa(aligned_dataa_w[14:7]),
.datab(aligned_datab_w[14:7])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cmpr3.lpm_representation = "UNSIGNED",
cmpr3.lpm_width = 8,
cmpr3.lpm_type = "lpm_compare";
lpm_compare cmpr4
(
.aeb(wire_cmpr4_aeb),
.agb(wire_cmpr4_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa(aligned_dataa_w[6:0]),
.datab(aligned_datab_w[6:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cmpr4.lpm_representation = "UNSIGNED",
cmpr4.lpm_width = 7,
cmpr4.lpm_type = "lpm_compare";
assign
aclr = 1'b0,
ageb = out_ageb_dffe3_wo,
aleb = out_aleb_dffe3_wo,
aligned_dataa_sign_adjusted_dffe2_wi = aligned_dataa_sign_adjusted_w,
aligned_dataa_sign_adjusted_dffe2_wo = aligned_dataa_sign_adjusted_dffe2_wi,
aligned_dataa_sign_adjusted_w = (aligned_dataa_sign_dffe1_wo & (~ input_dataa_zero_w)),
aligned_dataa_sign_dffe1_wi = aligned_dataa_sign_w,
aligned_dataa_sign_dffe1_wo = aligned_dataa_sign_dffe1_wi,
aligned_dataa_sign_w = dataa[31],
aligned_dataa_w = {dataa[30:0]},
aligned_datab_sign_adjusted_dffe2_wi = aligned_datab_sign_adjusted_w,
aligned_datab_sign_adjusted_dffe2_wo = aligned_datab_sign_adjusted_dffe2_wi,
aligned_datab_sign_adjusted_w = (aligned_datab_sign_dffe1_wo & (~ input_datab_zero_w)),
aligned_datab_sign_dffe1_wi = aligned_datab_sign_w,
aligned_datab_sign_dffe1_wo = aligned_datab_sign_dffe1_wi,
aligned_datab_sign_w = datab[31],
aligned_datab_w = {datab[30:0]},
both_inputs_zero = (input_dataa_zero_w & input_datab_zero_w),
both_inputs_zero_dffe2_wi = both_inputs_zero,
both_inputs_zero_dffe2_wo = both_inputs_zero_dffe2_wi,
exp_a_all_one_dffe1_wi = exp_a_all_one_w[7],
exp_a_all_one_dffe1_wo = exp_a_all_one_dffe1_wi,
exp_a_all_one_w = {(dataa[30] & exp_a_all_one_w[6]), (dataa[29] & exp_a_all_one_w[5]), (dataa[28] & exp_a_all_one_w[4]), (dataa[27] & exp_a_all_one_w[3]), (dataa[26] & exp_a_all_one_w[2]), (dataa[25] & exp_a_all_one_w[1]), (dataa[24] & exp_a_all_one_w[0]), dataa[23]},
exp_a_not_zero_dffe1_wi = exp_a_not_zero_w[7],
exp_a_not_zero_dffe1_wo = exp_a_not_zero_dffe1_wi,
exp_a_not_zero_w = {(dataa[30] | exp_a_not_zero_w[6]), (dataa[29] | exp_a_not_zero_w[5]), (dataa[28] | exp_a_not_zero_w[4]), (dataa[27] | exp_a_not_zero_w[3]), (dataa[26] | exp_a_not_zero_w[2]), (dataa[25] | exp_a_not_zero_w[1]), (dataa[24] | exp_a_not_zero_w[0]), dataa[23]},
exp_aeb = {wire_cmpr4_aeb, wire_cmpr3_aeb, wire_cmpr2_aeb, wire_cmpr1_aeb},
exp_aeb_tmp_w = {(exp_aeb[3] & exp_aeb_tmp_w[2]), (exp_aeb[2] & exp_aeb_tmp_w[1]), (exp_aeb[1] & exp_aeb_tmp_w[0]), exp_aeb[0]},
exp_aeb_w = exp_aeb_tmp_w[3],
exp_aeb_w_dffe2_wi = exp_aeb_w,
exp_aeb_w_dffe2_wo = exp_aeb_w_dffe2_wi,
exp_agb = {wire_cmpr4_agb, wire_cmpr3_agb, wire_cmpr2_agb, wire_cmpr1_agb},
exp_agb_tmp_w = {(exp_agb_tmp_w[2] | exp_eq_gt_grp[3]), (exp_agb_tmp_w[1] | exp_eq_gt_grp[2]), (exp_agb_tmp_w[0] | exp_eq_gt_grp[1]), exp_eq_gt_grp[0]},
exp_agb_w = exp_agb_tmp_w[3],
exp_agb_w_dffe2_wi = exp_agb_w,
exp_agb_w_dffe2_wo = exp_agb_w_dffe2_wi,
exp_b_all_one_dffe1_wi = exp_b_all_one_w[7],
exp_b_all_one_dffe1_wo = exp_b_all_one_dffe1_wi,
exp_b_all_one_w = {(datab[30] & exp_b_all_one_w[6]), (datab[29] & exp_b_all_one_w[5]), (datab[28] & exp_b_all_one_w[4]), (datab[27] & exp_b_all_one_w[3]), (datab[26] & exp_b_all_one_w[2]), (datab[25] & exp_b_all_one_w[1]), (datab[24] & exp_b_all_one_w[0]), datab[23]},
exp_b_not_zero_dffe1_wi = exp_b_not_zero_w[7],
exp_b_not_zero_dffe1_wo = exp_b_not_zero_dffe1_wi,
exp_b_not_zero_w = {(datab[30] | exp_b_not_zero_w[6]), (datab[29] | exp_b_not_zero_w[5]), (datab[28] | exp_b_not_zero_w[4]), (datab[27] | exp_b_not_zero_w[3]), (datab[26] | exp_b_not_zero_w[2]), (datab[25] | exp_b_not_zero_w[1]), (datab[24] | exp_b_not_zero_w[0]), datab[23]},
exp_eq_grp = {(exp_eq_grp[1] & exp_aeb[2]), (exp_eq_grp[0] & exp_aeb[1]), exp_aeb[0]},
exp_eq_gt_grp = {(exp_eq_grp[2] & exp_agb[3]), (exp_eq_grp[1] & exp_agb[2]), (exp_eq_grp[0] & exp_agb[1]), exp_agb[0]},
flip_outputs_dffe2_wi = flip_outputs_w,
flip_outputs_dffe2_wo = flip_outputs_dffe2_wi,
flip_outputs_w = (aligned_dataa_sign_adjusted_w & aligned_datab_sign_adjusted_w),
input_dataa_nan_dffe2_wi = input_dataa_nan_w,
input_dataa_nan_dffe2_wo = input_dataa_nan_dffe2_wi,
input_dataa_nan_w = (exp_a_all_one_dffe1_wo & man_a_not_zero_merge_w[1]),
input_dataa_zero_w = (~ exp_a_not_zero_dffe1_wo),
input_datab_nan_dffe2_wi = input_datab_nan_w,
input_datab_nan_dffe2_wo = input_datab_nan_dffe2_wi,
input_datab_nan_w = (exp_b_all_one_dffe1_wo & man_b_not_zero_merge_w[1]),
input_datab_zero_w = (~ exp_b_not_zero_dffe1_wo),
man_a_not_zero_dffe1_wi = {man_a_not_zero_w[22], man_a_not_zero_w[11]},
man_a_not_zero_dffe1_wo = man_a_not_zero_dffe1_wi,
man_a_not_zero_merge_w = {(man_a_not_zero_dffe1_wo[1] | man_a_not_zero_merge_w[0]), man_a_not_zero_dffe1_wo[0]},
man_a_not_zero_w = {(dataa[22] | man_a_not_zero_w[21]), (dataa[21] | man_a_not_zero_w[20]), (dataa[20] | man_a_not_zero_w[19]), (dataa[19] | man_a_not_zero_w[18]), (dataa[18] | man_a_not_zero_w[17]), (dataa[17] | man_a_not_zero_w[16]), (dataa[16] | man_a_not_zero_w[15]), (dataa[15] | man_a_not_zero_w[14]), (dataa[14] | man_a_not_zero_w[13]), (dataa[13] | man_a_not_zero_w[12]), dataa[12], (dataa[11] | man_a_not_zero_w[10]), (dataa[10] | man_a_not_zero_w[9]), (dataa[9] | man_a_not_zero_w[8]), (dataa[8] | man_a_not_zero_w[7]), (dataa[7] | man_a_not_zero_w[6]), (dataa[6] | man_a_not_zero_w[5]), (dataa[5] | man_a_not_zero_w[4]), (dataa[4] | man_a_not_zero_w[3]), (dataa[3] | man_a_not_zero_w[2]), (dataa[2] | man_a_not_zero_w[1]), (dataa[1] | man_a_not_zero_w[0]), dataa[0]},
man_b_not_zero_dffe1_wi = {man_b_not_zero_w[22], man_b_not_zero_w[11]},
man_b_not_zero_dffe1_wo = man_b_not_zero_dffe1_wi,
man_b_not_zero_merge_w = {(man_b_not_zero_dffe1_wo[1] | man_b_not_zero_merge_w[0]), man_b_not_zero_dffe1_wo[0]},
man_b_not_zero_w = {(datab[22] | man_b_not_zero_w[21]), (datab[21] | man_b_not_zero_w[20]), (datab[20] | man_b_not_zero_w[19]), (datab[19] | man_b_not_zero_w[18]), (datab[18] | man_b_not_zero_w[17]), (datab[17] | man_b_not_zero_w[16]), (datab[16] | man_b_not_zero_w[15]), (datab[15] | man_b_not_zero_w[14]), (datab[14] | man_b_not_zero_w[13]), (datab[13] | man_b_not_zero_w[12]), datab[12], (datab[11] | man_b_not_zero_w[10]), (datab[10] | man_b_not_zero_w[9]), (datab[9] | man_b_not_zero_w[8]), (datab[8] | man_b_not_zero_w[7]), (datab[7] | man_b_not_zero_w[6]), (datab[6] | man_b_not_zero_w[5]), (datab[5] | man_b_not_zero_w[4]), (datab[4] | man_b_not_zero_w[3]), (datab[3] | man_b_not_zero_w[2]), (datab[2] | man_b_not_zero_w[1]), (datab[1] | man_b_not_zero_w[0]), datab[0]},
out_aeb_w = ((((~ (aligned_dataa_sign_adjusted_dffe2_wo ^ aligned_datab_sign_adjusted_dffe2_wo)) & exp_aeb_w_dffe2_wo) | both_inputs_zero_dffe2_wo) & (~ out_unordered_w)),
out_agb_w = (((((~ aligned_dataa_sign_adjusted_dffe2_wo) & aligned_datab_sign_adjusted_dffe2_wo) | ((exp_agb_w_dffe2_wo & (~ aligned_dataa_sign_adjusted_dffe2_wo)) & (~ both_inputs_zero_dffe2_wo))) | ((flip_outputs_dffe2_wo & (~ exp_agb_w_dffe2_wo)) & (~ out_aeb_w))) & (~ out_unordered_w)),
out_ageb_dffe3_wi = out_ageb_w,
out_ageb_dffe3_wo = out_ageb_w_dffe3,
out_ageb_w = ((out_agb_w | out_aeb_w) & (~ out_unordered_w)),
out_alb_w = (((~ out_agb_w) & (~ out_aeb_w)) & (~ out_unordered_w)),
out_aleb_dffe3_wi = out_aleb_w,
out_aleb_dffe3_wo = out_aleb_w_dffe3,
out_aleb_w = ((out_alb_w | out_aeb_w) & (~ out_unordered_w)),
out_unordered_w = (input_dataa_nan_dffe2_wo | input_datab_nan_dffe2_wo);
endmodule //float_cmp_altfp_compare_5ac
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module float_cmp (
clk_en,
clock,
dataa,
datab,
ageb,
aleb);
input clk_en;
input clock;
input [31:0] dataa;
input [31:0] datab;
output ageb;
output aleb;
wire sub_wire0;
wire sub_wire1;
wire aleb = sub_wire0;
wire ageb = sub_wire1;
float_cmp_altfp_compare_5ac float_cmp_altfp_compare_5ac_component (
.clk_en (clk_en),
.clock (clock),
.datab (datab),
.dataa (dataa),
.aleb (sub_wire0),
.ageb (sub_wire1));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: FPM_FORMAT NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_EXP NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_MAN NUMERIC "23"
// Retrieval info: USED_PORT: ageb 0 0 0 0 OUTPUT NODEFVAL "ageb"
// Retrieval info: USED_PORT: aleb 0 0 0 0 OUTPUT NODEFVAL "aleb"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
// Retrieval info: CONNECT: ageb 0 0 0 0 @ageb 0 0 0 0
// Retrieval info: CONNECT: aleb 0 0 0 0 @aleb 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL float_cmp.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL float_cmp.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL float_cmp.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL float_cmp.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL float_cmp_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL float_cmp_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
/*****************************************************************************
* *
* Module: Altera_UP_PS2_Command_Out *
* Description: *
* This module sends commands out to the PS2 core. *
* *
*****************************************************************************/
module Altera_UP_PS2_Command_Out (
// Inputs
clk,
reset,
the_command,
send_command,
ps2_clk_posedge,
ps2_clk_negedge,
// Bidirectionals
PS2_CLK,
PS2_DAT,
// Outputs
command_was_sent,
error_communication_timed_out
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
// Timing info for initiating Host-to-Device communication
// when using a 50MHz system clock
parameter CLOCK_CYCLES_FOR_101US = 5050;
parameter NUMBER_OF_BITS_FOR_101US = 13;
parameter COUNTER_INCREMENT_FOR_101US = 13'h0001;
//parameter CLOCK_CYCLES_FOR_101US = 50;
//parameter NUMBER_OF_BITS_FOR_101US = 6;
//parameter COUNTER_INCREMENT_FOR_101US = 6'h01;
// Timing info for start of transmission error
// when using a 50MHz system clock
parameter CLOCK_CYCLES_FOR_15MS = 750000;
parameter NUMBER_OF_BITS_FOR_15MS = 20;
parameter COUNTER_INCREMENT_FOR_15MS = 20'h00001;
// Timing info for sending data error
// when using a 50MHz system clock
parameter CLOCK_CYCLES_FOR_2MS = 100000;
parameter NUMBER_OF_BITS_FOR_2MS = 17;
parameter COUNTER_INCREMENT_FOR_2MS = 17'h00001;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [7:0] the_command;
input send_command;
input ps2_clk_posedge;
input ps2_clk_negedge;
// Bidirectionals
inout PS2_CLK;
inout PS2_DAT;
// Outputs
output reg command_was_sent;
output reg error_communication_timed_out;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// states
parameter PS2_STATE_0_IDLE = 3'h0,
PS2_STATE_1_INITIATE_COMMUNICATION = 3'h1,
PS2_STATE_2_WAIT_FOR_CLOCK = 3'h2,
PS2_STATE_3_TRANSMIT_DATA = 3'h3,
PS2_STATE_4_TRANSMIT_STOP_BIT = 3'h4,
PS2_STATE_5_RECEIVE_ACK_BIT = 3'h5,
PS2_STATE_6_COMMAND_WAS_SENT = 3'h6,
PS2_STATE_7_TRANSMISSION_ERROR = 3'h7;
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [3:0] cur_bit;
reg [8:0] ps2_command;
reg [NUMBER_OF_BITS_FOR_101US:1] command_initiate_counter;
reg [NUMBER_OF_BITS_FOR_15MS:1] waiting_counter;
reg [NUMBER_OF_BITS_FOR_2MS:1] transfer_counter;
// State Machine Registers
reg [2:0] ns_ps2_transmitter;
reg [2:0] s_ps2_transmitter;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
s_ps2_transmitter <= PS2_STATE_0_IDLE;
else
s_ps2_transmitter <= ns_ps2_transmitter;
end
always @(*)
begin
// Defaults
ns_ps2_transmitter = PS2_STATE_0_IDLE;
case (s_ps2_transmitter)
PS2_STATE_0_IDLE:
begin
if (send_command == 1'b1)
ns_ps2_transmitter = PS2_STATE_1_INITIATE_COMMUNICATION;
else
ns_ps2_transmitter = PS2_STATE_0_IDLE;
end
PS2_STATE_1_INITIATE_COMMUNICATION:
begin
if (command_initiate_counter == CLOCK_CYCLES_FOR_101US)
ns_ps2_transmitter = PS2_STATE_2_WAIT_FOR_CLOCK;
else
ns_ps2_transmitter = PS2_STATE_1_INITIATE_COMMUNICATION;
end
PS2_STATE_2_WAIT_FOR_CLOCK:
begin
if (ps2_clk_negedge == 1'b1)
ns_ps2_transmitter = PS2_STATE_3_TRANSMIT_DATA;
else if (waiting_counter == CLOCK_CYCLES_FOR_15MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_2_WAIT_FOR_CLOCK;
end
PS2_STATE_3_TRANSMIT_DATA:
begin
if ((cur_bit == 4'd8) && (ps2_clk_negedge == 1'b1))
ns_ps2_transmitter = PS2_STATE_4_TRANSMIT_STOP_BIT;
else if (transfer_counter == CLOCK_CYCLES_FOR_2MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_3_TRANSMIT_DATA;
end
PS2_STATE_4_TRANSMIT_STOP_BIT:
begin
if (ps2_clk_negedge == 1'b1)
ns_ps2_transmitter = PS2_STATE_5_RECEIVE_ACK_BIT;
else if (transfer_counter == CLOCK_CYCLES_FOR_2MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_4_TRANSMIT_STOP_BIT;
end
PS2_STATE_5_RECEIVE_ACK_BIT:
begin
if (ps2_clk_posedge == 1'b1)
ns_ps2_transmitter = PS2_STATE_6_COMMAND_WAS_SENT;
else if (transfer_counter == CLOCK_CYCLES_FOR_2MS)
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
else
ns_ps2_transmitter = PS2_STATE_5_RECEIVE_ACK_BIT;
end
PS2_STATE_6_COMMAND_WAS_SENT:
begin
if (send_command == 1'b0)
ns_ps2_transmitter = PS2_STATE_0_IDLE;
else
ns_ps2_transmitter = PS2_STATE_6_COMMAND_WAS_SENT;
end
PS2_STATE_7_TRANSMISSION_ERROR:
begin
if (send_command == 1'b0)
ns_ps2_transmitter = PS2_STATE_0_IDLE;
else
ns_ps2_transmitter = PS2_STATE_7_TRANSMISSION_ERROR;
end
default:
begin
ns_ps2_transmitter = PS2_STATE_0_IDLE;
end
endcase
end
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
always @(posedge clk)
begin
if (reset == 1'b1)
ps2_command <= 9'h000;
else if (s_ps2_transmitter == PS2_STATE_0_IDLE)
ps2_command <= {(^the_command) ^ 1'b1, the_command};
end
always @(posedge clk)
begin
if (reset == 1'b1)
command_initiate_counter <= {NUMBER_OF_BITS_FOR_101US{1'b0}};
else if ((s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) &&
(command_initiate_counter != CLOCK_CYCLES_FOR_101US))
command_initiate_counter <=
command_initiate_counter + COUNTER_INCREMENT_FOR_101US;
else if (s_ps2_transmitter != PS2_STATE_1_INITIATE_COMMUNICATION)
command_initiate_counter <= {NUMBER_OF_BITS_FOR_101US{1'b0}};
end
always @(posedge clk)
begin
if (reset == 1'b1)
waiting_counter <= {NUMBER_OF_BITS_FOR_15MS{1'b0}};
else if ((s_ps2_transmitter == PS2_STATE_2_WAIT_FOR_CLOCK) &&
(waiting_counter != CLOCK_CYCLES_FOR_15MS))
waiting_counter <= waiting_counter + COUNTER_INCREMENT_FOR_15MS;
else if (s_ps2_transmitter != PS2_STATE_2_WAIT_FOR_CLOCK)
waiting_counter <= {NUMBER_OF_BITS_FOR_15MS{1'b0}};
end
always @(posedge clk)
begin
if (reset == 1'b1)
transfer_counter <= {NUMBER_OF_BITS_FOR_2MS{1'b0}};
else
begin
if ((s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) ||
(s_ps2_transmitter == PS2_STATE_4_TRANSMIT_STOP_BIT) ||
(s_ps2_transmitter == PS2_STATE_5_RECEIVE_ACK_BIT))
begin
if (transfer_counter != CLOCK_CYCLES_FOR_2MS)
transfer_counter <= transfer_counter + COUNTER_INCREMENT_FOR_2MS;
end
else
transfer_counter <= {NUMBER_OF_BITS_FOR_2MS{1'b0}};
end
end
always @(posedge clk)
begin
if (reset == 1'b1)
cur_bit <= 4'h0;
else if ((s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) &&
(ps2_clk_negedge == 1'b1))
cur_bit <= cur_bit + 4'h1;
else if (s_ps2_transmitter != PS2_STATE_3_TRANSMIT_DATA)
cur_bit <= 4'h0;
end
always @(posedge clk)
begin
if (reset == 1'b1)
command_was_sent <= 1'b0;
else if (s_ps2_transmitter == PS2_STATE_6_COMMAND_WAS_SENT)
command_was_sent <= 1'b1;
else if (send_command == 1'b0)
command_was_sent <= 1'b0;
end
always @(posedge clk)
begin
if (reset == 1'b1)
error_communication_timed_out <= 1'b0;
else if (s_ps2_transmitter == PS2_STATE_7_TRANSMISSION_ERROR)
error_communication_timed_out <= 1'b1;
else if (send_command == 1'b0)
error_communication_timed_out <= 1'b0;
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign PS2_CLK =
(s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) ?
1'b0 :
1'bz;
assign PS2_DAT =
(s_ps2_transmitter == PS2_STATE_3_TRANSMIT_DATA) ? ps2_command[cur_bit] :
(s_ps2_transmitter == PS2_STATE_2_WAIT_FOR_CLOCK) ? 1'b0 :
((s_ps2_transmitter == PS2_STATE_1_INITIATE_COMMUNICATION) &&
(command_initiate_counter[NUMBER_OF_BITS_FOR_101US] == 1'b1)) ? 1'b0 :
1'bz;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
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