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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 18:47:00 09/02/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #4 Project
// Module Name: BCD_Binary_Encoder
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: Binary to BCD Converter
//
// When the CONVERT signal asserts, the binary input BIN_IN is
// converted to BCD format. The BCD data is output at the end
// of the process on BCD_OUT and if an overflow occured then the
// BCD_OVERFLOW bit will be set. The conversion time depends on
// BIN_WINTH and is approximately BIN_WIDTH * 2 + 3 clock cycles.
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module BCD_Binary_Encoder
#(
parameter BIN_WIDTH = 8,
parameter BDC_DIGITS = 2
)
(
// Input Signals
input CONVERT,
output reg DONE,
input [BIN_WIDTH-1:0] BIN_IN,
// BCD Data Output Signals
output reg [BDC_DIGITS*4-1:0] BCD_OUT, // Packed Array
output reg BCD_OVERFLOW,
// System Signals
input CLK,
input RESET
);
// Include Standard Functions header file (needed for bit_index())
`include "StdFunctions.vh"
//
// BCD Register Width is 4-bits per BCD Digit
//
reg [4:0] State;
localparam [4:0]
S0 = 5'b00001,
S1 = 5'b00010,
S2 = 5'b00100,
S3 = 5'b01000,
S4 = 5'b10000;
localparam BCD_WIDTH = 4 * BDC_DIGITS;
reg [BIN_WIDTH-1:0] bin_shift_reg;
reg [BCD_WIDTH-1:0] bcd_shift_reg;
reg [BCD_WIDTH-1:0] bcd_adder_sum;
//
// Shift Counter tracks number of BIN_IN bits shifted (using a Rollover Counter)
//
localparam SHIFT_COUNTER_WIDTH = bit_index( BIN_WIDTH );
localparam [SHIFT_COUNTER_WIDTH:0] SHIFT_COUNTER_LOADVAL = { 1'b1, {SHIFT_COUNTER_WIDTH{1'b0}} } - BIN_WIDTH[SHIFT_COUNTER_WIDTH:0] + 1'b1;
reg [SHIFT_COUNTER_WIDTH:0] shift_counter_reg;
// Shift Count Done when the counter rollsover
wire shift_counter_done = shift_counter_reg[SHIFT_COUNTER_WIDTH];
//
// BCD Column Adders
// After each shift, add 3 to any column equaling 5 or greater.
// One adder will be generated per BCD Digit.
// The selective adding is done by LUT instead of an actual adder.
//
genvar i;
generate
begin
for (i = 0; i < BDC_DIGITS; i=i+1)
begin : bcd_adders
always @*
begin
case (bcd_shift_reg[i*4 +: 4])
// No Add
4'b0000 : bcd_adder_sum[i*4 +: 4] <= 4'b0000; // 0 => 0
4'b0001 : bcd_adder_sum[i*4 +: 4] <= 4'b0001; // 1 => 1
4'b0010 : bcd_adder_sum[i*4 +: 4] <= 4'b0010; // 2 => 2
4'b0011 : bcd_adder_sum[i*4 +: 4] <= 4'b0011; // 3 => 3
4'b0100 : bcd_adder_sum[i*4 +: 4] <= 4'b0100; // 4 => 4
// Add 3
4'b0101 : bcd_adder_sum[i*4 +: 4] <= 4'b1000; // 5 => 8
4'b0110 : bcd_adder_sum[i*4 +: 4] <= 4'b1001; // 6 => 9
4'b0111 : bcd_adder_sum[i*4 +: 4] <= 4'b1010; // 7 => 10
4'b1000 : bcd_adder_sum[i*4 +: 4] <= 4'b1011; // 8 => 11
4'b1001 : bcd_adder_sum[i*4 +: 4] <= 4'b1100; // 9 => 12
// Invalid Inputs
4'b1010 : bcd_adder_sum[i*4 +: 4] <= 4'b0000; // 10
4'b1011 : bcd_adder_sum[i*4 +: 4] <= 4'b0000; // 11
4'b1100 : bcd_adder_sum[i*4 +: 4] <= 4'b0000; // 12
4'b1101 : bcd_adder_sum[i*4 +: 4] <= 4'b0000; // 13
4'b1110 : bcd_adder_sum[i*4 +: 4] <= 4'b0000; // 14
4'b1111 : bcd_adder_sum[i*4 +: 4] <= 4'b0000; // 15
endcase
end
end
end
endgenerate
//
// BCD Binary Encoder State Machine
//
reg overflow_flag;
// !! Lab 4: Implement the BCD Binary Encoder State Machine here !!
always @(posedge CLK, posedge RESET)
begin
if (RESET)
begin
State <= S0;
DONE <= 1'b0;
BCD_OUT <= {BDC_DIGITS*4{1'b0}};
BCD_OVERFLOW <= 1'b0;
shift_counter_reg <= {SHIFT_COUNTER_WIDTH+1{1'b0}};
bin_shift_reg <= {BIN_WIDTH{1'b0}};
bcd_shift_reg <= {BCD_WIDTH{1'b0}};
overflow_flag <= 1'b0;
end
else
begin
case (State)
S0 :
begin
DONE <= 1'b0;
if(CONVERT)
State <= S1;
end
S1 :
begin
bin_shift_reg <= BIN_IN;
bcd_shift_reg <= {BCD_WIDTH{1'b0}};
shift_counter_reg <= SHIFT_COUNTER_LOADVAL;
overflow_flag <= 1'b0;
State <= S2;
end
S2 :
begin
overflow_flag <= overflow_flag | bcd_shift_reg[BCD_WIDTH-1];
bcd_shift_reg <= { bcd_shift_reg[BCD_WIDTH-2:0], bin_shift_reg[BIN_WIDTH-1] };
bin_shift_reg <= { bin_shift_reg[BIN_WIDTH-2:0], 1'b0 };
if(shift_counter_done)
State <= S4;
else
State <= S3;
end
S3 :
begin
bcd_shift_reg <= bcd_adder_sum;
shift_counter_reg <= shift_counter_reg + 1'b1;
State <= S2;
end
S4:
begin
BCD_OUT <= bcd_shift_reg;
BCD_OVERFLOW <= overflow_flag;
DONE <= 1'b1;
State <= S0;
end
endcase
end
end
endmodule
|
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
`include "HardFloat_consts.vi"
`include "HardFloat_specialize.vi"
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
mulAddRecFNToRaw_preMul#(
parameter expWidth = 3, parameter sigWidth = 3
) (
control,
op,
a,
b,
c,
roundingMode,
mulAddA,
mulAddB,
mulAddC,
intermed_compactState,
intermed_sExp,
intermed_CDom_CAlignDist,
intermed_highAlignedSigC
);
`include "HardFloat_localFuncs.vi"
input [(`floatControlWidth - 1):0] control;
input [1:0] op;
input [(expWidth + sigWidth):0] a;
input [(expWidth + sigWidth):0] b;
input [(expWidth + sigWidth):0] c;
input [2:0] roundingMode;
output [(sigWidth - 1):0] mulAddA;
output [(sigWidth - 1):0] mulAddB;
output [(sigWidth*2 - 1):0] mulAddC;
output [5:0] intermed_compactState;
output signed [(expWidth + 1):0] intermed_sExp;
output [(clog2(sigWidth + 1) - 1):0] intermed_CDom_CAlignDist;
output [(sigWidth + 1):0] intermed_highAlignedSigC;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
localparam prodWidth = sigWidth*2;
localparam sigSumWidth = sigWidth + prodWidth + 3;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire isNaNA, isInfA, isZeroA, signA;
wire signed [(expWidth + 1):0] sExpA;
wire [sigWidth:0] sigA;
recFNToRawFN#(expWidth, sigWidth)
recFNToRawFN_a(a, isNaNA, isInfA, isZeroA, signA, sExpA, sigA);
wire isSigNaNA;
isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_a(a, isSigNaNA);
wire isNaNB, isInfB, isZeroB, signB;
wire signed [(expWidth + 1):0] sExpB;
wire [sigWidth:0] sigB;
recFNToRawFN#(expWidth, sigWidth)
recFNToRawFN_b(b, isNaNB, isInfB, isZeroB, signB, sExpB, sigB);
wire isSigNaNB;
isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_b(b, isSigNaNB);
wire isNaNC, isInfC, isZeroC, signC;
wire signed [(expWidth + 1):0] sExpC;
wire [sigWidth:0] sigC;
recFNToRawFN#(expWidth, sigWidth)
recFNToRawFN_c(c, isNaNC, isInfC, isZeroC, signC, sExpC, sigC);
wire isSigNaNC;
isSigNaNRecFN#(expWidth, sigWidth) isSigNaN_c(c, isSigNaNC);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire signProd = signA ^ signB ^ op[1];
wire signed [(expWidth + 2):0] sExpAlignedProd =
sExpA + sExpB + (-(1<<expWidth) + sigWidth + 3);
wire doSubMags = signProd ^ signC ^ op[0];
wire opSignC = signProd ^ doSubMags;
wire roundingMode_min = (roundingMode == `round_min);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire signed [(expWidth + 2):0] sNatCAlignDist = sExpAlignedProd - sExpC;
wire [(expWidth + 1):0] posNatCAlignDist =
sNatCAlignDist[(expWidth + 1):0];
wire isMinCAlign = isZeroA || isZeroB || (sNatCAlignDist < 0);
wire CIsDominant =
!isZeroC && (isMinCAlign || (posNatCAlignDist <= sigWidth));
wire signed [(expWidth + 1):0] sExpSum =
CIsDominant ? sExpC : sExpAlignedProd - sigWidth;
wire [(clog2(sigSumWidth) - 1):0] CAlignDist =
isMinCAlign ? 0
: (posNatCAlignDist < sigSumWidth - 1)
? posNatCAlignDist[(clog2(sigSumWidth) - 1):0]
: sigSumWidth - 1;
wire signed [(sigSumWidth + 2):0] extComplSigC =
{doSubMags ? ~sigC : sigC, {(sigSumWidth - sigWidth + 2){doSubMags}}};
wire [(sigSumWidth + 1):0] mainAlignedSigC = extComplSigC>>>CAlignDist;
localparam CGrainAlign = (sigSumWidth - sigWidth - 1) & 3;
wire [(sigWidth + CGrainAlign):0] grainAlignedSigC = sigC<<CGrainAlign;
wire [(sigWidth + CGrainAlign)/4:0] reduced4SigC;
compressBy4#(sigWidth + 1 + CGrainAlign)
compressBy4_sigC(grainAlignedSigC, reduced4SigC);
localparam CExtraMaskHiBound = (sigSumWidth - 1)/4;
localparam CExtraMaskLoBound = (sigSumWidth - sigWidth - 1)/4;
wire [(CExtraMaskHiBound - CExtraMaskLoBound - 1):0] CExtraMask;
lowMaskHiLo#(clog2(sigSumWidth) - 2, CExtraMaskHiBound, CExtraMaskLoBound)
lowMask_CExtraMask(CAlignDist[(clog2(sigSumWidth) - 1):2], CExtraMask);
wire reduced4CExtra = |(reduced4SigC & CExtraMask);
wire [(sigSumWidth - 1):0] alignedSigC =
{mainAlignedSigC>>3,
doSubMags ? (&mainAlignedSigC[2:0]) && !reduced4CExtra
: (|mainAlignedSigC[2:0]) || reduced4CExtra};
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire isNaNAOrB = isNaNA || isNaNB;
wire isNaNAny = isNaNAOrB || isNaNC;
wire isInfAOrB = isInfA || isInfB;
wire invalidProd = (isInfA && isZeroB) || (isZeroA && isInfB);
wire notSigNaN_invalidExc =
invalidProd || (!isNaNAOrB && isInfAOrB && isInfC && doSubMags);
wire invalidExc =
isSigNaNA || isSigNaNB || isSigNaNC || notSigNaN_invalidExc;
wire notNaN_addZeros = (isZeroA || isZeroB) && isZeroC;
wire specialCase = isNaNAny || isInfAOrB || isInfC || notNaN_addZeros;
wire specialNotNaN_signOut =
(isInfAOrB && signProd) || (isInfC && opSignC)
|| (notNaN_addZeros && !roundingMode_min && signProd && opSignC)
|| (notNaN_addZeros && roundingMode_min && (signProd || opSignC));
`ifdef HardFloat_propagateNaNPayloads
wire signNaN;
wire [(sigWidth - 2):0] fractNaN;
propagateFloatNaN_mulAdd#(sigWidth)
propagateNaN(
control,
op,
isNaNA,
signA,
sigA[(sigWidth - 2):0],
isNaNB,
signB,
sigB[(sigWidth - 2):0],
invalidProd,
isNaNC,
signC,
sigC[(sigWidth - 2):0],
signNaN,
fractNaN
);
wire isNaNOut = isNaNAny || notSigNaN_invalidExc;
wire special_signOut =
isNaNAny || notSigNaN_invalidExc ? signNaN : specialNotNaN_signOut;
`else
wire special_signOut = specialNotNaN_signOut;
`endif
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
assign mulAddA = sigA;
assign mulAddB = sigB;
assign mulAddC = alignedSigC[prodWidth:1];
assign intermed_compactState =
{specialCase,
invalidExc || (!specialCase && signProd ),
`ifdef HardFloat_propagateNaNPayloads
isNaNOut || (!specialCase && doSubMags ),
`else
isNaNAny || (!specialCase && doSubMags ),
`endif
isInfAOrB || isInfC || (!specialCase && CIsDominant ),
notNaN_addZeros || (!specialCase && alignedSigC[0]),
special_signOut};
assign intermed_sExp = sExpSum;
assign intermed_CDom_CAlignDist = CAlignDist[(clog2(sigWidth + 1) - 1):0];
assign intermed_highAlignedSigC =
`ifdef HardFloat_propagateNaNPayloads
isNaNOut ? fractNaN :
`endif
alignedSigC[(sigSumWidth - 1):(prodWidth + 1)];
endmodule
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
mulAddRecFNToRaw_postMul#(parameter expWidth = 3, parameter sigWidth = 3) (
intermed_compactState,
intermed_sExp,
intermed_CDom_CAlignDist,
intermed_highAlignedSigC,
mulAddResult,
roundingMode,
invalidExc,
out_isNaN,
out_isInf,
out_isZero,
out_sign,
out_sExp,
out_sig
);
`include "HardFloat_localFuncs.vi"
input [5:0] intermed_compactState;
input signed [(expWidth + 1):0] intermed_sExp;
input [(clog2(sigWidth + 1) - 1):0] intermed_CDom_CAlignDist;
input [(sigWidth + 1):0] intermed_highAlignedSigC;
input [sigWidth*2:0] mulAddResult;
input [2:0] roundingMode;
output invalidExc;
output out_isNaN;
output out_isInf;
output out_isZero;
output out_sign;
output signed [(expWidth + 1):0] out_sExp;
output [(sigWidth + 2):0] out_sig;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
localparam prodWidth = sigWidth*2;
localparam sigSumWidth = sigWidth + prodWidth + 3;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire specialCase = intermed_compactState[5];
assign invalidExc = specialCase && intermed_compactState[4];
assign out_isNaN = specialCase && intermed_compactState[3];
assign out_isInf = specialCase && intermed_compactState[2];
wire notNaN_addZeros = specialCase && intermed_compactState[1];
wire signProd = intermed_compactState[4];
wire doSubMags = intermed_compactState[3];
wire CIsDominant = intermed_compactState[2];
wire bit0AlignedSigC = intermed_compactState[1];
wire special_signOut = intermed_compactState[0];
`ifdef HardFloat_propagateNaNPayloads
wire [(sigWidth - 2):0] fractNaN = intermed_highAlignedSigC;
`endif
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire opSignC = signProd ^ doSubMags;
wire [(sigWidth + 1):0] incHighAlignedSigC = intermed_highAlignedSigC + 1;
wire [(sigSumWidth - 1):0] sigSum =
{mulAddResult[prodWidth] ? incHighAlignedSigC
: intermed_highAlignedSigC,
mulAddResult[(prodWidth - 1):0],
bit0AlignedSigC};
wire roundingMode_min = (roundingMode == `round_min);
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire CDom_sign = opSignC;
wire signed [(expWidth + 1):0] CDom_sExp = intermed_sExp - doSubMags;
wire [(sigWidth*2 + 1):0] CDom_absSigSum =
doSubMags ? ~sigSum[(sigSumWidth - 1):(sigWidth + 1)]
: {1'b0, intermed_highAlignedSigC[(sigWidth + 1):sigWidth],
sigSum[(sigSumWidth - 3):(sigWidth + 2)]};
wire CDom_absSigSumExtra =
doSubMags ? !(&sigSum[sigWidth:1]) : |sigSum[(sigWidth + 1):1];
wire [(sigWidth + 4):0] CDom_mainSig =
(CDom_absSigSum<<intermed_CDom_CAlignDist)>>(sigWidth - 3);
wire [((sigWidth | 3) - 1):0] CDom_grainAlignedLowSig =
CDom_absSigSum[(sigWidth - 1):0]<<(~sigWidth & 3);
wire [sigWidth/4:0] CDom_reduced4LowSig;
compressBy4#(sigWidth | 3)
compressBy4_CDom_absSigSum(
CDom_grainAlignedLowSig, CDom_reduced4LowSig);
wire [(sigWidth/4 - 1):0] CDom_sigExtraMask;
lowMaskLoHi#(clog2(sigWidth + 1) - 2, 0, sigWidth/4)
lowMask_CDom_sigExtraMask(
intermed_CDom_CAlignDist[(clog2(sigWidth + 1) - 1):2],
CDom_sigExtraMask
);
wire CDom_reduced4SigExtra = |(CDom_reduced4LowSig & CDom_sigExtraMask);
wire [(sigWidth + 2):0] CDom_sig =
{CDom_mainSig>>3,
(|CDom_mainSig[2:0]) || CDom_reduced4SigExtra || CDom_absSigSumExtra};
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
wire notCDom_signSigSum = sigSum[prodWidth + 3];
wire [(prodWidth + 2):0] notCDom_absSigSum =
notCDom_signSigSum ? ~sigSum[(prodWidth + 2):0]
: sigSum[(prodWidth + 2):0] + doSubMags;
wire [(prodWidth + 2)/2:0] notCDom_reduced2AbsSigSum;
compressBy2#(prodWidth + 3)
compressBy2_notCDom_absSigSum(
notCDom_absSigSum, notCDom_reduced2AbsSigSum);
wire [(clog2(prodWidth + 4) - 2):0] notCDom_normDistReduced2;
countLeadingZeros#((prodWidth + 2)/2 + 1, clog2(prodWidth + 4) - 1)
countLeadingZeros_notCDom(
notCDom_reduced2AbsSigSum, notCDom_normDistReduced2);
wire [(clog2(prodWidth + 4) - 1):0] notCDom_nearNormDist =
notCDom_normDistReduced2<<1;
wire signed [(expWidth + 1):0] notCDom_sExp =
intermed_sExp - notCDom_nearNormDist;
wire [(sigWidth + 4):0] notCDom_mainSig =
({1'b0, notCDom_absSigSum}<<notCDom_nearNormDist)>>(sigWidth - 1);
wire [(((sigWidth/2 + 1) | 1) - 1):0] CDom_grainAlignedLowReduced2Sig =
notCDom_reduced2AbsSigSum[sigWidth/2:0]<<((sigWidth/2) & 1);
wire [(sigWidth + 2)/4:0] notCDom_reduced4AbsSigSum;
compressBy2#((sigWidth/2 + 1) | 1)
compressBy2_notCDom_reduced2AbsSigSum(
CDom_grainAlignedLowReduced2Sig, notCDom_reduced4AbsSigSum);
wire [((sigWidth + 2)/4 - 1):0] notCDom_sigExtraMask;
lowMaskLoHi#(clog2(prodWidth + 4) - 2, 0, (sigWidth + 2)/4)
lowMask_notCDom_sigExtraMask(
notCDom_normDistReduced2[(clog2(prodWidth + 4) - 2):1],
notCDom_sigExtraMask
);
wire notCDom_reduced4SigExtra =
|(notCDom_reduced4AbsSigSum & notCDom_sigExtraMask);
wire [(sigWidth + 2):0] notCDom_sig =
{notCDom_mainSig>>3,
(|notCDom_mainSig[2:0]) || notCDom_reduced4SigExtra};
wire notCDom_completeCancellation =
(notCDom_sig[(sigWidth + 2):(sigWidth + 1)] == 0);
wire notCDom_sign =
notCDom_completeCancellation ? roundingMode_min
: signProd ^ notCDom_signSigSum;
/*------------------------------------------------------------------------
*------------------------------------------------------------------------*/
assign out_isZero =
notNaN_addZeros || (!CIsDominant && notCDom_completeCancellation);
assign out_sign =
( specialCase && special_signOut)
|| (!specialCase && CIsDominant && CDom_sign )
|| (!specialCase && !CIsDominant && notCDom_sign );
assign out_sExp = CIsDominant ? CDom_sExp : notCDom_sExp;
`ifdef HardFloat_propagateNaNPayloads
assign out_sig =
out_isNaN ? {1'b1, fractNaN, 2'b00}
: CIsDominant ? CDom_sig : notCDom_sig;
`else
assign out_sig = CIsDominant ? CDom_sig : notCDom_sig;
`endif
endmodule
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
mulAddRecFNToRaw#(parameter expWidth = 3, parameter sigWidth = 3) (
input [(`floatControlWidth - 1):0] control,
input [1:0] op,
input [(expWidth + sigWidth):0] a,
input [(expWidth + sigWidth):0] b,
input [(expWidth + sigWidth):0] c,
input [2:0] roundingMode,
output invalidExc,
output out_isNaN,
output out_isInf,
output out_isZero,
output out_sign,
output signed [(expWidth + 1):0] out_sExp,
output [(sigWidth + 2):0] out_sig
);
`include "HardFloat_localFuncs.vi"
wire [(sigWidth - 1):0] mulAddA, mulAddB;
wire [(sigWidth*2 - 1):0] mulAddC;
wire [5:0] intermed_compactState;
wire signed [(expWidth + 1):0] intermed_sExp;
wire [(clog2(sigWidth + 1) - 1):0] intermed_CDom_CAlignDist;
wire [(sigWidth + 1):0] intermed_highAlignedSigC;
mulAddRecFNToRaw_preMul#(expWidth, sigWidth)
mulAddToRaw_preMul(
control,
op,
a,
b,
c,
roundingMode,
mulAddA,
mulAddB,
mulAddC,
intermed_compactState,
intermed_sExp,
intermed_CDom_CAlignDist,
intermed_highAlignedSigC
);
wire [sigWidth*2:0] mulAddResult = mulAddA * mulAddB + mulAddC;
mulAddRecFNToRaw_postMul#(expWidth, sigWidth)
mulAddToRaw_postMul(
intermed_compactState,
intermed_sExp,
intermed_CDom_CAlignDist,
intermed_highAlignedSigC,
mulAddResult,
roundingMode,
invalidExc,
out_isNaN,
out_isInf,
out_isZero,
out_sign,
out_sExp,
out_sig
);
endmodule
/*----------------------------------------------------------------------------
*----------------------------------------------------------------------------*/
module
mulAddRecFN#(parameter expWidth = 3, parameter sigWidth = 3) (
input [(`floatControlWidth - 1):0] control,
input [1:0] op,
input [(expWidth + sigWidth):0] a,
input [(expWidth + sigWidth):0] b,
input [(expWidth + sigWidth):0] c,
input [2:0] roundingMode,
output [(expWidth + sigWidth):0] out,
output [4:0] exceptionFlags
);
wire invalidExc, out_isNaN, out_isInf, out_isZero, out_sign;
wire signed [(expWidth + 1):0] out_sExp;
wire [(sigWidth + 2):0] out_sig;
mulAddRecFNToRaw#(expWidth, sigWidth)
mulAddRecFNToRaw(
control,
op,
a,
b,
c,
roundingMode,
invalidExc,
out_isNaN,
out_isInf,
out_isZero,
out_sign,
out_sExp,
out_sig
);
roundRawFNToRecFN#(expWidth, sigWidth, 0)
roundRawOut(
control,
invalidExc,
1'b0,
out_isNaN,
out_isInf,
out_isZero,
out_sign,
out_sExp,
out_sig,
roundingMode,
out,
exceptionFlags
);
endmodule
|
`timescale 1ns / 1ps
module nkmd_dai_tx_t;
// ins
reg clk;
parameter TCLK = 20;
initial clk = 0;
always #(TCLK/2) clk = ~clk;
reg rst;
reg pop;
reg [31:0] nkmd_data_i;
wire [31:0] nkmd_data_o;
reg [31:0] nkmd_addr;
reg nkmd_we;
nkmd_dai_tx uut(
.clk(clk),
.rst(rst),
.tx_pop_i(pop),
.data_i(nkmd_data_i),
.data_o(nkmd_data_o),
.addr_i(nkmd_addr),
.we_i(nkmd_we));
task queue;
input wire [23:0] sample;
begin
nkmd_addr = 32'h0000d001;
nkmd_data_i = {8'h0, sample};
nkmd_we = 1'b1;
#(TCLK);
nkmd_we = 1'b0;
end
endtask
task trigger_pop;
begin
pop = 1'b1;
#(TCLK);
pop = 1'b0;
end
endtask
reg [31:0] i;
initial begin
$dumpfile("nkmd_dai_tx_t.lxt");
$dumpvars(0, nkmd_dai_tx_t);
pop = 0;
nkmd_data_i = 32'h0;
nkmd_addr = 32'h0;
nkmd_we = 1'b0;
rst = 1'b1;
#(TCLK);
rst = 1'b0;
#(TCLK);
nkmd_addr = 32'h0000d001;
#(TCLK);
$display("expect %h, actual %h : queued_ff peek", 6'h0, uut.queued_ff);
$display("expect %h, actual %h : queued_ff ram read", 32'h0, nkmd_data_o);
queue(24'hcafebb);
nkmd_addr = 32'h0000e000;
#(TCLK);
$display("expect %h, actual %h : ringbuf ram read", 32'h00cafebb, nkmd_data_o);
nkmd_addr = 32'h0000d001;
#(TCLK);
$display("expect %h, actual %h : queued_ff peek", 6'h1, uut.queued_ff);
$display("expect %h, actual %h : queued_ff ram read", 32'h1, nkmd_data_o);
trigger_pop();
nkmd_addr = 32'h0000d001;
#(TCLK);
$display("expect %h, actual %h : queued_ff peek", 6'h0, uut.queued_ff);
$display("expect %h, actual %h : queued_ff ram read", 32'h0, nkmd_data_o);
for (i = 0; i < 63; i = i + 1) begin
queue(i);
end
$display("expect %h, actual %h : queued_ff peek", 6'd63, uut.queued_ff);
for (i = 0; i < 63; i = i + 1) begin
trigger_pop();
end
for (i = 63; i < 80; i = i + 1) begin
queue(i);
end
for (i = 63; i < 80; i = i + 1) begin
trigger_pop();
end
#(TCLK*3);
$finish(2);
end
always @(posedge clk) begin
if (uut.tx_ack_o)
$display("tx emit sample %h", uut.tx_data_o);
end
endmodule
|
/*
Copyright (c) 2016-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Generic source synchronous SDR output
*/
module ssio_sdr_out #
(
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
parameter TARGET = "GENERIC",
// IODDR style ("IODDR", "IODDR2")
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
// Use IODDR2 for Spartan-6
parameter IODDR_STYLE = "IODDR2",
// Width of register in bits
parameter WIDTH = 1
)
(
input wire clk,
input wire [WIDTH-1:0] input_d,
output wire output_clk,
output wire [WIDTH-1:0] output_q
);
oddr #(
.TARGET(TARGET),
.IODDR_STYLE(IODDR_STYLE),
.WIDTH(1)
)
clk_oddr_inst (
.clk(clk),
.d1(1'b0),
.d2(1'b1),
.q(output_clk)
);
(* IOB = "TRUE" *)
reg [WIDTH-1:0] output_q_reg = {WIDTH{1'b0}};
assign output_q = output_q_reg;
always @(posedge clk) begin
output_q_reg <= input_d;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:32:12 01/08/2011
// Design Name:
// Module Name: rtc_srtc
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module rtc (
input clkin,
input pgm_we,
input [55:0] rtc_data_in,
input we1,
input [59:0] rtc_data_in1,
output [59:0] rtc_data
);
reg [59:0] rtc_data_r;
reg [59:0] rtc_data_out_r;
reg [1:0] pgm_we_sreg;
always @(posedge clkin) pgm_we_sreg <= {pgm_we_sreg[0], pgm_we};
wire pgm_we_rising = (pgm_we_sreg[1:0] == 2'b01);
reg [2:0] we1_sreg;
always @(posedge clkin) we1_sreg <= {we1_sreg[1:0], we1};
wire we1_rising = (we1_sreg[2:1] == 2'b01);
reg [31:0] tick_cnt;
always @(posedge clkin) begin
tick_cnt <= tick_cnt + 1;
if((tick_cnt == 21500000) || pgm_we_rising) tick_cnt <= 0;
end
assign rtc_data = rtc_data_out_r;
reg [21:0] rtc_state;
reg carry;
reg [3:0] dom1[11:0];
reg [3:0] dom10[11:0];
reg [3:0] month;
reg [1:0] year;
reg [4:0] dow_day;
reg [3:0] dow_month;
reg [13:0] dow_year;
reg [6:0] dow_year1;
reg [6:0] dow_year100;
reg [15:0] dow_tmp;
parameter [21:0]
STATE_SEC1 = 22'b0000000000000000000001,
STATE_SEC10 = 22'b0000000000000000000010,
STATE_MIN1 = 22'b0000000000000000000100,
STATE_MIN10 = 22'b0000000000000000001000,
STATE_HOUR1 = 22'b0000000000000000010000,
STATE_HOUR10 = 22'b0000000000000000100000,
STATE_DAY1 = 22'b0000000000000001000000,
STATE_DAY10 = 22'b0000000000000010000000,
STATE_MON1 = 22'b0000000000000100000000,
STATE_MON10 = 22'b0000000000001000000000,
STATE_YEAR1 = 22'b0000000000010000000000,
STATE_YEAR10 = 22'b0000000000100000000000,
STATE_YEAR100 = 22'b0000000001000000000000,
STATE_YEAR1000 = 22'b0000000010000000000000,
STATE_DOW0 = 22'b0000000100000000000000,
STATE_DOW1 = 22'b0000001000000000000000,
STATE_DOW2 = 22'b0000010000000000000000,
STATE_DOW3 = 22'b0000100000000000000000,
STATE_DOW4 = 22'b0001000000000000000000,
STATE_DOW5 = 22'b0010000000000000000000,
STATE_LATCH = 22'b0100000000000000000000,
STATE_IDLE = 22'b1000000000000000000000;
initial begin
rtc_state = STATE_IDLE;
dom1[0] = 1; dom10[0] = 3;
dom1[1] = 8; dom10[1] = 2;
dom1[2] = 1; dom10[2] = 3;
dom1[3] = 0; dom10[3] = 3;
dom1[4] = 1; dom10[4] = 3;
dom1[5] = 0; dom10[5] = 3;
dom1[6] = 1; dom10[6] = 3;
dom1[7] = 1; dom10[7] = 3;
dom1[8] = 0; dom10[8] = 3;
dom1[9] = 1; dom10[9] = 3;
dom1[10] = 0; dom10[10] = 3;
dom1[11] = 1; dom10[11] = 3;
month = 0;
rtc_data_r = 60'h220110301000000;
tick_cnt = 0;
end
wire is_leapyear_feb = (month == 1) && (year[1:0] == 2'b00);
always @(posedge clkin) begin
if(!tick_cnt) begin
rtc_state <= STATE_SEC1;
end else begin
case (rtc_state)
STATE_SEC1:
rtc_state <= STATE_SEC10;
STATE_SEC10:
rtc_state <= STATE_MIN1;
STATE_MIN1:
rtc_state <= STATE_MIN10;
STATE_MIN10:
rtc_state <= STATE_HOUR1;
STATE_HOUR1:
rtc_state <= STATE_HOUR10;
STATE_HOUR10:
rtc_state <= STATE_DAY1;
STATE_DAY1:
rtc_state <= STATE_DAY10;
STATE_DAY10:
rtc_state <= STATE_MON1;
STATE_MON1:
rtc_state <= STATE_MON10;
STATE_MON10:
rtc_state <= STATE_YEAR1;
STATE_YEAR1:
rtc_state <= STATE_YEAR10;
STATE_YEAR10:
rtc_state <= STATE_YEAR100;
STATE_YEAR100:
rtc_state <= STATE_YEAR1000;
STATE_YEAR1000:
rtc_state <= STATE_DOW0;
STATE_DOW0:
rtc_state <= STATE_DOW1;
STATE_DOW1:
rtc_state <= STATE_DOW2;
STATE_DOW2:
rtc_state <= STATE_DOW3;
STATE_DOW3:
rtc_state <= STATE_DOW4;
STATE_DOW4:
if(dow_tmp > 13)
rtc_state <= STATE_DOW4;
else
rtc_state <= STATE_DOW5;
STATE_DOW5:
rtc_state <= STATE_LATCH;
STATE_LATCH:
rtc_state <= STATE_IDLE;
default:
rtc_state <= STATE_IDLE;
endcase
end
end
always @(posedge clkin) begin
if(pgm_we_rising) begin
rtc_data_r[55:0] <= rtc_data_in;
end else if (we1_rising) begin
rtc_data_r <= rtc_data_in1;
end else begin
case(rtc_state)
STATE_SEC1: begin
if(rtc_data_r[3:0] == 9) begin
rtc_data_r[3:0] <= 0;
carry <= 1;
end else begin
rtc_data_r[3:0] <= rtc_data_r[3:0] + 1;
carry <= 0;
end
end
STATE_SEC10: begin
if(carry) begin
if(rtc_data_r[7:4] == 5) begin
rtc_data_r[7:4] <= 0;
carry <= 1;
end else begin
rtc_data_r[7:4] <= rtc_data_r[7:4] + 1;
carry <= 0;
end
end
end
STATE_MIN1: begin
if(carry) begin
if(rtc_data_r[11:8] == 9) begin
rtc_data_r[11:8] <= 0;
carry <= 1;
end else begin
rtc_data_r[11:8] <= rtc_data_r[11:8] + 1;
carry <= 0;
end
end
end
STATE_MIN10: begin
if(carry) begin
if(rtc_data_r[15:12] == 5) begin
rtc_data_r[15:12] <= 0;
carry <= 1;
end else begin
rtc_data_r[15:12] <= rtc_data_r[15:12] + 1;
carry <= 0;
end
end
end
STATE_HOUR1: begin
if(carry) begin
if(rtc_data_r[23:20] == 2 && rtc_data_r[19:16] == 3) begin
rtc_data_r[19:16] <= 0;
carry <= 1;
end else if (rtc_data_r[19:16] == 9) begin
rtc_data_r[19:16] <= 0;
carry <= 1;
end else begin
rtc_data_r[19:16] <= rtc_data_r[19:16] + 1;
carry <= 0;
end
end
end
STATE_HOUR10: begin
if(carry) begin
if(rtc_data_r[23:20] == 2) begin
rtc_data_r[23:20] <= 0;
carry <= 1;
end else begin
rtc_data_r[23:20] <= rtc_data_r[23:20] + 1;
carry <= 0;
end
end
end
STATE_DAY1: begin
if(carry) begin
if(rtc_data_r[31:28] == dom10[month]
&& rtc_data_r[27:24] == dom1[month] + is_leapyear_feb) begin
rtc_data_r[27:24] <= 0;
carry <= 1;
end else if (rtc_data_r[27:24] == 9) begin
rtc_data_r[27:24] <= 0;
carry <= 1;
end else begin
rtc_data_r[27:24] <= rtc_data_r[27:24] + 1;
carry <= 0;
end
end
end
STATE_DAY10: begin
if(carry) begin
if(rtc_data_r[31:28] == dom10[month]) begin
rtc_data_r[31:28] <= 0;
rtc_data_r[27:24] <= 1;
carry <= 1;
end else begin
rtc_data_r[31:28] <= rtc_data_r[31:28] + 1;
carry <= 0;
end
end
end
STATE_MON1: begin
if(carry) begin
if(rtc_data_r[39:36] == 1 && rtc_data_r[35:32] == 2) begin
rtc_data_r[35:32] <= 1;
carry <= 1;
end else if (rtc_data_r[35:32] == 9) begin
rtc_data_r[35:32] <= 0;
carry <= 1;
end else begin
rtc_data_r[35:32] <= rtc_data_r[35:32] + 1;
carry <= 0;
end
end
end
STATE_MON10: begin
if(carry) begin
if(rtc_data_r[39:36] == 1) begin
rtc_data_r[39:36] <= 0;
carry <= 1;
end else begin
rtc_data_r[39:36] <= rtc_data_r[39:36] + 1;
carry <= 0;
end
end
end
STATE_YEAR1: begin
month <= rtc_data_r[35:32] + (rtc_data_r[36] ? 10 : 0) - 1;
if(carry) begin
if(rtc_data_r[43:40] == 9) begin
rtc_data_r[43:40] <= 0;
carry <= 1;
end else begin
rtc_data_r[43:40] <= rtc_data_r[43:40] + 1;
carry <= 0;
end
end
end
STATE_YEAR10: begin
if(carry) begin
if(rtc_data_r[47:44] == 9) begin
rtc_data_r[47:44] <= 0;
carry <= 1;
end else begin
rtc_data_r[47:44] <= rtc_data_r[47:44] + 1;
carry <= 0;
end
end
end
STATE_YEAR100: begin
if(carry) begin
if(rtc_data_r[51:48] == 9) begin
rtc_data_r[51:48] <= 0;
carry <= 1;
end else begin
rtc_data_r[51:48] <= rtc_data_r[51:48] + 1;
carry <= 0;
end
end
end
STATE_YEAR1000: begin
if(carry) begin
if(rtc_data_r[55:52] == 9) begin
rtc_data_r[55:52] <= 0;
carry <= 1;
end else begin
rtc_data_r[55:52] <= rtc_data_r[55:52] + 1;
carry <= 0;
end
end
end
STATE_DOW0: begin
dow_year1 <= rtc_data_r[43:40]
+(rtc_data_r[47:44] << 1) + (rtc_data_r[47:44] << 3);
dow_year100 <= rtc_data_r[51:48]
+(rtc_data_r[55:52] << 1) + (rtc_data_r[55:52] << 3);
dow_month <= month + 1;
dow_day <= rtc_data_r[27:24]
+ (rtc_data_r[31:28] << 1)
+ (rtc_data_r[31:28] << 3);
end
STATE_DOW1: begin
year <= dow_year1[1:0];
if(dow_month <= 2) begin
dow_month <= dow_month + 10;
dow_year <= dow_year1
+ (dow_year100 << 2)
+ (dow_year100 << 5)
+ (dow_year100 << 6) - 1;
if(dow_year1)
dow_year1 <= dow_year1 - 1;
else begin
dow_year1 <= 99;
dow_year100 <= dow_year100 - 1;
end
end else begin
dow_month <= dow_month - 2;
dow_year <= dow_year1 + (dow_year100 << 2) + (dow_year100 << 5) + (dow_year100 << 6);
end
end
STATE_DOW2: begin
dow_tmp <= (83 * dow_month);
end
STATE_DOW3: begin
dow_tmp <= (dow_tmp >> 5)
+ dow_day
+ dow_year
+ (dow_year >> 2)
- (dow_year100)
+ (dow_year100 >> 2);
end
STATE_DOW4: begin
dow_tmp <= dow_tmp - 7;
end
STATE_DOW5: begin
rtc_data_r[59:56] <= {1'b0, dow_tmp[2:0]};
end
STATE_LATCH: begin
rtc_data_out_r <= rtc_data_r;
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__MUX4_PP_SYMBOL_V
`define SKY130_FD_SC_HVL__MUX4_PP_SYMBOL_V
/**
* mux4: 4-input multiplexer.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__mux4 (
//# {{data|Data Signals}}
input A0 ,
input A1 ,
input A2 ,
input A3 ,
output X ,
//# {{control|Control Signals}}
input S0 ,
input S1 ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__MUX4_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFRTP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__SDFRTP_FUNCTIONAL_PP_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_ms__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ms__udp_dff$PR_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, RESET, , VPWR, VGND);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFRTP_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRBP_SYMBOL_V
`define SKY130_FD_SC_HS__SDFRBP_SYMBOL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRBP_SYMBOL_V
|
module main(
// clocks
input fclk,
output clkz_out,
input clkz_in,
// z80
input iorq_n,
input mreq_n,
input rd_n,
input wr_n,
input m1_n,
input rfsh_n,
output int_n,
output nmi_n,
output wait_n,
output res,
inout [7:0] d,
input [15:0] a,
// zxbus and related
output csrom,
output romoe_n,
output romwe_n,
output rompg0_n,
output dos_n, // aka rompg1
output rompg2,
output rompg3,
output rompg4,
input iorqge1,
input iorqge2,
output iorq1_n,
output iorq2_n,
// DRAM
inout [15:0] rd,
output [9:0] ra,
output rwe_n,
output rucas_n,
output rlcas_n,
output rras0_n,
output rras1_n,
// video
output [1:0] vred,
output [1:0] vgrn,
output [1:0] vblu,
output vhsync,
output vvsync,
output vcsync,
// AY control and audio/tape
output ay_clk,
output ay_bdir,
output ay_bc1,
output beep,
// IDE
output [2:0] ide_a,
inout [15:0] ide_d,
output ide_dir,
input ide_rdy,
output ide_cs0_n,
output ide_cs1_n,
output ide_rs_n,
output ide_rd_n,
output ide_wr_n,
// VG93 and diskdrive
output vg_clk,
output vg_cs_n,
output vg_res_n,
output vg_hrdy,
output vg_rclk,
output vg_rawr,
output [1:0] vg_a, // disk drive selection
output vg_wrd,
output vg_side,
input step,
input vg_sl,
input vg_sr,
input vg_tr43,
input rdat_b_n,
input vg_wf_de,
input vg_drq,
input vg_irq,
input vg_wd,
// serial links (atmega-fpga, sdcard)
output sdcs_n,
output sddo,
output sdclk,
input sddi,
input spics_n,
input spick,
input spido,
output spidi,
output spiint_n
);
wire zclk; // z80 clock for short
reg [2:0] zclk_gen; // make 3.5 mhz clock
wire rst_n; // global reset
wire rrdy;
wire cbeg;
wire [15:0] rddata;
wire [4:0] rompg;
wire [7:0] zports_dout;
wire zports_dataout;
wire porthit;
wire [4:0] keys;
wire tape_in;
wire [15:0] ideout;
wire [15:0] idein;
wire [7:0] zmem_dout;
wire zmem_dataout;
wire [7:0] sd_dout_to_zports;
wire start_from_zports;
wire sd_inserted;
wire sd_readonly;
reg [3:0] ayclk_gen;
wire [7:0] received;
wire [7:0] tobesent;
wire intrq,drq;
wire vg_wrFF;
// Z80 clock control
assign zclk = clkz_in;
always @(posedge fclk)
zclk_gen <= zclk_gen + 3'd1;
assign clkz_out = zclk_gen[2];
/* // RESETTER
resetter myrst( .clk(fclk),
.rst_in1_n(1'b1),
.rst_in2_n(1'b1),
.rst_out_n(rst_n) );
defparam myrst.RST_CNT_SIZE = 6;
*/
dram mydram( .clk(fclk),
.rst_n(1'b1),
.ra(ra),
.rd(rd),
.rwe_n(rwe_n),
.rras0_n(rras0_n),
.rras1_n(rras1_n),
.rucas_n(rucas_n),
.rlcas_n(rlcas_n),
.req(1'b0),
.rnw(1'b1)//,
//.rrdy(rrdy),
//.cbeg(cbeg),
//.bsel({a[0],~a[0]}),
//.wrdata({d,~d}),
//.rddata(rddata),
/*.addr({a[5:0],a[15:1]})*/ );
assign int_n=1'b1;
assign nmi_n=1'b1;
assign wait_n=1'b1;
assign res=1'b1;
assign d=8'hZZ;
assign csrom=1'b0;
assign romoe_n=1'b1;
assign romwe_n=1'b1;
assign iorq1_n=1'b1;
assign iorq2_n=1'b1;
assign rd=16'hZZZZ;
assign ay_bdir=1'b0;
assign ay_bc1=1'b0;
assign ide_d=16'hZZZZ;
assign ide_dir=1'b1;
assign ide_rs_n = 1'b0;
assign ide_cs1_n = 1'b1;
assign ide_rd_n = 1'b1;
assign ide_wr_n = 1'b1;
assign vg_cs_n=1'b1;
assign vg_res_n=1'b0;
assign sdcs_n=1'b1;
assign spiint_n=1'b1;
//AY control
always @(posedge fclk)
begin
ayclk_gen <= ayclk_gen + 4'd1;
end
assign ay_clk = ayclk_gen[3];
reg [23:0] counter;
reg blinker;
always @(posedge fclk)
begin
if( !counter )
begin
counter <= 24'd13999999;
blinker <= ~blinker;
end
else
counter <= counter - 24'd1;
end
assign ide_cs0_n = blinker;
endmodule
|
`timescale 1 ns / 1 ps
`define STR(a) `"a`"
`ifndef CPUNAME
`define CPUPREFIX .
`define CPUNAME cpu
`endif
`define IPATH(a) `include `STR(`CPUPREFIX/a)
`include "defines.v"
// This core is somewhat more complex than it should have been, because on ICE40 BRAMs are
// inferred if there is a registered input, while on Xilinx platforms an output must be registered,
// therefore we have to support both modes here.
//
// Register file is implemented as a distributed RAM (on Xilinx), but for the sake of timing we have to register
// the outputs on Xilinx anyway.
//
// ICE40 register file is inferred as mirroring BRAMs
//
`ifdef NEXYS
`define RAM_REGISTERED_OUT 1
`endif
`ifdef ICE
`define RAM_REGISTERED_OUT 1
`endif
`ifndef ICE
`define REGFILE_REGISTERED_OUT 1
`endif
// Uncomment this to disable microops support (CALL/RET)
// `define DISABLE_MICROOPS 1
// `define ENABLE_BARREL_SHIFTER 1
/* ISA encoding: see core.txt */
/* Microcode:
If DISABLE_MICROOPS is not defined, the core will treat absolute jumps to non-zero addresses as calls
and jumps to zero addresses as returns. Both are implemented as sequence of instructions scheduled while
FETCH stage is stalled:
For CALL, the instructions are following:
- (storei SP SP (const -1))
- (storei SP FP (const -1))
- (storei SP PC (const -1))
- (jmp (label ...))
For RET, the instructions are following:
- (load SP CP (const 3))
- (load SC FP (const 1))
- (load FP FP (const 2))
- (jmpci R1 SC (const 2))
- (nop)
- (nop)
(TODO: consider moving SP and FP loads into the delay slots?)
*/
// Pipeline:
//
// FETCH: sets the PC value, the next PC value (potentially from forwarding),
// for the next clock cycle to fetch the instruction for this PC
// DECODE0: receive the new instruction from or muop FSM, forward the new PC if it's a
// simple branch instruction, set the argument register addresses for regfile
// DECODE: receive the values from the regfile, apply forwarding from the corresponding
// WB stage
// EXEC: apply forwarding from the corresponding MEM and WB stage, the former is for the simple register
// results only (i.e., no addition, no memory output). Set up the complex branching PC forwarding.
// Run the ALU actions on the arguments. Set the RAM input/output address, data and WE
// MEM: receive the EXEC result and RAM output, set up forwarding into DECODE stage and a simple forwarding
// into the EXEC stage.
// WB: commit the register file write-back
/*
Ext includes here:
c2_custom_include.v - for including external modules
c2_custom_hoist.v - wires, registers, assignments, module instantiations
c2_custom_reset.v - register assignments in reset
c2_custom_pipeline.v - register assignments in pipeline
Long ext only:
c2_custom_idle.v - IDLE stage of the FSM
c2_custom_wait.v - WAIT stage of the FSM
*/
`ifdef ENABLE_EXT
`IPATH(c2_custom_include.v)
`endif
/////////////////////////
// A note on register and wire naming:
// A value relevant to a certain pipeline stage is prefixed with this stage name,
// e.g., if it's a DECODE stage PC, it is called decode_PC, even if it's assigned in the DECODE0 stage.
/////////////////////////
module `CPUNAME
(input clk,
input rst,
input [31:0] ram_data_in_a,
output [31:0] ram_addr_in_a,
input [31:0] ram_data_in_b,
output [31:0] ram_addr_in_b,
output [31:0] ram_data_out_b,
output ram_we_out,
/**************************/
// TODO: also include hoisted external signals
`IPATH(soccpusignals.v)
/**************************/
input stall_cpu // external stall
);
//---------------------------------------------------
//--1. Clock counter, for debugging and perf counters
//---------------------------------------------------
reg [31:0] clkcounter;
always @(posedge clk)
if (~rst) clkcounter <= 0;
else clkcounter <= clkcounter + 1;
// COMMON Stall logic
wire stall_exec;
wire stall_mem;
wire stall;
wire stall_but_ext;
reg unstall;
assign stall = stall_cpu | stall_exec | stall_mem; // ?!?
assign stall_but_ext = 0; // ?!?
assign stall_mem = 0;
//------------------------------------------------
//--2. FETCH logic--------------------------------
//------------------------------------------------
reg [31:0] fetch_PC; // PC value at the end of FETCH stage / in DECODE0 stage
wire [31:0] decode0_PC;
assign decode0_PC = fetch_PC;
wire [31:0] fetch_PC_next; // PC value in the FETCH stage
`ifndef RAM_REGISTERED_OUT
assign ram_addr_in_a = fetch_PC;
`else
assign ram_addr_in_a = fetch_PC_next;
`endif
wire decode0_branch_override1;
wire exec_branch_override2;
wire [31:0] decode0_PC_next; // PC value inferred at the DECODE stage
wire [31:0] exec_PC_next; // PC value inferred at the EXEC stage
reg decode_ready; // It's not the first clock cycle
assign fetch_PC_next = decode_ready?
(decode0_branch_override1?decode0_PC_next:
exec_branch_override2?exec_PC_next:
fetch_microops?fetch_PC:(fetch_PC + 1)):fetch_PC;
always @(posedge clk)
if (~rst) begin
fetch_PC <= 0;
decode_ready <= 0;
unstall <= 0;
end else begin
fetch_PC <= stall?fetch_PC:fetch_PC_next;
decode_ready <= 1;
unstall <= stall;
end
//------------------------------------------------
//--3. DECODE0 logic------------------------------
//------------------------------------------------
wire fetch_microops;
wire [31:0] fetch_next_muop;
wire [31:0] decode0_Instr; // Instruction as of beginning of DECODE0
reg [31:0] decode0_Instr_r;
reg stall_r;
// decode0_Instr arrives in the DECODE0 stage (from a PC address formed in the FETCH stage),
// or is generated by the muop FSM if it's a multi-stage instruction and muops are enabled.
assign decode0_Instr = stall_r?decode0_Instr_r:(
exec_typeee?0: // If it's a second part of a long extended instruction, push a bubble
fetch_microops?fetch_next_muop:
ram_data_in_a);
wire [4:0] decode0_reg1addr_next;
wire [4:0] decode0_reg2addr_next;
reg [4:0] decode_reg1addr;
reg [4:0] decode_reg2addr;
wire decode0_typea;
wire decode0_typeb1;
wire decode0_typeb2;
wire decode0_typei;
wire decode0_typee;
wire decode0_typem;
assign decode0_typea = decode0_Instr[2:0] == 0; // also true for type E and type EE
assign decode0_typeb1 = decode0_Instr[1:0] == 2'b01;
assign decode0_typeb2 = decode0_Instr[1:0] == 2'b11;
assign decode0_typei = decode0_Instr[1:0] == 2'b10;
assign decode0_typem = decode0_Instr[2:0] == 3'b100;
assign decode0_typee = decode0_Instr[6:0] == 7'b1111000;
assign decode0_reg1addr_next = decode0_typea?decode0_Instr[16:12]:
decode0_typeb2?decode0_Instr[7:3]:
decode0_typem?decode0_Instr[9:5]:0;
assign decode0_reg2addr_next = decode0_typea?decode0_Instr[21:17]:
decode0_typeb2?decode0_Instr[12:8]:
decode0_typem?decode0_Instr[14:10]:0;
assign decode0_branch_override1 = decode_ready?decode0_typeb1:0;
// Forwarding the simple branching PC value - 0 delay slots
wire [31:0] decode0_simmed29;
assign decode0_simmed29 = {{3{decode0_Instr[31]}},decode0_Instr[31:3]};
assign decode0_PC_next = decode0_typeb1?
(decode0_Instr[2]?(fetch_PC + decode0_simmed29):decode0_Instr[31:3]):
(fetch_PC + 1);
reg [31:0] decode_Instr;
reg [31:0] decode_PC;
wire [31:0] decode0_reg1addr_next1;
wire [31:0] decode0_reg2addr_next1;
assign decode0_reg1addr_next1 = stall?decode_reg1addr:decode0_reg1addr_next;
assign decode0_reg2addr_next1 = stall?decode_reg2addr:decode0_reg2addr_next;
always @(posedge clk)
if (~rst) begin
decode_reg1addr <= 0;
decode_reg2addr <= 0;
decode_PC <= 0;
decode_Instr <= 0;
// Stall logic:
decode0_Instr_r <= 0;
stall_r <= 0;
end else begin
decode_reg1addr <= decode0_reg1addr_next1;
decode_reg2addr <= decode0_reg2addr_next1;
decode_PC <= (stall|fetch_microops)?decode_PC:decode0_PC;
decode_Instr <= stall?decode_Instr:decode0_Instr;
decode0_Instr_r <= decode0_Instr;
stall_r <= stall;
end // else: !if(~rst)
// MUOP logic for DECODE0
`ifndef DISABLE_MICROOPS
wire is_muop;
wire is_call;
wire is_ret;
wire executing_microops;
assign fetch_microops = is_muop | executing_microops;
assign is_muop = (~executing_microops) & (ram_data_in_a[2:0] == 1);
assign is_ret = ram_data_in_a[31:3] == 0;
assign is_call = ~is_ret;
reg [31:0] next_muop_r;
assign fetch_next_muop = is_muop? // starting insn
(is_call?32'hfffff7bc: // (storei SP SP (const -1))
32'h1fba4): // (load SP FP (const 3))
next_muop_r;
reg [28:0] muop_call_dst;
reg [3:0] muop_state;
localparam S_MU_IDLE = 0;
localparam S_MU_CALL1 = 1;
localparam S_MU_CALL2 = 2;
localparam S_MU_RET1 = 3;
localparam S_MU_RET2 = 4;
localparam S_MU_RET3 = 5;
localparam S_MU_RET4 = 6;
localparam S_MU_DONE = 7;
assign executing_microops = muop_state != S_MU_IDLE;
always @(posedge clk)
if (~rst) begin
next_muop_r <= 0;
muop_call_dst <= 0;
muop_state <= S_MU_IDLE;
end else begin
case (muop_state)
S_MU_IDLE: begin
if (is_muop) begin // start muops
muop_call_dst <= ram_data_in_a[31:3];
if (is_call) begin
muop_state <= S_MU_CALL1;
next_muop_r <= 32'hfffff7dc; // (storei SP FP (const -1))
end else begin
muop_state <= S_MU_RET1;
next_muop_r <= 32'hfb84; // (load SC FP (const 1))
end
end
end
S_MU_CALL1: begin
muop_state <= S_MU_CALL2;
next_muop_r <= 32'hfffff7fc;
end
S_MU_CALL2: begin
muop_state <= S_MU_DONE;
next_muop_r <= {muop_call_dst, 3'b001};
end
S_MU_RET1: begin
next_muop_r <= 32'h17bc4; // (load FP FP (const 2))
muop_state <= S_MU_RET2;
end
S_MU_RET2: begin
next_muop_r <= 32'h9c0f; // (jmpci R1 SC (const 1))
muop_state <= S_MU_RET3;
end
S_MU_RET3: begin
next_muop_r <= 0;
muop_state <= S_MU_RET4;
end
S_MU_RET4: begin
next_muop_r <= 0;
muop_state <= S_MU_DONE;
end
S_MU_DONE: begin
muop_state <= S_MU_IDLE;
end
endcase
end // else: !if(~rst)
`else // !`ifndef DISABLE_MICROOPS
assign fetch_microops = 0;
assign fetch_next_muop = 0;
`endif
//------------------------------------------------
//--4. DECODE logic-------------------------------
//------------------------------------------------
wire fwd_mem;
wire [31:0] fwd_mem_data;
wire [4:0] fwd_mem_reg;
wire fwd_wb;
wire [31:0] fwd_wb_data;
wire [4:0] fwd_wb_reg;
wire [31:0] decode_arg1_next;
wire [31:0] decode_arg2_next;
// Register values returned from the regfile (as requested by the DECODE0 stage)
wire [31:0] decode_arg1_out;
wire [31:0] decode_arg2_out;
reg [31:0] decode_arg1_out_r;
reg [31:0] decode_arg2_out_r;
wire [31:0] decode_arg1_out_s = (unstall)?decode_arg1_out_r:decode_arg1_out;
wire [31:0] decode_arg2_out_s = (unstall)?decode_arg2_out_r:decode_arg2_out;
// Register argument values amended with forwarding (TODO!)
// Forwarding: WB -> DECODE
assign decode_arg1_next =
(fwd_mem &(fwd_mem_reg!=0)&(decode_reg1addr == fwd_mem_reg))?fwd_mem_data:
(fwd_wb &(fwd_wb_reg!=0)&(decode_reg1addr == fwd_wb_reg))?fwd_wb_data:
decode_arg1_out_s;
assign decode_arg2_next =
(fwd_mem &(fwd_mem_reg!=0)&(decode_reg2addr == fwd_mem_reg))?fwd_mem_data:
(fwd_wb &(fwd_wb_reg!=0)&(decode_reg2addr == fwd_wb_reg))?fwd_wb_data:
decode_arg2_out_s;
reg [31:0] exec_Instr;
reg [31:0] exec_PC;
reg [31:0] exec_arg1_r;
reg [31:0] exec_arg2_r;
reg [4:0] exec_reg1addr;
reg [4:0] exec_reg2addr;
`ifdef ICE_DEBUG
assign PCdebug = exec_PC;
`endif
always @(posedge clk)
if (~rst) begin
exec_Instr <= 0;
exec_PC <= 0;
exec_arg1_r <= 0;
exec_arg2_r <= 0;
exec_reg1addr <= 0;
exec_reg2addr <= 0;
decode_arg1_out_r <= 0;
decode_arg2_out_r <= 0;
end else begin
exec_Instr <= stall?exec_Instr:decode_Instr;
exec_PC <= stall?exec_PC:decode_PC;
exec_arg1_r <= stall?exec_arg1:decode_arg1_next;
exec_arg2_r <= stall?exec_arg2:decode_arg2_next;
exec_reg1addr <= stall?exec_reg1addr:decode_reg1addr;
exec_reg2addr <= stall?exec_reg2addr:decode_reg2addr;
decode_arg1_out_r <= decode_arg1_out_s;
decode_arg2_out_r <= decode_arg2_out_s;
end // else: !if(~rst)
//------------------------------------------------
//--5. EXEC logic---------------------------------
//------------------------------------------------
wire [31:0] exec_arg1;
wire [31:0] exec_arg2;
// Apply simple forwarding (MEM -> EXEC) and WB->EXEC
wire fwd_simple;
wire [31:0] fwd_simple_data;
wire [4:0] fwd_simple_reg;
assign exec_arg1 = (fwd_simple&(fwd_simple_reg!=0)&(exec_reg1addr == fwd_simple_reg))?fwd_simple_data:
(fwd_mem &(fwd_mem_reg!=0)&(exec_reg1addr == fwd_mem_reg))?fwd_mem_data:
(fwd_wb &(fwd_wb_reg!=0)&(exec_reg1addr == fwd_wb_reg))?fwd_wb_data:
exec_arg1_r;
assign exec_arg2 = (fwd_simple&(fwd_simple_reg!=0)&(exec_reg2addr == fwd_simple_reg))?fwd_simple_data:
(fwd_mem &(fwd_mem_reg!=0)&(exec_reg2addr == fwd_mem_reg))?fwd_mem_data:
(fwd_wb &(fwd_wb_reg!=0)&(exec_reg2addr == fwd_wb_reg))?fwd_wb_data:
exec_arg2_r;
wire exec_typei;
assign exec_typei = exec_Instr[1:0] == 2'b10;
wire [3:0] exec_opcode_typeA;
assign exec_opcode_typeA = exec_Instr[6:3];
wire exec_typee;
wire exec_typeee;
wire exec_isext;
wire exec_typeb2;
wire exec_typem;
wire exec_typea;
reg mem_typee;
reg mem_typei;
reg mem_typem;
reg mem_typea;
assign exec_typea = exec_Instr[2:0] == 0;
wire exec_ext_hasout;
assign exec_ext_hasout = exec_typee;
assign exec_isext = exec_typee;
assign exec_typeb2 = exec_Instr[1:0] == 2'b11;
assign exec_typem = exec_Instr[2:0] == 3'b100;
assign exec_typee = exec_Instr[6:0] == 7'b1111000;
assign exec_typeee = exec_typee & ( exec_Instr[31:22] == 10'b1111111111 );
localparam OPC_AND = 1;
localparam OPC_ADD = 2;
localparam OPC_SUB = 3;
localparam OPC_OR = 4;
localparam OPC_NOT = 5;
localparam OPC_SHL = 6;
localparam OPC_SHR = 7;
localparam OPC_XOR = 8;
localparam OPC_EQ = 9;
localparam OPC_NE = 10;
localparam OPC_CMP = 11;
localparam OPC_ASHR = 12;
localparam OPC_SELECT = 14;
localparam CMP_SLT = 0;
localparam CMP_SGT = 1;
localparam CMP_SLE = 2;
localparam CMP_SGE = 3;
localparam CMP_ULT = 4;
localparam CMP_UGT = 5;
localparam CMP_ULE = 6;
localparam CMP_UGE = 7;
wire [9:0] exec_immed10;
wire [31:0] exec_immed_signext;
assign exec_immed10 = exec_Instr[31:22];
assign exec_immed_signext = {{22{exec_Instr[31]}},exec_Instr[31:22]};
wire [31:0] exec_immed25_signext;
assign exec_immed25_signext = {{7{exec_Instr[31]}},exec_Instr[31:7]};
wire [31:0] exec_out_cmp;
assign exec_out_cmp = (exec_immed10[2:0] == CMP_SLT)?($signed(exec_arg1)<$signed(exec_arg2)):
(exec_immed10[2:0] == CMP_SGT)?($signed(exec_arg1)>$signed(exec_arg2)):
`ifndef DISABLE_CMPOPS
(exec_immed10[2:0] == CMP_SLE)?($signed(exec_arg1)<=$signed(exec_arg2)):
(exec_immed10[2:0] == CMP_SGE)?($signed(exec_arg1)>=$signed(exec_arg2)):
(exec_immed10[2:0] == CMP_ULT)?(exec_arg1<exec_arg2):
(exec_immed10[2:0] == CMP_UGT)?(exec_arg1>exec_arg2):
(exec_immed10[2:0] == CMP_ULE)?(exec_arg1<=exec_arg2):
(exec_immed10[2:0] == CMP_UGE)?(exec_arg1>=exec_arg2):
`endif
0;
wire [31:0] exec_out_next_alu;
assign exec_out_next_alu = (exec_opcode_typeA == OPC_ADD)?
(exec_arg1 + exec_arg2):
(exec_opcode_typeA == OPC_SUB)?
(exec_arg1 - exec_arg2):
(exec_opcode_typeA == OPC_AND)?
(exec_arg1 & exec_arg2):
(exec_opcode_typeA == OPC_OR)?
(exec_arg1 | exec_arg2):
(exec_opcode_typeA == OPC_XOR)?
(exec_arg1 ^ exec_arg2):
(exec_opcode_typeA == OPC_NOT)?
(~exec_arg1):
`ifdef ENABLE_BARREL_SHIFTER
(exec_opcode_typeA == OPC_SHL)?(exec_arg1 << exec_arg2):
(exec_opcode_typeA == OPC_SHR)?(exec_arg1 >> exec_arg2):
(exec_opcode_typeA == OPC_ASHR)?$signed($signed(exec_arg1) >>> exec_arg2):
`else
(exec_opcode_typeA == OPC_SHL)?(exec_arg1 << 1):
(exec_opcode_typeA == OPC_SHR)?(exec_arg1>>1):
(exec_opcode_typeA == OPC_ASHR)?({exec_arg1[31],exec_arg1[31:1]}):
`endif
(exec_opcode_typeA == OPC_EQ)?
(exec_arg1 ==
((exec_immed_signext == 0)?
exec_arg2:exec_immed_signext)):
(exec_opcode_typeA == OPC_NE)?
(exec_arg1 != exec_arg2):
(exec_opcode_typeA == OPC_CMP)?
(exec_out_cmp):
(exec_opcode_typeA == OPC_SELECT)?
(fwd_simple_data[0]?exec_arg1:exec_arg2):0;
wire [1:0] exec_opcode_typeM;
assign exec_opcode_typeM = exec_Instr[4:3];
localparam OPC_LOAD = 0;
localparam OPC_LOADR = 2;
localparam OPC_STORE = 1;
localparam OPC_STOREI = 3;
///
// EXEC memory address logic
///
reg [31:0] exec_ram_addr_b;
wire [31:0] exec_ram_addr_b_next;
reg [31:0] exec_ram_data_out_b;
wire [31:0] exec_ram_data_out_b_next;
reg exec_ram_we_out;
wire exec_ram_we_out_next;
// Mem queue:
reg [31:0] mem_queue_addr_1;
reg [31:0] mem_queue_data_1;
reg mem_queue_we_1;
reg [31:0] mem_queue_addr_2;
reg [31:0] mem_queue_data_2;
reg mem_queue_we_2;
reg [31:0] mem_queue_addr_3;
reg [31:0] mem_queue_data_3;
reg mem_queue_we_3;
wire [31:0] mem_queue_addr_0;
wire [31:0] mem_queue_data_0;
wire mem_queue_we_0;
assign mem_queue_addr_0 = exec_ram_addr_b;
assign mem_queue_data_0 = exec_ram_data_out_b;
assign mem_queue_we_0 = exec_ram_we_out;
assign ram_addr_in_b = exec_ram_addr_b;
assign ram_data_out_b = exec_ram_data_out_b;
assign ram_we_out = exec_ram_we_out;
wire [31:0] exec_simmed17;
assign exec_simmed17 = {{15{exec_Instr[31]}},exec_Instr[31:15]};
wire exec_isstore;
assign exec_isstore = exec_Instr[3];
assign exec_ram_addr_b_next
=
exec_typem?
((exec_opcode_typeM == OPC_STOREI)?exec_arg2:
(exec_arg2 + exec_simmed17)):0; // both LOAD and STORE
assign exec_ram_we_out_next = exec_typem&(exec_isstore);
assign exec_ram_data_out_b_next = exec_arg1;
reg [31:0] mem_out_alu_r;
reg [31:0] mem_out_s1_r;
reg [31:0] mem_immed_signext_r;
reg [31:0] mem_Instr;
reg [31:0] mem_PC;
wire [31:0] exec_simmed24;
assign exec_simmed24 = {{8{exec_Instr[31]}},exec_Instr[31:8]};
assign exec_branch_override2 = exec_typeb2;
assign exec_PC_next = (exec_Instr[2:1] == 2'b01 )?
(exec_arg1[0]?(exec_PC + exec_simmed24):(fetch_PC + 1)):
(exec_arg1[0]?(exec_arg2):(fetch_PC + 1));
reg [4:0] mem_sd_class;
wire [4:0] mem_sd_class_next;
assign mem_sd_class_next[0] = exec_typei;
assign mem_sd_class_next[1] = exec_ext_hasout;
assign mem_sd_class_next[2] = (exec_typem&(exec_opcode_typeM==3));
assign mem_sd_class_next[3] = exec_typea & (exec_opcode_typeA == OPC_ADD);
assign mem_sd_class_next[4] = exec_typem && (exec_opcode_typeM == 0); // LOAD
`ifdef ENABLE_EXT
`IPATH(c2_custom_hoist.v)
`endif
reg [3:0] sfsm_state;
localparam S_IDLE = 0;
localparam S_WAIT = 1;
localparam DONE = 1;
reg ext_done;
reg stall_exec_r;
assign stall_exec = (exec_typee && exec_immed10[0] && ~ext_done) || (sfsm_state == S_WAIT);
reg [31:0] mem_out_ext_r;
always @(posedge clk)
if (~rst) begin
mem_out_alu_r <= 0;
mem_out_s1_r <= 0;
mem_Instr <= 0;
mem_PC <= 0;
mem_typee <= 0; mem_typei <= 0; mem_typem <= 0; mem_typea <= 0;
mem_sd_class <= 0;
exec_ram_addr_b <= 0;
exec_ram_data_out_b <= 0;
exec_ram_we_out <= 0;
ext_done <= 0;
sfsm_state <= S_IDLE;
stall_exec_r <= 0;
mem_out_ext_r <= 0;
`ifdef ENABLE_EXT
`IPATH(c2_custom_reset.v)
`endif
end else begin
mem_out_alu_r <= stall?mem_out_alu_r:((exec_typei)?exec_immed25_signext:exec_out_next_alu);
mem_out_s1_r <= stall?mem_out_s1_r:(exec_arg2+exec_simmed17);
mem_immed_signext_r <= stall?mem_immed_signext_r:exec_immed_signext;
mem_Instr <= stall?mem_Instr:exec_Instr;
mem_PC <= stall?mem_PC:exec_PC;
mem_typee <= stall?mem_typee:exec_typee;
mem_typei <= stall?mem_typei:exec_typei;
mem_typem <= stall?mem_typem:exec_typem;
mem_typea <= stall?mem_typea:exec_typea;
mem_sd_class <= stall?mem_sd_class:mem_sd_class_next;
//
exec_ram_addr_b <= exec_ram_addr_b_next;
exec_ram_data_out_b <= exec_ram_data_out_b_next;
exec_ram_we_out <= exec_ram_we_out_next;
`ifndef DISABLE_MEMQUEUE
if (~stall) begin
mem_queue_addr_1 <= exec_ram_addr_b;
mem_queue_we_1 <= exec_ram_we_out;
mem_queue_data_1 <= exec_ram_data_out_b;
mem_queue_addr_2 <= mem_queue_addr_1;
mem_queue_we_2 <= mem_queue_we_1;
mem_queue_data_2 <= mem_queue_data_1;
mem_queue_addr_3 <= mem_queue_addr_2;
mem_queue_we_3 <= mem_queue_we_2;
mem_queue_data_3 <= mem_queue_data_2;
end // if (~stall)
`endif
`ifdef ENABLE_EXT
`IPATH(c2_custom_pipeline.v)
`endif
// Ext. FSM for the multi-cycle instructions (i.e., those with a wait stage)
`ifdef ENABLE_LONG_EXT
stall_exec_r <= stall_exec;
case (sfsm_state)
S_IDLE:
begin
ext_done <= 0;
if (exec_typee && exec_immed10[0] && ~stall_but_ext && ~ext_done) begin
sfsm_state <= S_WAIT;
end
end
S_WAIT:
begin
`IPATH(c2_custom_wait.v)
end
endcase
`endif
end
//------------------------------------------------
//--6. MEM logic----------------------------------
//------------------------------------------------
wire [31:0] mem_out_next;
wire [31:0] mem_out_simple_next;
wire mem_ext_hasout;
assign mem_ext_hasout = mem_typee;
wire [1:0] mem_opcode_typeM;
assign mem_opcode_typeM = mem_Instr[4:3];
wire [3:0] mem_opcode_typeA;
assign mem_opcode_typeA = mem_Instr[6:3];
wire [31:0] mem_ram_input;
`ifndef DISABLE_MEMQUEUE
assign mem_ram_input = ((mem_queue_addr_0 == mem_queue_addr_1)&mem_queue_we_1)?mem_queue_data_1:
((mem_queue_addr_0 == mem_queue_addr_2)&mem_queue_we_2)?mem_queue_data_2:
((mem_queue_addr_0 == mem_queue_addr_3)&mem_queue_we_3)?mem_queue_data_3:ram_data_in_b;
`else
assign mem_ram_input = ram_data_in_b;
`endif
// Selecting the right EXEC / RAM output
assign mem_out_next =
mem_sd_class==1?mem_out_alu_r:
mem_sd_class==2?mem_out_ext_r:
mem_sd_class==4?mem_out_s1_r:
mem_sd_class==8?(mem_out_alu_r + mem_immed_signext_r):
mem_out_alu_r;
// Same but without an addition and mem output, to shorten the forwarding critical path
assign mem_out_simple_next =
mem_sd_class==1?mem_out_alu_r:
mem_sd_class==2?mem_out_ext_r:
mem_sd_class==4?mem_out_s1_r:
mem_out_alu_r;
wire mem_out_we_next;
assign mem_out_we_next = mem_typei |
(mem_typea && (mem_opcode_typeA!=0)) |
(mem_typem && (mem_opcode_typeM == 3));
wire mem_out_we_delayed_next;
assign mem_out_we_delayed_next = mem_out_we_next | (mem_typem && (mem_opcode_typeM != 1));
wire [4:0] mem_out_reg_next;
assign mem_out_reg_next =
mem_typea?mem_Instr[11:7]:
(mem_typei?mem_Instr[6:2]:
((mem_typem&(mem_Instr[3]==0))?
mem_Instr[9:5]:
(mem_typem&(mem_opcode_typeM==3))?mem_Instr[14:10]:
mem_Instr[19:15]));
// A simple MEM->EXEC forwarding feedback
assign fwd_simple = mem_out_we_next;
assign fwd_simple_data = mem_out_simple_next;
assign fwd_simple_reg = mem_out_reg_next;
/////
reg [31:0] wb_Instr;
reg [31:0] wb_PC;
reg [31:0] mem_out;
reg mem_out_we;
reg mem_out_we_delayed;
reg [4:0] mem_out_reg;
reg wb_readmem;
assign fwd_mem = mem_out_we;
assign fwd_mem_reg = mem_out_reg;
assign fwd_mem_data = mem_out;
always @(posedge clk)
if (~rst) begin
wb_Instr <= 0;
wb_PC <= 0;
mem_out <= 0;
mem_out_we <= 0;
mem_out_we_delayed <= 0;
mem_out_reg <= 0;
wb_readmem <= 0;
end else begin
wb_Instr <= stall?wb_Instr:mem_Instr;
wb_PC <= stall?wb_PC:mem_PC;
mem_out <= stall?mem_out:mem_out_next;
mem_out_we <= stall?mem_out_we:mem_out_we_next;
mem_out_we_delayed <= stall?mem_out_we_delayed:mem_out_we_delayed_next;
mem_out_reg <= stall?mem_out_reg:mem_out_reg_next;
wb_readmem <= stall?wb_readmem:(mem_sd_class==16);
end // else: !if(~rst)
//------------------------------------------------
//--7. WB logic-----------------------------------
//------------------------------------------------
reg [31:0] wb_out;
reg wb_out_we;
reg [4:0] wb_out_reg;
wire [31:0] wb_ram_input;
`ifndef DISABLE_MEMQUEUE
assign wb_ram_input = ((mem_queue_addr_0 == mem_queue_addr_1)&mem_queue_we_1)?mem_queue_data_1:
((mem_queue_addr_0 == mem_queue_addr_2)&mem_queue_we_2)?mem_queue_data_2:
((mem_queue_addr_0 == mem_queue_addr_3)&mem_queue_we_3)?mem_queue_data_3:ram_data_in_b;
`else
assign wb_ram_input = ram_data_in_b;
`endif
wire [31:0] wb_out_next;
wire wb_out_we_next;
assign wb_out_next = wb_readmem?wb_ram_input:mem_out;
assign wb_out_we_next = mem_out_we_delayed;
assign fwd_wb = wb_out_we;
assign fwd_wb_reg = wb_out_reg;
assign fwd_wb_data = wb_out;
always @(posedge clk)
if (~rst) begin
wb_out <= 0;
wb_out_we <= 0;
wb_out_reg <= 0;
end else begin
wb_out <= stall?wb_out:wb_out_next;
wb_out_we <= stall?wb_out_we:wb_out_we_next;
wb_out_reg <= stall?wb_out_reg:mem_out_reg;
end
//------------------------------------------------
//--8. Reg file instance--------------------------
//------------------------------------------------
// Address values for the reg file are formed in the DECODE0 stage (or after DECODE0 stage if
// REGFILE_REGISTERED_OUT is not set).
// The output is ready in the DECODE stage (and quite late in it).
// Input port address, data and WE are formed in the end of WB stage
wire [4:0] dbgreg;
wire dbgreg_en;
assign dbgreg_en = 0;
regfile #(
`ifndef DISABLE_MICROOPS
.MICROOPS_ENABLED(1)
`else
.MICROOPS_ENABLED(0)
`endif
) regfile1
(.clk(clk),
.rst(rst),
.PC(fetch_PC), // PC value to be fed as a virtual register R31
`ifdef REGFILE_REGISTERED_OUT
.addr1(decode0_reg1addr_next1),
.addr2(decode0_reg2addr_next1),
`else
.addr1(decode_reg1addr),
.addr2(decode_reg2addr),
`endif
.out1(decode_arg1_out),
.out2(decode_arg2_out),
.dbgreg(dbgreg),
.dbgreg_en(dbgreg_en),
.wdata(wb_out),
.addrw(wb_out_reg),
.we(wb_out_we),
.clkcounter(clkcounter) // for debugging only
);
//------------------------------------------------
//-- 9. Debugging output--------------------------
//------------------------------------------------
`ifdef DEBUG
always @(posedge clk)
if (rst) begin
$display("");
$display("----------------------------------------------------");
$display("CLK %0d", clkcounter);
$display("IF PC=%0d", fetch_PC_next);
$display("DECODE0 PC=%0d \t INSN=%x", decode0_PC, decode0_Instr);
$display(" ARG1(R%0d) \t ARG2(R%0d)", decode0_reg1addr_next,
decode0_reg2addr_next);
$display("DECODE PC=%0d \t INSN=%x", decode_PC, decode_Instr);
/*
$display(" ARG1(R%0d) = %0d \t ARG2(R%0d) = %0d", decode_reg1addr,
decode_arg1_next,
decode_reg2addr, decode_arg2_next);
if (fwd_mem) $display(" MEM FWD: R%0d = %d", fwd_mem_reg, fwd_mem_data);
if (fwd_wb) $display(" WB FWD: R%0d = %d", fwd_wb_reg, fwd_wb_data);
*/
$display("EXEC PC=%0d \t INSN=%x", exec_PC, exec_Instr);
$display(" ARG1(R%0d)=%0d \t ARG2(R%0d)=%0d", exec_reg1addr, exec_arg1, exec_reg2addr, exec_arg2);
`ifdef DEBUGFWD
if (fwd_simple) $display(" SIMPLE FWD: R%0d = %d", fwd_simple_reg, fwd_simple_data);
if (fwd_mem) $display(" MEM FWD: R%0d = %d", fwd_mem_reg, fwd_mem_data);
if (fwd_wb) $display(" WB FWD: R%0d = %d", fwd_wb_reg, fwd_wb_data);
if (exec_isext) $display(" EXT OP");
if (exec_typem) $display(" MEM OP");
if (exec_typei) $display(" IMMED OP");
if (exec_typem & exec_isstore) $display(" STORE OP");
`endif
$display("MEM PC=%0d \t INSN=%x", mem_PC, mem_Instr);
$display("WB PC=%0d \t INSN=%x", wb_PC, wb_Instr);
if(mem_out_we)
$display(" WB: R%0d <= %0d", mem_out_reg, wb_out_next);
end
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A211OI_SYMBOL_V
`define SKY130_FD_SC_HDLL__A211OI_SYMBOL_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a211oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A211OI_SYMBOL_V
|
`include "constants.vh"
`include "rv32_opcodes.vh"
module testbench();
parameter CLK_CYCLE_TIME = 50;
parameter IMEM_INTERVAL = 2000;
parameter SIM_CYCLE = 100000000;
parameter SIM_TIME = SIM_CYCLE * CLK_CYCLE_TIME * 2;
reg [31:0] CLK_CYCLE;
reg clk;
reg reset;
initial begin
clk = 0;
forever #CLK_CYCLE_TIME clk = ~clk;
end
initial begin
reset = 0;
#IMEM_INTERVAL reset = 1;
end
initial begin
CLK_CYCLE = 32'h0;
#IMEM_INTERVAL CLK_CYCLE = 32'h0;
end
always @(posedge clk) begin
CLK_CYCLE <= CLK_CYCLE + 1;
end
/*
initial begin
$dumpfile("wave.vcd");
$dumpvars(0, testbench);
end
*/
initial begin
#IMEM_INTERVAL;
#SIM_TIME;
$finish;
end
top rv(
.clk(clk),
.reset_x(reset)
);
integer fp;
integer temp;
integer i, j;
initial begin
//btb, bia init
for (i = 0; i < `BTB_IDX_NUM ; i = i + 1) begin
rv.pipe.pipe_if.brtbl.bia.mem[i] = 0;
rv.pipe.pipe_if.brtbl.bta.mem[i] = 0;
end
for (i = 0; i < `GSH_PHT_NUM ; i = i + 1) begin
rv.pipe.pipe_if.gsh.prhisttbl.pht0.mem[i] = 2;
rv.pipe.pipe_if.gsh.prhisttbl.pht1.mem[i] = 2;
end
fp = $fopen("../bin/init.bin", "rb");
temp = $fread(rv.instmemory.mem, fp);
fp = $fopen("../bin/init.bin", "rb");
temp = $fread(rv.datamemory.mem, fp);
for (i = 0 ; i < 512 ; i = i + 1) begin
j = rv.instmemory.mem[i][7:0];
rv.instmemory.mem[i][7:0] = rv.instmemory.mem[i][31:24];
rv.instmemory.mem[i][31:24] = j;
j = rv.instmemory.mem[i][15:8];
rv.instmemory.mem[i][15:8] = rv.instmemory.mem[i][23:16];
rv.instmemory.mem[i][23:16] = j;
j = rv.instmemory.mem[i][32+7:0+32];
rv.instmemory.mem[i][32+7:0+32]
= rv.instmemory.mem[i][32+31:24+32];
rv.instmemory.mem[i][32+31:24+32] = j;
j = rv.instmemory.mem[i][32+15:8+32];
rv.instmemory.mem[i][32+15:8+32]
= rv.instmemory.mem[i][32+23:16+32];
rv.instmemory.mem[i][32+23:16+32] = j;
j = rv.instmemory.mem[i][64+7:0+64];
rv.instmemory.mem[i][64+7:0+64]
= rv.instmemory.mem[i][64+31:24+64];
rv.instmemory.mem[i][64+31:24+64] = j;
j = rv.instmemory.mem[i][64+15:8+64];
rv.instmemory.mem[i][64+15:8+64]
= rv.instmemory.mem[i][64+23:16+64];
rv.instmemory.mem[i][64+23:16+64] = j;
j = rv.instmemory.mem[i][96+7:0+96];
rv.instmemory.mem[i][96+7:0+96]
= rv.instmemory.mem[i][96+31:24+96];
rv.instmemory.mem[i][96+31:24+96] = j;
j = rv.instmemory.mem[i][96+15:8+96];
rv.instmemory.mem[i][96+15:8+96]
= rv.instmemory.mem[i][96+23:16+96];
rv.instmemory.mem[i][96+23:16+96] = j;
j = rv.instmemory.mem[i][31:0];
rv.instmemory.mem[i][31:0] = rv.instmemory.mem[i][127:96];
rv.instmemory.mem[i][127:96] = j;
j = rv.instmemory.mem[i][63:32];
rv.instmemory.mem[i][63:32] = rv.instmemory.mem[i][95:64];
rv.instmemory.mem[i][95:64] = j;
end
for (i = 0 ; i < 2048 ; i = i + 1) begin
j = rv.datamemory.mem[i][7:0];
rv.datamemory.mem[i][7:0] = rv.datamemory.mem[i][31:24];
rv.datamemory.mem[i][31:24] = j;
j = rv.datamemory.mem[i][15:8];
rv.datamemory.mem[i][15:8] = rv.datamemory.mem[i][23:16];
rv.datamemory.mem[i][23:16] = j;
end
end
integer prmi, prsu, prnum, prcom;
initial begin
prmi = 0;
prsu = 0;
prnum = 0;
prcom = 0;
end
always @ (posedge clk) begin
if (reset && rv.pipe.prmiss) begin
prmi = prmi + 1;
prnum = prnum + 1;
end
if (reset && rv.pipe.prsuccess) begin
prsu = prsu + 1;
prnum = prnum + 1;
end
if (reset && rv.pipe.combranch) begin
prcom = prcom + 1;
end
end
always @ (posedge clk) begin
//Simulation I/OMAP****************************************************
if (rv.dmem_we && rv.dmem_addr == 32'h0) begin
$write("%c", rv.dmem_wdata[7:0]);
end
if (rv.dmem_we && rv.dmem_addr == 32'h4) begin
$write("%d", rv.dmem_wdata);
end
if (rv.dmem_we && rv.dmem_addr == 32'h8) begin
$write("\n%d clks\n", CLK_CYCLE);
/*
$write("stall: %d stall_by_LDST: %d\n", stall, stall_ldst);
$write("stall_by_branch: %d stall_by_prsuccess: %d",
stall_branch, stall_prsuccess);
*/
$write("prnum: %d, prsuccess: %d, prmiss: %d\n (prcom: %d)\n", prnum, prsu, prmi, prcom);
$finish;
end
end // always @ (posedge clk)
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_83x256.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 203 02/05/2008 SP 2 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_83x256 (
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input clock;
input [82:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [82:0] q;
output [7:0] usedw;
wire [7:0] sub_wire0;
wire sub_wire1;
wire [82:0] sub_wire2;
wire sub_wire3;
wire [7:0] usedw = sub_wire0[7:0];
wire empty = sub_wire1;
wire [82:0] q = sub_wire2[82:0];
wire full = sub_wire3;
scfifo scfifo_component (
.rdreq (rdreq),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.q (sub_wire2),
.full (sub_wire3)
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.almost_full (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Cyclone III",
scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M9K",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 83,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "83"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "83"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M9K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "83"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 83 0 INPUT NODEFVAL data[82..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 83 0 OUTPUT NODEFVAL q[82..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL usedw[7..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 83 0 data 0 0 83 0
// Retrieval info: CONNECT: q 0 0 83 0 @q 0 0 83 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_83x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_83x256.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_83x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_83x256.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_83x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_83x256_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_83x256_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_83x256_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1ns/1ps
//`define DEBUG
module top;
parameter length = 34;
parameter str = "%s";
reg [length*8-1:0] result, fmt;
integer val = 1000;
reg [31:0] eval, uval, zval;
reg [63:0] hval, sval;
real rval = 1234.567;
wire net;
time tm = 234567;
realtime rtm = 2345.678;
reg failed;
`ifdef DEBUG
integer lp;
`endif
assign (pull1, strong0) net = 1'b1;
task check_result;
input [length*8-1:0] result, value;
input [80*8-1:0] message;
if (result != value) begin
$display("%0s", message);
$display("Got :%s:", result);
$display("Wanted :%s:", value);
`ifdef DEBUG
for (lp=0; lp<length; lp=lp+1) begin
$display("%d - %d, %d", lp, result[lp*8 +: 8], value[lp*8 +: 8]);
end
`endif
failed = 1;
end
endtask
initial begin
$timeformat(-12, 4, " ps", 20);
fmt = "%s";
failed = 0;
// Determine the endian order.
$swrite(result, "%u", "Help");
if (result != "\000Help") begin
// Big endian so reverse the bytes.
eval = 32'h22000000;
hval = 64'h206d652148656c70;
uval = 32'b010010xz_01100101_01101100_01110000;
zval = 32'b01z01000_0xx0zx0x_0xx01x0z_01x1000z;
sval = " me!Help";
end else begin
// Little endian.
eval = 32'h00000022;
hval = 64'h21656d20706c6548;
uval = 32'b01110000_01101100_01100101_010010xz;
zval = 32'b01x1000z_0xx01x0z_0xx0zx0x_01z01000;
sval = "!em pleH";
end
#1;
// Basic variables and functions.
$swrite(result, val);
check_result(result, " 1000", "Decimal in $swrite failed!");
$swriteb(result, val);
check_result(result, "00000000000000000000001111101000",
"Decimal in $swriteb failed!");
$swriteo(result, val);
check_result(result, "00000001750", "Decimal in $swriteo failed!");
$swriteh(result, val);
check_result(result, "000003e8", "Decimal in $swriteo failed!");
$swrite(result, rval);
check_result(result, "1234.57", "Real in $swrite failed!");
$swrite(result, "Normal string.");
check_result(result, "Normal string.", "String in $swrite failed!");
$swrite(result, tm);
check_result(result, " 234567", "Time in $swrite failed!");
$swrite(result, rtm);
check_result(result, "2345.68", "Real time in $swrite failed!");
$swrite(result, $time);
check_result(result, " 1", "$time in $swrite failed!");
$swrite(result, $stime);
check_result(result, " 1", "$stime in $swrite failed!");
$swrite(result, $simtime);
check_result(result, " 1000", "$simtime in $swrite failed!");
$swrite(result, $realtime);
check_result(result, "1.000", "$realtime in $swrite failed!");
// %% and extra variables.
$swrite(result, "%%",, val);
check_result(result, "% 1000", "% and value in $swrite failed!");
// %b
$swrite(result, "%b", net);
check_result(result, "1", "%b in $swrite failed!");
$swrite(result, "%B", net);
check_result(result, "1", "%b in $swrite failed!");
$swrite(result, "%b", 8'b00001001);
check_result(result, "00001001", "%b in $swrite failed!");
$swrite(result, "%0b", 8'b00001001);
check_result(result, "1001", "%0b in $swrite failed!");
$swrite(result, "%14b", 8'b00001001);
check_result(result, " 00001001", "%14b in $swrite failed!");
$swrite(result, "%-14b", 8'b00001001);
check_result(result, "00001001 ", "%-14b in $swrite failed!");
// %o
$swrite(result, "%o", 8'b00001001);
check_result(result, "011", "%o in $swrite failed!");
$swrite(result, "%O", 8'b00001001);
check_result(result, "011", "%O in $swrite failed!");
$swrite(result, "%0o", 8'b00001001);
check_result(result, "11", "%0o in $swrite failed!");
$swrite(result, "%14o", 8'b00001001);
check_result(result, " 011", "%14o in $swrite failed!");
$swrite(result, "%-14o", 8'b00001001);
check_result(result, "011 ", "%-14o in $swrite failed!");
// %h
$swrite(result, "%h", 8'b00001001);
check_result(result, "09", "%h in $swrite failed!");
$swrite(result, "%H", 8'b00001001);
check_result(result, "09", "%H in $swrite failed!");
$swrite(result, "%0h", 8'b00001001);
check_result(result, "9", "%0h in $swrite failed!");
$swrite(result, "%14h", 8'b00001001);
check_result(result, " 09", "%14h in $swrite failed!");
$swrite(result, "%-14h", 8'b00001001);
check_result(result, "09 ", "%-14h in $swrite failed!");
// %c
$swrite(result, "%c", "abcd");
check_result(result, "d", "%c in $swrite failed!");
$swrite(result, "%C", "abcd");
check_result(result, "d", "%C in $swrite failed!");
$swrite(result, "%4c", "abcd");
check_result(result, " d", "%4c in $swrite failed!");
$swrite(result, "%-4c", "abcd");
check_result(result, "d ", "%-4c in $swrite failed!");
// %d
$swrite(result, "%d", val);
check_result(result, " 1000", "%d in $swrite failed!");
$swrite(result, "%D", val);
check_result(result, " 1000", "%D in $swrite failed!");
$swrite(result, "%d", length);
`ifdef __ICARUS_UNSIZED__
check_result(result, " 34", "%d in $swrite failed!");
`else
check_result(result, " 34", "%d in $swrite failed!");
`endif
$swrite(result, "%d", 31);
`ifdef __ICARUS_UNSIZED__
check_result(result, " 31", "%d in $swrite failed!");
`else
check_result(result, " 31", "%d in $swrite failed!");
`endif
$swrite(result, "%d", $unsigned(31));
`ifdef __ICARUS_UNSIZED__
check_result(result, "31", "%d in $swrite failed!");
`else
check_result(result, " 31", "%d in $swrite failed!");
`endif
$swrite(result, "%0d", val);
check_result(result, "1000", "%0d in $swrite failed!");
$swrite(result, "%+d", val);
check_result(result, " +1000", "%+d in $swrite failed!");
$swrite(result, "%14d", val);
check_result(result, " 1000", "%14d in $swrite failed!");
$swrite(result, "%-14d", val);
check_result(result, "1000 ", "%-14d in $swrite failed!");
// %e
$swrite(result, "%e", rval);
check_result(result, "1.234567e+03", "%e in $swrite failed!");
$swrite(result, "%E", rval);
check_result(result, "1.234567E+03", "%E in $swrite failed!");
$swrite(result, "%+e", rval);
check_result(result, "+1.234567e+03", "%+e in $swrite failed!");
$swrite(result, "%14.3e", rval);
check_result(result, " 1.235e+03", "%14.3e in $swrite failed!");
$swrite(result, "%-14.3e", rval);
check_result(result, "1.235e+03 ", "%-14.3e in $swrite failed!");
// %f
$swrite(result, "%f", rval);
check_result(result, "1234.567000", "%f in $swrite failed!");
$swrite(result, "%F", rval);
check_result(result, "1234.567000", "%F in $swrite failed!");
$swrite(result, "%+f", rval);
check_result(result, "+1234.567000", "%+f in $swrite failed!");
$swrite(result, "%14.3f", rval);
check_result(result, " 1234.567", "%14.3f in $swrite failed!");
$swrite(result, "%-14.3f", rval);
check_result(result, "1234.567 ", "%-14.3f in $swrite failed!");
// %g
$swrite(result, "%g", rval);
check_result(result, "1234.57", "%g in $swrite failed!");
$swrite(result, "%G", rval);
check_result(result, "1234.57", "%G in $swrite failed!");
$swrite(result, "%+g", rval);
check_result(result, "+1234.57", "%+g in $swrite failed!");
$swrite(result, "%14.3g", rval);
check_result(result, " 1.23e+03", "%14.3g in $swrite failed!");
$swrite(result, "%-14.3G", rval);
check_result(result, "1.23E+03 ", "%-14.3G in $swrite failed!");
// %l is currently unsupported.
$swrite(result, "%l");
check_result(result, "<%l>", "%l in $swrite failed!");
$swrite(result, "%L");
check_result(result, "<%L>", "%L in $swrite failed!");
// %m
$swrite(result, "%m");
check_result(result, "top", "%m in $swrite failed!");
$swrite(result, "%M");
check_result(result, "top", "%M in $swrite failed!");
$swrite(result, "%8m");
check_result(result, " top", "%m in $swrite failed!");
$swrite(result, "%-8m");
check_result(result, "top ", "%m in $swrite failed!");
// %s
$swrite(result, "%s", "Hello");
check_result(result, "Hello", "%s in $swrite failed!");
$swrite(result, "%S", "Hello");
check_result(result, "Hello", "%S in $swrite failed!");
$swrite(result, str, "Hello");
check_result(result, "Hello", "%s in $swrite failed!");
$swrite(result, "%14s", "Hello");
check_result(result, " Hello", "%14s in $swrite failed!");
$swrite(result, "%-14s", "Hello");
check_result(result, "Hello ", "%-14s in $swrite failed!");
// %t
$swrite(result, "%t", 0);
check_result(result, " 0.0000 ps", "%t in $swrite failed!");
$swrite(result, "%t", 1);
check_result(result, " 1000.0000 ps", "%t in $swrite failed!");
$swrite(result, "%T", 1);
check_result(result, " 1000.0000 ps", "%T in $swrite failed!");
$swrite(result, "%t", 10_000);
check_result(result, " 10000000.0000 ps", "%t in $swrite failed!");
$swrite(result, "%t", $time);
check_result(result, " 1000.0000 ps", "%t $time in $swrite failed!");
// $swrite(result, "%t", $simtime);
// check_result(result, " 1000.0000 ps",
// "%t $simtime in $swrite failed!");
$swrite(result, "%-t", 1);
check_result(result, "1000.0000 ps ", "%-t in $swrite failed!");
$swrite(result, "%15t", 1);
check_result(result, " 1000.0000 ps", "%15t in $swrite failed!");
$swrite(result, "%-15t", 1);
check_result(result, "1000.0000 ps ", "%-15t in $swrite failed!");
$swrite(result, "%15.1t", 1);
check_result(result, " 1000.0 ps", "%15.1t in $swrite failed!");
// Real values.
$swrite(result, "%t", 1.1);
check_result(result, " 1100.0000 ps", "%t in $swrite failed!");
$swrite(result, "%t", $realtime);
check_result(result, " 1000.0000 ps",
"%t $realtime in $swrite failed!");
$swrite(result, "%-t", 1.1);
check_result(result, "1100.0000 ps ", "%-t in $swrite failed!");
$swrite(result, "%15t", 1.1);
check_result(result, " 1100.0000 ps", "%15t in $swrite failed!");
$swrite(result, "%-15t", 1.1);
check_result(result, "1100.0000 ps ", "%-15t in $swrite failed!");
$swrite(result, "%15.1t", 1.1);
check_result(result, " 1100.0 ps", "%15.1t in $swrite failed!");
// %u
$swrite(result, "%u", eval);
check_result(result, "\"", "%u in $swrite failed!");
$swrite(result, "%U", eval);
check_result(result, "\"", "%U in $swrite failed!");
$swrite(result, "%u", sval);
check_result(result, "Help me!", "%u in $swrite failed!");
// "Help me!"
$swrite(result, "%u", hval);
check_result(result, "Help me!", "%u in $swrite failed!");
// "Help" with check for correct x and z functionality.
$swrite(result, "%u", uval);
check_result(result, "Help", "%u in $swrite failed!");
// %v
$swrite(result, "%v", net);
check_result(result, "Pu1", "%v in $swrite failed!");
$swrite(result, "%V", net);
check_result(result, "Pu1", "%V in $swrite failed!");
$swrite(result, "%14v", net);
check_result(result, " Pu1", "%14v in $swrite failed!");
$swrite(result, "%-14v", net);
check_result(result, "Pu1 ", "%-14v in $swrite failed!");
// %z
$swrite(result, "%z", eval);
check_result(result, "\"", "%z in $swrite failed!");
$swrite(result, "%Z", eval);
check_result(result, "\"", "%Z in $swrite failed!");
// "Help me!", but because of NULLs we only get "Help"
$swrite(result, "%z", hval);
check_result(result, "Help", "%z in $swrite failed!");
// "Help me!" encoded using all the states!
$swrite(result, "%z", zval);
check_result(result, "Help me!", "%z in $swrite failed!");
// $sformat()
$sformat(result, "%s", "Hello world");
check_result(result, "Hello world", "String in $sformat failed!");
$sformat(result, str, "Hello world");
check_result(result, "Hello world", "Parameter in $sformat failed!");
$sformat(result, fmt, "Hello world");
check_result(result, "Hello world", "Register in $sformat failed!");
$sformat(result, "%s");
check_result(result, "<%s>", "$sformat missing argument failed!");
$sformat(result, "%s", "Hello world", 2);
check_result(result, "Hello world", "$sformat extra argument failed!");
if (!failed) $display("All tests passed.");
end
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module TimeHoldOver_Qsys_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "TimeHoldOver_Qsys_onchip_memory2_0.hex";
output [ 31: 0] readdata;
input [ 11: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 2560,
the_altsyncram.numwords_a = 2560,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "M9K",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 12;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
/*
* Milkymist VJ SoC
* Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, version 3 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
module hpdmc #(
parameter csr_addr = 4'h0,
/*
* The depth of the SDRAM array, in bytes.
* Capacity (in bytes) is 2^sdram_depth.
*/
parameter sdram_depth = 26,
/*
* The number of column address bits of the SDRAM.
*/
parameter sdram_columndepth = 9
) (
input sys_clk,
input sys_clk_n,
/*
* Clock used to generate DQS.
* Typically sys_clk phased out by 90 degrees,
* as data is sent synchronously to sys_clk.
*/
input dqs_clk,
input dqs_clk_n,
input sys_rst,
/* Control interface */
input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output [31:0] csr_do,
/* Simple FML 4x64 interface to the memory contents */
input [sdram_depth-1:0] fml_adr,
input fml_stb,
input fml_we,
output fml_ack,
input [7:0] fml_sel,
input [63:0] fml_di,
output [63:0] fml_do,
/* SDRAM interface.
* The SDRAM clock should be driven synchronously to the system clock.
* It is not generated inside this core so you can take advantage of
* architecture-dependent clocking resources to generate a clean
* differential clock.
*/
output reg sdram_cke,
output reg sdram_cs_n,
output reg sdram_we_n,
output reg sdram_cas_n,
output reg sdram_ras_n,
output reg [12:0] sdram_adr,
output reg [1:0] sdram_ba,
output [3:0] sdram_dqm,
inout [31:0] sdram_dq,
inout [3:0] sdram_dqs,
/* Interface to the DCM generating DQS */
output dqs_psen,
output dqs_psincdec,
input dqs_psdone,
input [1:0] pll_stat
);
/* Register all control signals, leaving the possibility to use IOB registers */
wire sdram_cke_r;
wire sdram_cs_n_r;
wire sdram_we_n_r;
wire sdram_cas_n_r;
wire sdram_ras_n_r;
wire [12:0] sdram_adr_r;
wire [1:0] sdram_ba_r;
always @(posedge sys_clk) begin
sdram_cke <= sdram_cke_r;
sdram_cs_n <= sdram_cs_n_r;
sdram_we_n <= sdram_we_n_r;
sdram_cas_n <= sdram_cas_n_r;
sdram_ras_n <= sdram_ras_n_r;
sdram_ba <= sdram_ba_r;
sdram_adr <= sdram_adr_r;
end
/* Mux the control signals according to the "bypass" selection.
* CKE always comes from the control interface.
*/
wire bypass;
wire sdram_cs_n_bypass;
wire sdram_we_n_bypass;
wire sdram_cas_n_bypass;
wire sdram_ras_n_bypass;
wire [12:0] sdram_adr_bypass;
wire [1:0] sdram_ba_bypass;
wire sdram_cs_n_mgmt;
wire sdram_we_n_mgmt;
wire sdram_cas_n_mgmt;
wire sdram_ras_n_mgmt;
wire [12:0] sdram_adr_mgmt;
wire [1:0] sdram_ba_mgmt;
assign sdram_cs_n_r = bypass ? sdram_cs_n_bypass : sdram_cs_n_mgmt;
assign sdram_we_n_r = bypass ? sdram_we_n_bypass : sdram_we_n_mgmt;
assign sdram_cas_n_r = bypass ? sdram_cas_n_bypass : sdram_cas_n_mgmt;
assign sdram_ras_n_r = bypass ? sdram_ras_n_bypass : sdram_ras_n_mgmt;
assign sdram_adr_r = bypass ? sdram_adr_bypass : sdram_adr_mgmt;
assign sdram_ba_r = bypass ? sdram_ba_bypass : sdram_ba_mgmt;
/* Control interface */
wire sdram_rst;
wire [2:0] tim_rp;
wire [2:0] tim_rcd;
wire tim_cas;
wire [10:0] tim_refi;
wire [3:0] tim_rfc;
wire [1:0] tim_wr;
wire idelay_rst;
wire idelay_ce;
wire idelay_inc;
hpdmc_ctlif #(
.csr_addr(csr_addr)
) ctlif (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
.csr_a(csr_a),
.csr_we(csr_we),
.csr_di(csr_di),
.csr_do(csr_do),
.bypass(bypass),
.sdram_rst(sdram_rst),
.sdram_cke(sdram_cke_r),
.sdram_cs_n(sdram_cs_n_bypass),
.sdram_we_n(sdram_we_n_bypass),
.sdram_cas_n(sdram_cas_n_bypass),
.sdram_ras_n(sdram_ras_n_bypass),
.sdram_adr(sdram_adr_bypass),
.sdram_ba(sdram_ba_bypass),
.tim_rp(tim_rp),
.tim_rcd(tim_rcd),
.tim_cas(tim_cas),
.tim_refi(tim_refi),
.tim_rfc(tim_rfc),
.tim_wr(tim_wr),
.idelay_rst(idelay_rst),
.idelay_ce(idelay_ce),
.idelay_inc(idelay_inc),
.dqs_psen(dqs_psen),
.dqs_psincdec(dqs_psincdec),
.dqs_psdone(dqs_psdone),
.pll_stat(pll_stat)
);
/* SDRAM management unit */
wire mgmt_stb;
wire mgmt_we;
wire [sdram_depth-3-1:0] mgmt_address;
wire mgmt_ack;
wire read;
wire write;
wire [3:0] concerned_bank;
wire read_safe;
wire write_safe;
wire [3:0] precharge_safe;
hpdmc_mgmt #(
.sdram_depth(sdram_depth),
.sdram_columndepth(sdram_columndepth)
) mgmt (
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.tim_rp(tim_rp),
.tim_rcd(tim_rcd),
.tim_refi(tim_refi),
.tim_rfc(tim_rfc),
.stb(mgmt_stb),
.we(mgmt_we),
.address(mgmt_address),
.ack(mgmt_ack),
.read(read),
.write(write),
.concerned_bank(concerned_bank),
.read_safe(read_safe),
.write_safe(write_safe),
.precharge_safe(precharge_safe),
.sdram_cs_n(sdram_cs_n_mgmt),
.sdram_we_n(sdram_we_n_mgmt),
.sdram_cas_n(sdram_cas_n_mgmt),
.sdram_ras_n(sdram_ras_n_mgmt),
.sdram_adr(sdram_adr_mgmt),
.sdram_ba(sdram_ba_mgmt)
);
/* Bus interface */
wire data_ack;
hpdmc_busif #(
.sdram_depth(sdram_depth)
) busif (
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.fml_adr(fml_adr),
.fml_stb(fml_stb),
.fml_we(fml_we),
.fml_ack(fml_ack),
.mgmt_stb(mgmt_stb),
.mgmt_we(mgmt_we),
.mgmt_address(mgmt_address),
.mgmt_ack(mgmt_ack),
.data_ack(data_ack)
);
/* Data path controller */
wire direction;
wire direction_r;
hpdmc_datactl datactl(
.sys_clk(sys_clk),
.sdram_rst(sdram_rst),
.read(read),
.write(write),
.concerned_bank(concerned_bank),
.read_safe(read_safe),
.write_safe(write_safe),
.precharge_safe(precharge_safe),
.ack(data_ack),
.direction(direction),
.direction_r(direction_r),
.tim_cas(tim_cas),
.tim_wr(tim_wr)
);
/* Data path */
hpdmc_ddrio ddrio(
.sys_clk(sys_clk),
.sys_clk_n(sys_clk_n),
.dqs_clk(dqs_clk),
.dqs_clk_n(dqs_clk_n),
.direction(direction),
.direction_r(direction_r),
/* Bit meaning is the opposite between
* the FML selection signal and SDRAM DQM pins.
*/
.mo(~fml_sel),
.do(fml_di),
.di(fml_do),
.sdram_dqm(sdram_dqm),
.sdram_dq(sdram_dq),
.sdram_dqs(sdram_dqs),
.idelay_rst(idelay_rst),
.idelay_ce(idelay_ce),
.idelay_inc(idelay_inc)
);
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of m0
//
// Generated
// by: wig
// on: Tue Apr 1 13:31:51 2008
// cmd: /cygdrive/c/eclipse/MIX/mix_0.pl -strip -nodelta ../noassign.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: m0.v,v 1.1 2008/04/01 12:53:30 wig Exp $
// $Date: 2008/04/01 12:53:30 $
// $Log: m0.v,v $
// Revision 1.1 2008/04/01 12:53:30 wig
// Added testcase noassign for optimzeassignport feature
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.108 2007/04/26 06:35:17 wig Exp
//
// Generator: mix_0.pl Revision: 1.47 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of m0
//
// No user `defines in this module
module m0
//
// Generated Module M0
//
(
output reg clk_o,
output reg data_o,
input wire ready0_i,
input wire ready1_i,
output reg clk2_o,
output reg data2_o,
input wire ready2_0,
input wire ready2_1
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of m0
//
//
//!End of Module/s
// --------------------------------------------------------------
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_11_0_axi_basic_rx_pipeline.v
// Version : 1.11
// //
// Description: //
// TRN to AXI RX pipeline. Converts received data from TRN protocol to AXI. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_rx //
// axi_basic_rx_pipeline //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie_7x_v1_11_0_axi_basic_rx_pipeline #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
// AXI RX
//-----------
output reg [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output reg m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output reg [21:0] m_axis_rx_tuser, // RX user signals
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output reg trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// Null Inputs
//-----------
input null_rx_tvalid, // NULL generated tvalid
input null_rx_tlast, // NULL generated tlast
input [KEEP_WIDTH-1:0] null_rx_tkeep, // NULL generated tkeep
input null_rdst_rdy, // NULL generated rdst_rdy
input [4:0] null_is_eof, // NULL generated is_eof
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Wires and regs for creating AXI signals
wire [4:0] is_sof;
wire [4:0] is_sof_prev;
wire [4:0] is_eof;
wire [4:0] is_eof_prev;
reg [KEEP_WIDTH-1:0] reg_tkeep;
wire [KEEP_WIDTH-1:0] tkeep;
wire [KEEP_WIDTH-1:0] tkeep_prev;
reg reg_tlast;
wire rsrc_rdy_filtered;
// Wires and regs for previous value buffer
wire [C_DATA_WIDTH-1:0] trn_rd_DW_swapped;
reg [C_DATA_WIDTH-1:0] trn_rd_prev;
wire data_hold;
reg data_prev;
reg trn_reof_prev;
reg [REM_WIDTH-1:0] trn_rrem_prev;
reg trn_rsrc_rdy_prev;
reg trn_rsrc_dsc_prev;
reg trn_rsof_prev;
reg [6:0] trn_rbar_hit_prev;
reg trn_rerrfwd_prev;
reg trn_recrc_err_prev;
// Null packet handling signals
reg null_mux_sel;
reg trn_in_packet;
wire dsc_flag;
wire dsc_detect;
reg reg_dsc_detect;
reg trn_rsrc_dsc_d;
// Create "filtered" version of rsrc_rdy, where discontinued SOFs are removed.
assign rsrc_rdy_filtered = trn_rsrc_rdy &&
(trn_in_packet || (trn_rsof && !trn_rsrc_dsc));
//----------------------------------------------------------------------------//
// Previous value buffer //
// --------------------- //
// We are inserting a pipeline stage in between TRN and AXI, which causes //
// some issues with handshaking signals m_axis_rx_tready/trn_rdst_rdy. The //
// added cycle of latency in the path causes the user design to fall behind //
// the TRN interface whenever it throttles. //
// //
// To avoid loss of data, we must keep the previous value of all trn_r* //
// signals in case the user throttles. //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
trn_rd_prev <= #TCQ {C_DATA_WIDTH{1'b0}};
trn_rsof_prev <= #TCQ 1'b0;
trn_rrem_prev <= #TCQ {REM_WIDTH{1'b0}};
trn_rsrc_rdy_prev <= #TCQ 1'b0;
trn_rbar_hit_prev <= #TCQ 7'h00;
trn_rerrfwd_prev <= #TCQ 1'b0;
trn_recrc_err_prev <= #TCQ 1'b0;
trn_reof_prev <= #TCQ 1'b0;
trn_rsrc_dsc_prev <= #TCQ 1'b0;
end
else begin
// prev buffer works by checking trn_rdst_rdy. When trn_rdst_rdy is
// asserted, a new value is present on the interface.
if(trn_rdst_rdy) begin
trn_rd_prev <= #TCQ trn_rd_DW_swapped;
trn_rsof_prev <= #TCQ trn_rsof;
trn_rrem_prev <= #TCQ trn_rrem;
trn_rbar_hit_prev <= #TCQ trn_rbar_hit;
trn_rerrfwd_prev <= #TCQ trn_rerrfwd;
trn_recrc_err_prev <= #TCQ trn_recrc_err;
trn_rsrc_rdy_prev <= #TCQ rsrc_rdy_filtered;
trn_reof_prev <= #TCQ trn_reof;
trn_rsrc_dsc_prev <= #TCQ trn_rsrc_dsc || dsc_flag;
end
end
end
//----------------------------------------------------------------------------//
// Create TDATA //
//----------------------------------------------------------------------------//
// Convert TRN data format to AXI data format. AXI is DWORD swapped from TRN
// 128-bit: 64-bit: 32-bit:
// TRN DW0 maps to AXI DW3 TRN DW0 maps to AXI DW1 TNR DW0 maps to AXI DW0
// TRN DW1 maps to AXI DW2 TRN DW1 maps to AXI DW0
// TRN DW2 maps to AXI DW1
// TRN DW3 maps to AXI DW0
generate
if(C_DATA_WIDTH == 128) begin : rd_DW_swap_128
assign trn_rd_DW_swapped = {trn_rd[31:0],
trn_rd[63:32],
trn_rd[95:64],
trn_rd[127:96]};
end
else if(C_DATA_WIDTH == 64) begin : rd_DW_swap_64
assign trn_rd_DW_swapped = {trn_rd[31:0], trn_rd[63:32]};
end
else begin : rd_DW_swap_32
assign trn_rd_DW_swapped = trn_rd;
end
endgenerate
// Create special buffer which locks in the proper value of TDATA depending
// on whether the user is throttling or not. This buffer has three states:
//
// HOLD state: TDATA maintains its current value
// - the user has throttled the PCIe block
// PREVIOUS state: the buffer provides the previous value on trn_rd
// - the user has finished throttling, and is a little behind
// the PCIe block
// CURRENT state: the buffer passes the current value on trn_rd
// - the user is caught up and ready to receive the latest
// data from the PCIe block
always @(posedge user_clk) begin
if(user_rst) begin
m_axis_rx_tdata <= #TCQ {C_DATA_WIDTH{1'b0}};
end
else begin
if(!data_hold) begin
// PREVIOUS state
if(data_prev) begin
m_axis_rx_tdata <= #TCQ trn_rd_prev;
end
// CURRENT state
else begin
m_axis_rx_tdata <= #TCQ trn_rd_DW_swapped;
end
end
// else HOLD state
end
end
// Logic to instruct pipeline to hold its value
assign data_hold = (!m_axis_rx_tready && m_axis_rx_tvalid);
// Logic to instruct pipeline to use previous bus values. Always use previous
// value after holding a value.
always @(posedge user_clk) begin
if(user_rst) begin
data_prev <= #TCQ 1'b0;
end
else begin
data_prev <= #TCQ data_hold;
end
end
//----------------------------------------------------------------------------//
// Create TVALID, TLAST, tkeep, TUSER //
// ----------------------------------- //
// Use the same strategy for these signals as for TDATA, except here we need //
// an extra provision for null packets. //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
m_axis_rx_tvalid <= #TCQ 1'b0;
reg_tlast <= #TCQ 1'b0;
reg_tkeep <= #TCQ {KEEP_WIDTH{1'b1}};
m_axis_rx_tuser <= #TCQ 22'h0;
end
else begin
if(!data_hold) begin
// If in a null packet, use null generated value
if(null_mux_sel) begin
m_axis_rx_tvalid <= #TCQ null_rx_tvalid;
reg_tlast <= #TCQ null_rx_tlast;
reg_tkeep <= #TCQ null_rx_tkeep;
m_axis_rx_tuser <= #TCQ {null_is_eof, 17'h0000};
end
// PREVIOUS state
else if(data_prev) begin
m_axis_rx_tvalid <= #TCQ (trn_rsrc_rdy_prev || dsc_flag);
reg_tlast <= #TCQ trn_reof_prev;
reg_tkeep <= #TCQ tkeep_prev;
m_axis_rx_tuser <= #TCQ {is_eof_prev, // TUSER bits [21:17]
2'b00, // TUSER bits [16:15]
is_sof_prev, // TUSER bits [14:10]
1'b0, // TUSER bit [9]
trn_rbar_hit_prev, // TUSER bits [8:2]
trn_rerrfwd_prev, // TUSER bit [1]
trn_recrc_err_prev}; // TUSER bit [0]
end
// CURRENT state
else begin
m_axis_rx_tvalid <= #TCQ (rsrc_rdy_filtered || dsc_flag);
reg_tlast <= #TCQ trn_reof;
reg_tkeep <= #TCQ tkeep;
m_axis_rx_tuser <= #TCQ {is_eof, // TUSER bits [21:17]
2'b00, // TUSER bits [16:15]
is_sof, // TUSER bits [14:10]
1'b0, // TUSER bit [9]
trn_rbar_hit, // TUSER bits [8:2]
trn_rerrfwd, // TUSER bit [1]
trn_recrc_err}; // TUSER bit [0]
end
end
// else HOLD state
end
end
// Hook up TLAST and tkeep depending on interface width
generate
// For 128-bit interface, don't pass TLAST and tkeep to user (is_eof and
// is_data passed to user instead). reg_tlast is still used internally.
if(C_DATA_WIDTH == 128) begin : tlast_tkeep_hookup_128
assign m_axis_rx_tlast = 1'b0;
assign m_axis_rx_tkeep = {KEEP_WIDTH{1'b1}};
end
// For 64/32-bit interface, pass TLAST to user.
else begin : tlast_tkeep_hookup_64_32
assign m_axis_rx_tlast = reg_tlast;
assign m_axis_rx_tkeep = reg_tkeep;
end
endgenerate
//----------------------------------------------------------------------------//
// Create tkeep //
// ------------ //
// Convert RREM to STRB. Here, we are converting the encoding method for the //
// location of the EOF from TRN flavor (rrem) to AXI (tkeep). //
// //
// NOTE: for each configuration, we need two values of tkeep, the current and //
// previous values. The need for these two values is described below. //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : rrem_to_tkeep_128
// TLAST and tkeep not used in 128-bit interface. is_sof and is_eof used
// instead.
assign tkeep = 16'h0000;
assign tkeep_prev = 16'h0000;
end
else if(C_DATA_WIDTH == 64) begin : rrem_to_tkeep_64
// 64-bit interface: contains 2 DWORDs per cycle, for a total of 8 bytes
// - tkeep has only two possible values here, 0xFF or 0x0F
assign tkeep = trn_rrem ? 8'hFF : 8'h0F;
assign tkeep_prev = trn_rrem_prev ? 8'hFF : 8'h0F;
end
else begin : rrem_to_tkeep_32
// 32-bit interface: contains 1 DWORD per cycle, for a total of 4 bytes
// - tkeep is always 0xF in this case, due to the nature of the PCIe block
assign tkeep = 4'hF;
assign tkeep_prev = 4'hF;
end
endgenerate
//----------------------------------------------------------------------------//
// Create is_sof //
// ------------- //
// is_sof is a signal to the user indicating the location of SOF in TDATA . //
// Due to inherent 64-bit alignment of packets from the block, the only //
// possible values are: //
// Value Valid data widths //
// 5'b11000 (sof @ byte 8) 128 //
// 5'b10000 (sof @ byte 0) 128, 64, 32 //
// 5'b00000 (sof not present) 128, 64, 32 //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : is_sof_128
assign is_sof = {(trn_rsof && !trn_rsrc_dsc), // bit 4: enable
(trn_rsof && !trn_rrem[1]), // bit 3: sof @ byte 8?
3'b000}; // bit 2-0: hardwired 0
assign is_sof_prev = {(trn_rsof_prev && !trn_rsrc_dsc_prev), // bit 4
(trn_rsof_prev && !trn_rrem_prev[1]), // bit 3
3'b000}; // bit 2-0
end
else begin : is_sof_64_32
assign is_sof = {(trn_rsof && !trn_rsrc_dsc), // bit 4: enable
4'b0000}; // bit 3-0: hardwired 0
assign is_sof_prev = {(trn_rsof_prev && !trn_rsrc_dsc_prev), // bit 4
4'b0000}; // bit 3-0
end
endgenerate
//----------------------------------------------------------------------------//
// Create is_eof //
// ------------- //
// is_eof is a signal to the user indicating the location of EOF in TDATA . //
// Due to DWORD granularity of packets from the block, the only //
// possible values are: //
// Value Valid data widths //
// 5'b11111 (eof @ byte 15) 128 //
// 5'b11011 (eof @ byte 11) 128 //
// 5'b10111 (eof @ byte 7) 128, 64 //
// 5'b10011 (eof @ byte 3)` 128, 64, 32 //
// 5'b00011 (eof not present) 128, 64, 32 //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : is_eof_128
assign is_eof = {trn_reof, // bit 4: enable
trn_rrem, // bit 3-2: encoded eof loc rom block
2'b11}; // bit 1-0: hardwired 1
assign is_eof_prev = {trn_reof_prev, // bit 4: enable
trn_rrem_prev, // bit 3-2: encoded eof loc from block
2'b11}; // bit 1-0: hardwired 1
end
else if(C_DATA_WIDTH == 64) begin : is_eof_64
assign is_eof = {trn_reof, // bit 4: enable
1'b0, // bit 3: hardwired 0
trn_rrem, // bit 2: encoded eof loc from block
2'b11}; // bit 1-0: hardwired 1
assign is_eof_prev = {trn_reof_prev, // bit 4: enable
1'b0, // bit 3: hardwired 0
trn_rrem_prev, // bit 2: encoded eof loc from block
2'b11}; // bit 1-0: hardwired 1
end
else begin : is_eof_32
assign is_eof = {trn_reof, // bit 4: enable
4'b0011}; // bit 3-0: hardwired to byte 3
assign is_eof_prev = {trn_reof_prev, // bit 4: enable
4'b0011}; // bit 3-0: hardwired to byte 3
end
endgenerate
//----------------------------------------------------------------------------//
// Create trn_rdst_rdy //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
trn_rdst_rdy <= #TCQ 1'b0;
end
else begin
// If in a null packet, use null generated value
if(null_mux_sel && m_axis_rx_tready) begin
trn_rdst_rdy <= #TCQ null_rdst_rdy;
end
// If a discontinue needs to be serviced, throttle the block until we are
// ready to pad out the packet.
else if(dsc_flag) begin
trn_rdst_rdy <= #TCQ 1'b0;
end
// If in a packet, pass user back-pressure directly to block
else if(m_axis_rx_tvalid) begin
trn_rdst_rdy <= #TCQ m_axis_rx_tready;
end
// If idle, default to no back-pressure. We need to default to the
// "ready to accept data" state to make sure we catch the first
// clock of data of a new packet.
else begin
trn_rdst_rdy <= #TCQ 1'b1;
end
end
end
//----------------------------------------------------------------------------//
// Create null_mux_sel //
// null_mux_sel is the signal used to detect a discontinue situation and //
// mux in the null packet generated in rx_null_gen. Only mux in null data //
// when not at the beginningof a packet. SOF discontinues do not require //
// padding, as the whole packet is simply squashed instead. //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
null_mux_sel <= #TCQ 1'b0;
end
else begin
// NULL packet done
if(null_mux_sel && null_rx_tlast && m_axis_rx_tready)
begin
null_mux_sel <= #TCQ 1'b0;
end
// Discontinue detected and we're in packet, so switch to NULL packet
else if(dsc_flag && !data_hold) begin
null_mux_sel <= #TCQ 1'b1;
end
end
end
//----------------------------------------------------------------------------//
// Create discontinue tracking signals //
//----------------------------------------------------------------------------//
// Create signal trn_in_packet, which is needed to validate trn_rsrc_dsc. We
// should ignore trn_rsrc_dsc when it's asserted out-of-packet.
always @(posedge user_clk) begin
if(user_rst) begin
trn_in_packet <= #TCQ 1'b0;
end
else begin
if(trn_rsof && !trn_reof && rsrc_rdy_filtered && trn_rdst_rdy)
begin
trn_in_packet <= #TCQ 1'b1;
end
else if(trn_rsrc_dsc) begin
trn_in_packet <= #TCQ 1'b0;
end
else if(trn_reof && !trn_rsof && trn_rsrc_rdy && trn_rdst_rdy) begin
trn_in_packet <= #TCQ 1'b0;
end
end
end
// Create dsc_flag, which identifies and stores mid-packet discontinues that
// require null packet padding. This signal is edge sensitive to trn_rsrc_dsc,
// to make sure we don't service the same dsc twice in the event that
// trn_rsrc_dsc stays asserted for longer than it takes to pad out the packet.
assign dsc_detect = trn_rsrc_dsc && !trn_rsrc_dsc_d && trn_in_packet &&
(!trn_rsof || trn_reof) && !(trn_rdst_rdy && trn_reof);
always @(posedge user_clk) begin
if(user_rst) begin
reg_dsc_detect <= #TCQ 1'b0;
trn_rsrc_dsc_d <= #TCQ 1'b0;
end
else begin
if(dsc_detect) begin
reg_dsc_detect <= #TCQ 1'b1;
end
else if(null_mux_sel) begin
reg_dsc_detect <= #TCQ 1'b0;
end
trn_rsrc_dsc_d <= #TCQ trn_rsrc_dsc;
end
end
assign dsc_flag = dsc_detect || reg_dsc_detect;
//----------------------------------------------------------------------------//
// Create np_counter (V6 128-bit only). This counter tells the V6 128-bit //
// interface core how many NP packets have left the RX pipeline. The V6 //
// 128-bit interface uses this count to perform rnp_ok modulation. //
//----------------------------------------------------------------------------//
generate
if(C_FAMILY == "V6" && C_DATA_WIDTH == 128) begin : np_cntr_to_128_enabled
reg [2:0] reg_np_counter;
// Look for NP packets beginning on lower (i.e. unaligned) start
wire mrd_lower = (!(|m_axis_rx_tdata[92:88]) && !m_axis_rx_tdata[94]);
wire mrd_lk_lower = (m_axis_rx_tdata[92:88] == 5'b00001);
wire io_rdwr_lower = (m_axis_rx_tdata[92:88] == 5'b00010);
wire cfg_rdwr_lower = (m_axis_rx_tdata[92:89] == 4'b0010);
wire atomic_lower = ((&m_axis_rx_tdata[91:90]) && m_axis_rx_tdata[94]);
wire np_pkt_lower = (mrd_lower ||
mrd_lk_lower ||
io_rdwr_lower ||
cfg_rdwr_lower ||
atomic_lower) && m_axis_rx_tuser[13];
// Look for NP packets beginning on upper (i.e. aligned) start
wire mrd_upper = (!(|m_axis_rx_tdata[28:24]) && !m_axis_rx_tdata[30]);
wire mrd_lk_upper = (m_axis_rx_tdata[28:24] == 5'b00001);
wire io_rdwr_upper = (m_axis_rx_tdata[28:24] == 5'b00010);
wire cfg_rdwr_upper = (m_axis_rx_tdata[28:25] == 4'b0010);
wire atomic_upper = ((&m_axis_rx_tdata[27:26]) && m_axis_rx_tdata[30]);
wire np_pkt_upper = (mrd_upper ||
mrd_lk_upper ||
io_rdwr_upper ||
cfg_rdwr_upper ||
atomic_upper) && !m_axis_rx_tuser[13];
wire pkt_accepted =
m_axis_rx_tuser[14] && m_axis_rx_tready && m_axis_rx_tvalid;
// Increment counter whenever an NP packet leaves the RX pipeline
always @(posedge user_clk) begin
if (user_rst) begin
reg_np_counter <= #TCQ 0;
end
else begin
if((np_pkt_lower || np_pkt_upper) && pkt_accepted)
begin
reg_np_counter <= #TCQ reg_np_counter + 3'h1;
end
end
end
assign np_counter = reg_np_counter;
end
else begin : np_cntr_to_128_disabled
assign np_counter = 3'h0;
end
endgenerate
endmodule
|
/*
Copyright (c) 2015-2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* I2C master
*/
module i2c_master (
input wire clk,
input wire rst,
/*
* Host interface
*/
input wire [6:0] s_axis_cmd_address,
input wire s_axis_cmd_start,
input wire s_axis_cmd_read,
input wire s_axis_cmd_write,
input wire s_axis_cmd_write_multiple,
input wire s_axis_cmd_stop,
input wire s_axis_cmd_valid,
output wire s_axis_cmd_ready,
input wire [7:0] s_axis_data_tdata,
input wire s_axis_data_tvalid,
output wire s_axis_data_tready,
input wire s_axis_data_tlast,
output wire [7:0] m_axis_data_tdata,
output wire m_axis_data_tvalid,
input wire m_axis_data_tready,
output wire m_axis_data_tlast,
/*
* I2C interface
*/
input wire scl_i,
output wire scl_o,
output wire scl_t,
input wire sda_i,
output wire sda_o,
output wire sda_t,
/*
* Status
*/
output wire busy,
output wire bus_control,
output wire bus_active,
output wire missed_ack,
/*
* Configuration
*/
input wire [15:0] prescale,
input wire stop_on_idle
);
/*
I2C
Read
__ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __
sda \__/_6_X_5_X_4_X_3_X_2_X_1_X_0_\_R___A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A____/
____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
scl ST \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ SP
Write
__ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __
sda \__/_6_X_5_X_4_X_3_X_2_X_1_X_0_/ W \_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_/ N \__/
____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
scl ST \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ SP
Commands:
read
read data byte
set start to force generation of a start condition
start is implied when bus is inactive or active with write or different address
set stop to issue a stop condition after reading current byte
if stop is set with read command, then m_axis_data_tlast will be set
write
write data byte
set start to force generation of a start condition
start is implied when bus is inactive or active with read or different address
set stop to issue a stop condition after writing current byte
write multiple
write multiple data bytes (until s_axis_data_tlast)
set start to force generation of a start condition
start is implied when bus is inactive or active with read or different address
set stop to issue a stop condition after writing block
stop
issue stop condition if bus is active
Status:
busy
module is communicating over the bus
bus_control
module has control of bus in active state
bus_active
bus is active, not necessarily controlled by this module
missed_ack
strobed when a slave ack is missed
Parameters:
prescale
set prescale to 1/4 of the minimum clock period in units
of input clk cycles (prescale = Fclk / (FI2Cclk * 4))
stop_on_idle
automatically issue stop when command input is not valid
Example of interfacing with tristate pins:
(this will work for any tristate bus)
assign scl_i = scl_pin;
assign scl_pin = scl_t ? 1'bz : scl_o;
assign sda_i = sda_pin;
assign sda_pin = sda_t ? 1'bz : sda_o;
Equivalent code that does not use *_t connections:
(we can get away with this because I2C is open-drain)
assign scl_i = scl_pin;
assign scl_pin = scl_o ? 1'bz : 1'b0;
assign sda_i = sda_pin;
assign sda_pin = sda_o ? 1'bz : 1'b0;
Example of two interconnected I2C devices:
assign scl_1_i = scl_1_o & scl_2_o;
assign scl_2_i = scl_1_o & scl_2_o;
assign sda_1_i = sda_1_o & sda_2_o;
assign sda_2_i = sda_1_o & sda_2_o;
Example of two I2C devices sharing the same pins:
assign scl_1_i = scl_pin;
assign scl_2_i = scl_pin;
assign scl_pin = (scl_1_o & scl_2_o) ? 1'bz : 1'b0;
assign sda_1_i = sda_pin;
assign sda_2_i = sda_pin;
assign sda_pin = (sda_1_o & sda_2_o) ? 1'bz : 1'b0;
Notes:
scl_o should not be connected directly to scl_i, only via AND logic or a tristate
I/O pin. This would prevent devices from stretching the clock period.
*/
localparam [4:0]
STATE_IDLE = 4'd0,
STATE_ACTIVE_WRITE = 4'd1,
STATE_ACTIVE_READ = 4'd2,
STATE_START_WAIT = 4'd3,
STATE_START = 4'd4,
STATE_ADDRESS_1 = 4'd5,
STATE_ADDRESS_2 = 4'd6,
STATE_WRITE_1 = 4'd7,
STATE_WRITE_2 = 4'd8,
STATE_WRITE_3 = 4'd9,
STATE_READ = 4'd10,
STATE_STOP = 4'd11;
reg [4:0] state_reg = STATE_IDLE, state_next;
localparam [4:0]
PHY_STATE_IDLE = 5'd0,
PHY_STATE_ACTIVE = 5'd1,
PHY_STATE_REPEATED_START_1 = 5'd2,
PHY_STATE_REPEATED_START_2 = 5'd3,
PHY_STATE_START_1 = 5'd4,
PHY_STATE_START_2 = 5'd5,
PHY_STATE_WRITE_BIT_1 = 5'd6,
PHY_STATE_WRITE_BIT_2 = 5'd7,
PHY_STATE_WRITE_BIT_3 = 5'd8,
PHY_STATE_READ_BIT_1 = 5'd9,
PHY_STATE_READ_BIT_2 = 5'd10,
PHY_STATE_READ_BIT_3 = 5'd11,
PHY_STATE_READ_BIT_4 = 5'd12,
PHY_STATE_STOP_1 = 5'd13,
PHY_STATE_STOP_2 = 5'd14,
PHY_STATE_STOP_3 = 5'd15;
reg [4:0] phy_state_reg = STATE_IDLE, phy_state_next;
reg phy_start_bit;
reg phy_stop_bit;
reg phy_write_bit;
reg phy_read_bit;
reg phy_release_bus;
reg phy_tx_data;
reg phy_rx_data_reg = 1'b0, phy_rx_data_next;
reg [6:0] addr_reg = 7'd0, addr_next;
reg [7:0] data_reg = 8'd0, data_next;
reg last_reg = 1'b0, last_next;
reg mode_read_reg = 1'b0, mode_read_next;
reg mode_write_multiple_reg = 1'b0, mode_write_multiple_next;
reg mode_stop_reg = 1'b0, mode_stop_next;
reg [16:0] delay_reg = 16'd0, delay_next;
reg delay_scl_reg = 1'b0, delay_scl_next;
reg delay_sda_reg = 1'b0, delay_sda_next;
reg [3:0] bit_count_reg = 4'd0, bit_count_next;
reg s_axis_cmd_ready_reg = 1'b0, s_axis_cmd_ready_next;
reg s_axis_data_tready_reg = 1'b0, s_axis_data_tready_next;
reg [7:0] m_axis_data_tdata_reg = 8'd0, m_axis_data_tdata_next;
reg m_axis_data_tvalid_reg = 1'b0, m_axis_data_tvalid_next;
reg m_axis_data_tlast_reg = 1'b0, m_axis_data_tlast_next;
reg scl_i_reg = 1'b1;
reg sda_i_reg = 1'b1;
reg scl_o_reg = 1'b1, scl_o_next;
reg sda_o_reg = 1'b1, sda_o_next;
reg last_scl_i_reg = 1'b1;
reg last_sda_i_reg = 1'b1;
reg busy_reg = 1'b0;
reg bus_active_reg = 1'b0;
reg bus_control_reg = 1'b0, bus_control_next;
reg missed_ack_reg = 1'b0, missed_ack_next;
assign s_axis_cmd_ready = s_axis_cmd_ready_reg;
assign s_axis_data_tready = s_axis_data_tready_reg;
assign m_axis_data_tdata = m_axis_data_tdata_reg;
assign m_axis_data_tvalid = m_axis_data_tvalid_reg;
assign m_axis_data_tlast = m_axis_data_tlast_reg;
assign scl_o = scl_o_reg;
assign scl_t = scl_o_reg;
assign sda_o = sda_o_reg;
assign sda_t = sda_o_reg;
assign busy = busy_reg;
assign bus_active = bus_active_reg;
assign bus_control = bus_control_reg;
assign missed_ack = missed_ack_reg;
wire scl_posedge = scl_i_reg & ~last_scl_i_reg;
wire scl_negedge = ~scl_i_reg & last_scl_i_reg;
wire sda_posedge = sda_i_reg & ~last_sda_i_reg;
wire sda_negedge = ~sda_i_reg & last_sda_i_reg;
wire start_bit = sda_negedge & scl_i_reg;
wire stop_bit = sda_posedge & scl_i_reg;
always @* begin
state_next = STATE_IDLE;
phy_start_bit = 1'b0;
phy_stop_bit = 1'b0;
phy_write_bit = 1'b0;
phy_read_bit = 1'b0;
phy_tx_data = 1'b0;
phy_release_bus = 1'b0;
addr_next = addr_reg;
data_next = data_reg;
last_next = last_reg;
mode_read_next = mode_read_reg;
mode_write_multiple_next = mode_write_multiple_reg;
mode_stop_next = mode_stop_reg;
bit_count_next = bit_count_reg;
s_axis_cmd_ready_next = 1'b0;
s_axis_data_tready_next = 1'b0;
m_axis_data_tdata_next = m_axis_data_tdata_reg;
m_axis_data_tvalid_next = m_axis_data_tvalid_reg & ~m_axis_data_tready;
m_axis_data_tlast_next = m_axis_data_tlast_reg;
missed_ack_next = 1'b0;
// generate delays
if (phy_state_reg != PHY_STATE_IDLE && phy_state_reg != PHY_STATE_ACTIVE) begin
// wait for phy operation
state_next = state_reg;
end else begin
// process states
case (state_reg)
STATE_IDLE: begin
// line idle
s_axis_cmd_ready_next = 1'b1;
if (s_axis_cmd_ready & s_axis_cmd_valid) begin
// command valid
if (s_axis_cmd_read ^ (s_axis_cmd_write | s_axis_cmd_write_multiple)) begin
// read or write command
addr_next = s_axis_cmd_address;
mode_read_next = s_axis_cmd_read;
mode_write_multiple_next = s_axis_cmd_write_multiple;
mode_stop_next = s_axis_cmd_stop;
s_axis_cmd_ready_next = 1'b0;
// start bit
if (bus_active) begin
state_next = STATE_START_WAIT;
end else begin
phy_start_bit = 1'b1;
bit_count_next = 4'd8;
state_next = STATE_ADDRESS_1;
end
end else begin
// invalid or unspecified - ignore
state_next = STATE_IDLE;
end
end else begin
state_next = STATE_IDLE;
end
end
STATE_ACTIVE_WRITE: begin
// line active with current address and read/write mode
s_axis_cmd_ready_next = 1'b1;
if (s_axis_cmd_ready & s_axis_cmd_valid) begin
// command valid
if (s_axis_cmd_read ^ (s_axis_cmd_write | s_axis_cmd_write_multiple)) begin
// read or write command
addr_next = s_axis_cmd_address;
mode_read_next = s_axis_cmd_read;
mode_write_multiple_next = s_axis_cmd_write_multiple;
mode_stop_next = s_axis_cmd_stop;
s_axis_cmd_ready_next = 1'b0;
if (s_axis_cmd_start || s_axis_cmd_address != addr_reg || s_axis_cmd_read) begin
// address or mode mismatch or forced start - repeated start
// repeated start bit
phy_start_bit = 1'b1;
bit_count_next = 4'd8;
state_next = STATE_ADDRESS_1;
end else begin
// address and mode match
// start write
s_axis_data_tready_next = 1'b1;
state_next = STATE_WRITE_1;
end
end else if (s_axis_cmd_stop && !(s_axis_cmd_read || s_axis_cmd_write || s_axis_cmd_write_multiple)) begin
// stop command
phy_stop_bit = 1'b1;
state_next = STATE_IDLE;
end else begin
// invalid or unspecified - ignore
state_next = STATE_ACTIVE_WRITE;
end
end else begin
if (stop_on_idle & s_axis_cmd_ready & ~s_axis_cmd_valid) begin
// no waiting command and stop_on_idle selected, issue stop condition
phy_stop_bit = 1'b1;
state_next = STATE_IDLE;
end else begin
state_next = STATE_ACTIVE_WRITE;
end
end
end
STATE_ACTIVE_READ: begin
// line active to current address
s_axis_cmd_ready_next = ~m_axis_data_tvalid;
if (s_axis_cmd_ready & s_axis_cmd_valid) begin
// command valid
if (s_axis_cmd_read ^ (s_axis_cmd_write | s_axis_cmd_write_multiple)) begin
// read or write command
addr_next = s_axis_cmd_address;
mode_read_next = s_axis_cmd_read;
mode_write_multiple_next = s_axis_cmd_write_multiple;
mode_stop_next = s_axis_cmd_stop;
s_axis_cmd_ready_next = 1'b0;
if (s_axis_cmd_start || s_axis_cmd_address != addr_reg || s_axis_cmd_write) begin
// address or mode mismatch or forced start - repeated start
// write nack for previous read
phy_write_bit = 1'b1;
phy_tx_data = 1'b1;
// repeated start bit
state_next = STATE_START;
end else begin
// address and mode match
// write ack for previous read
phy_write_bit = 1'b1;
phy_tx_data = 1'b0;
// start next read
bit_count_next = 4'd8;
data_next = 8'd0;
state_next = STATE_READ;
end
end else if (s_axis_cmd_stop && !(s_axis_cmd_read || s_axis_cmd_write || s_axis_cmd_write_multiple)) begin
// stop command
// write nack for previous read
phy_write_bit = 1'b1;
phy_tx_data = 1'b1;
// send stop bit
state_next = STATE_STOP;
end else begin
// invalid or unspecified - ignore
state_next = STATE_ACTIVE_READ;
end
end else begin
if (stop_on_idle & s_axis_cmd_ready & ~s_axis_cmd_valid) begin
// no waiting command and stop_on_idle selected, issue stop condition
// write ack for previous read
phy_write_bit = 1'b1;
phy_tx_data = 1'b1;
// send stop bit
state_next = STATE_STOP;
end else begin
state_next = STATE_ACTIVE_READ;
end
end
end
STATE_START_WAIT: begin
// wait for bus idle
if (bus_active) begin
state_next = STATE_START_WAIT;
end else begin
// bus is idle, take control
phy_start_bit = 1'b1;
bit_count_next = 4'd8;
state_next = STATE_ADDRESS_1;
end
end
STATE_START: begin
// send start bit
phy_start_bit = 1'b1;
bit_count_next = 4'd8;
state_next = STATE_ADDRESS_1;
end
STATE_ADDRESS_1: begin
// send address
bit_count_next = bit_count_reg - 1;
if (bit_count_reg > 1) begin
// send address
phy_write_bit = 1'b1;
phy_tx_data = addr_reg[bit_count_reg-2];
state_next = STATE_ADDRESS_1;
end else if (bit_count_reg > 0) begin
// send read/write bit
phy_write_bit = 1'b1;
phy_tx_data = mode_read_reg;
state_next = STATE_ADDRESS_1;
end else begin
// read ack bit
phy_read_bit = 1'b1;
state_next = STATE_ADDRESS_2;
end
end
STATE_ADDRESS_2: begin
// read ack bit
missed_ack_next = phy_rx_data_reg;
if (mode_read_reg) begin
// start read
bit_count_next = 4'd8;
data_next = 1'b0;
state_next = STATE_READ;
end else begin
// start write
s_axis_data_tready_next = 1'b1;
state_next = STATE_WRITE_1;
end
end
STATE_WRITE_1: begin
s_axis_data_tready_next = 1'b1;
if (s_axis_data_tready & s_axis_data_tvalid) begin
// got data, start write
data_next = s_axis_data_tdata;
last_next = s_axis_data_tlast;
bit_count_next = 4'd8;
s_axis_data_tready_next = 1'b0;
state_next = STATE_WRITE_2;
end else begin
// wait for data
state_next = STATE_WRITE_1;
end
end
STATE_WRITE_2: begin
// send data
bit_count_next = bit_count_reg - 1;
if (bit_count_reg > 0) begin
// write data bit
phy_write_bit = 1'b1;
phy_tx_data = data_reg[bit_count_reg-1];
state_next = STATE_WRITE_2;
end else begin
// read ack bit
phy_read_bit = 1'b1;
state_next = STATE_WRITE_3;
end
end
STATE_WRITE_3: begin
// read ack bit
missed_ack_next = phy_rx_data_reg;
if (mode_write_multiple_reg && !last_reg) begin
// more to write
state_next = STATE_WRITE_1;
end else if (mode_stop_reg) begin
// last cycle and stop selected
phy_stop_bit = 1'b1;
state_next = STATE_IDLE;
end else begin
// otherwise, return to bus active state
state_next = STATE_ACTIVE_WRITE;
end
end
STATE_READ: begin
// read data
bit_count_next = bit_count_reg - 1;
data_next = {data_reg[6:0], phy_rx_data_reg};
if (bit_count_reg > 0) begin
// read next bit
phy_read_bit = 1'b1;
state_next = STATE_READ;
end else begin
// output data word
m_axis_data_tdata_next = data_next;
m_axis_data_tvalid_next = 1'b1;
m_axis_data_tlast_next = 1'b0;
if (mode_stop_reg) begin
// send nack and stop
m_axis_data_tlast_next = 1'b1;
phy_write_bit = 1'b1;
phy_tx_data = 1'b1;
state_next = STATE_STOP;
end else begin
// return to bus active state
state_next = STATE_ACTIVE_READ;
end
end
end
STATE_STOP: begin
// send stop bit
phy_stop_bit = 1'b1;
state_next = STATE_IDLE;
end
endcase
end
end
always @* begin
phy_state_next = PHY_STATE_IDLE;
phy_rx_data_next = phy_rx_data_reg;
delay_next = delay_reg;
delay_scl_next = delay_scl_reg;
delay_sda_next = delay_sda_reg;
scl_o_next = scl_o_reg;
sda_o_next = sda_o_reg;
bus_control_next = bus_control_reg;
if (phy_release_bus) begin
// release bus and return to idle state
sda_o_next = 1'b1;
scl_o_next = 1'b1;
delay_scl_next = 1'b0;
delay_sda_next = 1'b0;
delay_next = 1'b0;
phy_state_next = PHY_STATE_IDLE;
end else if (delay_scl_reg) begin
// wait for SCL to match command
delay_scl_next = scl_o_reg & ~scl_i_reg;
phy_state_next = phy_state_reg;
end else if (delay_sda_reg) begin
// wait for SDA to match command
delay_sda_next = sda_o_reg & ~sda_i_reg;
phy_state_next = phy_state_reg;
end else if (delay_reg > 0) begin
// time delay
delay_next = delay_reg - 1;
phy_state_next = phy_state_reg;
end else begin
case (phy_state_reg)
PHY_STATE_IDLE: begin
// bus idle - wait for start command
sda_o_next = 1'b1;
scl_o_next = 1'b1;
if (phy_start_bit) begin
sda_o_next = 1'b0;
delay_next = prescale;
phy_state_next = PHY_STATE_START_1;
end else begin
phy_state_next = PHY_STATE_IDLE;
end
end
PHY_STATE_ACTIVE: begin
// bus active
if (phy_start_bit) begin
sda_o_next = 1'b1;
delay_next = prescale;
phy_state_next = PHY_STATE_REPEATED_START_1;
end else if (phy_write_bit) begin
sda_o_next = phy_tx_data;
delay_next = prescale;
phy_state_next = PHY_STATE_WRITE_BIT_1;
end else if (phy_read_bit) begin
sda_o_next = 1'b1;
delay_next = prescale;
phy_state_next = PHY_STATE_READ_BIT_1;
end else if (phy_stop_bit) begin
sda_o_next = 1'b0;
delay_next = prescale;
phy_state_next = PHY_STATE_STOP_1;
end else begin
phy_state_next = PHY_STATE_ACTIVE;
end
end
PHY_STATE_REPEATED_START_1: begin
// generate repeated start bit
// ______
// sda XXX/ \_______
// _______
// scl ______/ \___
//
scl_o_next = 1'b1;
delay_scl_next = 1'b1;
delay_next = prescale;
phy_state_next = PHY_STATE_REPEATED_START_2;
end
PHY_STATE_REPEATED_START_2: begin
// generate repeated start bit
// ______
// sda XXX/ \_______
// _______
// scl ______/ \___
//
sda_o_next = 1'b0;
delay_next = prescale;
phy_state_next = PHY_STATE_START_1;
end
PHY_STATE_START_1: begin
// generate start bit
// ___
// sda \_______
// _______
// scl \___
//
scl_o_next = 1'b0;
delay_next = prescale;
phy_state_next = PHY_STATE_START_2;
end
PHY_STATE_START_2: begin
// generate start bit
// ___
// sda \_______
// _______
// scl \___
//
bus_control_next = 1'b1;
phy_state_next = PHY_STATE_ACTIVE;
end
PHY_STATE_WRITE_BIT_1: begin
// write bit
// ________
// sda X________X
// ____
// scl __/ \__
scl_o_next = 1'b1;
delay_scl_next = 1'b1;
delay_next = prescale << 1;
phy_state_next = PHY_STATE_WRITE_BIT_2;
end
PHY_STATE_WRITE_BIT_2: begin
// write bit
// ________
// sda X________X
// ____
// scl __/ \__
scl_o_next = 1'b0;
delay_next = prescale;
phy_state_next = PHY_STATE_WRITE_BIT_3;
end
PHY_STATE_WRITE_BIT_3: begin
// write bit
// ________
// sda X________X
// ____
// scl __/ \__
phy_state_next = PHY_STATE_ACTIVE;
end
PHY_STATE_READ_BIT_1: begin
// read bit
// ________
// sda X________X
// ____
// scl __/ \__
scl_o_next = 1'b1;
delay_scl_next = 1'b1;
delay_next = prescale;
phy_state_next = PHY_STATE_READ_BIT_2;
end
PHY_STATE_READ_BIT_2: begin
// read bit
// ________
// sda X________X
// ____
// scl __/ \__
phy_rx_data_next = sda_i_reg;
delay_next = prescale;
phy_state_next = PHY_STATE_READ_BIT_3;
end
PHY_STATE_READ_BIT_3: begin
// read bit
// ________
// sda X________X
// ____
// scl __/ \__
scl_o_next = 1'b0;
delay_next = prescale;
phy_state_next = PHY_STATE_READ_BIT_4;
end
PHY_STATE_READ_BIT_4: begin
// read bit
// ________
// sda X________X
// ____
// scl __/ \__
phy_state_next = PHY_STATE_ACTIVE;
end
PHY_STATE_STOP_1: begin
// stop bit
// ___
// sda XXX\_______/
// _______
// scl _______/
scl_o_next = 1'b1;
delay_scl_next = 1'b1;
delay_next = prescale;
phy_state_next = PHY_STATE_STOP_2;
end
PHY_STATE_STOP_2: begin
// stop bit
// ___
// sda XXX\_______/
// _______
// scl _______/
sda_o_next = 1'b1;
delay_next = prescale;
phy_state_next = PHY_STATE_STOP_3;
end
PHY_STATE_STOP_3: begin
// stop bit
// ___
// sda XXX\_______/
// _______
// scl _______/
bus_control_next = 1'b0;
phy_state_next = PHY_STATE_IDLE;
end
endcase
end
end
always @(posedge clk) begin
state_reg <= state_next;
phy_state_reg <= phy_state_next;
phy_rx_data_reg <= phy_rx_data_next;
addr_reg <= addr_next;
data_reg <= data_next;
last_reg <= last_next;
mode_read_reg <= mode_read_next;
mode_write_multiple_reg <= mode_write_multiple_next;
mode_stop_reg <= mode_stop_next;
delay_reg <= delay_next;
delay_scl_reg <= delay_scl_next;
delay_sda_reg <= delay_sda_next;
bit_count_reg <= bit_count_next;
s_axis_cmd_ready_reg <= s_axis_cmd_ready_next;
s_axis_data_tready_reg <= s_axis_data_tready_next;
m_axis_data_tdata_reg <= m_axis_data_tdata_next;
m_axis_data_tlast_reg <= m_axis_data_tlast_next;
m_axis_data_tvalid_reg <= m_axis_data_tvalid_next;
scl_i_reg <= scl_i;
sda_i_reg <= sda_i;
scl_o_reg <= scl_o_next;
sda_o_reg <= sda_o_next;
last_scl_i_reg <= scl_i_reg;
last_sda_i_reg <= sda_i_reg;
busy_reg <= !(state_reg == STATE_IDLE || state_reg == STATE_ACTIVE_WRITE || state_reg == STATE_ACTIVE_READ) || !(phy_state_reg == PHY_STATE_IDLE || phy_state_reg == PHY_STATE_ACTIVE);
if (start_bit) begin
bus_active_reg <= 1'b1;
end else if (stop_bit) begin
bus_active_reg <= 1'b0;
end else begin
bus_active_reg <= bus_active_reg;
end
bus_control_reg <= bus_control_next;
missed_ack_reg <= missed_ack_next;
if (rst) begin
state_reg <= STATE_IDLE;
phy_state_reg <= PHY_STATE_IDLE;
delay_reg <= 16'd0;
delay_scl_reg <= 1'b0;
delay_sda_reg <= 1'b0;
s_axis_cmd_ready_reg <= 1'b0;
s_axis_data_tready_reg <= 1'b0;
m_axis_data_tvalid_reg <= 1'b0;
scl_o_reg <= 1'b1;
sda_o_reg <= 1'b1;
busy_reg <= 1'b0;
bus_active_reg <= 1'b0;
bus_control_reg <= 1'b0;
missed_ack_reg <= 1'b0;
end
end
endmodule
`resetall
|
// (C) 2001-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_SystemID (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1500011272 : 255;
endmodule
|
module fifo_full_block (/*AUTOARG*/
// Outputs
wr_fifo_full, wr_fifo_progfull, wr_addr, wr_gray_pointer,
// Inputs
reset, wr_clk, wr_rd_gray_pointer, wr_write
);
parameter AW = 2; // Number of bits to access all the entries
//##########
//# INPUTS
//##########
input reset;
input wr_clk;
input [AW:0] wr_rd_gray_pointer;//synced from read domain
input wr_write;
//###########
//# OUTPUTS
//###########
output wr_fifo_full;
output wr_fifo_progfull;//TODO: hack!, fix this properly
//also make, programmable
output [AW-1:0] wr_addr;
output [AW:0] wr_gray_pointer;//for read domain
//#########
//# REGS
//#########
reg [AW:0] wr_gray_pointer;
reg [AW:0] wr_binary_pointer;
reg wr_fifo_full;
//##########
//# WIRES
//##########
wire wr_fifo_full_next;
wire [AW:0] wr_gray_next;
wire [AW:0] wr_binary_next;
wire wr_fifo_progfull_next;
reg wr_fifo_progfull;
//Counter States
always @(posedge wr_clk or posedge reset)
if(reset)
begin
wr_binary_pointer[AW:0] <= {(AW+1){1'b0}};
wr_gray_pointer[AW:0] <= {(AW+1){1'b0}};
end
else if(wr_write)
begin
wr_binary_pointer[AW:0] <= wr_binary_next[AW:0];
wr_gray_pointer[AW:0] <= wr_gray_next[AW:0];
end
//Write Address
assign wr_addr[AW-1:0] = wr_binary_pointer[AW-1:0];
//Updating binary pointer
assign wr_binary_next[AW:0] = wr_binary_pointer[AW:0] +
{{(AW){1'b0}},wr_write};
//Gray Pointer Conversion (for more reliable synchronization)!
assign wr_gray_next[AW:0] = {1'b0,wr_binary_next[AW:1]} ^
wr_binary_next[AW:0];
//FIFO full indication
assign wr_fifo_full_next =
(wr_gray_next[AW-2:0] == wr_rd_gray_pointer[AW-2:0]) &
(wr_gray_next[AW] ^ wr_rd_gray_pointer[AW]) &
(wr_gray_next[AW-1] ^ wr_rd_gray_pointer[AW-1]);
//FIFO almost full
assign wr_fifo_progfull_next =
(wr_gray_next[AW-3:0] == wr_rd_gray_pointer[AW-3:0]) &
(wr_gray_next[AW] ^ wr_rd_gray_pointer[AW]) &
(wr_gray_next[AW-1] ^ wr_rd_gray_pointer[AW-1]) &
(wr_gray_next[AW-2] ^ wr_rd_gray_pointer[AW-2]);
always @ (posedge wr_clk or posedge reset)
if(reset)
wr_fifo_full <= 1'b0;
else
wr_fifo_full <=wr_fifo_full_next;
always @ (posedge wr_clk or posedge reset)
if(reset)
wr_fifo_progfull <= 1'b0;
else
wr_fifo_progfull <=wr_fifo_progfull_next;
endmodule // fifo_full_block
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson, Roman Trogan <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_11_0_pipe_drp.v
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : pipe_drp.v
// Description : PIPE DRP Module for 7 Series Transceiver
// Version : 20.0
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE DRP Module ---------------------------------------------------
module pcie_7x_v1_11_0_pipe_drp #
(
parameter PCIE_GT_DEVICE = "GTX", // PCIe GT device
parameter PCIE_USE_MODE = "3.0", // PCIe use mode
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async mode
parameter PCIE_PLL_SEL = "CPLL", // PCIe PLL select for Gen1/Gen2 only
parameter PCIE_AUX_CDR_GEN3_EN = "TRUE", // PCIe AUX CDR Gen3 enable
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_RXBUF_EN = "TRUE", // PCIe RX buffer enable for Gen3 only
parameter PCIE_TXSYNC_MODE = 0, // PCIe TX sync mode
parameter PCIE_RXSYNC_MODE = 0, // PCIe RX sync mode
parameter LOAD_CNT_MAX = 2'd1, // Load max count
parameter INDEX_MAX = 5'd21 // Index max count
)
(
//---------- Input -------------------------------------
input DRP_CLK,
input DRP_RST_N,
input DRP_GTXRESET,
input [ 1:0] DRP_RATE,
input DRP_X16X20_MODE,
input DRP_X16,
input DRP_START,
input [15:0] DRP_DO,
input DRP_RDY,
//---------- Output ------------------------------------
output [ 8:0] DRP_ADDR,
output DRP_EN,
output [15:0] DRP_DI,
output DRP_WE,
output DRP_DONE,
output [ 2:0] DRP_FSM
);
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gtxreset_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16x20_mode_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg1;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gtxreset_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [ 1:0] rate_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16x20_mode_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg x16_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg start_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] do_reg2;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg rdy_reg2;
//---------- Internal Signals --------------------------
reg [ 1:0] load_cnt = 2'd0;
reg [ 4:0] index = 5'd0;
reg mode = 1'd0;
reg [ 8:0] addr_reg = 9'd0;
reg [15:0] di_reg = 16'd0;
//---------- Output Registers --------------------------
reg done = 1'd0;
reg [ 2:0] fsm = 0;
//---------- DRP Address -------------------------------
// DRP access for *RXCDR_EIDLE includes
// - [11] RXCDR_HOLD_DURING_EIDLE
// - [12] RXCDR_FR_RESET_ON_EIDLE
// - [13] RXCDR_PH_RESET_ON_EIDLE
//------------------------------------------------------
localparam ADDR_PCS_RSVD_ATTR = 9'h06F;
localparam ADDR_TXOUT_DIV = 9'h088;
localparam ADDR_RXOUT_DIV = 9'h088;
localparam ADDR_TX_DATA_WIDTH = 9'h06B;
localparam ADDR_TX_INT_DATAWIDTH = 9'h06B;
localparam ADDR_RX_DATA_WIDTH = 9'h011;
localparam ADDR_RX_INT_DATAWIDTH = 9'h011;
localparam ADDR_TXBUF_EN = 9'h01C;
localparam ADDR_RXBUF_EN = 9'h09D;
localparam ADDR_TX_XCLK_SEL = 9'h059;
localparam ADDR_RX_XCLK_SEL = 9'h059;
localparam ADDR_CLK_CORRECT_USE = 9'h044;
localparam ADDR_TX_DRIVE_MODE = 9'h019;
localparam ADDR_RXCDR_EIDLE = 9'h0A7;
localparam ADDR_RX_DFE_LPM_EIDLE = 9'h01E;
localparam ADDR_PMA_RSV_A = 9'h099;
localparam ADDR_PMA_RSV_B = 9'h09A;
localparam ADDR_RXCDR_CFG_A = 9'h0A8;
localparam ADDR_RXCDR_CFG_B = 9'h0A9;
localparam ADDR_RXCDR_CFG_C = 9'h0AA;
localparam ADDR_RXCDR_CFG_D = 9'h0AB;
localparam ADDR_RXCDR_CFG_E = 9'h0AC;
localparam ADDR_RXCDR_CFG_F = 9'h0AD; // GTH only
//---------- DRP Mask ----------------------------------
localparam MASK_PCS_RSVD_ATTR = 16'b1111111111111001; // Unmask bit [ 2: 1]
localparam MASK_TXOUT_DIV = 16'b1111111110001111; // Unmask bit [ 6: 4]
localparam MASK_RXOUT_DIV = 16'b1111111111111000; // Unmask bit [ 2: 0]
localparam MASK_TX_DATA_WIDTH = 16'b1111111111111000; // Unmask bit [ 2: 0]
localparam MASK_TX_INT_DATAWIDTH = 16'b1111111111101111; // Unmask bit [ 4]
localparam MASK_RX_DATA_WIDTH = 16'b1100011111111111; // Unmask bit [13:11]
localparam MASK_X16X20_RX_DATA_WIDTH = 16'b1111011111111111; // Unmask bit [ 11] // for x16 or x20 mode only
localparam MASK_RX_INT_DATAWIDTH = 16'b1011111111111111; // Unmask bit [ 14]
localparam MASK_TXBUF_EN = 16'b1011111111111111; // Unmask bit [ 14]
localparam MASK_RXBUF_EN = 16'b1111111111111101; // Unmask bit [ 1]
localparam MASK_TX_XCLK_SEL = 16'b1111111101111111; // Unmask bit [ 7]
localparam MASK_RX_XCLK_SEL = 16'b1111111110111111; // Unmask bit [ 6]
localparam MASK_CLK_CORRECT_USE = 16'b1011111111111111; // Unmask bit [ 14]
localparam MASK_TX_DRIVE_MODE = 16'b1111111111100000; // Unmask bit [ 4:0]
localparam MASK_RXCDR_EIDLE = 16'b1111011111111111; // Unmask bit [ 11]
localparam MASK_RX_DFE_LPM_EIDLE = 16'b1011111111111111; // Unmask bit [ 14]
localparam MASK_PMA_RSV_A = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_PMA_RSV_B = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_A = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_B = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_C = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_D = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_E_GTX = 16'b1111111100000000; // Unmask bit [ 7: 0]
localparam MASK_RXCDR_CFG_E_GTH = 16'b0000000000000000; // Unmask bit [15: 0]
localparam MASK_RXCDR_CFG_F_GTX = 16'b1111111111111111; // Unmask bit [ ]
localparam MASK_RXCDR_CFG_F_GTH = 16'b1111111111111000; // Unmask bit [ 2: 0]
//---------- DRP Data for PCIe Gen1 and Gen2 -----------
localparam GEN12_TXOUT_DIV = (PCIE_PLL_SEL == "QPLL") ? 16'b0000000000100000 : 16'b0000000000010000; // Divide by 4 or 2
localparam GEN12_RXOUT_DIV = (PCIE_PLL_SEL == "QPLL") ? 16'b0000000000000010 : 16'b0000000000000001; // Divide by 4 or 2
localparam GEN12_TX_DATA_WIDTH = 16'b0000000000000011; // 2-byte (16-bit) external data width
localparam GEN12_TX_INT_DATAWIDTH = 16'b0000000000000000; // 2-byte (20-bit) internal data width
localparam GEN12_RX_DATA_WIDTH = 16'b0001100000000000; // 2-byte (16-bit) external data width
localparam GEN12_RX_INT_DATAWIDTH = 16'b0000000000000000; // 2-byte (20-bit) internal data width
localparam GEN12_TXBUF_EN = 16'b0100000000000000; // Use TX buffer if PCIE_TXBUF_EN == "TRUE"
localparam GEN12_RXBUF_EN = 16'b0000000000000010; // Use RX buffer
localparam GEN12_TX_XCLK_SEL = 16'b0000000000000000; // Use TXOUT if PCIE_TXBUF_EN == "TRUE"
localparam GEN12_RX_XCLK_SEL = 16'b0000000000000000; // Use RXREC
localparam GEN12_CLK_CORRECT_USE = 16'b0100000000000000; // Use clock correction
localparam GEN12_TX_DRIVE_MODE = 16'b0000000000000001; // Use PIPE Gen1 and Gen2 mode
localparam GEN12_RXCDR_EIDLE = 16'b0000100000000000; // Hold RXCDR during electrical idle
localparam GEN12_RX_DFE_LPM_EIDLE = 16'b0100000000000000; // Hold RX DFE or LPM during electrical idle
localparam GEN12_PMA_RSV_A_GTX = 16'b1000010010000000; // 16'h8480
localparam GEN12_PMA_RSV_B_GTX = 16'b0000000000000001; // 16'h0001
localparam GEN12_PMA_RSV_A_GTH = 16'b0000000000001000; // 16'h0008
localparam GEN12_PMA_RSV_B_GTH = 16'b0000000000000000; // 16'h0000
//----------
localparam GEN12_RXCDR_CFG_A_GTX = 16'h0020; // 16'h0020
localparam GEN12_RXCDR_CFG_B_GTX = 16'h1020; // 16'h1020
localparam GEN12_RXCDR_CFG_C_GTX = 16'h23FF; // 16'h23FF
localparam GEN12_RXCDR_CFG_D_GTX_S = 16'h0000; // 16'h0000 Sync
localparam GEN12_RXCDR_CFG_D_GTX_A = 16'h8000; // 16'h8000 Async
localparam GEN12_RXCDR_CFG_E_GTX = 16'h0003; // 16'h0003
localparam GEN12_RXCDR_CFG_F_GTX = 16'h0000; // 16'h0000
//----------
localparam GEN12_RXCDR_CFG_A_GTH_S = 16'h0018; // 16'h0018 Sync
localparam GEN12_RXCDR_CFG_A_GTH_A = 16'h8018; // 16'h8018 Async
localparam GEN12_RXCDR_CFG_B_GTH = 16'hC208; // 16'hC208
localparam GEN12_RXCDR_CFG_C_GTH = 16'h2000; // 16'h2000
localparam GEN12_RXCDR_CFG_D_GTH = 16'h07FE; // 16'h07FE
localparam GEN12_RXCDR_CFG_E_GTH = 16'h0020; // 16'h0020
localparam GEN12_RXCDR_CFG_F_GTH = 16'h0000; // 16'h0000
//---------- DRP Data for PCIe Gen3 --------------------
localparam GEN3_TXOUT_DIV = 16'b0000000000000000; // Divide by 1
localparam GEN3_RXOUT_DIV = 16'b0000000000000000; // Divide by 1
localparam GEN3_TX_DATA_WIDTH = 16'b0000000000000100; // 4-byte (32-bit) external data width
localparam GEN3_TX_INT_DATAWIDTH = 16'b0000000000010000; // 4-byte (32-bit) internal data width
localparam GEN3_RX_DATA_WIDTH = 16'b0010000000000000; // 4-byte (32-bit) external data width
localparam GEN3_RX_INT_DATAWIDTH = 16'b0100000000000000; // 4-byte (32-bit) internal data width
localparam GEN3_TXBUF_EN = 16'b0000000000000000; // Bypass TX buffer
localparam GEN3_RXBUF_EN = 16'b0000000000000000; // Bypass RX buffer
localparam GEN3_TX_XCLK_SEL = 16'b0000000010000000; // Use TXUSR
localparam GEN3_RX_XCLK_SEL = 16'b0000000001000000; // Use RXUSR
localparam GEN3_CLK_CORRECT_USE = 16'b0000000000000000; // Bypass clock correction
localparam GEN3_TX_DRIVE_MODE = 16'b0000000000000010; // Use PIPE Gen3 mode
localparam GEN3_RXCDR_EIDLE = 16'b0000000000000000; // Disable Hold RXCDR during electrical idle
localparam GEN3_RX_DFE_LPM_EIDLE = 16'b0000000000000000; // Disable RX DFE or LPM during electrical idle
localparam GEN3_PMA_RSV_A_GTX = 16'b0111000010000000; // 16'h7080
localparam GEN3_PMA_RSV_B_GTX = 16'b0000000000011110; // 16'h001E
localparam GEN3_PMA_RSV_A_GTH = 16'b0000000000001000; // 16'h0008
localparam GEN3_PMA_RSV_B_GTH = 16'b0000000000000000; // 16'h0000
//----------
localparam GEN3_RXCDR_CFG_A_GTX = 16'h0080; // 16'h0080
localparam GEN3_RXCDR_CFG_B_GTX = 16'h1010; // 16'h1010
localparam GEN3_RXCDR_CFG_C_GTX = 16'h0BFF; // 16'h0BFF
localparam GEN3_RXCDR_CFG_D_GTX_S = 16'h0000; // 16'h0000 Sync
localparam GEN3_RXCDR_CFG_D_GTX_A = 16'h8000; // 16'h8000 Async
localparam GEN3_RXCDR_CFG_E_GTX = 16'h000B; // 16'h000B
localparam GEN3_RXCDR_CFG_F_GTX = 16'h0000; // 16'h0000
//----------
//localparam GEN3_RXCDR_CFG_A_GTH_S = 16'h0018; // 16'h0018 Sync
//localparam GEN3_RXCDR_CFG_A_GTH_A = 16'h8018; // 16'h8018 Async
//localparam GEN3_RXCDR_CFG_B_GTH = 16'hC208; // 16'hC848
//localparam GEN3_RXCDR_CFG_C_GTH = 16'h2000; // 16'h1000
//localparam GEN3_RXCDR_CFG_D_GTH = 16'h07FE; // 16'h07FE v1.0 silicon
//localparam GEN3_RXCDR_CFG_D_GTH_AUX = 16'h0FFE; // 16'h07FE v2.0 silicon, [62:59] AUX CDR configuration
//localparam GEN3_RXCDR_CFG_E_GTH = 16'h0020; // 16'h0010
//localparam GEN3_RXCDR_CFG_F_GTH = 16'h0000; // 16'h0000 v1.0 silicon
//localparam GEN3_RXCDR_CFG_F_GTH_AUX = 16'h0002; // 16'h0000 v2.0 silicon, [81] AUX CDR enable
//----------
localparam GEN3_RXCDR_CFG_A_GTH_S = 16'h0018; // 16'h0018 Sync
localparam GEN3_RXCDR_CFG_A_GTH_A = 16'h8018; // 16'h8018 Async
localparam GEN3_RXCDR_CFG_B_GTH = 16'hC848; // 16'hC848
localparam GEN3_RXCDR_CFG_C_GTH = 16'h1000; // 16'h1000
localparam GEN3_RXCDR_CFG_D_GTH = 16'h07FE; // 16'h07FE v1.0 silicon
localparam GEN3_RXCDR_CFG_D_GTH_AUX = 16'h0FFE; // 16'h07FE v2.0 silicon, [62:59] AUX CDR configuration
localparam GEN3_RXCDR_CFG_E_GTH = 16'h0010; // 16'h0010
localparam GEN3_RXCDR_CFG_F_GTH = 16'h0000; // 16'h0000 v1.0 silicon
localparam GEN3_RXCDR_CFG_F_GTH_AUX = 16'h0002; // 16'h0000 v2.0 silicon, [81] AUX CDR enable
//---------- DRP Data for PCIe Gen1, Gen2 and Gen3 -----
localparam GEN123_PCS_RSVD_ATTR_A = 16'b0000000000000000; // Auto TX and RX sync mode
localparam GEN123_PCS_RSVD_ATTR_M_TX = 16'b0000000000000010; // Manual TX sync mode
localparam GEN123_PCS_RSVD_ATTR_M_RX = 16'b0000000000000100; // Manual RX sync mode
//---------- DRP Data for x16 --------------------------
localparam X16_RX_DATAWIDTH = 16'b0000000000000000; // 2-byte (16-bit) internal data width
//---------- DRP Data for x20 --------------------------
localparam X20_RX_DATAWIDTH = 16'b0000100000000000; // 2-byte (20-bit) internal data width
//---------- DRP Data ----------------------------------
wire [15:0] data_txout_div;
wire [15:0] data_rxout_div;
wire [15:0] data_tx_data_width;
wire [15:0] data_tx_int_datawidth;
wire [15:0] data_rx_data_width;
wire [15:0] data_rx_int_datawidth;
wire [15:0] data_txbuf_en;
wire [15:0] data_rxbuf_en;
wire [15:0] data_tx_xclk_sel;
wire [15:0] data_rx_xclk_sel;
wire [15:0] data_clk_correction_use;
wire [15:0] data_tx_drive_mode;
wire [15:0] data_rxcdr_eidle;
wire [15:0] data_rx_dfe_lpm_eidle;
wire [15:0] data_pma_rsv_a;
wire [15:0] data_pma_rsv_b;
wire [15:0] data_rxcdr_cfg_a;
wire [15:0] data_rxcdr_cfg_b;
wire [15:0] data_rxcdr_cfg_c;
wire [15:0] data_rxcdr_cfg_d;
wire [15:0] data_rxcdr_cfg_e;
wire [15:0] data_rxcdr_cfg_f;
wire [15:0] data_pcs_rsvd_attr_a;
wire [15:0] data_pcs_rsvd_attr_m_tx;
wire [15:0] data_pcs_rsvd_attr_m_rx;
wire [15:0] data_pcs_rsvd_attr_m;
wire [15:0] data_x16x20_rx_datawidth;
//---------- FSM ---------------------------------------
localparam FSM_IDLE = 0;
localparam FSM_LOAD = 1;
localparam FSM_READ = 2;
localparam FSM_RRDY = 3;
localparam FSM_WRITE = 4;
localparam FSM_WRDY = 5;
localparam FSM_DONE = 6;
//---------- Input FF ----------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
//---------- 1st Stage FF --------------------------
gtxreset_reg1 <= 1'd0;
rate_reg1 <= 2'd0;
x16x20_mode_reg1 <= 1'd0;
x16_reg1 <= 1'd0;
do_reg1 <= 16'd0;
rdy_reg1 <= 1'd0;
start_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
gtxreset_reg2 <= 1'd0;
rate_reg2 <= 2'd0;
x16x20_mode_reg2 <= 1'd0;
x16_reg2 <= 1'd0;
do_reg2 <= 16'd0;
rdy_reg2 <= 1'd0;
start_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
gtxreset_reg1 <= DRP_GTXRESET;
rate_reg1 <= DRP_RATE;
x16x20_mode_reg1 <= DRP_X16X20_MODE;
x16_reg1 <= DRP_X16;
do_reg1 <= DRP_DO;
rdy_reg1 <= DRP_RDY;
start_reg1 <= DRP_START;
//---------- 2nd Stage FF --------------------------
gtxreset_reg2 <= gtxreset_reg1;
rate_reg2 <= rate_reg1;
x16x20_mode_reg2 <= x16x20_mode_reg1;
x16_reg2 <= x16_reg1;
do_reg2 <= do_reg1;
rdy_reg2 <= rdy_reg1;
start_reg2 <= start_reg1;
end
end
//---------- Select DRP Data ---------------------------------------------------
assign data_txout_div = (rate_reg2 == 2'd2) ? GEN3_TXOUT_DIV : GEN12_TXOUT_DIV;
assign data_rxout_div = (rate_reg2 == 2'd2) ? GEN3_RXOUT_DIV : GEN12_RXOUT_DIV;
assign data_tx_data_width = (rate_reg2 == 2'd2) ? GEN3_TX_DATA_WIDTH : GEN12_TX_DATA_WIDTH;
assign data_tx_int_datawidth = (rate_reg2 == 2'd2) ? GEN3_TX_INT_DATAWIDTH : GEN12_TX_INT_DATAWIDTH;
assign data_rx_data_width = (rate_reg2 == 2'd2) ? GEN3_RX_DATA_WIDTH : GEN12_RX_DATA_WIDTH;
assign data_rx_int_datawidth = (rate_reg2 == 2'd2) ? GEN3_RX_INT_DATAWIDTH : GEN12_RX_INT_DATAWIDTH;
assign data_txbuf_en = ((rate_reg2 == 2'd2) || (PCIE_TXBUF_EN == "FALSE")) ? GEN3_TXBUF_EN : GEN12_TXBUF_EN;
assign data_rxbuf_en = ((rate_reg2 == 2'd2) && (PCIE_RXBUF_EN == "FALSE")) ? GEN3_RXBUF_EN : GEN12_RXBUF_EN;
assign data_tx_xclk_sel = ((rate_reg2 == 2'd2) || (PCIE_TXBUF_EN == "FALSE")) ? GEN3_TX_XCLK_SEL : GEN12_TX_XCLK_SEL;
assign data_rx_xclk_sel = ((rate_reg2 == 2'd2) && (PCIE_RXBUF_EN == "FALSE")) ? GEN3_RX_XCLK_SEL : GEN12_RX_XCLK_SEL;
assign data_clk_correction_use = (rate_reg2 == 2'd2) ? GEN3_CLK_CORRECT_USE : GEN12_CLK_CORRECT_USE;
assign data_tx_drive_mode = (rate_reg2 == 2'd2) ? GEN3_TX_DRIVE_MODE : GEN12_TX_DRIVE_MODE;
assign data_rxcdr_eidle = (rate_reg2 == 2'd2) ? GEN3_RXCDR_EIDLE : GEN12_RXCDR_EIDLE;
assign data_rx_dfe_lpm_eidle = (rate_reg2 == 2'd2) ? GEN3_RX_DFE_LPM_EIDLE : GEN12_RX_DFE_LPM_EIDLE;
assign data_pma_rsv_a = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_PMA_RSV_A_GTH : GEN3_PMA_RSV_A_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_PMA_RSV_A_GTH : GEN12_PMA_RSV_A_GTX);
assign data_pma_rsv_b = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_PMA_RSV_B_GTH : GEN3_PMA_RSV_B_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_PMA_RSV_B_GTH : GEN12_PMA_RSV_B_GTX);
assign data_rxcdr_cfg_a = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? ((PCIE_ASYNC_EN == "TRUE") ? GEN3_RXCDR_CFG_A_GTH_A : GEN3_RXCDR_CFG_A_GTH_S) : GEN3_RXCDR_CFG_A_GTX) :
((PCIE_GT_DEVICE == "GTH") ? ((PCIE_ASYNC_EN == "TRUE") ? GEN12_RXCDR_CFG_A_GTH_A : GEN12_RXCDR_CFG_A_GTH_S) : GEN12_RXCDR_CFG_A_GTX);
assign data_rxcdr_cfg_b = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_RXCDR_CFG_B_GTH : GEN3_RXCDR_CFG_B_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_B_GTH : GEN12_RXCDR_CFG_B_GTX);
assign data_rxcdr_cfg_c = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_RXCDR_CFG_C_GTH : GEN3_RXCDR_CFG_C_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_C_GTH : GEN12_RXCDR_CFG_C_GTX);
assign data_rxcdr_cfg_d = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? ((PCIE_AUX_CDR_GEN3_EN == "TRUE") ? GEN3_RXCDR_CFG_D_GTH_AUX : GEN3_RXCDR_CFG_D_GTH) : ((PCIE_ASYNC_EN == "TRUE") ? GEN3_RXCDR_CFG_D_GTX_A : GEN3_RXCDR_CFG_D_GTX_S)) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_D_GTH : ((PCIE_ASYNC_EN == "TRUE") ? GEN3_RXCDR_CFG_D_GTX_A : GEN3_RXCDR_CFG_D_GTX_S));
assign data_rxcdr_cfg_e = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? GEN3_RXCDR_CFG_E_GTH : GEN3_RXCDR_CFG_E_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_E_GTH : GEN12_RXCDR_CFG_E_GTX);
assign data_rxcdr_cfg_f = (rate_reg2 == 2'd2) ? ((PCIE_GT_DEVICE == "GTH") ? ((PCIE_AUX_CDR_GEN3_EN == "TRUE") ? GEN3_RXCDR_CFG_F_GTH_AUX : GEN3_RXCDR_CFG_F_GTH) : GEN3_RXCDR_CFG_F_GTX) :
((PCIE_GT_DEVICE == "GTH") ? GEN12_RXCDR_CFG_F_GTH : GEN12_RXCDR_CFG_F_GTX);
assign data_pcs_rsvd_attr_a = GEN123_PCS_RSVD_ATTR_A;
assign data_pcs_rsvd_attr_m_tx = PCIE_TXSYNC_MODE ? GEN123_PCS_RSVD_ATTR_A : GEN123_PCS_RSVD_ATTR_M_TX;
assign data_pcs_rsvd_attr_m_rx = PCIE_RXSYNC_MODE ? GEN123_PCS_RSVD_ATTR_A : GEN123_PCS_RSVD_ATTR_M_RX;
assign data_pcs_rsvd_attr_m = data_pcs_rsvd_attr_m_tx | data_pcs_rsvd_attr_m_rx;
assign data_x16x20_rx_datawidth = x16_reg2 ? X16_RX_DATAWIDTH : X20_RX_DATAWIDTH;
//---------- Load Counter ------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
load_cnt <= 2'd0;
else
//---------- Increment Load Counter ----------------
if ((fsm == FSM_LOAD) && (load_cnt < LOAD_CNT_MAX))
load_cnt <= load_cnt + 2'd1;
//---------- Hold Load Counter ---------------------
else if ((fsm == FSM_LOAD) && (load_cnt == LOAD_CNT_MAX))
load_cnt <= load_cnt;
//---------- Reset Load Counter --------------------
else
load_cnt <= 2'd0;
end
//---------- Update DRP Address and Data ---------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
addr_reg <= 9'd0;
di_reg <= 16'd0;
end
else
begin
case (index)
//--------------------------------------------------
5'd0:
begin
addr_reg <= mode ? ADDR_PCS_RSVD_ATTR :
x16x20_mode_reg2 ? ADDR_RX_DATA_WIDTH : ADDR_TXOUT_DIV;
di_reg <= mode ? ((do_reg2 & MASK_PCS_RSVD_ATTR) | data_pcs_rsvd_attr_a) :
x16x20_mode_reg2 ? ((do_reg2 & MASK_X16X20_RX_DATA_WIDTH) | data_x16x20_rx_datawidth) :
((do_reg2 & MASK_TXOUT_DIV) | data_txout_div);
end
//--------------------------------------------------
5'd1:
begin
addr_reg <= mode ? ADDR_PCS_RSVD_ATTR : ADDR_RXOUT_DIV;
di_reg <= mode ? ((do_reg2 & MASK_PCS_RSVD_ATTR) | data_pcs_rsvd_attr_m) :
((do_reg2 & MASK_RXOUT_DIV) | data_rxout_div);
end
//--------------------------------------------------
5'd2 :
begin
addr_reg <= ADDR_TX_DATA_WIDTH;
di_reg <= (do_reg2 & MASK_TX_DATA_WIDTH) | data_tx_data_width;
end
//--------------------------------------------------
5'd3 :
begin
addr_reg <= ADDR_TX_INT_DATAWIDTH;
di_reg <= (do_reg2 & MASK_TX_INT_DATAWIDTH) | data_tx_int_datawidth;
end
//--------------------------------------------------
5'd4 :
begin
addr_reg <= ADDR_RX_DATA_WIDTH;
di_reg <= (do_reg2 & MASK_RX_DATA_WIDTH) | data_rx_data_width;
end
//--------------------------------------------------
5'd5 :
begin
addr_reg <= ADDR_RX_INT_DATAWIDTH;
di_reg <= (do_reg2 & MASK_RX_INT_DATAWIDTH) | data_rx_int_datawidth;
end
//--------------------------------------------------
5'd6 :
begin
addr_reg <= ADDR_TXBUF_EN;
di_reg <= (do_reg2 & MASK_TXBUF_EN) | data_txbuf_en;
end
//--------------------------------------------------
5'd7 :
begin
addr_reg <= ADDR_RXBUF_EN;
di_reg <= (do_reg2 & MASK_RXBUF_EN) | data_rxbuf_en;
end
//--------------------------------------------------
5'd8 :
begin
addr_reg <= ADDR_TX_XCLK_SEL;
di_reg <= (do_reg2 & MASK_TX_XCLK_SEL) | data_tx_xclk_sel;
end
//--------------------------------------------------
5'd9 :
begin
addr_reg <= ADDR_RX_XCLK_SEL;
di_reg <= (do_reg2 & MASK_RX_XCLK_SEL) | data_rx_xclk_sel;
end
//--------------------------------------------------
5'd10 :
begin
addr_reg <= ADDR_CLK_CORRECT_USE;
di_reg <= (do_reg2 & MASK_CLK_CORRECT_USE) | data_clk_correction_use;
end
//--------------------------------------------------
5'd11 :
begin
addr_reg <= ADDR_TX_DRIVE_MODE;
di_reg <= (do_reg2 & MASK_TX_DRIVE_MODE) | data_tx_drive_mode;
end
//--------------------------------------------------
5'd12 :
begin
addr_reg <= ADDR_RXCDR_EIDLE;
di_reg <= (do_reg2 & MASK_RXCDR_EIDLE) | data_rxcdr_eidle;
end
//--------------------------------------------------
5'd13 :
begin
addr_reg <= ADDR_RX_DFE_LPM_EIDLE;
di_reg <= (do_reg2 & MASK_RX_DFE_LPM_EIDLE) | data_rx_dfe_lpm_eidle;
end
//--------------------------------------------------
5'd14 :
begin
addr_reg <= ADDR_PMA_RSV_A;
di_reg <= (do_reg2 & MASK_PMA_RSV_A) | data_pma_rsv_a;
end
//--------------------------------------------------
5'd15 :
begin
addr_reg <= ADDR_PMA_RSV_B;
di_reg <= (do_reg2 & MASK_PMA_RSV_B) | data_pma_rsv_b;
end
//--------------------------------------------------
5'd16 :
begin
addr_reg <= ADDR_RXCDR_CFG_A;
di_reg <= (do_reg2 & MASK_RXCDR_CFG_A) | data_rxcdr_cfg_a;
end
//--------------------------------------------------
5'd17 :
begin
addr_reg <= ADDR_RXCDR_CFG_B;
di_reg <= (do_reg2 & MASK_RXCDR_CFG_B) | data_rxcdr_cfg_b;
end
//--------------------------------------------------
5'd18 :
begin
addr_reg <= ADDR_RXCDR_CFG_C;
di_reg <= (do_reg2 & MASK_RXCDR_CFG_C) | data_rxcdr_cfg_c;
end
//--------------------------------------------------
5'd19 :
begin
addr_reg <= ADDR_RXCDR_CFG_D;
di_reg <= (do_reg2 & MASK_RXCDR_CFG_D) | data_rxcdr_cfg_d;
end
//--------------------------------------------------
5'd20 :
begin
addr_reg <= ADDR_RXCDR_CFG_E;
di_reg <= (do_reg2 & ((PCIE_GT_DEVICE == "GTH") ? MASK_RXCDR_CFG_E_GTH : MASK_RXCDR_CFG_E_GTX)) | data_rxcdr_cfg_e;
end
//--------------------------------------------------
5'd21 :
begin
addr_reg <= ADDR_RXCDR_CFG_F;
di_reg <= (do_reg2 & ((PCIE_GT_DEVICE == "GTH") ? MASK_RXCDR_CFG_F_GTH : MASK_RXCDR_CFG_F_GTX)) | data_rxcdr_cfg_f;
end
//--------------------------------------------------
default :
begin
addr_reg <= 9'd0;
di_reg <= 16'd0;
end
endcase
end
end
//---------- PIPE DRP FSM ------------------------------------------------------
always @ (posedge DRP_CLK)
begin
if (!DRP_RST_N)
begin
fsm <= FSM_IDLE;
index <= 5'd0;
mode <= 1'd0;
done <= 1'd0;
end
else
begin
case (fsm)
//---------- Idle State ----------------------------
FSM_IDLE :
begin
//---------- Reset or Rate Change --------------
if (start_reg2)
begin
fsm <= FSM_LOAD;
index <= 5'd0;
mode <= 1'd0;
done <= 1'd0;
end
//---------- GTXRESET --------------------------
else if ((gtxreset_reg2 && !gtxreset_reg1) && ((PCIE_TXSYNC_MODE == 0) || (PCIE_RXSYNC_MODE == 0)) && (PCIE_USE_MODE == "1.0"))
begin
fsm <= FSM_LOAD;
index <= 5'd0;
mode <= 1'd1;
done <= 1'd0;
end
//---------- Idle ------------------------------
else
begin
fsm <= FSM_IDLE;
index <= 5'd0;
mode <= 1'd0;
done <= 1'd1;
end
end
//---------- Load DRP Address ---------------------
FSM_LOAD :
begin
fsm <= (load_cnt == LOAD_CNT_MAX) ? FSM_READ : FSM_LOAD;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Read DRP ------------------------------
FSM_READ :
begin
fsm <= FSM_RRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Read DRP Ready ------------------------
FSM_RRDY :
begin
fsm <= rdy_reg2 ? FSM_WRITE : FSM_RRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Write DRP -----------------------------
FSM_WRITE :
begin
fsm <= FSM_WRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- Write DRP Ready -----------------------
FSM_WRDY :
begin
fsm <= rdy_reg2 ? FSM_DONE : FSM_WRDY;
index <= index;
mode <= mode;
done <= 1'd0;
end
//---------- DRP Done ------------------------------
FSM_DONE :
begin
if ((index == INDEX_MAX) || (mode && (index == 5'd1)) || (x16x20_mode_reg2 && (index == 5'd0)))
begin
fsm <= FSM_IDLE;
index <= 5'd0;
mode <= 1'd0;
done <= 1'd0;
end
else
begin
fsm <= FSM_LOAD;
index <= index + 5'd1;
mode <= mode;
done <= 1'd0;
end
end
//---------- Default State -------------------------
default :
begin
fsm <= FSM_IDLE;
index <= 5'd0;
mode <= 1'd0;
done <= 1'd0;
end
endcase
end
end
//---------- PIPE DRP Output ---------------------------------------------------
assign DRP_ADDR = addr_reg;
assign DRP_EN = (fsm == FSM_READ) || (fsm == FSM_WRITE);
assign DRP_DI = di_reg;
assign DRP_WE = (fsm == FSM_WRITE);
assign DRP_DONE = done;
assign DRP_FSM = fsm;
endmodule
|
// This is a generated system top level RTL file.
// Parameters are taken by 'create_ghrd_top.tcl' in order to
// generate appropriate RTL top based on system requirement.
module ghrd_a10_top (
// FPGA peripherals ports
input wire [3:0] fpga_dipsw_pio,
output wire [3:0] fpga_led_pio,
input wire [3:0] fpga_button_pio,
// HPS memory controller ports
// DDR4 single rank -2133 device
output wire hps_memory_mem_act_n,
output wire hps_memory_mem_bg,
output wire hps_memory_mem_par,
input wire hps_memory_mem_alert_n,
inout wire [4-1:0] hps_memory_mem_dbi_n,
output wire [16:0] hps_memory_mem_a,
output wire [1:0] hps_memory_mem_ba,
output wire hps_memory_mem_ck,
output wire hps_memory_mem_ck_n,
output wire hps_memory_mem_cke,
output wire hps_memory_mem_cs_n,
output wire hps_memory_mem_reset_n,
inout wire [32-1:0] hps_memory_mem_dq,
inout wire [4-1:0] hps_memory_mem_dqs,
inout wire [4-1:0] hps_memory_mem_dqs_n,
output wire hps_memory_mem_odt,
input wire hps_memory_oct_rzqin,
input wire emif_ref_clk,
// HPS peripherals
output wire hps_emac0_TX_CLK,
output wire hps_emac0_TXD0,
output wire hps_emac0_TXD1,
output wire hps_emac0_TXD2,
output wire hps_emac0_TXD3,
input wire hps_emac0_RXD0,
inout wire hps_emac0_MDIO,
output wire hps_emac0_MDC,
input wire hps_emac0_RX_CTL,
output wire hps_emac0_TX_CTL,
input wire hps_emac0_RX_CLK,
input wire hps_emac0_RXD1,
input wire hps_emac0_RXD2,
input wire hps_emac0_RXD3,
inout wire hps_usb0_D0,
inout wire hps_usb0_D1,
inout wire hps_usb0_D2,
inout wire hps_usb0_D3,
inout wire hps_usb0_D4,
inout wire hps_usb0_D5,
inout wire hps_usb0_D6,
inout wire hps_usb0_D7,
input wire hps_usb0_CLK,
output wire hps_usb0_STP,
input wire hps_usb0_DIR,
input wire hps_usb0_NXT,
output wire hps_spim1_CLK,
output wire hps_spim1_MOSI,
input wire hps_spim1_MISO,
output wire hps_spim1_SS0_N,
output wire hps_spim1_SS1_N,
input wire hps_uart1_RX,
output wire hps_uart1_TX,
inout wire hps_i2c1_SDA,
inout wire hps_i2c1_SCL,
inout wire hps_sdio_CMD,
output wire hps_sdio_CLK,
inout wire hps_sdio_D0,
inout wire hps_sdio_D1,
inout wire hps_sdio_D2,
inout wire hps_sdio_D3,
inout wire hps_sdio_D4,
inout wire hps_sdio_D5,
inout wire hps_sdio_D6,
inout wire hps_sdio_D7,
output wire hps_trace_CLK,
output wire hps_trace_D0,
output wire hps_trace_D1,
output wire hps_trace_D2,
output wire hps_trace_D3,
inout wire hps_gpio_GPIO14,
inout wire hps_gpio_GPIO05,
inout wire hps_gpio_GPIO16,
inout wire hps_gpio_GPIO17,
// Other HPS-FPGA peripherals
// FPGA clock and reset
input wire fpga_clk_100,
input wire fpga_reset_n
);
// internal wires and registers declaration
wire [3:0] fpga_debounced_buttons;
wire [3:0] fpga_led_internal;
wire [27:0] stm_hw_events;
wire hps_fpga_reset;
wire [2:0] hps_reset_req;
wire hps_cold_reset;
wire hps_warm_reset;
wire hps_debug_reset;
// connection of internal logics
assign fpga_led_pio = fpga_led_internal;
assign stm_hw_events = {{16{1'b0}}, fpga_dipsw_pio, fpga_led_internal, fpga_debounced_buttons};
wire pr_handshake_start_req;
wire pr_handshake_stop_req;
// SoC sub-system module
ghrd_10as066n2 soc_inst (
.pr_handshake_start_req (pr_handshake_start_req),
.pr_handshake_start_ack (pr_handshake_start_req),
.pr_handshake_stop_req (pr_handshake_stop_req),
.pr_handshake_stop_ack (pr_handshake_stop_req),
.f2h_stm_hw_events_stm_hwevents (stm_hw_events),
.pio_dipsw_external_connection_export (fpga_dipsw_pio),
.pio_led_external_connection_in_port (fpga_led_internal),
.pio_led_external_connection_out_port (fpga_led_internal),
.pio_button_external_connection_export (fpga_debounced_buttons),
.hps_io_hps_io_phery_emac0_TX_CLK (hps_emac0_TX_CLK),
.hps_io_hps_io_phery_emac0_TXD0 (hps_emac0_TXD0),
.hps_io_hps_io_phery_emac0_TXD1 (hps_emac0_TXD1),
.hps_io_hps_io_phery_emac0_TXD2 (hps_emac0_TXD2),
.hps_io_hps_io_phery_emac0_TXD3 (hps_emac0_TXD3),
.hps_io_hps_io_phery_emac0_MDIO (hps_emac0_MDIO),
.hps_io_hps_io_phery_emac0_MDC (hps_emac0_MDC),
.hps_io_hps_io_phery_emac0_RX_CTL (hps_emac0_RX_CTL),
.hps_io_hps_io_phery_emac0_TX_CTL (hps_emac0_TX_CTL),
.hps_io_hps_io_phery_emac0_RX_CLK (hps_emac0_RX_CLK),
.hps_io_hps_io_phery_emac0_RXD0 (hps_emac0_RXD0),
.hps_io_hps_io_phery_emac0_RXD1 (hps_emac0_RXD1),
.hps_io_hps_io_phery_emac0_RXD2 (hps_emac0_RXD2),
.hps_io_hps_io_phery_emac0_RXD3 (hps_emac0_RXD3),
.hps_io_hps_io_phery_usb0_DATA0 (hps_usb0_D0),
.hps_io_hps_io_phery_usb0_DATA1 (hps_usb0_D1),
.hps_io_hps_io_phery_usb0_DATA2 (hps_usb0_D2),
.hps_io_hps_io_phery_usb0_DATA3 (hps_usb0_D3),
.hps_io_hps_io_phery_usb0_DATA4 (hps_usb0_D4),
.hps_io_hps_io_phery_usb0_DATA5 (hps_usb0_D5),
.hps_io_hps_io_phery_usb0_DATA6 (hps_usb0_D6),
.hps_io_hps_io_phery_usb0_DATA7 (hps_usb0_D7),
.hps_io_hps_io_phery_usb0_CLK (hps_usb0_CLK),
.hps_io_hps_io_phery_usb0_STP (hps_usb0_STP),
.hps_io_hps_io_phery_usb0_DIR (hps_usb0_DIR),
.hps_io_hps_io_phery_usb0_NXT (hps_usb0_NXT),
.hps_io_hps_io_phery_spim1_CLK (hps_spim1_CLK),
.hps_io_hps_io_phery_spim1_MOSI (hps_spim1_MOSI),
.hps_io_hps_io_phery_spim1_MISO (hps_spim1_MISO),
.hps_io_hps_io_phery_spim1_SS0_N (hps_spim1_SS0_N),
.hps_io_hps_io_phery_spim1_SS1_N (hps_spim1_SS1_N),
.hps_io_hps_io_phery_uart1_RX (hps_uart1_RX),
.hps_io_hps_io_phery_uart1_TX (hps_uart1_TX),
.hps_io_hps_io_phery_sdmmc_CMD (hps_sdio_CMD),
.hps_io_hps_io_phery_sdmmc_D0 (hps_sdio_D0),
.hps_io_hps_io_phery_sdmmc_D1 (hps_sdio_D1),
.hps_io_hps_io_phery_sdmmc_D2 (hps_sdio_D2),
.hps_io_hps_io_phery_sdmmc_D3 (hps_sdio_D3),
.hps_io_hps_io_phery_sdmmc_D4 (hps_sdio_D4),
.hps_io_hps_io_phery_sdmmc_D5 (hps_sdio_D5),
.hps_io_hps_io_phery_sdmmc_D6 (hps_sdio_D6),
.hps_io_hps_io_phery_sdmmc_D7 (hps_sdio_D7),
.hps_io_hps_io_phery_sdmmc_CCLK (hps_sdio_CLK),
.hps_io_hps_io_phery_trace_CLK (hps_trace_CLK),
.hps_io_hps_io_phery_trace_D0 (hps_trace_D0),
.hps_io_hps_io_phery_trace_D1 (hps_trace_D1),
.hps_io_hps_io_phery_trace_D2 (hps_trace_D2),
.hps_io_hps_io_phery_trace_D3 (hps_trace_D3),
.emif_a10_hps_0_mem_conduit_end_mem_ck (hps_memory_mem_ck),
.emif_a10_hps_0_mem_conduit_end_mem_ck_n (hps_memory_mem_ck_n),
.emif_a10_hps_0_mem_conduit_end_mem_a (hps_memory_mem_a),
.emif_a10_hps_0_mem_conduit_end_mem_act_n (hps_memory_mem_act_n),
.emif_a10_hps_0_mem_conduit_end_mem_ba (hps_memory_mem_ba),
.emif_a10_hps_0_mem_conduit_end_mem_bg (hps_memory_mem_bg),
.emif_a10_hps_0_mem_conduit_end_mem_cke (hps_memory_mem_cke),
.emif_a10_hps_0_mem_conduit_end_mem_cs_n (hps_memory_mem_cs_n),
.emif_a10_hps_0_mem_conduit_end_mem_odt (hps_memory_mem_odt),
.emif_a10_hps_0_mem_conduit_end_mem_reset_n (hps_memory_mem_reset_n),
.emif_a10_hps_0_mem_conduit_end_mem_par (hps_memory_mem_par),
.emif_a10_hps_0_mem_conduit_end_mem_alert_n (hps_memory_mem_alert_n),
.emif_a10_hps_0_mem_conduit_end_mem_dqs (hps_memory_mem_dqs),
.emif_a10_hps_0_mem_conduit_end_mem_dqs_n (hps_memory_mem_dqs_n),
.emif_a10_hps_0_mem_conduit_end_mem_dq (hps_memory_mem_dq),
.emif_a10_hps_0_mem_conduit_end_mem_dbi_n (hps_memory_mem_dbi_n),
.emif_a10_hps_0_oct_conduit_end_oct_rzqin (hps_memory_oct_rzqin),
.emif_a10_hps_0_pll_ref_clk_clock_sink_clk (emif_ref_clk),
.hps_io_hps_io_gpio_gpio1_io5 (hps_gpio_GPIO05),
.hps_io_hps_io_gpio_gpio1_io14 (hps_gpio_GPIO14),
.hps_io_hps_io_gpio_gpio1_io16 (hps_gpio_GPIO16),
.hps_io_hps_io_gpio_gpio1_io17 (hps_gpio_GPIO17),
.hps_io_hps_io_phery_i2c1_SDA (hps_i2c1_SDA),
.hps_io_hps_io_phery_i2c1_SCL (hps_i2c1_SCL),
.hps_fpga_reset_reset (hps_fpga_reset),
.issp_hps_resets_source (hps_reset_req),
.f2h_cold_reset_req_reset_n (~hps_cold_reset),
.f2h_warm_reset_req_reset_n (~hps_warm_reset),
.f2h_debug_reset_req_reset_n (~hps_debug_reset),
.reset_reset_n (fpga_reset_n),
.clk_100_clk (fpga_clk_100)
);
// Debounce logic to clean out glitches within 1ms
debounce debounce_inst (
.clk (fpga_clk_100),
.reset_n (~hps_fpga_reset),
.data_in (fpga_button_pio),
.data_out (fpga_debounced_buttons)
);
defparam debounce_inst.WIDTH = 4;
defparam debounce_inst.POLARITY = "LOW";
defparam debounce_inst.TIMEOUT = 100000; // at 100Mhz this is a debounce time of 1ms
defparam debounce_inst.TIMEOUT_WIDTH = 32; // ceil(log2(TIMEOUT))
altera_edge_detector pulse_cold_reset (
.clk (fpga_clk_100),
.rst_n (~hps_fpga_reset),
.signal_in (hps_reset_req[0]),
.pulse_out (hps_cold_reset)
);
defparam pulse_cold_reset.PULSE_EXT = 6;
defparam pulse_cold_reset.EDGE_TYPE = 1;
defparam pulse_cold_reset.IGNORE_RST_WHILE_BUSY = 1;
altera_edge_detector pulse_warm_reset (
.clk (fpga_clk_100),
.rst_n (~hps_fpga_reset),
.signal_in (hps_reset_req[1]),
.pulse_out (hps_warm_reset)
);
defparam pulse_warm_reset.PULSE_EXT = 2;
defparam pulse_warm_reset.EDGE_TYPE = 1;
defparam pulse_warm_reset.IGNORE_RST_WHILE_BUSY = 1;
altera_edge_detector pulse_debug_reset (
.clk (fpga_clk_100),
.rst_n (~hps_fpga_reset),
.signal_in (hps_reset_req[2]),
.pulse_out (hps_debug_reset)
);
defparam pulse_debug_reset.PULSE_EXT = 32;
defparam pulse_debug_reset.EDGE_TYPE = 1;
defparam pulse_debug_reset.IGNORE_RST_WHILE_BUSY = 1;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FAHCON_BEHAVIORAL_V
`define SKY130_FD_SC_LS__FAHCON_BEHAVIORAL_V
/**
* fahcon: Full adder, inverted carry in, inverted carry out.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__fahcon (
COUT_N,
SUM ,
A ,
B ,
CI
);
// Module ports
output COUT_N;
output SUM ;
input A ;
input B ;
input CI ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xor0_out_SUM ;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_coutn;
// Name Output Other arguments
xor xor0 (xor0_out_SUM , A, B, CI );
buf buf0 (SUM , xor0_out_SUM );
nor nor0 (a_b , A, B );
nor nor1 (a_ci , A, CI );
nor nor2 (b_ci , B, CI );
or or0 (or0_out_coutn, a_b, a_ci, b_ci);
buf buf1 (COUT_N , or0_out_coutn );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__FAHCON_BEHAVIORAL_V |
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2013 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// Permission:
//
// Lattice SG Pte. Ltd. grants permission to use this code
// pursuant to the terms of the Lattice Reference Design License Agreement.
//
//
// Disclaimer:
//
// This VHDL or Verilog source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Lattice provides no warranty
// regarding the use or functionality of this code.
//
// --------------------------------------------------------------------
//
// Lattice SG Pte. Ltd.
// 101 Thomson Road, United Square #07-02
// Singapore 307591
//
//
// TEL: 1-800-Lattice (USA and Canada)
// +65-6631-2000 (Singapore)
// +1-503-268-8001 (other locations)
//
// web: http://www.latticesemi.com/
// email: [email protected]
//
// --------------------------------------------------------------------
//
`timescale 1 ns / 1 ps
module lfsr_count255(
input i_sys_clk,
input i_sys_rst,
output reg o_lfsr_256_done);
reg [7:0] lfsr_reg_i;
wire lfsr_d0_i,lfsr_256_equal_i;
xnor(lfsr_d0_i,lfsr_reg_i[7],lfsr_reg_i[5],lfsr_reg_i[4],lfsr_reg_i[3]);
assign lfsr_256_equal_i = (lfsr_reg_i == 8'h80);
//2D for 100us, 8'h05 for 125us, 8'h10 for 150us, 8'h80 gives 160us
always @(posedge i_sys_clk,posedge i_sys_rst) begin
if(i_sys_rst) begin
lfsr_reg_i <= 0;
o_lfsr_256_done <= 0;
end
else begin
lfsr_reg_i <= lfsr_256_equal_i ? 8'h0 : {lfsr_reg_i[6:0],lfsr_d0_i};
o_lfsr_256_done <= lfsr_256_equal_i;
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1i
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Source Synchronous Output Serializer
// /___/ /\ Filename : OSERDES.v
// \ \ / \ Timestamp : Thu Mar 11 16:44:07 PST 2005
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Added LOC parameter, removed GSR ports and initialized outpus.
// 05/30/06 - CR 232324 -- Added timing checks for SR/REV wrt negedge CLKDIV
// 08/21/06 - CR 210819 -- Added timing checks for DDR mode
// 06/06/07 - Fixed timescale values
// 01/08/08 - CR 458156 -- enabled TRISTATE_WIDTH to be 1 in DDR mode.
// 04/16/08 - CR 468871 Negative SetupHold fix
// 04/23/09 - CR 516748 simprim only fix
// 06/01/09 - CR 523601 simprim only (timing) fix for Tristate Output
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module OSERDES (OQ, SHIFTOUT1, SHIFTOUT2, TQ,
CLK, CLKDIV, D1, D2, D3, D4, D5, D6, OCE, REV, SHIFTIN1, SHIFTIN2, SR, T1, T2, T3, T4, TCE);
parameter DATA_RATE_OQ = "DDR";
parameter DATA_RATE_TQ = "DDR";
parameter integer DATA_WIDTH = 4;
parameter [0:0] INIT_OQ = 1'b0;
parameter [0:0] INIT_TQ = 1'b0;
parameter SERDES_MODE = "MASTER";
parameter [0:0] SRVAL_OQ = 1'b0;
parameter [0:0] SRVAL_TQ = 1'b0;
parameter integer TRISTATE_WIDTH = 4;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output OQ;
output SHIFTOUT1;
output SHIFTOUT2;
output TQ;
input CLK;
input CLKDIV;
input D1;
input D2;
input D3;
input D4;
input D5;
input D6;
tri0 GSR = glbl.GSR;
input OCE;
input REV;
input SHIFTIN1;
input SHIFTIN2;
input SR;
input T1;
input T2;
input T3;
input T4;
input TCE;
reg c23, c45, c67;
reg t1r, t2r, t3r, t4r;
reg io_sdata_edge, io_odata_edge, io_ddr_data;
reg iot_sdata_edge, iot_odata_edge, iot_ddr_data;
reg data1, data2, data3, data4, data5, data6;
reg serdes_mode_int, serdes_int;
reg data_rate_oq_int, ddr_clk_edge_int;
reg [1:0] data_rate_tq_int, tristate_width_int;
reg [1:0] sel;
reg d1r, d2r, d3r, d4r, d5r, d6r;
reg q0, q1, q2, q3;
reg d1rnk2, d2rnk2, d2nrnk2, d3rnk2, d4rnk2, d5rnk2, d6rnk2;
reg qt1, qt2, qt2n;
reg load, qhr, qlr, mux;
reg data1t, data2t;
reg oq_out = INIT_OQ, tq_out = INIT_TQ;
reg [3:0] data_width_int;
reg notifier;
wire oqsr, oqrev;
wire tqsr, tqrev;
wire c2p, c3;
wire [2:0] sel1_4;
wire [3:0] sel5_6;
wire [4:0] sel_tri;
wire [6:0] seltq;
wire [3:0] seloq;
wire clk_in;
wire clkdiv_in;
wire d1_in;
wire d2_in;
wire d3_in;
wire d4_in;
wire d5_in;
wire d6_in;
wire gsr_in;
wire oce_in;
wire sr_in;
wire rev_in;
wire shiftin1_in;
wire shiftin2_in;
wire t1_in;
wire t2_in;
wire t3_in;
wire t4_in;
wire tce_in;
wire shiftout1_out;
wire shiftout2_out;
buf b_oq (OQ, oq_out);
buf b_shiftout1 (SHIFTOUT1, shiftout1_out);
buf b_shiftout2 (SHIFTOUT2, shiftout2_out);
buf b_tq (TQ, tq_out);
buf b_clk (clk_in, CLK);
buf b_clkdiv (clkdiv_in, CLKDIV);
buf b_d1 (d1_in, D1);
buf b_d2 (d2_in, D2);
buf b_d3 (d3_in, D3);
buf b_d4 (d4_in, D4);
buf b_d5 (d5_in, D5);
buf b_d6 (d6_in, D6);
buf b_gsr (gsr_in, GSR);
buf b_oce (oce_in, OCE);
buf b_r (sr_in, SR);
buf b_s (rev_in, REV);
buf b_shiftin1 (shiftin1_in, SHIFTIN1);
buf b_shiftin2 (shiftin2_in, SHIFTIN2);
buf b_t1 (t1_in, T1);
buf b_t2 (t2_in, T2);
buf b_t3 (t3_in, T3);
buf b_t4 (t4_in, T4);
buf b_tce (tce_in, TCE);
// workaround for XSIM
wire rev_in_AND_NOT_sr_in = rev_in & !sr_in;
wire NOT_rev_in_AND_sr_in = !rev_in & sr_in;
/////////////////////////////////////////////////////////
//
// Delay assignments
//
/////////////////////////////////////////////////////////
// Data output delays
localparam io_ffd = 1; // clock to out delay for flip flops driven by clk
localparam io_ffcd = 1; // clock to out delay for flip flops driven by clkdiv
localparam io_mxd = 1; // 60 ps mux delay
localparam io_mxr1 = 1; // mux before 2nd rank of flops
// Programmable load generator
localparam ffdcnt = 1;
localparam mxdcnt = 1;
// CR 516748
// localparam ffrst = 145; // clock to out delay for flop in PLSG
localparam ffrst = 45; // clock to out delay for flop in PLSG
// Tristate output delays
localparam iot_ffd = 1;
// CR 523601
// localparam iot_mxd = 1;
localparam iot_mxd = 20;
/////////////////////////////////////////////////////////////
always @(gsr_in)
if (gsr_in) begin
assign oq_out = INIT_OQ;
assign d1rnk2 = INIT_OQ;
assign d2rnk2 = INIT_OQ;
assign d2nrnk2 = INIT_OQ;
assign d6rnk2 = 1'b0;
assign d5rnk2 = 1'b0;
assign d4rnk2 = 1'b0;
assign d3rnk2 = 1'b0;
assign d6r = 1'b0;
assign d5r = 1'b0;
assign d4r = 1'b0;
assign d3r = 1'b0;
assign d2r = 1'b0;
assign d1r = 1'b0;
// PLG
assign q3 = 1'b0;
assign q2 = 1'b0;
assign q1 = 1'b0;
assign q0 = 1'b0;
// Tristate output
assign tq_out = INIT_TQ;
assign qt1 = INIT_TQ;
assign qt2 = INIT_TQ;
assign qt2n = INIT_TQ;
assign t4r = 1'b0;
assign t3r = 1'b0;
assign t2r = 1'b0;
assign t1r = 1'b0;
end
else begin
deassign oq_out;
deassign d1rnk2;
deassign d2rnk2;
deassign d2nrnk2;
deassign d6rnk2;
deassign d5rnk2;
deassign d4rnk2;
deassign d3rnk2;
deassign d6r;
deassign d5r;
deassign d4r;
deassign d3r;
deassign d2r;
deassign d1r;
// PLG
deassign q3;
deassign q2;
deassign q1;
deassign q0;
// Tristate output
deassign tq_out;
deassign qt1;
deassign qt2;
deassign qt2n;
deassign t4r;
deassign t3r;
deassign t2r;
deassign t1r;
end
initial begin
case (SERDES_MODE)
"MASTER" : serdes_mode_int <= 1'b0;
"SLAVE" : serdes_mode_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute SERDES_MODE on OSERDES instance %m is set to %s. Legal values for this attribute are MASTER or SLAVE", SERDES_MODE);
#1 $finish;
end
endcase // case(SERDES_MODE)
serdes_int <= 1'b1; // SERDES = TRUE
ddr_clk_edge_int <= 1'b1; // DDR_CLK_EDGE = SAME_EDGE
case (DATA_RATE_OQ)
"SDR" : data_rate_oq_int <= 1'b1;
"DDR" : data_rate_oq_int <= 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DATA_RATE_OQ on OSERDES instance %m is set to %s. Legal values for this attribute are SDR or DDR", DATA_RATE_OQ);
#1 $finish;
end
endcase // case(DATA_RATE_OQ)
case (DATA_WIDTH)
2, 3, 4, 5, 6, 7, 8, 10 : data_width_int = DATA_WIDTH[3:0];
default : begin
$display("Attribute Syntax Error : The attribute DATA_WIDTH on OSERDES instance %m is set to %d. Legal values for this attribute are 2, 3, 4, 5, 6, 7, 8, or 10", DATA_WIDTH);
#1 $finish;
end
endcase // case(DATA_WIDTH)
case (DATA_RATE_TQ)
"BUF" : data_rate_tq_int <= 2'b00;
"SDR" : data_rate_tq_int <= 2'b01;
"DDR" : data_rate_tq_int <= 2'b10;
default : begin
$display("Attribute Syntax Error : The attribute DATA_RATE_TQ on OSERDES instance %m is set to %s. Legal values for this attribute are BUF, SDR or DDR", DATA_RATE_TQ);
#1 $finish;
end
endcase // case(DATA_RATE_TQ)
case (TRISTATE_WIDTH)
1 : tristate_width_int <= 2'b00;
2 : tristate_width_int <= 2'b01;
4 : tristate_width_int <= 2'b10;
default : begin
$display("Attribute Syntax Error : The attribute TRISTATE_WIDTH on OSERDES instance %m is set to %d. Legal values for this attribute are 1, 2 or 4", TRISTATE_WIDTH);
#1 $finish;
end
endcase // case(TRISTATE_WIDTH)
end // initial begin
assign shiftout1_out = d3rnk2 & serdes_mode_int;
assign shiftout2_out = d4rnk2 & serdes_mode_int;
assign c2p = (clk_in & ddr_clk_edge_int) | (!clk_in & !ddr_clk_edge_int);
assign c3 = !c2p;
assign sel1_4 = {serdes_int, load, data_rate_oq_int};
assign sel5_6 = {serdes_int, serdes_mode_int, load, data_rate_oq_int};
// Tristate output
assign sel_tri = {load, data_rate_tq_int, tristate_width_int};
assign seloq = {oce_in, data_rate_oq_int, oqsr, oqrev};
assign seltq = {tce_in, data_rate_tq_int, tristate_width_int, tqsr, tqrev};
assign oqsr = (sr_in & !SRVAL_OQ) | (rev_in & SRVAL_OQ);
assign oqrev = (sr_in & SRVAL_OQ) | (rev_in & !SRVAL_OQ);
assign tqsr = (sr_in & !SRVAL_TQ) | (rev_in & SRVAL_TQ);
assign tqrev = (sr_in & SRVAL_TQ) | (rev_in & !SRVAL_TQ);
// 3 flops to create DDR operations of 4 latches
// asynchronous operation
always @ (posedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_OQ == 1'b1))
d1rnk2 <= # io_ffd SRVAL_OQ;
else if (rev_in == 1'b1)
d1rnk2 <= # io_ffd !SRVAL_OQ;
else if (oce_in == 1'b1)
d1rnk2 <= # io_ffd data1;
else if (oce_in == 1'b0) // to match with HW
d1rnk2 <= # io_ffd oq_out;
end // always @ (posedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// Representation of 2nd latch
// asynchronous operation
always @ (posedge c2p or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_OQ == 1'b1))
d2rnk2 <= # io_ffd SRVAL_OQ;
else if (rev_in == 1'b1)
d2rnk2 <= # io_ffd !SRVAL_OQ;
else if (oce_in == 1'b1)
d2rnk2 <= # io_ffd data2;
else if (oce_in == 1'b0) // to match with HW
d2rnk2 <= # io_ffd oq_out;
end // always @ (posedge c2p or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// Representation of 3rd flop ( latch and output latch)
// asynchronous operation
always @ (posedge c3 or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_OQ == 1'b1))
d2nrnk2 <= # io_ffd SRVAL_OQ;
else if (rev_in == 1'b1)
d2nrnk2 <= # io_ffd !SRVAL_OQ;
else if (oce_in == 1'b1)
d2nrnk2 <= # io_ffd d2rnk2;
else if (oce_in == 1'b0) // to match with HW
d2nrnk2 <= # io_ffd oq_out;
end // always @ (posedge c3 or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// last 4 flops which only have reset and init
// asynchronous operation
always @ (posedge clk_in or posedge sr_in) begin
if (sr_in == 1'b1) begin
d3rnk2 <= # io_ffd 1'b0;
d4rnk2 <= # io_ffd 1'b0;
d5rnk2 <= # io_ffd 1'b0;
d6rnk2 <= # io_ffd 1'b0;
end
else begin
d3rnk2 <= # io_ffd data3;
d4rnk2 <= # io_ffd data4;
d5rnk2 <= # io_ffd data5;
d6rnk2 <= # io_ffd data6;
end
end // always @ (posedge clk_in or posedge sr_in)
// First rank of flops for input data
// asynchronous operation
always @ (posedge clkdiv_in or posedge sr_in) begin
if (sr_in == 1'b1) begin
d1r <= # io_ffcd 1'b0;
d2r <= # io_ffcd 1'b0;
d3r <= # io_ffcd 1'b0;
d4r <= # io_ffcd 1'b0;
d5r <= # io_ffcd 1'b0;
d6r <= # io_ffcd 1'b0;
end
else begin
d1r <= # io_ffcd d1_in;
d2r <= # io_ffcd d2_in;
d3r <= # io_ffcd d3_in;
d4r <= # io_ffcd d4_in;
d5r <= # io_ffcd d5_in;
d6r <= # io_ffcd d6_in;
end
end // always @ (posedge clkdiv_in or posedge sr_in)
// Muxs for 2nd rank of flops
always @ (sel1_4 or d1r or d2rnk2 or d3rnk2) begin
casex (sel1_4)
3'b100: data1 <= # io_mxr1 d3rnk2;
3'b110: data1 <= # io_mxr1 d1r;
3'b101: data1 <= # io_mxr1 d2rnk2;
3'b111: data1 <= # io_mxr1 d1r;
default: data1 <= # io_mxr1 d3rnk2;
endcase
end
always @ (sel1_4 or d2r or d3rnk2 or d4rnk2) begin
casex (sel1_4)
3'b100: data2 <= # io_mxr1 d4rnk2;
3'b110: data2 <= # io_mxr1 d2r;
3'b101: data2 <= # io_mxr1 d3rnk2;
3'b111: data2 <= # io_mxr1 d2r;
default: data2 <= # io_mxr1 d4rnk2;
endcase
end
//Note: To stop data rate of 00 from being illegal, register data is fed to mux
always @ (sel1_4 or d3r or d4rnk2 or d5rnk2) begin
casex (sel1_4)
3'b100: data3 <= # io_mxr1 d5rnk2;
3'b110: data3 <= # io_mxr1 d3r;
3'b101: data3 <= # io_mxr1 d4rnk2;
3'b111: data3 <= # io_mxr1 d3r;
default: data3 <= # io_mxr1 d5rnk2;
endcase
end
always @ (sel1_4 or d4r or d5rnk2 or d6rnk2) begin
casex (sel1_4)
3'b100: data4 <= # io_mxr1 d6rnk2;
3'b110: data4 <= # io_mxr1 d4r;
3'b101: data4 <= # io_mxr1 d5rnk2;
3'b111: data4 <= # io_mxr1 d4r;
default: data4 <= # io_mxr1 d6rnk2;
endcase
end
always @ (sel5_6 or d5r or d6rnk2 or shiftin1_in) begin
casex (sel5_6)
4'b1000: data5 <= # io_mxr1 shiftin1_in;
4'b1010: data5 <= # io_mxr1 d5r;
4'b1001: data5 <= # io_mxr1 d6rnk2;
4'b1011: data5 <= # io_mxr1 d5r;
4'b1100: data5 <= # io_mxr1 1'b0;
4'b1110: data5 <= # io_mxr1 d5r;
4'b1101: data5 <= # io_mxr1 d6rnk2;
4'b1111: data5 <= # io_mxr1 d5r;
default: data5 <= # io_mxr1 shiftin1_in;
endcase
end
always @ (sel5_6 or D6 or d6r or shiftin1_in or shiftin2_in) begin
casex (sel5_6)
4'b1000: data6 <= # io_mxr1 shiftin2_in;
4'b1010: data6 <= # io_mxr1 d6r;
4'b1001: data6 <= # io_mxr1 shiftin1_in;
4'b1011: data6 <= # io_mxr1 d6r;
4'b1100: data6 <= # io_mxr1 1'b0;
4'b1110: data6 <= # io_mxr1 d6r;
4'b1101: data6 <= # io_mxr1 1'b0;
4'b1111: data6 <= # io_mxr1 d6r;
default: data6 <= # io_mxr1 shiftin2_in;
endcase
end
// Logic to generate same edge data from d1rnk2 and d2nrnk2;
always @ (clk_in or c3 or d1rnk2 or d2nrnk2) begin
io_sdata_edge <= # io_mxd (d1rnk2 & clk_in) | (d2nrnk2 & c3);
end
// Mux to create opposite edge DDR data from d1rnk2 and d2rnk2
always @(clk_in or d1rnk2 or d2rnk2) begin
case (clk_in)
1'b0: io_odata_edge <= # io_mxd d2rnk2;
1'b1: io_odata_edge <= # io_mxd d1rnk2;
default: io_odata_edge <= # io_mxd d1rnk2;
endcase
end
// Logic to same edge and opposite data into just ddr data
always @(io_sdata_edge or io_odata_edge or ddr_clk_edge_int) begin
io_ddr_data <= # io_mxd (io_odata_edge & !ddr_clk_edge_int) | (io_sdata_edge & ddr_clk_edge_int);
end
// Output mux to generate OQ
always @ (seloq or d1rnk2 or io_ddr_data or oq_out) begin
casex (seloq)
4'bXX01: oq_out <= # io_mxd 1'b1;
4'bXX10: oq_out <= # io_mxd 1'b0;
4'bXX11: oq_out <= # io_mxd 1'b0;
4'b0000: oq_out <= # io_mxd oq_out;
4'b0100: oq_out <= # io_mxd oq_out;
4'b1000: oq_out <= # io_mxd io_ddr_data;
4'b1100: oq_out <= # io_mxd d1rnk2;
default: oq_out <= # io_mxd io_ddr_data;
endcase
end
// Set value of counter in bitslip controller
always @ (data_rate_oq_int or data_width_int) begin
casex ({data_rate_oq_int, data_width_int})
5'b00100: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b00; end
5'b00110: begin c23 <= 1'b1; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b00; end
5'b01000: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b01; end
5'b01010: begin c23 <= 1'b0; c45 <= 1'b1; c67 <= 1'b0; sel <= 2'b01; end
5'b10010: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b00; end
5'b10011: begin c23 <= 1'b1; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b00; end
5'b10100: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b01; end
5'b10101: begin c23 <= 1'b0; c45 <= 1'b1; c67 <= 1'b0; sel <= 2'b01; end
5'b10110: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b10; end
5'b10111: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b1; sel <= 2'b10; end
5'b11000: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b11; end
default: begin
$display("DATA_WIDTH %d and DATA_RATE_OQ %s at time %t ns are illegal.", DATA_WIDTH, DATA_RATE_OQ, $time/1000.0);
$finish;
end
endcase
end // always @ (data_rate_oq_int or data_width_int)
///////////////////////////////////////////////////////////////
// Programmable Load Generator (PLG)
// Divide by 2-8 counter with load enable output
//////////////////////////////////////////////////////////////////
// flops for counter
// asynchronous reset
always @ (posedge qhr or posedge clk_in) begin
if (qhr) begin
q0 <= # ffdcnt 1'b0;
q1 <= # ffdcnt 1'b0;
q2 <= # ffdcnt 1'b0;
q3 <= # ffdcnt 1'b0;
end
else begin
q3 <= # ffdcnt q2;
q2 <= # ffdcnt (!(!q0 & !q2) & q1);
q1 <= # ffdcnt q0;
q0 <= # ffdcnt mux;
end
end // always @ (posedge qhr or posedge clk_in)
// mux settings for counter
always @ (sel or c23 or c45 or c67 or q0 or q1 or q2 or q3) begin
case (sel)
2'b00: mux <= # mxdcnt (!q0 & !(c23 & q1));
2'b01: mux <= # mxdcnt (!q1 & !(c45 & q2));
2'b10: mux <= # mxdcnt (!q2 & !(c67 & q3));
2'b11: mux <= # mxdcnt !q3;
default: mux <= # mxdcnt 1'b0;
endcase
end
// mux decoding for load signal
always @ (sel or c23 or c45 or c67 or q0 or q1 or q2 or q3) begin
case (sel)
2'b00: load <= # mxdcnt q0;
2'b01: load <= # mxdcnt q0 & q1;
2'b10: load <= # mxdcnt q0 & q2;
2'b11: load <= # mxdcnt q0 & q3;
default: load <= # mxdcnt 1'b0;
endcase
end
// flops to reset counter
// Low speed flop
// asynchronous reset
always @ (posedge sr_in or posedge clkdiv_in) begin
if (sr_in == 1'b1)
qlr <= # ffrst 1'b1;
else
qlr <= # ffrst 1'b0;
end // always @ (posedge sr_in or posedge clkdiv_in)
// High speed flop
// asynchronous reset
always @ (posedge sr_in or posedge clk_in) begin
if (sr_in == 1'b1)
qhr <= # ffdcnt 1'b1;
else
qhr <= # ffdcnt qlr;
end // always @ (posedge sr_in or posedge clk_in)
///////////////////////////////////////////////////////
//
// Tristate Output cell
//
////////////////////////////////////////////////////////
// 3 flops to create DDR operations of 4 latches
// Representation of top latch
// asynchronous operation
always @ (posedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_TQ == 1'b1))
qt1 <= # iot_ffd SRVAL_TQ;
else if (rev_in == 1'b1)
qt1 <= # iot_ffd !SRVAL_TQ;
else if (tce_in == 1'b1)
qt1 <= # iot_ffd data1t;
else if (tce_in == 1'b0)
qt1 <= # iot_ffd tq_out;
end // always @ (posedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// Representation of 2nd latch
// asynchronous operation
always @ (posedge c2p or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_TQ == 1'b1))
qt2 <= # iot_ffd SRVAL_TQ;
else if (rev_in == 1'b1)
qt2 <= # iot_ffd !SRVAL_TQ;
else if (tce_in == 1'b1)
qt2 <= # iot_ffd data2t;
else if (tce_in == 1'b0)
qt2 <= # iot_ffd tq_out;
end // always @ (posedge c2p or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// Representation of 3rd flop ( latch and output latch)
// asynchronous operation
always @ (posedge c3 or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_TQ == 1'b1))
qt2n <= # iot_ffd SRVAL_TQ;
else if (rev_in == 1'b1)
qt2n <= # iot_ffd !SRVAL_TQ;
else if (tce_in == 1'b1)
qt2n <= # iot_ffd qt2;
else if (tce_in == 1'b0)
qt2n <= # iot_ffd tq_out;
end // always @ (posedge c3 or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// First rank of flops
// asynchronous reset operation
always @ (posedge clkdiv_in or posedge sr_in) begin
if (sr_in == 1'b1) begin
t1r <= # iot_ffd 1'b0;
t2r <= # iot_ffd 1'b0;
t3r <= # iot_ffd 1'b0;
t4r <= # iot_ffd 1'b0;
end
else begin
t1r <= # iot_ffd t1_in;
t2r <= # iot_ffd t2_in;
t3r <= # iot_ffd t3_in;
t4r <= # iot_ffd t4_in;
end
end // always @ (posedge clkdiv_in or posedge sr_in)
// Data Muxs for tristate otuput signals
always @ (sel_tri or t1_in or t1r or t3r) begin
casex (sel_tri)
5'b00000: data1t <= # iot_mxd t1_in;
5'b10000: data1t <= # iot_mxd t1_in;
5'bX0000: data1t <= # iot_mxd t1_in;
5'b00100: data1t <= # iot_mxd t1_in;
5'b10100: data1t <= # iot_mxd t1_in;
5'bX0100: data1t <= # iot_mxd t1_in;
5'b01001: data1t <= # iot_mxd t1_in;
5'b11001: data1t <= # iot_mxd t1_in;
5'b01010: data1t <= # iot_mxd t3r;
5'b11010: data1t <= # iot_mxd t1r;
// CR 458156 -- allow/enabled TRISTATE_WIDTH to be 1 in DDR mode. No func change, but removed warnings
5'b01000: ;
5'b11000: ;
5'bX1000: ;
default: begin
$display("DATA_RATE_TQ %s and/or TRISTATE_WIDTH %d at time %t ns are not supported by OSERDES", DATA_RATE_TQ, TRISTATE_WIDTH, $time/1000.0);
$finish;
end
endcase
end
// For data 2, width of 1 is inserted as acceptable for buf and sdr
// The capability exists in the device if the feature is added
always @ (sel_tri or t2_in or t2r or t4r) begin
casex (sel_tri)
5'b00000: data2t <= # iot_mxd t2_in;
5'b00100: data2t <= # iot_mxd t2_in;
5'b10000: data2t <= # iot_mxd t2_in;
5'b10100: data2t <= # iot_mxd t2_in;
5'bX0000: data2t <= # iot_mxd t2_in;
5'bX0100: data2t <= # iot_mxd t2_in;
5'b00X00: data2t <= # iot_mxd t2_in;
5'b10X00: data2t <= # iot_mxd t2_in;
5'bX0X00: data2t <= # iot_mxd t2_in;
5'b01001: data2t <= # iot_mxd t2_in;
5'b11001: data2t <= # iot_mxd t2_in;
5'bX1001: data2t <= # iot_mxd t2_in;
5'b01010: data2t <= # iot_mxd t4r;
5'b11010: data2t <= # iot_mxd t2r;
// CR 458156 -- allow/enabled TRISTATE_WIDTH to be 1 in DDR mode. No func change, but removed warnings
5'b01000: ;
5'b11000: ;
5'bX1000: ;
default: begin
$display("DATA_RATE_TQ %s and/or TRISTATE_WIDTH %d at time %t ns are not supported by OSERDES", DATA_RATE_TQ, TRISTATE_WIDTH, $time/1000.0);
$finish;
end
endcase
end
// Logic to generate same edge data from qt1, qt3;
always @ (clk_in or c3 or qt1 or qt2n) begin
iot_sdata_edge <= # iot_mxd (qt1 & clk_in) | (qt2n & c3);
end
// Mux to create opposite edge DDR function
always @ (clk_in or qt1 or qt2) begin
case (clk_in)
1'b0: iot_odata_edge <= # iot_mxd qt2;
1'b1: iot_odata_edge <= # iot_mxd qt1;
default: iot_odata_edge <= 1'b0;
endcase
end
// Logic to same edge and opposite data into just ddr data
always @ (iot_sdata_edge or iot_odata_edge or ddr_clk_edge_int) begin
iot_ddr_data <= # iot_mxd (iot_odata_edge & !ddr_clk_edge_int) | (iot_sdata_edge & ddr_clk_edge_int);
end
// Output mux to generate TQ
// Note that the TQ mux can also support T2 combinatorial or
// registered outputs. Those modes are not support in this model.
always @ (seltq or data1t or iot_ddr_data or qt1 or tq_out) begin
casex (seltq)
7'bX01XX01: tq_out <= # iot_mxd 1'b1;
7'bX10XX01: tq_out <= # iot_mxd 1'b1;
7'bX01XX10: tq_out <= # iot_mxd 1'b0;
7'bX10XX10: tq_out <= # iot_mxd 1'b0;
7'bX01XX11: tq_out <= # iot_mxd 1'b0;
7'bX10XX11: tq_out <= # iot_mxd 1'b0;
7'bX0000XX: tq_out <= # iot_mxd data1t;
7'b0010000: tq_out <= # iot_mxd tq_out;
7'b0100100: tq_out <= # iot_mxd tq_out;
7'b0101000: tq_out <= # iot_mxd tq_out;
7'b1010000: tq_out <= # iot_mxd qt1;
7'b1100100: tq_out <= # iot_mxd iot_ddr_data;
7'b1101000: tq_out <= # iot_mxd iot_ddr_data;
default: tq_out <= # iot_mxd iot_ddr_data;
endcase
end
//*** Timing Checks Start here
`ifndef XIL_TIMING
assign clk_in = CLK;
assign oce_in = OCE;
assign tce_in = TCE;
assign clkdiv_in = CLKDIV;
assign d1_in = D1;
assign d2_in = D2;
assign d3_in = D3;
assign d4_in = D4;
assign d5_in = D5;
assign d6_in = D6;
assign rev_in = REV;
assign sr_in = SR;
assign t1_in = T1;
assign t2_in = T2;
assign t3_in = T3;
assign t4_in = T4;
`endif
specify
(CLK => OQ) = (100:100:100, 100:100:100);
(CLK => TQ) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
(SR => OQ) = (0:0:0, 0:0:0);
(REV => OQ) = (0:0:0, 0:0:0);
(T1 => TQ) = (0:0:0, 0:0:0);
(SR => TQ) = (0:0:0, 0:0:0);
(REV => TQ) = (0:0:0, 0:0:0);
$setuphold (posedge CLKDIV, posedge D1, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d1_in);
$setuphold (posedge CLKDIV, negedge D1, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d1_in);
$setuphold (posedge CLKDIV, posedge D2, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d2_in);
$setuphold (posedge CLKDIV, negedge D2, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d2_in);
$setuphold (posedge CLKDIV, posedge D3, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d3_in);
$setuphold (posedge CLKDIV, negedge D3, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d3_in);
$setuphold (posedge CLKDIV, posedge D4, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d4_in);
$setuphold (posedge CLKDIV, negedge D4, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d4_in);
$setuphold (posedge CLKDIV, posedge D5, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d5_in);
$setuphold (posedge CLKDIV, negedge D5, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d5_in);
$setuphold (posedge CLKDIV, posedge D6, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d6_in);
$setuphold (posedge CLKDIV, negedge D6, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d6_in);
$setuphold (posedge CLK, posedge T1, 0:0:0, 0:0:0, notifier, , , clk_in, t1_in);
$setuphold (posedge CLK, negedge T1, 0:0:0, 0:0:0, notifier, , , clk_in, t1_in);
$setuphold (posedge CLK, posedge T2, 0:0:0, 0:0:0, notifier, , , clk_in, t2_in);
$setuphold (posedge CLK, negedge T2, 0:0:0, 0:0:0, notifier, , , clk_in, t2_in);
$setuphold (posedge CLKDIV, posedge T1, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t1_in);
$setuphold (posedge CLKDIV, negedge T1, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t1_in);
$setuphold (posedge CLKDIV, posedge T2, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t2_in);
$setuphold (posedge CLKDIV, negedge T2, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t2_in);
$setuphold (posedge CLKDIV, posedge T3, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t3_in);
$setuphold (posedge CLKDIV, negedge T3, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t3_in);
$setuphold (posedge CLKDIV, posedge T4, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t4_in);
$setuphold (posedge CLKDIV, negedge T4, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t4_in);
$setuphold (posedge CLK, posedge OCE, 0:0:0, 0:0:0, notifier, , , clk_in, oce_in);
$setuphold (posedge CLK, negedge OCE, 0:0:0, 0:0:0, notifier, , , clk_in, oce_in);
$setuphold (negedge CLK, posedge OCE, 0:0:0, 0:0:0, notifier, , , clk_in, oce_in);
$setuphold (negedge CLK, negedge OCE, 0:0:0, 0:0:0, notifier, , , clk_in, oce_in);
$setuphold (posedge CLK, posedge TCE, 0:0:0, 0:0:0, notifier, , , clk_in, tce_in);
$setuphold (posedge CLK, negedge TCE, 0:0:0, 0:0:0, notifier, , , clk_in, tce_in);
$setuphold (negedge CLK, posedge TCE, 0:0:0, 0:0:0, notifier, , , clk_in, tce_in);
$setuphold (negedge CLK, negedge TCE, 0:0:0, 0:0:0, notifier, , , clk_in, tce_in);
$period (posedge CLK, 0:0:0, notifier);
$period (posedge CLKDIV, 0:0:0, notifier);
$recrem (negedge REV, posedge CLK, 0:0:0, 0:0:0, notifier);
$recrem (negedge SR, posedge CLK, 0:0:0, 0:0:0, notifier);
$recrem (negedge SR, posedge CLKDIV, 0:0:0, 0:0:0, notifier);
// CR 232324
$setuphold (posedge CLKDIV, posedge REV, 0:0:0, 0:0:0, notifier, , , clkdiv_in, rev_in);
$setuphold (posedge CLKDIV, negedge REV, 0:0:0, 0:0:0, notifier, , , clkdiv_in, rev_in);
$setuphold (negedge CLKDIV, posedge REV, 0:0:0, 0:0:0, notifier, , , clkdiv_in, rev_in);
$setuphold (negedge CLKDIV, negedge REV, 0:0:0, 0:0:0, notifier, , , clkdiv_in, rev_in);
$setuphold (posedge CLKDIV, posedge SR, 0:0:0, 0:0:0, notifier, , , clkdiv_in, sr_in);
$setuphold (posedge CLKDIV, negedge SR, 0:0:0, 0:0:0, notifier, , , clkdiv_in, sr_in);
$setuphold (negedge CLKDIV, posedge SR, 0:0:0, 0:0:0, notifier, , , clkdiv_in, sr_in);
$setuphold (negedge CLKDIV, negedge SR, 0:0:0, 0:0:0, notifier, , , clkdiv_in, sr_in);
// CR 210819
$setuphold (negedge CLK, posedge T1, 0:0:0, 0:0:0, notifier, , , clk_in, t1_in);
$setuphold (negedge CLK, negedge T1, 0:0:0, 0:0:0, notifier, , , clk_in, t1_in);
$setuphold (negedge CLK, posedge T2, 0:0:0, 0:0:0, notifier, , , clk_in, t2_in);
$setuphold (negedge CLK, negedge T2, 0:0:0, 0:0:0, notifier, , , clk_in, t2_in);
$recrem (negedge REV, negedge CLK, 0:0:0, 0:0:0, notifier);
$recrem (negedge SR, negedge CLK, 0:0:0, 0:0:0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
$width (posedge CLKDIV, 0:0:0, 0, notifier);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (negedge CLKDIV, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule // OSERDES
`endcelldefine
|
module zeowaa
(
input clk_50,
input [ 5:2] key,
input [ 7:0] sw,
output [11:0] led,
output [ 7:0] hex,
output [ 7:0] digit,
output buzzer
);
// wires & inputs
wire clkCpu;
wire clkIn = clk_50;
wire rst_n = key[4];
wire clkEnable = ~sw[ 7] | ~key[5];
wire [ 3:0 ] clkDevide = { ~sw[6:5], 2'b00 };
wire [ 4:0 ] regAddr = ~sw[4:0];
wire [ 31:0 ] regData;
//cores
sm_top sm_top
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.clkDevide ( clkDevide ),
.clkEnable ( clkEnable ),
.clk ( clkCpu ),
.regAddr ( regAddr ),
.regData ( regData )
);
//outputs
assign led[0] = ~clkCpu;
assign led[11:1] = ~regData[11:0];
//hex out
wire [ 31:0 ] h7segment = regData;
wire clkHex;
sm_clk_divider hex_clk_divider
(
.clkIn ( clkIn ),
.rst_n ( rst_n ),
.devide ( 4'b0 ),
.enable ( 1'b1 ),
.clkOut ( clkHex )
);
sm_hex_display_8 sm_hex_display_8
(
.clock ( clkHex ),
.resetn ( rst_n ),
.number ( h7segment ),
.seven_segments ( hex[6:0] ),
.dot ( hex[7] ),
.anodes ( digit )
);
assign buzzer = 1'b1;
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: txc_engine_classic.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The TXC Engine takes unformatted completions, formats
// these packets into "TLP's" or Transaction Layer Packets. These
// packets must meet max-request, max-payload, and payload termination
// requirements (see Read Completion Boundary). The TXC Engine does not
// check these requirements during operation, but may do so during
// simulation.
// This file also contains the txc_formatter module, which formats
// completion headers.
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh" // Defines the user-facing signal widths.
`include "tlp.vh" // Defines the endpoint-facing field widths in a TLP
module txc_engine_classic
#(
parameter C_PCI_DATA_WIDTH = 128,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 0,
parameter C_MAX_PAYLOAD_DWORDS = 64,
parameter C_DEPTH_PACKETS = 10,
parameter C_VENDOR = "ALTERA"
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
// Interface: TXC Classic
input TXC_TLP_READY,
output [C_PCI_DATA_WIDTH-1:0] TXC_TLP,
output TXC_TLP_VALID,
output TXC_TLP_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_TLP_START_OFFSET,
output TXC_TLP_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_TLP_END_OFFSET,
// Interface: TXC Engine
input TXC_DATA_VALID,
input [C_PCI_DATA_WIDTH-1:0] TXC_DATA,
input TXC_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_START_OFFSET,
input TXC_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_END_OFFSET,
output TXC_DATA_READY,
input TXC_META_VALID,
input [`SIG_FBE_W-1:0] TXC_META_FDWBE,
input [`SIG_LBE_W-1:0] TXC_META_LDWBE,
input [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
input [`SIG_TYPE_W-1:0] TXC_META_TYPE,
input [`SIG_LEN_W-1:0] TXC_META_LENGTH,
input [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
input [`SIG_TAG_W-1:0] TXC_META_TAG,
input [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
input [`SIG_TC_W-1:0] TXC_META_TC,
input [`SIG_ATTR_W-1:0] TXC_META_ATTR,
input TXC_META_EP,
output TXC_META_READY);
`include "functions.vh"
localparam C_DATA_WIDTH = C_PCI_DATA_WIDTH;
localparam C_MAX_HDR_WIDTH = `TLP_MAXHDR_W;
localparam C_MAX_ALIGN_WIDTH = (C_VENDOR == "ALTERA") ? 32:
(C_VENDOR == "XILINX") ? 0 :
0;
localparam C_PIPELINE_FORMATTER_INPUT = C_PIPELINE_INPUT;
localparam C_PIPELINE_FORMATTER_OUTPUT = C_PIPELINE_OUTPUT;
localparam C_FORMATTER_DELAY = C_PIPELINE_FORMATTER_OUTPUT + C_PIPELINE_FORMATTER_INPUT;
/*AUTOWIRE*/
/*AUTOINPUT*/
///*AUTOOUTPUT*/
wire wTxHdrReady;
wire wTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
wire [`SIG_TYPE_W-1:0] wTxType;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
wire wTxHdrNopayload;
txc_formatter_classic
#(
.C_PIPELINE_OUTPUT (C_PIPELINE_FORMATTER_OUTPUT),
.C_PIPELINE_INPUT (C_PIPELINE_FORMATTER_INPUT),
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
.C_MAX_ALIGN_WIDTH (C_MAX_ALIGN_WIDTH),
.C_VENDOR (C_VENDOR))
txc_formatter_inst
(
// Outputs
.TX_HDR_VALID (wTxHdrValid),
.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.TX_HDR_NOPAYLOAD (wTxHdrNopayload),
.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
// Inputs
.TX_HDR_READY (wTxHdrReady),
/*AUTOINST*/
// Outputs
.TXC_META_READY (TXC_META_READY),
// Inputs
.CLK (CLK),
.RST_IN (RST_IN),
.CONFIG_COMPLETER_ID (CONFIG_COMPLETER_ID[`SIG_CPLID_W-1:0]),
.TXC_META_VALID (TXC_META_VALID),
.TXC_META_FDWBE (TXC_META_FDWBE[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (TXC_META_LDWBE[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (TXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
.TXC_META_LENGTH (TXC_META_LENGTH[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (TXC_META_BYTE_COUNT[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (TXC_META_TAG[`SIG_TAG_W-1:0]),
.TXC_META_TYPE (TXC_META_TYPE[`SIG_TYPE_W-1:0]),
.TXC_META_REQUESTER_ID (TXC_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
.TXC_META_TC (TXC_META_TC[`SIG_TC_W-1:0]),
.TXC_META_ATTR (TXC_META_ATTR[`SIG_ATTR_W-1:0]),
.TXC_META_EP (TXC_META_EP));
tx_engine
#(
.C_DATA_WIDTH (C_PCI_DATA_WIDTH),
/*AUTOINSTPARAM*/
// Parameters
.C_DEPTH_PACKETS (C_DEPTH_PACKETS),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_FORMATTER_DELAY (C_FORMATTER_DELAY),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
.C_MAX_PAYLOAD_DWORDS (C_MAX_PAYLOAD_DWORDS),
.C_VENDOR (C_VENDOR))
txc_engine_inst
(
// Outputs
.TX_HDR_READY (wTxHdrReady),
.TX_DATA_READY (TXC_DATA_READY),
.TX_PKT (TXC_TLP[C_DATA_WIDTH-1:0]),
.TX_PKT_START_FLAG (TXC_TLP_START_FLAG),
.TX_PKT_START_OFFSET (TXC_TLP_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_END_FLAG (TXC_TLP_END_FLAG),
.TX_PKT_END_OFFSET (TXC_TLP_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_VALID (TXC_TLP_VALID),
// Inputs
.TX_HDR_VALID (wTxHdrValid),
.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.TX_HDR_NOPAYLOAD (wTxHdrNopayload),
.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
.TX_DATA_VALID (TXC_DATA_VALID),
.TX_DATA (TXC_DATA[C_DATA_WIDTH-1:0]),
.TX_DATA_START_FLAG (TXC_DATA_START_FLAG),
.TX_DATA_START_OFFSET (TXC_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_DATA_END_FLAG (TXC_DATA_END_FLAG),
.TX_DATA_END_OFFSET (TXC_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_READY (TXC_TLP_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
module txc_formatter_classic
#(
parameter C_PCI_DATA_WIDTH = 10'd128,
parameter C_MAX_HDR_WIDTH = `TLP_MAXHDR_W,
parameter C_MAX_ALIGN_WIDTH = 32,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 1,
parameter C_VENDOR = "ALTERA"
)
(
// Interface: Clocks
input CLK,
// Interface: Resets
input RST_IN,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
// Interface: TXC
input TXC_META_VALID,
input [`SIG_FBE_W-1:0] TXC_META_FDWBE,
input [`SIG_LBE_W-1:0] TXC_META_LDWBE,
input [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
input [`SIG_LEN_W-1:0] TXC_META_LENGTH,
input [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
input [`SIG_TAG_W-1:0] TXC_META_TAG,
input [`SIG_TYPE_W-1:0] TXC_META_TYPE,
input [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
input [`SIG_TC_W-1:0] TXC_META_TC,
input [`SIG_ATTR_W-1:0] TXC_META_ATTR,
input TXC_META_EP,
output TXC_META_READY,
// Interface: TX HDR
output TX_HDR_VALID,
output [C_MAX_HDR_WIDTH-1:0] TX_HDR,
output [`SIG_LEN_W-1:0] TX_HDR_PAYLOAD_LEN,
output [`SIG_NONPAY_W-1:0] TX_HDR_NONPAY_LEN,
output [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
output TX_HDR_NOPAYLOAD,
input TX_HDR_READY
);
`include "functions.vh"
wire [C_MAX_HDR_WIDTH-1:0] wCplHdr;
wire wTxHdrReady;
wire wTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
wire [`SIG_TYPE_W-1:0] wTxType;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
wire wTxHdrNopayload;
wire [`TLP_CPLADDR_W-1:0] wTxLoAddr;
// Reserved Fields
assign wCplHdr[`TLP_RSVD0_R] = `TLP_RSVD0_V;
assign wCplHdr[`TLP_ADDRTYPE_R] = `TLP_ADDRTYPE_W'b0;
assign wCplHdr[`TLP_TH_R] = `TLP_TH_W'b0;
assign wCplHdr[`TLP_RSVD1_R] = `TLP_RSVD1_V;
assign wCplHdr[`TLP_RSVD2_R] = `TLP_RSVD2_V;
assign wCplHdr[`TLP_CPLBCM_R] = `TLP_CPLBCM_W'b0;
assign wCplHdr[`TLP_CPLRSVD0_R] = `TLP_CPLRSVD0_W'b0;
assign wCplHdr[127:96] = 32'b0;
// Generic Header Fields
assign wCplHdr[`TLP_LEN_R] = TXC_META_LENGTH;
assign wCplHdr[`TLP_EP_R] = TXC_META_EP;
assign wCplHdr[`TLP_TD_R] = `TLP_NODIGEST_V;
assign wCplHdr[`TLP_ATTR0_R] = TXC_META_ATTR[1:0];
assign wCplHdr[`TLP_ATTR1_R] = TXC_META_ATTR[2];
assign {wCplHdr[`TLP_FMT_R], wCplHdr[`TLP_TYPE_R]} = trellis_to_tlp_type(TXC_META_TYPE,0);
assign wCplHdr[`TLP_TC_R] = TXC_META_TC;
// Completion Specific Fields
assign wCplHdr[`TLP_CPLBYTECNT_R] = TXC_META_BYTE_COUNT;
assign wCplHdr[`TLP_CPLSTAT_R] = 0;
assign wCplHdr[`TLP_CPLCPLID_R] = CONFIG_COMPLETER_ID;
assign wCplHdr[`TLP_CPLADDR_R] = TXC_META_ADDR;
assign wCplHdr[`TLP_CPLTAG_R] = TXC_META_TAG;
assign wCplHdr[`TLP_CPLREQID_R] = TXC_META_REQUESTER_ID;
// Metadata, to the aligner
assign wTxLoAddr = wTxHdr[`TLP_CPLADDR_R];
assign wTxHdrNopayload = ~wTxHdr[`TLP_PAYBIT_I];
assign wTxHdrNonpayLen = 3 + ((C_VENDOR == "ALTERA")? {3'b0,(~wTxLoAddr[2] & ~wTxHdrNopayload)} : 4'b0);
assign wTxHdrPayloadLen = wTxHdrNopayload ? 0 : wTxHdr[`TLP_LEN_R];
assign wTxHdrPacketLen = wTxHdrPayloadLen + wTxHdrNonpayLen;
pipeline
#(// Parameters
.C_DEPTH (C_PIPELINE_INPUT?1:0),
.C_WIDTH (C_MAX_HDR_WIDTH),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
input_inst
(// Outputs
.WR_DATA_READY (TXC_META_READY),
.RD_DATA (wTxHdr),
.RD_DATA_VALID (wTxHdrValid),
// Inputs
.WR_DATA (wCplHdr),
.WR_DATA_VALID (TXC_META_VALID),
.RD_DATA_READY (wTxHdrReady),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
pipeline
#(
// Parameters
.C_DEPTH (C_PIPELINE_OUTPUT?1:0),
.C_WIDTH (C_MAX_HDR_WIDTH+ 1 + `SIG_PACKETLEN_W + `SIG_LEN_W + `SIG_NONPAY_W),
.C_USE_MEMORY (0)
/*AUTOINSTPARAM*/)
output_inst
(
// Outputs
.WR_DATA_READY (wTxHdrReady),
.RD_DATA ({TX_HDR,TX_HDR_NOPAYLOAD,TX_HDR_PACKET_LEN,TX_HDR_PAYLOAD_LEN,TX_HDR_NONPAY_LEN}),
.RD_DATA_VALID (TX_HDR_VALID),
// Inputs
.WR_DATA ({wTxHdr,wTxHdrNopayload,wTxHdrPacketLen,wTxHdrPayloadLen,wTxHdrNonpayLen}),
.WR_DATA_VALID (wTxHdrValid),
.RD_DATA_READY (TX_HDR_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
// Local Variables:
// verilog-library-directories:("." "../../../common/" "../../common/")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DLYGATE4SD3_1_V
`define SKY130_FD_SC_HD__DLYGATE4SD3_1_V
/**
* dlygate4sd3: Delay Buffer 4-stage 0.50um length inner stage gates.
*
* Verilog wrapper for dlygate4sd3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__dlygate4sd3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlygate4sd3_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__dlygate4sd3 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__dlygate4sd3_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__dlygate4sd3 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__DLYGATE4SD3_1_V
|
module registerFile (input wrEnable, input [4:0] wrReg, input [31:0] wrData, input [4:0] rdReg1, output [31:0] rdData1, input [4:0] rdReg2, output [31:0] rdData2, input clk);
reg [31:0] regFile [31:0];
assign rdData1 = regFile[rdReg1];
assign rdData2 = regFile[rdReg2];
always @(posedge clk) begin if (wrEnable) begin regFile[wrReg] <= wrData; end end
endmodule
module registerFile_tb();
reg wrEnable;
reg [4:0] wrReg;
reg [31:0] wrData;
reg [4:0] rdReg1;
wire [31:0] rdData1;
reg [4:0] rdReg2;
wire [31:0] rdData2;
reg clk;
reg [5:0] index; // 6 bits so that it doesnt overflow in the following for loop.
always begin #5 clk = ~clk; end
initial begin
// $monitor ("clk:%d en:%d wrReg:%d wrData:%d rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", clk, wrEnable, wrReg, wrData, rdReg1, rdData1, rdReg2, rdData2);
clk = 0;
wrEnable = 1;
for (index = 0; index < 32; index = index + 1) begin #10 wrReg = index; wrData = index * 2; $display ("wrReg:%d wrData:%d", wrReg, wrData); end
#10 wrEnable = 0; wrReg = 31; wrData = 93;
#10 rdReg1 = 0; rdReg2 = 1; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
#10 rdReg1 = 2; rdReg2 = 3; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
#10 rdReg1 = 4; rdReg2 = 5; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
#10 rdReg1 = 6; rdReg2 = 7; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
#10 rdReg1 = 8; rdReg2 = 9; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
#10 rdReg1 = 10; rdReg2 = 11; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
#10 rdReg1 = 12; rdReg2 = 13; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
#10 rdReg1 = 14; rdReg2 = 15; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
#10 rdReg1 = 16; rdReg2 = 17; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
#10 rdReg1 = 18; rdReg2 = 19; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
#10 rdReg1 = 20; rdReg2 = 21; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
#10 rdReg1 = 22; rdReg2 = 23; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
#10 rdReg1 = 24; rdReg2 = 25; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
#10 rdReg1 = 26; rdReg2 = 27; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
#10 rdReg1 = 28; rdReg2 = 29; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
#10 rdReg1 = 30; rdReg2 = 31; #2 $display ("rdReg1:%d rdData1:%d rdReg2:%d rdData2:%d", rdReg1, rdData1, rdReg2, rdData2);
end
registerFile regFile1 (wrEnable, wrReg, wrData, rdReg1, rdData1, rdReg2, rdData2, clk);
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
typedef struct packed {
union packed {
logic ua;
logic ub;
} u;
logic b;
} str_t;
reg toggle; initial toggle='0;
str_t stoggle; initial stoggle='0;
const reg aconst = '0;
reg [1:0][1:0] ptoggle; initial ptoggle=0;
integer cyc; initial cyc=1;
wire [7:0] cyc_copy = cyc[7:0];
wire toggle_up;
alpha a1 (/*AUTOINST*/
// Outputs
.toggle_up (toggle_up),
// Inputs
.clk (clk),
.toggle (toggle),
.cyc_copy (cyc_copy[7:0]));
alpha a2 (/*AUTOINST*/
// Outputs
.toggle_up (toggle_up),
// Inputs
.clk (clk),
.toggle (toggle),
.cyc_copy (cyc_copy[7:0]));
beta b1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle_up (toggle_up));
off o1 (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle));
reg [1:0] memory[121:110];
reg [1023:0] largeish;
// CHECK_COVER_MISSING(-1)
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1;
toggle <= '0;
stoggle.u <= toggle;
stoggle.b <= toggle;
ptoggle[0][0] <= toggle;
if (cyc==3) begin
toggle <= '1;
end
if (cyc==4) begin
toggle <= '0;
end
else if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module alpha (/*AUTOARG*/
// Outputs
toggle_up,
// Inputs
clk, toggle, cyc_copy
);
// t.a1 and t.a2 collapse to a count of 2
input clk;
input toggle;
// CHECK_COVER(-1,"top.t.a*",4)
// 2 edges * (t.a1 and t.a2)
input [7:0] cyc_copy;
// CHECK_COVER(-1,"top.t.a*","cyc_copy[0]",22)
// CHECK_COVER(-2,"top.t.a*","cyc_copy[1]",10)
// CHECK_COVER(-3,"top.t.a*","cyc_copy[2]",4)
// CHECK_COVER(-4,"top.t.a*","cyc_copy[3]",2)
// CHECK_COVER(-5,"top.t.a*","cyc_copy[4]",0)
// CHECK_COVER(-6,"top.t.a*","cyc_copy[5]",0)
// CHECK_COVER(-7,"top.t.a*","cyc_copy[6]",0)
// CHECK_COVER(-8,"top.t.a*","cyc_copy[7]",0)
reg toggle_internal;
// CHECK_COVER(-1,"top.t.a*",4)
// 2 edges * (t.a1 and t.a2)
output reg toggle_up;
// CHECK_COVER(-1,"top.t.a*",4)
// 2 edges * (t.a1 and t.a2)
always @ (posedge clk) begin
toggle_internal <= toggle;
toggle_up <= toggle;
end
endmodule
module beta (/*AUTOARG*/
// Inputs
clk, toggle_up
);
input clk;
input toggle_up;
// CHECK_COVER(-1,"top.t.b1","toggle_up",2)
/* verilator public_module */
always @ (posedge clk) begin
if (0 && toggle_up) begin end
end
endmodule
module off (/*AUTOARG*/
// Inputs
clk, toggle
);
// verilator coverage_off
input clk;
// CHECK_COVER_MISSING(-1)
// verilator coverage_on
input toggle;
// CHECK_COVER(-1,"top.t.o1","toggle",2)
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_bb
//
// Generated
// by: wig
// on: Wed Jul 16 10:16:52 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_bb.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_bb.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:15 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.19 2003/07/09 07:52:44 wig Exp
//
// Generator: mix_0.pl Revision: 1.13 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
'timescale 1ns / 1ns;
//
//
// Start of Generated Module rtl of ent_bb
//
module ent_bb
//
// Generated module inst_bb
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//TODO: %VERI_CONSTANTS%
// %VERI_CONCURS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_bb
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_bb
//
// Generated
// by: wig
// on: Tue Jul 22 11:18:49 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_bb.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_bb.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:15 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.21 2003/07/17 12:10:43 wig Exp
//
// Generator: mix_0.pl Revision: 1.13 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps;
//
//
// Start of Generated Module rtl of ent_bb
//
// No `defines in this module
module ent_bb
//
// Generated module inst_bb
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//TODO: %VERI_CONSTANTS%
// %VERI_CONCURS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_bb
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_bb
//
// Generated
// by: wig
// on: Tue Aug 12 16:53:17 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_bb.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_bb.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:15 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.24 2003/08/11 07:16:25 wig Exp
//
// Generator: mix_0.pl Revision: 1.14 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_bb
//
// No `defines in this module
module ent_bb
//
// Generated module inst_bb
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_bb
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_bb
//
// Generated
// by: wig
// on: Mon Sep 8 17:52:50 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_bb.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_bb.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:15 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.27 2003/09/08 15:14:24 wig Exp
//
// Generator: mix_0.pl Revision: 1.14 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_bb
//
// No `defines in this module
module ent_bb
//
// Generated module inst_bb
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_bb
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_bb
//
// Generated
// by: wig
// on: Wed Oct 8 09:51:06 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_bb.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_bb.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:15 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.27 2003/09/08 15:14:24 wig Exp
//
// Generator: mix_0.pl Revision: 1.14 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_bb
//
// No `defines in this module
module ent_bb
//
// Generated module inst_bb
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_bb
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_bb
//
// Generated
// by: wig
// on: Wed Oct 8 10:24:03 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_bb.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_bb.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:15 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.27 2003/09/08 15:14:24 wig Exp
//
// Generator: mix_0.pl Revision: 1.14 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_bb
//
// No `defines in this module
module ent_bb
//
// Generated module inst_bb
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_bb
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_bb
//
// Generated
// by: wig
// on: Mon Oct 13 09:32:34 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_bb.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_bb.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:15 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.27 2003/09/08 15:14:24 wig Exp
//
// Generator: mix_0.pl Revision: 1.14 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_bb
//
// No `defines in this module
module ent_bb
//
// Generated module inst_bb
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_bb
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_bb
//
// Generated
// by: wig
// on: Thu Nov 6 15:57:35 2003
// cmd: H:\work\mix\mix_0.pl -nodelta ..\conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_bb.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_bb.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
// Revision 1.1 2004/04/06 11:12:15 wig
// Adding result/conf
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.31 2003/10/23 12:13:17 wig Exp
//
// Generator: mix_0.pl Revision: 1.17 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_bb
//
// No `defines in this module
module ent_bb
//
// Generated module inst_bb
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_bb
//
//
//!End of Module/s
// --------------------------------------------------------------
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_bb
//
// Generated
// by: wig
// on: Fri Jul 15 12:55:13 2005
// cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../conf.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_bb.v,v 1.2 2005/07/15 16:20:06 wig Exp $
// $Date: 2005/07/15 16:20:06 $
// $Log: ent_bb.v,v $
// Revision 1.2 2005/07/15 16:20:06 wig
// Update all testcases; still problems though
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
//
// Generator: mix_0.pl Revision: 1.36 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_bb
//
// No `defines in this module
module ent_bb
//
// Generated module inst_bb
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_bb
//
//
//!End of Module/s
// --------------------------------------------------------------
|
//altlvds_rx CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" COMMON_RX_TX_PLL="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DESERIALIZATION_FACTOR=12 DEVICE_FAMILY="Cyclone III" IMPLEMENT_IN_LES="ON" INCLOCK_PERIOD=20000 INCLOCK_PHASE_SHIFT=521 INPUT_DATA_RATE=600 NUMBER_OF_CHANNELS=8 PLL_SELF_RESET_ON_LOSS_LOCK="ON" PORT_RX_CHANNEL_DATA_ALIGN="PORT_UNUSED" PORT_RX_DATA_ALIGN="PORT_UNUSED" REGISTERED_DATA_ALIGN_INPUT="OFF" REGISTERED_OUTPUT="ON" USE_EXTERNAL_PLL="OFF" rx_in rx_inclock rx_locked rx_out rx_outclock CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 LOW_POWER_MODE="AUTO" ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
//VERSION_BEGIN 9.0 cbx_altaccumulate 2009:01:13:19:20:53:SJ cbx_altclkbuf 2008:07:07:05:29:15:SJ cbx_altddio_in 2008:10:21:23:35:16:SJ cbx_altddio_out 2008:10:21:23:18:09:SJ cbx_altlvds_rx 2009:01:29:13:16:58:SJ cbx_altsyncram 2008:11:06:10:05:41:SJ cbx_cyclone 2008:05:19:10:58:28:SJ cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2008:12:09:22:11:50:SJ cbx_lpm_compare 2009:02:03:01:43:16:SJ cbx_lpm_counter 2008:05:19:10:42:20:SJ cbx_lpm_decode 2008:05:19:10:39:27:SJ cbx_lpm_mux 2008:05:19:10:30:36:SJ cbx_lpm_shiftreg 2008:05:19:10:27:41:SJ cbx_mgl 2009:01:29:16:12:07:SJ cbx_stratix 2008:09:18:16:08:35:SJ cbx_stratixii 2008:11:14:16:08:42:SJ cbx_stratixiii 2008:12:24:11:49:14:SJ cbx_util_mgl 2008:11:21:14:58:47:SJ VERSION_END
//CBXI_INSTANCE_NAME="ArrayUltrasound_LVDS_AD_LVDS_AD_inst_A_altlvds_rx_altlvds_rx_component"
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2009 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
//alt_lvds_ddio_in ADD_LATENCY_REG="TRUE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" WIDTH=8 clock datain dataout_h dataout_l
//VERSION_BEGIN 9.0 cbx_altaccumulate 2009:01:13:19:20:53:SJ cbx_altclkbuf 2008:07:07:05:29:15:SJ cbx_altddio_in 2008:10:21:23:35:16:SJ cbx_altddio_out 2008:10:21:23:18:09:SJ cbx_altlvds_rx 2009:01:29:13:16:58:SJ cbx_altsyncram 2008:11:06:10:05:41:SJ cbx_cyclone 2008:05:19:10:58:28:SJ cbx_cycloneii 2008:05:19:10:57:37:SJ cbx_lpm_add_sub 2008:12:09:22:11:50:SJ cbx_lpm_compare 2009:02:03:01:43:16:SJ cbx_lpm_counter 2008:05:19:10:42:20:SJ cbx_lpm_decode 2008:05:19:10:39:27:SJ cbx_lpm_mux 2008:05:19:10:30:36:SJ cbx_lpm_shiftreg 2008:05:19:10:27:41:SJ cbx_mgl 2009:01:29:16:12:07:SJ cbx_stratix 2008:09:18:16:08:35:SJ cbx_stratixii 2008:11:14:16:08:42:SJ cbx_stratixiii 2008:12:24:11:49:14:SJ cbx_util_mgl 2008:11:21:14:58:47:SJ VERSION_END
//synthesis_resources = reg 40
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"{-to ddio_h_reg*} PLL_COMPENSATE=ON;ADV_NETLIST_OPT_ALLOWED=\"NEVER_ALLOW\""} *)
module LVDS_AD_lvds_ddio_in
(
clock,
datain,
dataout_h,
dataout_l) /* synthesis synthesis_clearbox=1 */;
input clock;
input [7:0] datain;
output [7:0] dataout_h;
output [7:0] dataout_l;
reg [7:0] dataout_h_reg;
reg [7:0] dataout_l_latch;
reg [7:0] dataout_l_reg;
(* ALTERA_ATTRIBUTE = {"LVDS_RX_REGISTER=HIGH;PRESERVE_REGISTER=ON;PRESERVE_FANOUT_FREE_NODE=ON"} *)
reg [7:0] ddio_h_reg;
(* ALTERA_ATTRIBUTE = {"LVDS_RX_REGISTER=LOW;PRESERVE_REGISTER=ON;PRESERVE_FANOUT_FREE_NODE=ON"} *)
reg [7:0] ddio_l_reg;
// synopsys translate_off
initial
dataout_h_reg = 0;
// synopsys translate_on
always @ ( posedge clock)
dataout_h_reg <= ddio_h_reg;
// synopsys translate_off
initial
dataout_l_latch = 0;
// synopsys translate_on
always @ ( negedge clock)
dataout_l_latch <= ddio_l_reg;
// synopsys translate_off
initial
dataout_l_reg = 0;
// synopsys translate_on
always @ ( posedge clock)
dataout_l_reg <= dataout_l_latch;
// synopsys translate_off
initial
ddio_h_reg = 0;
// synopsys translate_on
always @ ( posedge clock)
ddio_h_reg <= datain;
// synopsys translate_off
initial
ddio_l_reg = 0;
// synopsys translate_on
always @ ( negedge clock)
ddio_l_reg <= datain;
assign
dataout_h = dataout_l_reg,
dataout_l = dataout_h_reg;
endmodule //LVDS_AD_lvds_ddio_in
//dffpipe CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DELAY=3 WIDTH=8 clock d q ALTERA_INTERNAL_OPTIONS=AUTO_SHIFT_REGISTER_RECOGNITION=OFF
//VERSION_BEGIN 9.0 cbx_mgl 2009:01:29:16:12:07:SJ cbx_stratixii 2008:11:14:16:08:42:SJ cbx_util_mgl 2008:11:21:14:58:47:SJ VERSION_END
//synthesis_resources = reg 24
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF"} *)
module LVDS_AD_dffpipe
(
clock,
d,
q) /* synthesis synthesis_clearbox=1 */;
input clock;
input [7:0] d;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [7:0] dffe17a;
reg [7:0] dffe18a;
reg [7:0] dffe19a;
wire clrn;
wire ena;
wire prn;
wire sclr;
// synopsys translate_off
initial
dffe17a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe17a <= {8{1'b1}};
else if (clrn == 1'b0) dffe17a <= 8'b0;
else if (ena == 1'b1) dffe17a <= (d & {8{(~ sclr)}});
// synopsys translate_off
initial
dffe18a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe18a <= {8{1'b1}};
else if (clrn == 1'b0) dffe18a <= 8'b0;
else if (ena == 1'b1) dffe18a <= (dffe17a & {8{(~ sclr)}});
// synopsys translate_off
initial
dffe19a = 0;
// synopsys translate_on
always @ ( posedge clock or negedge prn or negedge clrn)
if (prn == 1'b0) dffe19a <= {8{1'b1}};
else if (clrn == 1'b0) dffe19a <= 8'b0;
else if (ena == 1'b1) dffe19a <= (dffe18a & {8{(~ sclr)}});
assign
clrn = 1'b1,
ena = 1'b1,
prn = 1'b1,
q = dffe19a,
sclr = 1'b0;
endmodule //LVDS_AD_dffpipe
//synthesis_resources = cycloneiii_pll 1 reg 280
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{-to lvds_rx_pll} AUTO_MERGE_PLLS=OFF"} *)
module LVDS_AD_lvds_rx
(
rx_in,
rx_inclock,
rx_locked,
rx_out,
rx_outclock) /* synthesis synthesis_clearbox=1 */;
input [7:0] rx_in;
input rx_inclock;
output rx_locked;
output [95:0] rx_out;
output rx_outclock;
wire [7:0] wire_ddio_in_dataout_h;
wire [7:0] wire_ddio_in_dataout_l;
reg [5:0] h_shiftreg10a;
reg [5:0] h_shiftreg12a;
reg [5:0] h_shiftreg14a;
reg [5:0] h_shiftreg16a;
reg [5:0] h_shiftreg2a;
reg [5:0] h_shiftreg4a;
reg [5:0] h_shiftreg6a;
reg [5:0] h_shiftreg8a;
reg [5:0] l_shiftreg11a;
reg [5:0] l_shiftreg13a;
reg [5:0] l_shiftreg15a;
reg [5:0] l_shiftreg1a;
reg [5:0] l_shiftreg3a;
reg [5:0] l_shiftreg5a;
reg [5:0] l_shiftreg7a;
reg [5:0] l_shiftreg9a;
reg [95:0] rx_reg;
wire [7:0] wire_h_dffpipe_q;
wire [7:0] wire_l_dffpipe_q;
wire [4:0] wire_lvds_rx_pll_clk;
wire wire_lvds_rx_pll_fbout;
wire wire_lvds_rx_pll_locked;
wire [7:0] ddio_dataout_h;
wire [7:0] ddio_dataout_h_int;
wire [7:0] ddio_dataout_l;
wire [7:0] ddio_dataout_l_int;
wire fast_clock;
wire [95:0] rx_out_wire;
wire slow_clock;
LVDS_AD_lvds_ddio_in ddio_in
(
.clock(fast_clock),
.datain(rx_in),
.dataout_h(wire_ddio_in_dataout_h),
.dataout_l(wire_ddio_in_dataout_l));
// synopsys translate_off
initial
h_shiftreg10a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
h_shiftreg10a <= {h_shiftreg10a[4:0], ddio_dataout_l[4]};
// synopsys translate_off
initial
h_shiftreg12a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
h_shiftreg12a <= {h_shiftreg12a[4:0], ddio_dataout_l[5]};
// synopsys translate_off
initial
h_shiftreg14a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
h_shiftreg14a <= {h_shiftreg14a[4:0], ddio_dataout_l[6]};
// synopsys translate_off
initial
h_shiftreg16a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
h_shiftreg16a <= {h_shiftreg16a[4:0], ddio_dataout_l[7]};
// synopsys translate_off
initial
h_shiftreg2a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
h_shiftreg2a <= {h_shiftreg2a[4:0], ddio_dataout_l[0]};
// synopsys translate_off
initial
h_shiftreg4a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
h_shiftreg4a <= {h_shiftreg4a[4:0], ddio_dataout_l[1]};
// synopsys translate_off
initial
h_shiftreg6a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
h_shiftreg6a <= {h_shiftreg6a[4:0], ddio_dataout_l[2]};
// synopsys translate_off
initial
h_shiftreg8a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
h_shiftreg8a <= {h_shiftreg8a[4:0], ddio_dataout_l[3]};
// synopsys translate_off
initial
l_shiftreg11a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
l_shiftreg11a <= {l_shiftreg11a[4:0], ddio_dataout_h[5]};
// synopsys translate_off
initial
l_shiftreg13a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
l_shiftreg13a <= {l_shiftreg13a[4:0], ddio_dataout_h[6]};
// synopsys translate_off
initial
l_shiftreg15a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
l_shiftreg15a <= {l_shiftreg15a[4:0], ddio_dataout_h[7]};
// synopsys translate_off
initial
l_shiftreg1a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
l_shiftreg1a <= {l_shiftreg1a[4:0], ddio_dataout_h[0]};
// synopsys translate_off
initial
l_shiftreg3a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
l_shiftreg3a <= {l_shiftreg3a[4:0], ddio_dataout_h[1]};
// synopsys translate_off
initial
l_shiftreg5a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
l_shiftreg5a <= {l_shiftreg5a[4:0], ddio_dataout_h[2]};
// synopsys translate_off
initial
l_shiftreg7a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
l_shiftreg7a <= {l_shiftreg7a[4:0], ddio_dataout_h[3]};
// synopsys translate_off
initial
l_shiftreg9a = 0;
// synopsys translate_on
always @ ( posedge fast_clock)
l_shiftreg9a <= {l_shiftreg9a[4:0], ddio_dataout_h[4]};
// synopsys translate_off
initial
rx_reg = 0;
// synopsys translate_on
always @ ( posedge slow_clock)
rx_reg <= rx_out_wire;
LVDS_AD_dffpipe h_dffpipe
(
.clock(fast_clock),
.d(ddio_dataout_h_int),
.q(wire_h_dffpipe_q));
LVDS_AD_dffpipe l_dffpipe
(
.clock(fast_clock),
.d(ddio_dataout_l_int),
.q(wire_l_dffpipe_q));
cycloneiii_pll lvds_rx_pll
(
.activeclock(),
.clk(wire_lvds_rx_pll_clk),
.clkbad(),
.fbin(wire_lvds_rx_pll_fbout),
.fbout(wire_lvds_rx_pll_fbout),
.inclk({1'b0, rx_inclock}),
.locked(wire_lvds_rx_pll_locked),
.phasedone(),
.scandataout(),
.scandone(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.areset(1'b0),
.clkswitch(1'b0),
.configupdate(1'b0),
.pfdena(1'b1),
.phasecounterselect({3{1'b0}}),
.phasestep(1'b0),
.phaseupdown(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
lvds_rx_pll.clk0_divide_by = 1,
lvds_rx_pll.clk0_multiply_by = 6,
lvds_rx_pll.clk0_phase_shift = "-312",
lvds_rx_pll.clk1_divide_by = 6,
lvds_rx_pll.clk1_multiply_by = 6,
lvds_rx_pll.clk1_phase_shift = "-312",
lvds_rx_pll.inclk0_input_frequency = 20000,
lvds_rx_pll.operation_mode = "source_synchronous",
lvds_rx_pll.self_reset_on_loss_lock = "on",
lvds_rx_pll.lpm_type = "cycloneiii_pll";
assign
ddio_dataout_h = wire_h_dffpipe_q,
ddio_dataout_h_int = wire_ddio_in_dataout_h,
ddio_dataout_l = wire_l_dffpipe_q,
ddio_dataout_l_int = wire_ddio_in_dataout_l,
fast_clock = wire_lvds_rx_pll_clk[0],
rx_locked = wire_lvds_rx_pll_locked,
rx_out = rx_reg,
rx_out_wire = {l_shiftreg15a[5], h_shiftreg16a[5], l_shiftreg15a[4], h_shiftreg16a[4], l_shiftreg15a[3], h_shiftreg16a[3], l_shiftreg15a[2], h_shiftreg16a[2], l_shiftreg15a[1], h_shiftreg16a[1], l_shiftreg15a[0], h_shiftreg16a[0], l_shiftreg13a[5], h_shiftreg14a[5], l_shiftreg13a[4], h_shiftreg14a[4], l_shiftreg13a[3], h_shiftreg14a[3], l_shiftreg13a[2], h_shiftreg14a[2], l_shiftreg13a[1], h_shiftreg14a[1], l_shiftreg13a[0], h_shiftreg14a[0], l_shiftreg11a[5], h_shiftreg12a[5], l_shiftreg11a[4], h_shiftreg12a[4], l_shiftreg11a[3], h_shiftreg12a[3], l_shiftreg11a[2], h_shiftreg12a[2], l_shiftreg11a[1], h_shiftreg12a[1], l_shiftreg11a[0], h_shiftreg12a[0], l_shiftreg9a[5], h_shiftreg10a[5], l_shiftreg9a[4], h_shiftreg10a[4], l_shiftreg9a[3], h_shiftreg10a[3], l_shiftreg9a[2], h_shiftreg10a[2], l_shiftreg9a[1], h_shiftreg10a[1], l_shiftreg9a[0], h_shiftreg10a[0], l_shiftreg7a[5], h_shiftreg8a[5], l_shiftreg7a[4], h_shiftreg8a[4], l_shiftreg7a[3], h_shiftreg8a[3], l_shiftreg7a[2], h_shiftreg8a[2], l_shiftreg7a[1], h_shiftreg8a[1], l_shiftreg7a[0], h_shiftreg8a[0], l_shiftreg5a[5], h_shiftreg6a[5], l_shiftreg5a[4], h_shiftreg6a[4], l_shiftreg5a[3], h_shiftreg6a[3], l_shiftreg5a[2], h_shiftreg6a[2], l_shiftreg5a[1], h_shiftreg6a[1], l_shiftreg5a[0], h_shiftreg6a[0], l_shiftreg3a[5], h_shiftreg4a[5], l_shiftreg3a[4], h_shiftreg4a[4], l_shiftreg3a[3], h_shiftreg4a[3], l_shiftreg3a[2], h_shiftreg4a[2], l_shiftreg3a[1], h_shiftreg4a[1], l_shiftreg3a[0], h_shiftreg4a[0], l_shiftreg1a[5], h_shiftreg2a[5], l_shiftreg1a[4], h_shiftreg2a[4], l_shiftreg1a[3], h_shiftreg2a[3], l_shiftreg1a[2], h_shiftreg2a[2], l_shiftreg1a[1], h_shiftreg2a[1], l_shiftreg1a[0], h_shiftreg2a[0]},
rx_outclock = slow_clock,
slow_clock = wire_lvds_rx_pll_clk[1];
endmodule //LVDS_AD_lvds_rx
//VALID FILE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A21BOI_SYMBOL_V
`define SKY130_FD_SC_MS__A21BOI_SYMBOL_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a21boi (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A21BOI_SYMBOL_V
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file pcie_data_rec_fifo.v when simulating
// the core, pcie_data_rec_fifo. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module pcie_data_rec_fifo(
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
almost_full,
empty,
almost_empty,
rd_data_count,
wr_data_count,
prog_full
);
input rst;
input wr_clk;
input rd_clk;
input [127 : 0] din;
input wr_en;
input rd_en;
output [255 : 0] dout;
output full;
output almost_full;
output empty;
output almost_empty;
output [9 : 0] rd_data_count;
output [10 : 0] wr_data_count;
output prog_full;
// synthesis translate_off
FIFO_GENERATOR_V8_4 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(11),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(128),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(256),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("virtex6"),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(1),
.C_HAS_ALMOST_FULL(1),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(1),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(1),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("2kx18"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(1793),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(1792),
.C_PROG_FULL_TYPE(1),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(11),
.C_WR_DEPTH(2048),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(11),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.RST(rst),
.WR_CLK(wr_clk),
.RD_CLK(rd_clk),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.ALMOST_FULL(almost_full),
.EMPTY(empty),
.ALMOST_EMPTY(almost_empty),
.RD_DATA_COUNT(rd_data_count),
.WR_DATA_COUNT(wr_data_count),
.PROG_FULL(prog_full),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.SRST(),
.WR_RST(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.WR_ACK(),
.OVERFLOW(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_sub_outputs (
// inputs:
address,
clk,
in_port,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input [ 1: 0] address;
input clk;
input [ 7: 0] in_port;
input reset_n;
wire clk_en;
wire [ 7: 0] data_in;
wire [ 7: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_in;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
endmodule
|
module fifo_address_gray_pipelined (
input m_axis_aclk,
input m_axis_aresetn,
input m_axis_ready,
output reg m_axis_valid,
output [C_ADDRESS_WIDTH-1:0] m_axis_raddr_next,
input s_axis_aclk,
input s_axis_aresetn,
output reg s_axis_ready,
input s_axis_valid,
output reg s_axis_empty,
output [C_ADDRESS_WIDTH-1:0] s_axis_waddr
);
parameter C_ADDRESS_WIDTH = 4;
reg [C_ADDRESS_WIDTH:0] _s_axis_waddr = 'h00;
reg [C_ADDRESS_WIDTH:0] _s_axis_waddr_next;
wire [C_ADDRESS_WIDTH:0] _s_axis_raddr;
reg [C_ADDRESS_WIDTH:0] _m_axis_raddr = 'h00;
reg [C_ADDRESS_WIDTH:0] _m_axis_raddr_next;
wire [C_ADDRESS_WIDTH:0] _m_axis_waddr;
assign s_axis_waddr = _s_axis_waddr[C_ADDRESS_WIDTH-1:0];
assign m_axis_raddr_next = _m_axis_raddr_next[C_ADDRESS_WIDTH-1:0];
always @(*)
begin
if (s_axis_ready && s_axis_valid)
_s_axis_waddr_next <= _s_axis_waddr + 1;
else
_s_axis_waddr_next <= _s_axis_waddr;
end
always @(posedge s_axis_aclk)
begin
if (s_axis_aresetn == 1'b0) begin
_s_axis_waddr <= 'h00;
end else begin
_s_axis_waddr <= _s_axis_waddr_next;
end
end
always @(*)
begin
if (m_axis_ready && m_axis_valid)
_m_axis_raddr_next <= _m_axis_raddr + 1;
else
_m_axis_raddr_next <= _m_axis_raddr;
end
always @(posedge m_axis_aclk)
begin
if (m_axis_aresetn == 1'b0) begin
_m_axis_raddr <= 'h00;
end else begin
_m_axis_raddr <= _m_axis_raddr_next;
end
end
sync_gray #(
.DATA_WIDTH(C_ADDRESS_WIDTH + 1)
) i_waddr_sync (
.in_clk(s_axis_aclk),
.in_resetn(s_axis_aresetn),
.out_clk(m_axis_aclk),
.out_resetn(m_axis_aresetn),
.in_count(_s_axis_waddr),
.out_count(_m_axis_waddr)
);
sync_gray #(
.DATA_WIDTH(C_ADDRESS_WIDTH + 1)
) i_raddr_sync (
.in_clk(m_axis_aclk),
.in_resetn(m_axis_aresetn),
.out_clk(s_axis_aclk),
.out_resetn(s_axis_aresetn),
.in_count(_m_axis_raddr),
.out_count(_s_axis_raddr)
);
always @(posedge s_axis_aclk)
begin
if (s_axis_aresetn == 1'b0) begin
s_axis_ready <= 1'b1;
s_axis_empty <= 1'b1;
end else begin
s_axis_ready <= (_s_axis_raddr[C_ADDRESS_WIDTH] == _s_axis_waddr_next[C_ADDRESS_WIDTH] ||
_s_axis_raddr[C_ADDRESS_WIDTH-1:0] != _s_axis_waddr_next[C_ADDRESS_WIDTH-1:0]);
s_axis_empty <= _s_axis_raddr == _s_axis_waddr_next;
end
end
always @(posedge m_axis_aclk)
begin
if (s_axis_aresetn == 1'b0)
m_axis_valid <= 1'b0;
else begin
m_axis_valid <= _m_axis_waddr != _m_axis_raddr_next;
end
end
endmodule
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's CPU ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instantiation of internal CPU blocks. IFETCH, SPRS, FRZ, ////
//// ALU, EXCEPT, ID, WBMUX, OPERANDMUX, RF etc. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_cpu.v,v $
// Revision 1.1 2008/05/07 22:43:21 daughtry
// Initial Demo RTL check-in
//
// Revision 1.16 2005/01/07 09:28:37 andreje
// flag for l.cmov instruction added
//
// Revision 1.15 2004/05/09 19:49:04 lampret
// Added some l.cust5 custom instructions as example
//
// Revision 1.14 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.12.4.2 2004/02/11 01:40:11 lampret
// preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS.
//
// Revision 1.12.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.12 2002/09/07 05:42:02 lampret
// Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS.
//
// Revision 1.11 2002/08/28 01:44:25 lampret
// Removed some commented RTL. Fixed SR/ESR flag bug.
//
// Revision 1.10 2002/07/14 22:17:17 lampret
// Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
//
// Revision 1.9 2002/03/29 16:29:37 lampret
// Fixed some ports in instnatiations that were removed from the modules
//
// Revision 1.8 2002/03/29 15:16:54 lampret
// Some of the warnings fixed.
//
// Revision 1.7 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.6 2002/02/01 19:56:54 lampret
// Fixed combinational loops.
//
// Revision 1.5 2002/01/28 01:15:59 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.4 2002/01/18 14:21:43 lampret
// Fixed 'the NPC single-step fix'.
//
// Revision 1.3 2002/01/18 07:56:00 lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.19 2001/11/30 18:59:47 simons
// *** empty log message ***
//
// Revision 1.18 2001/11/23 21:42:31 simons
// Program counter divided to PPC and NPC.
//
// Revision 1.17 2001/11/23 08:38:51 lampret
// Changed DSR/DRR behavior and exception detection.
//
// Revision 1.16 2001/11/20 00:57:22 lampret
// Fixed width of du_except.
//
// Revision 1.15 2001/11/18 09:58:28 lampret
// Fixed some l.trap typos.
//
// Revision 1.14 2001/11/18 08:36:28 lampret
// For GDB changed single stepping and disabled trap exception.
//
// Revision 1.13 2001/11/13 10:02:21 lampret
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
//
// Revision 1.12 2001/11/12 01:45:40 lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.11 2001/11/10 03:43:57 lampret
// Fixed exceptions.
//
// Revision 1.10 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.9 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:35 igorm
// no message
//
// Revision 1.4 2001/08/17 08:01:19 lampret
// IC enable/disable.
//
// Revision 1.3 2001/08/13 03:36:20 lampret
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
//
// Revision 1.2 2001/08/09 13:39:33 lampret
// Major clean-up.
//
// Revision 1.1 2001/07/20 00:46:03 lampret
// Development version of RTL. Libraries are missing.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_cpu(
// Clk & Rst
clk, rst,
// Insn interface
ic_en,
icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
immu_en,
// Debug unit
ex_insn, ex_freeze, id_pc, branch_op,
spr_dat_npc, rf_dataw,
du_stall, du_addr, du_dat_du, du_read, du_write, du_dsr, du_hwbkpt,
du_except, du_dat_cpu,
// Data interface
dc_en,
dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i,
dmmu_en,
// Interrupt & tick exceptions
sig_int, sig_tick,
// SPR interface
supv, spr_addr, spr_dat_cpu, spr_dat_pic, spr_dat_tt, spr_dat_pm,
spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_we
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
//
// I/O ports
//
//
// Clk & Rst
//
input clk;
input rst;
//
// Insn (IC) interface
//
output ic_en;
output [31:0] icpu_adr_o;
output icpu_cycstb_o;
output [3:0] icpu_sel_o;
output [3:0] icpu_tag_o;
input [31:0] icpu_dat_i;
input icpu_ack_i;
input icpu_rty_i;
input icpu_err_i;
input [31:0] icpu_adr_i;
input [3:0] icpu_tag_i;
//
// Insn (IMMU) interface
//
output immu_en;
//
// Debug interface
//
output [31:0] ex_insn;
output ex_freeze;
output [31:0] id_pc;
output [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
input du_stall;
input [dw-1:0] du_addr;
input [dw-1:0] du_dat_du;
input du_read;
input du_write;
input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
input du_hwbkpt;
output [12:0] du_except;
output [dw-1:0] du_dat_cpu;
output [dw-1:0] rf_dataw;
//
// Data (DC) interface
//
output [31:0] dcpu_adr_o;
output dcpu_cycstb_o;
output dcpu_we_o;
output [3:0] dcpu_sel_o;
output [3:0] dcpu_tag_o;
output [31:0] dcpu_dat_o;
input [31:0] dcpu_dat_i;
input dcpu_ack_i;
input dcpu_rty_i;
input dcpu_err_i;
input [3:0] dcpu_tag_i;
output dc_en;
//
// Data (DMMU) interface
//
output dmmu_en;
//
// SPR interface
//
output supv;
input [dw-1:0] spr_dat_pic;
input [dw-1:0] spr_dat_tt;
input [dw-1:0] spr_dat_pm;
input [dw-1:0] spr_dat_dmmu;
input [dw-1:0] spr_dat_immu;
input [dw-1:0] spr_dat_du;
output [dw-1:0] spr_addr;
output [dw-1:0] spr_dat_cpu;
output [dw-1:0] spr_dat_npc;
output [31:0] spr_cs;
output spr_we;
//
// Interrupt exceptions
//
input sig_int;
input sig_tick;
//
// Internal wires
//
wire [31:0] if_insn;
wire [31:0] if_pc;
wire [31:2] lr_sav;
wire [aw-1:0] rf_addrw;
wire [aw-1:0] rf_addra;
wire [aw-1:0] rf_addrb;
wire rf_rda;
wire rf_rdb;
wire [dw-1:0] simm;
wire [dw-1:2] branch_addrofs;
wire [`OR1200_ALUOP_WIDTH-1:0] alu_op;
wire [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
wire [`OR1200_COMPOP_WIDTH-1:0] comp_op;
wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
wire [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
wire genpc_freeze;
wire if_freeze;
wire id_freeze;
wire ex_freeze;
wire wb_freeze;
wire [`OR1200_SEL_WIDTH-1:0] sel_a;
wire [`OR1200_SEL_WIDTH-1:0] sel_b;
wire [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op;
wire [dw-1:0] rf_dataw;
wire [dw-1:0] rf_dataa;
wire [dw-1:0] rf_datab;
wire [dw-1:0] muxed_b;
wire [dw-1:0] wb_forw;
wire wbforw_valid;
wire [dw-1:0] operand_a;
wire [dw-1:0] operand_b;
wire [dw-1:0] alu_dataout;
wire [dw-1:0] lsu_dataout;
wire [dw-1:0] sprs_dataout;
wire [31:0] lsu_addrofs;
wire [`OR1200_MULTICYCLE_WIDTH-1:0] multicycle;
wire [`OR1200_EXCEPT_WIDTH-1:0] except_type;
wire [4:0] cust5_op;
wire [5:0] cust5_limm;
wire flushpipe;
wire extend_flush;
wire branch_taken;
wire flag;
wire flagforw;
wire flag_we;
wire carry;
wire cyforw;
wire cy_we;
wire lsu_stall;
wire epcr_we;
wire eear_we;
wire esr_we;
wire pc_we;
wire [31:0] epcr;
wire [31:0] eear;
wire [`OR1200_SR_WIDTH-1:0] esr;
wire sr_we;
wire [`OR1200_SR_WIDTH-1:0] to_sr;
wire [`OR1200_SR_WIDTH-1:0] sr;
wire except_start;
wire except_started;
wire [31:0] wb_insn;
wire [15:0] spr_addrimm;
wire sig_syscall;
wire sig_trap;
wire [31:0] spr_dat_cfgr;
wire [31:0] spr_dat_rf;
wire [31:0] spr_dat_npc;
wire [31:0] spr_dat_ppc;
wire [31:0] spr_dat_mac;
wire force_dslot_fetch;
wire no_more_dslot;
wire ex_void;
wire if_stall;
wire id_macrc_op;
wire ex_macrc_op;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
wire [31:0] mult_mac_result;
wire mac_stall;
wire [12:0] except_stop;
wire genpc_refetch;
wire rfe;
wire lsu_unstall;
wire except_align;
wire except_dtlbmiss;
wire except_dmmufault;
wire except_illegal;
wire except_itlbmiss;
wire except_immufault;
wire except_ibuserr;
wire except_dbuserr;
wire abort_ex;
//
// Send exceptions to Debug Unit
//
assign du_except = except_stop;
//
// Data cache enable
//
assign dc_en = sr[`OR1200_SR_DCE];
//
// Instruction cache enable
//
assign ic_en = sr[`OR1200_SR_ICE];
//
// DMMU enable
//
assign dmmu_en = sr[`OR1200_SR_DME];
//
// IMMU enable
//
assign immu_en = sr[`OR1200_SR_IME];
//
// SUPV bit
//
assign supv = sr[`OR1200_SR_SM];
//
// Instantiation of instruction fetch block
//
or1200_genpc or1200_genpc(
.clk(clk),
.rst(rst),
.icpu_adr_o(icpu_adr_o),
.icpu_cycstb_o(icpu_cycstb_o),
.icpu_sel_o(icpu_sel_o),
.icpu_tag_o(icpu_tag_o),
.icpu_rty_i(icpu_rty_i),
.icpu_adr_i(icpu_adr_i),
.branch_op(branch_op),
.except_type(except_type),
.except_start(except_start),
.except_prefix(sr[`OR1200_SR_EPH]),
.branch_addrofs(branch_addrofs),
.lr_restor(operand_b),
.flag(flag),
.taken(branch_taken),
.binsn_addr(lr_sav),
.epcr(epcr),
.spr_dat_i(spr_dat_cpu),
.spr_pc_we(pc_we),
.genpc_refetch(genpc_refetch),
.genpc_freeze(genpc_freeze),
.genpc_stop_prefetch(1'b0),
.no_more_dslot(no_more_dslot)
);
//
// Instantiation of instruction fetch block
//
or1200_if or1200_if(
.clk(clk),
.rst(rst),
.icpu_dat_i(icpu_dat_i),
.icpu_ack_i(icpu_ack_i),
.icpu_err_i(icpu_err_i),
.icpu_adr_i(icpu_adr_i),
.icpu_tag_i(icpu_tag_i),
.if_freeze(if_freeze),
.if_insn(if_insn),
.if_pc(if_pc),
.flushpipe(flushpipe),
.if_stall(if_stall),
.no_more_dslot(no_more_dslot),
.genpc_refetch(genpc_refetch),
.rfe(rfe),
.except_itlbmiss(except_itlbmiss),
.except_immufault(except_immufault),
.except_ibuserr(except_ibuserr)
);
//
// Instantiation of instruction decode/control logic
//
or1200_ctrl or1200_ctrl(
.clk(clk),
.rst(rst),
.id_freeze(id_freeze),
.ex_freeze(ex_freeze),
.wb_freeze(wb_freeze),
.flushpipe(flushpipe),
.if_insn(if_insn),
.ex_insn(ex_insn),
.branch_op(branch_op),
.branch_taken(branch_taken),
.rf_addra(rf_addra),
.rf_addrb(rf_addrb),
.rf_rda(rf_rda),
.rf_rdb(rf_rdb),
.alu_op(alu_op),
.mac_op(mac_op),
.shrot_op(shrot_op),
.comp_op(comp_op),
.rf_addrw(rf_addrw),
.rfwb_op(rfwb_op),
.wb_insn(wb_insn),
.simm(simm),
.branch_addrofs(branch_addrofs),
.lsu_addrofs(lsu_addrofs),
.sel_a(sel_a),
.sel_b(sel_b),
.lsu_op(lsu_op),
.cust5_op(cust5_op),
.cust5_limm(cust5_limm),
.multicycle(multicycle),
.spr_addrimm(spr_addrimm),
.wbforw_valid(wbforw_valid),
.sig_syscall(sig_syscall),
.sig_trap(sig_trap),
.force_dslot_fetch(force_dslot_fetch),
.no_more_dslot(no_more_dslot),
.ex_void(ex_void),
.id_macrc_op(id_macrc_op),
.ex_macrc_op(ex_macrc_op),
.rfe(rfe),
.du_hwbkpt(du_hwbkpt),
.except_illegal(except_illegal)
);
//
// Instantiation of register file
//
or1200_rf or1200_rf(
.clk(clk),
.rst(rst),
.supv(sr[`OR1200_SR_SM]),
.wb_freeze(wb_freeze),
.addrw(rf_addrw),
.dataw(rf_dataw),
.id_freeze(id_freeze),
.we(rfwb_op[0]),
.flushpipe(flushpipe),
.addra(rf_addra),
.rda(rf_rda),
.dataa(rf_dataa),
.addrb(rf_addrb),
.rdb(rf_rdb),
.datab(rf_datab),
.spr_cs(spr_cs[`OR1200_SPR_GROUP_SYS]),
.spr_write(spr_we),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_rf)
);
//
// Instantiation of operand muxes
//
or1200_operandmuxes or1200_operandmuxes(
.clk(clk),
.rst(rst),
.id_freeze(id_freeze),
.ex_freeze(ex_freeze),
.rf_dataa(rf_dataa),
.rf_datab(rf_datab),
.ex_forw(rf_dataw),
.wb_forw(wb_forw),
.simm(simm),
.sel_a(sel_a),
.sel_b(sel_b),
.operand_a(operand_a),
.operand_b(operand_b),
.muxed_b(muxed_b)
);
//
// Instantiation of CPU's ALU
//
or1200_alu or1200_alu(
.a(operand_a),
.b(operand_b),
.mult_mac_result(mult_mac_result),
.macrc_op(ex_macrc_op),
.alu_op(alu_op),
.shrot_op(shrot_op),
.comp_op(comp_op),
.cust5_op(cust5_op),
.cust5_limm(cust5_limm),
.result(alu_dataout),
.flagforw(flagforw),
.flag_we(flag_we),
.cyforw(cyforw),
.cy_we(cy_we),
.flag(flag),
.carry(carry)
);
//
// Instantiation of CPU's ALU
//
or1200_mult_mac or1200_mult_mac(
.clk(clk),
.rst(rst),
.ex_freeze(ex_freeze),
.id_macrc_op(id_macrc_op),
.macrc_op(ex_macrc_op),
.a(operand_a),
.b(operand_b),
.mac_op(mac_op),
.alu_op(alu_op),
.result(mult_mac_result),
.mac_stall_r(mac_stall),
.spr_cs(spr_cs[`OR1200_SPR_GROUP_MAC]),
.spr_write(spr_we),
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_mac)
);
//
// Instantiation of CPU's SPRS block
//
or1200_sprs or1200_sprs(
.clk(clk),
.rst(rst),
.addrbase(operand_a),
.addrofs(spr_addrimm),
.dat_i(operand_b),
.alu_op(alu_op),
.flagforw(flagforw),
.flag_we(flag_we),
.flag(flag),
.cyforw(cyforw),
.cy_we(cy_we),
.carry(carry),
.to_wbmux(sprs_dataout),
.du_addr(du_addr),
.du_dat_du(du_dat_du),
.du_read(du_read),
.du_write(du_write),
.du_dat_cpu(du_dat_cpu),
.spr_addr(spr_addr),
.spr_dat_pic(spr_dat_pic),
.spr_dat_tt(spr_dat_tt),
.spr_dat_pm(spr_dat_pm),
.spr_dat_cfgr(spr_dat_cfgr),
.spr_dat_rf(spr_dat_rf),
.spr_dat_npc(spr_dat_npc),
.spr_dat_ppc(spr_dat_ppc),
.spr_dat_mac(spr_dat_mac),
.spr_dat_dmmu(spr_dat_dmmu),
.spr_dat_immu(spr_dat_immu),
.spr_dat_du(spr_dat_du),
.spr_dat_o(spr_dat_cpu),
.spr_cs(spr_cs),
.spr_we(spr_we),
.epcr_we(epcr_we),
.eear_we(eear_we),
.esr_we(esr_we),
.pc_we(pc_we),
.epcr(epcr),
.eear(eear),
.esr(esr),
.except_started(except_started),
.sr_we(sr_we),
.to_sr(to_sr),
.sr(sr),
.branch_op(branch_op)
);
//
// Instantiation of load/store unit
//
//XLNX_MODIFIED added in a clock
or1200_lsu or1200_lsu(
.clk(clk),
.addrbase(operand_a),
.addrofs(lsu_addrofs),
.lsu_op(lsu_op),
.lsu_datain(operand_b),
.lsu_dataout(lsu_dataout),
.lsu_stall(lsu_stall),
.lsu_unstall(lsu_unstall),
.du_stall(du_stall),
.except_align(except_align),
.except_dtlbmiss(except_dtlbmiss),
.except_dmmufault(except_dmmufault),
.except_dbuserr(except_dbuserr),
.dcpu_adr_o(dcpu_adr_o),
.dcpu_cycstb_o(dcpu_cycstb_o),
.dcpu_we_o(dcpu_we_o),
.dcpu_sel_o(dcpu_sel_o),
.dcpu_tag_o(dcpu_tag_o),
.dcpu_dat_o(dcpu_dat_o),
.dcpu_dat_i(dcpu_dat_i),
.dcpu_ack_i(dcpu_ack_i),
.dcpu_rty_i(dcpu_rty_i),
.dcpu_err_i(dcpu_err_i),
.dcpu_tag_i(dcpu_tag_i)
);
//
// Instantiation of write-back muxes
//
or1200_wbmux or1200_wbmux(
.clk(clk),
.rst(rst),
.wb_freeze(wb_freeze),
.rfwb_op(rfwb_op),
.muxin_a(alu_dataout),
.muxin_b(lsu_dataout),
.muxin_c(sprs_dataout),
.muxin_d({lr_sav, 2'b0}),
.muxout(rf_dataw),
.muxreg(wb_forw),
.muxreg_valid(wbforw_valid)
);
//
// Instantiation of freeze logic
//
or1200_freeze or1200_freeze(
.clk(clk),
.rst(rst),
.multicycle(multicycle),
.flushpipe(flushpipe),
.extend_flush(extend_flush),
.lsu_stall(lsu_stall),
.if_stall(if_stall),
.lsu_unstall(lsu_unstall),
.force_dslot_fetch(force_dslot_fetch),
.abort_ex(abort_ex),
.du_stall(du_stall),
.mac_stall(mac_stall),
.genpc_freeze(genpc_freeze),
.if_freeze(if_freeze),
.id_freeze(id_freeze),
.ex_freeze(ex_freeze),
.wb_freeze(wb_freeze),
.icpu_ack_i(icpu_ack_i),
.icpu_err_i(icpu_err_i)
);
//
// Instantiation of exception block
//
or1200_except or1200_except(
.clk(clk),
.rst(rst),
.sig_ibuserr(except_ibuserr),
.sig_dbuserr(except_dbuserr),
.sig_illegal(except_illegal),
.sig_align(except_align),
.sig_range(1'b0),
.sig_dtlbmiss(except_dtlbmiss),
.sig_dmmufault(except_dmmufault),
.sig_int(sig_int),
.sig_syscall(sig_syscall),
.sig_trap(sig_trap),
.sig_itlbmiss(except_itlbmiss),
.sig_immufault(except_immufault),
.sig_tick(sig_tick),
.branch_taken(branch_taken),
.icpu_ack_i(icpu_ack_i),
.icpu_err_i(icpu_err_i),
.dcpu_ack_i(dcpu_ack_i),
.dcpu_err_i(dcpu_err_i),
.genpc_freeze(genpc_freeze),
.id_freeze(id_freeze),
.ex_freeze(ex_freeze),
.wb_freeze(wb_freeze),
.if_stall(if_stall),
.if_pc(if_pc),
.id_pc(id_pc),
.lr_sav(lr_sav),
.flushpipe(flushpipe),
.extend_flush(extend_flush),
.except_type(except_type),
.except_start(except_start),
.except_started(except_started),
.except_stop(except_stop),
.ex_void(ex_void),
.spr_dat_ppc(spr_dat_ppc),
.spr_dat_npc(spr_dat_npc),
.datain(operand_b),
.du_dsr(du_dsr),
.epcr_we(epcr_we),
.eear_we(eear_we),
.esr_we(esr_we),
.pc_we(pc_we),
.epcr(epcr),
.eear(eear),
.esr(esr),
.lsu_addr(dcpu_adr_o),
.sr_we(sr_we),
.to_sr(to_sr),
.sr(sr),
.abort_ex(abort_ex)
);
//
// Instantiation of configuration registers
//
or1200_cfgr or1200_cfgr(
.spr_addr(spr_addr),
.spr_dat_o(spr_dat_cfgr)
);
endmodule
|
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 4, Question 1
*/
/**
* Testbench for behavioral model for Finite State Machine model of the
* sequential detector
*/
// Import the modules that will be tested for in this testbench
`include "seq_detector.v"
// IMPORTANT: To run this, try: ncverilog -f seq_detector.f +gui
module tb_seq_detect();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the seq_detector
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire error,match_op;
// ============================================================
// Declare "reg" signals: inputs to the DUT
reg inp,clock,reset;
// ============================================================
// Counter for loop to enumerate all the values of r
integer count;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen; Period=10ns
#5 clock = 0;
#5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of ee577bHw1q5model1() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "xor1model"
*/
seq_detect sqd (
// instance_name(signal name),
// Signal name can be the same as the instance name
inp,clock,reset,error,match_op);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// @ t=0; reset the sequence detector
inp = 1'd0;
reset = 1'd0;
// @ t=10,
#10
inp = 1'd0;
reset = 1'd1;
// @ t=20
#10
inp = 1'd0;
reset = 1'd0;
// @ t=30
#10
inp = 1'd1;
reset = 1'd0;
// @ t=40
#10
inp = 1'd1;
reset = 1'd0;
// @ t=50
#10
inp = 1'dx;
reset = 1'd0;
// @ t=60
#10
inp = 1'd0;
reset = 1'd0;
// @ t=70
#10
inp = 1'dz;
reset = 1'd0;
// @ t=80
#10
inp = 1'd0;
reset = 1'd0;
// @ t=90
#10
inp = 1'd1;
reset = 1'd0;
// @ t=100
#10
inp = 1'd1;
reset = 1'd0;
// @ t=110
#10
inp = 1'd0;
reset = 1'd0;
// @ t=120
#10
inp = 1'd1;
reset = 1'd0;
// @ t=130
#10
// Start of correct sequence
$display($time, " << Start of correct sequence >>");
inp = 1'd1;
reset = 1'd0;
// @ t=140
#10
inp = 1'd0;
reset = 1'd0;
// @ t=150
#10
inp = 1'd0;
reset = 1'd0;
// @ t=160
#10
inp = 1'd1;
reset = 1'd0;
// @ t=170
#10
inp = 1'd1;
reset = 1'd0;
// @ t=180
#10
inp = 1'd0;
reset = 1'd0;
// @ t=190
#10
inp = 1'd1;
reset = 1'd0;
// @ t=200
#10
inp = 1'd1;
reset = 1'd0;
// End of correct sequence
$display($time, " << End of correct sequence >>");
// @ t=210
#10
inp = 1'd1;
reset = 1'd0;
// @ t=220
#10
inp = 1'd1;
reset = 1'd0;
// @ t=230
#10
inp = 1'd0;
reset = 1'd0;
// @ t=240; reset the sequence detector
#10
inp = 1'd1;
reset = 1'd0;
// @ t=250
#10
inp = 1'd0;
reset = 1'd0;
// @ t=260
#10
inp = 1'd1;
reset = 1'd0;
// @ t=270
#10
inp = 1'd1;
reset = 1'd1;
// @ t=280
#10
inp = 1'd0;
reset = 1'd0;
// @ t=290
#10
inp = 1'd1;
reset = 1'd0;
// @ t=300
#10
inp = 1'dx;
reset = 1'd0;
// @ t=310
#10
inp = 1'd1;
reset = 1'd0;
// @ t=320
#10
inp = 1'd0;
reset = 1'd0;
// @ t=330
#10
inp = 1'd1;
reset = 1'd0;
// @ t=340
#10
inp = 1'dx;
reset = 1'd0;
// @ t=350
#10
inp = 1'dx;
reset = 1'd0;
// @ t=360
#10
inp = 1'dz;
reset = 1'd0;
// @ t=370
#10
inp = 1'd0;
reset = 1'd0;
// @ t=380
#10
inp = 1'd1;
reset = 1'd0;
// @ t=390
#10
inp = 1'd0;
reset = 1'd0;
// @ t=400
#10
inp = 1'd1;
reset = 1'd0;
// ============================================================
for(count=0;count<5'd24;count=count+1)
begin
#10
$display("Next");
inp=$random;
reset=1'd0;
end
// ============================================================
// @ t=650
#10
inp = 1'd1;
reset = 1'd0;
// @ t=660
#10
inp = 1'd1;
reset = 1'd0;
// @ t=670
#10
inp = 1'd1;
reset = 1'd0;
// @ t=680
#10
inp = 1'd1;
reset = 1'd0;
// @ t=690
#10
inp = 1'd1;
reset = 1'd0;
// @ t=700
#10
inp = 1'd0;
reset = 1'd0;
// @ t=710
#10
inp = 1'd0;
reset = 1'd0;
// @ t=720
#10
inp = 1'd0;
reset = 1'd0;
// Start of next correct sequence
// @ t=730
#10
inp = 1'd1;
reset = 1'd0;
// @ t=740
#10
inp = 1'd0;
reset = 1'd0;
// @ t=750
#10
inp = 1'd0;
reset = 1'd0;
// @ t=760
#10
inp = 1'd1;
reset = 1'd0;
// @ t=770
#10
inp = 1'd1;
reset = 1'd0;
// @ t=780
#10
inp = 1'd0;
reset = 1'd0;
// @ t=790
#10
inp = 1'd1;
reset = 1'd0;
// @ t=800
#10
inp = 1'd1;
reset = 1'd0;
// ============================================================
for(count=0;count<3'd5;count=count+1)
begin
#10
$display("Next");
inp=$random;
reset=1'd0;
end
// ============================================================
// @ t=890
#10
inp = 1'd1;
reset = 1'd0;
// @ t=900
#10
inp = 1'd1;
reset = 1'd0;
// @ t=910
#10
inp = 1'd0;
reset = 1'd0;
// @ t=920
#10
inp = 1'd0;
reset = 1'd0;
// @ t=930
#10
inp = 1'd1;
reset = 1'd0;
// @ t=940
#10
inp = 1'd1;
reset = 1'd0;
// @ t=950
#10
inp = 1'd1;
reset = 1'd0;
// Start of third good sequence
// @ t=960
#10
inp = 1'd1;
reset = 1'd0;
// @ t=970
#10
inp = 1'd0;
reset = 1'd0;
// @ t=980
#10
inp = 1'd0;
reset = 1'd0;
// @ t=990
#10
inp = 1'd1;
reset = 1'd0;
// @ t=1000
#10
inp = 1'd1;
reset = 1'd0;
// @ t=1010
#10
inp = 1'd0;
reset = 1'd0;
// @ t=1020
#10
inp = 1'd1;
reset = 1'd0;
// @ t=1030
#10
inp = 1'd1;
reset = 1'd0;
// End of third good sequence; start of 4th good sequence
// @ t=1040
#10
inp = 1'd1;
reset = 1'd0;
// @ t=1050
#10
inp = 1'd0;
reset = 1'd0;
// @ t=1060
#10
inp = 1'd0;
reset = 1'd0;
// @ t=1070
#10
inp = 1'd1;
reset = 1'd0;
// @ t=1080
#10
inp = 1'd1;
reset = 1'd0;
// @ t=1090
#10
inp = 1'd0;
reset = 1'd0;
// @ t=1100
#10
inp = 1'd1;
reset = 1'd0;
// @ t=1110
#10
inp = 1'd1;
reset = 1'd0;
// End of 4th good sequence
// @ t=1120
#10
inp = 1'd1;
reset = 1'd0;
// @ t=1130
#10
inp = 1'd0;
reset = 1'd0;
// @ t=1140
#10
inp = 1'd0;
reset = 1'd0;
// @ t=1150
#10
inp = 1'd1;
reset = 1'd0;
// @ t=1160
#10
inp = 1'd1;
reset = 1'd0;
// @ t=1170
#10
inp = 1'd0;
reset = 1'd0;
// @ t=1180
#10
inp = 1'd0;
reset = 1'd0;
// @ t=1190
#10
inp = 1'd1;
reset = 1'd0;
// Next pattern - faulty sequence; has last 7 bits
// @ t=1200
#10
inp = 1'd0;
reset = 1'd0;
// @ t=1200
#10
inp = 1'd0;
reset = 1'd0;
// @ t=1200
#10
inp = 1'd1;
reset = 1'd0;
// @ t=1200
#10
inp = 1'd1;
reset = 1'd0;
// @ t=1200
#10
inp = 1'd0;
reset = 1'd0;
// @ t=1200
#10
inp = 1'd1;
reset = 1'd0;
// @ t=1200
#10
inp = 1'd1;
reset = 1'd0;
// @ t=1200
#10
inp = 1'd1;
reset = 1'd0;
// Next pattern...
// @ t=1200
#10
inp = 1'd0;
reset = 1'd0;
// @ t=1200
#10
inp = 1'd0;
reset = 1'd0;
// @ t=1200
#10
inp = 1'd0;
reset = 1'd0;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S18_BEHAVIORAL_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S18_BEHAVIORAL_V
/**
* clkdlybuf4s18: Clock Delay Buffer 4-stage 0.18um length inner stage
* gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__clkdlybuf4s18 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S18_BEHAVIORAL_V |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Thu May 25 21:06:44 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/zed_dual_camera_test/zed_dual_camera_test.srcs/sources_1/bd/system/ip/system_clock_splitter_0_0/system_clock_splitter_0_0_sim_netlist.v
// Design : system_clock_splitter_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_clock_splitter_0_0,clock_splitter,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "clock_splitter,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_clock_splitter_0_0
(clk_in,
latch_edge,
clk_out);
input clk_in;
input latch_edge;
output clk_out;
wire clk_in;
wire clk_out;
wire latch_edge;
system_clock_splitter_0_0_clock_splitter U0
(.clk_in(clk_in),
.clk_out(clk_out),
.latch_edge(latch_edge));
endmodule
(* ORIG_REF_NAME = "clock_splitter" *)
module system_clock_splitter_0_0_clock_splitter
(clk_out,
latch_edge,
clk_in);
output clk_out;
input latch_edge;
input clk_in;
wire clk_i_1_n_0;
wire clk_in;
wire clk_out;
wire last_edge;
wire latch_edge;
LUT3 #(
.INIT(8'h6F))
clk_i_1
(.I0(latch_edge),
.I1(last_edge),
.I2(clk_out),
.O(clk_i_1_n_0));
FDRE #(
.INIT(1'b0))
clk_reg
(.C(clk_in),
.CE(1'b1),
.D(clk_i_1_n_0),
.Q(clk_out),
.R(1'b0));
FDRE #(
.INIT(1'b0))
last_edge_reg
(.C(clk_in),
.CE(1'b1),
.D(latch_edge),
.Q(last_edge),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/////////////////////////////////////////////////////////////////////
//// ////
//// Discrete Cosine Transform, MAC unit ////
//// ////
//// Virtex-II: Block-Multiplier is used ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: dct_mac.v,v 1.3 2002/10/31 12:50:03 rherveille Exp $
//
// $Date: 2002/10/31 12:50:03 $
// $Revision: 1.3 $
// $Author: rherveille $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: dct_mac.v,v $
// Revision 1.3 2002/10/31 12:50:03 rherveille
// *** empty log message ***
//
// Revision 1.2 2002/10/23 09:06:59 rherveille
// Improved many files.
// Fixed some bugs in Run-Length-Encoder.
// Removed dependency on ud_cnt and ro_cnt.
// Started (Motion)JPEG hardware encoder project.
//
//synopsys translate_off
//`include "timescale.v"
//synopsys translate_on
module dct_mac(clk, ena, dclr, din, coef, result);
//
// parameters
//
parameter dwidth = 8;
parameter cwidth = 16;
parameter mwidth = dwidth + cwidth; // multiplier result
parameter rwidth = mwidth +3; // add 3 bits for growth
//
// inputs & outputs
//
input clk; // clock input
input ena; // clock enable
input dclr; // start new mac (delayed 1 cycle)
input [dwidth-1:0] din; // data input
input [cwidth-1:0] coef; // coefficient input
output [rwidth-1:0] result; // mac-result
reg [rwidth -1:0] result;
//
// variables
//
wire [mwidth-1:0] idin;
wire [mwidth-1:0] icoef;
reg [mwidth -1:0] mult_res /* synthesis syn_multstyle="block_mult" syn_pipeline=1*/ ;
wire [rwidth -1:0] ext_mult_res;
//
// module body
//
assign icoef = { {(mwidth-cwidth){coef[cwidth-1]}}, coef};
assign idin = { {(mwidth-dwidth){din[dwidth-1]}}, din};
// generate multiplier structure
always @(posedge clk)
if(ena)
mult_res <= #1 icoef * idin;
assign ext_mult_res = { {3{mult_res[mwidth-1]}}, mult_res};
// generate adder structure
always @(posedge clk)
if(ena)
if(dclr)
result <= #1 ext_mult_res;
else
result <= #1 ext_mult_res + result;
endmodule
|
`include "project_defines.v"
module bipolar_micro_stepper #(
parameter CLOCK_DIV = 16
)(
input clk,
input rst,
//Control
input i_go,
output o_busy,
input i_stop,
//Position
input [31:0] i_current_position,
output [31:0] o_current_position,
input [7:0] i_step_pos,
output [7:0] o_step_pos,
output [31:0] o_step_count,
output reg o_move_strobe,
//Step Modifiers
input i_continuous,
input i_direction,
input [31:0] i_steps,
input [31:0] i_micro_step_hold,
//Counts
input [31:0] i_current_period,
//Pins
output o_hbridge0_l,
output o_hbridge0_r,
output o_hbridge1_l,
output o_hbridge1_r
);
//Local Parameters
localparam IDLE = 4'h0;
localparam PREPARE_STEP = 4'h1;
localparam PROCESS_STEP = 4'h2;
localparam FINISHED = 4'h3;
localparam PWM_PERIOD = 256;
localparam PWM_STEP_POS_MAX = 16;
//Registers/Wires
reg [3:0] state = IDLE;
reg direction;
reg continuous;
reg [31:0] step_pos;
wire [31:0] in_steps;
wire [31:0] in_micro_steps;
reg [31:0] current_period_count;
reg [31:0] current_position;
reg [31:0] step_count;
reg [31:0] total_step_count;
reg [31:0] micro_step_count ;
reg [31:0] final_micro_step_count ;
wire [3:0] step_path [7:0];
wire [7:0] micro_step_duty [15:0];
wire [31:0] step_inc_map [3:0];
wire [31:0] max_pos_map [3:0];
wire [1:0] micro_step_hbridge_pwm [7:0];
wire [7:0] micro_step_hbridge_dir;
reg micro_step_pwm_en;
wire [31:0] micro_step_pwm_duty;
wire [31:0] micro_step_pwm_period;
wire micro_step_pwm;
wire [31:0] micro_current_period;
reg [31:0] micro_current_period_count;
reg [3:0] hbridge_map;
reg [31:0] pwm_step_pos;
wire pwm_direction;
wire [31:0] steps_left;
wire [31:0] pwm_period;
wire [31:0] ms_step_pwm_duty;
//Submodules
pwm micro_pwm(
.clk (clk ),
.rst (rst ),
.en (micro_step_pwm_en ),
.period (pwm_period ),
.duty_cycle (ms_step_pwm_duty ),
.out (micro_step_pwm )
);
assign pwm_period = PWM_PERIOD << CLOCK_DIV;
assign ms_step_pwm_duty = micro_step_pwm_duty << CLOCK_DIV;
//Asynchronous Logic
assign o_busy = (i_go | (state != IDLE));
assign o_step_pos = step_pos;
assign o_current_position = current_position;
assign steps_left = total_step_count - step_count;
assign step_path[0] = 4'b1000;
assign step_path[1] = 4'b1010;
assign step_path[2] = 4'b0010;
assign step_path[3] = 4'b0110;
assign step_path[4] = 4'b0100;
assign step_path[5] = 4'b0101;
assign step_path[6] = 4'b0001;
assign step_path[7] = 4'b1001;
assign micro_step_duty[0] = 8'h00;
assign micro_step_duty[1] = 8'h18;
assign micro_step_duty[2] = 8'h31;
assign micro_step_duty[3] = 8'h4A;
assign micro_step_duty[4] = 8'h61;
assign micro_step_duty[5] = 8'h78;
assign micro_step_duty[6] = 8'h8D;
assign micro_step_duty[7] = 8'hA1;
assign micro_step_duty[8] = 8'hB4;
assign micro_step_duty[9] = 8'hC5;
assign micro_step_duty[10] = 8'hD4;
assign micro_step_duty[11] = 8'hE0;
assign micro_step_duty[12] = 8'hEB;
assign micro_step_duty[13] = 8'hF4;
assign micro_step_duty[14] = 8'hFA;
assign micro_step_duty[15] = 8'hFD;
assign micro_step_hbridge_pwm[0] = 2'h0;
assign micro_step_hbridge_pwm[1] = 2'h1;
assign micro_step_hbridge_pwm[2] = 2'h3;
assign micro_step_hbridge_pwm[3] = 2'h2;
assign micro_step_hbridge_pwm[4] = 2'h1;
assign micro_step_hbridge_pwm[5] = 2'h0;
assign micro_step_hbridge_pwm[6] = 2'h2;
assign micro_step_hbridge_pwm[7] = 2'h3;
assign micro_step_hbridge_dir[0] = 1'b0; //pos neutral
assign micro_step_hbridge_dir[1] = 1'b1; //pos pos
assign micro_step_hbridge_dir[2] = 1'b0; //neutral pos
assign micro_step_hbridge_dir[3] = 1'b1; //neg pos
assign micro_step_hbridge_dir[4] = 1'b0; //neg neutral
assign micro_step_hbridge_dir[5] = 1'b1; //neg neg
assign micro_step_hbridge_dir[6] = 1'b0; //neutral neg
assign micro_step_hbridge_dir[7] = 1'b1; //pos neg
assign o_hbridge0_l = hbridge_map[3];
assign o_hbridge0_r = hbridge_map[2];
assign o_hbridge1_l = hbridge_map[1];
assign o_hbridge1_r = hbridge_map[0];
assign micro_step_pwm_duty = {24'h0, micro_step_duty[pwm_step_pos]};
assign in_steps = {8'h0, i_steps[31:8]};
assign in_micro_steps = {28'h0, i_steps[7:4]};
assign pwm_direction = (micro_step_hbridge_dir[step_pos] ~^ direction);
assign micro_current_period = (i_current_period >> 4); //divide the step period by 16 so that there is enough time to execute each of the micro step
assign o_step_count = step_count;
//Synchronous Logig
always @ (posedge clk) begin
if (rst) begin
state <= IDLE;
step_pos <= 0;
current_position <= 0;
current_period_count <= 0;
step_count <= 0;
total_step_count <= 0;
final_micro_step_count <= 0;
micro_step_count <= 0;
micro_step_pwm_en <= 0;
hbridge_map <= 4'b0000;
direction <= 0;
continuous <= 0;
o_move_strobe <= 0;
end
else begin
o_move_strobe <= 0;
if (micro_current_period_count < micro_current_period) begin
micro_current_period_count <= micro_current_period_count + 1;
end
case (state)
IDLE: begin
hbridge_map <= 4'b0000;
current_position <= i_current_position;
step_pos <= i_step_pos;
current_period_count <= 0;
step_count <= 0;
micro_step_count <= 0;
if (i_go) begin
hbridge_map <= step_path[step_pos];
total_step_count <= in_steps;
final_micro_step_count <= in_micro_steps;
direction <= i_direction;
continuous <= i_continuous;
state <= PREPARE_STEP;
end
end
PREPARE_STEP: begin
if (i_stop || (step_count >= total_step_count)) begin
//we are above the amount of steps given to us, we are done
state <= FINISHED;
end
else begin
current_period_count <= 0;
micro_current_period_count<= 0;
micro_step_pwm_en <= 0;
hbridge_map <= step_path[step_pos];
o_move_strobe <= 1;
state <= PROCESS_STEP;
if (pwm_direction) begin
pwm_step_pos <= 0;
end
else begin
pwm_step_pos <= PWM_STEP_POS_MAX - 1;
end
end
end
PROCESS_STEP: begin
micro_step_pwm_en <= 1;
//Micro Step Count
if (micro_current_period_count >= micro_current_period) begin
o_move_strobe <= 1;
if (pwm_direction) begin
pwm_step_pos <= pwm_step_pos + 1;
end
else begin
pwm_step_pos <= pwm_step_pos - 1;
end
micro_current_period_count <= 0;
end
//Full Step Period Count
if (current_period_count < i_current_period) begin
current_period_count <= current_period_count + 1;
if ((current_period_count + i_micro_step_hold) < i_current_period) begin
hbridge_map[micro_step_hbridge_pwm[step_pos]] <= micro_step_pwm;
end
else begin
hbridge_map <= step_path[step_pos];
end
end
else begin
state <= PREPARE_STEP;
hbridge_map <= step_path[step_pos];
if (direction) begin
//Positive
if (step_pos >= 7) begin
step_pos <= 0;
end
else begin
step_pos <= step_pos + 1;
end
end
else begin
//Negative
if (step_pos == 0) begin
step_pos <= 7;
end
else begin
step_pos <= step_pos - 1;
end
end
if (step_count < total_step_count) begin
micro_step_count <= PWM_STEP_POS_MAX;
end
else if (final_micro_step_count > 0) begin
micro_step_count <= final_micro_step_count;
final_micro_step_count <= 0;
end
else begin
state <= FINISHED;
end
if (!continuous) begin
step_count <= step_count + 1;
end
end
end
FINISHED: begin
hbridge_map <= 4'b0000;
if (!i_go) begin
state <= IDLE;
end
end
default: begin
state <= FINISHED;
end
endcase
if (i_stop) begin
state <= IDLE;
end
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:49:08 02/22/2015
// Design Name:
// Module Name: NormaliseProdMult
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module NormaliseProdMult(
input [32:0] zout_Multiply,
input [49:0] productout_Multiply,
input clock,
input idle_Multiply,
output reg idle_NormaliseProd,
output reg [32:0] zout_NormaliseProd,
output reg [49:0] productout_NormaliseProd
);
parameter no_idle = 1'b0,
put_idle = 1'b1;
wire z_sign;
wire [7:0] z_exponent;
wire [26:0] z_mantissa;
assign z_sign = zout_Multiply[32];
assign z_exponent = zout_Multiply[31:24];
assign z_mantissa = {zout_Multiply[23:0]};
always @ (posedge clock) begin
idle_NormaliseProd <= idle_Multiply;
if (idle_Multiply == no_idle) begin
// This case will never arise. This is because for input with exponent less than -12 multiply isn't used.
if ($signed(z_exponent) < -126) begin
zout_NormaliseProd[32] <= z_sign;
zout_NormaliseProd[31:24] <= z_exponent + 1;
zout_NormaliseProd[23:0] <= z_mantissa;
productout_NormaliseProd <= productout_Multiply >> 1;
end
// This could be problematic. Will have to test for average number of cycles
// Current solution is to hard code for all cases like normalisation in addition.
else if (productout_Multiply[49] == 0) begin
zout_NormaliseProd[32] <= z_sign;
zout_NormaliseProd[31:24] <= z_exponent - 1;
zout_NormaliseProd[23:0] <= {productout_Multiply[48:25]};
productout_NormaliseProd <= productout_Multiply << 1;
end
else begin
zout_NormaliseProd[32] <= z_sign;
zout_NormaliseProd[31:24] <= z_exponent;
zout_NormaliseProd[23:0] <= {productout_Multiply[49:26]};
productout_NormaliseProd <= productout_Multiply;
end
end
else begin
zout_NormaliseProd <= zout_Multiply;
end
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 20 02:53:15 2016
/////////////////////////////////////////////////////////////
module GeAr_N16_R4_P4_DW01_add_J63_0 ( A, B, CI, SUM, CO );
input [8:0] A;
input [8:0] B;
output [8:0] SUM;
input CI;
output CO;
wire n38, n39, n40, n41, n42, n43, n44, n45;
NOR2X1TS U13 ( .A(A[3]), .B(B[3]), .Y(n40) );
OAI211X1TS U14 ( .A0(A[1]), .A1(B[1]), .B0(B[0]), .C0(A[0]), .Y(n38) );
OAI2BB1X1TS U15 ( .A0N(B[1]), .A1N(A[1]), .B0(n38), .Y(n39) );
AOI222X1TS U16 ( .A0(B[2]), .A1(A[2]), .B0(B[2]), .B1(n39), .C0(A[2]), .C1(
n39), .Y(n41) );
OAI2BB2XLTS U17 ( .B0(n41), .B1(n40), .A0N(A[3]), .A1N(B[3]), .Y(n42) );
CMPR32X2TS U18 ( .A(A[4]), .B(B[4]), .C(n42), .CO(n43), .S(SUM[4]) );
CMPR32X2TS U19 ( .A(A[5]), .B(B[5]), .C(n43), .CO(n44), .S(SUM[5]) );
CMPR32X2TS U20 ( .A(A[6]), .B(B[6]), .C(n44), .CO(n45), .S(SUM[6]) );
CMPR32X2TS U21 ( .A(A[7]), .B(B[7]), .C(n45), .CO(SUM[8]), .S(SUM[7]) );
initial $sdf_annotate("GeAr_N16_R4_P4_syn.sdf");
endmodule
module GeAr_N16_R4_P4_DW01_add_J63_1 ( A, B, CI, SUM, CO );
input [7:0] A;
input [7:0] B;
output [7:0] SUM;
input CI;
output CO;
wire n35, n36, n37, n38, n39, n40, n41, n42, n43;
NOR2XLTS U13 ( .A(A[3]), .B(B[3]), .Y(n37) );
XOR2XLTS U14 ( .A(B[7]), .B(n41), .Y(SUM[7]) );
OAI2BB2X1TS U15 ( .B0(n38), .B1(n37), .A0N(A[3]), .A1N(B[3]), .Y(n42) );
AOI222X2TS U16 ( .A0(B[2]), .A1(A[2]), .B0(B[2]), .B1(n36), .C0(A[2]), .C1(
n36), .Y(n38) );
ADDFHX2TS U17 ( .A(A[5]), .B(B[5]), .CI(n39), .CO(n43), .S(SUM[5]) );
OAI2BB1X1TS U18 ( .A0N(B[1]), .A1N(A[1]), .B0(n35), .Y(n36) );
XOR2X1TS U19 ( .A(A[7]), .B(n40), .Y(n41) );
OAI211X1TS U20 ( .A0(A[1]), .A1(B[1]), .B0(B[0]), .C0(A[0]), .Y(n35) );
CMPR32X2TS U21 ( .A(A[4]), .B(B[4]), .C(n42), .CO(n39), .S(SUM[4]) );
CMPR32X2TS U22 ( .A(A[6]), .B(B[6]), .C(n43), .CO(n40), .S(SUM[6]) );
initial $sdf_annotate("GeAr_N16_R4_P4_syn.sdf");
endmodule
module GeAr_N16_R4_P4 ( in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
wire n2, n3, n4, n5, n6, n7, n8, n9, SYNOPSYS_UNCONNECTED_1,
SYNOPSYS_UNCONNECTED_2, SYNOPSYS_UNCONNECTED_3,
SYNOPSYS_UNCONNECTED_4, SYNOPSYS_UNCONNECTED_5,
SYNOPSYS_UNCONNECTED_6, SYNOPSYS_UNCONNECTED_7,
SYNOPSYS_UNCONNECTED_8;
GeAr_N16_R4_P4_DW01_add_J63_0 add_x_3 ( .A({1'b0, in1[15:8]}), .B({1'b0,
in2[15:8]}), .CI(1'b0), .SUM({res[16:12], SYNOPSYS_UNCONNECTED_1,
SYNOPSYS_UNCONNECTED_2, SYNOPSYS_UNCONNECTED_3, SYNOPSYS_UNCONNECTED_4}) );
GeAr_N16_R4_P4_DW01_add_J63_1 add_x_2 ( .A(in1[11:4]), .B(in2[11:4]), .CI(
1'b0), .SUM({res[11:8], SYNOPSYS_UNCONNECTED_5, SYNOPSYS_UNCONNECTED_6,
SYNOPSYS_UNCONNECTED_7, SYNOPSYS_UNCONNECTED_8}) );
XOR2XLTS U2 ( .A(n3), .B(n2), .Y(res[7]) );
XOR2XLTS U3 ( .A(in1[7]), .B(in2[7]), .Y(n2) );
ADDHXLTS U4 ( .A(in2[0]), .B(in1[0]), .CO(n9), .S(res[0]) );
CMPR32X2TS U5 ( .A(in1[6]), .B(in2[6]), .C(n4), .CO(n3), .S(res[6]) );
CMPR32X2TS U6 ( .A(in1[5]), .B(in2[5]), .C(n5), .CO(n4), .S(res[5]) );
CMPR32X2TS U7 ( .A(in1[4]), .B(in2[4]), .C(n6), .CO(n5), .S(res[4]) );
CMPR32X2TS U8 ( .A(in1[3]), .B(in2[3]), .C(n7), .CO(n6), .S(res[3]) );
CMPR32X2TS U9 ( .A(in1[2]), .B(in2[2]), .C(n8), .CO(n7), .S(res[2]) );
CMPR32X2TS U10 ( .A(in1[1]), .B(in2[1]), .C(n9), .CO(n8), .S(res[1]) );
initial $sdf_annotate("GeAr_N16_R4_P4_syn.sdf");
endmodule
|
module top;
function automatic [31:0] operation1;
input [4:0] rounds;
input integer num;
integer i;
begin
begin : shadow
integer rounds;
rounds = 0;
end
for (i = 0; i < rounds; i = i + 1)
num = num * 2;
operation1 = num;
end
endfunction
function automatic [31:0] operation2;
input [4:0] var;
input integer num;
begin
var[0] = var[0] ^ 1;
operation2 = num * var;
end
endfunction
function automatic [31:0] operation3;
input [4:0] rounds;
input integer num;
reg [4:0] rounds;
integer i;
begin
begin : shadow
integer rounds;
rounds = 0;
end
for (i = 0; i < rounds; i = i + 1)
num = num * 2;
operation3 = num;
end
endfunction
wire [31:0] a;
assign a = 2;
parameter A = 3;
wire [31:0] x1;
assign x1 = operation1(A, a);
wire [31:0] x2;
assign x2 = operation2(A, a);
wire [31:0] x3;
assign x3 = operation3(A, a);
// `define VERIFY
`ifdef VERIFY
assert property (a == 2);
assert property (A == 3);
assert property (x1 == 16);
assert property (x2 == 4);
assert property (x3 == 16);
`endif
endmodule
|
`define MSG_REQ 1'b1
`define MSG_RESP 1'b0
`define CMD_PA 4'b0000
`define CMD_CL 4'b0001
`define CMD_W 4'b0010
`define CMD_R 4'b0011
`define CMD_S 4'b0100
`define CMD_F 4'b0101
`define CMD_IN 4'b0110
`define CMD_CPD 4'b1000
`define CMD_CPR 4'b1001
`define CMD_CPF 4'b1010
`define CMD_CPS 4'b1011
`define CMD_EN 4'b0001
`define CMD_OK 4'b0010
`define CMD_PE 4'b0011
`define CMD_NO 4'b0100
module iobus(
input clk_sys,
input clk_uart,
input rxd,
output txd,
output zg,
input zw,
input rcl,
output dpa,
input rs,
input rf,
input rok,
input rpe,
input rqb,
input rpn,
input [0:3] rnb,
input [0:15] rad,
input [0:15] rdt,
output dw,
output dr,
output din,
output dok,
output den,
output dpe,
output dpn,
output [0:3] dnb,
output [0:15] dad,
output [0:15] ddt,
input [0:15] w,
input [0:3] rotary_pos,
input [0:9] indicators,
output [0:3] rotary_out,
output rotary_trig,
output [0:15] keys,
output keys_trig,
output [0:3] fn,
output fn_v,
output fn_trig
);
parameter CLK_UART_HZ;
parameter UART_BAUD;
// --- UART --------------------------------------------------------------
wire uart_tx_ready;
wire uart_rx_ready;
wire uart_tx_send;
wire [0:7] uart_rx_byte;
wire [0:7] uart_tx_byte;
uart #(
.baud(UART_BAUD),
.clk_speed(CLK_UART_HZ)
) UART_IOB(
.clk(clk_uart),
.rx_byte(uart_rx_byte),
.rx_ready(uart_rx_ready),
.rxd(rxd),
.send(uart_tx_send),
.tx_byte(uart_tx_byte),
.tx_ready(uart_tx_ready),
.txd(txd)
);
// -----------------------------------------------------------------------
// --- TO FPGA -----------------------------------------------------------
// -----------------------------------------------------------------------
// --- Message receiver --------------------------------------------------
wire rx_ready;
wire rx_r, rx_w, rx_in, rx_pa, rx_ok, rx_pe, rx_en;
wire rx_cpd, rx_cpr, rx_cpf, rx_cps;
wire [0:7] rx_a1;
wire [0:15] rx_a2;
wire [0:15] rx_a3;
msg_rx MSG_RX(
.clk_sys(clk_sys),
.data_in(uart_rx_byte),
.data_in_ready(uart_rx_ready),
.ready(rx_ready),
.r(rx_r),
.w(rx_w),
.in(rx_in),
.pa(rx_pa),
.ok(rx_ok),
.pe(rx_pe),
.en(rx_en),
.cpd(rx_cpd),
.cpr(rx_cpr),
.cpf(rx_cpf),
.cps(rx_cps),
.a1(rx_a1),
.a2(rx_a2),
.a3(rx_a3)
);
// --- PA interrupt driver -----------------------------------------------
assign dpa = rx_ready & rx_pa;
// --- CP input driver ---------------------------------------------------
drv_cp_in DRV_CP_IN(
.ready(rx_ready),
.cpd(rx_cpd),
.cpr(rx_cpr),
.cpf(rx_cpf),
.a1(rx_a1),
.a3(rx_a3),
.rotary_out(rotary_out),
.rotary_trig(rotary_trig),
.keys(keys),
.keys_trig(keys_trig),
.fn(fn),
.fn_v(fn_v),
.fn_trig(fn_trig)
);
// --- CP output driver --------------------------------------------------
wire send_cp = rx_ready & rx_cps;
// --- Bus timeout -------------------------------------------------------
reg [0:4] timeout_cnt = 5'b0;
always @ (posedge clk_sys) begin
if (rok) begin
timeout_cnt <= 5'd0;
end else if (dw | dr | din) begin
if (timeout_cnt != 5'b11111) begin
timeout_cnt <= timeout_cnt + 1'd1;
end
end else begin
timeout_cnt <= 5'd0;
end
end
wire timeout = (timeout_cnt == 5'b11111);
// --- Bus request driver ------------------------------------------------
wire [0:15] ddt_req;
drv_bus_req DRV_BUS_REQ(
.clk_sys(clk_sys),
.ready(rx_ready),
.r(rx_r),
.w(rx_w),
.in(rx_in),
.a1(rx_a1),
.a2(rx_a2),
.a3(rx_a3),
.zw(zw),
.zg(zg),
.ans_any(rok | timeout),
.dw(dw),
.dr(dr),
.din(din),
.dpn(dpn),
.dnb(dnb),
.dad(dad),
.ddt(ddt_req)
);
// --- Bus response driver -----------------------------------------------
wire io_req = (rs | rf) & ~rad[15];
wire [0:15] ddt_resp;
drv_bus_resp DRV_BUS_RESP(
.clk_sys(clk_sys),
.ready(rx_ready),
.ok(rx_ok),
.en(rx_en),
.pe(rx_pe),
.a3(rx_a3),
.req(io_req),
.dok(dok),
.den(den),
.dpe(dpe),
.ddt(ddt_resp)
);
// -----------------------------------------------------------------------
// --- FROM FPGA ---------------------------------------------------------
// -----------------------------------------------------------------------
// --- Bus command encoder -----------------------------------------------
wire [0:7] enc_cmd;
msg_cmd_enc MSG_CMD_ENC(
.cmd(enc_cmd),
.f(rf),
.s(rs),
.r(dr),
.w(dw),
.in(din),
.ok(rok),
.timeout(timeout),
.pe(rpe)
);
// --- Bus receiver ------------------------------------------------------
wire send_req = io_req;
wire send_resp = (rok | timeout) & (dw | dr | din);
wire tx_ena_bus;
wire tx_trig_bus;
wire [0:7] tx_bus_cmd;
wire [0:7] tx_bus_a1;
wire [0:15] tx_bus_a2;
wire [0:15] tx_bus_a3;
recv_bus RECV_BUS(
.clk_sys(clk_sys),
.send_req(send_req),
.send_resp(send_resp),
.tx_ena_bus(tx_ena_bus),
.tx_trig_bus(tx_trig_bus),
.rqb(rqb),
.rpn(rpn),
.rnb(rnb),
.rad(rad),
.rdt(rdt),
.enc_cmd(enc_cmd),
.tx_bus_cmd(tx_bus_cmd),
.tx_bus_a1(tx_bus_a1),
.tx_bus_a2(tx_bus_a2),
.tx_bus_a3(tx_bus_a3)
);
// --- CP status receiver ------------------------------------------------
wire tx_ena_cp;
wire tx_trig_cp;
wire [0:7] tx_cp_cmd;
wire [0:15] tx_cp_a2;
wire [0:15] tx_cp_a3;
recv_cp RECV_CP(
.clk_sys(clk_sys),
.send_cp(send_cp),
.tx_ena_cp(tx_ena_cp),
.w(w),
.indicators(indicators),
.rotary_pos(rotary_pos),
.tx_trig_cp(tx_trig_cp),
.tx_cp_cmd(tx_cp_cmd),
.tx_cp_a2(tx_cp_a2),
.tx_cp_a3(tx_cp_a3)
);
// --- Reset receiver ----------------------------------------------------
wire tx_ena_cl;
wire tx_trig_cl;
wire [0:7] tx_reset_cmd;
recv_cl RECV_CL(
.clk_sys(clk_sys),
.rcl(rcl),
.tx_ena_cl(tx_ena_cl),
.tx_trig_cl(tx_trig_cl),
.tx_reset_cmd(tx_reset_cmd)
);
// --- Mesage sender -----------------------------------------------------
wire [0:7] tx_cmd = tx_bus_cmd | tx_cp_cmd | tx_reset_cmd;
wire [0:7] tx_a1 = tx_bus_a1;
wire [0:15] tx_a2 = tx_bus_a2 | tx_cp_a2;
wire [0:15] tx_a3 = tx_bus_a3 | tx_cp_a3;
msg_tx MSG_TX(
.clk_sys(clk_sys),
.uart_data(uart_tx_byte),
.uart_send(uart_tx_send),
.uart_ready(uart_tx_ready),
.trig({tx_trig_cl, tx_trig_cp, tx_trig_bus}),
.ena({tx_ena_cl, tx_ena_cp, tx_ena_bus}),
.cmd(tx_cmd),
.a1(tx_a1),
.a2(tx_a2),
.a3(tx_a3)
);
// -----------------------------------------------------------------------
assign ddt = ddt_req | ddt_resp;
endmodule
// vim: tabstop=2 shiftwidth=2 autoindent noexpandtab
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
// Testbench for behavioral model for the ALU
// Import the modules that will be tested for in this testbench
`include "mult.v"
`include "control.h"
// IMPORTANT: To run this, try: ncverilog -f alu.f +gui
module tb_alu();
// ============================================================
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the ALU
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// result output signal
wire [0:127] res;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// reg_A
reg [0:127] r_A;
// reg_B
reg [0:127] r_B;
// Control signal bits - ww; ctrl_ww
reg [0:1] c_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform; alu_op
*/
reg [0:4] a_op;
// Bus/Signal to contain the expected output/result
reg [0:127] e_r;
// ============================================================
// Defining constants: parameter [name_of_constant] = value;
//parameter size_of_input = 6'd32;
// ============================================================
/**
* Instantiate an instance of alu() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "rg"
*/
alu a_l_u (
// instance_name(signal name),
// Signal name can be the same as the instance name
// alu (reg_A,reg_B,ctrl_ppp,ctrl_ww,alu_op,result)
r_A,r_B,c_ww,a_op,res);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// aluwmuleu AND w8
/*
r_A=31'h0402050f;
r_B=31'h0301020c;
e_r=31'h000c0006;
c_ww=`w8;
a_op=`aluwmuleu;
*/
r_A=128'h0402030405060708f00a0b0cff0eff00;
r_B=128'h03010202030303031004f505ff09fe10;
e_r=128'h000c0006000f00150f000a87fe01fd02;
c_ww=`w8;
a_op=`aluwmuleu;
#10
// aluwmuleu AND w16
r_A=128'h000100020000ffff000f10bff103ffff;
r_B=128'h000200040006ffff000c100000120014;
e_r=128'h0000000200000000000000b40010f236;
c_ww=`w16;
a_op=`aluwmuleu;
// ======================================
#10
// aluwmulou AND w8
r_A=128'h0102030405060708090aff0c0dff0fff;
r_B=128'h01010202030303031004040508000fff;
e_r=128'h00020008001200180028003c0000fe01;
c_ww=`w8;
a_op=`aluwmulou;
#10
// aluwmulou AND w16
r_A=128'h0001000200000008000f10bff103ffff;
r_B=128'h0002000400060008000c001000120014;
e_r=128'h000000080000004000010bf00013ffec;
c_ww=`w16;
a_op=`aluwmulou;
// ======================================
#10
// aluwmulos AND w8
/*
r_A=128'h010330405060708090aff0c0dff0ff02;
r_B=128'h01fa0202030303031004040508000f08;
*/
r_A=128'h0180010501f9015301040100013c0100;
r_B=128'h017f010901fa010001fd01f101b80100;
e_r=128'hc080002d002a0000fff40000ef200000;
c_ww=`w8;
a_op=`aluwmulos;
#10
// aluwmulos AND w16
r_A=128'h1111000211118000111120541111fff9;
r_B=128'hffff0004ffff7fffffff0000fffffffd;
e_r=128'h00000008c00080000000000000000015;
c_ww=`w16;
a_op=`aluwmulos;
// ======================================
#10
// aluwmules AND w8
/*
r_A=128'h0180010501f9015301040100013c0100;
r_B=128'h017f010901fa010001fd01f101b80100;
*/
r_A=128'h80010501f9015301040100013c010001;
r_B=128'h7f010901fa010001fd01f101b8010001;
e_r=128'hc080002d002a0000fff40000ef200000;
c_ww=`w8;
a_op=`aluwmules;
#10
// aluwmules AND w16
/*
r_A=128'h1111000211118000111120541111fff9;
r_B=128'hffff0004ffff7fffffff0000fffffffd;
*/
r_A=128'h000211118000111120541111fff91111;
r_B=128'h0004ffff7fffffff0000fffffffdffff;
e_r=128'h00000008c00080000000000000000015;
c_ww=`w16;
a_op=`aluwmules;
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 15:31:22 2016
/////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_W64_EW11_SW52 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [63:0] Data_MX;
input [63:0] Data_MY;
input [1:0] round_mode;
output [63:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_add_overflow_flag, FSM_selector_A, FSM_selector_C,
Exp_module_Overflow_flag_A, Sgf_operation_ODD1_left_N51,
Sgf_operation_ODD1_left_N50, Sgf_operation_ODD1_left_N49,
Sgf_operation_ODD1_left_N48, Sgf_operation_ODD1_left_N47,
Sgf_operation_ODD1_left_N46, Sgf_operation_ODD1_left_N45,
Sgf_operation_ODD1_left_N44, Sgf_operation_ODD1_left_N43,
Sgf_operation_ODD1_left_N42, Sgf_operation_ODD1_left_N41,
Sgf_operation_ODD1_left_N40, Sgf_operation_ODD1_left_N39,
Sgf_operation_ODD1_left_N38, Sgf_operation_ODD1_left_N37,
Sgf_operation_ODD1_left_N36, Sgf_operation_ODD1_left_N35,
Sgf_operation_ODD1_left_N34, Sgf_operation_ODD1_left_N33,
Sgf_operation_ODD1_left_N32, Sgf_operation_ODD1_left_N31,
Sgf_operation_ODD1_left_N30, Sgf_operation_ODD1_left_N29,
Sgf_operation_ODD1_left_N28, Sgf_operation_ODD1_left_N27,
Sgf_operation_ODD1_left_N26, Sgf_operation_ODD1_left_N25,
Sgf_operation_ODD1_left_N24, Sgf_operation_ODD1_left_N23,
Sgf_operation_ODD1_left_N22, Sgf_operation_ODD1_left_N21,
Sgf_operation_ODD1_left_N20, Sgf_operation_ODD1_left_N19,
Sgf_operation_ODD1_left_N18, Sgf_operation_ODD1_left_N17,
Sgf_operation_ODD1_left_N16, Sgf_operation_ODD1_left_N15,
Sgf_operation_ODD1_left_N14, Sgf_operation_ODD1_left_N13,
Sgf_operation_ODD1_left_N12, Sgf_operation_ODD1_left_N11,
Sgf_operation_ODD1_left_N10, Sgf_operation_ODD1_left_N9,
Sgf_operation_ODD1_left_N8, Sgf_operation_ODD1_left_N7,
Sgf_operation_ODD1_left_N6, Sgf_operation_ODD1_left_N5,
Sgf_operation_ODD1_left_N4, Sgf_operation_ODD1_left_N3,
Sgf_operation_ODD1_left_N2, Sgf_operation_ODD1_left_N1,
Sgf_operation_ODD1_left_N0, Sgf_operation_ODD1_right_N53,
Sgf_operation_ODD1_right_N52, Sgf_operation_ODD1_right_N51,
Sgf_operation_ODD1_right_N50, Sgf_operation_ODD1_right_N49,
Sgf_operation_ODD1_right_N48, Sgf_operation_ODD1_right_N47,
Sgf_operation_ODD1_right_N46, Sgf_operation_ODD1_right_N45,
Sgf_operation_ODD1_right_N44, Sgf_operation_ODD1_right_N43,
Sgf_operation_ODD1_right_N42, Sgf_operation_ODD1_right_N41,
Sgf_operation_ODD1_right_N40, Sgf_operation_ODD1_right_N39,
Sgf_operation_ODD1_right_N38, Sgf_operation_ODD1_right_N37,
Sgf_operation_ODD1_right_N36, Sgf_operation_ODD1_right_N35,
Sgf_operation_ODD1_right_N34, Sgf_operation_ODD1_right_N33,
Sgf_operation_ODD1_right_N32, Sgf_operation_ODD1_right_N31,
Sgf_operation_ODD1_right_N30, Sgf_operation_ODD1_right_N29,
Sgf_operation_ODD1_right_N28, Sgf_operation_ODD1_right_N27,
Sgf_operation_ODD1_right_N26, Sgf_operation_ODD1_right_N25,
Sgf_operation_ODD1_right_N24, Sgf_operation_ODD1_right_N23,
Sgf_operation_ODD1_right_N22, Sgf_operation_ODD1_right_N21,
Sgf_operation_ODD1_right_N20, Sgf_operation_ODD1_right_N19,
Sgf_operation_ODD1_right_N18, Sgf_operation_ODD1_right_N17,
Sgf_operation_ODD1_right_N16, Sgf_operation_ODD1_right_N15,
Sgf_operation_ODD1_right_N14, Sgf_operation_ODD1_right_N13,
Sgf_operation_ODD1_right_N12, Sgf_operation_ODD1_right_N11,
Sgf_operation_ODD1_right_N10, Sgf_operation_ODD1_right_N9,
Sgf_operation_ODD1_right_N8, Sgf_operation_ODD1_right_N7,
Sgf_operation_ODD1_right_N6, Sgf_operation_ODD1_right_N5,
Sgf_operation_ODD1_right_N4, Sgf_operation_ODD1_right_N3,
Sgf_operation_ODD1_right_N2, Sgf_operation_ODD1_right_N1,
Sgf_operation_ODD1_right_N0, Sgf_operation_ODD1_middle_N55,
Sgf_operation_ODD1_middle_N54, Sgf_operation_ODD1_middle_N53,
Sgf_operation_ODD1_middle_N52, Sgf_operation_ODD1_middle_N51,
Sgf_operation_ODD1_middle_N50, Sgf_operation_ODD1_middle_N49,
Sgf_operation_ODD1_middle_N48, Sgf_operation_ODD1_middle_N47,
Sgf_operation_ODD1_middle_N46, Sgf_operation_ODD1_middle_N45,
Sgf_operation_ODD1_middle_N44, Sgf_operation_ODD1_middle_N43,
Sgf_operation_ODD1_middle_N42, Sgf_operation_ODD1_middle_N41,
Sgf_operation_ODD1_middle_N40, Sgf_operation_ODD1_middle_N39,
Sgf_operation_ODD1_middle_N38, Sgf_operation_ODD1_middle_N37,
Sgf_operation_ODD1_middle_N36, Sgf_operation_ODD1_middle_N35,
Sgf_operation_ODD1_middle_N34, Sgf_operation_ODD1_middle_N33,
Sgf_operation_ODD1_middle_N32, Sgf_operation_ODD1_middle_N31,
Sgf_operation_ODD1_middle_N30, Sgf_operation_ODD1_middle_N29,
Sgf_operation_ODD1_middle_N28, Sgf_operation_ODD1_middle_N27,
Sgf_operation_ODD1_middle_N26, Sgf_operation_ODD1_middle_N25,
Sgf_operation_ODD1_middle_N24, Sgf_operation_ODD1_middle_N23,
Sgf_operation_ODD1_middle_N22, Sgf_operation_ODD1_middle_N21,
Sgf_operation_ODD1_middle_N20, Sgf_operation_ODD1_middle_N19,
Sgf_operation_ODD1_middle_N18, Sgf_operation_ODD1_middle_N17,
Sgf_operation_ODD1_middle_N16, Sgf_operation_ODD1_middle_N15,
Sgf_operation_ODD1_middle_N14, Sgf_operation_ODD1_middle_N13,
Sgf_operation_ODD1_middle_N12, Sgf_operation_ODD1_middle_N11,
Sgf_operation_ODD1_middle_N10, Sgf_operation_ODD1_middle_N9,
Sgf_operation_ODD1_middle_N8, Sgf_operation_ODD1_middle_N7,
Sgf_operation_ODD1_middle_N6, Sgf_operation_ODD1_middle_N5,
Sgf_operation_ODD1_middle_N4, Sgf_operation_ODD1_middle_N3,
Sgf_operation_ODD1_middle_N2, Sgf_operation_ODD1_middle_N1,
Sgf_operation_ODD1_middle_N0, n287, n289, n290, n291, n292, n293,
n294, n295, n296, n297, n298, n299, n300, n301, n302, n303, n304,
n305, n306, n307, n308, n309, n310, n311, n312, n313, n314, n315,
n316, n317, n318, n319, n320, n321, n322, n323, n324, n325, n326,
n327, n328, n329, n330, n331, n332, n333, n334, n335, n336, n337,
n338, n339, n340, n341, n342, n343, n344, n345, n346, n347, n348,
n349, n350, n351, n352, n353, n354, n355, n356, n357, n358, n359,
n360, n361, n362, n363, n364, n365, n366, n367, n368, n369, n370,
n371, n372, n373, n374, n375, n376, n377, n378, n379, n380, n381,
n382, n383, n384, n385, n386, n387, n388, n389, n390, n391, n392,
n393, n394, n395, n396, n397, n398, n399, n400, n401, n402, n403,
n404, n405, n406, n407, n408, n409, n410, n411, n412, n413, n414,
n415, n416, n417, n418, n419, n420, n421, n422, n423, n424, n425,
n426, n427, n428, n429, n430, n431, n432, n433, n434, n435, n436,
n437, n438, n439, n440, n441, n442, n443, n444, n445, n446, n447,
n448, n449, n450, n451, n452, n453, n454, n455, n456, n457, n458,
n459, n460, n461, n462, n463, n464, n465, n466, n467, n468, n469,
n470, n471, n472, n473, n474, n475, n476, n477, n478, n479, n480,
n481, n482, n483, n484, n485, n486, n487, n488, n489, n490, n491,
n492, n493, n494, n495, n496, n497, n498, n499, n500, n501, n502,
n503, n504, n505, n506, n507, n508, n509, n510, n511, n512, n513,
n514, n515, n516, n517, n518, n519, n520, n521, n522, n523, n524,
n525, n526, n527, n528, n529, n530, n531, n532, n533, n534, n535,
n536, n537, n538, n539, n540, n541, n542, n543, n544, n545, n546,
n547, n548, n549, n550, n551, n552, n553, n554, n555, n556, n557,
n558, n559, n560, n561, n562, n563, n564, n565, n566, n567, n568,
n569, n570, n571, n572, n573, n574, n575, n576, n577, n578, n579,
n580, n581, n582, n583, n584, n585, n586, n587, n588, n589, n590,
n591, n592, n593, n594, n595, n596, n597, n598, n599, n600, n601,
n602, n603, n604, n605, n606, n607, n608, n609, n610, n611, n612,
n613, n614, n615, n616, n617, n618, n619, n620, n621, n622, n623,
n624, n625, n626, n627, n628, n629, n630, n631, n632, n633, n634,
n635, n636, n637, n638, n639, n640, n641, n642, n643, n644, n645,
n646, n647, n648, n649, n650, n651, n652, n653, n654, n655, n656,
n657, n658, n659, n660, n661, n662, n663, n664, n665, n666, n667,
n668, n669, n670, n671, n672, n673, n674, n675, n676, n677, n678,
n679, n680, n681, n682, n683, n684, n685, n686, n687, n688, n689,
n690, n691, n692, n693, n694, n695, n696, n697, n698, n699, n700,
n701, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711,
n712, n713, n714, n715, DP_OP_168J42_122_1342_n617,
DP_OP_168J42_122_1342_n587, DP_OP_36J42_124_1029_n28,
DP_OP_36J42_124_1029_n27, DP_OP_36J42_124_1029_n26,
DP_OP_36J42_124_1029_n25, DP_OP_36J42_124_1029_n24,
DP_OP_36J42_124_1029_n23, DP_OP_36J42_124_1029_n22,
DP_OP_36J42_124_1029_n21, DP_OP_36J42_124_1029_n20,
DP_OP_36J42_124_1029_n19, DP_OP_36J42_124_1029_n18,
DP_OP_36J42_124_1029_n12, DP_OP_36J42_124_1029_n11,
DP_OP_36J42_124_1029_n10, DP_OP_36J42_124_1029_n9,
DP_OP_36J42_124_1029_n8, DP_OP_36J42_124_1029_n7,
DP_OP_36J42_124_1029_n6, DP_OP_36J42_124_1029_n5,
DP_OP_36J42_124_1029_n4, DP_OP_36J42_124_1029_n3,
DP_OP_36J42_124_1029_n2, DP_OP_36J42_124_1029_n1, mult_x_24_n1657,
mult_x_24_n1656, mult_x_24_n1655, mult_x_24_n1654, mult_x_24_n1653,
mult_x_24_n1652, mult_x_24_n1651, mult_x_24_n1650, mult_x_24_n1649,
mult_x_24_n1648, mult_x_24_n1647, mult_x_24_n1646, mult_x_24_n1645,
mult_x_24_n1644, mult_x_24_n1643, mult_x_24_n1642, mult_x_24_n1641,
mult_x_24_n1640, mult_x_24_n1639, mult_x_24_n1638, mult_x_24_n1630,
mult_x_24_n1629, mult_x_24_n1628, mult_x_24_n1627, mult_x_24_n1626,
mult_x_24_n1625, mult_x_24_n1624, mult_x_24_n1623, mult_x_24_n1622,
mult_x_24_n1621, mult_x_24_n1620, mult_x_24_n1619, mult_x_24_n1618,
mult_x_24_n1617, mult_x_24_n1616, mult_x_24_n1615, mult_x_24_n1614,
mult_x_24_n1613, mult_x_24_n1612, mult_x_24_n1611, mult_x_24_n1610,
mult_x_24_n1609, mult_x_24_n1608, mult_x_24_n1603, mult_x_24_n1602,
mult_x_24_n1601, mult_x_24_n1600, mult_x_24_n1599, mult_x_24_n1597,
mult_x_24_n1596, mult_x_24_n1595, mult_x_24_n1594, mult_x_24_n1593,
mult_x_24_n1592, mult_x_24_n1591, mult_x_24_n1590, mult_x_24_n1589,
mult_x_24_n1588, mult_x_24_n1587, mult_x_24_n1586, mult_x_24_n1585,
mult_x_24_n1584, mult_x_24_n1583, mult_x_24_n1582, mult_x_24_n1581,
mult_x_24_n1580, mult_x_24_n1579, mult_x_24_n1578, mult_x_24_n1570,
mult_x_24_n1569, mult_x_24_n1568, mult_x_24_n1567, mult_x_24_n1566,
mult_x_24_n1565, mult_x_24_n1564, mult_x_24_n1563, mult_x_24_n1562,
mult_x_24_n1561, mult_x_24_n1560, mult_x_24_n1559, mult_x_24_n1558,
mult_x_24_n1557, mult_x_24_n1556, mult_x_24_n1555, mult_x_24_n1554,
mult_x_24_n1553, mult_x_24_n1552, mult_x_24_n1551, mult_x_24_n1550,
mult_x_24_n1549, mult_x_24_n1548, mult_x_24_n1543, mult_x_24_n1542,
mult_x_24_n1541, mult_x_24_n1540, mult_x_24_n1539, mult_x_24_n1537,
mult_x_24_n1536, mult_x_24_n1535, mult_x_24_n1534, mult_x_24_n1533,
mult_x_24_n1532, mult_x_24_n1531, mult_x_24_n1530, mult_x_24_n1529,
mult_x_24_n1528, mult_x_24_n1527, mult_x_24_n1526, mult_x_24_n1525,
mult_x_24_n1524, mult_x_24_n1523, mult_x_24_n1522, mult_x_24_n1521,
mult_x_24_n1520, mult_x_24_n1519, mult_x_24_n1510, mult_x_24_n1509,
mult_x_24_n1508, mult_x_24_n1507, mult_x_24_n1506, mult_x_24_n1505,
mult_x_24_n1504, mult_x_24_n1503, mult_x_24_n1502, mult_x_24_n1501,
mult_x_24_n1500, mult_x_24_n1499, mult_x_24_n1498, mult_x_24_n1497,
mult_x_24_n1496, mult_x_24_n1495, mult_x_24_n1494, mult_x_24_n1493,
mult_x_24_n1492, mult_x_24_n1491, mult_x_24_n1490, mult_x_24_n1489,
mult_x_24_n1488, mult_x_24_n1483, mult_x_24_n1482, mult_x_24_n1481,
mult_x_24_n1480, mult_x_24_n1479, mult_x_24_n1477, mult_x_24_n1476,
mult_x_24_n1475, mult_x_24_n1474, mult_x_24_n1473, mult_x_24_n1472,
mult_x_24_n1471, mult_x_24_n1470, mult_x_24_n1469, mult_x_24_n1468,
mult_x_24_n1467, mult_x_24_n1466, mult_x_24_n1465, mult_x_24_n1464,
mult_x_24_n1463, mult_x_24_n1462, mult_x_24_n1461, mult_x_24_n1460,
mult_x_24_n1450, mult_x_24_n1449, mult_x_24_n1448, mult_x_24_n1447,
mult_x_24_n1446, mult_x_24_n1445, mult_x_24_n1444, mult_x_24_n1443,
mult_x_24_n1442, mult_x_24_n1441, mult_x_24_n1440, mult_x_24_n1439,
mult_x_24_n1438, mult_x_24_n1437, mult_x_24_n1436, mult_x_24_n1435,
mult_x_24_n1434, mult_x_24_n1433, mult_x_24_n1432, mult_x_24_n1431,
mult_x_24_n1430, mult_x_24_n1429, mult_x_24_n1428, mult_x_24_n1423,
mult_x_24_n1422, mult_x_24_n1421, mult_x_24_n1420, mult_x_24_n1419,
mult_x_24_n1418, mult_x_24_n1415, mult_x_24_n1414, mult_x_24_n1413,
mult_x_24_n1412, mult_x_24_n1410, mult_x_24_n1409, mult_x_24_n1408,
mult_x_24_n1407, mult_x_24_n1406, mult_x_24_n1405, mult_x_24_n1404,
mult_x_24_n1403, mult_x_24_n1402, mult_x_24_n1401, mult_x_24_n1400,
mult_x_24_n1109, mult_x_24_n1108, mult_x_24_n1107, mult_x_24_n1106,
mult_x_24_n1105, mult_x_24_n1104, mult_x_24_n1100, mult_x_24_n1099,
mult_x_24_n1098, mult_x_24_n1094, mult_x_24_n1093, mult_x_24_n1092,
mult_x_24_n1088, mult_x_24_n1087, mult_x_24_n1086, mult_x_24_n1067,
mult_x_24_n1064, mult_x_24_n1062, mult_x_24_n1061, mult_x_24_n1060,
mult_x_24_n1059, mult_x_24_n1057, mult_x_24_n1056, mult_x_24_n1055,
mult_x_24_n1054, mult_x_24_n1052, mult_x_24_n1051, mult_x_24_n1050,
mult_x_24_n1047, mult_x_24_n1045, mult_x_24_n1044, mult_x_24_n1043,
mult_x_24_n1040, mult_x_24_n1039, mult_x_24_n1038, mult_x_24_n1037,
mult_x_24_n1036, mult_x_24_n1034, mult_x_24_n1033, mult_x_24_n1032,
mult_x_24_n1031, mult_x_24_n1030, mult_x_24_n1029, mult_x_24_n1028,
mult_x_24_n1026, mult_x_24_n1025, mult_x_24_n1024, mult_x_24_n1023,
mult_x_24_n1022, mult_x_24_n1021, mult_x_24_n1020, mult_x_24_n1018,
mult_x_24_n1017, mult_x_24_n1016, mult_x_24_n1015, mult_x_24_n1014,
mult_x_24_n1013, mult_x_24_n1012, mult_x_24_n1010, mult_x_24_n1009,
mult_x_24_n1008, mult_x_24_n1007, mult_x_24_n1006, mult_x_24_n1005,
mult_x_24_n1002, mult_x_24_n1000, mult_x_24_n999, mult_x_24_n998,
mult_x_24_n997, mult_x_24_n996, mult_x_24_n995, mult_x_24_n992,
mult_x_24_n991, mult_x_24_n990, mult_x_24_n989, mult_x_24_n988,
mult_x_24_n987, mult_x_24_n986, mult_x_24_n985, mult_x_24_n983,
mult_x_24_n982, mult_x_24_n981, mult_x_24_n980, mult_x_24_n979,
mult_x_24_n978, mult_x_24_n977, mult_x_24_n976, mult_x_24_n975,
mult_x_24_n974, mult_x_24_n972, mult_x_24_n971, mult_x_24_n970,
mult_x_24_n969, mult_x_24_n968, mult_x_24_n967, mult_x_24_n966,
mult_x_24_n965, mult_x_24_n964, mult_x_24_n963, mult_x_24_n961,
mult_x_24_n960, mult_x_24_n959, mult_x_24_n958, mult_x_24_n957,
mult_x_24_n956, mult_x_24_n955, mult_x_24_n954, mult_x_24_n953,
mult_x_24_n952, mult_x_24_n950, mult_x_24_n949, mult_x_24_n948,
mult_x_24_n947, mult_x_24_n946, mult_x_24_n945, mult_x_24_n944,
mult_x_24_n943, mult_x_24_n942, mult_x_24_n939, mult_x_24_n937,
mult_x_24_n936, mult_x_24_n935, mult_x_24_n934, mult_x_24_n933,
mult_x_24_n932, mult_x_24_n931, mult_x_24_n930, mult_x_24_n929,
mult_x_24_n926, mult_x_24_n925, mult_x_24_n924, mult_x_24_n923,
mult_x_24_n922, mult_x_24_n921, mult_x_24_n920, mult_x_24_n919,
mult_x_24_n918, mult_x_24_n917, mult_x_24_n916, mult_x_24_n914,
mult_x_24_n913, mult_x_24_n912, mult_x_24_n911, mult_x_24_n910,
mult_x_24_n909, mult_x_24_n908, mult_x_24_n907, mult_x_24_n906,
mult_x_24_n905, mult_x_24_n904, mult_x_24_n903, mult_x_24_n902,
mult_x_24_n901, mult_x_24_n900, mult_x_24_n899, mult_x_24_n898,
mult_x_24_n897, mult_x_24_n896, mult_x_24_n895, mult_x_24_n894,
mult_x_24_n893, mult_x_24_n892, mult_x_24_n891, mult_x_24_n890,
mult_x_24_n889, mult_x_24_n888, mult_x_24_n887, mult_x_24_n886,
mult_x_24_n885, mult_x_24_n884, mult_x_24_n883, mult_x_24_n882,
mult_x_24_n881, mult_x_24_n880, mult_x_24_n879, mult_x_24_n878,
mult_x_24_n877, mult_x_24_n876, mult_x_24_n875, mult_x_24_n874,
mult_x_24_n873, mult_x_24_n872, mult_x_24_n871, mult_x_24_n870,
mult_x_24_n869, mult_x_24_n868, mult_x_24_n867, mult_x_24_n866,
mult_x_24_n865, mult_x_24_n864, mult_x_24_n863, mult_x_24_n862,
mult_x_24_n861, mult_x_24_n860, mult_x_24_n859, mult_x_24_n858,
mult_x_24_n857, mult_x_24_n856, mult_x_24_n855, mult_x_24_n854,
mult_x_24_n853, mult_x_24_n852, mult_x_24_n851, mult_x_24_n850,
mult_x_24_n849, mult_x_24_n848, mult_x_24_n847, mult_x_24_n846,
mult_x_24_n845, mult_x_24_n844, mult_x_24_n843, mult_x_24_n842,
mult_x_24_n841, mult_x_24_n840, mult_x_24_n839, mult_x_24_n838,
mult_x_24_n837, mult_x_24_n836, mult_x_24_n835, mult_x_24_n834,
mult_x_24_n833, mult_x_24_n832, mult_x_24_n831, mult_x_24_n829,
mult_x_24_n828, mult_x_24_n827, mult_x_24_n826, mult_x_24_n825,
mult_x_24_n824, mult_x_24_n823, mult_x_24_n822, mult_x_24_n821,
mult_x_24_n820, mult_x_24_n819, mult_x_24_n817, mult_x_24_n816,
mult_x_24_n815, mult_x_24_n814, mult_x_24_n813, mult_x_24_n812,
mult_x_24_n811, mult_x_24_n810, mult_x_24_n809, mult_x_24_n808,
mult_x_24_n807, mult_x_24_n806, mult_x_24_n805, mult_x_24_n804,
mult_x_24_n803, mult_x_24_n802, mult_x_24_n801, mult_x_24_n800,
mult_x_24_n799, mult_x_24_n798, mult_x_24_n797, mult_x_24_n796,
mult_x_24_n795, mult_x_24_n794, mult_x_24_n793, mult_x_24_n792,
mult_x_24_n791, mult_x_24_n790, mult_x_24_n789, mult_x_24_n788,
mult_x_24_n787, mult_x_24_n786, mult_x_24_n784, mult_x_24_n783,
mult_x_24_n782, mult_x_24_n781, mult_x_24_n780, mult_x_24_n779,
mult_x_24_n778, mult_x_24_n777, mult_x_24_n776, mult_x_24_n775,
mult_x_24_n774, mult_x_24_n773, mult_x_24_n772, mult_x_24_n771,
mult_x_24_n770, mult_x_24_n769, mult_x_24_n768, mult_x_24_n767,
mult_x_24_n765, mult_x_24_n764, mult_x_24_n763, mult_x_24_n762,
mult_x_24_n761, mult_x_24_n760, mult_x_24_n759, mult_x_24_n758,
mult_x_24_n756, mult_x_24_n755, mult_x_24_n754, mult_x_24_n753,
mult_x_24_n752, mult_x_24_n751, mult_x_24_n750, mult_x_24_n749,
mult_x_24_n748, mult_x_24_n747, mult_x_24_n746, mult_x_24_n745,
mult_x_24_n744, mult_x_24_n743, mult_x_24_n742, mult_x_24_n741,
mult_x_24_n740, mult_x_24_n739, mult_x_24_n738, mult_x_24_n737,
mult_x_24_n736, mult_x_24_n735, mult_x_24_n734, mult_x_24_n732,
mult_x_24_n731, mult_x_24_n730, mult_x_24_n729, mult_x_24_n728,
mult_x_24_n727, mult_x_24_n726, mult_x_24_n725, mult_x_24_n724,
mult_x_24_n723, mult_x_24_n722, mult_x_24_n721, mult_x_24_n719,
mult_x_24_n718, mult_x_24_n717, mult_x_24_n716, mult_x_24_n715,
mult_x_24_n713, mult_x_24_n712, mult_x_24_n711, mult_x_24_n710,
mult_x_24_n709, mult_x_24_n708, mult_x_24_n707, mult_x_24_n706,
mult_x_24_n705, mult_x_24_n704, mult_x_24_n703, mult_x_24_n702,
mult_x_24_n701, mult_x_24_n700, mult_x_24_n698, mult_x_24_n697,
mult_x_24_n696, mult_x_24_n695, mult_x_24_n694, mult_x_24_n693,
mult_x_23_n1481, mult_x_23_n1480, mult_x_23_n1479, mult_x_23_n1478,
mult_x_23_n1477, mult_x_23_n1476, mult_x_23_n1475, mult_x_23_n1474,
mult_x_23_n1473, mult_x_23_n1472, mult_x_23_n1471, mult_x_23_n1470,
mult_x_23_n1469, mult_x_23_n1468, mult_x_23_n1467, mult_x_23_n1466,
mult_x_23_n1465, mult_x_23_n1464, mult_x_23_n1463, mult_x_23_n1455,
mult_x_23_n1454, mult_x_23_n1453, mult_x_23_n1452, mult_x_23_n1451,
mult_x_23_n1450, mult_x_23_n1449, mult_x_23_n1448, mult_x_23_n1447,
mult_x_23_n1446, mult_x_23_n1445, mult_x_23_n1444, mult_x_23_n1443,
mult_x_23_n1442, mult_x_23_n1441, mult_x_23_n1440, mult_x_23_n1439,
mult_x_23_n1438, mult_x_23_n1437, mult_x_23_n1436, mult_x_23_n1435,
mult_x_23_n1434, mult_x_23_n1429, mult_x_23_n1428, mult_x_23_n1427,
mult_x_23_n1426, mult_x_23_n1425, mult_x_23_n1423, mult_x_23_n1422,
mult_x_23_n1421, mult_x_23_n1420, mult_x_23_n1419, mult_x_23_n1418,
mult_x_23_n1417, mult_x_23_n1416, mult_x_23_n1415, mult_x_23_n1414,
mult_x_23_n1413, mult_x_23_n1412, mult_x_23_n1411, mult_x_23_n1410,
mult_x_23_n1409, mult_x_23_n1408, mult_x_23_n1407, mult_x_23_n1406,
mult_x_23_n1405, mult_x_23_n1397, mult_x_23_n1396, mult_x_23_n1395,
mult_x_23_n1394, mult_x_23_n1393, mult_x_23_n1392, mult_x_23_n1391,
mult_x_23_n1390, mult_x_23_n1389, mult_x_23_n1388, mult_x_23_n1387,
mult_x_23_n1386, mult_x_23_n1385, mult_x_23_n1384, mult_x_23_n1383,
mult_x_23_n1382, mult_x_23_n1381, mult_x_23_n1380, mult_x_23_n1379,
mult_x_23_n1378, mult_x_23_n1377, mult_x_23_n1371, mult_x_23_n1370,
mult_x_23_n1369, mult_x_23_n1368, mult_x_23_n1367, mult_x_23_n1365,
mult_x_23_n1364, mult_x_23_n1363, mult_x_23_n1362, mult_x_23_n1361,
mult_x_23_n1360, mult_x_23_n1359, mult_x_23_n1358, mult_x_23_n1357,
mult_x_23_n1356, mult_x_23_n1355, mult_x_23_n1354, mult_x_23_n1353,
mult_x_23_n1352, mult_x_23_n1351, mult_x_23_n1350, mult_x_23_n1349,
mult_x_23_n1348, mult_x_23_n1347, mult_x_23_n1339, mult_x_23_n1338,
mult_x_23_n1337, mult_x_23_n1336, mult_x_23_n1335, mult_x_23_n1334,
mult_x_23_n1333, mult_x_23_n1332, mult_x_23_n1331, mult_x_23_n1330,
mult_x_23_n1329, mult_x_23_n1328, mult_x_23_n1327, mult_x_23_n1326,
mult_x_23_n1325, mult_x_23_n1324, mult_x_23_n1323, mult_x_23_n1322,
mult_x_23_n1321, mult_x_23_n1320, mult_x_23_n1313, mult_x_23_n1312,
mult_x_23_n1311, mult_x_23_n1310, mult_x_23_n1309, mult_x_23_n1305,
mult_x_23_n1304, mult_x_23_n1303, mult_x_23_n1302, mult_x_23_n1301,
mult_x_23_n1300, mult_x_23_n1299, mult_x_23_n1298, mult_x_23_n1297,
mult_x_23_n1296, mult_x_23_n1295, mult_x_23_n1294, mult_x_23_n1293,
mult_x_23_n1292, mult_x_23_n1291, mult_x_23_n1290, mult_x_23_n1289,
mult_x_23_n1280, mult_x_23_n1277, mult_x_23_n1276, mult_x_23_n1275,
mult_x_23_n1274, mult_x_23_n1272, mult_x_23_n1270, mult_x_23_n1269,
mult_x_23_n1268, mult_x_23_n1267, mult_x_23_n1266, mult_x_23_n1264,
mult_x_23_n1263, mult_x_23_n1262, mult_x_23_n1251, mult_x_23_n1250,
mult_x_23_n1248, mult_x_23_n1247, mult_x_23_n1246, mult_x_23_n1244,
mult_x_23_n1243, mult_x_23_n1242, mult_x_23_n958, mult_x_23_n955,
mult_x_23_n953, mult_x_23_n952, mult_x_23_n951, mult_x_23_n950,
mult_x_23_n948, mult_x_23_n947, mult_x_23_n946, mult_x_23_n945,
mult_x_23_n943, mult_x_23_n942, mult_x_23_n941, mult_x_23_n938,
mult_x_23_n936, mult_x_23_n935, mult_x_23_n934, mult_x_23_n931,
mult_x_23_n930, mult_x_23_n929, mult_x_23_n928, mult_x_23_n927,
mult_x_23_n925, mult_x_23_n924, mult_x_23_n923, mult_x_23_n922,
mult_x_23_n921, mult_x_23_n920, mult_x_23_n919, mult_x_23_n917,
mult_x_23_n916, mult_x_23_n915, mult_x_23_n914, mult_x_23_n913,
mult_x_23_n912, mult_x_23_n911, mult_x_23_n909, mult_x_23_n908,
mult_x_23_n907, mult_x_23_n906, mult_x_23_n905, mult_x_23_n904,
mult_x_23_n903, mult_x_23_n901, mult_x_23_n900, mult_x_23_n899,
mult_x_23_n898, mult_x_23_n897, mult_x_23_n896, mult_x_23_n893,
mult_x_23_n891, mult_x_23_n890, mult_x_23_n889, mult_x_23_n888,
mult_x_23_n887, mult_x_23_n886, mult_x_23_n883, mult_x_23_n882,
mult_x_23_n881, mult_x_23_n880, mult_x_23_n879, mult_x_23_n878,
mult_x_23_n877, mult_x_23_n876, mult_x_23_n874, mult_x_23_n873,
mult_x_23_n872, mult_x_23_n871, mult_x_23_n870, mult_x_23_n869,
mult_x_23_n868, mult_x_23_n867, mult_x_23_n866, mult_x_23_n865,
mult_x_23_n863, mult_x_23_n862, mult_x_23_n861, mult_x_23_n860,
mult_x_23_n859, mult_x_23_n858, mult_x_23_n857, mult_x_23_n856,
mult_x_23_n855, mult_x_23_n854, mult_x_23_n852, mult_x_23_n851,
mult_x_23_n850, mult_x_23_n849, mult_x_23_n848, mult_x_23_n847,
mult_x_23_n846, mult_x_23_n845, mult_x_23_n844, mult_x_23_n843,
mult_x_23_n841, mult_x_23_n840, mult_x_23_n839, mult_x_23_n838,
mult_x_23_n837, mult_x_23_n836, mult_x_23_n835, mult_x_23_n834,
mult_x_23_n833, mult_x_23_n832, mult_x_23_n830, mult_x_23_n829,
mult_x_23_n828, mult_x_23_n827, mult_x_23_n826, mult_x_23_n825,
mult_x_23_n824, mult_x_23_n823, mult_x_23_n822, mult_x_23_n821,
mult_x_23_n820, mult_x_23_n819, mult_x_23_n818, mult_x_23_n817,
mult_x_23_n816, mult_x_23_n815, mult_x_23_n814, mult_x_23_n813,
mult_x_23_n812, mult_x_23_n811, mult_x_23_n810, mult_x_23_n809,
mult_x_23_n808, mult_x_23_n807, mult_x_23_n806, mult_x_23_n805,
mult_x_23_n804, mult_x_23_n803, mult_x_23_n802, mult_x_23_n801,
mult_x_23_n800, mult_x_23_n799, mult_x_23_n798, mult_x_23_n797,
mult_x_23_n796, mult_x_23_n795, mult_x_23_n794, mult_x_23_n793,
mult_x_23_n792, mult_x_23_n791, mult_x_23_n790, mult_x_23_n789,
mult_x_23_n788, mult_x_23_n787, mult_x_23_n786, mult_x_23_n785,
mult_x_23_n784, mult_x_23_n783, mult_x_23_n782, mult_x_23_n781,
mult_x_23_n780, mult_x_23_n779, mult_x_23_n778, mult_x_23_n777,
mult_x_23_n776, mult_x_23_n775, mult_x_23_n774, mult_x_23_n773,
mult_x_23_n772, mult_x_23_n771, mult_x_23_n770, mult_x_23_n769,
mult_x_23_n768, mult_x_23_n767, mult_x_23_n766, mult_x_23_n765,
mult_x_23_n764, mult_x_23_n763, mult_x_23_n762, mult_x_23_n761,
mult_x_23_n760, mult_x_23_n759, mult_x_23_n758, mult_x_23_n757,
mult_x_23_n756, mult_x_23_n755, mult_x_23_n754, mult_x_23_n753,
mult_x_23_n752, mult_x_23_n751, mult_x_23_n750, mult_x_23_n749,
mult_x_23_n748, mult_x_23_n747, mult_x_23_n746, mult_x_23_n745,
mult_x_23_n744, mult_x_23_n743, mult_x_23_n742, mult_x_23_n741,
mult_x_23_n740, mult_x_23_n739, mult_x_23_n738, mult_x_23_n737,
mult_x_23_n736, mult_x_23_n735, mult_x_23_n733, mult_x_23_n732,
mult_x_23_n731, mult_x_23_n730, mult_x_23_n729, mult_x_23_n728,
mult_x_23_n727, mult_x_23_n726, mult_x_23_n725, mult_x_23_n724,
mult_x_23_n723, mult_x_23_n722, mult_x_23_n721, mult_x_23_n720,
mult_x_23_n719, mult_x_23_n718, mult_x_23_n717, mult_x_23_n716,
mult_x_23_n714, mult_x_23_n713, mult_x_23_n712, mult_x_23_n711,
mult_x_23_n710, mult_x_23_n709, mult_x_23_n708, mult_x_23_n707,
mult_x_23_n706, mult_x_23_n703, mult_x_23_n702, mult_x_23_n701,
mult_x_23_n700, mult_x_23_n699, mult_x_23_n698, mult_x_23_n697,
mult_x_23_n696, mult_x_23_n695, mult_x_23_n694, mult_x_23_n693,
mult_x_23_n692, mult_x_23_n691, mult_x_23_n690, mult_x_23_n689,
mult_x_23_n688, mult_x_23_n687, mult_x_23_n686, mult_x_23_n685,
mult_x_23_n684, mult_x_23_n683, mult_x_23_n682, mult_x_23_n681,
mult_x_23_n679, mult_x_23_n678, mult_x_23_n677, mult_x_23_n676,
mult_x_23_n675, mult_x_23_n674, mult_x_23_n673, mult_x_23_n672,
mult_x_23_n671, mult_x_23_n670, mult_x_23_n669, mult_x_23_n668,
mult_x_23_n666, mult_x_23_n665, mult_x_23_n664, mult_x_23_n663,
mult_x_23_n662, mult_x_23_n661, mult_x_23_n658, mult_x_23_n657,
mult_x_23_n656, mult_x_23_n655, mult_x_23_n654, mult_x_23_n653,
mult_x_23_n652, mult_x_23_n651, mult_x_23_n650, mult_x_23_n649,
mult_x_23_n648, mult_x_23_n647, mult_x_23_n646, mult_x_23_n645,
mult_x_23_n643, mult_x_23_n642, mult_x_23_n641, mult_x_23_n640,
mult_x_23_n639, mult_x_23_n638, mult_x_23_n637, n728, n729, n730,
n731, n732, n733, n734, n735, n736, n737, n738, n739, n740, n741,
n742, n743, n744, n745, n746, n747, n748, n749, n750, n751, n752,
n753, n754, n755, n756, n757, n758, n759, n760, n761, n762, n763,
n764, n765, n766, n767, n768, n769, n770, n771, n772, n773, n774,
n775, n776, n777, n778, n779, n780, n781, n782, n783, n784, n785,
n786, n787, n788, n789, n790, n791, n792, n793, n794, n795, n796,
n797, n798, n799, n800, n801, n802, n803, n804, n805, n806, n807,
n808, n809, n810, n811, n812, n813, n814, n815, n816, n817, n818,
n819, n820, n821, n822, n823, n824, n825, n826, n827, n828, n829,
n830, n831, n832, n833, n834, n835, n836, n837, n838, n839, n840,
n841, n842, n843, n844, n845, n846, n847, n848, n849, n850, n851,
n852, n853, n854, n855, n856, n857, n858, n859, n860, n861, n862,
n863, n864, n865, n866, n867, n868, n869, n870, n871, n872, n873,
n874, n875, n876, n877, n878, n879, n880, n881, n882, n883, n884,
n885, n886, n887, n888, n889, n890, n891, n892, n893, n894, n895,
n896, n897, n899, n900, n901, n902, n903, n904, n905, n906, n907,
n908, n909, n910, n911, n912, n913, n914, n915, n916, n917, n918,
n919, n920, n921, n922, n923, n924, n925, n926, n927, n928, n929,
n930, n931, n932, n933, n934, n935, n936, n937, n938, n939, n940,
n941, n942, n943, n944, n945, n946, n947, n948, n949, n950, n951,
n952, n953, n954, n955, n956, n957, n958, n959, n960, n961, n962,
n963, n964, n965, n966, n967, n968, n969, n970, n971, n972, n973,
n974, n975, n976, n977, n978, n979, n980, n981, n982, n983, n984,
n985, n986, n987, n988, n989, n990, n991, n992, n993, n994, n995,
n996, n997, n998, n999, n1000, n1001, n1002, n1003, n1004, n1005,
n1006, n1007, n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015,
n1016, n1017, n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025,
n1026, n1027, n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035,
n1036, n1037, n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045,
n1046, n1047, n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055,
n1056, n1057, n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065,
n1066, n1067, n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075,
n1076, n1077, n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085,
n1086, n1087, n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095,
n1096, n1097, n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105,
n1106, n1107, n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115,
n1116, n1117, n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125,
n1126, n1127, n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135,
n1136, n1137, n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145,
n1146, n1147, n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155,
n1156, n1157, n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165,
n1166, n1167, n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175,
n1176, n1177, n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185,
n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195,
n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205,
n1206, n1207, n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215,
n1216, n1217, n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225,
n1226, n1227, n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235,
n1236, n1237, n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245,
n1246, n1247, n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255,
n1256, n1257, n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265,
n1266, n1267, n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275,
n1276, n1277, n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285,
n1286, n1287, n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295,
n1296, n1297, n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305,
n1306, n1307, n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315,
n1316, n1317, n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325,
n1326, n1327, n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335,
n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345,
n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355,
n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365,
n1366, n1367, n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375,
n1376, n1377, n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385,
n1386, n1387, n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395,
n1396, n1397, n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405,
n1406, n1407, n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415,
n1416, n1417, n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425,
n1426, n1427, n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435,
n1436, n1437, n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445,
n1446, n1447, n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455,
n1456, n1457, n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465,
n1466, n1467, n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475,
n1476, n1477, n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485,
n1486, n1487, n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495,
n1496, n1497, n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505,
n1506, n1507, n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515,
n1516, n1517, n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525,
n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535,
n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545,
n1546, n1547, n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555,
n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565,
n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575,
n1576, n1577, n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585,
n1586, n1587, n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595,
n1596, n1597, n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605,
n1606, n1607, n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615,
n1616, n1617, n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625,
n1626, n1627, n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635,
n1636, n1637, n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645,
n1646, n1647, n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655,
n1656, n1657, n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665,
n1666, n1667, n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675,
n1676, n1677, n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685,
n1686, n1687, n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695,
n1696, n1697, n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705,
n1706, n1707, n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715,
n1716, n1717, n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725,
n1726, n1727, n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735,
n1736, n1737, n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745,
n1746, n1747, n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755,
n1756, n1757, n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765,
n1766, n1767, n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775,
n1776, n1777, n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785,
n1786, n1787, n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795,
n1796, n1797, n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805,
n1806, n1807, n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815,
n1816, n1817, n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825,
n1826, n1827, n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835,
n1836, n1837, n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845,
n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855,
n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865,
n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875,
n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885,
n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895,
n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905,
n1906, n1907, n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915,
n1916, n1917, n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925,
n1926, n1927, n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935,
n1936, n1937, n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945,
n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955,
n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965,
n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975,
n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985,
n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995,
n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005,
n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015,
n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025,
n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035,
n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045,
n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055,
n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065,
n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075,
n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085,
n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095,
n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105,
n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115,
n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125,
n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135,
n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2144, n2145,
n2146, n2147, n2148, n2149, n2150, n2151, n2152, n2153, n2154, n2155,
n2156, n2157, n2158, n2159, n2160, n2161, n2162, n2163, n2164, n2165,
n2166, n2167, n2168, n2169, n2170, n2171, n2172, n2173, n2174, n2175,
n2176, n2177, n2178, n2179, n2180, n2181, n2182, n2183, n2184, n2185,
n2186, n2187, n2188, n2189, n2190, n2191, n2192, n2193, n2194, n2195,
n2196, n2197, n2198, n2199, n2200, n2201, n2202, n2203, n2204, n2205,
n2206, n2207, n2208, n2209, n2210, n2211, n2212, n2213, n2214, n2215,
n2216, n2217, n2218, n2219, n2220, n2221, n2222, n2223, n2224, n2225,
n2226, n2227, n2228, n2229, n2230, n2231, n2232, n2233, n2234, n2235,
n2236, n2237, n2238, n2239, n2240, n2241, n2242, n2243, n2244, n2245,
n2246, n2247, n2248, n2249, n2250, n2251, n2252, n2253, n2254, n2255,
n2256, n2257, n2258, n2259, n2260, n2261, n2262, n2263, n2264, n2265,
n2266, n2267, n2268, n2269, n2270, n2271, n2272, n2273, n2274, n2275,
n2276, n2277, n2278, n2279, n2280, n2281, n2282, n2283, n2284, n2285,
n2286, n2287, n2288, n2289, n2290, n2291, n2292, n2293, n2294, n2295,
n2296, n2297, n2298, n2299, n2300, n2301, n2302, n2303, n2304, n2305,
n2306, n2307, n2308, n2309, n2310, n2311, n2312, n2313, n2314, n2315,
n2316, n2317, n2318, n2319, n2320, n2321, n2322, n2323, n2324, n2325,
n2326, n2327, n2328, n2329, n2330, n2331, n2332, n2333, n2334, n2335,
n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343, n2344, n2345,
n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353, n2354, n2355,
n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363, n2364, n2365,
n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373, n2374, n2375,
n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383, n2384, n2385,
n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393, n2394, n2395,
n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403, n2404, n2405,
n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413, n2414, n2415,
n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423, n2424, n2425,
n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433, n2434, n2435,
n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443, n2444, n2445,
n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453, n2454, n2455,
n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463, n2464, n2465,
n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473, n2474, n2475,
n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483, n2484, n2485,
n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493, n2494, n2495,
n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503, n2504, n2505,
n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513, n2514, n2515,
n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523, n2524, n2525,
n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533, n2534, n2535,
n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543, n2544, n2545,
n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553, n2554, n2555,
n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563, n2564, n2565,
n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573, n2574, n2575,
n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583, n2584, n2585,
n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593, n2594, n2595,
n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603, n2604, n2605,
n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613, n2614, n2615,
n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623, n2624, n2625,
n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633, n2634, n2635,
n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643, n2644, n2645,
n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653, n2654, n2655,
n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663, n2664, n2665,
n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673, n2674, n2675,
n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683, n2684, n2685,
n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693, n2694, n2695,
n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703, n2704, n2705,
n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713, n2714, n2715,
n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723, n2724, n2725,
n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733, n2734, n2735,
n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743, n2744, n2745,
n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753, n2754, n2755,
n2756, n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764, n2765,
n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774, n2775,
n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784, n2785,
n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794, n2795,
n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804, n2805,
n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814, n2815,
n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824, n2825,
n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834, n2835,
n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844, n2845,
n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854, n2855,
n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864, n2865,
n2866, n2867, n2868, n2869, n2870, n2871, n2872, n2873, n2874, n2875,
n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883, n2884, n2885,
n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893, n2894, n2895,
n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903, n2904, n2905,
n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913, n2914, n2915,
n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923, n2924, n2925,
n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933, n2934, n2935,
n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943, n2944, n2945,
n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953, n2954, n2955,
n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963, n2964, n2965,
n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973, n2974, n2975,
n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983, n2984, n2985,
n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993, n2994, n2995,
n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003, n3004, n3005,
n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013, n3014, n3015,
n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023, n3024, n3025,
n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033, n3034, n3035,
n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043, n3044, n3045,
n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053, n3054, n3055,
n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063, n3064, n3065,
n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073, n3074, n3075,
n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083, n3084, n3085,
n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093, n3094, n3095,
n3096, n3097, n3098, n3099, n3100, n3101, n3102, n3103, n3104, n3105,
n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113, n3114, n3115,
n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123, n3124, n3125,
n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133, n3134, n3135,
n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143, n3144, n3145,
n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153, n3154, n3155,
n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163, n3164, n3165,
n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173, n3174, n3175,
n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183, n3184, n3185,
n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193, n3194, n3195,
n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203, n3204, n3205,
n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213, n3214, n3215,
n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223, n3224, n3225,
n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233, n3234, n3235,
n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243, n3244, n3245,
n3246, n3247, n3248, n3249, n3250, n3251, n3252, n3253, n3254, n3255,
n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263, n3264, n3265,
n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273, n3274, n3275,
n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283, n3284, n3285,
n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293, n3294, n3295,
n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303, n3304, n3305,
n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313, n3314, n3315,
n3316, n3317, n3318, n3319, n3320, n3321, n3322, n3323, n3324, n3325,
n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333, n3334, n3335,
n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343, n3344, n3345,
n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353, n3354, n3355,
n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363, n3364, n3365,
n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373, n3374, n3375,
n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383, n3384, n3385,
n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393, n3394, n3395,
n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403, n3404, n3405,
n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413, n3414, n3415,
n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423, n3424, n3425,
n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433, n3434, n3435,
n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443, n3444, n3445,
n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453, n3454, n3455,
n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463, n3464, n3465,
n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473, n3474, n3475,
n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483, n3484, n3485,
n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493, n3494, n3495,
n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503, n3504, n3505,
n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513, n3514, n3515,
n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523, n3524, n3525,
n3526, n3527, n3528, n3529, n3530, n3531, n3532, n3533, n3534, n3535,
n3536, n3537, n3538, n3539, n3540, n3541, n3542, n3543, n3544, n3545,
n3546, n3547, n3548, n3549, n3550, n3551, n3552, n3553, n3554, n3555,
n3556, n3557, n3558, n3559, n3560, n3561, n3562, n3563, n3564, n3565,
n3566, n3567, n3568, n3569, n3570, n3571, n3572, n3573, n3574, n3575,
n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583, n3584, n3585,
n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593, n3594, n3595,
n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603, n3604, n3605,
n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613, n3614, n3615,
n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623, n3624, n3625,
n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633, n3634, n3635,
n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643, n3644, n3645,
n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653, n3654, n3655,
n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663, n3664, n3665,
n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673, n3674, n3675,
n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683, n3684, n3685,
n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693, n3694, n3695,
n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3703, n3704, n3705,
n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713, n3714, n3715,
n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723, n3724, n3725,
n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733, n3734, n3735,
n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743, n3744, n3745,
n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753, n3754, n3755,
n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763, n3764, n3765,
n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773, n3774, n3775,
n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783, n3784, n3785,
n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793, n3794, n3795,
n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803, n3804, n3805,
n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813, n3814, n3815,
n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823, n3824, n3825,
n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833, n3834, n3835,
n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843, n3844, n3845,
n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853, n3854, n3855,
n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863, n3864, n3865,
n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873, n3874, n3875,
n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883, n3884, n3885,
n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893, n3894, n3895,
n3896, n3897, n3898, n3899, n3900, n3901, n3902, n3903, n3904, n3905,
n3906, n3907, n3908, n3909, n3910, n3911, n3912, n3913, n3914, n3915,
n3916, n3917, n3918, n3919, n3920, n3921, n3922, n3923, n3924, n3925,
n3926, n3927, n3928, n3929, n3930, n3931, n3932, n3933, n3934, n3935,
n3936, n3937, n3938, n3939, n3940, n3941, n3942, n3943, n3944, n3945,
n3946, n3947, n3948, n3949, n3950, n3951, n3952, n3953, n3954, n3955,
n3956, n3957, n3958, n3959, n3960, n3961, n3962, n3963, n3964, n3965,
n3966, n3967, n3968, n3969, n3970, n3971, n3972, n3973, n3974, n3975,
n3976, n3977, n3978, n3979, n3980, n3981, n3982, n3983, n3984, n3985,
n3986, n3987, n3988, n3989, n3990, n3991, n3992, n3993, n3994, n3995,
n3996, n3997, n3998, n3999, n4000, n4001, n4002, n4003, n4004, n4005,
n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013, n4014, n4015,
n4016, n4017, n4018, n4019, n4020, n4021, n4022, n4023, n4024, n4025,
n4026, n4027, n4028, n4029, n4030, n4031, n4032, n4033, n4034, n4035,
n4036, n4037, n4038, n4039, n4040, n4041, n4042, n4043, n4044, n4045,
n4046, n4047, n4048, n4049, n4050, n4051, n4052, n4053, n4054, n4055,
n4056, n4057, n4058, n4059, n4060, n4061, n4062, n4063, n4064, n4065,
n4066, n4067, n4068, n4069, n4070, n4071, n4072, n4073, n4074, n4075,
n4076, n4077, n4078, n4079, n4080, n4081, n4082, n4083, n4084, n4085,
n4086, n4087, n4088, n4089, n4090, n4091, n4092, n4093, n4094, n4095,
n4096, n4097, n4098, n4099, n4100, n4101, n4102, n4103, n4104, n4105,
n4106, n4107, n4108, n4109, n4110, n4111, n4112, n4113, n4114, n4115,
n4116, n4117, n4118, n4119, n4120, n4121, n4122, n4123, n4124, n4125,
n4126, n4127, n4128, n4129, n4130, n4131, n4132, n4133, n4134, n4135,
n4136, n4137, n4138, n4139, n4140, n4141, n4142, n4143, n4144, n4145,
n4146, n4147, n4148, n4149, n4150, n4151, n4152, n4153, n4154, n4155,
n4156, n4157, n4158, n4159, n4160, n4161, n4162, n4163, n4164, n4165,
n4166, n4167, n4168, n4169, n4170, n4171, n4172, n4173, n4174, n4175,
n4176, n4177, n4178, n4179, n4180, n4181, n4182, n4183, n4184, n4185,
n4186, n4187, n4188, n4189, n4190, n4191, n4192, n4193, n4194, n4195,
n4196, n4197, n4198, n4199, n4200, n4201, n4202, n4203, n4204, n4205,
n4206, n4207, n4208, n4209, n4210, n4211, n4212, n4213, n4214, n4215,
n4216, n4217, n4218, n4219, n4220, n4221, n4222, n4223, n4224, n4225,
n4226, n4227, n4228, n4229, n4230, n4231, n4232, n4233, n4234, n4235,
n4236, n4237, n4238, n4239, n4240, n4241, n4242, n4243, n4244, n4245,
n4246, n4247, n4248, n4249, n4250, n4251, n4252, n4253, n4254, n4255,
n4256, n4257, n4258, n4259, n4260, n4261, n4262, n4263, n4264, n4265,
n4266, n4267, n4268, n4269, n4270, n4271, n4272, n4273, n4274, n4275,
n4276, n4277, n4278, n4279, n4280, n4281, n4282, n4283, n4284, n4285,
n4286, n4287, n4288, n4289, n4290, n4291, n4292, n4293, n4294, n4295,
n4296, n4297, n4298, n4299, n4300, n4301, n4302, n4303, n4304, n4305,
n4306, n4307, n4308, n4309, n4310, n4311, n4312, n4313, n4314, n4315,
n4316, n4317, n4318, n4319, n4320, n4321, n4322, n4323, n4324, n4325,
n4326, n4327, n4328, n4329, n4330, n4331, n4332, n4333, n4334, n4335,
n4336, n4337, n4338, n4339, n4340, n4341, n4342, n4343, n4344, n4345,
n4346, n4347, n4348, n4349, n4350, n4351, n4352, n4353, n4354, n4355,
n4356, n4357, n4358, n4359, n4360, n4361, n4362, n4363, n4364, n4365,
n4366, n4367, n4368, n4369, n4370, n4371, n4372, n4373, n4374, n4375,
n4376, n4377, n4378, n4379, n4380, n4381, n4382, n4383, n4384, n4385,
n4386, n4387, n4388, n4389, n4390, n4391, n4392, n4393, n4394, n4395,
n4396, n4397, n4398, n4399, n4400, n4401, n4402, n4403, n4404, n4405,
n4406, n4407, n4408, n4409, n4410, n4411, n4412, n4413, n4414, n4415,
n4416, n4417, n4418, n4419, n4420, n4421, n4422, n4423, n4424, n4425,
n4426, n4427, n4428, n4429, n4430, n4431, n4432, n4433, n4434, n4435,
n4436, n4437, n4438, n4439, n4440, n4441, n4442, n4443, n4444, n4445,
n4446, n4447, n4448, n4449, n4450, n4451, n4452, n4453, n4454, n4455,
n4456, n4457, n4458, n4459, n4460, n4461, n4462, n4463, n4464, n4465,
n4466, n4467, n4468, n4469, n4470, n4471, n4472, n4473, n4474, n4475,
n4476, n4477, n4478, n4479, n4480, n4481, n4482, n4483, n4484, n4485,
n4486, n4487, n4488, n4489, n4490, n4491, n4492, n4493, n4494, n4495,
n4496, n4497, n4498, n4499, n4500, n4501, n4502, n4503, n4504, n4505,
n4506, n4507, n4508, n4509, n4510, n4511, n4512, n4513, n4514, n4515,
n4516, n4517, n4518, n4519, n4520, n4521, n4522, n4523, n4524, n4525,
n4526, n4527, n4528, n4529, n4530, n4531, n4532, n4533, n4534, n4535,
n4536, n4537, n4538, n4539, n4540, n4541, n4542, n4543, n4544, n4545,
n4546, n4547, n4548, n4549, n4550, n4551, n4552, n4553, n4554, n4555,
n4556, n4557, n4558, n4559, n4560, n4561, n4562, n4563, n4564, n4565,
n4566, n4567, n4568, n4569, n4570, n4571, n4572, n4573, n4574, n4575,
n4576, n4577, n4578, n4579, n4580, n4581, n4582, n4583, n4584, n4585,
n4586, n4587, n4588, n4589, n4590, n4591, n4592, n4593, n4594, n4595,
n4596, n4597, n4598, n4599, n4600, n4601, n4602, n4603, n4604, n4605,
n4606, n4607, n4608, n4609, n4610, n4611, n4612, n4613, n4614, n4615,
n4616, n4617, n4618, n4619, n4620, n4621, n4622, n4623, n4624, n4625,
n4626, n4627, n4628, n4629, n4630, n4631, n4632, n4633, n4634, n4635,
n4636, n4637, n4638, n4639, n4640, n4641, n4642, n4643, n4644, n4645,
n4646, n4647, n4648, n4649, n4650, n4651, n4652, n4653, n4654, n4655,
n4656, n4657, n4658, n4659, n4660, n4661, n4662, n4663, n4664, n4665,
n4666, n4667, n4668, n4669, n4670, n4671, n4672, n4673, n4674, n4675,
n4676, n4677, n4678, n4679, n4680, n4681, n4682, n4683, n4684, n4685,
n4686, n4687, n4688, n4689, n4690, n4691, n4692, n4693, n4694, n4695,
n4696, n4697, n4698, n4699, n4700, n4701, n4702, n4703, n4704, n4705,
n4706, n4707, n4708, n4709, n4710, n4711, n4712, n4713, n4714, n4715,
n4716, n4717, n4718, n4719, n4720, n4721, n4722, n4723, n4724, n4725,
n4726, n4727, n4728, n4729, n4730, n4731, n4732, n4733, n4734, n4735,
n4736, n4737, n4738, n4739, n4740, n4741, n4742, n4743, n4744, n4745,
n4746, n4747, n4748, n4749, n4750, n4751, n4752, n4753, n4754, n4755,
n4756, n4757, n4758, n4759, n4760, n4761, n4762, n4763, n4764, n4765,
n4766, n4767, n4768, n4769, n4770, n4771, n4772, n4773, n4774, n4775,
n4776, n4777, n4778, n4779, n4780, n4781, n4782, n4783, n4784, n4785,
n4786, n4787, n4788, n4789, n4790, n4791, n4792, n4793, n4794, n4795,
n4796, n4797, n4798, n4799, n4800, n4801, n4802, n4803, n4804, n4805,
n4806, n4807, n4808, n4809, n4810, n4811, n4812, n4813, n4814, n4815,
n4816, n4817, n4818, n4819, n4820, n4821, n4822, n4823, n4824, n4825,
n4826, n4827, n4828, n4829, n4830, n4831, n4832, n4833, n4834, n4835,
n4836, n4837, n4838, n4839, n4840, n4841, n4842, n4843, n4844, n4845,
n4846, n4847, n4848, n4849, n4850, n4851, n4852, n4853, n4854, n4855,
n4856, n4857, n4858, n4859, n4860, n4861, n4862, n4863, n4864, n4865,
n4866, n4867, n4868, n4869, n4870, n4871, n4872, n4873, n4874, n4875,
n4876, n4877, n4878, n4879, n4880, n4881, n4882, n4883, n4884, n4885,
n4886, n4887, n4888, n4889, n4890, n4891, n4892, n4893, n4894, n4895,
n4896, n4897, n4898, n4899, n4900, n4901, n4902, n4903, n4904, n4905,
n4906, n4907, n4908, n4909, n4910, n4911, n4912, n4913, n4914, n4915,
n4916, n4917, n4918, n4919, n4920, n4921, n4922, n4923, n4924, n4925,
n4926, n4927, n4928, n4929, n4930, n4931, n4932, n4933, n4934, n4935,
n4936, n4937, n4938, n4939, n4940, n4941, n4942, n4943, n4944, n4945,
n4946, n4947, n4948, n4949, n4950, n4951, n4952, n4953, n4954, n4955,
n4956, n4957, n4958, n4959, n4960, n4961, n4962, n4963, n4964, n4965,
n4966, n4967, n4968, n4969, n4970, n4971, n4972, n4973, n4974, n4975,
n4976, n4977, n4978, n4979, n4980, n4981, n4982, n4983, n4984, n4985,
n4986, n4987, n4988, n4989, n4990, n4991, n4992, n4993, n4994, n4995,
n4996, n4997, n4998, n4999, n5000, n5001, n5002, n5003, n5004, n5005,
n5006, n5007, n5008, n5009, n5010, n5011, n5012, n5013, n5014, n5015,
n5016, n5017, n5018, n5019, n5020, n5021, n5022, n5023, n5024, n5025,
n5026, n5027, n5028, n5029, n5030, n5031, n5032, n5033, n5034, n5035,
n5036, n5037, n5038, n5039, n5040, n5041, n5042, n5043, n5044, n5045,
n5046, n5047, n5048, n5049, n5050, n5051, n5052, n5053, n5054, n5055,
n5056, n5057, n5058, n5059, n5060, n5061, n5062, n5063, n5064, n5065,
n5066, n5067, n5068, n5069, n5070, n5071, n5072, n5073, n5074, n5075,
n5076, n5077, n5078, n5079, n5080, n5081, n5082, n5083, n5084, n5085,
n5086, n5087, n5088, n5089, n5090, n5091, n5092, n5093, n5094, n5095,
n5096, n5097, n5098, n5099, n5100, n5101, n5102, n5103, n5104, n5105,
n5106, n5107, n5108, n5109, n5110, n5111, n5112, n5113, n5114, n5115,
n5116, n5117, n5118, n5119, n5120, n5121, n5122, n5123, n5124, n5125,
n5126, n5127, n5128, n5129, n5130, n5131, n5132, n5133, n5134, n5135,
n5136, n5137, n5138, n5139, n5140, n5141, n5142, n5143, n5144, n5145,
n5146, n5147, n5148, n5149, n5150, n5151, n5152, n5153, n5154, n5155,
n5156, n5157, n5158, n5159, n5160, n5161, n5162, n5163, n5164, n5165,
n5166, n5167, n5168, n5169, n5170, n5171, n5172, n5173, n5174, n5175,
n5176, n5177, n5178, n5179, n5180, n5181, n5182, n5183, n5184, n5185,
n5186, n5187, n5188, n5189, n5190, n5191, n5192, n5193, n5194, n5195,
n5196, n5197, n5198, n5199, n5200, n5201, n5202, n5203, n5204, n5205,
n5206, n5207, n5208, n5209, n5210, n5211, n5212, n5213, n5214, n5215,
n5216, n5217, n5218, n5219, n5220, n5221, n5222, n5223, n5224, n5225,
n5226, n5227, n5228, n5229, n5230, n5231, n5232, n5233, n5234, n5235,
n5236, n5237, n5238, n5239, n5240, n5241, n5242, n5243, n5244, n5245,
n5246, n5247, n5248, n5249, n5250, n5251, n5252, n5253, n5254, n5255,
n5256, n5257, n5258, n5259, n5260, n5261, n5262, n5263, n5264, n5265,
n5266, n5267, n5268, n5269, n5270, n5271, n5272, n5273, n5274, n5275,
n5276, n5277, n5278, n5279, n5280, n5281, n5282, n5283, n5284, n5285,
n5286, n5287, n5288, n5289, n5290, n5291, n5292, n5293, n5294, n5295,
n5296, n5297, n5298, n5299, n5300, n5301, n5302, n5303, n5304, n5305,
n5306, n5307, n5308, n5309, n5310, n5311, n5312, n5313, n5314, n5315,
n5316, n5317, n5318, n5319, n5320, n5321, n5322, n5323, n5324, n5325,
n5326, n5327, n5328, n5329, n5330, n5331, n5332, n5333, n5334, n5335,
n5336, n5337, n5338, n5339, n5340, n5341, n5342, n5343, n5344, n5345,
n5346, n5347, n5348, n5349, n5350, n5351, n5352, n5353, n5354, n5355,
n5356, n5357, n5358, n5359, n5360, n5361, n5362, n5363, n5364, n5365,
n5366, n5367, n5368, n5369, n5370, n5371, n5372, n5373, n5374, n5375,
n5376, n5377, n5378, n5379, n5380, n5381, n5382, n5383, n5384, n5385,
n5386, n5387, n5388, n5389, n5390, n5391, n5392, n5393, n5394, n5395,
n5396, n5397, n5398, n5399, n5400, n5401, n5402, n5403, n5404, n5405,
n5406, n5407, n5408, n5409, n5410, n5411, n5412, n5413, n5414, n5415,
n5416, n5417, n5418, n5419, n5420, n5421, n5422, n5423, n5424, n5425,
n5426, n5427, n5428, n5429, n5430, n5431, n5432, n5433, n5434, n5435,
n5436, n5437, n5438, n5439, n5440, n5441, n5442, n5443, n5444, n5445,
n5446, n5447, n5448, n5449, n5450, n5451, n5452, n5453, n5454, n5455,
n5456, n5457, n5458, n5459, n5460, n5461, n5462, n5463, n5464, n5465,
n5466, n5467, n5468, n5469, n5470, n5471, n5472, n5473, n5474, n5475,
n5476, n5477, n5478, n5479, n5480, n5481, n5482, n5483, n5484, n5485,
n5486, n5487, n5488, n5489, n5490, n5491, n5492, n5493, n5494, n5495,
n5496, n5497, n5498, n5499, n5500, n5501, n5502, n5503, n5504, n5505,
n5506, n5507, n5508, n5509, n5510, n5511, n5512, n5513, n5514, n5515,
n5516, n5517, n5518, n5519, n5520, n5521, n5522, n5523, n5524, n5525,
n5526, n5527, n5528, n5529, n5530, n5531, n5532, n5533, n5534, n5535,
n5536, n5537, n5538, n5539, n5540, n5541, n5542, n5543, n5544, n5545,
n5546, n5547, n5548, n5549, n5550, n5551, n5552, n5553, n5554, n5555,
n5556, n5557, n5558, n5559, n5560, n5561, n5562, n5563, n5564, n5565,
n5566, n5567, n5568, n5569, n5570, n5571, n5572, n5573, n5574, n5575,
n5576, n5577, n5578, n5579, n5580, n5581, n5582, n5583, n5584, n5585,
n5586, n5587, n5588, n5589, n5590, n5591, n5592, n5593, n5594, n5595,
n5596, n5597, n5598, n5599, n5600, n5601, n5602, n5603, n5604, n5605,
n5606, n5607, n5608, n5609, n5610, n5611, n5612, n5613, n5614, n5615,
n5616, n5617, n5618, n5619, n5620, n5621, n5622, n5623, n5624, n5625,
n5626, n5627, n5628, n5629, n5630, n5631, n5632, n5633, n5634, n5635,
n5636, n5637, n5638, n5639, n5640, n5641, n5642, n5643, n5644, n5645,
n5646, n5647, n5648, n5649, n5650, n5651, n5652, n5653, n5654, n5655,
n5656, n5657, n5658, n5659, n5660, n5661, n5662, n5663, n5664, n5665,
n5666, n5667, n5668, n5669, n5670, n5671, n5672, n5673, n5674, n5675,
n5676, n5677, n5678, n5679, n5680, n5681, n5682, n5683, n5684, n5685,
n5686, n5687, n5688, n5689, n5690, n5691, n5692, n5693, n5694, n5695,
n5696, n5697, n5698, n5699, n5700, n5701, n5702, n5703, n5704, n5705,
n5706, n5707, n5708, n5709, n5710, n5711, n5712, n5713, n5714, n5715,
n5716, n5717, n5718, n5719, n5720, n5721, n5722, n5723, n5724, n5725,
n5726, n5727, n5728, n5729, n5730, n5731, n5732, n5733, n5734, n5735,
n5736, n5737, n5738, n5739, n5740, n5741, n5742, n5743, n5744, n5745,
n5746, n5747, n5748, n5749, n5750, n5751, n5752, n5753, n5754, n5755,
n5756, n5757, n5758, n5759, n5760, n5761, n5762, n5763, n5764, n5765,
n5766, n5767, n5768, n5769, n5770, n5771, n5772, n5773, n5774, n5775,
n5776, n5777, n5778, n5779, n5780, n5781, n5782, n5783, n5784, n5785,
n5786, n5787, n5788, n5789, n5790, n5791, n5792, n5793, n5794, n5795,
n5796, n5797, n5798, n5799, n5800, n5801, n5802, n5803, n5804, n5805,
n5806, n5807, n5808, n5809, n5810, n5811, n5812, n5813, n5814, n5815,
n5816, n5817, n5818, n5819, n5820, n5821, n5822, n5823, n5824, n5825,
n5826, n5827, n5828, n5829, n5830, n5831, n5832, n5833, n5834, n5835,
n5836, n5837, n5838, n5839, n5840, n5841, n5842, n5843, n5844, n5845,
n5846, n5847, n5848, n5849, n5850, n5851, n5852, n5853, n5854, n5855,
n5856, n5857, n5858, n5859, n5860, n5861, n5862, n5863, n5864, n5865,
n5866, n5867, n5868, n5869, n5870, n5871, n5872, n5873, n5874, n5875,
n5876, n5877, n5878, n5879, n5880, n5881, n5882, n5883, n5884, n5885,
n5886, n5887, n5888, n5889, n5890, n5891, n5892, n5893, n5894, n5895,
n5896, n5897, n5898, n5899, n5900, n5901, n5902, n5903, n5904, n5905,
n5906, n5907, n5908, n5909, n5910, n5911, n5912, n5913, n5914, n5915,
n5916, n5917, n5918, n5919, n5920, n5921, n5922, n5923, n5924, n5925,
n5926, n5927, n5928, n5929, n5930, n5931, n5932, n5933, n5934, n5935,
n5936, n5937, n5938, n5939, n5940, n5941, n5942, n5943, n5944, n5945,
n5946, n5947, n5948, n5949, n5950, n5951, n5952, n5953, n5954, n5955,
n5956, n5957, n5958, n5959, n5960, n5961, n5962, n5963, n5964, n5965,
n5966, n5967, n5968, n5969, n5970, n5971, n5972, n5973, n5974, n5975,
n5976, n5977, n5978, n5979, n5980, n5981, n5982, n5983, n5984, n5985,
n5986, n5987, n5988, n5989, n5990, n5991, n5992, n5993, n5994, n5995,
n5996, n5997, n5998, n5999, n6000, n6001, n6002, n6003, n6004, n6005,
n6006, n6007, n6008, n6009, n6010, n6011, n6012, n6013, n6014, n6015,
n6016, n6017, n6018, n6019, n6020, n6021, n6022, n6023, n6024, n6025,
n6026, n6027, n6028, n6029, n6030, n6031, n6032, n6033, n6034, n6035,
n6036, n6037, n6038, n6039, n6040, n6041, n6042, n6043, n6044, n6045,
n6046, n6047, n6048, n6049, n6050, n6051, n6052, n6053, n6054, n6055,
n6056, n6057, n6058, n6059, n6060, n6061, n6062, n6063, n6064, n6065,
n6066, n6067, n6068, n6069, n6070, n6071, n6072, n6073, n6074, n6075,
n6076, n6077, n6078, n6079, n6080, n6081, n6082, n6083, n6084, n6085,
n6086, n6087, n6088, n6089, n6090, n6091, n6092, n6093, n6094, n6095,
n6096, n6097, n6098, n6099, n6100, n6101, n6102, n6103, n6104, n6105,
n6106, n6107, n6108, n6109, n6110, n6111, n6112, n6113, n6114, n6115,
n6116, n6117, n6118, n6119, n6120, n6121, n6122, n6123, n6124, n6125,
n6126, n6127, n6128, n6129, n6130, n6131, n6132, n6133, n6134, n6135,
n6136, n6137, n6138, n6139, n6140, n6141, n6142, n6143, n6144, n6145,
n6146, n6147, n6148, n6149, n6150, n6151, n6152, n6153, n6154, n6155,
n6156, n6157, n6158, n6159, n6160, n6161, n6162, n6163, n6164, n6165,
n6166, n6167, n6168, n6169, n6170, n6171, n6172, n6173, n6174, n6175,
n6176, n6177, n6178, n6179, n6180, n6181, n6182, n6183, n6184, n6185,
n6186, n6187, n6188, n6189, n6190, n6191, n6192, n6193, n6194, n6195,
n6196, n6197, n6198, n6199, n6200, n6201, n6202, n6203, n6204, n6205,
n6206, n6207, n6208, n6209, n6210, n6211, n6212, n6213, n6214, n6215,
n6216, n6217, n6218, n6219, n6220, n6221, n6222, n6223, n6224, n6225,
n6226, n6227, n6228, n6229, n6230, n6231, n6232, n6233, n6234, n6235,
n6236, n6237, n6238, n6239, n6240, n6241, n6242, n6243, n6244, n6245,
n6246, n6247, n6248, n6249, n6250, n6251, n6252, n6253, n6254, n6255,
n6256, n6257, n6258, n6259, n6260, n6261, n6262, n6263, n6264, n6265,
n6266, n6267, n6268, n6269, n6270, n6271, n6272, n6273, n6274, n6275,
n6276, n6277, n6278, n6279, n6280, n6281, n6282, n6283, n6284, n6285,
n6286, n6287, n6288, n6289, n6290, n6291, n6292, n6293, n6294, n6295,
n6296, n6297, n6298, n6299, n6300, n6301, n6302, n6303, n6304, n6305,
n6306, n6307, n6308, n6309, n6310, n6311, n6312, n6313, n6314, n6315,
n6316, n6317, n6318, n6319, n6320, n6321, n6322, n6323, n6324, n6325,
n6326, n6327, n6328, n6329, n6330, n6331, n6332, n6333, n6334, n6335,
n6336, n6337, n6338, n6339, n6340, n6341, n6342, n6343, n6344, n6345,
n6346, n6347, n6348, n6349, n6350, n6351, n6352, n6353, n6354, n6355,
n6356, n6357, n6358, n6359, n6360, n6361, n6362, n6363, n6364, n6365,
n6366, n6367, n6368, n6369, n6370, n6371, n6372, n6373, n6374, n6375,
n6376, n6377, n6378, n6379, n6380, n6381, n6382, n6383, n6384, n6385,
n6386, n6387, n6388, n6389, n6390, n6391, n6392, n6393, n6394, n6395,
n6396, n6397, n6398, n6399, n6400, n6401, n6402, n6403, n6404, n6405,
n6406, n6407, n6408, n6409, n6410, n6411, n6412, n6413, n6414, n6415,
n6416, n6417, n6418, n6419, n6420, n6421, n6422, n6423, n6424, n6425,
n6426, n6427, n6428, n6429, n6430, n6431, n6432, n6433, n6434, n6435,
n6436, n6437, n6438, n6439, n6440, n6441, n6442, n6443, n6444, n6445,
n6446, n6447, n6448, n6449, n6450, n6451, n6452, n6453, n6454, n6455,
n6456, n6457, n6458, n6459, n6460, n6461, n6462, n6463, n6464, n6465,
n6466, n6467, n6468, n6469, n6470, n6471, n6472, n6473, n6474, n6475,
n6476, n6477, n6478, n6479, n6480, n6481, n6482, n6483, n6484, n6485,
n6486, n6487, n6488, n6489, n6490, n6491, n6492, n6493, n6494, n6495,
n6496, n6497, n6498, n6499, n6500, n6501, n6502, n6503, n6504, n6505,
n6506, n6507, n6508, n6509, n6510, n6511, n6512, n6513, n6514, n6515,
n6516, n6517, n6518, n6519, n6520, n6521, n6522, n6523, n6524, n6525,
n6526, n6527, n6528, n6529, n6530, n6531, n6532, n6533, n6534, n6535,
n6536, n6537, n6538, n6539, n6540, n6541, n6542, n6543, n6544, n6545,
n6546, n6547, n6548, n6549, n6550, n6551, n6552, n6553, n6554, n6555,
n6556, n6557, n6558, n6559, n6560, n6561, n6562, n6563, n6564, n6565,
n6566, n6567, n6568, n6569, n6570, n6571, n6572, n6573, n6574, n6575,
n6576, n6577, n6578, n6579, n6580, n6581, n6582, n6583, n6584, n6585,
n6586, n6587, n6588, n6589, n6590, n6591, n6592, n6593, n6594, n6595,
n6596, n6597, n6598, n6599, n6600, n6601, n6602, n6603, n6604, n6605,
n6606, n6607, n6608, n6609, n6610, n6611, n6612, n6613, n6614, n6615,
n6616, n6617, n6618, n6619, n6620, n6621, n6622, n6623, n6624, n6625,
n6626, n6627, n6628, n6629, n6630, n6631, n6632, n6633, n6634, n6635,
n6636, n6637, n6638, n6639, n6640, n6641, n6642, n6643, n6644, n6645,
n6646, n6647, n6648, n6649, n6650, n6651, n6652, n6653, n6654, n6655,
n6656, n6657, n6658, n6659, n6660, n6661, n6662, n6663, n6664, n6665,
n6666, n6667, n6668, n6669, n6670, n6671, n6672, n6673, n6674, n6675,
n6676, n6677, n6678, n6679, n6680, n6681, n6682, n6683, n6684, n6685,
n6686, n6687, n6688, n6689, n6690, n6691, n6692, n6693, n6694, n6695,
n6696, n6697, n6698, n6699, n6700, n6701, n6702, n6703, n6704, n6705,
n6706, n6707, n6708, n6709, n6710, n6711, n6712, n6713, n6714, n6715,
n6716, n6717, n6718, n6719, n6720, n6721, n6722, n6723, n6724, n6725,
n6726, n6727, n6728, n6729, n6730, n6731, n6732, n6733, n6734, n6735,
n6736, n6737, n6738, n6739, n6740, n6741, n6742, n6743, n6744, n6745,
n6746, n6747, n6748, n6749, n6750, n6751, n6752, n6753, n6754, n6755,
n6756, n6757, n6758, n6759, n6760, n6761, n6762, n6763, n6764, n6765,
n6766, n6767, n6768, n6769, n6770, n6771, n6772, n6773, n6774, n6775,
n6776, n6777, n6778, n6779, n6780, n6781, n6782, n6783, n6784, n6785,
n6786, n6787, n6788, n6789, n6790, n6791, n6792, n6793, n6794, n6795,
n6796, n6797, n6798, n6799, n6800, n6801, n6802, n6803, n6804, n6805,
n6806, n6807, n6808, n6809, n6810, n6811, n6812, n6813, n6814, n6815,
n6816, n6817, n6818, n6819, n6820, n6821, n6822, n6823, n6824, n6825,
n6826, n6827, n6828, n6829, n6830, n6831, n6832, n6833, n6834, n6835,
n6836, n6837, n6838, n6839, n6840, n6841, n6842, n6843, n6844, n6845,
n6846, n6847, n6848, n6849, n6850, n6851, n6852, n6853, n6854, n6855,
n6856, n6857, n6858, n6859, n6860, n6861, n6862, n6863, n6864, n6865,
n6866, n6867, n6868, n6869, n6870, n6871, n6872, n6873, n6874, n6875,
n6876, n6877, n6878, n6879, n6880, n6881, n6882, n6883, n6884, n6885,
n6886, n6887, n6888, n6889, n6890, n6891, n6892, n6893, n6894, n6895,
n6896, n6897, n6898, n6899, n6900, n6901, n6902, n6903, n6904, n6905,
n6906, n6907, n6908, n6909, n6910, n6911, n6912, n6913, n6914, n6915,
n6916, n6917, n6918, n6919, n6920, n6921, n6922, n6923, n6924, n6925,
n6926, n6927, n6928, n6929, n6930, n6931, n6932, n6933, n6934, n6935,
n6936, n6937, n6938, n6939, n6940, n6941, n6942, n6943, n6944, n6945,
n6946, n6947, n6948, n6949, n6950, n6951, n6952, n6953, n6954, n6955,
n6956, n6957, n6958, n6959, n6960, n6961, n6962, n6963, n6964, n6965,
n6966, n6967, n6968, n6969, n6970, n6971, n6972, n6973, n6974, n6975,
n6976, n6977, n6978, n6979, n6980, n6981, n6982, n6983, n6984, n6985,
n6986, n6987, n6988, n6989, n6990, n6991, n6992, n6993, n6994, n6995,
n6996, n6997, n6998, n6999, n7000, n7001, n7002, n7003, n7004, n7005,
n7006, n7007, n7008, n7009, n7010, n7011, n7012, n7013, n7014, n7015,
n7016, n7017, n7018, n7019, n7020, n7021, n7022, n7023, n7024, n7025,
n7026, n7027, n7028, n7029, n7030, n7031, n7032, n7033, n7034, n7035,
n7036, n7037, n7038, n7039, n7040, n7041, n7042, n7043, n7044, n7045,
n7046, n7047, n7048, n7049, n7050, n7051, n7052, n7053, n7054, n7055,
n7056, n7057, n7058, n7059, n7060, n7061, n7062, n7063, n7064, n7065,
n7066, n7067, n7068, n7069, n7070, n7071, n7072, n7073, n7074, n7075,
n7076, n7077, n7078, n7079, n7080, n7081, n7082, n7083, n7084, n7085,
n7086, n7087, n7088, n7089, n7090, n7091, n7092, n7093, n7094, n7095,
n7096, n7097, n7098, n7099, n7100, n7101, n7102, n7103, n7104, n7105,
n7106, n7107, n7108, n7109, n7110, n7111, n7112, n7113, n7114, n7115,
n7116, n7117, n7118, n7119, n7120, n7121, n7122, n7123, n7124, n7125,
n7126, n7127, n7128, n7129, n7130, n7131, n7132, n7133, n7134, n7135,
n7136, n7137, n7138, n7139, n7140, n7141, n7142, n7143, n7144, n7145,
n7146, n7147, n7148, n7149, n7150, n7151, n7152, n7153, n7154, n7155,
n7156, n7157, n7158, n7159, n7160, n7161, n7162, n7163, n7164, n7165,
n7166, n7167, n7168, n7169, n7170, n7171, n7172, n7173, n7174, n7175,
n7176, n7177, n7178, n7179, n7180, n7181, n7182, n7183, n7184, n7185,
n7186, n7187, n7188, n7189, n7190, n7191, n7192, n7193, n7194, n7195,
n7196, n7197, n7198, n7199, n7200, n7201, n7202, n7203, n7204, n7205,
n7206, n7207, n7208, n7209, n7210, n7211, n7212, n7213, n7214, n7215,
n7216, n7217, n7218, n7219, n7220, n7221, n7222, n7223, n7224, n7225,
n7226, n7227, n7228, n7229, n7230, n7231, n7232, n7233, n7234, n7235,
n7236, n7237, n7238, n7239, n7240, n7241, n7242, n7243, n7244, n7245,
n7246, n7247, n7248, n7249, n7250, n7251, n7252, n7253, n7254, n7255,
n7256, n7257, n7258, n7259, n7260, n7261, n7262, n7263, n7264, n7265,
n7266, n7267, n7268, n7269, n7270, n7271, n7272, n7273, n7274, n7275,
n7276, n7277, n7278, n7279, n7280, n7281, n7282, n7283, n7284, n7285,
n7286, n7287, n7288, n7289, n7290, n7291, n7292, n7293, n7294, n7295,
n7296, n7297, n7298, n7299, n7300, n7301, n7302, n7303, n7304, n7305,
n7306, n7307, n7308, n7309, n7310, n7311, n7312, n7313, n7314, n7315,
n7316, n7317, n7318, n7319, n7320, n7321, n7322, n7323, n7324, n7325,
n7326, n7327, n7328, n7329, n7330, n7331, n7332, n7333, n7334, n7335,
n7336, n7337, n7338, n7339, n7340, n7341, n7342, n7343, n7344, n7345,
n7346, n7347, n7348, n7349, n7350, n7351, n7352, n7353, n7354, n7355,
n7356, n7357, n7358, n7359, n7360, n7361, n7362, n7363, n7364, n7365,
n7366, n7367, n7368, n7369, n7370, n7371, n7372, n7373, n7374, n7375,
n7376, n7377, n7378, n7379, n7380, n7381, n7382, n7383, n7384, n7385,
n7386, n7387, n7388, n7389, n7390, n7391, n7392, n7393, n7394, n7395,
n7396, n7397, n7398, n7399, n7400, n7401, n7402, n7403, n7404, n7405,
n7406, n7407, n7408, n7409, n7410, n7411, n7412, n7413, n7414, n7415,
n7416, n7417, n7418, n7419, n7420, n7421, n7422, n7423, n7424, n7425,
n7426, n7427, n7428, n7429, n7430, n7431, n7432, n7433, n7434, n7435,
n7436, n7437, n7438, n7439, n7440, n7441, n7442, n7443, n7444, n7445,
n7446, n7447, n7448, n7449, n7450, n7451, n7452, n7453, n7454, n7455,
n7456, n7457, n7458, n7459, n7460, n7461, n7462, n7463, n7464, n7465,
n7466, n7467, n7468, n7469, n7470, n7471, n7472, n7473, n7474, n7475,
n7476, n7477, n7478, n7479, n7480, n7481, n7482, n7483, n7484, n7485,
n7487, n7488, n7489, n7490, n7491, n7492, n7493, n7494, n7495, n7496,
n7497, n7498, n7499, n7500, n7501, n7502, n7503, n7504, n7505, n7506,
n7507, n7508, n7509, n7510, n7511, n7512, n7513, n7514, n7515, n7516,
n7517, n7518, n7519, n7520, n7521, n7522, n7523, n7524, n7525, n7526,
n7527, n7528, n7529, n7530, n7531, n7532, n7533, n7534, n7535, n7536,
n7537, n7538, n7539, n7540, n7541, n7542, n7543, n7544, n7545, n7546,
n7547, n7548, n7549, n7550, n7551, n7552, n7553, n7554, n7555, n7556,
n7557, n7558, n7559, n7560, n7561, n7562, n7563, n7564, n7565, n7566,
n7567, n7568, n7569, n7570, n7571, n7572, n7573, n7574, n7575, n7576,
n7577, n7578, n7579, n7580, n7581, n7582, n7583, n7584, n7585, n7586,
n7587, n7588, n7589, n7590, n7591, n7592, n7593, n7594, n7595, n7596,
n7597, n7598, n7599, n7600, n7601, n7602, n7603, n7604, n7605, n7606,
n7607, n7608, n7609, n7610, n7611, n7612, n7613, n7614, n7615, n7616,
n7617, n7618, n7619, n7620, n7621, n7622, n7623, n7624, n7625, n7626,
n7627, n7628, n7629, n7630, n7631, n7632, n7633, n7634, n7635, n7636,
n7637, n7638, n7639, n7640, n7641, n7642, n7643, n7644, n7645, n7646,
n7647, n7648, n7649, n7650, n7651, n7652, n7653, n7654, n7655, n7656,
n7657, n7658, n7659, n7660, n7661, n7662, n7663, n7664, n7665, n7666,
n7667, n7668, n7669, n7670, n7671, n7672, n7673, n7674, n7675, n7676,
n7677, n7678, n7679, n7680, n7681, n7682, n7683, n7684, n7685, n7686,
n7687, n7688, n7689, n7690, n7691, n7692, n7693, n7694, n7695, n7696,
n7697, n7698, n7699, n7700, n7701, n7702, n7703, n7704, n7705, n7706,
n7707, n7708, n7709, n7710, n7711, n7712, n7713, n7714, n7715, n7716,
n7717, n7718, n7719, n7720, n7721, n7722, n7723, n7724, n7725, n7726,
n7727, n7728, n7729, n7730, n7731, n7732, n7733, n7734, n7735, n7736,
n7737, n7738, n7739, n7740, n7741, n7742, n7743, n7744, n7745, n7746,
n7747, n7748, n7749, n7750, n7751, n7752, n7753, n7754, n7755, n7756,
n7757, n7758, n7759, n7760, n7761, n7762, n7763, n7764, n7765, n7766,
n7767, n7768, n7769, n7770, n7771, n7772, n7773, n7774, n7775, n7776,
n7777, n7778, n7779, n7780, n7781, n7782, n7783, n7784, n7785, n7786,
n7787, n7788, n7789, n7790, n7791, n7792, n7793, n7794, n7795, n7796,
n7797, n7798, n7799, n7800, n7801, n7802, n7803, n7804, n7805, n7806,
n7807, n7808, n7809, n7810, n7811, n7812, n7813, n7814, n7815, n7816,
n7817, n7818, n7819, n7820, n7821, n7822, n7823, n7824, n7825, n7826,
n7827, n7828, n7829, n7830, n7831, n7832, n7833, n7834, n7835, n7836,
n7837, n7838, n7839, n7840, n7841, n7842, n7843, n7844, n7845, n7846,
n7847, n7848, n7849, n7850, n7851, n7852, n7853, n7854, n7855, n7856,
n7857, n7858, n7859, n7860, n7861, n7862, n7863, n7864, n7865, n7866,
n7867, n7868, n7869, n7870, n7871, n7872, n7873, n7874, n7875, n7876,
n7877, n7878, n7879, n7880, n7881, n7882, n7883, n7884, n7885, n7886,
n7887, n7888, n7889, n7890, n7891, n7892, n7893, n7894, n7895, n7896,
n7897, n7898, n7899, n7900, n7901, n7902, n7903, n7904, n7905, n7906,
n7907, n7908, n7909, n7910, n7911, n7912, n7913, n7914, n7915, n7916,
n7917, n7918, n7919, n7920, n7921, n7922, n7923, n7924, n7925, n7926,
n7927, n7928, n7929, n7930, n7931, n7932, n7933, n7934, n7935, n7936,
n7937, n7938, n7939, n7940, n7941, n7942, n7943, n7944, n7945, n7946,
n7947, n7948, n7949, n7950, n7951, n7952, n7953, n7954, n7955, n7956,
n7957, n7958, n7959, n7960, n7961, n7962, n7963, n7964, n7965, n7966,
n7967, n7968, n7969, n7970, n7971, n7972, n7973, n7974, n7975, n7976,
n7977, n7978, n7979, n7980, n7981, n7982, n7983, n7984, n7985, n7986,
n7987, n7988, n7989, n7990, n7991, n7992, n7993, n7994, n7995, n7996,
n7997, n7998, n7999, n8000, n8001, n8002, n8003, n8004, n8005, n8006,
n8007, n8008, n8009, n8010, n8011, n8012, n8013, n8014, n8015, n8016,
n8017, n8018, n8019, n8020, n8021, n8022, n8023, n8024, n8025, n8026,
n8027, n8028, n8029, n8030, n8031, n8032, n8033, n8034, n8035, n8036,
n8037, n8038, n8039, n8040, n8041, n8042, n8043, n8044, n8045, n8046,
n8047, n8048, n8049, n8050, n8051, n8052, n8053, n8054, n8055, n8056,
n8057, n8058, n8059, n8060, n8061, n8062, n8063, n8064, n8065, n8066,
n8067, n8068, n8069, n8070, n8071, n8072, n8073, n8074, n8075, n8076,
n8077, n8078, n8079, n8080, n8081, n8082, n8083, n8084, n8085, n8086,
n8087, n8088, n8089, n8090, n8091, n8092, n8093, n8094, n8095, n8096,
n8097, n8098, n8099, n8100, n8101, n8102, n8103, n8104, n8105, n8106,
n8107, n8108, n8109, n8110, n8111, n8112, n8113, n8114, n8115, n8116,
n8117, n8118, n8119, n8120, n8121, n8122, n8123, n8124, n8125, n8126,
n8127, n8128, n8129, n8130, n8131, n8132, n8133, n8134, n8135, n8136,
n8137, n8138, n8139, n8140, n8141, n8142, n8143, n8144, n8145, n8146,
n8147, n8148, n8149, n8150, n8151, n8152, n8153, n8154, n8155, n8156,
n8157, n8158, n8159, n8160, n8161, n8162, n8163, n8164, n8165, n8166,
n8167, n8168, n8169, n8170, n8171, n8172, n8173, n8174, n8175, n8176,
n8177, n8178, n8179, n8180, n8181, n8182, n8183, n8184, n8185, n8186,
n8187, n8188, n8189, n8190, n8191, n8192, n8193, n8194, n8195, n8196,
n8197, n8198, n8199, n8200, n8201, n8202, n8203, n8204, n8205, n8206,
n8207, n8208, n8209, n8210, n8211, n8212, n8213, n8214, n8215, n8216,
n8217, n8218, n8219, n8220, n8221, n8222, n8223, n8224, n8225, n8226,
n8227, n8228, n8229, n8230, n8231, n8232, n8233, n8234, n8235, n8236,
n8237, n8238, n8239, n8240, n8241, n8242, n8243, n8244, n8245, n8246,
n8247, n8248, n8249, n8250, n8251, n8252, n8253, n8254, n8255, n8256,
n8257, n8258, n8259, n8260, n8261, n8262, n8263, n8264, n8265, n8266,
n8267, n8268, n8269, n8270, n8271, n8272, n8273, n8274, n8275, n8276,
n8277, n8278, n8279, n8280, n8281, n8282, n8283, n8284, n8285, n8286,
n8287, n8288, n8289, n8290, n8291, n8292, n8293, n8294, n8295, n8296,
n8297, n8298, n8299, n8300, n8301, n8302, n8303, n8304, n8305, n8306,
n8307, n8308, n8309, n8310, n8311, n8312, n8313, n8314, n8315, n8316,
n8317, n8318, n8319, n8320, n8321, n8322, n8323, n8324, n8325, n8326,
n8327, n8328, n8329, n8330, n8331, n8332, n8333, n8334, n8335, n8336,
n8337, n8338, n8339, n8340, n8341, n8342, n8343, n8344, n8345, n8346,
n8347, n8348, n8349, n8350, n8351, n8352, n8353, n8354, n8355, n8356,
n8357, n8358, n8359, n8360, n8361, n8362, n8363, n8364, n8365, n8366,
n8367, n8368, n8369, n8370, n8371, n8372, n8373, n8374, n8375, n8376,
n8377, n8378, n8379, n8380, n8381, n8382, n8383, n8384, n8385, n8386,
n8387, n8388, n8389, n8390, n8391, n8392, n8393, n8394, n8395, n8396,
n8397, n8398, n8399, n8400, n8401, n8402, n8403, n8404, n8405, n8406,
n8407, n8408, n8409, n8410, n8411, n8412, n8413, n8414, n8415, n8416,
n8417, n8418, n8419, n8420, n8421, n8422, n8423, n8424, n8425, n8426,
n8427, n8428, n8429, n8430, n8431, n8432, n8433, n8434, n8435, n8436,
n8437, n8438, n8439, n8440, n8441, n8442, n8443, n8444, n8445, n8446,
n8447, n8448, n8449, n8450, n8451, n8452, n8453, n8454, n8455, n8456,
n8457, n8458, n8459, n8460, n8461, n8462, n8463, n8464, n8465, n8466,
n8467, n8468, n8469, n8470, n8471, n8472, n8473, n8474, n8475, n8476,
n8477, n8478, n8479, n8480, n8481, n8482, n8483, n8484, n8485, n8486,
n8487, n8488, n8489, n8490, n8491, n8492, n8493, n8494, n8495, n8496,
n8497, n8498, n8499, n8500, n8501, n8502, n8503, n8504, n8505, n8506,
n8507, n8508, n8509, n8510, n8511, n8512, n8513, n8514, n8515, n8516,
n8517, n8518, n8519, n8520, n8521, n8522, n8523, n8524, n8525, n8526,
n8527, n8528, n8529, n8530, n8531, n8532, n8533, n8534, n8535, n8536;
wire [105:0] P_Sgf;
wire [1:0] FSM_selector_B;
wire [63:0] Op_MX;
wire [63:0] Op_MY;
wire [11:0] exp_oper_result;
wire [11:0] S_Oper_A_exp;
wire [52:0] Add_result;
wire [52:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [11:0] Exp_module_Data_S;
wire [26:0] Sgf_operation_Result;
wire [55:0] Sgf_operation_ODD1_Q_middle;
wire [53:27] Sgf_operation_ODD1_Q_right;
wire [51:0] Sgf_operation_ODD1_Q_left;
DFFHQX4TS Sgf_operation_ODD1_left_DatO_reg_28_ ( .D(
Sgf_operation_ODD1_left_N28), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[28]) );
DFFHQX4TS Sgf_operation_ODD1_left_DatO_reg_30_ ( .D(
Sgf_operation_ODD1_left_N30), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[30]) );
DFFHQX4TS Sgf_operation_ODD1_left_DatO_reg_31_ ( .D(
Sgf_operation_ODD1_left_N31), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[31]) );
DFFHQX4TS Sgf_operation_ODD1_left_DatO_reg_32_ ( .D(
Sgf_operation_ODD1_left_N32), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[32]) );
DFFHQX4TS Sgf_operation_ODD1_left_DatO_reg_33_ ( .D(
Sgf_operation_ODD1_left_N33), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[33]) );
DFFHQX4TS Sgf_operation_ODD1_left_DatO_reg_34_ ( .D(
Sgf_operation_ODD1_left_N34), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[34]) );
DFFHQX4TS Sgf_operation_ODD1_left_DatO_reg_35_ ( .D(
Sgf_operation_ODD1_left_N35), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[35]) );
DFFHQX4TS Sgf_operation_ODD1_left_DatO_reg_39_ ( .D(
Sgf_operation_ODD1_left_N39), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[39]) );
DFFHQX4TS Sgf_operation_ODD1_left_DatO_reg_41_ ( .D(
Sgf_operation_ODD1_left_N41), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[41]) );
DFFHQX4TS Sgf_operation_ODD1_left_DatO_reg_42_ ( .D(
Sgf_operation_ODD1_left_N42), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[42]) );
DFFHQX4TS Sgf_operation_ODD1_left_DatO_reg_43_ ( .D(
Sgf_operation_ODD1_left_N43), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[43]) );
DFFHQX4TS Sgf_operation_ODD1_left_DatO_reg_44_ ( .D(
Sgf_operation_ODD1_left_N44), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[44]) );
DFFHQX4TS Sgf_operation_ODD1_left_DatO_reg_45_ ( .D(
Sgf_operation_ODD1_left_N45), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[45]) );
DFFHQX4TS Sgf_operation_ODD1_left_DatO_reg_46_ ( .D(
Sgf_operation_ODD1_left_N46), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[46]) );
DFFHQX4TS Sgf_operation_ODD1_left_DatO_reg_49_ ( .D(
Sgf_operation_ODD1_left_N49), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[49]) );
DFFHQX4TS Sgf_operation_ODD1_left_DatO_reg_50_ ( .D(
Sgf_operation_ODD1_left_N50), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[50]) );
DFFHQX4TS Sgf_operation_ODD1_right_DatO_reg_32_ ( .D(
Sgf_operation_ODD1_right_N32), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[32]) );
DFFHQX4TS Sgf_operation_ODD1_right_DatO_reg_35_ ( .D(
Sgf_operation_ODD1_right_N35), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[35]) );
DFFHQX4TS Sgf_operation_ODD1_right_DatO_reg_37_ ( .D(
Sgf_operation_ODD1_right_N37), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[37]) );
DFFHQX4TS Sgf_operation_ODD1_right_DatO_reg_38_ ( .D(
Sgf_operation_ODD1_right_N38), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[38]) );
DFFHQX4TS Sgf_operation_ODD1_right_DatO_reg_43_ ( .D(
Sgf_operation_ODD1_right_N43), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[43]) );
DFFHQX4TS Sgf_operation_ODD1_right_DatO_reg_45_ ( .D(
Sgf_operation_ODD1_right_N45), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[45]) );
DFFHQX4TS Sgf_operation_ODD1_right_DatO_reg_46_ ( .D(
Sgf_operation_ODD1_right_N46), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[46]) );
DFFHQX4TS Sgf_operation_ODD1_right_DatO_reg_47_ ( .D(
Sgf_operation_ODD1_right_N47), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[47]) );
DFFHQX4TS Sgf_operation_ODD1_right_DatO_reg_48_ ( .D(
Sgf_operation_ODD1_right_N48), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[48]) );
DFFHQX4TS Sgf_operation_ODD1_right_DatO_reg_49_ ( .D(
Sgf_operation_ODD1_right_N49), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[49]) );
DFFHQX4TS Sgf_operation_ODD1_right_DatO_reg_50_ ( .D(
Sgf_operation_ODD1_right_N50), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[50]) );
DFFQX1TS Sgf_operation_ODD1_right_DatO_reg_51_ ( .D(
Sgf_operation_ODD1_right_N51), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[51]) );
DFFQX1TS Sgf_operation_ODD1_right_DatO_reg_53_ ( .D(
Sgf_operation_ODD1_right_N53), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[53]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_51_ ( .D(
Sgf_operation_ODD1_middle_N51), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[51]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_52_ ( .D(
Sgf_operation_ODD1_middle_N52), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[52]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_53_ ( .D(
Sgf_operation_ODD1_middle_N53), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[53]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_54_ ( .D(
Sgf_operation_ODD1_middle_N54), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[54]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_55_ ( .D(
Sgf_operation_ODD1_middle_N55), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[55]) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_63_ ( .D(n715), .CK(clk), .RN(
n8518), .Q(Op_MY[63]) );
DFFRXLTS Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n581), .CK(clk),
.RN(n8518), .Q(zero_flag) );
DFFRXLTS Sel_A_Q_reg_0_ ( .D(n710), .CK(clk), .RN(n8518), .Q(FSM_selector_A),
.QN(n8471) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_51_ ( .D(n697), .CK(clk), .RN(
n8519), .Q(Op_MX[51]), .QN(n750) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_50_ ( .D(n696), .CK(clk), .RN(
n8519), .Q(Op_MX[50]), .QN(n1034) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_49_ ( .D(n695), .CK(clk), .RN(
n8519), .Q(Op_MX[49]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_48_ ( .D(n694), .CK(clk), .RN(
n8519), .Q(Op_MX[48]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_47_ ( .D(n693), .CK(clk), .RN(
n8519), .Q(Op_MX[47]), .QN(n1015) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_46_ ( .D(n692), .CK(clk), .RN(
n8519), .Q(Op_MX[46]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_45_ ( .D(n691), .CK(clk), .RN(
n8520), .Q(Op_MX[45]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_44_ ( .D(n690), .CK(clk), .RN(
n8520), .Q(Op_MX[44]), .QN(n1035) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_43_ ( .D(n689), .CK(clk), .RN(
n8520), .Q(Op_MX[43]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_42_ ( .D(n688), .CK(clk), .RN(
n8520), .Q(Op_MX[42]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_41_ ( .D(n687), .CK(clk), .RN(
n8520), .Q(Op_MX[41]), .QN(n1022) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_40_ ( .D(n686), .CK(clk), .RN(
n8520), .Q(Op_MX[40]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_39_ ( .D(n685), .CK(clk), .RN(
n8520), .Q(Op_MX[39]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_38_ ( .D(n684), .CK(clk), .RN(
n8520), .Q(Op_MX[38]), .QN(n1020) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_37_ ( .D(n683), .CK(clk), .RN(
n8520), .Q(Op_MX[37]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_36_ ( .D(n682), .CK(clk), .RN(
n8520), .Q(Op_MX[36]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_35_ ( .D(n681), .CK(clk), .RN(
n8521), .Q(Op_MX[35]), .QN(n793) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_34_ ( .D(n680), .CK(clk), .RN(
n8521), .Q(Op_MX[34]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_33_ ( .D(n679), .CK(clk), .RN(
n8521), .Q(Op_MX[33]), .QN(n748) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_32_ ( .D(n678), .CK(clk), .RN(
n8521), .Q(Op_MX[32]), .QN(n767) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n677), .CK(clk), .RN(
n8521), .Q(Op_MX[31]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n676), .CK(clk), .RN(
n8521), .Q(Op_MX[30]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n675), .CK(clk), .RN(
n8521), .Q(Op_MX[29]), .QN(n1032) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n674), .CK(clk), .RN(
n8521), .Q(Op_MX[28]), .QN(n766) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n672), .CK(clk), .RN(
n8521), .Q(Op_MX[26]), .QN(n971) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n671), .CK(clk), .RN(
n8522), .Q(Op_MX[25]), .QN(n794) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n670), .CK(clk), .RN(
n8522), .Q(Op_MX[24]), .QN(n751) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n669), .CK(clk), .RN(
n8522), .Q(Op_MX[23]), .QN(n772) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n668), .CK(clk), .RN(
n8522), .Q(Op_MX[22]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n667), .CK(clk), .RN(
n8522), .Q(Op_MX[21]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n666), .CK(clk), .RN(
n8522), .Q(Op_MX[20]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n665), .CK(clk), .RN(
n8522), .Q(Op_MX[19]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n664), .CK(clk), .RN(
n8522), .Q(Op_MX[18]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n663), .CK(clk), .RN(
n8522), .Q(Op_MX[17]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n662), .CK(clk), .RN(
n8522), .Q(Op_MX[16]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n661), .CK(clk), .RN(
n8523), .Q(Op_MX[15]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n660), .CK(clk), .RN(
n8523), .Q(Op_MX[14]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n659), .CK(clk), .RN(
n8523), .Q(Op_MX[13]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n658), .CK(clk), .RN(
n8523), .Q(Op_MX[12]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n657), .CK(clk), .RN(
n8523), .Q(Op_MX[11]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n656), .CK(clk), .RN(
n8523), .Q(Op_MX[10]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n655), .CK(clk), .RN(
n8523), .Q(Op_MX[9]), .QN(n770) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n654), .CK(clk), .RN(
n8523), .Q(Op_MX[8]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n653), .CK(clk), .RN(
n8523), .Q(Op_MX[7]), .QN(n800) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n652), .CK(clk), .RN(
n8523), .Q(Op_MX[6]), .QN(n747) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n651), .CK(clk), .RN(
n8524), .Q(Op_MX[5]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n650), .CK(clk), .RN(
n8524), .Q(Op_MX[4]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n649), .CK(clk), .RN(
n8524), .Q(Op_MX[3]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n648), .CK(clk), .RN(
n8524), .Q(Op_MX[2]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n647), .CK(clk), .RN(
n8524), .Q(Op_MX[1]) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n646), .CK(clk), .RN(
n8524), .Q(Op_MX[0]), .QN(n764) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n579), .CK(clk), .RN(n8529),
.Q(Add_result[0]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_50_ ( .D(n632), .CK(clk), .RN(
n8531), .Q(Op_MY[50]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_49_ ( .D(n631), .CK(clk), .RN(
n8531), .Q(Op_MY[49]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_48_ ( .D(n630), .CK(clk), .RN(
n8531), .Q(Op_MY[48]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_47_ ( .D(n629), .CK(clk), .RN(
n8531), .Q(Op_MY[47]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_46_ ( .D(n628), .CK(clk), .RN(
n8531), .Q(Op_MY[46]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_45_ ( .D(n627), .CK(clk), .RN(
n8531), .Q(Op_MY[45]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_44_ ( .D(n626), .CK(clk), .RN(
n8532), .Q(Op_MY[44]), .QN(n773) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_43_ ( .D(n625), .CK(clk), .RN(
n8532), .Q(Op_MY[43]), .QN(n804) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_42_ ( .D(n624), .CK(clk), .RN(
n8532), .Q(Op_MY[42]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_41_ ( .D(n623), .CK(clk), .RN(
n8532), .Q(Op_MY[41]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_40_ ( .D(n622), .CK(clk), .RN(
n8532), .Q(Op_MY[40]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_39_ ( .D(n621), .CK(clk), .RN(
n8532), .Q(Op_MY[39]), .QN(n765) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_38_ ( .D(n620), .CK(clk), .RN(
n8532), .Q(Op_MY[38]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_37_ ( .D(n619), .CK(clk), .RN(
n8532), .Q(Op_MY[37]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_36_ ( .D(n618), .CK(clk), .RN(
n8532), .Q(Op_MY[36]), .QN(n802) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_35_ ( .D(n617), .CK(clk), .RN(
n8532), .Q(Op_MY[35]), .QN(n782) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_34_ ( .D(n616), .CK(clk), .RN(
n8535), .Q(Op_MY[34]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_33_ ( .D(n615), .CK(clk), .RN(
n8534), .Q(Op_MY[33]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n613), .CK(clk), .RN(
n8534), .Q(Op_MY[31]), .QN(n798) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n612), .CK(clk), .RN(
n8535), .Q(Op_MY[30]), .QN(n801) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n611), .CK(clk), .RN(
n8535), .Q(Op_MY[29]), .QN(n854) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n610), .CK(clk), .RN(
n8535), .Q(Op_MY[28]), .QN(n797) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n609), .CK(clk), .RN(
n8535), .Q(Op_MY[27]), .QN(n803) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n608), .CK(clk), .RN(
n8534), .Q(Op_MY[26]), .QN(n1017) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n607), .CK(clk), .RN(
n8533), .Q(Op_MY[25]), .QN(n1010) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n606), .CK(clk), .RN(
n8533), .Q(Op_MY[24]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n605), .CK(clk), .RN(
n8533), .Q(Op_MY[23]), .QN(n769) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n604), .CK(clk), .RN(
n8533), .Q(Op_MY[22]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n603), .CK(clk), .RN(
n8533), .Q(Op_MY[21]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n602), .CK(clk), .RN(
n8533), .Q(Op_MY[20]), .QN(n1018) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n601), .CK(clk), .RN(
n8533), .Q(Op_MY[19]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n600), .CK(clk), .RN(
n8533), .Q(Op_MY[18]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n599), .CK(clk), .RN(
n8533), .Q(Op_MY[17]), .QN(n783) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n598), .CK(clk), .RN(
n8510), .Q(Op_MY[16]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n597), .CK(clk), .RN(
n8503), .Q(Op_MY[15]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n596), .CK(clk), .RN(
n8503), .Q(Op_MY[14]), .QN(n1009) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n595), .CK(clk), .RN(
n8503), .Q(Op_MY[13]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n594), .CK(clk), .RN(
n8503), .Q(Op_MY[12]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n593), .CK(clk), .RN(
n8503), .Q(Op_MY[11]), .QN(n735) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n592), .CK(clk), .RN(
n8503), .Q(Op_MY[10]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n591), .CK(clk), .RN(
n8503), .Q(Op_MY[9]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n590), .CK(clk), .RN(
n8503), .Q(Op_MY[8]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n589), .CK(clk), .RN(
n8503), .Q(Op_MY[7]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n588), .CK(clk), .RN(
n8504), .Q(Op_MY[6]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n587), .CK(clk), .RN(
n8504), .Q(Op_MY[5]), .QN(n730) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n586), .CK(clk), .RN(
n8504), .Q(Op_MY[4]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n585), .CK(clk), .RN(
n8504), .Q(Op_MY[3]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n584), .CK(clk), .RN(
n8504), .Q(Op_MY[2]), .QN(n1013) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n583), .CK(clk), .RN(
n8504), .Q(Op_MY[1]), .QN(n1005) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n582), .CK(clk), .RN(
n8504), .Q(Op_MY[0]), .QN(n999) );
DFFRXLTS Sgf_operation_ODD1_finalreg_Q_reg_52_ ( .D(n473), .CK(clk), .RN(
n8497), .Q(P_Sgf[52]) );
DFFRX1TS Sel_B_Q_reg_0_ ( .D(n419), .CK(clk), .RN(n8504), .Q(
FSM_selector_B[0]), .QN(n8450) );
DFFHQX4TS Sgf_operation_ODD1_right_DatO_reg_44_ ( .D(
Sgf_operation_ODD1_right_N44), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[44]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_63_ ( .D(n287),
.CK(clk), .RN(n8518), .Q(final_result_ieee[63]), .QN(n8490) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n356), .CK(clk),
.RN(n8511), .Q(Sgf_normalized_result[3]), .QN(n8489) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n360), .CK(clk),
.RN(n8510), .Q(Sgf_normalized_result[7]), .QN(n8488) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n366), .CK(clk),
.RN(n8510), .Q(Sgf_normalized_result[13]), .QN(n8487) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n368), .CK(clk),
.RN(n8510), .Q(Sgf_normalized_result[15]), .QN(n8486) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n370), .CK(clk),
.RN(n8509), .Q(Sgf_normalized_result[17]), .QN(n8485) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n372), .CK(clk),
.RN(n8509), .Q(Sgf_normalized_result[19]), .QN(n8484) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n362), .CK(clk),
.RN(n8510), .Q(Sgf_normalized_result[9]), .QN(n8483) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n364), .CK(clk),
.RN(n8510), .Q(Sgf_normalized_result[11]), .QN(n8482) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n374), .CK(clk),
.RN(n8509), .Q(Sgf_normalized_result[21]), .QN(n8481) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n376), .CK(clk),
.RN(n8509), .Q(Sgf_normalized_result[23]), .QN(n8480) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(n378), .CK(clk),
.RN(n8509), .Q(Sgf_normalized_result[25]), .QN(n8479) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_27_ ( .D(n380), .CK(clk),
.RN(n8508), .Q(Sgf_normalized_result[27]), .QN(n8478) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_29_ ( .D(n382), .CK(clk),
.RN(n8508), .Q(Sgf_normalized_result[29]), .QN(n8477) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_37_ ( .D(n390), .CK(clk),
.RN(n8507), .Q(Sgf_normalized_result[37]), .QN(n8476) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_31_ ( .D(n384), .CK(clk),
.RN(n8508), .Q(Sgf_normalized_result[31]), .QN(n8475) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_33_ ( .D(n386), .CK(clk),
.RN(n8508), .Q(Sgf_normalized_result[33]), .QN(n8474) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_35_ ( .D(n388), .CK(clk),
.RN(n8508), .Q(Sgf_normalized_result[35]), .QN(n8473) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_41_ ( .D(n394), .CK(clk),
.RN(n8507), .Q(Sgf_normalized_result[41]), .QN(n8472) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n367), .CK(clk),
.RN(n8510), .Q(Sgf_normalized_result[14]), .QN(n8469) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n359), .CK(clk),
.RN(n8511), .Q(Sgf_normalized_result[6]), .QN(n8468) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n365), .CK(clk),
.RN(n8510), .Q(Sgf_normalized_result[12]), .QN(n8467) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n369), .CK(clk),
.RN(n8509), .Q(Sgf_normalized_result[16]), .QN(n8466) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n371), .CK(clk),
.RN(n8509), .Q(Sgf_normalized_result[18]), .QN(n8465) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_36_ ( .D(n389), .CK(clk),
.RN(n8507), .Q(Sgf_normalized_result[36]), .QN(n8464) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n375), .CK(clk),
.RN(n8509), .Q(Sgf_normalized_result[22]), .QN(n8463) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_26_ ( .D(n379), .CK(clk),
.RN(n8508), .Q(Sgf_normalized_result[26]), .QN(n8462) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_30_ ( .D(n383), .CK(clk),
.RN(n8508), .Q(Sgf_normalized_result[30]), .QN(n8461) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n361), .CK(clk),
.RN(n8510), .Q(Sgf_normalized_result[8]), .QN(n8460) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n363), .CK(clk),
.RN(n8510), .Q(Sgf_normalized_result[10]), .QN(n8459) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n373), .CK(clk),
.RN(n8509), .Q(Sgf_normalized_result[20]), .QN(n8458) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(n377), .CK(clk),
.RN(n8509), .Q(Sgf_normalized_result[24]), .QN(n8457) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_28_ ( .D(n381), .CK(clk),
.RN(n8508), .Q(Sgf_normalized_result[28]), .QN(n8456) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_32_ ( .D(n385), .CK(clk),
.RN(n8508), .Q(Sgf_normalized_result[32]), .QN(n8455) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_34_ ( .D(n387), .CK(clk),
.RN(n8508), .Q(Sgf_normalized_result[34]), .QN(n8454) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_40_ ( .D(n393), .CK(clk),
.RN(n8507), .Q(Sgf_normalized_result[40]), .QN(n8452) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_38_ ( .D(n391), .CK(clk),
.RN(n8507), .Q(Sgf_normalized_result[38]), .QN(n8451) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_39_ ( .D(n392), .CK(clk),
.RN(n8507), .Q(Sgf_normalized_result[39]), .QN(n8449) );
DFFRX1TS Sel_C_Q_reg_0_ ( .D(n709), .CK(clk), .RN(n8505), .Q(FSM_selector_C),
.QN(n8448) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n351),
.CK(clk), .RN(n8511), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n350),
.CK(clk), .RN(n8511), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n349),
.CK(clk), .RN(n8512), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n348),
.CK(clk), .RN(n8512), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n347),
.CK(clk), .RN(n8512), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n346),
.CK(clk), .RN(n8512), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n345),
.CK(clk), .RN(n8512), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n344),
.CK(clk), .RN(n8512), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n343),
.CK(clk), .RN(n8512), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n342),
.CK(clk), .RN(n8512), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n341),
.CK(clk), .RN(n8512), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n340),
.CK(clk), .RN(n8512), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n339),
.CK(clk), .RN(n8513), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n338),
.CK(clk), .RN(n8513), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n337),
.CK(clk), .RN(n8513), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n336),
.CK(clk), .RN(n8513), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n335),
.CK(clk), .RN(n8513), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n334),
.CK(clk), .RN(n8513), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n333),
.CK(clk), .RN(n8513), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n332),
.CK(clk), .RN(n8513), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n331),
.CK(clk), .RN(n8513), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n330),
.CK(clk), .RN(n8513), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n329),
.CK(clk), .RN(n8514), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n328),
.CK(clk), .RN(n8514), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n327),
.CK(clk), .RN(n8514), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n326),
.CK(clk), .RN(n8514), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n325),
.CK(clk), .RN(n8514), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n324),
.CK(clk), .RN(n8514), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n323),
.CK(clk), .RN(n8514), .Q(final_result_ieee[28]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n322),
.CK(clk), .RN(n8514), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n321),
.CK(clk), .RN(n8514), .Q(final_result_ieee[30]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n320),
.CK(clk), .RN(n8514), .Q(final_result_ieee[31]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_32_ ( .D(n319),
.CK(clk), .RN(n8515), .Q(final_result_ieee[32]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_33_ ( .D(n318),
.CK(clk), .RN(n8515), .Q(final_result_ieee[33]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_34_ ( .D(n317),
.CK(clk), .RN(n8515), .Q(final_result_ieee[34]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_35_ ( .D(n316),
.CK(clk), .RN(n8515), .Q(final_result_ieee[35]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_36_ ( .D(n315),
.CK(clk), .RN(n8515), .Q(final_result_ieee[36]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_37_ ( .D(n314),
.CK(clk), .RN(n8515), .Q(final_result_ieee[37]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_38_ ( .D(n313),
.CK(clk), .RN(n8515), .Q(final_result_ieee[38]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_39_ ( .D(n312),
.CK(clk), .RN(n8515), .Q(final_result_ieee[39]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_40_ ( .D(n311),
.CK(clk), .RN(n8515), .Q(final_result_ieee[40]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_41_ ( .D(n310),
.CK(clk), .RN(n8515), .Q(final_result_ieee[41]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_42_ ( .D(n309),
.CK(clk), .RN(n8516), .Q(final_result_ieee[42]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_43_ ( .D(n308),
.CK(clk), .RN(n8516), .Q(final_result_ieee[43]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_44_ ( .D(n307),
.CK(clk), .RN(n8516), .Q(final_result_ieee[44]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_45_ ( .D(n306),
.CK(clk), .RN(n8516), .Q(final_result_ieee[45]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_46_ ( .D(n305),
.CK(clk), .RN(n8516), .Q(final_result_ieee[46]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_47_ ( .D(n304),
.CK(clk), .RN(n8516), .Q(final_result_ieee[47]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_48_ ( .D(n303),
.CK(clk), .RN(n8516), .Q(final_result_ieee[48]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_49_ ( .D(n302),
.CK(clk), .RN(n8516), .Q(final_result_ieee[49]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_50_ ( .D(n301),
.CK(clk), .RN(n8516), .Q(final_result_ieee[50]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_51_ ( .D(n300),
.CK(clk), .RN(n8516), .Q(final_result_ieee[51]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_52_ ( .D(n299),
.CK(clk), .RN(n8517), .Q(final_result_ieee[52]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_53_ ( .D(n298),
.CK(clk), .RN(n8517), .Q(final_result_ieee[53]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_54_ ( .D(n297),
.CK(clk), .RN(n8517), .Q(final_result_ieee[54]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_55_ ( .D(n296),
.CK(clk), .RN(n8517), .Q(final_result_ieee[55]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_56_ ( .D(n295),
.CK(clk), .RN(n8517), .Q(final_result_ieee[56]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_57_ ( .D(n294),
.CK(clk), .RN(n8517), .Q(final_result_ieee[57]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_58_ ( .D(n293),
.CK(clk), .RN(n8517), .Q(final_result_ieee[58]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_59_ ( .D(n292),
.CK(clk), .RN(n8517), .Q(final_result_ieee[59]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_60_ ( .D(n291),
.CK(clk), .RN(n8517), .Q(final_result_ieee[60]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_61_ ( .D(n290),
.CK(clk), .RN(n8517), .Q(final_result_ieee[61]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_62_ ( .D(n289),
.CK(clk), .RN(n8518), .Q(final_result_ieee[62]) );
DFFRXLTS Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n405), .CK(clk), .RN(n8504), .Q(
Exp_module_Overflow_flag_A) );
DFFQX1TS Sgf_operation_ODD1_left_DatO_reg_51_ ( .D(
Sgf_operation_ODD1_left_N51), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[51]) );
CMPR32X2TS DP_OP_36J42_124_1029_U2 ( .A(n8366), .B(S_Oper_A_exp[11]), .C(
DP_OP_36J42_124_1029_n2), .CO(DP_OP_36J42_124_1029_n1), .S(
Exp_module_Data_S[11]) );
CMPR32X2TS DP_OP_36J42_124_1029_U9 ( .A(DP_OP_36J42_124_1029_n24), .B(
S_Oper_A_exp[4]), .C(DP_OP_36J42_124_1029_n9), .CO(
DP_OP_36J42_124_1029_n8), .S(Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_36J42_124_1029_U10 ( .A(DP_OP_36J42_124_1029_n25), .B(
S_Oper_A_exp[3]), .C(DP_OP_36J42_124_1029_n10), .CO(
DP_OP_36J42_124_1029_n9), .S(Exp_module_Data_S[3]) );
CMPR42X2TS mult_x_24_U887 ( .A(mult_x_24_n1064), .B(mult_x_24_n1603), .C(
mult_x_24_n1067), .D(mult_x_24_n1630), .ICI(mult_x_24_n1657), .S(
mult_x_24_n1062), .ICO(mult_x_24_n1060), .CO(mult_x_24_n1061) );
CMPR42X2TS mult_x_24_U885 ( .A(mult_x_24_n1059), .B(mult_x_24_n1602), .C(
mult_x_24_n1060), .D(mult_x_24_n1656), .ICI(mult_x_24_n1629), .S(
mult_x_24_n1057), .ICO(mult_x_24_n1055), .CO(mult_x_24_n1056) );
CMPR42X2TS mult_x_24_U883 ( .A(mult_x_24_n1054), .B(mult_x_24_n1628), .C(
mult_x_24_n1601), .D(mult_x_24_n1655), .ICI(mult_x_24_n1055), .S(
mult_x_24_n1052), .ICO(mult_x_24_n1050), .CO(mult_x_24_n1051) );
CMPR42X2TS mult_x_24_U880 ( .A(mult_x_24_n1047), .B(mult_x_24_n1600), .C(
mult_x_24_n1627), .D(mult_x_24_n1654), .ICI(mult_x_24_n1050), .S(
mult_x_24_n1045), .ICO(mult_x_24_n1043), .CO(mult_x_24_n1044) );
CMPR42X2TS mult_x_24_U877 ( .A(mult_x_24_n1653), .B(mult_x_24_n1626), .C(
mult_x_24_n1599), .D(mult_x_24_n1040), .ICI(mult_x_24_n1043), .S(
mult_x_24_n1038), .ICO(mult_x_24_n1036), .CO(mult_x_24_n1037) );
CMPR42X2TS mult_x_24_U874 ( .A(mult_x_24_n1652), .B(mult_x_24_n1625), .C(
mult_x_24_n1039), .D(mult_x_24_n1033), .ICI(mult_x_24_n1036), .S(
mult_x_24_n1031), .ICO(mult_x_24_n1029), .CO(mult_x_24_n1030) );
CMPR42X2TS mult_x_24_U872 ( .A(mult_x_24_n1028), .B(mult_x_24_n1543), .C(
mult_x_24_n1034), .D(mult_x_24_n1570), .ICI(mult_x_24_n1651), .S(
mult_x_24_n1026), .ICO(mult_x_24_n1024), .CO(mult_x_24_n1025) );
CMPR42X2TS mult_x_24_U871 ( .A(mult_x_24_n1624), .B(mult_x_24_n1597), .C(
mult_x_24_n1032), .D(mult_x_24_n1029), .ICI(mult_x_24_n1026), .S(
mult_x_24_n1023), .ICO(mult_x_24_n1021), .CO(mult_x_24_n1022) );
CMPR42X2TS mult_x_24_U869 ( .A(mult_x_24_n1020), .B(mult_x_24_n1542), .C(
mult_x_24_n1024), .D(mult_x_24_n1623), .ICI(mult_x_24_n1596), .S(
mult_x_24_n1018), .ICO(mult_x_24_n1016), .CO(mult_x_24_n1017) );
CMPR42X2TS mult_x_24_U868 ( .A(mult_x_24_n1569), .B(mult_x_24_n1650), .C(
mult_x_24_n1025), .D(mult_x_24_n1021), .ICI(mult_x_24_n1018), .S(
mult_x_24_n1015), .ICO(mult_x_24_n1013), .CO(mult_x_24_n1014) );
CMPR42X1TS mult_x_24_U866 ( .A(mult_x_24_n1012), .B(mult_x_24_n1568), .C(
mult_x_24_n1541), .D(mult_x_24_n1622), .ICI(mult_x_24_n1016), .S(
mult_x_24_n1010), .ICO(mult_x_24_n1008), .CO(mult_x_24_n1009) );
CMPR42X2TS mult_x_24_U865 ( .A(mult_x_24_n1595), .B(mult_x_24_n1649), .C(
mult_x_24_n1017), .D(mult_x_24_n1013), .ICI(mult_x_24_n1010), .S(
mult_x_24_n1007), .ICO(mult_x_24_n1005), .CO(mult_x_24_n1006) );
CMPR42X2TS mult_x_24_U862 ( .A(mult_x_24_n1002), .B(mult_x_24_n1540), .C(
mult_x_24_n1594), .D(mult_x_24_n1567), .ICI(mult_x_24_n1648), .S(
mult_x_24_n1000), .ICO(mult_x_24_n998), .CO(mult_x_24_n999) );
CMPR42X2TS mult_x_24_U861 ( .A(mult_x_24_n1621), .B(mult_x_24_n1008), .C(
mult_x_24_n1009), .D(mult_x_24_n1000), .ICI(mult_x_24_n1005), .S(
mult_x_24_n997), .ICO(mult_x_24_n995), .CO(mult_x_24_n996) );
CMPR42X2TS mult_x_24_U858 ( .A(mult_x_24_n1593), .B(mult_x_24_n1539), .C(
mult_x_24_n992), .D(mult_x_24_n1620), .ICI(mult_x_24_n998), .S(
mult_x_24_n990), .ICO(mult_x_24_n988), .CO(mult_x_24_n989) );
CMPR42X2TS mult_x_24_U857 ( .A(mult_x_24_n1566), .B(mult_x_24_n1647), .C(
mult_x_24_n999), .D(mult_x_24_n990), .ICI(mult_x_24_n995), .S(
mult_x_24_n987), .ICO(mult_x_24_n985), .CO(mult_x_24_n986) );
CMPR42X2TS mult_x_24_U853 ( .A(mult_x_24_n1619), .B(mult_x_24_n982), .C(
mult_x_24_n989), .D(mult_x_24_n980), .ICI(mult_x_24_n985), .S(
mult_x_24_n977), .ICO(mult_x_24_n975), .CO(mult_x_24_n976) );
CMPR42X2TS mult_x_24_U851 ( .A(mult_x_24_n974), .B(mult_x_24_n1483), .C(
mult_x_24_n983), .D(mult_x_24_n1510), .ICI(mult_x_24_n1537), .S(
mult_x_24_n972), .ICO(mult_x_24_n970), .CO(mult_x_24_n971) );
CMPR42X2TS mult_x_24_U850 ( .A(mult_x_24_n1591), .B(mult_x_24_n1564), .C(
mult_x_24_n981), .D(mult_x_24_n1645), .ICI(mult_x_24_n978), .S(
mult_x_24_n969), .ICO(mult_x_24_n967), .CO(mult_x_24_n968) );
CMPR42X2TS mult_x_24_U849 ( .A(mult_x_24_n1618), .B(mult_x_24_n972), .C(
mult_x_24_n979), .D(mult_x_24_n969), .ICI(mult_x_24_n975), .S(
mult_x_24_n966), .ICO(mult_x_24_n964), .CO(mult_x_24_n965) );
CMPR42X2TS mult_x_24_U847 ( .A(mult_x_24_n963), .B(mult_x_24_n1482), .C(
mult_x_24_n970), .D(mult_x_24_n1536), .ICI(mult_x_24_n1563), .S(
mult_x_24_n961), .ICO(mult_x_24_n959), .CO(mult_x_24_n960) );
CMPR42X2TS mult_x_24_U845 ( .A(mult_x_24_n971), .B(mult_x_24_n961), .C(
mult_x_24_n968), .D(mult_x_24_n958), .ICI(mult_x_24_n964), .S(
mult_x_24_n955), .ICO(mult_x_24_n953), .CO(mult_x_24_n954) );
CMPR42X2TS mult_x_24_U842 ( .A(mult_x_24_n1562), .B(mult_x_24_n1616), .C(
mult_x_24_n1589), .D(mult_x_24_n1643), .ICI(mult_x_24_n960), .S(
mult_x_24_n947), .ICO(mult_x_24_n945), .CO(mult_x_24_n946) );
CMPR42X2TS mult_x_24_U841 ( .A(mult_x_24_n956), .B(mult_x_24_n950), .C(
mult_x_24_n957), .D(mult_x_24_n947), .ICI(mult_x_24_n953), .S(
mult_x_24_n944), .ICO(mult_x_24_n942), .CO(mult_x_24_n943) );
CMPR42X1TS mult_x_24_U837 ( .A(mult_x_24_n1507), .B(mult_x_24_n948), .C(
mult_x_24_n1588), .D(mult_x_24_n1642), .ICI(mult_x_24_n945), .S(
mult_x_24_n934), .ICO(mult_x_24_n932), .CO(mult_x_24_n933) );
CMPR42X2TS mult_x_24_U836 ( .A(mult_x_24_n949), .B(mult_x_24_n937), .C(
mult_x_24_n946), .D(mult_x_24_n934), .ICI(mult_x_24_n942), .S(
mult_x_24_n931), .ICO(mult_x_24_n929), .CO(mult_x_24_n930) );
CMPR42X2TS mult_x_24_U833 ( .A(mult_x_24_n1533), .B(mult_x_24_n1479), .C(
mult_x_24_n926), .D(mult_x_24_n1560), .ICI(mult_x_24_n932), .S(
mult_x_24_n924), .ICO(mult_x_24_n922), .CO(mult_x_24_n923) );
CMPR42X2TS mult_x_24_U832 ( .A(mult_x_24_n1506), .B(mult_x_24_n1614), .C(
mult_x_24_n1641), .D(mult_x_24_n1587), .ICI(mult_x_24_n935), .S(
mult_x_24_n921), .ICO(mult_x_24_n919), .CO(mult_x_24_n920) );
CMPR42X2TS mult_x_24_U831 ( .A(mult_x_24_n936), .B(mult_x_24_n924), .C(
mult_x_24_n933), .D(mult_x_24_n921), .ICI(mult_x_24_n929), .S(
mult_x_24_n918), .ICO(mult_x_24_n916), .CO(mult_x_24_n917) );
CMPR42X2TS mult_x_24_U828 ( .A(mult_x_24_n1532), .B(mult_x_24_n1505), .C(
mult_x_24_n925), .D(mult_x_24_n1559), .ICI(mult_x_24_n919), .S(
mult_x_24_n911), .ICO(mult_x_24_n909), .CO(mult_x_24_n910) );
CMPR42X2TS mult_x_24_U826 ( .A(mult_x_24_n923), .B(mult_x_24_n911), .C(
mult_x_24_n920), .D(mult_x_24_n908), .ICI(mult_x_24_n916), .S(
mult_x_24_n905), .ICO(mult_x_24_n903), .CO(mult_x_24_n904) );
CMPR42X2TS mult_x_24_U825 ( .A(mult_x_24_n1109), .B(mult_x_24_n1423), .C(
mult_x_24_n914), .D(mult_x_24_n1450), .ICI(mult_x_24_n1477), .S(
mult_x_24_n902), .ICO(mult_x_24_n900), .CO(mult_x_24_n901) );
CMPR42X2TS mult_x_24_U822 ( .A(mult_x_24_n910), .B(mult_x_24_n899), .C(
mult_x_24_n907), .D(mult_x_24_n896), .ICI(mult_x_24_n903), .S(
mult_x_24_n893), .ICO(mult_x_24_n891), .CO(mult_x_24_n892) );
CMPR42X2TS mult_x_24_U821 ( .A(mult_x_24_n1108), .B(mult_x_24_n1422), .C(
mult_x_24_n900), .D(mult_x_24_n1476), .ICI(mult_x_24_n1503), .S(
mult_x_24_n890), .ICO(mult_x_24_n888), .CO(mult_x_24_n889) );
CMPR42X2TS mult_x_24_U819 ( .A(mult_x_24_n1611), .B(mult_x_24_n1557), .C(
mult_x_24_n901), .D(mult_x_24_n897), .ICI(mult_x_24_n890), .S(
mult_x_24_n884), .ICO(mult_x_24_n882), .CO(mult_x_24_n883) );
CMPR42X2TS mult_x_24_U815 ( .A(mult_x_24_n1610), .B(mult_x_24_n1556), .C(
mult_x_24_n885), .D(mult_x_24_n878), .ICI(mult_x_24_n882), .S(
mult_x_24_n872), .ICO(mult_x_24_n870), .CO(mult_x_24_n871) );
CMPR42X1TS mult_x_24_U813 ( .A(n6730), .B(mult_x_24_n1106), .C(
mult_x_24_n1420), .D(mult_x_24_n1447), .ICI(mult_x_24_n1501), .S(
mult_x_24_n866), .ICO(mult_x_24_n864), .CO(mult_x_24_n865) );
CMPR42X1TS mult_x_24_U812 ( .A(mult_x_24_n1474), .B(mult_x_24_n876), .C(
mult_x_24_n1528), .D(mult_x_24_n1582), .ICI(mult_x_24_n873), .S(
mult_x_24_n863), .ICO(mult_x_24_n861), .CO(mult_x_24_n862) );
CMPR42X2TS mult_x_24_U811 ( .A(mult_x_24_n1609), .B(mult_x_24_n1555), .C(
mult_x_24_n877), .D(mult_x_24_n870), .ICI(mult_x_24_n866), .S(
mult_x_24_n860), .ICO(mult_x_24_n858), .CO(mult_x_24_n859) );
CMPR42X2TS mult_x_24_U808 ( .A(mult_x_24_n1608), .B(mult_x_24_n1500), .C(
mult_x_24_n864), .D(mult_x_24_n1581), .ICI(mult_x_24_n865), .S(
mult_x_24_n851), .ICO(mult_x_24_n849), .CO(mult_x_24_n850) );
CMPR42X2TS mult_x_24_U807 ( .A(mult_x_24_n1554), .B(mult_x_24_n1527), .C(
mult_x_24_n861), .D(mult_x_24_n854), .ICI(mult_x_24_n858), .S(
mult_x_24_n848), .ICO(mult_x_24_n846), .CO(mult_x_24_n847) );
CMPR42X2TS mult_x_24_U805 ( .A(n1013), .B(n730), .C(mult_x_24_n1104), .D(
mult_x_24_n1418), .ICI(mult_x_24_n1472), .S(mult_x_24_n842), .ICO(
mult_x_24_n840), .CO(mult_x_24_n841) );
CMPR42X2TS mult_x_24_U803 ( .A(mult_x_24_n1553), .B(mult_x_24_n852), .C(
mult_x_24_n842), .D(mult_x_24_n853), .ICI(mult_x_24_n846), .S(
mult_x_24_n836), .ICO(mult_x_24_n834), .CO(mult_x_24_n835) );
CMPR42X2TS mult_x_24_U802 ( .A(mult_x_24_n850), .B(mult_x_24_n839), .C(
mult_x_24_n847), .D(mult_x_24_n836), .ICI(mult_x_24_n843), .S(
mult_x_24_n833), .ICO(mult_x_24_n831), .CO(mult_x_24_n832) );
CMPR42X2TS mult_x_24_U799 ( .A(mult_x_24_n1471), .B(mult_x_24_n1444), .C(
mult_x_24_n1498), .D(mult_x_24_n1552), .ICI(mult_x_24_n837), .S(
mult_x_24_n827), .ICO(mult_x_24_n825), .CO(mult_x_24_n826) );
CMPR42X2TS mult_x_24_U798 ( .A(mult_x_24_n1579), .B(mult_x_24_n1525), .C(
mult_x_24_n829), .D(mult_x_24_n841), .ICI(mult_x_24_n834), .S(
mult_x_24_n824), .ICO(mult_x_24_n822), .CO(mult_x_24_n823) );
CMPR42X2TS mult_x_24_U797 ( .A(mult_x_24_n827), .B(mult_x_24_n838), .C(
mult_x_24_n824), .D(mult_x_24_n835), .ICI(mult_x_24_n831), .S(
mult_x_24_n821), .ICO(mult_x_24_n819), .CO(mult_x_24_n820) );
CMPR42X2TS mult_x_24_U794 ( .A(mult_x_24_n1443), .B(mult_x_24_n1578), .C(
mult_x_24_n1470), .D(mult_x_24_n828), .ICI(mult_x_24_n825), .S(
mult_x_24_n815), .ICO(mult_x_24_n813), .CO(mult_x_24_n814) );
CMPR42X2TS mult_x_24_U793 ( .A(mult_x_24_n1551), .B(mult_x_24_n1497), .C(
mult_x_24_n1524), .D(mult_x_24_n817), .ICI(mult_x_24_n822), .S(
mult_x_24_n812), .ICO(mult_x_24_n810), .CO(mult_x_24_n811) );
CMPR42X2TS mult_x_24_U792 ( .A(mult_x_24_n826), .B(mult_x_24_n815), .C(
mult_x_24_n812), .D(mult_x_24_n823), .ICI(mult_x_24_n819), .S(
mult_x_24_n809), .ICO(mult_x_24_n807), .CO(mult_x_24_n808) );
CMPR42X2TS mult_x_24_U790 ( .A(mult_x_24_n806), .B(mult_x_24_n1415), .C(
mult_x_24_n1442), .D(mult_x_24_n816), .ICI(mult_x_24_n1496), .S(
mult_x_24_n804), .ICO(mult_x_24_n802), .CO(mult_x_24_n803) );
CMPR42X2TS mult_x_24_U789 ( .A(mult_x_24_n1550), .B(mult_x_24_n1469), .C(
mult_x_24_n1523), .D(mult_x_24_n813), .ICI(mult_x_24_n810), .S(
mult_x_24_n801), .ICO(mult_x_24_n799), .CO(mult_x_24_n800) );
CMPR42X2TS mult_x_24_U788 ( .A(mult_x_24_n814), .B(mult_x_24_n804), .C(
mult_x_24_n811), .D(mult_x_24_n801), .ICI(mult_x_24_n807), .S(
mult_x_24_n798), .ICO(mult_x_24_n796), .CO(mult_x_24_n797) );
CMPR42X2TS mult_x_24_U785 ( .A(mult_x_24_n1549), .B(mult_x_24_n1468), .C(
mult_x_24_n1522), .D(mult_x_24_n802), .ICI(mult_x_24_n803), .S(
mult_x_24_n791), .ICO(mult_x_24_n789), .CO(mult_x_24_n790) );
CMPR42X2TS mult_x_24_U784 ( .A(mult_x_24_n799), .B(mult_x_24_n794), .C(
mult_x_24_n800), .D(mult_x_24_n791), .ICI(mult_x_24_n796), .S(
mult_x_24_n788), .ICO(mult_x_24_n786), .CO(mult_x_24_n787) );
CMPR42X2TS mult_x_24_U782 ( .A(mult_x_24_n1099), .B(mult_x_24_n795), .C(
mult_x_24_n1413), .D(mult_x_24_n1548), .ICI(mult_x_24_n1440), .S(
mult_x_24_n784), .ICO(mult_x_24_n782), .CO(mult_x_24_n783) );
CMPR42X2TS mult_x_24_U781 ( .A(mult_x_24_n1521), .B(mult_x_24_n1494), .C(
mult_x_24_n1467), .D(mult_x_24_n792), .ICI(mult_x_24_n784), .S(
mult_x_24_n781), .ICO(mult_x_24_n779), .CO(mult_x_24_n780) );
CMPR42X2TS mult_x_24_U780 ( .A(mult_x_24_n789), .B(mult_x_24_n793), .C(
mult_x_24_n790), .D(mult_x_24_n781), .ICI(mult_x_24_n786), .S(
mult_x_24_n778), .ICO(mult_x_24_n776), .CO(mult_x_24_n777) );
CMPR42X2TS mult_x_24_U779 ( .A(n735), .B(mult_x_24_n1100), .C(
mult_x_24_n1098), .D(mult_x_24_n1412), .ICI(mult_x_24_n1466), .S(
mult_x_24_n775), .ICO(mult_x_24_n773), .CO(mult_x_24_n774) );
CMPR42X2TS mult_x_24_U778 ( .A(mult_x_24_n1520), .B(mult_x_24_n1493), .C(
mult_x_24_n1439), .D(mult_x_24_n782), .ICI(mult_x_24_n775), .S(
mult_x_24_n772), .ICO(mult_x_24_n770), .CO(mult_x_24_n771) );
CMPR42X2TS mult_x_24_U777 ( .A(mult_x_24_n779), .B(mult_x_24_n783), .C(
mult_x_24_n780), .D(mult_x_24_n772), .ICI(mult_x_24_n776), .S(
mult_x_24_n769), .ICO(mult_x_24_n767), .CO(mult_x_24_n768) );
CMPR42X2TS mult_x_24_U773 ( .A(mult_x_24_n1438), .B(mult_x_24_n770), .C(
mult_x_24_n771), .D(mult_x_24_n763), .ICI(mult_x_24_n767), .S(
mult_x_24_n760), .ICO(mult_x_24_n758), .CO(mult_x_24_n759) );
CMPR42X2TS mult_x_24_U770 ( .A(mult_x_24_n1410), .B(mult_x_24_n764), .C(
mult_x_24_n1491), .D(mult_x_24_n1437), .ICI(mult_x_24_n761), .S(
mult_x_24_n754), .ICO(mult_x_24_n752), .CO(mult_x_24_n753) );
CMPR42X2TS mult_x_24_U769 ( .A(mult_x_24_n1464), .B(mult_x_24_n756), .C(
mult_x_24_n762), .D(mult_x_24_n754), .ICI(mult_x_24_n758), .S(
mult_x_24_n751), .ICO(mult_x_24_n749), .CO(mult_x_24_n750) );
CMPR42X1TS mult_x_24_U745 ( .A(n769), .B(mult_x_24_n1088), .C(
mult_x_24_n1086), .D(mult_x_24_n1400), .ICI(mult_x_24_n696), .S(
mult_x_24_n695), .ICO(mult_x_24_n693), .CO(mult_x_24_n694) );
CMPR42X2TS mult_x_23_U802 ( .A(mult_x_23_n950), .B(mult_x_23_n1428), .C(
mult_x_23_n951), .D(mult_x_23_n1480), .ICI(mult_x_23_n1454), .S(
mult_x_23_n948), .ICO(mult_x_23_n946), .CO(mult_x_23_n947) );
CMPR42X2TS mult_x_23_U800 ( .A(mult_x_23_n945), .B(mult_x_23_n1453), .C(
mult_x_23_n1427), .D(mult_x_23_n946), .ICI(mult_x_23_n1479), .S(
mult_x_23_n943), .ICO(mult_x_23_n941), .CO(mult_x_23_n942) );
CMPR42X2TS mult_x_23_U794 ( .A(mult_x_23_n1451), .B(mult_x_23_n1425), .C(
mult_x_23_n931), .D(mult_x_23_n934), .ICI(mult_x_23_n1477), .S(
mult_x_23_n929), .ICO(mult_x_23_n927), .CO(mult_x_23_n928) );
CMPR42X2TS mult_x_23_U791 ( .A(mult_x_23_n1476), .B(mult_x_23_n930), .C(
mult_x_23_n924), .D(mult_x_23_n1450), .ICI(mult_x_23_n927), .S(
mult_x_23_n922), .ICO(mult_x_23_n920), .CO(mult_x_23_n921) );
CMPR42X2TS mult_x_23_U789 ( .A(mult_x_23_n919), .B(mult_x_23_n1371), .C(
mult_x_23_n925), .D(mult_x_23_n1397), .ICI(mult_x_23_n1449), .S(
mult_x_23_n917), .ICO(mult_x_23_n915), .CO(mult_x_23_n916) );
CMPR42X2TS mult_x_23_U788 ( .A(mult_x_23_n1423), .B(mult_x_23_n923), .C(
mult_x_23_n1475), .D(mult_x_23_n920), .ICI(mult_x_23_n917), .S(
mult_x_23_n914), .ICO(mult_x_23_n912), .CO(mult_x_23_n913) );
CMPR42X1TS mult_x_23_U786 ( .A(mult_x_23_n911), .B(mult_x_23_n1370), .C(
mult_x_23_n915), .D(mult_x_23_n1422), .ICI(mult_x_23_n1474), .S(
mult_x_23_n909), .ICO(mult_x_23_n907), .CO(mult_x_23_n908) );
CMPR42X1TS mult_x_23_U783 ( .A(mult_x_23_n903), .B(mult_x_23_n1395), .C(
mult_x_23_n1369), .D(mult_x_23_n1447), .ICI(mult_x_23_n907), .S(
mult_x_23_n901), .ICO(mult_x_23_n899), .CO(mult_x_23_n900) );
CMPR42X2TS mult_x_23_U782 ( .A(mult_x_23_n1421), .B(mult_x_23_n1473), .C(
mult_x_23_n908), .D(mult_x_23_n904), .ICI(mult_x_23_n901), .S(
mult_x_23_n898), .ICO(mult_x_23_n896), .CO(mult_x_23_n897) );
CMPR42X2TS mult_x_23_U779 ( .A(mult_x_23_n1368), .B(mult_x_23_n893), .C(
mult_x_23_n1420), .D(mult_x_23_n1394), .ICI(mult_x_23_n1446), .S(
mult_x_23_n891), .ICO(mult_x_23_n889), .CO(mult_x_23_n890) );
CMPR42X2TS mult_x_23_U778 ( .A(mult_x_23_n899), .B(mult_x_23_n1472), .C(
mult_x_23_n900), .D(mult_x_23_n891), .ICI(mult_x_23_n896), .S(
mult_x_23_n888), .ICO(mult_x_23_n886), .CO(mult_x_23_n887) );
CMPR42X2TS mult_x_23_U775 ( .A(mult_x_23_n1393), .B(mult_x_23_n1367), .C(
mult_x_23_n1445), .D(mult_x_23_n883), .ICI(mult_x_23_n1419), .S(
mult_x_23_n881), .ICO(mult_x_23_n879), .CO(mult_x_23_n880) );
CMPR42X2TS mult_x_23_U774 ( .A(mult_x_23_n889), .B(mult_x_23_n1471), .C(
mult_x_23_n890), .D(mult_x_23_n881), .ICI(mult_x_23_n886), .S(
mult_x_23_n878), .ICO(mult_x_23_n876), .CO(mult_x_23_n877) );
CMPR42X2TS mult_x_23_U771 ( .A(mult_x_23_n1418), .B(mult_x_23_n882), .C(
mult_x_23_n1470), .D(mult_x_23_n873), .ICI(mult_x_23_n1444), .S(
mult_x_23_n871), .ICO(mult_x_23_n869), .CO(mult_x_23_n870) );
CMPR42X2TS mult_x_23_U770 ( .A(mult_x_23_n879), .B(mult_x_23_n1392), .C(
mult_x_23_n880), .D(mult_x_23_n871), .ICI(mult_x_23_n876), .S(
mult_x_23_n868), .ICO(mult_x_23_n866), .CO(mult_x_23_n867) );
CMPR42X2TS mult_x_23_U768 ( .A(mult_x_23_n865), .B(mult_x_23_n1313), .C(
mult_x_23_n874), .D(mult_x_23_n1339), .ICI(mult_x_23_n1365), .S(
mult_x_23_n863), .ICO(mult_x_23_n861), .CO(mult_x_23_n862) );
CMPR42X2TS mult_x_23_U767 ( .A(mult_x_23_n1391), .B(mult_x_23_n872), .C(
mult_x_23_n1443), .D(mult_x_23_n1417), .ICI(mult_x_23_n869), .S(
mult_x_23_n860), .ICO(mult_x_23_n858), .CO(mult_x_23_n859) );
CMPR42X2TS mult_x_23_U766 ( .A(mult_x_23_n1469), .B(mult_x_23_n863), .C(
mult_x_23_n870), .D(mult_x_23_n860), .ICI(mult_x_23_n866), .S(
mult_x_23_n857), .ICO(mult_x_23_n855), .CO(mult_x_23_n856) );
CMPR42X2TS mult_x_23_U764 ( .A(mult_x_23_n854), .B(mult_x_23_n1312), .C(
mult_x_23_n861), .D(mult_x_23_n1364), .ICI(mult_x_23_n1338), .S(
mult_x_23_n852), .ICO(mult_x_23_n850), .CO(mult_x_23_n851) );
CMPR42X2TS mult_x_23_U763 ( .A(mult_x_23_n1416), .B(mult_x_23_n1468), .C(
mult_x_23_n1390), .D(mult_x_23_n862), .ICI(mult_x_23_n858), .S(
mult_x_23_n849), .ICO(mult_x_23_n847), .CO(mult_x_23_n848) );
CMPR42X1TS mult_x_23_U760 ( .A(mult_x_23_n843), .B(mult_x_23_n1337), .C(
mult_x_23_n1311), .D(mult_x_23_n1389), .ICI(mult_x_23_n850), .S(
mult_x_23_n841), .ICO(mult_x_23_n839), .CO(mult_x_23_n840) );
CMPR42X2TS mult_x_23_U759 ( .A(mult_x_23_n1441), .B(mult_x_23_n1363), .C(
mult_x_23_n1415), .D(mult_x_23_n851), .ICI(mult_x_23_n841), .S(
mult_x_23_n838), .ICO(mult_x_23_n836), .CO(mult_x_23_n837) );
CMPR42X2TS mult_x_23_U758 ( .A(mult_x_23_n1467), .B(mult_x_23_n847), .C(
mult_x_23_n848), .D(mult_x_23_n844), .ICI(mult_x_23_n838), .S(
mult_x_23_n835), .ICO(mult_x_23_n833), .CO(mult_x_23_n834) );
CMPR42X2TS mult_x_23_U750 ( .A(mult_x_23_n1413), .B(mult_x_23_n819), .C(
mult_x_23_n826), .D(mult_x_23_n816), .ICI(mult_x_23_n822), .S(
mult_x_23_n813), .ICO(mult_x_23_n811), .CO(mult_x_23_n812) );
CMPR42X2TS mult_x_23_U746 ( .A(mult_x_23_n818), .B(mult_x_23_n808), .C(
mult_x_23_n815), .D(mult_x_23_n805), .ICI(mult_x_23_n811), .S(
mult_x_23_n802), .ICO(mult_x_23_n800), .CO(mult_x_23_n801) );
CMPR42X1TS mult_x_23_U743 ( .A(mult_x_23_n1385), .B(mult_x_23_n799), .C(
mult_x_23_n1359), .D(mult_x_23_n1411), .ICI(mult_x_23_n803), .S(
mult_x_23_n794), .ICO(mult_x_23_n792), .CO(mult_x_23_n793) );
CMPR42X2TS mult_x_23_U739 ( .A(mult_x_23_n788), .B(mult_x_23_n1332), .C(
mult_x_23_n1384), .D(mult_x_23_n1436), .ICI(mult_x_23_n792), .S(
mult_x_23_n783), .ICO(mult_x_23_n781), .CO(mult_x_23_n782) );
CMPR42X2TS mult_x_23_U738 ( .A(mult_x_23_n796), .B(mult_x_23_n786), .C(
mult_x_23_n793), .D(mult_x_23_n783), .ICI(mult_x_23_n789), .S(
mult_x_23_n780), .ICO(mult_x_23_n778), .CO(mult_x_23_n779) );
CMPR42X1TS mult_x_23_U736 ( .A(mult_x_23_n1331), .B(mult_x_23_n1435), .C(
mult_x_23_n777), .D(mult_x_23_n787), .ICI(mult_x_23_n784), .S(
mult_x_23_n775), .ICO(mult_x_23_n773), .CO(mult_x_23_n774) );
CMPR42X2TS mult_x_23_U734 ( .A(mult_x_23_n785), .B(mult_x_23_n775), .C(
mult_x_23_n782), .D(mult_x_23_n772), .ICI(mult_x_23_n778), .S(
mult_x_23_n769), .ICO(mult_x_23_n767), .CO(mult_x_23_n768) );
CMPR42X2TS mult_x_23_U732 ( .A(mult_x_23_n1304), .B(mult_x_23_n776), .C(
mult_x_23_n1434), .D(mult_x_23_n1408), .ICI(mult_x_23_n773), .S(
mult_x_23_n764), .ICO(mult_x_23_n762), .CO(mult_x_23_n763) );
CMPR42X2TS mult_x_23_U730 ( .A(mult_x_23_n774), .B(mult_x_23_n764), .C(
mult_x_23_n771), .D(mult_x_23_n761), .ICI(mult_x_23_n767), .S(
mult_x_23_n758), .ICO(mult_x_23_n756), .CO(mult_x_23_n757) );
CMPR42X2TS mult_x_23_U727 ( .A(mult_x_23_n1381), .B(mult_x_23_n1303), .C(
mult_x_23_n1355), .D(mult_x_23_n1407), .ICI(mult_x_23_n759), .S(
mult_x_23_n750), .ICO(mult_x_23_n748), .CO(mult_x_23_n749) );
CMPR42X2TS mult_x_23_U723 ( .A(mult_x_23_n751), .B(mult_x_23_n1276), .C(
mult_x_23_n1328), .D(mult_x_23_n1380), .ICI(mult_x_23_n748), .S(
mult_x_23_n740), .ICO(mult_x_23_n738), .CO(mult_x_23_n739) );
CMPR42X2TS mult_x_23_U722 ( .A(mult_x_23_n743), .B(mult_x_23_n752), .C(
mult_x_23_n749), .D(mult_x_23_n740), .ICI(mult_x_23_n745), .S(
mult_x_23_n737), .ICO(mult_x_23_n735), .CO(mult_x_23_n736) );
CMPR42X1TS mult_x_23_U720 ( .A(mult_x_23_n744), .B(mult_x_23_n1251), .C(
mult_x_23_n1275), .D(mult_x_23_n1405), .ICI(mult_x_23_n1379), .S(
mult_x_23_n732), .ICO(mult_x_23_n730), .CO(mult_x_23_n731) );
CMPR42X2TS mult_x_23_U718 ( .A(mult_x_23_n738), .B(mult_x_23_n732), .C(
mult_x_23_n739), .D(mult_x_23_n729), .ICI(mult_x_23_n735), .S(
mult_x_23_n726), .ICO(mult_x_23_n724), .CO(mult_x_23_n725) );
CMPR42X2TS mult_x_23_U712 ( .A(mult_x_23_n1377), .B(mult_x_23_n1325), .C(
mult_x_23_n1299), .D(mult_x_23_n713), .ICI(mult_x_23_n1351), .S(
mult_x_23_n711), .ICO(mult_x_23_n709), .CO(mult_x_23_n710) );
CMPR42X2TS mult_x_23_U708 ( .A(mult_x_23_n1298), .B(mult_x_23_n1350), .C(
mult_x_23_n1272), .D(mult_x_23_n712), .ICI(mult_x_23_n709), .S(
mult_x_23_n701), .ICO(mult_x_23_n699), .CO(mult_x_23_n700) );
CMPR42X2TS mult_x_23_U707 ( .A(mult_x_23_n703), .B(mult_x_23_n1324), .C(
mult_x_23_n710), .D(mult_x_23_n701), .ICI(mult_x_23_n706), .S(
mult_x_23_n698), .ICO(mult_x_23_n696), .CO(mult_x_23_n697) );
CMPR42X2TS mult_x_23_U705 ( .A(mult_x_23_n1248), .B(mult_x_23_n1323), .C(
mult_x_23_n695), .D(mult_x_23_n702), .ICI(mult_x_23_n699), .S(
mult_x_23_n693), .ICO(mult_x_23_n691), .CO(mult_x_23_n692) );
CMPR42X2TS mult_x_23_U704 ( .A(mult_x_23_n1349), .B(mult_x_23_n1297), .C(
mult_x_23_n700), .D(mult_x_23_n693), .ICI(mult_x_23_n696), .S(
mult_x_23_n690), .ICO(mult_x_23_n688), .CO(mult_x_23_n689) );
CMPR42X2TS mult_x_23_U696 ( .A(mult_x_23_n1320), .B(mult_x_23_n1268), .C(
mult_x_23_n677), .D(mult_x_23_n672), .ICI(mult_x_23_n673), .S(
mult_x_23_n670), .ICO(mult_x_23_n668), .CO(mult_x_23_n669) );
CMPR42X2TS mult_x_23_U693 ( .A(mult_x_23_n1267), .B(mult_x_23_n665), .C(
mult_x_23_n1293), .D(mult_x_23_n671), .ICI(mult_x_23_n668), .S(
mult_x_23_n663), .ICO(mult_x_23_n661), .CO(mult_x_23_n662) );
CMPR42X2TS mult_x_23_U686 ( .A(mult_x_23_n648), .B(mult_x_23_n1290), .C(
mult_x_23_n652), .D(mult_x_23_n1264), .ICI(mult_x_23_n649), .S(
mult_x_23_n647), .ICO(mult_x_23_n645), .CO(mult_x_23_n646) );
CMPR42X2TS mult_x_23_U702 ( .A(mult_x_23_n687), .B(mult_x_23_n1348), .C(
mult_x_23_n1296), .D(mult_x_23_n694), .ICI(mult_x_23_n1270), .S(
mult_x_23_n686), .ICO(mult_x_23_n684), .CO(mult_x_23_n685) );
CMPR42X2TS mult_x_23_U748 ( .A(mult_x_23_n1360), .B(mult_x_23_n820), .C(
mult_x_23_n1464), .D(mult_x_23_n1412), .ICI(mult_x_23_n1386), .S(
mult_x_23_n808), .ICO(mult_x_23_n806), .CO(mult_x_23_n807) );
CMPR42X2TS mult_x_24_U755 ( .A(mult_x_24_n1432), .B(mult_x_24_n1405), .C(
mult_x_24_n719), .D(mult_x_24_n725), .ICI(mult_x_24_n721), .S(
mult_x_24_n717), .ICO(mult_x_24_n715), .CO(mult_x_24_n716) );
CMPR42X2TS mult_x_23_U726 ( .A(mult_x_23_n763), .B(mult_x_23_n753), .C(
mult_x_23_n760), .D(mult_x_23_n750), .ICI(mult_x_23_n756), .S(
mult_x_23_n747), .ICO(mult_x_23_n745), .CO(mult_x_23_n746) );
CMPR42X2TS mult_x_23_U752 ( .A(mult_x_23_n1335), .B(mult_x_23_n1309), .C(
mult_x_23_n1387), .D(mult_x_23_n821), .ICI(mult_x_23_n825), .S(
mult_x_23_n819), .ICO(mult_x_23_n817), .CO(mult_x_23_n818) );
CMPR42X2TS mult_x_23_U762 ( .A(mult_x_23_n1442), .B(mult_x_23_n852), .C(
mult_x_23_n859), .D(mult_x_23_n855), .ICI(mult_x_23_n849), .S(
mult_x_23_n846), .ICO(mult_x_23_n844), .CO(mult_x_23_n845) );
CMPR42X2TS mult_x_23_U683 ( .A(n1015), .B(mult_x_23_n643), .C(
mult_x_23_n1242), .D(mult_x_23_n640), .ICI(mult_x_23_n1262), .S(
mult_x_23_n639), .ICO(mult_x_23_n637), .CO(mult_x_23_n638) );
CMPR42X2TS mult_x_23_U719 ( .A(mult_x_23_n1327), .B(mult_x_23_n741), .C(
mult_x_23_n1301), .D(mult_x_23_n1353), .ICI(mult_x_23_n742), .S(
mult_x_23_n729), .ICO(mult_x_23_n727), .CO(mult_x_23_n728) );
CMPR42X2TS mult_x_24_U814 ( .A(mult_x_24_n886), .B(mult_x_24_n875), .C(
mult_x_24_n883), .D(mult_x_24_n879), .ICI(mult_x_24_n872), .S(
mult_x_24_n869), .ICO(mult_x_24_n867), .CO(mult_x_24_n868) );
CMPR42X2TS mult_x_23_U754 ( .A(mult_x_23_n836), .B(mult_x_23_n830), .C(
mult_x_23_n837), .D(mult_x_23_n833), .ICI(mult_x_23_n827), .S(
mult_x_23_n824), .ICO(mult_x_23_n822), .CO(mult_x_23_n823) );
CMPR42X2TS mult_x_24_U820 ( .A(mult_x_24_n1449), .B(mult_x_24_n1638), .C(
mult_x_24_n1530), .D(mult_x_24_n1584), .ICI(mult_x_24_n894), .S(
mult_x_24_n887), .ICO(mult_x_24_n885), .CO(mult_x_24_n886) );
CMPR42X2TS mult_x_24_U810 ( .A(mult_x_24_n874), .B(mult_x_24_n863), .C(
mult_x_24_n871), .D(mult_x_24_n860), .ICI(mult_x_24_n867), .S(
mult_x_24_n857), .ICO(mult_x_24_n855), .CO(mult_x_24_n856) );
CMPR42X2TS mult_x_24_U806 ( .A(mult_x_24_n862), .B(mult_x_24_n851), .C(
mult_x_24_n859), .D(mult_x_24_n848), .ICI(mult_x_24_n855), .S(
mult_x_24_n845), .ICO(mult_x_24_n843), .CO(mult_x_24_n844) );
CMPR42X2TS mult_x_24_U827 ( .A(mult_x_24_n1640), .B(mult_x_24_n1586), .C(
mult_x_24_n1613), .D(mult_x_24_n913), .ICI(mult_x_24_n922), .S(
mult_x_24_n908), .ICO(mult_x_24_n906), .CO(mult_x_24_n907) );
CMPR42X2TS mult_x_23_U785 ( .A(mult_x_23_n1396), .B(mult_x_23_n1448), .C(
mult_x_23_n916), .D(mult_x_23_n912), .ICI(mult_x_23_n909), .S(
mult_x_23_n906), .ICO(mult_x_23_n904), .CO(mult_x_23_n905) );
CMPR42X2TS mult_x_23_U731 ( .A(mult_x_23_n1356), .B(mult_x_23_n766), .C(
mult_x_23_n1330), .D(mult_x_23_n1382), .ICI(mult_x_23_n770), .S(
mult_x_23_n761), .ICO(mult_x_23_n759), .CO(mult_x_23_n760) );
CMPR42X2TS mult_x_23_U711 ( .A(mult_x_23_n722), .B(mult_x_23_n719), .C(
mult_x_23_n711), .D(mult_x_23_n720), .ICI(mult_x_23_n716), .S(
mult_x_23_n708), .ICO(mult_x_23_n706), .CO(mult_x_23_n707) );
CMPR42X2TS mult_x_24_U750 ( .A(mult_x_24_n708), .B(mult_x_24_n1430), .C(
mult_x_24_n1403), .D(mult_x_24_n712), .ICI(mult_x_24_n709), .S(
mult_x_24_n706), .ICO(mult_x_24_n704), .CO(mult_x_24_n705) );
CMPR42X2TS mult_x_23_U699 ( .A(mult_x_23_n687), .B(mult_x_23_n1247), .C(
mult_x_23_n1347), .D(mult_x_23_n1269), .ICI(mult_x_23_n1321), .S(
mult_x_23_n678), .ICO(mult_x_23_n676), .CO(mult_x_23_n677) );
DFFRX2TS Sel_B_Q_reg_1_ ( .D(n418), .CK(clk), .RN(n8504), .Q(
FSM_selector_B[1]), .QN(n8536) );
DFFX1TS Sgf_operation_ODD1_right_DatO_reg_0_ ( .D(
Sgf_operation_ODD1_right_N0), .CK(clk), .Q(Sgf_operation_Result[0]),
.QN(DP_OP_168J42_122_1342_n587) );
DFFX1TS Sgf_operation_ODD1_left_DatO_reg_22_ ( .D(
Sgf_operation_ODD1_left_N22), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[22]), .QN(DP_OP_168J42_122_1342_n617) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_32_ ( .D(
Sgf_operation_ODD1_middle_N32), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[32]) );
DFFRX1TS FS_Module_state_reg_reg_1_ ( .D(n712), .CK(clk), .RN(n8497), .Q(
FS_Module_state_reg[1]), .QN(n1036) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n357), .CK(clk),
.RN(n8511), .Q(Sgf_normalized_result[4]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n355), .CK(clk),
.RN(n8511), .Q(Sgf_normalized_result[2]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n358), .CK(clk),
.RN(n8511), .Q(Sgf_normalized_result[5]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_42_ ( .D(n395), .CK(clk),
.RN(n8507), .Q(Sgf_normalized_result[42]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_44_ ( .D(n397), .CK(clk),
.RN(n8507), .Q(Sgf_normalized_result[44]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_46_ ( .D(n399), .CK(clk),
.RN(n8506), .Q(Sgf_normalized_result[46]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_48_ ( .D(n401), .CK(clk),
.RN(n8505), .Q(Sgf_normalized_result[48]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_50_ ( .D(n403), .CK(clk),
.RN(n8506), .Q(Sgf_normalized_result[50]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_43_ ( .D(n396), .CK(clk),
.RN(n8507), .Q(Sgf_normalized_result[43]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_45_ ( .D(n398), .CK(clk),
.RN(n8507), .Q(Sgf_normalized_result[45]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_47_ ( .D(n400), .CK(clk),
.RN(n8535), .Q(Sgf_normalized_result[47]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_49_ ( .D(n402), .CK(clk),
.RN(n8535), .Q(Sgf_normalized_result[49]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_51_ ( .D(n404), .CK(clk),
.RN(n8535), .Q(Sgf_normalized_result[51]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_105_ ( .D(n420), .CK(clk), .RN(
n8497), .Q(P_Sgf[105]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_57_ ( .D(n703), .CK(clk), .RN(
n8503), .Q(Op_MX[57]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_61_ ( .D(n707), .CK(clk), .RN(
n8518), .Q(Op_MX[61]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n575), .CK(clk), .RN(n8529),
.Q(Add_result[4]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n572), .CK(clk), .RN(n8529),
.Q(Add_result[7]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n571), .CK(clk), .RN(n8529),
.Q(Add_result[8]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n570), .CK(clk), .RN(n8529),
.Q(Add_result[9]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n569), .CK(clk), .RN(n8528),
.Q(Add_result[10]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n568), .CK(clk), .RN(n8528),
.Q(Add_result[11]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n567), .CK(clk), .RN(n8528),
.Q(Add_result[12]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n566), .CK(clk), .RN(n8528),
.Q(Add_result[13]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n565), .CK(clk), .RN(n8528),
.Q(Add_result[14]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n564), .CK(clk), .RN(n8528),
.Q(Add_result[15]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n563), .CK(clk), .RN(n8528),
.Q(Add_result[16]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n562), .CK(clk), .RN(n8528),
.Q(Add_result[17]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n561), .CK(clk), .RN(n8528),
.Q(Add_result[18]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n560), .CK(clk), .RN(n8528),
.Q(Add_result[19]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n559), .CK(clk), .RN(n8527),
.Q(Add_result[20]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n558), .CK(clk), .RN(n8527),
.Q(Add_result[21]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n557), .CK(clk), .RN(n8527),
.Q(Add_result[22]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n556), .CK(clk), .RN(n8527),
.Q(Add_result[23]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_24_ ( .D(n555), .CK(clk), .RN(n8527),
.Q(Add_result[24]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_25_ ( .D(n554), .CK(clk), .RN(n8527),
.Q(Add_result[25]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_26_ ( .D(n553), .CK(clk), .RN(n8527),
.Q(Add_result[26]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_27_ ( .D(n552), .CK(clk), .RN(n8527),
.Q(Add_result[27]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_28_ ( .D(n551), .CK(clk), .RN(n8527),
.Q(Add_result[28]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_39_ ( .D(n540), .CK(clk), .RN(n8525),
.Q(Add_result[39]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_40_ ( .D(n539), .CK(clk), .RN(n8525),
.Q(Add_result[40]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_41_ ( .D(n538), .CK(clk), .RN(n8525),
.Q(Add_result[41]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_42_ ( .D(n537), .CK(clk), .RN(n8525),
.Q(Add_result[42]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_62_ ( .D(n708), .CK(clk), .RN(
n8518), .Q(Op_MX[62]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_52_ ( .D(n698), .CK(clk), .RN(
n8519), .Q(Op_MX[52]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_57_ ( .D(n639), .CK(clk), .RN(
n8530), .Q(Op_MY[57]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_61_ ( .D(n643), .CK(clk), .RN(
n8530), .Q(Op_MY[61]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_104_ ( .D(n520), .CK(clk), .RN(
n8502), .Q(P_Sgf[104]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_91_ ( .D(n512), .CK(clk), .RN(
n8501), .Q(P_Sgf[91]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_62_ ( .D(n644), .CK(clk), .RN(
n8530), .Q(Op_MY[62]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_53_ ( .D(n635), .CK(clk), .RN(
n8531), .Q(Op_MY[53]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_53_ ( .D(n474), .CK(clk), .RN(
n8497), .Q(P_Sgf[53]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_55_ ( .D(n476), .CK(clk), .RN(
n8497), .Q(P_Sgf[55]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_58_ ( .D(n479), .CK(clk), .RN(
n8498), .Q(P_Sgf[58]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_59_ ( .D(n480), .CK(clk), .RN(
n8498), .Q(P_Sgf[59]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_60_ ( .D(n481), .CK(clk), .RN(
n8498), .Q(P_Sgf[60]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_61_ ( .D(n482), .CK(clk), .RN(
n8498), .Q(P_Sgf[61]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_62_ ( .D(n483), .CK(clk), .RN(
n8498), .Q(P_Sgf[62]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_63_ ( .D(n484), .CK(clk), .RN(
n8498), .Q(P_Sgf[63]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_64_ ( .D(n485), .CK(clk), .RN(
n8498), .Q(P_Sgf[64]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_65_ ( .D(n486), .CK(clk), .RN(
n8498), .Q(P_Sgf[65]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_66_ ( .D(n487), .CK(clk), .RN(
n8499), .Q(P_Sgf[66]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_67_ ( .D(n488), .CK(clk), .RN(
n8499), .Q(P_Sgf[67]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_68_ ( .D(n489), .CK(clk), .RN(
n8499), .Q(P_Sgf[68]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_69_ ( .D(n490), .CK(clk), .RN(
n8499), .Q(P_Sgf[69]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_70_ ( .D(n491), .CK(clk), .RN(
n8499), .Q(P_Sgf[70]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_71_ ( .D(n492), .CK(clk), .RN(
n8499), .Q(P_Sgf[71]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_72_ ( .D(n493), .CK(clk), .RN(
n8499), .Q(P_Sgf[72]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_73_ ( .D(n494), .CK(clk), .RN(
n8499), .Q(P_Sgf[73]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_74_ ( .D(n495), .CK(clk), .RN(
n8499), .Q(P_Sgf[74]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_75_ ( .D(n496), .CK(clk), .RN(
n8499), .Q(P_Sgf[75]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_76_ ( .D(n497), .CK(clk), .RN(
n8500), .Q(P_Sgf[76]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_77_ ( .D(n498), .CK(clk), .RN(
n8500), .Q(P_Sgf[77]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_78_ ( .D(n499), .CK(clk), .RN(
n8500), .Q(P_Sgf[78]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_79_ ( .D(n500), .CK(clk), .RN(
n8500), .Q(P_Sgf[79]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_80_ ( .D(n501), .CK(clk), .RN(
n8500), .Q(P_Sgf[80]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_81_ ( .D(n502), .CK(clk), .RN(
n8500), .Q(P_Sgf[81]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_82_ ( .D(n503), .CK(clk), .RN(
n8500), .Q(P_Sgf[82]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_83_ ( .D(n504), .CK(clk), .RN(
n8500), .Q(P_Sgf[83]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_84_ ( .D(n505), .CK(clk), .RN(
n8500), .Q(P_Sgf[84]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_85_ ( .D(n506), .CK(clk), .RN(
n8500), .Q(P_Sgf[85]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_86_ ( .D(n507), .CK(clk), .RN(
n8501), .Q(P_Sgf[86]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_87_ ( .D(n508), .CK(clk), .RN(
n8501), .Q(P_Sgf[87]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_88_ ( .D(n509), .CK(clk), .RN(
n8501), .Q(P_Sgf[88]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_89_ ( .D(n510), .CK(clk), .RN(
n8501), .Q(P_Sgf[89]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_90_ ( .D(n511), .CK(clk), .RN(
n8501), .Q(P_Sgf[90]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_92_ ( .D(n513), .CK(clk), .RN(
n8501), .Q(P_Sgf[92]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_93_ ( .D(n514), .CK(clk), .RN(
n8501), .Q(P_Sgf[93]) );
DFFRX1TS Exp_module_Underflow_m_Q_reg_0_ ( .D(n352), .CK(clk), .RN(n8511),
.Q(underflow_flag), .QN(n8491) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_52_ ( .D(n580), .CK(clk),
.RN(n8535), .Q(Sgf_normalized_result[52]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_0_ ( .D(n421), .CK(clk), .RN(
n8497), .Q(P_Sgf[0]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_4_ ( .D(n425), .CK(clk), .RN(
n8496), .Q(P_Sgf[4]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_8_ ( .D(n429), .CK(clk), .RN(
n8496), .Q(P_Sgf[8]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_12_ ( .D(n433), .CK(clk), .RN(
n8495), .Q(P_Sgf[12]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_16_ ( .D(n437), .CK(clk), .RN(
n8495), .Q(P_Sgf[16]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_20_ ( .D(n441), .CK(clk), .RN(
n8495), .Q(P_Sgf[20]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_24_ ( .D(n445), .CK(clk), .RN(
n8494), .Q(P_Sgf[24]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_28_ ( .D(n449), .CK(clk), .RN(
n8494), .Q(P_Sgf[28]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_32_ ( .D(n453), .CK(clk), .RN(
n8493), .Q(P_Sgf[32]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_36_ ( .D(n457), .CK(clk), .RN(
n8493), .Q(P_Sgf[36]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_51_ ( .D(n472), .CK(clk), .RN(
n8492), .Q(P_Sgf[51]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_41_ ( .D(n462), .CK(clk), .RN(
n8492), .Q(P_Sgf[41]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_47_ ( .D(n468), .CK(clk), .RN(
n8493), .Q(P_Sgf[47]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_63_ ( .D(n645), .CK(clk), .RN(
n8524), .Q(Op_MX[63]) );
DFFRX1TS Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n526), .CK(clk), .RN(
n8530), .Q(FSM_add_overflow_flag), .QN(n8453) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_55_ ( .D(n701), .CK(clk), .RN(
n8519), .Q(Op_MX[55]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_53_ ( .D(n699), .CK(clk), .RN(
n8519), .Q(Op_MX[53]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_52_ ( .D(n527), .CK(clk), .RN(n8530),
.Q(Add_result[52]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n353), .CK(clk),
.RN(n8511), .Q(Sgf_normalized_result[0]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_102_ ( .D(n524), .CK(clk), .RN(
n8502), .Q(P_Sgf[102]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_48_ ( .D(n469), .CK(clk), .RN(
n8492), .Q(P_Sgf[48]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_38_ ( .D(n459), .CK(clk), .RN(
n8493), .Q(P_Sgf[38]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_34_ ( .D(n455), .CK(clk), .RN(
n8493), .Q(P_Sgf[34]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_30_ ( .D(n451), .CK(clk), .RN(
n8494), .Q(P_Sgf[30]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_26_ ( .D(n447), .CK(clk), .RN(
n8494), .Q(P_Sgf[26]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_22_ ( .D(n443), .CK(clk), .RN(
n8494), .Q(P_Sgf[22]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_18_ ( .D(n439), .CK(clk), .RN(
n8495), .Q(P_Sgf[18]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_14_ ( .D(n435), .CK(clk), .RN(
n8495), .Q(P_Sgf[14]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_10_ ( .D(n431), .CK(clk), .RN(
n8496), .Q(P_Sgf[10]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_6_ ( .D(n427), .CK(clk), .RN(
n8496), .Q(P_Sgf[6]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_2_ ( .D(n423), .CK(clk), .RN(
n8496), .Q(P_Sgf[2]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_49_ ( .D(n470), .CK(clk), .RN(
n8492), .Q(P_Sgf[49]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_37_ ( .D(n458), .CK(clk), .RN(
n8493), .Q(P_Sgf[37]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_33_ ( .D(n454), .CK(clk), .RN(
n8493), .Q(P_Sgf[33]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_29_ ( .D(n450), .CK(clk), .RN(
n8494), .Q(P_Sgf[29]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_25_ ( .D(n446), .CK(clk), .RN(
n8494), .Q(P_Sgf[25]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_21_ ( .D(n442), .CK(clk), .RN(
n8495), .Q(P_Sgf[21]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_17_ ( .D(n438), .CK(clk), .RN(
n8495), .Q(P_Sgf[17]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_13_ ( .D(n434), .CK(clk), .RN(
n8495), .Q(P_Sgf[13]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_9_ ( .D(n430), .CK(clk), .RN(
n8496), .Q(P_Sgf[9]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_5_ ( .D(n426), .CK(clk), .RN(
n8496), .Q(P_Sgf[5]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_1_ ( .D(n422), .CK(clk), .RN(
n8497), .Q(P_Sgf[1]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_50_ ( .D(n471), .CK(clk), .RN(
n8492), .Q(P_Sgf[50]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_39_ ( .D(n460), .CK(clk), .RN(
n8493), .Q(P_Sgf[39]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_35_ ( .D(n456), .CK(clk), .RN(
n8493), .Q(P_Sgf[35]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_31_ ( .D(n452), .CK(clk), .RN(
n8494), .Q(P_Sgf[31]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_27_ ( .D(n448), .CK(clk), .RN(
n8494), .Q(P_Sgf[27]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_23_ ( .D(n444), .CK(clk), .RN(
n8494), .Q(P_Sgf[23]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_19_ ( .D(n440), .CK(clk), .RN(
n8495), .Q(P_Sgf[19]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_15_ ( .D(n436), .CK(clk), .RN(
n8495), .Q(P_Sgf[15]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_11_ ( .D(n432), .CK(clk), .RN(
n8496), .Q(P_Sgf[11]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_7_ ( .D(n428), .CK(clk), .RN(
n8496), .Q(P_Sgf[7]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_3_ ( .D(n424), .CK(clk), .RN(
n8496), .Q(P_Sgf[3]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_46_ ( .D(n467), .CK(clk), .RN(
n8493), .Q(P_Sgf[46]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_43_ ( .D(n464), .CK(clk), .RN(
n8492), .Q(P_Sgf[43]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_45_ ( .D(n466), .CK(clk), .RN(
n8492), .Q(P_Sgf[45]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_42_ ( .D(n463), .CK(clk), .RN(
n8492), .Q(P_Sgf[42]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_44_ ( .D(n465), .CK(clk), .RN(
n8492), .Q(P_Sgf[44]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_40_ ( .D(n461), .CK(clk), .RN(
n8492), .Q(P_Sgf[40]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_59_ ( .D(n705), .CK(clk), .RN(
n8518), .Q(Op_MX[59]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_60_ ( .D(n706), .CK(clk), .RN(
n8518), .Q(Op_MX[60]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_56_ ( .D(n702), .CK(clk), .RN(
n8526), .Q(Op_MX[56]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_58_ ( .D(n704), .CK(clk), .RN(
n8518), .Q(Op_MX[58]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_54_ ( .D(n700), .CK(clk), .RN(
n8519), .Q(Op_MX[54]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_51_ ( .D(n528), .CK(clk), .RN(n8524),
.Q(Add_result[51]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_50_ ( .D(n529), .CK(clk), .RN(n8524),
.Q(Add_result[50]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_49_ ( .D(n530), .CK(clk), .RN(n8524),
.Q(Add_result[49]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n576), .CK(clk), .RN(n8529),
.Q(Add_result[3]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n574), .CK(clk), .RN(n8529),
.Q(Add_result[5]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n573), .CK(clk), .RN(n8529),
.Q(Add_result[6]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_29_ ( .D(n550), .CK(clk), .RN(n8527),
.Q(Add_result[29]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_30_ ( .D(n549), .CK(clk), .RN(n8526),
.Q(Add_result[30]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_31_ ( .D(n548), .CK(clk), .RN(n8526),
.Q(Add_result[31]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_32_ ( .D(n547), .CK(clk), .RN(n8526),
.Q(Add_result[32]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_33_ ( .D(n546), .CK(clk), .RN(n8526),
.Q(Add_result[33]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_48_ ( .D(n531), .CK(clk), .RN(n8525),
.Q(Add_result[48]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_47_ ( .D(n532), .CK(clk), .RN(n8525),
.Q(Add_result[47]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_46_ ( .D(n533), .CK(clk), .RN(n8525),
.Q(Add_result[46]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_45_ ( .D(n534), .CK(clk), .RN(n8525),
.Q(Add_result[45]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_44_ ( .D(n535), .CK(clk), .RN(n8525),
.Q(Add_result[44]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_43_ ( .D(n536), .CK(clk), .RN(n8525),
.Q(Add_result[43]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_38_ ( .D(n541), .CK(clk), .RN(n8526),
.Q(Add_result[38]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_37_ ( .D(n542), .CK(clk), .RN(n8526),
.Q(Add_result[37]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_36_ ( .D(n543), .CK(clk), .RN(n8526),
.Q(Add_result[36]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_35_ ( .D(n544), .CK(clk), .RN(n8526),
.Q(Add_result[35]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_34_ ( .D(n545), .CK(clk), .RN(n8526),
.Q(Add_result[34]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n577), .CK(clk), .RN(n8529),
.Q(Add_result[2]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_59_ ( .D(n641), .CK(clk), .RN(
n8530), .Q(Op_MY[59]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_55_ ( .D(n637), .CK(clk), .RN(
n8530), .Q(Op_MY[55]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_0_ ( .D(n417), .CK(clk), .RN(n7462),
.Q(exp_oper_result[0]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_1_ ( .D(n416), .CK(clk), .RN(n8506),
.Q(exp_oper_result[1]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_2_ ( .D(n415), .CK(clk), .RN(n7465),
.Q(exp_oper_result[2]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_3_ ( .D(n414), .CK(clk), .RN(n7461),
.Q(exp_oper_result[3]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_4_ ( .D(n413), .CK(clk), .RN(n7463),
.Q(exp_oper_result[4]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_5_ ( .D(n412), .CK(clk), .RN(n8505),
.Q(exp_oper_result[5]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_6_ ( .D(n411), .CK(clk), .RN(n7462),
.Q(exp_oper_result[6]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_7_ ( .D(n410), .CK(clk), .RN(n8506),
.Q(exp_oper_result[7]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_8_ ( .D(n409), .CK(clk), .RN(n8505),
.Q(exp_oper_result[8]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_9_ ( .D(n408), .CK(clk), .RN(n8506),
.Q(exp_oper_result[9]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_10_ ( .D(n407), .CK(clk), .RN(n8505),
.Q(exp_oper_result[10]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_60_ ( .D(n642), .CK(clk), .RN(
n8530), .Q(Op_MY[60]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_56_ ( .D(n638), .CK(clk), .RN(
n8530), .Q(Op_MY[56]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n578), .CK(clk), .RN(n8529),
.Q(Add_result[1]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_58_ ( .D(n640), .CK(clk), .RN(
n8530), .Q(Op_MY[58]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_54_ ( .D(n636), .CK(clk), .RN(
n8531), .Q(Op_MY[54]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n354), .CK(clk),
.RN(n8511), .Q(Sgf_normalized_result[1]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_11_ ( .D(n406), .CK(clk), .RN(n8506),
.Q(exp_oper_result[11]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_103_ ( .D(n525), .CK(clk), .RN(
n8502), .Q(P_Sgf[103]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_101_ ( .D(n523), .CK(clk), .RN(
n8502), .Q(P_Sgf[101]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_100_ ( .D(n522), .CK(clk), .RN(
n8502), .Q(P_Sgf[100]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_99_ ( .D(n521), .CK(clk), .RN(
n8502), .Q(P_Sgf[99]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_98_ ( .D(n519), .CK(clk), .RN(
n8502), .Q(P_Sgf[98]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_97_ ( .D(n518), .CK(clk), .RN(
n8502), .Q(P_Sgf[97]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_96_ ( .D(n517), .CK(clk), .RN(
n8502), .Q(P_Sgf[96]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_95_ ( .D(n516), .CK(clk), .RN(
n8501), .Q(P_Sgf[95]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_94_ ( .D(n515), .CK(clk), .RN(
n8501), .Q(P_Sgf[94]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_57_ ( .D(n478), .CK(clk), .RN(
n8498), .Q(P_Sgf[57]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_56_ ( .D(n477), .CK(clk), .RN(
n8498), .Q(P_Sgf[56]) );
DFFRX1TS Sgf_operation_ODD1_finalreg_Q_reg_54_ ( .D(n475), .CK(clk), .RN(
n8497), .Q(P_Sgf[54]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_51_ ( .D(n633), .CK(clk), .RN(
n8531), .Q(Op_MY[51]), .QN(n1031) );
DFFQX1TS Sgf_operation_ODD1_left_DatO_reg_0_ ( .D(Sgf_operation_ODD1_left_N0), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[0]) );
DFFQX1TS Sgf_operation_ODD1_left_DatO_reg_1_ ( .D(Sgf_operation_ODD1_left_N1), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[1]) );
DFFHQX2TS Sgf_operation_ODD1_left_DatO_reg_5_ ( .D(
Sgf_operation_ODD1_left_N5), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[5]) );
DFFHQX2TS Sgf_operation_ODD1_left_DatO_reg_13_ ( .D(
Sgf_operation_ODD1_left_N13), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[13]) );
DFFHQX2TS Sgf_operation_ODD1_right_DatO_reg_5_ ( .D(
Sgf_operation_ODD1_right_N5), .CK(clk), .Q(Sgf_operation_Result[5]) );
DFFHQX2TS Sgf_operation_ODD1_right_DatO_reg_6_ ( .D(
Sgf_operation_ODD1_right_N6), .CK(clk), .Q(Sgf_operation_Result[6]) );
DFFHQX2TS Sgf_operation_ODD1_right_DatO_reg_11_ ( .D(
Sgf_operation_ODD1_right_N11), .CK(clk), .Q(Sgf_operation_Result[11])
);
DFFHQX2TS Sgf_operation_ODD1_right_DatO_reg_12_ ( .D(
Sgf_operation_ODD1_right_N12), .CK(clk), .Q(Sgf_operation_Result[12])
);
DFFHQX1TS Sgf_operation_ODD1_right_DatO_reg_15_ ( .D(
Sgf_operation_ODD1_right_N15), .CK(clk), .Q(Sgf_operation_Result[15])
);
DFFHQX2TS Sgf_operation_ODD1_right_DatO_reg_17_ ( .D(
Sgf_operation_ODD1_right_N17), .CK(clk), .Q(Sgf_operation_Result[17])
);
DFFHQX1TS Sgf_operation_ODD1_right_DatO_reg_20_ ( .D(
Sgf_operation_ODD1_right_N20), .CK(clk), .Q(Sgf_operation_Result[20])
);
DFFHQX2TS Sgf_operation_ODD1_right_DatO_reg_30_ ( .D(
Sgf_operation_ODD1_right_N30), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[30]) );
DFFHQX2TS Sgf_operation_ODD1_right_DatO_reg_31_ ( .D(
Sgf_operation_ODD1_right_N31), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[31]) );
DFFQX2TS Sgf_operation_ODD1_right_DatO_reg_33_ ( .D(
Sgf_operation_ODD1_right_N33), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[33]) );
DFFQX2TS Sgf_operation_ODD1_right_DatO_reg_34_ ( .D(
Sgf_operation_ODD1_right_N34), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[34]) );
DFFQX2TS Sgf_operation_ODD1_right_DatO_reg_42_ ( .D(
Sgf_operation_ODD1_right_N42), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[42]) );
DFFQX1TS Sgf_operation_ODD1_right_DatO_reg_52_ ( .D(
Sgf_operation_ODD1_right_N52), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[52]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_0_ ( .D(
Sgf_operation_ODD1_middle_N0), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[0]) );
DFFHQX1TS Sgf_operation_ODD1_middle_DatO_reg_5_ ( .D(
Sgf_operation_ODD1_middle_N5), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[5]) );
DFFHQX1TS Sgf_operation_ODD1_middle_DatO_reg_8_ ( .D(
Sgf_operation_ODD1_middle_N8), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[8]) );
DFFHQX1TS Sgf_operation_ODD1_middle_DatO_reg_13_ ( .D(
Sgf_operation_ODD1_middle_N13), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[13]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_28_ ( .D(
Sgf_operation_ODD1_middle_N28), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[28]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_31_ ( .D(
Sgf_operation_ODD1_middle_N31), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[31]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_33_ ( .D(
Sgf_operation_ODD1_middle_N33), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[33]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_34_ ( .D(
Sgf_operation_ODD1_middle_N34), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[34]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_43_ ( .D(
Sgf_operation_ODD1_middle_N43), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[43]) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(n711), .CK(clk), .RN(n8502), .Q(
FS_Module_state_reg[2]), .QN(n8447) );
DFFRX2TS FS_Module_state_reg_reg_0_ ( .D(n713), .CK(clk), .RN(n8497), .Q(
FS_Module_state_reg[0]), .QN(n8446) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_46_ ( .D(
Sgf_operation_ODD1_middle_N46), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[46]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_47_ ( .D(
Sgf_operation_ODD1_middle_N47), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[47]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_50_ ( .D(
Sgf_operation_ODD1_middle_N50), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[50]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_52_ ( .D(n634), .CK(clk), .RN(
n8531), .Q(Op_MY[52]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_40_ ( .D(
Sgf_operation_ODD1_middle_N40), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[40]) );
ADDFHX2TS DP_OP_36J42_124_1029_U6 ( .A(DP_OP_36J42_124_1029_n21), .B(
S_Oper_A_exp[7]), .CI(DP_OP_36J42_124_1029_n6), .CO(
DP_OP_36J42_124_1029_n5), .S(Exp_module_Data_S[7]) );
DFFRHQX8TS Operands_load_reg_YMRegister_Q_reg_32_ ( .D(n614), .CK(clk), .RN(
n8534), .Q(n755) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n673), .CK(clk), .RN(
n8521), .Q(Op_MX[27]), .QN(n1006) );
DFFHQX2TS Sgf_operation_ODD1_left_DatO_reg_6_ ( .D(
Sgf_operation_ODD1_left_N6), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[6]) );
DFFQX2TS Sgf_operation_ODD1_middle_DatO_reg_48_ ( .D(
Sgf_operation_ODD1_middle_N48), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[48]) );
DFFQX4TS Sgf_operation_ODD1_left_DatO_reg_17_ ( .D(
Sgf_operation_ODD1_left_N17), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[17]) );
DFFQX4TS Sgf_operation_ODD1_left_DatO_reg_26_ ( .D(
Sgf_operation_ODD1_left_N26), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[26]) );
ADDFHX2TS DP_OP_36J42_124_1029_U12 ( .A(DP_OP_36J42_124_1029_n27), .B(
S_Oper_A_exp[1]), .CI(DP_OP_36J42_124_1029_n12), .CO(
DP_OP_36J42_124_1029_n11), .S(Exp_module_Data_S[1]) );
ADDFHX2TS DP_OP_36J42_124_1029_U11 ( .A(DP_OP_36J42_124_1029_n26), .B(
S_Oper_A_exp[2]), .CI(DP_OP_36J42_124_1029_n11), .CO(
DP_OP_36J42_124_1029_n10), .S(Exp_module_Data_S[2]) );
ADDFHX2TS DP_OP_36J42_124_1029_U8 ( .A(DP_OP_36J42_124_1029_n23), .B(
S_Oper_A_exp[5]), .CI(DP_OP_36J42_124_1029_n8), .CO(
DP_OP_36J42_124_1029_n7), .S(Exp_module_Data_S[5]) );
ADDFHX2TS DP_OP_36J42_124_1029_U7 ( .A(DP_OP_36J42_124_1029_n22), .B(
S_Oper_A_exp[6]), .CI(DP_OP_36J42_124_1029_n7), .CO(
DP_OP_36J42_124_1029_n6), .S(Exp_module_Data_S[6]) );
ADDFHX2TS DP_OP_36J42_124_1029_U5 ( .A(DP_OP_36J42_124_1029_n20), .B(
S_Oper_A_exp[8]), .CI(DP_OP_36J42_124_1029_n5), .CO(
DP_OP_36J42_124_1029_n4), .S(Exp_module_Data_S[8]) );
ADDFHX2TS DP_OP_36J42_124_1029_U4 ( .A(DP_OP_36J42_124_1029_n19), .B(
S_Oper_A_exp[9]), .CI(DP_OP_36J42_124_1029_n4), .CO(
DP_OP_36J42_124_1029_n3), .S(Exp_module_Data_S[9]) );
DFFHQX1TS Sgf_operation_ODD1_left_DatO_reg_37_ ( .D(
Sgf_operation_ODD1_left_N37), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[37]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_38_ ( .D(
Sgf_operation_ODD1_middle_N38), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[38]) );
DFFQX4TS Sgf_operation_ODD1_left_DatO_reg_7_ ( .D(Sgf_operation_ODD1_left_N7), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[7]) );
DFFQX4TS Sgf_operation_ODD1_right_DatO_reg_28_ ( .D(
Sgf_operation_ODD1_right_N28), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[28]) );
DFFQX4TS Sgf_operation_ODD1_middle_DatO_reg_7_ ( .D(
Sgf_operation_ODD1_middle_N7), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[7]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_23_ ( .D(
Sgf_operation_ODD1_middle_N23), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[23]) );
DFFQX4TS Sgf_operation_ODD1_left_DatO_reg_20_ ( .D(
Sgf_operation_ODD1_left_N20), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[20]) );
DFFQX2TS Sgf_operation_ODD1_left_DatO_reg_9_ ( .D(Sgf_operation_ODD1_left_N9), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[9]) );
DFFQX4TS Sgf_operation_ODD1_left_DatO_reg_12_ ( .D(
Sgf_operation_ODD1_left_N12), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[12]) );
DFFQX4TS Sgf_operation_ODD1_left_DatO_reg_2_ ( .D(Sgf_operation_ODD1_left_N2), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[2]) );
DFFQX4TS Sgf_operation_ODD1_left_DatO_reg_3_ ( .D(Sgf_operation_ODD1_left_N3), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[3]) );
DFFQX4TS Sgf_operation_ODD1_left_DatO_reg_11_ ( .D(
Sgf_operation_ODD1_left_N11), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[11]) );
DFFQX4TS Sgf_operation_ODD1_left_DatO_reg_24_ ( .D(
Sgf_operation_ODD1_left_N24), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[24]) );
DFFQX4TS Sgf_operation_ODD1_left_DatO_reg_25_ ( .D(
Sgf_operation_ODD1_left_N25), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[25]) );
DFFHQX1TS Sgf_operation_ODD1_right_DatO_reg_26_ ( .D(
Sgf_operation_ODD1_right_N26), .CK(clk), .Q(Sgf_operation_Result[26])
);
DFFHQX2TS Sgf_operation_ODD1_right_DatO_reg_1_ ( .D(
Sgf_operation_ODD1_right_N1), .CK(clk), .Q(Sgf_operation_Result[1]) );
DFFHQX2TS Sgf_operation_ODD1_right_DatO_reg_3_ ( .D(
Sgf_operation_ODD1_right_N3), .CK(clk), .Q(Sgf_operation_Result[3]) );
DFFHQX2TS Sgf_operation_ODD1_right_DatO_reg_4_ ( .D(
Sgf_operation_ODD1_right_N4), .CK(clk), .Q(Sgf_operation_Result[4]) );
DFFHQX2TS Sgf_operation_ODD1_right_DatO_reg_10_ ( .D(
Sgf_operation_ODD1_right_N10), .CK(clk), .Q(Sgf_operation_Result[10])
);
DFFHQX2TS Sgf_operation_ODD1_right_DatO_reg_8_ ( .D(
Sgf_operation_ODD1_right_N8), .CK(clk), .Q(Sgf_operation_Result[8]) );
DFFHQX2TS Sgf_operation_ODD1_right_DatO_reg_13_ ( .D(
Sgf_operation_ODD1_right_N13), .CK(clk), .Q(Sgf_operation_Result[13])
);
DFFHQX2TS Sgf_operation_ODD1_left_DatO_reg_8_ ( .D(
Sgf_operation_ODD1_left_N8), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[8]) );
DFFHQX2TS Sgf_operation_ODD1_left_DatO_reg_27_ ( .D(
Sgf_operation_ODD1_left_N27), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[27]) );
DFFHQX2TS Sgf_operation_ODD1_left_DatO_reg_29_ ( .D(
Sgf_operation_ODD1_left_N29), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[29]) );
DFFQX2TS Sgf_operation_ODD1_right_DatO_reg_16_ ( .D(
Sgf_operation_ODD1_right_N16), .CK(clk), .Q(Sgf_operation_Result[16])
);
DFFQX2TS Sgf_operation_ODD1_right_DatO_reg_19_ ( .D(
Sgf_operation_ODD1_right_N19), .CK(clk), .Q(Sgf_operation_Result[19])
);
DFFQX1TS Sgf_operation_ODD1_right_DatO_reg_9_ ( .D(
Sgf_operation_ODD1_right_N9), .CK(clk), .Q(Sgf_operation_Result[9]) );
DFFQX4TS Sgf_operation_ODD1_left_DatO_reg_4_ ( .D(Sgf_operation_ODD1_left_N4), .CK(clk), .Q(Sgf_operation_ODD1_Q_left[4]) );
DFFQX2TS Sgf_operation_ODD1_right_DatO_reg_18_ ( .D(
Sgf_operation_ODD1_right_N18), .CK(clk), .Q(Sgf_operation_Result[18])
);
DFFQX2TS Sgf_operation_ODD1_left_DatO_reg_16_ ( .D(
Sgf_operation_ODD1_left_N16), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[16]) );
DFFQX2TS Sgf_operation_ODD1_left_DatO_reg_19_ ( .D(
Sgf_operation_ODD1_left_N19), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[19]) );
DFFQX2TS Sgf_operation_ODD1_left_DatO_reg_14_ ( .D(
Sgf_operation_ODD1_left_N14), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[14]) );
DFFQX2TS Sgf_operation_ODD1_left_DatO_reg_18_ ( .D(
Sgf_operation_ODD1_left_N18), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[18]) );
DFFQX2TS Sgf_operation_ODD1_right_DatO_reg_14_ ( .D(
Sgf_operation_ODD1_right_N14), .CK(clk), .Q(Sgf_operation_Result[14])
);
DFFHQX1TS Sgf_operation_ODD1_right_DatO_reg_25_ ( .D(
Sgf_operation_ODD1_right_N25), .CK(clk), .Q(Sgf_operation_Result[25])
);
DFFHQX1TS Sgf_operation_ODD1_right_DatO_reg_2_ ( .D(
Sgf_operation_ODD1_right_N2), .CK(clk), .Q(Sgf_operation_Result[2]) );
DFFHQX1TS Sgf_operation_ODD1_right_DatO_reg_7_ ( .D(
Sgf_operation_ODD1_right_N7), .CK(clk), .Q(Sgf_operation_Result[7]) );
DFFHQX1TS Sgf_operation_ODD1_right_DatO_reg_21_ ( .D(
Sgf_operation_ODD1_right_N21), .CK(clk), .Q(Sgf_operation_Result[21])
);
DFFHQX1TS Sgf_operation_ODD1_right_DatO_reg_22_ ( .D(
Sgf_operation_ODD1_right_N22), .CK(clk), .Q(Sgf_operation_Result[22])
);
DFFQX4TS Sgf_operation_ODD1_left_DatO_reg_15_ ( .D(
Sgf_operation_ODD1_left_N15), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[15]) );
DFFQX4TS Sgf_operation_ODD1_left_DatO_reg_10_ ( .D(
Sgf_operation_ODD1_left_N10), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[10]) );
DFFQX4TS Sgf_operation_ODD1_left_DatO_reg_21_ ( .D(
Sgf_operation_ODD1_left_N21), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[21]) );
DFFQX4TS Sgf_operation_ODD1_left_DatO_reg_23_ ( .D(
Sgf_operation_ODD1_left_N23), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[23]) );
DFFQX4TS Sgf_operation_ODD1_right_DatO_reg_27_ ( .D(
Sgf_operation_ODD1_right_N27), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[27]) );
DFFQX4TS Sgf_operation_ODD1_right_DatO_reg_29_ ( .D(
Sgf_operation_ODD1_right_N29), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[29]) );
DFFQX4TS Sgf_operation_ODD1_right_DatO_reg_23_ ( .D(
Sgf_operation_ODD1_right_N23), .CK(clk), .Q(Sgf_operation_Result[23])
);
DFFQX4TS Sgf_operation_ODD1_right_DatO_reg_24_ ( .D(
Sgf_operation_ODD1_right_N24), .CK(clk), .Q(Sgf_operation_Result[24])
);
DFFQX1TS Sgf_operation_ODD1_left_DatO_reg_40_ ( .D(
Sgf_operation_ODD1_left_N40), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[40]) );
DFFQX2TS Sgf_operation_ODD1_right_DatO_reg_41_ ( .D(
Sgf_operation_ODD1_right_N41), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[41]) );
DFFQX2TS Sgf_operation_ODD1_left_DatO_reg_47_ ( .D(
Sgf_operation_ODD1_left_N47), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[47]) );
DFFHQX2TS Sgf_operation_ODD1_right_DatO_reg_36_ ( .D(
Sgf_operation_ODD1_right_N36), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[36]) );
DFFHQX2TS Sgf_operation_ODD1_left_DatO_reg_38_ ( .D(
Sgf_operation_ODD1_left_N38), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[38]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_21_ ( .D(
Sgf_operation_ODD1_middle_N21), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[21]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_22_ ( .D(
Sgf_operation_ODD1_middle_N22), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[22]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_16_ ( .D(
Sgf_operation_ODD1_middle_N16), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[16]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_10_ ( .D(
Sgf_operation_ODD1_middle_N10), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[10]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_20_ ( .D(
Sgf_operation_ODD1_middle_N20), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[20]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_24_ ( .D(
Sgf_operation_ODD1_middle_N24), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[24]) );
DFFHQX1TS Sgf_operation_ODD1_middle_DatO_reg_1_ ( .D(
Sgf_operation_ODD1_middle_N1), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[1]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_29_ ( .D(
Sgf_operation_ODD1_middle_N29), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[29]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_30_ ( .D(
Sgf_operation_ODD1_middle_N30), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[30]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_25_ ( .D(
Sgf_operation_ODD1_middle_N25), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[25]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_26_ ( .D(
Sgf_operation_ODD1_middle_N26), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[26]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_15_ ( .D(
Sgf_operation_ODD1_middle_N15), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[15]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_19_ ( .D(
Sgf_operation_ODD1_middle_N19), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[19]) );
DFFHQX1TS Sgf_operation_ODD1_left_DatO_reg_36_ ( .D(
Sgf_operation_ODD1_left_N36), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[36]) );
DFFQX2TS Sgf_operation_ODD1_middle_DatO_reg_27_ ( .D(
Sgf_operation_ODD1_middle_N27), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[27]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_9_ ( .D(
Sgf_operation_ODD1_middle_N9), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[9]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_14_ ( .D(
Sgf_operation_ODD1_middle_N14), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[14]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_18_ ( .D(
Sgf_operation_ODD1_middle_N18), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[18]) );
DFFQX4TS Sgf_operation_ODD1_middle_DatO_reg_2_ ( .D(
Sgf_operation_ODD1_middle_N2), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[2]) );
DFFQX4TS Sgf_operation_ODD1_middle_DatO_reg_3_ ( .D(
Sgf_operation_ODD1_middle_N3), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[3]) );
DFFQX4TS Sgf_operation_ODD1_middle_DatO_reg_4_ ( .D(
Sgf_operation_ODD1_middle_N4), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[4]) );
DFFQX4TS Sgf_operation_ODD1_middle_DatO_reg_6_ ( .D(
Sgf_operation_ODD1_middle_N6), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[6]) );
DFFQX4TS Sgf_operation_ODD1_middle_DatO_reg_11_ ( .D(
Sgf_operation_ODD1_middle_N11), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[11]) );
DFFQX4TS Sgf_operation_ODD1_middle_DatO_reg_12_ ( .D(
Sgf_operation_ODD1_middle_N12), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[12]) );
DFFQX4TS Sgf_operation_ODD1_middle_DatO_reg_17_ ( .D(
Sgf_operation_ODD1_middle_N17), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[17]) );
DFFQX2TS Sgf_operation_ODD1_right_DatO_reg_39_ ( .D(
Sgf_operation_ODD1_right_N39), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[39]) );
DFFQX2TS Sgf_operation_ODD1_right_DatO_reg_40_ ( .D(
Sgf_operation_ODD1_right_N40), .CK(clk), .Q(
Sgf_operation_ODD1_Q_right[40]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_36_ ( .D(
Sgf_operation_ODD1_middle_N36), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[36]) );
DFFHQX4TS Sgf_operation_ODD1_middle_DatO_reg_39_ ( .D(
Sgf_operation_ODD1_middle_N39), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[39]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_35_ ( .D(
Sgf_operation_ODD1_middle_N35), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[35]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_44_ ( .D(
Sgf_operation_ODD1_middle_N44), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[44]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_37_ ( .D(
Sgf_operation_ODD1_middle_N37), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[37]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_41_ ( .D(
Sgf_operation_ODD1_middle_N41), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[41]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_45_ ( .D(
Sgf_operation_ODD1_middle_N45), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[45]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_42_ ( .D(
Sgf_operation_ODD1_middle_N42), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[42]) );
DFFQX1TS Sgf_operation_ODD1_left_DatO_reg_48_ ( .D(
Sgf_operation_ODD1_left_N48), .CK(clk), .Q(
Sgf_operation_ODD1_Q_left[48]) );
DFFQX1TS Sgf_operation_ODD1_middle_DatO_reg_49_ ( .D(
Sgf_operation_ODD1_middle_N49), .CK(clk), .Q(
Sgf_operation_ODD1_Q_middle[49]) );
CMPR42X1TS mult_x_23_U756 ( .A(mult_x_23_n1310), .B(mult_x_23_n832), .C(
mult_x_23_n1362), .D(mult_x_23_n1336), .ICI(mult_x_23_n1388), .S(
mult_x_23_n830), .ICO(mult_x_23_n828), .CO(mult_x_23_n829) );
CMPR32X2TS DP_OP_36J42_124_1029_U13 ( .A(S_Oper_A_exp[0]), .B(n904), .C(
DP_OP_36J42_124_1029_n28), .CO(DP_OP_36J42_124_1029_n12), .S(
Exp_module_Data_S[0]) );
DFFRX4TS FS_Module_state_reg_reg_3_ ( .D(n714), .CK(clk), .RN(n8497), .Q(
FS_Module_state_reg[3]), .QN(n8470) );
CMPR32X2TS DP_OP_36J42_124_1029_U3 ( .A(DP_OP_36J42_124_1029_n18), .B(
S_Oper_A_exp[10]), .C(DP_OP_36J42_124_1029_n3), .CO(
DP_OP_36J42_124_1029_n2), .S(Exp_module_Data_S[10]) );
CLKMX2X2TS U746 ( .A(P_Sgf[61]), .B(n8068), .S0(n8133), .Y(n482) );
XNOR2X2TS U747 ( .A(n5169), .B(n5168), .Y(Sgf_operation_ODD1_left_N43) );
XNOR2X2TS U748 ( .A(n4775), .B(n4774), .Y(Sgf_operation_ODD1_left_N32) );
XNOR2X1TS U749 ( .A(n5236), .B(n5235), .Y(Sgf_operation_ODD1_right_N31) );
XNOR2X2TS U750 ( .A(n4861), .B(n4860), .Y(Sgf_operation_ODD1_left_N36) );
XNOR2X2TS U751 ( .A(n7334), .B(n7333), .Y(Sgf_operation_ODD1_middle_N42) );
XNOR2X2TS U752 ( .A(n7243), .B(n7242), .Y(Sgf_operation_ODD1_middle_N37) );
XNOR2X2TS U753 ( .A(n7304), .B(n7303), .Y(Sgf_operation_ODD1_middle_N51) );
XNOR2X2TS U754 ( .A(n7342), .B(n7341), .Y(Sgf_operation_ODD1_middle_N38) );
XNOR2X2TS U755 ( .A(n7414), .B(n7413), .Y(Sgf_operation_ODD1_middle_N41) );
XOR2X2TS U756 ( .A(n816), .B(n6734), .Y(Sgf_operation_ODD1_right_N42) );
XOR2X2TS U757 ( .A(n4893), .B(n6091), .Y(Sgf_operation_ODD1_right_N30) );
BUFX3TS U758 ( .A(n8189), .Y(n8133) );
BUFX3TS U759 ( .A(n8189), .Y(n8188) );
BUFX3TS U760 ( .A(n8189), .Y(n8190) );
BUFX3TS U761 ( .A(n8189), .Y(n8224) );
BUFX3TS U762 ( .A(n8189), .Y(n8293) );
BUFX3TS U763 ( .A(n8189), .Y(n7712) );
BUFX3TS U764 ( .A(n8189), .Y(n7988) );
BUFX3TS U765 ( .A(n8189), .Y(n7850) );
BUFX3TS U766 ( .A(n8191), .Y(n8192) );
INVX2TS U767 ( .A(n8443), .Y(n8434) );
INVX2TS U768 ( .A(n8443), .Y(n8363) );
INVX2TS U769 ( .A(n8443), .Y(n8361) );
INVX2TS U770 ( .A(n8443), .Y(n8436) );
INVX2TS U771 ( .A(n8440), .Y(n8435) );
INVX2TS U772 ( .A(n8440), .Y(n8437) );
INVX2TS U773 ( .A(n8442), .Y(n8439) );
INVX2TS U774 ( .A(n8442), .Y(n8360) );
INVX2TS U775 ( .A(n8442), .Y(n8362) );
INVX2TS U776 ( .A(n8355), .Y(n941) );
INVX2TS U777 ( .A(n8355), .Y(n942) );
XOR2X1TS U778 ( .A(n7693), .B(n7692), .Y(n7694) );
XOR2X2TS U779 ( .A(n7512), .B(n7511), .Y(n7513) );
XOR2X2TS U780 ( .A(n7657), .B(n7656), .Y(n7658) );
XOR2X2TS U781 ( .A(n7711), .B(n7710), .Y(n7713) );
AOI21X1TS U782 ( .A0(n7108), .A1(n6097), .B0(n6096), .Y(n6102) );
XOR2X2TS U783 ( .A(n7604), .B(n7603), .Y(n7605) );
XOR2X2TS U784 ( .A(n7623), .B(n7622), .Y(n7624) );
XOR2X2TS U785 ( .A(n7632), .B(n7631), .Y(n7633) );
XOR2X2TS U786 ( .A(n7613), .B(n7612), .Y(n7614) );
XOR2X2TS U787 ( .A(n7725), .B(n7724), .Y(n7726) );
NAND2X1TS U788 ( .A(n4879), .B(n5221), .Y(n4881) );
NAND2X1TS U789 ( .A(n7354), .B(n7352), .Y(n7247) );
NAND2X1TS U790 ( .A(n5256), .B(n5258), .Y(n5261) );
INVX2TS U791 ( .A(n5316), .Y(n5331) );
INVX2TS U792 ( .A(n6146), .Y(n6163) );
INVX2TS U793 ( .A(n5332), .Y(n5989) );
BUFX3TS U794 ( .A(n8189), .Y(n8191) );
INVX2TS U795 ( .A(n897), .Y(n7274) );
NOR2X1TS U796 ( .A(n7095), .B(n7097), .Y(n7100) );
NOR2XLTS U797 ( .A(n7257), .B(n7437), .Y(n7261) );
NAND2XLTS U798 ( .A(n7335), .B(n7340), .Y(n3912) );
NAND2XLTS U799 ( .A(n7373), .B(n7376), .Y(n7378) );
AOI21X2TS U800 ( .A0(n7325), .A1(n4828), .B0(n4827), .Y(n4829) );
NAND2X1TS U801 ( .A(n7417), .B(n7407), .Y(n7409) );
CLKAND2X2TS U802 ( .A(n7323), .B(n4694), .Y(n745) );
NAND2X2TS U803 ( .A(n7323), .B(n3925), .Y(n3927) );
AOI21X2TS U804 ( .A0(n7427), .A1(n7426), .B0(n7425), .Y(n7428) );
AOI21X2TS U805 ( .A0(n7849), .A1(n7847), .B0(n7834), .Y(n7839) );
AOI21X2TS U806 ( .A0(n5225), .A1(n4879), .B0(n4878), .Y(n4880) );
NAND2X2TS U807 ( .A(n7323), .B(n771), .Y(n7327) );
NAND2X2TS U808 ( .A(n1021), .B(n7323), .Y(n3578) );
AOI21X2TS U809 ( .A0(n5174), .A1(n5173), .B0(n5172), .Y(n5175) );
AOI21X2TS U810 ( .A0(n7908), .A1(n7906), .B0(n7892), .Y(n7897) );
OAI21X1TS U811 ( .A0(n8032), .A1(n8046), .B0(n8047), .Y(n8037) );
OAI21X1TS U812 ( .A0(n762), .A1(n5300), .B0(n5301), .Y(n5291) );
BUFX3TS U813 ( .A(n8440), .Y(n8442) );
OAI21X1TS U814 ( .A0(n8080), .A1(n8076), .B0(n8077), .Y(n8067) );
AOI21X1TS U815 ( .A0(n7427), .A1(n7407), .B0(n7406), .Y(n7408) );
AOI21X1TS U816 ( .A0(n7336), .A1(n7340), .B0(n3910), .Y(n3911) );
INVX2TS U817 ( .A(n7244), .Y(n7360) );
NOR2X1TS U818 ( .A(n7315), .B(n4692), .Y(n4694) );
INVX2TS U819 ( .A(n7803), .Y(n7819) );
INVX2TS U820 ( .A(n3908), .Y(n7340) );
INVX2TS U821 ( .A(n5109), .Y(n7407) );
CLKBUFX2TS U822 ( .A(n3909), .Y(n7336) );
INVX8TS U823 ( .A(n7123), .Y(n7379) );
INVX2TS U824 ( .A(n7278), .Y(n7289) );
NAND2X1TS U825 ( .A(n4921), .B(n3901), .Y(n3903) );
INVX2TS U826 ( .A(n7254), .Y(n7376) );
BUFX3TS U827 ( .A(n8189), .Y(n8354) );
INVX2TS U828 ( .A(n7330), .Y(n7417) );
INVX2TS U829 ( .A(n7287), .Y(n7354) );
NOR2X2TS U830 ( .A(n4885), .B(n4877), .Y(n4879) );
OAI21X2TS U831 ( .A0(n7357), .A1(n7356), .B0(n7355), .Y(n7358) );
NOR2X2TS U832 ( .A(n7353), .B(n7356), .Y(n7359) );
NAND2X2TS U833 ( .A(n7733), .B(n7701), .Y(n7711) );
AND2X2TS U834 ( .A(n7489), .B(n8470), .Y(n8365) );
OAI21X1TS U835 ( .A0(n4777), .A1(n4793), .B0(n4794), .Y(n4778) );
INVX2TS U836 ( .A(n7473), .Y(n8433) );
OR3X2TS U837 ( .A(n8364), .B(underflow_flag), .C(overflow_flag), .Y(n8440)
);
INVX6TS U838 ( .A(n4821), .Y(n7292) );
NOR2X1TS U839 ( .A(n5111), .B(n5117), .Y(n5120) );
NAND2X1TS U840 ( .A(n7544), .B(n7547), .Y(n7546) );
AOI21X1TS U841 ( .A0(n4950), .A1(n4938), .B0(n4937), .Y(n4939) );
NAND2X2TS U842 ( .A(n3917), .B(n3556), .Y(n3575) );
INVX2TS U843 ( .A(n8443), .Y(n8364) );
NAND2X1TS U844 ( .A(n3897), .B(n3896), .Y(n4962) );
NAND2XLTS U845 ( .A(n7535), .B(FSM_add_overflow_flag), .Y(n4649) );
INVX4TS U846 ( .A(n7544), .Y(n8070) );
NOR3X2TS U847 ( .A(n8446), .B(FS_Module_state_reg[2]), .C(n7535), .Y(n7489)
);
NOR2X2TS U848 ( .A(n7294), .B(n7300), .Y(n4824) );
AND2X4TS U849 ( .A(FS_Module_state_reg[3]), .B(n7469), .Y(n8443) );
NOR2X1TS U850 ( .A(n7813), .B(n7720), .Y(n7741) );
NOR2X1TS U851 ( .A(n7928), .B(n7825), .Y(n7855) );
OAI21X1TS U852 ( .A0(n4936), .A1(n4935), .B0(n4934), .Y(n4937) );
OR2X2TS U853 ( .A(mult_x_24_n698), .B(mult_x_24_n701), .Y(n5023) );
NAND2X4TS U854 ( .A(n7352), .B(n2931), .Y(n2933) );
INVX2TS U855 ( .A(n8261), .Y(n8305) );
CLKINVX1TS U856 ( .A(n8369), .Y(n7469) );
NOR2X2TS U857 ( .A(n1288), .B(n1298), .Y(n1301) );
AND2X2TS U858 ( .A(n7482), .B(n7535), .Y(n7544) );
NAND2X1TS U859 ( .A(mult_x_24_n723), .B(mult_x_24_n728), .Y(n1277) );
NAND2X1TS U860 ( .A(mult_x_24_n717), .B(mult_x_24_n722), .Y(n1297) );
NOR2X4TS U861 ( .A(n3516), .B(n3515), .Y(n7238) );
NOR2X2TS U862 ( .A(mult_x_24_n717), .B(mult_x_24_n722), .Y(n1288) );
NAND2X2TS U863 ( .A(mult_x_23_n747), .B(mult_x_23_n757), .Y(n4899) );
NAND2X2TS U864 ( .A(mult_x_23_n758), .B(mult_x_23_n768), .Y(n4913) );
NAND2X2TS U865 ( .A(mult_x_23_n726), .B(mult_x_23_n736), .Y(n4794) );
NAND2X2TS U866 ( .A(mult_x_23_n718), .B(mult_x_23_n725), .Y(n4783) );
NOR2X1TS U867 ( .A(mult_x_24_n723), .B(mult_x_24_n728), .Y(n1275) );
CLKINVX3TS U868 ( .A(n5062), .Y(n4635) );
INVX2TS U869 ( .A(n5148), .Y(n3883) );
NAND2XLTS U870 ( .A(n7534), .B(n7481), .Y(n7482) );
NAND3X2TS U871 ( .A(FS_Module_state_reg[0]), .B(n7535), .C(n8447), .Y(n8369)
);
NOR2X6TS U872 ( .A(n7437), .B(n7262), .Y(n2453) );
OAI21X2TS U873 ( .A0(n3537), .A1(n7418), .B0(n3536), .Y(n3538) );
NOR2X1TS U874 ( .A(n7928), .B(n7718), .Y(n7800) );
NOR2X2TS U875 ( .A(n5217), .B(n5244), .Y(n1186) );
NOR2X6TS U876 ( .A(n5109), .B(n7410), .Y(n7343) );
NOR2X6TS U877 ( .A(n7128), .B(n7269), .Y(n7435) );
NOR2X4TS U878 ( .A(n7254), .B(n7380), .Y(n2921) );
NOR2X4TS U879 ( .A(n3908), .B(n3913), .Y(n3524) );
AOI21X1TS U880 ( .A0(n1295), .A1(n1294), .B0(n1293), .Y(n1296) );
NOR2X4TS U881 ( .A(n3526), .B(n3525), .Y(n5109) );
NOR2X4TS U882 ( .A(n2922), .B(n2923), .Y(n7278) );
NAND2X4TS U883 ( .A(n3516), .B(n3515), .Y(n7237) );
NOR2X4TS U884 ( .A(n3530), .B(n3529), .Y(n7345) );
NAND2X4TS U885 ( .A(n2927), .B(n2926), .Y(n7355) );
NOR2X4TS U886 ( .A(mult_x_23_n856), .B(mult_x_23_n846), .Y(n5319) );
NOR2X4TS U887 ( .A(mult_x_23_n726), .B(mult_x_23_n736), .Y(n4793) );
NOR2X4TS U888 ( .A(mult_x_24_n881), .B(mult_x_24_n892), .Y(n7097) );
NAND2X4TS U889 ( .A(mult_x_23_n813), .B(mult_x_23_n823), .Y(n5301) );
NOR2X6TS U890 ( .A(n2929), .B(n2928), .Y(n7363) );
NOR2X6TS U891 ( .A(n2916), .B(n2917), .Y(n7254) );
NOR2X6TS U892 ( .A(n3520), .B(n3519), .Y(n3908) );
NAND2X2TS U893 ( .A(n2929), .B(n2928), .Y(n7364) );
NAND2X2TS U894 ( .A(n2452), .B(n2451), .Y(n7263) );
NAND2X2TS U895 ( .A(n3528), .B(n3527), .Y(n7411) );
NOR2X2TS U896 ( .A(mult_x_23_n647), .B(mult_x_23_n650), .Y(n5177) );
NOR2X2TS U897 ( .A(mult_x_23_n835), .B(mult_x_23_n845), .Y(n5305) );
NAND2X2TS U898 ( .A(mult_x_23_n651), .B(mult_x_23_n655), .Y(n5171) );
NOR2X2TS U899 ( .A(n2445), .B(n2446), .Y(n7128) );
OR2X4TS U900 ( .A(n3545), .B(n3546), .Y(n791) );
NAND2X2TS U901 ( .A(n2914), .B(n2913), .Y(n7369) );
NOR2X4TS U902 ( .A(n2451), .B(n2452), .Y(n7262) );
NAND2X4TS U903 ( .A(n7139), .B(n7143), .Y(n2193) );
INVX2TS U904 ( .A(n5158), .Y(n5195) );
NAND2X4TS U905 ( .A(n1016), .B(n7432), .Y(n3537) );
NOR2X4TS U906 ( .A(mult_x_23_n758), .B(mult_x_23_n768), .Y(n4912) );
NAND2X4TS U907 ( .A(n6119), .B(n6113), .Y(n953) );
NAND2X4TS U908 ( .A(n768), .B(n788), .Y(n5220) );
INVX2TS U909 ( .A(n3837), .Y(n5149) );
INVX2TS U910 ( .A(n7270), .Y(n760) );
NAND2X4TS U911 ( .A(n6128), .B(n6124), .Y(n6117) );
INVX2TS U912 ( .A(n7717), .Y(n7928) );
INVX4TS U913 ( .A(n7275), .Y(n7324) );
NAND2X1TS U914 ( .A(n5258), .B(n1012), .Y(n3891) );
OAI21X1TS U915 ( .A0(n1292), .A1(n5016), .B0(n1291), .Y(n1293) );
OR2X6TS U916 ( .A(n3532), .B(n3531), .Y(n1016) );
OR2X6TS U917 ( .A(n2190), .B(n2189), .Y(n7139) );
NAND2X1TS U918 ( .A(n3551), .B(n3550), .Y(n4695) );
OR2X2TS U919 ( .A(mult_x_24_n750), .B(mult_x_24_n743), .Y(n1027) );
OR2X2TS U920 ( .A(mult_x_24_n751), .B(mult_x_24_n759), .Y(n1028) );
OR2X2TS U921 ( .A(mult_x_23_n646), .B(mult_x_23_n642), .Y(n5267) );
OR2X4TS U922 ( .A(mult_x_24_n798), .B(mult_x_24_n808), .Y(n768) );
OR2X4TS U923 ( .A(mult_x_23_n878), .B(mult_x_23_n887), .Y(n787) );
NAND2X2TS U924 ( .A(n2447), .B(n2448), .Y(n7270) );
NOR2X2TS U925 ( .A(mult_x_23_n669), .B(mult_x_23_n663), .Y(n3836) );
NOR2X2TS U926 ( .A(mult_x_24_n987), .B(mult_x_24_n996), .Y(n1174) );
OR2X4TS U927 ( .A(mult_x_23_n857), .B(mult_x_23_n867), .Y(n1008) );
OR2X4TS U928 ( .A(mult_x_24_n820), .B(mult_x_24_n809), .Y(n788) );
INVX4TS U929 ( .A(n7144), .Y(n7134) );
INVX2TS U930 ( .A(n7148), .Y(n2185) );
NOR2X2TS U931 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[2]), .Y(
n7485) );
INVX2TS U932 ( .A(n5324), .Y(n5329) );
INVX2TS U933 ( .A(n7147), .Y(n7152) );
NOR2X6TS U934 ( .A(n7388), .B(n7157), .Y(n7393) );
ADDFHX2TS U935 ( .A(n2426), .B(n2425), .CI(n2424), .CO(n2451), .S(n2450) );
INVX4TS U936 ( .A(n6122), .Y(n6128) );
NAND2X1TS U937 ( .A(mult_x_23_n906), .B(mult_x_23_n913), .Y(n5345) );
INVX2TS U938 ( .A(n2183), .Y(n965) );
NOR2X4TS U939 ( .A(mult_x_24_n1007), .B(mult_x_24_n1014), .Y(n6947) );
NOR2X6TS U940 ( .A(n1945), .B(n1944), .Y(n7400) );
NAND2X2TS U941 ( .A(n1945), .B(n1944), .Y(n7401) );
NOR2X2TS U942 ( .A(n1939), .B(n1938), .Y(n7157) );
NAND2X2TS U943 ( .A(mult_x_24_n743), .B(mult_x_24_n750), .Y(n4873) );
NAND2X2TS U944 ( .A(mult_x_24_n798), .B(mult_x_24_n808), .Y(n4852) );
NAND2X2TS U945 ( .A(mult_x_23_n878), .B(mult_x_23_n887), .Y(n5990) );
CLKINVX6TS U946 ( .A(n6124), .Y(n1176) );
NAND2X1TS U947 ( .A(mult_x_24_n778), .B(mult_x_24_n787), .Y(n4845) );
NOR2X6TS U948 ( .A(n4425), .B(n8000), .Y(n4427) );
ADDFHX2TS U949 ( .A(n3271), .B(n3270), .CI(n3269), .CO(n3318), .S(n3314) );
AOI21X2TS U950 ( .A0(n789), .A1(n7177), .B0(n1600), .Y(n1601) );
CMPR32X2TS U951 ( .A(n3083), .B(n3082), .C(n3081), .CO(n3133), .S(n3066) );
OR2X6TS U952 ( .A(mult_x_24_n1015), .B(mult_x_24_n1022), .Y(n6150) );
CMPR32X2TS U953 ( .A(n3127), .B(n3126), .C(n3125), .CO(n3566), .S(n3563) );
CMPR32X2TS U954 ( .A(n3114), .B(n3113), .C(n3112), .CO(n3564), .S(n3561) );
NAND2X1TS U955 ( .A(n8308), .B(n4331), .Y(n4333) );
INVX2TS U956 ( .A(n6149), .Y(n1171) );
INVX2TS U957 ( .A(n5355), .Y(n5350) );
CMPR32X2TS U958 ( .A(n3101), .B(n3100), .C(n3099), .CO(n3150), .S(n3139) );
INVX2TS U959 ( .A(n7168), .Y(n7174) );
AOI21X2TS U960 ( .A0(n4417), .A1(n8061), .B0(n4416), .Y(n8001) );
NAND2X2TS U961 ( .A(n4616), .B(n7887), .Y(n4618) );
NOR2X2TS U962 ( .A(n7185), .B(n7226), .Y(n1595) );
INVX2TS U963 ( .A(n7181), .Y(n7177) );
NAND2X2TS U964 ( .A(n8322), .B(n4393), .Y(n4395) );
CMPR32X2TS U965 ( .A(n1925), .B(n1924), .C(n1923), .CO(n1934), .S(n1935) );
CMPR32X2TS U966 ( .A(n3216), .B(n3215), .C(n3214), .CO(n3268), .S(n3262) );
CMPR32X2TS U967 ( .A(n1265), .B(n1264), .C(n1263), .CO(mult_x_23_n664), .S(
mult_x_23_n665) );
CMPR32X2TS U968 ( .A(n2895), .B(n2894), .C(n2893), .CO(n3197), .S(n2892) );
CMPR32X2TS U969 ( .A(n4741), .B(n6223), .C(n4740), .CO(mult_x_24_n712), .S(
mult_x_24_n713) );
CMPR42X1TS U970 ( .A(mult_x_23_n1333), .B(mult_x_23_n1463), .C(
mult_x_23_n809), .D(mult_x_23_n1437), .ICI(mult_x_23_n806), .S(
mult_x_23_n797), .ICO(mult_x_23_n795), .CO(mult_x_23_n796) );
CMPR42X1TS U971 ( .A(mult_x_23_n1358), .B(mult_x_23_n1280), .C(
mult_x_23_n1410), .D(mult_x_23_n798), .ICI(mult_x_23_n795), .S(
mult_x_23_n786), .ICO(mult_x_23_n784), .CO(mult_x_23_n785) );
NOR2X4TS U972 ( .A(mult_x_23_n936), .B(mult_x_23_n942), .Y(n5359) );
NAND2X2TS U973 ( .A(n1730), .B(n1729), .Y(n7169) );
NAND2X2TS U974 ( .A(mult_x_23_n936), .B(mult_x_23_n942), .Y(n5360) );
NOR2X2TS U975 ( .A(mult_x_23_n922), .B(mult_x_23_n928), .Y(n3746) );
NAND2X2TS U976 ( .A(n1593), .B(n1592), .Y(n7186) );
NOR2X1TS U977 ( .A(n7601), .B(n7603), .Y(n5063) );
CLKXOR2X2TS U978 ( .A(n5503), .B(n5868), .Y(mult_x_23_n1294) );
NOR2X2TS U979 ( .A(n7891), .B(n7893), .Y(n4616) );
NOR2X2TS U980 ( .A(n7791), .B(n7780), .Y(n4630) );
NOR2X2TS U981 ( .A(n8076), .B(n8063), .Y(n4417) );
NOR2X2TS U982 ( .A(n8128), .B(n8117), .Y(n4409) );
XOR2X1TS U983 ( .A(n4704), .B(n6021), .Y(mult_x_23_n1275) );
NOR2X2TS U984 ( .A(n7948), .B(n7950), .Y(n4610) );
OAI21X2TS U985 ( .A0(n8302), .A1(n8295), .B0(n8296), .Y(n8278) );
ADDFHX2TS U986 ( .A(n1931), .B(n1930), .CI(n1929), .CO(n1921), .S(n1932) );
OAI21X2TS U987 ( .A0(n8347), .A1(n8343), .B0(n8348), .Y(n8160) );
NAND2X2TS U988 ( .A(n7193), .B(n7197), .Y(n1571) );
OAI21X1TS U989 ( .A0(n8063), .A1(n8077), .B0(n8064), .Y(n4416) );
OAI21X1TS U990 ( .A0(n7950), .A1(n7961), .B0(n7951), .Y(n4609) );
OAI21X1TS U991 ( .A0(n8334), .A1(n8330), .B0(n8335), .Y(n4392) );
NOR2X2TS U992 ( .A(n7858), .B(n7861), .Y(n7829) );
CMPR32X2TS U993 ( .A(n3132), .B(n3131), .C(n3130), .CO(n3151), .S(n3126) );
CMPR32X2TS U994 ( .A(n1916), .B(n1915), .C(n1914), .CO(n2166), .S(n1918) );
CMPR32X2TS U995 ( .A(n1855), .B(n1854), .C(n1853), .CO(n1868), .S(n1922) );
CMPR32X2TS U996 ( .A(n2393), .B(n2392), .C(n2391), .CO(n2396), .S(n2412) );
CMPR32X2TS U997 ( .A(n3013), .B(n3012), .C(n3011), .CO(n3017), .S(n3014) );
CMPR32X2TS U998 ( .A(n1858), .B(n1857), .C(n1856), .CO(n1867), .S(n1931) );
CMPR32X2TS U999 ( .A(mult_x_23_n666), .B(n5838), .C(n5837), .CO(
mult_x_23_n657), .S(mult_x_23_n658) );
CMPR32X2TS U1000 ( .A(n2699), .B(n2698), .C(n2697), .CO(n2795), .S(n2745) );
CMPR32X2TS U1001 ( .A(n4759), .B(n4758), .C(n4757), .CO(mult_x_24_n912), .S(
mult_x_24_n913) );
CMPR32X2TS U1002 ( .A(n7491), .B(n5428), .C(n5427), .CO(mult_x_23_n776), .S(
mult_x_23_n777) );
CMPR32X2TS U1003 ( .A(n2813), .B(n2812), .C(n2811), .CO(n2900), .S(n2849) );
CMPR32X2TS U1004 ( .A(n2868), .B(n2867), .C(n2866), .CO(n3206), .S(n2901) );
CMPR32X2TS U1005 ( .A(n3397), .B(n3396), .C(n3395), .CO(n3486), .S(n3504) );
NAND2X1TS U1006 ( .A(n4628), .B(Sgf_operation_ODD1_Q_left[27]), .Y(n7781) );
CMPR32X2TS U1007 ( .A(n3117), .B(n3116), .C(n3115), .CO(n3127), .S(n3122) );
NAND2X1TS U1008 ( .A(n4627), .B(Sgf_operation_ODD1_Q_left[26]), .Y(n7792) );
NOR2X1TS U1009 ( .A(n4384), .B(Sgf_operation_ODD1_Q_right[44]), .Y(n8281) );
OR2X2TS U1010 ( .A(n1566), .B(n1565), .Y(n7197) );
NAND2X1TS U1011 ( .A(n7611), .B(Sgf_operation_ODD1_Q_left[42]), .Y(n7601) );
NAND2X1TS U1012 ( .A(n4406), .B(Sgf_operation_ODD1_Q_left[2]), .Y(n8129) );
NAND2X1TS U1013 ( .A(n4625), .B(Sgf_operation_ODD1_Q_left[24]), .Y(n7816) );
OR2X2TS U1014 ( .A(n1537), .B(n1536), .Y(n7201) );
NAND2X1TS U1015 ( .A(n4328), .B(Sgf_operation_ODD1_Q_right[40]), .Y(n8317)
);
CMPR32X2TS U1016 ( .A(n2755), .B(n2754), .C(n2753), .CO(n2850), .S(n2796) );
OR2X4TS U1017 ( .A(mult_x_24_n1057), .B(mult_x_24_n1061), .Y(n779) );
NAND2X2TS U1018 ( .A(n1568), .B(n1567), .Y(n7192) );
NOR2X1TS U1019 ( .A(n7531), .B(n7640), .Y(n7628) );
NAND2X1TS U1020 ( .A(n989), .B(n4284), .Y(n4293) );
NAND2X1TS U1021 ( .A(n4390), .B(Sgf_operation_ODD1_Q_right[48]), .Y(n8330)
);
NOR2X2TS U1022 ( .A(n4642), .B(Sgf_operation_ODD1_Q_left[28]), .Y(n7755) );
NOR2X2TS U1023 ( .A(n4643), .B(Sgf_operation_ODD1_Q_left[29]), .Y(n7744) );
NOR2X2TS U1024 ( .A(n4619), .B(Sgf_operation_ODD1_Q_left[20]), .Y(n7858) );
NOR2X1TS U1025 ( .A(n4390), .B(Sgf_operation_ODD1_Q_right[48]), .Y(n8327) );
NAND2X2TS U1026 ( .A(n4605), .B(Sgf_operation_ODD1_Q_left[12]), .Y(n7984) );
NAND2X2TS U1027 ( .A(n4643), .B(Sgf_operation_ODD1_Q_left[29]), .Y(n7745) );
CLKXOR2X2TS U1028 ( .A(n6698), .B(n8445), .Y(mult_x_24_n1640) );
CLKXOR2X2TS U1029 ( .A(n5572), .B(n7498), .Y(mult_x_23_n1348) );
NAND2X2TS U1030 ( .A(n4611), .B(Sgf_operation_ODD1_Q_left[16]), .Y(n7930) );
CLKXOR2X2TS U1031 ( .A(n5714), .B(n8404), .Y(mult_x_23_n1435) );
CMPR32X2TS U1032 ( .A(n1864), .B(n1863), .C(n1862), .CO(n1929), .S(n1937) );
ADDFHX1TS U1033 ( .A(n1843), .B(n1842), .CI(n1841), .CO(n1870), .S(n1866) );
OAI21X2TS U1034 ( .A0(n7006), .A1(n6966), .B0(n6514), .Y(n6515) );
XOR2X1TS U1035 ( .A(n5765), .B(n5819), .Y(mult_x_23_n1463) );
XOR2X1TS U1036 ( .A(n6518), .B(n6968), .Y(mult_x_24_n1491) );
XOR2X1TS U1037 ( .A(n6752), .B(n6758), .Y(mult_x_24_n1585) );
XOR2X1TS U1038 ( .A(n5723), .B(n5736), .Y(mult_x_23_n1439) );
XOR2X1TS U1039 ( .A(n6402), .B(n836), .Y(mult_x_24_n1434) );
ADDFHX1TS U1040 ( .A(n2844), .B(n2843), .CI(n2842), .CO(n2893), .S(n2845) );
OAI22X1TS U1041 ( .A0(n3277), .A1(n3428), .B0(n3345), .B1(n3344), .Y(n3325)
);
XOR2X1TS U1042 ( .A(n5593), .B(n6002), .Y(mult_x_23_n1359) );
NAND2X2TS U1043 ( .A(n4398), .B(Sgf_operation_ODD1_Q_right[50]), .Y(n8343)
);
ADDFHX2TS U1044 ( .A(n2129), .B(n2128), .CI(n2127), .CO(n2144), .S(n2161) );
ADDFX2TS U1045 ( .A(n2719), .B(n2718), .CI(n2717), .CO(n2751), .S(n2728) );
INVX2TS U1046 ( .A(n1569), .Y(n7193) );
OAI21XLTS U1047 ( .A0(n5925), .A1(n5878), .B0(n5626), .Y(n5627) );
OAI21X1TS U1048 ( .A0(n5938), .A1(n5684), .B0(n5681), .Y(n5682) );
XOR2X1TS U1049 ( .A(n2156), .B(n2155), .Y(n959) );
OAI21X1TS U1050 ( .A0(n5887), .A1(n5684), .B0(n5669), .Y(n5671) );
OAI21X1TS U1051 ( .A0(n6850), .A1(n6925), .B0(n6306), .Y(n6307) );
ADDFHX2TS U1052 ( .A(n1574), .B(n1573), .CI(n1572), .CO(n1596), .S(n1593) );
OAI21X1TS U1053 ( .A0(n6967), .A1(n6442), .B0(n6381), .Y(n6382) );
CMPR32X2TS U1054 ( .A(n3038), .B(n3037), .C(n3036), .CO(n3058), .S(n3021) );
CMPR32X2TS U1055 ( .A(n5107), .B(n5106), .C(n5105), .CO(mult_x_23_n923), .S(
mult_x_23_n924) );
CMPR32X2TS U1056 ( .A(n2037), .B(n2036), .C(n2035), .CO(n2400), .S(n2067) );
CMPR32X2TS U1057 ( .A(n7067), .B(mult_x_24_n773), .C(n7066), .CO(
mult_x_24_n764), .S(mult_x_24_n765) );
CMPR32X2TS U1058 ( .A(n2989), .B(n2988), .C(n2987), .CO(n3012), .S(n2970) );
CMPR32X2TS U1059 ( .A(n3300), .B(n3299), .C(n3298), .CO(n3357), .S(n3295) );
CMPR32X2TS U1060 ( .A(n2995), .B(n2994), .C(n2993), .CO(n3022), .S(n3008) );
BUFX3TS U1061 ( .A(n8366), .Y(n904) );
NOR2X1TS U1062 ( .A(n739), .B(n3157), .Y(n3094) );
NOR2X1TS U1063 ( .A(n3120), .B(n3157), .Y(n3160) );
XOR2X1TS U1064 ( .A(n4363), .B(n4362), .Y(n4384) );
XOR2X1TS U1065 ( .A(n4318), .B(n4317), .Y(n4328) );
AOI222X1TS U1066 ( .A0(n6923), .A1(n6922), .B0(n6921), .B1(Op_MX[21]), .C0(
n6920), .C1(n878), .Y(n6924) );
XOR2X1TS U1067 ( .A(n4595), .B(n4594), .Y(n4612) );
NAND2X1TS U1068 ( .A(n1537), .B(n1536), .Y(n7200) );
NAND2X2TS U1069 ( .A(mult_x_23_n948), .B(mult_x_23_n952), .Y(n5367) );
OAI21X1TS U1070 ( .A0(n5876), .A1(n5904), .B0(n5875), .Y(n6051) );
NOR2X1TS U1071 ( .A(n7620), .B(n7622), .Y(n7611) );
OAI22X1TS U1072 ( .A0(n2824), .A1(n3430), .B0(n2764), .B1(n3006), .Y(n2834)
);
CLKXOR2X2TS U1073 ( .A(n6548), .B(n6827), .Y(mult_x_24_n1521) );
OAI22X1TS U1074 ( .A0(n2763), .A1(n3279), .B0(n2841), .B1(n2762), .Y(n2835)
);
OAI22X1TS U1075 ( .A0(n2479), .A1(n3336), .B0(n2517), .B1(n3335), .Y(n2487)
);
OAI22X1TS U1076 ( .A0(n2757), .A1(n3231), .B0(n2806), .B1(n3335), .Y(n2812)
);
OAI22X1TS U1077 ( .A0(n2499), .A1(n2809), .B0(n2498), .B1(n2497), .Y(n2528)
);
XOR2X1TS U1078 ( .A(n6049), .B(Op_MX[50]), .Y(n6050) );
OAI22X1TS U1079 ( .A0(n2807), .A1(n3407), .B0(n2875), .B1(n3405), .Y(n2867)
);
NAND2X1TS U1080 ( .A(n7530), .B(n7717), .Y(n7640) );
XOR2X1TS U1081 ( .A(n6541), .B(n835), .Y(mult_x_24_n1509) );
XOR2X1TS U1082 ( .A(n6537), .B(n835), .Y(mult_x_24_n1506) );
OAI21X1TS U1083 ( .A0(n5925), .A1(n5827), .B0(n5826), .Y(n5829) );
XOR2X1TS U1084 ( .A(n5645), .B(n5644), .Y(mult_x_23_n1387) );
XOR2X1TS U1085 ( .A(n6671), .B(n6820), .Y(mult_x_24_n1617) );
XOR2X1TS U1086 ( .A(n5737), .B(n5736), .Y(mult_x_23_n1445) );
XOR2X1TS U1087 ( .A(n6472), .B(n8392), .Y(mult_x_24_n1449) );
OAI21X2TS U1088 ( .A0(n5896), .A1(n5886), .B0(n5506), .Y(n5507) );
OAI22X1TS U1089 ( .A0(n2564), .A1(n3432), .B0(n2652), .B1(n3430), .Y(n2614)
);
CMPR32X2TS U1090 ( .A(n2132), .B(n2131), .C(n2130), .CO(n2128), .S(n2171) );
OAI21X1TS U1091 ( .A0(n5945), .A1(n5924), .B0(n5822), .Y(n5823) );
ADDFHX1TS U1092 ( .A(n3394), .B(n3393), .CI(n3392), .CO(n3445), .S(n3487) );
XNOR2X1TS U1093 ( .A(n3249), .B(n3409), .Y(n3289) );
ADDFHX1TS U1094 ( .A(n1806), .B(n1805), .CI(n1804), .CO(n1899), .S(n1855) );
OAI21XLTS U1095 ( .A0(n5879), .A1(n5761), .B0(n5711), .Y(n5710) );
AOI222X1TS U1096 ( .A0(n882), .A1(n5796), .B0(n865), .B1(n5982), .C0(n6017),
.C1(n6005), .Y(n4703) );
ADDFHX1TS U1097 ( .A(n3454), .B(n3453), .CI(n3452), .CO(n2972), .S(n3462) );
OAI21X1TS U1098 ( .A0(n6993), .A1(n6788), .B0(n6510), .Y(n6511) );
OAI21X1TS U1099 ( .A0(n6993), .A1(n6792), .B0(n4738), .Y(n4739) );
XOR2X1TS U1100 ( .A(n4751), .B(n7494), .Y(n4758) );
XOR2X1TS U1101 ( .A(n5420), .B(n6021), .Y(n5421) );
XNOR2X2TS U1102 ( .A(n738), .B(n3363), .Y(n3026) );
XNOR2X1TS U1103 ( .A(n909), .B(n2221), .Y(n3128) );
XNOR2X2TS U1104 ( .A(n3349), .B(n3346), .Y(n3280) );
XNOR2X1TS U1105 ( .A(n753), .B(n2221), .Y(n3121) );
XNOR2X1TS U1106 ( .A(n4135), .B(n4134), .Y(n4414) );
XNOR2X2TS U1107 ( .A(n4585), .B(n4584), .Y(n4613) );
XOR2X2TS U1108 ( .A(n4099), .B(n4098), .Y(n4418) );
XNOR2X1TS U1109 ( .A(n4556), .B(n4130), .Y(n4421) );
CMPR32X2TS U1110 ( .A(n3382), .B(n3381), .C(n3380), .CO(n3393), .S(n3434) );
XOR2X2TS U1111 ( .A(n6770), .B(n6851), .Y(mult_x_24_n1551) );
AO21XLTS U1112 ( .A0(n2877), .A1(n2018), .B0(n2876), .Y(n3183) );
NAND2X1TS U1113 ( .A(n7630), .B(Sgf_operation_ODD1_Q_left[40]), .Y(n7620) );
INVX2TS U1114 ( .A(n6189), .Y(n6184) );
CLKXOR2X2TS U1115 ( .A(n4681), .B(n5567), .Y(n4690) );
NOR2X1TS U1116 ( .A(n7529), .B(n7938), .Y(n7717) );
OAI21X2TS U1117 ( .A0(n6043), .A1(n6061), .B0(n5405), .Y(n5834) );
CLKXOR2X2TS U1118 ( .A(n6738), .B(n7076), .Y(mult_x_24_n1444) );
CLKXOR2X2TS U1119 ( .A(n7077), .B(n8392), .Y(mult_x_24_n1442) );
OAI22X1TS U1120 ( .A0(n2320), .A1(n3279), .B0(n2319), .B1(n2762), .Y(n2337)
);
AOI222X1TS U1121 ( .A0(n6796), .A1(n875), .B0(n6806), .B1(n7008), .C0(n6805),
.C1(n910), .Y(n6743) );
OAI22X1TS U1122 ( .A0(n2306), .A1(n2809), .B0(n2499), .B1(n2772), .Y(n2456)
);
OAI22X1TS U1123 ( .A0(n2332), .A1(n932), .B0(n2318), .B1(n2715), .Y(n2338)
);
CLKXOR2X2TS U1124 ( .A(n6439), .B(n8392), .Y(mult_x_24_n1441) );
OAI21X2TS U1125 ( .A0(n6048), .A1(n4965), .B0(n6047), .Y(n6049) );
XOR2X1TS U1126 ( .A(n6856), .B(n6695), .Y(mult_x_24_n1625) );
XOR2X1TS U1127 ( .A(n6712), .B(n8445), .Y(mult_x_24_n1646) );
XOR2X1TS U1128 ( .A(n1221), .B(n6820), .Y(mult_x_24_n1616) );
XOR2X1TS U1129 ( .A(n6688), .B(n940), .Y(mult_x_24_n1624) );
XNOR2X1TS U1130 ( .A(n900), .B(Op_MX[26]), .Y(n3219) );
OAI21X1TS U1131 ( .A0(n6048), .A1(n5861), .B0(n5735), .Y(n5737) );
OAI21X1TS U1132 ( .A0(n4590), .A1(n4586), .B0(n4587), .Y(n4473) );
ADDFHX1TS U1133 ( .A(n2291), .B(n2290), .CI(n2289), .CO(n2299), .S(n2353) );
XNOR2X1TS U1134 ( .A(n914), .B(n3329), .Y(n3332) );
OAI21X1TS U1135 ( .A0(n6048), .A1(n5620), .B0(n5643), .Y(n5645) );
XNOR2X1TS U1136 ( .A(n3334), .B(n2583), .Y(n2366) );
XNOR2X1TS U1137 ( .A(n853), .B(n2997), .Y(n3032) );
XNOR2X1TS U1138 ( .A(n3287), .B(n3346), .Y(n2763) );
XNOR2X1TS U1139 ( .A(n3330), .B(n2939), .Y(n2722) );
XNOR2X2TS U1140 ( .A(n916), .B(n2784), .Y(n2807) );
XNOR2X1TS U1141 ( .A(n919), .B(n2468), .Y(n2367) );
XNOR2X2TS U1142 ( .A(n3303), .B(n2944), .Y(n2764) );
ADDFX2TS U1143 ( .A(n1535), .B(n1534), .CI(n1533), .CO(n1536), .S(n1527) );
XNOR2X1TS U1144 ( .A(n918), .B(n2632), .Y(n2364) );
XNOR2X2TS U1145 ( .A(n3330), .B(n2944), .Y(n2824) );
OAI21X1TS U1146 ( .A0(n6850), .A1(n7013), .B0(n6487), .Y(n6488) );
XNOR2X2TS U1147 ( .A(n3285), .B(n3074), .Y(n2875) );
ADDFHX2TS U1148 ( .A(n2828), .B(n2827), .CI(n2826), .CO(n2885), .S(n2842) );
OAI21X1TS U1149 ( .A0(n6793), .A1(n6792), .B0(n6791), .Y(n6795) );
XNOR2X1TS U1150 ( .A(n3410), .B(n2822), .Y(n2655) );
XNOR2X2TS U1151 ( .A(n753), .B(n3346), .Y(n3404) );
XNOR2X1TS U1152 ( .A(n919), .B(n2583), .Y(n2316) );
XNOR2X1TS U1153 ( .A(n3384), .B(n3275), .Y(n2774) );
XNOR2X2TS U1154 ( .A(n3384), .B(n3409), .Y(n3339) );
OAI21X1TS U1155 ( .A0(n7039), .A1(n6872), .B0(n4750), .Y(n4751) );
AOI21X1TS U1156 ( .A0(n4139), .A1(n4137), .B0(n4093), .Y(n4099) );
XNOR2X1TS U1157 ( .A(n3334), .B(n3275), .Y(n2723) );
XNOR2X1TS U1158 ( .A(n3276), .B(n2720), .Y(n2773) );
XNOR2X1TS U1159 ( .A(n3165), .B(n2784), .Y(n2649) );
AOI21X1TS U1160 ( .A0(n4599), .A1(n4598), .B0(n4597), .Y(n4604) );
CMPR32X2TS U1161 ( .A(n1666), .B(n1665), .C(n1664), .CO(n1696), .S(n1658) );
INVX6TS U1162 ( .A(n5002), .Y(n5792) );
INVX6TS U1163 ( .A(n6276), .Y(n6703) );
XOR2X1TS U1164 ( .A(n3699), .B(n5763), .Y(n3732) );
NOR2X1TS U1165 ( .A(n2629), .B(n3583), .Y(n2711) );
CMPR32X2TS U1166 ( .A(n1466), .B(n1465), .C(n1464), .CO(n1639), .S(n1486) );
BUFX3TS U1167 ( .A(n5491), .Y(n6035) );
INVX6TS U1168 ( .A(n3865), .Y(n5879) );
BUFX3TS U1169 ( .A(n4965), .Y(n6067) );
INVX2TS U1170 ( .A(n866), .Y(n868) );
INVX8TS U1171 ( .A(n1237), .Y(n6048) );
AOI222X1TS U1172 ( .A0(n6870), .A1(Op_MX[18]), .B0(n6834), .B1(n6790), .C0(
n6867), .C1(n6562), .Y(n6791) );
INVX4TS U1173 ( .A(n1036), .Y(n7535) );
INVX1TS U1174 ( .A(n4636), .Y(n4637) );
OAI22X1TS U1175 ( .A0(n2313), .A1(n3089), .B0(n2231), .B1(n3331), .Y(n2257)
);
NAND2X1TS U1176 ( .A(n7528), .B(n8057), .Y(n7938) );
AOI222X1TS U1177 ( .A0(n884), .A1(n875), .B0(n6727), .B1(Op_MX[11]), .C0(
n6914), .C1(n6904), .Y(n6721) );
OAI22X1TS U1178 ( .A0(n2265), .A1(n2976), .B0(n2330), .B1(n3006), .Y(n2290)
);
NAND2X2TS U1179 ( .A(n1155), .B(n1154), .Y(n6189) );
OAI22X1TS U1180 ( .A0(n1832), .A1(n2730), .B0(n1873), .B1(n2303), .Y(n1889)
);
NOR2X1TS U1181 ( .A(n7644), .B(n5060), .Y(n7630) );
XOR2X1TS U1182 ( .A(n6880), .B(n7490), .Y(mult_x_24_n1539) );
NOR2X2TS U1183 ( .A(n2825), .B(n3583), .Y(n3182) );
XNOR2X1TS U1184 ( .A(n3176), .B(n3227), .Y(n2332) );
OAI21X2TS U1185 ( .A0(n7006), .A1(n6973), .B0(n6972), .Y(n6975) );
OAI21X2TS U1186 ( .A0(n7063), .A1(n7062), .B0(n7061), .Y(n7065) );
XNOR2X1TS U1187 ( .A(n3364), .B(n3227), .Y(n2333) );
XNOR2X1TS U1188 ( .A(n914), .B(n2771), .Y(n2101) );
OAI22X1TS U1189 ( .A0(n2272), .A1(n3188), .B0(n2271), .B1(n3231), .Y(n2347)
);
XNOR2X1TS U1190 ( .A(n3359), .B(n3343), .Y(n2500) );
XNOR2X1TS U1191 ( .A(n3276), .B(n2254), .Y(n2262) );
XNOR2X1TS U1192 ( .A(n914), .B(n3363), .Y(n2967) );
OAI21XLTS U1193 ( .A0(n7014), .A1(n7005), .B0(n6719), .Y(n6720) );
XNOR2X1TS U1194 ( .A(n2954), .B(n3343), .Y(n2270) );
XNOR2X1TS U1195 ( .A(n2869), .B(n2650), .Y(n2557) );
OAI21X1TS U1196 ( .A0(n7086), .A1(n6763), .B0(n6467), .Y(n6468) );
XNOR2X1TS U1197 ( .A(n3165), .B(n1872), .Y(n1808) );
XNOR2X2TS U1198 ( .A(n860), .B(n2784), .Y(n2558) );
XNOR2X2TS U1199 ( .A(n921), .B(n2771), .Y(n2349) );
XNOR2X1TS U1200 ( .A(n900), .B(n2264), .Y(n2230) );
XNOR2X2TS U1201 ( .A(n922), .B(n2822), .Y(n2304) );
XNOR2X2TS U1202 ( .A(n915), .B(n2720), .Y(n2306) );
XNOR2X1TS U1203 ( .A(n2873), .B(n2881), .Y(n2334) );
XNOR2X1TS U1204 ( .A(n3582), .B(n2944), .Y(n2977) );
XNOR2X2TS U1205 ( .A(n753), .B(n3409), .Y(n2991) );
XNOR2X1TS U1206 ( .A(n3338), .B(n3383), .Y(n3418) );
XNOR2X2TS U1207 ( .A(n912), .B(n3409), .Y(n2968) );
XNOR2X1TS U1208 ( .A(n3223), .B(n1740), .Y(n1838) );
XNOR2X2TS U1209 ( .A(n913), .B(n2469), .Y(n1839) );
XNOR2X1TS U1210 ( .A(n3223), .B(n2254), .Y(n1492) );
XNOR2X1TS U1211 ( .A(n3364), .B(n2944), .Y(n2564) );
XNOR2X1TS U1212 ( .A(n916), .B(n2294), .Y(n2319) );
XNOR2X1TS U1213 ( .A(n916), .B(n1708), .Y(n1807) );
XNOR2X1TS U1214 ( .A(n3285), .B(n3275), .Y(n2292) );
CMPR32X2TS U1215 ( .A(n1163), .B(n1162), .C(n1161), .CO(n1164), .S(n1157) );
INVX6TS U1216 ( .A(n1219), .Y(n6832) );
BUFX8TS U1217 ( .A(n2008), .Y(n3349) );
INVX6TS U1218 ( .A(n6319), .Y(n6933) );
INVX6TS U1219 ( .A(n6437), .Y(n7063) );
BUFX8TS U1220 ( .A(n3226), .Y(n853) );
INVX2TS U1221 ( .A(n769), .Y(n836) );
BUFX8TS U1222 ( .A(n1964), .Y(n3338) );
INVX2TS U1223 ( .A(n1017), .Y(n6946) );
BUFX6TS U1224 ( .A(n3331), .Y(n3407) );
INVX8TS U1225 ( .A(n3828), .Y(n7006) );
INVX4TS U1226 ( .A(n2942), .Y(n3346) );
INVX8TS U1227 ( .A(n6265), .Y(n6769) );
NAND2XLTS U1228 ( .A(n5599), .B(n5597), .Y(n4701) );
INVX8TS U1229 ( .A(n4734), .Y(n6993) );
BUFX3TS U1230 ( .A(n5569), .Y(n6007) );
BUFX3TS U1231 ( .A(n4671), .Y(n6014) );
CLKINVX6TS U1232 ( .A(n5835), .Y(n6010) );
BUFX8TS U1233 ( .A(n2045), .Y(n2459) );
INVX4TS U1234 ( .A(n3051), .Y(n3409) );
BUFX3TS U1235 ( .A(n2877), .Y(n2809) );
BUFX8TS U1236 ( .A(n3419), .Y(n3336) );
BUFX6TS U1237 ( .A(n3276), .Y(n909) );
BUFX3TS U1238 ( .A(n6011), .Y(n5561) );
AOI222X1TS U1239 ( .A0(n6839), .A1(n8412), .B0(n7045), .B1(n7069), .C0(n7043), .C1(Op_MX[12]), .Y(n6604) );
CLKBUFX2TS U1240 ( .A(n3880), .Y(n5940) );
OAI22X2TS U1241 ( .A0(n1719), .A1(n3427), .B0(n1651), .B1(n3428), .Y(n1721)
);
NOR2X2TS U1242 ( .A(n8447), .B(FS_Module_state_reg[3]), .Y(n7480) );
CLKINVX3TS U1243 ( .A(n4113), .Y(n4126) );
NAND2X1TS U1244 ( .A(n7527), .B(n8108), .Y(n8057) );
AOI222X1TS U1245 ( .A0(n6817), .A1(n875), .B0(n6903), .B1(Op_MX[11]), .C0(
n6902), .C1(n6904), .Y(n6687) );
AOI222X1TS U1246 ( .A0(n5859), .A1(n814), .B0(n5712), .B1(Op_MY[36]), .C0(
n5751), .C1(n832), .Y(n5752) );
CLKXOR2X2TS U1247 ( .A(n5917), .B(n895), .Y(mult_x_23_n1429) );
AOI21X2TS U1248 ( .A0(n4983), .A1(n4982), .B0(n4981), .Y(n4988) );
NOR2X1TS U1249 ( .A(n7993), .B(n7523), .Y(n7939) );
BUFX3TS U1250 ( .A(n2815), .Y(n3303) );
INVX4TS U1251 ( .A(n2937), .Y(n3167) );
AOI21X2TS U1252 ( .A0(n1242), .A1(n1241), .B0(n1240), .Y(n1245) );
XNOR2X1TS U1253 ( .A(n2869), .B(n2264), .Y(n2265) );
XNOR2X1TS U1254 ( .A(n3276), .B(n2468), .Y(n2511) );
XNOR2X1TS U1255 ( .A(n3276), .B(n2583), .Y(n2654) );
XNOR2X1TS U1256 ( .A(n2954), .B(n2771), .Y(n2029) );
XNOR2X1TS U1257 ( .A(n911), .B(n2294), .Y(n2064) );
XNOR2X2TS U1258 ( .A(n906), .B(n2650), .Y(n2272) );
XNOR2X1TS U1259 ( .A(n3223), .B(n2070), .Y(n2062) );
XOR2X1TS U1260 ( .A(n4688), .B(n5567), .Y(n6086) );
XNOR2X2TS U1261 ( .A(n2789), .B(n3329), .Y(n2503) );
XNOR2X2TS U1262 ( .A(n3582), .B(n2469), .Y(n2561) );
XNOR2X2TS U1263 ( .A(n3410), .B(n2720), .Y(n2498) );
XNOR2X2TS U1264 ( .A(n862), .B(n2784), .Y(n2231) );
XNOR2X2TS U1265 ( .A(n915), .B(n3190), .Y(n2635) );
OAI21X1TS U1266 ( .A0(n7075), .A1(n6792), .B0(n6498), .Y(n6499) );
BUFX4TS U1267 ( .A(n888), .Y(n3279) );
INVX2TS U1268 ( .A(n3403), .Y(n889) );
XNOR2X1TS U1269 ( .A(n917), .B(n2632), .Y(n1610) );
XNOR2X2TS U1270 ( .A(n741), .B(n2650), .Y(n2271) );
XNOR2X1TS U1271 ( .A(n856), .B(n2254), .Y(n1544) );
AOI21X1TS U1272 ( .A0(n5600), .A1(n5599), .B0(n5598), .Y(n5605) );
OAI21X1TS U1273 ( .A0(n7086), .A1(n7085), .B0(n7084), .Y(n7088) );
NAND2X1TS U1274 ( .A(n4551), .B(Sgf_operation_ODD1_Q_middle[54]), .Y(n4636)
);
XNOR2X1TS U1275 ( .A(n3364), .B(n2881), .Y(n2017) );
CLKXOR2X2TS U1276 ( .A(n1072), .B(n1071), .Y(n1103) );
XNOR2X1TS U1277 ( .A(n3384), .B(n2822), .Y(n2470) );
XNOR2X1TS U1278 ( .A(n912), .B(n2720), .Y(n2656) );
XNOR2X1TS U1279 ( .A(n920), .B(n2822), .Y(n2600) );
XNOR2X1TS U1280 ( .A(n3359), .B(n2469), .Y(n1833) );
XNOR2X1TS U1281 ( .A(n2873), .B(n2653), .Y(n2025) );
XNOR2X1TS U1282 ( .A(n2789), .B(n3230), .Y(n2263) );
XNOR2X1TS U1283 ( .A(n2789), .B(n2944), .Y(n2099) );
XNOR2X1TS U1284 ( .A(n3287), .B(n3275), .Y(n2634) );
BUFX3TS U1285 ( .A(n822), .Y(n6813) );
BUFX3TS U1286 ( .A(n5075), .Y(n6869) );
BUFX3TS U1287 ( .A(n6531), .Y(n6960) );
BUFX6TS U1288 ( .A(n1313), .Y(n2878) );
BUFX3TS U1289 ( .A(n6237), .Y(n7085) );
BUFX8TS U1290 ( .A(n1313), .Y(n860) );
INVX6TS U1291 ( .A(n6453), .Y(n6855) );
INVX2TS U1292 ( .A(n1017), .Y(n7078) );
INVX4TS U1293 ( .A(n3426), .Y(n3275) );
INVX6TS U1294 ( .A(n6367), .Y(n6775) );
NOR2X1TS U1295 ( .A(n2535), .B(n3583), .Y(n2576) );
INVX4TS U1296 ( .A(n2786), .Y(n2583) );
INVX6TS U1297 ( .A(n6236), .Y(n6912) );
BUFX8TS U1298 ( .A(n2957), .Y(n912) );
BUFX8TS U1299 ( .A(n1785), .Y(n3287) );
BUFX3TS U1300 ( .A(n5665), .Y(n5978) );
BUFX3TS U1301 ( .A(n5620), .Y(n5985) );
BUFX3TS U1302 ( .A(n4749), .Y(n6872) );
BUFX3TS U1303 ( .A(n4805), .Y(n6763) );
BUFX8TS U1304 ( .A(n1447), .Y(n3368) );
BUFX8TS U1305 ( .A(n1447), .Y(n916) );
BUFX3TS U1306 ( .A(n5081), .Y(n6899) );
INVX6TS U1307 ( .A(n3623), .Y(n5905) );
BUFX3TS U1308 ( .A(n6639), .Y(n6990) );
NAND2X1TS U1309 ( .A(n6273), .B(n6272), .Y(n6274) );
BUFX4TS U1310 ( .A(n1895), .Y(n2368) );
BUFX16TS U1311 ( .A(n2950), .Y(n3276) );
INVX2TS U1312 ( .A(n3403), .Y(n890) );
BUFX4TS U1313 ( .A(n1973), .Y(n3410) );
BUFX6TS U1314 ( .A(n2008), .Y(n918) );
BUFX6TS U1315 ( .A(n3165), .Y(n856) );
INVX8TS U1316 ( .A(n6358), .Y(n7014) );
BUFX6TS U1317 ( .A(n2225), .Y(n3376) );
AOI222X1TS U1318 ( .A0(n7011), .A1(Op_MX[14]), .B0(n6834), .B1(n7069), .C0(
n5076), .C1(n7068), .Y(n6498) );
NOR2X1TS U1319 ( .A(n7700), .B(n4644), .Y(n5059) );
BUFX16TS U1320 ( .A(n3330), .Y(n921) );
OAI22X1TS U1321 ( .A0(n2582), .A1(n3154), .B0(n2536), .B1(n2966), .Y(n2575)
);
OR2X2TS U1322 ( .A(n4550), .B(Sgf_operation_ODD1_Q_middle[53]), .Y(n4551) );
BUFX8TS U1323 ( .A(n2225), .Y(n930) );
BUFX6TS U1324 ( .A(n6893), .Y(n7003) );
INVX4TS U1325 ( .A(n2876), .Y(n2720) );
INVX2TS U1326 ( .A(n5096), .Y(n866) );
AOI222X1TS U1327 ( .A0(n871), .A1(n6005), .B0(n873), .B1(Op_MY[36]), .C0(
n5801), .C1(n8385), .Y(n5803) );
CLKXOR2X2TS U1328 ( .A(n4716), .B(n892), .Y(n5136) );
BUFX8TS U1329 ( .A(n3176), .Y(n913) );
BUFX6TS U1330 ( .A(n2086), .Y(n3231) );
XNOR2X1TS U1331 ( .A(n2577), .B(n2871), .Y(n2616) );
XOR2X1TS U1332 ( .A(n3641), .B(n5763), .Y(n3701) );
XNOR2X1TS U1333 ( .A(n3358), .B(n2532), .Y(n2579) );
XNOR2X1TS U1334 ( .A(n3230), .B(n2580), .Y(n2088) );
XNOR2X2TS U1335 ( .A(n2580), .B(n3329), .Y(n2211) );
XOR2X1TS U1336 ( .A(n3800), .B(n5663), .Y(n4762) );
BUFX8TS U1337 ( .A(n3359), .Y(n2873) );
BUFX8TS U1338 ( .A(n3364), .Y(n2954) );
BUFX6TS U1339 ( .A(n1964), .Y(n920) );
XNOR2X1TS U1340 ( .A(n3668), .B(n5804), .Y(n5394) );
BUFX6TS U1341 ( .A(n2532), .Y(n2789) );
BUFX3TS U1342 ( .A(n6239), .Y(n7081) );
NAND2X1TS U1343 ( .A(n4528), .B(n4527), .Y(n4531) );
INVX12TS U1344 ( .A(n4525), .Y(n4488) );
BUFX8TS U1345 ( .A(n1462), .Y(n917) );
BUFX3TS U1346 ( .A(n822), .Y(n6902) );
BUFX6TS U1347 ( .A(n3880), .Y(n5899) );
NAND2X1TS U1348 ( .A(n6289), .B(n6288), .Y(n6290) );
NAND2X1TS U1349 ( .A(n6397), .B(n6396), .Y(n6398) );
INVX6TS U1350 ( .A(n5493), .Y(n5844) );
BUFX3TS U1351 ( .A(n6558), .Y(n6876) );
NAND2XLTS U1352 ( .A(n4982), .B(n4980), .Y(n4977) );
NAND2X1TS U1353 ( .A(n6302), .B(n6301), .Y(n6303) );
NAND2X1TS U1354 ( .A(n6434), .B(n6433), .Y(n6435) );
NAND2X1TS U1355 ( .A(n6262), .B(n6261), .Y(n6263) );
NAND2X1TS U1356 ( .A(n6297), .B(n6295), .Y(n1217) );
INVX4TS U1357 ( .A(n1067), .Y(n6865) );
BUFX4TS U1358 ( .A(n2532), .Y(n908) );
BUFX8TS U1359 ( .A(n6920), .Y(n7057) );
BUFX3TS U1360 ( .A(n6920), .Y(n7080) );
BUFX4TS U1361 ( .A(n6615), .Y(n7043) );
BUFX12TS U1362 ( .A(n1248), .Y(n5454) );
CLKBUFX2TS U1363 ( .A(n2578), .Y(n2956) );
CLKINVX6TS U1364 ( .A(n2709), .Y(n907) );
BUFX3TS U1365 ( .A(n4717), .Y(n6809) );
BUFX8TS U1366 ( .A(n1429), .Y(n3222) );
BUFX12TS U1367 ( .A(n1772), .Y(n3330) );
OAI21X2TS U1368 ( .A0(n740), .A1(n6299), .B0(n6298), .Y(n6304) );
NAND2BXLTS U1369 ( .AN(n2198), .B(n2650), .Y(n1991) );
OAI21X1TS U1370 ( .A0(n6824), .A1(n6788), .B0(n4715), .Y(n4716) );
INVX4TS U1371 ( .A(n5711), .Y(n5857) );
BUFX12TS U1372 ( .A(n2084), .Y(n3331) );
NAND2X2TS U1373 ( .A(n4992), .B(n4995), .Y(n4998) );
BUFX6TS U1374 ( .A(n1622), .Y(n934) );
BUFX4TS U1375 ( .A(n6239), .Y(n7058) );
BUFX12TS U1376 ( .A(n1882), .Y(n935) );
XNOR2X2TS U1377 ( .A(n2580), .B(n2944), .Y(n1884) );
XNOR2X1TS U1378 ( .A(n2223), .B(n3358), .Y(n2209) );
XNOR2X2TS U1379 ( .A(n2580), .B(n2997), .Y(n1994) );
XNOR2X2TS U1380 ( .A(n857), .B(n3227), .Y(n1624) );
BUFX3TS U1381 ( .A(n6238), .Y(n7060) );
XNOR2X2TS U1382 ( .A(n858), .B(n3343), .Y(n1651) );
XNOR2X1TS U1383 ( .A(n2198), .B(n3230), .Y(n1992) );
OAI22X1TS U1384 ( .A0(n1502), .A1(n7231), .B0(n929), .B1(n1810), .Y(n7223)
);
XNOR2X2TS U1385 ( .A(n6366), .B(n6365), .Y(n6367) );
XNOR2X2TS U1386 ( .A(n6452), .B(n6451), .Y(n6453) );
BUFX3TS U1387 ( .A(n2628), .Y(n1895) );
BUFX6TS U1388 ( .A(n5076), .Y(n6867) );
INVX6TS U1389 ( .A(n1127), .Y(n7039) );
BUFX3TS U1390 ( .A(n2627), .Y(n2559) );
INVX2TS U1391 ( .A(n793), .Y(n895) );
AND3X2TS U1392 ( .A(n4665), .B(n4664), .C(n1795), .Y(n5560) );
BUFX6TS U1393 ( .A(n6982), .Y(n7019) );
INVX4TS U1394 ( .A(n2692), .Y(n2650) );
INVX12TS U1395 ( .A(n733), .Y(n740) );
INVX2TS U1396 ( .A(n1018), .Y(n6861) );
BUFX6TS U1397 ( .A(n5096), .Y(n5830) );
BUFX6TS U1398 ( .A(n2097), .Y(n3350) );
NAND2X1TS U1399 ( .A(n6463), .B(n6462), .Y(n6464) );
BUFX3TS U1400 ( .A(n6544), .Y(n7023) );
BUFX4TS U1401 ( .A(n5668), .Y(n5698) );
BUFX3TS U1402 ( .A(n2627), .Y(n2053) );
NAND2X1TS U1403 ( .A(n6343), .B(n6424), .Y(n6344) );
NAND2X1TS U1404 ( .A(n6450), .B(n6449), .Y(n6451) );
NAND2X1TS U1405 ( .A(n6355), .B(n6354), .Y(n6356) );
BUFX3TS U1406 ( .A(n2628), .Y(n2560) );
NAND2XLTS U1407 ( .A(n6238), .B(n825), .Y(n4745) );
BUFX12TS U1408 ( .A(n2945), .Y(n3384) );
CLKINVX6TS U1409 ( .A(n2709), .Y(n906) );
INVX8TS U1410 ( .A(n3107), .Y(n3329) );
INVX6TS U1411 ( .A(n2942), .Y(n2939) );
BUFX6TS U1412 ( .A(n6238), .Y(n6923) );
BUFX4TS U1413 ( .A(n2877), .Y(n2100) );
BUFX6TS U1414 ( .A(n6512), .Y(n6962) );
BUFX6TS U1415 ( .A(n2788), .Y(n2045) );
INVX2TS U1416 ( .A(n5751), .Y(n5711) );
NAND3X2TS U1417 ( .A(n3626), .B(n3625), .C(n3624), .Y(n5493) );
BUFX4TS U1418 ( .A(n6405), .Y(n6473) );
OAI21X2TS U1419 ( .A0(n6461), .A1(n6231), .B0(n6230), .Y(n6235) );
AOI21X2TS U1420 ( .A0(n6269), .A1(n6245), .B0(n6244), .Y(n6246) );
BUFX4TS U1421 ( .A(n4675), .Y(n6012) );
INVX4TS U1422 ( .A(n3426), .Y(n2070) );
OAI21X2TS U1423 ( .A0(n2282), .A1(n819), .B0(n2280), .Y(n2286) );
OAI21X2TS U1424 ( .A0(n6461), .A1(n6447), .B0(n6446), .Y(n6452) );
BUFX6TS U1425 ( .A(n1429), .Y(n3179) );
BUFX3TS U1426 ( .A(n1500), .Y(n2477) );
CLKXOR2X2TS U1427 ( .A(n2206), .B(Op_MX[25]), .Y(n2207) );
NAND2X6TS U1428 ( .A(n4381), .B(n4141), .Y(n4144) );
BUFX4TS U1429 ( .A(n4672), .Y(n5564) );
BUFX6TS U1430 ( .A(n1882), .Y(n3415) );
BUFX12TS U1431 ( .A(n732), .Y(n2580) );
BUFX4TS U1432 ( .A(n1710), .Y(n2762) );
CLKINVX3TS U1433 ( .A(n4142), .Y(n4143) );
INVX6TS U1434 ( .A(n2937), .Y(n2871) );
CLKINVX6TS U1435 ( .A(n3107), .Y(n2784) );
XNOR2X2TS U1436 ( .A(n859), .B(n2771), .Y(n1482) );
AOI21X2TS U1437 ( .A0(n6392), .A1(n6297), .B0(n6296), .Y(n6298) );
OAI21X1TS U1438 ( .A0(n5043), .A1(n6841), .B0(n5008), .Y(n5009) );
BUFX3TS U1439 ( .A(n1478), .Y(n2016) );
XNOR2X1TS U1440 ( .A(n859), .B(n2632), .Y(n1502) );
XNOR2X2TS U1441 ( .A(n4721), .B(n6517), .Y(n6943) );
XNOR2X2TS U1442 ( .A(n858), .B(n2881), .Y(n1430) );
CLKXOR2X4TS U1443 ( .A(n1096), .B(n1095), .Y(n6900) );
BUFX3TS U1444 ( .A(n5081), .Y(n7025) );
XNOR2X1TS U1445 ( .A(n7232), .B(n2881), .Y(n1428) );
ADDHX1TS U1446 ( .A(n8404), .B(n3675), .CO(n3685), .S(n3676) );
XOR2X2TS U1447 ( .A(n3636), .B(n3635), .Y(n3697) );
INVX6TS U1448 ( .A(n1424), .Y(n2881) );
INVX6TS U1449 ( .A(n5667), .Y(n5928) );
INVX6TS U1450 ( .A(n4140), .Y(n4381) );
INVX4TS U1451 ( .A(n1007), .Y(n2632) );
INVX6TS U1452 ( .A(n2074), .Y(n3107) );
BUFX3TS U1453 ( .A(n3717), .Y(n5929) );
INVX8TS U1454 ( .A(n2534), .Y(n858) );
INVX6TS U1455 ( .A(n1615), .Y(n3426) );
BUFX3TS U1456 ( .A(n3796), .Y(n5960) );
CLKINVX6TS U1457 ( .A(n2786), .Y(n1708) );
INVX4TS U1458 ( .A(n1007), .Y(n2254) );
INVX6TS U1459 ( .A(n3220), .Y(n1872) );
NOR2BX2TS U1460 ( .AN(n5083), .B(n5082), .Y(n6558) );
NAND2X1TS U1461 ( .A(n7011), .B(n825), .Y(n4707) );
NAND2X1TS U1462 ( .A(n6736), .B(n825), .Y(n4806) );
NAND2X4TS U1463 ( .A(n2738), .B(n1324), .Y(n2788) );
NAND2X1TS U1464 ( .A(n1451), .B(n1812), .Y(n1500) );
BUFX6TS U1465 ( .A(n6065), .Y(n6019) );
BUFX8TS U1466 ( .A(n3129), .Y(n2937) );
BUFX6TS U1467 ( .A(n4749), .Y(n7013) );
BUFX6TS U1468 ( .A(n4675), .Y(n5922) );
BUFX6TS U1469 ( .A(n5081), .Y(n6984) );
BUFX6TS U1470 ( .A(n6454), .Y(n6440) );
INVX8TS U1471 ( .A(n3005), .Y(n2944) );
NAND2BX2TS U1472 ( .AN(n4742), .B(n4743), .Y(n6237) );
NAND2X6TS U1473 ( .A(n3031), .B(n1880), .Y(n1882) );
BUFX4TS U1474 ( .A(n5045), .Y(n6841) );
BUFX6TS U1475 ( .A(n1029), .Y(n2198) );
INVX3TS U1476 ( .A(n1352), .Y(n861) );
INVX4TS U1477 ( .A(n5877), .Y(n5660) );
INVX8TS U1478 ( .A(n2786), .Y(n2653) );
BUFX3TS U1479 ( .A(n1029), .Y(n7232) );
BUFX3TS U1480 ( .A(n6817), .Y(n6905) );
BUFX4TS U1481 ( .A(n732), .Y(n857) );
INVX4TS U1482 ( .A(n6281), .Y(n6392) );
INVX2TS U1483 ( .A(n2941), .Y(n2713) );
INVX8TS U1484 ( .A(n1718), .Y(n3403) );
INVX2TS U1485 ( .A(n6693), .Y(n823) );
BUFX6TS U1486 ( .A(n6589), .Y(n7045) );
CLKINVX6TS U1487 ( .A(n2876), .Y(n1740) );
INVX8TS U1488 ( .A(n2942), .Y(n2294) );
INVX6TS U1489 ( .A(n3005), .Y(n2264) );
BUFX12TS U1490 ( .A(n2215), .Y(n3301) );
CLKXOR2X2TS U1491 ( .A(n1619), .B(n1647), .Y(n1620) );
AOI21X1TS U1492 ( .A0(n2002), .A1(n2237), .B0(n2243), .Y(n1968) );
AOI21X1TS U1493 ( .A0(n6429), .A1(n6420), .B0(n6423), .Y(n6341) );
NOR2X2TS U1494 ( .A(n6279), .B(n6395), .Y(n6284) );
BUFX3TS U1495 ( .A(n5650), .Y(n5661) );
BUFX4TS U1496 ( .A(n4805), .Y(n6442) );
CLKINVX6TS U1497 ( .A(n3051), .Y(n2518) );
BUFX4TS U1498 ( .A(n5668), .Y(n5975) );
AOI21X1TS U1499 ( .A0(n2002), .A1(n2001), .B0(n2000), .Y(n2003) );
OAI21X1TS U1500 ( .A0(n3822), .A1(n6248), .B0(n6249), .Y(n3823) );
INVX12TS U1501 ( .A(n2281), .Y(n819) );
INVX6TS U1502 ( .A(n1876), .Y(n3051) );
NOR2X1TS U1503 ( .A(n1618), .B(n1617), .Y(n1619) );
NAND2X1TS U1504 ( .A(n1125), .B(n6230), .Y(n1126) );
NOR2X1TS U1505 ( .A(n1378), .B(n1377), .Y(n1380) );
NOR2X1TS U1506 ( .A(n5935), .B(n5942), .Y(n5455) );
BUFX6TS U1507 ( .A(n5045), .Y(n6999) );
NAND2XLTS U1508 ( .A(n3796), .B(n824), .Y(n3797) );
INVX4TS U1509 ( .A(n5789), .Y(n5964) );
BUFX3TS U1510 ( .A(n1112), .Y(n6889) );
BUFX3TS U1511 ( .A(n5748), .Y(n5742) );
INVX2TS U1512 ( .A(n5974), .Y(n5667) );
INVX4TS U1513 ( .A(n1518), .Y(n2786) );
NAND2X4TS U1514 ( .A(n6322), .B(n1216), .Y(n6280) );
NAND2BX2TS U1515 ( .AN(n4736), .B(n4737), .Y(n4749) );
BUFX3TS U1516 ( .A(n1080), .Y(n7005) );
INVX3TS U1517 ( .A(n2222), .Y(n2534) );
OAI21X2TS U1518 ( .A0(n1211), .A1(n6361), .B0(n1210), .Y(n1212) );
INVX4TS U1519 ( .A(n1794), .Y(n3005) );
INVX4TS U1520 ( .A(n1747), .Y(n2942) );
NAND2X2TS U1521 ( .A(n2278), .B(n2284), .Y(n2260) );
AOI21X2TS U1522 ( .A0(n2279), .A1(n2284), .B0(n2258), .Y(n2259) );
NOR2X1TS U1523 ( .A(n4502), .B(n4505), .Y(n4514) );
BUFX12TS U1524 ( .A(n2694), .Y(n3031) );
BUFX3TS U1525 ( .A(n4717), .Y(n6788) );
NAND2X2TS U1526 ( .A(n1697), .B(n1754), .Y(n1676) );
NAND2X2TS U1527 ( .A(n5935), .B(n5942), .Y(n5464) );
NAND2X2TS U1528 ( .A(n5939), .B(n5775), .Y(n5406) );
NOR2X2TS U1529 ( .A(n5771), .B(n5775), .Y(n3848) );
CLKXOR2X4TS U1530 ( .A(n1449), .B(n1448), .Y(n1007) );
BUFX3TS U1531 ( .A(n1424), .Y(n3220) );
BUFX3TS U1532 ( .A(n6644), .Y(n6992) );
NOR2X2TS U1533 ( .A(n1250), .B(n1249), .Y(n5398) );
NAND2X1TS U1534 ( .A(n4491), .B(n4490), .Y(n4504) );
NAND2X1TS U1535 ( .A(n1449), .B(n1448), .Y(n1415) );
BUFX6TS U1536 ( .A(Op_MY[48]), .Y(n5939) );
NOR2X1TS U1537 ( .A(n1417), .B(n3652), .Y(n1419) );
BUFX6TS U1538 ( .A(Op_MY[49]), .Y(n5775) );
NOR2X1TS U1539 ( .A(n3634), .B(n1401), .Y(n1403) );
BUFX6TS U1540 ( .A(Op_MY[47]), .Y(n5942) );
BUFX3TS U1541 ( .A(n1056), .Y(n6683) );
NOR2X1TS U1542 ( .A(n1797), .B(n1796), .Y(n1799) );
INVX3TS U1543 ( .A(n1755), .Y(n1697) );
NAND2BX1TS U1544 ( .AN(n1006), .B(n3652), .Y(n5766) );
OR2X2TS U1545 ( .A(Op_MY[51]), .B(Op_MY[24]), .Y(n2284) );
NOR2BX2TS U1546 ( .AN(n1114), .B(n1113), .Y(n6620) );
NOR2BX2TS U1547 ( .AN(n4709), .B(n4710), .Y(n6512) );
BUFX6TS U1548 ( .A(n1112), .Y(n6750) );
BUFX6TS U1549 ( .A(n4717), .Y(n6966) );
INVX1TS U1550 ( .A(n1965), .Y(n1976) );
NAND2X4TS U1551 ( .A(n1209), .B(n6420), .Y(n1211) );
INVX2TS U1552 ( .A(n1356), .Y(n947) );
NAND3X2TS U1553 ( .A(n3652), .B(n766), .C(n1006), .Y(n5789) );
NAND2BX2TS U1554 ( .AN(n3638), .B(n3639), .Y(n5861) );
NAND2X2TS U1555 ( .A(n2218), .B(Op_MX[25]), .Y(n2219) );
INVX12TS U1556 ( .A(n2281), .Y(n817) );
NAND2X4TS U1557 ( .A(n6391), .B(n3818), .Y(n3816) );
OAI21X2TS U1558 ( .A0(n1365), .A1(n1362), .B0(n1363), .Y(n1351) );
NAND2X4TS U1559 ( .A(n6457), .B(n1207), .Y(n6362) );
NAND2X2TS U1560 ( .A(n1370), .B(n1369), .Y(n1371) );
INVX2TS U1561 ( .A(n6693), .Y(n822) );
NOR2X2TS U1562 ( .A(n1353), .B(n3720), .Y(n1354) );
CLKXOR2X4TS U1563 ( .A(Op_MX[51]), .B(Op_MX[24]), .Y(n2204) );
XNOR2X2TS U1564 ( .A(Op_MY[18]), .B(Op_MY[19]), .Y(n4735) );
BUFX4TS U1565 ( .A(Op_MY[50]), .Y(n5771) );
XOR2X2TS U1566 ( .A(Op_MY[19]), .B(Op_MY[20]), .Y(n4737) );
OAI21X2TS U1567 ( .A0(n6819), .A1(n764), .B0(n1052), .Y(n1053) );
BUFX4TS U1568 ( .A(n6644), .Y(n6973) );
XOR2X2TS U1569 ( .A(Op_MX[48]), .B(Op_MX[49]), .Y(n3612) );
NAND2X2TS U1570 ( .A(n3619), .B(n3724), .Y(n4972) );
XNOR2X2TS U1571 ( .A(n1417), .B(n1414), .Y(n1416) );
XNOR2X2TS U1572 ( .A(n1394), .B(n1402), .Y(n1395) );
CLKXOR2X2TS U1573 ( .A(n1054), .B(n1073), .Y(n1055) );
OAI21X1TS U1574 ( .A0(n1672), .A1(n1753), .B0(n1757), .Y(n1699) );
NAND2X2TS U1575 ( .A(n6023), .B(n6038), .Y(n1251) );
NOR2X1TS U1576 ( .A(Op_MX[28]), .B(Op_MX[1]), .Y(n1414) );
NAND2X1TS U1577 ( .A(Op_MX[22]), .B(Op_MX[49]), .Y(n2072) );
NAND2X1TS U1578 ( .A(n3953), .B(n3952), .Y(n4197) );
NAND2X1TS U1579 ( .A(n3941), .B(n3940), .Y(n4186) );
NOR2X1TS U1580 ( .A(n1711), .B(n4655), .Y(n1712) );
INVX6TS U1581 ( .A(n773), .Y(n829) );
INVX6TS U1582 ( .A(n6053), .Y(n4966) );
AND2X2TS U1583 ( .A(Op_MX[27]), .B(Op_MX[0]), .Y(n1448) );
INVX6TS U1584 ( .A(n8444), .Y(n7503) );
NOR2X2TS U1585 ( .A(Op_MX[17]), .B(Op_MX[16]), .Y(n6333) );
BUFX8TS U1586 ( .A(Op_MY[46]), .Y(n5935) );
NOR2X4TS U1587 ( .A(n3704), .B(n3706), .Y(n1225) );
NAND2BX2TS U1588 ( .AN(n1114), .B(n1115), .Y(n6644) );
NOR2X1TS U1589 ( .A(n4591), .B(n4581), .Y(n4474) );
NAND2X2TS U1590 ( .A(Op_MY[51]), .B(Op_MY[24]), .Y(n2283) );
NAND2BX2TS U1591 ( .AN(n4709), .B(n4711), .Y(n4717) );
NAND2X4TS U1592 ( .A(n1951), .B(n1956), .Y(n2238) );
NAND2X2TS U1593 ( .A(n1744), .B(n1743), .Y(n1745) );
NOR2X2TS U1594 ( .A(n6945), .B(Op_MX[16]), .Y(n6414) );
NOR2X6TS U1595 ( .A(n6425), .B(n6432), .Y(n1209) );
NAND2X2TS U1596 ( .A(n1339), .B(n1338), .Y(n1370) );
BUFX8TS U1597 ( .A(n1130), .Y(n6681) );
XOR2X1TS U1598 ( .A(Op_MX[44]), .B(Op_MX[45]), .Y(n1878) );
XOR2X2TS U1599 ( .A(Op_MX[12]), .B(Op_MX[39]), .Y(n1617) );
BUFX6TS U1600 ( .A(n5087), .Y(n6796) );
NAND2X2TS U1601 ( .A(n833), .B(n6959), .Y(n6272) );
NAND2X1TS U1602 ( .A(n828), .B(n5963), .Y(n5602) );
NOR2X4TS U1603 ( .A(n6231), .B(n1205), .Y(n6457) );
OAI21X1TS U1604 ( .A0(n4123), .A1(n4122), .B0(n4121), .Y(n4439) );
BUFX12TS U1605 ( .A(Op_MY[43]), .Y(n6038) );
NOR2X4TS U1606 ( .A(n3812), .B(n6300), .Y(n6391) );
BUFX6TS U1607 ( .A(Op_MY[45]), .Y(n5906) );
NAND2X1TS U1608 ( .A(Op_MX[18]), .B(Op_MX[45]), .Y(n1874) );
NAND2X1TS U1609 ( .A(Op_MX[10]), .B(Op_MX[37]), .Y(n1358) );
NAND2X1TS U1610 ( .A(Op_MX[8]), .B(Op_MX[35]), .Y(n1338) );
NAND2X1TS U1611 ( .A(n4109), .B(n4108), .Y(n4122) );
NAND2X1TS U1612 ( .A(n4462), .B(n4461), .Y(n4592) );
NAND2X1TS U1613 ( .A(n4129), .B(n4128), .Y(n4553) );
NAND2X1TS U1614 ( .A(n4467), .B(n4466), .Y(n4587) );
NAND2X1TS U1615 ( .A(n4092), .B(n4091), .Y(n4136) );
INVX6TS U1616 ( .A(n1020), .Y(n7500) );
NOR2X4TS U1617 ( .A(n4711), .B(n4709), .Y(n5087) );
OAI21X2TS U1618 ( .A0(Op_MX[8]), .A1(Op_MX[35]), .B0(Op_MX[7]), .Y(n1339) );
NAND2X2TS U1619 ( .A(n4001), .B(n4000), .Y(n4378) );
NOR2X2TS U1620 ( .A(n4453), .B(n4452), .Y(n4568) );
INVX8TS U1621 ( .A(n1009), .Y(n7490) );
NOR2X2TS U1622 ( .A(Op_MX[5]), .B(Op_MX[32]), .Y(n1396) );
NOR2X2TS U1623 ( .A(Op_MX[15]), .B(Op_MX[42]), .Y(n1742) );
NAND2X2TS U1624 ( .A(n3986), .B(n3985), .Y(n4344) );
NAND2X2TS U1625 ( .A(n3972), .B(n3971), .Y(n4365) );
NAND2X2TS U1626 ( .A(Op_MX[15]), .B(Op_MX[16]), .Y(n6415) );
NAND2X2TS U1627 ( .A(Op_MX[17]), .B(Op_MX[16]), .Y(n6334) );
NAND2X2TS U1628 ( .A(Op_MX[51]), .B(Op_MX[24]), .Y(n2196) );
NOR2X6TS U1629 ( .A(n6785), .B(n7056), .Y(n6425) );
NOR2X4TS U1630 ( .A(n1144), .B(n1146), .Y(n1120) );
NOR2X4TS U1631 ( .A(n5892), .B(n5901), .Y(n3706) );
NOR2X2TS U1632 ( .A(n3652), .B(n1006), .Y(n3662) );
NOR2X2TS U1633 ( .A(n4467), .B(n4466), .Y(n4586) );
NAND2BX2TS U1634 ( .AN(n1058), .B(n1059), .Y(n1130) );
BUFX6TS U1635 ( .A(Op_MY[42]), .Y(n6023) );
NAND2X4TS U1636 ( .A(n7079), .B(n826), .Y(n6230) );
NAND2X2TS U1637 ( .A(n1315), .B(n1314), .Y(n1398) );
OR2X4TS U1638 ( .A(n6584), .B(n6897), .Y(n1000) );
BUFX3TS U1639 ( .A(Op_MY[35]), .Y(n7508) );
XOR2X2TS U1640 ( .A(Op_MY[10]), .B(Op_MY[11]), .Y(n5036) );
BUFX12TS U1641 ( .A(Op_MY[40]), .Y(n5963) );
NOR2X2TS U1642 ( .A(n4470), .B(n4469), .Y(n4478) );
NOR2X6TS U1643 ( .A(n6952), .B(n6484), .Y(n6395) );
BUFX4TS U1644 ( .A(Op_MX[24]), .Y(n6959) );
BUFX4TS U1645 ( .A(Op_MY[38]), .Y(n6016) );
NAND2X4TS U1646 ( .A(n902), .B(n3632), .Y(n3647) );
NOR2X6TS U1647 ( .A(n7008), .B(n6753), .Y(n6448) );
XOR2X2TS U1648 ( .A(Op_MX[32]), .B(Op_MX[33]), .Y(n3634) );
NAND2X2TS U1649 ( .A(n6829), .B(n6930), .Y(n6315) );
NOR2X4TS U1650 ( .A(n1777), .B(n1780), .Y(n1951) );
NOR2X2TS U1651 ( .A(n4455), .B(n4454), .Y(n4578) );
BUFX6TS U1652 ( .A(Op_MX[22]), .Y(n6484) );
BUFX3TS U1653 ( .A(Op_MY[29]), .Y(n8374) );
NOR2X4TS U1654 ( .A(n3974), .B(n3973), .Y(n4336) );
NOR2X4TS U1655 ( .A(Op_MY[43]), .B(Op_MY[16]), .Y(n1777) );
NOR2X4TS U1656 ( .A(n3972), .B(n3971), .Y(n4364) );
NAND2X2TS U1657 ( .A(n4057), .B(n4056), .Y(n4280) );
BUFX8TS U1658 ( .A(Op_MX[11]), .Y(n7008) );
NAND2X6TS U1659 ( .A(Op_MY[43]), .B(Op_MY[16]), .Y(n1779) );
NAND2X2TS U1660 ( .A(Op_MY[47]), .B(Op_MY[20]), .Y(n1975) );
NAND2X2TS U1661 ( .A(n4069), .B(n4068), .Y(n4369) );
BUFX6TS U1662 ( .A(Op_MX[8]), .Y(n7079) );
NOR2X1TS U1663 ( .A(n4001), .B(n4000), .Y(n4357) );
NAND2X2TS U1664 ( .A(Op_MY[50]), .B(Op_MY[23]), .Y(n2239) );
CLKXOR2X2TS U1665 ( .A(Op_MY[5]), .B(Op_MY[4]), .Y(n1059) );
INVX12TS U1666 ( .A(n6974), .Y(n7040) );
NAND2X4TS U1667 ( .A(n6897), .B(n905), .Y(n1074) );
BUFX16TS U1668 ( .A(Op_MX[9]), .Y(n6958) );
BUFX16TS U1669 ( .A(Op_MX[12]), .Y(n7068) );
BUFX12TS U1670 ( .A(Op_MX[13]), .Y(n7056) );
NAND2X2TS U1671 ( .A(n6897), .B(Op_MX[3]), .Y(n1075) );
NOR2X2TS U1672 ( .A(n4069), .B(n4068), .Y(n4324) );
BUFX6TS U1673 ( .A(Op_MX[15]), .Y(n6945) );
BUFX6TS U1674 ( .A(Op_MX[10]), .Y(n910) );
BUFX12TS U1675 ( .A(Op_MY[34]), .Y(n5901) );
NOR2X4TS U1676 ( .A(Op_MY[50]), .B(Op_MY[23]), .Y(n2241) );
BUFX6TS U1677 ( .A(Op_MX[1]), .Y(n6243) );
NOR2X4TS U1678 ( .A(Op_MY[49]), .B(Op_MY[22]), .Y(n2236) );
NAND2X2TS U1679 ( .A(n6584), .B(n6863), .Y(n1093) );
BUFX6TS U1680 ( .A(Op_MX[20]), .Y(n877) );
NOR2X2TS U1681 ( .A(n6874), .B(n6863), .Y(n1063) );
NAND2X2TS U1682 ( .A(n6874), .B(n6863), .Y(n1064) );
BUFX4TS U1683 ( .A(Op_MX[10]), .Y(n6753) );
BUFX12TS U1684 ( .A(Op_MX[11]), .Y(n827) );
NAND2X1TS U1685 ( .A(n8414), .B(n826), .Y(n1147) );
CMPR32X2TS U1686 ( .A(Sgf_operation_ODD1_Q_middle[42]), .B(n7612), .C(n4449),
.CO(n4456), .S(n4455) );
CMPR32X2TS U1687 ( .A(Sgf_operation_ODD1_Q_middle[25]), .B(n3939), .C(n3938),
.CO(n3940), .S(n3935) );
INVX6TS U1688 ( .A(n800), .Y(n826) );
CMPR32X2TS U1689 ( .A(Sgf_operation_ODD1_Q_middle[26]), .B(n3937), .C(n3936),
.CO(n3942), .S(n3941) );
OAI21X2TS U1690 ( .A0(Op_MX[12]), .A1(Op_MX[39]), .B0(Op_MX[11]), .Y(n1614)
);
NAND2X2TS U1691 ( .A(Op_MX[12]), .B(Op_MX[39]), .Y(n1613) );
INVX3TS U1692 ( .A(n755), .Y(n756) );
NAND2X4TS U1693 ( .A(n1453), .B(n1458), .Y(n1755) );
BUFX12TS U1694 ( .A(Op_MX[4]), .Y(n6863) );
BUFX6TS U1695 ( .A(Op_MX[0]), .Y(n825) );
BUFX12TS U1696 ( .A(Op_MX[14]), .Y(n8412) );
BUFX6TS U1697 ( .A(Op_MX[2]), .Y(n6897) );
BUFX6TS U1698 ( .A(Op_MX[1]), .Y(n905) );
NOR2X4TS U1699 ( .A(n1668), .B(n1671), .Y(n1754) );
NAND2X4TS U1700 ( .A(Op_MY[29]), .B(Op_MY[2]), .Y(n1363) );
NAND2X4TS U1701 ( .A(Op_MY[41]), .B(Op_MY[14]), .Y(n1757) );
NOR2X6TS U1702 ( .A(n755), .B(Op_MY[5]), .Y(n1389) );
NOR2X6TS U1703 ( .A(Op_MY[34]), .B(Op_MY[7]), .Y(n1327) );
NOR2X6TS U1704 ( .A(Op_MY[40]), .B(Op_MY[13]), .Y(n1671) );
NOR2X6TS U1705 ( .A(Op_MY[38]), .B(Op_MY[11]), .Y(n1455) );
NOR2X6TS U1706 ( .A(Op_MY[28]), .B(Op_MY[1]), .Y(n1373) );
NAND2X2TS U1707 ( .A(Op_MY[37]), .B(Op_MY[10]), .Y(n1456) );
NOR2X6TS U1708 ( .A(Op_MY[29]), .B(Op_MY[2]), .Y(n1362) );
NAND2X2TS U1709 ( .A(Op_MY[40]), .B(Op_MY[13]), .Y(n1669) );
NAND2X2TS U1710 ( .A(Op_MY[38]), .B(Op_MY[11]), .Y(n1454) );
NOR2X4TS U1711 ( .A(Op_MY[39]), .B(Op_MY[12]), .Y(n1668) );
NOR2X4TS U1712 ( .A(Op_MY[31]), .B(Op_MY[4]), .Y(n1336) );
NOR2X4TS U1713 ( .A(Op_MY[42]), .B(Op_MY[15]), .Y(n1758) );
INVX2TS U1714 ( .A(n1754), .Y(n1673) );
NAND2X2TS U1715 ( .A(Op_MY[42]), .B(Op_MY[15]), .Y(n1756) );
NAND2X1TS U1716 ( .A(n1441), .B(n1456), .Y(n1437) );
XNOR2X2TS U1717 ( .A(n741), .B(n4730), .Y(n2582) );
NOR2X2TS U1718 ( .A(Op_MX[13]), .B(Op_MX[40]), .Y(n1648) );
NOR2X2TS U1719 ( .A(n877), .B(n6952), .Y(n6300) );
INVX4TS U1720 ( .A(n6361), .Y(n6429) );
OAI22X1TS U1721 ( .A0(n2087), .A1(n3188), .B0(n2086), .B1(n1992), .Y(n2089)
);
BUFX6TS U1722 ( .A(n1029), .Y(n2223) );
AOI22X1TS U1723 ( .A0(n7010), .A1(n5041), .B0(n6870), .B1(n905), .Y(n4705)
);
NOR2X2TS U1724 ( .A(n8414), .B(n826), .Y(n1146) );
AO21X2TS U1725 ( .A0(n2788), .A1(n2787), .B0(n2786), .Y(n2828) );
XNOR2X2TS U1726 ( .A(n920), .B(n2720), .Y(n2499) );
XNOR2X1TS U1727 ( .A(n3330), .B(n2881), .Y(n2305) );
INVX4TS U1728 ( .A(n3220), .Y(n2822) );
BUFX8TS U1729 ( .A(n1785), .Y(n922) );
CLKXOR2X2TS U1730 ( .A(n1354), .B(n1369), .Y(n1355) );
AOI222X1TS U1731 ( .A0(n6964), .A1(n6884), .B0(n6786), .B1(n7020), .C0(n6531), .C1(n7018), .Y(n4722) );
OAI21X2TS U1732 ( .A0(n6461), .A1(n6342), .B0(n6341), .Y(n6345) );
OAI21X1TS U1733 ( .A0(n4484), .A1(n4483), .B0(n4482), .Y(n4485) );
XNOR2X1TS U1734 ( .A(n3176), .B(n2944), .Y(n2652) );
XNOR2X1TS U1735 ( .A(n918), .B(n2720), .Y(n2588) );
XNOR2X2TS U1736 ( .A(n917), .B(n3383), .Y(n2757) );
INVX2TS U1737 ( .A(n3176), .Y(n2938) );
XNOR2X2TS U1738 ( .A(n3410), .B(n3275), .Y(n2898) );
XNOR2X2TS U1739 ( .A(n3276), .B(n3190), .Y(n3229) );
XNOR2X1TS U1740 ( .A(n3276), .B(n2822), .Y(n2882) );
BUFX6TS U1741 ( .A(n1462), .Y(n3285) );
NAND2X1TS U1742 ( .A(n6316), .B(n6315), .Y(n6317) );
AOI222X1TS U1743 ( .A0(n6964), .A1(n8412), .B0(n6786), .B1(n7069), .C0(n6805), .C1(n7068), .Y(n6532) );
CLKINVX6TS U1744 ( .A(n6019), .Y(n880) );
NOR2X2TS U1745 ( .A(n4665), .B(n4664), .Y(n4675) );
INVX4TS U1746 ( .A(n5594), .Y(n5997) );
BUFX12TS U1747 ( .A(n1973), .Y(n919) );
OAI22X1TS U1748 ( .A0(n2480), .A1(n3279), .B0(n2520), .B1(n3401), .Y(n2486)
);
ADDFX2TS U1749 ( .A(n2516), .B(n2515), .CI(n2514), .CO(n2542), .S(n2507) );
OAI22X1TS U1750 ( .A0(n2302), .A1(n2368), .B0(n2311), .B1(n2510), .Y(n2310)
);
OAI22X1TS U1751 ( .A0(n2305), .A1(n2016), .B0(n2335), .B1(n3222), .Y(n2340)
);
XNOR2X1TS U1752 ( .A(n3384), .B(n2583), .Y(n2365) );
XNOR2X1TS U1753 ( .A(n919), .B(n2287), .Y(n2009) );
OAI22X1TS U1754 ( .A0(n2029), .A1(n2100), .B0(n2039), .B1(n2772), .Y(n2125)
);
ADDFX2TS U1755 ( .A(n1887), .B(n1886), .CI(n1885), .CO(n2026), .S(n1893) );
XNOR2X1TS U1756 ( .A(n3223), .B(n1872), .Y(n1832) );
OAI21XLTS U1757 ( .A0(n7086), .A1(n6872), .B0(n6504), .Y(n6505) );
BUFX3TS U1758 ( .A(n6995), .Y(n6843) );
NAND2X1TS U1759 ( .A(n1148), .B(n1147), .Y(n1149) );
AOI22X1TS U1760 ( .A0(n5701), .A1(n902), .B0(n5668), .B1(n4966), .Y(n3695)
);
CLKINVX3TS U1761 ( .A(n5711), .Y(n5732) );
OAI22X1TS U1762 ( .A0(n2958), .A1(n3350), .B0(n2977), .B1(n3430), .Y(n2985)
);
BUFX3TS U1763 ( .A(n2097), .Y(n3432) );
OAI22X1TS U1764 ( .A0(n3289), .A1(n935), .B0(n3339), .B1(n3413), .Y(n3327)
);
OAI22X1TS U1765 ( .A0(n2774), .A1(n934), .B0(n2818), .B1(n3344), .Y(n2831)
);
BUFX6TS U1766 ( .A(n1751), .Y(n2839) );
BUFX8TS U1767 ( .A(n1478), .Y(n3178) );
BUFX12TS U1768 ( .A(n6239), .Y(n6921) );
AOI222X1TS U1769 ( .A0(n6870), .A1(n6847), .B0(n6834), .B1(n6846), .C0(n6491), .C1(n6930), .Y(n6487) );
BUFX3TS U1770 ( .A(n4749), .Y(n6792) );
OAI21X1TS U1771 ( .A0(n6984), .A1(n764), .B0(n5039), .Y(n5040) );
BUFX4TS U1772 ( .A(n3880), .Y(n6060) );
BUFX4TS U1773 ( .A(n4672), .Y(n6011) );
CLKINVX3TS U1774 ( .A(n5493), .Y(n5884) );
CLKINVX3TS U1775 ( .A(n973), .Y(n5902) );
CLKINVX3TS U1776 ( .A(n5789), .Y(n6077) );
OAI21XLTS U1777 ( .A0(n979), .A1(n6014), .B0(n5558), .Y(n5559) );
BUFX3TS U1778 ( .A(n5701), .Y(n5976) );
ADDHX1TS U1779 ( .A(n1653), .B(n1652), .CO(n1720), .S(n1666) );
XNOR2X1TS U1780 ( .A(n3223), .B(n1611), .Y(n1439) );
CLKXOR2X2TS U1781 ( .A(n4804), .B(n7076), .Y(n5208) );
XNOR2X2TS U1782 ( .A(n1150), .B(n1149), .Y(n1151) );
OAI21XLTS U1783 ( .A0(n6036), .A1(n5978), .B0(n5699), .Y(n5700) );
OAI21XLTS U1784 ( .A0(n5931), .A1(n6007), .B0(n5616), .Y(n5617) );
INVX2TS U1785 ( .A(n4359), .Y(n4361) );
NAND2X1TS U1786 ( .A(n3990), .B(n3989), .Y(n4353) );
OAI21X2TS U1787 ( .A0(n4307), .A1(n4306), .B0(n4305), .Y(n4313) );
NAND2X1TS U1788 ( .A(n4536), .B(n4535), .Y(n4538) );
OAI21X2TS U1789 ( .A0(n4488), .A1(n4515), .B0(n4522), .Y(n4495) );
AOI21X2TS U1790 ( .A0(n8004), .A1(n4423), .B0(n4422), .Y(n4424) );
NAND2X1TS U1791 ( .A(n3957), .B(n3956), .Y(n4206) );
OAI22X1TS U1792 ( .A0(n2991), .A1(n3415), .B0(n2998), .B1(n3413), .Y(n3001)
);
BUFX12TS U1793 ( .A(n2946), .Y(n3089) );
OAI22X1TS U1794 ( .A0(n1809), .A1(n2730), .B0(n1808), .B1(n2303), .Y(n1860)
);
INVX6TS U1795 ( .A(n6253), .Y(n6967) );
BUFX4TS U1796 ( .A(n6237), .Y(n7062) );
XOR2X1TS U1797 ( .A(n7065), .B(n7064), .Y(n7066) );
OAI21X1TS U1798 ( .A0(n729), .A1(n6792), .B0(n6494), .Y(n6495) );
OAI21X1TS U1799 ( .A0(n6918), .A1(n6841), .B0(n6598), .Y(n6599) );
BUFX3TS U1800 ( .A(n6644), .Y(n7038) );
OAI21XLTS U1801 ( .A0(n6008), .A1(n6067), .B0(n5972), .Y(n5973) );
OAI21XLTS U1802 ( .A0(n6008), .A1(n6014), .B0(n5552), .Y(n5553) );
XNOR2X1TS U1803 ( .A(n859), .B(n2469), .Y(n1511) );
XOR2X1TS U1804 ( .A(n6744), .B(n835), .Y(mult_x_24_n1504) );
OAI21XLTS U1805 ( .A0(n7086), .A1(n7049), .B0(n6609), .Y(n6610) );
OAI21X1TS U1806 ( .A0(n8283), .A1(n8289), .B0(n8284), .Y(n4386) );
NOR2XLTS U1807 ( .A(n5057), .B(n5056), .Y(n5058) );
NOR2X2TS U1808 ( .A(n7833), .B(n7835), .Y(n4624) );
OAI21X2TS U1809 ( .A0(n8001), .A1(n4425), .B0(n4424), .Y(n4426) );
NOR2XLTS U1810 ( .A(n8451), .B(n8449), .Y(n7515) );
OAI21X1TS U1811 ( .A0(n3570), .A1(n7301), .B0(n3569), .Y(n3571) );
OAI21XLTS U1812 ( .A0(n6993), .A1(n7074), .B0(n6376), .Y(n6377) );
INVX2TS U1813 ( .A(n1017), .Y(n7087) );
CLKINVX3TS U1814 ( .A(n1017), .Y(n7064) );
XOR2X1TS U1815 ( .A(n6483), .B(n6861), .Y(mult_x_24_n1463) );
INVX6TS U1816 ( .A(n5468), .Y(n5896) );
CLKINVX3TS U1817 ( .A(n1035), .Y(n5926) );
XOR2X1TS U1818 ( .A(n5555), .B(n737), .Y(mult_x_23_n1335) );
OAI21XLTS U1819 ( .A0(n5931), .A1(n5978), .B0(n5930), .Y(n5932) );
CLKINVX3TS U1820 ( .A(n1038), .Y(n7018) );
XOR2X1TS U1821 ( .A(n4209), .B(n4208), .Y(n4407) );
NOR2XLTS U1822 ( .A(Sgf_normalized_result[4]), .B(Sgf_normalized_result[5]),
.Y(n7527) );
XNOR2X2TS U1823 ( .A(n4340), .B(n4339), .Y(n4388) );
NAND2X1TS U1824 ( .A(n5059), .B(n5058), .Y(n7644) );
CLKXOR2X2TS U1825 ( .A(n4590), .B(n4589), .Y(n4614) );
NOR2X1TS U1826 ( .A(n4398), .B(Sgf_operation_ODD1_Q_right[50]), .Y(n8340) );
OA21X1TS U1827 ( .A0(n3591), .A1(n3597), .B0(n3598), .Y(n792) );
INVX4TS U1828 ( .A(n4825), .Y(n7295) );
AOI21X1TS U1829 ( .A0(n3807), .A1(n3806), .B0(n3805), .Y(n5118) );
NAND2X2TS U1830 ( .A(n1182), .B(n7094), .Y(n1184) );
CMPR42X1TS U1831 ( .A(mult_x_23_n1277), .B(mult_x_23_n1329), .C(
mult_x_23_n755), .D(mult_x_23_n765), .ICI(mult_x_23_n762), .S(
mult_x_23_n753), .ICO(mult_x_23_n751), .CO(mult_x_23_n752) );
OAI21X1TS U1832 ( .A0(n7424), .A1(n7423), .B0(n7422), .Y(n7425) );
NOR2X2TS U1833 ( .A(n7416), .B(n7345), .Y(n7347) );
NOR2X4TS U1834 ( .A(n2450), .B(n2449), .Y(n7437) );
INVX2TS U1835 ( .A(n7151), .Y(n2186) );
OA21X2TS U1836 ( .A0(n7196), .A1(n1569), .B0(n7192), .Y(n1570) );
NOR2X6TS U1837 ( .A(mult_x_24_n845), .B(mult_x_24_n856), .Y(n5232) );
INVX2TS U1838 ( .A(n845), .Y(n847) );
NAND2X1TS U1839 ( .A(n4621), .B(Sgf_operation_ODD1_Q_left[22]), .Y(n7846) );
INVX2TS U1840 ( .A(n7919), .Y(n7921) );
NOR2X2TS U1841 ( .A(n4412), .B(Sgf_operation_ODD1_Q_left[4]), .Y(n8099) );
INVX2TS U1842 ( .A(n7652), .Y(n7653) );
NAND2X2TS U1843 ( .A(n7480), .B(n8446), .Y(n7533) );
NOR2X6TS U1844 ( .A(n3776), .B(n5154), .Y(n3778) );
NOR2X4TS U1845 ( .A(n4908), .B(n4912), .Y(n3765) );
NOR2X4TS U1846 ( .A(mult_x_23_n813), .B(mult_x_23_n823), .Y(n5300) );
NAND2X4TS U1847 ( .A(n3526), .B(n3525), .Y(n7405) );
INVX2TS U1848 ( .A(n4692), .Y(n7321) );
NAND2X1TS U1849 ( .A(n7417), .B(n7347), .Y(n7349) );
NAND2X2TS U1850 ( .A(n2190), .B(n2189), .Y(n7138) );
OAI21XLTS U1851 ( .A0(n7397), .A1(n7396), .B0(n7395), .Y(n7398) );
INVX2TS U1852 ( .A(n1733), .Y(n7170) );
OR2X1TS U1853 ( .A(n1516), .B(n1515), .Y(n7210) );
INVX2TS U1854 ( .A(n6136), .Y(n6132) );
NOR2XLTS U1855 ( .A(n7690), .B(n8464), .Y(n7681) );
OAI21XLTS U1856 ( .A0(n8305), .A1(n8301), .B0(n8302), .Y(n8299) );
NAND2X2TS U1857 ( .A(n7536), .B(n7535), .Y(n7547) );
INVX2TS U1858 ( .A(n7860), .Y(n7875) );
INVX4TS U1859 ( .A(n8087), .Y(n8103) );
NOR2XLTS U1860 ( .A(n7671), .B(n8451), .Y(n7665) );
NOR2XLTS U1861 ( .A(n8015), .B(n8467), .Y(n7995) );
NAND2X4TS U1862 ( .A(n2921), .B(n7373), .Y(n7287) );
OR2X4TS U1863 ( .A(n7330), .B(n3541), .Y(n1023) );
OA21X2TS U1864 ( .A0(n5164), .A1(n3903), .B0(n3902), .Y(n3904) );
NAND2X4TS U1865 ( .A(n1939), .B(n1938), .Y(n7385) );
NAND2X1TS U1866 ( .A(mult_x_24_n698), .B(mult_x_24_n701), .Y(n5022) );
NAND2X2TS U1867 ( .A(n1276), .B(n1279), .Y(n5027) );
OR2X1TS U1868 ( .A(mult_x_23_n639), .B(mult_x_23_n641), .Y(n5273) );
AOI21X1TS U1869 ( .A0(n5186), .A1(n5185), .B0(n5184), .Y(n5187) );
AOI21X1TS U1870 ( .A0(n4790), .A1(n4779), .B0(n4778), .Y(n4780) );
INVX2TS U1871 ( .A(n7127), .Y(n7436) );
OAI21XLTS U1872 ( .A0(n7160), .A1(n7162), .B0(n7161), .Y(n7167) );
BUFX3TS U1873 ( .A(n1029), .Y(n929) );
BUFX4TS U1874 ( .A(n6092), .Y(n4893) );
OAI21XLTS U1875 ( .A0(n6951), .A1(n6947), .B0(n6948), .Y(n6145) );
XNOR2X2TS U1876 ( .A(n7685), .B(n7684), .Y(n7686) );
XNOR2X1TS U1877 ( .A(n8067), .B(n8066), .Y(n8068) );
INVX2TS U1878 ( .A(n8433), .Y(n8186) );
INVX4TS U1879 ( .A(n6093), .Y(n7108) );
NAND2X2TS U1880 ( .A(n7485), .B(FS_Module_state_reg[3]), .Y(n7534) );
CLKINVX3TS U1881 ( .A(n803), .Y(n824) );
CLKINVX3TS U1882 ( .A(n8433), .Y(n7768) );
CLKINVX3TS U1883 ( .A(n8365), .Y(n7496) );
CLKINVX3TS U1884 ( .A(n8372), .Y(n7505) );
INVX2TS U1885 ( .A(n1035), .Y(n737) );
OAI21X2TS U1886 ( .A0(n7430), .A1(n7310), .B0(n7309), .Y(n7314) );
XOR2X1TS U1887 ( .A(n743), .B(n7250), .Y(Sgf_operation_ODD1_middle_N34) );
OAI31X1TS U1888 ( .A0(FS_Module_state_reg[1]), .A1(n7488), .A2(n8446), .B0(
n7487), .Y(n712) );
XOR2X1TS U1889 ( .A(n5271), .B(n4765), .Y(Sgf_operation_ODD1_left_N35) );
OR2X1TS U1890 ( .A(exp_oper_result[11]), .B(Exp_module_Overflow_flag_A), .Y(
overflow_flag) );
BUFX6TS U1891 ( .A(n5095), .Y(n5825) );
BUFX3TS U1892 ( .A(Op_MX[26]), .Y(n2221) );
XNOR2X2TS U1893 ( .A(n858), .B(n1794), .Y(n728) );
XNOR2X4TS U1894 ( .A(n820), .B(n6417), .Y(n729) );
CLKINVX3TS U1895 ( .A(n730), .Y(n940) );
OR2X1TS U1896 ( .A(n4233), .B(Sgf_operation_ODD1_Q_right[30]), .Y(n731) );
XNOR2X4TS U1897 ( .A(n1365), .B(n749), .Y(n732) );
AND3X4TS U1898 ( .A(n4711), .B(n4710), .C(n4709), .Y(n6531) );
BUFX3TS U1899 ( .A(n6531), .Y(n6805) );
INVX2TS U1900 ( .A(n6686), .Y(n6815) );
BUFX3TS U1901 ( .A(n6686), .Y(n6903) );
AO21X4TS U1902 ( .A0(n1214), .A1(n1213), .B0(n1212), .Y(n733) );
OR2X2TS U1903 ( .A(n1596), .B(n1597), .Y(n734) );
INVX4TS U1904 ( .A(n801), .Y(n851) );
CLKXOR2X4TS U1905 ( .A(n1413), .B(n1418), .Y(n736) );
CLKINVX3TS U1906 ( .A(n872), .Y(n873) );
BUFX3TS U1907 ( .A(n753), .Y(n899) );
BUFX3TS U1908 ( .A(n8365), .Y(n8372) );
XNOR2X2TS U1909 ( .A(n7808), .B(n7807), .Y(n7809) );
NOR2X4TS U1910 ( .A(n7512), .B(n7511), .Y(n5071) );
INVX4TS U1911 ( .A(n7683), .Y(n7693) );
NOR2X4TS U1912 ( .A(n7287), .B(n2933), .Y(n2935) );
OR2X2TS U1913 ( .A(n5161), .B(n3903), .Y(n3905) );
NAND2X4TS U1914 ( .A(n2923), .B(n2922), .Y(n7288) );
NOR2X4TS U1915 ( .A(n2193), .B(n7142), .Y(n2195) );
CLKINVX2TS U1916 ( .A(n7133), .Y(n7135) );
NOR2X4TS U1917 ( .A(n6117), .B(n953), .Y(n952) );
INVX3TS U1918 ( .A(n5162), .Y(n4950) );
NAND2X4TS U1919 ( .A(n2912), .B(n2911), .Y(n7124) );
NOR2X1TS U1920 ( .A(n7394), .B(n7396), .Y(n7399) );
NOR2X4TS U1921 ( .A(n7269), .B(n7129), .Y(n759) );
INVX2TS U1922 ( .A(n6112), .Y(n1179) );
AOI21X2TS U1923 ( .A0(n3568), .A1(n4832), .B0(n3567), .Y(n3569) );
NAND2X4TS U1924 ( .A(n2445), .B(n2446), .Y(n7129) );
NOR2X4TS U1925 ( .A(n4935), .B(n3891), .Y(n3893) );
NOR2X6TS U1926 ( .A(n8111), .B(n4411), .Y(n7999) );
NOR2X6TS U1927 ( .A(mult_x_24_n976), .B(mult_x_24_n966), .Y(n6122) );
ADDFHX2TS U1928 ( .A(n2444), .B(n2443), .CI(n2442), .CO(n2447), .S(n2446) );
NAND2X2TS U1929 ( .A(mult_x_24_n706), .B(mult_x_24_n710), .Y(n5016) );
NOR2X4TS U1930 ( .A(mult_x_23_n662), .B(mult_x_23_n656), .Y(n5189) );
NAND2X2TS U1931 ( .A(n3564), .B(n3563), .Y(n7312) );
INVX1TS U1932 ( .A(n7744), .Y(n7746) );
OAI2BB1X2TS U1933 ( .A0N(n2156), .A1N(n2155), .B0(n958), .Y(n2172) );
NOR2X4TS U1934 ( .A(n7173), .B(n1733), .Y(n1734) );
INVX2TS U1935 ( .A(n7169), .Y(n1735) );
ADDFHX2TS U1936 ( .A(n3262), .B(n3261), .CI(n3260), .CO(n3269), .S(n3265) );
INVX1TS U1937 ( .A(n8277), .Y(n8280) );
OAI21X2TS U1938 ( .A0(n2156), .A1(n2155), .B0(n2154), .Y(n958) );
NAND2X2TS U1939 ( .A(n4418), .B(Sgf_operation_ODD1_Q_left[8]), .Y(n8047) );
NAND2X2TS U1940 ( .A(n4414), .B(Sgf_operation_ODD1_Q_left[6]), .Y(n8077) );
INVX2TS U1941 ( .A(n8310), .Y(n8312) );
CLKMX2X2TS U1942 ( .A(P_Sgf[29]), .B(n8204), .S0(n8224), .Y(n450) );
INVX12TS U1943 ( .A(n739), .Y(n915) );
INVX6TS U1944 ( .A(n3384), .Y(n739) );
NAND2X2TS U1945 ( .A(n4384), .B(Sgf_operation_ODD1_Q_right[44]), .Y(n8289)
);
OAI21X1TS U1946 ( .A0(n6912), .A1(n6899), .B0(n6582), .Y(n6583) );
OAI21X1TS U1947 ( .A0(n6912), .A1(n6907), .B0(n6689), .Y(n6690) );
ADDHX2TS U1948 ( .A(n5052), .B(n5051), .CO(n6986), .S(mult_x_24_n1054) );
CLKMX2X2TS U1949 ( .A(n7828), .B(Add_result[25]), .S0(n8030), .Y(n554) );
INVX6TS U1950 ( .A(n1151), .Y(n6879) );
CMPR22X2TS U1951 ( .A(n5033), .B(n5032), .CO(n5052), .S(mult_x_24_n1059) );
CLKMX2X2TS U1952 ( .A(n7845), .B(Add_result[24]), .S0(n8186), .Y(n555) );
OAI21X1TS U1953 ( .A0(n6865), .A1(n6809), .B0(n6542), .Y(n6543) );
CLKMX2X2TS U1954 ( .A(P_Sgf[28]), .B(n8200), .S0(n8224), .Y(n449) );
CLKMX2X2TS U1955 ( .A(n7790), .B(Add_result[28]), .S0(n8030), .Y(n551) );
INVX12TS U1956 ( .A(n733), .Y(n820) );
OR2X2TS U1957 ( .A(n7223), .B(n7222), .Y(n7225) );
ADDHX2TS U1958 ( .A(n1100), .B(n1099), .CO(n1072), .S(n1101) );
CLKMX2X2TS U1959 ( .A(n7857), .B(Add_result[23]), .S0(n8030), .Y(n556) );
CLKMX2X2TS U1960 ( .A(n7814), .B(Add_result[26]), .S0(n8030), .Y(n553) );
CLKMX2X2TS U1961 ( .A(n7802), .B(Add_result[27]), .S0(n8030), .Y(n552) );
ADDHX1TS U1962 ( .A(n1423), .B(n1422), .CO(n1625), .S(n1466) );
ADDHX2TS U1963 ( .A(n1476), .B(n1475), .CO(n1468), .S(n1580) );
BUFX6TS U1964 ( .A(n3226), .Y(n3582) );
AO21X1TS U1965 ( .A0(n934), .A1(n2214), .B0(n3426), .Y(n2961) );
BUFX12TS U1966 ( .A(n2788), .Y(n2739) );
NAND3X1TS U1967 ( .A(n8370), .B(n8369), .C(n8368), .Y(n711) );
ADDHX2TS U1968 ( .A(n940), .B(n1089), .CO(n1099), .S(n1090) );
AO21X1TS U1969 ( .A0(n3376), .A1(n2956), .B0(n3129), .Y(n3161) );
AO21X1TS U1970 ( .A0(n2839), .A1(n2215), .B0(n3367), .Y(n3382) );
INVX8TS U1971 ( .A(n3403), .Y(n888) );
AO21X1TS U1972 ( .A0(n935), .A1(n3052), .B0(n3051), .Y(n3080) );
ADDHX2TS U1973 ( .A(n5208), .B(n5207), .CO(n5210), .S(mult_x_24_n963) );
INVX2TS U1974 ( .A(n7601), .Y(n7602) );
CLKMX2X2TS U1975 ( .A(n8060), .B(Add_result[9]), .S0(n8030), .Y(n570) );
BUFX12TS U1976 ( .A(n2577), .Y(n911) );
BUFX12TS U1977 ( .A(n2097), .Y(n3006) );
BUFX12TS U1978 ( .A(n2735), .Y(n3165) );
INVX12TS U1979 ( .A(n861), .Y(n741) );
OAI21X1TS U1980 ( .A0(n8447), .A1(n8367), .B0(FS_Module_state_reg[3]), .Y(
n7483) );
CLKMX2X2TS U1981 ( .A(n7929), .B(Add_result[18]), .S0(n8030), .Y(n561) );
BUFX12TS U1982 ( .A(n2084), .Y(n931) );
INVX2TS U1983 ( .A(n8440), .Y(n7470) );
AO21X1TS U1984 ( .A0(n865), .A1(n5769), .B0(n882), .Y(n5445) );
CLKMX2X2TS U1985 ( .A(Data_MY[54]), .B(Op_MY[54]), .S0(n8371), .Y(n636) );
CLKMX2X2TS U1986 ( .A(Data_MX[17]), .B(Op_MX[17]), .S0(n896), .Y(n663) );
INVX2TS U1987 ( .A(n7620), .Y(n7621) );
MX2X1TS U1988 ( .A(Data_MX[26]), .B(Op_MX[26]), .S0(n7504), .Y(n672) );
AND2X2TS U1989 ( .A(n6060), .B(n829), .Y(n5404) );
AOI222X1TS U1990 ( .A0(n6889), .A1(Op_MX[14]), .B0(n6887), .B1(n7069), .C0(
n7032), .C1(n875), .Y(n6640) );
AOI222X1TS U1991 ( .A0(n6848), .A1(n927), .B0(n7045), .B1(n6790), .C0(n6615),
.C1(n6894), .Y(n6596) );
CLKMX2X2TS U1992 ( .A(Data_MX[54]), .B(Op_MX[54]), .S0(n8371), .Y(n700) );
INVX4TS U1993 ( .A(n880), .Y(n882) );
CLKMX2X2TS U1994 ( .A(Data_MX[53]), .B(Op_MX[53]), .S0(n7505), .Y(n699) );
CLKMX2X2TS U1995 ( .A(Data_MY[17]), .B(n835), .S0(n7505), .Y(n599) );
CLKMX2X2TS U1996 ( .A(Data_MY[16]), .B(Op_MY[16]), .S0(n8371), .Y(n598) );
CLKMX2X2TS U1997 ( .A(Data_MY[15]), .B(Op_MY[15]), .S0(n7505), .Y(n597) );
NAND2X6TS U1998 ( .A(n3089), .B(n2082), .Y(n2084) );
CLKMX2X2TS U1999 ( .A(Data_MY[52]), .B(Op_MY[52]), .S0(n7505), .Y(n634) );
AOI222X1TS U2000 ( .A0(n7011), .A1(n6894), .B0(n6834), .B1(n939), .C0(n6867),
.C1(n6785), .Y(n6494) );
CLKMX2X2TS U2001 ( .A(Data_MY[12]), .B(Op_MY[12]), .S0(n7505), .Y(n594) );
CLKMX2X2TS U2002 ( .A(Data_MX[59]), .B(Op_MX[59]), .S0(n7505), .Y(n705) );
CLKMX2X2TS U2003 ( .A(Data_MY[11]), .B(Op_MY[11]), .S0(n7506), .Y(n593) );
CLKMX2X2TS U2004 ( .A(Data_MY[8]), .B(Op_MY[8]), .S0(n7509), .Y(n590) );
INVX4TS U2005 ( .A(n1124), .Y(n1096) );
CLKMX2X2TS U2006 ( .A(Data_MY[32]), .B(n755), .S0(n8371), .Y(n614) );
INVX8TS U2007 ( .A(n736), .Y(n2469) );
AND2X2TS U2008 ( .A(n5940), .B(n5779), .Y(n3863) );
AND2X2TS U2009 ( .A(n5899), .B(n6016), .Y(n5874) );
AND2X2TS U2010 ( .A(n6060), .B(n6023), .Y(n1238) );
AOI222X1TS U2011 ( .A0(n6839), .A1(n6894), .B0(n7045), .B1(n937), .C0(n6615),
.C1(n8412), .Y(n6600) );
AND2X2TS U2012 ( .A(n5940), .B(n5769), .Y(n3873) );
CLKMX2X2TS U2013 ( .A(Data_MY[45]), .B(Op_MY[45]), .S0(n8371), .Y(n627) );
CLKMX2X2TS U2014 ( .A(Data_MY[39]), .B(Op_MY[39]), .S0(n8371), .Y(n621) );
AOI222X1TS U2015 ( .A0(n885), .A1(n8412), .B0(n6916), .B1(n7069), .C0(n6914),
.C1(n875), .Y(n6717) );
INVX4TS U2016 ( .A(n863), .Y(n865) );
INVX4TS U2017 ( .A(n973), .Y(n5936) );
AOI222X1TS U2018 ( .A0(n885), .A1(Op_MX[13]), .B0(n1083), .B1(n7009), .C0(
n6914), .C1(n6853), .Y(n6719) );
CLKMX2X2TS U2019 ( .A(Data_MX[14]), .B(Op_MX[14]), .S0(n7496), .Y(n660) );
INVX4TS U2020 ( .A(n8433), .Y(n8030) );
CLKMX2X2TS U2021 ( .A(Data_MX[5]), .B(Op_MX[5]), .S0(n7497), .Y(n651) );
BUFX12TS U2022 ( .A(n2563), .Y(n2976) );
CLKMX2X2TS U2023 ( .A(Data_MX[2]), .B(n8402), .S0(n7501), .Y(n648) );
CLKMX2X2TS U2024 ( .A(Data_MX[0]), .B(Op_MX[0]), .S0(n7502), .Y(n646) );
CLKMX2X2TS U2025 ( .A(P_Sgf[7]), .B(Sgf_operation_Result[7]), .S0(n8190),
.Y(n428) );
CLKMX2X2TS U2026 ( .A(P_Sgf[4]), .B(Sgf_operation_Result[4]), .S0(n8190),
.Y(n425) );
CLKMX2X2TS U2027 ( .A(P_Sgf[8]), .B(Sgf_operation_Result[8]), .S0(n8190),
.Y(n429) );
CLKMX2X2TS U2028 ( .A(P_Sgf[12]), .B(Sgf_operation_Result[12]), .S0(n8190),
.Y(n433) );
CLKMX2X2TS U2029 ( .A(P_Sgf[11]), .B(Sgf_operation_Result[11]), .S0(n8190),
.Y(n432) );
INVX4TS U2030 ( .A(n8372), .Y(n8371) );
MX2X1TS U2031 ( .A(Data_MX[51]), .B(Op_MX[51]), .S0(n7499), .Y(n697) );
MX2X1TS U2032 ( .A(Data_MX[50]), .B(Op_MX[50]), .S0(n7502), .Y(n696) );
CLKMX2X2TS U2033 ( .A(Data_MX[49]), .B(Op_MX[49]), .S0(n7499), .Y(n695) );
BUFX16TS U2034 ( .A(n2578), .Y(n3118) );
CLKMX2X2TS U2035 ( .A(P_Sgf[10]), .B(Sgf_operation_Result[10]), .S0(n8190),
.Y(n431) );
CLKMX2X2TS U2036 ( .A(P_Sgf[5]), .B(Sgf_operation_Result[5]), .S0(n8190),
.Y(n426) );
OAI31X1TS U2037 ( .A0(n8433), .A1(n8430), .A2(n8536), .B0(n7472), .Y(n418)
);
BUFX12TS U2038 ( .A(n1710), .Y(n2940) );
CLKMX2X2TS U2039 ( .A(P_Sgf[6]), .B(Sgf_operation_Result[6]), .S0(n8190),
.Y(n427) );
CLKMX2X2TS U2040 ( .A(P_Sgf[9]), .B(Sgf_operation_Result[9]), .S0(n8190),
.Y(n430) );
CLKINVX2TS U2041 ( .A(n4106), .Y(n4088) );
CLKMX2X2TS U2042 ( .A(P_Sgf[13]), .B(Sgf_operation_Result[13]), .S0(n8190),
.Y(n434) );
INVX2TS U2043 ( .A(n4166), .Y(n4168) );
INVX2TS U2044 ( .A(n4352), .Y(n4354) );
INVX2TS U2045 ( .A(n4347), .Y(n4349) );
NOR2X1TS U2046 ( .A(n778), .B(n806), .Y(n807) );
NOR2X1TS U2047 ( .A(n775), .B(n805), .Y(n8381) );
INVX2TS U2048 ( .A(n4189), .Y(n4191) );
NOR2X1TS U2049 ( .A(n774), .B(n809), .Y(n8407) );
INVX2TS U2050 ( .A(n4151), .Y(n4153) );
INVX2TS U2051 ( .A(n4278), .Y(n4261) );
AO21X1TS U2052 ( .A0(n6011), .A1(n5769), .B0(n5922), .Y(n5526) );
NAND4X1TS U2053 ( .A(n7457), .B(n7456), .C(n7455), .D(n7454), .Y(n7459) );
INVX4TS U2054 ( .A(n4702), .Y(n5863) );
CLKINVX2TS U2055 ( .A(n4264), .Y(n4244) );
INVX2TS U2056 ( .A(n4123), .Y(n4117) );
INVX2TS U2057 ( .A(n7824), .Y(n7825) );
NAND2X6TS U2058 ( .A(n905), .B(n825), .Y(n1073) );
NAND2X2TS U2059 ( .A(n3997), .B(n3996), .Y(n4173) );
CLKMX2X2TS U2060 ( .A(Op_MX[55]), .B(exp_oper_result[3]), .S0(n847), .Y(
S_Oper_A_exp[3]) );
NAND2X2TS U2061 ( .A(n4455), .B(n4454), .Y(n4596) );
NOR2X2TS U2062 ( .A(n4544), .B(n4543), .Y(n4548) );
INVX2TS U2063 ( .A(n6310), .Y(n6327) );
CLKMX2X2TS U2064 ( .A(Op_MX[56]), .B(exp_oper_result[4]), .S0(n847), .Y(
S_Oper_A_exp[4]) );
NOR2X4TS U2065 ( .A(n4057), .B(n4056), .Y(n4279) );
NAND2X2TS U2066 ( .A(n4085), .B(n4084), .Y(n4157) );
NAND2X2TS U2067 ( .A(n4451), .B(n4450), .Y(n4564) );
NOR2X1TS U2068 ( .A(n808), .B(n776), .Y(n777) );
AND2X2TS U2069 ( .A(n2250), .B(n8393), .Y(n2251) );
NAND2X4TS U2070 ( .A(n7489), .B(FS_Module_state_reg[3]), .Y(n7473) );
INVX4TS U2071 ( .A(n1007), .Y(n2287) );
INVX2TS U2072 ( .A(n5535), .Y(n5537) );
XOR2X1TS U2073 ( .A(n1419), .B(n1418), .Y(n1420) );
AND2X2TS U2074 ( .A(n6946), .B(n6785), .Y(n6224) );
INVX4TS U2075 ( .A(n6517), .Y(n6968) );
INVX3TS U2076 ( .A(n735), .Y(n6851) );
INVX4TS U2077 ( .A(n2221), .Y(n3583) );
INVX2TS U2078 ( .A(n7480), .Y(n7481) );
CLKAND2X2TS U2079 ( .A(n7078), .B(n6874), .Y(mult_x_24_n1104) );
INVX6TS U2080 ( .A(n3813), .Y(n6989) );
INVX4TS U2081 ( .A(n1450), .Y(n1812) );
INVX3TS U2082 ( .A(n6974), .Y(n6758) );
INVX4TS U2083 ( .A(n3813), .Y(n6963) );
INVX4TS U2084 ( .A(n2221), .Y(n3157) );
INVX3TS U2085 ( .A(n6974), .Y(n6891) );
AND2X2TS U2086 ( .A(Op_MY[26]), .B(n6959), .Y(n5128) );
INVX12TS U2087 ( .A(n8444), .Y(n835) );
AND2X2TS U2088 ( .A(n6946), .B(n6484), .Y(mult_x_24_n1087) );
INVX3TS U2089 ( .A(n735), .Y(n7051) );
INVX2TS U2090 ( .A(n730), .Y(n8377) );
INVX4TS U2091 ( .A(n1034), .Y(n6069) );
INVX4TS U2092 ( .A(n769), .Y(n8392) );
INVX4TS U2093 ( .A(Op_MX[26]), .Y(n3813) );
INVX4TS U2094 ( .A(n767), .Y(n5736) );
INVX4TS U2095 ( .A(n1020), .Y(n5663) );
INVX4TS U2096 ( .A(n1015), .Y(n5847) );
INVX12TS U2097 ( .A(Op_MY[8]), .Y(n6974) );
INVX4TS U2098 ( .A(n1035), .Y(n5567) );
INVX4TS U2099 ( .A(n1022), .Y(n5828) );
INVX4TS U2100 ( .A(n1015), .Y(n7493) );
INVX4TS U2101 ( .A(n1017), .Y(n6882) );
INVX4TS U2102 ( .A(n767), .Y(n5763) );
INVX4TS U2103 ( .A(n1031), .Y(n5769) );
INVX4TS U2104 ( .A(n1009), .Y(n7027) );
INVX4TS U2105 ( .A(n1020), .Y(n5644) );
INVX4TS U2106 ( .A(n803), .Y(n3632) );
INVX4TS U2107 ( .A(n1031), .Y(n5883) );
INVX4TS U2108 ( .A(n769), .Y(n7076) );
INVX4TS U2109 ( .A(n1032), .Y(n5819) );
INVX4TS U2110 ( .A(n1015), .Y(n5868) );
BUFX12TS U2111 ( .A(Op_MX[3]), .Y(n6584) );
INVX4TS U2112 ( .A(n1022), .Y(n7498) );
INVX4TS U2113 ( .A(n1022), .Y(n6002) );
INVX4TS U2114 ( .A(n1009), .Y(n6827) );
MX2X2TS U2115 ( .A(P_Sgf[105]), .B(n5072), .S0(n8188), .Y(n420) );
XOR2X2TS U2116 ( .A(n3921), .B(n993), .Y(Sgf_operation_ODD1_middle_N49) );
CLKMX2X2TS U2117 ( .A(P_Sgf[79]), .B(n7809), .S0(n7850), .Y(n500) );
CLKMX2X2TS U2118 ( .A(P_Sgf[81]), .B(n7785), .S0(n7850), .Y(n502) );
OA21X2TS U2119 ( .A0(n7379), .A1(n7247), .B0(n7246), .Y(n743) );
CLKMX2X2TS U2120 ( .A(P_Sgf[78]), .B(n7820), .S0(n7850), .Y(n499) );
CLKMX2X2TS U2121 ( .A(P_Sgf[103]), .B(n7543), .S0(n8191), .Y(n525) );
CLKMX2X2TS U2122 ( .A(P_Sgf[76]), .B(n7851), .S0(n7850), .Y(n497) );
XOR2X2TS U2123 ( .A(n7839), .B(n7838), .Y(n7840) );
CLKMX2X2TS U2124 ( .A(P_Sgf[72]), .B(n7909), .S0(n7988), .Y(n493) );
CLKMX2X2TS U2125 ( .A(P_Sgf[80]), .B(n7796), .S0(n7850), .Y(n501) );
CLKMX2X2TS U2126 ( .A(P_Sgf[71]), .B(n7924), .S0(n7988), .Y(n492) );
CLKMX2X2TS U2127 ( .A(P_Sgf[75]), .B(n7866), .S0(n7988), .Y(n496) );
CLKMX2X2TS U2128 ( .A(P_Sgf[70]), .B(n7934), .S0(n7988), .Y(n491) );
NAND2X6TS U2129 ( .A(n7542), .B(Sgf_operation_ODD1_Q_left[49]), .Y(n7512) );
CLKMX2X2TS U2130 ( .A(P_Sgf[74]), .B(n7876), .S0(n7988), .Y(n495) );
CLKMX2X2TS U2131 ( .A(P_Sgf[69]), .B(n7955), .S0(n7988), .Y(n490) );
XOR2X1TS U2132 ( .A(n6102), .B(n6101), .Y(Sgf_operation_ODD1_right_N27) );
XNOR2X2TS U2133 ( .A(n4786), .B(n4785), .Y(Sgf_operation_ODD1_left_N34) );
CLKMX2X2TS U2134 ( .A(P_Sgf[102]), .B(n7555), .S0(n8191), .Y(n524) );
XOR2X1TS U2135 ( .A(n7379), .B(n7126), .Y(Sgf_operation_ODD1_middle_N28) );
CLKMX2X2TS U2136 ( .A(P_Sgf[84]), .B(n7734), .S0(n7850), .Y(n505) );
CLKMX2X2TS U2137 ( .A(P_Sgf[68]), .B(n7965), .S0(n7988), .Y(n489) );
XOR2X1TS U2138 ( .A(n5297), .B(n5296), .Y(Sgf_operation_ODD1_left_N26) );
OR2X2TS U2139 ( .A(n5142), .B(n5143), .Y(n1026) );
CLKMX2X2TS U2140 ( .A(P_Sgf[101]), .B(n7563), .S0(n8191), .Y(n523) );
CLKMX2X2TS U2141 ( .A(P_Sgf[82]), .B(n7760), .S0(n7850), .Y(n503) );
INVX8TS U2142 ( .A(n6106), .Y(n6130) );
CLKMX2X2TS U2143 ( .A(P_Sgf[100]), .B(n7571), .S0(n8191), .Y(n522) );
CLKMX2X2TS U2144 ( .A(P_Sgf[63]), .B(n8038), .S0(n8133), .Y(n484) );
CLKMX2X2TS U2145 ( .A(P_Sgf[62]), .B(n8051), .S0(n8133), .Y(n483) );
XOR2X1TS U2146 ( .A(n6135), .B(n6134), .Y(Sgf_operation_ODD1_right_N20) );
OAI21X1TS U2147 ( .A0(n7154), .A1(n7137), .B0(n7136), .Y(n7141) );
CLKMX2X2TS U2148 ( .A(P_Sgf[66]), .B(n7989), .S0(n7988), .Y(n487) );
NAND2X4TS U2149 ( .A(n3575), .B(n792), .Y(n3576) );
XOR2X1TS U2150 ( .A(n5331), .B(n5330), .Y(Sgf_operation_ODD1_left_N20) );
CLKMX2X2TS U2151 ( .A(P_Sgf[60]), .B(n8081), .S0(n8133), .Y(n481) );
OAI21X1TS U2152 ( .A0(n7154), .A1(n7147), .B0(n7151), .Y(n7150) );
INVX3TS U2153 ( .A(n7305), .Y(n7308) );
OAI21X1TS U2154 ( .A0(n7154), .A1(n7142), .B0(n7133), .Y(n7146) );
XOR2X1TS U2155 ( .A(n7154), .B(n7153), .Y(Sgf_operation_ODD1_middle_N20) );
NOR2X6TS U2156 ( .A(n7570), .B(n7569), .Y(n7561) );
CLKMX2X2TS U2157 ( .A(P_Sgf[56]), .B(n8134), .S0(n8133), .Y(n477) );
XOR2X1TS U2158 ( .A(n5339), .B(n5338), .Y(Sgf_operation_ODD1_left_N18) );
OAI21X1TS U2159 ( .A0(n5331), .A1(n5324), .B0(n5328), .Y(n5327) );
CLKMX2X2TS U2160 ( .A(P_Sgf[55]), .B(n8145), .S0(n8188), .Y(n476) );
XOR2X1TS U2161 ( .A(n7160), .B(n7175), .Y(Sgf_operation_ODD1_middle_N13) );
CLKMX2X2TS U2162 ( .A(P_Sgf[58]), .B(n8104), .S0(n8133), .Y(n479) );
NAND2X4TS U2163 ( .A(n7335), .B(n3524), .Y(n7330) );
CLKMX2X2TS U2164 ( .A(P_Sgf[53]), .B(n8167), .S0(n8188), .Y(n474) );
CLKMX2X2TS U2165 ( .A(P_Sgf[59]), .B(n8093), .S0(n8133), .Y(n480) );
CLKMX2X2TS U2166 ( .A(P_Sgf[49]), .B(n8339), .S0(n8354), .Y(n470) );
OAI21X1TS U2167 ( .A0(n7160), .A1(n7168), .B0(n7173), .Y(n7172) );
INVX3TS U2168 ( .A(n1290), .Y(n1276) );
CLKMX2X2TS U2169 ( .A(P_Sgf[54]), .B(n8154), .S0(n8188), .Y(n475) );
XOR2X1TS U2170 ( .A(n6951), .B(n6950), .Y(Sgf_operation_ODD1_right_N17) );
XOR2X1TS U2171 ( .A(n6159), .B(n6158), .Y(Sgf_operation_ODD1_right_N15) );
XOR2X1TS U2172 ( .A(n6152), .B(n6151), .Y(Sgf_operation_ODD1_right_N16) );
INVX8TS U2173 ( .A(n5250), .Y(n5221) );
INVX2TS U2174 ( .A(n7131), .Y(n7154) );
OAI21X1TS U2175 ( .A0(n5950), .A1(n5946), .B0(n5947), .Y(n5348) );
INVX2TS U2176 ( .A(n7155), .Y(n7156) );
CLKMX2X2TS U2177 ( .A(P_Sgf[48]), .B(n8329), .S0(n8354), .Y(n469) );
XOR2X1TS U2178 ( .A(n5950), .B(n5949), .Y(Sgf_operation_ODD1_left_N15) );
CLKMX2X2TS U2179 ( .A(P_Sgf[51]), .B(n8352), .S0(n8354), .Y(n472) );
XOR2X1TS U2180 ( .A(n5354), .B(n5353), .Y(Sgf_operation_ODD1_left_N14) );
XOR2X1TS U2181 ( .A(n7180), .B(n7179), .Y(Sgf_operation_ODD1_middle_N12) );
CLKMX2X2TS U2182 ( .A(P_Sgf[52]), .B(n8176), .S0(n8188), .Y(n473) );
NOR2X6TS U2183 ( .A(n3537), .B(n7345), .Y(n3539) );
NAND2X4TS U2184 ( .A(n2453), .B(n7435), .Y(n2455) );
INVX3TS U2185 ( .A(n6733), .Y(n1269) );
AND2X2TS U2186 ( .A(n1273), .B(n1297), .Y(n984) );
NAND2X6TS U2187 ( .A(n966), .B(n965), .Y(n964) );
CLKMX2X2TS U2188 ( .A(P_Sgf[45]), .B(n8288), .S0(n8293), .Y(n466) );
CLKMX2X2TS U2189 ( .A(P_Sgf[47]), .B(n8271), .S0(n8293), .Y(n468) );
CLKMX2X2TS U2190 ( .A(P_Sgf[46]), .B(n8276), .S0(n8293), .Y(n467) );
CLKMX2X2TS U2191 ( .A(P_Sgf[50]), .B(n8342), .S0(n8354), .Y(n471) );
INVX2TS U2192 ( .A(n7159), .Y(n7160) );
AND2X2TS U2193 ( .A(n3920), .B(n3922), .Y(n993) );
OAI21X1TS U2194 ( .A0(n6957), .A1(n6953), .B0(n6954), .Y(n6169) );
AND2X2TS U2195 ( .A(n785), .B(n1267), .Y(n982) );
NAND2X1TS U2196 ( .A(n7322), .B(n7321), .Y(n821) );
AND2X2TS U2197 ( .A(n3930), .B(n3929), .Y(n969) );
NAND2X4TS U2198 ( .A(n7578), .B(Sgf_operation_ODD1_Q_left[45]), .Y(n5066) );
OR2X4TS U2199 ( .A(n955), .B(n1174), .Y(n949) );
XOR2X1TS U2200 ( .A(n6957), .B(n6956), .Y(Sgf_operation_ODD1_right_N12) );
XOR2X1TS U2201 ( .A(n6175), .B(n6174), .Y(Sgf_operation_ODD1_right_N11) );
NAND2X4TS U2202 ( .A(n7110), .B(n7107), .Y(n6094) );
AND2X2TS U2203 ( .A(n1289), .B(n1277), .Y(n983) );
CLKMX2X2TS U2204 ( .A(P_Sgf[44]), .B(n8294), .S0(n8293), .Y(n465) );
INVX3TS U2205 ( .A(n7328), .Y(n3547) );
NOR2X4TS U2206 ( .A(n7590), .B(n7592), .Y(n7579) );
CLKMX2X2TS U2207 ( .A(P_Sgf[43]), .B(n8300), .S0(n8354), .Y(n464) );
AND2X2TS U2208 ( .A(n5185), .B(n5183), .Y(n992) );
AND2X2TS U2209 ( .A(n1284), .B(n1291), .Y(n985) );
OAI21X1TS U2210 ( .A0(n7230), .A1(n7226), .B0(n7227), .Y(n7189) );
AND2X2TS U2211 ( .A(n4696), .B(n4695), .Y(n1003) );
CLKMX2X2TS U2212 ( .A(n8187), .B(FSM_add_overflow_flag), .S0(n8186), .Y(n526) );
XOR2X1TS U2213 ( .A(n5955), .B(n5954), .Y(Sgf_operation_ODD1_left_N11) );
AND2X2TS U2214 ( .A(n4919), .B(n5153), .Y(n978) );
CLKMX2X2TS U2215 ( .A(P_Sgf[41]), .B(n8315), .S0(n8354), .Y(n462) );
XOR2X1TS U2216 ( .A(n7230), .B(n7229), .Y(Sgf_operation_ODD1_middle_N9) );
OAI21X1TS U2217 ( .A0(n5955), .A1(n5951), .B0(n5952), .Y(n5363) );
NOR2X4TS U2218 ( .A(n3923), .B(n3928), .Y(n4820) );
ADDFHX2TS U2219 ( .A(n2859), .B(n2858), .CI(n2857), .CO(n2926), .S(n2924) );
INVX2TS U2220 ( .A(n5285), .Y(n5287) );
INVX3TS U2221 ( .A(n6123), .Y(n1177) );
XOR2X1TS U2222 ( .A(n5369), .B(n5368), .Y(Sgf_operation_ODD1_left_N10) );
XOR2X1TS U2223 ( .A(n7195), .B(n7194), .Y(Sgf_operation_ODD1_middle_N8) );
OR2X4TS U2224 ( .A(mult_x_23_n675), .B(mult_x_23_n682), .Y(n3773) );
OR2X6TS U2225 ( .A(mult_x_24_n977), .B(mult_x_24_n986), .Y(n972) );
AND2X2TS U2226 ( .A(n3807), .B(n3804), .Y(n1024) );
CLKMX2X2TS U2227 ( .A(Exp_module_Data_S[11]), .B(exp_oper_result[11]), .S0(
n942), .Y(n406) );
AND2X2TS U2228 ( .A(n3834), .B(n5116), .Y(n974) );
CLKMX2X2TS U2229 ( .A(P_Sgf[39]), .B(n8260), .S0(n8293), .Y(n460) );
CLKMX2X2TS U2230 ( .A(P_Sgf[42]), .B(n8306), .S0(n8354), .Y(n463) );
NOR2X4TS U2231 ( .A(n3836), .B(n5189), .Y(n3884) );
CLKMX2X2TS U2232 ( .A(P_Sgf[40]), .B(n8321), .S0(n8354), .Y(n461) );
ADDFHX2TS U2233 ( .A(n2778), .B(n2777), .CI(n2776), .CO(n2858), .S(n2803) );
OAI21X2TS U2234 ( .A0(n5177), .A1(n5171), .B0(n5178), .Y(n4948) );
CLKMX2X2TS U2235 ( .A(P_Sgf[37]), .B(n8247), .S0(n8293), .Y(n458) );
XNOR2X2TS U2236 ( .A(DP_OP_36J42_124_1029_n1), .B(n4698), .Y(n4699) );
AND2X2TS U2237 ( .A(n3599), .B(n3598), .Y(n968) );
ADDFHX2TS U2238 ( .A(n2429), .B(n2428), .CI(n2427), .CO(n2445), .S(n2190) );
CLKMX2X2TS U2239 ( .A(n7532), .B(Add_result[52]), .S0(n8186), .Y(n527) );
AND2X2TS U2240 ( .A(n5267), .B(n4956), .Y(n1033) );
NAND2X4TS U2241 ( .A(n5273), .B(n5267), .Y(n4935) );
NAND2X4TS U2242 ( .A(n1008), .B(n5329), .Y(n5318) );
CLKMX2X2TS U2243 ( .A(P_Sgf[36]), .B(n8241), .S0(n8293), .Y(n457) );
NAND2X4TS U2244 ( .A(n8116), .B(n4409), .Y(n4411) );
CLKMX2X2TS U2245 ( .A(n7540), .B(Add_result[51]), .S0(n8432), .Y(n528) );
NAND2X4TS U2246 ( .A(n7174), .B(n7170), .Y(n7162) );
CLKMX2X2TS U2247 ( .A(P_Sgf[35]), .B(n8235), .S0(n8293), .Y(n456) );
ADDFHX2TS U2248 ( .A(n2408), .B(n2407), .CI(n2406), .CO(n2679), .S(n2424) );
ADDFHX2TS U2249 ( .A(n3194), .B(n3193), .CI(n3192), .CO(n3264), .S(n3212) );
AND2X2TS U2250 ( .A(n5258), .B(n4943), .Y(n1011) );
CLKMX2X2TS U2251 ( .A(P_Sgf[38]), .B(n8251), .S0(n8293), .Y(n459) );
ADDFHX2TS U2252 ( .A(n2174), .B(n2173), .CI(n2172), .CO(n2165), .S(n2175) );
OAI21X1TS U2253 ( .A0(n8320), .A1(n8316), .B0(n8317), .Y(n8314) );
XOR2X1TS U2254 ( .A(n6188), .B(n6187), .Y(Sgf_operation_ODD1_right_N8) );
CLKMX2X2TS U2255 ( .A(Exp_module_Data_S[10]), .B(exp_oper_result[10]), .S0(
n941), .Y(n407) );
ADDFHX2TS U2256 ( .A(n3044), .B(n3043), .CI(n3042), .CO(n3548), .S(n3545) );
ADDFHX2TS U2257 ( .A(n2361), .B(n2360), .CI(n2359), .CO(n2671), .S(n2407) );
OR2X2TS U2258 ( .A(n3566), .B(n3565), .Y(n4832) );
AND2X2TS U2259 ( .A(n4931), .B(n4930), .Y(n980) );
NAND2X4TS U2260 ( .A(n8161), .B(n4403), .Y(n8111) );
ADDFHX2TS U2261 ( .A(n3016), .B(n3015), .CI(n3014), .CO(n3039), .S(n3470) );
ADDFHX2TS U2262 ( .A(n2705), .B(n2704), .CI(n2703), .CO(n2801), .S(n2747) );
CLKMX2X2TS U2263 ( .A(Exp_module_Data_S[9]), .B(exp_oper_result[9]), .S0(
n942), .Y(n408) );
ADDFHX2TS U2264 ( .A(n2553), .B(n2552), .CI(n2551), .CO(n2593), .S(n2676) );
ADDFHX2TS U2265 ( .A(n2799), .B(n2798), .CI(n2797), .CO(n2837), .S(n2777) );
CLKMX2X2TS U2266 ( .A(P_Sgf[34]), .B(n8229), .S0(n8293), .Y(n455) );
ADDFHX2TS U2267 ( .A(n2162), .B(n2161), .CI(n2160), .CO(n2147), .S(n2163) );
ADDFHX2TS U2268 ( .A(n2168), .B(n2167), .CI(n2166), .CO(n2177), .S(n2178) );
ADDFHX2TS U2269 ( .A(n2144), .B(n2143), .CI(n2142), .CO(n2428), .S(n2145) );
CLKMX2X2TS U2270 ( .A(P_Sgf[33]), .B(n8225), .S0(n8224), .Y(n454) );
ADDFHX2TS U2271 ( .A(n2141), .B(n2140), .CI(n2139), .CO(n2433), .S(n2146) );
ADDFHX2TS U2272 ( .A(n2417), .B(n2416), .CI(n2415), .CO(n2436), .S(n2429) );
ADDFHX2TS U2273 ( .A(n2796), .B(n2795), .CI(n2794), .CO(n2851), .S(n2802) );
CLKMX2X2TS U2274 ( .A(n7552), .B(Add_result[50]), .S0(n7768), .Y(n529) );
AND2X2TS U2275 ( .A(n4963), .B(n4962), .Y(n967) );
ADDFHX2TS U2276 ( .A(n2856), .B(n2855), .CI(n2854), .CO(n2905), .S(n2859) );
NOR2X4TS U2277 ( .A(n8149), .B(n8140), .Y(n8116) );
CLKMX2X2TS U2278 ( .A(n7560), .B(Add_result[49]), .S0(n7666), .Y(n530) );
INVX2TS U2279 ( .A(n8140), .Y(n8142) );
OR2X2TS U2280 ( .A(n3888), .B(n3887), .Y(n1012) );
ADDFHX2TS U2281 ( .A(n2384), .B(n2383), .CI(n2382), .CO(n2669), .S(n2426) );
ADDFHX2TS U2282 ( .A(n2068), .B(n2067), .CI(n2066), .CO(n2435), .S(n2143) );
ADDFHX2TS U2283 ( .A(n2892), .B(n2891), .CI(n2890), .CO(n3194), .S(n2907) );
OAI21X1TS U2284 ( .A0(n4929), .A1(n4962), .B0(n4930), .Y(n3900) );
ADDFHX2TS U2285 ( .A(n2159), .B(n2158), .CI(n2157), .CO(n2142), .S(n2164) );
CLKMX2X2TS U2286 ( .A(P_Sgf[32]), .B(n8218), .S0(n8224), .Y(n453) );
ADDFHX2TS U2287 ( .A(n3460), .B(n3459), .CI(n3458), .CO(n3472), .S(n3469) );
XOR2X1TS U2288 ( .A(n7208), .B(n7207), .Y(Sgf_operation_ODD1_middle_N5) );
CLKMX2X2TS U2289 ( .A(Exp_module_Data_S[8]), .B(exp_oper_result[8]), .S0(
n941), .Y(n409) );
OR2X2TS U2290 ( .A(n5130), .B(n5129), .Y(n5132) );
XOR2X1TS U2291 ( .A(n6203), .B(n6202), .Y(Sgf_operation_ODD1_right_N5) );
ADDFHX2TS U2292 ( .A(n2644), .B(n2643), .CI(n2642), .CO(n2726), .S(n2664) );
CLKMX2X2TS U2293 ( .A(Exp_module_Data_S[7]), .B(exp_oper_result[7]), .S0(
n942), .Y(n410) );
ADDFHX2TS U2294 ( .A(n1642), .B(n1641), .CI(n1640), .CO(n1732), .S(n1599) );
CLKMX2X2TS U2295 ( .A(n7568), .B(Add_result[48]), .S0(n7768), .Y(n531) );
OAI21X1TS U2296 ( .A0(n6202), .A1(n6199), .B0(n6200), .Y(n6198) );
XOR2X1TS U2297 ( .A(n5384), .B(n5383), .Y(Sgf_operation_ODD1_left_N5) );
XOR2X2TS U2298 ( .A(n6488), .B(n6794), .Y(mult_x_24_n1465) );
XOR2X2TS U2299 ( .A(n6746), .B(n6851), .Y(mult_x_24_n1550) );
XOR2X2TS U2300 ( .A(n6773), .B(n6827), .Y(mult_x_24_n1525) );
XOR2X1TS U2301 ( .A(n6524), .B(n6968), .Y(mult_x_24_n1496) );
OAI21X1TS U2302 ( .A0(n7006), .A1(n6925), .B0(n3831), .Y(n3832) );
OAI21X1TS U2303 ( .A0(n6918), .A1(n6932), .B0(n6917), .Y(n6919) );
OAI21X1TS U2304 ( .A0(n6832), .A1(n6966), .B0(n6523), .Y(n6524) );
INVX2TS U2305 ( .A(n5834), .Y(n5838) );
CLKMX2X2TS U2306 ( .A(Exp_module_Data_S[6]), .B(exp_oper_result[6]), .S0(
n941), .Y(n411) );
OAI21X1TS U2307 ( .A0(n6769), .A1(n6925), .B0(n6266), .Y(n6267) );
OAI21X1TS U2308 ( .A0(n8317), .A1(n8310), .B0(n8311), .Y(n4330) );
INVX2TS U2309 ( .A(n8088), .Y(n8090) );
XOR2X1TS U2310 ( .A(n5774), .B(n7491), .Y(mult_x_23_n1465) );
XOR2X1TS U2311 ( .A(n5865), .B(n3866), .Y(mult_x_23_n1268) );
XOR2X1TS U2312 ( .A(n7217), .B(n7216), .Y(Sgf_operation_ODD1_middle_N3) );
ADDFHX2TS U2313 ( .A(n2793), .B(n2792), .CI(n2791), .CO(n2852), .S(n2799) );
XOR2X2TS U2314 ( .A(n4549), .B(n4546), .Y(n4627) );
INVX2TS U2315 ( .A(n8347), .Y(n8349) );
INVX2TS U2316 ( .A(n8266), .Y(n8268) );
OR2X2TS U2317 ( .A(n3735), .B(n3734), .Y(n5815) );
ADDFHX2TS U2318 ( .A(n1499), .B(n1498), .CI(n1497), .CO(n1598), .S(n1597) );
CLKMX2X2TS U2319 ( .A(n7576), .B(Add_result[47]), .S0(n7666), .Y(n532) );
CLKMX2X2TS U2320 ( .A(n7723), .B(Add_result[33]), .S0(n7768), .Y(n546) );
CLKMX2X2TS U2321 ( .A(P_Sgf[30]), .B(n8210), .S0(n8224), .Y(n451) );
ADDFHX2TS U2322 ( .A(n1846), .B(n1845), .CI(n1844), .CO(n1842), .S(n1928) );
CLKMX2X2TS U2323 ( .A(P_Sgf[31]), .B(n8214), .S0(n8224), .Y(n452) );
ADDFHX2TS U2324 ( .A(n2641), .B(n2640), .CI(n2639), .CO(n2703), .S(n2643) );
CLKMX2X2TS U2325 ( .A(n7731), .B(Add_result[32]), .S0(n7768), .Y(n547) );
XOR2X1TS U2326 ( .A(n5627), .B(n5644), .Y(mult_x_23_n1379) );
ADDFHX2TS U2327 ( .A(n1564), .B(n1563), .CI(n1562), .CO(n1565), .S(n1537) );
OAI21X1TS U2328 ( .A0(n5781), .A1(n5924), .B0(n5529), .Y(n5530) );
OAI21X1TS U2329 ( .A0(n729), .A1(n6932), .B0(n6895), .Y(n6896) );
OAI21X1TS U2330 ( .A0(n5781), .A1(n6083), .B0(n5780), .Y(n5782) );
OAI21X1TS U2331 ( .A0(n6993), .A1(n7025), .B0(n6226), .Y(n6227) );
OAI21X1TS U2332 ( .A0(n5773), .A1(n5827), .B0(n5574), .Y(n5575) );
OAI21X1TS U2333 ( .A0(n6084), .A1(n936), .B0(n5728), .Y(n5729) );
OAI21X1TS U2334 ( .A0(n5781), .A1(n5827), .B0(n5576), .Y(n5577) );
XOR2X1TS U2335 ( .A(n5389), .B(n5388), .Y(Sgf_operation_ODD1_left_N4) );
XOR2X2TS U2336 ( .A(n5545), .B(n5926), .Y(mult_x_23_n1329) );
OAI21X1TS U2337 ( .A0(n6084), .A1(n4965), .B0(n5864), .Y(n5865) );
OAI21X1TS U2338 ( .A0(n6993), .A1(n7062), .B0(n5114), .Y(n5115) );
CLKMX2X2TS U2339 ( .A(Exp_module_Data_S[5]), .B(exp_oper_result[5]), .S0(
n942), .Y(n412) );
OAI22X2TS U2340 ( .A0(n2588), .A1(n928), .B0(n2656), .B1(n2772), .Y(n2638)
);
ADDFHX2TS U2341 ( .A(n1894), .B(n1893), .CI(n1892), .CO(n2134), .S(n1897) );
INVX8TS U2342 ( .A(n6338), .Y(n6918) );
INVX8TS U2343 ( .A(n6305), .Y(n6850) );
ADDFHX1TS U2344 ( .A(n3254), .B(n3253), .CI(n3252), .CO(n3292), .S(n3215) );
CLKMX2X2TS U2345 ( .A(n7589), .B(Add_result[46]), .S0(n7666), .Y(n533) );
OAI21X1TS U2346 ( .A0(n5905), .A1(n5985), .B0(n5654), .Y(n5655) );
INVX4TS U2347 ( .A(n3053), .Y(n738) );
OAI21X1TS U2348 ( .A0(n6879), .A1(n7085), .B0(n6370), .Y(n6371) );
OAI21X1TS U2349 ( .A0(n5905), .A1(n6014), .B0(n5556), .Y(n5557) );
OAI21X1TS U2350 ( .A0(n5968), .A1(n5620), .B0(n5646), .Y(n5647) );
OAI21X1TS U2351 ( .A0(n6048), .A1(n6042), .B0(n5787), .Y(n5788) );
OAI21X1TS U2352 ( .A0(n6036), .A1(n6042), .B0(n5794), .Y(n5795) );
OAI21X1TS U2353 ( .A0(n6036), .A1(n936), .B0(n5743), .Y(n5744) );
OAI21X1TS U2354 ( .A0(n6026), .A1(n5620), .B0(n5641), .Y(n5642) );
OAI21X1TS U2355 ( .A0(n6912), .A1(n6872), .B0(n6506), .Y(n6507) );
OAI21X1TS U2356 ( .A0(n6036), .A1(n6007), .B0(n5606), .Y(n5607) );
ADDFHX2TS U2357 ( .A(n6073), .B(n6072), .CI(n6071), .CO(n6074), .S(
mult_x_23_n832) );
OAI21X1TS U2358 ( .A0(n5925), .A1(n5924), .B0(n5923), .Y(n5927) );
OAI21X1TS U2359 ( .A0(n5968), .A1(n6042), .B0(n5967), .Y(n5969) );
OAI21X1TS U2360 ( .A0(n5968), .A1(n936), .B0(n5738), .Y(n5739) );
OAI21X1TS U2361 ( .A0(n6912), .A1(n6729), .B0(n6728), .Y(n6731) );
OAI21X1TS U2362 ( .A0(n6912), .A1(n7049), .B0(n6611), .Y(n6612) );
CLKMX2X2TS U2363 ( .A(Exp_module_Data_S[4]), .B(exp_oper_result[4]), .S0(
n941), .Y(n413) );
OAI21X1TS U2364 ( .A0(n6026), .A1(n936), .B0(n5733), .Y(n5734) );
OAI21X1TS U2365 ( .A0(n6775), .A1(n6729), .B0(n6721), .Y(n6722) );
BUFX12TS U2366 ( .A(n5912), .Y(n6043) );
OAI21X1TS U2367 ( .A0(n7086), .A1(n7038), .B0(n6649), .Y(n6650) );
OAI21X1TS U2368 ( .A0(n6036), .A1(n5985), .B0(n5961), .Y(n5962) );
OAI21X1TS U2369 ( .A0(n6036), .A1(n6035), .B0(n6034), .Y(n6037) );
XOR2X1TS U2370 ( .A(n6838), .B(n6695), .Y(mult_x_24_n1628) );
OAI21X1TS U2371 ( .A0(n6855), .A1(n6729), .B0(n6723), .Y(n6724) );
OAI21X1TS U2372 ( .A0(n5905), .A1(n5807), .B0(n5806), .Y(n5808) );
CLKMX2X2TS U2373 ( .A(n7769), .B(Add_result[29]), .S0(n7768), .Y(n550) );
ADDFHX2TS U2374 ( .A(n1551), .B(n1550), .CI(n1549), .CO(n1556), .S(n1563) );
OAI21X1TS U2375 ( .A0(n7086), .A1(n6809), .B0(n6536), .Y(n6537) );
OAI21X1TS U2376 ( .A0(n6879), .A1(n6907), .B0(n6691), .Y(n6692) );
OAI21X1TS U2377 ( .A0(n7086), .A1(n6729), .B0(n6725), .Y(n6726) );
CLKMX2X2TS U2378 ( .A(n7754), .B(Add_result[30]), .S0(n7768), .Y(n549) );
CLKMX2X2TS U2379 ( .A(n7743), .B(Add_result[31]), .S0(n8432), .Y(n548) );
OAI21X1TS U2380 ( .A0(n6879), .A1(n6809), .B0(n6540), .Y(n6541) );
OAI21X1TS U2381 ( .A0(n6879), .A1(n6899), .B0(n6878), .Y(n6880) );
CLKMX2X2TS U2382 ( .A(n7599), .B(Add_result[45]), .S0(n8432), .Y(n534) );
OAI21X1TS U2383 ( .A0(n6036), .A1(n6014), .B0(n6013), .Y(n6015) );
ADDHX2TS U2384 ( .A(n1750), .B(n1749), .CO(n1819), .S(n1836) );
OAI21X1TS U2385 ( .A0(n5905), .A1(n936), .B0(n5754), .Y(n5755) );
OAI21X1TS U2386 ( .A0(n6855), .A1(n6907), .B0(n6854), .Y(n6856) );
XOR2X2TS U2387 ( .A(n6800), .B(n835), .Y(mult_x_24_n1508) );
INVX2TS U2388 ( .A(n8295), .Y(n8297) );
ADDFHX2TS U2389 ( .A(n2886), .B(n2885), .CI(n2884), .CO(n3184), .S(n2887) );
OAI21X1TS U2390 ( .A0(n6879), .A1(n7038), .B0(n6651), .Y(n6652) );
ADDFHX2TS U2391 ( .A(n1633), .B(n1632), .CI(n1631), .CO(n1657), .S(n1629) );
OAI21X1TS U2392 ( .A0(n6775), .A1(n6907), .B0(n6687), .Y(n6688) );
BUFX8TS U2393 ( .A(n3865), .Y(n5887) );
AO22X1TS U2394 ( .A0(Sgf_normalized_result[51]), .A1(n8439), .B0(
final_result_ieee[51]), .B1(n8438), .Y(n300) );
OAI21X1TS U2395 ( .A0(n6008), .A1(n5807), .B0(n5799), .Y(n5800) );
OAI21X1TS U2396 ( .A0(n6865), .A1(n7038), .B0(n6857), .Y(n6858) );
NOR2X1TS U2397 ( .A(n3369), .B(n971), .Y(n3380) );
CLKMX2X2TS U2398 ( .A(n7610), .B(Add_result[44]), .S0(n8432), .Y(n535) );
OAI21X1TS U2399 ( .A0(n6008), .A1(n936), .B0(n5749), .Y(n5750) );
CLKMX2X2TS U2400 ( .A(n7667), .B(Add_result[39]), .S0(n7666), .Y(n540) );
CMPR22X2TS U2401 ( .A(n4799), .B(n4798), .CO(mult_x_23_n958), .S(n3739) );
OAI21X1TS U2402 ( .A0(n6865), .A1(n7049), .B0(n6618), .Y(n6619) );
CLKMX2X2TS U2403 ( .A(Exp_module_Data_S[3]), .B(exp_oper_result[3]), .S0(
n942), .Y(n414) );
OAI21X1TS U2404 ( .A0(n5876), .A1(n936), .B0(n5746), .Y(n5747) );
INVX8TS U2405 ( .A(n6466), .Y(n7086) );
OAI21X1TS U2406 ( .A0(n6008), .A1(n5978), .B0(n5977), .Y(n5979) );
ADDHX2TS U2407 ( .A(n1531), .B(n1530), .CO(n1549), .S(n1535) );
ADDHX2TS U2408 ( .A(n6944), .B(n6943), .CO(n7093), .S(mult_x_24_n1020) );
AO22X1TS U2409 ( .A0(n8360), .A1(Sgf_normalized_result[9]), .B0(
final_result_ieee[9]), .B1(n8361), .Y(n342) );
AO22X1TS U2410 ( .A0(n8360), .A1(Sgf_normalized_result[10]), .B0(
final_result_ieee[10]), .B1(n8361), .Y(n341) );
AO22X1TS U2411 ( .A0(n8360), .A1(Sgf_normalized_result[11]), .B0(
final_result_ieee[11]), .B1(n8361), .Y(n340) );
XOR2X1TS U2412 ( .A(n998), .B(n6212), .Y(Sgf_operation_ODD1_right_N2) );
AO22X1TS U2413 ( .A0(n8362), .A1(Sgf_normalized_result[12]), .B0(
final_result_ieee[12]), .B1(n8361), .Y(n339) );
OAI21X2TS U2414 ( .A0(n7039), .A1(n6809), .B0(n6799), .Y(n6800) );
ADDFHX1TS U2415 ( .A(n1470), .B(n1469), .CI(n1468), .CO(n1464), .S(n1489) );
AO22X1TS U2416 ( .A0(n8362), .A1(Sgf_normalized_result[13]), .B0(
final_result_ieee[13]), .B1(n8363), .Y(n338) );
AO22X1TS U2417 ( .A0(n8362), .A1(Sgf_normalized_result[14]), .B0(
final_result_ieee[14]), .B1(n8363), .Y(n337) );
AO22X1TS U2418 ( .A0(n8362), .A1(Sgf_normalized_result[15]), .B0(
final_result_ieee[15]), .B1(n8363), .Y(n336) );
OR2X2TS U2419 ( .A(n4290), .B(Sgf_operation_ODD1_Q_right[37]), .Y(n989) );
AO22X1TS U2420 ( .A0(n8362), .A1(Sgf_normalized_result[16]), .B0(
final_result_ieee[16]), .B1(n8363), .Y(n335) );
AO22X1TS U2421 ( .A0(n8362), .A1(Sgf_normalized_result[17]), .B0(
final_result_ieee[17]), .B1(n8363), .Y(n334) );
OR2X2TS U2422 ( .A(n4289), .B(Sgf_operation_ODD1_Q_right[36]), .Y(n4284) );
ADDHX2TS U2423 ( .A(n7017), .B(n7016), .CO(n7030), .S(n5055) );
AO22X1TS U2424 ( .A0(n8362), .A1(Sgf_normalized_result[18]), .B0(
final_result_ieee[18]), .B1(n8363), .Y(n333) );
AO22X1TS U2425 ( .A0(n8362), .A1(Sgf_normalized_result[19]), .B0(
final_result_ieee[19]), .B1(n8363), .Y(n332) );
AO22X1TS U2426 ( .A0(n8362), .A1(Sgf_normalized_result[20]), .B0(
final_result_ieee[20]), .B1(n8363), .Y(n331) );
AO22X1TS U2427 ( .A0(n8362), .A1(Sgf_normalized_result[21]), .B0(
final_result_ieee[21]), .B1(n8363), .Y(n330) );
AO22X1TS U2428 ( .A0(n8439), .A1(Sgf_normalized_result[22]), .B0(
final_result_ieee[22]), .B1(n8363), .Y(n329) );
OAI21X2TS U2429 ( .A0(n7039), .A1(n6763), .B0(n6762), .Y(n6764) );
ADDFHX2TS U2430 ( .A(n1722), .B(n1721), .CI(n1720), .CO(n1834), .S(n1686) );
CLKMX2X2TS U2431 ( .A(n7682), .B(Add_result[37]), .S0(n7768), .Y(n542) );
AO22X1TS U2432 ( .A0(n8360), .A1(Sgf_normalized_result[4]), .B0(
final_result_ieee[4]), .B1(n8361), .Y(n347) );
BUFX12TS U2433 ( .A(n2957), .Y(n3278) );
INVX8TS U2434 ( .A(n6346), .Y(n7075) );
OAI21X1TS U2435 ( .A0(n6008), .A1(n6007), .B0(n6006), .Y(n6009) );
AO22X1TS U2436 ( .A0(n8360), .A1(Sgf_normalized_result[3]), .B0(
final_result_ieee[3]), .B1(n8361), .Y(n348) );
AO22X1TS U2437 ( .A0(n8360), .A1(Sgf_normalized_result[5]), .B0(
final_result_ieee[5]), .B1(n8361), .Y(n346) );
AO22X1TS U2438 ( .A0(n8360), .A1(Sgf_normalized_result[6]), .B0(
final_result_ieee[6]), .B1(n8361), .Y(n345) );
AO22X1TS U2439 ( .A0(n8360), .A1(Sgf_normalized_result[7]), .B0(
final_result_ieee[7]), .B1(n8361), .Y(n344) );
AO22X1TS U2440 ( .A0(n8360), .A1(Sgf_normalized_result[8]), .B0(
final_result_ieee[8]), .B1(n8361), .Y(n343) );
OR2X2TS U2441 ( .A(n4286), .B(Sgf_operation_ODD1_Q_right[35]), .Y(n988) );
AO22X1TS U2442 ( .A0(Sgf_normalized_result[49]), .A1(n8437), .B0(
final_result_ieee[49]), .B1(n8438), .Y(n302) );
OAI21X1TS U2443 ( .A0(n5762), .A1(n5761), .B0(n5760), .Y(n5764) );
CLKBUFX2TS U2444 ( .A(n3702), .Y(n894) );
AO22X1TS U2445 ( .A0(Sgf_normalized_result[50]), .A1(n8437), .B0(
final_result_ieee[50]), .B1(n8438), .Y(n301) );
AO22X1TS U2446 ( .A0(Sgf_normalized_result[39]), .A1(n8435), .B0(
final_result_ieee[39]), .B1(n8436), .Y(n312) );
XOR2X1TS U2447 ( .A(n5853), .B(n895), .Y(mult_x_23_n1428) );
OAI21X1TS U2448 ( .A0(n5957), .A1(n5807), .B0(n5803), .Y(n5805) );
AO22X1TS U2449 ( .A0(Sgf_normalized_result[40]), .A1(n8435), .B0(
final_result_ieee[40]), .B1(n8436), .Y(n311) );
AO22X1TS U2450 ( .A0(Sgf_normalized_result[38]), .A1(n8435), .B0(
final_result_ieee[38]), .B1(n8434), .Y(n313) );
AO22X1TS U2451 ( .A0(Sgf_normalized_result[37]), .A1(n8435), .B0(
final_result_ieee[37]), .B1(n8434), .Y(n314) );
AO22X1TS U2452 ( .A0(Sgf_normalized_result[41]), .A1(n8437), .B0(
final_result_ieee[41]), .B1(n8436), .Y(n310) );
AO22X1TS U2453 ( .A0(Sgf_normalized_result[1]), .A1(n7470), .B0(
final_result_ieee[1]), .B1(n8434), .Y(n350) );
AO22X1TS U2454 ( .A0(Sgf_normalized_result[0]), .A1(n7470), .B0(
final_result_ieee[0]), .B1(n8434), .Y(n351) );
XOR2X2TS U2455 ( .A(n3722), .B(n895), .Y(n4798) );
AO22X1TS U2456 ( .A0(Sgf_normalized_result[36]), .A1(n8435), .B0(
final_result_ieee[36]), .B1(n8438), .Y(n315) );
AO22X1TS U2457 ( .A0(Sgf_normalized_result[42]), .A1(n8437), .B0(
final_result_ieee[42]), .B1(n8436), .Y(n309) );
AO22X1TS U2458 ( .A0(Sgf_normalized_result[43]), .A1(n8437), .B0(
final_result_ieee[43]), .B1(n8436), .Y(n308) );
AO22X1TS U2459 ( .A0(Sgf_normalized_result[44]), .A1(n8437), .B0(
final_result_ieee[44]), .B1(n8436), .Y(n307) );
OR2X2TS U2460 ( .A(n4255), .B(Sgf_operation_ODD1_Q_right[32]), .Y(n987) );
ADDHX2TS U2461 ( .A(n3716), .B(n3715), .CO(n4799), .S(n3733) );
AO22X1TS U2462 ( .A0(Sgf_normalized_result[45]), .A1(n8437), .B0(
final_result_ieee[45]), .B1(n8436), .Y(n306) );
CLKMX2X2TS U2463 ( .A(Exp_module_Data_S[2]), .B(exp_oper_result[2]), .S0(
n941), .Y(n415) );
OAI21X1TS U2464 ( .A0(n6001), .A1(n936), .B0(n5756), .Y(n5757) );
AO22X1TS U2465 ( .A0(Sgf_normalized_result[35]), .A1(n8435), .B0(
final_result_ieee[35]), .B1(n8434), .Y(n316) );
AO22X1TS U2466 ( .A0(Sgf_normalized_result[46]), .A1(n8437), .B0(
final_result_ieee[46]), .B1(n8436), .Y(n305) );
BUFX12TS U2467 ( .A(n2869), .Y(n3223) );
CLKMX2X2TS U2468 ( .A(n7699), .B(Add_result[35]), .S0(n7768), .Y(n544) );
AO22X1TS U2469 ( .A0(Sgf_normalized_result[34]), .A1(n8435), .B0(
final_result_ieee[34]), .B1(n8434), .Y(n317) );
CLKMX2X2TS U2470 ( .A(n7691), .B(Add_result[36]), .S0(n8432), .Y(n543) );
AO22X1TS U2471 ( .A0(Sgf_normalized_result[47]), .A1(n8437), .B0(
final_result_ieee[47]), .B1(n8436), .Y(n304) );
AO22X1TS U2472 ( .A0(Sgf_normalized_result[33]), .A1(n8435), .B0(
final_result_ieee[33]), .B1(n8434), .Y(n318) );
OAI21X1TS U2473 ( .A0(n5957), .A1(n936), .B0(n5752), .Y(n5753) );
CLKMX2X2TS U2474 ( .A(n7672), .B(Add_result[38]), .S0(n7768), .Y(n541) );
CLKMX2X2TS U2475 ( .A(n7619), .B(Add_result[43]), .S0(n8432), .Y(n536) );
AO22X1TS U2476 ( .A0(Sgf_normalized_result[48]), .A1(n8437), .B0(
final_result_ieee[48]), .B1(n8436), .Y(n303) );
AO22X1TS U2477 ( .A0(Sgf_normalized_result[32]), .A1(n8435), .B0(
final_result_ieee[32]), .B1(n8434), .Y(n319) );
OAI21X1TS U2478 ( .A0(n5957), .A1(n6014), .B0(n5554), .Y(n5555) );
AO22X1TS U2479 ( .A0(Sgf_normalized_result[31]), .A1(n8435), .B0(
final_result_ieee[31]), .B1(n8434), .Y(n320) );
OR2X2TS U2480 ( .A(n1504), .B(n1503), .Y(n7219) );
ADDHX2TS U2481 ( .A(n4763), .B(n4762), .CO(n5993), .S(mult_x_23_n945) );
ADDHX1TS U2482 ( .A(n1134), .B(n1133), .CO(n4728), .S(n1142) );
CLKMX2X2TS U2483 ( .A(n7960), .B(Add_result[16]), .S0(n7473), .Y(n563) );
OAI21X1TS U2484 ( .A0(n5762), .A1(n5985), .B0(n5662), .Y(n5664) );
OR2X2TS U2485 ( .A(n1091), .B(n1090), .Y(n1014) );
CLKMX2X2TS U2486 ( .A(n7871), .B(Add_result[22]), .S0(n8030), .Y(n557) );
CLKMX2X2TS U2487 ( .A(n7655), .B(Add_result[40]), .S0(n7666), .Y(n539) );
CMPR22X2TS U2488 ( .A(n5212), .B(n5211), .CO(n6059), .S(mult_x_23_n854) );
OAI21X1TS U2489 ( .A0(n5957), .A1(n6007), .B0(n5610), .Y(n5611) );
CLKMX2X2TS U2490 ( .A(n7643), .B(Add_result[41]), .S0(n7666), .Y(n538) );
OAI21X1TS U2491 ( .A0(n5957), .A1(n5985), .B0(n5956), .Y(n5958) );
ADDHX2TS U2492 ( .A(n835), .B(n6940), .CO(n6944), .S(mult_x_24_n1028) );
ADDHX2TS U2493 ( .A(n2229), .B(n2228), .CO(n2232), .S(n2322) );
CLKMX2X2TS U2494 ( .A(n8110), .B(Add_result[5]), .S0(n7473), .Y(n574) );
CLKMX2X2TS U2495 ( .A(n8098), .B(Add_result[6]), .S0(n8432), .Y(n573) );
CLKMX2X2TS U2496 ( .A(n7915), .B(Add_result[19]), .S0(n7473), .Y(n560) );
CLKMX2X2TS U2497 ( .A(n8138), .B(Add_result[3]), .S0(n8432), .Y(n576) );
AOI222X1TS U2498 ( .A0(n6817), .A1(n6756), .B0(n887), .B1(n6701), .C0(n6813),
.C1(n6816), .Y(n6664) );
CLKMX2X2TS U2499 ( .A(n7904), .B(Add_result[20]), .S0(n7666), .Y(n559) );
OAI21X1TS U2500 ( .A0(n5931), .A1(n5985), .B0(n5103), .Y(n5104) );
CLKMX2X2TS U2501 ( .A(n7629), .B(Add_result[42]), .S0(n7666), .Y(n537) );
CLKMX2X2TS U2502 ( .A(n7982), .B(Add_result[14]), .S0(n7473), .Y(n565) );
CLKMX2X2TS U2503 ( .A(n7996), .B(Add_result[13]), .S0(n7473), .Y(n566) );
AO21X1TS U2504 ( .A0(Sgf_normalized_result[52]), .A1(n8070), .B0(n7538), .Y(
n580) );
CLKMX2X2TS U2505 ( .A(n8016), .B(Add_result[12]), .S0(n7666), .Y(n567) );
CLKMX2X2TS U2506 ( .A(n8031), .B(Add_result[11]), .S0(n7473), .Y(n568) );
BUFX3TS U2507 ( .A(n7545), .Y(n7899) );
CLKMX2X2TS U2508 ( .A(n8045), .B(Add_result[10]), .S0(n7473), .Y(n569) );
XOR2X2TS U2509 ( .A(n1045), .B(n1044), .Y(n1046) );
OAI21X1TS U2510 ( .A0(n5931), .A1(n6035), .B0(n5524), .Y(n5525) );
AO21X1TS U2511 ( .A0(n3331), .A1(n2946), .B0(n3107), .Y(n3117) );
AO21X1TS U2512 ( .A0(n3231), .A1(n1990), .B0(n2692), .Y(n3095) );
ADDHX2TS U2513 ( .A(n6021), .B(n5909), .CO(n5211), .S(mult_x_23_n865) );
CLKMX2X2TS U2514 ( .A(n8086), .B(Add_result[7]), .S0(n8186), .Y(n572) );
XOR2X2TS U2515 ( .A(n4748), .B(n7064), .Y(n6938) );
BUFX3TS U2516 ( .A(n7545), .Y(n8183) );
OAI211X1TS U2517 ( .A0(n4698), .A1(n8428), .B0(n7483), .C0(n8070), .Y(n714)
);
CLKMX2X2TS U2518 ( .A(n7709), .B(Add_result[34]), .S0(n8432), .Y(n545) );
CLKMX2X2TS U2519 ( .A(Exp_module_Data_S[1]), .B(exp_oper_result[1]), .S0(
n942), .Y(n416) );
AND2X2TS U2520 ( .A(n3672), .B(n7491), .Y(n5396) );
XOR2X2TS U2521 ( .A(n3696), .B(n895), .Y(n3716) );
AOI222X1TS U2522 ( .A0(n6817), .A1(n6847), .B0(n886), .B1(n6846), .C0(n6813),
.C1(n874), .Y(n6668) );
NOR2X1TS U2523 ( .A(n7959), .B(n8466), .Y(n7942) );
OR2X2TS U2524 ( .A(n4240), .B(Sgf_operation_ODD1_Q_right[31]), .Y(n991) );
CMPR22X2TS U2525 ( .A(n4761), .B(n4760), .CO(n4763), .S(mult_x_23_n950) );
INVX6TS U2526 ( .A(n3611), .Y(n5762) );
OAI21X1TS U2527 ( .A0(n6068), .A1(n5978), .B0(n5852), .Y(n5853) );
CLKMX2X2TS U2528 ( .A(P_Sgf[15]), .B(Sgf_operation_Result[15]), .S0(n8192),
.Y(n436) );
CLKMX2X2TS U2529 ( .A(P_Sgf[19]), .B(Sgf_operation_Result[19]), .S0(n8192),
.Y(n440) );
BUFX12TS U2530 ( .A(n1622), .Y(n3428) );
AOI222X1TS U2531 ( .A0(n6683), .A1(n6888), .B0(n886), .B1(n6886), .C0(n823),
.C1(n6884), .Y(n1135) );
OAI21X1TS U2532 ( .A0(n6068), .A1(n5861), .B0(n3698), .Y(n3699) );
AO21X1TS U2533 ( .A0(n7472), .A1(FSM_selector_B[0]), .B0(n7468), .Y(n419) );
CLKMX2X2TS U2534 ( .A(P_Sgf[23]), .B(Sgf_operation_Result[23]), .S0(n8192),
.Y(n444) );
AOI222X1TS U2535 ( .A0(n6683), .A1(n937), .B0(n887), .B1(n7071), .C0(n823),
.C1(n6569), .Y(n6678) );
CLKMX2X2TS U2536 ( .A(P_Sgf[20]), .B(Sgf_operation_Result[20]), .S0(n8192),
.Y(n441) );
NOR2X1TS U2537 ( .A(n7479), .B(n8367), .Y(n713) );
ADDHX2TS U2538 ( .A(n4686), .B(n4685), .CO(n6087), .S(mult_x_23_n911) );
AOI222X1TS U2539 ( .A0(n7036), .A1(n6853), .B0(n7034), .B1(n7082), .C0(n7032), .C1(Op_MX[9]), .Y(n6647) );
OR2X2TS U2540 ( .A(n3677), .B(n3676), .Y(n786) );
CLKMX2X2TS U2541 ( .A(P_Sgf[22]), .B(Sgf_operation_Result[22]), .S0(n8192),
.Y(n443) );
CLKMX2X2TS U2542 ( .A(P_Sgf[18]), .B(Sgf_operation_Result[18]), .S0(n8192),
.Y(n439) );
CLKMX2X2TS U2543 ( .A(P_Sgf[14]), .B(Sgf_operation_Result[14]), .S0(n8192),
.Y(n435) );
CLKMX2X2TS U2544 ( .A(P_Sgf[16]), .B(Sgf_operation_Result[16]), .S0(n8192),
.Y(n437) );
AOI222X1TS U2545 ( .A0(n6683), .A1(n6928), .B0(n887), .B1(n6915), .C0(n823),
.C1(n938), .Y(n6674) );
CLKMX2X2TS U2546 ( .A(Exp_module_Data_S[0]), .B(exp_oper_result[0]), .S0(
n941), .Y(n417) );
BUFX12TS U2547 ( .A(n2877), .Y(n928) );
AOI222X1TS U2548 ( .A0(n6817), .A1(n927), .B0(n887), .B1(n6790), .C0(n823),
.C1(n6894), .Y(n6672) );
CLKMX2X2TS U2549 ( .A(P_Sgf[21]), .B(Sgf_operation_Result[21]), .S0(n8192),
.Y(n442) );
CLKMX2X2TS U2550 ( .A(P_Sgf[17]), .B(Sgf_operation_Result[17]), .S0(n8192),
.Y(n438) );
OAI21X1TS U2551 ( .A0(n8186), .A1(Sgf_normalized_result[2]), .B0(n7474), .Y(
n577) );
ADDHX2TS U2552 ( .A(n5094), .B(n5093), .CO(n5102), .S(n3803) );
NAND2X2TS U2553 ( .A(n962), .B(n961), .Y(n960) );
CLKMX2X2TS U2554 ( .A(Data_MX[60]), .B(Op_MX[60]), .S0(n7509), .Y(n706) );
CLKMX2X2TS U2555 ( .A(Data_MY[55]), .B(Op_MY[55]), .S0(n7495), .Y(n637) );
NAND2BX1TS U2556 ( .AN(n929), .B(n1708), .Y(n1520) );
AOI222X1TS U2557 ( .A0(n5983), .A1(n832), .B0(n5981), .B1(n5858), .C0(n5660),
.C1(n5892), .Y(n5656) );
CLKMX2X2TS U2558 ( .A(P_Sgf[25]), .B(Sgf_operation_Result[25]), .S0(n8224),
.Y(n446) );
CLKMX2X2TS U2559 ( .A(Data_MX[56]), .B(Op_MX[56]), .S0(n8353), .Y(n702) );
CLKMX2X2TS U2560 ( .A(Data_MY[60]), .B(Op_MY[60]), .S0(n7509), .Y(n642) );
NAND2X6TS U2561 ( .A(n3178), .B(n1355), .Y(n1429) );
AOI222X1TS U2562 ( .A0(n5983), .A1(n5858), .B0(n5981), .B1(n5998), .C0(n5660), .C1(n755), .Y(n5658) );
CLKMX2X2TS U2563 ( .A(P_Sgf[2]), .B(Sgf_operation_Result[2]), .S0(n8188),
.Y(n423) );
CLKMX2X2TS U2564 ( .A(Data_MX[58]), .B(Op_MX[58]), .S0(n7504), .Y(n704) );
AOI222X1TS U2565 ( .A0(n6839), .A1(Op_MX[4]), .B0(n7045), .B1(n6886), .C0(
n6615), .C1(n6884), .Y(n5046) );
CLKMX2X2TS U2566 ( .A(P_Sgf[3]), .B(Sgf_operation_Result[3]), .S0(n8188),
.Y(n424) );
NOR2X1TS U2567 ( .A(n7928), .B(n8465), .Y(n7914) );
NOR2X1TS U2568 ( .A(n7969), .B(n8469), .Y(n7970) );
AOI222X1TS U2569 ( .A0(n6889), .A1(n874), .B0(n6970), .B1(n6929), .C0(n6990),
.C1(n6928), .Y(n6631) );
CLKMX2X2TS U2570 ( .A(P_Sgf[27]), .B(n8196), .S0(n8224), .Y(n448) );
CLKMX2X2TS U2571 ( .A(Data_MY[59]), .B(Op_MY[59]), .S0(n7506), .Y(n641) );
NAND2X6TS U2572 ( .A(n2976), .B(n1800), .Y(n2097) );
AND2X2TS U2573 ( .A(n6060), .B(n5963), .Y(n5205) );
CLKMX2X2TS U2574 ( .A(Data_MY[18]), .B(Op_MY[18]), .S0(n8353), .Y(n600) );
CLKMX2X2TS U2575 ( .A(Data_MX[23]), .B(Op_MX[23]), .S0(n7495), .Y(n669) );
CLKMX2X2TS U2576 ( .A(P_Sgf[0]), .B(Sgf_operation_Result[0]), .S0(n8188),
.Y(n421) );
NAND2BX1TS U2577 ( .AN(n7232), .B(n1872), .Y(n1427) );
AOI222X1TS U2578 ( .A0(n6877), .A1(n6859), .B0(n7021), .B1(Op_MX[4]), .C0(
n7019), .C1(n6584), .Y(n6585) );
CLKMX2X2TS U2579 ( .A(Data_MX[22]), .B(Op_MX[22]), .S0(n8353), .Y(n668) );
NAND2BX1TS U2580 ( .AN(n7232), .B(n2070), .Y(n1621) );
ADDHX2TS U2581 ( .A(Op_MX[44]), .B(n5910), .CO(n4685), .S(mult_x_23_n919) );
AOI222X1TS U2582 ( .A0(n7023), .A1(n7044), .B0(n7021), .B1(Op_MX[3]), .C0(
n7019), .C1(n6897), .Y(n6898) );
AOI222X1TS U2583 ( .A0(n6796), .A1(n6847), .B0(n6786), .B1(n6846), .C0(n6960), .C1(n874), .Y(n6521) );
AOI222X1TS U2584 ( .A0(n6839), .A1(n938), .B0(n7045), .B1(n7071), .C0(n6615),
.C1(n6569), .Y(n6602) );
CLKMX2X2TS U2585 ( .A(Data_MX[18]), .B(n927), .S0(n7504), .Y(n664) );
CLKMX2X2TS U2586 ( .A(Data_MY[27]), .B(n824), .S0(n7504), .Y(n609) );
CLKMX2X2TS U2587 ( .A(Data_MY[51]), .B(Op_MY[51]), .S0(n8353), .Y(n633) );
CLKMX2X2TS U2588 ( .A(Data_MY[29]), .B(n855), .S0(n896), .Y(n611) );
CLKMX2X2TS U2589 ( .A(Data_MY[30]), .B(Op_MY[30]), .S0(n896), .Y(n612) );
CLKMX2X2TS U2590 ( .A(Data_MY[31]), .B(n8376), .S0(n7504), .Y(n613) );
CLKMX2X2TS U2591 ( .A(Data_MY[33]), .B(Op_MY[33]), .S0(n7506), .Y(n615) );
AOI222X1TS U2592 ( .A0(n6877), .A1(n7082), .B0(n6876), .B1(Op_MX[9]), .C0(
n6581), .C1(n7079), .Y(n6579) );
CLKMX2X2TS U2593 ( .A(Data_MY[35]), .B(n8385), .S0(n8353), .Y(n617) );
CLKMX2X2TS U2594 ( .A(Data_MY[36]), .B(n838), .S0(n896), .Y(n618) );
NAND2X6TS U2595 ( .A(n2940), .B(n1713), .Y(n1718) );
CLKMX2X2TS U2596 ( .A(Data_MY[53]), .B(Op_MY[53]), .S0(n7506), .Y(n635) );
CLKMX2X2TS U2597 ( .A(Data_MY[62]), .B(Op_MY[62]), .S0(n896), .Y(n644) );
CLKMX2X2TS U2598 ( .A(Data_MY[38]), .B(Op_MY[38]), .S0(n896), .Y(n620) );
CLKMX2X2TS U2599 ( .A(Data_MY[61]), .B(Op_MY[61]), .S0(n7509), .Y(n643) );
CLKMX2X2TS U2600 ( .A(Data_MY[57]), .B(Op_MY[57]), .S0(n7506), .Y(n639) );
CLKMX2X2TS U2601 ( .A(Data_MY[40]), .B(Op_MY[40]), .S0(n7504), .Y(n622) );
CLKMX2X2TS U2602 ( .A(Data_MX[52]), .B(Op_MX[52]), .S0(n7504), .Y(n698) );
CLKMX2X2TS U2603 ( .A(Data_MX[62]), .B(Op_MX[62]), .S0(n8353), .Y(n708) );
CLKMX2X2TS U2604 ( .A(Data_MY[42]), .B(Op_MY[42]), .S0(n7509), .Y(n624) );
NAND2BX1TS U2605 ( .AN(n2223), .B(n2784), .Y(n2083) );
AOI222X1TS U2606 ( .A0(n7047), .A1(n7046), .B0(n7045), .B1(n7044), .C0(n7043), .C1(n7042), .Y(n7048) );
CLKMX2X2TS U2607 ( .A(Data_MY[47]), .B(Op_MY[47]), .S0(n8353), .Y(n629) );
CLKMX2X2TS U2608 ( .A(Data_MY[48]), .B(Op_MY[48]), .S0(n8353), .Y(n630) );
CLKMX2X2TS U2609 ( .A(Data_MY[49]), .B(Op_MY[49]), .S0(n896), .Y(n631) );
CLKMX2X2TS U2610 ( .A(Data_MY[50]), .B(Op_MY[50]), .S0(n7504), .Y(n632) );
AO22X1TS U2611 ( .A0(n8433), .A1(Sgf_normalized_result[0]), .B0(n7768), .B1(
Add_result[0]), .Y(n579) );
XOR2X2TS U2612 ( .A(n3783), .B(n6002), .Y(n5094) );
NOR2X4TS U2613 ( .A(n8448), .B(n7546), .Y(n8039) );
NOR2X4TS U2614 ( .A(FSM_selector_C), .B(n7546), .Y(n7545) );
CLKMX2X2TS U2615 ( .A(Data_MY[56]), .B(Op_MY[56]), .S0(n896), .Y(n638) );
NAND2BX1TS U2616 ( .AN(n929), .B(n2287), .Y(n1501) );
ADDHX2TS U2617 ( .A(Op_MY[26]), .B(n4800), .CO(n4810), .S(n4816) );
CLKMX2X2TS U2618 ( .A(P_Sgf[26]), .B(Sgf_operation_Result[26]), .S0(n8224),
.Y(n447) );
CLKMX2X2TS U2619 ( .A(Data_MY[0]), .B(n8386), .S0(n8353), .Y(n582) );
CLKMX2X2TS U2620 ( .A(Data_MY[2]), .B(n8391), .S0(n7504), .Y(n584) );
XOR2X2TS U2621 ( .A(n4807), .B(n7076), .Y(n6942) );
CLKMX2X2TS U2622 ( .A(Data_MX[55]), .B(Op_MX[55]), .S0(n8353), .Y(n701) );
CLKMX2X2TS U2623 ( .A(Data_MY[5]), .B(n6695), .S0(n7495), .Y(n587) );
AO22X1TS U2624 ( .A0(n8433), .A1(Sgf_normalized_result[1]), .B0(n8432), .B1(
Add_result[1]), .Y(n578) );
CLKMX2X2TS U2625 ( .A(Data_MY[6]), .B(Op_MY[6]), .S0(n7495), .Y(n588) );
AO22X1TS U2626 ( .A0(n8372), .A1(Data_MX[63]), .B0(n7509), .B1(Op_MX[63]),
.Y(n645) );
CLKMX2X2TS U2627 ( .A(Data_MY[7]), .B(Op_MY[7]), .S0(n7495), .Y(n589) );
CLKMX2X2TS U2628 ( .A(Data_MX[24]), .B(Op_MX[24]), .S0(n7506), .Y(n670) );
CLKMX2X2TS U2629 ( .A(Data_MY[58]), .B(Op_MY[58]), .S0(n7495), .Y(n640) );
CLKMX2X2TS U2630 ( .A(Data_MY[9]), .B(Op_MY[9]), .S0(n7509), .Y(n591) );
CLKMX2X2TS U2631 ( .A(Data_MX[57]), .B(Op_MX[57]), .S0(n7495), .Y(n703) );
CLKMX2X2TS U2632 ( .A(Data_MX[25]), .B(Op_MX[25]), .S0(n7506), .Y(n671) );
CLKMX2X2TS U2633 ( .A(Data_MY[10]), .B(Op_MY[10]), .S0(n7509), .Y(n592) );
CLKMX2X2TS U2634 ( .A(Data_MX[61]), .B(Op_MX[61]), .S0(n7506), .Y(n707) );
BUFX12TS U2635 ( .A(n1828), .Y(n2738) );
CLKMX2X2TS U2636 ( .A(P_Sgf[24]), .B(Sgf_operation_Result[24]), .S0(n8224),
.Y(n445) );
CLKMX2X2TS U2637 ( .A(Data_MY[14]), .B(n7490), .S0(n7495), .Y(n596) );
CLKMX2X2TS U2638 ( .A(n8075), .B(Add_result[8]), .S0(n8030), .Y(n571) );
AOI222X1TS U2639 ( .A0(n6839), .A1(n6928), .B0(n7045), .B1(n6915), .C0(n6615), .C1(n938), .Y(n6598) );
CLKMX2X2TS U2640 ( .A(Data_MY[13]), .B(Op_MY[13]), .S0(n7495), .Y(n595) );
CLKMX2X2TS U2641 ( .A(Data_MX[42]), .B(Op_MX[42]), .S0(n7501), .Y(n688) );
CLKMX2X2TS U2642 ( .A(Data_MX[43]), .B(Op_MX[43]), .S0(n7499), .Y(n689) );
CLKMX2X2TS U2643 ( .A(Data_MX[41]), .B(n7498), .S0(n7497), .Y(n687) );
BUFX16TS U2644 ( .A(n1990), .Y(n3188) );
CLKMX2X2TS U2645 ( .A(Data_MX[40]), .B(Op_MX[40]), .S0(n7502), .Y(n686) );
OR2X2TS U2646 ( .A(n8354), .B(n8430), .Y(n8355) );
CLKMX2X2TS U2647 ( .A(Data_MX[39]), .B(Op_MX[39]), .S0(n7499), .Y(n685) );
AOI222X1TS U2648 ( .A0(n5960), .A1(n8376), .B0(n5661), .B1(n830), .C0(n5660),
.C1(n8374), .Y(n3789) );
CLKMX2X2TS U2649 ( .A(Data_MX[38]), .B(n7500), .S0(n7502), .Y(n684) );
CLKMX2X2TS U2650 ( .A(Data_MX[37]), .B(Op_MX[37]), .S0(n7499), .Y(n683) );
XOR2X2TS U2651 ( .A(n8366), .B(n5255), .Y(DP_OP_36J42_124_1029_n28) );
CLKMX2X2TS U2652 ( .A(Data_MX[36]), .B(Op_MX[36]), .S0(n7501), .Y(n682) );
NAND2X2TS U2653 ( .A(n4474), .B(n4480), .Y(n4483) );
CLKMX2X2TS U2654 ( .A(Data_MX[34]), .B(Op_MX[34]), .S0(n7497), .Y(n680) );
CLKMX2X2TS U2655 ( .A(Data_MX[32]), .B(Op_MX[32]), .S0(n7499), .Y(n678) );
INVX2TS U2656 ( .A(n4574), .Y(n4575) );
AO21X1TS U2657 ( .A0(n4730), .A1(n6244), .B0(n4729), .Y(n790) );
INVX12TS U2658 ( .A(n3051), .Y(n2997) );
INVX4TS U2659 ( .A(n8433), .Y(n8432) );
CLKMX2X2TS U2660 ( .A(Data_MX[48]), .B(Op_MX[48]), .S0(n7501), .Y(n694) );
CLKMX2X2TS U2661 ( .A(Data_MX[47]), .B(n7493), .S0(n7502), .Y(n693) );
CLKMX2X2TS U2662 ( .A(Data_MX[8]), .B(n8413), .S0(n7496), .Y(n654) );
CLKMX2X2TS U2663 ( .A(Data_MX[7]), .B(Op_MX[7]), .S0(n7496), .Y(n653) );
CLKMX2X2TS U2664 ( .A(Data_MX[6]), .B(Op_MX[6]), .S0(n7501), .Y(n652) );
CLKMX2X2TS U2665 ( .A(Data_MX[4]), .B(Op_MX[4]), .S0(n7502), .Y(n650) );
CLKMX2X2TS U2666 ( .A(Data_MX[3]), .B(Op_MX[3]), .S0(n7499), .Y(n649) );
CLKMX2X2TS U2667 ( .A(Data_MX[1]), .B(Op_MX[1]), .S0(n7497), .Y(n647) );
INVX12TS U2668 ( .A(n3367), .Y(n3227) );
AOI222X1TS U2669 ( .A0(n1047), .A1(Op_MX[9]), .B0(n6727), .B1(n6910), .C0(
n6914), .C1(n6909), .Y(n6728) );
CLKMX2X2TS U2670 ( .A(Data_MY[19]), .B(Op_MY[19]), .S0(n7497), .Y(n601) );
CLKMX2X2TS U2671 ( .A(Data_MY[20]), .B(n7494), .S0(n7501), .Y(n602) );
OAI21X2TS U2672 ( .A0(n5043), .A1(n7062), .B0(n981), .Y(n4744) );
CLKMX2X2TS U2673 ( .A(Data_MY[21]), .B(Op_MY[21]), .S0(n7501), .Y(n603) );
OAI21X1TS U2674 ( .A0(n1001), .A1(n5861), .B0(n3640), .Y(n3641) );
CLKMX2X2TS U2675 ( .A(Data_MY[24]), .B(Op_MY[24]), .S0(n7497), .Y(n606) );
INVX4TS U2676 ( .A(n8433), .Y(n7666) );
CLKMX2X2TS U2677 ( .A(Data_MY[25]), .B(Op_MY[25]), .S0(n7501), .Y(n607) );
CLKMX2X2TS U2678 ( .A(Data_MY[26]), .B(n8393), .S0(n7499), .Y(n608) );
CLKMX2X2TS U2679 ( .A(Data_MX[31]), .B(Op_MX[31]), .S0(n7501), .Y(n677) );
CLKMX2X2TS U2680 ( .A(Data_MX[30]), .B(Op_MX[30]), .S0(n7497), .Y(n676) );
CLKMX2X2TS U2681 ( .A(Data_MX[29]), .B(n7491), .S0(n7501), .Y(n675) );
CLKMX2X2TS U2682 ( .A(Data_MX[28]), .B(Op_MX[28]), .S0(n7497), .Y(n674) );
CLKMX2X2TS U2683 ( .A(Data_MX[27]), .B(Op_MX[27]), .S0(n7502), .Y(n673) );
INVX4TS U2684 ( .A(n8372), .Y(n7506) );
AO21X1TS U2685 ( .A0(n868), .A1(n5769), .B0(n5825), .Y(n5573) );
INVX4TS U2686 ( .A(n8372), .Y(n7495) );
INVX4TS U2687 ( .A(n8372), .Y(n8353) );
INVX4TS U2688 ( .A(n8372), .Y(n896) );
INVX12TS U2689 ( .A(n3426), .Y(n3343) );
CLKMX2X2TS U2690 ( .A(Data_MX[16]), .B(Op_MX[16]), .S0(n7496), .Y(n662) );
CLKMX2X2TS U2691 ( .A(Data_MX[10]), .B(Op_MX[10]), .S0(n7496), .Y(n656) );
XOR2X2TS U2692 ( .A(n4659), .B(n5847), .Y(n4682) );
CLKMX2X2TS U2693 ( .A(Data_MX[13]), .B(Op_MX[13]), .S0(n7496), .Y(n659) );
CLKMX2X2TS U2694 ( .A(Data_MX[9]), .B(Op_MX[9]), .S0(n7496), .Y(n655) );
AOI222X1TS U2695 ( .A0(n885), .A1(n874), .B0(n6727), .B1(n6929), .C0(n7003),
.C1(n6928), .Y(n6931) );
CLKMX2X2TS U2696 ( .A(Data_MX[15]), .B(Op_MX[15]), .S0(n7496), .Y(n661) );
NAND2BX1TS U2697 ( .AN(n8368), .B(P_Sgf[105]), .Y(n7472) );
NAND2X1TS U2698 ( .A(n6065), .B(n824), .Y(n4970) );
NAND3X2TS U2699 ( .A(n1059), .B(n1058), .C(n1057), .Y(n6693) );
NAND2X4TS U2700 ( .A(n2627), .B(n1420), .Y(n2628) );
AOI222X1TS U2701 ( .A0(n6081), .A1(n848), .B0(n6079), .B1(n830), .C0(n5964),
.C1(n8374), .Y(n3683) );
NOR2X1TS U2702 ( .A(n7718), .B(n7522), .Y(n7530) );
AOI222X1TS U2703 ( .A0(n7083), .A1(n6859), .B0(n7058), .B1(Op_MX[4]), .C0(
n7057), .C1(n6584), .Y(n6374) );
NOR2X4TS U2704 ( .A(n1673), .B(n1753), .Y(n1700) );
NOR2X1TS U2705 ( .A(n8368), .B(P_Sgf[105]), .Y(n7477) );
CLKAND2X2TS U2706 ( .A(n6440), .B(n7001), .Y(n6378) );
INVX2TS U2707 ( .A(n4103), .Y(n4097) );
INVX2TS U2708 ( .A(n4600), .Y(n4602) );
INVX2TS U2709 ( .A(n4300), .Y(n4302) );
INVX2TS U2710 ( .A(n4336), .Y(n4338) );
OAI21X2TS U2711 ( .A0(n4266), .A1(n4263), .B0(n4267), .Y(n4032) );
INVX2TS U2712 ( .A(n4364), .Y(n4366) );
INVX2TS U2713 ( .A(n4557), .Y(n4559) );
INVX2TS U2714 ( .A(n4314), .Y(n4316) );
XOR2X2TS U2715 ( .A(n1799), .B(n1798), .Y(n1800) );
INVX2TS U2716 ( .A(n4568), .Y(n4570) );
INVX1TS U2717 ( .A(n4373), .Y(n4375) );
BUFX16TS U2718 ( .A(n3796), .Y(n5653) );
NOR2X4TS U2719 ( .A(n4562), .B(n4568), .Y(n4573) );
INVX2TS U2720 ( .A(n4216), .Y(n4218) );
NOR2X1TS U2721 ( .A(n8097), .B(n8468), .Y(n8085) );
AOI222X1TS U2722 ( .A0(n7060), .A1(n7044), .B0(n7058), .B1(Op_MX[3]), .C0(
n7057), .C1(n6897), .Y(n6881) );
INVX2TS U2723 ( .A(n4176), .Y(n4178) );
AOI222X1TS U2724 ( .A0(n7083), .A1(n7082), .B0(n7081), .B1(Op_MX[9]), .C0(
n7080), .C1(n7079), .Y(n7084) );
INVX2TS U2725 ( .A(n4250), .Y(n4252) );
OAI21X1TS U2726 ( .A0(n6053), .A1(n5861), .B0(n3644), .Y(n3645) );
BUFX8TS U2727 ( .A(n3853), .Y(n5904) );
OR2X2TS U2728 ( .A(n4551), .B(Sgf_operation_ODD1_Q_middle[54]), .Y(n4638) );
NOR2X1TS U2729 ( .A(n8126), .B(Sgf_normalized_result[4]), .Y(n8109) );
NAND2X4TS U2730 ( .A(n6232), .B(n6230), .Y(n6458) );
NAND2X2TS U2731 ( .A(n4544), .B(n4543), .Y(n4547) );
CLKMX2X2TS U2732 ( .A(Op_MX[54]), .B(exp_oper_result[2]), .S0(n846), .Y(
S_Oper_A_exp[2]) );
NAND2X4TS U2733 ( .A(n1064), .B(n1093), .Y(n1121) );
NAND2X2TS U2734 ( .A(n1252), .B(n1251), .Y(n5399) );
OR2X2TS U2735 ( .A(n4536), .B(n4535), .Y(n4540) );
CLKMX2X2TS U2736 ( .A(Op_MX[58]), .B(exp_oper_result[6]), .S0(n847), .Y(
S_Oper_A_exp[6]) );
CLKMX2X2TS U2737 ( .A(Op_MX[59]), .B(exp_oper_result[7]), .S0(n847), .Y(
S_Oper_A_exp[7]) );
CLKMX2X2TS U2738 ( .A(Op_MX[60]), .B(exp_oper_result[8]), .S0(n847), .Y(
S_Oper_A_exp[8]) );
OR2X2TS U2739 ( .A(n4511), .B(n4510), .Y(n4518) );
CLKMX2X2TS U2740 ( .A(Op_MX[61]), .B(exp_oper_result[9]), .S0(n847), .Y(
S_Oper_A_exp[9]) );
CLKMX2X2TS U2741 ( .A(Op_MX[62]), .B(exp_oper_result[10]), .S0(n847), .Y(
S_Oper_A_exp[10]) );
NOR2X6TS U2742 ( .A(n7533), .B(n7535), .Y(n8366) );
NOR2X4TS U2743 ( .A(n6287), .B(n6395), .Y(n3818) );
NAND2X4TS U2744 ( .A(n1793), .B(n1798), .Y(n1791) );
OAI21X4TS U2745 ( .A0(n7534), .A1(n4649), .B0(n7533), .Y(n8189) );
CLKAND2X2TS U2746 ( .A(n6946), .B(n874), .Y(n4741) );
BUFX8TS U2747 ( .A(n6512), .Y(n6786) );
INVX2TS U2748 ( .A(n1327), .Y(n1310) );
INVX2TS U2749 ( .A(n2241), .Y(n2005) );
AND2X2TS U2750 ( .A(n7078), .B(n8414), .Y(n6936) );
CLKAND2X2TS U2751 ( .A(n7078), .B(n826), .Y(n7091) );
AND2X2TS U2752 ( .A(n7078), .B(n6958), .Y(mult_x_24_n1100) );
CLKAND2X2TS U2753 ( .A(n7078), .B(n6863), .Y(mult_x_24_n1105) );
INVX1TS U2754 ( .A(n7940), .Y(n7941) );
ADDFHX2TS U2755 ( .A(Sgf_operation_ODD1_Q_middle[40]), .B(n7631), .CI(n4446),
.CO(n4452), .S(n4451) );
INVX4TS U2756 ( .A(n2205), .Y(n3853) );
OR2X2TS U2757 ( .A(n4542), .B(Sgf_operation_ODD1_Q_middle[52]), .Y(n4543) );
INVX1TS U2758 ( .A(n7993), .Y(n7994) );
AND2X2TS U2759 ( .A(Op_MY[26]), .B(n8403), .Y(n6217) );
INVX2TS U2760 ( .A(n1455), .Y(n1444) );
NOR2X1TS U2761 ( .A(n8058), .B(n7526), .Y(n7528) );
NOR2X1TS U2762 ( .A(n7940), .B(n7524), .Y(n7525) );
ADDFHX2TS U2763 ( .A(Sgf_operation_ODD1_Q_middle[16]), .B(n3964), .CI(n3963),
.CO(n3965), .S(n4001) );
OR2X2TS U2764 ( .A(n4007), .B(Sgf_operation_ODD1_Q_middle[1]), .Y(n4010) );
INVX2TS U2765 ( .A(n1670), .Y(n1604) );
ADDFHX2TS U2766 ( .A(Sgf_operation_ODD1_Q_middle[18]), .B(n3970), .CI(n3969),
.CO(n3973), .S(n3972) );
NOR2X1TS U2767 ( .A(n7721), .B(n7520), .Y(n7521) );
NOR2X1TS U2768 ( .A(n7826), .B(n7517), .Y(n7518) );
NAND2X4TS U2769 ( .A(n902), .B(n855), .Y(n3646) );
ADDFHX2TS U2770 ( .A(Sgf_operation_ODD1_Q_middle[19]), .B(n3977), .CI(n3976),
.CO(n3985), .S(n3974) );
ADDFHX2TS U2771 ( .A(Sgf_operation_ODD1_Q_middle[14]), .B(n4053), .CI(n4052),
.CO(n4070), .S(n4069) );
INVX1TS U2772 ( .A(n8108), .Y(n8126) );
AND2X2TS U2773 ( .A(n6946), .B(n6945), .Y(mult_x_24_n1094) );
INVX6TS U2774 ( .A(n1034), .Y(n3866) );
XOR2X2TS U2775 ( .A(Op_MX[10]), .B(Op_MX[37]), .Y(n1377) );
INVX12TS U2776 ( .A(n793), .Y(n7492) );
XOR2X2TS U2777 ( .A(n747), .B(n748), .Y(n1401) );
XOR2X2TS U2778 ( .A(n3628), .B(n7493), .Y(n3629) );
OR2X2TS U2779 ( .A(n903), .B(n8374), .Y(n996) );
NAND2X4TS U2780 ( .A(n3572), .B(n4820), .Y(n3592) );
CLKINVX6TS U2781 ( .A(n3281), .Y(n901) );
XOR2X4TS U2782 ( .A(n742), .B(n1034), .Y(n6058) );
OA21X1TS U2783 ( .A0(n5437), .A1(n4965), .B0(n5214), .Y(n742) );
OAI21X2TS U2784 ( .A0(n6053), .A1(n4671), .B0(n4676), .Y(n4677) );
OAI21X1TS U2785 ( .A0(n7379), .A1(n7378), .B0(n7377), .Y(n7384) );
INVX8TS U2786 ( .A(n752), .Y(n753) );
OAI21X1TS U2787 ( .A0(n4888), .A1(n4877), .B0(n4876), .Y(n4878) );
NOR2X4TS U2788 ( .A(n7068), .B(n7056), .Y(n6353) );
XOR2X2TS U2789 ( .A(n7329), .B(n763), .Y(Sgf_operation_ODD1_middle_N46) );
NAND2X2TS U2790 ( .A(n4985), .B(n4980), .Y(n1228) );
NOR2X4TS U2791 ( .A(mult_x_23_n898), .B(mult_x_23_n905), .Y(n5333) );
BUFX6TS U2792 ( .A(n1130), .Y(n6819) );
OAI21X2TS U2793 ( .A0(n6194), .A1(n6200), .B0(n6195), .Y(n1107) );
NAND2X6TS U2794 ( .A(n771), .B(n791), .Y(n7315) );
OR2X4TS U2795 ( .A(n3544), .B(n3543), .Y(n771) );
XNOR2X2TS U2796 ( .A(n3349), .B(n3383), .Y(n2992) );
BUFX4TS U2797 ( .A(n3717), .Y(n5701) );
OAI21X2TS U2798 ( .A0(Op_MX[6]), .A1(Op_MX[33]), .B0(Op_MX[5]), .Y(n1342) );
OAI21X1TS U2799 ( .A0(n7379), .A1(n7253), .B0(n7252), .Y(n7256) );
OAI21X2TS U2800 ( .A0(n7293), .A1(n7300), .B0(n7301), .Y(n4823) );
XNOR2X2TS U2801 ( .A(n899), .B(n3074), .Y(n3075) );
CLKXOR2X2TS U2802 ( .A(n1050), .B(n8445), .Y(n1104) );
OAI22X1TS U2803 ( .A0(n1651), .A1(n3427), .B0(n1623), .B1(n1622), .Y(n1652)
);
AOI222X2TS U2804 ( .A0(n7072), .A1(n6886), .B0(n7070), .B1(n7022), .C0(n6473), .C1(n7020), .Y(n4801) );
OAI21X4TS U2805 ( .A0(n7776), .A1(n4632), .B0(n4631), .Y(n4633) );
ADDFHX2TS U2806 ( .A(n2104), .B(n2103), .CI(n2102), .CO(n2115), .S(n2110) );
ADDFHX2TS U2807 ( .A(n3241), .B(n3240), .CI(n3239), .CO(n3315), .S(n3263) );
ADDFHX2TS U2808 ( .A(n3164), .B(n3163), .CI(n3162), .CO(n3216), .S(n3205) );
NAND2X4TS U2809 ( .A(mult_x_23_n835), .B(mult_x_23_n845), .Y(n5312) );
NAND2X4TS U2810 ( .A(n3601), .B(n3646), .Y(n1222) );
OAI21X1TS U2811 ( .A0(n5896), .A1(n5684), .B0(n5683), .Y(n5685) );
OAI21X4TS U2812 ( .A0(n4250), .A1(n4246), .B0(n4251), .Y(n4242) );
XNOR2X2TS U2813 ( .A(n856), .B(n1611), .Y(n1483) );
NAND2X4TS U2814 ( .A(n1318), .B(n1317), .Y(n1413) );
NAND2X2TS U2815 ( .A(n4870), .B(n5221), .Y(n4872) );
ADDFHX2TS U2816 ( .A(n3505), .B(n3504), .CI(n3503), .CO(n3510), .S(n3500) );
NOR2X6TS U2817 ( .A(mult_x_23_n888), .B(mult_x_23_n897), .Y(n5335) );
XOR2X2TS U2818 ( .A(n6546), .B(n6827), .Y(mult_x_24_n1520) );
NAND2X2TS U2819 ( .A(n6268), .B(n6245), .Y(n6247) );
ADDFHX2TS U2820 ( .A(n2150), .B(n2149), .CI(n2148), .CO(n2174), .S(n2167) );
INVX12TS U2821 ( .A(n944), .Y(n2869) );
ADDFX2TS U2822 ( .A(Sgf_operation_ODD1_Q_middle[17]), .B(n3968), .CI(n3967),
.CO(n3971), .S(n3966) );
XOR2X2TS U2823 ( .A(n4119), .B(n4118), .Y(n4420) );
ADDFHX2TS U2824 ( .A(n3247), .B(n3246), .CI(n3245), .CO(n3274), .S(n3243) );
NAND2X6TS U2825 ( .A(n3301), .B(n1381), .Y(n1751) );
NOR2X4TS U2826 ( .A(n6155), .B(n6153), .Y(n6148) );
OAI21X2TS U2827 ( .A0(n6092), .A1(n6088), .B0(n6089), .Y(n5236) );
NOR2X2TS U2828 ( .A(n5402), .B(n5535), .Y(n1254) );
ADDFHX2TS U2829 ( .A(n1524), .B(n1523), .CI(n1522), .CO(n1533), .S(n1516) );
XOR2X2TS U2830 ( .A(Op_MX[29]), .B(Op_MX[2]), .Y(n1417) );
AOI21X4TS U2831 ( .A0(n5013), .A1(n5017), .B0(n1281), .Y(n1282) );
OAI21X4TS U2832 ( .A0(n5026), .A1(n1287), .B0(n5028), .Y(n5013) );
ADDFHX2TS U2833 ( .A(n2372), .B(n2371), .CI(n2370), .CO(n2405), .S(n2411) );
OAI21X4TS U2834 ( .A0(Op_MX[4]), .A1(Op_MX[31]), .B0(Op_MX[3]), .Y(n1314) );
OAI21X1TS U2835 ( .A0(n5957), .A1(n5978), .B0(n5704), .Y(n5705) );
OAI21X1TS U2836 ( .A0(n5957), .A1(n5904), .B0(n4979), .Y(mult_x_23_n1250) );
INVX8TS U2837 ( .A(n4974), .Y(n4999) );
XNOR2X2TS U2838 ( .A(n5219), .B(n5218), .Y(Sgf_operation_ODD1_right_N32) );
NAND2X2TS U2839 ( .A(n6213), .B(n6214), .Y(n6212) );
ADDFHX2TS U2840 ( .A(n1660), .B(n1659), .CI(n1658), .CO(n1693), .S(n1683) );
NAND2X4TS U2841 ( .A(n1342), .B(n1341), .Y(n1394) );
ADDFHX2TS U2842 ( .A(n1487), .B(n1486), .CI(n1485), .CO(n1640), .S(n1497) );
ADDFHX2TS U2843 ( .A(n2043), .B(n2042), .CI(n2041), .CO(n2011), .S(n2056) );
AOI21X2TS U2844 ( .A0(n7325), .A1(n4821), .B0(n3917), .Y(n3918) );
AO21X4TS U2845 ( .A0(n744), .A1(n745), .B0(n746), .Y(n4697) );
INVX4TS U2846 ( .A(n891), .Y(n744) );
AO21X2TS U2847 ( .A0(n7325), .A1(n4694), .B0(n4693), .Y(n746) );
NAND2X4TS U2848 ( .A(n2449), .B(n2450), .Y(n7438) );
OAI21X1TS U2849 ( .A0(n7362), .A1(n7379), .B0(n7361), .Y(n7367) );
ADDFHX2TS U2850 ( .A(n1870), .B(n1869), .CI(n1868), .CO(n2180), .S(n1919) );
ADDFHX2TS U2851 ( .A(n1824), .B(n1823), .CI(n1822), .CO(n1916), .S(n1853) );
OAI21X2TS U2852 ( .A0(n6092), .A1(n5243), .B0(n5242), .Y(n5248) );
CMPR42X2TS U2853 ( .A(mult_x_24_n703), .B(mult_x_24_n707), .C(
mult_x_24_n1429), .D(mult_x_24_n1402), .ICI(mult_x_24_n704), .S(
mult_x_24_n702), .ICO(mult_x_24_n700), .CO(mult_x_24_n701) );
OAI21X2TS U2854 ( .A0(n7430), .A1(n3578), .B0(n3577), .Y(n3590) );
OAI21X2TS U2855 ( .A0(n7306), .A1(n4826), .B0(n7312), .Y(n4827) );
NOR2X4TS U2856 ( .A(n3564), .B(n3563), .Y(n4826) );
XNOR2X2TS U2857 ( .A(n856), .B(n1740), .Y(n1689) );
XNOR2X2TS U2858 ( .A(n3330), .B(n2221), .Y(n2974) );
OAI21X2TS U2859 ( .A0(n7295), .A1(n3592), .B0(n3591), .Y(n3593) );
OAI21X2TS U2860 ( .A0(n979), .A1(n6035), .B0(n5438), .Y(n5439) );
NAND2X4TS U2861 ( .A(n7323), .B(n3594), .Y(n3596) );
NOR2X4TS U2862 ( .A(n7305), .B(n4826), .Y(n4828) );
OAI21X2TS U2863 ( .A0(n6092), .A1(n5250), .B0(n5249), .Y(n5253) );
INVX12TS U2864 ( .A(n4834), .Y(n6092) );
INVX4TS U2865 ( .A(n1287), .Y(n5029) );
BUFX20TS U2866 ( .A(Op_MX[19]), .Y(n6930) );
CMPR42X2TS U2867 ( .A(n8444), .B(mult_x_24_n1094), .C(mult_x_24_n1092), .D(
mult_x_24_n1433), .ICI(mult_x_24_n1460), .S(mult_x_24_n726), .ICO(
mult_x_24_n724), .CO(mult_x_24_n725) );
AOI21X2TS U2868 ( .A0(n7325), .A1(n7318), .B0(n7317), .Y(n7319) );
OAI22X2TS U2869 ( .A0(n1748), .A1(n2940), .B0(n1718), .B1(n1717), .Y(n1749)
);
ADDFHX2TS U2870 ( .A(n3175), .B(n3174), .CI(n3173), .CO(n3261), .S(n3208) );
ADDFHX2TS U2871 ( .A(n3210), .B(n3209), .CI(n3208), .CO(n3239), .S(n3213) );
OAI21X2TS U2872 ( .A0(n891), .A1(n3919), .B0(n3918), .Y(n3921) );
XOR2X1TS U2873 ( .A(n6605), .B(n7051), .Y(mult_x_24_n1562) );
OAI21X1TS U2874 ( .A0(n7075), .A1(n6841), .B0(n6604), .Y(n6605) );
XOR2X4TS U2875 ( .A(n5110), .B(n976), .Y(Sgf_operation_ODD1_middle_N40) );
XOR2X4TS U2876 ( .A(Op_MX[29]), .B(Op_MX[28]), .Y(n3652) );
OAI21X4TS U2877 ( .A0(n5359), .A1(n5952), .B0(n5360), .Y(n3744) );
OAI21X4TS U2878 ( .A0(n6141), .A1(n6948), .B0(n6142), .Y(n956) );
NOR2X4TS U2879 ( .A(n6947), .B(n6141), .Y(n957) );
NAND2X4TS U2880 ( .A(n8005), .B(n4423), .Y(n4425) );
NAND2X4TS U2881 ( .A(n851), .B(n8374), .Y(n3601) );
OR2X4TS U2882 ( .A(n8374), .B(n851), .Y(n1002) );
NOR2X4TS U2883 ( .A(n851), .B(n848), .Y(n3655) );
NAND2X4TS U2884 ( .A(n851), .B(n848), .Y(n3679) );
OAI21X1TS U2885 ( .A0(n1001), .A1(n5569), .B0(n5832), .Y(n5833) );
OR2X4TS U2886 ( .A(mult_x_24_n778), .B(mult_x_24_n787), .Y(n4846) );
OAI21X4TS U2887 ( .A0(Op_MX[20]), .A1(Op_MX[47]), .B0(Op_MX[19]), .Y(n1989)
);
OAI21X4TS U2888 ( .A0(n5271), .A1(n5157), .B0(n5156), .Y(n5160) );
INVX12TS U2889 ( .A(n3772), .Y(n5271) );
INVX16TS U2890 ( .A(n6735), .Y(n815) );
AOI21X4TS U2891 ( .A0(n4846), .A1(n1189), .B0(n1188), .Y(n1190) );
XOR2X2TS U2892 ( .A(n7000), .B(n8373), .Y(mult_x_24_n1549) );
NOR2X6TS U2893 ( .A(mult_x_24_n1023), .B(mult_x_24_n1030), .Y(n6155) );
AOI222X4TS U2894 ( .A0(n6848), .A1(n6847), .B0(n7045), .B1(n6846), .C0(n6997), .C1(n6930), .Y(n6849) );
AOI222X1TS U2895 ( .A0(n6839), .A1(n6884), .B0(n7045), .B1(n7020), .C0(n6615), .C1(n7018), .Y(n5037) );
NOR2X4TS U2896 ( .A(Op_MY[35]), .B(Op_MY[8]), .Y(n1431) );
NAND2X4TS U2897 ( .A(Op_MY[35]), .B(Op_MY[8]), .Y(n1433) );
OAI21X2TS U2898 ( .A0(n8326), .A1(n8325), .B0(n8324), .Y(n8333) );
OAI21X4TS U2899 ( .A0(n4323), .A1(n4322), .B0(n4321), .Y(n4372) );
ADDFHX2TS U2900 ( .A(n1142), .B(n1141), .CI(n1140), .CO(n1156), .S(n1155) );
NOR2X6TS U2901 ( .A(n7775), .B(n4632), .Y(n4634) );
ADDFHX2TS U2902 ( .A(n2112), .B(n2111), .CI(n2110), .CO(n2141), .S(n2157) );
CLKINVX12TS U2903 ( .A(Op_MY[17]), .Y(n8444) );
NOR2X8TS U2904 ( .A(Op_MY[44]), .B(Op_MY[17]), .Y(n1780) );
CLKXOR2X2TS U2905 ( .A(n3671), .B(n5804), .Y(n5395) );
NOR2X2TS U2906 ( .A(n5394), .B(n5393), .Y(n5391) );
OAI21X2TS U2907 ( .A0(n7026), .A1(n6788), .B0(n4722), .Y(n4723) );
XOR2X4TS U2908 ( .A(n5040), .B(n7027), .Y(n5048) );
OAI21X2TS U2909 ( .A0(n7893), .A1(n7905), .B0(n7894), .Y(n4615) );
ADDFHX2TS U2910 ( .A(n4051), .B(Sgf_operation_ODD1_Q_middle[15]), .CI(n4050),
.CO(n4000), .S(n4071) );
OAI21X2TS U2911 ( .A0(n7919), .A1(n7930), .B0(n7920), .Y(n7888) );
OAI21X2TS U2912 ( .A0(n5293), .A1(n5301), .B0(n5294), .Y(n3759) );
CMPR42X2TS U2913 ( .A(mult_x_23_n839), .B(mult_x_23_n1466), .C(
mult_x_23_n1414), .D(mult_x_23_n1440), .ICI(mult_x_23_n840), .S(
mult_x_23_n827), .ICO(mult_x_23_n825), .CO(mult_x_23_n826) );
NAND2X4TS U2914 ( .A(n1075), .B(n1074), .Y(n1040) );
ADDFHX2TS U2915 ( .A(n3733), .B(n3732), .CI(n3731), .CO(n3734), .S(n3714) );
XOR2X4TS U2916 ( .A(n4561), .B(n4560), .Y(n4605) );
INVX16TS U2917 ( .A(n6735), .Y(n816) );
CMPR42X2TS U2918 ( .A(mult_x_24_n1465), .B(mult_x_24_n1519), .C(
mult_x_24_n1492), .D(mult_x_24_n765), .ICI(mult_x_24_n774), .S(
mult_x_24_n763), .ICO(mult_x_24_n761), .CO(mult_x_24_n762) );
ADDFHX2TS U2919 ( .A(n5995), .B(n5994), .CI(n5993), .CO(n3801), .S(
mult_x_23_n938) );
AOI21X4TS U2920 ( .A0(n5352), .A1(n5350), .B0(n3747), .Y(n3748) );
XOR2X1TS U2921 ( .A(n3931), .B(n969), .Y(Sgf_operation_ODD1_middle_N50) );
OAI21X2TS U2922 ( .A0(n7295), .A1(n3923), .B0(n3922), .Y(n3924) );
NOR2X4TS U2923 ( .A(mult_x_23_n877), .B(mult_x_23_n868), .Y(n5324) );
ADDFHX4TS U2924 ( .A(n4691), .B(n4690), .CI(n4689), .CO(mult_x_23_n882), .S(
mult_x_23_n883) );
NAND2X4TS U2925 ( .A(n6449), .B(n6462), .Y(n1206) );
BUFX8TS U2926 ( .A(Op_MX[20]), .Y(n876) );
XOR2X2TS U2927 ( .A(Op_MX[20]), .B(Op_MX[47]), .Y(n1985) );
NOR2X6TS U2928 ( .A(mult_x_23_n698), .B(mult_x_23_n707), .Y(n4857) );
CMPR42X2TS U2929 ( .A(n793), .B(mult_x_23_n733), .C(mult_x_23_n1250), .D(
mult_x_23_n1300), .ICI(mult_x_23_n1352), .S(mult_x_23_n723), .ICO(
mult_x_23_n714), .CO(mult_x_23_n722) );
NOR2X6TS U2930 ( .A(n1176), .B(n6127), .Y(n1178) );
OR2X8TS U2931 ( .A(mult_x_24_n955), .B(mult_x_24_n965), .Y(n6124) );
XOR2X2TS U2932 ( .A(n4706), .B(n6220), .Y(n5074) );
OAI21X2TS U2933 ( .A0(n5043), .A1(n6792), .B0(n4705), .Y(n4706) );
NOR2X4TS U2934 ( .A(n7508), .B(n850), .Y(n3618) );
NOR2X8TS U2935 ( .A(n7315), .B(n3555), .Y(n4821) );
NOR2X4TS U2936 ( .A(n7292), .B(n7294), .Y(n7297) );
XNOR2X2TS U2937 ( .A(n3384), .B(n3167), .Y(n3003) );
XNOR2X2TS U2938 ( .A(n3334), .B(n3167), .Y(n2990) );
BUFX20TS U2939 ( .A(n3249), .Y(n3334) );
OAI21X4TS U2940 ( .A0(n5335), .A1(n5340), .B0(n5336), .Y(n5987) );
CMPR22X2TS U2941 ( .A(n6087), .B(n6086), .CO(n5138), .S(mult_x_23_n903) );
NOR2X4TS U2942 ( .A(n3723), .B(n3618), .Y(n4975) );
NOR2X2TS U2943 ( .A(n5027), .B(n1287), .Y(n5012) );
OAI21X1TS U2944 ( .A0(n6933), .A1(n7074), .B0(n6408), .Y(n6409) );
BUFX12TS U2945 ( .A(n5494), .Y(n6031) );
NOR2X4TS U2946 ( .A(n7238), .B(n7239), .Y(n7335) );
NAND2X2TS U2947 ( .A(Op_MX[29]), .B(Op_MX[2]), .Y(n1318) );
ADDFHX2TS U2948 ( .A(n3274), .B(n3273), .CI(n3272), .CO(n3375), .S(n3270) );
OAI21X1TS U2949 ( .A0(n5876), .A1(n5985), .B0(n5651), .Y(n5652) );
OAI21X1TS U2950 ( .A0(n5876), .A1(n5978), .B0(n5702), .Y(n5703) );
OAI21X1TS U2951 ( .A0(n5876), .A1(n6014), .B0(n5550), .Y(n5551) );
OAI21X1TS U2952 ( .A0(n5876), .A1(n6035), .B0(n5518), .Y(n5519) );
AOI21X2TS U2953 ( .A0(n4866), .A1(n1028), .B0(n4865), .Y(n4867) );
OAI21X4TS U2954 ( .A0(n4161), .A1(n4003), .B0(n3995), .Y(n4142) );
AOI21X2TS U2955 ( .A0(n4334), .A1(n4002), .B0(n3975), .Y(n4161) );
OAI21X2TS U2956 ( .A0(n4595), .A1(n4591), .B0(n4592), .Y(n4585) );
NAND2X4TS U2957 ( .A(mult_x_23_n683), .B(mult_x_23_n689), .Y(n5158) );
OAI21X4TS U2958 ( .A0(n5271), .A1(n5261), .B0(n5260), .Y(n5264) );
AOI21X4TS U2959 ( .A0(n5259), .A1(n5258), .B0(n5257), .Y(n5260) );
AOI21X2TS U2960 ( .A0(n8103), .A1(n8062), .B0(n8061), .Y(n8080) );
OAI21X2TS U2961 ( .A0(n4236), .A1(n8202), .B0(n4235), .Y(n8213) );
NAND2X1TS U2962 ( .A(n781), .B(n731), .Y(n4236) );
AOI21X2TS U2963 ( .A0(n986), .A1(n8198), .B0(n4231), .Y(n8202) );
OAI21X2TS U2964 ( .A0(n7026), .A1(n6792), .B0(n5077), .Y(n5078) );
NOR2X4TS U2965 ( .A(n6958), .B(n910), .Y(n6444) );
INVX4TS U2966 ( .A(n6362), .Y(n6422) );
NOR2X4TS U2967 ( .A(n7079), .B(n826), .Y(n6231) );
NOR2X8TS U2968 ( .A(n3517), .B(n3518), .Y(n7239) );
ADDFHX4TS U2969 ( .A(n3496), .B(n3495), .CI(n3494), .CO(n3532), .S(n3529) );
XNOR2X2TS U2970 ( .A(n915), .B(n3383), .Y(n3420) );
OAI21X1TS U2971 ( .A0(n6026), .A1(n5665), .B0(n5691), .Y(n5692) );
OAI21X2TS U2972 ( .A0(Op_MX[10]), .A1(Op_MX[37]), .B0(Op_MX[9]), .Y(n1359)
);
OAI21X1TS U2973 ( .A0(n891), .A1(n7330), .B0(n5108), .Y(n5110) );
OAI21X1TS U2974 ( .A0(n891), .A1(n3912), .B0(n3911), .Y(n3916) );
ADDFHX2TS U2975 ( .A(n2986), .B(n2985), .CI(n2984), .CO(n3013), .S(n2981) );
OR2X4TS U2976 ( .A(n3534), .B(n3533), .Y(n7432) );
ADDFHX4TS U2977 ( .A(n3469), .B(n3468), .CI(n3467), .CO(n3534), .S(n3531) );
XNOR2X2TS U2978 ( .A(n857), .B(n1747), .Y(n1817) );
NOR2X6TS U2979 ( .A(n4856), .B(n4857), .Y(n4917) );
NOR2X4TS U2980 ( .A(n4976), .B(n4984), .Y(n1229) );
CMPR42X2TS U2981 ( .A(mult_x_23_n730), .B(mult_x_23_n1274), .C(
mult_x_23_n1326), .D(mult_x_23_n1378), .ICI(mult_x_23_n731), .S(
mult_x_23_n721), .ICO(mult_x_23_n719), .CO(mult_x_23_n720) );
NOR2X4TS U2982 ( .A(Op_MY[36]), .B(n5802), .Y(n4976) );
OAI22X4TS U2983 ( .A0(n1801), .A1(n2976), .B0(n3350), .B1(n3005), .Y(n1816)
);
AND2X4TS U2984 ( .A(n1364), .B(n1363), .Y(n749) );
NOR2X4TS U2985 ( .A(n1063), .B(n1062), .Y(n1118) );
NOR2X4TS U2986 ( .A(n6874), .B(n8414), .Y(n1144) );
ADDFHX4TS U2987 ( .A(n2432), .B(n2431), .CI(n2430), .CO(n2421), .S(n2444) );
ADDFHX4TS U2988 ( .A(n2402), .B(n2401), .CI(n2400), .CO(n2431), .S(n2415) );
OAI21X2TS U2989 ( .A0(n6778), .A1(n6984), .B0(n6552), .Y(n6553) );
INVX12TS U2990 ( .A(n6292), .Y(n6778) );
CMPR42X2TS U2991 ( .A(mult_x_23_n1383), .B(mult_x_23_n1305), .C(
mult_x_23_n1357), .D(mult_x_23_n1409), .ICI(mult_x_23_n781), .S(
mult_x_23_n772), .ICO(mult_x_23_n770), .CO(mult_x_23_n771) );
NAND2X4TS U2992 ( .A(mult_x_24_n1015), .B(mult_x_24_n1022), .Y(n6149) );
OAI21X2TS U2993 ( .A0(n979), .A1(n5985), .B0(n5656), .Y(n5657) );
ADDFHX2TS U2994 ( .A(n1890), .B(n1889), .CI(n1888), .CO(n2155), .S(n1914) );
OAI22X4TS U2995 ( .A0(n3179), .A1(n3220), .B0(n1427), .B1(n2303), .Y(n1476)
);
XNOR2X1TS U2996 ( .A(n2223), .B(n2221), .Y(n2224) );
OAI22X2TS U2997 ( .A0(n2579), .A1(n930), .B0(n2616), .B1(n3360), .Y(n2619)
);
XOR2X4TS U2998 ( .A(Op_MX[4]), .B(Op_MX[31]), .Y(n1321) );
NOR2X4TS U2999 ( .A(n4264), .B(n4266), .Y(n4033) );
NOR2X4TS U3000 ( .A(n4031), .B(n4030), .Y(n4266) );
NOR2X4TS U3001 ( .A(n5062), .B(n5066), .Y(n5069) );
AOI21X4TS U3002 ( .A0(n4639), .A1(n4638), .B0(n4637), .Y(n4641) );
OAI21X4TS U3003 ( .A0(n4549), .A1(n4548), .B0(n4547), .Y(n4639) );
ADDFHX2TS U3004 ( .A(n2603), .B(n2602), .CI(n2601), .CO(n2640), .S(n2609) );
OAI21X4TS U3005 ( .A0(Op_MX[14]), .A1(Op_MX[41]), .B0(Op_MX[13]), .Y(n1715)
);
NAND2X4TS U3006 ( .A(n6433), .B(n6424), .Y(n1208) );
OAI21X1TS U3007 ( .A0(n729), .A1(n6681), .B0(n6676), .Y(n6677) );
OAI22X1TS U3008 ( .A0(n2367), .A1(n2560), .B0(n2302), .B1(n2510), .Y(n2358)
);
OAI22X1TS U3009 ( .A0(n2511), .A1(n2560), .B0(n2561), .B1(n2510), .Y(n2587)
);
OAI22X2TS U3010 ( .A0(n1511), .A1(n2559), .B0(n2560), .B1(n1508), .Y(n1512)
);
AO21X1TS U3011 ( .A0(n2628), .A1(n2627), .B0(n736), .Y(n2712) );
OAI21X1TS U3012 ( .A0(n7316), .A1(n4692), .B0(n7322), .Y(n4693) );
XNOR2X4TS U3013 ( .A(n909), .B(n3409), .Y(n2998) );
NAND2X2TS U3014 ( .A(Op_MX[4]), .B(Op_MX[31]), .Y(n1315) );
AOI21X4TS U3015 ( .A0(n7998), .A1(n4427), .B0(n4426), .Y(n4428) );
ADDFHX4TS U3016 ( .A(n4041), .B(Sgf_operation_ODD1_Q_middle[9]), .CI(n4040),
.CO(n4058), .S(n4057) );
CLKINVX12TS U3017 ( .A(n2281), .Y(n818) );
XNOR2X2TS U3018 ( .A(n3278), .B(n2468), .Y(n2311) );
OAI21X4TS U3019 ( .A0(n816), .A1(n3811), .B0(n3810), .Y(n3835) );
AOI222X2TS U3020 ( .A0(n7060), .A1(n7022), .B0(n7058), .B1(n6243), .C0(n7057), .C1(n7018), .Y(n4747) );
AOI21X4TS U3021 ( .A0(n7830), .A1(n4624), .B0(n4623), .Y(n7776) );
OAI21X2TS U3022 ( .A0(n7835), .A1(n7846), .B0(n7836), .Y(n4623) );
NOR2X2TS U3023 ( .A(n4586), .B(n4478), .Y(n4480) );
XNOR2X2TS U3024 ( .A(n4513), .B(n4512), .Y(n4622) );
NOR2BX4TS U3025 ( .AN(n1006), .B(n766), .Y(n3669) );
CMPR42X2TS U3026 ( .A(mult_x_24_n939), .B(mult_x_24_n1480), .C(
mult_x_24_n1561), .D(mult_x_24_n1534), .ICI(mult_x_24_n1615), .S(
mult_x_24_n937), .ICO(mult_x_24_n935), .CO(mult_x_24_n936) );
XOR2X2TS U3027 ( .A(n4809), .B(n7076), .Y(n5209) );
CMPR42X2TS U3028 ( .A(mult_x_23_n1439), .B(mult_x_23_n828), .C(
mult_x_23_n1361), .D(mult_x_23_n1465), .ICI(mult_x_23_n829), .S(
mult_x_23_n816), .ICO(mult_x_23_n814), .CO(mult_x_23_n815) );
NOR2X8TS U3029 ( .A(n3615), .B(n3614), .Y(n6065) );
XNOR2X2TS U3030 ( .A(n3349), .B(n2583), .Y(n2460) );
ADDFHX2TS U3031 ( .A(n2821), .B(n2820), .CI(n2819), .CO(n2903), .S(n2854) );
ADDFHX2TS U3032 ( .A(n2832), .B(n2831), .CI(n2830), .CO(n2861), .S(n2819) );
XOR2X2TS U3033 ( .A(n2825), .B(n2650), .Y(n2314) );
XNOR2X2TS U3034 ( .A(n856), .B(n2650), .Y(n2517) );
XNOR2X2TS U3035 ( .A(n860), .B(n2650), .Y(n2479) );
AO21X4TS U3036 ( .A0(n750), .A1(n751), .B0(n772), .Y(n2197) );
XOR2X4TS U3037 ( .A(n2261), .B(Op_MY[25]), .Y(n752) );
ADDFHX2TS U3038 ( .A(n2626), .B(n2625), .CI(n2624), .CO(n2748), .S(n2660) );
NOR2X6TS U3039 ( .A(n2913), .B(n2914), .Y(n2915) );
XNOR2X4TS U3040 ( .A(n911), .B(n2784), .Y(n2521) );
CMPR42X2TS U3041 ( .A(mult_x_24_n1431), .B(mult_x_24_n1404), .C(
mult_x_24_n713), .D(mult_x_24_n718), .ICI(mult_x_24_n715), .S(
mult_x_24_n711), .ICO(mult_x_24_n709), .CO(mult_x_24_n710) );
NOR2X4TS U3042 ( .A(n6310), .B(n6314), .Y(n1216) );
ADDFHX4TS U3043 ( .A(n2438), .B(n2437), .CI(n2436), .CO(n2441), .S(n2442) );
ADDFHX4TS U3044 ( .A(n2414), .B(n2413), .CI(n2412), .CO(n2423), .S(n2437) );
ADDFHX4TS U3045 ( .A(n2387), .B(n2386), .CI(n2385), .CO(n2414), .S(n2410) );
ADDFX2TS U3046 ( .A(n2390), .B(n2389), .CI(n2388), .CO(n2413), .S(n2416) );
XNOR2X2TS U3047 ( .A(n906), .B(n2784), .Y(n2313) );
BUFX6TS U3048 ( .A(n6105), .Y(n6106) );
NOR2X6TS U3049 ( .A(mult_x_24_n997), .B(mult_x_24_n1006), .Y(n6141) );
XOR2X2TS U3050 ( .A(n4368), .B(n4367), .Y(n4385) );
NOR2X2TS U3051 ( .A(n8264), .B(n8266), .Y(n8322) );
ADDFHX2TS U3052 ( .A(n1899), .B(n1898), .CI(n1897), .CO(n2168), .S(n1869) );
NOR2X4TS U3053 ( .A(n4700), .B(n5601), .Y(n4995) );
NOR2X4TS U3054 ( .A(n6016), .B(n828), .Y(n4700) );
NAND2X4TS U3055 ( .A(n4995), .B(n1231), .Y(n1233) );
OAI21X1TS U3056 ( .A0(n6043), .A1(n5665), .B0(n5688), .Y(n5689) );
XNOR2X2TS U3057 ( .A(n2878), .B(Op_MX[26]), .Y(n2829) );
NAND2BX1TS U3058 ( .AN(n7232), .B(n2264), .Y(n1801) );
INVX12TS U3059 ( .A(n1768), .Y(n2281) );
ADDFHX2TS U3060 ( .A(n2907), .B(n2906), .CI(n2905), .CO(n3211), .S(n2908) );
ADDFHX2TS U3061 ( .A(n2782), .B(n2781), .CI(n2780), .CO(n2846), .S(n2791) );
OAI21X1TS U3062 ( .A0(n6053), .A1(n5665), .B0(n997), .Y(n3636) );
OAI21X1TS U3063 ( .A0(n6053), .A1(n5569), .B0(n3784), .Y(n3785) );
OAI21X1TS U3064 ( .A0(n6053), .A1(n4965), .B0(n4970), .Y(n4971) );
AOI21X4TS U3065 ( .A0(n6173), .A1(n6171), .B0(n1166), .Y(n1167) );
ADDFHX2TS U3066 ( .A(n6223), .B(mult_x_24_n724), .CI(n6222), .CO(
mult_x_24_n718), .S(mult_x_24_n719) );
NAND2X2TS U3067 ( .A(mult_x_24_n716), .B(mult_x_24_n711), .Y(n5028) );
NAND2X4TS U3068 ( .A(mult_x_24_n944), .B(mult_x_24_n954), .Y(n6118) );
XNOR2X2TS U3069 ( .A(n2198), .B(n2939), .Y(n1717) );
INVX4TS U3070 ( .A(n2184), .Y(n966) );
XNOR2X4TS U3071 ( .A(Op_MX[3]), .B(Op_MX[30]), .Y(n1418) );
ADDFHX2TS U3072 ( .A(n1852), .B(n1851), .CI(n1850), .CO(n1926), .S(n1924) );
OAI22X2TS U3073 ( .A0(n1707), .A1(n2477), .B0(n1811), .B1(n1974), .Y(n1852)
);
OAI22X2TS U3074 ( .A0(n1813), .A1(n1812), .B0(n1811), .B1(n1810), .Y(n1859)
);
XNOR2X2TS U3075 ( .A(n2873), .B(n2254), .Y(n1811) );
NOR2X6TS U3076 ( .A(n3528), .B(n3527), .Y(n7410) );
BUFX20TS U3077 ( .A(n2815), .Y(n914) );
ADDFHX2TS U3078 ( .A(n2329), .B(n2328), .CI(n2327), .CO(n2548), .S(n2384) );
ADDFHX2TS U3079 ( .A(n2381), .B(n2380), .CI(n2379), .CO(n2383), .S(n2418) );
ADDFHX2TS U3080 ( .A(n2341), .B(n2340), .CI(n2339), .CO(n2343), .S(n2379) );
XOR2X2TS U3081 ( .A(Op_MY[1]), .B(n6934), .Y(n1048) );
NOR2X4TS U3082 ( .A(n4306), .B(n4075), .Y(n4077) );
OAI21X1TS U3083 ( .A0(n5887), .A1(n6083), .B0(n5767), .Y(n5768) );
XNOR2X2TS U3084 ( .A(n2261), .B(Op_MY[25]), .Y(n754) );
OAI21X1TS U3085 ( .A0(n7379), .A1(n7368), .B0(n7124), .Y(n7372) );
OAI21X2TS U3086 ( .A0(n8266), .A1(n8273), .B0(n8267), .Y(n8323) );
XNOR2X4TS U3087 ( .A(Op_MX[5]), .B(Op_MX[32]), .Y(n1397) );
BUFX12TS U3088 ( .A(Op_MX[5]), .Y(n6874) );
OAI21X2TS U3089 ( .A0(n7430), .A1(n7327), .B0(n7326), .Y(n7329) );
AOI21X2TS U3090 ( .A0(n7325), .A1(n771), .B0(n7324), .Y(n7326) );
OAI22X2TS U3091 ( .A0(n2634), .A1(n3201), .B0(n2723), .B1(n2817), .Y(n2701)
);
NOR2X8TS U3092 ( .A(n5220), .B(n1191), .Y(n4862) );
NAND2X4TS U3093 ( .A(n5229), .B(n4846), .Y(n1191) );
XNOR2X1TS U3094 ( .A(n908), .B(n2939), .Y(n2044) );
OAI22X2TS U3095 ( .A0(n1621), .A1(n3427), .B0(n3428), .B1(n3426), .Y(n1653)
);
XNOR2X4TS U3096 ( .A(n8010), .B(n8009), .Y(n8011) );
OAI21X2TS U3097 ( .A0(n8021), .A1(n8017), .B0(n8018), .Y(n8010) );
NOR2X2TS U3098 ( .A(n8281), .B(n8283), .Y(n4387) );
NAND2X4TS U3099 ( .A(Op_MY[44]), .B(Op_MY[17]), .Y(n1778) );
OAI22X2TS U3100 ( .A0(n2262), .A1(n2477), .B0(n2478), .B1(n2476), .Y(n2458)
);
XNOR2X2TS U3101 ( .A(n853), .B(n2254), .Y(n2478) );
XNOR2X1TS U3102 ( .A(n920), .B(n2583), .Y(n2317) );
ADDFHX2TS U3103 ( .A(n2835), .B(n2834), .CI(n2833), .CO(n2860), .S(n2821) );
ADDFHX2TS U3104 ( .A(n2254), .B(n2576), .CI(n2575), .CO(n2620), .S(n2573) );
XOR2X4TS U3105 ( .A(n2203), .B(n2202), .Y(n2578) );
XOR2X2TS U3106 ( .A(n3334), .B(n3367), .Y(n2590) );
INVX4TS U3107 ( .A(n3367), .Y(n3190) );
AOI21X4TS U3108 ( .A0(n5358), .A1(n3745), .B0(n3744), .Y(n5349) );
NAND2X2TS U3109 ( .A(Op_MY[36]), .B(n7507), .Y(n4980) );
ADDFHX2TS U3110 ( .A(n2752), .B(n2751), .CI(n2750), .CO(n2856), .S(n2800) );
AOI21X4TS U3111 ( .A0(n6147), .A1(n6150), .B0(n1171), .Y(n1172) );
XOR2X2TS U3112 ( .A(n1403), .B(n1402), .Y(n1404) );
CLKINVX3TS U3113 ( .A(n1345), .Y(n1365) );
AOI21X2TS U3114 ( .A0(n8115), .A1(n4409), .B0(n4408), .Y(n4410) );
OAI21X2TS U3115 ( .A0(n8117), .A1(n8129), .B0(n8118), .Y(n4408) );
NAND2X6TS U3116 ( .A(Op_MY[31]), .B(Op_MY[4]), .Y(n1385) );
OAI21X4TS U3117 ( .A0(n5452), .A1(n1258), .B0(n1257), .Y(n3859) );
XOR2X4TS U3118 ( .A(n5829), .B(n5828), .Y(mult_x_23_n1350) );
OAI22X4TS U3119 ( .A0(n1482), .A1(n2808), .B0(n1481), .B1(n2100), .Y(n1545)
);
NAND2X4TS U3120 ( .A(n1614), .B(n1613), .Y(n1646) );
XNOR2X2TS U3121 ( .A(n857), .B(n3343), .Y(n1719) );
INVX4TS U3122 ( .A(n1332), .Y(n1388) );
NOR2X4TS U3123 ( .A(n3548), .B(n3549), .Y(n4692) );
ADDFHX4TS U3124 ( .A(n3066), .B(n3065), .CI(n3064), .CO(n3551), .S(n3549) );
ADDFHX2TS U3125 ( .A(n3200), .B(n3199), .CI(n3198), .CO(n3244), .S(n3196) );
ADDFHX4TS U3126 ( .A(n2596), .B(n2595), .CI(n2594), .CO(n2665), .S(n2592) );
INVX16TS U3127 ( .A(n2937), .Y(n3358) );
OAI22X2TS U3128 ( .A0(n1807), .A1(n2459), .B0(n1814), .B1(n2315), .Y(n1861)
);
NAND2X2TS U3129 ( .A(n4607), .B(Sgf_operation_ODD1_Q_left[14]), .Y(n7961) );
OAI21X4TS U3130 ( .A0(n4577), .A1(n4576), .B0(n4575), .Y(n4599) );
INVX4TS U3131 ( .A(n4567), .Y(n4577) );
XOR2X4TS U3132 ( .A(n4697), .B(n1003), .Y(Sgf_operation_ODD1_middle_N48) );
OAI21X2TS U3133 ( .A0(n6769), .A1(n6984), .B0(n6547), .Y(n6548) );
ADDFHX2TS U3134 ( .A(n2118), .B(n2117), .CI(n2116), .CO(n2417), .S(n2139) );
NAND2X8TS U3135 ( .A(n4766), .B(n3763), .Y(n3771) );
NAND2X2TS U3136 ( .A(n1697), .B(n1603), .Y(n1606) );
ADDFHX2TS U3137 ( .A(n1849), .B(n1848), .CI(n1847), .CO(n1927), .S(n1862) );
OAI22X1TS U3138 ( .A0(n1838), .A1(n2808), .B0(n1689), .B1(n2100), .Y(n1848)
);
ADDFHX4TS U3139 ( .A(n2729), .B(n2728), .CI(n2727), .CO(n2778), .S(n2725) );
NOR2X4TS U3140 ( .A(n4357), .B(n4359), .Y(n4335) );
BUFX8TS U3141 ( .A(n2086), .Y(n3419) );
NAND2X6TS U3142 ( .A(n3188), .B(n1987), .Y(n2086) );
ADDFHX2TS U3143 ( .A(n2344), .B(n2343), .CI(n2342), .CO(n2554), .S(n2382) );
NOR2X4TS U3144 ( .A(Op_MX[21]), .B(Op_MX[48]), .Y(n2075) );
NOR2X4TS U3145 ( .A(n7300), .B(n3570), .Y(n3572) );
NAND2X2TS U3146 ( .A(n7311), .B(n4832), .Y(n3570) );
ADDFHX2TS U3147 ( .A(n2632), .B(n2631), .CI(n2630), .CO(n2707), .S(n2618) );
NOR2X6TS U3148 ( .A(Op_MY[46]), .B(Op_MY[19]), .Y(n1954) );
ADDFHX4TS U3149 ( .A(n2275), .B(n2274), .CI(n2273), .CO(n2321), .S(n2346) );
ADDFHX2TS U3150 ( .A(n2269), .B(n2268), .CI(n2267), .CO(n2466), .S(n2344) );
OAI21X4TS U3151 ( .A0(n1327), .A1(n1406), .B0(n1326), .Y(n1328) );
XOR2X2TS U3152 ( .A(n6555), .B(n6827), .Y(mult_x_24_n1524) );
ADDFHX2TS U3153 ( .A(n2352), .B(n2351), .CI(n2350), .CO(n2391), .S(n2388) );
XNOR2X2TS U3154 ( .A(n2198), .B(n2944), .Y(n1802) );
ADDFHX2TS U3155 ( .A(n1696), .B(n1695), .CI(n1694), .CO(n1925), .S(n1691) );
XNOR2X2TS U3156 ( .A(n862), .B(n1979), .Y(n1645) );
OR2X4TS U3157 ( .A(n888), .B(n2942), .Y(n757) );
OR2X4TS U3158 ( .A(n1716), .B(n2762), .Y(n758) );
NAND2X4TS U3159 ( .A(n757), .B(n758), .Y(n1750) );
NAND2X4TS U3160 ( .A(n1754), .B(n1760), .Y(n1764) );
ADDFHX2TS U3161 ( .A(n1589), .B(n1588), .CI(n1587), .CO(n1590), .S(n1568) );
ADDFHX2TS U3162 ( .A(n2767), .B(n2766), .CI(n2765), .CO(n2833), .S(n2760) );
ADDFHX2TS U3163 ( .A(n1007), .B(n2712), .CI(n2711), .CO(n2766), .S(n2708) );
ADDFHX2TS U3164 ( .A(n2702), .B(n2701), .CI(n2700), .CO(n2794), .S(n2705) );
OAI22X2TS U3165 ( .A0(n2304), .A1(n2730), .B0(n2461), .B1(n2303), .Y(n2457)
);
BUFX16TS U3166 ( .A(Op_MX[18]), .Y(n6829) );
INVX8TS U3167 ( .A(n4862), .Y(n4885) );
XNOR2X2TS U3168 ( .A(n3349), .B(n2468), .Y(n2302) );
NOR2X4TS U3169 ( .A(n755), .B(n5892), .Y(n3704) );
ADDFHX2TS U3170 ( .A(n2544), .B(n2543), .CI(n2542), .CO(n2570), .S(n2529) );
XNOR2X2TS U3171 ( .A(n921), .B(n3227), .Y(n2513) );
OAI22X2TS U3172 ( .A0(n2558), .A1(n3407), .B0(n2649), .B1(n3405), .Y(n2647)
);
ADDFHX2TS U3173 ( .A(n2115), .B(n2114), .CI(n2113), .CO(n2409), .S(n2140) );
NOR2X8TS U3174 ( .A(n1405), .B(n1327), .Y(n1329) );
ADDFHX2TS U3175 ( .A(n2355), .B(n2354), .CI(n2353), .CO(n2342), .S(n2395) );
ADDFHX4TS U3176 ( .A(n2180), .B(n2179), .CI(n2178), .CO(n2182), .S(n1945) );
NOR2X4TS U3177 ( .A(n7368), .B(n2915), .Y(n7373) );
ADDFHX2TS U3178 ( .A(n1561), .B(n1560), .CI(n1559), .CO(n1567), .S(n1566) );
XNOR2X2TS U3179 ( .A(n1321), .B(n1316), .Y(n1320) );
ADDFHX2TS U3180 ( .A(n2770), .B(n2769), .CI(n2768), .CO(n2820), .S(n2750) );
NAND2X4TS U3181 ( .A(Op_MY[30]), .B(Op_MY[3]), .Y(n1348) );
XNOR2X2TS U3182 ( .A(Op_MY[3]), .B(Op_MY[4]), .Y(n1057) );
ADDFHX2TS U3183 ( .A(n2528), .B(n2527), .CI(n2526), .CO(n2607), .S(n2531) );
XOR2X2TS U3184 ( .A(n5710), .B(n8404), .Y(mult_x_23_n1434) );
AOI21X2TS U3185 ( .A0(n5225), .A1(n4890), .B0(n4889), .Y(n4891) );
BUFX12TS U3186 ( .A(Op_MX[21]), .Y(n6952) );
ADDFHX4TS U3187 ( .A(n2177), .B(n2176), .CI(n2175), .CO(n2183), .S(n2181) );
ADDFHX2TS U3188 ( .A(n2171), .B(n2170), .CI(n2169), .CO(n2160), .S(n2176) );
ADDFHX2TS U3189 ( .A(n2123), .B(n2122), .CI(n2121), .CO(n2152), .S(n2156) );
NOR2X8TS U3190 ( .A(n6094), .B(n6098), .Y(n7094) );
NOR2X4TS U3191 ( .A(n7079), .B(n6958), .Y(n1205) );
ADDFHX2TS U3192 ( .A(n2623), .B(n2622), .CI(n2621), .CO(n2744), .S(n2626) );
ADDFHX2TS U3193 ( .A(n2574), .B(n2573), .CI(n2572), .CO(n2623), .S(n2568) );
ADDFHX2TS U3194 ( .A(n2539), .B(n2538), .CI(n2537), .CO(n2572), .S(n2523) );
NOR2X4TS U3195 ( .A(Op_MY[47]), .B(Op_MY[20]), .Y(n1965) );
NOR2X6TS U3196 ( .A(n1965), .B(n1967), .Y(n2237) );
AOI21X2TS U3197 ( .A0(n2279), .A1(n2284), .B0(n2250), .Y(n2248) );
XNOR2X2TS U3198 ( .A(n899), .B(n2583), .Y(n2584) );
AOI21X4TS U3199 ( .A0(n4994), .A1(n1231), .B0(n1230), .Y(n1232) );
NAND2X4TS U3200 ( .A(n5481), .B(n5476), .Y(n1230) );
NAND2X4TS U3201 ( .A(n5602), .B(n5597), .Y(n4994) );
CMPR42X2TS U3202 ( .A(mult_x_23_n1244), .B(mult_x_23_n657), .C(
mult_x_23_n653), .D(mult_x_23_n1291), .ICI(mult_x_23_n654), .S(
mult_x_23_n651), .ICO(mult_x_23_n649), .CO(mult_x_23_n650) );
INVX12TS U3203 ( .A(n1013), .Y(n6934) );
AO21X4TS U3204 ( .A0(n3222), .A1(n3221), .B0(n3220), .Y(n3300) );
OAI21X2TS U3205 ( .A0(n891), .A1(n7429), .B0(n7428), .Y(n7434) );
NAND2X4TS U3206 ( .A(n1402), .B(n1394), .Y(n1343) );
NAND2X4TS U3207 ( .A(Op_MY[45]), .B(Op_MY[18]), .Y(n1953) );
OAI21X2TS U3208 ( .A0(n817), .A1(n1969), .B0(n1968), .Y(n1972) );
ADDFHX2TS U3209 ( .A(n2378), .B(n2377), .CI(n2376), .CO(n2381), .S(n2403) );
CMPR42X2TS U3210 ( .A(mult_x_23_n684), .B(mult_x_23_n1295), .C(
mult_x_23_n685), .D(mult_x_23_n678), .ICI(mult_x_23_n681), .S(
mult_x_23_n675), .ICO(mult_x_23_n673), .CO(mult_x_23_n674) );
OAI21X1TS U3211 ( .A0(n6026), .A1(n4965), .B0(n5474), .Y(n5475) );
NAND2X2TS U3212 ( .A(n1147), .B(n1143), .Y(n1119) );
INVX12TS U3213 ( .A(n1214), .Y(n6461) );
OAI21X1TS U3214 ( .A0(n7075), .A1(n6681), .B0(n6680), .Y(n6682) );
OAI21X1TS U3215 ( .A0(n7086), .A1(n6899), .B0(n6579), .Y(n6580) );
ADDFHX2TS U3216 ( .A(n2638), .B(n2637), .CI(n2636), .CO(n2704), .S(n2624) );
OAI21X2TS U3217 ( .A0(n1405), .A1(n1409), .B0(n1406), .Y(n1312) );
BUFX12TS U3218 ( .A(Op_MY[33]), .Y(n5892) );
NAND2X4TS U3219 ( .A(Op_MY[33]), .B(Op_MY[6]), .Y(n1406) );
NOR2X6TS U3220 ( .A(Op_MY[33]), .B(Op_MY[6]), .Y(n1405) );
NOR2X6TS U3221 ( .A(n2447), .B(n2448), .Y(n7269) );
NOR2X2TS U3222 ( .A(n1878), .B(n1877), .Y(n1879) );
OAI21X2TS U3223 ( .A0(Op_MX[18]), .A1(Op_MX[45]), .B0(Op_MX[17]), .Y(n1875)
);
XOR2X4TS U3224 ( .A(Op_MX[18]), .B(Op_MX[45]), .Y(n1877) );
ADDFHX2TS U3225 ( .A(n2509), .B(n2508), .CI(n2507), .CO(n2530), .S(n2549) );
ADDFHX4TS U3226 ( .A(n1683), .B(n1682), .CI(n1681), .CO(n1729), .S(n1731) );
ADDFHX4TS U3227 ( .A(n1657), .B(n1656), .CI(n1655), .CO(n1727), .S(n1681) );
ADDFHX2TS U3228 ( .A(n2301), .B(n2300), .CI(n2299), .CO(n2494), .S(n2360) );
OAI21X1TS U3229 ( .A0(n5968), .A1(n4671), .B0(n5546), .Y(n5547) );
OAI21X1TS U3230 ( .A0(n5968), .A1(n5491), .B0(n5514), .Y(n5515) );
CMPR42X2TS U3231 ( .A(mult_x_24_n1531), .B(mult_x_24_n1504), .C(
mult_x_24_n912), .D(mult_x_24_n1558), .ICI(mult_x_24_n906), .S(
mult_x_24_n899), .ICO(mult_x_24_n897), .CO(mult_x_24_n898) );
ADDFHX2TS U3232 ( .A(n2620), .B(n2619), .CI(n2618), .CO(n2697), .S(n2622) );
ADDFHX2TS U3233 ( .A(n2889), .B(n2888), .CI(n2887), .CO(n3173), .S(n2862) );
XNOR2X2TS U3234 ( .A(n753), .B(n2822), .Y(n2823) );
NOR2X4TS U3235 ( .A(n1362), .B(n1346), .Y(n1309) );
ADDFHX2TS U3236 ( .A(n2375), .B(n2374), .CI(n2373), .CO(n2356), .S(n2404) );
OAI21X1TS U3237 ( .A0(n5781), .A1(n5470), .B0(n5450), .Y(n5451) );
NOR2X8TS U3238 ( .A(Op_MY[41]), .B(Op_MY[14]), .Y(n1753) );
XNOR2X2TS U3239 ( .A(n3303), .B(n2881), .Y(n2335) );
NOR2X4TS U3240 ( .A(n8017), .B(n8006), .Y(n4423) );
OR2X8TS U3241 ( .A(n759), .B(n760), .Y(n7258) );
XNOR2X4TS U3242 ( .A(n907), .B(n2871), .Y(n2533) );
CMPR42X2TS U3243 ( .A(mult_x_23_n1426), .B(mult_x_23_n938), .C(
mult_x_23_n1452), .D(mult_x_23_n1478), .ICI(mult_x_23_n941), .S(
mult_x_23_n936), .ICO(mult_x_23_n934), .CO(mult_x_23_n935) );
NOR2X6TS U3244 ( .A(n3788), .B(n3787), .Y(n3796) );
INVX6TS U3245 ( .A(n1787), .Y(n2709) );
ADDFHX4TS U3246 ( .A(n2593), .B(n2592), .CI(n2591), .CO(n2667), .S(n2684) );
XNOR2X4TS U3247 ( .A(n4473), .B(n4472), .Y(n4619) );
OAI21X4TS U3248 ( .A0(n924), .A1(n5199), .B0(n5198), .Y(n5202) );
AOI21X2TS U3249 ( .A0(n5197), .A1(n5196), .B0(n5195), .Y(n5198) );
ADDFHX2TS U3250 ( .A(n1496), .B(n1495), .CI(n1494), .CO(n1498), .S(n1572) );
NOR2X8TS U3251 ( .A(n2919), .B(n2918), .Y(n7380) );
NAND2X4TS U3252 ( .A(n3767), .B(n4789), .Y(n3769) );
NOR2X4TS U3253 ( .A(n4782), .B(n4793), .Y(n3767) );
OAI21X1TS U3254 ( .A0(n6026), .A1(n4671), .B0(n5542), .Y(n5543) );
NAND2X4TS U3255 ( .A(mult_x_24_n1007), .B(mult_x_24_n1014), .Y(n6948) );
OAI21X1TS U3256 ( .A0(n1001), .A1(n5684), .B0(n5916), .Y(n5917) );
AND2X4TS U3257 ( .A(n1700), .B(n1697), .Y(n1019) );
ADDFHX2TS U3258 ( .A(n2338), .B(n2337), .CI(n2336), .CO(n2328), .S(n2380) );
NOR2X4TS U3259 ( .A(n6785), .B(Op_MX[15]), .Y(n6432) );
OAI21X1TS U3260 ( .A0(n729), .A1(n6841), .B0(n6600), .Y(n6601) );
CMPR22X2TS U3261 ( .A(n2506), .B(n2505), .CO(n2537), .S(n2473) );
XNOR2X4TS U3262 ( .A(n913), .B(n2939), .Y(n2520) );
NOR2X4TS U3263 ( .A(n1452), .B(n1455), .Y(n1458) );
XOR2X4TS U3264 ( .A(n4944), .B(n1011), .Y(Sgf_operation_ODD1_left_N47) );
NOR2X4TS U3265 ( .A(mult_x_23_n769), .B(mult_x_23_n779), .Y(n4908) );
OAI21X1TS U3266 ( .A0(n5968), .A1(n5569), .B0(n5592), .Y(n5593) );
NAND2X4TS U3267 ( .A(mult_x_23_n824), .B(mult_x_23_n834), .Y(n5308) );
OAI21X1TS U3268 ( .A0(n6048), .A1(n5665), .B0(n5693), .Y(n5695) );
NOR2X2TS U3269 ( .A(n8171), .B(n8162), .Y(n4403) );
AOI21X4TS U3270 ( .A0(n8160), .A1(n4403), .B0(n4402), .Y(n8112) );
XNOR2X2TS U3271 ( .A(n4180), .B(n4179), .Y(n4400) );
NOR2X6TS U3272 ( .A(n1950), .B(n1954), .Y(n1956) );
NOR2X4TS U3273 ( .A(n833), .B(n6484), .Y(n6287) );
NAND2X4TS U3274 ( .A(n833), .B(n6484), .Y(n6288) );
NOR2X6TS U3275 ( .A(n1943), .B(n1942), .Y(n7396) );
ADDFHX4TS U3276 ( .A(n1919), .B(n1918), .CI(n1917), .CO(n1944), .S(n1943) );
ADDFHX2TS U3277 ( .A(n2126), .B(n2125), .CI(n2124), .CO(n2127), .S(n2151) );
XNOR2X4TS U3278 ( .A(n1793), .B(n1798), .Y(n1794) );
CMPR42X2TS U3279 ( .A(mult_x_23_n1292), .B(mult_x_23_n664), .C(
mult_x_23_n658), .D(mult_x_23_n1266), .ICI(mult_x_23_n661), .S(
mult_x_23_n656), .ICO(mult_x_23_n654), .CO(mult_x_23_n655) );
OAI21X1TS U3280 ( .A0(n5781), .A1(n5886), .B0(n5500), .Y(n5501) );
ADDFHX4TS U3281 ( .A(n1728), .B(n1727), .CI(n1726), .CO(n1736), .S(n1730) );
ADDFHX2TS U3282 ( .A(n1693), .B(n1692), .CI(n1691), .CO(n1936), .S(n1726) );
XOR2X4TS U3283 ( .A(n4920), .B(n978), .Y(Sgf_operation_ODD1_left_N37) );
AOI21X2TS U3284 ( .A0(n8323), .A1(n4393), .B0(n4392), .Y(n4394) );
NOR2X2TS U3285 ( .A(n8327), .B(n8334), .Y(n4393) );
AOI21X2TS U3286 ( .A0(n3767), .A1(n4788), .B0(n3766), .Y(n3768) );
OAI21X4TS U3287 ( .A0(n4771), .A1(n4899), .B0(n4772), .Y(n4788) );
OAI21X1TS U3288 ( .A0(n5938), .A1(n5827), .B0(n5580), .Y(n5581) );
NOR2X8TS U3289 ( .A(n7248), .B(n7363), .Y(n2931) );
OAI22X2TS U3290 ( .A0(n2721), .A1(n928), .B0(n2773), .B1(n2772), .Y(n2770)
);
XNOR2X2TS U3291 ( .A(n899), .B(n2720), .Y(n2721) );
OAI21X2TS U3292 ( .A0(n4934), .A1(n3891), .B0(n3890), .Y(n3892) );
AOI21X4TS U3293 ( .A0(n5273), .A1(n5266), .B0(n3885), .Y(n4934) );
CMPR42X2TS U3294 ( .A(mult_x_23_n648), .B(mult_x_23_n1289), .C(
mult_x_23_n1263), .D(mult_x_23_n1243), .ICI(mult_x_23_n645), .S(
mult_x_23_n642), .ICO(mult_x_23_n640), .CO(mult_x_23_n641) );
OAI21X1TS U3295 ( .A0(n5879), .A1(n5886), .B0(n5493), .Y(n5492) );
NAND2X4TS U3296 ( .A(mult_x_23_n790), .B(mult_x_23_n780), .Y(n4904) );
NOR2X6TS U3297 ( .A(n2927), .B(n2926), .Y(n7248) );
XNOR2X2TS U3298 ( .A(n3334), .B(n3346), .Y(n2841) );
OAI22X2TS U3299 ( .A0(n2968), .A1(n935), .B0(n2991), .B1(n3413), .Y(n2988)
);
NOR2X8TS U3300 ( .A(n7396), .B(n7400), .Y(n1947) );
ADDFHX2TS U3301 ( .A(n1913), .B(n1912), .CI(n1911), .CO(n2148), .S(n1915) );
NOR2X2TS U3302 ( .A(n7919), .B(n7916), .Y(n7887) );
NOR2X4TS U3303 ( .A(n4614), .B(Sgf_operation_ODD1_Q_left[19]), .Y(n7893) );
ADDFHX4TS U3304 ( .A(n2165), .B(n2164), .CI(n2163), .CO(n2187), .S(n2184) );
XOR2X2TS U3305 ( .A(n1376), .B(n948), .Y(n2222) );
INVX2TS U3306 ( .A(n7200), .Y(n1538) );
OAI21X2TS U3307 ( .A0(n891), .A1(n7349), .B0(n7348), .Y(n7351) );
OAI21X1TS U3308 ( .A0(n7424), .A1(n7345), .B0(n7418), .Y(n7346) );
ADDFHX4TS U3309 ( .A(n2677), .B(n2676), .CI(n2675), .CO(n2682), .S(n2687) );
ADDFHX2TS U3310 ( .A(n2547), .B(n2546), .CI(n2545), .CO(n2569), .S(n2552) );
XNOR2X4TS U3311 ( .A(n738), .B(n2822), .Y(n2461) );
OAI21X4TS U3312 ( .A0(n5164), .A1(n5163), .B0(n5162), .Y(n5174) );
XOR2X2TS U3313 ( .A(n5509), .B(n5868), .Y(mult_x_23_n1298) );
OAI21X1TS U3314 ( .A0(n6043), .A1(n5886), .B0(n5508), .Y(n5509) );
CLKINVX12TS U3315 ( .A(n7600), .Y(n7733) );
NOR2X4TS U3316 ( .A(n4451), .B(n4450), .Y(n4562) );
CMPR42X2TS U3317 ( .A(mult_x_24_n1592), .B(mult_x_24_n1565), .C(
mult_x_24_n991), .D(mult_x_24_n1646), .ICI(mult_x_24_n988), .S(
mult_x_24_n980), .ICO(mult_x_24_n978), .CO(mult_x_24_n979) );
NOR2X4TS U3318 ( .A(n6448), .B(n6444), .Y(n1207) );
NAND2X4TS U3319 ( .A(n7079), .B(n6958), .Y(n6232) );
ADDFHX4TS U3320 ( .A(n1922), .B(n1921), .CI(n1920), .CO(n1942), .S(n1941) );
XNOR2X4TS U3321 ( .A(Op_MX[15]), .B(Op_MX[42]), .Y(n1743) );
OAI21X4TS U3322 ( .A0(n7395), .A1(n7400), .B0(n7401), .Y(n1946) );
XOR2X4TS U3323 ( .A(Op_MX[14]), .B(Op_MX[41]), .Y(n1711) );
XOR2X2TS U3324 ( .A(n1070), .B(n6891), .Y(n1111) );
OAI21X2TS U3325 ( .A0(n6973), .A1(n1038), .B0(n995), .Y(n1070) );
OAI21X1TS U3326 ( .A0(n7086), .A1(n6907), .B0(n6906), .Y(n6908) );
NAND2X4TS U3327 ( .A(n7779), .B(n4630), .Y(n4632) );
AOI21X4TS U3328 ( .A0(n7778), .A1(n4630), .B0(n4629), .Y(n4631) );
NOR2X6TS U3329 ( .A(n7600), .B(n4645), .Y(n7683) );
ADDFHX2TS U3330 ( .A(n2865), .B(n2864), .CI(n2863), .CO(n3207), .S(n2899) );
XNOR2X2TS U3331 ( .A(n3338), .B(n3275), .Y(n2818) );
ADDFHX2TS U3332 ( .A(n2138), .B(n2137), .CI(n2136), .CO(n2158), .S(n2169) );
ADDFHX4TS U3333 ( .A(n2147), .B(n2146), .CI(n2145), .CO(n2189), .S(n2188) );
ADDFHX4TS U3334 ( .A(n3472), .B(n3471), .CI(n3470), .CO(n3544), .S(n3533) );
CMPR42X2TS U3335 ( .A(mult_x_24_n1639), .B(mult_x_24_n1585), .C(
mult_x_24_n1612), .D(mult_x_24_n909), .ICI(mult_x_24_n902), .S(
mult_x_24_n896), .ICO(mult_x_24_n894), .CO(mult_x_24_n895) );
NOR2X6TS U3336 ( .A(n2924), .B(n2925), .Y(n7282) );
OAI22X2TS U3337 ( .A0(n2470), .A1(n3179), .B0(n2600), .B1(n2016), .Y(n2586)
);
XNOR2X2TS U3338 ( .A(n7542), .B(n7541), .Y(n7543) );
OAI21X2TS U3339 ( .A0(n4568), .A1(n4564), .B0(n4569), .Y(n4574) );
CMPR42X2TS U3340 ( .A(mult_x_24_n1093), .B(mult_x_24_n740), .C(
mult_x_24_n1488), .D(mult_x_24_n1434), .ICI(mult_x_24_n1461), .S(
mult_x_24_n732), .ICO(mult_x_24_n730), .CO(mult_x_24_n731) );
CMPR42X2TS U3341 ( .A(mult_x_24_n1406), .B(mult_x_24_n730), .C(
mult_x_24_n731), .D(mult_x_24_n726), .ICI(mult_x_24_n727), .S(
mult_x_24_n723), .ICO(mult_x_24_n721), .CO(mult_x_24_n722) );
NOR2X4TS U3342 ( .A(mult_x_24_n711), .B(mult_x_24_n716), .Y(n1287) );
OAI21X4TS U3343 ( .A0(n7262), .A1(n7438), .B0(n7263), .Y(n943) );
ADDFHX4TS U3344 ( .A(n2423), .B(n2422), .CI(n2421), .CO(n2425), .S(n2439) );
NAND2X2TS U3345 ( .A(n7829), .B(n4624), .Y(n7775) );
XOR2X2TS U3346 ( .A(n3916), .B(n970), .Y(Sgf_operation_ODD1_middle_N39) );
NAND2BX1TS U3347 ( .AN(n2223), .B(n2518), .Y(n1881) );
XNOR2X2TS U3348 ( .A(n7434), .B(n7433), .Y(Sgf_operation_ODD1_middle_N44) );
INVX4TS U3349 ( .A(n7344), .Y(n7424) );
OAI21X4TS U3350 ( .A0(n1671), .A1(n1670), .B0(n1669), .Y(n1761) );
NAND2X4TS U3351 ( .A(Op_MY[39]), .B(Op_MY[12]), .Y(n1670) );
OAI21X4TS U3352 ( .A0(n7875), .A1(n7832), .B0(n7831), .Y(n7849) );
NOR2X2TS U3353 ( .A(n6023), .B(n6038), .Y(n1250) );
OAI21X1TS U3354 ( .A0(n5879), .A1(n5684), .B0(n5667), .Y(n5666) );
OAI21X1TS U3355 ( .A0(n6043), .A1(n936), .B0(n5730), .Y(n5731) );
NOR2X6TS U3356 ( .A(n5307), .B(n5305), .Y(n5299) );
CMPR42X2TS U3357 ( .A(mult_x_24_n748), .B(mult_x_24_n1490), .C(
mult_x_24_n1463), .D(mult_x_24_n1409), .ICI(mult_x_24_n1436), .S(
mult_x_24_n746), .ICO(mult_x_24_n744), .CO(mult_x_24_n745) );
CMPR42X2TS U3358 ( .A(mult_x_24_n755), .B(mult_x_24_n752), .C(mult_x_24_n753), .D(mult_x_24_n746), .ICI(mult_x_24_n749), .S(mult_x_24_n743), .ICO(
mult_x_24_n741), .CO(mult_x_24_n742) );
NOR2X8TS U3359 ( .A(n4877), .B(n1196), .Y(n1198) );
NAND2X4TS U3360 ( .A(n1028), .B(n1027), .Y(n1196) );
XNOR2X2TS U3361 ( .A(n7351), .B(n7350), .Y(Sgf_operation_ODD1_middle_N43) );
BUFX12TS U3362 ( .A(n2936), .Y(n7430) );
OAI21X2TS U3363 ( .A0(n7430), .A1(n7332), .B0(n7331), .Y(n7334) );
OA21X4TS U3364 ( .A0(n7430), .A1(n7320), .B0(n7319), .Y(n761) );
XOR2X4TS U3365 ( .A(n761), .B(n821), .Y(Sgf_operation_ODD1_middle_N47) );
OA21X4TS U3366 ( .A0(n5141), .A1(n5143), .B0(n5144), .Y(n1025) );
NOR2X4TS U3367 ( .A(n1286), .B(n1292), .Y(n1295) );
NOR2X4TS U3368 ( .A(mult_x_24_n706), .B(mult_x_24_n710), .Y(n1286) );
XNOR2X4TS U3369 ( .A(n4884), .B(n4883), .Y(Sgf_operation_ODD1_right_N40) );
OAI21X4TS U3370 ( .A0(n4893), .A1(n4881), .B0(n4880), .Y(n4884) );
OAI21X4TS U3371 ( .A0(n6855), .A1(n7085), .B0(n6754), .Y(n6755) );
ADDFHX4TS U3372 ( .A(n3511), .B(n3510), .CI(n3509), .CO(n3528), .S(n3525) );
NOR2X4TS U3373 ( .A(n1753), .B(n1758), .Y(n1760) );
XNOR2X4TS U3374 ( .A(n4896), .B(n4895), .Y(Sgf_operation_ODD1_right_N39) );
XOR2X2TS U3375 ( .A(n6742), .B(n6861), .Y(mult_x_24_n1469) );
OAI21X4TS U3376 ( .A0(n4893), .A1(n4892), .B0(n4891), .Y(n4896) );
OAI21X4TS U3377 ( .A0(n818), .A1(n2260), .B0(n2259), .Y(n2261) );
OAI21X1TS U3378 ( .A0(n5879), .A1(n5807), .B0(n5789), .Y(n5765) );
OAI21X4TS U3379 ( .A0(n4903), .A1(n5286), .B0(n4904), .Y(n5277) );
NOR2X8TS U3380 ( .A(mult_x_23_n780), .B(mult_x_23_n790), .Y(n4903) );
CMPR42X2TS U3381 ( .A(mult_x_23_n807), .B(mult_x_23_n797), .C(mult_x_23_n804), .D(mult_x_23_n794), .ICI(mult_x_23_n800), .S(mult_x_23_n791), .ICO(
mult_x_23_n789), .CO(mult_x_23_n790) );
NAND2X4TS U3382 ( .A(n7321), .B(n4696), .Y(n3555) );
NOR2X4TS U3383 ( .A(Op_MY[37]), .B(Op_MY[10]), .Y(n1452) );
OAI21X4TS U3384 ( .A0(n891), .A1(n3927), .B0(n3926), .Y(n3931) );
AOI21X4TS U3385 ( .A0(n7325), .A1(n3925), .B0(n3924), .Y(n3926) );
XNOR2X4TS U3386 ( .A(n5147), .B(n5146), .Y(Sgf_operation_ODD1_right_N52) );
OAI21X4TS U3387 ( .A0(n816), .A1(n5142), .B0(n5141), .Y(n5147) );
OAI21X1TS U3388 ( .A0(n729), .A1(n7062), .B0(n6739), .Y(n6740) );
NOR2X8TS U3389 ( .A(n4903), .B(n5285), .Y(n5276) );
NOR2X4TS U3390 ( .A(mult_x_23_n791), .B(mult_x_23_n801), .Y(n5285) );
OAI21X4TS U3391 ( .A0(n4856), .A1(n924), .B0(n4855), .Y(n4861) );
OAI21X2TS U3392 ( .A0(n6043), .A1(n5620), .B0(n5638), .Y(n5639) );
XOR2X1TS U3393 ( .A(Op_MX[36]), .B(Op_MX[37]), .Y(n1378) );
INVX2TS U3394 ( .A(n3859), .Y(n3860) );
AOI21X2TS U3395 ( .A0(n4481), .A1(n4480), .B0(n4479), .Y(n4482) );
CLKAND2X2TS U3396 ( .A(n6946), .B(n905), .Y(mult_x_24_n1108) );
OAI21X1TS U3397 ( .A0(n5437), .A1(n5924), .B0(n4687), .Y(n4688) );
NOR2X4TS U3398 ( .A(n1730), .B(n1729), .Y(n1733) );
AOI21X2TS U3399 ( .A0(n6269), .A1(n4731), .B0(n790), .Y(n4732) );
CLKAND2X2TS U3400 ( .A(Op_MY[26]), .B(n834), .Y(mult_x_24_n1086) );
AOI21X2TS U3401 ( .A0(n5366), .A1(n5365), .B0(n3741), .Y(n3742) );
NOR2X2TS U3402 ( .A(n5000), .B(n5480), .Y(n1231) );
NOR2X4TS U3403 ( .A(Op_MY[48]), .B(Op_MY[21]), .Y(n1967) );
NOR2X1TS U3404 ( .A(n1985), .B(n3626), .Y(n1986) );
OAI22X1TS U3405 ( .A0(n2737), .A1(n3407), .B0(n2785), .B1(n3405), .Y(n2781)
);
NAND2X4TS U3406 ( .A(n1325), .B(n1329), .Y(n1333) );
XOR2X1TS U3407 ( .A(Op_MX[38]), .B(Op_MX[39]), .Y(n1618) );
ADDFHX2TS U3408 ( .A(n2057), .B(n2056), .CI(n2055), .CO(n2048), .S(n2136) );
AOI21X1TS U3409 ( .A0(n6269), .A1(n6273), .B0(n6257), .Y(n6258) );
INVX2TS U3410 ( .A(n4967), .Y(n863) );
OAI21X1TS U3411 ( .A0(n6053), .A1(n5491), .B0(n4658), .Y(n4659) );
NAND2X1TS U3412 ( .A(n5840), .B(n824), .Y(n4658) );
NAND2X4TS U3413 ( .A(n3658), .B(n3679), .Y(n3607) );
OAI21X2TS U3414 ( .A0(n4279), .A1(n4277), .B0(n4280), .Y(n4272) );
AOI21X2TS U3415 ( .A0(n4439), .A1(n4438), .B0(n4437), .Y(n4440) );
NAND2X4TS U3416 ( .A(n2201), .B(n2200), .Y(n2202) );
ADDFHX2TS U3417 ( .A(n1687), .B(n1686), .CI(n1685), .CO(n1863), .S(n1723) );
NOR2X2TS U3418 ( .A(n6362), .B(n1211), .Y(n1213) );
AOI21X2TS U3419 ( .A0(n6269), .A1(n3824), .B0(n3823), .Y(n3825) );
OAI21X2TS U3420 ( .A0(n6778), .A1(n6442), .B0(n6387), .Y(n6388) );
CLKAND2X2TS U3421 ( .A(n6962), .B(n7001), .Y(n6513) );
CLKAND2X2TS U3422 ( .A(n6946), .B(n827), .Y(mult_x_24_n1098) );
CLKAND2X2TS U3423 ( .A(n7078), .B(n7079), .Y(n6937) );
OAI21X1TS U3424 ( .A0(n6918), .A1(n6792), .B0(n6741), .Y(n6742) );
OAI21X2TS U3425 ( .A0(n6967), .A1(n6973), .B0(n6757), .Y(n6759) );
CLKAND2X2TS U3426 ( .A(n1083), .B(n7001), .Y(n7002) );
CLKAND2X2TS U3427 ( .A(n7078), .B(n825), .Y(mult_x_24_n1109) );
CLKINVX6TS U3428 ( .A(n863), .Y(n864) );
CLKAND2X2TS U3429 ( .A(n6060), .B(n6038), .Y(n1246) );
OAI21X1TS U3430 ( .A0(n6062), .A1(n4671), .B0(n4673), .Y(n4674) );
BUFX3TS U3431 ( .A(n5045), .Y(n7049) );
NOR2XLTS U3432 ( .A(FSM_selector_B[1]), .B(Op_MY[52]), .Y(n5254) );
OAI21X1TS U3433 ( .A0(n4356), .A1(n4352), .B0(n4353), .Y(n4170) );
AOI21X2TS U3434 ( .A0(n8226), .A1(n4295), .B0(n4294), .Y(n8248) );
NOR2X1TS U3435 ( .A(n4326), .B(Sgf_operation_ODD1_Q_right[38]), .Y(n8249) );
NOR2X1TS U3436 ( .A(n8249), .B(n8255), .Y(n8308) );
NAND2X1TS U3437 ( .A(n988), .B(n8227), .Y(n8237) );
XOR2X1TS U3438 ( .A(n4572), .B(n4571), .Y(n4607) );
OAI21X1TS U3439 ( .A0(n4209), .A1(n4205), .B0(n4206), .Y(n4155) );
NAND2X4TS U3440 ( .A(n3539), .B(n7343), .Y(n3541) );
NAND2X4TS U3441 ( .A(n5904), .B(Op_MX[51]), .Y(n973) );
AOI21X2TS U3442 ( .A0(n1301), .A1(n1300), .B0(n1299), .Y(n1302) );
OAI21X1TS U3443 ( .A0(n1298), .A1(n1297), .B0(n1296), .Y(n1299) );
INVX4TS U3444 ( .A(n1304), .Y(n1280) );
CMPR42X2TS U3445 ( .A(mult_x_23_n955), .B(mult_x_23_n1429), .C(
mult_x_23_n958), .D(mult_x_23_n1455), .ICI(mult_x_23_n1481), .S(
mult_x_23_n953), .ICO(mult_x_23_n951), .CO(mult_x_23_n952) );
NOR2X1TS U3446 ( .A(Sgf_operation_ODD1_Q_right[34]), .B(n4285), .Y(n8231) );
INVX2TS U3447 ( .A(n8057), .Y(n8097) );
NAND2X4TS U3448 ( .A(n3544), .B(n3543), .Y(n7275) );
BUFX8TS U3449 ( .A(n7325), .Y(n897) );
AOI21X2TS U3450 ( .A0(n7360), .A1(n7359), .B0(n7358), .Y(n7361) );
INVX2TS U3451 ( .A(n7379), .Y(n7281) );
NAND2X4TS U3452 ( .A(n2182), .B(n2181), .Y(n7151) );
NOR2X4TS U3453 ( .A(n1941), .B(n1940), .Y(n7388) );
NOR2X4TS U3454 ( .A(n1737), .B(n1736), .Y(n7163) );
NOR2X4TS U3455 ( .A(n1735), .B(n1734), .Y(n7161) );
NAND2X4TS U3456 ( .A(n1732), .B(n1731), .Y(n7173) );
NOR2X4TS U3457 ( .A(n1593), .B(n1592), .Y(n7185) );
NOR2X4TS U3458 ( .A(mult_x_24_n893), .B(mult_x_24_n904), .Y(n6098) );
NAND2X4TS U3459 ( .A(mult_x_24_n966), .B(mult_x_24_n976), .Y(n6127) );
INVX2TS U3460 ( .A(n6176), .Y(n6171) );
NAND2X4TS U3461 ( .A(mult_x_24_n1057), .B(mult_x_24_n1061), .Y(n6176) );
NAND2X1TS U3462 ( .A(n4958), .B(n4963), .Y(n4928) );
NOR2X4TS U3463 ( .A(n5161), .B(n4925), .Y(n4958) );
NOR2X4TS U3464 ( .A(mult_x_23_n802), .B(mult_x_23_n812), .Y(n5293) );
NAND2X4TS U3465 ( .A(mult_x_23_n914), .B(mult_x_23_n921), .Y(n5947) );
INVX2TS U3466 ( .A(n1459), .Y(n1435) );
INVX2TS U3467 ( .A(n1452), .Y(n1441) );
INVX2TS U3468 ( .A(n2238), .Y(n1998) );
NAND2X1TS U3469 ( .A(n1998), .B(n2237), .Y(n1969) );
AOI21X1TS U3470 ( .A0(n2002), .A1(n1976), .B0(n1958), .Y(n1959) );
INVX2TS U3471 ( .A(n1975), .Y(n1958) );
NAND2X1TS U3472 ( .A(n1998), .B(n1976), .Y(n1960) );
NAND2X1TS U3473 ( .A(n1951), .B(n1901), .Y(n1903) );
AOI21X1TS U3474 ( .A0(n1957), .A1(n1901), .B0(n1900), .Y(n1902) );
XNOR2X1TS U3475 ( .A(n900), .B(n2784), .Y(n2785) );
XNOR2X1TS U3476 ( .A(n2580), .B(n3358), .Y(n2227) );
INVX2TS U3477 ( .A(n1780), .Y(n1769) );
INVX2TS U3478 ( .A(n1671), .Y(n1607) );
INVX2TS U3479 ( .A(n1668), .Y(n1603) );
NAND2X1TS U3480 ( .A(n1453), .B(n1441), .Y(n1443) );
NOR2X4TS U3481 ( .A(n1336), .B(n1389), .Y(n1325) );
CLKBUFX2TS U3482 ( .A(n1346), .Y(n1347) );
XNOR2X1TS U3483 ( .A(n3227), .B(n3226), .Y(n3302) );
AOI21X2TS U3484 ( .A0(n1761), .A1(n1760), .B0(n1759), .Y(n1762) );
OAI21X2TS U3485 ( .A0(n1758), .A1(n1757), .B0(n1756), .Y(n1759) );
NAND2X1TS U3486 ( .A(n2001), .B(n1998), .Y(n2004) );
XNOR2X1TS U3487 ( .A(n3285), .B(n3167), .Y(n3218) );
XNOR2X1TS U3488 ( .A(n3368), .B(n2871), .Y(n3168) );
XNOR2X1TS U3489 ( .A(n2873), .B(n3230), .Y(n3187) );
XNOR2X1TS U3490 ( .A(n2815), .B(n2997), .Y(n2880) );
XNOR2X1TS U3491 ( .A(n3368), .B(n2650), .Y(n2693) );
ADDFHX2TS U3492 ( .A(n2708), .B(n2707), .CI(n2706), .CO(n2761), .S(n2702) );
XNOR2X1TS U3493 ( .A(n860), .B(n2871), .Y(n2736) );
OAI22X1TS U3494 ( .A0(n2503), .A1(n3407), .B0(n2521), .B1(n3405), .Y(n2524)
);
XNOR2X1TS U3495 ( .A(n912), .B(n2583), .Y(n2541) );
XNOR2X1TS U3496 ( .A(n753), .B(n2468), .Y(n2512) );
XNOR2X1TS U3497 ( .A(n917), .B(n3346), .Y(n2216) );
XNOR2X1TS U3498 ( .A(n860), .B(n2518), .Y(n2266) );
XNOR2X1TS U3499 ( .A(n3176), .B(n3343), .Y(n2217) );
XNOR2X1TS U3500 ( .A(n3334), .B(n2720), .Y(n2307) );
XNOR2X1TS U3501 ( .A(n3165), .B(n2264), .Y(n2330) );
OAI22X1TS U3502 ( .A0(n1994), .A1(n3031), .B0(n1993), .B1(n935), .Y(n2042)
);
NAND2X1TS U3503 ( .A(n1334), .B(n1433), .Y(n1335) );
NAND2X2TS U3504 ( .A(n755), .B(Op_MY[5]), .Y(n1390) );
NAND2X1TS U3505 ( .A(n1387), .B(n1385), .Y(n1337) );
NAND2X4TS U3506 ( .A(n4975), .B(n1229), .Y(n4991) );
NOR2X2TS U3507 ( .A(n4324), .B(n4373), .Y(n4073) );
AOI21X2TS U3508 ( .A0(n4320), .A1(n4073), .B0(n4072), .Y(n4074) );
OAI21X1TS U3509 ( .A0(n4373), .A1(n4369), .B0(n4374), .Y(n4072) );
NOR2X2TS U3510 ( .A(n4275), .B(n4300), .Y(n4063) );
AOI21X2TS U3511 ( .A0(n4574), .A1(n4459), .B0(n4458), .Y(n4484) );
NAND2X1TS U3512 ( .A(n4573), .B(n4459), .Y(n4475) );
AOI21X1TS U3513 ( .A0(n4149), .A1(n3961), .B0(n3960), .Y(n3962) );
NAND2X2TS U3514 ( .A(n4150), .B(n3961), .Y(n3999) );
AO21X1TS U3515 ( .A0(n888), .A1(n1710), .B0(n2942), .Y(n2980) );
NOR2X1TS U3516 ( .A(n2975), .B(n3583), .Y(n3029) );
OAI22X1TS U3517 ( .A0(n3280), .A1(n3279), .B0(n3347), .B1(n3401), .Y(n3324)
);
ADDFX2TS U3518 ( .A(n3328), .B(n3327), .CI(n3326), .CO(n3489), .S(n3321) );
NAND2X2TS U3519 ( .A(n2244), .B(n2237), .Y(n2246) );
NAND2X1TS U3520 ( .A(n2283), .B(n1010), .Y(n2250) );
XNOR2X1TS U3521 ( .A(n853), .B(n3230), .Y(n3073) );
XNOR2X1TS U3522 ( .A(n3276), .B(n3348), .Y(n2958) );
BUFX3TS U3523 ( .A(n935), .Y(n3250) );
OAI22X1TS U3524 ( .A0(n3180), .A1(n3179), .B0(n3178), .B1(n3220), .Y(n3258)
);
OAI22X1TS U3525 ( .A0(n2823), .A1(n3179), .B0(n2882), .B1(n2016), .Y(n2889)
);
ADDFHX2TS U3526 ( .A(n2847), .B(n2846), .CI(n2845), .CO(n2891), .S(n2853) );
ADDFHX2TS U3527 ( .A(n2490), .B(n2489), .CI(n2488), .CO(n2491), .S(n2496) );
XNOR2X1TS U3528 ( .A(n3334), .B(n2468), .Y(n2059) );
XNOR2X1TS U3529 ( .A(n3165), .B(n2070), .Y(n2061) );
XNOR2X1TS U3530 ( .A(n741), .B(n2294), .Y(n1818) );
CLKBUFX2TS U3531 ( .A(n2016), .Y(n3221) );
AOI21X2TS U3532 ( .A0(n1209), .A1(n6423), .B0(n1208), .Y(n1210) );
NAND2X1TS U3533 ( .A(n6389), .B(n6297), .Y(n6299) );
INVX2TS U3534 ( .A(n6280), .Y(n6389) );
OAI21X1TS U3535 ( .A0(n7075), .A1(n7062), .B0(n6347), .Y(n6348) );
AOI222X1TS U3536 ( .A0(n7060), .A1(n7071), .B0(n7058), .B1(n6569), .C0(n7080), .C1(n7068), .Y(n6347) );
AOI21X1TS U3537 ( .A0(n6392), .A1(n6284), .B0(n6283), .Y(n6285) );
NAND2X1TS U3538 ( .A(n6284), .B(n6389), .Y(n6286) );
OAI21X1TS U3539 ( .A0(n7014), .A1(n7013), .B0(n7012), .Y(n7015) );
OAI21XLTS U3540 ( .A0(n7014), .A1(n6966), .B0(n6534), .Y(n6535) );
BUFX3TS U3541 ( .A(n6454), .Y(n6760) );
BUFX3TS U3542 ( .A(n5075), .Y(n6834) );
AOI21X2TS U3543 ( .A0(n6429), .A1(n6364), .B0(n6350), .Y(n6351) );
NAND2X1TS U3544 ( .A(n6422), .B(n6364), .Y(n6352) );
INVX2TS U3545 ( .A(n6349), .Y(n6364) );
CLKAND2X2TS U3546 ( .A(n5899), .B(n5802), .Y(n4989) );
CLKAND2X2TS U3547 ( .A(n5899), .B(n852), .Y(n5417) );
CLKAND2X2TS U3548 ( .A(n5899), .B(n849), .Y(n5423) );
CLKAND2X2TS U3549 ( .A(n6060), .B(n851), .Y(n5429) );
OAI21X1TS U3550 ( .A0(n5957), .A1(n6035), .B0(n5431), .Y(n5432) );
OAI21X1TS U3551 ( .A0(n5762), .A1(n6067), .B0(n3616), .Y(n3617) );
CLKAND2X2TS U3552 ( .A(n6060), .B(n855), .Y(n3604) );
CLKAND2X2TS U3553 ( .A(n6060), .B(Op_MY[28]), .Y(n5435) );
NAND2X2TS U3554 ( .A(n5398), .B(n1254), .Y(n5453) );
NOR2X2TS U3555 ( .A(n829), .B(n5906), .Y(n5402) );
NOR2X1TS U3556 ( .A(n6038), .B(n829), .Y(n1249) );
INVX2TS U3557 ( .A(n1248), .Y(n1242) );
NAND2X1TS U3558 ( .A(n6038), .B(n829), .Y(n1252) );
NOR2X2TS U3559 ( .A(n6045), .B(n6023), .Y(n5480) );
NAND2X1TS U3560 ( .A(n6045), .B(n6023), .Y(n5481) );
NOR2X2TS U3561 ( .A(n5963), .B(n6045), .Y(n5000) );
NOR2X2TS U3562 ( .A(n828), .B(n5963), .Y(n5601) );
NAND2X2TS U3563 ( .A(n6016), .B(Op_MY[39]), .Y(n5597) );
NAND2X2TS U3564 ( .A(n4335), .B(n4002), .Y(n4160) );
NAND2X2TS U3565 ( .A(n4271), .B(n4063), .Y(n4306) );
INVX2TS U3566 ( .A(Sgf_operation_Result[7]), .Y(n4037) );
NOR2X1TS U3567 ( .A(n4156), .B(n4131), .Y(n4101) );
OAI22X1TS U3568 ( .A0(n3034), .A1(n3336), .B0(n3045), .B1(n3417), .Y(n3055)
);
ADDFHX2TS U3569 ( .A(n3478), .B(n3477), .CI(n3476), .CO(n3492), .S(n3503) );
OAI22X1TS U3570 ( .A0(n3347), .A1(n890), .B0(n3404), .B1(n3401), .Y(n3396)
);
ADDFHX2TS U3571 ( .A(n3342), .B(n3341), .CI(n3340), .CO(n3505), .S(n3372) );
AOI21X1TS U3572 ( .A0(n1256), .A1(n3841), .B0(n1255), .Y(n1257) );
NOR2X4TS U3573 ( .A(n2246), .B(n2238), .Y(n2278) );
ADDFHX2TS U3574 ( .A(n3481), .B(n3480), .CI(n3479), .CO(n3440), .S(n3491) );
ADDFX1TS U3575 ( .A(n3238), .B(n3237), .CI(n3236), .CO(n3266), .S(n3260) );
ADDFHX2TS U3576 ( .A(n2862), .B(n2861), .CI(n2860), .CO(n3210), .S(n2902) );
OAI22X1TS U3577 ( .A0(n1832), .A1(n3178), .B0(n1808), .B1(n3222), .Y(n1805)
);
ADDHX1TS U3578 ( .A(n1546), .B(n1545), .CO(n1540), .S(n1558) );
INVX4TS U3579 ( .A(n861), .Y(n862) );
NOR2X2TS U3580 ( .A(n3814), .B(n6248), .Y(n3824) );
CLKBUFX2TS U3581 ( .A(n3815), .Y(n6281) );
CLKAND2X2TS U3582 ( .A(n7010), .B(n7001), .Y(n6218) );
NAND2X1TS U3583 ( .A(n6322), .B(n6327), .Y(n6313) );
AOI21X1TS U3584 ( .A0(n6392), .A1(n6391), .B0(n6390), .Y(n6393) );
NAND2X1TS U3585 ( .A(n6389), .B(n6391), .Y(n6394) );
OAI21X1TS U3586 ( .A0(n6967), .A1(n6984), .B0(n6545), .Y(n6546) );
AOI222X1TS U3587 ( .A0(n883), .A1(n874), .B0(n7010), .B1(n6929), .C0(n6491),
.C1(n6559), .Y(n6492) );
OAI21X1TS U3588 ( .A0(n7006), .A1(n6999), .B0(n6998), .Y(n7000) );
CLKAND2X2TS U3589 ( .A(n6995), .B(n7001), .Y(n6996) );
AOI222X1TS U3590 ( .A0(n7072), .A1(n7071), .B0(n7070), .B1(n7069), .C0(n844),
.C1(n7068), .Y(n7073) );
OAI21X1TS U3591 ( .A0(n6967), .A1(n6999), .B0(n6745), .Y(n6746) );
AOI222X1TS U3592 ( .A0(n6771), .A1(n6922), .B0(n6980), .B1(Op_MX[21]), .C0(
n6982), .C1(n878), .Y(n6554) );
OAI21X2TS U3593 ( .A0(n6769), .A1(n6999), .B0(n6768), .Y(n6770) );
OAI21X2TS U3594 ( .A0(n6933), .A1(n6788), .B0(n6747), .Y(n6748) );
CLKAND2X2TS U3595 ( .A(n6970), .B(n7001), .Y(n6971) );
AOI222X1TS U3596 ( .A0(n6771), .A1(n6814), .B0(n7021), .B1(n879), .C0(n6982),
.C1(n6930), .Y(n6772) );
CLKAND2X2TS U3597 ( .A(n7078), .B(n6584), .Y(mult_x_24_n1106) );
CLKAND2X2TS U3598 ( .A(n887), .B(n7001), .Y(n6657) );
AOI222X1TS U3599 ( .A0(n6683), .A1(n6963), .B0(n886), .B1(n6961), .C0(n6813),
.C1(n6756), .Y(n6660) );
CLKAND2X2TS U3600 ( .A(n6897), .B(Op_MY[26]), .Y(mult_x_24_n1107) );
AOI222X1TS U3601 ( .A0(n6839), .A1(n874), .B0(n6995), .B1(n6929), .C0(n6997),
.C1(n6928), .Y(n6840) );
AOI222X1TS U3602 ( .A0(n6817), .A1(n926), .B0(n887), .B1(n6767), .C0(n6813),
.C1(n833), .Y(n6662) );
OAI21X1TS U3603 ( .A0(n729), .A1(n7025), .B0(n6565), .Y(n6566) );
AOI222X1TS U3604 ( .A0(n7023), .A1(n7071), .B0(n7021), .B1(n6569), .C0(n6581), .C1(n7068), .Y(n6570) );
AOI222X1TS U3605 ( .A0(n6750), .A1(n877), .B0(n6970), .B1(n6830), .C0(n6990),
.C1(Op_MX[18]), .Y(n6629) );
AOI222X1TS U3606 ( .A0(n6817), .A1(Op_MX[23]), .B0(n887), .B1(n6922), .C0(
n6813), .C1(n6847), .Y(n6666) );
OAI21X1TS U3607 ( .A0(n6967), .A1(n7005), .B0(n6697), .Y(n6698) );
OAI21X1TS U3608 ( .A0(n6879), .A1(n6872), .B0(n6871), .Y(n6873) );
OAI21XLTS U3609 ( .A0(n7014), .A1(n6999), .B0(n6606), .Y(n6607) );
AOI222X1TS U3610 ( .A0(n6848), .A1(n875), .B0(n6843), .B1(n7008), .C0(n7043),
.C1(n6904), .Y(n6774) );
AOI222X1TS U3611 ( .A0(n884), .A1(n6847), .B0(n6916), .B1(n6846), .C0(n7003),
.C1(n874), .Y(n6709) );
NAND2X4TS U3612 ( .A(n6958), .B(n6753), .Y(n6462) );
AOI222X1TS U3613 ( .A0(n6683), .A1(n6894), .B0(n886), .B1(n937), .C0(n6902),
.C1(n8412), .Y(n6676) );
AOI222X1TS U3614 ( .A0(n6750), .A1(n875), .B0(n7034), .B1(n827), .C0(n7032),
.C1(n6904), .Y(n6645) );
NAND2X1TS U3615 ( .A(n6428), .B(n6422), .Y(n6431) );
AOI21X2TS U3616 ( .A0(n6429), .A1(n6428), .B0(n6427), .Y(n6430) );
OAI21X1TS U3617 ( .A0(n6426), .A1(n6425), .B0(n6424), .Y(n6427) );
NAND2X1TS U3618 ( .A(n6457), .B(n6463), .Y(n6447) );
NAND2X2TS U3619 ( .A(n7008), .B(n910), .Y(n6449) );
AOI222X1TS U3620 ( .A0(n6683), .A1(n8412), .B0(n6903), .B1(n7069), .C0(n6902), .C1(n875), .Y(n6680) );
OAI21XLTS U3621 ( .A0(n7014), .A1(n6819), .B0(n6684), .Y(n6685) );
AOI222X1TS U3622 ( .A0(n6683), .A1(Op_MX[13]), .B0(n6903), .B1(n7009), .C0(
n6902), .C1(n6853), .Y(n6684) );
XOR2X2TS U3623 ( .A(n4719), .B(n892), .Y(n6940) );
OAI21XLTS U3624 ( .A0(n7063), .A1(n6932), .B0(n6715), .Y(n6716) );
BUFX3TS U3625 ( .A(n6639), .Y(n7032) );
NAND2X1TS U3626 ( .A(n6422), .B(n6420), .Y(n6342) );
NAND2X2TS U3627 ( .A(n6785), .B(n7056), .Y(n6424) );
XOR2X1TS U3628 ( .A(n5044), .B(n7027), .Y(n7016) );
AOI22X1TS U3629 ( .A0(n6558), .A1(n5041), .B0(n6771), .B1(n6243), .Y(n5042)
);
AOI21X2TS U3630 ( .A0(n1096), .A1(n1118), .B0(n1121), .Y(n1145) );
NAND2X2TS U3631 ( .A(n6874), .B(n8414), .Y(n1143) );
NAND2X1TS U3632 ( .A(n5883), .B(n5771), .Y(n3868) );
AOI21X1TS U3633 ( .A0(n5936), .A1(n6045), .B0(n1238), .Y(n1239) );
CLKAND2X2TS U3634 ( .A(n6060), .B(n6045), .Y(n5889) );
OAI21X1TS U3635 ( .A0(n5912), .A1(n5470), .B0(n5472), .Y(n5473) );
OAI21X1TS U3636 ( .A0(n5887), .A1(n5827), .B0(n5571), .Y(n5572) );
CLKAND2X2TS U3637 ( .A(n5899), .B(n828), .Y(n5897) );
CLKAND2X2TS U3638 ( .A(n5899), .B(n8385), .Y(n5900) );
AOI222X1TS U3639 ( .A0(n882), .A1(n6028), .B0(n865), .B1(n6005), .C0(n6017),
.C1(n850), .Y(n5972) );
AO21XLTS U3640 ( .A0(n5975), .A1(n5769), .B0(n5701), .Y(n5672) );
AO21XLTS U3641 ( .A0(n5745), .A1(n5769), .B0(n5859), .Y(n5715) );
AOI222X1TS U3642 ( .A0(n5922), .A1(n5796), .B0(n5561), .B1(n5982), .C0(n6010), .C1(n6005), .Y(n5550) );
AO21XLTS U3643 ( .A0(n873), .A1(n5769), .B0(n870), .Y(n5770) );
NOR2X1TS U3644 ( .A(n5942), .B(n5939), .Y(n5457) );
NAND2X1TS U3645 ( .A(n5942), .B(n5939), .Y(n5458) );
AOI222X1TS U3646 ( .A0(n5983), .A1(n6005), .B0(n5981), .B1(n837), .C0(n5980),
.C1(n8385), .Y(n5956) );
NOR2X2TS U3647 ( .A(n5906), .B(n5935), .Y(n5535) );
NAND2X1TS U3648 ( .A(n5906), .B(n5935), .Y(n5536) );
XOR2X1TS U3649 ( .A(n4684), .B(n5567), .Y(n5139) );
NAND2X2TS U3650 ( .A(n7507), .B(n6016), .Y(n4985) );
NAND2X2TS U3651 ( .A(n5901), .B(n7508), .Y(n3724) );
NOR2X2TS U3652 ( .A(n5901), .B(n7508), .Y(n3723) );
NAND2X1TS U3653 ( .A(Op_MY[35]), .B(Op_MY[36]), .Y(n3619) );
INVX2TS U3654 ( .A(n3618), .Y(n3620) );
XOR2X1TS U3655 ( .A(n4677), .B(n5567), .Y(n5910) );
NAND2X1TS U3656 ( .A(n4675), .B(n4966), .Y(n4676) );
NAND2X1TS U3657 ( .A(n5963), .B(n6045), .Y(n5476) );
BUFX3TS U3658 ( .A(n5650), .Y(n5959) );
NOR2X2TS U3659 ( .A(n848), .B(n852), .Y(n3657) );
NOR2X2TS U3660 ( .A(n4071), .B(n4070), .Y(n4373) );
AOI21X1TS U3661 ( .A0(n4381), .A1(n4335), .B0(n4334), .Y(n4368) );
AOI21X2TS U3662 ( .A0(n4343), .A1(n4165), .B0(n4164), .Y(n4356) );
NOR2X2TS U3663 ( .A(n4029), .B(n4028), .Y(n4264) );
INVX2TS U3664 ( .A(n4272), .Y(n4273) );
INVX2TS U3665 ( .A(n4271), .Y(n4274) );
INVX2TS U3666 ( .A(n4275), .Y(n4298) );
NAND2X1TS U3667 ( .A(n4061), .B(n4060), .Y(n4301) );
INVX2TS U3668 ( .A(n4320), .Y(n4321) );
NAND2X1TS U3669 ( .A(n4027), .B(n4026), .Y(n4251) );
OAI21X2TS U3670 ( .A0(n4522), .A1(n4521), .B0(n4520), .Y(n4523) );
NAND2X1TS U3671 ( .A(n4514), .B(n4518), .Y(n4521) );
INVX2TS U3672 ( .A(n4580), .Y(n4595) );
AOI21X1TS U3673 ( .A0(n4183), .A1(n4182), .B0(n4181), .Y(n4188) );
ADDFHX2TS U3674 ( .A(n3019), .B(n3018), .CI(n3017), .CO(n3044), .S(n3040) );
ADDFX2TS U3675 ( .A(n3372), .B(n3371), .CI(n3370), .CO(n3498), .S(n3373) );
ADDFHX2TS U3676 ( .A(n3502), .B(n3501), .CI(n3500), .CO(n3511), .S(n3499) );
INVX2TS U3677 ( .A(n4183), .Y(n4175) );
OAI22X1TS U3678 ( .A0(n3121), .A1(n3155), .B0(n3128), .B1(n3422), .Y(n3130)
);
OAI21X2TS U3679 ( .A0(n3928), .A1(n3922), .B0(n3929), .Y(n4822) );
INVX2TS U3680 ( .A(n7432), .Y(n3535) );
OAI22X1TS U3681 ( .A0(n3092), .A1(n3361), .B0(n3105), .B1(n3378), .Y(n3102)
);
ADDFHX2TS U3682 ( .A(n3466), .B(n3465), .CI(n3464), .CO(n3467), .S(n3494) );
ADDFHX2TS U3683 ( .A(n2904), .B(n2903), .CI(n2902), .CO(n3192), .S(n2910) );
ADDFHX2TS U3684 ( .A(n2749), .B(n2748), .CI(n2747), .CO(n2776), .S(n2691) );
INVX2TS U3685 ( .A(n812), .Y(n813) );
INVX2TS U3686 ( .A(n2660), .Y(n812) );
ADDFHX2TS U3687 ( .A(n2135), .B(n2134), .CI(n2133), .CO(n2170), .S(n2154) );
OAI22X1TS U3688 ( .A0(n1610), .A1(n2363), .B0(n1680), .B1(n1974), .Y(n1660)
);
ADDFHX2TS U3689 ( .A(n1630), .B(n1629), .CI(n1628), .CO(n1682), .S(n1642) );
ADDFX2TS U3690 ( .A(n1580), .B(n1579), .CI(n1578), .CO(n1496), .S(n1585) );
OAI22X1TS U3691 ( .A0(n1477), .A1(n2808), .B0(n1479), .B1(n2100), .Y(n1579)
);
BUFX3TS U3692 ( .A(n1828), .Y(n2787) );
NAND2X4TS U3693 ( .A(Op_MY[27]), .B(Op_MY[0]), .Y(n948) );
AOI21X1TS U3694 ( .A0(n6390), .A1(n3818), .B0(n3817), .Y(n3819) );
NOR2X4TS U3695 ( .A(n3816), .B(n6280), .Y(n6268) );
AND2X2TS U3696 ( .A(n4730), .B(n6245), .Y(n4731) );
NAND2X1TS U3697 ( .A(n5023), .B(n3807), .Y(n5111) );
CLKAND2X2TS U3698 ( .A(n6921), .B(n7001), .Y(n3830) );
CLKAND2X2TS U3699 ( .A(Op_MY[26]), .B(n6952), .Y(mult_x_24_n1088) );
NAND2X1TS U3700 ( .A(n1295), .B(n5029), .Y(n1298) );
CLKAND2X2TS U3701 ( .A(Op_MY[26]), .B(n879), .Y(n6216) );
CLKAND2X2TS U3702 ( .A(n6946), .B(n6559), .Y(mult_x_24_n1092) );
AOI222X1TS U3703 ( .A0(n6923), .A1(n6814), .B0(n7058), .B1(n877), .C0(n7080),
.C1(n874), .Y(n6306) );
CLKAND2X2TS U3704 ( .A(n6946), .B(n6562), .Y(mult_x_24_n1093) );
NAND2X2TS U3705 ( .A(n1198), .B(n4862), .Y(n1200) );
CMPR42X1TS U3706 ( .A(mult_x_24_n740), .B(mult_x_24_n747), .C(
mult_x_24_n1489), .D(mult_x_24_n1435), .ICI(mult_x_24_n1462), .S(
mult_x_24_n739), .ICO(mult_x_24_n737), .CO(mult_x_24_n738) );
XOR2X1TS U3707 ( .A(n6969), .B(n6968), .Y(mult_x_24_n1490) );
BUFX4TS U3708 ( .A(n5075), .Y(n7010) );
BUFX3TS U3709 ( .A(n5076), .Y(n6491) );
CLKAND2X2TS U3710 ( .A(n6946), .B(n7056), .Y(n6229) );
BUFX3TS U3711 ( .A(n6454), .Y(n7070) );
CLKAND2X2TS U3712 ( .A(n7078), .B(n910), .Y(mult_x_24_n1099) );
CMPR42X1TS U3713 ( .A(mult_x_24_n795), .B(mult_x_24_n805), .C(
mult_x_24_n1441), .D(mult_x_24_n1414), .ICI(mult_x_24_n1495), .S(
mult_x_24_n794), .ICO(mult_x_24_n792), .CO(mult_x_24_n793) );
XOR2X1TS U3714 ( .A(n6994), .B(n8378), .Y(mult_x_24_n1578) );
XOR2X1TS U3715 ( .A(n6759), .B(n6758), .Y(mult_x_24_n1580) );
CMPR42X1TS U3716 ( .A(mult_x_24_n1475), .B(mult_x_24_n888), .C(
mult_x_24_n1529), .D(mult_x_24_n1583), .ICI(mult_x_24_n889), .S(
mult_x_24_n875), .ICO(mult_x_24_n873), .CO(mult_x_24_n874) );
CMPR42X1TS U3717 ( .A(mult_x_24_n952), .B(mult_x_24_n1508), .C(
mult_x_24_n1481), .D(mult_x_24_n1535), .ICI(mult_x_24_n959), .S(
mult_x_24_n950), .ICO(mult_x_24_n948), .CO(mult_x_24_n949) );
INVX6TS U3718 ( .A(n6330), .Y(n6793) );
NAND2X1TS U3719 ( .A(n6327), .B(n6326), .Y(n6328) );
INVX2TS U3720 ( .A(n6815), .Y(n887) );
OAI21X1TS U3721 ( .A0(n7039), .A1(n6907), .B0(n6837), .Y(n6838) );
ADDHX1TS U3722 ( .A(n4728), .B(n4727), .CO(mult_x_24_n1067), .S(n1163) );
BUFX3TS U3723 ( .A(n1130), .Y(n6907) );
AOI222X1TS U3724 ( .A0(n6683), .A1(n7042), .B0(n886), .B1(n7022), .C0(n822),
.C1(n6822), .Y(n1078) );
INVX6TS U3725 ( .A(n1046), .Y(n7050) );
NAND2X1TS U3726 ( .A(n1043), .B(n1064), .Y(n1044) );
CLKXOR2X2TS U3727 ( .A(n1061), .B(n940), .Y(n1071) );
NAND2X1TS U3728 ( .A(n1094), .B(n1093), .Y(n1095) );
NAND2X1TS U3729 ( .A(n1000), .B(n1075), .Y(n1076) );
CLKAND2X2TS U3730 ( .A(n5940), .B(n5775), .Y(n3854) );
CLKAND2X2TS U3731 ( .A(n5940), .B(n5939), .Y(n5941) );
CLKAND2X2TS U3732 ( .A(n5940), .B(n5935), .Y(n5894) );
CLKAND2X2TS U3733 ( .A(n5940), .B(n5942), .Y(n5934) );
CLKAND2X2TS U3734 ( .A(n6060), .B(n5906), .Y(n5907) );
AO21XLTS U3735 ( .A0(n5494), .A1(n5769), .B0(n6033), .Y(n5495) );
OAI21X2TS U3736 ( .A0(n5945), .A1(n5470), .B0(n5411), .Y(n5412) );
OAI21X1TS U3737 ( .A0(n6026), .A1(n6061), .B0(n1247), .Y(n1265) );
OAI21X1TS U3738 ( .A0(n4782), .A1(n4794), .B0(n4783), .Y(n3766) );
NOR2X2TS U3739 ( .A(n3769), .B(n4898), .Y(n3763) );
CMPR42X1TS U3740 ( .A(mult_x_23_n744), .B(mult_x_23_n754), .C(
mult_x_23_n1302), .D(mult_x_23_n1406), .ICI(mult_x_23_n1354), .S(
mult_x_23_n743), .ICO(mult_x_23_n741), .CO(mult_x_23_n742) );
CMPR42X1TS U3741 ( .A(mult_x_23_n810), .B(mult_x_23_n817), .C(
mult_x_23_n1334), .D(mult_x_23_n1438), .ICI(mult_x_23_n814), .S(
mult_x_23_n805), .ICO(mult_x_23_n803), .CO(mult_x_23_n804) );
XOR2X1TS U3742 ( .A(n5842), .B(n5847), .Y(mult_x_23_n1313) );
CLKBUFX2TS U3743 ( .A(n5653), .Y(n5983) );
CLKBUFX2TS U3744 ( .A(n5650), .Y(n5981) );
AOI222X1TS U3745 ( .A0(n5929), .A1(n848), .B0(n5698), .B1(n830), .C0(n5928),
.C1(n855), .Y(n5852) );
OAI21XLTS U3746 ( .A0(n979), .A1(n5807), .B0(n3727), .Y(n3728) );
NAND2X1TS U3747 ( .A(n3708), .B(n3707), .Y(n3709) );
OAI21X2TS U3748 ( .A0(n3705), .A1(n3704), .B0(n3703), .Y(n3710) );
AND3X2TS U3749 ( .A(n3639), .B(n3638), .C(n3637), .Y(n5751) );
INVX2TS U3750 ( .A(n4205), .Y(n4207) );
NOR2X1TS U3751 ( .A(n8301), .B(n8295), .Y(n8277) );
OAI21X1TS U3752 ( .A0(n4508), .A1(n4507), .B0(n4506), .Y(n4513) );
NOR2X1TS U3753 ( .A(n7983), .B(n7972), .Y(n7944) );
OAI21X1TS U3754 ( .A0(n7972), .A1(n7984), .B0(n7973), .Y(n7945) );
ADDFX2TS U3755 ( .A(n3041), .B(n3040), .CI(n3039), .CO(n3546), .S(n3543) );
AND2X2TS U3756 ( .A(n4821), .B(n3556), .Y(n1021) );
BUFX3TS U3757 ( .A(n2941), .Y(n3154) );
INVX2TS U3758 ( .A(n4820), .Y(n7294) );
ADDHX1TS U3759 ( .A(n1513), .B(n1512), .CO(n1522), .S(n1509) );
AND3X4TS U3760 ( .A(n1048), .B(n1005), .C(n999), .Y(n6893) );
OAI21XLTS U3761 ( .A0(n6084), .A1(n5665), .B0(n5686), .Y(n5687) );
XOR2X1TS U3762 ( .A(n3645), .B(n5763), .Y(n3675) );
INVX4TS U3763 ( .A(n3649), .Y(n5437) );
AOI21X1TS U3764 ( .A0(n7427), .A1(n7343), .B0(n7344), .Y(n7331) );
INVX2TS U3765 ( .A(n8117), .Y(n8119) );
MX2X1TS U3766 ( .A(Op_MX[52]), .B(exp_oper_result[0]), .S0(n846), .Y(
S_Oper_A_exp[0]) );
NAND4XLTS U3767 ( .A(Exp_module_Data_S[3]), .B(Exp_module_Data_S[2]), .C(
Exp_module_Data_S[1]), .D(Exp_module_Data_S[0]), .Y(n8356) );
INVX2TS U3768 ( .A(n7893), .Y(n7895) );
INVX2TS U3769 ( .A(n8006), .Y(n8008) );
INVX2TS U3770 ( .A(n8063), .Y(n8065) );
INVX2TS U3771 ( .A(n5328), .Y(n3756) );
OR2X2TS U3772 ( .A(n3551), .B(n3550), .Y(n4696) );
INVX2TS U3773 ( .A(n4826), .Y(n7311) );
AOI21X2TS U3774 ( .A0(n7325), .A1(n7308), .B0(n7307), .Y(n7309) );
AOI21X1TS U3775 ( .A0(n7427), .A1(n7347), .B0(n7346), .Y(n7348) );
CLKAND2X2TS U3776 ( .A(n6946), .B(n926), .Y(n5126) );
XOR3X1TS U3777 ( .A(n1017), .B(n5128), .C(n5127), .Y(n5129) );
AOI21X2TS U3778 ( .A0(n1280), .A1(n1279), .B0(n1278), .Y(n5026) );
OAI21X1TS U3779 ( .A0(n4888), .A1(n4868), .B0(n4867), .Y(n4869) );
OAI21XLTS U3780 ( .A0(n5222), .A1(n4840), .B0(n5228), .Y(n4841) );
NOR2X1TS U3781 ( .A(n5152), .B(n5154), .Y(n5194) );
OR2X4TS U3782 ( .A(mult_x_23_n683), .B(mult_x_23_n689), .Y(n5196) );
OAI21X1TS U3783 ( .A0(n5155), .A1(n5154), .B0(n5153), .Y(n5197) );
NAND2X4TS U3784 ( .A(n5276), .B(n3765), .Y(n4898) );
NAND2X4TS U3785 ( .A(mult_x_23_n791), .B(mult_x_23_n801), .Y(n5286) );
NAND2X1TS U3786 ( .A(n3735), .B(n3734), .Y(n5814) );
INVX2TS U3787 ( .A(Sgf_operation_ODD1_left_N0), .Y(n3672) );
BUFX3TS U3788 ( .A(n803), .Y(n6053) );
NAND2X1TS U3789 ( .A(n7415), .B(n7418), .Y(n7333) );
NAND2X1TS U3790 ( .A(n7417), .B(n7343), .Y(n7332) );
CLKAND2X2TS U3791 ( .A(n7407), .B(n7405), .Y(n976) );
INVX2TS U3792 ( .A(n8149), .Y(n8151) );
INVX2TS U3793 ( .A(n8128), .Y(n8130) );
MX2X1TS U3794 ( .A(P_Sgf[98]), .B(n7594), .S0(n8191), .Y(n519) );
MX2X1TS U3795 ( .A(P_Sgf[99]), .B(n7584), .S0(n8191), .Y(n521) );
INVX2TS U3796 ( .A(n7578), .Y(n7581) );
INVX2TS U3797 ( .A(n8301), .Y(n8303) );
OAI21XLTS U3798 ( .A0(n8238), .A1(n8231), .B0(n8230), .Y(n8234) );
MX2X1TS U3799 ( .A(P_Sgf[1]), .B(Sgf_operation_Result[1]), .S0(n8188), .Y(
n422) );
MX2X1TS U3800 ( .A(P_Sgf[90]), .B(n7675), .S0(n7712), .Y(n511) );
MX2X1TS U3801 ( .A(P_Sgf[83]), .B(n7749), .S0(n7850), .Y(n504) );
INVX2TS U3802 ( .A(n7755), .Y(n7757) );
INVX2TS U3803 ( .A(n7791), .Y(n7793) );
MX2X1TS U3804 ( .A(P_Sgf[67]), .B(n7977), .S0(n7988), .Y(n488) );
OAI21XLTS U3805 ( .A0(n7987), .A1(n7983), .B0(n7984), .Y(n7976) );
MX2X1TS U3806 ( .A(P_Sgf[64]), .B(n8022), .S0(n8133), .Y(n485) );
INVX2TS U3807 ( .A(n8017), .Y(n8019) );
INVX2TS U3808 ( .A(n8076), .Y(n8078) );
OAI21XLTS U3809 ( .A0(n8087), .A1(n8099), .B0(n8100), .Y(n8092) );
OAI21XLTS U3810 ( .A0(n8175), .A1(n8171), .B0(n8172), .Y(n8166) );
MX2X1TS U3811 ( .A(n7884), .B(Add_result[21]), .S0(n8186), .Y(n558) );
MX2X1TS U3812 ( .A(n7943), .B(Add_result[17]), .S0(n8186), .Y(n562) );
MX2X1TS U3813 ( .A(n7971), .B(Add_result[15]), .S0(n7473), .Y(n564) );
MX2X1TS U3814 ( .A(n8127), .B(Add_result[4]), .S0(n8186), .Y(n575) );
XNOR2X1TS U3815 ( .A(n7291), .B(n7290), .Y(Sgf_operation_ODD1_middle_N32) );
NAND2X1TS U3816 ( .A(n7289), .B(n7288), .Y(n7290) );
OAI21X1TS U3817 ( .A0(n7379), .A1(n7287), .B0(n7244), .Y(n7291) );
OAI21X1TS U3818 ( .A0(n7005), .A1(n764), .B0(n1039), .Y(
Sgf_operation_ODD1_right_N0) );
NAND2X1TS U3819 ( .A(n7432), .B(n7431), .Y(n7433) );
NAND2X1TS U3820 ( .A(n7417), .B(n7426), .Y(n7429) );
NAND2X1TS U3821 ( .A(n7323), .B(n7318), .Y(n7320) );
AND2X2TS U3822 ( .A(n791), .B(n7328), .Y(n763) );
NAND2X1TS U3823 ( .A(n771), .B(n7275), .Y(n7276) );
NAND2X1TS U3824 ( .A(n7412), .B(n7411), .Y(n7413) );
AND2X2TS U3825 ( .A(n3915), .B(n3914), .Y(n970) );
NAND2X1TS U3826 ( .A(n7340), .B(n7339), .Y(n7341) );
NAND2X1TS U3827 ( .A(n7241), .B(n7240), .Y(n7242) );
XOR2X2TS U3828 ( .A(n3907), .B(n977), .Y(Sgf_operation_ODD1_left_N51) );
CLKAND2X2TS U3829 ( .A(n5943), .B(n3906), .Y(n977) );
OAI31X1TS U3830 ( .A0(n7535), .A1(n7484), .A2(n7534), .B0(n8448), .Y(n709)
);
MX2X1TS U3831 ( .A(Data_MY[1]), .B(Op_MY[1]), .S0(n7495), .Y(n583) );
MX2X1TS U3832 ( .A(Data_MY[3]), .B(Op_MY[3]), .S0(n8371), .Y(n585) );
MX2X1TS U3833 ( .A(Data_MY[4]), .B(Op_MY[4]), .S0(n896), .Y(n586) );
MX2X1TS U3834 ( .A(Data_MY[22]), .B(Op_MY[22]), .S0(n7499), .Y(n604) );
MX2X1TS U3835 ( .A(Data_MY[23]), .B(Op_MY[23]), .S0(n7502), .Y(n605) );
MX2X1TS U3836 ( .A(Data_MY[28]), .B(n903), .S0(n7505), .Y(n610) );
MX2X1TS U3837 ( .A(Data_MY[34]), .B(Op_MY[34]), .S0(n896), .Y(n616) );
MX2X1TS U3838 ( .A(Data_MY[37]), .B(n5802), .S0(n8371), .Y(n619) );
MX2X1TS U3839 ( .A(Data_MY[41]), .B(Op_MY[41]), .S0(n7509), .Y(n623) );
MX2X1TS U3840 ( .A(Data_MY[43]), .B(Op_MY[43]), .S0(n8371), .Y(n625) );
MX2X1TS U3841 ( .A(Data_MY[44]), .B(Op_MY[44]), .S0(n7505), .Y(n626) );
MX2X1TS U3842 ( .A(Data_MY[46]), .B(Op_MY[46]), .S0(n7506), .Y(n628) );
MX2X1TS U3843 ( .A(Data_MX[11]), .B(Op_MX[11]), .S0(n7496), .Y(n657) );
MX2X1TS U3844 ( .A(Data_MX[12]), .B(Op_MX[12]), .S0(n7496), .Y(n658) );
MX2X1TS U3845 ( .A(Data_MX[19]), .B(Op_MX[19]), .S0(n7509), .Y(n665) );
MX2X1TS U3846 ( .A(Data_MX[20]), .B(Op_MX[20]), .S0(n7505), .Y(n666) );
MX2X1TS U3847 ( .A(Data_MX[21]), .B(Op_MX[21]), .S0(n7506), .Y(n667) );
MX2X1TS U3848 ( .A(Data_MX[33]), .B(Op_MX[33]), .S0(n7502), .Y(n679) );
MX2X1TS U3849 ( .A(Data_MX[35]), .B(n7492), .S0(n7497), .Y(n681) );
MX2X1TS U3850 ( .A(Data_MX[44]), .B(n737), .S0(n7499), .Y(n690) );
MX2X1TS U3851 ( .A(Data_MX[45]), .B(Op_MX[45]), .S0(n7502), .Y(n691) );
MX2X1TS U3852 ( .A(Data_MX[46]), .B(Op_MX[46]), .S0(n7497), .Y(n692) );
NAND2X1TS U3853 ( .A(n7302), .B(n7301), .Y(n7303) );
OAI21X2TS U3854 ( .A0(n7430), .A1(n7299), .B0(n7298), .Y(n7304) );
NAND2X1TS U3855 ( .A(n7419), .B(n1016), .Y(n7350) );
XOR2X1TS U3856 ( .A(n891), .B(n4652), .Y(Sgf_operation_ODD1_middle_N36) );
XNOR2X1TS U3857 ( .A(n7367), .B(n7366), .Y(Sgf_operation_ODD1_middle_N35) );
NAND2X1TS U3858 ( .A(n7365), .B(n7364), .Y(n7366) );
NAND2X1TS U3859 ( .A(n7249), .B(n7355), .Y(n7250) );
XNOR2X1TS U3860 ( .A(n7286), .B(n7285), .Y(Sgf_operation_ODD1_middle_N33) );
NAND2X1TS U3861 ( .A(n7284), .B(n7283), .Y(n7285) );
OAI2BB1X1TS U3862 ( .A0N(n7281), .A1N(n799), .B0(n7280), .Y(n7286) );
XNOR2X1TS U3863 ( .A(n7384), .B(n7383), .Y(Sgf_operation_ODD1_middle_N31) );
NAND2X1TS U3864 ( .A(n7382), .B(n7381), .Y(n7383) );
XNOR2X1TS U3865 ( .A(n7256), .B(n7255), .Y(Sgf_operation_ODD1_middle_N30) );
NAND2X1TS U3866 ( .A(n7374), .B(n7376), .Y(n7255) );
XNOR2X1TS U3867 ( .A(n7372), .B(n7371), .Y(Sgf_operation_ODD1_middle_N29) );
NAND2X1TS U3868 ( .A(n7370), .B(n7369), .Y(n7371) );
XOR2X1TS U3869 ( .A(n7266), .B(n7265), .Y(Sgf_operation_ODD1_middle_N27) );
NAND2X1TS U3870 ( .A(n7264), .B(n7263), .Y(n7265) );
AOI21X1TS U3871 ( .A0(n7436), .A1(n7261), .B0(n7260), .Y(n7266) );
XOR2X1TS U3872 ( .A(n7441), .B(n7440), .Y(Sgf_operation_ODD1_middle_N26) );
NAND2X1TS U3873 ( .A(n7439), .B(n7438), .Y(n7440) );
XOR2X1TS U3874 ( .A(n7273), .B(n7272), .Y(Sgf_operation_ODD1_middle_N25) );
NAND2X1TS U3875 ( .A(n7271), .B(n7270), .Y(n7272) );
AOI21X1TS U3876 ( .A0(n7436), .A1(n7268), .B0(n7267), .Y(n7273) );
NAND2X1TS U3877 ( .A(n7148), .B(n964), .Y(n7149) );
XOR2X1TS U3878 ( .A(n7404), .B(n7403), .Y(Sgf_operation_ODD1_middle_N19) );
NAND2X1TS U3879 ( .A(n7402), .B(n7401), .Y(n7403) );
AOI21X1TS U3880 ( .A0(n7156), .A1(n7399), .B0(n7398), .Y(n7404) );
XOR2X1TS U3881 ( .A(n7236), .B(n7235), .Y(Sgf_operation_ODD1_middle_N18) );
NAND2X1TS U3882 ( .A(n7234), .B(n7395), .Y(n7235) );
XOR2X1TS U3883 ( .A(n7392), .B(n7391), .Y(Sgf_operation_ODD1_middle_N17) );
NAND2X1TS U3884 ( .A(n7389), .B(n7390), .Y(n7391) );
AOI21X1TS U3885 ( .A0(n7156), .A1(n7387), .B0(n7386), .Y(n7392) );
CLKAND2X2TS U3886 ( .A(n7225), .B(n7224), .Y(Sgf_operation_ODD1_middle_N1)
);
XNOR2X1TS U3887 ( .A(n5253), .B(n5252), .Y(Sgf_operation_ODD1_right_N34) );
XNOR2X1TS U3888 ( .A(n5248), .B(n5247), .Y(Sgf_operation_ODD1_right_N33) );
XOR2X1TS U3889 ( .A(n7105), .B(n7104), .Y(Sgf_operation_ODD1_right_N29) );
NAND2X1TS U3890 ( .A(n7103), .B(n7102), .Y(n7104) );
AOI21X1TS U3891 ( .A0(n7108), .A1(n7100), .B0(n7099), .Y(n7105) );
XOR2X1TS U3892 ( .A(n6979), .B(n6978), .Y(Sgf_operation_ODD1_right_N28) );
NAND2X1TS U3893 ( .A(n6977), .B(n7096), .Y(n6978) );
XOR2X1TS U3894 ( .A(n7112), .B(n7111), .Y(Sgf_operation_ODD1_right_N26) );
AOI21X1TS U3895 ( .A0(n7108), .A1(n7107), .B0(n7106), .Y(n7112) );
OAI21XLTS U3896 ( .A0(n6130), .A1(n6111), .B0(n6110), .Y(n6115) );
OAI21XLTS U3897 ( .A0(n6130), .A1(n6117), .B0(n6116), .Y(n6121) );
OAI21XLTS U3898 ( .A0(n6130), .A1(n6122), .B0(n6127), .Y(n6126) );
XOR2XLTS U3899 ( .A(n6130), .B(n6129), .Y(Sgf_operation_ODD1_right_N21) );
AOI21X1TS U3900 ( .A0(n6139), .A1(n6137), .B0(n6132), .Y(n6135) );
XOR2XLTS U3901 ( .A(n6208), .B(n6207), .Y(Sgf_operation_ODD1_right_N4) );
AOI21X2TS U3902 ( .A0(n5268), .A1(n5267), .B0(n5266), .Y(n5269) );
XOR2X2TS U3903 ( .A(n3781), .B(n992), .Y(Sgf_operation_ODD1_left_N41) );
INVX2TS U3904 ( .A(n4856), .Y(n4764) );
XNOR2X2TS U3905 ( .A(n4797), .B(n4796), .Y(Sgf_operation_ODD1_left_N33) );
AOI21X1TS U3906 ( .A0(n5315), .A1(n5292), .B0(n5291), .Y(n5297) );
XOR2X1TS U3907 ( .A(n5992), .B(n5991), .Y(Sgf_operation_ODD1_left_N19) );
NAND2X1TS U3908 ( .A(n787), .B(n5990), .Y(n5991) );
AOI21X1TS U3909 ( .A0(n5989), .A1(n5988), .B0(n5987), .Y(n5992) );
AOI21X1TS U3910 ( .A0(n5989), .A1(n5341), .B0(n5334), .Y(n5339) );
XOR2XLTS U3911 ( .A(n5813), .B(n5812), .Y(Sgf_operation_ODD1_left_N7) );
XOR2X2TS U3912 ( .A(n6782), .B(n6882), .Y(mult_x_24_n1418) );
OAI22X2TS U3913 ( .A0(n1529), .A1(n2738), .B0(n1519), .B1(n2045), .Y(n1531)
);
CLKXOR2X4TS U3914 ( .A(n1320), .B(n1319), .Y(n1828) );
XOR2X2TS U3915 ( .A(n5449), .B(Op_MX[50]), .Y(mult_x_23_n1263) );
OAI21X4TS U3916 ( .A0(n891), .A1(n4830), .B0(n4829), .Y(n4833) );
ADDFX2TS U3917 ( .A(n3457), .B(n3456), .CI(n3455), .CO(n3461), .S(n3441) );
XOR2X2TS U3918 ( .A(n4708), .B(n6794), .Y(n4714) );
ADDFHX2TS U3919 ( .A(n2746), .B(n2745), .CI(n2744), .CO(n2797), .S(n2749) );
ADDFHX4TS U3920 ( .A(n1934), .B(n1933), .CI(n1932), .CO(n1940), .S(n1939) );
ADDFHX2TS U3921 ( .A(n2587), .B(n2586), .CI(n2585), .CO(n2625), .S(n2596) );
AOI21X2TS U3922 ( .A0(n3893), .A1(n4948), .B0(n3892), .Y(n3894) );
OAI21X1TS U3923 ( .A0(n5938), .A1(n6052), .B0(n5937), .Y(mult_x_23_n1243) );
ADDFHX4TS U3924 ( .A(n2441), .B(n2440), .CI(n2439), .CO(n2449), .S(n2448) );
OAI21X1TS U3925 ( .A0(n6068), .A1(n6014), .B0(n4680), .Y(n4681) );
OAI21X1TS U3926 ( .A0(n5781), .A1(n5761), .B0(n5720), .Y(n5721) );
OR2X6TS U3927 ( .A(n2188), .B(n2187), .Y(n7143) );
XOR2X2TS U3928 ( .A(n3617), .B(n6069), .Y(n3630) );
NOR2X4TS U3929 ( .A(n1431), .B(n1434), .Y(n1453) );
BUFX12TS U3930 ( .A(n1763), .Y(n1698) );
OA21X1TS U3931 ( .A0(n5307), .A1(n5312), .B0(n5308), .Y(n762) );
NOR2X8TS U3932 ( .A(mult_x_23_n834), .B(mult_x_23_n824), .Y(n5307) );
OR2X4TS U3933 ( .A(n1599), .B(n1598), .Y(n789) );
OAI21X2TS U3934 ( .A0(n5162), .A1(n3895), .B0(n3894), .Y(n4923) );
CMPR42X2TS U3935 ( .A(n1022), .B(mult_x_23_n679), .C(mult_x_23_n1246), .D(
mult_x_23_n1294), .ICI(mult_x_23_n676), .S(mult_x_23_n672), .ICO(
mult_x_23_n666), .CO(mult_x_23_n671) );
NOR2X4TS U3936 ( .A(n6005), .B(n6016), .Y(n4984) );
NOR2X2TS U3937 ( .A(n5951), .B(n5359), .Y(n3745) );
INVX4TS U3938 ( .A(n3634), .Y(n3719) );
ADDFX2TS U3939 ( .A(n3357), .B(n3356), .CI(n3355), .CO(n3477), .S(n3341) );
ADDFHX2TS U3940 ( .A(n2734), .B(n2733), .CI(n2732), .CO(n2792), .S(n2741) );
OAI22X1TS U3941 ( .A0(n2216), .A1(n890), .B0(n2480), .B1(n2762), .Y(n2464)
);
ADDFX2TS U3942 ( .A(n2487), .B(n2486), .CI(n2485), .CO(n2597), .S(n2492) );
XNOR2X2TS U3943 ( .A(n3364), .B(n2939), .Y(n2480) );
NAND2X4TS U3944 ( .A(mult_x_24_n918), .B(mult_x_24_n930), .Y(n6103) );
OAI21X2TS U3945 ( .A0(n1145), .A1(n1144), .B0(n1143), .Y(n1150) );
XOR2X2TS U3946 ( .A(n6630), .B(n6758), .Y(mult_x_24_n1586) );
ADDFHX4TS U3947 ( .A(n2668), .B(n2667), .CI(n2666), .CO(n2918), .S(n2917) );
ADDFHX2TS U3948 ( .A(n2568), .B(n2567), .CI(n2566), .CO(n2657), .S(n2571) );
NAND2X2TS U3949 ( .A(mult_x_24_n751), .B(mult_x_24_n759), .Y(n4882) );
XNOR2X1TS U3950 ( .A(n5231), .B(n5230), .Y(Sgf_operation_ODD1_right_N36) );
OAI21X2TS U3951 ( .A0(n6092), .A1(n5227), .B0(n5226), .Y(n5231) );
OAI21X2TS U3952 ( .A0(n5280), .A1(n4781), .B0(n4780), .Y(n4786) );
INVX4TS U3953 ( .A(n4897), .Y(n4790) );
NOR2X8TS U3954 ( .A(n7278), .B(n7282), .Y(n7352) );
ADDFHX4TS U3955 ( .A(n2805), .B(n2804), .CI(n2803), .CO(n2925), .S(n2923) );
AOI222X1TS U3956 ( .A0(n6065), .A1(n8375), .B0(n6064), .B1(n6055), .C0(n6063), .C1(n6054), .Y(n6056) );
XNOR2X2TS U3957 ( .A(n2954), .B(n2653), .Y(n1829) );
ADDFHX2TS U3958 ( .A(n3135), .B(n3134), .CI(n3133), .CO(n3558), .S(n3550) );
AOI21X2TS U3959 ( .A0(n4822), .A1(n3572), .B0(n3571), .Y(n3591) );
ADDFHX4TS U3960 ( .A(n2681), .B(n2680), .CI(n2679), .CO(n2911), .S(n2452) );
CMPR42X2TS U3961 ( .A(mult_x_24_n1509), .B(mult_x_24_n1590), .C(
mult_x_24_n1617), .D(mult_x_24_n1644), .ICI(mult_x_24_n967), .S(
mult_x_24_n958), .ICO(mult_x_24_n956), .CO(mult_x_24_n957) );
OAI21X4TS U3962 ( .A0(n5161), .A1(n5271), .B0(n5164), .Y(n5151) );
BUFX3TS U3963 ( .A(n5712), .Y(n5745) );
INVX4TS U3964 ( .A(n765), .Y(n828) );
INVX2TS U3965 ( .A(n3662), .Y(n869) );
INVX2TS U3966 ( .A(n6405), .Y(n843) );
INVX4TS U3967 ( .A(n843), .Y(n844) );
INVX4TS U3968 ( .A(n880), .Y(n881) );
INVX4TS U3969 ( .A(n798), .Y(n848) );
BUFX3TS U3970 ( .A(Op_MX[13]), .Y(n6569) );
INVX4TS U3971 ( .A(n811), .Y(n1047) );
OR2X2TS U3972 ( .A(n999), .B(n1048), .Y(n811) );
INVX4TS U3973 ( .A(n756), .Y(n852) );
INVX2TS U3974 ( .A(n3669), .Y(n872) );
INVX2TS U3975 ( .A(n802), .Y(n850) );
OR2X1TS U3976 ( .A(n6021), .B(n737), .Y(n774) );
OR2X1TS U3977 ( .A(n6220), .B(Op_MY[17]), .Y(n775) );
OR2X1TS U3978 ( .A(n927), .B(n6562), .Y(n776) );
OR2X1TS U3979 ( .A(n8378), .B(Op_MY[51]), .Y(n778) );
INVX4TS U3980 ( .A(n772), .Y(n833) );
CLKINVX3TS U3981 ( .A(n772), .Y(n834) );
BUFX3TS U3982 ( .A(Op_MX[16]), .Y(n6562) );
OR2X2TS U3983 ( .A(mult_x_23_n929), .B(mult_x_23_n935), .Y(n780) );
OR2X1TS U3984 ( .A(n4232), .B(Sgf_operation_ODD1_Q_right[29]), .Y(n781) );
BUFX3TS U3985 ( .A(Op_MX[17]), .Y(n6559) );
OR2X2TS U3986 ( .A(mult_x_24_n760), .B(mult_x_24_n768), .Y(n784) );
OR2X2TS U3987 ( .A(mult_x_24_n729), .B(mult_x_24_n735), .Y(n785) );
INVX4TS U3988 ( .A(n794), .Y(n925) );
AOI22X1TS U3989 ( .A0(n5712), .A1(n4966), .B0(n5748), .B1(n6054), .Y(n795)
);
NAND2X1TS U3990 ( .A(n6060), .B(n824), .Y(n796) );
NOR2BX2TS U3991 ( .AN(n3614), .B(n3613), .Y(n4967) );
NOR2BX2TS U3992 ( .AN(n4654), .B(n4653), .Y(n5096) );
CLKBUFX2TS U3993 ( .A(Op_MY[31]), .Y(n7510) );
AND2X2TS U3994 ( .A(n7354), .B(n7289), .Y(n799) );
INVX6TS U3995 ( .A(n811), .Y(n884) );
OR2X1TS U3996 ( .A(Op_MY[14]), .B(n8373), .Y(n805) );
OR2X1TS U3997 ( .A(Op_MY[50]), .B(n6820), .Y(n806) );
OR2X1TS U3998 ( .A(Op_MX[21]), .B(Op_MX[20]), .Y(n808) );
OR2X1TS U3999 ( .A(Op_MX[41]), .B(Op_MX[35]), .Y(n809) );
NOR4X1TS U4000 ( .A(Op_MY[22]), .B(Op_MY[21]), .C(Op_MY[16]), .D(Op_MY[3]),
.Y(n810) );
OAI21X2TS U4001 ( .A0(n7101), .A1(n7096), .B0(n7102), .Y(n1181) );
CMPR42X2TS U4002 ( .A(mult_x_24_n898), .B(mult_x_24_n887), .C(mult_x_24_n895), .D(mult_x_24_n884), .ICI(mult_x_24_n891), .S(mult_x_24_n881), .ICO(
mult_x_24_n879), .CO(mult_x_24_n880) );
OAI21X2TS U4003 ( .A0(n7026), .A1(n6681), .B0(n1060), .Y(n1061) );
NAND2X4TS U4004 ( .A(n1118), .B(n1120), .Y(n1123) );
XOR2X2TS U4005 ( .A(n6821), .B(n8377), .Y(mult_x_24_n1614) );
NAND2X4TS U4006 ( .A(n2917), .B(n2916), .Y(n7374) );
ADDFHX2TS U4007 ( .A(n2458), .B(n2457), .CI(n2456), .CO(n2553), .S(n2495) );
BUFX3TS U4008 ( .A(Op_MY[37]), .Y(n814) );
BUFX3TS U4009 ( .A(Op_MY[37]), .Y(n7507) );
INVX8TS U4010 ( .A(n1203), .Y(n6735) );
AOI21X4TS U4011 ( .A0(n5987), .A1(n787), .B0(n3752), .Y(n3753) );
OAI21X4TS U4012 ( .A0(n7355), .A1(n7363), .B0(n7364), .Y(n2930) );
AOI21X2TS U4013 ( .A0(n4959), .A1(n4963), .B0(n4926), .Y(n4927) );
NAND2X2TS U4014 ( .A(n5458), .B(n5464), .Y(n3841) );
NAND2X2TS U4015 ( .A(n4863), .B(n1028), .Y(n4868) );
OAI21X4TS U4016 ( .A0(n4912), .A1(n5281), .B0(n4913), .Y(n3764) );
NOR2X4TS U4017 ( .A(n1591), .B(n1590), .Y(n7226) );
BUFX20TS U4018 ( .A(n2936), .Y(n891) );
ADDFHX4TS U4019 ( .A(n3316), .B(n3315), .CI(n3314), .CO(n3519), .S(n3517) );
ADDFHX2TS U4020 ( .A(n2326), .B(n2325), .CI(n2324), .CO(n2467), .S(n2327) );
NOR2X4TS U4021 ( .A(n2912), .B(n2911), .Y(n7368) );
ADDFHX2TS U4022 ( .A(n3147), .B(n3146), .CI(n3145), .CO(n3560), .S(n3557) );
ADDFHX2TS U4023 ( .A(n1937), .B(n1936), .CI(n1935), .CO(n1938), .S(n1737) );
OAI21X4TS U4024 ( .A0(n924), .A1(n3905), .B0(n3904), .Y(n3907) );
CMPR42X2TS U4025 ( .A(mult_x_24_n1445), .B(mult_x_24_n1580), .C(
mult_x_24_n1526), .D(mult_x_24_n1499), .ICI(mult_x_24_n849), .S(
mult_x_24_n839), .ICO(mult_x_24_n837), .CO(mult_x_24_n838) );
XNOR2X2TS U4026 ( .A(n859), .B(n1518), .Y(n1529) );
ADDFHX2TS U4027 ( .A(n1861), .B(n1860), .CI(n1859), .CO(n1854), .S(n1930) );
XNOR2X2TS U4028 ( .A(n3285), .B(n2583), .Y(n1814) );
ADDFHX4TS U4029 ( .A(n3499), .B(n3498), .CI(n3497), .CO(n3526), .S(n3521) );
ADDFHX2TS U4030 ( .A(n3375), .B(n3374), .CI(n3373), .CO(n3497), .S(n3317) );
AOI21X1TS U4031 ( .A0(n7156), .A1(n7393), .B0(n7233), .Y(n7236) );
XOR2X4TS U4032 ( .A(n1400), .B(n1399), .Y(n2018) );
ADDFHX4TS U4033 ( .A(n3265), .B(n3264), .CI(n3263), .CO(n3518), .S(n3516) );
CMPR42X2TS U4034 ( .A(n6934), .B(mult_x_24_n1105), .C(mult_x_24_n1473), .D(
mult_x_24_n1446), .ICI(mult_x_24_n1419), .S(mult_x_24_n854), .ICO(
mult_x_24_n852), .CO(mult_x_24_n853) );
ADDFHX4TS U4035 ( .A(n2691), .B(n2690), .CI(n2689), .CO(n2922), .S(n2919) );
OAI21X1TS U4036 ( .A0(n7075), .A1(n6992), .B0(n6640), .Y(n6641) );
AOI21X4TS U4037 ( .A0(n5121), .A1(n5120), .B0(n5119), .Y(n5141) );
NOR2X4TS U4038 ( .A(Op_MX[17]), .B(n6829), .Y(n6310) );
XNOR2X4TS U4039 ( .A(n2685), .B(n2688), .Y(n2678) );
ADDFHX4TS U4040 ( .A(n2671), .B(n2670), .CI(n2669), .CO(n2685), .S(n2680) );
ADDFHX2TS U4041 ( .A(n2435), .B(n2434), .CI(n2433), .CO(n2443), .S(n2427) );
XNOR2X2TS U4042 ( .A(n1397), .B(n1398), .Y(n1518) );
BUFX3TS U4043 ( .A(Op_MY[31]), .Y(n8376) );
INVX2TS U4044 ( .A(n801), .Y(n830) );
INVX2TS U4045 ( .A(n782), .Y(n831) );
INVX2TS U4046 ( .A(n782), .Y(n832) );
BUFX3TS U4047 ( .A(n5840), .Y(n5845) );
BUFX3TS U4048 ( .A(n5840), .Y(n6033) );
INVX2TS U4049 ( .A(n802), .Y(n837) );
INVX2TS U4050 ( .A(n802), .Y(n838) );
INVX2TS U4051 ( .A(n804), .Y(n839) );
INVX2TS U4052 ( .A(n804), .Y(n840) );
INVX2TS U4053 ( .A(n770), .Y(n841) );
INVX2TS U4054 ( .A(n770), .Y(n842) );
INVX2TS U4055 ( .A(FSM_selector_A), .Y(n845) );
INVX2TS U4056 ( .A(n845), .Y(n846) );
INVX2TS U4057 ( .A(n798), .Y(n849) );
OAI21X2TS U4058 ( .A0(n819), .A1(n2004), .B0(n2003), .Y(n2007) );
OAI21X2TS U4059 ( .A0(n817), .A1(n2238), .B0(n2247), .Y(n1978) );
OAI21X2TS U4060 ( .A0(n819), .A1(n1777), .B0(n1779), .Y(n1771) );
OAI21X2TS U4061 ( .A0(n817), .A1(n1960), .B0(n1959), .Y(n1963) );
OAI21X2TS U4062 ( .A0(n740), .A1(n6414), .B0(n6415), .Y(n6337) );
OAI21X2TS U4063 ( .A0(n740), .A1(n6259), .B0(n6258), .Y(n6264) );
OAI21X2TS U4064 ( .A0(n820), .A1(n6313), .B0(n6312), .Y(n6318) );
OAI21X2TS U4065 ( .A0(n740), .A1(n6394), .B0(n6393), .Y(n6399) );
OAI21X2TS U4066 ( .A0(n740), .A1(n6286), .B0(n6285), .Y(n6291) );
OAI21X2TS U4067 ( .A0(n740), .A1(n6280), .B0(n6281), .Y(n1218) );
XNOR2X2TS U4068 ( .A(n853), .B(n2771), .Y(n2810) );
XNOR2X2TS U4069 ( .A(n853), .B(n2939), .Y(n2951) );
INVX4TS U4070 ( .A(n854), .Y(n855) );
INVX8TS U4071 ( .A(n2534), .Y(n859) );
XNOR2X2TS U4072 ( .A(n858), .B(n1747), .Y(n1748) );
INVX4TS U4073 ( .A(n866), .Y(n867) );
INVX4TS U4074 ( .A(n869), .Y(n870) );
INVX2TS U4075 ( .A(n869), .Y(n871) );
BUFX3TS U4076 ( .A(n6930), .Y(n874) );
AOI222X4TS U4077 ( .A0(n6736), .A1(n6814), .B0(n7070), .B1(n6846), .C0(n6405), .C1(n6930), .Y(n6403) );
BUFX3TS U4078 ( .A(n7068), .Y(n875) );
NOR2X2TS U4079 ( .A(n827), .B(n7068), .Y(n6349) );
NAND2X2TS U4080 ( .A(n7068), .B(n7056), .Y(n6354) );
NAND2X2TS U4081 ( .A(n827), .B(n7068), .Y(n6363) );
CLKBUFX2TS U4082 ( .A(Op_MX[20]), .Y(n878) );
CLKBUFX2TS U4083 ( .A(Op_MX[20]), .Y(n879) );
NAND2X2TS U4084 ( .A(n876), .B(n6930), .Y(n6295) );
NAND2X2TS U4085 ( .A(n876), .B(n6952), .Y(n6301) );
AOI222X1TS U4086 ( .A0(n6817), .A1(n879), .B0(n887), .B1(n6830), .C0(n6813),
.C1(n8403), .Y(n1220) );
NOR2X2TS U4087 ( .A(n876), .B(n6930), .Y(n3812) );
BUFX3TS U4088 ( .A(n7011), .Y(n883) );
NOR2X6TS U4089 ( .A(n4737), .B(n4736), .Y(n7011) );
BUFX6TS U4090 ( .A(n7011), .Y(n6870) );
INVX2TS U4091 ( .A(n811), .Y(n885) );
CLKINVX6TS U4092 ( .A(n6815), .Y(n886) );
NAND2X2TS U4093 ( .A(n886), .B(n5041), .Y(n962) );
OAI21X2TS U4094 ( .A0(n891), .A1(n3596), .B0(n3595), .Y(n3600) );
OAI21X2TS U4095 ( .A0(n7430), .A1(n7409), .B0(n7408), .Y(n7414) );
OAI21X2TS U4096 ( .A0(n7430), .A1(n7238), .B0(n7237), .Y(n7243) );
OAI21X2TS U4097 ( .A0(n7430), .A1(n1023), .B0(n7274), .Y(n7277) );
OAI21X2TS U4098 ( .A0(n7430), .A1(n7338), .B0(n7337), .Y(n7342) );
NOR2X4TS U4099 ( .A(n7547), .B(FSM_selector_C), .Y(n8069) );
INVX2TS U4100 ( .A(n783), .Y(n892) );
INVX2TS U4101 ( .A(n783), .Y(n893) );
BUFX3TS U4102 ( .A(n7471), .Y(n8535) );
NAND2X1TS U4103 ( .A(n5395), .B(n5396), .Y(n5393) );
NOR2X2TS U4104 ( .A(n3714), .B(n3713), .Y(n5809) );
BUFX4TS U4105 ( .A(n6620), .Y(n6887) );
INVX2TS U4106 ( .A(n6974), .Y(n8378) );
NOR4X1TS U4107 ( .A(Op_MX[25]), .B(Op_MX[1]), .C(Op_MX[38]), .D(n8404), .Y(
n8405) );
INVX2TS U4108 ( .A(n767), .Y(n8404) );
AOI222X1TS U4109 ( .A0(n5748), .A1(n5796), .B0(n5712), .B1(n5982), .C0(n5751), .C1(n814), .Y(n5746) );
AOI222X1TS U4110 ( .A0(n5748), .A1(n6024), .B0(n5759), .B1(n840), .C0(n5732),
.C1(n5966), .Y(n5733) );
BUFX3TS U4111 ( .A(Op_MX[18]), .Y(n927) );
INVX2TS U4112 ( .A(n735), .Y(n8373) );
ADDFHX2TS U4113 ( .A(n5055), .B(n5054), .CI(n5053), .CO(mult_x_24_n1039),
.S(mult_x_24_n1040) );
CLKINVX3TS U4114 ( .A(n1013), .Y(n8391) );
NOR2X4TS U4115 ( .A(FS_Module_state_reg[3]), .B(n8369), .Y(n8430) );
INVX2TS U4116 ( .A(n1154), .Y(n963) );
CLKXOR2X2TS U4117 ( .A(n1153), .B(n8391), .Y(n1154) );
NOR3XLTS U4118 ( .A(Op_MX[34]), .B(Op_MX[53]), .C(Op_MX[52]), .Y(n8419) );
INVX4TS U4119 ( .A(n8365), .Y(n7502) );
INVX4TS U4120 ( .A(n8372), .Y(n7509) );
INVX4TS U4121 ( .A(n8365), .Y(n7497) );
INVX4TS U4122 ( .A(n8365), .Y(n7501) );
INVX4TS U4123 ( .A(n8365), .Y(n7499) );
AOI21X2TS U4124 ( .A0(n7325), .A1(n3594), .B0(n3593), .Y(n3595) );
AOI21X2TS U4125 ( .A0(n7325), .A1(n7297), .B0(n7296), .Y(n7298) );
AOI222X1TS U4126 ( .A0(n5748), .A1(n5871), .B0(n5745), .B1(n5870), .C0(n5732), .C1(n6080), .Y(n5724) );
BUFX4TS U4127 ( .A(n3179), .Y(n2730) );
XNOR2X2TS U4128 ( .A(n3359), .B(n2997), .Y(n2816) );
BUFX16TS U4129 ( .A(n1706), .Y(n3359) );
XNOR2X1TS U4130 ( .A(n3334), .B(n3383), .Y(n3385) );
INVX4TS U4131 ( .A(n3334), .Y(n3053) );
INVX8TS U4132 ( .A(n2474), .Y(n3281) );
CLKINVX12TS U4133 ( .A(n3281), .Y(n900) );
XNOR2X1TS U4134 ( .A(n901), .B(n1979), .Y(n2030) );
XNOR2X1TS U4135 ( .A(n901), .B(n1872), .Y(n1873) );
XNOR2X1TS U4136 ( .A(n900), .B(n2871), .Y(n2872) );
INVX2TS U4137 ( .A(n901), .Y(n3282) );
INVX4TS U4138 ( .A(n797), .Y(n902) );
INVX2TS U4139 ( .A(n797), .Y(n903) );
XNOR2X1TS U4140 ( .A(n908), .B(n2997), .Y(n2277) );
INVX2TS U4141 ( .A(n853), .Y(n3584) );
XNOR2X1TS U4142 ( .A(n3582), .B(n3343), .Y(n3429) );
XNOR2X2TS U4143 ( .A(n853), .B(n2881), .Y(n3180) );
XNOR2X2TS U4144 ( .A(n909), .B(n3167), .Y(n3105) );
XNOR2X2TS U4145 ( .A(n909), .B(n3383), .Y(n3045) );
XNOR2X1TS U4146 ( .A(n3368), .B(n2518), .Y(n2562) );
XNOR2X1TS U4147 ( .A(n917), .B(n2221), .Y(n3366) );
INVX2TS U4148 ( .A(n917), .Y(n2953) );
XNOR2X1TS U4149 ( .A(n919), .B(n3383), .Y(n2969) );
INVX2TS U4150 ( .A(n922), .Y(n3033) );
BUFX6TS U4151 ( .A(n5494), .Y(n923) );
AOI222X1TS U4152 ( .A0(n5840), .A1(n6055), .B0(n5494), .B1(n5839), .C0(n5844), .C1(n5213), .Y(n4662) );
INVX16TS U4153 ( .A(n3772), .Y(n924) );
OAI21X2TS U4154 ( .A0(n924), .A1(n3780), .B0(n3779), .Y(n3781) );
OAI21X2TS U4155 ( .A0(n924), .A1(n5166), .B0(n5165), .Y(n5169) );
OAI21X2TS U4156 ( .A0(n5271), .A1(n5176), .B0(n5175), .Y(n5181) );
OAI21X2TS U4157 ( .A0(n924), .A1(n5188), .B0(n5187), .Y(n5193) );
OAI21X2TS U4158 ( .A0(n5271), .A1(n5270), .B0(n5269), .Y(n5275) );
INVX2TS U4159 ( .A(n794), .Y(n926) );
NOR2X4TS U4160 ( .A(n925), .B(n6959), .Y(n6260) );
NAND2X2TS U4161 ( .A(n925), .B(n6959), .Y(n6261) );
NOR2X2TS U4162 ( .A(n6989), .B(n925), .Y(n6248) );
NOR2X2TS U4163 ( .A(n6829), .B(n6930), .Y(n6314) );
NAND2X4TS U4164 ( .A(Op_MX[17]), .B(n6829), .Y(n6326) );
OAI22X1TS U4165 ( .A0(n2810), .A1(n2100), .B0(n2808), .B1(n2876), .Y(n2866)
);
NAND2X6TS U4166 ( .A(n2808), .B(n1404), .Y(n2877) );
NAND2BX1TS U4167 ( .AN(n2223), .B(n4730), .Y(n2220) );
OAI22X1TS U4168 ( .A0(n3218), .A1(n3376), .B0(n3284), .B1(n3360), .Y(n3297)
);
BUFX3TS U4169 ( .A(n3376), .Y(n3361) );
OAI22X1TS U4170 ( .A0(n3332), .A1(n3333), .B0(n3304), .B1(n3331), .Y(n3355)
);
OAI22X1TS U4171 ( .A0(n2231), .A1(n3089), .B0(n2211), .B1(n931), .Y(n2323)
);
OAI22X2TS U4172 ( .A0(n2083), .A1(n3089), .B0(n3331), .B1(n3107), .Y(n2213)
);
BUFX3TS U4173 ( .A(n1751), .Y(n932) );
BUFX3TS U4174 ( .A(n1751), .Y(n933) );
OAI22X1TS U4175 ( .A0(n1645), .A1(n3301), .B0(n1624), .B1(n2839), .Y(n1665)
);
OAI22X1TS U4176 ( .A0(n2062), .A1(n3427), .B0(n2061), .B1(n3428), .Y(n2104)
);
BUFX3TS U4177 ( .A(n934), .Y(n3201) );
CLKMX2X2TS U4178 ( .A(Exp_module_Overflow_flag_A), .B(n4699), .S0(n8188),
.Y(n405) );
OAI22X1TS U4179 ( .A0(n1479), .A1(n2808), .B0(n1482), .B1(n928), .Y(n1541)
);
ADDFHX2TS U4180 ( .A(n1558), .B(n1557), .CI(n1556), .CO(n1587), .S(n1559) );
NOR4X1TS U4181 ( .A(Op_MX[45]), .B(Op_MX[39]), .C(Op_MX[27]), .D(Op_MX[51]),
.Y(n8408) );
BUFX3TS U4182 ( .A(n6558), .Y(n6980) );
AOI222X1TS U4183 ( .A0(n5748), .A1(n5779), .B0(n5745), .B1(n5778), .C0(n5732), .C1(n5871), .Y(n5720) );
CLKXOR2X2TS U4184 ( .A(n3654), .B(n5819), .Y(n3691) );
CLKINVX3TS U4185 ( .A(n793), .Y(n5694) );
OAI22X2TS U4186 ( .A0(beg_FSM), .A1(n8533), .B0(ack_FSM), .B1(n7478), .Y(
n8367) );
NOR2X2TS U4187 ( .A(n5123), .B(n5122), .Y(n5143) );
XOR2X1TS U4188 ( .A(n1110), .B(n6891), .Y(n1134) );
NOR3XLTS U4189 ( .A(Op_MY[25]), .B(Op_MY[52]), .C(Op_MY[53]), .Y(n8394) );
NOR4X1TS U4190 ( .A(n8393), .B(n8392), .C(n8391), .D(Op_MY[62]), .Y(n8395)
);
CLKMX2X2TS U4191 ( .A(P_Sgf[91]), .B(n4650), .S0(n7712), .Y(n512) );
XOR2X1TS U4192 ( .A(n3785), .B(n6002), .Y(n3791) );
NAND2BX4TS U4193 ( .AN(n3638), .B(n3639), .Y(n936) );
OAI21XLTS U4194 ( .A0(n979), .A1(n5861), .B0(n5860), .Y(n5862) );
BUFX3TS U4195 ( .A(n5861), .Y(n5761) );
XOR2X4TS U4196 ( .A(Op_MX[32]), .B(Op_MX[31]), .Y(n3639) );
INVX2TS U4197 ( .A(n6945), .Y(n7059) );
INVX2TS U4198 ( .A(n7059), .Y(n937) );
INVX2TS U4199 ( .A(n7059), .Y(n938) );
INVX2TS U4200 ( .A(n7059), .Y(n939) );
AOI222X1TS U4201 ( .A0(n7023), .A1(n938), .B0(n7021), .B1(Op_MX[14]), .C0(
n7019), .C1(n7056), .Y(n6567) );
AOI222X1TS U4202 ( .A0(n7060), .A1(n937), .B0(n7058), .B1(Op_MX[14]), .C0(
n7057), .C1(n7056), .Y(n7061) );
NOR4X1TS U4203 ( .A(Op_MX[26]), .B(Op_MX[47]), .C(Op_MX[29]), .D(Op_MX[62]),
.Y(n8420) );
NOR2X4TS U4204 ( .A(n7547), .B(n8448), .Y(n8178) );
XOR2X2TS U4205 ( .A(n960), .B(n6695), .Y(n1100) );
XOR2X2TS U4206 ( .A(n1053), .B(n8377), .Y(n1089) );
INVX4TS U4207 ( .A(n8372), .Y(n7504) );
NAND2X1TS U4208 ( .A(Sgf_normalized_result[3]), .B(Sgf_normalized_result[2]),
.Y(n8108) );
CMPR42X1TS U4209 ( .A(n6934), .B(mult_x_24_n1107), .C(mult_x_24_n1448), .D(
mult_x_24_n1421), .ICI(mult_x_24_n1502), .S(mult_x_24_n878), .ICO(
mult_x_24_n876), .CO(mult_x_24_n877) );
CLKINVX3TS U4210 ( .A(n1013), .Y(n8445) );
AOI21X4TS U4211 ( .A0(n7258), .A1(n2453), .B0(n943), .Y(n2454) );
XOR2X4TS U4212 ( .A(n945), .B(n1412), .Y(n944) );
OAI21X4TS U4213 ( .A0(n1675), .A1(n1431), .B0(n1433), .Y(n945) );
OAI21X4TS U4214 ( .A0(n1373), .A1(n948), .B0(n1374), .Y(n1345) );
NOR2X8TS U4215 ( .A(n947), .B(n946), .Y(n1029) );
INVX2TS U4216 ( .A(n948), .Y(n946) );
OAI21X4TS U4217 ( .A0(n6131), .A1(n949), .B0(n954), .Y(n6105) );
AOI21X4TS U4218 ( .A0(n6140), .A1(n957), .B0(n956), .Y(n6131) );
OAI21X4TS U4219 ( .A0(n1173), .A1(n6146), .B0(n1172), .Y(n6140) );
INVX2TS U4220 ( .A(n1174), .Y(n6137) );
AOI21X4TS U4221 ( .A0(n6105), .A1(n952), .B0(n950), .Y(n6093) );
OAI21X4TS U4222 ( .A0(n6116), .A1(n953), .B0(n951), .Y(n950) );
AOI21X4TS U4223 ( .A0(n6108), .A1(n6113), .B0(n1179), .Y(n951) );
NOR2X8TS U4224 ( .A(n1178), .B(n1177), .Y(n6116) );
AOI21X4TS U4225 ( .A0(n6132), .A1(n972), .B0(n1175), .Y(n954) );
INVX2TS U4226 ( .A(n972), .Y(n955) );
XOR2X4TS U4227 ( .A(n959), .B(n2154), .Y(n2179) );
AOI2BB2X2TS U4228 ( .B0(n6817), .B1(n6822), .A0N(n6681), .A1N(n5043), .Y(
n961) );
NAND2BX4TS U4229 ( .AN(n1155), .B(n963), .Y(n6190) );
AOI21X4TS U4230 ( .A0(n2186), .A1(n964), .B0(n2185), .Y(n7133) );
NAND2X4TS U4231 ( .A(n7152), .B(n964), .Y(n7142) );
ADDFHX2TS U4232 ( .A(n2153), .B(n2152), .CI(n2151), .CO(n2162), .S(n2173) );
OAI22X1TS U4233 ( .A0(n2099), .A1(n2976), .B0(n2063), .B1(n3006), .Y(n2103)
);
CLKXOR2X2TS U4234 ( .A(n3705), .B(n3610), .Y(n3611) );
AOI21X1TS U4235 ( .A0(n7108), .A1(n7094), .B0(n6976), .Y(n6979) );
AOI222X1TS U4236 ( .A0(n6889), .A1(n6894), .B0(n6887), .B1(n938), .C0(n6885),
.C1(Op_MX[14]), .Y(n6765) );
NOR2X2TS U4237 ( .A(mult_x_23_n651), .B(mult_x_23_n655), .Y(n5167) );
AOI21X1TS U4238 ( .A0(n7436), .A1(n7435), .B0(n7258), .Y(n7441) );
XOR2X4TS U4239 ( .A(n5011), .B(n7051), .Y(n6941) );
NOR2X2TS U4240 ( .A(n4885), .B(n4868), .Y(n4870) );
BUFX16TS U4241 ( .A(n2018), .Y(n2808) );
CMPR42X2TS U4242 ( .A(mult_x_24_n1407), .B(mult_x_24_n737), .C(
mult_x_24_n738), .D(mult_x_24_n732), .ICI(mult_x_24_n734), .S(
mult_x_24_n729), .ICO(mult_x_24_n727), .CO(mult_x_24_n728) );
XNOR2X4TS U4243 ( .A(n1401), .B(n1396), .Y(n1400) );
ADDFHX2TS U4244 ( .A(n2405), .B(n2404), .CI(n2403), .CO(n2419), .S(n2430) );
AND3X4TS U4245 ( .A(n5036), .B(n5035), .C(n5034), .Y(n6615) );
OAI21X2TS U4246 ( .A0(n7026), .A1(n6841), .B0(n5037), .Y(n5038) );
NOR2BX2TS U4247 ( .AN(n1058), .B(n1057), .Y(n6686) );
ADDFHX2TS U4248 ( .A(n2556), .B(n2555), .CI(n2554), .CO(n2675), .S(n2681) );
NAND2X4TS U4249 ( .A(n1398), .B(n1397), .Y(n1399) );
CMPR42X2TS U4250 ( .A(mult_x_24_n1408), .B(mult_x_24_n744), .C(
mult_x_24_n739), .D(mult_x_24_n745), .ICI(mult_x_24_n741), .S(
mult_x_24_n736), .ICO(mult_x_24_n734), .CO(mult_x_24_n735) );
ADDFHX2TS U4251 ( .A(n2599), .B(n2598), .CI(n2597), .CO(n2644), .S(n2595) );
NAND2X4TS U4252 ( .A(Op_MY[28]), .B(Op_MY[1]), .Y(n1374) );
ADDFHX2TS U4253 ( .A(n2612), .B(n2611), .CI(n2610), .CO(n2663), .S(n2683) );
ADDFHX2TS U4254 ( .A(n2609), .B(n2608), .CI(n2607), .CO(n2642), .S(n2612) );
XNOR2X2TS U4255 ( .A(n3364), .B(n3230), .Y(n2806) );
OAI21X2TS U4256 ( .A0(n6926), .A1(n6966), .B0(n6797), .Y(n6798) );
XNOR2X2TS U4257 ( .A(n912), .B(n3346), .Y(n3347) );
OAI21X2TS U4258 ( .A0(n6778), .A1(n6966), .B0(n6777), .Y(n6779) );
NOR2X4TS U4259 ( .A(n7292), .B(n3923), .Y(n3925) );
OAI21X2TS U4260 ( .A0(n5437), .A1(n5684), .B0(n3721), .Y(n3722) );
XNOR2X2TS U4261 ( .A(n3176), .B(n3230), .Y(n2874) );
ADDFHX2TS U4262 ( .A(n2550), .B(n2549), .CI(n2548), .CO(n2677), .S(n2670) );
NAND2X4TS U4263 ( .A(mult_x_23_n698), .B(mult_x_23_n707), .Y(n4858) );
OAI22X2TS U4264 ( .A0(n728), .A1(n2976), .B0(n1802), .B1(n3006), .Y(n1815)
);
CMPR42X2TS U4265 ( .A(mult_x_23_n691), .B(mult_x_23_n1322), .C(
mult_x_23_n686), .D(mult_x_23_n692), .ICI(mult_x_23_n688), .S(
mult_x_23_n683), .ICO(mult_x_23_n681), .CO(mult_x_23_n682) );
OAI22X2TS U4266 ( .A0(n1624), .A1(n3301), .B0(n1383), .B1(n1751), .Y(n1626)
);
ADDFHX2TS U4267 ( .A(n2052), .B(n2051), .CI(n2050), .CO(n2138), .S(n2149) );
OAI22X2TS U4268 ( .A0(n1384), .A1(n3301), .B0(n1751), .B1(n3367), .Y(n1422)
);
XNOR2X2TS U4269 ( .A(n859), .B(n3227), .Y(n1383) );
NAND2X4TS U4270 ( .A(n6334), .B(n6415), .Y(n6323) );
OAI22X2TS U4271 ( .A0(n1993), .A1(n3031), .B0(n1883), .B1(n3415), .Y(n1995)
);
CMPR42X2TS U4272 ( .A(mult_x_23_n727), .B(mult_x_23_n723), .C(mult_x_23_n728), .D(mult_x_23_n721), .ICI(mult_x_23_n724), .S(mult_x_23_n718), .ICO(
mult_x_23_n716), .CO(mult_x_23_n717) );
OAI21X2TS U4273 ( .A0(Op_MX[22]), .A1(Op_MX[49]), .B0(Op_MX[21]), .Y(n2073)
);
NAND2X4TS U4274 ( .A(n6261), .B(n6272), .Y(n6244) );
NAND2X4TS U4275 ( .A(n6354), .B(n6363), .Y(n6423) );
NAND2X4TS U4276 ( .A(n6301), .B(n6295), .Y(n6390) );
NAND2X2TS U4277 ( .A(n848), .B(n852), .Y(n3658) );
XNOR2X4TS U4278 ( .A(Op_MX[43]), .B(Op_MX[42]), .Y(n1795) );
CLKXOR2X4TS U4279 ( .A(Op_MX[50]), .B(Op_MX[51]), .Y(n2205) );
XOR2X4TS U4280 ( .A(n7492), .B(Op_MX[34]), .Y(n3720) );
XNOR2X4TS U4281 ( .A(Op_MX[31]), .B(Op_MX[30]), .Y(n3637) );
XOR2X4TS U4282 ( .A(Op_MX[41]), .B(Op_MX[40]), .Y(n4655) );
XOR2X4TS U4283 ( .A(Op_MX[47]), .B(Op_MX[46]), .Y(n3626) );
CLKBUFX2TS U4284 ( .A(n1616), .Y(n2214) );
OR2X1TS U4285 ( .A(n6897), .B(n6243), .Y(n975) );
XNOR2X4TS U4286 ( .A(n4999), .B(n3726), .Y(n979) );
AOI22X1TS U4287 ( .A0(n6921), .A1(n5041), .B0(n6923), .B1(n6822), .Y(n981)
);
OR2X1TS U4288 ( .A(n4230), .B(Sgf_operation_ODD1_Q_right[28]), .Y(n986) );
OR2X1TS U4289 ( .A(n4256), .B(Sgf_operation_ODD1_Q_right[33]), .Y(n990) );
AOI22X1TS U4290 ( .A0(n6440), .A1(n5041), .B0(n6736), .B1(n6243), .Y(n994)
);
NAND2X1TS U4291 ( .A(n1112), .B(n825), .Y(n995) );
NAND2X1TS U4292 ( .A(n3717), .B(n824), .Y(n997) );
XNOR2X2TS U4293 ( .A(n1082), .B(n8391), .Y(n998) );
CLKBUFX2TS U4294 ( .A(Op_MY[0]), .Y(n8386) );
CLKXOR2X4TS U4295 ( .A(n3603), .B(n3602), .Y(n1001) );
AND2X2TS U4296 ( .A(n4832), .B(n4831), .Y(n1004) );
INVX2TS U4297 ( .A(Op_MX[0]), .Y(n1038) );
CLKBUFX2TS U4298 ( .A(Op_MX[2]), .Y(n8402) );
BUFX6TS U4299 ( .A(Op_MX[6]), .Y(n8414) );
CLKBUFX2TS U4300 ( .A(Op_MY[26]), .Y(n8393) );
INVX2TS U4301 ( .A(n1018), .Y(n6220) );
AND2X2TS U4302 ( .A(n2284), .B(n8393), .Y(n1030) );
OR2X4TS U4303 ( .A(FSM_selector_B[1]), .B(n8450), .Y(n1037) );
OAI21X2TS U4304 ( .A0(n2241), .A1(n2240), .B0(n2239), .Y(n2242) );
INVX2TS U4305 ( .A(n3813), .Y(n4730) );
NOR2X2TS U4306 ( .A(n6421), .B(n6425), .Y(n6428) );
NOR2X2TS U4307 ( .A(n3848), .B(n3846), .Y(n1256) );
NAND2X1TS U4308 ( .A(n4433), .B(n4438), .Y(n4441) );
INVX2TS U4309 ( .A(n2577), .Y(n2825) );
NOR2X1TS U4310 ( .A(n2581), .B(n3583), .Y(n2631) );
NAND2X1TS U4311 ( .A(n6268), .B(n6273), .Y(n6259) );
XNOR2X1TS U4312 ( .A(n3330), .B(n3230), .Y(n3288) );
INVX2TS U4313 ( .A(Sgf_operation_Result[2]), .Y(n4009) );
INVX2TS U4314 ( .A(Sgf_operation_Result[9]), .Y(n4041) );
INVX4TS U4315 ( .A(n3005), .Y(n3348) );
XNOR2X1TS U4316 ( .A(n3176), .B(n3363), .Y(n3423) );
OAI22X1TS U4317 ( .A0(n2475), .A1(n3031), .B0(n2312), .B1(n3415), .Y(n2516)
);
BUFX3TS U4318 ( .A(n2563), .Y(n3290) );
NAND2X1TS U4319 ( .A(n6250), .B(n6249), .Y(n6251) );
BUFX4TS U4320 ( .A(n6982), .Y(n6581) );
AOI22X1TS U4321 ( .A0(n5922), .A1(n903), .B0(n4672), .B1(n4966), .Y(n4673)
);
XNOR2X1TS U4322 ( .A(n4007), .B(Sgf_operation_ODD1_Q_middle[1]), .Y(n4006)
);
OAI22X1TS U4323 ( .A0(n3362), .A1(n3361), .B0(n3377), .B1(n3360), .Y(n3436)
);
BUFX3TS U4324 ( .A(n2694), .Y(n3411) );
OAI22X1TS U4325 ( .A0(n3168), .A1(n930), .B0(n3218), .B1(n3360), .Y(n3253)
);
OAI22X1TS U4326 ( .A0(n2031), .A1(n3301), .B0(n1908), .B1(n2839), .Y(n2052)
);
BUFX4TS U4327 ( .A(n6639), .Y(n6885) );
NAND2X1TS U4328 ( .A(n5603), .B(n5602), .Y(n5604) );
INVX2TS U4329 ( .A(n4266), .Y(n4268) );
INVX2TS U4330 ( .A(n4324), .Y(n4371) );
INVX2TS U4331 ( .A(n4187), .Y(n4184) );
INVX2TS U4332 ( .A(n4433), .Y(n4125) );
OAI21X2TS U4333 ( .A0(n4581), .A1(n4592), .B0(n4582), .Y(n4481) );
INVX2TS U4334 ( .A(n4519), .Y(n4506) );
OAI22X1TS U4335 ( .A0(n1426), .A1(n3178), .B0(n1430), .B1(n3222), .Y(n1469)
);
BUFX3TS U4336 ( .A(n4805), .Y(n7074) );
ADDHX1TS U4337 ( .A(n7494), .B(n4714), .CO(n5073), .S(n5137) );
OAI21X2TS U4338 ( .A0(n6999), .A1(n764), .B0(n5010), .Y(n5011) );
OAI21X2TS U4339 ( .A0(n5792), .A1(n5886), .B0(n5516), .Y(n5517) );
NAND2X1TS U4340 ( .A(n3659), .B(n3658), .Y(n3660) );
INVX2TS U4341 ( .A(n7418), .Y(n7421) );
INVX2TS U4342 ( .A(n4346), .Y(n4343) );
AOI21X1TS U4343 ( .A0(n4113), .A1(n4112), .B0(n4111), .Y(n4119) );
XOR2X1TS U4344 ( .A(n3798), .B(n5663), .Y(n5933) );
XNOR2X2TS U4345 ( .A(n4193), .B(n4192), .Y(n4404) );
XOR2X1TS U4346 ( .A(n4126), .B(n4110), .Y(n4419) );
XOR3X1TS U4347 ( .A(n3813), .B(n3586), .C(n3585), .Y(n3587) );
ADDFX2TS U4348 ( .A(n7055), .B(n7054), .CI(n7053), .CO(mult_x_24_n1032), .S(
mult_x_24_n1033) );
XOR2X1TS U4349 ( .A(n1079), .B(n6820), .Y(n1137) );
OAI21X1TS U4350 ( .A0(FSM_selector_B[0]), .A1(n5254), .B0(n1037), .Y(n5255)
);
NAND2X1TS U4351 ( .A(n4285), .B(Sgf_operation_ODD1_Q_right[34]), .Y(n8230)
);
INVX2TS U4352 ( .A(n8283), .Y(n8285) );
INVX2TS U4353 ( .A(n8334), .Y(n8336) );
INVX2TS U4354 ( .A(n8162), .Y(n8164) );
INVX2TS U4355 ( .A(n8033), .Y(n8035) );
NAND2X1TS U4356 ( .A(n4613), .B(Sgf_operation_ODD1_Q_left[18]), .Y(n7905) );
INVX2TS U4357 ( .A(n7835), .Y(n7837) );
INVX2TS U4358 ( .A(n7780), .Y(n7782) );
OAI21XLTS U4359 ( .A0(n8139), .A1(n8149), .B0(n8150), .Y(n8144) );
INVX2TS U4360 ( .A(n7918), .Y(n7933) );
NOR2X2TS U4361 ( .A(n7674), .B(n7673), .Y(n4648) );
XOR2X1TS U4362 ( .A(n7674), .B(n7673), .Y(n7675) );
INVX2TS U4363 ( .A(n1032), .Y(n7491) );
NAND2X1TS U4364 ( .A(n7223), .B(n7222), .Y(n7224) );
AOI21X1TS U4365 ( .A0(n6163), .A1(n6148), .B0(n6147), .Y(n6152) );
OAI21XLTS U4366 ( .A0(n5383), .A1(n5380), .B0(n5381), .Y(n5379) );
NAND2BX2TS U4367 ( .AN(n999), .B(n1048), .Y(n1080) );
NAND2X1TS U4368 ( .A(n884), .B(n825), .Y(n1039) );
INVX2TS U4369 ( .A(n1073), .Y(n1041) );
AOI21X4TS U4370 ( .A0(n1000), .A1(n1041), .B0(n1040), .Y(n1124) );
NOR2X4TS U4371 ( .A(n6584), .B(n6863), .Y(n1062) );
INVX2TS U4372 ( .A(n1062), .Y(n1094) );
INVX2TS U4373 ( .A(n1093), .Y(n1042) );
AOI21X2TS U4374 ( .A0(n1096), .A1(n1094), .B0(n1042), .Y(n1045) );
INVX2TS U4375 ( .A(n1063), .Y(n1043) );
BUFX3TS U4376 ( .A(n1080), .Y(n6729) );
BUFX3TS U4377 ( .A(Op_MX[5]), .Y(n7046) );
NOR2BX4TS U4378 ( .AN(n999), .B(n1005), .Y(n1083) );
BUFX3TS U4379 ( .A(n1083), .Y(n6916) );
BUFX3TS U4380 ( .A(Op_MX[4]), .Y(n7044) );
BUFX3TS U4381 ( .A(n6584), .Y(n7042) );
AOI222X1TS U4382 ( .A0(n1047), .A1(n7046), .B0(n6916), .B1(n7044), .C0(n6893), .C1(n7042), .Y(n1049) );
OAI21X1TS U4383 ( .A0(n7050), .A1(n6729), .B0(n1049), .Y(n1050) );
INVX2TS U4384 ( .A(n1013), .Y(n6730) );
OR2X2TS U4385 ( .A(n905), .B(n825), .Y(n1051) );
NAND2X4TS U4386 ( .A(n1051), .B(n1073), .Y(n5043) );
XNOR2X4TS U4387 ( .A(n6934), .B(Op_MY[3]), .Y(n1058) );
INVX4TS U4388 ( .A(n1038), .Y(n5041) );
NOR2X4TS U4389 ( .A(n1059), .B(n1058), .Y(n1056) );
BUFX4TS U4390 ( .A(n1056), .Y(n6817) );
BUFX3TS U4391 ( .A(n6243), .Y(n6822) );
INVX2TS U4392 ( .A(n730), .Y(n6695) );
NAND2X1TS U4393 ( .A(n1056), .B(n825), .Y(n1052) );
NAND2X2TS U4394 ( .A(n975), .B(n1074), .Y(n1054) );
INVX6TS U4395 ( .A(n1055), .Y(n7026) );
BUFX3TS U4396 ( .A(Op_MX[2]), .Y(n6884) );
BUFX3TS U4397 ( .A(n6243), .Y(n7020) );
AOI222X2TS U4398 ( .A0(n6683), .A1(n6884), .B0(n886), .B1(n7020), .C0(n822),
.C1(n7018), .Y(n1060) );
NOR2X2TS U4399 ( .A(n1104), .B(n1103), .Y(n6199) );
INVX2TS U4400 ( .A(n1144), .Y(n1065) );
NAND2X1TS U4401 ( .A(n1065), .B(n1143), .Y(n1066) );
XOR2X2TS U4402 ( .A(n1145), .B(n1066), .Y(n1067) );
BUFX3TS U4403 ( .A(n8414), .Y(n7031) );
BUFX3TS U4404 ( .A(n1083), .Y(n6727) );
BUFX3TS U4405 ( .A(Op_MX[5]), .Y(n6859) );
BUFX3TS U4406 ( .A(n6863), .Y(n6888) );
AOI222X1TS U4407 ( .A0(n1047), .A1(n7031), .B0(n6727), .B1(n6859), .C0(n6893), .C1(n6888), .Y(n1068) );
OAI21X1TS U4408 ( .A0(n6865), .A1(n6729), .B0(n1068), .Y(n1069) );
XOR2X1TS U4409 ( .A(n1069), .B(n8445), .Y(n1106) );
XNOR2X4TS U4410 ( .A(Op_MY[6]), .B(Op_MY[5]), .Y(n1114) );
XOR2X4TS U4411 ( .A(Op_MY[7]), .B(n7040), .Y(n1115) );
NOR2X4TS U4412 ( .A(n1115), .B(n1114), .Y(n1112) );
AND2X4TS U4413 ( .A(n1072), .B(n1071), .Y(n1138) );
NAND2X1TS U4414 ( .A(n1074), .B(n1073), .Y(n1077) );
XOR2X4TS U4415 ( .A(n1077), .B(n1076), .Y(n6824) );
BUFX3TS U4416 ( .A(n8402), .Y(n7022) );
OAI21X1TS U4417 ( .A0(n6824), .A1(n6681), .B0(n1078), .Y(n1079) );
NOR2X2TS U4418 ( .A(n1106), .B(n1105), .Y(n6194) );
NOR2X2TS U4419 ( .A(n6199), .B(n6194), .Y(n1108) );
BUFX3TS U4420 ( .A(n1080), .Y(n6932) );
AOI222X1TS U4421 ( .A0(n885), .A1(n6884), .B0(n6916), .B1(n7020), .C0(n6893),
.C1(n7018), .Y(n1081) );
OAI21X1TS U4422 ( .A0(n7026), .A1(n6932), .B0(n1081), .Y(n1082) );
AOI22X1TS U4423 ( .A0(n884), .A1(n6243), .B0(n6727), .B1(n7018), .Y(n1084)
);
OAI21X1TS U4424 ( .A0(n5043), .A1(n6932), .B0(n1084), .Y(n1085) );
XOR2X1TS U4425 ( .A(n1085), .B(n6934), .Y(n6213) );
INVX2TS U4426 ( .A(Sgf_operation_ODD1_right_N0), .Y(n1086) );
AND2X2TS U4427 ( .A(n1086), .B(n8445), .Y(n6214) );
NOR2X4TS U4428 ( .A(n998), .B(n6212), .Y(n6210) );
AOI222X1TS U4429 ( .A0(n884), .A1(n7042), .B0(n6916), .B1(n7022), .C0(n6893),
.C1(n6822), .Y(n1087) );
OAI21X1TS U4430 ( .A0(n6824), .A1(n6932), .B0(n1087), .Y(n1088) );
XOR2X1TS U4431 ( .A(n1088), .B(n6730), .Y(n1091) );
NAND2X1TS U4432 ( .A(n1091), .B(n1090), .Y(n6209) );
INVX2TS U4433 ( .A(n6209), .Y(n1092) );
AOI21X4TS U4434 ( .A0(n6210), .A1(n1014), .B0(n1092), .Y(n6208) );
BUFX3TS U4435 ( .A(Op_MX[3]), .Y(n6886) );
AOI222X1TS U4436 ( .A0(n884), .A1(n6888), .B0(n6916), .B1(n6886), .C0(n6893),
.C1(n6884), .Y(n1097) );
OAI21X1TS U4437 ( .A0(n6900), .A1(n6729), .B0(n1097), .Y(n1098) );
XOR2X1TS U4438 ( .A(n1098), .B(n8445), .Y(n1102) );
NOR2X1TS U4439 ( .A(n1102), .B(n1101), .Y(n6204) );
NAND2X1TS U4440 ( .A(n1102), .B(n1101), .Y(n6205) );
OAI21X4TS U4441 ( .A0(n6208), .A1(n6204), .B0(n6205), .Y(n6193) );
NAND2X1TS U4442 ( .A(n1104), .B(n1103), .Y(n6200) );
NAND2X1TS U4443 ( .A(n1106), .B(n1105), .Y(n6195) );
AOI21X4TS U4444 ( .A0(n1108), .A1(n6193), .B0(n1107), .Y(n6183) );
XNOR2X2TS U4445 ( .A(Op_MY[6]), .B(Op_MY[7]), .Y(n1113) );
AOI22X1TS U4446 ( .A0(n6620), .A1(n5041), .B0(n6750), .B1(n6822), .Y(n1109)
);
OAI21X1TS U4447 ( .A0(n5043), .A1(n6992), .B0(n1109), .Y(n1110) );
ADDHX1TS U4448 ( .A(n7040), .B(n1111), .CO(n1133), .S(n1139) );
AND3X4TS U4449 ( .A(n1115), .B(n1114), .C(n1113), .Y(n6639) );
AOI222X1TS U4450 ( .A0(n6889), .A1(n6884), .B0(n6887), .B1(n7020), .C0(n6885), .C1(n7018), .Y(n1116) );
OAI21X1TS U4451 ( .A0(n7026), .A1(n6992), .B0(n1116), .Y(n1117) );
XOR2X1TS U4452 ( .A(n1117), .B(n6891), .Y(n4727) );
AOI21X4TS U4453 ( .A0(n1121), .A1(n1120), .B0(n1119), .Y(n1122) );
OAI21X4TS U4454 ( .A0(n1124), .A1(n1123), .B0(n1122), .Y(n1214) );
INVX2TS U4455 ( .A(n6231), .Y(n1125) );
XOR2X4TS U4456 ( .A(n6461), .B(n1126), .Y(n1127) );
BUFX3TS U4457 ( .A(Op_MX[8]), .Y(n8413) );
BUFX3TS U4458 ( .A(n8413), .Y(n7035) );
CLKBUFX2TS U4459 ( .A(Op_MX[7]), .Y(n6780) );
BUFX3TS U4460 ( .A(n6780), .Y(n7033) );
BUFX6TS U4461 ( .A(n6893), .Y(n6914) );
AOI222X1TS U4462 ( .A0(n1047), .A1(n7035), .B0(n6727), .B1(n7033), .C0(n6914), .C1(n7031), .Y(n1128) );
OAI21X1TS U4463 ( .A0(n7039), .A1(n6729), .B0(n1128), .Y(n1129) );
XOR2X1TS U4464 ( .A(n1129), .B(n6934), .Y(n1162) );
AOI222X1TS U4465 ( .A0(n6905), .A1(n7046), .B0(n6903), .B1(n7044), .C0(n823),
.C1(n7042), .Y(n1131) );
OAI21X1TS U4466 ( .A0(n7050), .A1(n6907), .B0(n1131), .Y(n1132) );
XOR2X1TS U4467 ( .A(n1132), .B(n940), .Y(n1161) );
OAI21X1TS U4468 ( .A0(n6900), .A1(n6907), .B0(n1135), .Y(n1136) );
XOR2X1TS U4469 ( .A(n1136), .B(n6695), .Y(n1141) );
ADDFHX2TS U4470 ( .A(n1139), .B(n1138), .CI(n1137), .CO(n1140), .S(n1105) );
OR2X4TS U4471 ( .A(n1157), .B(n1156), .Y(n6186) );
INVX2TS U4472 ( .A(n1146), .Y(n1148) );
BUFX3TS U4473 ( .A(n6780), .Y(n6909) );
CLKBUFX2TS U4474 ( .A(n8414), .Y(n6875) );
BUFX3TS U4475 ( .A(n6875), .Y(n6868) );
AOI222X1TS U4476 ( .A0(n1047), .A1(n6909), .B0(n6727), .B1(n6868), .C0(n6893), .C1(n7046), .Y(n1152) );
OAI21X1TS U4477 ( .A0(n6879), .A1(n6729), .B0(n1152), .Y(n1153) );
NAND2X2TS U4478 ( .A(n6186), .B(n6190), .Y(n1160) );
NAND2X2TS U4479 ( .A(n1157), .B(n1156), .Y(n6185) );
INVX2TS U4480 ( .A(n6185), .Y(n1158) );
AOI21X4TS U4481 ( .A0(n6186), .A1(n6184), .B0(n1158), .Y(n1159) );
OAI21X4TS U4482 ( .A0(n6183), .A1(n1160), .B0(n1159), .Y(n6181) );
OR2X2TS U4483 ( .A(mult_x_24_n1062), .B(n1164), .Y(n6180) );
NAND2X2TS U4484 ( .A(mult_x_24_n1062), .B(n1164), .Y(n6179) );
INVX2TS U4485 ( .A(n6179), .Y(n1165) );
AOI21X4TS U4486 ( .A0(n6181), .A1(n6180), .B0(n1165), .Y(n6170) );
OR2X4TS U4487 ( .A(mult_x_24_n1052), .B(mult_x_24_n1056), .Y(n6173) );
NAND2X2TS U4488 ( .A(n6173), .B(n779), .Y(n1168) );
NAND2X2TS U4489 ( .A(mult_x_24_n1052), .B(mult_x_24_n1056), .Y(n6172) );
INVX2TS U4490 ( .A(n6172), .Y(n1166) );
OAI21X4TS U4491 ( .A0(n6170), .A1(n1168), .B0(n1167), .Y(n6164) );
NOR2X4TS U4492 ( .A(mult_x_24_n1038), .B(mult_x_24_n1044), .Y(n6165) );
NOR2X4TS U4493 ( .A(mult_x_24_n1045), .B(mult_x_24_n1051), .Y(n6953) );
NOR2X2TS U4494 ( .A(n6165), .B(n6953), .Y(n1170) );
NAND2X2TS U4495 ( .A(mult_x_24_n1045), .B(mult_x_24_n1051), .Y(n6954) );
NAND2X2TS U4496 ( .A(mult_x_24_n1038), .B(mult_x_24_n1044), .Y(n6166) );
OAI21X2TS U4497 ( .A0(n6165), .A1(n6954), .B0(n6166), .Y(n1169) );
AOI21X4TS U4498 ( .A0(n6164), .A1(n1170), .B0(n1169), .Y(n6146) );
NOR2X2TS U4499 ( .A(mult_x_24_n1031), .B(mult_x_24_n1037), .Y(n6153) );
NAND2X2TS U4500 ( .A(n6148), .B(n6150), .Y(n1173) );
NAND2X2TS U4501 ( .A(mult_x_24_n1031), .B(mult_x_24_n1037), .Y(n6160) );
NAND2X2TS U4502 ( .A(mult_x_24_n1023), .B(mult_x_24_n1030), .Y(n6156) );
OAI21X4TS U4503 ( .A0(n6155), .A1(n6160), .B0(n6156), .Y(n6147) );
NAND2X2TS U4504 ( .A(mult_x_24_n997), .B(mult_x_24_n1006), .Y(n6142) );
NAND2X4TS U4505 ( .A(mult_x_24_n987), .B(mult_x_24_n996), .Y(n6136) );
NAND2X2TS U4506 ( .A(mult_x_24_n977), .B(mult_x_24_n986), .Y(n6133) );
INVX2TS U4507 ( .A(n6133), .Y(n1175) );
OR2X4TS U4508 ( .A(mult_x_24_n944), .B(mult_x_24_n954), .Y(n6119) );
OR2X4TS U4509 ( .A(mult_x_24_n931), .B(mult_x_24_n943), .Y(n6113) );
NAND2X2TS U4510 ( .A(mult_x_24_n955), .B(mult_x_24_n965), .Y(n6123) );
INVX4TS U4511 ( .A(n6118), .Y(n6108) );
NAND2X2TS U4512 ( .A(mult_x_24_n931), .B(mult_x_24_n943), .Y(n6112) );
NOR2X6TS U4513 ( .A(mult_x_24_n880), .B(mult_x_24_n869), .Y(n7101) );
NOR2X4TS U4514 ( .A(n7101), .B(n7097), .Y(n1182) );
OR2X4TS U4515 ( .A(mult_x_24_n905), .B(mult_x_24_n917), .Y(n7110) );
OR2X4TS U4516 ( .A(mult_x_24_n930), .B(mult_x_24_n918), .Y(n7107) );
INVX4TS U4517 ( .A(n6103), .Y(n7106) );
NAND2X2TS U4518 ( .A(mult_x_24_n905), .B(mult_x_24_n917), .Y(n7109) );
INVX2TS U4519 ( .A(n7109), .Y(n1180) );
AOI21X4TS U4520 ( .A0(n7110), .A1(n7106), .B0(n1180), .Y(n6095) );
NAND2X2TS U4521 ( .A(mult_x_24_n893), .B(mult_x_24_n904), .Y(n6099) );
OAI21X4TS U4522 ( .A0(n6095), .A1(n6098), .B0(n6099), .Y(n6976) );
NAND2X2TS U4523 ( .A(mult_x_24_n881), .B(mult_x_24_n892), .Y(n7096) );
NAND2X2TS U4524 ( .A(mult_x_24_n869), .B(mult_x_24_n880), .Y(n7102) );
AOI21X4TS U4525 ( .A0(n6976), .A1(n1182), .B0(n1181), .Y(n1183) );
OAI21X4TS U4526 ( .A0(n6093), .A1(n1184), .B0(n1183), .Y(n4834) );
NOR2X4TS U4527 ( .A(mult_x_24_n777), .B(mult_x_24_n769), .Y(n4887) );
INVX2TS U4528 ( .A(n4887), .Y(n4837) );
NAND2X4TS U4529 ( .A(n4837), .B(n784), .Y(n4877) );
NOR2X4TS U4530 ( .A(mult_x_24_n797), .B(mult_x_24_n788), .Y(n4840) );
INVX2TS U4531 ( .A(n4840), .Y(n5229) );
NOR2X4TS U4532 ( .A(mult_x_24_n857), .B(mult_x_24_n868), .Y(n6088) );
NOR2X4TS U4533 ( .A(n6088), .B(n5232), .Y(n5237) );
NOR2X4TS U4534 ( .A(mult_x_24_n833), .B(mult_x_24_n844), .Y(n5217) );
NOR2X4TS U4535 ( .A(mult_x_24_n821), .B(mult_x_24_n832), .Y(n5244) );
NAND2X4TS U4536 ( .A(n5237), .B(n1186), .Y(n5250) );
NOR2X4TS U4537 ( .A(n1200), .B(n5250), .Y(n1202) );
NAND2X4TS U4538 ( .A(mult_x_24_n857), .B(mult_x_24_n868), .Y(n6089) );
NAND2X2TS U4539 ( .A(mult_x_24_n845), .B(mult_x_24_n856), .Y(n5233) );
OAI21X4TS U4540 ( .A0(n5232), .A1(n6089), .B0(n5233), .Y(n5241) );
NAND2X2TS U4541 ( .A(mult_x_24_n833), .B(mult_x_24_n844), .Y(n5238) );
NAND2X2TS U4542 ( .A(mult_x_24_n821), .B(mult_x_24_n832), .Y(n5245) );
OAI21X2TS U4543 ( .A0(n5238), .A1(n5244), .B0(n5245), .Y(n1185) );
AOI21X4TS U4544 ( .A0(n5241), .A1(n1186), .B0(n1185), .Y(n5249) );
NAND2X2TS U4545 ( .A(mult_x_24_n820), .B(mult_x_24_n809), .Y(n5251) );
INVX2TS U4546 ( .A(n5251), .Y(n4849) );
INVX2TS U4547 ( .A(n4852), .Y(n1187) );
AOI21X4TS U4548 ( .A0(n4849), .A1(n768), .B0(n1187), .Y(n5222) );
NAND2X2TS U4549 ( .A(mult_x_24_n788), .B(mult_x_24_n797), .Y(n5228) );
INVX2TS U4550 ( .A(n5228), .Y(n1189) );
INVX2TS U4551 ( .A(n4845), .Y(n1188) );
OAI21X4TS U4552 ( .A0(n5222), .A1(n1191), .B0(n1190), .Y(n4864) );
NAND2X2TS U4553 ( .A(mult_x_24_n769), .B(mult_x_24_n777), .Y(n4886) );
INVX2TS U4554 ( .A(n4886), .Y(n1193) );
NAND2X2TS U4555 ( .A(mult_x_24_n760), .B(mult_x_24_n768), .Y(n4894) );
INVX2TS U4556 ( .A(n4894), .Y(n1192) );
AOI21X4TS U4557 ( .A0(n784), .A1(n1193), .B0(n1192), .Y(n4876) );
INVX2TS U4558 ( .A(n4882), .Y(n4865) );
INVX2TS U4559 ( .A(n4873), .Y(n1194) );
AOI21X2TS U4560 ( .A0(n1027), .A1(n4865), .B0(n1194), .Y(n1195) );
OAI21X2TS U4561 ( .A0(n4876), .A1(n1196), .B0(n1195), .Y(n1197) );
AOI21X4TS U4562 ( .A0(n4864), .A1(n1198), .B0(n1197), .Y(n1199) );
OAI21X4TS U4563 ( .A0(n1200), .A1(n5249), .B0(n1199), .Y(n1201) );
AOI21X4TS U4564 ( .A0(n4834), .A1(n1202), .B0(n1201), .Y(n1203) );
NOR2X2TS U4565 ( .A(mult_x_24_n736), .B(mult_x_24_n742), .Y(n1266) );
NAND2X2TS U4566 ( .A(mult_x_24_n736), .B(mult_x_24_n742), .Y(n6733) );
OAI21X2TS U4567 ( .A0(n816), .A1(n1266), .B0(n6733), .Y(n1204) );
NAND2X2TS U4568 ( .A(mult_x_24_n729), .B(mult_x_24_n735), .Y(n1267) );
XOR2X4TS U4569 ( .A(n1204), .B(n982), .Y(Sgf_operation_ODD1_right_N43) );
BUFX20TS U4570 ( .A(n8412), .Y(n6785) );
NOR2X8TS U4571 ( .A(n6349), .B(n6353), .Y(n6420) );
AOI21X4TS U4572 ( .A0(n6458), .A1(n1207), .B0(n1206), .Y(n6361) );
NAND2X2TS U4573 ( .A(n6785), .B(n6945), .Y(n6433) );
NOR2X6TS U4574 ( .A(n6333), .B(n6414), .Y(n6322) );
NAND2X1TS U4575 ( .A(n6315), .B(n6326), .Y(n1215) );
AOI21X4TS U4576 ( .A0(n1216), .A1(n6323), .B0(n1215), .Y(n3815) );
INVX2TS U4577 ( .A(n3812), .Y(n6297) );
XNOR2X4TS U4578 ( .A(n1218), .B(n1217), .Y(n1219) );
CLKBUFX2TS U4579 ( .A(Op_MX[19]), .Y(n6749) );
BUFX3TS U4580 ( .A(n6749), .Y(n6830) );
OAI21X1TS U4581 ( .A0(n6832), .A1(n6819), .B0(n1220), .Y(n1221) );
INVX2TS U4582 ( .A(n730), .Y(n6820) );
NOR2X6TS U4583 ( .A(n3655), .B(n3657), .Y(n3608) );
NAND2X4TS U4584 ( .A(n3608), .B(n1225), .Y(n1227) );
INVX2TS U4585 ( .A(n3647), .Y(n1223) );
AOI21X4TS U4586 ( .A0(n1002), .A1(n1223), .B0(n1222), .Y(n3606) );
NAND2X2TS U4587 ( .A(n5892), .B(n5901), .Y(n3707) );
NAND2X4TS U4588 ( .A(n755), .B(n5892), .Y(n3703) );
NAND2X1TS U4589 ( .A(n3707), .B(n3703), .Y(n1224) );
AOI21X4TS U4590 ( .A0(n3607), .A1(n1225), .B0(n1224), .Y(n1226) );
OAI21X4TS U4591 ( .A0(n1227), .A1(n3606), .B0(n1226), .Y(n4974) );
BUFX16TS U4592 ( .A(Op_MY[41]), .Y(n6045) );
NOR2X4TS U4593 ( .A(n4991), .B(n1233), .Y(n1235) );
AOI21X4TS U4594 ( .A0(n4972), .A1(n1229), .B0(n1228), .Y(n4993) );
OAI21X4TS U4595 ( .A0(n4993), .A1(n1233), .B0(n1232), .Y(n1234) );
AOI21X4TS U4596 ( .A0(n4974), .A1(n1235), .B0(n1234), .Y(n1248) );
INVX2TS U4597 ( .A(n1250), .Y(n1241) );
NAND2X1TS U4598 ( .A(n1241), .B(n1251), .Y(n1236) );
XNOR2X4TS U4599 ( .A(n1242), .B(n1236), .Y(n1237) );
BUFX3TS U4600 ( .A(n3853), .Y(n6061) );
NOR2BX4TS U4601 ( .AN(n5904), .B(Op_MX[51]), .Y(n3880) );
OAI21X2TS U4602 ( .A0(n6048), .A1(n6061), .B0(n1239), .Y(mult_x_23_n1246) );
INVX2TS U4603 ( .A(n1251), .Y(n1240) );
INVX2TS U4604 ( .A(n1249), .Y(n1243) );
NAND2X1TS U4605 ( .A(n1243), .B(n1252), .Y(n1244) );
XNOR2X4TS U4606 ( .A(n1245), .B(n1244), .Y(n6026) );
AOI21X1TS U4607 ( .A0(n5936), .A1(n6023), .B0(n1246), .Y(n1247) );
INVX2TS U4608 ( .A(mult_x_23_n666), .Y(n1264) );
NOR2X2TS U4609 ( .A(n5939), .B(n5775), .Y(n3846) );
NOR2X4TS U4610 ( .A(n5455), .B(n5457), .Y(n3842) );
NAND2X4TS U4611 ( .A(n1256), .B(n3842), .Y(n1258) );
NOR2X4TS U4612 ( .A(n1258), .B(n5453), .Y(n3858) );
OR2X2TS U4613 ( .A(n5883), .B(n5771), .Y(n3870) );
NAND2X2TS U4614 ( .A(n3858), .B(n3870), .Y(n1260) );
NAND2X2TS U4615 ( .A(n829), .B(n5906), .Y(n5531) );
NAND2X1TS U4616 ( .A(n5536), .B(n5531), .Y(n1253) );
AOI21X4TS U4617 ( .A0(n5399), .A1(n1254), .B0(n1253), .Y(n5452) );
NAND2X1TS U4618 ( .A(n5771), .B(n5775), .Y(n3849) );
NAND2X1TS U4619 ( .A(n3849), .B(n5406), .Y(n1255) );
AOI21X4TS U4620 ( .A0(n3859), .A1(n3870), .B0(Op_MY[51]), .Y(n1259) );
OAI21X4TS U4621 ( .A0(n5454), .A1(n1260), .B0(n1259), .Y(n3865) );
XNOR2X4TS U4622 ( .A(Op_MX[41]), .B(Op_MX[42]), .Y(n4664) );
XOR2X4TS U4623 ( .A(Op_MX[44]), .B(Op_MX[43]), .Y(n4665) );
NAND2BX4TS U4624 ( .AN(n4664), .B(n4665), .Y(n4671) );
BUFX3TS U4625 ( .A(n4671), .Y(n5924) );
INVX4TS U4626 ( .A(n5560), .Y(n5835) );
INVX4TS U4627 ( .A(n5835), .Y(n5919) );
NOR2BX4TS U4628 ( .AN(n4664), .B(n1795), .Y(n4672) );
AOI21X1TS U4629 ( .A0(n5919), .A1(n5883), .B0(n6011), .Y(n1261) );
OAI21X1TS U4630 ( .A0(n5887), .A1(n5924), .B0(n1261), .Y(n1262) );
XOR2X1TS U4631 ( .A(n1262), .B(Op_MX[44]), .Y(n1263) );
INVX2TS U4632 ( .A(n1266), .Y(n6732) );
NAND2X4TS U4633 ( .A(n6732), .B(n785), .Y(n1290) );
INVX2TS U4634 ( .A(n1267), .Y(n1268) );
AOI21X4TS U4635 ( .A0(n1269), .A1(n785), .B0(n1268), .Y(n1304) );
OAI21X2TS U4636 ( .A0(n816), .A1(n1290), .B0(n1304), .Y(n1270) );
INVX4TS U4637 ( .A(n1275), .Y(n1289) );
XOR2X4TS U4638 ( .A(n1270), .B(n983), .Y(Sgf_operation_ODD1_right_N44) );
NAND2X1TS U4639 ( .A(n1276), .B(n1289), .Y(n1272) );
INVX2TS U4640 ( .A(n1277), .Y(n1300) );
AOI21X1TS U4641 ( .A0(n1280), .A1(n1289), .B0(n1300), .Y(n1271) );
OAI21X2TS U4642 ( .A0(n815), .A1(n1272), .B0(n1271), .Y(n1274) );
INVX2TS U4643 ( .A(n1288), .Y(n1273) );
XOR2X4TS U4644 ( .A(n1274), .B(n984), .Y(Sgf_operation_ODD1_right_N45) );
NOR2X2TS U4645 ( .A(n1275), .B(n1288), .Y(n1279) );
INVX2TS U4646 ( .A(n1286), .Y(n5017) );
NAND2X1TS U4647 ( .A(n5012), .B(n5017), .Y(n1283) );
OAI21X1TS U4648 ( .A0(n1277), .A1(n1288), .B0(n1297), .Y(n1278) );
INVX2TS U4649 ( .A(n5016), .Y(n1281) );
OAI21X2TS U4650 ( .A0(n815), .A1(n1283), .B0(n1282), .Y(n1285) );
NOR2X2TS U4651 ( .A(mult_x_24_n705), .B(mult_x_24_n702), .Y(n1292) );
INVX2TS U4652 ( .A(n1292), .Y(n1284) );
NAND2X1TS U4653 ( .A(mult_x_24_n705), .B(mult_x_24_n702), .Y(n1291) );
XOR2X4TS U4654 ( .A(n1285), .B(n985), .Y(Sgf_operation_ODD1_right_N48) );
NAND2X4TS U4655 ( .A(n1301), .B(n1289), .Y(n1303) );
NOR2X6TS U4656 ( .A(n1290), .B(n1303), .Y(n5112) );
NAND2X1TS U4657 ( .A(n5112), .B(n5023), .Y(n1306) );
INVX2TS U4658 ( .A(n5028), .Y(n1294) );
OAI21X4TS U4659 ( .A0(n1304), .A1(n1303), .B0(n1302), .Y(n5121) );
INVX2TS U4660 ( .A(n5022), .Y(n3806) );
AOI21X1TS U4661 ( .A0(n5121), .A1(n5023), .B0(n3806), .Y(n1305) );
OAI21X2TS U4662 ( .A0(n815), .A1(n1306), .B0(n1305), .Y(n1307) );
OR2X2TS U4663 ( .A(mult_x_24_n695), .B(mult_x_24_n697), .Y(n3807) );
NAND2X1TS U4664 ( .A(mult_x_24_n695), .B(mult_x_24_n697), .Y(n3804) );
XOR2X4TS U4665 ( .A(n1307), .B(n1024), .Y(Sgf_operation_ODD1_right_N50) );
NOR2X8TS U4666 ( .A(Op_MY[30]), .B(Op_MY[3]), .Y(n1346) );
OAI21X4TS U4667 ( .A0(n1346), .A1(n1363), .B0(n1348), .Y(n1308) );
AOI21X4TS U4668 ( .A0(n1345), .A1(n1309), .B0(n1308), .Y(n1332) );
OAI21X4TS U4669 ( .A0(n1389), .A1(n1385), .B0(n1390), .Y(n1330) );
AOI21X4TS U4670 ( .A0(n1388), .A1(n1325), .B0(n1330), .Y(n1409) );
NAND2X2TS U4671 ( .A(Op_MY[34]), .B(Op_MY[7]), .Y(n1326) );
NAND2X1TS U4672 ( .A(n1310), .B(n1326), .Y(n1311) );
XNOR2X4TS U4673 ( .A(n1312), .B(n1311), .Y(n1313) );
XNOR2X1TS U4674 ( .A(n860), .B(n1708), .Y(n1421) );
NOR2X2TS U4675 ( .A(Op_MX[3]), .B(Op_MX[30]), .Y(n1316) );
OAI21X2TS U4676 ( .A0(Op_MX[29]), .A1(Op_MX[2]), .B0(Op_MX[1]), .Y(n1317) );
NAND2X2TS U4677 ( .A(n1413), .B(n1418), .Y(n1319) );
INVX2TS U4678 ( .A(n3637), .Y(n1322) );
NOR2X1TS U4679 ( .A(n1322), .B(n1321), .Y(n1323) );
XOR2X1TS U4680 ( .A(n1323), .B(n1397), .Y(n1324) );
AOI21X4TS U4681 ( .A0(n1330), .A1(n1329), .B0(n1328), .Y(n1331) );
OAI21X4TS U4682 ( .A0(n1333), .A1(n1332), .B0(n1331), .Y(n1767) );
INVX12TS U4683 ( .A(n1767), .Y(n1675) );
INVX2TS U4684 ( .A(n1431), .Y(n1334) );
XOR2X4TS U4685 ( .A(n1675), .B(n1335), .Y(n2735) );
XNOR2X1TS U4686 ( .A(n856), .B(n1708), .Y(n1635) );
BUFX3TS U4687 ( .A(n1828), .Y(n2315) );
OAI22X1TS U4688 ( .A0(n1421), .A1(n2459), .B0(n1635), .B1(n2315), .Y(n1630)
);
INVX2TS U4689 ( .A(n1336), .Y(n1387) );
XNOR2X2TS U4690 ( .A(n1388), .B(n1337), .Y(n1787) );
XNOR2X4TS U4691 ( .A(Op_MX[9]), .B(Op_MX[36]), .Y(n1369) );
XOR2X4TS U4692 ( .A(n1370), .B(n1369), .Y(n1424) );
XNOR2X1TS U4693 ( .A(n907), .B(n1872), .Y(n1634) );
CLKXOR2X4TS U4694 ( .A(Op_MX[8]), .B(Op_MX[35]), .Y(n1353) );
NOR2X2TS U4695 ( .A(Op_MX[7]), .B(Op_MX[34]), .Y(n1340) );
XNOR2X4TS U4696 ( .A(n1353), .B(n1340), .Y(n1344) );
XNOR2X4TS U4697 ( .A(Op_MX[7]), .B(Op_MX[34]), .Y(n1402) );
NAND2X1TS U4698 ( .A(Op_MX[6]), .B(Op_MX[33]), .Y(n1341) );
XOR2X4TS U4699 ( .A(n1344), .B(n1343), .Y(n1478) );
INVX2TS U4700 ( .A(n1347), .Y(n1349) );
NAND2X2TS U4701 ( .A(n1349), .B(n1348), .Y(n1350) );
XNOR2X4TS U4702 ( .A(n1351), .B(n1350), .Y(n1352) );
XNOR2X1TS U4703 ( .A(n741), .B(n1872), .Y(n1425) );
OAI22X1TS U4704 ( .A0(n1634), .A1(n3178), .B0(n1425), .B1(n3222), .Y(n1633)
);
OR2X4TS U4705 ( .A(n3632), .B(Op_MY[0]), .Y(n1356) );
NOR2X2TS U4706 ( .A(Op_MX[11]), .B(Op_MX[38]), .Y(n1357) );
XNOR2X4TS U4707 ( .A(n1617), .B(n1357), .Y(n1361) );
XNOR2X4TS U4708 ( .A(Op_MX[11]), .B(Op_MX[38]), .Y(n1379) );
NAND2X4TS U4709 ( .A(n1359), .B(n1358), .Y(n1366) );
NAND2X2TS U4710 ( .A(n1379), .B(n1366), .Y(n1360) );
XOR2X4TS U4711 ( .A(n1361), .B(n1360), .Y(n1616) );
NOR2BX1TS U4712 ( .AN(n1029), .B(n2214), .Y(n1627) );
INVX2TS U4713 ( .A(n1362), .Y(n1364) );
XNOR2X4TS U4714 ( .A(n1379), .B(n1366), .Y(n1367) );
INVX8TS U4715 ( .A(n1367), .Y(n3367) );
NOR2X2TS U4716 ( .A(Op_MX[9]), .B(Op_MX[36]), .Y(n1368) );
XNOR2X4TS U4717 ( .A(n1377), .B(n1368), .Y(n1372) );
XOR2X4TS U4718 ( .A(n1372), .B(n1371), .Y(n2215) );
INVX2TS U4719 ( .A(n1373), .Y(n1375) );
NAND2X2TS U4720 ( .A(n1375), .B(n1374), .Y(n1376) );
XOR2X1TS U4721 ( .A(n1380), .B(n1379), .Y(n1381) );
XNOR2X1TS U4722 ( .A(n2223), .B(n3227), .Y(n1382) );
OAI22X2TS U4723 ( .A0(n1383), .A1(n3301), .B0(n1382), .B1(n1751), .Y(n1423)
);
INVX4TS U4724 ( .A(n3367), .Y(n1979) );
NAND2BX1TS U4725 ( .AN(n2198), .B(n1979), .Y(n1384) );
INVX2TS U4726 ( .A(n1385), .Y(n1386) );
AOI21X4TS U4727 ( .A0(n1388), .A1(n1387), .B0(n1386), .Y(n1393) );
INVX2TS U4728 ( .A(n1389), .Y(n1391) );
NAND2X1TS U4729 ( .A(n1391), .B(n1390), .Y(n1392) );
XOR2X4TS U4730 ( .A(n1393), .B(n1392), .Y(n2532) );
INVX6TS U4731 ( .A(n1395), .Y(n2876) );
INVX12TS U4732 ( .A(n2876), .Y(n2771) );
XNOR2X1TS U4733 ( .A(n908), .B(n2771), .Y(n1410) );
INVX2TS U4734 ( .A(n1405), .Y(n1407) );
NAND2X1TS U4735 ( .A(n1407), .B(n1406), .Y(n1408) );
XOR2X4TS U4736 ( .A(n1409), .B(n1408), .Y(n2577) );
XNOR2X1TS U4737 ( .A(n911), .B(n1740), .Y(n1636) );
BUFX3TS U4738 ( .A(n2018), .Y(n2497) );
OAI22X1TS U4739 ( .A0(n1410), .A1(n2809), .B0(n1636), .B1(n2497), .Y(n1631)
);
XNOR2X1TS U4740 ( .A(n907), .B(n1740), .Y(n1467) );
OAI22X1TS U4741 ( .A0(n1410), .A1(n2808), .B0(n1467), .B1(n2100), .Y(n1474)
);
NOR2X8TS U4742 ( .A(Op_MY[36]), .B(Op_MY[9]), .Y(n1434) );
CLKINVX1TS U4743 ( .A(n1434), .Y(n1411) );
NAND2X4TS U4744 ( .A(Op_MY[36]), .B(Op_MY[9]), .Y(n1432) );
NAND2X1TS U4745 ( .A(n1411), .B(n1432), .Y(n1412) );
INVX4TS U4746 ( .A(n736), .Y(n1611) );
XNOR2X4TS U4747 ( .A(Op_MX[28]), .B(Op_MX[1]), .Y(n1449) );
XOR2X4TS U4748 ( .A(n1416), .B(n1415), .Y(n2627) );
OAI22X1TS U4749 ( .A0(n1439), .A1(n2559), .B0(n1483), .B1(n1895), .Y(n1473)
);
XNOR2X1TS U4750 ( .A(n911), .B(n1708), .Y(n1471) );
OAI22X1TS U4751 ( .A0(n1421), .A1(n2738), .B0(n1471), .B1(n2045), .Y(n1472)
);
XNOR2X1TS U4752 ( .A(n2580), .B(n2881), .Y(n1426) );
OAI22X1TS U4753 ( .A0(n1425), .A1(n3178), .B0(n1426), .B1(n3222), .Y(n1465)
);
NOR2BX1TS U4754 ( .AN(n1029), .B(n2215), .Y(n1470) );
BUFX3TS U4755 ( .A(n1478), .Y(n2303) );
OAI22X2TS U4756 ( .A0(n1430), .A1(n3178), .B0(n1429), .B1(n1428), .Y(n1475)
);
INVX2TS U4757 ( .A(n1453), .Y(n1436) );
OAI21X4TS U4758 ( .A0(n1434), .A1(n1433), .B0(n1432), .Y(n1459) );
OAI21X4TS U4759 ( .A0(n1675), .A1(n1436), .B0(n1435), .Y(n1438) );
XNOR2X4TS U4760 ( .A(n1438), .B(n1437), .Y(n2474) );
XNOR2X1TS U4761 ( .A(n901), .B(n1611), .Y(n1612) );
OAI22X1TS U4762 ( .A0(n1439), .A1(n2368), .B0(n1612), .B1(n2053), .Y(n1638)
);
INVX2TS U4763 ( .A(n1456), .Y(n1440) );
AOI21X1TS U4764 ( .A0(n1459), .A1(n1441), .B0(n1440), .Y(n1442) );
OAI21X4TS U4765 ( .A0(n1675), .A1(n1443), .B0(n1442), .Y(n1446) );
NAND2X1TS U4766 ( .A(n1444), .B(n1454), .Y(n1445) );
XNOR2X4TS U4767 ( .A(n1446), .B(n1445), .Y(n1447) );
XNOR2X1TS U4768 ( .A(n3368), .B(n2287), .Y(n1463) );
XOR2X1TS U4769 ( .A(n1006), .B(n1449), .Y(n1451) );
XOR2X1TS U4770 ( .A(Op_MX[27]), .B(Op_MX[0]), .Y(n1450) );
BUFX3TS U4771 ( .A(n1500), .Y(n2363) );
OAI21X4TS U4772 ( .A0(n1456), .A1(n1455), .B0(n1454), .Y(n1457) );
AOI21X4TS U4773 ( .A0(n1459), .A1(n1458), .B0(n1457), .Y(n1763) );
OAI21X4TS U4774 ( .A0(n1675), .A1(n1755), .B0(n1698), .Y(n1461) );
NAND2X1TS U4775 ( .A(n1603), .B(n1670), .Y(n1460) );
XNOR2X4TS U4776 ( .A(n1461), .B(n1460), .Y(n1462) );
BUFX3TS U4777 ( .A(n1812), .Y(n1974) );
OAI22X1TS U4778 ( .A0(n1463), .A1(n2363), .B0(n1610), .B1(n1974), .Y(n1637)
);
XNOR2X1TS U4779 ( .A(n901), .B(n2287), .Y(n1484) );
OAI22X1TS U4780 ( .A0(n1484), .A1(n2363), .B0(n1463), .B1(n1974), .Y(n1487)
);
XNOR2X1TS U4781 ( .A(n862), .B(n1740), .Y(n1477) );
OAI22X1TS U4782 ( .A0(n1467), .A1(n2808), .B0(n1477), .B1(n2100), .Y(n1490)
);
XNOR2X1TS U4783 ( .A(n908), .B(n2653), .Y(n1491) );
OAI22X1TS U4784 ( .A0(n1491), .A1(n2459), .B0(n1471), .B1(n2315), .Y(n1488)
);
CMPR32X2TS U4785 ( .A(n1474), .B(n1473), .C(n1472), .CO(n1628), .S(n1499) );
XNOR2X1TS U4786 ( .A(n857), .B(n2771), .Y(n1479) );
NOR2BX1TS U4787 ( .AN(n1029), .B(n3221), .Y(n1542) );
NAND2BX1TS U4788 ( .AN(n7232), .B(n1740), .Y(n1480) );
OAI22X1TS U4789 ( .A0(n1480), .A1(n2808), .B0(n2877), .B1(n2876), .Y(n1546)
);
XNOR2X1TS U4790 ( .A(n929), .B(n2771), .Y(n1481) );
XNOR2X1TS U4791 ( .A(n860), .B(n1611), .Y(n1493) );
OAI22X1TS U4792 ( .A0(n1493), .A1(n2368), .B0(n1483), .B1(n2053), .Y(n1495)
);
OAI22X1TS U4793 ( .A0(n1492), .A1(n2363), .B0(n1484), .B1(n1974), .Y(n1494)
);
CMPR32X2TS U4794 ( .A(n1490), .B(n1489), .C(n1488), .CO(n1485), .S(n1574) );
XNOR2X1TS U4795 ( .A(n907), .B(n1708), .Y(n1539) );
OAI22X1TS U4796 ( .A0(n1491), .A1(n2738), .B0(n1539), .B1(n2045), .Y(n1583)
);
BUFX3TS U4797 ( .A(n1500), .Y(n1810) );
OAI22X1TS U4798 ( .A0(n1492), .A1(n1812), .B0(n1544), .B1(n1810), .Y(n1582)
);
XNOR2X1TS U4799 ( .A(n911), .B(n1611), .Y(n1543) );
OAI22X1TS U4800 ( .A0(n1493), .A1(n2559), .B0(n1543), .B1(n1895), .Y(n1581)
);
NAND2X2TS U4801 ( .A(n789), .B(n734), .Y(n1602) );
CLKBUFX2TS U4802 ( .A(n1812), .Y(n7231) );
NAND2X1TS U4803 ( .A(n2477), .B(n1501), .Y(n7222) );
INVX2TS U4804 ( .A(n7224), .Y(n7220) );
XNOR2X1TS U4805 ( .A(n857), .B(n2254), .Y(n1506) );
OAI22X1TS U4806 ( .A0(n1506), .A1(n1812), .B0(n1502), .B1(n1810), .Y(n1504)
);
NOR2BX1TS U4807 ( .AN(n929), .B(n2559), .Y(n1503) );
NAND2X1TS U4808 ( .A(n1504), .B(n1503), .Y(n7218) );
INVX2TS U4809 ( .A(n7218), .Y(n1505) );
AOI21X4TS U4810 ( .A0(n7220), .A1(n7219), .B0(n1505), .Y(n7217) );
XNOR2X1TS U4811 ( .A(n741), .B(n2254), .Y(n1514) );
OAI22X1TS U4812 ( .A0(n1514), .A1(n1812), .B0(n1506), .B1(n1810), .Y(n1510)
);
NAND2BX1TS U4813 ( .AN(n2198), .B(n1611), .Y(n1507) );
OAI22X1TS U4814 ( .A0(n2560), .A1(n736), .B0(n1507), .B1(n2053), .Y(n1513)
);
XNOR2X1TS U4815 ( .A(n2198), .B(n2469), .Y(n1508) );
NOR2X1TS U4816 ( .A(n1510), .B(n1509), .Y(n7213) );
NAND2X1TS U4817 ( .A(n1510), .B(n1509), .Y(n7214) );
OAI21X4TS U4818 ( .A0(n7217), .A1(n7213), .B0(n7214), .Y(n7211) );
NOR2BX1TS U4819 ( .AN(n929), .B(n2787), .Y(n1524) );
XNOR2X1TS U4820 ( .A(n857), .B(n2469), .Y(n1521) );
OAI22X1TS U4821 ( .A0(n1521), .A1(n2053), .B0(n1511), .B1(n1895), .Y(n1523)
);
XNOR2X1TS U4822 ( .A(n907), .B(n2287), .Y(n1525) );
OAI22X1TS U4823 ( .A0(n1525), .A1(n1812), .B0(n1514), .B1(n1810), .Y(n1515)
);
NAND2X1TS U4824 ( .A(n1516), .B(n1515), .Y(n7209) );
INVX2TS U4825 ( .A(n7209), .Y(n1517) );
AOI21X4TS U4826 ( .A0(n7211), .A1(n7210), .B0(n1517), .Y(n7207) );
XNOR2X1TS U4827 ( .A(n929), .B(n2653), .Y(n1519) );
OAI22X1TS U4828 ( .A0(n1520), .A1(n2738), .B0(n2739), .B1(n2786), .Y(n1530)
);
XNOR2X1TS U4829 ( .A(n862), .B(n1611), .Y(n1528) );
OAI22X1TS U4830 ( .A0(n1528), .A1(n2559), .B0(n1521), .B1(n1895), .Y(n1534)
);
XNOR2X1TS U4831 ( .A(n908), .B(n2287), .Y(n1532) );
OAI22X1TS U4832 ( .A0(n1532), .A1(n7231), .B0(n1525), .B1(n1810), .Y(n1526)
);
NOR2X2TS U4833 ( .A(n1527), .B(n1526), .Y(n7204) );
NAND2X2TS U4834 ( .A(n1527), .B(n1526), .Y(n7205) );
OAI21X4TS U4835 ( .A0(n7207), .A1(n7204), .B0(n7205), .Y(n7202) );
XNOR2X1TS U4836 ( .A(n907), .B(n1611), .Y(n1552) );
OAI22X1TS U4837 ( .A0(n1552), .A1(n2559), .B0(n1528), .B1(n1895), .Y(n1564)
);
NOR2BX1TS U4838 ( .AN(n7232), .B(n2018), .Y(n1551) );
XNOR2X1TS U4839 ( .A(n2580), .B(n2653), .Y(n1547) );
OAI22X2TS U4840 ( .A0(n1547), .A1(n2738), .B0(n1529), .B1(n2045), .Y(n1550)
);
XNOR2X1TS U4841 ( .A(n911), .B(n2632), .Y(n1554) );
OAI22X1TS U4842 ( .A0(n1532), .A1(n2363), .B0(n1554), .B1(n1974), .Y(n1562)
);
AOI21X4TS U4843 ( .A0(n7202), .A1(n7201), .B0(n1538), .Y(n7190) );
XNOR2X1TS U4844 ( .A(n741), .B(n1708), .Y(n1548) );
OAI22X1TS U4845 ( .A0(n1539), .A1(n2738), .B0(n1548), .B1(n2045), .Y(n1577)
);
ADDFHX2TS U4846 ( .A(n1542), .B(n1541), .CI(n1540), .CO(n1578), .S(n1576) );
XNOR2X1TS U4847 ( .A(n2789), .B(n2469), .Y(n1553) );
OAI22X1TS U4848 ( .A0(n1553), .A1(n2368), .B0(n1543), .B1(n2053), .Y(n1575)
);
XNOR2X1TS U4849 ( .A(n860), .B(n2632), .Y(n1555) );
OAI22X1TS U4850 ( .A0(n1555), .A1(n2363), .B0(n1544), .B1(n1974), .Y(n1588)
);
OAI22X1TS U4851 ( .A0(n1548), .A1(n2738), .B0(n1547), .B1(n2045), .Y(n1557)
);
OAI22X1TS U4852 ( .A0(n1553), .A1(n2559), .B0(n1552), .B1(n1895), .Y(n1561)
);
OAI22X1TS U4853 ( .A0(n1555), .A1(n1812), .B0(n1554), .B1(n1810), .Y(n1560)
);
NOR2X4TS U4854 ( .A(n1568), .B(n1567), .Y(n1569) );
NAND2X2TS U4855 ( .A(n1566), .B(n1565), .Y(n7196) );
OAI21X4TS U4856 ( .A0(n7190), .A1(n1571), .B0(n1570), .Y(n7184) );
ADDFHX2TS U4857 ( .A(n1577), .B(n1576), .CI(n1575), .CO(n1586), .S(n1589) );
CMPR32X2TS U4858 ( .A(n1583), .B(n1582), .C(n1581), .CO(n1573), .S(n1584) );
CMPR32X2TS U4859 ( .A(n1586), .B(n1585), .C(n1584), .CO(n1592), .S(n1591) );
NAND2X2TS U4860 ( .A(n1591), .B(n1590), .Y(n7227) );
OAI21X4TS U4861 ( .A0(n7185), .A1(n7227), .B0(n7186), .Y(n1594) );
AOI21X4TS U4862 ( .A0(n7184), .A1(n1595), .B0(n1594), .Y(n7176) );
NAND2X2TS U4863 ( .A(n1597), .B(n1596), .Y(n7181) );
NAND2X2TS U4864 ( .A(n1599), .B(n1598), .Y(n7178) );
INVX2TS U4865 ( .A(n7178), .Y(n1600) );
OAI21X4TS U4866 ( .A0(n1602), .A1(n7176), .B0(n1601), .Y(n7159) );
AOI2BB1X4TS U4867 ( .A0N(n1698), .A1N(n1668), .B0(n1604), .Y(n1605) );
OAI21X4TS U4868 ( .A0(n1606), .A1(n1675), .B0(n1605), .Y(n1609) );
NAND2X1TS U4869 ( .A(n1607), .B(n1669), .Y(n1608) );
XNOR2X4TS U4870 ( .A(n1609), .B(n1608), .Y(n3217) );
BUFX20TS U4871 ( .A(n3217), .Y(n3364) );
XNOR2X1TS U4872 ( .A(n2954), .B(n2632), .Y(n1680) );
XNOR2X1TS U4873 ( .A(n916), .B(n1611), .Y(n1667) );
OAI22X1TS U4874 ( .A0(n1612), .A1(n2368), .B0(n1667), .B1(n2053), .Y(n1659)
);
XNOR2X4TS U4875 ( .A(Op_MX[13]), .B(Op_MX[40]), .Y(n1647) );
XNOR2X4TS U4876 ( .A(n1646), .B(n1647), .Y(n1615) );
BUFX12TS U4877 ( .A(n1616), .Y(n3427) );
NAND2X4TS U4878 ( .A(n3427), .B(n1620), .Y(n1622) );
XNOR2X1TS U4879 ( .A(n2198), .B(n3343), .Y(n1623) );
ADDFHX2TS U4880 ( .A(n1627), .B(n1626), .CI(n1625), .CO(n1664), .S(n1632) );
XNOR2X1TS U4881 ( .A(n2789), .B(n2881), .Y(n1654) );
OAI22X1TS U4882 ( .A0(n1654), .A1(n3178), .B0(n1634), .B1(n3222), .Y(n1663)
);
XNOR2X1TS U4883 ( .A(n2869), .B(n1708), .Y(n1644) );
OAI22X1TS U4884 ( .A0(n1644), .A1(n2738), .B0(n1635), .B1(n2045), .Y(n1662)
);
XNOR2X1TS U4885 ( .A(n860), .B(n1740), .Y(n1643) );
OAI22X1TS U4886 ( .A0(n1643), .A1(n2808), .B0(n1636), .B1(n2809), .Y(n1661)
);
ADDFHX2TS U4887 ( .A(n1639), .B(n1638), .CI(n1637), .CO(n1655), .S(n1641) );
NOR2X4TS U4888 ( .A(n1731), .B(n1732), .Y(n7168) );
OAI22X1TS U4889 ( .A0(n1643), .A1(n928), .B0(n1689), .B1(n2497), .Y(n1725)
);
XNOR2X1TS U4890 ( .A(n901), .B(n1708), .Y(n1709) );
OAI22X1TS U4891 ( .A0(n1644), .A1(n2459), .B0(n1709), .B1(n2315), .Y(n1724)
);
XNOR2X1TS U4892 ( .A(n907), .B(n1979), .Y(n1688) );
OAI22X1TS U4893 ( .A0(n1688), .A1(n3301), .B0(n1645), .B1(n2839), .Y(n1687)
);
NAND2X2TS U4894 ( .A(n1647), .B(n1646), .Y(n1650) );
XNOR2X4TS U4895 ( .A(n1711), .B(n1648), .Y(n1649) );
XOR2X4TS U4896 ( .A(n1650), .B(n1649), .Y(n1710) );
NOR2BX1TS U4897 ( .AN(n929), .B(n1710), .Y(n1722) );
XNOR2X1TS U4898 ( .A(n911), .B(n1872), .Y(n1690) );
OAI22X1TS U4899 ( .A0(n1654), .A1(n2730), .B0(n1690), .B1(n2303), .Y(n1685)
);
ADDFX2TS U4900 ( .A(n1663), .B(n1662), .CI(n1661), .CO(n1692), .S(n1656) );
INVX4TS U4901 ( .A(n736), .Y(n2468) );
XNOR2X1TS U4902 ( .A(n917), .B(n2468), .Y(n1684) );
OAI22X1TS U4903 ( .A0(n1667), .A1(n2368), .B0(n1684), .B1(n2053), .Y(n1695)
);
INVX2TS U4904 ( .A(n1761), .Y(n1672) );
OA21X4TS U4905 ( .A0(n1698), .A1(n1673), .B0(n1672), .Y(n1674) );
OAI21X4TS U4906 ( .A0(n1676), .A1(n1675), .B0(n1674), .Y(n1679) );
INVX2TS U4907 ( .A(n1753), .Y(n1677) );
NAND2X1TS U4908 ( .A(n1677), .B(n1757), .Y(n1678) );
XNOR2X4TS U4909 ( .A(n1679), .B(n1678), .Y(n3283) );
BUFX20TS U4910 ( .A(n3283), .Y(n3176) );
XNOR2X1TS U4911 ( .A(n913), .B(n2254), .Y(n1707) );
BUFX3TS U4912 ( .A(n1812), .Y(n2476) );
OAI22X1TS U4913 ( .A0(n1680), .A1(n2363), .B0(n1707), .B1(n2476), .Y(n1694)
);
XNOR2X1TS U4914 ( .A(n2954), .B(n2469), .Y(n1840) );
OAI22X1TS U4915 ( .A0(n1684), .A1(n1895), .B0(n1840), .B1(n2053), .Y(n1864)
);
XNOR2X1TS U4916 ( .A(n908), .B(n3227), .Y(n1752) );
OAI22X1TS U4917 ( .A0(n1752), .A1(n3301), .B0(n1688), .B1(n932), .Y(n1849)
);
XNOR2X1TS U4918 ( .A(n2878), .B(n1872), .Y(n1809) );
OAI22X1TS U4919 ( .A0(n1809), .A1(n3178), .B0(n1690), .B1(n3222), .Y(n1847)
);
INVX2TS U4920 ( .A(n1698), .Y(n1701) );
AOI21X4TS U4921 ( .A0(n1701), .A1(n1700), .B0(n1699), .Y(n1702) );
OAI2BB1X4TS U4922 ( .A0N(n1019), .A1N(n1767), .B0(n1702), .Y(n1705) );
INVX2TS U4923 ( .A(n1758), .Y(n1703) );
NAND2X1TS U4924 ( .A(n1703), .B(n1756), .Y(n1704) );
XNOR2X4TS U4925 ( .A(n1705), .B(n1704), .Y(n1706) );
OAI22X1TS U4926 ( .A0(n1709), .A1(n2459), .B0(n1807), .B1(n2315), .Y(n1851)
);
XOR2X1TS U4927 ( .A(n1712), .B(n1743), .Y(n1713) );
NAND2X2TS U4928 ( .A(Op_MX[14]), .B(Op_MX[41]), .Y(n1714) );
NAND2X4TS U4929 ( .A(n1715), .B(n1714), .Y(n1744) );
XNOR2X4TS U4930 ( .A(n1744), .B(n1743), .Y(n1747) );
NAND2BX1TS U4931 ( .AN(n2198), .B(n2294), .Y(n1716) );
XNOR2X1TS U4932 ( .A(n862), .B(n2070), .Y(n1741) );
OAI22X1TS U4933 ( .A0(n1741), .A1(n3427), .B0(n1719), .B1(n3428), .Y(n1835)
);
CMPR32X2TS U4934 ( .A(n1725), .B(n1724), .C(n1723), .CO(n1923), .S(n1728) );
NOR2X4TS U4935 ( .A(n7162), .B(n7163), .Y(n1739) );
NAND2X2TS U4936 ( .A(n1737), .B(n1736), .Y(n7164) );
OAI21X4TS U4937 ( .A0(n7161), .A1(n7163), .B0(n7164), .Y(n1738) );
AOI21X4TS U4938 ( .A0(n7159), .A1(n1739), .B0(n1738), .Y(n7155) );
XNOR2X1TS U4939 ( .A(n901), .B(n1740), .Y(n1837) );
XNOR2X1TS U4940 ( .A(n916), .B(n1740), .Y(n1830) );
OAI22X1TS U4941 ( .A0(n1837), .A1(n928), .B0(n1830), .B1(n2497), .Y(n1843)
);
XNOR2X1TS U4942 ( .A(n906), .B(n2070), .Y(n1775) );
OAI22X1TS U4943 ( .A0(n1775), .A1(n3427), .B0(n1741), .B1(n3428), .Y(n1846)
);
XOR2X4TS U4944 ( .A(Op_MX[16]), .B(Op_MX[43]), .Y(n1796) );
XNOR2X4TS U4945 ( .A(n1796), .B(n1742), .Y(n1746) );
XOR2X4TS U4946 ( .A(n1746), .B(n1745), .Y(n2563) );
NOR2BX1TS U4947 ( .AN(n929), .B(n2563), .Y(n1821) );
OAI22X2TS U4948 ( .A0(n1817), .A1(n2940), .B0(n1748), .B1(n888), .Y(n1820)
);
XNOR2X1TS U4949 ( .A(n911), .B(n1979), .Y(n1776) );
BUFX3TS U4950 ( .A(n2215), .Y(n2715) );
OAI22X1TS U4951 ( .A0(n1752), .A1(n933), .B0(n1776), .B1(n2715), .Y(n1844)
);
NOR2X4TS U4952 ( .A(n1755), .B(n1764), .Y(n1766) );
OAI21X4TS U4953 ( .A0(n1764), .A1(n1763), .B0(n1762), .Y(n1765) );
AOI21X4TS U4954 ( .A0(n1767), .A1(n1766), .B0(n1765), .Y(n1768) );
NAND2X1TS U4955 ( .A(n1769), .B(n1778), .Y(n1770) );
XNOR2X4TS U4956 ( .A(n1771), .B(n1770), .Y(n1772) );
XNOR2X1TS U4957 ( .A(n3330), .B(n2287), .Y(n1786) );
INVX2TS U4958 ( .A(n1777), .Y(n1773) );
NAND2X1TS U4959 ( .A(n1773), .B(n1779), .Y(n1774) );
XOR2X4TS U4960 ( .A(n818), .B(n1774), .Y(n2815) );
XNOR2X1TS U4961 ( .A(n3303), .B(n2254), .Y(n1813) );
OAI22X1TS U4962 ( .A0(n1786), .A1(n2476), .B0(n1813), .B1(n1810), .Y(n1841)
);
XNOR2X1TS U4963 ( .A(n908), .B(n3343), .Y(n1803) );
OAI22X1TS U4964 ( .A0(n1803), .A1(n3427), .B0(n1775), .B1(n934), .Y(n1806)
);
XNOR2X1TS U4965 ( .A(n2878), .B(n1979), .Y(n1831) );
OAI22X1TS U4966 ( .A0(n1831), .A1(n3301), .B0(n1776), .B1(n933), .Y(n1804)
);
INVX2TS U4967 ( .A(n1951), .Y(n1782) );
OAI21X4TS U4968 ( .A0(n1780), .A1(n1779), .B0(n1778), .Y(n1957) );
INVX2TS U4969 ( .A(n1957), .Y(n1781) );
OAI21X4TS U4970 ( .A0(n819), .A1(n1782), .B0(n1781), .Y(n1784) );
NOR2X4TS U4971 ( .A(Op_MY[45]), .B(Op_MY[18]), .Y(n1950) );
INVX2TS U4972 ( .A(n1950), .Y(n1901) );
NAND2X1TS U4973 ( .A(n1901), .B(n1953), .Y(n1783) );
XNOR2X4TS U4974 ( .A(n1784), .B(n1783), .Y(n1785) );
XNOR2X1TS U4975 ( .A(n922), .B(n2632), .Y(n1907) );
OAI22X1TS U4976 ( .A0(n1786), .A1(n2363), .B0(n1907), .B1(n1974), .Y(n1898)
);
XNOR2X1TS U4977 ( .A(n1787), .B(n2294), .Y(n1909) );
OAI22X1TS U4978 ( .A0(n1909), .A1(n2940), .B0(n1818), .B1(n890), .Y(n1894)
);
NOR2X2TS U4979 ( .A(Op_MX[17]), .B(Op_MX[44]), .Y(n1788) );
XNOR2X4TS U4980 ( .A(n1877), .B(n1788), .Y(n1792) );
OAI21X4TS U4981 ( .A0(Op_MX[16]), .A1(Op_MX[43]), .B0(Op_MX[15]), .Y(n1790)
);
NAND2X2TS U4982 ( .A(Op_MX[16]), .B(Op_MX[43]), .Y(n1789) );
NAND2X4TS U4983 ( .A(n1790), .B(n1789), .Y(n1793) );
XNOR2X4TS U4984 ( .A(Op_MX[17]), .B(Op_MX[44]), .Y(n1798) );
XOR2X4TS U4985 ( .A(n1792), .B(n1791), .Y(n2694) );
CLKBUFX2TS U4986 ( .A(n2694), .Y(n3052) );
NOR2BX1TS U4987 ( .AN(n1029), .B(n3052), .Y(n1887) );
INVX2TS U4988 ( .A(n1795), .Y(n1797) );
OAI22X2TS U4989 ( .A0(n1884), .A1(n2976), .B0(n728), .B1(n3006), .Y(n1886)
);
XNOR2X1TS U4990 ( .A(n911), .B(n2070), .Y(n1910) );
BUFX3TS U4991 ( .A(n2214), .Y(n2817) );
OAI22X1TS U4992 ( .A0(n1803), .A1(n3201), .B0(n1910), .B1(n2817), .Y(n1892)
);
OAI22X1TS U4993 ( .A0(n1814), .A1(n2459), .B0(n1829), .B1(n2315), .Y(n1824)
);
BUFX3TS U4994 ( .A(n2627), .Y(n2510) );
OAI22X1TS U4995 ( .A0(n1839), .A1(n2560), .B0(n1833), .B1(n2510), .Y(n1823)
);
CMPR22X2TS U4996 ( .A(n1816), .B(n1815), .CO(n1885), .S(n1827) );
OAI22X1TS U4997 ( .A0(n1818), .A1(n2940), .B0(n1817), .B1(n888), .Y(n1826)
);
ADDFHX2TS U4998 ( .A(n1821), .B(n1820), .CI(n1819), .CO(n1825), .S(n1845) );
ADDFHX2TS U4999 ( .A(n1827), .B(n1826), .CI(n1825), .CO(n1913), .S(n1822) );
XNOR2X1TS U5000 ( .A(n3176), .B(n2653), .Y(n1891) );
OAI22X1TS U5001 ( .A0(n1829), .A1(n2459), .B0(n1891), .B1(n2787), .Y(n1912)
);
XNOR2X1TS U5002 ( .A(n917), .B(n2720), .Y(n1871) );
OAI22X1TS U5003 ( .A0(n1830), .A1(n928), .B0(n1871), .B1(n2497), .Y(n1911)
);
XNOR2X1TS U5004 ( .A(n3165), .B(n1979), .Y(n1908) );
OAI22X1TS U5005 ( .A0(n1831), .A1(n932), .B0(n1908), .B1(n2715), .Y(n1890)
);
XNOR2X1TS U5006 ( .A(n914), .B(n2469), .Y(n1896) );
OAI22X1TS U5007 ( .A0(n1896), .A1(n2559), .B0(n1833), .B1(n1895), .Y(n1888)
);
ADDFHX2TS U5008 ( .A(n1836), .B(n1835), .CI(n1834), .CO(n1858), .S(n1850) );
OAI22X1TS U5009 ( .A0(n1838), .A1(n2809), .B0(n1837), .B1(n2497), .Y(n1857)
);
OAI22X1TS U5010 ( .A0(n1840), .A1(n2368), .B0(n1839), .B1(n2053), .Y(n1856)
);
ADDFHX2TS U5011 ( .A(n1867), .B(n1866), .CI(n1865), .CO(n1917), .S(n1920) );
OAI22X1TS U5012 ( .A0(n1871), .A1(n2100), .B0(n2029), .B1(n2497), .Y(n2123)
);
XNOR2X1TS U5013 ( .A(n3368), .B(n1872), .Y(n2024) );
OAI22X1TS U5014 ( .A0(n1873), .A1(n2730), .B0(n2024), .B1(n2303), .Y(n2122)
);
XNOR2X4TS U5015 ( .A(Op_MX[19]), .B(Op_MX[46]), .Y(n1982) );
NAND2X4TS U5016 ( .A(n1875), .B(n1874), .Y(n1981) );
XNOR2X4TS U5017 ( .A(n1982), .B(n1981), .Y(n1876) );
XOR2X1TS U5018 ( .A(n1879), .B(n1982), .Y(n1880) );
OAI22X1TS U5019 ( .A0(n1881), .A1(n3031), .B0(n1882), .B1(n3051), .Y(n1996)
);
XNOR2X2TS U5020 ( .A(n858), .B(n2997), .Y(n1993) );
XNOR2X1TS U5021 ( .A(n2223), .B(n2997), .Y(n1883) );
XNOR2X1TS U5022 ( .A(n741), .B(n2264), .Y(n2040) );
OAI22X1TS U5023 ( .A0(n2040), .A1(n2976), .B0(n1884), .B1(n3006), .Y(n2027)
);
OAI22X1TS U5024 ( .A0(n1891), .A1(n2739), .B0(n2025), .B1(n2315), .Y(n2135)
);
XNOR2X1TS U5025 ( .A(n921), .B(n2469), .Y(n2054) );
OAI22X1TS U5026 ( .A0(n2054), .A1(n2559), .B0(n1896), .B1(n1895), .Y(n2133)
);
INVX2TS U5027 ( .A(n1953), .Y(n1900) );
OAI21X4TS U5028 ( .A0(n818), .A1(n1903), .B0(n1902), .Y(n1906) );
CLKINVX1TS U5029 ( .A(n1954), .Y(n1904) );
NAND2X2TS U5030 ( .A(Op_MY[46]), .B(Op_MY[19]), .Y(n1952) );
NAND2X1TS U5031 ( .A(n1904), .B(n1952), .Y(n1905) );
XNOR2X4TS U5032 ( .A(n1906), .B(n1905), .Y(n3249) );
XNOR2X1TS U5033 ( .A(n3334), .B(n2287), .Y(n2120) );
OAI22X1TS U5034 ( .A0(n1907), .A1(n2363), .B0(n2120), .B1(n1974), .Y(n2150)
);
XNOR2X1TS U5035 ( .A(n2869), .B(n1979), .Y(n2031) );
OAI22X1TS U5036 ( .A0(n2044), .A1(n2940), .B0(n1909), .B1(n889), .Y(n2051)
);
XNOR2X1TS U5037 ( .A(n860), .B(n2070), .Y(n2022) );
OAI22X1TS U5038 ( .A0(n2022), .A1(n3427), .B0(n1910), .B1(n934), .Y(n2050)
);
CMPR32X2TS U5039 ( .A(n1928), .B(n1927), .C(n1926), .CO(n1865), .S(n1933) );
NAND2X4TS U5040 ( .A(n1947), .B(n7393), .Y(n1949) );
NAND2X2TS U5041 ( .A(n1941), .B(n1940), .Y(n7389) );
OAI21X4TS U5042 ( .A0(n7388), .A1(n7385), .B0(n7389), .Y(n7233) );
NAND2X4TS U5043 ( .A(n1943), .B(n1942), .Y(n7395) );
AOI21X4TS U5044 ( .A0(n1947), .A1(n7233), .B0(n1946), .Y(n1948) );
OAI21X4TS U5045 ( .A0(n7155), .A1(n1949), .B0(n1948), .Y(n7131) );
OAI21X4TS U5046 ( .A0(n1954), .A1(n1953), .B0(n1952), .Y(n1955) );
AOI21X4TS U5047 ( .A0(n1957), .A1(n1956), .B0(n1955), .Y(n2247) );
INVX4TS U5048 ( .A(n2247), .Y(n2002) );
INVX2TS U5049 ( .A(n1967), .Y(n1961) );
NAND2X2TS U5050 ( .A(Op_MY[48]), .B(Op_MY[21]), .Y(n1966) );
NAND2X1TS U5051 ( .A(n1961), .B(n1966), .Y(n1962) );
XNOR2X4TS U5052 ( .A(n1963), .B(n1962), .Y(n1964) );
XNOR2X1TS U5053 ( .A(n3338), .B(n2287), .Y(n2058) );
OAI21X4TS U5054 ( .A0(n1967), .A1(n1975), .B0(n1966), .Y(n2243) );
INVX2TS U5055 ( .A(n2236), .Y(n1970) );
NAND2X2TS U5056 ( .A(Op_MY[49]), .B(Op_MY[22]), .Y(n2240) );
NAND2X1TS U5057 ( .A(n1970), .B(n2240), .Y(n1971) );
XNOR2X4TS U5058 ( .A(n1972), .B(n1971), .Y(n1973) );
OAI22X1TS U5059 ( .A0(n2058), .A1(n2477), .B0(n2009), .B1(n1974), .Y(n2118)
);
NAND2X1TS U5060 ( .A(n1976), .B(n1975), .Y(n1977) );
XNOR2X4TS U5061 ( .A(n1978), .B(n1977), .Y(n2945) );
XNOR2X1TS U5062 ( .A(n915), .B(n2468), .Y(n2010) );
OAI22X1TS U5063 ( .A0(n2059), .A1(n2560), .B0(n2010), .B1(n2510), .Y(n2117)
);
XNOR2X1TS U5064 ( .A(n3285), .B(n2822), .Y(n2023) );
OAI22X1TS U5065 ( .A0(n2023), .A1(n3222), .B0(n2017), .B1(n2303), .Y(n2021)
);
XNOR2X1TS U5066 ( .A(n3368), .B(n1979), .Y(n2014) );
OAI22X1TS U5067 ( .A0(n2030), .A1(n933), .B0(n2014), .B1(n2715), .Y(n2020)
);
NOR2X2TS U5068 ( .A(Op_MX[19]), .B(Op_MX[46]), .Y(n1980) );
XNOR2X4TS U5069 ( .A(n1985), .B(n1980), .Y(n1984) );
NAND2X2TS U5070 ( .A(n1982), .B(n1981), .Y(n1983) );
XOR2X4TS U5071 ( .A(n1984), .B(n1983), .Y(n1990) );
XNOR2X4TS U5072 ( .A(Op_MX[21]), .B(Op_MX[48]), .Y(n2076) );
XOR2X1TS U5073 ( .A(n1986), .B(n2076), .Y(n1987) );
NAND2X2TS U5074 ( .A(Op_MX[20]), .B(Op_MX[47]), .Y(n1988) );
NAND2X4TS U5075 ( .A(n1989), .B(n1988), .Y(n2077) );
XOR2X4TS U5076 ( .A(n2077), .B(n2076), .Y(n2692) );
BUFX4TS U5077 ( .A(n1990), .Y(n3335) );
OAI22X2TS U5078 ( .A0(n3419), .A1(n2692), .B0(n1991), .B1(n3335), .Y(n2090)
);
INVX8TS U5079 ( .A(n2692), .Y(n3230) );
XNOR2X2TS U5080 ( .A(n859), .B(n3230), .Y(n2087) );
XNOR2X1TS U5081 ( .A(n741), .B(n2518), .Y(n2092) );
OAI22X1TS U5082 ( .A0(n2092), .A1(n3031), .B0(n1994), .B1(n3415), .Y(n2012)
);
NOR2BX1TS U5083 ( .AN(n7232), .B(n1990), .Y(n2043) );
ADDHX1TS U5084 ( .A(n1996), .B(n1995), .CO(n2041), .S(n2028) );
XNOR2X1TS U5085 ( .A(n922), .B(n2583), .Y(n2105) );
OAI22X1TS U5086 ( .A0(n2105), .A1(n2459), .B0(n2366), .B1(n2315), .Y(n2390)
);
INVX2TS U5087 ( .A(n2237), .Y(n1997) );
NOR2X2TS U5088 ( .A(n1997), .B(n2236), .Y(n2001) );
INVX2TS U5089 ( .A(n2243), .Y(n1999) );
OAI21X1TS U5090 ( .A0(n1999), .A1(n2236), .B0(n2240), .Y(n2000) );
NAND2X1TS U5091 ( .A(n2005), .B(n2239), .Y(n2006) );
XNOR2X4TS U5092 ( .A(n2007), .B(n2006), .Y(n2008) );
OAI22X1TS U5093 ( .A0(n2009), .A1(n2477), .B0(n2364), .B1(n2476), .Y(n2389)
);
XNOR2X1TS U5094 ( .A(n2869), .B(n2294), .Y(n2295) );
XNOR2X1TS U5095 ( .A(n3165), .B(n2294), .Y(n2015) );
OAI22X1TS U5096 ( .A0(n2295), .A1(n2940), .B0(n2015), .B1(n890), .Y(n2352)
);
XNOR2X1TS U5097 ( .A(n907), .B(n2518), .Y(n2093) );
OAI22X1TS U5098 ( .A0(n2277), .A1(n3031), .B0(n2093), .B1(n3415), .Y(n2351)
);
XNOR2X1TS U5099 ( .A(n860), .B(n2264), .Y(n2331) );
XNOR2X1TS U5100 ( .A(n911), .B(n2264), .Y(n2098) );
OAI22X1TS U5101 ( .A0(n2331), .A1(n2976), .B0(n2098), .B1(n3006), .Y(n2350)
);
XNOR2X1TS U5102 ( .A(n3338), .B(n2468), .Y(n2369) );
OAI22X1TS U5103 ( .A0(n2010), .A1(n2560), .B0(n2369), .B1(n2510), .Y(n2402)
);
ADDFHX2TS U5104 ( .A(n2013), .B(n2012), .CI(n2011), .CO(n2034), .S(n2019) );
XNOR2X1TS U5105 ( .A(n901), .B(n2070), .Y(n2071) );
OAI22X1TS U5106 ( .A0(n2062), .A1(n3201), .B0(n2071), .B1(n2817), .Y(n2033)
);
XNOR2X1TS U5107 ( .A(n917), .B(n3190), .Y(n2069) );
OAI22X1TS U5108 ( .A0(n2014), .A1(n932), .B0(n2069), .B1(n2715), .Y(n2032)
);
XNOR2X1TS U5109 ( .A(n2878), .B(n2294), .Y(n2065) );
OAI22X1TS U5110 ( .A0(n2065), .A1(n3279), .B0(n2015), .B1(n2762), .Y(n2037)
);
XNOR2X1TS U5111 ( .A(n3176), .B(n2881), .Y(n2091) );
OAI22X1TS U5112 ( .A0(n2017), .A1(n2730), .B0(n2091), .B1(n2016), .Y(n2036)
);
BUFX3TS U5113 ( .A(n2018), .Y(n2772) );
XNOR2X1TS U5114 ( .A(n2873), .B(n2771), .Y(n2038) );
OAI22X1TS U5115 ( .A0(n2101), .A1(n2772), .B0(n2038), .B1(n928), .Y(n2035)
);
ADDFHX2TS U5116 ( .A(n2021), .B(n2020), .CI(n2019), .CO(n2116), .S(n2129) );
OAI22X1TS U5117 ( .A0(n2022), .A1(n3201), .B0(n2061), .B1(n2817), .Y(n2132)
);
OAI22X1TS U5118 ( .A0(n2024), .A1(n2730), .B0(n2023), .B1(n2303), .Y(n2131)
);
XNOR2X1TS U5119 ( .A(n3303), .B(n2653), .Y(n2046) );
OAI22X1TS U5120 ( .A0(n2046), .A1(n2787), .B0(n2025), .B1(n2045), .Y(n2130)
);
ADDFHX2TS U5121 ( .A(n2028), .B(n2027), .CI(n2026), .CO(n2126), .S(n2121) );
XNOR2X1TS U5122 ( .A(n913), .B(n2771), .Y(n2039) );
OAI22X1TS U5123 ( .A0(n2031), .A1(n932), .B0(n2030), .B1(n2715), .Y(n2124)
);
ADDFHX2TS U5124 ( .A(n2034), .B(n2033), .CI(n2032), .CO(n2401), .S(n2068) );
OAI22X1TS U5125 ( .A0(n2039), .A1(n928), .B0(n2038), .B1(n2497), .Y(n2049)
);
XNOR2X1TS U5126 ( .A(n906), .B(n2264), .Y(n2063) );
OAI22X1TS U5127 ( .A0(n2063), .A1(n2976), .B0(n2040), .B1(n3006), .Y(n2057)
);
OAI22X1TS U5128 ( .A0(n2044), .A1(n3279), .B0(n2064), .B1(n2762), .Y(n2055)
);
XNOR2X1TS U5129 ( .A(n921), .B(n2653), .Y(n2106) );
OAI22X1TS U5130 ( .A0(n2106), .A1(n1828), .B0(n2046), .B1(n2045), .Y(n2047)
);
ADDFHX2TS U5131 ( .A(n2049), .B(n2048), .CI(n2047), .CO(n2066), .S(n2159) );
XNOR2X1TS U5132 ( .A(n922), .B(n2468), .Y(n2060) );
OAI22X1TS U5133 ( .A0(n2054), .A1(n2368), .B0(n2060), .B1(n2053), .Y(n2137)
);
XNOR2X1TS U5134 ( .A(n3384), .B(n2287), .Y(n2119) );
OAI22X1TS U5135 ( .A0(n2119), .A1(n2477), .B0(n2058), .B1(n2476), .Y(n2112)
);
OAI22X1TS U5136 ( .A0(n2060), .A1(n2368), .B0(n2059), .B1(n2510), .Y(n2111)
);
OAI22X1TS U5137 ( .A0(n2065), .A1(n2940), .B0(n2064), .B1(n889), .Y(n2102)
);
OAI22X1TS U5138 ( .A0(n2069), .A1(n933), .B0(n2333), .B1(n2715), .Y(n2372)
);
XNOR2X1TS U5139 ( .A(n3368), .B(n2070), .Y(n2293) );
OAI22X1TS U5140 ( .A0(n2071), .A1(n3201), .B0(n2293), .B1(n2817), .Y(n2371)
);
XNOR2X4TS U5141 ( .A(Op_MX[50]), .B(Op_MX[23]), .Y(n2201) );
NAND2X4TS U5142 ( .A(n2073), .B(n2072), .Y(n2200) );
XNOR2X4TS U5143 ( .A(n2201), .B(n2200), .Y(n2074) );
XOR2X4TS U5144 ( .A(Op_MX[22]), .B(Op_MX[49]), .Y(n2080) );
XNOR2X4TS U5145 ( .A(n2080), .B(n2075), .Y(n2079) );
NAND2X4TS U5146 ( .A(n2077), .B(n2076), .Y(n2078) );
XOR2X4TS U5147 ( .A(n2079), .B(n2078), .Y(n2946) );
NOR2X2TS U5148 ( .A(n3612), .B(n2080), .Y(n2081) );
XOR2X1TS U5149 ( .A(n2081), .B(n2201), .Y(n2082) );
XNOR2X2TS U5150 ( .A(n859), .B(n3329), .Y(n2210) );
XNOR2X1TS U5151 ( .A(n2223), .B(n3329), .Y(n2085) );
OAI22X2TS U5152 ( .A0(n2210), .A1(n3089), .B0(n2085), .B1(n2084), .Y(n2212)
);
OAI22X1TS U5153 ( .A0(n2271), .A1(n3188), .B0(n2088), .B1(n3231), .Y(n2297)
);
NOR2BX1TS U5154 ( .AN(n1029), .B(n2946), .Y(n2096) );
OAI22X2TS U5155 ( .A0(n2088), .A1(n3188), .B0(n2087), .B1(n3231), .Y(n2095)
);
CMPR22X2TS U5156 ( .A(n2090), .B(n2089), .CO(n2094), .S(n2013) );
OAI22X1TS U5157 ( .A0(n2091), .A1(n3179), .B0(n2334), .B1(n2303), .Y(n2387)
);
OAI22X1TS U5158 ( .A0(n2093), .A1(n3031), .B0(n2092), .B1(n3415), .Y(n2109)
);
ADDFHX2TS U5159 ( .A(n2096), .B(n2095), .CI(n2094), .CO(n2296), .S(n2108) );
OAI22X1TS U5160 ( .A0(n2099), .A1(n3432), .B0(n2098), .B1(n3290), .Y(n2107)
);
OAI22X1TS U5161 ( .A0(n2349), .A1(n2772), .B0(n2101), .B1(n2809), .Y(n2385)
);
OAI22X1TS U5162 ( .A0(n2106), .A1(n2459), .B0(n2105), .B1(n2315), .Y(n2114)
);
ADDFHX2TS U5163 ( .A(n2109), .B(n2108), .CI(n2107), .CO(n2386), .S(n2113) );
OAI22X1TS U5164 ( .A0(n2120), .A1(n2477), .B0(n2119), .B1(n2476), .Y(n2153)
);
NOR2X4TS U5165 ( .A(n2181), .B(n2182), .Y(n7147) );
NAND2X4TS U5166 ( .A(n2184), .B(n2183), .Y(n7148) );
NAND2X4TS U5167 ( .A(n2188), .B(n2187), .Y(n7144) );
INVX4TS U5168 ( .A(n7138), .Y(n2191) );
AOI21X4TS U5169 ( .A0(n7139), .A1(n7134), .B0(n2191), .Y(n2192) );
OAI21X4TS U5170 ( .A0(n2193), .A1(n7133), .B0(n2192), .Y(n2194) );
AOI21X4TS U5171 ( .A0(n7131), .A1(n2195), .B0(n2194), .Y(n7127) );
NAND2X4TS U5172 ( .A(n2197), .B(n2196), .Y(n2218) );
XOR2X4TS U5173 ( .A(n2218), .B(Op_MX[25]), .Y(n3129) );
NAND2BX1TS U5174 ( .AN(n2223), .B(n2871), .Y(n2208) );
NOR2X2TS U5175 ( .A(Op_MX[50]), .B(Op_MX[23]), .Y(n2199) );
XNOR2X4TS U5176 ( .A(n2204), .B(n2199), .Y(n2203) );
NOR2X2TS U5177 ( .A(n2205), .B(n2204), .Y(n2206) );
NAND2X6TS U5178 ( .A(n3118), .B(n2207), .Y(n2225) );
OAI22X2TS U5179 ( .A0(n2208), .A1(n3118), .B0(n2225), .B1(n2937), .Y(n2229)
);
XNOR2X2TS U5180 ( .A(n858), .B(n3358), .Y(n2226) );
OAI22X2TS U5181 ( .A0(n2226), .A1(n3118), .B0(n2209), .B1(n2225), .Y(n2228)
);
NOR2BX1TS U5182 ( .AN(n1029), .B(n2956), .Y(n2275) );
OAI22X2TS U5183 ( .A0(n2211), .A1(n3089), .B0(n2210), .B1(n931), .Y(n2274)
);
CMPR22X2TS U5184 ( .A(n2213), .B(n2212), .CO(n2273), .S(n2298) );
OAI22X1TS U5185 ( .A0(n2265), .A1(n3432), .B0(n2230), .B1(n3290), .Y(n2325)
);
BUFX3TS U5186 ( .A(n2214), .Y(n3344) );
OAI22X1TS U5187 ( .A0(n2270), .A1(n3201), .B0(n2217), .B1(n3344), .Y(n2324)
);
XNOR2X1TS U5188 ( .A(n3165), .B(n2518), .Y(n2312) );
OAI22X1TS U5189 ( .A0(n2266), .A1(n3250), .B0(n2312), .B1(n3411), .Y(n2269)
);
OAI22X1TS U5190 ( .A0(n2319), .A1(n3279), .B0(n2216), .B1(n2762), .Y(n2268)
);
XNOR2X1TS U5191 ( .A(n914), .B(n3227), .Y(n2235) );
BUFX3TS U5192 ( .A(n2215), .Y(n3228) );
XNOR2X2TS U5193 ( .A(n2873), .B(n3227), .Y(n2318) );
OAI22X1TS U5194 ( .A0(n2235), .A1(n3228), .B0(n2318), .B1(n932), .Y(n2267)
);
OAI22X1TS U5195 ( .A0(n2217), .A1(n934), .B0(n2500), .B1(n2817), .Y(n2463)
);
XOR2X4TS U5196 ( .A(n2219), .B(n3813), .Y(n2941) );
OAI21X1TS U5197 ( .A0(n2713), .A1(n971), .B0(n2220), .Y(n2506) );
XNOR2X1TS U5198 ( .A(n2222), .B(n2221), .Y(n2504) );
BUFX8TS U5199 ( .A(n2713), .Y(n2966) );
OAI22X1TS U5200 ( .A0(n2504), .A1(n3154), .B0(n2224), .B1(n2966), .Y(n2505)
);
XNOR2X1TS U5201 ( .A(n1352), .B(n2871), .Y(n2502) );
OAI22X1TS U5202 ( .A0(n2502), .A1(n3118), .B0(n2227), .B1(n3376), .Y(n2472)
);
NOR2BX1TS U5203 ( .AN(n2198), .B(n2941), .Y(n2234) );
OAI22X2TS U5204 ( .A0(n2227), .A1(n3118), .B0(n2226), .B1(n930), .Y(n2233)
);
XNOR2X1TS U5205 ( .A(n916), .B(n2264), .Y(n2481) );
OAI22X1TS U5206 ( .A0(n2230), .A1(n3432), .B0(n2481), .B1(n3290), .Y(n2490)
);
ADDFHX2TS U5207 ( .A(n2234), .B(n2233), .CI(n2232), .CO(n2471), .S(n2256) );
OAI22X1TS U5208 ( .A0(n2263), .A1(n3336), .B0(n2314), .B1(n3335), .Y(n2255)
);
OAI22X1TS U5209 ( .A0(n2513), .A1(n3228), .B0(n2235), .B1(n932), .Y(n2488)
);
NOR2X4TS U5210 ( .A(n2241), .B(n2236), .Y(n2244) );
AOI21X4TS U5211 ( .A0(n2244), .A1(n2243), .B0(n2242), .Y(n2245) );
OAI21X4TS U5212 ( .A0(n2247), .A1(n2246), .B0(n2245), .Y(n2279) );
OAI21X4TS U5213 ( .A0(n818), .A1(n2260), .B0(n2248), .Y(n2249) );
XNOR2X4TS U5214 ( .A(n2249), .B(n1017), .Y(n2950) );
NAND2X2TS U5215 ( .A(n2278), .B(n1030), .Y(n2253) );
AOI21X2TS U5216 ( .A0(n2279), .A1(n1030), .B0(n2251), .Y(n2252) );
OAI21X4TS U5217 ( .A0(n817), .A1(n2253), .B0(n2252), .Y(n3226) );
ADDFHX2TS U5218 ( .A(n2257), .B(n2256), .CI(n2255), .CO(n2489), .S(n2301) );
INVX2TS U5219 ( .A(n2283), .Y(n2258) );
XNOR2X1TS U5220 ( .A(n753), .B(n2632), .Y(n2288) );
OAI22X1TS U5221 ( .A0(n2288), .A1(n2477), .B0(n2262), .B1(n2476), .Y(n2300)
);
OAI22X1TS U5222 ( .A0(n2263), .A1(n3188), .B0(n2272), .B1(n3231), .Y(n2291)
);
XNOR2X1TS U5223 ( .A(n2577), .B(n2518), .Y(n2276) );
OAI22X1TS U5224 ( .A0(n2266), .A1(n3031), .B0(n2276), .B1(n935), .Y(n2289)
);
OAI22X1TS U5225 ( .A0(n2292), .A1(n3201), .B0(n2270), .B1(n2817), .Y(n2341)
);
OAI22X1TS U5226 ( .A0(n2277), .A1(n3250), .B0(n2276), .B1(n3411), .Y(n2345)
);
INVX2TS U5227 ( .A(n2278), .Y(n2282) );
INVX2TS U5228 ( .A(n2279), .Y(n2280) );
NAND2X1TS U5229 ( .A(n2284), .B(n2283), .Y(n2285) );
XNOR2X4TS U5230 ( .A(n2286), .B(n2285), .Y(n2957) );
XNOR2X1TS U5231 ( .A(n912), .B(n2632), .Y(n2362) );
OAI22X1TS U5232 ( .A0(n2362), .A1(n2477), .B0(n2288), .B1(n2476), .Y(n2355)
);
XNOR2X1TS U5233 ( .A(n3287), .B(n2720), .Y(n2348) );
OAI22X1TS U5234 ( .A0(n2348), .A1(n2809), .B0(n2307), .B1(n2497), .Y(n2354)
);
OAI22X1TS U5235 ( .A0(n2365), .A1(n2739), .B0(n2317), .B1(n2787), .Y(n2357)
);
OAI22X1TS U5236 ( .A0(n2293), .A1(n3201), .B0(n2292), .B1(n2817), .Y(n2375)
);
XNOR2X1TS U5237 ( .A(n2474), .B(n2294), .Y(n2320) );
OAI22X1TS U5238 ( .A0(n2295), .A1(n3279), .B0(n2320), .B1(n2762), .Y(n2374)
);
ADDFHX2TS U5239 ( .A(n2298), .B(n2297), .CI(n2296), .CO(n2373), .S(n2370) );
OAI22X1TS U5240 ( .A0(n2305), .A1(n2730), .B0(n2304), .B1(n2303), .Y(n2309)
);
OAI22X1TS U5241 ( .A0(n2307), .A1(n928), .B0(n2306), .B1(n2772), .Y(n2308)
);
CMPR32X2TS U5242 ( .A(n2310), .B(n2309), .C(n2308), .CO(n2550), .S(n2359) );
OAI22X1TS U5243 ( .A0(n2311), .A1(n2560), .B0(n2512), .B1(n2510), .Y(n2509)
);
OAI22X1TS U5244 ( .A0(n2316), .A1(n2739), .B0(n2460), .B1(n2787), .Y(n2508)
);
XNOR2X1TS U5245 ( .A(n2869), .B(n2518), .Y(n2475) );
OAI22X1TS U5246 ( .A0(n2503), .A1(n3089), .B0(n2313), .B1(n931), .Y(n2515)
);
OAI22X1TS U5247 ( .A0(n2479), .A1(n3188), .B0(n2314), .B1(n3231), .Y(n2514)
);
OAI22X1TS U5248 ( .A0(n2317), .A1(n2739), .B0(n2316), .B1(n2315), .Y(n2329)
);
ADDFHX2TS U5249 ( .A(n2323), .B(n2322), .CI(n2321), .CO(n2326), .S(n2336) );
OAI22X1TS U5250 ( .A0(n2331), .A1(n3432), .B0(n2330), .B1(n3290), .Y(n2378)
);
OAI22X1TS U5251 ( .A0(n2333), .A1(n2839), .B0(n2332), .B1(n3228), .Y(n2377)
);
OAI22X1TS U5252 ( .A0(n2335), .A1(n3178), .B0(n2334), .B1(n3222), .Y(n2376)
);
ADDFHX2TS U5253 ( .A(n2347), .B(n2346), .CI(n2345), .CO(n2339), .S(n2393) );
OAI22X1TS U5254 ( .A0(n2349), .A1(n2809), .B0(n2348), .B1(n2497), .Y(n2392)
);
ADDFHX2TS U5255 ( .A(n2358), .B(n2357), .CI(n2356), .CO(n2361), .S(n2394) );
OAI22X1TS U5256 ( .A0(n2364), .A1(n2363), .B0(n2362), .B1(n2476), .Y(n2399)
);
OAI22X1TS U5257 ( .A0(n2366), .A1(n2739), .B0(n2365), .B1(n1828), .Y(n2398)
);
OAI22X1TS U5258 ( .A0(n2369), .A1(n2368), .B0(n2367), .B1(n2510), .Y(n2397)
);
ADDFHX2TS U5259 ( .A(n2396), .B(n2395), .CI(n2394), .CO(n2408), .S(n2422) );
CMPR32X2TS U5260 ( .A(n2399), .B(n2398), .C(n2397), .CO(n2420), .S(n2432) );
ADDFHX4TS U5261 ( .A(n2411), .B(n2410), .CI(n2409), .CO(n2438), .S(n2434) );
ADDFHX2TS U5262 ( .A(n2420), .B(n2419), .CI(n2418), .CO(n2406), .S(n2440) );
OAI21X4TS U5263 ( .A0(n7127), .A1(n2455), .B0(n2454), .Y(n7123) );
OAI22X1TS U5264 ( .A0(n2460), .A1(n2459), .B0(n2541), .B1(n1828), .Y(n2547)
);
OAI22X1TS U5265 ( .A0(n2461), .A1(n3179), .B0(n2470), .B1(n2016), .Y(n2546)
);
ADDFHX2TS U5266 ( .A(n2464), .B(n2463), .CI(n2462), .CO(n2545), .S(n2465) );
ADDFHX2TS U5267 ( .A(n2467), .B(n2466), .CI(n2465), .CO(n2551), .S(n2556) );
OAI22X1TS U5268 ( .A0(n2498), .A1(n2809), .B0(n2588), .B1(n2772), .Y(n2585)
);
ADDFHX2TS U5269 ( .A(n2473), .B(n2472), .CI(n2471), .CO(n2484), .S(n2462) );
XNOR2X1TS U5270 ( .A(n2518), .B(n2474), .Y(n2519) );
OAI22X1TS U5271 ( .A0(n2475), .A1(n3250), .B0(n2519), .B1(n3411), .Y(n2483)
);
OAI22X1TS U5272 ( .A0(n2478), .A1(n2477), .B0(n1007), .B1(n2476), .Y(n2482)
);
XNOR2X1TS U5273 ( .A(n3330), .B(n3343), .Y(n2589) );
XNOR2X1TS U5274 ( .A(n914), .B(n3343), .Y(n2501) );
OAI22X1TS U5275 ( .A0(n2589), .A1(n3344), .B0(n2501), .B1(n934), .Y(n2598)
);
BUFX3TS U5276 ( .A(n1710), .Y(n3401) );
XNOR2X1TS U5277 ( .A(n917), .B(n3348), .Y(n2522) );
OAI22X1TS U5278 ( .A0(n2481), .A1(n3432), .B0(n2522), .B1(n3290), .Y(n2485)
);
ADDFHX2TS U5279 ( .A(n2484), .B(n2483), .CI(n2482), .CO(n2599), .S(n2493) );
ADDFHX2TS U5280 ( .A(n2493), .B(n2492), .CI(n2491), .CO(n2594), .S(n2674) );
ADDFHX2TS U5281 ( .A(n2496), .B(n2495), .CI(n2494), .CO(n2673), .S(n2555) );
OAI22X1TS U5282 ( .A0(n2501), .A1(n3344), .B0(n2500), .B1(n934), .Y(n2527)
);
OAI22X1TS U5283 ( .A0(n2533), .A1(n3118), .B0(n2502), .B1(n3376), .Y(n2525)
);
BUFX3TS U5284 ( .A(n2946), .Y(n3405) );
NOR2BX1TS U5285 ( .AN(n7232), .B(n971), .Y(n2539) );
XNOR2X1TS U5286 ( .A(n2221), .B(n732), .Y(n2536) );
OAI22X1TS U5287 ( .A0(n2536), .A1(n3154), .B0(n2504), .B1(n2966), .Y(n2538)
);
OAI22X1TS U5288 ( .A0(n2512), .A1(n2560), .B0(n2511), .B1(n2510), .Y(n2544)
);
XNOR2X1TS U5289 ( .A(n922), .B(n3190), .Y(n2540) );
OAI22X1TS U5290 ( .A0(n2513), .A1(n933), .B0(n2540), .B1(n2715), .Y(n2543)
);
OAI22X1TS U5291 ( .A0(n2557), .A1(n3188), .B0(n2517), .B1(n3231), .Y(n2603)
);
OAI22X1TS U5292 ( .A0(n2519), .A1(n3250), .B0(n2562), .B1(n3411), .Y(n2602)
);
XNOR2X1TS U5293 ( .A(n3359), .B(n2939), .Y(n2565) );
OAI22X1TS U5294 ( .A0(n2520), .A1(n890), .B0(n2565), .B1(n2762), .Y(n2601)
);
OAI22X1TS U5295 ( .A0(n2558), .A1(n3089), .B0(n2521), .B1(n931), .Y(n2606)
);
OAI22X1TS U5296 ( .A0(n2522), .A1(n3432), .B0(n2564), .B1(n3290), .Y(n2605)
);
ADDFHX2TS U5297 ( .A(n2525), .B(n2524), .CI(n2523), .CO(n2604), .S(n2526) );
ADDFHX2TS U5298 ( .A(n2531), .B(n2530), .CI(n2529), .CO(n2611), .S(n2672) );
OAI22X1TS U5299 ( .A0(n2579), .A1(n3118), .B0(n2533), .B1(n3376), .Y(n2574)
);
INVX2TS U5300 ( .A(n859), .Y(n2535) );
OAI22X1TS U5301 ( .A0(n2540), .A1(n933), .B0(n2590), .B1(n2715), .Y(n2567)
);
OAI22X1TS U5302 ( .A0(n2541), .A1(n2739), .B0(n2584), .B1(n1828), .Y(n2566)
);
XNOR2X2TS U5303 ( .A(n2650), .B(n900), .Y(n2651) );
OAI22X2TS U5304 ( .A0(n2557), .A1(n3336), .B0(n2651), .B1(n3335), .Y(n2648)
);
OAI22X1TS U5305 ( .A0(n2561), .A1(n2560), .B0(n2559), .B1(n736), .Y(n2646)
);
XNOR2X1TS U5306 ( .A(n917), .B(n3409), .Y(n2617) );
OAI22X1TS U5307 ( .A0(n2562), .A1(n3250), .B0(n2617), .B1(n3411), .Y(n2615)
);
BUFX3TS U5308 ( .A(n2563), .Y(n3430) );
XNOR2X1TS U5309 ( .A(n914), .B(n2939), .Y(n2645) );
OAI22X1TS U5310 ( .A0(n2645), .A1(n2940), .B0(n2565), .B1(n889), .Y(n2613)
);
ADDFHX2TS U5311 ( .A(n2571), .B(n2570), .CI(n2569), .CO(n2661), .S(n2610) );
BUFX3TS U5312 ( .A(n2956), .Y(n3360) );
INVX2TS U5313 ( .A(n857), .Y(n2581) );
XNOR2X2TS U5314 ( .A(n906), .B(n4730), .Y(n2633) );
OAI22X2TS U5315 ( .A0(n2633), .A1(n3154), .B0(n2582), .B1(n2966), .Y(n2630)
);
OAI22X1TS U5316 ( .A0(n2584), .A1(n2739), .B0(n2654), .B1(n1828), .Y(n2621)
);
OAI22X1TS U5317 ( .A0(n2589), .A1(n3201), .B0(n2634), .B1(n2817), .Y(n2637)
);
OAI22X1TS U5318 ( .A0(n2590), .A1(n933), .B0(n2635), .B1(n3228), .Y(n2636)
);
OAI22X1TS U5319 ( .A0(n2600), .A1(n3179), .B0(n2655), .B1(n2016), .Y(n2641)
);
CMPR32X2TS U5320 ( .A(n2606), .B(n2605), .C(n2604), .CO(n2639), .S(n2608) );
CMPR32X2TS U5321 ( .A(n2615), .B(n2614), .C(n2613), .CO(n2746), .S(n2658) );
OAI22X1TS U5322 ( .A0(n2736), .A1(n3118), .B0(n2616), .B1(n930), .Y(n2699)
);
XNOR2X1TS U5323 ( .A(n3364), .B(n2997), .Y(n2695) );
OAI22X1TS U5324 ( .A0(n2617), .A1(n3250), .B0(n2695), .B1(n3411), .Y(n2698)
);
INVX2TS U5325 ( .A(n741), .Y(n2629) );
XNOR2X1TS U5326 ( .A(n2789), .B(n4730), .Y(n2714) );
OAI22X1TS U5327 ( .A0(n2714), .A1(n3154), .B0(n2633), .B1(n2966), .Y(n2706)
);
XNOR2X1TS U5328 ( .A(n3338), .B(n3190), .Y(n2716) );
OAI22X1TS U5329 ( .A0(n2635), .A1(n932), .B0(n2716), .B1(n3228), .Y(n2700)
);
OAI22X1TS U5330 ( .A0(n2722), .A1(n3401), .B0(n2645), .B1(n889), .Y(n2743)
);
ADDFHX2TS U5331 ( .A(n2648), .B(n2647), .CI(n2646), .CO(n2742), .S(n2659) );
XNOR2X1TS U5332 ( .A(n2869), .B(n2784), .Y(n2737) );
OAI22X1TS U5333 ( .A0(n2737), .A1(n3089), .B0(n2649), .B1(n931), .Y(n2734)
);
OAI22X1TS U5334 ( .A0(n2651), .A1(n2086), .B0(n2693), .B1(n3335), .Y(n2733)
);
XNOR2X1TS U5335 ( .A(n3359), .B(n2944), .Y(n2696) );
OAI22X1TS U5336 ( .A0(n2652), .A1(n3350), .B0(n2696), .B1(n3290), .Y(n2732)
);
XNOR2X1TS U5337 ( .A(n853), .B(n2653), .Y(n2740) );
OAI22X1TS U5338 ( .A0(n2654), .A1(n2739), .B0(n2740), .B1(n2787), .Y(n2719)
);
XNOR2X1TS U5339 ( .A(n3349), .B(n2822), .Y(n2731) );
OAI22X1TS U5340 ( .A0(n2655), .A1(n2730), .B0(n2731), .B1(n2016), .Y(n2718)
);
OAI22X1TS U5341 ( .A0(n2656), .A1(n2809), .B0(n2721), .B1(n2772), .Y(n2717)
);
ADDFHX2TS U5342 ( .A(n2659), .B(n2658), .CI(n2657), .CO(n2727), .S(n2662) );
ADDFHX2TS U5343 ( .A(n2662), .B(n2661), .CI(n813), .CO(n2724), .S(n2668) );
ADDFHX2TS U5344 ( .A(n2665), .B(n2664), .CI(n2663), .CO(n2689), .S(n2666) );
ADDFHX2TS U5345 ( .A(n2674), .B(n2673), .CI(n2672), .CO(n2591), .S(n2688) );
XNOR2X4TS U5346 ( .A(n2678), .B(n2687), .Y(n2912) );
ADDFHX4TS U5347 ( .A(n2684), .B(n2683), .CI(n2682), .CO(n2916), .S(n2914) );
OAI21X4TS U5348 ( .A0(n2687), .A1(n2688), .B0(n2685), .Y(n2686) );
OAI2BB1X4TS U5349 ( .A0N(n2688), .A1N(n2687), .B0(n2686), .Y(n2913) );
INVX4TS U5350 ( .A(n2692), .Y(n3383) );
OAI22X1TS U5351 ( .A0(n2693), .A1(n3336), .B0(n2757), .B1(n3335), .Y(n2755)
);
XNOR2X2TS U5352 ( .A(n913), .B(n2997), .Y(n2758) );
BUFX3TS U5353 ( .A(n2694), .Y(n3413) );
OAI22X1TS U5354 ( .A0(n2695), .A1(n3250), .B0(n2758), .B1(n3413), .Y(n2754)
);
OAI22X1TS U5355 ( .A0(n2764), .A1(n3430), .B0(n2696), .B1(n3006), .Y(n2753)
);
INVX2TS U5356 ( .A(n906), .Y(n2710) );
NOR2X2TS U5357 ( .A(n2710), .B(n971), .Y(n2827) );
INVX2TS U5358 ( .A(n2827), .Y(n2767) );
BUFX4TS U5359 ( .A(n2713), .Y(n3155) );
BUFX3TS U5360 ( .A(n3155), .Y(n3424) );
XNOR2X1TS U5361 ( .A(n2577), .B(n4730), .Y(n2756) );
BUFX3TS U5362 ( .A(n2941), .Y(n3365) );
OAI22X1TS U5363 ( .A0(n2714), .A1(n3424), .B0(n2756), .B1(n3365), .Y(n2765)
);
XNOR2X1TS U5364 ( .A(n919), .B(n3190), .Y(n2775) );
OAI22X1TS U5365 ( .A0(n2716), .A1(n932), .B0(n2775), .B1(n2715), .Y(n2759)
);
OAI22X1TS U5366 ( .A0(n2722), .A1(n3279), .B0(n2763), .B1(n2762), .Y(n2769)
);
OAI22X1TS U5367 ( .A0(n2723), .A1(n3428), .B0(n2774), .B1(n3344), .Y(n2768)
);
ADDFHX4TS U5368 ( .A(n2726), .B(n2725), .CI(n2724), .CO(n2804), .S(n2690) );
XNOR2X1TS U5369 ( .A(n3278), .B(n2822), .Y(n2779) );
OAI22X1TS U5370 ( .A0(n2731), .A1(n2730), .B0(n2779), .B1(n3221), .Y(n2793)
);
XNOR2X1TS U5371 ( .A(n2735), .B(n2871), .Y(n2783) );
OAI22X1TS U5372 ( .A0(n2736), .A1(n930), .B0(n2783), .B1(n3360), .Y(n2782)
);
OAI22X1TS U5373 ( .A0(n2740), .A1(n2739), .B0(n2738), .B1(n2786), .Y(n2780)
);
CMPR32X2TS U5374 ( .A(n2743), .B(n2742), .C(n2741), .CO(n2798), .S(n2729) );
OAI22X1TS U5375 ( .A0(n2829), .A1(n3154), .B0(n2756), .B1(n2966), .Y(n2813)
);
OAI22X1TS U5376 ( .A0(n2758), .A1(n3415), .B0(n2816), .B1(n3411), .Y(n2811)
);
ADDFHX2TS U5377 ( .A(n2761), .B(n2760), .CI(n2759), .CO(n2848), .S(n2752) );
OAI22X1TS U5378 ( .A0(n2773), .A1(n928), .B0(n2810), .B1(n2772), .Y(n2832)
);
XNOR2X1TS U5379 ( .A(n3349), .B(n3190), .Y(n2840) );
OAI22X1TS U5380 ( .A0(n2775), .A1(n933), .B0(n2840), .B1(n3228), .Y(n2830)
);
OAI22X1TS U5381 ( .A0(n2779), .A1(n3179), .B0(n2823), .B1(n2016), .Y(n2847)
);
XNOR2X1TS U5382 ( .A(n2869), .B(n2871), .Y(n2814) );
OAI22X1TS U5383 ( .A0(n2814), .A1(n3118), .B0(n2783), .B1(n930), .Y(n2844)
);
OAI22X1TS U5384 ( .A0(n2785), .A1(n3407), .B0(n2807), .B1(n3405), .Y(n2843)
);
INVX2TS U5385 ( .A(n2789), .Y(n2790) );
NOR2X1TS U5386 ( .A(n2790), .B(n3583), .Y(n2826) );
ADDFHX2TS U5387 ( .A(n2802), .B(n2801), .CI(n2800), .CO(n2836), .S(n2805) );
BUFX3TS U5388 ( .A(n1990), .Y(n3417) );
OAI22X1TS U5389 ( .A0(n2806), .A1(n3336), .B0(n2874), .B1(n3417), .Y(n2868)
);
INVX4TS U5390 ( .A(n3107), .Y(n3074) );
OAI22X1TS U5391 ( .A0(n2814), .A1(n3376), .B0(n2872), .B1(n3360), .Y(n2865)
);
OAI22X1TS U5392 ( .A0(n2880), .A1(n3413), .B0(n2816), .B1(n935), .Y(n2864)
);
OAI22X1TS U5393 ( .A0(n2818), .A1(n3428), .B0(n2898), .B1(n2817), .Y(n2863)
);
XNOR2X2TS U5394 ( .A(n922), .B(n3348), .Y(n2883) );
OAI22X1TS U5395 ( .A0(n2824), .A1(n3432), .B0(n2883), .B1(n3290), .Y(n2888)
);
INVX2TS U5396 ( .A(n3182), .Y(n2886) );
XNOR2X1TS U5397 ( .A(n3165), .B(n4730), .Y(n2870) );
OAI22X1TS U5398 ( .A0(n2829), .A1(n3424), .B0(n2870), .B1(n3365), .Y(n2884)
);
ADDFHX2TS U5399 ( .A(n2838), .B(n2837), .CI(n2836), .CO(n2909), .S(n2857) );
XNOR2X1TS U5400 ( .A(n3278), .B(n3190), .Y(n2896) );
OAI22X1TS U5401 ( .A0(n2840), .A1(n933), .B0(n2896), .B1(n3228), .Y(n2895)
);
XNOR2X1TS U5402 ( .A(n3384), .B(n3346), .Y(n2897) );
OAI22X1TS U5403 ( .A0(n2841), .A1(n890), .B0(n2897), .B1(n3401), .Y(n2894)
);
CMPR32X2TS U5404 ( .A(n2850), .B(n2849), .C(n2848), .CO(n2890), .S(n2855) );
ADDFHX2TS U5405 ( .A(n2853), .B(n2852), .CI(n2851), .CO(n2906), .S(n2838) );
XNOR2X1TS U5406 ( .A(n2869), .B(Op_MX[26]), .Y(n3169) );
OAI22X1TS U5407 ( .A0(n3169), .A1(n3154), .B0(n2870), .B1(n2966), .Y(n3164)
);
OAI22X1TS U5408 ( .A0(n2872), .A1(n3376), .B0(n3168), .B1(n3360), .Y(n3163)
);
OAI22X1TS U5409 ( .A0(n2874), .A1(n3419), .B0(n3187), .B1(n3335), .Y(n3162)
);
XNOR2X1TS U5410 ( .A(n3364), .B(n3329), .Y(n3177) );
OAI22X1TS U5411 ( .A0(n2875), .A1(n3407), .B0(n3177), .B1(n3405), .Y(n3172)
);
INVX2TS U5412 ( .A(n2878), .Y(n2879) );
NOR2X1TS U5413 ( .A(n2879), .B(n971), .Y(n3181) );
XNOR2X1TS U5414 ( .A(n3330), .B(n2997), .Y(n3189) );
OAI22X1TS U5415 ( .A0(n3189), .A1(n3413), .B0(n2880), .B1(n3415), .Y(n3170)
);
OAI22X1TS U5416 ( .A0(n2882), .A1(n3179), .B0(n3180), .B1(n2016), .Y(n3186)
);
XNOR2X1TS U5417 ( .A(n3249), .B(n3348), .Y(n3203) );
OAI22X1TS U5418 ( .A0(n2883), .A1(n3432), .B0(n3203), .B1(n3290), .Y(n3185)
);
XNOR2X1TS U5419 ( .A(n753), .B(n3190), .Y(n3191) );
OAI22X1TS U5420 ( .A0(n2896), .A1(n932), .B0(n3191), .B1(n3228), .Y(n3200)
);
XNOR2X1TS U5421 ( .A(n3338), .B(n3346), .Y(n3204) );
OAI22X1TS U5422 ( .A0(n2897), .A1(n889), .B0(n3204), .B1(n3401), .Y(n3199)
);
XNOR2X1TS U5423 ( .A(n918), .B(n3275), .Y(n3202) );
OAI22X1TS U5424 ( .A0(n2898), .A1(n934), .B0(n3202), .B1(n3344), .Y(n3198)
);
CMPR32X2TS U5425 ( .A(n2901), .B(n2900), .C(n2899), .CO(n3195), .S(n2904) );
ADDFHX4TS U5426 ( .A(n2910), .B(n2909), .CI(n2908), .CO(n2928), .S(n2927) );
OAI21X4TS U5427 ( .A0(n2915), .A1(n7124), .B0(n7369), .Y(n7251) );
NAND2X4TS U5428 ( .A(n2919), .B(n2918), .Y(n7381) );
OAI21X4TS U5429 ( .A0(n7380), .A1(n7374), .B0(n7381), .Y(n2920) );
AOI21X4TS U5430 ( .A0(n2921), .A1(n7251), .B0(n2920), .Y(n7244) );
NAND2X4TS U5431 ( .A(n2925), .B(n2924), .Y(n7283) );
OAI21X4TS U5432 ( .A0(n7282), .A1(n7288), .B0(n7283), .Y(n7245) );
AOI21X4TS U5433 ( .A0(n7245), .A1(n2931), .B0(n2930), .Y(n2932) );
OAI21X4TS U5434 ( .A0(n7244), .A1(n2933), .B0(n2932), .Y(n2934) );
AOI21X4TS U5435 ( .A0(n7123), .A1(n2935), .B0(n2934), .Y(n2936) );
XNOR2X1TS U5436 ( .A(n3287), .B(n3167), .Y(n2964) );
OAI22X1TS U5437 ( .A0(n2964), .A1(n930), .B0(n2990), .B1(n3360), .Y(n2983)
);
NOR2X2TS U5438 ( .A(n2938), .B(n3583), .Y(n2979) );
INVX2TS U5439 ( .A(n2979), .Y(n2949) );
OAI22X1TS U5440 ( .A0(n2951), .A1(n889), .B0(n2940), .B1(n2942), .Y(n2948)
);
BUFX3TS U5441 ( .A(n2221), .Y(n3363) );
BUFX3TS U5442 ( .A(n2941), .Y(n3422) );
XNOR2X1TS U5443 ( .A(n3359), .B(n3363), .Y(n2952) );
OAI22X1TS U5444 ( .A0(n2967), .A1(n3422), .B0(n2952), .B1(n2966), .Y(n2947)
);
INVX2TS U5445 ( .A(n3359), .Y(n2943) );
NOR2X1TS U5446 ( .A(n2943), .B(n3583), .Y(n2978) );
XNOR2X1TS U5447 ( .A(n2945), .B(n3074), .Y(n2962) );
XNOR2X1TS U5448 ( .A(n920), .B(n3074), .Y(n2973) );
BUFX3TS U5449 ( .A(n2946), .Y(n3333) );
OAI22X1TS U5450 ( .A0(n2962), .A1(n3331), .B0(n2973), .B1(n3333), .Y(n2984)
);
CMPR32X2TS U5451 ( .A(n2949), .B(n2948), .C(n2947), .CO(n2982), .S(n3448) );
XNOR2X1TS U5452 ( .A(n3346), .B(n2950), .Y(n3402) );
OAI22X1TS U5453 ( .A0(n3402), .A1(n889), .B0(n2951), .B1(n3401), .Y(n3388)
);
OAI22X1TS U5454 ( .A0(n3423), .A1(n3155), .B0(n2952), .B1(n3365), .Y(n3387)
);
NOR2X2TS U5455 ( .A(n2953), .B(n971), .Y(n3421) );
INVX2TS U5456 ( .A(n2954), .Y(n2955) );
NOR2X1TS U5457 ( .A(n2955), .B(n3157), .Y(n2960) );
XNOR2X1TS U5458 ( .A(n3330), .B(n3358), .Y(n2965) );
BUFX3TS U5459 ( .A(n2956), .Y(n3378) );
XNOR2X1TS U5460 ( .A(n914), .B(n3358), .Y(n3379) );
OAI22X1TS U5461 ( .A0(n2965), .A1(n3378), .B0(n3379), .B1(n930), .Y(n3391)
);
XNOR2X1TS U5462 ( .A(n2957), .B(n3348), .Y(n3431) );
XNOR2X1TS U5463 ( .A(n754), .B(n3348), .Y(n2959) );
OAI22X1TS U5464 ( .A0(n3431), .A1(n3350), .B0(n2959), .B1(n3430), .Y(n3390)
);
XNOR2X1TS U5465 ( .A(n3287), .B(n3074), .Y(n3406) );
XNOR2X1TS U5466 ( .A(n3249), .B(n3074), .Y(n2963) );
OAI22X1TS U5467 ( .A0(n3406), .A1(n3407), .B0(n2963), .B1(n3405), .Y(n3389)
);
OAI22X1TS U5468 ( .A0(n2959), .A1(n3350), .B0(n2958), .B1(n3430), .Y(n3454)
);
OAI22X1TS U5469 ( .A0(n3418), .A1(n3336), .B0(n2969), .B1(n3417), .Y(n3453)
);
XNOR2X1TS U5470 ( .A(n918), .B(n3409), .Y(n3414) );
OAI22X1TS U5471 ( .A0(n3414), .A1(n3250), .B0(n2968), .B1(n3413), .Y(n3452)
);
CMPR32X2TS U5472 ( .A(n2961), .B(n3421), .C(n2960), .CO(n3451), .S(n3386) );
OAI22X1TS U5473 ( .A0(n2963), .A1(n931), .B0(n2962), .B1(n3333), .Y(n3450)
);
OAI22X1TS U5474 ( .A0(n2965), .A1(n3376), .B0(n2964), .B1(n3360), .Y(n3449)
);
OAI22X1TS U5475 ( .A0(n2974), .A1(n3422), .B0(n2967), .B1(n2966), .Y(n2989)
);
OAI22X1TS U5476 ( .A0(n2969), .A1(n3419), .B0(n2992), .B1(n3417), .Y(n2987)
);
CMPR32X2TS U5477 ( .A(n2972), .B(n2971), .C(n2970), .CO(n3471), .S(n3458) );
XNOR2X1TS U5478 ( .A(n919), .B(n3074), .Y(n2999) );
OAI22X1TS U5479 ( .A0(n2973), .A1(n931), .B0(n2999), .B1(n3405), .Y(n3010)
);
XNOR2X1TS U5480 ( .A(n3287), .B(n3363), .Y(n3004) );
OAI22X1TS U5481 ( .A0(n2974), .A1(n3424), .B0(n3004), .B1(n3365), .Y(n3009)
);
INVX2TS U5482 ( .A(n914), .Y(n2975) );
INVX2TS U5483 ( .A(n3029), .Y(n2995) );
OAI22X1TS U5484 ( .A0(n2977), .A1(n3350), .B0(n2976), .B1(n3005), .Y(n2994)
);
CMPR32X2TS U5485 ( .A(n2980), .B(n2979), .C(n2978), .CO(n2993), .S(n2986) );
CMPR32X2TS U5486 ( .A(n2983), .B(n2982), .C(n2981), .CO(n3015), .S(n3460) );
OAI22X1TS U5487 ( .A0(n2990), .A1(n3361), .B0(n3003), .B1(n3378), .Y(n3002)
);
XNOR2X1TS U5488 ( .A(n3278), .B(n3383), .Y(n2996) );
OAI22X1TS U5489 ( .A0(n2992), .A1(n3336), .B0(n2996), .B1(n3417), .Y(n3000)
);
XNOR2X1TS U5490 ( .A(n754), .B(n3383), .Y(n3034) );
OAI22X1TS U5491 ( .A0(n2996), .A1(n3419), .B0(n3034), .B1(n3417), .Y(n3038)
);
OAI22X1TS U5492 ( .A0(n2998), .A1(n3415), .B0(n3032), .B1(n3413), .Y(n3037)
);
XNOR2X1TS U5493 ( .A(n3349), .B(n3074), .Y(n3035) );
OAI22X1TS U5494 ( .A0(n2999), .A1(n3331), .B0(n3035), .B1(n3333), .Y(n3036)
);
CMPR32X2TS U5495 ( .A(n3002), .B(n3001), .C(n3000), .CO(n3020), .S(n3011) );
XNOR2X1TS U5496 ( .A(n920), .B(n3167), .Y(n3027) );
OAI22X1TS U5497 ( .A0(n3003), .A1(n3361), .B0(n3027), .B1(n3378), .Y(n3025)
);
OAI22X1TS U5498 ( .A0(n3004), .A1(n3424), .B0(n3026), .B1(n3365), .Y(n3024)
);
AO21X1TS U5499 ( .A0(n3006), .A1(n2563), .B0(n3005), .Y(n3030) );
INVX2TS U5500 ( .A(n921), .Y(n3007) );
NOR2X1TS U5501 ( .A(n3007), .B(n3583), .Y(n3028) );
CMPR32X2TS U5502 ( .A(n3010), .B(n3009), .C(n3008), .CO(n3018), .S(n3016) );
CMPR32X2TS U5503 ( .A(n3022), .B(n3021), .C(n3020), .CO(n3043), .S(n3041) );
CMPR32X2TS U5504 ( .A(n3025), .B(n3024), .C(n3023), .CO(n3063), .S(n3019) );
XNOR2X1TS U5505 ( .A(n915), .B(Op_MX[26]), .Y(n3047) );
OAI22X1TS U5506 ( .A0(n3026), .A1(n3155), .B0(n3047), .B1(n3422), .Y(n3050)
);
XNOR2X1TS U5507 ( .A(n919), .B(n3167), .Y(n3054) );
OAI22X1TS U5508 ( .A0(n3027), .A1(n3361), .B0(n3054), .B1(n3360), .Y(n3049)
);
CMPR32X2TS U5509 ( .A(n3030), .B(n3029), .C(n3028), .CO(n3048), .S(n3023) );
OAI22X1TS U5510 ( .A0(n3032), .A1(n935), .B0(n3031), .B1(n3051), .Y(n3057)
);
NOR2X2TS U5511 ( .A(n3033), .B(n3157), .Y(n3079) );
INVX2TS U5512 ( .A(n3079), .Y(n3056) );
XNOR2X1TS U5513 ( .A(n3278), .B(n3074), .Y(n3046) );
OAI22X1TS U5514 ( .A0(n3035), .A1(n3407), .B0(n3046), .B1(n3333), .Y(n3059)
);
OAI22X1TS U5515 ( .A0(n3045), .A1(n3419), .B0(n3073), .B1(n3417), .Y(n3072)
);
OAI22X1TS U5516 ( .A0(n3046), .A1(n931), .B0(n3075), .B1(n3333), .Y(n3071)
);
XNOR2X1TS U5517 ( .A(n3338), .B(n3363), .Y(n3077) );
OAI22X1TS U5518 ( .A0(n3047), .A1(n3155), .B0(n3077), .B1(n3422), .Y(n3070)
);
CMPR32X2TS U5519 ( .A(n3050), .B(n3049), .C(n3048), .CO(n3082), .S(n3062) );
NOR2X1TS U5520 ( .A(n3053), .B(n3157), .Y(n3078) );
XNOR2X1TS U5521 ( .A(n918), .B(n3167), .Y(n3076) );
OAI22X1TS U5522 ( .A0(n3054), .A1(n3361), .B0(n3076), .B1(n3378), .Y(n3068)
);
CMPR32X2TS U5523 ( .A(n3057), .B(n3056), .C(n3055), .CO(n3067), .S(n3060) );
ADDFX2TS U5524 ( .A(n3060), .B(n3059), .CI(n3058), .CO(n3065), .S(n3061) );
CMPR32X2TS U5525 ( .A(n3063), .B(n3062), .C(n3061), .CO(n3064), .S(n3042) );
CMPR32X2TS U5526 ( .A(n3069), .B(n3068), .C(n3067), .CO(n3135), .S(n3081) );
CMPR32X2TS U5527 ( .A(n3072), .B(n3071), .C(n3070), .CO(n3144), .S(n3083) );
OAI22X1TS U5528 ( .A0(n3073), .A1(n3419), .B0(n3188), .B1(n2692), .Y(n3098)
);
INVX2TS U5529 ( .A(n3094), .Y(n3097) );
XNOR2X1TS U5530 ( .A(n3276), .B(n3074), .Y(n3084) );
OAI22X1TS U5531 ( .A0(n3075), .A1(n3331), .B0(n3084), .B1(n3333), .Y(n3096)
);
XNOR2X1TS U5532 ( .A(n912), .B(n3167), .Y(n3086) );
OAI22X1TS U5533 ( .A0(n3076), .A1(n930), .B0(n3086), .B1(n3378), .Y(n3138)
);
XNOR2X1TS U5534 ( .A(n3410), .B(n3363), .Y(n3085) );
OAI22X1TS U5535 ( .A0(n3077), .A1(n3155), .B0(n3085), .B1(n3365), .Y(n3137)
);
CMPR32X2TS U5536 ( .A(n3080), .B(n3079), .C(n3078), .CO(n3136), .S(n3069) );
XNOR2X1TS U5537 ( .A(n3582), .B(n3329), .Y(n3090) );
OAI22X1TS U5538 ( .A0(n3084), .A1(n931), .B0(n3090), .B1(n3333), .Y(n3101)
);
XNOR2X1TS U5539 ( .A(n918), .B(n3363), .Y(n3087) );
OAI22X1TS U5540 ( .A0(n3085), .A1(n3155), .B0(n3087), .B1(n3422), .Y(n3100)
);
XNOR2X1TS U5541 ( .A(n753), .B(n3167), .Y(n3092) );
OAI22X1TS U5542 ( .A0(n3086), .A1(n3361), .B0(n3092), .B1(n3378), .Y(n3099)
);
XNOR2X1TS U5543 ( .A(n3278), .B(n3363), .Y(n3106) );
OAI22X1TS U5544 ( .A0(n3087), .A1(n3424), .B0(n3106), .B1(n3422), .Y(n3111)
);
INVX2TS U5545 ( .A(n920), .Y(n3088) );
NOR2X1TS U5546 ( .A(n3088), .B(n3157), .Y(n3093) );
OAI22X1TS U5547 ( .A0(n3090), .A1(n3331), .B0(n3089), .B1(n3107), .Y(n3104)
);
INVX2TS U5548 ( .A(n3410), .Y(n3091) );
NOR2X2TS U5549 ( .A(n3091), .B(n3157), .Y(n3116) );
INVX2TS U5550 ( .A(n3116), .Y(n3103) );
CMPR32X2TS U5551 ( .A(n3095), .B(n3094), .C(n3093), .CO(n3110), .S(n3141) );
CMPR32X2TS U5552 ( .A(n3098), .B(n3097), .C(n3096), .CO(n3140), .S(n3143) );
CMPR32X2TS U5553 ( .A(n3104), .B(n3103), .C(n3102), .CO(n3114), .S(n3109) );
XNOR2X1TS U5554 ( .A(n853), .B(n3358), .Y(n3119) );
OAI22X1TS U5555 ( .A0(n3105), .A1(n3361), .B0(n3119), .B1(n3378), .Y(n3124)
);
OAI22X1TS U5556 ( .A0(n3106), .A1(n3155), .B0(n3121), .B1(n3422), .Y(n3123)
);
INVX2TS U5557 ( .A(n918), .Y(n3108) );
NOR2X1TS U5558 ( .A(n3108), .B(n3157), .Y(n3115) );
CMPR32X2TS U5559 ( .A(n3111), .B(n3110), .C(n3109), .CO(n3112), .S(n3149) );
NOR2X4TS U5560 ( .A(n3562), .B(n3561), .Y(n7300) );
OAI22X1TS U5561 ( .A0(n3119), .A1(n3361), .B0(n3118), .B1(n3129), .Y(n3132)
);
INVX2TS U5562 ( .A(n912), .Y(n3120) );
INVX2TS U5563 ( .A(n3160), .Y(n3131) );
CMPR32X2TS U5564 ( .A(n3124), .B(n3123), .C(n3122), .CO(n3125), .S(n3113) );
XNOR2X1TS U5565 ( .A(n853), .B(Op_MX[26]), .Y(n3156) );
OAI22X1TS U5566 ( .A0(n3128), .A1(n3155), .B0(n3156), .B1(n3422), .Y(n3153)
);
NOR2X1TS U5567 ( .A(n752), .B(n3157), .Y(n3159) );
CMPR32X2TS U5568 ( .A(n3138), .B(n3137), .C(n3136), .CO(n3147), .S(n3142) );
CMPR32X2TS U5569 ( .A(n3141), .B(n3140), .C(n3139), .CO(n3148), .S(n3146) );
CMPR32X2TS U5570 ( .A(n3144), .B(n3143), .C(n3142), .CO(n3145), .S(n3134) );
NOR2X4TS U5571 ( .A(n3558), .B(n3557), .Y(n3923) );
CMPR32X2TS U5572 ( .A(n3150), .B(n3149), .C(n3148), .CO(n3562), .S(n3559) );
NOR2X4TS U5573 ( .A(n3560), .B(n3559), .Y(n3928) );
CMPR32X2TS U5574 ( .A(n3153), .B(n3152), .C(n3151), .CO(n3574), .S(n3565) );
OAI22X1TS U5575 ( .A0(n3156), .A1(n3155), .B0(n3154), .B1(n971), .Y(n3581)
);
INVX2TS U5576 ( .A(n909), .Y(n3158) );
NOR2X1TS U5577 ( .A(n3158), .B(n3157), .Y(n3585) );
INVX2TS U5578 ( .A(n3585), .Y(n3580) );
CMPR32X2TS U5579 ( .A(n3161), .B(n3160), .C(n3159), .CO(n3579), .S(n3152) );
NOR2X2TS U5580 ( .A(n3574), .B(n3573), .Y(n3597) );
NOR2X2TS U5581 ( .A(n3592), .B(n3597), .Y(n3556) );
INVX2TS U5582 ( .A(n3165), .Y(n3166) );
NOR2X2TS U5583 ( .A(n3166), .B(n971), .Y(n3299) );
INVX2TS U5584 ( .A(n3299), .Y(n3254) );
OAI22X1TS U5585 ( .A0(n3169), .A1(n3424), .B0(n3219), .B1(n3365), .Y(n3252)
);
CMPR32X2TS U5586 ( .A(n3172), .B(n3171), .C(n3170), .CO(n3214), .S(n3175) );
XNOR2X1TS U5587 ( .A(n3176), .B(n3329), .Y(n3225) );
OAI22X1TS U5588 ( .A0(n3177), .A1(n3407), .B0(n3225), .B1(n3333), .Y(n3259)
);
CMPR32X2TS U5589 ( .A(n3183), .B(n3182), .C(n3181), .CO(n3257), .S(n3171) );
ADDFHX2TS U5590 ( .A(n3186), .B(n3185), .CI(n3184), .CO(n3237), .S(n3174) );
XNOR2X1TS U5591 ( .A(n914), .B(n3230), .Y(n3232) );
OAI22X1TS U5592 ( .A0(n3232), .A1(n3188), .B0(n3187), .B1(n3231), .Y(n3235)
);
XNOR2X1TS U5593 ( .A(n3287), .B(n3409), .Y(n3251) );
OAI22X1TS U5594 ( .A0(n3189), .A1(n3250), .B0(n3251), .B1(n3411), .Y(n3234)
);
OAI22X1TS U5595 ( .A0(n3191), .A1(n933), .B0(n3229), .B1(n3228), .Y(n3233)
);
ADDFX2TS U5596 ( .A(n3197), .B(n3196), .CI(n3195), .CO(n3241), .S(n3193) );
XNOR2X1TS U5597 ( .A(n3278), .B(n3275), .Y(n3248) );
OAI22X1TS U5598 ( .A0(n3202), .A1(n3201), .B0(n3248), .B1(n3344), .Y(n3247)
);
XNOR2X1TS U5599 ( .A(n3384), .B(n3348), .Y(n3256) );
OAI22X1TS U5600 ( .A0(n3203), .A1(n3350), .B0(n3256), .B1(n3430), .Y(n3246)
);
XNOR2X1TS U5601 ( .A(n919), .B(n3346), .Y(n3255) );
OAI22X1TS U5602 ( .A0(n3204), .A1(n3279), .B0(n3255), .B1(n3401), .Y(n3245)
);
CMPR32X2TS U5603 ( .A(n3207), .B(n3206), .C(n3205), .CO(n3242), .S(n3209) );
ADDFHX4TS U5604 ( .A(n3213), .B(n3212), .CI(n3211), .CO(n3515), .S(n2929) );
XNOR2X1TS U5605 ( .A(n3217), .B(n3358), .Y(n3284) );
XNOR2X1TS U5606 ( .A(n916), .B(n4730), .Y(n3286) );
OAI22X1TS U5607 ( .A0(n3219), .A1(n3424), .B0(n3286), .B1(n3365), .Y(n3296)
);
INVX2TS U5608 ( .A(n3223), .Y(n3224) );
NOR2X1TS U5609 ( .A(n3224), .B(n971), .Y(n3298) );
XNOR2X1TS U5610 ( .A(n3359), .B(n3329), .Y(n3304) );
OAI22X1TS U5611 ( .A0(n3225), .A1(n3331), .B0(n3304), .B1(n3405), .Y(n3307)
);
OAI22X1TS U5612 ( .A0(n3229), .A1(n2839), .B0(n3302), .B1(n3228), .Y(n3306)
);
OAI22X1TS U5613 ( .A0(n3288), .A1(n3417), .B0(n3232), .B1(n3231), .Y(n3305)
);
CMPR32X2TS U5614 ( .A(n3235), .B(n3234), .C(n3233), .CO(n3311), .S(n3236) );
CMPR32X2TS U5615 ( .A(n3244), .B(n3243), .C(n3242), .CO(n3271), .S(n3240) );
XNOR2X1TS U5616 ( .A(n753), .B(n3275), .Y(n3277) );
OAI22X1TS U5617 ( .A0(n3248), .A1(n3428), .B0(n3277), .B1(n3344), .Y(n3294)
);
OAI22X1TS U5618 ( .A0(n3251), .A1(n3250), .B0(n3289), .B1(n3411), .Y(n3293)
);
OAI22X1TS U5619 ( .A0(n3255), .A1(n890), .B0(n3280), .B1(n3401), .Y(n3310)
);
XNOR2X1TS U5620 ( .A(n920), .B(n3348), .Y(n3291) );
OAI22X1TS U5621 ( .A0(n3256), .A1(n3350), .B0(n3291), .B1(n3430), .Y(n3309)
);
CMPR32X2TS U5622 ( .A(n3259), .B(n3258), .C(n3257), .CO(n3308), .S(n3238) );
CMPR32X2TS U5623 ( .A(n3268), .B(n3267), .C(n3266), .CO(n3319), .S(n3316) );
XNOR2X1TS U5624 ( .A(n3276), .B(n3275), .Y(n3345) );
NOR2X2TS U5625 ( .A(n3282), .B(n971), .Y(n3381) );
INVX2TS U5626 ( .A(n3381), .Y(n3354) );
XNOR2X1TS U5627 ( .A(n3358), .B(n3283), .Y(n3362) );
OAI22X1TS U5628 ( .A0(n3284), .A1(n930), .B0(n3362), .B1(n3378), .Y(n3353)
);
OAI22X1TS U5629 ( .A0(n3286), .A1(n3424), .B0(n3366), .B1(n3365), .Y(n3352)
);
XNOR2X1TS U5630 ( .A(n3287), .B(n3383), .Y(n3337) );
OAI22X1TS U5631 ( .A0(n3288), .A1(n3336), .B0(n3337), .B1(n3335), .Y(n3328)
);
XNOR2X1TS U5632 ( .A(n919), .B(n3348), .Y(n3351) );
OAI22X1TS U5633 ( .A0(n3291), .A1(n3350), .B0(n3351), .B1(n3290), .Y(n3326)
);
CMPR32X2TS U5634 ( .A(n3294), .B(n3293), .C(n3292), .CO(n3320), .S(n3273) );
CMPR32X2TS U5635 ( .A(n3297), .B(n3296), .C(n3295), .CO(n3342), .S(n3313) );
OAI22X1TS U5636 ( .A0(n3302), .A1(n2839), .B0(n3301), .B1(n3367), .Y(n3356)
);
CMPR32X2TS U5637 ( .A(n3307), .B(n3306), .C(n3305), .CO(n3340), .S(n3312) );
CMPR32X2TS U5638 ( .A(n3310), .B(n3309), .C(n3308), .CO(n3371), .S(n3272) );
ADDFHX2TS U5639 ( .A(n3313), .B(n3312), .CI(n3311), .CO(n3370), .S(n3267) );
ADDFHX4TS U5640 ( .A(n3319), .B(n3318), .CI(n3317), .CO(n3522), .S(n3520) );
CMPR32X2TS U5641 ( .A(n3322), .B(n3321), .C(n3320), .CO(n3502), .S(n3374) );
CMPR32X2TS U5642 ( .A(n3325), .B(n3324), .C(n3323), .CO(n3490), .S(n3322) );
XNOR2X1TS U5643 ( .A(n921), .B(n3329), .Y(n3408) );
OAI22X1TS U5644 ( .A0(n3408), .A1(n3333), .B0(n3332), .B1(n931), .Y(n3400)
);
OAI22X1TS U5645 ( .A0(n3337), .A1(n3336), .B0(n3385), .B1(n3335), .Y(n3399)
);
XNOR2X1TS U5646 ( .A(n3338), .B(n3409), .Y(n3412) );
OAI22X1TS U5647 ( .A0(n3339), .A1(n3415), .B0(n3412), .B1(n3413), .Y(n3398)
);
OAI22X1TS U5648 ( .A0(n3345), .A1(n934), .B0(n3429), .B1(n3344), .Y(n3397)
);
XNOR2X1TS U5649 ( .A(n3349), .B(n3348), .Y(n3433) );
OAI22X1TS U5650 ( .A0(n3351), .A1(n3350), .B0(n3433), .B1(n3430), .Y(n3395)
);
ADDFHX2TS U5651 ( .A(n3354), .B(n3353), .CI(n3352), .CO(n3478), .S(n3323) );
XNOR2X1TS U5652 ( .A(n3359), .B(n3358), .Y(n3377) );
XNOR2X1TS U5653 ( .A(n3364), .B(n3363), .Y(n3425) );
OAI22X1TS U5654 ( .A0(n3366), .A1(n3424), .B0(n3425), .B1(n3365), .Y(n3435)
);
INVX2TS U5655 ( .A(n3368), .Y(n3369) );
NOR2X8TS U5656 ( .A(n3522), .B(n3521), .Y(n3913) );
OAI22X1TS U5657 ( .A0(n3379), .A1(n3378), .B0(n3377), .B1(n3376), .Y(n3394)
);
OAI22X1TS U5658 ( .A0(n3385), .A1(n3419), .B0(n3420), .B1(n3417), .Y(n3392)
);
CMPR32X2TS U5659 ( .A(n3388), .B(n3387), .C(n3386), .CO(n3447), .S(n3444) );
CMPR32X2TS U5660 ( .A(n3391), .B(n3390), .C(n3389), .CO(n3446), .S(n3443) );
CMPR32X2TS U5661 ( .A(n3400), .B(n3399), .C(n3398), .CO(n3485), .S(n3488) );
OAI22X1TS U5662 ( .A0(n3404), .A1(n889), .B0(n3402), .B1(n3401), .Y(n3475)
);
OAI22X1TS U5663 ( .A0(n3408), .A1(n3407), .B0(n3406), .B1(n3405), .Y(n3474)
);
XNOR2X1TS U5664 ( .A(n919), .B(n3409), .Y(n3416) );
OAI22X1TS U5665 ( .A0(n3412), .A1(n935), .B0(n3416), .B1(n3411), .Y(n3473)
);
OAI22X1TS U5666 ( .A0(n3416), .A1(n935), .B0(n3414), .B1(n3413), .Y(n3457)
);
OAI22X1TS U5667 ( .A0(n3420), .A1(n3419), .B0(n3418), .B1(n3417), .Y(n3456)
);
INVX2TS U5668 ( .A(n3421), .Y(n3439) );
OAI22X1TS U5669 ( .A0(n3425), .A1(n3424), .B0(n3423), .B1(n3422), .Y(n3438)
);
OAI22X1TS U5670 ( .A0(n3429), .A1(n3428), .B0(n3427), .B1(n3426), .Y(n3437)
);
OAI22X1TS U5671 ( .A0(n3433), .A1(n3432), .B0(n3431), .B1(n3430), .Y(n3481)
);
ADDFHX2TS U5672 ( .A(n3436), .B(n3435), .CI(n3434), .CO(n3480), .S(n3476) );
CMPR32X2TS U5673 ( .A(n3439), .B(n3438), .C(n3437), .CO(n3455), .S(n3479) );
ADDFHX1TS U5674 ( .A(n3442), .B(n3441), .CI(n3440), .CO(n3495), .S(n3482) );
ADDFX2TS U5675 ( .A(n3445), .B(n3444), .CI(n3443), .CO(n3466), .S(n3484) );
CMPR32X2TS U5676 ( .A(n3448), .B(n3447), .C(n3446), .CO(n3459), .S(n3465) );
CMPR32X2TS U5677 ( .A(n3451), .B(n3450), .C(n3449), .CO(n2971), .S(n3463) );
CMPR32X2TS U5678 ( .A(n3463), .B(n3462), .C(n3461), .CO(n3468), .S(n3464) );
CMPR32X2TS U5679 ( .A(n3475), .B(n3474), .C(n3473), .CO(n3442), .S(n3493) );
ADDFHX2TS U5680 ( .A(n3484), .B(n3483), .CI(n3482), .CO(n3496), .S(n3513) );
CMPR32X2TS U5681 ( .A(n3487), .B(n3486), .C(n3485), .CO(n3483), .S(n3508) );
CMPR32X2TS U5682 ( .A(n3490), .B(n3489), .C(n3488), .CO(n3507), .S(n3501) );
CMPR32X2TS U5683 ( .A(n3493), .B(n3492), .C(n3491), .CO(n3514), .S(n3506) );
ADDFHX2TS U5684 ( .A(n3508), .B(n3507), .CI(n3506), .CO(n3512), .S(n3509) );
ADDFHX2TS U5685 ( .A(n3514), .B(n3513), .CI(n3512), .CO(n3530), .S(n3527) );
INVX16TS U5686 ( .A(n1023), .Y(n7323) );
NAND2X4TS U5687 ( .A(n3518), .B(n3517), .Y(n7240) );
OAI21X4TS U5688 ( .A0(n7239), .A1(n7237), .B0(n7240), .Y(n3909) );
NAND2X4TS U5689 ( .A(n3520), .B(n3519), .Y(n7339) );
NAND2X4TS U5690 ( .A(n3522), .B(n3521), .Y(n3914) );
OAI21X4TS U5691 ( .A0(n3913), .A1(n7339), .B0(n3914), .Y(n3523) );
AOI21X4TS U5692 ( .A0(n3909), .A1(n3524), .B0(n3523), .Y(n5108) );
OAI21X4TS U5693 ( .A0(n7410), .A1(n7405), .B0(n7411), .Y(n7344) );
NAND2X4TS U5694 ( .A(n3530), .B(n3529), .Y(n7418) );
NAND2X4TS U5695 ( .A(n3532), .B(n3531), .Y(n7419) );
NAND2X2TS U5696 ( .A(n3534), .B(n3533), .Y(n7431) );
OA21X4TS U5697 ( .A0(n3535), .A1(n7419), .B0(n7431), .Y(n3536) );
AOI21X4TS U5698 ( .A0(n7344), .A1(n3539), .B0(n3538), .Y(n3540) );
OAI21X4TS U5699 ( .A0(n5108), .A1(n3541), .B0(n3540), .Y(n3542) );
BUFX20TS U5700 ( .A(n3542), .Y(n7325) );
NAND2X2TS U5701 ( .A(n3546), .B(n3545), .Y(n7328) );
AOI21X4TS U5702 ( .A0(n7324), .A1(n791), .B0(n3547), .Y(n7316) );
NAND2X2TS U5703 ( .A(n3549), .B(n3548), .Y(n7322) );
INVX2TS U5704 ( .A(n7322), .Y(n3553) );
INVX2TS U5705 ( .A(n4695), .Y(n3552) );
AOI21X4TS U5706 ( .A0(n3553), .A1(n4696), .B0(n3552), .Y(n3554) );
OAI21X4TS U5707 ( .A0(n7316), .A1(n3555), .B0(n3554), .Y(n4825) );
BUFX3TS U5708 ( .A(n4825), .Y(n3917) );
NAND2X2TS U5709 ( .A(n3558), .B(n3557), .Y(n3922) );
NAND2X2TS U5710 ( .A(n3560), .B(n3559), .Y(n3929) );
NAND2X2TS U5711 ( .A(n3562), .B(n3561), .Y(n7301) );
INVX2TS U5712 ( .A(n7312), .Y(n3568) );
NAND2X1TS U5713 ( .A(n3566), .B(n3565), .Y(n4831) );
INVX2TS U5714 ( .A(n4831), .Y(n3567) );
NAND2X1TS U5715 ( .A(n3574), .B(n3573), .Y(n3598) );
AOI21X4TS U5716 ( .A0(n897), .A1(n1021), .B0(n3576), .Y(n3577) );
CMPR32X2TS U5717 ( .A(n3581), .B(n3580), .C(n3579), .CO(n3588), .S(n3573) );
NOR2X1TS U5718 ( .A(n3584), .B(n3583), .Y(n3586) );
NAND2X1TS U5719 ( .A(n3588), .B(n3587), .Y(n3589) );
XOR2X4TS U5720 ( .A(n3590), .B(n3589), .Y(Sgf_operation_ODD1_middle_N55) );
NOR2X2TS U5721 ( .A(n7292), .B(n3592), .Y(n3594) );
INVX2TS U5722 ( .A(n3597), .Y(n3599) );
XOR2X4TS U5723 ( .A(n3600), .B(n968), .Y(Sgf_operation_ODD1_middle_N54) );
NAND2X1TS U5724 ( .A(n3646), .B(n3647), .Y(n3603) );
NAND2X2TS U5725 ( .A(n1002), .B(n3601), .Y(n3602) );
AOI21X1TS U5726 ( .A0(n5936), .A1(n903), .B0(n3604), .Y(n3605) );
OAI21X1TS U5727 ( .A0(n1001), .A1(n6061), .B0(n3605), .Y(n3631) );
INVX4TS U5728 ( .A(n3606), .Y(n3682) );
AOI21X4TS U5729 ( .A0(n3682), .A1(n3608), .B0(n3607), .Y(n3705) );
INVX2TS U5730 ( .A(n3704), .Y(n3609) );
NAND2X1TS U5731 ( .A(n3609), .B(n3703), .Y(n3610) );
XNOR2X4TS U5732 ( .A(Op_MX[47]), .B(Op_MX[48]), .Y(n3614) );
XOR2X4TS U5733 ( .A(n3866), .B(Op_MX[49]), .Y(n3615) );
NAND2BX4TS U5734 ( .AN(n3614), .B(n3615), .Y(n4965) );
BUFX3TS U5735 ( .A(Op_MY[33]), .Y(n5856) );
INVX2TS U5736 ( .A(n3612), .Y(n3613) );
BUFX8TS U5737 ( .A(n4967), .Y(n6064) );
BUFX3TS U5738 ( .A(n852), .Y(n5758) );
NAND3X4TS U5739 ( .A(n3615), .B(n3614), .C(n3613), .Y(n4702) );
INVX8TS U5740 ( .A(n4702), .Y(n6063) );
AOI222X1TS U5741 ( .A0(n881), .A1(n5856), .B0(n6064), .B1(n5758), .C0(n6063),
.C1(n849), .Y(n3616) );
OAI21X2TS U5742 ( .A0(n4999), .A1(n3723), .B0(n3724), .Y(n3622) );
NAND2X1TS U5743 ( .A(n3620), .B(n3619), .Y(n3621) );
XNOR2X4TS U5744 ( .A(n3622), .B(n3621), .Y(n3623) );
XNOR2X4TS U5745 ( .A(Op_MX[44]), .B(Op_MX[45]), .Y(n3625) );
NAND2BX4TS U5746 ( .AN(n3625), .B(n3626), .Y(n5491) );
NOR2X8TS U5747 ( .A(n3626), .B(n3625), .Y(n5840) );
XNOR2X2TS U5748 ( .A(Op_MX[45]), .B(Op_MX[46]), .Y(n3624) );
NOR2BX4TS U5749 ( .AN(n3625), .B(n3624), .Y(n5494) );
BUFX3TS U5750 ( .A(Op_MY[34]), .Y(n5999) );
AOI222X1TS U5751 ( .A0(n5845), .A1(n837), .B0(n6031), .B1(n831), .C0(n5844),
.C1(n5999), .Y(n3627) );
OAI21X1TS U5752 ( .A0(n5905), .A1(n6035), .B0(n3627), .Y(n3628) );
ADDFX2TS U5753 ( .A(n3631), .B(n3630), .CI(n3629), .CO(mult_x_23_n798), .S(
mult_x_23_n799) );
BUFX3TS U5754 ( .A(n5766), .Y(n5807) );
NAND2X1TS U5755 ( .A(n870), .B(n824), .Y(n3633) );
OAI21X1TS U5756 ( .A0(n5807), .A1(n6053), .B0(n3633), .Y(
Sgf_operation_ODD1_left_N0) );
NAND2BX4TS U5757 ( .AN(n3719), .B(n3720), .Y(n5665) );
NOR2X4TS U5758 ( .A(n3720), .B(n3719), .Y(n3717) );
CLKINVX1TS U5759 ( .A(n793), .Y(n3635) );
XNOR2X4TS U5760 ( .A(Op_MX[29]), .B(Op_MX[30]), .Y(n3638) );
NOR2X4TS U5761 ( .A(n3639), .B(n3638), .Y(n5748) );
NOR2BX4TS U5762 ( .AN(n3638), .B(n3637), .Y(n5712) );
BUFX4TS U5763 ( .A(n5712), .Y(n5759) );
BUFX3TS U5764 ( .A(n8374), .Y(n6055) );
BUFX3TS U5765 ( .A(n903), .Y(n6054) );
AOI222X1TS U5766 ( .A0(n5742), .A1(n8375), .B0(n5759), .B1(n6055), .C0(n5751), .C1(n6054), .Y(n3640) );
OR2X2TS U5767 ( .A(n903), .B(n824), .Y(n3642) );
NAND2X4TS U5768 ( .A(n3642), .B(n3647), .Y(n6062) );
OAI21X1TS U5769 ( .A0(n6062), .A1(n5861), .B0(n795), .Y(n3643) );
XOR2X1TS U5770 ( .A(n3643), .B(n5763), .Y(n3686) );
NAND2X1TS U5771 ( .A(n5748), .B(n4966), .Y(n3644) );
NAND2X2TS U5772 ( .A(n996), .B(n3646), .Y(n3648) );
XOR2X2TS U5773 ( .A(n3648), .B(n3647), .Y(n3649) );
BUFX3TS U5774 ( .A(n8374), .Y(n5843) );
BUFX3TS U5775 ( .A(n903), .Y(n5839) );
INVX2TS U5776 ( .A(n803), .Y(n5213) );
AOI222X1TS U5777 ( .A0(n5742), .A1(n5843), .B0(n5759), .B1(n5839), .C0(n5751), .C1(n5213), .Y(n3650) );
OAI21X1TS U5778 ( .A0(n5437), .A1(n5861), .B0(n3650), .Y(n3651) );
XOR2X1TS U5779 ( .A(n3651), .B(n5763), .Y(n3665) );
BUFX3TS U5780 ( .A(n3669), .Y(n6079) );
AOI222X1TS U5781 ( .A0(n871), .A1(n5856), .B0(n6079), .B1(n5758), .C0(n5964),
.C1(n849), .Y(n3653) );
OAI21X1TS U5782 ( .A0(n5762), .A1(n5807), .B0(n3653), .Y(n3654) );
NOR2X4TS U5783 ( .A(n3692), .B(n3691), .Y(n5375) );
INVX2TS U5784 ( .A(n3655), .Y(n3680) );
INVX2TS U5785 ( .A(n3679), .Y(n3656) );
AOI21X2TS U5786 ( .A0(n3682), .A1(n3680), .B0(n3656), .Y(n3661) );
INVX2TS U5787 ( .A(n3657), .Y(n3659) );
XNOR2X4TS U5788 ( .A(n3661), .B(n3660), .Y(n5931) );
BUFX3TS U5789 ( .A(n5766), .Y(n6042) );
BUFX3TS U5790 ( .A(n3662), .Y(n6081) );
BUFX3TS U5791 ( .A(n852), .Y(n5996) );
AOI222X1TS U5792 ( .A0(n6081), .A1(n5996), .B0(n6079), .B1(n8376), .C0(n5964), .C1(n851), .Y(n3663) );
OAI21X1TS U5793 ( .A0(n5931), .A1(n6042), .B0(n3663), .Y(n3664) );
XOR2X1TS U5794 ( .A(n3664), .B(n5819), .Y(n3690) );
CMPR22X2TS U5795 ( .A(n3666), .B(n3665), .CO(n3700), .S(n3689) );
NOR2X2TS U5796 ( .A(n3690), .B(n3689), .Y(n5380) );
NOR2X2TS U5797 ( .A(n5375), .B(n5380), .Y(n3694) );
AOI222X1TS U5798 ( .A0(n6081), .A1(n5843), .B0(n6079), .B1(n5839), .C0(n5964), .C1(n5213), .Y(n3667) );
OAI21X1TS U5799 ( .A0(n5437), .A1(n6042), .B0(n3667), .Y(n3668) );
INVX2TS U5800 ( .A(n1032), .Y(n5804) );
AOI22X1TS U5801 ( .A0(n870), .A1(n903), .B0(n873), .B1(n4966), .Y(n3670) );
OAI21X1TS U5802 ( .A0(n6062), .A1(n6042), .B0(n3670), .Y(n3671) );
AOI222X1TS U5803 ( .A0(n6081), .A1(n8375), .B0(n6079), .B1(n6055), .C0(n5964), .C1(n6054), .Y(n3673) );
OAI21X1TS U5804 ( .A0(n1001), .A1(n6042), .B0(n3673), .Y(n3674) );
XOR2X1TS U5805 ( .A(n3674), .B(n5804), .Y(n3677) );
NAND2X1TS U5806 ( .A(n3677), .B(n3676), .Y(n5390) );
INVX2TS U5807 ( .A(n5390), .Y(n3678) );
AOI21X2TS U5808 ( .A0(n5391), .A1(n786), .B0(n3678), .Y(n5389) );
NAND2X1TS U5809 ( .A(n3680), .B(n3679), .Y(n3681) );
CLKXOR2X4TS U5810 ( .A(n3682), .B(n3681), .Y(n6068) );
BUFX3TS U5811 ( .A(n851), .Y(n8375) );
OAI21X1TS U5812 ( .A0(n6068), .A1(n5807), .B0(n3683), .Y(n3684) );
XOR2X1TS U5813 ( .A(n3684), .B(n5804), .Y(n3688) );
CMPR22X2TS U5814 ( .A(n3686), .B(n3685), .CO(n3666), .S(n3687) );
NOR2X1TS U5815 ( .A(n3688), .B(n3687), .Y(n5385) );
NAND2X1TS U5816 ( .A(n3688), .B(n3687), .Y(n5386) );
OAI21X4TS U5817 ( .A0(n5389), .A1(n5385), .B0(n5386), .Y(n5374) );
NAND2X1TS U5818 ( .A(n3690), .B(n3689), .Y(n5381) );
NAND2X2TS U5819 ( .A(n3692), .B(n3691), .Y(n5376) );
OAI21X2TS U5820 ( .A0(n5375), .A1(n5381), .B0(n5376), .Y(n3693) );
AOI21X4TS U5821 ( .A0(n3694), .A1(n5374), .B0(n3693), .Y(n5813) );
XNOR2X2TS U5822 ( .A(Op_MX[33]), .B(Op_MX[34]), .Y(n3718) );
NOR2BX4TS U5823 ( .AN(n3719), .B(n3718), .Y(n5668) );
OAI21X1TS U5824 ( .A0(n6062), .A1(n5665), .B0(n3695), .Y(n3696) );
ADDHXLTS U5825 ( .A(n7492), .B(n3697), .CO(n3715), .S(n3702) );
AOI222X1TS U5826 ( .A0(n5742), .A1(n849), .B0(n5759), .B1(n830), .C0(n5857),
.C1(n5843), .Y(n3698) );
ADDFHX2TS U5827 ( .A(n894), .B(n3701), .CI(n3700), .CO(n3731), .S(n3692) );
INVX2TS U5828 ( .A(n3706), .Y(n3708) );
XOR2X4TS U5829 ( .A(n3710), .B(n3709), .Y(n6001) );
BUFX3TS U5830 ( .A(Op_MY[33]), .Y(n5998) );
AOI222X1TS U5831 ( .A0(n871), .A1(n5999), .B0(n873), .B1(n5998), .C0(n5964),
.C1(n5996), .Y(n3711) );
OAI21X1TS U5832 ( .A0(n6001), .A1(n5807), .B0(n3711), .Y(n3712) );
XOR2X1TS U5833 ( .A(n3712), .B(n5819), .Y(n3713) );
NAND2X2TS U5834 ( .A(n3714), .B(n3713), .Y(n5810) );
OAI21X4TS U5835 ( .A0(n5813), .A1(n5809), .B0(n5810), .Y(n5817) );
AND3X4TS U5836 ( .A(n3720), .B(n3719), .C(n3718), .Y(n5974) );
AOI222X1TS U5837 ( .A0(n5929), .A1(n855), .B0(n5975), .B1(n5839), .C0(n5928),
.C1(n5213), .Y(n3721) );
INVX2TS U5838 ( .A(n3723), .Y(n3725) );
NAND2X2TS U5839 ( .A(n3725), .B(n3724), .Y(n3726) );
BUFX3TS U5840 ( .A(Op_MY[35]), .Y(n8385) );
BUFX3TS U5841 ( .A(Op_MY[34]), .Y(n5858) );
AOI222X1TS U5842 ( .A0(n871), .A1(n832), .B0(n873), .B1(n5858), .C0(n5964),
.C1(n5892), .Y(n3727) );
XOR2X1TS U5843 ( .A(n3728), .B(n5819), .Y(n3738) );
AOI222X1TS U5844 ( .A0(n5742), .A1(n5996), .B0(n5759), .B1(n8376), .C0(n5857), .C1(n830), .Y(n3729) );
OAI21X1TS U5845 ( .A0(n5931), .A1(n5761), .B0(n3729), .Y(n3730) );
XOR2X1TS U5846 ( .A(n3730), .B(n5763), .Y(n3737) );
INVX2TS U5847 ( .A(n5814), .Y(n3736) );
AOI21X4TS U5848 ( .A0(n5817), .A1(n5815), .B0(n3736), .Y(n5364) );
OR2X4TS U5849 ( .A(mult_x_23_n948), .B(mult_x_23_n952), .Y(n5366) );
CMPR32X2TS U5850 ( .A(n3739), .B(n3738), .C(n3737), .CO(n3740), .S(n3735) );
OR2X2TS U5851 ( .A(mult_x_23_n953), .B(n3740), .Y(n5371) );
NAND2X2TS U5852 ( .A(n5366), .B(n5371), .Y(n3743) );
NAND2X2TS U5853 ( .A(mult_x_23_n953), .B(n3740), .Y(n5370) );
INVX2TS U5854 ( .A(n5370), .Y(n5365) );
INVX2TS U5855 ( .A(n5367), .Y(n3741) );
OAI21X4TS U5856 ( .A0(n5364), .A1(n3743), .B0(n3742), .Y(n5358) );
NOR2X4TS U5857 ( .A(mult_x_23_n943), .B(mult_x_23_n947), .Y(n5951) );
NAND2X2TS U5858 ( .A(mult_x_23_n943), .B(mult_x_23_n947), .Y(n5952) );
INVX4TS U5859 ( .A(n3746), .Y(n5352) );
NAND2X2TS U5860 ( .A(n780), .B(n5352), .Y(n3749) );
NAND2X2TS U5861 ( .A(mult_x_23_n929), .B(mult_x_23_n935), .Y(n5355) );
NAND2X2TS U5862 ( .A(mult_x_23_n922), .B(mult_x_23_n928), .Y(n5351) );
INVX2TS U5863 ( .A(n5351), .Y(n3747) );
OAI21X4TS U5864 ( .A0(n5349), .A1(n3749), .B0(n3748), .Y(n5343) );
NOR2X4TS U5865 ( .A(mult_x_23_n906), .B(mult_x_23_n913), .Y(n5344) );
NOR2X4TS U5866 ( .A(mult_x_23_n914), .B(mult_x_23_n921), .Y(n5946) );
NOR2X2TS U5867 ( .A(n5344), .B(n5946), .Y(n3751) );
OAI21X2TS U5868 ( .A0(n5344), .A1(n5947), .B0(n5345), .Y(n3750) );
AOI21X4TS U5869 ( .A0(n5343), .A1(n3751), .B0(n3750), .Y(n5332) );
NOR2X4TS U5870 ( .A(n5335), .B(n5333), .Y(n5988) );
NAND2X2TS U5871 ( .A(n5988), .B(n787), .Y(n3754) );
NAND2X4TS U5872 ( .A(mult_x_23_n898), .B(mult_x_23_n905), .Y(n5340) );
NAND2X2TS U5873 ( .A(mult_x_23_n888), .B(mult_x_23_n897), .Y(n5336) );
INVX2TS U5874 ( .A(n5990), .Y(n3752) );
OAI21X4TS U5875 ( .A0(n5332), .A1(n3754), .B0(n3753), .Y(n5316) );
NOR2X4TS U5876 ( .A(n5318), .B(n5319), .Y(n3758) );
NAND2X4TS U5877 ( .A(mult_x_23_n868), .B(mult_x_23_n877), .Y(n5328) );
NAND2X2TS U5878 ( .A(mult_x_23_n857), .B(mult_x_23_n867), .Y(n5325) );
INVX2TS U5879 ( .A(n5325), .Y(n3755) );
AOI21X4TS U5880 ( .A0(n3756), .A1(n1008), .B0(n3755), .Y(n5317) );
NAND2X2TS U5881 ( .A(mult_x_23_n846), .B(mult_x_23_n856), .Y(n5320) );
OAI21X4TS U5882 ( .A0(n5317), .A1(n5319), .B0(n5320), .Y(n3757) );
AOI21X4TS U5883 ( .A0(n5316), .A1(n3758), .B0(n3757), .Y(n5289) );
NOR2X6TS U5884 ( .A(n5300), .B(n5293), .Y(n3760) );
NAND2X4TS U5885 ( .A(n3760), .B(n5299), .Y(n3762) );
OAI21X4TS U5886 ( .A0(n5307), .A1(n5312), .B0(n5308), .Y(n5298) );
NAND2X2TS U5887 ( .A(mult_x_23_n802), .B(mult_x_23_n812), .Y(n5294) );
AOI21X4TS U5888 ( .A0(n5298), .A1(n3760), .B0(n3759), .Y(n3761) );
OAI21X4TS U5889 ( .A0(n5289), .A1(n3762), .B0(n3761), .Y(n4766) );
NOR2X4TS U5890 ( .A(mult_x_23_n718), .B(mult_x_23_n725), .Y(n4782) );
NOR2X4TS U5891 ( .A(mult_x_23_n747), .B(mult_x_23_n757), .Y(n4767) );
NOR2X4TS U5892 ( .A(mult_x_23_n737), .B(mult_x_23_n746), .Y(n4771) );
NOR2X4TS U5893 ( .A(n4767), .B(n4771), .Y(n4789) );
NAND2X2TS U5894 ( .A(mult_x_23_n769), .B(mult_x_23_n779), .Y(n5281) );
AOI21X4TS U5895 ( .A0(n5277), .A1(n3765), .B0(n3764), .Y(n4897) );
NAND2X2TS U5896 ( .A(mult_x_23_n737), .B(mult_x_23_n746), .Y(n4772) );
OA21X4TS U5897 ( .A0(n4897), .A1(n3769), .B0(n3768), .Y(n3770) );
NAND2X8TS U5898 ( .A(n3771), .B(n3770), .Y(n3772) );
NOR2X4TS U5899 ( .A(mult_x_23_n717), .B(mult_x_23_n708), .Y(n4856) );
NAND2X4TS U5900 ( .A(n5196), .B(n3773), .Y(n3776) );
NOR2X6TS U5901 ( .A(mult_x_23_n690), .B(mult_x_23_n697), .Y(n5154) );
NAND2X6TS U5902 ( .A(n4917), .B(n3778), .Y(n5161) );
NOR2X4TS U5903 ( .A(mult_x_23_n670), .B(mult_x_23_n674), .Y(n3837) );
NOR2X2TS U5904 ( .A(n5161), .B(n3837), .Y(n5182) );
INVX2TS U5905 ( .A(n5182), .Y(n3780) );
NAND2X4TS U5906 ( .A(mult_x_23_n708), .B(mult_x_23_n717), .Y(n4855) );
OAI21X4TS U5907 ( .A0(n4855), .A1(n4857), .B0(n4858), .Y(n4918) );
NAND2X2TS U5908 ( .A(mult_x_23_n690), .B(mult_x_23_n697), .Y(n5153) );
NAND2X2TS U5909 ( .A(mult_x_23_n675), .B(mult_x_23_n682), .Y(n5200) );
INVX2TS U5910 ( .A(n5200), .Y(n3774) );
AOI21X4TS U5911 ( .A0(n3773), .A1(n5195), .B0(n3774), .Y(n3775) );
OAI21X4TS U5912 ( .A0(n3776), .A1(n5153), .B0(n3775), .Y(n3777) );
AOI21X4TS U5913 ( .A0(n4918), .A1(n3778), .B0(n3777), .Y(n4946) );
NAND2X2TS U5914 ( .A(mult_x_23_n670), .B(mult_x_23_n674), .Y(n5148) );
OAI21X2TS U5915 ( .A0(n4946), .A1(n3837), .B0(n5148), .Y(n5186) );
INVX2TS U5916 ( .A(n5186), .Y(n3779) );
INVX2TS U5917 ( .A(n3836), .Y(n5185) );
NAND2X2TS U5918 ( .A(mult_x_23_n669), .B(mult_x_23_n663), .Y(n5183) );
XNOR2X4TS U5919 ( .A(Op_MX[38]), .B(Op_MX[39]), .Y(n4654) );
NAND2BX4TS U5920 ( .AN(n4654), .B(n4655), .Y(n5569) );
NOR2X4TS U5921 ( .A(n4655), .B(n4654), .Y(n5095) );
XNOR2X2TS U5922 ( .A(Op_MX[39]), .B(Op_MX[40]), .Y(n4653) );
AOI22X1TS U5923 ( .A0(n5825), .A1(n903), .B0(n5096), .B1(n4966), .Y(n3782)
);
OAI21X1TS U5924 ( .A0(n6062), .A1(n5569), .B0(n3782), .Y(n3783) );
NAND2X2TS U5925 ( .A(n5095), .B(n824), .Y(n3784) );
XNOR2X4TS U5926 ( .A(Op_MX[35]), .B(Op_MX[36]), .Y(n3787) );
XOR2X4TS U5927 ( .A(n7500), .B(Op_MX[37]), .Y(n3788) );
NAND2BX4TS U5928 ( .AN(n3787), .B(n3788), .Y(n5620) );
XNOR2X2TS U5929 ( .A(Op_MX[37]), .B(Op_MX[36]), .Y(n3786) );
NOR2BX4TS U5930 ( .AN(n3787), .B(n3786), .Y(n5650) );
NAND3X4TS U5931 ( .A(n3788), .B(n3787), .C(n3786), .Y(n5877) );
OAI21X1TS U5932 ( .A0(n6068), .A1(n5985), .B0(n3789), .Y(n3790) );
XOR2X1TS U5933 ( .A(n3790), .B(n5663), .Y(n3802) );
ADDHX1TS U5934 ( .A(n7498), .B(n3791), .CO(n5093), .S(n5995) );
AOI222X1TS U5935 ( .A0(n5960), .A1(n830), .B0(n5661), .B1(n6055), .C0(n5660),
.C1(n6054), .Y(n3792) );
OAI21X1TS U5936 ( .A0(n1001), .A1(n5878), .B0(n3792), .Y(n3793) );
XOR2X1TS U5937 ( .A(n3793), .B(n5663), .Y(n5994) );
AOI22X2TS U5938 ( .A0(n5653), .A1(n6054), .B0(n5959), .B1(n4966), .Y(n3794)
);
OAI21X2TS U5939 ( .A0(n6062), .A1(n5620), .B0(n3794), .Y(n3795) );
XOR2X2TS U5940 ( .A(n3795), .B(n5663), .Y(n4761) );
OAI21X2TS U5941 ( .A0(n6053), .A1(n5620), .B0(n3797), .Y(n3798) );
AOI222X1TS U5942 ( .A0(n5960), .A1(n6055), .B0(n5661), .B1(n5839), .C0(n5660), .C1(n5213), .Y(n3799) );
OAI21X1TS U5943 ( .A0(n5437), .A1(n5878), .B0(n3799), .Y(n3800) );
ADDFX2TS U5944 ( .A(n3803), .B(n3802), .CI(n3801), .CO(mult_x_23_n930), .S(
mult_x_23_n931) );
INVX2TS U5945 ( .A(n5111), .Y(n3809) );
NAND2X1TS U5946 ( .A(n5112), .B(n3809), .Y(n3811) );
INVX2TS U5947 ( .A(n3804), .Y(n3805) );
INVX2TS U5948 ( .A(n5118), .Y(n3808) );
AOI21X1TS U5949 ( .A0(n5121), .A1(n3809), .B0(n3808), .Y(n3810) );
INVX2TS U5950 ( .A(n5128), .Y(n5125) );
NOR2X4TS U5951 ( .A(n834), .B(n6959), .Y(n6256) );
NOR2X6TS U5952 ( .A(n6256), .B(n6260), .Y(n6245) );
INVX2TS U5953 ( .A(n6245), .Y(n3814) );
NAND2X2TS U5954 ( .A(n6268), .B(n3824), .Y(n3826) );
INVX2TS U5955 ( .A(n3815), .Y(n3821) );
INVX2TS U5956 ( .A(n3816), .Y(n3820) );
NAND2X4TS U5957 ( .A(n6952), .B(n6484), .Y(n6396) );
NAND2X1TS U5958 ( .A(n6288), .B(n6396), .Y(n3817) );
OAI2BB1X4TS U5959 ( .A0N(n3821), .A1N(n3820), .B0(n3819), .Y(n6269) );
INVX2TS U5960 ( .A(n6244), .Y(n3822) );
NAND2X2TS U5961 ( .A(n6989), .B(n925), .Y(n6249) );
OAI21X4TS U5962 ( .A0(n820), .A1(n3826), .B0(n3825), .Y(n3827) );
XNOR2X4TS U5963 ( .A(n3827), .B(n3813), .Y(n3828) );
XNOR2X4TS U5964 ( .A(Op_MY[23]), .B(Op_MY[24]), .Y(n4742) );
XOR2X4TS U5965 ( .A(Op_MY[26]), .B(Op_MY[25]), .Y(n4743) );
BUFX8TS U5966 ( .A(n6237), .Y(n6925) );
XNOR2X2TS U5967 ( .A(Op_MY[24]), .B(Op_MY[25]), .Y(n3829) );
AND3X6TS U5968 ( .A(n4743), .B(n4742), .C(n3829), .Y(n6920) );
NOR2BX4TS U5969 ( .AN(n4742), .B(n3829), .Y(n6239) );
INVX2TS U5970 ( .A(n3813), .Y(n7001) );
AOI21X1TS U5971 ( .A0(n6920), .A1(n926), .B0(n3830), .Y(n3831) );
XOR2X1TS U5972 ( .A(n3832), .B(n7087), .Y(n5113) );
NOR2X2TS U5973 ( .A(mult_x_24_n694), .B(n3833), .Y(n5117) );
INVX2TS U5974 ( .A(n5117), .Y(n3834) );
NAND2X1TS U5975 ( .A(mult_x_24_n694), .B(n3833), .Y(n5116) );
XOR2X4TS U5976 ( .A(n3835), .B(n974), .Y(Sgf_operation_ODD1_right_N51) );
NAND2X4TS U5977 ( .A(n3884), .B(n5149), .Y(n5163) );
BUFX3TS U5978 ( .A(n4965), .Y(n5470) );
AOI21X1TS U5979 ( .A0(n5863), .A1(n5883), .B0(n865), .Y(n3838) );
OAI21X1TS U5980 ( .A0(n5887), .A1(n5470), .B0(n3838), .Y(n3839) );
XOR2X1TS U5981 ( .A(n3839), .B(n6021), .Y(n3876) );
INVX2TS U5982 ( .A(n3876), .Y(n3857) );
INVX2TS U5983 ( .A(n5453), .Y(n3840) );
NAND2X2TS U5984 ( .A(n3840), .B(n3842), .Y(n3845) );
INVX2TS U5985 ( .A(n5452), .Y(n3843) );
AOI21X2TS U5986 ( .A0(n3843), .A1(n3842), .B0(n3841), .Y(n3844) );
OAI21X4TS U5987 ( .A0(n5454), .A1(n3845), .B0(n3844), .Y(n5409) );
INVX2TS U5988 ( .A(n3846), .Y(n5407) );
INVX2TS U5989 ( .A(n5406), .Y(n3847) );
AOI21X4TS U5990 ( .A0(n5409), .A1(n5407), .B0(n3847), .Y(n3852) );
INVX2TS U5991 ( .A(n3848), .Y(n3850) );
NAND2X1TS U5992 ( .A(n3850), .B(n3849), .Y(n3851) );
XNOR2X4TS U5993 ( .A(n3852), .B(n3851), .Y(n5781) );
BUFX3TS U5994 ( .A(n3853), .Y(n6052) );
INVX2TS U5995 ( .A(n973), .Y(n5943) );
AOI21X1TS U5996 ( .A0(n5943), .A1(n5939), .B0(n3854), .Y(n3855) );
OAI21X1TS U5997 ( .A0(n5781), .A1(n6052), .B0(n3855), .Y(n3856) );
OR2X2TS U5998 ( .A(mult_x_23_n638), .B(n3886), .Y(n5258) );
CMPR32X2TS U5999 ( .A(n3857), .B(mult_x_23_n637), .C(n3856), .CO(n3888), .S(
n3886) );
INVX2TS U6000 ( .A(n3858), .Y(n3861) );
OAI21X4TS U6001 ( .A0(n5454), .A1(n3861), .B0(n3860), .Y(n3871) );
NAND2X1TS U6002 ( .A(n3870), .B(n3868), .Y(n3862) );
XOR2X4TS U6003 ( .A(n3871), .B(n3862), .Y(n5925) );
BUFX3TS U6004 ( .A(Op_MY[50]), .Y(n5779) );
AOI21X1TS U6005 ( .A0(n5943), .A1(n5775), .B0(n3863), .Y(n3864) );
OAI21X1TS U6006 ( .A0(n5925), .A1(n6052), .B0(n3864), .Y(n3879) );
INVX2TS U6007 ( .A(n3879), .Y(n3877) );
OAI21X1TS U6008 ( .A0(n5879), .A1(n5470), .B0(n4702), .Y(n3867) );
BUFX3TS U6009 ( .A(n3866), .Y(n6021) );
XOR2X1TS U6010 ( .A(n3867), .B(n6021), .Y(n3875) );
NOR2X4TS U6011 ( .A(n5167), .B(n5177), .Y(n4949) );
NAND2X4TS U6012 ( .A(n3893), .B(n4949), .Y(n3895) );
NOR2X4TS U6013 ( .A(n5163), .B(n3895), .Y(n4921) );
INVX2TS U6014 ( .A(n3868), .Y(n3869) );
AOI21X4TS U6015 ( .A0(n3871), .A1(n3870), .B0(n3869), .Y(n3872) );
XNOR2X4TS U6016 ( .A(n3872), .B(n5769), .Y(n5773) );
AOI21X1TS U6017 ( .A0(n5943), .A1(n5771), .B0(n3873), .Y(n3874) );
OAI21X1TS U6018 ( .A0(n5773), .A1(n6052), .B0(n3874), .Y(n3878) );
CMPR32X2TS U6019 ( .A(n3877), .B(n3876), .C(n3875), .CO(n3896), .S(n3887) );
NOR2X1TS U6020 ( .A(n3897), .B(n3896), .Y(n4922) );
CMPR32X2TS U6021 ( .A(n1034), .B(n3879), .C(n3878), .CO(n3899), .S(n3897) );
AOI21X1TS U6022 ( .A0(n5943), .A1(n5883), .B0(n5899), .Y(n3881) );
OAI21X1TS U6023 ( .A0(n6052), .A1(n5887), .B0(n3881), .Y(n3906) );
INVX2TS U6024 ( .A(n3906), .Y(n3898) );
NOR2X2TS U6025 ( .A(n3899), .B(n3898), .Y(n4929) );
NOR2X1TS U6026 ( .A(n4922), .B(n4929), .Y(n3901) );
BUFX8TS U6027 ( .A(n4946), .Y(n5164) );
NAND2X1TS U6028 ( .A(mult_x_23_n662), .B(mult_x_23_n656), .Y(n5190) );
OAI21X2TS U6029 ( .A0(n5183), .A1(n5189), .B0(n5190), .Y(n3882) );
AOI21X4TS U6030 ( .A0(n3884), .A1(n3883), .B0(n3882), .Y(n5162) );
NAND2X1TS U6031 ( .A(mult_x_23_n647), .B(mult_x_23_n650), .Y(n5178) );
NAND2X1TS U6032 ( .A(mult_x_23_n642), .B(mult_x_23_n646), .Y(n4956) );
INVX2TS U6033 ( .A(n4956), .Y(n5266) );
NAND2X1TS U6034 ( .A(mult_x_23_n639), .B(mult_x_23_n641), .Y(n5272) );
INVX2TS U6035 ( .A(n5272), .Y(n3885) );
NAND2X1TS U6036 ( .A(mult_x_23_n638), .B(n3886), .Y(n4943) );
INVX2TS U6037 ( .A(n4943), .Y(n5257) );
NAND2X1TS U6038 ( .A(n3888), .B(n3887), .Y(n5262) );
INVX2TS U6039 ( .A(n5262), .Y(n3889) );
AOI21X1TS U6040 ( .A0(n5257), .A1(n1012), .B0(n3889), .Y(n3890) );
NAND2X1TS U6041 ( .A(n3899), .B(n3898), .Y(n4930) );
AOI21X1TS U6042 ( .A0(n4923), .A1(n3901), .B0(n3900), .Y(n3902) );
INVX2TS U6043 ( .A(n7339), .Y(n3910) );
INVX2TS U6044 ( .A(n3913), .Y(n3915) );
NAND2X2TS U6045 ( .A(n7323), .B(n4821), .Y(n3919) );
INVX2TS U6046 ( .A(n3923), .Y(n3920) );
INVX2TS U6047 ( .A(n3928), .Y(n3930) );
INVX2TS U6048 ( .A(Sgf_operation_Result[25]), .Y(n3939) );
INVX2TS U6049 ( .A(Sgf_operation_ODD1_Q_left[25]), .Y(n3938) );
INVX2TS U6050 ( .A(Sgf_operation_Result[24]), .Y(n3933) );
INVX2TS U6051 ( .A(Sgf_operation_ODD1_Q_left[24]), .Y(n3932) );
NOR2X2TS U6052 ( .A(n3935), .B(n3934), .Y(n4176) );
CMPR32X2TS U6053 ( .A(n3933), .B(Sgf_operation_ODD1_Q_middle[24]), .C(n3932),
.CO(n3934), .S(n3997) );
INVX2TS U6054 ( .A(Sgf_operation_Result[23]), .Y(n3983) );
INVX2TS U6055 ( .A(Sgf_operation_ODD1_Q_left[23]), .Y(n3982) );
NAND2X1TS U6056 ( .A(n3935), .B(n3934), .Y(n4177) );
OAI21X2TS U6057 ( .A0(n4176), .A1(n4173), .B0(n4177), .Y(n4181) );
INVX2TS U6058 ( .A(Sgf_operation_ODD1_Q_left[27]), .Y(n3946) );
INVX2TS U6059 ( .A(Sgf_operation_ODD1_Q_right[27]), .Y(n3945) );
INVX2TS U6060 ( .A(Sgf_operation_Result[26]), .Y(n3937) );
INVX2TS U6061 ( .A(Sgf_operation_ODD1_Q_left[26]), .Y(n3936) );
NOR2X2TS U6062 ( .A(n3943), .B(n3942), .Y(n4189) );
NOR2X2TS U6063 ( .A(n3941), .B(n3940), .Y(n4187) );
NOR2X2TS U6064 ( .A(n4189), .B(n4187), .Y(n3998) );
NAND2X1TS U6065 ( .A(n3943), .B(n3942), .Y(n4190) );
OAI21X1TS U6066 ( .A0(n4189), .A1(n4186), .B0(n4190), .Y(n3944) );
AOI21X2TS U6067 ( .A0(n4181), .A1(n3998), .B0(n3944), .Y(n4146) );
INVX2TS U6068 ( .A(Sgf_operation_ODD1_Q_left[28]), .Y(n3948) );
INVX2TS U6069 ( .A(Sgf_operation_ODD1_Q_right[28]), .Y(n3947) );
CMPR32X2TS U6070 ( .A(n3946), .B(Sgf_operation_ODD1_Q_middle[27]), .C(n3945),
.CO(n3952), .S(n3943) );
NOR2X2TS U6071 ( .A(n3953), .B(n3952), .Y(n4198) );
INVX2TS U6072 ( .A(Sgf_operation_ODD1_Q_left[29]), .Y(n3950) );
INVX2TS U6073 ( .A(Sgf_operation_ODD1_Q_right[29]), .Y(n3949) );
CMPR32X2TS U6074 ( .A(Sgf_operation_ODD1_Q_middle[28]), .B(n3948), .C(n3947),
.CO(n3954), .S(n3953) );
NOR2X2TS U6075 ( .A(n3955), .B(n3954), .Y(n4200) );
NOR2X2TS U6076 ( .A(n4198), .B(n4200), .Y(n4150) );
INVX2TS U6077 ( .A(Sgf_operation_ODD1_Q_right[30]), .Y(n3951) );
INVX2TS U6078 ( .A(Sgf_operation_ODD1_Q_left[30]), .Y(n7732) );
CMPR32X2TS U6079 ( .A(Sgf_operation_ODD1_Q_middle[29]), .B(n3950), .C(n3949),
.CO(n3956), .S(n3955) );
NOR2X2TS U6080 ( .A(n3957), .B(n3956), .Y(n4205) );
INVX2TS U6081 ( .A(Sgf_operation_ODD1_Q_right[31]), .Y(n4082) );
INVX2TS U6082 ( .A(Sgf_operation_ODD1_Q_left[31]), .Y(n7724) );
CMPR32X2TS U6083 ( .A(Sgf_operation_ODD1_Q_middle[30]), .B(n3951), .C(n7732),
.CO(n3958), .S(n3957) );
NOR2X2TS U6084 ( .A(n3959), .B(n3958), .Y(n4151) );
NOR2X2TS U6085 ( .A(n4205), .B(n4151), .Y(n3961) );
NAND2X1TS U6086 ( .A(n3955), .B(n3954), .Y(n4201) );
OAI21X2TS U6087 ( .A0(n4200), .A1(n4197), .B0(n4201), .Y(n4149) );
NAND2X1TS U6088 ( .A(n3959), .B(n3958), .Y(n4152) );
OAI21X1TS U6089 ( .A0(n4151), .A1(n4206), .B0(n4152), .Y(n3960) );
OAI21X2TS U6090 ( .A0(n4146), .A1(n3999), .B0(n3962), .Y(n4081) );
INVX2TS U6091 ( .A(Sgf_operation_Result[17]), .Y(n3968) );
INVX2TS U6092 ( .A(Sgf_operation_ODD1_Q_left[17]), .Y(n3967) );
INVX2TS U6093 ( .A(Sgf_operation_Result[16]), .Y(n3964) );
INVX2TS U6094 ( .A(Sgf_operation_ODD1_Q_left[16]), .Y(n3963) );
NOR2X2TS U6095 ( .A(n3966), .B(n3965), .Y(n4359) );
INVX2TS U6096 ( .A(Sgf_operation_Result[15]), .Y(n4051) );
INVX2TS U6097 ( .A(Sgf_operation_ODD1_Q_left[15]), .Y(n4050) );
NAND2X1TS U6098 ( .A(n3966), .B(n3965), .Y(n4360) );
OAI21X2TS U6099 ( .A0(n4359), .A1(n4378), .B0(n4360), .Y(n4334) );
INVX2TS U6100 ( .A(Sgf_operation_Result[18]), .Y(n3970) );
INVX2TS U6101 ( .A(Sgf_operation_ODD1_Q_left[18]), .Y(n3969) );
INVX2TS U6102 ( .A(Sgf_operation_Result[19]), .Y(n3977) );
INVX2TS U6103 ( .A(Sgf_operation_ODD1_Q_left[19]), .Y(n3976) );
NOR2X2TS U6104 ( .A(n4364), .B(n4336), .Y(n4002) );
NAND2X1TS U6105 ( .A(n3974), .B(n3973), .Y(n4337) );
OAI21X1TS U6106 ( .A0(n4336), .A1(n4365), .B0(n4337), .Y(n3975) );
INVX2TS U6107 ( .A(Sgf_operation_Result[20]), .Y(n3979) );
INVX2TS U6108 ( .A(Sgf_operation_ODD1_Q_left[20]), .Y(n3978) );
NOR2X2TS U6109 ( .A(n3986), .B(n3985), .Y(n4345) );
INVX2TS U6110 ( .A(Sgf_operation_Result[21]), .Y(n3981) );
INVX2TS U6111 ( .A(Sgf_operation_ODD1_Q_left[21]), .Y(n3980) );
CMPR32X2TS U6112 ( .A(n3979), .B(Sgf_operation_ODD1_Q_middle[20]), .C(n3978),
.CO(n3987), .S(n3986) );
NOR2X2TS U6113 ( .A(n3988), .B(n3987), .Y(n4347) );
NOR2X2TS U6114 ( .A(n4345), .B(n4347), .Y(n4165) );
INVX2TS U6115 ( .A(Sgf_operation_Result[22]), .Y(n3984) );
CMPR32X2TS U6116 ( .A(Sgf_operation_ODD1_Q_middle[21]), .B(n3981), .C(n3980),
.CO(n3989), .S(n3988) );
NOR2X2TS U6117 ( .A(n3990), .B(n3989), .Y(n4352) );
CMPR32X2TS U6118 ( .A(n3983), .B(Sgf_operation_ODD1_Q_middle[23]), .C(n3982),
.CO(n3996), .S(n3992) );
CMPR32X2TS U6119 ( .A(Sgf_operation_ODD1_Q_middle[22]), .B(n3984), .C(
DP_OP_168J42_122_1342_n617), .CO(n3991), .S(n3990) );
NOR2X2TS U6120 ( .A(n3992), .B(n3991), .Y(n4166) );
NOR2X2TS U6121 ( .A(n4352), .B(n4166), .Y(n3994) );
NAND2X4TS U6122 ( .A(n4165), .B(n3994), .Y(n4003) );
NAND2X1TS U6123 ( .A(n3988), .B(n3987), .Y(n4348) );
OAI21X2TS U6124 ( .A0(n4347), .A1(n4344), .B0(n4348), .Y(n4164) );
NAND2X1TS U6125 ( .A(n3992), .B(n3991), .Y(n4167) );
OAI21X1TS U6126 ( .A0(n4166), .A1(n4353), .B0(n4167), .Y(n3993) );
AOI21X2TS U6127 ( .A0(n4164), .A1(n3994), .B0(n3993), .Y(n3995) );
NOR2X2TS U6128 ( .A(n3997), .B(n3996), .Y(n4174) );
NOR2X2TS U6129 ( .A(n4174), .B(n4176), .Y(n4182) );
NAND2X2TS U6130 ( .A(n4182), .B(n3998), .Y(n4145) );
NOR2X4TS U6131 ( .A(n3999), .B(n4145), .Y(n4079) );
NOR2X4TS U6132 ( .A(n4160), .B(n4003), .Y(n4141) );
NAND2X4TS U6133 ( .A(n4079), .B(n4141), .Y(n4078) );
INVX2TS U6134 ( .A(Sgf_operation_Result[1]), .Y(n4007) );
INVX2TS U6135 ( .A(Sgf_operation_ODD1_Q_left[1]), .Y(n4005) );
NOR2X2TS U6136 ( .A(n4006), .B(n4005), .Y(n4221) );
OR2X2TS U6137 ( .A(DP_OP_168J42_122_1342_n587), .B(
Sgf_operation_ODD1_Q_middle[0]), .Y(n4227) );
INVX2TS U6138 ( .A(Sgf_operation_ODD1_Q_left[0]), .Y(n4228) );
NAND2X2TS U6139 ( .A(DP_OP_168J42_122_1342_n587), .B(
Sgf_operation_ODD1_Q_middle[0]), .Y(n4226) );
INVX2TS U6140 ( .A(n4226), .Y(n4004) );
AOI21X2TS U6141 ( .A0(n4227), .A1(n4228), .B0(n4004), .Y(n4224) );
NAND2X2TS U6142 ( .A(n4006), .B(n4005), .Y(n4222) );
OAI21X4TS U6143 ( .A0(n4221), .A1(n4224), .B0(n4222), .Y(n4210) );
INVX2TS U6144 ( .A(Sgf_operation_ODD1_Q_left[2]), .Y(n4008) );
NOR2X4TS U6145 ( .A(n4011), .B(n4010), .Y(n4214) );
INVX2TS U6146 ( .A(Sgf_operation_Result[3]), .Y(n4017) );
INVX2TS U6147 ( .A(Sgf_operation_ODD1_Q_left[3]), .Y(n4016) );
CMPR32X2TS U6148 ( .A(n4009), .B(Sgf_operation_ODD1_Q_middle[2]), .C(n4008),
.CO(n4012), .S(n4011) );
NOR2X4TS U6149 ( .A(n4013), .B(n4012), .Y(n4216) );
NOR2X2TS U6150 ( .A(n4214), .B(n4216), .Y(n4015) );
NAND2X2TS U6151 ( .A(n4011), .B(n4010), .Y(n4213) );
NAND2X2TS U6152 ( .A(n4013), .B(n4012), .Y(n4217) );
OAI21X4TS U6153 ( .A0(n4216), .A1(n4213), .B0(n4217), .Y(n4014) );
AOI21X4TS U6154 ( .A0(n4210), .A1(n4015), .B0(n4014), .Y(n4237) );
INVX2TS U6155 ( .A(Sgf_operation_Result[4]), .Y(n4019) );
INVX2TS U6156 ( .A(Sgf_operation_ODD1_Q_left[4]), .Y(n4018) );
CMPR32X2TS U6157 ( .A(Sgf_operation_ODD1_Q_middle[3]), .B(n4017), .C(n4016),
.CO(n4024), .S(n4013) );
NOR2X2TS U6158 ( .A(n4025), .B(n4024), .Y(n4238) );
INVX2TS U6159 ( .A(Sgf_operation_Result[5]), .Y(n4021) );
INVX2TS U6160 ( .A(Sgf_operation_ODD1_Q_left[5]), .Y(n4020) );
CMPR32X2TS U6161 ( .A(Sgf_operation_ODD1_Q_middle[4]), .B(n4019), .C(n4018),
.CO(n4026), .S(n4025) );
NOR2X4TS U6162 ( .A(n4027), .B(n4026), .Y(n4250) );
NOR2X2TS U6163 ( .A(n4238), .B(n4250), .Y(n4243) );
INVX2TS U6164 ( .A(Sgf_operation_Result[6]), .Y(n4023) );
INVX2TS U6165 ( .A(Sgf_operation_ODD1_Q_left[6]), .Y(n4022) );
CMPR32X2TS U6166 ( .A(Sgf_operation_ODD1_Q_middle[5]), .B(n4021), .C(n4020),
.CO(n4028), .S(n4027) );
INVX2TS U6167 ( .A(Sgf_operation_ODD1_Q_left[7]), .Y(n4036) );
CMPR32X2TS U6168 ( .A(Sgf_operation_ODD1_Q_middle[6]), .B(n4023), .C(n4022),
.CO(n4030), .S(n4029) );
NAND2X2TS U6169 ( .A(n4243), .B(n4033), .Y(n4035) );
NAND2X2TS U6170 ( .A(n4025), .B(n4024), .Y(n4246) );
NAND2X2TS U6171 ( .A(n4029), .B(n4028), .Y(n4263) );
NAND2X1TS U6172 ( .A(n4031), .B(n4030), .Y(n4267) );
AOI21X4TS U6173 ( .A0(n4242), .A1(n4033), .B0(n4032), .Y(n4034) );
OAI21X4TS U6174 ( .A0(n4237), .A1(n4035), .B0(n4034), .Y(n4260) );
INVX2TS U6175 ( .A(Sgf_operation_Result[8]), .Y(n4039) );
INVX2TS U6176 ( .A(Sgf_operation_ODD1_Q_left[8]), .Y(n4038) );
CMPR32X2TS U6177 ( .A(n4037), .B(Sgf_operation_ODD1_Q_middle[7]), .C(n4036),
.CO(n4054), .S(n4031) );
NOR2X2TS U6178 ( .A(n4055), .B(n4054), .Y(n4278) );
INVX2TS U6179 ( .A(Sgf_operation_ODD1_Q_left[9]), .Y(n4040) );
CMPR32X2TS U6180 ( .A(n4039), .B(Sgf_operation_ODD1_Q_middle[8]), .C(n4038),
.CO(n4056), .S(n4055) );
NOR2X2TS U6181 ( .A(n4278), .B(n4279), .Y(n4271) );
INVX2TS U6182 ( .A(Sgf_operation_Result[10]), .Y(n4043) );
INVX2TS U6183 ( .A(Sgf_operation_ODD1_Q_left[10]), .Y(n4042) );
NOR2X2TS U6184 ( .A(n4059), .B(n4058), .Y(n4275) );
INVX2TS U6185 ( .A(Sgf_operation_Result[11]), .Y(n4045) );
INVX2TS U6186 ( .A(Sgf_operation_ODD1_Q_left[11]), .Y(n4044) );
CMPR32X2TS U6187 ( .A(Sgf_operation_ODD1_Q_middle[10]), .B(n4043), .C(n4042),
.CO(n4060), .S(n4059) );
NOR2X4TS U6188 ( .A(n4061), .B(n4060), .Y(n4300) );
INVX2TS U6189 ( .A(Sgf_operation_Result[12]), .Y(n4047) );
INVX2TS U6190 ( .A(Sgf_operation_ODD1_Q_left[12]), .Y(n4046) );
CMPR32X2TS U6191 ( .A(Sgf_operation_ODD1_Q_middle[11]), .B(n4045), .C(n4044),
.CO(n4064), .S(n4061) );
NOR2X2TS U6192 ( .A(n4065), .B(n4064), .Y(n4308) );
INVX2TS U6193 ( .A(Sgf_operation_Result[13]), .Y(n4049) );
INVX2TS U6194 ( .A(Sgf_operation_ODD1_Q_left[13]), .Y(n4048) );
CMPR32X2TS U6195 ( .A(Sgf_operation_ODD1_Q_middle[12]), .B(n4047), .C(n4046),
.CO(n4066), .S(n4065) );
NOR2X4TS U6196 ( .A(n4067), .B(n4066), .Y(n4314) );
NOR2X2TS U6197 ( .A(n4308), .B(n4314), .Y(n4319) );
INVX2TS U6198 ( .A(Sgf_operation_Result[14]), .Y(n4053) );
INVX2TS U6199 ( .A(Sgf_operation_ODD1_Q_left[14]), .Y(n4052) );
CMPR32X2TS U6200 ( .A(n4049), .B(Sgf_operation_ODD1_Q_middle[13]), .C(n4048),
.CO(n4068), .S(n4067) );
NAND2X4TS U6201 ( .A(n4319), .B(n4073), .Y(n4075) );
NAND2X2TS U6202 ( .A(n4055), .B(n4054), .Y(n4277) );
NAND2X2TS U6203 ( .A(n4059), .B(n4058), .Y(n4296) );
OAI21X2TS U6204 ( .A0(n4300), .A1(n4296), .B0(n4301), .Y(n4062) );
AOI21X4TS U6205 ( .A0(n4272), .A1(n4063), .B0(n4062), .Y(n4305) );
NAND2X2TS U6206 ( .A(n4065), .B(n4064), .Y(n4310) );
NAND2X1TS U6207 ( .A(n4067), .B(n4066), .Y(n4315) );
OAI21X2TS U6208 ( .A0(n4314), .A1(n4310), .B0(n4315), .Y(n4320) );
NAND2X1TS U6209 ( .A(n4071), .B(n4070), .Y(n4374) );
OAI21X4TS U6210 ( .A0(n4305), .A1(n4075), .B0(n4074), .Y(n4076) );
AOI21X4TS U6211 ( .A0(n4260), .A1(n4077), .B0(n4076), .Y(n4140) );
AOI2BB2X4TS U6212 ( .B0(n4142), .B1(n4079), .A0N(n4078), .A1N(n4140), .Y(
n4080) );
NAND2BX4TS U6213 ( .AN(n4081), .B(n4080), .Y(n4525) );
INVX2TS U6214 ( .A(Sgf_operation_ODD1_Q_left[32]), .Y(n7710) );
INVX2TS U6215 ( .A(Sgf_operation_ODD1_Q_right[32]), .Y(n4083) );
CMPR32X2TS U6216 ( .A(Sgf_operation_ODD1_Q_middle[31]), .B(n4082), .C(n7724),
.CO(n4084), .S(n3959) );
NOR2X2TS U6217 ( .A(n4085), .B(n4084), .Y(n4156) );
INVX2TS U6218 ( .A(Sgf_operation_ODD1_Q_left[33]), .Y(n7702) );
INVX2TS U6219 ( .A(Sgf_operation_ODD1_Q_right[33]), .Y(n4090) );
CMPR32X2TS U6220 ( .A(Sgf_operation_ODD1_Q_middle[32]), .B(n7710), .C(n4083),
.CO(n4086), .S(n4085) );
NOR2X2TS U6221 ( .A(n4087), .B(n4086), .Y(n4131) );
INVX2TS U6222 ( .A(n4101), .Y(n4089) );
NAND2X1TS U6223 ( .A(n4087), .B(n4086), .Y(n4132) );
OAI21X1TS U6224 ( .A0(n4131), .A1(n4157), .B0(n4132), .Y(n4106) );
OAI21X2TS U6225 ( .A0(n4488), .A1(n4089), .B0(n4088), .Y(n4139) );
INVX2TS U6226 ( .A(Sgf_operation_ODD1_Q_left[34]), .Y(n7692) );
INVX2TS U6227 ( .A(Sgf_operation_ODD1_Q_right[34]), .Y(n4094) );
CMPR32X2TS U6228 ( .A(Sgf_operation_ODD1_Q_middle[33]), .B(n7702), .C(n4090),
.CO(n4091), .S(n4087) );
NOR2X1TS U6229 ( .A(n4092), .B(n4091), .Y(n4100) );
INVX2TS U6230 ( .A(n4100), .Y(n4137) );
INVX2TS U6231 ( .A(n4136), .Y(n4093) );
INVX2TS U6232 ( .A(Sgf_operation_ODD1_Q_left[35]), .Y(n7685) );
INVX2TS U6233 ( .A(Sgf_operation_ODD1_Q_right[35]), .Y(n4107) );
CMPR32X2TS U6234 ( .A(Sgf_operation_ODD1_Q_middle[34]), .B(n7692), .C(n4094),
.CO(n4095), .S(n4092) );
NOR2X2TS U6235 ( .A(n4096), .B(n4095), .Y(n4103) );
NAND2X1TS U6236 ( .A(n4096), .B(n4095), .Y(n4102) );
NAND2X1TS U6237 ( .A(n4097), .B(n4102), .Y(n4098) );
NOR2X2TS U6238 ( .A(n4418), .B(Sgf_operation_ODD1_Q_left[8]), .Y(n8046) );
NOR2X2TS U6239 ( .A(n4100), .B(n4103), .Y(n4105) );
NAND2X2TS U6240 ( .A(n4101), .B(n4105), .Y(n4434) );
OAI21X1TS U6241 ( .A0(n4103), .A1(n4136), .B0(n4102), .Y(n4104) );
AOI21X4TS U6242 ( .A0(n4106), .A1(n4105), .B0(n4104), .Y(n4442) );
OAI21X4TS U6243 ( .A0(n4488), .A1(n4434), .B0(n4442), .Y(n4113) );
INVX2TS U6244 ( .A(Sgf_operation_ODD1_Q_right[36]), .Y(n4114) );
INVX2TS U6245 ( .A(Sgf_operation_ODD1_Q_left[36]), .Y(n7673) );
CMPR32X2TS U6246 ( .A(Sgf_operation_ODD1_Q_middle[35]), .B(n7685), .C(n4107),
.CO(n4108), .S(n4096) );
NOR2X1TS U6247 ( .A(n4109), .B(n4108), .Y(n4120) );
INVX2TS U6248 ( .A(n4120), .Y(n4112) );
NAND2X1TS U6249 ( .A(n4112), .B(n4122), .Y(n4110) );
NOR2X2TS U6250 ( .A(n4419), .B(Sgf_operation_ODD1_Q_left[9]), .Y(n8033) );
NOR2X2TS U6251 ( .A(n8046), .B(n8033), .Y(n8005) );
INVX2TS U6252 ( .A(n4122), .Y(n4111) );
INVX2TS U6253 ( .A(Sgf_operation_ODD1_Q_left[37]), .Y(n4647) );
INVX2TS U6254 ( .A(Sgf_operation_ODD1_Q_right[37]), .Y(n4127) );
CMPR32X2TS U6255 ( .A(Sgf_operation_ODD1_Q_middle[36]), .B(n4114), .C(n7673),
.CO(n4115), .S(n4109) );
NOR2X2TS U6256 ( .A(n4116), .B(n4115), .Y(n4123) );
NAND2X1TS U6257 ( .A(n4116), .B(n4115), .Y(n4121) );
NAND2X1TS U6258 ( .A(n4117), .B(n4121), .Y(n4118) );
NOR2X2TS U6259 ( .A(n4420), .B(Sgf_operation_ODD1_Q_left[10]), .Y(n8017) );
NOR2X2TS U6260 ( .A(n4120), .B(n4123), .Y(n4433) );
INVX2TS U6261 ( .A(n4439), .Y(n4124) );
OAI21X4TS U6262 ( .A0(n4126), .A1(n4125), .B0(n4124), .Y(n4556) );
INVX2TS U6263 ( .A(Sgf_operation_ODD1_Q_left[38]), .Y(n7656) );
INVX2TS U6264 ( .A(Sgf_operation_ODD1_Q_right[38]), .Y(n4431) );
CMPR32X2TS U6265 ( .A(Sgf_operation_ODD1_Q_middle[37]), .B(n4647), .C(n4127),
.CO(n4128), .S(n4116) );
NOR2X2TS U6266 ( .A(n4129), .B(n4128), .Y(n4432) );
INVX2TS U6267 ( .A(n4432), .Y(n4555) );
NAND2X1TS U6268 ( .A(n4555), .B(n4553), .Y(n4130) );
NOR2X2TS U6269 ( .A(n4421), .B(Sgf_operation_ODD1_Q_left[11]), .Y(n8006) );
OAI21X1TS U6270 ( .A0(n4488), .A1(n4156), .B0(n4157), .Y(n4135) );
INVX2TS U6271 ( .A(n4131), .Y(n4133) );
NAND2X1TS U6272 ( .A(n4133), .B(n4132), .Y(n4134) );
NOR2X2TS U6273 ( .A(n4414), .B(Sgf_operation_ODD1_Q_left[6]), .Y(n8076) );
NAND2X1TS U6274 ( .A(n4137), .B(n4136), .Y(n4138) );
XNOR2X1TS U6275 ( .A(n4139), .B(n4138), .Y(n4415) );
NOR2X2TS U6276 ( .A(n4415), .B(Sgf_operation_ODD1_Q_left[7]), .Y(n8063) );
NAND2X8TS U6277 ( .A(n4144), .B(n4143), .Y(n4183) );
INVX2TS U6278 ( .A(n4145), .Y(n4148) );
INVX2TS U6279 ( .A(n4146), .Y(n4147) );
AOI21X4TS U6280 ( .A0(n4183), .A1(n4148), .B0(n4147), .Y(n4199) );
INVX4TS U6281 ( .A(n4199), .Y(n4196) );
AOI21X4TS U6282 ( .A0(n4196), .A1(n4150), .B0(n4149), .Y(n4209) );
NAND2X1TS U6283 ( .A(n4153), .B(n4152), .Y(n4154) );
XNOR2X2TS U6284 ( .A(n4155), .B(n4154), .Y(n4412) );
INVX2TS U6285 ( .A(n4156), .Y(n4158) );
NAND2X1TS U6286 ( .A(n4158), .B(n4157), .Y(n4159) );
XOR2X1TS U6287 ( .A(n4488), .B(n4159), .Y(n4413) );
NOR2X2TS U6288 ( .A(n4413), .B(Sgf_operation_ODD1_Q_left[5]), .Y(n8088) );
NOR2X2TS U6289 ( .A(n8099), .B(n8088), .Y(n8062) );
NAND2X2TS U6290 ( .A(n4417), .B(n8062), .Y(n8000) );
INVX2TS U6291 ( .A(n4160), .Y(n4163) );
INVX2TS U6292 ( .A(n4161), .Y(n4162) );
AOI21X4TS U6293 ( .A0(n4381), .A1(n4163), .B0(n4162), .Y(n4346) );
NAND2X1TS U6294 ( .A(n4168), .B(n4167), .Y(n4169) );
XNOR2X2TS U6295 ( .A(n4170), .B(n4169), .Y(n4398) );
INVX2TS U6296 ( .A(n4174), .Y(n4171) );
NAND2X1TS U6297 ( .A(n4171), .B(n4173), .Y(n4172) );
XNOR2X1TS U6298 ( .A(n4183), .B(n4172), .Y(n4399) );
NOR2X2TS U6299 ( .A(n4399), .B(Sgf_operation_ODD1_Q_right[51]), .Y(n8347) );
NOR2X2TS U6300 ( .A(n8340), .B(n8347), .Y(n8161) );
OAI21X1TS U6301 ( .A0(n4175), .A1(n4174), .B0(n4173), .Y(n4180) );
NAND2X1TS U6302 ( .A(n4178), .B(n4177), .Y(n4179) );
NOR2X2TS U6303 ( .A(n4400), .B(Sgf_operation_ODD1_Q_right[52]), .Y(n8171) );
NAND2X1TS U6304 ( .A(n4184), .B(n4186), .Y(n4185) );
CLKXOR2X2TS U6305 ( .A(n4188), .B(n4185), .Y(n4401) );
NOR2X2TS U6306 ( .A(n4401), .B(Sgf_operation_ODD1_Q_right[53]), .Y(n8162) );
OAI21X1TS U6307 ( .A0(n4188), .A1(n4187), .B0(n4186), .Y(n4193) );
NAND2X1TS U6308 ( .A(n4191), .B(n4190), .Y(n4192) );
NOR2X2TS U6309 ( .A(n4404), .B(Sgf_operation_ODD1_Q_left[0]), .Y(n8149) );
INVX2TS U6310 ( .A(n4198), .Y(n4194) );
NAND2X1TS U6311 ( .A(n4194), .B(n4197), .Y(n4195) );
XNOR2X1TS U6312 ( .A(n4196), .B(n4195), .Y(n4405) );
NOR2X2TS U6313 ( .A(n4405), .B(Sgf_operation_ODD1_Q_left[1]), .Y(n8140) );
OAI21X1TS U6314 ( .A0(n4199), .A1(n4198), .B0(n4197), .Y(n4204) );
CLKINVX1TS U6315 ( .A(n4200), .Y(n4202) );
NAND2X1TS U6316 ( .A(n4202), .B(n4201), .Y(n4203) );
XNOR2X1TS U6317 ( .A(n4204), .B(n4203), .Y(n4406) );
NOR2X2TS U6318 ( .A(n4406), .B(Sgf_operation_ODD1_Q_left[2]), .Y(n8128) );
NAND2X1TS U6319 ( .A(n4207), .B(n4206), .Y(n4208) );
NOR2X2TS U6320 ( .A(n4407), .B(Sgf_operation_ODD1_Q_left[3]), .Y(n8117) );
NAND2X4TS U6321 ( .A(n4427), .B(n7999), .Y(n4429) );
INVX2TS U6322 ( .A(n4210), .Y(n4215) );
INVX2TS U6323 ( .A(n4214), .Y(n4211) );
NAND2X1TS U6324 ( .A(n4211), .B(n4213), .Y(n4212) );
XOR2X1TS U6325 ( .A(n4215), .B(n4212), .Y(n4232) );
OAI21X1TS U6326 ( .A0(n4215), .A1(n4214), .B0(n4213), .Y(n4220) );
NAND2X1TS U6327 ( .A(n4218), .B(n4217), .Y(n4219) );
XNOR2X1TS U6328 ( .A(n4220), .B(n4219), .Y(n4233) );
INVX1TS U6329 ( .A(n4221), .Y(n4223) );
NAND2X1TS U6330 ( .A(n4223), .B(n4222), .Y(n4225) );
XOR2X1TS U6331 ( .A(n4225), .B(n4224), .Y(n4230) );
NAND2X1TS U6332 ( .A(n4227), .B(n4226), .Y(n4229) );
XNOR2X1TS U6333 ( .A(n4229), .B(n4228), .Y(n8193) );
NAND2X1TS U6334 ( .A(n8193), .B(Sgf_operation_ODD1_Q_right[27]), .Y(n8194)
);
INVX2TS U6335 ( .A(n8194), .Y(n8198) );
NAND2X1TS U6336 ( .A(n4230), .B(Sgf_operation_ODD1_Q_right[28]), .Y(n8197)
);
INVX2TS U6337 ( .A(n8197), .Y(n4231) );
NAND2X1TS U6338 ( .A(n4232), .B(Sgf_operation_ODD1_Q_right[29]), .Y(n8201)
);
INVX2TS U6339 ( .A(n8201), .Y(n8205) );
NAND2X1TS U6340 ( .A(n4233), .B(Sgf_operation_ODD1_Q_right[30]), .Y(n8207)
);
INVX2TS U6341 ( .A(n8207), .Y(n4234) );
AOI21X1TS U6342 ( .A0(n8205), .A1(n731), .B0(n4234), .Y(n4235) );
INVX4TS U6343 ( .A(n4237), .Y(n4249) );
INVX2TS U6344 ( .A(n4238), .Y(n4248) );
NAND2X1TS U6345 ( .A(n4248), .B(n4246), .Y(n4239) );
XNOR2X1TS U6346 ( .A(n4249), .B(n4239), .Y(n4240) );
NAND2X1TS U6347 ( .A(n4240), .B(Sgf_operation_ODD1_Q_right[31]), .Y(n8211)
);
INVX2TS U6348 ( .A(n8211), .Y(n4241) );
AOI21X2TS U6349 ( .A0(n8213), .A1(n991), .B0(n4241), .Y(n8215) );
AOI21X4TS U6350 ( .A0(n4249), .A1(n4243), .B0(n4242), .Y(n4265) );
NAND2X1TS U6351 ( .A(n4244), .B(n4263), .Y(n4245) );
XOR2X1TS U6352 ( .A(n4265), .B(n4245), .Y(n4256) );
INVX2TS U6353 ( .A(n4246), .Y(n4247) );
AOI21X1TS U6354 ( .A0(n4249), .A1(n4248), .B0(n4247), .Y(n4254) );
NAND2X1TS U6355 ( .A(n4252), .B(n4251), .Y(n4253) );
XOR2X1TS U6356 ( .A(n4254), .B(n4253), .Y(n4255) );
NAND2X1TS U6357 ( .A(n990), .B(n987), .Y(n4259) );
NAND2X1TS U6358 ( .A(n4255), .B(Sgf_operation_ODD1_Q_right[32]), .Y(n8216)
);
INVX2TS U6359 ( .A(n8216), .Y(n8219) );
NAND2X1TS U6360 ( .A(n4256), .B(Sgf_operation_ODD1_Q_right[33]), .Y(n8221)
);
INVX2TS U6361 ( .A(n8221), .Y(n4257) );
AOI21X1TS U6362 ( .A0(n990), .A1(n8219), .B0(n4257), .Y(n4258) );
OAI21X4TS U6363 ( .A0(n8215), .A1(n4259), .B0(n4258), .Y(n8226) );
INVX4TS U6364 ( .A(n4260), .Y(n4307) );
NAND2X1TS U6365 ( .A(n4261), .B(n4277), .Y(n4262) );
XOR2X1TS U6366 ( .A(n4307), .B(n4262), .Y(n4286) );
OAI21X1TS U6367 ( .A0(n4265), .A1(n4264), .B0(n4263), .Y(n4270) );
NAND2X1TS U6368 ( .A(n4268), .B(n4267), .Y(n4269) );
XNOR2X1TS U6369 ( .A(n4270), .B(n4269), .Y(n4285) );
INVX2TS U6370 ( .A(n8231), .Y(n8227) );
OAI21X2TS U6371 ( .A0(n4307), .A1(n4274), .B0(n4273), .Y(n4299) );
NAND2X1TS U6372 ( .A(n4298), .B(n4296), .Y(n4276) );
XNOR2X1TS U6373 ( .A(n4299), .B(n4276), .Y(n4290) );
OAI21X1TS U6374 ( .A0(n4307), .A1(n4278), .B0(n4277), .Y(n4283) );
INVX2TS U6375 ( .A(n4279), .Y(n4281) );
NAND2X1TS U6376 ( .A(n4281), .B(n4280), .Y(n4282) );
XNOR2X1TS U6377 ( .A(n4283), .B(n4282), .Y(n4289) );
NOR2X2TS U6378 ( .A(n8237), .B(n4293), .Y(n4295) );
INVX2TS U6379 ( .A(n8230), .Y(n4288) );
NAND2X1TS U6380 ( .A(n4286), .B(Sgf_operation_ODD1_Q_right[35]), .Y(n8232)
);
INVX2TS U6381 ( .A(n8232), .Y(n4287) );
AOI21X2TS U6382 ( .A0(n988), .A1(n4288), .B0(n4287), .Y(n8236) );
NAND2X1TS U6383 ( .A(n4289), .B(Sgf_operation_ODD1_Q_right[36]), .Y(n8239)
);
INVX2TS U6384 ( .A(n8239), .Y(n8242) );
NAND2X1TS U6385 ( .A(n4290), .B(Sgf_operation_ODD1_Q_right[37]), .Y(n8244)
);
INVX2TS U6386 ( .A(n8244), .Y(n4291) );
AOI21X1TS U6387 ( .A0(n989), .A1(n8242), .B0(n4291), .Y(n4292) );
OAI21X1TS U6388 ( .A0(n8236), .A1(n4293), .B0(n4292), .Y(n4294) );
INVX2TS U6389 ( .A(n4296), .Y(n4297) );
AOI21X1TS U6390 ( .A0(n4299), .A1(n4298), .B0(n4297), .Y(n4304) );
NAND2X1TS U6391 ( .A(n4302), .B(n4301), .Y(n4303) );
CLKXOR2X2TS U6392 ( .A(n4304), .B(n4303), .Y(n4326) );
INVX4TS U6393 ( .A(n4313), .Y(n4323) );
INVX2TS U6394 ( .A(n4308), .Y(n4312) );
NAND2X1TS U6395 ( .A(n4312), .B(n4310), .Y(n4309) );
XOR2X1TS U6396 ( .A(n4323), .B(n4309), .Y(n4327) );
NOR2X2TS U6397 ( .A(n4327), .B(Sgf_operation_ODD1_Q_right[39]), .Y(n8255) );
INVX2TS U6398 ( .A(n4310), .Y(n4311) );
AOI21X1TS U6399 ( .A0(n4313), .A1(n4312), .B0(n4311), .Y(n4318) );
NAND2X1TS U6400 ( .A(n4316), .B(n4315), .Y(n4317) );
NOR2X2TS U6401 ( .A(n4328), .B(Sgf_operation_ODD1_Q_right[40]), .Y(n8316) );
INVX2TS U6402 ( .A(n4319), .Y(n4322) );
NAND2X1TS U6403 ( .A(n4371), .B(n4369), .Y(n4325) );
XNOR2X1TS U6404 ( .A(n4372), .B(n4325), .Y(n4329) );
NOR2X2TS U6405 ( .A(n4329), .B(Sgf_operation_ODD1_Q_right[41]), .Y(n8310) );
NOR2X2TS U6406 ( .A(n8316), .B(n8310), .Y(n4331) );
NAND2X2TS U6407 ( .A(n4326), .B(Sgf_operation_ODD1_Q_right[38]), .Y(n8252)
);
NAND2X1TS U6408 ( .A(n4327), .B(Sgf_operation_ODD1_Q_right[39]), .Y(n8256)
);
OAI21X1TS U6409 ( .A0(n8252), .A1(n8255), .B0(n8256), .Y(n8307) );
NAND2X1TS U6410 ( .A(n4329), .B(Sgf_operation_ODD1_Q_right[41]), .Y(n8311)
);
AOI21X1TS U6411 ( .A0(n4331), .A1(n8307), .B0(n4330), .Y(n4332) );
OAI21X4TS U6412 ( .A0(n8248), .A1(n4333), .B0(n4332), .Y(n8261) );
OAI21X1TS U6413 ( .A0(n4368), .A1(n4364), .B0(n4365), .Y(n4340) );
NAND2X1TS U6414 ( .A(n4338), .B(n4337), .Y(n4339) );
NOR2X2TS U6415 ( .A(n4388), .B(Sgf_operation_ODD1_Q_right[46]), .Y(n8264) );
INVX2TS U6416 ( .A(n4345), .Y(n4341) );
NAND2X1TS U6417 ( .A(n4341), .B(n4344), .Y(n4342) );
XNOR2X1TS U6418 ( .A(n4343), .B(n4342), .Y(n4389) );
NOR2X2TS U6419 ( .A(n4389), .B(Sgf_operation_ODD1_Q_right[47]), .Y(n8266) );
OAI21X1TS U6420 ( .A0(n4346), .A1(n4345), .B0(n4344), .Y(n4351) );
NAND2X1TS U6421 ( .A(n4349), .B(n4348), .Y(n4350) );
XNOR2X1TS U6422 ( .A(n4351), .B(n4350), .Y(n4390) );
NAND2X1TS U6423 ( .A(n4354), .B(n4353), .Y(n4355) );
CLKXOR2X2TS U6424 ( .A(n4356), .B(n4355), .Y(n4391) );
NOR2X2TS U6425 ( .A(n4391), .B(Sgf_operation_ODD1_Q_right[49]), .Y(n8334) );
INVX2TS U6426 ( .A(n4357), .Y(n4379) );
INVX2TS U6427 ( .A(n4378), .Y(n4358) );
AOI21X1TS U6428 ( .A0(n4381), .A1(n4379), .B0(n4358), .Y(n4363) );
NAND2X1TS U6429 ( .A(n4361), .B(n4360), .Y(n4362) );
NAND2X1TS U6430 ( .A(n4366), .B(n4365), .Y(n4367) );
NOR2X2TS U6431 ( .A(n4385), .B(Sgf_operation_ODD1_Q_right[45]), .Y(n8283) );
INVX2TS U6432 ( .A(n4369), .Y(n4370) );
AOI21X1TS U6433 ( .A0(n4372), .A1(n4371), .B0(n4370), .Y(n4377) );
NAND2X1TS U6434 ( .A(n4375), .B(n4374), .Y(n4376) );
CLKXOR2X2TS U6435 ( .A(n4377), .B(n4376), .Y(n4382) );
NOR2X2TS U6436 ( .A(n4382), .B(Sgf_operation_ODD1_Q_right[42]), .Y(n8301) );
NAND2X1TS U6437 ( .A(n4379), .B(n4378), .Y(n4380) );
XNOR2X1TS U6438 ( .A(n4381), .B(n4380), .Y(n4383) );
NOR2X2TS U6439 ( .A(n4383), .B(Sgf_operation_ODD1_Q_right[43]), .Y(n8295) );
NAND2X2TS U6440 ( .A(n4387), .B(n8277), .Y(n8263) );
NOR2X2TS U6441 ( .A(n4395), .B(n8263), .Y(n4397) );
NAND2X2TS U6442 ( .A(n4382), .B(Sgf_operation_ODD1_Q_right[42]), .Y(n8302)
);
NAND2X1TS U6443 ( .A(n4383), .B(Sgf_operation_ODD1_Q_right[43]), .Y(n8296)
);
NAND2X1TS U6444 ( .A(n4385), .B(Sgf_operation_ODD1_Q_right[45]), .Y(n8284)
);
AOI21X2TS U6445 ( .A0(n4387), .A1(n8278), .B0(n4386), .Y(n8262) );
NAND2X2TS U6446 ( .A(n4388), .B(Sgf_operation_ODD1_Q_right[46]), .Y(n8273)
);
NAND2X1TS U6447 ( .A(n4389), .B(Sgf_operation_ODD1_Q_right[47]), .Y(n8267)
);
NAND2X1TS U6448 ( .A(n4391), .B(Sgf_operation_ODD1_Q_right[49]), .Y(n8335)
);
OAI21X2TS U6449 ( .A0(n8262), .A1(n4395), .B0(n4394), .Y(n4396) );
AOI21X4TS U6450 ( .A0(n8261), .A1(n4397), .B0(n4396), .Y(n7997) );
NAND2X1TS U6451 ( .A(n4399), .B(Sgf_operation_ODD1_Q_right[51]), .Y(n8348)
);
NAND2X1TS U6452 ( .A(n4400), .B(Sgf_operation_ODD1_Q_right[52]), .Y(n8172)
);
NAND2X1TS U6453 ( .A(n4401), .B(Sgf_operation_ODD1_Q_right[53]), .Y(n8163)
);
OAI21X1TS U6454 ( .A0(n8162), .A1(n8172), .B0(n8163), .Y(n4402) );
NAND2X2TS U6455 ( .A(n4404), .B(Sgf_operation_ODD1_Q_left[0]), .Y(n8150) );
NAND2X1TS U6456 ( .A(n4405), .B(Sgf_operation_ODD1_Q_left[1]), .Y(n8141) );
OAI21X4TS U6457 ( .A0(n8140), .A1(n8150), .B0(n8141), .Y(n8115) );
NAND2X1TS U6458 ( .A(n4407), .B(Sgf_operation_ODD1_Q_left[3]), .Y(n8118) );
OAI21X4TS U6459 ( .A0(n8112), .A1(n4411), .B0(n4410), .Y(n7998) );
NAND2X2TS U6460 ( .A(n4412), .B(Sgf_operation_ODD1_Q_left[4]), .Y(n8100) );
NAND2X1TS U6461 ( .A(n4413), .B(Sgf_operation_ODD1_Q_left[5]), .Y(n8089) );
OAI21X4TS U6462 ( .A0(n8100), .A1(n8088), .B0(n8089), .Y(n8061) );
NAND2X1TS U6463 ( .A(n4415), .B(Sgf_operation_ODD1_Q_left[7]), .Y(n8064) );
NAND2X1TS U6464 ( .A(n4419), .B(Sgf_operation_ODD1_Q_left[9]), .Y(n8034) );
OAI21X2TS U6465 ( .A0(n8033), .A1(n8047), .B0(n8034), .Y(n8004) );
NAND2X1TS U6466 ( .A(n4420), .B(Sgf_operation_ODD1_Q_left[10]), .Y(n8018) );
NAND2X1TS U6467 ( .A(n4421), .B(Sgf_operation_ODD1_Q_left[11]), .Y(n8007) );
OAI21X2TS U6468 ( .A0(n8006), .A1(n8018), .B0(n8007), .Y(n4422) );
OAI21X4TS U6469 ( .A0(n4429), .A1(n7997), .B0(n4428), .Y(n7770) );
INVX2TS U6470 ( .A(Sgf_operation_ODD1_Q_right[44]), .Y(n4430) );
INVX2TS U6471 ( .A(Sgf_operation_ODD1_Q_left[44]), .Y(n7592) );
INVX2TS U6472 ( .A(Sgf_operation_ODD1_Q_left[43]), .Y(n7603) );
INVX2TS U6473 ( .A(Sgf_operation_ODD1_Q_right[43]), .Y(n4448) );
NOR2X2TS U6474 ( .A(n4462), .B(n4461), .Y(n4591) );
INVX2TS U6475 ( .A(Sgf_operation_ODD1_Q_left[45]), .Y(n7582) );
INVX2TS U6476 ( .A(Sgf_operation_ODD1_Q_right[45]), .Y(n4465) );
CMPR32X2TS U6477 ( .A(Sgf_operation_ODD1_Q_middle[44]), .B(n4430), .C(n7592),
.CO(n4463), .S(n4462) );
NOR2X2TS U6478 ( .A(n4464), .B(n4463), .Y(n4581) );
INVX2TS U6479 ( .A(Sgf_operation_ODD1_Q_left[39]), .Y(n7646) );
INVX2TS U6480 ( .A(Sgf_operation_ODD1_Q_right[39]), .Y(n4445) );
CMPR32X2TS U6481 ( .A(Sgf_operation_ODD1_Q_middle[38]), .B(n7656), .C(n4431),
.CO(n4435), .S(n4129) );
NOR2X2TS U6482 ( .A(n4436), .B(n4435), .Y(n4557) );
NOR2X2TS U6483 ( .A(n4432), .B(n4557), .Y(n4438) );
NOR2X2TS U6484 ( .A(n4434), .B(n4441), .Y(n4476) );
INVX2TS U6485 ( .A(n4476), .Y(n4444) );
NAND2X1TS U6486 ( .A(n4436), .B(n4435), .Y(n4558) );
OAI21X1TS U6487 ( .A0(n4557), .A1(n4553), .B0(n4558), .Y(n4437) );
OAI21X4TS U6488 ( .A0(n4442), .A1(n4441), .B0(n4440), .Y(n4487) );
INVX2TS U6489 ( .A(n4487), .Y(n4443) );
OAI21X4TS U6490 ( .A0(n4488), .A1(n4444), .B0(n4443), .Y(n4567) );
INVX2TS U6491 ( .A(Sgf_operation_ODD1_Q_left[40]), .Y(n7631) );
INVX2TS U6492 ( .A(Sgf_operation_ODD1_Q_right[40]), .Y(n4446) );
CMPR32X2TS U6493 ( .A(Sgf_operation_ODD1_Q_middle[39]), .B(n7646), .C(n4445),
.CO(n4450), .S(n4436) );
INVX2TS U6494 ( .A(Sgf_operation_ODD1_Q_left[41]), .Y(n7622) );
INVX2TS U6495 ( .A(Sgf_operation_ODD1_Q_right[41]), .Y(n4447) );
INVX2TS U6496 ( .A(Sgf_operation_ODD1_Q_left[42]), .Y(n7612) );
INVX2TS U6497 ( .A(Sgf_operation_ODD1_Q_right[42]), .Y(n4449) );
CMPR32X2TS U6498 ( .A(Sgf_operation_ODD1_Q_middle[41]), .B(n7622), .C(n4447),
.CO(n4454), .S(n4453) );
CMPR32X2TS U6499 ( .A(Sgf_operation_ODD1_Q_middle[43]), .B(n7603), .C(n4448),
.CO(n4461), .S(n4457) );
NOR2X2TS U6500 ( .A(n4457), .B(n4456), .Y(n4600) );
NOR2X2TS U6501 ( .A(n4578), .B(n4600), .Y(n4459) );
INVX2TS U6502 ( .A(n4475), .Y(n4460) );
NAND2X1TS U6503 ( .A(n4453), .B(n4452), .Y(n4569) );
NAND2X1TS U6504 ( .A(n4457), .B(n4456), .Y(n4601) );
OAI21X1TS U6505 ( .A0(n4600), .A1(n4596), .B0(n4601), .Y(n4458) );
OAI2BB1X4TS U6506 ( .A0N(n4567), .A1N(n4460), .B0(n4484), .Y(n4580) );
NAND2X1TS U6507 ( .A(n4464), .B(n4463), .Y(n4582) );
AOI21X2TS U6508 ( .A0(n4474), .A1(n4580), .B0(n4481), .Y(n4590) );
INVX2TS U6509 ( .A(Sgf_operation_ODD1_Q_left[46]), .Y(n7569) );
INVX2TS U6510 ( .A(Sgf_operation_ODD1_Q_right[46]), .Y(n4468) );
CMPR32X2TS U6511 ( .A(Sgf_operation_ODD1_Q_middle[45]), .B(n7582), .C(n4465),
.CO(n4466), .S(n4464) );
INVX2TS U6512 ( .A(Sgf_operation_ODD1_Q_left[47]), .Y(n7562) );
INVX2TS U6513 ( .A(Sgf_operation_ODD1_Q_right[47]), .Y(n4489) );
CMPR32X2TS U6514 ( .A(Sgf_operation_ODD1_Q_middle[46]), .B(n7569), .C(n4468),
.CO(n4469), .S(n4467) );
INVX2TS U6515 ( .A(n4478), .Y(n4471) );
NAND2X1TS U6516 ( .A(n4470), .B(n4469), .Y(n4477) );
NAND2X1TS U6517 ( .A(n4471), .B(n4477), .Y(n4472) );
NOR2X2TS U6518 ( .A(n4475), .B(n4483), .Y(n4486) );
NAND2X2TS U6519 ( .A(n4476), .B(n4486), .Y(n4515) );
OAI21X1TS U6520 ( .A0(n4478), .A1(n4587), .B0(n4477), .Y(n4479) );
AOI21X4TS U6521 ( .A0(n4487), .A1(n4486), .B0(n4485), .Y(n4522) );
INVX2TS U6522 ( .A(n4495), .Y(n4508) );
INVX2TS U6523 ( .A(Sgf_operation_ODD1_Q_left[48]), .Y(n7553) );
INVX2TS U6524 ( .A(Sgf_operation_ODD1_Q_right[48]), .Y(n4496) );
CMPR32X2TS U6525 ( .A(Sgf_operation_ODD1_Q_middle[47]), .B(n7562), .C(n4489),
.CO(n4490), .S(n4470) );
NOR2X1TS U6526 ( .A(n4491), .B(n4490), .Y(n4502) );
INVX2TS U6527 ( .A(n4502), .Y(n4494) );
NAND2X1TS U6528 ( .A(n4494), .B(n4504), .Y(n4492) );
XOR2X1TS U6529 ( .A(n4508), .B(n4492), .Y(n4620) );
NOR2X2TS U6530 ( .A(n4620), .B(Sgf_operation_ODD1_Q_left[21]), .Y(n7861) );
INVX2TS U6531 ( .A(n4504), .Y(n4493) );
AOI21X1TS U6532 ( .A0(n4495), .A1(n4494), .B0(n4493), .Y(n4501) );
INVX2TS U6533 ( .A(Sgf_operation_ODD1_Q_left[49]), .Y(n7541) );
INVX2TS U6534 ( .A(Sgf_operation_ODD1_Q_right[49]), .Y(n4509) );
CMPR32X2TS U6535 ( .A(Sgf_operation_ODD1_Q_middle[48]), .B(n7553), .C(n4496),
.CO(n4497), .S(n4491) );
NOR2X2TS U6536 ( .A(n4498), .B(n4497), .Y(n4505) );
INVX2TS U6537 ( .A(n4505), .Y(n4499) );
NAND2X1TS U6538 ( .A(n4498), .B(n4497), .Y(n4503) );
NAND2X1TS U6539 ( .A(n4499), .B(n4503), .Y(n4500) );
XOR2X1TS U6540 ( .A(n4501), .B(n4500), .Y(n4621) );
NOR2X2TS U6541 ( .A(n4621), .B(Sgf_operation_ODD1_Q_left[22]), .Y(n7833) );
INVX2TS U6542 ( .A(n4514), .Y(n4507) );
OAI21X1TS U6543 ( .A0(n4505), .A1(n4504), .B0(n4503), .Y(n4519) );
INVX2TS U6544 ( .A(Sgf_operation_ODD1_Q_left[50]), .Y(n7511) );
INVX2TS U6545 ( .A(Sgf_operation_ODD1_Q_right[50]), .Y(n4526) );
CMPR32X2TS U6546 ( .A(Sgf_operation_ODD1_Q_middle[49]), .B(n7541), .C(n4509),
.CO(n4510), .S(n4498) );
NAND2X1TS U6547 ( .A(n4511), .B(n4510), .Y(n4516) );
NAND2X1TS U6548 ( .A(n4518), .B(n4516), .Y(n4512) );
NOR2X2TS U6549 ( .A(n4622), .B(Sgf_operation_ODD1_Q_left[23]), .Y(n7835) );
NOR2X2TS U6550 ( .A(n4515), .B(n4521), .Y(n4524) );
INVX2TS U6551 ( .A(n4516), .Y(n4517) );
AOI21X1TS U6552 ( .A0(n4519), .A1(n4518), .B0(n4517), .Y(n4520) );
AOI21X4TS U6553 ( .A0(n4525), .A1(n4524), .B0(n4523), .Y(n4533) );
INVX2TS U6554 ( .A(Sgf_operation_ODD1_Q_left[51]), .Y(n5070) );
INVX2TS U6555 ( .A(Sgf_operation_ODD1_Q_right[51]), .Y(n4534) );
CMPR32X2TS U6556 ( .A(Sgf_operation_ODD1_Q_middle[50]), .B(n7511), .C(n4526),
.CO(n4527), .S(n4511) );
NOR2X1TS U6557 ( .A(n4528), .B(n4527), .Y(n4532) );
INVX2TS U6558 ( .A(n4532), .Y(n4529) );
NAND2X1TS U6559 ( .A(n4529), .B(n4531), .Y(n4530) );
XOR2X1TS U6560 ( .A(n4533), .B(n4530), .Y(n4625) );
NOR2X2TS U6561 ( .A(n4625), .B(Sgf_operation_ODD1_Q_left[24]), .Y(n7815) );
OAI21X4TS U6562 ( .A0(n4533), .A1(n4532), .B0(n4531), .Y(n4541) );
INVX2TS U6563 ( .A(Sgf_operation_ODD1_Q_right[52]), .Y(n4542) );
XNOR2X1TS U6564 ( .A(n4542), .B(Sgf_operation_ODD1_Q_middle[52]), .Y(n4536)
);
CMPR32X2TS U6565 ( .A(Sgf_operation_ODD1_Q_middle[51]), .B(n5070), .C(n4534),
.CO(n4535), .S(n4528) );
NAND2X1TS U6566 ( .A(n4540), .B(n4538), .Y(n4537) );
XNOR2X1TS U6567 ( .A(n4541), .B(n4537), .Y(n4626) );
NOR2X2TS U6568 ( .A(n4626), .B(Sgf_operation_ODD1_Q_left[25]), .Y(n7804) );
NOR2X2TS U6569 ( .A(n7815), .B(n7804), .Y(n7779) );
INVX2TS U6570 ( .A(n4538), .Y(n4539) );
AOI21X4TS U6571 ( .A0(n4541), .A1(n4540), .B0(n4539), .Y(n4549) );
INVX2TS U6572 ( .A(Sgf_operation_ODD1_Q_right[53]), .Y(n4550) );
XNOR2X1TS U6573 ( .A(n4550), .B(Sgf_operation_ODD1_Q_middle[53]), .Y(n4544)
);
INVX2TS U6574 ( .A(n4548), .Y(n4545) );
NAND2X1TS U6575 ( .A(n4545), .B(n4547), .Y(n4546) );
NOR2X2TS U6576 ( .A(n4627), .B(Sgf_operation_ODD1_Q_left[26]), .Y(n7791) );
NAND2X1TS U6577 ( .A(n4638), .B(n4636), .Y(n4552) );
XNOR2X4TS U6578 ( .A(n4639), .B(n4552), .Y(n4628) );
NOR2X2TS U6579 ( .A(n4628), .B(Sgf_operation_ODD1_Q_left[27]), .Y(n7780) );
INVX2TS U6580 ( .A(n4553), .Y(n4554) );
AOI21X2TS U6581 ( .A0(n4556), .A1(n4555), .B0(n4554), .Y(n4561) );
NAND2X1TS U6582 ( .A(n4559), .B(n4558), .Y(n4560) );
NOR2X2TS U6583 ( .A(n4605), .B(Sgf_operation_ODD1_Q_left[12]), .Y(n7983) );
INVX2TS U6584 ( .A(n4562), .Y(n4566) );
NAND2X1TS U6585 ( .A(n4566), .B(n4564), .Y(n4563) );
XOR2X1TS U6586 ( .A(n4577), .B(n4563), .Y(n4606) );
NOR2X2TS U6587 ( .A(n4606), .B(Sgf_operation_ODD1_Q_left[13]), .Y(n7972) );
INVX2TS U6588 ( .A(n4564), .Y(n4565) );
AOI21X1TS U6589 ( .A0(n4567), .A1(n4566), .B0(n4565), .Y(n4572) );
NAND2X1TS U6590 ( .A(n4570), .B(n4569), .Y(n4571) );
NOR2X2TS U6591 ( .A(n4607), .B(Sgf_operation_ODD1_Q_left[14]), .Y(n7948) );
INVX2TS U6592 ( .A(n4573), .Y(n4576) );
INVX2TS U6593 ( .A(n4578), .Y(n4598) );
NAND2X1TS U6594 ( .A(n4598), .B(n4596), .Y(n4579) );
XNOR2X1TS U6595 ( .A(n4599), .B(n4579), .Y(n4608) );
NOR2X2TS U6596 ( .A(n4608), .B(Sgf_operation_ODD1_Q_left[15]), .Y(n7950) );
NAND2X2TS U6597 ( .A(n7944), .B(n4610), .Y(n7886) );
INVX2TS U6598 ( .A(n4581), .Y(n4583) );
NAND2X1TS U6599 ( .A(n4583), .B(n4582), .Y(n4584) );
NOR2X2TS U6600 ( .A(n4613), .B(Sgf_operation_ODD1_Q_left[18]), .Y(n7891) );
INVX2TS U6601 ( .A(n4586), .Y(n4588) );
NAND2X1TS U6602 ( .A(n4588), .B(n4587), .Y(n4589) );
INVX2TS U6603 ( .A(n4591), .Y(n4593) );
NAND2X1TS U6604 ( .A(n4593), .B(n4592), .Y(n4594) );
NOR2X2TS U6605 ( .A(n4612), .B(Sgf_operation_ODD1_Q_left[17]), .Y(n7919) );
INVX2TS U6606 ( .A(n4596), .Y(n4597) );
NAND2X1TS U6607 ( .A(n4602), .B(n4601), .Y(n4603) );
CLKXOR2X2TS U6608 ( .A(n4604), .B(n4603), .Y(n4611) );
NOR2X2TS U6609 ( .A(n4611), .B(Sgf_operation_ODD1_Q_left[16]), .Y(n7916) );
NOR2X4TS U6610 ( .A(n7886), .B(n4618), .Y(n7771) );
NAND2X4TS U6611 ( .A(n4634), .B(n7771), .Y(n5062) );
NAND2X1TS U6612 ( .A(n4606), .B(Sgf_operation_ODD1_Q_left[13]), .Y(n7973) );
NAND2X1TS U6613 ( .A(n4608), .B(Sgf_operation_ODD1_Q_left[15]), .Y(n7951) );
AOI21X2TS U6614 ( .A0(n7945), .A1(n4610), .B0(n4609), .Y(n7885) );
NAND2X1TS U6615 ( .A(n4612), .B(Sgf_operation_ODD1_Q_left[17]), .Y(n7920) );
NAND2X1TS U6616 ( .A(n4614), .B(Sgf_operation_ODD1_Q_left[19]), .Y(n7894) );
AOI21X2TS U6617 ( .A0(n7888), .A1(n4616), .B0(n4615), .Y(n4617) );
OAI21X4TS U6618 ( .A0(n7885), .A1(n4618), .B0(n4617), .Y(n7772) );
NAND2X2TS U6619 ( .A(n4619), .B(Sgf_operation_ODD1_Q_left[20]), .Y(n7872) );
NAND2X1TS U6620 ( .A(n4620), .B(Sgf_operation_ODD1_Q_left[21]), .Y(n7862) );
OAI21X2TS U6621 ( .A0(n7861), .A1(n7872), .B0(n7862), .Y(n7830) );
NAND2X1TS U6622 ( .A(n4622), .B(Sgf_operation_ODD1_Q_left[23]), .Y(n7836) );
NAND2X1TS U6623 ( .A(n4626), .B(Sgf_operation_ODD1_Q_left[25]), .Y(n7805) );
OAI21X2TS U6624 ( .A0(n7804), .A1(n7816), .B0(n7805), .Y(n7778) );
OAI21X2TS U6625 ( .A0(n7780), .A1(n7792), .B0(n7781), .Y(n4629) );
AOI21X4TS U6626 ( .A0(n7772), .A1(n4634), .B0(n4633), .Y(n5067) );
OAI2BB1X4TS U6627 ( .A0N(n7770), .A1N(n4635), .B0(n5067), .Y(n7577) );
XOR2X4TS U6628 ( .A(n4641), .B(Sgf_operation_ODD1_Q_middle[55]), .Y(n4642)
);
INVX2TS U6629 ( .A(Sgf_operation_ODD1_Q_middle[55]), .Y(n4640) );
AND2X4TS U6630 ( .A(n4641), .B(n4640), .Y(n4643) );
NOR2X4TS U6631 ( .A(n7755), .B(n7744), .Y(n5061) );
NAND2X2TS U6632 ( .A(n4642), .B(Sgf_operation_ODD1_Q_left[28]), .Y(n7756) );
OAI21X4TS U6633 ( .A0(n7756), .A1(n7744), .B0(n7745), .Y(n5064) );
AOI21X4TS U6634 ( .A0(n7577), .A1(n5061), .B0(n5064), .Y(n7600) );
NAND2X1TS U6635 ( .A(Sgf_operation_ODD1_Q_left[30]), .B(
Sgf_operation_ODD1_Q_left[31]), .Y(n7700) );
NAND2X1TS U6636 ( .A(Sgf_operation_ODD1_Q_left[32]), .B(
Sgf_operation_ODD1_Q_left[33]), .Y(n4644) );
INVX2TS U6637 ( .A(n5059), .Y(n4645) );
NAND2X1TS U6638 ( .A(Sgf_operation_ODD1_Q_left[34]), .B(
Sgf_operation_ODD1_Q_left[35]), .Y(n5057) );
INVX2TS U6639 ( .A(n5057), .Y(n4646) );
NAND2X4TS U6640 ( .A(n7683), .B(n4646), .Y(n7674) );
XNOR2X4TS U6641 ( .A(n4648), .B(n4647), .Y(n4650) );
INVX2TS U6642 ( .A(n7238), .Y(n4651) );
NAND2X1TS U6643 ( .A(n4651), .B(n7237), .Y(n4652) );
NAND3X4TS U6644 ( .A(n4655), .B(n4654), .C(n4653), .Y(n5594) );
AOI222X1TS U6645 ( .A0(n5825), .A1(n831), .B0(n867), .B1(n5858), .C0(n5997),
.C1(n5856), .Y(n4656) );
OAI21X1TS U6646 ( .A0(n979), .A1(n6007), .B0(n4656), .Y(n4657) );
XOR2X1TS U6647 ( .A(n4657), .B(n7498), .Y(n4670) );
AOI22X2TS U6648 ( .A0(n5845), .A1(n6054), .B0(n5494), .B1(n4966), .Y(n4660)
);
OAI21X2TS U6649 ( .A0(n6062), .A1(n5491), .B0(n4660), .Y(n4661) );
XOR2X2TS U6650 ( .A(n4661), .B(n5847), .Y(n4678) );
OAI21X1TS U6651 ( .A0(n5437), .A1(n5491), .B0(n4662), .Y(n4663) );
XOR2X1TS U6652 ( .A(n4663), .B(n5847), .Y(n5203) );
AOI222X1TS U6653 ( .A0(n6012), .A1(n5758), .B0(n5564), .B1(n8376), .C0(n6010), .C1(n8375), .Y(n4666) );
OAI21X1TS U6654 ( .A0(n5931), .A1(n6014), .B0(n4666), .Y(n4667) );
XOR2X1TS U6655 ( .A(n4667), .B(n5567), .Y(n4668) );
ADDFHX2TS U6656 ( .A(n4670), .B(n4669), .CI(n4668), .CO(mult_x_23_n872), .S(
mult_x_23_n873) );
XOR2X2TS U6657 ( .A(n4674), .B(n5567), .Y(n4686) );
ADDHX1TS U6658 ( .A(n4679), .B(n4678), .CO(n5204), .S(n4691) );
AOI222X1TS U6659 ( .A0(n6012), .A1(n7510), .B0(n5564), .B1(Op_MY[30]), .C0(
n5560), .C1(n5843), .Y(n4680) );
ADDHX1TS U6660 ( .A(n7493), .B(n4682), .CO(n4679), .S(n5140) );
AOI222X1TS U6661 ( .A0(n6012), .A1(n8375), .B0(n5564), .B1(n6055), .C0(n5560), .C1(n5839), .Y(n4683) );
OAI21X1TS U6662 ( .A0(n1001), .A1(n5924), .B0(n4683), .Y(n4684) );
AOI222X1TS U6663 ( .A0(n6012), .A1(n5843), .B0(n5564), .B1(n5839), .C0(n5560), .C1(n5213), .Y(n4687) );
INVX2TS U6664 ( .A(n904), .Y(n4698) );
OAI21X4TS U6665 ( .A0(n4999), .A1(n4991), .B0(n4993), .Y(n5600) );
INVX2TS U6666 ( .A(n4700), .Y(n5599) );
XOR2X4TS U6667 ( .A(n5600), .B(n4701), .Y(n5876) );
BUFX3TS U6668 ( .A(Op_MY[39]), .Y(n5796) );
BUFX3TS U6669 ( .A(Op_MY[38]), .Y(n5982) );
INVX2TS U6670 ( .A(n4702), .Y(n6017) );
OAI21X1TS U6671 ( .A0(n5876), .A1(n6067), .B0(n4703), .Y(n4704) );
XNOR2X4TS U6672 ( .A(Op_MY[18]), .B(n7503), .Y(n4736) );
NOR2BX4TS U6673 ( .AN(n4736), .B(n4735), .Y(n5075) );
BUFX3TS U6674 ( .A(n6861), .Y(n7494) );
OAI21X2TS U6675 ( .A0(n7013), .A1(n764), .B0(n4707), .Y(n4708) );
XNOR2X4TS U6676 ( .A(Op_MY[15]), .B(Op_MY[14]), .Y(n4709) );
XOR2X4TS U6677 ( .A(n835), .B(Op_MY[16]), .Y(n4711) );
BUFX4TS U6678 ( .A(n5087), .Y(n6964) );
XNOR2X2TS U6679 ( .A(Op_MY[15]), .B(Op_MY[16]), .Y(n4710) );
AOI222X1TS U6680 ( .A0(n6964), .A1(n6888), .B0(n6786), .B1(n6886), .C0(n6531), .C1(n6897), .Y(n4712) );
OAI21X1TS U6681 ( .A0(n6900), .A1(n6809), .B0(n4712), .Y(n4713) );
CLKBUFX2TS U6682 ( .A(n8444), .Y(n6517) );
XOR2X1TS U6683 ( .A(n4713), .B(n893), .Y(n4725) );
AOI222X1TS U6684 ( .A0(n6964), .A1(n7042), .B0(n6786), .B1(n7022), .C0(n6531), .C1(n7020), .Y(n4715) );
NAND2X2TS U6685 ( .A(n6796), .B(n825), .Y(n4718) );
OAI21X2TS U6686 ( .A0(n6966), .A1(n764), .B0(n4718), .Y(n4719) );
AOI22X1TS U6687 ( .A0(n6512), .A1(n5041), .B0(n6796), .B1(n6822), .Y(n4720)
);
OAI21X2TS U6688 ( .A0(n5043), .A1(n6788), .B0(n4720), .Y(n4721) );
XOR2X1TS U6689 ( .A(n4723), .B(n892), .Y(n7092) );
ADDFHX2TS U6690 ( .A(n4726), .B(n4725), .CI(n4724), .CO(mult_x_24_n991), .S(
mult_x_24_n992) );
INVX2TS U6691 ( .A(n6217), .Y(n6223) );
NAND2X2TS U6692 ( .A(n6268), .B(n4731), .Y(n4733) );
INVX2TS U6693 ( .A(n6249), .Y(n4729) );
OAI21X4TS U6694 ( .A0(n4733), .A1(n740), .B0(n4732), .Y(n4734) );
AND3X4TS U6695 ( .A(n4737), .B(n4736), .C(n4735), .Y(n5076) );
NAND2X1TS U6696 ( .A(n6491), .B(n6989), .Y(n4738) );
XOR2X1TS U6697 ( .A(n4739), .B(n6220), .Y(n4740) );
NOR2X4TS U6698 ( .A(n4743), .B(n4742), .Y(n6238) );
XOR2X2TS U6699 ( .A(n4744), .B(n6882), .Y(n4811) );
OAI21X2TS U6700 ( .A0(n6925), .A1(n764), .B0(n4745), .Y(n4746) );
XOR2X2TS U6701 ( .A(n4746), .B(n7064), .Y(n4800) );
OAI21X1TS U6702 ( .A0(n7026), .A1(n7062), .B0(n4747), .Y(n4748) );
AOI222X1TS U6703 ( .A0(n6870), .A1(n7035), .B0(n6869), .B1(n7033), .C0(n5076), .C1(n6875), .Y(n4750) );
XNOR2X4TS U6704 ( .A(Op_MY[21]), .B(Op_MY[20]), .Y(n4753) );
XOR2X4TS U6705 ( .A(Op_MY[23]), .B(Op_MY[22]), .Y(n4754) );
NAND2BX4TS U6706 ( .AN(n4753), .B(n4754), .Y(n4805) );
NOR2X4TS U6707 ( .A(n4754), .B(n4753), .Y(n4803) );
BUFX3TS U6708 ( .A(n4803), .Y(n6761) );
XNOR2X2TS U6709 ( .A(Op_MY[21]), .B(Op_MY[22]), .Y(n4752) );
NOR2BX4TS U6710 ( .AN(n4753), .B(n4752), .Y(n6454) );
AND3X6TS U6711 ( .A(n4754), .B(n4753), .C(n4752), .Y(n6405) );
AOI222X1TS U6712 ( .A0(n6761), .A1(n6859), .B0(n7070), .B1(n7044), .C0(n6473), .C1(n6584), .Y(n4755) );
OAI21X1TS U6713 ( .A0(n7050), .A1(n6763), .B0(n4755), .Y(n4756) );
XOR2X1TS U6714 ( .A(n4756), .B(n836), .Y(n4757) );
NAND2X1TS U6715 ( .A(n4764), .B(n4855), .Y(n4765) );
INVX8TS U6716 ( .A(n4766), .Y(n5280) );
INVX2TS U6717 ( .A(n4898), .Y(n4787) );
INVX2TS U6718 ( .A(n4767), .Y(n4900) );
NAND2X1TS U6719 ( .A(n4787), .B(n4900), .Y(n4770) );
INVX2TS U6720 ( .A(n4899), .Y(n4768) );
AOI21X1TS U6721 ( .A0(n4790), .A1(n4900), .B0(n4768), .Y(n4769) );
OAI21X2TS U6722 ( .A0(n5280), .A1(n4770), .B0(n4769), .Y(n4775) );
INVX2TS U6723 ( .A(n4771), .Y(n4773) );
NAND2X1TS U6724 ( .A(n4773), .B(n4772), .Y(n4774) );
INVX2TS U6725 ( .A(n4789), .Y(n4776) );
NOR2X2TS U6726 ( .A(n4776), .B(n4793), .Y(n4779) );
NAND2X1TS U6727 ( .A(n4779), .B(n4787), .Y(n4781) );
INVX2TS U6728 ( .A(n4788), .Y(n4777) );
INVX2TS U6729 ( .A(n4782), .Y(n4784) );
NAND2X1TS U6730 ( .A(n4784), .B(n4783), .Y(n4785) );
NAND2X1TS U6731 ( .A(n4787), .B(n4789), .Y(n4792) );
AOI21X1TS U6732 ( .A0(n4790), .A1(n4789), .B0(n4788), .Y(n4791) );
OAI21X2TS U6733 ( .A0(n5280), .A1(n4792), .B0(n4791), .Y(n4797) );
INVX2TS U6734 ( .A(n4793), .Y(n4795) );
NAND2X1TS U6735 ( .A(n4795), .B(n4794), .Y(n4796) );
BUFX4TS U6736 ( .A(n4803), .Y(n7072) );
OAI21X1TS U6737 ( .A0(n6824), .A1(n7074), .B0(n4801), .Y(n4802) );
CLKXOR2X2TS U6738 ( .A(n4802), .B(n7076), .Y(n4815) );
BUFX8TS U6739 ( .A(n4803), .Y(n6736) );
OAI21X2TS U6740 ( .A0(n5043), .A1(n7074), .B0(n994), .Y(n4804) );
OAI21X2TS U6741 ( .A0(n6442), .A1(n764), .B0(n4806), .Y(n4807) );
AOI222X1TS U6742 ( .A0(n7072), .A1(n7022), .B0(n7070), .B1(n905), .C0(n6473),
.C1(n7018), .Y(n4808) );
OAI21X2TS U6743 ( .A0(n7026), .A1(n7074), .B0(n4808), .Y(n4809) );
ADDHX1TS U6744 ( .A(n4811), .B(n4810), .CO(n6939), .S(n4819) );
AOI222X1TS U6745 ( .A0(n7072), .A1(n7044), .B0(n7070), .B1(n6886), .C0(n6473), .C1(n6897), .Y(n4812) );
OAI21X1TS U6746 ( .A0(n6900), .A1(n6763), .B0(n4812), .Y(n4813) );
XOR2X1TS U6747 ( .A(n4813), .B(n836), .Y(n4818) );
ADDFHX2TS U6748 ( .A(n4816), .B(n4815), .CI(n4814), .CO(n4817), .S(
mult_x_24_n939) );
ADDFHX2TS U6749 ( .A(n4819), .B(n4818), .CI(n4817), .CO(mult_x_24_n925), .S(
mult_x_24_n926) );
NAND2X4TS U6750 ( .A(n4821), .B(n4824), .Y(n7305) );
NAND2X2TS U6751 ( .A(n7323), .B(n4828), .Y(n4830) );
INVX2TS U6752 ( .A(n4822), .Y(n7293) );
AOI21X4TS U6753 ( .A0(n4825), .A1(n4824), .B0(n4823), .Y(n7306) );
XOR2X4TS U6754 ( .A(n4833), .B(n1004), .Y(Sgf_operation_ODD1_middle_N53) );
NAND2X1TS U6755 ( .A(n5221), .B(n4862), .Y(n4836) );
INVX8TS U6756 ( .A(n5249), .Y(n5225) );
AOI21X1TS U6757 ( .A0(n5225), .A1(n4862), .B0(n4864), .Y(n4835) );
OAI21X2TS U6758 ( .A0(n6092), .A1(n4836), .B0(n4835), .Y(n4839) );
NAND2X1TS U6759 ( .A(n4837), .B(n4886), .Y(n4838) );
XNOR2X4TS U6760 ( .A(n4839), .B(n4838), .Y(Sgf_operation_ODD1_right_N38) );
NOR2X1TS U6761 ( .A(n4840), .B(n5220), .Y(n4842) );
NAND2X1TS U6762 ( .A(n5221), .B(n4842), .Y(n4844) );
AOI21X1TS U6763 ( .A0(n5225), .A1(n4842), .B0(n4841), .Y(n4843) );
OAI21X2TS U6764 ( .A0(n6092), .A1(n4844), .B0(n4843), .Y(n4848) );
NAND2X1TS U6765 ( .A(n4846), .B(n4845), .Y(n4847) );
XNOR2X4TS U6766 ( .A(n4848), .B(n4847), .Y(Sgf_operation_ODD1_right_N37) );
NAND2X1TS U6767 ( .A(n5221), .B(n788), .Y(n4851) );
AOI21X1TS U6768 ( .A0(n5225), .A1(n788), .B0(n4849), .Y(n4850) );
OAI21X2TS U6769 ( .A0(n6092), .A1(n4851), .B0(n4850), .Y(n4854) );
NAND2X1TS U6770 ( .A(n768), .B(n4852), .Y(n4853) );
XNOR2X4TS U6771 ( .A(n4854), .B(n4853), .Y(Sgf_operation_ODD1_right_N35) );
INVX2TS U6772 ( .A(n4857), .Y(n4859) );
NAND2X1TS U6773 ( .A(n4859), .B(n4858), .Y(n4860) );
INVX2TS U6774 ( .A(n4877), .Y(n4863) );
INVX4TS U6775 ( .A(n4864), .Y(n4888) );
INVX2TS U6776 ( .A(n4876), .Y(n4866) );
AOI21X2TS U6777 ( .A0(n4870), .A1(n5225), .B0(n4869), .Y(n4871) );
OAI21X2TS U6778 ( .A0(n6092), .A1(n4872), .B0(n4871), .Y(n4875) );
NAND2X1TS U6779 ( .A(n4873), .B(n1027), .Y(n4874) );
XNOR2X4TS U6780 ( .A(n4875), .B(n4874), .Y(Sgf_operation_ODD1_right_N41) );
NAND2X1TS U6781 ( .A(n1028), .B(n4882), .Y(n4883) );
NOR2X1TS U6782 ( .A(n4885), .B(n4887), .Y(n4890) );
NAND2X2TS U6783 ( .A(n4890), .B(n5221), .Y(n4892) );
OAI21X1TS U6784 ( .A0(n4888), .A1(n4887), .B0(n4886), .Y(n4889) );
NAND2X1TS U6785 ( .A(n784), .B(n4894), .Y(n4895) );
OAI21X1TS U6786 ( .A0(n5280), .A1(n4898), .B0(n4897), .Y(n4902) );
NAND2X1TS U6787 ( .A(n4900), .B(n4899), .Y(n4901) );
XNOR2X2TS U6788 ( .A(n4902), .B(n4901), .Y(Sgf_operation_ODD1_left_N31) );
OAI21X1TS U6789 ( .A0(n5280), .A1(n5285), .B0(n5286), .Y(n4907) );
INVX2TS U6790 ( .A(n4903), .Y(n4905) );
NAND2X1TS U6791 ( .A(n4905), .B(n4904), .Y(n4906) );
XNOR2X2TS U6792 ( .A(n4907), .B(n4906), .Y(Sgf_operation_ODD1_left_N28) );
INVX2TS U6793 ( .A(n4908), .Y(n5282) );
NAND2X1TS U6794 ( .A(n5276), .B(n5282), .Y(n4911) );
INVX2TS U6795 ( .A(n5281), .Y(n4909) );
AOI21X1TS U6796 ( .A0(n5277), .A1(n5282), .B0(n4909), .Y(n4910) );
OAI21X1TS U6797 ( .A0(n5280), .A1(n4911), .B0(n4910), .Y(n4916) );
INVX2TS U6798 ( .A(n4912), .Y(n4914) );
NAND2X1TS U6799 ( .A(n4914), .B(n4913), .Y(n4915) );
XNOR2X2TS U6800 ( .A(n4916), .B(n4915), .Y(Sgf_operation_ODD1_left_N30) );
INVX2TS U6801 ( .A(n4917), .Y(n5152) );
INVX2TS U6802 ( .A(n4918), .Y(n5155) );
OAI21X2TS U6803 ( .A0(n924), .A1(n5152), .B0(n5155), .Y(n4920) );
INVX2TS U6804 ( .A(n5154), .Y(n4919) );
INVX2TS U6805 ( .A(n4921), .Y(n4925) );
INVX2TS U6806 ( .A(n4922), .Y(n4963) );
INVX2TS U6807 ( .A(n4923), .Y(n4924) );
OAI21X4TS U6808 ( .A0(n5164), .A1(n4925), .B0(n4924), .Y(n4959) );
INVX2TS U6809 ( .A(n4962), .Y(n4926) );
OAI21X2TS U6810 ( .A0(n5271), .A1(n4928), .B0(n4927), .Y(n4932) );
INVX2TS U6811 ( .A(n4929), .Y(n4931) );
XOR2X4TS U6812 ( .A(n4932), .B(n980), .Y(Sgf_operation_ODD1_left_N50) );
INVX2TS U6813 ( .A(n4949), .Y(n4933) );
NOR2X2TS U6814 ( .A(n4933), .B(n4935), .Y(n4938) );
INVX2TS U6815 ( .A(n5163), .Y(n4945) );
NAND2X2TS U6816 ( .A(n4938), .B(n4945), .Y(n4940) );
NOR2X2TS U6817 ( .A(n5161), .B(n4940), .Y(n5256) );
INVX2TS U6818 ( .A(n5256), .Y(n4942) );
INVX2TS U6819 ( .A(n4948), .Y(n4936) );
OAI21X4TS U6820 ( .A0(n5164), .A1(n4940), .B0(n4939), .Y(n5259) );
INVX2TS U6821 ( .A(n5259), .Y(n4941) );
OAI21X2TS U6822 ( .A0(n924), .A1(n4942), .B0(n4941), .Y(n4944) );
NAND2X2TS U6823 ( .A(n4945), .B(n4949), .Y(n4947) );
NOR2X2TS U6824 ( .A(n5161), .B(n4947), .Y(n5265) );
INVX2TS U6825 ( .A(n5265), .Y(n4955) );
INVX2TS U6826 ( .A(n4946), .Y(n4953) );
INVX2TS U6827 ( .A(n4947), .Y(n4952) );
AOI21X1TS U6828 ( .A0(n4950), .A1(n4949), .B0(n4948), .Y(n4951) );
OAI2BB1X4TS U6829 ( .A0N(n4953), .A1N(n4952), .B0(n4951), .Y(n5268) );
INVX2TS U6830 ( .A(n5268), .Y(n4954) );
OAI21X2TS U6831 ( .A0(n5271), .A1(n4955), .B0(n4954), .Y(n4957) );
XOR2X4TS U6832 ( .A(n4957), .B(n1033), .Y(Sgf_operation_ODD1_left_N45) );
INVX2TS U6833 ( .A(n4958), .Y(n4961) );
INVX2TS U6834 ( .A(n4959), .Y(n4960) );
OAI21X2TS U6835 ( .A0(n5271), .A1(n4961), .B0(n4960), .Y(n4964) );
XOR2X4TS U6836 ( .A(n4964), .B(n967), .Y(Sgf_operation_ODD1_left_N49) );
AOI22X1TS U6837 ( .A0(n6065), .A1(n6054), .B0(n4967), .B1(n4966), .Y(n4968)
);
OAI21X2TS U6838 ( .A0(n6062), .A1(n4965), .B0(n4968), .Y(n4969) );
XOR2X2TS U6839 ( .A(n4969), .B(n6069), .Y(n5212) );
XOR2X2TS U6840 ( .A(n4971), .B(n6069), .Y(n5909) );
INVX2TS U6841 ( .A(n4972), .Y(n4973) );
OAI2BB1X4TS U6842 ( .A0N(n4975), .A1N(n4974), .B0(n4973), .Y(n4983) );
INVX2TS U6843 ( .A(n4976), .Y(n4982) );
XOR2X4TS U6844 ( .A(n4983), .B(n4977), .Y(n5957) );
AND2X2TS U6845 ( .A(n5899), .B(n850), .Y(n4978) );
AOI21X1TS U6846 ( .A0(n5902), .A1(n8385), .B0(n4978), .Y(n4979) );
INVX2TS U6847 ( .A(mult_x_23_n714), .Y(n5007) );
INVX2TS U6848 ( .A(n4980), .Y(n4981) );
INVX1TS U6849 ( .A(n4984), .Y(n4986) );
NAND2X1TS U6850 ( .A(n4986), .B(n4985), .Y(n4987) );
XNOR2X4TS U6851 ( .A(n4988), .B(n4987), .Y(n6008) );
AOI21X1TS U6852 ( .A0(n5902), .A1(n850), .B0(n4989), .Y(n4990) );
OAI21X1TS U6853 ( .A0(n6008), .A1(n5904), .B0(n4990), .Y(n5006) );
INVX2TS U6854 ( .A(n4991), .Y(n4992) );
INVX2TS U6855 ( .A(n4993), .Y(n4996) );
AOI21X4TS U6856 ( .A0(n4996), .A1(n4995), .B0(n4994), .Y(n4997) );
OAI21X4TS U6857 ( .A0(n4999), .A1(n4998), .B0(n4997), .Y(n5479) );
INVX2TS U6858 ( .A(n5000), .Y(n5478) );
NAND2X1TS U6859 ( .A(n5478), .B(n5476), .Y(n5001) );
XNOR2X4TS U6860 ( .A(n5479), .B(n5001), .Y(n5002) );
BUFX3TS U6861 ( .A(Op_MY[41]), .Y(n5790) );
BUFX3TS U6862 ( .A(Op_MY[40]), .Y(n6032) );
AOI222X1TS U6863 ( .A0(n6065), .A1(n5790), .B0(n6064), .B1(n6032), .C0(n6017), .C1(n828), .Y(n5003) );
OAI21X1TS U6864 ( .A0(n5792), .A1(n5470), .B0(n5003), .Y(n5004) );
XOR2X1TS U6865 ( .A(n5004), .B(n6069), .Y(n5005) );
ADDFHX2TS U6866 ( .A(n5007), .B(n5006), .CI(n5005), .CO(mult_x_23_n712), .S(
mult_x_23_n713) );
XNOR2X4TS U6867 ( .A(Op_MY[9]), .B(n7040), .Y(n5035) );
NAND2BX4TS U6868 ( .AN(n5035), .B(n5036), .Y(n5045) );
XNOR2X2TS U6869 ( .A(Op_MY[9]), .B(Op_MY[10]), .Y(n5034) );
NOR2BX4TS U6870 ( .AN(n5035), .B(n5034), .Y(n6589) );
NOR2X4TS U6871 ( .A(n5036), .B(n5035), .Y(n6608) );
BUFX12TS U6872 ( .A(n6608), .Y(n6848) );
AOI22X1TS U6873 ( .A0(n6589), .A1(n5041), .B0(n6848), .B1(n905), .Y(n5008)
);
XOR2X2TS U6874 ( .A(n5009), .B(n7051), .Y(n5033) );
NAND2X2TS U6875 ( .A(n6848), .B(n5041), .Y(n5010) );
INVX2TS U6876 ( .A(n5012), .Y(n5015) );
INVX2TS U6877 ( .A(n5013), .Y(n5014) );
OAI21X2TS U6878 ( .A0(n815), .A1(n5015), .B0(n5014), .Y(n5019) );
NAND2X1TS U6879 ( .A(n5017), .B(n5016), .Y(n5018) );
XNOR2X4TS U6880 ( .A(n5019), .B(n5018), .Y(Sgf_operation_ODD1_right_N47) );
INVX2TS U6881 ( .A(n5112), .Y(n5021) );
INVX2TS U6882 ( .A(n5121), .Y(n5020) );
OAI21X2TS U6883 ( .A0(n815), .A1(n5021), .B0(n5020), .Y(n5025) );
NAND2X1TS U6884 ( .A(n5023), .B(n5022), .Y(n5024) );
XNOR2X4TS U6885 ( .A(n5025), .B(n5024), .Y(Sgf_operation_ODD1_right_N49) );
OAI21X2TS U6886 ( .A0(n815), .A1(n5027), .B0(n5026), .Y(n5031) );
NAND2X1TS U6887 ( .A(n5029), .B(n5028), .Y(n5030) );
XNOR2X4TS U6888 ( .A(n5031), .B(n5030), .Y(Sgf_operation_ODD1_right_N46) );
BUFX4TS U6889 ( .A(n6608), .Y(n6839) );
XOR2X1TS U6890 ( .A(n5038), .B(n7051), .Y(n5051) );
XNOR2X4TS U6891 ( .A(Op_MY[12]), .B(Op_MY[11]), .Y(n5083) );
XOR2X4TS U6892 ( .A(Op_MY[13]), .B(n7490), .Y(n5084) );
NAND2BX4TS U6893 ( .AN(n5083), .B(n5084), .Y(n5081) );
NOR2X4TS U6894 ( .A(n5084), .B(n5083), .Y(n6544) );
BUFX8TS U6895 ( .A(n6544), .Y(n6771) );
NAND2X2TS U6896 ( .A(n6771), .B(n5041), .Y(n5039) );
XNOR2X2TS U6897 ( .A(Op_MY[12]), .B(Op_MY[13]), .Y(n5082) );
OAI21X1TS U6898 ( .A0(n5043), .A1(n7025), .B0(n5042), .Y(n5044) );
OAI21X1TS U6899 ( .A0(n6900), .A1(n7049), .B0(n5046), .Y(n5047) );
XOR2X1TS U6900 ( .A(n5047), .B(n7051), .Y(n5054) );
ADDHX1TS U6901 ( .A(n7490), .B(n5048), .CO(n7017), .S(n6988) );
AOI222X1TS U6902 ( .A0(n6839), .A1(n7042), .B0(n7045), .B1(n7022), .C0(n6615), .C1(n6822), .Y(n5049) );
OAI21X1TS U6903 ( .A0(n6824), .A1(n6841), .B0(n5049), .Y(n5050) );
XOR2X1TS U6904 ( .A(n5050), .B(n7051), .Y(n6987) );
NAND2X1TS U6905 ( .A(Sgf_operation_ODD1_Q_left[36]), .B(
Sgf_operation_ODD1_Q_left[37]), .Y(n5056) );
NAND2X1TS U6906 ( .A(Sgf_operation_ODD1_Q_left[38]), .B(
Sgf_operation_ODD1_Q_left[39]), .Y(n5060) );
NAND2X2TS U6907 ( .A(n5061), .B(n5063), .Y(n7591) );
NOR2X4TS U6908 ( .A(n7591), .B(n7592), .Y(n7578) );
NAND2X2TS U6909 ( .A(n5064), .B(n5063), .Y(n7590) );
NAND2X2TS U6910 ( .A(n7579), .B(Sgf_operation_ODD1_Q_left[45]), .Y(n5065) );
OAI21X4TS U6911 ( .A0(n5067), .A1(n5066), .B0(n5065), .Y(n5068) );
AOI21X4TS U6912 ( .A0(n7770), .A1(n5069), .B0(n5068), .Y(n7570) );
NAND2X4TS U6913 ( .A(n7561), .B(Sgf_operation_ODD1_Q_left[47]), .Y(n7554) );
NOR2X8TS U6914 ( .A(n7554), .B(n7553), .Y(n7542) );
XNOR2X4TS U6915 ( .A(n5071), .B(n5070), .Y(n5072) );
ADDHX1TS U6916 ( .A(n5074), .B(n5073), .CO(n5080), .S(n4726) );
AOI222X1TS U6917 ( .A0(n6870), .A1(n6884), .B0(n6834), .B1(n7020), .C0(n6867), .C1(n7018), .Y(n5077) );
XOR2X1TS U6918 ( .A(n5078), .B(n6794), .Y(n5079) );
CMPR22X2TS U6919 ( .A(n5080), .B(n5079), .CO(mult_x_24_n983), .S(n5092) );
BUFX3TS U6920 ( .A(n6544), .Y(n6877) );
BUFX3TS U6921 ( .A(n8413), .Y(n6910) );
AND3X6TS U6922 ( .A(n5084), .B(n5083), .C(n5082), .Y(n6982) );
AOI222X1TS U6923 ( .A0(n6877), .A1(n6910), .B0(n6876), .B1(n6780), .C0(n6581), .C1(n8414), .Y(n5085) );
OAI21X1TS U6924 ( .A0(n7039), .A1(n6899), .B0(n5085), .Y(n5086) );
XOR2X1TS U6925 ( .A(n5086), .B(n7490), .Y(n5091) );
BUFX3TS U6926 ( .A(n5087), .Y(n6807) );
AOI222X1TS U6927 ( .A0(n6807), .A1(n7046), .B0(n6786), .B1(n7044), .C0(n6805), .C1(n6584), .Y(n5088) );
OAI21X1TS U6928 ( .A0(n7050), .A1(n6809), .B0(n5088), .Y(n5089) );
XOR2X1TS U6929 ( .A(n5089), .B(n893), .Y(n5090) );
ADDFHX2TS U6930 ( .A(n5092), .B(n5091), .CI(n5090), .CO(mult_x_24_n981), .S(
mult_x_24_n982) );
BUFX4TS U6931 ( .A(n5095), .Y(n5831) );
AOI222X1TS U6932 ( .A0(n5831), .A1(n5843), .B0(n5830), .B1(n5839), .C0(n5997), .C1(n5213), .Y(n5097) );
OAI21X1TS U6933 ( .A0(n5437), .A1(n5827), .B0(n5097), .Y(n5098) );
XOR2X1TS U6934 ( .A(n5098), .B(n6002), .Y(n5101) );
AOI222X1TS U6935 ( .A0(n5976), .A1(n831), .B0(n5698), .B1(n5858), .C0(n5928),
.C1(n5892), .Y(n5099) );
OAI21X1TS U6936 ( .A0(n979), .A1(n5978), .B0(n5099), .Y(n5100) );
XOR2X1TS U6937 ( .A(n5100), .B(n7492), .Y(n5107) );
CMPR22X2TS U6938 ( .A(n5102), .B(n5101), .CO(mult_x_23_n925), .S(n5106) );
AOI222X1TS U6939 ( .A0(n5960), .A1(n5996), .B0(n5661), .B1(n8376), .C0(n5660), .C1(n851), .Y(n5103) );
XOR2X1TS U6940 ( .A(n5104), .B(n5663), .Y(n5105) );
NAND2X2TS U6941 ( .A(n5112), .B(n5120), .Y(n5142) );
CMPR32X2TS U6942 ( .A(n5125), .B(mult_x_24_n693), .C(n5113), .CO(n5123), .S(
n3833) );
NAND2X1TS U6943 ( .A(n6920), .B(n6989), .Y(n5114) );
XOR2X1TS U6944 ( .A(n5115), .B(n7087), .Y(n5124) );
OAI21X1TS U6945 ( .A0(n5118), .A1(n5117), .B0(n5116), .Y(n5119) );
NAND2X1TS U6946 ( .A(n5123), .B(n5122), .Y(n5144) );
OAI21X4TS U6947 ( .A0(n816), .A1(n1026), .B0(n1025), .Y(n5134) );
CMPR32X2TS U6948 ( .A(n5126), .B(n5125), .C(n5124), .CO(n5130), .S(n5122) );
CLKAND2X2TS U6949 ( .A(n6963), .B(Op_MY[26]), .Y(n5127) );
NAND2X1TS U6950 ( .A(n5130), .B(n5129), .Y(n5131) );
NAND2X1TS U6951 ( .A(n5132), .B(n5131), .Y(n5133) );
XNOR2X4TS U6952 ( .A(n5134), .B(n5133), .Y(Sgf_operation_ODD1_right_N53) );
ADDFHX2TS U6953 ( .A(n5137), .B(n5136), .CI(n5135), .CO(n4724), .S(
mult_x_24_n1002) );
ADDFHX2TS U6954 ( .A(n5140), .B(n5139), .CI(n5138), .CO(n4689), .S(
mult_x_23_n893) );
INVX2TS U6955 ( .A(n5143), .Y(n5145) );
NAND2X1TS U6956 ( .A(n5145), .B(n5144), .Y(n5146) );
NAND2X1TS U6957 ( .A(n5149), .B(n5148), .Y(n5150) );
XNOR2X4TS U6958 ( .A(n5151), .B(n5150), .Y(Sgf_operation_ODD1_left_N40) );
INVX2TS U6959 ( .A(n5194), .Y(n5157) );
INVX2TS U6960 ( .A(n5197), .Y(n5156) );
NAND2X1TS U6961 ( .A(n5158), .B(n5196), .Y(n5159) );
XNOR2X4TS U6962 ( .A(n5160), .B(n5159), .Y(Sgf_operation_ODD1_left_N38) );
NOR2X2TS U6963 ( .A(n5161), .B(n5163), .Y(n5170) );
INVX2TS U6964 ( .A(n5170), .Y(n5166) );
INVX2TS U6965 ( .A(n5174), .Y(n5165) );
INVX2TS U6966 ( .A(n5167), .Y(n5173) );
NAND2X1TS U6967 ( .A(n5173), .B(n5171), .Y(n5168) );
NAND2X1TS U6968 ( .A(n5170), .B(n5173), .Y(n5176) );
INVX2TS U6969 ( .A(n5171), .Y(n5172) );
INVX2TS U6970 ( .A(n5177), .Y(n5179) );
NAND2X1TS U6971 ( .A(n5179), .B(n5178), .Y(n5180) );
XNOR2X4TS U6972 ( .A(n5181), .B(n5180), .Y(Sgf_operation_ODD1_left_N44) );
NAND2X1TS U6973 ( .A(n5182), .B(n5185), .Y(n5188) );
INVX2TS U6974 ( .A(n5183), .Y(n5184) );
INVX2TS U6975 ( .A(n5189), .Y(n5191) );
NAND2X1TS U6976 ( .A(n5191), .B(n5190), .Y(n5192) );
XNOR2X4TS U6977 ( .A(n5193), .B(n5192), .Y(Sgf_operation_ODD1_left_N42) );
NAND2X1TS U6978 ( .A(n5194), .B(n5196), .Y(n5199) );
NAND2X1TS U6979 ( .A(n3773), .B(n5200), .Y(n5201) );
XNOR2X4TS U6980 ( .A(n5202), .B(n5201), .Y(Sgf_operation_ODD1_left_N39) );
CMPR22X2TS U6981 ( .A(n5204), .B(n5203), .CO(mult_x_23_n874), .S(n4669) );
AOI21X1TS U6982 ( .A0(n5902), .A1(n828), .B0(n5205), .Y(n5206) );
OAI21X4TS U6983 ( .A0(n5792), .A1(n6061), .B0(n5206), .Y(mult_x_23_n679) );
CMPR22X2TS U6984 ( .A(n5210), .B(n5209), .CO(n4814), .S(mult_x_24_n952) );
AOI222X1TS U6985 ( .A0(n881), .A1(n5843), .B0(n6064), .B1(n5839), .C0(n6063),
.C1(n5213), .Y(n5214) );
INVX2TS U6986 ( .A(n5237), .Y(n5216) );
INVX2TS U6987 ( .A(n5241), .Y(n5215) );
OAI21X1TS U6988 ( .A0(n6092), .A1(n5216), .B0(n5215), .Y(n5219) );
INVX2TS U6989 ( .A(n5217), .Y(n5240) );
NAND2X1TS U6990 ( .A(n5240), .B(n5238), .Y(n5218) );
INVX2TS U6991 ( .A(n5220), .Y(n5224) );
NAND2X1TS U6992 ( .A(n5221), .B(n5224), .Y(n5227) );
INVX2TS U6993 ( .A(n5222), .Y(n5223) );
AOI21X2TS U6994 ( .A0(n5225), .A1(n5224), .B0(n5223), .Y(n5226) );
NAND2X1TS U6995 ( .A(n5229), .B(n5228), .Y(n5230) );
INVX2TS U6996 ( .A(n5232), .Y(n5234) );
NAND2X1TS U6997 ( .A(n5234), .B(n5233), .Y(n5235) );
NAND2X1TS U6998 ( .A(n5237), .B(n5240), .Y(n5243) );
INVX2TS U6999 ( .A(n5238), .Y(n5239) );
AOI21X1TS U7000 ( .A0(n5241), .A1(n5240), .B0(n5239), .Y(n5242) );
INVX2TS U7001 ( .A(n5244), .Y(n5246) );
NAND2X1TS U7002 ( .A(n5246), .B(n5245), .Y(n5247) );
NAND2X1TS U7003 ( .A(n788), .B(n5251), .Y(n5252) );
NAND2X1TS U7004 ( .A(n1012), .B(n5262), .Y(n5263) );
XNOR2X4TS U7005 ( .A(n5264), .B(n5263), .Y(Sgf_operation_ODD1_left_N48) );
NAND2X1TS U7006 ( .A(n5265), .B(n5267), .Y(n5270) );
NAND2X1TS U7007 ( .A(n5273), .B(n5272), .Y(n5274) );
XNOR2X4TS U7008 ( .A(n5275), .B(n5274), .Y(Sgf_operation_ODD1_left_N46) );
INVX2TS U7009 ( .A(n5276), .Y(n5279) );
INVX2TS U7010 ( .A(n5277), .Y(n5278) );
OAI21X2TS U7011 ( .A0(n5280), .A1(n5279), .B0(n5278), .Y(n5284) );
NAND2X1TS U7012 ( .A(n5282), .B(n5281), .Y(n5283) );
XNOR2X1TS U7013 ( .A(n5284), .B(n5283), .Y(Sgf_operation_ODD1_left_N29) );
NAND2X1TS U7014 ( .A(n5287), .B(n5286), .Y(n5288) );
XOR2X1TS U7015 ( .A(n5280), .B(n5288), .Y(Sgf_operation_ODD1_left_N27) );
INVX4TS U7016 ( .A(n5289), .Y(n5315) );
INVX2TS U7017 ( .A(n5299), .Y(n5290) );
NOR2X1TS U7018 ( .A(n5290), .B(n5300), .Y(n5292) );
INVX2TS U7019 ( .A(n5293), .Y(n5295) );
NAND2X1TS U7020 ( .A(n5295), .B(n5294), .Y(n5296) );
AOI21X1TS U7021 ( .A0(n5315), .A1(n5299), .B0(n5298), .Y(n5304) );
INVX2TS U7022 ( .A(n5300), .Y(n5302) );
NAND2X1TS U7023 ( .A(n5302), .B(n5301), .Y(n5303) );
XOR2X1TS U7024 ( .A(n5304), .B(n5303), .Y(Sgf_operation_ODD1_left_N25) );
INVX2TS U7025 ( .A(n5305), .Y(n5313) );
INVX2TS U7026 ( .A(n5312), .Y(n5306) );
AOI21X1TS U7027 ( .A0(n5315), .A1(n5313), .B0(n5306), .Y(n5311) );
INVX2TS U7028 ( .A(n5307), .Y(n5309) );
NAND2X1TS U7029 ( .A(n5309), .B(n5308), .Y(n5310) );
XOR2X1TS U7030 ( .A(n5311), .B(n5310), .Y(Sgf_operation_ODD1_left_N24) );
NAND2X1TS U7031 ( .A(n5313), .B(n5312), .Y(n5314) );
XNOR2X1TS U7032 ( .A(n5315), .B(n5314), .Y(Sgf_operation_ODD1_left_N23) );
OAI21X1TS U7033 ( .A0(n5331), .A1(n5318), .B0(n5317), .Y(n5323) );
INVX2TS U7034 ( .A(n5319), .Y(n5321) );
NAND2X1TS U7035 ( .A(n5321), .B(n5320), .Y(n5322) );
XNOR2X1TS U7036 ( .A(n5323), .B(n5322), .Y(Sgf_operation_ODD1_left_N22) );
NAND2X1TS U7037 ( .A(n1008), .B(n5325), .Y(n5326) );
XNOR2X1TS U7038 ( .A(n5327), .B(n5326), .Y(Sgf_operation_ODD1_left_N21) );
NAND2X1TS U7039 ( .A(n5329), .B(n5328), .Y(n5330) );
INVX2TS U7040 ( .A(n5333), .Y(n5341) );
INVX2TS U7041 ( .A(n5340), .Y(n5334) );
INVX2TS U7042 ( .A(n5335), .Y(n5337) );
NAND2X1TS U7043 ( .A(n5337), .B(n5336), .Y(n5338) );
NAND2X1TS U7044 ( .A(n5341), .B(n5340), .Y(n5342) );
XNOR2X1TS U7045 ( .A(n5989), .B(n5342), .Y(Sgf_operation_ODD1_left_N17) );
INVX2TS U7046 ( .A(n5343), .Y(n5950) );
INVX2TS U7047 ( .A(n5344), .Y(n5346) );
NAND2X1TS U7048 ( .A(n5346), .B(n5345), .Y(n5347) );
XNOR2X1TS U7049 ( .A(n5348), .B(n5347), .Y(Sgf_operation_ODD1_left_N16) );
INVX2TS U7050 ( .A(n5349), .Y(n5357) );
AOI21X1TS U7051 ( .A0(n5357), .A1(n780), .B0(n5350), .Y(n5354) );
NAND2X1TS U7052 ( .A(n5352), .B(n5351), .Y(n5353) );
NAND2X1TS U7053 ( .A(n780), .B(n5355), .Y(n5356) );
XNOR2X1TS U7054 ( .A(n5357), .B(n5356), .Y(Sgf_operation_ODD1_left_N13) );
INVX2TS U7055 ( .A(n5358), .Y(n5955) );
INVX2TS U7056 ( .A(n5359), .Y(n5361) );
NAND2X1TS U7057 ( .A(n5361), .B(n5360), .Y(n5362) );
XNOR2X1TS U7058 ( .A(n5363), .B(n5362), .Y(Sgf_operation_ODD1_left_N12) );
INVX2TS U7059 ( .A(n5364), .Y(n5373) );
AOI21X1TS U7060 ( .A0(n5373), .A1(n5371), .B0(n5365), .Y(n5369) );
NAND2X1TS U7061 ( .A(n5367), .B(n5366), .Y(n5368) );
NAND2X1TS U7062 ( .A(n5371), .B(n5370), .Y(n5372) );
XNOR2X1TS U7063 ( .A(n5373), .B(n5372), .Y(Sgf_operation_ODD1_left_N9) );
INVX2TS U7064 ( .A(n5374), .Y(n5383) );
INVX2TS U7065 ( .A(n5375), .Y(n5377) );
NAND2X1TS U7066 ( .A(n5377), .B(n5376), .Y(n5378) );
XNOR2X1TS U7067 ( .A(n5379), .B(n5378), .Y(Sgf_operation_ODD1_left_N6) );
INVX2TS U7068 ( .A(n5380), .Y(n5382) );
NAND2X1TS U7069 ( .A(n5382), .B(n5381), .Y(n5384) );
INVX2TS U7070 ( .A(n5385), .Y(n5387) );
NAND2X1TS U7071 ( .A(n5387), .B(n5386), .Y(n5388) );
NAND2X1TS U7072 ( .A(n786), .B(n5390), .Y(n5392) );
XNOR2X1TS U7073 ( .A(n5392), .B(n5391), .Y(Sgf_operation_ODD1_left_N3) );
XOR2X1TS U7074 ( .A(n5394), .B(n5393), .Y(Sgf_operation_ODD1_left_N2) );
INVX2TS U7075 ( .A(n5395), .Y(n5397) );
XNOR2X1TS U7076 ( .A(n5397), .B(n5396), .Y(Sgf_operation_ODD1_left_N1) );
INVX2TS U7077 ( .A(n5398), .Y(n5401) );
INVX2TS U7078 ( .A(n5399), .Y(n5400) );
OAI21X4TS U7079 ( .A0(n5454), .A1(n5401), .B0(n5400), .Y(n5534) );
INVX2TS U7080 ( .A(n5402), .Y(n5533) );
NAND2X1TS U7081 ( .A(n5533), .B(n5531), .Y(n5403) );
XOR2X4TS U7082 ( .A(n5534), .B(n5403), .Y(n5912) );
AOI21X1TS U7083 ( .A0(n5936), .A1(n6038), .B0(n5404), .Y(n5405) );
NAND2X1TS U7084 ( .A(n5407), .B(n5406), .Y(n5408) );
XNOR2X4TS U7085 ( .A(n5409), .B(n5408), .Y(n5410) );
INVX8TS U7086 ( .A(n5410), .Y(n5945) );
BUFX3TS U7087 ( .A(Op_MY[49]), .Y(n5918) );
BUFX3TS U7088 ( .A(Op_MY[48]), .Y(n5821) );
AOI222X1TS U7089 ( .A0(n882), .A1(n5918), .B0(n864), .B1(n5821), .C0(n5863),
.C1(n5942), .Y(n5411) );
XOR2X1TS U7090 ( .A(n5412), .B(Op_MX[50]), .Y(n5413) );
CMPR32X2TS U7091 ( .A(n1035), .B(n5834), .C(n5413), .CO(mult_x_23_n652), .S(
mult_x_23_n653) );
AND2X2TS U7092 ( .A(n5899), .B(n5892), .Y(n5414) );
AOI21X1TS U7093 ( .A0(n5902), .A1(n852), .B0(n5414), .Y(n5415) );
OAI21X1TS U7094 ( .A0(n6001), .A1(n5904), .B0(n5415), .Y(n5416) );
CMPR32X2TS U7095 ( .A(n767), .B(n1032), .C(n5416), .CO(mult_x_23_n754), .S(
mult_x_23_n755) );
AOI21X1TS U7096 ( .A0(n5902), .A1(n849), .B0(n5417), .Y(n5418) );
OAI21X1TS U7097 ( .A0(n5762), .A1(n6061), .B0(n5418), .Y(n5422) );
AOI222X1TS U7098 ( .A0(n881), .A1(n837), .B0(n864), .B1(n8385), .C0(n6063),
.C1(n5901), .Y(n5419) );
OAI21X1TS U7099 ( .A0(n5905), .A1(n6067), .B0(n5419), .Y(n5420) );
CMPR32X2TS U7100 ( .A(n7491), .B(n5422), .C(n5421), .CO(mult_x_23_n765), .S(
mult_x_23_n766) );
AOI21X1TS U7101 ( .A0(n5902), .A1(Op_MY[30]), .B0(n5423), .Y(n5424) );
OAI21X1TS U7102 ( .A0(n5931), .A1(n5904), .B0(n5424), .Y(n5428) );
AOI222X1TS U7103 ( .A0(n881), .A1(n831), .B0(n864), .B1(n5858), .C0(n6063),
.C1(n5892), .Y(n5425) );
OAI21X1TS U7104 ( .A0(n979), .A1(n6067), .B0(n5425), .Y(n5426) );
XOR2X1TS U7105 ( .A(n5426), .B(n6021), .Y(n5427) );
AOI21X1TS U7106 ( .A0(n5936), .A1(n855), .B0(n5429), .Y(n5430) );
OAI21X1TS U7107 ( .A0(n6068), .A1(n5904), .B0(n5430), .Y(n5434) );
BUFX3TS U7108 ( .A(Op_MY[37]), .Y(n6005) );
INVX2TS U7109 ( .A(n5493), .Y(n6029) );
AOI222X1TS U7110 ( .A0(n5845), .A1(n5802), .B0(n923), .B1(n837), .C0(n6029),
.C1(n831), .Y(n5431) );
XOR2X1TS U7111 ( .A(n5432), .B(n7493), .Y(n5433) );
CMPR32X2TS U7112 ( .A(n7491), .B(n5434), .C(n5433), .CO(mult_x_23_n787), .S(
mult_x_23_n788) );
AOI21X1TS U7113 ( .A0(n5936), .A1(n824), .B0(n5435), .Y(n5436) );
OAI21X1TS U7114 ( .A0(n5437), .A1(n6061), .B0(n5436), .Y(n5444) );
AOI222X1TS U7115 ( .A0(n5845), .A1(n831), .B0(n923), .B1(n5858), .C0(n5844),
.C1(n5856), .Y(n5438) );
XOR2X2TS U7116 ( .A(n5439), .B(n7493), .Y(n5443) );
AOI222X1TS U7117 ( .A0(n6065), .A1(n5758), .B0(n6064), .B1(n7510), .C0(n6063), .C1(n851), .Y(n5440) );
OAI21X1TS U7118 ( .A0(n5931), .A1(n6067), .B0(n5440), .Y(n5441) );
XOR2X1TS U7119 ( .A(n5441), .B(n6069), .Y(n5442) );
CMPR32X2TS U7120 ( .A(n5444), .B(n5443), .C(n5442), .CO(mult_x_23_n809), .S(
mult_x_23_n810) );
AOI21X1TS U7121 ( .A0(n5863), .A1(n5771), .B0(n5445), .Y(n5446) );
OAI21X1TS U7122 ( .A0(n5773), .A1(n5470), .B0(n5446), .Y(n5447) );
XOR2X1TS U7123 ( .A(n5447), .B(n3866), .Y(mult_x_23_n1262) );
INVX2TS U7124 ( .A(n1031), .Y(n5921) );
BUFX3TS U7125 ( .A(Op_MY[50]), .Y(n5920) );
AOI222X1TS U7126 ( .A0(n882), .A1(n5921), .B0(n865), .B1(n5920), .C0(n5863),
.C1(n5775), .Y(n5448) );
OAI21X1TS U7127 ( .A0(n5925), .A1(n5470), .B0(n5448), .Y(n5449) );
BUFX3TS U7128 ( .A(Op_MY[49]), .Y(n5778) );
AOI222X1TS U7129 ( .A0(n6019), .A1(n5779), .B0(n865), .B1(n5778), .C0(n5863),
.C1(n5939), .Y(n5450) );
XOR2X1TS U7130 ( .A(n5451), .B(n3866), .Y(mult_x_23_n1264) );
OAI21X4TS U7131 ( .A0(n5454), .A1(n5453), .B0(n5452), .Y(n5467) );
INVX2TS U7132 ( .A(n5455), .Y(n5465) );
INVX2TS U7133 ( .A(n5464), .Y(n5456) );
AOI21X4TS U7134 ( .A0(n5467), .A1(n5465), .B0(n5456), .Y(n5461) );
INVX2TS U7135 ( .A(n5457), .Y(n5459) );
NAND2X1TS U7136 ( .A(n5459), .B(n5458), .Y(n5460) );
XNOR2X4TS U7137 ( .A(n5461), .B(n5460), .Y(n5938) );
BUFX3TS U7138 ( .A(Op_MY[48]), .Y(n5871) );
BUFX3TS U7139 ( .A(Op_MY[47]), .Y(n5870) );
AOI222X1TS U7140 ( .A0(n882), .A1(n5871), .B0(n865), .B1(n5870), .C0(n5863),
.C1(n5935), .Y(n5462) );
OAI21X1TS U7141 ( .A0(n5938), .A1(n5470), .B0(n5462), .Y(n5463) );
XOR2X1TS U7142 ( .A(n5463), .B(Op_MX[50]), .Y(mult_x_23_n1266) );
NAND2X1TS U7143 ( .A(n5465), .B(n5464), .Y(n5466) );
XNOR2X4TS U7144 ( .A(n5467), .B(n5466), .Y(n5468) );
BUFX3TS U7145 ( .A(Op_MY[47]), .Y(n5849) );
BUFX3TS U7146 ( .A(Op_MY[46]), .Y(n5866) );
AOI222X1TS U7147 ( .A0(n882), .A1(n5849), .B0(n865), .B1(n5866), .C0(n5863),
.C1(n5906), .Y(n5469) );
OAI21X1TS U7148 ( .A0(n5896), .A1(n5470), .B0(n5469), .Y(n5471) );
XOR2X1TS U7149 ( .A(n5471), .B(n3866), .Y(mult_x_23_n1267) );
BUFX3TS U7150 ( .A(Op_MY[45]), .Y(n6040) );
BUFX3TS U7151 ( .A(Op_MY[44]), .Y(n6039) );
AOI222X1TS U7152 ( .A0(n6065), .A1(n6040), .B0(n864), .B1(n6039), .C0(n5863),
.C1(n6038), .Y(n5472) );
XOR2X1TS U7153 ( .A(n5473), .B(Op_MX[50]), .Y(mult_x_23_n1269) );
BUFX3TS U7154 ( .A(Op_MY[44]), .Y(n6024) );
AOI222X1TS U7155 ( .A0(n6019), .A1(n6024), .B0(n6064), .B1(n839), .C0(n5863),
.C1(n6023), .Y(n5474) );
XOR2X1TS U7156 ( .A(n5475), .B(Op_MX[50]), .Y(mult_x_23_n1270) );
INVX2TS U7157 ( .A(n5476), .Y(n5477) );
AOI21X4TS U7158 ( .A0(n5479), .A1(n5478), .B0(n5477), .Y(n5484) );
INVX2TS U7159 ( .A(n5480), .Y(n5482) );
NAND2X1TS U7160 ( .A(n5482), .B(n5481), .Y(n5483) );
XNOR2X4TS U7161 ( .A(n5484), .B(n5483), .Y(n5968) );
BUFX3TS U7162 ( .A(Op_MY[42]), .Y(n5966) );
BUFX3TS U7163 ( .A(Op_MY[41]), .Y(n5965) );
AOI222X1TS U7164 ( .A0(n882), .A1(n5966), .B0(n6064), .B1(n5965), .C0(n6063),
.C1(n5963), .Y(n5485) );
OAI21X1TS U7165 ( .A0(n5968), .A1(n4965), .B0(n5485), .Y(n5486) );
XOR2X1TS U7166 ( .A(n5486), .B(n6069), .Y(mult_x_23_n1272) );
BUFX3TS U7167 ( .A(Op_MY[37]), .Y(n5802) );
AOI222X1TS U7168 ( .A0(n882), .A1(n5802), .B0(n864), .B1(n837), .C0(n6017),
.C1(n8385), .Y(n5487) );
OAI21X1TS U7169 ( .A0(n5957), .A1(n6067), .B0(n5487), .Y(n5488) );
XOR2X1TS U7170 ( .A(n5488), .B(n6021), .Y(mult_x_23_n1277) );
AOI222X1TS U7171 ( .A0(n882), .A1(n5999), .B0(n864), .B1(n5998), .C0(n6063),
.C1(n5996), .Y(n5489) );
OAI21X1TS U7172 ( .A0(n6001), .A1(n6067), .B0(n5489), .Y(n5490) );
XOR2X1TS U7173 ( .A(n5490), .B(n6069), .Y(mult_x_23_n1280) );
BUFX3TS U7174 ( .A(n5491), .Y(n5886) );
XOR2X1TS U7175 ( .A(n5492), .B(n7493), .Y(mult_x_23_n1289) );
AOI21X1TS U7176 ( .A0(n5884), .A1(n5779), .B0(n5495), .Y(n5496) );
OAI21X1TS U7177 ( .A0(n5773), .A1(n5886), .B0(n5496), .Y(n5497) );
XOR2X1TS U7178 ( .A(n5497), .B(n5868), .Y(mult_x_23_n1291) );
AOI222X1TS U7179 ( .A0(n6033), .A1(n5921), .B0(n923), .B1(n5920), .C0(n5884),
.C1(n5918), .Y(n5498) );
OAI21X1TS U7180 ( .A0(n5925), .A1(n5886), .B0(n5498), .Y(n5499) );
XOR2X1TS U7181 ( .A(n5499), .B(n5868), .Y(mult_x_23_n1292) );
AOI222X1TS U7182 ( .A0(n6033), .A1(n5920), .B0(n5494), .B1(n5778), .C0(n5884), .C1(n5871), .Y(n5500) );
XOR2X1TS U7183 ( .A(n5501), .B(n5868), .Y(mult_x_23_n1293) );
AOI222X1TS U7184 ( .A0(n6033), .A1(n5778), .B0(n923), .B1(n5821), .C0(n5884),
.C1(n5849), .Y(n5502) );
OAI21X1TS U7185 ( .A0(n5945), .A1(n5886), .B0(n5502), .Y(n5503) );
BUFX3TS U7186 ( .A(Op_MY[46]), .Y(n6080) );
AOI222X1TS U7187 ( .A0(n6033), .A1(n5821), .B0(n6031), .B1(n5870), .C0(n5884), .C1(n6080), .Y(n5504) );
OAI21X1TS U7188 ( .A0(n5938), .A1(n5886), .B0(n5504), .Y(n5505) );
XOR2X1TS U7189 ( .A(n5505), .B(n5868), .Y(mult_x_23_n1295) );
AOI222X1TS U7190 ( .A0(n5845), .A1(n5942), .B0(n923), .B1(n5866), .C0(n5884),
.C1(n6040), .Y(n5506) );
XOR2X1TS U7191 ( .A(n5507), .B(n5868), .Y(mult_x_23_n1296) );
BUFX3TS U7192 ( .A(Op_MY[45]), .Y(n6078) );
AOI222X1TS U7193 ( .A0(n5840), .A1(n6078), .B0(n6031), .B1(n6039), .C0(n5884), .C1(n840), .Y(n5508) );
AOI222X1TS U7194 ( .A0(n6033), .A1(n6039), .B0(n5494), .B1(n839), .C0(n5884),
.C1(n5966), .Y(n5510) );
OAI21X1TS U7195 ( .A0(n6026), .A1(n5491), .B0(n5510), .Y(n5511) );
XOR2X1TS U7196 ( .A(n5511), .B(n5868), .Y(mult_x_23_n1299) );
BUFX3TS U7197 ( .A(Op_MY[42]), .Y(n6046) );
AOI222X1TS U7198 ( .A0(n5840), .A1(n839), .B0(n923), .B1(n6046), .C0(n5844),
.C1(n5790), .Y(n5512) );
OAI21X1TS U7199 ( .A0(n6048), .A1(n5491), .B0(n5512), .Y(n5513) );
XOR2X1TS U7200 ( .A(n5513), .B(n5868), .Y(mult_x_23_n1300) );
BUFX3TS U7201 ( .A(Op_MY[40]), .Y(n6018) );
AOI222X1TS U7202 ( .A0(n6033), .A1(n6046), .B0(n6031), .B1(n5965), .C0(n5844), .C1(n6018), .Y(n5514) );
XOR2X1TS U7203 ( .A(n5515), .B(n5847), .Y(mult_x_23_n1301) );
AOI222X1TS U7204 ( .A0(n5840), .A1(n5965), .B0(n5494), .B1(n6032), .C0(n6029), .C1(n5796), .Y(n5516) );
XOR2X1TS U7205 ( .A(n5517), .B(n5847), .Y(mult_x_23_n1302) );
BUFX3TS U7206 ( .A(Op_MY[39]), .Y(n6030) );
AOI222X1TS U7207 ( .A0(n5845), .A1(n6030), .B0(n6031), .B1(n5982), .C0(n6029), .C1(n6005), .Y(n5518) );
XOR2X1TS U7208 ( .A(n5519), .B(n7493), .Y(mult_x_23_n1304) );
AOI222X1TS U7209 ( .A0(n5845), .A1(n5858), .B0(n923), .B1(n5998), .C0(n5844),
.C1(n852), .Y(n5520) );
OAI21X1TS U7210 ( .A0(n6001), .A1(n6035), .B0(n5520), .Y(n5521) );
XOR2X1TS U7211 ( .A(n5521), .B(n5847), .Y(mult_x_23_n1309) );
AOI222X1TS U7212 ( .A0(n5845), .A1(n5998), .B0(n923), .B1(n5758), .C0(n5844),
.C1(n7510), .Y(n5522) );
OAI21X1TS U7213 ( .A0(n5762), .A1(n6035), .B0(n5522), .Y(n5523) );
XOR2X1TS U7214 ( .A(n5523), .B(n5847), .Y(mult_x_23_n1310) );
AOI222X1TS U7215 ( .A0(n5840), .A1(n5996), .B0(n6031), .B1(n8376), .C0(n5844), .C1(n8375), .Y(n5524) );
XOR2X1TS U7216 ( .A(n5525), .B(n5847), .Y(mult_x_23_n1311) );
AOI21X1TS U7217 ( .A0(n5919), .A1(n5779), .B0(n5526), .Y(n5527) );
OAI21X1TS U7218 ( .A0(n5773), .A1(n5924), .B0(n5527), .Y(n5528) );
XOR2X1TS U7219 ( .A(n5528), .B(n5926), .Y(mult_x_23_n1320) );
AOI222X1TS U7220 ( .A0(n5922), .A1(n5779), .B0(n6011), .B1(n5778), .C0(n5919), .C1(n5871), .Y(n5529) );
XOR2X1TS U7221 ( .A(n5530), .B(n5926), .Y(mult_x_23_n1322) );
INVX2TS U7222 ( .A(n5531), .Y(n5532) );
AOI21X4TS U7223 ( .A0(n5534), .A1(n5533), .B0(n5532), .Y(n5539) );
NAND2X1TS U7224 ( .A(n5537), .B(n5536), .Y(n5538) );
XNOR2X4TS U7225 ( .A(n5539), .B(n5538), .Y(n6084) );
AOI222X1TS U7226 ( .A0(n6012), .A1(n6080), .B0(n5564), .B1(n6078), .C0(n5919), .C1(n6024), .Y(n5540) );
OAI21X1TS U7227 ( .A0(n6084), .A1(n4671), .B0(n5540), .Y(n5541) );
XOR2X1TS U7228 ( .A(n5541), .B(n5926), .Y(mult_x_23_n1326) );
AOI222X1TS U7229 ( .A0(n5922), .A1(n6024), .B0(n5564), .B1(n840), .C0(n5919),
.C1(n5966), .Y(n5542) );
XOR2X1TS U7230 ( .A(n5543), .B(n5926), .Y(mult_x_23_n1328) );
AOI222X1TS U7231 ( .A0(n6012), .A1(n840), .B0(n5564), .B1(n6046), .C0(n6010),
.C1(n5790), .Y(n5544) );
OAI21X1TS U7232 ( .A0(n6048), .A1(n4671), .B0(n5544), .Y(n5545) );
AOI222X1TS U7233 ( .A0(n6012), .A1(n5966), .B0(n5564), .B1(n5965), .C0(n5560), .C1(n6018), .Y(n5546) );
XOR2X1TS U7234 ( .A(n5547), .B(n5567), .Y(mult_x_23_n1330) );
AOI222X1TS U7235 ( .A0(n6012), .A1(n5790), .B0(n5564), .B1(n6032), .C0(n6010), .C1(n5796), .Y(n5548) );
OAI21X1TS U7236 ( .A0(n5792), .A1(n4671), .B0(n5548), .Y(n5549) );
XOR2X1TS U7237 ( .A(n5549), .B(n5567), .Y(mult_x_23_n1331) );
XOR2X1TS U7238 ( .A(n5551), .B(n737), .Y(mult_x_23_n1333) );
BUFX3TS U7239 ( .A(n5922), .Y(n5565) );
BUFX3TS U7240 ( .A(Op_MY[38]), .Y(n6028) );
AOI222X1TS U7241 ( .A0(n5565), .A1(n6028), .B0(n5561), .B1(n814), .C0(n6010),
.C1(n838), .Y(n5552) );
XOR2X1TS U7242 ( .A(n5553), .B(n737), .Y(mult_x_23_n1334) );
AOI222X1TS U7243 ( .A0(n5565), .A1(n5802), .B0(n5561), .B1(n837), .C0(n6010),
.C1(n832), .Y(n5554) );
AOI222X1TS U7244 ( .A0(n5565), .A1(n838), .B0(n5561), .B1(n8385), .C0(n5560),
.C1(n5999), .Y(n5556) );
XOR2X1TS U7245 ( .A(n5557), .B(n737), .Y(mult_x_23_n1336) );
AOI222X1TS U7246 ( .A0(n5565), .A1(n832), .B0(n5561), .B1(n5858), .C0(n6010),
.C1(n5856), .Y(n5558) );
XOR2X1TS U7247 ( .A(n5559), .B(n737), .Y(mult_x_23_n1337) );
AOI222X1TS U7248 ( .A0(n5565), .A1(n5999), .B0(n5561), .B1(n5998), .C0(n5560), .C1(n5996), .Y(n5562) );
OAI21X1TS U7249 ( .A0(n6001), .A1(n6014), .B0(n5562), .Y(n5563) );
XOR2X1TS U7250 ( .A(n5563), .B(n5567), .Y(mult_x_23_n1338) );
AOI222X1TS U7251 ( .A0(n5565), .A1(n5856), .B0(n5564), .B1(n5758), .C0(n6010), .C1(n849), .Y(n5566) );
OAI21X1TS U7252 ( .A0(n5762), .A1(n6014), .B0(n5566), .Y(n5568) );
XOR2X1TS U7253 ( .A(n5568), .B(n5567), .Y(mult_x_23_n1339) );
BUFX3TS U7254 ( .A(n5569), .Y(n5827) );
OAI21X1TS U7255 ( .A0(n5879), .A1(n5827), .B0(n5594), .Y(n5570) );
XOR2X1TS U7256 ( .A(n5570), .B(n7498), .Y(mult_x_23_n1347) );
INVX4TS U7257 ( .A(n5594), .Y(n5824) );
AOI21X1TS U7258 ( .A0(n5824), .A1(n5883), .B0(n867), .Y(n5571) );
AOI21X1TS U7259 ( .A0(n5824), .A1(n5779), .B0(n5573), .Y(n5574) );
XOR2X1TS U7260 ( .A(n5575), .B(n5828), .Y(mult_x_23_n1349) );
AOI222X1TS U7261 ( .A0(n5825), .A1(n5779), .B0(n868), .B1(n5778), .C0(n5824),
.C1(n5871), .Y(n5576) );
XOR2X1TS U7262 ( .A(n5577), .B(n5828), .Y(mult_x_23_n1351) );
AOI222X1TS U7263 ( .A0(n5825), .A1(n5918), .B0(n868), .B1(n5821), .C0(n5824),
.C1(n5849), .Y(n5578) );
OAI21X1TS U7264 ( .A0(n5945), .A1(n5827), .B0(n5578), .Y(n5579) );
XOR2X1TS U7265 ( .A(n5579), .B(n5828), .Y(mult_x_23_n1352) );
AOI222X1TS U7266 ( .A0(n5825), .A1(n5871), .B0(n868), .B1(n5870), .C0(n5824),
.C1(n6080), .Y(n5580) );
XOR2X1TS U7267 ( .A(n5581), .B(n5828), .Y(mult_x_23_n1353) );
AOI222X1TS U7268 ( .A0(n5825), .A1(n5849), .B0(n868), .B1(n5866), .C0(n5824),
.C1(n6040), .Y(n5582) );
OAI21X1TS U7269 ( .A0(n5896), .A1(n5827), .B0(n5582), .Y(n5583) );
XOR2X1TS U7270 ( .A(n5583), .B(n5828), .Y(mult_x_23_n1354) );
AOI222X1TS U7271 ( .A0(n5831), .A1(n6080), .B0(n5830), .B1(n6078), .C0(n5824), .C1(n6024), .Y(n5584) );
OAI21X1TS U7272 ( .A0(n6084), .A1(n5827), .B0(n5584), .Y(n5585) );
XOR2X1TS U7273 ( .A(n5585), .B(n5828), .Y(mult_x_23_n1355) );
AOI222X1TS U7274 ( .A0(n5831), .A1(n6040), .B0(n867), .B1(n6039), .C0(n5824),
.C1(n839), .Y(n5586) );
OAI21X1TS U7275 ( .A0(n5912), .A1(n5569), .B0(n5586), .Y(n5587) );
XOR2X1TS U7276 ( .A(n5587), .B(n5828), .Y(mult_x_23_n1356) );
AOI222X1TS U7277 ( .A0(n5825), .A1(n6024), .B0(n5830), .B1(n839), .C0(n5824),
.C1(n5966), .Y(n5588) );
OAI21X1TS U7278 ( .A0(n6026), .A1(n5569), .B0(n5588), .Y(n5589) );
XOR2X1TS U7279 ( .A(n5589), .B(n5828), .Y(mult_x_23_n1357) );
AOI222X1TS U7280 ( .A0(n5831), .A1(n840), .B0(n5830), .B1(n6046), .C0(n5997),
.C1(n5790), .Y(n5590) );
OAI21X1TS U7281 ( .A0(n6048), .A1(n5569), .B0(n5590), .Y(n5591) );
XOR2X1TS U7282 ( .A(n5591), .B(n5828), .Y(mult_x_23_n1358) );
AOI222X1TS U7283 ( .A0(n5831), .A1(n5966), .B0(n5830), .B1(n5965), .C0(n5997), .C1(n6018), .Y(n5592) );
INVX2TS U7284 ( .A(n5594), .Y(n6004) );
AOI222X1TS U7285 ( .A0(n5831), .A1(n5790), .B0(n5830), .B1(n6032), .C0(n6004), .C1(n5796), .Y(n5595) );
OAI21X1TS U7286 ( .A0(n5792), .A1(n5569), .B0(n5595), .Y(n5596) );
XOR2X1TS U7287 ( .A(n5596), .B(n6002), .Y(mult_x_23_n1360) );
INVX2TS U7288 ( .A(n5597), .Y(n5598) );
INVX2TS U7289 ( .A(n5601), .Y(n5603) );
XNOR2X4TS U7290 ( .A(n5605), .B(n5604), .Y(n6036) );
AOI222X1TS U7291 ( .A0(n5831), .A1(n6018), .B0(n868), .B1(n6030), .C0(n6004),
.C1(n6028), .Y(n5606) );
XOR2X1TS U7292 ( .A(n5607), .B(n7498), .Y(mult_x_23_n1361) );
AOI222X1TS U7293 ( .A0(n5825), .A1(n5796), .B0(n867), .B1(n5982), .C0(n6004),
.C1(n5802), .Y(n5608) );
OAI21X1TS U7294 ( .A0(n5876), .A1(n6007), .B0(n5608), .Y(n5609) );
XOR2X1TS U7295 ( .A(n5609), .B(n7498), .Y(mult_x_23_n1362) );
AOI222X1TS U7296 ( .A0(n5095), .A1(n814), .B0(n868), .B1(n837), .C0(n6004),
.C1(n832), .Y(n5610) );
XOR2X1TS U7297 ( .A(n5611), .B(n7498), .Y(mult_x_23_n1364) );
AOI222X1TS U7298 ( .A0(n5095), .A1(n838), .B0(n868), .B1(n831), .C0(n5997),
.C1(n5999), .Y(n5612) );
OAI21X1TS U7299 ( .A0(n5905), .A1(n6007), .B0(n5612), .Y(n5613) );
XOR2X1TS U7300 ( .A(n5613), .B(n7498), .Y(mult_x_23_n1365) );
AOI222X1TS U7301 ( .A0(n5095), .A1(n5856), .B0(n5830), .B1(n5758), .C0(n5997), .C1(n7510), .Y(n5614) );
OAI21X1TS U7302 ( .A0(n5762), .A1(n6007), .B0(n5614), .Y(n5615) );
XOR2X1TS U7303 ( .A(n5615), .B(n6002), .Y(mult_x_23_n1368) );
AOI222X1TS U7304 ( .A0(n5831), .A1(n5996), .B0(n5830), .B1(n8376), .C0(n5997), .C1(n8375), .Y(n5616) );
XOR2X1TS U7305 ( .A(n5617), .B(n6002), .Y(mult_x_23_n1369) );
AOI222X1TS U7306 ( .A0(n5831), .A1(n7510), .B0(n5830), .B1(n830), .C0(n5997),
.C1(n5843), .Y(n5618) );
OAI21X1TS U7307 ( .A0(n6068), .A1(n6007), .B0(n5618), .Y(n5619) );
XOR2X1TS U7308 ( .A(n5619), .B(n6002), .Y(mult_x_23_n1370) );
BUFX3TS U7309 ( .A(n5620), .Y(n5878) );
INVX4TS U7310 ( .A(n5877), .Y(n5640) );
AOI21X1TS U7311 ( .A0(n5640), .A1(n5883), .B0(n5959), .Y(n5621) );
OAI21X1TS U7312 ( .A0(n5887), .A1(n5878), .B0(n5621), .Y(n5622) );
XOR2X1TS U7313 ( .A(n5622), .B(Op_MX[38]), .Y(mult_x_23_n1377) );
AO21X1TS U7314 ( .A0(n5959), .A1(n5921), .B0(n5653), .Y(n5623) );
AOI21X1TS U7315 ( .A0(n5640), .A1(n5771), .B0(n5623), .Y(n5624) );
OAI21X1TS U7316 ( .A0(n5773), .A1(n5878), .B0(n5624), .Y(n5625) );
XOR2X1TS U7317 ( .A(n5625), .B(n5644), .Y(mult_x_23_n1378) );
AOI222X1TS U7318 ( .A0(n5653), .A1(n5921), .B0(n5959), .B1(n5920), .C0(n5640), .C1(n5775), .Y(n5626) );
AOI222X1TS U7319 ( .A0(n5653), .A1(n5920), .B0(n5959), .B1(n5778), .C0(n5640), .C1(n5939), .Y(n5628) );
OAI21X1TS U7320 ( .A0(n5781), .A1(n5878), .B0(n5628), .Y(n5629) );
XOR2X1TS U7321 ( .A(n5629), .B(n5644), .Y(mult_x_23_n1380) );
AOI222X1TS U7322 ( .A0(n5653), .A1(n5778), .B0(n5959), .B1(n5821), .C0(n5640), .C1(n5942), .Y(n5630) );
OAI21X1TS U7323 ( .A0(n5945), .A1(n5878), .B0(n5630), .Y(n5631) );
XOR2X1TS U7324 ( .A(n5631), .B(n5644), .Y(mult_x_23_n1381) );
AOI222X1TS U7325 ( .A0(n5653), .A1(n5821), .B0(n5959), .B1(n5870), .C0(n5640), .C1(n5935), .Y(n5632) );
OAI21X1TS U7326 ( .A0(n5938), .A1(n5878), .B0(n5632), .Y(n5633) );
XOR2X1TS U7327 ( .A(n5633), .B(n5644), .Y(mult_x_23_n1382) );
AOI222X1TS U7328 ( .A0(n5653), .A1(n5870), .B0(n5959), .B1(n5866), .C0(n5640), .C1(n5906), .Y(n5634) );
OAI21X1TS U7329 ( .A0(n5896), .A1(n5878), .B0(n5634), .Y(n5635) );
XOR2X1TS U7330 ( .A(n5635), .B(n5644), .Y(mult_x_23_n1383) );
AOI222X1TS U7331 ( .A0(n5960), .A1(n5866), .B0(n5661), .B1(n6078), .C0(n5640), .C1(n829), .Y(n5636) );
OAI21X1TS U7332 ( .A0(n6084), .A1(n5620), .B0(n5636), .Y(n5637) );
XOR2X1TS U7333 ( .A(n5637), .B(n5644), .Y(mult_x_23_n1384) );
AOI222X1TS U7334 ( .A0(n5960), .A1(n6078), .B0(n5959), .B1(n6039), .C0(n5640), .C1(n6038), .Y(n5638) );
XOR2X1TS U7335 ( .A(n5639), .B(n5644), .Y(mult_x_23_n1385) );
AOI222X1TS U7336 ( .A0(n5653), .A1(n6039), .B0(n5661), .B1(n840), .C0(n5640),
.C1(n6023), .Y(n5641) );
XOR2X1TS U7337 ( .A(n5642), .B(n5644), .Y(mult_x_23_n1386) );
AOI222X1TS U7338 ( .A0(n5960), .A1(n839), .B0(n5661), .B1(n6046), .C0(n5660),
.C1(n6045), .Y(n5643) );
AOI222X1TS U7339 ( .A0(n5960), .A1(n6046), .B0(n5661), .B1(n5965), .C0(n5660), .C1(n5963), .Y(n5646) );
XOR2X1TS U7340 ( .A(n5647), .B(n5663), .Y(mult_x_23_n1388) );
INVX2TS U7341 ( .A(n5877), .Y(n5980) );
AOI222X1TS U7342 ( .A0(n5960), .A1(n5965), .B0(n5661), .B1(n6032), .C0(n5980), .C1(n828), .Y(n5648) );
OAI21X1TS U7343 ( .A0(n5792), .A1(n5620), .B0(n5648), .Y(n5649) );
XOR2X1TS U7344 ( .A(n5649), .B(n5663), .Y(mult_x_23_n1389) );
AOI222X1TS U7345 ( .A0(n5653), .A1(n6030), .B0(n5981), .B1(n5982), .C0(n5980), .C1(n5802), .Y(n5651) );
XOR2X1TS U7346 ( .A(n5652), .B(n7500), .Y(mult_x_23_n1391) );
AOI222X1TS U7347 ( .A0(n5983), .A1(n850), .B0(n5981), .B1(n832), .C0(n5980),
.C1(n5901), .Y(n5654) );
XOR2X1TS U7348 ( .A(n5655), .B(n7500), .Y(mult_x_23_n1394) );
XOR2X1TS U7349 ( .A(n5657), .B(n7500), .Y(mult_x_23_n1395) );
OAI21X1TS U7350 ( .A0(n6001), .A1(n5985), .B0(n5658), .Y(n5659) );
XOR2X1TS U7351 ( .A(n5659), .B(n5663), .Y(mult_x_23_n1396) );
AOI222X1TS U7352 ( .A0(n5983), .A1(n5998), .B0(n5661), .B1(n5758), .C0(n5660), .C1(n849), .Y(n5662) );
XOR2X1TS U7353 ( .A(n5664), .B(n5663), .Y(mult_x_23_n1397) );
BUFX3TS U7354 ( .A(n5665), .Y(n5684) );
XOR2X1TS U7355 ( .A(n5666), .B(n7492), .Y(mult_x_23_n1405) );
INVX4TS U7356 ( .A(n5667), .Y(n5690) );
AOI21X1TS U7357 ( .A0(n5690), .A1(n5883), .B0(n5975), .Y(n5669) );
CLKINVX1TS U7358 ( .A(n793), .Y(n5670) );
XOR2X1TS U7359 ( .A(n5671), .B(n5670), .Y(mult_x_23_n1406) );
AOI21X1TS U7360 ( .A0(n5690), .A1(n5771), .B0(n5672), .Y(n5673) );
OAI21X1TS U7361 ( .A0(n5773), .A1(n5684), .B0(n5673), .Y(n5674) );
XOR2X1TS U7362 ( .A(n5674), .B(n5694), .Y(mult_x_23_n1407) );
AOI222X1TS U7363 ( .A0(n5701), .A1(n5921), .B0(n5698), .B1(n5920), .C0(n5690), .C1(n5775), .Y(n5675) );
OAI21X1TS U7364 ( .A0(n5925), .A1(n5684), .B0(n5675), .Y(n5676) );
XOR2X1TS U7365 ( .A(n5676), .B(n5694), .Y(mult_x_23_n1408) );
AOI222X1TS U7366 ( .A0(n5701), .A1(n5779), .B0(n5698), .B1(n5778), .C0(n5690), .C1(n5939), .Y(n5677) );
OAI21X1TS U7367 ( .A0(n5781), .A1(n5684), .B0(n5677), .Y(n5678) );
XOR2X1TS U7368 ( .A(n5678), .B(n5694), .Y(mult_x_23_n1409) );
AOI222X1TS U7369 ( .A0(n5701), .A1(n5918), .B0(n5698), .B1(n5821), .C0(n5690), .C1(n5870), .Y(n5679) );
OAI21X1TS U7370 ( .A0(n5945), .A1(n5684), .B0(n5679), .Y(n5680) );
XOR2X1TS U7371 ( .A(n5680), .B(n5694), .Y(mult_x_23_n1410) );
AOI222X1TS U7372 ( .A0(n5701), .A1(n5871), .B0(n5698), .B1(n5870), .C0(n5690), .C1(n5935), .Y(n5681) );
XOR2X1TS U7373 ( .A(n5682), .B(n5694), .Y(mult_x_23_n1411) );
AOI222X1TS U7374 ( .A0(n5701), .A1(n5849), .B0(n5975), .B1(n5866), .C0(n5690), .C1(n5906), .Y(n5683) );
XOR2X1TS U7375 ( .A(n5685), .B(n5694), .Y(mult_x_23_n1412) );
AOI222X1TS U7376 ( .A0(n5929), .A1(n6080), .B0(n5975), .B1(n6078), .C0(n5690), .C1(n829), .Y(n5686) );
XOR2X1TS U7377 ( .A(n5687), .B(n5694), .Y(mult_x_23_n1413) );
AOI222X1TS U7378 ( .A0(n5929), .A1(n6040), .B0(n5975), .B1(n6039), .C0(n5690), .C1(n6038), .Y(n5688) );
XOR2X1TS U7379 ( .A(n5689), .B(n5694), .Y(mult_x_23_n1414) );
AOI222X1TS U7380 ( .A0(n5701), .A1(n6024), .B0(n5668), .B1(n840), .C0(n5690),
.C1(n6023), .Y(n5691) );
XOR2X1TS U7381 ( .A(n5692), .B(n5694), .Y(mult_x_23_n1415) );
AOI222X1TS U7382 ( .A0(n5929), .A1(n839), .B0(n5698), .B1(n6046), .C0(n5928),
.C1(n6045), .Y(n5693) );
XOR2X1TS U7383 ( .A(n5695), .B(n5694), .Y(mult_x_23_n1416) );
AOI222X1TS U7384 ( .A0(n5929), .A1(n5790), .B0(n5975), .B1(n6032), .C0(n5974), .C1(n828), .Y(n5696) );
OAI21X1TS U7385 ( .A0(n5792), .A1(n5665), .B0(n5696), .Y(n5697) );
XOR2X1TS U7386 ( .A(n5697), .B(n895), .Y(mult_x_23_n1418) );
AOI222X1TS U7387 ( .A0(n5929), .A1(n6018), .B0(n5668), .B1(n6030), .C0(n5974), .C1(n6016), .Y(n5699) );
XOR2X1TS U7388 ( .A(n5700), .B(n7492), .Y(mult_x_23_n1419) );
AOI222X1TS U7389 ( .A0(n5701), .A1(n5796), .B0(n5975), .B1(n5982), .C0(n5974), .C1(n6005), .Y(n5702) );
XOR2X1TS U7390 ( .A(n5703), .B(n7492), .Y(mult_x_23_n1420) );
AOI222X1TS U7391 ( .A0(n5976), .A1(n814), .B0(n5698), .B1(n838), .C0(n5974),
.C1(n8385), .Y(n5704) );
XOR2X1TS U7392 ( .A(n5705), .B(n7492), .Y(mult_x_23_n1422) );
AOI222X1TS U7393 ( .A0(n5976), .A1(n838), .B0(n5668), .B1(n831), .C0(n5928),
.C1(n5901), .Y(n5706) );
OAI21X1TS U7394 ( .A0(n5905), .A1(n5978), .B0(n5706), .Y(n5707) );
XOR2X1TS U7395 ( .A(n5707), .B(n7492), .Y(mult_x_23_n1423) );
AOI222X1TS U7396 ( .A0(n5976), .A1(n5856), .B0(n5975), .B1(n5758), .C0(n5928), .C1(n849), .Y(n5708) );
OAI21X1TS U7397 ( .A0(n5762), .A1(n5978), .B0(n5708), .Y(n5709) );
XOR2X1TS U7398 ( .A(n5709), .B(n895), .Y(mult_x_23_n1426) );
AOI21X1TS U7399 ( .A0(n5732), .A1(n5883), .B0(n5745), .Y(n5713) );
OAI21X1TS U7400 ( .A0(n5887), .A1(n5761), .B0(n5713), .Y(n5714) );
AOI21X1TS U7401 ( .A0(n5732), .A1(n5771), .B0(n5715), .Y(n5716) );
OAI21X1TS U7402 ( .A0(n5773), .A1(n5761), .B0(n5716), .Y(n5717) );
XOR2X1TS U7403 ( .A(n5717), .B(n5736), .Y(mult_x_23_n1436) );
AOI222X1TS U7404 ( .A0(n5859), .A1(n5921), .B0(n5745), .B1(n5920), .C0(n5732), .C1(n5918), .Y(n5718) );
OAI21X1TS U7405 ( .A0(n5925), .A1(n5761), .B0(n5718), .Y(n5719) );
XOR2X1TS U7406 ( .A(n5719), .B(n5736), .Y(mult_x_23_n1437) );
XOR2X1TS U7407 ( .A(n5721), .B(n5736), .Y(mult_x_23_n1438) );
AOI222X1TS U7408 ( .A0(n5859), .A1(n5918), .B0(n5745), .B1(n5821), .C0(n5732), .C1(n5849), .Y(n5722) );
OAI21X1TS U7409 ( .A0(n5945), .A1(n5761), .B0(n5722), .Y(n5723) );
OAI21X1TS U7410 ( .A0(n5938), .A1(n5761), .B0(n5724), .Y(n5725) );
XOR2X1TS U7411 ( .A(n5725), .B(n5736), .Y(mult_x_23_n1440) );
AOI222X1TS U7412 ( .A0(n5859), .A1(n5849), .B0(n5745), .B1(n5866), .C0(n5732), .C1(n6040), .Y(n5726) );
OAI21X1TS U7413 ( .A0(n5896), .A1(n5761), .B0(n5726), .Y(n5727) );
XOR2X1TS U7414 ( .A(n5727), .B(n5736), .Y(mult_x_23_n1441) );
AOI222X1TS U7415 ( .A0(n5742), .A1(n6080), .B0(n5759), .B1(n6078), .C0(n5732), .C1(n6024), .Y(n5728) );
XOR2X1TS U7416 ( .A(n5729), .B(n5736), .Y(mult_x_23_n1442) );
AOI222X1TS U7417 ( .A0(n5742), .A1(n6040), .B0(n5745), .B1(n6039), .C0(n5732), .C1(Op_MY[43]), .Y(n5730) );
XOR2X1TS U7418 ( .A(n5731), .B(n5736), .Y(mult_x_23_n1443) );
XOR2X1TS U7419 ( .A(n5734), .B(n5736), .Y(mult_x_23_n1444) );
AOI222X1TS U7420 ( .A0(n5742), .A1(Op_MY[43]), .B0(n5759), .B1(n6046), .C0(
n5857), .C1(n5790), .Y(n5735) );
AOI222X1TS U7421 ( .A0(n5742), .A1(n5966), .B0(n5759), .B1(n5965), .C0(n5857), .C1(n6018), .Y(n5738) );
XOR2X1TS U7422 ( .A(n5739), .B(n5763), .Y(mult_x_23_n1446) );
AOI222X1TS U7423 ( .A0(n5742), .A1(n5790), .B0(n5759), .B1(n6032), .C0(n5751), .C1(n5796), .Y(n5740) );
OAI21X1TS U7424 ( .A0(n5792), .A1(n5861), .B0(n5740), .Y(n5741) );
XOR2X1TS U7425 ( .A(n5741), .B(n5763), .Y(mult_x_23_n1447) );
AOI222X1TS U7426 ( .A0(n5742), .A1(n6018), .B0(n5745), .B1(n6030), .C0(n5857), .C1(n6028), .Y(n5743) );
XOR2X1TS U7427 ( .A(n5744), .B(Op_MX[32]), .Y(mult_x_23_n1448) );
XOR2X1TS U7428 ( .A(n5747), .B(n8404), .Y(mult_x_23_n1449) );
BUFX3TS U7429 ( .A(n5748), .Y(n5859) );
AOI222X1TS U7430 ( .A0(n5859), .A1(n6028), .B0(n5712), .B1(n6005), .C0(n5857), .C1(n838), .Y(n5749) );
XOR2X1TS U7431 ( .A(n5750), .B(Op_MX[32]), .Y(mult_x_23_n1450) );
XOR2X1TS U7432 ( .A(n5753), .B(n8404), .Y(mult_x_23_n1451) );
AOI222X1TS U7433 ( .A0(n5859), .A1(n837), .B0(n5712), .B1(n8385), .C0(n5857),
.C1(n5999), .Y(n5754) );
XOR2X1TS U7434 ( .A(n5755), .B(n8404), .Y(mult_x_23_n1452) );
AOI222X1TS U7435 ( .A0(n5859), .A1(n5999), .B0(n5712), .B1(n5998), .C0(n5857), .C1(n852), .Y(n5756) );
XOR2X1TS U7436 ( .A(n5757), .B(n5763), .Y(mult_x_23_n1454) );
AOI222X1TS U7437 ( .A0(n5859), .A1(n5856), .B0(n5759), .B1(n5758), .C0(n5857), .C1(n848), .Y(n5760) );
XOR2X1TS U7438 ( .A(n5764), .B(n5763), .Y(mult_x_23_n1455) );
BUFX3TS U7439 ( .A(n5766), .Y(n6083) );
AOI21X1TS U7440 ( .A0(n6077), .A1(n5769), .B0(n873), .Y(n5767) );
XOR2X1TS U7441 ( .A(n5768), .B(n7491), .Y(mult_x_23_n1464) );
AOI21X1TS U7442 ( .A0(n6077), .A1(n5771), .B0(n5770), .Y(n5772) );
OAI21X1TS U7443 ( .A0(n5773), .A1(n6083), .B0(n5772), .Y(n5774) );
AOI222X1TS U7444 ( .A0(n870), .A1(n5921), .B0(n3669), .B1(n5920), .C0(n6077),
.C1(n5775), .Y(n5776) );
OAI21X1TS U7445 ( .A0(n5925), .A1(n6083), .B0(n5776), .Y(n5777) );
XOR2X1TS U7446 ( .A(n5777), .B(n5819), .Y(mult_x_23_n1466) );
AOI222X1TS U7447 ( .A0(n871), .A1(n5779), .B0(n3669), .B1(n5778), .C0(n6077),
.C1(n5939), .Y(n5780) );
XOR2X1TS U7448 ( .A(n5782), .B(n5819), .Y(mult_x_23_n1467) );
AOI222X1TS U7449 ( .A0(n870), .A1(n5871), .B0(n3669), .B1(n5870), .C0(n6077),
.C1(n5935), .Y(n5783) );
OAI21X1TS U7450 ( .A0(n5938), .A1(n6083), .B0(n5783), .Y(n5784) );
XOR2X1TS U7451 ( .A(n5784), .B(n5819), .Y(mult_x_23_n1469) );
AOI222X1TS U7452 ( .A0(n870), .A1(n5849), .B0(n873), .B1(n5866), .C0(n6077),
.C1(n5906), .Y(n5785) );
OAI21X1TS U7453 ( .A0(n5896), .A1(n6083), .B0(n5785), .Y(n5786) );
XOR2X1TS U7454 ( .A(n5786), .B(n7491), .Y(mult_x_23_n1470) );
AOI222X1TS U7455 ( .A0(n6081), .A1(Op_MY[43]), .B0(n6079), .B1(n6046), .C0(
n5964), .C1(n6045), .Y(n5787) );
XOR2X1TS U7456 ( .A(n5788), .B(n7491), .Y(mult_x_23_n1474) );
INVX2TS U7457 ( .A(n5789), .Y(n5801) );
AOI222X1TS U7458 ( .A0(n6081), .A1(n5790), .B0(n6079), .B1(n6032), .C0(n5801), .C1(n828), .Y(n5791) );
OAI21X1TS U7459 ( .A0(n5792), .A1(n6042), .B0(n5791), .Y(n5793) );
XOR2X1TS U7460 ( .A(n5793), .B(n5804), .Y(mult_x_23_n1476) );
AOI222X1TS U7461 ( .A0(n6081), .A1(n6018), .B0(n873), .B1(n6030), .C0(n5801),
.C1(n6016), .Y(n5794) );
XOR2X1TS U7462 ( .A(n5795), .B(n5804), .Y(mult_x_23_n1477) );
AOI222X1TS U7463 ( .A0(n871), .A1(n5796), .B0(n3669), .B1(n5982), .C0(n5801),
.C1(n814), .Y(n5797) );
OAI21X1TS U7464 ( .A0(n5876), .A1(n5807), .B0(n5797), .Y(n5798) );
XOR2X1TS U7465 ( .A(n5798), .B(n5804), .Y(mult_x_23_n1478) );
AOI222X1TS U7466 ( .A0(n870), .A1(n6028), .B0(n873), .B1(n814), .C0(n5801),
.C1(n850), .Y(n5799) );
XOR2X1TS U7467 ( .A(n5800), .B(n5804), .Y(mult_x_23_n1479) );
XOR2X1TS U7468 ( .A(n5805), .B(n5804), .Y(mult_x_23_n1480) );
AOI222X1TS U7469 ( .A0(n870), .A1(n838), .B0(n3669), .B1(n831), .C0(n5964),
.C1(n5901), .Y(n5806) );
XOR2X1TS U7470 ( .A(n5808), .B(n5819), .Y(mult_x_23_n1481) );
INVX2TS U7471 ( .A(n5809), .Y(n5811) );
NAND2X1TS U7472 ( .A(n5811), .B(n5810), .Y(n5812) );
NAND2X1TS U7473 ( .A(n5815), .B(n5814), .Y(n5816) );
XNOR2X1TS U7474 ( .A(n5817), .B(n5816), .Y(Sgf_operation_ODD1_left_N8) );
AOI222X1TS U7475 ( .A0(n871), .A1(n5918), .B0(n873), .B1(n5821), .C0(n6077),
.C1(n5942), .Y(n5818) );
OAI21X1TS U7476 ( .A0(n5945), .A1(n6083), .B0(n5818), .Y(n5820) );
XOR2X1TS U7477 ( .A(n5820), .B(n5819), .Y(mult_x_23_n1468) );
AOI222X1TS U7478 ( .A0(n5922), .A1(n5918), .B0(n6011), .B1(n5821), .C0(n5919), .C1(n5849), .Y(n5822) );
XOR2X1TS U7479 ( .A(n5823), .B(n5926), .Y(mult_x_23_n1323) );
AOI222X1TS U7480 ( .A0(n5825), .A1(n5921), .B0(n867), .B1(n5920), .C0(n5824),
.C1(n5918), .Y(n5826) );
AOI222X1TS U7481 ( .A0(n5831), .A1(n8375), .B0(n5830), .B1(n6055), .C0(n5997), .C1(n6054), .Y(n5832) );
XOR2X1TS U7482 ( .A(n5833), .B(n6002), .Y(mult_x_23_n1371) );
OAI21X1TS U7483 ( .A0(n5879), .A1(n5924), .B0(n5835), .Y(n5836) );
XOR2X1TS U7484 ( .A(n5836), .B(n737), .Y(n5837) );
AOI222X1TS U7485 ( .A0(n5840), .A1(n8375), .B0(n6031), .B1(n6055), .C0(n5844), .C1(n5839), .Y(n5841) );
OAI21X1TS U7486 ( .A0(n1001), .A1(n5491), .B0(n5841), .Y(n5842) );
AOI222X1TS U7487 ( .A0(n5845), .A1(n8376), .B0(n923), .B1(n830), .C0(n5844),
.C1(n5843), .Y(n5846) );
OAI21X1TS U7488 ( .A0(n6068), .A1(n6035), .B0(n5846), .Y(n5848) );
XOR2X1TS U7489 ( .A(n5848), .B(n5847), .Y(mult_x_23_n1312) );
AOI222X1TS U7490 ( .A0(n5922), .A1(n5849), .B0(n6011), .B1(n5866), .C0(n5919), .C1(n6040), .Y(n5850) );
OAI21X1TS U7491 ( .A0(n5896), .A1(n5924), .B0(n5850), .Y(n5851) );
XOR2X1TS U7492 ( .A(n5851), .B(n5926), .Y(mult_x_23_n1325) );
AOI222X1TS U7493 ( .A0(n5976), .A1(n5999), .B0(n5668), .B1(n5998), .C0(n5928), .C1(n852), .Y(n5854) );
OAI21X1TS U7494 ( .A0(n6001), .A1(n5978), .B0(n5854), .Y(n5855) );
XOR2X1TS U7495 ( .A(n5855), .B(n895), .Y(mult_x_23_n1425) );
AOI222X1TS U7496 ( .A0(n5859), .A1(n832), .B0(n5745), .B1(n5858), .C0(n5857),
.C1(n5856), .Y(n5860) );
XOR2X1TS U7497 ( .A(n5862), .B(n8404), .Y(mult_x_23_n1453) );
AOI222X1TS U7498 ( .A0(n6019), .A1(n6080), .B0(n6064), .B1(n6078), .C0(n5863), .C1(n829), .Y(n5864) );
AOI222X1TS U7499 ( .A0(n6033), .A1(n5866), .B0(n923), .B1(n6078), .C0(n5884),
.C1(n6024), .Y(n5867) );
OAI21X1TS U7500 ( .A0(n6084), .A1(n5491), .B0(n5867), .Y(n5869) );
XOR2X1TS U7501 ( .A(n5869), .B(n5868), .Y(mult_x_23_n1297) );
AOI222X1TS U7502 ( .A0(n5922), .A1(n5871), .B0(n6011), .B1(n5870), .C0(n5919), .C1(n6080), .Y(n5872) );
OAI21X1TS U7503 ( .A0(n5938), .A1(n5924), .B0(n5872), .Y(n5873) );
XOR2X1TS U7504 ( .A(n5873), .B(n5926), .Y(mult_x_23_n1324) );
AOI21X1TS U7505 ( .A0(n5902), .A1(n814), .B0(n5874), .Y(n5875) );
INVX2TS U7506 ( .A(n6051), .Y(n5882) );
OAI21X1TS U7507 ( .A0(n5879), .A1(n5878), .B0(n5877), .Y(n5880) );
XOR2X1TS U7508 ( .A(n5880), .B(n7500), .Y(n5881) );
CMPR32X2TS U7509 ( .A(n5882), .B(mult_x_23_n714), .C(n5881), .CO(
mult_x_23_n702), .S(mult_x_23_n703) );
AOI21X1TS U7510 ( .A0(n5884), .A1(n5883), .B0(n5494), .Y(n5885) );
OAI21X1TS U7511 ( .A0(n5887), .A1(n5886), .B0(n5885), .Y(n5888) );
XOR2X1TS U7512 ( .A(n5888), .B(n7493), .Y(mult_x_23_n1290) );
AOI21X1TS U7513 ( .A0(n5936), .A1(n5963), .B0(n5889), .Y(n5890) );
OAI21X1TS U7514 ( .A0(n5968), .A1(n6061), .B0(n5890), .Y(mult_x_23_n1247) );
AND2X2TS U7515 ( .A(n5899), .B(n5901), .Y(n5891) );
AOI21X1TS U7516 ( .A0(n5902), .A1(n5892), .B0(n5891), .Y(n5893) );
OAI21X2TS U7517 ( .A0(n979), .A1(n5904), .B0(n5893), .Y(mult_x_23_n733) );
AOI21X1TS U7518 ( .A0(n5936), .A1(n5906), .B0(n5894), .Y(n5895) );
OAI21X2TS U7519 ( .A0(n5896), .A1(n6052), .B0(n5895), .Y(mult_x_23_n643) );
AOI21X1TS U7520 ( .A0(n5902), .A1(n6016), .B0(n5897), .Y(n5898) );
OAI21X1TS U7521 ( .A0(n6036), .A1(n6052), .B0(n5898), .Y(mult_x_23_n1248) );
AOI21X1TS U7522 ( .A0(n5902), .A1(n5901), .B0(n5900), .Y(n5903) );
OAI21X1TS U7523 ( .A0(n5905), .A1(n5904), .B0(n5903), .Y(mult_x_23_n1251) );
AOI21X1TS U7524 ( .A0(n5936), .A1(n829), .B0(n5907), .Y(n5908) );
OAI21X1TS U7525 ( .A0(n6084), .A1(n6052), .B0(n5908), .Y(mult_x_23_n1244) );
INVX2TS U7526 ( .A(mult_x_23_n679), .Y(mult_x_23_n687) );
AOI222X1TS U7527 ( .A0(n6012), .A1(n6040), .B0(n6011), .B1(n6039), .C0(n5919), .C1(n839), .Y(n5911) );
OAI21X1TS U7528 ( .A0(n5912), .A1(n4671), .B0(n5911), .Y(n5913) );
XOR2X1TS U7529 ( .A(n5913), .B(n5926), .Y(mult_x_23_n1327) );
AOI222X1TS U7530 ( .A0(n5929), .A1(n5966), .B0(n5975), .B1(n5965), .C0(n5928), .C1(n5963), .Y(n5914) );
OAI21X1TS U7531 ( .A0(n5968), .A1(n5665), .B0(n5914), .Y(n5915) );
XOR2X1TS U7532 ( .A(n5915), .B(n895), .Y(mult_x_23_n1417) );
AOI222X1TS U7533 ( .A0(n5929), .A1(n8375), .B0(n5698), .B1(n6055), .C0(n5928), .C1(n6054), .Y(n5916) );
AOI222X1TS U7534 ( .A0(n5922), .A1(n5921), .B0(n6011), .B1(n5920), .C0(n5919), .C1(n5918), .Y(n5923) );
XOR2X1TS U7535 ( .A(n5927), .B(n5926), .Y(mult_x_23_n1321) );
INVX2TS U7536 ( .A(mult_x_23_n733), .Y(mult_x_23_n744) );
INVX2TS U7537 ( .A(mult_x_23_n643), .Y(mult_x_23_n648) );
AOI222X1TS U7538 ( .A0(n5929), .A1(n5996), .B0(n5668), .B1(n8376), .C0(n5928), .C1(Op_MY[30]), .Y(n5930) );
XOR2X1TS U7539 ( .A(n5932), .B(n895), .Y(mult_x_23_n1427) );
ADDHX1TS U7540 ( .A(n7500), .B(n5933), .CO(n4760), .S(mult_x_23_n955) );
AOI21X1TS U7541 ( .A0(n5936), .A1(n5935), .B0(n5934), .Y(n5937) );
AOI21X1TS U7542 ( .A0(n5943), .A1(n5942), .B0(n5941), .Y(n5944) );
OAI21X1TS U7543 ( .A0(n5945), .A1(n6052), .B0(n5944), .Y(mult_x_23_n1242) );
INVX2TS U7544 ( .A(n5946), .Y(n5948) );
NAND2X1TS U7545 ( .A(n5948), .B(n5947), .Y(n5949) );
INVX2TS U7546 ( .A(n5951), .Y(n5953) );
NAND2X1TS U7547 ( .A(n5953), .B(n5952), .Y(n5954) );
XOR2X1TS U7548 ( .A(n5958), .B(n7500), .Y(mult_x_23_n1393) );
AOI222X1TS U7549 ( .A0(n5960), .A1(n6032), .B0(n5959), .B1(n6030), .C0(n5980), .C1(n6016), .Y(n5961) );
XOR2X1TS U7550 ( .A(n5962), .B(n7500), .Y(mult_x_23_n1390) );
AOI222X1TS U7551 ( .A0(n6081), .A1(n5966), .B0(n6079), .B1(n5965), .C0(n5964), .C1(n5963), .Y(n5967) );
XOR2X1TS U7552 ( .A(n5969), .B(Op_MX[29]), .Y(mult_x_23_n1475) );
AOI222X1TS U7553 ( .A0(n6033), .A1(n5982), .B0(n6031), .B1(n814), .C0(n6029),
.C1(n837), .Y(n5970) );
OAI21X1TS U7554 ( .A0(n6008), .A1(n6035), .B0(n5970), .Y(n5971) );
XOR2X1TS U7555 ( .A(n5971), .B(n7493), .Y(mult_x_23_n1305) );
XOR2X1TS U7556 ( .A(n5973), .B(n6021), .Y(mult_x_23_n1276) );
AOI222X1TS U7557 ( .A0(n5976), .A1(n6028), .B0(n5698), .B1(n7507), .C0(n5974), .C1(n850), .Y(n5977) );
XOR2X1TS U7558 ( .A(n5979), .B(n7492), .Y(mult_x_23_n1421) );
AOI222X1TS U7559 ( .A0(n5983), .A1(n5982), .B0(n5981), .B1(n814), .C0(n5980),
.C1(n850), .Y(n5984) );
OAI21X1TS U7560 ( .A0(n6008), .A1(n5985), .B0(n5984), .Y(n5986) );
XOR2X1TS U7561 ( .A(n5986), .B(n7500), .Y(mult_x_23_n1392) );
AOI222X1TS U7562 ( .A0(n5095), .A1(n5999), .B0(n867), .B1(n5998), .C0(n5997),
.C1(n5996), .Y(n6000) );
OAI21X1TS U7563 ( .A0(n6001), .A1(n6007), .B0(n6000), .Y(n6003) );
XOR2X1TS U7564 ( .A(n6003), .B(n6002), .Y(mult_x_23_n1367) );
AOI222X1TS U7565 ( .A0(n5095), .A1(n6028), .B0(n868), .B1(n5802), .C0(n6004),
.C1(n838), .Y(n6006) );
XOR2X1TS U7566 ( .A(n6009), .B(n7498), .Y(mult_x_23_n1363) );
AOI222X1TS U7567 ( .A0(n6012), .A1(n6018), .B0(n6011), .B1(n6030), .C0(n6010), .C1(n6028), .Y(n6013) );
XOR2X1TS U7568 ( .A(n6015), .B(n737), .Y(mult_x_23_n1332) );
AOI222X1TS U7569 ( .A0(n881), .A1(n6018), .B0(n865), .B1(n6030), .C0(n6017),
.C1(n6016), .Y(n6020) );
OAI21X1TS U7570 ( .A0(n6036), .A1(n6067), .B0(n6020), .Y(n6022) );
XOR2X1TS U7571 ( .A(n6022), .B(n6021), .Y(mult_x_23_n1274) );
AOI222X1TS U7572 ( .A0(n871), .A1(n6024), .B0(n6079), .B1(n840), .C0(n6077),
.C1(n6023), .Y(n6025) );
OAI21X1TS U7573 ( .A0(n6026), .A1(n6042), .B0(n6025), .Y(n6027) );
XOR2X1TS U7574 ( .A(n6027), .B(Op_MX[29]), .Y(mult_x_23_n1473) );
AOI222X1TS U7575 ( .A0(n6033), .A1(n6032), .B0(n6031), .B1(n6030), .C0(n6029), .C1(n6028), .Y(n6034) );
XOR2X1TS U7576 ( .A(n6037), .B(n7493), .Y(mult_x_23_n1303) );
AOI222X1TS U7577 ( .A0(n6081), .A1(n6040), .B0(n3669), .B1(n6039), .C0(n6077), .C1(n6038), .Y(n6041) );
OAI21X1TS U7578 ( .A0(n6043), .A1(n6042), .B0(n6041), .Y(n6044) );
XOR2X1TS U7579 ( .A(n6044), .B(Op_MX[29]), .Y(mult_x_23_n1472) );
AOI222X1TS U7580 ( .A0(n6065), .A1(n839), .B0(n6064), .B1(n6046), .C0(n6063),
.C1(n6045), .Y(n6047) );
ADDFHX1TS U7581 ( .A(n1020), .B(n6051), .CI(n6050), .CO(mult_x_23_n694), .S(
mult_x_23_n695) );
NOR2X1TS U7582 ( .A(n6053), .B(n6052), .Y(n6073) );
OAI21X1TS U7583 ( .A0(n1001), .A1(n4965), .B0(n6056), .Y(n6057) );
XOR2X2TS U7584 ( .A(n6057), .B(n6069), .Y(n6072) );
CMPR22X2TS U7585 ( .A(n6059), .B(n6058), .CO(n6071), .S(mult_x_23_n843) );
OAI21X1TS U7586 ( .A0(n6062), .A1(n6061), .B0(n796), .Y(n6076) );
AOI222X1TS U7587 ( .A0(n6065), .A1(n7510), .B0(n6064), .B1(n851), .C0(n6063),
.C1(n5843), .Y(n6066) );
OAI21X1TS U7588 ( .A0(n6068), .A1(n6067), .B0(n6066), .Y(n6070) );
XOR2X1TS U7589 ( .A(n6070), .B(n6069), .Y(n6075) );
ADDFHX1TS U7590 ( .A(n6076), .B(n6075), .CI(n6074), .CO(mult_x_23_n820), .S(
mult_x_23_n821) );
AOI222X1TS U7591 ( .A0(n6081), .A1(n6080), .B0(n6079), .B1(n6078), .C0(n6077), .C1(n829), .Y(n6082) );
OAI21X1TS U7592 ( .A0(n6084), .A1(n6083), .B0(n6082), .Y(n6085) );
XOR2X1TS U7593 ( .A(n6085), .B(Op_MX[29]), .Y(mult_x_23_n1471) );
INVX2TS U7594 ( .A(n6088), .Y(n6090) );
NAND2X1TS U7595 ( .A(n6090), .B(n6089), .Y(n6091) );
INVX2TS U7596 ( .A(n6094), .Y(n6097) );
INVX2TS U7597 ( .A(n6095), .Y(n6096) );
INVX2TS U7598 ( .A(n6098), .Y(n6100) );
NAND2X1TS U7599 ( .A(n6100), .B(n6099), .Y(n6101) );
NAND2X1TS U7600 ( .A(n7107), .B(n6103), .Y(n6104) );
XNOR2X1TS U7601 ( .A(n7108), .B(n6104), .Y(Sgf_operation_ODD1_right_N25) );
INVX2TS U7602 ( .A(n6117), .Y(n6107) );
NAND2X1TS U7603 ( .A(n6107), .B(n6119), .Y(n6111) );
INVX2TS U7604 ( .A(n6116), .Y(n6109) );
AOI21X1TS U7605 ( .A0(n6109), .A1(n6119), .B0(n6108), .Y(n6110) );
NAND2X1TS U7606 ( .A(n6113), .B(n6112), .Y(n6114) );
XNOR2X1TS U7607 ( .A(n6115), .B(n6114), .Y(Sgf_operation_ODD1_right_N24) );
NAND2X1TS U7608 ( .A(n6119), .B(n6118), .Y(n6120) );
XNOR2X1TS U7609 ( .A(n6121), .B(n6120), .Y(Sgf_operation_ODD1_right_N23) );
NAND2X1TS U7610 ( .A(n6124), .B(n6123), .Y(n6125) );
XNOR2X1TS U7611 ( .A(n6126), .B(n6125), .Y(Sgf_operation_ODD1_right_N22) );
NAND2X1TS U7612 ( .A(n6128), .B(n6127), .Y(n6129) );
INVX2TS U7613 ( .A(n6131), .Y(n6139) );
NAND2X1TS U7614 ( .A(n972), .B(n6133), .Y(n6134) );
NAND2X1TS U7615 ( .A(n6137), .B(n6136), .Y(n6138) );
XNOR2X1TS U7616 ( .A(n6139), .B(n6138), .Y(Sgf_operation_ODD1_right_N19) );
INVX2TS U7617 ( .A(n6140), .Y(n6951) );
INVX2TS U7618 ( .A(n6141), .Y(n6143) );
NAND2X1TS U7619 ( .A(n6143), .B(n6142), .Y(n6144) );
XNOR2X1TS U7620 ( .A(n6145), .B(n6144), .Y(Sgf_operation_ODD1_right_N18) );
NAND2X1TS U7621 ( .A(n6150), .B(n6149), .Y(n6151) );
INVX2TS U7622 ( .A(n6153), .Y(n6161) );
INVX2TS U7623 ( .A(n6160), .Y(n6154) );
AOI21X1TS U7624 ( .A0(n6163), .A1(n6161), .B0(n6154), .Y(n6159) );
INVX2TS U7625 ( .A(n6155), .Y(n6157) );
NAND2X1TS U7626 ( .A(n6157), .B(n6156), .Y(n6158) );
NAND2X1TS U7627 ( .A(n6161), .B(n6160), .Y(n6162) );
XNOR2X1TS U7628 ( .A(n6163), .B(n6162), .Y(Sgf_operation_ODD1_right_N14) );
INVX2TS U7629 ( .A(n6164), .Y(n6957) );
INVX2TS U7630 ( .A(n6165), .Y(n6167) );
NAND2X1TS U7631 ( .A(n6167), .B(n6166), .Y(n6168) );
XNOR2X1TS U7632 ( .A(n6169), .B(n6168), .Y(Sgf_operation_ODD1_right_N13) );
INVX2TS U7633 ( .A(n6170), .Y(n6178) );
AOI21X1TS U7634 ( .A0(n6178), .A1(n779), .B0(n6171), .Y(n6175) );
NAND2X1TS U7635 ( .A(n6173), .B(n6172), .Y(n6174) );
NAND2X1TS U7636 ( .A(n779), .B(n6176), .Y(n6177) );
XNOR2X1TS U7637 ( .A(n6178), .B(n6177), .Y(Sgf_operation_ODD1_right_N10) );
NAND2X1TS U7638 ( .A(n6180), .B(n6179), .Y(n6182) );
XNOR2X1TS U7639 ( .A(n6182), .B(n6181), .Y(Sgf_operation_ODD1_right_N9) );
INVX2TS U7640 ( .A(n6183), .Y(n6192) );
AOI21X1TS U7641 ( .A0(n6192), .A1(n6190), .B0(n6184), .Y(n6188) );
NAND2X1TS U7642 ( .A(n6186), .B(n6185), .Y(n6187) );
NAND2X1TS U7643 ( .A(n6190), .B(n6189), .Y(n6191) );
XNOR2X1TS U7644 ( .A(n6192), .B(n6191), .Y(Sgf_operation_ODD1_right_N7) );
INVX2TS U7645 ( .A(n6193), .Y(n6202) );
INVX2TS U7646 ( .A(n6194), .Y(n6196) );
NAND2X1TS U7647 ( .A(n6196), .B(n6195), .Y(n6197) );
XNOR2X1TS U7648 ( .A(n6198), .B(n6197), .Y(Sgf_operation_ODD1_right_N6) );
INVX2TS U7649 ( .A(n6199), .Y(n6201) );
NAND2X1TS U7650 ( .A(n6201), .B(n6200), .Y(n6203) );
INVX2TS U7651 ( .A(n6204), .Y(n6206) );
NAND2X1TS U7652 ( .A(n6206), .B(n6205), .Y(n6207) );
NAND2X1TS U7653 ( .A(n1014), .B(n6209), .Y(n6211) );
XNOR2X1TS U7654 ( .A(n6211), .B(n6210), .Y(Sgf_operation_ODD1_right_N3) );
INVX2TS U7655 ( .A(n6213), .Y(n6215) );
XNOR2X1TS U7656 ( .A(n6215), .B(n6214), .Y(Sgf_operation_ODD1_right_N1) );
CMPR32X2TS U7657 ( .A(n1018), .B(n6217), .C(n6216), .CO(mult_x_24_n707), .S(
mult_x_24_n708) );
AOI21X1TS U7658 ( .A0(n6491), .A1(n925), .B0(n6218), .Y(n6219) );
OAI21X1TS U7659 ( .A0(n7006), .A1(n7013), .B0(n6219), .Y(n6221) );
XOR2X1TS U7660 ( .A(n6221), .B(n6220), .Y(n6222) );
AND2X2TS U7661 ( .A(n7087), .B(n875), .Y(n6225) );
CMPR32X2TS U7662 ( .A(n1009), .B(n6225), .C(n6224), .CO(mult_x_24_n747), .S(
mult_x_24_n748) );
INVX2TS U7663 ( .A(n6225), .Y(n7067) );
NAND2X1TS U7664 ( .A(n6982), .B(n6989), .Y(n6226) );
XOR2X1TS U7665 ( .A(n6227), .B(Op_MY[14]), .Y(n6228) );
CMPR32X2TS U7666 ( .A(n6229), .B(n7067), .C(n6228), .CO(mult_x_24_n755), .S(
mult_x_24_n756) );
INVX2TS U7667 ( .A(n6936), .Y(n7090) );
INVX2TS U7668 ( .A(n1205), .Y(n6233) );
NAND2X1TS U7669 ( .A(n6233), .B(n6232), .Y(n6234) );
XNOR2X4TS U7670 ( .A(n6235), .B(n6234), .Y(n6236) );
BUFX3TS U7671 ( .A(n6238), .Y(n7083) );
AOI222X1TS U7672 ( .A0(n7083), .A1(n841), .B0(n7081), .B1(n8413), .C0(n7080),
.C1(n6780), .Y(n6240) );
OAI21X2TS U7673 ( .A0(n6912), .A1(n7085), .B0(n6240), .Y(n6241) );
XOR2X1TS U7674 ( .A(n6241), .B(n6882), .Y(n6242) );
CMPR32X2TS U7675 ( .A(n7090), .B(mult_x_24_n840), .C(n6242), .CO(
mult_x_24_n828), .S(mult_x_24_n829) );
OAI21X4TS U7676 ( .A0(n740), .A1(n6247), .B0(n6246), .Y(n6252) );
INVX2TS U7677 ( .A(n6248), .Y(n6250) );
XNOR2X4TS U7678 ( .A(n6252), .B(n6251), .Y(n6253) );
AOI222X1TS U7679 ( .A0(n7060), .A1(n6963), .B0(n6921), .B1(n925), .C0(n6920),
.C1(n6959), .Y(n6254) );
OAI21X1TS U7680 ( .A0(n6967), .A1(n6925), .B0(n6254), .Y(n6255) );
XOR2X1TS U7681 ( .A(n6255), .B(n7087), .Y(mult_x_24_n1400) );
INVX2TS U7682 ( .A(n6256), .Y(n6273) );
INVX2TS U7683 ( .A(n6272), .Y(n6257) );
INVX2TS U7684 ( .A(n6260), .Y(n6262) );
XNOR2X4TS U7685 ( .A(n6264), .B(n6263), .Y(n6265) );
BUFX3TS U7686 ( .A(Op_MX[25]), .Y(n6961) );
AOI222X1TS U7687 ( .A0(n6923), .A1(n6961), .B0(n6921), .B1(Op_MX[24]), .C0(
n6920), .C1(n834), .Y(n6266) );
XOR2X1TS U7688 ( .A(n6267), .B(n7064), .Y(mult_x_24_n1401) );
INVX2TS U7689 ( .A(n6268), .Y(n6271) );
INVX2TS U7690 ( .A(n6269), .Y(n6270) );
OAI21X4TS U7691 ( .A0(n740), .A1(n6271), .B0(n6270), .Y(n6275) );
XNOR2X4TS U7692 ( .A(n6275), .B(n6274), .Y(n6276) );
BUFX3TS U7693 ( .A(Op_MX[24]), .Y(n6767) );
AOI222X1TS U7694 ( .A0(n6923), .A1(n6767), .B0(n6921), .B1(n834), .C0(n6920),
.C1(n6551), .Y(n6277) );
OAI21X1TS U7695 ( .A0(n6703), .A1(n6925), .B0(n6277), .Y(n6278) );
XOR2X1TS U7696 ( .A(n6278), .B(n7078), .Y(mult_x_24_n1402) );
INVX2TS U7697 ( .A(n6391), .Y(n6279) );
INVX2TS U7698 ( .A(n6390), .Y(n6282) );
OAI21X1TS U7699 ( .A0(n6282), .A1(n6395), .B0(n6396), .Y(n6283) );
INVX2TS U7700 ( .A(n6287), .Y(n6289) );
XNOR2X4TS U7701 ( .A(n6291), .B(n6290), .Y(n6292) );
BUFX3TS U7702 ( .A(n834), .Y(n6701) );
CLKBUFX2TS U7703 ( .A(Op_MX[22]), .Y(n6551) );
AOI222X1TS U7704 ( .A0(n6923), .A1(n6701), .B0(n6921), .B1(n6551), .C0(n7080), .C1(n6952), .Y(n6293) );
OAI21X1TS U7705 ( .A0(n6778), .A1(n6925), .B0(n6293), .Y(n6294) );
XOR2X1TS U7706 ( .A(n6294), .B(n7064), .Y(mult_x_24_n1403) );
INVX2TS U7707 ( .A(n6295), .Y(n6296) );
INVX2TS U7708 ( .A(n6300), .Y(n6302) );
XNOR2X4TS U7709 ( .A(n6304), .B(n6303), .Y(n6305) );
BUFX3TS U7710 ( .A(Op_MX[21]), .Y(n6814) );
XOR2X1TS U7711 ( .A(n6307), .B(n7064), .Y(mult_x_24_n1405) );
BUFX3TS U7712 ( .A(n878), .Y(n6846) );
AOI222X1TS U7713 ( .A0(n6923), .A1(n6846), .B0(n6921), .B1(n6749), .C0(n6920), .C1(n927), .Y(n6308) );
OAI21X1TS U7714 ( .A0(n6832), .A1(n6925), .B0(n6308), .Y(n6309) );
XOR2X1TS U7715 ( .A(n6309), .B(n7064), .Y(mult_x_24_n1406) );
INVX2TS U7716 ( .A(n6326), .Y(n6311) );
AOI21X1TS U7717 ( .A0(n6323), .A1(n6327), .B0(n6311), .Y(n6312) );
INVX2TS U7718 ( .A(n6314), .Y(n6316) );
XNOR2X4TS U7719 ( .A(n6318), .B(n6317), .Y(n6319) );
CLKBUFX2TS U7720 ( .A(Op_MX[18]), .Y(n8403) );
AOI222X1TS U7721 ( .A0(n7060), .A1(n6830), .B0(n6921), .B1(n927), .C0(n6920),
.C1(n6559), .Y(n6320) );
OAI21X1TS U7722 ( .A0(n6933), .A1(n7062), .B0(n6320), .Y(n6321) );
XOR2X1TS U7723 ( .A(n6321), .B(n7064), .Y(mult_x_24_n1407) );
INVX2TS U7724 ( .A(n6322), .Y(n6325) );
INVX2TS U7725 ( .A(n6323), .Y(n6324) );
OAI21X4TS U7726 ( .A0(n820), .A1(n6325), .B0(n6324), .Y(n6329) );
XNOR2X4TS U7727 ( .A(n6329), .B(n6328), .Y(n6330) );
BUFX3TS U7728 ( .A(n6829), .Y(n6929) );
AOI222X1TS U7729 ( .A0(n6923), .A1(n6929), .B0(n7058), .B1(n6559), .C0(n7057), .C1(n6562), .Y(n6331) );
OAI21X1TS U7730 ( .A0(n6793), .A1(n7062), .B0(n6331), .Y(n6332) );
XOR2X1TS U7731 ( .A(n6332), .B(n6882), .Y(mult_x_24_n1408) );
INVX2TS U7732 ( .A(n6333), .Y(n6335) );
NAND2X1TS U7733 ( .A(n6335), .B(n6334), .Y(n6336) );
XNOR2X4TS U7734 ( .A(n6337), .B(n6336), .Y(n6338) );
BUFX3TS U7735 ( .A(n6559), .Y(n6790) );
AOI222X1TS U7736 ( .A0(n7060), .A1(n6790), .B0(n7058), .B1(n6562), .C0(n7057), .C1(n6945), .Y(n6339) );
OAI21X1TS U7737 ( .A0(n6918), .A1(n7062), .B0(n6339), .Y(n6340) );
XOR2X1TS U7738 ( .A(n6340), .B(n7064), .Y(mult_x_24_n1409) );
INVX2TS U7739 ( .A(n6425), .Y(n6343) );
XNOR2X4TS U7740 ( .A(n6345), .B(n6344), .Y(n6346) );
BUFX3TS U7741 ( .A(n8412), .Y(n7071) );
XOR2X1TS U7742 ( .A(n6348), .B(n6882), .Y(mult_x_24_n1412) );
INVX2TS U7743 ( .A(n6363), .Y(n6350) );
OAI21X4TS U7744 ( .A0(n6461), .A1(n6352), .B0(n6351), .Y(n6357) );
INVX2TS U7745 ( .A(n6353), .Y(n6355) );
XNOR2X4TS U7746 ( .A(n6357), .B(n6356), .Y(n6358) );
BUFX3TS U7747 ( .A(n6569), .Y(n7069) );
AOI222X1TS U7748 ( .A0(n7060), .A1(n7069), .B0(n6921), .B1(Op_MX[12]), .C0(
n7080), .C1(n7008), .Y(n6359) );
OAI21X1TS U7749 ( .A0(n7014), .A1(n6925), .B0(n6359), .Y(n6360) );
XOR2X1TS U7750 ( .A(n6360), .B(n7087), .Y(mult_x_24_n1413) );
OAI21X2TS U7751 ( .A0(n6461), .A1(n6362), .B0(n6361), .Y(n6366) );
NAND2X1TS U7752 ( .A(n6364), .B(n6363), .Y(n6365) );
BUFX3TS U7753 ( .A(n875), .Y(n7009) );
CLKBUFX2TS U7754 ( .A(Op_MX[11]), .Y(n6574) );
AOI222X1TS U7755 ( .A0(n6923), .A1(n7009), .B0(n7081), .B1(n6574), .C0(n7080), .C1(n910), .Y(n6368) );
OAI21X1TS U7756 ( .A0(n6775), .A1(n7085), .B0(n6368), .Y(n6369) );
XOR2X1TS U7757 ( .A(n6369), .B(n7087), .Y(mult_x_24_n1414) );
AOI222X1TS U7758 ( .A0(n7083), .A1(n7033), .B0(n7081), .B1(n6875), .C0(n7057), .C1(n6874), .Y(n6370) );
XOR2X1TS U7759 ( .A(n6371), .B(n7087), .Y(mult_x_24_n1419) );
AOI222X1TS U7760 ( .A0(n7083), .A1(n6868), .B0(n7081), .B1(Op_MX[5]), .C0(
n7057), .C1(n6863), .Y(n6372) );
OAI21X1TS U7761 ( .A0(n6865), .A1(n7085), .B0(n6372), .Y(n6373) );
XOR2X1TS U7762 ( .A(n6373), .B(n6882), .Y(mult_x_24_n1420) );
OAI21X1TS U7763 ( .A0(n7050), .A1(n7085), .B0(n6374), .Y(n6375) );
XOR2X1TS U7764 ( .A(n6375), .B(n6882), .Y(mult_x_24_n1421) );
NAND2X1TS U7765 ( .A(n6405), .B(n6989), .Y(n6376) );
XOR2X1TS U7766 ( .A(n6377), .B(n8392), .Y(mult_x_24_n1428) );
AOI21X1TS U7767 ( .A0(n6405), .A1(n925), .B0(n6378), .Y(n6379) );
OAI21X1TS U7768 ( .A0(n7006), .A1(n6442), .B0(n6379), .Y(n6380) );
XOR2X1TS U7769 ( .A(n6380), .B(n8392), .Y(mult_x_24_n1429) );
AOI222X1TS U7770 ( .A0(n7072), .A1(n6963), .B0(n6440), .B1(n6961), .C0(n6405), .C1(n6959), .Y(n6381) );
XOR2X1TS U7771 ( .A(n6382), .B(n836), .Y(mult_x_24_n1430) );
AOI222X1TS U7772 ( .A0(n6736), .A1(n6961), .B0(n6440), .B1(n6767), .C0(n6405), .C1(n834), .Y(n6383) );
OAI21X1TS U7773 ( .A0(n6769), .A1(n6442), .B0(n6383), .Y(n6384) );
XOR2X1TS U7774 ( .A(n6384), .B(Op_MY[23]), .Y(mult_x_24_n1431) );
AOI222X1TS U7775 ( .A0(n6736), .A1(n6767), .B0(n6440), .B1(n6701), .C0(n6405), .C1(n6484), .Y(n6385) );
OAI21X1TS U7776 ( .A0(n6703), .A1(n6442), .B0(n6385), .Y(n6386) );
XOR2X1TS U7777 ( .A(n6386), .B(Op_MY[23]), .Y(mult_x_24_n1432) );
BUFX3TS U7778 ( .A(n6551), .Y(n6922) );
AOI222X1TS U7779 ( .A0(n6736), .A1(n6701), .B0(n6440), .B1(n6922), .C0(n844),
.C1(n6952), .Y(n6387) );
XOR2X1TS U7780 ( .A(n6388), .B(n836), .Y(mult_x_24_n1433) );
INVX2TS U7781 ( .A(n6395), .Y(n6397) );
XNOR2X4TS U7782 ( .A(n6399), .B(n6398), .Y(n6400) );
INVX12TS U7783 ( .A(n6400), .Y(n6926) );
AOI222X1TS U7784 ( .A0(n6736), .A1(n6922), .B0(n6440), .B1(n6814), .C0(n844),
.C1(n879), .Y(n6401) );
OAI21X1TS U7785 ( .A0(n6926), .A1(n6442), .B0(n6401), .Y(n6402) );
OAI21X2TS U7786 ( .A0(n6850), .A1(n6442), .B0(n6403), .Y(n6404) );
XOR2X1TS U7787 ( .A(n6404), .B(n836), .Y(mult_x_24_n1435) );
AOI222X1TS U7788 ( .A0(n6736), .A1(n6846), .B0(n6440), .B1(n6830), .C0(n6405), .C1(n927), .Y(n6406) );
OAI21X1TS U7789 ( .A0(n6832), .A1(n6442), .B0(n6406), .Y(n6407) );
XOR2X1TS U7790 ( .A(n6407), .B(n8392), .Y(mult_x_24_n1436) );
AOI222X1TS U7791 ( .A0(n7072), .A1(n6830), .B0(n6440), .B1(n6929), .C0(n844),
.C1(n6559), .Y(n6408) );
XOR2X1TS U7792 ( .A(n6409), .B(n8392), .Y(mult_x_24_n1437) );
AOI222X1TS U7793 ( .A0(n6736), .A1(n6929), .B0(n7070), .B1(n6790), .C0(n6473), .C1(n6562), .Y(n6410) );
OAI21X1TS U7794 ( .A0(n6793), .A1(n7074), .B0(n6410), .Y(n6411) );
XOR2X1TS U7795 ( .A(n6411), .B(Op_MY[23]), .Y(mult_x_24_n1438) );
BUFX3TS U7796 ( .A(n6562), .Y(n6915) );
AOI222X1TS U7797 ( .A0(n7072), .A1(n6790), .B0(n7070), .B1(n6915), .C0(n6473), .C1(n6945), .Y(n6412) );
OAI21X1TS U7798 ( .A0(n6918), .A1(n7074), .B0(n6412), .Y(n6413) );
XOR2X1TS U7799 ( .A(n6413), .B(n836), .Y(mult_x_24_n1439) );
INVX2TS U7800 ( .A(n6414), .Y(n6416) );
NAND2X1TS U7801 ( .A(n6416), .B(n6415), .Y(n6417) );
AOI222X1TS U7802 ( .A0(n7072), .A1(n6915), .B0(n7070), .B1(n938), .C0(n6473),
.C1(n6785), .Y(n6418) );
OAI21X1TS U7803 ( .A0(n729), .A1(n7074), .B0(n6418), .Y(n6419) );
XOR2X1TS U7804 ( .A(n6419), .B(n8392), .Y(mult_x_24_n1440) );
INVX2TS U7805 ( .A(n6420), .Y(n6421) );
INVX2TS U7806 ( .A(n6423), .Y(n6426) );
OAI21X4TS U7807 ( .A0(n6461), .A1(n6431), .B0(n6430), .Y(n6436) );
INVX2TS U7808 ( .A(n6432), .Y(n6434) );
XNOR2X4TS U7809 ( .A(n6436), .B(n6435), .Y(n6437) );
AOI222X1TS U7810 ( .A0(n7072), .A1(n939), .B0(n7070), .B1(n7071), .C0(n6473),
.C1(n7056), .Y(n6438) );
OAI21X1TS U7811 ( .A0(n7063), .A1(n7074), .B0(n6438), .Y(n6439) );
AOI222X1TS U7812 ( .A0(n7072), .A1(n7069), .B0(n6440), .B1(n7009), .C0(n844),
.C1(n827), .Y(n6441) );
OAI21X1TS U7813 ( .A0(n7014), .A1(n6442), .B0(n6441), .Y(n6443) );
XOR2X1TS U7814 ( .A(n6443), .B(n836), .Y(mult_x_24_n1443) );
INVX2TS U7815 ( .A(n6444), .Y(n6463) );
INVX2TS U7816 ( .A(n6462), .Y(n6445) );
AOI21X1TS U7817 ( .A0(n6458), .A1(n6463), .B0(n6445), .Y(n6446) );
INVX2TS U7818 ( .A(n6448), .Y(n6450) );
BUFX3TS U7819 ( .A(n6753), .Y(n7082) );
AOI222X1TS U7820 ( .A0(n6761), .A1(n6574), .B0(n6760), .B1(n7082), .C0(n844),
.C1(n6958), .Y(n6455) );
OAI21X1TS U7821 ( .A0(n6855), .A1(n6763), .B0(n6455), .Y(n6456) );
XOR2X1TS U7822 ( .A(n6456), .B(n7076), .Y(mult_x_24_n1445) );
INVX2TS U7823 ( .A(n6457), .Y(n6460) );
INVX2TS U7824 ( .A(n6458), .Y(n6459) );
OAI21X4TS U7825 ( .A0(n6461), .A1(n6460), .B0(n6459), .Y(n6465) );
XNOR2X4TS U7826 ( .A(n6465), .B(n6464), .Y(n6466) );
AOI222X1TS U7827 ( .A0(n6761), .A1(n7082), .B0(n6760), .B1(n841), .C0(n844),
.C1(n7079), .Y(n6467) );
XOR2X1TS U7828 ( .A(n6468), .B(n7076), .Y(mult_x_24_n1446) );
AOI222X1TS U7829 ( .A0(n6761), .A1(n841), .B0(n6760), .B1(n6910), .C0(n844),
.C1(n826), .Y(n6469) );
OAI21X1TS U7830 ( .A0(n6912), .A1(n6763), .B0(n6469), .Y(n6470) );
XOR2X1TS U7831 ( .A(n6470), .B(n8392), .Y(mult_x_24_n1447) );
AOI222X1TS U7832 ( .A0(n6761), .A1(n7033), .B0(n6760), .B1(n6868), .C0(n6473), .C1(n6874), .Y(n6471) );
OAI21X1TS U7833 ( .A0(n6879), .A1(n6763), .B0(n6471), .Y(n6472) );
AOI222X1TS U7834 ( .A0(n6761), .A1(n6868), .B0(n6760), .B1(n6859), .C0(n6473), .C1(n6888), .Y(n6474) );
OAI21X1TS U7835 ( .A0(n6865), .A1(n6763), .B0(n6474), .Y(n6475) );
XOR2X1TS U7836 ( .A(n6475), .B(n7076), .Y(mult_x_24_n1450) );
AOI222X1TS U7837 ( .A0(n883), .A1(n6963), .B0(n7010), .B1(n6961), .C0(n6491),
.C1(n6959), .Y(n6476) );
OAI21X1TS U7838 ( .A0(n6967), .A1(n7013), .B0(n6476), .Y(n6477) );
INVX2TS U7839 ( .A(n1018), .Y(n6794) );
XOR2X1TS U7840 ( .A(n6477), .B(n6861), .Y(mult_x_24_n1460) );
AOI222X1TS U7841 ( .A0(n883), .A1(n926), .B0(n7010), .B1(n6767), .C0(n6491),
.C1(n834), .Y(n6478) );
OAI21X1TS U7842 ( .A0(n6769), .A1(n7013), .B0(n6478), .Y(n6479) );
XOR2X1TS U7843 ( .A(n6479), .B(n6220), .Y(mult_x_24_n1461) );
BUFX3TS U7844 ( .A(Op_MX[24]), .Y(n6756) );
AOI222X1TS U7845 ( .A0(n883), .A1(n6756), .B0(n7010), .B1(n6701), .C0(n6491),
.C1(n6484), .Y(n6480) );
OAI21X1TS U7846 ( .A0(n6703), .A1(n7013), .B0(n6480), .Y(n6481) );
XOR2X1TS U7847 ( .A(n6481), .B(n6794), .Y(mult_x_24_n1462) );
AOI222X1TS U7848 ( .A0(n883), .A1(n833), .B0(n7010), .B1(n6922), .C0(n6491),
.C1(n6952), .Y(n6482) );
OAI21X1TS U7849 ( .A0(n6778), .A1(n7013), .B0(n6482), .Y(n6483) );
BUFX3TS U7850 ( .A(n6484), .Y(n6816) );
AOI222X1TS U7851 ( .A0(n883), .A1(n6816), .B0(n7010), .B1(n6814), .C0(n6491),
.C1(n877), .Y(n6485) );
OAI21X1TS U7852 ( .A0(n6926), .A1(n7013), .B0(n6485), .Y(n6486) );
XOR2X1TS U7853 ( .A(n6486), .B(n6861), .Y(mult_x_24_n1464) );
BUFX3TS U7854 ( .A(Op_MX[21]), .Y(n6847) );
AOI222X1TS U7855 ( .A0(n883), .A1(n877), .B0(n7010), .B1(n6830), .C0(n6491),
.C1(n8403), .Y(n6489) );
OAI21X1TS U7856 ( .A0(n6832), .A1(n7013), .B0(n6489), .Y(n6490) );
XOR2X1TS U7857 ( .A(n6490), .B(n6794), .Y(mult_x_24_n1466) );
OAI21X1TS U7858 ( .A0(n6933), .A1(n6792), .B0(n6492), .Y(n6493) );
XOR2X1TS U7859 ( .A(n6493), .B(n6861), .Y(mult_x_24_n1467) );
BUFX3TS U7860 ( .A(n6562), .Y(n6894) );
XOR2X1TS U7861 ( .A(n6495), .B(n6220), .Y(mult_x_24_n1470) );
AOI222X1TS U7862 ( .A0(n7011), .A1(n937), .B0(n6834), .B1(n7071), .C0(n6867),
.C1(n7056), .Y(n6496) );
OAI21X1TS U7863 ( .A0(n7063), .A1(n6792), .B0(n6496), .Y(n6497) );
XOR2X1TS U7864 ( .A(n6497), .B(n6861), .Y(mult_x_24_n1471) );
XOR2X1TS U7865 ( .A(n6499), .B(n6794), .Y(mult_x_24_n1472) );
AOI222X1TS U7866 ( .A0(n6870), .A1(Op_MX[12]), .B0(n6869), .B1(n6574), .C0(
n5076), .C1(n6753), .Y(n6500) );
OAI21X1TS U7867 ( .A0(n6775), .A1(n6872), .B0(n6500), .Y(n6501) );
XOR2X1TS U7868 ( .A(n6501), .B(n7494), .Y(mult_x_24_n1474) );
BUFX3TS U7869 ( .A(n7008), .Y(n6853) );
AOI222X1TS U7870 ( .A0(n883), .A1(n6853), .B0(n6869), .B1(n7082), .C0(n5076),
.C1(n841), .Y(n6502) );
OAI21X1TS U7871 ( .A0(n6855), .A1(n6872), .B0(n6502), .Y(n6503) );
XOR2X1TS U7872 ( .A(n6503), .B(n7494), .Y(mult_x_24_n1475) );
BUFX3TS U7873 ( .A(n910), .Y(n6904) );
AOI222X1TS U7874 ( .A0(n883), .A1(n6904), .B0(n6869), .B1(n842), .C0(n5076),
.C1(n8413), .Y(n6504) );
XOR2X1TS U7875 ( .A(n6505), .B(n7494), .Y(mult_x_24_n1476) );
AOI222X1TS U7876 ( .A0(n883), .A1(n841), .B0(n6869), .B1(n6910), .C0(n5076),
.C1(n826), .Y(n6506) );
XOR2X1TS U7877 ( .A(n6507), .B(n7494), .Y(mult_x_24_n1477) );
AOI222X1TS U7878 ( .A0(n6870), .A1(n7046), .B0(n6834), .B1(n7044), .C0(n6867), .C1(n6584), .Y(n6508) );
OAI21X1TS U7879 ( .A0(n7050), .A1(n6872), .B0(n6508), .Y(n6509) );
XOR2X1TS U7880 ( .A(n6509), .B(n6861), .Y(mult_x_24_n1481) );
NAND2X1TS U7881 ( .A(n6960), .B(n6989), .Y(n6510) );
XOR2X1TS U7882 ( .A(n6511), .B(n893), .Y(mult_x_24_n1488) );
AOI21X1TS U7883 ( .A0(n6960), .A1(n926), .B0(n6513), .Y(n6514) );
XOR2X1TS U7884 ( .A(n6515), .B(n893), .Y(mult_x_24_n1489) );
AOI222X1TS U7885 ( .A0(n6796), .A1(n925), .B0(n6962), .B1(n6767), .C0(n6960),
.C1(n834), .Y(n6516) );
OAI21X1TS U7886 ( .A0(n6769), .A1(n6966), .B0(n6516), .Y(n6518) );
AOI222X1TS U7887 ( .A0(n6796), .A1(n6756), .B0(n6962), .B1(n6701), .C0(n6960), .C1(n6551), .Y(n6519) );
OAI21X1TS U7888 ( .A0(n6703), .A1(n6966), .B0(n6519), .Y(n6520) );
XOR2X1TS U7889 ( .A(n6520), .B(n6968), .Y(mult_x_24_n1492) );
OAI21X1TS U7890 ( .A0(n6850), .A1(n6966), .B0(n6521), .Y(n6522) );
XOR2X1TS U7891 ( .A(n6522), .B(n6968), .Y(mult_x_24_n1495) );
AOI222X1TS U7892 ( .A0(n6796), .A1(n878), .B0(n6962), .B1(n6830), .C0(n6960),
.C1(n927), .Y(n6523) );
AOI222X1TS U7893 ( .A0(n6796), .A1(Op_MX[18]), .B0(n6786), .B1(n6790), .C0(
n6805), .C1(Op_MX[16]), .Y(n6525) );
OAI21X1TS U7894 ( .A0(n6793), .A1(n6788), .B0(n6525), .Y(n6526) );
XOR2X1TS U7895 ( .A(n6526), .B(n6968), .Y(mult_x_24_n1498) );
BUFX3TS U7896 ( .A(n6559), .Y(n6928) );
AOI222X1TS U7897 ( .A0(n6964), .A1(n6928), .B0(n6786), .B1(n6915), .C0(n6531), .C1(n6945), .Y(n6527) );
OAI21X1TS U7898 ( .A0(n6918), .A1(n6788), .B0(n6527), .Y(n6528) );
XOR2X1TS U7899 ( .A(n6528), .B(n6968), .Y(mult_x_24_n1499) );
AOI222X1TS U7900 ( .A0(n6964), .A1(n939), .B0(n6786), .B1(n7071), .C0(n6531),
.C1(n7056), .Y(n6529) );
OAI21X1TS U7901 ( .A0(n7063), .A1(n6788), .B0(n6529), .Y(n6530) );
XOR2X1TS U7902 ( .A(n6530), .B(n893), .Y(mult_x_24_n1501) );
OAI21X1TS U7903 ( .A0(n7075), .A1(n6788), .B0(n6532), .Y(n6533) );
XOR2X1TS U7904 ( .A(n6533), .B(n893), .Y(mult_x_24_n1502) );
AOI222X1TS U7905 ( .A0(n6964), .A1(n6569), .B0(n6962), .B1(n7009), .C0(n6805), .C1(n7008), .Y(n6534) );
XOR2X1TS U7906 ( .A(n6535), .B(n835), .Y(mult_x_24_n1503) );
BUFX4TS U7907 ( .A(n6962), .Y(n6806) );
AOI222X1TS U7908 ( .A0(n6807), .A1(n6904), .B0(n6806), .B1(n842), .C0(n6805),
.C1(n7079), .Y(n6536) );
AOI222X1TS U7909 ( .A0(n6807), .A1(n6958), .B0(n6806), .B1(n6910), .C0(n6805), .C1(n826), .Y(n6538) );
OAI21X1TS U7910 ( .A0(n6912), .A1(n6809), .B0(n6538), .Y(n6539) );
XOR2X1TS U7911 ( .A(n6539), .B(n835), .Y(mult_x_24_n1507) );
AOI222X1TS U7912 ( .A0(n6807), .A1(n6909), .B0(n6806), .B1(n6868), .C0(n6531), .C1(n6874), .Y(n6540) );
AOI222X1TS U7913 ( .A0(n6807), .A1(n7031), .B0(n6806), .B1(n6859), .C0(n6531), .C1(n6863), .Y(n6542) );
XOR2X1TS U7914 ( .A(n6543), .B(n893), .Y(mult_x_24_n1510) );
AOI222X1TS U7915 ( .A0(n7023), .A1(n6963), .B0(n6980), .B1(n925), .C0(n6581),
.C1(n6959), .Y(n6545) );
AOI222X1TS U7916 ( .A0(n6771), .A1(n6961), .B0(n6980), .B1(Op_MX[24]), .C0(
n6982), .C1(n834), .Y(n6547) );
AOI222X1TS U7917 ( .A0(n6771), .A1(n6767), .B0(n6980), .B1(n833), .C0(n6982),
.C1(n6551), .Y(n6549) );
OAI21X1TS U7918 ( .A0(n6703), .A1(n6984), .B0(n6549), .Y(n6550) );
XOR2X1TS U7919 ( .A(n6550), .B(n6827), .Y(mult_x_24_n1522) );
AOI222X1TS U7920 ( .A0(n6771), .A1(n6701), .B0(n6980), .B1(n6551), .C0(n6581), .C1(n6952), .Y(n6552) );
XOR2X1TS U7921 ( .A(n6553), .B(n6827), .Y(mult_x_24_n1523) );
OAI21X1TS U7922 ( .A0(n6926), .A1(n6984), .B0(n6554), .Y(n6555) );
AOI222X1TS U7923 ( .A0(n6771), .A1(n6846), .B0(n6980), .B1(n6749), .C0(n6581), .C1(n6829), .Y(n6556) );
OAI21X1TS U7924 ( .A0(n6832), .A1(n6984), .B0(n6556), .Y(n6557) );
XOR2X1TS U7925 ( .A(n6557), .B(n6827), .Y(mult_x_24_n1526) );
BUFX6TS U7926 ( .A(n6558), .Y(n7021) );
AOI222X1TS U7927 ( .A0(n6771), .A1(n6929), .B0(n7021), .B1(n6559), .C0(n7019), .C1(n6562), .Y(n6560) );
OAI21X1TS U7928 ( .A0(n6793), .A1(n7025), .B0(n6560), .Y(n6561) );
XOR2X1TS U7929 ( .A(n6561), .B(n6827), .Y(mult_x_24_n1528) );
AOI222X1TS U7930 ( .A0(n7023), .A1(n6790), .B0(n7021), .B1(n6562), .C0(n7019), .C1(n6945), .Y(n6563) );
OAI21X1TS U7931 ( .A0(n6918), .A1(n7025), .B0(n6563), .Y(n6564) );
XOR2X1TS U7932 ( .A(n6564), .B(n6827), .Y(mult_x_24_n1529) );
AOI222X1TS U7933 ( .A0(n7023), .A1(n6915), .B0(n7021), .B1(n939), .C0(n7019),
.C1(n6785), .Y(n6565) );
XOR2X1TS U7934 ( .A(n6566), .B(n7027), .Y(mult_x_24_n1530) );
OAI21X1TS U7935 ( .A0(n7063), .A1(n7025), .B0(n6567), .Y(n6568) );
XOR2X1TS U7936 ( .A(n6568), .B(n7027), .Y(mult_x_24_n1531) );
OAI21X1TS U7937 ( .A0(n7075), .A1(n7025), .B0(n6570), .Y(n6571) );
XOR2X1TS U7938 ( .A(n6571), .B(n7027), .Y(mult_x_24_n1532) );
AOI222X1TS U7939 ( .A0(n7023), .A1(n7069), .B0(n6980), .B1(Op_MX[12]), .C0(
n6581), .C1(n7008), .Y(n6572) );
OAI21X1TS U7940 ( .A0(n7014), .A1(n6984), .B0(n6572), .Y(n6573) );
XOR2X1TS U7941 ( .A(n6573), .B(n7490), .Y(mult_x_24_n1533) );
AOI222X1TS U7942 ( .A0(n6771), .A1(n7009), .B0(n6876), .B1(n6574), .C0(n6581), .C1(n6753), .Y(n6575) );
OAI21X1TS U7943 ( .A0(n6775), .A1(n6899), .B0(n6575), .Y(n6576) );
XOR2X1TS U7944 ( .A(n6576), .B(n7490), .Y(mult_x_24_n1534) );
AOI222X1TS U7945 ( .A0(n6877), .A1(n827), .B0(n6876), .B1(n6753), .C0(n6581),
.C1(n6958), .Y(n6577) );
OAI21X1TS U7946 ( .A0(n6855), .A1(n6899), .B0(n6577), .Y(n6578) );
XOR2X1TS U7947 ( .A(n6578), .B(n7490), .Y(mult_x_24_n1535) );
XOR2X1TS U7948 ( .A(n6580), .B(n7490), .Y(mult_x_24_n1536) );
AOI222X1TS U7949 ( .A0(n6877), .A1(n842), .B0(n6876), .B1(n8413), .C0(n6581),
.C1(n826), .Y(n6582) );
XOR2X1TS U7950 ( .A(n6583), .B(n7490), .Y(mult_x_24_n1537) );
OAI21X1TS U7951 ( .A0(n7050), .A1(n6899), .B0(n6585), .Y(n6586) );
XOR2X1TS U7952 ( .A(n6586), .B(n7027), .Y(mult_x_24_n1541) );
BUFX6TS U7953 ( .A(n6615), .Y(n6997) );
NAND2X1TS U7954 ( .A(n6997), .B(n6989), .Y(n6587) );
OAI21X1TS U7955 ( .A0(n6993), .A1(n6841), .B0(n6587), .Y(n6588) );
XOR2X1TS U7956 ( .A(n6588), .B(n8373), .Y(mult_x_24_n1548) );
BUFX8TS U7957 ( .A(n6589), .Y(n6995) );
AOI222X1TS U7958 ( .A0(n6848), .A1(n6756), .B0(n6995), .B1(n6701), .C0(n6997), .C1(n6816), .Y(n6590) );
OAI21X1TS U7959 ( .A0(n6703), .A1(n6999), .B0(n6590), .Y(n6591) );
XOR2X1TS U7960 ( .A(n6591), .B(n6851), .Y(mult_x_24_n1552) );
AOI222X1TS U7961 ( .A0(n6848), .A1(Op_MX[23]), .B0(n6995), .B1(n6922), .C0(
n6997), .C1(n6847), .Y(n6592) );
OAI21X1TS U7962 ( .A0(n6778), .A1(n6999), .B0(n6592), .Y(n6593) );
XOR2X1TS U7963 ( .A(n6593), .B(n6851), .Y(mult_x_24_n1553) );
AOI222X1TS U7964 ( .A0(n6848), .A1(n6816), .B0(n6995), .B1(n6814), .C0(n6997), .C1(n877), .Y(n6594) );
OAI21X1TS U7965 ( .A0(n6926), .A1(n6999), .B0(n6594), .Y(n6595) );
XOR2X1TS U7966 ( .A(n6595), .B(n6851), .Y(mult_x_24_n1554) );
OAI21X1TS U7967 ( .A0(n6793), .A1(n6841), .B0(n6596), .Y(n6597) );
XOR2X1TS U7968 ( .A(n6597), .B(n6851), .Y(mult_x_24_n1558) );
XOR2X1TS U7969 ( .A(n6599), .B(n6851), .Y(mult_x_24_n1559) );
XOR2X1TS U7970 ( .A(n6601), .B(n7051), .Y(mult_x_24_n1560) );
OAI21X1TS U7971 ( .A0(n7063), .A1(n6841), .B0(n6602), .Y(n6603) );
XOR2X1TS U7972 ( .A(n6603), .B(n7051), .Y(mult_x_24_n1561) );
AOI222X1TS U7973 ( .A0(n6839), .A1(n6569), .B0(n6995), .B1(n7009), .C0(n7043), .C1(n6853), .Y(n6606) );
XOR2X1TS U7974 ( .A(n6607), .B(Op_MY[11]), .Y(mult_x_24_n1563) );
BUFX3TS U7975 ( .A(n6608), .Y(n7047) );
AOI222X1TS U7976 ( .A0(n7047), .A1(n6904), .B0(n6843), .B1(n842), .C0(n7043),
.C1(n7035), .Y(n6609) );
XOR2X1TS U7977 ( .A(n6610), .B(Op_MY[11]), .Y(mult_x_24_n1566) );
AOI222X1TS U7978 ( .A0(n7047), .A1(n841), .B0(n6843), .B1(n6910), .C0(n7043),
.C1(n6909), .Y(n6611) );
XOR2X1TS U7979 ( .A(n6612), .B(n8373), .Y(mult_x_24_n1567) );
AOI222X1TS U7980 ( .A0(n7047), .A1(n7035), .B0(n6843), .B1(n7033), .C0(n7043), .C1(n7031), .Y(n6613) );
OAI21X1TS U7981 ( .A0(n7039), .A1(n7049), .B0(n6613), .Y(n6614) );
XOR2X1TS U7982 ( .A(n6614), .B(n8373), .Y(mult_x_24_n1568) );
AOI222X1TS U7983 ( .A0(n7047), .A1(n6909), .B0(n6843), .B1(n6868), .C0(n6615), .C1(n7046), .Y(n6616) );
OAI21X1TS U7984 ( .A0(n6879), .A1(n7049), .B0(n6616), .Y(n6617) );
XOR2X1TS U7985 ( .A(n6617), .B(n8373), .Y(mult_x_24_n1569) );
AOI222X1TS U7986 ( .A0(n7047), .A1(n7031), .B0(n6843), .B1(n6859), .C0(n7043), .C1(n6888), .Y(n6618) );
XOR2X1TS U7987 ( .A(n6619), .B(n7051), .Y(mult_x_24_n1570) );
BUFX6TS U7988 ( .A(n6620), .Y(n6970) );
AOI222X1TS U7989 ( .A0(n6750), .A1(n926), .B0(n6970), .B1(n6767), .C0(n6990),
.C1(n833), .Y(n6621) );
OAI21X1TS U7990 ( .A0(n6769), .A1(n6973), .B0(n6621), .Y(n6622) );
XOR2X1TS U7991 ( .A(n6622), .B(n6758), .Y(mult_x_24_n1581) );
AOI222X1TS U7992 ( .A0(n6750), .A1(n6756), .B0(n6970), .B1(n6701), .C0(n6990), .C1(n6816), .Y(n6623) );
OAI21X1TS U7993 ( .A0(n6703), .A1(n6973), .B0(n6623), .Y(n6624) );
XOR2X1TS U7994 ( .A(n6624), .B(n6758), .Y(mult_x_24_n1582) );
AOI222X1TS U7995 ( .A0(n6750), .A1(Op_MX[23]), .B0(n6970), .B1(n6922), .C0(
n6990), .C1(n6847), .Y(n6625) );
OAI21X1TS U7996 ( .A0(n6778), .A1(n6973), .B0(n6625), .Y(n6626) );
XOR2X1TS U7997 ( .A(n6626), .B(n6758), .Y(mult_x_24_n1583) );
AOI222X1TS U7998 ( .A0(n6750), .A1(n6816), .B0(n6970), .B1(n6814), .C0(n6990), .C1(n878), .Y(n6627) );
OAI21X1TS U7999 ( .A0(n6926), .A1(n6973), .B0(n6627), .Y(n6628) );
XOR2X1TS U8000 ( .A(n6628), .B(n6758), .Y(mult_x_24_n1584) );
OAI21X1TS U8001 ( .A0(n6832), .A1(n6973), .B0(n6629), .Y(n6630) );
OAI21X1TS U8002 ( .A0(n6933), .A1(n6992), .B0(n6631), .Y(n6632) );
XOR2X1TS U8003 ( .A(n6632), .B(n6758), .Y(mult_x_24_n1587) );
AOI222X1TS U8004 ( .A0(n6750), .A1(n8403), .B0(n6887), .B1(n6790), .C0(n6885), .C1(n6894), .Y(n6633) );
OAI21X1TS U8005 ( .A0(n6793), .A1(n6992), .B0(n6633), .Y(n6634) );
XOR2X1TS U8006 ( .A(n6634), .B(n6758), .Y(mult_x_24_n1588) );
AOI222X1TS U8007 ( .A0(n6889), .A1(n6928), .B0(n6887), .B1(n6915), .C0(n6885), .C1(n939), .Y(n6635) );
OAI21X1TS U8008 ( .A0(n6918), .A1(n6992), .B0(n6635), .Y(n6636) );
XOR2X1TS U8009 ( .A(n6636), .B(n6758), .Y(mult_x_24_n1589) );
AOI222X1TS U8010 ( .A0(n6889), .A1(n939), .B0(n6887), .B1(n7071), .C0(n6885),
.C1(n6569), .Y(n6637) );
OAI21X1TS U8011 ( .A0(n7063), .A1(n6992), .B0(n6637), .Y(n6638) );
XOR2X1TS U8012 ( .A(n6638), .B(n6891), .Y(mult_x_24_n1591) );
XOR2X1TS U8013 ( .A(n6641), .B(n6891), .Y(mult_x_24_n1592) );
AOI222X1TS U8014 ( .A0(n6889), .A1(Op_MX[13]), .B0(n6970), .B1(n7009), .C0(
n7032), .C1(n6853), .Y(n6642) );
OAI21X1TS U8015 ( .A0(n7014), .A1(n6973), .B0(n6642), .Y(n6643) );
XOR2X1TS U8016 ( .A(n6643), .B(n7040), .Y(mult_x_24_n1593) );
BUFX4TS U8017 ( .A(n6970), .Y(n7034) );
OAI21X1TS U8018 ( .A0(n6775), .A1(n7038), .B0(n6645), .Y(n6646) );
XOR2X1TS U8019 ( .A(n6646), .B(n7040), .Y(mult_x_24_n1594) );
BUFX3TS U8020 ( .A(n6750), .Y(n7036) );
OAI21X1TS U8021 ( .A0(n6855), .A1(n7038), .B0(n6647), .Y(n6648) );
XOR2X1TS U8022 ( .A(n6648), .B(n7040), .Y(mult_x_24_n1595) );
AOI222X1TS U8023 ( .A0(n7036), .A1(n6904), .B0(n7034), .B1(n842), .C0(n7032),
.C1(n7035), .Y(n6649) );
XOR2X1TS U8024 ( .A(n6650), .B(n7040), .Y(mult_x_24_n1596) );
AOI222X1TS U8025 ( .A0(n7036), .A1(n6909), .B0(n7034), .B1(n6868), .C0(n6885), .C1(n7046), .Y(n6651) );
XOR2X1TS U8026 ( .A(n6652), .B(n7040), .Y(mult_x_24_n1599) );
AOI222X1TS U8027 ( .A0(n7036), .A1(n7046), .B0(n6887), .B1(n7044), .C0(n6885), .C1(n7042), .Y(n6653) );
OAI21X1TS U8028 ( .A0(n7050), .A1(n7038), .B0(n6653), .Y(n6654) );
XOR2X1TS U8029 ( .A(n6654), .B(n6891), .Y(mult_x_24_n1601) );
NAND2X1TS U8030 ( .A(n6813), .B(n6989), .Y(n6655) );
OAI21X1TS U8031 ( .A0(n6993), .A1(n6681), .B0(n6655), .Y(n6656) );
XOR2X1TS U8032 ( .A(n6656), .B(n940), .Y(mult_x_24_n1608) );
AOI21X1TS U8033 ( .A0(n6813), .A1(n926), .B0(n6657), .Y(n6658) );
OAI21X1TS U8034 ( .A0(n7006), .A1(n6819), .B0(n6658), .Y(n6659) );
XOR2X1TS U8035 ( .A(n6659), .B(n940), .Y(mult_x_24_n1609) );
OAI21X1TS U8036 ( .A0(n6967), .A1(n6819), .B0(n6660), .Y(n6661) );
XOR2X1TS U8037 ( .A(n6661), .B(n6695), .Y(mult_x_24_n1610) );
OAI21X1TS U8038 ( .A0(n6769), .A1(n6819), .B0(n6662), .Y(n6663) );
XOR2X1TS U8039 ( .A(n6663), .B(n8377), .Y(mult_x_24_n1611) );
OAI21X1TS U8040 ( .A0(n6703), .A1(n6819), .B0(n6664), .Y(n6665) );
XOR2X1TS U8041 ( .A(n6665), .B(n940), .Y(mult_x_24_n1612) );
OAI21X1TS U8042 ( .A0(n6778), .A1(n6819), .B0(n6666), .Y(n6667) );
XOR2X1TS U8043 ( .A(n6667), .B(n6820), .Y(mult_x_24_n1613) );
OAI21X1TS U8044 ( .A0(n6850), .A1(n6819), .B0(n6668), .Y(n6669) );
XOR2X1TS U8045 ( .A(n6669), .B(n8377), .Y(mult_x_24_n1615) );
AOI222X1TS U8046 ( .A0(n6683), .A1(n6749), .B0(n886), .B1(n6929), .C0(n6813),
.C1(n6928), .Y(n6670) );
OAI21X1TS U8047 ( .A0(n6933), .A1(n6681), .B0(n6670), .Y(n6671) );
OAI21X1TS U8048 ( .A0(n6793), .A1(n6681), .B0(n6672), .Y(n6673) );
XOR2X1TS U8049 ( .A(n6673), .B(n6820), .Y(mult_x_24_n1618) );
OAI21X1TS U8050 ( .A0(n6918), .A1(n6681), .B0(n6674), .Y(n6675) );
XOR2X1TS U8051 ( .A(n6675), .B(n940), .Y(mult_x_24_n1619) );
XOR2X1TS U8052 ( .A(n6677), .B(n940), .Y(mult_x_24_n1620) );
OAI21X1TS U8053 ( .A0(n7063), .A1(n6681), .B0(n6678), .Y(n6679) );
XOR2X1TS U8054 ( .A(n6679), .B(n6695), .Y(mult_x_24_n1621) );
XOR2X1TS U8055 ( .A(n6682), .B(n6695), .Y(mult_x_24_n1622) );
XOR2X1TS U8056 ( .A(n6685), .B(n6695), .Y(mult_x_24_n1623) );
AOI222X1TS U8057 ( .A0(n6905), .A1(Op_MX[9]), .B0(n6903), .B1(n6910), .C0(
n6902), .C1(n6909), .Y(n6689) );
XOR2X1TS U8058 ( .A(n6690), .B(n6820), .Y(mult_x_24_n1627) );
AOI222X1TS U8059 ( .A0(n6905), .A1(n6909), .B0(n6903), .B1(n6868), .C0(n823),
.C1(n7046), .Y(n6691) );
XOR2X1TS U8060 ( .A(n6692), .B(n940), .Y(mult_x_24_n1629) );
AOI222X1TS U8061 ( .A0(n6905), .A1(n7031), .B0(n6903), .B1(n6859), .C0(n823),
.C1(n6888), .Y(n6694) );
OAI21X1TS U8062 ( .A0(n6865), .A1(n6907), .B0(n6694), .Y(n6696) );
XOR2X1TS U8063 ( .A(n6696), .B(n6820), .Y(mult_x_24_n1630) );
AOI222X1TS U8064 ( .A0(n885), .A1(n6963), .B0(n1083), .B1(n6961), .C0(n7003),
.C1(n6756), .Y(n6697) );
AOI222X1TS U8065 ( .A0(n1047), .A1(n926), .B0(n1083), .B1(n6767), .C0(n7003),
.C1(n833), .Y(n6699) );
OAI21X1TS U8066 ( .A0(n6769), .A1(n7005), .B0(n6699), .Y(n6700) );
XOR2X1TS U8067 ( .A(n6700), .B(n8391), .Y(mult_x_24_n1641) );
AOI222X1TS U8068 ( .A0(n1047), .A1(n6756), .B0(n1083), .B1(n6701), .C0(n7003), .C1(n6816), .Y(n6702) );
OAI21X1TS U8069 ( .A0(n6703), .A1(n7005), .B0(n6702), .Y(n6704) );
XOR2X1TS U8070 ( .A(n6704), .B(n6730), .Y(mult_x_24_n1642) );
AOI222X1TS U8071 ( .A0(n885), .A1(Op_MX[23]), .B0(n1083), .B1(n6922), .C0(
n7003), .C1(n6847), .Y(n6705) );
OAI21X1TS U8072 ( .A0(n6778), .A1(n7005), .B0(n6705), .Y(n6706) );
XOR2X1TS U8073 ( .A(n6706), .B(n8391), .Y(mult_x_24_n1643) );
AOI222X1TS U8074 ( .A0(n884), .A1(n6816), .B0(n1083), .B1(n6814), .C0(n7003),
.C1(Op_MX[20]), .Y(n6707) );
OAI21X1TS U8075 ( .A0(n6926), .A1(n7005), .B0(n6707), .Y(n6708) );
XOR2X1TS U8076 ( .A(n6708), .B(n6730), .Y(mult_x_24_n1644) );
OAI21X1TS U8077 ( .A0(n6850), .A1(n7005), .B0(n6709), .Y(n6710) );
XOR2X1TS U8078 ( .A(n6710), .B(n6730), .Y(mult_x_24_n1645) );
AOI222X1TS U8079 ( .A0(n885), .A1(n879), .B0(n1083), .B1(n6830), .C0(n7003),
.C1(n927), .Y(n6711) );
OAI21X1TS U8080 ( .A0(n6832), .A1(n7005), .B0(n6711), .Y(n6712) );
AOI222X1TS U8081 ( .A0(n885), .A1(n927), .B0(n6916), .B1(n6790), .C0(n6914),
.C1(n6894), .Y(n6713) );
OAI21X1TS U8082 ( .A0(n6793), .A1(n6932), .B0(n6713), .Y(n6714) );
XOR2X1TS U8083 ( .A(n6714), .B(n8391), .Y(mult_x_24_n1648) );
AOI222X1TS U8084 ( .A0(n884), .A1(n938), .B0(n6916), .B1(n7071), .C0(n6893),
.C1(n6569), .Y(n6715) );
XOR2X1TS U8085 ( .A(n6716), .B(n8445), .Y(mult_x_24_n1651) );
OAI21X1TS U8086 ( .A0(n7075), .A1(n6932), .B0(n6717), .Y(n6718) );
XOR2X1TS U8087 ( .A(n6718), .B(n6730), .Y(mult_x_24_n1652) );
XOR2X1TS U8088 ( .A(n6720), .B(n8445), .Y(mult_x_24_n1653) );
XOR2X1TS U8089 ( .A(n6722), .B(n6730), .Y(mult_x_24_n1654) );
AOI222X1TS U8090 ( .A0(n1047), .A1(n6853), .B0(n6727), .B1(n7082), .C0(n6914), .C1(n841), .Y(n6723) );
XOR2X1TS U8091 ( .A(n6724), .B(n8445), .Y(mult_x_24_n1655) );
AOI222X1TS U8092 ( .A0(n1047), .A1(n6904), .B0(n6727), .B1(n842), .C0(n6914),
.C1(n7035), .Y(n6725) );
XOR2X1TS U8093 ( .A(n6726), .B(n6730), .Y(mult_x_24_n1656) );
XOR2X1TS U8094 ( .A(n6731), .B(n6730), .Y(mult_x_24_n1657) );
NAND2X1TS U8095 ( .A(n6733), .B(n6732), .Y(n6734) );
AOI222X1TS U8096 ( .A0(n6736), .A1(n7009), .B0(n6760), .B1(n6574), .C0(n844),
.C1(n910), .Y(n6737) );
OAI21X1TS U8097 ( .A0(n6775), .A1(n6763), .B0(n6737), .Y(n6738) );
AOI222X1TS U8098 ( .A0(n7060), .A1(n6915), .B0(n7058), .B1(n939), .C0(n7057),
.C1(n6785), .Y(n6739) );
XOR2X1TS U8099 ( .A(n6740), .B(n6882), .Y(mult_x_24_n1410) );
AOI222X1TS U8100 ( .A0(n7011), .A1(n6928), .B0(n6834), .B1(n6915), .C0(n6867), .C1(n6945), .Y(n6741) );
OAI21X1TS U8101 ( .A0(n6775), .A1(n6809), .B0(n6743), .Y(n6744) );
AOI222X1TS U8102 ( .A0(n6839), .A1(n6963), .B0(n6995), .B1(n6961), .C0(n6997), .C1(n6756), .Y(n6745) );
AOI222X1TS U8103 ( .A0(n6964), .A1(Op_MX[19]), .B0(n6962), .B1(n6929), .C0(
n6960), .C1(n6559), .Y(n6747) );
XOR2X1TS U8104 ( .A(n6748), .B(n6968), .Y(mult_x_24_n1497) );
AOI222X1TS U8105 ( .A0(n6750), .A1(n6847), .B0(n6887), .B1(n6846), .C0(n6990), .C1(n6749), .Y(n6751) );
OAI21X1TS U8106 ( .A0(n6850), .A1(n6973), .B0(n6751), .Y(n6752) );
AOI222X1TS U8107 ( .A0(n7083), .A1(n6574), .B0(n7081), .B1(n6753), .C0(n7080), .C1(n6958), .Y(n6754) );
XOR2X1TS U8108 ( .A(n6755), .B(n6882), .Y(mult_x_24_n1415) );
AOI222X1TS U8109 ( .A0(n6889), .A1(n6963), .B0(n6970), .B1(n6961), .C0(n6990), .C1(n6756), .Y(n6757) );
AOI222X1TS U8110 ( .A0(n6761), .A1(n6910), .B0(n6760), .B1(n7033), .C0(n844),
.C1(n8414), .Y(n6762) );
XOR2X1TS U8111 ( .A(n6764), .B(n836), .Y(mult_x_24_n1448) );
OAI21X1TS U8112 ( .A0(n729), .A1(n6992), .B0(n6765), .Y(n6766) );
XOR2X1TS U8113 ( .A(n6766), .B(n6891), .Y(mult_x_24_n1590) );
AOI222X1TS U8114 ( .A0(n6848), .A1(Op_MX[25]), .B0(n6995), .B1(n6767), .C0(
n6997), .C1(n833), .Y(n6768) );
OAI21X1TS U8115 ( .A0(n6850), .A1(n6984), .B0(n6772), .Y(n6773) );
OAI21X1TS U8116 ( .A0(n6775), .A1(n7049), .B0(n6774), .Y(n6776) );
XOR2X1TS U8117 ( .A(n6776), .B(n8373), .Y(mult_x_24_n1564) );
AOI222X1TS U8118 ( .A0(n6796), .A1(n834), .B0(n6962), .B1(n6922), .C0(n6960),
.C1(n6952), .Y(n6777) );
XOR2X1TS U8119 ( .A(n6779), .B(n6968), .Y(mult_x_24_n1493) );
AOI222X1TS U8120 ( .A0(n7083), .A1(n6910), .B0(n7081), .B1(n6780), .C0(n7080), .C1(n6875), .Y(n6781) );
OAI21X1TS U8121 ( .A0(n7039), .A1(n7085), .B0(n6781), .Y(n6782) );
AOI222X1TS U8122 ( .A0(n7011), .A1(n7042), .B0(n6834), .B1(n7022), .C0(n6867), .C1(n6822), .Y(n6783) );
OAI21X1TS U8123 ( .A0(n6824), .A1(n6792), .B0(n6783), .Y(n6784) );
XOR2X1TS U8124 ( .A(n6784), .B(n6220), .Y(mult_x_24_n1483) );
AOI222X1TS U8125 ( .A0(n6964), .A1(n6894), .B0(n6786), .B1(n937), .C0(n6531),
.C1(n6785), .Y(n6787) );
OAI21X1TS U8126 ( .A0(n729), .A1(n6788), .B0(n6787), .Y(n6789) );
XOR2X1TS U8127 ( .A(n6789), .B(n893), .Y(mult_x_24_n1500) );
XOR2X1TS U8128 ( .A(n6795), .B(n6794), .Y(mult_x_24_n1468) );
AOI222X1TS U8129 ( .A0(n6796), .A1(n6816), .B0(n6962), .B1(n6814), .C0(n6960), .C1(n879), .Y(n6797) );
XOR2X1TS U8130 ( .A(n6798), .B(n6968), .Y(mult_x_24_n1494) );
AOI222X1TS U8131 ( .A0(n6807), .A1(n7035), .B0(n6806), .B1(n7033), .C0(n6805), .C1(n6875), .Y(n6799) );
AOI222X1TS U8132 ( .A0(n7060), .A1(n6886), .B0(n7058), .B1(n8402), .C0(n7057), .C1(n6822), .Y(n6801) );
OAI21X1TS U8133 ( .A0(n6824), .A1(n7062), .B0(n6801), .Y(n6802) );
XOR2X1TS U8134 ( .A(n6802), .B(n7064), .Y(mult_x_24_n1423) );
NAND2X1TS U8135 ( .A(n7003), .B(n7001), .Y(n6803) );
OAI21X1TS U8136 ( .A0(n6993), .A1(n6932), .B0(n6803), .Y(n6804) );
XOR2X1TS U8137 ( .A(n6804), .B(n6934), .Y(mult_x_24_n1638) );
AOI222X1TS U8138 ( .A0(n6807), .A1(n6853), .B0(n6806), .B1(n7082), .C0(n6805), .C1(n6958), .Y(n6808) );
OAI21X1TS U8139 ( .A0(n6855), .A1(n6809), .B0(n6808), .Y(n6810) );
XOR2X1TS U8140 ( .A(n6810), .B(n835), .Y(mult_x_24_n1505) );
AOI222X1TS U8141 ( .A0(n7023), .A1(n6886), .B0(n7021), .B1(n8402), .C0(n7019), .C1(n7020), .Y(n6811) );
OAI21X1TS U8142 ( .A0(n6824), .A1(n7025), .B0(n6811), .Y(n6812) );
XOR2X1TS U8143 ( .A(n6812), .B(n7027), .Y(mult_x_24_n1543) );
AOI222X1TS U8144 ( .A0(n6817), .A1(n6816), .B0(n887), .B1(n6814), .C0(n6813),
.C1(n877), .Y(n6818) );
OAI21X1TS U8145 ( .A0(n6926), .A1(n6819), .B0(n6818), .Y(n6821) );
AOI222X1TS U8146 ( .A0(n6889), .A1(n7042), .B0(n6887), .B1(n7022), .C0(n6885), .C1(n6822), .Y(n6823) );
OAI21X1TS U8147 ( .A0(n6824), .A1(n6992), .B0(n6823), .Y(n6825) );
XOR2X1TS U8148 ( .A(n6825), .B(n6891), .Y(mult_x_24_n1603) );
AOI222X1TS U8149 ( .A0(n7023), .A1(n6830), .B0(n6980), .B1(n8403), .C0(n6982), .C1(n6559), .Y(n6826) );
OAI21X1TS U8150 ( .A0(n6933), .A1(n7025), .B0(n6826), .Y(n6828) );
XOR2X1TS U8151 ( .A(n6828), .B(n6827), .Y(mult_x_24_n1527) );
AOI222X1TS U8152 ( .A0(n6848), .A1(n878), .B0(n6995), .B1(n6830), .C0(n6997),
.C1(n8403), .Y(n6831) );
OAI21X1TS U8153 ( .A0(n6832), .A1(n6999), .B0(n6831), .Y(n6833) );
XOR2X1TS U8154 ( .A(n6833), .B(n6851), .Y(mult_x_24_n1556) );
AOI222X1TS U8155 ( .A0(n7011), .A1(n6888), .B0(n6834), .B1(n6886), .C0(n6867), .C1(n6897), .Y(n6835) );
OAI21X1TS U8156 ( .A0(n6900), .A1(n6872), .B0(n6835), .Y(n6836) );
XOR2X1TS U8157 ( .A(n6836), .B(n6220), .Y(mult_x_24_n1482) );
AOI222X1TS U8158 ( .A0(n6905), .A1(n7035), .B0(n6903), .B1(n7033), .C0(n6902), .C1(n7031), .Y(n6837) );
OAI21X1TS U8159 ( .A0(n6933), .A1(n6841), .B0(n6840), .Y(n6842) );
XOR2X1TS U8160 ( .A(n6842), .B(n6851), .Y(mult_x_24_n1557) );
AOI222X1TS U8161 ( .A0(n7047), .A1(n6853), .B0(n6843), .B1(n7082), .C0(n7043), .C1(n842), .Y(n6844) );
OAI21X1TS U8162 ( .A0(n6855), .A1(n7049), .B0(n6844), .Y(n6845) );
XOR2X1TS U8163 ( .A(n6845), .B(n8373), .Y(mult_x_24_n1565) );
OAI21X1TS U8164 ( .A0(n6850), .A1(n6999), .B0(n6849), .Y(n6852) );
XOR2X1TS U8165 ( .A(n6852), .B(n6851), .Y(mult_x_24_n1555) );
AOI222X1TS U8166 ( .A0(n6905), .A1(n6853), .B0(n6903), .B1(n7082), .C0(n6902), .C1(n841), .Y(n6854) );
AOI222X1TS U8167 ( .A0(n7036), .A1(n7031), .B0(n7034), .B1(n6859), .C0(n6885), .C1(n6888), .Y(n6857) );
XOR2X1TS U8168 ( .A(n6858), .B(n6891), .Y(mult_x_24_n1600) );
AOI222X1TS U8169 ( .A0(n6870), .A1(n7031), .B0(n6869), .B1(n6859), .C0(n6867), .C1(n6863), .Y(n6860) );
OAI21X1TS U8170 ( .A0(n6865), .A1(n6872), .B0(n6860), .Y(n6862) );
XOR2X1TS U8171 ( .A(n6862), .B(n6794), .Y(mult_x_24_n1480) );
AOI222X1TS U8172 ( .A0(n6877), .A1(n6868), .B0(n6876), .B1(Op_MX[5]), .C0(
n7019), .C1(n6863), .Y(n6864) );
OAI21X1TS U8173 ( .A0(n6865), .A1(n6899), .B0(n6864), .Y(n6866) );
XOR2X1TS U8174 ( .A(n6866), .B(n7027), .Y(mult_x_24_n1540) );
AOI222X1TS U8175 ( .A0(n6870), .A1(n6909), .B0(n6869), .B1(n6868), .C0(n6867), .C1(n6874), .Y(n6871) );
XOR2X1TS U8176 ( .A(n6873), .B(n7494), .Y(mult_x_24_n1479) );
AOI222X1TS U8177 ( .A0(n6877), .A1(n7033), .B0(n6876), .B1(n6875), .C0(n7019), .C1(n6874), .Y(n6878) );
OAI21X1TS U8178 ( .A0(n6900), .A1(n7085), .B0(n6881), .Y(n6883) );
XOR2X1TS U8179 ( .A(n6883), .B(n6882), .Y(mult_x_24_n1422) );
AOI222X1TS U8180 ( .A0(n6889), .A1(n6888), .B0(n6887), .B1(n6886), .C0(n6885), .C1(n6884), .Y(n6890) );
OAI21X1TS U8181 ( .A0(n6900), .A1(n7038), .B0(n6890), .Y(n6892) );
XOR2X1TS U8182 ( .A(n6892), .B(n6891), .Y(mult_x_24_n1602) );
AOI222X1TS U8183 ( .A0(n885), .A1(n6894), .B0(n6916), .B1(n937), .C0(n6893),
.C1(n8412), .Y(n6895) );
XOR2X1TS U8184 ( .A(n6896), .B(n8445), .Y(mult_x_24_n1650) );
OAI21X1TS U8185 ( .A0(n6900), .A1(n6899), .B0(n6898), .Y(n6901) );
XOR2X1TS U8186 ( .A(n6901), .B(n7027), .Y(mult_x_24_n1542) );
AOI222X1TS U8187 ( .A0(n6905), .A1(n6904), .B0(n6903), .B1(n842), .C0(n6902),
.C1(n7035), .Y(n6906) );
XOR2X1TS U8188 ( .A(n6908), .B(n6820), .Y(mult_x_24_n1626) );
AOI222X1TS U8189 ( .A0(n7036), .A1(n841), .B0(n7034), .B1(n6910), .C0(n7032),
.C1(n6909), .Y(n6911) );
OAI21X1TS U8190 ( .A0(n6912), .A1(n7038), .B0(n6911), .Y(n6913) );
XOR2X1TS U8191 ( .A(n6913), .B(n7040), .Y(mult_x_24_n1597) );
AOI222X1TS U8192 ( .A0(n884), .A1(n6928), .B0(n6916), .B1(n6915), .C0(n6914),
.C1(n939), .Y(n6917) );
XOR2X1TS U8193 ( .A(n6919), .B(n8391), .Y(mult_x_24_n1649) );
OAI21X1TS U8194 ( .A0(n6926), .A1(n6925), .B0(n6924), .Y(n6927) );
XOR2X1TS U8195 ( .A(n6927), .B(n7087), .Y(mult_x_24_n1404) );
OAI21X1TS U8196 ( .A0(n6933), .A1(n6932), .B0(n6931), .Y(n6935) );
XOR2X1TS U8197 ( .A(n6935), .B(n8391), .Y(mult_x_24_n1647) );
CMPR32X2TS U8198 ( .A(n6974), .B(n6937), .C(n6936), .CO(mult_x_24_n805), .S(
mult_x_24_n806) );
ADDHX1TS U8199 ( .A(n6939), .B(n6938), .CO(mult_x_24_n914), .S(n4759) );
ADDHX1TS U8200 ( .A(n8373), .B(n6941), .CO(n5032), .S(mult_x_24_n1064) );
ADDHX1TS U8201 ( .A(n7076), .B(n6942), .CO(n5207), .S(mult_x_24_n974) );
INVX2TS U8202 ( .A(mult_x_24_n1094), .Y(mult_x_24_n740) );
INVX2TS U8203 ( .A(n6947), .Y(n6949) );
NAND2X1TS U8204 ( .A(n6949), .B(n6948), .Y(n6950) );
INVX2TS U8205 ( .A(mult_x_24_n1088), .Y(mult_x_24_n703) );
INVX2TS U8206 ( .A(n6953), .Y(n6955) );
NAND2X1TS U8207 ( .A(n6955), .B(n6954), .Y(n6956) );
INVX2TS U8208 ( .A(mult_x_24_n1100), .Y(mult_x_24_n795) );
AOI222X1TS U8209 ( .A0(n6964), .A1(n6963), .B0(n6962), .B1(n6961), .C0(n6960), .C1(n6959), .Y(n6965) );
OAI21X1TS U8210 ( .A0(n6967), .A1(n6966), .B0(n6965), .Y(n6969) );
AOI21X1TS U8211 ( .A0(n6990), .A1(n926), .B0(n6971), .Y(n6972) );
XOR2X1TS U8212 ( .A(n6975), .B(n8378), .Y(mult_x_24_n1579) );
INVX2TS U8213 ( .A(n7097), .Y(n6977) );
AND2X2TS U8214 ( .A(n6980), .B(n7001), .Y(n6981) );
AOI21X1TS U8215 ( .A0(n6982), .A1(n925), .B0(n6981), .Y(n6983) );
OAI21X2TS U8216 ( .A0(n7006), .A1(n6984), .B0(n6983), .Y(n6985) );
XOR2X1TS U8217 ( .A(n6985), .B(Op_MY[14]), .Y(mult_x_24_n1519) );
ADDFHX1TS U8218 ( .A(n6988), .B(n6987), .CI(n6986), .CO(n5053), .S(
mult_x_24_n1047) );
NAND2X1TS U8219 ( .A(n6990), .B(n6989), .Y(n6991) );
OAI21X1TS U8220 ( .A0(n6993), .A1(n6992), .B0(n6991), .Y(n6994) );
AOI21X1TS U8221 ( .A0(n6997), .A1(Op_MX[25]), .B0(n6996), .Y(n6998) );
AOI21X1TS U8222 ( .A0(n7003), .A1(Op_MX[25]), .B0(n7002), .Y(n7004) );
OAI21X1TS U8223 ( .A0(n7006), .A1(n7005), .B0(n7004), .Y(n7007) );
XOR2X1TS U8224 ( .A(n7007), .B(n8391), .Y(mult_x_24_n1639) );
AOI222X1TS U8225 ( .A0(n7011), .A1(n6569), .B0(n7010), .B1(n7009), .C0(n5076), .C1(n827), .Y(n7012) );
XOR2X2TS U8226 ( .A(n7015), .B(n7494), .Y(mult_x_24_n1473) );
AOI222X1TS U8227 ( .A0(n7023), .A1(n7022), .B0(n7021), .B1(n7020), .C0(n7019), .C1(n7018), .Y(n7024) );
OAI21X1TS U8228 ( .A0(n7026), .A1(n7025), .B0(n7024), .Y(n7028) );
XOR2X1TS U8229 ( .A(n7028), .B(n7027), .Y(n7029) );
CMPR22X2TS U8230 ( .A(n7030), .B(n7029), .CO(mult_x_24_n1034), .S(n7055) );
AOI222X1TS U8231 ( .A0(n7036), .A1(n7035), .B0(n7034), .B1(n7033), .C0(n7032), .C1(n7031), .Y(n7037) );
OAI21X1TS U8232 ( .A0(n7039), .A1(n7038), .B0(n7037), .Y(n7041) );
XOR2X1TS U8233 ( .A(n7041), .B(n7040), .Y(n7054) );
OAI21X1TS U8234 ( .A0(n7050), .A1(n7049), .B0(n7048), .Y(n7052) );
XOR2X1TS U8235 ( .A(n7052), .B(n7051), .Y(n7053) );
OAI21X1TS U8236 ( .A0(n7075), .A1(n7074), .B0(n7073), .Y(n7077) );
XOR2X1TS U8237 ( .A(n7088), .B(n7087), .Y(n7089) );
ADDFHX1TS U8238 ( .A(n7091), .B(n7090), .CI(n7089), .CO(mult_x_24_n816), .S(
mult_x_24_n817) );
ADDHX1TS U8239 ( .A(n7093), .B(n7092), .CO(n5135), .S(mult_x_24_n1012) );
INVX2TS U8240 ( .A(n7094), .Y(n7095) );
INVX2TS U8241 ( .A(n6976), .Y(n7098) );
OAI21X1TS U8242 ( .A0(n7098), .A1(n7097), .B0(n7096), .Y(n7099) );
INVX2TS U8243 ( .A(n7101), .Y(n7103) );
NAND2X1TS U8244 ( .A(n7110), .B(n7109), .Y(n7111) );
NOR3BX1TS U8245 ( .AN(Op_MY[62]), .B(FSM_selector_B[1]), .C(
FSM_selector_B[0]), .Y(n7113) );
XOR2X1TS U8246 ( .A(n904), .B(n7113), .Y(DP_OP_36J42_124_1029_n18) );
OAI2BB1X1TS U8247 ( .A0N(Op_MY[61]), .A1N(n8536), .B0(n1037), .Y(n7114) );
XOR2X1TS U8248 ( .A(n8366), .B(n7114), .Y(DP_OP_36J42_124_1029_n19) );
OAI2BB1X1TS U8249 ( .A0N(Op_MY[60]), .A1N(n8536), .B0(n1037), .Y(n7115) );
XOR2X1TS U8250 ( .A(n904), .B(n7115), .Y(DP_OP_36J42_124_1029_n20) );
OAI2BB1X1TS U8251 ( .A0N(Op_MY[59]), .A1N(n8536), .B0(n1037), .Y(n7116) );
XOR2X1TS U8252 ( .A(n8366), .B(n7116), .Y(DP_OP_36J42_124_1029_n21) );
OAI2BB1X1TS U8253 ( .A0N(Op_MY[58]), .A1N(n8536), .B0(n1037), .Y(n7117) );
XOR2X1TS U8254 ( .A(n904), .B(n7117), .Y(DP_OP_36J42_124_1029_n22) );
OAI2BB1X1TS U8255 ( .A0N(Op_MY[57]), .A1N(n8536), .B0(n1037), .Y(n7118) );
XOR2X1TS U8256 ( .A(n8366), .B(n7118), .Y(DP_OP_36J42_124_1029_n23) );
OAI2BB1X1TS U8257 ( .A0N(Op_MY[56]), .A1N(n8536), .B0(n1037), .Y(n7119) );
XOR2X1TS U8258 ( .A(n904), .B(n7119), .Y(DP_OP_36J42_124_1029_n24) );
OAI2BB1X1TS U8259 ( .A0N(Op_MY[55]), .A1N(n8536), .B0(n1037), .Y(n7120) );
XOR2X1TS U8260 ( .A(n8366), .B(n7120), .Y(DP_OP_36J42_124_1029_n25) );
OAI2BB1X1TS U8261 ( .A0N(Op_MY[54]), .A1N(n8536), .B0(n1037), .Y(n7121) );
XOR2X1TS U8262 ( .A(n904), .B(n7121), .Y(DP_OP_36J42_124_1029_n26) );
OAI2BB1X1TS U8263 ( .A0N(Op_MY[53]), .A1N(n8536), .B0(n1037), .Y(n7122) );
XOR2X1TS U8264 ( .A(n8366), .B(n7122), .Y(DP_OP_36J42_124_1029_n27) );
INVX2TS U8265 ( .A(n7368), .Y(n7125) );
NAND2X1TS U8266 ( .A(n7125), .B(n7124), .Y(n7126) );
INVX2TS U8267 ( .A(n7128), .Y(n7268) );
NAND2X1TS U8268 ( .A(n7268), .B(n7129), .Y(n7130) );
XNOR2X1TS U8269 ( .A(n7436), .B(n7130), .Y(Sgf_operation_ODD1_middle_N24) );
INVX2TS U8270 ( .A(n7142), .Y(n7132) );
NAND2X1TS U8271 ( .A(n7132), .B(n7143), .Y(n7137) );
AOI21X1TS U8272 ( .A0(n7135), .A1(n7143), .B0(n7134), .Y(n7136) );
NAND2X1TS U8273 ( .A(n7139), .B(n7138), .Y(n7140) );
XNOR2X1TS U8274 ( .A(n7141), .B(n7140), .Y(Sgf_operation_ODD1_middle_N23) );
NAND2X1TS U8275 ( .A(n7144), .B(n7143), .Y(n7145) );
XNOR2X1TS U8276 ( .A(n7146), .B(n7145), .Y(Sgf_operation_ODD1_middle_N22) );
XNOR2X1TS U8277 ( .A(n7150), .B(n7149), .Y(Sgf_operation_ODD1_middle_N21) );
NAND2X1TS U8278 ( .A(n7152), .B(n7151), .Y(n7153) );
INVX2TS U8279 ( .A(n7157), .Y(n7387) );
NAND2X1TS U8280 ( .A(n7387), .B(n7385), .Y(n7158) );
XNOR2X1TS U8281 ( .A(n7156), .B(n7158), .Y(Sgf_operation_ODD1_middle_N16) );
INVX2TS U8282 ( .A(n7163), .Y(n7165) );
NAND2X1TS U8283 ( .A(n7165), .B(n7164), .Y(n7166) );
XNOR2X1TS U8284 ( .A(n7167), .B(n7166), .Y(Sgf_operation_ODD1_middle_N15) );
NAND2X1TS U8285 ( .A(n7170), .B(n7169), .Y(n7171) );
XNOR2X1TS U8286 ( .A(n7172), .B(n7171), .Y(Sgf_operation_ODD1_middle_N14) );
NAND2X1TS U8287 ( .A(n7174), .B(n7173), .Y(n7175) );
INVX2TS U8288 ( .A(n7176), .Y(n7183) );
AOI21X1TS U8289 ( .A0(n7183), .A1(n734), .B0(n7177), .Y(n7180) );
NAND2X1TS U8290 ( .A(n789), .B(n7178), .Y(n7179) );
NAND2X1TS U8291 ( .A(n7181), .B(n734), .Y(n7182) );
XNOR2X1TS U8292 ( .A(n7183), .B(n7182), .Y(Sgf_operation_ODD1_middle_N11) );
INVX2TS U8293 ( .A(n7184), .Y(n7230) );
INVX2TS U8294 ( .A(n7185), .Y(n7187) );
NAND2X1TS U8295 ( .A(n7187), .B(n7186), .Y(n7188) );
XNOR2X1TS U8296 ( .A(n7189), .B(n7188), .Y(Sgf_operation_ODD1_middle_N10) );
INVX2TS U8297 ( .A(n7190), .Y(n7199) );
INVX2TS U8298 ( .A(n7196), .Y(n7191) );
AOI21X1TS U8299 ( .A0(n7199), .A1(n7197), .B0(n7191), .Y(n7195) );
NAND2X1TS U8300 ( .A(n7193), .B(n7192), .Y(n7194) );
NAND2X1TS U8301 ( .A(n7197), .B(n7196), .Y(n7198) );
XNOR2X1TS U8302 ( .A(n7199), .B(n7198), .Y(Sgf_operation_ODD1_middle_N7) );
NAND2X1TS U8303 ( .A(n7201), .B(n7200), .Y(n7203) );
XNOR2X1TS U8304 ( .A(n7203), .B(n7202), .Y(Sgf_operation_ODD1_middle_N6) );
INVX2TS U8305 ( .A(n7204), .Y(n7206) );
NAND2X1TS U8306 ( .A(n7206), .B(n7205), .Y(n7208) );
NAND2X1TS U8307 ( .A(n7210), .B(n7209), .Y(n7212) );
XNOR2X1TS U8308 ( .A(n7212), .B(n7211), .Y(Sgf_operation_ODD1_middle_N4) );
INVX2TS U8309 ( .A(n7213), .Y(n7215) );
NAND2X1TS U8310 ( .A(n7215), .B(n7214), .Y(n7216) );
NAND2X1TS U8311 ( .A(n7219), .B(n7218), .Y(n7221) );
XNOR2X1TS U8312 ( .A(n7221), .B(n7220), .Y(Sgf_operation_ODD1_middle_N2) );
INVX2TS U8313 ( .A(n7226), .Y(n7228) );
NAND2X1TS U8314 ( .A(n7228), .B(n7227), .Y(n7229) );
NOR2BX1TS U8315 ( .AN(n929), .B(n7231), .Y(Sgf_operation_ODD1_middle_N0) );
INVX2TS U8316 ( .A(n7396), .Y(n7234) );
INVX2TS U8317 ( .A(n7239), .Y(n7241) );
AOI21X2TS U8318 ( .A0(n7360), .A1(n7352), .B0(n7245), .Y(n7246) );
BUFX3TS U8319 ( .A(n7248), .Y(n7356) );
INVX2TS U8320 ( .A(n7356), .Y(n7249) );
INVX2TS U8321 ( .A(n7373), .Y(n7253) );
INVX2TS U8322 ( .A(n7251), .Y(n7252) );
INVX2TS U8323 ( .A(n7435), .Y(n7257) );
INVX2TS U8324 ( .A(n7258), .Y(n7259) );
OAI21X1TS U8325 ( .A0(n7259), .A1(n7437), .B0(n7438), .Y(n7260) );
INVX2TS U8326 ( .A(n7262), .Y(n7264) );
INVX2TS U8327 ( .A(n7129), .Y(n7267) );
INVX2TS U8328 ( .A(n7269), .Y(n7271) );
XNOR2X4TS U8329 ( .A(n7277), .B(n7276), .Y(Sgf_operation_ODD1_middle_N45) );
INVX2TS U8330 ( .A(n7288), .Y(n7279) );
AOI21X2TS U8331 ( .A0(n7360), .A1(n7289), .B0(n7279), .Y(n7280) );
INVX2TS U8332 ( .A(n7282), .Y(n7284) );
NAND2X2TS U8333 ( .A(n7323), .B(n7297), .Y(n7299) );
OAI21X2TS U8334 ( .A0(n7295), .A1(n7294), .B0(n7293), .Y(n7296) );
INVX2TS U8335 ( .A(n7300), .Y(n7302) );
NAND2X2TS U8336 ( .A(n7323), .B(n7308), .Y(n7310) );
INVX2TS U8337 ( .A(n7306), .Y(n7307) );
NAND2X1TS U8338 ( .A(n7312), .B(n7311), .Y(n7313) );
XNOR2X4TS U8339 ( .A(n7314), .B(n7313), .Y(Sgf_operation_ODD1_middle_N52) );
INVX2TS U8340 ( .A(n7315), .Y(n7318) );
INVX2TS U8341 ( .A(n7316), .Y(n7317) );
INVX4TS U8342 ( .A(n5108), .Y(n7427) );
INVX2TS U8343 ( .A(n7345), .Y(n7415) );
INVX2TS U8344 ( .A(n7335), .Y(n7338) );
INVX2TS U8345 ( .A(n7336), .Y(n7337) );
INVX4TS U8346 ( .A(n7343), .Y(n7416) );
INVX2TS U8347 ( .A(n7352), .Y(n7353) );
NAND2X2TS U8348 ( .A(n7359), .B(n7354), .Y(n7362) );
INVX2TS U8349 ( .A(n7245), .Y(n7357) );
INVX2TS U8350 ( .A(n7363), .Y(n7365) );
INVX2TS U8351 ( .A(n2915), .Y(n7370) );
INVX2TS U8352 ( .A(n7374), .Y(n7375) );
AOI21X1TS U8353 ( .A0(n7376), .A1(n7251), .B0(n7375), .Y(n7377) );
INVX2TS U8354 ( .A(n7380), .Y(n7382) );
INVX2TS U8355 ( .A(n7385), .Y(n7386) );
INVX2TS U8356 ( .A(n7388), .Y(n7390) );
INVX2TS U8357 ( .A(n7393), .Y(n7394) );
INVX2TS U8358 ( .A(n7233), .Y(n7397) );
INVX2TS U8359 ( .A(n7400), .Y(n7402) );
INVX2TS U8360 ( .A(n7405), .Y(n7406) );
INVX2TS U8361 ( .A(n7410), .Y(n7412) );
NAND2X2TS U8362 ( .A(n7415), .B(n1016), .Y(n7423) );
NOR2X4TS U8363 ( .A(n7416), .B(n7423), .Y(n7426) );
INVX2TS U8364 ( .A(n7419), .Y(n7420) );
AOI21X1TS U8365 ( .A0(n1016), .A1(n7421), .B0(n7420), .Y(n7422) );
INVX2TS U8366 ( .A(n7437), .Y(n7439) );
NAND3X2TS U8367 ( .A(n7485), .B(n8470), .C(n1036), .Y(n7471) );
CLKBUFX2TS U8368 ( .A(n8535), .Y(n8534) );
CLKXOR2X2TS U8369 ( .A(Op_MX[63]), .B(Op_MY[63]), .Y(n7475) );
NOR4X1TS U8370 ( .A(P_Sgf[0]), .B(P_Sgf[1]), .C(P_Sgf[2]), .D(P_Sgf[3]), .Y(
n7457) );
NOR4X1TS U8371 ( .A(P_Sgf[4]), .B(P_Sgf[5]), .C(P_Sgf[6]), .D(P_Sgf[7]), .Y(
n7456) );
NOR4X1TS U8372 ( .A(P_Sgf[51]), .B(P_Sgf[49]), .C(P_Sgf[48]), .D(P_Sgf[50]),
.Y(n7455) );
OR4X2TS U8373 ( .A(P_Sgf[47]), .B(P_Sgf[45]), .C(P_Sgf[46]), .D(P_Sgf[44]),
.Y(n7453) );
OR4X2TS U8374 ( .A(P_Sgf[41]), .B(P_Sgf[42]), .C(P_Sgf[43]), .D(P_Sgf[40]),
.Y(n7452) );
NOR4X1TS U8375 ( .A(P_Sgf[8]), .B(P_Sgf[9]), .C(P_Sgf[10]), .D(P_Sgf[11]),
.Y(n7445) );
NOR4X1TS U8376 ( .A(P_Sgf[12]), .B(P_Sgf[13]), .C(P_Sgf[14]), .D(P_Sgf[15]),
.Y(n7444) );
NOR4X1TS U8377 ( .A(P_Sgf[16]), .B(P_Sgf[17]), .C(P_Sgf[18]), .D(P_Sgf[19]),
.Y(n7443) );
NOR4X1TS U8378 ( .A(P_Sgf[20]), .B(P_Sgf[21]), .C(P_Sgf[22]), .D(P_Sgf[23]),
.Y(n7442) );
NAND4XLTS U8379 ( .A(n7445), .B(n7444), .C(n7443), .D(n7442), .Y(n7451) );
NOR4X1TS U8380 ( .A(P_Sgf[24]), .B(P_Sgf[25]), .C(P_Sgf[26]), .D(P_Sgf[27]),
.Y(n7449) );
NOR4X1TS U8381 ( .A(P_Sgf[28]), .B(P_Sgf[29]), .C(P_Sgf[30]), .D(P_Sgf[31]),
.Y(n7448) );
NOR4X1TS U8382 ( .A(P_Sgf[32]), .B(P_Sgf[33]), .C(P_Sgf[34]), .D(P_Sgf[35]),
.Y(n7447) );
NOR4X1TS U8383 ( .A(P_Sgf[36]), .B(P_Sgf[37]), .C(P_Sgf[38]), .D(P_Sgf[39]),
.Y(n7446) );
NAND4XLTS U8384 ( .A(n7449), .B(n7448), .C(n7447), .D(n7446), .Y(n7450) );
NOR4X1TS U8385 ( .A(n7453), .B(n7452), .C(n7451), .D(n7450), .Y(n7454) );
MXI2X1TS U8386 ( .A(n7475), .B(round_mode[1]), .S0(round_mode[0]), .Y(n7458)
);
OAI211X1TS U8387 ( .A0(n7475), .A1(round_mode[1]), .B0(n7459), .C0(n7458),
.Y(n7484) );
INVX2TS U8388 ( .A(rst), .Y(n7460) );
BUFX3TS U8389 ( .A(n7460), .Y(n8495) );
CLKBUFX2TS U8390 ( .A(n7460), .Y(n7464) );
BUFX3TS U8391 ( .A(n7464), .Y(n8494) );
BUFX3TS U8392 ( .A(n7460), .Y(n8493) );
BUFX3TS U8393 ( .A(n7460), .Y(n8492) );
BUFX3TS U8394 ( .A(n7464), .Y(n8498) );
BUFX3TS U8395 ( .A(n7460), .Y(n8499) );
BUFX3TS U8396 ( .A(n7460), .Y(n8500) );
BUFX3TS U8397 ( .A(n7464), .Y(n8501) );
CLKBUFX2TS U8398 ( .A(n7471), .Y(n7461) );
BUFX3TS U8399 ( .A(n7461), .Y(n8512) );
BUFX3TS U8400 ( .A(n7465), .Y(n8513) );
BUFX3TS U8401 ( .A(n8505), .Y(n8514) );
BUFX3TS U8402 ( .A(n8506), .Y(n8509) );
BUFX3TS U8403 ( .A(n8505), .Y(n8508) );
BUFX3TS U8404 ( .A(n7462), .Y(n8510) );
CLKBUFX2TS U8405 ( .A(n7471), .Y(n7463) );
BUFX3TS U8406 ( .A(n7461), .Y(n8515) );
BUFX3TS U8407 ( .A(n7465), .Y(n8516) );
BUFX3TS U8408 ( .A(n8506), .Y(n8517) );
BUFX3TS U8409 ( .A(n7463), .Y(n8511) );
CLKBUFX2TS U8410 ( .A(n7471), .Y(n7462) );
BUFX3TS U8411 ( .A(n8505), .Y(n8507) );
CLKBUFX2TS U8412 ( .A(n7471), .Y(n7465) );
BUFX3TS U8413 ( .A(n7463), .Y(n8504) );
BUFX3TS U8414 ( .A(n7464), .Y(n8496) );
BUFX3TS U8415 ( .A(n7461), .Y(n8527) );
BUFX3TS U8416 ( .A(n8506), .Y(n8525) );
BUFX3TS U8417 ( .A(n7462), .Y(n8524) );
BUFX3TS U8418 ( .A(n7463), .Y(n8523) );
BUFX3TS U8419 ( .A(n7461), .Y(n8522) );
BUFX3TS U8420 ( .A(n7465), .Y(n8521) );
BUFX3TS U8421 ( .A(n7462), .Y(n8520) );
BUFX3TS U8422 ( .A(n7463), .Y(n8519) );
BUFX3TS U8423 ( .A(n8505), .Y(n8526) );
BUFX3TS U8424 ( .A(n7461), .Y(n8503) );
BUFX3TS U8425 ( .A(n7465), .Y(n8518) );
BUFX3TS U8426 ( .A(n7464), .Y(n8502) );
BUFX3TS U8427 ( .A(n7464), .Y(n8497) );
BUFX3TS U8428 ( .A(n7465), .Y(n8528) );
BUFX3TS U8429 ( .A(n8505), .Y(n8529) );
BUFX3TS U8430 ( .A(n8506), .Y(n8532) );
BUFX3TS U8431 ( .A(n7462), .Y(n8530) );
BUFX3TS U8432 ( .A(n7463), .Y(n8531) );
NOR2XLTS U8433 ( .A(n8446), .B(FS_Module_state_reg[3]), .Y(n7467) );
NOR2XLTS U8434 ( .A(n8447), .B(n7535), .Y(n7466) );
NAND2X1TS U8435 ( .A(n7467), .B(n7466), .Y(n8368) );
INVX2TS U8436 ( .A(n8430), .Y(n8427) );
NAND2X1TS U8437 ( .A(n8427), .B(n7666), .Y(n7468) );
BUFX3TS U8438 ( .A(n8443), .Y(n8441) );
OA22X1TS U8439 ( .A0(n8441), .A1(final_result_ieee[57]), .B0(
exp_oper_result[5]), .B1(n8442), .Y(n294) );
OA22X1TS U8440 ( .A0(n8441), .A1(final_result_ieee[60]), .B0(
exp_oper_result[8]), .B1(n8442), .Y(n291) );
OA22X1TS U8441 ( .A0(n8441), .A1(final_result_ieee[59]), .B0(
exp_oper_result[7]), .B1(n8442), .Y(n292) );
OA22X1TS U8442 ( .A0(n8441), .A1(final_result_ieee[58]), .B0(
exp_oper_result[6]), .B1(n8442), .Y(n293) );
OA22X1TS U8443 ( .A0(n8441), .A1(final_result_ieee[53]), .B0(
exp_oper_result[1]), .B1(n8442), .Y(n298) );
BUFX3TS U8444 ( .A(n8534), .Y(n8533) );
BUFX3TS U8445 ( .A(n7471), .Y(n8505) );
BUFX3TS U8446 ( .A(n7471), .Y(n8506) );
NAND2X1TS U8447 ( .A(n8030), .B(Add_result[2]), .Y(n7474) );
NOR2X1TS U8448 ( .A(n8470), .B(n8447), .Y(n7488) );
NAND3X1TS U8449 ( .A(n7488), .B(n8446), .C(n1036), .Y(n7478) );
INVX2TS U8450 ( .A(n7478), .Y(ready) );
NOR2XLTS U8451 ( .A(n7475), .B(underflow_flag), .Y(n7476) );
OAI32X1TS U8452 ( .A0(n8434), .A1(n7476), .A2(overflow_flag), .B0(n8441),
.B1(n8490), .Y(n287) );
INVX2TS U8453 ( .A(zero_flag), .Y(n8428) );
AOI211X1TS U8454 ( .A0(n8366), .A1(n8428), .B0(n7485), .C0(n7477), .Y(n7479)
);
AOI32X1TS U8455 ( .A0(FS_Module_state_reg[3]), .A1(n7485), .A2(n7484), .B0(
n7535), .B1(n7485), .Y(n7487) );
CLKMX2X2TS U8456 ( .A(P_Sgf[104]), .B(n7513), .S0(n8354), .Y(n520) );
NAND2X1TS U8457 ( .A(Sgf_normalized_result[34]), .B(
Sgf_normalized_result[35]), .Y(n7679) );
NAND2X1TS U8458 ( .A(Sgf_normalized_result[36]), .B(
Sgf_normalized_result[37]), .Y(n7514) );
NOR2X1TS U8459 ( .A(n7679), .B(n7514), .Y(n7664) );
NAND2X1TS U8460 ( .A(n7664), .B(n7515), .Y(n7652) );
NOR2X1TS U8461 ( .A(n7652), .B(n8452), .Y(n7641) );
NAND2X1TS U8462 ( .A(n7641), .B(Sgf_normalized_result[41]), .Y(n7531) );
NAND2X1TS U8463 ( .A(Sgf_normalized_result[18]), .B(
Sgf_normalized_result[19]), .Y(n7882) );
NAND2X1TS U8464 ( .A(Sgf_normalized_result[20]), .B(
Sgf_normalized_result[21]), .Y(n7516) );
NOR2X1TS U8465 ( .A(n7882), .B(n7516), .Y(n7824) );
NAND2X1TS U8466 ( .A(Sgf_normalized_result[22]), .B(
Sgf_normalized_result[23]), .Y(n7826) );
NAND2X1TS U8467 ( .A(Sgf_normalized_result[24]), .B(
Sgf_normalized_result[25]), .Y(n7517) );
NAND2X1TS U8468 ( .A(n7824), .B(n7518), .Y(n7718) );
NAND2X1TS U8469 ( .A(Sgf_normalized_result[26]), .B(
Sgf_normalized_result[27]), .Y(n7766) );
NAND2X1TS U8470 ( .A(Sgf_normalized_result[28]), .B(
Sgf_normalized_result[29]), .Y(n7519) );
NOR2X1TS U8471 ( .A(n7766), .B(n7519), .Y(n7719) );
NAND2X1TS U8472 ( .A(Sgf_normalized_result[30]), .B(
Sgf_normalized_result[31]), .Y(n7721) );
NAND2X1TS U8473 ( .A(Sgf_normalized_result[32]), .B(
Sgf_normalized_result[33]), .Y(n7520) );
NAND2X1TS U8474 ( .A(n7719), .B(n7521), .Y(n7522) );
NAND2X1TS U8475 ( .A(Sgf_normalized_result[10]), .B(
Sgf_normalized_result[11]), .Y(n7993) );
NAND2X1TS U8476 ( .A(Sgf_normalized_result[12]), .B(
Sgf_normalized_result[13]), .Y(n7523) );
NAND2X1TS U8477 ( .A(Sgf_normalized_result[14]), .B(
Sgf_normalized_result[15]), .Y(n7940) );
NAND2X1TS U8478 ( .A(Sgf_normalized_result[16]), .B(
Sgf_normalized_result[17]), .Y(n7524) );
NAND2X1TS U8479 ( .A(n7939), .B(n7525), .Y(n7529) );
NAND2X1TS U8480 ( .A(Sgf_normalized_result[6]), .B(Sgf_normalized_result[7]),
.Y(n8058) );
NAND2X1TS U8481 ( .A(Sgf_normalized_result[8]), .B(Sgf_normalized_result[9]),
.Y(n7526) );
MXI2X1TS U8482 ( .A(P_Sgf[104]), .B(Add_result[52]), .S0(FSM_selector_C),
.Y(n7537) );
OAI21X1TS U8483 ( .A0(n7534), .A1(n8453), .B0(n7533), .Y(n7536) );
AOI21X1TS U8484 ( .A0(n7537), .A1(n7547), .B0(n8070), .Y(n7538) );
AHHCINX2TS U8485 ( .A(Sgf_normalized_result[51]), .CIN(n7539), .S(n7540),
.CO(n8184) );
BUFX3TS U8486 ( .A(n8183), .Y(n7639) );
BUFX3TS U8487 ( .A(n8039), .Y(n7637) );
BUFX3TS U8488 ( .A(n8178), .Y(n7634) );
AOI22X1TS U8489 ( .A0(n7634), .A1(Add_result[52]), .B0(
Sgf_normalized_result[51]), .B1(n8070), .Y(n7548) );
OAI2BB1X1TS U8490 ( .A0N(P_Sgf[104]), .A1N(n8069), .B0(n7548), .Y(n7549) );
AOI21X1TS U8491 ( .A0(n7637), .A1(Add_result[51]), .B0(n7549), .Y(n7550) );
OAI2BB1X1TS U8492 ( .A0N(n7639), .A1N(P_Sgf[103]), .B0(n7550), .Y(n404) );
AHHCONX2TS U8493 ( .A(Sgf_normalized_result[50]), .CI(n7551), .CON(n7539),
.S(n7552) );
XOR2X1TS U8494 ( .A(n7554), .B(n7553), .Y(n7555) );
AOI22X1TS U8495 ( .A0(n7634), .A1(Add_result[51]), .B0(
Sgf_normalized_result[50]), .B1(n8070), .Y(n7556) );
OAI2BB1X1TS U8496 ( .A0N(P_Sgf[103]), .A1N(n8069), .B0(n7556), .Y(n7557) );
AOI21X1TS U8497 ( .A0(n7637), .A1(Add_result[50]), .B0(n7557), .Y(n7558) );
OAI2BB1X1TS U8498 ( .A0N(n7639), .A1N(P_Sgf[102]), .B0(n7558), .Y(n403) );
AHHCINX2TS U8499 ( .A(Sgf_normalized_result[49]), .CIN(n7559), .S(n7560),
.CO(n7551) );
XNOR2X1TS U8500 ( .A(n7562), .B(n7561), .Y(n7563) );
BUFX3TS U8501 ( .A(n8069), .Y(n7661) );
BUFX3TS U8502 ( .A(n8070), .Y(n7659) );
AOI22X1TS U8503 ( .A0(n7634), .A1(Add_result[50]), .B0(
Sgf_normalized_result[49]), .B1(n7659), .Y(n7564) );
OAI2BB1X1TS U8504 ( .A0N(n7661), .A1N(P_Sgf[102]), .B0(n7564), .Y(n7565) );
AOI21X1TS U8505 ( .A0(n7637), .A1(Add_result[49]), .B0(n7565), .Y(n7566) );
OAI2BB1X1TS U8506 ( .A0N(n7639), .A1N(P_Sgf[101]), .B0(n7566), .Y(n402) );
AHHCONX2TS U8507 ( .A(Sgf_normalized_result[48]), .CI(n7567), .CON(n7559),
.S(n7568) );
XOR2X1TS U8508 ( .A(n7570), .B(n7569), .Y(n7571) );
AOI22X1TS U8509 ( .A0(n7634), .A1(Add_result[49]), .B0(
Sgf_normalized_result[48]), .B1(n7659), .Y(n7572) );
OAI2BB1X1TS U8510 ( .A0N(n7661), .A1N(P_Sgf[101]), .B0(n7572), .Y(n7573) );
AOI21X1TS U8511 ( .A0(n7637), .A1(Add_result[48]), .B0(n7573), .Y(n7574) );
OAI2BB1X1TS U8512 ( .A0N(n7639), .A1N(P_Sgf[100]), .B0(n7574), .Y(n401) );
AHHCINX2TS U8513 ( .A(Sgf_normalized_result[47]), .CIN(n7575), .S(n7576),
.CO(n7567) );
INVX4TS U8514 ( .A(n7577), .Y(n7759) );
INVX2TS U8515 ( .A(n7579), .Y(n7580) );
OAI21X1TS U8516 ( .A0(n7759), .A1(n7581), .B0(n7580), .Y(n7583) );
XNOR2X1TS U8517 ( .A(n7583), .B(n7582), .Y(n7584) );
AOI22X1TS U8518 ( .A0(n7634), .A1(Add_result[48]), .B0(
Sgf_normalized_result[47]), .B1(n7659), .Y(n7585) );
OAI2BB1X1TS U8519 ( .A0N(n7661), .A1N(P_Sgf[100]), .B0(n7585), .Y(n7586) );
AOI21X1TS U8520 ( .A0(n7637), .A1(Add_result[47]), .B0(n7586), .Y(n7587) );
OAI2BB1X1TS U8521 ( .A0N(n7639), .A1N(P_Sgf[99]), .B0(n7587), .Y(n400) );
AHHCONX2TS U8522 ( .A(Sgf_normalized_result[46]), .CI(n7588), .CON(n7575),
.S(n7589) );
OAI21X1TS U8523 ( .A0(n7759), .A1(n7591), .B0(n7590), .Y(n7593) );
XNOR2X1TS U8524 ( .A(n7593), .B(n7592), .Y(n7594) );
AOI22X1TS U8525 ( .A0(n7634), .A1(Add_result[47]), .B0(
Sgf_normalized_result[46]), .B1(n7659), .Y(n7595) );
OAI2BB1X1TS U8526 ( .A0N(n7661), .A1N(P_Sgf[99]), .B0(n7595), .Y(n7596) );
AOI21X1TS U8527 ( .A0(n7637), .A1(Add_result[46]), .B0(n7596), .Y(n7597) );
OAI2BB1X1TS U8528 ( .A0N(n7639), .A1N(P_Sgf[98]), .B0(n7597), .Y(n399) );
AHHCINX2TS U8529 ( .A(Sgf_normalized_result[45]), .CIN(n7598), .S(n7599),
.CO(n7588) );
NAND2X1TS U8530 ( .A(n7733), .B(n7602), .Y(n7604) );
CLKMX2X2TS U8531 ( .A(P_Sgf[97]), .B(n7605), .S0(n8191), .Y(n518) );
AOI22X1TS U8532 ( .A0(n7634), .A1(Add_result[46]), .B0(
Sgf_normalized_result[45]), .B1(n7659), .Y(n7606) );
OAI2BB1X1TS U8533 ( .A0N(n7661), .A1N(P_Sgf[98]), .B0(n7606), .Y(n7607) );
AOI21X1TS U8534 ( .A0(n7637), .A1(Add_result[45]), .B0(n7607), .Y(n7608) );
OAI2BB1X1TS U8535 ( .A0N(n7639), .A1N(P_Sgf[97]), .B0(n7608), .Y(n398) );
AHHCONX2TS U8536 ( .A(Sgf_normalized_result[44]), .CI(n7609), .CON(n7598),
.S(n7610) );
NAND2X1TS U8537 ( .A(n7733), .B(n7611), .Y(n7613) );
CLKMX2X2TS U8538 ( .A(P_Sgf[96]), .B(n7614), .S0(n8191), .Y(n517) );
AOI22X1TS U8539 ( .A0(n7634), .A1(Add_result[45]), .B0(
Sgf_normalized_result[44]), .B1(n7659), .Y(n7615) );
OAI2BB1X1TS U8540 ( .A0N(n7661), .A1N(P_Sgf[97]), .B0(n7615), .Y(n7616) );
AOI21X1TS U8541 ( .A0(n7637), .A1(Add_result[44]), .B0(n7616), .Y(n7617) );
OAI2BB1X1TS U8542 ( .A0N(n7639), .A1N(P_Sgf[96]), .B0(n7617), .Y(n397) );
AHHCINX2TS U8543 ( .A(Sgf_normalized_result[43]), .CIN(n7618), .S(n7619),
.CO(n7609) );
NAND2X1TS U8544 ( .A(n7733), .B(n7621), .Y(n7623) );
CLKMX2X2TS U8545 ( .A(P_Sgf[95]), .B(n7624), .S0(n7712), .Y(n516) );
AOI22X1TS U8546 ( .A0(n7634), .A1(Add_result[44]), .B0(
Sgf_normalized_result[43]), .B1(n7659), .Y(n7625) );
OAI2BB1X1TS U8547 ( .A0N(n7661), .A1N(P_Sgf[96]), .B0(n7625), .Y(n7626) );
AOI21X1TS U8548 ( .A0(n7637), .A1(Add_result[43]), .B0(n7626), .Y(n7627) );
OAI2BB1X1TS U8549 ( .A0N(n7639), .A1N(P_Sgf[95]), .B0(n7627), .Y(n396) );
AHHCONX2TS U8550 ( .A(Sgf_normalized_result[42]), .CI(n7628), .CON(n7618),
.S(n7629) );
NAND2X1TS U8551 ( .A(n7733), .B(n7630), .Y(n7632) );
CLKMX2X2TS U8552 ( .A(P_Sgf[94]), .B(n7633), .S0(n7712), .Y(n515) );
AOI22X1TS U8553 ( .A0(n7634), .A1(Add_result[43]), .B0(
Sgf_normalized_result[42]), .B1(n7659), .Y(n7635) );
OAI2BB1X1TS U8554 ( .A0N(n7661), .A1N(P_Sgf[95]), .B0(n7635), .Y(n7636) );
AOI21X1TS U8555 ( .A0(n7637), .A1(Add_result[42]), .B0(n7636), .Y(n7638) );
OAI2BB1X1TS U8556 ( .A0N(n7639), .A1N(P_Sgf[94]), .B0(n7638), .Y(n395) );
INVX2TS U8557 ( .A(n7640), .Y(n7708) );
NAND2X1TS U8558 ( .A(n7708), .B(n7641), .Y(n7642) );
XOR2X1TS U8559 ( .A(n7642), .B(n8472), .Y(n7643) );
INVX2TS U8560 ( .A(n7644), .Y(n7645) );
NAND2X2TS U8561 ( .A(n7733), .B(n7645), .Y(n7657) );
NOR2X4TS U8562 ( .A(n7657), .B(n7656), .Y(n7647) );
XNOR2X4TS U8563 ( .A(n7647), .B(n7646), .Y(n7648) );
CLKMX2X2TS U8564 ( .A(P_Sgf[93]), .B(n7648), .S0(n7712), .Y(n514) );
BUFX3TS U8565 ( .A(n8183), .Y(n7740) );
BUFX3TS U8566 ( .A(n8039), .Y(n7738) );
BUFX3TS U8567 ( .A(n8178), .Y(n7735) );
AOI22X1TS U8568 ( .A0(n7735), .A1(Add_result[42]), .B0(
Sgf_normalized_result[41]), .B1(n7659), .Y(n7649) );
OAI2BB1X1TS U8569 ( .A0N(n7661), .A1N(P_Sgf[94]), .B0(n7649), .Y(n7650) );
AOI21X1TS U8570 ( .A0(n7738), .A1(Add_result[41]), .B0(n7650), .Y(n7651) );
OAI2BB1X1TS U8571 ( .A0N(n7740), .A1N(P_Sgf[93]), .B0(n7651), .Y(n394) );
NAND2X1TS U8572 ( .A(n7708), .B(n7653), .Y(n7654) );
XOR2X1TS U8573 ( .A(n7654), .B(n8452), .Y(n7655) );
CLKMX2X2TS U8574 ( .A(P_Sgf[92]), .B(n7658), .S0(n7712), .Y(n513) );
AOI22X1TS U8575 ( .A0(n7735), .A1(Add_result[41]), .B0(
Sgf_normalized_result[40]), .B1(n7659), .Y(n7660) );
OAI2BB1X1TS U8576 ( .A0N(n7661), .A1N(P_Sgf[93]), .B0(n7660), .Y(n7662) );
AOI21X1TS U8577 ( .A0(n7738), .A1(Add_result[40]), .B0(n7662), .Y(n7663) );
OAI2BB1X1TS U8578 ( .A0N(n7740), .A1N(P_Sgf[92]), .B0(n7663), .Y(n393) );
NAND2X1TS U8579 ( .A(n7708), .B(n7664), .Y(n7671) );
XNOR2X1TS U8580 ( .A(n7665), .B(n8449), .Y(n7667) );
BUFX3TS U8581 ( .A(n8069), .Y(n7763) );
BUFX3TS U8582 ( .A(n8070), .Y(n7761) );
AOI22X1TS U8583 ( .A0(n7735), .A1(Add_result[40]), .B0(
Sgf_normalized_result[39]), .B1(n7761), .Y(n7668) );
OAI2BB1X1TS U8584 ( .A0N(n7763), .A1N(P_Sgf[92]), .B0(n7668), .Y(n7669) );
AOI21X1TS U8585 ( .A0(n7738), .A1(Add_result[39]), .B0(n7669), .Y(n7670) );
OAI2BB1X1TS U8586 ( .A0N(n7740), .A1N(P_Sgf[91]), .B0(n7670), .Y(n392) );
XOR2X1TS U8587 ( .A(n7671), .B(n8451), .Y(n7672) );
AOI22X1TS U8588 ( .A0(n7735), .A1(Add_result[39]), .B0(
Sgf_normalized_result[38]), .B1(n7761), .Y(n7676) );
OAI2BB1X1TS U8589 ( .A0N(n7763), .A1N(P_Sgf[91]), .B0(n7676), .Y(n7677) );
AOI21X1TS U8590 ( .A0(n7738), .A1(Add_result[38]), .B0(n7677), .Y(n7678) );
OAI2BB1X1TS U8591 ( .A0N(n7740), .A1N(P_Sgf[90]), .B0(n7678), .Y(n391) );
INVX2TS U8592 ( .A(n7679), .Y(n7680) );
NAND2X1TS U8593 ( .A(n7708), .B(n7680), .Y(n7690) );
XNOR2X1TS U8594 ( .A(n7681), .B(n8476), .Y(n7682) );
NOR2X4TS U8595 ( .A(n7693), .B(n7692), .Y(n7684) );
CLKMX2X2TS U8596 ( .A(P_Sgf[89]), .B(n7686), .S0(n7712), .Y(n510) );
AOI22X1TS U8597 ( .A0(n7735), .A1(Add_result[38]), .B0(
Sgf_normalized_result[37]), .B1(n7761), .Y(n7687) );
OAI2BB1X1TS U8598 ( .A0N(n7763), .A1N(P_Sgf[90]), .B0(n7687), .Y(n7688) );
AOI21X1TS U8599 ( .A0(n7738), .A1(Add_result[37]), .B0(n7688), .Y(n7689) );
OAI2BB1X1TS U8600 ( .A0N(n7740), .A1N(P_Sgf[89]), .B0(n7689), .Y(n390) );
XOR2X1TS U8601 ( .A(n7690), .B(n8464), .Y(n7691) );
CLKMX2X2TS U8602 ( .A(P_Sgf[88]), .B(n7694), .S0(n7712), .Y(n509) );
AOI22X1TS U8603 ( .A0(n7735), .A1(Add_result[37]), .B0(
Sgf_normalized_result[36]), .B1(n7761), .Y(n7695) );
OAI2BB1X1TS U8604 ( .A0N(n7763), .A1N(P_Sgf[89]), .B0(n7695), .Y(n7696) );
AOI21X1TS U8605 ( .A0(n7738), .A1(Add_result[36]), .B0(n7696), .Y(n7697) );
OAI2BB1X1TS U8606 ( .A0N(n7740), .A1N(P_Sgf[88]), .B0(n7697), .Y(n389) );
NAND2X1TS U8607 ( .A(n7708), .B(Sgf_normalized_result[34]), .Y(n7698) );
XOR2X1TS U8608 ( .A(n7698), .B(n8473), .Y(n7699) );
INVX2TS U8609 ( .A(n7700), .Y(n7701) );
NOR2X4TS U8610 ( .A(n7711), .B(n7710), .Y(n7703) );
XNOR2X4TS U8611 ( .A(n7703), .B(n7702), .Y(n7704) );
CLKMX2X2TS U8612 ( .A(P_Sgf[87]), .B(n7704), .S0(n7712), .Y(n508) );
AOI22X1TS U8613 ( .A0(n7735), .A1(Add_result[36]), .B0(
Sgf_normalized_result[35]), .B1(n7761), .Y(n7705) );
OAI2BB1X1TS U8614 ( .A0N(n7763), .A1N(P_Sgf[88]), .B0(n7705), .Y(n7706) );
AOI21X1TS U8615 ( .A0(n7738), .A1(Add_result[35]), .B0(n7706), .Y(n7707) );
OAI2BB1X1TS U8616 ( .A0N(n7740), .A1N(P_Sgf[87]), .B0(n7707), .Y(n388) );
XNOR2X1TS U8617 ( .A(n7708), .B(n8454), .Y(n7709) );
CLKMX2X2TS U8618 ( .A(P_Sgf[86]), .B(n7713), .S0(n7712), .Y(n507) );
AOI22X1TS U8619 ( .A0(n7735), .A1(Add_result[35]), .B0(
Sgf_normalized_result[34]), .B1(n7761), .Y(n7714) );
OAI2BB1X1TS U8620 ( .A0N(n7763), .A1N(P_Sgf[87]), .B0(n7714), .Y(n7715) );
AOI21X1TS U8621 ( .A0(n7738), .A1(Add_result[34]), .B0(n7715), .Y(n7716) );
OAI2BB1X1TS U8622 ( .A0N(n7740), .A1N(P_Sgf[86]), .B0(n7716), .Y(n387) );
INVX2TS U8623 ( .A(n7800), .Y(n7813) );
INVX2TS U8624 ( .A(n7719), .Y(n7720) );
INVX2TS U8625 ( .A(n7741), .Y(n7753) );
NOR2X1TS U8626 ( .A(n7753), .B(n7721), .Y(n7730) );
NAND2X1TS U8627 ( .A(n7730), .B(Sgf_normalized_result[32]), .Y(n7722) );
XOR2X1TS U8628 ( .A(n7722), .B(n8474), .Y(n7723) );
NAND2X1TS U8629 ( .A(n7733), .B(Sgf_operation_ODD1_Q_left[30]), .Y(n7725) );
CLKMX2X2TS U8630 ( .A(P_Sgf[85]), .B(n7726), .S0(n7850), .Y(n506) );
AOI22X1TS U8631 ( .A0(n7735), .A1(Add_result[34]), .B0(
Sgf_normalized_result[33]), .B1(n7761), .Y(n7727) );
OAI2BB1X1TS U8632 ( .A0N(n7763), .A1N(P_Sgf[86]), .B0(n7727), .Y(n7728) );
AOI21X1TS U8633 ( .A0(n7738), .A1(Add_result[33]), .B0(n7728), .Y(n7729) );
OAI2BB1X1TS U8634 ( .A0N(n7740), .A1N(P_Sgf[85]), .B0(n7729), .Y(n386) );
XNOR2X1TS U8635 ( .A(n7730), .B(n8455), .Y(n7731) );
XNOR2X1TS U8636 ( .A(n7733), .B(n7732), .Y(n7734) );
AOI22X1TS U8637 ( .A0(n7735), .A1(Add_result[33]), .B0(
Sgf_normalized_result[32]), .B1(n7761), .Y(n7736) );
OAI2BB1X1TS U8638 ( .A0N(n7763), .A1N(P_Sgf[85]), .B0(n7736), .Y(n7737) );
AOI21X1TS U8639 ( .A0(n7738), .A1(Add_result[32]), .B0(n7737), .Y(n7739) );
OAI2BB1X1TS U8640 ( .A0N(n7740), .A1N(P_Sgf[84]), .B0(n7739), .Y(n385) );
NAND2X1TS U8641 ( .A(n7741), .B(Sgf_normalized_result[30]), .Y(n7742) );
XOR2X1TS U8642 ( .A(n7742), .B(n8475), .Y(n7743) );
OAI21X1TS U8643 ( .A0(n7759), .A1(n7755), .B0(n7756), .Y(n7748) );
NAND2X1TS U8644 ( .A(n7746), .B(n7745), .Y(n7747) );
XNOR2X1TS U8645 ( .A(n7748), .B(n7747), .Y(n7749) );
BUFX3TS U8646 ( .A(n8039), .Y(n7880) );
BUFX3TS U8647 ( .A(n8178), .Y(n7877) );
AOI22X1TS U8648 ( .A0(n7877), .A1(Add_result[32]), .B0(
Sgf_normalized_result[31]), .B1(n7761), .Y(n7750) );
OAI2BB1X1TS U8649 ( .A0N(n7763), .A1N(P_Sgf[84]), .B0(n7750), .Y(n7751) );
AOI21X1TS U8650 ( .A0(n7880), .A1(Add_result[31]), .B0(n7751), .Y(n7752) );
OAI2BB1X1TS U8651 ( .A0N(n7899), .A1N(P_Sgf[83]), .B0(n7752), .Y(n384) );
XOR2X1TS U8652 ( .A(n7753), .B(n8461), .Y(n7754) );
NAND2X1TS U8653 ( .A(n7757), .B(n7756), .Y(n7758) );
XOR2X1TS U8654 ( .A(n7759), .B(n7758), .Y(n7760) );
AOI22X1TS U8655 ( .A0(n7877), .A1(Add_result[31]), .B0(
Sgf_normalized_result[30]), .B1(n7761), .Y(n7762) );
OAI2BB1X1TS U8656 ( .A0N(n7763), .A1N(P_Sgf[83]), .B0(n7762), .Y(n7764) );
AOI21X1TS U8657 ( .A0(n7880), .A1(Add_result[30]), .B0(n7764), .Y(n7765) );
OAI2BB1X1TS U8658 ( .A0N(n7899), .A1N(P_Sgf[82]), .B0(n7765), .Y(n383) );
NOR2X1TS U8659 ( .A(n7813), .B(n7766), .Y(n7789) );
NAND2X1TS U8660 ( .A(n7789), .B(Sgf_normalized_result[28]), .Y(n7767) );
XOR2X1TS U8661 ( .A(n7767), .B(n8477), .Y(n7769) );
INVX8TS U8662 ( .A(n7770), .Y(n7987) );
INVX2TS U8663 ( .A(n7771), .Y(n7774) );
INVX2TS U8664 ( .A(n7772), .Y(n7773) );
OAI21X4TS U8665 ( .A0(n7987), .A1(n7774), .B0(n7773), .Y(n7860) );
INVX2TS U8666 ( .A(n7775), .Y(n7777) );
OAI2BB1X4TS U8667 ( .A0N(n7860), .A1N(n7777), .B0(n7776), .Y(n7803) );
AOI21X4TS U8668 ( .A0(n7803), .A1(n7779), .B0(n7778), .Y(n7795) );
OAI21X2TS U8669 ( .A0(n7795), .A1(n7791), .B0(n7792), .Y(n7784) );
NAND2X1TS U8670 ( .A(n7782), .B(n7781), .Y(n7783) );
XNOR2X4TS U8671 ( .A(n7784), .B(n7783), .Y(n7785) );
BUFX3TS U8672 ( .A(n8069), .Y(n7911) );
BUFX3TS U8673 ( .A(n8070), .Y(n8040) );
AOI22X1TS U8674 ( .A0(n7877), .A1(Add_result[30]), .B0(
Sgf_normalized_result[29]), .B1(n8040), .Y(n7786) );
OAI2BB1X1TS U8675 ( .A0N(n7911), .A1N(P_Sgf[82]), .B0(n7786), .Y(n7787) );
AOI21X1TS U8676 ( .A0(n7880), .A1(Add_result[29]), .B0(n7787), .Y(n7788) );
OAI2BB1X1TS U8677 ( .A0N(n7899), .A1N(P_Sgf[81]), .B0(n7788), .Y(n382) );
XNOR2X1TS U8678 ( .A(n7789), .B(n8456), .Y(n7790) );
NAND2X1TS U8679 ( .A(n7793), .B(n7792), .Y(n7794) );
XOR2X1TS U8680 ( .A(n7795), .B(n7794), .Y(n7796) );
AOI22X1TS U8681 ( .A0(n7877), .A1(Add_result[29]), .B0(
Sgf_normalized_result[28]), .B1(n8040), .Y(n7797) );
OAI2BB1X1TS U8682 ( .A0N(n7911), .A1N(P_Sgf[81]), .B0(n7797), .Y(n7798) );
AOI21X1TS U8683 ( .A0(n7880), .A1(Add_result[28]), .B0(n7798), .Y(n7799) );
OAI2BB1X1TS U8684 ( .A0N(n7899), .A1N(P_Sgf[80]), .B0(n7799), .Y(n381) );
NAND2X1TS U8685 ( .A(n7800), .B(Sgf_normalized_result[26]), .Y(n7801) );
XOR2X1TS U8686 ( .A(n7801), .B(n8478), .Y(n7802) );
OAI21X4TS U8687 ( .A0(n7819), .A1(n7815), .B0(n7816), .Y(n7808) );
CLKINVX1TS U8688 ( .A(n7804), .Y(n7806) );
NAND2X1TS U8689 ( .A(n7806), .B(n7805), .Y(n7807) );
AOI22X1TS U8690 ( .A0(n7877), .A1(Add_result[28]), .B0(
Sgf_normalized_result[27]), .B1(n8040), .Y(n7810) );
OAI2BB1X1TS U8691 ( .A0N(n7911), .A1N(P_Sgf[80]), .B0(n7810), .Y(n7811) );
AOI21X1TS U8692 ( .A0(n7880), .A1(Add_result[27]), .B0(n7811), .Y(n7812) );
OAI2BB1X1TS U8693 ( .A0N(n7545), .A1N(P_Sgf[79]), .B0(n7812), .Y(n380) );
XOR2X1TS U8694 ( .A(n7813), .B(n8462), .Y(n7814) );
INVX2TS U8695 ( .A(n7815), .Y(n7817) );
NAND2X1TS U8696 ( .A(n7817), .B(n7816), .Y(n7818) );
XOR2X1TS U8697 ( .A(n7819), .B(n7818), .Y(n7820) );
AOI22X1TS U8698 ( .A0(n7877), .A1(Add_result[27]), .B0(
Sgf_normalized_result[26]), .B1(n8040), .Y(n7821) );
OAI2BB1X1TS U8699 ( .A0N(n7911), .A1N(P_Sgf[79]), .B0(n7821), .Y(n7822) );
AOI21X1TS U8700 ( .A0(n7880), .A1(Add_result[26]), .B0(n7822), .Y(n7823) );
OAI2BB1X1TS U8701 ( .A0N(n7545), .A1N(P_Sgf[78]), .B0(n7823), .Y(n379) );
INVX2TS U8702 ( .A(n7855), .Y(n7870) );
NOR2X1TS U8703 ( .A(n7870), .B(n7826), .Y(n7844) );
NAND2X1TS U8704 ( .A(n7844), .B(Sgf_normalized_result[24]), .Y(n7827) );
XOR2X1TS U8705 ( .A(n7827), .B(n8479), .Y(n7828) );
INVX2TS U8706 ( .A(n7829), .Y(n7832) );
INVX2TS U8707 ( .A(n7830), .Y(n7831) );
INVX2TS U8708 ( .A(n7833), .Y(n7847) );
INVX2TS U8709 ( .A(n7846), .Y(n7834) );
NAND2X1TS U8710 ( .A(n7837), .B(n7836), .Y(n7838) );
CLKMX2X2TS U8711 ( .A(P_Sgf[77]), .B(n7840), .S0(n7850), .Y(n498) );
AOI22X1TS U8712 ( .A0(n7877), .A1(Add_result[26]), .B0(
Sgf_normalized_result[25]), .B1(n8040), .Y(n7841) );
OAI2BB1X1TS U8713 ( .A0N(n7911), .A1N(P_Sgf[78]), .B0(n7841), .Y(n7842) );
AOI21X1TS U8714 ( .A0(n7880), .A1(Add_result[25]), .B0(n7842), .Y(n7843) );
OAI2BB1X1TS U8715 ( .A0N(n7545), .A1N(P_Sgf[77]), .B0(n7843), .Y(n378) );
XNOR2X1TS U8716 ( .A(n7844), .B(n8457), .Y(n7845) );
NAND2X1TS U8717 ( .A(n7847), .B(n7846), .Y(n7848) );
XNOR2X1TS U8718 ( .A(n7849), .B(n7848), .Y(n7851) );
AOI22X1TS U8719 ( .A0(n7877), .A1(Add_result[25]), .B0(
Sgf_normalized_result[24]), .B1(n8040), .Y(n7852) );
OAI2BB1X1TS U8720 ( .A0N(n7911), .A1N(P_Sgf[77]), .B0(n7852), .Y(n7853) );
AOI21X1TS U8721 ( .A0(n7880), .A1(Add_result[24]), .B0(n7853), .Y(n7854) );
OAI2BB1X1TS U8722 ( .A0N(n7545), .A1N(P_Sgf[76]), .B0(n7854), .Y(n377) );
NAND2X1TS U8723 ( .A(n7855), .B(Sgf_normalized_result[22]), .Y(n7856) );
XOR2X1TS U8724 ( .A(n7856), .B(n8480), .Y(n7857) );
INVX2TS U8725 ( .A(n7858), .Y(n7873) );
INVX2TS U8726 ( .A(n7872), .Y(n7859) );
AOI21X1TS U8727 ( .A0(n7860), .A1(n7873), .B0(n7859), .Y(n7865) );
INVX2TS U8728 ( .A(n7861), .Y(n7863) );
NAND2X1TS U8729 ( .A(n7863), .B(n7862), .Y(n7864) );
XOR2X1TS U8730 ( .A(n7865), .B(n7864), .Y(n7866) );
AOI22X1TS U8731 ( .A0(n7877), .A1(Add_result[24]), .B0(
Sgf_normalized_result[23]), .B1(n8040), .Y(n7867) );
OAI2BB1X1TS U8732 ( .A0N(n7911), .A1N(P_Sgf[76]), .B0(n7867), .Y(n7868) );
AOI21X1TS U8733 ( .A0(n7880), .A1(Add_result[23]), .B0(n7868), .Y(n7869) );
OAI2BB1X1TS U8734 ( .A0N(n7899), .A1N(P_Sgf[75]), .B0(n7869), .Y(n376) );
XOR2X1TS U8735 ( .A(n7870), .B(n8463), .Y(n7871) );
NAND2X1TS U8736 ( .A(n7873), .B(n7872), .Y(n7874) );
XOR2X1TS U8737 ( .A(n7875), .B(n7874), .Y(n7876) );
AOI22X1TS U8738 ( .A0(n7877), .A1(Add_result[23]), .B0(
Sgf_normalized_result[22]), .B1(n8040), .Y(n7878) );
OAI2BB1X1TS U8739 ( .A0N(n7911), .A1N(P_Sgf[75]), .B0(n7878), .Y(n7879) );
AOI21X1TS U8740 ( .A0(n7880), .A1(Add_result[22]), .B0(n7879), .Y(n7881) );
OAI2BB1X1TS U8741 ( .A0N(n7899), .A1N(P_Sgf[74]), .B0(n7881), .Y(n375) );
NOR2X1TS U8742 ( .A(n7928), .B(n7882), .Y(n7903) );
NAND2X1TS U8743 ( .A(n7903), .B(Sgf_normalized_result[20]), .Y(n7883) );
XOR2X1TS U8744 ( .A(n7883), .B(n8481), .Y(n7884) );
OAI21X4TS U8745 ( .A0(n7987), .A1(n7886), .B0(n7885), .Y(n7918) );
INVX2TS U8746 ( .A(n7887), .Y(n7890) );
INVX2TS U8747 ( .A(n7888), .Y(n7889) );
OAI21X4TS U8748 ( .A0(n7933), .A1(n7890), .B0(n7889), .Y(n7908) );
INVX2TS U8749 ( .A(n7891), .Y(n7906) );
INVX2TS U8750 ( .A(n7905), .Y(n7892) );
NAND2X1TS U8751 ( .A(n7895), .B(n7894), .Y(n7896) );
XOR2X1TS U8752 ( .A(n7897), .B(n7896), .Y(n7898) );
CLKMX2X2TS U8753 ( .A(P_Sgf[73]), .B(n7898), .S0(n7988), .Y(n494) );
BUFX3TS U8754 ( .A(n7899), .Y(n8028) );
BUFX3TS U8755 ( .A(n8039), .Y(n8026) );
BUFX3TS U8756 ( .A(n8178), .Y(n8023) );
AOI22X1TS U8757 ( .A0(n8023), .A1(Add_result[22]), .B0(
Sgf_normalized_result[21]), .B1(n8040), .Y(n7900) );
OAI2BB1X1TS U8758 ( .A0N(n7911), .A1N(P_Sgf[74]), .B0(n7900), .Y(n7901) );
AOI21X1TS U8759 ( .A0(n8026), .A1(Add_result[21]), .B0(n7901), .Y(n7902) );
OAI2BB1X1TS U8760 ( .A0N(n8028), .A1N(P_Sgf[73]), .B0(n7902), .Y(n374) );
XNOR2X1TS U8761 ( .A(n7903), .B(n8458), .Y(n7904) );
NAND2X1TS U8762 ( .A(n7906), .B(n7905), .Y(n7907) );
XNOR2X1TS U8763 ( .A(n7908), .B(n7907), .Y(n7909) );
BUFX3TS U8764 ( .A(n8070), .Y(n8052) );
AOI22X1TS U8765 ( .A0(n8023), .A1(Add_result[21]), .B0(
Sgf_normalized_result[20]), .B1(n8052), .Y(n7910) );
OAI2BB1X1TS U8766 ( .A0N(n7911), .A1N(P_Sgf[73]), .B0(n7910), .Y(n7912) );
AOI21X1TS U8767 ( .A0(n8026), .A1(Add_result[20]), .B0(n7912), .Y(n7913) );
OAI2BB1X1TS U8768 ( .A0N(n8028), .A1N(P_Sgf[72]), .B0(n7913), .Y(n373) );
XNOR2X1TS U8769 ( .A(n7914), .B(n8484), .Y(n7915) );
INVX2TS U8770 ( .A(n7916), .Y(n7931) );
INVX2TS U8771 ( .A(n7930), .Y(n7917) );
AOI21X1TS U8772 ( .A0(n7918), .A1(n7931), .B0(n7917), .Y(n7923) );
NAND2X1TS U8773 ( .A(n7921), .B(n7920), .Y(n7922) );
XOR2X1TS U8774 ( .A(n7923), .B(n7922), .Y(n7924) );
BUFX3TS U8775 ( .A(n8069), .Y(n8054) );
AOI22X1TS U8776 ( .A0(n8023), .A1(Add_result[20]), .B0(
Sgf_normalized_result[19]), .B1(n8052), .Y(n7925) );
OAI2BB1X1TS U8777 ( .A0N(n8054), .A1N(P_Sgf[72]), .B0(n7925), .Y(n7926) );
AOI21X1TS U8778 ( .A0(n8026), .A1(Add_result[19]), .B0(n7926), .Y(n7927) );
OAI2BB1X1TS U8779 ( .A0N(n8028), .A1N(P_Sgf[71]), .B0(n7927), .Y(n372) );
XOR2X1TS U8780 ( .A(n7928), .B(n8465), .Y(n7929) );
NAND2X1TS U8781 ( .A(n7931), .B(n7930), .Y(n7932) );
XOR2X1TS U8782 ( .A(n7933), .B(n7932), .Y(n7934) );
AOI22X1TS U8783 ( .A0(n8023), .A1(Add_result[19]), .B0(
Sgf_normalized_result[18]), .B1(n8052), .Y(n7935) );
OAI2BB1X1TS U8784 ( .A0N(n8054), .A1N(P_Sgf[71]), .B0(n7935), .Y(n7936) );
AOI21X1TS U8785 ( .A0(n8026), .A1(Add_result[18]), .B0(n7936), .Y(n7937) );
OAI2BB1X1TS U8786 ( .A0N(n8028), .A1N(P_Sgf[70]), .B0(n7937), .Y(n371) );
INVX2TS U8787 ( .A(n7938), .Y(n8044) );
NAND2X1TS U8788 ( .A(n8044), .B(n7939), .Y(n7969) );
INVX2TS U8789 ( .A(n7969), .Y(n7981) );
NAND2X1TS U8790 ( .A(n7981), .B(n7941), .Y(n7959) );
XNOR2X1TS U8791 ( .A(n7942), .B(n8485), .Y(n7943) );
INVX2TS U8792 ( .A(n7944), .Y(n7947) );
INVX2TS U8793 ( .A(n7945), .Y(n7946) );
OAI21X2TS U8794 ( .A0(n7987), .A1(n7947), .B0(n7946), .Y(n7964) );
INVX2TS U8795 ( .A(n7948), .Y(n7962) );
INVX2TS U8796 ( .A(n7961), .Y(n7949) );
AOI21X1TS U8797 ( .A0(n7964), .A1(n7962), .B0(n7949), .Y(n7954) );
CLKINVX1TS U8798 ( .A(n7950), .Y(n7952) );
NAND2X1TS U8799 ( .A(n7952), .B(n7951), .Y(n7953) );
XOR2X1TS U8800 ( .A(n7954), .B(n7953), .Y(n7955) );
AOI22X1TS U8801 ( .A0(n8023), .A1(Add_result[18]), .B0(
Sgf_normalized_result[17]), .B1(n8052), .Y(n7956) );
OAI2BB1X1TS U8802 ( .A0N(n8054), .A1N(P_Sgf[70]), .B0(n7956), .Y(n7957) );
AOI21X1TS U8803 ( .A0(n8026), .A1(Add_result[17]), .B0(n7957), .Y(n7958) );
OAI2BB1X1TS U8804 ( .A0N(n8028), .A1N(P_Sgf[69]), .B0(n7958), .Y(n370) );
XOR2X1TS U8805 ( .A(n7959), .B(n8466), .Y(n7960) );
NAND2X1TS U8806 ( .A(n7962), .B(n7961), .Y(n7963) );
XNOR2X1TS U8807 ( .A(n7964), .B(n7963), .Y(n7965) );
AOI22X1TS U8808 ( .A0(n8023), .A1(Add_result[17]), .B0(
Sgf_normalized_result[16]), .B1(n8052), .Y(n7966) );
OAI2BB1X1TS U8809 ( .A0N(n8054), .A1N(P_Sgf[69]), .B0(n7966), .Y(n7967) );
AOI21X1TS U8810 ( .A0(n8026), .A1(Add_result[16]), .B0(n7967), .Y(n7968) );
OAI2BB1X1TS U8811 ( .A0N(n8028), .A1N(P_Sgf[68]), .B0(n7968), .Y(n369) );
XNOR2X1TS U8812 ( .A(n7970), .B(n8486), .Y(n7971) );
INVX2TS U8813 ( .A(n7972), .Y(n7974) );
NAND2X1TS U8814 ( .A(n7974), .B(n7973), .Y(n7975) );
XNOR2X1TS U8815 ( .A(n7976), .B(n7975), .Y(n7977) );
AOI22X1TS U8816 ( .A0(n8023), .A1(Add_result[16]), .B0(
Sgf_normalized_result[15]), .B1(n8052), .Y(n7978) );
OAI2BB1X1TS U8817 ( .A0N(n8054), .A1N(P_Sgf[68]), .B0(n7978), .Y(n7979) );
AOI21X1TS U8818 ( .A0(n8026), .A1(Add_result[15]), .B0(n7979), .Y(n7980) );
OAI2BB1X1TS U8819 ( .A0N(n8028), .A1N(P_Sgf[67]), .B0(n7980), .Y(n368) );
XNOR2X1TS U8820 ( .A(n7981), .B(n8469), .Y(n7982) );
INVX2TS U8821 ( .A(n7983), .Y(n7985) );
NAND2X1TS U8822 ( .A(n7985), .B(n7984), .Y(n7986) );
XOR2X1TS U8823 ( .A(n7987), .B(n7986), .Y(n7989) );
AOI22X1TS U8824 ( .A0(n8023), .A1(Add_result[15]), .B0(
Sgf_normalized_result[14]), .B1(n8052), .Y(n7990) );
OAI2BB1X1TS U8825 ( .A0N(n8054), .A1N(P_Sgf[67]), .B0(n7990), .Y(n7991) );
AOI21X1TS U8826 ( .A0(n8026), .A1(Add_result[14]), .B0(n7991), .Y(n7992) );
OAI2BB1X1TS U8827 ( .A0N(n8028), .A1N(P_Sgf[66]), .B0(n7992), .Y(n367) );
NAND2X1TS U8828 ( .A(n8044), .B(n7994), .Y(n8015) );
XNOR2X1TS U8829 ( .A(n7995), .B(n8487), .Y(n7996) );
INVX6TS U8830 ( .A(n7997), .Y(n8346) );
AOI21X4TS U8831 ( .A0(n8346), .A1(n7999), .B0(n7998), .Y(n8087) );
INVX2TS U8832 ( .A(n8000), .Y(n8003) );
INVX2TS U8833 ( .A(n8001), .Y(n8002) );
AOI21X4TS U8834 ( .A0(n8103), .A1(n8003), .B0(n8002), .Y(n8032) );
INVX2TS U8835 ( .A(n8032), .Y(n8050) );
AOI21X4TS U8836 ( .A0(n8050), .A1(n8005), .B0(n8004), .Y(n8021) );
NAND2X1TS U8837 ( .A(n8008), .B(n8007), .Y(n8009) );
CLKMX2X2TS U8838 ( .A(P_Sgf[65]), .B(n8011), .S0(n8133), .Y(n486) );
AOI22X1TS U8839 ( .A0(n8023), .A1(Add_result[14]), .B0(
Sgf_normalized_result[13]), .B1(n8052), .Y(n8012) );
OAI2BB1X1TS U8840 ( .A0N(n8054), .A1N(P_Sgf[66]), .B0(n8012), .Y(n8013) );
AOI21X1TS U8841 ( .A0(n8026), .A1(Add_result[13]), .B0(n8013), .Y(n8014) );
OAI2BB1X1TS U8842 ( .A0N(n8028), .A1N(P_Sgf[65]), .B0(n8014), .Y(n366) );
XOR2X1TS U8843 ( .A(n8015), .B(n8467), .Y(n8016) );
NAND2X1TS U8844 ( .A(n8019), .B(n8018), .Y(n8020) );
XOR2X1TS U8845 ( .A(n8021), .B(n8020), .Y(n8022) );
AOI22X1TS U8846 ( .A0(n8023), .A1(Add_result[13]), .B0(
Sgf_normalized_result[12]), .B1(n8052), .Y(n8024) );
OAI2BB1X1TS U8847 ( .A0N(n8054), .A1N(P_Sgf[65]), .B0(n8024), .Y(n8025) );
AOI21X1TS U8848 ( .A0(n8026), .A1(Add_result[12]), .B0(n8025), .Y(n8027) );
OAI2BB1X1TS U8849 ( .A0N(n8028), .A1N(P_Sgf[64]), .B0(n8027), .Y(n365) );
NAND2X1TS U8850 ( .A(n8044), .B(Sgf_normalized_result[10]), .Y(n8029) );
XOR2X1TS U8851 ( .A(n8029), .B(n8482), .Y(n8031) );
NAND2X1TS U8852 ( .A(n8035), .B(n8034), .Y(n8036) );
XNOR2X1TS U8853 ( .A(n8037), .B(n8036), .Y(n8038) );
BUFX3TS U8854 ( .A(n8039), .Y(n8158) );
BUFX3TS U8855 ( .A(n8178), .Y(n8155) );
AOI22X1TS U8856 ( .A0(n8155), .A1(Add_result[12]), .B0(
Sgf_normalized_result[11]), .B1(n8040), .Y(n8041) );
OAI2BB1X1TS U8857 ( .A0N(n8054), .A1N(P_Sgf[64]), .B0(n8041), .Y(n8042) );
AOI21X1TS U8858 ( .A0(n8158), .A1(Add_result[11]), .B0(n8042), .Y(n8043) );
OAI2BB1X1TS U8859 ( .A0N(n8183), .A1N(P_Sgf[63]), .B0(n8043), .Y(n364) );
XNOR2X1TS U8860 ( .A(n8044), .B(n8459), .Y(n8045) );
INVX2TS U8861 ( .A(n8046), .Y(n8048) );
NAND2X1TS U8862 ( .A(n8048), .B(n8047), .Y(n8049) );
XNOR2X1TS U8863 ( .A(n8050), .B(n8049), .Y(n8051) );
AOI22X1TS U8864 ( .A0(n8155), .A1(Add_result[11]), .B0(
Sgf_normalized_result[10]), .B1(n8052), .Y(n8053) );
OAI2BB1X1TS U8865 ( .A0N(n8054), .A1N(P_Sgf[63]), .B0(n8053), .Y(n8055) );
AOI21X1TS U8866 ( .A0(n8158), .A1(Add_result[10]), .B0(n8055), .Y(n8056) );
OAI2BB1X1TS U8867 ( .A0N(n8183), .A1N(P_Sgf[62]), .B0(n8056), .Y(n363) );
NOR2X1TS U8868 ( .A(n8097), .B(n8058), .Y(n8074) );
NAND2X1TS U8869 ( .A(n8074), .B(Sgf_normalized_result[8]), .Y(n8059) );
XOR2X1TS U8870 ( .A(n8059), .B(n8483), .Y(n8060) );
NAND2X1TS U8871 ( .A(n8065), .B(n8064), .Y(n8066) );
BUFX3TS U8872 ( .A(n8069), .Y(n8180) );
BUFX3TS U8873 ( .A(n8070), .Y(n8177) );
AOI22X1TS U8874 ( .A0(n8155), .A1(Add_result[10]), .B0(
Sgf_normalized_result[9]), .B1(n8177), .Y(n8071) );
OAI2BB1X1TS U8875 ( .A0N(n8180), .A1N(P_Sgf[62]), .B0(n8071), .Y(n8072) );
AOI21X1TS U8876 ( .A0(n8158), .A1(Add_result[9]), .B0(n8072), .Y(n8073) );
OAI2BB1X1TS U8877 ( .A0N(n8183), .A1N(P_Sgf[61]), .B0(n8073), .Y(n362) );
XNOR2X1TS U8878 ( .A(n8074), .B(n8460), .Y(n8075) );
NAND2X1TS U8879 ( .A(n8078), .B(n8077), .Y(n8079) );
XOR2X1TS U8880 ( .A(n8080), .B(n8079), .Y(n8081) );
AOI22X1TS U8881 ( .A0(n8155), .A1(Add_result[9]), .B0(
Sgf_normalized_result[8]), .B1(n8177), .Y(n8082) );
OAI2BB1X1TS U8882 ( .A0N(n8180), .A1N(P_Sgf[61]), .B0(n8082), .Y(n8083) );
AOI21X1TS U8883 ( .A0(n8158), .A1(Add_result[8]), .B0(n8083), .Y(n8084) );
OAI2BB1X1TS U8884 ( .A0N(n7899), .A1N(P_Sgf[60]), .B0(n8084), .Y(n361) );
XNOR2X1TS U8885 ( .A(n8085), .B(n8488), .Y(n8086) );
NAND2X1TS U8886 ( .A(n8090), .B(n8089), .Y(n8091) );
XNOR2X1TS U8887 ( .A(n8092), .B(n8091), .Y(n8093) );
AOI22X1TS U8888 ( .A0(n8155), .A1(Add_result[8]), .B0(
Sgf_normalized_result[7]), .B1(n8177), .Y(n8094) );
OAI2BB1X1TS U8889 ( .A0N(n8180), .A1N(P_Sgf[60]), .B0(n8094), .Y(n8095) );
AOI21X1TS U8890 ( .A0(n8158), .A1(Add_result[7]), .B0(n8095), .Y(n8096) );
OAI2BB1X1TS U8891 ( .A0N(n7545), .A1N(P_Sgf[59]), .B0(n8096), .Y(n360) );
XOR2X1TS U8892 ( .A(n8097), .B(n8468), .Y(n8098) );
INVX2TS U8893 ( .A(n8099), .Y(n8101) );
NAND2X1TS U8894 ( .A(n8101), .B(n8100), .Y(n8102) );
XNOR2X1TS U8895 ( .A(n8103), .B(n8102), .Y(n8104) );
AOI22X1TS U8896 ( .A0(n8155), .A1(Add_result[7]), .B0(
Sgf_normalized_result[6]), .B1(n8177), .Y(n8105) );
OAI2BB1X1TS U8897 ( .A0N(n8180), .A1N(P_Sgf[59]), .B0(n8105), .Y(n8106) );
AOI21X1TS U8898 ( .A0(n8158), .A1(Add_result[6]), .B0(n8106), .Y(n8107) );
OAI2BB1X1TS U8899 ( .A0N(n7545), .A1N(P_Sgf[58]), .B0(n8107), .Y(n359) );
XOR2X1TS U8900 ( .A(n8109), .B(Sgf_normalized_result[5]), .Y(n8110) );
INVX2TS U8901 ( .A(n8111), .Y(n8114) );
INVX2TS U8902 ( .A(n8112), .Y(n8113) );
AOI21X4TS U8903 ( .A0(n8346), .A1(n8114), .B0(n8113), .Y(n8139) );
INVX2TS U8904 ( .A(n8139), .Y(n8153) );
AOI21X2TS U8905 ( .A0(n8153), .A1(n8116), .B0(n8115), .Y(n8132) );
OAI21X1TS U8906 ( .A0(n8132), .A1(n8128), .B0(n8129), .Y(n8121) );
NAND2X1TS U8907 ( .A(n8119), .B(n8118), .Y(n8120) );
XNOR2X1TS U8908 ( .A(n8121), .B(n8120), .Y(n8122) );
CLKMX2X2TS U8909 ( .A(P_Sgf[57]), .B(n8122), .S0(n8133), .Y(n478) );
AOI22X1TS U8910 ( .A0(n8155), .A1(Add_result[6]), .B0(
Sgf_normalized_result[5]), .B1(n8177), .Y(n8123) );
OAI2BB1X1TS U8911 ( .A0N(n8180), .A1N(P_Sgf[58]), .B0(n8123), .Y(n8124) );
AOI21X1TS U8912 ( .A0(n8158), .A1(Add_result[5]), .B0(n8124), .Y(n8125) );
OAI2BB1X1TS U8913 ( .A0N(n7545), .A1N(P_Sgf[57]), .B0(n8125), .Y(n358) );
XNOR2X1TS U8914 ( .A(n8126), .B(Sgf_normalized_result[4]), .Y(n8127) );
NAND2X1TS U8915 ( .A(n8130), .B(n8129), .Y(n8131) );
XOR2X1TS U8916 ( .A(n8132), .B(n8131), .Y(n8134) );
AOI22X1TS U8917 ( .A0(n8155), .A1(Add_result[5]), .B0(
Sgf_normalized_result[4]), .B1(n8177), .Y(n8135) );
OAI2BB1X1TS U8918 ( .A0N(n8180), .A1N(P_Sgf[57]), .B0(n8135), .Y(n8136) );
AOI21X1TS U8919 ( .A0(n8158), .A1(Add_result[4]), .B0(n8136), .Y(n8137) );
OAI2BB1X1TS U8920 ( .A0N(n8183), .A1N(P_Sgf[56]), .B0(n8137), .Y(n357) );
XNOR2X1TS U8921 ( .A(n8489), .B(Sgf_normalized_result[2]), .Y(n8138) );
NAND2X1TS U8922 ( .A(n8142), .B(n8141), .Y(n8143) );
XNOR2X1TS U8923 ( .A(n8144), .B(n8143), .Y(n8145) );
AOI22X1TS U8924 ( .A0(n8155), .A1(Add_result[4]), .B0(
Sgf_normalized_result[3]), .B1(n8177), .Y(n8146) );
OAI2BB1X1TS U8925 ( .A0N(n8180), .A1N(P_Sgf[56]), .B0(n8146), .Y(n8147) );
AOI21X1TS U8926 ( .A0(n8158), .A1(Add_result[3]), .B0(n8147), .Y(n8148) );
OAI2BB1X1TS U8927 ( .A0N(n7545), .A1N(P_Sgf[55]), .B0(n8148), .Y(n356) );
NAND2X1TS U8928 ( .A(n8151), .B(n8150), .Y(n8152) );
XNOR2X1TS U8929 ( .A(n8153), .B(n8152), .Y(n8154) );
AOI22X1TS U8930 ( .A0(n8155), .A1(Add_result[3]), .B0(
Sgf_normalized_result[2]), .B1(n8177), .Y(n8156) );
OAI2BB1X1TS U8931 ( .A0N(n8180), .A1N(P_Sgf[55]), .B0(n8156), .Y(n8157) );
AOI21X1TS U8932 ( .A0(n8158), .A1(Add_result[2]), .B0(n8157), .Y(n8159) );
OAI2BB1X1TS U8933 ( .A0N(n8183), .A1N(P_Sgf[54]), .B0(n8159), .Y(n355) );
AOI21X2TS U8934 ( .A0(n8346), .A1(n8161), .B0(n8160), .Y(n8175) );
NAND2X1TS U8935 ( .A(n8164), .B(n8163), .Y(n8165) );
XNOR2X1TS U8936 ( .A(n8166), .B(n8165), .Y(n8167) );
AOI22X1TS U8937 ( .A0(n8178), .A1(Add_result[2]), .B0(
Sgf_normalized_result[1]), .B1(n8177), .Y(n8168) );
OAI2BB1X1TS U8938 ( .A0N(n8180), .A1N(P_Sgf[54]), .B0(n8168), .Y(n8169) );
AOI21X1TS U8939 ( .A0(n8039), .A1(Add_result[1]), .B0(n8169), .Y(n8170) );
OAI2BB1X1TS U8940 ( .A0N(n8183), .A1N(P_Sgf[53]), .B0(n8170), .Y(n354) );
INVX2TS U8941 ( .A(n8171), .Y(n8173) );
NAND2X1TS U8942 ( .A(n8173), .B(n8172), .Y(n8174) );
XOR2X1TS U8943 ( .A(n8175), .B(n8174), .Y(n8176) );
AOI22X1TS U8944 ( .A0(n8178), .A1(Add_result[1]), .B0(
Sgf_normalized_result[0]), .B1(n8177), .Y(n8179) );
OAI2BB1X1TS U8945 ( .A0N(n8180), .A1N(P_Sgf[53]), .B0(n8179), .Y(n8181) );
AOI21X1TS U8946 ( .A0(n8039), .A1(Add_result[0]), .B0(n8181), .Y(n8182) );
OAI2BB1X1TS U8947 ( .A0N(P_Sgf[52]), .A1N(n8183), .B0(n8182), .Y(n353) );
AHHCONX2TS U8948 ( .A(Sgf_normalized_result[52]), .CI(n8184), .CON(n8185),
.S(n7532) );
INVX2TS U8949 ( .A(n8185), .Y(n8187) );
OR2X1TS U8950 ( .A(n8193), .B(Sgf_operation_ODD1_Q_right[27]), .Y(n8195) );
CLKAND2X2TS U8951 ( .A(n8195), .B(n8194), .Y(n8196) );
NAND2X1TS U8952 ( .A(n986), .B(n8197), .Y(n8199) );
XNOR2X1TS U8953 ( .A(n8199), .B(n8198), .Y(n8200) );
NAND2X1TS U8954 ( .A(n781), .B(n8201), .Y(n8203) );
INVX2TS U8955 ( .A(n8202), .Y(n8206) );
XNOR2X1TS U8956 ( .A(n8203), .B(n8206), .Y(n8204) );
AOI21X1TS U8957 ( .A0(n8206), .A1(n781), .B0(n8205), .Y(n8209) );
NAND2X1TS U8958 ( .A(n731), .B(n8207), .Y(n8208) );
XOR2X1TS U8959 ( .A(n8209), .B(n8208), .Y(n8210) );
NAND2X1TS U8960 ( .A(n991), .B(n8211), .Y(n8212) );
XNOR2X1TS U8961 ( .A(n8213), .B(n8212), .Y(n8214) );
INVX2TS U8962 ( .A(n8215), .Y(n8220) );
NAND2X1TS U8963 ( .A(n987), .B(n8216), .Y(n8217) );
XNOR2X1TS U8964 ( .A(n8220), .B(n8217), .Y(n8218) );
AOI21X1TS U8965 ( .A0(n8220), .A1(n987), .B0(n8219), .Y(n8223) );
NAND2X1TS U8966 ( .A(n990), .B(n8221), .Y(n8222) );
XOR2X1TS U8967 ( .A(n8223), .B(n8222), .Y(n8225) );
INVX2TS U8968 ( .A(n8226), .Y(n8238) );
NAND2X1TS U8969 ( .A(n8227), .B(n8230), .Y(n8228) );
XOR2X1TS U8970 ( .A(n8238), .B(n8228), .Y(n8229) );
NAND2X1TS U8971 ( .A(n988), .B(n8232), .Y(n8233) );
XNOR2X1TS U8972 ( .A(n8234), .B(n8233), .Y(n8235) );
OAI21X1TS U8973 ( .A0(n8238), .A1(n8237), .B0(n8236), .Y(n8243) );
NAND2X1TS U8974 ( .A(n4284), .B(n8239), .Y(n8240) );
XNOR2X1TS U8975 ( .A(n8243), .B(n8240), .Y(n8241) );
AOI21X1TS U8976 ( .A0(n8243), .A1(n4284), .B0(n8242), .Y(n8246) );
NAND2X1TS U8977 ( .A(n989), .B(n8244), .Y(n8245) );
XOR2X1TS U8978 ( .A(n8246), .B(n8245), .Y(n8247) );
INVX2TS U8979 ( .A(n8248), .Y(n8309) );
INVX2TS U8980 ( .A(n8249), .Y(n8254) );
NAND2X1TS U8981 ( .A(n8254), .B(n8252), .Y(n8250) );
XNOR2X1TS U8982 ( .A(n8309), .B(n8250), .Y(n8251) );
INVX2TS U8983 ( .A(n8252), .Y(n8253) );
AOI21X1TS U8984 ( .A0(n8309), .A1(n8254), .B0(n8253), .Y(n8259) );
INVX2TS U8985 ( .A(n8255), .Y(n8257) );
NAND2X1TS U8986 ( .A(n8257), .B(n8256), .Y(n8258) );
XOR2X1TS U8987 ( .A(n8259), .B(n8258), .Y(n8260) );
OAI21X2TS U8988 ( .A0(n8305), .A1(n8263), .B0(n8262), .Y(n8272) );
INVX2TS U8989 ( .A(n8264), .Y(n8274) );
INVX2TS U8990 ( .A(n8273), .Y(n8265) );
AOI21X1TS U8991 ( .A0(n8272), .A1(n8274), .B0(n8265), .Y(n8270) );
NAND2X1TS U8992 ( .A(n8268), .B(n8267), .Y(n8269) );
XOR2X1TS U8993 ( .A(n8270), .B(n8269), .Y(n8271) );
INVX2TS U8994 ( .A(n8272), .Y(n8326) );
NAND2X1TS U8995 ( .A(n8274), .B(n8273), .Y(n8275) );
XOR2X1TS U8996 ( .A(n8326), .B(n8275), .Y(n8276) );
INVX2TS U8997 ( .A(n8278), .Y(n8279) );
OAI21X1TS U8998 ( .A0(n8305), .A1(n8280), .B0(n8279), .Y(n8292) );
INVX2TS U8999 ( .A(n8281), .Y(n8290) );
INVX2TS U9000 ( .A(n8289), .Y(n8282) );
AOI21X1TS U9001 ( .A0(n8292), .A1(n8290), .B0(n8282), .Y(n8287) );
NAND2X1TS U9002 ( .A(n8285), .B(n8284), .Y(n8286) );
XOR2X1TS U9003 ( .A(n8287), .B(n8286), .Y(n8288) );
NAND2X1TS U9004 ( .A(n8290), .B(n8289), .Y(n8291) );
XNOR2X1TS U9005 ( .A(n8292), .B(n8291), .Y(n8294) );
NAND2X1TS U9006 ( .A(n8297), .B(n8296), .Y(n8298) );
XNOR2X1TS U9007 ( .A(n8299), .B(n8298), .Y(n8300) );
NAND2X1TS U9008 ( .A(n8303), .B(n8302), .Y(n8304) );
XOR2X1TS U9009 ( .A(n8305), .B(n8304), .Y(n8306) );
AOI21X1TS U9010 ( .A0(n8309), .A1(n8308), .B0(n8307), .Y(n8320) );
NAND2X1TS U9011 ( .A(n8312), .B(n8311), .Y(n8313) );
XNOR2X1TS U9012 ( .A(n8314), .B(n8313), .Y(n8315) );
INVX2TS U9013 ( .A(n8316), .Y(n8318) );
NAND2X1TS U9014 ( .A(n8318), .B(n8317), .Y(n8319) );
XOR2X1TS U9015 ( .A(n8320), .B(n8319), .Y(n8321) );
INVX2TS U9016 ( .A(n8322), .Y(n8325) );
INVX2TS U9017 ( .A(n8323), .Y(n8324) );
INVX2TS U9018 ( .A(n8327), .Y(n8332) );
NAND2X1TS U9019 ( .A(n8332), .B(n8330), .Y(n8328) );
XNOR2X1TS U9020 ( .A(n8333), .B(n8328), .Y(n8329) );
INVX2TS U9021 ( .A(n8330), .Y(n8331) );
AOI21X1TS U9022 ( .A0(n8333), .A1(n8332), .B0(n8331), .Y(n8338) );
NAND2X1TS U9023 ( .A(n8336), .B(n8335), .Y(n8337) );
XOR2X1TS U9024 ( .A(n8338), .B(n8337), .Y(n8339) );
INVX2TS U9025 ( .A(n8340), .Y(n8345) );
NAND2X1TS U9026 ( .A(n8345), .B(n8343), .Y(n8341) );
XNOR2X1TS U9027 ( .A(n8346), .B(n8341), .Y(n8342) );
INVX2TS U9028 ( .A(n8343), .Y(n8344) );
AOI21X1TS U9029 ( .A0(n8346), .A1(n8345), .B0(n8344), .Y(n8351) );
NAND2X1TS U9030 ( .A(n8349), .B(n8348), .Y(n8350) );
XOR2X1TS U9031 ( .A(n8351), .B(n8350), .Y(n8352) );
NAND2X1TS U9032 ( .A(n8427), .B(n8471), .Y(n710) );
NOR2BX1TS U9033 ( .AN(exp_oper_result[11]), .B(n8471), .Y(S_Oper_A_exp[11])
);
CLKMX2X2TS U9034 ( .A(Op_MX[57]), .B(exp_oper_result[5]), .S0(n847), .Y(
S_Oper_A_exp[5]) );
CLKMX2X2TS U9035 ( .A(Op_MX[53]), .B(exp_oper_result[1]), .S0(n846), .Y(
S_Oper_A_exp[1]) );
NAND4BX1TS U9036 ( .AN(n8356), .B(Exp_module_Data_S[6]), .C(
Exp_module_Data_S[5]), .D(Exp_module_Data_S[4]), .Y(n8357) );
NAND4BX1TS U9037 ( .AN(n8357), .B(Exp_module_Data_S[9]), .C(
Exp_module_Data_S[8]), .D(Exp_module_Data_S[7]), .Y(n8358) );
NAND3BX1TS U9038 ( .AN(Exp_module_Data_S[10]), .B(n8430), .C(n8358), .Y(
n8359) );
OAI22X1TS U9039 ( .A0(Exp_module_Data_S[11]), .A1(n8359), .B0(n8430), .B1(
n8491), .Y(n352) );
AO22X1TS U9040 ( .A0(n8360), .A1(Sgf_normalized_result[2]), .B0(
final_result_ieee[2]), .B1(n8364), .Y(n349) );
AO22X1TS U9041 ( .A0(n8439), .A1(Sgf_normalized_result[23]), .B0(
final_result_ieee[23]), .B1(n8364), .Y(n328) );
AO22X1TS U9042 ( .A0(n8439), .A1(Sgf_normalized_result[24]), .B0(
final_result_ieee[24]), .B1(n8364), .Y(n327) );
AO22X1TS U9043 ( .A0(n8439), .A1(Sgf_normalized_result[25]), .B0(
final_result_ieee[25]), .B1(n8364), .Y(n326) );
AO22X1TS U9044 ( .A0(n8439), .A1(Sgf_normalized_result[26]), .B0(
final_result_ieee[26]), .B1(n8364), .Y(n325) );
AO22X1TS U9045 ( .A0(n8439), .A1(Sgf_normalized_result[27]), .B0(
final_result_ieee[27]), .B1(n8364), .Y(n324) );
AO22X1TS U9046 ( .A0(n8439), .A1(Sgf_normalized_result[28]), .B0(
final_result_ieee[28]), .B1(n8364), .Y(n323) );
AO22X1TS U9047 ( .A0(n8439), .A1(Sgf_normalized_result[29]), .B0(
final_result_ieee[29]), .B1(n8364), .Y(n322) );
AO22X1TS U9048 ( .A0(n8439), .A1(Sgf_normalized_result[30]), .B0(
final_result_ieee[30]), .B1(n8364), .Y(n321) );
AO22X1TS U9049 ( .A0(n8365), .A1(Data_MY[63]), .B0(n7504), .B1(Op_MY[63]),
.Y(n715) );
AOI21X1TS U9050 ( .A0(FS_Module_state_reg[2]), .A1(n8367), .B0(n8366), .Y(
n8370) );
NOR4X1TS U9051 ( .A(n830), .B(n855), .C(n902), .D(n5213), .Y(n8380) );
NOR4X1TS U9052 ( .A(Op_MY[34]), .B(Op_MY[33]), .C(n852), .D(n849), .Y(n8379)
);
NAND4XLTS U9053 ( .A(n8381), .B(n8380), .C(n8379), .D(n807), .Y(n8401) );
NOR4X1TS U9054 ( .A(Op_MY[19]), .B(Op_MY[15]), .C(Op_MY[13]), .D(Op_MY[10]),
.Y(n8384) );
NOR4X1TS U9055 ( .A(Op_MY[24]), .B(Op_MY[18]), .C(Op_MY[9]), .D(Op_MY[7]),
.Y(n8383) );
NOR4X1TS U9056 ( .A(Op_MY[12]), .B(Op_MY[6]), .C(Op_MY[1]), .D(Op_MY[4]),
.Y(n8382) );
NAND4XLTS U9057 ( .A(n8384), .B(n8383), .C(n8382), .D(n810), .Y(n8400) );
NOR4X1TS U9058 ( .A(Op_MY[38]), .B(Op_MY[37]), .C(Op_MY[36]), .D(n832), .Y(
n8390) );
NOR4X1TS U9059 ( .A(Op_MY[42]), .B(Op_MY[41]), .C(Op_MY[40]), .D(n828), .Y(
n8389) );
NOR4X1TS U9060 ( .A(Op_MY[46]), .B(Op_MY[45]), .C(Op_MY[44]), .D(n840), .Y(
n8388) );
NOR4X1TS U9061 ( .A(n8386), .B(Op_MY[49]), .C(Op_MY[48]), .D(Op_MY[47]), .Y(
n8387) );
NAND4XLTS U9062 ( .A(n8390), .B(n8389), .C(n8388), .D(n8387), .Y(n8399) );
NOR4X1TS U9063 ( .A(Op_MY[57]), .B(Op_MY[56]), .C(Op_MY[55]), .D(Op_MY[54]),
.Y(n8397) );
NOR4X1TS U9064 ( .A(Op_MY[61]), .B(Op_MY[60]), .C(Op_MY[59]), .D(Op_MY[58]),
.Y(n8396) );
NAND4XLTS U9065 ( .A(n8397), .B(n8396), .C(n8395), .D(n8394), .Y(n8398) );
OR4X2TS U9066 ( .A(n8401), .B(n8400), .C(n8399), .D(n8398), .Y(n8431) );
NOR4X1TS U9067 ( .A(Op_MX[24]), .B(Op_MX[23]), .C(Op_MX[22]), .D(n8402), .Y(
n8406) );
NAND4XLTS U9068 ( .A(n8407), .B(n8406), .C(n777), .D(n8405), .Y(n8426) );
NOR4X1TS U9069 ( .A(Op_MX[49]), .B(Op_MX[43]), .C(Op_MX[31]), .D(Op_MX[33]),
.Y(n8411) );
NOR4X1TS U9070 ( .A(Op_MX[48]), .B(Op_MX[42]), .C(Op_MX[30]), .D(Op_MX[37]),
.Y(n8410) );
NOR4X1TS U9071 ( .A(Op_MX[46]), .B(Op_MX[40]), .C(Op_MX[28]), .D(Op_MX[36]),
.Y(n8409) );
NAND4XLTS U9072 ( .A(n8411), .B(n8410), .C(n8409), .D(n8408), .Y(n8425) );
NOR4X1TS U9073 ( .A(Op_MX[19]), .B(n8412), .C(Op_MX[4]), .D(Op_MX[0]), .Y(
n8418) );
NOR4X1TS U9074 ( .A(Op_MX[17]), .B(Op_MX[13]), .C(Op_MX[10]), .D(n8413), .Y(
n8417) );
NOR4X1TS U9075 ( .A(Op_MX[15]), .B(Op_MX[12]), .C(Op_MX[5]), .D(Op_MX[3]),
.Y(n8416) );
NOR4X1TS U9076 ( .A(Op_MX[11]), .B(n842), .C(Op_MX[7]), .D(n8414), .Y(n8415)
);
NAND4XLTS U9077 ( .A(n8418), .B(n8417), .C(n8416), .D(n8415), .Y(n8424) );
NOR4X1TS U9078 ( .A(Op_MX[57]), .B(Op_MX[56]), .C(Op_MX[55]), .D(Op_MX[54]),
.Y(n8422) );
NOR4X1TS U9079 ( .A(Op_MX[61]), .B(Op_MX[60]), .C(Op_MX[59]), .D(Op_MX[58]),
.Y(n8421) );
NAND4XLTS U9080 ( .A(n8422), .B(n8421), .C(n8420), .D(n8419), .Y(n8423) );
OR4X2TS U9081 ( .A(n8426), .B(n8425), .C(n8424), .D(n8423), .Y(n8429) );
AOI32X1TS U9082 ( .A0(n8431), .A1(n8430), .A2(n8429), .B0(n8428), .B1(n8427),
.Y(n581) );
INVX2TS U9083 ( .A(n8443), .Y(n8438) );
OA22X1TS U9084 ( .A0(n8441), .A1(final_result_ieee[52]), .B0(
exp_oper_result[0]), .B1(n8440), .Y(n299) );
OA22X1TS U9085 ( .A0(n8441), .A1(final_result_ieee[54]), .B0(
exp_oper_result[2]), .B1(n8440), .Y(n297) );
OA22X1TS U9086 ( .A0(n8441), .A1(final_result_ieee[55]), .B0(
exp_oper_result[3]), .B1(n8440), .Y(n296) );
OA22X1TS U9087 ( .A0(n8441), .A1(final_result_ieee[56]), .B0(
exp_oper_result[4]), .B1(n8440), .Y(n295) );
OA22X1TS U9088 ( .A0(n8443), .A1(final_result_ieee[61]), .B0(
exp_oper_result[9]), .B1(n8442), .Y(n290) );
OA22X1TS U9089 ( .A0(n8443), .A1(final_result_ieee[62]), .B0(
exp_oper_result[10]), .B1(n8442), .Y(n289) );
CMPR42X1TS U9090 ( .A(mult_x_24_n1087), .B(mult_x_24_n703), .C(
mult_x_24_n1428), .D(mult_x_24_n1401), .ICI(mult_x_24_n700), .S(
mult_x_24_n698), .ICO(mult_x_24_n696), .CO(mult_x_24_n697) );
initial $sdf_annotate("FPU_Multiplication_Function_ASIC_fpu_syn_constraints_clk10.tcl_KOA_2STAGE_syn.sdf");
endmodule
|
`timescale 1 ns / 1 ps
module axis_scaler #
(
parameter integer AXIS_TDATA_WIDTH = 14
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire signed [AXIS_TDATA_WIDTH-1:0] cfg_data,
// Slave side
input wire signed [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
output wire s_axis_tready,
// Master side
input wire m_axis_tready,
output wire signed [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid
);
reg signed [AXIS_TDATA_WIDTH-1:0] s_axis_tdata_reg,s_axis_tdata_next;
reg [AXIS_TDATA_WIDTH*2-1:0] int_data_reg, int_data_next;
wire multiply = s_axis_tvalid & m_axis_tready;
always @(posedge aclk)
begin
if(~aresetn)
begin
s_axis_tdata_reg <= 0;
s_axis_tdata_next <= 0;
int_data_reg <= 0;
int_data_next <= 0;
end
else
begin
if(multiply)
begin
s_axis_tdata_reg <= s_axis_tdata;
s_axis_tdata_next <= s_axis_tdata_reg;
int_data_reg <= s_axis_tdata_next*cfg_data;
int_data_next <= int_data_reg;
end
end
end
assign s_axis_tready = m_axis_tready;
assign m_axis_tvalid = s_axis_tvalid;
//scales down relative to 2^(AXIS_TDATA_WIDTH-2), e.g. cfg=4096 for 14 bit equals scale of 1
assign m_axis_tdata = int_data_next[AXIS_TDATA_WIDTH*2-3:AXIS_TDATA_WIDTH-2];
endmodule
|
/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
This version has been modified with SPI mode support. Changes are:
Copyright 2017, Micah Elizabeth Scott, licensed under identical terms.
*/
module sd_link (
input wire clk_50,
input wire reset_n,
output wire [3:0] link_card_state,
input wire [47:0] phy_cmd_in,
input wire phy_cmd_in_crc_good,
input wire phy_cmd_in_act,
input wire phy_spi_sel,
output reg phy_data_in_act,
input wire phy_data_in_busy,
output reg phy_data_in_stop,
output reg phy_data_in_another,
input wire phy_data_in_done,
input wire phy_data_in_crc_good,
output reg [135:0] phy_resp_out,
output reg [3:0] phy_resp_type,
output reg phy_resp_busy,
output reg phy_resp_act,
input wire phy_resp_done,
output reg phy_mode_4bit,
output reg phy_mode_spi,
output reg phy_mode_crc_disable,
output reg [511:0] phy_data_out_reg,
output reg phy_data_out_src,
output reg [9:0] phy_data_out_len,
input wire phy_data_out_busy,
output reg phy_data_out_act,
output reg phy_data_out_stop,
input wire phy_data_out_done,
output reg block_read_act,
input wire block_read_go,
output reg [31:0] block_read_addr,
output reg [31:0] block_read_byteaddr,
output reg [31:0] block_read_num,
output reg block_read_stop,
output reg block_write_act,
input wire block_write_done,
output reg [31:0] block_write_addr,
output reg [31:0] block_write_byteaddr,
output reg [31:0] block_write_num,
output reg [22:0] block_preerase_num,
output reg [31:0] block_erase_start,
output reg [31:0] block_erase_end,
input wire opt_enable_hs,
output reg [5:0] cmd_in_last,
output reg info_card_desel,
output reg err_op_out_range,
output reg err_unhandled_cmd,
output reg err_cmd_crc,
// Debug/status outputs
output reg host_hc_support,
output wire [5:0] cmd_in_cmd,
output reg [31:0] card_status,
output reg [15:0] dc,
output reg [15:0] ddc,
output reg [6:0] state
);
`include "sd_params.vh"
`include "sd_const.vh"
reg [47:0] cmd_in_latch;
// wire [5:0] cmd_in_cmd = cmd_in_latch[45:40] /* synthesis noprune */;
assign cmd_in_cmd = cmd_in_latch[45:40];
wire [31:0] cmd_in_arg = cmd_in_latch[39:8] /* synthesis noprune */;
wire [6:0] cmd_in_crc = cmd_in_latch[7:1];
// High capacity mode uses blocks natively, legacy mode byte offsets are converted here
wire [31:0] cmd_in_arg_blockaddr = host_hc_support ? cmd_in_arg : { 9'b0, cmd_in_arg[31:9] };
wire [31:0] cmd_in_arg_byteaddr = host_hc_support ? { cmd_in_arg[22:0], 9'b0 } : cmd_in_arg;
reg [3:0] card_state;
assign link_card_state = card_state;
reg [3:0] card_state_next;
reg [2:0] card_erase_state;
reg card_appcmd;
reg [127:0] card_sd_status;
reg [127:0] card_csd;
reg [127:0] card_cid;
reg [31:0] card_ocr;
reg [15:0] card_rca;
reg [63:0] card_scr;
reg [111:0] card_function_caps;
reg [23:0] card_function;
reg [23:0] card_function_check;
reg [31:0] card_blocks_written;
reg [127:0] resp_arg; // for 32 or 128bit
reg [3:0] resp_type;
parameter [6:0] ST_RESET = 'd0,
ST_IDLE = 'd4,
ST_CMD_ACT = 'd8,
ST_CMD_RESP_0 = 'd9,
ST_CMD_RESP_1 = 'd10,
ST_CMD_RESP_2 = 'd11,
ST_LAST = 'd127;
reg [6:0] data_state;
parameter [6:0] DST_RESET = 'd0,
DST_IDLE = 'd1,
DST_IDLE_1 = 'd2,
DST_DATA_OUT_0 = 'd10,
DST_DATA_OUT_1 = 'd11,
DST_DATA_OUT_2 = 'd12,
DST_DATA_OUT_3 = 'd13,
DST_DATA_OUT_4 = 'd14,
DST_DATA_OUT_5 = 'd15,
DST_DATA_IN_0 = 'd20,
DST_DATA_IN_1 = 'd21,
DST_DATA_IN_2 = 'd22,
DST_DATA_IN_3 = 'd23,
DST_DATA_IN_4 = 'd24,
DST_DATA_IN_5 = 'd25,
DST_LAST = 'd127;
wire [15:0] spi_status_word = {
// R1
1'b0,
card_status[STAT_ADDRESS_ERROR] | card_status[STAT_BLOCK_LEN_ERROR] | card_status[STAT_ERASE_PARAM],
card_status[STAT_ADDRESS_ERROR],
card_status[STAT_ERASE_SEQ_ERROR],
card_status[STAT_COM_CRC_ERROR],
card_status[STAT_ILLEGAL_COMMAND],
card_status[STAT_ERASE_RESET],
card_state == CARD_IDLE,
// R2
card_status[STAT_OUT_OF_RANGE] | card_status[STAT_CSD_OVERWRITE],
card_status[STAT_ERASE_PARAM],
card_status[STAT_WP_VIOLATION],
card_status[STAT_CARD_ECC_FAILED],
card_status[STAT_CC_ERROR],
card_status[STAT_ERROR],
card_status[STAT_WP_ERASE_SKIP] | card_status[STAT_LOCK_UNLOCK_FAILED],
card_status[STAT_CARD_IS_LOCKED]
};
reg data_op_send_scr;
reg data_op_send_cid;
reg data_op_send_csd;
reg data_op_send_sdstatus;
reg data_op_send_function;
reg data_op_send_written;
reg data_op_send_block;
reg data_op_send_block_queue;
reg data_op_recv_block;
// synchronizers
wire reset_s;
wire [47:0] cmd_in_s;
wire cmd_in_crc_good_s;
wire cmd_in_act_s, cmd_in_act_r;
wire spi_sel_s;
wire data_in_busy_s;
wire data_in_done_s, data_in_done_r;
wire data_in_crc_good_s;
wire resp_done_s, resp_done_r;
wire data_out_busy_s;
wire data_out_done_s, data_out_done_r;
synch_3 a(reset_n, reset_s, clk_50);
synch_3 #(48) b(phy_cmd_in, cmd_in_s, clk_50);
synch_3 c(phy_cmd_in_crc_good, cmd_in_crc_good_s, clk_50);
synch_3r d(phy_cmd_in_act, cmd_in_act_s, clk_50, cmd_in_act_r);
synch_3 e(phy_data_in_busy, data_in_busy_s, clk_50);
synch_3r f(phy_data_in_done, data_in_done_s, clk_50, data_in_done_r);
synch_3 g(phy_data_in_crc_good, data_in_crc_good_s, clk_50);
synch_3r h(phy_resp_done, resp_done_s, clk_50, resp_done_r);
synch_3 i(phy_data_out_busy, data_out_busy_s, clk_50);
synch_3r j(phy_data_out_done, data_out_done_s, clk_50, data_out_done_r);
synch_3 k(phy_spi_sel, spi_sel_s, clk_50);
always @(posedge clk_50) begin
// free running counter
dc <= dc + 1'b1;
case(state)
ST_RESET: begin
dc <= 0;
info_card_desel <= 0;
err_op_out_range <= 0;
err_unhandled_cmd <= 0;
err_cmd_crc <= 0;
card_erase_state <= 0;
card_blocks_written <= 0;
card_appcmd <= 0;
card_rca <= 16'h0;
card_status <= 0;
card_status[STAT_READY_FOR_DATA] <= 1'b1;
card_state <= CARD_IDLE;
card_ocr <= {8'b01000000, OCR_VOLTAGE_WINDOW}; // high capacity, not powered up
card_cid <= {CID_FIELD_MID, CID_FIELD_OID, CID_FIELD_PNM, CID_FIELD_PRV, CID_FIELD_PSN,
4'b0, CID_FIELD_MDT, 8'hFF};
card_csd <= {CSD_CSD_STRUCTURE, 6'h0, CSD_TAAC, CSD_NSAC, CSD_TRAN_SPEED_25, CSD_CCC, CSD_READ_BL_LEN,
CSD_READ_BL_PARTIAL, CSD_WRITE_BLK_MISALIGN, CSD_READ_BLK_MISALIGN, CSD_DSR_IMPL, 6'h0,
CSD_C_SIZE, 1'b0, CSD_ERASE_BLK_EN, CSD_SECTOR_SIZE, CSD_WP_GRP_SIZE, CSD_WP_GRP_ENABLE,
2'b00, CSD_R2W_FACTOR, CSD_WRITE_BL_LEN, CSD_WRITE_BL_PARTIAL, 5'h0, CSD_FILE_FORMAT_GRP,
CSD_COPY, CSD_PERM_WRITE_PROTECT, CSD_TMP_WRITE_PROTECT, CSD_FILE_FORMAT, 2'h0, 8'hFF};
card_scr <= {SCR_SCR_STRUCTURE, SCR_SD_SPEC, SCR_DATA_STATE_ERASE, SCR_SD_SECURITY, SCR_SD_BUS_WIDTHS,
SCR_SD_SPEC3, 13'h0, 2'h0, 32'h0};
card_sd_status <= { STAT_DAT_BUS_WIDTH_1, STAT_SECURED_MODE, 7'h0, 6'h0, STAT_SD_CARD_TYPE,
STAT_SIZE_OF_PROT_AREA, STAT_SPEED_CLASS, STAT_PERFORMANCE_MOVE, STAT_AU_SIZE,
4'h0, STAT_ERASE_SIZE, STAT_ERASE_TIMEOUT, STAT_ERASE_OFFSET, 15'h0};
// set high speed capability bit
card_function_caps <= 112'h0032800180018001800180018001 | opt_enable_hs ? 2'b10 : 2'b00;
card_function <= 24'h0;
card_function_check <= 24'h0;
data_op_send_scr <= 0;
data_op_send_cid <= 0;
data_op_send_csd <= 0;
data_op_send_sdstatus <= 0;
data_op_send_function <= 0;
data_op_send_written <= 0;
data_op_send_block <= 0;
data_op_send_block_queue <= 0;
data_op_recv_block <= 0;
phy_data_in_act <= 0;
phy_data_in_stop <= 0;
phy_resp_act <= 0;
phy_data_out_act <= 0;
phy_data_out_stop <= 0;
phy_mode_4bit <= 0;
phy_mode_crc_disable <= phy_mode_spi;
block_read_act <= 0;
block_read_num <= 0;
block_read_stop <= 0;
block_write_act <= 0;
block_write_num <= 0;
block_preerase_num <= 0;
// By default the host doesn't support high capacity mode
host_hc_support <= 0;
// In SPI mode, reset gets an R1 response
state <= phy_mode_spi ? ST_CMD_RESP_0 : ST_IDLE;
end
ST_IDLE: begin
// rising edge + crc is good
if(cmd_in_act_r) begin
phy_resp_act <= 0;
if(cmd_in_crc_good_s) begin
// new command
cmd_in_latch <= phy_cmd_in;
card_status[STAT_COM_CRC_ERROR] <= 0;
card_status[STAT_ILLEGAL_COMMAND] <= 0;
state <= ST_CMD_ACT;
cmd_in_last <= cmd_in_cmd;
end else begin
// bad crc
err_cmd_crc <= 1;
card_status[STAT_COM_CRC_ERROR] <= 1;
end
end
end
ST_CMD_ACT: begin
// parse the command
state <= ST_CMD_RESP_0;
// unless otherwise, stay in the same SD state
card_state_next <= card_state;
// unless set below, assume it's illegal
resp_type <= RESP_BAD;
if(~card_appcmd) begin
// CMD
case(cmd_in_cmd)
CMD0_GO_IDLE: begin
if(card_state != CARD_INA) begin
// reset to default, optionally enter SPI mode.
state <= ST_RESET;
data_state <= DST_RESET;
if (phy_mode_spi | spi_sel_s) begin
phy_mode_spi <= 1'b1;
resp_type <= RESP_R1;
end
else begin
resp_type <= RESP_NONE;
end
end
end
CMD1_SEND_OP_COND: begin
if (card_state == CARD_IDLE || phy_mode_spi) begin
resp_type <= RESP_R1;
host_hc_support <= cmd_in_arg[30];
end
end
CMD2_ALL_SEND_CID: begin
if (card_state == CARD_READY || phy_mode_spi) begin
resp_type <= RESP_R2;
card_state_next <= CARD_IDENT;
end
end
CMD3_SEND_REL_ADDR : case(card_state)
CARD_IDENT, CARD_STBY: begin
card_rca <= card_rca + 16'h1337;
resp_type <= RESP_R6;
card_state_next <= CARD_STBY;
end
endcase
//CMD4_SET_DSR: begin
//end
CMD6_SWITCH_FUNC: begin
case(card_state)
CARD_TRAN: begin
case(cmd_in_arg[23:20])
4'h0, 4'hF: card_function_check[23:20] <= 4'h0; // valid
default: card_function_check[23:20] <= 4'hF; // invalid
endcase
case(cmd_in_arg[19:16])
4'h0, 4'hF: card_function_check[19:16] <= 4'h0; // valid
default: card_function_check[19:16] <= 4'hF; // invalid
endcase
case(cmd_in_arg[15:12])
4'h0, 4'hF: card_function_check[15:12] <= 4'h0; // valid
default: card_function_check[15:12] <= 4'hF; // invalid
endcase
case(cmd_in_arg[11:8])
4'h0, 4'hF: card_function_check[11:8] <= 4'h0; // valid
default: card_function_check[11:8] <= 4'hF; // invalid
endcase
case(cmd_in_arg[7:4])
4'h0, 4'hF: card_function_check[7:4] <= 4'h0; // valid
default: card_function_check[7:4] <= 4'hF; // invalid
endcase
case(cmd_in_arg[3:0])
4'h0: card_function_check[3:0] <= 4'h0;
4'hF: card_function_check[3:0] <= card_function[3:0];
4'h1: begin
card_function_check[3:0] <= 4'h1; // high speed enable
if(cmd_in_arg[31]) card_function[3:0] <= 4'h1;
end
default: card_function_check[3:0] <= 4'hF; // invalid
endcase
resp_type <= RESP_R1;
card_state_next <= CARD_DATA;
data_op_send_function <= 1;
end
endcase
end
CMD7_SEL_CARD: begin
if(cmd_in_arg[31:16] == card_rca) begin
// select
resp_type <= RESP_R1B;
case(card_state)
CARD_STBY: card_state_next <= CARD_TRAN;
//CARD_DIS: card_state_next <= CARD_PRG;
CARD_DIS: card_state_next <= CARD_TRAN;
default: resp_type <= RESP_BAD;
endcase
end else begin
// deselected
case(card_state)
CARD_STBY: card_state_next <= CARD_STBY;
CARD_TRAN: card_state_next <= CARD_STBY;
CARD_DATA: card_state_next <= CARD_STBY;
CARD_PRG: card_state_next <= CARD_DIS;
//default: resp_type <= RESP_BAD;
endcase
info_card_desel <= 1;
resp_type <= RESP_NONE;
end
end
CMD8_SEND_IF_COND: begin
if ( ((card_state == CARD_IDLE) & (cmd_in_arg[11:8] == 4'b0001))
| phy_mode_spi ) begin
resp_type <= RESP_R7;
resp_arg <= {20'h0, 4'b0001, cmd_in_arg[7:0]};
end else resp_type <= RESP_NONE;
end
CMD9_SEND_CSD: begin
if(cmd_in_arg[31:16] == card_rca) begin
case(card_state)
CARD_STBY: begin
resp_type <= RESP_R2;
end
endcase
end else resp_type <= RESP_NONE;
if(phy_mode_spi) begin
resp_type <= RESP_R1;
data_op_send_csd <= 1;
end
end
CMD10_SEND_CID: begin
if(cmd_in_arg[31:16] == card_rca) begin
case(card_state)
CARD_STBY: begin
resp_type <= RESP_R2;
end
endcase
end else resp_type <= RESP_NONE;
if(phy_mode_spi) begin
resp_type <= RESP_R1;
data_op_send_cid <= 1;
end
end
CMD12_STOP: case(card_state)
// N.B. should not be allowed in PRG state, but readers do anyway
CARD_DATA, CARD_RCV, CARD_PRG: begin
resp_type <= RESP_R1B;
if(card_state == CARD_DATA) card_state_next <= CARD_TRAN;
// PRG > TRAN transition is handled by the data states below
if(card_state == CARD_RCV) card_state_next <= CARD_TRAN;
if(card_state == CARD_PRG) card_state_next <= CARD_TRAN;
phy_data_in_stop <= 1;
phy_data_out_stop <= 1;
end
endcase
CMD13_SEND_STATUS: begin
if(cmd_in_arg[31:16] == card_rca) begin
case(card_state)
CARD_STBY, CARD_TRAN, CARD_DATA, CARD_RCV, CARD_PRG, CARD_DIS: begin
resp_type <= RESP_R1;
end
endcase
end else resp_type <= RESP_NONE;
if(phy_mode_spi) begin
resp_type <= RESP_R2;
end
end
CMD15_GO_INACTIVE: begin
if(cmd_in_arg[31:16] == card_rca) begin
case(card_state)
CARD_STBY, CARD_TRAN, CARD_DATA, CARD_RCV, CARD_PRG, CARD_DIS: begin
card_state_next <= CARD_INA;
resp_type <= RESP_NONE;
end
endcase
end else resp_type <= RESP_NONE;
end
CMD16_SET_BLOCKLEN: begin
if (card_state == CARD_TRAN || phy_mode_spi) begin
resp_type <= RESP_R1;
if(cmd_in_arg > 512) card_status[STAT_BLOCK_LEN_ERROR] <= 1;
end
end
CMD17_READ_SINGLE: begin
if (card_state == CARD_TRAN || phy_mode_spi) begin
if(cmd_in_arg_blockaddr >= SD_TOTAL_BLOCKS) begin
card_status[STAT_OUT_OF_RANGE] <= 1'b1; err_op_out_range <= 1;
end else begin
resp_type <= RESP_R1;
block_read_addr <= cmd_in_arg_blockaddr;
block_read_byteaddr <= cmd_in_arg_byteaddr;
block_read_num <= 1;
data_op_send_block_queue <= 1;
card_state_next <= CARD_DATA;
end
end
end
CMD18_READ_MULTIPLE: begin
if (card_state == CARD_TRAN || phy_mode_spi) begin
if(cmd_in_arg_blockaddr >= SD_TOTAL_BLOCKS) begin
card_status[STAT_OUT_OF_RANGE] <= 1'b1; err_op_out_range <= 1;
end else begin
resp_type <= RESP_R1;
block_read_addr <= cmd_in_arg_blockaddr;
block_read_byteaddr <= cmd_in_arg_byteaddr;
block_read_num <= 32'hFFFFFFFF;
data_op_send_block_queue <= 1;
card_state_next <= CARD_DATA;
end
end
end
CMD24_WRITE_SINGLE: begin
if (card_state == CARD_TRAN || phy_mode_spi) begin
if(cmd_in_arg_blockaddr >= SD_TOTAL_BLOCKS) begin
card_status[STAT_OUT_OF_RANGE] <= 1'b1; err_op_out_range <= 1;
end else begin
resp_type <= RESP_R1;
block_write_addr <= cmd_in_arg_blockaddr;
block_write_byteaddr <= cmd_in_arg_byteaddr;
block_write_num <= 1;
card_blocks_written <= 0;
data_op_recv_block <= 1;
card_state_next <= CARD_RCV;
end
end
end
CMD25_WRITE_MULTIPLE: begin
if (card_state == CARD_TRAN || phy_mode_spi) begin
if(cmd_in_arg_blockaddr >= SD_TOTAL_BLOCKS) begin
card_status[STAT_OUT_OF_RANGE] <= 1'b1; err_op_out_range <= 1;
end else begin
resp_type <= RESP_R1;
block_write_addr <= cmd_in_arg_blockaddr;
block_write_byteaddr <= cmd_in_arg_byteaddr;
block_write_num <= 32'hFFFFFFFF;
card_blocks_written <= 0;
data_op_recv_block <= 1;
card_state_next <= CARD_RCV;
end
end
end
//CMD27_PROGRAM_CSD: begin
//end
CMD32_ERASE_START: begin
if (card_state == CARD_TRAN || phy_mode_spi) begin
resp_type <= RESP_R1;
card_erase_state <= 0;
if(card_erase_state == 0) begin
block_erase_start <= cmd_in_arg_blockaddr;
card_erase_state <= 1;
end else card_status[STAT_ERASE_SEQ_ERROR] <= 1'b1;
end
end
CMD33_ERASE_END: begin
if (card_state == CARD_TRAN || phy_mode_spi) begin
resp_type <= RESP_R1;
card_erase_state <= 0;
if(card_erase_state == 1) begin
block_erase_end <= cmd_in_arg_blockaddr;
card_erase_state <= 2;
end else card_status[STAT_ERASE_SEQ_ERROR] <= 1'b1;
end
end
CMD38_ERASE: begin
if (card_state == CARD_TRAN || phy_mode_spi) begin
resp_type <= RESP_R1B;
card_erase_state <= 0;
if(card_erase_state == 2) begin
// process erase
end else card_status[STAT_ERASE_SEQ_ERROR] <= 1'b1;
// since erase are unimpl they happen immediately
//card_state_next <= CARD_PRG;
end
end
//CMD42_LOCK_UNLOCK: begin
//end
CMD55_APP_CMD: begin
if(cmd_in_arg[31:16] == card_rca) begin
case(card_state)
CARD_IDLE, CARD_STBY, CARD_TRAN, CARD_DATA, CARD_RCV, CARD_PRG, CARD_DIS: begin
resp_type <= RESP_R1;
card_appcmd <= 1;
card_status[STAT_APP_CMD] <= 1;
end
endcase
end else resp_type <= RESP_NONE;
if(phy_mode_spi) begin
resp_type <= RESP_R1;
card_appcmd <= 1;
card_status[STAT_APP_CMD] <= 1;
end
end
//CMD56_GEN_CMD: begin
//end
CMD58_READ_OCR: begin
resp_type <= RESP_R3;
end
CMD59_CRC_ON_OFF: begin
phy_mode_crc_disable <= ~cmd_in_arg[0];
resp_type <= RESP_R1;
end
default: begin
err_unhandled_cmd <= 1;
if(cmd_in_cmd == 6'd1) err_unhandled_cmd <= 0; // CMD1 for SPI cards
if(cmd_in_cmd == 6'd5) err_unhandled_cmd <= 0; // CMD5 for SDIO combo cards
end
endcase
// check for illegal commands during an expected erase sequence
if(card_erase_state > 0) begin
if( cmd_in_cmd != CMD13_SEND_STATUS &&
cmd_in_cmd != CMD33_ERASE_END &&
cmd_in_cmd != CMD38_ERASE) begin
card_erase_state <= 0;
card_status[STAT_ERASE_RESET] <= 1;
end
end
end else begin
// ACMD
case(cmd_in_cmd)
ACMD6_SET_BUS_WIDTH: begin
if (card_state == CARD_TRAN || phy_mode_spi) begin
resp_type <= RESP_R1;
phy_mode_4bit <= cmd_in_arg[1];
end
end
ACMD13_SD_STATUS: begin
if (card_state == CARD_TRAN || phy_mode_spi) begin
resp_type <= RESP_R1;
// send SD status
data_op_send_sdstatus <= 1;
card_state_next <= CARD_DATA;
end
end
ACMD22_NUM_WR_BLK: begin
if (card_state == CARD_TRAN || phy_mode_spi) begin
resp_type <= RESP_R1;
// send number blocks written
data_op_send_written <= 1;
card_state_next <= CARD_DATA;
end
end
ACMD23_SET_WR_BLK: begin
if (card_state == CARD_TRAN || phy_mode_spi) begin
resp_type <= RESP_R1;
block_preerase_num[22:0] <= cmd_in_arg[22:0];
end
end
ACMD41_SEND_OP_COND: begin
if (card_state == CARD_IDLE || phy_mode_spi) begin
resp_type <= RESP_R3;
card_ocr[OCR_POWERED_UP] <= 1;
card_state_next <= CARD_READY;
host_hc_support <= cmd_in_arg[30];
end
end
ACMD42_SET_CARD_DET: begin
if (card_state == CARD_TRAN || phy_mode_spi) begin
resp_type <= RESP_R1;
end
end
ACMD51_SEND_SCR: begin
if (card_state == CARD_TRAN || phy_mode_spi) begin
resp_type <= RESP_R1;
// send SCR
data_op_send_scr <= 1;
card_state_next <= CARD_DATA;
end
end
default: begin
// retry this as a regular CMD (retry this state with APPCMD=0)
state <= ST_CMD_ACT;
card_appcmd <= 0;
//err_unhandled_cmd <= 1;
end
endcase
end
end
ST_CMD_RESP_0: begin
// update status register and such
card_status[12:9] <= card_state;
state <= ST_CMD_RESP_1;
end
ST_CMD_RESP_1: begin
// send response
state <= ST_CMD_RESP_2;
phy_resp_type <= resp_type;
phy_resp_busy <= 0;
case(resp_type)
RESP_NONE: begin
// don't send a response
card_state <= card_state_next;
state <= ST_IDLE;
end
RESP_BAD: begin
card_status[STAT_ILLEGAL_COMMAND] <= 1;
if (phy_mode_spi) begin
// SPI mode; R1 response with 'illegal command' bit already set
phy_resp_out <= {spi_status_word[15:11], 1'b1, spi_status_word[9:8], 128'h0};
end
else begin
// SD mode
state <= ST_IDLE;
end
end
RESP_R1, RESP_R1B: begin
phy_resp_out <= phy_mode_spi ?
{spi_status_word[15:8], 128'h0} :
{2'b00, cmd_in_cmd, card_status, 8'h1, 88'h0};
end
RESP_R2: begin
phy_resp_out <= phy_mode_spi ?
{spi_status_word[15:0], 120'h0} :
{2'b00, 6'b111111, cmd_in_cmd == CMD9_SEND_CSD ? card_csd[127:1] : card_cid[127:1], 1'b1};
end
RESP_R3: begin
phy_resp_out <= phy_mode_spi ?
{spi_status_word[15:8], card_ocr, 96'h0 } :
{2'b00, 6'b111111, card_ocr, 8'hFF, 88'h0};
end
RESP_R6: begin
phy_resp_out <= {2'b00, 6'b000011, card_rca, {card_status[23:22], card_status[19], card_status[12:0]}, 8'h1, 88'h0};
end
RESP_R7: begin
phy_resp_out <= phy_mode_spi ?
{spi_status_word[15:8], resp_arg[31:0], 96'h0} :
{2'b00, 6'b001000, resp_arg[31:0], 8'h1, 88'h0};
end
endcase
end
ST_CMD_RESP_2: begin
phy_resp_act <= 1;
if(resp_done_r) begin
// rising edge, phy is done sending response
phy_resp_act <= 0;
// clear APP_CMD after ACMD response sent
if(card_appcmd && (cmd_in_cmd != CMD55_APP_CMD)) begin
card_appcmd <= 0;
card_status[STAT_APP_CMD] <= 0; // not spec? but cards do it
end
case(cmd_in_cmd)
CMD13_SEND_STATUS: begin
// clear all bits that are Clear-On-Read
card_status[STAT_OUT_OF_RANGE] <= 0;
card_status[STAT_ADDRESS_ERROR] <= 0;
card_status[STAT_BLOCK_LEN_ERROR] <= 0;
card_status[STAT_ERASE_SEQ_ERROR] <= 0;
card_status[STAT_ERASE_PARAM] <= 0;
card_status[STAT_WP_VIOLATION] <= 0;
card_status[STAT_LOCK_UNLOCK_FAILED] <= 0;
card_status[STAT_CARD_ECC_FAILED] <= 0;
card_status[STAT_CC_ERROR] <= 0;
card_status[STAT_CSD_OVERWRITE] <= 0;
card_status[STAT_WP_ERASE_SKIP] <= 0;
card_status[STAT_ERASE_RESET] <= 0;
card_status[STAT_APP_CMD] <= 0;
card_status[STAT_AKE_SEQ_ERROR] <= 0;
end
endcase
card_state <= card_state_next;
state <= ST_IDLE;
// Clear bits for SPI status responses
if (phy_mode_spi) begin
// R1
card_status[STAT_BLOCK_LEN_ERROR] <= 0;
card_status[STAT_ADDRESS_ERROR] <= 0;
card_status[STAT_ERASE_SEQ_ERROR] <= 0;
card_status[STAT_COM_CRC_ERROR] <= 0;
card_status[STAT_ILLEGAL_COMMAND] <= 0;
card_status[STAT_ERASE_RESET] <= 0;
// R2
if (phy_resp_type == RESP_R2) begin
card_status[STAT_OUT_OF_RANGE] <= 0;
card_status[STAT_CSD_OVERWRITE] <= 0;
card_status[STAT_ERASE_PARAM] <= 0;
card_status[STAT_WP_VIOLATION] <= 0;
card_status[STAT_CARD_ECC_FAILED] <= 0;
card_status[STAT_CC_ERROR] <= 0;
card_status[STAT_ERROR] <= 0;
card_status[STAT_WP_ERASE_SKIP] <= 0;
card_status[STAT_LOCK_UNLOCK_FAILED] <= 0;
card_status[STAT_CARD_IS_LOCKED] <= 0;
end
end
end
end
endcase
// data FSM
// must be separate so that data packets can be transferred
// and commands still sent/responsed
//
// free running counter
ddc <= ddc + 1'b1;
case(data_state)
DST_RESET: begin
phy_data_out_act <= 0;
data_state <= DST_IDLE;
end
DST_IDLE: begin
card_status[STAT_READY_FOR_DATA] <= 1'b1;
if(data_op_recv_block) begin
// for data receive ops
data_state <= DST_DATA_IN_0;
end else
if( data_op_send_scr | data_op_send_sdstatus | data_op_send_cid | data_op_send_csd |
data_op_send_function | data_op_send_written | data_op_send_block_queue ) begin
// move to next state once response is processing
// to prevent false starts
if(~resp_done_s) begin
data_state <= DST_IDLE_1;
// queue block read, so that it can be accepted after a much-delayed read cycle
if(data_op_send_block_queue) begin
//card_state <= CARD_DATA;
data_op_send_block_queue <= 0;
data_op_send_block <= 1;
end
end
end
end
DST_IDLE_1: begin
ddc <= 0;
// process these data ops while response starts to send
if( data_op_send_scr | data_op_send_sdstatus | data_op_send_cid | data_op_send_csd |
data_op_send_function | data_op_send_written | data_op_send_block ) begin
phy_data_out_src <= 1; // default: send from register
data_state <= DST_DATA_OUT_0;
if(data_op_send_scr) begin
data_op_send_scr <= 0;
phy_data_out_len <= 8;
phy_data_out_reg <= {card_scr, 448'h0};
end else
if(data_op_send_sdstatus) begin
data_op_send_sdstatus <= 0;
phy_data_out_len <= 64;
phy_data_out_reg <= {card_sd_status, 384'h0};
end else
if(data_op_send_function) begin
data_op_send_function <= 0;
phy_data_out_len <= 64;
phy_data_out_reg <= {card_function_caps, card_function_check, 376'h0};
end else
if(data_op_send_written) begin
data_op_send_written <= 0;
phy_data_out_len <= 4;
phy_data_out_reg <= {card_blocks_written, 480'h0};
end else
if(data_op_send_block) begin
phy_data_out_src <= 0; // send data from bram
phy_data_out_len <= 512;
data_state <= DST_DATA_OUT_5;
end
if(data_op_send_cid) begin
data_op_send_cid <= 0;
phy_data_out_len <= 16;
phy_data_out_reg <= {card_cid, 384'h0};
end
if(data_op_send_csd) begin
data_op_send_csd <= 0;
phy_data_out_len <= 16;
phy_data_out_reg <= {card_csd, 384'h0};
end
end
end
DST_DATA_OUT_5: begin
// make sure MGR cleared from any previous ops
if(~block_read_go) begin
block_read_stop <= 0;
data_state <= DST_DATA_OUT_3;
end
end
DST_DATA_OUT_3: begin
// external bram op:
// wait for bram contents to be valid
block_read_act <= 1;
if(block_read_go) begin
// ready
block_read_act <= 0;
data_state <= DST_DATA_OUT_0;
end
end
DST_DATA_OUT_0: begin
// wait to send data until response was sent
if(resp_done_s) begin
phy_data_out_act <= 1;
data_state <= DST_DATA_OUT_1;
end
end
DST_DATA_OUT_1: begin
if(data_out_done_r) begin
// rising edge, phy is done sending data
phy_data_out_act <= 0;
// did link detect a stop command?
if(phy_data_out_stop) begin
phy_data_in_stop <= 0;
phy_data_out_stop <= 0;
data_op_send_block <= 0;
end
// tell upper level we're done
block_read_stop <= 1;
data_state <= DST_DATA_OUT_4;
end
end
DST_DATA_OUT_4: begin
// wait for SD_MGR to finish
if(~block_read_go) data_state <= DST_DATA_OUT_2;
// link detected stop while we're waiting
if(phy_data_out_stop) begin
phy_data_in_stop <= 0;
phy_data_out_stop <= 0;
data_op_send_block <= 0;
block_read_stop <= 1;
data_state <= DST_DATA_OUT_2;
end
end
DST_DATA_OUT_2: begin
// wait until phy de-asserts busy so that it can detect another rising edge
// due to clocking differences
if(~data_out_busy_s) begin
//block_read_stop <= 0;
// fall back to TRAN state
card_state <= CARD_TRAN;
data_state <= DST_IDLE;
// don't wait around for a response to be sent if more blocks are to be done
if(data_op_send_block) begin
if(block_read_num == 1) begin
data_op_send_block <= 0;
end else begin
// stay in current state
// advance block count
card_state <= card_state;
block_read_addr <= block_read_addr + 1'b1;
block_read_num <= block_read_num - 1'b1;
block_read_byteaddr <= block_read_byteaddr + 512;
if(block_read_addr >= SD_TOTAL_BLOCKS) begin
card_status[STAT_OUT_OF_RANGE] <= 1'b1;
err_op_out_range <= 1;
end
data_state <= DST_IDLE_1;
end
end
end
end
DST_DATA_IN_0: begin
// signal to PHY that we are expecting a data packet
phy_data_in_act <= 1;
if(data_in_done_r) begin
card_status[STAT_READY_FOR_DATA] <= 1'b0;
data_state <= DST_DATA_IN_1;
end
if(phy_data_in_stop) begin
phy_data_in_act <= 0;
card_state <= CARD_TRAN;
data_state <= DST_DATA_IN_2;
end
end
DST_DATA_IN_1: begin
if(~data_in_crc_good_s) begin
// bad CRC, don't commit
// expect host to re-send entire CMD24/25 sequence
phy_data_in_act <= 0;
data_op_recv_block <= 0;
card_state <= CARD_TRAN;
data_state <= DST_IDLE;
end else begin
// tell mgr/ext there is data to be written
block_write_act <= 1;
card_state <= CARD_PRG;
// mgr/ext has finished
if(block_write_done) begin
// tell PHY to let go of the busy signal on DAT0
card_state <= CARD_RCV;
phy_data_in_act <= 0;
block_write_act <= 0;
data_state <= DST_DATA_IN_2;
end
end
end
DST_DATA_IN_2: begin
// wait until PHY is able to detect new ACT
// or if it's a burst write, just go ahead anyway
if(~data_in_busy_s | (phy_data_in_another & ~phy_data_in_stop)) begin
data_state <= DST_DATA_IN_3;
end
phy_data_in_another <= block_write_num > 1;
//phy_data_in_stop <= 1;
end
DST_DATA_IN_3: begin
card_blocks_written <= card_blocks_written + 1'b1;
if(block_write_num == 1 || phy_data_in_stop) begin
// last block, or it was CMD12'd
card_state <= CARD_TRAN;
phy_data_in_stop <= 0;
phy_data_out_stop <= 0;
phy_data_in_another <= 0;
data_op_recv_block <= 0;
data_state <= DST_IDLE;
end else begin
// more blocks to go
card_state <= CARD_RCV;
card_status[STAT_READY_FOR_DATA] <= 1'b1;
block_write_addr <= block_write_addr + 1'b1;
block_write_num <= block_write_num - 1'b1;
block_write_byteaddr <= block_write_byteaddr + 512;
if(block_write_addr >= SD_TOTAL_BLOCKS) begin
card_status[STAT_OUT_OF_RANGE] <= 1'b1;
err_op_out_range <= 1;
end
data_state <= DST_DATA_IN_0;
end
end
endcase
if(~reset_s) begin
state <= ST_RESET;
data_state <= DST_RESET;
phy_mode_spi <= 0;
phy_mode_crc_disable <= 0;
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 20:17:00 09/05/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #3 Project
// Module Name: LED_Segment_Mapper
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: LED to Seven-Segment Display Mapper
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module LED_Segment_Mapper
(
// Control Signals
input LED_ENABLE_1,
input LED_ENABLE_2,
// LED Data Signals
input [15:0] LED_DATA_1,
input [15:0] LED_DATA_2,
// Output Signals
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
// System Signals
input CLK
);
//
// LED Output Registers
//
reg [15:0] led_out_reg;
initial
begin
led_out_reg = 16'hFFFF;
end
always @(posedge CLK)
begin
led_out_reg[ 0] <= ~( (LED_ENABLE_1 & LED_DATA_1[ 0]) | (LED_ENABLE_2 & LED_DATA_2[ 0]) );
led_out_reg[ 1] <= ~( (LED_ENABLE_1 & LED_DATA_1[ 1]) | (LED_ENABLE_2 & LED_DATA_2[ 1]) );
led_out_reg[ 2] <= ~( (LED_ENABLE_1 & LED_DATA_1[ 2]) | (LED_ENABLE_2 & LED_DATA_2[ 2]) );
led_out_reg[ 3] <= ~( (LED_ENABLE_1 & LED_DATA_1[ 3]) | (LED_ENABLE_2 & LED_DATA_2[ 3]) );
led_out_reg[ 4] <= ~( (LED_ENABLE_1 & LED_DATA_1[ 4]) | (LED_ENABLE_2 & LED_DATA_2[ 4]) );
led_out_reg[ 5] <= ~( (LED_ENABLE_1 & LED_DATA_1[ 5]) | (LED_ENABLE_2 & LED_DATA_2[ 5]) );
led_out_reg[ 6] <= ~( (LED_ENABLE_1 & LED_DATA_1[ 6]) | (LED_ENABLE_2 & LED_DATA_2[ 6]) );
led_out_reg[ 7] <= ~( (LED_ENABLE_1 & LED_DATA_1[ 7]) | (LED_ENABLE_2 & LED_DATA_2[ 7]) );
led_out_reg[ 8] <= ~( (LED_ENABLE_1 & LED_DATA_1[ 8]) | (LED_ENABLE_2 & LED_DATA_2[ 8]) );
led_out_reg[ 9] <= ~( (LED_ENABLE_1 & LED_DATA_1[ 9]) | (LED_ENABLE_2 & LED_DATA_2[ 9]) );
led_out_reg[10] <= ~( (LED_ENABLE_1 & LED_DATA_1[10]) | (LED_ENABLE_2 & LED_DATA_2[10]) );
led_out_reg[11] <= ~( (LED_ENABLE_1 & LED_DATA_1[11]) | (LED_ENABLE_2 & LED_DATA_2[11]) );
led_out_reg[12] <= ~( (LED_ENABLE_1 & LED_DATA_1[12]) | (LED_ENABLE_2 & LED_DATA_2[12]) );
led_out_reg[13] <= ~( (LED_ENABLE_1 & LED_DATA_1[13]) | (LED_ENABLE_2 & LED_DATA_2[13]) );
led_out_reg[14] <= ~( (LED_ENABLE_1 & LED_DATA_1[14]) | (LED_ENABLE_2 & LED_DATA_2[14]) );
led_out_reg[15] <= ~( (LED_ENABLE_1 & LED_DATA_1[15]) | (LED_ENABLE_2 & LED_DATA_2[15]) );
end
//
// 7-Segment Display Mapping
//
// Map the 16 LED Output Signals to the
// outer LED segments of the 7-Segment Display
//
assign HEX3[0] = led_out_reg[ 0];
assign HEX4[0] = led_out_reg[ 1];
assign HEX5[0] = led_out_reg[ 2];
assign HEX5[5] = led_out_reg[ 3];
assign HEX5[4] = led_out_reg[ 4];
assign HEX5[3] = led_out_reg[ 5];
assign HEX4[3] = led_out_reg[ 6];
assign HEX3[3] = led_out_reg[ 7];
assign HEX2[3] = led_out_reg[ 8];
assign HEX1[3] = led_out_reg[ 9];
assign HEX0[3] = led_out_reg[10];
assign HEX0[2] = led_out_reg[11];
assign HEX0[1] = led_out_reg[12];
assign HEX0[0] = led_out_reg[13];
assign HEX1[0] = led_out_reg[14];
assign HEX2[0] = led_out_reg[15];
//
// Unused Segment Assignments
//
// This segment LEDs will not be used to leave turned off.
// NOTE: The compiler will generate warnings about these signals
// begin tied to GND. Those warnings can be ignored.
//
assign HEX0[6:4] = ~3'h0;
assign HEX1[2:1] = ~2'h0;
assign HEX1[6:4] = ~3'h0;
assign HEX2[2:1] = ~2'h0;
assign HEX2[6:4] = ~3'h0;
assign HEX3[2:1] = ~2'h0;
assign HEX3[6:4] = ~3'h0;
assign HEX4[2:1] = ~2'h0;
assign HEX4[6:4] = ~3'h0;
assign HEX5[2:1] = ~2'h0;
assign HEX5[6] = ~1'b0;
endmodule
|
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 10G Ethernet PHY RX IF
*/
module eth_phy_10g_rx_if #
(
parameter DATA_WIDTH = 64,
parameter HDR_WIDTH = 2,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8,
parameter COUNT_125US = 125000/6.4
)
(
input wire clk,
input wire rst,
/*
* 10GBASE-R encoded interface
*/
output wire [DATA_WIDTH-1:0] encoded_rx_data,
output wire [HDR_WIDTH-1:0] encoded_rx_hdr,
/*
* SERDES interface
*/
input wire [DATA_WIDTH-1:0] serdes_rx_data,
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
/*
* Status
*/
output wire [6:0] rx_error_count,
output wire rx_block_lock,
output wire rx_high_ber,
/*
* Configuration
*/
input wire rx_prbs31_enable
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
wire [DATA_WIDTH-1:0] serdes_rx_data_rev, serdes_rx_data_int;
wire [HDR_WIDTH-1:0] serdes_rx_hdr_rev, serdes_rx_hdr_int;
generate
genvar n;
if (BIT_REVERSE) begin
for (n = 0; n < DATA_WIDTH; n = n + 1) begin
assign serdes_rx_data_rev[n] = serdes_rx_data[DATA_WIDTH-n-1];
end
for (n = 0; n < HDR_WIDTH; n = n + 1) begin
assign serdes_rx_hdr_rev[n] = serdes_rx_hdr[HDR_WIDTH-n-1];
end
end else begin
assign serdes_rx_data_rev = serdes_rx_data;
assign serdes_rx_hdr_rev = serdes_rx_hdr;
end
if (SERDES_PIPELINE > 0) begin
(* srl_style = "register" *)
reg [DATA_WIDTH-1:0] serdes_rx_data_pipe_reg[SERDES_PIPELINE-1:0];
(* srl_style = "register" *)
reg [HDR_WIDTH-1:0] serdes_rx_hdr_pipe_reg[SERDES_PIPELINE-1:0];
for (n = 0; n < SERDES_PIPELINE; n = n + 1) begin
initial begin
serdes_rx_data_pipe_reg[n] <= {DATA_WIDTH{1'b0}};
serdes_rx_hdr_pipe_reg[n] <= {HDR_WIDTH{1'b0}};
end
always @(posedge clk) begin
serdes_rx_data_pipe_reg[n] <= n == 0 ? serdes_rx_data_rev : serdes_rx_data_pipe_reg[n-1];
serdes_rx_hdr_pipe_reg[n] <= n == 0 ? serdes_rx_hdr_rev : serdes_rx_hdr_pipe_reg[n-1];
end
end
assign serdes_rx_data_int = serdes_rx_data_pipe_reg[SERDES_PIPELINE-1];
assign serdes_rx_hdr_int = serdes_rx_hdr_pipe_reg[SERDES_PIPELINE-1];
end else begin
assign serdes_rx_data_int = serdes_rx_data_rev;
assign serdes_rx_hdr_int = serdes_rx_hdr_rev;
end
endgenerate
wire [DATA_WIDTH-1:0] descrambled_rx_data;
reg [DATA_WIDTH-1:0] encoded_rx_data_reg = {DATA_WIDTH{1'b0}};
reg [HDR_WIDTH-1:0] encoded_rx_hdr_reg = {HDR_WIDTH{1'b0}};
reg [57:0] scrambler_state_reg = {58{1'b1}};
wire [57:0] scrambler_state;
reg [30:0] prbs31_state_reg = 31'h7fffffff;
wire [30:0] prbs31_state;
wire [DATA_WIDTH+HDR_WIDTH-1:0] prbs31_data;
reg [6:0] rx_error_count_reg = 0;
reg [5:0] rx_error_count_1_reg = 0;
reg [5:0] rx_error_count_2_reg = 0;
reg [5:0] rx_error_count_1_temp = 0;
reg [5:0] rx_error_count_2_temp = 0;
lfsr #(
.LFSR_WIDTH(58),
.LFSR_POLY(58'h8000000001),
.LFSR_CONFIG("FIBONACCI"),
.LFSR_FEED_FORWARD(1),
.REVERSE(1),
.DATA_WIDTH(DATA_WIDTH),
.STYLE("AUTO")
)
descrambler_inst (
.data_in(serdes_rx_data_int),
.state_in(scrambler_state_reg),
.data_out(descrambled_rx_data),
.state_out(scrambler_state)
);
lfsr #(
.LFSR_WIDTH(31),
.LFSR_POLY(31'h10000001),
.LFSR_CONFIG("FIBONACCI"),
.LFSR_FEED_FORWARD(1),
.REVERSE(1),
.DATA_WIDTH(DATA_WIDTH+HDR_WIDTH),
.STYLE("AUTO")
)
prbs31_check_inst (
.data_in(~{serdes_rx_data_int, serdes_rx_hdr_int}),
.state_in(prbs31_state_reg),
.data_out(prbs31_data),
.state_out(prbs31_state)
);
integer i;
always @* begin
rx_error_count_1_temp = 0;
rx_error_count_2_temp = 0;
for (i = 0; i < DATA_WIDTH+HDR_WIDTH; i = i + 1) begin
if (i & 1) begin
rx_error_count_1_temp = rx_error_count_1_temp + prbs31_data[i];
end else begin
rx_error_count_2_temp = rx_error_count_2_temp + prbs31_data[i];
end
end
end
always @(posedge clk) begin
scrambler_state_reg <= scrambler_state;
encoded_rx_data_reg <= SCRAMBLER_DISABLE ? serdes_rx_data_int : descrambled_rx_data;
encoded_rx_hdr_reg <= serdes_rx_hdr_int;
if (PRBS31_ENABLE && rx_prbs31_enable) begin
prbs31_state_reg <= prbs31_state;
rx_error_count_1_reg <= rx_error_count_1_temp;
rx_error_count_2_reg <= rx_error_count_2_temp;
rx_error_count_reg <= rx_error_count_1_reg + rx_error_count_2_reg;
end
end
assign encoded_rx_data = encoded_rx_data_reg;
assign encoded_rx_hdr = encoded_rx_hdr_reg;
assign rx_error_count = rx_error_count_reg;
wire serdes_rx_bitslip_int;
assign serdes_rx_bitslip = serdes_rx_bitslip_int && !(PRBS31_ENABLE && rx_prbs31_enable);
eth_phy_10g_rx_frame_sync #(
.HDR_WIDTH(HDR_WIDTH),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES)
)
eth_phy_10g_rx_frame_sync_inst (
.clk(clk),
.rst(rst),
.serdes_rx_hdr(serdes_rx_hdr_int),
.serdes_rx_bitslip(serdes_rx_bitslip_int),
.rx_block_lock(rx_block_lock)
);
eth_phy_10g_rx_ber_mon #(
.HDR_WIDTH(HDR_WIDTH),
.COUNT_125US(COUNT_125US)
)
eth_phy_10g_rx_ber_mon_inst (
.clk(clk),
.rst(rst),
.serdes_rx_hdr(serdes_rx_hdr_int),
.rx_high_ber(rx_high_ber)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4BB_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__NAND4BB_FUNCTIONAL_PP_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__nand4bb (
Y ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , D, C );
or or0 (or0_out_Y , B_N, A_N, nand0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, or0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4BB_FUNCTIONAL_PP_V |
module \$__ICE40_RAM4K (
output [15:0] RDATA,
input RCLK, RCLKE, RE,
input [10:0] RADDR,
input WCLK, WCLKE, WE,
input [10:0] WADDR,
input [15:0] MASK, WDATA
);
parameter [1:0] READ_MODE = 0;
parameter [1:0] WRITE_MODE = 0;
parameter [0:0] NEGCLK_R = 0;
parameter [0:0] NEGCLK_W = 0;
parameter [255:0] INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
parameter [255:0] INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
generate
case ({NEGCLK_R, NEGCLK_W})
2'b00:
SB_RAM40_4K #(
.READ_MODE(READ_MODE),
.WRITE_MODE(WRITE_MODE),
.INIT_0(INIT_0),
.INIT_1(INIT_1),
.INIT_2(INIT_2),
.INIT_3(INIT_3),
.INIT_4(INIT_4),
.INIT_5(INIT_5),
.INIT_6(INIT_6),
.INIT_7(INIT_7),
.INIT_8(INIT_8),
.INIT_9(INIT_9),
.INIT_A(INIT_A),
.INIT_B(INIT_B),
.INIT_C(INIT_C),
.INIT_D(INIT_D),
.INIT_E(INIT_E),
.INIT_F(INIT_F)
) _TECHMAP_REPLACE_ (
.RDATA(RDATA),
.RCLK (RCLK ),
.RCLKE(RCLKE),
.RE (RE ),
.RADDR(RADDR),
.WCLK (WCLK ),
.WCLKE(WCLKE),
.WE (WE ),
.WADDR(WADDR),
.MASK (MASK ),
.WDATA(WDATA)
);
2'b01:
SB_RAM40_4KNW #(
.READ_MODE(READ_MODE),
.WRITE_MODE(WRITE_MODE),
.INIT_0(INIT_0),
.INIT_1(INIT_1),
.INIT_2(INIT_2),
.INIT_3(INIT_3),
.INIT_4(INIT_4),
.INIT_5(INIT_5),
.INIT_6(INIT_6),
.INIT_7(INIT_7),
.INIT_8(INIT_8),
.INIT_9(INIT_9),
.INIT_A(INIT_A),
.INIT_B(INIT_B),
.INIT_C(INIT_C),
.INIT_D(INIT_D),
.INIT_E(INIT_E),
.INIT_F(INIT_F)
) _TECHMAP_REPLACE_ (
.RDATA(RDATA),
.RCLK (RCLK ),
.RCLKE(RCLKE),
.RE (RE ),
.RADDR(RADDR),
.WCLKN(WCLK ),
.WCLKE(WCLKE),
.WE (WE ),
.WADDR(WADDR),
.MASK (MASK ),
.WDATA(WDATA)
);
2'b10:
SB_RAM40_4KNR #(
.READ_MODE(READ_MODE),
.WRITE_MODE(WRITE_MODE),
.INIT_0(INIT_0),
.INIT_1(INIT_1),
.INIT_2(INIT_2),
.INIT_3(INIT_3),
.INIT_4(INIT_4),
.INIT_5(INIT_5),
.INIT_6(INIT_6),
.INIT_7(INIT_7),
.INIT_8(INIT_8),
.INIT_9(INIT_9),
.INIT_A(INIT_A),
.INIT_B(INIT_B),
.INIT_C(INIT_C),
.INIT_D(INIT_D),
.INIT_E(INIT_E),
.INIT_F(INIT_F)
) _TECHMAP_REPLACE_ (
.RDATA(RDATA),
.RCLKN(RCLK ),
.RCLKE(RCLKE),
.RE (RE ),
.RADDR(RADDR),
.WCLK (WCLK ),
.WCLKE(WCLKE),
.WE (WE ),
.WADDR(WADDR),
.MASK (MASK ),
.WDATA(WDATA)
);
2'b11:
SB_RAM40_4KNRNW #(
.READ_MODE(READ_MODE),
.WRITE_MODE(WRITE_MODE),
.INIT_0(INIT_0),
.INIT_1(INIT_1),
.INIT_2(INIT_2),
.INIT_3(INIT_3),
.INIT_4(INIT_4),
.INIT_5(INIT_5),
.INIT_6(INIT_6),
.INIT_7(INIT_7),
.INIT_8(INIT_8),
.INIT_9(INIT_9),
.INIT_A(INIT_A),
.INIT_B(INIT_B),
.INIT_C(INIT_C),
.INIT_D(INIT_D),
.INIT_E(INIT_E),
.INIT_F(INIT_F)
) _TECHMAP_REPLACE_ (
.RDATA(RDATA),
.RCLKN(RCLK ),
.RCLKE(RCLKE),
.RE (RE ),
.RADDR(RADDR),
.WCLKN(WCLK ),
.WCLKE(WCLKE),
.WE (WE ),
.WADDR(WADDR),
.MASK (MASK ),
.WDATA(WDATA)
);
endcase
endgenerate
endmodule
module \$__ICE40_RAM4K_M0 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter [0:0] CLKPOL2 = 1;
parameter [0:0] CLKPOL3 = 1;
parameter [4095:0] INIT = 4096'bx;
input CLK2;
input CLK3;
input [7:0] A1ADDR;
output [15:0] A1DATA;
input A1EN;
input [7:0] B1ADDR;
input [15:0] B1DATA;
input [15:0] B1EN;
wire [10:0] A1ADDR_11 = A1ADDR;
wire [10:0] B1ADDR_11 = B1ADDR;
\$__ICE40_RAM4K #(
.READ_MODE(0),
.WRITE_MODE(0),
.NEGCLK_R(!CLKPOL2),
.NEGCLK_W(!CLKPOL3),
.INIT_0(INIT[ 0*256 +: 256]),
.INIT_1(INIT[ 1*256 +: 256]),
.INIT_2(INIT[ 2*256 +: 256]),
.INIT_3(INIT[ 3*256 +: 256]),
.INIT_4(INIT[ 4*256 +: 256]),
.INIT_5(INIT[ 5*256 +: 256]),
.INIT_6(INIT[ 6*256 +: 256]),
.INIT_7(INIT[ 7*256 +: 256]),
.INIT_8(INIT[ 8*256 +: 256]),
.INIT_9(INIT[ 9*256 +: 256]),
.INIT_A(INIT[10*256 +: 256]),
.INIT_B(INIT[11*256 +: 256]),
.INIT_C(INIT[12*256 +: 256]),
.INIT_D(INIT[13*256 +: 256]),
.INIT_E(INIT[14*256 +: 256]),
.INIT_F(INIT[15*256 +: 256])
) _TECHMAP_REPLACE_ (
.RDATA(A1DATA),
.RADDR(A1ADDR_11),
.RCLK(CLK2),
.RCLKE(A1EN),
.RE(1'b1),
.WDATA(B1DATA),
.WADDR(B1ADDR_11),
.MASK(~B1EN),
.WCLK(CLK3),
.WCLKE(|B1EN),
.WE(1'b1)
);
endmodule
module \$__ICE40_RAM4K_M123 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
parameter CFG_ABITS = 9;
parameter CFG_DBITS = 8;
parameter [0:0] CLKPOL2 = 1;
parameter [0:0] CLKPOL3 = 1;
parameter [4095:0] INIT = 4096'bx;
localparam MODE =
CFG_ABITS == 9 ? 1 :
CFG_ABITS == 10 ? 2 :
CFG_ABITS == 11 ? 3 : 'bx;
input CLK2;
input CLK3;
input [CFG_ABITS-1:0] A1ADDR;
output [CFG_DBITS-1:0] A1DATA;
input A1EN;
input [CFG_ABITS-1:0] B1ADDR;
input [CFG_DBITS-1:0] B1DATA;
input B1EN;
wire [10:0] A1ADDR_11 = A1ADDR;
wire [10:0] B1ADDR_11 = B1ADDR;
wire [15:0] A1DATA_16, B1DATA_16;
generate
if (MODE == 1) begin
assign A1DATA = {A1DATA_16[14], A1DATA_16[12], A1DATA_16[10], A1DATA_16[ 8],
A1DATA_16[ 6], A1DATA_16[ 4], A1DATA_16[ 2], A1DATA_16[ 0]};
assign {B1DATA_16[14], B1DATA_16[12], B1DATA_16[10], B1DATA_16[ 8],
B1DATA_16[ 6], B1DATA_16[ 4], B1DATA_16[ 2], B1DATA_16[ 0]} = B1DATA;
`include "brams_init1.vh"
end
if (MODE == 2) begin
assign A1DATA = {A1DATA_16[13], A1DATA_16[9], A1DATA_16[5], A1DATA_16[1]};
assign {B1DATA_16[13], B1DATA_16[9], B1DATA_16[5], B1DATA_16[1]} = B1DATA;
`include "brams_init2.vh"
end
if (MODE == 3) begin
assign A1DATA = {A1DATA_16[11], A1DATA_16[3]};
assign {B1DATA_16[11], B1DATA_16[3]} = B1DATA;
`include "brams_init3.vh"
end
endgenerate
\$__ICE40_RAM4K #(
.READ_MODE(MODE),
.WRITE_MODE(MODE),
.NEGCLK_R(!CLKPOL2),
.NEGCLK_W(!CLKPOL3),
.INIT_0(INIT_0),
.INIT_1(INIT_1),
.INIT_2(INIT_2),
.INIT_3(INIT_3),
.INIT_4(INIT_4),
.INIT_5(INIT_5),
.INIT_6(INIT_6),
.INIT_7(INIT_7),
.INIT_8(INIT_8),
.INIT_9(INIT_9),
.INIT_A(INIT_A),
.INIT_B(INIT_B),
.INIT_C(INIT_C),
.INIT_D(INIT_D),
.INIT_E(INIT_E),
.INIT_F(INIT_F)
) _TECHMAP_REPLACE_ (
.RDATA(A1DATA_16),
.RADDR(A1ADDR_11),
.RCLK(CLK2),
.RCLKE(A1EN),
.RE(1'b1),
.WDATA(B1DATA_16),
.WADDR(B1ADDR_11),
.WCLK(CLK3),
.WCLKE(|B1EN),
.WE(1'b1)
);
endmodule
|
// This module is a small fifo which has a bsg_channel_narrow
// on its output, that would send out each data in several steps
// based on the input and output width. width_p is the FIFO data
// width and width_out_p is the output width. els_p is the number
// of elements in fifo and lsb_to_msb_p determined the directions
// of sending the data. ready_THEN_valid_p determined input
// handshake protocol.
`include "bsg_defines.v"
module bsg_fifo_1r1w_narrowed
#( parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
, parameter `BSG_INV_PARAM(width_out_p )
, parameter lsb_to_msb_p = 1
, parameter ready_THEN_valid_p = 0
)
( input clk_i
, input reset_i
, input [width_p-1:0] data_i
, input v_i
, output ready_o
, output v_o
, output [width_out_p-1:0] data_o
, input yumi_i
);
// Internal signals
logic [width_p-1:0] data;
logic yumi;
// FIFO of els_p elements of width width_p
bsg_fifo_1r1w_small #(.width_p(width_p)
,.els_p(els_p)
,.ready_THEN_valid_p(ready_THEN_valid_p)
) main_fifo
( .clk_i(clk_i)
, .reset_i(reset_i)
, .data_i(data_i)
, .v_i(v_i)
, .ready_o(ready_o)
, .v_o(v_o)
, .data_o(data)
, .yumi_i(yumi)
);
// selecting from two FIFO outputs and sending one out at a time
bsg_channel_narrow #( .width_in_p(width_p)
, .width_out_p(width_out_p)
, .lsb_to_msb_p(lsb_to_msb_p)
) output_narrower
( .clk_i(clk_i)
, .reset_i(reset_i)
, .data_i(data)
, .deque_o(yumi)
, .data_o(data_o)
, .deque_i(yumi_i)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_fifo_1r1w_narrowed)
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIEBus_axi_basic_tx.v
// Version : 1.11
// //
// Description: //
// AXI to TRN TX module. Instantiates pipeline and throttle control TX //
// submodules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_tx //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module PCIEBus_axi_basic_tx #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
input user_clk, // user clock from block
input user_rst // user reset from block
);
wire tready_thrtl;
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
PCIEBus_axi_basic_tx_pipeline #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) tx_pipeline_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tkeep( s_axis_tx_tkeep ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
// Outgoing TRN TX
//-----------
.trn_td( trn_td ),
.trn_tsof( trn_tsof ),
.trn_teof( trn_teof ),
.trn_tsrc_rdy( trn_tsrc_rdy ),
.trn_tdst_rdy( trn_tdst_rdy ),
.trn_tsrc_dsc( trn_tsrc_dsc ),
.trn_trem( trn_trem ),
.trn_terrfwd( trn_terrfwd ),
.trn_tstr( trn_tstr ),
.trn_tecrc_gen( trn_tecrc_gen ),
.trn_lnk_up( trn_lnk_up ),
// System
//-----------
.tready_thrtl( tready_thrtl ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// TX Throttle Controller //
//---------------------------------------------//
generate
if(C_PM_PRIORITY == "FALSE") begin : thrtl_ctl_enabled
PCIEBus_axi_basic_tx_thrtl_ctl #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.TCQ( TCQ )
) tx_thrl_ctl_inst (
// Outgoing AXI TX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
// User Misc.
//-----------
.user_turnoff_ok( user_turnoff_ok ),
.user_tcfg_gnt( user_tcfg_gnt ),
// Incoming TRN RX
//-----------
.trn_tbuf_av( trn_tbuf_av ),
.trn_tdst_rdy( trn_tdst_rdy ),
// TRN Misc.
//-----------
.trn_tcfg_req( trn_tcfg_req ),
.trn_tcfg_gnt( trn_tcfg_gnt ),
.trn_lnk_up( trn_lnk_up ),
// 7 Seriesq/Virtex6 PM
//-----------
.cfg_pcie_link_state( cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
.trn_rdllp_data( trn_rdllp_data ),
.trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
// System
//-----------
.tready_thrtl( tready_thrtl ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
end
else begin : thrtl_ctl_disabled
assign tready_thrtl = 1'b0;
assign cfg_turnoff_ok = user_turnoff_ok;
assign trn_tcfg_gnt = user_tcfg_gnt;
end
endgenerate
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Wed Nov 2 00:39:52 2016
/////////////////////////////////////////////////////////////
module FPU_Interface2_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, begin_operation,
ack_operation, operation, region_flag, Data_1, Data_2, r_mode,
overflow_flag, underflow_flag, NaN_flag, operation_ready, op_result,
busy );
input [2:0] operation;
input [1:0] region_flag;
input [31:0] Data_1;
input [31:0] Data_2;
input [1:0] r_mode;
output [31:0] op_result;
input clk, rst, begin_operation, ack_operation;
output overflow_flag, underflow_flag, NaN_flag, operation_ready, busy;
wire n8838, NaN_reg, ready_add_subt, underflow_flag_mult,
overflow_flag_addsubt, underflow_flag_addsubt,
FPSENCOS_d_ff3_sign_out, FPSENCOS_d_ff1_operation_out,
FPMULT_FSM_selector_C, FPMULT_FSM_selector_A, FPMULT_zero_flag,
FPADDSUB_OP_FLAG_SFG, FPADDSUB_SIGN_FLAG_SFG, FPADDSUB_SIGN_FLAG_NRM,
FPADDSUB_SIGN_FLAG_SHT1SHT2, FPADDSUB_ADD_OVRFLW_NRM2,
FPADDSUB_OP_FLAG_SHT2, FPADDSUB_SIGN_FLAG_SHT2,
FPADDSUB_bit_shift_SHT2, FPADDSUB_left_right_SHT2,
FPADDSUB_Data_array_SWR_3__25_, FPADDSUB_ADD_OVRFLW_NRM,
FPADDSUB_OP_FLAG_SHT1, FPADDSUB_SIGN_FLAG_SHT1, FPADDSUB_OP_FLAG_EXP,
FPADDSUB_SIGN_FLAG_EXP, FPADDSUB_intAS, FPADDSUB_Shift_reg_FLAGS_7_5,
FPMULT_Exp_module_Overflow_flag_A,
FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_, n1182, n1183, n1184,
n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192, n1193, n1194,
n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202, n1203, n1204,
n1205, n1206, n1207, n1208, n1209, n1210, n1212, n1213, n1214, n1216,
n1217, n1218, n1220, n1221, n1222, n1224, n1225, n1226, n1228, n1229,
n1230, n1232, n1233, n1234, n1236, n1238, n1240, n1242, n1244, n1245,
n1246, n1248, n1249, n1250, n1252, n1253, n1254, n1256, n1257, n1258,
n1260, n1261, n1262, n1264, n1265, n1266, n1268, n1269, n1270, n1272,
n1274, n1276, n1278, n1280, n1281, n1282, n1283, n1285, n1287, n1288,
n1290, n1292, n1294, n1295, n1297, n1299, n1301, n1302, n1304, n1306,
n1308, n1309, n1311, n1313, n1315, n1316, n1317, n1318, n1319, n1320,
n1321, n1322, n1323, n1324, n1325, n1327, n1329, n1331, n1332, n1333,
n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342, n1343,
n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352, n1353,
n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362, n1363,
n1364, n1365, n1366, n1368, n1369, n1371, n1372, n1374, n1375, n1377,
n1378, n1380, n1381, n1383, n1384, n1386, n1387, n1389, n1390, n1392,
n1393, n1395, n1396, n1398, n1399, n1401, n1402, n1404, n1405, n1407,
n1408, n1410, n1411, n1412, n1413, n1414, n1419, n1420, n1421, n1422,
n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432,
n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442,
n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452,
n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1467, n1468, n1469,
n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479,
n1480, n1483, n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492,
n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502,
n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512,
n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1521, n1523, n1524,
n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532, n1533, n1534,
n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542, n1543, n1544,
n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1553, n1554, n1555,
n1556, n1557, n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565,
n1566, n1567, n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575,
n1576, n1577, n1578, n1579, n1580, n1582, n1583, n1584, n1585, n1586,
n1587, n1588, n1589, n1603, n1604, n1605, n1606, n1607, n1608, n1609,
n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619,
n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629,
n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639,
n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650,
n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660,
n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670,
n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680,
n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690,
n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700,
n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710,
n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720,
n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1731,
n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741,
n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751,
n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761,
n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771,
n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781,
n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1790, n1791, n1792,
n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802,
n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812,
n1813, n1814, n1846, n1847, n1848, n1849, n1850, n1851, n1852, n1853,
n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862, n1863,
n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872, n1873,
n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882, n1883,
n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892, n1893,
n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902, n1903,
n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1944, n1945,
n1946, n1947, n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955,
n1956, n1957, n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965,
n1966, n1967, n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975,
n1976, n1977, n1978, n1979, n1980, n1981, n1982, n1983, n1984, n1985,
n1986, n1987, n1988, n1989, n1990, n1991, n1992, n1993, n1994, n1995,
n1996, n1997, n1998, n1999, n2000, n2001, n2002, n2003, n2004, n2005,
n2006, n2007, n2008, n2009, n2010, n2011, n2012, n2013, n2014, n2015,
n2016, n2017, n2018, n2019, n2020, n2021, n2022, n2023, n2024, n2025,
n2026, n2027, n2028, n2029, n2030, n2031, n2032, n2033, n2034, n2035,
n2036, n2037, n2038, n2039, n2040, n2041, n2042, n2043, n2044, n2045,
n2046, n2047, n2048, n2049, n2050, n2051, n2052, n2053, n2054, n2055,
n2056, n2057, n2058, n2059, n2060, n2061, n2062, n2063, n2064, n2065,
n2066, n2067, n2068, n2069, n2070, n2071, n2072, n2073, n2074, n2075,
n2076, n2077, n2078, n2079, n2080, n2081, n2082, n2083, n2084, n2085,
n2086, n2087, n2088, n2089, n2090, n2091, n2092, n2093, n2094, n2095,
n2096, n2097, n2098, n2099, n2100, n2101, n2102, n2103, n2104, n2105,
n2106, n2107, n2108, n2109, n2110, n2111, n2112, n2113, n2114, n2115,
n2116, n2117, n2118, n2119, n2120, n2121, n2122, n2123, n2124, n2125,
n2126, n2127, n2128, n2129, n2130, n2131, n2132, n2133, n2134, n2135,
n2136, n2137, n2138, n2139, n2140, n2141, n2142, n2143, n2145, n2146,
n2147, n2148, n2149, n2150, n2151, n2193, DP_OP_26J2_126_1325_n18,
DP_OP_26J2_126_1325_n17, DP_OP_26J2_126_1325_n16,
DP_OP_26J2_126_1325_n15, DP_OP_26J2_126_1325_n14,
DP_OP_26J2_126_1325_n8, DP_OP_26J2_126_1325_n7,
DP_OP_26J2_126_1325_n6, DP_OP_26J2_126_1325_n5,
DP_OP_26J2_126_1325_n4, DP_OP_26J2_126_1325_n3,
DP_OP_26J2_126_1325_n2, DP_OP_26J2_126_1325_n1, intadd_9_B_1_,
intadd_9_CI, intadd_9_SUM_2_, intadd_9_SUM_1_, intadd_9_SUM_0_,
intadd_9_n3, intadd_9_n2, intadd_9_n1, intadd_10_CI, intadd_10_SUM_2_,
intadd_10_SUM_1_, intadd_10_SUM_0_, intadd_10_n3, intadd_10_n2,
intadd_10_n1, add_x_246_A_5_, add_x_246_A_3_, add_x_246_A_2_,
add_x_246_A_1_, add_x_246_A_0_, add_x_246_n19, add_x_246_n2,
gt_x_74_A_23_, gt_x_74_B_23_, add_x_69_n272, add_x_69_n205,
add_x_69_n204, add_x_69_n202, add_x_69_n201, add_x_69_n198,
add_x_69_n188, add_x_69_n186, add_x_69_n113, add_x_69_n94,
add_x_69_n85, add_x_69_n69, add_x_69_n59, add_x_69_n57, add_x_69_n51,
add_x_69_n47, add_x_69_n39, add_x_69_n16, DP_OP_496J2_122_3540_n1514,
DP_OP_496J2_122_3540_n1513, DP_OP_496J2_122_3540_n1512,
DP_OP_496J2_122_3540_n1506, DP_OP_496J2_122_3540_n1502,
DP_OP_496J2_122_3540_n1499, DP_OP_496J2_122_3540_n1498,
DP_OP_496J2_122_3540_n1493, DP_OP_496J2_122_3540_n1478,
DP_OP_496J2_122_3540_n1472, DP_OP_496J2_122_3540_n1462,
DP_OP_496J2_122_3540_n1461, DP_OP_496J2_122_3540_n1203,
DP_OP_496J2_122_3540_n1202, DP_OP_496J2_122_3540_n1199,
DP_OP_496J2_122_3540_n1193, DP_OP_496J2_122_3540_n1192,
DP_OP_496J2_122_3540_n1120, DP_OP_496J2_122_3540_n1114,
DP_OP_496J2_122_3540_n1113, DP_OP_496J2_122_3540_n1108,
DP_OP_496J2_122_3540_n1107, DP_OP_496J2_122_3540_n1103,
DP_OP_496J2_122_3540_n1102, DP_OP_496J2_122_3540_n1063,
DP_OP_496J2_122_3540_n778, DP_OP_497J2_123_1725_n794,
DP_OP_497J2_123_1725_n793, DP_OP_497J2_123_1725_n792,
DP_OP_497J2_123_1725_n791, DP_OP_497J2_123_1725_n782,
DP_OP_497J2_123_1725_n781, DP_OP_497J2_123_1725_n780,
DP_OP_497J2_123_1725_n779, DP_OP_497J2_123_1725_n778,
DP_OP_497J2_123_1725_n716, DP_OP_497J2_123_1725_n705,
DP_OP_497J2_123_1725_n686, DP_OP_497J2_123_1725_n669,
DP_OP_497J2_123_1725_n668, DP_OP_497J2_123_1725_n638,
DP_OP_497J2_123_1725_n631, DP_OP_497J2_123_1725_n392,
DP_OP_497J2_123_1725_n324, DP_OP_497J2_123_1725_n312,
DP_OP_498J2_124_1725_n803, DP_OP_498J2_124_1725_n802,
DP_OP_498J2_124_1725_n801, DP_OP_498J2_124_1725_n797,
DP_OP_498J2_124_1725_n796, DP_OP_498J2_124_1725_n795,
DP_OP_498J2_124_1725_n792, DP_OP_498J2_124_1725_n791,
DP_OP_498J2_124_1725_n790, DP_OP_498J2_124_1725_n789,
DP_OP_498J2_124_1725_n788, DP_OP_498J2_124_1725_n786,
DP_OP_498J2_124_1725_n732, DP_OP_498J2_124_1725_n722,
DP_OP_498J2_124_1725_n718, DP_OP_498J2_124_1725_n645,
DP_OP_498J2_124_1725_n636, DP_OP_498J2_124_1725_n635,
DP_OP_498J2_124_1725_n631, DP_OP_498J2_124_1725_n390,
DP_OP_498J2_124_1725_n362, DP_OP_499J2_125_1651_n62,
DP_OP_499J2_125_1651_n44, DP_OP_499J2_125_1651_n39,
DP_OP_499J2_125_1651_n34, DP_OP_499J2_125_1651_n8,
DP_OP_499J2_125_1651_n6, DP_OP_499J2_125_1651_n5,
DP_OP_499J2_125_1651_n4, DP_OP_499J2_125_1651_n3, n2196, n2197, n2198,
n2199, n2200, n2201, n2202, n2203, n2204, n2205, n2206, n2207, n2208,
n2209, n2210, n2211, n2212, n2213, n2214, n2215, n2216, n2217, n2218,
n2219, n2220, n2221, n2222, n2226, n2227, n2228, n2229, n2230, n2231,
n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241,
n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251,
n2252, n2253, n2254, n2255, n2256, n2257, n2259, n2260, n2261, n2262,
n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272,
n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282,
n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292,
n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302,
n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312,
n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322,
n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2332, n2333,
n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342, n2343,
n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352, n2353,
n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362, n2363,
n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372, n2373,
n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382, n2383,
n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392, n2393,
n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402, n2403,
n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412, n2413,
n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422, n2423,
n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432, n2433,
n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442, n2443,
n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452, n2453,
n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462, n2463,
n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472, n2473,
n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482, n2483,
n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492, n2493,
n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502, n2503,
n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512, n2513,
n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522, n2523,
n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532, n2533,
n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542, n2543,
n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552, n2553,
n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562, n2563,
n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572, n2573,
n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582, n2583,
n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592, n2593,
n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602, n2603,
n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612, n2613,
n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622, n2623,
n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632, n2633,
n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642, n2643,
n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652, n2653,
n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662, n2663,
n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672, n2673,
n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682, n2683,
n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692, n2693,
n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702, n2703,
n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712, n2713,
n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722, n2723,
n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732, n2733,
n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742, n2743,
n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752, n2753,
n2754, n2755, n2757, n2758, n2759, n2760, n2761, n2762, n2763, n2764,
n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772, n2773, n2774,
n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782, n2783, n2784,
n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792, n2793, n2794,
n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802, n2803, n2804,
n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812, n2813, n2814,
n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822, n2823, n2824,
n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832, n2833, n2834,
n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842, n2843, n2844,
n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852, n2853, n2854,
n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862, n2863, n2864,
n2865, n2866, n2867, n2868, n2870, n2871, n2872, n2873, n2874, n2875,
n2876, n2877, n2878, n2879, n2880, n2881, n2882, n2883, n2884, n2885,
n2886, n2887, n2888, n2889, n2890, n2891, n2892, n2893, n2894, n2895,
n2896, n2897, n2898, n2899, n2900, n2901, n2902, n2903, n2904, n2905,
n2906, n2907, n2908, n2909, n2910, n2911, n2912, n2913, n2914, n2915,
n2916, n2917, n2918, n2919, n2920, n2921, n2922, n2923, n2924, n2925,
n2926, n2927, n2928, n2929, n2930, n2931, n2932, n2933, n2934, n2935,
n2936, n2937, n2938, n2939, n2940, n2941, n2942, n2943, n2944, n2945,
n2946, n2947, n2948, n2949, n2950, n2951, n2952, n2953, n2954, n2955,
n2956, n2957, n2958, n2959, n2960, n2961, n2962, n2963, n2964, n2965,
n2966, n2967, n2968, n2969, n2970, n2971, n2972, n2973, n2974, n2975,
n2976, n2977, n2978, n2979, n2980, n2981, n2982, n2983, n2984, n2985,
n2986, n2987, n2988, n2989, n2990, n2991, n2992, n2993, n2994, n2995,
n2996, n2997, n2998, n2999, n3000, n3001, n3002, n3003, n3004, n3005,
n3006, n3007, n3008, n3009, n3010, n3011, n3012, n3013, n3014, n3015,
n3016, n3017, n3018, n3019, n3020, n3021, n3022, n3023, n3024, n3025,
n3026, n3027, n3028, n3029, n3030, n3031, n3032, n3033, n3034, n3035,
n3036, n3037, n3038, n3039, n3040, n3041, n3042, n3043, n3044, n3045,
n3046, n3047, n3048, n3049, n3050, n3051, n3052, n3053, n3054, n3055,
n3056, n3057, n3058, n3059, n3060, n3061, n3062, n3063, n3064, n3065,
n3066, n3067, n3068, n3069, n3070, n3071, n3072, n3073, n3074, n3075,
n3076, n3077, n3078, n3079, n3080, n3081, n3082, n3083, n3084, n3085,
n3086, n3087, n3088, n3089, n3090, n3091, n3092, n3093, n3094, n3095,
n3096, n3097, n3098, n3099, n3100, n3101, n3102, n3103, n3104, n3105,
n3106, n3107, n3108, n3109, n3110, n3111, n3112, n3113, n3114, n3115,
n3116, n3117, n3118, n3119, n3120, n3121, n3122, n3123, n3124, n3125,
n3126, n3127, n3128, n3129, n3130, n3131, n3132, n3133, n3134, n3135,
n3136, n3137, n3138, n3139, n3140, n3141, n3142, n3143, n3144, n3145,
n3146, n3147, n3148, n3149, n3150, n3151, n3152, n3153, n3154, n3155,
n3156, n3157, n3158, n3159, n3160, n3161, n3162, n3163, n3164, n3165,
n3166, n3167, n3168, n3169, n3170, n3171, n3172, n3173, n3174, n3175,
n3176, n3177, n3178, n3179, n3180, n3181, n3182, n3183, n3184, n3185,
n3186, n3187, n3188, n3189, n3190, n3191, n3192, n3193, n3194, n3195,
n3196, n3197, n3198, n3199, n3200, n3201, n3202, n3203, n3204, n3205,
n3206, n3207, n3208, n3209, n3210, n3211, n3212, n3213, n3214, n3215,
n3216, n3217, n3218, n3219, n3220, n3221, n3222, n3223, n3224, n3225,
n3226, n3227, n3228, n3229, n3230, n3231, n3232, n3233, n3234, n3235,
n3236, n3237, n3238, n3239, n3240, n3241, n3242, n3243, n3244, n3245,
n3246, n3247, n3248, n3249, n3250, n3251, n3252, n3253, n3254, n3255,
n3256, n3257, n3258, n3259, n3260, n3261, n3262, n3263, n3264, n3265,
n3266, n3267, n3268, n3269, n3270, n3271, n3272, n3273, n3274, n3275,
n3276, n3277, n3278, n3279, n3280, n3281, n3282, n3283, n3284, n3285,
n3286, n3287, n3288, n3289, n3290, n3291, n3292, n3293, n3294, n3295,
n3296, n3297, n3298, n3299, n3300, n3301, n3302, n3303, n3304, n3305,
n3306, n3307, n3308, n3309, n3310, n3311, n3312, n3313, n3314, n3315,
n3316, n3317, n3318, n3319, n3320, n3321, n3322, n3323, n3324, n3325,
n3326, n3327, n3328, n3329, n3330, n3331, n3332, n3333, n3334, n3335,
n3336, n3337, n3338, n3339, n3340, n3341, n3342, n3343, n3344, n3345,
n3346, n3347, n3348, n3349, n3350, n3351, n3352, n3353, n3354, n3355,
n3356, n3357, n3358, n3359, n3360, n3361, n3362, n3363, n3364, n3365,
n3366, n3367, n3368, n3369, n3370, n3371, n3372, n3373, n3374, n3375,
n3376, n3377, n3378, n3379, n3380, n3381, n3382, n3383, n3384, n3385,
n3386, n3387, n3388, n3389, n3390, n3391, n3392, n3393, n3394, n3395,
n3396, n3397, n3398, n3399, n3400, n3401, n3402, n3403, n3404, n3405,
n3406, n3407, n3408, n3409, n3410, n3411, n3412, n3413, n3414, n3415,
n3416, n3417, n3418, n3419, n3420, n3421, n3422, n3423, n3424, n3425,
n3426, n3427, n3428, n3429, n3430, n3431, n3432, n3433, n3434, n3435,
n3436, n3437, n3438, n3439, n3440, n3441, n3442, n3443, n3444, n3445,
n3446, n3447, n3448, n3449, n3450, n3451, n3452, n3453, n3454, n3455,
n3456, n3457, n3458, n3459, n3460, n3461, n3462, n3463, n3464, n3465,
n3466, n3467, n3468, n3469, n3470, n3471, n3472, n3473, n3474, n3475,
n3476, n3477, n3478, n3479, n3480, n3481, n3482, n3483, n3484, n3485,
n3486, n3487, n3488, n3489, n3490, n3491, n3492, n3493, n3494, n3495,
n3496, n3497, n3498, n3499, n3500, n3501, n3502, n3503, n3504, n3505,
n3506, n3507, n3508, n3509, n3510, n3511, n3512, n3513, n3514, n3515,
n3516, n3517, n3518, n3519, n3520, n3521, n3522, n3523, n3524, n3525,
n3526, n3527, n3528, n3529, n3530, n3531, n3532, n3533, n3534, n3535,
n3536, n3537, n3538, n3539, n3540, n3541, n3542, n3543, n3544, n3545,
n3546, n3547, n3548, n3549, n3550, n3551, n3552, n3553, n3554, n3555,
n3556, n3557, n3558, n3559, n3560, n3561, n3562, n3563, n3564, n3565,
n3566, n3567, n3568, n3569, n3570, n3571, n3572, n3573, n3574, n3575,
n3576, n3577, n3578, n3579, n3580, n3581, n3582, n3583, n3584, n3585,
n3586, n3587, n3588, n3589, n3590, n3591, n3592, n3593, n3594, n3595,
n3596, n3597, n3598, n3599, n3600, n3601, n3602, n3603, n3604, n3605,
n3606, n3607, n3608, n3609, n3610, n3611, n3612, n3613, n3614, n3615,
n3616, n3617, n3618, n3619, n3620, n3621, n3622, n3623, n3624, n3625,
n3626, n3627, n3628, n3629, n3630, n3631, n3632, n3633, n3634, n3635,
n3636, n3637, n3638, n3639, n3640, n3641, n3642, n3643, n3644, n3645,
n3646, n3647, n3648, n3649, n3650, n3651, n3652, n3653, n3654, n3655,
n3656, n3657, n3658, n3659, n3660, n3661, n3662, n3663, n3664, n3665,
n3666, n3667, n3668, n3669, n3670, n3671, n3672, n3673, n3674, n3675,
n3676, n3677, n3678, n3679, n3680, n3681, n3682, n3683, n3684, n3685,
n3686, n3687, n3688, n3689, n3690, n3691, n3692, n3693, n3694, n3695,
n3696, n3697, n3698, n3699, n3700, n3701, n3702, n3703, n3704, n3705,
n3706, n3707, n3708, n3709, n3710, n3711, n3712, n3713, n3714, n3715,
n3716, n3717, n3718, n3719, n3720, n3721, n3722, n3723, n3724, n3725,
n3726, n3727, n3728, n3729, n3730, n3731, n3732, n3733, n3734, n3735,
n3736, n3737, n3738, n3739, n3740, n3741, n3742, n3743, n3744, n3745,
n3746, n3747, n3748, n3749, n3750, n3751, n3752, n3753, n3754, n3755,
n3756, n3757, n3758, n3759, n3760, n3761, n3762, n3763, n3764, n3765,
n3766, n3767, n3768, n3769, n3770, n3771, n3772, n3773, n3774, n3775,
n3776, n3777, n3778, n3779, n3780, n3781, n3782, n3783, n3784, n3785,
n3786, n3787, n3788, n3789, n3790, n3791, n3792, n3793, n3794, n3795,
n3796, n3797, n3798, n3799, n3800, n3801, n3802, n3803, n3804, n3805,
n3806, n3807, n3808, n3809, n3810, n3811, n3812, n3813, n3814, n3815,
n3816, n3817, n3818, n3819, n3820, n3821, n3822, n3823, n3824, n3825,
n3826, n3827, n3828, n3829, n3830, n3831, n3832, n3833, n3834, n3835,
n3836, n3837, n3838, n3839, n3840, n3841, n3842, n3843, n3844, n3845,
n3846, n3847, n3848, n3849, n3850, n3851, n3852, n3853, n3854, n3855,
n3856, n3857, n3858, n3859, n3860, n3861, n3862, n3863, n3864, n3865,
n3866, n3867, n3868, n3869, n3870, n3871, n3872, n3873, n3874, n3875,
n3876, n3877, n3878, n3879, n3880, n3881, n3882, n3883, n3884, n3885,
n3886, n3887, n3888, n3889, n3890, n3891, n3892, n3893, n3894, n3895,
n3896, n3897, n3898, n3899, n3900, n3901, n3902, n3903, n3904, n3905,
n3906, n3907, n3908, n3909, n3910, n3911, n3912, n3913, n3914, n3915,
n3916, n3917, n3918, n3919, n3920, n3921, n3922, n3923, n3924, n3925,
n3926, n3927, n3928, n3929, n3930, n3931, n3932, n3933, n3934, n3935,
n3936, n3937, n3938, n3939, n3940, n3941, n3942, n3943, n3944, n3945,
n3946, n3947, n3948, n3949, n3950, n3951, n3952, n3953, n3954, n3955,
n3956, n3957, n3958, n3959, n3960, n3961, n3962, n3963, n3964, n3965,
n3966, n3967, n3968, n3969, n3970, n3971, n3972, n3973, n3974, n3975,
n3976, n3977, n3978, n3979, n3980, n3981, n3982, n3983, n3984, n3985,
n3986, n3987, n3988, n3989, n3990, n3991, n3992, n3993, n3994, n3995,
n3996, n3997, n3998, n3999, n4000, n4001, n4002, n4003, n4004, n4005,
n4006, n4007, n4008, n4009, n4010, n4011, n4012, n4013, n4014, n4015,
n4016, n4017, n4018, n4019, n4020, n4021, n4022, n4023, n4024, n4025,
n4026, n4027, n4028, n4029, n4030, n4031, n4032, n4033, n4034, n4035,
n4036, n4037, n4038, n4039, n4040, n4041, n4042, n4043, n4044, n4045,
n4046, n4047, n4048, n4049, n4050, n4051, n4052, n4053, n4054, n4055,
n4056, n4057, n4058, n4059, n4060, n4061, n4062, n4063, n4064, n4065,
n4066, n4067, n4068, n4069, n4070, n4071, n4072, n4073, n4074, n4075,
n4076, n4077, n4078, n4079, n4080, n4081, n4082, n4083, n4084, n4085,
n4086, n4087, n4088, n4089, n4090, n4091, n4092, n4093, n4094, n4095,
n4096, n4097, n4098, n4099, n4100, n4102, n4103, n4104, n4105, n4106,
n4107, n4108, n4109, n4110, n4111, n4112, n4113, n4114, n4115, n4116,
n4117, n4118, n4119, n4120, n4121, n4122, n4123, n4124, n4125, n4126,
n4127, n4128, n4129, n4130, n4131, n4132, n4133, n4134, n4135, n4136,
n4137, n4138, n4139, n4140, n4141, n4142, n4143, n4144, n4145, n4146,
n4147, n4148, n4149, n4150, n4151, n4152, n4153, n4154, n4155, n4156,
n4157, n4158, n4159, n4160, n4161, n4162, n4163, n4164, n4165, n4166,
n4167, n4168, n4169, n4170, n4171, n4172, n4173, n4174, n4175, n4176,
n4177, n4178, n4179, n4180, n4181, n4182, n4183, n4184, n4185, n4186,
n4187, n4188, n4189, n4190, n4191, n4192, n4193, n4194, n4195, n4196,
n4197, n4198, n4199, n4200, n4201, n4202, n4203, n4204, n4205, n4206,
n4207, n4208, n4209, n4210, n4211, n4212, n4213, n4214, n4215, n4216,
n4217, n4218, n4219, n4220, n4221, n4222, n4223, n4224, n4225, n4226,
n4227, n4228, n4229, n4230, n4231, n4232, n4233, n4234, n4235, n4236,
n4237, n4238, n4239, n4240, n4241, n4242, n4243, n4244, n4245, n4246,
n4247, n4248, n4249, n4250, n4251, n4252, n4253, n4254, n4255, n4256,
n4257, n4258, n4259, n4260, n4261, n4262, n4263, n4264, n4265, n4266,
n4267, n4268, n4269, n4270, n4271, n4272, n4273, n4274, n4275, n4276,
n4277, n4278, n4279, n4280, n4281, n4282, n4283, n4284, n4285, n4286,
n4287, n4288, n4289, n4290, n4291, n4292, n4293, n4294, n4295, n4296,
n4297, n4298, n4299, n4300, n4301, n4302, n4303, n4304, n4305, n4306,
n4307, n4308, n4309, n4310, n4311, n4312, n4313, n4314, n4315, n4316,
n4317, n4318, n4319, n4320, n4321, n4322, n4323, n4324, n4325, n4326,
n4327, n4328, n4329, n4330, n4331, n4332, n4333, n4334, n4335, n4336,
n4337, n4338, n4339, n4340, n4341, n4342, n4343, n4344, n4345, n4346,
n4347, n4348, n4349, n4350, n4351, n4352, n4353, n4354, n4355, n4356,
n4357, n4358, n4359, n4360, n4361, n4362, n4363, n4364, n4365, n4366,
n4367, n4368, n4369, n4370, n4371, n4372, n4373, n4374, n4375, n4376,
n4377, n4378, n4379, n4380, n4381, n4382, n4383, n4384, n4385, n4386,
n4387, n4388, n4389, n4390, n4391, n4392, n4393, n4394, n4395, n4396,
n4397, n4398, n4399, n4400, n4401, n4402, n4403, n4404, n4405, n4406,
n4407, n4408, n4409, n4410, n4411, n4412, n4413, n4414, n4415, n4416,
n4417, n4418, n4419, n4420, n4421, n4422, n4423, n4424, n4425, n4426,
n4427, n4428, n4429, n4430, n4431, n4432, n4433, n4434, n4435, n4436,
n4437, n4438, n4439, n4440, n4441, n4442, n4443, n4444, n4445, n4446,
n4447, n4448, n4449, n4450, n4451, n4452, n4453, n4454, n4455, n4456,
n4457, n4458, n4459, n4460, n4461, n4462, n4463, n4464, n4465, n4466,
n4467, n4468, n4469, n4470, n4471, n4472, n4473, n4474, n4475, n4476,
n4477, n4478, n4479, n4480, n4481, n4482, n4483, n4484, n4485, n4486,
n4487, n4488, n4489, n4490, n4491, n4492, n4493, n4494, n4495, n4496,
n4497, n4498, n4499, n4500, n4501, n4502, n4503, n4504, n4505, n4506,
n4507, n4508, n4509, n4510, n4511, n4512, n4513, n4514, n4515, n4516,
n4517, n4518, n4519, n4520, n4521, n4522, n4523, n4524, n4525, n4526,
n4527, n4528, n4529, n4530, n4531, n4532, n4533, n4534, n4535, n4536,
n4537, n4538, n4539, n4540, n4541, n4542, n4543, n4544, n4545, n4546,
n4547, n4548, n4549, n4550, n4551, n4552, n4553, n4554, n4555, n4556,
n4557, n4558, n4559, n4560, n4561, n4562, n4563, n4564, n4565, n4566,
n4567, n4568, n4569, n4570, n4571, n4572, n4573, n4574, n4575, n4576,
n4577, n4578, n4579, n4580, n4581, n4582, n4583, n4584, n4585, n4586,
n4587, n4588, n4589, n4590, n4591, n4592, n4593, n4594, n4595, n4596,
n4597, n4598, n4599, n4600, n4601, n4602, n4603, n4604, n4605, n4606,
n4607, n4608, n4609, n4610, n4611, n4612, n4613, n4614, n4615, n4616,
n4617, n4618, n4619, n4620, n4621, n4622, n4623, n4624, n4625, n4626,
n4627, n4628, n4629, n4630, n4631, n4632, n4633, n4634, n4635, n4636,
n4637, n4638, n4639, n4640, n4641, n4642, n4643, n4644, n4645, n4646,
n4647, n4648, n4649, n4650, n4651, n4652, n4653, n4654, n4655, n4656,
n4657, n4658, n4659, n4660, n4661, n4662, n4663, n4664, n4665, n4666,
n4667, n4668, n4669, n4670, n4671, n4672, n4673, n4674, n4675, n4676,
n4677, n4678, n4679, n4680, n4681, n4682, n4683, n4684, n4685, n4686,
n4687, n4688, n4689, n4690, n4691, n4692, n4693, n4694, n4695, n4696,
n4697, n4698, n4699, n4700, n4701, n4702, n4703, n4704, n4705, n4706,
n4707, n4708, n4709, n4710, n4711, n4712, n4713, n4714, n4715, n4716,
n4717, n4718, n4719, n4720, n4721, n4722, n4723, n4724, n4725, n4726,
n4727, n4728, n4729, n4730, n4731, n4732, n4733, n4734, n4735, n4736,
n4737, n4738, n4739, n4740, n4741, n4742, n4743, n4744, n4745, n4746,
n4747, n4748, n4749, n4750, n4751, n4752, n4753, n4754, n4755, n4756,
n4757, n4758, n4759, n4760, n4761, n4762, n4763, n4764, n4765, n4766,
n4767, n4768, n4769, n4770, n4771, n4772, n4773, n4774, n4775, n4776,
n4777, n4778, n4779, n4780, n4781, n4782, n4783, n4784, n4785, n4786,
n4787, n4788, n4789, n4790, n4791, n4792, n4793, n4794, n4795, n4796,
n4797, n4798, n4799, n4800, n4801, n4802, n4803, n4804, n4805, n4806,
n4807, n4808, n4809, n4810, n4811, n4812, n4813, n4814, n4815, n4816,
n4817, n4818, n4819, n4820, n4821, n4822, n4823, n4824, n4825, n4826,
n4827, n4828, n4829, n4830, n4831, n4832, n4833, n4834, n4835, n4836,
n4837, n4838, n4839, n4840, n4841, n4842, n4843, n4844, n4845, n4846,
n4847, n4848, n4849, n4850, n4851, n4852, n4853, n4854, n4855, n4856,
n4857, n4858, n4859, n4860, n4861, n4862, n4863, n4864, n4865, n4866,
n4867, n4868, n4869, n4870, n4871, n4872, n4873, n4874, n4875, n4876,
n4877, n4878, n4879, n4880, n4881, n4882, n4883, n4884, n4885, n4886,
n4887, n4888, n4889, n4890, n4891, n4892, n4893, n4894, n4895, n4896,
n4897, n4898, n4899, n4900, n4901, n4902, n4903, n4904, n4905, n4906,
n4907, n4908, n4909, n4910, n4911, n4912, n4913, n4914, n4915, n4916,
n4917, n4918, n4919, n4920, n4921, n4922, n4923, n4924, n4925, n4926,
n4927, n4928, n4929, n4930, n4931, n4932, n4933, n4934, n4935, n4936,
n4937, n4938, n4939, n4940, n4941, n4942, n4943, n4944, n4945, n4946,
n4947, n4948, n4949, n4950, n4951, n4952, n4953, n4954, n4955, n4956,
n4957, n4958, n4959, n4960, n4961, n4962, n4963, n4964, n4965, n4966,
n4967, n4968, n4969, n4970, n4971, n4972, n4973, n4974, n4975, n4976,
n4977, n4978, n4979, n4980, n4981, n4982, n4983, n4984, n4985, n4986,
n4987, n4988, n4989, n4990, n4991, n4992, n4993, n4994, n4995, n4996,
n4997, n4998, n4999, n5000, n5001, n5002, n5003, n5004, n5005, n5006,
n5007, n5008, n5009, n5010, n5011, n5012, n5013, n5014, n5015, n5016,
n5017, n5018, n5019, n5020, n5021, n5022, n5023, n5024, n5025, n5026,
n5027, n5028, n5029, n5030, n5031, n5032, n5033, n5034, n5035, n5036,
n5037, n5038, n5039, n5040, n5041, n5042, n5043, n5044, n5045, n5046,
n5047, n5048, n5049, n5050, n5051, n5052, n5053, n5054, n5055, n5056,
n5057, n5058, n5059, n5060, n5061, n5062, n5063, n5064, n5065, n5066,
n5067, n5068, n5069, n5070, n5071, n5072, n5073, n5074, n5075, n5076,
n5077, n5078, n5079, n5080, n5081, n5082, n5083, n5084, n5085, n5086,
n5087, n5088, n5089, n5090, n5091, n5092, n5093, n5094, n5095, n5096,
n5097, n5098, n5099, n5100, n5101, n5102, n5103, n5104, n5105, n5106,
n5107, n5108, n5109, n5110, n5111, n5112, n5113, n5114, n5115, n5116,
n5117, n5118, n5119, n5120, n5121, n5122, n5123, n5124, n5125, n5126,
n5127, n5128, n5129, n5130, n5131, n5132, n5133, n5134, n5135, n5136,
n5137, n5138, n5139, n5140, n5141, n5142, n5143, n5144, n5145, n5146,
n5147, n5148, n5149, n5150, n5151, n5152, n5153, n5154, n5155, n5156,
n5157, n5158, n5159, n5160, n5161, n5162, n5163, n5164, n5165, n5166,
n5167, n5168, n5169, n5170, n5171, n5172, n5173, n5174, n5175, n5176,
n5177, n5178, n5179, n5180, n5181, n5182, n5183, n5184, n5185, n5186,
n5187, n5188, n5189, n5190, n5191, n5192, n5193, n5194, n5195, n5196,
n5197, n5198, n5199, n5200, n5201, n5202, n5203, n5204, n5205, n5206,
n5207, n5208, n5209, n5210, n5211, n5212, n5213, n5214, n5215, n5216,
n5217, n5218, n5219, n5220, n5221, n5222, n5223, n5224, n5225, n5226,
n5227, n5228, n5229, n5230, n5231, n5232, n5233, n5234, n5235, n5236,
n5237, n5238, n5239, n5240, n5241, n5242, n5243, n5244, n5245, n5246,
n5247, n5248, n5249, n5250, n5251, n5252, n5253, n5254, n5255, n5256,
n5257, n5258, n5259, n5260, n5261, n5262, n5263, n5264, n5265, n5266,
n5267, n5268, n5269, n5270, n5271, n5272, n5273, n5274, n5275, n5276,
n5277, n5278, n5279, n5280, n5281, n5282, n5283, n5284, n5285, n5286,
n5287, n5288, n5289, n5290, n5291, n5292, n5293, n5294, n5295, n5296,
n5297, n5298, n5299, n5300, n5301, n5302, n5303, n5304, n5305, n5306,
n5307, n5308, n5309, n5310, n5311, n5312, n5313, n5314, n5315, n5316,
n5317, n5318, n5319, n5320, n5321, n5322, n5323, n5324, n5325, n5326,
n5327, n5328, n5329, n5330, n5331, n5332, n5333, n5334, n5335, n5336,
n5337, n5338, n5339, n5340, n5341, n5342, n5343, n5344, n5345, n5346,
n5347, n5348, n5349, n5350, n5351, n5352, n5353, n5354, n5355, n5356,
n5357, n5358, n5359, n5360, n5361, n5362, n5363, n5364, n5365, n5366,
n5367, n5368, n5369, n5370, n5371, n5372, n5373, n5374, n5375, n5376,
n5377, n5378, n5379, n5380, n5381, n5382, n5383, n5384, n5385, n5386,
n5387, n5388, n5389, n5390, n5391, n5392, n5393, n5394, n5395, n5396,
n5397, n5398, n5399, n5400, n5401, n5402, n5403, n5404, n5405, n5406,
n5407, n5408, n5409, n5410, n5411, n5412, n5413, n5414, n5415, n5416,
n5417, n5418, n5419, n5420, n5421, n5422, n5423, n5424, n5425, n5426,
n5427, n5428, n5429, n5430, n5431, n5432, n5433, n5434, n5435, n5436,
n5437, n5438, n5439, n5440, n5441, n5442, n5443, n5444, n5445, n5446,
n5447, n5448, n5449, n5450, n5451, n5452, n5453, n5454, n5455, n5456,
n5457, n5458, n5459, n5460, n5461, n5462, n5463, n5464, n5465, n5466,
n5467, n5468, n5469, n5470, n5471, n5472, n5473, n5474, n5475, n5476,
n5477, n5478, n5479, n5480, n5481, n5482, n5483, n5484, n5485, n5486,
n5487, n5488, n5489, n5490, n5491, n5492, n5493, n5494, n5495, n5496,
n5497, n5498, n5499, n5500, n5501, n5502, n5503, n5504, n5505, n5506,
n5507, n5508, n5509, n5510, n5511, n5512, n5513, n5514, n5515, n5516,
n5517, n5518, n5519, n5520, n5521, n5522, n5523, n5524, n5525, n5526,
n5527, n5528, n5529, n5530, n5531, n5532, n5533, n5534, n5535, n5536,
n5537, n5538, n5539, n5540, n5541, n5542, n5543, n5544, n5545, n5546,
n5547, n5548, n5549, n5550, n5551, n5552, n5553, n5554, n5555, n5556,
n5557, n5558, n5559, n5560, n5561, n5562, n5563, n5564, n5565, n5566,
n5567, n5568, n5569, n5570, n5571, n5572, n5573, n5574, n5575, n5576,
n5577, n5578, n5579, n5580, n5581, n5582, n5583, n5584, n5585, n5586,
n5587, n5588, n5589, n5590, n5591, n5592, n5593, n5594, n5595, n5596,
n5597, n5598, n5599, n5600, n5601, n5602, n5603, n5604, n5605, n5606,
n5607, n5608, n5609, n5610, n5611, n5612, n5613, n5614, n5615, n5616,
n5617, n5618, n5619, n5620, n5621, n5622, n5623, n5624, n5625, n5626,
n5627, n5628, n5629, n5630, n5631, n5632, n5633, n5634, n5635, n5636,
n5637, n5638, n5639, n5640, n5641, n5642, n5643, n5644, n5645, n5646,
n5647, n5648, n5649, n5650, n5651, n5652, n5653, n5654, n5655, n5656,
n5657, n5658, n5659, n5660, n5661, n5662, n5663, n5664, n5665, n5666,
n5667, n5668, n5669, n5670, n5671, n5672, n5673, n5674, n5675, n5676,
n5677, n5678, n5679, n5680, n5681, n5682, n5683, n5684, n5685, n5686,
n5687, n5688, n5689, n5690, n5691, n5692, n5693, n5694, n5695, n5696,
n5697, n5698, n5699, n5700, n5701, n5702, n5703, n5704, n5705, n5706,
n5707, n5708, n5709, n5710, n5711, n5712, n5713, n5714, n5715, n5716,
n5717, n5718, n5719, n5720, n5721, n5722, n5723, n5724, n5725, n5726,
n5727, n5728, n5729, n5730, n5731, n5732, n5733, n5734, n5735, n5736,
n5737, n5738, n5739, n5740, n5741, n5742, n5743, n5744, n5745, n5746,
n5747, n5748, n5749, n5750, n5751, n5752, n5753, n5754, n5755, n5756,
n5757, n5758, n5759, n5760, n5761, n5762, n5763, n5764, n5765, n5766,
n5767, n5768, n5769, n5770, n5771, n5772, n5773, n5774, n5775, n5776,
n5777, n5778, n5779, n5780, n5781, n5782, n5783, n5784, n5785, n5786,
n5787, n5788, n5789, n5790, n5791, n5792, n5793, n5794, n5795, n5796,
n5797, n5798, n5799, n5800, n5801, n5802, n5803, n5804, n5805, n5806,
n5807, n5808, n5809, n5810, n5811, n5812, n5813, n5814, n5815, n5816,
n5817, n5818, n5819, n5820, n5821, n5822, n5823, n5824, n5825, n5826,
n5827, n5828, n5829, n5830, n5831, n5832, n5833, n5834, n5835, n5836,
n5837, n5838, n5839, n5840, n5841, n5842, n5843, n5844, n5845, n5846,
n5847, n5848, n5849, n5850, n5851, n5852, n5853, n5854, n5855, n5856,
n5857, n5858, n5859, n5860, n5861, n5862, n5863, n5864, n5865, n5866,
n5867, n5868, n5869, n5870, n5871, n5872, n5873, n5874, n5875, n5876,
n5877, n5878, n5879, n5880, n5881, n5882, n5883, n5884, n5885, n5886,
n5887, n5888, n5889, n5890, n5891, n5892, n5893, n5894, n5895, n5896,
n5897, n5898, n5899, n5900, n5901, n5902, n5903, n5904, n5905, n5906,
n5907, n5908, n5909, n5910, n5911, n5912, n5913, n5914, n5915, n5916,
n5917, n5918, n5919, n5920, n5921, n5922, n5923, n5924, n5925, n5926,
n5927, n5928, n5929, n5930, n5931, n5932, n5933, n5934, n5935, n5936,
n5937, n5938, n5939, n5940, n5941, n5942, n5943, n5944, n5945, n5946,
n5947, n5948, n5949, n5950, n5951, n5952, n5953, n5954, n5955, n5956,
n5957, n5958, n5959, n5960, n5961, n5962, n5963, n5964, n5965, n5966,
n5967, n5968, n5969, n5970, n5971, n5972, n5973, n5974, n5975, n5976,
n5977, n5978, n5979, n5980, n5981, n5982, n5983, n5984, n5985, n5986,
n5987, n5988, n5989, n5990, n5991, n5992, n5993, n5994, n5995, n5996,
n5997, n5998, n5999, n6000, n6001, n6002, n6003, n6004, n6005, n6006,
n6007, n6008, n6009, n6010, n6011, n6012, n6013, n6014, n6015, n6016,
n6017, n6018, n6019, n6020, n6021, n6022, n6023, n6024, n6025, n6026,
n6027, n6028, n6029, n6030, n6031, n6032, n6033, n6034, n6035, n6036,
n6037, n6038, n6039, n6040, n6041, n6042, n6043, n6044, n6045, n6046,
n6047, n6048, n6049, n6050, n6051, n6052, n6053, n6054, n6055, n6056,
n6057, n6058, n6059, n6060, n6061, n6062, n6063, n6064, n6065, n6066,
n6067, n6068, n6069, n6070, n6071, n6072, n6073, n6074, n6075, n6076,
n6077, n6078, n6079, n6080, n6081, n6082, n6083, n6084, n6085, n6086,
n6087, n6088, n6089, n6090, n6091, n6092, n6093, n6094, n6095, n6096,
n6097, n6098, n6099, n6100, n6101, n6102, n6103, n6104, n6105, n6106,
n6107, n6108, n6109, n6110, n6111, n6112, n6113, n6114, n6115, n6116,
n6117, n6118, n6119, n6120, n6121, n6122, n6123, n6124, n6125, n6126,
n6127, n6128, n6129, n6130, n6131, n6132, n6133, n6134, n6135, n6136,
n6137, n6138, n6139, n6140, n6141, n6142, n6143, n6144, n6145, n6146,
n6147, n6148, n6149, n6150, n6151, n6152, n6153, n6154, n6155, n6156,
n6157, n6158, n6159, n6160, n6161, n6162, n6163, n6164, n6165, n6166,
n6167, n6168, n6169, n6170, n6171, n6172, n6173, n6174, n6175, n6176,
n6177, n6178, n6179, n6180, n6181, n6182, n6183, n6184, n6185, n6186,
n6187, n6188, n6189, n6190, n6191, n6192, n6193, n6194, n6195, n6196,
n6197, n6198, n6199, n6200, n6201, n6202, n6203, n6204, n6205, n6206,
n6207, n6208, n6209, n6210, n6211, n6212, n6213, n6214, n6215, n6216,
n6217, n6218, n6219, n6220, n6221, n6222, n6223, n6224, n6225, n6226,
n6227, n6228, n6229, n6230, n6231, n6232, n6233, n6234, n6235, n6236,
n6237, n6238, n6239, n6240, n6241, n6242, n6243, n6244, n6245, n6246,
n6247, n6248, n6249, n6250, n6251, n6252, n6253, n6254, n6255, n6256,
n6257, n6258, n6259, n6260, n6261, n6262, n6263, n6264, n6265, n6266,
n6267, n6268, n6269, n6270, n6271, n6272, n6273, n6274, n6275, n6276,
n6277, n6278, n6279, n6280, n6281, n6282, n6283, n6284, n6285, n6286,
n6287, n6288, n6289, n6290, n6291, n6292, n6293, n6294, n6295, n6296,
n6297, n6298, n6299, n6300, n6301, n6302, n6303, n6304, n6305, n6306,
n6307, n6308, n6309, n6310, n6311, n6312, n6313, n6314, n6315, n6316,
n6317, n6318, n6319, n6320, n6321, n6322, n6323, n6324, n6325, n6326,
n6327, n6328, n6329, n6330, n6331, n6332, n6333, n6334, n6335, n6336,
n6337, n6338, n6339, n6340, n6341, n6342, n6343, n6344, n6345, n6346,
n6347, n6348, n6349, n6350, n6351, n6352, n6353, n6354, n6355, n6356,
n6357, n6358, n6359, n6360, n6361, n6362, n6363, n6364, n6365, n6366,
n6367, n6368, n6369, n6370, n6371, n6372, n6373, n6374, n6375, n6376,
n6377, n6378, n6379, n6380, n6381, n6382, n6383, n6384, n6385, n6386,
n6387, n6388, n6389, n6390, n6391, n6392, n6393, n6394, n6395, n6396,
n6397, n6398, n6399, n6400, n6401, n6402, n6403, n6404, n6405, n6406,
n6407, n6408, n6409, n6410, n6411, n6412, n6413, n6414, n6415, n6416,
n6417, n6418, n6419, n6420, n6421, n6422, n6423, n6424, n6425, n6426,
n6427, n6428, n6429, n6430, n6431, n6432, n6433, n6434, n6435, n6436,
n6437, n6438, n6439, n6440, n6441, n6442, n6443, n6444, n6445, n6446,
n6447, n6448, n6449, n6450, n6451, n6452, n6453, n6454, n6455, n6456,
n6457, n6458, n6459, n6460, n6461, n6462, n6463, n6464, n6465, n6466,
n6467, n6468, n6469, n6470, n6471, n6472, n6473, n6474, n6475, n6476,
n6477, n6478, n6479, n6480, n6481, n6482, n6483, n6484, n6485, n6486,
n6487, n6488, n6489, n6490, n6491, n6492, n6493, n6494, n6495, n6496,
n6497, n6498, n6499, n6500, n6501, n6502, n6503, n6504, n6505, n6506,
n6507, n6508, n6509, n6510, n6511, n6512, n6513, n6514, n6515, n6516,
n6517, n6518, n6519, n6520, n6521, n6522, n6523, n6524, n6525, n6526,
n6527, n6528, n6529, n6530, n6531, n6532, n6533, n6534, n6535, n6536,
n6537, n6538, n6539, n6540, n6541, n6542, n6543, n6544, n6545, n6546,
n6547, n6548, n6549, n6550, n6551, n6552, n6553, n6554, n6555, n6556,
n6557, n6558, n6559, n6560, n6561, n6562, n6563, n6564, n6565, n6566,
n6567, n6568, n6569, n6570, n6571, n6572, n6573, n6574, n6575, n6576,
n6577, n6578, n6579, n6580, n6581, n6582, n6583, n6584, n6585, n6586,
n6587, n6588, n6589, n6590, n6591, n6592, n6593, n6594, n6595, n6596,
n6597, n6598, n6599, n6600, n6601, n6602, n6603, n6604, n6605, n6606,
n6607, n6608, n6609, n6610, n6611, n6612, n6613, n6614, n6615, n6616,
n6617, n6618, n6619, n6620, n6621, n6622, n6623, n6624, n6625, n6626,
n6627, n6628, n6629, n6630, n6631, n6632, n6633, n6634, n6635, n6636,
n6637, n6638, n6639, n6640, n6641, n6642, n6643, n6644, n6645, n6646,
n6647, n6648, n6649, n6650, n6651, n6652, n6653, n6654, n6655, n6656,
n6657, n6658, n6659, n6660, n6661, n6662, n6663, n6664, n6665, n6666,
n6667, n6668, n6669, n6670, n6671, n6672, n6673, n6674, n6675, n6676,
n6677, n6678, n6679, n6680, n6681, n6682, n6683, n6684, n6685, n6686,
n6687, n6688, n6689, n6690, n6691, n6692, n6693, n6694, n6695, n6696,
n6697, n6698, n6699, n6700, n6701, n6702, n6703, n6704, n6705, n6706,
n6707, n6708, n6709, n6710, n6711, n6712, n6713, n6714, n6715, n6716,
n6717, n6718, n6719, n6720, n6721, n6722, n6723, n6724, n6725, n6726,
n6727, n6728, n6729, n6730, n6731, n6732, n6733, n6734, n6735, n6736,
n6737, n6738, n6739, n6740, n6741, n6742, n6743, n6744, n6745, n6746,
n6747, n6748, n6749, n6750, n6751, n6752, n6753, n6754, n6755, n6756,
n6757, n6758, n6759, n6760, n6761, n6762, n6763, n6764, n6765, n6766,
n6767, n6768, n6769, n6770, n6771, n6772, n6773, n6774, n6775, n6776,
n6777, n6778, n6779, n6780, n6781, n6782, n6783, n6784, n6785, n6786,
n6787, n6788, n6789, n6790, n6791, n6792, n6793, n6794, n6795, n6796,
n6797, n6798, n6799, n6800, n6801, n6802, n6803, n6804, n6805, n6806,
n6807, n6808, n6809, n6810, n6811, n6812, n6813, n6814, n6815, n6816,
n6817, n6818, n6819, n6820, n6821, n6822, n6823, n6824, n6825, n6826,
n6827, n6828, n6829, n6830, n6831, n6832, n6833, n6834, n6835, n6836,
n6837, n6838, n6839, n6840, n6841, n6842, n6843, n6844, n6845, n6846,
n6847, n6848, n6849, n6850, n6851, n6852, n6853, n6854, n6855, n6856,
n6857, n6858, n6859, n6860, n6861, n6862, n6863, n6864, n6865, n6866,
n6867, n6868, n6869, n6870, n6871, n6872, n6873, n6874, n6875, n6876,
n6877, n6878, n6879, n6880, n6881, n6882, n6883, n6884, n6885, n6886,
n6887, n6888, n6889, n6890, n6891, n6892, n6893, n6894, n6895, n6896,
n6897, n6898, n6899, n6900, n6901, n6902, n6903, n6904, n6905, n6906,
n6907, n6908, n6909, n6910, n6911, n6912, n6913, n6914, n6915, n6916,
n6917, n6918, n6919, n6920, n6921, n6922, n6923, n6924, n6925, n6926,
n6927, n6928, n6929, n6930, n6931, n6932, n6933, n6934, n6935, n6936,
n6937, n6938, n6939, n6940, n6941, n6942, n6943, n6944, n6945, n6946,
n6947, n6948, n6949, n6950, n6951, n6952, n6953, n6954, n6955, n6956,
n6957, n6958, n6959, n6960, n6961, n6962, n6963, n6964, n6965, n6966,
n6967, n6968, n6969, n6970, n6971, n6972, n6973, n6974, n6975, n6976,
n6977, n6978, n6979, n6980, n6981, n6982, n6983, n6984, n6985, n6986,
n6987, n6988, n6989, n6990, n6991, n6992, n6993, n6994, n6995, n6996,
n6997, n6998, n6999, n7000, n7001, n7002, n7003, n7004, n7005, n7006,
n7007, n7008, n7009, n7010, n7011, n7012, n7013, n7014, n7015, n7016,
n7017, n7018, n7019, n7020, n7021, n7022, n7023, n7024, n7025, n7026,
n7027, n7028, n7029, n7030, n7031, n7032, n7033, n7034, n7035, n7036,
n7037, n7038, n7039, n7040, n7041, n7042, n7043, n7044, n7045, n7046,
n7047, n7048, n7049, n7050, n7051, n7052, n7053, n7054, n7055, n7056,
n7057, n7058, n7059, n7060, n7061, n7062, n7063, n7064, n7065, n7066,
n7067, n7068, n7069, n7070, n7071, n7072, n7073, n7074, n7075, n7076,
n7077, n7078, n7079, n7080, n7081, n7082, n7083, n7084, n7085, n7086,
n7087, n7088, n7089, n7090, n7091, n7092, n7093, n7094, n7095, n7096,
n7097, n7098, n7099, n7100, n7101, n7102, n7103, n7104, n7105, n7106,
n7107, n7108, n7109, n7110, n7111, n7112, n7113, n7114, n7115, n7116,
n7117, n7118, n7119, n7120, n7121, n7122, n7123, n7124, n7125, n7126,
n7127, n7128, n7129, n7130, n7131, n7132, n7133, n7134, n7135, n7136,
n7137, n7138, n7139, n7140, n7141, n7142, n7143, n7144, n7145, n7146,
n7147, n7148, n7149, n7150, n7151, n7152, n7153, n7154, n7155, n7156,
n7157, n7158, n7159, n7160, n7161, n7162, n7163, n7164, n7165, n7166,
n7167, n7168, n7169, n7170, n7171, n7172, n7173, n7174, n7175, n7176,
n7177, n7178, n7179, n7180, n7181, n7182, n7183, n7184, n7185, n7186,
n7187, n7188, n7189, n7190, n7191, n7192, n7193, n7194, n7195, n7196,
n7197, n7198, n7199, n7200, n7201, n7202, n7203, n7204, n7205, n7206,
n7207, n7208, n7209, n7210, n7211, n7212, n7213, n7214, n7215, n7216,
n7217, n7218, n7219, n7220, n7221, n7222, n7223, n7224, n7225, n7226,
n7227, n7228, n7229, n7230, n7231, n7232, n7233, n7234, n7235, n7236,
n7237, n7238, n7239, n7240, n7241, n7242, n7243, n7244, n7245, n7246,
n7247, n7248, n7249, n7250, n7251, n7252, n7253, n7254, n7255, n7256,
n7257, n7258, n7259, n7260, n7261, n7262, n7263, n7264, n7265, n7266,
n7267, n7268, n7269, n7270, n7271, n7272, n7273, n7274, n7275, n7276,
n7277, n7278, n7279, n7280, n7281, n7282, n7283, n7284, n7285, n7286,
n7287, n7288, n7289, n7290, n7291, n7292, n7293, n7294, n7295, n7296,
n7297, n7298, n7299, n7300, n7301, n7302, n7303, n7304, n7305, n7306,
n7307, n7308, n7309, n7310, n7311, n7312, n7313, n7314, n7315, n7316,
n7317, n7318, n7319, n7320, n7321, n7322, n7323, n7324, n7325, n7327,
n7328, n7329, n7330, n7331, n7332, n7333, n7334, n7335, n7336, n7337,
n7338, n7339, n7340, n7341, n7342, n7343, n7344, n7345, n7346, n7347,
n7348, n7349, n7350, n7351, n7352, n7353, n7354, n7355, n7356, n7357,
n7358, n7359, n7360, n7361, n7362, n7363, n7364, n7365, n7366, n7367,
n7368, n7369, n7370, n7371, n7372, n7373, n7374, n7375, n7376, n7377,
n7378, n7379, n7380, n7381, n7382, n7383, n7384, n7385, n7386, n7387,
n7388, n7389, n7390, n7391, n7392, n7393, n7394, n7395, n7396, n7397,
n7398, n7399, n7400, n7401, n7402, n7403, n7404, n7405, n7406, n7407,
n7408, n7409, n7410, n7411, n7412, n7413, n7414, n7415, n7416, n7417,
n7418, n7419, n7420, n7421, n7422, n7423, n7424, n7425, n7426, n7427,
n7428, n7429, n7430, n7431, n7432, n7433, n7434, n7435, n7436, n7437,
n7438, n7439, n7440, n7441, n7442, n7443, n7444, n7445, n7446, n7447,
n7448, n7449, n7450, n7451, n7452, n7453, n7454, n7455, n7456, n7457,
n7458, n7459, n7460, n7461, n7462, n7463, n7464, n7465, n7466, n7467,
n7468, n7469, n7470, n7471, n7472, n7473, n7474, n7475, n7476, n7477,
n7478, n7479, n7480, n7481, n7482, n7483, n7484, n7485, n7486, n7487,
n7488, n7489, n7490, n7491, n7492, n7493, n7494, n7495, n7496, n7497,
n7498, n7499, n7500, n7501, n7502, n7503, n7504, n7505, n7506, n7507,
n7508, n7509, n7510, n7511, n7512, n7513, n7514, n7515, n7516, n7517,
n7518, n7519, n7520, n7521, n7522, n7523, n7524, n7525, n7526, n7527,
n7528, n7529, n7530, n7531, n7532, n7533, n7534, n7535, n7536, n7537,
n7538, n7539, n7540, n7541, n7542, n7543, n7544, n7545, n7546, n7547,
n7548, n7549, n7550, n7551, n7552, n7553, n7554, n7555, n7556, n7557,
n7558, n7559, n7560, n7561, n7562, n7563, n7564, n7565, n7566, n7567,
n7568, n7569, n7570, n7571, n7572, n7573, n7574, n7575, n7576, n7577,
n7578, n7579, n7580, n7581, n7582, n7583, n7584, n7585, n7586, n7587,
n7588, n7589, n7590, n7591, n7592, n7593, n7594, n7595, n7596, n7597,
n7598, n7599, n7600, n7601, n7602, n7603, n7604, n7605, n7606, n7607,
n7608, n7609, n7610, n7611, n7612, n7613, n7614, n7615, n7616, n7617,
n7618, n7619, n7620, n7621, n7622, n7623, n7624, n7625, n7626, n7627,
n7628, n7629, n7630, n7631, n7632, n7633, n7634, n7635, n7636, n7637,
n7638, n7639, n7640, n7641, n7642, n7643, n7644, n7645, n7646, n7647,
n7648, n7649, n7650, n7651, n7652, n7653, n7654, n7655, n7656, n7657,
n7658, n7659, n7660, n7661, n7662, n7663, n7664, n7665, n7666, n7667,
n7668, n7673, n7674, n7675, n7676, n7677, n7678, n7679, n7680, n7681,
n7682, n7683, n7684, n7685, n7686, n7687, n7688, n7689, n7690, n7691,
n7692, n7693, n7694, n7695, n7696, n7697, n7698, n7699, n7700, n7701,
n7702, n7703, n7704, n7705, n7706, n7707, n7708, n7709, n7710, n7711,
n7712, n7713, n7714, n7715, n7716, n7717, n7718, n7719, n7720, n7721,
n7722, n7723, n7724, n7725, n7726, n7727, n7728, n7729, n7730, n7731,
n7732, n7733, n7734, n7735, n7736, n7737, n7738, n7739, n7740, n7741,
n7742, n7743, n7744, n7745, n7746, n7747, n7748, n7749, n7750, n7751,
n7752, n7753, n7754, n7755, n7756, n7757, n7758, n7759, n7760, n7761,
n7762, n7763, n7764, n7765, n7766, n7767, n7768, n7769, n7770, n7771,
n7772, n7773, n7774, n7775, n7776, n7777, n7778, n7779, n7780, n7781,
n7782, n7783, n7784, n7785, n7786, n7787, n7788, n7789, n7790, n7791,
n7792, n7793, n7794, n7795, n7796, n7797, n7798, n7799, n7800, n7801,
n7802, n7803, n7804, n7805, n7806, n7807, n7808, n7809, n7810, n7811,
n7812, n7813, n7814, n7815, n7816, n7817, n7818, n7819, n7820, n7821,
n7822, n7823, n7824, n7825, n7826, n7827, n7828, n7829, n7830, n7831,
n7832, n7833, n7834, n7835, n7836, n7837, n7838, n7839, n7840, n7841,
n7842, n7843, n7844, n7845, n7846, n7847, n7848, n7849, n7850, n7851,
n7852, n7853, n7854, n7855, n7856, n7857, n7858, n7859, n7860, n7861,
n7862, n7863, n7864, n7865, n7866, n7867, n7868, n7869, n7870, n7871,
n7872, n7873, n7874, n7875, n7876, n7877, n7878, n7879, n7880, n7881,
n7882, n7883, n7884, n7885, n7886, n7887, n7888, n7889, n7890, n7891,
n7892, n7893, n7894, n7895, n7896, n7897, n7898, n7899, n7900, n7901,
n7902, n7903, n7904, n7905, n7906, n7907, n7908, n7909, n7910, n7911,
n7912, n7913, n7914, n7915, n7916, n7917, n7918, n7919, n7920, n7921,
n7922, n7923, n7924, n7925, n7926, n7927, n7928, n7929, n7930, n7931,
n7932, n7933, n7934, n7935, n7936, n7937, n7938, n7939, n7940, n7941,
n7942, n7943, n7944, n7945, n7946, n7947, n7948, n7949, n7950, n7951,
n7952, n7953, n7954, n7955, n7956, n7957, n7958, n7959, n7960, n7961,
n7962, n7963, n7964, n7965, n7966, n7967, n7968, n7969, n7970, n7971,
n7972, n7973, n7974, n7975, n7976, n7977, n7978, n7979, n7980, n7981,
n7982, n7983, n7984, n7985, n7986, n7987, n7988, n7989, n7990, n7991,
n7992, n7993, n7994, n7995, n7996, n7997, n7998, n7999, n8000, n8001,
n8002, n8003, n8004, n8005, n8006, n8007, n8008, n8009, n8010, n8011,
n8012, n8013, n8014, n8015, n8016, n8017, n8018, n8019, n8020, n8021,
n8022, n8023, n8024, n8025, n8026, n8027, n8028, n8029, n8030, n8031,
n8032, n8033, n8034, n8035, n8036, n8037, n8038, n8039, n8040, n8041,
n8042, n8043, n8044, n8045, n8046, n8047, n8048, n8049, n8050, n8051,
n8052, n8053, n8054, n8055, n8056, n8057, n8058, n8059, n8060, n8061,
n8062, n8063, n8064, n8065, n8066, n8067, n8068, n8069, n8070, n8071,
n8072, n8073, n8074, n8075, n8076, n8077, n8078, n8079, n8080, n8081,
n8082, n8083, n8084, n8085, n8086, n8087, n8088, n8089, n8090, n8091,
n8092, n8093, n8094, n8095, n8096, n8097, n8098, n8099, n8100, n8101,
n8102, n8103, n8104, n8105, n8106, n8107, n8108, n8109, n8110, n8111,
n8112, n8113, n8114, n8115, n8116, n8117, n8118, n8119, n8120, n8121,
n8122, n8123, n8124, n8125, n8126, n8127, n8128, n8129, n8130, n8131,
n8132, n8133, n8134, n8135, n8136, n8137, n8138, n8139, n8140, n8141,
n8142, n8143, n8144, n8145, n8146, n8147, n8148, n8149, n8150, n8151,
n8152, n8153, n8154, n8155, n8156, n8157, n8158, n8159, n8160, n8161,
n8162, n8163, n8164, n8165, n8166, n8167, n8168, n8169, n8170, n8171,
n8172, n8173, n8174, n8175, n8176, n8177, n8178, n8179, n8180, n8181,
n8182, n8183, n8184, n8185, n8186, n8187, n8188, n8189, n8190, n8191,
n8192, n8193, n8194, n8195, n8196, n8197, n8198, n8199, n8200, n8201,
n8202, n8203, n8204, n8205, n8206, n8207, n8208, n8209, n8210, n8211,
n8212, n8213, n8214, n8215, n8216, n8217, n8218, n8219, n8220, n8221,
n8222, n8223, n8224, n8225, n8226, n8227, n8228, n8229, n8230, n8231,
n8232, n8233, n8234, n8235, n8236, n8237, n8238, n8239, n8240, n8241,
n8242, n8243, n8244, n8245, n8246, n8247, n8248, n8249, n8250, n8251,
n8252, n8253, n8254, n8255, n8256, n8257, n8258, n8259, n8260, n8261,
n8262, n8263, n8264, n8265, n8266, n8267, n8268, n8269, n8270, n8271,
n8272, n8273, n8274, n8275, n8276, n8277, n8278, n8279, n8280, n8281,
n8282, n8283, n8284, n8285, n8286, n8287, n8288, n8289, n8290, n8291,
n8292, n8293, n8294, n8295, n8296, n8297, n8298, n8299, n8300, n8301,
n8302, n8303, n8304, n8305, n8306, n8307, n8308, n8309, n8310, n8311,
n8312, n8313, n8314, n8315, n8316, n8317, n8318, n8319, n8320, n8321,
n8322, n8323, n8324, n8325, n8326, n8327, n8328, n8329, n8330, n8331,
n8332, n8333, n8334, n8335, n8336, n8337, n8338, n8339, n8340, n8341,
n8342, n8343, n8344, n8345, n8346, n8347, n8348, n8349, n8350, n8351,
n8352, n8353, n8354, n8355, n8356, n8357, n8358, n8359, n8360, n8361,
n8362, n8363, n8364, n8365, n8366, n8367, n8368, n8369, n8370, n8371,
n8372, n8373, n8374, n8375, n8376, n8377, n8378, n8379, n8380, n8381,
n8382, n8383, n8384, n8385, n8386, n8387, n8388, n8389, n8390, n8391,
n8392, n8393, n8394, n8395, n8396, n8397, n8398, n8399, n8400, n8401,
n8402, n8403, n8404, n8405, n8406, n8407, n8408, n8409, n8410, n8411,
n8412, n8413, n8414, n8415, n8416, n8417, n8418, n8419, n8420, n8421,
n8422, n8423, n8424, n8425, n8426, n8427, n8428, n8429, n8430, n8431,
n8432, n8433, n8434, n8435, n8436, n8437, n8438, n8439, n8440, n8441,
n8442, n8443, n8444, n8445, n8446, n8447, n8448, n8449, n8450, n8451,
n8452, n8453, n8454, n8455, n8456, n8457, n8458, n8459, n8460, n8461,
n8462, n8463, n8464, n8465, n8466, n8467, n8468, n8469, n8470, n8471,
n8472, n8473, n8474, n8475, n8476, n8477, n8478, n8479, n8480, n8481,
n8482, n8483, n8484, n8485, n8486, n8487, n8488, n8489, n8490, n8491,
n8492, n8493, n8494, n8495, n8496, n8497, n8498, n8499, n8500, n8501,
n8502, n8503, n8504, n8505, n8506, n8507, n8508, n8509, n8510, n8511,
n8512, n8513, n8514, n8515, n8516, n8517, n8518, n8519, n8520, n8521,
n8522, n8523, n8524, n8525, n8526, n8527, n8528, n8529, n8530, n8531,
n8532, n8533, n8534, n8535, n8536, n8537, n8538, n8539, n8540, n8541,
n8542, n8543, n8544, n8545, n8546, n8547, n8548, n8549, n8550, n8551,
n8552, n8553, n8554, n8555, n8556, n8557, n8558, n8559, n8560, n8561,
n8562, n8563, n8564, n8565, n8566, n8567, n8568, n8569, n8570, n8571,
n8572, n8573, n8574, n8575, n8576, n8577, n8578, n8579, n8580, n8581,
n8582, n8583, n8584, n8585, n8586, n8587, n8588, n8589, n8590, n8591,
n8592, n8593, n8594, n8595, n8596, n8597, n8598, n8599, n8600, n8601,
n8602, n8603, n8604, n8605, n8606, n8607, n8608, n8609, n8610, n8611,
n8612, n8614, n8615, n8616, n8617, n8618, n8619, n8620, n8621, n8622,
n8623, n8624, n8625, n8626, n8627, n8628, n8629, n8630, n8631, n8632,
n8633, n8634, n8635, n8636, n8637, n8638, n8639, n8640, n8641, n8642,
n8643, n8644, n8645, n8646, n8647, n8648, n8649, n8650, n8651, n8652,
n8653, n8654, n8655, n8656, n8657, n8658, n8659, n8660, n8661, n8662,
n8663, n8664, n8665, n8666, n8667, n8668, n8669, n8670, n8671, n8672,
n8673, n8674, n8675, n8676, n8677, n8678, n8679, n8680, n8681, n8682,
n8683, n8684, n8685, n8686, n8687, n8688, n8689, n8690, n8691, n8692,
n8693, n8694, n8695, n8696, n8697, n8698, n8699, n8700, n8701, n8702,
n8703, n8704, n8705, n8706, n8707, n8708, n8709, n8710, n8711, n8712,
n8713, n8714, n8715, n8716, n8717, n8718, n8719, n8720, n8721, n8722,
n8723, n8724, n8725, n8726, n8727, n8728, n8729, n8730, n8731, n8732,
n8733, n8734, n8735, n8736, n8737, n8738, n8739, n8740, n8741, n8742,
n8743, n8744, n8745, n8746, n8747, n8748, n8749, n8750, n8751, n8752,
n8753, n8754, n8755, n8756, n8757, n8758, n8759, n8760, n8761, n8762,
n8763, n8764, n8765, n8766, n8767, n8768, n8769, n8770, n8771, n8772,
n8773, n8774, n8775, n8776, n8777, n8778, n8779, n8780, n8781, n8782,
n8783, n8784, n8785, n8786, n8787, n8788, n8789, n8790, n8791, n8792,
n8793, n8794, n8795, n8796, n8797, n8798, n8799, n8800, n8801, n8802,
n8803, n8804, n8805, n8806, n8807, n8808, n8809, n8810, n8811, n8812,
n8813, n8814, n8815, n8816, n8817, n8818, n8819, n8820, n8821, n8822,
n8823, n8824, n8825, n8826, n8827, n8828, n8829, n8830, n8831, n8832,
n8833, n8834, n8835, n8836, n8837;
wire [1:0] operation_reg;
wire [31:23] dataA;
wire [31:23] dataB;
wire [31:0] cordic_result;
wire [31:0] result_add_subt;
wire [31:0] mult_result;
wire [27:0] FPSENCOS_d_ff3_LUT_out;
wire [31:0] FPSENCOS_d_ff3_sh_y_out;
wire [31:0] FPSENCOS_d_ff3_sh_x_out;
wire [31:0] FPSENCOS_d_ff2_Z;
wire [31:0] FPSENCOS_d_ff2_Y;
wire [31:0] FPSENCOS_d_ff2_X;
wire [31:0] FPSENCOS_d_ff_Zn;
wire [31:0] FPSENCOS_d_ff_Yn;
wire [31:0] FPSENCOS_d_ff_Xn;
wire [31:0] FPSENCOS_d_ff1_Z;
wire [1:0] FPSENCOS_d_ff1_shift_region_flag_out;
wire [1:0] FPSENCOS_cont_var_out;
wire [3:1] FPSENCOS_cont_iter_out;
wire [23:0] FPMULT_Sgf_normalized_result;
wire [21:0] FPMULT_Add_result;
wire [8:0] FPMULT_exp_oper_result;
wire [31:4] FPMULT_Op_MY;
wire [31:4] FPMULT_Op_MX;
wire [1:0] FPMULT_FSM_selector_B;
wire [24:0] FPMULT_P_Sgf;
wire [25:1] FPADDSUB_DmP_mant_SFG_SWR;
wire [30:0] FPADDSUB_DMP_SFG;
wire [7:0] FPADDSUB_exp_rslt_NRM2_EW1;
wire [4:0] FPADDSUB_LZD_output_NRM2_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM_EW;
wire [7:0] FPADDSUB_DMP_exp_NRM2_EW;
wire [4:2] FPADDSUB_shift_value_SHT2_EWR;
wire [30:0] FPADDSUB_DMP_SHT2_EWSW;
wire [25:0] FPADDSUB_Raw_mant_NRM_SWR;
wire [4:0] FPADDSUB_Shift_amount_SHT1_EWR;
wire [22:0] FPADDSUB_DmP_mant_SHT1_SW;
wire [30:0] FPADDSUB_DMP_SHT1_EWSW;
wire [3:1] FPADDSUB_Shift_reg_FLAGS_7;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_next;
wire [7:0] FPSENCOS_inst_CORDIC_FSM_v3_state_reg;
wire [3:0] FPMULT_FS_Module_state_reg;
wire [27:25] FPMULT_Sgf_operation_Result;
wire [21:17] FPMULT_Sgf_operation_EVEN1_S_B;
wire [13:5] FPMULT_Sgf_operation_EVEN1_Q_left;
wire [22:3] FPMULT_Adder_M_result_A_adder;
wire [2:0] FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg;
DFFRXLTS reg_dataA_Q_reg_28_ ( .D(Data_1[28]), .CK(clk), .RN(n8577), .Q(
dataA[28]) );
DFFRXLTS reg_dataA_Q_reg_31_ ( .D(Data_1[31]), .CK(clk), .RN(n8577), .Q(
dataA[31]) );
DFFRXLTS reg_dataB_Q_reg_24_ ( .D(Data_2[24]), .CK(clk), .RN(n8576), .Q(
dataB[24]) );
DFFRXLTS reg_dataB_Q_reg_26_ ( .D(Data_2[26]), .CK(clk), .RN(n8575), .Q(
dataB[26]) );
DFFRXLTS reg_dataB_Q_reg_27_ ( .D(Data_2[27]), .CK(clk), .RN(n8575), .Q(
dataB[27]) );
DFFRXLTS reg_dataB_Q_reg_29_ ( .D(Data_2[29]), .CK(clk), .RN(n8575), .Q(
dataB[29]) );
DFFRXLTS reg_dataB_Q_reg_30_ ( .D(Data_2[30]), .CK(clk), .RN(n8575), .Q(
dataB[30]) );
DFFRXLTS reg_dataB_Q_reg_31_ ( .D(Data_2[31]), .CK(clk), .RN(n8575), .Q(
dataB[31]) );
DFFRXLTS FPSENCOS_ITER_CONT_temp_reg_0_ ( .D(n2143), .CK(clk), .RN(n8575),
.Q(n2332), .QN(n7798) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_5_ ( .D(n2149), .CK(clk), .RN(
n7990), .Q(FPADDSUB_Shift_reg_FLAGS_7_5), .QN(n7876) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_3_ ( .D(n2147), .CK(clk), .RN(
n8544), .Q(FPADDSUB_Shift_reg_FLAGS_7[3]), .QN(n7855) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_2_ ( .D(n2146), .CK(clk), .RN(
n2400), .Q(FPADDSUB_Shift_reg_FLAGS_7[2]), .QN(n3179) );
DFFRXLTS FPADDSUB_inst_ShiftRegister_Q_reg_1_ ( .D(n2145), .CK(clk), .RN(
n8546), .Q(FPADDSUB_Shift_reg_FLAGS_7[1]), .QN(n2296) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_0_ ( .D(n2135), .CK(clk), .RN(n8573), .Q(
FPSENCOS_d_ff3_LUT_out[0]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_1_ ( .D(n2134), .CK(clk), .RN(n8573), .Q(
FPSENCOS_d_ff3_LUT_out[1]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_2_ ( .D(n2133), .CK(clk), .RN(n8573), .Q(
FPSENCOS_d_ff3_LUT_out[2]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_3_ ( .D(n2132), .CK(clk), .RN(n8573), .Q(
FPSENCOS_d_ff3_LUT_out[3]), .QN(n7909) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_4_ ( .D(n2131), .CK(clk), .RN(n8573), .Q(
FPSENCOS_d_ff3_LUT_out[4]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_5_ ( .D(n2130), .CK(clk), .RN(n8573), .Q(
FPSENCOS_d_ff3_LUT_out[5]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_6_ ( .D(n2129), .CK(clk), .RN(n8573), .Q(
FPSENCOS_d_ff3_LUT_out[6]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_7_ ( .D(n2128), .CK(clk), .RN(n8572), .Q(
FPSENCOS_d_ff3_LUT_out[7]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_8_ ( .D(n2127), .CK(clk), .RN(n8572), .Q(
FPSENCOS_d_ff3_LUT_out[8]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_9_ ( .D(n2126), .CK(clk), .RN(n8572), .Q(
FPSENCOS_d_ff3_LUT_out[9]), .QN(n7910) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_10_ ( .D(n2125), .CK(clk), .RN(n8572), .Q(
FPSENCOS_d_ff3_LUT_out[10]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_12_ ( .D(n2124), .CK(clk), .RN(n8572), .Q(
FPSENCOS_d_ff3_LUT_out[12]), .QN(n7912) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_13_ ( .D(n2123), .CK(clk), .RN(n8572), .Q(
FPSENCOS_d_ff3_LUT_out[13]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_15_ ( .D(n2122), .CK(clk), .RN(n8572), .Q(
FPSENCOS_d_ff3_LUT_out[15]), .QN(n7911) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_19_ ( .D(n2121), .CK(clk), .RN(n8572), .Q(
FPSENCOS_d_ff3_LUT_out[19]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_21_ ( .D(n2120), .CK(clk), .RN(n8572), .Q(
FPSENCOS_d_ff3_LUT_out[21]), .QN(n7913) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_23_ ( .D(n2119), .CK(clk), .RN(n8572), .Q(
FPSENCOS_d_ff3_LUT_out[23]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_24_ ( .D(n2118), .CK(clk), .RN(n8571), .Q(
FPSENCOS_d_ff3_LUT_out[24]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_25_ ( .D(n2117), .CK(clk), .RN(n8571), .Q(
FPSENCOS_d_ff3_LUT_out[25]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_26_ ( .D(n2116), .CK(clk), .RN(n8571), .Q(
FPSENCOS_d_ff3_LUT_out[26]) );
DFFRXLTS FPSENCOS_reg_LUT_Q_reg_27_ ( .D(n2115), .CK(clk), .RN(n8571), .Q(
FPSENCOS_d_ff3_LUT_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_23_ ( .D(n1855), .CK(clk), .RN(n8571),
.Q(FPSENCOS_d_ff3_sh_y_out[23]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_24_ ( .D(n1854), .CK(clk), .RN(n8571),
.Q(FPSENCOS_d_ff3_sh_y_out[24]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_25_ ( .D(n1853), .CK(clk), .RN(n8571),
.Q(FPSENCOS_d_ff3_sh_y_out[25]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_26_ ( .D(n1852), .CK(clk), .RN(n8571),
.Q(FPSENCOS_d_ff3_sh_y_out[26]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_27_ ( .D(n1851), .CK(clk), .RN(n8571),
.Q(FPSENCOS_d_ff3_sh_y_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_28_ ( .D(n1850), .CK(clk), .RN(n8571),
.Q(FPSENCOS_d_ff3_sh_y_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_29_ ( .D(n1849), .CK(clk), .RN(n8570),
.Q(FPSENCOS_d_ff3_sh_y_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_30_ ( .D(n1848), .CK(clk), .RN(n8570),
.Q(FPSENCOS_d_ff3_sh_y_out[30]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_23_ ( .D(n1953), .CK(clk), .RN(n8570),
.Q(FPSENCOS_d_ff3_sh_x_out[23]), .QN(n7925) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_24_ ( .D(n1952), .CK(clk), .RN(n8570),
.Q(FPSENCOS_d_ff3_sh_x_out[24]), .QN(n7926) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_25_ ( .D(n1951), .CK(clk), .RN(n8570),
.Q(FPSENCOS_d_ff3_sh_x_out[25]), .QN(n7927) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_26_ ( .D(n1950), .CK(clk), .RN(n8570),
.Q(FPSENCOS_d_ff3_sh_x_out[26]), .QN(n7928) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_27_ ( .D(n1949), .CK(clk), .RN(n8570),
.Q(FPSENCOS_d_ff3_sh_x_out[27]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_28_ ( .D(n1948), .CK(clk), .RN(n8570),
.Q(FPSENCOS_d_ff3_sh_x_out[28]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_29_ ( .D(n1947), .CK(clk), .RN(n8570),
.Q(FPSENCOS_d_ff3_sh_x_out[29]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_30_ ( .D(n1946), .CK(clk), .RN(n8570),
.Q(FPSENCOS_d_ff3_sh_x_out[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_0_ ( .D(n2114), .CK(clk), .RN(n8575), .Q(
FPSENCOS_d_ff1_Z[0]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_1_ ( .D(n2113), .CK(clk), .RN(n8590), .Q(
FPSENCOS_d_ff1_Z[1]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_2_ ( .D(n2112), .CK(clk), .RN(n8590), .Q(
FPSENCOS_d_ff1_Z[2]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_3_ ( .D(n2111), .CK(clk), .RN(n8590), .Q(
FPSENCOS_d_ff1_Z[3]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_4_ ( .D(n2110), .CK(clk), .RN(n8590), .Q(
FPSENCOS_d_ff1_Z[4]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_5_ ( .D(n2109), .CK(clk), .RN(n8590), .Q(
FPSENCOS_d_ff1_Z[5]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_6_ ( .D(n2108), .CK(clk), .RN(n8590), .Q(
FPSENCOS_d_ff1_Z[6]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_7_ ( .D(n2107), .CK(clk), .RN(n8590), .Q(
FPSENCOS_d_ff1_Z[7]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_8_ ( .D(n2106), .CK(clk), .RN(n8590), .Q(
FPSENCOS_d_ff1_Z[8]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_9_ ( .D(n2105), .CK(clk), .RN(n8589), .Q(
FPSENCOS_d_ff1_Z[9]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_10_ ( .D(n2104), .CK(clk), .RN(n8589), .Q(
FPSENCOS_d_ff1_Z[10]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_11_ ( .D(n2103), .CK(clk), .RN(n8589), .Q(
FPSENCOS_d_ff1_Z[11]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_12_ ( .D(n2102), .CK(clk), .RN(n8589), .Q(
FPSENCOS_d_ff1_Z[12]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_13_ ( .D(n2101), .CK(clk), .RN(n8589), .Q(
FPSENCOS_d_ff1_Z[13]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_14_ ( .D(n2100), .CK(clk), .RN(n8589), .Q(
FPSENCOS_d_ff1_Z[14]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_15_ ( .D(n2099), .CK(clk), .RN(n8589), .Q(
FPSENCOS_d_ff1_Z[15]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_16_ ( .D(n2098), .CK(clk), .RN(n8589), .Q(
FPSENCOS_d_ff1_Z[16]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_17_ ( .D(n2097), .CK(clk), .RN(n8589), .Q(
FPSENCOS_d_ff1_Z[17]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_18_ ( .D(n2096), .CK(clk), .RN(n8589), .Q(
FPSENCOS_d_ff1_Z[18]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_19_ ( .D(n2095), .CK(clk), .RN(n8588), .Q(
FPSENCOS_d_ff1_Z[19]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_20_ ( .D(n2094), .CK(clk), .RN(n8588), .Q(
FPSENCOS_d_ff1_Z[20]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_21_ ( .D(n2093), .CK(clk), .RN(n8588), .Q(
FPSENCOS_d_ff1_Z[21]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_22_ ( .D(n2092), .CK(clk), .RN(n8588), .Q(
FPSENCOS_d_ff1_Z[22]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_23_ ( .D(n2091), .CK(clk), .RN(n8588), .Q(
FPSENCOS_d_ff1_Z[23]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_24_ ( .D(n2090), .CK(clk), .RN(n8588), .Q(
FPSENCOS_d_ff1_Z[24]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_25_ ( .D(n2089), .CK(clk), .RN(n8588), .Q(
FPSENCOS_d_ff1_Z[25]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_26_ ( .D(n2088), .CK(clk), .RN(n8588), .Q(
FPSENCOS_d_ff1_Z[26]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_27_ ( .D(n2087), .CK(clk), .RN(n8588), .Q(
FPSENCOS_d_ff1_Z[27]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_28_ ( .D(n2086), .CK(clk), .RN(n8588), .Q(
FPSENCOS_d_ff1_Z[28]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_29_ ( .D(n2085), .CK(clk), .RN(n8587), .Q(
FPSENCOS_d_ff1_Z[29]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_30_ ( .D(n2084), .CK(clk), .RN(n8587), .Q(
FPSENCOS_d_ff1_Z[30]) );
DFFRXLTS FPSENCOS_reg_Z0_Q_reg_31_ ( .D(n2083), .CK(clk), .RN(n8587), .Q(
FPSENCOS_d_ff1_Z[31]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_23_ ( .D(n1788), .CK(clk), .RN(n8587), .Q(
FPSENCOS_d_ff_Zn[23]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_23_ ( .D(n1743), .CK(clk), .RN(
n8587), .Q(FPSENCOS_d_ff2_Z[23]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_23_ ( .D(n1863), .CK(clk), .RN(
n8587), .Q(FPSENCOS_d_ff2_Y[23]), .QN(n7796) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_24_ ( .D(n1785), .CK(clk), .RN(n8586), .Q(
FPSENCOS_d_ff_Zn[24]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_24_ ( .D(n1742), .CK(clk), .RN(
n8586), .Q(FPSENCOS_d_ff2_Z[24]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_24_ ( .D(n1704), .CK(clk), .RN(n8586),
.Q(cordic_result[24]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_25_ ( .D(n1782), .CK(clk), .RN(n8586), .Q(
FPSENCOS_d_ff_Zn[25]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_25_ ( .D(n1741), .CK(clk), .RN(
n8586), .Q(FPSENCOS_d_ff2_Z[25]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_26_ ( .D(n1779), .CK(clk), .RN(n8585), .Q(
FPSENCOS_d_ff_Zn[26]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_26_ ( .D(n1740), .CK(clk), .RN(
n8585), .Q(FPSENCOS_d_ff2_Z[26]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_27_ ( .D(n1776), .CK(clk), .RN(n8584), .Q(
FPSENCOS_d_ff_Zn[27]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_27_ ( .D(n1739), .CK(clk), .RN(
n8584), .Q(FPSENCOS_d_ff2_Z[27]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_28_ ( .D(n1773), .CK(clk), .RN(n8583), .Q(
FPSENCOS_d_ff_Zn[28]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_28_ ( .D(n1738), .CK(clk), .RN(
n8583), .Q(FPSENCOS_d_ff2_Z[28]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_28_ ( .D(n1858), .CK(clk), .RN(
n8583), .Q(FPSENCOS_d_ff2_Y[28]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_28_ ( .D(n1700), .CK(clk), .RN(n8583),
.Q(cordic_result[28]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_29_ ( .D(n1770), .CK(clk), .RN(n8583), .Q(
FPSENCOS_d_ff_Zn[29]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_29_ ( .D(n1737), .CK(clk), .RN(
n8583), .Q(FPSENCOS_d_ff2_Z[29]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_30_ ( .D(n1767), .CK(clk), .RN(n8582), .Q(
FPSENCOS_d_ff_Zn[30]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_30_ ( .D(n1736), .CK(clk), .RN(
n8582), .Q(FPSENCOS_d_ff2_Z[30]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_22_ ( .D(n2010), .CK(clk), .RN(n8581), .Q(
FPSENCOS_d_ff_Zn[22]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_22_ ( .D(n1744), .CK(clk), .RN(
n8581), .Q(FPSENCOS_d_ff2_Z[22]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_22_ ( .D(n1865), .CK(clk), .RN(
n8581), .Q(FPSENCOS_d_ff2_Y[22]), .QN(n7896) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_22_ ( .D(n1864), .CK(clk), .RN(n8581),
.Q(FPSENCOS_d_ff3_sh_y_out[22]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_22_ ( .D(n1962), .CK(clk), .RN(n8581),
.Q(FPSENCOS_d_ff3_sh_x_out[22]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_15_ ( .D(n2031), .CK(clk), .RN(n8581), .Q(
FPSENCOS_d_ff_Zn[15]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_15_ ( .D(n1751), .CK(clk), .RN(
n8580), .Q(FPSENCOS_d_ff2_Z[15]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_15_ ( .D(n1879), .CK(clk), .RN(
n8580), .Q(FPSENCOS_d_ff2_Y[15]), .QN(n7897) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_15_ ( .D(n1878), .CK(clk), .RN(n8580),
.Q(FPSENCOS_d_ff3_sh_y_out[15]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_15_ ( .D(n1976), .CK(clk), .RN(n8580),
.Q(FPSENCOS_d_ff3_sh_x_out[15]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_18_ ( .D(n2022), .CK(clk), .RN(n8580), .Q(
FPSENCOS_d_ff_Zn[18]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_18_ ( .D(n1748), .CK(clk), .RN(
n8580), .Q(FPSENCOS_d_ff2_Z[18]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_18_ ( .D(n1873), .CK(clk), .RN(
n8579), .Q(FPSENCOS_d_ff2_Y[18]), .QN(n7898) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_18_ ( .D(n1872), .CK(clk), .RN(n8579),
.Q(FPSENCOS_d_ff3_sh_y_out[18]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_18_ ( .D(n1970), .CK(clk), .RN(n8579),
.Q(FPSENCOS_d_ff3_sh_x_out[18]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_21_ ( .D(n2013), .CK(clk), .RN(n8579), .Q(
FPSENCOS_d_ff_Zn[21]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_21_ ( .D(n1745), .CK(clk), .RN(
n8579), .Q(FPSENCOS_d_ff2_Z[21]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_21_ ( .D(n1867), .CK(clk), .RN(
n8579), .Q(FPSENCOS_d_ff2_Y[21]), .QN(n7899) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_21_ ( .D(n1866), .CK(clk), .RN(n8579),
.Q(FPSENCOS_d_ff3_sh_y_out[21]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_21_ ( .D(n1964), .CK(clk), .RN(n2426),
.Q(FPSENCOS_d_ff3_sh_x_out[21]), .QN(n7929) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_19_ ( .D(n2019), .CK(clk), .RN(n8561), .Q(
FPSENCOS_d_ff_Zn[19]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_19_ ( .D(n1747), .CK(clk), .RN(
n8561), .Q(FPSENCOS_d_ff2_Z[19]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_19_ ( .D(n1871), .CK(clk), .RN(
n8561), .Q(FPSENCOS_d_ff2_Y[19]), .QN(n7900) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_19_ ( .D(n1870), .CK(clk), .RN(n8561),
.Q(FPSENCOS_d_ff3_sh_y_out[19]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_19_ ( .D(n1968), .CK(clk), .RN(n8561),
.Q(FPSENCOS_d_ff3_sh_x_out[19]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_20_ ( .D(n2016), .CK(clk), .RN(n8561), .Q(
FPSENCOS_d_ff_Zn[20]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_20_ ( .D(n1746), .CK(clk), .RN(
n8561), .Q(FPSENCOS_d_ff2_Z[20]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_20_ ( .D(n1869), .CK(clk), .RN(
n8560), .Q(FPSENCOS_d_ff2_Y[20]), .QN(n7901) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_20_ ( .D(n1868), .CK(clk), .RN(n8560),
.Q(FPSENCOS_d_ff3_sh_y_out[20]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_20_ ( .D(n1966), .CK(clk), .RN(n8560),
.Q(FPSENCOS_d_ff3_sh_x_out[20]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_17_ ( .D(n2025), .CK(clk), .RN(n8560), .Q(
FPSENCOS_d_ff_Zn[17]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_17_ ( .D(n1749), .CK(clk), .RN(
n8560), .Q(FPSENCOS_d_ff2_Z[17]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_17_ ( .D(n1875), .CK(clk), .RN(
n8560), .Q(FPSENCOS_d_ff2_Y[17]), .QN(n7902) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_17_ ( .D(n1874), .CK(clk), .RN(n8559),
.Q(FPSENCOS_d_ff3_sh_y_out[17]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_17_ ( .D(n1972), .CK(clk), .RN(n8559),
.Q(FPSENCOS_d_ff3_sh_x_out[17]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_4_ ( .D(n2064), .CK(clk), .RN(n8559), .Q(
FPSENCOS_d_ff_Zn[4]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_4_ ( .D(n1762), .CK(clk), .RN(
n8559), .Q(FPSENCOS_d_ff2_Z[4]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_4_ ( .D(n1901), .CK(clk), .RN(
n8559), .Q(FPSENCOS_d_ff2_Y[4]), .QN(n7887) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_4_ ( .D(n1900), .CK(clk), .RN(n8559),
.Q(FPSENCOS_d_ff3_sh_y_out[4]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_4_ ( .D(n1998), .CK(clk), .RN(n8558),
.Q(FPSENCOS_d_ff3_sh_x_out[4]), .QN(n7930) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_6_ ( .D(n2058), .CK(clk), .RN(n8558), .Q(
FPSENCOS_d_ff_Zn[6]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_6_ ( .D(n1760), .CK(clk), .RN(
n8558), .Q(FPSENCOS_d_ff2_Z[6]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_6_ ( .D(n1897), .CK(clk), .RN(
n8558), .Q(FPSENCOS_d_ff2_Y[6]), .QN(n7888) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_6_ ( .D(n1896), .CK(clk), .RN(n8558),
.Q(FPSENCOS_d_ff3_sh_y_out[6]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_6_ ( .D(n1994), .CK(clk), .RN(n8558),
.Q(FPSENCOS_d_ff3_sh_x_out[6]), .QN(n7931) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_13_ ( .D(n2037), .CK(clk), .RN(n8557), .Q(
FPSENCOS_d_ff_Zn[13]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_13_ ( .D(n1753), .CK(clk), .RN(
n8557), .Q(FPSENCOS_d_ff2_Z[13]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_13_ ( .D(n1883), .CK(clk), .RN(
n8557), .Q(FPSENCOS_d_ff2_Y[13]), .QN(n7903) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_13_ ( .D(n1882), .CK(clk), .RN(n8557),
.Q(FPSENCOS_d_ff3_sh_y_out[13]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_13_ ( .D(n1980), .CK(clk), .RN(n8557),
.Q(FPSENCOS_d_ff3_sh_x_out[13]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_16_ ( .D(n2028), .CK(clk), .RN(n8557), .Q(
FPSENCOS_d_ff_Zn[16]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_16_ ( .D(n1750), .CK(clk), .RN(
n8557), .Q(FPSENCOS_d_ff2_Z[16]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_16_ ( .D(n1877), .CK(clk), .RN(
n8556), .Q(FPSENCOS_d_ff2_Y[16]), .QN(n7904) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_16_ ( .D(n1876), .CK(clk), .RN(n8556),
.Q(FPSENCOS_d_ff3_sh_y_out[16]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_16_ ( .D(n1974), .CK(clk), .RN(n8556),
.Q(FPSENCOS_d_ff3_sh_x_out[16]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_8_ ( .D(n2052), .CK(clk), .RN(n8556), .Q(
FPSENCOS_d_ff_Zn[8]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_8_ ( .D(n1758), .CK(clk), .RN(
n8556), .Q(FPSENCOS_d_ff2_Z[8]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_8_ ( .D(n1893), .CK(clk), .RN(
n8555), .Q(FPSENCOS_d_ff2_Y[8]), .QN(n7889) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_8_ ( .D(n1892), .CK(clk), .RN(n8555),
.Q(FPSENCOS_d_ff3_sh_y_out[8]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_8_ ( .D(n1990), .CK(clk), .RN(n8555),
.Q(FPSENCOS_d_ff3_sh_x_out[8]), .QN(n7932) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_11_ ( .D(n2043), .CK(clk), .RN(n8555), .Q(
FPSENCOS_d_ff_Zn[11]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_11_ ( .D(n1755), .CK(clk), .RN(
n8555), .Q(FPSENCOS_d_ff2_Z[11]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_11_ ( .D(n1887), .CK(clk), .RN(
n8555), .Q(FPSENCOS_d_ff2_Y[11]), .QN(n7905) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_11_ ( .D(n1886), .CK(clk), .RN(n8555),
.Q(FPSENCOS_d_ff3_sh_y_out[11]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_11_ ( .D(n1984), .CK(clk), .RN(n8554),
.Q(FPSENCOS_d_ff3_sh_x_out[11]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_14_ ( .D(n2034), .CK(clk), .RN(n8554), .Q(
FPSENCOS_d_ff_Zn[14]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_14_ ( .D(n1752), .CK(clk), .RN(
n8554), .Q(FPSENCOS_d_ff2_Z[14]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_14_ ( .D(n1881), .CK(clk), .RN(
n8554), .Q(FPSENCOS_d_ff2_Y[14]), .QN(n7906) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_14_ ( .D(n1880), .CK(clk), .RN(n8554),
.Q(FPSENCOS_d_ff3_sh_y_out[14]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_14_ ( .D(n1978), .CK(clk), .RN(n8553),
.Q(FPSENCOS_d_ff3_sh_x_out[14]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_10_ ( .D(n2046), .CK(clk), .RN(n8553), .Q(
FPSENCOS_d_ff_Zn[10]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_10_ ( .D(n1756), .CK(clk), .RN(
n8553), .Q(FPSENCOS_d_ff2_Z[10]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_10_ ( .D(n1889), .CK(clk), .RN(
n8553), .Q(FPSENCOS_d_ff2_Y[10]), .QN(n7907) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_10_ ( .D(n1888), .CK(clk), .RN(n8553),
.Q(FPSENCOS_d_ff3_sh_y_out[10]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_10_ ( .D(n1986), .CK(clk), .RN(n8553),
.Q(FPSENCOS_d_ff3_sh_x_out[10]), .QN(n7933) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_12_ ( .D(n2040), .CK(clk), .RN(n8553), .Q(
FPSENCOS_d_ff_Zn[12]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_12_ ( .D(n1754), .CK(clk), .RN(
n8552), .Q(FPSENCOS_d_ff2_Z[12]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_12_ ( .D(n1885), .CK(clk), .RN(
n8552), .Q(FPSENCOS_d_ff2_Y[12]), .QN(n7908) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_12_ ( .D(n1884), .CK(clk), .RN(n8552),
.Q(FPSENCOS_d_ff3_sh_y_out[12]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_12_ ( .D(n1982), .CK(clk), .RN(n8552),
.Q(FPSENCOS_d_ff3_sh_x_out[12]), .QN(n7938) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_31_ ( .D(n1911), .CK(clk), .RN(n8552), .Q(
FPSENCOS_d_ff_Zn[31]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_31_ ( .D(n1847), .CK(clk), .RN(
n8551), .Q(FPSENCOS_d_ff2_Y[31]), .QN(n7878) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_31_ ( .D(n1846), .CK(clk), .RN(n8551),
.Q(FPSENCOS_d_ff3_sh_y_out[31]) );
DFFRXLTS FPSENCOS_d_ff4_Xn_Q_reg_31_ ( .D(n1729), .CK(clk), .RN(n8551), .Q(
FPSENCOS_d_ff_Xn[31]), .QN(n7882) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_31_ ( .D(n1944), .CK(clk), .RN(n8551),
.Q(FPSENCOS_d_ff3_sh_x_out[31]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_0_ ( .D(n2081), .CK(clk), .RN(
n7974), .Q(FPADDSUB_bit_shift_SHT2) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_3_ ( .D(n2067), .CK(clk), .RN(n8551), .Q(
FPSENCOS_d_ff_Zn[3]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_3_ ( .D(n1763), .CK(clk), .RN(
n8551), .Q(FPSENCOS_d_ff2_Z[3]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_3_ ( .D(n1903), .CK(clk), .RN(
n8551), .Q(FPSENCOS_d_ff2_Y[3]), .QN(n7890) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_3_ ( .D(n1902), .CK(clk), .RN(n8550),
.Q(FPSENCOS_d_ff3_sh_y_out[3]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_3_ ( .D(n2000), .CK(clk), .RN(n8550),
.Q(FPSENCOS_d_ff3_sh_x_out[3]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_3_ ( .D(n1725), .CK(clk), .RN(n8550),
.Q(cordic_result[3]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_2_ ( .D(n2070), .CK(clk), .RN(n8550), .Q(
FPSENCOS_d_ff_Zn[2]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_2_ ( .D(n1764), .CK(clk), .RN(
n8550), .Q(FPSENCOS_d_ff2_Z[2]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_2_ ( .D(n1905), .CK(clk), .RN(
n8556), .Q(FPSENCOS_d_ff2_Y[2]), .QN(n7891) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_2_ ( .D(n1904), .CK(clk), .RN(n8569),
.Q(FPSENCOS_d_ff3_sh_y_out[2]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_2_ ( .D(n2002), .CK(clk), .RN(n8569),
.Q(FPSENCOS_d_ff3_sh_x_out[2]), .QN(n7934) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_2_ ( .D(n1726), .CK(clk), .RN(n8569),
.Q(cordic_result[2]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_7_ ( .D(n2055), .CK(clk), .RN(n8569), .Q(
FPSENCOS_d_ff_Zn[7]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_7_ ( .D(n1759), .CK(clk), .RN(
n8569), .Q(FPSENCOS_d_ff2_Z[7]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_7_ ( .D(n1895), .CK(clk), .RN(
n8569), .Q(FPSENCOS_d_ff2_Y[7]), .QN(n7892) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_7_ ( .D(n1894), .CK(clk), .RN(n8568),
.Q(FPSENCOS_d_ff3_sh_y_out[7]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_7_ ( .D(n1992), .CK(clk), .RN(n8568),
.Q(FPSENCOS_d_ff3_sh_x_out[7]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_7_ ( .D(n1721), .CK(clk), .RN(n8568),
.Q(cordic_result[7]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_0_ ( .D(n2076), .CK(clk), .RN(n8568), .Q(
FPSENCOS_d_ff_Zn[0]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_0_ ( .D(n1766), .CK(clk), .RN(
n8568), .Q(FPSENCOS_d_ff2_Z[0]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_0_ ( .D(n1909), .CK(clk), .RN(
n8568), .Q(FPSENCOS_d_ff2_Y[0]), .QN(n7886) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_0_ ( .D(n1908), .CK(clk), .RN(n8568),
.Q(FPSENCOS_d_ff3_sh_y_out[0]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_0_ ( .D(n2006), .CK(clk), .RN(n8567),
.Q(FPSENCOS_d_ff3_sh_x_out[0]), .QN(n7935) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_0_ ( .D(n1728), .CK(clk), .RN(n8567),
.Q(cordic_result[0]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_1_ ( .D(n2073), .CK(clk), .RN(n8567), .Q(
FPSENCOS_d_ff_Zn[1]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_1_ ( .D(n1765), .CK(clk), .RN(
n8567), .Q(FPSENCOS_d_ff2_Z[1]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_1_ ( .D(n1907), .CK(clk), .RN(
n8567), .Q(FPSENCOS_d_ff2_Y[1]), .QN(n7893) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_1_ ( .D(n1906), .CK(clk), .RN(n8567),
.Q(FPSENCOS_d_ff3_sh_y_out[1]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_1_ ( .D(n2004), .CK(clk), .RN(n8566),
.Q(FPSENCOS_d_ff3_sh_x_out[1]), .QN(n7936) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_1_ ( .D(n1727), .CK(clk), .RN(n8566),
.Q(cordic_result[1]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_9_ ( .D(n2049), .CK(clk), .RN(n8566), .Q(
FPSENCOS_d_ff_Zn[9]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_9_ ( .D(n1757), .CK(clk), .RN(
n8566), .Q(FPSENCOS_d_ff2_Z[9]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_9_ ( .D(n1891), .CK(clk), .RN(
n8566), .Q(FPSENCOS_d_ff2_Y[9]), .QN(n7894) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_9_ ( .D(n1890), .CK(clk), .RN(n8566),
.Q(FPSENCOS_d_ff3_sh_y_out[9]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_9_ ( .D(n1988), .CK(clk), .RN(n8565),
.Q(FPSENCOS_d_ff3_sh_x_out[9]), .QN(n7937) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_9_ ( .D(n1719), .CK(clk), .RN(n8565),
.Q(cordic_result[9]) );
DFFRXLTS FPSENCOS_d_ff4_Zn_Q_reg_5_ ( .D(n2061), .CK(clk), .RN(n8565), .Q(
FPSENCOS_d_ff_Zn[5]) );
DFFRXLTS FPSENCOS_reg_val_muxZ_2stage_Q_reg_5_ ( .D(n1761), .CK(clk), .RN(
n8565), .Q(FPSENCOS_d_ff2_Z[5]) );
DFFRXLTS FPSENCOS_reg_val_muxY_2stage_Q_reg_5_ ( .D(n1899), .CK(clk), .RN(
n8565), .Q(FPSENCOS_d_ff2_Y[5]), .QN(n7895) );
DFFRXLTS FPSENCOS_reg_shift_y_Q_reg_5_ ( .D(n1898), .CK(clk), .RN(n8565),
.Q(FPSENCOS_d_ff3_sh_y_out[5]) );
DFFRXLTS FPSENCOS_reg_shift_x_Q_reg_5_ ( .D(n1996), .CK(clk), .RN(n8565),
.Q(FPSENCOS_d_ff3_sh_x_out[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_5_ ( .D(n1723), .CK(clk), .RN(n8564),
.Q(cordic_result[5]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_12_ ( .D(n1716), .CK(clk), .RN(n8564),
.Q(cordic_result[12]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_10_ ( .D(n1718), .CK(clk), .RN(n8564),
.Q(cordic_result[10]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_14_ ( .D(n1714), .CK(clk), .RN(n8564),
.Q(cordic_result[14]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_11_ ( .D(n1717), .CK(clk), .RN(n8564),
.Q(cordic_result[11]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_8_ ( .D(n1720), .CK(clk), .RN(n8564),
.Q(cordic_result[8]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_16_ ( .D(n1712), .CK(clk), .RN(n8564),
.Q(cordic_result[16]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_13_ ( .D(n1715), .CK(clk), .RN(n8564),
.Q(cordic_result[13]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_6_ ( .D(n1722), .CK(clk), .RN(n8564),
.Q(cordic_result[6]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_4_ ( .D(n1724), .CK(clk), .RN(n8595),
.Q(cordic_result[4]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_17_ ( .D(n1711), .CK(clk), .RN(n7776),
.Q(cordic_result[17]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_20_ ( .D(n1708), .CK(clk), .RN(n7991),
.Q(cordic_result[20]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_19_ ( .D(n1709), .CK(clk), .RN(n8562),
.Q(cordic_result[19]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_21_ ( .D(n1707), .CK(clk), .RN(n2470),
.Q(cordic_result[21]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_18_ ( .D(n1710), .CK(clk), .RN(n7991),
.Q(cordic_result[18]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_15_ ( .D(n1713), .CK(clk), .RN(n8594),
.Q(cordic_result[15]) );
DFFRXLTS FPSENCOS_d_ff5_data_out_Q_reg_22_ ( .D(n1706), .CK(clk), .RN(n8592),
.Q(cordic_result[22]) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n1696), .CK(clk),
.RN(n8599), .Q(FPMULT_Op_MY[31]) );
DFFRXLTS FPMULT_Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n1626), .CK(
clk), .RN(n2366), .Q(FPMULT_zero_flag) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n1681), .CK(clk),
.RN(n2394), .Q(FPMULT_Op_MX[22]), .QN(n8285) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n1679), .CK(clk),
.RN(n8596), .Q(FPMULT_Op_MX[20]), .QN(n2226) );
DFFRX4TS R_678 ( .D(n1678), .CK(clk), .RN(n2493), .Q(FPMULT_Op_MX[19]) );
DFFRX4TS R_291 ( .D(n1677), .CK(clk), .RN(n8599), .Q(FPMULT_Op_MX[18]), .QN(
n2304) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n1675), .CK(clk),
.RN(n2393), .Q(FPMULT_Op_MX[16]), .QN(n8343) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n1670), .CK(clk),
.RN(n2393), .Q(FPMULT_Op_MX[11]), .QN(n8286) );
DFFRX4TS FPMULT_Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n1663), .CK(clk),
.RN(n2393), .Q(FPMULT_Op_MX[4]), .QN(n8489) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n1658), .CK(clk),
.RN(n2420), .Q(FPMULT_Op_MX[31]) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n1649), .CK(clk),
.RN(n7995), .Q(FPMULT_Op_MY[22]), .QN(n3175) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n1647), .CK(clk),
.RN(n7995), .Q(FPMULT_Op_MY[20]), .QN(n3174) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n1636), .CK(clk),
.RN(n2384), .Q(FPMULT_Op_MY[9]), .QN(n8486) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n1635), .CK(clk),
.RN(n2385), .Q(FPMULT_Op_MY[8]), .QN(n8487) );
DFFRX4TS FPMULT_Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n1633), .CK(clk),
.RN(n2385), .Q(FPMULT_Op_MY[6]), .QN(n8482) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_24_ ( .D(n1577), .CK(clk),
.RN(n2424), .Q(FPMULT_P_Sgf[24]), .QN(n3164) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_23_ ( .D(n1576), .CK(clk),
.RN(n2424), .Q(FPMULT_P_Sgf[23]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_22_ ( .D(n1575), .CK(clk),
.RN(n8562), .Q(FPMULT_P_Sgf[22]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_21_ ( .D(n1574), .CK(clk),
.RN(n8591), .Q(FPMULT_P_Sgf[21]), .QN(n3158) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_1_ ( .D(n1554), .CK(clk),
.RN(n8592), .Q(FPMULT_P_Sgf[1]) );
DFFRXLTS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_0_ ( .D(n1553), .CK(clk),
.RN(n7991), .Q(FPMULT_P_Sgf[0]) );
DFFRXLTS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n1625), .CK(
clk), .RN(n2384), .Q(FPMULT_Sgf_normalized_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(
n1515), .CK(clk), .RN(n2392), .Q(mult_result[0]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(
n1514), .CK(clk), .RN(n2392), .Q(mult_result[1]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(
n1513), .CK(clk), .RN(n2367), .Q(mult_result[2]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(
n1512), .CK(clk), .RN(n2367), .Q(mult_result[3]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(
n1511), .CK(clk), .RN(n2367), .Q(mult_result[4]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(
n1510), .CK(clk), .RN(n2367), .Q(mult_result[5]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(
n1509), .CK(clk), .RN(n2367), .Q(mult_result[6]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(
n1508), .CK(clk), .RN(n2368), .Q(mult_result[7]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(
n1507), .CK(clk), .RN(n2368), .Q(mult_result[8]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(
n1506), .CK(clk), .RN(n2368), .Q(mult_result[9]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(
n1505), .CK(clk), .RN(n2368), .Q(mult_result[10]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(
n1504), .CK(clk), .RN(n2368), .Q(mult_result[11]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(
n1503), .CK(clk), .RN(n8597), .Q(mult_result[12]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(
n1502), .CK(clk), .RN(n8597), .Q(mult_result[13]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(
n1501), .CK(clk), .RN(n8597), .Q(mult_result[14]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(
n1500), .CK(clk), .RN(n8597), .Q(mult_result[15]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(
n1499), .CK(clk), .RN(n8597), .Q(mult_result[16]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(
n1498), .CK(clk), .RN(n8597), .Q(mult_result[17]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(
n1497), .CK(clk), .RN(n8597), .Q(mult_result[18]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(
n1496), .CK(clk), .RN(n8597), .Q(mult_result[19]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(
n1495), .CK(clk), .RN(n8597), .Q(mult_result[20]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(
n1494), .CK(clk), .RN(n8597), .Q(mult_result[21]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(
n1493), .CK(clk), .RN(n2363), .Q(mult_result[22]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(
n1492), .CK(clk), .RN(n2363), .Q(mult_result[23]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(
n1491), .CK(clk), .RN(n2363), .Q(mult_result[24]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(
n1490), .CK(clk), .RN(n2363), .Q(mult_result[25]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(
n1489), .CK(clk), .RN(n2364), .Q(mult_result[26]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(
n1488), .CK(clk), .RN(n2364), .Q(mult_result[27]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(
n1487), .CK(clk), .RN(n2364), .Q(mult_result[28]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(
n1486), .CK(clk), .RN(n2364), .Q(mult_result[29]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(
n1485), .CK(clk), .RN(n2364), .Q(mult_result[30]) );
DFFRXLTS FPMULT_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(
n1483), .CK(clk), .RN(n2364), .Q(mult_result[31]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_3_ ( .D(n1480), .CK(clk), .RN(
n7984), .Q(FPADDSUB_Shift_amount_SHT1_EWR[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_2_ ( .D(n1479), .CK(clk), .RN(
n7984), .Q(FPADDSUB_Shift_amount_SHT1_EWR[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_1_ ( .D(n1478), .CK(clk), .RN(
n7984), .Q(FPADDSUB_Shift_amount_SHT1_EWR[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_0_ ( .D(n1477), .CK(clk), .RN(
n7984), .Q(FPADDSUB_Shift_amount_SHT1_EWR[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_sft_amount_Q_reg_4_ ( .D(n1476), .CK(clk), .RN(
n7984), .Q(FPADDSUB_Shift_amount_SHT1_EWR[4]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_0_ ( .D(n1456), .CK(clk), .RN(
n8544), .Q(FPADDSUB_DMP_exp_NRM_EW[0]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_0_ ( .D(n1455), .CK(clk), .RN(
n8544), .Q(FPADDSUB_DMP_exp_NRM2_EW[0]), .QN(n2448) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_1_ ( .D(n1451), .CK(clk), .RN(
n8545), .Q(FPADDSUB_DMP_exp_NRM_EW[1]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_1_ ( .D(n1450), .CK(clk), .RN(
n8545), .Q(FPADDSUB_DMP_exp_NRM2_EW[1]), .QN(n2450) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_25_ ( .D(n1449), .CK(clk), .RN(n8527),
.Q(FPADDSUB_DMP_SHT1_EWSW[25]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_25_ ( .D(n1448), .CK(clk), .RN(n8527),
.Q(FPADDSUB_DMP_SHT2_EWSW[25]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_25_ ( .D(n1447), .CK(clk), .RN(n8527),
.Q(FPADDSUB_DMP_SFG[25]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_2_ ( .D(n1446), .CK(clk), .RN(
n8545), .Q(FPADDSUB_DMP_exp_NRM_EW[2]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_2_ ( .D(n1445), .CK(clk), .RN(
n8545), .Q(FPADDSUB_DMP_exp_NRM2_EW[2]), .QN(n2452) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_26_ ( .D(n1444), .CK(clk), .RN(n8527),
.Q(FPADDSUB_DMP_SHT1_EWSW[26]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_26_ ( .D(n1443), .CK(clk), .RN(n8527),
.Q(FPADDSUB_DMP_SHT2_EWSW[26]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_26_ ( .D(n1442), .CK(clk), .RN(n8527),
.Q(FPADDSUB_DMP_SFG[26]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_3_ ( .D(n1441), .CK(clk), .RN(
n8545), .Q(FPADDSUB_DMP_exp_NRM_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_3_ ( .D(n1440), .CK(clk), .RN(
n8545), .Q(FPADDSUB_DMP_exp_NRM2_EW[3]), .QN(n2454) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_27_ ( .D(n1439), .CK(clk), .RN(n8527),
.Q(FPADDSUB_DMP_SHT1_EWSW[27]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_27_ ( .D(n1438), .CK(clk), .RN(n8527),
.Q(FPADDSUB_DMP_SHT2_EWSW[27]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_27_ ( .D(n1437), .CK(clk), .RN(n8527),
.Q(FPADDSUB_DMP_SFG[27]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_4_ ( .D(n1436), .CK(clk), .RN(
n8545), .Q(FPADDSUB_DMP_exp_NRM_EW[4]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_4_ ( .D(n1435), .CK(clk), .RN(
n8545), .Q(FPADDSUB_DMP_exp_NRM2_EW[4]), .QN(n2456) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_28_ ( .D(n1434), .CK(clk), .RN(n8527),
.Q(FPADDSUB_DMP_SHT1_EWSW[28]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_28_ ( .D(n1433), .CK(clk), .RN(n7961),
.Q(FPADDSUB_DMP_SHT2_EWSW[28]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_28_ ( .D(n1432), .CK(clk), .RN(n7957),
.Q(FPADDSUB_DMP_SFG[28]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_5_ ( .D(n1431), .CK(clk), .RN(
n8545), .Q(FPADDSUB_DMP_exp_NRM_EW[5]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_5_ ( .D(n1430), .CK(clk), .RN(
n8545), .Q(FPADDSUB_DMP_exp_NRM2_EW[5]), .QN(n2458) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_29_ ( .D(n1429), .CK(clk), .RN(n8529),
.Q(FPADDSUB_DMP_SHT1_EWSW[29]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_29_ ( .D(n1428), .CK(clk), .RN(n8548),
.Q(FPADDSUB_DMP_SHT2_EWSW[29]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_29_ ( .D(n1427), .CK(clk), .RN(n8547),
.Q(FPADDSUB_DMP_SFG[29]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_6_ ( .D(n1426), .CK(clk), .RN(
n8546), .Q(FPADDSUB_DMP_exp_NRM_EW[6]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_6_ ( .D(n1425), .CK(clk), .RN(
n8546), .Q(FPADDSUB_DMP_exp_NRM2_EW[6]), .QN(n2460) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_30_ ( .D(n1424), .CK(clk), .RN(n8528),
.Q(FPADDSUB_DMP_SHT1_EWSW[30]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_30_ ( .D(n1423), .CK(clk), .RN(n8532),
.Q(FPADDSUB_DMP_SHT2_EWSW[30]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_30_ ( .D(n1422), .CK(clk), .RN(n7961),
.Q(FPADDSUB_DMP_SFG[30]) );
DFFRXLTS FPADDSUB_NRM_STAGE_DMP_exp_Q_reg_7_ ( .D(n1421), .CK(clk), .RN(
n8546), .Q(FPADDSUB_DMP_exp_NRM_EW[7]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_7_ ( .D(n1420), .CK(clk), .RN(
n8546), .Q(FPADDSUB_DMP_exp_NRM2_EW[7]), .QN(n2462) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1414), .CK(clk), .RN(n8532), .Q(underflow_flag_addsubt) );
DFFRXLTS FPADDSUB_FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1413), .CK(clk), .RN(n8634), .Q(overflow_flag_addsubt) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_9_ ( .D(n1411), .CK(clk), .RN(
n8530), .Q(FPADDSUB_LZD_output_NRM2_EW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_22_ ( .D(n1408), .CK(clk), .RN(
n8540), .Q(FPADDSUB_DmP_mant_SHT1_SW[22]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_15_ ( .D(n1405), .CK(clk), .RN(
n8540), .Q(FPADDSUB_DmP_mant_SHT1_SW[15]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_18_ ( .D(n1402), .CK(clk), .RN(
n8540), .Q(FPADDSUB_DmP_mant_SHT1_SW[18]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_21_ ( .D(n1399), .CK(clk), .RN(
n8540), .Q(FPADDSUB_DmP_mant_SHT1_SW[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_19_ ( .D(n1396), .CK(clk), .RN(
n8540), .Q(FPADDSUB_DmP_mant_SHT1_SW[19]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_20_ ( .D(n1393), .CK(clk), .RN(
n8540), .Q(FPADDSUB_DmP_mant_SHT1_SW[20]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_17_ ( .D(n1390), .CK(clk), .RN(
n8540), .Q(FPADDSUB_DmP_mant_SHT1_SW[17]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_4_ ( .D(n1387), .CK(clk), .RN(
n8540), .Q(FPADDSUB_DmP_mant_SHT1_SW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_6_ ( .D(n1384), .CK(clk), .RN(
n8540), .Q(FPADDSUB_DmP_mant_SHT1_SW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_13_ ( .D(n1381), .CK(clk), .RN(
n8531), .Q(FPADDSUB_DmP_mant_SHT1_SW[13]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_16_ ( .D(n1378), .CK(clk), .RN(
n8531), .Q(FPADDSUB_DmP_mant_SHT1_SW[16]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_8_ ( .D(n1375), .CK(clk), .RN(
n7961), .Q(FPADDSUB_DmP_mant_SHT1_SW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_11_ ( .D(n1372), .CK(clk), .RN(
n7957), .Q(FPADDSUB_DmP_mant_SHT1_SW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_14_ ( .D(n1369), .CK(clk), .RN(
n8529), .Q(FPADDSUB_DmP_mant_SHT1_SW[14]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_10_ ( .D(n1366), .CK(clk), .RN(
n8528), .Q(FPADDSUB_DmP_mant_SHT1_SW[10]) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_2_ ( .D(n1364), .CK(clk), .RN(n8533),
.Q(FPADDSUB_SIGN_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_2_ ( .D(n1363), .CK(clk), .RN(n8549), .Q(FPADDSUB_SIGN_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_2_ ( .D(n1362), .CK(clk), .RN(n8536), .Q(FPADDSUB_SIGN_FLAG_SHT2) );
DFFRXLTS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_2_ ( .D(n1361), .CK(clk), .RN(n6353),
.Q(FPADDSUB_SIGN_FLAG_SFG) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_1_ ( .D(n1360), .CK(clk), .RN(n6354),
.Q(FPADDSUB_SIGN_FLAG_NRM) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_1_ ( .D(n1359), .CK(clk), .RN(
n7987), .Q(FPADDSUB_SIGN_FLAG_SHT1SHT2) );
DFFRXLTS FPADDSUB_EXP_STAGE_FLAGS_Q_reg_1_ ( .D(n1357), .CK(clk), .RN(n8533),
.Q(FPADDSUB_OP_FLAG_EXP) );
DFFRXLTS FPADDSUB_SHT1_STAGE_FLAGS_Q_reg_1_ ( .D(n1356), .CK(clk), .RN(n8549), .Q(FPADDSUB_OP_FLAG_SHT1) );
DFFRXLTS FPADDSUB_SHT2_STAGE_FLAGS_Q_reg_1_ ( .D(n1355), .CK(clk), .RN(n8536), .Q(FPADDSUB_OP_FLAG_SHT2) );
DFFRXLTS FPADDSUB_NRM_STAGE_FLAGS_Q_reg_2_ ( .D(n1353), .CK(clk), .RN(n7955),
.Q(FPADDSUB_ADD_OVRFLW_NRM), .QN(n7824) );
DFFRXLTS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_0_ ( .D(n1351), .CK(clk), .RN(
n8541), .Q(FPADDSUB_Raw_mant_NRM_SWR[0]) );
DFFRXLTS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_11_ ( .D(n1340), .CK(clk), .RN(
n8541), .Q(FPADDSUB_Raw_mant_NRM_SWR[11]), .QN(n7799) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_13_ ( .D(n1338), .CK(clk), .RN(
n8541), .Q(FPADDSUB_Raw_mant_NRM_SWR[13]), .QN(n7856) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_14_ ( .D(n1337), .CK(clk), .RN(
n8541), .Q(FPADDSUB_Raw_mant_NRM_SWR[14]), .QN(n7807) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_12_ ( .D(n1332), .CK(clk), .RN(
n8544), .Q(FPADDSUB_LZD_output_NRM2_EW[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_3_ ( .D(n1329), .CK(clk), .RN(
n7987), .Q(FPADDSUB_DmP_mant_SHT1_SW[3]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_3_ ( .D(n1327), .CK(clk), .RN(n8538),
.Q(FPADDSUB_DMP_SHT1_EWSW[3]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_3_ ( .D(n7924), .CK(clk), .RN(n8634),
.Q(FPADDSUB_DMP_SHT2_EWSW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_11_ ( .D(n1324), .CK(clk), .RN(
n8538), .Q(FPADDSUB_LZD_output_NRM2_EW[3]) );
DFFRXLTS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_10_ ( .D(n1320), .CK(clk), .RN(
n2401), .Q(FPADDSUB_LZD_output_NRM2_EW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_2_ ( .D(n1313), .CK(clk), .RN(
n7987), .Q(FPADDSUB_DmP_mant_SHT1_SW[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_2_ ( .D(n1311), .CK(clk), .RN(n7969),
.Q(FPADDSUB_DMP_SHT1_EWSW[2]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_2_ ( .D(n7923), .CK(clk), .RN(n2399),
.Q(FPADDSUB_DMP_SHT2_EWSW[2]) );
DFFRX4TS FPADDSUB_SGF_STAGE_DMP_Q_reg_2_ ( .D(n1309), .CK(clk), .RN(n2421),
.Q(FPADDSUB_DMP_SFG[2]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_7_ ( .D(n1306), .CK(clk), .RN(
n2387), .Q(FPADDSUB_DmP_mant_SHT1_SW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_7_ ( .D(n1304), .CK(clk), .RN(n2387),
.Q(FPADDSUB_DMP_SHT1_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_7_ ( .D(n7922), .CK(clk), .RN(n7953),
.Q(FPADDSUB_DMP_SHT2_EWSW[7]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_0_ ( .D(n1299), .CK(clk), .RN(
n7987), .Q(FPADDSUB_DmP_mant_SHT1_SW[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_0_ ( .D(n1297), .CK(clk), .RN(n2387),
.Q(FPADDSUB_DMP_SHT1_EWSW[0]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_0_ ( .D(n7921), .CK(clk), .RN(n2401),
.Q(FPADDSUB_DMP_SHT2_EWSW[0]) );
DFFRX4TS FPADDSUB_SGF_STAGE_DMP_Q_reg_0_ ( .D(n1295), .CK(clk), .RN(n8530),
.Q(FPADDSUB_DMP_SFG[0]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_1_ ( .D(n1292), .CK(clk), .RN(
n7987), .Q(FPADDSUB_DmP_mant_SHT1_SW[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_1_ ( .D(n1290), .CK(clk), .RN(n8533),
.Q(FPADDSUB_DMP_SHT1_EWSW[1]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_1_ ( .D(n7920), .CK(clk), .RN(n2387),
.Q(FPADDSUB_DMP_SHT2_EWSW[1]) );
DFFRX4TS FPADDSUB_SGF_STAGE_DMP_Q_reg_1_ ( .D(n1288), .CK(clk), .RN(n2400),
.Q(FPADDSUB_DMP_SFG[1]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_9_ ( .D(n1285), .CK(clk), .RN(
n8549), .Q(FPADDSUB_DmP_mant_SHT1_SW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_9_ ( .D(n1283), .CK(clk), .RN(n8536),
.Q(FPADDSUB_DMP_SHT1_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_9_ ( .D(n1282), .CK(clk), .RN(n8538),
.Q(FPADDSUB_DMP_SHT2_EWSW[9]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_5_ ( .D(n1278), .CK(clk), .RN(
n8540), .Q(FPADDSUB_DmP_mant_SHT1_SW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_5_ ( .D(n1276), .CK(clk), .RN(n6354),
.Q(FPADDSUB_DMP_SHT1_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_5_ ( .D(n7919), .CK(clk), .RN(n7980),
.Q(FPADDSUB_DMP_SHT2_EWSW[5]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DmP_mant_Q_reg_12_ ( .D(n1272), .CK(clk), .RN(
n2389), .Q(FPADDSUB_DmP_mant_SHT1_SW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_12_ ( .D(n1270), .CK(clk), .RN(n2389),
.Q(FPADDSUB_DMP_SHT1_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_12_ ( .D(n1269), .CK(clk), .RN(n8542),
.Q(FPADDSUB_DMP_SHT2_EWSW[12]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_10_ ( .D(n1266), .CK(clk), .RN(n2389),
.Q(FPADDSUB_DMP_SHT1_EWSW[10]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_10_ ( .D(n1265), .CK(clk), .RN(n8542),
.Q(FPADDSUB_DMP_SHT2_EWSW[10]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DMP_Q_reg_10_ ( .D(n1264), .CK(clk), .RN(n8542),
.Q(FPADDSUB_DMP_SFG[10]), .QN(n2465) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_14_ ( .D(n1262), .CK(clk), .RN(n2389),
.Q(FPADDSUB_DMP_SHT1_EWSW[14]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_14_ ( .D(n1261), .CK(clk), .RN(n8542),
.Q(FPADDSUB_DMP_SHT2_EWSW[14]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_14_ ( .D(n1260), .CK(clk), .RN(n8542),
.Q(FPADDSUB_DMP_SFG[14]), .QN(n2480) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_11_ ( .D(n1258), .CK(clk), .RN(n2389),
.Q(FPADDSUB_DMP_SHT1_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_11_ ( .D(n1257), .CK(clk), .RN(n8542),
.Q(FPADDSUB_DMP_SHT2_EWSW[11]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_8_ ( .D(n1254), .CK(clk), .RN(n2422),
.Q(FPADDSUB_DMP_SHT1_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_8_ ( .D(n1253), .CK(clk), .RN(n7955),
.Q(FPADDSUB_DMP_SHT2_EWSW[8]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_16_ ( .D(n1250), .CK(clk), .RN(n2422),
.Q(FPADDSUB_DMP_SHT1_EWSW[16]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_16_ ( .D(n1249), .CK(clk), .RN(n8543),
.Q(FPADDSUB_DMP_SHT2_EWSW[16]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_16_ ( .D(n1248), .CK(clk), .RN(n8543),
.Q(FPADDSUB_DMP_SFG[16]), .QN(n2474) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_13_ ( .D(n1246), .CK(clk), .RN(n2422),
.Q(FPADDSUB_DMP_SHT1_EWSW[13]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_13_ ( .D(n1245), .CK(clk), .RN(n8542),
.Q(FPADDSUB_DMP_SHT2_EWSW[13]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_13_ ( .D(n1244), .CK(clk), .RN(n8542),
.QN(n2289) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_6_ ( .D(n1242), .CK(clk), .RN(n2422),
.Q(FPADDSUB_DMP_SHT1_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_6_ ( .D(n7918), .CK(clk), .RN(n2400),
.Q(FPADDSUB_DMP_SHT2_EWSW[6]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_4_ ( .D(n1238), .CK(clk), .RN(n2422),
.Q(FPADDSUB_DMP_SHT1_EWSW[4]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_4_ ( .D(n7917), .CK(clk), .RN(n8538),
.Q(FPADDSUB_DMP_SHT2_EWSW[4]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_4_ ( .D(n1236), .CK(clk), .RN(n2347),
.Q(FPADDSUB_DMP_SFG[4]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_17_ ( .D(n1234), .CK(clk), .RN(n2399),
.Q(FPADDSUB_DMP_SHT1_EWSW[17]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_17_ ( .D(n1233), .CK(clk), .RN(n8543),
.Q(FPADDSUB_DMP_SHT2_EWSW[17]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_17_ ( .D(n1232), .CK(clk), .RN(n8543),
.Q(FPADDSUB_DMP_SFG[17]), .QN(n2482) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_20_ ( .D(n1230), .CK(clk), .RN(n2399),
.Q(FPADDSUB_DMP_SHT1_EWSW[20]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_20_ ( .D(n1229), .CK(clk), .RN(n8544),
.Q(FPADDSUB_DMP_SHT2_EWSW[20]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_20_ ( .D(n1228), .CK(clk), .RN(n8544),
.Q(FPADDSUB_DMP_SFG[20]), .QN(n2476) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_19_ ( .D(n1226), .CK(clk), .RN(n2399),
.Q(FPADDSUB_DMP_SHT1_EWSW[19]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_19_ ( .D(n1225), .CK(clk), .RN(n8543),
.Q(FPADDSUB_DMP_SHT2_EWSW[19]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_19_ ( .D(n1224), .CK(clk), .RN(n8543),
.Q(FPADDSUB_DMP_SFG[19]), .QN(n2484) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_21_ ( .D(n1222), .CK(clk), .RN(n2399),
.Q(FPADDSUB_DMP_SHT1_EWSW[21]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_21_ ( .D(n1221), .CK(clk), .RN(n8544),
.Q(FPADDSUB_DMP_SHT2_EWSW[21]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_21_ ( .D(n1220), .CK(clk), .RN(n8544),
.Q(FPADDSUB_DMP_SFG[21]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_18_ ( .D(n1218), .CK(clk), .RN(n2399),
.Q(FPADDSUB_DMP_SHT1_EWSW[18]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_18_ ( .D(n1217), .CK(clk), .RN(n8543),
.Q(FPADDSUB_DMP_SHT2_EWSW[18]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_18_ ( .D(n1216), .CK(clk), .RN(n8543),
.Q(FPADDSUB_DMP_SFG[18]), .QN(n2478) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_15_ ( .D(n1214), .CK(clk), .RN(n7987),
.Q(FPADDSUB_DMP_SHT1_EWSW[15]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_15_ ( .D(n1213), .CK(clk), .RN(n8543),
.Q(FPADDSUB_DMP_SHT2_EWSW[15]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_15_ ( .D(n1212), .CK(clk), .RN(n8543),
.QN(n2290) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_22_ ( .D(n1210), .CK(clk), .RN(n7987),
.Q(FPADDSUB_DMP_SHT1_EWSW[22]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_22_ ( .D(n1209), .CK(clk), .RN(n8544),
.Q(FPADDSUB_DMP_SHT2_EWSW[22]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_22_ ( .D(n1208), .CK(clk), .RN(n8544),
.Q(FPADDSUB_DMP_SFG[22]), .QN(n2472) );
DFFRX4TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_0_ ( .D(n1207), .CK(clk), .RN(
n2370), .QN(n7805) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_12_ ( .D(n1195), .CK(clk), .RN(
n8634), .Q(FPADDSUB_DmP_mant_SFG_SWR[12]), .QN(n7914) );
DFFRXLTS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_25_ ( .D(n1182), .CK(clk), .RN(
n2389), .Q(FPADDSUB_DmP_mant_SFG_SWR[25]), .QN(n7875) );
CMPR32X2TS DP_OP_26J2_126_1325_U4 ( .A(n7806), .B(n2459), .C(
DP_OP_26J2_126_1325_n4), .CO(DP_OP_26J2_126_1325_n3), .S(
FPADDSUB_exp_rslt_NRM2_EW1[5]) );
CMPR32X2TS DP_OP_26J2_126_1325_U3 ( .A(n7806), .B(n2461), .C(
DP_OP_26J2_126_1325_n3), .CO(DP_OP_26J2_126_1325_n2), .S(
FPADDSUB_exp_rslt_NRM2_EW1[6]) );
CMPR32X2TS DP_OP_26J2_126_1325_U2 ( .A(n7806), .B(n2463), .C(
DP_OP_26J2_126_1325_n2), .CO(DP_OP_26J2_126_1325_n1), .S(
FPADDSUB_exp_rslt_NRM2_EW1[7]) );
CMPR32X2TS intadd_9_U4 ( .A(FPSENCOS_d_ff2_Y[24]), .B(n7809), .C(intadd_9_CI), .CO(intadd_9_n3), .S(intadd_9_SUM_0_) );
CMPR32X2TS intadd_9_U3 ( .A(FPSENCOS_d_ff2_Y[25]), .B(intadd_9_B_1_), .C(
intadd_9_n3), .CO(intadd_9_n2), .S(intadd_9_SUM_1_) );
CMPR32X2TS intadd_9_U2 ( .A(FPSENCOS_d_ff2_Y[26]), .B(n7790), .C(intadd_9_n2), .CO(intadd_9_n1), .S(intadd_9_SUM_2_) );
DFFSX2TS R_62 ( .D(n8753), .CK(clk), .SN(n7988), .Q(n8504) );
DFFSX2TS R_108 ( .D(n8744), .CK(clk), .SN(n7963), .Q(n8499) );
DFFSX2TS R_169 ( .D(n8711), .CK(clk), .SN(n7978), .Q(n8497) );
DFFSX2TS R_170 ( .D(n8713), .CK(clk), .SN(n7979), .Q(n8496) );
DFFRX4TS R_561 ( .D(n1672), .CK(clk), .RN(n2393), .Q(
DP_OP_497J2_123_1725_n792) );
DFFRX4TS R_300 ( .D(n1659), .CK(clk), .RN(n2420), .Q(
DP_OP_496J2_122_3540_n1506), .QN(n3165) );
DFFRX4TS R_441 ( .D(n1629), .CK(clk), .RN(n2384), .Q(
DP_OP_498J2_124_1725_n790) );
DFFRX4TS R_423 ( .D(n1646), .CK(clk), .RN(n8598), .Q(
DP_OP_496J2_122_3540_n778), .QN(n3167) );
DFFRX4TS R_1704 ( .D(n1643), .CK(clk), .RN(n8604), .Q(
DP_OP_497J2_123_1725_n782), .QN(n2326) );
DFFRX4TS R_656 ( .D(n1642), .CK(clk), .RN(n7993), .Q(
DP_OP_497J2_123_1725_n781) );
DFFRX4TS R_435 ( .D(n1628), .CK(clk), .RN(n2384), .Q(
DP_OP_498J2_124_1725_n789) );
DFFRX4TS R_444 ( .D(n1641), .CK(clk), .RN(n8598), .Q(
DP_OP_497J2_123_1725_n780) );
DFFRX4TS R_614 ( .D(n1666), .CK(clk), .RN(n2494), .Q(
DP_OP_496J2_122_3540_n1513) );
DFFRX4TS R_626 ( .D(n1627), .CK(clk), .RN(n2384), .Q(
DP_OP_498J2_124_1725_n788) );
DFFRX2TS R_633 ( .D(n1322), .CK(clk), .RN(n8541), .Q(
FPADDSUB_Raw_mant_NRM_SWR[20]) );
DFFRX4TS R_1703 ( .D(n1644), .CK(clk), .RN(n8604), .Q(
DP_OP_496J2_122_3540_n1461), .QN(n3144) );
DFFRX4TS R_665 ( .D(n1634), .CK(clk), .RN(n2384), .Q(n8518), .QN(n3145) );
DFFSX2TS R_666 ( .D(n8697), .CK(clk), .SN(n7966), .Q(n8412) );
DFFSX2TS R_669 ( .D(n8709), .CK(clk), .SN(n7958), .Q(n8411) );
DFFRXLTS R_675 ( .D(add_x_246_A_3_), .CK(clk), .RN(n2392), .Q(
FPMULT_Sgf_normalized_result[3]) );
DFFSX2TS R_685 ( .D(n8708), .CK(clk), .SN(n7958), .Q(n8409) );
DFFRX4TS R_689 ( .D(n1671), .CK(clk), .RN(n7994), .Q(
DP_OP_496J2_122_3540_n1493), .QN(n3180) );
DFFSX2TS R_692 ( .D(n8695), .CK(clk), .SN(n7958), .Q(n8408) );
DFFSX2TS R_695 ( .D(n8707), .CK(clk), .SN(n7953), .Q(n8407) );
DFFRX4TS R_700 ( .D(n1662), .CK(clk), .RN(n7994), .Q(
DP_OP_498J2_124_1725_n803) );
DFFRX4TS R_703 ( .D(n1674), .CK(clk), .RN(n2393), .Q(
DP_OP_497J2_123_1725_n794), .QN(n8344) );
DFFSX2TS R_706 ( .D(n8679), .CK(clk), .SN(n7955), .Q(n8406) );
DFFSX2TS R_707 ( .D(n8675), .CK(clk), .SN(n7955), .Q(n8405) );
DFFSX2TS R_710 ( .D(n7878), .CK(clk), .SN(n7976), .Q(n8404) );
DFFSX2TS R_711 ( .D(n8678), .CK(clk), .SN(n7976), .Q(n8403) );
DFFSX2TS R_714 ( .D(n7796), .CK(clk), .SN(n2419), .Q(n8402) );
DFFSX2TS R_718 ( .D(n7938), .CK(clk), .SN(n7973), .Q(n8400) );
DFFSX2TS R_719 ( .D(n8692), .CK(clk), .SN(n7975), .Q(n8399) );
DFFSX2TS R_722 ( .D(n7937), .CK(clk), .SN(n7983), .Q(n8398) );
DFFSX2TS R_723 ( .D(n8689), .CK(clk), .SN(n7983), .Q(n8397) );
DFFSX2TS R_727 ( .D(n8681), .CK(clk), .SN(n7983), .Q(n8395) );
DFFSX2TS R_731 ( .D(n8680), .CK(clk), .SN(n7979), .Q(n8393) );
DFFSX2TS R_730 ( .D(n7935), .CK(clk), .SN(n7978), .Q(n8394) );
DFFSX2TS R_735 ( .D(n8682), .CK(clk), .SN(n7979), .Q(n8391) );
DFFSX2TS R_734 ( .D(n7934), .CK(clk), .SN(n7978), .Q(n8392) );
DFFSX2TS R_739 ( .D(n8659), .CK(clk), .SN(n7976), .Q(n8389) );
DFFSX2TS R_738 ( .D(n7908), .CK(clk), .SN(n7976), .Q(n8390) );
DFFSX2TS R_742 ( .D(n7907), .CK(clk), .SN(n7973), .Q(n8388) );
DFFSX2TS R_746 ( .D(n7933), .CK(clk), .SN(n8537), .Q(n8386) );
DFFSX2TS R_747 ( .D(n8690), .CK(clk), .SN(n7958), .Q(n8385) );
DFFSX2TS R_750 ( .D(n7906), .CK(clk), .SN(n7973), .Q(n8384) );
DFFSX2TS R_751 ( .D(n8661), .CK(clk), .SN(n8539), .Q(n8383) );
DFFSX2TS R_754 ( .D(n7905), .CK(clk), .SN(n7973), .Q(n8382) );
DFFSX2TS R_755 ( .D(n8658), .CK(clk), .SN(n7973), .Q(n8381) );
DFFSX2TS R_758 ( .D(n7932), .CK(clk), .SN(n7969), .Q(n8380) );
DFFSX2TS R_759 ( .D(n8688), .CK(clk), .SN(n7969), .Q(n8379) );
DFFSX2TS R_762 ( .D(n7904), .CK(clk), .SN(n7969), .Q(n8378) );
DFFSX2TS R_763 ( .D(n8663), .CK(clk), .SN(n7969), .Q(n8377) );
DFFSX2TS R_766 ( .D(n7903), .CK(clk), .SN(n7970), .Q(n8376) );
DFFSX2TS R_767 ( .D(n8660), .CK(clk), .SN(n7970), .Q(n8375) );
DFFSX2TS R_770 ( .D(n7931), .CK(clk), .SN(n7965), .Q(n8374) );
DFFSX2TS R_771 ( .D(n8686), .CK(clk), .SN(n7966), .Q(n8373) );
DFFSX2TS R_775 ( .D(n8684), .CK(clk), .SN(n7966), .Q(n8371) );
DFFSX2TS R_774 ( .D(n7930), .CK(clk), .SN(n7965), .Q(n8372) );
DFFSX2TS R_778 ( .D(n7902), .CK(clk), .SN(n7965), .Q(n8370) );
DFFSX2TS R_779 ( .D(n8664), .CK(clk), .SN(n7965), .Q(n8369) );
DFFSX2TS R_782 ( .D(n7901), .CK(clk), .SN(n7965), .Q(n8368) );
DFFSX2TS R_783 ( .D(n8667), .CK(clk), .SN(n7965), .Q(n8367) );
DFFSX2TS R_798 ( .D(n7897), .CK(clk), .SN(n7958), .Q(n8360) );
DFFSX2TS R_799 ( .D(n8662), .CK(clk), .SN(n7958), .Q(n8359) );
DFFSX2TS R_802 ( .D(n7896), .CK(clk), .SN(n7958), .Q(n8358) );
DFFSX2TS R_803 ( .D(n8669), .CK(clk), .SN(n7958), .Q(n8357) );
DFFSX2TS R_806 ( .D(n7881), .CK(clk), .SN(n7955), .Q(n8356) );
DFFSX2TS R_822 ( .D(n7884), .CK(clk), .SN(n2469), .Q(n8348) );
DFFSX2TS R_823 ( .D(n8672), .CK(clk), .SN(n2469), .Q(n8347) );
DFFSX2TS R_826 ( .D(n7883), .CK(clk), .SN(n8538), .Q(n8346) );
DFFSX2TS R_827 ( .D(n8671), .CK(clk), .SN(n8530), .Q(n8345) );
DFFRX4TS R_837 ( .D(n1673), .CK(clk), .RN(n2393), .Q(
DP_OP_497J2_123_1725_n793), .QN(n2320) );
DFFRX4TS R_858 ( .D(n1676), .CK(clk), .RN(n2393), .Q(
DP_OP_496J2_122_3540_n1498) );
DFFRX4TS R_848 ( .D(n1648), .CK(clk), .RN(n7995), .Q(n8462) );
DFFRX4TS R_852 ( .D(n1645), .CK(clk), .RN(n7993), .Q(
DP_OP_496J2_122_3540_n1462) );
DFFSX2TS R_866 ( .D(n8652), .CK(clk), .SN(n2387), .Q(n8335) );
DFFSX2TS R_865 ( .D(n7895), .CK(clk), .SN(n7983), .Q(n8336) );
DFFSX2TS R_869 ( .D(n7894), .CK(clk), .SN(n7970), .Q(n8334) );
DFFSX2TS R_870 ( .D(n8656), .CK(clk), .SN(n2421), .Q(n8333) );
DFFSX2TS R_873 ( .D(n7893), .CK(clk), .SN(n7963), .Q(n8332) );
DFFSX2TS R_874 ( .D(n8648), .CK(clk), .SN(n7970), .Q(n8331) );
DFFSX2TS R_877 ( .D(n7892), .CK(clk), .SN(n7979), .Q(n8330) );
DFFSX2TS R_878 ( .D(n8654), .CK(clk), .SN(n7979), .Q(n8329) );
DFFSX2TS R_881 ( .D(n7891), .CK(clk), .SN(n7979), .Q(n8328) );
DFFSX2TS R_882 ( .D(n8649), .CK(clk), .SN(n7979), .Q(n8327) );
DFFSX2TS R_885 ( .D(n7890), .CK(clk), .SN(n7975), .Q(n8326) );
DFFSX2TS R_886 ( .D(n8650), .CK(clk), .SN(n7976), .Q(n8325) );
DFFSX2TS R_889 ( .D(n7889), .CK(clk), .SN(n7970), .Q(n8324) );
DFFSX2TS R_890 ( .D(n8655), .CK(clk), .SN(n7970), .Q(n8323) );
DFFSX2TS R_893 ( .D(n7888), .CK(clk), .SN(n7965), .Q(n8322) );
DFFSX2TS R_894 ( .D(n8653), .CK(clk), .SN(n7965), .Q(n8321) );
DFFSX2TS R_898 ( .D(n8651), .CK(clk), .SN(n7965), .Q(n8319) );
DFFSX2TS R_897 ( .D(n7887), .CK(clk), .SN(n7965), .Q(n8320) );
DFFSX2TS R_901 ( .D(n7886), .CK(clk), .SN(n7979), .Q(n8318) );
DFFSX2TS R_902 ( .D(n8647), .CK(clk), .SN(n7979), .Q(n8317) );
DFFSX2TS R_905 ( .D(n7929), .CK(clk), .SN(n7963), .Q(n8316) );
DFFSX2TS R_913 ( .D(n7927), .CK(clk), .SN(n7953), .Q(n8312) );
DFFSX2TS R_917 ( .D(n7926), .CK(clk), .SN(n7953), .Q(n8310) );
DFFSX2TS R_918 ( .D(n8704), .CK(clk), .SN(n7953), .Q(n8309) );
DFFSX2TS R_921 ( .D(n7925), .CK(clk), .SN(n7953), .Q(n8308) );
DFFSX2TS R_922 ( .D(n8703), .CK(clk), .SN(n7953), .Q(n8307) );
DFFSX2TS R_924 ( .D(n8685), .CK(clk), .SN(n8534), .Q(n8306) );
DFFSX2TS R_927 ( .D(n8694), .CK(clk), .SN(n7973), .Q(n8305) );
DFFSX2TS R_930 ( .D(n8687), .CK(clk), .SN(n7980), .Q(n8304) );
DFFSX2TS R_933 ( .D(n8691), .CK(clk), .SN(n7973), .Q(n8303) );
DFFSX2TS R_936 ( .D(n8693), .CK(clk), .SN(n7970), .Q(n8302) );
DFFSX2TS R_939 ( .D(n8683), .CK(clk), .SN(n7975), .Q(n8301) );
DFFSX2TS R_942 ( .D(n8696), .CK(clk), .SN(n7970), .Q(n8300) );
DFFSX2TS R_950 ( .D(n8698), .CK(clk), .SN(n7963), .Q(n8298) );
DFFSX2TS R_953 ( .D(n8699), .CK(clk), .SN(n7963), .Q(n8297) );
DFFSX2TS R_956 ( .D(n8702), .CK(clk), .SN(n7959), .Q(n8296) );
DFFSX2TS R_976 ( .D(n8754), .CK(clk), .SN(n7975), .Q(n8295) );
DFFSX2TS R_978 ( .D(n8710), .CK(clk), .SN(n7959), .Q(n8294) );
DFFSX2TS R_990 ( .D(n8414), .CK(clk), .SN(n2419), .Q(n8631) );
DFFSX2TS R_1014 ( .D(n8299), .CK(clk), .SN(n2419), .Q(n8630) );
DFFSX2TS R_1016 ( .D(n8293), .CK(clk), .SN(n2419), .Q(n8633) );
DFFRXLTS R_1020 ( .D(n1521), .CK(clk), .RN(n2392), .Q(
FPMULT_Sgf_normalized_result[4]) );
DFFRX1TS R_1031 ( .D(n8292), .CK(clk), .RN(n2418), .Q(n8646) );
DFFSX2TS R_1038 ( .D(n8644), .CK(clk), .SN(n8546), .Q(n8290) );
DFFSX2TS R_1039 ( .D(n8526), .CK(clk), .SN(n8546), .Q(n8289) );
DFFSX2TS R_1040 ( .D(n7548), .CK(clk), .SN(n8546), .Q(n8288) );
DFFSX2TS R_1041 ( .D(n8643), .CK(clk), .SN(n8546), .Q(n8287) );
DFFRX4TS R_1052 ( .D(n1680), .CK(clk), .RN(n8596), .Q(
DP_OP_496J2_122_3540_n1502), .QN(n3166) );
DFFRX4TS R_1053 ( .D(n1668), .CK(clk), .RN(n2493), .Q(
DP_OP_498J2_124_1725_n797) );
DFFRXLTS R_1063 ( .D(FPSENCOS_d_ff3_LUT_out[15]), .CK(clk), .RN(n7956), .Q(
n8284) );
DFFSX2TS R_1074 ( .D(n8282), .CK(clk), .SN(n2469), .Q(n8642) );
DFFRXLTS R_1080 ( .D(FPSENCOS_d_ff3_sh_y_out[14]), .CK(clk), .RN(n7972), .Q(
n8279) );
DFFRXLTS R_1082 ( .D(FPSENCOS_d_ff3_sh_x_out[14]), .CK(clk), .RN(n7972), .Q(
n8278) );
DFFRXLTS R_1096 ( .D(FPSENCOS_d_ff3_sh_y_out[11]), .CK(clk), .RN(n7972), .Q(
n8271) );
DFFRXLTS R_1098 ( .D(FPSENCOS_d_ff3_sh_x_out[11]), .CK(clk), .RN(n7972), .Q(
n8270) );
DFFRXLTS R_1108 ( .D(FPSENCOS_d_ff3_sh_y_out[13]), .CK(clk), .RN(n7968), .Q(
n8265) );
DFFRXLTS R_1110 ( .D(FPSENCOS_d_ff3_sh_x_out[13]), .CK(clk), .RN(n7968), .Q(
n8264) );
DFFRXLTS R_1114 ( .D(FPSENCOS_d_ff3_sh_x_out[3]), .CK(clk), .RN(n7974), .Q(
n8262) );
DFFRXLTS R_1112 ( .D(FPSENCOS_d_ff3_sh_y_out[3]), .CK(clk), .RN(n7974), .Q(
n8263) );
DFFRXLTS R_1167 ( .D(FPSENCOS_d_ff3_sh_y_out[15]), .CK(clk), .RN(n8529), .Q(
n8237) );
DFFRXLTS R_1169 ( .D(FPSENCOS_d_ff3_sh_x_out[15]), .CK(clk), .RN(n8548), .Q(
n8236) );
DFFRXLTS R_1173 ( .D(FPSENCOS_d_ff3_LUT_out[1]), .CK(clk), .RN(n7981), .Q(
n8234) );
DFFRXLTS R_1171 ( .D(FPSENCOS_d_ff3_sh_y_out[1]), .CK(clk), .RN(n7981), .Q(
n8235) );
DFFRXLTS R_1183 ( .D(FPSENCOS_d_ff3_sh_y_out[12]), .CK(clk), .RN(n7972), .Q(
n8229) );
DFFRXLTS R_1185 ( .D(FPSENCOS_d_ff3_LUT_out[12]), .CK(clk), .RN(n7972), .Q(
n8228) );
DFFRXLTS R_1189 ( .D(FPSENCOS_d_ff3_LUT_out[0]), .CK(clk), .RN(n7977), .Q(
n8226) );
DFFRXLTS R_1187 ( .D(FPSENCOS_d_ff3_sh_y_out[0]), .CK(clk), .RN(n7977), .Q(
n8227) );
DFFRXLTS R_1197 ( .D(FPSENCOS_d_ff3_LUT_out[9]), .CK(clk), .RN(n7982), .Q(
n8222) );
DFFRXLTS R_1203 ( .D(FPSENCOS_d_ff3_sh_y_out[2]), .CK(clk), .RN(n7978), .Q(
n8219) );
DFFRXLTS R_1205 ( .D(FPSENCOS_d_ff3_LUT_out[2]), .CK(clk), .RN(n7978), .Q(
n8218) );
DFFRX4TS R_1207 ( .D(n1664), .CK(clk), .RN(n2365), .Q(n8519), .QN(n3173) );
DFFRXLTS R_1275 ( .D(FPSENCOS_d_ff2_Z[1]), .CK(clk), .RN(n7981), .Q(n8188)
);
DFFSX2TS R_1355 ( .D(n1419), .CK(clk), .SN(n8528), .Q(n8152) );
DFFSX2TS R_1353 ( .D(n8610), .CK(clk), .SN(n7961), .Q(n8153) );
DFFRXLTS R_1373 ( .D(FPSENCOS_d_ff3_LUT_out[5]), .CK(clk), .RN(n7971), .Q(
n8150) );
DFFRXLTS R_1375 ( .D(FPSENCOS_d_ff3_LUT_out[3]), .CK(clk), .RN(n7967), .Q(
n8149) );
DFFRXLTS R_1385 ( .D(FPSENCOS_d_ff3_LUT_out[7]), .CK(clk), .RN(n7971), .Q(
n8148) );
DFFRXLTS R_1387 ( .D(FPSENCOS_d_ff3_LUT_out[13]), .CK(clk), .RN(n7960), .Q(
n8147) );
DFFSX2TS R_338_RW_0 ( .D(n8725), .CK(clk), .SN(n7988), .Q(n8475) );
DFFSX2TS R_346_RW_0 ( .D(n8723), .CK(clk), .SN(n7988), .Q(n8472) );
DFFSX2TS R_354_RW_0 ( .D(n8720), .CK(clk), .SN(n7988), .Q(n8470) );
DFFSX2TS R_366_RW_0 ( .D(n8729), .CK(clk), .SN(n7988), .Q(n8466) );
DFFSX2TS R_383_RW_0 ( .D(n8726), .CK(clk), .SN(n7988), .Q(n8457) );
DFFSX2TS R_409_RW_0 ( .D(n8717), .CK(clk), .SN(n7988), .Q(n8449) );
DFFSX2TS R_481_RW_0 ( .D(n8732), .CK(clk), .SN(n7988), .Q(n8440) );
DFFSX2TS R_485_RW_0 ( .D(n8735), .CK(clk), .SN(n7988), .Q(n8438) );
DFFSX1TS R_1413 ( .D(FPMULT_Sgf_operation_Result[27]), .CK(clk), .SN(n2426),
.Q(n8145) );
DFFSX2TS R_1420 ( .D(n1467), .CK(clk), .SN(n7985), .Q(n8142) );
DFFSX2TS R_1418 ( .D(n8608), .CK(clk), .SN(n7985), .Q(n8143) );
DFFSX2TS R_1439 ( .D(n8775), .CK(clk), .SN(n8531), .Q(n8140) );
DFFSX2TS R_1442 ( .D(n8774), .CK(clk), .SN(n2370), .Q(n8139) );
DFFSX2TS R_1445 ( .D(n8791), .CK(clk), .SN(n8549), .Q(n8138) );
DFFSX2TS R_1448 ( .D(n8781), .CK(clk), .SN(n7955), .Q(n8137) );
DFFSX2TS R_1454 ( .D(n8803), .CK(clk), .SN(n8534), .Q(n8135) );
DFFSX2TS R_1457 ( .D(n8770), .CK(clk), .SN(n2370), .Q(n8134) );
DFFSX2TS R_1462 ( .D(n8778), .CK(clk), .SN(n8531), .Q(n8133) );
DFFSX2TS R_1465 ( .D(n8797), .CK(clk), .SN(n2388), .Q(n8132) );
DFFSX2TS R_1471 ( .D(n8777), .CK(clk), .SN(n8531), .Q(n8130) );
DFFSX2TS R_1474 ( .D(n8771), .CK(clk), .SN(n2370), .Q(n8129) );
DFFSX2TS R_1475 ( .D(n8796), .CK(clk), .SN(n2388), .Q(n8128) );
DFFSX2TS R_1477 ( .D(n8795), .CK(clk), .SN(n2388), .Q(n8127) );
DFFSX2TS R_1480 ( .D(n8776), .CK(clk), .SN(n8531), .Q(n8126) );
DFFSX2TS R_1483 ( .D(n8780), .CK(clk), .SN(n7961), .Q(n8125) );
DFFRXLTS R_1484 ( .D(add_x_246_A_5_), .CK(clk), .RN(n2392), .Q(
FPMULT_Sgf_normalized_result[5]) );
DFFSX2TS R_1489 ( .D(n8767), .CK(clk), .SN(n8530), .Q(n8124) );
DFFSX2TS R_1492 ( .D(n8766), .CK(clk), .SN(n7961), .Q(n8123) );
DFFSX2TS R_1493 ( .D(n5947), .CK(clk), .SN(n8533), .Q(n8122) );
DFFSX2TS R_1495 ( .D(n8794), .CK(clk), .SN(n8536), .Q(n8121) );
DFFSX2TS R_1499 ( .D(n8779), .CK(clk), .SN(n8536), .Q(n8120) );
DFFSX2TS R_1504 ( .D(n8769), .CK(clk), .SN(n7957), .Q(n8119) );
DFFSX2TS R_1505 ( .D(n8752), .CK(clk), .SN(n7990), .Q(n8118) );
DFFSX2TS R_1520 ( .D(n8827), .CK(clk), .SN(n2400), .Q(n8116) );
DFFSX2TS R_1523 ( .D(n8818), .CK(clk), .SN(n2423), .Q(n8115) );
DFFSX2TS R_1526 ( .D(n8822), .CK(clk), .SN(n2423), .Q(n8114) );
DFFSX2TS R_1529 ( .D(n8821), .CK(clk), .SN(n2423), .Q(n8113) );
DFFSX2TS R_1532 ( .D(n8765), .CK(clk), .SN(n8528), .Q(n8112) );
DFFSX2TS R_1544 ( .D(n8819), .CK(clk), .SN(n2423), .Q(n8109) );
DFFSX2TS R_1547 ( .D(n8800), .CK(clk), .SN(n2388), .Q(n8108) );
DFFSX2TS R_1550 ( .D(n8788), .CK(clk), .SN(n6354), .Q(n8107) );
DFFSX2TS R_1553 ( .D(n8762), .CK(clk), .SN(n7957), .Q(n8106) );
DFFSX2TS R_1559 ( .D(n8758), .CK(clk), .SN(n8539), .Q(n8105) );
DFFSX2TS R_1565 ( .D(n8792), .CK(clk), .SN(n8533), .Q(n8103) );
DFFSX2TS R_1568 ( .D(n8829), .CK(clk), .SN(n2401), .Q(n8102) );
DFFSX2TS R_1574 ( .D(n8804), .CK(clk), .SN(n8535), .Q(n8100) );
DFFSX2TS R_1577 ( .D(n8772), .CK(clk), .SN(n2370), .Q(n8099) );
DFFSX2TS R_1580 ( .D(n8773), .CK(clk), .SN(n2370), .Q(n8098) );
DFFSX2TS R_1583 ( .D(n8768), .CK(clk), .SN(n8532), .Q(n8097) );
DFFSX2TS R_1590 ( .D(n8764), .CK(clk), .SN(n8532), .Q(n8096) );
DFFSX2TS R_1596 ( .D(n8831), .CK(clk), .SN(n2400), .Q(n8095) );
DFFSX2TS R_1602 ( .D(n8816), .CK(clk), .SN(n2423), .Q(n8093) );
DFFSX2TS R_1605 ( .D(n8798), .CK(clk), .SN(n2388), .Q(n8092) );
DFFSX2TS R_1606 ( .D(n5896), .CK(clk), .SN(n8539), .Q(n8091) );
DFFSX2TS R_1608 ( .D(n8759), .CK(clk), .SN(n8539), .Q(n8090) );
DFFSX2TS R_1609 ( .D(n8782), .CK(clk), .SN(n8539), .Q(n8089) );
DFFSX2TS R_1611 ( .D(n8760), .CK(clk), .SN(n8539), .Q(n8088) );
DFFSX2TS R_1612 ( .D(n8783), .CK(clk), .SN(n8539), .Q(n8087) );
DFFSX2TS R_1614 ( .D(n8761), .CK(clk), .SN(n8535), .Q(n8086) );
DFFRXLTS R_1270_RW_0 ( .D(FPSENCOS_d_ff2_Z[0]), .CK(clk), .RN(n7967), .Q(
n8190) );
DFFSX2TS R_1619 ( .D(n8756), .CK(clk), .SN(n7985), .Q(n8085) );
DFFSX2TS R_1625 ( .D(n8757), .CK(clk), .SN(n7985), .Q(n8084) );
DFFSX2TS R_1631 ( .D(n8755), .CK(clk), .SN(n7985), .Q(n8083) );
DFFSX2TS R_1637 ( .D(n8825), .CK(clk), .SN(n2401), .Q(n8082) );
DFFSX2TS R_1640 ( .D(n8823), .CK(clk), .SN(n2400), .Q(n8081) );
DFFSX2TS R_1646 ( .D(n8789), .CK(clk), .SN(n8549), .Q(n8079) );
DFFSX2TS R_1649 ( .D(n8801), .CK(clk), .SN(n2388), .Q(n8078) );
DFFSX2TS R_1657 ( .D(n8606), .CK(clk), .SN(n7964), .Q(n8077) );
DFFSX2TS R_1660 ( .D(n8606), .CK(clk), .SN(n7969), .Q(n8076) );
DFFSX2TS R_1661 ( .D(n8606), .CK(clk), .SN(n7966), .Q(n8075) );
DFFSX2TS R_1662 ( .D(n8606), .CK(clk), .SN(n7959), .Q(n8074) );
DFFSX1TS R_1667 ( .D(FPMULT_Sgf_operation_Result[26]), .CK(clk), .SN(n2425),
.Q(n8072) );
DFFSX2TS R_1670 ( .D(FPMULT_Sgf_operation_Result[25]), .CK(clk), .SN(n2426),
.Q(n8070) );
DFFRX4TS R_1700 ( .D(n1632), .CK(clk), .RN(n8604), .Q(
DP_OP_496J2_122_3540_n1472), .QN(n3150) );
DFFRX4TS R_1699 ( .D(n1638), .CK(clk), .RN(n8598), .Q(
DP_OP_496J2_122_3540_n1478), .QN(n3172) );
DFFSX2TS R_1734 ( .D(n8525), .CK(clk), .SN(n8593), .Q(n8057) );
DFFSX2TS R_1739 ( .D(n8523), .CK(clk), .SN(n7985), .Q(n8056) );
DFFSX2TS R_1752 ( .D(n7826), .CK(clk), .SN(n7963), .Q(n8046) );
DFFSX2TS R_1759 ( .D(n5942), .CK(clk), .SN(n8537), .Q(n8042) );
DFFSX2TS R_1760 ( .D(n8790), .CK(clk), .SN(n6353), .Q(n8041) );
DFFSX2TS R_1762 ( .D(n8799), .CK(clk), .SN(n2388), .Q(n8039) );
DFFSX2TS R_1763 ( .D(n8802), .CK(clk), .SN(n2388), .Q(n8038) );
DFFSX2TS R_1767 ( .D(n8820), .CK(clk), .SN(n2423), .Q(n8034) );
DFFSX2TS R_1768 ( .D(n8834), .CK(clk), .SN(n7988), .Q(n8033) );
DFFSX2TS R_1769 ( .D(n5884), .CK(clk), .SN(n7985), .Q(n8032) );
DFFSX2TS R_1770 ( .D(n5878), .CK(clk), .SN(n7986), .Q(n8031) );
DFFSX2TS R_1771 ( .D(n8763), .CK(clk), .SN(n7985), .Q(n8030) );
DFFSX2TS R_1772 ( .D(n8733), .CK(clk), .SN(n7973), .Q(n8029) );
DFFSX2TS R_1773 ( .D(n8730), .CK(clk), .SN(n7969), .Q(n8028) );
DFFSX2TS R_1775 ( .D(n8742), .CK(clk), .SN(n7959), .Q(n8026) );
DFFSX2TS R_1776 ( .D(n8739), .CK(clk), .SN(n7966), .Q(n8025) );
DFFSX2TS R_1777 ( .D(n8724), .CK(clk), .SN(n7983), .Q(n8024) );
DFFSX2TS R_1778 ( .D(n8721), .CK(clk), .SN(n7983), .Q(n8023) );
DFFSX2TS R_1779 ( .D(n8718), .CK(clk), .SN(n7958), .Q(n8022) );
DFFSX2TS R_1780 ( .D(n8715), .CK(clk), .SN(n8547), .Q(n8021) );
DFFSX2TS R_1781 ( .D(n8712), .CK(clk), .SN(n7979), .Q(n8020) );
DFFSX2TS R_1784 ( .D(n7374), .CK(clk), .SN(n7976), .Q(n8017) );
DFFSX2TS R_1786 ( .D(n8810), .CK(clk), .SN(n2389), .Q(n8015) );
DFFSX2TS R_1789 ( .D(n8824), .CK(clk), .SN(n2401), .Q(n8012) );
DFFSX2TS R_1790 ( .D(n8828), .CK(clk), .SN(n2401), .Q(n8011) );
DFFSX2TS R_1791 ( .D(n8832), .CK(clk), .SN(n2400), .Q(n8010) );
DFFSX2TS R_1792 ( .D(n8784), .CK(clk), .SN(n8539), .Q(n8009) );
DFFSX2TS R_1793 ( .D(n8786), .CK(clk), .SN(n7986), .Q(n8008) );
DFFSX2TS R_1794 ( .D(n8817), .CK(clk), .SN(n2423), .Q(n8007) );
DFFSX2TS R_1795 ( .D(n5946), .CK(clk), .SN(n2423), .Q(n8006) );
DFFSX2TS R_1796 ( .D(n5945), .CK(clk), .SN(n2423), .Q(n8005) );
DFFSX2TS R_1798 ( .D(n8830), .CK(clk), .SN(n2400), .Q(n8003) );
DFFSX2TS R_1799 ( .D(n8787), .CK(clk), .SN(n7986), .Q(n8002) );
DFFSX2TS R_1800 ( .D(n8785), .CK(clk), .SN(n7986), .Q(n8001) );
DFFSX2TS R_1801 ( .D(n8736), .CK(clk), .SN(n8534), .Q(n8000) );
DFFSX2TS R_1802 ( .D(n8826), .CK(clk), .SN(n2401), .Q(n7999) );
DFFSX2TS R_1804 ( .D(n8727), .CK(clk), .SN(n7969), .Q(n7998) );
DFFSX2TS R_1805 ( .D(gt_x_74_A_23_), .CK(clk), .SN(n7985), .Q(n7997) );
DFFRX1TS R_1015 ( .D(n1336), .CK(clk), .RN(n2418), .Q(
FPADDSUB_Raw_mant_NRM_SWR[15]), .QN(n7940) );
DFFRXLTS R_1698 ( .D(n8065), .CK(clk), .RN(n7994), .QN(n7916) );
DFFRXLTS R_1705 ( .D(n8062), .CK(clk), .RN(n7994), .QN(n7915) );
DFFRXLTS R_1004 ( .D(n1672), .CK(clk), .RN(n2394), .Q(n8481), .QN(n7877) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_28_ ( .D(n1956), .CK(clk), .RN(
n8583), .Q(FPSENCOS_d_ff2_X[28]), .QN(n7860) );
DFFRX1TS R_632 ( .D(n1321), .CK(clk), .RN(n8541), .Q(
FPADDSUB_Raw_mant_NRM_SWR[21]), .QN(n7825) );
DFFRX1TS R_947 ( .D(n1335), .CK(clk), .RN(n2418), .Q(
FPADDSUB_Raw_mant_NRM_SWR[16]), .QN(n7823) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_0_ ( .D(n2137), .CK(clk), .RN(n8573),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[0]), .QN(n7822) );
DFFRX1TS R_1030 ( .D(n1333), .CK(clk), .RN(n8541), .Q(
FPADDSUB_Raw_mant_NRM_SWR[18]), .QN(n7821) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_0_ ( .D(n2139), .CK(clk), .RN(n8574),
.Q(FPSENCOS_cont_var_out[0]), .QN(n7819) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_1_ ( .D(n2142), .CK(clk), .RN(n8574),
.Q(FPSENCOS_cont_iter_out[1]), .QN(n7809) );
DFFRX1TS FPMULT_Sel_B_Q_reg_0_ ( .D(n1551), .CK(clk), .RN(n7993), .Q(
FPMULT_FSM_selector_B[0]), .QN(n7808) );
DFFRX2TS FPADDSUB_inst_ShiftRegister_Q_reg_4_ ( .D(n2148), .CK(clk), .RN(
n8530), .Q(n8838), .QN(n7939) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_31_ ( .D(n1910), .CK(clk), .RN(n8551), .Q(
FPSENCOS_d_ff_Yn[31]), .QN(n7804) );
DFFRX1TS FPSENCOS_reg_region_flag_Q_reg_1_ ( .D(n2136), .CK(clk), .RN(n8573),
.Q(FPSENCOS_d_ff1_shift_region_flag_out[1]), .QN(n7802) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_8_ ( .D(n1541), .CK(clk), .RN(
n7994), .Q(FPMULT_exp_oper_result[8]), .QN(n7801) );
DFFRX2TS FPMULT_Sel_B_Q_reg_1_ ( .D(n1550), .CK(clk), .RN(n2367), .Q(
FPMULT_FSM_selector_B[1]), .QN(n7791) );
DFFRX2TS FPMULT_Sel_A_Q_reg_0_ ( .D(n1691), .CK(clk), .RN(n2365), .Q(
FPMULT_FSM_selector_A), .QN(n7854) );
DFFRX2TS FPSENCOS_ITER_CONT_temp_reg_3_ ( .D(n2140), .CK(clk), .RN(n8574),
.Q(FPSENCOS_cont_iter_out[3]), .QN(n7790) );
DFFRX1TS FPSENCOS_reg_operation_Q_reg_0_ ( .D(n2082), .CK(clk), .RN(n8587),
.Q(FPSENCOS_d_ff1_operation_out), .QN(n7789) );
DFFRX4TS FPMULT_FS_Module_state_reg_reg_2_ ( .D(n1692), .CK(clk), .RN(n8635),
.Q(FPMULT_FS_Module_state_reg[2]), .QN(n7788) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_30_ ( .D(n1856), .CK(clk), .RN(
n8582), .Q(FPSENCOS_d_ff2_Y[30]), .QN(n7881) );
DFFRXLTS NaN_dff_Q_reg_0_ ( .D(NaN_reg), .CK(clk), .RN(n8575), .Q(NaN_flag)
);
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_29_ ( .D(n1857), .CK(clk), .RN(
n8582), .Q(FPSENCOS_d_ff2_Y[29]), .QN(n7879) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_27_ ( .D(n1859), .CK(clk), .RN(
n8584), .Q(FPSENCOS_d_ff2_Y[27]), .QN(n7880) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_26_ ( .D(n1860), .CK(clk), .RN(
n8585), .Q(FPSENCOS_d_ff2_Y[26]), .QN(n7885) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_25_ ( .D(n1861), .CK(clk), .RN(
n8585), .Q(FPSENCOS_d_ff2_Y[25]), .QN(n7884) );
DFFRX1TS FPSENCOS_reg_val_muxY_2stage_Q_reg_24_ ( .D(n1862), .CK(clk), .RN(
n8586), .Q(FPSENCOS_d_ff2_Y[24]), .QN(n7883) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_4_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]), .CK(clk), .RN(n8574), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .QN(n7792) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_1_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]), .CK(clk), .RN(n8574), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .QN(n7818) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_2_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]), .CK(clk), .RN(n8574), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .QN(n7813) );
CMPR32X2TS DP_OP_26J2_126_1325_U5 ( .A(DP_OP_26J2_126_1325_n14), .B(n2457),
.C(DP_OP_26J2_126_1325_n5), .CO(DP_OP_26J2_126_1325_n4), .S(
FPADDSUB_exp_rslt_NRM2_EW1[4]) );
CMPR32X2TS DP_OP_26J2_126_1325_U6 ( .A(DP_OP_26J2_126_1325_n15), .B(n2455),
.C(DP_OP_26J2_126_1325_n6), .CO(DP_OP_26J2_126_1325_n5), .S(
FPADDSUB_exp_rslt_NRM2_EW1[3]) );
CMPR32X2TS DP_OP_26J2_126_1325_U7 ( .A(DP_OP_26J2_126_1325_n16), .B(n2453),
.C(DP_OP_26J2_126_1325_n7), .CO(DP_OP_26J2_126_1325_n6), .S(
FPADDSUB_exp_rslt_NRM2_EW1[2]) );
CMPR32X2TS DP_OP_26J2_126_1325_U8 ( .A(DP_OP_26J2_126_1325_n17), .B(n2451),
.C(DP_OP_26J2_126_1325_n8), .CO(DP_OP_26J2_126_1325_n7), .S(
FPADDSUB_exp_rslt_NRM2_EW1[1]) );
DFFSX1TS add_x_69_R_1825 ( .D(FPMULT_Sgf_operation_EVEN1_S_B[19]), .CK(clk),
.SN(n7777), .Q(n7775) );
DFFSX1TS add_x_69_R_1824 ( .D(FPMULT_Sgf_operation_EVEN1_S_B[21]), .CK(clk),
.SN(n7777), .Q(n7774) );
DFFSX2TS add_x_69_R_1818 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[12]), .CK(
clk), .SN(n2426), .Q(n7768) );
DFFSX1TS add_x_69_R_1816 ( .D(add_x_69_n188), .CK(clk), .SN(n7776), .Q(n7766) );
DFFRXLTS add_x_69_R_1656 ( .D(add_x_69_n205), .CK(clk), .RN(n7779), .Q(n7755) );
DFFRXLTS add_x_69_R_1655 ( .D(add_x_69_n204), .CK(clk), .RN(n7778), .Q(n7754) );
DFFSX1TS add_x_69_R_1429 ( .D(add_x_69_n202), .CK(clk), .SN(n7777), .QN(
n7752) );
DFFSX1TS add_x_69_R_1650 ( .D(FPMULT_Sgf_operation_EVEN1_S_B[17]), .CK(clk),
.SN(n7777), .Q(n7750) );
DFFSX1TS add_x_69_R_1506 ( .D(FPMULT_Sgf_operation_EVEN1_S_B[18]), .CK(clk),
.SN(n7777), .Q(n7748) );
DFFRXLTS add_x_69_R_1051 ( .D(add_x_69_n202), .CK(clk), .RN(n7777), .Q(n7745) );
DFFSX1TS add_x_69_R_975 ( .D(add_x_69_n186), .CK(clk), .SN(n7777), .Q(n7744)
);
DFFSX1TS add_x_69_R_651 ( .D(add_x_69_n16), .CK(clk), .SN(n7777), .Q(n7743)
);
DFFSX4TS DP_OP_496J2_122_3540_R_1714 ( .D(n7725), .CK(clk), .SN(n7726), .Q(
DP_OP_496J2_122_3540_n1203) );
DFFSX4TS DP_OP_496J2_122_3540_R_1713 ( .D(n7724), .CK(clk), .SN(n8596), .Q(
DP_OP_496J2_122_3540_n1199) );
DFFSX4TS DP_OP_496J2_122_3540_R_1711 ( .D(n7722), .CK(clk), .SN(n7726), .Q(
DP_OP_496J2_122_3540_n1108) );
DFFSX4TS DP_OP_496J2_122_3540_R_1708 ( .D(n7721), .CK(clk), .SN(n7726), .Q(
DP_OP_496J2_122_3540_n1113), .QN(n7730) );
DFFSX2TS DP_OP_496J2_122_3540_R_1707 ( .D(n7720), .CK(clk), .SN(n7726), .Q(
DP_OP_496J2_122_3540_n1063) );
DFFSX4TS DP_OP_496J2_122_3540_R_1006 ( .D(n7719), .CK(clk), .SN(n2364), .Q(
DP_OP_496J2_122_3540_n1202), .QN(n7728) );
DFFRX4TS DP_OP_496J2_122_3540_R_835 ( .D(n7717), .CK(clk), .RN(n8600), .Q(
n7716), .QN(n7733) );
DFFSX4TS DP_OP_496J2_122_3540_R_701 ( .D(n7715), .CK(clk), .SN(n2368), .Q(
DP_OP_496J2_122_3540_n1192), .QN(n7731) );
DFFSX4TS DP_OP_496J2_122_3540_R_658 ( .D(n7714), .CK(clk), .SN(n7726), .Q(
DP_OP_496J2_122_3540_n1107), .QN(n7727) );
DFFSX4TS DP_OP_496J2_122_3540_R_999 ( .D(n7713), .CK(clk), .SN(n7726), .Q(
DP_OP_496J2_122_3540_n1120) );
DFFSX4TS DP_OP_496J2_122_3540_R_442 ( .D(n7712), .CK(clk), .SN(n7726), .Q(
DP_OP_496J2_122_3540_n1114) );
DFFRX1TS DP_OP_497J2_123_1725_R_860 ( .D(n1676), .CK(clk), .RN(n8599), .Q(
DP_OP_497J2_123_1725_n312) );
DFFSX4TS DP_OP_497J2_123_1725_R_859 ( .D(n7707), .CK(clk), .SN(n8596), .Q(
DP_OP_497J2_123_1725_n324), .QN(n7708) );
DFFSX4TS DP_OP_497J2_123_1725_R_857 ( .D(n7706), .CK(clk), .SN(n2364), .Q(
DP_OP_497J2_123_1725_n631), .QN(n3178) );
DFFSX4TS DP_OP_497J2_123_1725_R_850 ( .D(n7705), .CK(clk), .SN(n8604), .Q(
DP_OP_497J2_123_1725_n392), .QN(n3141) );
DFFRX4TS DP_OP_497J2_123_1725_R_851 ( .D(n1645), .CK(clk), .RN(n7995), .Q(
DP_OP_497J2_123_1725_n686) );
DFFRX4TS DP_OP_497J2_123_1725_R_853 ( .D(n1639), .CK(clk), .RN(n2363), .Q(
DP_OP_497J2_123_1725_n778) );
DFFSX4TS DP_OP_497J2_123_1725_R_690 ( .D(n7704), .CK(clk), .SN(n2394), .Q(
DP_OP_497J2_123_1725_n638) );
DFFRX4TS DP_OP_497J2_123_1725_R_681 ( .D(n1678), .CK(clk), .RN(n8599), .Q(
DP_OP_497J2_123_1725_n705) );
DFFSX4TS DP_OP_497J2_123_1725_R_854 ( .D(n7701), .CK(clk), .SN(n8604), .Q(
DP_OP_497J2_123_1725_n716), .QN(n3177) );
DFFSX4TS DP_OP_498J2_124_1725_R_1045 ( .D(n7696), .CK(clk), .SN(n2385), .Q(
DP_OP_498J2_124_1725_n635) );
DFFRX4TS DP_OP_498J2_124_1725_R_845 ( .D(n1667), .CK(clk), .RN(n2366), .Q(
DP_OP_498J2_124_1725_n796) );
DFFRX4TS DP_OP_498J2_124_1725_R_846 ( .D(n1661), .CK(clk), .RN(n2365), .Q(
DP_OP_498J2_124_1725_n802), .QN(n7698) );
DFFRX4TS DP_OP_498J2_124_1725_R_611 ( .D(n7693), .CK(clk), .RN(n2494), .Q(
DP_OP_498J2_124_1725_n390), .QN(n7700) );
DFFRX4TS DP_OP_498J2_124_1725_R_613 ( .D(n1666), .CK(clk), .RN(n2417), .Q(
DP_OP_498J2_124_1725_n795) );
DFFRX4TS DP_OP_498J2_124_1725_R_615 ( .D(n1660), .CK(clk), .RN(n2368), .Q(
DP_OP_498J2_124_1725_n801) );
DFFSX4TS DP_OP_498J2_124_1725_R_608 ( .D(n7689), .CK(clk), .SN(n2393), .Q(
DP_OP_498J2_124_1725_n732) );
DFFSX4TS DP_OP_498J2_124_1725_R_1043 ( .D(n7690), .CK(clk), .SN(n2420), .Q(
DP_OP_498J2_124_1725_n645) );
DFFSX4TS DP_OP_498J2_124_1725_R_282 ( .D(n5702), .CK(clk), .SN(n2385), .Q(
DP_OP_498J2_124_1725_n636), .QN(n7694) );
DFFSX4TS DP_OP_498J2_124_1725_R_606 ( .D(n7687), .CK(clk), .SN(n2368), .Q(
DP_OP_498J2_124_1725_n722) );
DFFSX1TS DP_OP_499J2_125_1651_R_1682 ( .D(DP_OP_499J2_125_1651_n34), .CK(clk), .SN(n2425), .QN(n7684) );
DFFSX1TS DP_OP_499J2_125_1651_R_1677 ( .D(DP_OP_499J2_125_1651_n6), .CK(clk),
.SN(n8578), .Q(n7682) );
DFFRXLTS DP_OP_499J2_125_1651_R_1674 ( .D(n7685), .CK(clk), .RN(n2424), .Q(
n7681) );
DFFRXLTS DP_OP_499J2_125_1651_R_1659 ( .D(DP_OP_499J2_125_1651_n8), .CK(clk),
.RN(n2470), .Q(n7680) );
DFFSX1TS DP_OP_499J2_125_1651_R_1658 ( .D(DP_OP_499J2_125_1651_n62), .CK(clk), .SN(n8562), .Q(n7679) );
DFFRXLTS DP_OP_499J2_125_1651_R_1459 ( .D(DP_OP_499J2_125_1651_n4), .CK(clk),
.RN(n2426), .Q(n7678) );
DFFSX1TS DP_OP_499J2_125_1651_R_1458 ( .D(DP_OP_499J2_125_1651_n39), .CK(clk), .SN(n2426), .Q(n7677) );
DFFRXLTS DP_OP_499J2_125_1651_R_1377 ( .D(DP_OP_499J2_125_1651_n5), .CK(clk),
.RN(n8591), .Q(n7675) );
DFFSX1TS DP_OP_499J2_125_1651_R_1376 ( .D(DP_OP_499J2_125_1651_n44), .CK(clk), .SN(n2425), .Q(n7674) );
DFFRXLTS R_657 ( .D(n1630), .CK(clk), .RN(n2385), .QN(n7803) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_12_ ( .D(n1268), .CK(clk), .RN(n8542),
.Q(FPADDSUB_DMP_SFG[12]) );
DFFRXLTS R_1047 ( .D(n1668), .CK(clk), .RN(n2394), .QN(n8340) );
DFFRHQX2TS FPADDSUB_inst_ShiftRegister_Q_reg_6_ ( .D(n2150), .CK(clk), .RN(
n2422), .Q(n8523) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n1650), .CK(clk),
.RN(n7995), .Q(FPMULT_Op_MY[23]), .QN(n8418) );
DFFRXLTS R_1142 ( .D(FPSENCOS_d_ff2_Z[18]), .CK(clk), .RN(n7957), .Q(n8248)
);
DFFSRX2TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n1523), .CK(
clk), .SN(1'b1), .RN(n2492), .Q(FPMULT_Sgf_normalized_result[6]) );
DFFSRX4TS FPMULT_FS_Module_state_reg_reg_0_ ( .D(n1694), .CK(clk), .SN(1'b1),
.RN(n8635), .Q(FPMULT_FS_Module_state_reg[0]), .QN(n7794) );
DFFSRX4TS FPMULT_FS_Module_state_reg_reg_3_ ( .D(n1695), .CK(clk), .SN(1'b1),
.RN(n8635), .Q(FPMULT_FS_Module_state_reg[3]), .QN(n7817) );
DFFRXLTS R_259 ( .D(FPMULT_Adder_M_result_A_adder[22]), .CK(clk), .RN(n8603),
.Q(n8494) );
DFFRXLTS DP_OP_499J2_125_1651_R_1417 ( .D(DP_OP_499J2_125_1651_n3), .CK(clk),
.RN(n2424), .Q(n7676) );
DFFSX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_0_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]), .CK(clk), .SN(n8590), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .QN(n7815) );
DFFSX1TS R_5 ( .D(n8621), .CK(clk), .SN(n8591), .Q(n8516) );
DFFRXLTS R_68 ( .D(n1586), .CK(clk), .RN(n7992), .Q(n8502) );
DFFRXLTS R_330 ( .D(n8723), .CK(clk), .RN(n8532), .Q(n8478) );
DFFRXLTS R_389 ( .D(n1803), .CK(clk), .RN(n7968), .Q(n8455) );
DFFRXLTS R_475 ( .D(n1799), .CK(clk), .RN(n7981), .Q(n8443) );
DFFRXLTS R_565 ( .D(n1518), .CK(clk), .RN(n2392), .Q(
FPMULT_Sgf_normalized_result[1]) );
DFFSX1TS R_743 ( .D(n8657), .CK(clk), .SN(n2370), .Q(n8387) );
DFFRXLTS R_1078 ( .D(FPSENCOS_d_ff3_sh_x_out[5]), .CK(clk), .RN(n7981), .Q(
n8280) );
DFFRXLTS R_1106 ( .D(FPSENCOS_d_ff2_Z[13]), .CK(clk), .RN(n7968), .Q(n8266)
);
DFFRXLTS R_1165 ( .D(FPSENCOS_d_ff2_Z[12]), .CK(clk), .RN(n7975), .Q(n8238)
);
DFFRXLTS R_1263 ( .D(FPSENCOS_d_ff2_Z[8]), .CK(clk), .RN(n7967), .Q(n8194)
);
DFFRXLTS R_1328 ( .D(FPSENCOS_d_ff3_sh_x_out[22]), .CK(clk), .RN(n8547), .Q(
n8162) );
DFFRXLTS R_1358 ( .D(n8835), .CK(clk), .RN(n7957), .Q(n8151) );
DFFRXLTS R_1423 ( .D(n8610), .CK(clk), .RN(n7984), .Q(n8141) );
DFFRXLTS R_1671 ( .D(n1578), .CK(clk), .RN(n2424), .Q(n8069) );
DFFRX1TS R_1748 ( .D(n8731), .CK(clk), .RN(n7967), .Q(n8050) );
DFFSX1TS R_1764 ( .D(n8805), .CK(clk), .SN(n8535), .Q(n8037) );
DFFRXLTS add_x_69_R_1807 ( .D(add_x_69_n39), .CK(clk), .RN(n2424), .Q(n7758)
);
DFFRXLTS add_x_69_R_49 ( .D(add_x_69_n59), .CK(clk), .RN(n7779), .Q(n7740)
);
DFFSHQX1TS DP_OP_496J2_122_3540_R_292 ( .D(n7710), .CK(clk), .SN(n2494), .Q(
n7709) );
DFFRX2TS FPSENCOS_VAR_CONT_temp_reg_1_ ( .D(n2138), .CK(clk), .RN(n8573),
.Q(FPSENCOS_cont_var_out[1]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_7_ ( .D(n1344), .CK(clk), .RN(
n8536), .Q(FPADDSUB_Raw_mant_NRM_SWR[7]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_2_ ( .D(n1349), .CK(clk), .RN(
n6353), .Q(FPADDSUB_Raw_mant_NRM_SWR[2]) );
DFFRX2TS FPSENCOS_reg_val_muxX_2stage_Q_reg_27_ ( .D(n1957), .CK(clk), .RN(
n8584), .Q(FPSENCOS_d_ff2_X[27]) );
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_12_ ( .D(n1339), .CK(clk), .RN(
n6354), .Q(FPADDSUB_Raw_mant_NRM_SWR[12]), .QN(n7867) );
DFFRX2TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_5_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]), .CK(clk), .RN(n8574), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]) );
DFFRHQX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_16_ ( .D(n1569), .CK(
clk), .RN(n8635), .Q(FPMULT_P_Sgf[16]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_3_ ( .D(n1348), .CK(clk), .RN(
n8533), .Q(FPADDSUB_Raw_mant_NRM_SWR[3]), .QN(n2334) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_5_ ( .D(n1346), .CK(clk), .RN(
n8549), .Q(FPADDSUB_Raw_mant_NRM_SWR[5]), .QN(n7797) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_6_ ( .D(n1345), .CK(clk), .RN(
n8536), .Q(FPADDSUB_Raw_mant_NRM_SWR[6]), .QN(n7810) );
DFFRX1TS FPMULT_Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n1540), .CK(clk), .RN(
n2365), .Q(FPMULT_Exp_module_Overflow_flag_A) );
DFFSX4TS R_1718 ( .D(n8521), .CK(clk), .SN(n2469), .Q(n8059), .QN(n2467) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_6_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]), .CK(clk), .RN(n8575), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_29_ ( .D(n1955), .CK(clk), .RN(
n8582), .Q(FPSENCOS_d_ff2_X[29]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n1525), .CK(
clk), .RN(n8598), .Q(FPMULT_Sgf_normalized_result[8]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n1529), .CK(
clk), .RN(n8604), .Q(FPMULT_Sgf_normalized_result[12]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n1532), .CK(
clk), .RN(n7993), .Q(FPMULT_Sgf_normalized_result[15]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n1534), .CK(
clk), .RN(n7994), .Q(FPMULT_Sgf_normalized_result[17]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n1538), .CK(
clk), .RN(n8604), .Q(FPMULT_Sgf_normalized_result[21]) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_3_ ( .D(n8611), .CK(clk),
.RN(n8574), .Q(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_4_ ( .D(n1347), .CK(clk), .RN(
n6354), .Q(FPADDSUB_Raw_mant_NRM_SWR[4]), .QN(n7816) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n1527), .CK(
clk), .RN(n8598), .Q(FPMULT_Sgf_normalized_result[10]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n1535), .CK(
clk), .RN(n2492), .Q(FPMULT_Sgf_normalized_result[18]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n1536), .CK(
clk), .RN(n2492), .Q(FPMULT_Sgf_normalized_result[19]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n1537), .CK(
clk), .RN(n2492), .Q(FPMULT_Sgf_normalized_result[20]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_1_ ( .D(n1350), .CK(clk), .RN(
n8533), .Q(FPADDSUB_Raw_mant_NRM_SWR[1]), .QN(n2294) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n1686), .CK(clk),
.RN(n2366), .Q(FPMULT_Op_MX[27]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_9_ ( .D(n1342), .CK(clk), .RN(
n6353), .Q(FPADDSUB_Raw_mant_NRM_SWR[9]), .QN(n7812) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n1623), .CK(clk), .RN(
n8601), .Q(FPMULT_Add_result[1]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n1622), .CK(clk), .RN(
n8601), .Q(FPMULT_Add_result[2]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n1621), .CK(clk), .RN(
n8601), .Q(FPMULT_Add_result[3]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n1619), .CK(clk), .RN(
n8601), .Q(FPMULT_Add_result[5]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n1609), .CK(clk),
.RN(n8602), .Q(FPMULT_Add_result[15]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n1607), .CK(clk),
.RN(n8603), .Q(FPMULT_Add_result[17]) );
DFFRX1TS operation_dff_Q_reg_0_ ( .D(operation[1]), .CK(clk), .RN(n8550),
.Q(operation_reg[0]) );
DFFRX1TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_8_ ( .D(n1343), .CK(clk), .RN(
n8549), .Q(FPADDSUB_Raw_mant_NRM_SWR[8]), .QN(n7793) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_7_ ( .D(n1542), .CK(clk), .RN(
n8598), .Q(FPMULT_exp_oper_result[7]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_6_ ( .D(n1543), .CK(clk), .RN(
n2366), .Q(FPMULT_exp_oper_result[6]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_5_ ( .D(n1544), .CK(clk), .RN(
n2391), .Q(FPMULT_exp_oper_result[5]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_3_ ( .D(n1546), .CK(clk), .RN(
n2363), .Q(FPMULT_exp_oper_result[3]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_2_ ( .D(n1547), .CK(clk), .RN(
n2385), .Q(FPMULT_exp_oper_result[2]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_1_ ( .D(n1548), .CK(clk), .RN(
n2367), .Q(FPMULT_exp_oper_result[1]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_0_ ( .D(n1549), .CK(clk), .RN(
n2384), .Q(FPMULT_exp_oper_result[0]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_26_ ( .D(n1958), .CK(clk), .RN(
n8584), .Q(FPSENCOS_d_ff2_X[26]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n1526), .CK(
clk), .RN(n8604), .Q(FPMULT_Sgf_normalized_result[9]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n1528), .CK(
clk), .RN(n7993), .Q(FPMULT_Sgf_normalized_result[11]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n1530), .CK(
clk), .RN(n8598), .Q(FPMULT_Sgf_normalized_result[13]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n1539), .CK(
clk), .RN(n7993), .Q(FPMULT_Sgf_normalized_result[22]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_5_ ( .D(n2059), .CK(clk), .RN(n8565), .Q(
FPSENCOS_d_ff_Xn[5]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_1_ ( .D(n2071), .CK(clk), .RN(n8567), .Q(
FPSENCOS_d_ff_Xn[1]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_7_ ( .D(n2053), .CK(clk), .RN(n8568), .Q(
FPSENCOS_d_ff_Xn[7]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_2_ ( .D(n2068), .CK(clk), .RN(n8569), .Q(
FPSENCOS_d_ff_Xn[2]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_3_ ( .D(n2065), .CK(clk), .RN(n8550), .Q(
FPSENCOS_d_ff_Xn[3]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_12_ ( .D(n2038), .CK(clk), .RN(n8552), .Q(
FPSENCOS_d_ff_Xn[12]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_10_ ( .D(n2044), .CK(clk), .RN(n8553), .Q(
FPSENCOS_d_ff_Xn[10]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_14_ ( .D(n2032), .CK(clk), .RN(n8554), .Q(
FPSENCOS_d_ff_Xn[14]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_16_ ( .D(n2026), .CK(clk), .RN(n8556), .Q(
FPSENCOS_d_ff_Xn[16]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_13_ ( .D(n2035), .CK(clk), .RN(n8557), .Q(
FPSENCOS_d_ff_Xn[13]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_6_ ( .D(n2056), .CK(clk), .RN(n8558), .Q(
FPSENCOS_d_ff_Xn[6]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_17_ ( .D(n2023), .CK(clk), .RN(n8559), .Q(
FPSENCOS_d_ff_Xn[17]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_20_ ( .D(n2014), .CK(clk), .RN(n8560), .Q(
FPSENCOS_d_ff_Xn[20]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_19_ ( .D(n2017), .CK(clk), .RN(n8561), .Q(
FPSENCOS_d_ff_Xn[19]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_24_ ( .D(n1783), .CK(clk), .RN(n8586), .Q(
FPSENCOS_d_ff_Xn[24]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_28_ ( .D(n1771), .CK(clk), .RN(n8583), .Q(
FPSENCOS_d_ff_Xn[28]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_9_ ( .D(n2047), .CK(clk), .RN(n8566), .Q(
FPSENCOS_d_ff_Xn[9]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_0_ ( .D(n2074), .CK(clk), .RN(n8567), .Q(
FPSENCOS_d_ff_Xn[0]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_11_ ( .D(n2041), .CK(clk), .RN(n8554), .Q(
FPSENCOS_d_ff_Xn[11]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_8_ ( .D(n2050), .CK(clk), .RN(n8555), .Q(
FPSENCOS_d_ff_Xn[8]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_4_ ( .D(n2062), .CK(clk), .RN(n8559), .Q(
FPSENCOS_d_ff_Xn[4]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_21_ ( .D(n2011), .CK(clk), .RN(n8576), .Q(
FPSENCOS_d_ff_Xn[21]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_18_ ( .D(n2020), .CK(clk), .RN(n8579), .Q(
FPSENCOS_d_ff_Xn[18]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_15_ ( .D(n2029), .CK(clk), .RN(n8580), .Q(
FPSENCOS_d_ff_Xn[15]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_22_ ( .D(n2008), .CK(clk), .RN(n8581), .Q(
FPSENCOS_d_ff_Xn[22]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n1651), .CK(clk),
.RN(n7995), .Q(FPMULT_Op_MY[24]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_5_ ( .D(n2060), .CK(clk), .RN(n8565), .Q(
FPSENCOS_d_ff_Yn[5]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_9_ ( .D(n2048), .CK(clk), .RN(n8566), .Q(
FPSENCOS_d_ff_Yn[9]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_1_ ( .D(n2072), .CK(clk), .RN(n8567), .Q(
FPSENCOS_d_ff_Yn[1]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_0_ ( .D(n2075), .CK(clk), .RN(n8568), .Q(
FPSENCOS_d_ff_Yn[0]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_7_ ( .D(n2054), .CK(clk), .RN(n8569), .Q(
FPSENCOS_d_ff_Yn[7]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_2_ ( .D(n2069), .CK(clk), .RN(n8550), .Q(
FPSENCOS_d_ff_Yn[2]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_3_ ( .D(n2066), .CK(clk), .RN(n8551), .Q(
FPSENCOS_d_ff_Yn[3]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_12_ ( .D(n2039), .CK(clk), .RN(n8552), .Q(
FPSENCOS_d_ff_Yn[12]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_10_ ( .D(n2045), .CK(clk), .RN(n8553), .Q(
FPSENCOS_d_ff_Yn[10]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_14_ ( .D(n2033), .CK(clk), .RN(n8554), .Q(
FPSENCOS_d_ff_Yn[14]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_11_ ( .D(n2042), .CK(clk), .RN(n8555), .Q(
FPSENCOS_d_ff_Yn[11]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_8_ ( .D(n2051), .CK(clk), .RN(n8556), .Q(
FPSENCOS_d_ff_Yn[8]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_16_ ( .D(n2027), .CK(clk), .RN(n8556), .Q(
FPSENCOS_d_ff_Yn[16]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_13_ ( .D(n2036), .CK(clk), .RN(n8557), .Q(
FPSENCOS_d_ff_Yn[13]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_6_ ( .D(n2057), .CK(clk), .RN(n8558), .Q(
FPSENCOS_d_ff_Yn[6]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_4_ ( .D(n2063), .CK(clk), .RN(n8559), .Q(
FPSENCOS_d_ff_Yn[4]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_17_ ( .D(n2024), .CK(clk), .RN(n8560), .Q(
FPSENCOS_d_ff_Yn[17]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_20_ ( .D(n2015), .CK(clk), .RN(n8560), .Q(
FPSENCOS_d_ff_Yn[20]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_19_ ( .D(n2018), .CK(clk), .RN(n8561), .Q(
FPSENCOS_d_ff_Yn[19]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_21_ ( .D(n2012), .CK(clk), .RN(n8579), .Q(
FPSENCOS_d_ff_Yn[21]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_18_ ( .D(n2021), .CK(clk), .RN(n8580), .Q(
FPSENCOS_d_ff_Yn[18]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_15_ ( .D(n2030), .CK(clk), .RN(n8580), .Q(
FPSENCOS_d_ff_Yn[15]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_22_ ( .D(n2009), .CK(clk), .RN(n8581), .Q(
FPSENCOS_d_ff_Yn[22]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_28_ ( .D(n1772), .CK(clk), .RN(n8583), .Q(
FPSENCOS_d_ff_Yn[28]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_27_ ( .D(n1775), .CK(clk), .RN(n8584), .Q(
FPSENCOS_d_ff_Yn[27]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_26_ ( .D(n1778), .CK(clk), .RN(n8585), .Q(
FPSENCOS_d_ff_Yn[26]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_24_ ( .D(n1784), .CK(clk), .RN(n8586), .Q(
FPSENCOS_d_ff_Yn[24]) );
DFFRX1TS FPSENCOS_reg_val_muxZ_2stage_Q_reg_31_ ( .D(n1735), .CK(clk), .RN(
n8552), .Q(FPSENCOS_d_ff2_Z[31]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_30_ ( .D(n1954), .CK(clk), .RN(
n8582), .Q(FPSENCOS_d_ff2_X[30]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_31_ ( .D(n1945), .CK(clk), .RN(
n8551), .Q(FPSENCOS_d_ff2_X[31]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_10_ ( .D(n1563), .CK(clk),
.RN(n8592), .Q(FPMULT_P_Sgf[10]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_20_ ( .D(n1573), .CK(clk),
.RN(n8563), .Q(FPMULT_P_Sgf[20]) );
DFFSX1TS R_1691 ( .D(n8066), .CK(clk), .SN(n8593), .Q(n8641) );
DFFSX1TS R_1690 ( .D(n8067), .CK(clk), .SN(n8577), .Q(n8640) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_2_ ( .D(n1555), .CK(clk),
.RN(n2424), .Q(FPMULT_P_Sgf[2]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_17_ ( .D(n1570), .CK(clk),
.RN(n8563), .Q(FPMULT_P_Sgf[17]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_30_ ( .D(n1698), .CK(clk), .RN(n8581),
.Q(cordic_result[30]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_29_ ( .D(n1699), .CK(clk), .RN(n8582),
.Q(cordic_result[29]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_27_ ( .D(n1701), .CK(clk), .RN(n8584),
.Q(cordic_result[27]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_26_ ( .D(n1702), .CK(clk), .RN(n8584),
.Q(cordic_result[26]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_25_ ( .D(n1703), .CK(clk), .RN(n8585),
.Q(cordic_result[25]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_23_ ( .D(n1705), .CK(clk), .RN(n8586),
.Q(cordic_result[23]) );
DFFRX1TS FPSENCOS_d_ff5_data_out_Q_reg_31_ ( .D(n1697), .CK(clk), .RN(n8564),
.Q(cordic_result[31]) );
DFFRX1TS reg_dataA_Q_reg_30_ ( .D(Data_1[30]), .CK(clk), .RN(n8577), .Q(
dataA[30]) );
DFFRX1TS reg_dataA_Q_reg_29_ ( .D(Data_1[29]), .CK(clk), .RN(n8577), .Q(
dataA[29]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_31_ ( .D(n1358), .CK(clk), .RN(
n8536), .Q(result_add_subt[31]), .QN(n2343) );
DFFRX1TS DP_OP_497J2_123_1725_R_679 ( .D(n7702), .CK(clk), .RN(n2494), .Q(
DP_OP_497J2_123_1725_n668) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n1624), .CK(clk), .RN(
n8601), .Q(FPMULT_Add_result[0]) );
DFFRX1TS R_1073 ( .D(FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_), .CK(clk),
.RN(n2423), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_2_ ( .D(n2193), .CK(
clk), .RN(n2469), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]),
.QN(n7820) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_23_ ( .D(n1961), .CK(clk), .RN(
n8587), .Q(FPSENCOS_d_ff2_X[23]) );
DFFSX1TS R_1720 ( .D(n8746), .CK(clk), .SN(n7959), .Q(n2293), .QN(n2337) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n1684), .CK(clk),
.RN(n2366), .Q(FPMULT_Op_MX[25]) );
DFFRX1TS FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg_reg_0_ ( .D(n2151), .CK(
clk), .RN(n2469), .Q(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]),
.QN(n7795) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_25_ ( .D(n1959), .CK(clk), .RN(
n8585), .Q(FPSENCOS_d_ff2_X[25]) );
DFFRX1TS FPMULT_Exp_module_exp_result_m_Q_reg_4_ ( .D(n1545), .CK(clk), .RN(
n2366), .Q(FPMULT_exp_oper_result[4]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_24_ ( .D(n1960), .CK(clk), .RN(
n8586), .Q(FPSENCOS_d_ff2_X[24]) );
DFFRX1TS operation_dff_Q_reg_1_ ( .D(operation[2]), .CK(clk), .RN(n8577),
.Q(operation_reg[1]) );
DFFSX1TS R_1721 ( .D(n8748), .CK(clk), .SN(n2469), .Q(n2292), .QN(n2338) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_14_ ( .D(n1193), .CK(clk), .RN(
n2422), .Q(FPADDSUB_DmP_mant_SFG_SWR[14]), .QN(n7873) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n1533), .CK(
clk), .RN(n8604), .Q(FPMULT_Sgf_normalized_result[16]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_17_ ( .D(n1190), .CK(clk), .RN(
n8530), .Q(FPADDSUB_DmP_mant_SFG_SWR[17]), .QN(n7864) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_23_ ( .D(n1184), .CK(clk), .RN(
n8538), .Q(FPADDSUB_DmP_mant_SFG_SWR[23]), .QN(n7861) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_0_ ( .D(n1301), .CK(clk), .RN(
n2387), .Q(result_add_subt[0]), .QN(n7846) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_1_ ( .D(n1294), .CK(clk), .RN(
n2387), .Q(result_add_subt[1]), .QN(n7847) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_15_ ( .D(n1192), .CK(clk), .RN(
n2421), .Q(FPADDSUB_DmP_mant_SFG_SWR[15]), .QN(n7865) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n1654), .CK(clk),
.RN(n8600), .Q(FPMULT_Op_MY[27]) );
DFFSX1TS R_1761 ( .D(n8793), .CK(clk), .SN(n6354), .Q(n8040) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_2_ ( .D(n1315), .CK(clk), .RN(
n8534), .Q(result_add_subt[2]), .QN(n7844) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_3_ ( .D(n1331), .CK(clk), .RN(
n8535), .Q(result_add_subt[3]), .QN(n7843) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_7_ ( .D(n1308), .CK(clk), .RN(
n8537), .Q(result_add_subt[7]), .QN(n7845) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_29_ ( .D(n1768), .CK(clk), .RN(n8582), .Q(
FPSENCOS_d_ff_Xn[29]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_26_ ( .D(n1777), .CK(clk), .RN(n8585), .Q(
FPSENCOS_d_ff_Xn[26]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_27_ ( .D(n1774), .CK(clk), .RN(n8584), .Q(
FPSENCOS_d_ff_Xn[27]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_29_ ( .D(n1769), .CK(clk), .RN(n8583), .Q(
FPSENCOS_d_ff_Yn[29]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_30_ ( .D(n1732), .CK(clk), .RN(n8582), .Q(
FPSENCOS_d_ff_Yn[30]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_30_ ( .D(n1731), .CK(clk), .RN(n8582), .Q(
FPSENCOS_d_ff_Xn[30]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_23_ ( .D(n1787), .CK(clk), .RN(n8587), .Q(
FPSENCOS_d_ff_Yn[23]) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_23_ ( .D(n1786), .CK(clk), .RN(n8587), .Q(
FPSENCOS_d_ff_Xn[23]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_5_ ( .D(n1280), .CK(clk), .RN(
n6353), .Q(result_add_subt[5]), .QN(n7849) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_12_ ( .D(n1365), .CK(clk), .RN(
n6354), .Q(result_add_subt[12]), .QN(n7842) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_9_ ( .D(n1287), .CK(clk), .RN(
n6354), .Q(result_add_subt[9]), .QN(n7848) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_14_ ( .D(n1371), .CK(clk), .RN(
n8532), .Q(result_add_subt[14]), .QN(n7840) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_10_ ( .D(n1368), .CK(clk), .RN(
n8528), .Q(result_add_subt[10]), .QN(n7841) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_8_ ( .D(n1377), .CK(clk), .RN(
n8531), .Q(result_add_subt[8]), .QN(n7838) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_11_ ( .D(n1374), .CK(clk), .RN(
n7961), .Q(result_add_subt[11]), .QN(n7839) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_24_ ( .D(n1474), .CK(clk), .RN(
n2418), .Q(result_add_subt[24]), .QN(n7853) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_26_ ( .D(n1472), .CK(clk), .RN(
n2418), .Q(result_add_subt[26]), .QN(n7852) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_27_ ( .D(n1471), .CK(clk), .RN(
n8634), .Q(result_add_subt[27]), .QN(n7851) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_28_ ( .D(n1470), .CK(clk), .RN(
n8538), .Q(result_add_subt[28]), .QN(n7850) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_15_ ( .D(n1407), .CK(clk), .RN(
n7957), .Q(result_add_subt[15]), .QN(n7828) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_18_ ( .D(n1404), .CK(clk), .RN(
n8528), .Q(result_add_subt[18]), .QN(n7829) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_6_ ( .D(n1386), .CK(clk), .RN(
n8531), .Q(result_add_subt[6]), .QN(n7835) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_13_ ( .D(n1383), .CK(clk), .RN(
n8531), .Q(result_add_subt[13]), .QN(n7836) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_16_ ( .D(n1380), .CK(clk), .RN(
n8531), .Q(result_add_subt[16]), .QN(n7837) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_19_ ( .D(n1969), .CK(clk), .RN(
n8561), .Q(FPSENCOS_d_ff2_X[19]) );
DFFRXLTS R_1128 ( .D(FPSENCOS_d_ff2_X[19]), .CK(clk), .RN(n8529), .Q(n8255)
);
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_20_ ( .D(n1967), .CK(clk), .RN(
n8560), .Q(FPSENCOS_d_ff2_X[20]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_17_ ( .D(n1973), .CK(clk), .RN(
n8559), .Q(FPSENCOS_d_ff2_X[17]) );
DFFRXLTS R_1116 ( .D(FPSENCOS_d_ff2_X[17]), .CK(clk), .RN(n8539), .Q(n8261)
);
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_13_ ( .D(n1981), .CK(clk), .RN(
n8557), .Q(FPSENCOS_d_ff2_X[13]) );
DFFRXLTS R_1104 ( .D(FPSENCOS_d_ff2_X[13]), .CK(clk), .RN(n7969), .Q(n8267)
);
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_16_ ( .D(n1975), .CK(clk), .RN(
n8556), .Q(FPSENCOS_d_ff2_X[16]) );
DFFRXLTS R_1229 ( .D(FPSENCOS_d_ff2_X[16]), .CK(clk), .RN(n7968), .Q(n8207)
);
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_14_ ( .D(n1979), .CK(clk), .RN(
n8554), .Q(FPSENCOS_d_ff2_X[14]) );
DFFRXLTS R_1199 ( .D(FPSENCOS_d_ff2_X[14]), .CK(clk), .RN(n7972), .Q(n8221)
);
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_3_ ( .D(n2001), .CK(clk), .RN(
n8550), .Q(FPSENCOS_d_ff2_X[3]) );
DFFRXLTS R_1285 ( .D(FPSENCOS_d_ff2_X[3]), .CK(clk), .RN(n7975), .Q(n8183)
);
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_7_ ( .D(n1993), .CK(clk), .RN(
n8568), .Q(FPSENCOS_d_ff2_X[7]) );
DFFRXLTS R_1256 ( .D(FPSENCOS_d_ff2_X[7]), .CK(clk), .RN(n7978), .Q(n8197)
);
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_5_ ( .D(n1997), .CK(clk), .RN(
n8565), .Q(FPSENCOS_d_ff2_X[5]) );
DFFRXLTS R_1250 ( .D(FPSENCOS_d_ff2_X[5]), .CK(clk), .RN(n7982), .Q(n8199)
);
DFFRXLTS R_831 ( .D(n1661), .CK(clk), .RN(n2420), .QN(n8490) );
DFFRXLTS R_843 ( .D(n1661), .CK(clk), .RN(n2420), .Q(n8341) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n1603), .CK(clk),
.RN(n8603), .Q(FPMULT_Add_result[21]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n1604), .CK(clk),
.RN(n8603), .Q(FPMULT_Add_result[20]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n1605), .CK(clk),
.RN(n8603), .Q(FPMULT_Add_result[19]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n1606), .CK(clk),
.RN(n8603), .Q(FPMULT_Add_result[18]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_22_ ( .D(n1963), .CK(clk), .RN(
n8581), .Q(FPSENCOS_d_ff2_X[22]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_15_ ( .D(n1977), .CK(clk), .RN(
n8580), .Q(FPSENCOS_d_ff2_X[15]) );
DFFRXLTS R_1179 ( .D(FPSENCOS_d_ff2_X[15]), .CK(clk), .RN(n8532), .Q(n8231)
);
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_18_ ( .D(n1971), .CK(clk), .RN(
n8579), .Q(FPSENCOS_d_ff2_X[18]) );
DFFRXLTS R_1140 ( .D(FPSENCOS_d_ff2_X[18]), .CK(clk), .RN(n8548), .Q(n8249)
);
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_11_ ( .D(n1985), .CK(clk), .RN(
n8554), .Q(FPSENCOS_d_ff2_X[11]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_6_ ( .D(n1995), .CK(clk), .RN(
n8558), .Q(FPSENCOS_d_ff2_X[6]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_10_ ( .D(n1987), .CK(clk), .RN(
n8553), .Q(FPSENCOS_d_ff2_X[10]) );
DFFRXLTS R_1088 ( .D(FPSENCOS_d_ff2_X[10]), .CK(clk), .RN(n7972), .Q(n8275)
);
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_12_ ( .D(n1983), .CK(clk), .RN(
n8552), .Q(FPSENCOS_d_ff2_X[12]) );
DFFRXLTS R_1163 ( .D(FPSENCOS_d_ff2_X[12]), .CK(clk), .RN(n7974), .Q(n8239)
);
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_2_ ( .D(n2003), .CK(clk), .RN(
n8569), .Q(FPSENCOS_d_ff2_X[2]) );
DFFRXLTS R_1277 ( .D(FPSENCOS_d_ff2_X[2]), .CK(clk), .RN(n7978), .Q(n8187)
);
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_1_ ( .D(n2005), .CK(clk), .RN(
n8566), .Q(FPSENCOS_d_ff2_X[1]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_21_ ( .D(n1965), .CK(clk), .RN(
n8584), .Q(FPSENCOS_d_ff2_X[21]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_4_ ( .D(n1999), .CK(clk), .RN(
n8558), .Q(FPSENCOS_d_ff2_X[4]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_8_ ( .D(n1991), .CK(clk), .RN(
n8555), .Q(FPSENCOS_d_ff2_X[8]) );
DFFRXLTS R_1261 ( .D(FPSENCOS_d_ff2_X[8]), .CK(clk), .RN(n7968), .Q(n8195)
);
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_0_ ( .D(n2007), .CK(clk), .RN(
n8567), .Q(FPSENCOS_d_ff2_X[0]) );
DFFRX1TS FPSENCOS_reg_val_muxX_2stage_Q_reg_9_ ( .D(n1989), .CK(clk), .RN(
n8566), .Q(FPSENCOS_d_ff2_X[9]) );
DFFRXLTS R_1246 ( .D(FPSENCOS_d_ff2_X[9]), .CK(clk), .RN(n7982), .Q(n8201)
);
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_11_ ( .D(n1256), .CK(clk), .RN(n8542),
.Q(FPADDSUB_DMP_SFG[11]) );
DFFRX4TS FPADDSUB_SFT2FRMT_STAGE_FLAGS_Q_reg_2_ ( .D(n1352), .CK(clk), .RN(
n8634), .Q(FPADDSUB_ADD_OVRFLW_NRM2), .QN(n7806) );
DFFRX1TS reg_dataA_Q_reg_27_ ( .D(Data_1[27]), .CK(clk), .RN(n8578), .Q(
dataA[27]) );
DFFRX1TS reg_dataA_Q_reg_26_ ( .D(Data_1[26]), .CK(clk), .RN(n8578), .Q(
dataA[26]) );
DFFRX1TS reg_dataA_Q_reg_25_ ( .D(Data_1[25]), .CK(clk), .RN(n8578), .Q(
dataA[25]) );
DFFRX1TS reg_dataA_Q_reg_24_ ( .D(Data_1[24]), .CK(clk), .RN(n8578), .Q(
dataA[24]) );
DFFRX1TS reg_dataA_Q_reg_23_ ( .D(Data_1[23]), .CK(clk), .RN(n8578), .Q(
dataA[23]) );
DFFRX1TS reg_dataB_Q_reg_23_ ( .D(Data_2[23]), .CK(clk), .RN(n8576), .Q(
dataB[23]) );
DFFRX1TS R_1717 ( .D(n8060), .CK(clk), .RN(n8576), .Q(n8638) );
DFFRXLTS R_487 ( .D(n1793), .CK(clk), .RN(n7984), .Q(n8437) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_19_ ( .D(n1572), .CK(clk),
.RN(n8563), .Q(FPMULT_P_Sgf[19]) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_3_ ( .D(n2078), .CK(clk), .RN(
n7974), .Q(FPADDSUB_shift_value_SHT2_EWR[3]), .QN(n2490) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_13_ ( .D(n1566), .CK(clk),
.RN(n8563), .Q(FPMULT_P_Sgf[13]) );
DFFRX1TS reg_dataB_Q_reg_28_ ( .D(Data_2[28]), .CK(clk), .RN(n8575), .Q(
dataB[28]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_18_ ( .D(n1571), .CK(clk),
.RN(n8563), .Q(FPMULT_P_Sgf[18]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_15_ ( .D(n1568), .CK(clk),
.RN(n8563), .Q(FPMULT_P_Sgf[15]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_11_ ( .D(n1564), .CK(clk),
.RN(n8563), .Q(FPMULT_P_Sgf[11]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_4_ ( .D(n1557), .CK(clk),
.RN(n2424), .Q(FPMULT_P_Sgf[4]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_12_ ( .D(n1565), .CK(clk),
.RN(n8563), .Q(FPMULT_P_Sgf[12]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_3_ ( .D(n1556), .CK(clk),
.RN(n2425), .Q(FPMULT_P_Sgf[3]) );
DFFRXLTS add_x_246_R_250 ( .D(FPMULT_Sgf_normalized_result[23]), .CK(clk),
.RN(n2417), .Q(n7780) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n1657), .CK(clk),
.RN(n2417), .Q(FPMULT_Op_MY[30]), .QN(n8463) );
DFFRXLTS add_x_246_R_251 ( .D(add_x_246_n2), .CK(clk), .RN(n2417), .Q(n7781)
);
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n1618), .CK(clk), .RN(
n8601), .Q(FPMULT_Add_result[6]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n1620), .CK(clk), .RN(
n2417), .Q(FPMULT_Add_result[4]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_14_ ( .D(n1567), .CK(clk),
.RN(n8563), .Q(FPMULT_P_Sgf[14]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_5_ ( .D(n1558), .CK(clk),
.RN(n7991), .Q(FPMULT_P_Sgf[5]) );
DFFRXLTS R_471 ( .D(n1797), .CK(clk), .RN(n7982), .Q(n8445) );
DFFRX1TS FPSENCOS_inst_CORDIC_FSM_v3_state_reg_reg_7_ ( .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]), .CK(clk), .RN(n8574), .Q(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]) );
DFFRX1TS FPADDSUB_Ready_reg_Q_reg_0_ ( .D(n8612), .CK(clk), .RN(n2469), .Q(
ready_add_subt), .QN(n7800) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n1685), .CK(clk),
.RN(n2366), .Q(FPMULT_Op_MX[26]) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n1682), .CK(clk),
.RN(n2366), .Q(FPMULT_Op_MX[23]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n1608), .CK(clk),
.RN(n8602), .Q(FPMULT_Add_result[16]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n1610), .CK(clk),
.RN(n8602), .Q(FPMULT_Add_result[14]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n1611), .CK(clk),
.RN(n8602), .Q(FPMULT_Add_result[13]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n1612), .CK(clk),
.RN(n8602), .Q(FPMULT_Add_result[12]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n1613), .CK(clk),
.RN(n8602), .Q(FPMULT_Add_result[11]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n1614), .CK(clk),
.RN(n8602), .Q(FPMULT_Add_result[10]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n1615), .CK(clk), .RN(
n8602), .Q(FPMULT_Add_result[9]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n1616), .CK(clk), .RN(
n8602), .Q(FPMULT_Add_result[8]) );
DFFRX1TS FPMULT_Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n1617), .CK(clk), .RN(
n8602), .Q(FPMULT_Add_result[7]) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_19_ ( .D(n1188), .CK(clk), .RN(
n2347), .Q(FPADDSUB_DmP_mant_SFG_SWR[19]), .QN(n7863) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_21_ ( .D(n1186), .CK(clk), .RN(
n2421), .Q(FPADDSUB_DmP_mant_SFG_SWR[21]), .QN(n7862) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n1652), .CK(clk),
.RN(n8600), .Q(FPMULT_Op_MY[25]) );
DFFRX1TS FPMULT_Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n1653), .CK(clk),
.RN(n8600), .Q(FPMULT_Op_MY[26]) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n1531), .CK(
clk), .RN(n7993), .Q(FPMULT_Sgf_normalized_result[14]) );
DFFRX1TS FPMULT_Exp_module_Underflow_m_Q_reg_0_ ( .D(n1516), .CK(clk), .RN(
n2391), .Q(underflow_flag_mult), .QN(n7874) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_16_ ( .D(n1191), .CK(clk), .RN(
n2369), .Q(FPADDSUB_DmP_mant_SFG_SWR[16]), .QN(n7872) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_18_ ( .D(n1189), .CK(clk), .RN(
n2400), .Q(FPADDSUB_DmP_mant_SFG_SWR[18]), .QN(n7871) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_20_ ( .D(n1187), .CK(clk), .RN(
n2370), .Q(FPADDSUB_DmP_mant_SFG_SWR[20]), .QN(n7870) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_22_ ( .D(n1185), .CK(clk), .RN(
n7980), .Q(FPADDSUB_DmP_mant_SFG_SWR[22]), .QN(n7869) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_24_ ( .D(n1183), .CK(clk), .RN(
n2421), .Q(FPADDSUB_DmP_mant_SFG_SWR[24]), .QN(n7868) );
DFFRX1TS FPSENCOS_d_ff4_Xn_Q_reg_25_ ( .D(n1780), .CK(clk), .RN(n8585), .Q(
FPSENCOS_d_ff_Xn[25]) );
DFFRX1TS FPSENCOS_d_ff4_Yn_Q_reg_25_ ( .D(n1781), .CK(clk), .RN(n8585), .Q(
FPSENCOS_d_ff_Yn[25]) );
DFFRX1TS FPSENCOS_reg_sign_Q_reg_0_ ( .D(n1734), .CK(clk), .RN(n8552), .Q(
FPSENCOS_d_ff3_sign_out) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_9_ ( .D(n1562), .CK(clk),
.RN(n2425), .Q(FPMULT_P_Sgf[9]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_6_ ( .D(n1559), .CK(clk),
.RN(n8595), .Q(FPMULT_P_Sgf[6]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_8_ ( .D(n1561), .CK(clk),
.RN(n8578), .Q(FPMULT_P_Sgf[8]) );
DFFRX1TS FPMULT_Sgf_operation_EVEN1_finalreg_Q_reg_7_ ( .D(n1560), .CK(clk),
.RN(n8562), .Q(FPMULT_P_Sgf[7]) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_4_ ( .D(n2077), .CK(clk), .RN(
n7974), .Q(FPADDSUB_shift_value_SHT2_EWR[4]), .QN(n2340) );
DFFSX2TS R_1719 ( .D(n8522), .CK(clk), .SN(n7980), .Q(n8058), .QN(n2295) );
DFFRX1TS FPMULT_FS_Module_state_reg_reg_1_ ( .D(n1693), .CK(clk), .RN(n8569),
.Q(FPMULT_FS_Module_state_reg[1]), .QN(n3146) );
DFFRHQX8TS FPMULT_Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n1669), .CK(
clk), .RN(n2494), .Q(n2274) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_2_ ( .D(n1205), .CK(clk), .RN(
n2401), .Q(FPADDSUB_DmP_mant_SFG_SWR[2]), .QN(n7951) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_5_ ( .D(n1202), .CK(clk), .RN(
n8634), .Q(FPADDSUB_DmP_mant_SFG_SWR[5]), .QN(n7948) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_6_ ( .D(n1201), .CK(clk), .RN(
n2422), .Q(FPADDSUB_DmP_mant_SFG_SWR[6]), .QN(n7947) );
DFFRX1TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_8_ ( .D(n1199), .CK(clk), .RN(
n2348), .Q(FPADDSUB_DmP_mant_SFG_SWR[8]), .QN(n7946) );
DFFSX1TS R_2 ( .D(n8628), .CK(clk), .SN(n2425), .Q(n8517) );
DFFSX1TS R_8 ( .D(n8614), .CK(clk), .SN(n7776), .Q(n8515) );
DFFSX1TS R_11 ( .D(n8619), .CK(clk), .SN(n8562), .Q(n8514) );
DFFSX1TS R_14 ( .D(n8617), .CK(clk), .SN(n8576), .Q(n8513) );
DFFSX1TS R_17 ( .D(n8623), .CK(clk), .SN(n8594), .Q(n8512) );
DFFSX1TS R_20 ( .D(n8622), .CK(clk), .SN(n8562), .Q(n8511) );
DFFSX1TS R_23 ( .D(n8618), .CK(clk), .SN(n8562), .Q(n8510) );
DFFSX1TS R_26 ( .D(n8620), .CK(clk), .SN(n8593), .Q(n8509) );
DFFSX1TS R_29 ( .D(n8625), .CK(clk), .SN(n8562), .Q(n8508) );
DFFSX1TS R_30 ( .D(n6859), .CK(clk), .SN(n8576), .Q(n8507) );
DFFSX1TS R_32 ( .D(n8624), .CK(clk), .SN(n2470), .Q(n8506) );
DFFRXLTS R_34 ( .D(n1589), .CK(clk), .RN(n8562), .Q(n8505) );
DFFRXLTS R_65 ( .D(n1588), .CK(clk), .RN(n7992), .Q(n8503) );
DFFRXLTS R_71 ( .D(n1587), .CK(clk), .RN(n7992), .Q(n8501) );
DFFRXLTS R_74 ( .D(n1585), .CK(clk), .RN(n7992), .Q(n8500) );
DFFSX1TS R_168 ( .D(n8627), .CK(clk), .SN(n2417), .Q(n8498) );
DFFSX1TS R_174 ( .D(n8615), .CK(clk), .SN(n2417), .Q(n8495) );
DFFSX1TS R_260 ( .D(n8616), .CK(clk), .SN(n2420), .Q(n8493) );
DFFRXLTS R_268 ( .D(n1584), .CK(clk), .RN(n7992), .Q(n8492) );
DFFRXLTS R_272 ( .D(n1583), .CK(clk), .RN(n7992), .Q(n8491) );
DFFRX2TS R_296 ( .D(n1665), .CK(clk), .RN(n2363), .Q(
DP_OP_496J2_122_3540_n1512) );
DFFRXLTS R_334 ( .D(n8741), .CK(clk), .RN(n7984), .Q(n8477) );
DFFRXLTS R_336 ( .D(n1805), .CK(clk), .RN(n7955), .Q(n8476) );
DFFRXLTS R_342 ( .D(n8732), .CK(clk), .RN(n7981), .Q(n8474) );
DFFRXLTS R_344 ( .D(n1806), .CK(clk), .RN(n7981), .Q(n8473) );
DFFRXLTS R_352 ( .D(n1808), .CK(clk), .RN(n8549), .Q(n8471) );
DFFRXLTS R_360 ( .D(n1807), .CK(clk), .RN(n7982), .Q(n8469) );
DFFRXLTS R_364 ( .D(n1802), .CK(clk), .RN(n7990), .Q(n8467) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n1655), .CK(clk),
.RN(n8600), .Q(FPMULT_Op_MY[28]), .QN(n8465) );
DFFRXLTS FPMULT_Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n1656), .CK(clk),
.RN(n8600), .Q(FPMULT_Op_MY[29]), .QN(n8464) );
DFFRXLTS R_373 ( .D(n1801), .CK(clk), .RN(n7967), .Q(n8461) );
DFFRXLTS R_379 ( .D(n8738), .CK(clk), .RN(n8533), .Q(n8459) );
DFFRXLTS R_381 ( .D(n1804), .CK(clk), .RN(n7967), .Q(n8458) );
DFFRXLTS R_387 ( .D(n8716), .CK(clk), .RN(n7958), .Q(n8456) );
DFFRXLTS R_395 ( .D(n8729), .CK(clk), .RN(n7968), .Q(n8453) );
DFFRXLTS R_401 ( .D(n1809), .CK(clk), .RN(n7960), .Q(n8452) );
DFFRXLTS R_404 ( .D(n1629), .CK(clk), .RN(n2385), .QN(n8484) );
DFFRXLTS R_407 ( .D(n1810), .CK(clk), .RN(n7956), .Q(n8450) );
DFFRXLTS R_413 ( .D(n8717), .CK(clk), .RN(n7960), .Q(n8448) );
DFFRXLTS R_417 ( .D(n8735), .CK(clk), .RN(n7981), .Q(n8447) );
DFFRXLTS R_461 ( .D(n8726), .CK(clk), .RN(n7968), .Q(n8446) );
DFFRXLTS R_479 ( .D(n1800), .CK(clk), .RN(n7971), .Q(n8441) );
DFFRXLTS R_483 ( .D(n1798), .CK(clk), .RN(n7971), .Q(n8439) );
DFFRXLTS R_498 ( .D(n1791), .CK(clk), .RN(n7960), .Q(n8433) );
DFFRXLTS R_504 ( .D(n8720), .CK(clk), .RN(n7981), .Q(n8431) );
DFFRXLTS R_508 ( .D(n8745), .CK(clk), .RN(n8548), .Q(n8430) );
DFFSX1TS R_519 ( .D(n8626), .CK(clk), .SN(n7992), .Q(n8426) );
DFFRXLTS R_521 ( .D(n1796), .CK(clk), .RN(n7969), .Q(n8425) );
DFFRXLTS R_528 ( .D(n1792), .CK(clk), .RN(n7962), .Q(n8423) );
DFFRXLTS R_535 ( .D(n1790), .CK(clk), .RN(n7956), .Q(n8421) );
DFFRX1TS R_566 ( .D(n1517), .CK(clk), .RN(n2391), .Q(
FPMULT_Sgf_normalized_result[0]) );
DFFRXLTS R_564 ( .D(n1519), .CK(clk), .RN(n2392), .Q(
FPMULT_Sgf_normalized_result[2]) );
DFFRXLTS R_579 ( .D(n1582), .CK(clk), .RN(n7992), .Q(n8416) );
DFFRX1TS R_597 ( .D(n1317), .CK(clk), .RN(n2419), .Q(
FPADDSUB_Raw_mant_NRM_SWR[24]) );
DFFRX1TS R_596 ( .D(n1412), .CK(clk), .RN(n2419), .Q(
FPADDSUB_Raw_mant_NRM_SWR[25]) );
DFFRX1TS R_604 ( .D(n1319), .CK(clk), .RN(n8541), .Q(
FPADDSUB_Raw_mant_NRM_SWR[22]) );
DFFRX1TS R_603 ( .D(n1318), .CK(clk), .RN(n2419), .Q(
FPADDSUB_Raw_mant_NRM_SWR[23]) );
DFFRXLTS R_609 ( .D(n1666), .CK(clk), .RN(n2394), .QN(n8479) );
DFFRX1TS R_634 ( .D(n1323), .CK(clk), .RN(n8541), .Q(
FPADDSUB_Raw_mant_NRM_SWR[19]) );
DFFRXLTS R_653 ( .D(n6859), .CK(clk), .RN(n7992), .Q(n8413) );
DFFSX1TS R_682 ( .D(n8700), .CK(clk), .SN(n7962), .Q(n8410) );
DFFSX1TS R_715 ( .D(n8670), .CK(clk), .SN(n2369), .Q(n8401) );
DFFSX1TS R_726 ( .D(n7936), .CK(clk), .SN(n2399), .Q(n8396) );
DFFSX1TS R_786 ( .D(n7900), .CK(clk), .SN(n7962), .Q(n8366) );
DFFSX1TS R_787 ( .D(n8666), .CK(clk), .SN(n7962), .Q(n8365) );
DFFSX1TS R_790 ( .D(n7899), .CK(clk), .SN(n7962), .Q(n8364) );
DFFSX1TS R_791 ( .D(n8668), .CK(clk), .SN(n7962), .Q(n8363) );
DFFSX1TS R_794 ( .D(n7898), .CK(clk), .SN(n7962), .Q(n8362) );
DFFSX1TS R_795 ( .D(n8665), .CK(clk), .SN(n7962), .Q(n8361) );
DFFSX1TS R_807 ( .D(n8677), .CK(clk), .SN(n7954), .Q(n8355) );
DFFSX1TS R_810 ( .D(n7879), .CK(clk), .SN(n7954), .Q(n8354) );
DFFSX1TS R_811 ( .D(n8676), .CK(clk), .SN(n7954), .Q(n8353) );
DFFSX1TS R_814 ( .D(n7880), .CK(clk), .SN(n7954), .Q(n8352) );
DFFSX1TS R_815 ( .D(n8674), .CK(clk), .SN(n7954), .Q(n8351) );
DFFSX1TS R_818 ( .D(n7885), .CK(clk), .SN(n7954), .Q(n8350) );
DFFSX1TS R_819 ( .D(n8673), .CK(clk), .SN(n7954), .Q(n8349) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n1687), .CK(clk),
.RN(n2365), .Q(FPMULT_Op_MX[28]), .QN(n8339) );
DFFRX1TS FPMULT_Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n1688), .CK(clk),
.RN(n2365), .Q(FPMULT_Op_MX[29]), .QN(n8338) );
DFFRXLTS R_849 ( .D(n1639), .CK(clk), .RN(n7994), .Q(n8520) );
DFFRX1TS R_855 ( .D(DP_OP_497J2_123_1725_n779), .CK(clk), .RN(n7994), .Q(
n8485) );
DFFSX1TS R_906 ( .D(n8701), .CK(clk), .SN(n7962), .Q(n8315) );
DFFSX1TS R_909 ( .D(n7928), .CK(clk), .SN(n7954), .Q(n8314) );
DFFSX1TS R_910 ( .D(n8706), .CK(clk), .SN(n7954), .Q(n8313) );
DFFSX1TS R_914 ( .D(n8705), .CK(clk), .SN(n7954), .Q(n8311) );
DFFRX1TS R_948 ( .D(n1334), .CK(clk), .RN(n2419), .Q(
FPADDSUB_Raw_mant_NRM_SWR[17]) );
DFFRXLTS R_1005 ( .D(n1660), .CK(clk), .RN(n2394), .Q(n8488), .QN(n8342) );
DFFRXLTS R_1032 ( .D(n8291), .CK(clk), .RN(n2419), .Q(n8629) );
DFFRXLTS R_1042 ( .D(n1631), .CK(clk), .RN(n2385), .Q(FPMULT_Op_MY[4]), .QN(
n8483) );
DFFRXLTS R_1065 ( .D(FPSENCOS_d_ff3_LUT_out[27]), .CK(clk), .RN(n7952), .Q(
n8283) );
DFFRXLTS R_1076 ( .D(FPSENCOS_d_ff3_sh_y_out[5]), .CK(clk), .RN(n7982), .Q(
n8281) );
DFFRXLTS R_1084 ( .D(FPSENCOS_d_ff2_X[28]), .CK(clk), .RN(n7952), .Q(n8277)
);
DFFRXLTS R_1086 ( .D(FPSENCOS_d_ff2_Z[28]), .CK(clk), .RN(n7952), .Q(n8276)
);
DFFRXLTS R_1090 ( .D(FPSENCOS_d_ff2_Z[10]), .CK(clk), .RN(n7972), .Q(n8274)
);
DFFRXLTS R_1092 ( .D(FPSENCOS_d_ff3_sh_y_out[7]), .CK(clk), .RN(n7978), .Q(
n8273) );
DFFRXLTS R_1094 ( .D(FPSENCOS_d_ff3_sh_x_out[7]), .CK(clk), .RN(n7978), .Q(
n8272) );
DFFRXLTS R_1102 ( .D(FPSENCOS_d_ff2_Z[23]), .CK(clk), .RN(n7955), .Q(n8268)
);
DFFRXLTS R_1118 ( .D(FPSENCOS_d_ff2_Z[17]), .CK(clk), .RN(n8548), .Q(n8260)
);
DFFRXLTS R_1124 ( .D(FPSENCOS_d_ff3_sh_y_out[16]), .CK(clk), .RN(n7968), .Q(
n8257) );
DFFRXLTS R_1126 ( .D(FPSENCOS_d_ff3_sh_x_out[16]), .CK(clk), .RN(n7968), .Q(
n8256) );
DFFRXLTS R_1130 ( .D(FPSENCOS_d_ff2_Z[19]), .CK(clk), .RN(n8529), .Q(n8254)
);
DFFRXLTS R_1138 ( .D(FPSENCOS_d_ff2_Z[30]), .CK(clk), .RN(n7952), .Q(n8250)
);
DFFRXLTS R_1144 ( .D(FPSENCOS_d_ff2_X[25]), .CK(clk), .RN(n2369), .Q(n8247)
);
DFFRXLTS R_1148 ( .D(FPSENCOS_d_ff3_sh_y_out[17]), .CK(clk), .RN(n8547), .Q(
n8245) );
DFFRXLTS R_1150 ( .D(FPSENCOS_d_ff3_sh_x_out[17]), .CK(clk), .RN(n8529), .Q(
n8244) );
DFFRXLTS R_1159 ( .D(FPSENCOS_d_ff2_X[24]), .CK(clk), .RN(n2370), .Q(n8241)
);
DFFRXLTS R_1161 ( .D(FPSENCOS_d_ff2_Z[24]), .CK(clk), .RN(n8548), .Q(n8240)
);
DFFRXLTS R_1181 ( .D(FPSENCOS_d_ff2_Z[15]), .CK(clk), .RN(n8528), .Q(n8230)
);
DFFRXLTS R_1193 ( .D(FPSENCOS_d_ff2_Z[29]), .CK(clk), .RN(n7952), .Q(n8224)
);
DFFRXLTS R_1201 ( .D(FPSENCOS_d_ff2_Z[14]), .CK(clk), .RN(n7972), .Q(n8220)
);
DFFRXLTS R_1211 ( .D(FPSENCOS_d_ff2_Z[27]), .CK(clk), .RN(n7952), .Q(n8216)
);
DFFRXLTS R_1213 ( .D(FPSENCOS_d_ff3_sh_y_out[10]), .CK(clk), .RN(n7971), .Q(
n8215) );
DFFRXLTS R_1215 ( .D(FPSENCOS_d_ff3_LUT_out[10]), .CK(clk), .RN(n7971), .Q(
n8214) );
DFFRXLTS R_1219 ( .D(FPSENCOS_d_ff2_Z[11]), .CK(clk), .RN(n7971), .Q(n8212)
);
DFFRXLTS R_1221 ( .D(FPSENCOS_d_ff3_sh_y_out[4]), .CK(clk), .RN(n7964), .Q(
n8211) );
DFFRXLTS R_1223 ( .D(FPSENCOS_d_ff3_LUT_out[4]), .CK(clk), .RN(n7964), .Q(
n8210) );
DFFRXLTS R_1227 ( .D(FPSENCOS_d_ff2_Z[26]), .CK(clk), .RN(n8548), .Q(n8208)
);
DFFRXLTS R_1231 ( .D(FPSENCOS_d_ff2_Z[16]), .CK(clk), .RN(n7967), .Q(n8206)
);
DFFRXLTS R_1233 ( .D(FPSENCOS_d_ff3_sh_y_out[8]), .CK(clk), .RN(n7967), .Q(
n8205) );
DFFRXLTS R_1235 ( .D(FPSENCOS_d_ff3_LUT_out[8]), .CK(clk), .RN(n7967), .Q(
n8204) );
DFFRXLTS R_1237 ( .D(FPSENCOS_d_ff3_sh_y_out[6]), .CK(clk), .RN(n7964), .Q(
n8203) );
DFFRXLTS R_1239 ( .D(FPSENCOS_d_ff3_LUT_out[6]), .CK(clk), .RN(n7964), .Q(
n8202) );
DFFRXLTS R_1248 ( .D(FPSENCOS_d_ff2_Z[9]), .CK(clk), .RN(n7982), .Q(n8200)
);
DFFRXLTS R_1252 ( .D(FPSENCOS_d_ff2_Z[5]), .CK(clk), .RN(n7982), .Q(n8198)
);
DFFRXLTS R_1258 ( .D(FPSENCOS_d_ff2_Z[7]), .CK(clk), .RN(n7978), .Q(n8196)
);
DFFRXLTS R_1267 ( .D(FPSENCOS_d_ff2_Z[4]), .CK(clk), .RN(n7964), .Q(n8192)
);
DFFRXLTS R_1279 ( .D(FPSENCOS_d_ff2_Z[2]), .CK(clk), .RN(n7977), .Q(n8186)
);
DFFRXLTS R_1281 ( .D(FPSENCOS_d_ff3_sh_y_out[23]), .CK(clk), .RN(n8532), .Q(
n8185) );
DFFRXLTS R_1283 ( .D(FPSENCOS_d_ff3_LUT_out[23]), .CK(clk), .RN(n8532), .Q(
n8184) );
DFFRXLTS R_1287 ( .D(FPSENCOS_d_ff2_Z[3]), .CK(clk), .RN(n7975), .Q(n8182)
);
DFFRXLTS R_1295 ( .D(FPSENCOS_d_ff2_Z[6]), .CK(clk), .RN(n7964), .Q(n8178)
);
DFFRXLTS R_1305 ( .D(FPSENCOS_d_ff3_sh_y_out[24]), .CK(clk), .RN(n2418), .Q(
n8173) );
DFFRXLTS R_1313 ( .D(FPSENCOS_d_ff3_sh_y_out[20]), .CK(clk), .RN(n7960), .Q(
n8169) );
DFFRXLTS R_1315 ( .D(FPSENCOS_d_ff3_sh_x_out[20]), .CK(clk), .RN(n7960), .Q(
n8168) );
DFFRXLTS R_1322 ( .D(FPSENCOS_d_ff3_sh_y_out[19]), .CK(clk), .RN(n7960), .Q(
n8165) );
DFFRXLTS R_1324 ( .D(FPSENCOS_d_ff3_sh_x_out[19]), .CK(clk), .RN(n7960), .Q(
n8164) );
DFFRXLTS R_1326 ( .D(FPSENCOS_d_ff3_sh_y_out[22]), .CK(clk), .RN(n8547), .Q(
n8163) );
DFFRXLTS R_1336 ( .D(FPSENCOS_d_ff3_sh_y_out[30]), .CK(clk), .RN(n8529), .Q(
n8161) );
DFFRXLTS R_1338 ( .D(Data_2[30]), .CK(clk), .RN(n7957), .Q(n8160) );
DFFRXLTS R_1342 ( .D(FPSENCOS_d_ff3_sh_y_out[31]), .CK(clk), .RN(n7975), .Q(
n8159) );
DFFRXLTS R_1344 ( .D(Data_2[31]), .CK(clk), .RN(n7975), .Q(n8158) );
DFFRXLTS R_1346 ( .D(FPSENCOS_d_ff3_sh_y_out[28]), .CK(clk), .RN(n7956), .Q(
n8157) );
DFFRXLTS R_1348 ( .D(FPSENCOS_d_ff3_sh_x_out[28]), .CK(clk), .RN(n7956), .Q(
n8156) );
DFFRXLTS R_1350 ( .D(FPSENCOS_d_ff3_sh_y_out[29]), .CK(clk), .RN(n7956), .Q(
n8155) );
DFFRXLTS R_1352 ( .D(FPSENCOS_d_ff3_sh_x_out[29]), .CK(clk), .RN(n7956), .Q(
n8154) );
DFFRXLTS R_1389 ( .D(FPSENCOS_d_ff3_LUT_out[19]), .CK(clk), .RN(n7956), .Q(
n8146) );
DFFSX1TS R_510_RW_0 ( .D(n8716), .CK(clk), .SN(n7989), .Q(n8429) );
DFFSX1TS R_516_RW_0 ( .D(n8741), .CK(clk), .SN(n7989), .Q(n8427) );
DFFSX1TS R_523_RW_0 ( .D(n8738), .CK(clk), .SN(n7989), .Q(n8424) );
DFFSX1TS R_530_RW_0 ( .D(n8745), .CK(clk), .SN(n7989), .Q(n8422) );
DFFSX1TS R_537_RW_0 ( .D(n8751), .CK(clk), .SN(n7989), .Q(n8420) );
DFFSX1TS R_362_RW_0 ( .D(n8722), .CK(clk), .SN(n7990), .Q(n8468) );
DFFSX1TS R_375_RW_0 ( .D(n8731), .CK(clk), .SN(n7990), .Q(n8460) );
DFFSX1TS R_391_RW_0 ( .D(n8728), .CK(clk), .SN(n7990), .Q(n8454) );
DFFSX1TS R_403_RW_0 ( .D(n8719), .CK(clk), .SN(n7990), .Q(n8451) );
DFFSX1TS R_473_RW_0 ( .D(n8737), .CK(clk), .SN(n7989), .Q(n8444) );
DFFSX1TS R_477_RW_0 ( .D(n8734), .CK(clk), .SN(n7989), .Q(n8442) );
DFFSX1TS R_489_RW_0 ( .D(n8743), .CK(clk), .SN(n7989), .Q(n8436) );
DFFSX1TS R_496_RW_0 ( .D(n8740), .CK(clk), .SN(n7989), .Q(n8434) );
DFFSX1TS R_500_RW_0 ( .D(n8747), .CK(clk), .SN(n7990), .Q(n8432) );
DFFRXLTS R_1414 ( .D(n1580), .CK(clk), .RN(n2425), .Q(n8144) );
DFFSX1TS R_1451 ( .D(n8808), .CK(clk), .SN(n2390), .Q(n8136) );
DFFSX1TS R_1468 ( .D(n8806), .CK(clk), .SN(n7985), .Q(n8131) );
DFFSX1TS R_1517 ( .D(n8807), .CK(clk), .SN(n7966), .Q(n8117) );
DFFSX1TS R_1538 ( .D(n8836), .CK(clk), .SN(n7990), .Q(n8111) );
DFFSX1TS R_1541 ( .D(n8812), .CK(clk), .SN(n2390), .Q(n8110) );
DFFSX1TS R_1562 ( .D(n8811), .CK(clk), .SN(n2390), .Q(n8104) );
DFFSX1TS R_1571 ( .D(n8809), .CK(clk), .SN(n2390), .Q(n8101) );
DFFSX1TS R_1599 ( .D(n8814), .CK(clk), .SN(n2390), .Q(n8094) );
DFFSX1TS R_1643 ( .D(n8833), .CK(clk), .SN(n7990), .Q(n8080) );
DFFRXLTS R_1664 ( .D(n1813), .CK(clk), .RN(n7977), .Q(n8073) );
DFFRXLTS R_1668 ( .D(n1579), .CK(clk), .RN(n2426), .Q(n8071) );
DFFRXLTS R_1684 ( .D(n1811), .CK(clk), .RN(n7977), .Q(n8068) );
DFFSX1TS R_1701 ( .D(n8064), .CK(clk), .SN(n2394), .Q(n8632) );
DFFRXLTS R_1702 ( .D(n8063), .CK(clk), .RN(n2418), .Q(n8645) );
DFFSX1TS R_1716 ( .D(n8061), .CK(clk), .SN(n8593), .Q(n8639) );
DFFRX1TS R_1743 ( .D(n8747), .CK(clk), .RN(n7956), .Q(n8055) );
DFFRX1TS R_1744 ( .D(n8743), .CK(clk), .RN(n7960), .Q(n8054) );
DFFRX1TS R_1745 ( .D(n8740), .CK(clk), .RN(n7982), .Q(n8053) );
DFFRX1TS R_1746 ( .D(n8737), .CK(clk), .RN(n7971), .Q(n8052) );
DFFRX1TS R_1747 ( .D(n8734), .CK(clk), .RN(n7971), .Q(n8051) );
DFFRX1TS R_1749 ( .D(n8728), .CK(clk), .RN(n7967), .Q(n8049) );
DFFRX1TS R_1750 ( .D(n8722), .CK(clk), .RN(n7959), .Q(n8048) );
DFFRX1TS R_1751 ( .D(n8719), .CK(clk), .RN(n7977), .Q(n8047) );
DFFRX1TS R_1753 ( .D(n8725), .CK(clk), .RN(n6352), .Q(n8045) );
DFFSX1TS R_1756 ( .D(n8524), .CK(clk), .SN(n2425), .Q(n8044) );
DFFSX1TS R_1757 ( .D(n7827), .CK(clk), .SN(n2420), .Q(n8043) );
DFFSX1TS R_1765 ( .D(n8813), .CK(clk), .SN(n2390), .Q(n8036) );
DFFSX1TS R_1766 ( .D(n8815), .CK(clk), .SN(n2390), .Q(n8035) );
DFFRX1TS R_1774 ( .D(n8751), .CK(clk), .RN(n7987), .Q(n8027) );
DFFRX1TS R_1782 ( .D(n8714), .CK(clk), .RN(n7977), .Q(n8019) );
DFFRX1TS R_1783 ( .D(n6864), .CK(clk), .RN(n7984), .Q(n8018) );
DFFRX1TS R_1785 ( .D(n8750), .CK(clk), .RN(n7987), .Q(n8016) );
DFFSX1TS R_1787 ( .D(n5914), .CK(clk), .SN(n2390), .Q(n8014) );
DFFSX1TS R_1788 ( .D(n6009), .CK(clk), .SN(n2422), .Q(n8013) );
DFFSX1TS R_1797 ( .D(n8837), .CK(clk), .SN(n7989), .Q(n8004) );
DFFRX1TS R_1806 ( .D(gt_x_74_B_23_), .CK(clk), .RN(n7984), .Q(n7996) );
DFFRX1TS FPMULT_Sel_C_Q_reg_0_ ( .D(n1690), .CK(clk), .RN(n8598), .Q(
FPMULT_FSM_selector_C), .QN(n7811) );
DFFRXLTS add_x_246_R_570 ( .D(n1517), .CK(clk), .RN(n2391), .Q(
add_x_246_A_0_), .QN(n7786) );
DFFSX1TS add_x_246_R_1706 ( .D(n7785), .CK(clk), .SN(n2392), .Q(
FPMULT_Adder_M_result_A_adder[4]) );
DFFRXLTS add_x_246_R_1486 ( .D(n7784), .CK(clk), .RN(n2391), .Q(
FPMULT_Adder_M_result_A_adder[5]) );
DFFRXLTS add_x_246_R_677 ( .D(n7782), .CK(clk), .RN(n2391), .Q(
FPMULT_Adder_M_result_A_adder[3]) );
DFFRX1TS add_x_246_R_569 ( .D(n1518), .CK(clk), .RN(n2391), .Q(
add_x_246_A_1_) );
DFFRXLTS add_x_246_R_568 ( .D(n1519), .CK(clk), .RN(n2391), .Q(
add_x_246_A_2_) );
DFFSX1TS add_x_69_R_1823 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[7]), .CK(clk), .SN(n7776), .Q(n7773) );
DFFSX1TS add_x_69_R_1822 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[8]), .CK(clk), .SN(n7776), .Q(n7772) );
DFFSX1TS add_x_69_R_1821 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[9]), .CK(clk), .SN(n7776), .Q(n7771) );
DFFSX1TS add_x_69_R_1820 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[10]), .CK(
clk), .SN(n7776), .Q(n7770) );
DFFSX1TS add_x_69_R_1819 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[11]), .CK(
clk), .SN(n7776), .Q(n7769) );
DFFRX1TS add_x_69_R_1815 ( .D(n3171), .CK(clk), .RN(n7779), .Q(n7765) );
DFFRX1TS add_x_69_R_1814 ( .D(n5723), .CK(clk), .RN(n7778), .Q(n7764) );
DFFRX1TS add_x_69_R_1813 ( .D(add_x_69_n94), .CK(clk), .RN(n7778), .Q(n7763)
);
DFFSX1TS add_x_69_R_1812 ( .D(add_x_69_n85), .CK(clk), .SN(n7778), .Q(n7762)
);
DFFRX1TS add_x_69_R_1809 ( .D(add_x_69_n57), .CK(clk), .RN(n7778), .Q(n7760)
);
DFFSX1TS add_x_69_R_1654 ( .D(add_x_69_n272), .CK(clk), .SN(n8590), .Q(n7753) );
DFFRXLTS add_x_69_R_1651 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[5]), .CK(clk), .RN(n7777), .Q(n7751) );
DFFSX1TS add_x_69_R_1507 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[6]), .CK(clk), .SN(n7777), .Q(n7749) );
DFFRXLTS add_x_69_R_1071 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[13]), .CK(
clk), .RN(n2425), .Q(n7747) );
DFFSX1TS add_x_69_R_1055 ( .D(FPMULT_Sgf_operation_EVEN1_Q_left[13]), .CK(
clk), .SN(n7778), .Q(n7746) );
DFFSX1TS add_x_69_R_57 ( .D(add_x_69_n113), .CK(clk), .SN(n7778), .Q(n7742)
);
DFFRXLTS add_x_69_R_51 ( .D(n4902), .CK(clk), .RN(n7779), .Q(n7741) );
DFFRXLTS add_x_69_R_47 ( .D(n5300), .CK(clk), .RN(n7779), .Q(n7739) );
DFFRXLTS add_x_69_R_45 ( .D(add_x_69_n69), .CK(clk), .RN(n7779), .Q(n7738)
);
DFFRXLTS add_x_69_R_43 ( .D(add_x_69_n51), .CK(clk), .RN(n7779), .Q(n7737)
);
DFFRXLTS add_x_69_R_41 ( .D(n5596), .CK(clk), .RN(n7779), .Q(n7736) );
DFFRXLTS add_x_69_R_39 ( .D(n5443), .CK(clk), .RN(n7779), .Q(n7735) );
DFFRXLTS add_x_69_R_37 ( .D(n3149), .CK(clk), .RN(n2426), .Q(n7734) );
DFFRXLTS DP_OP_497J2_123_1725_R_691 ( .D(n1671), .CK(clk), .RN(n2394), .Q(
DP_OP_497J2_123_1725_n791) );
DFFRX1TS DP_OP_498J2_124_1725_R_283 ( .D(n1630), .CK(clk), .RN(n2384), .Q(
DP_OP_498J2_124_1725_n791) );
DFFRX2TS DP_OP_498J2_124_1725_R_278 ( .D(n1637), .CK(clk), .RN(n7995), .Q(
DP_OP_498J2_124_1725_n786) );
DFFRX1TS FPMULT_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n1524), .CK(
clk), .RN(n8598), .Q(FPMULT_Sgf_normalized_result[7]) );
DFFRX1TS DP_OP_498J2_124_1725_R_607 ( .D(n7692), .CK(clk), .RN(n7995), .Q(
DP_OP_498J2_124_1725_n718) );
DFFRX1TS DP_OP_497J2_123_1725_R_680 ( .D(n7703), .CK(clk), .RN(n2417), .Q(
DP_OP_497J2_123_1725_n669) );
DFFSX2TS DP_OP_496J2_122_3540_R_1712 ( .D(n7723), .CK(clk), .SN(n7994), .Q(
DP_OP_496J2_122_3540_n1193) );
DFFSX1TS R_989 ( .D(n8415), .CK(clk), .SN(n2419), .QN(n7857) );
DFFRHQX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_22_ ( .D(n1410), .CK(clk), .RN(
n2347), .Q(result_add_subt[22]) );
DFFRX2TS DP_OP_496J2_122_3540_R_1709_IP ( .D(n3148), .CK(clk), .RN(n2492),
.Q(n7729), .QN(DP_OP_496J2_122_3540_n1102) );
DFFRXLTS DP_OP_496J2_122_3540_R_1710_IP ( .D(n7668), .CK(clk), .RN(n2494),
.Q(n7732) );
DFFRHQX1TS DP_OP_498J2_124_1725_R_1046 ( .D(n1631), .CK(clk), .RN(n2492),
.Q(DP_OP_498J2_124_1725_n792) );
DFFSHQX1TS DP_OP_498J2_124_1725_R_1715 ( .D(n7697), .CK(clk), .SN(n2493),
.Q(DP_OP_498J2_124_1725_n362) );
DFFSHQX1TS DP_OP_498J2_124_1725_R_610 ( .D(n7691), .CK(clk), .SN(n2492), .Q(
n7688) );
DFFRHQX2TS R_842 ( .D(n1667), .CK(clk), .RN(n2494), .Q(
DP_OP_496J2_122_3540_n1514) );
DFFRX1TS DP_OP_498J2_124_1725_R_1044 ( .D(n7695), .CK(clk), .RN(n2493), .Q(
DP_OP_498J2_124_1725_n631) );
DFFRHQX1TS DP_OP_497J2_123_1725_R_856_IP ( .D(n3160), .CK(clk), .RN(n2494),
.Q(n7673) );
DFFRXLTS R_1195 ( .D(FPSENCOS_d_ff3_sh_y_out[9]), .CK(clk), .RN(n7982), .Q(
n8223) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_25_ ( .D(n1473), .CK(clk), .RN(
n2418), .Q(result_add_subt[25]) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_23_ ( .D(n1475), .CK(clk), .RN(
n2418), .Q(result_add_subt[23]), .QN(n7859) );
DFFRX2TS FPADDSUB_SHT2_STAGE_SHFTVARS2_Q_reg_1_ ( .D(n2080), .CK(clk), .RN(
n2369), .Q(FPADDSUB_left_right_SHT2), .QN(n2344) );
DFFSX1TS add_x_69_R_1817 ( .D(add_x_69_n201), .CK(clk), .SN(n7776), .Q(n7767) );
DFFRX1TS FPADDSUB_SHT2_STAGE_SHFTVARS1_Q_reg_2_ ( .D(n2079), .CK(clk), .RN(
n7974), .Q(FPADDSUB_shift_value_SHT2_EWR[2]), .QN(n7814) );
DFFSX1TS add_x_69_R_1758 ( .D(add_x_69_n198), .CK(clk), .SN(n7776), .Q(n7756), .QN(n7757) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_21_ ( .D(n1401), .CK(clk), .RN(
n2369), .Q(result_add_subt[21]), .QN(n7830) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_19_ ( .D(n1398), .CK(clk), .RN(
n2369), .Q(result_add_subt[19]), .QN(n7831) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_20_ ( .D(n1395), .CK(clk), .RN(
n2369), .Q(result_add_subt[20]), .QN(n7832) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_17_ ( .D(n1392), .CK(clk), .RN(
n2369), .Q(result_add_subt[17]), .QN(n7833) );
DFFRX1TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_4_ ( .D(n1389), .CK(clk), .RN(
n2369), .Q(result_add_subt[4]), .QN(n7834) );
DFFSRX2TS add_x_246_R_1485 ( .D(n7783), .CK(clk), .SN(1'b1), .RN(n2493), .Q(
add_x_246_n19) );
DFFSX4TS DP_OP_496J2_122_3540_R_427 ( .D(n7711), .CK(clk), .SN(n7726), .Q(
DP_OP_496J2_122_3540_n1103) );
DFFRX2TS DP_OP_496J2_122_3540_R_293 ( .D(n1677), .CK(clk), .RN(n7726), .Q(
DP_OP_496J2_122_3540_n1499) );
DFFRHQX2TS DP_OP_496J2_122_3540_R_1001 ( .D(n7718), .CK(clk), .RN(n7726),
.Q(n2270) );
DFFRX4TS R_276 ( .D(n1637), .CK(clk), .RN(n7993), .Q(FPMULT_Op_MY[10]), .QN(
n8417) );
DFFSX2TS R_1828 ( .D(n6040), .CK(clk), .SN(n7962), .Q(n2256) );
DFFSX2TS R_1829 ( .D(n7787), .CK(clk), .SN(n7959), .Q(n2255) );
DFFSX2TS R_1830 ( .D(n8609), .CK(clk), .SN(n2388), .Q(n2254) );
DFFSX2TS R_1831 ( .D(n8607), .CK(clk), .SN(n2390), .Q(n2253), .QN(n2252) );
DFFRXLTS R_1132 ( .D(FPSENCOS_d_ff2_X[21]), .CK(clk), .RN(n8547), .Q(n8253)
);
DFFRXLTS R_1134 ( .D(FPSENCOS_d_ff2_Z[21]), .CK(clk), .RN(n8548), .Q(n8252)
);
DFFRXLTS R_1175 ( .D(FPSENCOS_d_ff2_X[22]), .CK(clk), .RN(n8528), .Q(n8233)
);
DFFRXLTS R_1177 ( .D(FPSENCOS_d_ff2_Z[22]), .CK(clk), .RN(n8532), .Q(n8232)
);
DFFRXLTS R_1120 ( .D(FPSENCOS_d_ff2_X[20]), .CK(clk), .RN(n8528), .Q(n8259)
);
DFFRXLTS R_1122 ( .D(FPSENCOS_d_ff2_Z[20]), .CK(clk), .RN(n7961), .Q(n8258)
);
DFFRXLTS R_1146 ( .D(FPSENCOS_d_ff2_Z[25]), .CK(clk), .RN(n8547), .Q(n8246)
);
DFFRXLTS R_1100 ( .D(FPSENCOS_d_ff2_X[23]), .CK(clk), .RN(n8538), .Q(n8269)
);
DFFRXLTS R_1309 ( .D(FPSENCOS_d_ff3_sh_y_out[18]), .CK(clk), .RN(n8528), .Q(
n8171) );
DFFRXLTS R_1311 ( .D(FPSENCOS_d_ff3_sh_x_out[18]), .CK(clk), .RN(n7960), .Q(
n8170) );
DFFRXLTS R_1289 ( .D(FPSENCOS_d_ff3_sh_y_out[21]), .CK(clk), .RN(n8547), .Q(
n8181) );
DFFRXLTS R_1291 ( .D(FPSENCOS_d_ff3_LUT_out[21]), .CK(clk), .RN(n7961), .Q(
n8180) );
DFFRXLTS R_1318 ( .D(FPSENCOS_d_ff3_sh_y_out[27]), .CK(clk), .RN(n7953), .Q(
n8167) );
DFFRXLTS R_1320 ( .D(FPSENCOS_d_ff3_sh_x_out[27]), .CK(clk), .RN(n8534), .Q(
n8166) );
DFFRXLTS R_1297 ( .D(FPSENCOS_d_ff3_sh_y_out[26]), .CK(clk), .RN(n7973), .Q(
n8177) );
DFFRXLTS R_1299 ( .D(FPSENCOS_d_ff3_LUT_out[26]), .CK(clk), .RN(n8537), .Q(
n8176) );
DFFRXLTS R_1307 ( .D(FPSENCOS_d_ff3_LUT_out[24]), .CK(clk), .RN(n6352), .Q(
n8172) );
DFFRXLTS R_1301 ( .D(FPSENCOS_d_ff3_sh_y_out[25]), .CK(clk), .RN(n8535), .Q(
n8175) );
DFFRXLTS R_1303 ( .D(FPSENCOS_d_ff3_LUT_out[25]), .CK(clk), .RN(n8539), .Q(
n8174) );
DFFSX2TS R_1833 ( .D(n6859), .CK(clk), .SN(n2470), .Q(n2250) );
DFFSX2TS R_1834 ( .D(n8636), .CK(clk), .SN(n7973), .Q(n2249) );
DFFRX2TS R_1835 ( .D(n6859), .CK(clk), .RN(n7991), .Q(n2248) );
DFFSX2TS R_1836 ( .D(n7787), .CK(clk), .SN(n7959), .Q(n2247) );
DFFRX2TS R_1837 ( .D(n5303), .CK(clk), .RN(n7779), .Q(n2246) );
DFFSX2TS DP_OP_498J2_124_1725_R_844_IP ( .D(n3140), .CK(clk), .SN(n2493),
.Q(n7699), .QN(n2227) );
DFFRXLTS reg_dataB_Q_reg_25_ ( .D(Data_2[25]), .CK(clk), .RN(n8576), .Q(
dataB[25]) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n1683), .CK(clk),
.RN(n2365), .Q(FPMULT_Op_MX[24]), .QN(n8480) );
DFFRXLTS FPMULT_Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n1689), .CK(clk),
.RN(n2365), .Q(FPMULT_Op_MX[30]), .QN(n8337) );
DFFRXLTS add_x_69_R_1810 ( .D(n5717), .CK(clk), .RN(n7778), .Q(n7761) );
DFFRXLTS add_x_69_R_1808 ( .D(add_x_69_n47), .CK(clk), .RN(n7778), .Q(n7759)
);
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_3_ ( .D(n1204), .CK(clk), .RN(
n2387), .Q(FPADDSUB_DmP_mant_SFG_SWR[3]), .QN(n7950) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_11_ ( .D(n1196), .CK(clk), .RN(
n2347), .Q(FPADDSUB_DmP_mant_SFG_SWR[11]), .QN(n7941) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_8_ ( .D(n1252), .CK(clk), .RN(n7970),
.Q(FPADDSUB_DMP_SFG[8]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_10_ ( .D(n1197), .CK(clk), .RN(
n8530), .Q(FPADDSUB_DmP_mant_SFG_SWR[10]), .QN(n7944) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_9_ ( .D(n1281), .CK(clk), .RN(n7980),
.Q(FPADDSUB_DMP_SFG[9]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_4_ ( .D(n1203), .CK(clk), .RN(
n2399), .Q(FPADDSUB_DmP_mant_SFG_SWR[4]), .QN(n7949) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_6_ ( .D(n1240), .CK(clk), .RN(n2469),
.Q(FPADDSUB_DMP_SFG[6]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_7_ ( .D(n1302), .CK(clk), .RN(n7953),
.Q(FPADDSUB_DMP_SFG[7]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_7_ ( .D(n1200), .CK(clk), .RN(
n2389), .Q(FPADDSUB_DmP_mant_SFG_SWR[7]), .QN(n7942) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_9_ ( .D(n1198), .CK(clk), .RN(
n8538), .Q(FPADDSUB_DmP_mant_SFG_SWR[9]), .QN(n7945) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_5_ ( .D(n1274), .CK(clk), .RN(n7970),
.Q(FPADDSUB_DMP_SFG[5]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DMP_Q_reg_3_ ( .D(n1325), .CK(clk), .RN(n8538),
.Q(FPADDSUB_DMP_SFG[3]) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_1_ ( .D(n1206), .CK(clk), .RN(
n7980), .Q(FPADDSUB_DmP_mant_SFG_SWR[1]), .QN(n7943) );
DFFRX2TS FPADDSUB_SGF_STAGE_DmP_mant_Q_reg_13_ ( .D(n1194), .CK(clk), .RN(
n2421), .Q(FPADDSUB_DmP_mant_SFG_SWR[13]), .QN(n7866) );
DFFRX2TS FPADDSUB_SFT2FRMT_STAGE_VARS_Q_reg_8_ ( .D(n1316), .CK(clk), .RN(
n2347), .Q(FPADDSUB_LZD_output_NRM2_EW[0]) );
DFFSX2TS DP_OP_499J2_125_1651_R_1826 ( .D(n7686), .CK(clk), .SN(n2470), .Q(
n7683) );
CMPR32X2TS DP_OP_26J2_126_1325_U9 ( .A(n2449), .B(n7806), .C(
DP_OP_26J2_126_1325_n18), .CO(DP_OP_26J2_126_1325_n8), .S(
FPADDSUB_exp_rslt_NRM2_EW1[0]) );
DFFSX4TS R_1827 ( .D(n8605), .CK(clk), .SN(n7953), .Q(n2260), .QN(n2229) );
DFFRXLTS R_1217 ( .D(FPSENCOS_d_ff2_X[11]), .CK(clk), .RN(n7971), .Q(n8213)
);
DFFRXLTS R_1273 ( .D(FPSENCOS_d_ff2_X[1]), .CK(clk), .RN(n7981), .Q(n8189)
);
DFFRXLTS R_1269 ( .D(FPSENCOS_d_ff2_X[0]), .CK(clk), .RN(n7977), .Q(n8191)
);
DFFRX2TS FPADDSUB_NRM_STAGE_Raw_mant_Q_reg_10_ ( .D(n1341), .CK(clk), .RN(
n8541), .Q(FPADDSUB_Raw_mant_NRM_SWR[10]) );
DFFRXLTS R_1293 ( .D(FPSENCOS_d_ff2_X[6]), .CK(clk), .RN(n7964), .Q(n8179)
);
DFFRXLTS R_1265 ( .D(FPSENCOS_d_ff2_X[4]), .CK(clk), .RN(n7964), .Q(n8193)
);
DFFRX4TS FPSENCOS_ITER_CONT_temp_reg_2_ ( .D(n2141), .CK(clk), .RN(n8574),
.Q(n2196) );
DFFRXLTS R_1209 ( .D(FPSENCOS_d_ff2_X[27]), .CK(clk), .RN(n7952), .Q(n8217)
);
DFFRXLTS R_1191 ( .D(FPSENCOS_d_ff2_X[29]), .CK(clk), .RN(n7952), .Q(n8225)
);
DFFRX2TS R_1390 ( .D(n8749), .CK(clk), .RN(n7987), .Q(n2291), .QN(n3147) );
DFFRXLTS R_1225 ( .D(FPSENCOS_d_ff2_X[26]), .CK(clk), .RN(n7952), .Q(n8209)
);
DFFRXLTS R_1136 ( .D(FPSENCOS_d_ff2_X[30]), .CK(clk), .RN(n7952), .Q(n8251)
);
DFFRX2TS FPADDSUB_SGF_STAGE_FLAGS_Q_reg_1_ ( .D(n1354), .CK(clk), .RN(n2421),
.Q(FPADDSUB_OP_FLAG_SFG) );
DFFRXLTS R_557 ( .D(n1812), .CK(clk), .RN(n7977), .Q(n8419) );
DFFRXLTS R_494 ( .D(n1795), .CK(clk), .RN(n7964), .Q(n8435) );
DFFRXLTS R_514 ( .D(n1794), .CK(clk), .RN(n7956), .Q(n8428) );
CMPR32X2TS intadd_10_U4 ( .A(FPSENCOS_d_ff2_X[24]), .B(n7809), .C(
intadd_10_CI), .CO(intadd_10_n3), .S(intadd_10_SUM_0_) );
DFFRX2TS FPADDSUB_SHT2_SHIFT_DATA_Q_reg_25_ ( .D(n1814), .CK(clk), .RN(n7977), .Q(FPADDSUB_Data_array_SWR_3__25_), .QN(n2341) );
CMPR32X2TS intadd_10_U3 ( .A(FPSENCOS_d_ff2_X[25]), .B(intadd_9_B_1_), .C(
intadd_10_n3), .CO(intadd_10_n2), .S(intadd_10_SUM_1_) );
DFFRXLTS R_1152 ( .D(FPSENCOS_d_ff2_X[31]), .CK(clk), .RN(n7974), .Q(n8243)
);
DFFRXLTS R_1154 ( .D(FPSENCOS_d_ff2_Z[31]), .CK(clk), .RN(n7974), .Q(n8242)
);
CMPR32X2TS intadd_10_U2 ( .A(FPSENCOS_d_ff2_X[26]), .B(n7790), .C(
intadd_10_n2), .CO(intadd_10_n1), .S(intadd_10_SUM_2_) );
DFFRX2TS FPADDSUB_INPUT_STAGE_FLAGS_Q_reg_0_ ( .D(n1733), .CK(clk), .RN(
n7974), .Q(FPADDSUB_intAS) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_29_ ( .D(n1469), .CK(clk), .RN(
n2421), .Q(result_add_subt[29]), .QN(n7858) );
DFFRX2TS FPADDSUB_FRMT_STAGE_DATAOUT_Q_reg_30_ ( .D(n1468), .CK(clk), .RN(
n8530), .Q(result_add_subt[30]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_24_ ( .D(n1452), .CK(clk), .RN(n6353),
.Q(FPADDSUB_DMP_SFG[24]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_23_ ( .D(n1458), .CK(clk), .RN(n8549),
.Q(FPADDSUB_DMP_SHT2_EWSW[23]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_23_ ( .D(n1459), .CK(clk), .RN(n8536),
.Q(FPADDSUB_DMP_SHT1_EWSW[23]) );
DFFRXLTS FPADDSUB_SGF_STAGE_DMP_Q_reg_23_ ( .D(n1457), .CK(clk), .RN(n8533),
.Q(FPADDSUB_DMP_SFG[23]) );
DFFRXLTS FPADDSUB_SHT1_STAGE_DMP_Q_reg_24_ ( .D(n1454), .CK(clk), .RN(n8533),
.Q(FPADDSUB_DMP_SHT1_EWSW[24]) );
DFFRXLTS FPADDSUB_SHT2_STAGE_DMP_Q_reg_24_ ( .D(n1453), .CK(clk), .RN(n6354),
.Q(FPADDSUB_DMP_SHT2_EWSW[24]) );
ADDHXLTS U2219 ( .A(add_x_246_A_5_), .B(n5796), .CO(n7783), .S(n7784) );
NAND2X1TS U2220 ( .A(n5669), .B(n5668), .Y(DP_OP_499J2_125_1651_n3) );
NOR2X1TS U2221 ( .A(n6833), .B(n8713), .Y(n8749) );
OR2X2TS U2222 ( .A(n8291), .B(n1333), .Y(n8292) );
INVX2TS U2223 ( .A(n7409), .Y(n7443) );
INVX2TS U2224 ( .A(n7409), .Y(n7427) );
INVX2TS U2225 ( .A(n7409), .Y(n7407) );
INVX2TS U2226 ( .A(n7337), .Y(n7333) );
INVX2TS U2227 ( .A(n7409), .Y(n7357) );
INVX2TS U2228 ( .A(n8611), .Y(n7412) );
INVX2TS U2229 ( .A(n7441), .Y(n7442) );
INVX2TS U2230 ( .A(n7488), .Y(n7482) );
INVX2TS U2231 ( .A(n7488), .Y(n7484) );
INVX2TS U2232 ( .A(n2407), .Y(n2408) );
BUFX3TS U2233 ( .A(n7385), .Y(n7396) );
BUFX3TS U2234 ( .A(n7385), .Y(n7404) );
BUFX3TS U2235 ( .A(n7374), .Y(n7429) );
INVX2TS U2236 ( .A(n6859), .Y(n8525) );
BUFX3TS U2237 ( .A(n8835), .Y(n7655) );
NOR2X1TS U2238 ( .A(n6833), .B(n7435), .Y(n8748) );
NOR2X1TS U2239 ( .A(n7435), .B(n6858), .Y(n8746) );
BUFX3TS U2240 ( .A(n6863), .Y(n8610) );
BUFX3TS U2241 ( .A(n6863), .Y(n7633) );
INVX2TS U2242 ( .A(n5691), .Y(n5693) );
BUFX3TS U2243 ( .A(n8835), .Y(n7637) );
NOR2X1TS U2244 ( .A(n5717), .B(n5716), .Y(n5724) );
NAND2X2TS U2245 ( .A(n3127), .B(n5747), .Y(n5748) );
AOI222X1TS U2246 ( .A0(n6829), .A1(cordic_result[1]), .B0(n6824), .B1(
FPSENCOS_d_ff_Yn[1]), .C0(n6721), .C1(FPSENCOS_d_ff_Xn[1]), .Y(n6825)
);
AOI222X1TS U2247 ( .A0(n6829), .A1(cordic_result[0]), .B0(n6824), .B1(
FPSENCOS_d_ff_Yn[0]), .C0(n6728), .C1(FPSENCOS_d_ff_Xn[0]), .Y(n6818)
);
AOI222X1TS U2248 ( .A0(n6829), .A1(cordic_result[2]), .B0(n6824), .B1(
FPSENCOS_d_ff_Yn[2]), .C0(n6728), .C1(FPSENCOS_d_ff_Xn[2]), .Y(n6830)
);
AOI222X1TS U2249 ( .A0(n6794), .A1(cordic_result[22]), .B0(n6793), .B1(
FPSENCOS_d_ff_Yn[22]), .C0(n6796), .C1(FPSENCOS_d_ff_Xn[22]), .Y(n6782) );
AOI222X1TS U2250 ( .A0(n6794), .A1(cordic_result[28]), .B0(n6793), .B1(
FPSENCOS_d_ff_Yn[28]), .C0(n6796), .C1(FPSENCOS_d_ff_Xn[28]), .Y(n6784) );
AOI222X1TS U2251 ( .A0(n6794), .A1(cordic_result[24]), .B0(n6793), .B1(
FPSENCOS_d_ff_Yn[24]), .C0(n6796), .C1(FPSENCOS_d_ff_Xn[24]), .Y(n6786) );
AOI222X1TS U2252 ( .A0(n6827), .A1(cordic_result[6]), .B0(n6723), .B1(
FPSENCOS_d_ff_Yn[6]), .C0(n6721), .C1(FPSENCOS_d_ff_Xn[6]), .Y(n6828)
);
AOI222X1TS U2253 ( .A0(n6827), .A1(cordic_result[3]), .B0(n6723), .B1(
FPSENCOS_d_ff_Yn[3]), .C0(n6721), .C1(FPSENCOS_d_ff_Xn[3]), .Y(n6823)
);
AOI222X1TS U2254 ( .A0(n6827), .A1(cordic_result[7]), .B0(n6723), .B1(
FPSENCOS_d_ff_Yn[7]), .C0(n6721), .C1(FPSENCOS_d_ff_Xn[7]), .Y(n6826)
);
AOI222X1TS U2255 ( .A0(n6827), .A1(cordic_result[5]), .B0(n6723), .B1(
FPSENCOS_d_ff_Yn[5]), .C0(n6728), .C1(FPSENCOS_d_ff_Xn[5]), .Y(n6822)
);
AOI222X1TS U2256 ( .A0(n6802), .A1(cordic_result[21]), .B0(n6801), .B1(
FPSENCOS_d_ff_Yn[21]), .C0(n6796), .C1(FPSENCOS_d_ff_Xn[21]), .Y(n6779) );
AOI222X1TS U2257 ( .A0(n6802), .A1(cordic_result[20]), .B0(n6801), .B1(
FPSENCOS_d_ff_Yn[20]), .C0(n6796), .C1(FPSENCOS_d_ff_Xn[20]), .Y(n6797) );
AOI222X1TS U2258 ( .A0(n6827), .A1(cordic_result[4]), .B0(n6824), .B1(
FPSENCOS_d_ff_Yn[4]), .C0(n6728), .C1(FPSENCOS_d_ff_Xn[4]), .Y(n6819)
);
AOI222X1TS U2259 ( .A0(n6827), .A1(cordic_result[8]), .B0(n6824), .B1(
FPSENCOS_d_ff_Yn[8]), .C0(n6728), .C1(FPSENCOS_d_ff_Xn[8]), .Y(n6821)
);
AOI222X1TS U2260 ( .A0(n6827), .A1(cordic_result[9]), .B0(n6824), .B1(
FPSENCOS_d_ff_Yn[9]), .C0(n6728), .C1(FPSENCOS_d_ff_Xn[9]), .Y(n6820)
);
INVX2TS U2261 ( .A(n6778), .Y(n6800) );
CLKBUFX3TS U2262 ( .A(n6734), .Y(n6753) );
INVX2TS U2263 ( .A(n6996), .Y(n7031) );
ADDHXLTS U2264 ( .A(add_x_246_A_3_), .B(n5797), .CO(n5795), .S(n7782) );
INVX2TS U2265 ( .A(n6859), .Y(n8524) );
NOR2X4TS U2266 ( .A(n5003), .B(n5002), .Y(add_x_69_n201) );
NAND2X2TS U2267 ( .A(n5641), .B(n5640), .Y(n5647) );
NAND2X1TS U2268 ( .A(n6215), .B(n6214), .Y(n6216) );
BUFX3TS U2269 ( .A(n7308), .Y(n7334) );
BUFX3TS U2270 ( .A(n7385), .Y(n7433) );
BUFX3TS U2271 ( .A(n7634), .Y(n7661) );
INVX2TS U2272 ( .A(n6989), .Y(n7598) );
CLKBUFX2TS U2273 ( .A(n7343), .Y(n7345) );
BUFX3TS U2274 ( .A(n7437), .Y(n7441) );
INVX2TS U2275 ( .A(n7425), .Y(n2407) );
INVX2TS U2276 ( .A(n7508), .Y(n7061) );
CLKBUFX2TS U2277 ( .A(n7634), .Y(n7665) );
INVX2TS U2278 ( .A(n5740), .Y(n3122) );
CLKBUFX2TS U2279 ( .A(n7486), .Y(n7488) );
BUFX3TS U2280 ( .A(n7364), .Y(n7409) );
BUFX3TS U2281 ( .A(n6623), .Y(n7294) );
BUFX3TS U2282 ( .A(n6624), .Y(n6714) );
BUFX3TS U2283 ( .A(n6623), .Y(n6715) );
CLKBUFX2TS U2284 ( .A(n6623), .Y(n7299) );
INVX2TS U2285 ( .A(n6840), .Y(n6641) );
INVX2TS U2286 ( .A(n6840), .Y(n6576) );
INVX6TS U2287 ( .A(n3184), .Y(n5743) );
INVX2TS U2288 ( .A(n6264), .Y(n6857) );
INVX2TS U2289 ( .A(FPADDSUB_Shift_reg_FLAGS_7_5), .Y(n7634) );
OR3X1TS U2290 ( .A(n1519), .B(n1518), .C(n1517), .Y(n5797) );
INVX2TS U2291 ( .A(n5730), .Y(n5753) );
NAND2X1TS U2292 ( .A(n5532), .B(n5526), .Y(n5490) );
AOI211X2TS U2293 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[0]), .A1(n8526), .B0(
n7093), .C0(n6838), .Y(n6858) );
OR3X2TS U2294 ( .A(FPSENCOS_cont_var_out[1]), .B(FPSENCOS_cont_var_out[0]),
.C(n7800), .Y(n7340) );
NAND2X1TS U2295 ( .A(n7084), .B(n7052), .Y(n6996) );
INVX2TS U2296 ( .A(n6721), .Y(n6778) );
CLKBUFX2TS U2297 ( .A(n6736), .Y(n6734) );
BUFX3TS U2298 ( .A(n6989), .Y(n7508) );
BUFX3TS U2299 ( .A(n6864), .Y(n7654) );
INVX2TS U2300 ( .A(add_x_69_n59), .Y(n5736) );
NAND2X6TS U2301 ( .A(n2522), .B(n2590), .Y(n5547) );
NOR2X1TS U2302 ( .A(n6647), .B(n7372), .Y(n6188) );
OAI2BB1X1TS U2303 ( .A0N(n2199), .A1N(n6613), .B0(n8517), .Y(n6892) );
AND2X2TS U2304 ( .A(n6602), .B(n6166), .Y(n7827) );
NAND2X2TS U2305 ( .A(n2670), .B(n2818), .Y(n2669) );
CLKBUFX2TS U2306 ( .A(n7408), .Y(n6759) );
BUFX3TS U2307 ( .A(n6730), .Y(n7425) );
BUFX3TS U2308 ( .A(n7426), .Y(n7413) );
NOR2X4TS U2309 ( .A(operation[1]), .B(n7372), .Y(n7385) );
OR4X2TS U2310 ( .A(n7489), .B(FPMULT_Exp_module_Overflow_flag_A), .C(
FPMULT_exp_oper_result[8]), .D(underflow_flag_mult), .Y(n7486) );
BUFX3TS U2311 ( .A(n6624), .Y(n7293) );
INVX2TS U2312 ( .A(n6264), .Y(n6838) );
NOR2XLTS U2313 ( .A(n6263), .B(n5453), .Y(n5454) );
INVX2TS U2314 ( .A(n7487), .Y(n7489) );
CLKINVX6TS U2315 ( .A(n5763), .Y(n5750) );
INVX2TS U2316 ( .A(n6840), .Y(n6882) );
INVX4TS U2317 ( .A(n5685), .Y(n2590) );
NAND4BBX1TS U2318 ( .AN(n6033), .BN(n6032), .C(n6031), .D(n6030), .Y(n6034)
);
NOR2BX2TS U2319 ( .AN(n6722), .B(n6829), .Y(n6723) );
INVX4TS U2320 ( .A(n2905), .Y(n5671) );
BUFX3TS U2321 ( .A(n6869), .Y(n7372) );
NOR2X4TS U2322 ( .A(n7855), .B(n7629), .Y(n6989) );
AOI2BB2X1TS U2323 ( .B0(n5902), .B1(n6031), .A0N(n5901), .A1N(n5900), .Y(
n6037) );
INVX2TS U2324 ( .A(n6730), .Y(n7408) );
INVX2TS U2325 ( .A(operation[1]), .Y(n6647) );
OAI2BB2XLTS U2326 ( .B0(n7577), .B1(n6025), .A0N(gt_x_74_A_23_), .A1N(n6024),
.Y(n6026) );
INVX2TS U2327 ( .A(n6211), .Y(n2671) );
NAND3X1TS U2328 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .B(n6645),
.C(n7792), .Y(n7282) );
NAND2X6TS U2329 ( .A(n4998), .B(n4999), .Y(n5670) );
BUFX3TS U2330 ( .A(n6832), .Y(n6840) );
OAI222X1TS U2331 ( .A0(n2222), .A1(n8032), .B0(n8112), .B1(n8056), .C0(n8002), .C1(n2215), .Y(n7501) );
XNOR2X1TS U2332 ( .A(n5607), .B(n5606), .Y(n5639) );
BUFX3TS U2333 ( .A(n6581), .Y(n7301) );
NOR2X4TS U2334 ( .A(operation[1]), .B(n7287), .Y(n6624) );
CLKINVX3TS U2335 ( .A(n5759), .Y(n3125) );
INVX2TS U2336 ( .A(n6283), .Y(n6264) );
NAND2X4TS U2337 ( .A(n3029), .B(n2640), .Y(n3027) );
NAND2X2TS U2338 ( .A(n7243), .B(n6212), .Y(n2672) );
NAND2X2TS U2339 ( .A(n6731), .B(n7426), .Y(n6730) );
NAND2X2TS U2340 ( .A(n6854), .B(n6585), .Y(n6869) );
CLKBUFX2TS U2341 ( .A(n7485), .Y(n7487) );
BUFX3TS U2342 ( .A(n6829), .Y(n6794) );
INVX2TS U2343 ( .A(n5561), .Y(n5595) );
INVX6TS U2344 ( .A(n3029), .Y(n2602) );
NOR2X1TS U2345 ( .A(n5899), .B(n7403), .Y(n5900) );
NAND4X1TS U2346 ( .A(n7809), .B(n2360), .C(n7790), .D(intadd_9_B_1_), .Y(
n6731) );
AND2X2TS U2347 ( .A(n6618), .B(FPMULT_FS_Module_state_reg[3]), .Y(n7485) );
XNOR2X1TS U2348 ( .A(DP_OP_26J2_126_1325_n1), .B(FPADDSUB_ADD_OVRFLW_NRM2),
.Y(n6806) );
NOR2X4TS U2349 ( .A(n7300), .B(n6719), .Y(n6829) );
NAND2X6TS U2350 ( .A(n2568), .B(n5726), .Y(n2567) );
INVX2TS U2351 ( .A(operation[2]), .Y(n7287) );
AO22X1TS U2352 ( .A0(operation[1]), .A1(n6039), .B0(begin_operation), .B1(
n7297), .Y(n6585) );
OR2X2TS U2353 ( .A(n6699), .B(FPADDSUB_ADD_OVRFLW_NRM), .Y(n6832) );
AOI211X1TS U2354 ( .A0(n7816), .A1(n6057), .B0(FPADDSUB_Raw_mant_NRM_SWR[5]),
.C0(n6669), .Y(n6058) );
NOR2X1TS U2355 ( .A(FPMULT_FS_Module_state_reg[3]), .B(n2350), .Y(n5708) );
INVX4TS U2356 ( .A(n5326), .Y(n2506) );
OA22X1TS U2357 ( .A0(n5996), .A1(n7393), .B0(n6024), .B1(gt_x_74_A_23_), .Y(
n6029) );
NOR2X1TS U2358 ( .A(n7302), .B(n6439), .Y(n6719) );
NAND2XLTS U2359 ( .A(n7286), .B(n7285), .Y(n6039) );
NOR3X1TS U2360 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(n7813),
.C(n6646), .Y(n6190) );
NOR2X4TS U2361 ( .A(n5482), .B(n5481), .Y(n6248) );
NAND2X6TS U2362 ( .A(n5726), .B(n5725), .Y(n3029) );
NOR2X1TS U2363 ( .A(n5898), .B(n7401), .Y(n5895) );
NAND2X2TS U2364 ( .A(n5150), .B(n5149), .Y(n7240) );
OAI222X1TS U2365 ( .A0(n2219), .A1(n8030), .B0(n8106), .B1(n8056), .C0(n8008), .C1(n2214), .Y(n6435) );
NAND3BX1TS U2366 ( .AN(n6547), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]),
.C(n6546), .Y(n6548) );
BUFX3TS U2367 ( .A(n6581), .Y(n6699) );
OR2X6TS U2368 ( .A(n2980), .B(n4896), .Y(n5726) );
NAND2X4TS U2369 ( .A(n2980), .B(n4896), .Y(n5725) );
INVX2TS U2370 ( .A(n2286), .Y(n5483) );
NOR3X1TS U2371 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .Y(n6546) );
BUFX3TS U2372 ( .A(n3179), .Y(n7196) );
CLKBUFX2TS U2373 ( .A(n5774), .Y(n2380) );
NAND3X1TS U2374 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .B(n5813),
.C(n5815), .Y(n6718) );
NOR2X2TS U2375 ( .A(n7794), .B(FPMULT_FS_Module_state_reg[2]), .Y(n6602) );
NOR2X1TS U2376 ( .A(n6016), .B(n7388), .Y(n6014) );
OAI21X1TS U2377 ( .A0(n4900), .A1(n4899), .B0(n4897), .Y(n4898) );
INVX2TS U2378 ( .A(n2359), .Y(n6581) );
NAND2X2TS U2379 ( .A(n2984), .B(n5539), .Y(n2652) );
OAI21X2TS U2380 ( .A0(n7231), .A1(n7228), .B0(n7232), .Y(n5147) );
NAND2BX2TS U2381 ( .AN(n5721), .B(n5444), .Y(n2504) );
CLKBUFX2TS U2382 ( .A(n6494), .Y(n6606) );
NOR2X1TS U2383 ( .A(n5878), .B(n7397), .Y(n6032) );
NOR2X2TS U2384 ( .A(n7229), .B(n7231), .Y(n5148) );
NAND3X1TS U2385 ( .A(FPSENCOS_cont_iter_out[1]), .B(n7303), .C(n6632), .Y(
n6439) );
NAND2BX1TS U2386 ( .AN(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .B(n6189),
.Y(n6646) );
OR2X6TS U2387 ( .A(n4894), .B(n4895), .Y(n2282) );
AND2X6TS U2388 ( .A(n4899), .B(n2301), .Y(n7231) );
NAND2X1TS U2389 ( .A(n5138), .B(n5137), .Y(n7219) );
NAND2X1TS U2390 ( .A(n2736), .B(n5460), .Y(n2733) );
BUFX3TS U2391 ( .A(n5059), .Y(n5149) );
INVX2TS U2392 ( .A(n5721), .Y(n5443) );
NAND2X1TS U2393 ( .A(n7214), .B(n5136), .Y(n7221) );
OAI2BB2XLTS U2394 ( .B0(n7617), .B1(n5933), .A0N(n7369), .A1N(n5932), .Y(
n5939) );
NAND2X2TS U2395 ( .A(n5428), .B(n5427), .Y(n5564) );
CLKBUFX2TS U2396 ( .A(n6202), .Y(n6609) );
NAND2X1TS U2397 ( .A(n6507), .B(n6905), .Y(n5769) );
INVX2TS U2398 ( .A(n7379), .Y(n5914) );
INVX2TS U2399 ( .A(n3133), .Y(n5444) );
OR2X4TS U2400 ( .A(n4899), .B(n2301), .Y(n7232) );
NAND2X2TS U2401 ( .A(n3189), .B(n5460), .Y(n5462) );
NOR2BX1TS U2402 ( .AN(n6038), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]),
.Y(n6645) );
OAI21X1TS U2403 ( .A0(n5358), .A1(n5373), .B0(n5375), .Y(n5363) );
INVX2TS U2404 ( .A(n2358), .Y(n2359) );
INVX2TS U2405 ( .A(n5354), .Y(n2988) );
CMPR32X2TS U2406 ( .A(n6976), .B(n6984), .C(n6975), .CO(n6972), .S(n7094) );
INVX2TS U2407 ( .A(n5353), .Y(n2989) );
NOR2X1TS U2408 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .B(n6547),
.Y(n6038) );
INVX4TS U2409 ( .A(n2793), .Y(n5303) );
NOR2X1TS U2410 ( .A(n5376), .B(n5373), .Y(n5379) );
CLKINVX2TS U2411 ( .A(n3120), .Y(n3082) );
NAND3X4TS U2412 ( .A(n2897), .B(n2889), .C(n5331), .Y(n2896) );
NAND2X6TS U2413 ( .A(n2897), .B(n5330), .Y(n2895) );
NAND2BX2TS U2414 ( .AN(n5329), .B(n5327), .Y(n2690) );
NAND2X2TS U2415 ( .A(n2235), .B(n5328), .Y(n5294) );
AND2X2TS U2416 ( .A(n5766), .B(n2350), .Y(n6507) );
NAND2BX2TS U2417 ( .AN(n5816), .B(n6189), .Y(n7302) );
XNOR2X1TS U2418 ( .A(n5141), .B(n5140), .Y(n5146) );
INVX2TS U2419 ( .A(n6988), .Y(n2358) );
CLKBUFX2TS U2420 ( .A(n8074), .Y(n7447) );
INVX2TS U2421 ( .A(n4899), .Y(n2642) );
NAND2X1TS U2422 ( .A(n5314), .B(n5313), .Y(n5315) );
NOR2BX2TS U2423 ( .AN(n5815), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]),
.Y(n6189) );
INVX3TS U2424 ( .A(n2280), .Y(n2890) );
NAND2X4TS U2425 ( .A(n3130), .B(n3129), .Y(n4900) );
AOI21X2TS U2426 ( .A0(n3135), .A1(n5311), .B0(n5310), .Y(n5316) );
BUFX3TS U2427 ( .A(FPADDSUB_Shift_reg_FLAGS_7[1]), .Y(n6988) );
NOR2BX1TS U2428 ( .AN(n6358), .B(n6263), .Y(n5767) );
NAND2X4TS U2429 ( .A(n5271), .B(n5270), .Y(n5327) );
INVX2TS U2430 ( .A(n4684), .Y(n3026) );
NAND2X2TS U2431 ( .A(n5235), .B(n5234), .Y(n5320) );
INVX2TS U2432 ( .A(n5197), .Y(n5318) );
NAND2X1TS U2433 ( .A(n5062), .B(n5061), .Y(n5064) );
NAND2X6TS U2434 ( .A(n2951), .B(n3117), .Y(n5330) );
NOR2X6TS U2435 ( .A(n5384), .B(n5464), .Y(n2833) );
INVX4TS U2436 ( .A(n2702), .Y(n2235) );
NOR2X1TS U2437 ( .A(n6307), .B(n6319), .Y(n6219) );
NOR2X1TS U2438 ( .A(n5278), .B(n5279), .Y(n5288) );
NAND2X1TS U2439 ( .A(n5279), .B(n5278), .Y(n5287) );
NAND3X2TS U2440 ( .A(n4946), .B(n4945), .C(n5234), .Y(n3117) );
INVX1TS U2441 ( .A(n2229), .Y(n2257) );
NOR2X4TS U2442 ( .A(n5317), .B(n5197), .Y(n2581) );
NOR2X1TS U2443 ( .A(n5396), .B(n5399), .Y(n5554) );
NAND2X4TS U2444 ( .A(n2982), .B(n5491), .Y(n2572) );
NAND2X1TS U2445 ( .A(n5934), .B(n8284), .Y(n5992) );
NAND2X2TS U2446 ( .A(n2233), .B(n5010), .Y(n2676) );
BUFX3TS U2447 ( .A(n2256), .Y(n5998) );
NOR2X2TS U2448 ( .A(n6064), .B(n2489), .Y(n6059) );
INVX2TS U2449 ( .A(n2260), .Y(n2203) );
AO21X1TS U2450 ( .A0(n5338), .A1(n2237), .B0(n2511), .Y(n5423) );
INVX2TS U2451 ( .A(n5137), .Y(n4682) );
CLKBUFX2TS U2452 ( .A(FPADDSUB_Raw_mant_NRM_SWR[11]), .Y(n2489) );
NAND2X4TS U2453 ( .A(n4885), .B(n4884), .Y(n5491) );
NAND2X4TS U2454 ( .A(n2524), .B(n3070), .Y(n2501) );
NAND2BX2TS U2455 ( .AN(n5339), .B(n5262), .Y(n5422) );
BUFX4TS U2456 ( .A(n2256), .Y(n6872) );
NAND2X2TS U2457 ( .A(n5051), .B(n5094), .Y(n5052) );
INVX3TS U2458 ( .A(n5283), .Y(n3102) );
INVX6TS U2459 ( .A(n2619), .Y(n5317) );
XNOR2X2TS U2460 ( .A(n5369), .B(n5368), .Y(n5466) );
INVX3TS U2461 ( .A(n5008), .Y(n2233) );
INVX6TS U2462 ( .A(n5092), .Y(n5051) );
CLKINVX2TS U2463 ( .A(n5011), .Y(n4993) );
NOR2X4TS U2464 ( .A(n3089), .B(n2745), .Y(n2744) );
NAND2X4TS U2465 ( .A(n3016), .B(n4636), .Y(n3019) );
INVX3TS U2466 ( .A(n5718), .Y(n2503) );
XNOR2X1TS U2467 ( .A(n5570), .B(n5345), .Y(n5417) );
INVX4TS U2468 ( .A(n4996), .Y(n5311) );
CLKXOR2X4TS U2469 ( .A(n2329), .B(n3720), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[13]) );
OAI2BB1X2TS U2470 ( .A0N(n5193), .A1N(n5192), .B0(n2648), .Y(n5215) );
NAND2X4TS U2471 ( .A(n3689), .B(n3688), .Y(n5309) );
NAND2X4TS U2472 ( .A(n2588), .B(n4905), .Y(n2526) );
ADDHX1TS U2473 ( .A(FPMULT_Sgf_normalized_result[6]), .B(add_x_246_n19),
.CO(n6937), .S(n6940) );
ADDFX2TS U2474 ( .A(n5349), .B(n5348), .CI(n5347), .CO(n5413), .S(n5337) );
NOR2X4TS U2475 ( .A(n2263), .B(n5050), .Y(n5092) );
NAND2X4TS U2476 ( .A(n4086), .B(n4085), .Y(n4905) );
NOR2X1TS U2477 ( .A(n5114), .B(n5111), .Y(n5117) );
NAND2X4TS U2478 ( .A(n4571), .B(n4570), .Y(n5010) );
CLKXOR2X2TS U2479 ( .A(n5339), .B(n5262), .Y(n5342) );
NOR2X1TS U2480 ( .A(n3703), .B(n3700), .Y(n3706) );
NAND2X4TS U2481 ( .A(n2695), .B(n4645), .Y(n2588) );
OAI22X2TS U2482 ( .A0(n5199), .A1(n5338), .B0(n5251), .B1(n2237), .Y(n5247)
);
OAI22X2TS U2483 ( .A0(n2231), .A1(n5261), .B0(n5346), .B1(n5416), .Y(n5343)
);
NAND2X6TS U2484 ( .A(n3095), .B(n3516), .Y(n2791) );
NAND2X6TS U2485 ( .A(n3096), .B(n3095), .Y(n2792) );
NAND3X6TS U2486 ( .A(n3016), .B(n4523), .C(n4636), .Y(n2610) );
NAND2X1TS U2487 ( .A(n5254), .B(n5262), .Y(n4638) );
OR2X6TS U2488 ( .A(n2605), .B(n4475), .Y(n4636) );
AND2X6TS U2489 ( .A(n2559), .B(n2558), .Y(n2328) );
NAND2X1TS U2490 ( .A(n4855), .B(n4618), .Y(n4620) );
OAI22X2TS U2491 ( .A0(n5173), .A1(n5338), .B0(n5199), .B1(n2376), .Y(n5214)
);
OR2X4TS U2492 ( .A(n2318), .B(n3740), .Y(n2968) );
NAND2X2TS U2493 ( .A(n3672), .B(n3671), .Y(n3693) );
NAND2X6TS U2494 ( .A(n2262), .B(n5050), .Y(n5094) );
XNOR2X2TS U2495 ( .A(n5340), .B(n5345), .Y(n5261) );
INVX2TS U2496 ( .A(n4635), .Y(n2612) );
INVX2TS U2497 ( .A(n5181), .Y(n5223) );
INVX2TS U2498 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[10]), .Y(n4872) );
INVX6TS U2499 ( .A(n5066), .Y(n5105) );
NOR2X1TS U2500 ( .A(n5180), .B(n2354), .Y(n5224) );
NAND2X1TS U2501 ( .A(n3191), .B(n4847), .Y(n4849) );
NOR2X4TS U2502 ( .A(n3672), .B(n3671), .Y(n3694) );
INVX3TS U2503 ( .A(n3692), .Y(n3660) );
INVX4TS U2504 ( .A(n2972), .Y(n2970) );
NAND2X6TS U2505 ( .A(n2731), .B(n2689), .Y(n2589) );
CLKXOR2X4TS U2506 ( .A(n4697), .B(n4696), .Y(n4866) );
NAND2X1TS U2507 ( .A(n5204), .B(n5203), .Y(n4666) );
NAND2BX1TS U2508 ( .AN(n4616), .B(n4920), .Y(n2704) );
INVX6TS U2509 ( .A(n4652), .Y(n2689) );
NAND2X1TS U2510 ( .A(n3735), .B(n3734), .Y(n3736) );
NAND2X1TS U2511 ( .A(n4688), .B(n4687), .Y(n4690) );
NAND2X2TS U2512 ( .A(n2753), .B(n3722), .Y(n3723) );
XNOR2X2TS U2513 ( .A(n5198), .B(n5340), .Y(n5173) );
OAI21X1TS U2514 ( .A0(n3488), .A1(n3088), .B0(n3485), .Y(n2732) );
OAI22X1TS U2515 ( .A0(n2644), .A1(n2240), .B0(n4625), .B1(n4633), .Y(n4631)
);
XOR2X2TS U2516 ( .A(n4756), .B(n4755), .Y(n7209) );
NAND2X4TS U2517 ( .A(n4076), .B(n4075), .Y(n4657) );
INVX4TS U2518 ( .A(n3093), .Y(n2234) );
NOR2X1TS U2519 ( .A(n4917), .B(n2353), .Y(n5168) );
NAND2X2TS U2520 ( .A(n5079), .B(n5078), .Y(n5098) );
INVX6TS U2521 ( .A(n2998), .Y(n2726) );
NAND2X4TS U2522 ( .A(n3620), .B(n3619), .Y(n3631) );
NAND2BX2TS U2523 ( .AN(n4524), .B(n4527), .Y(n4471) );
AOI21X2TS U2524 ( .A0(n4763), .A1(n4760), .B0(n4752), .Y(n4756) );
OR2X4TS U2525 ( .A(n2236), .B(n3095), .Y(n3092) );
OR2X6TS U2526 ( .A(n4076), .B(n4075), .Y(n4658) );
INVX2TS U2527 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[7]), .Y(n4825) );
INVX2TS U2528 ( .A(n2279), .Y(n2703) );
INVX4TS U2529 ( .A(n4751), .Y(n4763) );
NAND2X1TS U2530 ( .A(n3485), .B(n3733), .Y(n3292) );
NAND2X2TS U2531 ( .A(n4813), .B(n4812), .Y(n5005) );
OAI22X2TS U2532 ( .A0(n4095), .A1(n4093), .B0(n3939), .B1(n4094), .Y(n4090)
);
NOR2X4TS U2533 ( .A(n3560), .B(n3559), .Y(n3093) );
NOR2X2TS U2534 ( .A(n4939), .B(n5212), .Y(n5178) );
NAND2X2TS U2535 ( .A(n2321), .B(n4469), .Y(n2573) );
XNOR2X2TS U2536 ( .A(n5205), .B(n5345), .Y(n5169) );
CLKINVX2TS U2537 ( .A(n3662), .Y(n2877) );
INVX2TS U2538 ( .A(n7207), .Y(n4746) );
INVX6TS U2539 ( .A(n2807), .Y(n4983) );
NOR2X1TS U2540 ( .A(n4829), .B(n4827), .Y(n4587) );
OAI22X1TS U2541 ( .A0(n4941), .A1(n5209), .B0(n4116), .B1(n5210), .Y(n4932)
);
NOR2X6TS U2542 ( .A(n3518), .B(n3517), .Y(n3717) );
NAND2X1TS U2543 ( .A(n3628), .B(n3627), .Y(n3682) );
OR2X6TS U2544 ( .A(n4043), .B(n4042), .Y(n3191) );
INVX2TS U2545 ( .A(n5360), .Y(n3986) );
NOR2X4TS U2546 ( .A(n4586), .B(n4585), .Y(n4829) );
NOR2X1TS U2547 ( .A(n3867), .B(n5212), .Y(n4118) );
NOR2X1TS U2548 ( .A(n4119), .B(n5212), .Y(n4937) );
INVX2TS U2549 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[6]), .Y(n4819) );
NAND2X1TS U2550 ( .A(n4805), .B(n4804), .Y(n4807) );
NAND2X2TS U2551 ( .A(n4799), .B(n4798), .Y(n5055) );
INVX2TS U2552 ( .A(n4701), .Y(n4201) );
OR2X4TS U2553 ( .A(n2981), .B(n2312), .Y(n3722) );
INVX4TS U2554 ( .A(n4524), .Y(n2788) );
NAND2X2TS U2555 ( .A(n4267), .B(n4266), .Y(n4761) );
OAI22X2TS U2556 ( .A0(n4633), .A1(n4613), .B0(n4625), .B1(n2644), .Y(n4630)
);
XNOR2X2TS U2557 ( .A(n4938), .B(n4940), .Y(n4116) );
XNOR2X2TS U2558 ( .A(n4319), .B(n4318), .Y(n4320) );
NAND2X1TS U2559 ( .A(n4566), .B(n4565), .Y(n4987) );
INVX2TS U2560 ( .A(n5359), .Y(n3943) );
OAI2BB1X1TS U2561 ( .A0N(n5021), .A1N(n5022), .B0(n2852), .Y(n5069) );
OAI2BB1X2TS U2562 ( .A0N(n4046), .A1N(n2698), .B0(n2696), .Y(n4074) );
NAND2X6TS U2563 ( .A(n3553), .B(n3554), .Y(n3589) );
NAND2X6TS U2564 ( .A(n4468), .B(n4467), .Y(n4527) );
NAND2X6TS U2565 ( .A(n3591), .B(n3590), .Y(n2587) );
INVX6TS U2566 ( .A(n2795), .Y(n2627) );
NAND2X1TS U2567 ( .A(n3557), .B(n3556), .Y(n3626) );
INVX4TS U2568 ( .A(n7206), .Y(n4820) );
AO21X2TS U2569 ( .A0(n4600), .A1(n2243), .B0(n4599), .Y(n4611) );
NAND2X1TS U2570 ( .A(n4473), .B(n4472), .Y(n4567) );
INVX2TS U2571 ( .A(n2284), .Y(n3588) );
NAND2BX1TS U2572 ( .AN(n4108), .B(n5345), .Y(n3966) );
CLKINVX2TS U2573 ( .A(n3737), .Y(n3083) );
CLKXOR2X2TS U2574 ( .A(n2961), .B(n4006), .Y(n4120) );
OAI22X1TS U2575 ( .A0(n4633), .A1(n4601), .B0(n2644), .B1(n4613), .Y(n4610)
);
NAND2X2TS U2576 ( .A(n2948), .B(n3916), .Y(n2946) );
NOR2X1TS U2577 ( .A(n2435), .B(n2299), .Y(n3666) );
BUFX6TS U2578 ( .A(n2623), .Y(n2548) );
INVX2TS U2579 ( .A(n5290), .Y(n3983) );
CMPR32X2TS U2580 ( .A(n5074), .B(n5073), .C(n5072), .CO(n5108), .S(n5076) );
INVX2TS U2581 ( .A(n5002), .Y(n4769) );
INVX2TS U2582 ( .A(n5279), .Y(n4049) );
OR2X2TS U2583 ( .A(n4032), .B(n4031), .Y(n4758) );
OAI21X2TS U2584 ( .A0(n4046), .A1(n2698), .B0(n4045), .Y(n2696) );
NAND2X1TS U2585 ( .A(n2238), .B(n4259), .Y(n4260) );
NOR2X2TS U2586 ( .A(n4582), .B(n4581), .Y(n4803) );
BUFX8TS U2587 ( .A(n2795), .Y(n2749) );
NAND2X2TS U2588 ( .A(n3081), .B(n3499), .Y(n3737) );
OR2X4TS U2589 ( .A(n4200), .B(n4199), .Y(n4702) );
NAND2X6TS U2590 ( .A(n2622), .B(n4376), .Y(n2835) );
OR2X1TS U2591 ( .A(n4780), .B(n4779), .Y(n4781) );
XNOR2X2TS U2592 ( .A(n5252), .B(n4921), .Y(n3960) );
OAI21X2TS U2593 ( .A0(n4977), .A1(n4976), .B0(n4975), .Y(n3109) );
INVX12TS U2594 ( .A(n2513), .Y(n5338) );
NAND2X2TS U2595 ( .A(n4032), .B(n4031), .Y(n4757) );
NAND2X1TS U2596 ( .A(n4027), .B(n3128), .Y(n4699) );
OR2X2TS U2597 ( .A(n3081), .B(n3499), .Y(n3738) );
NOR2BX1TS U2598 ( .AN(n4027), .B(n5212), .Y(n3959) );
INVX2TS U2599 ( .A(n2352), .Y(n2353) );
OAI22X2TS U2600 ( .A0(n4100), .A1(n4600), .B0(n4591), .B1(n2243), .Y(n4590)
);
OR2X2TS U2601 ( .A(n4029), .B(n4028), .Y(n2302) );
CLKXOR2X2TS U2602 ( .A(n4046), .B(n2698), .Y(n2697) );
NAND2X1TS U2603 ( .A(n4548), .B(n4547), .Y(n4368) );
INVX6TS U2604 ( .A(n2781), .Y(n2644) );
AND2X6TS U2605 ( .A(n2376), .B(n2516), .Y(n2513) );
NOR2BX1TS U2606 ( .AN(n4027), .B(n5209), .Y(n4055) );
INVX6TS U2607 ( .A(n2659), .Y(n3183) );
OAI2BB1X2TS U2608 ( .A0N(n4957), .A1N(n3108), .B0(n3106), .Y(n5036) );
OAI22X2TS U2609 ( .A0(n3950), .A1(n4026), .B0(n3978), .B1(n3993), .Y(n4054)
);
NAND2X1TS U2610 ( .A(n4716), .B(n4715), .Y(n4717) );
NAND2XLTS U2611 ( .A(n3505), .B(n3510), .Y(n3513) );
INVX3TS U2612 ( .A(n4365), .Y(n2720) );
INVX6TS U2613 ( .A(n3428), .Y(n2626) );
INVX2TS U2614 ( .A(n3427), .Y(n2625) );
INVX2TS U2615 ( .A(n4604), .Y(n2240) );
NOR2X6TS U2616 ( .A(n4360), .B(n4359), .Y(n2659) );
INVX6TS U2617 ( .A(n2512), .Y(n2376) );
NAND2X2TS U2618 ( .A(n4304), .B(n4303), .Y(n4361) );
NOR2BX2TS U2619 ( .AN(n3570), .B(n3522), .Y(n3600) );
NAND2X2TS U2620 ( .A(n3291), .B(n3290), .Y(n3485) );
NOR2X2TS U2621 ( .A(n3078), .B(n3923), .Y(n2900) );
XNOR2X2TS U2622 ( .A(n4573), .B(n4000), .Y(n4789) );
OAI21X2TS U2623 ( .A0(n4189), .A1(n4710), .B0(n4190), .Y(n4174) );
OAI22X1TS U2624 ( .A0(n2349), .A1(n3606), .B0(n3664), .B1(n3571), .Y(n3599)
);
INVX4TS U2625 ( .A(n3488), .Y(n3086) );
NAND2X4TS U2626 ( .A(n2682), .B(n2681), .Y(n5557) );
XOR2X2TS U2627 ( .A(n2285), .B(n2995), .Y(n3950) );
OR2X6TS U2628 ( .A(n3389), .B(n3388), .Y(n3501) );
CLKINVX6TS U2629 ( .A(n5119), .Y(n2268) );
CLKINVX2TS U2630 ( .A(n4441), .Y(n4507) );
INVX6TS U2631 ( .A(n2990), .Y(n4604) );
INVX4TS U2632 ( .A(n5084), .Y(n4435) );
INVX3TS U2633 ( .A(n4390), .Y(n4436) );
NOR2X4TS U2634 ( .A(n4304), .B(n4303), .Y(n4363) );
NAND2X2TS U2635 ( .A(n4441), .B(n4449), .Y(n4257) );
NAND2X2TS U2636 ( .A(n4417), .B(n4390), .Y(n4190) );
NAND2X6TS U2637 ( .A(n3788), .B(n4626), .Y(n4627) );
INVX4TS U2638 ( .A(n3907), .Y(n5167) );
INVX2TS U2639 ( .A(n3733), .Y(n3088) );
OAI22X2TS U2640 ( .A0(n4536), .A1(n4491), .B0(n5030), .B1(n4440), .Y(n4508)
);
NAND2X2TS U2641 ( .A(n4572), .B(n3999), .Y(n4574) );
BUFX8TS U2642 ( .A(n3883), .Y(n3965) );
XOR2X2TS U2643 ( .A(n4251), .B(n4554), .Y(n2528) );
NAND2X2TS U2644 ( .A(n3997), .B(n3996), .Y(n4780) );
INVX3TS U2645 ( .A(n3078), .Y(n3007) );
OAI22X2TS U2646 ( .A0(n3996), .A1(n2382), .B0(n3995), .B1(n4024), .Y(n4779)
);
NOR2X2TS U2647 ( .A(n3759), .B(n2306), .Y(n2789) );
XNOR2X1TS U2648 ( .A(n4027), .B(n4006), .Y(n4007) );
CLKXOR2X2TS U2649 ( .A(n3827), .B(n3826), .Y(n2595) );
INVX2TS U2650 ( .A(n3582), .Y(n3609) );
INVX2TS U2651 ( .A(n4417), .Y(n4445) );
INVX2TS U2652 ( .A(n4510), .Y(n3013) );
NOR2X4TS U2653 ( .A(n4323), .B(n4350), .Y(n4709) );
NOR2X4TS U2654 ( .A(n3387), .B(n3386), .Y(n3489) );
NOR2X1TS U2655 ( .A(n5030), .B(n4448), .Y(n4496) );
OAI2BB1X2TS U2656 ( .A0N(n3456), .A1N(n2974), .B0(n2973), .Y(n3532) );
INVX3TS U2657 ( .A(n4548), .Y(n4956) );
NOR2X4TS U2658 ( .A(n3808), .B(n3161), .Y(n2646) );
INVX4TS U2659 ( .A(n3867), .Y(n3951) );
NOR2X4TS U2660 ( .A(n3904), .B(n3110), .Y(n3923) );
BUFX8TS U2661 ( .A(n3798), .Y(n4626) );
INVX6TS U2662 ( .A(n4605), .Y(n2442) );
NOR2X2TS U2663 ( .A(n5030), .B(n4491), .Y(n4534) );
OAI2BB2X2TS U2664 ( .B0(n2433), .B1(n7708), .A0N(n2776), .A1N(n7708), .Y(
n3607) );
XOR2X2TS U2665 ( .A(n3605), .B(n2685), .Y(n5402) );
NOR2X1TS U2666 ( .A(n3763), .B(n3758), .Y(n3756) );
INVX8TS U2667 ( .A(n2957), .Y(n3110) );
INVX8TS U2668 ( .A(n3074), .Y(n4936) );
INVX4TS U2669 ( .A(n4411), .Y(n5070) );
OAI2BB2X1TS U2670 ( .B0(n3393), .B1(n7708), .A0N(n3445), .A1N(n7708), .Y(
n3528) );
NOR2X2TS U2671 ( .A(n3150), .B(n3173), .Y(n4971) );
AOI21X2TS U2672 ( .A0(n3872), .A1(n2966), .B0(n3871), .Y(n2991) );
INVX6TS U2673 ( .A(n2928), .Y(n4027) );
NOR2X2TS U2674 ( .A(n2730), .B(n2539), .Y(n2538) );
CLKXOR2X4TS U2675 ( .A(n2727), .B(n2316), .Y(n4026) );
XOR2X2TS U2676 ( .A(n3836), .B(n3172), .Y(n2618) );
ADDFHX2TS U2677 ( .A(n4487), .B(n4486), .CI(n4485), .CO(n4551), .S(n4488) );
ADDFHX2TS U2678 ( .A(n4338), .B(n4337), .CI(n4336), .CO(n4418), .S(n4357) );
INVX3TS U2679 ( .A(n4323), .Y(n4389) );
NOR2X1TS U2680 ( .A(DP_OP_498J2_124_1725_n722), .B(n4972), .Y(n4968) );
OAI2BB1X2TS U2681 ( .A0N(n3363), .A1N(n2798), .B0(n2797), .Y(n3403) );
NOR2X1TS U2682 ( .A(n4973), .B(n4451), .Y(n4480) );
NAND2X1TS U2683 ( .A(n3845), .B(n3840), .Y(n3833) );
OR2X4TS U2684 ( .A(n3378), .B(n3377), .Y(n3469) );
INVX4TS U2685 ( .A(n2686), .Y(n3826) );
NAND2BXLTS U2686 ( .AN(DP_OP_496J2_122_3540_n778), .B(n2316), .Y(n3076) );
INVX6TS U2687 ( .A(n3421), .Y(n2435) );
NOR2X1TS U2688 ( .A(DP_OP_498J2_124_1725_n722), .B(n4483), .Y(n4487) );
NOR2X4TS U2689 ( .A(n4972), .B(n4450), .Y(n4481) );
AOI21X2TS U2690 ( .A0(n2940), .A1(n3828), .B0(n3830), .Y(n3119) );
OAI21X2TS U2691 ( .A0(n3514), .A1(n2317), .B0(n3473), .Y(n2767) );
XNOR2X2TS U2692 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MY[22]), .Y(n3863) );
OAI21X2TS U2693 ( .A0(n4316), .A1(n2785), .B0(n2786), .Y(n2783) );
NAND2X2TS U2694 ( .A(n3814), .B(n3813), .Y(n3906) );
BUFX6TS U2695 ( .A(n3791), .Y(n2429) );
INVX2TS U2696 ( .A(n3412), .Y(n3429) );
NOR2X1TS U2697 ( .A(n3582), .B(n3573), .Y(n3504) );
BUFX6TS U2698 ( .A(n4549), .Y(n2379) );
BUFX8TS U2699 ( .A(n2851), .Y(n2837) );
NAND2X2TS U2700 ( .A(n3544), .B(n3543), .Y(n2679) );
CLKAND2X2TS U2701 ( .A(n3495), .B(n2918), .Y(n2920) );
NAND2X1TS U2702 ( .A(n2315), .B(n3870), .Y(n3004) );
INVX4TS U2703 ( .A(n4299), .Y(n4970) );
INVX4TS U2704 ( .A(n4218), .Y(n4537) );
OAI21X2TS U2705 ( .A0(n3908), .A1(n3911), .B0(n2727), .Y(n3814) );
NAND2X2TS U2706 ( .A(n3810), .B(n3823), .Y(n3754) );
BUFX16TS U2707 ( .A(n2851), .Y(n4954) );
NOR2X6TS U2708 ( .A(n3781), .B(n3800), .Y(n3818) );
NAND3X2TS U2709 ( .A(n2940), .B(n3884), .C(n3785), .Y(n2963) );
OR2X2TS U2710 ( .A(n4405), .B(n4402), .Y(n4406) );
NAND2X2TS U2711 ( .A(n4734), .B(n4733), .Y(n4739) );
NOR2X2TS U2712 ( .A(n4450), .B(n2275), .Y(n4456) );
NAND2X2TS U2713 ( .A(n3248), .B(n3473), .Y(n3253) );
NAND2X6TS U2714 ( .A(n2884), .B(n2883), .Y(n3708) );
ADDHX2TS U2715 ( .A(n4142), .B(n4141), .CO(n4245), .S(n4138) );
NAND2X2TS U2716 ( .A(n2862), .B(n2867), .Y(n2861) );
ADDFHX2TS U2717 ( .A(n4400), .B(n4399), .CI(n4398), .CO(n4452), .S(n4415) );
NAND2X1TS U2718 ( .A(n3522), .B(n3541), .Y(n3472) );
CLKINVX2TS U2719 ( .A(n3758), .Y(n3037) );
NOR2X1TS U2720 ( .A(n4484), .B(n4451), .Y(n4398) );
NOR2X1TS U2721 ( .A(n4242), .B(DP_OP_498J2_124_1725_n636), .Y(n4143) );
NAND2X1TS U2722 ( .A(n7729), .B(DP_OP_496J2_122_3540_n1103), .Y(n3755) );
INVX2TS U2723 ( .A(n2710), .Y(n2440) );
XOR2X4TS U2724 ( .A(n3794), .B(n3780), .Y(n3800) );
INVX4TS U2725 ( .A(n4276), .Y(n4335) );
INVX4TS U2726 ( .A(n3657), .Y(n2542) );
INVX2TS U2727 ( .A(n3358), .Y(n3423) );
NAND2X2TS U2728 ( .A(n3450), .B(n3449), .Y(n2883) );
NOR2X2TS U2729 ( .A(n4450), .B(n4483), .Y(n4399) );
NAND2BX1TS U2730 ( .AN(DP_OP_498J2_124_1725_n636), .B(n4294), .Y(n4140) );
BUFX3TS U2731 ( .A(n3790), .Y(n3823) );
NAND2X4TS U2732 ( .A(n2727), .B(n3068), .Y(n3067) );
NAND2BX2TS U2733 ( .AN(n2313), .B(n3447), .Y(n3473) );
NAND2X4TS U2734 ( .A(n3136), .B(n3420), .Y(n3421) );
INVX4TS U2735 ( .A(n3786), .Y(n4099) );
NOR2X2TS U2736 ( .A(n4166), .B(n4243), .Y(n4141) );
AND2X4TS U2737 ( .A(n3761), .B(n3762), .Y(n2536) );
ADDHX2TS U2738 ( .A(n4396), .B(n4395), .CO(n4454), .S(n4392) );
OR2X2TS U2739 ( .A(n3496), .B(n2922), .Y(n2918) );
INVX3TS U2740 ( .A(n3782), .Y(n3884) );
CMPR32X2TS U2741 ( .A(n4232), .B(n4231), .C(n4230), .CO(n4289), .S(n4236) );
CMPR32X2TS U2742 ( .A(n3335), .B(n3334), .C(n3333), .CO(n3370), .S(n3284) );
INVX2TS U2743 ( .A(n3321), .Y(n3331) );
XOR2X1TS U2744 ( .A(FPMULT_Op_MY[22]), .B(FPMULT_Op_MY[10]), .Y(n2578) );
NOR2X4TS U2745 ( .A(n3358), .B(n3312), .Y(n3728) );
NOR2X1TS U2746 ( .A(n4450), .B(n4451), .Y(n4351) );
NOR2X6TS U2747 ( .A(n3397), .B(n3412), .Y(n3250) );
INVX4TS U2748 ( .A(n4213), .Y(n2437) );
NOR2BX1TS U2749 ( .AN(DP_OP_496J2_122_3540_n778), .B(n3145), .Y(n3746) );
NOR2X4TS U2750 ( .A(n4972), .B(n4355), .Y(n4396) );
NOR2X2TS U2751 ( .A(n3258), .B(n3257), .Y(n3288) );
NOR2X4TS U2752 ( .A(n4355), .B(n2275), .Y(n4354) );
NOR2BX2TS U2753 ( .AN(n3166), .B(n6893), .Y(n3832) );
NAND2X2TS U2754 ( .A(n7731), .B(DP_OP_496J2_122_3540_n1193), .Y(n3795) );
INVX2TS U2755 ( .A(n3317), .Y(n3606) );
NOR2X2TS U2756 ( .A(n4185), .B(n8489), .Y(n4154) );
NOR2X6TS U2757 ( .A(DP_OP_498J2_124_1725_n722), .B(n4451), .Y(n2867) );
NAND2X1TS U2758 ( .A(n4195), .B(n4194), .Y(n4196) );
NOR2X2TS U2759 ( .A(n4484), .B(n4391), .Y(n4352) );
BUFX4TS U2760 ( .A(n3393), .Y(n2428) );
NOR2X2TS U2761 ( .A(n4242), .B(n4166), .Y(n4153) );
OR2X4TS U2762 ( .A(n3136), .B(n3480), .Y(n2881) );
NOR2X2TS U2763 ( .A(n3480), .B(n3479), .Y(n3496) );
NAND3X6TS U2764 ( .A(n3872), .B(n2966), .C(n3873), .Y(n2959) );
CLKINVX6TS U2765 ( .A(n3447), .Y(n2241) );
OAI2BB1X2TS U2766 ( .A0N(n3400), .A1N(n3401), .B0(n2561), .Y(n3451) );
NAND2X4TS U2767 ( .A(DP_OP_498J2_124_1725_n803), .B(
DP_OP_498J2_124_1725_n790), .Y(n2849) );
INVX6TS U2768 ( .A(n4293), .Y(n2840) );
INVX12TS U2769 ( .A(n3538), .Y(n7454) );
INVX4TS U2770 ( .A(n8519), .Y(n4243) );
OR2X4TS U2771 ( .A(n2771), .B(n2320), .Y(n3318) );
NAND2X2TS U2772 ( .A(n7730), .B(DP_OP_496J2_122_3540_n1114), .Y(n2711) );
INVX8TS U2773 ( .A(n2655), .Y(n2776) );
NOR2X6TS U2774 ( .A(n3116), .B(n3869), .Y(n3872) );
BUFX4TS U2775 ( .A(DP_OP_496J2_122_3540_n1472), .Y(n6860) );
NAND3X4TS U2776 ( .A(n3876), .B(n3877), .C(n3879), .Y(n2728) );
NOR2X1TS U2777 ( .A(n3538), .B(n3166), .Y(n3453) );
NOR2X1TS U2778 ( .A(DP_OP_497J2_123_1725_n716), .B(n3166), .Y(n3352) );
INVX6TS U2779 ( .A(n4213), .Y(n2436) );
OR2X2TS U2780 ( .A(n3321), .B(n3305), .Y(n3204) );
INVX6TS U2781 ( .A(n3760), .Y(n3877) );
INVX2TS U2782 ( .A(n3278), .Y(n3519) );
NOR2X6TS U2783 ( .A(n3355), .B(DP_OP_497J2_123_1725_n716), .Y(n3556) );
NOR2X2TS U2784 ( .A(n3174), .B(n2226), .Y(n3353) );
NOR2X2TS U2785 ( .A(n4450), .B(n4391), .Y(n4275) );
INVX12TS U2786 ( .A(n3610), .Y(n2433) );
INVX4TS U2787 ( .A(n4207), .Y(n4491) );
INVX4TS U2788 ( .A(n3231), .Y(n3422) );
NOR2X6TS U2789 ( .A(n3745), .B(DP_OP_496J2_122_3540_n1102), .Y(n3876) );
INVX3TS U2790 ( .A(n2730), .Y(n3879) );
NAND2X2TS U2791 ( .A(n2856), .B(n7699), .Y(n2855) );
INVX2TS U2792 ( .A(FPMULT_Op_MY[22]), .Y(n2684) );
INVX4TS U2793 ( .A(n3306), .Y(n3571) );
NOR2X1TS U2794 ( .A(n3145), .B(n4451), .Y(n4301) );
INVX6TS U2795 ( .A(FPMULT_Op_MY[9]), .Y(n4484) );
OR2X6TS U2796 ( .A(n3144), .B(n4255), .Y(n3761) );
OAI21X2TS U2797 ( .A0(n3266), .A1(n3267), .B0(n3265), .Y(n2910) );
INVX6TS U2798 ( .A(n4206), .Y(n4495) );
INVX2TS U2799 ( .A(FPMULT_Op_MX[22]), .Y(n2683) );
NAND2X2TS U2800 ( .A(n3321), .B(n3305), .Y(n4727) );
NOR2X4TS U2801 ( .A(n3538), .B(n2226), .Y(n3401) );
INVX8TS U2802 ( .A(n4180), .Y(n4331) );
NOR2X2TS U2803 ( .A(n3310), .B(n3166), .Y(n3309) );
NAND2X1TS U2804 ( .A(n3247), .B(n2768), .Y(n2628) );
NAND2X2TS U2805 ( .A(n3180), .B(n3165), .Y(n3770) );
BUFX4TS U2806 ( .A(n3769), .Y(n3774) );
OAI2BB1X2TS U2807 ( .A0N(n2762), .A1N(n2761), .B0(n3213), .Y(n2760) );
NAND2BX2TS U2808 ( .AN(n7700), .B(n4220), .Y(n2856) );
NAND2X4TS U2809 ( .A(n3762), .B(n2496), .Y(n2495) );
CLKXOR2X4TS U2810 ( .A(n2899), .B(n2898), .Y(n3215) );
ADDHX1TS U2811 ( .A(DP_OP_497J2_123_1725_n794), .B(
DP_OP_496J2_122_3540_n1502), .CO(n3317), .S(n3306) );
CMPR22X2TS U2812 ( .A(n3323), .B(n3322), .CO(n3325), .S(n3557) );
CLKXOR2X4TS U2813 ( .A(DP_OP_498J2_124_1725_n362), .B(n7688), .Y(n2314) );
INVX12TS U2814 ( .A(DP_OP_498J2_124_1725_n797), .Y(n4483) );
INVX2TS U2815 ( .A(DP_OP_496J2_122_3540_n1103), .Y(n2496) );
NOR2X2TS U2816 ( .A(n2643), .B(DP_OP_497J2_123_1725_n324), .Y(n3481) );
BUFX4TS U2817 ( .A(FPMULT_Op_MX[16]), .Y(n2936) );
NOR2X4TS U2818 ( .A(n4166), .B(n4211), .Y(n4162) );
INVX8TS U2819 ( .A(FPMULT_Op_MY[8]), .Y(n4450) );
NOR2X2TS U2820 ( .A(n3310), .B(n8285), .Y(n3357) );
NOR2X2TS U2821 ( .A(n2226), .B(n3310), .Y(n3323) );
NAND2X2TS U2822 ( .A(n7673), .B(n3279), .Y(n3255) );
NOR2X4TS U2823 ( .A(n3310), .B(n3355), .Y(n3465) );
AND2X4TS U2824 ( .A(n3230), .B(DP_OP_497J2_123_1725_n392), .Y(n3408) );
CMPR22X2TS U2825 ( .A(DP_OP_498J2_124_1725_n790), .B(n6900), .CO(n4217), .S(
n4206) );
NOR2X4TS U2826 ( .A(n4391), .B(n4355), .Y(n4472) );
INVX6TS U2827 ( .A(DP_OP_498J2_124_1725_n795), .Y(n4391) );
INVX2TS U2828 ( .A(n2270), .Y(n2521) );
INVX8TS U2829 ( .A(DP_OP_498J2_124_1725_n801), .Y(n4165) );
INVX8TS U2830 ( .A(DP_OP_497J2_123_1725_n686), .Y(n3310) );
OR2X2TS U2831 ( .A(DP_OP_497J2_123_1725_n686), .B(DP_OP_497J2_123_1725_n778),
.Y(n3230) );
NOR2X2TS U2832 ( .A(n2870), .B(DP_OP_497J2_123_1725_n638), .Y(n3212) );
NOR2X4TS U2833 ( .A(n3232), .B(n3270), .Y(n3209) );
NOR2X2TS U2834 ( .A(DP_OP_497J2_123_1725_n324), .B(n3240), .Y(n3268) );
BUFX12TS U2835 ( .A(FPMULT_Op_MY[8]), .Y(n6900) );
XOR2X2TS U2836 ( .A(n2917), .B(n2916), .Y(n2769) );
NOR2X2TS U2837 ( .A(DP_OP_497J2_123_1725_n324), .B(n3232), .Y(n3221) );
NOR2X6TS U2838 ( .A(n3270), .B(DP_OP_497J2_123_1725_n631), .Y(n2898) );
NOR2X6TS U2839 ( .A(n3480), .B(DP_OP_497J2_123_1725_n638), .Y(n2975) );
NOR2X2TS U2840 ( .A(n3240), .B(n3479), .Y(n3241) );
NAND2X6TS U2841 ( .A(n3293), .B(n2653), .Y(n3139) );
INVX6TS U2842 ( .A(DP_OP_497J2_123_1725_n778), .Y(n3232) );
INVX6TS U2843 ( .A(DP_OP_497J2_123_1725_n780), .Y(n3240) );
NOR2X4TS U2844 ( .A(n2748), .B(n3538), .Y(n2871) );
BUFX8TS U2845 ( .A(n3300), .Y(n2868) );
NAND2X6TS U2846 ( .A(n3279), .B(n2654), .Y(n3294) );
INVX16TS U2847 ( .A(DP_OP_497J2_123_1725_n781), .Y(n2870) );
BUFX6TS U2848 ( .A(DP_OP_497J2_123_1725_n780), .Y(n5707) );
AND2X6TS U2849 ( .A(n3538), .B(n2870), .Y(n3300) );
BUFX8TS U2850 ( .A(FPMULT_Op_MY[20]), .Y(n3860) );
INVX2TS U2851 ( .A(n2250), .Y(n2197) );
INVX2TS U2852 ( .A(n2197), .Y(n2198) );
INVX2TS U2853 ( .A(n2197), .Y(n2199) );
INVX2TS U2854 ( .A(n2257), .Y(n2200) );
INVX2TS U2855 ( .A(n2200), .Y(n2201) );
INVX2TS U2856 ( .A(n2200), .Y(n2202) );
INVX2TS U2857 ( .A(n2203), .Y(n2204) );
CLKINVX3TS U2858 ( .A(n2203), .Y(n2205) );
INVX2TS U2859 ( .A(n2255), .Y(n2206) );
INVX2TS U2860 ( .A(n2206), .Y(n2207) );
INVX2TS U2861 ( .A(n2206), .Y(n2208) );
INVX2TS U2862 ( .A(n2249), .Y(n2209) );
INVX2TS U2863 ( .A(n2209), .Y(n2210) );
INVX2TS U2864 ( .A(n2209), .Y(n2211) );
INVX2TS U2865 ( .A(n2209), .Y(n2212) );
INVX2TS U2866 ( .A(n2253), .Y(n2213) );
INVX2TS U2867 ( .A(n2213), .Y(n2214) );
INVX2TS U2868 ( .A(n2213), .Y(n2215) );
INVX2TS U2869 ( .A(n2213), .Y(n2216) );
INVX2TS U2870 ( .A(n2213), .Y(n2217) );
INVX2TS U2871 ( .A(n2254), .Y(n2218) );
INVX2TS U2872 ( .A(n2218), .Y(n2219) );
CLKINVX3TS U2873 ( .A(n2218), .Y(n2220) );
INVX2TS U2874 ( .A(n2218), .Y(n2221) );
CLKINVX3TS U2875 ( .A(n2218), .Y(n2222) );
NAND2X1TS U2876 ( .A(n3908), .B(n3911), .Y(n3813) );
BUFX3TS U2877 ( .A(n2870), .Y(n2748) );
BUFX4TS U2878 ( .A(n3786), .Y(n2576) );
OA21X1TS U2879 ( .A0(n4405), .A1(n4404), .B0(n4403), .Y(n3163) );
INVX4TS U2880 ( .A(n4324), .Y(n5029) );
ADDFX2TS U2881 ( .A(n4540), .B(n4539), .CI(n4538), .CO(n4951), .S(n4559) );
OAI22X1TS U2882 ( .A0(n4627), .A1(n4098), .B0(n4588), .B1(n4626), .Y(n4595)
);
CMPR22X2TS U2883 ( .A(DP_OP_498J2_124_1725_n791), .B(n6899), .CO(n4299), .S(
n4218) );
INVX6TS U2884 ( .A(n3910), .Y(n4093) );
OAI21X2TS U2885 ( .A0(n4065), .A1(n2943), .B0(n4064), .Y(n2941) );
INVX2TS U2886 ( .A(n3573), .Y(n3614) );
AND2X2TS U2887 ( .A(n3419), .B(n3480), .Y(n3420) );
INVX2TS U2888 ( .A(n2882), .Y(n3639) );
NOR2X1TS U2889 ( .A(DP_OP_498J2_124_1725_n722), .B(n2275), .Y(n4544) );
INVX2TS U2890 ( .A(n4562), .Y(n2677) );
OR2X2TS U2891 ( .A(n8285), .B(n8343), .Y(n2299) );
NOR2X4TS U2892 ( .A(n3480), .B(n2320), .Y(n3269) );
INVX4TS U2893 ( .A(n2314), .Y(n2377) );
XNOR2X2TS U2894 ( .A(n2812), .B(n2811), .Y(n2810) );
NOR2X1TS U2895 ( .A(n4973), .B(n2275), .Y(n4969) );
NOR2X1TS U2896 ( .A(n5341), .B(n2354), .Y(n5421) );
NOR2X2TS U2897 ( .A(n3174), .B(n3166), .Y(n2563) );
NAND2BX2TS U2898 ( .AN(n2933), .B(n3269), .Y(n2932) );
INVX2TS U2899 ( .A(n3543), .Y(n2739) );
NAND2X1TS U2900 ( .A(n5080), .B(n5098), .Y(n5081) );
ADDFHX2TS U2901 ( .A(n4969), .B(n4968), .CI(n4967), .CO(n5476), .S(n5391) );
OAI22X1TS U2902 ( .A0(n5417), .A1(n5416), .B0(n2231), .B1(n5346), .Y(n5414)
);
NAND2X2TS U2903 ( .A(n2806), .B(n4950), .Y(n4564) );
OR2X1TS U2904 ( .A(n4018), .B(n4003), .Y(n3751) );
INVX2TS U2905 ( .A(n7213), .Y(n4879) );
OAI21X1TS U2906 ( .A0(n4828), .A1(n4827), .B0(n4826), .Y(n4833) );
NAND2X1TS U2907 ( .A(n2269), .B(n5118), .Y(n5387) );
NOR2X2TS U2908 ( .A(n3355), .B(n3538), .Y(n3356) );
OAI22X2TS U2909 ( .A0(n4008), .A1(n4933), .B0(n4934), .B1(n4007), .Y(n5275)
);
NAND2X1TS U2910 ( .A(n4645), .B(n4905), .Y(n4647) );
BUFX4TS U2911 ( .A(n2587), .Y(n2557) );
INVX6TS U2912 ( .A(FPMULT_Op_MX[16]), .Y(n3479) );
NAND2X4TS U2913 ( .A(n2629), .B(n2628), .Y(n3447) );
NAND2X4TS U2914 ( .A(n2605), .B(n4475), .Y(n4635) );
INVX2TS U2915 ( .A(n4306), .Y(n4307) );
INVX2TS U2916 ( .A(n5143), .Y(n5054) );
OAI211XLTS U2917 ( .A0(n5941), .A1(n7371), .B0(n5939), .C0(n5938), .Y(n5944)
);
NOR2X1TS U2918 ( .A(n5174), .B(n5212), .Y(n5202) );
OR2X1TS U2919 ( .A(n5276), .B(n5275), .Y(n5297) );
NAND2X1TS U2920 ( .A(n5381), .B(n5380), .Y(n5600) );
OAI21XLTS U2921 ( .A0(n7186), .A1(n7191), .B0(n7187), .Y(n5847) );
NAND2X6TS U2922 ( .A(n3189), .B(n5461), .Y(n2736) );
NAND2X1TS U2923 ( .A(n3582), .B(n3573), .Y(n3508) );
INVX4TS U2924 ( .A(n4179), .Y(n4407) );
CLKBUFX2TS U2925 ( .A(n6191), .Y(n6603) );
NOR2XLTS U2926 ( .A(n6403), .B(n6397), .Y(n5846) );
NAND2X1TS U2927 ( .A(FPMULT_Op_MX[22]), .B(FPMULT_Op_MY[22]), .Y(n2681) );
OAI21XLTS U2928 ( .A0(n5826), .A1(n6362), .B0(n5825), .Y(n5827) );
NOR2XLTS U2929 ( .A(n6563), .B(FPADDSUB_exp_rslt_NRM2_EW1[5]), .Y(n6564) );
NOR2X4TS U2930 ( .A(n3689), .B(n3688), .Y(n4996) );
NAND2X2TS U2931 ( .A(n2760), .B(n2758), .Y(n3226) );
NOR2BX1TS U2932 ( .AN(n3493), .B(n3514), .Y(n3046) );
INVX6TS U2933 ( .A(n2859), .Y(n2860) );
OAI21XLTS U2934 ( .A0(n7392), .A1(n6012), .B0(n7391), .Y(n6013) );
NAND2X1TS U2935 ( .A(n5409), .B(n5566), .Y(n5355) );
OAI21XLTS U2936 ( .A0(n5660), .A1(n5632), .B0(n5631), .Y(n5637) );
OR2X1TS U2937 ( .A(n4731), .B(n4730), .Y(n4732) );
AND4X1TS U2938 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[5]), .C(FPADDSUB_exp_rslt_NRM2_EW1[4]), .D(
n6804), .Y(n6805) );
BUFX3TS U2939 ( .A(n5561), .Y(n5486) );
NOR2X2TS U2940 ( .A(n3342), .B(n3422), .Y(n3260) );
NOR2X4TS U2941 ( .A(n3487), .B(n3486), .Y(n3484) );
AOI21X2TS U2942 ( .A0(n6162), .A1(n6158), .B0(n6093), .Y(n6153) );
NOR2XLTS U2943 ( .A(n7861), .B(n2486), .Y(n6086) );
OAI21XLTS U2944 ( .A0(n6335), .A1(n6236), .B0(n6235), .Y(n6240) );
XNOR2X2TS U2945 ( .A(n4193), .B(n4192), .Y(n4706) );
OAI21XLTS U2946 ( .A0(n6604), .A1(n6498), .B0(n6497), .Y(n6499) );
OAI21XLTS U2947 ( .A0(n6404), .A1(n6403), .B0(n6402), .Y(n6406) );
NOR2X1TS U2948 ( .A(n5553), .B(n3186), .Y(n5610) );
OR2X4TS U2949 ( .A(n2755), .B(n2596), .Y(n3716) );
BUFX3TS U2950 ( .A(n2256), .Y(n5934) );
NOR2X6TS U2951 ( .A(n7250), .B(n6213), .Y(n5151) );
NAND2X2TS U2952 ( .A(n3487), .B(n3486), .Y(n3735) );
NOR2XLTS U2953 ( .A(n7062), .B(n2339), .Y(n7063) );
NOR2XLTS U2954 ( .A(n7071), .B(n7029), .Y(n7006) );
NOR2XLTS U2955 ( .A(n7074), .B(n7029), .Y(n7001) );
NAND2X1TS U2956 ( .A(n4851), .B(n4850), .Y(n4852) );
OAI21XLTS U2957 ( .A0(n7190), .A1(n7172), .B0(n7171), .Y(n7177) );
NAND2X2TS U2958 ( .A(n5750), .B(n5739), .Y(n5745) );
NOR2X1TS U2959 ( .A(n6699), .B(n7824), .Y(n6283) );
INVX4TS U2960 ( .A(n2229), .Y(n2259) );
NAND2X1TS U2961 ( .A(n5934), .B(n8283), .Y(n5892) );
NOR2XLTS U2962 ( .A(n2339), .B(n7077), .Y(n7078) );
AOI31XLTS U2963 ( .A0(n7593), .A1(n7592), .A2(n7591), .B0(n7595), .Y(n7596)
);
NAND2X1TS U2964 ( .A(n5513), .B(n5533), .Y(n5514) );
BUFX3TS U2965 ( .A(n6723), .Y(n6824) );
CLKINVX3TS U2966 ( .A(n6778), .Y(n6796) );
NOR2XLTS U2967 ( .A(n2361), .B(n7322), .Y(n7324) );
BUFX3TS U2968 ( .A(n6624), .Y(n6711) );
NOR2X4TS U2969 ( .A(n6647), .B(operation[2]), .Y(n6623) );
AOI21X2TS U2970 ( .A0(n6211), .A1(n5151), .B0(n5129), .Y(n5153) );
NAND3X6TS U2971 ( .A(n3085), .B(n3084), .C(n3735), .Y(n3739) );
INVX2TS U2972 ( .A(n1662), .Y(n6426) );
NOR3X1TS U2973 ( .A(n1321), .B(n1322), .C(n1323), .Y(n6878) );
NAND2X1TS U2974 ( .A(n6581), .B(FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n6280) );
OAI2BB1X1TS U2975 ( .A0N(n8043), .A1N(n5452), .B0(n8498), .Y(n6358) );
NAND2X2TS U2976 ( .A(n6651), .B(FPMULT_FS_Module_state_reg[3]), .Y(n6263) );
ADDHXLTS U2977 ( .A(FPMULT_Sgf_normalized_result[7]), .B(n6937), .CO(n6935),
.S(n6938) );
INVX2TS U2978 ( .A(n7519), .Y(n6816) );
BUFX3TS U2979 ( .A(FPMULT_FS_Module_state_reg[1]), .Y(n2350) );
AND2X4TS U2980 ( .A(n8523), .B(n7595), .Y(n6863) );
BUFX3TS U2981 ( .A(n7385), .Y(n7432) );
AO22X1TS U2982 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[1]), .A1(n6581), .B0(
n6882), .B1(n7092), .Y(n6817) );
INVX2TS U2983 ( .A(n2244), .Y(n2355) );
BUFX3TS U2984 ( .A(n6190), .Y(n7426) );
INVX2TS U2985 ( .A(n8611), .Y(n7406) );
INVX2TS U2986 ( .A(n7334), .Y(n7338) );
INVX2TS U2987 ( .A(n7334), .Y(n7332) );
INVX2TS U2988 ( .A(n7424), .Y(n7353) );
INVX2TS U2989 ( .A(n2196), .Y(intadd_9_B_1_) );
INVX2TS U2990 ( .A(n7297), .Y(n6661) );
NOR2X4TS U2991 ( .A(operation[1]), .B(operation[2]), .Y(n7297) );
INVX2TS U2992 ( .A(n8835), .Y(n8607) );
NOR2X2TS U2993 ( .A(FPMULT_Sgf_operation_EVEN1_S_B[17]), .B(
FPMULT_Sgf_operation_EVEN1_Q_left[5]), .Y(add_x_69_n198) );
NOR2XLTS U2994 ( .A(n7687), .B(n7689), .Y(n7692) );
NAND2X1TS U2995 ( .A(n5715), .B(n2794), .Y(n5717) );
OAI21XLTS U2996 ( .A0(n6682), .A1(n6832), .B0(n6681), .Y(n2077) );
OAI211XLTS U2997 ( .A0(n8612), .A1(n7853), .B0(n6816), .C0(n6814), .Y(n1474)
);
OAI21XLTS U2998 ( .A0(n6587), .A1(n6586), .B0(n7288), .Y(n2151) );
OAI21XLTS U2999 ( .A0(n6763), .A1(n6762), .B0(n6761), .Y(n1733) );
BUFX3TS U3000 ( .A(n7413), .Y(n8611) );
NOR2X2TS U3001 ( .A(n7654), .B(n7595), .Y(n8835) );
BUFX3TS U3002 ( .A(n7385), .Y(n7374) );
BUFX3TS U3003 ( .A(n8835), .Y(n8608) );
OAI21XLTS U3004 ( .A0(n6682), .A1(n8526), .B0(n6680), .Y(n1332) );
OAI21XLTS U3005 ( .A0(n2196), .A1(n7322), .B0(n6634), .Y(n2131) );
CLKINVX3TS U3006 ( .A(n7663), .Y(busy) );
INVX2TS U3007 ( .A(n7627), .Y(n2412) );
NAND3X6TS U3008 ( .A(n5460), .B(n5463), .C(n2736), .Y(n2985) );
AND2X8TS U3009 ( .A(n4983), .B(n2806), .Y(n2228) );
AND2X4TS U3010 ( .A(n3470), .B(n3469), .Y(n2230) );
INVX4TS U3011 ( .A(n7452), .Y(n2244) );
CLKINVX3TS U3012 ( .A(n2244), .Y(n2357) );
NAND2X4TS U3013 ( .A(n3963), .B(n3962), .Y(n2231) );
BUFX3TS U3014 ( .A(n6862), .Y(n6864) );
CLKINVX3TS U3015 ( .A(n8523), .Y(n6862) );
BUFX3TS U3016 ( .A(n7424), .Y(n7364) );
CLKINVX3TS U3017 ( .A(n6548), .Y(n6559) );
BUFX3TS U3018 ( .A(n6559), .Y(n7424) );
AND2X4TS U3019 ( .A(n2981), .B(n2312), .Y(n3721) );
INVX4TS U3020 ( .A(n3721), .Y(n2753) );
INVX2TS U3021 ( .A(n5157), .Y(n3580) );
OA21X4TS U3022 ( .A0(n2986), .A1(n3923), .B0(n3007), .Y(n2232) );
INVX2TS U3023 ( .A(n2961), .Y(n5211) );
NAND2X6TS U3024 ( .A(n2530), .B(n5395), .Y(n5406) );
AOI21X2TS U3025 ( .A0(n4856), .A1(n4749), .B0(n4692), .Y(n4697) );
NAND2X6TS U3026 ( .A(n2712), .B(n2713), .Y(n2631) );
INVX12TS U3027 ( .A(add_x_69_n272), .Y(n6252) );
NAND2X6TS U3028 ( .A(n2323), .B(n5153), .Y(add_x_69_n272) );
CLKMX2X2TS U3029 ( .A(n7254), .B(FPMULT_P_Sgf[18]), .S0(n7216), .Y(n1571) );
NAND2X2TS U3030 ( .A(n2669), .B(n7251), .Y(n6217) );
NAND2X4TS U3031 ( .A(n2672), .B(n2671), .Y(n2670) );
INVX4TS U3032 ( .A(n6210), .Y(n7243) );
NAND2X4TS U3033 ( .A(n2820), .B(n5126), .Y(n7251) );
INVX4TS U3034 ( .A(n2265), .Y(n2825) );
CLKMX2X2TS U3035 ( .A(n7223), .B(FPMULT_P_Sgf[13]), .S0(n8524), .Y(n1566) );
NAND2X4TS U3036 ( .A(n2970), .B(n2499), .Y(n2969) );
INVX3TS U3037 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[13]), .Y(n4680) );
CLKMX2X2TS U3038 ( .A(n7217), .B(FPMULT_P_Sgf[12]), .S0(n8525), .Y(n1565) );
NOR2X4TS U3039 ( .A(n3742), .B(n3740), .Y(n2745) );
NAND2X4TS U3040 ( .A(n3019), .B(n4635), .Y(n3018) );
INVX2TS U3041 ( .A(n5409), .Y(n5563) );
OR2X2TS U3042 ( .A(n7214), .B(n5136), .Y(n7215) );
NAND2X4TS U3043 ( .A(n5353), .B(n5354), .Y(n5566) );
CLKMX2X2TS U3044 ( .A(n7213), .B(FPMULT_P_Sgf[11]), .S0(n7253), .Y(n1564) );
NAND2X4TS U3045 ( .A(n2548), .B(n3589), .Y(n3555) );
CLKMX2X2TS U3046 ( .A(n7212), .B(FPMULT_P_Sgf[10]), .S0(n6955), .Y(n1563) );
OR2X2TS U3047 ( .A(n4813), .B(n4812), .Y(n4811) );
NAND2X4TS U3048 ( .A(n4043), .B(n4042), .Y(n4847) );
ADDHX1TS U3049 ( .A(FPMULT_Sgf_normalized_result[22]), .B(n5787), .CO(
add_x_246_n2), .S(FPMULT_Adder_M_result_A_adder[22]) );
NAND2BX2TS U3050 ( .AN(n6817), .B(n7434), .Y(n7435) );
NAND2X2TS U3051 ( .A(n6817), .B(n7434), .Y(n8713) );
INVX6TS U3052 ( .A(n2412), .Y(n2413) );
ADDHX2TS U3053 ( .A(FPMULT_Sgf_normalized_result[21]), .B(n6908), .CO(n5787),
.S(n6909) );
CLKMX2X2TS U3054 ( .A(n6915), .B(FPMULT_Add_result[18]), .S0(n6921), .Y(
n1606) );
ADDHX1TS U3055 ( .A(FPMULT_Sgf_normalized_result[19]), .B(n6912), .CO(n6910),
.S(n6913) );
ADDHX2TS U3056 ( .A(n3956), .B(n3955), .CO(n3972), .S(n3974) );
INVX2TS U3057 ( .A(n5203), .Y(n5257) );
AOI211X1TS U3058 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[12]), .A1(n6698), .B0(n6697), .C0(n6696), .Y(n6702) );
ADDHX1TS U3059 ( .A(FPMULT_Sgf_normalized_result[18]), .B(n6914), .CO(n6912),
.S(n6915) );
CLKINVX2TS U3060 ( .A(n7520), .Y(n6808) );
CLKMX2X2TS U3061 ( .A(n6917), .B(FPMULT_Add_result[17]), .S0(n6921), .Y(
n1607) );
CLKMX2X2TS U3062 ( .A(n6919), .B(FPMULT_Add_result[16]), .S0(n6921), .Y(
n1608) );
ADDHX1TS U3063 ( .A(FPMULT_Sgf_normalized_result[17]), .B(n6916), .CO(n6914),
.S(n6917) );
ADDFHX2TS U3064 ( .A(n3667), .B(n3666), .CI(n3665), .CO(n3697), .S(n3669) );
CLKMX2X2TS U3065 ( .A(FPMULT_exp_oper_result[5]), .B(n7099), .S0(n6981), .Y(
n1544) );
OR2X2TS U3066 ( .A(n4794), .B(n4793), .Y(n3176) );
ADDHX1TS U3067 ( .A(FPMULT_Sgf_normalized_result[16]), .B(n6918), .CO(n6916),
.S(n6919) );
NAND3BX2TS U3068 ( .AN(n6014), .B(n6011), .C(n6010), .Y(n6036) );
AOI211X1TS U3069 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[12]), .A1(n6698), .B0(n6067), .C0(n6058), .Y(n6671) );
CLKMX2X2TS U3070 ( .A(FPMULT_exp_oper_result[4]), .B(n7098), .S0(n6981), .Y(
n1545) );
AOI2BB2X1TS U3071 ( .B0(n7424), .B1(n7423), .A0N(FPSENCOS_d_ff3_sh_y_out[29]), .A1N(n7422), .Y(n1849) );
AOI2BB2X1TS U3072 ( .B0(n6559), .B1(n7363), .A0N(FPSENCOS_d_ff3_sh_x_out[29]), .A1N(n7422), .Y(n1947) );
BUFX16TS U3073 ( .A(n4001), .Y(n4108) );
CLKMX2X2TS U3074 ( .A(FPMULT_exp_oper_result[3]), .B(n7097), .S0(n6981), .Y(
n1546) );
INVX4TS U3075 ( .A(n6838), .Y(n6855) );
AOI2BB2X1TS U3076 ( .B0(n6559), .B1(n7419), .A0N(FPSENCOS_d_ff3_sh_y_out[27]), .A1N(n7422), .Y(n1851) );
AOI2BB2X1TS U3077 ( .B0(FPADDSUB_left_right_SHT2), .B1(n7085), .A0N(n7081),
.A1N(n7029), .Y(n6184) );
OR2X2TS U3078 ( .A(n6336), .B(n6335), .Y(n6340) );
INVX2TS U3079 ( .A(n2442), .Y(n2271) );
INVX4TS U3080 ( .A(n2409), .Y(n2411) );
XOR2X1TS U3081 ( .A(n6593), .B(n6592), .Y(n6598) );
AOI2BB2X1TS U3082 ( .B0(n6559), .B1(n7321), .A0N(FPSENCOS_d_ff3_LUT_out[13]),
.A1N(n7422), .Y(n2123) );
OR2X2TS U3083 ( .A(n1673), .B(n1661), .Y(n7717) );
AND2X2TS U3084 ( .A(n4782), .B(n4781), .Y(n4783) );
OAI21X1TS U3085 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[6]), .A1(
FPADDSUB_Raw_mant_NRM_SWR[7]), .B0(n6065), .Y(n6066) );
NOR2X4TS U3086 ( .A(n4510), .B(n4251), .Y(n4258) );
BUFX3TS U3087 ( .A(n4026), .Y(n3072) );
NAND2BX1TS U3088 ( .AN(n2382), .B(n2442), .Y(n3789) );
MX2X1TS U3089 ( .A(FPMULT_exp_oper_result[2]), .B(n7096), .S0(n6981), .Y(
n1547) );
MX2X1TS U3090 ( .A(FPMULT_exp_oper_result[1]), .B(n7095), .S0(n6981), .Y(
n1548) );
AOI2BB2X1TS U3091 ( .B0(n6559), .B1(n7358), .A0N(FPSENCOS_d_ff3_sh_x_out[27]), .A1N(n7422), .Y(n1949) );
INVX12TS U3092 ( .A(n2617), .Y(n5209) );
INVX2TS U3093 ( .A(n2268), .Y(n2269) );
INVX4TS U3094 ( .A(n7413), .Y(n6775) );
INVX4TS U3095 ( .A(n6559), .Y(n7330) );
INVX4TS U3096 ( .A(n7364), .Y(n7325) );
NAND2X1TS U3097 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(n7629), .Y(n6815) );
OR2X2TS U3098 ( .A(n1643), .B(n1631), .Y(n3148) );
NAND2X1TS U3099 ( .A(n6283), .B(FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n6286) );
INVX4TS U3100 ( .A(n7426), .Y(n6755) );
INVX4TS U3101 ( .A(n7426), .Y(n6750) );
CLKMX2X2TS U3102 ( .A(Data_1[20]), .B(FPMULT_Op_MX[20]), .S0(n2356), .Y(
n1679) );
NOR2X1TS U3103 ( .A(n6014), .B(n7562), .Y(n6015) );
INVX4TS U3104 ( .A(n6859), .Y(n7253) );
INVX4TS U3105 ( .A(n6859), .Y(n7216) );
NAND2X1TS U3106 ( .A(n6699), .B(FPADDSUB_LZD_output_NRM2_EW[4]), .Y(n6680)
);
INVX4TS U3107 ( .A(n6859), .Y(n6955) );
NAND3X1TS U3108 ( .A(n6059), .B(FPADDSUB_Raw_mant_NRM_SWR[8]), .C(n7812),
.Y(n6060) );
NAND2X1TS U3109 ( .A(n6699), .B(FPADDSUB_LZD_output_NRM2_EW[3]), .Y(n6700)
);
NAND4X1TS U3110 ( .A(n8641), .B(n8640), .C(n8639), .D(n7274), .Y(n7276) );
OAI211X1TS U3111 ( .A0(n8633), .A1(n8646), .B0(n6691), .C0(n6690), .Y(n6697)
);
AO22X1TS U3112 ( .A0(n2244), .A1(Data_1[31]), .B0(n7452), .B1(
FPMULT_Op_MX[31]), .Y(n1658) );
INVX3TS U3113 ( .A(n2244), .Y(n6901) );
NAND2X1TS U3114 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[1]), .B(n7629), .Y(n6814) );
AO22X1TS U3115 ( .A0(n2244), .A1(Data_2[31]), .B0(n7452), .B1(
FPMULT_Op_MY[31]), .Y(n1696) );
AOI2BB2X1TS U3116 ( .B0(n7602), .B1(n7601), .A0N(n7601), .A1N(n7602), .Y(
n7603) );
OAI21X1TS U3117 ( .A0(n6201), .A1(n6220), .B0(n6200), .Y(n6202) );
INVX4TS U3118 ( .A(n2244), .Y(n2356) );
NOR2X4TS U3119 ( .A(n6905), .B(n7811), .Y(n5774) );
AO22X1TS U3120 ( .A0(n7355), .A1(FPSENCOS_d_ff2_X[18]), .B0(n6548), .B1(
FPSENCOS_d_ff3_sh_x_out[18]), .Y(n1970) );
NOR2X1TS U3121 ( .A(FPADDSUB_Raw_mant_NRM_SWR[12]), .B(n6064), .Y(n6068) );
AO22X1TS U3122 ( .A0(n7355), .A1(FPSENCOS_d_ff2_X[20]), .B0(n6548), .B1(
FPSENCOS_d_ff3_sh_x_out[20]), .Y(n1966) );
AO22X1TS U3123 ( .A0(n7355), .A1(FPSENCOS_d_ff2_X[19]), .B0(n6548), .B1(
FPSENCOS_d_ff3_sh_x_out[19]), .Y(n1968) );
CLKMX2X2TS U3124 ( .A(n7803), .B(n5701), .S0(n2244), .Y(n5702) );
OR2X2TS U3125 ( .A(n3556), .B(n3557), .Y(n3185) );
INVX4TS U3126 ( .A(n7827), .Y(n6939) );
NAND2X1TS U3127 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[0]), .B(n7629), .Y(n6811) );
INVX1TS U3128 ( .A(n6453), .Y(n6343) );
AND2X2TS U3129 ( .A(n4735), .B(n4739), .Y(n7211) );
NAND2X4TS U3130 ( .A(n3761), .B(n2495), .Y(n3875) );
OAI21X1TS U3131 ( .A0(n7157), .A1(n6377), .B0(n6376), .Y(n6380) );
AO22X1TS U3132 ( .A0(n7664), .A1(FPADDSUB_DMP_SHT1_EWSW[14]), .B0(n7642),
.B1(FPADDSUB_DMP_SHT2_EWSW[14]), .Y(n1261) );
XOR2X1TS U3133 ( .A(n6335), .B(n7743), .Y(n5770) );
AO22X1TS U3134 ( .A0(n7664), .A1(FPADDSUB_DMP_SHT1_EWSW[11]), .B0(n7939),
.B1(FPADDSUB_DMP_SHT2_EWSW[11]), .Y(n1257) );
AO22X1TS U3135 ( .A0(n8838), .A1(FPADDSUB_DMP_SHT1_EWSW[3]), .B0(
FPADDSUB_DMP_SHT2_EWSW[3]), .B1(n7658), .Y(n7924) );
AO22X1TS U3136 ( .A0(n7600), .A1(FPADDSUB_DMP_SFG[29]), .B0(n7599), .B1(
FPADDSUB_DMP_exp_NRM_EW[6]), .Y(n1426) );
AO22X1TS U3137 ( .A0(n7648), .A1(FPADDSUB_DMP_SHT1_EWSW[29]), .B0(n7642),
.B1(FPADDSUB_DMP_SHT2_EWSW[29]), .Y(n1428) );
AO22X1TS U3138 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[0]), .B0(
FPADDSUB_DMP_SHT2_EWSW[0]), .B1(n7658), .Y(n7921) );
AO22X1TS U3139 ( .A0(n7664), .A1(FPADDSUB_DMP_SHT1_EWSW[16]), .B0(n7658),
.B1(FPADDSUB_DMP_SHT2_EWSW[16]), .Y(n1249) );
AO22X1TS U3140 ( .A0(n7664), .A1(FPADDSUB_DMP_SHT1_EWSW[8]), .B0(n7939),
.B1(FPADDSUB_DMP_SHT2_EWSW[8]), .Y(n1253) );
AO22X1TS U3141 ( .A0(n7664), .A1(FPADDSUB_DMP_SHT1_EWSW[10]), .B0(n7642),
.B1(FPADDSUB_DMP_SHT2_EWSW[10]), .Y(n1265) );
AO22X1TS U3142 ( .A0(n7648), .A1(FPADDSUB_DMP_SHT1_EWSW[26]), .B0(n7642),
.B1(FPADDSUB_DMP_SHT2_EWSW[26]), .Y(n1443) );
OAI211X2TS U3143 ( .A0(n2204), .A1(n8332), .B0(n8331), .C0(n5929), .Y(n7369)
);
NAND2X1TS U3144 ( .A(n2358), .B(FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n6287) );
OAI211X2TS U3145 ( .A0(n2204), .A1(n8330), .B0(n8329), .C0(n5921), .Y(n7614)
);
AO22X1TS U3146 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[1]), .B0(
FPADDSUB_DMP_SHT2_EWSW[1]), .B1(n7658), .Y(n7920) );
AO22X1TS U3147 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[7]), .B0(
FPADDSUB_DMP_SHT2_EWSW[7]), .B1(n7663), .Y(n7922) );
AO22X1TS U3148 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[24]), .B0(n7658),
.B1(FPADDSUB_DMP_SHT2_EWSW[24]), .Y(n1453) );
AO22X1TS U3149 ( .A0(n7648), .A1(FPADDSUB_DMP_SHT1_EWSW[27]), .B0(n7642),
.B1(FPADDSUB_DMP_SHT2_EWSW[27]), .Y(n1438) );
AO22X1TS U3150 ( .A0(n7648), .A1(FPADDSUB_DMP_SHT1_EWSW[9]), .B0(n7642),
.B1(FPADDSUB_DMP_SHT2_EWSW[9]), .Y(n1282) );
AO22X1TS U3151 ( .A0(n7648), .A1(FPADDSUB_DMP_SHT1_EWSW[28]), .B0(n7642),
.B1(FPADDSUB_DMP_SHT2_EWSW[28]), .Y(n1433) );
AO22X1TS U3152 ( .A0(n8838), .A1(FPADDSUB_DMP_SHT1_EWSW[2]), .B0(
FPADDSUB_DMP_SHT2_EWSW[2]), .B1(n7658), .Y(n7923) );
AO22X1TS U3153 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[5]), .B0(
FPADDSUB_DMP_SHT2_EWSW[5]), .B1(n7663), .Y(n7919) );
AO22X1TS U3154 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[23]), .B0(n7663),
.B1(FPADDSUB_DMP_SHT2_EWSW[23]), .Y(n1458) );
AO22X1TS U3155 ( .A0(n7600), .A1(FPADDSUB_DMP_SFG[30]), .B0(n7088), .B1(
FPADDSUB_DMP_exp_NRM_EW[7]), .Y(n1421) );
AO22X1TS U3156 ( .A0(n7600), .A1(FPADDSUB_DMP_SFG[28]), .B0(n7088), .B1(
FPADDSUB_DMP_exp_NRM_EW[5]), .Y(n1431) );
AO22X1TS U3157 ( .A0(n7648), .A1(FPADDSUB_DMP_SHT1_EWSW[12]), .B0(n7642),
.B1(FPADDSUB_DMP_SHT2_EWSW[12]), .Y(n1269) );
AO22X1TS U3158 ( .A0(n7600), .A1(FPADDSUB_DMP_SFG[26]), .B0(n7088), .B1(
FPADDSUB_DMP_exp_NRM_EW[3]), .Y(n1441) );
AO22X1TS U3159 ( .A0(n7648), .A1(FPADDSUB_DMP_SHT1_EWSW[30]), .B0(n7642),
.B1(FPADDSUB_DMP_SHT2_EWSW[30]), .Y(n1423) );
OAI211X4TS U3160 ( .A0(n2202), .A1(n8350), .B0(n8349), .C0(n5879), .Y(n7398)
);
AO22X1TS U3161 ( .A0(n7648), .A1(FPADDSUB_OP_FLAG_SHT1), .B0(n7663), .B1(
FPADDSUB_OP_FLAG_SHT2), .Y(n1355) );
AO22X1TS U3162 ( .A0(n7089), .A1(FPADDSUB_SIGN_FLAG_SFG), .B0(n7599), .B1(
FPADDSUB_SIGN_FLAG_NRM), .Y(n1360) );
AO22X1TS U3163 ( .A0(n7089), .A1(FPADDSUB_DMP_SFG[23]), .B0(n7088), .B1(
FPADDSUB_DMP_exp_NRM_EW[0]), .Y(n1456) );
OAI211X4TS U3164 ( .A0(n2201), .A1(n8316), .B0(n8315), .C0(n5999), .Y(n7576)
);
AO22X1TS U3165 ( .A0(n7342), .A1(result_add_subt[2]), .B0(n7339), .B1(
FPSENCOS_d_ff_Yn[2]), .Y(n2069) );
AO22X1TS U3166 ( .A0(n8643), .A1(n8523), .B0(n8644), .B1(n6854), .Y(n2150)
);
AND2X2TS U3167 ( .A(n6651), .B(n5708), .Y(n8637) );
NAND2X4TS U3168 ( .A(n6602), .B(n5708), .Y(n7452) );
AO22X1TS U3169 ( .A0(n7342), .A1(result_add_subt[1]), .B0(n7339), .B1(
FPSENCOS_d_ff_Yn[1]), .Y(n2072) );
OAI211X4TS U3170 ( .A0(n2202), .A1(n8346), .B0(n8345), .C0(n5875), .Y(n7395)
);
INVX4TS U3171 ( .A(n2403), .Y(n7084) );
INVX4TS U3172 ( .A(n2335), .Y(n2373) );
AO22X1TS U3173 ( .A0(n7664), .A1(FPADDSUB_DMP_SHT1_EWSW[19]), .B0(n7939),
.B1(FPADDSUB_DMP_SHT2_EWSW[19]), .Y(n1225) );
AO22X1TS U3174 ( .A0(n7664), .A1(FPADDSUB_DMP_SHT1_EWSW[20]), .B0(n7658),
.B1(FPADDSUB_DMP_SHT2_EWSW[20]), .Y(n1229) );
OAI211X2TS U3175 ( .A0(n2260), .A1(n8334), .B0(n8333), .C0(n5908), .Y(n7378)
);
AO22X1TS U3176 ( .A0(n7664), .A1(FPADDSUB_DMP_SHT1_EWSW[17]), .B0(n7939),
.B1(FPADDSUB_DMP_SHT2_EWSW[17]), .Y(n1233) );
OAI211X4TS U3177 ( .A0(n2260), .A1(n8400), .B0(n8399), .C0(n5953), .Y(n7638)
);
AO22X1TS U3178 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[4]), .B0(
FPADDSUB_DMP_SHT2_EWSW[4]), .B1(n7939), .Y(n7917) );
AO22X1TS U3179 ( .A0(n7648), .A1(FPADDSUB_SIGN_FLAG_SHT1), .B0(n7663), .B1(
FPADDSUB_SIGN_FLAG_SHT2), .Y(n1362) );
AO22X1TS U3180 ( .A0(n7648), .A1(FPADDSUB_DMP_SHT1_EWSW[13]), .B0(n7939),
.B1(FPADDSUB_DMP_SHT2_EWSW[13]), .Y(n1245) );
AO22X1TS U3181 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[6]), .B0(
FPADDSUB_DMP_SHT2_EWSW[6]), .B1(n7663), .Y(n7918) );
AO22X1TS U3182 ( .A0(n7664), .A1(FPADDSUB_DMP_SHT1_EWSW[18]), .B0(n7663),
.B1(FPADDSUB_DMP_SHT2_EWSW[18]), .Y(n1217) );
AO22X1TS U3183 ( .A0(n7600), .A1(FPADDSUB_DMP_SFG[25]), .B0(n7088), .B1(
FPADDSUB_DMP_exp_NRM_EW[2]), .Y(n1446) );
AO22X1TS U3184 ( .A0(n7089), .A1(FPADDSUB_DMP_SFG[24]), .B0(n7088), .B1(
FPADDSUB_DMP_exp_NRM_EW[1]), .Y(n1451) );
AO22X1TS U3185 ( .A0(busy), .A1(FPADDSUB_DMP_SHT1_EWSW[25]), .B0(n7658),
.B1(FPADDSUB_DMP_SHT2_EWSW[25]), .Y(n1448) );
AO22X1TS U3186 ( .A0(n7664), .A1(FPADDSUB_DMP_SHT1_EWSW[21]), .B0(n7939),
.B1(FPADDSUB_DMP_SHT2_EWSW[21]), .Y(n1221) );
NOR2X1TS U3187 ( .A(n2297), .B(n2342), .Y(n7265) );
INVX4TS U3188 ( .A(n7548), .Y(n7557) );
INVX2TS U3189 ( .A(n3878), .Y(n2539) );
INVX2TS U3190 ( .A(FPMULT_Op_MX[20]), .Y(n2771) );
INVX4TS U3191 ( .A(n7548), .Y(n7629) );
NOR2X4TS U3192 ( .A(n3232), .B(n2320), .Y(n3282) );
INVX4TS U3193 ( .A(n7548), .Y(n7622) );
AND2X4TS U3194 ( .A(n7732), .B(DP_OP_496J2_122_3540_n1120), .Y(n3908) );
AO22XLTS U3195 ( .A0(operation[2]), .A1(underflow_flag_mult), .B0(n7287),
.B1(underflow_flag_addsubt), .Y(underflow_flag) );
NAND3X1TS U3196 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n8642),
.C(n7795), .Y(n7288) );
INVX4TS U3197 ( .A(n7798), .Y(n7303) );
INVX1TS U3198 ( .A(DP_OP_496J2_122_3540_n1514), .Y(n7467) );
INVX8TS U3199 ( .A(DP_OP_496J2_122_3540_n1472), .Y(n4255) );
CLKMX2X2TS U3200 ( .A(FPMULT_Op_MX[30]), .B(FPMULT_exp_oper_result[7]), .S0(
FPMULT_FSM_selector_A), .Y(n6979) );
CLKMX2X2TS U3201 ( .A(FPMULT_Op_MX[29]), .B(FPMULT_exp_oper_result[6]), .S0(
FPMULT_FSM_selector_A), .Y(n6957) );
CLKMX2X2TS U3202 ( .A(FPMULT_Op_MX[28]), .B(FPMULT_exp_oper_result[5]), .S0(
FPMULT_FSM_selector_A), .Y(n6960) );
CLKMX2X2TS U3203 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_exp_oper_result[4]), .S0(
FPMULT_FSM_selector_A), .Y(n6964) );
OR2X2TS U3204 ( .A(FPADDSUB_DMP_SFG[16]), .B(FPADDSUB_DmP_mant_SFG_SWR[18]),
.Y(n6158) );
OR2X2TS U3205 ( .A(FPADDSUB_DMP_SFG[14]), .B(FPADDSUB_DmP_mant_SFG_SWR[16]),
.Y(n5867) );
INVX4TS U3206 ( .A(add_x_69_n201), .Y(n5004) );
MX2X2TS U3207 ( .A(n6253), .B(FPMULT_P_Sgf[20]), .S0(n7216), .Y(n1573) );
NAND2X4TS U3208 ( .A(n2505), .B(n2504), .Y(n5440) );
NAND2X4TS U3209 ( .A(n5741), .B(n3122), .Y(n3121) );
XNOR2X2TS U3210 ( .A(n6217), .B(n6216), .Y(n6218) );
NAND2X6TS U3211 ( .A(n3063), .B(n5324), .Y(n2510) );
OR2X2TS U3212 ( .A(n5667), .B(n3192), .Y(n5669) );
CLKMX2X2TS U3213 ( .A(n7239), .B(FPMULT_P_Sgf[16]), .S0(n8525), .Y(n1569) );
NAND2X4TS U3214 ( .A(n5481), .B(n5482), .Y(n6249) );
NAND2X6TS U3215 ( .A(n2926), .B(n5727), .Y(n2568) );
CLKMX2X2TS U3216 ( .A(n7236), .B(FPMULT_P_Sgf[15]), .S0(n8524), .Y(n1568) );
NAND2X4TS U3217 ( .A(n2503), .B(n4901), .Y(n2502) );
INVX8TS U3218 ( .A(n5161), .Y(add_x_69_n59) );
NOR2X1TS U3219 ( .A(n5723), .B(n5722), .Y(add_x_69_n85) );
NAND2X4TS U3220 ( .A(n5718), .B(n4903), .Y(n2524) );
CLKMX2X2TS U3221 ( .A(n7227), .B(FPMULT_P_Sgf[14]), .S0(n8525), .Y(n1567) );
INVX8TS U3222 ( .A(n4902), .Y(n5718) );
INVX6TS U3223 ( .A(n5719), .Y(n5300) );
INVX2TS U3224 ( .A(n3171), .Y(add_x_69_n113) );
NAND2X2TS U3225 ( .A(n3712), .B(n5154), .Y(n3713) );
BUFX16TS U3226 ( .A(n2830), .Y(n2823) );
NAND3X4TS U3227 ( .A(n2318), .B(n2972), .C(n3740), .Y(n2971) );
NAND3X6TS U3228 ( .A(n2847), .B(n2846), .C(n4950), .Y(n2845) );
NAND2X6TS U3229 ( .A(n3560), .B(n3559), .Y(n3740) );
NAND2X6TS U3230 ( .A(n5237), .B(n5236), .Y(n5328) );
NAND3X4TS U3231 ( .A(n2827), .B(n2826), .C(n5100), .Y(n2527) );
INVX3TS U3232 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[11]), .Y(n4878) );
INVX2TS U3233 ( .A(n5592), .Y(n5585) );
INVX4TS U3234 ( .A(n3718), .Y(n2236) );
NAND2X4TS U3235 ( .A(n2989), .B(n2988), .Y(n5409) );
NOR2X6TS U3236 ( .A(n5428), .B(n5427), .Y(n5565) );
NAND2X4TS U3237 ( .A(n4644), .B(n4642), .Y(n2715) );
INVX4TS U3238 ( .A(n4905), .Y(n2583) );
NAND2X4TS U3239 ( .A(n2763), .B(n2753), .Y(n2752) );
XNOR2X1TS U3240 ( .A(n5637), .B(n5636), .Y(n5649) );
ADDFHX2TS U3241 ( .A(n5412), .B(n5411), .CI(n5410), .CO(n5428), .S(n5353) );
OAI21X1TS U3242 ( .A0(n5660), .A1(n5659), .B0(n5658), .Y(n5666) );
ADDFHX2TS U3243 ( .A(n5426), .B(n5425), .CI(n5424), .CO(n5567), .S(n5411) );
AO22X1TS U3244 ( .A0(n7091), .A1(n6371), .B0(FPADDSUB_ADD_OVRFLW_NRM), .B1(
n7599), .Y(n1353) );
NOR2X2TS U3245 ( .A(n1318), .B(n1319), .Y(n8414) );
AND2X4TS U3246 ( .A(n3660), .B(n3695), .Y(n3652) );
OAI2BB1X2TS U3247 ( .A0N(n6599), .A1N(n6108), .B0(n6107), .Y(n1317) );
INVX2TS U3248 ( .A(n7209), .Y(n4864) );
NAND2X4TS U3249 ( .A(n2753), .B(n3083), .Y(n2751) );
ADDFHX2TS U3250 ( .A(n5247), .B(n5246), .CI(n5245), .CO(n5352), .S(n5244) );
NOR2X1TS U3251 ( .A(n5571), .B(n2354), .Y(n5573) );
NOR2X1TS U3252 ( .A(n6858), .B(n8713), .Y(n8752) );
CLKMX2X2TS U3253 ( .A(n6909), .B(FPMULT_Add_result[21]), .S0(n6943), .Y(
n1603) );
NAND2X4TS U3254 ( .A(n2803), .B(n2802), .Y(n4824) );
INVX4TS U3255 ( .A(n2412), .Y(n2374) );
XOR2X1TS U3256 ( .A(n6113), .B(n6112), .Y(n6118) );
OAI21X1TS U3257 ( .A0(n5654), .A1(n5653), .B0(n5652), .Y(n5655) );
ADDFHX2TS U3258 ( .A(n5257), .B(n5256), .CI(n5255), .CO(n5336), .S(n5243) );
CLKMX2X2TS U3259 ( .A(n6911), .B(FPMULT_Add_result[20]), .S0(n6943), .Y(
n1604) );
OAI211X1TS U3260 ( .A0(n6568), .A1(n7548), .B0(n6816), .C0(n6567), .Y(n1473)
);
CLKMX2X2TS U3261 ( .A(n6913), .B(FPMULT_Add_result[19]), .S0(n6921), .Y(
n1605) );
AOI2BB2X1TS U3262 ( .B0(n8523), .B1(n7597), .A0N(FPADDSUB_SIGN_FLAG_EXP),
.A1N(n8523), .Y(n1364) );
ADDHX2TS U3263 ( .A(FPMULT_Sgf_normalized_result[20]), .B(n6910), .CO(n6908),
.S(n6911) );
NAND2X1TS U3264 ( .A(n3064), .B(n5272), .Y(n4948) );
INVX4TS U3265 ( .A(n5549), .Y(n4925) );
NOR2X1TS U3266 ( .A(n6600), .B(n1336), .Y(n8293) );
OAI21X1TS U3267 ( .A0(n8612), .A1(n2343), .B0(n6809), .Y(n1358) );
INVX2TS U3268 ( .A(n5604), .Y(n5219) );
OAI21X1TS U3269 ( .A0(n6808), .A1(FPADDSUB_SIGN_FLAG_SHT1SHT2), .B0(n7521),
.Y(n6809) );
OAI21X1TS U3270 ( .A0(n6684), .A1(n6832), .B0(n6672), .Y(n2079) );
AO21X1TS U3271 ( .A0(underflow_flag_addsubt), .A1(n7548), .B0(n7519), .Y(
n1414) );
OAI211X2TS U3272 ( .A0(n6071), .A1(n7857), .B0(n6070), .C0(n6691), .Y(n7092)
);
AOI2BB1X1TS U3273 ( .A0N(n7629), .A1N(overflow_flag_addsubt), .B0(n7521),
.Y(n1413) );
AND2X2TS U3274 ( .A(n3751), .B(n5273), .Y(n4901) );
AO22X1TS U3275 ( .A0(n7521), .A1(FPADDSUB_exp_rslt_NRM2_EW1[7]), .B0(
result_add_subt[30]), .B1(n7548), .Y(n1468) );
INVX2TS U3276 ( .A(n2766), .Y(n3291) );
AO21X1TS U3277 ( .A0(FPMULT_Sgf_normalized_result[23]), .A1(n6539), .B0(
n6906), .Y(n1625) );
XOR2X1TS U3278 ( .A(n6132), .B(n6131), .Y(n6137) );
OAI21X1TS U3279 ( .A0(n2296), .A1(n6684), .B0(n6683), .Y(n1320) );
OAI21X1TS U3280 ( .A0(n6702), .A1(n8526), .B0(n6700), .Y(n1324) );
OAI21X1TS U3281 ( .A0(n6702), .A1(n6840), .B0(n6701), .Y(n2078) );
ADDFHX2TS U3282 ( .A(n4020), .B(n4019), .CI(n4018), .CO(n4034), .S(n4032) );
OAI2BB1X2TS U3283 ( .A0N(n3505), .A1N(n3046), .B0(n3494), .Y(n3045) );
CLKMX2X2TS U3284 ( .A(FPMULT_exp_oper_result[7]), .B(n7103), .S0(n6981), .Y(
n1542) );
NAND2BX2TS U3285 ( .AN(n5418), .B(n4632), .Y(n5575) );
INVX3TS U3286 ( .A(n5275), .Y(n4051) );
NAND3BX1TS U3287 ( .AN(n7103), .B(n7480), .C(n7102), .Y(n7104) );
ADDFHX2TS U3288 ( .A(n5178), .B(n5177), .CI(n5176), .CO(n5200), .S(n5185) );
AOI211X1TS U3289 ( .A0(n2489), .A1(n6068), .B0(n6067), .C0(n6678), .Y(n6070)
);
AO21X1TS U3290 ( .A0(FPADDSUB_LZD_output_NRM2_EW[0]), .A1(n8526), .B0(n7093),
.Y(n1316) );
NOR2X1TS U3291 ( .A(n6649), .B(n6892), .Y(n6650) );
XOR2X1TS U3292 ( .A(n6151), .B(n6150), .Y(n6156) );
OAI21X1TS U3293 ( .A0(n5618), .A1(n5396), .B0(n5398), .Y(n5160) );
OAI21X1TS U3294 ( .A0(n5618), .A1(n5617), .B0(n5556), .Y(n5558) );
NAND2BX1TS U3295 ( .AN(n6649), .B(n6892), .Y(n6621) );
NAND4BX1TS U3296 ( .AN(n7101), .B(n7100), .C(n7099), .D(n7098), .Y(n7102) );
NAND2X4TS U3297 ( .A(n3387), .B(n3386), .Y(n3490) );
ADDFHX2TS U3298 ( .A(n3404), .B(n3403), .CI(n3402), .CO(n3457), .S(n3426) );
CLKMX2X2TS U3299 ( .A(FPMULT_exp_oper_result[6]), .B(n7100), .S0(n6981), .Y(
n1543) );
INVX12TS U3300 ( .A(n2353), .Y(n5345) );
ADDFHX2TS U3301 ( .A(n4631), .B(n4630), .CI(n4629), .CO(n4632), .S(n5262) );
NOR2BX2TS U3302 ( .AN(n4108), .B(n2353), .Y(n4920) );
NOR2X1TS U3303 ( .A(n6763), .B(n7284), .Y(n6040) );
INVX3TS U3304 ( .A(n3274), .Y(n3474) );
OAI21X1TS U3305 ( .A0(n6727), .A1(n6778), .B0(n6726), .Y(n1697) );
AO22X1TS U3306 ( .A0(FPSENCOS_d_ff2_Y[2]), .A1(n7406), .B0(
FPSENCOS_d_ff_Yn[2]), .B1(n7405), .Y(n1905) );
AO22X1TS U3307 ( .A0(FPMULT_Sgf_normalized_result[11]), .A1(n7482), .B0(
mult_result[11]), .B1(n7483), .Y(n1504) );
AO22X1TS U3308 ( .A0(FPSENCOS_d_ff2_X[22]), .A1(n7406), .B0(
FPSENCOS_d_ff_Xn[22]), .B1(n7405), .Y(n1963) );
AO22X1TS U3309 ( .A0(FPSENCOS_d_ff2_Y[19]), .A1(n7415), .B0(
FPSENCOS_d_ff_Yn[19]), .B1(n7414), .Y(n1871) );
AO22X1TS U3310 ( .A0(FPMULT_Sgf_normalized_result[10]), .A1(n7482), .B0(
mult_result[10]), .B1(n7483), .Y(n1505) );
OAI21X1TS U3311 ( .A0(n6604), .A1(n6482), .B0(n6481), .Y(n6483) );
AO22X1TS U3312 ( .A0(FPMULT_Sgf_normalized_result[9]), .A1(n7482), .B0(
mult_result[9]), .B1(n7493), .Y(n1506) );
AO22X1TS U3313 ( .A0(FPSENCOS_d_ff2_Y[26]), .A1(n7417), .B0(
FPSENCOS_d_ff_Yn[26]), .B1(n7416), .Y(n1860) );
AO22X1TS U3314 ( .A0(FPSENCOS_d_ff2_Y[23]), .A1(n7415), .B0(
FPSENCOS_d_ff_Yn[23]), .B1(n7414), .Y(n1863) );
NAND2X6TS U3315 ( .A(n4093), .B(n3915), .Y(n4094) );
AO22X1TS U3316 ( .A0(FPSENCOS_d_ff2_Y[27]), .A1(n7417), .B0(
FPSENCOS_d_ff_Yn[27]), .B1(n7416), .Y(n1859) );
AO22X1TS U3317 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n7417), .B0(
FPSENCOS_d_ff_Yn[29]), .B1(n7416), .Y(n1857) );
AO22X1TS U3318 ( .A0(FPSENCOS_d_ff2_Y[25]), .A1(n7415), .B0(
FPSENCOS_d_ff_Yn[25]), .B1(n7414), .Y(n1861) );
AO22X1TS U3319 ( .A0(FPMULT_Sgf_normalized_result[8]), .A1(n7482), .B0(
mult_result[8]), .B1(n7483), .Y(n1507) );
AO22X1TS U3320 ( .A0(FPSENCOS_d_ff2_Y[24]), .A1(n7415), .B0(
FPSENCOS_d_ff_Yn[24]), .B1(n7414), .Y(n1862) );
AO22X1TS U3321 ( .A0(FPSENCOS_d_ff2_Y[18]), .A1(n7415), .B0(
FPSENCOS_d_ff_Yn[18]), .B1(n7414), .Y(n1873) );
AO21X1TS U3322 ( .A0(FPADDSUB_DmP_mant_SFG_SWR[25]), .A1(n7515), .B0(n6185),
.Y(n1182) );
AO22X1TS U3323 ( .A0(FPMULT_Sgf_normalized_result[7]), .A1(n7482), .B0(
mult_result[7]), .B1(n7493), .Y(n1508) );
AO22X1TS U3324 ( .A0(FPMULT_Sgf_normalized_result[20]), .A1(n7484), .B0(
mult_result[20]), .B1(n7489), .Y(n1495) );
AO22X1TS U3325 ( .A0(FPSENCOS_d_ff2_Y[10]), .A1(n7412), .B0(
FPSENCOS_d_ff_Yn[10]), .B1(n7411), .Y(n1889) );
AO22X1TS U3326 ( .A0(FPMULT_Sgf_normalized_result[21]), .A1(n7484), .B0(
mult_result[21]), .B1(n7489), .Y(n1494) );
AO22X1TS U3327 ( .A0(FPSENCOS_d_ff2_Y[1]), .A1(n7406), .B0(
FPSENCOS_d_ff_Yn[1]), .B1(n7405), .Y(n1907) );
AO22X1TS U3328 ( .A0(FPMULT_Sgf_normalized_result[6]), .A1(n7482), .B0(
mult_result[6]), .B1(n7493), .Y(n1509) );
OAI21X1TS U3329 ( .A0(n5703), .A1(n7691), .B0(n5704), .Y(n7693) );
INVX4TS U3330 ( .A(n2512), .Y(n2237) );
AO22X1TS U3331 ( .A0(FPMULT_Sgf_normalized_result[22]), .A1(n7484), .B0(
mult_result[22]), .B1(n7489), .Y(n1493) );
AO22X1TS U3332 ( .A0(FPSENCOS_d_ff2_Y[8]), .A1(n7412), .B0(
FPSENCOS_d_ff_Yn[8]), .B1(n7411), .Y(n1893) );
AO22X1TS U3333 ( .A0(FPSENCOS_d_ff2_X[0]), .A1(n7417), .B0(
FPSENCOS_d_ff_Xn[0]), .B1(n7416), .Y(n2007) );
CLKAND2X2TS U3334 ( .A(n3498), .B(n3506), .Y(n2308) );
AO22X1TS U3335 ( .A0(FPMULT_Sgf_normalized_result[15]), .A1(n7482), .B0(
mult_result[15]), .B1(n7483), .Y(n1500) );
AO22X1TS U3336 ( .A0(FPSENCOS_d_ff2_Y[4]), .A1(n7406), .B0(
FPSENCOS_d_ff_Yn[4]), .B1(n7405), .Y(n1901) );
AO22X1TS U3337 ( .A0(FPSENCOS_d_ff2_Y[21]), .A1(n7415), .B0(
FPSENCOS_d_ff_Yn[21]), .B1(n7414), .Y(n1867) );
AO22X1TS U3338 ( .A0(FPSENCOS_d_ff2_X[4]), .A1(n7417), .B0(
FPSENCOS_d_ff_Xn[4]), .B1(n7416), .Y(n1999) );
OAI21X1TS U3339 ( .A0(n6604), .A1(n6471), .B0(n6470), .Y(n6472) );
AO22X1TS U3340 ( .A0(FPSENCOS_d_ff2_X[23]), .A1(n7406), .B0(
FPSENCOS_d_ff_Xn[23]), .B1(n7405), .Y(n1961) );
AO22X1TS U3341 ( .A0(FPSENCOS_d_ff2_X[21]), .A1(n7367), .B0(
FPSENCOS_d_ff_Xn[21]), .B1(n7405), .Y(n1965) );
AO22X1TS U3342 ( .A0(FPSENCOS_d_ff2_Y[14]), .A1(n7412), .B0(
FPSENCOS_d_ff_Yn[14]), .B1(n7411), .Y(n1881) );
ADDFHX2TS U3343 ( .A(n3369), .B(n3368), .CI(n3367), .CO(n3380), .S(n3378) );
AO22X1TS U3344 ( .A0(n7512), .A1(n7506), .B0(n7665), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[4]), .Y(n1476) );
AO22X1TS U3345 ( .A0(FPMULT_Sgf_normalized_result[16]), .A1(n7484), .B0(
mult_result[16]), .B1(n7483), .Y(n1499) );
AO22X1TS U3346 ( .A0(FPMULT_Sgf_normalized_result[14]), .A1(n7482), .B0(
mult_result[14]), .B1(n7483), .Y(n1501) );
AO22X1TS U3347 ( .A0(FPSENCOS_d_ff2_Y[30]), .A1(n7417), .B0(
FPSENCOS_d_ff_Yn[30]), .B1(n7416), .Y(n1856) );
AO22X1TS U3348 ( .A0(FPMULT_Sgf_normalized_result[17]), .A1(n7484), .B0(
mult_result[17]), .B1(n7483), .Y(n1498) );
AO22X1TS U3349 ( .A0(FPMULT_Sgf_normalized_result[13]), .A1(n7482), .B0(
mult_result[13]), .B1(n7483), .Y(n1502) );
AO22X1TS U3350 ( .A0(FPSENCOS_d_ff2_Y[17]), .A1(n7415), .B0(
FPSENCOS_d_ff_Yn[17]), .B1(n7414), .Y(n1875) );
NOR2X1TS U3351 ( .A(n2435), .B(DP_OP_497J2_123_1725_n324), .Y(n3698) );
AO22X1TS U3352 ( .A0(FPSENCOS_d_ff_Xn[31]), .A1(n7416), .B0(
FPSENCOS_d_ff2_X[31]), .B1(n7367), .Y(n1945) );
AO22X1TS U3353 ( .A0(FPSENCOS_d_ff2_Y[16]), .A1(n7415), .B0(
FPSENCOS_d_ff_Yn[16]), .B1(n7414), .Y(n1877) );
AO22X1TS U3354 ( .A0(FPMULT_Sgf_normalized_result[18]), .A1(n7484), .B0(
mult_result[18]), .B1(n7483), .Y(n1497) );
AO22X1TS U3355 ( .A0(FPSENCOS_d_ff2_Y[13]), .A1(n7412), .B0(
FPSENCOS_d_ff_Yn[13]), .B1(n7411), .Y(n1883) );
AO22X1TS U3356 ( .A0(FPSENCOS_d_ff2_Y[3]), .A1(n7406), .B0(
FPSENCOS_d_ff_Yn[3]), .B1(n7405), .Y(n1903) );
OAI21X1TS U3357 ( .A0(n6604), .A1(n6514), .B0(n6513), .Y(n6515) );
AO22X1TS U3358 ( .A0(FPSENCOS_d_ff2_Y[20]), .A1(n7415), .B0(
FPSENCOS_d_ff_Yn[20]), .B1(n7414), .Y(n1869) );
OAI21X1TS U3359 ( .A0(n6604), .A1(n6504), .B0(n6503), .Y(n6505) );
AO22X1TS U3360 ( .A0(FPMULT_Sgf_normalized_result[19]), .A1(n7484), .B0(
mult_result[19]), .B1(n7489), .Y(n1496) );
AO22X1TS U3361 ( .A0(FPSENCOS_d_ff2_X[30]), .A1(n7406), .B0(
FPSENCOS_d_ff_Xn[30]), .B1(n7405), .Y(n1954) );
AO22X1TS U3362 ( .A0(FPSENCOS_d_ff2_Y[6]), .A1(n7412), .B0(
FPSENCOS_d_ff_Yn[6]), .B1(n7411), .Y(n1897) );
AO22X1TS U3363 ( .A0(FPSENCOS_d_ff2_Y[9]), .A1(n7412), .B0(
FPSENCOS_d_ff_Yn[9]), .B1(n7411), .Y(n1891) );
AO22X1TS U3364 ( .A0(FPMULT_Sgf_normalized_result[12]), .A1(n7482), .B0(
mult_result[12]), .B1(n7483), .Y(n1503) );
AO22X1TS U3365 ( .A0(n7484), .A1(FPMULT_Sgf_normalized_result[2]), .B0(
mult_result[2]), .B1(n7489), .Y(n1513) );
AO22X1TS U3366 ( .A0(FPSENCOS_d_ff2_Y[5]), .A1(n7406), .B0(
FPSENCOS_d_ff_Yn[5]), .B1(n7405), .Y(n1899) );
OAI21X1TS U3367 ( .A0(n5082), .A1(n5111), .B0(n5113), .Y(n5087) );
AO22X1TS U3368 ( .A0(FPSENCOS_d_ff2_Y[22]), .A1(n7415), .B0(
FPSENCOS_d_ff_Yn[22]), .B1(n7414), .Y(n1865) );
NAND2X2TS U3369 ( .A(n4191), .B(n4190), .Y(n4192) );
AO22X1TS U3370 ( .A0(n7355), .A1(n6560), .B0(n7357), .B1(
FPSENCOS_d_ff3_sh_y_out[30]), .Y(n1848) );
AO22X1TS U3371 ( .A0(FPMULT_Sgf_normalized_result[3]), .A1(n7481), .B0(
mult_result[3]), .B1(n7489), .Y(n1512) );
AO22X1TS U3372 ( .A0(n7484), .A1(FPMULT_Sgf_normalized_result[1]), .B0(
mult_result[1]), .B1(n7489), .Y(n1514) );
AO22X1TS U3373 ( .A0(FPSENCOS_d_ff2_Y[0]), .A1(n7406), .B0(
FPSENCOS_d_ff_Yn[0]), .B1(n7405), .Y(n1909) );
AO22X1TS U3374 ( .A0(FPSENCOS_d_ff2_Y[15]), .A1(n7412), .B0(
FPSENCOS_d_ff_Yn[15]), .B1(n7411), .Y(n1879) );
OAI21X1TS U3375 ( .A0(n7434), .A1(n6570), .B0(n6855), .Y(n2081) );
AO22X1TS U3376 ( .A0(FPMULT_Sgf_normalized_result[4]), .A1(n7481), .B0(
mult_result[4]), .B1(n7493), .Y(n1511) );
AO22X1TS U3377 ( .A0(FPSENCOS_d_ff2_Y[28]), .A1(n7417), .B0(
FPSENCOS_d_ff_Yn[28]), .B1(n7416), .Y(n1858) );
AO22X1TS U3378 ( .A0(FPSENCOS_d_ff2_Y[11]), .A1(n7412), .B0(
FPSENCOS_d_ff_Yn[11]), .B1(n7411), .Y(n1887) );
AO22X1TS U3379 ( .A0(FPMULT_Sgf_normalized_result[5]), .A1(n7481), .B0(
mult_result[5]), .B1(n7493), .Y(n1510) );
XOR2X1TS U3380 ( .A(n6074), .B(n5864), .Y(n5872) );
AO22X1TS U3381 ( .A0(FPSENCOS_d_ff2_Y[12]), .A1(n7412), .B0(
FPSENCOS_d_ff_Yn[12]), .B1(n7411), .Y(n1885) );
AO22X1TS U3382 ( .A0(n7484), .A1(FPMULT_Sgf_normalized_result[0]), .B0(
mult_result[0]), .B1(n7489), .Y(n1515) );
AO22X1TS U3383 ( .A0(FPSENCOS_d_ff2_Y[7]), .A1(n7412), .B0(
FPSENCOS_d_ff_Yn[7]), .B1(n7411), .Y(n1895) );
AO22X1TS U3384 ( .A0(FPSENCOS_d_ff2_X[11]), .A1(n7367), .B0(
FPSENCOS_d_ff_Xn[11]), .B1(n2407), .Y(n1985) );
OAI21X1TS U3385 ( .A0(n7321), .A1(n7322), .B0(n6633), .Y(n2135) );
OAI21X1TS U3386 ( .A0(n7319), .A1(n7327), .B0(n6637), .Y(n2119) );
AO22X1TS U3387 ( .A0(FPSENCOS_d_ff2_X[15]), .A1(n7406), .B0(
FPSENCOS_d_ff_Xn[15]), .B1(n2407), .Y(n1977) );
AO22X1TS U3388 ( .A0(n7332), .A1(FPSENCOS_d_ff1_Z[2]), .B0(n7331), .B1(
Data_1[2]), .Y(n2112) );
NAND2BX1TS U3389 ( .AN(n7316), .B(n7315), .Y(n2125) );
OAI21X1TS U3390 ( .A0(n7713), .A1(n5709), .B0(n5710), .Y(n7718) );
OAI21X1TS U3391 ( .A0(n3508), .A1(n3507), .B0(n3506), .Y(n3509) );
OAI21X1TS U3392 ( .A0(n2361), .A1(n7320), .B0(n6655), .Y(n2118) );
OAI21X1TS U3393 ( .A0(n5504), .A1(n5503), .B0(n5502), .Y(n5505) );
AO22X1TS U3394 ( .A0(n7428), .A1(n6550), .B0(n7357), .B1(
FPSENCOS_d_ff3_sh_y_out[28]), .Y(n1850) );
AO22X1TS U3395 ( .A0(n7444), .A1(n7366), .B0(n7407), .B1(
FPSENCOS_d_ff3_sh_x_out[30]), .Y(n1946) );
CLKMX2X2TS U3396 ( .A(FPMULT_exp_oper_result[0]), .B(n7094), .S0(n6981), .Y(
n1549) );
NOR2X1TS U3397 ( .A(n7696), .B(n7690), .Y(n7695) );
OAI21X1TS U3398 ( .A0(n7329), .A1(n6636), .B0(n6635), .Y(n2133) );
OAI21X1TS U3399 ( .A0(n7330), .A1(intadd_10_CI), .B0(n6644), .Y(n1953) );
INVX2TS U3400 ( .A(n4574), .Y(n4575) );
OAI21X1TS U3401 ( .A0(FPSENCOS_cont_iter_out[3]), .A1(n7329), .B0(n6639),
.Y(n2116) );
AOI2BB2X1TS U3402 ( .B0(FPSENCOS_d_ff2_Y[30]), .B1(n7420), .A0N(n7420),
.A1N(FPSENCOS_d_ff2_Y[30]), .Y(n6560) );
OAI21X1TS U3403 ( .A0(n7330), .A1(intadd_9_CI), .B0(n6642), .Y(n1855) );
AO22X1TS U3404 ( .A0(n7332), .A1(FPSENCOS_d_ff1_Z[7]), .B0(n7331), .B1(
Data_1[7]), .Y(n2107) );
AO22X1TS U3405 ( .A0(n7332), .A1(FPSENCOS_d_ff1_Z[8]), .B0(n7331), .B1(
Data_1[8]), .Y(n2106) );
NOR2X4TS U3406 ( .A(n3728), .B(n3250), .Y(n3252) );
AO22X1TS U3407 ( .A0(n7336), .A1(FPSENCOS_d_ff1_Z[28]), .B0(n7337), .B1(
Data_1[28]), .Y(n2086) );
AO22X1TS U3408 ( .A0(n7338), .A1(FPSENCOS_d_ff1_Z[13]), .B0(n7308), .B1(
Data_1[13]), .Y(n2101) );
AO22X1TS U3409 ( .A0(n7336), .A1(FPSENCOS_d_ff1_Z[27]), .B0(n7337), .B1(
Data_1[27]), .Y(n2087) );
OAI21X1TS U3410 ( .A0(n6604), .A1(n6532), .B0(n6531), .Y(n6533) );
AO22X1TS U3411 ( .A0(n7338), .A1(FPSENCOS_d_ff1_Z[14]), .B0(n7334), .B1(
Data_1[14]), .Y(n2100) );
AO22X1TS U3412 ( .A0(n7338), .A1(FPSENCOS_d_ff1_Z[15]), .B0(n7334), .B1(
Data_1[15]), .Y(n2099) );
AO22X1TS U3413 ( .A0(n7336), .A1(FPSENCOS_d_ff1_Z[26]), .B0(n7335), .B1(
Data_1[26]), .Y(n2088) );
AO22X1TS U3414 ( .A0(n7338), .A1(FPSENCOS_d_ff1_Z[16]), .B0(n7335), .B1(
Data_1[16]), .Y(n2098) );
OR2X2TS U3415 ( .A(n7690), .B(n7689), .Y(n7691) );
OAI21X1TS U3416 ( .A0(n6604), .A1(n6523), .B0(n6522), .Y(n6524) );
AO22X1TS U3417 ( .A0(n7336), .A1(FPSENCOS_d_ff1_Z[25]), .B0(n7335), .B1(
Data_1[25]), .Y(n2089) );
AO22X1TS U3418 ( .A0(n7338), .A1(FPSENCOS_d_ff1_Z[17]), .B0(n7335), .B1(
Data_1[17]), .Y(n2097) );
AO22X1TS U3419 ( .A0(n7336), .A1(FPSENCOS_d_ff1_Z[24]), .B0(n7335), .B1(
Data_1[24]), .Y(n2090) );
AOI222X1TS U3420 ( .A0(n6755), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n6754), .B1(
FPSENCOS_d_ff_Zn[31]), .C0(n6734), .C1(FPSENCOS_d_ff1_Z[31]), .Y(n6732) );
AO22X1TS U3421 ( .A0(n7338), .A1(FPSENCOS_d_ff1_Z[18]), .B0(n7335), .B1(
Data_1[18]), .Y(n2096) );
OAI211X1TS U3422 ( .A0(n6985), .A1(n7478), .B0(n6617), .C0(n6440), .Y(n1695)
);
OAI21X1TS U3423 ( .A0(n2350), .A1(n6620), .B0(n6619), .Y(n1692) );
AO22X1TS U3424 ( .A0(n7332), .A1(FPSENCOS_d_ff1_Z[22]), .B0(n7334), .B1(
Data_1[22]), .Y(n2092) );
AO22X1TS U3425 ( .A0(n7332), .A1(FPSENCOS_d_ff1_Z[21]), .B0(n7335), .B1(
Data_1[21]), .Y(n2093) );
AO22X1TS U3426 ( .A0(n7338), .A1(FPSENCOS_d_ff1_Z[19]), .B0(n7335), .B1(
Data_1[19]), .Y(n2095) );
AO22X1TS U3427 ( .A0(n7332), .A1(FPSENCOS_d_ff1_Z[20]), .B0(n7335), .B1(
Data_1[20]), .Y(n2094) );
AO22X1TS U3428 ( .A0(n7512), .A1(n6448), .B0(n7665), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[3]), .Y(n1480) );
NAND4BX1TS U3429 ( .AN(n1644), .B(n6877), .C(n6876), .D(n6875), .Y(n8062) );
AO22X1TS U3430 ( .A0(n7332), .A1(FPSENCOS_d_ff1_Z[4]), .B0(n7331), .B1(
Data_1[4]), .Y(n2110) );
AO22X1TS U3431 ( .A0(n7338), .A1(FPSENCOS_d_ff1_Z[31]), .B0(n7337), .B1(
Data_1[31]), .Y(n2083) );
AO22X1TS U3432 ( .A0(n7338), .A1(FPSENCOS_d_ff1_Z[29]), .B0(n7337), .B1(
Data_1[29]), .Y(n2085) );
AO22X1TS U3433 ( .A0(n7332), .A1(FPSENCOS_d_ff1_Z[3]), .B0(n7331), .B1(
Data_1[3]), .Y(n2111) );
AO22X1TS U3434 ( .A0(n7332), .A1(FPSENCOS_d_ff1_Z[5]), .B0(n7331), .B1(
Data_1[5]), .Y(n2109) );
AO22X1TS U3435 ( .A0(n7338), .A1(FPSENCOS_d_ff1_Z[30]), .B0(n7337), .B1(
Data_1[30]), .Y(n2084) );
INVX8TS U3436 ( .A(n3421), .Y(n3664) );
AO22X1TS U3437 ( .A0(n7332), .A1(FPSENCOS_d_ff1_Z[6]), .B0(n7331), .B1(
Data_1[6]), .Y(n2108) );
AO22X1TS U3438 ( .A0(n7355), .A1(FPSENCOS_d_ff2_X[3]), .B0(n7353), .B1(
FPSENCOS_d_ff3_sh_x_out[3]), .Y(n2000) );
AO22X1TS U3439 ( .A0(n7428), .A1(FPSENCOS_d_ff2_Y[2]), .B0(n7407), .B1(
FPSENCOS_d_ff3_sh_y_out[2]), .Y(n1904) );
NAND2X6TS U3440 ( .A(n3067), .B(n3747), .Y(n3856) );
AO22X1TS U3441 ( .A0(n7424), .A1(FPSENCOS_d_ff2_X[7]), .B0(n7353), .B1(
FPSENCOS_d_ff3_sh_x_out[7]), .Y(n1992) );
AO22X1TS U3442 ( .A0(n7357), .A1(FPSENCOS_d_ff3_sh_x_out[21]), .B0(n7422),
.B1(FPSENCOS_d_ff2_X[21]), .Y(n1964) );
AO22X1TS U3443 ( .A0(n7424), .A1(FPSENCOS_d_ff2_X[15]), .B0(n7353), .B1(
FPSENCOS_d_ff3_sh_x_out[15]), .Y(n1976) );
AO22X1TS U3444 ( .A0(n7428), .A1(FPSENCOS_d_ff2_Y[7]), .B0(n7443), .B1(
FPSENCOS_d_ff3_sh_y_out[7]), .Y(n1894) );
INVX4TS U3445 ( .A(n4258), .Y(n2238) );
AO22X1TS U3446 ( .A0(n7361), .A1(FPSENCOS_d_ff2_Y[21]), .B0(n7427), .B1(
FPSENCOS_d_ff3_sh_y_out[21]), .Y(n1866) );
AO22X1TS U3447 ( .A0(n7444), .A1(FPSENCOS_d_ff2_Y[15]), .B0(n7427), .B1(
FPSENCOS_d_ff3_sh_y_out[15]), .Y(n1878) );
AO22X1TS U3448 ( .A0(n7354), .A1(FPSENCOS_d_ff3_sh_x_out[2]), .B0(n7410),
.B1(FPSENCOS_d_ff2_X[2]), .Y(n2002) );
NAND2X1TS U3449 ( .A(n5366), .B(n5365), .Y(n5386) );
AO22X1TS U3450 ( .A0(n7354), .A1(FPSENCOS_d_ff3_sh_x_out[0]), .B0(n7410),
.B1(FPSENCOS_d_ff2_X[0]), .Y(n2006) );
NAND3X1TS U3451 ( .A(n7279), .B(n7325), .C(n7286), .Y(n7280) );
AO22X1TS U3452 ( .A0(n7361), .A1(FPSENCOS_d_ff2_Y[18]), .B0(n7427), .B1(
FPSENCOS_d_ff3_sh_y_out[18]), .Y(n1872) );
AO22X1TS U3453 ( .A0(n7428), .A1(FPSENCOS_d_ff2_Y[31]), .B0(n7427), .B1(
FPSENCOS_d_ff3_sh_y_out[31]), .Y(n1846) );
NOR2X1TS U3454 ( .A(n7062), .B(n7029), .Y(n7020) );
AO22X1TS U3455 ( .A0(n7354), .A1(FPSENCOS_d_ff3_sh_x_out[12]), .B0(n7422),
.B1(FPSENCOS_d_ff2_X[12]), .Y(n1982) );
AO22X1TS U3456 ( .A0(n7355), .A1(FPSENCOS_d_ff2_X[22]), .B0(n7407), .B1(
FPSENCOS_d_ff3_sh_x_out[22]), .Y(n1962) );
AO22X1TS U3457 ( .A0(n7361), .A1(FPSENCOS_d_ff2_Y[22]), .B0(n7357), .B1(
FPSENCOS_d_ff3_sh_y_out[22]), .Y(n1864) );
AO22X1TS U3458 ( .A0(n7444), .A1(FPSENCOS_d_ff2_Y[0]), .B0(n7407), .B1(
FPSENCOS_d_ff3_sh_y_out[0]), .Y(n1908) );
INVX4TS U3459 ( .A(n3965), .Y(n2239) );
AO22X1TS U3460 ( .A0(n7444), .A1(FPSENCOS_d_ff2_Y[12]), .B0(n7443), .B1(
FPSENCOS_d_ff3_sh_y_out[12]), .Y(n1884) );
NOR2X1TS U3461 ( .A(n1642), .B(n1630), .Y(n7714) );
OAI21X1TS U3462 ( .A0(n7788), .A1(n6653), .B0(FPMULT_FS_Module_state_reg[3]),
.Y(n6617) );
INVX1TS U3463 ( .A(n4521), .Y(n2614) );
NOR2X1TS U3464 ( .A(n1674), .B(n1662), .Y(n7715) );
NAND2X6TS U3465 ( .A(n4026), .B(n3075), .Y(n3993) );
AO22X1TS U3466 ( .A0(n7428), .A1(FPSENCOS_d_ff2_Y[3]), .B0(n7407), .B1(
FPSENCOS_d_ff3_sh_y_out[3]), .Y(n1902) );
NOR2X1TS U3467 ( .A(n1672), .B(n1660), .Y(n7719) );
NAND4BX1TS U3468 ( .AN(FPADDSUB_exp_rslt_NRM2_EW1[4]), .B(n6562), .C(n6561),
.D(n6568), .Y(n6563) );
AO22X1TS U3469 ( .A0(n7428), .A1(FPSENCOS_d_ff2_X[31]), .B0(n7407), .B1(
FPSENCOS_d_ff3_sh_x_out[31]), .Y(n1944) );
NOR2X1TS U3470 ( .A(n1641), .B(n1629), .Y(n7721) );
AO22X1TS U3471 ( .A0(n7428), .A1(FPSENCOS_d_ff2_Y[9]), .B0(n7443), .B1(
FPSENCOS_d_ff3_sh_y_out[9]), .Y(n1890) );
AO22X1TS U3472 ( .A0(n7357), .A1(FPSENCOS_d_ff3_sh_x_out[26]), .B0(n7422),
.B1(intadd_10_SUM_2_), .Y(n1950) );
AO22X1TS U3473 ( .A0(n7357), .A1(FPSENCOS_d_ff3_sh_x_out[25]), .B0(n7422),
.B1(intadd_10_SUM_1_), .Y(n1951) );
AO22X1TS U3474 ( .A0(n7444), .A1(FPSENCOS_d_ff2_Z[31]), .B0(n7443), .B1(
FPSENCOS_d_ff3_sign_out), .Y(n1734) );
AO22X1TS U3475 ( .A0(n7333), .A1(FPSENCOS_d_ff1_Z[9]), .B0(n7334), .B1(
Data_1[9]), .Y(n2105) );
AO22X1TS U3476 ( .A0(n7357), .A1(FPSENCOS_d_ff3_sh_x_out[24]), .B0(n7422),
.B1(intadd_10_SUM_0_), .Y(n1952) );
AOI211X1TS U3477 ( .A0(FPMULT_FS_Module_state_reg[2]), .A1(n6653), .B0(n7480), .C0(n7487), .Y(n6619) );
AO22X1TS U3478 ( .A0(n7333), .A1(FPSENCOS_d_ff1_Z[10]), .B0(n7308), .B1(
Data_1[10]), .Y(n2104) );
AO22X1TS U3479 ( .A0(n7333), .A1(FPSENCOS_d_ff1_Z[11]), .B0(n7308), .B1(
Data_1[11]), .Y(n2103) );
AO22X1TS U3480 ( .A0(n7333), .A1(FPSENCOS_d_ff1_Z[12]), .B0(n7308), .B1(
Data_1[12]), .Y(n2102) );
AO22X1TS U3481 ( .A0(n7512), .A1(n6437), .B0(n7634), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[2]), .Y(n1479) );
OAI21X1TS U3482 ( .A0(n6604), .A1(n6465), .B0(n6464), .Y(n6466) );
AO22X1TS U3483 ( .A0(n7444), .A1(FPSENCOS_d_ff2_Y[11]), .B0(n7443), .B1(
FPSENCOS_d_ff3_sh_y_out[11]), .Y(n1886) );
AO22X1TS U3484 ( .A0(n7428), .A1(FPSENCOS_d_ff2_Y[4]), .B0(n7407), .B1(
FPSENCOS_d_ff3_sh_y_out[4]), .Y(n1900) );
OAI21X1TS U3485 ( .A0(n7491), .A1(underflow_flag_mult), .B0(n7490), .Y(n7492) );
AO22X1TS U3486 ( .A0(n7354), .A1(FPSENCOS_d_ff3_sh_x_out[4]), .B0(n7410),
.B1(FPSENCOS_d_ff2_X[4]), .Y(n1998) );
OAI21X1TS U3487 ( .A0(n7418), .A1(n8679), .B0(n7421), .Y(n6550) );
AO22X1TS U3488 ( .A0(n7361), .A1(intadd_9_SUM_2_), .B0(n7427), .B1(
FPSENCOS_d_ff3_sh_y_out[26]), .Y(n1852) );
AO22X1TS U3489 ( .A0(n7361), .A1(intadd_9_SUM_1_), .B0(n7427), .B1(
FPSENCOS_d_ff3_sh_y_out[25]), .Y(n1853) );
AO22X1TS U3490 ( .A0(n7361), .A1(intadd_9_SUM_0_), .B0(n7427), .B1(
FPSENCOS_d_ff3_sh_y_out[24]), .Y(n1854) );
AO22X1TS U3491 ( .A0(n7409), .A1(FPSENCOS_d_ff2_Y[6]), .B0(n7443), .B1(
FPSENCOS_d_ff3_sh_y_out[6]), .Y(n1896) );
AO22X1TS U3492 ( .A0(n7333), .A1(FPSENCOS_d_ff1_shift_region_flag_out[1]),
.B0(n7331), .B1(region_flag[1]), .Y(n2136) );
AO22X1TS U3493 ( .A0(n7354), .A1(FPSENCOS_d_ff3_sh_x_out[6]), .B0(n7410),
.B1(FPSENCOS_d_ff2_X[6]), .Y(n1994) );
NAND2BX1TS U3494 ( .AN(FPSENCOS_d_ff3_LUT_out[27]), .B(n7330), .Y(n2115) );
AO22X1TS U3495 ( .A0(n7355), .A1(FPSENCOS_d_ff2_X[17]), .B0(n7353), .B1(
FPSENCOS_d_ff3_sh_x_out[17]), .Y(n1972) );
ADDFHX2TS U3496 ( .A(n3615), .B(n3614), .CI(n3613), .CO(n3641), .S(n3598) );
AO22X1TS U3497 ( .A0(n7355), .A1(FPSENCOS_d_ff2_X[5]), .B0(n7353), .B1(
FPSENCOS_d_ff3_sh_x_out[5]), .Y(n1996) );
BUFX12TS U3498 ( .A(n2777), .Y(n3610) );
OR2X2TS U3499 ( .A(n6605), .B(n6604), .Y(n6611) );
OAI21X1TS U3500 ( .A0(n2356), .A1(n2938), .B0(n2937), .Y(n1675) );
AO22X1TS U3501 ( .A0(n7410), .A1(FPSENCOS_d_ff2_Y[13]), .B0(n7443), .B1(
FPSENCOS_d_ff3_sh_y_out[13]), .Y(n1882) );
AO22X1TS U3502 ( .A0(n7333), .A1(FPSENCOS_d_ff1_shift_region_flag_out[0]),
.B0(n7334), .B1(region_flag[0]), .Y(n2137) );
AO22X1TS U3503 ( .A0(n7354), .A1(FPSENCOS_d_ff3_sh_x_out[9]), .B0(n7410),
.B1(FPSENCOS_d_ff2_X[9]), .Y(n1988) );
INVX1TS U3504 ( .A(n1643), .Y(n6877) );
INVX1TS U3505 ( .A(n1642), .Y(n6876) );
AO22X1TS U3506 ( .A0(n7444), .A1(FPSENCOS_d_ff2_Y[5]), .B0(n7407), .B1(
FPSENCOS_d_ff3_sh_y_out[5]), .Y(n1898) );
AO22X1TS U3507 ( .A0(n7409), .A1(FPSENCOS_d_ff2_X[13]), .B0(n7353), .B1(
FPSENCOS_d_ff3_sh_x_out[13]), .Y(n1980) );
AO22X1TS U3508 ( .A0(n7354), .A1(FPSENCOS_d_ff3_sh_x_out[8]), .B0(n7410),
.B1(FPSENCOS_d_ff2_X[8]), .Y(n1990) );
AO22X1TS U3509 ( .A0(n7361), .A1(FPSENCOS_d_ff2_Y[16]), .B0(n7427), .B1(
FPSENCOS_d_ff3_sh_y_out[16]), .Y(n1876) );
AO22X1TS U3510 ( .A0(n7355), .A1(FPSENCOS_d_ff2_X[16]), .B0(n7353), .B1(
FPSENCOS_d_ff3_sh_x_out[16]), .Y(n1974) );
AO22X1TS U3511 ( .A0(n7333), .A1(FPSENCOS_d_ff1_Z[23]), .B0(n7335), .B1(
Data_1[23]), .Y(n2091) );
AO22X1TS U3512 ( .A0(n7410), .A1(FPSENCOS_d_ff2_Y[8]), .B0(n7443), .B1(
FPSENCOS_d_ff3_sh_y_out[8]), .Y(n1892) );
AO22X1TS U3513 ( .A0(n7424), .A1(n7319), .B0(n7353), .B1(
FPSENCOS_d_ff3_LUT_out[19]), .Y(n2121) );
AO22X1TS U3514 ( .A0(n7428), .A1(intadd_9_B_1_), .B0(n7357), .B1(
FPSENCOS_d_ff3_LUT_out[8]), .Y(n2127) );
OAI21X1TS U3515 ( .A0(n6601), .A1(n7285), .B0(n7330), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[4]) );
AO22X1TS U3516 ( .A0(n7333), .A1(FPSENCOS_d_ff1_Z[1]), .B0(n7331), .B1(
Data_1[1]), .Y(n2113) );
AO22X1TS U3517 ( .A0(n7354), .A1(FPSENCOS_d_ff3_sh_x_out[1]), .B0(n7410),
.B1(FPSENCOS_d_ff2_X[1]), .Y(n2004) );
ADDFHX2TS U3518 ( .A(n4447), .B(n4446), .CI(n4445), .CO(n4492), .S(n4437) );
AO22X1TS U3519 ( .A0(n7333), .A1(FPSENCOS_d_ff1_Z[0]), .B0(n7331), .B1(
Data_1[0]), .Y(n2114) );
AO22X1TS U3520 ( .A0(n7355), .A1(FPSENCOS_d_ff2_X[14]), .B0(n7353), .B1(
FPSENCOS_d_ff3_sh_x_out[14]), .Y(n1978) );
AO22X1TS U3521 ( .A0(n7517), .A1(FPADDSUB_DMP_SHT2_EWSW[27]), .B0(n7515),
.B1(FPADDSUB_DMP_SFG[27]), .Y(n1437) );
AO22X1TS U3522 ( .A0(n7361), .A1(FPSENCOS_d_ff2_Y[20]), .B0(n7357), .B1(
FPSENCOS_d_ff3_sh_y_out[20]), .Y(n1868) );
AO22X1TS U3523 ( .A0(n7428), .A1(FPSENCOS_d_ff2_Y[1]), .B0(n7407), .B1(
FPSENCOS_d_ff3_sh_y_out[1]), .Y(n1906) );
AO22X1TS U3524 ( .A0(n7444), .A1(FPSENCOS_d_ff2_Y[14]), .B0(n7443), .B1(
FPSENCOS_d_ff3_sh_y_out[14]), .Y(n1880) );
AO22X1TS U3525 ( .A0(n7517), .A1(FPADDSUB_DMP_SHT2_EWSW[29]), .B0(n7515),
.B1(FPADDSUB_DMP_SFG[29]), .Y(n1427) );
AO22X1TS U3526 ( .A0(n7361), .A1(FPSENCOS_d_ff2_Y[19]), .B0(n7427), .B1(
FPSENCOS_d_ff3_sh_y_out[19]), .Y(n1870) );
AO22X1TS U3527 ( .A0(n7444), .A1(FPSENCOS_d_ff2_Y[10]), .B0(n7443), .B1(
FPSENCOS_d_ff3_sh_y_out[10]), .Y(n1888) );
ADDFHX2TS U3528 ( .A(n3415), .B(n3414), .CI(n3413), .CO(n3432), .S(n3416) );
NAND2BX1TS U3529 ( .AN(n3158), .B(n8524), .Y(n5523) );
OAI21X1TS U3530 ( .A0(n6335), .A1(n6204), .B0(n6203), .Y(n6207) );
AO22X1TS U3531 ( .A0(n7424), .A1(FPSENCOS_d_ff2_X[11]), .B0(n7353), .B1(
FPSENCOS_d_ff3_sh_x_out[11]), .Y(n1984) );
AO22X1TS U3532 ( .A0(n7444), .A1(FPSENCOS_d_ff2_Y[17]), .B0(n7427), .B1(
FPSENCOS_d_ff3_sh_y_out[17]), .Y(n1874) );
AO22X1TS U3533 ( .A0(n7361), .A1(n7360), .B0(n7407), .B1(
FPSENCOS_d_ff3_sh_x_out[28]), .Y(n1948) );
AO22X1TS U3534 ( .A0(n7357), .A1(FPSENCOS_d_ff3_sh_x_out[10]), .B0(n7410),
.B1(FPSENCOS_d_ff2_X[10]), .Y(n1986) );
NOR2X1TS U3535 ( .A(n7055), .B(n2339), .Y(n7056) );
OAI21X1TS U3536 ( .A0(n6335), .A1(n6223), .B0(n6222), .Y(n6226) );
AO22X1TS U3537 ( .A0(n6989), .A1(FPADDSUB_SIGN_FLAG_SHT2), .B0(n7598), .B1(
FPADDSUB_SIGN_FLAG_SFG), .Y(n1361) );
NOR2X1TS U3538 ( .A(n7058), .B(n7029), .Y(n7023) );
AO22X1TS U3539 ( .A0(n7508), .A1(FPADDSUB_DMP_SHT2_EWSW[24]), .B0(n7598),
.B1(FPADDSUB_DMP_SFG[24]), .Y(n1452) );
AO22X1TS U3540 ( .A0(n7517), .A1(FPADDSUB_DMP_SHT2_EWSW[26]), .B0(n7598),
.B1(FPADDSUB_DMP_SFG[26]), .Y(n1442) );
NOR2X1TS U3541 ( .A(n7051), .B(n7029), .Y(n7030) );
CLKMX2X2TS U3542 ( .A(Data_2[18]), .B(DP_OP_496J2_122_3540_n1462), .S0(n6901), .Y(n1645) );
AO22X1TS U3543 ( .A0(n7517), .A1(FPADDSUB_DMP_SHT2_EWSW[25]), .B0(n7598),
.B1(FPADDSUB_DMP_SFG[25]), .Y(n1447) );
XOR2X1TS U3544 ( .A(n4520), .B(n4567), .Y(n4521) );
OAI21X1TS U3545 ( .A0(n7359), .A1(n7860), .B0(n7362), .Y(n7360) );
AO22X1TS U3546 ( .A0(n7508), .A1(FPADDSUB_DMP_SHT2_EWSW[23]), .B0(n7598),
.B1(FPADDSUB_DMP_SFG[23]), .Y(n1457) );
NOR2X1TS U3547 ( .A(n6606), .B(n2246), .Y(n6501) );
NOR2X1TS U3548 ( .A(n7065), .B(n2339), .Y(n7066) );
CLKMX2X2TS U3549 ( .A(Data_2[11]), .B(DP_OP_496J2_122_3540_n1478), .S0(n2357), .Y(n1638) );
CLKMX2X2TS U3550 ( .A(Data_2[13]), .B(n8485), .S0(n6962), .Y(
DP_OP_497J2_123_1725_n779) );
CLKMX2X2TS U3551 ( .A(Data_2[5]), .B(n6860), .S0(n2357), .Y(n1632) );
OAI21X1TS U3552 ( .A0(FPMULT_Sgf_normalized_result[0]), .A1(n6943), .B0(
n6569), .Y(n1624) );
NOR2X1TS U3553 ( .A(n7055), .B(n7029), .Y(n7026) );
NOR2X1TS U3554 ( .A(n7065), .B(n7029), .Y(n7017) );
NOR2X1TS U3555 ( .A(n7058), .B(n2339), .Y(n7059) );
OAI211X1TS U3556 ( .A0(n7409), .A1(n7909), .B0(n6640), .C0(n6656), .Y(n2132)
);
AO22X1TS U3557 ( .A0(n7517), .A1(FPADDSUB_DMP_SHT2_EWSW[30]), .B0(n7598),
.B1(FPADDSUB_DMP_SFG[30]), .Y(n1422) );
NOR2X1TS U3558 ( .A(n7051), .B(n2339), .Y(n7053) );
AO22X1TS U3559 ( .A0(n7517), .A1(FPADDSUB_DMP_SHT2_EWSW[28]), .B0(n7598),
.B1(FPADDSUB_DMP_SFG[28]), .Y(n1432) );
CLKMX2X2TS U3560 ( .A(Data_2[1]), .B(DP_OP_498J2_124_1725_n789), .S0(n6901),
.Y(n1628) );
CLKMX2X2TS U3561 ( .A(Data_1[12]), .B(n7468), .S0(n2357), .Y(n1671) );
CLKMX2X2TS U3562 ( .A(Data_2[14]), .B(n5707), .S0(n6962), .Y(n1641) );
CLKMX2X2TS U3563 ( .A(Data_1[15]), .B(DP_OP_497J2_123_1725_n794), .S0(n2356),
.Y(n1674) );
CLKMX2X2TS U3564 ( .A(Data_1[8]), .B(DP_OP_496J2_122_3540_n1514), .S0(n7452),
.Y(n1667) );
CLKMX2X2TS U3565 ( .A(Data_2[17]), .B(DP_OP_496J2_122_3540_n1461), .S0(n6962), .Y(n1644) );
CLKMX2X2TS U3566 ( .A(Data_1[5]), .B(n8519), .S0(n7452), .Y(n1664) );
CLKMX2X2TS U3567 ( .A(Data_1[17]), .B(DP_OP_496J2_122_3540_n1498), .S0(n2356), .Y(n1676) );
CLKMX2X2TS U3568 ( .A(Data_1[13]), .B(n8481), .S0(n2357), .Y(n1672) );
NOR2X1TS U3569 ( .A(n6606), .B(n7759), .Y(n6529) );
NOR2X4TS U3570 ( .A(n6755), .B(n6731), .Y(n6736) );
CLKMX2X2TS U3571 ( .A(Data_2[10]), .B(FPMULT_Op_MY[10]), .S0(n2357), .Y(
n1637) );
AOI2BB2X1TS U3572 ( .B0(n7307), .B1(n7819), .A0N(n7819), .A1N(n7307), .Y(
n2139) );
NOR2X1TS U3573 ( .A(n6606), .B(n7761), .Y(n6511) );
CLKMX2X2TS U3574 ( .A(Data_2[19]), .B(DP_OP_496J2_122_3540_n778), .S0(n6901),
.Y(n1646) );
NOR2X1TS U3575 ( .A(n6606), .B(n7760), .Y(n6520) );
AO22X1TS U3576 ( .A0(n7512), .A1(n7497), .B0(n7634), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[1]), .Y(n1478) );
OAI211X1TS U3577 ( .A0(n7377), .A1(n5970), .B0(n5969), .C0(n5973), .Y(n5985)
);
NOR2X1TS U3578 ( .A(n5966), .B(n7566), .Y(n5967) );
NOR2X1TS U3579 ( .A(n2339), .B(n7081), .Y(n7083) );
NAND3X1TS U3580 ( .A(n5970), .B(n5969), .C(n7377), .Y(n5971) );
NAND2XLTS U3581 ( .A(n6699), .B(FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n6573) );
OAI21X1TS U3582 ( .A0(n6414), .A1(n6363), .B0(n6362), .Y(n6366) );
INVX6TS U3583 ( .A(n3818), .Y(n2242) );
OAI21X1TS U3584 ( .A0(n6335), .A1(n6306), .B0(n6305), .Y(n6309) );
NOR2X4TS U3585 ( .A(FPMULT_FSM_selector_C), .B(n5769), .Y(n5768) );
NAND3X4TS U3586 ( .A(n2666), .B(n2664), .C(n4404), .Y(n4343) );
OAI21X1TS U3587 ( .A0(n6335), .A1(n6318), .B0(n6317), .Y(n6323) );
OAI211X2TS U3588 ( .A0(n7381), .A1(n5963), .B0(n5981), .C0(n5962), .Y(n5983)
);
OAI21X1TS U3589 ( .A0(n7180), .A1(n7135), .B0(n7144), .Y(n7137) );
NOR2X1TS U3590 ( .A(n7071), .B(n2339), .Y(n7072) );
OAI21X1TS U3591 ( .A0(n7190), .A1(n7143), .B0(n7142), .Y(n7147) );
OAI21X1TS U3592 ( .A0(n7180), .A1(n7179), .B0(n7178), .Y(n7182) );
OAI21X1TS U3593 ( .A0(n7193), .A1(n7192), .B0(n7191), .Y(n7195) );
NOR2X1TS U3594 ( .A(n7068), .B(n2339), .Y(n7069) );
NOR2X1TS U3595 ( .A(n7077), .B(n7029), .Y(n6997) );
NOR2X1TS U3596 ( .A(n7068), .B(n7029), .Y(n7014) );
AO22X1TS U3597 ( .A0(n8523), .A1(n7603), .B0(n6862), .B1(
FPADDSUB_OP_FLAG_EXP), .Y(n1357) );
AO21X1TS U3598 ( .A0(n7293), .A1(begin_operation), .B0(n2492), .Y(n6616) );
NOR2X1TS U3599 ( .A(n6032), .B(n7575), .Y(n5877) );
NOR2X1TS U3600 ( .A(n7074), .B(n2339), .Y(n7075) );
INVX2TS U3601 ( .A(n3449), .Y(n2886) );
OAI211X2TS U3602 ( .A0(n7391), .A1(n6001), .B0(n6029), .C0(n6000), .Y(n6022)
);
ADDHX2TS U3603 ( .A(n3411), .B(n3410), .CO(n3430), .S(n3405) );
AO22X1TS U3604 ( .A0(n7512), .A1(n7500), .B0(n7665), .B1(
FPADDSUB_Shift_amount_SHT1_EWR[0]), .Y(n1477) );
NOR2X1TS U3605 ( .A(n6478), .B(n7765), .Y(n6462) );
ADDFHX2TS U3606 ( .A(n3332), .B(n3331), .CI(n3330), .CO(n3364), .S(n3371) );
NOR2X1TS U3607 ( .A(n6478), .B(n7764), .Y(n6468) );
OAI21X1TS U3608 ( .A0(n7190), .A1(n7129), .B0(n7128), .Y(n7133) );
NOR2X1TS U3609 ( .A(n6478), .B(n7763), .Y(n6479) );
AO22X1TS U3610 ( .A0(n7451), .A1(result_add_subt[29]), .B0(n7450), .B1(
FPSENCOS_d_ff_Xn[29]), .Y(n1768) );
AO22X1TS U3611 ( .A0(n7451), .A1(result_add_subt[27]), .B0(n7450), .B1(
FPSENCOS_d_ff_Xn[27]), .Y(n1774) );
AO22X1TS U3612 ( .A0(n7446), .A1(result_add_subt[30]), .B0(n7445), .B1(
FPSENCOS_d_ff_Yn[30]), .Y(n1732) );
AO22X1TS U3613 ( .A0(n7451), .A1(result_add_subt[26]), .B0(n7450), .B1(
FPSENCOS_d_ff_Xn[26]), .Y(n1777) );
NOR2X1TS U3614 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[0]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[1]), .Y(n6562) );
AO22X1TS U3615 ( .A0(n7440), .A1(result_add_subt[29]), .B0(n7439), .B1(
FPSENCOS_d_ff_Yn[29]), .Y(n1769) );
OAI211X2TS U3616 ( .A0(n7303), .A1(n2196), .B0(n6636), .C0(n7318), .Y(n7311)
);
NAND2BX1TS U3617 ( .AN(n7625), .B(n7378), .Y(n5972) );
AO22X1TS U3618 ( .A0(n7440), .A1(result_add_subt[24]), .B0(n7439), .B1(
FPSENCOS_d_ff_Yn[24]), .Y(n1784) );
AO22X1TS U3619 ( .A0(n7440), .A1(result_add_subt[26]), .B0(n7439), .B1(
FPSENCOS_d_ff_Yn[26]), .Y(n1778) );
NAND2BX1TS U3620 ( .AN(n7392), .B(n7576), .Y(n6000) );
AO22X1TS U3621 ( .A0(n7440), .A1(result_add_subt[27]), .B0(n7439), .B1(
FPSENCOS_d_ff_Yn[27]), .Y(n1775) );
AO22X1TS U3622 ( .A0(n7440), .A1(result_add_subt[28]), .B0(n7439), .B1(
FPSENCOS_d_ff_Yn[28]), .Y(n1772) );
NAND2X4TS U3623 ( .A(n2554), .B(n2553), .Y(n3449) );
OAI21X1TS U3624 ( .A0(gt_x_74_A_23_), .A1(n6024), .B0(n7393), .Y(n6025) );
AO22X1TS U3625 ( .A0(n7440), .A1(result_add_subt[22]), .B0(n7445), .B1(
FPSENCOS_d_ff_Yn[22]), .Y(n2009) );
AO22X1TS U3626 ( .A0(n7446), .A1(result_add_subt[15]), .B0(n7445), .B1(
FPSENCOS_d_ff_Yn[15]), .Y(n2030) );
AO22X1TS U3627 ( .A0(n7446), .A1(result_add_subt[18]), .B0(n7445), .B1(
FPSENCOS_d_ff_Yn[18]), .Y(n2021) );
AO22X1TS U3628 ( .A0(n7446), .A1(result_add_subt[21]), .B0(n7445), .B1(
FPSENCOS_d_ff_Yn[21]), .Y(n2012) );
AO22X1TS U3629 ( .A0(n7446), .A1(result_add_subt[19]), .B0(n7445), .B1(
FPSENCOS_d_ff_Yn[19]), .Y(n2018) );
AO22X1TS U3630 ( .A0(n7446), .A1(result_add_subt[20]), .B0(n7445), .B1(
FPSENCOS_d_ff_Yn[20]), .Y(n2015) );
AO22X1TS U3631 ( .A0(n7446), .A1(result_add_subt[17]), .B0(n7445), .B1(
FPSENCOS_d_ff_Yn[17]), .Y(n2024) );
OAI21X1TS U3632 ( .A0(n7386), .A1(n5976), .B0(n7384), .Y(n5977) );
OAI21X1TS U3633 ( .A0(n7382), .A1(n5964), .B0(n7381), .Y(n5965) );
NAND2X4TS U3634 ( .A(n3875), .B(n3879), .Y(n2729) );
AO22X1TS U3635 ( .A0(n7451), .A1(result_add_subt[25]), .B0(n7450), .B1(
FPSENCOS_d_ff_Xn[25]), .Y(n1780) );
AO22X1TS U3636 ( .A0(n7442), .A1(result_add_subt[30]), .B0(n7441), .B1(
FPSENCOS_d_ff_Zn[30]), .Y(n1767) );
AO22X1TS U3637 ( .A0(n7440), .A1(result_add_subt[25]), .B0(n7439), .B1(
FPSENCOS_d_ff_Yn[25]), .Y(n1781) );
AO22X1TS U3638 ( .A0(n7442), .A1(result_add_subt[29]), .B0(n7441), .B1(
FPSENCOS_d_ff_Zn[29]), .Y(n1770) );
NAND3X1TS U3639 ( .A(n5884), .B(n5883), .C(n7398), .Y(n5886) );
AO22X1TS U3640 ( .A0(n7442), .A1(result_add_subt[8]), .B0(n7345), .B1(
FPSENCOS_d_ff_Zn[8]), .Y(n2052) );
AO22X1TS U3641 ( .A0(n7442), .A1(result_add_subt[22]), .B0(n7436), .B1(
FPSENCOS_d_ff_Zn[22]), .Y(n2010) );
NOR2X1TS U3642 ( .A(n6306), .B(n6201), .Y(n6191) );
AO22X1TS U3643 ( .A0(n7451), .A1(result_add_subt[23]), .B0(n7348), .B1(
FPSENCOS_d_ff_Xn[23]), .Y(n1786) );
AO22X1TS U3644 ( .A0(n7440), .A1(result_add_subt[23]), .B0(n7445), .B1(
FPSENCOS_d_ff_Yn[23]), .Y(n1787) );
AO22X1TS U3645 ( .A0(n7451), .A1(result_add_subt[30]), .B0(n7450), .B1(
FPSENCOS_d_ff_Xn[30]), .Y(n1731) );
INVX3TS U3646 ( .A(n3324), .Y(n3338) );
NOR2X4TS U3647 ( .A(n4025), .B(n3772), .Y(n3782) );
AO22X1TS U3648 ( .A0(n7440), .A1(result_add_subt[0]), .B0(n7339), .B1(
FPSENCOS_d_ff_Yn[0]), .Y(n2075) );
AO22X1TS U3649 ( .A0(n7346), .A1(result_add_subt[5]), .B0(n7350), .B1(
FPSENCOS_d_ff_Xn[5]), .Y(n2059) );
AO22X1TS U3650 ( .A0(n7451), .A1(result_add_subt[22]), .B0(n7340), .B1(
FPSENCOS_d_ff_Xn[22]), .Y(n2008) );
AO22X1TS U3651 ( .A0(n7352), .A1(result_add_subt[15]), .B0(n7348), .B1(
FPSENCOS_d_ff_Xn[15]), .Y(n2029) );
AO22X1TS U3652 ( .A0(n7352), .A1(result_add_subt[18]), .B0(n7450), .B1(
FPSENCOS_d_ff_Xn[18]), .Y(n2020) );
AO22X1TS U3653 ( .A0(n7352), .A1(result_add_subt[21]), .B0(n7340), .B1(
FPSENCOS_d_ff_Xn[21]), .Y(n2011) );
AO22X1TS U3654 ( .A0(n7341), .A1(result_add_subt[1]), .B0(n7348), .B1(
FPSENCOS_d_ff_Xn[1]), .Y(n2071) );
AO22X1TS U3655 ( .A0(n7346), .A1(result_add_subt[4]), .B0(n7340), .B1(
FPSENCOS_d_ff_Xn[4]), .Y(n2062) );
AO22X1TS U3656 ( .A0(n7346), .A1(result_add_subt[8]), .B0(n7350), .B1(
FPSENCOS_d_ff_Xn[8]), .Y(n2050) );
AO22X1TS U3657 ( .A0(n7442), .A1(result_add_subt[31]), .B0(n7436), .B1(
FPSENCOS_d_ff_Zn[31]), .Y(n1911) );
AO22X1TS U3658 ( .A0(n7346), .A1(result_add_subt[11]), .B0(n7350), .B1(
FPSENCOS_d_ff_Xn[11]), .Y(n2041) );
AO22X1TS U3659 ( .A0(n7346), .A1(result_add_subt[7]), .B0(n7350), .B1(
FPSENCOS_d_ff_Xn[7]), .Y(n2053) );
AO22X1TS U3660 ( .A0(n7341), .A1(result_add_subt[0]), .B0(n7348), .B1(
FPSENCOS_d_ff_Xn[0]), .Y(n2074) );
AO22X1TS U3661 ( .A0(n7346), .A1(result_add_subt[2]), .B0(n7348), .B1(
FPSENCOS_d_ff_Xn[2]), .Y(n2068) );
OAI31X4TS U3662 ( .A0(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .A1(n7818),
.A2(n6646), .B0(n7282), .Y(n7308) );
AO22X1TS U3663 ( .A0(n7346), .A1(result_add_subt[9]), .B0(n7350), .B1(
FPSENCOS_d_ff_Xn[9]), .Y(n2047) );
AO22X1TS U3664 ( .A0(n7451), .A1(result_add_subt[28]), .B0(n7450), .B1(
FPSENCOS_d_ff_Xn[28]), .Y(n1771) );
AO22X1TS U3665 ( .A0(n7346), .A1(result_add_subt[3]), .B0(n7340), .B1(
FPSENCOS_d_ff_Xn[3]), .Y(n2065) );
AO22X1TS U3666 ( .A0(n7451), .A1(result_add_subt[24]), .B0(n7340), .B1(
FPSENCOS_d_ff_Xn[24]), .Y(n1783) );
OR2X2TS U3667 ( .A(n5403), .B(n5402), .Y(n5614) );
AO22X1TS U3668 ( .A0(n7442), .A1(result_add_subt[20]), .B0(n7436), .B1(
FPSENCOS_d_ff_Zn[20]), .Y(n2016) );
AO22X1TS U3669 ( .A0(n7352), .A1(result_add_subt[12]), .B0(n7350), .B1(
FPSENCOS_d_ff_Xn[12]), .Y(n2038) );
AO22X1TS U3670 ( .A0(n7352), .A1(result_add_subt[19]), .B0(n7340), .B1(
FPSENCOS_d_ff_Xn[19]), .Y(n2017) );
AO22X1TS U3671 ( .A0(n7352), .A1(result_add_subt[20]), .B0(n7340), .B1(
FPSENCOS_d_ff_Xn[20]), .Y(n2014) );
AO22X1TS U3672 ( .A0(n7346), .A1(result_add_subt[10]), .B0(n7350), .B1(
FPSENCOS_d_ff_Xn[10]), .Y(n2044) );
AO22X1TS U3673 ( .A0(n7352), .A1(result_add_subt[14]), .B0(n7350), .B1(
FPSENCOS_d_ff_Xn[14]), .Y(n2032) );
AO22X1TS U3674 ( .A0(n7352), .A1(result_add_subt[17]), .B0(n7348), .B1(
FPSENCOS_d_ff_Xn[17]), .Y(n2023) );
ADDHX2TS U3675 ( .A(n3329), .B(n3328), .CO(n3410), .S(n3336) );
AO22X1TS U3676 ( .A0(n7346), .A1(result_add_subt[6]), .B0(n7350), .B1(
FPSENCOS_d_ff_Xn[6]), .Y(n2056) );
AO22X1TS U3677 ( .A0(n7352), .A1(result_add_subt[13]), .B0(n7350), .B1(
FPSENCOS_d_ff_Xn[13]), .Y(n2035) );
AO22X1TS U3678 ( .A0(n7352), .A1(result_add_subt[16]), .B0(n7348), .B1(
FPSENCOS_d_ff_Xn[16]), .Y(n2026) );
AO22X1TS U3679 ( .A0(n7446), .A1(result_add_subt[13]), .B0(n7349), .B1(
FPSENCOS_d_ff_Yn[13]), .Y(n2036) );
AO22X1TS U3680 ( .A0(n7446), .A1(result_add_subt[16]), .B0(n7445), .B1(
FPSENCOS_d_ff_Yn[16]), .Y(n2027) );
OR2X2TS U3681 ( .A(n6905), .B(FPMULT_FSM_selector_C), .Y(n6542) );
NAND2BX1TS U3682 ( .AN(n7382), .B(n7563), .Y(n5962) );
NAND2BX1TS U3683 ( .AN(n7390), .B(n7578), .Y(n6018) );
AO22X1TS U3684 ( .A0(n7442), .A1(result_add_subt[23]), .B0(n7436), .B1(
FPSENCOS_d_ff_Zn[23]), .Y(n1788) );
OAI21X1TS U3685 ( .A0(n6232), .A1(n6224), .B0(n6231), .Y(n6233) );
OR2X4TS U3686 ( .A(n5454), .B(n6614), .Y(n6859) );
AO22X1TS U3687 ( .A0(n7442), .A1(result_add_subt[21]), .B0(n7436), .B1(
FPSENCOS_d_ff_Zn[21]), .Y(n2013) );
AO22X1TS U3688 ( .A0(n7446), .A1(result_add_subt[14]), .B0(n7349), .B1(
FPSENCOS_d_ff_Yn[14]), .Y(n2033) );
INVX6TS U3689 ( .A(n2518), .Y(n3787) );
AO22X1TS U3690 ( .A0(n7442), .A1(result_add_subt[19]), .B0(n7436), .B1(
FPSENCOS_d_ff_Zn[19]), .Y(n2019) );
NAND2BX1TS U3691 ( .AN(n7378), .B(n7625), .Y(n5969) );
NAND2XLTS U3692 ( .A(n6581), .B(FPADDSUB_DmP_mant_SHT1_SW[19]), .Y(n6277) );
OAI211X1TS U3693 ( .A0(n6261), .A1(n6263), .B0(n5808), .C0(n6649), .Y(n1693)
);
BUFX6TS U3694 ( .A(n3791), .Y(n2243) );
OAI21XLTS U3695 ( .A0(n6717), .A1(n7853), .B0(n6663), .Y(op_result[24]) );
OAI21XLTS U3696 ( .A0(n6717), .A1(n2343), .B0(n6666), .Y(op_result[31]) );
OAI21XLTS U3697 ( .A0(n6717), .A1(n7852), .B0(n6665), .Y(op_result[26]) );
OAI21XLTS U3698 ( .A0(n6661), .A1(n7843), .B0(n6627), .Y(op_result[3]) );
OAI21XLTS U3699 ( .A0(n6661), .A1(n7846), .B0(n6686), .Y(op_result[0]) );
OAI21XLTS U3700 ( .A0(n6661), .A1(n7847), .B0(n6688), .Y(op_result[1]) );
OAI21XLTS U3701 ( .A0(n6717), .A1(n7851), .B0(n6662), .Y(op_result[27]) );
OAI21XLTS U3702 ( .A0(n6713), .A1(n7839), .B0(n6687), .Y(op_result[11]) );
OAI21XLTS U3703 ( .A0(n6717), .A1(n7523), .B0(n6667), .Y(op_result[22]) );
OAI21XLTS U3704 ( .A0(n6713), .A1(n7842), .B0(n6712), .Y(op_result[12]) );
OAI21XLTS U3705 ( .A0(n6717), .A1(n7830), .B0(n6716), .Y(op_result[21]) );
OAI21XLTS U3706 ( .A0(n6717), .A1(n7832), .B0(n6709), .Y(op_result[20]) );
OAI21XLTS U3707 ( .A0(n6713), .A1(n7841), .B0(n6685), .Y(op_result[10]) );
OAI21XLTS U3708 ( .A0(n6717), .A1(n7831), .B0(n6710), .Y(op_result[19]) );
OAI21XLTS U3709 ( .A0(n6713), .A1(n7836), .B0(n6704), .Y(op_result[13]) );
OAI21XLTS U3710 ( .A0(n6713), .A1(n7840), .B0(n6706), .Y(op_result[14]) );
OAI21XLTS U3711 ( .A0(n6713), .A1(n7828), .B0(n6705), .Y(op_result[15]) );
OAI21XLTS U3712 ( .A0(n6717), .A1(n7829), .B0(n6703), .Y(op_result[18]) );
OAI21XLTS U3713 ( .A0(n6713), .A1(n7837), .B0(n6707), .Y(op_result[16]) );
OAI21XLTS U3714 ( .A0(n6717), .A1(n7850), .B0(n6664), .Y(op_result[28]) );
OAI21XLTS U3715 ( .A0(n6713), .A1(n7833), .B0(n6708), .Y(op_result[17]) );
AO22X1TS U3716 ( .A0(n7512), .A1(n7510), .B0(n7526), .B1(
FPADDSUB_DMP_SHT1_EWSW[26]), .Y(n1444) );
AO22X1TS U3717 ( .A0(n7347), .A1(result_add_subt[10]), .B0(n7349), .B1(
FPSENCOS_d_ff_Yn[10]), .Y(n2045) );
AO22X1TS U3718 ( .A0(n7605), .A1(n7555), .B0(n7604), .B1(
FPADDSUB_DmP_mant_SHT1_SW[14]), .Y(n1369) );
AO22X1TS U3719 ( .A0(n7512), .A1(n7507), .B0(n7526), .B1(
FPADDSUB_DMP_SHT1_EWSW[24]), .Y(n1454) );
AO22X1TS U3720 ( .A0(n7605), .A1(n7553), .B0(n7604), .B1(
FPADDSUB_DmP_mant_SHT1_SW[11]), .Y(n1372) );
AO22X1TS U3721 ( .A0(n7347), .A1(result_add_subt[12]), .B0(n7349), .B1(
FPSENCOS_d_ff_Yn[12]), .Y(n2039) );
AO22X1TS U3722 ( .A0(n7347), .A1(result_add_subt[11]), .B0(n7349), .B1(
FPSENCOS_d_ff_Yn[11]), .Y(n2042) );
NAND2BX1TS U3723 ( .AN(n7569), .B(n7399), .Y(n5885) );
AO22X1TS U3724 ( .A0(n7605), .A1(n7558), .B0(n7604), .B1(
FPADDSUB_DmP_mant_SHT1_SW[10]), .Y(n1366) );
AO22X1TS U3725 ( .A0(n7438), .A1(result_add_subt[24]), .B0(n7436), .B1(
FPSENCOS_d_ff_Zn[24]), .Y(n1785) );
NAND2BX1TS U3726 ( .AN(n7399), .B(n7569), .Y(n5883) );
AO22X1TS U3727 ( .A0(n7512), .A1(n7511), .B0(n7526), .B1(
FPADDSUB_DMP_SHT1_EWSW[27]), .Y(n1439) );
AO22X1TS U3728 ( .A0(n7347), .A1(result_add_subt[8]), .B0(n7349), .B1(
FPSENCOS_d_ff_Yn[8]), .Y(n2051) );
OAI211X2TS U3729 ( .A0(n2259), .A1(n8388), .B0(n8387), .C0(n5911), .Y(n7379)
);
AO22X1TS U3730 ( .A0(n7347), .A1(result_add_subt[6]), .B0(n7349), .B1(
FPSENCOS_d_ff_Yn[6]), .Y(n2057) );
AO22X1TS U3731 ( .A0(n7351), .A1(result_add_subt[18]), .B0(n7436), .B1(
FPSENCOS_d_ff_Zn[18]), .Y(n2022) );
AO22X1TS U3732 ( .A0(n7539), .A1(n7513), .B0(n7526), .B1(
FPADDSUB_DMP_SHT1_EWSW[28]), .Y(n1434) );
AO22X1TS U3733 ( .A0(n7539), .A1(n7516), .B0(n7526), .B1(
FPADDSUB_DMP_SHT1_EWSW[30]), .Y(n1424) );
NOR2X6TS U3734 ( .A(n4205), .B(n4204), .Y(n4736) );
OAI21X1TS U3735 ( .A0(n6335), .A1(n6294), .B0(n6293), .Y(n6299) );
AO22X1TS U3736 ( .A0(n7347), .A1(result_add_subt[4]), .B0(n7339), .B1(
FPSENCOS_d_ff_Yn[4]), .Y(n2063) );
CLKINVX2TS U3737 ( .A(n7302), .Y(n7304) );
AO22X1TS U3738 ( .A0(n7539), .A1(n7514), .B0(n7526), .B1(
FPADDSUB_DMP_SHT1_EWSW[29]), .Y(n1429) );
OAI21X1TS U3739 ( .A0(n6444), .A1(n8756), .B0(n6446), .Y(n6436) );
INVX6TS U3740 ( .A(n3445), .Y(n2351) );
AO22X1TS U3741 ( .A0(n7539), .A1(n7524), .B0(n7526), .B1(
FPADDSUB_DmP_mant_SHT1_SW[22]), .Y(n1408) );
AO22X1TS U3742 ( .A0(n7351), .A1(result_add_subt[15]), .B0(n7437), .B1(
FPSENCOS_d_ff_Zn[15]), .Y(n2031) );
ADDFHX2TS U3743 ( .A(n3556), .B(n3320), .CI(n3319), .CO(n3332), .S(n3334) );
AO22X1TS U3744 ( .A0(n7539), .A1(n7527), .B0(n7526), .B1(
FPADDSUB_DmP_mant_SHT1_SW[15]), .Y(n1405) );
AO22X1TS U3745 ( .A0(n7539), .A1(n7529), .B0(n7550), .B1(
FPADDSUB_DmP_mant_SHT1_SW[18]), .Y(n1402) );
OAI211X2TS U3746 ( .A0(n2259), .A1(n8378), .B0(n8377), .C0(n5990), .Y(n7387)
);
AO22X1TS U3747 ( .A0(n7438), .A1(result_add_subt[25]), .B0(n7436), .B1(
FPSENCOS_d_ff_Zn[25]), .Y(n1782) );
AO22X1TS U3748 ( .A0(n7539), .A1(n7531), .B0(n7550), .B1(
FPADDSUB_DmP_mant_SHT1_SW[21]), .Y(n1399) );
AO22X1TS U3749 ( .A0(n7438), .A1(result_add_subt[26]), .B0(n7437), .B1(
FPSENCOS_d_ff_Zn[26]), .Y(n1779) );
AO22X1TS U3750 ( .A0(n7539), .A1(n7533), .B0(n7550), .B1(
FPADDSUB_DmP_mant_SHT1_SW[19]), .Y(n1396) );
AO22X1TS U3751 ( .A0(n7539), .A1(n7535), .B0(n7550), .B1(
FPADDSUB_DmP_mant_SHT1_SW[20]), .Y(n1393) );
AO22X1TS U3752 ( .A0(n7512), .A1(n7509), .B0(n7526), .B1(
FPADDSUB_DMP_SHT1_EWSW[25]), .Y(n1449) );
NOR2X1TS U3753 ( .A(n7286), .B(n7441), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[6]) );
ADDFHX2TS U3754 ( .A(n4518), .B(n4223), .CI(n4222), .CO(n4298), .S(n4231) );
AO22X1TS U3755 ( .A0(n7539), .A1(n7538), .B0(n7550), .B1(
FPADDSUB_DmP_mant_SHT1_SW[17]), .Y(n1390) );
AO22X1TS U3756 ( .A0(n7605), .A1(n7541), .B0(n7550), .B1(
FPADDSUB_DmP_mant_SHT1_SW[4]), .Y(n1387) );
NOR2X4TS U3757 ( .A(n3342), .B(n3441), .Y(n3276) );
AO22X1TS U3758 ( .A0(n7438), .A1(result_add_subt[27]), .B0(n7437), .B1(
FPSENCOS_d_ff_Zn[27]), .Y(n1776) );
AO22X1TS U3759 ( .A0(n7347), .A1(result_add_subt[5]), .B0(n7349), .B1(
FPSENCOS_d_ff_Yn[5]), .Y(n2060) );
AO22X1TS U3760 ( .A0(n7605), .A1(n7543), .B0(n7550), .B1(
FPADDSUB_DmP_mant_SHT1_SW[6]), .Y(n1384) );
OAI211X2TS U3761 ( .A0(n2259), .A1(n8362), .B0(n8361), .C0(n6002), .Y(n7389)
);
AO22X1TS U3762 ( .A0(n7347), .A1(result_add_subt[9]), .B0(n7349), .B1(
FPSENCOS_d_ff_Yn[9]), .Y(n2048) );
AO22X1TS U3763 ( .A0(n7605), .A1(n7545), .B0(n7550), .B1(
FPADDSUB_DmP_mant_SHT1_SW[13]), .Y(n1381) );
AO22X1TS U3764 ( .A0(n7438), .A1(result_add_subt[28]), .B0(n7437), .B1(
FPSENCOS_d_ff_Zn[28]), .Y(n1773) );
AO22X1TS U3765 ( .A0(n7605), .A1(n7547), .B0(n7550), .B1(
FPADDSUB_DmP_mant_SHT1_SW[16]), .Y(n1378) );
AO22X1TS U3766 ( .A0(n7512), .A1(n1467), .B0(n7526), .B1(
FPADDSUB_DMP_SHT1_EWSW[23]), .Y(n1459) );
AND2X2TS U3767 ( .A(n4474), .B(n4567), .Y(n4475) );
AO22X1TS U3768 ( .A0(n7347), .A1(result_add_subt[7]), .B0(n7349), .B1(
FPSENCOS_d_ff_Yn[7]), .Y(n2054) );
AO22X1TS U3769 ( .A0(n7605), .A1(n7551), .B0(n7550), .B1(
FPADDSUB_DmP_mant_SHT1_SW[8]), .Y(n1375) );
AO22X1TS U3770 ( .A0(n7347), .A1(result_add_subt[3]), .B0(n7339), .B1(
FPSENCOS_d_ff_Yn[3]), .Y(n2066) );
AO22X1TS U3771 ( .A0(n7645), .A1(n7626), .B0(n7631), .B1(
FPADDSUB_DMP_SHT1_EWSW[9]), .Y(n1283) );
AO22X1TS U3772 ( .A0(n7645), .A1(n7630), .B0(n7631), .B1(
FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n1278) );
AO22X1TS U3773 ( .A0(n7645), .A1(n7632), .B0(n7631), .B1(
FPADDSUB_DMP_SHT1_EWSW[5]), .Y(n1276) );
AO22X1TS U3774 ( .A0(n7344), .A1(result_add_subt[7]), .B0(n7437), .B1(
FPSENCOS_d_ff_Zn[7]), .Y(n2055) );
AO22X1TS U3775 ( .A0(n7645), .A1(n7635), .B0(n7650), .B1(
FPADDSUB_DmP_mant_SHT1_SW[12]), .Y(n1272) );
AO22X1TS U3776 ( .A0(n7645), .A1(n7639), .B0(n7650), .B1(
FPADDSUB_DMP_SHT1_EWSW[12]), .Y(n1270) );
AO22X1TS U3777 ( .A0(n7645), .A1(n7640), .B0(n7650), .B1(
FPADDSUB_DMP_SHT1_EWSW[10]), .Y(n1266) );
AO22X1TS U3778 ( .A0(n7645), .A1(n7641), .B0(n7650), .B1(
FPADDSUB_DMP_SHT1_EWSW[14]), .Y(n1262) );
AO22X1TS U3779 ( .A0(n7645), .A1(n7643), .B0(n7650), .B1(
FPADDSUB_DMP_SHT1_EWSW[11]), .Y(n1258) );
AO22X1TS U3780 ( .A0(n7645), .A1(n7644), .B0(n7650), .B1(
FPADDSUB_DMP_SHT1_EWSW[8]), .Y(n1254) );
AO22X1TS U3781 ( .A0(n7667), .A1(n7646), .B0(n7650), .B1(
FPADDSUB_DMP_SHT1_EWSW[16]), .Y(n1250) );
AO22X1TS U3782 ( .A0(n7351), .A1(result_add_subt[0]), .B0(n7345), .B1(
FPSENCOS_d_ff_Zn[0]), .Y(n2076) );
AO22X1TS U3783 ( .A0(n7667), .A1(n7647), .B0(n7650), .B1(
FPADDSUB_DMP_SHT1_EWSW[13]), .Y(n1246) );
AO22X1TS U3784 ( .A0(n7667), .A1(n7649), .B0(n7650), .B1(
FPADDSUB_DMP_SHT1_EWSW[6]), .Y(n1242) );
AO22X1TS U3785 ( .A0(n7667), .A1(n7651), .B0(n7650), .B1(
FPADDSUB_DMP_SHT1_EWSW[4]), .Y(n1238) );
AO22X1TS U3786 ( .A0(n7667), .A1(n7653), .B0(n7661), .B1(
FPADDSUB_DMP_SHT1_EWSW[17]), .Y(n1234) );
AO22X1TS U3787 ( .A0(n7667), .A1(n7657), .B0(n7661), .B1(
FPADDSUB_DMP_SHT1_EWSW[20]), .Y(n1230) );
AO22X1TS U3788 ( .A0(n7667), .A1(n7659), .B0(n7661), .B1(
FPADDSUB_DMP_SHT1_EWSW[19]), .Y(n1226) );
AO22X1TS U3789 ( .A0(n7667), .A1(n7660), .B0(n7661), .B1(
FPADDSUB_DMP_SHT1_EWSW[21]), .Y(n1222) );
AO22X1TS U3790 ( .A0(n7344), .A1(result_add_subt[6]), .B0(n7441), .B1(
FPSENCOS_d_ff_Zn[6]), .Y(n2058) );
AO22X1TS U3791 ( .A0(n7438), .A1(result_add_subt[12]), .B0(n7343), .B1(
FPSENCOS_d_ff_Zn[12]), .Y(n2040) );
AO22X1TS U3792 ( .A0(n7667), .A1(n7662), .B0(n7661), .B1(
FPADDSUB_DMP_SHT1_EWSW[18]), .Y(n1218) );
AO22X1TS U3793 ( .A0(n7351), .A1(result_add_subt[1]), .B0(n7441), .B1(
FPSENCOS_d_ff_Zn[1]), .Y(n2073) );
ADDFHX2TS U3794 ( .A(n4394), .B(n4393), .CI(n4392), .CO(n4459), .S(n4414) );
AO22X1TS U3795 ( .A0(n7667), .A1(n7666), .B0(n7665), .B1(
FPADDSUB_DMP_SHT1_EWSW[15]), .Y(n1214) );
AO22X1TS U3796 ( .A0(n6356), .A1(n6861), .B0(n7604), .B1(
FPADDSUB_DMP_SHT1_EWSW[22]), .Y(n1210) );
AND2X2TS U3797 ( .A(n3467), .B(n3625), .Y(n3517) );
AO22X1TS U3798 ( .A0(n7645), .A1(n7623), .B0(n7631), .B1(
FPADDSUB_DmP_mant_SHT1_SW[9]), .Y(n1285) );
AO22X1TS U3799 ( .A0(n7438), .A1(result_add_subt[11]), .B0(n7437), .B1(
FPSENCOS_d_ff_Zn[11]), .Y(n2043) );
AO22X1TS U3800 ( .A0(n7438), .A1(result_add_subt[9]), .B0(n7437), .B1(
FPSENCOS_d_ff_Zn[9]), .Y(n2049) );
CLKBUFX3TS U3801 ( .A(n6180), .Y(n2381) );
NAND2BX1TS U3802 ( .AN(n7395), .B(n7575), .Y(n6030) );
AO22X1TS U3803 ( .A0(n7351), .A1(result_add_subt[17]), .B0(n7436), .B1(
FPSENCOS_d_ff_Zn[17]), .Y(n2025) );
INVX1TS U3804 ( .A(gt_x_74_A_23_), .Y(n7574) );
AO22X1TS U3805 ( .A0(n7344), .A1(result_add_subt[5]), .B0(n7441), .B1(
FPSENCOS_d_ff_Zn[5]), .Y(n2061) );
AO22X1TS U3806 ( .A0(n7438), .A1(result_add_subt[10]), .B0(n7437), .B1(
FPSENCOS_d_ff_Zn[10]), .Y(n2046) );
AO22X1TS U3807 ( .A0(n7605), .A1(FPADDSUB_SIGN_FLAG_EXP), .B0(n7604), .B1(
FPADDSUB_SIGN_FLAG_SHT1), .Y(n1363) );
AO22X1TS U3808 ( .A0(n7351), .A1(result_add_subt[14]), .B0(n7345), .B1(
FPSENCOS_d_ff_Zn[14]), .Y(n2034) );
AO22X1TS U3809 ( .A0(n7351), .A1(result_add_subt[4]), .B0(n7441), .B1(
FPSENCOS_d_ff_Zn[4]), .Y(n2064) );
AO22X1TS U3810 ( .A0(n7605), .A1(FPADDSUB_OP_FLAG_EXP), .B0(n7604), .B1(
FPADDSUB_OP_FLAG_SHT1), .Y(n1356) );
AO22X1TS U3811 ( .A0(n7351), .A1(result_add_subt[16]), .B0(n7345), .B1(
FPSENCOS_d_ff_Zn[16]), .Y(n2028) );
AO22X1TS U3812 ( .A0(n7438), .A1(result_add_subt[13]), .B0(n7343), .B1(
FPSENCOS_d_ff_Zn[13]), .Y(n2037) );
AO22X1TS U3813 ( .A0(n7351), .A1(result_add_subt[3]), .B0(n7441), .B1(
FPSENCOS_d_ff_Zn[3]), .Y(n2067) );
INVX2TS U3814 ( .A(n2812), .Y(n2809) );
AO22X1TS U3815 ( .A0(n7351), .A1(result_add_subt[2]), .B0(n7441), .B1(
FPSENCOS_d_ff_Zn[2]), .Y(n2070) );
OAI21XLTS U3816 ( .A0(n6661), .A1(n7835), .B0(n6631), .Y(op_result[6]) );
OAI21XLTS U3817 ( .A0(n6661), .A1(n7849), .B0(n6630), .Y(op_result[5]) );
OAI21XLTS U3818 ( .A0(n6661), .A1(n7834), .B0(n6626), .Y(op_result[4]) );
OAI21XLTS U3819 ( .A0(n6661), .A1(n7845), .B0(n6629), .Y(op_result[7]) );
OAI21XLTS U3820 ( .A0(n6713), .A1(n7848), .B0(n6628), .Y(op_result[9]) );
OAI21XLTS U3821 ( .A0(n6713), .A1(n7838), .B0(n6625), .Y(op_result[8]) );
OAI21XLTS U3822 ( .A0(n6661), .A1(n7844), .B0(n6657), .Y(op_result[2]) );
NAND2BX1TS U3823 ( .AN(n6238), .B(n6237), .Y(n6239) );
OAI211X2TS U3824 ( .A0(n2259), .A1(n8320), .B0(n8319), .C0(n5918), .Y(n7373)
);
AO22X1TS U3825 ( .A0(n6355), .A1(n6868), .B0(n7604), .B1(
FPADDSUB_DmP_mant_SHT1_SW[2]), .Y(n1313) );
AO22X1TS U3826 ( .A0(n6355), .A1(n7610), .B0(n7604), .B1(
FPADDSUB_DMP_SHT1_EWSW[2]), .Y(n1311) );
OAI211X2TS U3827 ( .A0(n2260), .A1(n8318), .B0(n8317), .C0(n5931), .Y(n7368)
);
NOR2X1TS U3828 ( .A(n7817), .B(n2350), .Y(n6166) );
INVX12TS U3829 ( .A(n3408), .Y(n3342) );
OAI211X2TS U3830 ( .A0(n2260), .A1(n8328), .B0(n8327), .C0(n5936), .Y(n7370)
);
NAND2XLTS U3831 ( .A(n7548), .B(result_add_subt[25]), .Y(n6567) );
OAI211X4TS U3832 ( .A0(n2204), .A1(n8398), .B0(n8397), .C0(n5909), .Y(n7625)
);
OAI211X2TS U3833 ( .A0(n2202), .A1(n8322), .B0(n8321), .C0(n5924), .Y(n7376)
);
AO22X1TS U3834 ( .A0(n6355), .A1(n7619), .B0(n7631), .B1(
FPADDSUB_DMP_SHT1_EWSW[1]), .Y(n1290) );
AO22X1TS U3835 ( .A0(n6355), .A1(n6871), .B0(n7631), .B1(
FPADDSUB_DmP_mant_SHT1_SW[1]), .Y(n1292) );
OAI211X2TS U3836 ( .A0(n2259), .A1(n8324), .B0(n8323), .C0(n5906), .Y(n7377)
);
AND2X2TS U3837 ( .A(n7600), .B(FPADDSUB_OP_FLAG_SFG), .Y(n6424) );
OAI21X1TS U3838 ( .A0(n6238), .A1(n6231), .B0(n6237), .Y(n6198) );
AO22X1TS U3839 ( .A0(n6355), .A1(n7616), .B0(n7631), .B1(
FPADDSUB_DMP_SHT1_EWSW[0]), .Y(n1297) );
AO22X1TS U3840 ( .A0(n6355), .A1(n6870), .B0(n7631), .B1(
FPADDSUB_DmP_mant_SHT1_SW[0]), .Y(n1299) );
AO22X1TS U3841 ( .A0(n6355), .A1(n6865), .B0(n7604), .B1(
FPADDSUB_DmP_mant_SHT1_SW[3]), .Y(n1329) );
CMPR22X2TS U3842 ( .A(n3206), .B(n3205), .CO(n3210), .S(n3283) );
AO22X1TS U3843 ( .A0(n6355), .A1(n7613), .B0(n7631), .B1(
FPADDSUB_DMP_SHT1_EWSW[7]), .Y(n1304) );
AO22X1TS U3844 ( .A0(n6355), .A1(n7607), .B0(n7604), .B1(
FPADDSUB_DMP_SHT1_EWSW[3]), .Y(n1327) );
AO22X1TS U3845 ( .A0(n6355), .A1(n6866), .B0(n7631), .B1(
FPADDSUB_DmP_mant_SHT1_SW[7]), .Y(n1306) );
OAI211X2TS U3846 ( .A0(n8023), .A1(n8059), .B0(n6046), .C0(n6045), .Y(n1808)
);
OAI211X2TS U3847 ( .A0(n2201), .A1(n8312), .B0(n8311), .C0(n5874), .Y(n7571)
);
OAI211X2TS U3848 ( .A0(n8025), .A1(n8059), .B0(n6850), .C0(n6849), .Y(n1796)
);
OAI211X2TS U3849 ( .A0(n2205), .A1(n8404), .B0(n8403), .C0(n6874), .Y(n7602)
);
OAI211X2TS U3850 ( .A0(n2205), .A1(n8368), .B0(n8367), .C0(n5991), .Y(n7391)
);
OAI211X2TS U3851 ( .A0(n7998), .A1(n2468), .B0(n6837), .C0(n6836), .Y(n1804)
);
OAI211X2TS U3852 ( .A0(n8024), .A1(n8058), .B0(n6168), .C0(n6167), .Y(n1805)
);
INVX2TS U3853 ( .A(n7548), .Y(n8612) );
INVX8TS U3854 ( .A(n3316), .Y(n3612) );
OAI211X2TS U3855 ( .A0(n8028), .A1(n2468), .B0(n6552), .C0(n6551), .Y(n1802)
);
OAI211X2TS U3856 ( .A0(n8029), .A1(n8059), .B0(n6247), .C0(n6246), .Y(n1800)
);
OAI211X2TS U3857 ( .A0(n8026), .A1(n8059), .B0(n6846), .C0(n6845), .Y(n1794)
);
NOR2X1TS U3858 ( .A(n6052), .B(FPADDSUB_Raw_mant_NRM_SWR[25]), .Y(n6056) );
OAI211X2TS U3859 ( .A0(n8000), .A1(n8059), .B0(n6351), .C0(n6350), .Y(n1798)
);
NOR2X1TS U3860 ( .A(n6054), .B(FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n6055) );
OAI211X2TS U3861 ( .A0(n2259), .A1(n8358), .B0(n8357), .C0(n5995), .Y(n7393)
);
OAI211X2TS U3862 ( .A0(n8021), .A1(n2371), .B0(n6044), .C0(n6043), .Y(n1811)
);
AND2X2TS U3863 ( .A(n6602), .B(n2350), .Y(n6618) );
OAI211X2TS U3864 ( .A0(n8024), .A1(n8059), .B0(n6554), .C0(n6553), .Y(n1806)
);
OAI211X2TS U3865 ( .A0(n2205), .A1(n8308), .B0(n8307), .C0(n5764), .Y(
gt_x_74_B_23_) );
ADDFHX2TS U3866 ( .A(n4352), .B(DP_OP_498J2_124_1725_n718), .CI(n4351), .CO(
n4416), .S(n4327) );
OAI211X2TS U3867 ( .A0(n8023), .A1(n8058), .B0(n6187), .C0(n6186), .Y(n1807)
);
OAI211X2TS U3868 ( .A0(n7998), .A1(n8058), .B0(n6835), .C0(n6834), .Y(n1803)
);
INVX1TS U3869 ( .A(n7665), .Y(n6356) );
AO22X1TS U3870 ( .A0(n8644), .A1(busy), .B0(n8643), .B1(
FPADDSUB_Shift_reg_FLAGS_7[3]), .Y(n2147) );
OAI211X2TS U3871 ( .A0(n2205), .A1(n8314), .B0(n8313), .C0(n5880), .Y(n7580)
);
OAI21X1TS U3872 ( .A0(r_mode[1]), .A1(r_mode[0]), .B0(n5802), .Y(n5803) );
OAI211X2TS U3873 ( .A0(n8000), .A1(n8058), .B0(n6171), .C0(n6170), .Y(n1797)
);
OAI211X2TS U3874 ( .A0(n8029), .A1(n8058), .B0(n6245), .C0(n6244), .Y(n1799)
);
NOR2X4TS U3875 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n6991), .Y(n6178)
);
OAI21X1TS U3876 ( .A0(n6335), .A1(n7767), .B0(n7745), .Y(n5789) );
NOR2X6TS U3877 ( .A(n2683), .B(n3174), .Y(n3455) );
NOR2X4TS U3878 ( .A(n3232), .B(n3479), .Y(n2899) );
NOR2X4TS U3879 ( .A(n7196), .B(FPADDSUB_OP_FLAG_SFG), .Y(n6371) );
NOR2X4TS U3880 ( .A(n4973), .B(DP_OP_498J2_124_1725_n732), .Y(n4400) );
OAI21X1TS U3881 ( .A0(n6397), .A1(n6402), .B0(n6398), .Y(n5845) );
OR2X2TS U3882 ( .A(FPADDSUB_shift_value_SHT2_EWR[2]), .B(n2491), .Y(n2335)
);
NOR2X4TS U3883 ( .A(n3295), .B(n3479), .Y(n3482) );
OAI21X1TS U3884 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n6953), .B0(n3154), .Y(
n6954) );
OR2X2TS U3885 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .B(n7012), .Y(n6181)
);
INVX2TS U3886 ( .A(n7088), .Y(n7089) );
NAND2X6TS U3887 ( .A(n5707), .B(n3860), .Y(n3297) );
INVX12TS U3888 ( .A(n4294), .Y(n2953) );
OAI21X1TS U3889 ( .A0(n6295), .A1(n7766), .B0(n6296), .Y(n6193) );
CLKINVX2TS U3890 ( .A(n6587), .Y(n7289) );
NOR2X1TS U3891 ( .A(n7794), .B(n6620), .Y(n5807) );
NAND2X6TS U3892 ( .A(n4451), .B(n4211), .Y(n4220) );
OAI21X1TS U3893 ( .A0(n5820), .A1(n6376), .B0(n5819), .Y(n5821) );
ADDHX2TS U3894 ( .A(n6860), .B(DP_OP_496J2_122_3540_n1478), .CO(n4411), .S(
n4324) );
INVX1TS U3895 ( .A(n6449), .Y(n6255) );
NAND3X1TS U3896 ( .A(n7261), .B(n7260), .C(n7259), .Y(n8060) );
OAI32X1TS U3897 ( .A0(n7287), .A1(FPMULT_exp_oper_result[8]), .A2(
FPMULT_Exp_module_Overflow_flag_A), .B0(overflow_flag_addsubt), .B1(
operation[2]), .Y(n6588) );
CLKAND2X2TS U3898 ( .A(n7941), .B(FPADDSUB_DMP_SFG[9]), .Y(n5833) );
BUFX16TS U3899 ( .A(n4255), .Y(n2245) );
INVX12TS U3900 ( .A(DP_OP_498J2_124_1725_n789), .Y(n4166) );
AO22X4TS U3901 ( .A0(n8290), .A1(n8289), .B0(n8288), .B1(n8287), .Y(n7548)
);
NAND2X4TS U3902 ( .A(n7727), .B(DP_OP_496J2_122_3540_n1108), .Y(n2579) );
CLKMX2X2TS U3903 ( .A(n8072), .B(n8071), .S0(n8044), .Y(n1579) );
CLKMX2X2TS U3904 ( .A(n8145), .B(n8144), .S0(n8044), .Y(n1580) );
OR2X2TS U3905 ( .A(n7788), .B(FPMULT_FS_Module_state_reg[3]), .Y(n6620) );
INVX6TS U3906 ( .A(DP_OP_498J2_124_1725_n802), .Y(n4211) );
OR3X4TS U3907 ( .A(FPSENCOS_cont_var_out[1]), .B(n7819), .C(n7800), .Y(n7339) );
NOR2X1TS U3908 ( .A(add_x_246_A_1_), .B(add_x_246_A_0_), .Y(n6941) );
NOR2X1TS U3909 ( .A(n7801), .B(n7854), .Y(n6983) );
OR2X2TS U3910 ( .A(FPADDSUB_DMP_SFG[22]), .B(FPADDSUB_DmP_mant_SFG_SWR[24]),
.Y(n6101) );
INVX4TS U3911 ( .A(FPADDSUB_Shift_reg_FLAGS_7[2]), .Y(n7088) );
OR2X2TS U3912 ( .A(FPADDSUB_DMP_SFG[20]), .B(FPADDSUB_DmP_mant_SFG_SWR[22]),
.Y(n6120) );
CLKMX2X2TS U3913 ( .A(n8070), .B(n8069), .S0(n8044), .Y(n1578) );
CLKINVX2TS U3914 ( .A(FPSENCOS_d_ff2_Y[28]), .Y(n8679) );
INVX12TS U3915 ( .A(DP_OP_498J2_124_1725_n796), .Y(n4451) );
OR2X2TS U3916 ( .A(FPADDSUB_DMP_SFG[18]), .B(FPADDSUB_DmP_mant_SFG_SWR[20]),
.Y(n6139) );
INVX8TS U3917 ( .A(DP_OP_497J2_123_1725_n792), .Y(n3220) );
INVX8TS U3918 ( .A(DP_OP_497J2_123_1725_n782), .Y(n3295) );
NOR2X1TS U3919 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .Y(n5814) );
NAND3X1TS U3920 ( .A(n5811), .B(n5810), .C(n5809), .Y(n5812) );
BUFX3TS U3921 ( .A(n8077), .Y(n5986) );
AOI22X1TS U3922 ( .A0(n8074), .A1(n8175), .B0(n5998), .B1(n8174), .Y(n5874)
);
AOI22X1TS U3923 ( .A0(n8074), .A1(n8173), .B0(n5998), .B1(n8172), .Y(n5876)
);
AOI22X1TS U3924 ( .A0(n8074), .A1(n8177), .B0(n5998), .B1(n8176), .Y(n5880)
);
AOI22X1TS U3925 ( .A0(n8074), .A1(n8167), .B0(n2208), .B1(n8166), .Y(n5882)
);
AOI22X1TS U3926 ( .A0(n8074), .A1(n8181), .B0(n5998), .B1(n8180), .Y(n5999)
);
AOI22X1TS U3927 ( .A0(n8074), .A1(n8171), .B0(n2208), .B1(n8170), .Y(n6004)
);
BUFX3TS U3928 ( .A(n5904), .Y(n2251) );
AOI22X1TS U3929 ( .A0(n8076), .A1(n8269), .B0(n6005), .B1(n8268), .Y(n5765)
);
AOI22X1TS U3930 ( .A0(n8076), .A1(n8247), .B0(n6005), .B1(n8246), .Y(n5873)
);
AOI22X1TS U3931 ( .A0(n8076), .A1(n8259), .B0(n6005), .B1(n8258), .Y(n5991)
);
AOI22X1TS U3932 ( .A0(n8076), .A1(n8233), .B0(n6005), .B1(n8232), .Y(n5995)
);
AOI22X1TS U3933 ( .A0(n8076), .A1(n8253), .B0(n6005), .B1(n8252), .Y(n5997)
);
OAI21X1TS U3934 ( .A0(n7371), .A1(n5941), .B0(n7370), .Y(n5940) );
OAI2BB2XLTS U3935 ( .B0(n7564), .B1(n5977), .A0N(n7386), .A1N(n5976), .Y(
n5978) );
OAI2BB2XLTS U3936 ( .B0(n7638), .B1(n5965), .A0N(n7382), .A1N(n5964), .Y(
n5980) );
OAI211X1TS U3937 ( .A0(n2260), .A1(n8336), .B0(n8335), .C0(n5916), .Y(n7375)
);
OAI211X4TS U3938 ( .A0(n2202), .A1(n8366), .B0(n8365), .C0(n6006), .Y(n7390)
);
OAI211X4TS U3939 ( .A0(n2204), .A1(n8384), .B0(n8383), .C0(n5956), .Y(n7384)
);
OAI211X4TS U3940 ( .A0(n2259), .A1(n8390), .B0(n8389), .C0(n5952), .Y(n7381)
);
OAI211X4TS U3941 ( .A0(n2205), .A1(n8370), .B0(n8369), .C0(n5905), .Y(n7388)
);
OAI211X4TS U3942 ( .A0(n2202), .A1(n8310), .B0(n8309), .C0(n5876), .Y(n7575)
);
OAI211X4TS U3943 ( .A0(n2205), .A1(n8364), .B0(n8363), .C0(n5997), .Y(n7392)
);
OAI211X4TS U3944 ( .A0(n2205), .A1(n8354), .B0(n8353), .C0(n5894), .Y(n7401)
);
OAI211X1TS U3945 ( .A0(n2205), .A1(n8406), .B0(n8405), .C0(n5889), .Y(n7400)
);
OAI211X4TS U3946 ( .A0(n2202), .A1(n8352), .B0(n8351), .C0(n5881), .Y(n7399)
);
OAI211X4TS U3947 ( .A0(n2205), .A1(n8348), .B0(n8347), .C0(n5873), .Y(n7397)
);
OAI211X4TS U3948 ( .A0(n2259), .A1(n8402), .B0(n8401), .C0(n5765), .Y(
gt_x_74_A_23_) );
OAI211X4TS U3949 ( .A0(n2202), .A1(n8374), .B0(n8373), .C0(n5920), .Y(n7584)
);
OAI211X4TS U3950 ( .A0(n2259), .A1(n8372), .B0(n8371), .C0(n5915), .Y(n7582)
);
OAI211X4TS U3951 ( .A0(n2205), .A1(n8356), .B0(n8355), .C0(n5891), .Y(n7403)
);
NOR2X4TS U3952 ( .A(n4844), .B(n4843), .Y(n5456) );
NOR2X6TS U3953 ( .A(n3819), .B(n2277), .Y(n2902) );
XOR2X4TS U3954 ( .A(n3595), .B(n2261), .Y(n3616) );
XOR2X4TS U3955 ( .A(n3596), .B(n3597), .Y(n2261) );
NAND3X6TS U3956 ( .A(n3003), .B(n3002), .C(n5675), .Y(n2267) );
NAND3X6TS U3957 ( .A(n3003), .B(n3002), .C(n5675), .Y(n3000) );
NAND3X4TS U3958 ( .A(n2687), .B(n2688), .C(n3695), .Y(n2545) );
NOR2X8TS U3959 ( .A(n3591), .B(n3590), .Y(n3681) );
ADDFHX2TS U3960 ( .A(n5214), .B(n5633), .CI(n5213), .CO(n5242), .S(n5228) );
ADDFHX2TS U3961 ( .A(n5224), .B(n5223), .CI(n5222), .CO(n5249), .S(n5213) );
NOR2X6TS U3962 ( .A(n4294), .B(n2274), .Y(n4402) );
BUFX16TS U3963 ( .A(FPMULT_Op_MX[4]), .Y(n4294) );
CLKINVX6TS U3964 ( .A(n4583), .Y(n3945) );
NAND2X2TS U3965 ( .A(n4584), .B(n4583), .Y(n4826) );
NOR2X2TS U3966 ( .A(n4584), .B(n4583), .Y(n4827) );
AND2X8TS U3967 ( .A(n5441), .B(n5440), .Y(n5685) );
INVX12TS U3968 ( .A(n8518), .Y(n4397) );
OAI22X2TS U3969 ( .A0(n4549), .A1(n4495), .B0(n2437), .B1(n4550), .Y(n4383)
);
INVX4TS U3970 ( .A(n4734), .Y(n4203) );
INVX12TS U3971 ( .A(DP_OP_498J2_124_1725_n788), .Y(n4185) );
NOR2X4TS U3972 ( .A(n4295), .B(n4276), .Y(n4714) );
NOR2X8TS U3973 ( .A(n4996), .B(n5312), .Y(n5282) );
NAND2X4TS U3974 ( .A(n3038), .B(n3036), .Y(n5259) );
INVX8TS U3975 ( .A(n2594), .Y(n5208) );
ADDFHX4TS U3976 ( .A(n4926), .B(n4925), .CI(n4924), .CO(n5164), .S(n4911) );
NAND2X4TS U3977 ( .A(n2929), .B(n2930), .Y(n2712) );
NAND3X6TS U3978 ( .A(n2929), .B(n2930), .C(n3660), .Y(n2687) );
NOR2X4TS U3979 ( .A(n3484), .B(n3088), .Y(n3087) );
OAI2BB1X4TS U3980 ( .A0N(n4699), .A1N(n5142), .B0(n3171), .Y(n3130) );
XNOR2X4TS U3981 ( .A(n3289), .B(n3375), .Y(n3290) );
NOR2X4TS U3982 ( .A(n4397), .B(n2275), .Y(n4395) );
NOR2X4TS U3983 ( .A(n4972), .B(n4397), .Y(n4455) );
NAND2X6TS U3984 ( .A(n5445), .B(n2904), .Y(n3050) );
XNOR2X4TS U3985 ( .A(n2633), .B(n5157), .Y(n2635) );
NAND2X6TS U3986 ( .A(DP_OP_496J2_122_3540_n1493), .B(
DP_OP_496J2_122_3540_n1506), .Y(n3769) );
XOR2X4TS U3987 ( .A(n4294), .B(n2936), .Y(n2955) );
ADDFHX4TS U3988 ( .A(n4463), .B(n4462), .CI(n4461), .CO(n4502), .S(n4464) );
NOR2X2TS U3989 ( .A(n5071), .B(n5032), .Y(n5073) );
BUFX12TS U3990 ( .A(n5030), .Y(n5071) );
AND2X4TS U3991 ( .A(n5698), .B(n5689), .Y(n3011) );
ADDFHX4TS U3992 ( .A(n5190), .B(n5189), .CI(n5188), .CO(n5218), .S(n5192) );
NAND2X6TS U3993 ( .A(n4869), .B(n4868), .Y(n5463) );
XNOR2X4TS U3994 ( .A(n4853), .B(n4852), .Y(n7212) );
XNOR2X2TS U3995 ( .A(n2867), .B(n2866), .Y(n2865) );
CLKXOR2X4TS U3996 ( .A(n4457), .B(n2865), .Y(n4460) );
ADDFX2TS U3997 ( .A(n4039), .B(n4038), .CI(n4037), .CO(n4061), .S(n4040) );
OAI22X4TS U3998 ( .A0(n4009), .A1(n4093), .B0(n4002), .B1(n4094), .Y(n4039)
);
NAND2X4TS U3999 ( .A(n4894), .B(n4895), .Y(n5727) );
NAND2X4TS U4000 ( .A(n4636), .B(n4635), .Y(n4637) );
XNOR2X4TS U4001 ( .A(n5042), .B(n5041), .Y(n2262) );
XNOR2X4TS U4002 ( .A(n5042), .B(n5041), .Y(n2263) );
NAND2X6TS U4003 ( .A(n2657), .B(DP_OP_498J2_124_1725_n390), .Y(n2839) );
NAND2X4TS U4004 ( .A(n2665), .B(n2657), .Y(n2664) );
AND2X8TS U4005 ( .A(n2843), .B(n5051), .Y(n2264) );
NAND2BX2TS U4006 ( .AN(n4027), .B(n4936), .Y(n3750) );
NOR2X4TS U4007 ( .A(n2994), .B(n2993), .Y(n2992) );
NAND2X4TS U4008 ( .A(n5123), .B(n5122), .Y(n5495) );
NAND2X2TS U4009 ( .A(n2843), .B(n5093), .Y(n2842) );
NAND2X4TS U4010 ( .A(DP_OP_496J2_122_3540_n1462), .B(FPMULT_Op_MY[6]), .Y(
n3878) );
XNOR2X4TS U4011 ( .A(n4704), .B(n4703), .Y(n7207) );
OR2X4TS U4012 ( .A(FPMULT_Op_MX[22]), .B(n2274), .Y(n3850) );
OAI22X2TS U4013 ( .A0(n4941), .A1(n5210), .B0(n5175), .B1(n5209), .Y(n5176)
);
NAND2X6TS U4014 ( .A(n4563), .B(n4562), .Y(n4950) );
OAI22X4TS U4015 ( .A0(n2837), .A1(n4440), .B0(n2379), .B1(n4491), .Y(n4386)
);
NAND2X4TS U4016 ( .A(n3015), .B(n3014), .Y(n4263) );
NAND2X6TS U4017 ( .A(n5449), .B(n2267), .Y(n5450) );
NOR2X4TS U4018 ( .A(n5697), .B(n2319), .Y(DP_OP_499J2_125_1651_n62) );
OR2X2TS U4019 ( .A(n1521), .B(n5795), .Y(n5796) );
NAND3X8TS U4020 ( .A(n3135), .B(n3042), .C(n5282), .Y(n3039) );
NAND2X4TS U4021 ( .A(n3087), .B(n3086), .Y(n3085) );
CLKAND2X2TS U4022 ( .A(n5698), .B(n3000), .Y(n2319) );
NAND2X4TS U4023 ( .A(n4523), .B(n4522), .Y(n3017) );
INVX6TS U4024 ( .A(n2613), .Y(n2599) );
NAND2X4TS U4025 ( .A(n2264), .B(n2833), .Y(n2832) );
NAND2X2TS U4026 ( .A(n4773), .B(n4772), .Y(n4775) );
OAI2BB1X4TS U4027 ( .A0N(n2824), .A1N(n5364), .B0(n5495), .Y(n2265) );
NAND2X2TS U4028 ( .A(n2755), .B(n3515), .Y(n3715) );
NAND2X6TS U4029 ( .A(n2726), .B(n2806), .Y(n2846) );
NOR2BX2TS U4030 ( .AN(n2382), .B(n2429), .Y(n3999) );
ADDFHX4TS U4031 ( .A(n3892), .B(n3891), .CI(n3890), .CO(n3928), .S(n4578) );
XOR2X4TS U4032 ( .A(n5105), .B(n4564), .Y(n2266) );
NAND2X6TS U4033 ( .A(n2575), .B(n2574), .Y(n3596) );
NOR2X6TS U4034 ( .A(n3632), .B(n3681), .Y(n2930) );
NAND2X4TS U4035 ( .A(n4425), .B(n4424), .Y(n4469) );
NAND2X4TS U4036 ( .A(n4427), .B(n4426), .Y(n4641) );
INVX6TS U4037 ( .A(n2999), .Y(n2848) );
NAND2X8TS U4038 ( .A(n3120), .B(n3190), .Y(n2983) );
OR2X6TS U4039 ( .A(n4869), .B(n4868), .Y(n3120) );
ADDHX4TS U4040 ( .A(n3981), .B(n4574), .CO(n3921), .S(n4016) );
INVX4TS U4041 ( .A(n4576), .Y(n3981) );
NOR2X8TS U4042 ( .A(n2702), .B(n5329), .Y(n2897) );
NOR2X2TS U4043 ( .A(n3992), .B(n3072), .Y(n3066) );
BUFX8TS U4044 ( .A(n2889), .Y(n2604) );
OAI22X4TS U4045 ( .A0(n2303), .A1(n4004), .B0(n3924), .B1(n2593), .Y(n4058)
);
INVX12TS U4046 ( .A(n2287), .Y(n2843) );
OAI21X2TS U4047 ( .A0(n4662), .A1(n4857), .B0(n4858), .Y(n4663) );
BUFX16TS U4048 ( .A(n2824), .Y(n2667) );
AOI21X2TS U4049 ( .A0(n5591), .A1(n2701), .B0(n5594), .Y(n5628) );
OAI22X2TS U4050 ( .A0(n2231), .A1(n4112), .B0(n4918), .B1(n5416), .Y(n4919)
);
NAND2X6TS U4051 ( .A(n3501), .B(n3502), .Y(n2770) );
NAND2X8TS U4052 ( .A(n5696), .B(n5689), .Y(n3010) );
OAI21X2TS U4053 ( .A0(n3288), .A1(n3287), .B0(n3286), .Y(n3375) );
XNOR2X4TS U4054 ( .A(n3787), .B(n2430), .Y(n3798) );
INVX6TS U4055 ( .A(n5746), .Y(n3127) );
NAND2X8TS U4056 ( .A(n2678), .B(n2677), .Y(n2806) );
INVX4TS U4057 ( .A(n4563), .Y(n2678) );
OAI2BB1X2TS U4058 ( .A0N(n3423), .A1N(n2542), .B0(n2541), .Y(n3435) );
NOR2X6TS U4059 ( .A(n5441), .B(n5440), .Y(n5546) );
NAND2X6TS U4060 ( .A(n2848), .B(n2806), .Y(n2847) );
INVX8TS U4061 ( .A(n5735), .Y(n5754) );
XNOR2X2TS U4062 ( .A(n5462), .B(n5461), .Y(n5484) );
OR2X2TS U4063 ( .A(n4797), .B(n4796), .Y(n3155) );
NOR2X6TS U4064 ( .A(n4577), .B(n4576), .Y(n4771) );
INVX8TS U4065 ( .A(n5546), .Y(n2522) );
NAND3X6TS U4066 ( .A(n2747), .B(n2743), .C(n5284), .Y(n3100) );
NAND2X8TS U4067 ( .A(n2566), .B(n2905), .Y(n3003) );
XOR2X4TS U4068 ( .A(n5205), .B(n5167), .Y(n4010) );
NAND2X4TS U4069 ( .A(n2282), .B(n5727), .Y(n3030) );
NAND2X4TS U4070 ( .A(n4226), .B(n4225), .Y(n4306) );
ADDFHX2TS U4071 ( .A(n4286), .B(n4285), .CI(n4284), .CO(n4345), .S(n4225) );
NOR2X2TS U4072 ( .A(n4483), .B(n4973), .Y(n4546) );
NOR2X4TS U4073 ( .A(n4483), .B(n4397), .Y(n4353) );
INVX12TS U4074 ( .A(n2667), .Y(n5095) );
INVX8TS U4075 ( .A(n5094), .Y(n2272) );
XOR2X4TS U4076 ( .A(n2273), .B(n5179), .Y(n3961) );
INVX2TS U4077 ( .A(n5198), .Y(n2273) );
BUFX12TS U4078 ( .A(n3963), .Y(n5416) );
NAND2X4TS U4079 ( .A(n3888), .B(n3887), .Y(n2586) );
NAND2BX2TS U4080 ( .AN(n5142), .B(n4648), .Y(n3129) );
XNOR2X4TS U4081 ( .A(n3806), .B(n2439), .Y(n3893) );
AOI22X2TS U4082 ( .A0(n6097), .A1(n6371), .B0(FPADDSUB_Raw_mant_NRM_SWR[25]),
.B1(n7599), .Y(n6098) );
OAI21X4TS U4083 ( .A0(n6153), .A1(n6147), .B0(n6148), .Y(n6143) );
OAI21X2TS U4084 ( .A0(n7153), .A1(n7165), .B0(n7154), .Y(n6381) );
NAND2X6TS U4085 ( .A(n5436), .B(n5435), .Y(n5690) );
NAND2X2TS U4086 ( .A(n2860), .B(n3051), .Y(n2904) );
NAND2X4TS U4087 ( .A(n3754), .B(n3753), .Y(n3809) );
OAI22X2TS U4088 ( .A0(n3934), .A1(n5209), .B0(n5210), .B1(n5212), .Y(n3956)
);
INVX8TS U4089 ( .A(n3880), .Y(n4605) );
BUFX12TS U4090 ( .A(n2823), .Y(n2829) );
NAND2X8TS U4091 ( .A(n2272), .B(n2843), .Y(n2841) );
AND2X8TS U4092 ( .A(n3062), .B(n2333), .Y(n2287) );
NOR2X4TS U4093 ( .A(n2442), .B(n3964), .Y(n3889) );
OR2X8TS U4094 ( .A(n4425), .B(n4424), .Y(n2321) );
INVX4TS U4095 ( .A(n5407), .Y(n5481) );
NAND2X4TS U4096 ( .A(n3835), .B(n2699), .Y(n3854) );
XOR2X4TS U4097 ( .A(n2285), .B(n2707), .Y(n3868) );
NAND3X6TS U4098 ( .A(n2572), .B(n2984), .C(n2571), .Y(n2570) );
OR2X8TS U4099 ( .A(n4893), .B(n4892), .Y(n2984) );
OR2X8TS U4100 ( .A(n4846), .B(n4845), .Y(n3189) );
INVX8TS U4101 ( .A(n5118), .Y(n4505) );
INVX2TS U4102 ( .A(n5661), .Y(n5258) );
ADDFHX2TS U4103 ( .A(n5265), .B(n5264), .CI(n5263), .CO(n5266), .S(n5661) );
XOR2X2TS U4104 ( .A(n2441), .B(n3787), .Y(n3788) );
INVX6TS U4105 ( .A(n5127), .Y(n5356) );
OAI21X1TS U4106 ( .A0(n5510), .A1(n5385), .B0(n5387), .Y(n5369) );
INVX6TS U4107 ( .A(n2658), .Y(n2836) );
NAND2X8TS U4108 ( .A(n2715), .B(n4641), .Y(n3016) );
OAI21X4TS U4109 ( .A0(n4235), .A1(n4234), .B0(n4233), .Y(n4264) );
NOR2X4TS U4110 ( .A(n4183), .B(n4182), .Y(n4235) );
AND2X8TS U4111 ( .A(n5537), .B(n5538), .Y(n3079) );
NOR2X8TS U4112 ( .A(n5535), .B(n5531), .Y(n5537) );
NAND2X4TS U4113 ( .A(n3227), .B(n3249), .Y(n3228) );
NAND2X4TS U4114 ( .A(n3397), .B(n3412), .Y(n3249) );
NOR2X8TS U4115 ( .A(n3553), .B(n3554), .Y(n2549) );
NAND2X4TS U4116 ( .A(n2639), .B(n2874), .Y(n2592) );
INVX4TS U4117 ( .A(n2639), .Y(n2713) );
OAI21X4TS U4118 ( .A0(n3544), .A1(n3543), .B0(n3542), .Y(n2680) );
INVX6TS U4119 ( .A(n5608), .Y(n5638) );
NOR2X2TS U4120 ( .A(n7520), .B(n7548), .Y(n7519) );
XNOR2X4TS U4121 ( .A(n3110), .B(n2430), .Y(n4100) );
NAND2X6TS U4122 ( .A(FPMULT_Sgf_operation_EVEN1_S_B[18]), .B(
FPMULT_Sgf_operation_EVEN1_Q_left[6]), .Y(add_x_69_n188) );
ADDFHX4TS U4123 ( .A(n4963), .B(n4962), .CI(n4961), .CO(n5022), .S(n4952) );
OAI21X1TS U4124 ( .A0(n5022), .A1(n5021), .B0(n5020), .Y(n2852) );
NOR2X4TS U4125 ( .A(n2860), .B(n3048), .Y(n7244) );
OAI22X2TS U4126 ( .A0(n2349), .A1(n3446), .B0(n3664), .B1(n3422), .Y(n3437)
);
XNOR2X4TS U4127 ( .A(n4936), .B(n4938), .Y(n3978) );
OAI21X4TS U4128 ( .A0(n7244), .A1(n7240), .B0(n7245), .Y(n6211) );
NAND2X4TS U4129 ( .A(n2863), .B(n2861), .Y(n4485) );
OAI2BB2X4TS U4130 ( .B0(n2349), .B1(DP_OP_497J2_123_1725_n312), .A0N(n3611),
.A1N(n7708), .Y(n3643) );
NAND2BX4TS U4131 ( .AN(n3818), .B(n3805), .Y(n2277) );
OR2X8TS U4132 ( .A(n4086), .B(n4085), .Y(n4645) );
ADDFHX4TS U4133 ( .A(n4132), .B(n4131), .CI(n4130), .CO(n4134), .S(n4086) );
OAI22X4TS U4134 ( .A0(n3925), .A1(n2593), .B0(n2303), .B1(n3924), .Y(n3938)
);
ADDFHX2TS U4135 ( .A(n3372), .B(n3371), .CI(n3370), .CO(n3382), .S(n3377) );
NOR2X8TS U4136 ( .A(n5235), .B(n5234), .Y(n5319) );
ADDFHX4TS U4137 ( .A(n5172), .B(n5171), .CI(n5170), .CO(n5229), .S(n5191) );
OAI21X4TS U4138 ( .A0(n2231), .A1(n2354), .B0(n3966), .Y(n4097) );
ADDFHX4TS U4139 ( .A(n4129), .B(n4128), .CI(n4127), .CO(n4909), .S(n4132) );
ADDFHX4TS U4140 ( .A(n3919), .B(n3918), .CI(n3917), .CO(n4129), .S(n3991) );
NAND3X6TS U4141 ( .A(n2694), .B(n2693), .C(n2692), .Y(n2691) );
NAND2X6TS U4142 ( .A(n2939), .B(n2817), .Y(n3785) );
INVX2TS U4143 ( .A(n3775), .Y(n2939) );
XNOR2X4TS U4144 ( .A(n3774), .B(n3773), .Y(n2817) );
NOR2X6TS U4145 ( .A(n2868), .B(n3298), .Y(n3293) );
NOR2X6TS U4146 ( .A(n6248), .B(n5518), .Y(n5532) );
OAI22X2TS U4147 ( .A0(n5031), .A1(n5070), .B0(n5030), .B1(n5029), .Y(n5074)
);
NAND2X4TS U4148 ( .A(n2983), .B(n5491), .Y(n2571) );
XOR2X4TS U4149 ( .A(n4819), .B(n4820), .Y(n2805) );
NAND2X8TS U4150 ( .A(n2998), .B(n2999), .Y(n5066) );
ADDFHX4TS U4151 ( .A(n3552), .B(n3551), .CI(n3550), .CO(n3554), .S(n3464) );
OAI22X2TS U4152 ( .A0(n2349), .A1(n3441), .B0(n2434), .B1(n3519), .Y(n3436)
);
NAND2X4TS U4153 ( .A(n4180), .B(n4218), .Y(n3058) );
NAND2BX4TS U4154 ( .AN(n3166), .B(n6893), .Y(n3840) );
NAND2X4TS U4155 ( .A(n4014), .B(n4037), .Y(n3064) );
NOR2X4TS U4156 ( .A(n3066), .B(n3065), .Y(n4037) );
NOR2X6TS U4157 ( .A(n3240), .B(DP_OP_497J2_123_1725_n638), .Y(n3206) );
OAI2BB1X2TS U4158 ( .A0N(n2864), .A1N(n2866), .B0(n4457), .Y(n2863) );
BUFX8TS U4159 ( .A(DP_OP_498J2_124_1725_n797), .Y(n6893) );
ADDFHX4TS U4160 ( .A(n3549), .B(n3548), .CI(n3547), .CO(n3577), .S(n3552) );
OAI2BB1X4TS U4161 ( .A0N(n3418), .A1N(n3417), .B0(n2716), .Y(n3439) );
OAI21X4TS U4162 ( .A0(n3417), .A1(n3418), .B0(n3416), .Y(n2716) );
NAND2X8TS U4163 ( .A(n2908), .B(n3716), .Y(n3097) );
NAND3X8TS U4164 ( .A(n2752), .B(n3722), .C(n2751), .Y(n2908) );
INVX2TS U4165 ( .A(n4235), .Y(n4184) );
OAI22X2TS U4166 ( .A0(n3409), .A1(n3612), .B0(n3342), .B1(n2299), .Y(n3415)
);
OAI22X4TS U4167 ( .A0(n2837), .A1(n4955), .B0(n4549), .B1(n5032), .Y(n4554)
);
INVX16TS U4168 ( .A(n2776), .Y(n3521) );
NAND2BX1TS U4169 ( .AN(n3318), .B(n2776), .Y(n2778) );
OAI22X2TS U4170 ( .A0(n4970), .A1(n2603), .B0(n4537), .B1(n2378), .Y(n4341)
);
OAI21X1TS U4171 ( .A0(n7230), .A1(n7229), .B0(n7228), .Y(n7235) );
AND2X6TS U4172 ( .A(n3904), .B(n3110), .Y(n3078) );
OAI21X4TS U4173 ( .A0(n3399), .A1(n2556), .B0(n3398), .Y(n2554) );
NAND2X6TS U4174 ( .A(DP_OP_497J2_123_1725_n782), .B(
DP_OP_497J2_123_1725_n793), .Y(n2916) );
NAND2X4TS U4175 ( .A(n5707), .B(DP_OP_497J2_123_1725_n793), .Y(n2761) );
OAI2BB1X4TS U4176 ( .A0N(n3267), .A1N(n3266), .B0(n2910), .Y(n3522) );
NAND2X4TS U4177 ( .A(n2283), .B(n4904), .Y(n2525) );
NAND2X6TS U4178 ( .A(n2283), .B(n2583), .Y(n2582) );
NAND3X6TS U4179 ( .A(n4645), .B(n2695), .C(n2283), .Y(n2584) );
OAI22X2TS U4180 ( .A0(n5031), .A1(n4550), .B0(n5071), .B1(n4495), .Y(n4540)
);
ADDFHX2TS U4181 ( .A(n5415), .B(n5414), .CI(n5413), .CO(n5569), .S(n5424) );
XNOR2X4TS U4182 ( .A(n5570), .B(n5198), .Y(n5251) );
OAI22X4TS U4183 ( .A0(n4923), .A1(n2237), .B0(n5338), .B1(n4107), .Y(n4912)
);
OAI22X2TS U4184 ( .A0(n2436), .A1(n4537), .B0(n2377), .B1(n4970), .Y(n4409)
);
OAI2BB1X4TS U4185 ( .A0N(n4335), .A1N(n4334), .B0(n4333), .Y(n4408) );
NOR2BX2TS U4186 ( .AN(n3740), .B(n3093), .Y(n3131) );
NOR2X4TS U4187 ( .A(DP_OP_497J2_123_1725_n631), .B(n2320), .Y(n3208) );
NOR2X4TS U4188 ( .A(DP_OP_497J2_123_1725_n631), .B(n3479), .Y(n2976) );
NOR2X4TS U4189 ( .A(DP_OP_497J2_123_1725_n631), .B(DP_OP_497J2_123_1725_n638), .Y(n4730) );
NOR2X4TS U4190 ( .A(DP_OP_497J2_123_1725_n631), .B(n3220), .Y(n3205) );
NAND2X6TS U4191 ( .A(n2742), .B(n3102), .Y(n2747) );
NOR2X8TS U4192 ( .A(n2630), .B(n3690), .Y(n5312) );
NAND2X8TS U4193 ( .A(n4514), .B(n4515), .Y(n4526) );
XOR2X4TS U4194 ( .A(n2754), .B(n2908), .Y(n4676) );
OA21X2TS U4195 ( .A0(n3514), .A1(n3513), .B0(n3512), .Y(n2312) );
NOR2X4TS U4196 ( .A(n2236), .B(n3516), .Y(n3091) );
OAI22X2TS U4197 ( .A0(n2351), .A1(n3441), .B0(n3342), .B1(n3519), .Y(n3350)
);
ADDFHX4TS U4198 ( .A(n5241), .B(n5240), .CI(n5239), .CO(n5334), .S(n5267) );
ADDFHX4TS U4199 ( .A(n5250), .B(n5249), .CI(n5248), .CO(n5351), .S(n5240) );
ADDFHX4TS U4200 ( .A(n5639), .B(n5638), .CI(n3149), .CO(n5648), .S(n5626) );
ADDFHX4TS U4201 ( .A(n4289), .B(n4288), .CI(n4287), .CO(n4344), .S(n4226) );
ADDFHX4TS U4202 ( .A(n4789), .B(n4014), .CI(n4013), .CO(n4046), .S(n4035) );
NOR2BX2TS U4203 ( .AN(n4027), .B(n4933), .Y(n4947) );
OAI21X4TS U4204 ( .A0(n3768), .A1(n3782), .B0(n3885), .Y(n3777) );
ADDFHX2TS U4205 ( .A(n4023), .B(n4022), .CI(n4021), .CO(n4036), .S(n4031) );
NOR2X4TS U4206 ( .A(n5565), .B(n5563), .Y(n5591) );
XNOR2X4TS U4207 ( .A(n5419), .B(n5345), .Y(n5346) );
OAI22X2TS U4208 ( .A0(n5165), .A1(n2303), .B0(n2593), .B1(n5207), .Y(n5227)
);
NAND2X8TS U4209 ( .A(n4946), .B(n4945), .Y(n2619) );
ADDFHX2TS U4210 ( .A(n3946), .B(n3945), .CI(n3944), .CO(n4091), .S(n3988) );
ADDFHX2TS U4211 ( .A(n5184), .B(n5604), .CI(n5183), .CO(n5217), .S(n5163) );
NOR2X6TS U4212 ( .A(n5644), .B(n5643), .Y(n5646) );
ADDFHX4TS U4213 ( .A(n3382), .B(n3381), .CI(n3380), .CO(n3424), .S(n3387) );
NOR2X4TS U4214 ( .A(n5097), .B(n5099), .Y(n5102) );
NOR2X6TS U4215 ( .A(n5079), .B(n5078), .Y(n5099) );
NAND2X4TS U4216 ( .A(n4972), .B(n3173), .Y(n4401) );
OAI21X4TS U4217 ( .A0(n5762), .A1(n5735), .B0(n2977), .Y(add_x_69_n205) );
OAI22X2TS U4218 ( .A0(n3409), .A1(n3571), .B0(n3342), .B1(n3606), .Y(n3366)
);
AND2X4TS U4219 ( .A(n3035), .B(n3034), .Y(n4273) );
INVX2TS U4220 ( .A(n4363), .Y(n4305) );
ADDFHX4TS U4221 ( .A(n5305), .B(n5304), .CI(n5303), .CO(n5371), .S(n5306) );
NOR2X4TS U4222 ( .A(n4450), .B(DP_OP_498J2_124_1725_n732), .Y(n3035) );
OAI21X4TS U4223 ( .A0(n7121), .A1(n7115), .B0(n7116), .Y(n7111) );
NOR2X4TS U4224 ( .A(n2651), .B(n3082), .Y(n5493) );
NOR2BX2TS U4225 ( .AN(n4108), .B(n4093), .Y(n4029) );
ADDFHX4TS U4226 ( .A(n5217), .B(n5216), .CI(n5215), .CO(n5268), .S(n5231) );
BUFX12TS U4227 ( .A(n3101), .Y(n2742) );
ADDFHX2TS U4228 ( .A(n3437), .B(n3436), .CI(n3435), .CO(n3547), .S(n3438) );
ADDFHX4TS U4229 ( .A(n5164), .B(n5163), .CI(n5162), .CO(n5233), .S(n5194) );
XNOR2X4TS U4230 ( .A(n4916), .B(n5345), .Y(n4112) );
OAI22X2TS U4231 ( .A0(n4002), .A1(n4093), .B0(n4001), .B1(n4094), .Y(n4020)
);
NAND2X4TS U4232 ( .A(n2546), .B(n3711), .Y(n5154) );
OAI21X4TS U4233 ( .A0(n5535), .A1(n5534), .B0(n5533), .Y(n5536) );
XOR2X4TS U4234 ( .A(n2815), .B(n3070), .Y(n4897) );
XOR2X4TS U4235 ( .A(n4065), .B(n2943), .Y(n2942) );
ADDFHX4TS U4236 ( .A(n4082), .B(n4081), .CI(n4080), .CO(n4083), .S(n4076) );
NOR2X6TS U4237 ( .A(n5487), .B(n5486), .Y(n5531) );
ADDFHX2TS U4238 ( .A(n4842), .B(n4841), .CI(n4840), .CO(n4862), .S(n4843) );
NAND2X2TS U4239 ( .A(n4758), .B(n4757), .Y(n4759) );
NOR2BX1TS U4240 ( .AN(n4108), .B(n5416), .Y(n3946) );
NAND2BX1TS U4241 ( .AN(n4108), .B(n5198), .Y(n3947) );
XNOR2X2TS U4242 ( .A(n4108), .B(n5345), .Y(n3967) );
NAND2X4TS U4243 ( .A(n4846), .B(n4845), .Y(n5460) );
INVX4TS U4244 ( .A(n2985), .Y(n2982) );
XNOR2X4TS U4245 ( .A(n3727), .B(n3726), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[7]) );
INVX3TS U4246 ( .A(n3264), .Y(n3726) );
XOR2X2TS U4247 ( .A(n3022), .B(n3287), .Y(n3021) );
NAND2BX2TS U4248 ( .AN(n3023), .B(n3259), .Y(n3022) );
INVX6TS U4249 ( .A(n2509), .Y(n2500) );
ADDFHX4TS U4250 ( .A(n3991), .B(n3990), .CI(n3989), .CO(n4131), .S(n4077) );
OAI22X2TS U4251 ( .A0(n5338), .A1(n3948), .B0(n2376), .B1(n3961), .Y(n3919)
);
NAND2X4TS U4252 ( .A(n4992), .B(n4991), .Y(n5009) );
CMPR22X2TS U4253 ( .A(n4413), .B(n4412), .CO(n4443), .S(n4388) );
NAND2X8TS U4254 ( .A(n5532), .B(n5537), .Y(n5763) );
ADDFHX4TS U4255 ( .A(n4891), .B(n4890), .CI(n4889), .CO(n4892), .S(n4885) );
AOI21X2TS U4256 ( .A0(n4856), .A1(n4664), .B0(n4663), .Y(n4669) );
ADDFHX4TS U4257 ( .A(n3361), .B(n3360), .CI(n3359), .CO(n3391), .S(n3381) );
OAI22X2TS U4258 ( .A0(n3521), .A1(n3441), .B0(n3393), .B1(n3519), .Y(n3360)
);
AND2X4TS U4259 ( .A(n3043), .B(n3737), .Y(n2330) );
NAND2X4TS U4260 ( .A(n4893), .B(n4892), .Y(n5539) );
NOR2X8TS U4261 ( .A(n4946), .B(n4945), .Y(n5197) );
OAI22X4TS U4262 ( .A0(n4095), .A1(n4094), .B0(n5167), .B1(n4093), .Y(n4929)
);
AOI21X4TS U4263 ( .A0(n2834), .A1(n5694), .B0(n5642), .Y(
DP_OP_499J2_125_1651_n34) );
NOR2X8TS U4264 ( .A(n5464), .B(n3153), .Y(n5497) );
OR2X4TS U4265 ( .A(n5494), .B(n3152), .Y(n3153) );
NAND2X8TS U4266 ( .A(n2979), .B(n5739), .Y(n5762) );
XNOR2X4TS U4267 ( .A(n3110), .B(n2438), .Y(n3894) );
XOR2X4TS U4268 ( .A(n4807), .B(n4806), .Y(n4813) );
NAND2X6TS U4269 ( .A(n2280), .B(n2500), .Y(n3063) );
XNOR2X4TS U4270 ( .A(n5179), .B(n4921), .Y(n3924) );
NAND2X4TS U4271 ( .A(n5326), .B(n5325), .Y(n5686) );
NAND2X4TS U4272 ( .A(n4780), .B(n4779), .Y(n4782) );
INVX2TS U4273 ( .A(n4780), .Y(n4022) );
AOI21X4TS U4274 ( .A0(n5141), .A1(n3176), .B0(n4795), .Y(n5053) );
OAI21X2TS U4275 ( .A0(n5130), .A1(n4787), .B0(n5131), .Y(n5141) );
XOR2X4TS U4276 ( .A(n3883), .B(n3880), .Y(n2781) );
XNOR2X4TS U4277 ( .A(n4750), .B(n4856), .Y(n4837) );
NOR2X4TS U4278 ( .A(n5763), .B(n5762), .Y(add_x_69_n204) );
NOR2X4TS U4279 ( .A(n3342), .B(n2298), .Y(n3339) );
XNOR2X4TS U4280 ( .A(n2598), .B(n2597), .Y(n2755) );
NAND2X4TS U4281 ( .A(n3500), .B(n2770), .Y(n2597) );
INVX6TS U4282 ( .A(n5679), .Y(n5689) );
INVX8TS U4283 ( .A(n2882), .Y(n2349) );
OA21X4TS U4284 ( .A0(n3695), .A1(n3694), .B0(n3693), .Y(n2873) );
OAI2BB1X2TS U4285 ( .A0N(n3663), .A1N(n3662), .B0(n2875), .Y(n3672) );
OAI21X2TS U4286 ( .A0(n3662), .A1(n3663), .B0(n3661), .Y(n2875) );
ADDFHX4TS U4287 ( .A(n3670), .B(n3669), .CI(n3668), .CO(n3696), .S(n3663) );
ADDFHX4TS U4288 ( .A(n3434), .B(n3433), .CI(n3432), .CO(n3548), .S(n3440) );
ADDFHX4TS U4289 ( .A(n3431), .B(n3430), .CI(n3429), .CO(n3535), .S(n3433) );
XNOR2X4TS U4290 ( .A(n3135), .B(n4997), .Y(n5719) );
NOR2X4TS U4291 ( .A(n2950), .B(n2240), .Y(n2948) );
ADDHX4TS U4292 ( .A(DP_OP_496J2_122_3540_n1513), .B(FPMULT_Op_MX[19]), .CO(
n3778), .S(n3772) );
ADDFHX4TS U4293 ( .A(n4561), .B(n4560), .CI(n4559), .CO(n4975), .S(n4530) );
ADDFHX4TS U4294 ( .A(n4494), .B(n4493), .CI(n4492), .CO(n4560), .S(n4501) );
ADDFHX2TS U4295 ( .A(n4533), .B(n4532), .CI(n4531), .CO(n4953), .S(n4561) );
NOR2X2TS U4296 ( .A(n5495), .B(n5494), .Y(n5467) );
AOI21X2TS U4297 ( .A0(n5538), .A1(n5526), .B0(n5488), .Y(n5489) );
NOR2X4TS U4298 ( .A(n5040), .B(n5039), .Y(n5097) );
ADDFHX4TS U4299 ( .A(n5069), .B(n5068), .CI(n5067), .CO(n5079), .S(n5039) );
OAI22X2TS U4300 ( .A0(n4633), .A1(n3771), .B0(n4102), .B1(n2644), .Y(n4103)
);
ADDFHX4TS U4301 ( .A(n4883), .B(n4882), .CI(n4881), .CO(n4884), .S(n4869) );
NOR2X8TS U4302 ( .A(n5435), .B(n5436), .Y(n5679) );
XNOR2X4TS U4303 ( .A(n3495), .B(n2922), .Y(n2921) );
NAND3X4TS U4304 ( .A(n2929), .B(n2874), .C(n2930), .Y(n2591) );
NOR2X4TS U4305 ( .A(n3692), .B(n3694), .Y(n2874) );
ADDFHX4TS U4306 ( .A(n5628), .B(n5627), .CI(n5626), .CO(n5641), .S(n5624) );
NAND2X8TS U4307 ( .A(n2624), .B(n2775), .Y(n2795) );
NAND3X6TS U4308 ( .A(n2714), .B(n2770), .C(n3500), .Y(n2624) );
NAND2X6TS U4309 ( .A(n3428), .B(n3427), .Y(n2714) );
OR2X8TS U4310 ( .A(n3089), .B(n3742), .Y(n2318) );
AND2X8TS U4311 ( .A(n3687), .B(n3686), .Y(n3089) );
NOR2X8TS U4312 ( .A(n3687), .B(n3686), .Y(n3742) );
NAND2X4TS U4313 ( .A(n5448), .B(n5447), .Y(n5675) );
XNOR2X4TS U4314 ( .A(n2929), .B(n2637), .Y(n3687) );
NAND2X4TS U4315 ( .A(n2638), .B(n2557), .Y(n2637) );
OR2X4TS U4316 ( .A(n4427), .B(n4426), .Y(n4642) );
XOR2X4TS U4317 ( .A(n4470), .B(n2573), .Y(n4427) );
XOR2X4TS U4318 ( .A(n6252), .B(n6251), .Y(n6253) );
NOR2X8TS U4319 ( .A(n5128), .B(n3105), .Y(n6213) );
BUFX12TS U4320 ( .A(n5127), .Y(n3105) );
ADDFHX4TS U4321 ( .A(n4341), .B(n4340), .CI(n4339), .CO(n4385), .S(n4356) );
NAND2X4TS U4322 ( .A(n3055), .B(n3053), .Y(n4340) );
NOR2X8TS U4323 ( .A(n5236), .B(n5237), .Y(n2702) );
XOR2X4TS U4324 ( .A(n5570), .B(n5167), .Y(n4095) );
NAND2X8TS U4325 ( .A(n2946), .B(n2945), .Y(n5570) );
NAND2X4TS U4326 ( .A(n3775), .B(n3895), .Y(n3783) );
NAND2X4TS U4327 ( .A(n4084), .B(n4083), .Y(n4653) );
ADDFHX4TS U4328 ( .A(n4079), .B(n4078), .CI(n4077), .CO(n4085), .S(n4084) );
OAI2BB1X4TS U4329 ( .A0N(n4900), .A1N(n4899), .B0(n4898), .Y(n4998) );
NAND2BX1TS U4330 ( .AN(n5593), .B(n5592), .Y(n5594) );
OAI21X4TS U4331 ( .A0(n5566), .A1(n5565), .B0(n5564), .Y(n5593) );
OR2X8TS U4332 ( .A(n2781), .B(n2239), .Y(n4633) );
ADDFHX4TS U4333 ( .A(n4543), .B(n4542), .CI(n4541), .CO(n4979), .S(n4528) );
NOR2X8TS U4334 ( .A(n2266), .B(n4570), .Y(n5008) );
XOR2X4TS U4335 ( .A(n5105), .B(n4564), .Y(n4571) );
OAI22X2TS U4336 ( .A0(n5070), .A1(n2603), .B0(n5029), .B1(n2378), .Y(n4444)
);
NOR2X4TS U4337 ( .A(n7237), .B(n7244), .Y(n6212) );
XNOR2X4TS U4338 ( .A(n2890), .B(n2509), .Y(n2700) );
XOR2X4TS U4339 ( .A(n3514), .B(n3253), .Y(n3024) );
XNOR2X4TS U4340 ( .A(n5761), .B(n5760), .Y(FPMULT_Sgf_operation_Result[25])
);
OAI21X4TS U4341 ( .A0(n6252), .A1(n5756), .B0(n5755), .Y(n5761) );
NOR2X8TS U4342 ( .A(n5536), .B(n3079), .Y(n5735) );
NOR2X8TS U4343 ( .A(n5740), .B(n5746), .Y(n2979) );
AND2X8TS U4344 ( .A(n2800), .B(n4790), .Y(n5746) );
NAND2X2TS U4345 ( .A(n3785), .B(n3783), .Y(n3776) );
AOI21X4TS U4346 ( .A0(n5754), .A1(n5739), .B0(n5743), .Y(n5744) );
OAI21X4TS U4347 ( .A0(n5455), .A1(n5456), .B0(n5457), .Y(n5461) );
AOI21X4TS U4348 ( .A0(n5091), .A1(n5089), .B0(n4836), .Y(n5455) );
NAND2X4TS U4349 ( .A(n4843), .B(n4844), .Y(n5457) );
XNOR2X4TS U4350 ( .A(n4767), .B(n4766), .Y(n4799) );
NAND2X2TS U4351 ( .A(n4765), .B(n4764), .Y(n4767) );
NAND2X8TS U4352 ( .A(n3518), .B(n3517), .Y(n3718) );
NOR2X8TS U4353 ( .A(n4999), .B(n4998), .Y(n5672) );
XNOR2X4TS U4354 ( .A(n2700), .B(n5324), .Y(n4999) );
AND2X8TS U4355 ( .A(n5695), .B(n5694), .Y(n7685) );
OR2X4TS U4356 ( .A(n5641), .B(n5640), .Y(n5694) );
NOR2X8TS U4357 ( .A(n2546), .B(n3711), .Y(n5155) );
XOR2X4TS U4358 ( .A(n2547), .B(n2872), .Y(n2546) );
NAND3X4TS U4359 ( .A(n2591), .B(n2592), .C(n2873), .Y(n2547) );
NOR2X8TS U4360 ( .A(n5646), .B(n5691), .Y(n5695) );
NOR2X8TS U4361 ( .A(n5624), .B(n5625), .Y(n5691) );
INVX6TS U4362 ( .A(n2817), .Y(n3895) );
OAI2BB1X4TS U4363 ( .A0N(n4065), .A1N(n2943), .B0(n2941), .Y(n3990) );
XNOR2X4TS U4364 ( .A(n5619), .B(n3187), .Y(n3149) );
OAI21X4TS U4365 ( .A0(n5155), .A1(n5284), .B0(n5154), .Y(n3041) );
CMPR22X2TS U4366 ( .A(n4747), .B(n4746), .CO(n4839), .S(n4823) );
XOR2X4TS U4367 ( .A(n4838), .B(n2645), .Y(n4844) );
XOR2X4TS U4368 ( .A(n4837), .B(n4839), .Y(n2645) );
NOR2X8TS U4369 ( .A(n5512), .B(n5608), .Y(n5535) );
NAND2X2TS U4370 ( .A(n5311), .B(n5309), .Y(n4997) );
ADDFHX4TS U4371 ( .A(n3462), .B(n3461), .CI(n3460), .CO(n3463), .S(n3428) );
ADDFHX2TS U4372 ( .A(n3440), .B(n3439), .CI(n3438), .CO(n3551), .S(n3460) );
XOR2X4TS U4373 ( .A(n2328), .B(n2288), .Y(n3689) );
OAI21X4TS U4374 ( .A0(n5444), .A1(n5443), .B0(n2620), .Y(n2505) );
OAI21X4TS U4375 ( .A0(n2542), .A1(n3423), .B0(n2544), .Y(n2541) );
ADDFHX2TS U4376 ( .A(n3600), .B(n3599), .CI(n3598), .CO(n3649), .S(n3592) );
ADDFHX2TS U4377 ( .A(n4864), .B(n4863), .CI(n4862), .CO(n4881), .S(n4845) );
NAND2X2TS U4378 ( .A(n5364), .B(n2264), .Y(n2822) );
MX2X1TS U4379 ( .A(FPMULT_Op_MX[24]), .B(FPMULT_exp_oper_result[1]), .S0(
FPMULT_FSM_selector_A), .Y(n6973) );
OAI21X2TS U4380 ( .A0(n4334), .A1(n4335), .B0(n4332), .Y(n4333) );
INVX2TS U4381 ( .A(n2727), .Y(n3909) );
NOR3X6TS U4382 ( .A(DP_OP_496J2_122_3540_n1107), .B(
DP_OP_496J2_122_3540_n1113), .C(n2521), .Y(n2520) );
INVX2TS U4383 ( .A(n2986), .Y(n3113) );
INVX12TS U4384 ( .A(n2996), .Y(n4921) );
INVX2TS U4385 ( .A(n4565), .Y(n4296) );
NAND2X4TS U4386 ( .A(n3779), .B(n2967), .Y(n2956) );
INVX2TS U4387 ( .A(DP_OP_496J2_122_3540_n1193), .Y(n2993) );
NAND2X2TS U4388 ( .A(DP_OP_496J2_122_3540_n1499), .B(
DP_OP_496J2_122_3540_n1512), .Y(n2307) );
INVX2TS U4389 ( .A(n2240), .Y(n3008) );
INVX2TS U4390 ( .A(n3623), .Y(n3362) );
NAND2X4TS U4391 ( .A(n2947), .B(n2949), .Y(n2945) );
AOI21X2TS U4392 ( .A0(n3007), .A1(n3923), .B0(n2240), .Y(n2947) );
INVX2TS U4393 ( .A(n2917), .Y(n2914) );
NAND2X1TS U4394 ( .A(n5549), .B(n5548), .Y(n5599) );
NAND2X1TS U4395 ( .A(n5361), .B(n5374), .Y(n5362) );
NAND2X1TS U4396 ( .A(n5630), .B(n5653), .Y(n5606) );
NAND2X1TS U4397 ( .A(n3708), .B(n3707), .Y(n5398) );
NAND2X1TS U4398 ( .A(n5157), .B(n5156), .Y(n5397) );
XOR2X1TS U4399 ( .A(FPMULT_Op_MX[22]), .B(FPMULT_Op_MY[22]), .Y(n2685) );
INVX2TS U4400 ( .A(n3724), .Y(n3020) );
NAND2X1TS U4401 ( .A(n6290), .B(n6194), .Y(n6306) );
MX2X1TS U4402 ( .A(FPMULT_Op_MX[23]), .B(FPMULT_exp_oper_result[0]), .S0(
FPMULT_FSM_selector_A), .Y(n6976) );
MX2X1TS U4403 ( .A(FPMULT_Op_MX[26]), .B(FPMULT_exp_oper_result[3]), .S0(
FPMULT_FSM_selector_A), .Y(n6967) );
CLKAND2X2TS U4404 ( .A(n7870), .B(n2479), .Y(n6079) );
CLKAND2X2TS U4405 ( .A(n7872), .B(n2481), .Y(n5860) );
INVX2TS U4406 ( .A(n4584), .Y(n3944) );
NAND2BX2TS U4407 ( .AN(n4402), .B(n4404), .Y(n2838) );
NAND2X4TS U4408 ( .A(n3141), .B(n7673), .Y(n2654) );
INVX2TS U4409 ( .A(n4615), .Y(n4927) );
NAND2X4TS U4410 ( .A(n2535), .B(n2534), .Y(n2540) );
NAND2X4TS U4411 ( .A(n4526), .B(n4527), .Y(n2724) );
NAND2X4TS U4412 ( .A(n2658), .B(n4526), .Y(n2725) );
INVX4TS U4413 ( .A(n3294), .Y(n3299) );
INVX2TS U4414 ( .A(n2871), .Y(n3301) );
INVX2TS U4415 ( .A(n4936), .Y(n2995) );
NAND2X2TS U4416 ( .A(n3856), .B(n3855), .Y(n3859) );
INVX2TS U4417 ( .A(n5572), .Y(n2352) );
NAND2X4TS U4418 ( .A(n3136), .B(n2880), .Y(n2879) );
NAND2X1TS U4419 ( .A(n3828), .B(n3748), .Y(n3749) );
INVX6TS U4420 ( .A(n3099), .Y(n2560) );
INVX4TS U4421 ( .A(n3557), .Y(n3340) );
INVX2TS U4422 ( .A(n3283), .Y(n3341) );
INVX4TS U4423 ( .A(n3254), .Y(n3441) );
NAND2BXLTS U4424 ( .AN(n7370), .B(n7611), .Y(n5938) );
OAI21X2TS U4425 ( .A0(n4838), .A1(n4839), .B0(n4837), .Y(n2737) );
NOR2X4TS U4426 ( .A(n3044), .B(n6898), .Y(n2961) );
NAND2X4TS U4427 ( .A(n3681), .B(n2557), .Y(n2558) );
INVX4TS U4428 ( .A(n3256), .Y(n3446) );
NAND2X4TS U4429 ( .A(n2934), .B(n2932), .Y(n3478) );
OAI21X2TS U4430 ( .A0(n3269), .A1(n2935), .B0(n3268), .Y(n2934) );
INVX2TS U4431 ( .A(n4371), .Y(n2719) );
NAND2X4TS U4432 ( .A(n4309), .B(n4306), .Y(n2721) );
NOR2X4TS U4433 ( .A(n4160), .B(n4165), .Y(n4172) );
INVX4TS U4434 ( .A(n4223), .Y(n4204) );
NOR2X4TS U4435 ( .A(n4269), .B(n4268), .Y(n4270) );
NAND2X1TS U4436 ( .A(n3466), .B(n3465), .Y(n3625) );
INVX4TS U4437 ( .A(n4188), .Y(n4712) );
INVX4TS U4438 ( .A(n4673), .Y(n4671) );
NAND2X2TS U4439 ( .A(n2284), .B(n3099), .Y(n2796) );
NAND2X2TS U4440 ( .A(n3234), .B(n3233), .Y(n3261) );
INVX2TS U4441 ( .A(n3213), .Y(n2276) );
INVX2TS U4442 ( .A(n3234), .Y(n2596) );
AND2X2TS U4443 ( .A(n5429), .B(n5564), .Y(n5430) );
NOR2X1TS U4444 ( .A(n6195), .B(n7772), .Y(n6307) );
NOR2X1TS U4445 ( .A(n6205), .B(n7768), .Y(n6450) );
AOI2BB1XLTS U4446 ( .A0N(n6051), .A1N(FPADDSUB_Raw_mant_NRM_SWR[23]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n6052) );
AOI2BB1XLTS U4447 ( .A0N(n7823), .A1N(n8629), .B0(n6053), .Y(n6054) );
NOR3XLTS U4448 ( .A(n8646), .B(FPADDSUB_Raw_mant_NRM_SWR[15]), .C(n7807),
.Y(n6053) );
OR2X1TS U4449 ( .A(FPADDSUB_DMP_SFG[9]), .B(FPADDSUB_DmP_mant_SFG_SWR[11]),
.Y(n7131) );
NAND2X1TS U4450 ( .A(n3120), .B(n5463), .Y(n2734) );
NOR3XLTS U4451 ( .A(Data_1[2]), .B(Data_1[5]), .C(Data_1[4]), .Y(n7257) );
MX2X1TS U4452 ( .A(FPMULT_Op_MX[25]), .B(FPMULT_exp_oper_result[2]), .S0(
FPMULT_FSM_selector_A), .Y(n6970) );
NAND2X1TS U4453 ( .A(n5635), .B(n5652), .Y(n5636) );
INVX8TS U4454 ( .A(n3715), .Y(n3516) );
CLKAND2X2TS U4455 ( .A(begin_operation), .B(operation[1]), .Y(n7283) );
NAND3XLTS U4456 ( .A(dataB[28]), .B(dataB[23]), .C(dataB[25]), .Y(n7272) );
AOI31XLTS U4457 ( .A0(n7270), .A1(n7269), .A2(n7268), .B0(n7275), .Y(n7273)
);
INVX2TS U4458 ( .A(n6091), .Y(n5863) );
INVX2TS U4459 ( .A(n6147), .Y(n6149) );
CLKAND2X2TS U4460 ( .A(n7871), .B(n2475), .Y(n6075) );
CLKAND2X2TS U4461 ( .A(n7869), .B(n2477), .Y(n6083) );
OAI21XLTS U4462 ( .A0(n8802), .A1(n7620), .B0(n7572), .Y(n7573) );
OAI21XLTS U4463 ( .A0(n7614), .A1(n8796), .B0(n7579), .Y(n7590) );
OAI21X2TS U4464 ( .A0(n5767), .A1(n6614), .B0(FPMULT_FS_Module_state_reg[1]),
.Y(n6905) );
OAI21X2TS U4465 ( .A0(n6213), .A1(n7251), .B0(n6214), .Y(n5129) );
OAI31X1TS U4466 ( .A0(n2350), .A1(n6263), .A2(n6262), .B0(n7811), .Y(n1690)
);
NOR2X1TS U4467 ( .A(n1335), .B(n1334), .Y(n8299) );
INVX2TS U4468 ( .A(n3785), .Y(n2965) );
ADDFX2TS U4469 ( .A(n6893), .B(DP_OP_496J2_122_3540_n1502), .CI(n3802), .CO(
n3803), .S(n3781) );
NOR2X4TS U4470 ( .A(n4292), .B(n4290), .Y(n2657) );
INVX2TS U4471 ( .A(n4220), .Y(n4290) );
NOR2X1TS U4472 ( .A(n4402), .B(n7700), .Y(n2665) );
ADDFHX2TS U4473 ( .A(DP_OP_496J2_122_3540_n1514), .B(FPMULT_Op_MX[20]), .CI(
n3778), .CO(n3802), .S(n3775) );
INVX2TS U4474 ( .A(n3819), .Y(n3821) );
INVX2TS U4475 ( .A(n4401), .Y(n4405) );
OR2X2TS U4476 ( .A(n4972), .B(n3173), .Y(n4403) );
OAI21X2TS U4477 ( .A0(n4957), .A1(n3108), .B0(n4956), .Y(n3106) );
NOR2X4TS U4478 ( .A(n5706), .B(n6893), .Y(n4292) );
NOR2X2TS U4479 ( .A(n5029), .B(n2603), .Y(n4413) );
NAND2X1TS U4480 ( .A(n7728), .B(DP_OP_496J2_122_3540_n1203), .Y(n3773) );
NAND2X1TS U4481 ( .A(n7716), .B(DP_OP_496J2_122_3540_n1199), .Y(n3780) );
INVX2TS U4482 ( .A(n2966), .Y(n2927) );
INVX2TS U4483 ( .A(n2954), .Y(n2944) );
INVX4TS U4484 ( .A(n5391), .Y(n3108) );
INVX2TS U4485 ( .A(n4251), .Y(n4555) );
OAI22X1TS U4486 ( .A0(n4536), .A1(n4537), .B0(n4954), .B1(n4970), .Y(n4539)
);
INVX2TS U4487 ( .A(n5366), .Y(n4532) );
INVX2TS U4488 ( .A(n5365), .Y(n4533) );
NAND2X1TS U4489 ( .A(n2303), .B(n5208), .Y(n3036) );
INVX2TS U4490 ( .A(n5207), .Y(n3038) );
NAND2X4TS U4491 ( .A(n2382), .B(n3772), .Y(n3885) );
NAND2X6TS U4492 ( .A(n3808), .B(n3161), .Y(n2986) );
OAI21X2TS U4493 ( .A0(FPMULT_Op_MY[22]), .A1(FPMULT_Op_MY[10]), .B0(n2576),
.Y(n2577) );
XNOR2X2TS U4494 ( .A(n5198), .B(n4916), .Y(n3948) );
NAND2X1TS U4495 ( .A(n2523), .B(n3907), .Y(n3998) );
XNOR2X2TS U4496 ( .A(n4921), .B(n4916), .Y(n4004) );
INVX4TS U4497 ( .A(n4292), .Y(n2858) );
OR2X4TS U4498 ( .A(n4242), .B(n4483), .Y(n4291) );
INVX2TS U4499 ( .A(n4985), .Y(n4332) );
NAND2X2TS U4500 ( .A(n4300), .B(n3056), .Y(n3055) );
NAND2X1TS U4501 ( .A(n4566), .B(n3058), .Y(n3056) );
NAND2BX1TS U4502 ( .AN(n4566), .B(n3054), .Y(n3053) );
INVX2TS U4503 ( .A(n3058), .Y(n3054) );
CLKXOR2X2TS U4504 ( .A(n3790), .B(n2430), .Y(n3792) );
NOR2X2TS U4505 ( .A(n7733), .B(DP_OP_496J2_122_3540_n1192), .Y(n2967) );
NOR2X2TS U4506 ( .A(DP_OP_496J2_122_3540_n1192), .B(
DP_OP_496J2_122_3540_n1199), .Y(n2994) );
NOR2X4TS U4507 ( .A(n2953), .B(n8343), .Y(n2954) );
OR2X4TS U4508 ( .A(n8519), .B(DP_OP_496J2_122_3540_n1498), .Y(n3870) );
NAND2X1TS U4509 ( .A(n4397), .B(n3167), .Y(n3068) );
OR2X2TS U4510 ( .A(n3806), .B(n6898), .Y(n3904) );
NAND2X1TS U4511 ( .A(n3873), .B(n2307), .Y(n3874) );
INVX2TS U4512 ( .A(n3875), .Y(n2535) );
NAND2X2TS U4513 ( .A(n3876), .B(n3877), .Y(n2534) );
OAI22X1TS U4514 ( .A0(n5031), .A1(n4970), .B0(n5071), .B1(n4537), .Y(n4961)
);
NOR2X2TS U4515 ( .A(n5071), .B(n4970), .Y(n5027) );
NAND2X4TS U4516 ( .A(n3177), .B(n3178), .Y(n3279) );
XOR2X1TS U4517 ( .A(n3764), .B(n3758), .Y(n3759) );
BUFX3TS U4518 ( .A(n5208), .Y(n2593) );
INVX2TS U4519 ( .A(n4921), .Y(n5207) );
XNOR2X2TS U4520 ( .A(n5252), .B(n5345), .Y(n5221) );
INVX2TS U4521 ( .A(n2866), .Y(n2862) );
INVX2TS U4522 ( .A(n2867), .Y(n2864) );
INVX2TS U4523 ( .A(n5276), .Y(n2698) );
INVX2TS U4524 ( .A(n4018), .Y(n4038) );
INVX2TS U4525 ( .A(n2849), .Y(n2675) );
INVX4TS U4526 ( .A(n4180), .Y(n2603) );
INVX2TS U4527 ( .A(n2314), .Y(n2378) );
ADDFX2TS U4528 ( .A(n4473), .B(n4203), .CI(n4202), .CO(n4232), .S(n4208) );
ADDFHX2TS U4529 ( .A(n4433), .B(n4432), .CI(n4431), .CO(n4479), .S(n4428) );
INVX2TS U4530 ( .A(n4350), .Y(n4382) );
NOR2X6TS U4531 ( .A(DP_OP_498J2_124_1725_n635), .B(n2953), .Y(n2812) );
NAND2X2TS U4532 ( .A(n8519), .B(n7694), .Y(n2813) );
ADDFHX2TS U4533 ( .A(n4246), .B(n4245), .CI(n4244), .CO(n4252), .S(n4247) );
NOR2X1TS U4534 ( .A(DP_OP_498J2_124_1725_n635), .B(n4242), .Y(n4246) );
ADDFHX2TS U4535 ( .A(n4241), .B(n4240), .CI(n4239), .CO(n4254), .S(n4248) );
NOR2X2TS U4536 ( .A(n4160), .B(n4243), .Y(n4240) );
NOR2X2TS U4537 ( .A(n2245), .B(n7698), .Y(n4241) );
NOR2X2TS U4538 ( .A(n3173), .B(DP_OP_498J2_124_1725_n635), .Y(n2785) );
AND2X2TS U4539 ( .A(FPMULT_Op_MX[20]), .B(DP_OP_496J2_122_3540_n1514), .Y(
n3829) );
INVX2TS U4540 ( .A(n3748), .Y(n3830) );
NAND2X2TS U4541 ( .A(n2986), .B(n3007), .Y(n2949) );
INVX2TS U4542 ( .A(n3110), .Y(n4625) );
OR2X2TS U4543 ( .A(FPMULT_Op_MX[19]), .B(DP_OP_496J2_122_3540_n1513), .Y(
n3828) );
XNOR2X2TS U4544 ( .A(n3951), .B(n4936), .Y(n3994) );
OAI22X2TS U4545 ( .A0(n2433), .A1(n3571), .B0(n3521), .B1(n3606), .Y(n3536)
);
AND2X2TS U4546 ( .A(n3408), .B(DP_OP_497J2_123_1725_n324), .Y(n3411) );
INVX2TS U4547 ( .A(n2916), .Y(n2913) );
XNOR2X2TS U4548 ( .A(n3931), .B(n4936), .Y(n3992) );
INVX2TS U4549 ( .A(n4921), .Y(n2278) );
NAND2BX1TS U4550 ( .AN(n4920), .B(n4616), .Y(n2705) );
XNOR2X2TS U4551 ( .A(n5570), .B(n4921), .Y(n5165) );
INVX2TS U4552 ( .A(n5380), .Y(n4128) );
ADDFHX2TS U4553 ( .A(n4126), .B(n4125), .CI(n4124), .CO(n4910), .S(n4087) );
INVX2TS U4554 ( .A(n5381), .Y(n4124) );
INVX2TS U4555 ( .A(n5548), .Y(n4924) );
ADDFX2TS U4556 ( .A(n5109), .B(n5108), .CI(n5107), .CO(n5110), .S(n5078) );
NOR2XLTS U4557 ( .A(n5071), .B(n5070), .Y(n5109) );
NAND2X2TS U4558 ( .A(FPMULT_Op_MY[9]), .B(DP_OP_498J2_124_1725_n797), .Y(
n2866) );
INVX8TS U4559 ( .A(FPMULT_Op_MX[11]), .Y(n4972) );
INVX6TS U4560 ( .A(DP_OP_496J2_122_3540_n1478), .Y(n4973) );
NOR2X1TS U4561 ( .A(n4661), .B(n4857), .Y(n4664) );
NAND2X1TS U4562 ( .A(n4667), .B(n4666), .Y(n4668) );
AOI21X2TS U4563 ( .A0(n4856), .A1(n4855), .B0(n4854), .Y(n4861) );
NAND2X1TS U4564 ( .A(n4859), .B(n4858), .Y(n4860) );
NAND2X1TS U4565 ( .A(n4749), .B(n4748), .Y(n4750) );
AO21X1TS U4566 ( .A0(n2302), .A1(n4699), .B0(n4030), .Y(n3156) );
ADDFHX2TS U4567 ( .A(n4358), .B(n4357), .CI(n4356), .CO(n4378), .S(n4303) );
NAND2X1TS U4568 ( .A(n4579), .B(n4578), .Y(n4764) );
OR2X1TS U4569 ( .A(n4578), .B(n4579), .Y(n4765) );
AOI2BB1X2TS U4570 ( .A0N(n3840), .A1N(n2709), .B0(n3848), .Y(n2708) );
NAND2X4TS U4571 ( .A(n3871), .B(n3873), .Y(n2960) );
XNOR2X2TS U4572 ( .A(n4938), .B(n4006), .Y(n3932) );
NAND2BX1TS U4573 ( .AN(n4027), .B(n4940), .Y(n3934) );
INVX2TS U4574 ( .A(n5419), .Y(n5420) );
AO21X1TS U4575 ( .A0(n4627), .A1(n4626), .B0(n2271), .Y(n4629) );
NOR2X4TS U4576 ( .A(DP_OP_497J2_123_1725_n324), .B(DP_OP_497J2_123_1725_n631), .Y(n2915) );
NOR2X1TS U4577 ( .A(n3994), .B(n3993), .Y(n3065) );
NAND2X1TS U4578 ( .A(n3993), .B(n3750), .Y(n4003) );
INVX2TS U4579 ( .A(n5103), .Y(n5016) );
INVX2TS U4580 ( .A(n5097), .Y(n5065) );
AND2X2TS U4581 ( .A(n4983), .B(n5015), .Y(n3159) );
NAND3X4TS U4582 ( .A(n2228), .B(n5066), .C(n5065), .Y(n2827) );
NAND2X4TS U4583 ( .A(n5103), .B(n5065), .Y(n2826) );
NAND2X1TS U4584 ( .A(n4586), .B(n4585), .Y(n4830) );
ADDFHX2TS U4585 ( .A(n3594), .B(n3593), .CI(n3592), .CO(n3635), .S(n3618) );
ADDFHX2TS U4586 ( .A(n3649), .B(n3648), .CI(n3647), .CO(n3661), .S(n3633) );
NOR2X4TS U4587 ( .A(n3651), .B(n3650), .Y(n3692) );
NOR2X2TS U4588 ( .A(n2326), .B(DP_OP_497J2_123_1725_n324), .Y(n2922) );
NOR2X4TS U4589 ( .A(n2870), .B(n3479), .Y(n2935) );
INVX2TS U4590 ( .A(n2935), .Y(n2933) );
INVX2TS U4591 ( .A(n5234), .Y(n3118) );
INVX2TS U4592 ( .A(n4914), .Y(n5190) );
ADDFHX2TS U4593 ( .A(n5230), .B(n5229), .CI(n5228), .CO(n5239), .S(n5232) );
CLKXOR2X2TS U4594 ( .A(n4632), .B(n5418), .Y(n5415) );
INVX2TS U4595 ( .A(n2731), .Y(n4656) );
INVX2TS U4596 ( .A(n2695), .Y(n4646) );
NAND2X1TS U4597 ( .A(n5367), .B(n5386), .Y(n5368) );
NAND2X1TS U4598 ( .A(n2302), .B(n4698), .Y(n4700) );
INVX2TS U4599 ( .A(n4686), .Y(n4688) );
NAND2X1TS U4600 ( .A(n4695), .B(n4694), .Y(n4696) );
NAND2X1TS U4601 ( .A(n5466), .B(n5465), .Y(n5494) );
CLKXOR2X2TS U4602 ( .A(n5510), .B(n5121), .Y(n5122) );
NAND2X1TS U4603 ( .A(n5120), .B(n5387), .Y(n5121) );
NOR2X1TS U4604 ( .A(n4984), .B(n4985), .Y(n5047) );
NAND2X1TS U4605 ( .A(n4985), .B(n4984), .Y(n5046) );
AOI21X1TS U4606 ( .A0(n3182), .A1(n4989), .B0(n4988), .Y(n5048) );
INVX2TS U4607 ( .A(n5136), .Y(n4675) );
NAND2X1TS U4608 ( .A(n3142), .B(n4638), .Y(n4639) );
NAND2X2TS U4609 ( .A(n4264), .B(n4263), .Y(n2903) );
INVX2TS U4610 ( .A(n4236), .Y(n3014) );
INVX2TS U4611 ( .A(n4237), .Y(n3015) );
NAND2X2TS U4612 ( .A(DP_OP_498J2_124_1725_n802), .B(n7694), .Y(n2850) );
ADDFHX2TS U4613 ( .A(n4156), .B(DP_OP_498J2_124_1725_n631), .CI(n4155), .CO(
n4159), .S(n4168) );
NOR2X2TS U4614 ( .A(DP_OP_498J2_124_1725_n636), .B(n4165), .Y(n4156) );
NOR2X2TS U4615 ( .A(n4160), .B(n7698), .Y(n4155) );
NAND2X4TS U4616 ( .A(n2660), .B(n4361), .Y(n4377) );
OR2X1TS U4617 ( .A(n4519), .B(n4518), .Y(n3168) );
OR2X1TS U4618 ( .A(n4473), .B(n4472), .Y(n4474) );
INVX2TS U4619 ( .A(n4803), .Y(n4805) );
OR2X4TS U4620 ( .A(n7698), .B(n4185), .Y(n4223) );
INVX2TS U4621 ( .A(n5010), .Y(n4949) );
XOR2X1TS U4622 ( .A(n4775), .B(n4774), .Y(n4797) );
NOR2X1TS U4623 ( .A(FPMULT_Op_MY[10]), .B(FPMULT_Op_MY[22]), .Y(n3836) );
NAND2BX1TS U4624 ( .AN(n8486), .B(n7454), .Y(n3835) );
OAI21X2TS U4625 ( .A0(n6899), .A1(n7454), .B0(n6900), .Y(n2699) );
INVX2TS U4626 ( .A(n4936), .Y(n5177) );
XOR2X2TS U4627 ( .A(n2285), .B(n5212), .Y(n4941) );
BUFX6TS U4628 ( .A(n3866), .Y(n4933) );
NAND2X4TS U4629 ( .A(n3866), .B(n3865), .Y(n4934) );
NAND2X1TS U4630 ( .A(n3399), .B(n2556), .Y(n2553) );
INVX2TS U4631 ( .A(n3450), .Y(n2885) );
AOI2BB2X1TS U4632 ( .B0(n2882), .B1(n7708), .A0N(DP_OP_497J2_123_1725_n312),
.A1N(n3664), .Y(n3640) );
BUFX4TS U4633 ( .A(n2870), .Y(n2643) );
NAND2X1TS U4634 ( .A(n5276), .B(n5275), .Y(n5296) );
NAND2BX1TS U4635 ( .AN(n4037), .B(n4947), .Y(n5272) );
NAND2X1TS U4636 ( .A(n4018), .B(n4003), .Y(n5273) );
CLKXOR2X2TS U4637 ( .A(n4818), .B(n2805), .Y(n4821) );
CLKXOR2X2TS U4638 ( .A(n4817), .B(n4828), .Y(n4822) );
XOR2X1TS U4639 ( .A(n5087), .B(n5086), .Y(n2333) );
NAND2BX1TS U4640 ( .AN(DP_OP_497J2_123_1725_n324), .B(
DP_OP_496J2_122_3540_n1461), .Y(n3638) );
NOR2X1TS U4641 ( .A(n3342), .B(n3571), .Y(n3343) );
INVX2TS U4642 ( .A(n3627), .Y(n3345) );
INVX2TS U4643 ( .A(n3514), .Y(n2907) );
ADDFHX2TS U4644 ( .A(n3351), .B(n3350), .CI(n3349), .CO(n3367), .S(n3285) );
INVX4TS U4645 ( .A(n3541), .Y(n3581) );
NOR2X4TS U4646 ( .A(n5329), .B(n5328), .Y(n2894) );
INVX2TS U4647 ( .A(n5327), .Y(n2893) );
AOI2BB2XLTS U4648 ( .B0(n7371), .B1(n5941), .A0N(n5940), .A1N(n7611), .Y(
n5943) );
NAND2X1TS U4649 ( .A(n5084), .B(n5083), .Y(n5112) );
NAND2X1TS U4650 ( .A(n5044), .B(n5043), .Y(n5113) );
NAND2X2TS U4651 ( .A(n4875), .B(n4874), .Y(n4876) );
NAND2X1TS U4652 ( .A(n4184), .B(n4233), .Y(n4187) );
INVX2TS U4653 ( .A(n3771), .Y(n4025) );
INVX4TS U4654 ( .A(n3908), .Y(n4024) );
INVX2TS U4655 ( .A(n2835), .Y(n4470) );
OAI21X1TS U4656 ( .A0(n4311), .A1(n4373), .B0(n4372), .Y(n4374) );
NAND2X1TS U4657 ( .A(n4365), .B(n4370), .Y(n4373) );
NOR2X1TS U4658 ( .A(n4364), .B(n4367), .Y(n4370) );
NOR2X1TS U4659 ( .A(n4783), .B(n4786), .Y(n5130) );
OR2X2TS U4660 ( .A(n4799), .B(n4798), .Y(n5056) );
NOR2X1TS U4661 ( .A(n6224), .B(n6238), .Y(n6199) );
NOR2X1TS U4662 ( .A(n5604), .B(n5605), .Y(n5650) );
NOR2X2TS U4663 ( .A(n5360), .B(n5359), .Y(n5376) );
OAI21X2TS U4664 ( .A0(n5289), .A1(n5288), .B0(n5287), .Y(n5378) );
NAND2X1TS U4665 ( .A(n5360), .B(n5359), .Y(n5374) );
NAND2X1TS U4666 ( .A(n5291), .B(n5290), .Y(n5375) );
ADDFHX2TS U4667 ( .A(n5187), .B(n5186), .CI(n5185), .CO(n5634), .S(n5605) );
AO21X1TS U4668 ( .A0(n4934), .A1(n4933), .B0(n2707), .Y(n5187) );
NAND2X1TS U4669 ( .A(n5584), .B(n5583), .Y(n5592) );
XOR3X1TS U4670 ( .A(n5582), .B(n5581), .C(n5580), .Y(n5583) );
NAND2X1TS U4671 ( .A(n5550), .B(n5599), .Y(n5551) );
INVX2TS U4672 ( .A(n3545), .Y(n3707) );
NAND2X4TS U4673 ( .A(n2680), .B(n2679), .Y(n5157) );
NOR2X1TS U4674 ( .A(n3623), .B(n3622), .Y(n3654) );
AOI21X1TS U4675 ( .A0(n3683), .A1(n3684), .B0(n3629), .Y(n3655) );
NAND2X1TS U4676 ( .A(n3623), .B(n3622), .Y(n3653) );
NAND2X4TS U4677 ( .A(n2639), .B(n3660), .Y(n2688) );
NAND2X2TS U4678 ( .A(n3651), .B(n3650), .Y(n3695) );
INVX2TS U4679 ( .A(n3681), .Y(n2638) );
AND2X2TS U4680 ( .A(n3621), .B(n3631), .Y(n2288) );
OR2X6TS U4681 ( .A(n3464), .B(n3463), .Y(n2284) );
NAND2X4TS U4682 ( .A(n3464), .B(n3463), .Y(n3099) );
NAND2X2TS U4683 ( .A(n2775), .B(n2714), .Y(n2598) );
NAND2X2TS U4684 ( .A(n3378), .B(n3377), .Y(n3468) );
OR2X2TS U4685 ( .A(n3285), .B(n3284), .Y(n3376) );
NAND2X2TS U4686 ( .A(n3098), .B(n3581), .Y(n3274) );
INVX2TS U4687 ( .A(n3522), .Y(n3098) );
INVX2TS U4688 ( .A(n5566), .Y(n2987) );
INVX2TS U4689 ( .A(n5238), .Y(n2693) );
INVX2TS U4690 ( .A(n5328), .Y(n5238) );
NAND2X1TS U4691 ( .A(n5280), .B(n5287), .Y(n5281) );
XOR2X1TS U4692 ( .A(n6341), .B(n7676), .Y(n6342) );
NAND2X1TS U4693 ( .A(n6219), .B(n6199), .Y(n6201) );
INVX2TS U4694 ( .A(n4707), .Y(n4703) );
OAI21X2TS U4695 ( .A0(n4712), .A1(n4709), .B0(n4710), .Y(n4193) );
XNOR2X1TS U4696 ( .A(n4198), .B(n4197), .Y(n4705) );
NAND2X2TS U4697 ( .A(n4706), .B(n4705), .Y(n4707) );
NAND2X4TS U4698 ( .A(n3032), .B(n3031), .Y(n4673) );
INVX2TS U4699 ( .A(n4374), .Y(n3031) );
INVX2TS U4700 ( .A(n4375), .Y(n3032) );
NAND2X2TS U4701 ( .A(n4375), .B(n4374), .Y(n4672) );
INVX2TS U4702 ( .A(n4851), .Y(n4322) );
INVX2TS U4703 ( .A(n6381), .Y(n6404) );
NOR2XLTS U4704 ( .A(n6377), .B(n5820), .Y(n5822) );
NAND2X1TS U4705 ( .A(n5605), .B(n5604), .Y(n5653) );
AO21X1TS U4706 ( .A0(n5210), .A1(n5209), .B0(n5212), .Y(n5265) );
NOR2X1TS U4707 ( .A(n2961), .B(n5212), .Y(n5264) );
NAND2X1TS U4708 ( .A(n5634), .B(n5633), .Y(n5652) );
NAND2X1TS U4709 ( .A(n3657), .B(n3656), .Y(n3702) );
NAND2X1TS U4710 ( .A(n3677), .B(n3676), .Y(n3701) );
INVX2TS U4711 ( .A(n3699), .Y(n2872) );
OR2X1TS U4712 ( .A(n3466), .B(n3465), .Y(n3467) );
NAND2X1TS U4713 ( .A(n5089), .B(n5088), .Y(n5090) );
INVX2TS U4714 ( .A(n5309), .Y(n5310) );
INVX2TS U4715 ( .A(n3286), .Y(n3023) );
NAND2X1TS U4716 ( .A(n4743), .B(n4742), .Y(n4745) );
NAND2X1TS U4717 ( .A(n3204), .B(n4727), .Y(n4729) );
NAND2X4TS U4718 ( .A(n2641), .B(n5727), .Y(n2640) );
CLKBUFX2TS U4719 ( .A(n8076), .Y(n5904) );
NOR2X2TS U4720 ( .A(n6450), .B(n6453), .Y(n6491) );
OR2X1TS U4721 ( .A(FPADDSUB_DMP_SFG[12]), .B(FPADDSUB_DmP_mant_SFG_SWR[14]),
.Y(n7107) );
OAI2BB2XLTS U4722 ( .B0(n7656), .B1(n6013), .A0N(n7392), .A1N(n6012), .Y(
n6028) );
NAND3BXLTS U4723 ( .AN(DP_OP_498J2_124_1725_n788), .B(n8417), .C(n8418), .Y(
n7458) );
INVX4TS U4724 ( .A(n2274), .Y(n2275) );
NAND2X2TS U4725 ( .A(n4702), .B(n4701), .Y(n4704) );
XNOR2X2TS U4726 ( .A(n4763), .B(n4762), .Y(n7208) );
NAND2X1TS U4727 ( .A(n4761), .B(n4760), .Y(n4762) );
NAND2X1TS U4728 ( .A(n4754), .B(n4753), .Y(n4755) );
ADDHXLTS U4729 ( .A(FPMULT_Sgf_normalized_result[8]), .B(n6935), .CO(n6933),
.S(n6936) );
ADDHXLTS U4730 ( .A(FPMULT_Sgf_normalized_result[10]), .B(n6931), .CO(n6929),
.S(n6932) );
ADDHXLTS U4731 ( .A(FPMULT_Sgf_normalized_result[12]), .B(n6927), .CO(n6925),
.S(n6928) );
XOR2X1TS U4732 ( .A(n4713), .B(n4712), .Y(n7205) );
XOR2X1TS U4733 ( .A(n4718), .B(n4717), .Y(n7204) );
XOR2X1TS U4734 ( .A(n4740), .B(n4739), .Y(n7202) );
ADDHXLTS U4735 ( .A(FPMULT_Sgf_normalized_result[15]), .B(n6920), .CO(n6918),
.S(n6922) );
INVX2TS U4736 ( .A(n7134), .Y(n7180) );
INVX2TS U4737 ( .A(n5155), .Y(n3712) );
INVX2TS U4738 ( .A(n2318), .Y(n2499) );
XNOR2X1TS U4739 ( .A(n3260), .B(n3236), .Y(n3237) );
NAND2X1TS U4740 ( .A(n3238), .B(n3237), .Y(n3264) );
NAND2X1TS U4741 ( .A(n4721), .B(n4720), .Y(n4723) );
NAND2X2TS U4742 ( .A(n5128), .B(n3105), .Y(n6214) );
NAND2X2TS U4743 ( .A(n6212), .B(n5151), .Y(n5152) );
NAND2X1TS U4744 ( .A(n5736), .B(n5713), .Y(n5716) );
NAND2X6TS U4745 ( .A(n2740), .B(n3691), .Y(n5284) );
INVX2TS U4746 ( .A(n5283), .Y(n5285) );
NAND2X2TS U4747 ( .A(n3716), .B(n3715), .Y(n2754) );
CLKXOR2X2TS U4748 ( .A(n3736), .B(n2732), .Y(n4863) );
NAND2X4TS U4749 ( .A(n2765), .B(n2766), .Y(n3733) );
INVX2TS U4750 ( .A(n3290), .Y(n2765) );
NAND2X2TS U4751 ( .A(n3024), .B(n3021), .Y(n3724) );
OR2X4TS U4752 ( .A(n3024), .B(n3021), .Y(n3725) );
NAND2X4TS U4753 ( .A(n3010), .B(n5690), .Y(n3009) );
OAI21X2TS U4754 ( .A0(n6092), .A1(n6091), .B0(n6090), .Y(n6162) );
OAI21X2TS U4755 ( .A0(n6595), .A1(n6589), .B0(n6590), .Y(n5868) );
INVX2TS U4756 ( .A(n6589), .Y(n6591) );
CLKAND2X2TS U4757 ( .A(n7873), .B(FPADDSUB_DMP_SFG[12]), .Y(n5840) );
INVX2TS U4758 ( .A(n5739), .Y(n5742) );
CLKAND2X2TS U4759 ( .A(n7868), .B(n2473), .Y(n6087) );
AO21XLTS U4760 ( .A0(n6255), .A1(n6290), .B0(n6292), .Y(n6258) );
INVX2TS U4761 ( .A(n8838), .Y(n7642) );
BUFX3TS U4762 ( .A(n7939), .Y(n7663) );
INVX2TS U4763 ( .A(n7088), .Y(n7600) );
NOR2X1TS U4764 ( .A(n4185), .B(DP_OP_498J2_124_1725_n645), .Y(n7210) );
OR2X1TS U4765 ( .A(n4734), .B(n4733), .Y(n4735) );
NAND2X2TS U4766 ( .A(n5541), .B(n5540), .Y(n5751) );
BUFX3TS U4767 ( .A(FPMULT_Op_MY[9]), .Y(n6899) );
NAND4BXLTS U4768 ( .AN(DP_OP_496J2_122_3540_n1498), .B(n8337), .C(n8338),
.D(n8339), .Y(n7462) );
NOR2XLTS U4769 ( .A(FPMULT_Op_MX[18]), .B(n2772), .Y(n7464) );
NAND3XLTS U4770 ( .A(n8343), .B(n8344), .C(n2320), .Y(n2772) );
NAND4BXLTS U4771 ( .AN(n7454), .B(n8463), .C(n8464), .D(n8465), .Y(n7455) );
BUFX3TS U4772 ( .A(n6759), .Y(n6774) );
BUFX3TS U4773 ( .A(n7408), .Y(n6754) );
MX2X1TS U4774 ( .A(Data_1[10]), .B(n2274), .S0(n6901), .Y(n1669) );
MX2X1TS U4775 ( .A(n7207), .B(FPMULT_P_Sgf[7]), .S0(n8524), .Y(n1560) );
MX2X1TS U4776 ( .A(n7208), .B(FPMULT_P_Sgf[8]), .S0(n8525), .Y(n1561) );
MX2X1TS U4777 ( .A(n7206), .B(FPMULT_P_Sgf[6]), .S0(n7253), .Y(n1559) );
MX2X1TS U4778 ( .A(n7209), .B(FPMULT_P_Sgf[9]), .S0(n7216), .Y(n1562) );
NAND4XLTS U4779 ( .A(n7097), .B(n7096), .C(n7095), .D(n7094), .Y(n7101) );
MX2X1TS U4780 ( .A(Data_2[26]), .B(FPMULT_Op_MY[26]), .S0(n6977), .Y(n1653)
);
MX2X1TS U4781 ( .A(Data_2[25]), .B(FPMULT_Op_MY[25]), .S0(n6977), .Y(n1652)
);
MX2X1TS U4782 ( .A(n6938), .B(FPMULT_Add_result[7]), .S0(n6939), .Y(n1617)
);
MX2X1TS U4783 ( .A(n6936), .B(FPMULT_Add_result[8]), .S0(n6921), .Y(n1616)
);
MX2X1TS U4784 ( .A(n6934), .B(FPMULT_Add_result[9]), .S0(n6939), .Y(n1615)
);
MX2X1TS U4785 ( .A(n6932), .B(FPMULT_Add_result[10]), .S0(n6939), .Y(n1614)
);
MX2X1TS U4786 ( .A(n6930), .B(FPMULT_Add_result[11]), .S0(n6921), .Y(n1613)
);
MX2X1TS U4787 ( .A(n6928), .B(FPMULT_Add_result[12]), .S0(n6939), .Y(n1612)
);
MX2X1TS U4788 ( .A(n6926), .B(FPMULT_Add_result[13]), .S0(n6939), .Y(n1611)
);
MX2X1TS U4789 ( .A(n6924), .B(FPMULT_Add_result[14]), .S0(n6921), .Y(n1610)
);
MX2X1TS U4790 ( .A(Data_1[23]), .B(FPMULT_Op_MX[23]), .S0(n6977), .Y(n1682)
);
MX2X1TS U4791 ( .A(Data_1[26]), .B(FPMULT_Op_MX[26]), .S0(n6977), .Y(n1685)
);
OR2X1TS U4792 ( .A(n7281), .B(n6719), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[7]) );
MX2X1TS U4793 ( .A(n7205), .B(FPMULT_P_Sgf[5]), .S0(n6955), .Y(n1558) );
MX2X1TS U4794 ( .A(FPMULT_Adder_M_result_A_adder[4]), .B(
FPMULT_Add_result[4]), .S0(n6939), .Y(n1620) );
MX2X1TS U4795 ( .A(n6940), .B(FPMULT_Add_result[6]), .S0(n6939), .Y(n1618)
);
MX2X1TS U4796 ( .A(Data_2[30]), .B(FPMULT_Op_MY[30]), .S0(n6977), .Y(n1657)
);
MX2X1TS U4797 ( .A(n7203), .B(FPMULT_P_Sgf[3]), .S0(n8524), .Y(n1556) );
CLKAND2X2TS U4798 ( .A(n7215), .B(n7221), .Y(n7217) );
MX2X1TS U4799 ( .A(n7204), .B(FPMULT_P_Sgf[4]), .S0(n7216), .Y(n1557) );
XNOR2X1TS U4800 ( .A(n2670), .B(n7252), .Y(n7254) );
MX2X1TS U4801 ( .A(FPADDSUB_DMP_SFG[11]), .B(FPADDSUB_DMP_SHT2_EWSW[11]),
.S0(n6990), .Y(n1256) );
MX2X1TS U4802 ( .A(Data_2[27]), .B(FPMULT_Op_MY[27]), .S0(n6977), .Y(n1654)
);
MX2X1TS U4803 ( .A(Data_1[25]), .B(FPMULT_Op_MX[25]), .S0(n6977), .Y(n1684)
);
MX2X1TS U4804 ( .A(n7249), .B(FPMULT_P_Sgf[17]), .S0(n8525), .Y(n1570) );
MX2X1TS U4805 ( .A(n7202), .B(FPMULT_P_Sgf[2]), .S0(n7253), .Y(n1555) );
NAND2X1TS U4806 ( .A(n6250), .B(n6249), .Y(n6251) );
MX2X1TS U4807 ( .A(Data_2[24]), .B(FPMULT_Op_MY[24]), .S0(n7452), .Y(n1651)
);
MX2X1TS U4808 ( .A(FPADDSUB_OP_FLAG_SFG), .B(FPADDSUB_OP_FLAG_SHT2), .S0(
n7517), .Y(n1354) );
MX2X1TS U4809 ( .A(n6922), .B(FPMULT_Add_result[15]), .S0(n6939), .Y(n1609)
);
MX2X1TS U4810 ( .A(FPMULT_Adder_M_result_A_adder[5]), .B(
FPMULT_Add_result[5]), .S0(n6943), .Y(n1619) );
MX2X1TS U4811 ( .A(FPMULT_Adder_M_result_A_adder[3]), .B(
FPMULT_Add_result[3]), .S0(n6943), .Y(n1621) );
MX2X1TS U4812 ( .A(n6942), .B(FPMULT_Add_result[2]), .S0(n6943), .Y(n1622)
);
MX2X1TS U4813 ( .A(n6944), .B(FPMULT_Add_result[1]), .S0(n6943), .Y(n1623)
);
XOR2XLTS U4814 ( .A(n7190), .B(n7189), .Y(n7200) );
MX2X1TS U4815 ( .A(Data_1[27]), .B(FPMULT_Op_MX[27]), .S0(n6962), .Y(n1686)
);
OAI21XLTS U4816 ( .A0(n7434), .A1(n2344), .B0(n6832), .Y(n2080) );
MX2X1TS U4817 ( .A(n6987), .B(FPMULT_Exp_module_Overflow_flag_A), .S0(n6955),
.Y(n1540) );
XOR2XLTS U4818 ( .A(n6392), .B(n6391), .Y(n6396) );
XOR2XLTS U4819 ( .A(n7157), .B(n7156), .Y(n7162) );
NAND2X1TS U4820 ( .A(n7242), .B(n7240), .Y(n7238) );
XOR2XLTS U4821 ( .A(n6414), .B(n6413), .Y(n6423) );
OAI31X1TS U4822 ( .A0(n7307), .A1(FPSENCOS_cont_var_out[1]), .A2(n7819),
.B0(n6856), .Y(n2138) );
NAND2X1TS U4823 ( .A(n5724), .B(n5714), .Y(add_x_69_n39) );
NAND2X1TS U4824 ( .A(n5667), .B(n3192), .Y(n5668) );
MX2X1TS U4825 ( .A(Data_2[23]), .B(FPMULT_Op_MY[23]), .S0(n7452), .Y(n1650)
);
MX2X1TS U4826 ( .A(FPADDSUB_DMP_SFG[12]), .B(FPADDSUB_DMP_SHT2_EWSW[12]),
.S0(n7508), .Y(n1268) );
INVX2TS U4827 ( .A(n5699), .Y(n5645) );
NAND2X1TS U4828 ( .A(n5694), .B(n5647), .Y(DP_OP_499J2_125_1651_n4) );
CLKBUFX2TS U4829 ( .A(n5696), .Y(n5697) );
NAND2X1TS U4830 ( .A(n5690), .B(n5689), .Y(DP_OP_499J2_125_1651_n8) );
NAND2X1TS U4831 ( .A(n5700), .B(n5699), .Y(DP_OP_499J2_125_1651_n6) );
INVX2TS U4832 ( .A(n5647), .Y(n5642) );
INVX2TS U4833 ( .A(add_x_69_n188), .Y(add_x_69_n186) );
INVX2TS U4834 ( .A(n3516), .Y(n3094) );
NAND2X1TS U4835 ( .A(n3730), .B(n3729), .Y(n3732) );
NAND2X1TS U4836 ( .A(n5737), .B(n5736), .Y(add_x_69_n57) );
INVX2TS U4837 ( .A(add_x_69_n69), .Y(n5715) );
INVX2TS U4838 ( .A(n5303), .Y(n2794) );
NAND2X1TS U4839 ( .A(n5738), .B(n5720), .Y(add_x_69_n94) );
XOR2X2TS U4840 ( .A(n3081), .B(n3499), .Y(n3080) );
INVX2TS U4841 ( .A(n4863), .Y(FPMULT_Sgf_operation_EVEN1_Q_left[9]) );
NAND2X1TS U4842 ( .A(n3725), .B(n3724), .Y(n3727) );
AO21XLTS U4843 ( .A0(n7304), .A1(n6439), .B0(n6438), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[2]) );
INVX2TS U4844 ( .A(n7284), .Y(n6601) );
MX2X1TS U4845 ( .A(FPMULT_exp_oper_result[8]), .B(n7105), .S0(n6981), .Y(
n1541) );
OAI2BB1X1TS U4846 ( .A0N(n6599), .A1N(n6137), .B0(n6136), .Y(n1321) );
OAI2BB2XLTS U4847 ( .B0(n6855), .B1(n2294), .A0N(
FPADDSUB_Raw_mant_NRM_SWR[24]), .A1N(n6882), .Y(n8750) );
AND3X1TS U4848 ( .A(n6575), .B(n6574), .C(n6573), .Y(n7826) );
NAND2X1TS U4849 ( .A(n5759), .B(n5758), .Y(n5760) );
MX2X1TS U4850 ( .A(Data_1[9]), .B(n6893), .S0(n7452), .Y(n1668) );
MX2X1TS U4851 ( .A(Data_1[21]), .B(DP_OP_496J2_122_3540_n1502), .S0(n2356),
.Y(n1680) );
MX2X1TS U4852 ( .A(Data_2[21]), .B(n7454), .S0(n6901), .Y(n1648) );
MX2X1TS U4853 ( .A(Data_1[30]), .B(FPMULT_Op_MX[30]), .S0(n6962), .Y(n1689)
);
MX2X1TS U4854 ( .A(Data_1[29]), .B(FPMULT_Op_MX[29]), .S0(n6962), .Y(n1688)
);
MX2X1TS U4855 ( .A(Data_1[28]), .B(FPMULT_Op_MX[28]), .S0(n6962), .Y(n1687)
);
OAI21X2TS U4856 ( .A0(n2357), .A1(n2774), .B0(n2773), .Y(n1673) );
INVX2TS U4857 ( .A(Data_1[14]), .Y(n2774) );
NAND2X1TS U4858 ( .A(n2355), .B(DP_OP_497J2_123_1725_n793), .Y(n2773) );
CLKBUFX3TS U4859 ( .A(n7957), .Y(n2469) );
CLKINVX3TS U4860 ( .A(n2346), .Y(n2369) );
MX2X1TS U4861 ( .A(Data_1[3]), .B(n5706), .S0(n2356), .Y(n1662) );
MX2X1TS U4862 ( .A(Data_2[7]), .B(n8518), .S0(n2355), .Y(n1634) );
MX2X1TS U4863 ( .A(Data_2[0]), .B(DP_OP_498J2_124_1725_n788), .S0(n6901),
.Y(n1627) );
OAI2BB1X1TS U4864 ( .A0N(n6599), .A1N(n6118), .B0(n6117), .Y(n1318) );
OAI2BB1X1TS U4865 ( .A0N(n6599), .A1N(n6127), .B0(n6126), .Y(n1319) );
CLKINVX3TS U4866 ( .A(n2386), .Y(n2419) );
MX2X1TS U4867 ( .A(Data_2[15]), .B(DP_OP_497J2_123_1725_n781), .S0(n6962),
.Y(n1642) );
MX2X1TS U4868 ( .A(Data_2[16]), .B(DP_OP_497J2_123_1725_n782), .S0(n6962),
.Y(n1643) );
MX2X1TS U4869 ( .A(Data_2[2]), .B(DP_OP_498J2_124_1725_n790), .S0(n6901),
.Y(n1629) );
MX2X1TS U4870 ( .A(Data_2[29]), .B(FPMULT_Op_MY[29]), .S0(n6977), .Y(n1656)
);
MX2X1TS U4871 ( .A(Data_2[28]), .B(FPMULT_Op_MY[28]), .S0(n6977), .Y(n1655)
);
MX2X1TS U4872 ( .A(Data_1[24]), .B(FPMULT_Op_MX[24]), .S0(n6977), .Y(n1683)
);
MX2X1TS U4873 ( .A(Data_1[0]), .B(DP_OP_496J2_122_3540_n1506), .S0(n2355),
.Y(n1659) );
MX2X1TS U4874 ( .A(Data_1[6]), .B(DP_OP_496J2_122_3540_n1512), .S0(n2356),
.Y(n1665) );
MX2X1TS U4875 ( .A(n2473), .B(FPADDSUB_DMP_SHT2_EWSW[22]), .S0(n7508), .Y(
n1208) );
MX2X1TS U4876 ( .A(n2487), .B(FPADDSUB_DMP_SHT2_EWSW[15]), .S0(n6989), .Y(
n1212) );
MX2X1TS U4877 ( .A(n2479), .B(FPADDSUB_DMP_SHT2_EWSW[18]), .S0(n7508), .Y(
n1216) );
MX2X1TS U4878 ( .A(n2486), .B(FPADDSUB_DMP_SHT2_EWSW[21]), .S0(n7508), .Y(
n1220) );
MX2X1TS U4879 ( .A(n2485), .B(FPADDSUB_DMP_SHT2_EWSW[19]), .S0(n7508), .Y(
n1224) );
MX2X1TS U4880 ( .A(n2477), .B(FPADDSUB_DMP_SHT2_EWSW[20]), .S0(n7508), .Y(
n1228) );
MX2X1TS U4881 ( .A(n2483), .B(FPADDSUB_DMP_SHT2_EWSW[17]), .S0(n6989), .Y(
n1232) );
MX2X1TS U4882 ( .A(FPADDSUB_DMP_SFG[4]), .B(FPADDSUB_DMP_SHT2_EWSW[4]), .S0(
n6990), .Y(n1236) );
MX2X1TS U4883 ( .A(FPADDSUB_DMP_SFG[6]), .B(FPADDSUB_DMP_SHT2_EWSW[6]), .S0(
n6990), .Y(n1240) );
MX2X1TS U4884 ( .A(n2488), .B(FPADDSUB_DMP_SHT2_EWSW[13]), .S0(n7517), .Y(
n1244) );
MX2X1TS U4885 ( .A(n2475), .B(FPADDSUB_DMP_SHT2_EWSW[16]), .S0(n7508), .Y(
n1248) );
MX2X1TS U4886 ( .A(FPADDSUB_DMP_SFG[8]), .B(FPADDSUB_DMP_SHT2_EWSW[8]), .S0(
n6990), .Y(n1252) );
MX2X1TS U4887 ( .A(n2481), .B(FPADDSUB_DMP_SHT2_EWSW[14]), .S0(n6989), .Y(
n1260) );
MX2X1TS U4888 ( .A(FPADDSUB_DMP_SFG[10]), .B(FPADDSUB_DMP_SHT2_EWSW[10]),
.S0(n6990), .Y(n1264) );
MX2X1TS U4889 ( .A(FPADDSUB_DMP_SFG[5]), .B(FPADDSUB_DMP_SHT2_EWSW[5]), .S0(
n6990), .Y(n1274) );
MX2X1TS U4890 ( .A(FPADDSUB_DMP_SFG[9]), .B(FPADDSUB_DMP_SHT2_EWSW[9]), .S0(
n6990), .Y(n1281) );
MX2X1TS U4891 ( .A(FPADDSUB_DMP_SFG[1]), .B(FPADDSUB_DMP_SHT2_EWSW[1]), .S0(
n7517), .Y(n1288) );
MX2X1TS U4892 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DMP_SHT2_EWSW[0]), .S0(
n7517), .Y(n1295) );
MX2X1TS U4893 ( .A(FPADDSUB_DMP_SFG[7]), .B(FPADDSUB_DMP_SHT2_EWSW[7]), .S0(
n6990), .Y(n1302) );
MX2X1TS U4894 ( .A(FPADDSUB_DMP_SFG[2]), .B(FPADDSUB_DMP_SHT2_EWSW[2]), .S0(
n6990), .Y(n1309) );
MX2X1TS U4895 ( .A(FPADDSUB_DMP_SFG[3]), .B(FPADDSUB_DMP_SHT2_EWSW[3]), .S0(
n6990), .Y(n1325) );
XOR2XLTS U4896 ( .A(n7119), .B(n7118), .Y(n7124) );
AO22XLTS U4897 ( .A0(n2359), .A1(FPADDSUB_SIGN_FLAG_NRM), .B0(n6581), .B1(
FPADDSUB_SIGN_FLAG_SHT1SHT2), .Y(n1359) );
MX2X1TS U4898 ( .A(n7092), .B(FPADDSUB_LZD_output_NRM2_EW[1]), .S0(n8526),
.Y(n1411) );
MX2X1TS U4899 ( .A(FPADDSUB_DMP_exp_NRM2_EW[7]), .B(
FPADDSUB_DMP_exp_NRM_EW[7]), .S0(n6988), .Y(n1420) );
MX2X1TS U4900 ( .A(FPADDSUB_DMP_exp_NRM2_EW[6]), .B(
FPADDSUB_DMP_exp_NRM_EW[6]), .S0(n6988), .Y(n1425) );
MX2X1TS U4901 ( .A(FPADDSUB_DMP_exp_NRM2_EW[5]), .B(
FPADDSUB_DMP_exp_NRM_EW[5]), .S0(n6988), .Y(n1430) );
MX2X1TS U4902 ( .A(FPADDSUB_DMP_exp_NRM2_EW[4]), .B(
FPADDSUB_DMP_exp_NRM_EW[4]), .S0(n6988), .Y(n1435) );
AO22XLTS U4903 ( .A0(n7600), .A1(FPADDSUB_DMP_SFG[27]), .B0(n3179), .B1(
FPADDSUB_DMP_exp_NRM_EW[4]), .Y(n1436) );
MX2X1TS U4904 ( .A(FPADDSUB_DMP_exp_NRM2_EW[3]), .B(
FPADDSUB_DMP_exp_NRM_EW[3]), .S0(n6988), .Y(n1440) );
MX2X1TS U4905 ( .A(FPADDSUB_DMP_exp_NRM2_EW[2]), .B(
FPADDSUB_DMP_exp_NRM_EW[2]), .S0(n6988), .Y(n1445) );
MX2X1TS U4906 ( .A(FPADDSUB_DMP_exp_NRM2_EW[1]), .B(
FPADDSUB_DMP_exp_NRM_EW[1]), .S0(n6988), .Y(n1450) );
MX2X1TS U4907 ( .A(FPADDSUB_DMP_exp_NRM2_EW[0]), .B(
FPADDSUB_DMP_exp_NRM_EW[0]), .S0(n6988), .Y(n1455) );
OAI21XLTS U4908 ( .A0(n1419), .A1(n7499), .B0(n7498), .Y(n7500) );
MX2X1TS U4909 ( .A(n7210), .B(FPMULT_P_Sgf[0]), .S0(n6955), .Y(n1553) );
MX2X1TS U4910 ( .A(n7211), .B(FPMULT_P_Sgf[1]), .S0(n7216), .Y(n1554) );
NAND2X1TS U4911 ( .A(n5520), .B(n5519), .Y(n5521) );
NAND2X1TS U4912 ( .A(n5526), .B(n5534), .Y(n5527) );
MX2X1TS U4913 ( .A(Data_2[6]), .B(FPMULT_Op_MY[6]), .S0(n2355), .Y(n1633) );
MX2X1TS U4914 ( .A(Data_2[8]), .B(n6900), .S0(n2357), .Y(n1635) );
MX2X1TS U4915 ( .A(Data_2[9]), .B(n6899), .S0(n2355), .Y(n1636) );
MX2X1TS U4916 ( .A(Data_2[20]), .B(n3860), .S0(n6901), .Y(n1647) );
MX2X1TS U4917 ( .A(Data_2[22]), .B(FPMULT_Op_MY[22]), .S0(n6901), .Y(n1649)
);
MX2X1TS U4918 ( .A(Data_1[4]), .B(n4294), .S0(n7452), .Y(n1663) );
MX2X1TS U4919 ( .A(Data_1[11]), .B(n6898), .S0(n7452), .Y(n1670) );
INVX2TS U4920 ( .A(Data_1[16]), .Y(n2938) );
NAND2X1TS U4921 ( .A(n2356), .B(n2936), .Y(n2937) );
MX2X1TS U4922 ( .A(Data_1[18]), .B(FPMULT_Op_MX[18]), .S0(n2356), .Y(n1677)
);
MX2X1TS U4923 ( .A(Data_1[19]), .B(FPMULT_Op_MX[19]), .S0(n2355), .Y(n1678)
);
MX2X1TS U4924 ( .A(Data_1[22]), .B(FPMULT_Op_MX[22]), .S0(n2356), .Y(n1681)
);
AOI32X1TS U4925 ( .A0(n7303), .A1(n7409), .A2(n7319), .B0(
FPSENCOS_d_ff3_LUT_out[23]), .B1(n7325), .Y(n6637) );
OAI211XLTS U4926 ( .A0(n6559), .A1(n7911), .B0(n7320), .C0(n6656), .Y(n2122)
);
OAI211XLTS U4927 ( .A0(n7364), .A1(n7910), .B0(n7317), .C0(n6640), .Y(n2126)
);
MX2X1TS U4928 ( .A(FPADDSUB_Shift_reg_FLAGS_7[3]), .B(n7089), .S0(n8643),
.Y(n2146) );
AOI2BB2XLTS U4929 ( .B0(n2196), .B1(n7305), .A0N(n7305), .A1N(n2196), .Y(
n2141) );
NOR2X4TS U4930 ( .A(DP_OP_496J2_122_3540_n1462), .B(FPMULT_Op_MY[6]), .Y(
n2730) );
INVX12TS U4931 ( .A(n2549), .Y(n2623) );
XNOR2X4TS U4932 ( .A(n5406), .B(n3186), .Y(n5712) );
NOR2BX4TS U4933 ( .AN(n8462), .B(n8285), .Y(n3537) );
INVX12TS U4934 ( .A(n8462), .Y(n3538) );
NAND2X6TS U4935 ( .A(n2621), .B(n4469), .Y(n4525) );
NAND2X4TS U4936 ( .A(n2321), .B(n2835), .Y(n2621) );
OAI21X4TS U4937 ( .A0(n2521), .A1(DP_OP_496J2_122_3540_n1113), .B0(
DP_OP_496J2_122_3540_n1114), .Y(n2580) );
INVX6TS U4938 ( .A(n2531), .Y(n2532) );
ADDFHX4TS U4939 ( .A(n3483), .B(n3482), .CI(n3481), .CO(n3495), .S(n3477) );
CLKINVX6TS U4940 ( .A(n3656), .Y(n3406) );
CLKINVX6TS U4941 ( .A(n3708), .Y(n3546) );
OAI2BB2X2TS U4942 ( .B0(n3521), .B1(n7708), .A0N(n3520), .A1N(n7708), .Y(
n3570) );
NAND2X4TS U4943 ( .A(n3183), .B(n4376), .Y(n3033) );
ADDHX4TS U4944 ( .A(n4302), .B(n4301), .CO(n4329), .S(n4566) );
XOR2X4TS U4945 ( .A(n2757), .B(n2276), .Y(n3214) );
ADDFHX2TS U4946 ( .A(n4953), .B(n4952), .CI(n4951), .CO(n5019), .S(n4980) );
NOR2X6TS U4947 ( .A(n2433), .B(n2298), .Y(n2780) );
XOR2X4TS U4948 ( .A(n3044), .B(n8286), .Y(n2285) );
NAND2X4TS U4949 ( .A(n4360), .B(n4359), .Y(n4376) );
NOR2X4TS U4950 ( .A(n2675), .B(n2565), .Y(n2674) );
INVX2TS U4951 ( .A(n2565), .Y(n2673) );
ADDFHX4TS U4952 ( .A(n3392), .B(n3391), .CI(n3390), .CO(n3462), .S(n3388) );
NOR2X4TS U4953 ( .A(n4483), .B(n4355), .Y(n4302) );
NOR2X4TS U4954 ( .A(n4451), .B(n4355), .Y(n3034) );
NAND2X4TS U4955 ( .A(n3028), .B(n3027), .Y(n2808) );
ADDFHX4TS U4956 ( .A(n3540), .B(DP_OP_497J2_123_1725_n668), .CI(n3539), .CO(
n3574), .S(n3542) );
NOR2X4TS U4957 ( .A(n2953), .B(n4160), .Y(n4142) );
XNOR2X4TS U4958 ( .A(n4604), .B(n2430), .Y(n4591) );
INVX4TS U4959 ( .A(n2780), .Y(n2779) );
INVX8TS U4960 ( .A(n5325), .Y(n2507) );
ADDFHX2TS U4961 ( .A(n4603), .B(n2440), .CI(n4602), .CO(n4608), .S(n4596) );
ADDFHX4TS U4962 ( .A(n4929), .B(n4928), .CI(n4927), .CO(n5184), .S(n4943) );
ADDFHX4TS U4963 ( .A(n3903), .B(n3902), .CI(n3901), .CO(n4110), .S(n3968) );
OAI22X2TS U4964 ( .A0(n5173), .A1(n2237), .B0(n4923), .B1(n5338), .Y(n5170)
);
ADDFHX4TS U4965 ( .A(n4880), .B(n4879), .CI(n4878), .CO(n4887), .S(n4889) );
OAI21X4TS U4966 ( .A0(n3250), .A1(n3729), .B0(n3249), .Y(n2735) );
INVX4TS U4967 ( .A(n3916), .Y(n3905) );
XOR2X2TS U4968 ( .A(n2789), .B(n3887), .Y(n2516) );
NOR2X6TS U4969 ( .A(n5757), .B(n5751), .Y(n2801) );
NAND3X6TS U4970 ( .A(n2881), .B(n2879), .C(n2878), .Y(n2882) );
NOR2X4TS U4971 ( .A(n3113), .B(n2646), .Y(n3114) );
AOI21X4TS U4972 ( .A0(n5754), .A1(n5753), .B0(n5752), .Y(n5755) );
ADDFHX4TS U4973 ( .A(n4888), .B(n4887), .CI(n4886), .CO(n4678), .S(n4893) );
XOR2X4TS U4974 ( .A(n5252), .B(n5167), .Y(n3982) );
ADDFHX2TS U4975 ( .A(n5579), .B(n5578), .CI(n5577), .CO(n5580), .S(n5568) );
OAI22X2TS U4976 ( .A0(n3960), .A1(n5208), .B0(n3925), .B1(n2303), .Y(n3917)
);
XOR2X4TS U4977 ( .A(n5419), .B(n2278), .Y(n4922) );
NAND2X4TS U4978 ( .A(n3311), .B(n3419), .Y(n3296) );
ADDFHX2TS U4979 ( .A(n5220), .B(n5219), .CI(n5218), .CO(n5241), .S(n5216) );
AND2X4TS U4980 ( .A(n2587), .B(n3589), .Y(n2327) );
NAND2X6TS U4981 ( .A(n3137), .B(n3311), .Y(n3136) );
OAI22X2TS U4982 ( .A0(n3996), .A1(n3797), .B0(n3799), .B1(n4024), .Y(n3979)
);
XOR2X4TS U4983 ( .A(n2901), .B(n2900), .Y(n5340) );
OAI22X4TS U4984 ( .A0(n3996), .A1(n3799), .B0(n3893), .B1(n4024), .Y(n3891)
);
NOR2X2TS U4985 ( .A(n3175), .B(n2226), .Y(n3454) );
OR2X1TS U4986 ( .A(n3419), .B(n3480), .Y(n2878) );
CLKAND2X2TS U4987 ( .A(n3419), .B(n3480), .Y(n2880) );
INVX4TS U4988 ( .A(n3456), .Y(n2551) );
NAND3X4TS U4989 ( .A(n3102), .B(n5282), .C(n3135), .Y(n2743) );
NAND2X4TS U4990 ( .A(n3097), .B(n3091), .Y(n3090) );
INVX6TS U4991 ( .A(n3097), .Y(n3096) );
INVX4TS U4992 ( .A(n3397), .Y(n2974) );
INVX16TS U4993 ( .A(n4099), .Y(n2430) );
OAI22X2TS U4994 ( .A0(n4933), .A1(n3868), .B0(n4934), .B1(n3932), .Y(n3957)
);
NOR2X4TS U4995 ( .A(n3166), .B(n2684), .Y(n3540) );
ADDFX2TS U4996 ( .A(n5569), .B(n5568), .CI(n5567), .CO(n5584), .S(n5427) );
NAND2X6TS U4997 ( .A(n5643), .B(n5644), .Y(n5699) );
XOR2X2TS U4998 ( .A(n2305), .B(n2616), .Y(n2615) );
OAI21X1TS U4999 ( .A0(n2274), .A1(FPMULT_Op_MX[22]), .B0(n2305), .Y(n3807)
);
INVX8TS U5000 ( .A(n2710), .Y(n2438) );
XNOR2X4TS U5001 ( .A(n4616), .B(n4920), .Y(n2279) );
XNOR2X4TS U5002 ( .A(n2889), .B(n2581), .Y(n2280) );
NOR2X4TS U5003 ( .A(n4615), .B(n4616), .Y(n4691) );
NOR2X8TS U5004 ( .A(n2740), .B(n3691), .Y(n5283) );
XNOR2X4TS U5005 ( .A(n4604), .B(n2439), .Y(n3881) );
XOR2X4TS U5006 ( .A(n2620), .B(n2281), .Y(n5447) );
XOR2X4TS U5007 ( .A(n3133), .B(n5721), .Y(n2281) );
NOR2X2TS U5008 ( .A(n3175), .B(n2304), .Y(n3354) );
NOR2X4TS U5009 ( .A(n3175), .B(n3355), .Y(n2556) );
INVX12TS U5010 ( .A(n2511), .Y(n5198) );
NAND2X4TS U5011 ( .A(n7521), .B(n7520), .Y(n7627) );
OR2X8TS U5012 ( .A(n4133), .B(n4134), .Y(n2283) );
XNOR2X4TS U5013 ( .A(n2831), .B(n5465), .Y(n2286) );
OR2X1TS U5014 ( .A(dataB[30]), .B(dataB[24]), .Y(n2297) );
INVX2TS U5015 ( .A(n2346), .Y(n2348) );
CLKINVX3TS U5016 ( .A(n2346), .Y(n2422) );
XNOR2X4TS U5017 ( .A(FPMULT_Op_MX[20]), .B(DP_OP_497J2_123_1725_n793), .Y(
n2298) );
XOR2X1TS U5018 ( .A(n5007), .B(n5006), .Y(n2300) );
CLKXOR2X2TS U5019 ( .A(n5145), .B(n5144), .Y(n2301) );
NAND2X6TS U5020 ( .A(n2595), .B(n5208), .Y(n2303) );
XNOR2X4TS U5021 ( .A(n3071), .B(n3795), .Y(n2305) );
CLKXOR2X2TS U5022 ( .A(n3764), .B(n3765), .Y(n2306) );
AND2X2TS U5023 ( .A(n3493), .B(n3508), .Y(n2309) );
AND2X2TS U5024 ( .A(n3831), .B(n3744), .Y(n2310) );
AND2X2TS U5025 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[7]), .B(n6805), .Y(n2311) );
INVX2TS U5026 ( .A(n5538), .Y(n5485) );
XNOR2X4TS U5027 ( .A(n2497), .B(n3266), .Y(n2313) );
AND2X4TS U5028 ( .A(n3239), .B(n3264), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[6]) );
NAND2X2TS U5029 ( .A(n8519), .B(DP_OP_496J2_122_3540_n1498), .Y(n2315) );
XNOR2X2TS U5030 ( .A(n6900), .B(n3860), .Y(n3855) );
CLKXOR2X2TS U5031 ( .A(DP_OP_496J2_122_3540_n778), .B(n3145), .Y(n2316) );
AND2X2TS U5032 ( .A(n2241), .B(n2313), .Y(n2317) );
CLKXOR2X4TS U5033 ( .A(n3834), .B(n3833), .Y(n3931) );
NAND2X2TS U5034 ( .A(n3965), .B(n3964), .Y(n5572) );
NAND2X4TS U5035 ( .A(n3770), .B(n3774), .Y(n3771) );
CLKINVX6TS U5036 ( .A(n3771), .Y(n2382) );
INVX2TS U5037 ( .A(n2762), .Y(n2759) );
INVX2TS U5038 ( .A(n5395), .Y(n5553) );
NAND2X2TS U5039 ( .A(n2274), .B(n4294), .Y(n4404) );
AND2X4TS U5040 ( .A(n4188), .B(n4175), .Y(n2322) );
OR2X4TS U5041 ( .A(n5152), .B(n6210), .Y(n2323) );
NAND2X4TS U5042 ( .A(n3389), .B(n3388), .Y(n3500) );
INVX4TS U5043 ( .A(n5464), .Y(n5364) );
NAND2X2TS U5044 ( .A(n3175), .B(n3295), .Y(n3311) );
INVX2TS U5045 ( .A(n2818), .Y(n7250) );
AND2X2TS U5046 ( .A(n5285), .B(n5284), .Y(n2324) );
NAND2X1TS U5047 ( .A(n3274), .B(n3472), .Y(n2325) );
INVX2TS U5048 ( .A(n2552), .Y(n3676) );
AND2X2TS U5049 ( .A(n3097), .B(n3094), .Y(n2329) );
INVX2TS U5050 ( .A(n2919), .Y(n3604) );
AOI21X2TS U5051 ( .A0(n2922), .A1(n3496), .B0(n2920), .Y(n2919) );
CLKBUFX2TS U5052 ( .A(n5719), .Y(n5720) );
INVX2TS U5053 ( .A(n4947), .Y(n4014) );
NAND2X2TS U5054 ( .A(n8417), .B(n3172), .Y(n4940) );
INVX2TS U5055 ( .A(n5466), .Y(n5384) );
CLKBUFX2TS U5056 ( .A(FPMULT_Op_MX[11]), .Y(n6898) );
NOR2X4TS U5057 ( .A(n7811), .B(n5769), .Y(n6544) );
INVX2TS U5058 ( .A(n3064), .Y(n5274) );
NAND2X1TS U5059 ( .A(n2372), .B(n7050), .Y(n2336) );
NOR2X1TS U5060 ( .A(n3310), .B(n2304), .Y(n3515) );
INVX2TS U5061 ( .A(n4699), .Y(n4648) );
NAND2X4TS U5062 ( .A(n2403), .B(n7050), .Y(n2339) );
INVX2TS U5063 ( .A(FPADDSUB_shift_value_SHT2_EWR[4]), .Y(n7050) );
OR2X1TS U5064 ( .A(dataB[26]), .B(dataB[29]), .Y(n2342) );
INVX2TS U5065 ( .A(n5733), .Y(n4790) );
CLKBUFX2TS U5066 ( .A(n2420), .Y(n8596) );
CLKBUFX2TS U5067 ( .A(n8596), .Y(n8599) );
INVX2TS U5068 ( .A(n6254), .Y(n8634) );
CLKBUFX3TS U5069 ( .A(n2347), .Y(n8534) );
NOR2X2TS U5070 ( .A(n2439), .B(n3822), .Y(n3812) );
OAI22X2TS U5071 ( .A0(n3521), .A1(n3571), .B0(n3393), .B1(n3606), .Y(n3444)
);
NAND2X6TS U5072 ( .A(n3001), .B(n2282), .Y(n2926) );
OAI22X4TS U5073 ( .A0(n3996), .A1(n3995), .B0(n3797), .B1(n4024), .Y(n4572)
);
AOI21X4TS U5074 ( .A0(n4766), .A1(n4765), .B0(n4580), .Y(n4806) );
OR2X4TS U5075 ( .A(n2860), .B(n3051), .Y(n3049) );
INVX4TS U5076 ( .A(n4449), .Y(n4506) );
NAND2X4TS U5077 ( .A(n2282), .B(n3001), .Y(n2601) );
NAND2X4TS U5078 ( .A(n2282), .B(n3001), .Y(n2641) );
NAND2X4TS U5079 ( .A(n4685), .B(n4684), .Y(n5729) );
INVX6TS U5080 ( .A(n4685), .Y(n2569) );
OAI22X4TS U5081 ( .A0(n2303), .A1(n4005), .B0(n5208), .B1(n4004), .Y(n4052)
);
INVX2TS U5082 ( .A(n3844), .Y(n3112) );
OAI22X2TS U5083 ( .A0(n2433), .A1(n3612), .B0(n3521), .B1(n2299), .Y(n3565)
);
ADDFHX4TS U5084 ( .A(n4089), .B(n4088), .CI(n4087), .CO(n4908), .S(n4130) );
ADDHX4TS U5085 ( .A(n4097), .B(n4096), .CO(n4928), .S(n4114) );
NAND2X6TS U5086 ( .A(n2438), .B(n4024), .Y(n3996) );
NAND2X4TS U5087 ( .A(n3005), .B(n2944), .Y(n2958) );
NAND2X4TS U5088 ( .A(n4220), .B(n7699), .Y(n4212) );
AOI21X2TS U5089 ( .A0(n2233), .A1(n5013), .B0(n4949), .Y(n4995) );
NAND2X4TS U5090 ( .A(n2612), .B(n4523), .Y(n2611) );
OAI22X2TS U5091 ( .A0(n3639), .A1(n3612), .B0(n2434), .B1(n2299), .Y(n3603)
);
NOR2X4TS U5092 ( .A(n5541), .B(n5540), .Y(n5730) );
INVX2TS U5093 ( .A(n2338), .Y(n2345) );
INVX2TS U5094 ( .A(n8634), .Y(n2346) );
INVX2TS U5095 ( .A(n2346), .Y(n2347) );
OAI22X2TS U5096 ( .A0(n2349), .A1(n3519), .B0(n3664), .B1(n3441), .Y(n3525)
);
OAI22X2TS U5097 ( .A0(n2349), .A1(n2299), .B0(n2435), .B1(n3612), .Y(n3642)
);
OAI2BB2X2TS U5098 ( .B0(n3409), .B1(n7708), .A0N(n3408), .A1N(n7708), .Y(
n3431) );
INVX4TS U5099 ( .A(n3445), .Y(n3409) );
OAI22X2TS U5100 ( .A0(n2351), .A1(n3422), .B0(n3446), .B1(n3342), .Y(n3257)
);
INVX2TS U5101 ( .A(n2352), .Y(n2354) );
INVX2TS U5102 ( .A(n2332), .Y(n2360) );
INVX2TS U5103 ( .A(n7303), .Y(n2361) );
INVX2TS U5104 ( .A(n8596), .Y(n2362) );
INVX2TS U5105 ( .A(n2362), .Y(n2363) );
INVX2TS U5106 ( .A(n2362), .Y(n2364) );
CLKBUFX2TS U5107 ( .A(n2493), .Y(n8600) );
CLKBUFX3TS U5108 ( .A(n2493), .Y(n7995) );
INVX2TS U5109 ( .A(n2383), .Y(n2365) );
INVX2TS U5110 ( .A(n2383), .Y(n2366) );
INVX2TS U5111 ( .A(n2362), .Y(n2367) );
INVX2TS U5112 ( .A(n2362), .Y(n2368) );
INVX2TS U5113 ( .A(n2346), .Y(n2370) );
INVX2TS U5114 ( .A(n2295), .Y(n2371) );
INVX2TS U5115 ( .A(n2335), .Y(n2372) );
INVX2TS U5116 ( .A(n2337), .Y(n2375) );
OAI22X1TS U5117 ( .A0(n4954), .A1(n4407), .B0(n2379), .B1(n4448), .Y(n4358)
);
OAI22X2TS U5118 ( .A0(n4549), .A1(n4407), .B0(n2437), .B1(n4448), .Y(n4285)
);
INVX2TS U5119 ( .A(n8599), .Y(n2383) );
INVX2TS U5120 ( .A(n2383), .Y(n2384) );
INVX2TS U5121 ( .A(n2383), .Y(n2385) );
CLKBUFX3TS U5122 ( .A(n2348), .Y(n8537) );
CLKBUFX3TS U5123 ( .A(n2347), .Y(n8535) );
INVX2TS U5124 ( .A(n6354), .Y(n2386) );
INVX2TS U5125 ( .A(n2386), .Y(n2387) );
INVX2TS U5126 ( .A(n2386), .Y(n2388) );
INVX2TS U5127 ( .A(n2386), .Y(n2389) );
INVX2TS U5128 ( .A(n2346), .Y(n2390) );
CLKBUFX3TS U5129 ( .A(n8537), .Y(n8539) );
INVX2TS U5130 ( .A(n2362), .Y(n2391) );
INVX2TS U5131 ( .A(n2383), .Y(n2392) );
INVX2TS U5132 ( .A(n2362), .Y(n2393) );
INVX2TS U5133 ( .A(n2383), .Y(n2394) );
INVX2TS U5134 ( .A(n2336), .Y(n2395) );
INVX2TS U5135 ( .A(n2336), .Y(n2396) );
INVX2TS U5136 ( .A(n6181), .Y(n2397) );
INVX2TS U5137 ( .A(n6181), .Y(n2398) );
INVX2TS U5138 ( .A(n2346), .Y(n2399) );
INVX2TS U5139 ( .A(n2386), .Y(n2400) );
INVX2TS U5140 ( .A(n6254), .Y(n2401) );
INVX2TS U5141 ( .A(FPADDSUB_left_right_SHT2), .Y(n2402) );
INVX2TS U5142 ( .A(n2402), .Y(n2403) );
INVX2TS U5143 ( .A(n2402), .Y(n2404) );
INVX2TS U5144 ( .A(n3147), .Y(n2405) );
INVX2TS U5145 ( .A(n3147), .Y(n2406) );
INVX2TS U5146 ( .A(n6544), .Y(n2409) );
INVX2TS U5147 ( .A(n2409), .Y(n2410) );
INVX2TS U5148 ( .A(n5768), .Y(n2414) );
INVX2TS U5149 ( .A(n2414), .Y(n2415) );
INVX2TS U5150 ( .A(n2414), .Y(n2416) );
NOR4X1TS U5151 ( .A(FPMULT_P_Sgf[6]), .B(FPMULT_P_Sgf[7]), .C(
FPMULT_P_Sgf[8]), .D(FPMULT_P_Sgf[9]), .Y(n5798) );
AOI222X1TS U5152 ( .A0(n6794), .A1(cordic_result[25]), .B0(n6793), .B1(
FPSENCOS_d_ff_Yn[25]), .C0(n6796), .C1(FPSENCOS_d_ff_Xn[25]), .Y(n6789) );
NOR2XLTS U5153 ( .A(n6653), .B(n6652), .Y(n1694) );
INVX2TS U5154 ( .A(n8637), .Y(n2417) );
CLKBUFX2TS U5155 ( .A(n7995), .Y(n8601) );
NOR4X2TS U5156 ( .A(n2350), .B(FPMULT_FS_Module_state_reg[0]), .C(n7817),
.D(n7788), .Y(n7296) );
CLKINVX3TS U5157 ( .A(n6254), .Y(n2418) );
AOI32X1TS U5158 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[2]), .A1(n7434), .A2(
n7301), .B0(FPADDSUB_shift_value_SHT2_EWR[2]), .B1(n8636), .Y(n6672)
);
AOI32X1TS U5159 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[3]), .A1(n7434), .A2(
n8526), .B0(n2491), .B1(n8636), .Y(n6701) );
AOI32X1TS U5160 ( .A0(FPADDSUB_Shift_amount_SHT1_EWR[4]), .A1(n7434), .A2(
n8526), .B0(FPADDSUB_shift_value_SHT2_EWR[4]), .B1(n8636), .Y(n6681)
);
NAND2X4TS U5161 ( .A(n6581), .B(n7658), .Y(n7434) );
CLKMX2X2TS U5162 ( .A(n6218), .B(FPMULT_P_Sgf[19]), .S0(n7216), .Y(n1572) );
NOR3BX2TS U5163 ( .AN(n6059), .B(FPADDSUB_Raw_mant_NRM_SWR[12]), .C(
FPADDSUB_Raw_mant_NRM_SWR[10]), .Y(n6674) );
AOI21X2TS U5164 ( .A0(n2373), .A1(n1813), .B0(n7005), .Y(n7077) );
AOI21X2TS U5165 ( .A0(n1807), .A1(n2373), .B0(n6998), .Y(n7058) );
OAI21X1TS U5166 ( .A0(n7043), .A1(n7012), .B0(n7011), .Y(n6998) );
CLKBUFX3TS U5167 ( .A(n8576), .Y(n8562) );
OAI211X4TS U5168 ( .A0(n8026), .A1(n8058), .B0(n6175), .C0(n6174), .Y(n1793)
);
OAI211X4TS U5169 ( .A0(n8025), .A1(n8058), .B0(n6848), .C0(n6847), .Y(n1795)
);
NAND2X2TS U5170 ( .A(n6618), .B(n7817), .Y(n7477) );
NAND2X4TS U5171 ( .A(n2340), .B(n7084), .Y(n7029) );
CLKBUFX3TS U5172 ( .A(n8593), .Y(n8576) );
AND2X4TS U5173 ( .A(n7052), .B(n2403), .Y(n7082) );
CLKBUFX3TS U5174 ( .A(n8593), .Y(n8578) );
OAI21XLTS U5175 ( .A0(n2359), .A1(n7806), .B0(n6855), .Y(n1352) );
BUFX3TS U5176 ( .A(n8534), .Y(n8547) );
BUFX3TS U5177 ( .A(n8535), .Y(n8548) );
INVX2TS U5178 ( .A(n8637), .Y(n2420) );
CLKBUFX2TS U5179 ( .A(n7993), .Y(n8603) );
INVX2TS U5180 ( .A(n2386), .Y(n2421) );
OAI211XLTS U5181 ( .A0(n8612), .A1(n7850), .B0(n6816), .C0(n6810), .Y(n1470)
);
OAI211XLTS U5182 ( .A0(n8612), .A1(n7851), .B0(n6816), .C0(n6812), .Y(n1471)
);
OAI211XLTS U5183 ( .A0(n8612), .A1(n7852), .B0(n6816), .C0(n6815), .Y(n1472)
);
BUFX3TS U5184 ( .A(n2348), .Y(n6354) );
CLKBUFX3TS U5185 ( .A(n7955), .Y(n7959) );
CLKBUFX3TS U5186 ( .A(n7961), .Y(n7955) );
CLKBUFX3TS U5187 ( .A(n6352), .Y(n7970) );
CLKBUFX3TS U5188 ( .A(n8534), .Y(n6352) );
AOI222X1TS U5189 ( .A0(n6802), .A1(cordic_result[23]), .B0(n6793), .B1(
FPSENCOS_d_ff_Yn[23]), .C0(n6796), .C1(FPSENCOS_d_ff_Xn[23]), .Y(n6781) );
CLKBUFX3TS U5190 ( .A(n7991), .Y(n7776) );
AOI222X1TS U5191 ( .A0(n6794), .A1(cordic_result[30]), .B0(n6793), .B1(
FPSENCOS_d_ff_Yn[30]), .C0(n6728), .C1(FPSENCOS_d_ff_Xn[30]), .Y(n6729) );
AOI222X1TS U5192 ( .A0(n6794), .A1(cordic_result[29]), .B0(n6793), .B1(
FPSENCOS_d_ff_Yn[29]), .C0(n6796), .C1(FPSENCOS_d_ff_Xn[29]), .Y(n6795) );
AOI222X1TS U5193 ( .A0(n6794), .A1(cordic_result[27]), .B0(n6793), .B1(
FPSENCOS_d_ff_Yn[27]), .C0(n6796), .C1(FPSENCOS_d_ff_Xn[27]), .Y(n6792) );
AOI222X1TS U5194 ( .A0(n6794), .A1(cordic_result[26]), .B0(n6793), .B1(
FPSENCOS_d_ff_Yn[26]), .C0(n6796), .C1(FPSENCOS_d_ff_Xn[26]), .Y(n6790) );
NAND2X4TS U5195 ( .A(n7216), .B(n7477), .Y(n6981) );
NOR4X1TS U5196 ( .A(FPMULT_Op_MY[27]), .B(FPMULT_Op_MY[26]), .C(
FPMULT_Op_MY[25]), .D(FPMULT_Op_MY[24]), .Y(n7457) );
NOR2X1TS U5197 ( .A(n7865), .B(n2488), .Y(n5843) );
NOR2X1TS U5198 ( .A(n7864), .B(n2487), .Y(n6073) );
OR2X1TS U5199 ( .A(n7873), .B(FPADDSUB_DMP_SFG[12]), .Y(n5841) );
CLKINVX3TS U5200 ( .A(n2386), .Y(n2423) );
INVX2TS U5201 ( .A(rst), .Y(n2424) );
INVX2TS U5202 ( .A(rst), .Y(n2425) );
INVX2TS U5203 ( .A(rst), .Y(n2426) );
NOR2X2TS U5204 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B(n7795),
.Y(n6587) );
XNOR2X2TS U5205 ( .A(FPMULT_Op_MX[22]), .B(n2274), .Y(n3844) );
NAND2X1TS U5206 ( .A(FPMULT_Op_MX[22]), .B(n2274), .Y(n3847) );
INVX2TS U5207 ( .A(n6985), .Y(n2427) );
BUFX6TS U5208 ( .A(n6945), .Y(n6984) );
OAI22X2TS U5209 ( .A0(n3521), .A1(n2298), .B0(n3318), .B1(n3393), .Y(n2544)
);
INVX2TS U5210 ( .A(n2430), .Y(n4599) );
XNOR2X2TS U5211 ( .A(n3806), .B(n2430), .Y(n3882) );
INVX2TS U5212 ( .A(n2430), .Y(n2616) );
INVX2TS U5213 ( .A(n6204), .Y(n2431) );
INVX2TS U5214 ( .A(n6203), .Y(n2432) );
INVX6TS U5215 ( .A(n3610), .Y(n2434) );
OAI22X1TS U5216 ( .A0(n3639), .A1(n3318), .B0(n2435), .B1(n2298), .Y(n3569)
);
NOR2X1TS U5217 ( .A(n2435), .B(n3446), .Y(n3526) );
NAND2BX1TS U5218 ( .AN(n4108), .B(n4921), .Y(n2997) );
NOR2BX1TS U5219 ( .AN(n4108), .B(n5208), .Y(n4013) );
XNOR2X1TS U5220 ( .A(n4921), .B(n4108), .Y(n4005) );
INVX2TS U5221 ( .A(n4108), .Y(n2523) );
INVX2TS U5222 ( .A(n2710), .Y(n2439) );
INVX2TS U5223 ( .A(n2440), .Y(n4612) );
OAI21X2TS U5224 ( .A0(n3810), .A1(n3823), .B0(n2440), .Y(n3753) );
XNOR2X2TS U5225 ( .A(n2439), .B(n3895), .Y(n3995) );
XNOR2X2TS U5226 ( .A(n3790), .B(n2438), .Y(n3791) );
CLKINVX12TS U5227 ( .A(n4605), .Y(n2441) );
OR2X1TS U5228 ( .A(n2442), .B(n3965), .Y(n3962) );
XNOR2X1TS U5229 ( .A(n2442), .B(n4604), .Y(n4614) );
XNOR2X2TS U5230 ( .A(n2442), .B(n2305), .Y(n4098) );
XNOR2X1TS U5231 ( .A(n2441), .B(n3895), .Y(n3900) );
XNOR2X2TS U5232 ( .A(n2442), .B(n3110), .Y(n4606) );
CLKBUFX2TS U5233 ( .A(n6178), .Y(n2443) );
INVX2TS U5234 ( .A(n6542), .Y(n2444) );
INVX2TS U5235 ( .A(n6542), .Y(n2445) );
INVX2TS U5236 ( .A(n6542), .Y(n2446) );
NOR2XLTS U5237 ( .A(FPMULT_FSM_selector_B[1]), .B(FPMULT_Op_MY[23]), .Y(
n6953) );
NOR2XLTS U5238 ( .A(n7758), .B(n6606), .Y(n6607) );
INVX2TS U5239 ( .A(n2252), .Y(n2447) );
NOR4BX2TS U5240 ( .AN(n6671), .B(n6689), .C(n8645), .D(n6670), .Y(n6684) );
OAI33X4TS U5241 ( .A0(FPSENCOS_d_ff1_operation_out), .A1(
FPSENCOS_d_ff1_shift_region_flag_out[1]), .A2(n7822), .B0(n7789), .B1(
n7802), .B2(FPSENCOS_d_ff1_shift_region_flag_out[0]), .Y(n6724) );
NOR4X1TS U5242 ( .A(Data_2[2]), .B(Data_2[10]), .C(Data_2[12]), .D(
Data_2[14]), .Y(n8067) );
NOR4X1TS U5243 ( .A(Data_2[7]), .B(Data_2[9]), .C(Data_2[11]), .D(Data_2[6]),
.Y(n8066) );
OR2X2TS U5244 ( .A(n4706), .B(n4705), .Y(n4708) );
INVX2TS U5245 ( .A(n2448), .Y(n2449) );
INVX2TS U5246 ( .A(n2450), .Y(n2451) );
INVX2TS U5247 ( .A(n2452), .Y(n2453) );
INVX2TS U5248 ( .A(n2454), .Y(n2455) );
INVX2TS U5249 ( .A(n2456), .Y(n2457) );
INVX2TS U5250 ( .A(n2458), .Y(n2459) );
INVX2TS U5251 ( .A(n2460), .Y(n2461) );
INVX2TS U5252 ( .A(n2462), .Y(n2463) );
NOR4X1TS U5253 ( .A(FPMULT_P_Sgf[13]), .B(FPMULT_P_Sgf[12]), .C(
FPMULT_P_Sgf[11]), .D(FPMULT_P_Sgf[10]), .Y(n5799) );
NOR2X2TS U5254 ( .A(FPSENCOS_d_ff2_Y[29]), .B(n7421), .Y(n7420) );
XNOR2X1TS U5255 ( .A(n2860), .B(n5446), .Y(n3052) );
NOR2X2TS U5256 ( .A(n7323), .B(n7313), .Y(n7321) );
NOR2X2TS U5257 ( .A(FPSENCOS_cont_iter_out[3]), .B(intadd_9_B_1_), .Y(n7323)
);
AOI31XLTS U5258 ( .A0(n7266), .A1(n7265), .A2(n7264), .B0(dataB[27]), .Y(
n7277) );
OAI21X2TS U5259 ( .A0(n8009), .A1(n2221), .B0(n8105), .Y(n7511) );
INVX2TS U5260 ( .A(n6570), .Y(n2464) );
NAND2X2TS U5261 ( .A(FPADDSUB_shift_value_SHT2_EWR[3]), .B(n2464), .Y(n7011)
);
NOR2X2TS U5262 ( .A(n7767), .B(n7756), .Y(n6290) );
NAND2X1TS U5263 ( .A(n6955), .B(FPMULT_P_Sgf[23]), .Y(n5516) );
INVX2TS U5264 ( .A(n5540), .Y(n3233) );
NAND2X1TS U5265 ( .A(n7253), .B(FPMULT_P_Sgf[22]), .Y(n5529) );
AOI21X2TS U5266 ( .A0(n7753), .A1(n7754), .B0(n7755), .Y(n6449) );
AOI211X1TS U5267 ( .A0(n7809), .A1(n2361), .B0(n7325), .C0(n7318), .Y(n6659)
);
OAI21X2TS U5268 ( .A0(n8497), .A1(n8496), .B0(n6042), .Y(n1812) );
NAND2X4TS U5269 ( .A(n2808), .B(n5734), .Y(n5741) );
INVX2TS U5270 ( .A(n5734), .Y(n4777) );
XNOR2X2TS U5271 ( .A(n3951), .B(n4006), .Y(n4008) );
INVX2TS U5272 ( .A(n4006), .Y(n2707) );
OAI32X1TS U5273 ( .A0(n7305), .A1(n7302), .A2(n2361), .B0(n7809), .B1(n7305),
.Y(n2142) );
NOR3X4TS U5274 ( .A(n7302), .B(n7809), .C(n2361), .Y(n7305) );
OAI21X2TS U5275 ( .A0(n6632), .A1(n2361), .B0(n7318), .Y(n7313) );
NAND2X2TS U5276 ( .A(FPSENCOS_cont_iter_out[3]), .B(intadd_9_B_1_), .Y(n7318) );
INVX2TS U5277 ( .A(n2465), .Y(n2466) );
AOI222X4TS U5278 ( .A0(n6802), .A1(cordic_result[15]), .B0(n6801), .B1(
FPSENCOS_d_ff_Yn[15]), .C0(n6800), .C1(FPSENCOS_d_ff_Xn[15]), .Y(n6780) );
AOI222X4TS U5279 ( .A0(n6802), .A1(cordic_result[18]), .B0(n6801), .B1(
FPSENCOS_d_ff_Yn[18]), .C0(n6800), .C1(FPSENCOS_d_ff_Xn[18]), .Y(n6783) );
AOI222X4TS U5280 ( .A0(n6827), .A1(cordic_result[11]), .B0(n6824), .B1(
FPSENCOS_d_ff_Yn[11]), .C0(n6800), .C1(FPSENCOS_d_ff_Xn[11]), .Y(n6777) );
AOI222X4TS U5281 ( .A0(n6802), .A1(cordic_result[19]), .B0(n6801), .B1(
FPSENCOS_d_ff_Yn[19]), .C0(n6800), .C1(FPSENCOS_d_ff_Xn[19]), .Y(n6785) );
AOI222X4TS U5282 ( .A0(n6802), .A1(cordic_result[17]), .B0(n6801), .B1(
FPSENCOS_d_ff_Yn[17]), .C0(n6800), .C1(FPSENCOS_d_ff_Xn[17]), .Y(n6803) );
AOI222X4TS U5283 ( .A0(n6802), .A1(cordic_result[13]), .B0(n6801), .B1(
FPSENCOS_d_ff_Yn[13]), .C0(n6800), .C1(FPSENCOS_d_ff_Xn[13]), .Y(n6791) );
AOI222X4TS U5284 ( .A0(n6802), .A1(cordic_result[16]), .B0(n6801), .B1(
FPSENCOS_d_ff_Yn[16]), .C0(n6800), .C1(FPSENCOS_d_ff_Xn[16]), .Y(n6798) );
AOI222X4TS U5285 ( .A0(n6802), .A1(cordic_result[14]), .B0(n6801), .B1(
FPSENCOS_d_ff_Yn[14]), .C0(n6800), .C1(FPSENCOS_d_ff_Xn[14]), .Y(n6787) );
AOI222X4TS U5286 ( .A0(n6827), .A1(cordic_result[10]), .B0(n6824), .B1(
FPSENCOS_d_ff_Yn[10]), .C0(n6800), .C1(FPSENCOS_d_ff_Xn[10]), .Y(n6788) );
AOI222X4TS U5287 ( .A0(n6827), .A1(cordic_result[12]), .B0(n6801), .B1(
FPSENCOS_d_ff_Yn[12]), .C0(n6800), .C1(FPSENCOS_d_ff_Xn[12]), .Y(n6799) );
AOI21X2TS U5288 ( .A0(n2373), .A1(FPADDSUB_Data_array_SWR_3__25_), .B0(n7005), .Y(n7081) );
NAND2X1TS U5289 ( .A(FPADDSUB_DMP_SFG[11]), .B(FPADDSUB_DmP_mant_SFG_SWR[13]), .Y(n7116) );
AOI222X4TS U5290 ( .A0(n7301), .A1(FPADDSUB_DmP_mant_SHT1_SW[7]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[9]), .B1(n6838), .C0(
FPADDSUB_Raw_mant_NRM_SWR[16]), .C1(n6882), .Y(n8736) );
NOR4X2TS U5291 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[0]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[3]), .Y(n5815) );
INVX4TS U5292 ( .A(n2244), .Y(n6977) );
OAI21XLTS U5293 ( .A0(n7369), .A1(n5932), .B0(n7368), .Y(n5933) );
NAND2BX1TS U5294 ( .AN(n3164), .B(n7253), .Y(n5544) );
OAI211XLTS U5295 ( .A0(n8612), .A1(n7859), .B0(n6816), .C0(n6811), .Y(n1475)
);
OAI211XLTS U5296 ( .A0(n8612), .A1(n7858), .B0(n6816), .C0(n6813), .Y(n1469)
);
NOR3X1TS U5297 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n5813) );
INVX2TS U5298 ( .A(n2467), .Y(n2468) );
OAI21X2TS U5299 ( .A0(n8020), .A1(n8059), .B0(n6169), .Y(n1813) );
NOR3X1TS U5300 ( .A(FPMULT_exp_oper_result[8]), .B(
FPMULT_Exp_module_Overflow_flag_A), .C(n7489), .Y(n7490) );
NOR2X1TS U5301 ( .A(FPADDSUB_Raw_mant_NRM_SWR[3]), .B(
FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n6692) );
INVX2TS U5302 ( .A(rst), .Y(n2470) );
CLKBUFX3TS U5303 ( .A(n8635), .Y(n8592) );
CLKBUFX3TS U5304 ( .A(n8635), .Y(n8595) );
CLKBUFX3TS U5305 ( .A(n8635), .Y(n8594) );
CLKBUFX3TS U5306 ( .A(n8635), .Y(n8591) );
CLKBUFX3TS U5307 ( .A(n8635), .Y(n8593) );
BUFX3TS U5308 ( .A(n8118), .Y(n2471) );
CLKBUFX2TS U5309 ( .A(n8118), .Y(n6851) );
AOI222X4TS U5310 ( .A0(n7301), .A1(FPADDSUB_DmP_mant_SHT1_SW[11]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[13]), .B1(n6838), .C0(
FPADDSUB_Raw_mant_NRM_SWR[12]), .C1(n6641), .Y(n8730) );
INVX2TS U5311 ( .A(n2472), .Y(n2473) );
INVX2TS U5312 ( .A(n2474), .Y(n2475) );
INVX2TS U5313 ( .A(n2476), .Y(n2477) );
INVX2TS U5314 ( .A(n2478), .Y(n2479) );
AOI32X1TS U5315 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[0]), .A1(n2334), .A2(n2294),
.B0(FPADDSUB_Raw_mant_NRM_SWR[2]), .B1(n2334), .Y(n6057) );
INVX2TS U5316 ( .A(n2480), .Y(n2481) );
NAND2X1TS U5317 ( .A(FPADDSUB_DMP_SFG[14]), .B(FPADDSUB_DmP_mant_SFG_SWR[16]), .Y(n5865) );
INVX2TS U5318 ( .A(n2482), .Y(n2483) );
INVX2TS U5319 ( .A(n2484), .Y(n2485) );
CLKBUFX2TS U5320 ( .A(FPADDSUB_DMP_SFG[21]), .Y(n2486) );
INVX2TS U5321 ( .A(n2290), .Y(n2487) );
NAND2X1TS U5322 ( .A(n2487), .B(FPADDSUB_DmP_mant_SFG_SWR[17]), .Y(n6090) );
INVX2TS U5323 ( .A(n2289), .Y(n2488) );
NOR2X1TS U5324 ( .A(n2488), .B(FPADDSUB_DmP_mant_SFG_SWR[15]), .Y(n6589) );
NOR2BX2TS U5325 ( .AN(n6065), .B(FPADDSUB_Raw_mant_NRM_SWR[7]), .Y(n6675) );
AOI222X4TS U5326 ( .A0(n6581), .A1(FPADDSUB_DmP_mant_SHT1_SW[13]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[10]), .B1(n6576), .C0(
FPADDSUB_Raw_mant_NRM_SWR[15]), .C1(n6857), .Y(n8727) );
AOI222X4TS U5327 ( .A0(n7301), .A1(FPADDSUB_DmP_mant_SHT1_SW[9]), .B0(n2489),
.B1(n6857), .C0(FPADDSUB_Raw_mant_NRM_SWR[14]), .C1(n6641), .Y(n8733)
);
INVX2TS U5328 ( .A(n2490), .Y(n2491) );
NAND2BX2TS U5329 ( .AN(FPADDSUB_shift_value_SHT2_EWR[3]), .B(
FPADDSUB_shift_value_SHT2_EWR[2]), .Y(n7012) );
NAND3X1TS U5330 ( .A(n7050), .B(FPADDSUB_shift_value_SHT2_EWR[2]), .C(n2491),
.Y(n7038) );
INVX2TS U5331 ( .A(n8637), .Y(n2492) );
INVX2TS U5332 ( .A(n8637), .Y(n2493) );
INVX2TS U5333 ( .A(n8637), .Y(n2494) );
INVX4TS U5334 ( .A(n3762), .Y(n3745) );
XOR2X4TS U5335 ( .A(n3265), .B(n3267), .Y(n2497) );
XOR2X4TS U5336 ( .A(n2498), .B(n3268), .Y(n3267) );
XOR2X4TS U5337 ( .A(n3269), .B(n2935), .Y(n2498) );
NAND2X8TS U5338 ( .A(n2502), .B(n2501), .Y(n2509) );
NAND2X8TS U5339 ( .A(n2529), .B(n5685), .Y(n2656) );
NAND2X8TS U5340 ( .A(n2507), .B(n2506), .Y(n2529) );
XNOR2X4TS U5341 ( .A(n3000), .B(n5547), .Y(
FPMULT_Sgf_operation_EVEN1_S_B[18]) );
NOR2X8TS U5342 ( .A(n5447), .B(n5448), .Y(n5673) );
XNOR2X4TS U5343 ( .A(n5323), .B(n5322), .Y(n3133) );
NAND2X8TS U5344 ( .A(n2510), .B(n2508), .Y(n2620) );
NAND2X4TS U5345 ( .A(n2509), .B(n2890), .Y(n2508) );
OAI22X4TS U5346 ( .A0(n5338), .A1(n3961), .B0(n2237), .B1(n4107), .Y(n4115)
);
XNOR2X4TS U5347 ( .A(n5205), .B(n5198), .Y(n4107) );
XNOR2X4TS U5348 ( .A(n2515), .B(n2514), .Y(n5205) );
NAND2X4TS U5349 ( .A(n3821), .B(n3820), .Y(n2514) );
NAND2X2TS U5350 ( .A(n2962), .B(n3817), .Y(n2515) );
XOR2X4TS U5351 ( .A(n3888), .B(n3887), .Y(n2511) );
XOR2X4TS U5352 ( .A(n2517), .B(n2306), .Y(n2512) );
XOR2X4TS U5353 ( .A(n3757), .B(n3756), .Y(n2517) );
XNOR2X4TS U5354 ( .A(n3760), .B(n3755), .Y(n2518) );
NOR2X8TS U5355 ( .A(n2520), .B(n2519), .Y(n3760) );
OAI21X4TS U5356 ( .A0(DP_OP_496J2_122_3540_n1107), .A1(
DP_OP_496J2_122_3540_n1114), .B0(DP_OP_496J2_122_3540_n1108), .Y(n2519) );
NAND2X8TS U5357 ( .A(n3144), .B(n4255), .Y(n3762) );
AOI21X4TS U5358 ( .A0(n7686), .A1(n5695), .B0(n2834), .Y(
DP_OP_499J2_125_1651_n39) );
AOI21X4TS U5359 ( .A0(n7686), .A1(n5700), .B0(n5645), .Y(
DP_OP_499J2_125_1651_n44) );
NAND2X8TS U5360 ( .A(n5450), .B(n5451), .Y(n7686) );
AND2X8TS U5361 ( .A(n2522), .B(n2529), .Y(n5698) );
XNOR2X4TS U5362 ( .A(n3907), .B(n4916), .Y(n4002) );
XNOR2X4TS U5363 ( .A(n5179), .B(n3907), .Y(n4009) );
XOR2X4TS U5364 ( .A(n5340), .B(n5167), .Y(n3940) );
XOR2X4TS U5365 ( .A(n5419), .B(n5167), .Y(n3939) );
NAND3X8TS U5366 ( .A(n2728), .B(n2729), .C(n3878), .Y(n2727) );
XNOR2X4TS U5367 ( .A(n2526), .B(n2525), .Y(n3070) );
XOR2X4TS U5368 ( .A(n2527), .B(n5081), .Y(n3062) );
XOR2X4TS U5369 ( .A(n2528), .B(n4510), .Y(n4556) );
INVX12TS U5370 ( .A(DP_OP_498J2_124_1725_n790), .Y(n4160) );
NAND2X1TS U5371 ( .A(n2529), .B(n5686), .Y(n5687) );
NAND2X8TS U5372 ( .A(n3039), .B(n3040), .Y(n2530) );
NAND2X2TS U5373 ( .A(n2530), .B(n5610), .Y(n5560) );
NAND2X1TS U5374 ( .A(n2530), .B(n3188), .Y(n5619) );
XOR2X4TS U5375 ( .A(n2530), .B(n5395), .Y(n5161) );
CLKINVX6TS U5376 ( .A(n2636), .Y(n2531) );
INVX6TS U5377 ( .A(n5156), .Y(n2636) );
NAND3X8TS U5378 ( .A(n2533), .B(n2923), .C(n3589), .Y(n2929) );
NAND3X4TS U5379 ( .A(n2327), .B(n2923), .C(n2533), .Y(n2559) );
NAND3X8TS U5380 ( .A(n2623), .B(n2627), .C(n2284), .Y(n2533) );
XOR2X4TS U5381 ( .A(n2537), .B(n2536), .Y(n3880) );
OAI21X4TS U5382 ( .A0(n3760), .A1(DP_OP_496J2_122_3540_n1102), .B0(
DP_OP_496J2_122_3540_n1103), .Y(n2537) );
XOR2X4TS U5383 ( .A(n2540), .B(n2538), .Y(n3883) );
NAND2X4TS U5384 ( .A(n5330), .B(n2235), .Y(n2692) );
INVX2TS U5385 ( .A(n5182), .Y(n5222) );
XNOR2X4TS U5386 ( .A(n2543), .B(n3423), .Y(n3392) );
XOR2X4TS U5387 ( .A(n3657), .B(n2544), .Y(n2543) );
INVX12TS U5388 ( .A(n3520), .Y(n3393) );
XNOR2X4TS U5389 ( .A(n2545), .B(n3674), .Y(n2740) );
XOR2X4TS U5390 ( .A(n2550), .B(n3397), .Y(n3458) );
XOR2X4TS U5391 ( .A(n2552), .B(n2551), .Y(n2550) );
XNOR2X4TS U5392 ( .A(n2887), .B(n3448), .Y(n2552) );
XOR2X4TS U5393 ( .A(n3398), .B(n2555), .Y(n3395) );
XOR2X4TS U5394 ( .A(n3399), .B(n2556), .Y(n2555) );
INVX12TS U5395 ( .A(DP_OP_497J2_123_1725_n705), .Y(n3355) );
NAND2X8TS U5396 ( .A(n2623), .B(n2560), .Y(n2923) );
OAI21X4TS U5397 ( .A0(n3400), .A1(n3401), .B0(n2563), .Y(n2561) );
XOR2X4TS U5398 ( .A(n2562), .B(n3401), .Y(n3394) );
XOR2X4TS U5399 ( .A(n3400), .B(n2563), .Y(n2562) );
XNOR2X4TS U5400 ( .A(n2850), .B(n2564), .Y(n4158) );
XNOR2X4TS U5401 ( .A(n2565), .B(n2849), .Y(n2564) );
NOR2X8TS U5402 ( .A(DP_OP_498J2_124_1725_n645), .B(n2245), .Y(n2565) );
NOR2X8TS U5403 ( .A(n5673), .B(n5672), .Y(n2566) );
NAND2X8TS U5404 ( .A(n2567), .B(n5725), .Y(n2905) );
NAND2X8TS U5405 ( .A(n2569), .B(n3026), .Y(n2750) );
NAND2X8TS U5406 ( .A(n2750), .B(n5728), .Y(n2909) );
NAND2X8TS U5407 ( .A(n2570), .B(n5539), .Y(n5728) );
NAND2X4TS U5408 ( .A(n2632), .B(n3584), .Y(n2574) );
OAI21X4TS U5409 ( .A0(n2632), .A1(n3584), .B0(n3583), .Y(n2575) );
OAI2BB1X4TS U5410 ( .A0N(FPMULT_Op_MY[10]), .A1N(FPMULT_Op_MY[22]), .B0(
n2577), .Y(n3764) );
XOR2X4TS U5411 ( .A(n2576), .B(n2578), .Y(n3763) );
XNOR2X4TS U5412 ( .A(n2580), .B(n2579), .Y(n3786) );
NAND3X8TS U5413 ( .A(n2584), .B(n4904), .C(n2582), .Y(n2889) );
NAND2X8TS U5414 ( .A(n2589), .B(n4653), .Y(n2695) );
XOR2X4TS U5415 ( .A(n2586), .B(n2585), .Y(n3963) );
XOR2X4TS U5416 ( .A(n3889), .B(n2239), .Y(n2585) );
OR2X8TS U5417 ( .A(n3632), .B(n2587), .Y(n2931) );
NOR2X8TS U5418 ( .A(n3620), .B(n3619), .Y(n3632) );
NAND2X8TS U5419 ( .A(n2931), .B(n3631), .Y(n2639) );
INVX12TS U5420 ( .A(FPMULT_Op_MY[6]), .Y(n4355) );
XNOR2X4TS U5421 ( .A(n3816), .B(n3815), .Y(n2594) );
NAND2X4TS U5422 ( .A(n2613), .B(n4521), .Y(n4522) );
NAND2X8TS U5423 ( .A(n2599), .B(n2614), .Y(n4523) );
INVX2TS U5424 ( .A(n3307), .Y(n2798) );
XNOR2X4TS U5425 ( .A(n2600), .B(n3363), .Y(n3384) );
XNOR2X4TS U5426 ( .A(n3623), .B(n3307), .Y(n2600) );
NAND3X8TS U5427 ( .A(n2602), .B(n5727), .C(n2601), .Y(n3028) );
XOR2X4TS U5428 ( .A(n3787), .B(n3172), .Y(n3765) );
NOR2X4TS U5429 ( .A(n4440), .B(n2603), .Y(n4209) );
OAI22X2TS U5430 ( .A0(n4491), .A1(n2603), .B0(n2378), .B1(n4440), .Y(n4229)
);
XOR2X4TS U5431 ( .A(n4471), .B(n4476), .Y(n2605) );
OAI2BB1X4TS U5432 ( .A0N(n4913), .A1N(n4912), .B0(n2606), .Y(n5193) );
OAI21X2TS U5433 ( .A0(n4912), .A1(n4913), .B0(n2607), .Y(n2606) );
XOR2X4TS U5434 ( .A(n2609), .B(n2607), .Y(n4942) );
XOR2X4TS U5435 ( .A(n2703), .B(n2608), .Y(n2607) );
INVX2TS U5436 ( .A(n4919), .Y(n2608) );
XOR2X4TS U5437 ( .A(n4912), .B(n4913), .Y(n2609) );
NAND3X8TS U5438 ( .A(n2611), .B(n4522), .C(n2610), .Y(n5013) );
XNOR2X4TS U5439 ( .A(n4517), .B(n4516), .Y(n2613) );
OAI22X4TS U5440 ( .A0(n2243), .A1(n3882), .B0(n2615), .B1(n4600), .Y(n3903)
);
OAI22X4TS U5441 ( .A0(n2615), .A1(n2243), .B0(n4600), .B1(n2925), .Y(n3898)
);
NAND2X8TS U5442 ( .A(n5209), .B(n3838), .Y(n5210) );
XOR2X4TS U5443 ( .A(n3837), .B(n2618), .Y(n2617) );
NAND2X6TS U5444 ( .A(n3118), .B(n2619), .Y(n2952) );
NAND2X6TS U5445 ( .A(n3183), .B(n4377), .Y(n2622) );
NAND2X8TS U5446 ( .A(n2626), .B(n2625), .Y(n2775) );
OAI21X4TS U5447 ( .A0(n3247), .A1(n2768), .B0(n3246), .Y(n2629) );
OAI21X4TS U5448 ( .A0(n5312), .A1(n5309), .B0(n5313), .Y(n3101) );
NAND2X4TS U5449 ( .A(n2630), .B(n3690), .Y(n5313) );
XOR2X4TS U5450 ( .A(n2631), .B(n3652), .Y(n2630) );
BUFX6TS U5451 ( .A(n2635), .Y(n2632) );
XOR2X4TS U5452 ( .A(n3581), .B(n2636), .Y(n2633) );
OAI2BB1X4TS U5453 ( .A0N(n2532), .A1N(n3581), .B0(n2634), .Y(n3602) );
OAI21X4TS U5454 ( .A0(n3581), .A1(n2532), .B0(n3580), .Y(n2634) );
NAND2X8TS U5455 ( .A(n2909), .B(n5729), .Y(n3001) );
XOR2X4TS U5456 ( .A(n4900), .B(n2642), .Y(n2814) );
XOR2X4TS U5457 ( .A(n2676), .B(n5013), .Y(n4899) );
AND2X2TS U5458 ( .A(n2781), .B(n2382), .Y(n3901) );
OAI22X1TS U5459 ( .A0(n4633), .A1(n4592), .B0(n4601), .B1(n2644), .Y(n4602)
);
NOR2X8TS U5460 ( .A(n2646), .B(n3923), .Y(n3916) );
OAI21X4TS U5461 ( .A0(n2950), .A1(n2646), .B0(n2986), .Y(n2901) );
OAI22X4TS U5462 ( .A0(n4106), .A1(n2303), .B0(n5208), .B1(n4922), .Y(n4913)
);
XOR2X4TS U5463 ( .A(n2647), .B(n3008), .Y(n5419) );
OAI21X4TS U5464 ( .A0(n3905), .A1(n2950), .B0(n2232), .Y(n2647) );
OAI21X4TS U5465 ( .A0(n5193), .A1(n5192), .B0(n5191), .Y(n2648) );
XNOR2X4TS U5466 ( .A(n2649), .B(n5191), .Y(n5195) );
XNOR2X4TS U5467 ( .A(n5193), .B(n5192), .Y(n2649) );
XNOR2X4TS U5468 ( .A(n2652), .B(n2650), .Y(n5541) );
OAI21X4TS U5469 ( .A0(n2983), .A1(n2651), .B0(n5491), .Y(n2650) );
INVX4TS U5470 ( .A(n2985), .Y(n2651) );
OAI21X4TS U5471 ( .A0(n5518), .A1(n6249), .B0(n5519), .Y(n5538) );
BUFX16TS U5472 ( .A(n3294), .Y(n2653) );
XOR2X4TS U5473 ( .A(n3303), .B(n3304), .Y(n2655) );
NAND2X8TS U5474 ( .A(n2656), .B(n5686), .Y(n5696) );
NOR2X8TS U5475 ( .A(n4514), .B(n4515), .Y(n2658) );
OR2X8TS U5476 ( .A(n4362), .B(n4363), .Y(n2660) );
NOR2X8TS U5477 ( .A(n2661), .B(n4307), .Y(n4362) );
AND2X8TS U5478 ( .A(n4308), .B(n4309), .Y(n2661) );
NAND3X8TS U5479 ( .A(n2663), .B(n4291), .C(n2662), .Y(n4293) );
NAND2X4TS U5480 ( .A(n6893), .B(n2227), .Y(n2662) );
NAND2X4TS U5481 ( .A(n5706), .B(n2227), .Y(n2663) );
NAND2BX4TS U5482 ( .AN(n4402), .B(n4293), .Y(n2666) );
AOI2BB2X4TS U5483 ( .B0(n2824), .B1(n2833), .A0N(n5495), .A1N(n5384), .Y(
n2828) );
NAND2X8TS U5484 ( .A(n2841), .B(n5093), .Y(n2824) );
AND2X8TS U5485 ( .A(n2668), .B(n3163), .Y(n5030) );
NAND2BX4TS U5486 ( .AN(n4406), .B(n3134), .Y(n2668) );
NAND2X8TS U5487 ( .A(n2840), .B(n2839), .Y(n3134) );
OAI22X4TS U5488 ( .A0(n2850), .A1(n2674), .B0(n2849), .B1(n2673), .Y(n4137)
);
OAI2BB1X4TS U5489 ( .A0N(n2684), .A1N(n2683), .B0(n3605), .Y(n2682) );
XNOR2X4TS U5490 ( .A(n3763), .B(n3037), .Y(n2686) );
NAND2X8TS U5491 ( .A(n2924), .B(n4657), .Y(n2731) );
XNOR2X4TS U5492 ( .A(n2691), .B(n2690), .Y(n5372) );
NOR2X8TS U5493 ( .A(n5271), .B(n5270), .Y(n5329) );
NAND3X6TS U5494 ( .A(n2604), .B(n5331), .C(n2235), .Y(n2694) );
XOR2X4TS U5495 ( .A(n2697), .B(n4045), .Y(n4042) );
XNOR2X4TS U5496 ( .A(n3854), .B(n3863), .Y(n4006) );
AOI21X4TS U5497 ( .A0(n2701), .A1(n5409), .B0(n2987), .Y(n5431) );
AOI21X2TS U5498 ( .A0(n2701), .A1(n5591), .B0(n5593), .Y(n5586) );
XNOR2X4TS U5499 ( .A(n2701), .B(n5355), .Y(n5434) );
NAND3X8TS U5500 ( .A(n2896), .B(n2895), .C(n2892), .Y(n2701) );
OAI2BB1X4TS U5501 ( .A0N(n2705), .A1N(n4919), .B0(n2704), .Y(n5172) );
XNOR2X4TS U5502 ( .A(n2706), .B(n3844), .Y(n4938) );
OAI21X4TS U5503 ( .A0(n3843), .A1(n3768), .B0(n3842), .Y(n2706) );
INVX2TS U5504 ( .A(n3840), .Y(n3849) );
OA21X4TS U5505 ( .A0(n3852), .A1(n3851), .B0(n2708), .Y(n3073) );
INVX2TS U5506 ( .A(n3850), .Y(n2709) );
XNOR2X4TS U5507 ( .A(DP_OP_496J2_122_3540_n1063), .B(
DP_OP_496J2_122_3540_n1120), .Y(n2710) );
XOR2X4TS U5508 ( .A(n2711), .B(n2521), .Y(n3790) );
OAI21X4TS U5509 ( .A0(n4670), .A1(n4671), .B0(n4672), .Y(n4644) );
AOI21X4TS U5510 ( .A0(n4853), .A1(n4850), .B0(n4322), .Y(n4670) );
XOR2X4TS U5511 ( .A(n2717), .B(n3417), .Y(n3425) );
XOR2X4TS U5512 ( .A(n3416), .B(n3418), .Y(n2717) );
INVX4TS U5513 ( .A(n3312), .Y(n3407) );
XNOR2X4TS U5514 ( .A(n2718), .B(n4256), .Y(n4268) );
OAI21X4TS U5515 ( .A0(n4311), .A1(n2720), .B0(n2719), .Y(n2718) );
NOR2X8TS U5516 ( .A(n4174), .B(n2322), .Y(n4311) );
XNOR2X4TS U5517 ( .A(n4308), .B(n2721), .Y(n4269) );
NAND2X6TS U5518 ( .A(n2723), .B(n2722), .Y(n4309) );
INVX2TS U5519 ( .A(n4225), .Y(n2722) );
INVX4TS U5520 ( .A(n4226), .Y(n2723) );
NAND2BX4TS U5521 ( .AN(n4238), .B(n2903), .Y(n4308) );
NAND2X8TS U5522 ( .A(n2725), .B(n2724), .Y(n2998) );
NOR2X4TS U5523 ( .A(n3307), .B(n3324), .Y(n4719) );
NOR2X4TS U5524 ( .A(n4211), .B(DP_OP_498J2_124_1725_n635), .Y(n4145) );
NAND2BX2TS U5525 ( .AN(n2761), .B(n2759), .Y(n2758) );
XOR2X4TS U5526 ( .A(n2761), .B(n2759), .Y(n2757) );
XNOR2X4TS U5527 ( .A(n2734), .B(n2733), .Y(n5487) );
AOI21X4TS U5528 ( .A0(n3252), .A1(n3251), .B0(n2735), .Y(n3514) );
NOR2X4TS U5529 ( .A(n2643), .B(n2320), .Y(n3219) );
OAI2BB1X4TS U5530 ( .A0N(n4839), .A1N(n4838), .B0(n2737), .Y(n4865) );
XOR2X4TS U5531 ( .A(n2738), .B(n3542), .Y(n3545) );
XOR2X4TS U5532 ( .A(n3544), .B(n2739), .Y(n2738) );
XNOR2X4TS U5533 ( .A(n2741), .B(n3584), .Y(n3578) );
XNOR2X4TS U5534 ( .A(n2635), .B(n3583), .Y(n2741) );
NAND2X8TS U5535 ( .A(n2746), .B(n2744), .Y(n3135) );
NAND3X8TS U5536 ( .A(n2790), .B(n2234), .C(n3741), .Y(n2746) );
NAND2X4TS U5537 ( .A(n2750), .B(n5729), .Y(n3025) );
NAND2X4TS U5538 ( .A(DP_OP_497J2_123_1725_n781), .B(
DP_OP_497J2_123_1725_n792), .Y(n2762) );
INVX4TS U5539 ( .A(n3043), .Y(n2763) );
XOR2X4TS U5540 ( .A(n2764), .B(n3246), .Y(n3397) );
XOR2X4TS U5541 ( .A(n3247), .B(n2768), .Y(n2764) );
XOR2X4TS U5542 ( .A(n2767), .B(n2325), .Y(n2766) );
XNOR2X4TS U5543 ( .A(n2769), .B(n2915), .Y(n2768) );
NOR2X8TS U5544 ( .A(n2870), .B(n3270), .Y(n2917) );
NAND2X6TS U5545 ( .A(n2779), .B(n2778), .Y(n3456) );
XNOR2X4TS U5546 ( .A(n3137), .B(n3296), .Y(n2777) );
NAND2X4TS U5547 ( .A(n4133), .B(n4134), .Y(n4904) );
NOR2X4TS U5548 ( .A(n2782), .B(n2812), .Y(n2787) );
INVX2TS U5549 ( .A(n2811), .Y(n2782) );
OAI2BB1X4TS U5550 ( .A0N(n2785), .A1N(n4316), .B0(n2783), .Y(n4974) );
XNOR2X4TS U5551 ( .A(n2784), .B(n4316), .Y(n4547) );
XNOR2X4TS U5552 ( .A(n2786), .B(n2785), .Y(n2784) );
OAI22X4TS U5553 ( .A0(n2813), .A1(n2787), .B0(n2811), .B1(n2809), .Y(n2786)
);
NAND3X8TS U5554 ( .A(n2836), .B(n4525), .C(n2788), .Y(n2999) );
XNOR2X4TS U5555 ( .A(n3964), .B(n2441), .Y(n3887) );
NOR2X2TS U5556 ( .A(n4331), .B(n4495), .Y(n4214) );
ADDFX2TS U5557 ( .A(n4482), .B(n4481), .CI(n4480), .CO(n4553), .S(n4490) );
NOR2X4TS U5558 ( .A(n4160), .B(DP_OP_498J2_124_1725_n645), .Y(n4163) );
ADDFHX4TS U5559 ( .A(n4283), .B(n4282), .CI(n4281), .CO(n4347), .S(n4287) );
INVX2TS U5560 ( .A(n4205), .Y(n4216) );
INVX2TS U5561 ( .A(n4224), .Y(n4297) );
INVX4TS U5562 ( .A(n2868), .Y(n3302) );
ADDFHX4TS U5563 ( .A(n3341), .B(n3340), .CI(n3339), .CO(n3348), .S(n3333) );
ADDFHX4TS U5564 ( .A(n3459), .B(n3458), .CI(n3457), .CO(n3529), .S(n3461) );
NOR2X8TS U5565 ( .A(n5732), .B(n5731), .Y(n5757) );
OAI22X2TS U5566 ( .A0(n5031), .A1(n5032), .B0(n5071), .B1(n4955), .Y(n5037)
);
OAI21X4TS U5567 ( .A0(n3731), .A1(n3728), .B0(n3729), .Y(n3229) );
INVX8TS U5568 ( .A(n4525), .Y(n4476) );
INVX4TS U5569 ( .A(n3742), .Y(n2790) );
NAND3X8TS U5570 ( .A(n3718), .B(n2792), .C(n2791), .Y(n3741) );
XNOR2X4TS U5571 ( .A(n5286), .B(n2324), .Y(n2793) );
XOR2X4TS U5572 ( .A(n2796), .B(n2749), .Y(n3518) );
OAI21X4TS U5573 ( .A0(n3363), .A1(n2798), .B0(n3362), .Y(n2797) );
OA21X4TS U5574 ( .A0(n3184), .A1(n5746), .B0(n5747), .Y(n3124) );
NAND2X8TS U5575 ( .A(n2799), .B(n5733), .Y(n5747) );
INVX3TS U5576 ( .A(n2800), .Y(n2799) );
XOR2X4TS U5577 ( .A(n3030), .B(n3001), .Y(n2800) );
NOR2X8TS U5578 ( .A(n3125), .B(n2801), .Y(n3184) );
NAND2X2TS U5579 ( .A(n4819), .B(n4820), .Y(n2802) );
OAI2BB1X4TS U5580 ( .A0N(FPMULT_Sgf_operation_EVEN1_Q_left[6]), .A1N(n2804),
.B0(n4818), .Y(n2803) );
INVX2TS U5581 ( .A(n4820), .Y(n2804) );
OR2X8TS U5582 ( .A(n4950), .B(n2807), .Y(n2854) );
NOR2X8TS U5583 ( .A(n4981), .B(n4982), .Y(n2807) );
AND3X8TS U5584 ( .A(n3028), .B(n3027), .C(n4777), .Y(n5740) );
INVX12TS U5585 ( .A(DP_OP_498J2_124_1725_n803), .Y(n4242) );
XNOR2X4TS U5586 ( .A(n2813), .B(n2810), .Y(n4253) );
NAND2X4TS U5587 ( .A(DP_OP_496J2_122_3540_n1472), .B(
DP_OP_498J2_124_1725_n803), .Y(n2811) );
XNOR2X4TS U5588 ( .A(n4897), .B(n2814), .Y(n2980) );
XOR2X4TS U5589 ( .A(n4902), .B(n4901), .Y(n2815) );
XNOR2X4TS U5590 ( .A(n2816), .B(n5110), .Y(n5123) );
OAI21X4TS U5591 ( .A0(n5106), .A1(n5105), .B0(n5104), .Y(n2816) );
XNOR2X2TS U5592 ( .A(n2430), .B(n3895), .Y(n3801) );
NAND2X4TS U5593 ( .A(n5304), .B(n2819), .Y(n2818) );
INVX2TS U5594 ( .A(n5126), .Y(n2819) );
INVX2TS U5595 ( .A(n5304), .Y(n2820) );
XOR2X4TS U5596 ( .A(n2844), .B(n2842), .Y(n5304) );
XOR2X4TS U5597 ( .A(n2821), .B(n5384), .Y(n5407) );
OAI21X4TS U5598 ( .A0(n2829), .A1(n2822), .B0(n2825), .Y(n2821) );
AOI21X4TS U5599 ( .A0(n5014), .A1(n5013), .B0(n5012), .Y(n2830) );
NAND2X8TS U5600 ( .A(n2854), .B(n5015), .Y(n5103) );
OAI21X4TS U5601 ( .A0(n2832), .A1(n2823), .B0(n2828), .Y(n2831) );
NAND2X4TS U5602 ( .A(n2836), .B(n4526), .Y(n4516) );
OAI21X4TS U5603 ( .A0(n5691), .A1(n5699), .B0(n5692), .Y(n2834) );
NOR2X8TS U5604 ( .A(n4468), .B(n4467), .Y(n4524) );
XOR2X4TS U5605 ( .A(n3134), .B(n2838), .Y(n2851) );
OR2X4TS U5606 ( .A(n3062), .B(n2333), .Y(n5093) );
OAI21X4TS U5607 ( .A0(n2830), .A1(n5092), .B0(n5094), .Y(n2844) );
NOR2X8TS U5608 ( .A(n4992), .B(n4991), .Y(n5011) );
XOR2X4TS U5609 ( .A(n2845), .B(n3159), .Y(n4992) );
XOR2X4TS U5610 ( .A(n2853), .B(n5022), .Y(n5023) );
XOR2X4TS U5611 ( .A(n5020), .B(n5021), .Y(n2853) );
XNOR2X4TS U5612 ( .A(n2857), .B(n2855), .Y(n4221) );
NAND2X6TS U5613 ( .A(n4291), .B(n2858), .Y(n2857) );
NAND2X2TS U5614 ( .A(n2860), .B(n3048), .Y(n7245) );
XNOR2X4TS U5615 ( .A(n2823), .B(n5052), .Y(n2859) );
AOI2BB1X4TS U5616 ( .A0N(n3300), .A1N(n3297), .B0(n2871), .Y(n3138) );
XNOR2X4TS U5617 ( .A(n3661), .B(n2876), .Y(n3650) );
XOR2X4TS U5618 ( .A(n3663), .B(n2877), .Y(n2876) );
OAI2BB1X4TS U5619 ( .A0N(n2886), .A1N(n2885), .B0(n3448), .Y(n2884) );
XOR2X4TS U5620 ( .A(n3450), .B(n3449), .Y(n2887) );
XNOR2X4TS U5621 ( .A(n3805), .B(n2888), .Y(n5179) );
NAND2X4TS U5622 ( .A(n3817), .B(n2242), .Y(n2888) );
NAND3X8TS U5623 ( .A(n3783), .B(n2964), .C(n2963), .Y(n3805) );
XNOR2X4TS U5624 ( .A(n2891), .B(n3555), .Y(n3560) );
OAI21X4TS U5625 ( .A0(n2749), .A1(n3588), .B0(n3099), .Y(n2891) );
NOR2X8TS U5626 ( .A(n2894), .B(n2893), .Y(n2892) );
NOR2X8TS U5627 ( .A(n5319), .B(n5197), .Y(n5331) );
AND2X6TS U5628 ( .A(n2899), .B(n2898), .Y(n3218) );
NOR2X8TS U5629 ( .A(n2902), .B(n3804), .Y(n2950) );
INVX12TS U5630 ( .A(DP_OP_496J2_122_3540_n1461), .Y(n3480) );
XOR2X4TS U5631 ( .A(n2906), .B(n2309), .Y(n3486) );
OAI2BB1X4TS U5632 ( .A0N(n3505), .A1N(n2907), .B0(n3475), .Y(n2906) );
OAI2BB1X4TS U5633 ( .A0N(n3597), .A1N(n3596), .B0(n2911), .Y(n3634) );
OAI21X4TS U5634 ( .A0(n3596), .A1(n3597), .B0(n3595), .Y(n2911) );
OAI21X4TS U5635 ( .A0(n2916), .A1(n2914), .B0(n2912), .Y(n3271) );
OAI21X4TS U5636 ( .A0(n2913), .A1(n2917), .B0(n2915), .Y(n2912) );
INVX12TS U5637 ( .A(DP_OP_497J2_123_1725_n794), .Y(n3270) );
INVX2TS U5638 ( .A(n3632), .Y(n3621) );
XNOR2X4TS U5639 ( .A(n2921), .B(n3496), .Y(n3573) );
OR2X8TS U5640 ( .A(n5673), .B(n5670), .Y(n3002) );
NAND2X6TS U5641 ( .A(n4658), .B(n4659), .Y(n2924) );
OAI21X4TS U5642 ( .A0(n4873), .A1(n4877), .B0(n4875), .Y(n4659) );
OAI22X2TS U5643 ( .A0(n3801), .A1(n4600), .B0(n2243), .B1(n2925), .Y(n3890)
);
XNOR2X2TS U5644 ( .A(n2576), .B(n3800), .Y(n2925) );
AND2X8TS U5645 ( .A(n5442), .B(n5698), .Y(n5449) );
NOR2X6TS U5646 ( .A(n5680), .B(n5679), .Y(n5442) );
NOR2X8TS U5647 ( .A(n5437), .B(n5438), .Y(n5680) );
NAND2BX4TS U5648 ( .AN(n2927), .B(n3006), .Y(n3005) );
INVX4TS U5649 ( .A(n2940), .Y(n3768) );
XOR2X4TS U5650 ( .A(n2940), .B(n3749), .Y(n2928) );
NOR2X8TS U5651 ( .A(n4294), .B(n2936), .Y(n3869) );
XOR2X4TS U5652 ( .A(FPMULT_Op_MX[22]), .B(n2936), .Y(n3316) );
NAND3X8TS U5653 ( .A(n2960), .B(n2959), .C(n2307), .Y(n2940) );
XOR2X4TS U5654 ( .A(n2942), .B(n4064), .Y(n4082) );
OAI22X4TS U5655 ( .A0(n3940), .A1(n4093), .B0(n4094), .B1(n3982), .Y(n2943)
);
AOI21X4TS U5656 ( .A0(n5331), .A1(n2604), .B0(n5330), .Y(n5295) );
NAND2X6TS U5657 ( .A(n2952), .B(n5235), .Y(n2951) );
XOR2X4TS U5658 ( .A(n2966), .B(n2955), .Y(n3806) );
NAND2X8TS U5659 ( .A(n2956), .B(n2992), .Y(n2966) );
OAI21X4TS U5660 ( .A0(n3769), .A1(DP_OP_496J2_122_3540_n1202), .B0(
DP_OP_496J2_122_3540_n1203), .Y(n3779) );
XOR2X4TS U5661 ( .A(n2958), .B(n3004), .Y(n2957) );
NAND2X6TS U5662 ( .A(n3115), .B(n2315), .Y(n3871) );
OAI22X4TS U5663 ( .A0(n3868), .A1(n4934), .B0(n4933), .B1(n4120), .Y(n4117)
);
NAND2X2TS U5664 ( .A(n2242), .B(n3805), .Y(n2962) );
NAND2BX4TS U5665 ( .AN(n2965), .B(n3784), .Y(n2964) );
NAND3X8TS U5666 ( .A(n2971), .B(n2969), .C(n2968), .Y(n4902) );
NAND3X8TS U5667 ( .A(n3090), .B(n2234), .C(n3092), .Y(n2972) );
OAI21X4TS U5668 ( .A0(n2974), .A1(n3456), .B0(n2552), .Y(n2973) );
AND2X4TS U5669 ( .A(n2976), .B(n2975), .Y(n3245) );
XOR2X4TS U5670 ( .A(n2976), .B(n2975), .Y(n3217) );
AOI21X4TS U5671 ( .A0(n2979), .A1(n5743), .B0(n2978), .Y(n2977) );
OAI21X4TS U5672 ( .A0(n5740), .A1(n5747), .B0(n5741), .Y(n2978) );
XOR2X4TS U5673 ( .A(n3503), .B(n3502), .Y(n2981) );
XNOR2X4TS U5674 ( .A(n2991), .B(n3874), .Y(n2990) );
NOR2X4TS U5675 ( .A(n3556), .B(n3305), .Y(n3328) );
XOR2X4TS U5676 ( .A(n3305), .B(n3556), .Y(n3344) );
XOR2X4TS U5677 ( .A(n3052), .B(n5445), .Y(n5448) );
OAI22X2TS U5678 ( .A0(n2303), .A1(n5207), .B0(n2593), .B1(n2997), .Y(n4015)
);
XOR2X4TS U5679 ( .A(n3826), .B(n3809), .Y(n2996) );
INVX2TS U5680 ( .A(n3869), .Y(n3006) );
INVX2TS U5681 ( .A(n4215), .Y(n4519) );
XNOR2X4TS U5682 ( .A(n3035), .B(n3034), .Y(n4215) );
AOI21X4TS U5683 ( .A0(n3011), .A1(n2267), .B0(n3009), .Y(n5684) );
OAI2BB1X4TS U5684 ( .A0N(n4555), .A1N(n3013), .B0(n3012), .Y(n4958) );
OAI21X4TS U5685 ( .A0(n3013), .A1(n4555), .B0(n4554), .Y(n3012) );
XOR2X4TS U5686 ( .A(n4977), .B(n4976), .Y(n3061) );
XNOR2X4TS U5687 ( .A(n3018), .B(n3017), .Y(n5142) );
NOR2BX4TS U5688 ( .AN(n2238), .B(n4250), .Y(n4365) );
AOI21X4TS U5689 ( .A0(n3726), .A1(n3725), .B0(n3020), .Y(n3488) );
XNOR2X4TS U5690 ( .A(n3025), .B(n5728), .Y(n5732) );
XNOR2X4TS U5691 ( .A(n3033), .B(n4377), .Y(n4375) );
AOI21X4TS U5692 ( .A0(n3042), .A1(n3101), .B0(n3041), .Y(n3040) );
NOR2X8TS U5693 ( .A(n5155), .B(n5283), .Y(n3042) );
INVX2TS U5694 ( .A(n4676), .Y(FPMULT_Sgf_operation_EVEN1_Q_left[12]) );
NAND2X6TS U5695 ( .A(n3738), .B(n3739), .Y(n3043) );
OA21X4TS U5696 ( .A0(n3262), .A1(n3263), .B0(n3261), .Y(n3287) );
OAI2BB1X4TS U5697 ( .A0N(n2940), .A1N(n3853), .B0(n3073), .Y(n3044) );
XOR2X4TS U5698 ( .A(n3045), .B(n2308), .Y(n3499) );
XOR2X4TS U5699 ( .A(n3047), .B(n3491), .Y(n3081) );
NOR2X8TS U5700 ( .A(n2230), .B(n3379), .Y(n3491) );
NAND2BX4TS U5701 ( .AN(n3489), .B(n3490), .Y(n3047) );
INVX2TS U5702 ( .A(n2300), .Y(n3048) );
NAND2X8TS U5703 ( .A(n3050), .B(n3049), .Y(n5307) );
INVX2TS U5704 ( .A(n5446), .Y(n3051) );
XOR2X4TS U5705 ( .A(n4300), .B(n3057), .Y(n4281) );
XOR2X4TS U5706 ( .A(n4566), .B(n3058), .Y(n3057) );
AND2X8TS U5707 ( .A(n4177), .B(n7688), .Y(n4180) );
OAI2BB1X4TS U5708 ( .A0N(n4386), .A1N(n4385), .B0(n3059), .Y(n4465) );
OAI21X4TS U5709 ( .A0(n4385), .A1(n4386), .B0(n4384), .Y(n3059) );
XNOR2X4TS U5710 ( .A(n3060), .B(n4385), .Y(n4422) );
XNOR2X4TS U5711 ( .A(n4384), .B(n4386), .Y(n3060) );
XOR2X4TS U5712 ( .A(n3061), .B(n4975), .Y(n4978) );
XOR2X4TS U5713 ( .A(n3856), .B(n3855), .Y(n3074) );
CLKBUFX3TS U5714 ( .A(n5680), .Y(n3069) );
NOR2X8TS U5715 ( .A(n3111), .B(n3803), .Y(n3819) );
XOR2X4TS U5716 ( .A(n2305), .B(n3112), .Y(n3111) );
OAI21X4TS U5717 ( .A0(n3794), .A1(n7733), .B0(DP_OP_496J2_122_3540_n1199),
.Y(n3071) );
AOI21X4TS U5718 ( .A0(n5318), .A1(n2889), .B0(n5317), .Y(n5323) );
OAI22X4TS U5719 ( .A0(n5177), .A1(n3072), .B0(n3935), .B1(n3993), .Y(n3958)
);
XOR2X4TS U5720 ( .A(n3076), .B(n3077), .Y(n3075) );
XNOR2X4TS U5721 ( .A(n5211), .B(n4936), .Y(n3935) );
INVX2TS U5722 ( .A(n3855), .Y(n3077) );
OAI21X4TS U5723 ( .A0(n5763), .A1(n6252), .B0(n5735), .Y(n5543) );
XOR2X4TS U5724 ( .A(n3739), .B(n3080), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[10]) );
INVX2TS U5725 ( .A(n3484), .Y(n3734) );
OR2X4TS U5726 ( .A(n3484), .B(n3485), .Y(n3084) );
INVX12TS U5727 ( .A(n3717), .Y(n3095) );
XNOR2X4TS U5728 ( .A(n3522), .B(n3570), .Y(n3564) );
XNOR2X4TS U5729 ( .A(n3100), .B(n3713), .Y(n3714) );
XOR2X4TS U5730 ( .A(n3103), .B(n2653), .Y(n3520) );
NOR2X8TS U5731 ( .A(n3298), .B(n3104), .Y(n3103) );
INVX6TS U5732 ( .A(n3297), .Y(n3104) );
XNOR2X4TS U5733 ( .A(n5125), .B(n5124), .Y(n5127) );
XOR2X4TS U5734 ( .A(n3107), .B(n4957), .Y(n4960) );
XOR2X4TS U5735 ( .A(n4956), .B(n3108), .Y(n3107) );
OAI2BB1X4TS U5736 ( .A0N(n4976), .A1N(n4977), .B0(n3109), .Y(n5017) );
NAND2X4TS U5737 ( .A(n3803), .B(n3111), .Y(n3820) );
XNOR2X4TS U5738 ( .A(n2950), .B(n3114), .Y(n5252) );
NAND2X4TS U5739 ( .A(n2954), .B(n3870), .Y(n3115) );
INVX4TS U5740 ( .A(n3870), .Y(n3116) );
XOR2X4TS U5741 ( .A(n3119), .B(n2310), .Y(n3867) );
XNOR2X4TS U5742 ( .A(n3123), .B(n3121), .Y(FPMULT_Sgf_operation_Result[27])
);
OAI21X4TS U5743 ( .A0(n3126), .A1(n5742), .B0(n3124), .Y(n3123) );
OAI21X4TS U5744 ( .A0(n3157), .A1(n5754), .B0(n3127), .Y(n3126) );
INVX2TS U5745 ( .A(n4026), .Y(n3128) );
XOR2X4TS U5746 ( .A(n3132), .B(n3171), .Y(n4649) );
XNOR2X4TS U5747 ( .A(n3131), .B(n3741), .Y(n3171) );
XNOR2X4TS U5748 ( .A(n5142), .B(n4648), .Y(n3132) );
NOR2X4TS U5749 ( .A(n3220), .B(n3295), .Y(n3223) );
NAND2X8TS U5750 ( .A(n3139), .B(n3138), .Y(n3137) );
INVX8TS U5751 ( .A(n5714), .Y(n5596) );
NAND2BX1TS U5752 ( .AN(n2382), .B(n2430), .Y(n3796) );
ADDFHX4TS U5753 ( .A(n4466), .B(n4465), .CI(n4464), .CO(n4499), .S(n4429) );
ADDFHX4TS U5754 ( .A(n4229), .B(n4228), .CI(n4227), .CO(n4288), .S(n4237) );
ADDFHX4TS U5755 ( .A(n4052), .B(n4051), .CI(n4050), .CO(n4068), .S(n4059) );
INVX4TS U5756 ( .A(n4847), .Y(n4044) );
NAND2X2TS U5757 ( .A(n3283), .B(n3282), .Y(n4742) );
INVX2TS U5758 ( .A(n4578), .Y(n3920) );
XOR2X4TS U5759 ( .A(n4669), .B(n4668), .Y(n4880) );
NOR2X8TS U5760 ( .A(n4397), .B(DP_OP_498J2_124_1725_n732), .Y(n4473) );
XOR2X4TS U5761 ( .A(n4861), .B(n4860), .Y(n4870) );
ADDFHX2TS U5762 ( .A(n4937), .B(n4936), .CI(n4935), .CO(n5186), .S(n4930) );
OAI22X2TS U5763 ( .A0(n4934), .A1(n4120), .B0(n4933), .B1(n2707), .Y(n4935)
);
NOR2X4TS U5764 ( .A(n4166), .B(DP_OP_498J2_124_1725_n645), .Y(n4733) );
NOR2X6TS U5765 ( .A(n3342), .B(n3612), .Y(n3329) );
ADDFHX4TS U5766 ( .A(n3988), .B(n3987), .CI(n3986), .CO(n4088), .S(n4078) );
ADDFHX2TS U5767 ( .A(n3528), .B(n3527), .CI(n3526), .CO(n3567), .S(n3534) );
ADDHX4TS U5768 ( .A(n4164), .B(n4163), .CO(n4171), .S(n4205) );
ADDFHX4TS U5769 ( .A(n3338), .B(n3337), .CI(n3336), .CO(n3413), .S(n3361) );
NOR2X4TS U5770 ( .A(n4822), .B(n4821), .Y(n5060) );
ADDFHX4TS U5771 ( .A(n3938), .B(n3937), .CI(n3936), .CO(n3942), .S(n4064) );
OAI22X2TS U5772 ( .A0(n4106), .A1(n5208), .B0(n3960), .B1(n2303), .Y(n4126)
);
XNOR2X4TS U5773 ( .A(n4833), .B(n4832), .Y(n4834) );
ADDFHX4TS U5774 ( .A(n4058), .B(n4057), .CI(n4056), .CO(n4065), .S(n4066) );
ADDHX4TS U5775 ( .A(n8518), .B(DP_OP_496J2_122_3540_n778), .CO(n3811), .S(
n3911) );
ADDFHX2TS U5776 ( .A(n4498), .B(n4497), .CI(n4496), .CO(n4538), .S(n4504) );
XNOR2X2TS U5777 ( .A(n5252), .B(n5198), .Y(n4923) );
ADDFHX4TS U5778 ( .A(n4966), .B(n4965), .CI(n4964), .CO(n5021), .S(n4959) );
OAI22X2TS U5779 ( .A0(n5031), .A1(n4407), .B0(n4954), .B1(n4448), .Y(n4384)
);
ADDFHX4TS U5780 ( .A(n2313), .B(n3536), .CI(n3535), .CO(n3584), .S(n3549) );
ADDFHX2TS U5781 ( .A(n5168), .B(n5167), .CI(n5166), .CO(n5226), .S(n5188) );
ADDFHX4TS U5782 ( .A(n3525), .B(n3524), .CI(n3523), .CO(n3586), .S(n3531) );
ADDFHX4TS U5783 ( .A(n4911), .B(n4910), .CI(n4909), .CO(n5196), .S(n4906) );
ADDFHX2TS U5784 ( .A(n4420), .B(n4419), .CI(n4418), .CO(n4431), .S(n4423) );
OAI22X2TS U5785 ( .A0(n2349), .A1(n3571), .B0(n2434), .B1(n3606), .Y(n3568)
);
XNOR2X4TS U5786 ( .A(n5340), .B(n4921), .Y(n4106) );
ADDFHX4TS U5787 ( .A(n5196), .B(n5195), .CI(n5194), .CO(n5234), .S(n4946) );
OAI22X2TS U5788 ( .A0(n3982), .A1(n4093), .B0(n4010), .B1(n4094), .Y(n4047)
);
OAI22X2TS U5789 ( .A0(n4010), .A1(n4093), .B0(n4009), .B1(n4094), .Y(n4050)
);
NOR2X4TS U5790 ( .A(n3295), .B(DP_OP_497J2_123_1725_n638), .Y(n3213) );
ADDFHX4TS U5791 ( .A(n3985), .B(n3984), .CI(n3983), .CO(n3987), .S(n4069) );
ADDFHX4TS U5792 ( .A(n4558), .B(n4557), .CI(n4556), .CO(n4976), .S(n4542) );
ADDFHX4TS U5793 ( .A(n4624), .B(n4623), .CI(n4622), .CO(n5254), .S(n5203) );
ADDFHX2TS U5794 ( .A(n4612), .B(n4611), .CI(n4610), .CO(n4624), .S(n4609) );
ADDFHX4TS U5795 ( .A(n4055), .B(n4054), .CI(n4053), .CO(n5290), .S(n5278) );
ADDFHX2TS U5796 ( .A(n5028), .B(n5027), .CI(n5026), .CO(n5077), .S(n5020) );
ADDFHX2TS U5797 ( .A(n5038), .B(n5037), .CI(n5036), .CO(n5075), .S(n5025) );
ADDFHX4TS U5798 ( .A(n4513), .B(n4512), .CI(n4511), .CO(n4541), .S(n4478) );
NOR2X4TS U5799 ( .A(n4484), .B(DP_OP_498J2_124_1725_n732), .Y(n4274) );
ADDFHX2TS U5800 ( .A(n4410), .B(n4409), .CI(n4408), .CO(n4439), .S(n4419) );
XNOR2X4TS U5801 ( .A(n2940), .B(n3886), .Y(n4001) );
ADDHX4TS U5802 ( .A(n3209), .B(n3208), .CO(n3216), .S(n3305) );
CMPR22X2TS U5803 ( .A(n4535), .B(n4534), .CO(n4963), .S(n4531) );
ADDFHX4TS U5804 ( .A(n3315), .B(n3314), .CI(n3313), .CO(n3656), .S(n3623) );
ADDHX4TS U5805 ( .A(n3309), .B(n3308), .CO(n3315), .S(n3627) );
OAI22X2TS U5806 ( .A0(n3940), .A1(n4094), .B0(n3939), .B1(n4093), .Y(n3941)
);
OAI22X2TS U5807 ( .A0(n3409), .A1(n2298), .B0(n3342), .B1(n3318), .Y(n3347)
);
ADDFHX2TS U5808 ( .A(n3444), .B(n3443), .CI(n3442), .CO(n3523), .S(n3459) );
ADDFHX4TS U5809 ( .A(n4506), .B(n4505), .CI(n2268), .CO(n4558), .S(n4503) );
NAND2X4TS U5810 ( .A(n4577), .B(n4576), .Y(n4772) );
ADDFHX4TS U5811 ( .A(n4423), .B(n4422), .CI(n4421), .CO(n4424), .S(n4360) );
ADDFHX2TS U5812 ( .A(n3609), .B(n3608), .CI(n3607), .CO(n3645), .S(n3601) );
ADDFHX4TS U5813 ( .A(n5202), .B(n5201), .CI(n5200), .CO(n5662), .S(n5633) );
ADDFHX4TS U5814 ( .A(n3245), .B(n3244), .CI(n3243), .CO(n3265), .S(n3246) );
OAI22X2TS U5815 ( .A0(n3393), .A1(n2298), .B0(n2351), .B1(n3318), .Y(n3365)
);
OAI22X2TS U5816 ( .A0(n3393), .A1(n3571), .B0(n2351), .B1(n3606), .Y(n3414)
);
ADDFHX2TS U5817 ( .A(n3569), .B(n3568), .CI(n3567), .CO(n3593), .S(n3585) );
OAI22X2TS U5818 ( .A0(n5031), .A1(n4448), .B0(n5071), .B1(n4407), .Y(n4434)
);
ADDFHX4TS U5819 ( .A(n4380), .B(n4379), .CI(n4378), .CO(n4430), .S(n4359) );
ADDHX4TS U5820 ( .A(n3242), .B(n3241), .CO(n3272), .S(n3244) );
ADDFHX4TS U5821 ( .A(n3455), .B(n3454), .CI(n3453), .CO(n3543), .S(n3450) );
ADDFHX4TS U5822 ( .A(n4553), .B(n4552), .CI(n4551), .CO(n5392), .S(n5365) );
ADDFHX4TS U5823 ( .A(n4509), .B(n4508), .CI(n4507), .CO(n4557), .S(n4511) );
NOR2X8TS U5824 ( .A(DP_OP_497J2_123_1725_n716), .B(n2304), .Y(n3466) );
NOR2X4TS U5825 ( .A(DP_OP_497J2_123_1725_n716), .B(n8285), .Y(n3400) );
ADDFHX4TS U5826 ( .A(n4249), .B(n4248), .CI(n4247), .CO(n4510), .S(n4441) );
ADDFHX4TS U5827 ( .A(n4346), .B(n4345), .CI(n4344), .CO(n4421), .S(n4304) );
ADDHX4TS U5828 ( .A(n4326), .B(n4325), .CO(n4412), .S(n4334) );
NOR2X4TS U5829 ( .A(n4331), .B(n4955), .Y(n4326) );
NAND2X2TS U5830 ( .A(n3863), .B(n3854), .Y(n3837) );
ADDFHX2TS U5831 ( .A(n4546), .B(n4545), .CI(n4544), .CO(n4967), .S(n4552) );
NOR2X4TS U5832 ( .A(n4166), .B(n4165), .Y(n4164) );
OAI22X2TS U5833 ( .A0(n3881), .A1(n3996), .B0(n4612), .B1(n4024), .Y(n4105)
);
ADDFHX4TS U5834 ( .A(n3226), .B(n3225), .CI(n3224), .CO(n3412), .S(n3358) );
ADDFHX4TS U5835 ( .A(n4416), .B(n4415), .CI(n4414), .CO(n5083), .S(n5043) );
ADDFHX4TS U5836 ( .A(n6899), .B(n7454), .CI(n3752), .CO(n3758), .S(n3810) );
ADDFHX4TS U5837 ( .A(n4275), .B(n4274), .CI(n4273), .CO(n4985), .S(n4565) );
OAI22X2TS U5838 ( .A0(n4922), .A1(n2303), .B0(n5165), .B1(n5208), .Y(n5171)
);
ADDFHX4TS U5839 ( .A(n3327), .B(n3326), .CI(n3325), .CO(n3622), .S(n3628) );
ADDFHX4TS U5840 ( .A(n3216), .B(n3215), .CI(n3214), .CO(n3312), .S(n3307) );
ADDHX4TS U5841 ( .A(n3930), .B(n3929), .CO(n3918), .S(n3936) );
OAI22X4TS U5842 ( .A0(n5338), .A1(n3949), .B0(n2237), .B1(n3948), .Y(n3984)
);
OAI22X4TS U5843 ( .A0(n5338), .A1(n2511), .B0(n2237), .B1(n3947), .Y(n3985)
);
CMPR22X2TS U5844 ( .A(n4012), .B(n4011), .CO(n5279), .S(n5276) );
OAI22X4TS U5845 ( .A0(n3994), .A1(n3072), .B0(n4027), .B1(n3993), .Y(n4018)
);
ADDFHX4TS U5846 ( .A(n3928), .B(n3927), .CI(n3926), .CO(n4583), .S(n4582) );
NOR2X8TS U5847 ( .A(n4397), .B(n4391), .Y(n4518) );
ADDHX4TS U5848 ( .A(n4162), .B(n4161), .CO(n4170), .S(n4219) );
ADDFHX4TS U5849 ( .A(n4254), .B(n4253), .CI(n4252), .CO(n4548), .S(n4251) );
ADDFHX4TS U5850 ( .A(n3970), .B(n3969), .CI(n3968), .CO(n4585), .S(n4584) );
CMPR22X2TS U5851 ( .A(n3898), .B(n3897), .CO(n3970), .S(n3927) );
ADDFHX4TS U5852 ( .A(n4159), .B(n4158), .CI(n4157), .CO(n4417), .S(n4350) );
ADDFHX4TS U5853 ( .A(n3426), .B(n3425), .CI(n3424), .CO(n3427), .S(n3389) );
NAND2X4TS U5854 ( .A(n5732), .B(n5731), .Y(n5759) );
ADDFHX2TS U5855 ( .A(n5077), .B(n5076), .CI(n5075), .CO(n5107), .S(n5067) );
ADDFHX4TS U5856 ( .A(n3579), .B(n3578), .CI(n3577), .CO(n3617), .S(n3561) );
ADDFHX4TS U5857 ( .A(n3396), .B(n3395), .CI(n3394), .CO(n3677), .S(n3657) );
ADDFHX2TS U5858 ( .A(n3354), .B(n3353), .CI(n3352), .CO(n3396), .S(n3313) );
NOR2X8TS U5859 ( .A(n5123), .B(n5122), .Y(n5464) );
ADDFHX4TS U5860 ( .A(n4017), .B(n4016), .CI(n4015), .CO(n4048), .S(n4045) );
ADDFHX4TS U5861 ( .A(n3212), .B(n3211), .CI(n3210), .CO(n3324), .S(n3321) );
OAI22X2TS U5862 ( .A0(n4536), .A1(n4955), .B0(n2837), .B1(n5032), .Y(n4962)
);
BUFX20TS U5863 ( .A(n4536), .Y(n5031) );
ADDFHX4TS U5864 ( .A(n3976), .B(n3975), .CI(n3974), .CO(n5359), .S(n5291) );
OAI22X2TS U5865 ( .A0(n2837), .A1(n4495), .B0(n2379), .B1(n4550), .Y(n4463)
);
OAI22X2TS U5866 ( .A0(n2837), .A1(n5029), .B0(n4549), .B1(n5070), .Y(n4966)
);
OAI22X2TS U5867 ( .A0(n4549), .A1(n4440), .B0(n2437), .B1(n4491), .Y(n4349)
);
OAI22X2TS U5868 ( .A0(n4549), .A1(n4955), .B0(n2437), .B1(n5032), .Y(n4497)
);
OAI22X2TS U5869 ( .A0(n4549), .A1(n4537), .B0(n2437), .B1(n4970), .Y(n4447)
);
ADDFHX4TS U5870 ( .A(n4329), .B(n4328), .CI(n4327), .CO(n5044), .S(n4984) );
ADDFHX4TS U5871 ( .A(n3921), .B(n3922), .CI(n3920), .CO(n3929), .S(n4057) );
INVX4TS U5872 ( .A(n4873), .Y(n4874) );
XNOR2X4TS U5873 ( .A(n5419), .B(n5198), .Y(n5199) );
ADDFHX2TS U5874 ( .A(n4118), .B(n4936), .CI(n4117), .CO(n4931), .S(n4121) );
XNOR2X4TS U5875 ( .A(n5205), .B(n4921), .Y(n3925) );
ADDFHX4TS U5876 ( .A(n4460), .B(n4459), .CI(n4458), .CO(n5119), .S(n5084) );
ADDFHX4TS U5877 ( .A(n4170), .B(n4169), .CI(n4168), .CO(n4323), .S(n4295) );
ADDFHX4TS U5878 ( .A(n4173), .B(n4172), .CI(n4171), .CO(n4276), .S(n4224) );
ADDFHX4TS U5879 ( .A(n4152), .B(n4151), .CI(n4150), .CO(n4449), .S(n4390) );
ADDFHX2TS U5880 ( .A(n4145), .B(n4144), .CI(n4143), .CO(n4244), .S(n4151) );
NAND2X1TS U5881 ( .A(n1667), .B(n1661), .Y(n3140) );
OR2X2TS U5882 ( .A(n5254), .B(n5262), .Y(n3142) );
OA21X4TS U5883 ( .A0(n4829), .A1(n4826), .B0(n4830), .Y(n3143) );
INVX2TS U5884 ( .A(n4572), .Y(n4573) );
OA21XLTS U5885 ( .A0(n5510), .A1(n5509), .B0(n5508), .Y(n3151) );
CLKXOR2X2TS U5886 ( .A(n5479), .B(n5478), .Y(n3152) );
OR2X2TS U5887 ( .A(FPMULT_FSM_selector_B[1]), .B(n7808), .Y(n3154) );
INVX2TS U5888 ( .A(n5723), .Y(n5738) );
NAND2X1TS U5889 ( .A(add_x_69_n113), .B(n5718), .Y(n5723) );
AND2X4TS U5890 ( .A(add_x_69_n272), .B(n5750), .Y(n3157) );
NAND2X1TS U5891 ( .A(n7701), .B(n7706), .Y(n3160) );
XNOR2X4TS U5892 ( .A(n3806), .B(n6898), .Y(n3161) );
OR2X1TS U5893 ( .A(n4195), .B(n4194), .Y(n3162) );
AO22XLTS U5894 ( .A0(n5896), .A1(n7570), .B0(n8784), .B1(n7569), .Y(n3169)
);
AO22XLTS U5895 ( .A0(n8786), .A1(n7575), .B0(n7574), .B1(gt_x_74_B_23_), .Y(
n3170) );
NOR2BX2TS U5896 ( .AN(n6614), .B(FPMULT_FS_Module_state_reg[1]), .Y(n6945)
);
CLKBUFX2TS U5897 ( .A(DP_OP_496J2_122_3540_n1493), .Y(n7468) );
OR2X4TS U5898 ( .A(n4224), .B(n4219), .Y(n3181) );
OR2X2TS U5899 ( .A(n4565), .B(n4566), .Y(n3182) );
CLKXOR2X2TS U5900 ( .A(n5405), .B(n5404), .Y(n3186) );
OA21XLTS U5901 ( .A0(n5618), .A1(n5617), .B0(n5616), .Y(n3187) );
AND2X2TS U5902 ( .A(n5610), .B(n5609), .Y(n3188) );
OR2X8TS U5903 ( .A(n4885), .B(n4884), .Y(n3190) );
XOR2X1TS U5904 ( .A(n5666), .B(n5665), .Y(n3192) );
OR2X1TS U5905 ( .A(FPADDSUB_ADD_OVRFLW_NRM2), .B(
FPADDSUB_LZD_output_NRM2_EW[0]), .Y(n3193) );
OR2X1TS U5906 ( .A(n7941), .B(FPADDSUB_DMP_SFG[9]), .Y(n3194) );
AO22XLTS U5907 ( .A0(n8783), .A1(n7568), .B0(n8782), .B1(n7567), .Y(n3195)
);
AO22XLTS U5908 ( .A0(n5914), .A1(n7566), .B0(n8805), .B1(n7625), .Y(n3196)
);
AO22XLTS U5909 ( .A0(n8810), .A1(n7638), .B0(n8815), .B1(n7565), .Y(n3197)
);
AO22XLTS U5910 ( .A0(n8813), .A1(n7564), .B0(n8820), .B1(n7563), .Y(n3198)
);
AO22XLTS U5911 ( .A0(n8832), .A1(n7560), .B0(n8824), .B1(n7652), .Y(n3199)
);
AO22XLTS U5912 ( .A0(n6009), .A1(n7562), .B0(n8834), .B1(n7561), .Y(n3200)
);
AO22XLTS U5913 ( .A0(n8837), .A1(n7577), .B0(n8830), .B1(n7576), .Y(n3201)
);
INVX2TS U5914 ( .A(n5392), .Y(n4964) );
NAND2X2TS U5915 ( .A(n4401), .B(n4403), .Y(n4342) );
OAI21X2TS U5916 ( .A0(n5100), .A1(n5099), .B0(n5098), .Y(n5101) );
NOR2X1TS U5917 ( .A(n3664), .B(n3519), .Y(n3566) );
ADDFHX2TS U5918 ( .A(FPMULT_Op_MX[20]), .B(n3860), .CI(n3537), .CO(n3576),
.S(n3539) );
NAND2X2TS U5919 ( .A(n4993), .B(n5009), .Y(n4994) );
NOR2X1TS U5920 ( .A(n5968), .B(n7380), .Y(n5966) );
OR2X1TS U5921 ( .A(n5662), .B(n5661), .Y(n5664) );
NAND2X1TS U5922 ( .A(n5382), .B(n5600), .Y(n5383) );
NAND2X1TS U5923 ( .A(n2491), .B(n7814), .Y(n6991) );
NAND2X1TS U5924 ( .A(n5554), .B(n5614), .Y(n5617) );
NAND2X1TS U5925 ( .A(n2488), .B(FPADDSUB_DmP_mant_SFG_SWR[15]), .Y(n6590) );
OR2X1TS U5926 ( .A(n6306), .B(n6230), .Y(n6223) );
INVX2TS U5927 ( .A(n7173), .Y(n7175) );
OR2X1TS U5928 ( .A(n7870), .B(n2479), .Y(n6080) );
OAI21X2TS U5929 ( .A0(n7218), .A1(n7221), .B0(n7219), .Y(n7224) );
NAND2X1TS U5930 ( .A(n6069), .B(n7807), .Y(n6668) );
OAI21X2TS U5931 ( .A0(n6113), .A1(n6086), .B0(n6085), .Y(n6103) );
OAI21X1TS U5932 ( .A0(n6692), .A1(n6695), .B0(n6066), .Y(n6678) );
INVX2TS U5933 ( .A(n5717), .Y(n5737) );
INVX2TS U5934 ( .A(FPMULT_zero_flag), .Y(n7478) );
OR2X1TS U5935 ( .A(FPSENCOS_d_ff2_X[23]), .B(n2360), .Y(intadd_10_CI) );
INVX2TS U5936 ( .A(result_add_subt[22]), .Y(n7523) );
INVX2TS U5937 ( .A(n6718), .Y(n7300) );
OAI2BB1X1TS U5938 ( .A0N(n6599), .A1N(n6146), .B0(n6145), .Y(n1322) );
INVX2TS U5939 ( .A(n1646), .Y(n7701) );
INVX4TS U5940 ( .A(n2244), .Y(n6962) );
INVX2TS U5941 ( .A(DP_OP_497J2_123_1725_n779), .Y(n7706) );
CLKMX2X2TS U5942 ( .A(Data_2[12]), .B(n8520), .S0(n6962), .Y(n1639) );
INVX2TS U5943 ( .A(n1639), .Y(n3202) );
NOR2BX1TS U5944 ( .AN(n3202), .B(n1627), .Y(n3203) );
INVX2TS U5945 ( .A(n3203), .Y(n7668) );
CLKMX2X2TS U5946 ( .A(Data_1[2]), .B(n8341), .S0(n2357), .Y(n1661) );
CLKMX2X2TS U5947 ( .A(Data_2[4]), .B(FPMULT_Op_MY[4]), .S0(n6901), .Y(n1631)
);
NOR2X2TS U5952 ( .A(n3240), .B(n3220), .Y(n3211) );
NOR2X2TS U5953 ( .A(n3283), .B(n3282), .Y(n4741) );
NOR2X2TS U5954 ( .A(n3232), .B(n3220), .Y(n4731) );
NAND2X2TS U5955 ( .A(n4731), .B(n4730), .Y(n4744) );
OAI21X2TS U5956 ( .A0(n4741), .A1(n4744), .B0(n4742), .Y(n4728) );
INVX2TS U5957 ( .A(n4727), .Y(n3207) );
AOI21X4TS U5958 ( .A0(n3204), .A1(n4728), .B0(n3207), .Y(n4722) );
NAND2X2TS U5959 ( .A(n3307), .B(n3324), .Y(n4720) );
OAI21X4TS U5960 ( .A0(n4722), .A1(n4719), .B0(n4720), .Y(n3251) );
INVX4TS U5961 ( .A(n3251), .Y(n3731) );
NOR2X4TS U5962 ( .A(n3240), .B(n8344), .Y(n3222) );
NAND2X2TS U5963 ( .A(n3312), .B(n3358), .Y(n3729) );
ADDFHX4TS U5964 ( .A(n3219), .B(n3218), .CI(n3217), .CO(n3247), .S(n3224) );
NOR2X4TS U5965 ( .A(n3480), .B(n3220), .Y(n3242) );
ADDFHX4TS U5966 ( .A(n3223), .B(n3222), .CI(n3221), .CO(n3243), .S(n3225) );
INVX2TS U5967 ( .A(n3250), .Y(n3227) );
XNOR2X4TS U5968 ( .A(n3229), .B(n3228), .Y(n3238) );
INVX2TS U5969 ( .A(n3515), .Y(n3234) );
NOR2X2TS U5970 ( .A(n3232), .B(DP_OP_497J2_123_1725_n638), .Y(n5540) );
NOR2X4TS U5971 ( .A(n3234), .B(n3233), .Y(n3262) );
INVX2TS U5972 ( .A(n3262), .Y(n3235) );
NAND2X1TS U5973 ( .A(n3235), .B(n3261), .Y(n3236) );
OR2X2TS U5974 ( .A(n3238), .B(n3237), .Y(n3239) );
NOR2X2TS U5975 ( .A(n3295), .B(n8344), .Y(n3273) );
INVX2TS U5976 ( .A(n2317), .Y(n3248) );
INVX2TS U5977 ( .A(n4731), .Y(n3277) );
INVX2TS U5978 ( .A(n3465), .Y(n3281) );
INVX2TS U5979 ( .A(n4730), .Y(n3280) );
XOR2X4TS U5980 ( .A(n3255), .B(DP_OP_497J2_123_1725_n392), .Y(n3445) );
ADDHX1TS U5981 ( .A(DP_OP_497J2_123_1725_n791), .B(FPMULT_Op_MX[18]), .CO(
n3256), .S(n3231) );
INVX2TS U5982 ( .A(n3288), .Y(n3259) );
NAND2X2TS U5983 ( .A(n3258), .B(n3257), .Y(n3286) );
INVX2TS U5984 ( .A(n3260), .Y(n3263) );
NOR2X2TS U5985 ( .A(n3480), .B(n3270), .Y(n3483) );
ADDFHX4TS U5986 ( .A(n3273), .B(n3272), .CI(n3271), .CO(n3476), .S(n3266) );
ADDFHX4TS U5987 ( .A(n3277), .B(n3276), .CI(n3275), .CO(n3351), .S(n3258) );
ADDHX1TS U5988 ( .A(DP_OP_497J2_123_1725_n792), .B(DP_OP_497J2_123_1725_n705), .CO(n3278), .S(n3254) );
NOR2X8TS U5989 ( .A(n3860), .B(n5707), .Y(n3298) );
OAI22X1TS U5990 ( .A0(n3393), .A1(n3422), .B0(n2351), .B1(n3446), .Y(n3349)
);
CMPR32X2TS U5991 ( .A(n3281), .B(n3466), .C(n3280), .CO(n3335), .S(n3275) );
INVX2TS U5992 ( .A(n3282), .Y(n3320) );
INVX2TS U5993 ( .A(n3466), .Y(n3319) );
NOR2X2TS U5994 ( .A(n3174), .B(n2304), .Y(n3322) );
NAND2X2TS U5995 ( .A(n3285), .B(n3284), .Y(n3373) );
NAND2X2TS U5996 ( .A(n3376), .B(n3373), .Y(n3289) );
XNOR2X4TS U5997 ( .A(n3086), .B(n3292), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[8]) );
NAND2BX4TS U5998 ( .AN(n3175), .B(DP_OP_497J2_123_1725_n782), .Y(n3419) );
OAI21X4TS U5999 ( .A0(n3299), .A1(n3298), .B0(n3297), .Y(n3304) );
NAND2X4TS U6000 ( .A(n3302), .B(n3301), .Y(n3303) );
OAI22X2TS U6001 ( .A0(n2434), .A1(n3441), .B0(n3521), .B1(n3519), .Y(n3404)
);
NOR2X4TS U6002 ( .A(DP_OP_497J2_123_1725_n716), .B(n2771), .Y(n3308) );
OAI22X1TS U6003 ( .A0(n2349), .A1(n3422), .B0(n2434), .B1(n3446), .Y(n3402)
);
NOR2X2TS U6004 ( .A(n3174), .B(n3355), .Y(n3327) );
NOR2X2TS U6005 ( .A(n3538), .B(n2304), .Y(n3326) );
INVX2TS U6006 ( .A(n3628), .Y(n3330) );
INVX4TS U6007 ( .A(n3622), .Y(n3337) );
OAI22X1TS U6008 ( .A0(n3393), .A1(n3441), .B0(n2351), .B1(n3519), .Y(n3372)
);
ADDFHX2TS U6009 ( .A(n3345), .B(n3344), .CI(n3343), .CO(n3363), .S(n3346) );
OAI22X1TS U6010 ( .A0(n3521), .A1(n3422), .B0(n2428), .B1(n3446), .Y(n3369)
);
ADDFHX2TS U6011 ( .A(n3348), .B(n3347), .CI(n3346), .CO(n3359), .S(n3368) );
ADDHX4TS U6012 ( .A(n3357), .B(n3356), .CO(n3398), .S(n3314) );
OAI22X1TS U6013 ( .A0(n2433), .A1(n3422), .B0(n3521), .B1(n3446), .Y(n3385)
);
ADDFHX2TS U6014 ( .A(n3366), .B(n3365), .CI(n3364), .CO(n3417), .S(n3383) );
INVX2TS U6015 ( .A(n3373), .Y(n3374) );
AO21X4TS U6016 ( .A0(n3376), .A1(n3375), .B0(n3374), .Y(n3470) );
INVX4TS U6017 ( .A(n3468), .Y(n3379) );
ADDFHX2TS U6018 ( .A(n3385), .B(n3384), .CI(n3383), .CO(n3390), .S(n3386) );
OAI21X4TS U6019 ( .A0(n3491), .A1(n3489), .B0(n3490), .Y(n3502) );
OAI22X1TS U6020 ( .A0(n3393), .A1(n3612), .B0(n2351), .B1(n2299), .Y(n3443)
);
INVX2TS U6021 ( .A(n3677), .Y(n3442) );
CMPR22X2TS U6022 ( .A(FPMULT_Op_MX[18]), .B(DP_OP_497J2_123_1725_n686), .CO(
n3452), .S(n3399) );
ADDFHX4TS U6023 ( .A(n3407), .B(n3406), .CI(n3405), .CO(n3434), .S(n3418) );
OAI22X2TS U6024 ( .A0(n2349), .A1(n2298), .B0(n2434), .B1(n3318), .Y(n3524)
);
OAI22X2TS U6025 ( .A0(n3521), .A1(n3612), .B0(n2428), .B1(n2299), .Y(n3527)
);
ADDFHX4TS U6026 ( .A(n3452), .B(DP_OP_497J2_123_1725_n669), .CI(n3451), .CO(
n3544), .S(n3448) );
NAND2X2TS U6027 ( .A(n3469), .B(n3468), .Y(n3471) );
XNOR2X4TS U6028 ( .A(n3471), .B(n3470), .Y(n3487) );
NOR2X2TS U6029 ( .A(n2317), .B(n3474), .Y(n3505) );
OAI21X4TS U6030 ( .A0(n3474), .A1(n3473), .B0(n3472), .Y(n3511) );
INVX2TS U6031 ( .A(n3511), .Y(n3475) );
ADDFHX4TS U6032 ( .A(n3478), .B(n3477), .CI(n3476), .CO(n3582), .S(n3541) );
INVX2TS U6033 ( .A(n3504), .Y(n3493) );
INVX2TS U6034 ( .A(n3508), .Y(n3492) );
AOI21X1TS U6035 ( .A0(n3511), .A1(n3493), .B0(n3492), .Y(n3494) );
INVX2TS U6036 ( .A(n3638), .Y(n3497) );
NOR2X2TS U6037 ( .A(n3604), .B(n3497), .Y(n3507) );
INVX2TS U6038 ( .A(n3507), .Y(n3498) );
NAND2X1TS U6039 ( .A(n3604), .B(n3497), .Y(n3506) );
NAND2X4TS U6040 ( .A(n3501), .B(n3500), .Y(n3503) );
NOR2X1TS U6041 ( .A(n3504), .B(n3507), .Y(n3510) );
AOI21X1TS U6042 ( .A0(n3511), .A1(n3510), .B0(n3509), .Y(n3512) );
ADDFHX4TS U6043 ( .A(n3531), .B(n3530), .CI(n3529), .CO(n3562), .S(n3550) );
ADDFHX4TS U6044 ( .A(n3534), .B(n3533), .CI(n3532), .CO(n3579), .S(n3530) );
NOR2X2TS U6045 ( .A(n3175), .B(n8285), .Y(n3572) );
ADDFHX4TS U6046 ( .A(n2241), .B(n3546), .CI(n3545), .CO(n3583), .S(n3533) );
NAND2X1TS U6047 ( .A(n3185), .B(n3626), .Y(n3558) );
CLKXOR2X2TS U6048 ( .A(n3558), .B(n3625), .Y(n3559) );
ADDFHX4TS U6049 ( .A(n3563), .B(n3562), .CI(n3561), .CO(n3590), .S(n3553) );
ADDFHX2TS U6050 ( .A(n3566), .B(n3565), .CI(n3564), .CO(n3594), .S(n3587) );
ADDFHX4TS U6051 ( .A(DP_OP_496J2_122_3540_n1502), .B(n7454), .CI(n3572),
.CO(n3605), .S(n3575) );
INVX2TS U6052 ( .A(n5402), .Y(n3615) );
ADDFHX4TS U6053 ( .A(n3576), .B(n3575), .CI(n3574), .CO(n5403), .S(n5156) );
INVX2TS U6054 ( .A(n5403), .Y(n3613) );
NOR2X2TS U6055 ( .A(n3664), .B(n3318), .Y(n3608) );
ADDFHX4TS U6056 ( .A(n3587), .B(n3586), .CI(n3585), .CO(n3595), .S(n3563) );
ADDFHX4TS U6057 ( .A(n3603), .B(n3602), .CI(n3601), .CO(n3648), .S(n3597) );
CLKINVX6TS U6058 ( .A(n5557), .Y(n5611) );
NOR2X1TS U6059 ( .A(n2435), .B(n3606), .Y(n3636) );
INVX2TS U6060 ( .A(n2434), .Y(n3611) );
ADDFHX4TS U6061 ( .A(n3618), .B(n3617), .CI(n3616), .CO(n3619), .S(n3591) );
INVX2TS U6062 ( .A(n3654), .Y(n3624) );
NAND2X1TS U6063 ( .A(n3624), .B(n3653), .Y(n3630) );
OR2X2TS U6064 ( .A(n3628), .B(n3627), .Y(n3683) );
NAND2X1TS U6065 ( .A(n3626), .B(n3625), .Y(n3684) );
INVX2TS U6066 ( .A(n3682), .Y(n3629) );
CLKXOR2X2TS U6067 ( .A(n3630), .B(n3655), .Y(n3688) );
ADDFHX4TS U6068 ( .A(n3635), .B(n3634), .CI(n3633), .CO(n3651), .S(n3620) );
CMPR32X2TS U6069 ( .A(n2919), .B(n3637), .C(n3636), .CO(n3670), .S(n3646) );
ADDHX1TS U6070 ( .A(n3638), .B(n5611), .CO(n3667), .S(n3637) );
INVX2TS U6071 ( .A(n3640), .Y(n3665) );
ADDFHX2TS U6072 ( .A(n3643), .B(n3642), .CI(n3641), .CO(n3668), .S(n3644) );
ADDFHX4TS U6073 ( .A(n3646), .B(n3645), .CI(n3644), .CO(n3662), .S(n3647) );
OAI21X2TS U6074 ( .A0(n3655), .A1(n3654), .B0(n3653), .Y(n3705) );
INVX2TS U6075 ( .A(n3705), .Y(n3675) );
NOR2X2TS U6076 ( .A(n3657), .B(n3656), .Y(n3700) );
INVX2TS U6077 ( .A(n3700), .Y(n3658) );
NAND2X1TS U6078 ( .A(n3658), .B(n3702), .Y(n3659) );
CLKXOR2X2TS U6079 ( .A(n3675), .B(n3659), .Y(n3690) );
INVX2TS U6080 ( .A(n3694), .Y(n3673) );
NAND2X2TS U6081 ( .A(n3673), .B(n3693), .Y(n3674) );
OAI21X1TS U6082 ( .A0(n3675), .A1(n3700), .B0(n3702), .Y(n3680) );
NOR2X2TS U6083 ( .A(n3677), .B(n3676), .Y(n3703) );
INVX2TS U6084 ( .A(n3703), .Y(n3678) );
NAND2X1TS U6085 ( .A(n3678), .B(n3701), .Y(n3679) );
XNOR2X2TS U6086 ( .A(n3680), .B(n3679), .Y(n3691) );
NAND2X1TS U6087 ( .A(n3683), .B(n3682), .Y(n3685) );
XNOR2X2TS U6088 ( .A(n3685), .B(n3684), .Y(n3686) );
CMPR32X2TS U6089 ( .A(n3698), .B(n3697), .C(n3696), .CO(n3699), .S(n3671) );
OAI21X1TS U6090 ( .A0(n3703), .A1(n3702), .B0(n3701), .Y(n3704) );
AOI21X4TS U6091 ( .A0(n3706), .A1(n3705), .B0(n3704), .Y(n5618) );
NOR2X2TS U6092 ( .A(n3707), .B(n3708), .Y(n5396) );
INVX2TS U6093 ( .A(n5396), .Y(n3709) );
NAND2X1TS U6094 ( .A(n3709), .B(n5398), .Y(n3710) );
CLKXOR2X2TS U6095 ( .A(n5618), .B(n3710), .Y(n3711) );
INVX8TS U6096 ( .A(n3714), .Y(add_x_69_n69) );
INVX2TS U6097 ( .A(n3717), .Y(n3719) );
NAND2X2TS U6098 ( .A(n3719), .B(n3718), .Y(n3720) );
XOR2X4TS U6099 ( .A(n2330), .B(n3723), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[11]) );
INVX2TS U6100 ( .A(n3728), .Y(n3730) );
CLKXOR2X2TS U6101 ( .A(n3732), .B(n3731), .Y(
FPMULT_Sgf_operation_EVEN1_Q_left[5]) );
NOR2BX4TS U6102 ( .AN(n7709), .B(DP_OP_496J2_122_3540_n1512), .Y(n3743) );
INVX4TS U6103 ( .A(n3743), .Y(n3873) );
NAND2X2TS U6104 ( .A(FPMULT_Op_MX[19]), .B(DP_OP_496J2_122_3540_n1513), .Y(
n3748) );
OR2X4TS U6105 ( .A(FPMULT_Op_MX[20]), .B(DP_OP_496J2_122_3540_n1514), .Y(
n3831) );
INVX2TS U6106 ( .A(n3829), .Y(n3744) );
INVX2TS U6107 ( .A(n3746), .Y(n3747) );
NAND2X2TS U6108 ( .A(n3826), .B(n3809), .Y(n3757) );
NAND2BX4TS U6109 ( .AN(n3787), .B(n3172), .Y(n3964) );
OAI21X2TS U6110 ( .A0(n3765), .A1(n3764), .B0(n3763), .Y(n3767) );
NAND2X2TS U6111 ( .A(n3765), .B(n3764), .Y(n3766) );
NAND2X4TS U6112 ( .A(n3767), .B(n3766), .Y(n3888) );
XNOR2X4TS U6113 ( .A(n3777), .B(n3776), .Y(n4916) );
INVX6TS U6114 ( .A(n3779), .Y(n3794) );
NAND2X4TS U6115 ( .A(n3800), .B(n3781), .Y(n3817) );
INVX2TS U6116 ( .A(n3885), .Y(n3784) );
OAI22X2TS U6117 ( .A0(n4627), .A1(n2271), .B0(n3789), .B1(n4626), .Y(n4581)
);
INVX2TS U6118 ( .A(n4581), .Y(n3930) );
NAND2X8TS U6119 ( .A(n3792), .B(n2429), .Y(n4600) );
XNOR2X1TS U6120 ( .A(n2430), .B(n2382), .Y(n3793) );
OAI22X2TS U6121 ( .A0(n4600), .A1(n3793), .B0(n2243), .B1(n3801), .Y(n3980)
);
XNOR2X2TS U6122 ( .A(n3800), .B(n2440), .Y(n3797) );
XNOR2X2TS U6123 ( .A(n2305), .B(n2438), .Y(n3799) );
INVX4TS U6124 ( .A(n4579), .Y(n3922) );
OAI22X4TS U6125 ( .A0(n4600), .A1(n4599), .B0(n2243), .B1(n3796), .Y(n4576)
);
NOR2BX1TS U6126 ( .AN(n2382), .B(n3798), .Y(n3892) );
OAI21X4TS U6127 ( .A0(n3819), .A1(n3817), .B0(n3820), .Y(n3804) );
OAI2BB1X4TS U6128 ( .A0N(FPMULT_Op_MX[22]), .A1N(n2274), .B0(n3807), .Y(
n3808) );
XOR2X4TS U6129 ( .A(n3810), .B(n3823), .Y(n3825) );
ADDFHX4TS U6130 ( .A(n6900), .B(n3860), .CI(n3811), .CO(n3752), .S(n3822) );
XNOR2X4TS U6131 ( .A(n3825), .B(n3812), .Y(n3816) );
XNOR2X4TS U6132 ( .A(n2440), .B(n3822), .Y(n3914) );
NAND2X2TS U6133 ( .A(n3906), .B(n3914), .Y(n3815) );
XOR2X1TS U6134 ( .A(n3823), .B(n3822), .Y(n3824) );
NOR2X2TS U6135 ( .A(n3825), .B(n3824), .Y(n3827) );
NAND2X2TS U6136 ( .A(n3828), .B(n3831), .Y(n3846) );
INVX2TS U6137 ( .A(n3846), .Y(n3839) );
AOI21X4TS U6138 ( .A0(n3831), .A1(n3830), .B0(n3829), .Y(n3851) );
INVX2TS U6139 ( .A(n3851), .Y(n3841) );
AOI21X4TS U6140 ( .A0(n2940), .A1(n3839), .B0(n3841), .Y(n3834) );
INVX6TS U6141 ( .A(n3832), .Y(n3845) );
XNOR2X2TS U6142 ( .A(n3931), .B(n4940), .Y(n3953) );
OR2X2TS U6143 ( .A(n3175), .B(n3172), .Y(n3838) );
NAND2X2TS U6144 ( .A(n3839), .B(n3845), .Y(n3843) );
AOI21X4TS U6145 ( .A0(n3841), .A1(n3845), .B0(n3849), .Y(n3842) );
OAI22X1TS U6146 ( .A0(n3953), .A1(n5210), .B0(n4116), .B1(n5209), .Y(n4123)
);
INVX4TS U6147 ( .A(n4940), .Y(n5212) );
NAND2X4TS U6148 ( .A(n3845), .B(n3850), .Y(n3852) );
NOR2X2TS U6149 ( .A(n3846), .B(n3852), .Y(n3853) );
INVX2TS U6150 ( .A(n3847), .Y(n3848) );
XNOR2X4TS U6151 ( .A(n8486), .B(n7454), .Y(n3861) );
NOR2X1TS U6152 ( .A(n6900), .B(n3860), .Y(n3857) );
XNOR2X1TS U6153 ( .A(n3861), .B(n3857), .Y(n3858) );
XOR2X4TS U6154 ( .A(n3859), .B(n3858), .Y(n3866) );
XOR2X1TS U6155 ( .A(n3860), .B(n7454), .Y(n3862) );
NOR2X1TS U6156 ( .A(n3862), .B(n3861), .Y(n3864) );
XOR2X1TS U6157 ( .A(n3864), .B(n3863), .Y(n3865) );
XNOR2X2TS U6158 ( .A(n2442), .B(n3800), .Y(n3899) );
OAI22X2TS U6159 ( .A0(n4627), .A1(n3899), .B0(n4098), .B1(n4626), .Y(n4111)
);
OAI22X4TS U6160 ( .A0(n3894), .A1(n3996), .B0(n3881), .B1(n4024), .Y(n3902)
);
OAI22X2TS U6161 ( .A0(n4100), .A1(n2243), .B0(n4600), .B1(n3882), .Y(n4104)
);
INVX2TS U6162 ( .A(n3895), .Y(n4102) );
INVX2TS U6163 ( .A(n4586), .Y(n4092) );
NAND2X2TS U6164 ( .A(n3885), .B(n3884), .Y(n3886) );
OAI22X2TS U6165 ( .A0(n3894), .A1(n4024), .B0(n3996), .B1(n3893), .Y(n3897)
);
XNOR2X1TS U6166 ( .A(n2442), .B(n2382), .Y(n3896) );
OAI22X1TS U6167 ( .A0(n4627), .A1(n3896), .B0(n3900), .B1(n4626), .Y(n3926)
);
OAI22X2TS U6168 ( .A0(n3900), .A1(n4627), .B0(n3899), .B1(n4626), .Y(n3969)
);
XNOR2X4TS U6169 ( .A(n3906), .B(n3914), .Y(n3907) );
XOR2X2TS U6170 ( .A(n3908), .B(n3911), .Y(n3912) );
XNOR2X2TS U6171 ( .A(n3909), .B(n3912), .Y(n3910) );
NOR2X1TS U6172 ( .A(n3912), .B(n3911), .Y(n3913) );
CLKXOR2X2TS U6173 ( .A(n3914), .B(n3913), .Y(n3915) );
NOR2BX1TS U6174 ( .AN(n4001), .B(n2376), .Y(n4056) );
INVX4TS U6175 ( .A(n4582), .Y(n3937) );
XNOR2X2TS U6176 ( .A(n3931), .B(n4006), .Y(n3952) );
OAI22X2TS U6177 ( .A0(n3952), .A1(n4934), .B0(n4933), .B1(n3932), .Y(n3976)
);
XNOR2X2TS U6178 ( .A(n3951), .B(n4940), .Y(n3954) );
XNOR2X1TS U6179 ( .A(n4027), .B(n4940), .Y(n3933) );
OAI22X2TS U6180 ( .A0(n3954), .A1(n5209), .B0(n3933), .B1(n5210), .Y(n3975)
);
OAI22X2TS U6181 ( .A0(n3950), .A1(n3993), .B0(n3935), .B1(n3072), .Y(n3955)
);
ADDFHX2TS U6182 ( .A(n3943), .B(n3942), .CI(n3941), .CO(n4089), .S(n3989) );
XNOR2X1TS U6183 ( .A(n5198), .B(n4001), .Y(n3949) );
OAI22X1TS U6184 ( .A0(n4008), .A1(n4934), .B0(n3952), .B1(n4933), .Y(n4053)
);
OAI22X1TS U6185 ( .A0(n3954), .A1(n5210), .B0(n3953), .B1(n5209), .Y(n3973)
);
ADDFHX2TS U6186 ( .A(n3959), .B(n3958), .CI(n3957), .CO(n4122), .S(n3971) );
OAI22X4TS U6187 ( .A0(n2231), .A1(n3967), .B0(n5416), .B1(n4112), .Y(n4096)
);
INVX2TS U6188 ( .A(n4585), .Y(n4113) );
ADDFHX2TS U6189 ( .A(n3973), .B(n3972), .CI(n3971), .CO(n5381), .S(n5360) );
INVX2TS U6190 ( .A(n5291), .Y(n4071) );
NAND2BX1TS U6191 ( .AN(n4027), .B(n4006), .Y(n3977) );
OAI22X2TS U6192 ( .A0(n4934), .A1(n2707), .B0(n4933), .B1(n3977), .Y(n4012)
);
OAI22X4TS U6193 ( .A0(n3992), .A1(n3993), .B0(n3978), .B1(n3072), .Y(n4011)
);
CMPR22X2TS U6194 ( .A(n3980), .B(n3979), .CO(n4579), .S(n4577) );
INVX2TS U6195 ( .A(n4577), .Y(n4017) );
INVX2TS U6196 ( .A(n4779), .Y(n4023) );
NAND2BX1TS U6197 ( .AN(n2382), .B(n2439), .Y(n3997) );
NAND2X1TS U6198 ( .A(n4094), .B(n3998), .Y(n4021) );
INVX2TS U6199 ( .A(n3999), .Y(n4000) );
INVX2TS U6200 ( .A(n4003), .Y(n4019) );
NOR2BX1TS U6201 ( .AN(n4025), .B(n4024), .Y(n5135) );
INVX2TS U6202 ( .A(n5135), .Y(n4028) );
NAND2X2TS U6203 ( .A(n4029), .B(n4028), .Y(n4698) );
INVX2TS U6204 ( .A(n4698), .Y(n4030) );
INVX2TS U6205 ( .A(n4757), .Y(n4033) );
AOI21X4TS U6206 ( .A0(n4758), .A1(n3156), .B0(n4033), .Y(n4689) );
ADDFHX4TS U6207 ( .A(n4036), .B(n4035), .CI(n4034), .CO(n4060), .S(n4041) );
NOR2X4TS U6208 ( .A(n4041), .B(n4040), .Y(n4686) );
NAND2X2TS U6209 ( .A(n4041), .B(n4040), .Y(n4687) );
OAI21X4TS U6210 ( .A0(n4689), .A1(n4686), .B0(n4687), .Y(n4848) );
AOI21X4TS U6211 ( .A0(n3191), .A1(n4848), .B0(n4044), .Y(n4877) );
ADDFHX2TS U6212 ( .A(n4049), .B(n4048), .CI(n4047), .CO(n4070), .S(n4073) );
INVX4TS U6213 ( .A(n5278), .Y(n4067) );
ADDFHX4TS U6214 ( .A(n4061), .B(n4060), .CI(n4059), .CO(n4062), .S(n4043) );
NOR2X6TS U6215 ( .A(n4063), .B(n4062), .Y(n4873) );
NAND2X4TS U6216 ( .A(n4063), .B(n4062), .Y(n4875) );
ADDFHX4TS U6217 ( .A(n4068), .B(n4067), .CI(n4066), .CO(n4081), .S(n4072) );
ADDFHX2TS U6218 ( .A(n4071), .B(n4070), .CI(n4069), .CO(n4079), .S(n4080) );
ADDFHX4TS U6219 ( .A(n4074), .B(n4073), .CI(n4072), .CO(n4075), .S(n4063) );
NOR2X8TS U6220 ( .A(n4084), .B(n4083), .Y(n4652) );
ADDFHX2TS U6221 ( .A(n4092), .B(n4091), .CI(n4090), .CO(n4944), .S(n4127) );
XNOR2X1TS U6222 ( .A(n2441), .B(n3806), .Y(n4588) );
INVX2TS U6223 ( .A(n3800), .Y(n4592) );
OAI22X2TS U6224 ( .A0(n4633), .A1(n4102), .B0(n2644), .B1(n4592), .Y(n4589)
);
ADDFHX2TS U6225 ( .A(n4105), .B(n4104), .CI(n4103), .CO(n4593), .S(n4109) );
ADDFHX4TS U6226 ( .A(n4111), .B(n4110), .CI(n4109), .CO(n4616), .S(n4586) );
XNOR2X2TS U6227 ( .A(n5179), .B(n5345), .Y(n4918) );
ADDFHX4TS U6228 ( .A(n4115), .B(n4114), .CI(n4113), .CO(n4926), .S(n4125) );
INVX2TS U6229 ( .A(n3931), .Y(n4119) );
ADDFHX4TS U6230 ( .A(n4123), .B(n4122), .CI(n4121), .CO(n5548), .S(n5380) );
NOR2X2TS U6231 ( .A(DP_OP_498J2_124_1725_n635), .B(n4165), .Y(n4149) );
NOR2X4TS U6232 ( .A(n8489), .B(n4166), .Y(n4136) );
NOR2X4TS U6233 ( .A(n4185), .B(n4243), .Y(n4135) );
NOR2X4TS U6234 ( .A(n2245), .B(n4165), .Y(n4144) );
ADDHX4TS U6235 ( .A(n4136), .B(n4135), .CO(n4139), .S(n4148) );
ADDFHX2TS U6236 ( .A(n4139), .B(n4138), .CI(n4137), .CO(n4249), .S(n4150) );
INVX2TS U6237 ( .A(n4140), .Y(n4239) );
NOR2X2TS U6238 ( .A(n4449), .B(n4441), .Y(n4250) );
INVX2TS U6239 ( .A(n4250), .Y(n4146) );
NAND2X2TS U6240 ( .A(n4146), .B(n4257), .Y(n4176) );
ADDFHX2TS U6241 ( .A(n4149), .B(n4148), .CI(n4147), .CO(n4152), .S(n4157) );
NOR2X6TS U6242 ( .A(n4417), .B(n4390), .Y(n4189) );
NOR2X4TS U6243 ( .A(n4185), .B(n4242), .Y(n4161) );
CMPR22X2TS U6244 ( .A(n4154), .B(n4153), .CO(n4147), .S(n4169) );
NOR2X4TS U6245 ( .A(n4189), .B(n4709), .Y(n4175) );
NOR2X4TS U6246 ( .A(DP_OP_498J2_124_1725_n636), .B(DP_OP_498J2_124_1725_n645), .Y(n4173) );
NOR2X6TS U6247 ( .A(n4185), .B(n4165), .Y(n4734) );
NAND2X2TS U6248 ( .A(n4205), .B(n4204), .Y(n4737) );
OAI21X2TS U6249 ( .A0(n4736), .A1(n4739), .B0(n4737), .Y(n4726) );
NAND2X2TS U6250 ( .A(n4224), .B(n4219), .Y(n4724) );
INVX2TS U6251 ( .A(n4724), .Y(n4167) );
AOI21X2TS U6252 ( .A0(n3181), .A1(n4726), .B0(n4167), .Y(n4718) );
NAND2X2TS U6253 ( .A(n4295), .B(n4276), .Y(n4715) );
OAI21X4TS U6254 ( .A0(n4718), .A1(n4714), .B0(n4715), .Y(n4188) );
NAND2X2TS U6255 ( .A(n4350), .B(n4323), .Y(n4710) );
XOR2X4TS U6256 ( .A(n4176), .B(n4311), .Y(n4200) );
INVX2TS U6257 ( .A(n4733), .Y(n4210) );
NAND2X4TS U6258 ( .A(DP_OP_498J2_124_1725_n732), .B(
DP_OP_498J2_124_1725_n645), .Y(n4177) );
INVX4TS U6259 ( .A(n4178), .Y(n4440) );
INVX2TS U6260 ( .A(n4472), .Y(n4202) );
ADDHX1TS U6261 ( .A(FPMULT_Op_MY[6]), .B(DP_OP_498J2_124_1725_n788), .CO(
n4181), .S(n4179) );
INVX4TS U6262 ( .A(n4181), .Y(n4448) );
OAI22X2TS U6263 ( .A0(n2378), .A1(n4407), .B0(n4331), .B1(n4448), .Y(n4182)
);
NAND2X2TS U6264 ( .A(n4183), .B(n4182), .Y(n4233) );
NOR2X2TS U6265 ( .A(n4355), .B(DP_OP_498J2_124_1725_n732), .Y(n4426) );
INVX2TS U6266 ( .A(n4426), .Y(n4195) );
INVX2TS U6267 ( .A(n7210), .Y(n4194) );
NOR2X1TS U6268 ( .A(n4331), .B(n4407), .Y(n4198) );
INVX2TS U6269 ( .A(n4198), .Y(n4186) );
AND2X2TS U6270 ( .A(n4196), .B(n4186), .Y(n4234) );
CLKXOR2X2TS U6271 ( .A(n4187), .B(n4234), .Y(n4199) );
INVX2TS U6272 ( .A(n4189), .Y(n4191) );
NAND2X1TS U6273 ( .A(n3162), .B(n4196), .Y(n4197) );
NAND2X4TS U6274 ( .A(n4200), .B(n4199), .Y(n4701) );
AOI21X4TS U6275 ( .A0(n4702), .A1(n4703), .B0(n4201), .Y(n4751) );
INVX2TS U6276 ( .A(n4473), .Y(n4222) );
ADDHX1TS U6277 ( .A(n8518), .B(DP_OP_498J2_124_1725_n789), .CO(n4207), .S(
n4178) );
ADDFHX4TS U6278 ( .A(n4210), .B(n4209), .CI(n4208), .CO(n4228), .S(n4183) );
XOR2X4TS U6279 ( .A(n7700), .B(n4212), .Y(n4213) );
OAI22X1TS U6280 ( .A0(n2436), .A1(n4407), .B0(n2378), .B1(n4448), .Y(n4227)
);
ADDFHX4TS U6281 ( .A(n4216), .B(n4215), .CI(n4214), .CO(n4283), .S(n4230) );
INVX4TS U6282 ( .A(n4217), .Y(n4550) );
OAI22X2TS U6283 ( .A0(n2377), .A1(n4495), .B0(n4331), .B1(n4550), .Y(n4282)
);
INVX2TS U6284 ( .A(n4518), .Y(n4279) );
INVX4TS U6285 ( .A(n4219), .Y(n4278) );
OAI22X1TS U6286 ( .A0(n2436), .A1(n4440), .B0(n2377), .B1(n4491), .Y(n4286)
);
BUFX8TS U6287 ( .A(DP_OP_498J2_124_1725_n803), .Y(n5706) );
INVX12TS U6288 ( .A(n4221), .Y(n4549) );
NAND2X2TS U6289 ( .A(n4237), .B(n4236), .Y(n4262) );
INVX2TS U6290 ( .A(n4262), .Y(n4238) );
NAND2X2TS U6291 ( .A(n4251), .B(n4510), .Y(n4259) );
OAI21X4TS U6292 ( .A0(n4258), .A1(n4257), .B0(n4259), .Y(n4371) );
NOR2X2TS U6293 ( .A(n3150), .B(n2953), .Y(n4316) );
NOR2X2TS U6294 ( .A(n4548), .B(n4547), .Y(n4364) );
INVX2TS U6295 ( .A(n4364), .Y(n4313) );
NAND2X1TS U6296 ( .A(n4313), .B(n4368), .Y(n4256) );
INVX4TS U6297 ( .A(n4270), .Y(n4754) );
OAI21X4TS U6298 ( .A0(n4311), .A1(n4250), .B0(n4257), .Y(n4261) );
XNOR2X4TS U6299 ( .A(n4261), .B(n4260), .Y(n4267) );
NAND2X2TS U6300 ( .A(n4263), .B(n4262), .Y(n4265) );
XNOR2X2TS U6301 ( .A(n4265), .B(n4264), .Y(n4266) );
OR2X4TS U6302 ( .A(n4267), .B(n4266), .Y(n4760) );
NAND2X2TS U6303 ( .A(n4754), .B(n4760), .Y(n4272) );
NAND2X2TS U6304 ( .A(n4269), .B(n4268), .Y(n4753) );
OA21X4TS U6305 ( .A0(n4761), .A1(n4270), .B0(n4753), .Y(n4271) );
OAI21X4TS U6306 ( .A0(n4751), .A1(n4272), .B0(n4271), .Y(n4853) );
XNOR2X4TS U6307 ( .A(n4332), .B(n4335), .Y(n4280) );
INVX6TS U6308 ( .A(n4277), .Y(n4955) );
ADDHX4TS U6309 ( .A(n4279), .B(n4278), .CO(n4325), .S(n4300) );
XNOR2X4TS U6310 ( .A(n4280), .B(n4334), .Y(n4348) );
INVX2TS U6311 ( .A(n4295), .Y(n4338) );
OAI22X2TS U6312 ( .A0(n2437), .A1(n4495), .B0(n2378), .B1(n4550), .Y(n4337)
);
ADDFHX2TS U6313 ( .A(n4298), .B(n4297), .CI(n4296), .CO(n4336), .S(n4284) );
INVX2TS U6314 ( .A(n4984), .Y(n4339) );
NAND2X4TS U6315 ( .A(n4305), .B(n4361), .Y(n4310) );
XOR2X4TS U6316 ( .A(n4310), .B(n4362), .Y(n4321) );
NAND2X1TS U6317 ( .A(n4365), .B(n4313), .Y(n4315) );
INVX2TS U6318 ( .A(n4368), .Y(n4312) );
AOI21X1TS U6319 ( .A0(n4371), .A1(n4313), .B0(n4312), .Y(n4314) );
OAI21X2TS U6320 ( .A0(n4311), .A1(n4315), .B0(n4314), .Y(n4319) );
NOR2X2TS U6321 ( .A(n4974), .B(n4971), .Y(n4367) );
INVX2TS U6322 ( .A(n4367), .Y(n4317) );
NAND2X1TS U6323 ( .A(n4974), .B(n4971), .Y(n4366) );
NAND2X1TS U6324 ( .A(n4317), .B(n4366), .Y(n4318) );
OR2X4TS U6325 ( .A(n4321), .B(n4320), .Y(n4850) );
NAND2X2TS U6326 ( .A(n4321), .B(n4320), .Y(n4851) );
INVX2TS U6327 ( .A(n5044), .Y(n4387) );
ADDHX1TS U6328 ( .A(DP_OP_498J2_124_1725_n792), .B(DP_OP_498J2_124_1725_n786), .CO(n4330), .S(n4277) );
INVX4TS U6329 ( .A(n4330), .Y(n5032) );
OAI22X1TS U6330 ( .A0(n2377), .A1(n4955), .B0(n4331), .B1(n5032), .Y(n4410)
);
XOR2X4TS U6331 ( .A(n4343), .B(n4342), .Y(n4536) );
ADDFHX4TS U6332 ( .A(n4349), .B(n4348), .CI(n4347), .CO(n4380), .S(n4346) );
NOR2X2TS U6333 ( .A(DP_OP_498J2_124_1725_n722), .B(n4391), .Y(n4394) );
ADDHX4TS U6334 ( .A(n4354), .B(n4353), .CO(n4393), .S(n4328) );
INVX2TS U6335 ( .A(n5043), .Y(n4381) );
OAI21X1TS U6336 ( .A0(n4368), .A1(n4367), .B0(n4366), .Y(n4369) );
AOI21X1TS U6337 ( .A0(n4371), .A1(n4370), .B0(n4369), .Y(n4372) );
ADDFHX2TS U6338 ( .A(n4383), .B(n4382), .CI(n4381), .CO(n4466), .S(n4379) );
ADDFHX4TS U6339 ( .A(n4389), .B(n4388), .CI(n4387), .CO(n4462), .S(n4420) );
OAI22X1TS U6340 ( .A0(n5031), .A1(n4440), .B0(n4954), .B1(n4491), .Y(n4461)
);
NOR2X2TS U6341 ( .A(n4973), .B(n4391), .Y(n4457) );
OAI22X1TS U6342 ( .A0(n2436), .A1(n4955), .B0(n2377), .B1(n5032), .Y(n4442)
);
INVX4TS U6343 ( .A(n5083), .Y(n4446) );
ADDFHX4TS U6344 ( .A(n4430), .B(n4429), .CI(n4428), .CO(n4467), .S(n4425) );
ADDFHX4TS U6345 ( .A(n4436), .B(n4435), .CI(n4434), .CO(n4513), .S(n4433) );
ADDFHX4TS U6346 ( .A(n4439), .B(n4438), .CI(n4437), .CO(n4512), .S(n4432) );
OAI22X2TS U6347 ( .A0(n4954), .A1(n4537), .B0(n4549), .B1(n4970), .Y(n4509)
);
ADDFHX4TS U6348 ( .A(n4444), .B(n4443), .CI(n4442), .CO(n4494), .S(n4438) );
OAI22X2TS U6349 ( .A0(n5031), .A1(n4495), .B0(n4954), .B1(n4550), .Y(n4493)
);
OAI22X1TS U6350 ( .A0(n2436), .A1(n5029), .B0(n2377), .B1(n5070), .Y(n4498)
);
NOR2X2TS U6351 ( .A(n4484), .B(n2275), .Y(n4482) );
ADDFHX4TS U6352 ( .A(n4454), .B(n4453), .CI(n4452), .CO(n4489), .S(n4458) );
CMPR22X2TS U6353 ( .A(n4456), .B(n4455), .CO(n4486), .S(n4453) );
OAI21X4TS U6354 ( .A0(n4476), .A1(n4524), .B0(n4527), .Y(n4517) );
ADDFHX4TS U6355 ( .A(n4479), .B(n4478), .CI(n4477), .CO(n4515), .S(n4468) );
NOR2X2TS U6356 ( .A(n4484), .B(n4972), .Y(n4545) );
ADDFHX4TS U6357 ( .A(n4490), .B(n4489), .CI(n4488), .CO(n5366), .S(n5118) );
OAI22X2TS U6358 ( .A0(n4549), .A1(n5029), .B0(n2436), .B1(n5070), .Y(n4535)
);
ADDFHX4TS U6359 ( .A(n4501), .B(n4500), .CI(n4499), .CO(n4529), .S(n4477) );
ADDFHX4TS U6360 ( .A(n4504), .B(n4503), .CI(n4502), .CO(n4543), .S(n4500) );
NAND2X2TS U6361 ( .A(n4519), .B(n4518), .Y(n4568) );
NAND2X1TS U6362 ( .A(n3168), .B(n4568), .Y(n4520) );
ADDFHX4TS U6363 ( .A(n4530), .B(n4529), .CI(n4528), .CO(n4562), .S(n4514) );
INVX2TS U6364 ( .A(n4547), .Y(n4957) );
NOR2X2TS U6365 ( .A(n5030), .B(n4550), .Y(n4965) );
NAND2X1TS U6366 ( .A(n3182), .B(n4987), .Y(n4569) );
NAND2X1TS U6367 ( .A(n4568), .B(n4567), .Y(n4989) );
XNOR2X2TS U6368 ( .A(n4569), .B(n4989), .Y(n4570) );
INVX2TS U6369 ( .A(n4782), .Y(n4788) );
AOI21X4TS U6370 ( .A0(n4572), .A1(n4788), .B0(n4575), .Y(n4774) );
OAI21X4TS U6371 ( .A0(n4771), .A1(n4774), .B0(n4772), .Y(n4766) );
INVX2TS U6372 ( .A(n4764), .Y(n4580) );
NAND2X2TS U6373 ( .A(n4582), .B(n4581), .Y(n4804) );
OAI21X4TS U6374 ( .A0(n4803), .A1(n4806), .B0(n4804), .Y(n4816) );
OAI2BB1X4TS U6375 ( .A0N(n4587), .A1N(n4816), .B0(n3143), .Y(n4856) );
INVX2TS U6376 ( .A(n4856), .Y(n4621) );
OAI22X1TS U6377 ( .A0(n4627), .A1(n4588), .B0(n4606), .B1(n4626), .Y(n4598)
);
ADDFHX2TS U6378 ( .A(n2439), .B(n4590), .CI(n4589), .CO(n4597), .S(n4594) );
OAI22X2TS U6379 ( .A0(n4591), .A1(n4600), .B0(n2243), .B1(n4599), .Y(n4603)
);
INVX2TS U6380 ( .A(n2305), .Y(n4601) );
ADDFHX4TS U6381 ( .A(n4595), .B(n4594), .CI(n4593), .CO(n4914), .S(n4615) );
NOR2X4TS U6382 ( .A(n4915), .B(n4914), .Y(n4693) );
NOR2X4TS U6383 ( .A(n4691), .B(n4693), .Y(n4855) );
ADDFHX4TS U6384 ( .A(n4598), .B(n4597), .CI(n4596), .CO(n5181), .S(n4915) );
INVX2TS U6385 ( .A(n3806), .Y(n4613) );
OAI22X1TS U6386 ( .A0(n4627), .A1(n4606), .B0(n4614), .B1(n4626), .Y(n4607)
);
NOR2X4TS U6387 ( .A(n5181), .B(n5182), .Y(n4857) );
ADDFHX4TS U6388 ( .A(n4609), .B(n4608), .CI(n4607), .CO(n5204), .S(n5182) );
INVX2TS U6389 ( .A(n4630), .Y(n4623) );
OAI22X1TS U6390 ( .A0(n4627), .A1(n4614), .B0(n2271), .B1(n4626), .Y(n4622)
);
NOR2X4TS U6391 ( .A(n5204), .B(n5203), .Y(n4665) );
NOR2X2TS U6392 ( .A(n4857), .B(n4665), .Y(n4618) );
NAND2X4TS U6393 ( .A(n4616), .B(n4615), .Y(n4748) );
NAND2X2TS U6394 ( .A(n4915), .B(n4914), .Y(n4694) );
OAI21X4TS U6395 ( .A0(n4693), .A1(n4748), .B0(n4694), .Y(n4854) );
NAND2X2TS U6396 ( .A(n5182), .B(n5181), .Y(n4858) );
OAI21X1TS U6397 ( .A0(n4665), .A1(n4858), .B0(n4666), .Y(n4617) );
AOI21X2TS U6398 ( .A0(n4854), .A1(n4618), .B0(n4617), .Y(n4619) );
OAI21X4TS U6399 ( .A0(n4621), .A1(n4620), .B0(n4619), .Y(n4640) );
INVX2TS U6400 ( .A(n4638), .Y(n4628) );
AOI21X2TS U6401 ( .A0(n4640), .A1(n3142), .B0(n4628), .Y(n4634) );
NOR2X2TS U6402 ( .A(n4633), .B(n2240), .Y(n5418) );
XOR2X2TS U6403 ( .A(n4634), .B(n5415), .Y(n4683) );
XNOR2X4TS U6404 ( .A(n3016), .B(n4637), .Y(n5137) );
XNOR2X2TS U6405 ( .A(n4640), .B(n4639), .Y(n4677) );
NAND2X4TS U6406 ( .A(n4642), .B(n4641), .Y(n4643) );
XNOR2X4TS U6407 ( .A(n4644), .B(n4643), .Y(n5136) );
XOR2X4TS U6408 ( .A(n4647), .B(n4646), .Y(n4650) );
ADDFHX4TS U6409 ( .A(n4651), .B(n4650), .CI(n4649), .CO(n4896), .S(n4894) );
INVX2TS U6410 ( .A(n4652), .Y(n4654) );
NAND2X2TS U6411 ( .A(n4654), .B(n4653), .Y(n4655) );
XOR2X4TS U6412 ( .A(n4656), .B(n4655), .Y(n4679) );
NAND2X4TS U6413 ( .A(n4658), .B(n4657), .Y(n4660) );
XNOR2X4TS U6414 ( .A(n4660), .B(n4659), .Y(n4888) );
INVX2TS U6415 ( .A(n4855), .Y(n4661) );
INVX2TS U6416 ( .A(n4854), .Y(n4662) );
INVX2TS U6417 ( .A(n4665), .Y(n4667) );
NAND2X2TS U6418 ( .A(n4673), .B(n4672), .Y(n4674) );
XOR2X4TS U6419 ( .A(n4670), .B(n4674), .Y(n7213) );
ADDFHX2TS U6420 ( .A(n4677), .B(n4676), .CI(n4675), .CO(n4681), .S(n4886) );
ADDFHX4TS U6421 ( .A(n4680), .B(n4679), .CI(n4678), .CO(n4895), .S(n4685) );
ADDFHX2TS U6422 ( .A(n4683), .B(n4682), .CI(n4681), .CO(n4651), .S(n4684) );
CLKXOR2X2TS U6423 ( .A(n4690), .B(n4689), .Y(n4867) );
INVX2TS U6424 ( .A(n4691), .Y(n4749) );
INVX2TS U6425 ( .A(n4748), .Y(n4692) );
INVX2TS U6426 ( .A(n4693), .Y(n4695) );
XNOR2X1TS U6427 ( .A(n4700), .B(n4699), .Y(n4747) );
AND2X4TS U6428 ( .A(n4708), .B(n4707), .Y(n7206) );
INVX2TS U6429 ( .A(n4709), .Y(n4711) );
NAND2X1TS U6430 ( .A(n4711), .B(n4710), .Y(n4713) );
INVX2TS U6431 ( .A(n7205), .Y(n4810) );
INVX2TS U6432 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[5]), .Y(n4809) );
INVX2TS U6433 ( .A(n4714), .Y(n4716) );
INVX2TS U6434 ( .A(n7204), .Y(n4770) );
INVX2TS U6435 ( .A(n4719), .Y(n4721) );
CLKXOR2X2TS U6436 ( .A(n4723), .B(n4722), .Y(n5002) );
NAND2X1TS U6437 ( .A(n3181), .B(n4724), .Y(n4725) );
XNOR2X1TS U6438 ( .A(n4726), .B(n4725), .Y(n7203) );
INVX2TS U6439 ( .A(n7203), .Y(n4778) );
XNOR2X2TS U6440 ( .A(n4729), .B(n4728), .Y(n5734) );
AND2X2TS U6441 ( .A(n4732), .B(n4744), .Y(n5731) );
INVX2TS U6442 ( .A(n5731), .Y(n4785) );
INVX2TS U6443 ( .A(n7211), .Y(n4784) );
OR2X2TS U6444 ( .A(n4785), .B(n4784), .Y(n4792) );
INVX2TS U6445 ( .A(n4736), .Y(n4738) );
NAND2X1TS U6446 ( .A(n4738), .B(n4737), .Y(n4740) );
INVX2TS U6447 ( .A(n7202), .Y(n4791) );
INVX2TS U6448 ( .A(n4741), .Y(n4743) );
CLKXOR2X2TS U6449 ( .A(n4745), .B(n4744), .Y(n5733) );
INVX2TS U6450 ( .A(n4761), .Y(n4752) );
XNOR2X2TS U6451 ( .A(n4759), .B(n3156), .Y(n4842) );
INVX2TS U6452 ( .A(n7208), .Y(n4841) );
INVX2TS U6453 ( .A(FPMULT_Sgf_operation_EVEN1_Q_left[8]), .Y(n4840) );
ADDFHX4TS U6454 ( .A(n4770), .B(n4769), .CI(n4768), .CO(n4808), .S(n4798) );
INVX2TS U6455 ( .A(n4771), .Y(n4773) );
ADDFHX4TS U6456 ( .A(n4778), .B(n4777), .CI(n4776), .CO(n4768), .S(n4796) );
NAND2X2TS U6457 ( .A(n5056), .B(n3155), .Y(n4802) );
XNOR2X1TS U6458 ( .A(n4785), .B(n4784), .Y(n4786) );
INVX2TS U6459 ( .A(n5133), .Y(n4787) );
NAND2X1TS U6460 ( .A(n4783), .B(n4786), .Y(n5131) );
XNOR2X1TS U6461 ( .A(n4789), .B(n4788), .Y(n4794) );
CMPR32X2TS U6462 ( .A(n4792), .B(n4791), .C(n4790), .CO(n4776), .S(n4793) );
NAND2X1TS U6463 ( .A(n4794), .B(n4793), .Y(n5139) );
INVX2TS U6464 ( .A(n5139), .Y(n4795) );
NAND2X2TS U6465 ( .A(n4797), .B(n4796), .Y(n5143) );
INVX2TS U6466 ( .A(n5055), .Y(n4800) );
AOI21X4TS U6467 ( .A0(n5056), .A1(n5054), .B0(n4800), .Y(n4801) );
OAI21X4TS U6468 ( .A0(n4802), .A1(n5053), .B0(n4801), .Y(n5006) );
ADDFHX4TS U6469 ( .A(n4810), .B(n4809), .CI(n4808), .CO(n4818), .S(n4812) );
INVX2TS U6470 ( .A(n5005), .Y(n4814) );
AOI21X4TS U6471 ( .A0(n5006), .A1(n4811), .B0(n4814), .Y(n5063) );
INVX2TS U6472 ( .A(n4827), .Y(n4815) );
NAND2X1TS U6473 ( .A(n4815), .B(n4826), .Y(n4817) );
INVX2TS U6474 ( .A(n4816), .Y(n4828) );
NAND2X2TS U6475 ( .A(n4822), .B(n4821), .Y(n5061) );
OAI21X4TS U6476 ( .A0(n5063), .A1(n5060), .B0(n5061), .Y(n5091) );
ADDFHX4TS U6477 ( .A(n4825), .B(n4824), .CI(n4823), .CO(n4838), .S(n4835) );
INVX2TS U6478 ( .A(n4829), .Y(n4831) );
NAND2X1TS U6479 ( .A(n4831), .B(n4830), .Y(n4832) );
OR2X4TS U6480 ( .A(n4835), .B(n4834), .Y(n5089) );
NAND2X2TS U6481 ( .A(n4835), .B(n4834), .Y(n5088) );
INVX2TS U6482 ( .A(n5088), .Y(n4836) );
XNOR2X2TS U6483 ( .A(n4849), .B(n4848), .Y(n4883) );
INVX4TS U6484 ( .A(n7212), .Y(n4871) );
INVX2TS U6485 ( .A(n4857), .Y(n4859) );
ADDFHX4TS U6486 ( .A(n4867), .B(n4866), .CI(n4865), .CO(n4868), .S(n4846) );
ADDFHX4TS U6487 ( .A(n4872), .B(n4871), .CI(n4870), .CO(n4891), .S(n4882) );
XOR2X4TS U6488 ( .A(n4877), .B(n4876), .Y(n4890) );
INVX2TS U6489 ( .A(n4901), .Y(n4903) );
ADDFHX4TS U6490 ( .A(n4908), .B(n4907), .CI(n4906), .CO(n4945), .S(n4133) );
INVX2TS U6491 ( .A(n4915), .Y(n5189) );
INVX2TS U6492 ( .A(n4916), .Y(n4917) );
OAI22X2TS U6493 ( .A0(n5169), .A1(n5416), .B0(n2231), .B1(n4918), .Y(n5166)
);
ADDFHX4TS U6494 ( .A(n4932), .B(n4931), .CI(n4930), .CO(n5604), .S(n5549) );
INVX2TS U6495 ( .A(n4938), .Y(n4939) );
XNOR2X4TS U6496 ( .A(n5211), .B(n4940), .Y(n5175) );
INVX2TS U6497 ( .A(n5605), .Y(n5183) );
ADDFHX4TS U6498 ( .A(n4944), .B(n4943), .CI(n4942), .CO(n5162), .S(n4907) );
XOR2X1TS U6499 ( .A(n4948), .B(n5273), .Y(n5302) );
OAI22X1TS U6500 ( .A0(n5031), .A1(n5029), .B0(n4954), .B1(n5070), .Y(n5038)
);
ADDFHX4TS U6501 ( .A(n4960), .B(n4959), .CI(n4958), .CO(n5024), .S(n4977) );
INVX2TS U6502 ( .A(n5476), .Y(n5028) );
INVX2TS U6503 ( .A(n4971), .Y(n5035) );
NOR2X2TS U6504 ( .A(n4973), .B(n4972), .Y(n5475) );
INVX2TS U6505 ( .A(n5475), .Y(n5034) );
INVX4TS U6506 ( .A(n4974), .Y(n5033) );
ADDFHX4TS U6507 ( .A(n4980), .B(n4979), .CI(n4978), .CO(n4982), .S(n4563) );
NAND2X4TS U6508 ( .A(n4982), .B(n4981), .Y(n5015) );
INVX2TS U6509 ( .A(n5047), .Y(n4986) );
NAND2X1TS U6510 ( .A(n4986), .B(n5046), .Y(n4990) );
INVX2TS U6511 ( .A(n4987), .Y(n4988) );
CLKXOR2X2TS U6512 ( .A(n4990), .B(n5048), .Y(n4991) );
XOR2X4TS U6513 ( .A(n4995), .B(n4994), .Y(n5059) );
INVX4TS U6514 ( .A(n5059), .Y(n5301) );
INVX4TS U6515 ( .A(n5672), .Y(n5000) );
NAND2X4TS U6516 ( .A(n5000), .B(n5670), .Y(n5001) );
XOR2X4TS U6517 ( .A(n5671), .B(n5001), .Y(n5003) );
NAND2X4TS U6518 ( .A(n5003), .B(n5002), .Y(add_x_69_n202) );
NAND2X4TS U6519 ( .A(n5004), .B(add_x_69_n202), .Y(add_x_69_n16) );
NAND2X1TS U6520 ( .A(n4811), .B(n5005), .Y(n5007) );
NOR2X4TS U6521 ( .A(n5008), .B(n5011), .Y(n5014) );
OAI21X4TS U6522 ( .A0(n5011), .A1(n5010), .B0(n5009), .Y(n5012) );
OAI2BB1X4TS U6523 ( .A0N(n2228), .A1N(n5066), .B0(n5016), .Y(n5042) );
ADDFHX4TS U6524 ( .A(n5019), .B(n5018), .CI(n5017), .CO(n5040), .S(n4981) );
ADDFHX4TS U6525 ( .A(n5025), .B(n5024), .CI(n5023), .CO(n5068), .S(n5018) );
ADDFX2TS U6526 ( .A(n5035), .B(n5034), .CI(n5033), .CO(n5072), .S(n5026) );
NAND2X4TS U6527 ( .A(n5040), .B(n5039), .Y(n5100) );
NAND2X4TS U6528 ( .A(n5065), .B(n5100), .Y(n5041) );
NOR2X2TS U6529 ( .A(n5043), .B(n5044), .Y(n5111) );
INVX2TS U6530 ( .A(n5111), .Y(n5045) );
NAND2X1TS U6531 ( .A(n5045), .B(n5113), .Y(n5049) );
OAI21X2TS U6532 ( .A0(n5048), .A1(n5047), .B0(n5046), .Y(n5116) );
INVX2TS U6533 ( .A(n5116), .Y(n5082) );
CLKXOR2X2TS U6534 ( .A(n5049), .B(n5082), .Y(n5050) );
INVX2TS U6535 ( .A(n5053), .Y(n5144) );
AOI21X1TS U6536 ( .A0(n5144), .A1(n3155), .B0(n5054), .Y(n5058) );
NAND2X1TS U6537 ( .A(n5056), .B(n5055), .Y(n5057) );
CLKXOR2X2TS U6538 ( .A(n5058), .B(n5057), .Y(n5150) );
INVX2TS U6539 ( .A(n5060), .Y(n5062) );
CLKXOR2X2TS U6540 ( .A(n5064), .B(n5063), .Y(n5126) );
INVX2TS U6541 ( .A(n5099), .Y(n5080) );
NOR2X2TS U6542 ( .A(n5084), .B(n5083), .Y(n5114) );
INVX2TS U6543 ( .A(n5114), .Y(n5085) );
NAND2X1TS U6544 ( .A(n5085), .B(n5112), .Y(n5086) );
XNOR2X2TS U6545 ( .A(n5091), .B(n5090), .Y(n5128) );
INVX4TS U6546 ( .A(n2264), .Y(n5096) );
OAI21X4TS U6547 ( .A0(n5096), .A1(n2823), .B0(n5095), .Y(n5125) );
NAND2X4TS U6548 ( .A(n2228), .B(n5102), .Y(n5106) );
AOI21X4TS U6549 ( .A0(n5103), .A1(n5102), .B0(n5101), .Y(n5104) );
OAI21X1TS U6550 ( .A0(n5114), .A1(n5113), .B0(n5112), .Y(n5115) );
AOI21X4TS U6551 ( .A0(n5117), .A1(n5116), .B0(n5115), .Y(n5510) );
NOR2X2TS U6552 ( .A(n5118), .B(n2269), .Y(n5385) );
INVX2TS U6553 ( .A(n5385), .Y(n5120) );
NAND2X2TS U6554 ( .A(n5364), .B(n5495), .Y(n5124) );
INVX2TS U6555 ( .A(n5130), .Y(n5132) );
NAND2X1TS U6556 ( .A(n5132), .B(n5131), .Y(n5134) );
XNOR2X1TS U6557 ( .A(n5134), .B(n5133), .Y(n5138) );
NOR2X2TS U6558 ( .A(n5138), .B(n5137), .Y(n7218) );
CMPR32X2TS U6559 ( .A(n3233), .B(n4194), .C(n5135), .CO(n5133), .S(n7214) );
NAND2X1TS U6560 ( .A(n3176), .B(n5139), .Y(n5140) );
NOR2X2TS U6561 ( .A(n5146), .B(n5142), .Y(n7229) );
NAND2X1TS U6562 ( .A(n3155), .B(n5143), .Y(n5145) );
NAND2X2TS U6563 ( .A(n5146), .B(n5142), .Y(n7228) );
AOI21X4TS U6564 ( .A0(n7224), .A1(n5148), .B0(n5147), .Y(n6210) );
NOR2X2TS U6565 ( .A(n5150), .B(n5149), .Y(n7237) );
NOR2X2TS U6566 ( .A(n5156), .B(n5157), .Y(n5399) );
INVX2TS U6567 ( .A(n5399), .Y(n5158) );
NAND2X1TS U6568 ( .A(n5158), .B(n5397), .Y(n5159) );
XNOR2X2TS U6569 ( .A(n5160), .B(n5159), .Y(n5395) );
OAI22X1TS U6570 ( .A0(n5221), .A1(n5416), .B0(n5169), .B1(n2231), .Y(n5225)
);
INVX2TS U6571 ( .A(n2285), .Y(n5174) );
OAI22X4TS U6572 ( .A0(n5175), .A1(n5210), .B0(n5209), .B1(n5212), .Y(n5263)
);
INVX2TS U6573 ( .A(n5263), .Y(n5201) );
INVX2TS U6574 ( .A(n5179), .Y(n5180) );
INVX2TS U6575 ( .A(n5634), .Y(n5220) );
INVX2TS U6576 ( .A(n5662), .Y(n5246) );
INVX2TS U6577 ( .A(n5633), .Y(n5245) );
INVX2TS U6578 ( .A(n5204), .Y(n5256) );
INVX2TS U6579 ( .A(n5205), .Y(n5206) );
NOR2X2TS U6580 ( .A(n5206), .B(n2354), .Y(n5260) );
OAI22X1TS U6581 ( .A0(n5261), .A1(n5416), .B0(n5221), .B1(n2231), .Y(n5250)
);
ADDFHX2TS U6582 ( .A(n5227), .B(n5226), .CI(n5225), .CO(n5248), .S(n5230) );
ADDFHX4TS U6583 ( .A(n5233), .B(n5232), .CI(n5231), .CO(n5237), .S(n5235) );
ADDFX2TS U6584 ( .A(n5244), .B(n5243), .CI(n5242), .CO(n5333), .S(n5269) );
OAI22X2TS U6585 ( .A0(n5251), .A1(n5338), .B0(n2376), .B1(n2511), .Y(n5349)
);
INVX2TS U6586 ( .A(n5252), .Y(n5253) );
NOR2X2TS U6587 ( .A(n5253), .B(n2354), .Y(n5348) );
INVX2TS U6588 ( .A(n5254), .Y(n5347) );
ADDFHX2TS U6589 ( .A(n5260), .B(n5259), .CI(n5258), .CO(n5344), .S(n5255) );
INVX2TS U6590 ( .A(n5266), .Y(n5339) );
ADDFHX4TS U6591 ( .A(n5269), .B(n5268), .CI(n5267), .CO(n5270), .S(n5236) );
OAI21X2TS U6592 ( .A0(n5274), .A1(n5273), .B0(n5272), .Y(n5298) );
INVX2TS U6593 ( .A(n5296), .Y(n5277) );
AOI21X2TS U6594 ( .A0(n5298), .A1(n5297), .B0(n5277), .Y(n5289) );
INVX2TS U6595 ( .A(n5288), .Y(n5280) );
XOR2X1TS U6596 ( .A(n5289), .B(n5281), .Y(n5305) );
AOI21X4TS U6597 ( .A0(n3135), .A1(n5282), .B0(n2742), .Y(n5286) );
INVX2TS U6598 ( .A(n5378), .Y(n5358) );
NOR2X2TS U6599 ( .A(n5291), .B(n5290), .Y(n5373) );
INVX2TS U6600 ( .A(n5373), .Y(n5292) );
NAND2X1TS U6601 ( .A(n5292), .B(n5375), .Y(n5293) );
XOR2X1TS U6602 ( .A(n5358), .B(n5293), .Y(n5357) );
XOR2X4TS U6603 ( .A(n5295), .B(n5294), .Y(n5308) );
NAND2X1TS U6604 ( .A(n5297), .B(n5296), .Y(n5299) );
XNOR2X1TS U6605 ( .A(n5299), .B(n5298), .Y(n5446) );
ADDFHX4TS U6606 ( .A(n5302), .B(n5301), .CI(n5300), .CO(n5445), .S(n5324) );
ADDFHX4TS U6607 ( .A(n5308), .B(n5307), .CI(n5306), .CO(n5326), .S(n5441) );
INVX2TS U6608 ( .A(n5312), .Y(n5314) );
XOR2X4TS U6609 ( .A(n5316), .B(n5315), .Y(n5721) );
INVX2TS U6610 ( .A(n5319), .Y(n5321) );
NAND2X4TS U6611 ( .A(n5321), .B(n5320), .Y(n5322) );
ADDFHX4TS U6612 ( .A(n5334), .B(n5333), .CI(n5332), .CO(n5354), .S(n5271) );
ADDFHX2TS U6613 ( .A(n5337), .B(n5336), .CI(n5335), .CO(n5412), .S(n5350) );
INVX2TS U6614 ( .A(n5340), .Y(n5341) );
ADDFHX2TS U6615 ( .A(n5344), .B(n5343), .CI(n5342), .CO(n5425), .S(n5335) );
ADDFHX2TS U6616 ( .A(n5352), .B(n5351), .CI(n5350), .CO(n5410), .S(n5332) );
ADDFHX4TS U6617 ( .A(n5357), .B(add_x_69_n69), .CI(n5356), .CO(n5433), .S(
n5370) );
INVX2TS U6618 ( .A(n5376), .Y(n5361) );
XNOR2X1TS U6619 ( .A(n5363), .B(n5362), .Y(n5408) );
NOR2X2TS U6620 ( .A(n5365), .B(n5366), .Y(n5388) );
INVX2TS U6621 ( .A(n5388), .Y(n5367) );
ADDFHX4TS U6622 ( .A(n5372), .B(n5371), .CI(n5370), .CO(n5436), .S(n5325) );
OAI21X1TS U6623 ( .A0(n5376), .A1(n5375), .B0(n5374), .Y(n5377) );
AOI21X4TS U6624 ( .A0(n5379), .A1(n5378), .B0(n5377), .Y(n5660) );
NOR2X2TS U6625 ( .A(n5380), .B(n5381), .Y(n5598) );
INVX2TS U6626 ( .A(n5598), .Y(n5382) );
XOR2X1TS U6627 ( .A(n5660), .B(n5383), .Y(n5562) );
NOR2X2TS U6628 ( .A(n5385), .B(n5388), .Y(n5501) );
INVX2TS U6629 ( .A(n5501), .Y(n5390) );
OAI21X2TS U6630 ( .A0(n5388), .A1(n5387), .B0(n5386), .Y(n5507) );
INVX2TS U6631 ( .A(n5507), .Y(n5389) );
OAI21X1TS U6632 ( .A0(n5510), .A1(n5390), .B0(n5389), .Y(n5394) );
NOR2X1TS U6633 ( .A(n5392), .B(n5391), .Y(n5500) );
INVX2TS U6634 ( .A(n5500), .Y(n5472) );
NAND2X1TS U6635 ( .A(n5392), .B(n5391), .Y(n5504) );
NAND2X1TS U6636 ( .A(n5472), .B(n5504), .Y(n5393) );
XNOR2X2TS U6637 ( .A(n5394), .B(n5393), .Y(n5465) );
INVX2TS U6638 ( .A(n5554), .Y(n5401) );
OAI21X2TS U6639 ( .A0(n5399), .A1(n5398), .B0(n5397), .Y(n5615) );
INVX2TS U6640 ( .A(n5615), .Y(n5400) );
OAI21X1TS U6641 ( .A0(n5618), .A1(n5401), .B0(n5400), .Y(n5405) );
NAND2X1TS U6642 ( .A(n5403), .B(n5402), .Y(n5612) );
NAND2X1TS U6643 ( .A(n5614), .B(n5612), .Y(n5404) );
ADDFHX4TS U6644 ( .A(n5408), .B(add_x_69_n59), .CI(n5407), .CO(n5589), .S(
n5432) );
OAI22X1TS U6645 ( .A0(n5417), .A1(n2231), .B0(n5416), .B1(n2354), .Y(n5579)
);
INVX2TS U6646 ( .A(n5418), .Y(n5576) );
NOR2X2TS U6647 ( .A(n5420), .B(n2354), .Y(n5574) );
CMPR32X2TS U6648 ( .A(n5423), .B(n5422), .C(n5421), .CO(n5577), .S(n5426) );
INVX2TS U6649 ( .A(n5565), .Y(n5429) );
XNOR2X4TS U6650 ( .A(n5431), .B(n5430), .Y(n5588) );
ADDFHX4TS U6651 ( .A(n5434), .B(n5433), .CI(n5432), .CO(n5438), .S(n5435) );
NAND2X4TS U6652 ( .A(n5438), .B(n5437), .Y(n5681) );
OAI21X4TS U6653 ( .A0(n5680), .A1(n5690), .B0(n5681), .Y(n5439) );
AOI21X4TS U6654 ( .A0(n5696), .A1(n5442), .B0(n5439), .Y(n5451) );
NOR2X2TS U6655 ( .A(FPMULT_FS_Module_state_reg[0]), .B(
FPMULT_FS_Module_state_reg[2]), .Y(n6651) );
NAND2X1TS U6656 ( .A(n2350), .B(n6358), .Y(n5453) );
NOR3X2TS U6657 ( .A(n7788), .B(FPMULT_FS_Module_state_reg[3]), .C(
FPMULT_FS_Module_state_reg[0]), .Y(n6614) );
INVX2TS U6658 ( .A(n5456), .Y(n5458) );
NAND2X2TS U6659 ( .A(n5458), .B(n5457), .Y(n5459) );
CLKXOR2X2TS U6660 ( .A(n5455), .B(n5459), .Y(n5482) );
NOR2X8TS U6661 ( .A(n5484), .B(n5483), .Y(n5518) );
NOR2X4TS U6662 ( .A(n5464), .B(n5494), .Y(n5468) );
NAND2X2TS U6663 ( .A(n2264), .B(n5468), .Y(n5470) );
AOI21X4TS U6664 ( .A0(n2667), .A1(n5468), .B0(n5467), .Y(n5469) );
OAI21X4TS U6665 ( .A0(n2829), .A1(n5470), .B0(n5469), .Y(n5480) );
NAND2X1TS U6666 ( .A(n5501), .B(n5472), .Y(n5474) );
INVX2TS U6667 ( .A(n5504), .Y(n5471) );
AOI21X1TS U6668 ( .A0(n5507), .A1(n5472), .B0(n5471), .Y(n5473) );
OAI21X1TS U6669 ( .A0(n5510), .A1(n5474), .B0(n5473), .Y(n5479) );
NOR2X2TS U6670 ( .A(n5476), .B(n5475), .Y(n5503) );
INVX2TS U6671 ( .A(n5503), .Y(n5477) );
NAND2X1TS U6672 ( .A(n5476), .B(n5475), .Y(n5502) );
NAND2X1TS U6673 ( .A(n5477), .B(n5502), .Y(n5478) );
XNOR2X4TS U6674 ( .A(n5480), .B(n3152), .Y(n5561) );
INVX4TS U6675 ( .A(n5531), .Y(n5526) );
NAND2X4TS U6676 ( .A(n5484), .B(n5483), .Y(n5519) );
NAND2X4TS U6677 ( .A(n5487), .B(n5486), .Y(n5534) );
INVX2TS U6678 ( .A(n5534), .Y(n5488) );
OAI21X4TS U6679 ( .A0(n6252), .A1(n5490), .B0(n5489), .Y(n5515) );
NAND2X2TS U6680 ( .A(n3190), .B(n5491), .Y(n5492) );
XNOR2X4TS U6681 ( .A(n5493), .B(n5492), .Y(n5512) );
NAND2X2TS U6682 ( .A(n2264), .B(n5497), .Y(n5499) );
NOR2X2TS U6683 ( .A(n5495), .B(n3153), .Y(n5496) );
AOI21X4TS U6684 ( .A0(n2667), .A1(n5497), .B0(n5496), .Y(n5498) );
OAI21X4TS U6685 ( .A0(n2829), .A1(n5499), .B0(n5498), .Y(n5511) );
NOR2X1TS U6686 ( .A(n5500), .B(n5503), .Y(n5506) );
NAND2X1TS U6687 ( .A(n5501), .B(n5506), .Y(n5509) );
AOI21X1TS U6688 ( .A0(n5507), .A1(n5506), .B0(n5505), .Y(n5508) );
XNOR2X4TS U6689 ( .A(n5511), .B(n3151), .Y(n5608) );
INVX2TS U6690 ( .A(n5535), .Y(n5513) );
NAND2X2TS U6691 ( .A(n5512), .B(n5608), .Y(n5533) );
XOR2X4TS U6692 ( .A(n5515), .B(n5514), .Y(n5517) );
OAI21X4TS U6693 ( .A0(n5517), .A1(n7253), .B0(n5516), .Y(n1576) );
OAI21X4TS U6694 ( .A0(n6252), .A1(n6248), .B0(n6249), .Y(n5522) );
INVX2TS U6695 ( .A(n5518), .Y(n5520) );
XOR2X4TS U6696 ( .A(n5522), .B(n5521), .Y(n5524) );
OAI21X4TS U6697 ( .A0(n5524), .A1(n6955), .B0(n5523), .Y(n1574) );
INVX2TS U6698 ( .A(n5532), .Y(n5525) );
OAI21X4TS U6699 ( .A0(n6252), .A1(n5525), .B0(n5485), .Y(n5528) );
XOR2X4TS U6700 ( .A(n5528), .B(n5527), .Y(n5530) );
OAI21X4TS U6701 ( .A0(n5530), .A1(n6955), .B0(n5529), .Y(n1575) );
NAND2X2TS U6702 ( .A(n5753), .B(n5751), .Y(n5542) );
XOR2X4TS U6703 ( .A(n5543), .B(n5542), .Y(n5545) );
OAI21X4TS U6704 ( .A0(n5545), .A1(n7253), .B0(n5544), .Y(n1577) );
OAI21X1TS U6705 ( .A0(n5660), .A1(n5598), .B0(n5600), .Y(n5552) );
NOR2X2TS U6706 ( .A(n5549), .B(n5548), .Y(n5601) );
INVX2TS U6707 ( .A(n5601), .Y(n5550) );
XNOR2X1TS U6708 ( .A(n5552), .B(n5551), .Y(n5597) );
INVX2TS U6709 ( .A(n5612), .Y(n5555) );
AOI21X1TS U6710 ( .A0(n5615), .A1(n5614), .B0(n5555), .Y(n5556) );
XNOR2X1TS U6711 ( .A(n5558), .B(n5557), .Y(n5609) );
INVX2TS U6712 ( .A(n5609), .Y(n5559) );
XOR2X4TS U6713 ( .A(n5560), .B(n5559), .Y(n5714) );
ADDFHX4TS U6714 ( .A(n5562), .B(n2286), .CI(n5712), .CO(n5623), .S(n5590) );
XOR2X4TS U6715 ( .A(n5620), .B(n5623), .Y(n5587) );
INVX2TS U6716 ( .A(n5570), .Y(n5571) );
XNOR2X1TS U6717 ( .A(n5573), .B(n5572), .Y(n5582) );
CMPR32X2TS U6718 ( .A(n5576), .B(n5575), .C(n5574), .CO(n5581), .S(n5578) );
XOR2X4TS U6719 ( .A(n5586), .B(n5585), .Y(n5622) );
XOR2X4TS U6720 ( .A(n5587), .B(n5622), .Y(n5643) );
ADDFHX4TS U6721 ( .A(n5589), .B(n5590), .CI(n5588), .CO(n5644), .S(n5437) );
ADDFHX4TS U6722 ( .A(n5597), .B(n5596), .CI(n5595), .CO(n5627), .S(n5620) );
NOR2X2TS U6723 ( .A(n5598), .B(n5601), .Y(n5651) );
INVX2TS U6724 ( .A(n5651), .Y(n5603) );
OAI21X2TS U6725 ( .A0(n5601), .A1(n5600), .B0(n5599), .Y(n5657) );
INVX2TS U6726 ( .A(n5657), .Y(n5602) );
OAI21X1TS U6727 ( .A0(n5660), .A1(n5603), .B0(n5602), .Y(n5607) );
INVX2TS U6728 ( .A(n5650), .Y(n5630) );
NAND2X1TS U6729 ( .A(n5612), .B(n5611), .Y(n5613) );
AOI21X1TS U6730 ( .A0(n5615), .A1(n5614), .B0(n5613), .Y(n5616) );
OAI21X2TS U6731 ( .A0(n5622), .A1(n5623), .B0(n5620), .Y(n5621) );
OAI2BB1X4TS U6732 ( .A0N(n5623), .A1N(n5622), .B0(n5621), .Y(n5625) );
NAND2X4TS U6733 ( .A(n5625), .B(n5624), .Y(n5692) );
NAND2X1TS U6734 ( .A(n5651), .B(n5630), .Y(n5632) );
INVX2TS U6735 ( .A(n5653), .Y(n5629) );
AOI21X1TS U6736 ( .A0(n5657), .A1(n5630), .B0(n5629), .Y(n5631) );
NOR2X2TS U6737 ( .A(n5634), .B(n5633), .Y(n5654) );
INVX2TS U6738 ( .A(n5654), .Y(n5635) );
INVX4TS U6739 ( .A(n5646), .Y(n5700) );
ADDHX2TS U6740 ( .A(n5649), .B(n5648), .CO(n5667), .S(n5640) );
NOR2X1TS U6741 ( .A(n5650), .B(n5654), .Y(n5656) );
NAND2X1TS U6742 ( .A(n5651), .B(n5656), .Y(n5659) );
AOI21X1TS U6743 ( .A0(n5657), .A1(n5656), .B0(n5655), .Y(n5658) );
NAND2X1TS U6744 ( .A(n5662), .B(n5661), .Y(n5663) );
NAND2X1TS U6745 ( .A(n5664), .B(n5663), .Y(n5665) );
OAI21X4TS U6746 ( .A0(n5672), .A1(n5671), .B0(n5670), .Y(n5678) );
BUFX3TS U6747 ( .A(n5673), .Y(n5674) );
INVX4TS U6748 ( .A(n5674), .Y(n5676) );
NAND2X4TS U6749 ( .A(n5676), .B(n5675), .Y(n5677) );
XNOR2X4TS U6750 ( .A(n5678), .B(n5677), .Y(
FPMULT_Sgf_operation_EVEN1_S_B[17]) );
INVX4TS U6751 ( .A(n3069), .Y(n5682) );
NAND2X4TS U6752 ( .A(n5682), .B(n5681), .Y(n5683) );
XOR2X4TS U6753 ( .A(n5684), .B(n5683), .Y(FPMULT_Sgf_operation_EVEN1_S_B[21]) );
AOI21X4TS U6754 ( .A0(n2267), .A1(n2522), .B0(n5685), .Y(n5688) );
XOR2X4TS U6755 ( .A(n5688), .B(n5687), .Y(FPMULT_Sgf_operation_EVEN1_S_B[19]) );
NAND2X4TS U6756 ( .A(n5693), .B(n5692), .Y(DP_OP_499J2_125_1651_n5) );
INVX2TS U6757 ( .A(n1659), .Y(n7690) );
INVX2TS U6758 ( .A(n1665), .Y(n7689) );
CLKMX2X2TS U6759 ( .A(Data_1[7]), .B(DP_OP_496J2_122_3540_n1513), .S0(n2357),
.Y(n1666) );
CLKMX2X2TS U6760 ( .A(Data_1[1]), .B(n8488), .S0(n2355), .Y(n1660) );
NOR2X1TS U6761 ( .A(n1666), .B(n1660), .Y(n5703) );
NAND2X1TS U6762 ( .A(n1666), .B(n1660), .Y(n5704) );
INVX2TS U6763 ( .A(n1631), .Y(n7696) );
INVX2TS U6764 ( .A(n1637), .Y(n7687) );
INVX2TS U6765 ( .A(Data_2[3]), .Y(n5701) );
INVX2TS U6766 ( .A(n5702), .Y(n1630) );
INVX2TS U6767 ( .A(n5703), .Y(n5705) );
NAND2X1TS U6768 ( .A(n5705), .B(n5704), .Y(n7697) );
ADDHXLTS U6769 ( .A(n1678), .B(n1646), .CO(n7702), .S(n7703) );
INVX2TS U6770 ( .A(n1671), .Y(n7704) );
INVX2TS U6771 ( .A(n1676), .Y(n7707) );
NAND2X1TS U6772 ( .A(n1645), .B(n1639), .Y(n7705) );
NAND2X1TS U6773 ( .A(n1642), .B(n1630), .Y(n7722) );
NAND2X1TS U6774 ( .A(n1639), .B(n1627), .Y(n7713) );
NOR2X1TS U6775 ( .A(DP_OP_497J2_123_1725_n779), .B(n1628), .Y(n5709) );
NAND2X1TS U6776 ( .A(DP_OP_497J2_123_1725_n779), .B(n1628), .Y(n5710) );
INVX2TS U6777 ( .A(n1677), .Y(n7710) );
CLKBUFX3TS U6778 ( .A(n2367), .Y(n7993) );
CLKBUFX3TS U6779 ( .A(n8598), .Y(n7726) );
INVX2TS U6780 ( .A(n5709), .Y(n5711) );
NAND2X1TS U6781 ( .A(n5711), .B(n5710), .Y(n7720) );
NAND2X1TS U6782 ( .A(n1672), .B(n1660), .Y(n7725) );
NAND2X1TS U6783 ( .A(n1673), .B(n1661), .Y(n7724) );
NAND2X1TS U6784 ( .A(n1643), .B(n1631), .Y(n7711) );
NAND2X1TS U6785 ( .A(n1674), .B(n1662), .Y(n7723) );
NAND2X1TS U6786 ( .A(n1641), .B(n1629), .Y(n7712) );
INVX2TS U6787 ( .A(rst), .Y(n8635) );
CLKINVX1TS U6788 ( .A(n5712), .Y(n5713) );
INVX2TS U6789 ( .A(n5713), .Y(add_x_69_n51) );
INVX2TS U6790 ( .A(n5724), .Y(add_x_69_n47) );
NAND2X1TS U6791 ( .A(n5720), .B(n5721), .Y(n5722) );
BUFX3TS U6792 ( .A(n8593), .Y(n7779) );
CLKBUFX3TS U6793 ( .A(n2426), .Y(n7777) );
CLKBUFX3TS U6794 ( .A(n8562), .Y(n7778) );
NOR2X8TS U6795 ( .A(n5730), .B(n5757), .Y(n5739) );
OAI21X4TS U6796 ( .A0(n6252), .A1(n5745), .B0(n5744), .Y(n5749) );
XNOR2X4TS U6797 ( .A(n5749), .B(n5748), .Y(FPMULT_Sgf_operation_Result[26])
);
NAND2X2TS U6798 ( .A(n5750), .B(n5753), .Y(n5756) );
INVX2TS U6799 ( .A(n5751), .Y(n5752) );
INVX2TS U6800 ( .A(n5757), .Y(n5758) );
AOI22X1TS U6801 ( .A0(n8074), .A1(n8185), .B0(n5998), .B1(n8184), .Y(n5764)
);
BUFX3TS U6802 ( .A(n2256), .Y(n6005) );
NAND2X1TS U6803 ( .A(n6263), .B(n6620), .Y(n5766) );
BUFX3TS U6804 ( .A(n6449), .Y(n6335) );
OAI2BB1X1TS U6805 ( .A0N(n2198), .A1N(n5770), .B0(n8426), .Y(n6880) );
BUFX3TS U6806 ( .A(n5774), .Y(n6540) );
INVX2TS U6807 ( .A(n6507), .Y(n6440) );
AOI22X1TS U6808 ( .A0(n2380), .A1(FPMULT_Add_result[5]), .B0(
FPMULT_Sgf_normalized_result[4]), .B1(n6440), .Y(n5771) );
OAI2BB1X1TS U6809 ( .A0N(n2445), .A1N(n6880), .B0(n5771), .Y(n5772) );
AOI21X1TS U6810 ( .A0(n2411), .A1(FPMULT_Add_result[4]), .B0(n5772), .Y(
n5773) );
OAI2BB1X1TS U6811 ( .A0N(n2416), .A1N(n1580), .B0(n5773), .Y(n1521) );
AOI22X1TS U6812 ( .A0(n6540), .A1(FPMULT_Add_result[4]), .B0(
FPMULT_Sgf_normalized_result[3]), .B1(n6539), .Y(n5775) );
OAI2BB1X1TS U6813 ( .A0N(n2444), .A1N(n1580), .B0(n5775), .Y(n5776) );
AOI21X1TS U6814 ( .A0(n2410), .A1(FPMULT_Add_result[3]), .B0(n5776), .Y(
n5777) );
OAI2BB1X1TS U6815 ( .A0N(n2415), .A1N(n1579), .B0(n5777), .Y(add_x_246_A_3_)
);
AOI22X1TS U6816 ( .A0(n2380), .A1(FPMULT_Add_result[3]), .B0(
FPMULT_Sgf_normalized_result[2]), .B1(n6907), .Y(n5778) );
OAI2BB1X1TS U6817 ( .A0N(n2446), .A1N(n1579), .B0(n5778), .Y(n5779) );
AOI21X1TS U6818 ( .A0(n2410), .A1(FPMULT_Add_result[2]), .B0(n5779), .Y(
n5780) );
OAI2BB1X1TS U6819 ( .A0N(n2415), .A1N(n1578), .B0(n5780), .Y(n1519) );
AOI22X1TS U6820 ( .A0(n5774), .A1(FPMULT_Add_result[2]), .B0(
FPMULT_Sgf_normalized_result[1]), .B1(n6440), .Y(n5781) );
OAI2BB1X1TS U6821 ( .A0N(n2445), .A1N(n1578), .B0(n5781), .Y(n5782) );
AOI21X1TS U6822 ( .A0(n2410), .A1(FPMULT_Add_result[1]), .B0(n5782), .Y(
n5783) );
OAI2BB1X1TS U6823 ( .A0N(n2415), .A1N(FPMULT_P_Sgf[24]), .B0(n5783), .Y(
n1518) );
AOI22X1TS U6824 ( .A0(n2380), .A1(FPMULT_Add_result[1]), .B0(
FPMULT_Sgf_normalized_result[0]), .B1(n6539), .Y(n5784) );
OAI2BB1X1TS U6825 ( .A0N(n2444), .A1N(FPMULT_P_Sgf[24]), .B0(n5784), .Y(
n5785) );
AOI21X1TS U6826 ( .A0(n2410), .A1(FPMULT_Add_result[0]), .B0(n5785), .Y(
n5786) );
OAI2BB1X1TS U6827 ( .A0N(FPMULT_P_Sgf[23]), .A1N(n2415), .B0(n5786), .Y(
n1517) );
XNOR2X1TS U6828 ( .A(n1521), .B(n5795), .Y(n7785) );
NAND2X1TS U6829 ( .A(n7750), .B(n7751), .Y(n6192) );
NAND2X1TS U6830 ( .A(n7757), .B(n6192), .Y(n5788) );
XNOR2X1TS U6831 ( .A(n5789), .B(n5788), .Y(n5790) );
NAND2X1TS U6832 ( .A(n5790), .B(n8413), .Y(n5791) );
OAI2BB1X1TS U6833 ( .A0N(n8057), .A1N(n8416), .B0(n5791), .Y(n1582) );
INVX2TS U6834 ( .A(n6507), .Y(n6539) );
AOI22X1TS U6835 ( .A0(n6540), .A1(FPMULT_Add_result[6]), .B0(
FPMULT_Sgf_normalized_result[5]), .B1(n6907), .Y(n5792) );
OAI2BB1X1TS U6836 ( .A0N(n2446), .A1N(n1582), .B0(n5792), .Y(n5793) );
AOI21X1TS U6837 ( .A0(n6544), .A1(FPMULT_Add_result[5]), .B0(n5793), .Y(
n5794) );
OAI2BB1X1TS U6838 ( .A0N(n5768), .A1N(n6880), .B0(n5794), .Y(add_x_246_A_5_)
);
NOR4X1TS U6839 ( .A(FPMULT_P_Sgf[17]), .B(FPMULT_P_Sgf[16]), .C(
FPMULT_P_Sgf[15]), .D(FPMULT_P_Sgf[14]), .Y(n5806) );
NOR4X1TS U6840 ( .A(FPMULT_P_Sgf[20]), .B(FPMULT_P_Sgf[21]), .C(
FPMULT_P_Sgf[18]), .D(FPMULT_P_Sgf[19]), .Y(n5805) );
NOR4X1TS U6841 ( .A(FPMULT_P_Sgf[2]), .B(FPMULT_P_Sgf[3]), .C(
FPMULT_P_Sgf[4]), .D(FPMULT_P_Sgf[5]), .Y(n5801) );
NOR3XLTS U6842 ( .A(FPMULT_P_Sgf[22]), .B(FPMULT_P_Sgf[1]), .C(
FPMULT_P_Sgf[0]), .Y(n5800) );
AND4X1TS U6843 ( .A(n5801), .B(n5800), .C(n5799), .D(n5798), .Y(n5804) );
XOR2X1TS U6844 ( .A(FPMULT_Op_MX[31]), .B(FPMULT_Op_MY[31]), .Y(n7491) );
MXI2X1TS U6845 ( .A(r_mode[0]), .B(r_mode[1]), .S0(n7491), .Y(n5802) );
AOI31X1TS U6846 ( .A0(n5806), .A1(n5805), .A2(n5804), .B0(n5803), .Y(n6261)
);
OAI221XLTS U6847 ( .A0(n2350), .A1(FPMULT_FS_Module_state_reg[0]), .B0(n3146), .B1(n7794), .C0(n7788), .Y(n5808) );
NAND2X1TS U6848 ( .A(n3146), .B(n5807), .Y(n6649) );
NOR4X1TS U6849 ( .A(Data_2[15]), .B(Data_2[19]), .C(Data_2[13]), .D(
Data_2[21]), .Y(n5811) );
NOR4X1TS U6850 ( .A(Data_2[4]), .B(Data_2[18]), .C(Data_2[20]), .D(Data_2[1]), .Y(n5810) );
NOR4X1TS U6851 ( .A(Data_2[3]), .B(Data_2[5]), .C(Data_2[22]), .D(Data_2[0]),
.Y(n5809) );
NOR4X1TS U6852 ( .A(Data_2[17]), .B(Data_2[16]), .C(Data_2[8]), .D(n5812),
.Y(n8061) );
AOI21X1TS U6853 ( .A0(operation[1]), .A1(ack_operation), .B0(n6718), .Y(
n7281) );
NAND2X1TS U6854 ( .A(n5814), .B(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]),
.Y(n5816) );
NOR2X2TS U6855 ( .A(n7790), .B(intadd_9_B_1_), .Y(n6632) );
BUFX3TS U6856 ( .A(n6424), .Y(n6599) );
NAND2X1TS U6857 ( .A(n7943), .B(n7805), .Y(n7167) );
NOR2X1TS U6858 ( .A(n7951), .B(FPADDSUB_DMP_SFG[0]), .Y(n5818) );
NAND2X1TS U6859 ( .A(n7951), .B(FPADDSUB_DMP_SFG[0]), .Y(n5817) );
OAI21X1TS U6860 ( .A0(n7167), .A1(n5818), .B0(n5817), .Y(n6375) );
NOR2X1TS U6861 ( .A(n7950), .B(FPADDSUB_DMP_SFG[1]), .Y(n6377) );
NOR2X1TS U6862 ( .A(n7949), .B(FPADDSUB_DMP_SFG[2]), .Y(n5820) );
NAND2X1TS U6863 ( .A(n7950), .B(FPADDSUB_DMP_SFG[1]), .Y(n6376) );
NAND2X1TS U6864 ( .A(n7949), .B(FPADDSUB_DMP_SFG[2]), .Y(n5819) );
AOI21X1TS U6865 ( .A0(n6375), .A1(n5822), .B0(n5821), .Y(n6359) );
NOR2X1TS U6866 ( .A(n7948), .B(FPADDSUB_DMP_SFG[3]), .Y(n6386) );
NOR2X1TS U6867 ( .A(n7947), .B(FPADDSUB_DMP_SFG[4]), .Y(n5824) );
NOR2X1TS U6868 ( .A(n6386), .B(n5824), .Y(n6361) );
NOR2X1TS U6869 ( .A(n7942), .B(FPADDSUB_DMP_SFG[5]), .Y(n6363) );
NOR2X1TS U6870 ( .A(n7946), .B(FPADDSUB_DMP_SFG[6]), .Y(n5826) );
NOR2X1TS U6871 ( .A(n6363), .B(n5826), .Y(n5828) );
NAND2X1TS U6872 ( .A(n6361), .B(n5828), .Y(n5830) );
NAND2X1TS U6873 ( .A(n7948), .B(FPADDSUB_DMP_SFG[3]), .Y(n6387) );
NAND2X1TS U6874 ( .A(n7947), .B(FPADDSUB_DMP_SFG[4]), .Y(n5823) );
OAI21X1TS U6875 ( .A0(n5824), .A1(n6387), .B0(n5823), .Y(n6360) );
NAND2X1TS U6876 ( .A(n7942), .B(FPADDSUB_DMP_SFG[5]), .Y(n6362) );
NAND2X1TS U6877 ( .A(n7946), .B(FPADDSUB_DMP_SFG[6]), .Y(n5825) );
AOI21X1TS U6878 ( .A0(n6360), .A1(n5828), .B0(n5827), .Y(n5829) );
OAI21X1TS U6879 ( .A0(n6359), .A1(n5830), .B0(n5829), .Y(n7125) );
NOR2X1TS U6880 ( .A(n7945), .B(FPADDSUB_DMP_SFG[7]), .Y(n7143) );
NOR2X1TS U6881 ( .A(n7944), .B(FPADDSUB_DMP_SFG[8]), .Y(n5832) );
NOR2X1TS U6882 ( .A(n7143), .B(n5832), .Y(n7126) );
NAND2X1TS U6883 ( .A(n7126), .B(n3194), .Y(n7172) );
NOR2X1TS U6884 ( .A(n7914), .B(n2466), .Y(n5835) );
NOR2X1TS U6885 ( .A(n7172), .B(n5835), .Y(n5837) );
NAND2X1TS U6886 ( .A(n7945), .B(FPADDSUB_DMP_SFG[7]), .Y(n7142) );
NAND2X1TS U6887 ( .A(n7944), .B(FPADDSUB_DMP_SFG[8]), .Y(n5831) );
OAI21X1TS U6888 ( .A0(n5832), .A1(n7142), .B0(n5831), .Y(n7127) );
AOI21X1TS U6889 ( .A0(n7127), .A1(n3194), .B0(n5833), .Y(n7171) );
NAND2X1TS U6890 ( .A(n7914), .B(FPADDSUB_DMP_SFG[10]), .Y(n5834) );
OAI21X1TS U6891 ( .A0(n7171), .A1(n5835), .B0(n5834), .Y(n5836) );
AOI21X2TS U6892 ( .A0(n7125), .A1(n5837), .B0(n5836), .Y(n7119) );
NOR2X1TS U6893 ( .A(n7866), .B(FPADDSUB_DMP_SFG[11]), .Y(n5839) );
NAND2X1TS U6894 ( .A(n7866), .B(FPADDSUB_DMP_SFG[11]), .Y(n5838) );
OAI21X4TS U6895 ( .A0(n7119), .A1(n5839), .B0(n5838), .Y(n7109) );
AOI21X4TS U6896 ( .A0(n7109), .A1(n5841), .B0(n5840), .Y(n6593) );
NAND2X1TS U6897 ( .A(n7865), .B(n2488), .Y(n5842) );
OAI21X4TS U6898 ( .A0(n6593), .A1(n5843), .B0(n5842), .Y(n5862) );
NAND2X1TS U6899 ( .A(n5867), .B(n5865), .Y(n5856) );
INVX2TS U6900 ( .A(n5856), .Y(n5844) );
XNOR2X1TS U6901 ( .A(n5862), .B(n5844), .Y(n5859) );
NOR2X1TS U6902 ( .A(FPADDSUB_DMP_SFG[1]), .B(FPADDSUB_DmP_mant_SFG_SWR[3]),
.Y(n7153) );
NAND2X1TS U6903 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DmP_mant_SFG_SWR[2]),
.Y(n7165) );
NAND2X1TS U6904 ( .A(FPADDSUB_DMP_SFG[1]), .B(FPADDSUB_DmP_mant_SFG_SWR[3]),
.Y(n7154) );
NOR2X2TS U6905 ( .A(FPADDSUB_DMP_SFG[2]), .B(FPADDSUB_DmP_mant_SFG_SWR[4]),
.Y(n6403) );
NOR2X2TS U6906 ( .A(FPADDSUB_DMP_SFG[3]), .B(FPADDSUB_DmP_mant_SFG_SWR[5]),
.Y(n6397) );
NAND2X1TS U6907 ( .A(FPADDSUB_DMP_SFG[2]), .B(FPADDSUB_DmP_mant_SFG_SWR[4]),
.Y(n6402) );
NAND2X1TS U6908 ( .A(FPADDSUB_DMP_SFG[3]), .B(FPADDSUB_DmP_mant_SFG_SWR[5]),
.Y(n6398) );
AOI21X1TS U6909 ( .A0(n6381), .A1(n5846), .B0(n5845), .Y(n6367) );
NOR2X1TS U6910 ( .A(FPADDSUB_DMP_SFG[4]), .B(FPADDSUB_DmP_mant_SFG_SWR[6]),
.Y(n6390) );
NOR2X2TS U6911 ( .A(FPADDSUB_DMP_SFG[5]), .B(FPADDSUB_DmP_mant_SFG_SWR[7]),
.Y(n6410) );
NOR2X1TS U6912 ( .A(n6390), .B(n6410), .Y(n6369) );
NOR2X2TS U6913 ( .A(FPADDSUB_DMP_SFG[6]), .B(FPADDSUB_DmP_mant_SFG_SWR[8]),
.Y(n7192) );
NOR2X2TS U6914 ( .A(FPADDSUB_DMP_SFG[7]), .B(FPADDSUB_DmP_mant_SFG_SWR[9]),
.Y(n7186) );
NOR2X1TS U6915 ( .A(n7192), .B(n7186), .Y(n5848) );
NAND2X1TS U6916 ( .A(n6369), .B(n5848), .Y(n5850) );
NAND2X1TS U6917 ( .A(FPADDSUB_DMP_SFG[4]), .B(FPADDSUB_DmP_mant_SFG_SWR[6]),
.Y(n6415) );
NAND2X1TS U6918 ( .A(FPADDSUB_DMP_SFG[5]), .B(FPADDSUB_DmP_mant_SFG_SWR[7]),
.Y(n6411) );
OAI21X1TS U6919 ( .A0(n6410), .A1(n6415), .B0(n6411), .Y(n6368) );
NAND2X1TS U6920 ( .A(FPADDSUB_DMP_SFG[6]), .B(FPADDSUB_DmP_mant_SFG_SWR[8]),
.Y(n7191) );
NAND2X1TS U6921 ( .A(FPADDSUB_DMP_SFG[7]), .B(FPADDSUB_DmP_mant_SFG_SWR[9]),
.Y(n7187) );
AOI21X1TS U6922 ( .A0(n6368), .A1(n5848), .B0(n5847), .Y(n5849) );
OAI21X2TS U6923 ( .A0(n6367), .A1(n5850), .B0(n5849), .Y(n7134) );
NOR2X1TS U6924 ( .A(FPADDSUB_DMP_SFG[8]), .B(FPADDSUB_DmP_mant_SFG_SWR[10]),
.Y(n7135) );
INVX2TS U6925 ( .A(n7135), .Y(n7145) );
NAND2X1TS U6926 ( .A(n7145), .B(n7131), .Y(n7179) );
NOR2X2TS U6927 ( .A(FPADDSUB_DMP_SFG[10]), .B(FPADDSUB_DmP_mant_SFG_SWR[12]),
.Y(n7173) );
NOR2X1TS U6928 ( .A(n7179), .B(n7173), .Y(n5854) );
NAND2X1TS U6929 ( .A(FPADDSUB_DMP_SFG[8]), .B(FPADDSUB_DmP_mant_SFG_SWR[10]),
.Y(n7144) );
INVX2TS U6930 ( .A(n7144), .Y(n5852) );
NAND2X1TS U6931 ( .A(FPADDSUB_DMP_SFG[9]), .B(FPADDSUB_DmP_mant_SFG_SWR[11]),
.Y(n7130) );
INVX2TS U6932 ( .A(n7130), .Y(n5851) );
AOI21X1TS U6933 ( .A0(n7131), .A1(n5852), .B0(n5851), .Y(n7178) );
NAND2X1TS U6934 ( .A(FPADDSUB_DMP_SFG[10]), .B(FPADDSUB_DmP_mant_SFG_SWR[12]), .Y(n7174) );
OAI21X1TS U6935 ( .A0(n7178), .A1(n7173), .B0(n7174), .Y(n5853) );
AOI21X4TS U6936 ( .A0(n7134), .A1(n5854), .B0(n5853), .Y(n7121) );
NOR2X1TS U6937 ( .A(FPADDSUB_DMP_SFG[11]), .B(FPADDSUB_DmP_mant_SFG_SWR[13]),
.Y(n7115) );
NAND2X1TS U6938 ( .A(FPADDSUB_DMP_SFG[12]), .B(FPADDSUB_DmP_mant_SFG_SWR[14]), .Y(n7106) );
INVX2TS U6939 ( .A(n7106), .Y(n5855) );
AOI21X4TS U6940 ( .A0(n7111), .A1(n7107), .B0(n5855), .Y(n6595) );
XNOR2X1TS U6941 ( .A(n5868), .B(n5856), .Y(n5857) );
BUFX3TS U6942 ( .A(n7088), .Y(n7599) );
AOI22X1TS U6943 ( .A0(n5857), .A1(n6371), .B0(FPADDSUB_Raw_mant_NRM_SWR[16]),
.B1(n7599), .Y(n5858) );
OAI2BB1X1TS U6944 ( .A0N(n6599), .A1N(n5859), .B0(n5858), .Y(n1335) );
OR2X1TS U6945 ( .A(n7872), .B(n2481), .Y(n5861) );
AOI21X4TS U6946 ( .A0(n5862), .A1(n5861), .B0(n5860), .Y(n6074) );
NOR2X1TS U6947 ( .A(n2487), .B(FPADDSUB_DmP_mant_SFG_SWR[17]), .Y(n6091) );
NAND2X1TS U6948 ( .A(n5863), .B(n6090), .Y(n5869) );
INVX2TS U6949 ( .A(n5869), .Y(n5864) );
INVX2TS U6950 ( .A(n5865), .Y(n5866) );
AOI21X4TS U6951 ( .A0(n5868), .A1(n5867), .B0(n5866), .Y(n6092) );
XOR2X1TS U6952 ( .A(n6092), .B(n5869), .Y(n5870) );
AOI22X1TS U6953 ( .A0(n5870), .A1(n6371), .B0(FPADDSUB_Raw_mant_NRM_SWR[17]),
.B1(n7599), .Y(n5871) );
OAI2BB1X1TS U6954 ( .A0N(n6599), .A1N(n5872), .B0(n5871), .Y(n1334) );
INVX2TS U6955 ( .A(n7571), .Y(n5878) );
AOI22X1TS U6956 ( .A0(n5904), .A1(n8241), .B0(n6005), .B1(n8240), .Y(n5875)
);
AOI22X1TS U6957 ( .A0(n7397), .A1(n5878), .B0(n7395), .B1(n5877), .Y(n5887)
);
AOI22X1TS U6958 ( .A0(n5904), .A1(n8209), .B0(n6872), .B1(n8208), .Y(n5879)
);
INVX2TS U6959 ( .A(n7580), .Y(n5884) );
AOI22X1TS U6960 ( .A0(n8076), .A1(n8217), .B0(n6872), .B1(n8216), .Y(n5881)
);
NAND3X2TS U6961 ( .A(n8407), .B(n5882), .C(n5892), .Y(n7569) );
OAI21X1TS U6962 ( .A0(n7398), .A1(n5884), .B0(n5883), .Y(n6033) );
OAI211X1TS U6963 ( .A0(n5887), .A1(n6033), .B0(n5886), .C0(n5885), .Y(n5902)
);
AOI22X1TS U6964 ( .A0(n7447), .A1(n8157), .B0(n2208), .B1(n8156), .Y(n5888)
);
NAND3X2TS U6965 ( .A(n8409), .B(n5888), .C(n5892), .Y(n7570) );
AOI22X1TS U6966 ( .A0(n8076), .A1(n8277), .B0(n6872), .B1(n8276), .Y(n5889)
);
INVX2TS U6967 ( .A(n7400), .Y(n5896) );
AOI22X1TS U6968 ( .A0(n7447), .A1(n8161), .B0(n8017), .B1(n8160), .Y(n5890)
);
NAND2X2TS U6969 ( .A(n8294), .B(n5890), .Y(n7568) );
INVX2TS U6970 ( .A(n7568), .Y(n5899) );
BUFX3TS U6971 ( .A(n8077), .Y(n6873) );
AOI22X1TS U6972 ( .A0(n6873), .A1(n8251), .B0(n6872), .B1(n8250), .Y(n5891)
);
AOI22X1TS U6973 ( .A0(n7447), .A1(n8155), .B0(n2208), .B1(n8154), .Y(n5893)
);
NAND3X2TS U6974 ( .A(n8411), .B(n5893), .C(n5892), .Y(n7567) );
INVX2TS U6975 ( .A(n7567), .Y(n5898) );
AOI22X1TS U6976 ( .A0(n8076), .A1(n8225), .B0(n6872), .B1(n8224), .Y(n5894)
);
AOI211X2TS U6977 ( .A0(n7570), .A1(n5896), .B0(n5900), .C0(n5895), .Y(n6031)
);
NOR3X1TS U6978 ( .A(n5896), .B(n5895), .C(n7570), .Y(n5897) );
AOI221X1TS U6979 ( .A0(n7403), .A1(n5899), .B0(n7401), .B1(n5898), .C0(n5897), .Y(n5901) );
AOI22X1TS U6980 ( .A0(n5986), .A1(n8245), .B0(n2207), .B1(n8244), .Y(n5903)
);
NAND3X2TS U6981 ( .A(n8412), .B(n5903), .C(n5992), .Y(n7652) );
INVX2TS U6982 ( .A(n7652), .Y(n6016) );
AOI22X1TS U6983 ( .A0(n2251), .A1(n8261), .B0(n6005), .B1(n8260), .Y(n5905)
);
BUFX3TS U6984 ( .A(n8075), .Y(n5935) );
BUFX3TS U6985 ( .A(n2256), .Y(n5989) );
AOI22X1TS U6986 ( .A0(n5935), .A1(n8195), .B0(n5989), .B1(n8194), .Y(n5906)
);
AOI22X1TS U6987 ( .A0(n5986), .A1(n8205), .B0(n5998), .B1(n8204), .Y(n5907)
);
OAI211X4TS U6988 ( .A0(n2259), .A1(n8380), .B0(n8379), .C0(n5907), .Y(n7583)
);
INVX2TS U6989 ( .A(n7583), .Y(n5970) );
AOI22X1TS U6990 ( .A0(n5935), .A1(n8201), .B0(n5989), .B1(n8200), .Y(n5908)
);
AOI22X1TS U6991 ( .A0(n5986), .A1(n8223), .B0(n5998), .B1(n8222), .Y(n5909)
);
AOI22X1TS U6992 ( .A0(n5986), .A1(n8215), .B0(n5998), .B1(n8214), .Y(n5910)
);
OAI211X4TS U6993 ( .A0(n2201), .A1(n8386), .B0(n8385), .C0(n5910), .Y(n7566)
);
AOI22X1TS U6994 ( .A0(n2251), .A1(n8275), .B0(n5989), .B1(n8274), .Y(n5911)
);
AOI22X1TS U6995 ( .A0(n5986), .A1(n8271), .B0(n2207), .B1(n8270), .Y(n5912)
);
NAND2X1TS U6996 ( .A(n2256), .B(n8148), .Y(n5922) );
NAND3X2TS U6997 ( .A(n8303), .B(n5912), .C(n5922), .Y(n7565) );
INVX2TS U6998 ( .A(n7565), .Y(n5968) );
AOI22X1TS U6999 ( .A0(n2251), .A1(n8213), .B0(n5989), .B1(n8212), .Y(n5913)
);
OAI211X4TS U7000 ( .A0(n2204), .A1(n8382), .B0(n8381), .C0(n5913), .Y(n7380)
);
AOI21X1TS U7001 ( .A0(n7566), .A1(n5914), .B0(n5966), .Y(n5973) );
AOI22X1TS U7002 ( .A0(n6873), .A1(n8211), .B0(n6872), .B1(n8210), .Y(n5915)
);
AOI22X1TS U7003 ( .A0(n5935), .A1(n8199), .B0(n5989), .B1(n8198), .Y(n5916)
);
INVX2TS U7004 ( .A(n7375), .Y(n5942) );
AOI22X1TS U7005 ( .A0(n6873), .A1(n8281), .B0(n2208), .B1(n8280), .Y(n5917)
);
NAND2X1TS U7006 ( .A(n5934), .B(n8150), .Y(n5954) );
NAND3X2TS U7007 ( .A(n8306), .B(n5917), .C(n5954), .Y(n7581) );
AOI22X1TS U7008 ( .A0(n5935), .A1(n8193), .B0(n5934), .B1(n8192), .Y(n5918)
);
OAI2BB1X1TS U7009 ( .A0N(n5942), .A1N(n7581), .B0(n7373), .Y(n5919) );
OAI22X1TS U7010 ( .A0(n7582), .A1(n5919), .B0(n5942), .B1(n7581), .Y(n5951)
);
AOI22X1TS U7011 ( .A0(n6873), .A1(n8203), .B0(n5998), .B1(n8202), .Y(n5920)
);
AOI22X1TS U7012 ( .A0(n5935), .A1(n8197), .B0(n5989), .B1(n8196), .Y(n5921)
);
INVX2TS U7013 ( .A(n7614), .Y(n5947) );
AOI22X1TS U7014 ( .A0(n6873), .A1(n8273), .B0(n2207), .B1(n8272), .Y(n5923)
);
NAND3X2TS U7015 ( .A(n8304), .B(n5923), .C(n5922), .Y(n6867) );
AOI22X1TS U7016 ( .A0(n5935), .A1(n8179), .B0(n5934), .B1(n8178), .Y(n5924)
);
OAI2BB1X1TS U7017 ( .A0N(n5947), .A1N(n6867), .B0(n7376), .Y(n5925) );
OAI22X1TS U7018 ( .A0(n7584), .A1(n5925), .B0(n5947), .B1(n6867), .Y(n5950)
);
INVX2TS U7019 ( .A(n7373), .Y(n5945) );
AOI22X1TS U7020 ( .A0(n6873), .A1(n8263), .B0(n2247), .B1(n8262), .Y(n5926)
);
NAND2X1TS U7021 ( .A(n5934), .B(n8149), .Y(n5987) );
NAND3X2TS U7022 ( .A(n8301), .B(n5926), .C(n5987), .Y(n7608) );
INVX2TS U7023 ( .A(n7608), .Y(n5941) );
AOI22X1TS U7024 ( .A0(n5935), .A1(n8183), .B0(n5934), .B1(n8182), .Y(n5927)
);
OAI211X4TS U7025 ( .A0(n2260), .A1(n8326), .B0(n8325), .C0(n5927), .Y(n7371)
);
AOI22X1TS U7026 ( .A0(n6873), .A1(n8227), .B0(n6872), .B1(n8226), .Y(n5928)
);
OAI211X4TS U7027 ( .A0(n2201), .A1(n8394), .B0(n8393), .C0(n5928), .Y(n7617)
);
AOI22X1TS U7028 ( .A0(n5935), .A1(n8189), .B0(n5934), .B1(n8188), .Y(n5929)
);
AOI22X1TS U7029 ( .A0(n6873), .A1(n8235), .B0(n6872), .B1(n8234), .Y(n5930)
);
OAI211X4TS U7030 ( .A0(n2260), .A1(n8396), .B0(n8395), .C0(n5930), .Y(n7620)
);
INVX2TS U7031 ( .A(n7620), .Y(n5932) );
AOI22X1TS U7032 ( .A0(n5935), .A1(n8191), .B0(n8190), .B1(n5934), .Y(n5931)
);
AOI22X1TS U7033 ( .A0(n5935), .A1(n8187), .B0(n5934), .B1(n8186), .Y(n5936)
);
AOI22X1TS U7034 ( .A0(n6873), .A1(n8219), .B0(n6872), .B1(n8218), .Y(n5937)
);
OAI211X4TS U7035 ( .A0(n2260), .A1(n8392), .B0(n8391), .C0(n5937), .Y(n7611)
);
AOI222X1TS U7036 ( .A0(n7582), .A1(n5945), .B0(n5944), .B1(n5943), .C0(n7581), .C1(n5942), .Y(n5949) );
INVX2TS U7037 ( .A(n7376), .Y(n5946) );
AOI22X1TS U7038 ( .A0(n6867), .A1(n5947), .B0(n7584), .B1(n5946), .Y(n5948)
);
OAI32X1TS U7039 ( .A0(n5951), .A1(n5950), .A2(n5949), .B0(n5948), .B1(n5950),
.Y(n5984) );
AOI22X1TS U7040 ( .A0(n2251), .A1(n8239), .B0(n6005), .B1(n8238), .Y(n5952)
);
AOI22X1TS U7041 ( .A0(n5986), .A1(n8229), .B0(n5998), .B1(n8228), .Y(n5953)
);
INVX2TS U7042 ( .A(n7638), .Y(n5963) );
AOI22X1TS U7043 ( .A0(n5986), .A1(n8279), .B0(n2207), .B1(n8278), .Y(n5955)
);
NAND3X2TS U7044 ( .A(n8305), .B(n5955), .C(n5954), .Y(n7564) );
INVX2TS U7045 ( .A(n7564), .Y(n5959) );
AOI22X1TS U7046 ( .A0(n2251), .A1(n8221), .B0(n5989), .B1(n8220), .Y(n5956)
);
AOI22X1TS U7047 ( .A0(n5986), .A1(n8237), .B0(n2247), .B1(n8236), .Y(n5957)
);
NAND3X2TS U7048 ( .A(n8408), .B(n5957), .C(n5992), .Y(n7561) );
INVX2TS U7049 ( .A(n7561), .Y(n5976) );
AOI22X1TS U7050 ( .A0(n2251), .A1(n8231), .B0(n5989), .B1(n8230), .Y(n5958)
);
OAI211X4TS U7051 ( .A0(n2204), .A1(n8360), .B0(n8359), .C0(n5958), .Y(n7386)
);
OA22X2TS U7052 ( .A0(n5959), .A1(n7384), .B0(n5976), .B1(n7386), .Y(n5981)
);
AOI22X1TS U7053 ( .A0(n2251), .A1(n8267), .B0(n5989), .B1(n8266), .Y(n5960)
);
OAI211X4TS U7054 ( .A0(n2260), .A1(n8376), .B0(n8375), .C0(n5960), .Y(n7382)
);
AOI22X1TS U7055 ( .A0(n5986), .A1(n8265), .B0(n2207), .B1(n8264), .Y(n5961)
);
NAND2X1TS U7056 ( .A(n2256), .B(n8147), .Y(n6003) );
NAND3X2TS U7057 ( .A(n8302), .B(n5961), .C(n6003), .Y(n7563) );
INVX2TS U7058 ( .A(n7563), .Y(n5964) );
AOI22X1TS U7059 ( .A0(n7380), .A1(n5968), .B0(n7379), .B1(n5967), .Y(n5975)
);
AOI21X1TS U7060 ( .A0(n5972), .A1(n5971), .B0(n5983), .Y(n5974) );
OAI2BB2X1TS U7061 ( .B0(n5975), .B1(n5983), .A0N(n5974), .A1N(n5973), .Y(
n5979) );
AOI211X1TS U7062 ( .A0(n5981), .A1(n5980), .B0(n5979), .C0(n5978), .Y(n5982)
);
OAI31X1TS U7063 ( .A0(n5985), .A1(n5984), .A2(n5983), .B0(n5982), .Y(n6011)
);
AOI22X1TS U7064 ( .A0(n5986), .A1(n8257), .B0(n2208), .B1(n8256), .Y(n5988)
);
NAND3X2TS U7065 ( .A(n8300), .B(n5988), .C(n5987), .Y(n7562) );
AOI22X1TS U7066 ( .A0(n2251), .A1(n8207), .B0(n5989), .B1(n8206), .Y(n5990)
);
INVX2TS U7067 ( .A(n7387), .Y(n6009) );
AOI22X1TS U7068 ( .A0(n7447), .A1(n8169), .B0(n2208), .B1(n8168), .Y(n5993)
);
NAND3X2TS U7069 ( .A(n8410), .B(n5993), .C(n5992), .Y(n7656) );
INVX2TS U7070 ( .A(n7656), .Y(n6001) );
AOI22X1TS U7071 ( .A0(n7447), .A1(n8163), .B0(n2208), .B1(n8162), .Y(n5994)
);
NAND2X1TS U7072 ( .A(n2256), .B(n8146), .Y(n6007) );
NAND3X2TS U7073 ( .A(n8296), .B(n5994), .C(n6007), .Y(n7577) );
INVX2TS U7074 ( .A(n7577), .Y(n5996) );
INVX2TS U7075 ( .A(gt_x_74_B_23_), .Y(n6024) );
AOI22X1TS U7076 ( .A0(n2251), .A1(n8249), .B0(n6005), .B1(n8248), .Y(n6002)
);
NAND3X2TS U7077 ( .A(n8298), .B(n6004), .C(n6003), .Y(n7560) );
INVX2TS U7078 ( .A(n7560), .Y(n6019) );
AOI22X1TS U7079 ( .A0(n2251), .A1(n8255), .B0(n6005), .B1(n8254), .Y(n6006)
);
AOI22X1TS U7080 ( .A0(n8074), .A1(n8165), .B0(n2208), .B1(n8164), .Y(n6008)
);
NAND3X2TS U7081 ( .A(n8297), .B(n6008), .C(n6007), .Y(n7578) );
OAI21X1TS U7082 ( .A0(n7389), .A1(n6019), .B0(n6018), .Y(n6023) );
AOI211X1TS U7083 ( .A0(n7562), .A1(n6009), .B0(n6022), .C0(n6023), .Y(n6010)
);
INVX2TS U7084 ( .A(n7576), .Y(n6012) );
AOI22X1TS U7085 ( .A0(n7388), .A1(n6016), .B0(n7387), .B1(n6015), .Y(n6021)
);
INVX2TS U7086 ( .A(n7578), .Y(n6017) );
AOI32X1TS U7087 ( .A0(n6019), .A1(n6018), .A2(n7389), .B0(n7390), .B1(n6017),
.Y(n6020) );
OAI32X1TS U7088 ( .A0(n6023), .A1(n6022), .A2(n6021), .B0(n6020), .B1(n6022),
.Y(n6027) );
AOI211X1TS U7089 ( .A0(n6029), .A1(n6028), .B0(n6027), .C0(n6026), .Y(n6035)
);
AOI32X4TS U7090 ( .A0(n6037), .A1(n6036), .A2(n6035), .B0(n6034), .B1(n6037),
.Y(n7595) );
AOI22X1TS U7091 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
n6587), .B0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .B1(n8642),
.Y(n6854) );
OR4X2TS U7092 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[7]), .B(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[1]), .C(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .D(
FPSENCOS_inst_CORDIC_FSM_v3_state_reg[6]), .Y(n6547) );
NAND4X2TS U7093 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[5]), .B(n6038),
.C(n7792), .D(n7815), .Y(n7286) );
NAND3X2TS U7094 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[4]), .B(n6645),
.C(n7815), .Y(n7285) );
INVX2TS U7095 ( .A(n6188), .Y(n6763) );
NAND2X1TS U7096 ( .A(FPSENCOS_cont_var_out[1]), .B(FPSENCOS_cont_var_out[0]),
.Y(n7284) );
OAI22X1TS U7097 ( .A0(n8021), .A1(n8059), .B0(n8020), .B1(n2371), .Y(n6041)
);
AOI21X1TS U7098 ( .A0(n2212), .A1(n8419), .B0(n6041), .Y(n6042) );
AOI22X1TS U7099 ( .A0(n2210), .A1(n8068), .B0(n2345), .B1(n8047), .Y(n6044)
);
AOI22X1TS U7100 ( .A0(n2405), .A1(n8429), .B0(n6851), .B1(n8019), .Y(n6043)
);
AOI22X1TS U7101 ( .A0(n2211), .A1(n8471), .B0(n2406), .B1(n8470), .Y(n6046)
);
AOI22X1TS U7102 ( .A0(n2375), .A1(n8048), .B0(n2471), .B1(n8047), .Y(n6045)
);
AOI22X1TS U7103 ( .A0(n2210), .A1(n8450), .B0(n2405), .B1(n8449), .Y(n6048)
);
AOI22X1TS U7104 ( .A0(n2375), .A1(n8047), .B0(n6851), .B1(n8456), .Y(n6047)
);
OAI211X4TS U7105 ( .A0(n8022), .A1(n8059), .B0(n6048), .C0(n6047), .Y(n1810)
);
AOI22X1TS U7106 ( .A0(n2210), .A1(n8452), .B0(n2405), .B1(n8451), .Y(n6050)
);
AOI22X1TS U7107 ( .A0(n2345), .A1(n8048), .B0(n6851), .B1(n8448), .Y(n6049)
);
OAI211X4TS U7108 ( .A0(n8022), .A1(n2371), .B0(n6050), .C0(n6049), .Y(n1809)
);
BUFX3TS U7109 ( .A(n6581), .Y(n8526) );
NOR2BX2TS U7110 ( .AN(n8633), .B(n8646), .Y(n6069) );
NOR2X2TS U7111 ( .A(FPADDSUB_Raw_mant_NRM_SWR[13]), .B(n6668), .Y(n6698) );
INVX2TS U7112 ( .A(n6698), .Y(n6064) );
NAND2X1TS U7113 ( .A(n7812), .B(n7793), .Y(n6673) );
NOR2BX4TS U7114 ( .AN(n6674), .B(n6673), .Y(n6065) );
AOI21X1TS U7115 ( .A0(n7825), .A1(FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n6051) );
AOI211X1TS U7116 ( .A0(n6675), .A1(FPADDSUB_Raw_mant_NRM_SWR[6]), .B0(n6056),
.C0(n6055), .Y(n6061) );
NAND2X1TS U7117 ( .A(FPADDSUB_Raw_mant_NRM_SWR[10]), .B(n6059), .Y(n6693) );
OAI22X1TS U7118 ( .A0(n6693), .A1(FPADDSUB_Raw_mant_NRM_SWR[12]), .B0(n7821),
.B1(n8629), .Y(n6067) );
NAND2X4TS U7119 ( .A(n6675), .B(n7810), .Y(n6669) );
AOI31X1TS U7120 ( .A0(n6061), .A1(n6671), .A2(n6060), .B0(n7301), .Y(n7093)
);
INVX2TS U7121 ( .A(n6858), .Y(n6833) );
AOI21X1TS U7122 ( .A0(n8630), .A1(FPADDSUB_Raw_mant_NRM_SWR[15]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[19]), .Y(n6062) );
OAI31X1TS U7123 ( .A0(n6062), .A1(FPADDSUB_Raw_mant_NRM_SWR[21]), .A2(
FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(n8631), .Y(n6063) );
INVX2TS U7124 ( .A(n6063), .Y(n6071) );
INVX2TS U7125 ( .A(n6669), .Y(n6679) );
NAND3X2TS U7126 ( .A(n6679), .B(n7797), .C(n7816), .Y(n6695) );
NAND2X1TS U7127 ( .A(n6069), .B(FPADDSUB_Raw_mant_NRM_SWR[14]), .Y(n6691) );
BUFX3TS U7128 ( .A(n7642), .Y(n7658) );
NAND2X1TS U7129 ( .A(n7864), .B(n2487), .Y(n6072) );
OAI21X4TS U7130 ( .A0(n6074), .A1(n6073), .B0(n6072), .Y(n6160) );
OR2X1TS U7131 ( .A(n7871), .B(n2475), .Y(n6076) );
AOI21X4TS U7132 ( .A0(n6160), .A1(n6076), .B0(n6075), .Y(n6151) );
NOR2X1TS U7133 ( .A(n7863), .B(n2483), .Y(n6078) );
NAND2X1TS U7134 ( .A(n7863), .B(n2483), .Y(n6077) );
OAI21X4TS U7135 ( .A0(n6151), .A1(n6078), .B0(n6077), .Y(n6141) );
AOI21X4TS U7136 ( .A0(n6141), .A1(n6080), .B0(n6079), .Y(n6132) );
NOR2X1TS U7137 ( .A(n7862), .B(n2485), .Y(n6082) );
NAND2X1TS U7138 ( .A(n7862), .B(n2485), .Y(n6081) );
OAI21X4TS U7139 ( .A0(n6132), .A1(n6082), .B0(n6081), .Y(n6122) );
OR2X1TS U7140 ( .A(n7869), .B(n2477), .Y(n6084) );
AOI21X4TS U7141 ( .A0(n6122), .A1(n6084), .B0(n6083), .Y(n6113) );
NAND2X1TS U7142 ( .A(n7861), .B(n2486), .Y(n6085) );
OR2X1TS U7143 ( .A(n7868), .B(n2473), .Y(n6088) );
AOI21X1TS U7144 ( .A0(n6103), .A1(n6088), .B0(n6087), .Y(n6089) );
XOR2X1TS U7145 ( .A(n6089), .B(n7875), .Y(n6099) );
NAND2X1TS U7146 ( .A(FPADDSUB_DMP_SFG[16]), .B(FPADDSUB_DmP_mant_SFG_SWR[18]), .Y(n6157) );
INVX2TS U7147 ( .A(n6157), .Y(n6093) );
NOR2X1TS U7148 ( .A(n2483), .B(FPADDSUB_DmP_mant_SFG_SWR[19]), .Y(n6147) );
NAND2X1TS U7149 ( .A(FPADDSUB_DMP_SFG[17]), .B(FPADDSUB_DmP_mant_SFG_SWR[19]), .Y(n6148) );
NAND2X1TS U7150 ( .A(FPADDSUB_DMP_SFG[18]), .B(FPADDSUB_DmP_mant_SFG_SWR[20]), .Y(n6138) );
INVX2TS U7151 ( .A(n6138), .Y(n6094) );
AOI21X4TS U7152 ( .A0(n6143), .A1(n6139), .B0(n6094), .Y(n6134) );
NOR2X1TS U7153 ( .A(n2485), .B(FPADDSUB_DmP_mant_SFG_SWR[21]), .Y(n6128) );
NAND2X1TS U7154 ( .A(FPADDSUB_DMP_SFG[19]), .B(FPADDSUB_DmP_mant_SFG_SWR[21]), .Y(n6129) );
OAI21X4TS U7155 ( .A0(n6134), .A1(n6128), .B0(n6129), .Y(n6124) );
NAND2X1TS U7156 ( .A(FPADDSUB_DMP_SFG[20]), .B(FPADDSUB_DmP_mant_SFG_SWR[22]), .Y(n6119) );
INVX2TS U7157 ( .A(n6119), .Y(n6095) );
AOI21X4TS U7158 ( .A0(n6124), .A1(n6120), .B0(n6095), .Y(n6115) );
NOR2X1TS U7159 ( .A(n2486), .B(FPADDSUB_DmP_mant_SFG_SWR[23]), .Y(n6109) );
NAND2X1TS U7160 ( .A(n2486), .B(FPADDSUB_DmP_mant_SFG_SWR[23]), .Y(n6110) );
OAI21X4TS U7161 ( .A0(n6115), .A1(n6109), .B0(n6110), .Y(n6105) );
NAND2X1TS U7162 ( .A(FPADDSUB_DMP_SFG[22]), .B(FPADDSUB_DmP_mant_SFG_SWR[24]), .Y(n6100) );
INVX2TS U7163 ( .A(n6100), .Y(n6096) );
AOI21X4TS U7164 ( .A0(n6105), .A1(n6101), .B0(n6096), .Y(n7090) );
XOR2X1TS U7165 ( .A(n7090), .B(FPADDSUB_DmP_mant_SFG_SWR[25]), .Y(n6097) );
OAI2BB1X2TS U7166 ( .A0N(n6599), .A1N(n6099), .B0(n6098), .Y(n1412) );
NAND2X1TS U7167 ( .A(n6101), .B(n6100), .Y(n6104) );
INVX2TS U7168 ( .A(n6104), .Y(n6102) );
XNOR2X1TS U7169 ( .A(n6103), .B(n6102), .Y(n6108) );
XNOR2X1TS U7170 ( .A(n6105), .B(n6104), .Y(n6106) );
AOI22X1TS U7171 ( .A0(n6106), .A1(n6371), .B0(FPADDSUB_Raw_mant_NRM_SWR[24]),
.B1(n7599), .Y(n6107) );
NOR2X4TS U7172 ( .A(n1412), .B(n1317), .Y(n8415) );
INVX2TS U7173 ( .A(n6109), .Y(n6111) );
NAND2X1TS U7174 ( .A(n6111), .B(n6110), .Y(n6114) );
INVX2TS U7175 ( .A(n6114), .Y(n6112) );
XOR2X1TS U7176 ( .A(n6115), .B(n6114), .Y(n6116) );
BUFX3TS U7177 ( .A(n6371), .Y(n7138) );
AOI22X1TS U7178 ( .A0(n6116), .A1(n7138), .B0(FPADDSUB_Raw_mant_NRM_SWR[23]),
.B1(n7599), .Y(n6117) );
NAND2X1TS U7179 ( .A(n6120), .B(n6119), .Y(n6123) );
INVX2TS U7180 ( .A(n6123), .Y(n6121) );
XNOR2X1TS U7181 ( .A(n6122), .B(n6121), .Y(n6127) );
XNOR2X1TS U7182 ( .A(n6124), .B(n6123), .Y(n6125) );
BUFX3TS U7183 ( .A(n7088), .Y(n7159) );
AOI22X1TS U7184 ( .A0(n6125), .A1(n7138), .B0(FPADDSUB_Raw_mant_NRM_SWR[22]),
.B1(n7159), .Y(n6126) );
INVX2TS U7185 ( .A(n6128), .Y(n6130) );
NAND2X1TS U7186 ( .A(n6130), .B(n6129), .Y(n6133) );
INVX2TS U7187 ( .A(n6133), .Y(n6131) );
XOR2X1TS U7188 ( .A(n6134), .B(n6133), .Y(n6135) );
AOI22X1TS U7189 ( .A0(n6135), .A1(n7138), .B0(FPADDSUB_Raw_mant_NRM_SWR[21]),
.B1(n7159), .Y(n6136) );
NAND2X1TS U7190 ( .A(n6139), .B(n6138), .Y(n6142) );
INVX2TS U7191 ( .A(n6142), .Y(n6140) );
XNOR2X1TS U7192 ( .A(n6141), .B(n6140), .Y(n6146) );
XNOR2X1TS U7193 ( .A(n6143), .B(n6142), .Y(n6144) );
AOI22X1TS U7194 ( .A0(n6144), .A1(n7138), .B0(FPADDSUB_Raw_mant_NRM_SWR[20]),
.B1(n7159), .Y(n6145) );
NAND2X1TS U7195 ( .A(n6149), .B(n6148), .Y(n6152) );
INVX2TS U7196 ( .A(n6152), .Y(n6150) );
XOR2X1TS U7197 ( .A(n6153), .B(n6152), .Y(n6154) );
AOI22X1TS U7198 ( .A0(n6154), .A1(n7138), .B0(FPADDSUB_Raw_mant_NRM_SWR[19]),
.B1(n7159), .Y(n6155) );
OAI2BB1X1TS U7199 ( .A0N(n6599), .A1N(n6156), .B0(n6155), .Y(n1323) );
AND2X4TS U7200 ( .A(n8415), .B(n8414), .Y(n6879) );
NAND2X2TS U7201 ( .A(n6879), .B(n6878), .Y(n8291) );
BUFX3TS U7202 ( .A(n6424), .Y(n7201) );
NAND2X1TS U7203 ( .A(n6158), .B(n6157), .Y(n6161) );
INVX2TS U7204 ( .A(n6161), .Y(n6159) );
XNOR2X1TS U7205 ( .A(n6160), .B(n6159), .Y(n6165) );
XNOR2X1TS U7206 ( .A(n6162), .B(n6161), .Y(n6163) );
AOI22X1TS U7207 ( .A0(n6163), .A1(n7138), .B0(FPADDSUB_Raw_mant_NRM_SWR[18]),
.B1(n7159), .Y(n6164) );
OAI2BB1X1TS U7208 ( .A0N(n7201), .A1N(n6165), .B0(n6164), .Y(n1333) );
AOI22X1TS U7209 ( .A0(n2210), .A1(n8476), .B0(n2405), .B1(n8475), .Y(n6168)
);
AOI22X1TS U7210 ( .A0(n2345), .A1(n8049), .B0(n8118), .B1(n8478), .Y(n6167)
);
AOI22X1TS U7211 ( .A0(n2210), .A1(n8073), .B0(n2375), .B1(n8019), .Y(n6169)
);
AOI22X1TS U7212 ( .A0(n2212), .A1(n8445), .B0(n2406), .B1(n8444), .Y(n6171)
);
AOI22X1TS U7213 ( .A0(n2292), .A1(n8053), .B0(n8118), .B1(n8447), .Y(n6170)
);
AOI22X1TS U7214 ( .A0(n2211), .A1(n8461), .B0(n2406), .B1(n8460), .Y(n6173)
);
AOI22X1TS U7215 ( .A0(n2292), .A1(n8051), .B0(n8118), .B1(n8453), .Y(n6172)
);
OAI211X4TS U7216 ( .A0(n8028), .A1(n8058), .B0(n6173), .C0(n6172), .Y(n1801)
);
AOI22X1TS U7217 ( .A0(n2212), .A1(n8437), .B0(n2406), .B1(n8436), .Y(n6175)
);
AOI22X1TS U7218 ( .A0(n2345), .A1(n8055), .B0(n6851), .B1(n8477), .Y(n6174)
);
BUFX3TS U7219 ( .A(n7598), .Y(n7515) );
NOR2X2TS U7220 ( .A(n7814), .B(n7011), .Y(n7034) );
INVX2TS U7221 ( .A(n1809), .Y(n6176) );
INVX2TS U7222 ( .A(n1813), .Y(n7007) );
OAI22X1TS U7223 ( .A0(n6176), .A1(n7012), .B0(n7007), .B1(n6991), .Y(n6177)
);
AOI211X2TS U7224 ( .A0(n2373), .A1(n1805), .B0(n7034), .C0(n6177), .Y(n7051)
);
AOI21X1TS U7225 ( .A0(n2471), .A1(n8027), .B0(n8016), .Y(n6179) );
OAI211X1TS U7226 ( .A0(n8046), .A1(n3147), .B0(n8504), .C0(n6179), .Y(n6881)
);
AOI22X1TS U7227 ( .A0(n1797), .A1(n2443), .B0(n6881), .B1(n2396), .Y(n6183)
);
INVX2TS U7228 ( .A(n7038), .Y(n6180) );
AOI22X1TS U7229 ( .A0(n1801), .A1(n2381), .B0(n1793), .B1(n2398), .Y(n6182)
);
OAI211X1TS U7230 ( .A0(n7051), .A1(n7050), .B0(n6183), .C0(n6182), .Y(n7085)
);
INVX2TS U7231 ( .A(FPADDSUB_bit_shift_SHT2), .Y(n6570) );
NOR2X2TS U7232 ( .A(n2372), .B(n6570), .Y(n7005) );
NOR2X4TS U7233 ( .A(n2340), .B(n6570), .Y(n7052) );
AOI21X1TS U7234 ( .A0(n6184), .A1(n6996), .B0(n7598), .Y(n6185) );
AOI22X1TS U7235 ( .A0(n2212), .A1(n8469), .B0(n2291), .B1(n8468), .Y(n6187)
);
AOI22X1TS U7236 ( .A0(n2345), .A1(n8045), .B0(n8118), .B1(n8431), .Y(n6186)
);
AND3X2TS U7237 ( .A(FPSENCOS_cont_var_out[1]), .B(n6188), .C(n7819), .Y(
n7787) );
NOR2X1TS U7238 ( .A(n7748), .B(n7749), .Y(n6256) );
NOR2X2TS U7239 ( .A(n7775), .B(n7773), .Y(n6295) );
NOR2X1TS U7240 ( .A(n6256), .B(n6295), .Y(n6194) );
XOR2X1TS U7241 ( .A(n7679), .B(n7680), .Y(n6195) );
NOR2X2TS U7242 ( .A(n7774), .B(n7771), .Y(n6319) );
XNOR2X1TS U7243 ( .A(n7683), .B(n7682), .Y(n6196) );
NOR2X2TS U7244 ( .A(n6196), .B(n7770), .Y(n6224) );
XOR2X1TS U7245 ( .A(n7674), .B(n7675), .Y(n6197) );
NOR2X2TS U7246 ( .A(n6197), .B(n7769), .Y(n6238) );
INVX2TS U7247 ( .A(n6603), .Y(n6204) );
OAI2BB1X1TS U7248 ( .A0N(n7757), .A1N(n7752), .B0(n6192), .Y(n6292) );
NAND2X1TS U7249 ( .A(n7775), .B(n7773), .Y(n6296) );
AOI21X1TS U7250 ( .A0(n6292), .A1(n6194), .B0(n6193), .Y(n6220) );
NAND2X1TS U7251 ( .A(n6195), .B(n7772), .Y(n6313) );
NAND2X1TS U7252 ( .A(n7774), .B(n7771), .Y(n6320) );
OAI21X1TS U7253 ( .A0(n6319), .A1(n6313), .B0(n6320), .Y(n6221) );
NAND2X1TS U7254 ( .A(n6196), .B(n7770), .Y(n6231) );
NAND2X1TS U7255 ( .A(n6197), .B(n7769), .Y(n6237) );
AOI21X1TS U7256 ( .A0(n6221), .A1(n6199), .B0(n6198), .Y(n6200) );
INVX2TS U7257 ( .A(n6609), .Y(n6203) );
XOR2X1TS U7258 ( .A(n7677), .B(n7678), .Y(n6205) );
INVX2TS U7259 ( .A(n6450), .Y(n6338) );
NAND2X1TS U7260 ( .A(n6205), .B(n7768), .Y(n6452) );
NAND2X1TS U7261 ( .A(n6338), .B(n6452), .Y(n6206) );
XNOR2X1TS U7262 ( .A(n6207), .B(n6206), .Y(n6208) );
NAND2X1TS U7263 ( .A(n6208), .B(n2248), .Y(n6209) );
OAI2BB1X1TS U7264 ( .A0N(n8057), .A1N(n8505), .B0(n6209), .Y(n1589) );
INVX2TS U7265 ( .A(n6213), .Y(n6215) );
INVX2TS U7266 ( .A(n6219), .Y(n6230) );
INVX2TS U7267 ( .A(n6220), .Y(n6316) );
INVX2TS U7268 ( .A(n6316), .Y(n6305) );
INVX2TS U7269 ( .A(n6221), .Y(n6232) );
OA21XLTS U7270 ( .A0(n6305), .A1(n6230), .B0(n6232), .Y(n6222) );
INVX2TS U7271 ( .A(n6224), .Y(n6229) );
NAND2X1TS U7272 ( .A(n6229), .B(n6231), .Y(n6225) );
XNOR2X1TS U7273 ( .A(n6226), .B(n6225), .Y(n6227) );
NAND2X1TS U7274 ( .A(n6227), .B(n2248), .Y(n6228) );
OAI2BB1X1TS U7275 ( .A0N(n8057), .A1N(n8501), .B0(n6228), .Y(n1587) );
NOR2X1TS U7276 ( .A(n6230), .B(n6224), .Y(n6234) );
INVX2TS U7277 ( .A(n6306), .Y(n6312) );
NAND2X1TS U7278 ( .A(n6234), .B(n6312), .Y(n6236) );
AOI21X1TS U7279 ( .A0(n6316), .A1(n6234), .B0(n6233), .Y(n6235) );
XNOR2X1TS U7280 ( .A(n6240), .B(n6239), .Y(n6241) );
NAND2X1TS U7281 ( .A(n6241), .B(n2248), .Y(n6242) );
OAI2BB1X1TS U7282 ( .A0N(n8057), .A1N(n8503), .B0(n6242), .Y(n1588) );
NOR3XLTS U7283 ( .A(FPSENCOS_cont_var_out[1]), .B(n7819), .C(n6763), .Y(
n6243) );
CLKBUFX2TS U7284 ( .A(n6243), .Y(n8606) );
AOI22X1TS U7285 ( .A0(n2211), .A1(n8443), .B0(n2406), .B1(n8442), .Y(n6245)
);
AOI22X1TS U7286 ( .A0(n2292), .A1(n8052), .B0(n8118), .B1(n8474), .Y(n6244)
);
AOI22X1TS U7287 ( .A0(n2212), .A1(n8441), .B0(n2291), .B1(n8440), .Y(n6247)
);
AOI22X1TS U7288 ( .A0(n2375), .A1(n8051), .B0(n2471), .B1(n8050), .Y(n6246)
);
INVX2TS U7289 ( .A(n6248), .Y(n6250) );
BUFX3TS U7290 ( .A(n8593), .Y(n8550) );
NAND2X1TS U7291 ( .A(n7302), .B(n8550), .Y(n6254) );
CLKBUFX3TS U7292 ( .A(n2348), .Y(n8549) );
OAI33X4TS U7293 ( .A0(n7820), .A1(n8642), .A2(n7795), .B0(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .B1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B2(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[2]), .Y(n8643) );
INVX2TS U7294 ( .A(n8643), .Y(n8644) );
INVX2TS U7295 ( .A(n6256), .Y(n6291) );
NAND2X1TS U7296 ( .A(n6291), .B(n7766), .Y(n6257) );
XNOR2X1TS U7297 ( .A(n6258), .B(n6257), .Y(n6259) );
NAND2X1TS U7298 ( .A(n6259), .B(n2248), .Y(n6260) );
OAI2BB1X1TS U7299 ( .A0N(n8057), .A1N(n8491), .B0(n6260), .Y(n1583) );
INVX2TS U7300 ( .A(n6261), .Y(n6262) );
NAND2X1TS U7301 ( .A(n6857), .B(FPADDSUB_Raw_mant_NRM_SWR[7]), .Y(n6267) );
NAND2X1TS U7302 ( .A(n6641), .B(FPADDSUB_Raw_mant_NRM_SWR[18]), .Y(n6266) );
NAND2X1TS U7303 ( .A(n6699), .B(FPADDSUB_DmP_mant_SHT1_SW[5]), .Y(n6265) );
NAND3X1TS U7304 ( .A(n6267), .B(n6266), .C(n6265), .Y(n8741) );
NAND2X1TS U7305 ( .A(n6857), .B(FPADDSUB_Raw_mant_NRM_SWR[3]), .Y(n6270) );
NAND2X1TS U7306 ( .A(n6641), .B(FPADDSUB_Raw_mant_NRM_SWR[22]), .Y(n6269) );
NAND2X1TS U7307 ( .A(n6699), .B(FPADDSUB_DmP_mant_SHT1_SW[1]), .Y(n6268) );
NAND3X1TS U7308 ( .A(n6270), .B(n6269), .C(n6268), .Y(n8751) );
NAND2X1TS U7309 ( .A(n6838), .B(FPADDSUB_Raw_mant_NRM_SWR[5]), .Y(n6273) );
NAND2X1TS U7310 ( .A(n6576), .B(FPADDSUB_Raw_mant_NRM_SWR[20]), .Y(n6272) );
NAND2X1TS U7311 ( .A(n6699), .B(FPADDSUB_DmP_mant_SHT1_SW[3]), .Y(n6271) );
NAND3X1TS U7312 ( .A(n6273), .B(n6272), .C(n6271), .Y(n8745) );
NAND2X1TS U7313 ( .A(n6838), .B(FPADDSUB_Raw_mant_NRM_SWR[17]), .Y(n6276) );
NAND2X1TS U7314 ( .A(n6576), .B(FPADDSUB_Raw_mant_NRM_SWR[8]), .Y(n6275) );
NAND2X1TS U7315 ( .A(n2296), .B(FPADDSUB_DmP_mant_SHT1_SW[15]), .Y(n6274) );
NAND3X1TS U7316 ( .A(n6276), .B(n6275), .C(n6274), .Y(n8726) );
NAND2X1TS U7317 ( .A(n6857), .B(FPADDSUB_Raw_mant_NRM_SWR[21]), .Y(n6279) );
NAND2X1TS U7318 ( .A(n6882), .B(FPADDSUB_Raw_mant_NRM_SWR[4]), .Y(n6278) );
NAND3X1TS U7319 ( .A(n6279), .B(n6278), .C(n6277), .Y(n8720) );
NAND2X1TS U7320 ( .A(n6857), .B(FPADDSUB_Raw_mant_NRM_SWR[24]), .Y(n6282) );
NAND2X1TS U7321 ( .A(n6882), .B(FPADDSUB_Raw_mant_NRM_SWR[1]), .Y(n6281) );
NAND3X1TS U7322 ( .A(n6282), .B(n6281), .C(n6280), .Y(n8716) );
NAND2X1TS U7323 ( .A(n6641), .B(FPADDSUB_Raw_mant_NRM_SWR[6]), .Y(n6285) );
NAND2X1TS U7324 ( .A(n6699), .B(FPADDSUB_DmP_mant_SHT1_SW[17]), .Y(n6284) );
NAND3X1TS U7325 ( .A(n6286), .B(n6285), .C(n6284), .Y(n8723) );
NAND2X1TS U7326 ( .A(n6838), .B(FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n6289) );
NAND2X1TS U7327 ( .A(n6576), .B(FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n6288) );
NAND3X1TS U7328 ( .A(n6289), .B(n6288), .C(n6287), .Y(n8717) );
NAND2X1TS U7329 ( .A(n6290), .B(n6291), .Y(n6294) );
AOI21X1TS U7330 ( .A0(n6292), .A1(n6291), .B0(n7744), .Y(n6293) );
INVX2TS U7331 ( .A(n6295), .Y(n6297) );
NAND2X1TS U7332 ( .A(n6297), .B(n6296), .Y(n6298) );
XNOR2X1TS U7333 ( .A(n6299), .B(n6298), .Y(n6300) );
NAND2X1TS U7334 ( .A(n6300), .B(n2248), .Y(n6301) );
OAI2BB1X1TS U7335 ( .A0N(n8057), .A1N(n8492), .B0(n6301), .Y(n1584) );
AOI22X1TS U7336 ( .A0(n6540), .A1(FPMULT_Add_result[12]), .B0(
FPMULT_Sgf_normalized_result[11]), .B1(n6440), .Y(n6302) );
OAI2BB1X1TS U7337 ( .A0N(n2445), .A1N(n1588), .B0(n6302), .Y(n6303) );
AOI21X1TS U7338 ( .A0(n6544), .A1(FPMULT_Add_result[11]), .B0(n6303), .Y(
n6304) );
OAI2BB1X1TS U7339 ( .A0N(n2416), .A1N(n1587), .B0(n6304), .Y(n1528) );
INVX2TS U7340 ( .A(n6307), .Y(n6315) );
NAND2X1TS U7341 ( .A(n6315), .B(n6313), .Y(n6308) );
XNOR2X1TS U7342 ( .A(n6309), .B(n6308), .Y(n6310) );
NAND2X1TS U7343 ( .A(n6310), .B(n2248), .Y(n6311) );
OAI2BB1X1TS U7344 ( .A0N(n8057), .A1N(n8500), .B0(n6311), .Y(n1585) );
NAND2X1TS U7345 ( .A(n6312), .B(n6315), .Y(n6318) );
INVX2TS U7346 ( .A(n6313), .Y(n6314) );
AOI21X1TS U7347 ( .A0(n6316), .A1(n6315), .B0(n6314), .Y(n6317) );
INVX2TS U7348 ( .A(n6319), .Y(n6321) );
NAND2X1TS U7349 ( .A(n6321), .B(n6320), .Y(n6322) );
XNOR2X1TS U7350 ( .A(n6323), .B(n6322), .Y(n6324) );
NAND2X1TS U7351 ( .A(n6324), .B(n2248), .Y(n6325) );
OAI2BB1X1TS U7352 ( .A0N(n8057), .A1N(n8502), .B0(n6325), .Y(n1586) );
AOI22X1TS U7353 ( .A0(n6540), .A1(FPMULT_Add_result[10]), .B0(
FPMULT_Sgf_normalized_result[9]), .B1(n6440), .Y(n6326) );
OAI2BB1X1TS U7354 ( .A0N(n2446), .A1N(n1586), .B0(n6326), .Y(n6327) );
AOI21X1TS U7355 ( .A0(n2411), .A1(FPMULT_Add_result[9]), .B0(n6327), .Y(
n6328) );
OAI2BB1X1TS U7356 ( .A0N(n5768), .A1N(n1585), .B0(n6328), .Y(n1526) );
AOI22X1TS U7357 ( .A0(n5774), .A1(FPMULT_Add_result[11]), .B0(
FPMULT_Sgf_normalized_result[10]), .B1(n6539), .Y(n6329) );
OAI2BB1X1TS U7358 ( .A0N(n2444), .A1N(n1587), .B0(n6329), .Y(n6330) );
AOI21X1TS U7359 ( .A0(n2411), .A1(FPMULT_Add_result[10]), .B0(n6330), .Y(
n6331) );
OAI2BB1X1TS U7360 ( .A0N(n2416), .A1N(n1586), .B0(n6331), .Y(n1527) );
AOI22X1TS U7361 ( .A0(n2380), .A1(FPMULT_Add_result[13]), .B0(
FPMULT_Sgf_normalized_result[12]), .B1(n6907), .Y(n6332) );
OAI2BB1X1TS U7362 ( .A0N(n2445), .A1N(n1589), .B0(n6332), .Y(n6333) );
AOI21X1TS U7363 ( .A0(n6544), .A1(FPMULT_Add_result[12]), .B0(n6333), .Y(
n6334) );
OAI2BB1X1TS U7364 ( .A0N(n5768), .A1N(n1588), .B0(n6334), .Y(n1529) );
NAND2X1TS U7365 ( .A(n6603), .B(n6338), .Y(n6336) );
INVX2TS U7366 ( .A(n6452), .Y(n6337) );
AOI21X1TS U7367 ( .A0(n2432), .A1(n6338), .B0(n6337), .Y(n6339) );
NAND2X1TS U7368 ( .A(n6340), .B(n6339), .Y(n6345) );
AOI21X1TS U7369 ( .A0(n7683), .A1(n7681), .B0(n7684), .Y(n6341) );
NOR2X2TS U7370 ( .A(n6342), .B(n7746), .Y(n6453) );
NAND2X1TS U7371 ( .A(n6342), .B(n7747), .Y(n6451) );
NAND2X1TS U7372 ( .A(n6343), .B(n6451), .Y(n6344) );
XNOR2X1TS U7373 ( .A(n6345), .B(n6344), .Y(n6346) );
OAI2BB1X1TS U7374 ( .A0N(n2198), .A1N(n6346), .B0(n8508), .Y(n6884) );
AOI22X1TS U7375 ( .A0(n6540), .A1(FPMULT_Add_result[14]), .B0(
FPMULT_Sgf_normalized_result[13]), .B1(n6539), .Y(n6347) );
OAI2BB1X1TS U7376 ( .A0N(n6884), .A1N(n2445), .B0(n6347), .Y(n6348) );
AOI21X1TS U7377 ( .A0(n6544), .A1(FPMULT_Add_result[13]), .B0(n6348), .Y(
n6349) );
OAI2BB1X1TS U7378 ( .A0N(n2416), .A1N(n1589), .B0(n6349), .Y(n1530) );
INVX2TS U7379 ( .A(n7787), .Y(n8605) );
AOI22X1TS U7380 ( .A0(n2211), .A1(n8439), .B0(n2291), .B1(n8438), .Y(n6351)
);
AOI22X1TS U7381 ( .A0(n2293), .A1(n8052), .B0(n2471), .B1(n8051), .Y(n6350)
);
CLKBUFX2TS U7382 ( .A(n2348), .Y(n6353) );
CLKBUFX3TS U7383 ( .A(n8634), .Y(n7989) );
CLKBUFX2TS U7384 ( .A(n8548), .Y(n7986) );
CLKBUFX3TS U7385 ( .A(n7986), .Y(n7985) );
CLKBUFX3TS U7386 ( .A(n2401), .Y(n7990) );
CLKBUFX3TS U7387 ( .A(n8534), .Y(n7973) );
CLKBUFX3TS U7388 ( .A(n6352), .Y(n7979) );
CLKBUFX3TS U7389 ( .A(n7980), .Y(n7988) );
CLKBUFX3TS U7390 ( .A(n7963), .Y(n7965) );
CLKBUFX2TS U7391 ( .A(n8548), .Y(n7966) );
BUFX3TS U7392 ( .A(n7966), .Y(n8527) );
BUFX3TS U7393 ( .A(n8537), .Y(n8545) );
CLKBUFX2TS U7394 ( .A(n8547), .Y(n7963) );
BUFX3TS U7395 ( .A(n2363), .Y(n8598) );
BUFX3TS U7396 ( .A(n8604), .Y(n7994) );
BUFX3TS U7397 ( .A(n7994), .Y(n8597) );
BUFX3TS U7398 ( .A(n8535), .Y(n8542) );
BUFX3TS U7399 ( .A(n8534), .Y(n8543) );
BUFX3TS U7400 ( .A(n7980), .Y(n8538) );
BUFX3TS U7401 ( .A(n2422), .Y(n8532) );
CLKBUFX2TS U7402 ( .A(n8535), .Y(n7976) );
BUFX3TS U7403 ( .A(n7976), .Y(n8531) );
CLKBUFX2TS U7404 ( .A(n7986), .Y(n7983) );
BUFX3TS U7405 ( .A(n6352), .Y(n8540) );
CLKBUFX3TS U7406 ( .A(n8537), .Y(n8529) );
BUFX3TS U7407 ( .A(n8594), .Y(n8581) );
BUFX3TS U7408 ( .A(n8594), .Y(n8580) );
BUFX3TS U7409 ( .A(n8594), .Y(n8579) );
BUFX3TS U7410 ( .A(n8578), .Y(n8561) );
BUFX3TS U7411 ( .A(n8593), .Y(n8559) );
BUFX3TS U7412 ( .A(n8576), .Y(n8558) );
BUFX3TS U7413 ( .A(n7959), .Y(n8544) );
CLKBUFX3TS U7414 ( .A(n2348), .Y(n8546) );
BUFX3TS U7415 ( .A(n8592), .Y(n8572) );
BUFX3TS U7416 ( .A(n8592), .Y(n8571) );
BUFX3TS U7417 ( .A(n8592), .Y(n8570) );
BUFX3TS U7418 ( .A(n8595), .Y(n8590) );
BUFX3TS U7419 ( .A(n8595), .Y(n8589) );
BUFX3TS U7420 ( .A(n8595), .Y(n8588) );
BUFX3TS U7421 ( .A(n8591), .Y(n8564) );
CLKBUFX2TS U7422 ( .A(n8576), .Y(n7991) );
BUFX3TS U7423 ( .A(n2493), .Y(n8602) );
BUFX3TS U7424 ( .A(n8592), .Y(n8555) );
BUFX3TS U7425 ( .A(n8594), .Y(n8554) );
BUFX3TS U7426 ( .A(n8591), .Y(n8552) );
CLKBUFX2TS U7427 ( .A(n8593), .Y(n8577) );
BUFX3TS U7428 ( .A(n8591), .Y(n8569) );
BUFX3TS U7429 ( .A(n8591), .Y(n8568) );
BUFX3TS U7430 ( .A(n8591), .Y(n8567) );
BUFX3TS U7431 ( .A(n8591), .Y(n8566) );
BUFX3TS U7432 ( .A(n8591), .Y(n8565) );
BUFX3TS U7433 ( .A(n7959), .Y(n7974) );
BUFX3TS U7434 ( .A(n8594), .Y(n8583) );
BUFX3TS U7435 ( .A(n8595), .Y(n8551) );
BUFX3TS U7436 ( .A(n8592), .Y(n8573) );
BUFX3TS U7437 ( .A(n8595), .Y(n8587) );
BUFX3TS U7438 ( .A(n8592), .Y(n8575) );
BUFX3TS U7439 ( .A(n8594), .Y(n8582) );
BUFX3TS U7440 ( .A(n8594), .Y(n8584) );
BUFX3TS U7441 ( .A(n8595), .Y(n8585) );
BUFX3TS U7442 ( .A(n8595), .Y(n8586) );
BUFX3TS U7443 ( .A(n8592), .Y(n8574) );
BUFX3TS U7444 ( .A(n8537), .Y(n8528) );
CLKBUFX3TS U7445 ( .A(n2347), .Y(n7975) );
BUFX3TS U7446 ( .A(n7980), .Y(n7987) );
BUFX3TS U7447 ( .A(n6352), .Y(n7967) );
BUFX3TS U7448 ( .A(n6352), .Y(n7968) );
BUFX3TS U7449 ( .A(n8537), .Y(n7978) );
BUFX3TS U7450 ( .A(n6352), .Y(n7982) );
BUFX3TS U7451 ( .A(n8535), .Y(n7972) );
BUFX3TS U7452 ( .A(n8535), .Y(n7957) );
BUFX3TS U7453 ( .A(n8530), .Y(n7971) );
BUFX3TS U7454 ( .A(n6352), .Y(n7984) );
BUFX3TS U7455 ( .A(n8529), .Y(n7964) );
BUFX3TS U7456 ( .A(n7957), .Y(n7960) );
BUFX3TS U7457 ( .A(n7986), .Y(n7981) );
BUFX3TS U7458 ( .A(n8534), .Y(n7961) );
CLKBUFX3TS U7459 ( .A(n6352), .Y(n7969) );
CLKBUFX3TS U7460 ( .A(n2369), .Y(n7962) );
BUFX3TS U7461 ( .A(n7955), .Y(n7956) );
BUFX3TS U7462 ( .A(n2347), .Y(n7977) );
BUFX3TS U7463 ( .A(n8537), .Y(n8541) );
CLKBUFX3TS U7464 ( .A(n8578), .Y(n7992) );
BUFX3TS U7465 ( .A(n8599), .Y(n8604) );
INVX2TS U7466 ( .A(n7876), .Y(n6355) );
OAI21X1TS U7467 ( .A0(n8038), .A1(n2220), .B0(n8078), .Y(n7619) );
BUFX3TS U7468 ( .A(n7634), .Y(n7631) );
OAI21X1TS U7469 ( .A0(n8122), .A1(n2216), .B0(n8121), .Y(n6866) );
OAI21X1TS U7470 ( .A0(n8040), .A1(n2221), .B0(n8103), .Y(n7610) );
BUFX3TS U7471 ( .A(n7634), .Y(n7604) );
OAI21X1TS U7472 ( .A0(n8039), .A1(n2217), .B0(n8132), .Y(n6870) );
OAI21X1TS U7473 ( .A0(n8039), .A1(n2222), .B0(n8092), .Y(n7616) );
OAI21X1TS U7474 ( .A0(n8038), .A1(n2215), .B0(n8108), .Y(n6871) );
OAI21X1TS U7475 ( .A0(n8040), .A1(n2216), .B0(n8138), .Y(n6868) );
OAI21X1TS U7476 ( .A0(n8128), .A1(n2217), .B0(n8127), .Y(n7613) );
OAI21X1TS U7477 ( .A0(n8041), .A1(n2220), .B0(n8079), .Y(n7607) );
OAI21X1TS U7478 ( .A0(n8041), .A1(n2215), .B0(n8107), .Y(n6865) );
OAI21X1TS U7479 ( .A0(n8004), .A1(n2221), .B0(n8111), .Y(n6861) );
INVX2TS U7480 ( .A(n7827), .Y(n6943) );
ADDHXLTS U7481 ( .A(n7780), .B(n7781), .CO(n5452), .S(n6357) );
OAI2BB1X1TS U7482 ( .A0N(n8043), .A1N(n6357), .B0(n8495), .Y(n6902) );
NAND2X1TS U7483 ( .A(n6921), .B(n6902), .Y(n8615) );
NAND2X1TS U7484 ( .A(n6939), .B(n6358), .Y(n8627) );
OAI2BB1X1TS U7485 ( .A0N(n8043), .A1N(n8494), .B0(n8493), .Y(n6537) );
NAND2X1TS U7486 ( .A(n6939), .B(n6537), .Y(n8616) );
INVX2TS U7487 ( .A(n6359), .Y(n6401) );
AOI21X1TS U7488 ( .A0(n6401), .A1(n6361), .B0(n6360), .Y(n6414) );
INVX2TS U7489 ( .A(n7192), .Y(n6364) );
NAND2X1TS U7490 ( .A(n6364), .B(n7191), .Y(n6370) );
INVX2TS U7491 ( .A(n6370), .Y(n6365) );
XNOR2X1TS U7492 ( .A(n6366), .B(n6365), .Y(n6374) );
INVX2TS U7493 ( .A(n6367), .Y(n6418) );
AOI21X1TS U7494 ( .A0(n6418), .A1(n6369), .B0(n6368), .Y(n7193) );
XOR2X1TS U7495 ( .A(n7193), .B(n6370), .Y(n6372) );
BUFX3TS U7496 ( .A(n6371), .Y(n7197) );
AOI22X1TS U7497 ( .A0(n6372), .A1(n7197), .B0(FPADDSUB_Raw_mant_NRM_SWR[8]),
.B1(n7196), .Y(n6373) );
OAI2BB1X1TS U7498 ( .A0N(n6424), .A1N(n6374), .B0(n6373), .Y(n1343) );
INVX2TS U7499 ( .A(n6375), .Y(n7157) );
INVX2TS U7500 ( .A(n6403), .Y(n6378) );
NAND2X1TS U7501 ( .A(n6378), .B(n6402), .Y(n6382) );
INVX2TS U7502 ( .A(n6382), .Y(n6379) );
XNOR2X1TS U7503 ( .A(n6380), .B(n6379), .Y(n6385) );
XOR2X1TS U7504 ( .A(n6404), .B(n6382), .Y(n6383) );
AOI22X1TS U7505 ( .A0(n6383), .A1(n7197), .B0(FPADDSUB_Raw_mant_NRM_SWR[4]),
.B1(n7196), .Y(n6384) );
OAI2BB1X1TS U7506 ( .A0N(n6424), .A1N(n6385), .B0(n6384), .Y(n1347) );
INVX2TS U7507 ( .A(n6386), .Y(n6389) );
INVX2TS U7508 ( .A(n6387), .Y(n6388) );
AOI21X1TS U7509 ( .A0(n6401), .A1(n6389), .B0(n6388), .Y(n6392) );
INVX2TS U7510 ( .A(n6390), .Y(n6417) );
NAND2X1TS U7511 ( .A(n6417), .B(n6415), .Y(n6393) );
INVX2TS U7512 ( .A(n6393), .Y(n6391) );
XNOR2X1TS U7513 ( .A(n6418), .B(n6393), .Y(n6394) );
AOI22X1TS U7514 ( .A0(n6394), .A1(n7197), .B0(FPADDSUB_Raw_mant_NRM_SWR[6]),
.B1(n7196), .Y(n6395) );
OAI2BB1X1TS U7515 ( .A0N(n6424), .A1N(n6396), .B0(n6395), .Y(n1345) );
INVX2TS U7516 ( .A(n6397), .Y(n6399) );
NAND2X1TS U7517 ( .A(n6399), .B(n6398), .Y(n6405) );
INVX2TS U7518 ( .A(n6405), .Y(n6400) );
XNOR2X1TS U7519 ( .A(n6401), .B(n6400), .Y(n6409) );
XNOR2X1TS U7520 ( .A(n6406), .B(n6405), .Y(n6407) );
AOI22X1TS U7521 ( .A0(n6407), .A1(n7138), .B0(FPADDSUB_Raw_mant_NRM_SWR[5]),
.B1(n7196), .Y(n6408) );
OAI2BB1X1TS U7522 ( .A0N(n6424), .A1N(n6409), .B0(n6408), .Y(n1346) );
INVX2TS U7523 ( .A(n6410), .Y(n6412) );
NAND2X1TS U7524 ( .A(n6412), .B(n6411), .Y(n6419) );
INVX2TS U7525 ( .A(n6419), .Y(n6413) );
INVX2TS U7526 ( .A(n6415), .Y(n6416) );
AOI21X1TS U7527 ( .A0(n6418), .A1(n6417), .B0(n6416), .Y(n6420) );
XOR2X1TS U7528 ( .A(n6420), .B(n6419), .Y(n6421) );
AOI22X1TS U7529 ( .A0(n6421), .A1(n7197), .B0(FPADDSUB_Raw_mant_NRM_SWR[7]),
.B1(n7196), .Y(n6422) );
OAI2BB1X1TS U7530 ( .A0N(n6424), .A1N(n6423), .B0(n6422), .Y(n1344) );
INVX2TS U7531 ( .A(n1664), .Y(n6425) );
AND4X1TS U7532 ( .A(n7689), .B(n6426), .C(n7690), .D(n6425), .Y(n8064) );
AOI22X1TS U7533 ( .A0(n6540), .A1(FPMULT_Add_result[8]), .B0(
FPMULT_Sgf_normalized_result[7]), .B1(n6539), .Y(n6427) );
OAI2BB1X1TS U7534 ( .A0N(n2444), .A1N(n1584), .B0(n6427), .Y(n6428) );
AOI21X1TS U7535 ( .A0(n2411), .A1(FPMULT_Add_result[7]), .B0(n6428), .Y(
n6429) );
OAI2BB1X1TS U7536 ( .A0N(n2416), .A1N(n1583), .B0(n6429), .Y(n1524) );
AOI22X1TS U7537 ( .A0(n2380), .A1(FPMULT_Add_result[7]), .B0(
FPMULT_Sgf_normalized_result[6]), .B1(n6440), .Y(n6430) );
OAI2BB1X1TS U7538 ( .A0N(n2444), .A1N(n1583), .B0(n6430), .Y(n6431) );
AOI21X1TS U7539 ( .A0(n2411), .A1(FPMULT_Add_result[6]), .B0(n6431), .Y(
n6432) );
OAI2BB1X1TS U7540 ( .A0N(n5768), .A1N(n1582), .B0(n6432), .Y(n1523) );
AOI222X1TS U7541 ( .A0(n8153), .A1(n7996), .B0(n8152), .B1(n8018), .C0(n7997), .C1(n8151), .Y(n6433) );
INVX2TS U7542 ( .A(n6433), .Y(n1419) );
AOI222X1TS U7543 ( .A0(n8143), .A1(n7996), .B0(n8142), .B1(n8018), .C0(n7997), .C1(n8141), .Y(n6434) );
INVX2TS U7544 ( .A(n6434), .Y(n1467) );
INVX2TS U7545 ( .A(n6435), .Y(n8762) );
OAI222X4TS U7546 ( .A0(n2214), .A1(n8030), .B0(n8083), .B1(n8056), .C0(n8008), .C1(n2219), .Y(n7507) );
INVX2TS U7547 ( .A(n7507), .Y(n8755) );
OAI222X4TS U7548 ( .A0(n2214), .A1(n8031), .B0(n8085), .B1(n8056), .C0(n8001), .C1(n2219), .Y(n7509) );
INVX2TS U7549 ( .A(n7509), .Y(n8756) );
INVX2TS U7550 ( .A(n7661), .Y(n7512) );
INVX2TS U7551 ( .A(n1467), .Y(n7499) );
NAND2X1TS U7552 ( .A(n1419), .B(n7499), .Y(n7498) );
INVX2TS U7553 ( .A(n7498), .Y(n7496) );
NOR2X1TS U7554 ( .A(n8762), .B(n7507), .Y(n7494) );
OAI22X1TS U7555 ( .A0(n7496), .A1(n7494), .B0(n6435), .B1(n8755), .Y(n6445)
);
OAI222X4TS U7556 ( .A0(n2220), .A1(n8031), .B0(n8096), .B1(n8056), .C0(n8001), .C1(n2217), .Y(n6444) );
NAND2X1TS U7557 ( .A(n6444), .B(n8756), .Y(n6446) );
XNOR2X1TS U7558 ( .A(n6445), .B(n6436), .Y(n6437) );
NOR3XLTS U7559 ( .A(FPSENCOS_inst_CORDIC_FSM_v3_state_reg[2]), .B(n7818),
.C(n6646), .Y(n6438) );
INVX2TS U7560 ( .A(n8736), .Y(n8738) );
AOI22X1TS U7561 ( .A0(n5774), .A1(FPMULT_Add_result[9]), .B0(
FPMULT_Sgf_normalized_result[8]), .B1(n6907), .Y(n6441) );
OAI2BB1X1TS U7562 ( .A0N(n2446), .A1N(n1585), .B0(n6441), .Y(n6442) );
AOI21X1TS U7563 ( .A0(n2411), .A1(FPMULT_Add_result[8]), .B0(n6442), .Y(
n6443) );
OAI2BB1X1TS U7564 ( .A0N(n5768), .A1N(n1584), .B0(n6443), .Y(n1525) );
INVX2TS U7565 ( .A(n6444), .Y(n8764) );
INVX2TS U7566 ( .A(n7501), .Y(n8765) );
AOI22X1TS U7567 ( .A0(n7509), .A1(n8764), .B0(n6446), .B1(n6445), .Y(n7502)
);
OAI222X4TS U7568 ( .A0(n2216), .A1(n8032), .B0(n8084), .B1(n8056), .C0(n8002), .C1(n2222), .Y(n7510) );
NOR2X1TS U7569 ( .A(n8765), .B(n7510), .Y(n7503) );
AOI21X1TS U7570 ( .A0(n7510), .A1(n8765), .B0(n7503), .Y(n6447) );
XNOR2X1TS U7571 ( .A(n7502), .B(n6447), .Y(n6448) );
BUFX3TS U7572 ( .A(n6449), .Y(n6604) );
NAND2X1TS U7573 ( .A(n2431), .B(n6491), .Y(n6456) );
OAI21X1TS U7574 ( .A0(n6453), .A1(n6452), .B0(n6451), .Y(n6493) );
INVX2TS U7575 ( .A(n6493), .Y(n6478) );
INVX2TS U7576 ( .A(n6478), .Y(n6454) );
AOI21X1TS U7577 ( .A0(n2432), .A1(n6491), .B0(n6454), .Y(n6455) );
OAI21X1TS U7578 ( .A0(n6604), .A1(n6456), .B0(n6455), .Y(n6457) );
XOR2X1TS U7579 ( .A(n6457), .B(n7742), .Y(n6458) );
OAI2BB1X1TS U7580 ( .A0N(n8507), .A1N(n6458), .B0(n8506), .Y(n6883) );
AOI22X1TS U7581 ( .A0(n5774), .A1(FPMULT_Add_result[15]), .B0(
FPMULT_Sgf_normalized_result[14]), .B1(n6907), .Y(n6459) );
OAI2BB1X1TS U7582 ( .A0N(n6883), .A1N(n2446), .B0(n6459), .Y(n6460) );
AOI21X1TS U7583 ( .A0(n2411), .A1(FPMULT_Add_result[14]), .B0(n6460), .Y(
n6461) );
OAI2BB1X1TS U7584 ( .A0N(n6884), .A1N(n2416), .B0(n6461), .Y(n1531) );
INVX2TS U7585 ( .A(n6491), .Y(n6477) );
NOR2X1TS U7586 ( .A(n6477), .B(n7765), .Y(n6463) );
NAND2X1TS U7587 ( .A(n6603), .B(n6463), .Y(n6465) );
AOI21X1TS U7588 ( .A0(n6609), .A1(n6463), .B0(n6462), .Y(n6464) );
XNOR2X1TS U7589 ( .A(n6466), .B(n7741), .Y(n6467) );
OAI2BB1X1TS U7590 ( .A0N(n2199), .A1N(n6467), .B0(n8512), .Y(n6888) );
NOR2X1TS U7591 ( .A(n6477), .B(n7764), .Y(n6469) );
NAND2X1TS U7592 ( .A(n2431), .B(n6469), .Y(n6471) );
AOI21X1TS U7593 ( .A0(n2432), .A1(n6469), .B0(n6468), .Y(n6470) );
XNOR2X1TS U7594 ( .A(n6472), .B(n7739), .Y(n6473) );
OAI2BB1X1TS U7595 ( .A0N(n2199), .A1N(n6473), .B0(n8511), .Y(n6887) );
AOI22X1TS U7596 ( .A0(n5774), .A1(FPMULT_Add_result[17]), .B0(
FPMULT_Sgf_normalized_result[16]), .B1(n6440), .Y(n6474) );
OAI2BB1X1TS U7597 ( .A0N(n6887), .A1N(n2444), .B0(n6474), .Y(n6475) );
AOI21X1TS U7598 ( .A0(n6544), .A1(FPMULT_Add_result[16]), .B0(n6475), .Y(
n6476) );
OAI2BB1X1TS U7599 ( .A0N(n6888), .A1N(n5768), .B0(n6476), .Y(n1533) );
NOR2X1TS U7600 ( .A(n7763), .B(n6477), .Y(n6480) );
NAND2X1TS U7601 ( .A(n2431), .B(n6480), .Y(n6482) );
AOI21X1TS U7602 ( .A0(n6609), .A1(n6480), .B0(n6479), .Y(n6481) );
XNOR2X1TS U7603 ( .A(n6483), .B(n7735), .Y(n6484) );
OAI2BB1X1TS U7604 ( .A0N(n2199), .A1N(n6484), .B0(n8516), .Y(n6891) );
AOI22X1TS U7605 ( .A0(n6540), .A1(FPMULT_Add_result[18]), .B0(
FPMULT_Sgf_normalized_result[17]), .B1(n6907), .Y(n6485) );
OAI2BB1X1TS U7606 ( .A0N(n6891), .A1N(n2445), .B0(n6485), .Y(n6486) );
AOI21X1TS U7607 ( .A0(n2411), .A1(FPMULT_Add_result[17]), .B0(n6486), .Y(
n6487) );
OAI2BB1X1TS U7608 ( .A0N(n6887), .A1N(n2416), .B0(n6487), .Y(n1534) );
AOI22X1TS U7609 ( .A0(n6540), .A1(FPMULT_Add_result[16]), .B0(
FPMULT_Sgf_normalized_result[15]), .B1(n6539), .Y(n6488) );
OAI2BB1X1TS U7610 ( .A0N(n6888), .A1N(n2446), .B0(n6488), .Y(n6489) );
AOI21X1TS U7611 ( .A0(n6544), .A1(FPMULT_Add_result[15]), .B0(n6489), .Y(
n6490) );
OAI2BB1X1TS U7612 ( .A0N(n6883), .A1N(n5768), .B0(n6490), .Y(n1532) );
NAND2X2TS U7613 ( .A(n7762), .B(n6491), .Y(n6492) );
INVX2TS U7614 ( .A(n6492), .Y(n6496) );
NAND2X1TS U7615 ( .A(n2431), .B(n6496), .Y(n6498) );
NAND2X1TS U7616 ( .A(n7762), .B(n6493), .Y(n6494) );
INVX2TS U7617 ( .A(n6606), .Y(n6495) );
AOI21X1TS U7618 ( .A0(n2432), .A1(n6496), .B0(n6495), .Y(n6497) );
XNOR2X1TS U7619 ( .A(n6499), .B(n2246), .Y(n6500) );
OAI2BB1X1TS U7620 ( .A0N(n2199), .A1N(n6500), .B0(n8509), .Y(n6885) );
NOR2X1TS U7621 ( .A(n6492), .B(n2246), .Y(n6502) );
NAND2X1TS U7622 ( .A(n6502), .B(n2431), .Y(n6504) );
AOI21X1TS U7623 ( .A0(n2432), .A1(n6502), .B0(n6501), .Y(n6503) );
XNOR2X1TS U7624 ( .A(n6505), .B(n7738), .Y(n6506) );
OAI2BB1X1TS U7625 ( .A0N(n2199), .A1N(n6506), .B0(n8514), .Y(n6890) );
INVX2TS U7626 ( .A(n6507), .Y(n6907) );
AOI22X1TS U7627 ( .A0(n6540), .A1(FPMULT_Add_result[20]), .B0(
FPMULT_Sgf_normalized_result[19]), .B1(n6440), .Y(n6508) );
OAI2BB1X1TS U7628 ( .A0N(n6890), .A1N(n2445), .B0(n6508), .Y(n6509) );
AOI21X1TS U7629 ( .A0(n2411), .A1(FPMULT_Add_result[19]), .B0(n6509), .Y(
n6510) );
OAI2BB1X1TS U7630 ( .A0N(n6885), .A1N(n2416), .B0(n6510), .Y(n1536) );
NOR2X1TS U7631 ( .A(n6492), .B(n7761), .Y(n6512) );
NAND2X1TS U7632 ( .A(n6512), .B(n2431), .Y(n6514) );
AOI21X1TS U7633 ( .A0(n2432), .A1(n6512), .B0(n6511), .Y(n6513) );
XNOR2X1TS U7634 ( .A(n6515), .B(n7740), .Y(n6516) );
OAI2BB1X1TS U7635 ( .A0N(n2199), .A1N(n6516), .B0(n8510), .Y(n6886) );
AOI22X1TS U7636 ( .A0(n5774), .A1(FPMULT_Add_result[21]), .B0(
FPMULT_Sgf_normalized_result[20]), .B1(n6539), .Y(n6517) );
OAI2BB1X1TS U7637 ( .A0N(n6886), .A1N(n2446), .B0(n6517), .Y(n6518) );
AOI21X1TS U7638 ( .A0(n6544), .A1(FPMULT_Add_result[20]), .B0(n6518), .Y(
n6519) );
OAI2BB1X1TS U7639 ( .A0N(n6890), .A1N(n5768), .B0(n6519), .Y(n1537) );
NOR2X1TS U7640 ( .A(n6492), .B(n7760), .Y(n6521) );
NAND2X1TS U7641 ( .A(n6521), .B(n6603), .Y(n6523) );
AOI21X1TS U7642 ( .A0(n6609), .A1(n6521), .B0(n6520), .Y(n6522) );
XNOR2X1TS U7643 ( .A(n6524), .B(n7737), .Y(n6525) );
OAI2BB1X1TS U7644 ( .A0N(n2198), .A1N(n6525), .B0(n8513), .Y(n6889) );
AOI22X1TS U7645 ( .A0(n6540), .A1(n6537), .B0(
FPMULT_Sgf_normalized_result[21]), .B1(n6539), .Y(n6526) );
OAI2BB1X1TS U7646 ( .A0N(n6889), .A1N(n2444), .B0(n6526), .Y(n6527) );
AOI21X1TS U7647 ( .A0(n2411), .A1(FPMULT_Add_result[21]), .B0(n6527), .Y(
n6528) );
OAI2BB1X1TS U7648 ( .A0N(n6886), .A1N(n2416), .B0(n6528), .Y(n1538) );
NOR2X1TS U7649 ( .A(n6492), .B(n7759), .Y(n6530) );
NAND2X1TS U7650 ( .A(n6530), .B(n6603), .Y(n6532) );
AOI21X1TS U7651 ( .A0(n6609), .A1(n6530), .B0(n6529), .Y(n6531) );
XNOR2X1TS U7652 ( .A(n6533), .B(n7736), .Y(n6534) );
OAI2BB1X1TS U7653 ( .A0N(n2198), .A1N(n6534), .B0(n8515), .Y(n6903) );
AOI22X1TS U7654 ( .A0(n5774), .A1(n6902), .B0(
FPMULT_Sgf_normalized_result[22]), .B1(n6907), .Y(n6535) );
OAI2BB1X1TS U7655 ( .A0N(n6903), .A1N(n2445), .B0(n6535), .Y(n6536) );
AOI21X1TS U7656 ( .A0(n6544), .A1(n6537), .B0(n6536), .Y(n6538) );
OAI2BB1X1TS U7657 ( .A0N(n6889), .A1N(n5768), .B0(n6538), .Y(n1539) );
AOI22X1TS U7658 ( .A0(n5774), .A1(FPMULT_Add_result[19]), .B0(
FPMULT_Sgf_normalized_result[18]), .B1(n6440), .Y(n6541) );
OAI2BB1X1TS U7659 ( .A0N(n6885), .A1N(n2444), .B0(n6541), .Y(n6543) );
AOI21X1TS U7660 ( .A0(n6544), .A1(FPMULT_Add_result[18]), .B0(n6543), .Y(
n6545) );
OAI2BB1X1TS U7661 ( .A0N(n6891), .A1N(n2416), .B0(n6545), .Y(n1535) );
NAND2X2TS U7662 ( .A(n6559), .B(n7809), .Y(n7329) );
INVX2TS U7663 ( .A(n7329), .Y(n7309) );
INVX2TS U7664 ( .A(n7323), .Y(n6636) );
AOI22X1TS U7665 ( .A0(FPSENCOS_d_ff3_LUT_out[1]), .A1(n7325), .B0(n7309),
.B1(n7311), .Y(n6549) );
OAI2BB1X1TS U7666 ( .A0N(n7318), .A1N(n6636), .B0(n7364), .Y(n6656) );
NAND2X1TS U7667 ( .A(n6549), .B(n6656), .Y(n2134) );
BUFX3TS U7668 ( .A(n6559), .Y(n7361) );
BUFX3TS U7669 ( .A(n7424), .Y(n7428) );
NOR2X2TS U7670 ( .A(FPSENCOS_d_ff2_Y[27]), .B(intadd_9_n1), .Y(n7418) );
NAND2X1TS U7671 ( .A(n7418), .B(n8679), .Y(n7421) );
AOI22X1TS U7672 ( .A0(n2211), .A1(n8467), .B0(n2291), .B1(n8466), .Y(n6552)
);
AOI22X1TS U7673 ( .A0(n2293), .A1(n8050), .B0(n2471), .B1(n8049), .Y(n6551)
);
AOI22X1TS U7674 ( .A0(n2210), .A1(n8473), .B0(n2405), .B1(n8472), .Y(n6554)
);
AOI22X1TS U7675 ( .A0(n2375), .A1(n8045), .B0(n2471), .B1(n8048), .Y(n6553)
);
AOI22X1TS U7676 ( .A0(n1810), .A1(n2443), .B0(n1802), .B1(n2396), .Y(n6556)
);
AOI22X1TS U7677 ( .A0(n1806), .A1(n2397), .B0(FPADDSUB_Data_array_SWR_3__25_), .B1(n2381), .Y(n6555) );
NAND2X1TS U7678 ( .A(n6556), .B(n6555), .Y(n7044) );
AOI22X1TS U7679 ( .A0(n1809), .A1(n2443), .B0(n1801), .B1(n2396), .Y(n6558)
);
AOI22X1TS U7680 ( .A0(n1805), .A1(n2398), .B0(n1813), .B1(n2381), .Y(n6557)
);
NAND2X1TS U7681 ( .A(n6558), .B(n6557), .Y(n7045) );
AOI221X1TS U7682 ( .A0(FPADDSUB_left_right_SHT2), .A1(n7044), .B0(n2344),
.B1(n7045), .C0(n7052), .Y(n7556) );
MXI2X1TS U7683 ( .A(n7556), .B(n7914), .S0(n7515), .Y(n1195) );
BUFX3TS U7684 ( .A(n6559), .Y(n7355) );
INVX2TS U7685 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[2]), .Y(n6568) );
INVX2TS U7686 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .Y(n6561) );
NOR2BX1TS U7687 ( .AN(n6564), .B(FPADDSUB_exp_rslt_NRM2_EW1[6]), .Y(n6565)
);
NOR2BX2TS U7688 ( .AN(n6565), .B(FPADDSUB_exp_rslt_NRM2_EW1[7]), .Y(n6566)
);
NAND2BX4TS U7689 ( .AN(n6806), .B(n6566), .Y(n7520) );
CLKBUFX3TS U7690 ( .A(n2348), .Y(n7980) );
CLKBUFX3TS U7691 ( .A(n2418), .Y(n7954) );
CLKBUFX3TS U7692 ( .A(n8546), .Y(n7958) );
CLKBUFX3TS U7693 ( .A(n2348), .Y(n8536) );
BUFX3TS U7694 ( .A(n2348), .Y(n8533) );
CLKBUFX3TS U7695 ( .A(n7983), .Y(n8530) );
BUFX3TS U7696 ( .A(n2470), .Y(n8560) );
BUFX3TS U7697 ( .A(n2470), .Y(n8557) );
CLKBUFX3TS U7698 ( .A(n8594), .Y(n8563) );
BUFX3TS U7699 ( .A(n2470), .Y(n8553) );
BUFX3TS U7700 ( .A(n2470), .Y(n8556) );
CLKBUFX3TS U7701 ( .A(n8547), .Y(n7953) );
BUFX3TS U7702 ( .A(n8529), .Y(n7952) );
INVX2TS U7703 ( .A(n7575), .Y(n8763) );
NAND2X1TS U7704 ( .A(n6943), .B(FPMULT_Add_result[0]), .Y(n6569) );
AOI22X1TS U7705 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[0]), .B0(n7289), .B1(n8642),
.Y(FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_) );
INVX2TS U7706 ( .A(FPADDSUB_inst_FSM_INPUT_ENABLE_state_next_1_), .Y(n8282)
);
AOI22X1TS U7707 ( .A0(n6857), .A1(FPADDSUB_Raw_mant_NRM_SWR[22]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[20]), .B1(n8526), .Y(n6571) );
OAI21X1TS U7708 ( .A0(n2334), .A1(n6832), .B0(n6571), .Y(n8719) );
AOI22X1TS U7709 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[10]), .A1(n6857), .B0(
FPADDSUB_DmP_mant_SHT1_SW[8]), .B1(n7301), .Y(n6572) );
OAI21X1TS U7710 ( .A0(n7940), .A1(n6832), .B0(n6572), .Y(n8737) );
NAND2X1TS U7711 ( .A(n6838), .B(FPADDSUB_Raw_mant_NRM_SWR[2]), .Y(n6575) );
NAND2X1TS U7712 ( .A(n6576), .B(FPADDSUB_Raw_mant_NRM_SWR[23]), .Y(n6574) );
INVX2TS U7713 ( .A(n8741), .Y(n8739) );
INVX2TS U7714 ( .A(n8751), .Y(n8744) );
INVX2TS U7715 ( .A(n8745), .Y(n8742) );
INVX2TS U7716 ( .A(n8726), .Y(n8724) );
INVX2TS U7717 ( .A(n8720), .Y(n8718) );
INVX2TS U7718 ( .A(n8716), .Y(n8712) );
INVX2TS U7719 ( .A(n8723), .Y(n8721) );
INVX2TS U7720 ( .A(n8717), .Y(n8715) );
AOI22X1TS U7721 ( .A0(n6882), .A1(FPADDSUB_Raw_mant_NRM_SWR[17]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[6]), .B1(n2358), .Y(n6577) );
OAI21X1TS U7722 ( .A0(n7793), .A1(n6855), .B0(n6577), .Y(n8740) );
AOI22X1TS U7723 ( .A0(n6641), .A1(FPADDSUB_Raw_mant_NRM_SWR[19]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[4]), .B1(n2358), .Y(n6578) );
OAI21X1TS U7724 ( .A0(n7810), .A1(n6855), .B0(n6578), .Y(n8743) );
AOI22X1TS U7725 ( .A0(n6882), .A1(FPADDSUB_Raw_mant_NRM_SWR[21]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[2]), .B1(n2358), .Y(n6579) );
OAI21X1TS U7726 ( .A0(n7816), .A1(n6855), .B0(n6579), .Y(n8747) );
AOI22X1TS U7727 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[13]), .A1(n6641), .B0(
FPADDSUB_DmP_mant_SHT1_SW[10]), .B1(n7301), .Y(n6580) );
OAI21X1TS U7728 ( .A0(n7867), .A1(n6855), .B0(n6580), .Y(n8734) );
INVX2TS U7729 ( .A(n8727), .Y(n8729) );
AOI22X1TS U7730 ( .A0(n6576), .A1(FPADDSUB_Raw_mant_NRM_SWR[7]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[16]), .B1(n2358), .Y(n6582) );
OAI21X1TS U7731 ( .A0(n6855), .A1(n7821), .B0(n6582), .Y(n8725) );
AOI22X1TS U7732 ( .A0(FPADDSUB_Raw_mant_NRM_SWR[9]), .A1(n6882), .B0(
FPADDSUB_DmP_mant_SHT1_SW[14]), .B1(n7301), .Y(n6583) );
OAI21X1TS U7733 ( .A0(n7823), .A1(n6855), .B0(n6583), .Y(n8728) );
AOI22X1TS U7734 ( .A0(n2489), .A1(n6576), .B0(FPADDSUB_DmP_mant_SHT1_SW[12]),
.B1(n7301), .Y(n6584) );
OAI21X1TS U7735 ( .A0(n7807), .A1(n6855), .B0(n6584), .Y(n8731) );
AOI22X1TS U7736 ( .A0(FPADDSUB_inst_FSM_INPUT_ENABLE_state_reg[1]), .A1(
n7820), .B0(n6585), .B1(n8642), .Y(n6586) );
INVX2TS U7737 ( .A(n6588), .Y(overflow_flag) );
NAND2X1TS U7738 ( .A(n6591), .B(n6590), .Y(n6594) );
INVX2TS U7739 ( .A(n6594), .Y(n6592) );
XOR2X1TS U7740 ( .A(n6595), .B(n6594), .Y(n6596) );
AOI22X1TS U7741 ( .A0(n6596), .A1(n6371), .B0(FPADDSUB_Raw_mant_NRM_SWR[15]),
.B1(n7599), .Y(n6597) );
OAI2BB1X1TS U7742 ( .A0N(n6599), .A1N(n6598), .B0(n6597), .Y(n1336) );
INVX2TS U7743 ( .A(n8299), .Y(n6600) );
NAND3X1TS U7744 ( .A(FPSENCOS_cont_var_out[1]), .B(ready_add_subt), .C(n7819), .Y(n7343) );
BUFX3TS U7745 ( .A(n7343), .Y(n7437) );
INVX2TS U7746 ( .A(n7510), .Y(n8757) );
INVX2TS U7747 ( .A(n7477), .Y(n7480) );
NOR2X1TS U7748 ( .A(n6492), .B(n7758), .Y(n6608) );
NAND2X1TS U7749 ( .A(n6608), .B(n6603), .Y(n6605) );
AOI21X1TS U7750 ( .A0(n6609), .A1(n6608), .B0(n6607), .Y(n6610) );
NAND2X1TS U7751 ( .A(n6611), .B(n6610), .Y(n6612) );
XNOR2X1TS U7752 ( .A(n6612), .B(n7734), .Y(n6613) );
OAI31X1TS U7753 ( .A0(n7480), .A1(n7827), .A2(n7791), .B0(n6621), .Y(n1550)
);
INVX2TS U7754 ( .A(n6632), .Y(n7319) );
NAND2X1TS U7755 ( .A(n7309), .B(n7319), .Y(n6640) );
OAI2BB1X1TS U7756 ( .A0N(ack_operation), .A1N(n6624), .B0(n7296), .Y(n6615)
);
NAND2X1TS U7757 ( .A(n6616), .B(n6615), .Y(n6653) );
AOI211X1TS U7758 ( .A0(FPMULT_FSM_selector_B[0]), .A1(n6621), .B0(n7480),
.C0(n7827), .Y(n6622) );
INVX2TS U7759 ( .A(n6622), .Y(n1551) );
BUFX3TS U7760 ( .A(n6661), .Y(n6713) );
AOI22X1TS U7761 ( .A0(n6623), .A1(cordic_result[8]), .B0(n6711), .B1(
mult_result[8]), .Y(n6625) );
AOI22X1TS U7762 ( .A0(n6623), .A1(cordic_result[4]), .B0(n6711), .B1(
mult_result[4]), .Y(n6626) );
AOI22X1TS U7763 ( .A0(n7299), .A1(cordic_result[3]), .B0(n6711), .B1(
mult_result[3]), .Y(n6627) );
AOI22X1TS U7764 ( .A0(n6623), .A1(cordic_result[9]), .B0(n6711), .B1(
mult_result[9]), .Y(n6628) );
AOI22X1TS U7765 ( .A0(n6623), .A1(cordic_result[7]), .B0(n6711), .B1(
mult_result[7]), .Y(n6629) );
AOI22X1TS U7766 ( .A0(n6623), .A1(cordic_result[5]), .B0(n6711), .B1(
mult_result[5]), .Y(n6630) );
AOI22X1TS U7767 ( .A0(n6623), .A1(cordic_result[6]), .B0(n6711), .B1(
mult_result[6]), .Y(n6631) );
NAND2X2TS U7768 ( .A(n7424), .B(FPSENCOS_cont_iter_out[1]), .Y(n7322) );
AOI211X1TS U7769 ( .A0(n7303), .A1(n7790), .B0(n2196), .C0(n7329), .Y(n7316)
);
AOI21X1TS U7770 ( .A0(FPSENCOS_d_ff3_LUT_out[0]), .A1(n7330), .B0(n7316),
.Y(n6633) );
AOI21X1TS U7771 ( .A0(n7303), .A1(n2196), .B0(FPSENCOS_cont_iter_out[3]),
.Y(n6638) );
AOI22X1TS U7772 ( .A0(FPSENCOS_d_ff3_LUT_out[4]), .A1(n7325), .B0(n7309),
.B1(n6638), .Y(n6634) );
NOR3X1TS U7773 ( .A(n2196), .B(n2361), .C(n7322), .Y(n6658) );
AOI21X1TS U7774 ( .A0(FPSENCOS_d_ff3_LUT_out[2]), .A1(n7330), .B0(n6658),
.Y(n6635) );
NAND2X1TS U7775 ( .A(n7364), .B(n2360), .Y(n7327) );
INVX2TS U7776 ( .A(n8730), .Y(n8732) );
AOI22X1TS U7777 ( .A0(n7409), .A1(n6638), .B0(FPSENCOS_d_ff3_LUT_out[26]),
.B1(n7330), .Y(n6639) );
INVX2TS U7778 ( .A(n7322), .Y(n7314) );
NAND2X1TS U7779 ( .A(n7314), .B(n7311), .Y(n7317) );
INVX2TS U7780 ( .A(n8733), .Y(n8735) );
NAND2X1TS U7781 ( .A(n7303), .B(n7796), .Y(intadd_9_CI) );
INVX2TS U7782 ( .A(n7327), .Y(n6643) );
AOI22X1TS U7783 ( .A0(FPSENCOS_d_ff2_Y[23]), .A1(n6643), .B0(
FPSENCOS_d_ff3_sh_y_out[23]), .B1(n7330), .Y(n6642) );
AOI22X1TS U7784 ( .A0(FPSENCOS_d_ff2_X[23]), .A1(n6643), .B0(
FPSENCOS_d_ff3_sh_x_out[23]), .B1(n7330), .Y(n6644) );
BUFX3TS U7785 ( .A(n7308), .Y(n7337) );
INVX2TS U7786 ( .A(operation[0]), .Y(n6648) );
OAI32X1TS U7787 ( .A0(n7333), .A1(n6648), .A2(n6647), .B0(n7789), .B1(n7337),
.Y(n2082) );
AOI211XLTS U7788 ( .A0(n6945), .A1(n7478), .B0(n6651), .C0(n6650), .Y(n6652)
);
NAND2X1TS U7789 ( .A(n7314), .B(n7319), .Y(n7320) );
NAND2X1TS U7790 ( .A(n7303), .B(n7319), .Y(n6654) );
AOI22X1TS U7791 ( .A0(FPSENCOS_d_ff3_LUT_out[24]), .A1(n7325), .B0(n7309),
.B1(n6654), .Y(n6655) );
AOI22X1TS U7792 ( .A0(n6623), .A1(cordic_result[2]), .B0(n6624), .B1(
mult_result[2]), .Y(n6657) );
AOI211X1TS U7793 ( .A0(FPSENCOS_d_ff3_LUT_out[6]), .A1(n7325), .B0(n6659),
.C0(n6658), .Y(n6660) );
OAI31X1TS U7794 ( .A0(n7303), .A1(FPSENCOS_cont_iter_out[3]), .A2(n7329),
.B0(n6660), .Y(n2129) );
BUFX3TS U7795 ( .A(n6661), .Y(n6717) );
AOI22X1TS U7796 ( .A0(cordic_result[27]), .A1(n7294), .B0(n7293), .B1(
mult_result[27]), .Y(n6662) );
AOI22X1TS U7797 ( .A0(n7294), .A1(cordic_result[24]), .B0(n7293), .B1(
mult_result[24]), .Y(n6663) );
AOI22X1TS U7798 ( .A0(n7294), .A1(cordic_result[28]), .B0(n7293), .B1(
mult_result[28]), .Y(n6664) );
AOI22X1TS U7799 ( .A0(cordic_result[26]), .A1(n7294), .B0(n7293), .B1(
mult_result[26]), .Y(n6665) );
AOI22X1TS U7800 ( .A0(cordic_result[31]), .A1(n7294), .B0(n7293), .B1(
mult_result[31]), .Y(n6666) );
AOI22X1TS U7801 ( .A0(n7294), .A1(cordic_result[22]), .B0(n6714), .B1(
mult_result[22]), .Y(n6667) );
INVX2TS U7802 ( .A(n7434), .Y(n8636) );
AOI21X1TS U7803 ( .A0(n7856), .A1(n7799), .B0(n6668), .Y(n6689) );
OAI22X1TS U7804 ( .A0(n7797), .A1(n6669), .B0(n6695), .B1(n2334), .Y(n6670)
);
AOI22X1TS U7805 ( .A0(n6675), .A1(FPADDSUB_Raw_mant_NRM_SWR[5]), .B0(n6674),
.B1(n6673), .Y(n6676) );
INVX1TS U7806 ( .A(FPADDSUB_Raw_mant_NRM_SWR[0]), .Y(n7152) );
AOI32X1TS U7807 ( .A0(n2294), .A1(n6676), .A2(n7152), .B0(n6695), .B1(n6676),
.Y(n6677) );
AOI211X1TS U7808 ( .A0(n6679), .A1(FPADDSUB_Raw_mant_NRM_SWR[4]), .B0(n6678),
.C0(n6677), .Y(n6682) );
INVX2TS U7809 ( .A(n6863), .Y(n8609) );
NAND2X1TS U7810 ( .A(n6699), .B(FPADDSUB_LZD_output_NRM2_EW[2]), .Y(n6683)
);
AOI22X1TS U7811 ( .A0(n7299), .A1(cordic_result[10]), .B0(n6711), .B1(
mult_result[10]), .Y(n6685) );
AOI22X1TS U7812 ( .A0(n7299), .A1(cordic_result[0]), .B0(n6624), .B1(
mult_result[0]), .Y(n6686) );
AOI22X1TS U7813 ( .A0(n7299), .A1(cordic_result[11]), .B0(n6711), .B1(
mult_result[11]), .Y(n6687) );
AOI22X1TS U7814 ( .A0(n7299), .A1(cordic_result[1]), .B0(n6624), .B1(
mult_result[1]), .Y(n6688) );
INVX2TS U7815 ( .A(n6689), .Y(n6690) );
INVX2TS U7816 ( .A(n6692), .Y(n6694) );
OAI31X1TS U7817 ( .A0(n6695), .A1(n6694), .A2(n2294), .B0(n6693), .Y(n6696)
);
INVX2TS U7818 ( .A(n7377), .Y(n8817) );
INVX2TS U7819 ( .A(n7371), .Y(n8790) );
INVX2TS U7820 ( .A(n7370), .Y(n8793) );
INVX2TS U7821 ( .A(n7398), .Y(n8787) );
INVX2TS U7822 ( .A(n7368), .Y(n8799) );
INVX2TS U7823 ( .A(n7390), .Y(n8828) );
INVX2TS U7824 ( .A(n7391), .Y(n8826) );
INVX2TS U7825 ( .A(n6867), .Y(n8796) );
INVX2TS U7826 ( .A(n7392), .Y(n8830) );
INVX2TS U7827 ( .A(n7393), .Y(n8837) );
INVX2TS U7828 ( .A(n7395), .Y(n8786) );
INVX2TS U7829 ( .A(n7369), .Y(n8802) );
INVX2TS U7830 ( .A(n7397), .Y(n8785) );
INVX2TS U7831 ( .A(n7399), .Y(n8784) );
INVX2TS U7832 ( .A(n7401), .Y(n8782) );
INVX2TS U7833 ( .A(n7403), .Y(n8783) );
INVX2TS U7834 ( .A(n7378), .Y(n8805) );
INVX2TS U7835 ( .A(n7380), .Y(n8815) );
INVX2TS U7836 ( .A(n7381), .Y(n8810) );
INVX2TS U7837 ( .A(n7382), .Y(n8820) );
INVX2TS U7838 ( .A(n7384), .Y(n8813) );
INVX2TS U7839 ( .A(n7386), .Y(n8834) );
INVX2TS U7840 ( .A(n7388), .Y(n8824) );
INVX2TS U7841 ( .A(n7389), .Y(n8832) );
AOI22X1TS U7842 ( .A0(n6715), .A1(cordic_result[18]), .B0(n6714), .B1(
mult_result[18]), .Y(n6703) );
AOI22X1TS U7843 ( .A0(n6715), .A1(cordic_result[13]), .B0(n6714), .B1(
mult_result[13]), .Y(n6704) );
AOI22X1TS U7844 ( .A0(n6715), .A1(cordic_result[15]), .B0(n6714), .B1(
mult_result[15]), .Y(n6705) );
AOI22X1TS U7845 ( .A0(n6715), .A1(cordic_result[14]), .B0(n6714), .B1(
mult_result[14]), .Y(n6706) );
AOI22X1TS U7846 ( .A0(n6715), .A1(cordic_result[16]), .B0(n6714), .B1(
mult_result[16]), .Y(n6707) );
AOI22X1TS U7847 ( .A0(n6715), .A1(cordic_result[17]), .B0(n6714), .B1(
mult_result[17]), .Y(n6708) );
AOI22X1TS U7848 ( .A0(n6715), .A1(cordic_result[20]), .B0(n6714), .B1(
mult_result[20]), .Y(n6709) );
AOI22X1TS U7849 ( .A0(n6715), .A1(cordic_result[19]), .B0(n6714), .B1(
mult_result[19]), .Y(n6710) );
AOI22X1TS U7850 ( .A0(n6715), .A1(cordic_result[12]), .B0(n6711), .B1(
mult_result[12]), .Y(n6712) );
AOI22X1TS U7851 ( .A0(n6715), .A1(cordic_result[21]), .B0(n6714), .B1(
mult_result[21]), .Y(n6716) );
XNOR2X1TS U7852 ( .A(n6724), .B(FPSENCOS_d_ff_Xn[31]), .Y(n6727) );
XNOR2X1TS U7853 ( .A(FPSENCOS_d_ff1_operation_out), .B(
FPSENCOS_d_ff1_shift_region_flag_out[1]), .Y(n6720) );
XNOR2X1TS U7854 ( .A(FPSENCOS_d_ff1_shift_region_flag_out[0]), .B(n6720),
.Y(n6722) );
NOR2X2TS U7855 ( .A(n6794), .B(n6722), .Y(n6721) );
BUFX3TS U7856 ( .A(n6824), .Y(n6793) );
XOR2X1TS U7857 ( .A(FPSENCOS_d_ff_Yn[31]), .B(n6724), .Y(n6725) );
AOI22X1TS U7858 ( .A0(n6794), .A1(cordic_result[31]), .B0(n6793), .B1(n6725),
.Y(n6726) );
INVX2TS U7859 ( .A(n6778), .Y(n6728) );
INVX2TS U7860 ( .A(n6729), .Y(n1698) );
INVX2TS U7861 ( .A(n6732), .Y(n1735) );
AOI222X1TS U7862 ( .A0(n6755), .A1(FPSENCOS_d_ff2_Z[29]), .B0(n6754), .B1(
FPSENCOS_d_ff_Zn[29]), .C0(n6753), .C1(FPSENCOS_d_ff1_Z[29]), .Y(n6733) );
INVX2TS U7863 ( .A(n6733), .Y(n1737) );
AOI222X1TS U7864 ( .A0(n6755), .A1(FPSENCOS_d_ff2_Z[30]), .B0(n6754), .B1(
FPSENCOS_d_ff_Zn[30]), .C0(n6734), .C1(FPSENCOS_d_ff1_Z[30]), .Y(n6735) );
INVX2TS U7865 ( .A(n6735), .Y(n1736) );
BUFX3TS U7866 ( .A(n6736), .Y(n6772) );
AOI222X1TS U7867 ( .A0(n6750), .A1(FPSENCOS_d_ff2_Z[15]), .B0(n6759), .B1(
FPSENCOS_d_ff_Zn[15]), .C0(n6772), .C1(FPSENCOS_d_ff1_Z[15]), .Y(n6737) );
INVX2TS U7868 ( .A(n6737), .Y(n1751) );
AOI222X1TS U7869 ( .A0(n6750), .A1(FPSENCOS_d_ff2_Z[19]), .B0(n7408), .B1(
FPSENCOS_d_ff_Zn[19]), .C0(n6772), .C1(FPSENCOS_d_ff1_Z[19]), .Y(n6738) );
INVX2TS U7870 ( .A(n6738), .Y(n1747) );
AOI222X1TS U7871 ( .A0(n6750), .A1(FPSENCOS_d_ff2_Z[16]), .B0(n7408), .B1(
FPSENCOS_d_ff_Zn[16]), .C0(n6772), .C1(FPSENCOS_d_ff1_Z[16]), .Y(n6739) );
INVX2TS U7872 ( .A(n6739), .Y(n1750) );
AOI222X1TS U7873 ( .A0(n6755), .A1(FPSENCOS_d_ff2_Z[27]), .B0(n6754), .B1(
FPSENCOS_d_ff_Zn[27]), .C0(n6753), .C1(FPSENCOS_d_ff1_Z[27]), .Y(n6740) );
INVX2TS U7874 ( .A(n6740), .Y(n1739) );
AOI222X1TS U7875 ( .A0(n6750), .A1(FPSENCOS_d_ff2_Z[14]), .B0(n7408), .B1(
FPSENCOS_d_ff_Zn[14]), .C0(n6772), .C1(FPSENCOS_d_ff1_Z[14]), .Y(n6741) );
INVX2TS U7876 ( .A(n6741), .Y(n1752) );
AOI222X1TS U7877 ( .A0(n6755), .A1(FPSENCOS_d_ff2_Z[26]), .B0(n6754), .B1(
FPSENCOS_d_ff_Zn[26]), .C0(n6753), .C1(FPSENCOS_d_ff1_Z[26]), .Y(n6742) );
INVX2TS U7878 ( .A(n6742), .Y(n1740) );
AOI222X1TS U7879 ( .A0(n6750), .A1(FPSENCOS_d_ff2_Z[21]), .B0(n7408), .B1(
FPSENCOS_d_ff_Zn[21]), .C0(n6753), .C1(FPSENCOS_d_ff1_Z[21]), .Y(n6743) );
INVX2TS U7880 ( .A(n6743), .Y(n1745) );
AOI222X1TS U7881 ( .A0(n6755), .A1(FPSENCOS_d_ff2_Z[24]), .B0(n6754), .B1(
FPSENCOS_d_ff_Zn[24]), .C0(n6753), .C1(FPSENCOS_d_ff1_Z[24]), .Y(n6744) );
INVX2TS U7882 ( .A(n6744), .Y(n1742) );
AOI222X1TS U7883 ( .A0(n6750), .A1(FPSENCOS_d_ff2_Z[13]), .B0(n7408), .B1(
FPSENCOS_d_ff_Zn[13]), .C0(n6772), .C1(FPSENCOS_d_ff1_Z[13]), .Y(n6745) );
INVX2TS U7884 ( .A(n6745), .Y(n1753) );
AOI222X1TS U7885 ( .A0(n6755), .A1(FPSENCOS_d_ff2_Z[22]), .B0(n6754), .B1(
FPSENCOS_d_ff_Zn[22]), .C0(n6753), .C1(FPSENCOS_d_ff1_Z[22]), .Y(n6746) );
INVX2TS U7886 ( .A(n6746), .Y(n1744) );
AOI222X1TS U7887 ( .A0(n6750), .A1(FPSENCOS_d_ff2_Z[23]), .B0(n6754), .B1(
FPSENCOS_d_ff_Zn[23]), .C0(n6753), .C1(FPSENCOS_d_ff1_Z[23]), .Y(n6747) );
INVX2TS U7888 ( .A(n6747), .Y(n1743) );
AOI222X1TS U7889 ( .A0(n6750), .A1(FPSENCOS_d_ff2_Z[17]), .B0(n7408), .B1(
FPSENCOS_d_ff_Zn[17]), .C0(n6772), .C1(FPSENCOS_d_ff1_Z[17]), .Y(n6748) );
INVX2TS U7890 ( .A(n6748), .Y(n1749) );
AOI222X1TS U7891 ( .A0(n6750), .A1(FPSENCOS_d_ff2_Z[20]), .B0(n2407), .B1(
FPSENCOS_d_ff_Zn[20]), .C0(n6753), .C1(FPSENCOS_d_ff1_Z[20]), .Y(n6749) );
INVX2TS U7892 ( .A(n6749), .Y(n1746) );
AOI222X1TS U7893 ( .A0(n6750), .A1(FPSENCOS_d_ff2_Z[18]), .B0(n2407), .B1(
FPSENCOS_d_ff_Zn[18]), .C0(n6772), .C1(FPSENCOS_d_ff1_Z[18]), .Y(n6751) );
INVX2TS U7894 ( .A(n6751), .Y(n1748) );
AOI222X1TS U7895 ( .A0(n6755), .A1(FPSENCOS_d_ff2_Z[28]), .B0(n6754), .B1(
FPSENCOS_d_ff_Zn[28]), .C0(n6753), .C1(FPSENCOS_d_ff1_Z[28]), .Y(n6752) );
INVX2TS U7896 ( .A(n6752), .Y(n1738) );
AOI222X1TS U7897 ( .A0(n6755), .A1(FPSENCOS_d_ff2_Z[25]), .B0(n6754), .B1(
FPSENCOS_d_ff_Zn[25]), .C0(n6753), .C1(FPSENCOS_d_ff1_Z[25]), .Y(n6756) );
INVX2TS U7898 ( .A(n6756), .Y(n1741) );
INVX2TS U7899 ( .A(n7413), .Y(n7417) );
AOI222X1TS U7900 ( .A0(n7417), .A1(FPSENCOS_d_ff2_Z[2]), .B0(n6774), .B1(
FPSENCOS_d_ff_Zn[2]), .C0(n6736), .C1(FPSENCOS_d_ff1_Z[2]), .Y(n6757)
);
INVX2TS U7901 ( .A(n6757), .Y(n1764) );
AOI222X1TS U7902 ( .A0(n7417), .A1(FPSENCOS_d_ff2_Z[3]), .B0(n6774), .B1(
FPSENCOS_d_ff_Zn[3]), .C0(n6736), .C1(FPSENCOS_d_ff1_Z[3]), .Y(n6758)
);
INVX2TS U7903 ( .A(n6758), .Y(n1763) );
BUFX3TS U7904 ( .A(n6759), .Y(n7416) );
AOI222X1TS U7905 ( .A0(n7417), .A1(FPSENCOS_d_ff2_Z[0]), .B0(n6734), .B1(
FPSENCOS_d_ff1_Z[0]), .C0(FPSENCOS_d_ff_Zn[0]), .C1(n7416), .Y(n6760)
);
INVX2TS U7906 ( .A(n6760), .Y(n1766) );
AOI2BB2XLTS U7907 ( .B0(FPSENCOS_d_ff3_sign_out), .B1(n7819), .A0N(n7819),
.A1N(FPSENCOS_d_ff3_sign_out), .Y(n6762) );
BUFX3TS U7908 ( .A(n7372), .Y(n7449) );
AOI22X1TS U7909 ( .A0(operation[0]), .A1(n7433), .B0(FPADDSUB_intAS), .B1(
n7449), .Y(n6761) );
AOI222X1TS U7910 ( .A0(n6775), .A1(FPSENCOS_d_ff2_Z[7]), .B0(n6774), .B1(
FPSENCOS_d_ff_Zn[7]), .C0(n6736), .C1(FPSENCOS_d_ff1_Z[7]), .Y(n6764)
);
INVX2TS U7911 ( .A(n6764), .Y(n1759) );
AOI222X1TS U7912 ( .A0(n6775), .A1(FPSENCOS_d_ff2_Z[8]), .B0(n6774), .B1(
FPSENCOS_d_ff_Zn[8]), .C0(n6736), .C1(FPSENCOS_d_ff1_Z[8]), .Y(n6765)
);
INVX2TS U7913 ( .A(n6765), .Y(n1758) );
AOI222X1TS U7914 ( .A0(n6775), .A1(FPSENCOS_d_ff2_Z[6]), .B0(n6774), .B1(
FPSENCOS_d_ff_Zn[6]), .C0(n6736), .C1(FPSENCOS_d_ff1_Z[6]), .Y(n6766)
);
INVX2TS U7915 ( .A(n6766), .Y(n1760) );
AOI222X1TS U7916 ( .A0(n6775), .A1(FPSENCOS_d_ff2_Z[9]), .B0(n6774), .B1(
FPSENCOS_d_ff_Zn[9]), .C0(n6736), .C1(FPSENCOS_d_ff1_Z[9]), .Y(n6767)
);
INVX2TS U7917 ( .A(n6767), .Y(n1757) );
AOI222X1TS U7918 ( .A0(n6775), .A1(FPSENCOS_d_ff2_Z[5]), .B0(n6774), .B1(
FPSENCOS_d_ff_Zn[5]), .C0(n6736), .C1(FPSENCOS_d_ff1_Z[5]), .Y(n6768)
);
INVX2TS U7919 ( .A(n6768), .Y(n1761) );
AOI222X1TS U7920 ( .A0(n6775), .A1(FPSENCOS_d_ff2_Z[1]), .B0(n7416), .B1(
FPSENCOS_d_ff_Zn[1]), .C0(n6734), .C1(FPSENCOS_d_ff1_Z[1]), .Y(n6769)
);
INVX2TS U7921 ( .A(n6769), .Y(n1765) );
AOI222X1TS U7922 ( .A0(n6775), .A1(FPSENCOS_d_ff2_Z[12]), .B0(n6774), .B1(
FPSENCOS_d_ff_Zn[12]), .C0(n6772), .C1(FPSENCOS_d_ff1_Z[12]), .Y(n6770) );
INVX2TS U7923 ( .A(n6770), .Y(n1754) );
AOI222X1TS U7924 ( .A0(n6775), .A1(FPSENCOS_d_ff2_Z[10]), .B0(n6774), .B1(
FPSENCOS_d_ff_Zn[10]), .C0(n6772), .C1(FPSENCOS_d_ff1_Z[10]), .Y(n6771) );
INVX2TS U7925 ( .A(n6771), .Y(n1756) );
AOI222X1TS U7926 ( .A0(n6775), .A1(FPSENCOS_d_ff2_Z[11]), .B0(n6759), .B1(
FPSENCOS_d_ff_Zn[11]), .C0(n6772), .C1(FPSENCOS_d_ff1_Z[11]), .Y(n6773) );
INVX2TS U7927 ( .A(n6773), .Y(n1755) );
AOI222X1TS U7928 ( .A0(n6775), .A1(FPSENCOS_d_ff2_Z[4]), .B0(n6774), .B1(
FPSENCOS_d_ff_Zn[4]), .C0(n6736), .C1(FPSENCOS_d_ff1_Z[4]), .Y(n6776)
);
INVX2TS U7929 ( .A(n6776), .Y(n1762) );
BUFX3TS U7930 ( .A(n6829), .Y(n6827) );
INVX2TS U7931 ( .A(n6777), .Y(n1717) );
BUFX3TS U7932 ( .A(n6829), .Y(n6802) );
BUFX3TS U7933 ( .A(n6824), .Y(n6801) );
INVX2TS U7934 ( .A(n6779), .Y(n1707) );
INVX2TS U7935 ( .A(n6780), .Y(n1713) );
INVX2TS U7936 ( .A(n6781), .Y(n1705) );
INVX2TS U7937 ( .A(n6782), .Y(n1706) );
INVX2TS U7938 ( .A(n6783), .Y(n1710) );
INVX2TS U7939 ( .A(n6784), .Y(n1700) );
INVX2TS U7940 ( .A(n6785), .Y(n1709) );
INVX2TS U7941 ( .A(n6786), .Y(n1704) );
INVX2TS U7942 ( .A(n6787), .Y(n1714) );
INVX2TS U7943 ( .A(n6788), .Y(n1718) );
INVX2TS U7944 ( .A(n6789), .Y(n1703) );
INVX2TS U7945 ( .A(n6790), .Y(n1702) );
INVX2TS U7946 ( .A(n6791), .Y(n1715) );
INVX2TS U7947 ( .A(n6792), .Y(n1701) );
INVX2TS U7948 ( .A(n6795), .Y(n1699) );
INVX2TS U7949 ( .A(n6797), .Y(n1708) );
INVX2TS U7950 ( .A(n6798), .Y(n1712) );
INVX2TS U7951 ( .A(n6799), .Y(n1716) );
INVX2TS U7952 ( .A(n6803), .Y(n1711) );
AND4X1TS U7953 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[3]), .B(
FPADDSUB_exp_rslt_NRM2_EW1[2]), .C(FPADDSUB_exp_rslt_NRM2_EW1[1]), .D(
FPADDSUB_exp_rslt_NRM2_EW1[0]), .Y(n6804) );
OAI2BB1X2TS U7954 ( .A0N(n2311), .A1N(n6806), .B0(n7629), .Y(n6807) );
INVX4TS U7955 ( .A(n6807), .Y(n7521) );
NAND2X1TS U7956 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[5]), .B(n7629), .Y(n6810) );
NAND2X1TS U7957 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[4]), .B(n7629), .Y(n6812) );
NAND2X1TS U7958 ( .A(FPADDSUB_exp_rslt_NRM2_EW1[6]), .B(n7629), .Y(n6813) );
INVX2TS U7959 ( .A(n6818), .Y(n1728) );
INVX2TS U7960 ( .A(n6819), .Y(n1724) );
INVX2TS U7961 ( .A(n6820), .Y(n1719) );
INVX2TS U7962 ( .A(n6821), .Y(n1720) );
INVX2TS U7963 ( .A(n6822), .Y(n1723) );
INVX2TS U7964 ( .A(n6823), .Y(n1725) );
INVX2TS U7965 ( .A(n6825), .Y(n1727) );
INVX2TS U7966 ( .A(n6826), .Y(n1721) );
INVX2TS U7967 ( .A(n6828), .Y(n1722) );
INVX2TS U7968 ( .A(n6830), .Y(n1726) );
AOI21X1TS U7969 ( .A0(n6840), .A1(FPADDSUB_Raw_mant_NRM_SWR[25]), .B0(n8526),
.Y(n6831) );
OAI21X1TS U7970 ( .A0(n6832), .A1(n7152), .B0(n6831), .Y(n8714) );
AOI22X1TS U7971 ( .A0(n2211), .A1(n8455), .B0(n2406), .B1(n8454), .Y(n6835)
);
AOI22X1TS U7972 ( .A0(n2345), .A1(n8050), .B0(n6851), .B1(n8446), .Y(n6834)
);
AOI22X1TS U7973 ( .A0(n2212), .A1(n8458), .B0(n2291), .B1(n8457), .Y(n6837)
);
AOI22X1TS U7974 ( .A0(n2375), .A1(n8049), .B0(n2471), .B1(n8045), .Y(n6836)
);
INVX2TS U7975 ( .A(n8746), .Y(n8522) );
INVX2TS U7976 ( .A(n8748), .Y(n8521) );
AOI22X1TS U7977 ( .A0(n6838), .A1(FPADDSUB_Raw_mant_NRM_SWR[20]), .B0(
FPADDSUB_DmP_mant_SHT1_SW[18]), .B1(n2358), .Y(n6839) );
OAI21X1TS U7978 ( .A0(n7797), .A1(n6840), .B0(n6839), .Y(n8722) );
AOI22X1TS U7979 ( .A0(n2211), .A1(n8421), .B0(n2406), .B1(n8420), .Y(n6842)
);
AOI22X1TS U7980 ( .A0(n2292), .A1(n8016), .B0(n8118), .B1(n8055), .Y(n6841)
);
OAI211X1TS U7981 ( .A0(n8046), .A1(n8058), .B0(n6842), .C0(n6841), .Y(n1790)
);
AOI22X1TS U7982 ( .A0(n2212), .A1(n8433), .B0(n2406), .B1(n8432), .Y(n6844)
);
AOI22X1TS U7983 ( .A0(n2293), .A1(n8027), .B0(n8118), .B1(n8430), .Y(n6843)
);
OAI211X1TS U7984 ( .A0(n8046), .A1(n8059), .B0(n6844), .C0(n6843), .Y(n1791)
);
AOI22X1TS U7985 ( .A0(n2212), .A1(n8428), .B0(n2291), .B1(n8427), .Y(n6846)
);
AOI22X1TS U7986 ( .A0(n2375), .A1(n8054), .B0(n2471), .B1(n8053), .Y(n6845)
);
AOI22X1TS U7987 ( .A0(n2211), .A1(n8435), .B0(n2406), .B1(n8434), .Y(n6848)
);
AOI22X1TS U7988 ( .A0(n2345), .A1(n8054), .B0(n6851), .B1(n8459), .Y(n6847)
);
AOI22X1TS U7989 ( .A0(n2211), .A1(n8425), .B0(n2291), .B1(n8424), .Y(n6850)
);
AOI22X1TS U7990 ( .A0(n2375), .A1(n8053), .B0(n2471), .B1(n8052), .Y(n6849)
);
AOI22X1TS U7991 ( .A0(n2212), .A1(n8423), .B0(n2291), .B1(n8422), .Y(n6853)
);
AOI22X1TS U7992 ( .A0(n2293), .A1(n8055), .B0(n2471), .B1(n8054), .Y(n6852)
);
OAI211X1TS U7993 ( .A0(n8499), .A1(n2468), .B0(n6853), .C0(n6852), .Y(n1792)
);
NAND2X1TS U7994 ( .A(n7285), .B(n7302), .Y(n7278) );
NOR2X2TS U7995 ( .A(ready_add_subt), .B(n7278), .Y(n7307) );
OAI21XLTS U7996 ( .A0(n7307), .A1(n7819), .B0(FPSENCOS_cont_var_out[1]), .Y(
n6856) );
AOI21X1TS U7997 ( .A0(n6858), .A1(n8714), .B0(n6857), .Y(n8711) );
OR4X2TS U7998 ( .A(n1638), .B(n1632), .C(n1628), .D(n1639), .Y(n8065) );
AOI22X1TS U7999 ( .A0(FPSENCOS_d_ff3_sh_x_out[30]), .A1(n7787), .B0(n7568),
.B1(n7449), .Y(n8710) );
BUFX3TS U8000 ( .A(n6862), .Y(n7624) );
AOI22X1TS U8001 ( .A0(n7577), .A1(n7637), .B0(n6861), .B1(n7624), .Y(n8836)
);
BUFX3TS U8002 ( .A(n7372), .Y(n7431) );
AOI22X1TS U8003 ( .A0(Data_2[22]), .A1(n7432), .B0(n7577), .B1(n7431), .Y(
n8702) );
OAI21X1TS U8004 ( .A0(n8011), .A1(n2217), .B0(n8129), .Y(n7533) );
BUFX3TS U8005 ( .A(n6862), .Y(n7537) );
AOI22X1TS U8006 ( .A0(n7578), .A1(n8610), .B0(n7533), .B1(n7537), .Y(n8771)
);
OAI21X1TS U8007 ( .A0(n8011), .A1(n2222), .B0(n8116), .Y(n7659) );
AOI22X1TS U8008 ( .A0(n7578), .A1(n7655), .B0(n7659), .B1(n7654), .Y(n8827)
);
AOI22X1TS U8009 ( .A0(Data_2[19]), .A1(n7432), .B0(n7578), .B1(n7431), .Y(
n8699) );
OAI21X1TS U8010 ( .A0(n8010), .A1(n2221), .B0(n8095), .Y(n7662) );
AOI22X1TS U8011 ( .A0(n7560), .A1(n7655), .B0(n7662), .B1(n7654), .Y(n8831)
);
AOI22X1TS U8012 ( .A0(Data_2[18]), .A1(n7432), .B0(n7560), .B1(n7431), .Y(
n8698) );
OAI21X1TS U8013 ( .A0(n8013), .A1(n2220), .B0(n8115), .Y(n7646) );
BUFX3TS U8014 ( .A(n6864), .Y(n7636) );
AOI22X1TS U8015 ( .A0(n7562), .A1(n7637), .B0(n7646), .B1(n7636), .Y(n8818)
);
OAI21X1TS U8016 ( .A0(n8013), .A1(n2215), .B0(n8130), .Y(n7547) );
AOI22X1TS U8017 ( .A0(n7562), .A1(n7633), .B0(n7547), .B1(n6862), .Y(n8777)
);
AOI22X1TS U8018 ( .A0(Data_2[16]), .A1(n7404), .B0(n7562), .B1(n7431), .Y(
n8696) );
AOI22X1TS U8019 ( .A0(n7608), .A1(n7633), .B0(n6865), .B1(n6862), .Y(n8788)
);
BUFX3TS U8020 ( .A(n7372), .Y(n7430) );
AOI22X1TS U8021 ( .A0(Data_2[3]), .A1(n7429), .B0(n7608), .B1(n7430), .Y(
n8683) );
OAI21X1TS U8022 ( .A0(n8034), .A1(n2221), .B0(n8109), .Y(n7647) );
AOI22X1TS U8023 ( .A0(n7563), .A1(n7637), .B0(n7647), .B1(n7636), .Y(n8819)
);
OAI21X1TS U8024 ( .A0(n8034), .A1(n2447), .B0(n8126), .Y(n7545) );
AOI22X1TS U8025 ( .A0(n7563), .A1(n7633), .B0(n7545), .B1(n6864), .Y(n8776)
);
AOI22X1TS U8026 ( .A0(Data_2[13]), .A1(n7432), .B0(n7563), .B1(n7431), .Y(
n8693) );
OAI21X1TS U8027 ( .A0(n8035), .A1(n2222), .B0(n8094), .Y(n7643) );
AOI22X1TS U8028 ( .A0(n7565), .A1(n7637), .B0(n7643), .B1(n7636), .Y(n8814)
);
OAI21X1TS U8029 ( .A0(n8035), .A1(n2216), .B0(n8120), .Y(n7553) );
AOI22X1TS U8030 ( .A0(n7565), .A1(n7633), .B0(n7553), .B1(n6862), .Y(n8779)
);
AOI22X1TS U8031 ( .A0(Data_2[11]), .A1(n7429), .B0(n7565), .B1(n7430), .Y(
n8691) );
AOI22X1TS U8032 ( .A0(n6867), .A1(n6863), .B0(n6866), .B1(n7624), .Y(n8794)
);
AOI22X1TS U8033 ( .A0(Data_2[7]), .A1(n7429), .B0(n6867), .B1(n7430), .Y(
n8687) );
OAI21X1TS U8034 ( .A0(n8036), .A1(n2221), .B0(n8110), .Y(n7641) );
AOI22X1TS U8035 ( .A0(n7564), .A1(n7637), .B0(n7641), .B1(n7636), .Y(n8812)
);
AOI22X1TS U8036 ( .A0(Data_2[14]), .A1(n7432), .B0(n7564), .B1(n7431), .Y(
n8694) );
OAI21X1TS U8037 ( .A0(n8042), .A1(n2216), .B0(n8131), .Y(n7630) );
AOI22X1TS U8038 ( .A0(n7581), .A1(n6863), .B0(n7630), .B1(n7636), .Y(n8806)
);
OAI21X1TS U8039 ( .A0(n8042), .A1(n2222), .B0(n8117), .Y(n7632) );
AOI22X1TS U8040 ( .A0(n7581), .A1(n7637), .B0(n7632), .B1(n7636), .Y(n8807)
);
AOI22X1TS U8041 ( .A0(Data_2[5]), .A1(n7429), .B0(n7581), .B1(n7430), .Y(
n8685) );
AOI22X1TS U8042 ( .A0(Data_2[24]), .A1(n7433), .B0(n7575), .B1(n7449), .Y(
n8704) );
AOI22X1TS U8043 ( .A0(Data_2[25]), .A1(n7433), .B0(n7571), .B1(n7449), .Y(
n8705) );
AOI22X1TS U8044 ( .A0(Data_2[26]), .A1(n7433), .B0(n7580), .B1(n7449), .Y(
n8706) );
OAI21X1TS U8045 ( .A0(n8003), .A1(n2222), .B0(n8102), .Y(n7660) );
AOI22X1TS U8046 ( .A0(n7576), .A1(n7655), .B0(n7660), .B1(n7654), .Y(n8829)
);
AOI22X1TS U8047 ( .A0(Data_2[21]), .A1(n7432), .B0(n7576), .B1(n7431), .Y(
n8701) );
OAI21X1TS U8048 ( .A0(n8005), .A1(n2220), .B0(n8114), .Y(n7651) );
AOI22X1TS U8049 ( .A0(n7582), .A1(n7655), .B0(n7651), .B1(n7654), .Y(n8822)
);
AOI22X1TS U8050 ( .A0(Data_2[4]), .A1(n7429), .B0(n7582), .B1(n7430), .Y(
n8684) );
OAI21X1TS U8051 ( .A0(n8006), .A1(n2221), .B0(n8113), .Y(n7649) );
AOI22X1TS U8052 ( .A0(n7584), .A1(n7637), .B0(n7649), .B1(n7654), .Y(n8821)
);
OAI21X1TS U8053 ( .A0(n8006), .A1(n2217), .B0(n8140), .Y(n7543) );
AOI22X1TS U8054 ( .A0(n7584), .A1(n7633), .B0(n7543), .B1(n7537), .Y(n8775)
);
AOI22X1TS U8055 ( .A0(Data_2[6]), .A1(n7429), .B0(n7584), .B1(n7430), .Y(
n8686) );
OAI21X1TS U8056 ( .A0(n8007), .A1(n2222), .B0(n8093), .Y(n7644) );
AOI22X1TS U8057 ( .A0(n7583), .A1(n7637), .B0(n7644), .B1(n7636), .Y(n8816)
);
AOI22X1TS U8058 ( .A0(Data_2[8]), .A1(n7429), .B0(n7583), .B1(n7430), .Y(
n8688) );
OAI21X1TS U8059 ( .A0(n8014), .A1(n2220), .B0(n8104), .Y(n7640) );
AOI22X1TS U8060 ( .A0(n7566), .A1(n7637), .B0(n7640), .B1(n7636), .Y(n8811)
);
OAI21X1TS U8061 ( .A0(n8014), .A1(n2217), .B0(n8137), .Y(n7558) );
AOI22X1TS U8062 ( .A0(n7633), .A1(n7566), .B0(n7558), .B1(n6862), .Y(n8781)
);
AOI22X1TS U8063 ( .A0(Data_2[10]), .A1(n7429), .B0(n7566), .B1(n7430), .Y(
n8690) );
AOI22X1TS U8064 ( .A0(n7611), .A1(n6863), .B0(n6868), .B1(n6862), .Y(n8791)
);
BUFX3TS U8065 ( .A(n6869), .Y(n7402) );
AOI22X1TS U8066 ( .A0(Data_2[2]), .A1(n7429), .B0(n7611), .B1(n7402), .Y(
n8682) );
AOI22X1TS U8067 ( .A0(n7617), .A1(n6863), .B0(n6870), .B1(n7624), .Y(n8797)
);
AOI22X1TS U8068 ( .A0(Data_2[0]), .A1(n7404), .B0(n7617), .B1(n7402), .Y(
n8680) );
AOI22X1TS U8069 ( .A0(n7620), .A1(n6863), .B0(n6871), .B1(n7624), .Y(n8800)
);
AOI22X1TS U8070 ( .A0(Data_2[1]), .A1(n7404), .B0(n7620), .B1(n7402), .Y(
n8681) );
OAI21X1TS U8071 ( .A0(n8037), .A1(n2215), .B0(n8135), .Y(n7623) );
AOI22X1TS U8072 ( .A0(n7625), .A1(n6863), .B0(n7623), .B1(n7624), .Y(n8803)
);
AOI22X1TS U8073 ( .A0(n6873), .A1(n8243), .B0(n6872), .B1(n8242), .Y(n6874)
);
AOI22X1TS U8074 ( .A0(Data_1[31]), .A1(n7404), .B0(n7602), .B1(n7402), .Y(
n8678) );
AOI22X1TS U8075 ( .A0(n7569), .A1(n8608), .B0(n7511), .B1(n6864), .Y(n8758)
);
OAI21X1TS U8076 ( .A0(n8033), .A1(n2220), .B0(n8080), .Y(n7666) );
AOI22X1TS U8077 ( .A0(n7561), .A1(n7655), .B0(n7666), .B1(n7654), .Y(n8833)
);
AOI22X1TS U8078 ( .A0(Data_2[15]), .A1(n7432), .B0(n7561), .B1(n7431), .Y(
n8695) );
INVX2TS U8079 ( .A(n1641), .Y(n6875) );
NOR2BX1TS U8080 ( .AN(n6879), .B(n6878), .Y(n8063) );
NAND2X1TS U8081 ( .A(n6955), .B(n6880), .Y(n8626) );
AOI22X1TS U8082 ( .A0(n6641), .A1(FPADDSUB_Raw_mant_NRM_SWR[25]), .B0(n6881),
.B1(n8636), .Y(n8753) );
NAND2X1TS U8083 ( .A(n6955), .B(n6883), .Y(n8624) );
NAND2X1TS U8084 ( .A(n7253), .B(n6884), .Y(n8625) );
NAND2X1TS U8085 ( .A(n7216), .B(n6885), .Y(n8620) );
NAND2X1TS U8086 ( .A(n8524), .B(n6886), .Y(n8618) );
NAND2X1TS U8087 ( .A(n8524), .B(n6887), .Y(n8622) );
NAND2X1TS U8088 ( .A(n8524), .B(n6888), .Y(n8623) );
NAND2X1TS U8089 ( .A(n7253), .B(n6889), .Y(n8617) );
NAND2X1TS U8090 ( .A(n8525), .B(n6890), .Y(n8619) );
NAND2X1TS U8091 ( .A(n8525), .B(n6903), .Y(n8614) );
NAND2X1TS U8092 ( .A(n8525), .B(n6891), .Y(n8621) );
NAND2X1TS U8093 ( .A(n7216), .B(n6892), .Y(n8628) );
NOR2BX1TS U8094 ( .AN(FPADDSUB_LZD_output_NRM2_EW[4]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n6894) );
XOR2X1TS U8095 ( .A(n7806), .B(n6894), .Y(DP_OP_26J2_126_1325_n14) );
NOR2BX1TS U8096 ( .AN(FPADDSUB_LZD_output_NRM2_EW[3]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n6895) );
XOR2X1TS U8097 ( .A(n7806), .B(n6895), .Y(DP_OP_26J2_126_1325_n15) );
NOR2BX1TS U8098 ( .AN(FPADDSUB_LZD_output_NRM2_EW[2]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n6896) );
XOR2X1TS U8099 ( .A(n7806), .B(n6896), .Y(DP_OP_26J2_126_1325_n16) );
NOR2BX1TS U8100 ( .AN(FPADDSUB_LZD_output_NRM2_EW[1]), .B(
FPADDSUB_ADD_OVRFLW_NRM2), .Y(n6897) );
XOR2X1TS U8101 ( .A(n7806), .B(n6897), .Y(DP_OP_26J2_126_1325_n17) );
XOR2X1TS U8102 ( .A(n7806), .B(n3193), .Y(DP_OP_26J2_126_1325_n18) );
MXI2X1TS U8103 ( .A(n6903), .B(n6902), .S0(FPMULT_FSM_selector_C), .Y(n6904)
);
AOI21X1TS U8104 ( .A0(n6905), .A1(n6904), .B0(n6907), .Y(n6906) );
INVX2TS U8105 ( .A(n7827), .Y(n6921) );
ADDHXLTS U8106 ( .A(FPMULT_Sgf_normalized_result[14]), .B(n6923), .CO(n6920),
.S(n6924) );
ADDHXLTS U8107 ( .A(FPMULT_Sgf_normalized_result[13]), .B(n6925), .CO(n6923),
.S(n6926) );
ADDHXLTS U8108 ( .A(FPMULT_Sgf_normalized_result[11]), .B(n6929), .CO(n6927),
.S(n6930) );
ADDHXLTS U8109 ( .A(FPMULT_Sgf_normalized_result[9]), .B(n6933), .CO(n6931),
.S(n6934) );
XOR2X1TS U8110 ( .A(add_x_246_A_2_), .B(n6941), .Y(n6942) );
AOI2BB2XLTS U8111 ( .B0(add_x_246_A_1_), .B1(n7786), .A0N(n7786), .A1N(
add_x_246_A_1_), .Y(n6944) );
NAND2X1TS U8112 ( .A(n7477), .B(n7854), .Y(n1691) );
NOR3BX1TS U8113 ( .AN(FPMULT_Op_MY[30]), .B(FPMULT_FSM_selector_B[0]), .C(
FPMULT_FSM_selector_B[1]), .Y(n6946) );
XOR2X1TS U8114 ( .A(n6984), .B(n6946), .Y(n6980) );
OAI2BB1X1TS U8115 ( .A0N(FPMULT_Op_MY[29]), .A1N(n7791), .B0(n3154), .Y(
n6947) );
XOR2X1TS U8116 ( .A(n6984), .B(n6947), .Y(n6958) );
OAI2BB1X1TS U8117 ( .A0N(FPMULT_Op_MY[28]), .A1N(n7791), .B0(n3154), .Y(
n6948) );
XOR2X1TS U8118 ( .A(n6984), .B(n6948), .Y(n6961) );
OAI2BB1X1TS U8119 ( .A0N(FPMULT_Op_MY[27]), .A1N(n7791), .B0(n3154), .Y(
n6949) );
XOR2X1TS U8120 ( .A(n6984), .B(n6949), .Y(n6965) );
OAI2BB1X1TS U8121 ( .A0N(FPMULT_Op_MY[26]), .A1N(n7791), .B0(n3154), .Y(
n6950) );
XOR2X1TS U8122 ( .A(n6984), .B(n6950), .Y(n6968) );
OAI2BB1X1TS U8123 ( .A0N(FPMULT_Op_MY[25]), .A1N(n7791), .B0(n3154), .Y(
n6951) );
XOR2X1TS U8124 ( .A(n6984), .B(n6951), .Y(n6971) );
OAI2BB1X1TS U8125 ( .A0N(FPMULT_Op_MY[24]), .A1N(n7791), .B0(n3154), .Y(
n6952) );
XOR2X1TS U8126 ( .A(n6984), .B(n6952), .Y(n6974) );
XOR2X1TS U8127 ( .A(n6984), .B(n6954), .Y(n6975) );
CMPR32X2TS U8128 ( .A(n6958), .B(n6957), .C(n6956), .CO(n6978), .S(n7100) );
CMPR32X2TS U8129 ( .A(n6961), .B(n6960), .C(n6959), .CO(n6956), .S(n7099) );
CMPR32X2TS U8130 ( .A(n6965), .B(n6964), .C(n6963), .CO(n6959), .S(n7098) );
CMPR32X2TS U8131 ( .A(n6968), .B(n6967), .C(n6966), .CO(n6963), .S(n7097) );
CMPR32X2TS U8132 ( .A(n6971), .B(n6970), .C(n6969), .CO(n6966), .S(n7096) );
CMPR32X2TS U8133 ( .A(n6974), .B(n6973), .C(n6972), .CO(n6969), .S(n7095) );
CMPR32X2TS U8134 ( .A(n6980), .B(n6979), .C(n6978), .CO(n6982), .S(n7103) );
CMPR32X2TS U8135 ( .A(n2427), .B(n6983), .C(n6982), .CO(n6986), .S(n7105) );
INVX2TS U8136 ( .A(n6984), .Y(n6985) );
XNOR2X1TS U8137 ( .A(n6986), .B(n6985), .Y(n6987) );
BUFX3TS U8138 ( .A(n6989), .Y(n7517) );
BUFX3TS U8139 ( .A(n6989), .Y(n6990) );
INVX2TS U8140 ( .A(n1810), .Y(n6992) );
OAI22X1TS U8141 ( .A0(n6992), .A1(n7012), .B0(n2341), .B1(n6991), .Y(n6993)
);
AOI211X2TS U8142 ( .A0(n2373), .A1(n1806), .B0(n7034), .C0(n6993), .Y(n7055)
);
AOI22X1TS U8143 ( .A0(n1802), .A1(n2381), .B0(n1794), .B1(n2398), .Y(n6995)
);
AOI22X1TS U8144 ( .A0(n1798), .A1(n6178), .B0(n1790), .B1(n2396), .Y(n6994)
);
OAI211X1TS U8145 ( .A0(n7055), .A1(n2340), .B0(n6995), .C0(n6994), .Y(n7079)
);
AOI211X1TS U8146 ( .A0(n2404), .A1(n7079), .B0(n7031), .C0(n6997), .Y(n7522)
);
MXI2X1TS U8147 ( .A(n7522), .B(n7868), .S0(n7598), .Y(n1183) );
INVX2TS U8148 ( .A(n1811), .Y(n7043) );
AOI22X1TS U8149 ( .A0(n1799), .A1(n6178), .B0(n1791), .B1(n2395), .Y(n7000)
);
AOI22X1TS U8150 ( .A0(n1803), .A1(n6180), .B0(n1795), .B1(n2397), .Y(n6999)
);
OAI211X1TS U8151 ( .A0(n7058), .A1(n7050), .B0(n7000), .C0(n6999), .Y(n7076)
);
AOI21X2TS U8152 ( .A0(n2373), .A1(n1812), .B0(n7005), .Y(n7074) );
AOI211X1TS U8153 ( .A0(FPADDSUB_left_right_SHT2), .A1(n7076), .B0(n7031),
.C0(n7001), .Y(n7530) );
MXI2X1TS U8154 ( .A(n7530), .B(n7861), .S0(n7515), .Y(n1184) );
INVX2TS U8155 ( .A(n1812), .Y(n7039) );
OAI21X1TS U8156 ( .A0(n7039), .A1(n7012), .B0(n7011), .Y(n7002) );
AOI21X2TS U8157 ( .A0(n1808), .A1(n2373), .B0(n7002), .Y(n7062) );
AOI22X1TS U8158 ( .A0(n1800), .A1(n6178), .B0(n1792), .B1(n2395), .Y(n7004)
);
AOI22X1TS U8159 ( .A0(n1804), .A1(n6180), .B0(n1796), .B1(n2397), .Y(n7003)
);
OAI211X1TS U8160 ( .A0(n7062), .A1(n2340), .B0(n7004), .C0(n7003), .Y(n7073)
);
AOI21X2TS U8161 ( .A0(n2373), .A1(n1811), .B0(n7005), .Y(n7071) );
AOI211X1TS U8162 ( .A0(n2404), .A1(n7073), .B0(n7031), .C0(n7006), .Y(n7534)
);
MXI2X1TS U8163 ( .A(n7534), .B(n7869), .S0(n7061), .Y(n1185) );
OAI21X1TS U8164 ( .A0(n7007), .A1(n7012), .B0(n7011), .Y(n7008) );
AOI21X2TS U8165 ( .A0(n1809), .A1(n2372), .B0(n7008), .Y(n7065) );
AOI22X1TS U8166 ( .A0(n1801), .A1(n6178), .B0(n1793), .B1(n2395), .Y(n7010)
);
AOI22X1TS U8167 ( .A0(n1805), .A1(n6180), .B0(n1797), .B1(n2397), .Y(n7009)
);
OAI211X1TS U8168 ( .A0(n7065), .A1(n7050), .B0(n7010), .C0(n7009), .Y(n7070)
);
OAI21X1TS U8169 ( .A0(n2341), .A1(n7012), .B0(n7011), .Y(n7013) );
AOI21X2TS U8170 ( .A0(n1810), .A1(n2373), .B0(n7013), .Y(n7068) );
AOI211X1TS U8171 ( .A0(n2404), .A1(n7070), .B0(n7031), .C0(n7014), .Y(n7532)
);
MXI2X1TS U8172 ( .A(n7532), .B(n7862), .S0(n7061), .Y(n1186) );
AOI22X1TS U8173 ( .A0(n1802), .A1(n6178), .B0(n1794), .B1(n2395), .Y(n7016)
);
AOI22X1TS U8174 ( .A0(n1806), .A1(n2381), .B0(n1798), .B1(n2397), .Y(n7015)
);
OAI211X1TS U8175 ( .A0(n7068), .A1(n2340), .B0(n7016), .C0(n7015), .Y(n7067)
);
AOI211X1TS U8176 ( .A0(n2404), .A1(n7067), .B0(n7031), .C0(n7017), .Y(n7528)
);
MXI2X1TS U8177 ( .A(n7528), .B(n7870), .S0(n7515), .Y(n1187) );
AOI22X1TS U8178 ( .A0(n1807), .A1(n2381), .B0(n1799), .B1(n2397), .Y(n7019)
);
AOI22X1TS U8179 ( .A0(n1803), .A1(n6178), .B0(n1795), .B1(n2395), .Y(n7018)
);
OAI211X1TS U8180 ( .A0(n7071), .A1(n7050), .B0(n7019), .C0(n7018), .Y(n7064)
);
AOI211X1TS U8181 ( .A0(n2404), .A1(n7064), .B0(n7031), .C0(n7020), .Y(n7536)
);
MXI2X1TS U8182 ( .A(n7536), .B(n7863), .S0(n7061), .Y(n1188) );
AOI22X1TS U8183 ( .A0(n1808), .A1(n6180), .B0(n1800), .B1(n2397), .Y(n7022)
);
AOI22X1TS U8184 ( .A0(n1804), .A1(n6178), .B0(n1796), .B1(n2395), .Y(n7021)
);
OAI211X1TS U8185 ( .A0(n7074), .A1(n2340), .B0(n7022), .C0(n7021), .Y(n7060)
);
AOI211X1TS U8186 ( .A0(FPADDSUB_left_right_SHT2), .A1(n7060), .B0(n7031),
.C0(n7023), .Y(n7546) );
MXI2X1TS U8187 ( .A(n7546), .B(n7871), .S0(n7061), .Y(n1189) );
AOI22X1TS U8188 ( .A0(n1809), .A1(n2381), .B0(n1801), .B1(n2398), .Y(n7025)
);
AOI22X1TS U8189 ( .A0(n1805), .A1(n6178), .B0(n1797), .B1(n2395), .Y(n7024)
);
OAI211X1TS U8190 ( .A0(n7077), .A1(n2340), .B0(n7025), .C0(n7024), .Y(n7057)
);
AOI211X1TS U8191 ( .A0(FPADDSUB_left_right_SHT2), .A1(n7057), .B0(n7031),
.C0(n7026), .Y(n7525) );
MXI2X1TS U8192 ( .A(n7525), .B(n7864), .S0(n7515), .Y(n1190) );
AOI22X1TS U8193 ( .A0(n1810), .A1(n6180), .B0(n1802), .B1(n2397), .Y(n7028)
);
AOI22X1TS U8194 ( .A0(n1806), .A1(n6178), .B0(n1798), .B1(n2395), .Y(n7027)
);
OAI211X1TS U8195 ( .A0(n7081), .A1(n2340), .B0(n7028), .C0(n7027), .Y(n7054)
);
AOI211X1TS U8196 ( .A0(n2404), .A1(n7054), .B0(n7031), .C0(n7030), .Y(n7554)
);
MXI2X1TS U8197 ( .A(n7554), .B(n7872), .S0(n7086), .Y(n1191) );
AOI21X1TS U8198 ( .A0(n1803), .A1(n2398), .B0(n7052), .Y(n7033) );
AOI22X1TS U8199 ( .A0(n1807), .A1(n2443), .B0(n1799), .B1(n2396), .Y(n7032)
);
OAI211X1TS U8200 ( .A0(n7043), .A1(n7038), .B0(n7033), .C0(n7032), .Y(n7048)
);
INVX2TS U8201 ( .A(n2443), .Y(n7042) );
NOR2X1TS U8202 ( .A(n7052), .B(n7034), .Y(n7041) );
AOI22X1TS U8203 ( .A0(n1808), .A1(n2398), .B0(n1804), .B1(n2396), .Y(n7035)
);
OAI211X1TS U8204 ( .A0(n7039), .A1(n7042), .B0(n7041), .C0(n7035), .Y(n7049)
);
AOI22X1TS U8205 ( .A0(n2404), .A1(n7048), .B0(n7049), .B1(n2344), .Y(n7544)
);
MXI2X1TS U8206 ( .A(n7544), .B(n7865), .S0(n7515), .Y(n1192) );
AOI21X1TS U8207 ( .A0(n1804), .A1(n2398), .B0(n7052), .Y(n7037) );
AOI22X1TS U8208 ( .A0(n1808), .A1(n2443), .B0(n1800), .B1(n2396), .Y(n7036)
);
OAI211X1TS U8209 ( .A0(n7039), .A1(n7038), .B0(n7037), .C0(n7036), .Y(n7046)
);
AOI22X1TS U8210 ( .A0(n1807), .A1(n2398), .B0(n1803), .B1(n2396), .Y(n7040)
);
OAI211X1TS U8211 ( .A0(n7043), .A1(n7042), .B0(n7041), .C0(n7040), .Y(n7047)
);
AOI22X1TS U8212 ( .A0(FPADDSUB_left_right_SHT2), .A1(n7046), .B0(n7047),
.B1(n2344), .Y(n7559) );
MXI2X1TS U8213 ( .A(n7559), .B(n7873), .S0(n7061), .Y(n1193) );
AOI221X1TS U8214 ( .A0(n2404), .A1(n7045), .B0(n2344), .B1(n7044), .C0(n7052), .Y(n7552) );
MXI2X1TS U8215 ( .A(n7552), .B(n7866), .S0(n7515), .Y(n1194) );
AOI22X1TS U8216 ( .A0(n2404), .A1(n7047), .B0(n7046), .B1(n2344), .Y(n7621)
);
MXI2X1TS U8217 ( .A(n7621), .B(n7941), .S0(n7086), .Y(n1196) );
AOI22X1TS U8218 ( .A0(FPADDSUB_left_right_SHT2), .A1(n7049), .B0(n7048),
.B1(n2344), .Y(n7549) );
MXI2X1TS U8219 ( .A(n7549), .B(n7944), .S0(n7515), .Y(n1197) );
AOI211X1TS U8220 ( .A0(n7054), .A1(n7084), .B0(n7053), .C0(n7082), .Y(n7612)
);
MXI2X1TS U8221 ( .A(n7612), .B(n7945), .S0(n7061), .Y(n1198) );
AOI211X1TS U8222 ( .A0(n7057), .A1(n7084), .B0(n7056), .C0(n7082), .Y(n7542)
);
BUFX3TS U8223 ( .A(n7061), .Y(n7086) );
MXI2X1TS U8224 ( .A(n7542), .B(n7946), .S0(n7086), .Y(n1199) );
AOI211X1TS U8225 ( .A0(n7060), .A1(n7084), .B0(n7059), .C0(n7082), .Y(n7628)
);
MXI2X1TS U8226 ( .A(n7628), .B(n7942), .S0(n7061), .Y(n1200) );
AOI211X1TS U8227 ( .A0(n7064), .A1(n7084), .B0(n7063), .C0(n7082), .Y(n7540)
);
MXI2X1TS U8228 ( .A(n7540), .B(n7947), .S0(n7086), .Y(n1201) );
AOI211X1TS U8229 ( .A0(n7067), .A1(n7084), .B0(n7066), .C0(n7082), .Y(n7606)
);
MXI2X1TS U8230 ( .A(n7606), .B(n7948), .S0(n7086), .Y(n1202) );
AOI211X1TS U8231 ( .A0(n7070), .A1(n7084), .B0(n7069), .C0(n7082), .Y(n7609)
);
MXI2X1TS U8232 ( .A(n7609), .B(n7949), .S0(n7086), .Y(n1203) );
AOI211X1TS U8233 ( .A0(n7073), .A1(n7084), .B0(n7072), .C0(n7082), .Y(n7618)
);
MXI2X1TS U8234 ( .A(n7618), .B(n7950), .S0(n7086), .Y(n1204) );
AOI211X1TS U8235 ( .A0(n7076), .A1(n7084), .B0(n7075), .C0(n7082), .Y(n7615)
);
MXI2X1TS U8236 ( .A(n7615), .B(n7951), .S0(n7086), .Y(n1205) );
AOI211X1TS U8237 ( .A0(n7079), .A1(n2344), .B0(n7078), .C0(n7082), .Y(n7080)
);
MXI2X1TS U8238 ( .A(n7080), .B(n7943), .S0(n7086), .Y(n1206) );
AOI211X1TS U8239 ( .A0(n7085), .A1(n2344), .B0(n7083), .C0(n7082), .Y(n7087)
);
MXI2X1TS U8240 ( .A(n7087), .B(n7805), .S0(n7086), .Y(n1207) );
NAND2X1TS U8241 ( .A(n7090), .B(n7875), .Y(n7091) );
OAI22X1TS U8242 ( .A0(n7105), .A1(n7104), .B0(n7480), .B1(n7874), .Y(n1516)
);
NAND2X1TS U8243 ( .A(n7107), .B(n7106), .Y(n7110) );
INVX2TS U8244 ( .A(n7110), .Y(n7108) );
XNOR2X1TS U8245 ( .A(n7109), .B(n7108), .Y(n7114) );
XNOR2X1TS U8246 ( .A(n7111), .B(n7110), .Y(n7112) );
AOI22X1TS U8247 ( .A0(n7112), .A1(n7138), .B0(FPADDSUB_Raw_mant_NRM_SWR[14]),
.B1(n7159), .Y(n7113) );
OAI2BB1X1TS U8248 ( .A0N(n7201), .A1N(n7114), .B0(n7113), .Y(n1337) );
INVX2TS U8249 ( .A(n7115), .Y(n7117) );
NAND2X1TS U8250 ( .A(n7117), .B(n7116), .Y(n7120) );
INVX2TS U8251 ( .A(n7120), .Y(n7118) );
XOR2X1TS U8252 ( .A(n7121), .B(n7120), .Y(n7122) );
AOI22X1TS U8253 ( .A0(n7122), .A1(n7138), .B0(FPADDSUB_Raw_mant_NRM_SWR[13]),
.B1(n7159), .Y(n7123) );
OAI2BB1X1TS U8254 ( .A0N(n7201), .A1N(n7124), .B0(n7123), .Y(n1338) );
INVX2TS U8255 ( .A(n7125), .Y(n7190) );
INVX2TS U8256 ( .A(n7126), .Y(n7129) );
INVX2TS U8257 ( .A(n7127), .Y(n7128) );
NAND2X1TS U8258 ( .A(n7131), .B(n7130), .Y(n7136) );
INVX2TS U8259 ( .A(n7136), .Y(n7132) );
XNOR2X1TS U8260 ( .A(n7133), .B(n7132), .Y(n7141) );
XNOR2X1TS U8261 ( .A(n7137), .B(n7136), .Y(n7139) );
AOI22X1TS U8262 ( .A0(n7139), .A1(n7138), .B0(n2489), .B1(n7159), .Y(n7140)
);
OAI2BB1X1TS U8263 ( .A0N(n7201), .A1N(n7141), .B0(n7140), .Y(n1340) );
NAND2X1TS U8264 ( .A(n7145), .B(n7144), .Y(n7148) );
INVX2TS U8265 ( .A(n7148), .Y(n7146) );
XNOR2X1TS U8266 ( .A(n7147), .B(n7146), .Y(n7151) );
XOR2X1TS U8267 ( .A(n7180), .B(n7148), .Y(n7149) );
AOI22X1TS U8268 ( .A0(n7149), .A1(n7197), .B0(FPADDSUB_Raw_mant_NRM_SWR[10]),
.B1(n7159), .Y(n7150) );
OAI2BB1X1TS U8269 ( .A0N(n7201), .A1N(n7151), .B0(n7150), .Y(n1341) );
MXI2X1TS U8270 ( .A(n7152), .B(n7805), .S0(n7600), .Y(n1351) );
INVX2TS U8271 ( .A(n7153), .Y(n7155) );
NAND2X1TS U8272 ( .A(n7155), .B(n7154), .Y(n7158) );
INVX2TS U8273 ( .A(n7158), .Y(n7156) );
XOR2X1TS U8274 ( .A(n7158), .B(n7165), .Y(n7160) );
AOI22X1TS U8275 ( .A0(n7160), .A1(n7197), .B0(FPADDSUB_Raw_mant_NRM_SWR[3]),
.B1(n7159), .Y(n7161) );
OAI2BB1X1TS U8276 ( .A0N(n7201), .A1N(n7162), .B0(n7161), .Y(n1348) );
XNOR2X1TS U8277 ( .A(FPADDSUB_DmP_mant_SFG_SWR[1]), .B(n7805), .Y(n7164) );
AOI22X1TS U8278 ( .A0(n7197), .A1(FPADDSUB_DmP_mant_SFG_SWR[1]), .B0(
FPADDSUB_Raw_mant_NRM_SWR[1]), .B1(n7196), .Y(n7163) );
OAI2BB1X1TS U8279 ( .A0N(n7201), .A1N(n7164), .B0(n7163), .Y(n1350) );
OR2X1TS U8280 ( .A(FPADDSUB_DMP_SFG[0]), .B(FPADDSUB_DmP_mant_SFG_SWR[2]),
.Y(n7166) );
CLKAND2X2TS U8281 ( .A(n7166), .B(n7165), .Y(n7168) );
XOR2XLTS U8282 ( .A(n7168), .B(n7167), .Y(n7170) );
AOI22X1TS U8283 ( .A0(n7168), .A1(n7197), .B0(FPADDSUB_Raw_mant_NRM_SWR[2]),
.B1(n7196), .Y(n7169) );
OAI2BB1X1TS U8284 ( .A0N(n7201), .A1N(n7170), .B0(n7169), .Y(n1349) );
NAND2X1TS U8285 ( .A(n7175), .B(n7174), .Y(n7181) );
INVX2TS U8286 ( .A(n7181), .Y(n7176) );
XNOR2X1TS U8287 ( .A(n7177), .B(n7176), .Y(n7185) );
XNOR2X1TS U8288 ( .A(n7182), .B(n7181), .Y(n7183) );
AOI22X1TS U8289 ( .A0(n7183), .A1(n7197), .B0(FPADDSUB_Raw_mant_NRM_SWR[12]),
.B1(n7196), .Y(n7184) );
OAI2BB1X1TS U8290 ( .A0N(n7201), .A1N(n7185), .B0(n7184), .Y(n1339) );
INVX2TS U8291 ( .A(n7186), .Y(n7188) );
NAND2X1TS U8292 ( .A(n7188), .B(n7187), .Y(n7194) );
INVX2TS U8293 ( .A(n7194), .Y(n7189) );
XNOR2X1TS U8294 ( .A(n7195), .B(n7194), .Y(n7198) );
AOI22X1TS U8295 ( .A0(n7198), .A1(n7197), .B0(FPADDSUB_Raw_mant_NRM_SWR[9]),
.B1(n7196), .Y(n7199) );
OAI2BB1X1TS U8296 ( .A0N(n7201), .A1N(n7200), .B0(n7199), .Y(n1342) );
INVX2TS U8297 ( .A(n7218), .Y(n7220) );
NAND2X1TS U8298 ( .A(n7220), .B(n7219), .Y(n7222) );
XOR2X1TS U8299 ( .A(n7222), .B(n7221), .Y(n7223) );
INVX2TS U8300 ( .A(n7224), .Y(n7230) );
INVX2TS U8301 ( .A(n7229), .Y(n7225) );
NAND2X1TS U8302 ( .A(n7225), .B(n7228), .Y(n7226) );
XOR2X1TS U8303 ( .A(n7230), .B(n7226), .Y(n7227) );
INVX2TS U8304 ( .A(n7231), .Y(n7233) );
NAND2X1TS U8305 ( .A(n7233), .B(n7232), .Y(n7234) );
XNOR2X1TS U8306 ( .A(n7235), .B(n7234), .Y(n7236) );
INVX2TS U8307 ( .A(n7237), .Y(n7242) );
XNOR2X1TS U8308 ( .A(n7238), .B(n7243), .Y(n7239) );
INVX2TS U8309 ( .A(n7240), .Y(n7241) );
AOI21X1TS U8310 ( .A0(n7243), .A1(n7242), .B0(n7241), .Y(n7248) );
INVX2TS U8311 ( .A(n7244), .Y(n7246) );
NAND2X1TS U8312 ( .A(n7246), .B(n7245), .Y(n7247) );
XOR2X1TS U8313 ( .A(n7248), .B(n7247), .Y(n7249) );
NAND2X1TS U8314 ( .A(n2818), .B(n7251), .Y(n7252) );
NOR4X1TS U8315 ( .A(Data_1[12]), .B(Data_1[11]), .C(Data_1[10]), .D(
Data_1[9]), .Y(n7261) );
NOR4X1TS U8316 ( .A(Data_1[8]), .B(Data_1[7]), .C(Data_1[6]), .D(Data_1[0]),
.Y(n7260) );
NOR4X1TS U8317 ( .A(Data_1[3]), .B(Data_1[16]), .C(Data_1[1]), .D(Data_1[22]), .Y(n7258) );
NOR4X1TS U8318 ( .A(Data_1[21]), .B(Data_1[19]), .C(Data_1[14]), .D(
Data_1[20]), .Y(n7256) );
NOR4X1TS U8319 ( .A(Data_1[13]), .B(Data_1[15]), .C(Data_1[17]), .D(
Data_1[18]), .Y(n7255) );
AND4X1TS U8320 ( .A(n7258), .B(n7257), .C(n7256), .D(n7255), .Y(n7259) );
NOR4BX1TS U8321 ( .AN(operation_reg[1]), .B(dataB[28]), .C(operation_reg[0]),
.D(dataB[23]), .Y(n7266) );
NAND4XLTS U8322 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[28]), .D(dataA[26]),
.Y(n7263) );
NAND4XLTS U8323 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n7262) );
OR3X1TS U8324 ( .A(n8638), .B(n7263), .C(n7262), .Y(n7267) );
NOR3X1TS U8325 ( .A(dataB[25]), .B(dataB[31]), .C(n7267), .Y(n7264) );
NOR4X1TS U8326 ( .A(dataA[30]), .B(dataA[27]), .C(dataA[26]), .D(dataA[28]),
.Y(n7270) );
NOR4X1TS U8327 ( .A(dataA[29]), .B(dataA[23]), .C(dataA[25]), .D(dataA[24]),
.Y(n7269) );
NOR4BX1TS U8328 ( .AN(operation_reg[1]), .B(dataA[31]), .C(operation_reg[0]),
.D(n8638), .Y(n7268) );
NOR2X1TS U8329 ( .A(operation_reg[1]), .B(n7267), .Y(n7275) );
NAND4XLTS U8330 ( .A(dataB[30]), .B(dataB[24]), .C(dataB[26]), .D(dataB[29]),
.Y(n7271) );
OAI31X1TS U8331 ( .A0(n7273), .A1(n7272), .A2(n7271), .B0(dataB[27]), .Y(
n7274) );
OAI2BB2XLTS U8332 ( .B0(n7277), .B1(n7276), .A0N(n7275), .A1N(
operation_reg[0]), .Y(NaN_reg) );
NOR3X1TS U8333 ( .A(n7426), .B(n7337), .C(n7278), .Y(n7279) );
OAI22X1TS U8334 ( .A0(n7281), .A1(n7280), .B0(n7283), .B1(n7282), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[0]) );
NOR2BX1TS U8335 ( .AN(n7283), .B(n7282), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[1]) );
OAI22X1TS U8336 ( .A0(n7442), .A1(n7286), .B0(n7285), .B1(n7284), .Y(
FPSENCOS_inst_CORDIC_FSM_v3_state_next[5]) );
NAND2X1TS U8337 ( .A(n7289), .B(n7288), .Y(n2193) );
AOI22X1TS U8338 ( .A0(cordic_result[30]), .A1(n7294), .B0(n7293), .B1(
mult_result[30]), .Y(n7290) );
OAI2BB1X1TS U8339 ( .A0N(n7297), .A1N(result_add_subt[30]), .B0(n7290), .Y(
op_result[30]) );
AOI22X1TS U8340 ( .A0(cordic_result[29]), .A1(n7294), .B0(n7293), .B1(
mult_result[29]), .Y(n7291) );
OAI2BB1X1TS U8341 ( .A0N(n7297), .A1N(result_add_subt[29]), .B0(n7291), .Y(
op_result[29]) );
AOI22X1TS U8342 ( .A0(cordic_result[25]), .A1(n7294), .B0(n7293), .B1(
mult_result[25]), .Y(n7292) );
OAI2BB1X1TS U8343 ( .A0N(n7297), .A1N(result_add_subt[25]), .B0(n7292), .Y(
op_result[25]) );
AOI22X1TS U8344 ( .A0(cordic_result[23]), .A1(n7294), .B0(n7293), .B1(
mult_result[23]), .Y(n7295) );
OAI2BB1X1TS U8345 ( .A0N(n7297), .A1N(result_add_subt[23]), .B0(n7295), .Y(
op_result[23]) );
AOI22X1TS U8346 ( .A0(n7297), .A1(ready_add_subt), .B0(n6624), .B1(n7296),
.Y(n7298) );
OAI2BB1X1TS U8347 ( .A0N(n7300), .A1N(n7299), .B0(n7298), .Y(operation_ready) );
AOI22X1TS U8348 ( .A0(n8644), .A1(n7654), .B0(n7661), .B1(n8643), .Y(n2149)
);
AOI22X1TS U8349 ( .A0(n8644), .A1(n7661), .B0(n7658), .B1(n8643), .Y(n2148)
);
AOI22X1TS U8350 ( .A0(n8644), .A1(n7599), .B0(n7301), .B1(n8643), .Y(n2145)
);
AOI22X1TS U8351 ( .A0(n7304), .A1(n7303), .B0(n2361), .B1(n7302), .Y(n2143)
);
NAND2X1TS U8352 ( .A(n2196), .B(n7305), .Y(n7306) );
XNOR2X1TS U8353 ( .A(FPSENCOS_cont_iter_out[3]), .B(n7306), .Y(n2140) );
BUFX3TS U8354 ( .A(n7308), .Y(n7331) );
AOI22X1TS U8355 ( .A0(FPSENCOS_d_ff3_LUT_out[5]), .A1(n7325), .B0(n7309),
.B1(n7313), .Y(n7310) );
NAND2X1TS U8356 ( .A(n7310), .B(n7317), .Y(n2130) );
AOI22X1TS U8357 ( .A0(n7409), .A1(n7311), .B0(FPSENCOS_d_ff3_LUT_out[7]),
.B1(n7330), .Y(n7312) );
NAND2X1TS U8358 ( .A(n7312), .B(n7320), .Y(n2128) );
AOI22X1TS U8359 ( .A0(FPSENCOS_d_ff3_LUT_out[10]), .A1(n7325), .B0(n7314),
.B1(n7313), .Y(n7315) );
INVX2TS U8360 ( .A(n7364), .Y(n7354) );
OAI221XLTS U8361 ( .A0(n7364), .A1(n7912), .B0(n7354), .B1(n7318), .C0(n7317), .Y(n2124) );
BUFX3TS U8362 ( .A(n7364), .Y(n7422) );
OAI221XLTS U8363 ( .A0(n7364), .A1(n7913), .B0(n7354), .B1(n7321), .C0(n7320), .Y(n2120) );
AOI22X1TS U8364 ( .A0(FPSENCOS_d_ff3_LUT_out[25]), .A1(n7325), .B0(n7324),
.B1(n7323), .Y(n7328) );
AOI32X1TS U8365 ( .A0(n7329), .A1(n7328), .A2(n7327), .B0(n2196), .B1(n7328),
.Y(n2117) );
BUFX3TS U8366 ( .A(n7308), .Y(n7335) );
INVX2TS U8367 ( .A(n7334), .Y(n7336) );
INVX2TS U8368 ( .A(n7345), .Y(n7351) );
BUFX3TS U8369 ( .A(n7339), .Y(n7439) );
INVX2TS U8370 ( .A(n7439), .Y(n7440) );
BUFX3TS U8371 ( .A(n7340), .Y(n7348) );
INVX2TS U8372 ( .A(n7348), .Y(n7341) );
INVX2TS U8373 ( .A(n7339), .Y(n7342) );
INVX2TS U8374 ( .A(n7348), .Y(n7346) );
INVX2TS U8375 ( .A(n7339), .Y(n7347) );
INVX2TS U8376 ( .A(n7345), .Y(n7344) );
BUFX3TS U8377 ( .A(n7339), .Y(n7349) );
BUFX3TS U8378 ( .A(n7340), .Y(n7350) );
INVX2TS U8379 ( .A(n7345), .Y(n7438) );
INVX2TS U8380 ( .A(n7348), .Y(n7352) );
INVX2TS U8381 ( .A(n7439), .Y(n7446) );
BUFX3TS U8382 ( .A(n7339), .Y(n7445) );
BUFX3TS U8383 ( .A(n7437), .Y(n7436) );
BUFX3TS U8384 ( .A(n7340), .Y(n7450) );
INVX2TS U8385 ( .A(n7450), .Y(n7451) );
BUFX3TS U8386 ( .A(n7424), .Y(n7410) );
OA22X1TS U8387 ( .A0(FPSENCOS_d_ff_Xn[1]), .A1(n2408), .B0(
FPSENCOS_d_ff2_X[1]), .B1(n7426), .Y(n2005) );
OA22X1TS U8388 ( .A0(FPSENCOS_d_ff_Xn[2]), .A1(n7425), .B0(
FPSENCOS_d_ff2_X[2]), .B1(n8611), .Y(n2003) );
OA22X1TS U8389 ( .A0(FPSENCOS_d_ff_Xn[3]), .A1(n2408), .B0(
FPSENCOS_d_ff2_X[3]), .B1(n8611), .Y(n2001) );
OA22X1TS U8390 ( .A0(FPSENCOS_d_ff_Xn[5]), .A1(n7425), .B0(
FPSENCOS_d_ff2_X[5]), .B1(n8611), .Y(n1997) );
OA22X1TS U8391 ( .A0(FPSENCOS_d_ff_Xn[6]), .A1(n2408), .B0(
FPSENCOS_d_ff2_X[6]), .B1(n8611), .Y(n1995) );
OA22X1TS U8392 ( .A0(FPSENCOS_d_ff_Xn[7]), .A1(n7425), .B0(
FPSENCOS_d_ff2_X[7]), .B1(n8611), .Y(n1993) );
INVX2TS U8393 ( .A(n7413), .Y(n7367) );
AO22X1TS U8394 ( .A0(FPSENCOS_d_ff2_X[8]), .A1(n7367), .B0(
FPSENCOS_d_ff_Xn[8]), .B1(n6759), .Y(n1991) );
AO22X1TS U8395 ( .A0(FPSENCOS_d_ff2_X[9]), .A1(n7367), .B0(
FPSENCOS_d_ff_Xn[9]), .B1(n6759), .Y(n1989) );
OA22X1TS U8396 ( .A0(FPSENCOS_d_ff_Xn[10]), .A1(n2408), .B0(
FPSENCOS_d_ff2_X[10]), .B1(n8611), .Y(n1987) );
BUFX3TS U8397 ( .A(n7413), .Y(n7356) );
OA22X1TS U8398 ( .A0(FPSENCOS_d_ff_Xn[12]), .A1(n7425), .B0(
FPSENCOS_d_ff2_X[12]), .B1(n7356), .Y(n1983) );
OA22X1TS U8399 ( .A0(FPSENCOS_d_ff_Xn[13]), .A1(n2408), .B0(
FPSENCOS_d_ff2_X[13]), .B1(n8611), .Y(n1981) );
OA22X1TS U8400 ( .A0(FPSENCOS_d_ff_Xn[14]), .A1(n7425), .B0(
FPSENCOS_d_ff2_X[14]), .B1(n7356), .Y(n1979) );
OA22X1TS U8401 ( .A0(FPSENCOS_d_ff_Xn[16]), .A1(n2408), .B0(
FPSENCOS_d_ff2_X[16]), .B1(n7356), .Y(n1975) );
OA22X1TS U8402 ( .A0(FPSENCOS_d_ff_Xn[17]), .A1(n7425), .B0(
FPSENCOS_d_ff2_X[17]), .B1(n7356), .Y(n1973) );
AO22X1TS U8403 ( .A0(FPSENCOS_d_ff2_X[18]), .A1(n7367), .B0(
FPSENCOS_d_ff_Xn[18]), .B1(n6759), .Y(n1971) );
OA22X1TS U8404 ( .A0(FPSENCOS_d_ff_Xn[19]), .A1(n2408), .B0(
FPSENCOS_d_ff2_X[19]), .B1(n7356), .Y(n1969) );
OA22X1TS U8405 ( .A0(FPSENCOS_d_ff_Xn[20]), .A1(n2408), .B0(
FPSENCOS_d_ff2_X[20]), .B1(n7356), .Y(n1967) );
BUFX3TS U8406 ( .A(n2407), .Y(n7405) );
OA22X1TS U8407 ( .A0(FPSENCOS_d_ff_Xn[24]), .A1(n7425), .B0(
FPSENCOS_d_ff2_X[24]), .B1(n7356), .Y(n1960) );
OA22X1TS U8408 ( .A0(FPSENCOS_d_ff_Xn[25]), .A1(n2408), .B0(
FPSENCOS_d_ff2_X[25]), .B1(n7356), .Y(n1959) );
OA22X1TS U8409 ( .A0(FPSENCOS_d_ff_Xn[26]), .A1(n7425), .B0(
FPSENCOS_d_ff2_X[26]), .B1(n7356), .Y(n1958) );
OA22X1TS U8410 ( .A0(FPSENCOS_d_ff_Xn[27]), .A1(n6730), .B0(
FPSENCOS_d_ff2_X[27]), .B1(n7356), .Y(n1957) );
OA22X1TS U8411 ( .A0(FPSENCOS_d_ff2_X[28]), .A1(n7426), .B0(
FPSENCOS_d_ff_Xn[28]), .B1(n6730), .Y(n1956) );
OA22X1TS U8412 ( .A0(FPSENCOS_d_ff_Xn[29]), .A1(n2408), .B0(
FPSENCOS_d_ff2_X[29]), .B1(n7413), .Y(n1955) );
NOR2X1TS U8413 ( .A(FPSENCOS_d_ff2_X[27]), .B(intadd_10_n1), .Y(n7359) );
AOI21X1TS U8414 ( .A0(intadd_10_n1), .A1(FPSENCOS_d_ff2_X[27]), .B0(n7359),
.Y(n7358) );
OR3X1TS U8415 ( .A(FPSENCOS_d_ff2_X[27]), .B(FPSENCOS_d_ff2_X[28]), .C(
intadd_10_n1), .Y(n7362) );
NOR2X1TS U8416 ( .A(FPSENCOS_d_ff2_X[29]), .B(n7362), .Y(n7365) );
AOI21X1TS U8417 ( .A0(FPSENCOS_d_ff2_X[29]), .A1(n7362), .B0(n7365), .Y(
n7363) );
BUFX3TS U8418 ( .A(n7364), .Y(n7444) );
XOR2X1TS U8419 ( .A(FPSENCOS_d_ff2_X[30]), .B(n7365), .Y(n7366) );
AOI22X1TS U8420 ( .A0(n7433), .A1(Data_1[0]), .B0(n7368), .B1(n7372), .Y(
n8647) );
AOI22X1TS U8421 ( .A0(Data_1[1]), .A1(n7433), .B0(n7369), .B1(n7372), .Y(
n8648) );
AOI22X1TS U8422 ( .A0(Data_1[2]), .A1(n7385), .B0(n7370), .B1(n7372), .Y(
n8649) );
AOI22X1TS U8423 ( .A0(Data_1[3]), .A1(n7385), .B0(n7371), .B1(n7372), .Y(
n8650) );
AOI22X1TS U8424 ( .A0(Data_1[4]), .A1(n7385), .B0(n7373), .B1(n7372), .Y(
n8651) );
BUFX3TS U8425 ( .A(n6869), .Y(n7383) );
AOI22X1TS U8426 ( .A0(Data_1[5]), .A1(n7374), .B0(n7375), .B1(n7383), .Y(
n8652) );
AOI22X1TS U8427 ( .A0(Data_1[6]), .A1(n7374), .B0(n7376), .B1(n7383), .Y(
n8653) );
AOI22X1TS U8428 ( .A0(Data_1[7]), .A1(n7374), .B0(n7614), .B1(n7383), .Y(
n8654) );
AOI22X1TS U8429 ( .A0(Data_1[8]), .A1(n7374), .B0(n7377), .B1(n7383), .Y(
n8655) );
AOI22X1TS U8430 ( .A0(Data_1[9]), .A1(n7385), .B0(n7378), .B1(n7383), .Y(
n8656) );
AOI22X1TS U8431 ( .A0(Data_1[10]), .A1(n7385), .B0(n7379), .B1(n7383), .Y(
n8657) );
AOI22X1TS U8432 ( .A0(Data_1[11]), .A1(n7374), .B0(n7380), .B1(n7383), .Y(
n8658) );
AOI22X1TS U8433 ( .A0(Data_1[12]), .A1(n7374), .B0(n7381), .B1(n7383), .Y(
n8659) );
AOI22X1TS U8434 ( .A0(Data_1[13]), .A1(n7374), .B0(n7382), .B1(n7383), .Y(
n8660) );
AOI22X1TS U8435 ( .A0(Data_1[14]), .A1(n7374), .B0(n7384), .B1(n7383), .Y(
n8661) );
BUFX3TS U8436 ( .A(n6869), .Y(n7394) );
AOI22X1TS U8437 ( .A0(Data_1[15]), .A1(n7396), .B0(n7386), .B1(n7394), .Y(
n8662) );
AOI22X1TS U8438 ( .A0(Data_1[16]), .A1(n7396), .B0(n7387), .B1(n7394), .Y(
n8663) );
AOI22X1TS U8439 ( .A0(Data_1[17]), .A1(n7396), .B0(n7388), .B1(n7394), .Y(
n8664) );
AOI22X1TS U8440 ( .A0(Data_1[18]), .A1(n7396), .B0(n7389), .B1(n7394), .Y(
n8665) );
AOI22X1TS U8441 ( .A0(Data_1[19]), .A1(n7396), .B0(n7390), .B1(n7394), .Y(
n8666) );
AOI22X1TS U8442 ( .A0(Data_1[20]), .A1(n7396), .B0(n7391), .B1(n7394), .Y(
n8667) );
AOI22X1TS U8443 ( .A0(Data_1[21]), .A1(n7396), .B0(n7392), .B1(n7394), .Y(
n8668) );
AOI22X1TS U8444 ( .A0(Data_1[22]), .A1(n7396), .B0(n7393), .B1(n7394), .Y(
n8669) );
AOI22X1TS U8445 ( .A0(Data_1[23]), .A1(n7396), .B0(gt_x_74_A_23_), .B1(n7394), .Y(n8670) );
AOI22X1TS U8446 ( .A0(Data_1[24]), .A1(n7396), .B0(n7395), .B1(n7394), .Y(
n8671) );
AOI22X1TS U8447 ( .A0(Data_1[25]), .A1(n7404), .B0(n7397), .B1(n7402), .Y(
n8672) );
AOI22X1TS U8448 ( .A0(Data_1[26]), .A1(n7404), .B0(n7398), .B1(n7402), .Y(
n8673) );
AOI22X1TS U8449 ( .A0(Data_1[27]), .A1(n7404), .B0(n7399), .B1(n7402), .Y(
n8674) );
AOI22X1TS U8450 ( .A0(Data_1[28]), .A1(n7404), .B0(n7400), .B1(n7402), .Y(
n8675) );
AOI22X1TS U8451 ( .A0(Data_1[29]), .A1(n7404), .B0(n7401), .B1(n7402), .Y(
n8676) );
AOI22X1TS U8452 ( .A0(Data_1[30]), .A1(n7404), .B0(n7403), .B1(n7402), .Y(
n8677) );
AOI22X1TS U8453 ( .A0(n7440), .A1(n2343), .B0(n7804), .B1(n7439), .Y(n1910)
);
BUFX3TS U8454 ( .A(n2407), .Y(n7411) );
INVX2TS U8455 ( .A(n7413), .Y(n7415) );
BUFX3TS U8456 ( .A(n2407), .Y(n7414) );
AOI21X1TS U8457 ( .A0(intadd_9_n1), .A1(FPSENCOS_d_ff2_Y[27]), .B0(n7418),
.Y(n7419) );
AOI21X1TS U8458 ( .A0(FPSENCOS_d_ff2_Y[29]), .A1(n7421), .B0(n7420), .Y(
n7423) );
OAI22X1TS U8459 ( .A0(n7426), .A1(n7878), .B0(n7804), .B1(n7425), .Y(n1847)
);
AOI22X1TS U8460 ( .A0(Data_2[9]), .A1(n7429), .B0(n7625), .B1(n7430), .Y(
n8689) );
AOI22X1TS U8461 ( .A0(Data_2[12]), .A1(n7432), .B0(n7638), .B1(n7430), .Y(
n8692) );
AOI22X1TS U8462 ( .A0(Data_2[17]), .A1(n7432), .B0(n7652), .B1(n7431), .Y(
n8697) );
AOI22X1TS U8463 ( .A0(Data_2[20]), .A1(n7432), .B0(n7656), .B1(n7431), .Y(
n8700) );
AOI22X1TS U8464 ( .A0(Data_2[23]), .A1(n7433), .B0(gt_x_74_B_23_), .B1(n7449), .Y(n8703) );
AOI22X1TS U8465 ( .A0(Data_2[27]), .A1(n7433), .B0(n7569), .B1(n7449), .Y(
n8707) );
AOI22X1TS U8466 ( .A0(Data_2[28]), .A1(n7433), .B0(n7570), .B1(n7449), .Y(
n8708) );
AOI22X1TS U8467 ( .A0(Data_2[29]), .A1(n7433), .B0(n7567), .B1(n7449), .Y(
n8709) );
OAI22X1TS U8468 ( .A0(n8711), .A1(n7435), .B0(n7434), .B1(n2341), .Y(n1814)
);
AOI22X1TS U8469 ( .A0(n7447), .A1(n8159), .B0(n8017), .B1(n8158), .Y(n7448)
);
NAND2X1TS U8470 ( .A(n8295), .B(n7448), .Y(n7594) );
AOI22X1TS U8471 ( .A0(FPSENCOS_d_ff3_sh_x_out[31]), .A1(n7787), .B0(n7594),
.B1(n7449), .Y(n8754) );
AOI22X1TS U8472 ( .A0(n7451), .A1(n2343), .B0(n7882), .B1(n7450), .Y(n1729)
);
NOR4X1TS U8473 ( .A(FPMULT_Op_MY[22]), .B(n3860), .C(
DP_OP_496J2_122_3540_n1462), .D(DP_OP_496J2_122_3540_n778), .Y(n7453)
);
INVX2TS U8474 ( .A(n7455), .Y(n7456) );
NAND4XLTS U8475 ( .A(n7457), .B(n7453), .C(n7915), .D(n7456), .Y(n7476) );
AND4X1TS U8476 ( .A(n8482), .B(n8483), .C(n7803), .D(n8484), .Y(n7461) );
NOR4BBX1TS U8477 ( .AN(n8486), .BN(n8487), .C(n8485), .D(n8518), .Y(n7460)
);
INVX2TS U8478 ( .A(n7458), .Y(n7459) );
NAND4XLTS U8479 ( .A(n7916), .B(n7461), .C(n7460), .D(n7459), .Y(n7475) );
NOR4X1TS U8480 ( .A(FPMULT_Op_MX[27]), .B(FPMULT_Op_MX[26]), .C(
FPMULT_Op_MX[25]), .D(FPMULT_Op_MX[23]), .Y(n7466) );
NOR4BX1TS U8481 ( .AN(n8285), .B(DP_OP_496J2_122_3540_n1502), .C(
FPMULT_Op_MX[19]), .D(FPMULT_Op_MX[20]), .Y(n7465) );
INVX2TS U8482 ( .A(n7462), .Y(n7463) );
NAND4XLTS U8483 ( .A(n7466), .B(n7465), .C(n7464), .D(n7463), .Y(n7474) );
AND4X1TS U8484 ( .A(n8489), .B(n8490), .C(n7877), .D(n8342), .Y(n7472) );
AND4X1TS U8485 ( .A(n2275), .B(n8340), .C(n7467), .D(n8286), .Y(n7471) );
NAND3BXLTS U8486 ( .AN(n7468), .B(n8479), .C(n8480), .Y(n7469) );
INVX2TS U8487 ( .A(n7469), .Y(n7470) );
NAND4XLTS U8488 ( .A(n8632), .B(n7472), .C(n7471), .D(n7470), .Y(n7473) );
OA22X1TS U8489 ( .A0(n7476), .A1(n7475), .B0(n7474), .B1(n7473), .Y(n7479)
);
AOI22X1TS U8490 ( .A0(n7480), .A1(n7479), .B0(n7478), .B1(n7477), .Y(n1626)
);
INVX2TS U8491 ( .A(n7488), .Y(n7481) );
INVX2TS U8492 ( .A(n7487), .Y(n7493) );
INVX2TS U8493 ( .A(n7487), .Y(n7483) );
OA22X1TS U8494 ( .A0(FPMULT_exp_oper_result[0]), .A1(n7488), .B0(n7485),
.B1(mult_result[23]), .Y(n1492) );
OA22X1TS U8495 ( .A0(FPMULT_exp_oper_result[1]), .A1(n7486), .B0(n7485),
.B1(mult_result[24]), .Y(n1491) );
OA22X1TS U8496 ( .A0(FPMULT_exp_oper_result[2]), .A1(n7486), .B0(n7485),
.B1(mult_result[25]), .Y(n1490) );
OA22X1TS U8497 ( .A0(FPMULT_exp_oper_result[3]), .A1(n7488), .B0(n7485),
.B1(mult_result[26]), .Y(n1489) );
OA22X1TS U8498 ( .A0(FPMULT_exp_oper_result[4]), .A1(n7486), .B0(n7485),
.B1(mult_result[27]), .Y(n1488) );
OA22X1TS U8499 ( .A0(FPMULT_exp_oper_result[5]), .A1(n7486), .B0(n7485),
.B1(mult_result[28]), .Y(n1487) );
OA22X1TS U8500 ( .A0(FPMULT_exp_oper_result[6]), .A1(n7486), .B0(n7487),
.B1(mult_result[29]), .Y(n1486) );
OA22X1TS U8501 ( .A0(FPMULT_exp_oper_result[7]), .A1(n7488), .B0(n7487),
.B1(mult_result[30]), .Y(n1485) );
OAI2BB1X1TS U8502 ( .A0N(mult_result[31]), .A1N(n7493), .B0(n7492), .Y(n1483) );
AOI21X1TS U8503 ( .A0(n7507), .A1(n8762), .B0(n7494), .Y(n7495) );
XNOR2X1TS U8504 ( .A(n7496), .B(n7495), .Y(n7497) );
OAI22X1TS U8505 ( .A0(n7503), .A1(n7502), .B0(n7501), .B1(n8757), .Y(n7505)
);
OAI21X1TS U8506 ( .A0(n8009), .A1(n2217), .B0(n8123), .Y(n7518) );
XNOR2X1TS U8507 ( .A(n7518), .B(n7511), .Y(n7504) );
XOR2X1TS U8508 ( .A(n7505), .B(n7504), .Y(n7506) );
OAI21X1TS U8509 ( .A0(n8091), .A1(n2222), .B0(n8090), .Y(n7513) );
AOI22X1TS U8510 ( .A0(n7570), .A1(n8608), .B0(n7513), .B1(n6864), .Y(n8759)
);
OAI21X1TS U8511 ( .A0(n8089), .A1(n2220), .B0(n8088), .Y(n7514) );
AOI22X1TS U8512 ( .A0(n7567), .A1(n8608), .B0(n7514), .B1(n6864), .Y(n8760)
);
OAI21X1TS U8513 ( .A0(n8087), .A1(n2221), .B0(n8086), .Y(n7516) );
AOI22X1TS U8514 ( .A0(n7568), .A1(n8608), .B0(n7516), .B1(n7537), .Y(n8761)
);
BUFX3TS U8515 ( .A(n7634), .Y(n7526) );
INVX2TS U8516 ( .A(n7663), .Y(n7648) );
INVX2TS U8517 ( .A(n7661), .Y(n7539) );
AOI22X1TS U8518 ( .A0(n7569), .A1(n8610), .B0(n7518), .B1(n7537), .Y(n8766)
);
OAI22X1TS U8519 ( .A0(n8612), .A1(n7523), .B0(n7522), .B1(n2413), .Y(n1410)
);
OAI21X1TS U8520 ( .A0(n8004), .A1(n2217), .B0(n8124), .Y(n7524) );
AOI22X1TS U8521 ( .A0(n7577), .A1(n8610), .B0(n7524), .B1(n7537), .Y(n8767)
);
OAI22X1TS U8522 ( .A0(n8612), .A1(n7828), .B0(n7525), .B1(n2374), .Y(n1407)
);
OAI21X1TS U8523 ( .A0(n8033), .A1(n2215), .B0(n8097), .Y(n7527) );
AOI22X1TS U8524 ( .A0(n7561), .A1(n8610), .B0(n7527), .B1(n7537), .Y(n8768)
);
OAI22X1TS U8525 ( .A0(n7557), .A1(n7829), .B0(n7528), .B1(n7627), .Y(n1404)
);
OAI21X1TS U8526 ( .A0(n8010), .A1(n2216), .B0(n8119), .Y(n7529) );
AOI22X1TS U8527 ( .A0(n7560), .A1(n8610), .B0(n7529), .B1(n7537), .Y(n8769)
);
BUFX3TS U8528 ( .A(n7634), .Y(n7550) );
OAI22X1TS U8529 ( .A0(n7557), .A1(n7830), .B0(n7530), .B1(n2374), .Y(n1401)
);
OAI21X1TS U8530 ( .A0(n8003), .A1(n2215), .B0(n8134), .Y(n7531) );
AOI22X1TS U8531 ( .A0(n7576), .A1(n8610), .B0(n7531), .B1(n7537), .Y(n8770)
);
OAI22X1TS U8532 ( .A0(n7557), .A1(n7831), .B0(n7532), .B1(n2374), .Y(n1398)
);
OAI22X1TS U8533 ( .A0(n7557), .A1(n7832), .B0(n7534), .B1(n2374), .Y(n1395)
);
OAI21X1TS U8534 ( .A0(n7999), .A1(n2216), .B0(n8099), .Y(n7535) );
AOI22X1TS U8535 ( .A0(n7656), .A1(n8610), .B0(n7535), .B1(n7537), .Y(n8772)
);
OAI22X1TS U8536 ( .A0(n7557), .A1(n7833), .B0(n7536), .B1(n2374), .Y(n1392)
);
OAI21X1TS U8537 ( .A0(n8012), .A1(n2217), .B0(n8098), .Y(n7538) );
AOI22X1TS U8538 ( .A0(n7652), .A1(n8610), .B0(n7538), .B1(n7537), .Y(n8773)
);
OAI22X1TS U8539 ( .A0(n7557), .A1(n7834), .B0(n7540), .B1(n2374), .Y(n1389)
);
OAI21X1TS U8540 ( .A0(n8005), .A1(n2215), .B0(n8139), .Y(n7541) );
AOI22X1TS U8541 ( .A0(n7582), .A1(n7633), .B0(n7541), .B1(n6864), .Y(n8774)
);
INVX2TS U8542 ( .A(n7661), .Y(n7605) );
OAI22X1TS U8543 ( .A0(n7557), .A1(n7835), .B0(n7542), .B1(n7627), .Y(n1386)
);
OAI22X1TS U8544 ( .A0(n7557), .A1(n7836), .B0(n7544), .B1(n7627), .Y(n1383)
);
OAI22X1TS U8545 ( .A0(n7557), .A1(n7837), .B0(n7546), .B1(n7627), .Y(n1380)
);
OAI22X1TS U8546 ( .A0(n7622), .A1(n7838), .B0(n7549), .B1(n7627), .Y(n1377)
);
OAI21X1TS U8547 ( .A0(n8007), .A1(n2216), .B0(n8133), .Y(n7551) );
AOI22X1TS U8548 ( .A0(n7633), .A1(n7583), .B0(n7551), .B1(n6864), .Y(n8778)
);
OAI22X1TS U8549 ( .A0(n7622), .A1(n7839), .B0(n7552), .B1(n2374), .Y(n1374)
);
OAI22X1TS U8550 ( .A0(n7622), .A1(n7840), .B0(n7554), .B1(n2413), .Y(n1371)
);
OAI21X1TS U8551 ( .A0(n8036), .A1(n2216), .B0(n8125), .Y(n7555) );
AOI22X1TS U8552 ( .A0(n7564), .A1(n7633), .B0(n7555), .B1(n6864), .Y(n8780)
);
OAI22X1TS U8553 ( .A0(n7557), .A1(n7841), .B0(n7556), .B1(n2413), .Y(n1368)
);
OAI22X1TS U8554 ( .A0(n7622), .A1(n7842), .B0(n7559), .B1(n2413), .Y(n1365)
);
NOR4X1TS U8555 ( .A(n3199), .B(n3200), .C(n3198), .D(n3197), .Y(n7593) );
AOI22X1TS U8556 ( .A0(n8785), .A1(n7571), .B0(n8802), .B1(n7620), .Y(n7572)
);
NOR4X1TS U8557 ( .A(n3196), .B(n3195), .C(n3169), .D(n7573), .Y(n7592) );
AOI22X1TS U8558 ( .A0(n7578), .A1(n8828), .B0(n8826), .B1(n7656), .Y(n7579)
);
AOI22X1TS U8559 ( .A0(n7617), .A1(n8799), .B0(n8787), .B1(n7580), .Y(n7588)
);
AOI22X1TS U8560 ( .A0(n7611), .A1(n8793), .B0(n8790), .B1(n7608), .Y(n7587)
);
AOI22X1TS U8561 ( .A0(n7582), .A1(n5945), .B0(n5942), .B1(n7581), .Y(n7586)
);
AOI22X1TS U8562 ( .A0(n7584), .A1(n5946), .B0(n8817), .B1(n7583), .Y(n7585)
);
NAND4XLTS U8563 ( .A(n7588), .B(n7587), .C(n7586), .D(n7585), .Y(n7589) );
NOR4X1TS U8564 ( .A(n3170), .B(n3201), .C(n7590), .D(n7589), .Y(n7591) );
CLKXOR2X2TS U8565 ( .A(n7594), .B(FPADDSUB_intAS), .Y(n7601) );
OAI22X1TS U8566 ( .A0(n7602), .A1(n7596), .B0(n7595), .B1(n7601), .Y(n7597)
);
OAI22X1TS U8567 ( .A0(n7622), .A1(n7843), .B0(n7606), .B1(n2413), .Y(n1331)
);
AOI22X1TS U8568 ( .A0(n7608), .A1(n8608), .B0(n7607), .B1(n6862), .Y(n8789)
);
OAI22X1TS U8569 ( .A0(n7622), .A1(n7844), .B0(n7609), .B1(n2413), .Y(n1315)
);
AOI22X1TS U8570 ( .A0(n7611), .A1(n8608), .B0(n7610), .B1(n7624), .Y(n8792)
);
OAI22X1TS U8571 ( .A0(n7622), .A1(n7845), .B0(n7612), .B1(n2413), .Y(n1308)
);
AOI22X1TS U8572 ( .A0(n7614), .A1(n6863), .B0(n7613), .B1(n7624), .Y(n8795)
);
OAI22X1TS U8573 ( .A0(n7622), .A1(n7846), .B0(n7615), .B1(n2413), .Y(n1301)
);
AOI22X1TS U8574 ( .A0(n7617), .A1(n8608), .B0(n7616), .B1(n7624), .Y(n8798)
);
OAI22X1TS U8575 ( .A0(n7622), .A1(n7847), .B0(n7618), .B1(n2413), .Y(n1294)
);
AOI22X1TS U8576 ( .A0(n7620), .A1(n8608), .B0(n7619), .B1(n7624), .Y(n8801)
);
OAI22X1TS U8577 ( .A0(n7622), .A1(n7848), .B0(n7621), .B1(n7627), .Y(n1287)
);
INVX2TS U8578 ( .A(n7665), .Y(n7645) );
OAI21X1TS U8579 ( .A0(n8037), .A1(n2222), .B0(n8100), .Y(n7626) );
AOI22X1TS U8580 ( .A0(n7625), .A1(n8608), .B0(n7626), .B1(n7624), .Y(n8804)
);
OAI22X1TS U8581 ( .A0(n7629), .A1(n7849), .B0(n7628), .B1(n2413), .Y(n1280)
);
OAI21X1TS U8582 ( .A0(n8015), .A1(n2215), .B0(n8136), .Y(n7635) );
AOI22X1TS U8583 ( .A0(n7638), .A1(n7633), .B0(n7635), .B1(n7636), .Y(n8808)
);
BUFX3TS U8584 ( .A(n7634), .Y(n7650) );
OAI21X1TS U8585 ( .A0(n8015), .A1(n2220), .B0(n8101), .Y(n7639) );
AOI22X1TS U8586 ( .A0(n7638), .A1(n7637), .B0(n7639), .B1(n7636), .Y(n8809)
);
INVX2TS U8587 ( .A(n7663), .Y(n7664) );
INVX2TS U8588 ( .A(n7665), .Y(n7667) );
OAI21X1TS U8589 ( .A0(n8012), .A1(n2220), .B0(n8081), .Y(n7653) );
AOI22X1TS U8590 ( .A0(n7652), .A1(n7655), .B0(n7653), .B1(n7654), .Y(n8823)
);
OAI21X1TS U8591 ( .A0(n7999), .A1(n2221), .B0(n8082), .Y(n7657) );
AOI22X1TS U8592 ( .A0(n7656), .A1(n7655), .B0(n7657), .B1(n7654), .Y(n8825)
);
AO22XLTS U8593 ( .A0(n8838), .A1(FPADDSUB_DMP_SHT1_EWSW[15]), .B0(n7939),
.B1(FPADDSUB_DMP_SHT2_EWSW[15]), .Y(n1213) );
AO22XLTS U8594 ( .A0(n8838), .A1(FPADDSUB_DMP_SHT1_EWSW[22]), .B0(n7939),
.B1(FPADDSUB_DMP_SHT2_EWSW[22]), .Y(n1209) );
initial $sdf_annotate("FPU_Interface2_RKOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_RKOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_RKOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_RKOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_RKOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_RKOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_RKOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_RKOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_RKOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_RKOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_RKOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_RKOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_RKOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_RKOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_RKOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_noclk.tcl_RKOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk1.tcl_RKOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk10.tcl_RKOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk20.tcl_RKOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk30.tcl_RKOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk40.tcl_RKOA_1STAGE_syn.sdf");
initial $sdf_annotate("FPU_Interface2_ASIC_fpu_syn_constraints_clk1.tcl_RKOA_1STAGE_syn.sdf");
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlconcat:2.1
// IP Revision: 2
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module image_processing_2d_design_xlconcat_0_0 (
In0,
In1,
dout
);
input wire [0 : 0] In0;
input wire [0 : 0] In1;
output wire [1 : 0] dout;
xlconcat #(
.IN0_WIDTH(1),
.IN1_WIDTH(1),
.IN2_WIDTH(1),
.IN3_WIDTH(1),
.IN4_WIDTH(1),
.IN5_WIDTH(1),
.IN6_WIDTH(1),
.IN7_WIDTH(1),
.IN8_WIDTH(1),
.IN9_WIDTH(1),
.IN10_WIDTH(1),
.IN11_WIDTH(1),
.IN12_WIDTH(1),
.IN13_WIDTH(1),
.IN14_WIDTH(1),
.IN15_WIDTH(1),
.IN16_WIDTH(1),
.IN17_WIDTH(1),
.IN18_WIDTH(1),
.IN19_WIDTH(1),
.IN20_WIDTH(1),
.IN21_WIDTH(1),
.IN22_WIDTH(1),
.IN23_WIDTH(1),
.IN24_WIDTH(1),
.IN25_WIDTH(1),
.IN26_WIDTH(1),
.IN27_WIDTH(1),
.IN28_WIDTH(1),
.IN29_WIDTH(1),
.IN30_WIDTH(1),
.IN31_WIDTH(1),
.dout_width(2),
.NUM_PORTS(2)
) inst (
.In0(In0),
.In1(In1),
.In2(1'B0),
.In3(1'B0),
.In4(1'B0),
.In5(1'B0),
.In6(1'B0),
.In7(1'B0),
.In8(1'B0),
.In9(1'B0),
.In10(1'B0),
.In11(1'B0),
.In12(1'B0),
.In13(1'B0),
.In14(1'B0),
.In15(1'B0),
.In16(1'B0),
.In17(1'B0),
.In18(1'B0),
.In19(1'B0),
.In20(1'B0),
.In21(1'B0),
.In22(1'B0),
.In23(1'B0),
.In24(1'B0),
.In25(1'B0),
.In26(1'B0),
.In27(1'B0),
.In28(1'B0),
.In29(1'B0),
.In30(1'B0),
.In31(1'B0),
.dout(dout)
);
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:fifo_generator:13.1
// IP Revision: 4
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module fifo_bt_txd (
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty
);
input wire rst;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 write_clk CLK" *)
input wire wr_clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 read_clk CLK" *)
input wire rd_clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *)
input wire [7 : 0] din;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *)
input wire wr_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *)
input wire rd_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *)
output wire [7 : 0] dout;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *)
output wire full;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *)
output wire empty;
fifo_generator_v13_1_4 #(
.C_COMMON_CLOCK(0),
.C_SELECT_XPM(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(10),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(8),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(8),
.C_ENABLE_RLOCS(0),
.C_FAMILY("artix7"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("1kx18"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(1022),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_PIPELINE_REG(0),
.C_POWER_SAVING_MODE(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(1024),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_EN_SAFETY_CKT(0),
.C_ERROR_INJECTION_TYPE(0),
.C_SYNCHRONIZER_STAGE(2),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_HAS_AXI_WR_CHANNEL(1),
.C_HAS_AXI_RD_CHANNEL(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(1),
.C_HAS_AXI_ID(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(1),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(1),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(8),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(1),
.C_AXIS_TKEEP_WIDTH(1),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_PRIM_FIFO_TYPE_WACH("512x36"),
.C_PRIM_FIFO_TYPE_WDCH("1kx36"),
.C_PRIM_FIFO_TYPE_WRCH("512x36"),
.C_PRIM_FIFO_TYPE_RACH("512x36"),
.C_PRIM_FIFO_TYPE_RDCH("1kx36"),
.C_PRIM_FIFO_TYPE_AXIS("1kx18"),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_WACH(1),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0)
) inst (
.backup(1'D0),
.backup_marker(1'D0),
.clk(1'D0),
.rst(rst),
.srst(1'D0),
.wr_clk(wr_clk),
.wr_rst(1'D0),
.rd_clk(rd_clk),
.rd_rst(1'D0),
.din(din),
.wr_en(wr_en),
.rd_en(rd_en),
.prog_empty_thresh(10'B0),
.prog_empty_thresh_assert(10'B0),
.prog_empty_thresh_negate(10'B0),
.prog_full_thresh(10'B0),
.prog_full_thresh_assert(10'B0),
.prog_full_thresh_negate(10'B0),
.int_clk(1'D0),
.injectdbiterr(1'D0),
.injectsbiterr(1'D0),
.sleep(1'D0),
.dout(dout),
.full(full),
.almost_full(),
.wr_ack(),
.overflow(),
.empty(empty),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.wr_rst_busy(),
.rd_rst_busy(),
.m_aclk(1'D0),
.s_aclk(1'D0),
.s_aresetn(1'D0),
.m_aclk_en(1'D0),
.s_aclk_en(1'D0),
.s_axi_awid(1'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awlock(1'B0),
.s_axi_awcache(4'B0),
.s_axi_awprot(3'B0),
.s_axi_awqos(4'B0),
.s_axi_awregion(4'B0),
.s_axi_awuser(1'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wid(1'B0),
.s_axi_wdata(64'B0),
.s_axi_wstrb(8'B0),
.s_axi_wlast(1'D0),
.s_axi_wuser(1'B0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'D0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'D0),
.m_axi_bid(1'B0),
.m_axi_bresp(2'B0),
.m_axi_buser(1'B0),
.m_axi_bvalid(1'D0),
.m_axi_bready(),
.s_axi_arid(1'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arlock(1'B0),
.s_axi_arcache(4'B0),
.s_axi_arprot(3'B0),
.s_axi_arqos(4'B0),
.s_axi_arregion(4'B0),
.s_axi_aruser(1'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'D0),
.m_axi_rid(1'B0),
.m_axi_rdata(64'B0),
.m_axi_rresp(2'B0),
.m_axi_rlast(1'D0),
.m_axi_ruser(1'B0),
.m_axi_rvalid(1'D0),
.m_axi_rready(),
.s_axis_tvalid(1'D0),
.s_axis_tready(),
.s_axis_tdata(8'B0),
.s_axis_tstrb(1'B0),
.s_axis_tkeep(1'B0),
.s_axis_tlast(1'D0),
.s_axis_tid(1'B0),
.s_axis_tdest(1'B0),
.s_axis_tuser(4'B0),
.m_axis_tvalid(),
.m_axis_tready(1'D0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'D0),
.axi_aw_injectdbiterr(1'D0),
.axi_aw_prog_full_thresh(4'B0),
.axi_aw_prog_empty_thresh(4'B0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'D0),
.axi_w_injectdbiterr(1'D0),
.axi_w_prog_full_thresh(10'B0),
.axi_w_prog_empty_thresh(10'B0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectsbiterr(1'D0),
.axi_b_injectdbiterr(1'D0),
.axi_b_prog_full_thresh(4'B0),
.axi_b_prog_empty_thresh(4'B0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectsbiterr(1'D0),
.axi_ar_injectdbiterr(1'D0),
.axi_ar_prog_full_thresh(4'B0),
.axi_ar_prog_empty_thresh(4'B0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'D0),
.axi_r_injectdbiterr(1'D0),
.axi_r_prog_full_thresh(10'B0),
.axi_r_prog_empty_thresh(10'B0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectsbiterr(1'D0),
.axis_injectdbiterr(1'D0),
.axis_prog_full_thresh(10'B0),
.axis_prog_empty_thresh(10'B0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty()
);
endmodule
|
// +----------------------------------------------------------------------------
// GNU General Public License
// -----------------------------------------------------------------------------
// This file is part of uDLX (micro-DeLuX) soft IP-core.
//
// uDLX is free soft IP-core: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// uDLX soft core is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with uDLX. If not, see <http://www.gnu.org/licenses/>.
// +----------------------------------------------------------------------------
// PROJECT: uDLX core Processor
// ------------------------------------------------------------------------------
// FILE NAME : top_fetch.v
// KEYWORDS : instruction fetch, program counter, pc, dlx
// -----------------------------------------------------------------------------
// PURPOSE:
// -----------------------------------------------------------------------------
module top_fetch
#(
parameter PC_DATA_WIDTH = 20,
parameter INSTRUCTION_WIDTH = 32,
parameter PC_INITIAL_ADDRESS = 20'h0
)(
input clk, // CPU core clock
input rst_n, // CPU core reset active low
input en,
input stall, // Indicates a stall insertion on the datapath
// input flush, // Force flush in pipeline registers
// input [INSTRUCTION_WIDTH-1:0] inst_mem_data_in, // SRAM input data
input select_new_pc_in, // Signal used for branch not taken
input [PC_DATA_WIDTH-1:0] new_pc_in, // New value of Program Counter
// output reg [PC_DATA_WIDTH-1:0] new_pc_out, // Updated value of the Program Counter
output [PC_DATA_WIDTH-1:0] pc_out, // Value of the Program Counter
// output reg [INSTRUCTION_WIDTH-1:0] instruction_reg_out, // CPU core fetched instruction
output [PC_DATA_WIDTH-1:0] inst_mem_addr_out, // Instruction SRAM address bus
input boot_mode
);
reg [PC_DATA_WIDTH-1:0] pc;
reg [PC_DATA_WIDTH-1:0] pc_mux_data;
reg [PC_DATA_WIDTH-1:0] pc_adder_data;
// -------------------------------------------------------------
// Multiplex to select new PC value
// -------------------------------------------------------------
always@(*)
begin
case(select_new_pc_in)
0 : pc_mux_data = pc_adder_data;
1 : pc_mux_data = new_pc_in;
endcase
end
// -------------------------------------------------------------
// Program Counter adder
// -------------------------------------------------------------
always@(*)
begin
pc_adder_data = pc + 20'd4;
end
// -------------------------------------------------------------
// Program Counter regireg [FUNCTION_WIDTH-1:0] inst_function,ster
// -------------------------------------------------------------
assign inst_mem_addr_out = pc;
always@(posedge clk or negedge rst_n) begin
if(!rst_n) begin
pc <= PC_INITIAL_ADDRESS;
end
else if (boot_mode) begin
pc <= PC_INITIAL_ADDRESS;
end
else if((!stall)&en) begin
pc <= pc_mux_data;
end
end
assign pc_out = pc;
// -------------------------------------------------------------
// Pipeline Registers
// The if_id pipe needs only this
// ++TODO: Plance this procedure into a module.
// -------------------------------------------------------------
// always@(posedge clk or negedge rst_n)begin
// if(!rst_n) begin
// new_pc_out <= 0;
// instruction_reg_out <= 0;
// end else if(!stall)begin
// new_pc_out <= pc;
// if(flush)begin
// instruction_reg_out <= 0;
// end
// else begin
// instruction_reg_out <= inst_mem_data_in;
// end
// end
// end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFXBP_PP_SYMBOL_V
`define SKY130_FD_SC_LS__DFXBP_PP_SYMBOL_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dfxbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFXBP_PP_SYMBOL_V
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
*
* (C)2012 Korotkyi Ievgen
* National Technical University of Ukraine "Kiev Polytechnic Institute"
* -------------------------------------------------------------------------------
*
* Physical-Channel (Channel-level) Flow-Control
* ============================================
*
* Supports
* - credit flow-control
*
* Credit Counter Optimization (for credit-based flow-control)
* ===========================
*
* optimized_credit_counter = 0 | 1
*
* Set to '1' to move credit counter logic to start of next clock cycle.
* Remove add/sub from critical path.
*
* To move add/sub logic we buffer the last credit rec. and the any
* flit sent on the output.
*
*/
module LAG_pl_fc_out (flits_valid,
channel_cntrl_in,
pl_status, // pl_status[pl]=1 if blocked (fifo is full)
// only when using credit-based flow control
pl_empty, // pl_empty[pl]=1 if PL fifo is empty (credits=init_credits)
pl_credits,
clk, rst_n);
`include "LAG_functions.v"
parameter num_pls = 4;
parameter init_credits = 4;
parameter optimized_credit_counter = 1;
// +1 as has to hold 'init_credits' value
parameter counter_bits = clogb2(init_credits+1);
input [num_pls-1:0] flits_valid;
input chan_cntrl_t channel_cntrl_in;
output pl_t pl_status;
output [num_pls-1:0] pl_empty;
output [num_pls-1:0][counter_bits-1:0] pl_credits;
input clk, rst_n;
logic [num_pls-1:0][counter_bits-1:0] counter;
logic [num_pls-1:0] inc, dec;
// buffer credit and flit pl id.'s so we can move counter in credit counter optimization
logic [num_pls-1:0] last_flits_valid;
pl_t last_credits;
logic [num_pls-1:0][counter_bits-1:0] counter_current;
logic [num_pls-1:0] pl_empty;
genvar i;
// fsm states
parameter stop=1'b0, go=1'b1;
logic [num_pls-1:0] current_state, next_state;
generate
if (optimized_credit_counter) begin
// ***********************************
// optimized credit-counter (moves counter logic off critical path)
// ***********************************
always@(posedge clk) begin
last_credits <= channel_cntrl_in.credits;
last_flits_valid <= flits_valid;
// $display ("empty=%b", pl_empty);
end
assign pl_credits = counter_current;
for (i=0; i<num_pls; i++) begin:perpl1
always_comb begin:addsub
if (inc[i] && !dec[i])
counter_current[i]=counter[i]+1;
else if (dec[i] && !inc[i])
counter_current[i]=counter[i]-1;
else
counter_current[i]=counter[i];
end
always@(posedge clk) begin
if (!rst_n) begin
counter[i]<=init_credits;
pl_empty[i]<='1;
end else begin
counter[i]<=counter_current[i];
if ((counter_current[i]==0) ||
((counter_current[i]==1) && flits_valid[i]) &&
!(channel_cntrl_in.credits[i])) begin
pl_status[i] <= 1'b1;
pl_empty[i] <= 1'b0;
end else begin
pl_status[i] <= 1'b0;
pl_empty[i] <= (counter_current[i]==init_credits);
end
end // else: !if(!rst_n)
end // always@ (posedge clk)
assign inc[i] = last_credits[i];
assign dec[i] = last_flits_valid[i];
end
end else begin
assign pl_credits = counter;
// ***********************************
// unoptimized credit-counter
// ***********************************
for (i=0; i<num_pls; i++) begin:perpl
always@(posedge clk) begin
if (!rst_n) begin
counter[i]<=init_credits;
end else begin
if (inc[i] && !dec[i]) begin
assert (counter[i]!=init_credits) else $fatal;
counter[i]<=counter[i]+1;
end
if (dec[i] && !inc[i]) begin
assert (counter[i]!=0) else $fatal;
counter[i]<=counter[i]-1;
end
end // else: !if(!rst_n)
end
// received credit for PL i?
assign inc[i]= channel_cntrl_in.credits[i];
// flit sent, one less credit
assign dec[i] = flits_valid[i];
// if counter==0, PL is blocked
assign pl_status[i]=(counter[i]==0);
// if counter==init_credits, PL buffer is empty
assign pl_empty[i]=(counter[i]==init_credits);
end // block: perpl
end
endgenerate
endmodule
|
// megafunction wizard: %ALTIOBUF%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altiobuf_bidir
// ============================================================
// File Name: bidirbuf.v
// Megafunction Name(s):
// altiobuf_bidir
//
// Simulation Library Files(s):
// cyclonev
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.0.0 Build 200 06/17/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
//altiobuf_bidir CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone V" ENABLE_BUS_HOLD="FALSE" NUMBER_OF_CHANNELS=16 OPEN_DRAIN_OUTPUT="FALSE" USE_DIFFERENTIAL_MODE="FALSE" USE_DYNAMIC_TERMINATION_CONTROL="FALSE" USE_TERMINATION_CONTROL="FALSE" datain dataio dataout oe
//VERSION_BEGIN 14.0 cbx_altiobuf_bidir 2014:06:05:09:45:41:SJ cbx_mgl 2014:06:05:10:17:12:SJ cbx_stratixiii 2014:06:05:09:45:41:SJ cbx_stratixv 2014:06:05:09:45:41:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = cyclonev_io_ibuf 16 cyclonev_io_obuf 16
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module bidirbuf_iobuf_bidir_bqo
(
datain,
dataio,
dataout,
oe) ;
input [15:0] datain;
inout [15:0] dataio;
output [15:0] dataout;
input [15:0] oe;
wire [15:0] wire_ibufa_i;
wire [15:0] wire_ibufa_o;
wire [15:0] wire_obufa_i;
wire [15:0] wire_obufa_o;
wire [15:0] wire_obufa_oe;
cyclonev_io_ibuf ibufa_0
(
.i(wire_ibufa_i[0:0]),
.o(wire_ibufa_o[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.ibar(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
ibufa_0.bus_hold = "false",
ibufa_0.differential_mode = "false",
ibufa_0.lpm_type = "cyclonev_io_ibuf";
cyclonev_io_ibuf ibufa_1
(
.i(wire_ibufa_i[1:1]),
.o(wire_ibufa_o[1:1])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.ibar(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
ibufa_1.bus_hold = "false",
ibufa_1.differential_mode = "false",
ibufa_1.lpm_type = "cyclonev_io_ibuf";
cyclonev_io_ibuf ibufa_2
(
.i(wire_ibufa_i[2:2]),
.o(wire_ibufa_o[2:2])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.ibar(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
ibufa_2.bus_hold = "false",
ibufa_2.differential_mode = "false",
ibufa_2.lpm_type = "cyclonev_io_ibuf";
cyclonev_io_ibuf ibufa_3
(
.i(wire_ibufa_i[3:3]),
.o(wire_ibufa_o[3:3])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.ibar(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
ibufa_3.bus_hold = "false",
ibufa_3.differential_mode = "false",
ibufa_3.lpm_type = "cyclonev_io_ibuf";
cyclonev_io_ibuf ibufa_4
(
.i(wire_ibufa_i[4:4]),
.o(wire_ibufa_o[4:4])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.ibar(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
ibufa_4.bus_hold = "false",
ibufa_4.differential_mode = "false",
ibufa_4.lpm_type = "cyclonev_io_ibuf";
cyclonev_io_ibuf ibufa_5
(
.i(wire_ibufa_i[5:5]),
.o(wire_ibufa_o[5:5])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.ibar(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
ibufa_5.bus_hold = "false",
ibufa_5.differential_mode = "false",
ibufa_5.lpm_type = "cyclonev_io_ibuf";
cyclonev_io_ibuf ibufa_6
(
.i(wire_ibufa_i[6:6]),
.o(wire_ibufa_o[6:6])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.ibar(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
ibufa_6.bus_hold = "false",
ibufa_6.differential_mode = "false",
ibufa_6.lpm_type = "cyclonev_io_ibuf";
cyclonev_io_ibuf ibufa_7
(
.i(wire_ibufa_i[7:7]),
.o(wire_ibufa_o[7:7])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.ibar(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
ibufa_7.bus_hold = "false",
ibufa_7.differential_mode = "false",
ibufa_7.lpm_type = "cyclonev_io_ibuf";
cyclonev_io_ibuf ibufa_8
(
.i(wire_ibufa_i[8:8]),
.o(wire_ibufa_o[8:8])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.ibar(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
ibufa_8.bus_hold = "false",
ibufa_8.differential_mode = "false",
ibufa_8.lpm_type = "cyclonev_io_ibuf";
cyclonev_io_ibuf ibufa_9
(
.i(wire_ibufa_i[9:9]),
.o(wire_ibufa_o[9:9])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.ibar(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
ibufa_9.bus_hold = "false",
ibufa_9.differential_mode = "false",
ibufa_9.lpm_type = "cyclonev_io_ibuf";
cyclonev_io_ibuf ibufa_10
(
.i(wire_ibufa_i[10:10]),
.o(wire_ibufa_o[10:10])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.ibar(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
ibufa_10.bus_hold = "false",
ibufa_10.differential_mode = "false",
ibufa_10.lpm_type = "cyclonev_io_ibuf";
cyclonev_io_ibuf ibufa_11
(
.i(wire_ibufa_i[11:11]),
.o(wire_ibufa_o[11:11])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.ibar(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
ibufa_11.bus_hold = "false",
ibufa_11.differential_mode = "false",
ibufa_11.lpm_type = "cyclonev_io_ibuf";
cyclonev_io_ibuf ibufa_12
(
.i(wire_ibufa_i[12:12]),
.o(wire_ibufa_o[12:12])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.ibar(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
ibufa_12.bus_hold = "false",
ibufa_12.differential_mode = "false",
ibufa_12.lpm_type = "cyclonev_io_ibuf";
cyclonev_io_ibuf ibufa_13
(
.i(wire_ibufa_i[13:13]),
.o(wire_ibufa_o[13:13])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.ibar(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
ibufa_13.bus_hold = "false",
ibufa_13.differential_mode = "false",
ibufa_13.lpm_type = "cyclonev_io_ibuf";
cyclonev_io_ibuf ibufa_14
(
.i(wire_ibufa_i[14:14]),
.o(wire_ibufa_o[14:14])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.ibar(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
ibufa_14.bus_hold = "false",
ibufa_14.differential_mode = "false",
ibufa_14.lpm_type = "cyclonev_io_ibuf";
cyclonev_io_ibuf ibufa_15
(
.i(wire_ibufa_i[15:15]),
.o(wire_ibufa_o[15:15])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.ibar(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
ibufa_15.bus_hold = "false",
ibufa_15.differential_mode = "false",
ibufa_15.lpm_type = "cyclonev_io_ibuf";
assign
wire_ibufa_i = dataio;
cyclonev_io_obuf obufa_0
(
.i(wire_obufa_i[0:0]),
.o(wire_obufa_o[0:0]),
.obar(),
.oe(wire_obufa_oe[0:0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_0.bus_hold = "false",
obufa_0.open_drain_output = "false",
obufa_0.lpm_type = "cyclonev_io_obuf";
cyclonev_io_obuf obufa_1
(
.i(wire_obufa_i[1:1]),
.o(wire_obufa_o[1:1]),
.obar(),
.oe(wire_obufa_oe[1:1])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_1.bus_hold = "false",
obufa_1.open_drain_output = "false",
obufa_1.lpm_type = "cyclonev_io_obuf";
cyclonev_io_obuf obufa_2
(
.i(wire_obufa_i[2:2]),
.o(wire_obufa_o[2:2]),
.obar(),
.oe(wire_obufa_oe[2:2])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_2.bus_hold = "false",
obufa_2.open_drain_output = "false",
obufa_2.lpm_type = "cyclonev_io_obuf";
cyclonev_io_obuf obufa_3
(
.i(wire_obufa_i[3:3]),
.o(wire_obufa_o[3:3]),
.obar(),
.oe(wire_obufa_oe[3:3])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_3.bus_hold = "false",
obufa_3.open_drain_output = "false",
obufa_3.lpm_type = "cyclonev_io_obuf";
cyclonev_io_obuf obufa_4
(
.i(wire_obufa_i[4:4]),
.o(wire_obufa_o[4:4]),
.obar(),
.oe(wire_obufa_oe[4:4])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_4.bus_hold = "false",
obufa_4.open_drain_output = "false",
obufa_4.lpm_type = "cyclonev_io_obuf";
cyclonev_io_obuf obufa_5
(
.i(wire_obufa_i[5:5]),
.o(wire_obufa_o[5:5]),
.obar(),
.oe(wire_obufa_oe[5:5])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_5.bus_hold = "false",
obufa_5.open_drain_output = "false",
obufa_5.lpm_type = "cyclonev_io_obuf";
cyclonev_io_obuf obufa_6
(
.i(wire_obufa_i[6:6]),
.o(wire_obufa_o[6:6]),
.obar(),
.oe(wire_obufa_oe[6:6])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_6.bus_hold = "false",
obufa_6.open_drain_output = "false",
obufa_6.lpm_type = "cyclonev_io_obuf";
cyclonev_io_obuf obufa_7
(
.i(wire_obufa_i[7:7]),
.o(wire_obufa_o[7:7]),
.obar(),
.oe(wire_obufa_oe[7:7])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_7.bus_hold = "false",
obufa_7.open_drain_output = "false",
obufa_7.lpm_type = "cyclonev_io_obuf";
cyclonev_io_obuf obufa_8
(
.i(wire_obufa_i[8:8]),
.o(wire_obufa_o[8:8]),
.obar(),
.oe(wire_obufa_oe[8:8])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_8.bus_hold = "false",
obufa_8.open_drain_output = "false",
obufa_8.lpm_type = "cyclonev_io_obuf";
cyclonev_io_obuf obufa_9
(
.i(wire_obufa_i[9:9]),
.o(wire_obufa_o[9:9]),
.obar(),
.oe(wire_obufa_oe[9:9])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_9.bus_hold = "false",
obufa_9.open_drain_output = "false",
obufa_9.lpm_type = "cyclonev_io_obuf";
cyclonev_io_obuf obufa_10
(
.i(wire_obufa_i[10:10]),
.o(wire_obufa_o[10:10]),
.obar(),
.oe(wire_obufa_oe[10:10])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_10.bus_hold = "false",
obufa_10.open_drain_output = "false",
obufa_10.lpm_type = "cyclonev_io_obuf";
cyclonev_io_obuf obufa_11
(
.i(wire_obufa_i[11:11]),
.o(wire_obufa_o[11:11]),
.obar(),
.oe(wire_obufa_oe[11:11])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_11.bus_hold = "false",
obufa_11.open_drain_output = "false",
obufa_11.lpm_type = "cyclonev_io_obuf";
cyclonev_io_obuf obufa_12
(
.i(wire_obufa_i[12:12]),
.o(wire_obufa_o[12:12]),
.obar(),
.oe(wire_obufa_oe[12:12])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_12.bus_hold = "false",
obufa_12.open_drain_output = "false",
obufa_12.lpm_type = "cyclonev_io_obuf";
cyclonev_io_obuf obufa_13
(
.i(wire_obufa_i[13:13]),
.o(wire_obufa_o[13:13]),
.obar(),
.oe(wire_obufa_oe[13:13])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_13.bus_hold = "false",
obufa_13.open_drain_output = "false",
obufa_13.lpm_type = "cyclonev_io_obuf";
cyclonev_io_obuf obufa_14
(
.i(wire_obufa_i[14:14]),
.o(wire_obufa_o[14:14]),
.obar(),
.oe(wire_obufa_oe[14:14])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_14.bus_hold = "false",
obufa_14.open_drain_output = "false",
obufa_14.lpm_type = "cyclonev_io_obuf";
cyclonev_io_obuf obufa_15
(
.i(wire_obufa_i[15:15]),
.o(wire_obufa_o[15:15]),
.obar(),
.oe(wire_obufa_oe[15:15])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dynamicterminationcontrol(1'b0),
.parallelterminationcontrol({16{1'b0}}),
.seriesterminationcontrol({16{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
// synopsys translate_off
,
.devoe(1'b1)
// synopsys translate_on
);
defparam
obufa_15.bus_hold = "false",
obufa_15.open_drain_output = "false",
obufa_15.lpm_type = "cyclonev_io_obuf";
assign
wire_obufa_i = datain,
wire_obufa_oe = oe;
assign
dataio = wire_obufa_o,
dataout = wire_ibufa_o;
endmodule //bidirbuf_iobuf_bidir_bqo
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module bidirbuf (
datain,
oe,
dataio,
dataout);
input [15:0] datain;
input [15:0] oe;
inout [15:0] dataio;
output [15:0] dataout;
wire [15:0] sub_wire0;
wire [15:0] dataout = sub_wire0[15:0];
bidirbuf_iobuf_bidir_bqo bidirbuf_iobuf_bidir_bqo_component (
.datain (datain),
.oe (oe),
.dataio (dataio),
.dataout (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: enable_bus_hold STRING "FALSE"
// Retrieval info: CONSTANT: left_shift_series_termination_control STRING "FALSE"
// Retrieval info: CONSTANT: number_of_channels NUMERIC "16"
// Retrieval info: CONSTANT: open_drain_output STRING "FALSE"
// Retrieval info: CONSTANT: use_differential_mode STRING "FALSE"
// Retrieval info: CONSTANT: use_dynamic_termination_control STRING "FALSE"
// Retrieval info: CONSTANT: use_termination_control STRING "FALSE"
// Retrieval info: USED_PORT: datain 0 0 16 0 INPUT NODEFVAL "datain[15..0]"
// Retrieval info: USED_PORT: dataio 0 0 16 0 BIDIR NODEFVAL "dataio[15..0]"
// Retrieval info: USED_PORT: dataout 0 0 16 0 OUTPUT NODEFVAL "dataout[15..0]"
// Retrieval info: USED_PORT: oe 0 0 16 0 INPUT NODEFVAL "oe[15..0]"
// Retrieval info: CONNECT: @datain 0 0 16 0 datain 0 0 16 0
// Retrieval info: CONNECT: @oe 0 0 16 0 oe 0 0 16 0
// Retrieval info: CONNECT: dataio 0 0 16 0 @dataio 0 0 16 0
// Retrieval info: CONNECT: dataout 0 0 16 0 @dataout 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL bidirbuf.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL bidirbuf.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bidirbuf.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bidirbuf.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bidirbuf_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL bidirbuf_bb.v TRUE
// Retrieval info: LIB_FILE: cyclonev
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Mon Sep 18 13:10:43 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ fifo_generator_rx_inst_sim_netlist.v
// Design : fifo_generator_rx_inst
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "fifo_generator_rx_inst,fifo_generator_v13_1_2,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
rd_data_count,
wr_data_count,
prog_full,
prog_empty);
input rst;
(* x_interface_info = "xilinx.com:signal:clock:1.0 write_clk CLK" *) input wr_clk;
(* x_interface_info = "xilinx.com:signal:clock:1.0 read_clk CLK" *) input rd_clk;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [63:0]din;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [63:0]dout;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty;
output [9:0]rd_data_count;
output [8:0]wr_data_count;
output prog_full;
output prog_empty;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire prog_empty;
wire prog_full;
wire rd_clk;
wire [9:0]rd_data_count;
wire rd_en;
wire rst;
wire wr_clk;
wire [8:0]wr_data_count;
wire wr_en;
wire NLW_U0_almost_empty_UNCONNECTED;
wire NLW_U0_almost_full_UNCONNECTED;
wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_overflow_UNCONNECTED;
wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_underflow_UNCONNECTED;
wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_overflow_UNCONNECTED;
wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_underflow_UNCONNECTED;
wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
wire NLW_U0_axi_b_overflow_UNCONNECTED;
wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
wire NLW_U0_axi_b_prog_full_UNCONNECTED;
wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
wire NLW_U0_axi_b_underflow_UNCONNECTED;
wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
wire NLW_U0_axi_r_overflow_UNCONNECTED;
wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
wire NLW_U0_axi_r_prog_full_UNCONNECTED;
wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
wire NLW_U0_axi_r_underflow_UNCONNECTED;
wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
wire NLW_U0_axi_w_overflow_UNCONNECTED;
wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
wire NLW_U0_axi_w_prog_full_UNCONNECTED;
wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
wire NLW_U0_axi_w_underflow_UNCONNECTED;
wire NLW_U0_axis_dbiterr_UNCONNECTED;
wire NLW_U0_axis_overflow_UNCONNECTED;
wire NLW_U0_axis_prog_empty_UNCONNECTED;
wire NLW_U0_axis_prog_full_UNCONNECTED;
wire NLW_U0_axis_sbiterr_UNCONNECTED;
wire NLW_U0_axis_underflow_UNCONNECTED;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_m_axi_arvalid_UNCONNECTED;
wire NLW_U0_m_axi_awvalid_UNCONNECTED;
wire NLW_U0_m_axi_bready_UNCONNECTED;
wire NLW_U0_m_axi_rready_UNCONNECTED;
wire NLW_U0_m_axi_wlast_UNCONNECTED;
wire NLW_U0_m_axi_wvalid_UNCONNECTED;
wire NLW_U0_m_axis_tlast_UNCONNECTED;
wire NLW_U0_m_axis_tvalid_UNCONNECTED;
wire NLW_U0_overflow_UNCONNECTED;
wire NLW_U0_rd_rst_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_s_axis_tready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire NLW_U0_underflow_UNCONNECTED;
wire NLW_U0_valid_UNCONNECTED;
wire NLW_U0_wr_ack_UNCONNECTED;
wire NLW_U0_wr_rst_busy_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
wire [9:0]NLW_U0_data_count_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "0" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "10" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "64" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "32" *)
(* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "1" *)
(* C_DIN_WIDTH_WDCH = "64" *)
(* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "64" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "kintex7" *)
(* C_FULL_FLAGS_RST_VAL = "1" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "1" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "1" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "2" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *)
(* C_PRELOAD_REGS = "0" *)
(* C_PRIM_FIFO_TYPE = "1kx36" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "956" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "957" *)
(* C_PROG_EMPTY_TYPE = "1" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "65" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "64" *)
(* C_PROG_FULL_TYPE = "1" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "10" *)
(* C_RD_DEPTH = "1024" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "10" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "9" *)
(* C_WR_DEPTH = "1024" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "10" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 U0
(.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
.almost_full(NLW_U0_almost_full_UNCONNECTED),
.axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
.axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
.axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
.axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
.axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
.axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
.axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
.axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
.axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
.axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
.axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
.axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
.axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
.axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
.axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
.axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
.axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
.axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
.axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
.axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
.axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
.axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
.axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
.axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
.axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
.axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
.axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
.axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
.axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
.axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
.axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),
.axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
.axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),
.axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
.axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
.axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.data_count(NLW_U0_data_count_UNCONNECTED[9:0]),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
.m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
.m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(1'b0),
.m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
.m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
.m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
.m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(1'b0),
.m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
.m_axi_bid(1'b0),
.m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
.m_axi_bresp({1'b0,1'b0}),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
.m_axi_rresp({1'b0,1'b0}),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
.m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
.m_axi_wready(1'b0),
.m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
.m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
.m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),
.m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
.m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
.m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),
.m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),
.m_axis_tready(1'b0),
.m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),
.m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),
.m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),
.overflow(NLW_U0_overflow_UNCONNECTED),
.prog_empty(prog_empty),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full(prog_full),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.rd_rst(1'b0),
.rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
.rst(rst),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot({1'b0,1'b0,1'b0}),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot({1'b0,1'b0,1'b0}),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.srst(1'b0),
.underflow(NLW_U0_underflow_UNCONNECTED),
.valid(NLW_U0_valid_UNCONNECTED),
.wr_ack(NLW_U0_wr_ack_UNCONNECTED),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en),
.wr_rst(1'b0),
.wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr
(dout,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
out,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [63:0]dout;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [63:0]din;
wire [0:0]E;
wire [63:0]din;
wire [63:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width \ramloop[0].ram.r
(.E(E),
.din(din[35:0]),
.dout(dout[35:0]),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0 \ramloop[1].ram.r
(.E(E),
.din(din[63:36]),
.dout(dout[63:36]),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width
(dout,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
out,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [35:0]dout;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [35:0]din;
wire [0:0]E;
wire [35:0]din;
wire [35:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.E(E),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_width__parameterized0
(dout,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
out,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [27:0]dout;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [27:0]din;
wire [0:0]E;
wire [27:0]din;
wire [27:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0 \prim_noinit.ram
(.E(E),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper
(dout,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
out,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [35:0]dout;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [35:0]din;
wire [0:0]E;
wire [35:0]din;
wire [35:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\gic0.gc0.count_d2_reg[9] ,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[9] ,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(wr_clk),
.CLKBWRCLK(rd_clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({din[34:27],din[25:18],din[16:9],din[7:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({din[35],din[26],din[17],din[8]}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({dout[34:27],dout[25:18],dout[16:9],dout[7:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({dout[35],dout[26],dout[17],dout[8]}),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(E),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({E,E,E,E}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_prim_wrapper__parameterized0
(dout,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
out,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [27:0]dout;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [27:0]din;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 ;
wire [0:0]E;
wire [27:0]din;
wire [27:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ;
wire \NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ;
wire [31:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED ;
wire [3:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED ;
wire [7:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED ;
wire [8:0]\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED ;
(* CLOCK_DOMAINS = "INDEPENDENT" *)
(* box_type = "PRIMITIVE" *)
RAMB36E1 #(
.DOA_REG(0),
.DOB_REG(0),
.EN_ECC_READ("FALSE"),
.EN_ECC_WRITE("FALSE"),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INITP_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_40(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_41(256'h0000000000000000000000000000000000000000000000000000000000000000),
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.INIT_43(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_44(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_45(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_46(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_47(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_48(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_49(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_50(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_51(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_52(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_53(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_54(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_55(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_56(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_57(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_58(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_59(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_60(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_61(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_62(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_63(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_64(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_65(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_66(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_67(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_68(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_69(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_70(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_71(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_72(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_73(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_74(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_75(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_76(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_77(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_78(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_79(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
.READ_WIDTH_A(36),
.READ_WIDTH_B(36),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(36'h000000000),
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(36),
.WRITE_WIDTH_B(36))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram
(.ADDRARDADDR({1'b1,\gic0.gc0.count_d2_reg[9] ,1'b1,1'b1,1'b1,1'b1,1'b1}),
.ADDRBWRADDR({1'b1,\gc0.count_d1_reg[9] ,1'b1,1'b1,1'b1,1'b1,1'b1}),
.CASCADEINA(1'b0),
.CASCADEINB(1'b0),
.CASCADEOUTA(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED ),
.CASCADEOUTB(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED ),
.CLKARDCLK(wr_clk),
.CLKBWRCLK(rd_clk),
.DBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED ),
.DIADI({1'b0,din[27:21],1'b0,din[20:14],1'b0,din[13:7],1'b0,din[6:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.DIPADIP({1'b0,1'b0,1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0,1'b0,1'b0}),
.DOADO(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED [31:0]),
.DOBDO({\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_53 ,dout[27:21],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_61 ,dout[20:14],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_69 ,dout[13:7],\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_77 ,dout[6:0]}),
.DOPADOP(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED [3:0]),
.DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_89 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_90 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_91 ,\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_n_92 }),
.ECCPARITY(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED [7:0]),
.ENARDEN(E),
.ENBWREN(tmp_ram_rd_en),
.INJECTDBITERR(1'b0),
.INJECTSBITERR(1'b0),
.RDADDRECC(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED [8:0]),
.REGCEAREGCE(1'b0),
.REGCEB(1'b0),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(out),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.SBITERR(\NLW_DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED ),
.WEA({E,E,E,E}),
.WEBWE({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top
(dout,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
out,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [63:0]dout;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [63:0]din;
wire [0:0]E;
wire [63:0]din;
wire [63:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_generic_cstr \valid.cstr
(.E(E),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4
(dout,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
out,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [63:0]dout;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [63:0]din;
wire [0:0]E;
wire [63:0]din;
wire [63:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth inst_blk_mem_gen
(.E(E),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4_synth
(dout,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
out,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [63:0]dout;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [63:0]din;
wire [0:0]E;
wire [63:0]din;
wire [63:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.E(E),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs
(v1_reg,
v1_reg_0,
D,
\rd_dc_i_reg[9] ,
v1_reg_1,
RD_PNTR_WR,
v1_reg_2,
Q,
\gc0.count_reg[9] ,
p_0_out,
\gic0.gc0.count_d1_reg[7] ,
\gic0.gc0.count_reg[9] ,
\gic0.gc0.count_d2_reg[9] ,
wr_clk,
AR,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [4:0]v1_reg;
output [4:0]v1_reg_0;
output [9:0]D;
output [9:0]\rd_dc_i_reg[9] ;
output [3:0]v1_reg_1;
output [9:0]RD_PNTR_WR;
output [4:0]v1_reg_2;
input [9:0]Q;
input [9:0]\gc0.count_reg[9] ;
input p_0_out;
input [7:0]\gic0.gc0.count_d1_reg[7] ;
input [9:0]\gic0.gc0.count_reg[9] ;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input wr_clk;
input [0:0]AR;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [0:0]AR;
wire [9:0]D;
wire [9:0]Q;
wire [9:0]RD_PNTR_WR;
wire [8:0]bin2gray;
wire [9:0]\gc0.count_reg[9] ;
wire \gdiff.diff_pntr_pad[10]_i_2_n_0 ;
wire \gdiff.diff_pntr_pad[10]_i_3_n_0 ;
wire \gdiff.diff_pntr_pad[4]_i_3_n_0 ;
wire \gdiff.diff_pntr_pad[4]_i_4_n_0 ;
wire \gdiff.diff_pntr_pad[4]_i_5_n_0 ;
wire \gdiff.diff_pntr_pad[4]_i_6_n_0 ;
wire \gdiff.diff_pntr_pad[8]_i_2_n_0 ;
wire \gdiff.diff_pntr_pad[8]_i_3_n_0 ;
wire \gdiff.diff_pntr_pad[8]_i_4_n_0 ;
wire \gdiff.diff_pntr_pad[8]_i_5_n_0 ;
wire \gdiff.diff_pntr_pad_reg[10]_i_1_n_3 ;
wire \gdiff.diff_pntr_pad_reg[4]_i_1_n_0 ;
wire \gdiff.diff_pntr_pad_reg[4]_i_1_n_1 ;
wire \gdiff.diff_pntr_pad_reg[4]_i_1_n_2 ;
wire \gdiff.diff_pntr_pad_reg[4]_i_1_n_3 ;
wire \gdiff.diff_pntr_pad_reg[8]_i_1_n_0 ;
wire \gdiff.diff_pntr_pad_reg[8]_i_1_n_1 ;
wire \gdiff.diff_pntr_pad_reg[8]_i_1_n_2 ;
wire \gdiff.diff_pntr_pad_reg[8]_i_1_n_3 ;
wire [7:0]\gic0.gc0.count_d1_reg[7] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [9:0]\gic0.gc0.count_reg[9] ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ;
wire \gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 ;
wire \gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ;
wire \gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0 ;
wire [7:0]gray2bin;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire p_0_out;
wire p_0_out_0;
wire [9:0]p_22_out;
wire [9:0]p_3_out;
wire [9:0]p_4_out;
wire [9:9]p_5_out;
wire [9:9]p_6_out;
wire rd_clk;
wire \rd_dc_i[3]_i_2_n_0 ;
wire \rd_dc_i[3]_i_3_n_0 ;
wire \rd_dc_i[3]_i_4_n_0 ;
wire \rd_dc_i[3]_i_5_n_0 ;
wire \rd_dc_i[7]_i_2_n_0 ;
wire \rd_dc_i[7]_i_3_n_0 ;
wire \rd_dc_i[7]_i_4_n_0 ;
wire \rd_dc_i[7]_i_5_n_0 ;
wire \rd_dc_i[9]_i_2_n_0 ;
wire \rd_dc_i[9]_i_3_n_0 ;
wire \rd_dc_i_reg[3]_i_1_n_0 ;
wire \rd_dc_i_reg[3]_i_1_n_1 ;
wire \rd_dc_i_reg[3]_i_1_n_2 ;
wire \rd_dc_i_reg[3]_i_1_n_3 ;
wire \rd_dc_i_reg[7]_i_1_n_0 ;
wire \rd_dc_i_reg[7]_i_1_n_1 ;
wire \rd_dc_i_reg[7]_i_1_n_2 ;
wire \rd_dc_i_reg[7]_i_1_n_3 ;
wire [9:0]\rd_dc_i_reg[9] ;
wire \rd_dc_i_reg[9]_i_1_n_3 ;
wire [9:0]rd_pntr_gc;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
wire [3:0]v1_reg_1;
wire [4:0]v1_reg_2;
wire wr_clk;
wire [9:0]wr_pntr_gc;
wire [3:1]\NLW_gdiff.diff_pntr_pad_reg[10]_i_1_CO_UNCONNECTED ;
wire [3:2]\NLW_gdiff.diff_pntr_pad_reg[10]_i_1_O_UNCONNECTED ;
wire [3:1]\NLW_rd_dc_i_reg[9]_i_1_CO_UNCONNECTED ;
wire [3:2]\NLW_rd_dc_i_reg[9]_i_1_O_UNCONNECTED ;
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[10]_i_2
(.I0(p_22_out[9]),
.I1(Q[9]),
.O(\gdiff.diff_pntr_pad[10]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[10]_i_3
(.I0(p_22_out[8]),
.I1(Q[8]),
.O(\gdiff.diff_pntr_pad[10]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[4]_i_3
(.I0(p_22_out[3]),
.I1(Q[3]),
.O(\gdiff.diff_pntr_pad[4]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[4]_i_4
(.I0(p_22_out[2]),
.I1(Q[2]),
.O(\gdiff.diff_pntr_pad[4]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[4]_i_5
(.I0(p_22_out[1]),
.I1(Q[1]),
.O(\gdiff.diff_pntr_pad[4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[4]_i_6
(.I0(p_22_out[0]),
.I1(Q[0]),
.O(\gdiff.diff_pntr_pad[4]_i_6_n_0 ));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[8]_i_2
(.I0(p_22_out[7]),
.I1(Q[7]),
.O(\gdiff.diff_pntr_pad[8]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[8]_i_3
(.I0(p_22_out[6]),
.I1(Q[6]),
.O(\gdiff.diff_pntr_pad[8]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[8]_i_4
(.I0(p_22_out[5]),
.I1(Q[5]),
.O(\gdiff.diff_pntr_pad[8]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\gdiff.diff_pntr_pad[8]_i_5
(.I0(p_22_out[4]),
.I1(Q[4]),
.O(\gdiff.diff_pntr_pad[8]_i_5_n_0 ));
CARRY4 \gdiff.diff_pntr_pad_reg[10]_i_1
(.CI(\gdiff.diff_pntr_pad_reg[8]_i_1_n_0 ),
.CO({\NLW_gdiff.diff_pntr_pad_reg[10]_i_1_CO_UNCONNECTED [3:1],\gdiff.diff_pntr_pad_reg[10]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,p_22_out[8]}),
.O({\NLW_gdiff.diff_pntr_pad_reg[10]_i_1_O_UNCONNECTED [3:2],D[9:8]}),
.S({1'b0,1'b0,\gdiff.diff_pntr_pad[10]_i_2_n_0 ,\gdiff.diff_pntr_pad[10]_i_3_n_0 }));
CARRY4 \gdiff.diff_pntr_pad_reg[4]_i_1
(.CI(1'b0),
.CO({\gdiff.diff_pntr_pad_reg[4]_i_1_n_0 ,\gdiff.diff_pntr_pad_reg[4]_i_1_n_1 ,\gdiff.diff_pntr_pad_reg[4]_i_1_n_2 ,\gdiff.diff_pntr_pad_reg[4]_i_1_n_3 }),
.CYINIT(p_0_out),
.DI(p_22_out[3:0]),
.O(D[3:0]),
.S({\gdiff.diff_pntr_pad[4]_i_3_n_0 ,\gdiff.diff_pntr_pad[4]_i_4_n_0 ,\gdiff.diff_pntr_pad[4]_i_5_n_0 ,\gdiff.diff_pntr_pad[4]_i_6_n_0 }));
CARRY4 \gdiff.diff_pntr_pad_reg[8]_i_1
(.CI(\gdiff.diff_pntr_pad_reg[4]_i_1_n_0 ),
.CO({\gdiff.diff_pntr_pad_reg[8]_i_1_n_0 ,\gdiff.diff_pntr_pad_reg[8]_i_1_n_1 ,\gdiff.diff_pntr_pad_reg[8]_i_1_n_2 ,\gdiff.diff_pntr_pad_reg[8]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(p_22_out[7:4]),
.O(D[7:4]),
.S({\gdiff.diff_pntr_pad[8]_i_2_n_0 ,\gdiff.diff_pntr_pad[8]_i_3_n_0 ,\gdiff.diff_pntr_pad[8]_i_4_n_0 ,\gdiff.diff_pntr_pad[8]_i_5_n_0 }));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1
(.I0(p_22_out[0]),
.I1(Q[0]),
.I2(p_22_out[1]),
.I3(Q[1]),
.O(v1_reg[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__0
(.I0(p_22_out[0]),
.I1(\gc0.count_reg[9] [0]),
.I2(p_22_out[1]),
.I3(\gc0.count_reg[9] [1]),
.O(v1_reg_0[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__1
(.I0(RD_PNTR_WR[0]),
.I1(\gic0.gc0.count_d1_reg[7] [0]),
.I2(RD_PNTR_WR[1]),
.I3(\gic0.gc0.count_d1_reg[7] [1]),
.O(v1_reg_1[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[0].gm1.m1_i_1__2
(.I0(RD_PNTR_WR[0]),
.I1(\gic0.gc0.count_reg[9] [0]),
.I2(RD_PNTR_WR[1]),
.I3(\gic0.gc0.count_reg[9] [1]),
.O(v1_reg_2[0]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1
(.I0(p_22_out[2]),
.I1(Q[2]),
.I2(p_22_out[3]),
.I3(Q[3]),
.O(v1_reg[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__0
(.I0(p_22_out[2]),
.I1(\gc0.count_reg[9] [2]),
.I2(p_22_out[3]),
.I3(\gc0.count_reg[9] [3]),
.O(v1_reg_0[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__1
(.I0(RD_PNTR_WR[2]),
.I1(\gic0.gc0.count_d1_reg[7] [2]),
.I2(RD_PNTR_WR[3]),
.I3(\gic0.gc0.count_d1_reg[7] [3]),
.O(v1_reg_1[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[1].gms.ms_i_1__2
(.I0(RD_PNTR_WR[2]),
.I1(\gic0.gc0.count_reg[9] [2]),
.I2(RD_PNTR_WR[3]),
.I3(\gic0.gc0.count_reg[9] [3]),
.O(v1_reg_2[1]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1
(.I0(p_22_out[4]),
.I1(Q[4]),
.I2(p_22_out[5]),
.I3(Q[5]),
.O(v1_reg[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__0
(.I0(p_22_out[4]),
.I1(\gc0.count_reg[9] [4]),
.I2(p_22_out[5]),
.I3(\gc0.count_reg[9] [5]),
.O(v1_reg_0[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__1
(.I0(RD_PNTR_WR[4]),
.I1(\gic0.gc0.count_d1_reg[7] [4]),
.I2(RD_PNTR_WR[5]),
.I3(\gic0.gc0.count_d1_reg[7] [5]),
.O(v1_reg_1[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[2].gms.ms_i_1__2
(.I0(RD_PNTR_WR[4]),
.I1(\gic0.gc0.count_reg[9] [4]),
.I2(RD_PNTR_WR[5]),
.I3(\gic0.gc0.count_reg[9] [5]),
.O(v1_reg_2[2]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1
(.I0(p_22_out[6]),
.I1(Q[6]),
.I2(p_22_out[7]),
.I3(Q[7]),
.O(v1_reg[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__0
(.I0(p_22_out[6]),
.I1(\gc0.count_reg[9] [6]),
.I2(p_22_out[7]),
.I3(\gc0.count_reg[9] [7]),
.O(v1_reg_0[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__1
(.I0(RD_PNTR_WR[6]),
.I1(\gic0.gc0.count_d1_reg[7] [6]),
.I2(RD_PNTR_WR[7]),
.I3(\gic0.gc0.count_d1_reg[7] [7]),
.O(v1_reg_1[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[3].gms.ms_i_1__2
(.I0(RD_PNTR_WR[6]),
.I1(\gic0.gc0.count_reg[9] [6]),
.I2(RD_PNTR_WR[7]),
.I3(\gic0.gc0.count_reg[9] [7]),
.O(v1_reg_2[3]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1
(.I0(p_22_out[8]),
.I1(Q[8]),
.I2(p_22_out[9]),
.I3(Q[9]),
.O(v1_reg[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__0
(.I0(p_22_out[8]),
.I1(\gc0.count_reg[9] [8]),
.I2(p_22_out[9]),
.I3(\gc0.count_reg[9] [9]),
.O(v1_reg_0[4]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__2
(.I0(RD_PNTR_WR[8]),
.I1(\gic0.gc0.count_reg[9] [8]),
.I2(RD_PNTR_WR[9]),
.I3(\gic0.gc0.count_reg[9] [9]),
.O(v1_reg_2[4]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0 \gnxpm_cdc.gsync_stage[1].rd_stg_inst
(.D(p_3_out),
.Q(wr_pntr_gc),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.rd_clk(rd_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1 \gnxpm_cdc.gsync_stage[1].wr_stg_inst
(.AR(AR),
.D(p_4_out),
.Q(rd_pntr_gc),
.wr_clk(wr_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2 \gnxpm_cdc.gsync_stage[2].rd_stg_inst
(.D(p_3_out),
.\gnxpm_cdc.wr_pntr_bin_reg[8] ({p_0_out_0,gray2bin}),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.out(p_5_out),
.rd_clk(rd_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3 \gnxpm_cdc.gsync_stage[2].wr_stg_inst
(.AR(AR),
.D(p_4_out),
.\gnxpm_cdc.rd_pntr_bin_reg[8] ({\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ,\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 }),
.out(p_6_out),
.wr_clk(wr_clk));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_9 ),
.Q(RD_PNTR_WR[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_8 ),
.Q(RD_PNTR_WR[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_7 ),
.Q(RD_PNTR_WR[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_6 ),
.Q(RD_PNTR_WR[3]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_5 ),
.Q(RD_PNTR_WR[4]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_4 ),
.Q(RD_PNTR_WR[5]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_3 ),
.Q(RD_PNTR_WR[6]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_2 ),
.Q(RD_PNTR_WR[7]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[2].wr_stg_inst_n_1 ),
.Q(RD_PNTR_WR[8]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(p_6_out),
.Q(RD_PNTR_WR[9]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[0]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(\gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[1]_i_1
(.I0(Q[1]),
.I1(Q[2]),
.O(\gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[2]_i_1
(.I0(Q[2]),
.I1(Q[3]),
.O(\gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[3]_i_1
(.I0(Q[3]),
.I1(Q[4]),
.O(\gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[4]_i_1
(.I0(Q[4]),
.I1(Q[5]),
.O(\gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[5]_i_1
(.I0(Q[5]),
.I1(Q[6]),
.O(\gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[6]_i_1
(.I0(Q[6]),
.I1(Q[7]),
.O(\gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[7]_i_1
(.I0(Q[7]),
.I1(Q[8]),
.O(\gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[8]_i_1
(.I0(Q[8]),
.I1(Q[9]),
.O(\gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0 ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[0]_i_1_n_0 ),
.Q(rd_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[1]_i_1_n_0 ),
.Q(rd_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[2]_i_1_n_0 ),
.Q(rd_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[3]_i_1_n_0 ),
.Q(rd_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[4]_i_1_n_0 ),
.Q(rd_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[5]_i_1_n_0 ),
.Q(rd_pntr_gc[5]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[6]_i_1_n_0 ),
.Q(rd_pntr_gc[6]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[7]_i_1_n_0 ),
.Q(rd_pntr_gc[7]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.rd_pntr_gc[8]_i_1_n_0 ),
.Q(rd_pntr_gc[8]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[9]),
.Q(rd_pntr_gc[9]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[0]),
.Q(p_22_out[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[1]),
.Q(p_22_out[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[2]),
.Q(p_22_out[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[3]),
.Q(p_22_out[3]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[4]),
.Q(p_22_out[4]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[5]),
.Q(p_22_out[5]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[6]),
.Q(p_22_out[6]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin[7]),
.Q(p_22_out[7]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_out_0),
.Q(p_22_out[8]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_5_out),
.Q(p_22_out[9]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[0]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [0]),
.I1(\gic0.gc0.count_d2_reg[9] [1]),
.O(bin2gray[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[1]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [1]),
.I1(\gic0.gc0.count_d2_reg[9] [2]),
.O(bin2gray[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[2]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [2]),
.I1(\gic0.gc0.count_d2_reg[9] [3]),
.O(bin2gray[2]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[3]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [3]),
.I1(\gic0.gc0.count_d2_reg[9] [4]),
.O(bin2gray[3]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[4]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [4]),
.I1(\gic0.gc0.count_d2_reg[9] [5]),
.O(bin2gray[4]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[5]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [5]),
.I1(\gic0.gc0.count_d2_reg[9] [6]),
.O(bin2gray[5]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[6]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [6]),
.I1(\gic0.gc0.count_d2_reg[9] [7]),
.O(bin2gray[6]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[7]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [7]),
.I1(\gic0.gc0.count_d2_reg[9] [8]),
.O(bin2gray[7]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[8]_i_1
(.I0(\gic0.gc0.count_d2_reg[9] [8]),
.I1(\gic0.gc0.count_d2_reg[9] [9]),
.O(bin2gray[8]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[0]),
.Q(wr_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[1]),
.Q(wr_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[2]),
.Q(wr_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[3]),
.Q(wr_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[4]),
.Q(wr_pntr_gc[4]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[5]),
.Q(wr_pntr_gc[5]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[6]),
.Q(wr_pntr_gc[6]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[7]),
.Q(wr_pntr_gc[7]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[8]),
.Q(wr_pntr_gc[8]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[9] [9]),
.Q(wr_pntr_gc[9]));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[3]_i_2
(.I0(p_22_out[3]),
.I1(Q[3]),
.O(\rd_dc_i[3]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[3]_i_3
(.I0(p_22_out[2]),
.I1(Q[2]),
.O(\rd_dc_i[3]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[3]_i_4
(.I0(p_22_out[1]),
.I1(Q[1]),
.O(\rd_dc_i[3]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[3]_i_5
(.I0(p_22_out[0]),
.I1(Q[0]),
.O(\rd_dc_i[3]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[7]_i_2
(.I0(p_22_out[7]),
.I1(Q[7]),
.O(\rd_dc_i[7]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[7]_i_3
(.I0(p_22_out[6]),
.I1(Q[6]),
.O(\rd_dc_i[7]_i_3_n_0 ));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[7]_i_4
(.I0(p_22_out[5]),
.I1(Q[5]),
.O(\rd_dc_i[7]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[7]_i_5
(.I0(p_22_out[4]),
.I1(Q[4]),
.O(\rd_dc_i[7]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[9]_i_2
(.I0(p_22_out[9]),
.I1(Q[9]),
.O(\rd_dc_i[9]_i_2_n_0 ));
LUT2 #(
.INIT(4'h9))
\rd_dc_i[9]_i_3
(.I0(p_22_out[8]),
.I1(Q[8]),
.O(\rd_dc_i[9]_i_3_n_0 ));
CARRY4 \rd_dc_i_reg[3]_i_1
(.CI(1'b0),
.CO({\rd_dc_i_reg[3]_i_1_n_0 ,\rd_dc_i_reg[3]_i_1_n_1 ,\rd_dc_i_reg[3]_i_1_n_2 ,\rd_dc_i_reg[3]_i_1_n_3 }),
.CYINIT(1'b1),
.DI(p_22_out[3:0]),
.O(\rd_dc_i_reg[9] [3:0]),
.S({\rd_dc_i[3]_i_2_n_0 ,\rd_dc_i[3]_i_3_n_0 ,\rd_dc_i[3]_i_4_n_0 ,\rd_dc_i[3]_i_5_n_0 }));
CARRY4 \rd_dc_i_reg[7]_i_1
(.CI(\rd_dc_i_reg[3]_i_1_n_0 ),
.CO({\rd_dc_i_reg[7]_i_1_n_0 ,\rd_dc_i_reg[7]_i_1_n_1 ,\rd_dc_i_reg[7]_i_1_n_2 ,\rd_dc_i_reg[7]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(p_22_out[7:4]),
.O(\rd_dc_i_reg[9] [7:4]),
.S({\rd_dc_i[7]_i_2_n_0 ,\rd_dc_i[7]_i_3_n_0 ,\rd_dc_i[7]_i_4_n_0 ,\rd_dc_i[7]_i_5_n_0 }));
CARRY4 \rd_dc_i_reg[9]_i_1
(.CI(\rd_dc_i_reg[7]_i_1_n_0 ),
.CO({\NLW_rd_dc_i_reg[9]_i_1_CO_UNCONNECTED [3:1],\rd_dc_i_reg[9]_i_1_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,p_22_out[8]}),
.O({\NLW_rd_dc_i_reg[9]_i_1_O_UNCONNECTED [3:2],\rd_dc_i_reg[9] [9:8]}),
.S({1'b0,1'b0,\rd_dc_i[9]_i_2_n_0 ,\rd_dc_i[9]_i_3_n_0 }));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare
(comp1,
\gnxpm_cdc.rd_pntr_bin_reg[6] ,
v1_reg_0);
output comp1;
input [3:0]\gnxpm_cdc.rd_pntr_bin_reg[6] ;
input [0:0]v1_reg_0;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire comp1;
wire [3:0]\gnxpm_cdc.rd_pntr_bin_reg[6] ;
wire [0:0]v1_reg_0;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(\gnxpm_cdc.rd_pntr_bin_reg[6] ));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg_0}));
endmodule
(* ORIG_REF_NAME = "compare" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3
(ram_full_fb_i_reg,
v1_reg,
out,
wr_en,
wr_rst_busy,
comp1);
output ram_full_fb_i_reg;
input [4:0]v1_reg;
input out;
input wr_en;
input wr_rst_busy;
input comp1;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire comp1;
wire comp2;
wire out;
wire ram_full_fb_i_reg;
wire [4:0]v1_reg;
wire wr_en;
wire wr_rst_busy;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp2}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg[4]}));
LUT5 #(
.INIT(32'h00FF0020))
ram_full_i_i_1
(.I0(comp2),
.I1(out),
.I2(wr_en),
.I3(wr_rst_busy),
.I4(comp1),
.O(ram_full_fb_i_reg));
endmodule
(* ORIG_REF_NAME = "compare" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4
(ram_empty_fb_i_reg,
v1_reg,
rd_en,
out,
comp1);
output ram_empty_fb_i_reg;
input [4:0]v1_reg;
input rd_en;
input out;
input comp1;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire comp0;
wire comp1;
wire out;
wire ram_empty_fb_i_reg;
wire rd_en;
wire [4:0]v1_reg;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp0}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg[4]}));
LUT4 #(
.INIT(16'hAEAA))
ram_empty_i_i_1
(.I0(comp0),
.I1(rd_en),
.I2(out),
.I3(comp1),
.O(ram_empty_fb_i_reg));
endmodule
(* ORIG_REF_NAME = "compare" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5
(comp1,
v1_reg_0);
output comp1;
input [4:0]v1_reg_0;
wire carrynet_0;
wire carrynet_1;
wire carrynet_2;
wire carrynet_3;
wire comp1;
wire [4:0]v1_reg_0;
wire [3:0]\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED ;
wire [3:1]\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED ;
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[0].gm1.m1_CARRY4
(.CI(1'b0),
.CO({carrynet_3,carrynet_2,carrynet_1,carrynet_0}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_gmux.gm[0].gm1.m1_CARRY4_O_UNCONNECTED [3:0]),
.S(v1_reg_0[3:0]));
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
(* box_type = "PRIMITIVE" *)
CARRY4 \gmux.gm[4].gms.ms_CARRY4
(.CI(carrynet_3),
.CO({\NLW_gmux.gm[4].gms.ms_CARRY4_CO_UNCONNECTED [3:1],comp1}),
.CYINIT(1'b0),
.DI({\NLW_gmux.gm[4].gms.ms_CARRY4_DI_UNCONNECTED [3:1],1'b0}),
.O(\NLW_gmux.gm[4].gms.ms_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_gmux.gm[4].gms.ms_CARRY4_S_UNCONNECTED [3:1],v1_reg_0[4]}));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo
(wr_rst_busy,
dout,
empty,
full,
rd_data_count,
wr_data_count,
prog_empty,
prog_full,
rd_en,
wr_clk,
rd_clk,
din,
rst,
wr_en);
output wr_rst_busy;
output [63:0]dout;
output empty;
output full;
output [9:0]rd_data_count;
output [8:0]wr_data_count;
output prog_empty;
output prog_full;
input rd_en;
input wr_clk;
input rd_clk;
input [63:0]din;
input rst;
input wr_en;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire [4:0]\gras.rsts/c0/v1_reg ;
wire [4:0]\gras.rsts/c1/v1_reg ;
wire [3:0]\gwas.wsts/c1/v1_reg ;
wire [4:0]\gwas.wsts/c2/v1_reg ;
wire [9:0]minusOp;
wire p_0_out;
wire [9:0]p_0_out_0;
wire [9:0]p_12_out;
wire [7:0]p_13_out;
wire p_18_out;
wire [9:0]p_23_out;
wire p_2_out;
wire [10:1]plusOp;
wire prog_empty;
wire prog_full;
wire rd_clk;
wire [9:0]rd_data_count;
wire rd_en;
wire [9:0]rd_pntr_plus1;
wire [2:0]rd_rst_i;
wire rst;
wire rst_full_ff_i;
wire tmp_ram_rd_en;
wire wr_clk;
wire [8:0]wr_data_count;
wire wr_en;
wire [9:0]wr_pntr_plus2;
wire wr_rst_busy;
wire [1:0]wr_rst_i;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_x_pntrs \gntv_or_sync_fifo.gcx.clkx
(.AR(wr_rst_i[0]),
.D(plusOp),
.Q(p_0_out_0),
.RD_PNTR_WR(p_23_out),
.\gc0.count_reg[9] (rd_pntr_plus1),
.\gic0.gc0.count_d1_reg[7] (p_13_out),
.\gic0.gc0.count_d2_reg[9] (p_12_out),
.\gic0.gc0.count_reg[9] (wr_pntr_plus2),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]),
.p_0_out(p_0_out),
.rd_clk(rd_clk),
.\rd_dc_i_reg[9] (minusOp),
.v1_reg(\gras.rsts/c0/v1_reg ),
.v1_reg_0(\gras.rsts/c1/v1_reg ),
.v1_reg_1(\gwas.wsts/c1/v1_reg ),
.v1_reg_2(\gwas.wsts/c2/v1_reg ),
.wr_clk(wr_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic \gntv_or_sync_fifo.gl0.rd
(.AR(rd_rst_i[2]),
.D(plusOp),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (p_0_out_0),
.Q(rd_pntr_plus1),
.empty(empty),
.\gnxpm_cdc.wr_pntr_bin_reg[8] (minusOp),
.out(p_2_out),
.p_0_out(p_0_out),
.prog_empty(prog_empty),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.v1_reg(\gras.rsts/c0/v1_reg ),
.v1_reg_0(\gras.rsts/c1/v1_reg ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic \gntv_or_sync_fifo.gl0.wr
(.AR(wr_rst_i[1]),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (p_12_out),
.E(p_18_out),
.Q(p_13_out),
.RD_PNTR_WR(p_23_out),
.full(full),
.\gic0.gc0.count_d1_reg[9] (wr_pntr_plus2),
.\gnxpm_cdc.rd_pntr_bin_reg[6] (\gwas.wsts/c1/v1_reg ),
.out(rst_full_ff_i),
.prog_full(prog_full),
.v1_reg(\gwas.wsts/c2/v1_reg ),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory \gntv_or_sync_fifo.mem
(.E(p_18_out),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (p_0_out_0),
.\gic0.gc0.count_d2_reg[9] (p_12_out),
.out(rd_rst_i[0]),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo rstblk
(.\gc0.count_reg[1] (rd_rst_i),
.\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i),
.out(wr_rst_i),
.ram_empty_fb_i_reg(p_2_out),
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk),
.wr_rst_busy(wr_rst_busy));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top
(wr_rst_busy,
dout,
empty,
full,
rd_data_count,
wr_data_count,
prog_empty,
prog_full,
rd_en,
wr_clk,
rd_clk,
din,
rst,
wr_en);
output wr_rst_busy;
output [63:0]dout;
output empty;
output full;
output [9:0]rd_data_count;
output [8:0]wr_data_count;
output prog_empty;
output prog_full;
input rd_en;
input wr_clk;
input rd_clk;
input [63:0]din;
input rst;
input wr_en;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire prog_empty;
wire prog_full;
wire rd_clk;
wire [9:0]rd_data_count;
wire rd_en;
wire rst;
wire wr_clk;
wire [8:0]wr_data_count;
wire wr_en;
wire wr_rst_busy;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo \grf.rf
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.prog_empty(prog_empty),
.prog_full(prog_full),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
(* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "10" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "64" *)
(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "1" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "64" *) (* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "kintex7" *) (* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "1" *)
(* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *) (* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "1" *) (* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "2" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "1" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "1kx36" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "956" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "957" *) (* C_PROG_EMPTY_TYPE = "1" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "65" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "64" *) (* C_PROG_FULL_TYPE = "1" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "10" *)
(* C_RD_DEPTH = "1024" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "10" *)
(* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *) (* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *) (* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "9" *)
(* C_WR_DEPTH = "1024" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "10" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [63:0]din;
input wr_en;
input rd_en;
input [9:0]prog_empty_thresh;
input [9:0]prog_empty_thresh_assert;
input [9:0]prog_empty_thresh_negate;
input [9:0]prog_full_thresh;
input [9:0]prog_full_thresh_assert;
input [9:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [63:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [9:0]data_count;
output [9:0]rd_data_count;
output [8:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [63:0]s_axi_wdata;
input [7:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [63:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [9:0]axi_w_prog_full_thresh;
input [9:0]axi_w_prog_empty_thresh;
output [10:0]axi_w_data_count;
output [10:0]axi_w_wr_data_count;
output [10:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [9:0]axi_r_prog_full_thresh;
input [9:0]axi_r_prog_empty_thresh;
output [10:0]axi_r_data_count;
output [10:0]axi_r_wr_data_count;
output [10:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire \<const1> ;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire prog_empty;
wire prog_full;
wire rd_clk;
wire [9:0]rd_data_count;
wire rd_en;
wire rst;
wire wr_clk;
wire [8:0]wr_data_count;
wire wr_en;
wire wr_rst_busy;
assign almost_empty = \<const0> ;
assign almost_full = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const1> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const1> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const1> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[10] = \<const0> ;
assign axi_r_data_count[9] = \<const0> ;
assign axi_r_data_count[8] = \<const0> ;
assign axi_r_data_count[7] = \<const0> ;
assign axi_r_data_count[6] = \<const0> ;
assign axi_r_data_count[5] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const1> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[10] = \<const0> ;
assign axi_r_rd_data_count[9] = \<const0> ;
assign axi_r_rd_data_count[8] = \<const0> ;
assign axi_r_rd_data_count[7] = \<const0> ;
assign axi_r_rd_data_count[6] = \<const0> ;
assign axi_r_rd_data_count[5] = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[10] = \<const0> ;
assign axi_r_wr_data_count[9] = \<const0> ;
assign axi_r_wr_data_count[8] = \<const0> ;
assign axi_r_wr_data_count[7] = \<const0> ;
assign axi_r_wr_data_count[6] = \<const0> ;
assign axi_r_wr_data_count[5] = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[10] = \<const0> ;
assign axi_w_data_count[9] = \<const0> ;
assign axi_w_data_count[8] = \<const0> ;
assign axi_w_data_count[7] = \<const0> ;
assign axi_w_data_count[6] = \<const0> ;
assign axi_w_data_count[5] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const1> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[10] = \<const0> ;
assign axi_w_rd_data_count[9] = \<const0> ;
assign axi_w_rd_data_count[8] = \<const0> ;
assign axi_w_rd_data_count[7] = \<const0> ;
assign axi_w_rd_data_count[6] = \<const0> ;
assign axi_w_rd_data_count[5] = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[10] = \<const0> ;
assign axi_w_wr_data_count[9] = \<const0> ;
assign axi_w_wr_data_count[8] = \<const0> ;
assign axi_w_wr_data_count[7] = \<const0> ;
assign axi_w_wr_data_count[6] = \<const0> ;
assign axi_w_wr_data_count[5] = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const1> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[9] = \<const0> ;
assign data_count[8] = \<const0> ;
assign data_count[7] = \<const0> ;
assign data_count[6] = \<const0> ;
assign data_count[5] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign m_axi_araddr[31] = \<const0> ;
assign m_axi_araddr[30] = \<const0> ;
assign m_axi_araddr[29] = \<const0> ;
assign m_axi_araddr[28] = \<const0> ;
assign m_axi_araddr[27] = \<const0> ;
assign m_axi_araddr[26] = \<const0> ;
assign m_axi_araddr[25] = \<const0> ;
assign m_axi_araddr[24] = \<const0> ;
assign m_axi_araddr[23] = \<const0> ;
assign m_axi_araddr[22] = \<const0> ;
assign m_axi_araddr[21] = \<const0> ;
assign m_axi_araddr[20] = \<const0> ;
assign m_axi_araddr[19] = \<const0> ;
assign m_axi_araddr[18] = \<const0> ;
assign m_axi_araddr[17] = \<const0> ;
assign m_axi_araddr[16] = \<const0> ;
assign m_axi_araddr[15] = \<const0> ;
assign m_axi_araddr[14] = \<const0> ;
assign m_axi_araddr[13] = \<const0> ;
assign m_axi_araddr[12] = \<const0> ;
assign m_axi_araddr[11] = \<const0> ;
assign m_axi_araddr[10] = \<const0> ;
assign m_axi_araddr[9] = \<const0> ;
assign m_axi_araddr[8] = \<const0> ;
assign m_axi_araddr[7] = \<const0> ;
assign m_axi_araddr[6] = \<const0> ;
assign m_axi_araddr[5] = \<const0> ;
assign m_axi_araddr[4] = \<const0> ;
assign m_axi_araddr[3] = \<const0> ;
assign m_axi_araddr[2] = \<const0> ;
assign m_axi_araddr[1] = \<const0> ;
assign m_axi_araddr[0] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[2] = \<const0> ;
assign m_axi_arprot[1] = \<const0> ;
assign m_axi_arprot[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_arvalid = \<const0> ;
assign m_axi_awaddr[31] = \<const0> ;
assign m_axi_awaddr[30] = \<const0> ;
assign m_axi_awaddr[29] = \<const0> ;
assign m_axi_awaddr[28] = \<const0> ;
assign m_axi_awaddr[27] = \<const0> ;
assign m_axi_awaddr[26] = \<const0> ;
assign m_axi_awaddr[25] = \<const0> ;
assign m_axi_awaddr[24] = \<const0> ;
assign m_axi_awaddr[23] = \<const0> ;
assign m_axi_awaddr[22] = \<const0> ;
assign m_axi_awaddr[21] = \<const0> ;
assign m_axi_awaddr[20] = \<const0> ;
assign m_axi_awaddr[19] = \<const0> ;
assign m_axi_awaddr[18] = \<const0> ;
assign m_axi_awaddr[17] = \<const0> ;
assign m_axi_awaddr[16] = \<const0> ;
assign m_axi_awaddr[15] = \<const0> ;
assign m_axi_awaddr[14] = \<const0> ;
assign m_axi_awaddr[13] = \<const0> ;
assign m_axi_awaddr[12] = \<const0> ;
assign m_axi_awaddr[11] = \<const0> ;
assign m_axi_awaddr[10] = \<const0> ;
assign m_axi_awaddr[9] = \<const0> ;
assign m_axi_awaddr[8] = \<const0> ;
assign m_axi_awaddr[7] = \<const0> ;
assign m_axi_awaddr[6] = \<const0> ;
assign m_axi_awaddr[5] = \<const0> ;
assign m_axi_awaddr[4] = \<const0> ;
assign m_axi_awaddr[3] = \<const0> ;
assign m_axi_awaddr[2] = \<const0> ;
assign m_axi_awaddr[1] = \<const0> ;
assign m_axi_awaddr[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[2] = \<const0> ;
assign m_axi_awprot[1] = \<const0> ;
assign m_axi_awprot[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_awvalid = \<const0> ;
assign m_axi_bready = \<const0> ;
assign m_axi_rready = \<const0> ;
assign m_axi_wdata[63] = \<const0> ;
assign m_axi_wdata[62] = \<const0> ;
assign m_axi_wdata[61] = \<const0> ;
assign m_axi_wdata[60] = \<const0> ;
assign m_axi_wdata[59] = \<const0> ;
assign m_axi_wdata[58] = \<const0> ;
assign m_axi_wdata[57] = \<const0> ;
assign m_axi_wdata[56] = \<const0> ;
assign m_axi_wdata[55] = \<const0> ;
assign m_axi_wdata[54] = \<const0> ;
assign m_axi_wdata[53] = \<const0> ;
assign m_axi_wdata[52] = \<const0> ;
assign m_axi_wdata[51] = \<const0> ;
assign m_axi_wdata[50] = \<const0> ;
assign m_axi_wdata[49] = \<const0> ;
assign m_axi_wdata[48] = \<const0> ;
assign m_axi_wdata[47] = \<const0> ;
assign m_axi_wdata[46] = \<const0> ;
assign m_axi_wdata[45] = \<const0> ;
assign m_axi_wdata[44] = \<const0> ;
assign m_axi_wdata[43] = \<const0> ;
assign m_axi_wdata[42] = \<const0> ;
assign m_axi_wdata[41] = \<const0> ;
assign m_axi_wdata[40] = \<const0> ;
assign m_axi_wdata[39] = \<const0> ;
assign m_axi_wdata[38] = \<const0> ;
assign m_axi_wdata[37] = \<const0> ;
assign m_axi_wdata[36] = \<const0> ;
assign m_axi_wdata[35] = \<const0> ;
assign m_axi_wdata[34] = \<const0> ;
assign m_axi_wdata[33] = \<const0> ;
assign m_axi_wdata[32] = \<const0> ;
assign m_axi_wdata[31] = \<const0> ;
assign m_axi_wdata[30] = \<const0> ;
assign m_axi_wdata[29] = \<const0> ;
assign m_axi_wdata[28] = \<const0> ;
assign m_axi_wdata[27] = \<const0> ;
assign m_axi_wdata[26] = \<const0> ;
assign m_axi_wdata[25] = \<const0> ;
assign m_axi_wdata[24] = \<const0> ;
assign m_axi_wdata[23] = \<const0> ;
assign m_axi_wdata[22] = \<const0> ;
assign m_axi_wdata[21] = \<const0> ;
assign m_axi_wdata[20] = \<const0> ;
assign m_axi_wdata[19] = \<const0> ;
assign m_axi_wdata[18] = \<const0> ;
assign m_axi_wdata[17] = \<const0> ;
assign m_axi_wdata[16] = \<const0> ;
assign m_axi_wdata[15] = \<const0> ;
assign m_axi_wdata[14] = \<const0> ;
assign m_axi_wdata[13] = \<const0> ;
assign m_axi_wdata[12] = \<const0> ;
assign m_axi_wdata[11] = \<const0> ;
assign m_axi_wdata[10] = \<const0> ;
assign m_axi_wdata[9] = \<const0> ;
assign m_axi_wdata[8] = \<const0> ;
assign m_axi_wdata[7] = \<const0> ;
assign m_axi_wdata[6] = \<const0> ;
assign m_axi_wdata[5] = \<const0> ;
assign m_axi_wdata[4] = \<const0> ;
assign m_axi_wdata[3] = \<const0> ;
assign m_axi_wdata[2] = \<const0> ;
assign m_axi_wdata[1] = \<const0> ;
assign m_axi_wdata[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const0> ;
assign m_axi_wstrb[7] = \<const0> ;
assign m_axi_wstrb[6] = \<const0> ;
assign m_axi_wstrb[5] = \<const0> ;
assign m_axi_wstrb[4] = \<const0> ;
assign m_axi_wstrb[3] = \<const0> ;
assign m_axi_wstrb[2] = \<const0> ;
assign m_axi_wstrb[1] = \<const0> ;
assign m_axi_wstrb[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_wready = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign valid = \<const0> ;
assign wr_ack = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth inst_fifo_gen
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.prog_empty(prog_empty),
.prog_full(prog_full),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth
(wr_rst_busy,
dout,
empty,
full,
rd_data_count,
wr_data_count,
prog_empty,
prog_full,
rd_en,
wr_clk,
rd_clk,
din,
rst,
wr_en);
output wr_rst_busy;
output [63:0]dout;
output empty;
output full;
output [9:0]rd_data_count;
output [8:0]wr_data_count;
output prog_empty;
output prog_full;
input rd_en;
input wr_clk;
input rd_clk;
input [63:0]din;
input rst;
input wr_en;
wire [63:0]din;
wire [63:0]dout;
wire empty;
wire full;
wire prog_empty;
wire prog_full;
wire rd_clk;
wire [9:0]rd_data_count;
wire rd_en;
wire rst;
wire wr_clk;
wire [8:0]wr_data_count;
wire wr_en;
wire wr_rst_busy;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top \gconvfifo.rf
(.din(din),
.dout(dout),
.empty(empty),
.full(full),
.prog_empty(prog_empty),
.prog_full(prog_full),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory
(dout,
wr_clk,
rd_clk,
E,
tmp_ram_rd_en,
out,
\gic0.gc0.count_d2_reg[9] ,
\gc0.count_d1_reg[9] ,
din);
output [63:0]dout;
input wr_clk;
input rd_clk;
input [0:0]E;
input tmp_ram_rd_en;
input [0:0]out;
input [9:0]\gic0.gc0.count_d2_reg[9] ;
input [9:0]\gc0.count_d1_reg[9] ;
input [63:0]din;
wire [0:0]E;
wire [63:0]din;
wire [63:0]dout;
wire [9:0]\gc0.count_d1_reg[9] ;
wire [9:0]\gic0.gc0.count_d2_reg[9] ;
wire [0:0]out;
wire rd_clk;
wire tmp_ram_rd_en;
wire wr_clk;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_blk_mem_gen_v8_3_4 \gbm.gbmg.gbmga.ngecc.bmg
(.E(E),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[9] (\gc0.count_d1_reg[9] ),
.\gic0.gc0.count_d2_reg[9] (\gic0.gc0.count_d2_reg[9] ),
.out(out),
.rd_clk(rd_clk),
.tmp_ram_rd_en(tmp_ram_rd_en),
.wr_clk(wr_clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr
(Q,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
E,
rd_clk,
AR);
output [9:0]Q;
output [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
input [0:0]E;
input rd_clk;
input [0:0]AR;
wire [0:0]AR;
wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [0:0]E;
wire [9:0]Q;
wire \gc0.count[9]_i_2_n_0 ;
wire [9:0]plusOp__0;
wire rd_clk;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1
(.I0(Q[0]),
.O(plusOp__0[0]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(plusOp__0[3]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gc0.count[4]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(plusOp__0[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gc0.count[5]_i_1
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[4]),
.I5(Q[5]),
.O(plusOp__0[5]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h6))
\gc0.count[6]_i_1
(.I0(\gc0.count[9]_i_2_n_0 ),
.I1(Q[6]),
.O(plusOp__0[6]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[7]_i_1
(.I0(\gc0.count[9]_i_2_n_0 ),
.I1(Q[6]),
.I2(Q[7]),
.O(plusOp__0[7]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[8]_i_1
(.I0(Q[6]),
.I1(\gc0.count[9]_i_2_n_0 ),
.I2(Q[7]),
.I3(Q[8]),
.O(plusOp__0[8]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gc0.count[9]_i_1
(.I0(Q[7]),
.I1(\gc0.count[9]_i_2_n_0 ),
.I2(Q[6]),
.I3(Q[8]),
.I4(Q[9]),
.O(plusOp__0[9]));
LUT6 #(
.INIT(64'h8000000000000000))
\gc0.count[9]_i_2
(.I0(Q[5]),
.I1(Q[3]),
.I2(Q[1]),
.I3(Q[0]),
.I4(Q[2]),
.I5(Q[4]),
.O(\gc0.count[9]_i_2_n_0 ));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(Q[0]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(Q[1]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(Q[2]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(Q[3]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(Q[4]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[5]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(Q[5]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[6]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(Q[6]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[7]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(Q[7]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[8]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(Q[8]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[9]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(Q[9]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(rd_clk),
.CE(E),
.D(plusOp__0[0]),
.PRE(AR),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[4]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[5]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[6]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[7]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[8]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[9]
(.C(rd_clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[9]),
.Q(Q[9]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_dc_as
(rd_data_count,
\gnxpm_cdc.wr_pntr_bin_reg[8] ,
rd_clk,
AR);
output [9:0]rd_data_count;
input [9:0]\gnxpm_cdc.wr_pntr_bin_reg[8] ;
input rd_clk;
input [0:0]AR;
wire [0:0]AR;
wire [9:0]\gnxpm_cdc.wr_pntr_bin_reg[8] ;
wire rd_clk;
wire [9:0]rd_data_count;
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.wr_pntr_bin_reg[8] [0]),
.Q(rd_data_count[0]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.wr_pntr_bin_reg[8] [1]),
.Q(rd_data_count[1]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.wr_pntr_bin_reg[8] [2]),
.Q(rd_data_count[2]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.wr_pntr_bin_reg[8] [3]),
.Q(rd_data_count[3]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.wr_pntr_bin_reg[8] [4]),
.Q(rd_data_count[4]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.wr_pntr_bin_reg[8] [5]),
.Q(rd_data_count[5]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.wr_pntr_bin_reg[8] [6]),
.Q(rd_data_count[6]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.wr_pntr_bin_reg[8] [7]),
.Q(rd_data_count[7]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.wr_pntr_bin_reg[8] [8]),
.Q(rd_data_count[8]));
FDCE #(
.INIT(1'b0))
\rd_dc_i_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.wr_pntr_bin_reg[8] [9]),
.Q(rd_data_count[9]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic
(empty,
out,
prog_empty,
Q,
p_0_out,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
rd_data_count,
v1_reg,
v1_reg_0,
rd_clk,
AR,
rd_en,
D,
\gnxpm_cdc.wr_pntr_bin_reg[8] );
output empty;
output out;
output prog_empty;
output [9:0]Q;
output p_0_out;
output [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
output [9:0]rd_data_count;
input [4:0]v1_reg;
input [4:0]v1_reg_0;
input rd_clk;
input [0:0]AR;
input rd_en;
input [9:0]D;
input [9:0]\gnxpm_cdc.wr_pntr_bin_reg[8] ;
wire [0:0]AR;
wire [9:0]D;
wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [9:0]Q;
wire empty;
wire [9:0]\gnxpm_cdc.wr_pntr_bin_reg[8] ;
wire \gras.rsts_n_2 ;
wire out;
wire p_0_out;
wire prog_empty;
wire rd_clk;
wire [9:0]rd_data_count;
wire rd_en;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as \gras.gpe.rdpe
(.AR(AR),
.D(D),
.out(out),
.prog_empty(prog_empty),
.rd_clk(rd_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_dc_as \gras.grdc1.rdc
(.AR(AR),
.\gnxpm_cdc.wr_pntr_bin_reg[8] (\gnxpm_cdc.wr_pntr_bin_reg[8] ),
.rd_clk(rd_clk),
.rd_data_count(rd_data_count));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as \gras.rsts
(.AR(AR),
.E(\gras.rsts_n_2 ),
.empty(empty),
.out(out),
.p_0_out(p_0_out),
.rd_clk(rd_clk),
.rd_en(rd_en),
.v1_reg(v1_reg),
.v1_reg_0(v1_reg_0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr rpntr
(.AR(AR),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ),
.E(\gras.rsts_n_2 ),
.Q(Q),
.rd_clk(rd_clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_pe_as
(prog_empty,
rd_clk,
AR,
out,
D);
output prog_empty;
input rd_clk;
input [0:0]AR;
input out;
input [9:0]D;
wire [0:0]AR;
wire [9:0]D;
wire \gdiff.diff_pntr_pad_reg_n_0_[10] ;
wire \gdiff.diff_pntr_pad_reg_n_0_[1] ;
wire \gdiff.diff_pntr_pad_reg_n_0_[2] ;
wire \gdiff.diff_pntr_pad_reg_n_0_[3] ;
wire \gdiff.diff_pntr_pad_reg_n_0_[4] ;
wire \gdiff.diff_pntr_pad_reg_n_0_[5] ;
wire \gdiff.diff_pntr_pad_reg_n_0_[6] ;
wire \gdiff.diff_pntr_pad_reg_n_0_[7] ;
wire \gdiff.diff_pntr_pad_reg_n_0_[8] ;
wire \gdiff.diff_pntr_pad_reg_n_0_[9] ;
wire \gpe1.prog_empty_i_i_1_n_0 ;
wire \gpe1.prog_empty_i_i_2_n_0 ;
wire \gpe1.prog_empty_i_i_3_n_0 ;
wire out;
wire prog_empty;
wire rd_clk;
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[10]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(D[9]),
.Q(\gdiff.diff_pntr_pad_reg_n_0_[10] ));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(D[0]),
.Q(\gdiff.diff_pntr_pad_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(D[1]),
.Q(\gdiff.diff_pntr_pad_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(D[2]),
.Q(\gdiff.diff_pntr_pad_reg_n_0_[3] ));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(D[3]),
.Q(\gdiff.diff_pntr_pad_reg_n_0_[4] ));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(D[4]),
.Q(\gdiff.diff_pntr_pad_reg_n_0_[5] ));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(D[5]),
.Q(\gdiff.diff_pntr_pad_reg_n_0_[6] ));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(D[6]),
.Q(\gdiff.diff_pntr_pad_reg_n_0_[7] ));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(D[7]),
.Q(\gdiff.diff_pntr_pad_reg_n_0_[8] ));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(AR),
.D(D[8]),
.Q(\gdiff.diff_pntr_pad_reg_n_0_[9] ));
LUT5 #(
.INIT(32'h8B8BBB8B))
\gpe1.prog_empty_i_i_1
(.I0(prog_empty),
.I1(out),
.I2(\gpe1.prog_empty_i_i_2_n_0 ),
.I3(\gpe1.prog_empty_i_i_3_n_0 ),
.I4(\gdiff.diff_pntr_pad_reg_n_0_[7] ),
.O(\gpe1.prog_empty_i_i_1_n_0 ));
LUT3 #(
.INIT(8'h80))
\gpe1.prog_empty_i_i_2
(.I0(\gdiff.diff_pntr_pad_reg_n_0_[9] ),
.I1(\gdiff.diff_pntr_pad_reg_n_0_[10] ),
.I2(\gdiff.diff_pntr_pad_reg_n_0_[8] ),
.O(\gpe1.prog_empty_i_i_2_n_0 ));
LUT6 #(
.INIT(64'h7F7F7FFFFFFFFFFF))
\gpe1.prog_empty_i_i_3
(.I0(\gdiff.diff_pntr_pad_reg_n_0_[3] ),
.I1(\gdiff.diff_pntr_pad_reg_n_0_[4] ),
.I2(\gdiff.diff_pntr_pad_reg_n_0_[6] ),
.I3(\gdiff.diff_pntr_pad_reg_n_0_[2] ),
.I4(\gdiff.diff_pntr_pad_reg_n_0_[1] ),
.I5(\gdiff.diff_pntr_pad_reg_n_0_[5] ),
.O(\gpe1.prog_empty_i_i_3_n_0 ));
FDPE #(
.INIT(1'b1))
\gpe1.prog_empty_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(\gpe1.prog_empty_i_i_1_n_0 ),
.PRE(AR),
.Q(prog_empty));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_as
(empty,
out,
E,
p_0_out,
v1_reg,
v1_reg_0,
rd_clk,
AR,
rd_en);
output empty;
output out;
output [0:0]E;
output p_0_out;
input [4:0]v1_reg;
input [4:0]v1_reg_0;
input rd_clk;
input [0:0]AR;
input rd_en;
wire [0:0]AR;
wire [0:0]E;
wire c0_n_0;
wire comp1;
wire p_0_out;
(* DONT_TOUCH *) wire ram_empty_fb_i;
(* DONT_TOUCH *) wire ram_empty_i;
wire rd_clk;
wire rd_en;
wire [4:0]v1_reg;
wire [4:0]v1_reg_0;
assign empty = ram_empty_i;
assign out = ram_empty_fb_i;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_4 c0
(.comp1(comp1),
.out(ram_empty_fb_i),
.ram_empty_fb_i_reg(c0_n_0),
.rd_en(rd_en),
.v1_reg(v1_reg));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_5 c1
(.comp1(comp1),
.v1_reg_0(v1_reg_0));
LUT2 #(
.INIT(4'h2))
\gc0.count_d1[9]_i_1
(.I0(rd_en),
.I1(ram_empty_fb_i),
.O(E));
LUT2 #(
.INIT(4'hB))
\gdiff.diff_pntr_pad[4]_i_2
(.I0(ram_empty_fb_i),
.I1(rd_en),
.O(p_0_out));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(c0_n_0),
.PRE(AR),
.Q(ram_empty_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(rd_clk),
.CE(1'b1),
.D(c0_n_0),
.PRE(AR),
.Q(ram_empty_i));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo
(out,
\gc0.count_reg[1] ,
\grstd1.grst_full.grst_f.rst_d3_reg_0 ,
wr_rst_busy,
tmp_ram_rd_en,
rd_clk,
wr_clk,
rst,
ram_empty_fb_i_reg,
rd_en);
output [1:0]out;
output [2:0]\gc0.count_reg[1] ;
output \grstd1.grst_full.grst_f.rst_d3_reg_0 ;
output wr_rst_busy;
output tmp_ram_rd_en;
input rd_clk;
input wr_clk;
input rst;
input ram_empty_fb_i_reg;
input rd_en;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ;
wire p_7_out;
wire p_8_out;
wire ram_empty_fb_i_reg;
wire rd_clk;
wire rd_en;
wire rd_rst_asreg;
(* DONT_TOUCH *) wire [2:0]rd_rst_reg;
wire rst;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire tmp_ram_rd_en;
wire wr_clk;
wire wr_rst_asreg;
(* DONT_TOUCH *) wire [2:0]wr_rst_reg;
assign \gc0.count_reg[1] [2:0] = rd_rst_reg;
assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2;
assign out[1:0] = wr_rst_reg[1:0];
assign wr_rst_busy = rst_d3;
LUT3 #(
.INIT(8'hBA))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_2
(.I0(rd_rst_reg[0]),
.I1(ram_empty_fb_i_reg),
.I2(rd_en),
.O(tmp_ram_rd_en));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst_wr_reg2),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst_wr_reg2),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst_wr_reg2),
.Q(rst_d3));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst
(.in0(rd_rst_asreg),
.\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg (\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ),
.out(p_7_out),
.rd_clk(rd_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst
(.in0(wr_rst_asreg),
.\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg (\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ),
.out(p_8_out),
.wr_clk(wr_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.in0(rd_rst_asreg),
.out(p_7_out),
.rd_clk(rd_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.in0(wr_rst_asreg),
.out(p_8_out),
.wr_clk(wr_clk));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(rd_clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(rd_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(rd_clk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(rst),
.Q(rst_rd_reg2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(wr_clk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(rst),
.Q(rst_wr_reg2));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(wr_clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[2]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff
(out,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ,
in0,
rd_clk);
output out;
output \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ;
input [0:0]in0;
input rd_clk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ;
wire rd_clk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1
(.I0(in0),
.I1(Q_reg),
.O(\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0
(out,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ,
in0,
wr_clk);
output out;
output \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ;
input [0:0]in0;
input wr_clk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ;
wire wr_clk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1
(.I0(in0),
.I1(Q_reg),
.O(\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1
(AS,
out,
rd_clk,
in0);
output [0:0]AS;
input out;
input rd_clk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire out;
wire rd_clk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2
(AS,
out,
wr_clk,
in0);
output [0:0]AS;
input out;
input wr_clk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire out;
wire wr_clk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized0
(D,
Q,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [9:0]D;
input [9:0]Q;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [9:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [9:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire rd_clk;
assign D[9:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[8]),
.Q(Q_reg[8]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[9]),
.Q(Q_reg[9]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized1
(D,
Q,
wr_clk,
AR);
output [9:0]D;
input [9:0]Q;
input wr_clk;
input [0:0]AR;
wire [0:0]AR;
wire [9:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [9:0]Q_reg;
wire wr_clk;
assign D[9:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[8]),
.Q(Q_reg[8]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(Q[9]),
.Q(Q_reg[9]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized2
(out,
\gnxpm_cdc.wr_pntr_bin_reg[8] ,
D,
rd_clk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [0:0]out;
output [8:0]\gnxpm_cdc.wr_pntr_bin_reg[8] ;
input [9:0]D;
input rd_clk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [9:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [9:0]Q_reg;
wire \gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0 ;
wire \gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ;
wire \gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 ;
wire [8:0]\gnxpm_cdc.wr_pntr_bin_reg[8] ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire rd_clk;
assign out[0] = Q_reg[9];
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[8]),
.Q(Q_reg[8]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(rd_clk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[9]),
.Q(Q_reg[9]));
LUT5 #(
.INIT(32'h96696996))
\gnxpm_cdc.wr_pntr_bin[0]_i_1
(.I0(Q_reg[1]),
.I1(Q_reg[0]),
.I2(Q_reg[2]),
.I3(\gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0 ),
.I4(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [0]));
LUT3 #(
.INIT(8'h96))
\gnxpm_cdc.wr_pntr_bin[0]_i_2
(.I0(Q_reg[4]),
.I1(Q_reg[3]),
.I2(Q_reg[9]),
.O(\gnxpm_cdc.wr_pntr_bin[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\gnxpm_cdc.wr_pntr_bin[1]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[9]),
.I2(Q_reg[3]),
.I3(Q_reg[4]),
.I4(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ),
.I5(Q_reg[1]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [1]));
LUT5 #(
.INIT(32'h96696996))
\gnxpm_cdc.wr_pntr_bin[2]_i_1
(.I0(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ),
.I1(Q_reg[4]),
.I2(Q_reg[3]),
.I3(Q_reg[9]),
.I4(Q_reg[2]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [2]));
LUT4 #(
.INIT(16'h6996))
\gnxpm_cdc.wr_pntr_bin[2]_i_2
(.I0(Q_reg[8]),
.I1(Q_reg[7]),
.I2(Q_reg[6]),
.I3(Q_reg[5]),
.O(\gnxpm_cdc.wr_pntr_bin[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\gnxpm_cdc.wr_pntr_bin[3]_i_1
(.I0(Q_reg[9]),
.I1(Q_reg[3]),
.I2(Q_reg[4]),
.I3(\gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 ),
.I4(Q_reg[7]),
.I5(Q_reg[8]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_bin[3]_i_2
(.I0(Q_reg[5]),
.I1(Q_reg[6]),
.O(\gnxpm_cdc.wr_pntr_bin[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\gnxpm_cdc.wr_pntr_bin[4]_i_1
(.I0(Q_reg[6]),
.I1(Q_reg[4]),
.I2(Q_reg[5]),
.I3(Q_reg[9]),
.I4(Q_reg[7]),
.I5(Q_reg[8]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [4]));
LUT5 #(
.INIT(32'h96696996))
\gnxpm_cdc.wr_pntr_bin[5]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[5]),
.I2(Q_reg[6]),
.I3(Q_reg[9]),
.I4(Q_reg[8]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [5]));
LUT4 #(
.INIT(16'h6996))
\gnxpm_cdc.wr_pntr_bin[6]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[6]),
.I2(Q_reg[9]),
.I3(Q_reg[8]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [6]));
LUT3 #(
.INIT(8'h96))
\gnxpm_cdc.wr_pntr_bin[7]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[7]),
.I2(Q_reg[9]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [7]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_bin[8]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[9]),
.O(\gnxpm_cdc.wr_pntr_bin_reg[8] [8]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff__parameterized3
(out,
\gnxpm_cdc.rd_pntr_bin_reg[8] ,
D,
wr_clk,
AR);
output [0:0]out;
output [8:0]\gnxpm_cdc.rd_pntr_bin_reg[8] ;
input [9:0]D;
input wr_clk;
input [0:0]AR;
wire [0:0]AR;
wire [9:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [9:0]Q_reg;
wire \gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0 ;
wire \gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ;
wire \gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0 ;
wire [8:0]\gnxpm_cdc.rd_pntr_bin_reg[8] ;
wire wr_clk;
assign out[0] = Q_reg[9];
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[3]),
.Q(Q_reg[3]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[4]),
.Q(Q_reg[4]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[5]),
.Q(Q_reg[5]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[6]),
.Q(Q_reg[6]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[7]),
.Q(Q_reg[7]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[8]),
.Q(Q_reg[8]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(D[9]),
.Q(Q_reg[9]));
LUT5 #(
.INIT(32'h96696996))
\gnxpm_cdc.rd_pntr_bin[0]_i_1
(.I0(Q_reg[1]),
.I1(Q_reg[0]),
.I2(Q_reg[2]),
.I3(\gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0 ),
.I4(\gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [0]));
LUT3 #(
.INIT(8'h96))
\gnxpm_cdc.rd_pntr_bin[0]_i_2
(.I0(Q_reg[4]),
.I1(Q_reg[3]),
.I2(Q_reg[9]),
.O(\gnxpm_cdc.rd_pntr_bin[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\gnxpm_cdc.rd_pntr_bin[1]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[9]),
.I2(Q_reg[3]),
.I3(Q_reg[4]),
.I4(\gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ),
.I5(Q_reg[1]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [1]));
LUT5 #(
.INIT(32'h96696996))
\gnxpm_cdc.rd_pntr_bin[2]_i_1
(.I0(\gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ),
.I1(Q_reg[4]),
.I2(Q_reg[3]),
.I3(Q_reg[9]),
.I4(Q_reg[2]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [2]));
LUT4 #(
.INIT(16'h6996))
\gnxpm_cdc.rd_pntr_bin[2]_i_2
(.I0(Q_reg[8]),
.I1(Q_reg[7]),
.I2(Q_reg[6]),
.I3(Q_reg[5]),
.O(\gnxpm_cdc.rd_pntr_bin[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\gnxpm_cdc.rd_pntr_bin[3]_i_1
(.I0(Q_reg[9]),
.I1(Q_reg[3]),
.I2(Q_reg[4]),
.I3(\gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0 ),
.I4(Q_reg[7]),
.I5(Q_reg[8]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_bin[3]_i_2
(.I0(Q_reg[5]),
.I1(Q_reg[6]),
.O(\gnxpm_cdc.rd_pntr_bin[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6996966996696996))
\gnxpm_cdc.rd_pntr_bin[4]_i_1
(.I0(Q_reg[6]),
.I1(Q_reg[4]),
.I2(Q_reg[5]),
.I3(Q_reg[9]),
.I4(Q_reg[7]),
.I5(Q_reg[8]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [4]));
LUT5 #(
.INIT(32'h96696996))
\gnxpm_cdc.rd_pntr_bin[5]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[5]),
.I2(Q_reg[6]),
.I3(Q_reg[9]),
.I4(Q_reg[8]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [5]));
LUT4 #(
.INIT(16'h6996))
\gnxpm_cdc.rd_pntr_bin[6]_i_1
(.I0(Q_reg[7]),
.I1(Q_reg[6]),
.I2(Q_reg[9]),
.I3(Q_reg[8]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [6]));
LUT3 #(
.INIT(8'h96))
\gnxpm_cdc.rd_pntr_bin[7]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[7]),
.I2(Q_reg[9]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [7]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_bin[8]_i_1
(.I0(Q_reg[8]),
.I1(Q_reg[9]),
.O(\gnxpm_cdc.rd_pntr_bin_reg[8] [8]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr
(\wr_data_count_i_reg[9] ,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
\gdiff.diff_pntr_pad_reg[10] ,
Q,
\wr_data_count_i_reg[7] ,
\gdiff.diff_pntr_pad_reg[8] ,
S,
\gdiff.diff_pntr_pad_reg[4] ,
\gic0.gc0.count_d1_reg[9]_0 ,
v1_reg,
RD_PNTR_WR,
E,
wr_clk,
AR);
output [1:0]\wr_data_count_i_reg[9] ;
output [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
output [1:0]\gdiff.diff_pntr_pad_reg[10] ;
output [8:0]Q;
output [3:0]\wr_data_count_i_reg[7] ;
output [3:0]\gdiff.diff_pntr_pad_reg[8] ;
output [3:0]S;
output [3:0]\gdiff.diff_pntr_pad_reg[4] ;
output [9:0]\gic0.gc0.count_d1_reg[9]_0 ;
output [0:0]v1_reg;
input [9:0]RD_PNTR_WR;
input [0:0]E;
input wr_clk;
input [0:0]AR;
wire [0:0]AR;
wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [0:0]E;
wire [8:0]Q;
wire [9:0]RD_PNTR_WR;
wire [3:0]S;
wire [1:0]\gdiff.diff_pntr_pad_reg[10] ;
wire [3:0]\gdiff.diff_pntr_pad_reg[4] ;
wire [3:0]\gdiff.diff_pntr_pad_reg[8] ;
wire \gic0.gc0.count[9]_i_2_n_0 ;
wire [9:0]\gic0.gc0.count_d1_reg[9]_0 ;
wire [9:9]p_13_out;
wire [9:0]plusOp__1;
wire [0:0]v1_reg;
wire wr_clk;
wire [3:0]\wr_data_count_i_reg[7] ;
wire [1:0]\wr_data_count_i_reg[9] ;
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT1 #(
.INIT(2'h1))
\gic0.gc0.count[0]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [0]),
.O(plusOp__1[0]));
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[1]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [0]),
.I1(\gic0.gc0.count_d1_reg[9]_0 [1]),
.O(plusOp__1[1]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'h78))
\gic0.gc0.count[2]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [0]),
.I1(\gic0.gc0.count_d1_reg[9]_0 [1]),
.I2(\gic0.gc0.count_d1_reg[9]_0 [2]),
.O(plusOp__1[2]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h7F80))
\gic0.gc0.count[3]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [1]),
.I1(\gic0.gc0.count_d1_reg[9]_0 [0]),
.I2(\gic0.gc0.count_d1_reg[9]_0 [2]),
.I3(\gic0.gc0.count_d1_reg[9]_0 [3]),
.O(plusOp__1[3]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT5 #(
.INIT(32'h7FFF8000))
\gic0.gc0.count[4]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [2]),
.I1(\gic0.gc0.count_d1_reg[9]_0 [0]),
.I2(\gic0.gc0.count_d1_reg[9]_0 [1]),
.I3(\gic0.gc0.count_d1_reg[9]_0 [3]),
.I4(\gic0.gc0.count_d1_reg[9]_0 [4]),
.O(plusOp__1[4]));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\gic0.gc0.count[5]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [3]),
.I1(\gic0.gc0.count_d1_reg[9]_0 [1]),
.I2(\gic0.gc0.count_d1_reg[9]_0 [0]),
.I3(\gic0.gc0.count_d1_reg[9]_0 [2]),
.I4(\gic0.gc0.count_d1_reg[9]_0 [4]),
.I5(\gic0.gc0.count_d1_reg[9]_0 [5]),
.O(plusOp__1[5]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h9))
\gic0.gc0.count[6]_i_1
(.I0(\gic0.gc0.count[9]_i_2_n_0 ),
.I1(\gic0.gc0.count_d1_reg[9]_0 [6]),
.O(plusOp__1[6]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB4))
\gic0.gc0.count[7]_i_1
(.I0(\gic0.gc0.count[9]_i_2_n_0 ),
.I1(\gic0.gc0.count_d1_reg[9]_0 [6]),
.I2(\gic0.gc0.count_d1_reg[9]_0 [7]),
.O(plusOp__1[7]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'hDF20))
\gic0.gc0.count[8]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [6]),
.I1(\gic0.gc0.count[9]_i_2_n_0 ),
.I2(\gic0.gc0.count_d1_reg[9]_0 [7]),
.I3(\gic0.gc0.count_d1_reg[9]_0 [8]),
.O(plusOp__1[8]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'hF7FF0800))
\gic0.gc0.count[9]_i_1
(.I0(\gic0.gc0.count_d1_reg[9]_0 [8]),
.I1(\gic0.gc0.count_d1_reg[9]_0 [7]),
.I2(\gic0.gc0.count[9]_i_2_n_0 ),
.I3(\gic0.gc0.count_d1_reg[9]_0 [6]),
.I4(\gic0.gc0.count_d1_reg[9]_0 [9]),
.O(plusOp__1[9]));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\gic0.gc0.count[9]_i_2
(.I0(\gic0.gc0.count_d1_reg[9]_0 [5]),
.I1(\gic0.gc0.count_d1_reg[9]_0 [3]),
.I2(\gic0.gc0.count_d1_reg[9]_0 [1]),
.I3(\gic0.gc0.count_d1_reg[9]_0 [0]),
.I4(\gic0.gc0.count_d1_reg[9]_0 [2]),
.I5(\gic0.gc0.count_d1_reg[9]_0 [4]),
.O(\gic0.gc0.count[9]_i_2_n_0 ));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_d1_reg[0]
(.C(wr_clk),
.CE(E),
.D(\gic0.gc0.count_d1_reg[9]_0 [0]),
.PRE(AR),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[1]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d1_reg[9]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d1_reg[9]_0 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d1_reg[9]_0 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d1_reg[9]_0 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d1_reg[9]_0 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d1_reg[9]_0 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d1_reg[9]_0 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[8]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d1_reg[9]_0 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[9]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d1_reg[9]_0 [9]),
.Q(p_13_out));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[0]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(Q[0]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[1]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(Q[1]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(Q[2]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(Q[3]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(Q[4]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(Q[5]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(Q[6]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(Q[7]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[8]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(Q[8]),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[9]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(p_13_out),
.Q(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[0]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__1[0]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [0]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_reg[1]
(.C(wr_clk),
.CE(E),
.D(plusOp__1[1]),
.PRE(AR),
.Q(\gic0.gc0.count_d1_reg[9]_0 [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[2]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__1[2]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[3]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__1[3]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[4]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__1[4]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [4]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[5]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__1[5]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [5]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[6]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__1[6]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [6]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[7]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__1[7]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [7]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[8]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__1[8]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [8]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[9]
(.C(wr_clk),
.CE(E),
.CLR(AR),
.D(plusOp__1[9]),
.Q(\gic0.gc0.count_d1_reg[9]_0 [9]));
LUT4 #(
.INIT(16'h9009))
\gmux.gm[4].gms.ms_i_1__1
(.I0(p_13_out),
.I1(RD_PNTR_WR[9]),
.I2(RD_PNTR_WR[8]),
.I3(Q[8]),
.O(v1_reg));
LUT2 #(
.INIT(4'h9))
minusOp_carry__0_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [7]),
.I1(RD_PNTR_WR[7]),
.O(\wr_data_count_i_reg[7] [3]));
LUT2 #(
.INIT(4'h9))
minusOp_carry__0_i_2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [6]),
.I1(RD_PNTR_WR[6]),
.O(\wr_data_count_i_reg[7] [2]));
LUT2 #(
.INIT(4'h9))
minusOp_carry__0_i_3
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [5]),
.I1(RD_PNTR_WR[5]),
.O(\wr_data_count_i_reg[7] [1]));
LUT2 #(
.INIT(4'h9))
minusOp_carry__0_i_4
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [4]),
.I1(RD_PNTR_WR[4]),
.O(\wr_data_count_i_reg[7] [0]));
LUT2 #(
.INIT(4'h9))
minusOp_carry__1_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [9]),
.I1(RD_PNTR_WR[9]),
.O(\wr_data_count_i_reg[9] [1]));
LUT2 #(
.INIT(4'h9))
minusOp_carry__1_i_2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8]),
.I1(RD_PNTR_WR[8]),
.O(\wr_data_count_i_reg[9] [0]));
LUT2 #(
.INIT(4'h9))
minusOp_carry_i_1
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [3]),
.I1(RD_PNTR_WR[3]),
.O(S[3]));
LUT2 #(
.INIT(4'h9))
minusOp_carry_i_2
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [2]),
.I1(RD_PNTR_WR[2]),
.O(S[2]));
LUT2 #(
.INIT(4'h9))
minusOp_carry_i_3
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [1]),
.I1(RD_PNTR_WR[1]),
.O(S[1]));
LUT2 #(
.INIT(4'h9))
minusOp_carry_i_4
(.I0(\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [0]),
.I1(RD_PNTR_WR[0]),
.O(S[0]));
LUT2 #(
.INIT(4'h9))
plusOp_carry__0_i_1
(.I0(Q[7]),
.I1(RD_PNTR_WR[7]),
.O(\gdiff.diff_pntr_pad_reg[8] [3]));
LUT2 #(
.INIT(4'h9))
plusOp_carry__0_i_2
(.I0(Q[6]),
.I1(RD_PNTR_WR[6]),
.O(\gdiff.diff_pntr_pad_reg[8] [2]));
LUT2 #(
.INIT(4'h9))
plusOp_carry__0_i_3
(.I0(Q[5]),
.I1(RD_PNTR_WR[5]),
.O(\gdiff.diff_pntr_pad_reg[8] [1]));
LUT2 #(
.INIT(4'h9))
plusOp_carry__0_i_4
(.I0(Q[4]),
.I1(RD_PNTR_WR[4]),
.O(\gdiff.diff_pntr_pad_reg[8] [0]));
LUT2 #(
.INIT(4'h9))
plusOp_carry__1_i_1
(.I0(p_13_out),
.I1(RD_PNTR_WR[9]),
.O(\gdiff.diff_pntr_pad_reg[10] [1]));
LUT2 #(
.INIT(4'h9))
plusOp_carry__1_i_2
(.I0(Q[8]),
.I1(RD_PNTR_WR[8]),
.O(\gdiff.diff_pntr_pad_reg[10] [0]));
LUT2 #(
.INIT(4'h9))
plusOp_carry_i_1
(.I0(Q[3]),
.I1(RD_PNTR_WR[3]),
.O(\gdiff.diff_pntr_pad_reg[4] [3]));
LUT2 #(
.INIT(4'h9))
plusOp_carry_i_2
(.I0(Q[2]),
.I1(RD_PNTR_WR[2]),
.O(\gdiff.diff_pntr_pad_reg[4] [2]));
LUT2 #(
.INIT(4'h9))
plusOp_carry_i_3
(.I0(Q[1]),
.I1(RD_PNTR_WR[1]),
.O(\gdiff.diff_pntr_pad_reg[4] [1]));
LUT2 #(
.INIT(4'h9))
plusOp_carry_i_4
(.I0(Q[0]),
.I1(RD_PNTR_WR[0]),
.O(\gdiff.diff_pntr_pad_reg[4] [0]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_dc_as
(wr_data_count,
\gic0.gc0.count_d2_reg[8] ,
S,
\gic0.gc0.count_d2_reg[7] ,
\gic0.gc0.count_d2_reg[9] ,
wr_clk,
AR);
output [8:0]wr_data_count;
input [8:0]\gic0.gc0.count_d2_reg[8] ;
input [3:0]S;
input [3:0]\gic0.gc0.count_d2_reg[7] ;
input [1:0]\gic0.gc0.count_d2_reg[9] ;
input wr_clk;
input [0:0]AR;
wire [0:0]AR;
wire [3:0]S;
wire [3:0]\gic0.gc0.count_d2_reg[7] ;
wire [8:0]\gic0.gc0.count_d2_reg[8] ;
wire [1:0]\gic0.gc0.count_d2_reg[9] ;
wire minusOp_carry__0_n_0;
wire minusOp_carry__0_n_1;
wire minusOp_carry__0_n_2;
wire minusOp_carry__0_n_3;
wire minusOp_carry__0_n_4;
wire minusOp_carry__0_n_5;
wire minusOp_carry__0_n_6;
wire minusOp_carry__0_n_7;
wire minusOp_carry__1_n_3;
wire minusOp_carry__1_n_6;
wire minusOp_carry__1_n_7;
wire minusOp_carry_n_0;
wire minusOp_carry_n_1;
wire minusOp_carry_n_2;
wire minusOp_carry_n_3;
wire minusOp_carry_n_4;
wire minusOp_carry_n_5;
wire minusOp_carry_n_6;
wire wr_clk;
wire [8:0]wr_data_count;
wire [0:0]NLW_minusOp_carry_O_UNCONNECTED;
wire [3:1]NLW_minusOp_carry__1_CO_UNCONNECTED;
wire [3:2]NLW_minusOp_carry__1_O_UNCONNECTED;
CARRY4 minusOp_carry
(.CI(1'b0),
.CO({minusOp_carry_n_0,minusOp_carry_n_1,minusOp_carry_n_2,minusOp_carry_n_3}),
.CYINIT(1'b1),
.DI(\gic0.gc0.count_d2_reg[8] [3:0]),
.O({minusOp_carry_n_4,minusOp_carry_n_5,minusOp_carry_n_6,NLW_minusOp_carry_O_UNCONNECTED[0]}),
.S(S));
CARRY4 minusOp_carry__0
(.CI(minusOp_carry_n_0),
.CO({minusOp_carry__0_n_0,minusOp_carry__0_n_1,minusOp_carry__0_n_2,minusOp_carry__0_n_3}),
.CYINIT(1'b0),
.DI(\gic0.gc0.count_d2_reg[8] [7:4]),
.O({minusOp_carry__0_n_4,minusOp_carry__0_n_5,minusOp_carry__0_n_6,minusOp_carry__0_n_7}),
.S(\gic0.gc0.count_d2_reg[7] ));
CARRY4 minusOp_carry__1
(.CI(minusOp_carry__0_n_0),
.CO({NLW_minusOp_carry__1_CO_UNCONNECTED[3:1],minusOp_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,\gic0.gc0.count_d2_reg[8] [8]}),
.O({NLW_minusOp_carry__1_O_UNCONNECTED[3:2],minusOp_carry__1_n_6,minusOp_carry__1_n_7}),
.S({1'b0,1'b0,\gic0.gc0.count_d2_reg[9] }));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(minusOp_carry_n_6),
.Q(wr_data_count[0]));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(minusOp_carry_n_5),
.Q(wr_data_count[1]));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(minusOp_carry_n_4),
.Q(wr_data_count[2]));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(minusOp_carry__0_n_7),
.Q(wr_data_count[3]));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(minusOp_carry__0_n_6),
.Q(wr_data_count[4]));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(minusOp_carry__0_n_5),
.Q(wr_data_count[5]));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(minusOp_carry__0_n_4),
.Q(wr_data_count[6]));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(minusOp_carry__1_n_7),
.Q(wr_data_count[7]));
FDCE #(
.INIT(1'b0))
\wr_data_count_i_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(minusOp_carry__1_n_6),
.Q(wr_data_count[8]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic
(full,
E,
Q,
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ,
prog_full,
\gic0.gc0.count_d1_reg[9] ,
wr_data_count,
\gnxpm_cdc.rd_pntr_bin_reg[6] ,
v1_reg,
wr_clk,
out,
RD_PNTR_WR,
wr_en,
wr_rst_busy,
AR);
output full;
output [0:0]E;
output [7:0]Q;
output [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
output prog_full;
output [9:0]\gic0.gc0.count_d1_reg[9] ;
output [8:0]wr_data_count;
input [3:0]\gnxpm_cdc.rd_pntr_bin_reg[6] ;
input [4:0]v1_reg;
input wr_clk;
input out;
input [9:0]RD_PNTR_WR;
input wr_en;
input wr_rst_busy;
input [0:0]AR;
wire [0:0]AR;
wire [9:0]\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ;
wire [0:0]E;
wire [7:0]Q;
wire [9:0]RD_PNTR_WR;
wire [4:4]\c1/v1_reg ;
wire full;
wire [9:0]\gic0.gc0.count_d1_reg[9] ;
wire [3:0]\gnxpm_cdc.rd_pntr_bin_reg[6] ;
wire \gwas.wsts_n_1 ;
wire out;
wire [8:8]p_13_out;
wire prog_full;
wire [4:0]v1_reg;
wire wpntr_n_0;
wire wpntr_n_1;
wire wpntr_n_12;
wire wpntr_n_13;
wire wpntr_n_23;
wire wpntr_n_24;
wire wpntr_n_25;
wire wpntr_n_26;
wire wpntr_n_27;
wire wpntr_n_28;
wire wpntr_n_29;
wire wpntr_n_30;
wire wpntr_n_31;
wire wpntr_n_32;
wire wpntr_n_33;
wire wpntr_n_34;
wire wpntr_n_35;
wire wpntr_n_36;
wire wpntr_n_37;
wire wpntr_n_38;
wire wr_clk;
wire [8:0]wr_data_count;
wire wr_en;
wire wr_rst_busy;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_pf_as \gwas.gpf.wrpf
(.AR(AR),
.E(E),
.Q({p_13_out,Q}),
.S({wpntr_n_35,wpntr_n_36,wpntr_n_37,wpntr_n_38}),
.\gic0.gc0.count_d1_reg[7] ({wpntr_n_27,wpntr_n_28,wpntr_n_29,wpntr_n_30}),
.\gic0.gc0.count_d1_reg[9] ({wpntr_n_12,wpntr_n_13}),
.out(out),
.prog_full(prog_full),
.ram_full_fb_i_reg(\gwas.wsts_n_1 ),
.wr_clk(wr_clk),
.wr_rst_busy(wr_rst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_dc_as \gwas.gwdc0.wdc
(.AR(AR),
.S({wpntr_n_31,wpntr_n_32,wpntr_n_33,wpntr_n_34}),
.\gic0.gc0.count_d2_reg[7] ({wpntr_n_23,wpntr_n_24,wpntr_n_25,wpntr_n_26}),
.\gic0.gc0.count_d2_reg[8] (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram [8:0]),
.\gic0.gc0.count_d2_reg[9] ({wpntr_n_0,wpntr_n_1}),
.wr_clk(wr_clk),
.wr_data_count(wr_data_count));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as \gwas.wsts
(.E(E),
.full(full),
.\gnxpm_cdc.rd_pntr_bin_reg[6] (\gnxpm_cdc.rd_pntr_bin_reg[6] ),
.\grstd1.grst_full.grst_f.rst_d2_reg (out),
.out(\gwas.wsts_n_1 ),
.v1_reg(v1_reg),
.v1_reg_0(\c1/v1_reg ),
.wr_clk(wr_clk),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr wpntr
(.AR(AR),
.\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram (\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram ),
.E(E),
.Q({p_13_out,Q}),
.RD_PNTR_WR(RD_PNTR_WR),
.S({wpntr_n_31,wpntr_n_32,wpntr_n_33,wpntr_n_34}),
.\gdiff.diff_pntr_pad_reg[10] ({wpntr_n_12,wpntr_n_13}),
.\gdiff.diff_pntr_pad_reg[4] ({wpntr_n_35,wpntr_n_36,wpntr_n_37,wpntr_n_38}),
.\gdiff.diff_pntr_pad_reg[8] ({wpntr_n_27,wpntr_n_28,wpntr_n_29,wpntr_n_30}),
.\gic0.gc0.count_d1_reg[9]_0 (\gic0.gc0.count_d1_reg[9] ),
.v1_reg(\c1/v1_reg ),
.wr_clk(wr_clk),
.\wr_data_count_i_reg[7] ({wpntr_n_23,wpntr_n_24,wpntr_n_25,wpntr_n_26}),
.\wr_data_count_i_reg[9] ({wpntr_n_0,wpntr_n_1}));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_pf_as
(prog_full,
E,
Q,
S,
\gic0.gc0.count_d1_reg[7] ,
\gic0.gc0.count_d1_reg[9] ,
wr_clk,
out,
wr_rst_busy,
ram_full_fb_i_reg,
AR);
output prog_full;
input [0:0]E;
input [8:0]Q;
input [3:0]S;
input [3:0]\gic0.gc0.count_d1_reg[7] ;
input [1:0]\gic0.gc0.count_d1_reg[9] ;
input wr_clk;
input out;
input wr_rst_busy;
input ram_full_fb_i_reg;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [8:0]Q;
wire [3:0]S;
wire [9:0]diff_pntr;
wire [3:0]\gic0.gc0.count_d1_reg[7] ;
wire [1:0]\gic0.gc0.count_d1_reg[9] ;
wire \gpf1.prog_full_i_i_1_n_0 ;
wire \gpf1.prog_full_i_i_2_n_0 ;
wire \gpf1.prog_full_i_i_3_n_0 ;
wire out;
wire plusOp_carry__0_n_0;
wire plusOp_carry__0_n_1;
wire plusOp_carry__0_n_2;
wire plusOp_carry__0_n_3;
wire plusOp_carry__0_n_4;
wire plusOp_carry__0_n_5;
wire plusOp_carry__0_n_6;
wire plusOp_carry__0_n_7;
wire plusOp_carry__1_n_3;
wire plusOp_carry__1_n_6;
wire plusOp_carry__1_n_7;
wire plusOp_carry_n_0;
wire plusOp_carry_n_1;
wire plusOp_carry_n_2;
wire plusOp_carry_n_3;
wire plusOp_carry_n_4;
wire plusOp_carry_n_5;
wire plusOp_carry_n_6;
wire plusOp_carry_n_7;
wire prog_full;
wire ram_full_fb_i_reg;
wire wr_clk;
wire wr_rst_busy;
wire [3:1]NLW_plusOp_carry__1_CO_UNCONNECTED;
wire [3:2]NLW_plusOp_carry__1_O_UNCONNECTED;
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[10]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(plusOp_carry__1_n_6),
.Q(diff_pntr[9]));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[1]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(plusOp_carry_n_7),
.Q(diff_pntr[0]));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[2]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(plusOp_carry_n_6),
.Q(diff_pntr[1]));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[3]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(plusOp_carry_n_5),
.Q(diff_pntr[2]));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[4]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(plusOp_carry_n_4),
.Q(diff_pntr[3]));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[5]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(plusOp_carry__0_n_7),
.Q(diff_pntr[4]));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[6]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(plusOp_carry__0_n_6),
.Q(diff_pntr[5]));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[7]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(plusOp_carry__0_n_5),
.Q(diff_pntr[6]));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[8]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(plusOp_carry__0_n_4),
.Q(diff_pntr[7]));
FDCE #(
.INIT(1'b0))
\gdiff.diff_pntr_pad_reg[9]
(.C(wr_clk),
.CE(1'b1),
.CLR(AR),
.D(plusOp_carry__1_n_7),
.Q(diff_pntr[8]));
LUT6 #(
.INIT(64'h00FF004F0000004F))
\gpf1.prog_full_i_i_1
(.I0(\gpf1.prog_full_i_i_2_n_0 ),
.I1(diff_pntr[6]),
.I2(\gpf1.prog_full_i_i_3_n_0 ),
.I3(wr_rst_busy),
.I4(ram_full_fb_i_reg),
.I5(prog_full),
.O(\gpf1.prog_full_i_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\gpf1.prog_full_i_i_2
(.I0(diff_pntr[2]),
.I1(diff_pntr[3]),
.I2(diff_pntr[0]),
.I3(diff_pntr[1]),
.I4(diff_pntr[5]),
.I5(diff_pntr[4]),
.O(\gpf1.prog_full_i_i_2_n_0 ));
LUT3 #(
.INIT(8'h01))
\gpf1.prog_full_i_i_3
(.I0(diff_pntr[9]),
.I1(diff_pntr[8]),
.I2(diff_pntr[7]),
.O(\gpf1.prog_full_i_i_3_n_0 ));
FDPE #(
.INIT(1'b1))
\gpf1.prog_full_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(\gpf1.prog_full_i_i_1_n_0 ),
.PRE(out),
.Q(prog_full));
CARRY4 plusOp_carry
(.CI(1'b0),
.CO({plusOp_carry_n_0,plusOp_carry_n_1,plusOp_carry_n_2,plusOp_carry_n_3}),
.CYINIT(E),
.DI(Q[3:0]),
.O({plusOp_carry_n_4,plusOp_carry_n_5,plusOp_carry_n_6,plusOp_carry_n_7}),
.S(S));
CARRY4 plusOp_carry__0
(.CI(plusOp_carry_n_0),
.CO({plusOp_carry__0_n_0,plusOp_carry__0_n_1,plusOp_carry__0_n_2,plusOp_carry__0_n_3}),
.CYINIT(1'b0),
.DI(Q[7:4]),
.O({plusOp_carry__0_n_4,plusOp_carry__0_n_5,plusOp_carry__0_n_6,plusOp_carry__0_n_7}),
.S(\gic0.gc0.count_d1_reg[7] ));
CARRY4 plusOp_carry__1
(.CI(plusOp_carry__0_n_0),
.CO({NLW_plusOp_carry__1_CO_UNCONNECTED[3:1],plusOp_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,Q[8]}),
.O({NLW_plusOp_carry__1_O_UNCONNECTED[3:2],plusOp_carry__1_n_6,plusOp_carry__1_n_7}),
.S({1'b0,1'b0,\gic0.gc0.count_d1_reg[9] }));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_as
(full,
out,
E,
\gnxpm_cdc.rd_pntr_bin_reg[6] ,
v1_reg_0,
v1_reg,
wr_clk,
\grstd1.grst_full.grst_f.rst_d2_reg ,
wr_en,
wr_rst_busy);
output full;
output out;
output [0:0]E;
input [3:0]\gnxpm_cdc.rd_pntr_bin_reg[6] ;
input [0:0]v1_reg_0;
input [4:0]v1_reg;
input wr_clk;
input \grstd1.grst_full.grst_f.rst_d2_reg ;
input wr_en;
input wr_rst_busy;
wire [0:0]E;
wire c2_n_0;
wire comp1;
wire [3:0]\gnxpm_cdc.rd_pntr_bin_reg[6] ;
wire \grstd1.grst_full.grst_f.rst_d2_reg ;
(* DONT_TOUCH *) wire ram_full_fb_i;
(* DONT_TOUCH *) wire ram_full_i;
wire [4:0]v1_reg;
wire [0:0]v1_reg_0;
wire wr_clk;
wire wr_en;
wire wr_rst_busy;
assign full = ram_full_i;
assign out = ram_full_fb_i;
LUT2 #(
.INIT(4'h2))
\DEVICE_7SERIES.NO_BMM_INFO.SDP.SIMPLE_PRIM36.ram_i_1
(.I0(wr_en),
.I1(ram_full_fb_i),
.O(E));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare c1
(.comp1(comp1),
.\gnxpm_cdc.rd_pntr_bin_reg[6] (\gnxpm_cdc.rd_pntr_bin_reg[6] ),
.v1_reg_0(v1_reg_0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_compare_3 c2
(.comp1(comp1),
.out(ram_full_fb_i),
.ram_full_fb_i_reg(c2_n_0),
.v1_reg(v1_reg),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(c2_n_0),
.PRE(\grstd1.grst_full.grst_f.rst_d2_reg ),
.Q(ram_full_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(wr_clk),
.CE(1'b1),
.D(c2_n_0),
.PRE(\grstd1.grst_full.grst_f.rst_d2_reg ),
.Q(ram_full_i));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Copyright (c) 2015-2017 The Ultiparc Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* System top level
*/
`include "config.vh"
`include "common.vh"
`include "ocp_const.vh"
/*
* System top
*/
module sys_top (
clk,
nrst
);
input wire clk;
input wire nrst;
/** Local interconnect **/
/* CPU I-Bus */
wire [`ADDR_WIDTH-1:0] C_IAddr;
wire C_IRdC;
wire [`DATA_WIDTH-1:0] C_IData;
wire C_IRdy;
wire C_IErr;
/* CPU D-Bus */
wire [`ADDR_WIDTH-1:0] C_DAddr;
wire C_DCmd;
wire C_DRnW;
wire [`BEN_WIDTH-1:0] C_DBen;
wire [`DATA_WIDTH-1:0] C_DDataM;
wire [`DATA_WIDTH-1:0] C_DDataS;
wire C_DRdy;
wire C_DErr;
/* OCP I-Port */
wire [`ADDR_WIDTH-1:0] I_MAddr;
wire [2:0] I_MCmd;
wire [`DATA_WIDTH-1:0] I_MData;
wire [`BEN_WIDTH-1:0] I_MByteEn;
wire I_SCmdAccept;
wire [`DATA_WIDTH-1:0] I_SData;
wire [1:0] I_SResp;
/* OCP D-Port */
wire [`ADDR_WIDTH-1:0] D_MAddr;
wire [2:0] D_MCmd;
wire [`DATA_WIDTH-1:0] D_MData;
wire [`BEN_WIDTH-1:0] D_MByteEn;
wire D_SCmdAccept;
wire [`DATA_WIDTH-1:0] D_SData;
wire [1:0] D_SResp;
/* Slave ports */
wire [`ADDR_WIDTH-1:0] P_MAddr[0:4];
wire [2:0] P_MCmd[0:4];
wire [`DATA_WIDTH-1:0] P_MData[0:4];
wire [`BEN_WIDTH-1:0] P_MByteEn[0:4];
wire P_SCmdAccept[0:4];
wire [`DATA_WIDTH-1:0] P_SData[0:4];
wire [1:0] P_SResp[0:4];
/* CPU interrupt */
wire intr;
/* Timer interrupt */
wire timer_intr;
/* IBus-to-OCP */
`ifdef CONFIG_FABRIC2
ibus2ocp2 ibus_ocp(
.clk(clk),
.nrst(nrst),
`else
ibus2ocp ibus_ocp(
`endif
.i_IAddr(C_IAddr),
.i_IRdC(C_IRdC),
.o_IData(C_IData),
.o_IRdy(C_IRdy),
.o_IErr(C_IErr),
.o_MAddr(I_MAddr),
.o_MCmd(I_MCmd),
.o_MData(I_MData),
.o_MByteEn(I_MByteEn),
.i_SCmdAccept(I_SCmdAccept),
.i_SData(I_SData),
.i_SResp(I_SResp)
);
/* DBus-to-OCP */
`ifdef CONFIG_FABRIC2
dbus2ocp2 dbus_ocp(
.clk(clk),
.nrst(nrst),
`else
dbus2ocp dbus_ocp(
`endif
.i_DAddr(C_DAddr),
.i_DCmd(C_DCmd),
.i_DRnW(C_DRnW),
.i_DBen(C_DBen),
.i_DData(C_DDataM),
.o_DData(C_DDataS),
.o_DRdy(C_DRdy),
.o_DErr(C_DErr),
.o_MAddr(D_MAddr),
.o_MCmd(D_MCmd),
.o_MData(D_MData),
.o_MByteEn(D_MByteEn),
.i_SCmdAccept(D_SCmdAccept),
.i_SData(D_SData),
.i_SResp(D_SResp)
);
/* CPU */
uparc_cpu_top cpu(
.clk(clk),
.nrst(nrst),
.i_intr(intr),
.o_IAddr(C_IAddr),
.o_IRdC(C_IRdC),
.i_IData(C_IData),
.i_IRdy(C_IRdy),
.i_IErr(C_IErr),
.o_DAddr(C_DAddr),
.o_DCmd(C_DCmd),
.o_DRnW(C_DRnW),
.o_DBen(C_DBen),
.o_DData(C_DDataM),
.i_DData(C_DDataS),
.i_DRdy(C_DRdy),
.i_DErr(C_DErr)
);
/* Memory */
memory mem(
.clk(clk),
.nrst(nrst),
.i_MAddr(P_MAddr[0]),
.i_MCmd(P_MCmd[0]),
.i_MData(P_MData[0]),
.i_MByteEn(P_MByteEn[0]),
.o_SCmdAccept(P_SCmdAccept[0]),
.o_SData(P_SData[0]),
.o_SResp(P_SResp[0])
);
/* micro UART */
micro_uart uart(
.clk(clk),
.nrst(nrst),
.i_MAddr(P_MAddr[1]),
.i_MCmd(P_MCmd[1]),
.i_MData(P_MData[1]),
.i_MByteEn(P_MByteEn[1]),
.o_SCmdAccept(P_SCmdAccept[1]),
.o_SData(P_SData[1]),
.o_SResp(P_SResp[1])
);
/* Control device */
sim_control sim_ctl(
.clk(clk),
.nrst(nrst),
.i_MAddr(P_MAddr[2]),
.i_MCmd(P_MCmd[2]),
.i_MData(P_MData[2]),
.i_MByteEn(P_MByteEn[2]),
.o_SCmdAccept(P_SCmdAccept[2]),
.o_SData(P_SData[2]),
.o_SResp(P_SResp[2])
);
/* Interrupt controller */
intr_controller intr_ctrl(
.clk(clk),
.nrst(nrst),
.i_MAddr(P_MAddr[3]),
.i_MCmd(P_MCmd[3]),
.i_MData(P_MData[3]),
.i_MByteEn(P_MByteEn[3]),
.o_SCmdAccept(P_SCmdAccept[3]),
.o_SData(P_SData[3]),
.o_SResp(P_SResp[3]),
.o_intr(intr),
.i_intr_vec({31'b0, timer_intr})
);
/* Interval timer */
interval_timer timer(
.clk(clk),
.nrst(nrst),
.i_MAddr(P_MAddr[4]),
.i_MCmd(P_MCmd[4]),
.i_MData(P_MData[4]),
.i_MByteEn(P_MByteEn[4]),
.o_SCmdAccept(P_SCmdAccept[4]),
.o_SData(P_SData[4]),
.o_SResp(P_SResp[4]),
.o_intr(timer_intr)
);
/* Fabric */
`ifdef CONFIG_FABRIC2
fabric2 fab(
`else
fabric fab(
`endif
.clk(clk),
.nrst(nrst),
/* OCP interface: instructions (master) */
.i_I_MAddr(I_MAddr), .i_I_MCmd(I_MCmd),
.i_I_MData(I_MData), .i_I_MByteEn(I_MByteEn),
.o_I_SCmdAccept(I_SCmdAccept), .o_I_SData(I_SData),
.o_I_SResp(I_SResp),
/* OCP interface: data (master) */
.i_D_MAddr(D_MAddr), .i_D_MCmd(D_MCmd),
.i_D_MData(D_MData), .i_D_MByteEn(D_MByteEn),
.o_D_SCmdAccept(D_SCmdAccept), .o_D_SData(D_SData),
.o_D_SResp(D_SResp),
/* OCP interface: Port 0 (slave) */
.o_P0_MAddr(P_MAddr[0]), .o_P0_MCmd(P_MCmd[0]),
.o_P0_MData(P_MData[0]), .o_P0_MByteEn(P_MByteEn[0]),
.i_P0_SCmdAccept(P_SCmdAccept[0]), .i_P0_SData(P_SData[0]),
.i_P0_SResp(P_SResp[0]),
/* OCP interface: Port 1 (slave) */
.o_P1_MAddr(P_MAddr[1]), .o_P1_MCmd(P_MCmd[1]),
.o_P1_MData(P_MData[1]), .o_P1_MByteEn(P_MByteEn[1]),
.i_P1_SCmdAccept(P_SCmdAccept[1]), .i_P1_SData(P_SData[1]),
.i_P1_SResp(P_SResp[1]),
/* OCP interface: Port 2 (slave) */
.o_P2_MAddr(P_MAddr[2]), .o_P2_MCmd(P_MCmd[2]),
.o_P2_MData(P_MData[2]), .o_P2_MByteEn(P_MByteEn[2]),
.i_P2_SCmdAccept(P_SCmdAccept[2]), .i_P2_SData(P_SData[2]),
.i_P2_SResp(P_SResp[2]),
/* OCP interface: Port 3 (slave) */
.o_P3_MAddr(P_MAddr[3]), .o_P3_MCmd(P_MCmd[3]),
.o_P3_MData(P_MData[3]), .o_P3_MByteEn(P_MByteEn[3]),
.i_P3_SCmdAccept(P_SCmdAccept[3]), .i_P3_SData(P_SData[3]),
.i_P3_SResp(P_SResp[3]),
/* OCP interface: Port 4 (slave) */
.o_P4_MAddr(P_MAddr[4]), .o_P4_MCmd(P_MCmd[4]),
.o_P4_MData(P_MData[4]), .o_P4_MByteEn(P_MByteEn[4]),
.i_P4_SCmdAccept(P_SCmdAccept[4]), .i_P4_SData(P_SData[4]),
.i_P4_SResp(P_SResp[4])
);
endmodule /* sys_top */
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:11:24 02/22/2015
// Design Name:
// Module Name: AllignAdder
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module AllignAdderProcess(
input [31:0] z_postSpecial,
input [3:0] Opcode_Special,
input idle_Special,
input [35:0] cout_Special,
input [35:0] zout_Special,
input [31:0] sout_Special,
input [7:0] difference_Special,
input [7:0] InsTagSpecial,
input clock,
output reg idle_Allign,
output reg [35:0] cout_Allign,
output reg [35:0] zout_Allign,
output reg [31:0] sout_Allign,
output reg [3:0] Opcode_Allign,
output reg [31:0] z_postAllign,
output reg [7:0] InsTagAllign
);
parameter no_idle = 1'b0,
put_idle = 1'b1;
wire z_sign;
wire [7:0] z_exponent;
wire [26:0] z_mantissa;
wire c_sign;
wire [7:0] c_exponent;
wire [26:0] c_mantissa;
assign z_sign = zout_Special[35];
assign z_exponent = zout_Special[34:27] - 127;
assign z_mantissa = {zout_Special[26:0]};
assign c_sign = cout_Special[35];
assign c_exponent = cout_Special[34:27] - 127;
assign c_mantissa = {cout_Special[26:0]};
parameter sin_cos = 4'd0,
sinh_cosh = 4'd1,
arctan = 4'd2,
arctanh = 4'd3,
exp = 4'd4,
sqr_root = 4'd5, // Pre processed input is given 4'd11
// This requires pre processing. x = (a+1)/2 and y = (a-1)/2
division = 4'd6,
tan = 4'd7, // This is iterative. sin_cos followed by division.
tanh = 4'd8, // This is iterative. sinh_cosh followed by division.
nat_log = 4'd9, // This requires pre processing. x = (a+1) and y = (a-1)
hypotenuse = 4'd10,
PreProcess = 4'd11;
always @ (posedge clock)
begin
InsTagAllign <= InsTagSpecial;
Opcode_Allign <= Opcode_Special;
z_postAllign <= z_postSpecial;
//if(Opcode_Special == PreProcess) begin
idle_Allign <= idle_Special;
sout_Allign <= sout_Special;
if (idle_Special != put_idle) begin
if ($signed(c_exponent) > $signed(z_exponent)) begin
zout_Allign[35] <= zout_Special[35];
zout_Allign[34:27] <= z_exponent + difference_Special + 127;
zout_Allign[26:0] <= z_mantissa >> difference_Special;
zout_Allign[0] <= z_mantissa[0] | z_mantissa[1];
cout_Allign <= cout_Special;
end else if ($signed(c_exponent) <= $signed(z_exponent)) begin
cout_Allign[35] <= cout_Special[35];
cout_Allign[34:27] <= c_exponent + difference_Special + 127;
cout_Allign[26:0] <= c_mantissa >> difference_Special;
cout_Allign[0] <= c_mantissa[0] | c_mantissa[1];
zout_Allign <= zout_Special;
end
end
else begin
zout_Allign <= zout_Special;
cout_Allign <= cout_Special;
end
//end
end
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_NANO_SOC_QSYS_nios2_qsys_jtag_debug_module_sysclk (
// inputs:
clk,
ir_in,
sr,
vs_udr,
vs_uir,
// outputs:
jdo,
take_action_break_a,
take_action_break_b,
take_action_break_c,
take_action_ocimem_a,
take_action_ocimem_b,
take_action_tracectrl,
take_action_tracemem_a,
take_action_tracemem_b,
take_no_action_break_a,
take_no_action_break_b,
take_no_action_break_c,
take_no_action_ocimem_a,
take_no_action_tracemem_a
)
;
output [ 37: 0] jdo;
output take_action_break_a;
output take_action_break_b;
output take_action_break_c;
output take_action_ocimem_a;
output take_action_ocimem_b;
output take_action_tracectrl;
output take_action_tracemem_a;
output take_action_tracemem_b;
output take_no_action_break_a;
output take_no_action_break_b;
output take_no_action_break_c;
output take_no_action_ocimem_a;
output take_no_action_tracemem_a;
input clk;
input [ 1: 0] ir_in;
input [ 37: 0] sr;
input vs_udr;
input vs_uir;
reg enable_action_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg [ 1: 0] ir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg [ 37: 0] jdo /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,R101\"" */;
reg jxuir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_udr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
reg sync2_uir /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
wire sync_udr;
wire sync_uir;
wire take_action_break_a;
wire take_action_break_b;
wire take_action_break_c;
wire take_action_ocimem_a;
wire take_action_ocimem_b;
wire take_action_tracectrl;
wire take_action_tracemem_a;
wire take_action_tracemem_b;
wire take_no_action_break_a;
wire take_no_action_break_b;
wire take_no_action_break_c;
wire take_no_action_ocimem_a;
wire take_no_action_tracemem_a;
wire unxunused_resetxx3;
wire unxunused_resetxx4;
reg update_jdo_strobe /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103\"" */;
assign unxunused_resetxx3 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer3
(
.clk (clk),
.din (vs_udr),
.dout (sync_udr),
.reset_n (unxunused_resetxx3)
);
defparam the_altera_std_synchronizer3.depth = 2;
assign unxunused_resetxx4 = 1'b1;
altera_std_synchronizer the_altera_std_synchronizer4
(
.clk (clk),
.din (vs_uir),
.dout (sync_uir),
.reset_n (unxunused_resetxx4)
);
defparam the_altera_std_synchronizer4.depth = 2;
always @(posedge clk)
begin
sync2_udr <= sync_udr;
update_jdo_strobe <= sync_udr & ~sync2_udr;
enable_action_strobe <= update_jdo_strobe;
sync2_uir <= sync_uir;
jxuir <= sync_uir & ~sync2_uir;
end
assign take_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && jdo[34];
assign take_no_action_ocimem_a = enable_action_strobe && (ir == 2'b00) &&
~jdo[35] && ~jdo[34];
assign take_action_ocimem_b = enable_action_strobe && (ir == 2'b00) &&
jdo[35];
assign take_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
jdo[36];
assign take_no_action_tracemem_a = enable_action_strobe && (ir == 2'b01) &&
~jdo[37] &&
~jdo[36];
assign take_action_tracemem_b = enable_action_strobe && (ir == 2'b01) &&
jdo[37];
assign take_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
jdo[37];
assign take_no_action_break_a = enable_action_strobe && (ir == 2'b10) &&
~jdo[36] &&
~jdo[37];
assign take_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
jdo[37];
assign take_no_action_break_b = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && ~jdo[35] &&
~jdo[37];
assign take_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
jdo[37];
assign take_no_action_break_c = enable_action_strobe && (ir == 2'b10) &&
jdo[36] && jdo[35] &&
~jdo[37];
assign take_action_tracectrl = enable_action_strobe && (ir == 2'b11) &&
jdo[15];
always @(posedge clk)
begin
if (jxuir)
ir <= ir_in;
if (update_jdo_strobe)
jdo <= sr;
end
endmodule
|
(*** An approach to representing Models with inductive types ***)
Require Import List.
Import ListNotations.
Require Import String.
(* Require Export Coq.Logic.Eqdep. *)
Add LoadPath "." as Specware.
Require Import Specware.Util.
(* Define the type of fields in one place, so we can change it later *)
Definition Field : Set := string.
Definition Field_dec : forall (f1 f2 : Field), {f1=f2} + {f1<>f2} := string_dec.
(**
** The basic structures: signatures, models, and specs
**)
(* A Model is an element of the record type denoted by a Sig *)
Inductive Model : Type :=
| Model_Nil : Model
| Model_Cons (fld:Field) A (a : A) (M:Model) : Model
.
(* A Spec is a partial Model of a Sig; README: Specs are indexed with
their fields so that the fields they contain are known: i.e., even
an inconsistent Spec has a fixed list of fields *)
Inductive Spec : forall {flds : list Field}, Type :=
| Spec_Nil : Spec (flds:=nil)
| Spec_ConsNone f A {flds} :
(forall (a:A), Spec (flds:=flds)) -> Spec (flds:= f :: flds)
| Spec_ConsSome f A (a : A) {flds} :
Spec (flds:=flds) ->
Spec (flds:= f :: flds)
.
(* helper function for printing purposes *)
Definition get_fields {flds} (spec : Spec (flds:=flds)) := flds.
(**
** Notions of elements of structures
**)
(* Proof that field f is associated with type A in spec *)
(* FIXME: the types (and elements!) depend on earlier elements! *)
(*
Inductive SpecElem (f : Field) :
forall A, option A -> forall {flds}, Spec (flds:=flds) -> Prop :=
| SpecElem_BaseNone flds (spec : A -> Spec (flds:=flds)) :
SpecElem f A None (Spec_ConsNone f A spec)
| SpecElem_BaseSome a flds (spec : Spec (flds:=flds)) :
SpecElem f A (Some a) (Spec_ConsSome f A a spec)
| SpecElem_ConsNone A a f' A' flds (spec : A' -> Spec (flds:=flds)) :
(forall a', SpecElem f A a (spec a')) ->
SpecElem f A a (Spec_ConsNone f' A' spec)
| SpecElem_ConsSome a f' A' a' flds (spec : Spec (flds:=flds)) :
SpecElem f A a spec ->
SpecElem f A a (Spec_ConsSome f' A' a' spec)
.
*)
(* Get the fields of a Model *)
Fixpoint modelFields (M : Model) : list Field :=
match M with
| Model_Nil => []
| Model_Cons fld _ _ M' => fld :: modelFields M'
end.
(* Proof that field f is associated with element a of type A in model *)
Inductive ModelElem (fld : Field) A (a:A) : Model -> Prop :=
| ModelElem_Base (model : Model) :
ModelElem fld A a (Model_Cons fld A a model)
| ModelElem_Cons fld' A' a' (model : Model) :
ModelElem fld A a model ->
ModelElem fld A a (Model_Cons fld' A' a' model)
.
(* Model_Nil has no ModelElems *)
Lemma not_ModelElem_nil (fld : Field) A (a:A) :
ModelElem fld A a Model_Nil -> False.
assert (forall model,
ModelElem fld A a model -> model = Model_Nil -> False).
intros model melem e; induction melem; discriminate.
intro melem; apply (H _ melem); reflexivity.
Qed.
(* Projecting an element out of a Model *)
(* FIXME: update or remove
Fixpoint modelProj (model : Model) :
forall f, In f (modelFields model) -> { A : Type & A } :=
match model in Model (flds:=flds)
return forall f, In f flds -> { A : Type & A }
with
| Model_Nil => fun f in_nil => False_rect _ in_nil
| Model_Cons f' A a _ model =>
fun f in_pf =>
match Field_dec f' f with
| left _ => existT id A a
| right neq =>
modelProj model f (or_proj_r _ _ neq in_pf)
end
end.
(* Correctness of modelProj: always returns a ModelElem *)
Lemma modelProj_correct flds (model : Model (flds:=flds)) f in_pf :
ModelElem f (projT1 (modelProj model f in_pf))
(projT2 (modelProj model f in_pf))
model.
revert f in_pf; induction model; intros.
elimtype False; apply in_pf.
unfold modelProj; fold (modelProj (flds:=flds)).
destruct (Field_dec f f0).
rewrite <- e; apply ModelElem_Base.
apply ModelElem_Cons.
apply IHmodel.
Qed.
*)
(**
** Defining the notion of models of specs
**)
Fixpoint IsModel (model : Model) {flds} (spec : Spec (flds:=flds)) {struct spec} : Prop :=
match spec in Spec (flds:=flds) with
| Spec_Nil => True
| Spec_ConsNone f A _ specF =>
exists a, ModelElem f A a model /\ IsModel model (specF a)
| Spec_ConsSome f A a _ spec' =>
ModelElem f A a model /\ IsModel model spec'
end.
Definition IsModel_Nil model : IsModel model Spec_Nil := I.
Definition IsModel_ConsNone model f A a {flds} (spec : A -> Spec (flds:=flds))
(melem : ModelElem f A a model) (ism : IsModel model (spec a)) :
IsModel model (Spec_ConsNone f A spec).
exists a; split; assumption.
Qed.
Definition IsModel_ConsSome model f A a {flds} (spec : Spec (flds:=flds))
(melem : ModelElem f A a model) (ism : IsModel model spec) :
IsModel model (Spec_ConsSome f A a spec).
split; assumption.
Qed.
(* A model of a Spec contains an element for each field in the spec *)
(* README: old, inductive version
Inductive IsModel (model : Model) :
forall {flds}, Spec (flds:=flds) -> Prop :=
| IsModel_Nil : IsModel model Spec_Nil
| IsModel_ConsNone f A a flds (spec : A -> Spec (flds:=flds)) :
ModelElem f A a model ->
IsModel model (spec a) ->
IsModel model (Spec_ConsNone f A spec)
| IsModel_ConsSome f A a flds (spec : Spec (flds:=flds)) :
ModelElem f A a model ->
IsModel model spec ->
IsModel model (Spec_ConsSome f A a spec)
.
*)
Lemma IsModel_nil_spec {flds} (spec : Spec (flds:=flds)) :
IsModel Model_Nil spec -> eq_dep _ (@Spec) _ spec _ Spec_Nil.
induction spec; intro ism.
reflexivity.
destruct ism as [ a sig ]; destruct sig as [ melem ism ];
elimtype False; apply (not_ModelElem_nil _ _ _ melem).
destruct ism as [ melem ism ];
elimtype False; apply (not_ModelElem_nil _ _ _ melem).
Qed.
(*
Lemma IsModel_ConsNone_inversion model {flds} f A
(spec : A -> Spec (flds:=flds)) :
IsModel model (Spec_ConsNone f A spec) ->
exists a, ModelElem f A a model /\ IsModel model (spec a).
intro ism; inversion ism.
exists a; split; [ assumption | ].
assert (spec1 = spec).
apply (inj_pair2_flds (inj_pair2_flds H3)).
*)
(* FIXME: write prove_ismodel tactic *)
(*
Lemma ModelElem_to_SpecElem {flds_m} (model : Model (flds:=flds_m))
{flds_s} (spec : Spec (flds:=flds_s)) f A a :
ModelElem f A a
*)
(**
** Oooh, supermodels!
**)
Definition SuperModel (model1 : Model) (model2 : Model) : Prop :=
forall f A a,
ModelElem f A a model2 -> ModelElem f A a model1.
Lemma SuperModel_cons_l f A a (model1 : Model) (model2 : Model) :
SuperModel model1 model2 ->
SuperModel (Model_Cons f A a model1) model2.
intros super12 f' A' a' melem2;
apply ModelElem_Cons; apply (super12 f' A' a' melem2); assumption.
Qed.
Lemma SuperModel_id (model : Model) : SuperModel model model.
intros f A a ism; assumption.
Qed.
Lemma SuperModel_trans model1 model2 model3 :
SuperModel model1 model2 -> SuperModel model2 model3 ->
SuperModel model1 model3.
intros super12 super23 f A a melem3;
apply (super12 f A a (super23 f A a melem3)).
Qed.
(**
** Field maps: finite functions on Fs
**)
(* A FieldMap is represented as a list of pairs *)
Definition FieldMap := list (Field * Field).
(* The identity FieldMap *)
Definition idFM : FieldMap := [].
(* Apply a FieldMap to a F *)
Fixpoint applyFM (m : FieldMap) (str : Field) : Field :=
match m with
| [] => str
| (str_from, str_to) :: m' =>
if Field_dec str str_from then str_to else
applyFM m' str
end.
(* Applying idFM is the identity *)
Lemma idFM_is_id (str : Field) : applyFM idFM str = str.
reflexivity.
Qed.
(* compose two FieldMaps, applying m1 and then m2 *)
Fixpoint composeFM (m1 m2 : FieldMap) : FieldMap :=
match m1 with
| [] => m2
| (str_from, str_to) :: m1' =>
(str_from, applyFM m2 str_to) :: composeFM m1' m2
end.
(* composition works as expected *)
Lemma FieldMap_compose m1 m2 str :
applyFM (composeFM m1 m2) str = applyFM m2 (applyFM m1 str).
induction m1.
reflexivity.
destruct a as [ str_from str_to ]; unfold composeFM; fold composeFM.
unfold applyFM; fold applyFM.
destruct (Field_dec str str_from).
reflexivity.
apply IHm1.
Qed.
(* Return the list of Fs that map to an output F *)
Fixpoint semiInvertFM (m : FieldMap) str : list Field :=
match m with
| [] => [str]
| (str_from, str_to) :: m' =>
if Field_dec str str_to then str_from :: semiInvertFM m' str
else remove Field_dec str_from (semiInvertFM m' str)
end.
(* semiInvertFM returns only Fs that map back to str *)
Lemma semiInvertFM_sound m str str' :
In str' (semiInvertFM m str) -> applyFM m str' = str.
induction m.
intro in_pf; destruct in_pf;
[ rewrite H; reflexivity | destruct H ].
destruct a as [ str_from str_to ]; unfold applyFM; fold applyFM.
unfold semiInvertFM; fold semiInvertFM.
destruct (Field_dec str str_to); intro in_pf;
destruct (Field_dec str' str_from).
rewrite e; reflexivity.
apply IHm; destruct in_pf;
[ elimtype False; apply n; rewrite H; reflexivity | assumption ].
rewrite e in in_pf; elimtype False; apply (remove_In _ _ _ in_pf).
apply IHm; apply (In_remove _ _ _ _ in_pf).
Qed.
(* semiInvertFM returns all Fs that map back to str *)
Lemma semiInvertFM_complete m str str' :
applyFM m str' = str -> In str' (semiInvertFM m str).
induction m; unfold applyFM; fold applyFM.
intro e; left; symmetry; assumption.
destruct a as [ str_from str_to ]; unfold semiInvertFM; fold semiInvertFM.
destruct (Field_dec str' str_from); intro eApp.
rewrite eApp; rewrite F_dec_true; left; symmetry; assumption.
destruct (Field_dec str str_to).
right; apply IHm; assumption.
apply remove_not_eq; [ assumption | apply IHm; assumption ].
Qed.
(* str is always in semiInvertFM m (applyFM m str) *)
Lemma in_semiInvert_apply m str : In str (semiInvertFM m (applyFM m str)).
apply semiInvertFM_complete; reflexivity.
Qed.
(**
** Mapping functions over structures
**)
Fixpoint model_map (m : FieldMap) (model : Model) : Model :=
match model with
| Model_Nil => Model_Nil
| Model_Cons f A a model =>
Model_Cons (applyFM m f) A a (model_map m model)
end.
Fixpoint spec_map (m : FieldMap) {flds} (spec : Spec (flds:=flds)) :
Spec (flds:=map (applyFM m) flds) :=
match spec in Spec (flds:=flds) return Spec (flds:=map (applyFM m) flds) with
| Spec_Nil => Spec_Nil
| Spec_ConsNone f A flds spec =>
Spec_ConsNone (applyFM m f) A (fun a => spec_map m (spec a))
| Spec_ConsSome f A a flds spec =>
Spec_ConsSome (applyFM m f) A a (spec_map m spec)
end.
(* mapping id over a model is the identity itself *)
Lemma model_map_id model : model_map idFM model = model.
induction model.
reflexivity.
unfold model_map; fold model_map. f_equal. assumption.
Qed.
(* mapping id over a spec is the identity itself *)
Lemma spec_map_id {flds} (spec : Spec (flds:=flds)) :
eq_dep _ (@Spec) _ (spec_map idFM spec) _ spec.
induction spec.
apply eq_dep_intro.
apply (eq_dep_ctx _ (fun fs => A -> @Spec fs)
(map id flds) flds (fun a => spec_map idFM (s a)) s
_ (fun fs => f :: fs)
_ (fun _ spec => Spec_ConsNone f A spec)).
apply (eq_dep_flds_fun _ Field_dec); [ apply map_id | assumption ].
apply (eq_dep_ctx _ (@Spec)
_ _ _ _ _ (fun fs => f :: fs) _ (fun _ => Spec_ConsSome f A a)
IHspec).
Qed.
(* if the result of spec_map is Spec_Nil, then the input is as well *)
Lemma spec_map_to_Nil m {flds} (spec : Spec (flds:=flds)) :
eq_dep _ (@Spec) _ (spec_map m spec) _ Spec_Nil ->
eq_dep _ (@Spec) _ spec _ Spec_Nil.
induction spec; unfold spec_map; fold spec_map; intro e;
[ reflexivity | | ];
(assert (map (applyFM m) (f :: flds) = []);
[ apply (eq_dep_fst e) | discriminate ]).
Qed.
(* if the result of spec_map is a Spec_ConsNone, then the input is as well *)
(* FIXME: prove or remove
Lemma spec_map_to_ConsNone m {flds} (spec : Spec (flds:=flds))
f' A {flds'} (spec' : A -> Spec (flds:=flds')) :
eq_dep _ (@Spec) _ (spec_map m spec) _ (Spec_ConsNone f' A spec') ->
{ f'':_ & { flds'':_ & { spec'' : A -> Spec (flds:=flds'') |
eq_dep _ (@Spec) _ spec
_ (Spec_ConsNone f'' A spec'') }}}.
induction spec; unfold spec_map; fold spec_map; intro e.
assert ([] = f' :: flds'); [ apply (eq_dep_fst e) | discriminate ].
assert (map (applyFM m) (f :: flds) = f' :: flds') as H;
[ apply (eq_dep_fst e) | ].
injection H; intros e_flds' e_f'.
revert s spec' X e; rewrite <- e_f'; rewrite <- e_flds'; intros.
assert (Spec_ConsNone (applyFM m f) A0 (fun a : A0 => spec_map m (s a))
= Spec_ConsNone (applyFM m f) A spec');
apply (eq_dep_eq_flds _ e).
assert (A0 = A) as H;
[
| revert s X e; rewrite H; intros;
exists f; exists flds; exists s; reflexivity ].
[ reflexivity | | ];
(assert (map (applyFM m) (f :: flds) = []);
[ apply (eq_dep_fst e) | discriminate ]).
Qed.
*)
(* composing two spec_maps together *)
Lemma spec_map_comp {flds} (spec : Spec (flds:=flds)) m1 m2 :
eq_dep _ (@Spec) _ (spec_map m2 (spec_map m1 spec)) _
(spec_map (composeFM m1 m2) spec).
induction spec.
apply eq_dep_intro.
unfold map; fold (map (applyFM m1)); fold (map (applyFM m2));
fold (map (applyFM (composeFM m1 m2))).
unfold spec_map; fold spec_map; rewrite FieldMap_compose.
apply (eq_dep_ctx _ (fun fs => A -> @Spec fs)
(map (applyFM m2) (map (applyFM m1) flds))
(map (applyFM (composeFM m1 m2)) flds)
(fun a => spec_map m2 (spec_map m1 (s a)))
(fun a => spec_map (composeFM m1 m2) (s a))
_ (fun fs => applyFM m2 (applyFM m1 f) :: fs)
_ (fun _ spec => Spec_ConsNone (applyFM m2 (applyFM m1 f)) A spec)
).
apply (eq_dep_flds_fun _ Field_dec);
[ rewrite map_map; apply map_ext;
intro fld; symmetry; apply FieldMap_compose
| assumption ].
unfold map; fold (map (applyFM m1)); fold (map (applyFM m2));
fold (map (applyFM (composeFM m1 m2))).
unfold spec_map; fold spec_map; rewrite FieldMap_compose.
apply (eq_dep_ctx _ (@Spec)
_ _ _ _ _
(fun fs => _ :: fs) _ (fun _ => Spec_ConsSome _ A a)
IHspec).
Qed.
(* FIXME: generalize spec_map_id and spec_map_comp into a Lemma and/or
tactic for proving things about specs *)
(* ModelElem commutes with mapping *)
Lemma ModelElem_map model m f A a :
ModelElem f A a model -> ModelElem (applyFM m f) A a (model_map m model).
intro melem; induction melem.
apply ModelElem_Base.
apply ModelElem_Cons; apply IHmelem.
Qed.
(* SpecElem commutes with mapping *)
(*
Lemma SpecElem_map {flds} (spec : Spec (flds:=flds)) m f A a :
SpecElem f A a spec ->
SpecElem (m f) A a (spec_map m spec).
intro selem; induction selem.
apply SpecElem_BaseNone.
apply SpecElem_BaseSome.
unfold spec_map; fold spec_map; apply SpecElem_ConsNone; assumption.
unfold spec_map; fold spec_map; apply SpecElem_ConsSome; assumption.
Qed.
*)
(* IsModel commutes with mapping *)
(* FIXME: prove or remove *)
(*
Lemma IsModel_map_commutes (g : F -> F)
{flds_s} (spec : Spec (flds:=flds_s))
{flds_m} (model : Model (flds:=flds_m)) :
IsModel model spec ->
IsModel (model_map g model) (spec_map g spec).
intro ism; induction ism.
apply IsModel_Nil.
apply IsModel_ConsNone; apply IHism.
apply IsModel_ConsSome; apply IHism.
Qed.
*)
(* FIXME: this no longer holds!
Lemma SuperModel_map_trans {flds1} (model1 : Model (flds:=flds1))
{flds2} (model2 : Model (flds:=flds2))
{flds3} (model3 : Model (flds:=flds3))
m1 m2 :
SuperModel model3 (model_map m2 model2) ->
SuperModel model2 (model_map m1 model1) ->
SuperModel model3 (model_map (fun x : F => m2 (m1 x)) model1).
induction model1.
intros super32 super21 f A a melem; inversion melem.
unfold model_map; fold model_map;
intros super32 super21 f' A' a' melem1.
apply (super32 f' A' a'). apply ModelElem_map.
apply (super21 f' A' a').
destruct super21 as [ melem2 super21 ].
split.
apply (SuperModel_elem (model_map m2 model2)); [ apply ModelElem_map | ]; assumption.
apply IHmodel1; assumption.
Qed.
*)
(**
** Model "un-mapping", which is a weak right inverse of model
** mapping; i.e., model_map m (model_unmap m model) has at least all
** of the same model elements of model
**)
(* Apply Model_Cons once for each field name in a list *)
Fixpoint multi_Model_Cons (flds : list Field) A (a : A) model :=
match flds with
| [] => model
| fld :: flds' => Model_Cons fld A a (multi_Model_Cons flds' A a model)
end.
Lemma In_multi_Model_Cons (flds : list Field) A (a : A) model f :
In f flds -> ModelElem f A a (multi_Model_Cons flds A a model).
induction flds; intro in_pf.
inversion in_pf.
destruct in_pf.
rewrite H; apply ModelElem_Base.
apply ModelElem_Cons; apply IHflds; assumption.
Qed.
Lemma multi_Model_Cons_ModelElem (flds : list Field) A (a : A) model f A' a' :
ModelElem f A' a' model ->
ModelElem f A' a' (multi_Model_Cons flds A a model).
induction flds; intro melem.
apply melem.
apply ModelElem_Cons; apply IHflds; assumption.
Qed.
Lemma multi_Model_Cons_un_ModelElem (flds : list Field) A (a : A) model f A' a' :
ModelElem f A' a' (multi_Model_Cons flds A a model) ->
(In f flds /\ eq_dep _ id A a A' a') \/ ModelElem f A' a' model.
revert A a model f A' a'; induction flds; intros.
right; assumption.
inversion H.
left; split; [ left; reflexivity | reflexivity ].
destruct (IHflds _ _ _ _ _ _ H1).
destruct H5; left; split; [ right | ]; assumption.
right; assumption.
Qed.
(* Un-map a model *)
Fixpoint model_unmap (m : FieldMap) (model : Model) {struct model} : Model :=
match model with
| Model_Nil => Model_Nil
| Model_Cons fld A a model =>
multi_Model_Cons (semiInvertFM m fld) A a (model_unmap m model)
end.
(* Un-mapping the identity function is an identity *)
Lemma model_unmap_id model : model_unmap idFM model = model.
induction model.
reflexivity.
unfold model_unmap; fold model_unmap.
unfold idFM; unfold semiInvertFM;
unfold idFM in IHmodel; rewrite IHmodel; reflexivity.
Qed.
(* applyFM and model_unmap form an adjunction w.r.t. ModelElem *)
Lemma ModelElem_spec_map_model_unmap f A a model m :
ModelElem (applyFM m f) A a model <-> ModelElem f A a (model_unmap m model).
split; intro melem.
induction melem; unfold model_unmap; fold model_unmap.
apply In_multi_Model_Cons; apply in_semiInvert_apply.
apply multi_Model_Cons_ModelElem; assumption.
induction model.
inversion melem.
unfold model_unmap in melem; fold model_unmap in melem.
destruct (multi_Model_Cons_un_ModelElem _ _ _ _ _ _ _ melem).
destruct H.
rewrite H0. rewrite (semiInvertFM_sound _ _ _ H).
apply ModelElem_Base.
apply ModelElem_Cons; apply IHmodel; assumption.
Qed.
(* spec_map and model_unmap form an adjunction w.r.t. IsModel *)
Lemma IsModel_spec_map_model_unmap model {flds} (spec : Spec (flds:=flds)) m :
IsModel model (spec_map m spec) <-> IsModel (model_unmap m model) spec.
split.
induction spec; unfold spec_map; fold spec_map; intro ism.
apply IsModel_Nil.
destruct ism as [ a sig ]; destruct sig as [ melem ism ].
exists a; split;
[ apply ModelElem_spec_map_model_unmap; assumption
| apply H; assumption ].
destruct ism as [ melem ism ]; split;
[ apply ModelElem_spec_map_model_unmap; assumption
| apply IHspec; assumption ].
induction spec; intro ism; unfold spec_map; fold spec_map.
apply IsModel_Nil.
destruct ism as [ a sig ]; destruct sig as [ melem ism ].
exists a; split;
[ apply ModelElem_spec_map_model_unmap; assumption
| apply H; assumption ].
destruct ism as [ melem ism ]; split;
[ apply ModelElem_spec_map_model_unmap; assumption
| apply IHspec; assumption ].
Qed.
(**
** Morphisms
**)
(* A morphism maps the elements of one spec to those of another *)
(*
2Definition IsMorphism_spec {flds1} (spec1 : Spec (flds:=flds1))
{flds2} (spec2 : Spec (flds:=flds2))
(m : F -> F) : Prop :=
forall f A a,
SpecElem f A a spec1 ->
SpecElem (m f) A a spec2.
*)
(* Another def of morphisms, as being a subset mapping for models *)
Definition IsMorphism {flds1} (spec1 : Spec (flds:=flds1))
{flds2} (spec2 : Spec (flds:=flds2))
(m : FieldMap) : Prop :=
forall model,
IsModel model spec2 ->
IsModel model (spec_map m spec1).
(* proof that the two definitions are equivalent *)
(*
Lemma IsMorphism_equiv {flds1} (spec1 : Spec (flds:=flds1))
{flds2} (spec2 : Spec (flds:=flds2))
(m : F -> F) :
IsMorphism spec1 spec2 m <-> IsMorphism_models spec1 spec2 m.
split.
*)
Inductive Morphism {flds1} (spec1 : Spec (flds:=flds1))
{flds2} (spec2 : Spec (flds:=flds2)) :=
| mkMorphism m : IsMorphism spec1 spec2 m -> Morphism spec1 spec2.
Definition projMorph {flds1 spec1 flds2 spec2}
(morph : @Morphism flds1 spec1 flds2 spec2) : FieldMap :=
match morph with
| mkMorphism m _ => m
end.
Definition projMorph_pf {flds1 spec1 flds2 spec2}
(morph : @Morphism flds1 spec1 flds2 spec2) :
IsMorphism spec1 spec2 (projMorph morph) :=
match morph with
| mkMorphism _ pf => pf
end.
(**
** Morphisms as a category
**)
Lemma IsMorphism_id {flds} (spec : Spec (flds:=flds)) :
IsMorphism spec spec idFM.
intros model ism.
rewrite spec_map_id; assumption.
Qed.
Definition mid {flds} spec :
Morphism (flds1:=flds) spec (flds2:=flds) spec :=
mkMorphism spec spec idFM (IsMorphism_id _).
(*
Lemma IsMorphism_map {flds1} (spec1 : Spec (flds:=flds1))
{flds2} (spec2 : Spec (flds:=flds2)) m1 m2 :
IsMorphism spec1 spec2 m1 ->
forall model,
IsModel model (spec_map m' spec2) ->
IsModel model (spec_map (fun f => m' (m f)) spec1).
induction spec1.
intros; apply IsModel_Nil.
intros.
FIXME HERE: how to prove this?!?
IDEA: "un-map" a model along an m, given a set of input fields:
- un-mapping should depend only on m and flds
- NOTE: might duplicate some fields, since model might have duplicate fields,
so we define unmap_flds : flds -> m -> model -> list Field and
unmap : forall flds m model, Model (flds:=unmap_flds flds m model)
- need IsModel model (spec_map m spec) <-> IsModel (unmap flds m model) spec
- can then unmap, pass to the original IsMorphism, and then undo the unmapping
IsMorphism (spec_map m' spec1) (spec_map m' spec2)
*)
Lemma IsMorphism_trans {flds1} (spec1 : Spec (flds:=flds1))
{flds2} (spec2 : Spec (flds:=flds2))
{flds3} (spec3 : Spec (flds:=flds3))
m1 m2 :
IsMorphism spec1 spec2 m1 ->
IsMorphism spec2 spec3 m2 ->
IsMorphism spec1 spec3 (composeFM m1 m2).
intros ismorph1 ismorph2 model ism3.
rewrite <- spec_map_comp.
apply IsModel_spec_map_model_unmap.
apply ismorph1.
apply IsModel_spec_map_model_unmap.
apply ismorph2.
assumption.
Qed.
Definition mcompose {flds1} {spec1 : Spec (flds:=flds1)}
{flds2} {spec2 : Spec (flds:=flds2)}
{flds3} {spec3 : Spec (flds:=flds3)}
(morph1 : Morphism spec1 spec2)
(morph2 : Morphism spec2 spec3) : Morphism spec1 spec3 :=
mkMorphism spec1 spec3 (composeFM (projMorph morph1) (projMorph morph2))
(IsMorphism_trans _ _ _ _ _ (projMorph_pf morph1) (projMorph_pf morph2)).
(**
** Syntax for specs and morphism
**)
(*
FIXME HERE: figure out notations
*)
(* one approach that works... *)
(*
Notation "{| |}" := Spec_Nil (at level 80).
Notation "{| spec |}" := spec.
Notation "end-spec" := Spec_Nil (at level 80).
Notation "f : A := a ; spec" := (Spec_ConsSome f A a spec) (at level 80, spec at level 80).
Notation "f : A ; x => spec" := (Spec_ConsNone f A (fun x => spec)) (at level 80, x ident, spec at level 80).
*)
(* another approach, which always prints one {| |} pair for each level of the spec *)
(*
Notation "{| f : A := a ; spec |}" := (Spec_ConsSome f A a spec) (at level 80, f at level 99, spec at level 80).
Notation "{| f : A ; x => spec |}" := (Spec_ConsNone f A (fun x => spec)) (at level 80, x ident, f at level 99, spec at level 80).
*)
(* README: this notation actually works (but for strings)
Delimit Scope spec_scope with spec_scope.
(* Bind Scope spec_scope with Spec. *)
Global Notation "end-spec" := Spec_Nil (at level 80).
Global Notation "{# spec #}" := (spec%spec_scope : Spec) (at level 100).
Global Notation "f ::: A := a ; spec" := (Spec_ConsSome f A a spec) (at level 80, spec at level 80) : spec_scope.
Global Notation "f ::: A ; x => spec" := (Spec_ConsNone f A (fun x => spec)) (at level 80, x ident, spec at level 80) : spec_scope.
(*
Notation "{{ f : A := a ; spec }}" := (Spec_ConsSome f A a (spec%spec_scope)) (at level 80, f at level 99, spec at level 80).
Notation "{{ f : A ; x => spec }}" := (Spec_ConsNone f A (fun x => (spec%spec_scope))) (at level 80, x ident, f at level 99, spec at level 80).
*)
Global Arguments Spec_ConsSome (f%string) _ _ _ (spec%spec_scope).
Global Arguments Spec_ConsNone (f%string) _ _ (spec%spec_scope).
(*
Eval compute in (Spec_ConsNone "f1" nat (fun f1 => Spec_ConsSome "f2" nat 0 Spec_Nil)).
Eval compute in ({# "f2" ::: nat := 0; end-spec #}).
Eval compute in ({# "f1" ::: nat ; f1 => "f2" ::: nat := 0; end-spec #}).
*)
*)
|
//------------------------------------------- cpu.v ????? -------------------------------------------
/******************************************************************************
*** ?????CPU ?????????RISC_ CPU???, ??????????
*** ????????????????????????????
*****************************************************************************/
`include "clk_gen.v"
`include "accum.v"
`include "adr.v"
`include "alu.v"
`include "machine.v"
`include "counter.v"
`include "machinectl.v"
`include "register.v"
`include "datactl.v"
module cpu(clk,reset,halt,rd,wr,addr,data);
input clk,reset;
output rd,wr,addr,halt;
inout data;
wire clk,reset,halt;
wire [7:0] data;
wire [12:0] addr;
wire rd,wr;
wire clk1,fetch,alu_clk;
wire [2:0] opcode;
wire [12:0] ir_addr,pc_addr;
wire [7:0] alu_out,accum;
wire zero,inc_pc,load_acc,load_pc,load_ir,data_ena,contr_ena;
clk_gen m_clk_gen (.clk(clk),.clk1(clk1),.fetch(fetch),
.alu_clk(alu_clk),.reset(reset));
register m_register (.data(data),.ena(load_ir),.rst(reset),
.clk1(clk1),.opc_iraddr({opcode,ir_addr}));
accum m_accum (.data(alu_out),.ena(load_acc),
.clk1(clk1),.rst(reset),.accum(accum));
alu m_alu (.data(data),.accum(accum),.alu_clk(alu_clk),
.opcode(opcode),.alu_out(alu_out),.zero(zero));
machinectl m_machinecl(.ena(contr_ena),.fetch(fetch),.rst(reset));
machine m_machine (.inc_pc(inc_pc),.load_acc(load_acc),.load_pc(load_pc),
.rd(rd), .wr(wr), .load_ir(load_ir), .clk1(clk1),
.datactl_ena(data_ena), .halt(halt), .zero(zero),
.ena(contr_ena),.opcode(opcode));
datactl m_datactl (.in(alu_out),.data_ena(data_ena),.data(data));
adr m_adr (.fetch(fetch),.ir_addr(ir_addr),.pc_addr(pc_addr),.addr(addr));
counter m_counter (.ir_addr(ir_addr),.load(load_pc),.clock(inc_pc),
.rst(reset),.pc_addr(pc_addr));
endmodule
//--------------------------------------- cpu.v ????? -------------------------------------------------
|
(** * Basics: Functional Programming in Coq *)
(* This library definition is included here temporarily
for backward compatibility with Coq 8.3.
Please ignore. *)
Definition admit {T: Type} : T. Admitted.
(* ###################################################################### *)
(** * Introduction *)
(** The functional programming style brings programming closer to
mathematics: If a procedure or method has no side effects, then
pretty much all you need to understand about it is how it maps
inputs to outputs -- that is, you can think of its behavior as
just computing a mathematical function. This is one reason for
the word "functional" in "functional programming." This direct
connection between programs and simple mathematical objects
supports both sound informal reasoning and formal proofs of
correctness.
The other sense in which functional programming is "functional" is
that it emphasizes the use of functions (or methods) as
_first-class_ values -- i.e., values that can be passed as
arguments to other functions, returned as results, stored in data
structures, etc. The recognition that functions can be treated as
data in this way enables a host of useful idioms, as we will see.
Other common features of functional languages include _algebraic
data types_ and _pattern matching_, which make it easy to construct
and manipulate rich data structures, and sophisticated
_polymorphic type systems_ that support abstraction and code
reuse. Coq shares all of these features.
*)
(* ###################################################################### *)
(** * Enumerated Types *)
(** One unusual aspect of Coq is that its set of built-in
features is _extremely_ small. For example, instead of providing
the usual palette of atomic data types (booleans, integers,
strings, etc.), Coq offers an extremely powerful mechanism for
defining new data types from scratch -- so powerful that all these
familiar types arise as instances.
Naturally, the Coq distribution comes with an extensive standard
library providing definitions of booleans, numbers, and many
common data structures like lists and hash tables. But there is
nothing magic or primitive about these library definitions: they
are ordinary user code.
To see how this works, let's start with a very simple example. *)
(* ###################################################################### *)
(** ** Days of the Week *)
(** The following declaration tells Coq that we are defining
a new set of data values -- a _type_. *)
Inductive day : Type :=
| monday : day
| tuesday : day
| wednesday : day
| thursday : day
| friday : day
| saturday : day
| sunday : day.
(** The type is called [day], and its members are [monday],
[tuesday], etc. The second through eighth lines of the definition
can be read "[monday] is a [day], [tuesday] is a [day], etc."
Having defined [day], we can write functions that operate on
days. *)
Definition next_weekday (d:day) : day :=
match d with
| monday => tuesday
| tuesday => wednesday
| wednesday => thursday
| thursday => friday
| friday => monday
| saturday => monday
| sunday => monday
end.
(** One thing to note is that the argument and return types of
this function are explicitly declared. Like most functional
programming languages, Coq can often work out these types even if
they are not given explicitly -- i.e., it performs some _type
inference_ -- but we'll always include them to make reading
easier. *)
(** Having defined a function, we should check that it works on
some examples. There are actually three different ways to do this
in Coq. First, we can use the command [Eval compute] to evaluate a
compound expression involving [next_weekday]. *)
Eval compute in (next_weekday friday).
(* ==> monday : day *)
Eval compute in (next_weekday (next_weekday saturday)).
(* ==> tuesday : day *)
(** If you have a computer handy, now would be an excellent
moment to fire up the Coq interpreter under your favorite IDE --
either CoqIde or Proof General -- and try this for yourself. Load
this file ([Basics.v]) from the book's accompanying Coq sources,
find the above example, submit it to Coq, and observe the
result. *)
(** The keyword [compute] tells Coq precisely how to
evaluate the expression we give it. For the moment, [compute] is
the only one we'll need; later on we'll see some alternatives that
are sometimes useful. *)
(** Second, we can record what we _expect_ the result to be in
the form of a Coq example: *)
Example test_next_weekday:
(next_weekday (next_weekday saturday)) = tuesday.
(** This declaration does two things: it makes an
assertion (that the second weekday after [saturday] is [tuesday]),
and it gives the assertion a name that can be used to refer to it
later. *)
(** Having made the assertion, we can also ask Coq to verify it,
like this: *)
Proof. simpl. reflexivity. Qed.
(** The details are not important for now (we'll come back to
them in a bit), but essentially this can be read as "The assertion
we've just made can be proved by observing that both sides of the
equality evaluate to the same thing, after some simplification." *)
(** Third, we can ask Coq to "extract," from a [Definition], a
program in some other, more conventional, programming
language (OCaml, Scheme, or Haskell) with a high-performance
compiler. This facility is very interesting, since it gives us a
way to construct _fully certified_ programs in mainstream
languages. Indeed, this is one of the main uses for which Coq was
developed. We'll come back to this topic in later chapters.
More information can also be found in the Coq'Art book by Bertot
and Casteran, as well as the Coq reference manual. *)
(* ###################################################################### *)
(** ** Booleans *)
(** In a similar way, we can define the type [bool] of booleans,
with members [true] and [false]. *)
Inductive bool : Type :=
| true : bool
| false : bool.
(** Although we are rolling our own booleans here for the sake
of building up everything from scratch, Coq does, of course,
provide a default implementation of the booleans in its standard
library, together with a multitude of useful functions and
lemmas. (Take a look at [Coq.Init.Datatypes] in the Coq library
documentation if you're interested.) Whenever possible, we'll
name our own definitions and theorems so that they exactly
coincide with the ones in the standard library. *)
(** Functions over booleans can be defined in the same way as
above: *)
Definition negb (b:bool) : bool :=
match b with
| true => false
| false => true
end.
Definition andb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => b2
| false => false
end.
Definition orb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => true
| false => b2
end.
(** The last two illustrate the syntax for multi-argument
function definitions. *)
(** The following four "unit tests" constitute a complete
specification -- a truth table -- for the [orb] function: *)
Example test_orb1: (orb true false) = true.
Proof. reflexivity. Qed.
Example test_orb2: (orb false false) = false.
Proof. reflexivity. Qed.
Example test_orb3: (orb false true) = true.
Proof. reflexivity. Qed.
Example test_orb4: (orb true true) = true.
Proof. reflexivity. Qed.
(** (Note that we've dropped the [simpl] in the proofs. It's not
actually needed because [reflexivity] will automatically perform
simplification.) *)
(** _A note on notation_: We use square brackets to delimit
fragments of Coq code in comments in .v files; this convention,
also used by the [coqdoc] documentation tool, keeps them visually
separate from the surrounding text. In the html version of the
files, these pieces of text appear in a [different font]. *)
(** The values [Admitted] and [admit] can be used to fill
a hole in an incomplete definition or proof. We'll use them in the
following exercises. In general, your job in the exercises is
to replace [admit] or [Admitted] with real definitions or proofs. *)
(** **** Exercise: 1 star (nandb) *)
(** Complete the definition of the following function, then make
sure that the [Example] assertions below can each be verified by
Coq. *)
(** This function should return [true] if either or both of
its inputs are [false]. *)
Definition nandb (b1:bool) (b2:bool) : bool :=
negb (andb b1 b2).
(** Remove "[Admitted.]" and fill in each proof with
"[Proof. reflexivity. Qed.]" *)
Example test_nandb1: (nandb true false) = true.
Proof. reflexivity. Qed.
Example test_nandb2: (nandb false false) = true.
Proof. reflexivity. Qed.
Example test_nandb3: (nandb false true) = true.
Proof. reflexivity. Qed.
Example test_nandb4: (nandb true true) = false.
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 1 star (andb3) *)
(** Do the same for the [andb3] function below. This function should
return [true] when all of its inputs are [true], and [false]
otherwise. *)
Definition andb3 (b1:bool) (b2:bool) (b3:bool) : bool :=
match b1 with
| true => andb b2 b3
| false => false
end.
Example test_andb31: (andb3 true true true) = true.
Proof. reflexivity. Qed.
Example test_andb32: (andb3 false true true) = false.
Proof. reflexivity. Qed.
Example test_andb33: (andb3 true false true) = false.
Proof. reflexivity. Qed.
Example test_andb34: (andb3 true true false) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** ** Function Types *)
(** The [Check] command causes Coq to print the type of an
expression. For example, the type of [negb true] is [bool]. *)
Check true.
(* ===> true : bool *)
Check (negb true).
(* ===> negb true : bool *)
(** Functions like [negb] itself are also data values, just like
[true] and [false]. Their types are called _function types_, and
they are written with arrows. *)
Check negb.
(* ===> negb : bool -> bool *)
(** The type of [negb], written [bool -> bool] and pronounced
"[bool] arrow [bool]," can be read, "Given an input of type
[bool], this function produces an output of type [bool]."
Similarly, the type of [andb], written [bool -> bool -> bool], can
be read, "Given two inputs, both of type [bool], this function
produces an output of type [bool]." *)
(* ###################################################################### *)
(** ** Numbers *)
(** _Technical digression_: Coq provides a fairly sophisticated
_module system_, to aid in organizing large developments. In this
course we won't need most of its features, but one is useful: If
we enclose a collection of declarations between [Module X] and
[End X] markers, then, in the remainder of the file after the
[End], these definitions will be referred to by names like [X.foo]
instead of just [foo]. Here, we use this feature to introduce the
definition of the type [nat] in an inner module so that it does
not shadow the one from the standard library. *)
Module Playground1.
(** The types we have defined so far are examples of "enumerated
types": their definitions explicitly enumerate a finite set of
elements. A more interesting way of defining a type is to give a
collection of "inductive rules" describing its elements. For
example, we can define the natural numbers as follows: *)
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
(** The clauses of this definition can be read:
- [O] is a natural number (note that this is the letter "[O]," not
the numeral "[0]").
- [S] is a "constructor" that takes a natural number and yields
another one -- that is, if [n] is a natural number, then [S n]
is too.
Let's look at this in a little more detail.
Every inductively defined set ([day], [nat], [bool], etc.) is
actually a set of _expressions_. The definition of [nat] says how
expressions in the set [nat] can be constructed:
- the expression [O] belongs to the set [nat];
- if [n] is an expression belonging to the set [nat], then [S n]
is also an expression belonging to the set [nat]; and
- expressions formed in these two ways are the only ones belonging
to the set [nat].
The same rules apply for our definitions of [day] and [bool]. The
annotations we used for their constructors are analogous to the
one for the [O] constructor, and indicate that each of those
constructors doesn't take any arguments. *)
(** These three conditions are the precise force of the
[Inductive] declaration. They imply that the expression [O], the
expression [S O], the expression [S (S O)], the expression
[S (S (S O))], and so on all belong to the set [nat], while other
expressions like [true], [andb true false], and [S (S false)] do
not.
We can write simple functions that pattern match on natural
numbers just as we did above -- for example, the predecessor
function: *)
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** The second branch can be read: "if [n] has the form [S n']
for some [n'], then return [n']." *)
End Playground1.
Definition minustwo (n : nat) : nat :=
match n with
| O => O
| S O => O
| S (S n') => n'
end.
(** Because natural numbers are such a pervasive form of data,
Coq provides a tiny bit of built-in magic for parsing and printing
them: ordinary arabic numerals can be used as an alternative to
the "unary" notation defined by the constructors [S] and [O]. Coq
prints numbers in arabic form by default: *)
Check (S (S (S (S O)))).
Eval simpl in (minustwo 4).
(** The constructor [S] has the type [nat -> nat], just like the
functions [minustwo] and [pred]: *)
Check S.
Check pred.
Check minustwo.
(** These are all things that can be applied to a number to yield a
number. However, there is a fundamental difference: functions
like [pred] and [minustwo] come with _computation rules_ -- e.g.,
the definition of [pred] says that [pred 2] can be simplified to
[1] -- while the definition of [S] has no such behavior attached.
Although it is like a function in the sense that it can be applied
to an argument, it does not _do_ anything at all! *)
(** For most function definitions over numbers, pure pattern
matching is not enough: we also need recursion. For example, to
check that a number [n] is even, we may need to recursively check
whether [n-2] is even. To write such functions, we use the
keyword [Fixpoint]. *)
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => evenb n'
end.
(** We can define [oddb] by a similar [Fixpoint] declaration, but here
is a simpler definition that will be a bit easier to work with: *)
Definition oddb (n:nat) : bool := negb (evenb n).
Example test_oddb1: (oddb (S O)) = true.
Proof. reflexivity. Qed.
Example test_oddb2: (oddb (S (S (S (S O))))) = false.
Proof. reflexivity. Qed.
(** Naturally, we can also define multi-argument functions by
recursion. (Once again, we use a module to avoid polluting the
namespace.) *)
Module Playground2.
Fixpoint plus (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(** Adding three to two now gives us five, as we'd expect. *)
Eval simpl in (plus (S (S (S O))) (S (S O))).
(** The simplification that Coq performs to reach this conclusion can
be visualized as follows: *)
(* [plus (S (S (S O))) (S (S O))]
==> [S (plus (S (S O)) (S (S O)))] by the second clause of the [match]
==> [S (S (plus (S O) (S (S O))))] by the second clause of the [match]
==> [S (S (S (plus O (S (S O)))))] by the second clause of the [match]
==> [S (S (S (S (S O))))] by the first clause of the [match]
*)
(** As a notational convenience, if two or more arguments have
the same type, they can be written together. In the following
definition, [(n m : nat)] means just the same as if we had written
[(n : nat) (m : nat)]. *)
Fixpoint mult (n m : nat) : nat :=
match n with
| O => O
| S n' => plus m (mult n' m)
end.
Example test_mult1: (mult 3 3) = 9.
Proof. reflexivity. Qed.
(** You can match two expressions at once by putting a comma
between them: *)
Fixpoint minus (n m:nat) : nat :=
match n, m with
| O , _ => O
| S _ , O => n
| S n', S m' => minus n' m'
end.
(** The _ in the first line is a _wildcard pattern_. Writing _ in a
pattern is the same as writing some variable that doesn't get used
on the right-hand side. This avoids the need to invent a bogus
variable name. *)
End Playground2.
Fixpoint exp (base power : nat) : nat :=
match power with
| O => S O
| S p => mult base (exp base p)
end.
(** **** Exercise: 1 star (factorial) *)
(** Recall the standard factorial function:
<<
factorial(0) = 1
factorial(n) = n * factorial(n-1) (if n>0)
>>
Translate this into Coq. *)
Fixpoint factorial (n:nat) : nat :=
match n with
| O => 1
| S n' => n * factorial n'
end.
Example test_factorial1: (factorial 3) = 6.
Proof. reflexivity. Qed.
Example test_factorial2: (factorial 5) = (mult 10 12).
Proof. reflexivity. Qed.
(** [] *)
(** We can make numerical expressions a little easier to read and
write by introducing "notations" for addition, multiplication, and
subtraction. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x - y" := (minus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
Check ((0 + 1) + 1).
(** (The [level], [associativity], and [nat_scope] annotations
control how these notations are treated by Coq's parser. The
details are not important, but interested readers can refer to the
"More on Notation" subsection in the "Optional Material" section at
the end of this chapter.) *)
(** Note that these do not change the definitions we've already
made: they are simply instructions to the Coq parser to accept [x
+ y] in place of [plus x y] and, conversely, to the Coq
pretty-printer to display [plus x y] as [x + y]. *)
(** When we say that Coq comes with nothing built-in, we really
mean it: even equality testing for numbers is a user-defined
operation! *)
(** The [beq_nat] function tests [nat]ural numbers for [eq]uality,
yielding a [b]oolean. Note the use of nested [match]es (we could
also have used a simultaneous match, as we did in [minus].) *)
Fixpoint beq_nat (n m : nat) : bool :=
match n with
| O => match m with
| O => true
| S m' => false
end
| S n' => match m with
| O => false
| S m' => beq_nat n' m'
end
end.
(** Similarly, the [ble_nat] function tests [nat]ural numbers for
[l]ess-or-[e]qual, yielding a [b]oolean. *)
Fixpoint ble_nat (n m : nat) : bool :=
match n with
| O => true
| S n' =>
match m with
| O => false
| S m' => ble_nat n' m'
end
end.
Example test_ble_nat1: (ble_nat 2 2) = true.
Proof. reflexivity. Qed.
Example test_ble_nat2: (ble_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_ble_nat3: (ble_nat 4 2) = false.
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (blt_nat) *)
(** The [blt_nat] function tests [nat]ural numbers for [l]ess-[t]han,
yielding a [b]oolean. Instead of making up a new [Fixpoint] for
this one, define it in terms of a previously defined function.
Note: If you have trouble with the [simpl] tactic, try using
[compute], which is like [simpl] on steroids. However, there is a
simple, elegant solution for which [simpl] suffices. *)
Definition blt_nat (n m : nat) : bool :=
andb (negb (beq_nat n m)) (ble_nat n m).
Example test_blt_nat1: (blt_nat 2 2) = false.
Proof. reflexivity. Qed.
Example test_blt_nat2: (blt_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_blt_nat3: (blt_nat 4 2) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Simplification *)
(** Now that we've defined a few datatypes and functions, let's
turn to the question of how to state and prove properties of their
behavior. Actually, in a sense, we've already started doing this:
each [Example] in the previous sections makes a precise claim
about the behavior of some function on some particular inputs.
The proofs of these claims were always the same: use [reflexivity]
to check that both sides of the [=] simplify to identical values.
(By the way, it will be useful later to know that
[reflexivity] actually does somewhat more than [simpl] -- for
example, it tries "unfolding" defined terms, replacing them with
their right-hand sides. The reason for this difference is that,
when reflexivity succeeds, the whole goal is finished and we don't
need to look at whatever expanded expressions [reflexivity] has
found; by contrast, [simpl] is used in situations where we may
have to read and understand the new goal, so we would not want it
blindly expanding definitions.)
The same sort of "proof by simplification" can be used to prove
more interesting properties as well. For example, the fact that
[0] is a "neutral element" for [+] on the left can be proved
just by observing that [0 + n] reduces to [n] no matter what
[n] is, a fact that can be read directly off the definition of [plus].*)
Theorem plus_O_n : forall n : nat, 0 + n = n.
Proof.
intros n. reflexivity. Qed.
(** (_Note_: You may notice that the above statement looks
different in the original source file and the final html output. In Coq
files, we write the [forall] universal quantifier using the
"_forall_" reserved identifier. This gets printed as an
upside-down "A", the familiar symbol used in logic.) *)
(** The form of this theorem and proof are almost exactly the
same as the examples above; there are just a few differences.
First, we've used the keyword keyword [Theorem] instead of
[Example]. Indeed, the latter difference is purely a matter of
style; the keywords [Example] and [Theorem] (and a few others,
including [Lemma], [Fact], and [Remark]) mean exactly the same
thing to Coq.
Secondly, we've added the quantifier [forall n:nat], so that our
theorem talks about _all_ natural numbers [n]. In order to prove
theorems of this form, we need to to be able to reason by
_assuming_ the existence of an arbitrary natural number [n]. This
is achieved in the proof by [intros n], which moves the quantifier
from the goal to a "context" of current assumptions. In effect, we
start the proof by saying "OK, suppose [n] is some arbitrary number."
The keywords [intros], [simpl], and [reflexivity] are examples of
_tactics_. A tactic is a command that is used between [Proof] and
[Qed] to tell Coq how it should check the correctness of some
claim we are making. We will see several more tactics in the rest
of this lecture, and yet more in future lectures. *)
(** Step through these proofs in Coq and notice how the goal and
context change. *)
Theorem plus_1_l : forall n:nat, 1 + n = S n.
Proof.
intros n. reflexivity. Qed.
Theorem mult_0_l : forall n:nat, 0 * n = 0.
Proof.
intros n. reflexivity. Qed.
(** The [_l] suffix in the names of these theorems is
pronounced "on the left." *)
(* ###################################################################### *)
(** * Proof by Rewriting *)
(** Here is a slightly more interesting theorem: *)
Theorem plus_id_example : forall n m:nat,
n = m ->
n + n = m + m.
(** Instead of making a completely universal claim about all numbers
[n] and [m], this theorem talks about a more specialized property
that only holds when [n = m]. The arrow symbol is pronounced
"implies."
As before, we need to be able to reason by assuming the existence
of some numbers [n] and [m]. We also need to assume the hypothesis
[n = m]. The [intros] tactic will serve to move all three of these
from the goal into assumptions in the current context.
Since [n] and [m] are arbitrary numbers, we can't just use
simplification to prove this theorem. Instead, we prove it by
observing that, if we are assuming [n = m], then we can replace
[n] with [m] in the goal statement and obtain an equality with the
same expression on both sides. The tactic that tells Coq to
perform this replacement is called [rewrite]. *)
Proof.
intros n m. (* move both quantifiers into the context *)
intros H. (* move the hypothesis into the context *)
rewrite -> H. (* Rewrite the goal using the hypothesis *)
reflexivity. Qed.
(** The first line of the proof moves the universally quantified
variables [n] and [m] into the context. The second moves the
hypothesis [n = m] into the context and gives it the (arbitrary)
name [H]. The third tells Coq to rewrite the current goal ([n + n
= m + m]) by replacing the left side of the equality hypothesis
[H] with the right side.
(The arrow symbol in the [rewrite] has nothing to do with
implication: it tells Coq to apply the rewrite from left to right.
To rewrite from right to left, you can use [rewrite <-]. Try
making this change in the above proof and see what difference it
makes in Coq's behavior.) *)
(** **** Exercise: 1 star (plus_id_exercise) *)
(** Remove "[Admitted.]" and fill in the proof. *)
Theorem plus_id_exercise : forall n m o : nat,
n = m -> m = o -> n + m = m + o.
Proof.
intros n m o H1 H2.
rewrite -> H1.
rewrite -> H2.
reflexivity.
Qed.
(** [] *)
(** As we've seen in earlier examples, the [Admitted] command
tells Coq that we want to skip trying to prove this theorem and
just accept it as a given. This can be useful for developing
longer proofs, since we can state subsidiary facts that we believe
will be useful for making some larger argument, use [Admitted] to
accept them on faith for the moment, and continue thinking about
the larger argument until we are sure it makes sense; then we can
go back and fill in the proofs we skipped. Be careful, though:
every time you say [Admitted] (or [admit]) you are leaving a door
open for total nonsense to enter Coq's nice, rigorous, formally
checked world! *)
(** We can also use the [rewrite] tactic with a previously proved
theorem instead of a hypothesis from the context. *)
Theorem mult_0_plus : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
rewrite -> plus_O_n.
reflexivity. Qed.
(** **** Exercise: 2 stars (mult_S_1) *)
Theorem mult_S_1 : forall n m : nat,
m = S n ->
m * (1 + n) = m * m.
Proof.
intros n m H.
rewrite -> plus_1_l.
rewrite -> H.
reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Case Analysis *)
(** Of course, not everything can be proved by simple
calculation: In general, unknown, hypothetical values (arbitrary
numbers, booleans, lists, etc.) can block the calculation.
For example, if we try to prove the following fact using the
[simpl] tactic as above, we get stuck. *)
Theorem plus_1_neq_0_firsttry : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n.
simpl. (* does nothing! *)
Abort.
(** The reason for this is that the definitions of both
[beq_nat] and [+] begin by performing a [match] on their first
argument. But here, the first argument to [+] is the unknown
number [n] and the argument to [beq_nat] is the compound
expression [n + 1]; neither can be simplified.
What we need is to be able to consider the possible forms of [n]
separately. If [n] is [O], then we can calculate the final result
of [beq_nat (n + 1) 0] and check that it is, indeed, [false].
And if [n = S n'] for some [n'], then, although we don't know
exactly what number [n + 1] yields, we can calculate that, at
least, it will begin with one [S], and this is enough to calculate
that, again, [beq_nat (n + 1) 0] will yield [false].
The tactic that tells Coq to consider, separately, the cases where
[n = O] and where [n = S n'] is called [destruct]. *)
Theorem plus_1_neq_0 : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n. destruct n as [| n'].
reflexivity.
reflexivity. Qed.
(** The [destruct] generates _two_ subgoals, which we must then
prove, separately, in order to get Coq to accept the theorem as
proved. (No special command is needed for moving from one subgoal
to the other. When the first subgoal has been proved, it just
disappears and we are left with the other "in focus.") In this
proof, each of the subgoals is easily proved by a single use of
[reflexivity].
The annotation "[as [| n']]" is called an _intro pattern_. It
tells Coq what variable names to introduce in each subgoal. In
general, what goes between the square brackets is a _list_ of
lists of names, separated by [|]. Here, the first component is
empty, since the [O] constructor is nullary (it doesn't carry any
data). The second component gives a single name, [n'], since [S]
is a unary constructor.
The [destruct] tactic can be used with any inductively defined
datatype. For example, we use it here to prove that boolean
negation is involutive -- i.e., that negation is its own
inverse. *)
Theorem negb_involutive : forall b : bool,
negb (negb b) = b.
Proof.
intros b. destruct b.
reflexivity.
reflexivity. Qed.
(** Note that the [destruct] here has no [as] clause because
none of the subcases of the [destruct] need to bind any variables,
so there is no need to specify any names. (We could also have
written [as [|]], or [as []].) In fact, we can omit the [as]
clause from _any_ [destruct] and Coq will fill in variable names
automatically. Although this is convenient, it is arguably bad
style, since Coq often makes confusing choices of names when left
to its own devices. *)
(** **** Exercise: 1 star (zero_nbeq_plus_1) *)
Theorem zero_nbeq_plus_1 : forall n : nat,
beq_nat 0 (n + 1) = false.
Proof.
intros n. destruct n as [| n'].
reflexivity.
reflexivity.
Qed.
(** [] *)
(* ###################################################################### *)
(** * More Exercises *)
(** **** Exercise: 2 stars (boolean functions) *)
(** Use the tactics you have learned so far to prove the following
theorem about boolean functions. *)
Theorem identity_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = x) ->
forall (b : bool), f (f b) = b.
Proof.
intros f x b.
destruct b.
rewrite -> x.
rewrite -> x.
reflexivity.
rewrite -> x.
rewrite -> x.
reflexivity.
Qed.
(** Now state and prove a theorem [negation_fn_applied_twice] similar
to the previous one but where the second hypothesis says that the
function [f] has the property that [f x = negb x].*)
Theorem negation_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = negb x) ->
forall (b : bool), f (f b) = b.
Proof.
intros f x b.
destruct b.
rewrite -> x.
rewrite -> x.
reflexivity.
rewrite -> x.
rewrite -> x.
reflexivity.
Qed.
(** **** Exercise: 2 stars (andb_eq_orb) *)
(** Prove the following theorem. (You may want to first prove a
subsidiary lemma or two.) *)
Theorem andb_true_false : andb true false = false.
Proof. reflexivity. Qed.
Theorem andb_false_true : andb false true = false.
Proof. reflexivity. Qed.
Theorem andb_eq_orb :
forall (b c : bool),
(andb b c = orb b c) ->
b = c.
Proof.
intros b c H.
destruct b.
destruct c.
reflexivity.
rewrite <- andb_true_false.
rewrite -> H.
reflexivity.
destruct c.
rewrite <- andb_false_true.
rewrite -> H.
reflexivity.
reflexivity.
Qed.
(** **** Exercise: 3 stars (binary) *)
(** Consider a different, more efficient representation of natural
numbers using a binary rather than unary system. That is, instead
of saying that each natural number is either zero or the successor
of a natural number, we can say that each binary number is either
- zero,
- twice a binary number, or
- one more than twice a binary number.
(a) First, write an inductive definition of the type [bin]
corresponding to this description of binary numbers.
(Hint: Recall that the definition of [nat] from class,
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
says nothing about what [O] and [S] "mean." It just says "[O] is
in the set called [nat], and if [n] is in the set then so is [S
n]." The interpretation of [O] as zero and [S] as successor/plus
one comes from the way that we _use_ [nat] values, by writing
functions to do things with them, proving things about them, and
so on. Your definition of [bin] should be correspondingly simple;
it is the functions you will write next that will give it
mathematical meaning.)
(b) Next, write an increment function for binary numbers, and a
function to convert binary numbers to unary numbers.
(c) Write some unit tests for your increment and binary-to-unary
functions. Notice that incrementing a binary number and
then converting it to unary should yield the same result as first
converting it to unary and then incrementing.
*)
Inductive bin : Type :=
| Zero : bin
| Twice : bin -> bin
| More : bin -> bin.
Fixpoint bin_inc (b : bin) : bin :=
match b with
| Zero => More Zero
| Twice b' => More b'
| More b' => Twice (bin_inc b')
end.
Fixpoint bin_to_nat (b : bin) : nat :=
match b with
| Zero => O
| Twice b' => 2 * bin_to_nat b'
| More b' => 2 * bin_to_nat b' + 1
end.
Example test_bin1 : bin_to_nat (bin_inc Zero) = bin_to_nat Zero + 1.
Proof. reflexivity. Qed.
Example test_bin2 : bin_to_nat (bin_inc (More Zero)) = bin_to_nat (More Zero) + 1.
Proof. reflexivity. Qed.
Example test_bin3 : bin_to_nat (Twice (More Zero)) = 2 * bin_to_nat (More Zero).
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Optional Material *)
(** ** More on Notation *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
(** For each notation-symbol in Coq we can specify its _precedence level_
and its _associativity_. The precedence level n can be specified by the
keywords [at level n] and it is helpful to disambiguate
expressions containing different symbols. The associativity is helpful
to disambiguate expressions containing more occurrences of the same
symbol. For example, the parameters specified above for [+] and [*]
say that the expression [1+2*3*4] is a shorthand for the expression
[(1+((2*3)*4))]. Coq uses precedence levels from 0 to 100, and
_left_, _right_, or _no_ associativity.
Each notation-symbol in Coq is also active in a _notation scope_.
Coq tries to guess what scope you mean, so when you write [S(O*O)]
it guesses [nat_scope], but when you write the cartesian
product (tuple) type [bool*bool] it guesses [type_scope].
Occasionally you have to help it out with percent-notation by
writing [(x*y)%nat], and sometimes in Coq's feedback to you it
will use [%nat] to indicate what scope a notation is in.
Notation scopes also apply to numeral notation (3,4,5, etc.), so you
may sometimes see [0%nat] which means [O], or [0%Z] which means the
Integer zero.
*)
(** ** [Fixpoint]s and Structural Recursion *)
Fixpoint plus' (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus' n' m)
end.
(** When Coq checks this definition, it notes that [plus'] is
"decreasing on 1st argument." What this means is that we are
performing a _structural recursion_ over the argument [n] -- i.e.,
that we make recursive calls only on strictly smaller values of
[n]. This implies that all calls to [plus'] will eventually
terminate. Coq demands that some argument of _every_ [Fixpoint]
definition is "decreasing".
This requirement is a fundamental feature of Coq's design: In
particular, it guarantees that every function that can be defined
in Coq will terminate on all inputs. However, because Coq's
"decreasing analysis" is not very sophisticated, it is sometimes
necessary to write functions in slightly unnatural ways. *)
(** **** Exercise: 2 stars, optional (decreasing) *)
(** To get a concrete sense of this, find a way to write a sensible
[Fixpoint] definition (of a simple function on numbers, say) that
_does_ terminate on all inputs, but that Coq will _not_ accept
because of this restriction. *)
(* FILL IN HERE *)
(** [] *)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of avfb_chip
//
// Generated
// by: wig
// on: Tue Apr 18 07:50:26 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bugver.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: avfb_chip.v,v 1.1 2006/04/19 07:33:12 wig Exp $
// $Date: 2006/04/19 07:33:12 $
// $Log: avfb_chip.v,v $
// Revision 1.1 2006/04/19 07:33:12 wig
// Updated/added testcase for 20060404c issue. Needs more work!
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.82 2006/04/13 13:31:52 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of avfb_chip
//
// No user `defines in this module
module avfb_chip
//
// Generated module dut
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
// Generated Instance Port Map for i_avfb_top
avfb_top i_avfb_top (
);
// End of Generated Instance Port Map for i_avfb_top
endmodule
//
// End of Generated Module rtl of avfb_chip
//
//
//!End of Module/s
// --------------------------------------------------------------
|
`default_nettype none
// ============================================================================
// Copyright (c) 2013 by Terasic Technologies Inc.
// ============================================================================
//
// Permission:
//
// Terasic grants permission to use and modify this code for use
// in synthesis for all Terasic Development Boards and Altera Development
// Kits made by Terasic. Other use of this code, including the selling
// ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
// This VHDL/Verilog or C/C++ source code is intended as a design reference
// which illustrates how these types of functions can be implemented.
// It is the user's responsibility to verify their design for
// consistency and functionality through the use of formal
// verification methods. Terasic provides no warranty regarding the use
// or functionality of this code.
//
// ============================================================================
//
// Terasic Technologies Inc
// 9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
//
//
// web: http://www.terasic.com/
// email: [email protected]
//
// ============================================================================
//Date: Mon Jun 17 20:35:29 2013
// ============================================================================
`define ENABLE_HPS
module ghrd_top(
///////// ADC /////////
inout ADC_CS_N,
output ADC_DIN,
input ADC_DOUT,
output ADC_SCLK,
///////// AUD /////////
input AUD_ADCDAT,
inout AUD_ADCLRCK,
inout AUD_BCLK,
output AUD_DACDAT,
inout AUD_DACLRCK,
output AUD_XCK,
///////// CLOCK2 /////////
input CLOCK2_50,
///////// CLOCK3 /////////
input CLOCK3_50,
///////// CLOCK4 /////////
input CLOCK4_50,
///////// CLOCK /////////
input CLOCK_50,
///////// DRAM /////////
output [12:0] DRAM_ADDR,
output [1:0] DRAM_BA,
output DRAM_CAS_N,
output DRAM_CKE,
output DRAM_CLK,
output DRAM_CS_N,
inout [15:0] DRAM_DQ,
output DRAM_LDQM,
output DRAM_RAS_N,
output DRAM_UDQM,
output DRAM_WE_N,
///////// FAN /////////
output FAN_CTRL,
///////// FPGA /////////
output FPGA_I2C_SCLK,
inout FPGA_I2C_SDAT,
///////// GPIO /////////
inout [35:0] GPIO_0,
inout [35:0] GPIO_1,
///////// HEX0 /////////
output [6:0] HEX0,
///////// HEX1 /////////
output [6:0] HEX1,
///////// HEX2 /////////
output [6:0] HEX2,
///////// HEX3 /////////
output [6:0] HEX3,
///////// HEX4 /////////
output [6:0] HEX4,
///////// HEX5 /////////
output [6:0] HEX5,
`ifdef ENABLE_HPS
///////// HPS /////////
inout HPS_CONV_USB_N,
output [14:0] HPS_DDR3_ADDR,
output [2:0] HPS_DDR3_BA,
output HPS_DDR3_CAS_N,
output HPS_DDR3_CKE,
output HPS_DDR3_CK_N,
output HPS_DDR3_CK_P,
output HPS_DDR3_CS_N,
output [3:0] HPS_DDR3_DM,
inout [31:0] HPS_DDR3_DQ,
inout [3:0] HPS_DDR3_DQS_N,
inout [3:0] HPS_DDR3_DQS_P,
output HPS_DDR3_ODT,
output HPS_DDR3_RAS_N,
output HPS_DDR3_RESET_N,
input HPS_DDR3_RZQ,
output HPS_DDR3_WE_N,
output HPS_ENET_GTX_CLK,
inout HPS_ENET_INT_N,
output HPS_ENET_MDC,
inout HPS_ENET_MDIO,
input HPS_ENET_RX_CLK,
input [3:0] HPS_ENET_RX_DATA,
input HPS_ENET_RX_DV,
output [3:0] HPS_ENET_TX_DATA,
output HPS_ENET_TX_EN,
inout [3:0] HPS_FLASH_DATA,
output HPS_FLASH_DCLK,
output HPS_FLASH_NCSO,
inout HPS_GSENSOR_INT,
inout HPS_I2C1_SCLK,
inout HPS_I2C1_SDAT,
inout HPS_I2C2_SCLK,
inout HPS_I2C2_SDAT,
inout HPS_I2C_CONTROL,
inout HPS_KEY,
inout HPS_LED,
inout HPS_LTC_GPIO,
output HPS_SD_CLK,
inout HPS_SD_CMD,
inout [3:0] HPS_SD_DATA,
output HPS_SPIM_CLK,
input HPS_SPIM_MISO,
output HPS_SPIM_MOSI,
inout HPS_SPIM_SS,
input HPS_UART_RX,
output HPS_UART_TX,
input HPS_USB_CLKOUT,
inout [7:0] HPS_USB_DATA,
input HPS_USB_DIR,
input HPS_USB_NXT,
output HPS_USB_STP,
`endif /*ENABLE_HPS*/
///////// IRDA /////////
input IRDA_RXD,
output IRDA_TXD,
///////// KEY /////////
input [3:0] KEY,
///////// LEDR /////////
output [9:0] LEDR,
///////// PS2 /////////
inout PS2_CLK,
inout PS2_CLK2,
inout PS2_DAT,
inout PS2_DAT2,
///////// SW /////////
input [9:0] SW,
///////// TD /////////
input TD_CLK27,
input [7:0] TD_DATA,
input TD_HS,
output TD_RESET_N,
input TD_VS,
///////// VGA /////////
output [7:0] VGA_B,
output VGA_BLANK_N,
output VGA_CLK,
output [7:0] VGA_G,
output VGA_HS,
output [7:0] VGA_R,
output VGA_SYNC_N,
output VGA_VS
);
//=======================================================
// REG/WIRE declarations
//=======================================================
wire hps_fpga_reset_n;
wire [3:0] fpga_button_internal;
wire [9:0] fpga_led_internal;
wire [9:0] fpga_dipsw_internal;
wire [2:0] hps_reset_req;
wire hps_cold_reset;
wire hps_warm_reset;
wire hps_debug_reset;
wire [27:0] stm_hw_events;
wire fpga_clk_50;
wire clk_65;
wire clk_130;
wire [7:0] vid_r,vid_g,vid_b;
wire vid_v_sync ;
wire vid_h_sync ;
wire vid_datavalid;
// connection of internal logics
//assign LEDR = fpga_led_internal;
assign LEDR = ece453_leds;
assign fpga_button_internal = KEY;
assign fpga_dipsw_internal = SW;
assign stm_hw_events = {{4{1'b0}}, fpga_dipsw_internal, fpga_led_internal, fpga_button_internal};
assign fpga_clk_50 = CLOCK_50;
//=======================================================
// Structural coding
//=======================================================
assign VGA_BLANK_N = 1'b1;
assign VGA_SYNC_N = 1'b0;
assign VGA_CLK = clk_65;
assign {VGA_B,VGA_G,VGA_R} = {vid_b,vid_g,vid_r};
assign VGA_VS = vid_v_sync;
assign VGA_HS = vid_h_sync;
vga_pll vga_pll_inst(
.refclk(CLOCK_50), // refclk.clk
.rst(1'b0), // reset.reset
.outclk_0(clk_65), // outclk0.clk
.outclk_1(clk_130), // outclk1.clk
.locked() // locked.export
);
//=====================================================================================//
// ECE 453 START
//=====================================================================================
// ECE453 Module Connections
wire [16:0] ece453_gpio_out_unused;
wire [9:0] ece453_leds;
// i2c connection
wire scl_o_e;
wire scl_o;
wire sda_o_e;
wire sda_o;
ALT_IOBUF scl_iobuf (.i(1'b0), .oe(scl_o_e), .o(scl_o), .io(GPIO_1[7])); //declared bi-directional buffer for scl
ALT_IOBUF sda_iobuf (.i(1'b0), .oe(sda_o_e), .o(sda_o), .io(GPIO_1[11])); //declared bi-directional buffer for s
//.ece453_0_switches (SW),
//.ece453_0_buttons (KEY),
//.ece453_0_lcd_cmd (GPIO_1[17]),
//.ece453_0_leds (LEDR),
//.ece453_0_ws2812b (GPIO_1[1]),
//=====================================================================================//
// ECE 453 END
//=====================================================================================
soc_system u0 (
.clk_clk (CLOCK_50), // clk.clk
.reset_reset_n (hps_fpga_reset_n), // reset.reset_n
//HPS ddr3
.memory_mem_a ( HPS_DDR3_ADDR), // memory.mem_a
.memory_mem_ba ( HPS_DDR3_BA), // .mem_ba
.memory_mem_ck ( HPS_DDR3_CK_P), // .mem_ck
.memory_mem_ck_n ( HPS_DDR3_CK_N), // .mem_ck_n
.memory_mem_cke ( HPS_DDR3_CKE), // .mem_cke
.memory_mem_cs_n ( HPS_DDR3_CS_N), // .mem_cs_n
.memory_mem_ras_n ( HPS_DDR3_RAS_N), // .mem_ras_n
.memory_mem_cas_n ( HPS_DDR3_CAS_N), // .mem_cas_n
.memory_mem_we_n ( HPS_DDR3_WE_N), // .mem_we_n
.memory_mem_reset_n ( HPS_DDR3_RESET_N), // .mem_reset_n
.memory_mem_dq ( HPS_DDR3_DQ), // .mem_dq
.memory_mem_dqs ( HPS_DDR3_DQS_P), // .mem_dqs
.memory_mem_dqs_n ( HPS_DDR3_DQS_N), // .mem_dqs_n
.memory_mem_odt ( HPS_DDR3_ODT), // .mem_odt
.memory_mem_dm ( HPS_DDR3_DM), // .mem_dm
.memory_oct_rzqin ( HPS_DDR3_RZQ), // .oct_rzqin
//HPS ethernet
.hps_0_hps_io_hps_io_emac1_inst_TX_CLK ( HPS_ENET_GTX_CLK), // hps_0_hps_io.hps_io_emac1_inst_TX_CLK
.hps_0_hps_io_hps_io_emac1_inst_TXD0 ( HPS_ENET_TX_DATA[0] ), // .hps_io_emac1_inst_TXD0
.hps_0_hps_io_hps_io_emac1_inst_TXD1 ( HPS_ENET_TX_DATA[1] ), // .hps_io_emac1_inst_TXD1
.hps_0_hps_io_hps_io_emac1_inst_TXD2 ( HPS_ENET_TX_DATA[2] ), // .hps_io_emac1_inst_TXD2
.hps_0_hps_io_hps_io_emac1_inst_TXD3 ( HPS_ENET_TX_DATA[3] ), // .hps_io_emac1_inst_TXD3
.hps_0_hps_io_hps_io_emac1_inst_RXD0 ( HPS_ENET_RX_DATA[0] ), // .hps_io_emac1_inst_RXD0
.hps_0_hps_io_hps_io_emac1_inst_MDIO ( HPS_ENET_MDIO ), // .hps_io_emac1_inst_MDIO
.hps_0_hps_io_hps_io_emac1_inst_MDC ( HPS_ENET_MDC ), // .hps_io_emac1_inst_MDC
.hps_0_hps_io_hps_io_emac1_inst_RX_CTL ( HPS_ENET_RX_DV), // .hps_io_emac1_inst_RX_CTL
.hps_0_hps_io_hps_io_emac1_inst_TX_CTL ( HPS_ENET_TX_EN), // .hps_io_emac1_inst_TX_CTL
.hps_0_hps_io_hps_io_emac1_inst_RX_CLK ( HPS_ENET_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_0_hps_io_hps_io_emac1_inst_RXD1 ( HPS_ENET_RX_DATA[1] ), // .hps_io_emac1_inst_RXD1
.hps_0_hps_io_hps_io_emac1_inst_RXD2 ( HPS_ENET_RX_DATA[2] ), // .hps_io_emac1_inst_RXD2
.hps_0_hps_io_hps_io_emac1_inst_RXD3 ( HPS_ENET_RX_DATA[3] ), // .hps_io_emac1_inst_RXD3
//HPS QSPI
.hps_0_hps_io_hps_io_qspi_inst_IO0 ( HPS_FLASH_DATA[0] ), // .hps_io_qspi_inst_IO0
.hps_0_hps_io_hps_io_qspi_inst_IO1 ( HPS_FLASH_DATA[1] ), // .hps_io_qspi_inst_IO1
.hps_0_hps_io_hps_io_qspi_inst_IO2 ( HPS_FLASH_DATA[2] ), // .hps_io_qspi_inst_IO2
.hps_0_hps_io_hps_io_qspi_inst_IO3 ( HPS_FLASH_DATA[3] ), // .hps_io_qspi_inst_IO3
.hps_0_hps_io_hps_io_qspi_inst_SS0 ( HPS_FLASH_NCSO ), // .hps_io_qspi_inst_SS0
.hps_0_hps_io_hps_io_qspi_inst_CLK ( HPS_FLASH_DCLK ), // .hps_io_qspi_inst_CLK
//HPS SD card
.hps_0_hps_io_hps_io_sdio_inst_CMD ( HPS_SD_CMD ), // .hps_io_sdio_inst_CMD
.hps_0_hps_io_hps_io_sdio_inst_D0 ( HPS_SD_DATA[0] ), // .hps_io_sdio_inst_D0
.hps_0_hps_io_hps_io_sdio_inst_D1 ( HPS_SD_DATA[1] ), // .hps_io_sdio_inst_D1
.hps_0_hps_io_hps_io_sdio_inst_CLK ( HPS_SD_CLK ), // .hps_io_sdio_inst_CLK
.hps_0_hps_io_hps_io_sdio_inst_D2 ( HPS_SD_DATA[2] ), // .hps_io_sdio_inst_D2
.hps_0_hps_io_hps_io_sdio_inst_D3 ( HPS_SD_DATA[3] ), // .hps_io_sdio_inst_D3
//HPS USB
.hps_0_hps_io_hps_io_usb1_inst_D0 ( HPS_USB_DATA[0] ), // .hps_io_usb1_inst_D0
.hps_0_hps_io_hps_io_usb1_inst_D1 ( HPS_USB_DATA[1] ), // .hps_io_usb1_inst_D1
.hps_0_hps_io_hps_io_usb1_inst_D2 ( HPS_USB_DATA[2] ), // .hps_io_usb1_inst_D2
.hps_0_hps_io_hps_io_usb1_inst_D3 ( HPS_USB_DATA[3] ), // .hps_io_usb1_inst_D3
.hps_0_hps_io_hps_io_usb1_inst_D4 ( HPS_USB_DATA[4] ), // .hps_io_usb1_inst_D4
.hps_0_hps_io_hps_io_usb1_inst_D5 ( HPS_USB_DATA[5] ), // .hps_io_usb1_inst_D5
.hps_0_hps_io_hps_io_usb1_inst_D6 ( HPS_USB_DATA[6] ), // .hps_io_usb1_inst_D6
.hps_0_hps_io_hps_io_usb1_inst_D7 ( HPS_USB_DATA[7] ), // .hps_io_usb1_inst_D7
.hps_0_hps_io_hps_io_usb1_inst_CLK ( HPS_USB_CLKOUT ), // .hps_io_usb1_inst_CLK
.hps_0_hps_io_hps_io_usb1_inst_STP ( HPS_USB_STP ), // .hps_io_usb1_inst_STP
.hps_0_hps_io_hps_io_usb1_inst_DIR ( HPS_USB_DIR ), // .hps_io_usb1_inst_DIR
.hps_0_hps_io_hps_io_usb1_inst_NXT ( HPS_USB_NXT ), // .hps_io_usb1_inst_NXT
//HPS SPI
.hps_0_hps_io_hps_io_spim1_inst_CLK ( HPS_SPIM_CLK ), // .hps_io_spim1_inst_CLK
.hps_0_hps_io_hps_io_spim1_inst_MOSI ( HPS_SPIM_MOSI ), // .hps_io_spim1_inst_MOSI
.hps_0_hps_io_hps_io_spim1_inst_MISO ( HPS_SPIM_MISO ), // .hps_io_spim1_inst_MISO
.hps_0_hps_io_hps_io_spim1_inst_SS0 ( HPS_SPIM_SS ), // .hps_io_spim1_inst_SS0
//HPS UART
.hps_0_hps_io_hps_io_uart0_inst_RX ( HPS_UART_RX ), // .hps_io_uart0_inst_RX
.hps_0_hps_io_hps_io_uart0_inst_TX ( HPS_UART_TX ), // .hps_io_uart0_inst_TX
//HPS I2C1
.hps_0_hps_io_hps_io_i2c0_inst_SDA ( HPS_I2C1_SDAT ), // .hps_io_i2c0_inst_SDA
.hps_0_hps_io_hps_io_i2c0_inst_SCL ( HPS_I2C1_SCLK ), // .hps_io_i2c0_inst_SCL
//HPS I2C2
.hps_0_hps_io_hps_io_i2c1_inst_SDA ( HPS_I2C2_SDAT ), // .hps_io_i2c1_inst_SDA
.hps_0_hps_io_hps_io_i2c1_inst_SCL ( HPS_I2C2_SCLK ), // .hps_io_i2c1_inst_SCL
//HPS GPIO
.hps_0_hps_io_hps_io_gpio_inst_GPIO09 ( HPS_CONV_USB_N), // .hps_io_gpio_inst_GPIO09
.hps_0_hps_io_hps_io_gpio_inst_GPIO35 ( HPS_ENET_INT_N), // .hps_io_gpio_inst_GPIO35
.hps_0_hps_io_hps_io_gpio_inst_GPIO40 ( HPS_LTC_GPIO), // .hps_io_gpio_inst_GPIO40
//.hps_0_hps_io_hps_io_gpio_inst_GPIO41 ( HPS_GPIO[1]), // .hps_io_gpio_inst_GPIO41
.hps_0_hps_io_hps_io_gpio_inst_GPIO48 ( HPS_I2C_CONTROL), // .hps_io_gpio_inst_GPIO48
.hps_0_hps_io_hps_io_gpio_inst_GPIO53 ( HPS_LED), // .hps_io_gpio_inst_GPIO53
.hps_0_hps_io_hps_io_gpio_inst_GPIO54 ( HPS_KEY), // .hps_io_gpio_inst_GPIO54
.hps_0_hps_io_hps_io_gpio_inst_GPIO61 ( HPS_GSENSOR_INT), // .hps_io_gpio_inst_GPIO61
//HPS reset output
//.led_pio_external_connection_export ( fpga_led_internal ), // led_pio_external_connection.export
//.dipsw_pio_external_connection_export ( fpga_dipsw_internal ), // dipsw_pio_external_connection.export
//.button_pio_external_connection_export ( fpga_button_internal ), // button_pio_external_connection.export
.hps_0_h2f_reset_reset_n ( hps_fpga_reset_n ), // hps_0_h2f_reset.reset_n
.hps_0_f2h_cold_reset_req_reset_n (~hps_cold_reset ), // hps_0_f2h_cold_reset_req.reset_n
.hps_0_f2h_debug_reset_req_reset_n (~hps_debug_reset ), // hps_0_f2h_debug_reset_req.reset_n
.hps_0_f2h_stm_hw_events_stm_hwevents (stm_hw_events ), // hps_0_f2h_stm_hw_events.stm_hwevents
.hps_0_f2h_warm_reset_req_reset_n (~hps_warm_reset ), // hps_0_f2h_warm_reset_req.reset_n
////itc
.alt_vip_itc_0_clocked_video_vid_clk (~clk_65), // alt_vip_itc_0_clocked_video.vid_clk
.alt_vip_itc_0_clocked_video_vid_data ({vid_r,vid_g,vid_b}), // .vid_data
.alt_vip_itc_0_clocked_video_underflow (), // .underflow
.alt_vip_itc_0_clocked_video_vid_datavalid (vid_datavalid), // .vid_datavalid
.alt_vip_itc_0_clocked_video_vid_v_sync (vid_v_sync), // .vid_v_sync
.alt_vip_itc_0_clocked_video_vid_h_sync (vid_h_sync), // .vid_h_sync
.alt_vip_itc_0_clocked_video_vid_f (), // .vid_f
.alt_vip_itc_0_clocked_video_vid_h (), // .vid_h
.alt_vip_itc_0_clocked_video_vid_v (),
.clk_130_clk (clk_130),
//=====================================================================================//
// ECE 453 START
//=====================================================================================//
// SPI - LCD Interface
.hps_0_spim0_txd (GPIO_1[13]),
.hps_0_spim0_rxd (1'b1),
.hps_0_spim0_ss_in_n (1'b1),
.hps_0_spim0_ssi_oe_n (1'b0),
.hps_0_spim0_ss_0_n (GPIO_1[21]),
.hps_0_spim0_ss_1_n (),
.hps_0_spim0_ss_2_n (),
.hps_0_spim0_ss_3_n (),
.hps_0_spim0_sclk_out_clk (GPIO_1[15]),
// I2C - Keypad
.hps_0_i2c2_out_data (sda_o_e),
.hps_0_i2c2_sda (sda_o),
.hps_0_i2c2_clk_clk (scl_o_e),
.hps_0_i2c2_scl_in_clk (scl_o),
.ece453_0_gpio_in_export ({18'h0, KEY, SW}),
.ece453_0_gpio_out_export ({
GPIO_1[1], // DMX+
GPIO_1[3], // DMX-
GPIO_1[17], // LCD Command
GPIO_1[19], // LCD Reset
GPIO_1[9], // Cap Sense Reset
ece453_gpio_out_unused,
ece453_leds // Red LEDs+
}),
//=====================================================================================//
// ECE 453 END
//=====================================================================================//
);
// Source/Probe megawizard instance
hps_reset hps_reset_inst (
.source_clk (fpga_clk_50),
.source (hps_reset_req)
);
altera_edge_detector pulse_cold_reset (
.clk (fpga_clk_50),
.rst_n (hps_fpga_reset_n),
.signal_in (hps_reset_req[0]),
.pulse_out (hps_cold_reset)
);
defparam pulse_cold_reset.PULSE_EXT = 6;
defparam pulse_cold_reset.EDGE_TYPE = 1;
defparam pulse_cold_reset.IGNORE_RST_WHILE_BUSY = 1;
altera_edge_detector pulse_warm_reset (
.clk (fpga_clk_50),
.rst_n (hps_fpga_reset_n),
.signal_in (hps_reset_req[1]),
.pulse_out (hps_warm_reset)
);
defparam pulse_warm_reset.PULSE_EXT = 2;
defparam pulse_warm_reset.EDGE_TYPE = 1;
defparam pulse_warm_reset.IGNORE_RST_WHILE_BUSY = 1;
altera_edge_detector pulse_debug_reset (
.clk (fpga_clk_50),
.rst_n (hps_fpga_reset_n),
.signal_in (hps_reset_req[2]),
.pulse_out (hps_debug_reset)
);
defparam pulse_debug_reset.PULSE_EXT = 32;
defparam pulse_debug_reset.EDGE_TYPE = 1;
defparam pulse_debug_reset.IGNORE_RST_WHILE_BUSY = 1;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
// clock and resets
sys_clk,
sys_resetn,
// ddr3
ddr3_a,
ddr3_ba,
ddr3_clk_p,
ddr3_clk_n,
ddr3_cke,
ddr3_cs_n,
ddr3_dm,
ddr3_ras_n,
ddr3_cas_n,
ddr3_we_n,
ddr3_reset_n,
ddr3_dq,
ddr3_dqs_p,
ddr3_dqs_n,
ddr3_odt,
ddr3_rzq,
// ethernet
eth_rx_clk,
eth_rx_data,
eth_rx_cntrl,
eth_tx_clk_out,
eth_tx_data,
eth_tx_cntrl,
eth_mdc,
eth_mdio_i,
eth_mdio_o,
eth_mdio_t,
eth_phy_resetn,
// board gpio
led_grn,
led_red,
push_buttons,
dip_switches,
// lane interface
ref_clk,
rx_data,
rx_sync,
rx_sysref,
// spi
spi_fout_enb_clk,
spi_fout_enb_mlo,
spi_fout_enb_rst,
spi_fout_enb_sync,
spi_fout_enb_sysref,
spi_fout_enb_trig,
spi_fout_clk,
spi_fout_sdio,
spi_afe_csn,
spi_afe_clk,
spi_afe_sdio,
spi_clk_csn,
spi_clk_clk,
spi_clk_sdio,
afe_rst,
afe_trig,
// gpio
dac_sleep,
dac_data,
afe_pdn,
afe_stby,
clk_resetn,
clk_syncn,
clk_status,
amp_disbn,
prc_sck,
prc_cnv,
prc_sdo_i,
prc_sdo_q);
// clock and resets
input sys_clk;
input sys_resetn;
// ddr3
output [ 13:0] ddr3_a;
output [ 2:0] ddr3_ba;
output ddr3_clk_p;
output ddr3_clk_n;
output ddr3_cke;
output ddr3_cs_n;
output [ 7:0] ddr3_dm;
output ddr3_ras_n;
output ddr3_cas_n;
output ddr3_we_n;
output ddr3_reset_n;
inout [ 63:0] ddr3_dq;
inout [ 7:0] ddr3_dqs_p;
inout [ 7:0] ddr3_dqs_n;
output ddr3_odt;
input ddr3_rzq;
// ethernet
input eth_rx_clk;
input [ 3:0] eth_rx_data;
input eth_rx_cntrl;
output eth_tx_clk_out;
output [ 3:0] eth_tx_data;
output eth_tx_cntrl;
output eth_mdc;
input eth_mdio_i;
output eth_mdio_o;
output eth_mdio_t;
output eth_phy_resetn;
// board gpio
output [ 7:0] led_grn;
output [ 7:0] led_red;
input [ 2:0] push_buttons;
input [ 7:0] dip_switches;
// lane interface
input ref_clk;
input [ 7:0] rx_data;
output rx_sysref;
output rx_sync;
// spi
output spi_fout_enb_clk;
output spi_fout_enb_mlo;
output spi_fout_enb_rst;
output spi_fout_enb_sync;
output spi_fout_enb_sysref;
output spi_fout_enb_trig;
output spi_fout_clk;
output spi_fout_sdio;
output [ 3:0] spi_afe_csn;
output spi_afe_clk;
inout spi_afe_sdio;
output spi_clk_csn;
output spi_clk_clk;
inout spi_clk_sdio;
output afe_rst;
output afe_trig;
// gpio
output dac_sleep;
output [ 13:0] dac_data;
output afe_pdn;
output afe_stby;
output clk_resetn;
output clk_syncn;
input clk_status;
output amp_disbn;
inout prc_sck;
inout prc_cnv;
inout prc_sdo_i;
inout prc_sdo_q;
// internal registers
reg rx_sysref_m1 = 'd0;
reg rx_sysref_m2 = 'd0;
reg rx_sysref_m3 = 'd0;
reg rx_sysref = 'd0;
reg dma_sync = 'd0;
reg dma_wr = 'd0;
reg adc_dovf;
reg [511:0] dma_data = 'd0;
reg rx_sof_0_s = 'd0;
reg rx_sof_1_s = 'd0;
reg rx_sof_2_s = 'd0;
reg rx_sof_3_s = 'd0;
reg [ 3:0] phy_rst_cnt = 0;
reg phy_rst_reg = 0;
// internal clocks and resets
wire sys_125m_clk;
wire sys_25m_clk;
wire sys_2m5_clk;
wire eth_tx_clk;
wire rx_clk;
wire adc_clk;
// internal signals
wire sys_pll_locked_s;
wire eth_tx_reset_s;
wire eth_tx_mode_1g_s;
wire eth_tx_mode_10m_100m_n_s;
wire [ 4:0] spi_csn;
wire spi_clk;
wire spi_mosi;
wire spi_miso;
wire rx_ref_clk;
wire rx_sync;
wire [127:0] adc_data_0;
wire [127:0] adc_data_1;
wire [127:0] adc_data_2;
wire [127:0] adc_data_3;
wire adc_valid;
wire [ 7:0] adc_valid_0;
wire [ 7:0] adc_valid_1;
wire [ 7:0] adc_valid_2;
wire [ 7:0] adc_valid_3;
wire [ 7:0] adc_enable_0;
wire [ 7:0] adc_enable_1;
wire [ 7:0] adc_enable_2;
wire [ 7:0] adc_enable_3;
wire adc_dovf_0;
wire adc_dovf_1;
wire adc_dovf_2;
wire adc_dovf_3;
wire [ 3:0] rx_ip_sof_s;
wire [255:0] rx_ip_data_s;
wire [255:0] rx_data_s;
wire rx_sw_rstn_s;
wire rx_sysref_s;
wire rx_err_s;
wire rx_ready_s;
wire [ 3:0] rx_rst_state_s;
wire rx_lane_aligned_s;
wire [ 7:0] rx_analog_reset_s;
wire [ 7:0] rx_digital_reset_s;
wire [ 7:0] rx_cdr_locked_s;
wire [ 7:0] rx_cal_busy_s;
wire rx_pll_locked_s;
wire [ 22:0] rx_xcvr_status_s;
wire [ 7:0] rx_sof;
wire [ 3:0] sync_raddr;
wire sync_signal;
// ethernet transmit clock
assign eth_tx_clk = (eth_tx_mode_1g_s == 1'b1) ? sys_125m_clk :
(eth_tx_mode_10m_100m_n_s == 1'b0) ? sys_25m_clk : sys_2m5_clk;
assign eth_phy_resetn = phy_rst_reg;
always@ (posedge eth_mdc) begin
phy_rst_cnt <= phy_rst_cnt + 4'd1;
if (phy_rst_cnt == 4'h0) begin
phy_rst_reg <= sys_pll_locked_s;
end
end
altddio_out #(.width(1)) i_eth_tx_clk_out (
.aset (1'b0),
.sset (1'b0),
.sclr (1'b0),
.oe (1'b1),
.oe_out (),
.datain_h (1'b1),
.datain_l (1'b0),
.outclocken (1'b1),
.aclr (eth_tx_reset_s),
.outclock (eth_tx_clk),
.dataout (eth_tx_clk_out));
assign eth_tx_reset_s = ~sys_pll_locked_s;
always @(posedge adc_clk) begin
dma_sync <= 1'b1;
dma_wr <= (|adc_enable_0)| (| adc_enable_1) | (|adc_enable_2) | (|adc_enable_3);
dma_data <= {adc_data_3, adc_data_2, adc_data_1, adc_data_0};
adc_dovf <= adc_dovf_3 | adc_dovf_2 | adc_dovf_1 | adc_dovf_0;
end
always @(posedge rx_clk) begin
rx_sysref_m1 <= rx_sysref_s;
rx_sysref_m2 <= rx_sysref_m1;
rx_sysref_m3 <= rx_sysref_m2;
rx_sysref <= rx_sysref_m2 & ~rx_sysref_m3;
end
sld_signaltap #(
.sld_advanced_trigger_entity ("basic,1,"),
.sld_data_bits (514),
.sld_data_bit_cntr_bits (8),
.sld_enable_advanced_trigger (0),
.sld_mem_address_bits (10),
.sld_node_crc_bits (32),
.sld_node_crc_hiword (10311),
.sld_node_crc_loword (14297),
.sld_node_info (1076736),
.sld_ram_block_type ("AUTO"),
.sld_sample_depth (1024),
.sld_storage_qualifier_gap_record (0),
.sld_storage_qualifier_mode ("OFF"),
.sld_trigger_bits (2),
.sld_trigger_in_enabled (0),
.sld_trigger_level (1),
.sld_trigger_level_pipeline (1))
i_signaltap (
.acq_clk (adc_clk),
.acq_data_in ({rx_sysref, rx_sync, dma_data}),
.acq_trigger_in ({rx_sysref, rx_sync}));
genvar n;
generate
for (n = 0; n < 8; n = n + 1) begin: g_align_1
ad_jesd_align i_jesd_align (
.rx_clk (rx_clk),
.rx_ip_sof (rx_ip_sof_s),
.rx_ip_data (rx_ip_data_s[n*32+31:n*32]),
.rx_sof (rx_sof[n]),
.rx_data (rx_data_s[n*32+31:n*32]));
end
endgenerate
assign rx_xcvr_status_s[22:22] = rx_sync;
assign rx_xcvr_status_s[21:21] = rx_ready_s;
assign rx_xcvr_status_s[20:20] = rx_pll_locked_s;
assign rx_xcvr_status_s[19:16] = rx_rst_state_s;
assign rx_xcvr_status_s[15: 8] = rx_cdr_locked_s;
assign rx_xcvr_status_s[ 7: 0] = rx_cal_busy_s;
ad_xcvr_rx_rst #(.NUM_OF_LANES (8)) i_xcvr_rx_rst (
.rx_clk (rx_clk),
.rx_rstn (sys_resetn),
.rx_sw_rstn (rx_sw_rstn_s),
.rx_pll_locked (rx_pll_locked_s),
.rx_cal_busy (rx_cal_busy_s),
.rx_cdr_locked (rx_cdr_locked_s),
.rx_analog_reset (rx_analog_reset_s),
.rx_digital_reset (rx_digital_reset_s),
.rx_ready (rx_ready_s),
.rx_rst_state (rx_rst_state_s));
assign spi_fout_enb_clk = 1'b0;
assign spi_fout_enb_mlo = 1'b0;
assign spi_fout_enb_rst = 1'b0;
assign spi_fout_enb_sync = 1'b0;
assign spi_fout_enb_sysref = 1'b0;
assign spi_fout_enb_trig = 1'b0;
assign spi_fout_clk = 1'b0;
assign spi_fout_sdio = 1'b0;
assign spi_afe_csn = spi_csn[ 4: 1];
assign spi_clk_csn = spi_csn[ 0: 0];
assign spi_afe_clk = spi_clk;
assign spi_clk_clk = spi_clk;
always @(posedge rx_clk)
begin
rx_sof_0_s <= rx_sof[0] | rx_sof[1];
rx_sof_1_s <= rx_sof[2] | rx_sof[3];
rx_sof_2_s <= rx_sof[4] | rx_sof[5];
rx_sof_3_s <= rx_sof[6] | rx_sof[7];
end
usdrx1_spi i_spi (
.spi_afe_csn (spi_csn[4:1]),
.spi_clk_csn (spi_csn[0]),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi),
.spi_miso (spi_miso),
.spi_afe_sdio (spi_afe_sdio),
.spi_clk_sdio (spi_clk_sdio));
system_bd i_system_bd (
.sys_clk_clk (sys_clk),
.sys_reset_reset_n (sys_resetn),
.sys_125m_clk_clk (sys_125m_clk),
.sys_25m_clk_clk (sys_25m_clk),
.sys_2m5_clk_clk (sys_2m5_clk),
.sys_pll_locked_export (sys_pll_locked_s),
.sys_ddr3_phy_mem_a (ddr3_a),
.sys_ddr3_phy_mem_ba (ddr3_ba),
.sys_ddr3_phy_mem_ck (ddr3_clk_p),
.sys_ddr3_phy_mem_ck_n (ddr3_clk_n),
.sys_ddr3_phy_mem_cke (ddr3_cke),
.sys_ddr3_phy_mem_cs_n (ddr3_cs_n),
.sys_ddr3_phy_mem_dm (ddr3_dm),
.sys_ddr3_phy_mem_ras_n (ddr3_ras_n),
.sys_ddr3_phy_mem_cas_n (ddr3_cas_n),
.sys_ddr3_phy_mem_we_n (ddr3_we_n),
.sys_ddr3_phy_mem_reset_n (ddr3_reset_n),
.sys_ddr3_phy_mem_dq (ddr3_dq),
.sys_ddr3_phy_mem_dqs (ddr3_dqs_p),
.sys_ddr3_phy_mem_dqs_n (ddr3_dqs_n),
.sys_ddr3_phy_mem_odt (ddr3_odt),
.sys_ddr3_oct_rzqin (ddr3_rzq),
.sys_ethernet_tx_clk_clk (eth_tx_clk),
.sys_ethernet_rx_clk_clk (eth_rx_clk),
.sys_ethernet_status_set_10 (),
.sys_ethernet_status_set_1000 (),
.sys_ethernet_status_eth_mode (eth_tx_mode_1g_s),
.sys_ethernet_status_ena_10 (eth_tx_mode_10m_100m_n_s),
.sys_ethernet_rgmii_rgmii_in (eth_rx_data),
.sys_ethernet_rgmii_rgmii_out (eth_tx_data),
.sys_ethernet_rgmii_rx_control (eth_rx_cntrl),
.sys_ethernet_rgmii_tx_control (eth_tx_cntrl),
.sys_ethernet_mdio_mdc (eth_mdc),
.sys_ethernet_mdio_mdio_in (eth_mdio_i),
.sys_ethernet_mdio_mdio_out (eth_mdio_o),
.sys_ethernet_mdio_mdio_oen (eth_mdio_t),
.sys_gpio_in_port ({25'h0, clk_status, 6'h0 }),
.sys_gpio_out_port ({3'h0, rx_sysref_s,
rx_sw_rstn_s, dac_data, dac_sleep,
1'b0, 1'b0, 1'b0, 1'b0,
amp_disbn, 1'b0, clk_syncn, clk_resetn,
afe_stby, afe_pdn, afe_trig, afe_rst}),
.sys_spi_MISO (spi_miso),
.sys_spi_MOSI (spi_mosi),
.sys_spi_SCLK (spi_clk),
.sys_spi_SS_n (spi_csn),
.axi_dmac_if_fifo_wr_clk_clk (adc_clk),
.axi_dmac_if_fifo_wr_overflow_adc_dovf (adc_dovf),
.axi_dmac_if_fifo_wr_en_adc_valid (dma_wr),
.axi_dmac_if_fifo_wr_din_adc_data (dma_data),
.axi_dmac_if_fifo_wr_sync_adc_sync (dma_sync),
.sys_jesd204b_s1_rx_link_data (rx_ip_data_s),
.sys_jesd204b_s1_rx_link_valid (),
.sys_jesd204b_s1_rx_link_ready (1'b1),
.sys_jesd204b_s1_lane_aligned_all_export (rx_lane_aligned_s),
.sys_jesd204b_s1_sysref_export (rx_sysref),
.sys_jesd204b_s1_rx_ferr_export (rx_err_s),
.sys_jesd204b_s1_lane_aligned_export (rx_lane_aligned_s),
.sys_jesd204b_s1_sync_n_export (rx_sync),
.sys_jesd204b_s1_rx_sof_export (rx_ip_sof_s),
.sys_jesd204b_s1_rx_xcvr_data_rx_serial_data (rx_data),
.sys_jesd204b_s1_rx_analogreset_rx_analogreset (rx_analog_reset_s),
.sys_jesd204b_s1_rx_digitalreset_rx_digitalreset (rx_digital_reset_s),
.sys_jesd204b_s1_locked_rx_is_lockedtodata (rx_cdr_locked_s),
.sys_jesd204b_s1_rx_cal_busy_rx_cal_busy (rx_cal_busy_s),
.sys_jesd204b_s1_ref_clk_clk (ref_clk),
.sys_jesd204b_s1_rx_clk_clk (rx_clk),
.sys_jesd204b_s1_pll_locked_export (rx_pll_locked_s),
.axi_ad9671_0_xcvr_clk_clk (rx_clk),
.axi_ad9671_0_xcvr_data_data (rx_data_s[63:0]),
.axi_ad9671_0_xcvr_data_data_sof(rx_sof_0_s),
.axi_ad9671_0_adc_clock_clk (adc_clk),
.axi_ad9671_0_adc_dma_if_valid (adc_valid_0),
.axi_ad9671_0_adc_dma_if_enable (adc_enable_0),
.axi_ad9671_0_adc_dma_if_data (adc_data_0),
.axi_ad9671_0_adc_dma_if_dovf (adc_dovf_0),
.axi_ad9671_0_adc_dma_if_dunf (1'b0),
.axi_ad9671_1_xcvr_clk_clk (rx_clk),
.axi_ad9671_1_xcvr_data_data (rx_data_s[127:64]),
.axi_ad9671_1_xcvr_data_data_sof(rx_sof_1_s),
.axi_ad9671_1_adc_clock_clk (),
.axi_ad9671_1_adc_dma_if_valid (adc_valid_1),
.axi_ad9671_1_adc_dma_if_enable (adc_enable_1),
.axi_ad9671_1_adc_dma_if_data (adc_data_1),
.axi_ad9671_1_adc_dma_if_dovf (adc_dovf_1),
.axi_ad9671_1_adc_dma_if_dunf (1'b0),
.axi_ad9671_2_xcvr_clk_clk (rx_clk),
.axi_ad9671_2_xcvr_data_data (rx_data_s[191:128]),
.axi_ad9671_2_xcvr_data_data_sof(rx_sof_2_s),
.axi_ad9671_2_adc_clock_clk (),
.axi_ad9671_2_adc_dma_if_valid (adc_valid_2),
.axi_ad9671_2_adc_dma_if_enable (adc_enable_2),
.axi_ad9671_2_adc_dma_if_data (adc_data_2),
.axi_ad9671_2_adc_dma_if_dovf (adc_dovf_2),
.axi_ad9671_2_adc_dma_if_dunf (1'b0),
.axi_ad9671_3_xcvr_clk_clk (rx_clk),
.axi_ad9671_3_xcvr_data_data (rx_data_s[255:192]),
.axi_ad9671_3_xcvr_data_data_sof(rx_sof_3_s),
.axi_ad9671_3_adc_clock_clk (),
.axi_ad9671_3_adc_dma_if_valid (adc_valid_3),
.axi_ad9671_3_adc_dma_if_enable (adc_enable_3),
.axi_ad9671_3_adc_dma_if_data (adc_data_3),
.axi_ad9671_3_adc_dma_if_dovf (adc_dovf_3),
.axi_ad9671_3_adc_dma_if_dunf (1'b0),
.axi_ad9671_0_xcvr_sync_sync_in (),
.axi_ad9671_0_xcvr_sync_sync_out (sync_signal),
.axi_ad9671_0_xcvr_sync_raddr_in (),
.axi_ad9671_0_xcvr_sync_raddr_out (sync_raddr),
.axi_ad9671_1_xcvr_sync_sync_in (sync_signal),
.axi_ad9671_1_xcvr_sync_sync_out (),
.axi_ad9671_1_xcvr_sync_raddr_in (sync_raddr),
.axi_ad9671_1_xcvr_sync_raddr_out(),
.axi_ad9671_2_xcvr_sync_sync_in (sync_signal),
.axi_ad9671_2_xcvr_sync_sync_out (),
.axi_ad9671_2_xcvr_sync_raddr_in (sync_raddr),
.axi_ad9671_2_xcvr_sync_raddr_out (),
.axi_ad9671_3_xcvr_sync_sync_in (sync_signal),
.axi_ad9671_3_xcvr_sync_sync_out (),
.axi_ad9671_3_xcvr_sync_raddr_in (sync_raddr),
.axi_ad9671_3_xcvr_sync_raddr_out ());
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR2_FUNCTIONAL_V
`define SKY130_FD_SC_HS__OR2_FUNCTIONAL_V
/**
* or2: 2-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__or2 (
VPWR,
VGND,
X ,
A ,
B
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
// Local signals
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR2_FUNCTIONAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:21:14 08/24/2011
// Design Name:
// Module Name: q15_mult
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module qmult #(
//Parameterized values
parameter Q = 15,
parameter N = 32
)
(
input [N-1:0] i_multiplicand,
input [N-1:0] i_multiplier,
output [N-1:0] o_result,
output reg ovr
);
// The underlying assumption, here, is that both fixed-point values are of the same length (N,Q)
// Because of this, the results will be of length N+N = 2N bits....
// This also simplifies the hand-back of results, as the binimal point
// will always be in the same location...
reg [2*N-1:0] r_result; // Multiplication by 2 values of N bits requires a
// register that is N+N = 2N deep...
reg [N-1:0] r_RetVal;
//--------------------------------------------------------------------------------
assign o_result = r_RetVal; // Only handing back the same number of bits as we received...
// with fixed point in same location...
//---------------------------------------------------------------------------------
always @(i_multiplicand, i_multiplier) begin // Do the multiply any time the inputs change
r_result <= i_multiplicand[N-2:0] * i_multiplier[N-2:0]; // Removing the sign bits from the multiply - that
// would introduce *big* errors
ovr <= 1'b0; // reset overflow flag to zero
end
// This always block will throw a warning, as it uses a & b, but only acts on changes in result...
always @(r_result) begin // Any time the result changes, we need to recompute the sign bit,
r_RetVal[N-1] <= i_multiplicand[N-1] ^ i_multiplier[N-1]; // which is the XOR of the input sign bits... (you do the truth table...)
r_RetVal[N-2:0] <= r_result[N-2+Q:Q]; // And we also need to push the proper N bits of result up to
// the calling entity...
if (r_result[2*N-2:N-1+Q] > 0) // And finally, we need to check for an overflow
ovr <= 1'b1;
end
endmodule
|
// file: clk25_2_X.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___100.000______0.000______50.0______226.965____237.727
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary______________25____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "clk25_2_X,clk_wiz_v3_6,{component_name=clk25_2_X,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=1,clkin1_period=40.000,clkin2_period=10.0,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
module clk25_2_X
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
// Status and control signals
input RESET
);
// Input buffering
//------------------------------------
//IBUFG clkin1_buf
// (.O (clkin1),
// .I (CLK_IN1));
assign clkin1 = CLK_IN1;
// Clocking primitive
//------------------------------------
// Instantiation of the MMCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_unused;
wire clkfbout;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
/*
freq M D
161 38.75 6
168 38.75 5.75
167 38.5 5.75
92 39.75 10.75
123 39.5 8
*/
localparam real MULT = 38.75;
localparam real DIV = 6.0;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (MULT),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (DIV),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (40.000),
.REF_JITTER1 (0.010))
mmcm_adv_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clkout0),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clkout1_unused),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clkout2_unused),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout),
.CLKIN1 (clkin1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_unused),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (RESET));
// Output buffering
//-----------------------------------
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkout0));
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Fri Jan 13 17:33:47 2017
// Host : KLight-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_pole/bg_pole_sim_netlist.v
// Design : bg_pole
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "bg_pole,blk_mem_gen_v8_3_5,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_3_5,Vivado 2016.4" *)
(* NotValidForBitStream *)
module bg_pole
(clka,
wea,
addra,
dina,
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [6:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [11:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [11:0]douta;
wire [6:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire [11:0]NLW_U0_doutb_UNCONNECTED;
wire [6:0]NLW_U0_rdaddrecc_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [6:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
wire [11:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
(* C_ADDRA_WIDTH = "7" *)
(* C_ADDRB_WIDTH = "7" *)
(* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "0" *)
(* C_CTRL_ECC_ALGO = "NONE" *)
(* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *)
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
(* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *)
(* C_EN_DEEPSLEEP_PIN = "0" *)
(* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *)
(* C_EN_RDADDRB_CHG = "0" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *)
(* C_EN_SLEEP_PIN = "0" *)
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.7064499999999998 mW" *)
(* C_FAMILY = "artix7" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *)
(* C_HAS_INJECTERR = "0" *)
(* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *)
(* C_HAS_REGCEB = "0" *)
(* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *)
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *)
(* C_INITB_VAL = "0" *)
(* C_INIT_FILE = "bg_pole.mem" *)
(* C_INIT_FILE_NAME = "bg_pole.mif" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *)
(* C_MUX_PIPELINE_STAGES = "0" *)
(* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "104" *)
(* C_READ_DEPTH_B = "104" *)
(* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *)
(* C_RSTRAM_A = "0" *)
(* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "104" *)
(* C_WRITE_DEPTH_B = "104" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "12" *)
(* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *)
(* downgradeipidentifiedwarnings = "yes" *)
bg_pole_blk_mem_gen_v8_3_5 U0
(.addra(addra),
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.clka(clka),
.clkb(1'b0),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.deepsleep(1'b0),
.dina(dina),
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.douta(douta),
.doutb(NLW_U0_doutb_UNCONNECTED[11:0]),
.eccpipece(1'b0),
.ena(1'b0),
.enb(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[6:0]),
.regcea(1'b0),
.regceb(1'b0),
.rsta(1'b0),
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
.rstb(1'b0),
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
.s_aclk(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
.s_axi_injectdbiterr(1'b0),
.s_axi_injectsbiterr(1'b0),
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[6:0]),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[11:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
module bg_pole_blk_mem_gen_generic_cstr
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [6:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [6:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
bg_pole_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
module bg_pole_blk_mem_gen_prim_width
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [6:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [6:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
bg_pole_blk_mem_gen_prim_wrapper_init \prim_init.ram
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper_init" *)
module bg_pole_blk_mem_gen_prim_wrapper_init
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [6:0]addra;
input [11:0]dina;
input [0:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_0 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_1 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_10 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_11 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_12 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_16 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_17 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_18 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_19 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_2 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_20 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_24 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_25 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_26 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_27 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_28 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_3 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_4 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_8 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_9 ;
wire [6:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
(* CLOCK_DOMAINS = "COMMON" *)
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
.DOA_REG(1),
.DOB_REG(1),
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_00(256'h0000000006050607040603010000000000000000030506070706010000000000),
.INIT_01(256'h0000020007060100040603010000000000000000060506070706010000000000),
.INIT_02(256'h0000000004060301070601000004000000000000060506070406030100000000),
.INIT_03(256'h0000000006050607040603010000000000000000030506070706010000000000),
.INIT_04(256'h0000000006050607070601000000000000000000050606060406030100040000),
.INIT_05(256'h0000000004060301070601000004000000000000060506070406030100000000),
.INIT_06(256'h0000000003050607070601000000000000000000060506070406030100040000),
.INIT_07(256'h0000000006050607070601000000000000000000050606060406030100040000),
.INIT_08(256'h0000000006050607040603010000000000000200070601000406030100000000),
.INIT_09(256'h0000000003050607070601000000000000000000060506070406030100040000),
.INIT_0A(256'h0000000005060606040603010004000000000000060506070406030100000000),
.INIT_0B(256'h0000000006050607040603010000000000000200070601000406030100000000),
.INIT_0C(256'h0000000006050607040603010004000000000000040603010706010000040000),
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(18'h00000),
.INIT_B(18'h00000),
.INIT_FILE("NONE"),
.IS_CLKARDCLK_INVERTED(1'b0),
.IS_CLKBWRCLK_INVERTED(1'b0),
.IS_ENARDEN_INVERTED(1'b0),
.IS_ENBWREN_INVERTED(1'b0),
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
.IS_RSTRAMB_INVERTED(1'b0),
.IS_RSTREGARSTREG_INVERTED(1'b0),
.IS_RSTREGB_INVERTED(1'b0),
.RAM_MODE("TDP"),
.RDADDR_COLLISION_HWCONFIG("PERFORMANCE"),
.READ_WIDTH_A(18),
.READ_WIDTH_B(18),
.RSTREG_PRIORITY_A("REGCE"),
.RSTREG_PRIORITY_B("REGCE"),
.SIM_COLLISION_CHECK("ALL"),
.SIM_DEVICE("7SERIES"),
.SRVAL_A(18'h00000),
.SRVAL_B(18'h00000),
.WRITE_MODE_A("WRITE_FIRST"),
.WRITE_MODE_B("WRITE_FIRST"),
.WRITE_WIDTH_A(18),
.WRITE_WIDTH_B(18))
\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram
(.ADDRARDADDR({1'b0,1'b0,addra,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ADDRBWRADDR({1'b0,1'b0,addra,1'b1,1'b0,1'b0,1'b0,1'b0}),
.CLKARDCLK(clka),
.CLKBWRCLK(clka),
.DIADI({1'b0,1'b0,1'b0,1'b0,1'b0,dina[5:3],1'b0,1'b0,1'b0,1'b0,1'b0,dina[2:0]}),
.DIBDI({1'b0,1'b0,1'b0,1'b0,1'b0,dina[11:9],1'b0,1'b0,1'b0,1'b0,1'b0,dina[8:6]}),
.DIPADIP({1'b0,1'b0}),
.DIPBDIP({1'b0,1'b0}),
.DOADO({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_0 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_1 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_2 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_3 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_4 ,douta[5:3],\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_8 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_9 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_10 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_11 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_12 ,douta[2:0]}),
.DOBDO({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_16 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_17 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_18 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_19 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_20 ,douta[11:9],\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_24 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_25 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_26 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_27 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_28 ,douta[8:6]}),
.DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33 }),
.DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35 }),
.ENARDEN(1'b1),
.ENBWREN(1'b1),
.REGCEAREGCE(1'b1),
.REGCEB(1'b1),
.RSTRAMARSTRAM(1'b0),
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({wea,wea}),
.WEBWE({1'b0,1'b0,wea,wea}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
module bg_pole_blk_mem_gen_top
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [6:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [6:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
bg_pole_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* C_ADDRA_WIDTH = "7" *) (* C_ADDRB_WIDTH = "7" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "0" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 2.7064499999999998 mW" *)
(* C_FAMILY = "artix7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "0" *)
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "1" *)
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "bg_pole.mem" *)
(* C_INIT_FILE_NAME = "bg_pole.mif" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "1" *)
(* C_MEM_TYPE = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
(* C_READ_DEPTH_A = "104" *) (* C_READ_DEPTH_B = "104" *) (* C_READ_WIDTH_A = "12" *)
(* C_READ_WIDTH_B = "12" *) (* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *)
(* C_RST_PRIORITY_A = "CE" *) (* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *) (* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *)
(* C_USE_DEFAULT_DATA = "0" *) (* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *) (* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *)
(* C_WRITE_DEPTH_A = "104" *) (* C_WRITE_DEPTH_B = "104" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *)
(* C_WRITE_MODE_B = "WRITE_FIRST" *) (* C_WRITE_WIDTH_A = "12" *) (* C_WRITE_WIDTH_B = "12" *)
(* C_XDEVICEFAMILY = "artix7" *) (* ORIG_REF_NAME = "blk_mem_gen_v8_3_5" *) (* downgradeipidentifiedwarnings = "yes" *)
module bg_pole_blk_mem_gen_v8_3_5
(clka,
rsta,
ena,
regcea,
wea,
addra,
dina,
douta,
clkb,
rstb,
enb,
regceb,
web,
addrb,
dinb,
doutb,
injectsbiterr,
injectdbiterr,
eccpipece,
sbiterr,
dbiterr,
rdaddrecc,
sleep,
deepsleep,
shutdown,
rsta_busy,
rstb_busy,
s_aclk,
s_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
s_axi_injectsbiterr,
s_axi_injectdbiterr,
s_axi_sbiterr,
s_axi_dbiterr,
s_axi_rdaddrecc);
input clka;
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [6:0]addra;
input [11:0]dina;
output [11:0]douta;
input clkb;
input rstb;
input enb;
input regceb;
input [0:0]web;
input [6:0]addrb;
input [11:0]dinb;
output [11:0]doutb;
input injectsbiterr;
input injectdbiterr;
input eccpipece;
output sbiterr;
output dbiterr;
output [6:0]rdaddrecc;
input sleep;
input deepsleep;
input shutdown;
output rsta_busy;
output rstb_busy;
input s_aclk;
input s_aresetn;
input [3:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input s_axi_awvalid;
output s_axi_awready;
input [11:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
output [3:0]s_axi_bid;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [3:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input s_axi_arvalid;
output s_axi_arready;
output [3:0]s_axi_rid;
output [11:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output s_axi_rvalid;
input s_axi_rready;
input s_axi_injectsbiterr;
input s_axi_injectdbiterr;
output s_axi_sbiterr;
output s_axi_dbiterr;
output [6:0]s_axi_rdaddrecc;
wire \<const0> ;
wire [6:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
assign dbiterr = \<const0> ;
assign doutb[11] = \<const0> ;
assign doutb[10] = \<const0> ;
assign doutb[9] = \<const0> ;
assign doutb[8] = \<const0> ;
assign doutb[7] = \<const0> ;
assign doutb[6] = \<const0> ;
assign doutb[5] = \<const0> ;
assign doutb[4] = \<const0> ;
assign doutb[3] = \<const0> ;
assign doutb[2] = \<const0> ;
assign doutb[1] = \<const0> ;
assign doutb[0] = \<const0> ;
assign rdaddrecc[6] = \<const0> ;
assign rdaddrecc[5] = \<const0> ;
assign rdaddrecc[4] = \<const0> ;
assign rdaddrecc[3] = \<const0> ;
assign rdaddrecc[2] = \<const0> ;
assign rdaddrecc[1] = \<const0> ;
assign rdaddrecc[0] = \<const0> ;
assign rsta_busy = \<const0> ;
assign rstb_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[3] = \<const0> ;
assign s_axi_bid[2] = \<const0> ;
assign s_axi_bid[1] = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_dbiterr = \<const0> ;
assign s_axi_rdaddrecc[6] = \<const0> ;
assign s_axi_rdaddrecc[5] = \<const0> ;
assign s_axi_rdaddrecc[4] = \<const0> ;
assign s_axi_rdaddrecc[3] = \<const0> ;
assign s_axi_rdaddrecc[2] = \<const0> ;
assign s_axi_rdaddrecc[1] = \<const0> ;
assign s_axi_rdaddrecc[0] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[3] = \<const0> ;
assign s_axi_rid[2] = \<const0> ;
assign s_axi_rid[1] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_sbiterr = \<const0> ;
assign s_axi_wready = \<const0> ;
assign sbiterr = \<const0> ;
GND GND
(.G(\<const0> ));
bg_pole_blk_mem_gen_v8_3_5_synth inst_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_v8_3_5_synth" *)
module bg_pole_blk_mem_gen_v8_3_5_synth
(douta,
clka,
addra,
dina,
wea);
output [11:0]douta;
input clka;
input [6:0]addra;
input [11:0]dina;
input [0:0]wea;
wire [6:0]addra;
wire clka;
wire [11:0]dina;
wire [11:0]douta;
wire [0:0]wea;
bg_pole_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),
.clka(clka),
.dina(dina),
.douta(douta),
.wea(wea));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKINV_2_V
`define SKY130_FD_SC_HS__CLKINV_2_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkinv_2 (
Y ,
A ,
VPWR,
VGND
);
output Y ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__clkinv_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKINV_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EINVN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__EINVN_BEHAVIORAL_PP_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__einvn (
VPWR,
VGND,
Z ,
A ,
TE_B
);
// Module ports
input VPWR;
input VGND;
output Z ;
input A ;
input TE_B;
// Local signals
wire u_vpwr_vgnd0_out_A ;
wire u_vpwr_vgnd1_out_teb;
// Name Output Other arguments
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_A , A, VPWR, VGND );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_teb, TE_B, VPWR, VGND );
notif0 notif00 (Z , u_vpwr_vgnd0_out_A, u_vpwr_vgnd1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__EINVN_BEHAVIORAL_PP_V |
//======================================================================
//
// coretest_test_core.v
// --------------------
// Top level wrapper that creates the Cryptech coretest system.
// The wrapper contains instances of external interface, coretest
// and the core to be tested. And if more than one core is
// present the wrapper also includes address and data muxes.
//
// Author: Joachim Strombergson
// Copyright (c) 2014 Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
module coretest_test_core(
input wire clk,
input wire reset_n,
// External interface.
input wire rxd,
output wire txd,
output wire [7 : 0] debug
);
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter TEST_CORE_ADDR_PREFIX = 8'h01;
parameter UART_ADDR_PREFIX = 8'h02;
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
// Coretest connections.
wire coretest_reset_n;
wire coretest_cs;
wire coretest_we;
wire [15 : 0] coretest_address;
wire [31 : 0] coretest_write_data;
reg [31 : 0] coretest_read_data;
reg coretest_error;
// uart connections
wire uart_rxd_syn;
wire [7 : 0] uart_rxd_data;
wire uart_rxd_ack;
wire uart_txd_syn;
wire [7 : 0] uart_txd_data;
wire uart_txd_ack;
reg uart_cs;
reg uart_we;
reg [3 : 0] uart_address;
reg [31 : 0] uart_write_data;
wire [31 : 0] uart_read_data;
wire uart_error;
wire [7 : 0] uart_debug;
// test_core connections.
reg test_core_reset_n;
reg test_core_cs;
reg test_core_we;
reg [7 : 0] test_core_address;
reg [31 : 0] test_core_write_data;
wire [31 : 0] test_core_read_data;
wire test_core_error;
wire [7 : 0] test_core_debug;
//----------------------------------------------------------------
// Concurrent assignment.
//----------------------------------------------------------------
assign debug = test_core_debug;
//----------------------------------------------------------------
// Core instantiations.
//----------------------------------------------------------------
coretest coretest(
.clk(clk),
.reset_n(reset_n),
.rx_syn(uart_rxd_syn),
.rx_data(uart_rxd_data),
.rx_ack(uart_rxd_ack),
.tx_syn(uart_txd_syn),
.tx_data(uart_txd_data),
.tx_ack(uart_txd_ack),
// Interface to the core being tested.
.core_reset_n(coretest_reset_n),
.core_cs(coretest_cs),
.core_we(coretest_we),
.core_address(coretest_address),
.core_write_data(coretest_write_data),
.core_read_data(coretest_read_data),
.core_error(coretest_error)
);
uart uart(
.clk(clk),
.reset_n(reset_n),
.rxd(rxd),
.txd(txd),
.rxd_syn(uart_rxd_syn),
.rxd_data(uart_rxd_data),
.rxd_ack(uart_rxd_ack),
.txd_syn(uart_txd_syn),
.txd_data(uart_txd_data),
.txd_ack(uart_txd_ack),
.cs(uart_cs),
.we(uart_we),
.address(uart_address),
.write_data(uart_write_data),
.read_data(uart_read_data),
.error(uart_error),
.debug(uart_debug)
);
test_core test_core(
.clk(clk),
.reset_n(reset_n),
.cs(test_core_cs),
.we(test_core_we),
.address(test_core_address),
.write_data(test_core_write_data),
.read_data(test_core_read_data),
.error(test_core_error),
.debug(test_core_debug)
);
//----------------------------------------------------------------
// address_mux
//
// Combinational data mux that handles addressing between
// cores using the 32-bit memory like interface.
//----------------------------------------------------------------
always @*
begin : address_mux
// Default assignments.
coretest_read_data = 32'h00000000;
coretest_error = 0;
uart_cs = 0;
uart_we = 0;
uart_address = 4'h0;
uart_write_data = 32'h00000000;
test_core_reset_n = 1;
test_core_cs = 0;
test_core_we = 0;
test_core_address = 8'h00;
test_core_write_data = 32'h00000000;
case (coretest_address[15 : 8])
TEST_CORE_ADDR_PREFIX:
begin
test_core_reset_n = coretest_reset_n;
test_core_cs = coretest_cs;
test_core_we = coretest_we;
test_core_address = coretest_address[7 : 0];
test_core_write_data = coretest_write_data;
coretest_read_data = test_core_read_data;
coretest_error = test_core_error;
end
UART_ADDR_PREFIX:
begin
uart_cs = coretest_cs;
uart_we = coretest_we;
uart_address = coretest_address[3 : 0];
uart_write_data = coretest_write_data;
coretest_read_data = uart_read_data;
coretest_error = uart_error;
end
default:
begin
end
endcase // case (coretest_address[15 : 8])
end // address_mux
endmodule // coretest_test_core
//======================================================================
// EOF coretest_test_core.v
//======================================================================
|
module control(op, funct, mem_to_reg, mem_write, branch, alu_ctrl, alu_src, reg_dst, reg_write, jump) ;
input [5:0] funct;
input [5:0] op;
output [0:0] mem_to_reg, mem_write, branch, alu_src, reg_dst, reg_write, jump;
output [1:0] alu_ctrl;
reg [0:0] mem_to_reg, mem_write, branch, alu_src, reg_dst, reg_write, jump;
reg [1:0] alu_ctrl;
always @(*) begin
case(op)
// jump opcode
6'b000010: begin
jump = 1;
reg_write = 0;
mem_write = 0;
end
// R type op-code
6'b000000:
case(funct)
// we are an R instruction type
// what function are we?
// add funct
6'b100000: begin
reg_write = 1;
reg_dst = 1;
alu_src = 0;
branch = 0;
mem_write = 0;
alu_ctrl = 2'b01;
jump = 0;
end
// sub funct
6'b100010: begin
reg_write = 1;
reg_dst = 1;
alu_src = 0;
branch = 0;
mem_write = 0;
alu_ctrl = 2'b10;
jump = 0;
end
endcase
// I type OP codes
// Addi
6'b001000: begin
reg_write = 1;
reg_dst = 0;
alu_src = 1;
alu_ctrl = 2'b01;
branch = 0;
mem_write = 0;
mem_to_reg = 0;
jump = 0;
end
// lw
6'b100011: begin
reg_write = 1;
reg_dst = 0;
alu_src = 1;
branch = 0;
mem_write = 0;
mem_to_reg = 1;
alu_ctrl = 2'b01;
jump = 0;
end
// sw
6'b101011: begin
reg_write = 0;
alu_src = 1;
branch = 0;
mem_write = 1;
alu_ctrl = 2'b01;
jump = 0;
end
// beq
6'b000100: begin
reg_write = 0;
alu_src = 0;
branch = 1;
mem_write = 0;
alu_ctrl = 2'b00;
jump = 0;
end
endcase
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CONB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__CONB_BEHAVIORAL_PP_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_p/sky130_fd_sc_ms__udp_pwrgood_pp_p.v"
`include "../../models/udp_pwrgood_pp_g/sky130_fd_sc_ms__udp_pwrgood_pp_g.v"
`celldefine
module sky130_fd_sc_ms__conb (
HI ,
LO ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output HI ;
output LO ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pullup0_out_HI ;
wire pulldown0_out_LO;
// Name Output Other arguments
pullup pullup0 (pullup0_out_HI );
sky130_fd_sc_ms__udp_pwrgood_pp$P pwrgood_pp0 (HI , pullup0_out_HI, VPWR );
pulldown pulldown0 (pulldown0_out_LO);
sky130_fd_sc_ms__udp_pwrgood_pp$G pwrgood_pp1 (LO , pulldown0_out_LO, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__CONB_BEHAVIORAL_PP_V |
module reg_256x32b_3r_1w
(/*AUTOARG*/
// Outputs
rd0_data, rd1_data, rd2_data,
// Inputs
clk, rd0_addr, rd1_addr, rd2_addr, wr0_addr, wr0_en, wr0_data
);
input clk;
output [31:0] rd0_data;
output [31:0] rd1_data;
output [31:0] rd2_data;
input [9:0] rd0_addr;
input [9:0] rd1_addr;
input [9:0] rd2_addr;
input [9:0] wr0_addr;
input wr0_en;
input [31:0] wr0_data;
wire [32767:0] word_out; //32 x 1024 depth is 32768 - 1
wire [32767:0] word_in;
wire [1023:0] wr_en_word;
wire [1023:0] wr0_word_select; //changed from 255 to 1023 (1024 select)
wire [31:0] rd0_data_i;
wire [31:0] rd1_data_i;
wire [31:0] rd2_data_i;
//Register file
flop_32b word[1023:0](.out(word_out), .in(word_in), .wr_en(wr_en_word), .clk(clk)); //actually 1024 flops
//Muxes for read ports ***ALL 1024 x 32b MUX
mux_256x32b_to_1x32b mux_rd_port_0
(.out(rd0_data_i),
.in(word_out),
.select(rd0_addr));
mux_256x32b_to_1x32b mux_rd_port_1
(.out(rd1_data_i),
.in(word_out),
.select(rd1_addr));
mux_256x32b_to_1x32b mux_rd_port_2
(.out(rd2_data_i),
.in(word_out),
.select(rd2_addr));
//Write port logic
decoder_param #(10,1024) decoder_wr_port_0
(.out(wr0_word_select),
.in(wr0_addr));
assign wr_en_word = {1024{wr0_en}} & wr0_word_select;
assign word_in = {1024{wr0_data}};
// Output flop on the read ports.
dff_en rd_port_0_out_flop[31:0]
(.q(rd0_data),
.d(rd0_data_i),
.en(1'b1),
.clk(clk),
.rst(1'b0));
dff_en rd_port_1_out_flop[31:0]
(.q(rd1_data),
.d(rd1_data_i),
.en(1'b1),
.clk(clk),
.rst(1'b0));
dff_en rd_port_2_out_flop[31:0]
(.q(rd2_data),
.d(rd2_data_i),
.en(1'b1),
.clk(clk),
.rst(1'b0));
/* // For now disable this flop
assign rd0_data = rd0_data_i;
assign rd1_data = rd1_data_i;
assign rd2_data = rd2_data_i;*/
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__AND4B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__AND4B_BEHAVIORAL_PP_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__and4b (
VPWR,
VGND,
X ,
A_N ,
B ,
C ,
D
);
// Module ports
input VPWR;
input VGND;
output X ;
input A_N ;
input B ;
input C ;
input D ;
// Local signals
wire D not0_out ;
wire and0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B, C, D );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__AND4B_BEHAVIORAL_PP_V |
// file: timer_exdes.v
//
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard example design
//----------------------------------------------------------------------------
// This example design instantiates the created clocking network, where each
// output clock drives a counter. The high bit of each counter is ported.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
module timer_exdes
#(
parameter TCQ = 100
)
(// Clock in ports
input CLK_IN1,
// Reset that only drives logic in example design
input COUNTER_RESET,
// High bits of counters driven by clocks
output [2:1] COUNT
);
// Parameters for the counters
//-------------------------------
// Counter width
localparam C_W = 16;
// Number of counters
localparam NUM_C = 2;
genvar count_gen;
// Create reset for the counters
wire reset_int = COUNTER_RESET;
// Declare the clocks and counters
wire [NUM_C:1] clk_int;
wire [NUM_C:1] clk;
reg [C_W-1:0] counter [NUM_C:1];
// Instantiation of the clocking network
//--------------------------------------
timer clknetwork
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Clock out ports
.CLK_OUT1 (clk_int[1]),
.CLK_OUT2 (clk_int[2]));
// Connect the output clocks to the design
//-----------------------------------------
assign clk[1] = clk_int[1];
assign clk[2] = clk_int[2];
// Output clock sampling
//-----------------------------------
generate for (count_gen = 1; count_gen <= NUM_C; count_gen = count_gen + 1) begin: counters
always @(posedge clk[count_gen]) begin
if (reset_int) begin
counter[count_gen] <= #TCQ { C_W { 1'b 0 } };
end else begin
counter[count_gen] <= #TCQ counter[count_gen] + 1'b 1;
end
end
// alias the high bit of each counter to the corresponding
// bit in the output bus
assign COUNT[count_gen] = counter[count_gen][C_W-1];
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:57:12 11/07/2014
// Design Name:
// Module Name: top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module top(
clock,
a1,
a2,
store000_out,
store001_out,
store010_out,
store100_out,
store101_out,
store110_out,
cout1,
cout2,
cout3,
cout4,
cout5,
cout6
);
parameter NUM_BITS = 5;
//-------------------------------------------------------------------------------
input clock;
input [NUM_BITS-1:0] a1;
input [NUM_BITS-1:0] a2;
//-------------------------------------------------------------------------------
output [3:0] store000_out;
output [3:0] store001_out;
output [3:0] store010_out;
output [3:0] store100_out;
output [3:0] store101_out;
output [3:0] store110_out;
wire [3:0] store000_0;
wire [3:0] store001_0;
wire [3:0] store010_0;
wire [3:0] store100_0;
wire [3:0] store101_0;
wire [3:0] store110_0;
wire [3:0] store000_1;
wire [3:0] store001_1;
wire [3:0] store010_1;
wire [3:0] store100_1;
wire [3:0] store101_1;
wire [3:0] store110_1;
output wire [1:0] cout1;
output wire [1:0] cout2;
output wire [1:0] cout3;
output wire [1:0] cout4;
output wire [1:0] cout5;
output wire [1:0] cout6;
temp dbns1(
.clock(clock),
.a(a1),
.store000(store000_0),
.store001(store001_0),
.store010(store010_0),
.store100(store100_0),
.store101(store101_0),
.store110(store110_0)
);
temp dbns2(
.clock(clock),
.a(a2),
.store000(store000_1),
.store001(store001_1),
.store010(store010_1),
.store100(store100_1),
.store101(store101_1),
.store110(store110_1)
);
addititon addn_1(
.store000_0(store000_0),
.store001_0(store001_0),
.store010_0(store010_0),
.store100_0(store100_0),
.store101_0(store101_0),
.store110_0(store110_0),
.store000_1(store000_1),
.store001_1(store001_1),
.store010_1(store010_1),
.store100_1(store100_1),
.store101_1(store101_1),
.store110_1(store110_1),
.clock(clock),
.store000_0_out(store000_out),
.store001_0_out(store001_out),
.store010_0_out(store010_out),
.store100_0_out(store100_out),
.store101_0_out(store101_out),
.store110_0_out(store110_out),
.cout1(cout1),
.cout2(cout2),
.cout3(cout3),
.cout4(cout4),
.cout5(cout5),
.cout6(cout6)
);
//reg final_out;
endmodule
|
// ======================================================================
// USB-UART.v generated from TopDesign.cysch
// 12/08/2014 at 16:15
// This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!!
// ======================================================================
/* -- WARNING: The following section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_DIE_LEOPARD 1
`define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3
`define CYDEV_CHIP_REV_LEOPARD_ES3 3
`define CYDEV_CHIP_REV_LEOPARD_ES2 1
`define CYDEV_CHIP_REV_LEOPARD_ES1 0
`define CYDEV_CHIP_DIE_PSOC4A 2
`define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17
`define CYDEV_CHIP_REV_PSOC4A_ES0 17
`define CYDEV_CHIP_DIE_PANTHER 3
`define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1
`define CYDEV_CHIP_REV_PANTHER_ES1 1
`define CYDEV_CHIP_REV_PANTHER_ES0 0
`define CYDEV_CHIP_DIE_PSOC5LP 4
`define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0
`define CYDEV_CHIP_REV_PSOC5LP_ES0 0
`define CYDEV_CHIP_DIE_EXPECT 2
`define CYDEV_CHIP_REV_EXPECT 17
`define CYDEV_CHIP_DIE_ACTUAL 2
/* -- WARNING: The previous section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_FAMILY_UNKNOWN 0
`define CYDEV_CHIP_MEMBER_UNKNOWN 0
`define CYDEV_CHIP_FAMILY_PSOC3 1
`define CYDEV_CHIP_MEMBER_3A 1
`define CYDEV_CHIP_REVISION_3A_PRODUCTION 3
`define CYDEV_CHIP_REVISION_3A_ES3 3
`define CYDEV_CHIP_REVISION_3A_ES2 1
`define CYDEV_CHIP_REVISION_3A_ES1 0
`define CYDEV_CHIP_FAMILY_PSOC4 2
`define CYDEV_CHIP_MEMBER_4A 2
`define CYDEV_CHIP_REVISION_4A_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4A_ES0 17
`define CYDEV_CHIP_MEMBER_4D 3
`define CYDEV_CHIP_REVISION_4D_PRODUCTION 0
`define CYDEV_CHIP_REVISION_4D_ES0 0
`define CYDEV_CHIP_FAMILY_PSOC5 3
`define CYDEV_CHIP_MEMBER_5A 4
`define CYDEV_CHIP_REVISION_5A_PRODUCTION 1
`define CYDEV_CHIP_REVISION_5A_ES1 1
`define CYDEV_CHIP_REVISION_5A_ES0 0
`define CYDEV_CHIP_MEMBER_5B 5
`define CYDEV_CHIP_REVISION_5B_PRODUCTION 0
`define CYDEV_CHIP_REVISION_5B_ES0 0
`define CYDEV_CHIP_FAMILY_USED 2
`define CYDEV_CHIP_MEMBER_USED 2
`define CYDEV_CHIP_REVISION_USED 17
// Component: ZeroTerminal
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`else
`define CY_BLK_DIR "C:\Program Files\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "C:\Program Files\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`endif
// Component: cy_virtualmux_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "C:\Program Files\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`endif
// Component: or_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0"
`include "C:\Program Files\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v"
`endif
// SCB_P4_v1_20(BitWidthReplacementStringRx=uint8, BitWidthReplacementStringTx=uint8, BufNum=1, Cond=#, DBGW_SCB_IP_V0=true, DBGW_SCB_IP_V1=false, EndCond=#endif, EzI2cBitWidthReplacementString=uint16, EzI2cClkFreqDes=1600, EzI2cClockFromTerm=false, EzI2cClockStretching=true, EzI2cDataRate=100, EzI2cIsPrimarySlaveAddressHex=true, EzI2cIsSecondarySlaveAddressHex=true, EzI2cMedianFilterEnable=true, EzI2cNumberOfAddresses=0, EzI2cOvsFactor=16, EzI2cPrimarySlaveAddress=8, EzI2cSecondarySlaveAddress=9, EzI2cSlaveAddressMask=254, EzI2cSubAddressSize=0, EzI2cWakeEnable=false, I2cAcceptAddress=false, I2cClkFreqDes=1600, I2cClockFromTerm=false, I2cDataRate=100, I2cExternIntrHandler=false, I2cIsSlaveAddressHex=true, I2cIsSlaveAddressMaskHex=true, I2cMedianFilterEnable=true, I2cMode=1, I2cOvsFactor=16, I2cOvsFactorHigh=8, I2cOvsFactorLow=8, I2cSlaveAddress=8, I2cSlaveAddressMask=254, I2cWakeEnable=false, PinName0Unconfig=spi_mosi_i2c_scl_uart_rx, PinName1Unconfig=spi_miso_i2c_sda_uart_tx, RemoveI2cPins=true, RemoveMisoSdaTx=true, RemoveMosiSclRx=true, RemoveMosiSclRxWake=true, RemoveScbClk=false, RemoveScbIrq=true, RemoveSpiMasterPins=true, RemoveSpiMasterSs0Pin=true, RemoveSpiMasterSs1Pin=true, RemoveSpiMasterSs2Pin=true, RemoveSpiMasterSs3Pin=true, RemoveSpiSclk=true, RemoveSpiSlavePins=true, RemoveSpiSs0=true, RemoveSpiSs1=true, RemoveSpiSs2=true, RemoveSpiSs3=true, RemoveUartRxPin=false, RemoveUartRxTxPin=true, RemoveUartRxWake=true, RemoveUartRxWakeupIrq=true, RemoveUartTxPin=false, ScbClkFreqDes=1382.4, ScbClockSelect=1, ScbClockTermEnable=false, ScbCustomIntrHandlerEnable=true, ScbInterruptTermEnable=false, ScbMisoSdaTxEnable=true, ScbMode=4, ScbModeHw=2, ScbMosiSclRxEnable=true, ScbRxWakeIrqEnable=false, ScbSclkEnable=false, ScbSs0Enable=false, ScbSs1Enable=false, ScbSs2Enable=false, ScbSs3Enable=false, SpiBitRate=1000, SpiBitsOrder=1, SpiClkFreqDes=16000, SpiClockFromTerm=false, SpiInterruptMode=1, SpiIntrMasterSpiDone=false, SpiIntrRxFull=false, SpiIntrRxNotEmpty=false, SpiIntrRxOverflow=false, SpiIntrRxTrigger=false, SpiIntrRxUnderflow=false, SpiIntrSlaveBusError=false, SpiIntrTxEmpty=false, SpiIntrTxNotFull=false, SpiIntrTxOverflow=false, SpiIntrTxTrigger=false, SpiIntrTxUnderflow=false, SpiLateMisoSampleEnable=false, SpiMedianFilterEnable=false, SpiMode=0, SpiNumberOfRxDataBits=8, SpiNumberOfSelectLines=1, SpiNumberOfTxDataBits=8, SpiOvsFactor=16, SpiRxBufferSize=8, SpiRxIntrMask=0, SpiRxTriggerLevel=7, SpiSclkMode=0, SpiSubMode=0, SpiTransferSeparation=1, SpiTxBufferSize=8, SpiTxIntrMask=0, SpiTxTriggerLevel=0, SpiWakeEnable=false, UartClkFreqDes=1382.4, UartClockFromTerm=false, UartDataRate=115200, UartDirection=3, UartDropOnFrameErr=false, UartDropOnParityErr=false, UartInterruptMode=0, UartIntrRxFrameErr=false, UartIntrRxFull=false, UartIntrRxNotEmpty=true, UartIntrRxOverflow=false, UartIntrRxParityErr=false, UartIntrRxTrigger=false, UartIntrRxUnderflow=false, UartIntrTxEmpty=false, UartIntrTxNotFull=false, UartIntrTxOverflow=false, UartIntrTxTrigger=false, UartIntrTxUartDone=false, UartIntrTxUartLostArb=false, UartIntrTxUartNack=false, UartIntrTxUnderflow=false, UartIrdaLowPower=false, UartIrdaPolarity=0, UartMedianFilterEnable=false, UartMpEnable=false, UartMpRxAcceptAddress=false, UartMpRxAddress=2, UartMpRxAddressMask=255, UartNumberOfDataBits=8, UartNumberOfStopBits=2, UartOvsFactor=12, UartParityType=2, UartRxBufferSize=8, UartRxEnable=true, UartRxIntrMask=4, UartRxTriggerLevel=7, UartSmCardRetryOnNack=false, UartSubMode=0, UartTxBufferSize=8, UartTxEnable=true, UartTxIntrMask=0, UartTxTriggerLevel=0, UartWakeEnable=false, CY_COMPONENT_NAME=SCB_P4_v1_20, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=UART, CY_INSTANCE_SHORT_NAME=UART, CY_MAJOR_VERSION=1, CY_MINOR_VERSION=20, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=UART, )
module SCB_P4_v1_20_0 (
sclk,
interrupt,
clock);
output sclk;
output interrupt;
input clock;
wire Net_427;
wire Net_416;
wire Net_245;
wire Net_676;
wire Net_452;
wire Net_459;
wire Net_496;
wire Net_660;
wire Net_656;
wire Net_687;
wire Net_703;
wire Net_682;
wire Net_422;
wire Net_379;
wire Net_555;
wire Net_387;
wire uncfg_rx_irq;
wire Net_458;
wire Net_596;
wire Net_252;
wire Net_547;
wire rx_irq;
wire [3:0] ss;
wire Net_467;
wire Net_655;
wire Net_663;
wire Net_581;
wire Net_474;
wire Net_651;
wire Net_580;
wire Net_654;
wire Net_653;
wire Net_652;
wire Net_284;
cy_clock_v1_0
#(.id("1ec6effd-8f31-4dd5-a825-0c49238d524e/81fcee8a-3b8b-4be1-9a5f-a5e2e619a938"),
.source_clock_id(""),
.divisor(0),
.period("723379629.62963"),
.is_direct(0),
.is_digital(0))
SCBCLK
(.clock_out(Net_284));
ZeroTerminal ZeroTerminal_5 (
.z(Net_459));
// select_s_VM (cy_virtualmux_v1_0)
assign Net_652 = Net_459;
ZeroTerminal ZeroTerminal_4 (
.z(Net_452));
ZeroTerminal ZeroTerminal_3 (
.z(Net_676));
ZeroTerminal ZeroTerminal_2 (
.z(Net_245));
ZeroTerminal ZeroTerminal_1 (
.z(Net_416));
// rx_VM (cy_virtualmux_v1_0)
assign Net_654 = Net_379;
// rx_wake_VM (cy_virtualmux_v1_0)
assign Net_682 = uncfg_rx_irq;
// clock_VM (cy_virtualmux_v1_0)
assign Net_655 = Net_284;
// sclk_s_VM (cy_virtualmux_v1_0)
assign Net_653 = Net_416;
// mosi_s_VM (cy_virtualmux_v1_0)
assign Net_651 = Net_676;
// miso_m_VM (cy_virtualmux_v1_0)
assign Net_663 = Net_245;
wire [0:0] tmpOE__tx_net;
wire [0:0] tmpFB_0__tx_net;
wire [0:0] tmpIO_0__tx_net;
wire [0:0] tmpINTERRUPT_0__tx_net;
electrical [0:0] tmpSIOVREF__tx_net;
cy_psoc3_pins_v1_10
#(.id("1ec6effd-8f31-4dd5-a825-0c49238d524e/23b8206d-1c77-4e61-be4a-b4037d5de5fc"),
.drive_mode(3'b110),
.ibuf_enabled(1'b0),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("B"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
tx
(.oe(tmpOE__tx_net),
.y({Net_656}),
.fb({tmpFB_0__tx_net[0:0]}),
.io({tmpIO_0__tx_net[0:0]}),
.siovref(tmpSIOVREF__tx_net),
.interrupt({tmpINTERRUPT_0__tx_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__tx_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
ZeroTerminal ZeroTerminal_7 (
.z(Net_427));
assign sclk = Net_284 | Net_427;
wire [0:0] tmpOE__rx_net;
wire [0:0] tmpIO_0__rx_net;
wire [0:0] tmpINTERRUPT_0__rx_net;
electrical [0:0] tmpSIOVREF__rx_net;
cy_psoc3_pins_v1_10
#(.id("1ec6effd-8f31-4dd5-a825-0c49238d524e/78e33e5d-45ea-4b75-88d5-73274e8a7ce4"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
rx
(.oe(tmpOE__rx_net),
.y({1'b0}),
.fb({Net_379}),
.io({tmpIO_0__rx_net[0:0]}),
.siovref(tmpSIOVREF__rx_net),
.interrupt({tmpINTERRUPT_0__rx_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__rx_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_m0s8_scb_v1_0 SCB (
.rx(Net_654),
.miso_m(Net_663),
.clock(Net_655),
.select_m(ss[3:0]),
.sclk_m(Net_687),
.mosi_s(Net_651),
.select_s(Net_652),
.sclk_s(Net_653),
.mosi_m(Net_660),
.scl(Net_580),
.sda(Net_581),
.tx(Net_656),
.miso_s(Net_703),
.interrupt(interrupt));
defparam SCB.scb_mode = 2;
endmodule
// Component: OneTerminal
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal\OneTerminal.v"
`else
`define CY_BLK_DIR "C:\Program Files\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal"
`include "C:\Program Files\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\OneTerminal\OneTerminal.v"
`endif
// IDAC_P4_v1_0(IDACRange=0, IDACValue=14, Polarity=1, Resolution=7, CY_COMPONENT_NAME=IDAC_P4_v1_0, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=CapSense:IDAC2, CY_INSTANCE_SHORT_NAME=IDAC2, CY_MAJOR_VERSION=1, CY_MINOR_VERSION=0, CY_REMOVE=false, CY_SUPPRESS_API_GEN=true, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=CapSense_IDAC2, )
module IDAC_P4_v1_0_1 (
Iout);
inout Iout;
electrical Iout;
wire Net_3;
cy_psoc4_csidac_v1_0 cy_psoc4_idac (
.en(Net_3),
.iout(Iout));
defparam cy_psoc4_idac.resolution = 7;
OneTerminal OneTerminal_1 (
.o(Net_3));
endmodule
// IDAC_P4_v1_0(IDACRange=0, IDACValue=16, Polarity=1, Resolution=8, CY_COMPONENT_NAME=IDAC_P4_v1_0, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=CapSense:IDAC1, CY_INSTANCE_SHORT_NAME=IDAC1, CY_MAJOR_VERSION=1, CY_MINOR_VERSION=0, CY_REMOVE=false, CY_SUPPRESS_API_GEN=true, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=CapSense_IDAC1, )
module IDAC_P4_v1_0_2 (
Iout);
inout Iout;
electrical Iout;
wire Net_3;
cy_psoc4_csidac_v1_0 cy_psoc4_idac (
.en(Net_3),
.iout(Iout));
defparam cy_psoc4_idac.resolution = 8;
OneTerminal OneTerminal_1 (
.o(Net_3));
endmodule
// CapSense_CSD_P4_v2_0(AnalogSwitchDivider=12, AvgSamplesNumber=1, CalibrationResulution=7, CmodPrecharge=1, ConnectInactiveSensors=0, CshTankPrecharge=1, CurrentSource=0, CustomEzI2CInstanceName=SCB_1, DbPwmMode=0, DbPwmPeriod=0, DfbEnable=false, DynamicButtonNumber=5, EmcSensorNumber=10, EnableAutoCalibration=false, EnableBIST=false, EnableTuneHelper=true, GuardSensorEnable=false, I2cCommunication=0, IDACRange=0, IDACsCount=2, ImmunityLevel=1, InputClkFreq=3, IsStreetFighter=false, KValueScalingFactor=8, LowBaselineReset=5, M0S8CSD_BLOCK_NUM=1, M0S8CSD_BLOCK_VER=0, M0S8GPIO2_BLOCK_NUM=1, M0S8GPIO2_BLOCK_VER=0, M0S8HSIOM4A_BLOCK_NUM=1, M0S8HSIOM4A_BLOCK_VER=0, M0S8IOSS_BLOCK_NUM=0, M0S8IOSS_BLOCK_VER=-1, M0S8PCLK_BLOCK_NUM=1, M0S8PCLK_BLOCK_VER=0, M0S8PERI_BLOCK_NUM=0, M0S8PERI_BLOCK_VER=-1, ModulatorClkDivider=12, NegativeNoiseThreshold=20, OversamplingEn=true, PrechargeClkDivider=12, PrechargeClkFreq=3, PrsOptions=0, PrtRegNameReplacementString=CYREG, RawDataFilterType=8, SensorAutoReset=false, SensorNumber=4, SensorsFreqSettingsInd=true, ShieldDelay=0, ShieldEnable=false, ShieldTankEnable=false, SizeReplacementString=uint8, SliderThresholdsUpdateManual=false, SnsAlias=Button0__BTN, Button1__BTN, Button2__BTN, Button3__BTN, ThresholdMode=true, TunerIntfAddress=8, TunerIntfDataRate=400, TunerProperties=, TuningMethod=0, WaterProofingEnabled=false, WidgetResolution=8, WidgetsData=<?xml version="1.0" encoding="utf-16"?> <CyWidgetsList xmlns:Version="2_0"> <ListMainTerminal> <CyTerminal NameIndex="0" WidgetName="Button0__BTN" /> <CyTerminal NameIndex="0" WidgetName="Button1__BTN" /> <CyTerminal NameIndex="0" WidgetName="Button2__BTN" /> <CyTerminal NameIndex="0" WidgetName="Button3__BTN" /> </ListMainTerminal> <ListButtons> <CyButton Name="Button0" Type="Button" Count="1" Angle="0" Fliped="false" Fliped2D="false" ScaleFactor="1"> <Location> <X>2147483647</X> <Y>2147483647</Y> </Location> <Properties> <Hysteresis>10</Hysteresis> <Debounce>5</Debounce> <FingerThreshold>100</FingerThreshold> <NoiseThreshold>20</NoiseThreshold> <ScanResolution>_14</ScanResolution> </Properties> </CyButton> <CyButton Name="Button1" Type="Button" Count="1" Angle="0" Fliped="false" Fliped2D="false" ScaleFactor="1"> <Location> <X>2147483647</X> <Y>2147483647</Y> </Location> <Properties> <Hysteresis>10</Hysteresis> <Debounce>5</Debounce> <FingerThreshold>100</FingerThreshold> <NoiseThreshold>20</NoiseThreshold> <ScanResolution>_14</ScanResolution> </Properties> </CyButton> <CyButton Name="Button2" Type="Button" Count="1" Angle="0" Fliped="false" Fliped2D="false" ScaleFactor="1"> <Location> <X>2147483647</X> <Y>2147483647</Y> </Location> <Properties> <Hysteresis>10</Hysteresis> <Debounce>5</Debounce> <FingerThreshold>100</FingerThreshold> <NoiseThreshold>20</NoiseThreshold> <ScanResolution>_14</ScanResolution> </Properties> </CyButton> <CyButton Name="Button3" Type="Button" Count="1" Angle="0" Fliped="false" Fliped2D="false" ScaleFactor="1"> <Location> <X>2147483647</X> <Y>2147483647</Y> </Location> <Properties> <Hysteresis>10</Hysteresis> <Debounce>5</Debounce> <FingerThreshold>100</FingerThreshold> <NoiseThreshold>20</NoiseThreshold> <ScanResolution>_14</ScanResolution> </Properties> </CyButton> </ListButtons> <ListMatrixButtons /> <ListTouchPads /> <ListSliders /> <GuardSensor Name="GuardSensor" Type="Button" Count="1" Angle="0" Fliped="false" Fliped2D="false" ScaleFactor="1"> <Location> <X>2147483647</X> <Y>2147483647</Y> </Location> <Properties> <Hysteresis>10</Hysteresis> <Debounce>5</Debounce> <FingerThreshold>100</FingerThreshold> <NoiseThreshold>20</NoiseThreshold> <ScanResolution>_12</ScanResolution> </Properties> </GuardSensor> <GuardSensorTerminal NameIndex="0" WidgetName="GuardSensor__GRD" /> <CyScanSlotsList> <ListScanSlots> <CyScanSlot IDAC1Settings="80" IDAC2Settings="80" Sensitivity="2" AnalogSwitchDivider="4" ModulatorDivider="4" WidgetName="Button0__BTN"> <ListTerminalsNames> <string>Button0__BTN</string> </ListTerminalsNames> </CyScanSlot> <CyScanSlot IDAC1Settings="80" IDAC2Settings="80" Sensitivity="2" AnalogSwitchDivider="4" ModulatorDivider="4" WidgetName="Button1__BTN"> <ListTerminalsNames> <string>Button1__BTN</string> </ListTerminalsNames> </CyScanSlot> <CyScanSlot IDAC1Settings="80" IDAC2Settings="80" Sensitivity="2" AnalogSwitchDivider="4" ModulatorDivider="4" WidgetName="Button2__BTN"> <ListTerminalsNames> <string>Button2__BTN</string> </ListTerminalsNames> </CyScanSlot> <CyScanSlot IDAC1Settings="80" IDAC2Settings="80" Sensitivity="2" AnalogSwitchDivider="4" ModulatorDivider="4" WidgetName="Button3__BTN"> <ListTerminalsNames> <string>Button3__BTN</string> </ListTerminalsNames> </CyScanSlot> </ListScanSlots> <GuardSensorScanSlot IDAC1Settings="120" IDAC2Settings="80" Sensitivity="2" AnalogSwitchDivider="2" ModulatorDivider="2" WidgetName="GuardSensor__GRD"> <ListTerminalsNames> <string>GuardSensor__GRD</string> </ListTerminalsNames> </GuardSensorScanSlot> </CyScanSlotsList> </CyWidgetsList>, CY_COMPONENT_NAME=CapSense_CSD_P4_v2_0, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=CapSense, CY_INSTANCE_SHORT_NAME=CapSense, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=0, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=CapSense, )
module CapSense_CSD_P4_v2_0_3 (
sclk2);
output sclk2;
wire Net_534;
wire Net_474;
wire Net_540;
wire Net_329;
wire Net_312;
wire Net_104;
wire Net_328;
electrical Net_398;
electrical Net_241;
electrical Net_246;
wire Net_420;
wire Net_429;
electrical [3:0] Net_245;
wire Net_248;
electrical Net_270;
cy_psoc4_csd_v1_0 CSD_FFB (
.source(Net_245[3:0]),
.csh(Net_246),
.shield(Net_241),
.cmod(Net_398),
.sample_out(Net_328),
.sense_in(Net_104),
.clk1(Net_429),
.clk2(Net_420),
.irq(Net_248),
.sample_in(Net_312),
.sense_out(Net_329),
.amuxa(Net_270));
defparam CSD_FFB.sensors_count = 4;
defparam CSD_FFB.shield_count = 1;
cy_clock_v1_0
#(.id("3c8c7eac-aaf5-41b9-9d0a-e31e77bfd8ce/74063576-f256-4f8f-8a82-9abdee876261"),
.source_clock_id("413DE2EF-D9F2-4233-A808-DFAF137FD877"),
.divisor(255),
.period("0"),
.is_direct(0),
.is_digital(0))
SampleClk
(.clock_out(Net_420));
wire [0:0] tmpOE__Cmod_net;
wire [0:0] tmpFB_0__Cmod_net;
wire [0:0] tmpIO_0__Cmod_net;
wire [0:0] tmpINTERRUPT_0__Cmod_net;
electrical [0:0] tmpSIOVREF__Cmod_net;
cy_psoc3_pins_v1_10
#(.id("3c8c7eac-aaf5-41b9-9d0a-e31e77bfd8ce/899719c0-e797-4403-a44f-07a66de2cbeb"),
.drive_mode(3'b000),
.ibuf_enabled(1'b0),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases("Cmod"),
.pin_mode("A"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
Cmod
(.oe(tmpOE__Cmod_net),
.y({1'b0}),
.fb({tmpFB_0__Cmod_net[0:0]}),
.analog({Net_398}),
.io({tmpIO_0__Cmod_net[0:0]}),
.siovref(tmpSIOVREF__Cmod_net),
.interrupt({tmpINTERRUPT_0__Cmod_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Cmod_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_isr_v1_0
#(.int_type(2'b10))
ISR
(.int_signal(Net_248));
IDAC_P4_v1_0_1 IDAC2 (
.Iout(Net_270));
wire [3:0] tmpOE__Sns_net;
wire [3:0] tmpFB_3__Sns_net;
wire [3:0] tmpIO_3__Sns_net;
wire [0:0] tmpINTERRUPT_0__Sns_net;
electrical [0:0] tmpSIOVREF__Sns_net;
cy_psoc3_pins_v1_10
#(.id("3c8c7eac-aaf5-41b9-9d0a-e31e77bfd8ce/73b612cd-240c-4d8e-8340-ea28aabf4b11"),
.drive_mode(12'b000_000_000_000),
.ibuf_enabled(4'b0_0_0_0),
.init_dr_st(4'b1_1_1_1),
.input_clk_en(0),
.input_sync(4'b1_1_1_1),
.input_sync_mode(4'b0_0_0_0),
.intr_mode(8'b00_00_00_00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(",,,"),
.layout_mode("NONCONTIGUOUS"),
.oe_conn(4'b0_0_0_0),
.oe_reset(0),
.oe_sync(4'b0_0_0_0),
.output_clk_en(0),
.output_clock_mode(4'b0_0_0_0),
.output_conn(4'b0_0_0_0),
.output_mode(4'b0_0_0_0),
.output_reset(0),
.output_sync(4'b0_0_0_0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases("Button0__BTN,Button1__BTN,Button2__BTN,Button3__BTN"),
.pin_mode("AAAA"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(4'b0_0_0_0),
.sio_ibuf(""),
.sio_info(8'b00_00_00_00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(4'b0_0_0_0),
.spanning(1),
.use_annotation(4'b0_0_0_0),
.vtrip(8'b10_10_10_10),
.width(4))
Sns
(.oe(tmpOE__Sns_net),
.y({4'b0}),
.fb({tmpFB_3__Sns_net[3:0]}),
.analog({Net_245[3:0]}),
.io({tmpIO_3__Sns_net[3:0]}),
.siovref(tmpSIOVREF__Sns_net),
.interrupt({tmpINTERRUPT_0__Sns_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Sns_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{4'b1111} : {4'b1111};
IDAC_P4_v1_0_2 IDAC1 (
.Iout(Net_270));
ZeroTerminal ZeroTerminal_1 (
.z(Net_312));
ZeroTerminal ZeroTerminal_2 (
.z(Net_104));
assign sclk2 = Net_420 | Net_474;
ZeroTerminal ZeroTerminal_7 (
.z(Net_474));
cy_clock_v1_0
#(.id("3c8c7eac-aaf5-41b9-9d0a-e31e77bfd8ce/9a635726-510c-483c-9c5c-3e233ee2906a"),
.source_clock_id("413DE2EF-D9F2-4233-A808-DFAF137FD877"),
.divisor(255),
.period("0"),
.is_direct(0),
.is_digital(0))
SenseClk
(.clock_out(Net_429));
endmodule
// SCB_P4_v1_20(BitWidthReplacementStringRx=uint8, BitWidthReplacementStringTx=uint8, BufNum=1, Cond=#, DBGW_SCB_IP_V0=true, DBGW_SCB_IP_V1=false, EndCond=#endif, EzI2cBitWidthReplacementString=uint16, EzI2cClkFreqDes=6400, EzI2cClockFromTerm=false, EzI2cClockStretching=true, EzI2cDataRate=400, EzI2cIsPrimarySlaveAddressHex=true, EzI2cIsSecondarySlaveAddressHex=true, EzI2cMedianFilterEnable=true, EzI2cNumberOfAddresses=0, EzI2cOvsFactor=16, EzI2cPrimarySlaveAddress=8, EzI2cSecondarySlaveAddress=9, EzI2cSlaveAddressMask=254, EzI2cSubAddressSize=1, EzI2cWakeEnable=false, I2cAcceptAddress=false, I2cClkFreqDes=1600, I2cClockFromTerm=false, I2cDataRate=100, I2cExternIntrHandler=false, I2cIsSlaveAddressHex=true, I2cIsSlaveAddressMaskHex=true, I2cMedianFilterEnable=true, I2cMode=1, I2cOvsFactor=16, I2cOvsFactorHigh=8, I2cOvsFactorLow=8, I2cSlaveAddress=8, I2cSlaveAddressMask=254, I2cWakeEnable=false, PinName0Unconfig=spi_mosi_i2c_scl_uart_rx, PinName1Unconfig=spi_miso_i2c_sda_uart_tx, RemoveI2cPins=false, RemoveMisoSdaTx=true, RemoveMosiSclRx=true, RemoveMosiSclRxWake=true, RemoveScbClk=false, RemoveScbIrq=false, RemoveSpiMasterPins=true, RemoveSpiMasterSs0Pin=true, RemoveSpiMasterSs1Pin=true, RemoveSpiMasterSs2Pin=true, RemoveSpiMasterSs3Pin=true, RemoveSpiSclk=true, RemoveSpiSlavePins=true, RemoveSpiSs0=true, RemoveSpiSs1=true, RemoveSpiSs2=true, RemoveSpiSs3=true, RemoveUartRxPin=true, RemoveUartRxTxPin=true, RemoveUartRxWake=true, RemoveUartRxWakeupIrq=true, RemoveUartTxPin=true, ScbClkFreqDes=6400, ScbClockSelect=1, ScbClockTermEnable=false, ScbCustomIntrHandlerEnable=true, ScbInterruptTermEnable=false, ScbMisoSdaTxEnable=true, ScbMode=8, ScbModeHw=0, ScbMosiSclRxEnable=true, ScbRxWakeIrqEnable=false, ScbSclkEnable=false, ScbSs0Enable=false, ScbSs1Enable=false, ScbSs2Enable=false, ScbSs3Enable=false, SpiBitRate=1000, SpiBitsOrder=1, SpiClkFreqDes=16000, SpiClockFromTerm=false, SpiInterruptMode=0, SpiIntrMasterSpiDone=false, SpiIntrRxFull=false, SpiIntrRxNotEmpty=false, SpiIntrRxOverflow=false, SpiIntrRxTrigger=false, SpiIntrRxUnderflow=false, SpiIntrSlaveBusError=false, SpiIntrTxEmpty=false, SpiIntrTxNotFull=false, SpiIntrTxOverflow=false, SpiIntrTxTrigger=false, SpiIntrTxUnderflow=false, SpiLateMisoSampleEnable=false, SpiMedianFilterEnable=false, SpiMode=0, SpiNumberOfRxDataBits=8, SpiNumberOfSelectLines=1, SpiNumberOfTxDataBits=8, SpiOvsFactor=16, SpiRxBufferSize=8, SpiRxIntrMask=0, SpiRxTriggerLevel=7, SpiSclkMode=0, SpiSubMode=0, SpiTransferSeparation=1, SpiTxBufferSize=8, SpiTxIntrMask=0, SpiTxTriggerLevel=0, SpiWakeEnable=false, UartClkFreqDes=1382.4, UartClockFromTerm=false, UartDataRate=115200, UartDirection=3, UartDropOnFrameErr=false, UartDropOnParityErr=false, UartInterruptMode=0, UartIntrRxFrameErr=false, UartIntrRxFull=false, UartIntrRxNotEmpty=false, UartIntrRxOverflow=false, UartIntrRxParityErr=false, UartIntrRxTrigger=false, UartIntrRxUnderflow=false, UartIntrTxEmpty=false, UartIntrTxNotFull=false, UartIntrTxOverflow=false, UartIntrTxTrigger=false, UartIntrTxUartDone=false, UartIntrTxUartLostArb=false, UartIntrTxUartNack=false, UartIntrTxUnderflow=false, UartIrdaLowPower=false, UartIrdaPolarity=0, UartMedianFilterEnable=false, UartMpEnable=false, UartMpRxAcceptAddress=false, UartMpRxAddress=2, UartMpRxAddressMask=255, UartNumberOfDataBits=8, UartNumberOfStopBits=2, UartOvsFactor=12, UartParityType=2, UartRxBufferSize=8, UartRxEnable=true, UartRxIntrMask=0, UartRxTriggerLevel=7, UartSmCardRetryOnNack=false, UartSubMode=0, UartTxBufferSize=8, UartTxEnable=true, UartTxIntrMask=0, UartTxTriggerLevel=0, UartWakeEnable=false, CY_COMPONENT_NAME=SCB_P4_v1_20, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=SCB_1, CY_INSTANCE_SHORT_NAME=SCB_1, CY_MAJOR_VERSION=1, CY_MINOR_VERSION=20, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=SCB_1, )
module SCB_P4_v1_20_4 (
sclk,
interrupt,
clock);
output sclk;
output interrupt;
input clock;
wire Net_427;
wire Net_416;
wire Net_245;
wire Net_676;
wire Net_452;
wire Net_459;
wire Net_496;
wire Net_660;
wire Net_656;
wire Net_687;
wire Net_703;
wire Net_682;
wire Net_422;
wire Net_379;
wire Net_555;
wire Net_387;
wire uncfg_rx_irq;
wire Net_458;
wire Net_596;
wire Net_252;
wire Net_547;
wire rx_irq;
wire [3:0] ss;
wire Net_467;
wire Net_655;
wire Net_663;
wire Net_581;
wire Net_474;
wire Net_651;
wire Net_580;
wire Net_654;
wire Net_653;
wire Net_652;
wire Net_284;
cy_clock_v1_0
#(.id("4ee47aff-a351-4cef-924e-4fb02af36bdf/81fcee8a-3b8b-4be1-9a5f-a5e2e619a938"),
.source_clock_id(""),
.divisor(0),
.period("156250000"),
.is_direct(0),
.is_digital(0))
SCBCLK
(.clock_out(Net_284));
ZeroTerminal ZeroTerminal_5 (
.z(Net_459));
// select_s_VM (cy_virtualmux_v1_0)
assign Net_652 = Net_459;
ZeroTerminal ZeroTerminal_4 (
.z(Net_452));
ZeroTerminal ZeroTerminal_3 (
.z(Net_676));
ZeroTerminal ZeroTerminal_2 (
.z(Net_245));
ZeroTerminal ZeroTerminal_1 (
.z(Net_416));
// rx_VM (cy_virtualmux_v1_0)
assign Net_654 = Net_452;
// rx_wake_VM (cy_virtualmux_v1_0)
assign Net_682 = uncfg_rx_irq;
// clock_VM (cy_virtualmux_v1_0)
assign Net_655 = Net_284;
// sclk_s_VM (cy_virtualmux_v1_0)
assign Net_653 = Net_416;
// mosi_s_VM (cy_virtualmux_v1_0)
assign Net_651 = Net_676;
// miso_m_VM (cy_virtualmux_v1_0)
assign Net_663 = Net_245;
wire [0:0] tmpOE__sda_net;
wire [0:0] tmpFB_0__sda_net;
wire [0:0] tmpINTERRUPT_0__sda_net;
electrical [0:0] tmpSIOVREF__sda_net;
cy_psoc3_pins_v1_10
#(.id("4ee47aff-a351-4cef-924e-4fb02af36bdf/5382e105-1382-4a2e-b9f4-3bb2feba71e0"),
.drive_mode(3'b100),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("B"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
sda
(.oe(tmpOE__sda_net),
.y({1'b0}),
.fb({tmpFB_0__sda_net[0:0]}),
.io({Net_581}),
.siovref(tmpSIOVREF__sda_net),
.interrupt({tmpINTERRUPT_0__sda_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__sda_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__scl_net;
wire [0:0] tmpFB_0__scl_net;
wire [0:0] tmpINTERRUPT_0__scl_net;
electrical [0:0] tmpSIOVREF__scl_net;
cy_psoc3_pins_v1_10
#(.id("4ee47aff-a351-4cef-924e-4fb02af36bdf/22863ebe-a37b-476f-b252-6e49a8c00b12"),
.drive_mode(3'b100),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("B"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
scl
(.oe(tmpOE__scl_net),
.y({1'b0}),
.fb({tmpFB_0__scl_net[0:0]}),
.io({Net_580}),
.siovref(tmpSIOVREF__scl_net),
.interrupt({tmpINTERRUPT_0__scl_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__scl_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
ZeroTerminal ZeroTerminal_7 (
.z(Net_427));
assign sclk = Net_284 | Net_427;
cy_isr_v1_0
#(.int_type(2'b10))
SCB_IRQ
(.int_signal(interrupt));
cy_m0s8_scb_v1_0 SCB (
.rx(Net_654),
.miso_m(Net_663),
.clock(Net_655),
.select_m(ss[3:0]),
.sclk_m(Net_687),
.mosi_s(Net_651),
.select_s(Net_652),
.sclk_s(Net_653),
.mosi_m(Net_660),
.scl(Net_580),
.sda(Net_581),
.tx(Net_656),
.miso_s(Net_703),
.interrupt(interrupt));
defparam SCB.scb_mode = 0;
endmodule
// top
module top ;
wire Net_21;
wire Net_20;
wire Net_19;
wire Net_27;
wire Net_3;
wire Net_2;
wire Net_1;
SCB_P4_v1_20_0 UART (
.sclk(Net_1),
.interrupt(Net_2),
.clock(1'b0));
CapSense_CSD_P4_v2_0_3 CapSense (
.sclk2(Net_27));
SCB_P4_v1_20_4 SCB_1 (
.sclk(Net_19),
.interrupt(Net_20),
.clock(1'b0));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND4B_BLACKBOX_V
`define SKY130_FD_SC_LP__AND4B_BLACKBOX_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and4b (
X ,
A_N,
B ,
C ,
D
);
output X ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND4B_BLACKBOX_V
|
(** * Equiv: Program Equivalence *)
(* IMPORTS *)
Require Import Coq.Bool.Bool.
Require Import Coq.Arith.Arith.
Require Import Coq.Arith.EqNat.
Require Import Coq.omega.Omega.
Require Import Coq.Lists.List.
Require Import Coq.Logic.FunctionalExtensionality.
Import ListNotations.
Require Import Maps.
Require Import Imp.
(* /IMPORTS *)
(** *** Some Advice for Working on Exercises:
- Most of the Coq proofs we ask you to do are similar to proofs
that we've provided. Before starting to work on exercises
problems, take the time to work through our proofs (both
informally, on paper, and in Coq) and make sure you understand
them in detail. This will save you a lot of time.
- The Coq proofs we're doing now are sufficiently complicated that
it is more or less impossible to complete them simply by random
experimentation or "following your nose." You need to start
with an idea about why the property is true and how the proof is
going to go. The best way to do this is to write out at least a
sketch of an informal proof on paper -- one that intuitively
convinces you of the truth of the theorem -- before starting to
work on the formal one. Alternately, grab a friend and try to
convince them that the theorem is true; then try to formalize
your explanation.
- Use automation to save work! The proofs in this chapter's
exercises can get pretty long if you try to write out all the
cases explicitly. *)
(* ################################################################# *)
(** * Behavioral Equivalence *)
(** In an earlier chapter, we investigated the correctness of a very
simple program transformation: the [optimize_0plus] function. The
programming language we were considering was the first version of
the language of arithmetic expressions -- with no variables -- so
in that setting it was very easy to define what it means for a
program transformation to be correct: it should always yield a
program that evaluates to the same number as the original.
To talk about the correctness of program transformations for the
full Imp language, including assignment and other commands, we
need to consider the role of variables and state. *)
(* ================================================================= *)
(** ** Definitions *)
(** For [aexp]s and [bexp]s with variables, the definition we want is
clear. We say that two [aexp]s or [bexp]s are _behaviorally
equivalent_ if they evaluate to the same result in every state. *)
Definition aequiv (a1 a2 : aexp) : Prop :=
forall (st:state),
aeval st a1 = aeval st a2.
Definition bequiv (b1 b2 : bexp) : Prop :=
forall (st:state),
beval st b1 = beval st b2.
(** Here are some simple examples of equivalences of arithmetic
and boolean expressions. *)
Theorem aequiv_example:
aequiv (AMinus (AId X) (AId X)) (ANum 0).
Proof.
intros st. simpl. omega.
Qed.
Theorem bequiv_example:
bequiv (BEq (AMinus (AId X) (AId X)) (ANum 0)) BTrue.
Proof.
intros st. unfold beval.
rewrite aequiv_example. reflexivity.
Qed.
(** For commands, the situation is a little more subtle. We can't
simply say "two commands are behaviorally equivalent if they
evaluate to the same ending state whenever they are started in the
same initial state," because some commands, when run in some
starting states, don't terminate in any final state at all! What
we need instead is this: two commands are behaviorally equivalent
if, for any given starting state, they either (1) both diverge
or (2) both terminate in the same final state. A compact way to
express this is "if the first one terminates in a particular state
then so does the second, and vice versa." *)
Definition cequiv (c1 c2 : com) : Prop :=
forall (st st' : state),
(c1 / st \\ st') <-> (c2 / st \\ st').
(* ================================================================= *)
(** ** Simple Examples *)
(** For examples of command equivalence, let's start by looking at
some trivial program transformations involving [SKIP]: *)
Theorem skip_left: forall c,
cequiv (SKIP;; c) c.
Proof.
(* WORKED IN CLASS *)
intros c st st'.
split; intros H.
- (* -> *)
inversion H. subst.
inversion H2. subst.
assumption.
- (* <- *)
apply E_Seq with st.
apply E_Skip.
assumption.
Qed.
(** **** Exercise: 2 stars (skip_right) *)
(** Prove that adding a [SKIP] after a command results in an
equivalent program *)
Theorem skip_right: forall c,
cequiv
(c ;; SKIP)
c.
Proof.
intros c st st'.
split; intros H.
- (* -> *)
inversion H. subst.
inversion H5. subst.
assumption.
- (* <- *)
apply E_Seq with st'.
assumption.
apply E_Skip.
Qed.
(** [] *)
(** Similarly, here is a simple transformation that optimizes [IFB]
commands: *)
Theorem IFB_true_simple: forall c1 c2,
cequiv
(IFB BTrue THEN c1 ELSE c2 FI)
c1.
Proof.
intros c1 c2.
split; intros H.
- (* -> *)
inversion H; subst. assumption. inversion H5.
- (* <- *)
apply E_IfTrue. reflexivity. assumption. Qed.
(** Of course, few programmers would be tempted to write a conditional
whose guard is literally [BTrue]. A more interesting case is when
the guard is _equivalent_ to true: *)
(** _Theorem_: If [b] is equivalent to [BTrue], then [IFB b THEN c1
ELSE c2 FI] is equivalent to [c1]. *)
(**
_Proof_:
- ([->]) We must show, for all [st] and [st'], that if [IFB b
THEN c1 ELSE c2 FI / st \\ st'] then [c1 / st \\ st'].
Proceed by cases on the rules that could possibly have been
used to show [IFB b THEN c1 ELSE c2 FI / st \\ st'], namely
[E_IfTrue] and [E_IfFalse].
- Suppose the final rule rule in the derivation of [IFB b THEN
c1 ELSE c2 FI / st \\ st'] was [E_IfTrue]. We then have, by
the premises of [E_IfTrue], that [c1 / st \\ st']. This is
exactly what we set out to prove.
- On the other hand, suppose the final rule in the derivation
of [IFB b THEN c1 ELSE c2 FI / st \\ st'] was [E_IfFalse].
We then know that [beval st b = false] and [c2 / st \\ st'].
Recall that [b] is equivalent to [BTrue], i.e., forall [st],
[beval st b = beval st BTrue]. In particular, this means
that [beval st b = true], since [beval st BTrue = true]. But
this is a contradiction, since [E_IfFalse] requires that
[beval st b = false]. Thus, the final rule could not have
been [E_IfFalse].
- ([<-]) We must show, for all [st] and [st'], that if [c1 / st
\\ st'] then [IFB b THEN c1 ELSE c2 FI / st \\ st'].
Since [b] is equivalent to [BTrue], we know that [beval st b] =
[beval st BTrue] = [true]. Together with the assumption that
[c1 / st \\ st'], we can apply [E_IfTrue] to derive [IFB b THEN
c1 ELSE c2 FI / st \\ st']. []
Here is the formal version of this proof: *)
Theorem IFB_true: forall b c1 c2,
bequiv b BTrue ->
cequiv
(IFB b THEN c1 ELSE c2 FI)
c1.
Proof.
intros b c1 c2 Hb.
split; intros H.
- (* -> *)
inversion H; subst.
+ (* b evaluates to true *)
assumption.
+ (* b evaluates to false (contradiction) *)
unfold bequiv in Hb. simpl in Hb.
rewrite Hb in H5.
inversion H5.
- (* <- *)
apply E_IfTrue; try assumption.
unfold bequiv in Hb. simpl in Hb.
rewrite Hb. reflexivity. Qed.
(** **** Exercise: 2 stars, recommended (IFB_false) *)
Theorem IFB_false: forall b c1 c2,
bequiv b BFalse ->
cequiv
(IFB b THEN c1 ELSE c2 FI)
c2.
Proof.
intros b c1 c2 Hb.
split ; intros H.
- (* -> *)
unfold bequiv in Hb. simpl in Hb.
inversion H. subst. rewrite -> Hb in H5.
inversion H5. subst. assumption.
- (* <- *)
apply E_IfFalse. unfold bequiv in Hb. simpl in Hb.
apply Hb. assumption.
Qed.
(** [] *)
(** **** Exercise: 3 stars (swap_if_branches) *)
(** Show that we can swap the branches of an IF if we also negate its
guard. *)
Theorem swap_if_branches: forall b e1 e2,
cequiv
(IFB b THEN e1 ELSE e2 FI)
(IFB BNot b THEN e2 ELSE e1 FI).
Proof.
intros b e1 e2. split; intros.
- inversion H. subst.
apply E_IfFalse. subst. simpl. apply negb_false_iff. assumption. assumption.
apply E_IfTrue. subst. simpl. apply negb_true_iff. assumption. assumption.
- inversion H; subst.
apply E_IfFalse. simpl in H5. apply negb_true_iff in H5. assumption. assumption.
apply E_IfTrue. simpl in H5. apply negb_false_iff in H5. assumption. assumption.
Qed.
(** [] *)
(** For [WHILE] loops, we can give a similar pair of theorems. A loop
whose guard is equivalent to [BFalse] is equivalent to [SKIP],
while a loop whose guard is equivalent to [BTrue] is equivalent to
[WHILE BTrue DO SKIP END] (or any other non-terminating program).
The first of these facts is easy. *)
Theorem WHILE_false : forall b c,
bequiv b BFalse ->
cequiv
(WHILE b DO c END)
SKIP.
Proof.
intros b c Hb. split; intros H.
- (* -> *)
inversion H; subst.
+ (* E_WhileEnd *)
apply E_Skip.
+ (* E_WhileLoop *)
rewrite Hb in H2. inversion H2.
- (* <- *)
inversion H; subst.
apply E_WhileEnd.
rewrite Hb.
reflexivity. Qed.
(** **** Exercise: 2 stars, advanced, optional (WHILE_false_informal) *)
(** Write an informal proof of [WHILE_false].
(* FILL IN HERE *)
[]
*)
(** To prove the second fact, we need an auxiliary lemma stating that
[WHILE] loops whose guards are equivalent to [BTrue] never
terminate. *)
(** _Lemma_: If [b] is equivalent to [BTrue], then it cannot be the
case that [(WHILE b DO c END) / st \\ st'].
_Proof_: Suppose that [(WHILE b DO c END) / st \\ st']. We show,
by induction on a derivation of [(WHILE b DO c END) / st \\ st'],
that this assumption leads to a contradiction.
- Suppose [(WHILE b DO c END) / st \\ st'] is proved using rule
[E_WhileEnd]. Then by assumption [beval st b = false]. But
this contradicts the assumption that [b] is equivalent to
[BTrue].
- Suppose [(WHILE b DO c END) / st \\ st'] is proved using rule
[E_WhileLoop]. Then we are given the induction hypothesis
that [(WHILE b DO c END) / st \\ st'] is contradictory, which
is exactly what we are trying to prove!
- Since these are the only rules that could have been used to
prove [(WHILE b DO c END) / st \\ st'], the other cases of
the induction are immediately contradictory. [] *)
Lemma WHILE_true_nonterm : forall b c st st',
bequiv b BTrue ->
~( (WHILE b DO c END) / st \\ st' ).
Proof.
(* WORKED IN CLASS *)
intros b c st st' Hb.
intros H.
remember (WHILE b DO c END) as cw eqn:Heqcw.
induction H;
(* Most rules don't apply, and we can rule them out
by inversion *)
inversion Heqcw; subst; clear Heqcw.
(* The two interesting cases are the ones for WHILE loops: *)
- (* E_WhileEnd *) (* contradictory -- b is always true! *)
unfold bequiv in Hb.
(* [rewrite] is able to instantiate the quantifier in [st] *)
rewrite Hb in H. inversion H.
- (* E_WhileLoop *) (* immediate from the IH *)
apply IHceval2. reflexivity. Qed.
(** **** Exercise: 2 stars, optional (WHILE_true_nonterm_informal) *)
(** Explain what the lemma [WHILE_true_nonterm] means in English.
(* FILL IN HERE *)
*)
(** [] *)
(** **** Exercise: 2 stars, recommended (WHILE_true) *)
(** Prove the following theorem. _Hint_: You'll want to use
[WHILE_true_nonterm] here. *)
Theorem WHILE_true: forall b c,
bequiv b BTrue ->
cequiv
(WHILE b DO c END)
(WHILE BTrue DO SKIP END).
Proof.
unfold cequiv. intros b c Hb st st'; split; intros Hw.
remember (WHILE b DO c END) as cw eqn:Heqcw.
induction Hw; inversion Heqcw; subst; clear Heqcw.
- unfold bequiv in Hb. simpl in Hb. rewrite Hb in H. inversion H.
- apply WHILE_true_nonterm in Hw2. inversion Hw2. auto.
- apply WHILE_true_nonterm in Hw. inversion Hw.
unfold bequiv. simpl. intros st1. reflexivity.
Qed.
(** [] *)
(** A more interesting fact about [WHILE] commands is that any finite
number of copies of the body can be "unrolled" without changing
meaning. Unrolling is a common transformation in real compilers. *)
Theorem loop_unrolling: forall b c,
cequiv
(WHILE b DO c END)
(IFB b THEN (c ;; WHILE b DO c END) ELSE SKIP FI).
Proof.
(* WORKED IN CLASS *)
intros b c st st'.
split; intros Hce.
- (* -> *)
inversion Hce; subst.
+ (* loop doesn't run *)
apply E_IfFalse. assumption. apply E_Skip.
+ (* loop runs *)
apply E_IfTrue. assumption.
apply E_Seq with (st' := st'0). assumption. assumption.
- (* <- *)
inversion Hce; subst.
+ (* loop runs *)
inversion H5; subst.
apply E_WhileLoop with (st' := st'0).
assumption. assumption. assumption.
+ (* loop doesn't run *)
inversion H5; subst. apply E_WhileEnd. assumption. Qed.
(** **** Exercise: 2 stars, optional (seq_assoc) *)
Theorem seq_assoc : forall c1 c2 c3,
cequiv ((c1;;c2);;c3) (c1;;(c2;;c3)).
Proof.
unfold cequiv. split; intros.
inversion H. inversion H2. subst.
- apply E_Seq with st'1. assumption.
apply E_Seq with st'0. assumption. assumption.
- inversion H. inversion H5. subst.
apply E_Seq with st'1.
apply E_Seq with st'0.
assumption. assumption. assumption.
Qed.
(** [] *)
(** Proving program properties involving assignments is one place
where the Functional Extensionality axiom often comes in handy. *)
Theorem identity_assignment : forall (X:id),
cequiv
(X ::= AId X)
SKIP.
Proof.
intros. split; intro H.
- (* -> *)
inversion H; subst. simpl.
replace (t_update st X (st X)) with st.
+ constructor.
+ apply functional_extensionality. intro.
rewrite t_update_same; reflexivity.
- (* <- *)
replace st' with (t_update st' X (aeval st' (AId X))).
+ inversion H. subst. apply E_Ass. reflexivity.
+ apply functional_extensionality. intro.
rewrite t_update_same. reflexivity.
Qed.
(** **** Exercise: 2 stars, recommended (assign_aequiv) *)
Theorem assign_aequiv : forall X e,
aequiv (AId X) e ->
cequiv SKIP (X ::= e).
Proof.
intros X e He; split; intros H.
- replace st' with (t_update st X (aeval st e)).
constructor. auto.
apply functional_extensionality. intros.
unfold aequiv in He. simpl in He. rewrite <- He.
rewrite t_update_same. inversion H. subst. auto.
- inversion H. subst.
replace (t_update st X (aeval st e)) with st.
apply E_Skip.
apply functional_extensionality.
unfold aequiv in He. simpl in He. rewrite <- He with st.
rewrite t_update_same. auto.
Qed.
(** [] *)
(** **** Exercise: 2 stars (equiv_classes) *)
(** Given the following programs, group together those that are
equivalent in Imp. Your answer should be given as a list of lists,
where each sub-list represents a group of equivalent programs. For
example, if you think programs (a) through (h) are all equivalent
to each other, but not to (i), your answer should look like this:
[ [prog_a;prog_b;prog_c;prog_d;prog_e;prog_f;prog_g;prog_h] ;
[prog_i] ]
Write down your answer below in the definition of
[equiv_classes]. *)
Definition prog_a : com :=
WHILE BNot (BLe (AId X) (ANum 0)) DO
X ::= APlus (AId X) (ANum 1)
END.
Definition prog_b : com :=
IFB BEq (AId X) (ANum 0) THEN
X ::= APlus (AId X) (ANum 1);;
Y ::= ANum 1
ELSE
Y ::= ANum 0
FI;;
X ::= AMinus (AId X) (AId Y);;
Y ::= ANum 0.
Definition prog_c : com :=
SKIP.
Definition prog_d : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
X ::= APlus (AMult (AId X) (AId Y)) (ANum 1)
END.
Definition prog_e : com :=
Y ::= ANum 0.
Definition prog_f : com :=
Y ::= APlus (AId X) (ANum 1);;
WHILE BNot (BEq (AId X) (AId Y)) DO
Y ::= APlus (AId X) (ANum 1)
END.
Definition prog_g : com :=
WHILE BTrue DO
SKIP
END.
Definition prog_h : com :=
WHILE BNot (BEq (AId X) (AId X)) DO
X ::= APlus (AId X) (ANum 1)
END.
Definition prog_i : com :=
WHILE BNot (BEq (AId X) (AId Y)) DO
X ::= APlus (AId Y) (ANum 1)
END.
Definition equiv_classes : list (list com)
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
(** [] *)
(* ################################################################# *)
(** * Properties of Behavioral Equivalence *)
(** We next consider some fundamental properties of the program
equivalence relations. *)
(* ================================================================= *)
(** ** Behavioral Equivalence Is an Equivalence *)
(** First, we verify that the equivalences on [aexps], [bexps], and
[com]s really are _equivalences_ -- i.e., that they are reflexive,
symmetric, and transitive. The proofs are all easy. *)
Lemma refl_aequiv : forall (a : aexp), aequiv a a.
Proof.
intros a st. reflexivity. Qed.
Lemma sym_aequiv : forall (a1 a2 : aexp),
aequiv a1 a2 -> aequiv a2 a1.
Proof.
intros a1 a2 H. intros st. symmetry. apply H. Qed.
Lemma trans_aequiv : forall (a1 a2 a3 : aexp),
aequiv a1 a2 -> aequiv a2 a3 -> aequiv a1 a3.
Proof.
unfold aequiv. intros a1 a2 a3 H12 H23 st.
rewrite (H12 st). rewrite (H23 st). reflexivity. Qed.
Lemma refl_bequiv : forall (b : bexp), bequiv b b.
Proof.
unfold bequiv. intros b st. reflexivity. Qed.
Lemma sym_bequiv : forall (b1 b2 : bexp),
bequiv b1 b2 -> bequiv b2 b1.
Proof.
unfold bequiv. intros b1 b2 H. intros st. symmetry. apply H. Qed.
Lemma trans_bequiv : forall (b1 b2 b3 : bexp),
bequiv b1 b2 -> bequiv b2 b3 -> bequiv b1 b3.
Proof.
unfold bequiv. intros b1 b2 b3 H12 H23 st.
rewrite (H12 st). rewrite (H23 st). reflexivity. Qed.
Lemma refl_cequiv : forall (c : com), cequiv c c.
Proof.
unfold cequiv. intros c st st'. apply iff_refl. Qed.
Lemma sym_cequiv : forall (c1 c2 : com),
cequiv c1 c2 -> cequiv c2 c1.
Proof.
unfold cequiv. intros c1 c2 H st st'.
assert (c1 / st \\ st' <-> c2 / st \\ st') as H'.
{ (* Proof of assertion *) apply H. }
apply iff_sym. assumption.
Qed.
Lemma iff_trans : forall (P1 P2 P3 : Prop),
(P1 <-> P2) -> (P2 <-> P3) -> (P1 <-> P3).
Proof.
intros P1 P2 P3 H12 H23.
inversion H12. inversion H23.
split; intros A.
apply H1. apply H. apply A.
apply H0. apply H2. apply A. Qed.
Lemma trans_cequiv : forall (c1 c2 c3 : com),
cequiv c1 c2 -> cequiv c2 c3 -> cequiv c1 c3.
Proof.
unfold cequiv. intros c1 c2 c3 H12 H23 st st'.
apply iff_trans with (c2 / st \\ st'). apply H12. apply H23. Qed.
(* ================================================================= *)
(** ** Behavioral Equivalence Is a Congruence *)
(** Less obviously, behavioral equivalence is also a _congruence_.
That is, the equivalence of two subprograms implies the
equivalence of the larger programs in which they are embedded:
aequiv a1 a1'
-----------------------------
cequiv (i ::= a1) (i ::= a1')
cequiv c1 c1'
cequiv c2 c2'
------------------------
cequiv (c1;;c2) (c1';;c2')
...and so on for the other forms of commands. *)
(** (Note that we are using the inference rule notation here not
as part of a definition, but simply to write down some valid
implications in a readable format. We prove these implications
below.) *)
(** We will see a concrete example of why these congruence
properties are important in the following section (in the proof of
[fold_constants_com_sound]), but the main idea is that they allow
us to replace a small part of a large program with an equivalent
small part and know that the whole large programs are equivalent
_without_ doing an explicit proof about the non-varying parts --
i.e., the "proof burden" of a small change to a large program is
proportional to the size of the change, not the program. *)
Theorem CAss_congruence : forall i a1 a1',
aequiv a1 a1' ->
cequiv (CAss i a1) (CAss i a1').
Proof.
intros i a1 a2 Heqv st st'.
split; intros Hceval.
- (* -> *)
inversion Hceval. subst. apply E_Ass.
rewrite Heqv. reflexivity.
- (* <- *)
inversion Hceval. subst. apply E_Ass.
rewrite Heqv. reflexivity. Qed.
(** The congruence property for loops is a little more interesting,
since it requires induction.
_Theorem_: Equivalence is a congruence for [WHILE] -- that is, if
[b1] is equivalent to [b1'] and [c1] is equivalent to [c1'], then
[WHILE b1 DO c1 END] is equivalent to [WHILE b1' DO c1' END].
_Proof_: Suppose [b1] is equivalent to [b1'] and [c1] is
equivalent to [c1']. We must show, for every [st] and [st'], that
[WHILE b1 DO c1 END / st \\ st'] iff [WHILE b1' DO c1' END / st
\\ st']. We consider the two directions separately.
- ([->]) We show that [WHILE b1 DO c1 END / st \\ st'] implies
[WHILE b1' DO c1' END / st \\ st'], by induction on a
derivation of [WHILE b1 DO c1 END / st \\ st']. The only
nontrivial cases are when the final rule in the derivation is
[E_WhileEnd] or [E_WhileLoop].
- [E_WhileEnd]: In this case, the form of the rule gives us
[beval st b1 = false] and [st = st']. But then, since
[b1] and [b1'] are equivalent, we have [beval st b1' =
false], and [E-WhileEnd] applies, giving us [WHILE b1' DO
c1' END / st \\ st'], as required.
- [E_WhileLoop]: The form of the rule now gives us [beval st
b1 = true], with [c1 / st \\ st'0] and [WHILE b1 DO c1
END / st'0 \\ st'] for some state [st'0], with the
induction hypothesis [WHILE b1' DO c1' END / st'0 \\
st'].
Since [c1] and [c1'] are equivalent, we know that [c1' /
st \\ st'0]. And since [b1] and [b1'] are equivalent, we
have [beval st b1' = true]. Now [E-WhileLoop] applies,
giving us [WHILE b1' DO c1' END / st \\ st'], as
required.
- ([<-]) Similar. [] *)
Theorem CWhile_congruence : forall b1 b1' c1 c1',
bequiv b1 b1' -> cequiv c1 c1' ->
cequiv (WHILE b1 DO c1 END) (WHILE b1' DO c1' END).
Proof.
(* WORKED IN CLASS *)
unfold bequiv,cequiv.
intros b1 b1' c1 c1' Hb1e Hc1e st st'.
split; intros Hce.
- (* -> *)
remember (WHILE b1 DO c1 END) as cwhile
eqn:Heqcwhile.
induction Hce; inversion Heqcwhile; subst.
+ (* E_WhileEnd *)
apply E_WhileEnd. rewrite <- Hb1e. apply H.
+ (* E_WhileLoop *)
apply E_WhileLoop with (st' := st').
* (* show loop runs *) rewrite <- Hb1e. apply H.
* (* body execution *)
apply (Hc1e st st'). apply Hce1.
* (* subsequent loop execution *)
apply IHHce2. reflexivity.
- (* <- *)
remember (WHILE b1' DO c1' END) as c'while
eqn:Heqc'while.
induction Hce; inversion Heqc'while; subst.
+ (* E_WhileEnd *)
apply E_WhileEnd. rewrite -> Hb1e. apply H.
+ (* E_WhileLoop *)
apply E_WhileLoop with (st' := st').
* (* show loop runs *) rewrite -> Hb1e. apply H.
* (* body execution *)
apply (Hc1e st st'). apply Hce1.
* (* subsequent loop execution *)
apply IHHce2. reflexivity. Qed.
(** **** Exercise: 3 stars, optional (CSeq_congruence) *)
Theorem CSeq_congruence : forall c1 c1' c2 c2',
cequiv c1 c1' -> cequiv c2 c2' ->
cequiv (c1;;c2) (c1';;c2').
Proof.
unfold cequiv. intros c1 c1' c2 c2' Hc1 Hc2.
split; intros H0.
- inversion H0; subst. apply E_Seq with st'0.
apply Hc1. assumption.
apply Hc2. assumption.
- inversion H0; subst. apply E_Seq with st'0.
apply Hc1. assumption.
apply Hc2. assumption.
Qed.
(** [] *)
(** **** Exercise: 3 stars (CIf_congruence) *)
Theorem CIf_congruence : forall b b' c1 c1' c2 c2',
bequiv b b' -> cequiv c1 c1' -> cequiv c2 c2' ->
cequiv (IFB b THEN c1 ELSE c2 FI)
(IFB b' THEN c1' ELSE c2' FI).
Proof.
unfold cequiv.
intros b b' c1 c1' c2 c2' Hbb' Hc1c1' Hc2c2'.
split; subst.
- intros H. inversion H; subst.
+ apply E_IfTrue. rewrite <- Hbb'. assumption. apply Hc1c1'. assumption.
+ apply E_IfFalse. rewrite <- Hbb'. assumption. apply Hc2c2'. assumption.
- intros H. inversion H; subst.
+ apply E_IfTrue. rewrite -> Hbb'. assumption. apply Hc1c1'. assumption.
+ apply E_IfFalse. rewrite -> Hbb'. assumption. apply Hc2c2'. assumption.
Qed.
(** [] *)
(** For example, here are two equivalent programs and a proof of their
equivalence... *)
Example congruence_example:
cequiv
(* Program 1: *)
(X ::= ANum 0;;
IFB (BEq (AId X) (ANum 0))
THEN
Y ::= ANum 0
ELSE
Y ::= ANum 42
FI)
(* Program 2: *)
(X ::= ANum 0;;
IFB (BEq (AId X) (ANum 0))
THEN
Y ::= AMinus (AId X) (AId X) (* <--- changed here *)
ELSE
Y ::= ANum 42
FI).
Proof.
apply CSeq_congruence.
apply refl_cequiv.
apply CIf_congruence.
apply refl_bequiv.
apply CAss_congruence. unfold aequiv. simpl.
symmetry. apply minus_diag.
apply refl_cequiv.
Qed.
(** **** Exercise: 3 stars, advanced, optional (not_congr) *)
(** We've shown that the [cequiv] relation is both an equivalence and
a congruence on commands. Can you think of a relation on commands
that is an equivalence but _not_ a congruence? *)
(* FILL IN HERE *)
(** [] *)
(* ################################################################# *)
(** * Program Transformations *)
(** A _program transformation_ is a function that takes a program as
input and produces some variant of the program as output.
Compiler optimizations such as constant folding are a canonical
example, but there are many others. *)
(** A program transformation is _sound_ if it preserves the
behavior of the original program. *)
Definition atrans_sound (atrans : aexp -> aexp) : Prop :=
forall (a : aexp),
aequiv a (atrans a).
Definition btrans_sound (btrans : bexp -> bexp) : Prop :=
forall (b : bexp),
bequiv b (btrans b).
Definition ctrans_sound (ctrans : com -> com) : Prop :=
forall (c : com),
cequiv c (ctrans c).
(* ================================================================= *)
(** ** The Constant-Folding Transformation *)
(** An expression is _constant_ when it contains no variable
references.
Constant folding is an optimization that finds constant
expressions and replaces them by their values. *)
Fixpoint fold_constants_aexp (a : aexp) : aexp :=
match a with
| ANum n => ANum n
| AId i => AId i
| APlus a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2)
with
| (ANum n1, ANum n2) => ANum (n1 + n2)
| (a1', a2') => APlus a1' a2'
end
| AMinus a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2)
with
| (ANum n1, ANum n2) => ANum (n1 - n2)
| (a1', a2') => AMinus a1' a2'
end
| AMult a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2)
with
| (ANum n1, ANum n2) => ANum (n1 * n2)
| (a1', a2') => AMult a1' a2'
end
end.
Example fold_aexp_ex1 :
fold_constants_aexp
(AMult (APlus (ANum 1) (ANum 2)) (AId X))
= AMult (ANum 3) (AId X).
Proof. reflexivity. Qed.
(** Note that this version of constant folding doesn't eliminate
trivial additions, etc. -- we are focusing attention on a single
optimization for the sake of simplicity. It is not hard to
incorporate other ways of simplifying expressions; the definitions
and proofs just get longer. *)
Example fold_aexp_ex2 :
fold_constants_aexp
(AMinus (AId X) (APlus (AMult (ANum 0) (ANum 6))
(AId Y)))
= AMinus (AId X) (APlus (ANum 0) (AId Y)).
Proof. reflexivity. Qed.
(** Not only can we lift [fold_constants_aexp] to [bexp]s (in the
[BEq] and [BLe] cases); we can also look for constant _boolean_
expressions and evaluate them in-place. *)
Fixpoint fold_constants_bexp (b : bexp) : bexp :=
match b with
| BTrue => BTrue
| BFalse => BFalse
| BEq a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) =>
if beq_nat n1 n2 then BTrue else BFalse
| (a1', a2') =>
BEq a1' a2'
end
| BLe a1 a2 =>
match (fold_constants_aexp a1, fold_constants_aexp a2) with
| (ANum n1, ANum n2) =>
if leb n1 n2 then BTrue else BFalse
| (a1', a2') =>
BLe a1' a2'
end
| BNot b1 =>
match (fold_constants_bexp b1) with
| BTrue => BFalse
| BFalse => BTrue
| b1' => BNot b1'
end
| BAnd b1 b2 =>
match (fold_constants_bexp b1, fold_constants_bexp b2) with
| (BTrue, BTrue) => BTrue
| (BTrue, BFalse) => BFalse
| (BFalse, BTrue) => BFalse
| (BFalse, BFalse) => BFalse
| (b1', b2') => BAnd b1' b2'
end
end.
Example fold_bexp_ex1 :
fold_constants_bexp (BAnd BTrue (BNot (BAnd BFalse BTrue)))
= BTrue.
Proof. reflexivity. Qed.
Example fold_bexp_ex2 :
fold_constants_bexp
(BAnd (BEq (AId X) (AId Y))
(BEq (ANum 0)
(AMinus (ANum 2) (APlus (ANum 1)
(ANum 1)))))
= BAnd (BEq (AId X) (AId Y)) BTrue.
Proof. reflexivity. Qed.
(** To fold constants in a command, we apply the appropriate folding
functions on all embedded expressions. *)
Fixpoint fold_constants_com (c : com) : com :=
match c with
| SKIP =>
SKIP
| i ::= a =>
CAss i (fold_constants_aexp a)
| c1 ;; c2 =>
(fold_constants_com c1) ;; (fold_constants_com c2)
| IFB b THEN c1 ELSE c2 FI =>
match fold_constants_bexp b with
| BTrue => fold_constants_com c1
| BFalse => fold_constants_com c2
| b' => IFB b' THEN fold_constants_com c1
ELSE fold_constants_com c2 FI
end
| WHILE b DO c END =>
match fold_constants_bexp b with
| BTrue => WHILE BTrue DO SKIP END
| BFalse => SKIP
| b' => WHILE b' DO (fold_constants_com c) END
end
end.
Example fold_com_ex1 :
fold_constants_com
(* Original program: *)
(X ::= APlus (ANum 4) (ANum 5);;
Y ::= AMinus (AId X) (ANum 3);;
IFB BEq (AMinus (AId X) (AId Y))
(APlus (ANum 2) (ANum 4)) THEN
SKIP
ELSE
Y ::= ANum 0
FI;;
IFB BLe (ANum 0)
(AMinus (ANum 4) (APlus (ANum 2) (ANum 1)))
THEN
Y ::= ANum 0
ELSE
SKIP
FI;;
WHILE BEq (AId Y) (ANum 0) DO
X ::= APlus (AId X) (ANum 1)
END)
= (* After constant folding: *)
(X ::= ANum 9;;
Y ::= AMinus (AId X) (ANum 3);;
IFB BEq (AMinus (AId X) (AId Y)) (ANum 6) THEN
SKIP
ELSE
(Y ::= ANum 0)
FI;;
Y ::= ANum 0;;
WHILE BEq (AId Y) (ANum 0) DO
X ::= APlus (AId X) (ANum 1)
END).
Proof. reflexivity. Qed.
(* ================================================================= *)
(** ** Soundness of Constant Folding *)
(** Now we need to show that what we've done is correct. *)
(** Here's the proof for arithmetic expressions: *)
Theorem fold_constants_aexp_sound :
atrans_sound fold_constants_aexp.
Proof.
unfold atrans_sound. intros a. unfold aequiv. intros st.
induction a; simpl;
(* ANum and AId follow immediately *)
try reflexivity;
(* APlus, AMinus, and AMult follow from the IH
and the observation that
aeval st (APlus a1 a2)
= ANum ((aeval st a1) + (aeval st a2))
= aeval st (ANum ((aeval st a1) + (aeval st a2)))
(and similarly for AMinus/minus and AMult/mult) *)
try (destruct (fold_constants_aexp a1);
destruct (fold_constants_aexp a2);
rewrite IHa1; rewrite IHa2; reflexivity). Qed.
(** **** Exercise: 3 stars, optional (fold_bexp_Eq_informal) *)
(** Here is an informal proof of the [BEq] case of the soundness
argument for boolean expression constant folding. Read it
carefully and compare it to the formal proof that follows. Then
fill in the [BLe] case of the formal proof (without looking at the
[BEq] case, if possible).
_Theorem_: The constant folding function for booleans,
[fold_constants_bexp], is sound.
_Proof_: We must show that [b] is equivalent to [fold_constants_bexp],
for all boolean expressions [b]. Proceed by induction on [b]. We
show just the case where [b] has the form [BEq a1 a2].
In this case, we must show
beval st (BEq a1 a2)
= beval st (fold_constants_bexp (BEq a1 a2)).
There are two cases to consider:
- First, suppose [fold_constants_aexp a1 = ANum n1] and
[fold_constants_aexp a2 = ANum n2] for some [n1] and [n2].
In this case, we have
fold_constants_bexp (BEq a1 a2)
= if beq_nat n1 n2 then BTrue else BFalse
and
beval st (BEq a1 a2)
= beq_nat (aeval st a1) (aeval st a2).
By the soundness of constant folding for arithmetic
expressions (Lemma [fold_constants_aexp_sound]), we know
aeval st a1
= aeval st (fold_constants_aexp a1)
= aeval st (ANum n1)
= n1
and
aeval st a2
= aeval st (fold_constants_aexp a2)
= aeval st (ANum n2)
= n2,
so
beval st (BEq a1 a2)
= beq_nat (aeval a1) (aeval a2)
= beq_nat n1 n2.
Also, it is easy to see (by considering the cases [n1 = n2] and
[n1 <> n2] separately) that
beval st (if beq_nat n1 n2 then BTrue else BFalse)
= if beq_nat n1 n2 then beval st BTrue else beval st BFalse
= if beq_nat n1 n2 then true else false
= beq_nat n1 n2.
So
beval st (BEq a1 a2)
= beq_nat n1 n2.
= beval st (if beq_nat n1 n2 then BTrue else BFalse),
as required.
- Otherwise, one of [fold_constants_aexp a1] and
[fold_constants_aexp a2] is not a constant. In this case, we
must show
beval st (BEq a1 a2)
= beval st (BEq (fold_constants_aexp a1)
(fold_constants_aexp a2)),
which, by the definition of [beval], is the same as showing
beq_nat (aeval st a1) (aeval st a2)
= beq_nat (aeval st (fold_constants_aexp a1))
(aeval st (fold_constants_aexp a2)).
But the soundness of constant folding for arithmetic
expressions ([fold_constants_aexp_sound]) gives us
aeval st a1 = aeval st (fold_constants_aexp a1)
aeval st a2 = aeval st (fold_constants_aexp a2),
completing the case. []
*)
Theorem fold_constants_bexp_sound:
btrans_sound fold_constants_bexp.
Proof.
unfold btrans_sound. intros b. unfold bequiv. intros st.
induction b;
(* BTrue and BFalse are immediate *)
try reflexivity.
- (* BEq *)
rename a into a1. rename a0 into a2. simpl.
(** (Doing induction when there are a lot of constructors makes
specifying variable names a chore, but Coq doesn't always
choose nice variable names. We can rename entries in the
context with the [rename] tactic: [rename a into a1] will
change [a] to [a1] in the current goal and context.) *)
remember (fold_constants_aexp a1) as a1' eqn:Heqa1'.
remember (fold_constants_aexp a2) as a2' eqn:Heqa2'.
replace (aeval st a1) with (aeval st a1') by
(subst a1'; rewrite <- fold_constants_aexp_sound; reflexivity).
replace (aeval st a2) with (aeval st a2') by
(subst a2'; rewrite <- fold_constants_aexp_sound; reflexivity).
destruct a1'; destruct a2'; try reflexivity.
(* The only interesting case is when both a1 and a2
become constants after folding *)
simpl. destruct (beq_nat n n0); reflexivity.
- (* BLe *)
rename a into a1. rename a0 into a2. simpl.
remember (BLe a1 a2) as b.
remember (fold_constants_bexp b) as b'.
remember (fold_constants_aexp a1) as a1'.
remember (fold_constants_aexp a2) as a2'.
replace (aeval st a1) with (aeval st a1') by
(subst a1'; rewrite <- fold_constants_aexp_sound; reflexivity).
replace (aeval st a2) with (aeval st a2') by
(subst a2'; rewrite <- fold_constants_aexp_sound; reflexivity).
destruct a1'; destruct a2'; try reflexivity.
simpl. subst. destruct (n <=? n0); simpl; reflexivity.
- (* BNot *)
simpl. remember (fold_constants_bexp b) as b' eqn:Heqb'.
rewrite IHb.
destruct b'; reflexivity.
- (* BAnd *)
simpl.
remember (fold_constants_bexp b1) as b1' eqn:Heqb1'.
remember (fold_constants_bexp b2) as b2' eqn:Heqb2'.
rewrite IHb1. rewrite IHb2.
destruct b1'; destruct b2'; reflexivity.
Qed.
(** [] *)
(** **** Exercise: 3 stars (fold_constants_com_sound) *)
(** Complete the [WHILE] case of the following proof. *)
Theorem fold_constants_com_sound :
ctrans_sound fold_constants_com.
Proof.
unfold ctrans_sound. intros c.
induction c; simpl.
- (* SKIP *) apply refl_cequiv.
- (* ::= *) apply CAss_congruence.
apply fold_constants_aexp_sound.
- (* ;; *) apply CSeq_congruence; assumption.
- (* IFB *)
assert (bequiv b (fold_constants_bexp b)). {
apply fold_constants_bexp_sound. }
destruct (fold_constants_bexp b) eqn:Heqb;
try (apply CIf_congruence; assumption).
(* (If the optimization doesn't eliminate the if, then the
result is easy to prove from the IH and
[fold_constants_bexp_sound].) *)
+ (* b always true *)
apply trans_cequiv with c1; try assumption.
apply IFB_true; assumption.
+ (* b always false *)
apply trans_cequiv with c2; try assumption.
apply IFB_false; assumption.
- assert (bequiv b (fold_constants_bexp b)).
{ apply fold_constants_bexp_sound. }
remember (fold_constants_bexp b) as b'.
destruct b'; try (apply CWhile_congruence; assumption).
+ apply WHILE_true. assumption.
+ apply WHILE_false. assumption.
Qed.
(** [] *)
(* ----------------------------------------------------------------- *)
(** *** Soundness of (0 + n) Elimination, Redux *)
(** **** Exercise: 4 stars, advanced, optional (optimize_0plus) *)
(** Recall the definition [optimize_0plus] from the [Imp] chapter:
Fixpoint optimize_0plus (e:aexp) : aexp :=
match e with
| ANum n =>
ANum n
| APlus (ANum 0) e2 =>
optimize_0plus e2
| APlus e1 e2 =>
APlus (optimize_0plus e1) (optimize_0plus e2)
| AMinus e1 e2 =>
AMinus (optimize_0plus e1) (optimize_0plus e2)
| AMult e1 e2 =>
AMult (optimize_0plus e1) (optimize_0plus e2)
end.
Note that this function is defined over the old [aexp]s,
without states.
Write a new version of this function that accounts for variables,
plus analogous ones for [bexp]s and commands:
optimize_0plus_aexp
optimize_0plus_bexp
optimize_0plus_com
Prove that these three functions are sound, as we did for
[fold_constants_*]. Make sure you use the congruence lemmas in
the proof of [optimize_0plus_com] -- otherwise it will be _long_!
Then define an optimizer on commands that first folds
constants (using [fold_constants_com]) and then eliminates [0 + n]
terms (using [optimize_0plus_com]).
- Give a meaningful example of this optimizer's output.
- Prove that the optimizer is sound. (This part should be _very_
easy.) *)
Fixpoint optimize_0plus_aexp (e:aexp) : aexp :=
match e with
| ANum n =>
ANum n
| AId X =>
AId X
| APlus (ANum 0) e2 =>
optimize_0plus_aexp e2
| APlus e1 e2 =>
APlus (optimize_0plus_aexp e1) (optimize_0plus_aexp e2)
| AMinus e1 e2 =>
AMinus (optimize_0plus_aexp e1) (optimize_0plus_aexp e2)
| AMult e1 e2 =>
AMult (optimize_0plus_aexp e1) (optimize_0plus_aexp e2)
end.
Fixpoint optimize_0plus_bexp (b : bexp) : bexp :=
match b with
| BTrue =>
BTrue
| BFalse =>
BFalse
| BEq a1 a2 =>
BEq (optimize_0plus_aexp a1) (optimize_0plus_aexp a2)
| BLe a1 a2 =>
BLe (optimize_0plus_aexp a1) (optimize_0plus_aexp a2)
| BNot b1 =>
BNot (optimize_0plus_bexp b1)
| BAnd b1 b2 =>
BAnd (optimize_0plus_bexp b1) (optimize_0plus_bexp b2)
end.
Fixpoint optimize_0plus_com (e : com) : com :=
match e with
| SKIP =>
SKIP
| i ::= a =>
i ::= optimize_0plus_aexp a
| c1;; c2 =>
optimize_0plus_com c1;; optimize_0plus_com c2
| IFB b THEN c1 ELSE c2 FI =>
IFB (optimize_0plus_bexp b) THEN (optimize_0plus_com c1)
ELSE (optimize_0plus_com c2) FI
| WHILE b DO c0 END =>
WHILE (optimize_0plus_bexp b) DO (optimize_0plus_com c0) END
end.
Lemma CSkip_congruence : cequiv SKIP SKIP.
Proof. apply refl_cequiv. Qed.
Theorem optimize_0plus_aexp_sound : atrans_sound optimize_0plus_aexp.
Proof.
unfold atrans_sound. unfold aequiv.
intros a. induction a; subst; simpl; auto.
intros st.
destruct a1;
try destruct n; try rewrite IHa1; try rewrite IHa2; auto.
Qed.
Theorem optimize_0plus_bexp_sound : btrans_sound optimize_0plus_bexp.
Proof.
assert (Ha : forall (a : aexp), aequiv a (optimize_0plus_aexp a)).
{ apply optimize_0plus_aexp_sound. }
unfold btrans_sound. unfold bequiv.
intros b st.
induction b; subst; simpl;
try rewrite <- Ha; try rewrite <- Ha; try reflexivity.
- rewrite <- IHb. reflexivity.
- rewrite <- IHb1. rewrite <- IHb2. reflexivity.
Qed.
Theorem optimize_0plus_com_sound : ctrans_sound optimize_0plus_com.
Proof.
unfold ctrans_sound. intros c.
induction c; simpl.
- apply CSkip_congruence.
- apply CAss_congruence. apply optimize_0plus_aexp_sound.
- apply CSeq_congruence. assumption. assumption.
- apply CIf_congruence. apply optimize_0plus_bexp_sound. assumption. assumption.
- apply CWhile_congruence. apply optimize_0plus_bexp_sound. assumption.
Qed.
Definition fold_constants_then_optimize_0plus (c : com) : com :=
optimize_0plus_com (fold_constants_com c).
Theorem fold_constants_then_optimize_0plus_sound :
ctrans_sound fold_constants_then_optimize_0plus.
Proof.
unfold ctrans_sound. unfold fold_constants_then_optimize_0plus.
intros c. apply trans_cequiv with (fold_constants_com c).
apply fold_constants_com_sound.
apply optimize_0plus_com_sound.
Qed.
(** [] *)
(* ################################################################# *)
(** * Proving That Programs Are _Not_ Equivalent *)
(** Suppose that [c1] is a command of the form [X ::= a1;; Y ::= a2]
and [c2] is the command [X ::= a1;; Y ::= a2'], where [a2'] is
formed by substituting [a1] for all occurrences of [X] in [a2].
For example, [c1] and [c2] might be:
c1 = (X ::= 42 + 53;;
Y ::= Y + X)
c2 = (X ::= 42 + 53;;
Y ::= Y + (42 + 53))
Clearly, this _particular_ [c1] and [c2] are equivalent. Is this
true in general? *)
(** We will see in a moment that it is not, but it is worthwhile
to pause, now, and see if you can find a counter-example on your
own. *)
(** More formally, here is the function that substitutes an arithmetic
expression for each occurrence of a given variable in another
expression: *)
Fixpoint subst_aexp (i : id) (u : aexp) (a : aexp) : aexp :=
match a with
| ANum n =>
ANum n
| AId i' =>
if beq_id i i' then u else AId i'
| APlus a1 a2 =>
APlus (subst_aexp i u a1) (subst_aexp i u a2)
| AMinus a1 a2 =>
AMinus (subst_aexp i u a1) (subst_aexp i u a2)
| AMult a1 a2 =>
AMult (subst_aexp i u a1) (subst_aexp i u a2)
end.
Example subst_aexp_ex :
subst_aexp X (APlus (ANum 42) (ANum 53))
(APlus (AId Y) (AId X))
= (APlus (AId Y) (APlus (ANum 42) (ANum 53))).
Proof. reflexivity. Qed.
(** And here is the property we are interested in, expressing the
claim that commands [c1] and [c2] as described above are
always equivalent. *)
Definition subst_equiv_property := forall i1 i2 a1 a2,
cequiv (i1 ::= a1;; i2 ::= a2)
(i1 ::= a1;; i2 ::= subst_aexp i1 a1 a2).
(** Sadly, the property does _not_ always hold -- i.e., it is not the
case that, for all [i1], [i2], [a1], and [a2],
cequiv (i1 ::= a1;; i2 ::= a2)
(i1 ::= a1;; i2 ::= subst_aexp i1 a1 a2).
To see this, suppose (for a contradiction) that for all [i1], [i2],
[a1], and [a2], we have
cequiv (i1 ::= a1;; i2 ::= a2)
(i1 ::= a1;; i2 ::= subst_aexp i1 a1 a2).
Consider the following program:
X ::= APlus (AId X) (ANum 1);; Y ::= AId X
Note that
(X ::= APlus (AId X) (ANum 1);; Y ::= AId X)
/ empty_state \\ st1,
where [st1 = { X |-> 1, Y |-> 1 }].
By assumption, we know that
cequiv (X ::= APlus (AId X) (ANum 1);;
Y ::= AId X)
(X ::= APlus (AId X) (ANum 1);;
Y ::= APlus (AId X) (ANum 1))
so, by the definition of [cequiv], we have
(X ::= APlus (AId X) (ANum 1);; Y ::= APlus (AId X) (ANum 1))
/ empty_state \\ st1.
But we can also derive
(X ::= APlus (AId X) (ANum 1);; Y ::= APlus (AId X) (ANum 1))
/ empty_state \\ st2,
where [st2 = { X |-> 1, Y |-> 2 }]. But [st1 <> st2], which is a
contradiction, since [ceval] is deterministic! [] *)
Theorem subst_inequiv :
~ subst_equiv_property.
Proof.
unfold subst_equiv_property.
intros Contra.
(* Here is the counterexample: assuming that [subst_equiv_property]
holds allows us to prove that these two programs are
equivalent... *)
remember (X ::= APlus (AId X) (ANum 1);;
Y ::= AId X)
as c1.
remember (X ::= APlus (AId X) (ANum 1);;
Y ::= APlus (AId X) (ANum 1))
as c2.
assert (cequiv c1 c2) by (subst; apply Contra).
(* ... allows us to show that the command [c2] can terminate
in two different final states:
st1 = {X |-> 1, Y |-> 1}
st2 = {X |-> 1, Y |-> 2}. *)
remember (t_update (t_update empty_state X 1) Y 1) as st1.
remember (t_update (t_update empty_state X 1) Y 2) as st2.
assert (H1: c1 / empty_state \\ st1);
assert (H2: c2 / empty_state \\ st2);
try (subst;
apply E_Seq with (st' := (t_update empty_state X 1));
apply E_Ass; reflexivity).
apply H in H1.
(* Finally, we use the fact that evaluation is deterministic
to obtain a contradiction. *)
assert (Hcontra: st1 = st2)
by (apply (ceval_deterministic c2 empty_state); assumption).
assert (Hcontra': st1 Y = st2 Y)
by (rewrite Hcontra; reflexivity).
subst. inversion Hcontra'. Qed.
(** **** Exercise: 4 stars, optional (better_subst_equiv) *)
(** The equivalence we had in mind above was not complete nonsense --
it was actually almost right. To make it correct, we just need to
exclude the case where the variable [X] occurs in the
right-hand-side of the first assignment statement. *)
Inductive var_not_used_in_aexp (X:id) : aexp -> Prop :=
| VNUNum: forall n, var_not_used_in_aexp X (ANum n)
| VNUId: forall Y, X <> Y -> var_not_used_in_aexp X (AId Y)
| VNUPlus: forall a1 a2,
var_not_used_in_aexp X a1 ->
var_not_used_in_aexp X a2 ->
var_not_used_in_aexp X (APlus a1 a2)
| VNUMinus: forall a1 a2,
var_not_used_in_aexp X a1 ->
var_not_used_in_aexp X a2 ->
var_not_used_in_aexp X (AMinus a1 a2)
| VNUMult: forall a1 a2,
var_not_used_in_aexp X a1 ->
var_not_used_in_aexp X a2 ->
var_not_used_in_aexp X (AMult a1 a2).
Lemma aeval_weakening : forall i st a ni,
var_not_used_in_aexp i a ->
aeval (t_update st i ni) a = aeval st a.
Proof.
intros i st a ni. intros H.
induction H; simpl; subst.
- reflexivity.
- apply t_update_neq. assumption.
- rewrite -> IHvar_not_used_in_aexp1.
rewrite -> IHvar_not_used_in_aexp2.
reflexivity.
- rewrite -> IHvar_not_used_in_aexp1.
rewrite -> IHvar_not_used_in_aexp2.
reflexivity.
- rewrite -> IHvar_not_used_in_aexp1.
rewrite -> IHvar_not_used_in_aexp2.
reflexivity.
Qed.
(** Using [var_not_used_in_aexp], formalize and prove a correct verson
of [subst_equiv_property]. *)
Lemma subst_equiv_lemma1 :
forall (a1 a2 : aexp) (i : id) (st : state),
st i = aeval st a1 ->
var_not_used_in_aexp i a1 ->
aeval st (subst_aexp i a1 a2) = aeval st a2.
Proof.
intros a1 a2. generalize dependent a1.
induction a2; intros; simpl; auto.
(* Every case follows trivially from the induction hypotheses except
case AId. *)
- destruct (beq_id i0 i) eqn : Heq.
assert (Heq' : i = i0). { symmetry. rewrite <- beq_id_true_iff. assumption. }
rewrite -> Heq'. auto. auto.
Qed.
Lemma subst_equiv_lemma2 :
forall (i : id) (a : aexp) (st st' : state),
var_not_used_in_aexp i a ->
(i ::= a) / st \\ st' -> st' i = aeval st' a.
Proof.
intros i a st st' H' H.
inversion H; subst.
remember (aeval st a) as a'.
(* remember (t_update st i a') as st'. *)
rewrite -> aeval_weakening. unfold t_update. rewrite <- beq_id_refl.
assumption. assumption.
Qed.
Theorem subst_equiv_property' :
forall (i1 i2 : id) (a1 a2 : aexp),
var_not_used_in_aexp i1 a1 ->
cequiv (i1 ::= a1;; i2 ::= a2)
(i1 ::= a1;; i2 ::= subst_aexp i1 a1 a2).
Proof.
intros i1 i2 a1 a2 H. split.
- intros H0. inversion H0; subst. inversion H3; subst.
inversion H6; subst.
remember (aeval st a1) as a1'.
remember (t_update st i1 a1') as st1'.
apply E_Seq with st1'. assumption. apply E_Ass. apply subst_equiv_lemma1.
apply subst_equiv_lemma2 with st.
assumption. assumption. assumption.
- intros H0. inversion H0; subst. inversion H3; subst.
inversion H6; subst.
remember (aeval st a1) as a1'.
remember (t_update st i1 a1') as st1'.
apply E_Seq with st1'. assumption.
apply E_Ass. symmetry. apply subst_equiv_lemma1.
apply subst_equiv_lemma2 with st.
assumption. assumption. assumption.
Qed.
(** [] *)
(** **** Exercise: 3 stars (inequiv_exercise) *)
(** Prove that an infinite loop is not equivalent to [SKIP] *)
Theorem inequiv_exercise:
~ cequiv (WHILE BTrue DO SKIP END) SKIP.
Proof.
intros contra.
apply loop_never_stops with empty_state empty_state.
unfold loop.
apply contra.
apply E_Skip.
Qed.
(** [] *)
(* ################################################################# *)
(** * Extended Exercise: Nondeterministic Imp *)
(** As we have seen (in theorem [ceval_deterministic] in the [Imp]
chapter), Imp's evaluation relation is deterministic. However,
_non_-determinism is an important part of the definition of many
real programming languages. For example, in many imperative
languages (such as C and its relatives), the order in which
function arguments are evaluated is unspecified. The program
fragment
x = 0;;
f(++x, x)
might call [f] with arguments [(1, 0)] or [(1, 1)], depending how
the compiler chooses to order things. This can be a little
confusing for programmers, but it gives the compiler writer useful
freedom.
In this exercise, we will extend Imp with a simple
nondeterministic command and study how this change affects
program equivalence. The new command has the syntax [HAVOC X],
where [X] is an identifier. The effect of executing [HAVOC X] is
to assign an _arbitrary_ number to the variable [X],
nondeterministically. For example, after executing the program:
HAVOC Y;;
Z ::= Y * 2
the value of [Y] can be any number, while the value of [Z] is
twice that of [Y] (so [Z] is always even). Note that we are not
saying anything about the _probabilities_ of the outcomes -- just
that there are (infinitely) many different outcomes that can
possibly happen after executing this nondeterministic code.
In a sense, a variable on which we do [HAVOC] roughly corresponds
to an unitialized variable in a low-level language like C. After
the [HAVOC], the variable holds a fixed but arbitrary number. Most
sources of nondeterminism in language definitions are there
precisely because programmers don't care which choice is made (and
so it is good to leave it open to the compiler to choose whichever
will run faster).
We call this new language _Himp_ (``Imp extended with [HAVOC]''). *)
Module Himp.
(** To formalize Himp, we first add a clause to the definition of
commands. *)
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CHavoc : id -> com. (* <---- new *)
Notation "'SKIP'" :=
CSkip.
Notation "X '::=' a" :=
(CAss X a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'HAVOC' l" := (CHavoc l) (at level 60).
(** **** Exercise: 2 stars (himp_ceval) *)
(** Now, we must extend the operational semantics. We have provided
a template for the [ceval] relation below, specifying the big-step
semantics. What rule(s) must be added to the definition of [ceval]
to formalize the behavior of the [HAVOC] command? *)
Reserved Notation "c1 '/' st '\\' st'"
(at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st \\ st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n ->
(X ::= a1) / st \\ t_update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st \\ st' ->
c2 / st' \\ st'' ->
(c1 ;; c2) / st \\ st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st \\ st' ->
(IFB b1 THEN c1 ELSE c2 FI) / st \\ st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st \\ st' ->
(IFB b1 THEN c1 ELSE c2 FI) / st \\ st'
| E_WhileEnd : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false ->
(WHILE b1 DO c1 END) / st \\ st
| E_WhileLoop : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st \\ st' ->
(WHILE b1 DO c1 END) / st' \\ st'' ->
(WHILE b1 DO c1 END) / st \\ st''
| E_Havoc : forall i st n,
(HAVOC i) / st \\ t_update st i n
where "c1 '/' st '\\' st'" := (ceval c1 st st').
(** As a sanity check, the following claims should be provable for
your definition: *)
Example havoc_example1 : (HAVOC X) / empty_state \\ t_update empty_state X 0.
Proof. constructor. Qed.
Example havoc_example2 :
(SKIP;; HAVOC Z) / empty_state \\ t_update empty_state Z 42.
Proof.
remember empty_state as st.
apply E_Seq with st. apply E_Skip. apply E_Havoc.
Qed.
(** [] *)
(** Finally, we repeat the definition of command equivalence from above: *)
Definition cequiv (c1 c2 : com) : Prop := forall st st' : state,
c1 / st \\ st' <-> c2 / st \\ st'.
(** Let's apply this definition to prove some nondeterministic
programs equivalent / inequivalent. *)
(** **** Exercise: 3 stars (havoc_swap) *)
(** Are the following two programs equivalent? *)
Definition pXY :=
HAVOC X;; HAVOC Y.
Definition pYX :=
HAVOC Y;; HAVOC X.
(** If you think they are equivalent, prove it. If you think they are
not, prove that. *)
Theorem pXY_cequiv_pYX :
cequiv pXY pYX \/ ~cequiv pXY pYX.
Proof.
left. split; intros;
inversion H; subst; inversion H2; subst; inversion H5; subst.
- apply E_Seq with (t_update st Y n0).
apply E_Havoc.
assert (H0 : t_update (t_update st X n) Y n0 = t_update (t_update st Y n0) X n).
{ apply functional_extensionality. intros.
unfold t_update.
destruct (beq_id Y x) eqn : Heqy; destruct (beq_id X x) eqn : Heqx; try reflexivity.
apply beq_id_true_iff in Heqy. apply beq_id_true_iff in Heqx.
rewrite <- Heqx in Heqy. inversion Heqy.
}
rewrite -> H0. apply E_Havoc.
- apply E_Seq with (t_update st X n0).
apply E_Havoc.
assert (H1 : t_update (t_update st X n0) Y n = t_update (t_update st Y n) X n0).
{ apply functional_extensionality. intros.
unfold t_update.
destruct (beq_id Y x) eqn : Heqy; destruct (beq_id X x) eqn : Heqx; try reflexivity.
apply beq_id_true_iff in Heqy. apply beq_id_true_iff in Heqx.
rewrite <- Heqx in Heqy. inversion Heqy.
}
rewrite <- H1. apply E_Havoc.
Qed.
(** **** Exercise: 4 stars, optional (havoc_copy) *)
(** Are the following two programs equivalent? *)
Definition ptwice :=
HAVOC X;; HAVOC Y.
Definition pcopy :=
HAVOC X;; Y ::= AId X.
(** If you think they are equivalent, then prove it. If you think they
are not, then prove that. (Hint: You may find the [assert] tactic
useful.) *)
Theorem ptwice_cequiv_pcopy :
cequiv ptwice pcopy \/ ~cequiv ptwice pcopy.
Proof.
right. unfold not. unfold cequiv. intros.
assert (pcopy / empty_state \\ t_update (t_update empty_state X 0) Y 1).
apply H. apply E_Seq with (t_update empty_state X 0).
apply E_Havoc. apply E_Havoc.
inversion H0; subst. inversion H3; subst. inversion H6; subst.
simpl in H7. rewrite t_update_eq in H7.
assert (t_update (t_update empty_state X n) Y n X = n).
{ rewrite t_update_permute. rewrite t_update_eq. reflexivity.
unfold not. intros. inversion H1. }
assert (t_update (t_update empty_state X n) Y n Y = n).
{ rewrite t_update_eq. reflexivity. }
rewrite H7 in H1. rewrite H7 in H2.
rewrite t_update_permute in H1. rewrite t_update_eq in H2.
rewrite t_update_eq in H1. rewrite <- H1 in H2. inversion H2.
unfold not. intros. inversion H4.
Qed.
(** [] *)
(** The definition of program equivalence we are using here has some
subtle consequences on programs that may loop forever. What
[cequiv] says is that the set of possible _terminating_ outcomes
of two equivalent programs is the same. However, in a language
with nondeterminism, like Himp, some programs always terminate,
some programs always diverge, and some programs can
nondeterministically terminate in some runs and diverge in
others. The final part of the following exercise illustrates this
phenomenon.
*)
(** **** Exercise: 4 stars, advanced (p1_p2_term) *)
(** Consider the following commands: *)
Definition p1 : com :=
WHILE (BNot (BEq (AId X) (ANum 0))) DO
HAVOC Y;;
X ::= APlus (AId X) (ANum 1)
END.
Definition p2 : com :=
WHILE (BNot (BEq (AId X) (ANum 0))) DO
SKIP
END.
(** Intuitively, [p1] and [p2] have the same termination behavior:
either they loop forever, or they terminate in the same state they
started in. We can capture the termination behavior of [p1] and
[p2] individually with these lemmas: *)
Lemma p1_may_diverge : forall st st', st X <> 0 ->
~ p1 / st \\ st'.
Proof.
unfold not. unfold p1. intros st st' H H0.
remember (WHILE BNot (BEq (AId X) (ANum 0))
DO HAVOC Y;; X ::= APlus (AId X) (ANum 1) END) as p1.
induction H0; inversion Heqp1.
- rewrite H2 in H0. simpl in H0.
apply H. apply beq_nat_true. apply negb_false_iff. assumption.
- apply IHceval2. rewrite H3 in H0_. inversion H0_; subst.
inversion H8; subst. rewrite t_update_eq. simpl.
rewrite <- plus_n_Sm. intros. inversion H1.
assumption.
Qed.
Lemma p2_may_diverge : forall st st', st X <> 0 ->
~ p2 / st \\ st'.
Proof.
unfold not. unfold p2. intros.
remember (WHILE BNot (BEq (AId X) (ANum 0)) DO SKIP END) as p2.
induction H0; inversion Heqp2.
- rewrite H2 in H0. simpl in H0. apply H. apply beq_nat_true.
apply negb_false_iff. assumption.
- rewrite -> H3 in H0_. inversion H0_; subst.
apply IHceval2. assumption. assumption.
Qed.
(** [] *)
(** **** Exercise: 4 stars, advanced (p1_p2_equiv) *)
(** Use these two lemmas to prove that [p1] and [p2] are actually
equivalent. *)
Lemma t_update_same' :
forall (n : nat) (X Y : id) (st : state),
st X = n -> t_update st X n Y = st Y.
Proof.
intros n X Y st H. Search t_update. unfold t_update.
destruct (beq_id X Y) eqn : Heq.
- apply beq_id_true_iff in Heq. symmetry. rewrite <- Heq. assumption.
- reflexivity.
Qed.
Theorem p1_p2_equiv : cequiv p1 p2.
Proof.
split; intros.
- (* -> *)
inversion H; subst.
apply E_WhileEnd. assumption.
inversion H3; subst. inversion H8; subst.
remember (t_update st'1 X (aeval st'1 (APlus (AId X) (ANum 1)))) as st'2.
assert(st'2 X <> 0).
{ rewrite Heqst'2. rewrite t_update_eq. simpl. rewrite <- plus_n_Sm.
unfold not. intros. inversion H0. }
apply p1_may_diverge with (st' := st') in H0. contradiction.
- (* <- *)
inversion H; subst. apply E_WhileEnd. assumption.
inversion H3; subst. simpl in H2. apply negb_true_iff in H2. apply beq_nat_false in H2.
apply p2_may_diverge in H6. inversion H6. assumption.
Qed.
(** [] *)
(** **** Exercise: 4 stars, advancedM (p3_p4_inequiv) *)
(** Prove that the following programs are _not_ equivalent. (Hint:
What should the value of [Z] be when [p3] terminates? What about
[p4]?) *)
Definition p3 : com :=
Z ::= ANum 1;;
WHILE (BNot (BEq (AId X) (ANum 0))) DO
HAVOC X;;
HAVOC Z
END.
Definition p4 : com :=
X ::= (ANum 0);;
Z ::= (ANum 1).
Theorem p3_p4_inequiv : ~ cequiv p3 p4.
Proof.
unfold cequiv. unfold not. intros.
assert (p4 / (t_update empty_state X 1) \\
t_update (t_update (t_update (t_update empty_state X 1) Z 1) X 0) Z 0).
apply H.
apply E_Seq with (t_update (t_update empty_state X 1) Z 1).
apply E_Ass. reflexivity.
apply E_WhileLoop with (t_update (t_update (t_update (t_update empty_state X 1) Z 1) X 0) Z 0).
reflexivity.
apply E_Seq with (t_update (t_update (t_update empty_state X 1) Z 1) X 0).
apply E_Havoc. apply E_Havoc.
apply E_WhileEnd. reflexivity.
inversion H0; subst.
inversion H3; subst.
inversion H6; subst.
simpl in H7.
assert (t_update (t_update (t_update empty_state X 1) X 0) Z 1 Z = 1).
rewrite t_update_eq. reflexivity.
assert (t_update (t_update (t_update (t_update empty_state X 1) Z 1) X 0) Z 0 Z = 0).
rewrite t_update_eq. reflexivity.
rewrite H7 in H1. rewrite H1 in H2.
inversion H2.
Qed.
(** [] *)
(** **** Exercise: 5 stars, advanced, optional (p5_p6_equiv) *)
(** Prove that the following commands are equivalent. (Hint: As
mentioned above, our definition of [cequiv] for Himp only takes
into account the sets of possible terminating configurations: two
programs are equivalent if and only if when given a same starting
state [st], the set of possible terminating states is the same for
both programs. If [p5] terminates, what should the final state be?
Conversely, is it always possible to make [p5] terminate?) *)
Definition p5 : com :=
WHILE (BNot (BEq (AId X) (ANum 1))) DO
HAVOC X
END.
Definition p6 : com :=
X ::= ANum 1.
Theorem p5_p6_equiv : cequiv p5 p6.
Proof.
split; intros.
- unfold p5 in H.
remember (WHILE BNot (BEq (AId X) (ANum 1)) DO HAVOC X END) as p5.
induction H; inversion Heqp5; clear Heqp5.
rewrite H1 in H. simpl in H.
assert (t_update st X 1 = st).
{ apply functional_extensionality. intros. Search t_update.
apply t_update_same'. apply beq_nat_true. apply negb_false_iff.
assumption. }
rewrite <- H0 at 2. apply E_Ass. reflexivity.
subst. inversion H0; subst.
assert (p6 / t_update st X n \\ st'').
{ apply IHceval2. reflexivity. }
inversion H2; subst. simpl.
assert (t_update (t_update st X n) X 1 = t_update st X 1).
{ apply functional_extensionality. intros.
rewrite t_update_shadow. reflexivity. }
rewrite H3. apply E_Ass. reflexivity.
- inversion H; subst. simpl in H. simpl.
destruct (negb (beq_nat (st X) 1)) eqn : Heqnat.
apply E_WhileLoop with (t_update st X 1).
simpl. assumption. apply E_Havoc. apply E_WhileEnd. reflexivity.
assert (t_update st X 1 = st).
{ apply functional_extensionality. intros. Search t_update.
apply t_update_same'. apply beq_nat_true. apply negb_false_iff.
assumption. }
rewrite H0.
apply E_WhileEnd. simpl. assumption.
Qed.
(** [] *)
End Himp.
(* ################################################################# *)
(** * Additional Exercises *)
(** **** Exercise: 4 stars, optional (for_while_equiv) *)
(** This exercise extends the optional [add_for_loop] exercise from
the [Imp] chapter, where you were asked to extend the language
of commands with C-style [for] loops. Prove that the command:
for (c1 ; b ; c2) {
c3
}
is equivalent to:
c1 ;
WHILE b DO
c3 ;
c2
END
*)
Module ForImp.
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CFor : com -> bexp -> com -> com -> com.
Notation "'SKIP'" :=
CSkip.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' c1 'THEN' c2 'ELSE' c3 'FI'" :=
(CIf c1 c2 c3) (at level 80, right associativity).
Notation "'FOR' a ; b ; c 'DO' d " :=
(CFor a b c d) (at level 80, right associativity).
Reserved Notation "c1 '/' st '\\' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip :
forall st, SKIP / st \\ st
| E_Ass :
forall st a1 n x,
aeval st a1 = n ->
(x ::= a1) / st \\ (t_update st x n)
| E_Seq :
forall c1 c2 st st' st'',
c1 / st \\ st' ->
c2 / st' \\ st'' ->
(c1 ;; c2) / st \\ st''
| E_IfTrue :
forall st st' b c1 c2,
beval st b = true ->
c1 / st \\ st' ->
(IFB b THEN c1 ELSE c2 FI) / st \\ st'
| E_IfFalse :
forall st st' b c1 c2,
beval st b = false ->
c2 / st \\ st' ->
(IFB b THEN c1 ELSE c2 FI) / st \\ st'
| E_WhileEnd :
forall b st c,
beval st b = false ->
(WHILE b DO c END) / st \\ st
| E_WhileLoop :
forall st st' st'' b c,
beval st b = true ->
c / st \\ st' ->
(WHILE b DO c END) / st' \\ st'' ->
(WHILE b DO c END) / st \\ st''
| E_For:
forall a b c d st st',
(a ;; WHILE b DO d;; c END) / st \\ st' ->
(FOR a ; b ; c DO d) / st \\ st'
where "c1 '/' st '\\' st'" := (ceval c1 st st').
Definition cequiv_for (c1 c2 : com) :=
forall (st st' : state), (c1 / st \\ st') <-> (c2 / st \\ st').
Theorem for_while_equiv : forall c1 c2 c3 b,
cequiv_for (FOR c1 ; b ; c2 DO c3) (c1 ;; WHILE b DO c3 ;; c2 END).
Proof.
split; intros H.
- inversion H. subst. assumption.
- apply E_For. assumption.
Qed.
End ForImp.
(** [] *)
(** **** Exercise: 3 stars, optional (swap_noninterfering_assignments) *)
(** (Hint: You'll need [functional_extensionality] for this one.) *)
Theorem swap_noninterfering_assignments: forall l1 l2 a1 a2,
l1 <> l2 ->
var_not_used_in_aexp l1 a2 ->
var_not_used_in_aexp l2 a1 ->
cequiv
(l1 ::= a1;; l2 ::= a2)
(l2 ::= a2;; l1 ::= a1).
Proof.
intros l1 l2 a1 a2 H H1 H2.
unfold cequiv. split.
- intros H3. inversion H3; subst.
inversion H5; subst. inversion H8; subst.
assert (t_update (t_update st l1 (aeval st a1)) l2
(aeval (t_update st l1 (aeval st a1)) a2) =
t_update (t_update st l2 (aeval st a2)) l1
(aeval (t_update st l2 (aeval st a2)) a1)).
{ apply aeval_weakening with (st := st) (ni := aeval st a1) in H1.
apply aeval_weakening with (st := st) (ni := aeval st a2) in H2.
rewrite -> H1. rewrite -> H2.
apply functional_extensionality. intros.
rewrite t_update_permute. reflexivity. assumption. }
rewrite H0.
apply E_Seq with (t_update st l2 (aeval st a2)).
apply E_Ass. reflexivity.
apply E_Ass. reflexivity.
- intros H3. inversion H3; subst.
inversion H5; subst. inversion H8; subst.
assert (t_update (t_update st l1 (aeval st a1)) l2
(aeval (t_update st l1 (aeval st a1)) a2) =
t_update (t_update st l2 (aeval st a2)) l1
(aeval (t_update st l2 (aeval st a2)) a1)).
{ apply aeval_weakening with (st := st) (ni := aeval st a1) in H1.
apply aeval_weakening with (st := st) (ni := aeval st a2) in H2.
rewrite -> H1. rewrite -> H2.
apply functional_extensionality. intros.
rewrite t_update_permute. reflexivity. assumption. }
rewrite <- H0.
apply E_Seq with (t_update st l1 (aeval st a1)).
apply E_Ass. reflexivity.
apply E_Ass. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 4 stars, advanced, optional (capprox) *)
(** In this exercise we define an asymmetric variant of program
equivalence we call _program approximation_. We say that a
program [c1] _approximates_ a program [c2] when, for each of
the initial states for which [c1] terminates, [c2] also terminates
and produces the same final state. Formally, program approximation
is defined as follows: *)
Definition capprox (c1 c2 : com) : Prop := forall (st st' : state),
c1 / st \\ st' -> c2 / st \\ st'.
(** For example, the program [c1 = WHILE X <> 1 DO X ::= X - 1 END]
approximates [c2 = X ::= 1], but [c2] does not approximate [c1]
since [c1] does not terminate when [X = 0] but [c2] does. If two
programs approximate each other in both directions, then they are
equivalent. *)
(** Find two programs [c3] and [c4] such that neither approximates
the other. *)
Definition c3 : com := SKIP.
Definition c4 : com := (WHILE BTrue DO SKIP END).
Theorem c3_c4_different : ~ capprox c3 c4 /\ ~ capprox c4 c3.
Proof.
Admitted.
(** Find a program [cmin] that approximates every other program. *)
Definition cmin : com
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Theorem cmin_minimal : forall c, capprox cmin c.
Proof. (* FILL IN HERE *) Admitted.
(** Finally, find a non-trivial property which is preserved by
program approximation (when going from left to right). *)
Definition zprop (c : com) : Prop
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Theorem zprop_preserving : forall c c',
zprop c -> capprox c c' -> zprop c'.
Proof. (* FILL IN HERE *) Admitted.
(** [] *)
(** $Date: 2016-12-20 10:47:46 -0500 (Tue, 20 Dec 2016) $ *)
|
(***********************************************************************)
(* *)
(* Compcert Extensions *)
(* *)
(* Jean-Baptiste Tristan *)
(* *)
(* All rights reserved. This file is distributed under the terms *)
(* described in file ../../LICENSE. *)
(* *)
(***********************************************************************)
Require Import Coqlib.
Require Import Maps.
Require Import AST.
Require Import Integers.
Require Import Floats.
Require Import Values.
Require Import Globalenvs.
Require Import Op.
Require Import Registers.
Require Import RTL.
Require Import RTL2.
Require Import Lattice.
Require Import Kildall.
Require Import DecidableType.
Require Import FSetWeakInterface.
Require Import FSetWeakFacts.
Require Import FSetWeakProperties.
Require Import FSetWeakList.
Require Import Errors.
Require Import Utilities.
Require Import Mem.
Require Import Events.
Require Import EqualityAnalysis.
Section AN.
Variable ge : genv.
(** *Correcteness proof for analysis of equalities *)
Definition eq_holds (r : reg) (a : approx) (st : std_state) : Prop :=
match a with
| Op op lr => eval_operation ge st.(sp) op st.(rs)##lr st.(m) = Some st.(rs)#r
| Load mc addr lr => exists a, eval_addressing ge st.(sp) addr st.(rs)##lr = Some a /\ Mem.loadv mc st.(m) a = Some st.(rs)#r
| Novalue => False
| Unknown => True
end.
Definition state_holds (eq : D.t) (st : state) : Prop :=
match st with
| State stack f sp pc rs m => forall (r : reg) (a : approx), D.get r eq = a -> eq_holds r a (mk_std_state f sp rs m)
| _ => True
end.
Definition stackframe_holds (st : stackframe) :=
forall m,
match st with
| Stackframe res f sp pc rs => forall (r : reg) (a : approx), D.get r ((analyze f)!!pc) = a -> forall v, eq_holds r a (mk_std_state f sp rs#res <- v m)
end.
Definition stack_holds (st : state) : Prop :=
match st with
| State stack c sp pc rs m => forall i, In i stack -> stackframe_holds i
| Callstate stack f args m => forall i, In i stack -> stackframe_holds i
| Returnstate stack v m => forall i, In i stack -> stackframe_holds i
end.
Definition holds (st : state) : Prop :=
match st with
| State stack f sp pc rs m => state_holds (analyze f)!!pc st /\ stack_holds st
| Callstate stack f args m => stack_holds st
| Returnstate stack v m => stack_holds st
end.
Lemma top_unknown : forall r, D.get r D.top = Unknown.
Proof.
intros.
unfold D.top. simpl. rewrite PTree.gempty. unfold Approx.top. trivial.
Qed.
Lemma top_always_holds : forall (st : state), state_holds D.top st.
Proof.
unfold state_holds; intros.
destruct st; trivial.
intros. rewrite top_unknown in H. subst.
unfold eq_holds. trivial.
Qed.
Lemma get_greater : forall m1 m2 r,
D.ge m2 m1 -> Approx.ge (D.get r m2) (D.get r m1).
Proof.
intros.
unfold D.ge in H. generalize (H r); clear H; intro H.
trivial.
Qed.
Lemma holds_decreasing : forall (m1 m2 : D.t), D.ge m2 m1 -> forall st, state_holds m1 st -> state_holds m2 st.
Proof.
unfold state_holds. intros.
destruct st; trivial. intros.
generalize (get_greater _ _ r H); clear H; intro H. unfold Approx.ge in H.
destruct H. rewrite H1 in H. rewrite H. unfold eq_holds; trivial.
destruct H. generalize (H0 r Novalue H); intro. unfold eq_holds; contradiction.
rewrite H1 in H. assert (D.get r m1 = a). symmetry. trivial.
generalize (H0 _ _ H2); intro; trivial.
Qed.
Lemma greater_than_top : forall m, D.ge m D.top -> forall r, D.get r m = Unknown.
Proof.
intros. unfold D.ge in H.
generalize (H r); intro. rewrite top_unknown in H0.
unfold Approx.ge in H0.
destruct H0. trivial.
destruct H0. congruence. trivial.
Qed.
Lemma analyze_correct_start : forall f st, state_holds (analyze f)!!(f.(fn_entrypoint)) st.
Proof.
intros.
unfold analyze.
generalize (DS.fixpoint_entry (successors f) (fn_nextpc f) (transfer f)
((fn_entrypoint f, D.top) :: nil)); intros; subst.
case_eq (DS.fixpoint (successors f) (fn_nextpc f) (transfer f)
((fn_entrypoint f, D.top) :: nil)); intros.
assert (In (fn_entrypoint f, D.top) ((fn_entrypoint f, D.top) :: nil)).
unfold In. left; trivial.
generalize (H t (fn_entrypoint f) D.top H0 H1); intro.
unfold DS.L.ge in H2.
generalize (greater_than_top _ H2); clear H2; intro H2.
unfold state_holds.
destruct st; trivial.
intros. generalize (H2 r); intro.
assert (D.get r (@PMap.get D.t (fn_entrypoint f) t) = D.get r (@PMap.get DS.L.t (fn_entrypoint f) t)). trivial.
rewrite H5 in H3. rewrite H4 in H3.
rewrite <- H3. unfold eq_holds; trivial.
rewrite PMap.gi. unfold state_holds.
destruct st; trivial.
intros. rewrite top_unknown in H1. rewrite <- H1.
unfold eq_holds; trivial.
Qed.
Lemma analyze_correct_transf:
forall f pc st pc' ast,
In pc' (successors f pc) ->
transfer f pc (analyze f)!!pc = ast ->
state_holds ast st /\ stack_holds st->
state_holds (analyze f)!!pc' st /\ stack_holds st.
Proof.
intros.
unfold analyze.
generalize (DS.fixpoint_solution (successors f) (fn_nextpc f) (transfer f)
((fn_entrypoint f, D.top) :: nil)); intros; subst.
case_eq ( DS.fixpoint (successors f) (fn_nextpc f) (transfer f)
((fn_entrypoint f, D.top) :: nil)); intros.
assert (Plt pc (fn_nextpc f)). generalize f.(fn_code_wf); intro. generalize (H3 pc); intro. destruct H4. trivial.
unfold successors in H. rewrite H4 in H. inversion H.
generalize (H2 t pc pc' H0 H3 H); intro.
destruct H1. split; trivial.
eapply holds_decreasing; eauto.
unfold analyze in H1. rewrite H0 in H1. trivial.
destruct H1. split; trivial.
rewrite PMap.gi. unfold state_holds.
destruct st; trivial.
intros. rewrite top_unknown in H4. rewrite <- H4.
unfold eq_holds; trivial.
Qed.
Lemma analyze_correct_transf_bis:
forall f pc pc' es,
In pc' (successors f pc) ->
transfer f pc (analyze f)!!pc = es ->
D.ge (analyze f)!!pc' es.
Proof.
intros. unfold analyze.
generalize (DS.fixpoint_solution (successors f) (fn_nextpc f) (transfer f)
((fn_entrypoint f, D.top) :: nil)); intros; subst.
case_eq ( DS.fixpoint (successors f) (fn_nextpc f) (transfer f)
((fn_entrypoint f, D.top) :: nil)); intros.
rewrite H0 in *|-.
assert (Plt pc (fn_nextpc f)). generalize f.(fn_code_wf); intro. generalize (H2 pc); intro. destruct H3. trivial.
unfold successors in H. rewrite H3 in H. inversion H.
assert (Some t = Some t). trivial.
generalize (H1 t pc pc' H3 H2 H); intro.
unfold DS.L.ge in H4. unfold D.ge in H4.
assert (@PMap.get DS.L.t = @PMap.get D.t). trivial.
unfold analyze. rewrite H0. unfold D.ge. trivial.
rewrite PMap.gi. eapply D.ge_top; eauto.
Qed.
Lemma transp_incr : forall a res, transp a res = a \/ transp a res = Unknown.
Proof.
intros.
destruct a; simpl.
left; trivial.
left; trivial.
case_eq (Utilities.mem res l); intros.
right; trivial.
left; trivial.
case_eq (Utilities.mem res l); intros.
right; trivial.
left; trivial.
Qed.
Lemma transp_incr_bis: forall a, transp_mem a = a \/ transp_mem a = Unknown.
Proof.
intros.
destruct a; simpl; intuition.
destruct o; intuition.
Qed.
Lemma transp_bot : forall r, transp Novalue r = Novalue.
Proof.
simpl; trivial.
Qed.
Lemma transp_top : forall r, transp Unknown r = Unknown.
Proof.
simpl; trivial.
Qed.
Lemma trans_prop_1 :
forall res m, D.ge (D.map (fun (_ : positive) (a : Approx.t) => transp a res) m) m.
Proof.
intros.
unfold D.ge. intro.
rewrite D.gmap; auto.
generalize (transp_incr (D.get p m) res); intro.
destruct H.
rewrite H. unfold Approx.ge. right; right; trivial.
rewrite H. unfold Approx.ge. left; trivial.
Qed.
Lemma transp_prop_2 :
forall r res l o m,
D.get r
(D.map (fun (_ : positive) (a : Approx.t) => transp a res)
m) = Op o l ->
~ In res l.
Proof.
intros.
rewrite D.gmap in H.
unfold transp in H.
destruct (D.get r m); intros; try congruence.
case_eq (Utilities.mem res l0); intros.
rewrite H0 in H. congruence.
rewrite H0 in H. inversion H; subst. eapply mem_false; eauto.
case_eq (Utilities.mem res l0); intros.
rewrite H0 in H. congruence.
rewrite H0 in H. congruence.
eapply transp_bot; eauto.
eapply transp_top; eauto.
Qed.
Lemma transp_prop_3 :
forall r res m1 a l m,
D.get r
(D.map (fun (_ : positive) (a : Approx.t) => transp a res)
m) = Load m1 a l ->
~ In res l.
Proof.
intros.
rewrite D.gmap in H.
unfold transp in H.
destruct (D.get r m); intros; try congruence.
case_eq (Utilities.mem res l0); intros.
rewrite H0 in H. congruence.
rewrite H0 in H. congruence.
case_eq (Utilities.mem res l0); intros.
rewrite H0 in H. congruence.
rewrite H0 in H. inversion H; subst. eapply mem_false; eauto.
eapply transp_bot; eauto.
eapply transp_top; eauto.
Qed.
Lemma transp_prop_4 :
forall f r pc o l sp rs m,
D.get r
(D.map (fun (_ : positive) (a : Approx.t) => transp_mem a)
(analyze f) !! pc) = Op o l ->
eval_operation ge sp o rs ## l m = Some rs # r ->
forall m', eval_operation ge sp o rs ## l m' = Some rs # r.
Proof.
intros.
rewrite D.gmap in H.
unfold transp_mem in H.
case_eq (D.get r (analyze f) !! pc); intros.
rewrite H1 in H. inversion H.
rewrite H1 in H. inversion H.
rewrite H1 in H.
destruct o0; try (
inversion H; subst;
simpl; simpl in *|-;
trivial).
rewrite H1 in H. inversion H.
simpl. trivial.
simpl; trivial.
Qed.
Lemma transp_prop_5 :
forall f r pc m a l,
D.get r
(D.map (fun (_ : positive) (a : Approx.t) => transp_mem a)
(analyze f) !! pc) = Load m a l -> False.
Proof.
intros.
rewrite D.gmap in H; try (simpl; trivial).
destruct (D.get r (analyze f) !! pc); try (inversion H).
destruct o; congruence.
Qed.
Lemma transp_prop_6 :
forall m,
D.ge (D.map (fun (_ : positive) (a : Approx.t) => transp_mem a) m) m.
Proof.
intros.
unfold D.ge. intros. rewrite D.gmap; try (simpl; trivial).
unfold Approx.ge.
destruct (D.get p m); simpl; intuition.
destruct o; intuition.
Qed.
Lemma transfer_op_correct :
forall f pc stack sp rs m op args res pc' v,
state_holds (analyze f) !! pc (State stack f sp pc rs m) ->
(fn_code f) ! pc = Some (Iop op args res pc') ->
eval_operation ge sp op rs ## args m = Some v ->
state_holds (transfer f pc (analyze f) !! pc)
(State stack f sp pc' rs # res <- v m).
Proof.
intros.
assert (D.ge (D.map (fun (_ : positive) (a : Approx.t) => transp a res)
(analyze f) !! pc) ((analyze f) !! pc)).
eapply trans_prop_1; eauto.
generalize (holds_decreasing _ _ H2); intro.
unfold transfer. rewrite H0.
unfold state_holds. intros.
unfold state_holds in H.
generalize (peq res r); intro. destruct H5.
rewrite e in H4.
rewrite D.gss in H4.
case_eq (Utilities.mem r args); intros.
rewrite H5 in H4. rewrite <- H4. unfold eq_holds; trivial.
rewrite H5 in H4. rewrite <- H4.
unfold eq_holds. simpl. rewrite e.
rewrite PMap.gss.
rewrite extended_gso; auto.
eapply mem_false; eauto.
rewrite D.gso in H4; auto.
unfold D.ge in H2.
generalize (H2 r); clear H2; intro H2.
unfold Approx.ge in H2.
destruct H2. rewrite H4 in H2.
rewrite H2. unfold eq_holds. trivial.
destruct H2.
generalize (H _ _ H2); intro.
inversion H5.
rewrite H2 in H4. generalize (H _ _ H4); intro.
unfold eq_holds.
destruct a.
inversion H5.
trivial.
simpl. rewrite PMap.gso; auto. inversion H5.
rewrite extended_gso; auto.
rewrite H4 in H2.
eapply transp_prop_2; eauto.
simpl. inversion H5. simpl in H6.
rewrite PMap.gso; auto. rewrite extended_gso; auto.
rewrite H4 in H2.
eapply transp_prop_3; eauto.
Qed.
Lemma transfer_load_correct :
forall f pc stack sp rs m args pc' v dst addr chunk a,
state_holds (analyze f) !! pc (State stack f sp pc rs m) ->
loadv chunk m a = Some v ->
eval_addressing ge sp addr rs ## args = Some a ->
(fn_code f) ! pc = Some (Iload chunk addr args dst pc') ->
state_holds (transfer f pc (analyze f) !! pc)
(State stack f sp pc' rs # dst <- v m).
Proof.
intros.
assert (D.ge (D.map (fun (_ : positive) (a : Approx.t) => transp a dst)
(analyze f) !! pc) ((analyze f) !! pc)).
eapply trans_prop_1; eauto.
generalize (holds_decreasing _ _ H3); intro.
unfold transfer. rewrite H2.
unfold state_holds. intros.
unfold state_holds in H.
generalize (peq dst r); intro. destruct H6.
rewrite e in H5.
rewrite D.gss in H5.
case_eq (Utilities.mem r args); intros.
rewrite H6 in H5. rewrite <- H5. unfold eq_holds; trivial.
rewrite H6 in H5. rewrite <- H5.
unfold eq_holds. simpl. rewrite e.
rewrite PMap.gss.
rewrite extended_gso; auto.
exists a. split; trivial.
eapply mem_false; eauto.
rewrite D.gso in H5; auto.
unfold D.ge in H3.
generalize (H3 r); clear H3; intro H3.
unfold Approx.ge in H3.
destruct H3. rewrite H5 in H3.
rewrite H3. unfold eq_holds. trivial.
destruct H3.
generalize (H _ _ H3); intro.
inversion H6.
rewrite H3 in H5. generalize (H _ _ H5); intro.
unfold eq_holds.
destruct a0.
inversion H6.
trivial.
simpl. rewrite PMap.gso; auto. inversion H6.
rewrite extended_gso; auto.
rewrite H5 in H3.
eapply transp_prop_2; eauto.
simpl. inversion H6. simpl in H7.
rewrite PMap.gso; auto. rewrite extended_gso; auto.
rewrite H5 in H3.
eapply transp_prop_3; eauto.
Qed.
Lemma transfer_store_correct :
forall f pc sp rs m addr args a src m' chunk pc' stack,
state_holds (analyze f) !! pc (State stack f sp pc rs m) ->
storev chunk m a rs # src = Some m' ->
eval_addressing ge sp addr rs ## args = Some a ->
(fn_code f) ! pc = Some (Istore chunk addr args src pc') ->
state_holds (transfer f pc (analyze f) !! pc) (State stack f sp pc' rs m').
Proof.
intros.
unfold state_holds. intros.
unfold transfer in H3. rewrite H2 in H3.
unfold state_holds in H.
assert (D.ge (D.map (fun (_ : positive) (a : Approx.t) => transp_mem a)
(analyze f) !! pc) ((analyze f) !! pc)).
eapply transp_prop_6; eauto.
unfold D.ge in H4.
generalize (H4 r); clear H4; intro H4.
unfold Approx.ge in H4.
destruct H4.
rewrite H4 in H3. rewrite <- H3. unfold eq_holds. trivial.
destruct H4. generalize (H r Novalue H4); intro.
unfold eq_holds in H5. inversion H5.
rewrite H4 in H3.
generalize (H _ _ H3); clear H; intro H.
destruct a0; trivial; try congruence.
simpl. simpl in H. rewrite H3 in H4.
eapply transp_prop_4; eauto.
rewrite H3 in H4.
elimtype False. eapply transp_prop_5; eauto.
Qed.
Lemma filter_1:
forall f r res o l pc,
D.get r
(D.map (fun (_ : positive) (a : Approx.t) => transp_mem a)
(D.map (fun (_ : positive) (a : Approx.t) => transp a res)
(analyze f) !! pc)) = Op o l ->
D.get r (analyze f) !! pc = Op o l.
Proof.
intros.
rewrite D.gmap in H; simpl; trivial.
rewrite D.gmap in H; simpl; trivial.
destruct (D.get r (analyze f) !! pc); simpl in H; try congruence.
killif H. simpl in H. inversion H.
simpl in H. analyze H for o0.
killif H. simpl in H. inversion H.
simpl in H. inversion H.
Qed.
Lemma filter_2:
forall f r res o l pc,
D.get r
(D.map (fun (_ : positive) (a : Approx.t) => transp_mem a)
(D.map (fun (_ : positive) (a : Approx.t) => transp a res)
(analyze f) !! pc)) = Op o l ->
D.get r
(D.map (fun (_ : positive) (a : Approx.t) => transp a res)
(analyze f) !! pc) = Op o l.
Proof.
intros.
rewrite D.gmap in H; simpl; trivial.
rewrite D.gmap in H; simpl; trivial.
rewrite D.gmap; simpl ; trivial.
destruct (D.get r (analyze f) !! pc); simpl in H; try congruence.
killif H. simpl in H. inversion H.
simpl in H.
analyze H for o0; inversion H; simpl; subst; rewrite EQ; trivial.
killif H. simpl in H. inversion H.
simpl in H. inversion H.
Qed.
Lemma filter_3:
forall f r res o l pc,
D.get r
(D.map (fun (_ : positive) (a : Approx.t) => transp_mem a)
(D.map (fun (_ : positive) (a : Approx.t) => transp a res)
(analyze f) !! pc)) = Op o l ->
D.get r
(D.map (fun (_ : positive) (a : Approx.t) => transp_mem a)
(analyze f) !! pc) = Op o l.
Proof.
intros.
rewrite D.gmap in H; simpl; trivial.
rewrite D.gmap in H; simpl; trivial.
rewrite D.gmap; simpl ; trivial.
destruct (D.get r (analyze f) !! pc); simpl in H; try congruence.
killif H. simpl in H. inversion H.
killif H. simpl in H. inversion H.
Qed.
Lemma transfer_call_correct :
forall f pc sp rs m ros args res pc' f0 stack,
state_holds (analyze f) !! pc (State stack f sp pc rs m) ->
(fn_code f) ! pc = Some (Icall (funsig f0) ros args res pc') ->
forall r a m' v,
D.get r (transfer f pc (analyze f) !! pc) = a ->
eq_holds r a (mk_std_state f sp rs # res <- v m').
Proof.
intros.
unfold transfer in H1.
rewrite H0 in H1.
generalize (peq r res); intro.
destruct H2.
subst. rewrite D.gss; auto.
unfold eq_holds. trivial.
rewrite D.gso in H1; auto.
assert (D.ge (D.map (fun (_ : positive) (a : Approx.t) => transp a res)
(analyze f) !! pc) ((analyze f) !! pc)).
eapply trans_prop_1; eauto.
assert (D.ge (D.map (fun (_ : positive) (a : Approx.t) => transp_mem a)
(D.map (fun (_ : positive) (a : Approx.t) => transp a res)
(analyze f) !! pc)) (D.map (fun (_ : positive) (a : Approx.t) => transp a res)
(analyze f) !! pc)).
eapply transp_prop_6; eauto.
assert (D.ge (D.map (fun (_ : positive) (a : Approx.t) => transp_mem a)
(D.map (fun (_ : positive) (a : Approx.t) => transp a res)
(analyze f) !! pc)) ((analyze f) !! pc)).
eapply D.ge_trans; eauto.
generalize (transp_prop_6 ((analyze f)!! pc)); intro.
generalize H1; intro TRI.
rewrite D.gmap in TRI; try (simpl; trivial).
rewrite D.gmap in TRI; try (simpl; trivial).
generalize (transp_incr a res); intro.
generalize (transp_incr_bis a); intro.
destruct a.
unfold transp_mem in TRI.
analyze TRI for (transp (D.get r (analyze f) !! pc) res).
unfold transp in EQ.
analyze EQ for (D.get r (analyze f) !! pc).
unfold state_holds in H.
generalize (H _ _ EQ0); intro. inversion H8.
analyze TRI for o.
unfold eq_holds. trivial.
simpl .
assert (D.get r (analyze f) !! pc = Op o l). eapply filter_1; eauto.
assert (D.get r
(D.map (fun (_ : positive) (a : Approx.t) => transp a res)
(analyze f) !! pc) = Op o l). eapply filter_2; eauto.
assert ( D.get r
(D.map (fun (_ : positive) (a : Approx.t) => transp_mem a)
(analyze f) !! pc) = Op o l). eapply filter_3; eauto.
rewrite PMap.gso; auto. rewrite extended_gso; auto.
unfold state_holds in H. generalize (H _ _ H8); intro.
unfold eq_holds in H11. simpl in H11.
eapply transp_prop_4; eauto.
eapply transp_prop_2; eauto.
unfold transp_mem in TRI.
analyze TRI for (transp (D.get r (analyze f) !! pc) res).
analyze TRI for o.
Qed.
Lemma transfer_alloc_correct :
forall f pc sp rs m arg res pc' stack,
state_holds (analyze f) !! pc (State stack f sp pc rs m) ->
(fn_code f) ! pc = Some (Ialloc arg res pc') ->
forall r a m' v,
D.get r (transfer f pc (analyze f) !! pc) = a ->
eq_holds r a (mk_std_state f sp rs # res <- v m').
Proof.
intros.
unfold transfer in H1.
rewrite H0 in H1.
generalize (peq r res); intro.
destruct H2.
subst. rewrite D.gss; auto.
unfold eq_holds. trivial.
rewrite D.gso in H1; auto.
assert (D.ge (D.map (fun (_ : positive) (a : Approx.t) => transp a res)
(analyze f) !! pc) ((analyze f) !! pc)).
eapply trans_prop_1; eauto.
assert (D.ge (D.map (fun (_ : positive) (a : Approx.t) => transp_mem a)
(D.map (fun (_ : positive) (a : Approx.t) => transp a res)
(analyze f) !! pc)) (D.map (fun (_ : positive) (a : Approx.t) => transp a res)
(analyze f) !! pc)).
eapply transp_prop_6; eauto.
assert (D.ge (D.map (fun (_ : positive) (a : Approx.t) => transp_mem a)
(D.map (fun (_ : positive) (a : Approx.t) => transp a res)
(analyze f) !! pc)) ((analyze f) !! pc)).
eapply D.ge_trans; eauto.
generalize (transp_prop_6 ((analyze f)!! pc)); intro.
generalize H1; intro TRI.
rewrite D.gmap in TRI; try (simpl; trivial).
rewrite D.gmap in TRI; try (simpl; trivial).
generalize (transp_incr a res); intro.
generalize (transp_incr_bis a); intro.
destruct a.
unfold transp_mem in TRI.
analyze TRI for (transp (D.get r (analyze f) !! pc) res).
unfold transp in EQ.
analyze EQ for (D.get r (analyze f) !! pc).
unfold state_holds in H.
generalize (H _ _ EQ0); intro. inversion H8.
analyze TRI for o.
unfold eq_holds. trivial.
simpl .
assert (D.get r (analyze f) !! pc = Op o l). eapply filter_1; eauto.
assert (D.get r
(D.map (fun (_ : positive) (a : Approx.t) => transp a res)
(analyze f) !! pc) = Op o l). eapply filter_2; eauto.
assert ( D.get r
(D.map (fun (_ : positive) (a : Approx.t) => transp_mem a)
(analyze f) !! pc) = Op o l). eapply filter_3; eauto.
rewrite PMap.gso; auto. rewrite extended_gso; auto.
unfold state_holds in H. generalize (H _ _ H8); intro.
unfold eq_holds in H11. simpl in H11.
eapply transp_prop_4; eauto.
eapply transp_prop_2; eauto.
unfold transp_mem in TRI.
analyze TRI for (transp (D.get r (analyze f) !! pc) res).
analyze TRI for o.
Qed.
Lemma abstract_interpretation_correct :
forall f t stack c sp pc rs m es es' st st',
c = f.(fn_code) ->
st = State stack f sp pc rs m ->
es = (analyze f)!!pc ->
step ge st t st' ->
state_holds es st /\ stack_holds st ->
transfer f pc es = es' ->
state_holds es' st' /\ stack_holds st'.
Proof.
intros.
inversion H2; subst.
(* Inop *)
inversion H6; subst.
destruct H3. split; trivial.
unfold transfer. rewrite H5.
unfold state_holds. intros.
unfold state_holds in H.
generalize (H _ _ H1); intro. trivial.
(* Iop *)
inversion H7; subst.
destruct H3. split; trivial.
eapply transfer_op_correct; eauto.
(* Load *)
inversion H8; subst.
destruct H3. split; trivial.
eapply transfer_load_correct; eauto.
(* store *)
inversion H8; subst.
destruct H3. split; trivial.
eapply transfer_store_correct; eauto.
(* call *)
inversion H8; subst.
split. simpl. trivial.
simpl. destruct H3. simpl in H0.
intro. inversion H8; subst. clear H8.
generalize (H0 i); intro. intro.
destruct H3; eauto.
subst. unfold stackframe_holds. intros.
assert (forall r a, D.get r (transfer f pc (analyze f) !! pc) = a -> eq_holds r a (mk_std_state f sp rs # res <- v m0)).
intros.
eapply transfer_call_correct; eauto.
assert (In pc' (successors f pc)).
unfold successors. rewrite H5.
simpl; trivial. left; trivial.
assert ( transfer f pc (analyze f) !! pc = transfer f pc (analyze f) !! pc) by trivial.
generalize (analyze_correct_transf_bis f pc pc' (transfer f pc (analyze f) !! pc) H7 H8); intro.
unfold D.ge in H9. generalize (H9 r); intro. unfold Approx.ge in H10.
destruct H10. rewrite H10 in H3. rewrite <- H3. unfold eq_holds. trivial.
destruct H10. generalize (H4 _ _ H10); intro. unfold eq_holds in H11. inversion H11.
subst. eapply H4; eauto.
(* tailcall *)
inversion H8; subst.
destruct H3; split; trivial.
simpl. trivial.
(* alloc *)
inversion H8; subst.
destruct H3; split; trivial.
unfold state_holds. intros.
eapply transfer_alloc_correct; eauto.
(* cond *)
inversion H7; subst.
destruct H3; split; trivial.
unfold transfer. rewrite H5.
simpl. intros. unfold state_holds in H. eapply H; eauto.
(* cond *)
inversion H7; subst.
destruct H3; split; trivial.
unfold transfer. rewrite H5.
simpl. intros. unfold state_holds in H. eapply H; eauto.
(* return *)
inversion H6; subst.
destruct H3; split; trivial.
simpl. trivial.
(* fin *)
inversion H6.
inversion H6.
inversion H5.
Qed.
Lemma return_correct :
forall f t stack v m st st' s sp pc rs m',
st = Returnstate stack v m ->
st' = State s f sp pc rs m' ->
step ge st t st' ->
stack_holds st ->
state_holds (analyze f)!!pc st' /\ stack_holds st'.
Proof.
intros f t0 stack v m0 st st' s sp0 pc rs0 m' EQ1 EQ2 STEP HOLD.
subst. simpl in HOLD.
inversion STEP; subst.
generalize (HOLD (Stackframe res f sp0 pc rs)); intro.
assert (In (Stackframe res f sp0 pc rs) (Stackframe res f sp0 pc rs :: s)). unfold In; left; trivial.
generalize (H H0); intro.
unfold stackframe_holds in H1.
generalize (H1 m'); intro PROP.
clear H1 H0 H STEP.
simpl. split. intros. eapply PROP; eauto.
simpl. intros.
assert (In i s -> In i (Stackframe res f sp0 pc rs :: s)). intro. unfold In; right; trivial.
generalize (HOLD i (H0 H)); intro. trivial.
Qed.
Lemma call_correct :
forall f t stack args m st st' s c sp pc rs m',
st = Callstate stack (Internal f) args m ->
st' = State s c sp pc rs m' ->
step ge st t st' ->
stack_holds st ->
state_holds (analyze f)!!pc st' /\ stack_holds st'.
Proof.
intros f t stack args m0 st st' s c0 sp0 pc rs0 m' EQ1 EQ2 STEP HOLD.
subst. simpl in HOLD.
inversion STEP; subst.
split; trivial.
eapply analyze_correct_start; eauto.
Qed.
Lemma ext_call_correct :
forall f t stack args m st st',
st = Callstate stack (External f) args m ->
step ge st t st' ->
stack_holds st ->
stack_holds st'.
Proof.
intros f t0 stack args m0 st st' EQ STEP HOLD.
subst. inversion STEP; subst.
trivial.
Qed.
Lemma abstract_interpretation_correct_bis :
forall f t stack c sp pc rs m es es' st st',
c = f.(fn_code) ->
st = State stack f sp pc rs m ->
es = (analyze f)!!pc ->
step ge st t st' ->
state_holds es st /\ stack_holds st ->
transfer f pc es = es' ->
stack_holds st'.
Proof.
intros.
generalize (abstract_interpretation_correct f t stack c sp pc rs m es es' st st' H H0 H1 H2 H3 H4); intro.
destruct H5; trivial.
Qed.
Lemma analysis_correctness_step:
forall st t st',
holds st ->
step ge st t st' ->
holds st'.
Proof.
intros st t st' HOLD STEP.
inversion STEP; subst; unfold holds in HOLD; unfold holds.
(* Inop *)
destruct HOLD as[HO1 HO2].
assert (In pc' ((successors f) pc)).
unfold successors. rewrite H. unfold In. left; trivial.
subst.
eapply analyze_correct_transf; eauto.
eapply abstract_interpretation_correct; eauto.
(* Iop *)
destruct HOLD as [HO1 HO2].
assert (In pc' ((successors f) pc)). unfold successors. rewrite H. unfold In. left; trivial.
subst.
eapply analyze_correct_transf; eauto.
eapply abstract_interpretation_correct; eauto.
(* Iload *)
destruct HOLD as [HO1 HO2].
assert (In pc' ((successors f) pc)). unfold successors. rewrite H. unfold In. left; trivial.
subst.
eapply analyze_correct_transf; eauto.
eapply abstract_interpretation_correct; eauto.
(* Istore *)
destruct HOLD as [HO1 HO2].
assert (In pc' ((successors f) pc)). unfold successors. rewrite H. unfold In. left; trivial.
subst.
eapply analyze_correct_transf; eauto.
eapply abstract_interpretation_correct; eauto.
(* Icall *)
destruct HOLD as [HO1 HO2].
subst.
eapply abstract_interpretation_correct_bis; eauto.
(* Itailcall *)
destruct HOLD as [HO1 HO2].
subst.
eapply abstract_interpretation_correct_bis; eauto.
(* Ialloc *)
destruct HOLD as [HO1 HO2].
assert (In pc' ((successors f) pc)). unfold successors. rewrite H. unfold In. left; trivial.
subst.
eapply analyze_correct_transf; eauto.
eapply abstract_interpretation_correct; eauto.
(* Icond *)
destruct HOLD as [HO1 HO2].
assert (In ifso ((successors f) pc)). unfold successors. rewrite H. unfold In. left; trivial.
subst.
eapply analyze_correct_transf; eauto.
eapply abstract_interpretation_correct; eauto.
(* Icond *)
destruct HOLD as [HO1 HO2].
assert (In ifnot ((successors f) pc)). unfold successors. rewrite H. unfold In. right. left. trivial.
subst.
eapply analyze_correct_transf; eauto.
eapply abstract_interpretation_correct; eauto.
(* instruciton return, prouvee a la main sans appel au lemme *)
destruct HOLD as [EQ HOLD].
simpl. simpl in HOLD. trivial.
(* callstate vers state *)
eapply call_correct; eauto.
(* callsate vers returnstate *)
eapply ext_call_correct; eauto.
(* returnstate vers state *)
simpl in HOLD.
generalize (HOLD (Stackframe res c sp pc rs)); intro.
assert (Stackframe res c sp pc rs = Stackframe res c sp pc rs \/ In (Stackframe res c sp pc rs) s).
left; trivial.
generalize (H H0); intro.
unfold stackframe_holds in H1.
generalize (H1 m); clear H1; intro. split; trivial.
unfold state_holds. intros. eapply H1. auto. simpl.
intros.
assert (Stackframe res c sp pc rs = i \/ In i s) by (right; trivial).
eapply HOLD; eauto.
Qed.
Theorem analysis_correctness_generalized:
forall st t st',
Smallstep.star RTL2.step ge st t st' ->
holds st ->
holds st'.
Proof.
intros st t st' STEPS.
induction STEPS ; intros.
trivial.
eapply IHSTEPS; eauto.
eapply analysis_correctness_step; eauto.
Qed.
Lemma init_correct:
forall p st, initial_state p st -> holds st.
Proof.
intros.
inversion H; subst.
unfold holds. unfold stack_holds.
intros. inversion H3.
Qed.
End AN.
|
//
// ICBLBC functions
//
// Copyright (c) 2013-2014 Dominic Spill
//
// This file is part of Unambiguous Encapsulation.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; see the file COPYING. If not, write to
// the Free Software Foundation, Inc., 51 Franklin Street,
// Boston, MA 02110-1301, USA.
//
module hamming_distance (
input wire clock,
input wire [7:0] val_a, val_b,
output reg [3:0] distance
);
wire [7:0] bit_diff;
assign bit_diff = val_a ^ val_b;
always @(posedge clock) begin
// Unless I misunderstood him, Marshall said this should work
distance = bit_diff[0] + bit_diff[1] + bit_diff[2] + bit_diff[3]
+ bit_diff[4] + bit_diff[5] + bit_diff[6] + bit_diff[7];
end
endmodule
// Populate candidates module
module populate_candidates (
input wire clock,
input wire [7:0] code,
input wire [7:0] base_candidate_addr,
output reg [7:0] addr_candidates,
input wire [7:0] read_candidates,
input wire [7:0] candidate_len,
input wire [7:0] base_next_cand_addr,
output reg [7:0] addr_next_cand,
output reg [7:0] data_next_cand,
output wire wren_next_cand,
output reg [7:0] next_cand_len,
input wire [3:0] min_dist,
input wire start,
output wire complete
);
wire [3:0] distance;
reg [7:0] ham_in_a, ham_in_b;
hamming_distance hd (
.clock ( clock),
.val_a ( ham_in_a ),
.val_b ( ham_in_b ),
.distance ( distance )
);
reg done;
assign complete = (done == 1 || state == ST_DONE);
reg write_cand;
assign wren_next_cand = write_cand;
reg [7:0] icand, inext;
reg start_1, start_2;
reg [5:0] state;
parameter [5:0] ST_RST = 6'h00,
ST_IDLE = 6'h01,
ST_DONE = 6'h07;
always @(posedge clock) begin
{start_2, start_1} <= {start_1, start};
case(state)
ST_RST: begin
done <= 0;
state <= ST_IDLE;
end
ST_IDLE: begin
if( start_2 ) begin
ham_in_a <= code;
icand <= 0;
inext <= 0;
state <= 3;
done <= 0;
end
end
// Read next candidate
3: begin
addr_candidates <= base_candidate_addr + icand;
state <= 4;
end
//
4: begin
ham_in_b <= read_candidates;
state <= 5;
end
5: begin
if ( distance >= min_dist ) begin
data_next_cand <= read_candidates;
addr_next_cand <= base_next_cand_addr + inext;
write_cand <= 1;
end
state <= 6;
end
6: begin
// Unsure if I need to wait until here to increment inext
if ( distance >= min_dist ) begin
inext <= inext + 1;
end
write_cand <= 0;
icand <= icand + 1;
if ( icand > candidate_len ) begin
done <= 1;
next_cand_len <= inext;
state <= 7;
end else begin
state <= 3;
end
end
ST_DONE: begin
state <= ST_IDLE;
end
endcase
end
endmodule
module find_iso (
input clock,
input wire start,
output wire complete
);
reg start_1, start_2;
reg [5:0] state;
parameter [5:0] ST_RST = 6'h00,
ST_IDLE = 6'h01;
always @(posedge clock) begin
{start_2, start_1} <= {start_1, start};
case(state)
ST_RST: begin
state <= ST_IDLE;
end
ST_IDLE: begin
if( start_2 ) begin
state <= 3;
end
end
3: begin
state <= 4;
end
4: begin
state <= 5;
end
5: begin
state <= 6;
end
6: begin
state <= ST_IDLE;
end
endcase
end
endmodule
module find_best_iso (
input wire clock,
input wire [7:0] min_hd,
input wire [7:0] min_iso,
input wire start_process,
output reg complete
);
parameter n = 5;
parameter MAX_N = 8;
parameter MAX_CAND = 2**MAX_N;
reg [5:0] state;
parameter [5:0] ST_RST = 6'h00,
ST_IDLE = 6'h01;
reg [7:0] count, icand;
reg [7:0] a_len, min_b_len;
reg start_process_1, start_process_2;
// Storage for sets of codes
wire wren_codes;
wire [7:0] read_codes;
wire [10:0] addr_codes;
wire [7:0] data_codes;
icblbc_ram codes (
.address ( addr_codes ),
.clock ( clock ),
.data ( data_codes ),
.wren ( wren_codes ),
.q ( read_codes )
);
reg fi_en;
find_iso fi (
.clock ( clock ),
.start ( fi_en ),
.complete ( fi_done )
);
always @(posedge clock) begin
{start_process_2, start_process_1} <= {start_process_1, start_process};
case(state)
ST_RST: begin
state <= ST_IDLE;
end
ST_IDLE: begin
if( start_process_2 ) begin
state <= 3;
a_len <= 1<<(n-1);
min_b_len <= 2;
end
end
3: begin
state <= 4;
end
4: begin
state <= 5;
end
5: begin
state <= 10;
end
// Wait for find_iso() to finish
10: begin
fi_en <= 1;
state <= 11;
end
11: begin
if( fi_done ) begin
state <= 12;
end
end
12: begin
state <= 13;
end
20: begin
state <= ST_IDLE;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR2_BLACKBOX_V
`define SKY130_FD_SC_LP__OR2_BLACKBOX_V
/**
* or2: 2-input OR.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__or2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR2_BLACKBOX_V
|
module TimeHoldOver_Qsys (
clk_clk,
epcs_flash_controller_dclk,
epcs_flash_controller_sce,
epcs_flash_controller_sdo,
epcs_flash_controller_data0,
on_chip_rst_and_pps_switch_export,
io_update_ctrl_export,
ocxo_lock_export,
pps_interrupt_export,
reset_reset_n,
sdram_controller_addr,
sdram_controller_ba,
sdram_controller_cas_n,
sdram_controller_cke,
sdram_controller_cs_n,
sdram_controller_dq,
sdram_controller_dqm,
sdram_controller_ras_n,
sdram_controller_we_n,
timer_ecc_fault_itr_export,
timer_interface_coe_sec_cnt_set_data_out,
timer_interface_coe_sec_cnt_get_data_in,
timer_interface_coe_ns_cnt_set_data_out,
timer_interface_coe_ns_cnt_get_data_in,
timer_interface_coe_ctrl_cnt_set_out,
timer_interface_coe_ctrl_cnt_get_in,
timer_interface_coe_err_cnt_in,
timer_interface_coe_utc_time_in,
timer_interface_coe_time_zone_set_out,
timer_interface_coe_time_zone_get_in,
timer_interface_coe_leap_cnt_set_out,
timer_interface_coe_leap_cnt_get_in,
timer_interface_coe_leap_occur_set_out,
timer_interface_coe_leap_occur_get_in,
timer_interface_coe_dst_ingress_set_out,
timer_interface_coe_dst_ingress_get_in,
timer_interface_coe_dst_engress_set_out,
timer_interface_coe_dst_engress_get_in,
timer_interface_coe_leap_direct_get_in,
timer_interface_coe_leap_direct_set_out,
timer_interface_coe_io_update_in,
timer_interface_coe_time_quality_get_in,
timer_interface_coe_time_quality_set_out,
uart_0_external_connection_rxd,
uart_0_external_connection_txd,
uart_1_external_connection_rxd,
uart_1_external_connection_txd,
uart_2_external_connection_rxd,
uart_2_external_connection_txd,
uart_3_external_connection_rxd,
uart_3_external_connection_txd);
input clk_clk;
output epcs_flash_controller_dclk;
output epcs_flash_controller_sce;
output epcs_flash_controller_sdo;
input epcs_flash_controller_data0;
output [8:0] on_chip_rst_and_pps_switch_export;
output io_update_ctrl_export;
input ocxo_lock_export;
input pps_interrupt_export;
input reset_reset_n;
output [11:0] sdram_controller_addr;
output [1:0] sdram_controller_ba;
output sdram_controller_cas_n;
output sdram_controller_cke;
output sdram_controller_cs_n;
inout [15:0] sdram_controller_dq;
output [1:0] sdram_controller_dqm;
output sdram_controller_ras_n;
output sdram_controller_we_n;
input timer_ecc_fault_itr_export;
output [192:0] timer_interface_coe_sec_cnt_set_data_out;
input [191:0] timer_interface_coe_sec_cnt_get_data_in;
output [96:0] timer_interface_coe_ns_cnt_set_data_out;
input [95:0] timer_interface_coe_ns_cnt_get_data_in;
output [24:0] timer_interface_coe_ctrl_cnt_set_out;
input [23:0] timer_interface_coe_ctrl_cnt_get_in;
input [23:0] timer_interface_coe_err_cnt_in;
input [55:0] timer_interface_coe_utc_time_in;
output [8:0] timer_interface_coe_time_zone_set_out;
input [7:0] timer_interface_coe_time_zone_get_in;
output [16:0] timer_interface_coe_leap_cnt_set_out;
input [15:0] timer_interface_coe_leap_cnt_get_in;
output [64:0] timer_interface_coe_leap_occur_set_out;
input [63:0] timer_interface_coe_leap_occur_get_in;
output [64:0] timer_interface_coe_dst_ingress_set_out;
input [63:0] timer_interface_coe_dst_ingress_get_in;
output [64:0] timer_interface_coe_dst_engress_set_out;
input [63:0] timer_interface_coe_dst_engress_get_in;
input [7:0] timer_interface_coe_leap_direct_get_in;
output [8:0] timer_interface_coe_leap_direct_set_out;
input timer_interface_coe_io_update_in;
input [7:0] timer_interface_coe_time_quality_get_in;
output [8:0] timer_interface_coe_time_quality_set_out;
input uart_0_external_connection_rxd;
output uart_0_external_connection_txd;
input uart_1_external_connection_rxd;
output uart_1_external_connection_txd;
input uart_2_external_connection_rxd;
output uart_2_external_connection_txd;
input uart_3_external_connection_rxd;
output uart_3_external_connection_txd;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_FUNCTIONAL_V
`define SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_FUNCTIONAL_V
/**
* lpflow_inputiso1p: Input isolation, noninverted sleep.
*
* X = (A & !SLEEP)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__lpflow_inputiso1p (
X ,
A ,
SLEEP
);
// Module ports
output X ;
input A ;
input SLEEP;
// Name Output Other arguments
or or0 (X , A, SLEEP );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_INPUTISO1P_FUNCTIONAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A22OI_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__A22OI_BEHAVIORAL_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__a22oi (
Y ,
A1,
A2,
B1,
B2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y, nand0_out, nand1_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A22OI_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FAH_FUNCTIONAL_V
`define SKY130_FD_SC_LS__FAH_FUNCTIONAL_V
/**
* fah: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__fah (
COUT,
SUM ,
A ,
B ,
CI
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Local signals
wire xor0_out_SUM;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT;
// Name Output Other arguments
xor xor0 (xor0_out_SUM, A, B, CI );
buf buf0 (SUM , xor0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, CI );
and and2 (b_ci , B, CI );
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
buf buf1 (COUT , or0_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__FAH_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DLXTP_SYMBOL_V
`define SKY130_FD_SC_HVL__DLXTP_SYMBOL_V
/**
* dlxtp: Delay latch, non-inverted enable, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dlxtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DLXTP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISOLATCH_BEHAVIORAL_V
`define SKY130_FD_SC_LP__ISOLATCH_BEHAVIORAL_V
/**
* isolatch: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_isolatch_pp_pkg_sn/sky130_fd_sc_lp__udp_isolatch_pp_pkg_sn.v"
`celldefine
module sky130_fd_sc_lp__isolatch (
Q ,
D ,
SLEEP_B
);
// Module ports
output Q ;
input D ;
input SLEEP_B;
// Module supplies
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire SLEEP_B_delayed;
wire D_delayed ;
reg notifier ;
// Name Output Other arguments
sky130_fd_sc_lp__udp_isolatch_pp$PKG$sN isolatch_pp0 (buf_Q , D_delayed, SLEEP_B_delayed, notifier, KAPWR, VGND, VPWR);
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISOLATCH_BEHAVIORAL_V |
// VGA¿ØÖÆÄ£¿é ¸ù¾Ýµ±Ç°É¨Ãèµ½µÄµãÊÇÄÄÒ»²¿·ÖÊä³öÏàÓ¦ÑÕÉ«
module VGA_Control
(
input clk,
input rst,
input [7:0]snake,
input [7:0]apple_x,
input [7:0]apple_y,
output reg[9:0]x_pos,
output reg[9:0]y_pos,
output reg hsync,
output reg vsync,
output reg [11:0] color_out
);
reg [19:0]clk_cnt;
reg [9:0]line_cnt;
reg clk_25M;
localparam NONE = 7'b0000_000;
localparam HEAD = 7'b0000_001;
localparam BODY = 7'b0000_010;
localparam WALL = 7'b0000_011;
localparam HEAD_COLOR = 12'b0000_1111_0000;
localparam BODY_COLOR = 12'b0000_1111_1111;
reg [3:0]lox;
reg [3:0]loy;
always@(posedge clk or posedge rst) begin
if(rst) begin
clk_cnt <= 0;
line_cnt <= 0;
hsync <= 1;
vsync <= 1;
end
else begin
x_pos <= clk_cnt - 144;
y_pos <= line_cnt - 33;
if(clk_cnt == 0) begin
hsync <= 0;
clk_cnt <= clk_cnt + 1;
end
else if(clk_cnt == 96) begin
hsync <= 1;
clk_cnt <= clk_cnt + 1;
end
else if(clk_cnt == 799) begin
clk_cnt <= 0;
line_cnt <= line_cnt + 1;
end
else clk_cnt <= clk_cnt + 1;
if(line_cnt == 0) begin
vsync <= 0;
end
else if(line_cnt == 2) begin
vsync <= 1;
end
else if(line_cnt == 521) begin
line_cnt <= 0;
vsync <= 0;
end
if(x_pos >= 0 && x_pos < 640 && y_pos >= 0 && y_pos < 480) begin
lox = x_pos[3:0];
loy = y_pos[3:0];
if(x_pos[9:4] == apple_x && y_pos[9:4] == apple_y)
case({loy,lox})
8'b0000_0000:color_out = 12'b0000_0000_0000;
default:color_out = 12'b0000_0000_1111;
endcase
else if(snake == NONE)
color_out = 12'b0000_0000_0000;
else if(snake == WALL)
color_out = 3'b101;
else if(snake == HEAD|snake == BODY) begin //¸ù¾Ýµ±Ç°É¨Ãèµ½µÄµãÊÇÄÄÒ»²¿·ÖÊä³öÏàÓ¦ÑÕÉ«
case({lox,loy})
8'b0000_0000:color_out = 12'b0000_0000_0000;
default:color_out = (snake == HEAD) ? HEAD_COLOR : BODY_COLOR;
endcase
end
end
else
color_out = 12'b0000_0000_0000;
end
end
endmodule |
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