input
stringlengths 144
489k
| output
stringlengths 45
339k
| shard
stringclasses 16
values | filename
stringlengths 135
135
| line_num
int64 0
2.62k
| context
list |
|---|---|---|---|---|---|
{"name": "gen_op_iwmmxt_addsl_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_addsl_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_addsl ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 921 |
[
"{\"name\": \"gen_helper_iwmmxt_addsl\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_addsl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_addsl , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_avgb0_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_avgb0_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_avgb0 ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 922 |
[
"{\"name\": \"gen_helper_iwmmxt_avgb0\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_avgb0 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_avgb0 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_avgb1_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_avgb1_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_avgb1 ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 923 |
[
"{\"name\": \"gen_helper_iwmmxt_avgb1\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_avgb1 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_avgb1 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_avgw0_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_avgw0_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_avgw0 ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 924 |
[
"{\"name\": \"gen_helper_iwmmxt_avgw0\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_avgw0 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_avgw0 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_avgw1_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_avgw1_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_avgw1 ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 925 |
[
"{\"name\": \"gen_helper_iwmmxt_avgw1\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_avgw1 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_avgw1 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_packuw_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_packuw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_packuw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 926 |
[
"{\"name\": \"gen_helper_iwmmxt_packuw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_packuw ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_packuw , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_packul_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_packul_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_packul ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 927 |
[
"{\"name\": \"gen_helper_iwmmxt_packul\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_packul ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_packul , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_packuq_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_packuq_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_packuq ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 928 |
[
"{\"name\": \"gen_helper_iwmmxt_packuq\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_packuq ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_packuq , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_packsw_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_packsw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_packsw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 929 |
[
"{\"name\": \"gen_helper_iwmmxt_packsw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_packsw ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_packsw , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_packsl_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_packsl_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_packsl ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 930 |
[
"{\"name\": \"gen_helper_iwmmxt_packsl\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_packsl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_packsl , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_packsq_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_packsq_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_packsq ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 931 |
[
"{\"name\": \"gen_helper_iwmmxt_packsq\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_packsq ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_packsq , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_set_mup", "code": "__int64 gen_op_iwmmxt_set_mup ( ) { __int64 @@v1@@ ; @@v1@@ = load_cpu_offset ( Number ) ; tcg_gen_ori_i32 ( @@v1@@ , @@v1@@ , Number L ) ; return store_cpu_offset ( @@v1@@ , Number ) ; }", "source": [{"n": "v1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 932 |
[
"{\"name\": \"load_cpu_offset\", \"code\": \"__int64 __fastcall load_cpu_offset ( int @@a1@@ ) { __int64 @@v2@@ ; @@v2@@ = tcg_temp_new_i32 ( ) ; tcg_gen_ld_i32 ( @@v2@@ , cpu_env , @@a1@@ ) ; return @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_cpu_offset\", \"code\": \"__int64 __fastcall store_cpu_offset ( __int64 @@a1@@ , int @@a2@@ ) { tcg_gen_st_i32 ( @@a1@@ , cpu_env , @@a2@@ ) ; return tcg_temp_free_i32 ( @@a1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_set_cup", "code": "__int64 gen_op_iwmmxt_set_cup ( ) { __int64 @@v1@@ ; @@v1@@ = load_cpu_offset ( Number ) ; tcg_gen_ori_i32 ( @@v1@@ , @@v1@@ , Number L ) ; return store_cpu_offset ( @@v1@@ , Number ) ; }", "source": [{"n": "v1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 933 |
[
"{\"name\": \"load_cpu_offset\", \"code\": \"__int64 __fastcall load_cpu_offset ( int @@a1@@ ) { __int64 @@v2@@ ; @@v2@@ = tcg_temp_new_i32 ( ) ; tcg_gen_ld_i32 ( @@v2@@ , cpu_env , @@a1@@ ) ; return @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_cpu_offset\", \"code\": \"__int64 __fastcall store_cpu_offset ( __int64 @@a1@@ , int @@a2@@ ) { tcg_gen_st_i32 ( @@a1@@ , cpu_env , @@a2@@ ) ; return tcg_temp_free_i32 ( @@a1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_setpsr_nz", "code": "__int64 gen_op_iwmmxt_setpsr_nz ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_i32 ( ) ; gen_helper_iwmmxt_setpsr_nz ( @@v1@@ , cpu_M0 ) ; return store_cpu_offset ( @@v1@@ , Number ) ; }", "source": [{"n": "v1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 934 |
[
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_setpsr_nz\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_setpsr_nz ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i64_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_setpsr_nz , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_cpu_offset\", \"code\": \"__int64 __fastcall store_cpu_offset ( __int64 @@a1@@ , int @@a2@@ ) { tcg_gen_st_i32 ( @@a1@@ , cpu_env , @@a2@@ ) ; return tcg_temp_free_i32 ( @@a1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_addl_M0_wRn", "code": "__int64 __fastcall gen_op_iwmmxt_addl_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; tcg_gen_ext32u_i64 ( cpu_V1 , cpu_V1 ) ; return tcg_gen_add_i64 ( cpu_M0 , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 935 |
[
"{\"name\": \"tcg_gen_add_i64\", \"code\": \"__int64 __fastcall tcg_gen_add_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_iwmmxt_address", "code": "_BOOL8 __fastcall gen_iwmmxt_address ( __int64 @@a1@@ , unsigned int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v5@@ ; __int64 @@v6@@ ; @@v6@@ = load_reg ( @@a1@@ , HIWORD ( @@a2@@ ) & Number ) ; @@v5@@ = ( unsigned __int8 ) @@a2@@ << ( ( @@a2@@ >> Number ) & Number ) ; if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) != Number ) tcg_gen_addi_i32 ( @@v6@@ , @@v6@@ , @@v5@@ ) ; else tcg_gen_addi_i32 ( @@v6@@ , @@v6@@ , - @@v5@@ ) ; tcg_gen_mov_i32 ( @@a3@@ , @@v6@@ ) ; if ( ( @@a2@@ & Number ) == Number ) { tcg_temp_free_i32 ( @@v6@@ ) ; return Number L ; } goto LABEL_6 ; } if ( ( @@a2@@ & Number ) != Number ) { tcg_gen_mov_i32 ( @@a3@@ , @@v6@@ ) ; if ( ( @@a2@@ & Number ) != Number ) tcg_gen_addi_i32 ( @@v6@@ , @@v6@@ , @@v5@@ ) ; else tcg_gen_addi_i32 ( @@v6@@ , @@v6@@ , - @@v5@@ ) ; LABEL_6 : store_reg ( @@a1@@ , HIWORD ( @@a2@@ ) & Number , @@v6@@ ) ; return Number L ; } return ( @@a2@@ & Number ) == Number ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "v5", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "dest", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "insn", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r64"}, {"n": "offset", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "s12"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 936 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_gen_mov_i32\", \"code\": \"__int64 __fastcall tcg_gen_mov_i32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@result@@ ; @@result@@ = @@a1@@ ; if ( @@a1@@ != @@a2@@ ) @@result@@ = tcg_gen_op2_i32 ( Number , @@a1@@ , @@a2@@ ) ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_iwmmxt_shift", "code": "__int64 __fastcall gen_iwmmxt_shift ( __int16 @@a1@@ , unsigned int @@a2@@ , __int64 @@a3@@ ) { int @@v5@@ ; __int64 @@v6@@ ; @@v5@@ = @@a1@@ & Number ; if ( ( @@a1@@ & Number ) != Number ) { if ( ( @@a1@@ & Number ) <= Number || ( @@a1@@ & Number ) > Number ) return Number L ; @@v6@@ = iwmmxt_load_creg ( @@v5@@ ) ; tcg_gen_andi_i32 ( @@v6@@ , @@v6@@ , @@a2@@ ) ; } else { @@v6@@ = tcg_temp_new_i32 ( ) ; iwmmxt_load_reg ( cpu_V0 , @@v5@@ ) ; tcg_gen_extrl_i64_i32 ( @@v6@@ , cpu_V0 ) ; tcg_gen_andi_i32 ( @@v6@@ , @@v6@@ , @@a2@@ ) ; } tcg_gen_mov_i32 ( @@a3@@ , @@v6@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return Number L ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int16", "s": 2}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "v5", "t": {"T": 1, "n": "int", "s": 4}, "location": "s12"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "dest", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "insn", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r56"}, {"n": "mask", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r64"}, {"n": "rd", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "s12"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 937 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_mov_i32\", \"code\": \"__int64 __fastcall tcg_gen_mov_i32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@result@@ ; @@result@@ = @@a1@@ ; if ( @@a1@@ != @@a2@@ ) @@result@@ = tcg_gen_op2_i32 ( Number , @@a1@@ , @@a2@@ ) ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"iwmmxt_load_creg\", \"code\": \"__int64 __fastcall iwmmxt_load_creg ( int @@a1@@ ) { __int64 @@v2@@ ; @@v2@@ = tcg_temp_new_i32 ( ) ; tcg_gen_ld_i32 ( @@v2@@ , cpu_env , Number * ( @@a1@@ + Number L ) ) ; return @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "disas_iwmmxt_insn", "code": "__int64 __fastcall disas_iwmmxt_insn ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 result ; int v3 ; int v4 ; int v5 ; int v6 ; int v7 ; int v8 ; int v9 ; int v10 ; unsigned int v11 ; int v12 ; int v13 ; int v14 ; unsigned int v15 ; int v16 ; int v17 ; unsigned int v18 ; int v19 ; int v20 ; int v21 ; int v22 ; int v23 ; int v24 ; int v25 ; int v26 ; int v27 ; int v28 ; int v29 ; int v30 ; int v31 ; int v32 ; unsigned int v33 ; int v34 ; int j ; int i ; int l ; int k ; int v39 ; int v40 ; int v41 ; int v42 ; int v43 ; int v44 ; int v45 ; int v46 ; int @@v47@@ ; int v48 ; int v49 ; int v50 ; int v51 ; int v52 ; int v53 ; int v54 ; int v55 ; int v56 ; int v57 ; int v58 ; int v59 ; int v60 ; int v61 ; int v62 ; int v63 ; int v64 ; int @@v65@@ ; __int64 v66 ; __int64 v67 ; __int64 v68 ; __int64 v69 ; __int64 v70 ; __int64 v71 ; __int64 v72 ; __int64 v73 ; __int64 v74 ; __int64 v75 ; __int64 v76 ; __int64 v77 ; __int64 v78 ; __int64 v79 ; __int64 v80 ; __int64 v81 ; __int64 v82 ; __int64 v83 ; __int64 v84 ; __int64 v85 ; __int64 v86 ; __int64 @@v87@@ ; __int64 @@v88@@ ; if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) != Number ) return Number L ; v11 = ( @@a2@@ >> Number ) & Number | ( unsigned __int8 ) ( @@a2@@ >> Number ) ; if ( v11 > Number ) return Number L ; if ( v11 < Number ) { if ( v11 > Number ) return Number L ; if ( v11 >= Number ) { switch ( v11 ) { case Number : case Number : LABEL_271 : if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) return Number L ; v45 = ( unsigned __int16 ) @@a2@@ >> Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v79 = tcg_temp_new_i32 ( ) ; if ( ( unsigned int ) gen_iwmmxt_shift ( @@a2@@ , Number , v79 ) ) goto LABEL_314 ; v26 = ( @@a2@@ >> Number ) & Number ; switch ( v26 ) { case Number : gen_helper_iwmmxt_srlq ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; break ; case Number : gen_helper_iwmmxt_srlw ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; break ; case Number : gen_helper_iwmmxt_srll ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; break ; } goto LABEL_316 ; case Number : goto LABEL_369 ; case Number : LABEL_258 : v43 = ( unsigned __int16 ) @@a2@@ >> Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v25 = ( @@a2@@ >> Number ) & Number ; if ( v25 == Number ) return Number L ; if ( v25 == Number ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_unpackhsl_M0 ( ) ; else gen_op_iwmmxt_unpackhul_M0 ( ) ; } else if ( v25 ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_unpackhsw_M0 ( ) ; else gen_op_iwmmxt_unpackhuw_M0 ( ) ; } else if ( ( @@a2@@ & Number ) != Number ) { gen_op_iwmmxt_unpackhsb_M0 ( ) ; } else { gen_op_iwmmxt_unpackhub_M0 ( ) ; } goto LABEL_385 ; case Number : LABEL_245 : v43 = ( unsigned __int16 ) @@a2@@ >> Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v24 = ( @@a2@@ >> Number ) & Number ; if ( v24 == Number ) return Number L ; if ( v24 == Number ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_unpacklsl_M0 ( ) ; else gen_op_iwmmxt_unpacklul_M0 ( ) ; } else if ( v24 ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_unpacklsw_M0 ( ) ; else gen_op_iwmmxt_unpackluw_M0 ( ) ; } else if ( ( @@a2@@ & Number ) != Number ) { gen_op_iwmmxt_unpacklsb_M0 ( ) ; } else { gen_op_iwmmxt_unpacklub_M0 ( ) ; } goto LABEL_385 ; case Number : LABEL_330 : v42 = ( unsigned __int16 ) @@a2@@ >> Number ; v58 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v31 = ( @@a2@@ >> Number ) & Number ; if ( v31 == Number ) return Number L ; if ( v31 == Number ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_maxsl_M0_wRn ( v58 ) ; else gen_op_iwmmxt_maxul_M0_wRn ( v58 ) ; } else if ( v31 ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_maxsw_M0_wRn ( v58 ) ; else gen_op_iwmmxt_maxuw_M0_wRn ( v58 ) ; } else if ( ( @@a2@@ & Number ) != Number ) { gen_op_iwmmxt_maxsb_M0_wRn ( v58 ) ; } else { gen_op_iwmmxt_maxub_M0_wRn ( v58 ) ; } break ; case Number : goto LABEL_357 ; case Number : goto LABEL_344 ; case Number : goto LABEL_356 ; default : return Number L ; } } else { if ( v11 > Number ) return Number L ; if ( v11 >= Number ) { switch ( v11 ) { case Number : LABEL_132 : v43 = ( unsigned __int16 ) @@a2@@ >> Number ; v55 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_avgw1_M0_wRn ( v55 ) ; else gen_op_iwmmxt_avgw0_M0_wRn ( v55 ) ; } else if ( ( @@a2@@ & Number ) != Number ) { gen_op_iwmmxt_avgb1_M0_wRn ( v55 ) ; } else { gen_op_iwmmxt_avgb0_M0_wRn ( v55 ) ; } goto LABEL_385 ; case Number : LABEL_222 : v64 = ( unsigned __int16 ) @@a2@@ >> Number ; if ( ( @@a2@@ & Number ) != Number || ( ( @@a2@@ >> Number ) & Number ) == Number ) return Number L ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v75 = tcg_temp_new_i32 ( ) ; v22 = ( @@a2@@ >> Number ) & Number ; if ( v22 == Number ) { gen_helper_iwmmxt_msbl ( v75 , cpu_M0 ) ; } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { if ( v22 ) gen_helper_iwmmxt_msbw ( v75 , cpu_M0 ) ; else gen_helper_iwmmxt_msbb ( v75 , cpu_M0 ) ; } goto LABEL_231 ; case Number : case Number : LABEL_292 : if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) return Number L ; v45 = ( unsigned __int16 ) @@a2@@ >> Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v79 = tcg_temp_new_i32 ( ) ; if ( ( unsigned int ) gen_iwmmxt_shift ( @@a2@@ , Number , v79 ) ) goto LABEL_314 ; v28 = ( @@a2@@ >> Number ) & Number ; switch ( v28 ) { case Number : gen_helper_iwmmxt_sllq ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; break ; case Number : gen_helper_iwmmxt_sllw ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; break ; case Number : gen_helper_iwmmxt_slll ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; break ; } goto LABEL_316 ; case Number : goto LABEL_232 ; case Number : LABEL_150 : v64 = ( unsigned __int16 ) @@a2@@ >> Number ; if ( v64 == Number || ( ( @@a2@@ >> Number ) & Number ) == Number ) return Number L ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v75 = tcg_temp_new_i32 ( ) ; v16 = ( @@a2@@ >> Number ) & Number ; if ( v16 == Number ) { tcg_gen_shri_i64 ( cpu_M0 , cpu_M0 , ( Number * ( _BYTE ) @@a2@@ ) & Number ) ; tcg_gen_extrl_i64_i32 ( v75 , cpu_M0 ) ; } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { if ( v16 ) { tcg_gen_shri_i64 ( cpu_M0 , cpu_M0 , ( Number * ( _BYTE ) @@a2@@ ) & Number ) ; tcg_gen_extrl_i64_i32 ( v75 , cpu_M0 ) ; if ( ( @@a2@@ & Number ) != Number ) tcg_gen_ext16s_i32 ( v75 , v75 ) ; else tcg_gen_andi_i32 ( v75 , v75 , Number ) ; } else { tcg_gen_shri_i64 ( cpu_M0 , cpu_M0 , ( Number * ( _BYTE ) @@a2@@ ) & Number ) ; tcg_gen_extrl_i64_i32 ( v75 , cpu_M0 ) ; if ( ( @@a2@@ & Number ) != Number ) tcg_gen_ext8s_i32 ( v75 , v75 ) ; else tcg_gen_andi_i32 ( v75 , v75 , Number L ) ; } } LABEL_231 : store_reg ( @@a1@@ , v64 , v75 ) ; return Number L ; case Number : goto LABEL_369 ; case Number : LABEL_99 : v43 = ( unsigned __int16 ) @@a2@@ >> Number ; v50 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v13 = ( @@a2@@ >> Number ) & Number ; if ( v13 == Number ) return Number L ; if ( v13 == Number ) { gen_op_iwmmxt_unpackhl_M0_wRn ( v50 ) ; } else if ( v13 ) { gen_op_iwmmxt_unpackhw_M0_wRn ( v50 ) ; } else { gen_op_iwmmxt_unpackhb_M0_wRn ( v50 ) ; } goto LABEL_385 ; case Number : LABEL_92 : v43 = ( unsigned __int16 ) @@a2@@ >> Number ; v49 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v12 = ( @@a2@@ >> Number ) & Number ; if ( v12 == Number ) return Number L ; if ( v12 == Number ) { gen_op_iwmmxt_unpackll_M0_wRn ( v49 ) ; } else if ( v12 ) { gen_op_iwmmxt_unpacklw_M0_wRn ( v49 ) ; } else { gen_op_iwmmxt_unpacklb_M0_wRn ( v49 ) ; } goto LABEL_385 ; case Number : LABEL_183 : if ( ( @@a2@@ & Number ) != ( _DWORD ) & loc_3F000 || ( ( @@a2@@ >> Number ) & Number ) == Number ) return Number L ; v78 = iwmmxt_load_creg ( Number ) ; v85 = tcg_temp_new_i32 ( ) ; tcg_gen_mov_i32 ( v85 , v78 ) ; v19 = ( @@a2@@ >> Number ) & Number ; if ( v19 == Number ) { tcg_gen_shli_i32 ( v85 , v85 , Number L ) ; tcg_gen_and_i32 ( v78 , v78 , v85 ) ; } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { if ( v19 ) { for ( i = Number ; i <= Number ; ++ i ) { tcg_gen_shli_i32 ( v85 , v85 , Number L ) ; tcg_gen_and_i32 ( v78 , v78 , v85 ) ; } } else { for ( j = Number ; j <= Number ; ++ j ) { tcg_gen_shli_i32 ( v85 , v85 , Number L ) ; tcg_gen_and_i32 ( v78 , v78 , v85 ) ; } } } goto LABEL_198 ; case Number : LABEL_206 : if ( ( @@a2@@ & Number ) != ( _DWORD ) & loc_3F000 || ( ( @@a2@@ >> Number ) & Number ) == Number ) return Number L ; v78 = iwmmxt_load_creg ( Number ) ; v85 = tcg_temp_new_i32 ( ) ; tcg_gen_mov_i32 ( v85 , v78 ) ; v21 = ( @@a2@@ >> Number ) & Number ; if ( v21 == Number ) { tcg_gen_shli_i32 ( v85 , v85 , Number L ) ; tcg_gen_or_i32 ( v78 , v78 , v85 ) ; } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { if ( v21 ) { for ( k = Number ; k <= Number ; ++ k ) { tcg_gen_shli_i32 ( v85 , v85 , Number L ) ; tcg_gen_or_i32 ( v78 , v78 , v85 ) ; } } else { for ( l = Number ; l <= Number ; ++ l ) { tcg_gen_shli_i32 ( v85 , v85 , Number L ) ; tcg_gen_or_i32 ( v78 , v78 , v85 ) ; } } } LABEL_198 : gen_set_cpsr ( v78 , Number ) ; tcg_temp_free_i32 ( v85 ) ; tcg_temp_free_i32 ( v78 ) ; return Number L ; case Number : goto LABEL_317 ; case Number : LABEL_164 : if ( ( @@a2@@ & Number ) != ( _DWORD ) & loc_3F000 || ( ( @@a2@@ >> Number ) & Number ) == Number ) return Number L ; v76 = iwmmxt_load_creg ( Number ) ; v17 = ( @@a2@@ >> Number ) & Number ; if ( v17 == Number ) { tcg_gen_shri_i32 ( v76 , v76 , ( ( Number * ( _BYTE ) @@a2@@ ) & Number ) + Number ) ; } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { if ( v17 ) tcg_gen_shri_i32 ( v76 , v76 , ( ( Number * ( _BYTE ) @@a2@@ ) & Number ) + Number ) ; else tcg_gen_shri_i32 ( v76 , v76 , ( Number * ( _BYTE ) @@a2@@ ) & Number ) ; } tcg_gen_shli_i32 ( v76 , v76 , Number L ) ; gen_set_cpsr ( v76 , Number ) ; tcg_temp_free_i32 ( v76 ) ; break ; case Number : goto LABEL_357 ; case Number : goto LABEL_344 ; case Number : goto LABEL_356 ; default : return Number L ; } return Number L ; } if ( v11 > Number ) return Number L ; if ( v11 < Number ) { if ( v11 <= Number ) { if ( v11 >= Number ) { switch ( v11 ) { case Number : LABEL_139 : gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v73 = iwmmxt_load_creg ( ( ( @@a2@@ >> Number ) & Number ) + Number ) ; tcg_gen_andi_i32 ( v73 , v73 , Number L ) ; iwmmxt_load_reg ( cpu_V1 , @@a2@@ & Number ) ; gen_helper_iwmmxt_align ( cpu_M0 , cpu_M0 , cpu_V1 , v73 ) ; tcg_temp_free_i32 ( v73 ) ; gen_op_iwmmxt_movq_wRn_M0 ( ( unsigned __int16 ) @@a2@@ >> Number ) ; gen_op_iwmmxt_set_mup ( ) ; return Number L ; case Number : case Number : goto LABEL_302 ; case Number : goto LABEL_232 ; case Number : goto LABEL_369 ; case Number : goto LABEL_317 ; case Number : goto LABEL_357 ; case Number : goto LABEL_344 ; case Number : goto LABEL_356 ; default : return Number L ; } } if ( v11 <= Number ) { if ( v11 >= Number ) { switch ( v11 ) { case Number : goto LABEL_139 ; case Number : case Number : goto LABEL_271 ; case Number : goto LABEL_369 ; case Number : goto LABEL_258 ; case Number : goto LABEL_245 ; case Number : LABEL_89 : v42 = ( unsigned __int16 ) @@a2@@ >> Number ; v48 = HIWORD ( @@a2@@ ) & Number ; gen_op_iwmmxt_movq_M0_wRn ( @@a2@@ & Number ) ; if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_maddsq_M0_wRn ( v48 ) ; else gen_op_iwmmxt_madduq_M0_wRn ( v48 ) ; goto LABEL_124 ; case Number : goto LABEL_330 ; case Number : goto LABEL_357 ; case Number : goto LABEL_344 ; case Number : goto LABEL_356 ; default : return Number L ; } } if ( v11 <= Number ) { if ( v11 >= Number ) { switch ( v11 ) { case Number : goto LABEL_132 ; case Number : goto LABEL_139 ; case Number : goto LABEL_222 ; case Number : case Number : goto LABEL_292 ; case Number : goto LABEL_232 ; case Number : goto LABEL_150 ; case Number : goto LABEL_369 ; case Number : goto LABEL_99 ; case Number : goto LABEL_92 ; case Number : goto LABEL_183 ; case Number : goto LABEL_206 ; case Number : goto LABEL_317 ; case Number : goto LABEL_164 ; case Number : goto LABEL_357 ; case Number : goto LABEL_344 ; case Number : goto LABEL_356 ; default : return Number L ; } } if ( v11 <= Number ) { if ( v11 >= Number ) { switch ( v11 ) { case Number : goto LABEL_132 ; case Number : goto LABEL_139 ; case Number : case Number : goto LABEL_282 ; case Number : goto LABEL_125 ; case Number : goto LABEL_369 ; case Number : goto LABEL_258 ; case Number : goto LABEL_245 ; case Number : goto LABEL_89 ; case Number : goto LABEL_330 ; case Number : goto LABEL_357 ; case Number : goto LABEL_344 ; case Number : goto LABEL_199 ; case Number : goto LABEL_356 ; default : return Number L ; } } if ( v11 <= Number ) { if ( v11 >= Number ) { switch ( v11 ) { case Number : LABEL_343 : gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v80 = tcg_const_i32 ( ( @@a2@@ >> Number ) & Number ) ; iwmmxt_load_reg ( cpu_V1 , @@a2@@ & Number ) ; gen_helper_iwmmxt_align ( cpu_M0 , cpu_M0 , cpu_V1 , v80 ) ; tcg_temp_free_i32 ( v80 ) ; gen_op_iwmmxt_movq_wRn_M0 ( ( unsigned __int16 ) @@a2@@ >> Number ) ; gen_op_iwmmxt_set_mup ( ) ; return Number L ; case Number : case Number : goto LABEL_302 ; case Number : goto LABEL_232 ; case Number : goto LABEL_369 ; case Number : LABEL_119 : v42 = ( unsigned __int16 ) @@a2@@ >> Number ; v53 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_macsw_M0_wRn ( v53 ) ; else gen_op_iwmmxt_macuw_M0_wRn ( v53 ) ; if ( ( @@a2@@ & Number ) == Number ) { iwmmxt_load_reg ( cpu_V1 , v42 ) ; tcg_gen_add_i64 ( cpu_M0 , cpu_M0 , cpu_V1 ) ; } goto LABEL_124 ; case Number : goto LABEL_317 ; case Number : goto LABEL_357 ; case Number : goto LABEL_344 ; case Number : goto LABEL_356 ; default : return Number L ; } } if ( v11 <= Number ) { if ( v11 >= Number ) { switch ( v11 ) { case Number : case Number : case Number : case Number : if ( ( unsigned __int8 ) @@a2@@ >> Number == Number ) return Number L ; v44 = HIWORD ( @@a2@@ ) & Number ; v74 = load_reg ( @@a1@@ , ( unsigned __int16 ) @@a2@@ >> Number ) ; gen_op_iwmmxt_movq_M0_wRn ( v44 ) ; v15 = ( unsigned __int8 ) @@a2@@ >> Number ; if ( v15 == Number ) { v84 = tcg_const_i32 ( Number ) ; @@v87@@ = tcg_const_i32 ( ( Number * ( _BYTE ) @@a2@@ ) & Number ) ; } else if ( v15 > Number ) { v84 = Number L ; @@v87@@ = Number L ; } else if ( ( unsigned __int8 ) @@a2@@ >> Number ) { v84 = tcg_const_i32 ( Number ) ; @@v87@@ = tcg_const_i32 ( ( Number * ( _BYTE ) @@a2@@ ) & Number ) ; } else { v84 = tcg_const_i32 ( Number L ) ; @@v87@@ = tcg_const_i32 ( ( Number * ( _BYTE ) @@a2@@ ) & Number ) ; } gen_helper_iwmmxt_insr ( cpu_M0 , cpu_M0 , v74 , v84 , @@v87@@ ) ; tcg_temp_free_i32 ( @@v87@@ ) ; tcg_temp_free_i32 ( v84 ) ; tcg_temp_free_i32 ( v74 ) ; gen_op_iwmmxt_movq_wRn_M0 ( v44 ) ; gen_op_iwmmxt_set_mup ( ) ; break ; case Number : goto LABEL_343 ; case Number : case Number : goto LABEL_271 ; case Number : goto LABEL_369 ; case Number : goto LABEL_258 ; case Number : goto LABEL_245 ; case Number : goto LABEL_119 ; case Number : goto LABEL_330 ; case Number : goto LABEL_357 ; case Number : goto LABEL_344 ; case Number : goto LABEL_356 ; default : return Number L ; } return Number L ; } if ( v11 <= Number ) { if ( v11 >= Number ) { switch ( v11 ) { case Number : case Number : case Number : case Number : if ( ( unsigned __int8 ) @@a2@@ >> Number == Number ) return Number L ; v77 = load_reg ( @@a1@@ , ( unsigned __int16 ) @@a2@@ >> Number ) ; v18 = ( unsigned __int8 ) @@a2@@ >> Number ; if ( v18 == Number ) { gen_helper_iwmmxt_bcstl ( cpu_M0 , v77 ) ; } else if ( v18 <= Number ) { if ( ( unsigned __int8 ) @@a2@@ >> Number ) gen_helper_iwmmxt_bcstw ( cpu_M0 , v77 ) ; else gen_helper_iwmmxt_bcstb ( cpu_M0 , v77 ) ; } tcg_temp_free_i32 ( v77 ) ; gen_op_iwmmxt_movq_wRn_M0 ( HIWORD ( @@a2@@ ) & Number ) ; gen_op_iwmmxt_set_mup ( ) ; break ; case Number : case Number : goto LABEL_343 ; case Number : case Number : goto LABEL_282 ; case Number : goto LABEL_125 ; case Number : case Number : goto LABEL_369 ; case Number : goto LABEL_258 ; case Number : goto LABEL_245 ; case Number : case Number : goto LABEL_119 ; case Number : case Number : LABEL_106 : v42 = ( unsigned __int16 ) @@a2@@ >> Number ; v51 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_sadw_M0_wRn ( v51 ) ; else gen_op_iwmmxt_sadb_M0_wRn ( v51 ) ; if ( ( @@a2@@ & Number ) == Number ) gen_op_iwmmxt_addl_M0_wRn ( v42 ) ; goto LABEL_124 ; case Number : goto LABEL_330 ; case Number : case Number : goto LABEL_357 ; case Number : case Number : goto LABEL_344 ; case Number : goto LABEL_199 ; case Number : case Number : goto LABEL_356 ; case Number : goto LABEL_222 ; case Number : case Number : goto LABEL_292 ; case Number : goto LABEL_232 ; case Number : goto LABEL_150 ; case Number : goto LABEL_99 ; case Number : goto LABEL_92 ; case Number : goto LABEL_183 ; case Number : goto LABEL_206 ; case Number : goto LABEL_317 ; case Number : goto LABEL_164 ; default : return Number L ; } return Number L ; } if ( v11 <= Number ) { switch ( v11 ) { case Number : gen_op_iwmmxt_movq_M0_wRn ( @@a2@@ & Number ) ; gen_op_iwmmxt_orq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; gen_op_iwmmxt_setpsr_nz ( ) ; gen_op_iwmmxt_movq_wRn_M0 ( ( unsigned __int16 ) @@a2@@ >> Number ) ; gen_op_iwmmxt_set_mup ( ) ; gen_op_iwmmxt_set_cup ( ) ; return Number L ; case Number : case Number : goto LABEL_343 ; case Number : case Number : goto LABEL_282 ; case Number : goto LABEL_125 ; case Number : case Number : goto LABEL_369 ; case Number : goto LABEL_258 ; case Number : goto LABEL_245 ; case Number : case Number : goto LABEL_112 ; case Number : if ( ( @@a2@@ & Number ) == Number ) { v63 = ( unsigned __int16 ) @@a2@@ >> Number ; v41 = HIWORD ( @@a2@@ ) & Number ; switch ( v41 ) { case Number : case Number : return Number L ; case Number : gen_op_iwmmxt_set_cup ( ) ; goto LABEL_80 ; case Number : LABEL_80 : v70 = iwmmxt_load_creg ( v41 ) ; v83 = load_reg ( @@a1@@ , v63 ) ; tcg_gen_andc_i32 ( v70 , v70 , v83 ) ; tcg_temp_free_i32 ( v83 ) ; iwmmxt_store_creg ( v41 , v70 ) ; return Number L ; case Number : case Number : case Number : case Number : gen_op_iwmmxt_set_cup ( ) ; v71 = load_reg ( @@a1@@ , v63 ) ; iwmmxt_store_creg ( v41 , v71 ) ; return Number L ; default : return Number L ; } } return Number L ; case Number : case Number : goto LABEL_106 ; case Number : goto LABEL_330 ; case Number : case Number : goto LABEL_357 ; case Number : case Number : goto LABEL_344 ; case Number : goto LABEL_199 ; case Number : case Number : goto LABEL_356 ; case Number : gen_op_iwmmxt_movq_M0_wRn ( @@a2@@ & Number ) ; gen_op_iwmmxt_xorq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; gen_op_iwmmxt_setpsr_nz ( ) ; gen_op_iwmmxt_movq_wRn_M0 ( ( unsigned __int16 ) @@a2@@ >> Number ) ; gen_op_iwmmxt_set_mup ( ) ; gen_op_iwmmxt_set_cup ( ) ; return Number L ; case Number : goto LABEL_222 ; case Number : case Number : goto LABEL_292 ; case Number : goto LABEL_232 ; case Number : goto LABEL_150 ; case Number : goto LABEL_99 ; case Number : goto LABEL_92 ; case Number : if ( ( @@a2@@ & Number ) != Number ) return Number L ; v72 = iwmmxt_load_creg ( HIWORD ( @@a2@@ ) & Number ) ; store_reg ( @@a1@@ , ( unsigned __int16 ) @@a2@@ >> Number , v72 ) ; break ; case Number : goto LABEL_183 ; case Number : goto LABEL_206 ; case Number : goto LABEL_317 ; case Number : goto LABEL_164 ; default : return Number L ; } return Number L ; } if ( v11 <= Number && v11 >= Number ) { switch ( v11 ) { case Number : gen_op_iwmmxt_movq_M0_wRn ( @@a2@@ & Number ) ; gen_op_iwmmxt_andq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; gen_op_iwmmxt_setpsr_nz ( ) ; gen_op_iwmmxt_movq_wRn_M0 ( ( unsigned __int16 ) @@a2@@ >> Number ) ; gen_op_iwmmxt_set_mup ( ) ; gen_op_iwmmxt_set_cup ( ) ; return Number L ; case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : v46 = ( @@a2@@ >> Number ) & Number ; @@v47@@ = ( unsigned __int16 ) @@a2@@ >> Number ; v62 = @@a2@@ & Number ; if ( @@v47@@ == Number || v62 == Number ) return Number L ; gen_op_iwmmxt_movq_M0_wRn ( v46 ) ; v82 = load_reg ( @@a1@@ , @@v47@@ ) ; v86 = load_reg ( @@a1@@ , v62 ) ; v33 = HIWORD ( @@a2@@ ) & Number ; if ( v33 >= Number ) { if ( ( @@a2@@ & Number ) != Number ) tcg_gen_shri_i32 ( v82 , v82 , Number L ) ; if ( ( @@a2@@ & Number ) != Number ) tcg_gen_shri_i32 ( v86 , v86 , Number L ) ; gen_helper_iwmmxt_muladdswl ( cpu_M0 , cpu_M0 , v82 , v86 ) ; } else if ( v33 ) { if ( v33 != Number ) { tcg_temp_free_i32 ( v86 ) ; tcg_temp_free_i32 ( v82 ) ; return Number L ; } gen_helper_iwmmxt_muladdsw ( cpu_M0 , cpu_M0 , v82 , v86 ) ; } else { gen_helper_iwmmxt_muladdsl ( cpu_M0 , cpu_M0 , v82 , v86 ) ; } tcg_temp_free_i32 ( v86 ) ; tcg_temp_free_i32 ( v82 ) ; gen_op_iwmmxt_movq_wRn_M0 ( v46 ) ; gen_op_iwmmxt_set_mup ( ) ; break ; case Number : case Number : goto LABEL_343 ; case Number : case Number : goto LABEL_271 ; case Number : case Number : goto LABEL_369 ; case Number : goto LABEL_258 ; case Number : goto LABEL_245 ; case Number : case Number : LABEL_112 : v42 = ( unsigned __int16 ) @@a2@@ >> Number ; v52 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_mulshw_M0_wRn ( v52 ) ; else gen_op_iwmmxt_mulslw_M0_wRn ( v52 ) ; } else if ( ( @@a2@@ & Number ) != Number ) { gen_op_iwmmxt_muluhw_M0_wRn ( v52 ) ; } else { gen_op_iwmmxt_mululw_M0_wRn ( v52 ) ; } goto LABEL_124 ; case Number : goto LABEL_330 ; case Number : case Number : goto LABEL_357 ; case Number : case Number : goto LABEL_344 ; case Number : case Number : goto LABEL_356 ; case Number : gen_op_iwmmxt_movq_M0_wRn ( @@a2@@ & Number ) ; tcg_gen_neg_i64 ( cpu_M0 , cpu_M0 ) ; gen_op_iwmmxt_andq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; gen_op_iwmmxt_setpsr_nz ( ) ; gen_op_iwmmxt_movq_wRn_M0 ( ( unsigned __int16 ) @@a2@@ >> Number ) ; gen_op_iwmmxt_set_mup ( ) ; gen_op_iwmmxt_set_cup ( ) ; return Number L ; case Number : case Number : goto LABEL_302 ; case Number : goto LABEL_232 ; case Number : goto LABEL_317 ; default : return Number L ; } return Number L ; } } } } } } } } return Number L ; } switch ( v11 ) { case Number : goto LABEL_132 ; case Number : case Number : LABEL_282 : if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) return Number L ; v45 = ( unsigned __int16 ) @@a2@@ >> Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v79 = tcg_temp_new_i32 ( ) ; if ( ( unsigned int ) gen_iwmmxt_shift ( @@a2@@ , Number , v79 ) ) goto LABEL_314 ; v27 = ( @@a2@@ >> Number ) & Number ; switch ( v27 ) { case Number : gen_helper_iwmmxt_sraq ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; break ; case Number : gen_helper_iwmmxt_sraw ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; break ; case Number : gen_helper_iwmmxt_sral ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; break ; } goto LABEL_316 ; case Number : LABEL_125 : v43 = ( unsigned __int16 ) @@a2@@ >> Number ; v54 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v14 = ( @@a2@@ >> Number ) & Number ; if ( v14 == Number ) return Number L ; if ( v14 == Number ) { gen_op_iwmmxt_cmpeql_M0_wRn ( v54 ) ; } else if ( v14 ) { gen_op_iwmmxt_cmpeqw_M0_wRn ( v54 ) ; } else { gen_op_iwmmxt_cmpeqb_M0_wRn ( v54 ) ; } goto LABEL_385 ; case Number : goto LABEL_369 ; case Number : goto LABEL_258 ; case Number : goto LABEL_245 ; case Number : goto LABEL_330 ; case Number : goto LABEL_357 ; case Number : goto LABEL_344 ; case Number : LABEL_199 : v42 = ( unsigned __int16 ) @@a2@@ >> Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v20 = ( @@a2@@ >> Number ) & Number ; if ( v20 == Number ) return Number L ; if ( v20 == Number ) { gen_helper_iwmmxt_addcl ( cpu_M0 , cpu_M0 ) ; } else if ( v20 ) { gen_helper_iwmmxt_addcw ( cpu_M0 , cpu_M0 ) ; } else { gen_helper_iwmmxt_addcb ( cpu_M0 , cpu_M0 ) ; } break ; case Number : goto LABEL_356 ; default : return Number L ; } } LABEL_124 : gen_op_iwmmxt_movq_wRn_M0 ( v42 ) ; gen_op_iwmmxt_set_mup ( ) ; return Number L ; } switch ( v11 ) { case Number : case Number : LABEL_302 : if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) return Number L ; v45 = ( unsigned __int16 ) @@a2@@ >> Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v79 = tcg_temp_new_i32 ( ) ; v29 = ( @@a2@@ >> Number ) & Number ; switch ( v29 ) { case Number : if ( ! ( unsigned int ) gen_iwmmxt_shift ( @@a2@@ , Number , v79 ) ) { gen_helper_iwmmxt_rorq ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; goto LABEL_316 ; } break ; case Number : if ( ! ( unsigned int ) gen_iwmmxt_shift ( @@a2@@ , Number , v79 ) ) { gen_helper_iwmmxt_rorw ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; LABEL_316 : tcg_temp_free_i32 ( v79 ) ; gen_op_iwmmxt_movq_wRn_M0 ( v45 ) ; gen_op_iwmmxt_set_mup ( ) ; gen_op_iwmmxt_set_cup ( ) ; return Number L ; } break ; case Number : if ( ! ( unsigned int ) gen_iwmmxt_shift ( @@a2@@ , Number , v79 ) ) { gen_helper_iwmmxt_rorl ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; goto LABEL_316 ; } break ; default : goto LABEL_316 ; } LABEL_314 : tcg_temp_free_i32 ( v79 ) ; return Number L ; case Number : LABEL_232 : v43 = ( unsigned __int16 ) @@a2@@ >> Number ; v56 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v23 = ( @@a2@@ >> Number ) & Number ; if ( v23 == Number ) return Number L ; if ( v23 == Number ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_cmpgtsl_M0_wRn ( v56 ) ; else gen_op_iwmmxt_cmpgtul_M0_wRn ( v56 ) ; } else if ( v23 ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_cmpgtsw_M0_wRn ( v56 ) ; else gen_op_iwmmxt_cmpgtuw_M0_wRn ( v56 ) ; } else if ( ( @@a2@@ & Number ) != Number ) { gen_op_iwmmxt_cmpgtsb_M0_wRn ( v56 ) ; } else { gen_op_iwmmxt_cmpgtub_M0_wRn ( v56 ) ; } goto LABEL_385 ; case Number : LABEL_369 : if ( ( @@a2@@ & Number ) == Number || ( ( @@a2@@ >> Number ) & Number ) == Number ) return Number L ; v43 = ( unsigned __int16 ) @@a2@@ >> Number ; v61 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v32 = ( @@a2@@ >> Number ) & Number ; switch ( v32 ) { case Number : if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_packsq_M0_wRn ( v61 ) ; else gen_op_iwmmxt_packuq_M0_wRn ( v61 ) ; break ; case Number : if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_packsw_M0_wRn ( v61 ) ; else gen_op_iwmmxt_packuw_M0_wRn ( v61 ) ; break ; case Number : if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_packsl_M0_wRn ( v61 ) ; else gen_op_iwmmxt_packul_M0_wRn ( v61 ) ; break ; } LABEL_385 : gen_op_iwmmxt_movq_wRn_M0 ( v43 ) ; gen_op_iwmmxt_set_mup ( ) ; gen_op_iwmmxt_set_cup ( ) ; return Number L ; case Number : LABEL_317 : v42 = ( unsigned __int16 ) @@a2@@ >> Number ; v57 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v30 = ( @@a2@@ >> Number ) & Number ; if ( v30 == Number ) return Number L ; if ( v30 == Number ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_minsl_M0_wRn ( v57 ) ; else gen_op_iwmmxt_minul_M0_wRn ( v57 ) ; } else if ( v30 ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_minsw_M0_wRn ( v57 ) ; else gen_op_iwmmxt_minuw_M0_wRn ( v57 ) ; } else if ( ( @@a2@@ & Number ) != Number ) { gen_op_iwmmxt_minsb_M0_wRn ( v57 ) ; } else { gen_op_iwmmxt_minub_M0_wRn ( v57 ) ; } goto LABEL_124 ; case Number : LABEL_357 : v43 = ( unsigned __int16 ) @@a2@@ >> Number ; v60 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; switch ( ( @@a2@@ >> Number ) & Number ) { case Number : gen_op_iwmmxt_addnb_M0_wRn ( v60 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_addub_M0_wRn ( v60 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_addsb_M0_wRn ( v60 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_addnw_M0_wRn ( v60 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_adduw_M0_wRn ( v60 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_addsw_M0_wRn ( v60 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_addnl_M0_wRn ( v60 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_addul_M0_wRn ( v60 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_addsl_M0_wRn ( v60 ) ; goto LABEL_385 ; default : result = Number L ; break ; } return result ; case Number : LABEL_344 : v43 = ( unsigned __int16 ) @@a2@@ >> Number ; v59 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; switch ( ( @@a2@@ >> Number ) & Number ) { case Number : gen_op_iwmmxt_subnb_M0_wRn ( v59 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_subub_M0_wRn ( v59 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_subsb_M0_wRn ( v59 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_subnw_M0_wRn ( v59 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_subuw_M0_wRn ( v59 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_subsw_M0_wRn ( v59 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_subnl_M0_wRn ( v59 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_subul_M0_wRn ( v59 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_subsl_M0_wRn ( v59 ) ; goto LABEL_385 ; default : result = Number L ; break ; } return result ; case Number : LABEL_356 : gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v81 = tcg_const_i32 ( HIWORD ( @@a2@@ ) & Number | @@a2@@ & Number ) ; gen_helper_iwmmxt_shufh ( cpu_M0 , cpu_env , cpu_M0 , v81 ) ; tcg_temp_free_i32 ( v81 ) ; gen_op_iwmmxt_movq_wRn_M0 ( ( unsigned __int16 ) @@a2@@ >> Number ) ; gen_op_iwmmxt_set_mup ( ) ; gen_op_iwmmxt_set_cup ( ) ; return Number L ; default : return Number L ; } } if ( ( @@a2@@ & Number ) == Number ) { v39 = @@a2@@ & Number ; @@v65@@ = HIWORD ( @@a2@@ ) & Number ; if ( ( @@a2@@ & Number ) != Number ) { iwmmxt_load_reg ( cpu_V0 , v39 ) ; tcg_gen_extrl_i64_i32 ( cpu_R [ ( unsigned __int16 ) @@a2@@ >> Number ] , cpu_V0 ) ; tcg_gen_extrh_i64_i32 ( cpu_R [ @@v65@@ ] , cpu_V0 ) ; } else { tcg_gen_concat_i32_i64 ( cpu_V0 , cpu_R [ ( unsigned __int16 ) @@a2@@ >> Number ] , cpu_R [ @@v65@@ ] ) ; iwmmxt_store_reg ( cpu_V0 , v39 ) ; gen_op_iwmmxt_set_mup ( ) ; } result = Number L ; } else { v40 = ( unsigned __int16 ) @@a2@@ >> Number ; @@v88@@ = tcg_temp_new_i32 ( ) ; if ( gen_iwmmxt_address ( @@a1@@ , @@a2@@ , @@v88@@ ) ) { tcg_temp_free_i32 ( @@v88@@ ) ; result = Number L ; } else { if ( ( @@a2@@ & Number ) != Number ) { if ( @@a2@@ >> Number == Number ) { v67 = tcg_temp_new_i32 ( ) ; v3 = get_mem_index ( @@a1@@ ) ; gen_aa32_ld32u ( @@a1@@ , v67 , @@v88@@ , v3 ) ; iwmmxt_store_creg ( v40 , v67 ) ; } else { v34 = Number ; if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) != Number ) { v4 = get_mem_index ( @@a1@@ ) ; gen_aa32_ld64 ( @@a1@@ , cpu_M0 , @@v88@@ , v4 ) ; v34 = Number ; } else { v66 = tcg_temp_new_i32 ( ) ; v5 = get_mem_index ( @@a1@@ ) ; gen_aa32_ld32u ( @@a1@@ , v66 , @@v88@@ , v5 ) ; } } else { v66 = tcg_temp_new_i32 ( ) ; v6 = get_mem_index ( @@a1@@ ) ; if ( ( @@a2@@ & Number ) != Number ) gen_aa32_ld16u ( @@a1@@ , v66 , @@v88@@ , v6 ) ; else gen_aa32_ld8u ( @@a1@@ , v66 , @@v88@@ , v6 ) ; } if ( v34 ) { tcg_gen_extu_i32_i64 ( cpu_M0 , v66 ) ; tcg_temp_free_i32 ( v66 ) ; } gen_op_iwmmxt_movq_wRn_M0 ( v40 ) ; } } else if ( @@a2@@ >> Number == Number ) { v68 = iwmmxt_load_creg ( v40 ) ; v7 = get_mem_index ( @@a1@@ ) ; gen_aa32_st32 ( @@a1@@ , v68 , @@v88@@ , v7 ) ; tcg_temp_free_i32 ( v68 ) ; } else { gen_op_iwmmxt_movq_M0_wRn ( v40 ) ; v69 = tcg_temp_new_i32 ( ) ; if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) != Number ) { v8 = get_mem_index ( @@a1@@ ) ; gen_aa32_st64 ( @@a1@@ , cpu_M0 , @@v88@@ , v8 ) ; } else { tcg_gen_extrl_i64_i32 ( v69 , cpu_M0 ) ; v9 = get_mem_index ( @@a1@@ ) ; gen_aa32_st32 ( @@a1@@ , v69 , @@v88@@ , v9 ) ; } } else { tcg_gen_extrl_i64_i32 ( v69 , cpu_M0 ) ; v10 = get_mem_index ( @@a1@@ ) ; if ( ( @@a2@@ & Number ) != Number ) gen_aa32_st16 ( @@a1@@ , v69 , @@v88@@ , v10 ) ; else gen_aa32_st8 ( @@a1@@ , v69 , @@v88@@ , v10 ) ; } tcg_temp_free_i32 ( v69 ) ; } tcg_temp_free_i32 ( @@v88@@ ) ; result = Number L ; } } return result ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "v87", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v65", "t": {"T": 1, "n": "int", "s": 4}, "location": "s36"}, {"n": "v47", "t": {"T": 1, "n": "int", "s": 4}, "location": "s52"}, {"n": "v88", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "insn", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r64"}, {"n": "tmp3", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "rdhi", "t": {"T": 1, "n": "int", "s": 4}, "location": "s36"}, {"n": "rd0", "t": {"T": 1, "n": "int", "s": 4}, "location": "s52"}, {"n": "addr", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 938 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_align\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_align ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_align , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_insr\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_insr ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ ) { __int64 @@v5@@ ; __int64 @@v10@@ [ Number ] ; unsigned __int64 @@v11@@ ; @@v11@@ = __readfsqword ( Number ) ; @@v10@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v10@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v10@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v10@@ [ Number ] = tcgv_i32_temp ( @@a5@@ ) ; @@v5@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_insr , @@v5@@ , Number L , @@v10@@ ) ; return __readfsqword ( Number ) ^ @@v11@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r72\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v10\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_bcstb\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_bcstb ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i32_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_bcstb , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_bcstw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_bcstw ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i32_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_bcstw , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_bcstl\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_bcstl ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i32_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_bcstl , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_addcb\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_addcb ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i64_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_addcb , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_addcw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_addcw ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i64_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_addcw , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_addcl\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_addcl ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i64_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_addcl , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_msbb\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_msbb ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i64_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_msbb , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_msbw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_msbw ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i64_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_msbw , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_msbl\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_msbl ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i64_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_msbl , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_srlw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_srlw ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_srlw , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_srll\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_srll ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_srll , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_srlq\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_srlq ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_srlq , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_sllw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_sllw ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_sllw , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_slll\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_slll ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_slll , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_sllq\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_sllq ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_sllq , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_sraw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_sraw ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_sraw , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_sral\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_sral ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_sral , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_sraq\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_sraq ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_sraq , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_rorw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_rorw ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_rorw , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_rorl\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_rorl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_rorl , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_rorq\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_rorq ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_rorq , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_shufh\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_shufh ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_shufh , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_muladdsl\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_muladdsl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_muladdsl , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_muladdsw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_muladdsw ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_muladdsw , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_muladdswl\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_muladdswl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_muladdswl , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_mov_i32\", \"code\": \"__int64 __fastcall tcg_gen_mov_i32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@result@@ ; @@result@@ = @@a1@@ ; if ( @@a1@@ != @@a2@@ ) @@result@@ = tcg_gen_op2_i32 ( Number , @@a1@@ , @@a2@@ ) ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_gen_and_i32\", \"code\": \"__int64 __fastcall tcg_gen_and_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_or_i32\", \"code\": \"__int64 __fastcall tcg_gen_or_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_add_i64\", \"code\": \"__int64 __fastcall tcg_gen_add_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_neg_i64\", \"code\": \"__int64 __fastcall tcg_gen_neg_i64 ( __int64 @@a1@@ , __int64 @@a2@@ ) { return tcg_gen_op2_i64 ( Number , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"get_mem_index\", \"code\": \"__int64 __fastcall get_mem_index ( __int64 @@a1@@ ) { return arm_to_core_mmu_idx ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_set_cpsr\", \"code\": \"__int64 __fastcall gen_set_cpsr ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_const_i32 ( @@a2@@ ) ; gen_helper_cpsr_write ( cpu_env , @@a1@@ , @@v3@@ ) ; return tcg_temp_free_i32 ( @@v3@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_shl\", \"code\": \"__int64 __fastcall gen_shl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shl_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_shr\", \"code\": \"__int64 __fastcall gen_shr ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shr_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_aa32_ld64\", \"code\": \"__int64 __fastcall gen_aa32_ld64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { return gen_aa32_ld_i64 ( @@a1@@ , @@a2@@ , @@a3@@ , @@a4@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_aa32_st64\", \"code\": \"__int64 __fastcall gen_aa32_st64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { return gen_aa32_st_i64 ( @@a1@@ , @@a2@@ , @@a3@@ , @@a4@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_aa32_ld8u\", \"code\": \"__int64 __fastcall gen_aa32_ld8u ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { return gen_aa32_ld_i32 ( @@a1@@ , @@a2@@ , @@a3@@ , @@a4@@ , * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_aa32_ld16u\", \"code\": \"__int64 __fastcall gen_aa32_ld16u ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { return gen_aa32_ld_i32 ( @@a1@@ , @@a2@@ , @@a3@@ , @@a4@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_aa32_ld32u\", \"code\": \"__int64 __fastcall gen_aa32_ld32u ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { return gen_aa32_ld_i32 ( @@a1@@ , @@a2@@ , @@a3@@ , @@a4@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_aa32_st8\", \"code\": \"__int64 __fastcall gen_aa32_st8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { return gen_aa32_st_i32 ( @@a1@@ , @@a2@@ , @@a3@@ , @@a4@@ , * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_aa32_st16\", \"code\": \"__int64 __fastcall gen_aa32_st16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { return gen_aa32_st_i32 ( @@a1@@ , @@a2@@ , @@a3@@ , @@a4@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_aa32_st32\", \"code\": \"__int64 __fastcall gen_aa32_st32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { return gen_aa32_st_i32 ( @@a1@@ , @@a2@@ , @@a3@@ , @@a4@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"iwmmxt_store_reg\", \"code\": \"__int64 __fastcall iwmmxt_store_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_st_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"iwmmxt_load_creg\", \"code\": \"__int64 __fastcall iwmmxt_load_creg ( int @@a1@@ ) { __int64 @@v2@@ ; @@v2@@ = tcg_temp_new_i32 ( ) ; tcg_gen_ld_i32 ( @@v2@@ , cpu_env , Number * ( @@a1@@ + Number L ) ) ; return @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_store_creg\", \"code\": \"__int64 __fastcall iwmmxt_store_creg ( int @@a1@@ , __int64 @@a2@@ ) { tcg_gen_st_i32 ( @@a2@@ , cpu_env , Number * ( @@a1@@ + Number L ) ) ; return tcg_temp_free_i32 ( @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_op_iwmmxt_movq_wRn_M0\", \"code\": \"__int64 __fastcall gen_op_iwmmxt_movq_wRn_M0 ( int @@a1@@ ) { return iwmmxt_store_reg ( cpu_M0 , @@a1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_movq_M0_wRn\", \"code\": \"__int64 __fastcall gen_op_iwmmxt_movq_M0_wRn ( int @@a1@@ ) { return iwmmxt_load_reg ( cpu_M0 , @@a1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_orq_M0_wRn\", \"code\": \"__int64 __fastcall gen_op_iwmmxt_orq_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return tcg_gen_or_i64 ( cpu_M0 , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_andq_M0_wRn\", \"code\": \"__int64 __fastcall gen_op_iwmmxt_andq_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return tcg_gen_and_i64 ( cpu_M0 , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_xorq_M0_wRn\", \"code\": \"__int64 __fastcall gen_op_iwmmxt_xorq_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return tcg_gen_xor_i64 ( cpu_M0 , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_maddsq_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_maddsq_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_maddsq ( cpu_M0 , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_madduq_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_madduq_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_madduq ( cpu_M0 , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_sadb_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_sadb_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_sadb ( cpu_M0 , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_sadw_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_sadw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_sadw ( cpu_M0 , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_mulslw_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_mulslw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_mulslw ( cpu_M0 , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_mulshw_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_mulshw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_mulshw ( cpu_M0 , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_mululw_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_mululw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_mululw ( cpu_M0 , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_muluhw_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_muluhw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_muluhw ( cpu_M0 , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_macsw_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_macsw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_macsw ( cpu_M0 , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_macuw_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_macuw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_macuw ( cpu_M0 , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_unpacklb_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_unpacklb_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_unpacklb ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_unpacklw_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_unpacklw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_unpacklw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_unpackll_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_unpackll_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_unpackll ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_unpackhb_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_unpackhb_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_unpackhb ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_unpackhw_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_unpackhw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_unpackhw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_unpackhl_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_unpackhl_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_unpackhl ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_cmpeqb_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_cmpeqb_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_cmpeqb ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_cmpeqw_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_cmpeqw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_cmpeqw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_cmpeql_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_cmpeql_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_cmpeql ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_cmpgtub_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_cmpgtub_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_cmpgtub ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_cmpgtuw_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_cmpgtuw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_cmpgtuw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_cmpgtul_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_cmpgtul_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_cmpgtul ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_cmpgtsb_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_cmpgtsb_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_cmpgtsb ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_cmpgtsw_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_cmpgtsw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_cmpgtsw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_cmpgtsl_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_cmpgtsl_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_cmpgtsl ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_minsb_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_minsb_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_minsb ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_minsw_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_minsw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_minsw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_minsl_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_minsl_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_minsl ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_minub_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_minub_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_minub ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_minuw_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_minuw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_minuw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_minul_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_minul_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_minul ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_maxsb_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_maxsb_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_maxsb ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_maxsw_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_maxsw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_maxsw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_maxsl_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_maxsl_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_maxsl ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_maxub_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_maxub_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_maxub ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_maxuw_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_maxuw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_maxuw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_maxul_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_maxul_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_maxul ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_subnb_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_subnb_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_subnb ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_subnw_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_subnw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_subnw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_subnl_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_subnl_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_subnl ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_addnb_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_addnb_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_addnb ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_addnw_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_addnw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_addnw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_addnl_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_addnl_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_addnl ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_subub_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_subub_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_subub ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_subuw_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_subuw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_subuw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_subul_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_subul_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_subul ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_addub_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_addub_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_addub ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_adduw_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_adduw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_adduw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_addul_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_addul_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_addul ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_subsb_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_subsb_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_subsb ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_subsw_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_subsw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_subsw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_subsl_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_subsl_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_subsl ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_addsb_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_addsb_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_addsb ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_addsw_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_addsw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_addsw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_addsl_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_addsl_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_addsl ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_avgb0_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_avgb0_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_avgb0 ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_avgb1_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_avgb1_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_avgb1 ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_avgw0_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_avgw0_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_avgw0 ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_avgw1_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_avgw1_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_avgw1 ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_packuw_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_packuw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_packuw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_packul_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_packul_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_packul ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_packuq_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_packuq_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_packuq ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_packsw_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_packsw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_packsw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_packsl_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_packsl_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_packsl ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_packsq_M0_wRn\", \"code\": \"unsigned __int64 __fastcall gen_op_iwmmxt_packsq_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_packsq ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_op_iwmmxt_set_mup\", \"code\": \"__int64 gen_op_iwmmxt_set_mup ( ) { __int64 @@v1@@ ; @@v1@@ = load_cpu_offset ( Number ) ; tcg_gen_ori_i32 ( @@v1@@ , @@v1@@ , Number L ) ; return store_cpu_offset ( @@v1@@ , Number ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_iwmmxt_set_cup\", \"code\": \"__int64 gen_op_iwmmxt_set_cup ( ) { __int64 @@v1@@ ; @@v1@@ = load_cpu_offset ( Number ) ; tcg_gen_ori_i32 ( @@v1@@ , @@v1@@ , Number L ) ; return store_cpu_offset ( @@v1@@ , Number ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_iwmmxt_setpsr_nz\", \"code\": \"__int64 gen_op_iwmmxt_setpsr_nz ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_i32 ( ) ; gen_helper_iwmmxt_setpsr_nz ( @@v1@@ , cpu_M0 ) ; return store_cpu_offset ( @@v1@@ , Number ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_op_iwmmxt_addl_M0_wRn\", \"code\": \"__int64 __fastcall gen_op_iwmmxt_addl_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; tcg_gen_ext32u_i64 ( cpu_V1 , cpu_V1 ) ; return tcg_gen_add_i64 ( cpu_M0 , cpu_M0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_iwmmxt_address\", \"code\": \"_BOOL8 __fastcall gen_iwmmxt_address ( __int64 @@a1@@ , unsigned int @@a2@@ , __int64 @@a3@@ ) { unsigned int @@v5@@ ; __int64 @@v6@@ ; @@v6@@ = load_reg ( @@a1@@ , HIWORD ( @@a2@@ ) & Number ) ; @@v5@@ = ( unsigned __int8 ) @@a2@@ << ( ( @@a2@@ >> Number ) & Number ) ; if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) != Number ) tcg_gen_addi_i32 ( @@v6@@ , @@v6@@ , @@v5@@ ) ; else tcg_gen_addi_i32 ( @@v6@@ , @@v6@@ , - @@v5@@ ) ; tcg_gen_mov_i32 ( @@a3@@ , @@v6@@ ) ; if ( ( @@a2@@ & Number ) == Number ) { tcg_temp_free_i32 ( @@v6@@ ) ; return Number L ; } goto LABEL_6 ; } if ( ( @@a2@@ & Number ) != Number ) { tcg_gen_mov_i32 ( @@a3@@ , @@v6@@ ) ; if ( ( @@a2@@ & Number ) != Number ) tcg_gen_addi_i32 ( @@v6@@ , @@v6@@ , @@v5@@ ) ; else tcg_gen_addi_i32 ( @@v6@@ , @@v6@@ , - @@v5@@ ) ; LABEL_6 : store_reg ( @@a1@@ , HIWORD ( @@a2@@ ) & Number , @@v6@@ ) ; return Number L ; } return ( @@a2@@ & Number ) == Number ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_iwmmxt_shift\", \"code\": \"__int64 __fastcall gen_iwmmxt_shift ( __int16 @@a1@@ , unsigned int @@a2@@ , __int64 @@a3@@ ) { int @@v5@@ ; __int64 @@v6@@ ; @@v5@@ = @@a1@@ & Number ; if ( ( @@a1@@ & Number ) != Number ) { if ( ( @@a1@@ & Number ) <= Number || ( @@a1@@ & Number ) > Number ) return Number L ; @@v6@@ = iwmmxt_load_creg ( @@v5@@ ) ; tcg_gen_andi_i32 ( @@v6@@ , @@v6@@ , @@a2@@ ) ; } else { @@v6@@ = tcg_temp_new_i32 ( ) ; iwmmxt_load_reg ( cpu_V0 , @@v5@@ ) ; tcg_gen_extrl_i64_i32 ( @@v6@@ , cpu_V0 ) ; tcg_gen_andi_i32 ( @@v6@@ , @@v6@@ , @@a2@@ ) ; } tcg_gen_mov_i32 ( @@a3@@ , @@v6@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "disas_dsp_insn", "code": "__int64 __fastcall disas_dsp_insn ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 result ; unsigned int v3 ; int @@v4@@ ; int @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( ( @@a2@@ & Number ) == Number ) { if ( ( unsigned __int8 ) @@a2@@ >> Number ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , ( unsigned __int16 ) @@a2@@ >> Number ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ & Number ) ; v3 = HIWORD ( @@a2@@ ) & Number ; if ( v3 >= Number ) { if ( ( @@a2@@ & Number ) != Number ) tcg_gen_shri_i32 ( @@v6@@ , @@v6@@ , Number L ) ; if ( ( @@a2@@ & Number ) != Number ) tcg_gen_shri_i32 ( @@v7@@ , @@v7@@ , Number L ) ; gen_helper_iwmmxt_muladdswl ( cpu_M0 , cpu_M0 , @@v6@@ , @@v7@@ ) ; } else if ( v3 ) { if ( v3 != Number ) return Number L ; gen_helper_iwmmxt_muladdsw ( cpu_M0 , cpu_M0 , @@v6@@ , @@v7@@ ) ; } else { gen_helper_iwmmxt_muladdsl ( cpu_M0 , cpu_M0 , @@v6@@ , @@v7@@ ) ; } tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; gen_op_iwmmxt_movq_wRn_M0 ( ( unsigned __int8 ) @@a2@@ >> Number ) ; result = Number L ; } else if ( ( @@a2@@ & Number ) == Number ) { @@v4@@ = HIWORD ( @@a2@@ ) & Number ; @@v5@@ = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != Number ) { result = Number L ; } else { if ( ( @@a2@@ & Number ) != Number ) { iwmmxt_load_reg ( cpu_V0 , @@v5@@ ) ; tcg_gen_extrl_i64_i32 ( cpu_R [ ( unsigned __int16 ) @@a2@@ >> Number ] , cpu_V0 ) ; tcg_gen_extrh_i64_i32 ( cpu_R [ @@v4@@ ] , cpu_V0 ) ; tcg_gen_andi_i32 ( cpu_R [ @@v4@@ ] , cpu_R [ @@v4@@ ] , Number L ) ; } else { tcg_gen_concat_i32_i64 ( cpu_V0 , cpu_R [ ( unsigned __int16 ) @@a2@@ >> Number ] , cpu_R [ @@v4@@ ] ) ; iwmmxt_store_reg ( cpu_V0 , @@v5@@ ) ; } result = Number L ; } } else { result = Number L ; } return result ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v5", "t": {"T": 1, "n": "int", "s": 4}, "location": "s28"}, {"n": "v4", "t": {"T": 1, "n": "int", "s": 4}, "location": "s36"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "insn", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r64"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "acc", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "s28"}, {"n": "rdhi", "t": {"T": 1, "n": "int", "s": 4}, "location": "s36"}, {"n": "tmp2", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 939 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_muladdsl\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_muladdsl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_muladdsl , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_muladdsw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_muladdsw ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_muladdsw , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_iwmmxt_muladdswl\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_muladdswl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_muladdswl , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_shr\", \"code\": \"__int64 __fastcall gen_shr ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shr_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"iwmmxt_store_reg\", \"code\": \"__int64 __fastcall iwmmxt_store_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_st_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_op_iwmmxt_movq_wRn_M0\", \"code\": \"__int64 __fastcall gen_op_iwmmxt_movq_wRn_M0 ( int @@a1@@ ) { return iwmmxt_store_reg ( cpu_M0 , @@a1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}"
] |
{"name": "gen_neon_dup_low16", "code": "__int64 __fastcall gen_neon_dup_low16 ( __int64 @@a1@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; tcg_gen_ext16u_i32 ( @@a1@@ , @@a1@@ ) ; tcg_gen_shli_i32 ( @@v3@@ , @@a1@@ , Number L ) ; tcg_gen_or_i32 ( @@a1@@ , @@a1@@ , @@v3@@ ) ; return tcg_temp_free_i32 ( @@v3@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "var", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 940 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_or_i32\", \"code\": \"__int64 __fastcall tcg_gen_or_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_shl\", \"code\": \"__int64 __fastcall gen_shl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shl_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_neon_dup_high16", "code": "__int64 __fastcall gen_neon_dup_high16 ( __int64 @@a1@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_shri_i32 ( @@v3@@ , @@a1@@ , Number L ) ; tcg_gen_or_i32 ( @@a1@@ , @@a1@@ , @@v3@@ ) ; return tcg_temp_free_i32 ( @@v3@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "var", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 941 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_or_i32\", \"code\": \"__int64 __fastcall tcg_gen_or_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_shr\", \"code\": \"__int64 __fastcall gen_shr ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shr_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "disas_vfp_insn", "code": "__int64 __fastcall disas_vfp_insn ( __int64 @@a1@@ , unsigned int @@a2@@ ) { if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) == Number ) { if ( disas_vfp_uncond ( @@a1@@ , @@a2@@ ) ) return Number L ; } else if ( disas_vfp ( @@a1@@ , @@a2@@ ) ) { return Number L ; } return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "insn", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 942 |
[
"{\"name\": \"extract32\", \"code\": \"__int64 __fastcall extract32 ( unsigned int @@a1@@ , int @@a2@@ , int @@a3@@ ) { if ( @@a2@@ < Number || @@a3@@ <= Number || @@a3@@ > Number - @@a2@@ ) _assert_fail ( String , String , Number , String ) ; return ( @@a1@@ >> @@a2@@ ) & ( Number >> ( Number - @@a3@@ ) ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"disas_vfp\", \"code\": \"_BOOL8 __fastcall disas_vfp ( __int64 @@a1@@ , unsigned int @@a2@@ ) { unsigned int v2 ; _BOOL8 result ; unsigned int v4 ; unsigned int v5 ; unsigned int v6 ; unsigned int v7 ; unsigned int v8 ; unsigned int v9 ; unsigned int v10 ; unsigned int v11 ; unsigned int v12 ; unsigned int v13 ; unsigned int v14 ; unsigned int v15 ; _DWORD @@v16@@ [ Number ] ; unsigned __int64 @@v17@@ ; @@v17@@ = __readfsqword ( Number ) ; v2 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { v10 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_0 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VMOV_to_gp ( @@a1@@ , @@v16@@ ) != Number ; } else { result = Number L ; } } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_1 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VMOV_to_gp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_2 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VMOV_to_gp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v10 != Number ) { if ( v10 <= Number ) { if ( ! v10 ) { v11 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_22 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VFM_dp ( @@a1@@ , @@v16@@ ) != Number ; } if ( v11 != Number ) { if ( v11 <= Number ) { if ( ! v11 ) { disas_vfp_extract_disas_vfp_Fmt_18 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VMLS_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VMLA_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } if ( v11 == Number ) { disas_vfp_extract_disas_vfp_Fmt_18 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VNMUL_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VMUL_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } } return Number L ; } disas_vfp_extract_disas_vfp_Fmt_18 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VDIV_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } if ( v10 == Number ) { if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_6 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VDUP ( @@a1@@ , @@v16@@ ) != Number ; } else { result = Number L ; } } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_3 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VMOV_from_gp ( @@a1@@ , @@v16@@ ) != Number ; } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_4 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VMOV_from_gp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_5 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VMOV_from_gp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } } return Number L ; } v12 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != Number ) { if ( v12 == Number ) { disas_vfp_extract_disas_vfp_Fmt_20 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VFM_dp ( @@a1@@ , @@v16@@ ) != Number ; } if ( v12 <= Number ) { if ( ! v12 ) { disas_vfp_extract_disas_vfp_Fmt_18 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VNMLA_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VNMLS_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } if ( v12 == Number ) { disas_vfp_extract_disas_vfp_Fmt_18 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VSUB_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VADD_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } } return Number L ; } if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_24 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VMOV_imm_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } v13 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_37 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_fix_dp ( @@a1@@ , @@v16@@ ) != Number ; } if ( v13 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_39 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VCVT_dp_int ( @@a1@@ , @@v16@@ ) != Number ; } else if ( ( @@a2@@ & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_33 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) result = ( unsigned __int8 ) trans_VJCVT ( @@a1@@ , @@v16@@ ) != Number ; else result = Number L ; } else { disas_vfp_extract_disas_vfp_Fmt_35 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VCVT_int_dp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v13 > Number ) return Number L ; if ( ! v13 ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_28 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCMP_dp ( @@a1@@ , @@v16@@ ) != Number ; } disas_vfp_extract_disas_vfp_Fmt_26 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; v14 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_VSQRT_dp ( @@a1@@ , @@v16@@ ) != Number ; if ( v14 == Number ) return ( unsigned __int8 ) trans_VNEG_dp ( @@a1@@ , @@v16@@ ) != Number ; if ( v14 > Number ) goto LABEL_195 ; if ( ! v14 ) return ( unsigned __int8 ) trans_VMOV_reg_dp ( @@a1@@ , @@v16@@ ) != Number ; if ( v14 == Number ) result = ( unsigned __int8 ) trans_VABS_dp ( @@a1@@ , @@v16@@ ) != Number ; else LABEL_195 : result = Number L ; return result ; } if ( v13 != ( _DWORD ) & loc_20000 ) return Number L ; v15 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != ( _DWORD ) & unk_50000 ) { if ( v15 <= ( unsigned int ) & unk_50000 ) { if ( v15 == Number ) { disas_vfp_extract_disas_vfp_Fmt_26 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VRINTZ_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VRINTR_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } if ( v15 <= Number ) { if ( ! v15 ) { disas_vfp_extract_disas_vfp_Fmt_30 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_f64_f16 ( @@a1@@ , @@v16@@ ) != Number ; } if ( v15 == Number ) { disas_vfp_extract_disas_vfp_Fmt_31 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_f16_f64 ( @@a1@@ , @@v16@@ ) != Number ; } } } return Number L ; } if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_33 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VCVT_dp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_26 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VRINTX_dp ( @@a1@@ , @@v16@@ ) != Number ; } } else { if ( v2 > Number ) return Number L ; if ( v2 != Number ) { if ( v2 <= Number ) { if ( v2 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_16 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VLDM_VSTM_dp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_12 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VLDR_VSTR_dp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v2 <= Number ) { if ( v2 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_15 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VLDM_VSTM_sp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_11 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VLDR_VSTR_sp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v2 <= Number ) { if ( v2 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_13 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VLDM_VSTM_sp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_9 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_VMOV_64_sp ( @@a1@@ , @@v16@@ ) != Number ; else result = Number L ; } } else { if ( v2 != Number ) return Number L ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_14 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VLDM_VSTM_dp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_10 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_VMOV_64_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = Number L ; } } return result ; } } } return Number L ; } v4 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_7 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_VMSR_VMRS ( @@a1@@ , @@v16@@ ) != Number ; else result = Number L ; return result ; } if ( v4 != Number ) { if ( v4 <= Number ) { if ( v4 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_19 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VFM_sp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_17 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VDIV_sp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v4 <= Number ) { if ( v4 == Number ) { disas_vfp_extract_disas_vfp_Fmt_17 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; v6 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_VSUB_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v6 == Number ) return ( unsigned __int8 ) trans_VADD_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v6 > Number ) goto LABEL_66 ; if ( ! v6 ) return ( unsigned __int8 ) trans_VMUL_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v6 == Number ) result = ( unsigned __int8 ) trans_VNMUL_sp ( @@a1@@ , @@v16@@ ) != Number ; else LABEL_66 : result = Number L ; return result ; } if ( v4 <= Number ) { if ( ! v4 ) { disas_vfp_extract_disas_vfp_Fmt_17 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; v5 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_VNMLA_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v5 == Number ) return ( unsigned __int8 ) trans_VNMLS_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v5 > Number ) goto LABEL_52 ; if ( ! v5 ) return ( unsigned __int8 ) trans_VMLA_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v5 == Number ) result = ( unsigned __int8 ) trans_VMLS_sp ( @@a1@@ , @@v16@@ ) != Number ; else LABEL_52 : result = Number L ; return result ; } if ( v4 == Number ) { disas_vfp_extract_disas_vfp_Fmt_8 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VMOV_single ( @@a1@@ , @@v16@@ ) != Number ; return result ; } } } } return Number L ; } if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_21 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VFM_sp ( @@a1@@ , @@v16@@ ) != Number ; } if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_23 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VMOV_imm_sp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } v7 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_36 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_fix_sp ( @@a1@@ , @@v16@@ ) != Number ; } if ( v7 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_38 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VCVT_sp_int ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_34 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VCVT_int_sp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v7 > Number ) return Number L ; if ( ! v7 ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_27 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCMP_sp ( @@a1@@ , @@v16@@ ) != Number ; } disas_vfp_extract_disas_vfp_Fmt_25 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; v8 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_VSQRT_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v8 == Number ) return ( unsigned __int8 ) trans_VNEG_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v8 > Number ) goto LABEL_96 ; if ( ! v8 ) return ( unsigned __int8 ) trans_VMOV_reg_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v8 == Number ) result = ( unsigned __int8 ) trans_VABS_sp ( @@a1@@ , @@v16@@ ) != Number ; else LABEL_96 : result = Number L ; return result ; } if ( v7 != ( _DWORD ) & loc_20000 ) return Number L ; v9 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != ( _DWORD ) & unk_50000 ) { if ( v9 <= ( unsigned int ) & unk_50000 ) { if ( v9 == Number ) { disas_vfp_extract_disas_vfp_Fmt_25 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VRINTZ_sp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VRINTR_sp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } if ( v9 <= Number ) { if ( ! v9 ) { disas_vfp_extract_disas_vfp_Fmt_29 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_f32_f16 ( @@a1@@ , @@v16@@ ) != Number ; } if ( v9 == Number ) { disas_vfp_extract_disas_vfp_Fmt_29 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_f16_f32 ( @@a1@@ , @@v16@@ ) != Number ; } } } return Number L ; } if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_32 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VCVT_sp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_25 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VRINTX_sp ( @@a1@@ , @@v16@@ ) != Number ; } } return result ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v16\", \"t\": {\"T\": 2, \"n\": 10, \"s\": 4, \"t\": \"_DWORD\"}, \"location\": \"s48\"}, {\"n\": \"v17\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"disas_vfp_uncond\", \"code\": \"_BOOL8 __fastcall disas_vfp_uncond ( __int64 @@a1@@ , unsigned int @@a2@@ ) { unsigned int v2 ; int v4 ; int v5 ; _DWORD @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; v2 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != Number ) { if ( v2 > Number ) return Number L ; if ( v2 != Number ) { if ( v2 <= Number ) { if ( v2 == Number ) { disas_vfp_uncond_extract_disas_vfp_uncond_Fmt_0 ( @@a1@@ , @@v6@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) return Number L ; } else { if ( v2 != Number ) return Number L ; disas_vfp_uncond_extract_disas_vfp_uncond_Fmt_1 ( @@a1@@ , @@v6@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) return Number L ; } return ( unsigned __int8 ) trans_VSEL ( @@a1@@ , @@v6@@ ) != Number ; } return Number L ; } v4 = ( @@a2@@ >> Number ) & Number ; if ( ! v4 ) { disas_vfp_uncond_extract_disas_vfp_uncond_Fmt_2 ( @@a1@@ , @@v6@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VMINMAXNM ( @@a1@@ , @@v6@@ ) != Number ; } if ( v4 != Number ) return Number L ; if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) != Number ) return Number L ; disas_vfp_uncond_extract_disas_vfp_uncond_Fmt_6 ( @@a1@@ , @@v6@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT ( @@a1@@ , @@v6@@ ) != Number ; } disas_vfp_uncond_extract_disas_vfp_uncond_Fmt_4 ( @@a1@@ , @@v6@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) return Number L ; return ( unsigned __int8 ) trans_VRINT ( @@a1@@ , @@v6@@ ) != Number ; } v5 = ( @@a2@@ >> Number ) & Number ; if ( ! v5 ) { disas_vfp_uncond_extract_disas_vfp_uncond_Fmt_3 ( @@a1@@ , @@v6@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VMINMAXNM ( @@a1@@ , @@v6@@ ) != Number ; } if ( v5 != Number ) return Number L ; if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_uncond_extract_disas_vfp_uncond_Fmt_5 ( @@a1@@ , @@v6@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) return Number L ; return ( unsigned __int8 ) trans_VRINT ( @@a1@@ , @@v6@@ ) != Number ; } if ( ( @@a2@@ & Number ) != Number ) return Number L ; disas_vfp_uncond_extract_disas_vfp_uncond_Fmt_7 ( @@a1@@ , @@v6@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT ( @@a1@@ , @@v6@@ ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 6, \"s\": 4, \"t\": \"_DWORD\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "use_goto_tb", "code": "_BOOL8 __fastcall use_goto_tb ( __int64 @@a1@@ , __int64 @@a2@@ ) { return ( target_page [ Number ] & ( @@a2@@ ^ * * ( _QWORD * * ) @@a1@@ ) ) == Number || ( target_page [ Number ] & ( @@a2@@ ^ ( * ( _QWORD * ) ( @@a1@@ + Number ) - Number L ) ) ) == Number ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "dest", "t": {"T": 1, "n": "target_ulong", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 943 |
[] |
{"name": "gen_goto_tb", "code": "__int64 __fastcall gen_goto_tb ( __int64 @@a1@@ , unsigned int @@a2@@ , __int64 @@a3@@ ) { __int64 @@result@@ ; int @@v4@@ ; @@v4@@ = @@a3@@ ; if ( use_goto_tb ( @@a1@@ , @@a3@@ ) ) { tcg_gen_goto_tb ( @@a2@@ ) ; gen_set_pc_im ( @@a1@@ , @@v4@@ ) ; tcg_gen_exit_tb ( * ( _QWORD * ) @@a1@@ , @@a2@@ ) ; } else { gen_set_pc_im ( @@a1@@ , @@v4@@ ) ; gen_goto_ptr ( ) ; } @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}, {"n": "v4", "t": {"T": 1, "n": "int", "s": 4}, "location": "s24"}]}
|
[{"n": "dest", "t": {"T": 1, "n": "target_ulong", "s": 8}, "location": "r16"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "n", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}, {"n": "", "t": {"T": 10}, "location": "s24"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 944 |
[
"{\"name\": \"gen_set_pc_im\", \"code\": \"__int64 __fastcall gen_set_pc_im ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_movi_i32 ( qword_4BEB8 , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"use_goto_tb\", \"code\": \"_BOOL8 __fastcall use_goto_tb ( __int64 @@a1@@ , __int64 @@a2@@ ) { return ( target_page [ Number ] & ( @@a2@@ ^ * * ( _QWORD * * ) @@a1@@ ) ) == Number || ( target_page [ Number ] & ( @@a2@@ ^ ( * ( _QWORD * ) ( @@a1@@ + Number ) - Number L ) ) ) == Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "gen_jmp", "code": "__int64 __fastcall gen_jmp ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@result@@ ; if ( ! is_singlestepping ( @@a1@@ ) ) return gen_goto_tb ( @@a1@@ , Number , @@a2@@ ) ; gen_set_pc_im ( @@a1@@ , @@a2@@ ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "dest", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 945 |
[
"{\"name\": \"is_singlestepping\", \"code\": \"_BOOL8 __fastcall is_singlestepping ( __int64 @@a1@@ ) { return * ( _BYTE * ) ( @@a1@@ + Number ) || * ( _BYTE * ) ( @@a1@@ + Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_set_pc_im\", \"code\": \"__int64 __fastcall gen_set_pc_im ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_movi_i32 ( qword_4BEB8 , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_goto_tb\", \"code\": \"__int64 __fastcall gen_goto_tb ( __int64 @@a1@@ , unsigned int @@a2@@ , __int64 @@a3@@ ) { __int64 @@result@@ ; int @@v4@@ ; @@v4@@ = @@a3@@ ; if ( use_goto_tb ( @@a1@@ , @@a3@@ ) ) { tcg_gen_goto_tb ( @@a2@@ ) ; gen_set_pc_im ( @@a1@@ , @@v4@@ ) ; tcg_gen_exit_tb ( * ( _QWORD * ) @@a1@@ , @@a2@@ ) ; } else { gen_set_pc_im ( @@a1@@ , @@v4@@ ) ; gen_goto_ptr ( ) ; } @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s24\"}]}"
] |
{"name": "gen_mulxy", "code": "__int64 __fastcall gen_mulxy ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ , int @@a4@@ ) { if ( @@a3@@ ) tcg_gen_sari_i32 ( @@a1@@ , @@a1@@ , Number L ) ; else tcg_gen_ext16s_i32 ( @@a1@@ , @@a1@@ ) ; if ( @@a4@@ ) tcg_gen_sari_i32 ( @@a2@@ , @@a2@@ , Number L ) ; else tcg_gen_ext16s_i32 ( @@a2@@ , @@a2@@ ) ; return tcg_gen_mul_i32 ( @@a1@@ , @@a1@@ , @@a2@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "x", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "y", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "t0", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "t1", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 946 |
[
"{\"name\": \"tcg_gen_mul_i32\", \"code\": \"__int64 __fastcall tcg_gen_mul_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_sar\", \"code\": \"__int64 __fastcall gen_sar ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v5@@ , @@v5@@ , @@v6@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; tcg_gen_sar_i32 ( @@a1@@ , @@a2@@ , @@v5@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "msr_mask", "code": "__int64 __fastcall msr_mask ( __int64 @@a1@@ , char @@a2@@ , int @@a3@@ ) { int v5 ; unsigned int v6 ; v5 = Number ; if ( ( @@a2@@ & Number ) != Number ) v5 = Number ; if ( ( @@a2@@ & Number ) != Number ) v5 |= Number ; if ( ( @@a2@@ & Number ) != Number ) v5 |= Number ; if ( ( @@a2@@ & Number ) != Number ) v5 |= Number ; v6 = v5 & Number ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) v6 &= Number ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) v6 &= Number ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) v6 &= Number ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) v6 &= Number ; if ( ! @@a3@@ ) v6 &= Number ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v6 &= Number ; return v6 ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "char", "s": 1}, "location": "r64"}]}
|
[{"n": "spsr", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "flags", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 947 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}"
] |
{"name": "gen_set_psr", "code": "__int64 __fastcall gen_set_psr ( __int64 @@a1@@ , unsigned int @@a2@@ , int @@a3@@ , __int64 @@a4@@ ) { __int64 @@v6@@ ; if ( @@a3@@ ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) return Number L ; @@v6@@ = load_cpu_offset ( Number ) ; tcg_gen_andi_i32 ( @@v6@@ , @@v6@@ , ~ @@a2@@ ) ; tcg_gen_andi_i32 ( @@a4@@ , @@a4@@ , @@a2@@ ) ; tcg_gen_or_i32 ( @@v6@@ , @@v6@@ , @@a4@@ ) ; store_cpu_offset ( @@v6@@ , Number ) ; } else { gen_set_cpsr ( @@a4@@ , @@a2@@ ) ; } tcg_temp_free_i32 ( @@a4@@ ) ; gen_lookup_tb ( @@a1@@ ) ; return Number L ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "spsr", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "t0", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "mask", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r64"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 948 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_gen_or_i32\", \"code\": \"__int64 __fastcall tcg_gen_or_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"load_cpu_offset\", \"code\": \"__int64 __fastcall load_cpu_offset ( int @@a1@@ ) { __int64 @@v2@@ ; @@v2@@ = tcg_temp_new_i32 ( ) ; tcg_gen_ld_i32 ( @@v2@@ , cpu_env , @@a1@@ ) ; return @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_cpu_offset\", \"code\": \"__int64 __fastcall store_cpu_offset ( __int64 @@a1@@ , int @@a2@@ ) { tcg_gen_st_i32 ( @@a1@@ , cpu_env , @@a2@@ ) ; return tcg_temp_free_i32 ( @@a1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_set_cpsr\", \"code\": \"__int64 __fastcall gen_set_cpsr ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_const_i32 ( @@a2@@ ) ; gen_helper_cpsr_write ( cpu_env , @@a1@@ , @@v3@@ ) ; return tcg_temp_free_i32 ( @@v3@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_lookup_tb\", \"code\": \"__int64 __fastcall gen_lookup_tb ( __int64 @@a1@@ ) { __int64 @@result@@ ; tcg_gen_movi_i32 ( qword_4BEB8 , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "gen_set_psr_im", "code": "__int64 __fastcall gen_set_psr_im ( __int64 @@a1@@ , unsigned int @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int64 @@v7@@ ; @@v7@@ = tcg_temp_new_i32 ( ) ; tcg_gen_movi_i32 ( @@v7@@ , @@a4@@ ) ; return gen_set_psr ( @@a1@@ , @@a2@@ , @@a3@@ , @@v7@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "spsr", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "val", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "mask", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r64"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 949 |
[
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_movi_i32\", \"code\": \"__int64 __fastcall tcg_gen_movi_i32 ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_op2i_i32 ( Number , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_set_psr\", \"code\": \"__int64 __fastcall gen_set_psr ( __int64 @@a1@@ , unsigned int @@a2@@ , int @@a3@@ , __int64 @@a4@@ ) { __int64 @@v6@@ ; if ( @@a3@@ ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) return Number L ; @@v6@@ = load_cpu_offset ( Number ) ; tcg_gen_andi_i32 ( @@v6@@ , @@v6@@ , ~ @@a2@@ ) ; tcg_gen_andi_i32 ( @@a4@@ , @@a4@@ , @@a2@@ ) ; tcg_gen_or_i32 ( @@v6@@ , @@v6@@ , @@a4@@ ) ; store_cpu_offset ( @@v6@@ , Number ) ; } else { gen_set_cpsr ( @@a4@@ , @@a2@@ ) ; } tcg_temp_free_i32 ( @@a4@@ ) ; gen_lookup_tb ( @@a1@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "msr_banked_access_decode", "code": "__int64 __fastcall msr_banked_access_decode ( __int64 @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ , _DWORD * @@a5@@ , int * @@a6@@ ) { int v6 ; int v7 ; int v8 ; int v9 ; int v10 ; int v11 ; unsigned int @@v13@@ ; unsigned int @@v18@@ ; @@v18@@ = default_exception_el ( @@a1@@ ) ; if ( ( arm_dc_feature ( @@a1@@ , Number ) || arm_dc_feature ( @@a1@@ , Number ) ) && ! * ( _DWORD * ) ( @@a1@@ + Number ) && @@a4@@ != Number ) { if ( ! @@a2@@ ) { switch ( @@a3@@ ) { case Number : case Number : case Number : case Number : case Number : case Number : case Number : * @@a5@@ = Number ; * @@a6@@ = @@a3@@ + Number ; goto LABEL_42 ; case Number : case Number : case Number : case Number : case Number : case Number : case Number : * @@a5@@ = Number ; * @@a6@@ = @@a3@@ ; goto LABEL_42 ; case Number : case Number : * @@a5@@ = Number ; if ( ( @@a3@@ & Number ) != Number ) v6 = Number ; else v6 = Number ; * @@a6@@ = v6 ; goto LABEL_42 ; case Number : case Number : * @@a5@@ = Number ; if ( ( @@a3@@ & Number ) != Number ) v7 = Number ; else v7 = Number ; * @@a6@@ = v7 ; goto LABEL_42 ; case Number : case Number : * @@a5@@ = Number ; if ( ( @@a3@@ & Number ) != Number ) v8 = Number ; else v8 = Number ; * @@a6@@ = v8 ; goto LABEL_42 ; case Number : case Number : * @@a5@@ = Number ; if ( ( @@a3@@ & Number ) != Number ) v9 = Number ; else v9 = Number ; * @@a6@@ = v9 ; goto LABEL_42 ; case Number : case Number : * @@a5@@ = Number ; if ( ( @@a3@@ & Number ) != Number ) v10 = Number ; else v10 = Number ; * @@a6@@ = v10 ; goto LABEL_42 ; case Number : case Number : * @@a5@@ = Number ; if ( ( @@a3@@ & Number ) != Number ) v11 = Number ; else v11 = Number ; * @@a6@@ = v11 ; goto LABEL_42 ; default : goto LABEL_54 ; } } switch ( @@a3@@ ) { case Number : * @@a5@@ = Number ; break ; case Number : * @@a5@@ = Number ; break ; case Number : * @@a5@@ = Number ; break ; case Number : * @@a5@@ = Number ; break ; case Number : * @@a5@@ = Number ; break ; case Number : * @@a5@@ = Number ; break ; case Number : * @@a5@@ = Number ; break ; default : goto LABEL_54 ; } * @@a6@@ = Number ; LABEL_42 : if ( * @@a5@@ == Number ) { if ( arm_dc_feature ( @@a1@@ , Number ) && ! * ( _BYTE * ) ( @@a1@@ + Number ) ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) != Number ) return Number L ; @@v18@@ = Number ; } } else if ( * @@a5@@ != Number || arm_dc_feature ( @@a1@@ , Number ) && * ( int * ) ( @@a1@@ + Number ) > Number && ( * ( int * ) ( @@a1@@ + Number ) > Number || * @@a6@@ == Number ) ) { return Number L ; } } LABEL_54 : @@v13@@ = syn_uncategorized ( ) ; gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v13@@ , @@v18@@ ) ; return Number L ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "a5", "t": {"T": 3, "t": "_DWORD"}, "location": "r72"}, {"n": "v13", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r8"}, {"n": "a6", "t": {"T": 3, "t": "int"}, "location": "r80"}, {"n": "v18", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s20"}]}
|
[{"n": "sysm", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "r", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "tgtmode", "t": {"T": 3, "t": "int"}, "location": "r72"}, {"n": "", "t": {"T": 10}, "location": "r8"}, {"n": "regno", "t": {"T": 3, "t": "int"}, "location": "r80"}, {"n": "exc_target", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "s20"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 950 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"default_exception_el\", \"code\": \"__int64 __fastcall default_exception_el ( __int64 @@a1@@ ) { __int64 @@result@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) == Number && * ( _BYTE * ) ( @@a1@@ + Number ) ) return Number L ; @@result@@ = * ( unsigned int * ) ( @@a1@@ + Number ) ; if ( ( int ) @@result@@ <= Number ) @@result@@ = Number L ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_exception\", \"code\": \"__int64 __fastcall gen_exception ( unsigned int @@a1@@ , unsigned int @@a2@@ , unsigned int @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_const_i32 ( @@a1@@ ) ; @@v6@@ = tcg_const_i32 ( @@a2@@ ) ; @@v7@@ = tcg_const_i32 ( @@a3@@ ) ; gen_helper_exception_with_syndrome ( cpu_env , @@v5@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_exception_insn\", \"code\": \"__int64 __fastcall gen_exception_insn ( __int64 @@a1@@ , int @@a2@@ , unsigned int @@a3@@ , unsigned int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@result@@ ; gen_set_condexec ( @@a1@@ ) ; gen_set_pc_im ( @@a1@@ , @@a2@@ ) ; gen_exception ( @@a3@@ , @@a4@@ , @@a5@@ ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "gen_msr_banked", "code": "unsigned __int64 __fastcall gen_msr_banked ( __int64 @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ ) { unsigned int @@v6@@ ; unsigned int @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; unsigned __int64 @@v11@@ ; @@v11@@ = __readfsqword ( Number ) ; @@v6@@ = Number ; @@v7@@ = Number ; if ( ( unsigned __int8 ) msr_banked_access_decode ( @@a1@@ , @@a2@@ , @@a3@@ , @@a4@@ , & @@v6@@ , ( int * ) & @@v7@@ ) == Number ) { gen_set_condexec ( @@a1@@ ) ; gen_set_pc_im ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; @@v8@@ = load_reg ( @@a1@@ , @@a4@@ ) ; @@v9@@ = tcg_const_i32 ( @@v6@@ ) ; @@v10@@ = tcg_const_i32 ( @@v7@@ ) ; gen_helper_msr_banked ( cpu_env , @@v8@@ , @@v9@@ , @@v10@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_i32 ( @@v8@@ ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } return __readfsqword ( Number ) ^ @@v11@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v10", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v9", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v8", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s32"}, {"n": "v7", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s36"}, {"n": "v6", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s40"}, {"n": "v11", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "sysm", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "r", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "tcg_regno", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "s16"}, {"n": "tcg_tgtmode", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "s24"}, {"n": "tcg_reg", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "s32"}, {"n": "regno", "t": {"T": 1, "n": "int", "s": 4}, "location": "s36"}, {"n": "tgtmode", "t": {"T": 1, "n": "int", "s": 4}, "location": "s40"}, {"n": "v10", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 951 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_helper_msr_banked\", \"code\": \"unsigned __int64 __fastcall gen_helper_msr_banked ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v7@@ [ Number ] ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; @@v7@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v7@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v7@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v7@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; tcg_gen_callN ( & helper_msr_banked , Number L , Number L , @@v7@@ ) ; return __readfsqword ( Number ) ^ @@v8@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_set_condexec\", \"code\": \"__int64 __fastcall gen_set_condexec ( __int64 @@a1@@ ) { __int64 @@result@@ ; int @@v2@@ ; __int64 @@v3@@ ; @@result@@ = * ( unsigned int * ) ( @@a1@@ + Number ) ; if ( ( _DWORD ) @@result@@ ) { @@v2@@ = ( Number * * ( _DWORD * ) ( @@a1@@ + Number ) ) | ( * ( int * ) ( @@a1@@ + Number ) >> Number ) ; @@v3@@ = tcg_temp_new_i32 ( ) ; tcg_gen_movi_i32 ( @@v3@@ , @@v2@@ ) ; @@result@@ = store_cpu_offset ( @@v3@@ , Number ) ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_set_pc_im\", \"code\": \"__int64 __fastcall gen_set_pc_im ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_movi_i32 ( qword_4BEB8 , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"msr_banked_access_decode\", \"code\": \"__int64 __fastcall msr_banked_access_decode ( __int64 @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ , _DWORD * @@a5@@ , int * @@a6@@ ) { int v6 ; int v7 ; int v8 ; int v9 ; int v10 ; int v11 ; unsigned int @@v13@@ ; unsigned int @@v18@@ ; @@v18@@ = default_exception_el ( @@a1@@ ) ; if ( ( arm_dc_feature ( @@a1@@ , Number ) || arm_dc_feature ( @@a1@@ , Number ) ) && ! * ( _DWORD * ) ( @@a1@@ + Number ) && @@a4@@ != Number ) { if ( ! @@a2@@ ) { switch ( @@a3@@ ) { case Number : case Number : case Number : case Number : case Number : case Number : case Number : * @@a5@@ = Number ; * @@a6@@ = @@a3@@ + Number ; goto LABEL_42 ; case Number : case Number : case Number : case Number : case Number : case Number : case Number : * @@a5@@ = Number ; * @@a6@@ = @@a3@@ ; goto LABEL_42 ; case Number : case Number : * @@a5@@ = Number ; if ( ( @@a3@@ & Number ) != Number ) v6 = Number ; else v6 = Number ; * @@a6@@ = v6 ; goto LABEL_42 ; case Number : case Number : * @@a5@@ = Number ; if ( ( @@a3@@ & Number ) != Number ) v7 = Number ; else v7 = Number ; * @@a6@@ = v7 ; goto LABEL_42 ; case Number : case Number : * @@a5@@ = Number ; if ( ( @@a3@@ & Number ) != Number ) v8 = Number ; else v8 = Number ; * @@a6@@ = v8 ; goto LABEL_42 ; case Number : case Number : * @@a5@@ = Number ; if ( ( @@a3@@ & Number ) != Number ) v9 = Number ; else v9 = Number ; * @@a6@@ = v9 ; goto LABEL_42 ; case Number : case Number : * @@a5@@ = Number ; if ( ( @@a3@@ & Number ) != Number ) v10 = Number ; else v10 = Number ; * @@a6@@ = v10 ; goto LABEL_42 ; case Number : case Number : * @@a5@@ = Number ; if ( ( @@a3@@ & Number ) != Number ) v11 = Number ; else v11 = Number ; * @@a6@@ = v11 ; goto LABEL_42 ; default : goto LABEL_54 ; } } switch ( @@a3@@ ) { case Number : * @@a5@@ = Number ; break ; case Number : * @@a5@@ = Number ; break ; case Number : * @@a5@@ = Number ; break ; case Number : * @@a5@@ = Number ; break ; case Number : * @@a5@@ = Number ; break ; case Number : * @@a5@@ = Number ; break ; case Number : * @@a5@@ = Number ; break ; default : goto LABEL_54 ; } * @@a6@@ = Number ; LABEL_42 : if ( * @@a5@@ == Number ) { if ( arm_dc_feature ( @@a1@@ , Number ) && ! * ( _BYTE * ) ( @@a1@@ + Number ) ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) != Number ) return Number L ; @@v18@@ = Number ; } } else if ( * @@a5@@ != Number || arm_dc_feature ( @@a1@@ , Number ) && * ( int * ) ( @@a1@@ + Number ) > Number && ( * ( int * ) ( @@a1@@ + Number ) > Number || * @@a6@@ == Number ) ) { return Number L ; } } LABEL_54 : @@v13@@ = syn_uncategorized ( ) ; gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v13@@ , @@v18@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r72\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"a6\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r80\"}, {\"n\": \"v18\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s20\"}]}"
] |
{"name": "gen_mrs_banked", "code": "unsigned __int64 __fastcall gen_mrs_banked ( __int64 @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ ) { unsigned int @@v6@@ ; unsigned int @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; unsigned __int64 @@v11@@ ; @@v11@@ = __readfsqword ( Number ) ; @@v6@@ = Number ; @@v7@@ = Number ; if ( ( unsigned __int8 ) msr_banked_access_decode ( @@a1@@ , @@a2@@ , @@a3@@ , @@a4@@ , & @@v6@@ , ( int * ) & @@v7@@ ) == Number ) { gen_set_condexec ( @@a1@@ ) ; gen_set_pc_im ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; @@v8@@ = tcg_temp_new_i32 ( ) ; @@v9@@ = tcg_const_i32 ( @@v6@@ ) ; @@v10@@ = tcg_const_i32 ( @@v7@@ ) ; gen_helper_mrs_banked ( @@v8@@ , cpu_env , @@v9@@ , @@v10@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; store_reg ( @@a1@@ , @@a4@@ , @@v8@@ ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } return __readfsqword ( Number ) ^ @@v11@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v10", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v9", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v8", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s32"}, {"n": "v7", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s36"}, {"n": "v6", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s40"}, {"n": "v11", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "sysm", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "r", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "tcg_regno", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "s16"}, {"n": "tcg_tgtmode", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "s24"}, {"n": "tcg_reg", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "s32"}, {"n": "regno", "t": {"T": 1, "n": "int", "s": 4}, "location": "s36"}, {"n": "tgtmode", "t": {"T": 1, "n": "int", "s": 4}, "location": "s40"}, {"n": "v10", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 952 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_mrs_banked\", \"code\": \"unsigned __int64 __fastcall gen_helper_mrs_banked ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_mrs_banked , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_set_condexec\", \"code\": \"__int64 __fastcall gen_set_condexec ( __int64 @@a1@@ ) { __int64 @@result@@ ; int @@v2@@ ; __int64 @@v3@@ ; @@result@@ = * ( unsigned int * ) ( @@a1@@ + Number ) ; if ( ( _DWORD ) @@result@@ ) { @@v2@@ = ( Number * * ( _DWORD * ) ( @@a1@@ + Number ) ) | ( * ( int * ) ( @@a1@@ + Number ) >> Number ) ; @@v3@@ = tcg_temp_new_i32 ( ) ; tcg_gen_movi_i32 ( @@v3@@ , @@v2@@ ) ; @@result@@ = store_cpu_offset ( @@v3@@ , Number ) ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_set_pc_im\", \"code\": \"__int64 __fastcall gen_set_pc_im ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_movi_i32 ( qword_4BEB8 , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"msr_banked_access_decode\", \"code\": \"__int64 __fastcall msr_banked_access_decode ( __int64 @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ , _DWORD * @@a5@@ , int * @@a6@@ ) { int v6 ; int v7 ; int v8 ; int v9 ; int v10 ; int v11 ; unsigned int @@v13@@ ; unsigned int @@v18@@ ; @@v18@@ = default_exception_el ( @@a1@@ ) ; if ( ( arm_dc_feature ( @@a1@@ , Number ) || arm_dc_feature ( @@a1@@ , Number ) ) && ! * ( _DWORD * ) ( @@a1@@ + Number ) && @@a4@@ != Number ) { if ( ! @@a2@@ ) { switch ( @@a3@@ ) { case Number : case Number : case Number : case Number : case Number : case Number : case Number : * @@a5@@ = Number ; * @@a6@@ = @@a3@@ + Number ; goto LABEL_42 ; case Number : case Number : case Number : case Number : case Number : case Number : case Number : * @@a5@@ = Number ; * @@a6@@ = @@a3@@ ; goto LABEL_42 ; case Number : case Number : * @@a5@@ = Number ; if ( ( @@a3@@ & Number ) != Number ) v6 = Number ; else v6 = Number ; * @@a6@@ = v6 ; goto LABEL_42 ; case Number : case Number : * @@a5@@ = Number ; if ( ( @@a3@@ & Number ) != Number ) v7 = Number ; else v7 = Number ; * @@a6@@ = v7 ; goto LABEL_42 ; case Number : case Number : * @@a5@@ = Number ; if ( ( @@a3@@ & Number ) != Number ) v8 = Number ; else v8 = Number ; * @@a6@@ = v8 ; goto LABEL_42 ; case Number : case Number : * @@a5@@ = Number ; if ( ( @@a3@@ & Number ) != Number ) v9 = Number ; else v9 = Number ; * @@a6@@ = v9 ; goto LABEL_42 ; case Number : case Number : * @@a5@@ = Number ; if ( ( @@a3@@ & Number ) != Number ) v10 = Number ; else v10 = Number ; * @@a6@@ = v10 ; goto LABEL_42 ; case Number : case Number : * @@a5@@ = Number ; if ( ( @@a3@@ & Number ) != Number ) v11 = Number ; else v11 = Number ; * @@a6@@ = v11 ; goto LABEL_42 ; default : goto LABEL_54 ; } } switch ( @@a3@@ ) { case Number : * @@a5@@ = Number ; break ; case Number : * @@a5@@ = Number ; break ; case Number : * @@a5@@ = Number ; break ; case Number : * @@a5@@ = Number ; break ; case Number : * @@a5@@ = Number ; break ; case Number : * @@a5@@ = Number ; break ; case Number : * @@a5@@ = Number ; break ; default : goto LABEL_54 ; } * @@a6@@ = Number ; LABEL_42 : if ( * @@a5@@ == Number ) { if ( arm_dc_feature ( @@a1@@ , Number ) && ! * ( _BYTE * ) ( @@a1@@ + Number ) ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) != Number ) return Number L ; @@v18@@ = Number ; } } else if ( * @@a5@@ != Number || arm_dc_feature ( @@a1@@ , Number ) && * ( int * ) ( @@a1@@ + Number ) > Number && ( * ( int * ) ( @@a1@@ + Number ) > Number || * @@a6@@ == Number ) ) { return Number L ; } } LABEL_54 : @@v13@@ = syn_uncategorized ( ) ; gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v13@@ , @@v18@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r72\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"a6\", \"t\": {\"T\": 3, \"t\": \"int\"}, \"location\": \"r80\"}, {\"n\": \"v18\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s20\"}]}"
] |
{"name": "store_pc_exc_ret", "code": "__int64 __fastcall store_pc_exc_ret ( __int64 @@a1@@ , __int64 @@a2@@ ) { tcg_gen_mov_i32 ( qword_4BEB8 , @@a2@@ ) ; return tcg_temp_free_i32 ( @@a2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "pc", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 953 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_gen_mov_i32\", \"code\": \"__int64 __fastcall tcg_gen_mov_i32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@result@@ ; @@result@@ = @@a1@@ ; if ( @@a1@@ != @@a2@@ ) @@result@@ = tcg_gen_op2_i32 ( Number , @@a1@@ , @@a2@@ ) ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "gen_rfe", "code": "__int64 __fastcall gen_rfe ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@result@@ ; store_pc_exc_ret ( @@a1@@ , @@a2@@ ) ; if ( ( tb_cflags ( * ( _QWORD * ) @@a1@@ ) & Number ) != Number ) gen_io_start ( ) ; gen_helper_cpsr_write_eret ( cpu_env , @@a3@@ ) ; tcg_temp_free_i32 ( @@a3@@ ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "cpsr", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "pc", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 954 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tb_cflags\", \"code\": \"__int64 __fastcall tb_cflags ( __int64 @@a1@@ ) { return * ( unsigned int * ) ( @@a1@@ + Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_helper_cpsr_write\", \"code\": \"unsigned __int64 __fastcall gen_helper_cpsr_write ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ [ Number ] ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v5@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v5@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; tcg_gen_callN ( & helper_cpsr_write , Number L , Number L , @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_cpsr_write_eret\", \"code\": \"unsigned __int64 __fastcall gen_helper_cpsr_write_eret ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v3@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; tcg_gen_callN ( & helper_cpsr_write_eret , Number L , Number L , @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_io_start\", \"code\": \"__int64 gen_io_start ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_const_i32 ( Number L ) ; tcg_gen_st_i32 ( @@v1@@ , cpu_env , Number ) ; return tcg_temp_free_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_pc_exc_ret\", \"code\": \"__int64 __fastcall store_pc_exc_ret ( __int64 @@a1@@ , __int64 @@a2@@ ) { tcg_gen_mov_i32 ( qword_4BEB8 , @@a2@@ ) ; return tcg_temp_free_i32 ( @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "gen_exception_return", "code": "__int64 __fastcall gen_exception_return ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = load_cpu_offset ( Number ) ; return gen_rfe ( @@a1@@ , @@a2@@ , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "pc", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 955 |
[
"{\"name\": \"gen_exception\", \"code\": \"__int64 __fastcall gen_exception ( unsigned int @@a1@@ , unsigned int @@a2@@ , unsigned int @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_const_i32 ( @@a1@@ ) ; @@v6@@ = tcg_const_i32 ( @@a2@@ ) ; @@v7@@ = tcg_const_i32 ( @@a3@@ ) ; gen_helper_exception_with_syndrome ( cpu_env , @@v5@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_cpu_offset\", \"code\": \"__int64 __fastcall load_cpu_offset ( int @@a1@@ ) { __int64 @@v2@@ ; @@v2@@ = tcg_temp_new_i32 ( ) ; tcg_gen_ld_i32 ( @@v2@@ , cpu_env , @@a1@@ ) ; return @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_rfe\", \"code\": \"__int64 __fastcall gen_rfe ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@result@@ ; store_pc_exc_ret ( @@a1@@ , @@a2@@ ) ; if ( ( tb_cflags ( * ( _QWORD * ) @@a1@@ ) & Number ) != Number ) gen_io_start ( ) ; gen_helper_cpsr_write_eret ( cpu_env , @@a3@@ ) ; tcg_temp_free_i32 ( @@a3@@ ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "gen_neon_add", "code": "__int64 __fastcall gen_neon_add ( int @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { if ( @@a1@@ == Number ) return tcg_gen_add_i32 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; if ( @@a1@@ > Number ) goto LABEL_9 ; if ( ! @@a1@@ ) return gen_helper_neon_add_u8 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; if ( @@a1@@ != Number ) LABEL_9 : abort ( ) ; return gen_helper_neon_add_u16 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "t1", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "size", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "t0", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 956 |
[
"{\"name\": \"gen_helper_neon_add_u8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_add_u8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_add_u8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_add_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_add_u16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_add_u16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_add_i32\", \"code\": \"__int64 __fastcall tcg_gen_add_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "gen_neon_rsb", "code": "__int64 __fastcall gen_neon_rsb ( int @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@result@@ ; if ( @@a1@@ == Number ) return tcg_gen_sub_i32 ( @@a2@@ , @@a3@@ , @@a2@@ ) ; if ( @@a1@@ <= Number ) { if ( @@a1@@ ) { if ( @@a1@@ == Number ) @@result@@ = gen_helper_neon_sub_u16 ( @@a2@@ , @@a3@@ , @@a2@@ ) ; } else { @@result@@ = gen_helper_neon_sub_u8 ( @@a2@@ , @@a3@@ , @@a2@@ ) ; } } return @@result@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "t1", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "size", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "t0", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 957 |
[
"{\"name\": \"gen_helper_neon_sub_u8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_sub_u8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_sub_u8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_sub_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_sub_u16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_sub_u16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_sub_i32\", \"code\": \"__int64 __fastcall tcg_gen_sub_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "neon_load_scratch", "code": "__int64 __fastcall neon_load_scratch ( int @@a1@@ ) { __int64 @@v2@@ ; @@v2@@ = tcg_temp_new_i32 ( ) ; tcg_gen_ld_i32 ( @@v2@@ , cpu_env , Number * ( @@a1@@ + Number L ) ) ; return @@v2@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "v2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "scratch", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 958 |
[
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_ld_i32\", \"code\": \"__int64 __fastcall tcg_gen_ld_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "neon_store_scratch", "code": "__int64 __fastcall neon_store_scratch ( int @@a1@@ , __int64 @@a2@@ ) { tcg_gen_st_i32 ( @@a2@@ , cpu_env , Number * ( @@a1@@ + Number L ) ) ; return tcg_temp_free_i32 ( @@a2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "scratch", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "var", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 959 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_gen_st_i32\", \"code\": \"__int64 __fastcall tcg_gen_st_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "neon_get_scalar", "code": "__int64 __fastcall neon_get_scalar ( int @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; if ( @@a1@@ != Number ) return neon_load_reg ( @@a2@@ & Number , @@a2@@ >> Number ) ; @@v3@@ = neon_load_reg ( @@a2@@ & Number , @@a2@@ >> Number ) ; if ( ( @@a2@@ & Number ) != Number ) gen_neon_dup_high16 ( @@v3@@ ) ; else gen_neon_dup_low16 ( @@v3@@ ) ; return @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "size", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "reg", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 960 |
[
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_load_reg\", \"code\": \"__int64 __fastcall neon_load_reg ( int @@a1@@ , int @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v2@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_ld_i32 ( @@v4@@ , cpu_env , @@v2@@ ) ; return @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_neon_dup_low16\", \"code\": \"__int64 __fastcall gen_neon_dup_low16 ( __int64 @@a1@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; tcg_gen_ext16u_i32 ( @@a1@@ , @@a1@@ ) ; tcg_gen_shli_i32 ( @@v3@@ , @@a1@@ , Number L ) ; tcg_gen_or_i32 ( @@a1@@ , @@a1@@ , @@v3@@ ) ; return tcg_temp_free_i32 ( @@v3@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_neon_dup_high16\", \"code\": \"__int64 __fastcall gen_neon_dup_high16 ( __int64 @@a1@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_shri_i32 ( @@v3@@ , @@a1@@ , Number L ) ; tcg_gen_or_i32 ( @@a1@@ , @@a1@@ , @@v3@@ ) ; return tcg_temp_free_i32 ( @@v3@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_neon_unzip", "code": "__int64 __fastcall gen_neon_unzip ( unsigned int @@a1@@ , unsigned int @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int64 @@v7@@ ; __int64 @@v8@@ ; if ( ! @@a4@@ && @@a3@@ == Number ) return Number L ; @@v7@@ = vfp_reg_ptr ( Number , @@a1@@ ) ; @@v8@@ = vfp_reg_ptr ( Number , @@a2@@ ) ; if ( @@a4@@ ) { if ( @@a3@@ == Number ) { gen_helper_neon_qunzip32 ( @@v7@@ , @@v8@@ ) ; } else { if ( @@a3@@ > Number ) goto LABEL_13 ; if ( @@a3@@ ) { if ( @@a3@@ != Number ) LABEL_13 : abort ( ) ; gen_helper_neon_qunzip16 ( @@v7@@ , @@v8@@ ) ; } else { gen_helper_neon_qunzip8 ( @@v7@@ , @@v8@@ ) ; } } } else if ( @@a3@@ ) { if ( @@a3@@ != Number ) abort ( ) ; gen_helper_neon_unzip16 ( @@v7@@ , @@v8@@ ) ; } else { gen_helper_neon_unzip8 ( @@v7@@ , @@v8@@ ) ; } tcg_temp_free_ptr ( @@v7@@ ) ; tcg_temp_free_ptr ( @@v8@@ ) ; return Number L ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v8", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "size", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "q", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "rd", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "rm", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "pd", "t": {"T": 3, "t": "TCGv_ptr_d"}, "location": "s16"}, {"n": "pm", "t": {"T": 3, "t": "TCGv_ptr_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 961 |
[
"{\"name\": \"tcg_temp_free_ptr\", \"code\": \"__int64 __fastcall tcg_temp_free_ptr ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_ptr_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_helper_neon_unzip8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_unzip8 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; tcg_gen_callN ( & helper_neon_unzip8 , Number L , Number L , @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_unzip16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_unzip16 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; tcg_gen_callN ( & helper_neon_unzip16 , Number L , Number L , @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qunzip8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qunzip8 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; tcg_gen_callN ( & helper_neon_qunzip8 , Number L , Number L , @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qunzip16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qunzip16 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; tcg_gen_callN ( & helper_neon_qunzip16 , Number L , Number L , @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qunzip32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qunzip32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; tcg_gen_callN ( & helper_neon_qunzip32 , Number L , Number L , @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"vfp_reg_ptr\", \"code\": \"__int64 __fastcall vfp_reg_ptr ( char @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; @@v4@@ = tcg_temp_new_ptr ( ) ; @@v2@@ = vfp_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_addi_ptr ( @@v4@@ , cpu_env , @@v2@@ ) ; return @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_neon_zip", "code": "__int64 __fastcall gen_neon_zip ( unsigned int @@a1@@ , unsigned int @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int64 @@v7@@ ; __int64 @@v8@@ ; if ( ! @@a4@@ && @@a3@@ == Number ) return Number L ; @@v7@@ = vfp_reg_ptr ( Number , @@a1@@ ) ; @@v8@@ = vfp_reg_ptr ( Number , @@a2@@ ) ; if ( @@a4@@ ) { if ( @@a3@@ == Number ) { gen_helper_neon_qzip32 ( @@v7@@ , @@v8@@ ) ; } else { if ( @@a3@@ > Number ) goto LABEL_13 ; if ( @@a3@@ ) { if ( @@a3@@ != Number ) LABEL_13 : abort ( ) ; gen_helper_neon_qzip16 ( @@v7@@ , @@v8@@ ) ; } else { gen_helper_neon_qzip8 ( @@v7@@ , @@v8@@ ) ; } } } else if ( @@a3@@ ) { if ( @@a3@@ != Number ) abort ( ) ; gen_helper_neon_zip16 ( @@v7@@ , @@v8@@ ) ; } else { gen_helper_neon_zip8 ( @@v7@@ , @@v8@@ ) ; } tcg_temp_free_ptr ( @@v7@@ ) ; tcg_temp_free_ptr ( @@v8@@ ) ; return Number L ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v8", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "size", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "q", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "rd", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "rm", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "pd", "t": {"T": 3, "t": "TCGv_ptr_d"}, "location": "s16"}, {"n": "pm", "t": {"T": 3, "t": "TCGv_ptr_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 962 |
[
"{\"name\": \"tcg_temp_free_ptr\", \"code\": \"__int64 __fastcall tcg_temp_free_ptr ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_ptr_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_helper_neon_zip8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_zip8 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; tcg_gen_callN ( & helper_neon_zip8 , Number L , Number L , @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_zip16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_zip16 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; tcg_gen_callN ( & helper_neon_zip16 , Number L , Number L , @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qzip8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qzip8 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; tcg_gen_callN ( & helper_neon_qzip8 , Number L , Number L , @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qzip16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qzip16 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; tcg_gen_callN ( & helper_neon_qzip16 , Number L , Number L , @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qzip32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qzip32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; tcg_gen_callN ( & helper_neon_qzip32 , Number L , Number L , @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"vfp_reg_ptr\", \"code\": \"__int64 __fastcall vfp_reg_ptr ( char @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; @@v4@@ = tcg_temp_new_ptr ( ) ; @@v2@@ = vfp_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_addi_ptr ( @@v4@@ , cpu_env , @@v2@@ ) ; return @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_neon_trn_u8", "code": "__int64 __fastcall gen_neon_trn_u8 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v4@@ ; __int64 @@v5@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_shli_i32 ( @@v4@@ , @@a1@@ , Number L ) ; tcg_gen_andi_i32 ( @@v4@@ , @@v4@@ , Number L ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a2@@ , Number L ) ; tcg_gen_or_i32 ( @@v4@@ , @@v4@@ , @@v5@@ ) ; tcg_gen_shri_i32 ( @@a2@@ , @@a2@@ , Number L ) ; tcg_gen_andi_i32 ( @@a2@@ , @@a2@@ , Number L ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a1@@ , Number L ) ; tcg_gen_or_i32 ( @@a2@@ , @@a2@@ , @@v5@@ ) ; tcg_gen_mov_i32 ( @@a1@@ , @@v4@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; return tcg_temp_free_i32 ( @@v4@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "t0", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "t1", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}, {"n": "rd", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 963 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_mov_i32\", \"code\": \"__int64 __fastcall tcg_gen_mov_i32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@result@@ ; @@result@@ = @@a1@@ ; if ( @@a1@@ != @@a2@@ ) @@result@@ = tcg_gen_op2_i32 ( Number , @@a1@@ , @@a2@@ ) ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_gen_or_i32\", \"code\": \"__int64 __fastcall tcg_gen_or_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_shl\", \"code\": \"__int64 __fastcall gen_shl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shl_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_shr\", \"code\": \"__int64 __fastcall gen_shr ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shr_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_neon_trn_u16", "code": "__int64 __fastcall gen_neon_trn_u16 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v4@@ ; __int64 @@v5@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_shli_i32 ( @@v4@@ , @@a1@@ , Number L ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a2@@ , Number ) ; tcg_gen_or_i32 ( @@v4@@ , @@v4@@ , @@v5@@ ) ; tcg_gen_shri_i32 ( @@a2@@ , @@a2@@ , Number L ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a1@@ , Number L ) ; tcg_gen_or_i32 ( @@a2@@ , @@a2@@ , @@v5@@ ) ; tcg_gen_mov_i32 ( @@a1@@ , @@v4@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; return tcg_temp_free_i32 ( @@v4@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "t0", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "t1", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}, {"n": "rd", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 964 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_mov_i32\", \"code\": \"__int64 __fastcall tcg_gen_mov_i32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@result@@ ; @@result@@ = @@a1@@ ; if ( @@a1@@ != @@a2@@ ) @@result@@ = tcg_gen_op2_i32 ( Number , @@a1@@ , @@a2@@ ) ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_gen_or_i32\", \"code\": \"__int64 __fastcall tcg_gen_or_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_shl\", \"code\": \"__int64 __fastcall gen_shl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shl_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_shr\", \"code\": \"__int64 __fastcall gen_shr ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shr_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "disas_neon_ls_insn", "code": "__int64 __fastcall disas_neon_ls_insn ( __int64 @@a1@@ , unsigned int @@a2@@ ) { unsigned int v2 ; unsigned int v3 ; int v5 ; int v6 ; int v7 ; int v8 ; int v9 ; unsigned int v10 ; unsigned int v11 ; unsigned int v12 ; unsigned int v13 ; int v14 ; int v15 ; int v16 ; int v17 ; int v18 ; int v19 ; int @@v20@@ ; unsigned int v21 ; int v22 ; int v23 ; int v24 ; int v25 ; unsigned int v26 ; int i ; int l ; int m ; int @@j@@ ; int @@v31@@ ; int @@k@@ ; int @@v33@@ ; int @@v34@@ ; int @@v35@@ ; int @@v36@@ ; int @@v37@@ ; int v38 ; int v39 ; int v40 ; int @@v41@@ ; unsigned int @@v42@@ ; unsigned int @@v43@@ ; int @@v44@@ ; int @@v45@@ ; int @@v46@@ ; __int64 v47 ; __int64 v48 ; __int64 v49 ; __int64 v50 ; __int64 v51 ; __int64 @@v52@@ ; __int64 @@v53@@ ; __int64 @@v54@@ ; __int64 @@v55@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { v2 = * ( _DWORD * ) ( @@a1@@ + Number ) ; v3 = syn_simd_access_trap ( Number , Number , Number ) ; gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , v3 , v2 ) ; return Number L ; } if ( * ( _BYTE * ) ( @@a1@@ + Number ) != Number ) return Number L ; if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v20@@ = ( ( unsigned __int16 ) @@a2@@ >> Number ) | ( @@a2@@ >> Number ) & Number ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v20@@ = ( unsigned __int16 ) @@a2@@ >> Number ; } @@v34@@ = HIWORD ( @@a2@@ ) & Number ; @@v35@@ = @@a2@@ & Number ; @@v31@@ = * ( _DWORD * ) ( @@a1@@ + Number ) ; @@v36@@ = get_mem_index ( @@a1@@ ) ; if ( ( @@a2@@ & Number ) == Number ) { @@v43@@ = ( @@a2@@ >> Number ) & Number ; v24 = ( unsigned __int8 ) @@a2@@ >> Number ; if ( @@v43@@ > Number ) return Number L ; v5 = @@v43@@ & Number ; if ( v5 == Number ) { if ( ( @@a2@@ & Number ) != Number ) return Number L ; } else if ( v5 == Number && ( ( @@a2@@ >> Number ) & Number ) == Number ) { return Number L ; } v38 = * ( ( _DWORD * ) & neon_ls_element_type + Number * ( int ) @@v43@@ ) ; @@v44@@ = * ( ( _DWORD * ) & unk_4D764 + Number * ( int ) @@v43@@ ) ; @@v45@@ = dword_4D768 [ Number * @@v43@@ ] ; if ( v24 == Number && ( @@v45@@ | @@v44@@ ) != Number ) return Number L ; if ( ! ( ( unsigned __int8 ) @@a2@@ >> Number ) ) @@v31@@ = Number ; if ( @@v44@@ == Number && ! @@v31@@ ) v24 = Number ; @@v52@@ = tcg_temp_new_i64 ( ) ; v49 = tcg_temp_new_i32 ( ) ; @@v53@@ = tcg_const_i32 ( ( unsigned int ) ( Number << v24 ) ) ; load_reg_var ( @@a1@@ , v49 , @@v34@@ ) ; for ( i = Number ; i < v38 ; ++ i ) { for ( @@j@@ = Number ; @@j@@ < Number >> v24 ; ++ @@j@@ ) { for ( @@k@@ = Number ; @@k@@ < @@v44@@ ; ++ @@k@@ ) { @@v46@@ = i + @@v20@@ + @@k@@ * @@v45@@ ; if ( ( @@a2@@ & Number ) != Number ) { gen_aa32_ld_i64 ( @@a1@@ , @@v52@@ , v49 , @@v36@@ , @@v31@@ | v24 ) ; neon_store_element64 ( @@v46@@ , @@j@@ , v24 , @@v52@@ ) ; } else { neon_load_element64 ( @@v52@@ , @@v46@@ , @@j@@ , v24 ) ; gen_aa32_st_i64 ( @@a1@@ , @@v52@@ , v49 , @@v36@@ , @@v31@@ | v24 ) ; } tcg_gen_add_i32 ( v49 , v49 , @@v53@@ ) ; } } } tcg_temp_free_i32 ( v49 ) ; tcg_temp_free_i32 ( @@v53@@ ) ; tcg_temp_free_i64 ( @@v52@@ ) ; v21 = Number * @@v44@@ * v38 ; goto LABEL_111 ; } v25 = ( @@a2@@ >> Number ) & Number ; if ( v25 == Number ) { @@v41@@ = ( @@a2@@ >> Number ) & Number ; if ( ( @@a2@@ & Number ) == Number ) return Number L ; v26 = ( unsigned __int8 ) @@a2@@ >> Number ; v39 = ( ( @@a2@@ >> Number ) & Number ) + Number ; if ( v26 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number || ! @@v41@@ ) return Number L ; v26 = Number ; } if ( ( ( @@a2@@ >> Number ) & Number ) == Number && @@v41@@ == Number && ! v26 ) return Number L ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number && @@v41@@ == Number ) return Number L ; v50 = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , v50 , @@v34@@ ) ; if ( ( @@a2@@ & Number ) != Number ) v6 = Number ; else v6 = Number ; v22 = v6 ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) v7 = Number ; else v7 = Number * v6 ; @@v42@@ = v7 ; v47 = tcg_temp_new_i32 ( ) ; for ( l = Number ; l < v39 ; ++ l ) { v8 = v26 | * ( _DWORD * ) ( @@a1@@ + Number ) ; v9 = get_mem_index ( @@a1@@ ) ; gen_aa32_ld_i32 ( @@a1@@ , v47 , v50 , v9 , v8 ) ; if ( ( @@v20@@ & Number ) != Number && @@v42@@ == Number ) { v10 = neon_reg_offset ( @@v20@@ , Number ) ; tcg_gen_gvec_dup_i32 ( v26 , v10 , Number L , Number L , v47 ) ; v11 = neon_reg_offset ( @@v20@@ , Number ) ; v12 = neon_reg_offset ( @@v20@@ + Number , Number ) ; tcg_gen_gvec_mov ( Number L , v12 , v11 , Number L , Number L ) ; } else { v13 = neon_reg_offset ( @@v20@@ , Number ) ; tcg_gen_gvec_dup_i32 ( v26 , v13 , @@v42@@ , @@v42@@ , v47 ) ; } tcg_gen_addi_i32 ( v50 , v50 , ( unsigned int ) ( Number << v26 ) ) ; @@v20@@ += v22 ; } tcg_temp_free_i32 ( v47 ) ; tcg_temp_free_i32 ( v50 ) ; v21 = v39 << v26 ; goto LABEL_111 ; } @@v37@@ = ( unsigned __int8 ) @@a2@@ >> Number ; if ( v25 == Number ) { @@v33@@ = ( @@a2@@ >> Number ) & Number ; if ( ( @@a2@@ & Number ) != Number ) v15 = Number ; else v15 = Number ; v23 = v15 ; } else if ( v25 ) { @@v33@@ = ( unsigned __int8 ) @@a2@@ >> Number ; if ( ( @@a2@@ & Number ) != Number ) v14 = Number ; else v14 = Number ; v23 = v14 ; } else { @@v33@@ = ( unsigned __int8 ) @@a2@@ >> Number ; v23 = Number ; } v40 = ( ( @@a2@@ >> Number ) & Number ) + Number ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) { if ( v25 == Number && ( @@v37@@ & Number ) == Number ) return Number L ; goto LABEL_102 ; } if ( v40 > Number ) goto LABEL_101 ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) { if ( ( @@a2@@ & Number ) != Number ) return Number L ; LABEL_95 : if ( v25 == Number && ( @@v37@@ & Number ) != Number ) return Number L ; goto LABEL_102 ; } if ( v40 > Number ) goto LABEL_101 ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) LABEL_101 : abort ( ) ; goto LABEL_95 ; } if ( ( ( @@v37@@ >> v25 ) & Number ) != Number || v25 == Number && ( ( @@v37@@ & Number ) == Number || ( @@v37@@ & Number ) == Number ) ) return Number L ; LABEL_102 : if ( ( int ) ( v23 * ( ( @@a2@@ >> Number ) & Number ) + @@v20@@ ) > Number ) return Number L ; v48 = tcg_temp_new_i32 ( ) ; v51 = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , v51 , @@v34@@ ) ; for ( m = Number ; m < v40 ; ++ m ) { if ( ( @@a2@@ & Number ) != Number ) { v16 = v25 | * ( _DWORD * ) ( @@a1@@ + Number ) ; v17 = get_mem_index ( @@a1@@ ) ; gen_aa32_ld_i32 ( @@a1@@ , v48 , v51 , v17 , v16 ) ; neon_store_element ( @@v20@@ , @@v33@@ , v25 , v48 ) ; } else { neon_load_element ( v48 , @@v20@@ , @@v33@@ , v25 ) ; v18 = v25 | * ( _DWORD * ) ( @@a1@@ + Number ) ; v19 = get_mem_index ( @@a1@@ ) ; gen_aa32_st_i32 ( @@a1@@ , v48 , v51 , v19 , v18 ) ; } @@v20@@ += v23 ; tcg_gen_addi_i32 ( v51 , v51 , ( unsigned int ) ( Number << v25 ) ) ; } tcg_temp_free_i32 ( v51 ) ; tcg_temp_free_i32 ( v48 ) ; v21 = v40 << v25 ; LABEL_111 : if ( @@v35@@ != Number ) { @@v54@@ = load_reg ( @@a1@@ , @@v34@@ ) ; if ( @@v35@@ == Number ) { tcg_gen_addi_i32 ( @@v54@@ , @@v54@@ , v21 ) ; } else { @@v55@@ = load_reg ( @@a1@@ , @@v35@@ ) ; tcg_gen_add_i32 ( @@v54@@ , @@v54@@ , @@v55@@ ) ; tcg_temp_free_i32 ( @@v55@@ ) ; } store_reg ( @@a1@@ , @@v34@@ , @@v54@@ ) ; } return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "v36", "t": {"T": 1, "n": "int", "s": 4}, "location": "s100"}, {"n": "v35", "t": {"T": 1, "n": "int", "s": 4}, "location": "s108"}, {"n": "v34", "t": {"T": 1, "n": "int", "s": 4}, "location": "s112"}, {"n": "v33", "t": {"T": 1, "n": "int", "s": 4}, "location": "s116"}, {"n": "k", "t": {"T": 1, "n": "int", "s": 4}, "location": "s120"}, {"n": "v31", "t": {"T": 1, "n": "int", "s": 4}, "location": "s124"}, {"n": "j", "t": {"T": 1, "n": "int", "s": 4}, "location": "s128"}, {"n": "v20", "t": {"T": 1, "n": "int", "s": 4}, "location": "s144"}, {"n": "v55", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v54", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s32"}, {"n": "v53", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s40"}, {"n": "v52", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s48"}, {"n": "v46", "t": {"T": 1, "n": "int", "s": 4}, "location": "s68"}, {"n": "v45", "t": {"T": 1, "n": "int", "s": 4}, "location": "s72"}, {"n": "v44", "t": {"T": 1, "n": "int", "s": 4}, "location": "s76"}, {"n": "v43", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s80"}, {"n": "v42", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s84"}, {"n": "v41", "t": {"T": 1, "n": "int", "s": 4}, "location": "s88"}, {"n": "v37", "t": {"T": 1, "n": "int", "s": 4}, "location": "s96"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "insn", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r64"}, {"n": "mmu_idx", "t": {"T": 1, "n": "int", "s": 4}, "location": "s100"}, {"n": "rm", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "s108"}, {"n": "rn", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "s112"}, {"n": "reg_idx", "t": {"T": 1, "n": "int", "s": 4}, "location": "s116"}, {"n": "xs", "t": {"T": 1, "n": "int", "s": 4}, "location": "s120"}, {"n": "endian", "t": {"T": 1, "n": "MemOp_0", "s": 4}, "location": "s124"}, {"n": "n", "t": {"T": 1, "n": "int", "s": 4}, "location": "s128"}, {"n": "rd", "t": {"T": 1, "n": "int", "s": 4}, "location": "s144"}, {"n": "index", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s24"}, {"n": "base", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s32"}, {"n": "tmp2", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s40"}, {"n": "tmp64", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s48"}, {"n": "tt", "t": {"T": 1, "n": "int", "s": 4}, "location": "s68"}, {"n": "spacing", "t": {"T": 1, "n": "int", "s": 4}, "location": "s72"}, {"n": "interleave", "t": {"T": 1, "n": "int", "s": 4}, "location": "s76"}, {"n": "op", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s80"}, {"n": "vec_size", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s84"}, {"n": "a", "t": {"T": 1, "n": "int", "s": 4}, "location": "s88"}, {"n": "idx", "t": {"T": 1, "n": "int", "s": 4}, "location": "s96"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 965 |
[
"{\"name\": \"syn_simd_access_trap\", \"code\": \"__int64 __fastcall syn_simd_access_trap ( int @@a1@@ , int @@a2@@ , char @@a3@@ ) { int v3 ; if ( @@a3@@ ) v3 = Number ; else v3 = Number ; return ( @@a1@@ << Number ) | v3 | ( @@a2@@ << Number ) | Number ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_i64\", \"code\": \"__int64 __fastcall tcg_temp_free_i64 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i64_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_temp_new_i64\", \"code\": \"__int64 tcg_temp_new_i64 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i64 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_add_i32\", \"code\": \"__int64 __fastcall tcg_gen_add_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"get_mem_index\", \"code\": \"__int64 __fastcall get_mem_index ( __int64 @@a1@@ ) { return arm_to_core_mmu_idx ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_exception\", \"code\": \"__int64 __fastcall gen_exception ( unsigned int @@a1@@ , unsigned int @@a2@@ , unsigned int @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_const_i32 ( @@a1@@ ) ; @@v6@@ = tcg_const_i32 ( @@a2@@ ) ; @@v7@@ = tcg_const_i32 ( @@a3@@ ) ; gen_helper_exception_with_syndrome ( cpu_env , @@v5@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg_var\", \"code\": \"__int64 __fastcall load_reg_var ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ ) { int @@v3@@ ; if ( @@a3@@ != Number ) return tcg_gen_mov_i32 ( @@a2@@ , cpu_R [ @@a3@@ ] ) ; @@v3@@ = read_pc ( @@a1@@ ) ; return tcg_gen_movi_i32 ( @@a2@@ , @@v3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_aa32_ld_i32\", \"code\": \"__int64 __fastcall gen_aa32_ld_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ) @@a5@@ |= Number ; @@v9@@ = gen_aa32_addr ( @@a1@@ , @@a3@@ , @@a5@@ ) ; tcg_gen_qemu_ld_i32 ( @@a2@@ , @@v9@@ , @@a4@@ , @@a5@@ ) ; return tcg_temp_free_i64 ( @@v9@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_aa32_st_i32\", \"code\": \"__int64 __fastcall gen_aa32_st_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ) @@a5@@ |= Number ; @@v9@@ = gen_aa32_addr ( @@a1@@ , @@a3@@ , @@a5@@ ) ; tcg_gen_qemu_st_i32 ( @@a2@@ , @@v9@@ , @@a4@@ , @@a5@@ ) ; return tcg_temp_free_i64 ( @@v9@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_aa32_ld_i64\", \"code\": \"__int64 __fastcall gen_aa32_ld_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v8@@ ; @@v8@@ = gen_aa32_addr ( @@a1@@ , @@a3@@ , @@a5@@ ) ; tcg_gen_qemu_ld_i64 ( @@a2@@ , @@v8@@ , @@a4@@ , @@a5@@ ) ; gen_aa32_frob64 ( @@a1@@ , @@a2@@ ) ; return tcg_temp_free_i64 ( @@v8@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_aa32_st_i64\", \"code\": \"__int64 __fastcall gen_aa32_st_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v8@@ ; __int64 @@v9@@ ; @@v8@@ = gen_aa32_addr ( @@a1@@ , @@a3@@ , @@a5@@ ) ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { @@v9@@ = tcg_temp_new_i64 ( ) ; tcg_gen_rotri_i64 ( @@v9@@ , @@a2@@ , Number L ) ; tcg_gen_qemu_st_i64 ( @@v9@@ , @@v8@@ , @@a4@@ , @@a5@@ ) ; tcg_temp_free_i64 ( @@v9@@ ) ; } else { tcg_gen_qemu_st_i64 ( @@a2@@ , @@v8@@ , @@a4@@ , @@a5@@ ) ; } return tcg_temp_free_i64 ( @@v8@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_exception_insn\", \"code\": \"__int64 __fastcall gen_exception_insn ( __int64 @@a1@@ , int @@a2@@ , unsigned int @@a3@@ , unsigned int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@result@@ ; gen_set_condexec ( @@a1@@ ) ; gen_set_pc_im ( @@a1@@ , @@a2@@ ) ; gen_exception ( @@a3@@ , @@a4@@ , @@a5@@ ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_reg_offset\", \"code\": \"__int64 __fastcall neon_reg_offset ( int @@a1@@ , int @@a2@@ ) { return vfp_reg_offset ( Number , Number * @@a1@@ + @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"neon_load_element\", \"code\": \"__int64 __fastcall neon_load_element ( __int64 @@a1@@ , int @@a2@@ , int @@a3@@ , unsigned int @@a4@@ ) { __int64 @@v6@@ ; @@v6@@ = neon_element_offset ( @@a2@@ , @@a3@@ , @@a4@@ & Number ) ; if ( @@a4@@ == Number ) return tcg_gen_ld_i32 ( @@a1@@ , cpu_env , @@v6@@ ) ; if ( @@a4@@ > Number ) return g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; if ( @@a4@@ ) return tcg_gen_ld16u_i32 ( @@a1@@ , cpu_env , @@v6@@ ) ; return tcg_gen_ld8u_i32 ( @@a1@@ , cpu_env , @@v6@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_load_element64\", \"code\": \"__int64 __fastcall neon_load_element64 ( __int64 @@a1@@ , int @@a2@@ , int @@a3@@ , unsigned int @@a4@@ ) { __int64 @@v6@@ ; @@v6@@ = neon_element_offset ( @@a2@@ , @@a3@@ , @@a4@@ & Number ) ; if ( @@a4@@ == Number ) return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , @@v6@@ ) ; if ( @@a4@@ > Number ) return g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; if ( @@a4@@ == Number ) return tcg_gen_ld32u_i64 ( @@a1@@ , cpu_env , @@v6@@ ) ; if ( @@a4@@ ) return tcg_gen_ld16u_i64 ( @@a1@@ , cpu_env , @@v6@@ ) ; return tcg_gen_ld8u_i64 ( @@a1@@ , cpu_env , @@v6@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_store_element\", \"code\": \"__int64 __fastcall neon_store_element ( int @@a1@@ , int @@a2@@ , unsigned int @@a3@@ , __int64 @@a4@@ ) { __int64 @@v7@@ ; @@v7@@ = neon_element_offset ( @@a1@@ , @@a2@@ , @@a3@@ ) ; if ( @@a3@@ == Number ) return tcg_gen_st_i32 ( @@a4@@ , cpu_env , @@v7@@ ) ; if ( @@a3@@ > Number ) return g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; if ( @@a3@@ ) return tcg_gen_st16_i32 ( @@a4@@ , cpu_env , @@v7@@ ) ; return tcg_gen_st8_i32 ( @@a4@@ , cpu_env , @@v7@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_store_element64\", \"code\": \"__int64 __fastcall neon_store_element64 ( int @@a1@@ , int @@a2@@ , unsigned int @@a3@@ , __int64 @@a4@@ ) { __int64 @@v7@@ ; @@v7@@ = neon_element_offset ( @@a1@@ , @@a2@@ , @@a3@@ ) ; if ( @@a3@@ == Number ) return tcg_gen_st_i64 ( @@a4@@ , cpu_env , @@v7@@ ) ; if ( @@a3@@ > Number ) return g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; if ( @@a3@@ == Number ) return tcg_gen_st32_i64 ( @@a4@@ , cpu_env , @@v7@@ ) ; if ( @@a3@@ ) return tcg_gen_st16_i64 ( @@a4@@ , cpu_env , @@v7@@ ) ; return tcg_gen_st8_i64 ( @@a4@@ , cpu_env , @@v7@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_neon_narrow", "code": "__int64 __fastcall gen_neon_narrow ( int @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { if ( @@a1@@ == Number ) return tcg_gen_extrl_i64_i32 ( @@a2@@ , @@a3@@ ) ; if ( @@a1@@ > Number ) goto LABEL_9 ; if ( ! @@a1@@ ) return gen_helper_neon_narrow_u8 ( @@a2@@ , @@a3@@ ) ; if ( @@a1@@ != Number ) LABEL_9 : abort ( ) ; return gen_helper_neon_narrow_u16 ( @@a2@@ , @@a3@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "src", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r16"}, {"n": "size", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "dest", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 966 |
[
"{\"name\": \"gen_helper_neon_narrow_u8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_narrow_u8 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i64_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_narrow_u8 , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_narrow_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_narrow_u16 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i64_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_narrow_u16 , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_neon_narrow_sats", "code": "unsigned __int64 __fastcall gen_neon_narrow_sats ( int @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { if ( @@a1@@ == Number ) return gen_helper_neon_narrow_sat_s32 ( @@a2@@ , cpu_env , @@a3@@ ) ; if ( @@a1@@ > Number ) goto LABEL_9 ; if ( ! @@a1@@ ) return gen_helper_neon_narrow_sat_s8 ( @@a2@@ , cpu_env , @@a3@@ ) ; if ( @@a1@@ != Number ) LABEL_9 : abort ( ) ; return gen_helper_neon_narrow_sat_s16 ( @@a2@@ , cpu_env , @@a3@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "src", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r16"}, {"n": "size", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "dest", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 967 |
[
"{\"name\": \"gen_helper_neon_narrow_sat_s8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_narrow_sat_s8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_narrow_sat_s8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_narrow_sat_s16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_narrow_sat_s16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_narrow_sat_s16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_narrow_sat_s32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_narrow_sat_s32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_narrow_sat_s32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_neon_narrow\", \"code\": \"__int64 __fastcall gen_neon_narrow ( int @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { if ( @@a1@@ == Number ) return tcg_gen_extrl_i64_i32 ( @@a2@@ , @@a3@@ ) ; if ( @@a1@@ > Number ) goto LABEL_9 ; if ( ! @@a1@@ ) return gen_helper_neon_narrow_u8 ( @@a2@@ , @@a3@@ ) ; if ( @@a1@@ != Number ) LABEL_9 : abort ( ) ; return gen_helper_neon_narrow_u16 ( @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "gen_neon_narrow_satu", "code": "unsigned __int64 __fastcall gen_neon_narrow_satu ( int @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { if ( @@a1@@ == Number ) return gen_helper_neon_narrow_sat_u32 ( @@a2@@ , cpu_env , @@a3@@ ) ; if ( @@a1@@ > Number ) goto LABEL_9 ; if ( ! @@a1@@ ) return gen_helper_neon_narrow_sat_u8 ( @@a2@@ , cpu_env , @@a3@@ ) ; if ( @@a1@@ != Number ) LABEL_9 : abort ( ) ; return gen_helper_neon_narrow_sat_u16 ( @@a2@@ , cpu_env , @@a3@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "src", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r16"}, {"n": "size", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "dest", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 968 |
[
"{\"name\": \"gen_helper_neon_narrow_sat_u8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_narrow_sat_u8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_narrow_sat_u8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_narrow_sat_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_narrow_sat_u16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_narrow_sat_u16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_narrow_sat_u32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_narrow_sat_u32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_narrow_sat_u32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_neon_narrow\", \"code\": \"__int64 __fastcall gen_neon_narrow ( int @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { if ( @@a1@@ == Number ) return tcg_gen_extrl_i64_i32 ( @@a2@@ , @@a3@@ ) ; if ( @@a1@@ > Number ) goto LABEL_9 ; if ( ! @@a1@@ ) return gen_helper_neon_narrow_u8 ( @@a2@@ , @@a3@@ ) ; if ( @@a1@@ != Number ) LABEL_9 : abort ( ) ; return gen_helper_neon_narrow_u16 ( @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "gen_neon_unarrow_sats", "code": "unsigned __int64 __fastcall gen_neon_unarrow_sats ( int @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { if ( @@a1@@ == Number ) return gen_helper_neon_unarrow_sat32 ( @@a2@@ , cpu_env , @@a3@@ ) ; if ( @@a1@@ > Number ) goto LABEL_9 ; if ( ! @@a1@@ ) return gen_helper_neon_unarrow_sat8 ( @@a2@@ , cpu_env , @@a3@@ ) ; if ( @@a1@@ != Number ) LABEL_9 : abort ( ) ; return gen_helper_neon_unarrow_sat16 ( @@a2@@ , cpu_env , @@a3@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "src", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r16"}, {"n": "size", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "dest", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 969 |
[
"{\"name\": \"gen_helper_neon_unarrow_sat8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_unarrow_sat8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_unarrow_sat8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_unarrow_sat16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_unarrow_sat16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_unarrow_sat16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_unarrow_sat32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_unarrow_sat32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_unarrow_sat32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_neon_shift_narrow", "code": "unsigned __int64 __fastcall gen_neon_shift_narrow ( int @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , int @@a5@@ ) { unsigned __int64 @@result@@ ; if ( @@a4@@ ) { if ( @@a5@@ ) { if ( @@a1@@ == Number ) { @@result@@ = gen_helper_neon_rshl_u16 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; } else { if ( @@a1@@ != Number ) abort ( ) ; @@result@@ = gen_helper_neon_rshl_u32 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; } } else if ( @@a1@@ == Number ) { @@result@@ = gen_helper_neon_rshl_s16 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; } else { if ( @@a1@@ != Number ) abort ( ) ; @@result@@ = gen_helper_neon_rshl_s32 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; } } else if ( @@a5@@ ) { if ( @@a1@@ == Number ) { @@result@@ = gen_helper_neon_shl_u16 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; } else { if ( @@a1@@ != Number ) abort ( ) ; @@result@@ = gen_helper_neon_shl_u32 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; } } else if ( @@a1@@ == Number ) { @@result@@ = gen_helper_neon_shl_s16 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; } else { if ( @@a1@@ != Number ) abort ( ) ; @@result@@ = gen_helper_neon_shl_s32 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; } return @@result@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "a5", "t": {"T": 1, "n": "int", "s": 4}, "location": "r72"}, {"n": "result", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "r8"}]}
|
[{"n": "shift", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "q", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "size", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "var", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}, {"n": "u", "t": {"T": 1, "n": "int", "s": 4}, "location": "r72"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 970 |
[
"{\"name\": \"gen_helper_neon_shl_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_shl_u16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_shl_u16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_shl_s16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_shl_s16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_shl_s16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_shl_u32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_shl_u32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_shl_u32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_shl_s32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_shl_s32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_shl_s32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_rshl_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_rshl_u16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_rshl_u16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_rshl_s16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_rshl_s16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_rshl_s16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_rshl_u32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_rshl_u32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_rshl_u32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_rshl_s32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_rshl_s32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_rshl_s32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_neon_widen", "code": "__int64 __fastcall gen_neon_widen ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ , int @@a4@@ ) { if ( ! @@a4@@ ) { if ( @@a3@@ == Number ) { tcg_gen_ext_i32_i64 ( @@a1@@ , @@a2@@ ) ; return tcg_temp_free_i32 ( @@a2@@ ) ; } if ( @@a3@@ <= Number ) { if ( ! @@a3@@ ) { gen_helper_neon_widen_s8 ( @@a1@@ , @@a2@@ ) ; return tcg_temp_free_i32 ( @@a2@@ ) ; } if ( @@a3@@ == Number ) { gen_helper_neon_widen_s16 ( @@a1@@ , @@a2@@ ) ; return tcg_temp_free_i32 ( @@a2@@ ) ; } } abort ( ) ; } if ( @@a3@@ == Number ) { tcg_gen_extu_i32_i64 ( @@a1@@ , @@a2@@ ) ; } else { if ( @@a3@@ > Number ) goto LABEL_10 ; if ( @@a3@@ ) { if ( @@a3@@ != Number ) LABEL_10 : abort ( ) ; gen_helper_neon_widen_u16 ( @@a1@@ , @@a2@@ ) ; } else { gen_helper_neon_widen_u8 ( @@a1@@ , @@a2@@ ) ; } } return tcg_temp_free_i32 ( @@a2@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "size", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "u", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "dest", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r56"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 971 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_helper_neon_widen_u8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_widen_u8 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i32_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_widen_u8 , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_widen_s8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_widen_s8 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i32_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_widen_s8 , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_widen_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_widen_u16 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i32_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_widen_u16 , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_widen_s16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_widen_s16 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i32_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_widen_s16 , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_neon_addl", "code": "__int64 __fastcall gen_neon_addl ( int @@a1@@ ) { if ( @@a1@@ == Number ) return tcg_gen_add_i64 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; if ( @@a1@@ > Number ) goto LABEL_9 ; if ( ! @@a1@@ ) return gen_helper_neon_addl_u16 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; if ( @@a1@@ != Number ) LABEL_9 : abort ( ) ; return gen_helper_neon_addl_u32 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "size", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 972 |
[
"{\"name\": \"gen_helper_neon_addl_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_addl_u16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_addl_u16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_addl_u32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_addl_u32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_addl_u32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_add_i64\", \"code\": \"__int64 __fastcall tcg_gen_add_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_neon_add\", \"code\": \"__int64 __fastcall gen_neon_add ( int @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { if ( @@a1@@ == Number ) return tcg_gen_add_i32 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; if ( @@a1@@ > Number ) goto LABEL_9 ; if ( ! @@a1@@ ) return gen_helper_neon_add_u8 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; if ( @@a1@@ != Number ) LABEL_9 : abort ( ) ; return gen_helper_neon_add_u16 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "gen_neon_subl", "code": "__int64 __fastcall gen_neon_subl ( int @@a1@@ ) { if ( @@a1@@ == Number ) return tcg_gen_sub_i64 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; if ( @@a1@@ > Number ) goto LABEL_9 ; if ( ! @@a1@@ ) return gen_helper_neon_subl_u16 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; if ( @@a1@@ != Number ) LABEL_9 : abort ( ) ; return gen_helper_neon_subl_u32 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "size", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 973 |
[
"{\"name\": \"gen_helper_neon_subl_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_subl_u16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_subl_u16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_subl_u32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_subl_u32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_subl_u32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_sub_i64\", \"code\": \"__int64 __fastcall tcg_gen_sub_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "gen_neon_negl", "code": "__int64 __fastcall gen_neon_negl ( __int64 @@a1@@ , int @@a2@@ ) { if ( @@a2@@ == Number ) return tcg_gen_neg_i64 ( @@a1@@ , @@a1@@ ) ; if ( @@a2@@ > Number ) goto LABEL_9 ; if ( ! @@a2@@ ) return gen_helper_neon_negl_u16 ( @@a1@@ , @@a1@@ ) ; if ( @@a2@@ != Number ) LABEL_9 : abort ( ) ; return gen_helper_neon_negl_u32 ( @@a1@@ , @@a1@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}]}
|
[{"n": "var", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r56"}, {"n": "size", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 974 |
[
"{\"name\": \"gen_helper_neon_negl_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_negl_u16 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i64_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_negl_u16 , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_negl_u32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_negl_u32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i64_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_negl_u32 , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_neg_i64\", \"code\": \"__int64 __fastcall tcg_gen_neg_i64 ( __int64 @@a1@@ , __int64 @@a2@@ ) { return tcg_gen_op2_i64 ( Number , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "gen_neon_addl_saturate", "code": "unsigned __int64 __fastcall gen_neon_addl_saturate ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ ) { if ( @@a3@@ == Number ) return gen_helper_neon_addl_saturate_s32 ( @@a1@@ , cpu_env , @@a1@@ , @@a2@@ ) ; if ( @@a3@@ != Number ) abort ( ) ; return gen_helper_neon_addl_saturate_s64 ( @@a1@@ , cpu_env , @@a1@@ , @@a2@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "size", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "op0", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r56"}, {"n": "op1", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 975 |
[
"{\"name\": \"gen_helper_neon_addl_saturate_s32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_addl_saturate_s32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_addl_saturate_s32 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_addl_saturate_s64\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_addl_saturate_s64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_addl_saturate_s64 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_neon_add\", \"code\": \"__int64 __fastcall gen_neon_add ( int @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { if ( @@a1@@ == Number ) return tcg_gen_add_i32 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; if ( @@a1@@ > Number ) goto LABEL_9 ; if ( ! @@a1@@ ) return gen_helper_neon_add_u8 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; if ( @@a1@@ != Number ) LABEL_9 : abort ( ) ; return gen_helper_neon_add_u16 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_neon_addl\", \"code\": \"__int64 __fastcall gen_neon_addl ( int @@a1@@ ) { if ( @@a1@@ == Number ) return tcg_gen_add_i64 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; if ( @@a1@@ > Number ) goto LABEL_9 ; if ( ! @@a1@@ ) return gen_helper_neon_addl_u16 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; if ( @@a1@@ != Number ) LABEL_9 : abort ( ) ; return gen_helper_neon_addl_u32 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}"
] |
{"name": "gen_neon_mull", "code": "unsigned __int64 __fastcall gen_neon_mull ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , int @@a5@@ ) { unsigned __int64 @@result@@ ; __int64 v8 ; __int64 v9 ; switch ( @@a5@@ | ( Number * @@a4@@ ) ) { case Number : @@result@@ = gen_helper_neon_mull_s8 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; break ; case Number : @@result@@ = gen_helper_neon_mull_u8 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; break ; case Number : @@result@@ = gen_helper_neon_mull_s16 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; break ; case Number : @@result@@ = gen_helper_neon_mull_u16 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; break ; case Number : v8 = gen_muls_i64_i32 ( @@a2@@ , @@a3@@ ) ; tcg_gen_mov_i64 ( @@a1@@ , v8 ) ; @@result@@ = tcg_temp_free_i64 ( v8 ) ; break ; case Number : v9 = gen_mulu_i64_i32 ( @@a2@@ , @@a3@@ ) ; tcg_gen_mov_i64 ( @@a1@@ , v9 ) ; @@result@@ = tcg_temp_free_i64 ( v9 ) ; break ; default : abort ( ) ; } if ( @@a4@@ <= Number ) { tcg_temp_free_i32 ( @@a2@@ ) ; @@result@@ = tcg_temp_free_i32 ( @@a3@@ ) ; } return @@result@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "a5", "t": {"T": 1, "n": "int", "s": 4}, "location": "r72"}, {"n": "result", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "r8"}]}
|
[{"n": "b", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "size", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "dest", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r56"}, {"n": "a", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}, {"n": "u", "t": {"T": 1, "n": "int", "s": 4}, "location": "r72"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 976 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_i64\", \"code\": \"__int64 __fastcall tcg_temp_free_i64 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i64_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_helper_neon_mull_u8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_mull_u8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_mull_u8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_mull_s8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_mull_s8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_mull_s8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_mull_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_mull_u16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_mull_u16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_mull_s16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_mull_s16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_mull_s16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_mov_i64\", \"code\": \"__int64 __fastcall tcg_gen_mov_i64 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@result@@ ; @@result@@ = @@a1@@ ; if ( @@a1@@ != @@a2@@ ) @@result@@ = tcg_gen_op2_i64 ( Number , @@a1@@ , @@a2@@ ) ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_mulu_i64_i32\", \"code\": \"__int64 __fastcall gen_mulu_i64_i32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; __int64 @@v5@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; @@v4@@ = tcg_temp_new_i32 ( ) ; tcg_gen_mulu2_i32 ( @@v3@@ , @@v4@@ , @@a1@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@a1@@ ) ; tcg_temp_free_i32 ( @@a2@@ ) ; @@v5@@ = tcg_temp_new_i64 ( ) ; tcg_gen_concat_i32_i64 ( @@v5@@ , @@v3@@ , @@v4@@ ) ; tcg_temp_free_i32 ( @@v3@@ ) ; tcg_temp_free_i32 ( @@v4@@ ) ; return @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_muls_i64_i32\", \"code\": \"__int64 __fastcall gen_muls_i64_i32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; __int64 @@v5@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; @@v4@@ = tcg_temp_new_i32 ( ) ; tcg_gen_muls2_i32 ( @@v3@@ , @@v4@@ , @@a1@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@a1@@ ) ; tcg_temp_free_i32 ( @@a2@@ ) ; @@v5@@ = tcg_temp_new_i64 ( ) ; tcg_gen_concat_i32_i64 ( @@v5@@ , @@v3@@ , @@v4@@ ) ; tcg_temp_free_i32 ( @@v3@@ ) ; tcg_temp_free_i32 ( @@v4@@ ) ; return @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_neon_narrow_op", "code": "unsigned __int64 __fastcall gen_neon_narrow_op ( int @@a1@@ , int @@a2@@ , int @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ ) { unsigned __int64 @@result@@ ; if ( @@a1@@ ) { if ( @@a2@@ ) @@result@@ = gen_neon_unarrow_sats ( @@a3@@ , @@a4@@ , @@a5@@ ) ; else @@result@@ = gen_neon_narrow ( @@a3@@ , @@a4@@ , @@a5@@ ) ; } else if ( @@a2@@ ) { @@result@@ = gen_neon_narrow_satu ( @@a3@@ , @@a4@@ , @@a5@@ ) ; } else { @@result@@ = gen_neon_narrow_sats ( @@a3@@ , @@a4@@ , @@a5@@ ) ; } return @@result@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "a5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r72"}, {"n": "result", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "r8"}]}
|
[{"n": "size", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "dest", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r24"}, {"n": "op", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "u", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "src", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r72"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 977 |
[
"{\"name\": \"gen_neon_narrow\", \"code\": \"__int64 __fastcall gen_neon_narrow ( int @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { if ( @@a1@@ == Number ) return tcg_gen_extrl_i64_i32 ( @@a2@@ , @@a3@@ ) ; if ( @@a1@@ > Number ) goto LABEL_9 ; if ( ! @@a1@@ ) return gen_helper_neon_narrow_u8 ( @@a2@@ , @@a3@@ ) ; if ( @@a1@@ != Number ) LABEL_9 : abort ( ) ; return gen_helper_neon_narrow_u16 ( @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_neon_narrow_sats\", \"code\": \"unsigned __int64 __fastcall gen_neon_narrow_sats ( int @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { if ( @@a1@@ == Number ) return gen_helper_neon_narrow_sat_s32 ( @@a2@@ , cpu_env , @@a3@@ ) ; if ( @@a1@@ > Number ) goto LABEL_9 ; if ( ! @@a1@@ ) return gen_helper_neon_narrow_sat_s8 ( @@a2@@ , cpu_env , @@a3@@ ) ; if ( @@a1@@ != Number ) LABEL_9 : abort ( ) ; return gen_helper_neon_narrow_sat_s16 ( @@a2@@ , cpu_env , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_neon_narrow_satu\", \"code\": \"unsigned __int64 __fastcall gen_neon_narrow_satu ( int @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { if ( @@a1@@ == Number ) return gen_helper_neon_narrow_sat_u32 ( @@a2@@ , cpu_env , @@a3@@ ) ; if ( @@a1@@ > Number ) goto LABEL_9 ; if ( ! @@a1@@ ) return gen_helper_neon_narrow_sat_u8 ( @@a2@@ , cpu_env , @@a3@@ ) ; if ( @@a1@@ != Number ) LABEL_9 : abort ( ) ; return gen_helper_neon_narrow_sat_u16 ( @@a2@@ , cpu_env , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_neon_unarrow_sats\", \"code\": \"unsigned __int64 __fastcall gen_neon_unarrow_sats ( int @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { if ( @@a1@@ == Number ) return gen_helper_neon_unarrow_sat32 ( @@a2@@ , cpu_env , @@a3@@ ) ; if ( @@a1@@ > Number ) goto LABEL_9 ; if ( ! @@a1@@ ) return gen_helper_neon_unarrow_sat8 ( @@a2@@ , cpu_env , @@a3@@ ) ; if ( @@a1@@ != Number ) LABEL_9 : abort ( ) ; return gen_helper_neon_unarrow_sat16 ( @@a2@@ , cpu_env , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "neon_2rm_is_v8_op", "code": "_BOOL8 __fastcall neon_2rm_is_v8_op ( unsigned int @@a1@@ ) { return @@a1@@ <= Number && ( ( Number L << @@a1@@ ) & Number ) != Number ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}]}
|
[{"n": "op", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 978 |
[] |
{"name": "do_v81_helper", "code": "__int64 __fastcall do_v81_helper ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ , unsigned int @@a4@@ , unsigned int @@a5@@ , unsigned int @@a6@@ ) { __int64 @@v6@@ ; unsigned int @@v7@@ ; unsigned int @@v8@@ ; unsigned int @@v9@@ ; if ( ! isar_feature_aa32_rdm ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v6@@ = cpu_env ; @@v7@@ = vfp_reg_offset ( Number , @@a6@@ ) ; @@v8@@ = vfp_reg_offset ( Number , @@a5@@ ) ; @@v9@@ = vfp_reg_offset ( Number , @@a4@@ ) ; tcg_gen_gvec_3_ptr ( @@v9@@ , @@v8@@ , @@v7@@ , @@v6@@ , ( unsigned int ) ( Number * ( @@a3@@ + Number ) ) , ( unsigned int ) ( Number * ( @@a3@@ + Number ) ) , Number L , @@a2@@ ) ; return Number L ; }", "source": [{"n": "v8", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r120"}, {"n": "v7", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r128"}, {"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r24"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r32"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "a5", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r72"}, {"n": "v9", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r8"}, {"n": "a6", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r80"}]}
|
[{"n": "v8", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r120"}, {"n": "v7", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r128"}, {"n": "q", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "rd", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "v6", "t": {"T": 1, "n": "TCGv_ptr", "s": 8}, "location": "r32"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "fn", "t": {"T": 9, "n": "gen_helper_gvec_3_ptr *"}, "location": "r64"}, {"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r72"}, {"n": "v9", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r8"}, {"n": "rm", "t": {"T": 1, "n": "int", "s": 4}, "location": "r80"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 979 |
[
"{\"name\": \"isar_feature_aa32_rdm\", \"code\": \"bool __fastcall isar_feature_aa32_rdm ( __int64 @@a1@@ ) { return ( unsigned int ) extract32 ( * ( _DWORD * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"vfp_reg_offset\", \"code\": \"__int64 __fastcall vfp_reg_offset ( char @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v3@@ ; if ( @@a1@@ ) return Number * ( Number * ( ( @@a2@@ >> Number ) + Number L ) + ( @@a2@@ & Number ) ) ; @@v3@@ = Number * ( Number * ( ( @@a2@@ >> Number ) + Number L ) + ( ( @@a2@@ >> Number ) & Number ) ) ; if ( ( @@a2@@ & Number ) != Number ) @@v3@@ += Number L ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_ssra8_i64", "code": "__int64 __fastcall gen_ssra8_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { tcg_gen_vec_sar8i_i64 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; return tcg_gen_vec_add8_i64 ( @@a1@@ , @@a1@@ , @@a2@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "shift", "t": {"T": 1, "n": "int64_t", "s": 8}, "location": "r16"}, {"n": "d", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r56"}, {"n": "a", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 980 |
[] |
{"name": "gen_ssra16_i64", "code": "__int64 __fastcall gen_ssra16_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { tcg_gen_vec_sar16i_i64 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; return tcg_gen_vec_add16_i64 ( @@a1@@ , @@a1@@ , @@a2@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "shift", "t": {"T": 1, "n": "int64_t", "s": 8}, "location": "r16"}, {"n": "d", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r56"}, {"n": "a", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 981 |
[] |
{"name": "gen_ssra32_i32", "code": "__int64 __fastcall gen_ssra32_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , unsigned int @@a3@@ ) { tcg_gen_sari_i32 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; return tcg_gen_add_i32 ( @@a1@@ , @@a1@@ , @@a2@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "shift", "t": {"T": 1, "n": "int32_t", "s": 4}, "location": "r16"}, {"n": "d", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "a", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 982 |
[
"{\"name\": \"tcg_gen_add_i32\", \"code\": \"__int64 __fastcall tcg_gen_add_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_sar\", \"code\": \"__int64 __fastcall gen_sar ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v5@@ , @@v5@@ , @@v6@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; tcg_gen_sar_i32 ( @@a1@@ , @@a2@@ , @@v5@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_ssra64_i64", "code": "__int64 __fastcall gen_ssra64_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { tcg_gen_sari_i64 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; return tcg_gen_add_i64 ( @@a1@@ , @@a1@@ , @@a2@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "shift", "t": {"T": 1, "n": "int64_t", "s": 8}, "location": "r16"}, {"n": "d", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r56"}, {"n": "a", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 983 |
[
"{\"name\": \"tcg_gen_add_i64\", \"code\": \"__int64 __fastcall tcg_gen_add_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_sar\", \"code\": \"__int64 __fastcall gen_sar ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v5@@ , @@v5@@ , @@v6@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; tcg_gen_sar_i32 ( @@a1@@ , @@a2@@ , @@v5@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_ssra_vec", "code": "__int64 __fastcall gen_ssra_vec ( unsigned int @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { tcg_gen_sari_vec ( @@a1@@ , @@a3@@ , @@a3@@ , @@a4@@ ) ; return tcg_gen_add_vec ( @@a1@@ , @@a2@@ , @@a2@@ , @@a3@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "a", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r16"}, {"n": "sh", "t": {"T": 1, "n": "int64_t", "s": 8}, "location": "r24"}, {"n": "vece", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "d", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 984 |
[
"{\"name\": \"gen_sar\", \"code\": \"__int64 __fastcall gen_sar ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v5@@ , @@v5@@ , @@v6@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; tcg_gen_sar_i32 ( @@a1@@ , @@a2@@ , @@v5@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_usra8_i64", "code": "__int64 __fastcall gen_usra8_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { tcg_gen_vec_shr8i_i64 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; return tcg_gen_vec_add8_i64 ( @@a1@@ , @@a1@@ , @@a2@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "shift", "t": {"T": 1, "n": "int64_t", "s": 8}, "location": "r16"}, {"n": "d", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r56"}, {"n": "a", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 985 |
[] |
{"name": "gen_usra16_i64", "code": "__int64 __fastcall gen_usra16_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { tcg_gen_vec_shr16i_i64 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; return tcg_gen_vec_add16_i64 ( @@a1@@ , @@a1@@ , @@a2@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "shift", "t": {"T": 1, "n": "int64_t", "s": 8}, "location": "r16"}, {"n": "d", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r56"}, {"n": "a", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 986 |
[] |
{"name": "gen_usra32_i32", "code": "__int64 __fastcall gen_usra32_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , unsigned int @@a3@@ ) { tcg_gen_shri_i32 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; return tcg_gen_add_i32 ( @@a1@@ , @@a1@@ , @@a2@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "shift", "t": {"T": 1, "n": "int32_t", "s": 4}, "location": "r16"}, {"n": "d", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "a", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 987 |
[
"{\"name\": \"tcg_gen_add_i32\", \"code\": \"__int64 __fastcall tcg_gen_add_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_shr\", \"code\": \"__int64 __fastcall gen_shr ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shr_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_usra64_i64", "code": "__int64 __fastcall gen_usra64_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { tcg_gen_shri_i64 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; return tcg_gen_add_i64 ( @@a1@@ , @@a1@@ , @@a2@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "shift", "t": {"T": 1, "n": "int64_t", "s": 8}, "location": "r16"}, {"n": "d", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r56"}, {"n": "a", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 988 |
[
"{\"name\": \"tcg_gen_add_i64\", \"code\": \"__int64 __fastcall tcg_gen_add_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_shr\", \"code\": \"__int64 __fastcall gen_shr ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shr_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_usra_vec", "code": "__int64 __fastcall gen_usra_vec ( unsigned int @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { tcg_gen_shri_vec ( @@a1@@ , @@a3@@ , @@a3@@ , @@a4@@ ) ; return tcg_gen_add_vec ( @@a1@@ , @@a2@@ , @@a2@@ , @@a3@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "a", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r16"}, {"n": "sh", "t": {"T": 1, "n": "int64_t", "s": 8}, "location": "r24"}, {"n": "vece", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "d", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 989 |
[
"{\"name\": \"gen_shr\", \"code\": \"__int64 __fastcall gen_shr ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shr_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_shr8_ins_i64", "code": "__int64 __fastcall gen_shr8_ins_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v6@@ ; __int64 @@v7@@ ; @@v6@@ = Number * ( unsigned __int8 ) ( Number >> @@a3@@ ) ; @@v7@@ = tcg_temp_new_i64 ( ) ; tcg_gen_shri_i64 ( @@v7@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_andi_i64 ( @@v7@@ , @@v7@@ , @@v6@@ ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , ~ @@v6@@ ) ; tcg_gen_or_i64 ( @@a1@@ , @@a1@@ , @@v7@@ ) ; return tcg_temp_free_i64 ( @@v7@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "shift", "t": {"T": 1, "n": "int64_t", "s": 8}, "location": "r16"}, {"n": "d", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r56"}, {"n": "a", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r64"}, {"n": "mask", "t": {"T": 1, "n": "uint64_t", "s": 8}, "location": "s16"}, {"n": "t", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 990 |
[
"{\"name\": \"tcg_temp_free_i64\", \"code\": \"__int64 __fastcall tcg_temp_free_i64 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i64_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i64\", \"code\": \"__int64 tcg_temp_new_i64 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i64 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_or_i64\", \"code\": \"__int64 __fastcall tcg_gen_or_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_shr\", \"code\": \"__int64 __fastcall gen_shr ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shr_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_shr16_ins_i64", "code": "__int64 __fastcall gen_shr16_ins_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v6@@ ; __int64 @@v7@@ ; @@v6@@ = Number * ( unsigned __int16 ) ( Number >> @@a3@@ ) ; @@v7@@ = tcg_temp_new_i64 ( ) ; tcg_gen_shri_i64 ( @@v7@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_andi_i64 ( @@v7@@ , @@v7@@ , @@v6@@ ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , ~ @@v6@@ ) ; tcg_gen_or_i64 ( @@a1@@ , @@a1@@ , @@v7@@ ) ; return tcg_temp_free_i64 ( @@v7@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "shift", "t": {"T": 1, "n": "int64_t", "s": 8}, "location": "r16"}, {"n": "d", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r56"}, {"n": "a", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r64"}, {"n": "mask", "t": {"T": 1, "n": "uint64_t", "s": 8}, "location": "s16"}, {"n": "t", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 991 |
[
"{\"name\": \"tcg_temp_free_i64\", \"code\": \"__int64 __fastcall tcg_temp_free_i64 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i64_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i64\", \"code\": \"__int64 tcg_temp_new_i64 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i64 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_or_i64\", \"code\": \"__int64 __fastcall tcg_gen_or_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_shr\", \"code\": \"__int64 __fastcall gen_shr ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shr_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_shr32_ins_i32", "code": "__int64 __fastcall gen_shr32_ins_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , unsigned int @@a3@@ ) { tcg_gen_shri_i32 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; return tcg_gen_deposit_i32 ( @@a1@@ , @@a1@@ , @@a2@@ , Number L , Number - @@a3@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "shift", "t": {"T": 1, "n": "int32_t", "s": 4}, "location": "r16"}, {"n": "d", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "a", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 992 |
[
"{\"name\": \"gen_shr\", \"code\": \"__int64 __fastcall gen_shr ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shr_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_shr64_ins_i64", "code": "__int64 __fastcall gen_shr64_ins_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { int @@v4@@ ; @@v4@@ = @@a3@@ ; tcg_gen_shri_i64 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; return tcg_gen_deposit_i64 ( @@a1@@ , @@a1@@ , @@a2@@ , Number L , ( unsigned int ) ( Number - @@v4@@ ) ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "int", "s": 4}, "location": "s24"}]}
|
[{"n": "shift", "t": {"T": 1, "n": "int64_t", "s": 8}, "location": "r16"}, {"n": "d", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r56"}, {"n": "a", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r64"}, {"n": "shifta", "t": {"T": 1, "n": "int", "s": 4}, "location": "s24"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 993 |
[
"{\"name\": \"gen_shr\", \"code\": \"__int64 __fastcall gen_shr ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shr_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_shr_ins_vec", "code": "__int64 __fastcall gen_shr_ins_vec ( unsigned int @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v7@@ ; __int64 @@v8@@ ; if ( ! @@a4@@ ) return tcg_gen_mov_vec ( @@a2@@ , @@a3@@ ) ; @@v7@@ = tcg_temp_new_vec_matching ( @@a2@@ ) ; @@v8@@ = tcg_temp_new_vec_matching ( @@a2@@ ) ; tcg_gen_dupi_vec ( @@a1@@ , @@v8@@ , Number >> ( Number - ( unsigned __int8 ) @@a4@@ ) << ( ( unsigned __int8 ) ( Number << @@a1@@ ) - ( unsigned __int8 ) @@a4@@ ) ) ; tcg_gen_shri_vec ( @@a1@@ , @@v7@@ , @@a3@@ , @@a4@@ ) ; tcg_gen_and_vec ( @@a1@@ , @@a2@@ , @@a2@@ , @@v8@@ ) ; tcg_gen_or_vec ( @@a1@@ , @@a2@@ , @@a2@@ , @@v7@@ ) ; tcg_temp_free_vec ( @@v7@@ ) ; return tcg_temp_free_vec ( @@v8@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v8", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "a", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r16"}, {"n": "sh", "t": {"T": 1, "n": "int64_t", "s": 8}, "location": "r24"}, {"n": "vece", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "d", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r64"}, {"n": "t", "t": {"T": 3, "t": "TCGv_vec_d"}, "location": "s16"}, {"n": "m", "t": {"T": 3, "t": "TCGv_vec_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 994 |
[
"{\"name\": \"tcg_temp_free_vec\", \"code\": \"__int64 __fastcall tcg_temp_free_vec ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_vec_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_shr\", \"code\": \"__int64 __fastcall gen_shr ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shr_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_shl8_ins_i64", "code": "__int64 __fastcall gen_shl8_ins_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v6@@ ; __int64 @@v7@@ ; @@v6@@ = Number * ( unsigned __int8 ) ( Number << @@a3@@ ) ; @@v7@@ = tcg_temp_new_i64 ( ) ; tcg_gen_shli_i64 ( @@v7@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_andi_i64 ( @@v7@@ , @@v7@@ , @@v6@@ ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , ~ @@v6@@ ) ; tcg_gen_or_i64 ( @@a1@@ , @@a1@@ , @@v7@@ ) ; return tcg_temp_free_i64 ( @@v7@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "shift", "t": {"T": 1, "n": "int64_t", "s": 8}, "location": "r16"}, {"n": "d", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r56"}, {"n": "a", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r64"}, {"n": "mask", "t": {"T": 1, "n": "uint64_t", "s": 8}, "location": "s16"}, {"n": "t", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 995 |
[
"{\"name\": \"tcg_temp_free_i64\", \"code\": \"__int64 __fastcall tcg_temp_free_i64 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i64_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i64\", \"code\": \"__int64 tcg_temp_new_i64 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i64 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_or_i64\", \"code\": \"__int64 __fastcall tcg_gen_or_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_shl\", \"code\": \"__int64 __fastcall gen_shl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shl_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_shl16_ins_i64", "code": "__int64 __fastcall gen_shl16_ins_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v6@@ ; __int64 @@v7@@ ; @@v6@@ = Number * ( unsigned __int16 ) ( Number << @@a3@@ ) ; @@v7@@ = tcg_temp_new_i64 ( ) ; tcg_gen_shli_i64 ( @@v7@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_andi_i64 ( @@v7@@ , @@v7@@ , @@v6@@ ) ; tcg_gen_andi_i64 ( @@a1@@ , @@a1@@ , ~ @@v6@@ ) ; tcg_gen_or_i64 ( @@a1@@ , @@a1@@ , @@v7@@ ) ; return tcg_temp_free_i64 ( @@v7@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "shift", "t": {"T": 1, "n": "int64_t", "s": 8}, "location": "r16"}, {"n": "d", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r56"}, {"n": "a", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r64"}, {"n": "mask", "t": {"T": 1, "n": "uint64_t", "s": 8}, "location": "s16"}, {"n": "t", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 996 |
[
"{\"name\": \"tcg_temp_free_i64\", \"code\": \"__int64 __fastcall tcg_temp_free_i64 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i64_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i64\", \"code\": \"__int64 tcg_temp_new_i64 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i64 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_or_i64\", \"code\": \"__int64 __fastcall tcg_gen_or_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_shl\", \"code\": \"__int64 __fastcall gen_shl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shl_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_shl32_ins_i32", "code": "__int64 __fastcall gen_shl32_ins_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , unsigned int @@a3@@ ) { return tcg_gen_deposit_i32 ( @@a1@@ , @@a1@@ , @@a2@@ , @@a3@@ , Number - @@a3@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "shift", "t": {"T": 1, "n": "int32_t", "s": 4}, "location": "r16"}, {"n": "d", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "a", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 997 |
[
"{\"name\": \"gen_shl\", \"code\": \"__int64 __fastcall gen_shl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shl_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_shl64_ins_i64", "code": "__int64 __fastcall gen_shl64_ins_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , unsigned int @@a3@@ ) { return tcg_gen_deposit_i64 ( @@a1@@ , @@a1@@ , @@a2@@ , @@a3@@ , Number - @@a3@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "shift", "t": {"T": 1, "n": "int64_t", "s": 8}, "location": "r16"}, {"n": "d", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r56"}, {"n": "a", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 998 |
[
"{\"name\": \"gen_shl\", \"code\": \"__int64 __fastcall gen_shl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shl_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_shl_ins_vec", "code": "__int64 __fastcall gen_shl_ins_vec ( unsigned int @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v7@@ ; __int64 @@v8@@ ; if ( ! @@a4@@ ) return tcg_gen_mov_vec ( @@a2@@ , @@a3@@ ) ; @@v7@@ = tcg_temp_new_vec_matching ( @@a2@@ ) ; @@v8@@ = tcg_temp_new_vec_matching ( @@a2@@ ) ; tcg_gen_dupi_vec ( @@a1@@ , @@v8@@ , Number >> ( Number - ( unsigned __int8 ) @@a4@@ ) ) ; tcg_gen_shli_vec ( @@a1@@ , @@v7@@ , @@a3@@ , @@a4@@ ) ; tcg_gen_and_vec ( @@a1@@ , @@a2@@ , @@a2@@ , @@v8@@ ) ; tcg_gen_or_vec ( @@a1@@ , @@a2@@ , @@a2@@ , @@v7@@ ) ; tcg_temp_free_vec ( @@v7@@ ) ; return tcg_temp_free_vec ( @@v8@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v8", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "a", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r16"}, {"n": "sh", "t": {"T": 1, "n": "int64_t", "s": 8}, "location": "r24"}, {"n": "vece", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "d", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r64"}, {"n": "t", "t": {"T": 3, "t": "TCGv_vec_d"}, "location": "s16"}, {"n": "m", "t": {"T": 3, "t": "TCGv_vec_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 999 |
[
"{\"name\": \"tcg_temp_free_vec\", \"code\": \"__int64 __fastcall tcg_temp_free_vec ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_vec_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_shl\", \"code\": \"__int64 __fastcall gen_shl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shl_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_mla8_i32", "code": "unsigned __int64 __fastcall gen_mla8_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { gen_helper_neon_mul_u8 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; return gen_helper_neon_add_u8 ( @@a1@@ , @@a1@@ , @@a2@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "b", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "d", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "a", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,000 |
[
"{\"name\": \"gen_helper_neon_add_u8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_add_u8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_add_u8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_mul_u8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_mul_u8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_mul_u8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_mls8_i32", "code": "unsigned __int64 __fastcall gen_mls8_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { gen_helper_neon_mul_u8 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; return gen_helper_neon_sub_u8 ( @@a1@@ , @@a1@@ , @@a2@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "b", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "d", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "a", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,001 |
[
"{\"name\": \"gen_helper_neon_sub_u8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_sub_u8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_sub_u8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_mul_u8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_mul_u8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_mul_u8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_mla16_i32", "code": "unsigned __int64 __fastcall gen_mla16_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { gen_helper_neon_mul_u16 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; return gen_helper_neon_add_u16 ( @@a1@@ , @@a1@@ , @@a2@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "b", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "d", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "a", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,002 |
[
"{\"name\": \"gen_helper_neon_add_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_add_u16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_add_u16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_mul_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_mul_u16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_mul_u16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_mls16_i32", "code": "unsigned __int64 __fastcall gen_mls16_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { gen_helper_neon_mul_u16 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; return gen_helper_neon_sub_u16 ( @@a1@@ , @@a1@@ , @@a2@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "b", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "d", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "a", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,003 |
[
"{\"name\": \"gen_helper_neon_sub_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_sub_u16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_sub_u16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_mul_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_mul_u16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_mul_u16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_mla32_i32", "code": "__int64 __fastcall gen_mla32_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { tcg_gen_mul_i32 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; return tcg_gen_add_i32 ( @@a1@@ , @@a1@@ , @@a2@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "b", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "d", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "a", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,004 |
[
"{\"name\": \"tcg_gen_add_i32\", \"code\": \"__int64 __fastcall tcg_gen_add_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_mul_i32\", \"code\": \"__int64 __fastcall tcg_gen_mul_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "gen_mls32_i32", "code": "__int64 __fastcall gen_mls32_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { tcg_gen_mul_i32 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; return tcg_gen_sub_i32 ( @@a1@@ , @@a1@@ , @@a2@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "b", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "d", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "a", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,005 |
[
"{\"name\": \"tcg_gen_sub_i32\", \"code\": \"__int64 __fastcall tcg_gen_sub_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_mul_i32\", \"code\": \"__int64 __fastcall tcg_gen_mul_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "gen_mla64_i64", "code": "__int64 __fastcall gen_mla64_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { tcg_gen_mul_i64 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; return tcg_gen_add_i64 ( @@a1@@ , @@a1@@ , @@a2@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "b", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r16"}, {"n": "d", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r56"}, {"n": "a", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,006 |
[
"{\"name\": \"tcg_gen_add_i64\", \"code\": \"__int64 __fastcall tcg_gen_add_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_mul_i64\", \"code\": \"__int64 __fastcall tcg_gen_mul_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "gen_mls64_i64", "code": "__int64 __fastcall gen_mls64_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { tcg_gen_mul_i64 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; return tcg_gen_sub_i64 ( @@a1@@ , @@a1@@ , @@a2@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "b", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r16"}, {"n": "d", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r56"}, {"n": "a", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,007 |
[
"{\"name\": \"tcg_gen_sub_i64\", \"code\": \"__int64 __fastcall tcg_gen_sub_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_mul_i64\", \"code\": \"__int64 __fastcall tcg_gen_mul_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "gen_mla_vec", "code": "__int64 __fastcall gen_mla_vec ( unsigned int @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { tcg_gen_mul_vec ( @@a1@@ , @@a3@@ , @@a3@@ , @@a4@@ ) ; return tcg_gen_add_vec ( @@a1@@ , @@a2@@ , @@a2@@ , @@a3@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "a", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r16"}, {"n": "b", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r24"}, {"n": "vece", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "d", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,008 |
[] |
{"name": "gen_mls_vec", "code": "__int64 __fastcall gen_mls_vec ( unsigned int @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { tcg_gen_mul_vec ( @@a1@@ , @@a3@@ , @@a3@@ , @@a4@@ ) ; return tcg_gen_sub_vec ( @@a1@@ , @@a2@@ , @@a2@@ , @@a3@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "a", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r16"}, {"n": "b", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r24"}, {"n": "vece", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "d", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,009 |
[] |
{"name": "gen_cmtst_i32", "code": "__int64 __fastcall gen_cmtst_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { tcg_gen_and_i32 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_setcondi_i32 ( Number L , @@a1@@ , @@a1@@ , Number L ) ; return tcg_gen_neg_i32 ( @@a1@@ , @@a1@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "b", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "d", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "a", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,010 |
[
"{\"name\": \"tcg_gen_and_i32\", \"code\": \"__int64 __fastcall tcg_gen_and_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_neg_i32\", \"code\": \"__int64 __fastcall tcg_gen_neg_i32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { return tcg_gen_op2_i32 ( Number , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "gen_cmtst_i64", "code": "__int64 __fastcall gen_cmtst_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { tcg_gen_and_i64 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_setcondi_i64 ( Number L , @@a1@@ , @@a1@@ , Number L ) ; return tcg_gen_neg_i64 ( @@a1@@ , @@a1@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "b", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r16"}, {"n": "d", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r56"}, {"n": "a", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,011 |
[
"{\"name\": \"tcg_gen_and_i64\", \"code\": \"__int64 __fastcall tcg_gen_and_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_neg_i64\", \"code\": \"__int64 __fastcall tcg_gen_neg_i64 ( __int64 @@a1@@ , __int64 @@a2@@ ) { return tcg_gen_op2_i64 ( Number , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "gen_cmtst_vec", "code": "__int64 __fastcall gen_cmtst_vec ( unsigned int @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { tcg_gen_and_vec ( @@a1@@ , @@a2@@ , @@a3@@ , @@a4@@ ) ; tcg_gen_dupi_vec ( @@a1@@ , @@a3@@ , Number L ) ; return tcg_gen_cmp_vec ( Number L , @@a1@@ , @@a2@@ , @@a2@@ , @@a3@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "a", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r16"}, {"n": "b", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r24"}, {"n": "vece", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "d", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,012 |
[] |
{"name": "gen_uqadd_vec", "code": "__int64 __fastcall gen_uqadd_vec ( unsigned int @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ ) { __int64 @@v9@@ ; @@v9@@ = tcg_temp_new_vec_matching ( @@a2@@ ) ; tcg_gen_add_vec ( @@a1@@ , @@v9@@ , @@a4@@ , @@a5@@ ) ; tcg_gen_usadd_vec ( @@a1@@ , @@a2@@ , @@a4@@ , @@a5@@ ) ; tcg_gen_cmp_vec ( Number L , @@a1@@ , @@v9@@ , @@v9@@ , @@a2@@ ) ; tcg_gen_or_vec ( @@a1@@ , @@a3@@ , @@a3@@ , @@v9@@ ) ; return tcg_temp_free_vec ( @@v9@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "a5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r72"}, {"n": "v9", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "sat", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r16"}, {"n": "a", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r24"}, {"n": "vece", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "t", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r64"}, {"n": "b", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r72"}, {"n": "x", "t": {"T": 3, "t": "TCGv_vec_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,013 |
[
"{\"name\": \"tcg_temp_free_vec\", \"code\": \"__int64 __fastcall tcg_temp_free_vec ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_vec_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "gen_sqadd_vec", "code": "__int64 __fastcall gen_sqadd_vec ( unsigned int @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ ) { __int64 @@v9@@ ; @@v9@@ = tcg_temp_new_vec_matching ( @@a2@@ ) ; tcg_gen_add_vec ( @@a1@@ , @@v9@@ , @@a4@@ , @@a5@@ ) ; tcg_gen_ssadd_vec ( @@a1@@ , @@a2@@ , @@a4@@ , @@a5@@ ) ; tcg_gen_cmp_vec ( Number L , @@a1@@ , @@v9@@ , @@v9@@ , @@a2@@ ) ; tcg_gen_or_vec ( @@a1@@ , @@a3@@ , @@a3@@ , @@v9@@ ) ; return tcg_temp_free_vec ( @@v9@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "a5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r72"}, {"n": "v9", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "sat", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r16"}, {"n": "a", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r24"}, {"n": "vece", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "t", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r64"}, {"n": "b", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r72"}, {"n": "x", "t": {"T": 3, "t": "TCGv_vec_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,014 |
[
"{\"name\": \"tcg_temp_free_vec\", \"code\": \"__int64 __fastcall tcg_temp_free_vec ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_vec_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "gen_uqsub_vec", "code": "__int64 __fastcall gen_uqsub_vec ( unsigned int @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ ) { __int64 @@v9@@ ; @@v9@@ = tcg_temp_new_vec_matching ( @@a2@@ ) ; tcg_gen_sub_vec ( @@a1@@ , @@v9@@ , @@a4@@ , @@a5@@ ) ; tcg_gen_ussub_vec ( @@a1@@ , @@a2@@ , @@a4@@ , @@a5@@ ) ; tcg_gen_cmp_vec ( Number L , @@a1@@ , @@v9@@ , @@v9@@ , @@a2@@ ) ; tcg_gen_or_vec ( @@a1@@ , @@a3@@ , @@a3@@ , @@v9@@ ) ; return tcg_temp_free_vec ( @@v9@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "a5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r72"}, {"n": "v9", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "sat", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r16"}, {"n": "a", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r24"}, {"n": "vece", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "t", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r64"}, {"n": "b", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r72"}, {"n": "x", "t": {"T": 3, "t": "TCGv_vec_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,015 |
[
"{\"name\": \"tcg_temp_free_vec\", \"code\": \"__int64 __fastcall tcg_temp_free_vec ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_vec_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "gen_sqsub_vec", "code": "__int64 __fastcall gen_sqsub_vec ( unsigned int @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ ) { __int64 @@v9@@ ; @@v9@@ = tcg_temp_new_vec_matching ( @@a2@@ ) ; tcg_gen_sub_vec ( @@a1@@ , @@v9@@ , @@a4@@ , @@a5@@ ) ; tcg_gen_sssub_vec ( @@a1@@ , @@a2@@ , @@a4@@ , @@a5@@ ) ; tcg_gen_cmp_vec ( Number L , @@a1@@ , @@v9@@ , @@v9@@ , @@a2@@ ) ; tcg_gen_or_vec ( @@a1@@ , @@a3@@ , @@a3@@ , @@v9@@ ) ; return tcg_temp_free_vec ( @@v9@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "a5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r72"}, {"n": "v9", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "sat", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r16"}, {"n": "a", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r24"}, {"n": "vece", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "t", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r64"}, {"n": "b", "t": {"T": 1, "n": "TCGv_vec", "s": 8}, "location": "r72"}, {"n": "x", "t": {"T": 3, "t": "TCGv_vec_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,016 |
[
"{\"name\": \"tcg_temp_free_vec\", \"code\": \"__int64 __fastcall tcg_temp_free_vec ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_vec_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "disas_neon_data_insn", "code": "__int64 __fastcall disas_neon_data_insn ( __int64 @@a1@@ , unsigned int @@a2@@ ) { unsigned int v2 ; unsigned int v3 ; __int64 result ; int v5 ; char * v6 ; char * v7 ; unsigned int @@v8@@ ; unsigned int v9 ; __int64 v10 ; __int64 @@v11@@ ; unsigned int @@v12@@ ; int v13 ; _BOOL4 v14 ; int v15 ; int v16 ; int v17 ; int v18 ; int v19 ; int v20 ; int v21 ; int v22 ; unsigned int v23 ; int v24 ; unsigned int v25 ; __int64 v26 ; __int64 v27 ; int v28 ; int v29 ; int v30 ; __int64 v31 ; int v32 ; unsigned int v33 ; unsigned int v34 ; unsigned int v35 ; int v36 ; unsigned int @@v37@@ ; unsigned int v38 ; unsigned int @@v39@@ ; unsigned int v40 ; bool @@v42@@ ; int @@v43@@ ; int @@v44@@ ; int @@v45@@ ; unsigned int v46 ; int i3 ; int v48 ; unsigned int v49 ; int v50 ; int v51 ; int v52 ; int v53 ; signed int v54 ; int i ; int v56 ; int j ; int i8 ; int i6 ; int i7 ; int i4 ; int i5 ; int i1 ; int nn ; int kk ; int ll ; int mm ; int k ; int l ; int n ; int ii ; int jj ; int @@v73@@ ; int @@v74@@ ; unsigned int v75 ; unsigned int v76 ; unsigned int v77 ; unsigned int v78 ; unsigned int v79 ; int @@i2@@ ; int @@m@@ ; unsigned int @@v82@@ ; int @@v83@@ ; unsigned int @@v84@@ ; int @@v85@@ ; int @@v86@@ ; unsigned int @@v87@@ ; unsigned int @@v88@@ ; unsigned int @@v89@@ ; unsigned int @@v90@@ ; int v91 ; int v92 ; int v93 ; int v94 ; int v95 ; unsigned int @@v96@@ ; int @@v97@@ ; int @@v98@@ ; int @@v99@@ ; int @@v100@@ ; unsigned int @@v101@@ ; int @@v102@@ ; int @@v103@@ ; __int64 v104 ; __int64 v105 ; __int64 v106 ; __int64 v107 ; __int64 v108 ; __int64 v109 ; __int64 v110 ; __int64 v111 ; __int64 v112 ; __int64 v113 ; __int64 v114 ; __int64 v115 ; __int64 v116 ; __int64 v117 ; __int64 v118 ; __int64 v119 ; __int64 v120 ; __int64 v121 ; __int64 v122 ; __int64 v123 ; __int64 v124 ; __int64 v125 ; __int64 v126 ; __int64 v127 ; __int64 v128 ; __int64 v129 ; __int64 v130 ; __int64 v131 ; __int64 v132 ; __int64 v133 ; __int64 v134 ; __int64 v135 ; __int64 v136 ; __int64 v137 ; __int64 v138 ; __int64 v139 ; __int64 v140 ; __int64 v141 ; __int64 v142 ; __int64 v143 ; __int64 v144 ; __int64 v145 ; __int64 v146 ; __int64 v147 ; __int64 v148 ; __int64 v149 ; __int64 v150 ; __int64 v151 ; __int64 v152 ; __int64 v153 ; __int64 v154 ; __int64 v155 ; __int64 v156 ; __int64 v157 ; __int64 v158 ; __int64 v159 ; __int64 v160 ; __int64 v161 ; __int64 v162 ; __int64 v163 ; __int64 v164 ; __int64 v165 ; __int64 v166 ; __int64 v167 ; __int64 v168 ; __int64 v169 ; __int64 v170 ; __int64 v171 ; __int64 @@v172@@ ; __int64 @@v173@@ ; unsigned __int64 @@v174@@ ; unsigned __int64 ( __fastcall * @@v175@@ ) ( __int64 , __int64 , __int64 , __int64 ) ; __int64 @@v176@@ ; unsigned __int64 ( __fastcall * @@v177@@ ) ( __int64 , __int64 , __int64 , __int64 , __int64 ) ; __int64 v178 ; __int64 v179 ; __int64 @@v180@@ ; __int64 @@v181@@ ; __int64 @@v182@@ ; __int64 @@v183@@ ; __int64 @@v184@@ ; __int64 @@v185@@ ; __int64 @@v186@@ ; __int64 @@v187@@ ; __int64 @@v188@@ ; __int64 @@v189@@ ; __int64 @@v190@@ ; __int64 @@v191@@ ; __int64 @@v192@@ ; __int64 @@v193@@ ; __int64 @@v194@@ ; __int64 @@v195@@ ; __int64 @@v196@@ ; __int64 @@v197@@ ; __int64 @@v198@@ ; __int64 @@v199@@ ; __int64 @@v200@@ ; __int64 @@v201@@ ; __int64 @@v202@@ ; __int64 v203 ; __int64 v204 ; __int64 v205 ; __int64 v206 ; __int64 v207 ; __int64 @@v208@@ ; __int64 @@v209@@ ; __int64 @@v210@@ ; __int64 @@v211@@ ; __int64 @@v212@@ ; __int64 @@v213@@ ; __int64 @@v214@@ ; __int64 @@v215@@ ; __int64 @@v216@@ ; __int64 @@v217@@ ; __int64 @@v218@@ ; __int64 @@v219@@ ; __int64 @@v220@@ ; __int64 @@v221@@ ; __int64 @@v222@@ ; __int64 @@v223@@ ; __int64 @@v224@@ ; __int64 @@v225@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { v2 = * ( _DWORD * ) ( @@a1@@ + Number ) ; v3 = syn_simd_access_trap ( Number , Number , Number ) ; gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , v3 , v2 ) ; return Number L ; } if ( * ( _BYTE * ) ( @@a1@@ + Number ) != Number ) return Number L ; @@v85@@ = ( @@a2@@ & Number ) != Number ; @@v86@@ = HIBYTE ( @@a2@@ ) & Number ; if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v43@@ = ( ( unsigned __int16 ) @@a2@@ >> Number ) | ( @@a2@@ >> Number ) & Number ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v43@@ = ( unsigned __int16 ) @@a2@@ >> Number ; } if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v44@@ = HIWORD ( @@a2@@ ) & Number | ( @@a2@@ >> Number ) & Number ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v44@@ = HIWORD ( @@a2@@ ) & Number ; } if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v45@@ = @@a2@@ & Number | ( @@a2@@ >> Number ) & Number ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v45@@ = @@a2@@ & Number ; } v46 = ( @@a2@@ >> Number ) & Number ; if ( ( @@a2@@ & Number ) != Number ) v5 = Number ; else v5 = Number ; @@v87@@ = v5 ; @@v88@@ = neon_reg_offset ( @@v43@@ , Number ) ; @@v89@@ = neon_reg_offset ( @@v44@@ , Number ) ; @@v90@@ = neon_reg_offset ( @@v45@@ , Number ) ; if ( ( @@a2@@ & Number ) == Number ) { v91 = ( @@a2@@ >> Number ) & Number | ( @@a2@@ >> Number ) & Number ; if ( ( ( ( int ) neon_3r_sizes [ v91 ] >> v46 ) & Number ) == Number ) return Number L ; if ( ( @@a2@@ & Number ) != Number && ( ( ( unsigned __int8 ) @@v45@@ | ( unsigned __int8 ) ( @@v44@@ | @@v43@@ ) ) & Number ) != Number ) return Number L ; switch ( v91 ) { case Number : if ( @@v86@@ ) v6 = ( char * ) & uqadd_op ; else v6 = ( char * ) & sqadd_op ; goto LABEL_76 ; case Number : switch ( v46 | ( Number * @@v86@@ ) ) { case Number : tcg_gen_gvec_and ( Number L , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; break ; case Number : tcg_gen_gvec_andc ( Number L , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; break ; case Number : tcg_gen_gvec_or ( Number L , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; break ; case Number : tcg_gen_gvec_orc ( Number L , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; break ; case Number : tcg_gen_gvec_xor ( Number L , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; break ; case Number : tcg_gen_gvec_bitsel ( Number L , @@v88@@ , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; break ; case Number : tcg_gen_gvec_bitsel ( Number L , @@v88@@ , @@v90@@ , @@v89@@ , @@v88@@ , @@v87@@ , @@v87@@ ) ; break ; case Number : tcg_gen_gvec_bitsel ( Number L , @@v88@@ , @@v90@@ , @@v88@@ , @@v89@@ , @@v87@@ , @@v87@@ ) ; break ; default : return Number L ; } return Number L ; case Number : if ( @@v86@@ ) v6 = ( char * ) & uqsub_op ; else v6 = ( char * ) & sqsub_op ; LABEL_76 : tcg_gen_gvec_4 ( @@v88@@ , Number L , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ , & v6 [ Number * v46 ] ) ; return Number L ; case Number : @@v8@@ = @@v87@@ ; v9 = @@v90@@ ; v10 = @@v89@@ ; @@v11@@ = @@v88@@ ; if ( @@v86@@ ) @@v12@@ = Number ; else @@v12@@ = Number ; goto LABEL_95 ; case Number : @@v8@@ = @@v87@@ ; v9 = @@v90@@ ; v10 = @@v89@@ ; @@v11@@ = @@v88@@ ; if ( @@v86@@ ) @@v12@@ = Number ; else @@v12@@ = Number ; LABEL_95 : tcg_gen_gvec_cmp ( @@v12@@ , v46 , @@v11@@ , v10 , v9 , @@v8@@ , @@v87@@ ) ; return Number L ; case Number : if ( @@v86@@ ) tcg_gen_gvec_umax ( v46 , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; else tcg_gen_gvec_smax ( v46 , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; return Number L ; case Number : if ( @@v86@@ ) tcg_gen_gvec_umin ( v46 , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; else tcg_gen_gvec_smin ( v46 , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; return Number L ; case Number : if ( @@v86@@ ) tcg_gen_gvec_sub ( v46 , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; else tcg_gen_gvec_add ( v46 , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; return Number L ; case Number : if ( @@v86@@ ) tcg_gen_gvec_cmp ( Number L , v46 , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; else tcg_gen_gvec_3 ( @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ , ( char * ) & cmtst_op + Number * ( int ) v46 ) ; return Number L ; case Number : if ( @@v86@@ ) v7 = ( char * ) & mls_op + Number * ( int ) v46 ; else v7 = ( char * ) & mla_op + Number * ( int ) v46 ; tcg_gen_gvec_3 ( @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ , v7 ) ; return Number L ; case Number : if ( @@v86@@ ) { if ( ! v46 ) goto LABEL_107 ; result = Number L ; } else { tcg_gen_gvec_mul ( v46 , @@v88@@ , @@v89@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; result = Number L ; } return result ; case Number : if ( ! @@v86@@ ) goto LABEL_107 ; if ( v46 == Number ) return do_v81_helper ( @@a1@@ , ( __int64 ) gen_helper_gvec_qrdmlah_s16 , @@v85@@ , @@v43@@ , @@v44@@ , @@v45@@ ) ; if ( v46 == Number ) return do_v81_helper ( @@a1@@ , ( __int64 ) gen_helper_gvec_qrdmlah_s32 , @@v85@@ , @@v43@@ , @@v44@@ , @@v45@@ ) ; return Number L ; case Number : if ( ( @@a2@@ & Number ) == Number ) return Number L ; if ( @@v86@@ ) { if ( ! isar_feature_aa32_sha2 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) || v46 == Number ) return Number L ; v163 = vfp_reg_ptr ( Number , @@v43@@ ) ; v168 = vfp_reg_ptr ( Number , @@v44@@ ) ; @@v172@@ = vfp_reg_ptr ( Number , @@v45@@ ) ; if ( v46 == Number ) { gen_helper_crypto_sha256su1 ( v163 , v168 , @@v172@@ ) ; } else if ( v46 ) { gen_helper_crypto_sha256h2 ( v163 , v168 , @@v172@@ ) ; } else { gen_helper_crypto_sha256h ( v163 , v168 , @@v172@@ ) ; } } else { if ( ! isar_feature_aa32_sha1 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; v163 = vfp_reg_ptr ( Number , @@v43@@ ) ; v168 = vfp_reg_ptr ( Number , @@v44@@ ) ; @@v172@@ = vfp_reg_ptr ( Number , @@v45@@ ) ; v205 = tcg_const_i32 ( v46 ) ; gen_helper_crypto_sha1_3reg ( v163 , v168 , @@v172@@ , v205 ) ; tcg_temp_free_i32 ( v205 ) ; } tcg_temp_free_ptr ( v163 ) ; tcg_temp_free_ptr ( v168 ) ; tcg_temp_free_ptr ( @@v172@@ ) ; return Number L ; case Number : if ( @@v86@@ ) { if ( v46 == Number ) return do_v81_helper ( @@a1@@ , ( __int64 ) gen_helper_gvec_qrdmlsh_s16 , @@v85@@ , @@v43@@ , @@v44@@ , @@v45@@ ) ; if ( v46 == Number ) return do_v81_helper ( @@a1@@ , ( __int64 ) gen_helper_gvec_qrdmlsh_s32 , @@v85@@ , @@v43@@ , @@v44@@ , @@v45@@ ) ; return Number L ; } if ( v46 == Number ) return Number L ; LABEL_107 : if ( v46 == Number ) { for ( i = Number ; ; ++ i ) { v13 = ( @@a2@@ & Number ) != Number ? Number : Number ; if ( v13 <= i ) break ; neon_load_reg64 ( cpu_V0 , i + @@v44@@ ) ; neon_load_reg64 ( cpu_V1 , i + @@v45@@ ) ; if ( v91 == Number ) { if ( @@v86@@ ) gen_helper_neon_qrshl_u64 ( cpu_V0 , cpu_env , cpu_V1 , cpu_V0 ) ; else gen_helper_neon_qrshl_s64 ( cpu_V0 , cpu_env , cpu_V1 , cpu_V0 ) ; } else { if ( v91 > Number ) goto LABEL_127 ; switch ( v91 ) { case Number : if ( @@v86@@ ) gen_helper_neon_rshl_u64 ( cpu_V0 , cpu_V1 , cpu_V0 ) ; else gen_helper_neon_rshl_s64 ( cpu_V0 , cpu_V1 , cpu_V0 ) ; break ; case Number : if ( @@v86@@ ) gen_helper_neon_shl_u64 ( cpu_V0 , cpu_V1 , cpu_V0 ) ; else gen_helper_neon_shl_s64 ( cpu_V0 , cpu_V1 , cpu_V0 ) ; break ; case Number : if ( @@v86@@ ) gen_helper_neon_qshl_u64 ( cpu_V0 , cpu_env , cpu_V1 , cpu_V0 ) ; else gen_helper_neon_qshl_s64 ( cpu_V0 , cpu_env , cpu_V1 , cpu_V0 ) ; break ; default : LABEL_127 : abort ( ) ; } } neon_store_reg64 ( cpu_V0 , i + @@v43@@ ) ; } return Number L ; } @@v74@@ = Number ; switch ( v91 ) { case Number : case Number : case Number : case Number : @@v103@@ = @@v44@@ ; @@v44@@ = @@v45@@ ; @@v45@@ = @@v103@@ ; goto LABEL_153 ; case Number : case Number : case Number : @@v74@@ = Number ; goto LABEL_153 ; case Number : if ( arm_dc_feature ( @@a1@@ , Number ) ) goto LABEL_153 ; return Number L ; case Number : v14 = @@v86@@ && ( ( @@a2@@ >> Number ) & Number ) <= Number ; @@v74@@ = v14 ; goto LABEL_153 ; case Number : if ( @@v86@@ || ! v46 ) goto LABEL_153 ; return Number L ; case Number : if ( @@v86@@ ) goto LABEL_153 ; return Number L ; case Number : @@v74@@ = HIBYTE ( @@a2@@ ) & Number ; goto LABEL_153 ; case Number : if ( ! @@v86@@ || arm_dc_feature ( @@a1@@ , Number ) ) goto LABEL_153 ; return Number L ; default : LABEL_153 : if ( @@v74@@ && ( @@a2@@ & Number ) != Number ) return Number L ; v56 = Number ; while ( Number ) { v16 = ( @@a2@@ & Number ) != Number ? Number : Number ; if ( v16 <= v56 ) break ; if ( @@v74@@ ) { if ( v56 > Number ) { v104 = neon_load_reg ( @@v45@@ , Number ) ; v128 = neon_load_reg ( @@v45@@ , Number ) ; } else { v104 = neon_load_reg ( @@v44@@ , Number ) ; v128 = neon_load_reg ( @@v44@@ , Number ) ; } } else { v104 = neon_load_reg ( @@v44@@ , v56 ) ; v128 = neon_load_reg ( @@v45@@ , v56 ) ; } switch ( v91 ) { case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_hadd_s8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_hadd_u8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_hadd_s16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_hadd_u16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_hadd_s32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_hadd_u32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_rhadd_s8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_rhadd_u8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_rhadd_s16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_rhadd_u16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_rhadd_s32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_rhadd_u32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_hsub_s8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_hsub_u8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_hsub_s16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_hsub_u16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_hsub_s32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_hsub_u32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_shl_s8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_shl_u8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_shl_s16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_shl_u16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_shl_s32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_shl_u32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_qshl_s8 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_qshl_u8 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_qshl_s16 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_qshl_u16 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_qshl_s32 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_qshl_u32 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_rshl_s8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_rshl_u8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_rshl_s16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_rshl_u16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_rshl_s32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_rshl_u32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_qrshl_s8 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_qrshl_u8 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_qrshl_s16 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_qrshl_u16 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_qrshl_s32 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_qrshl_u32 ( v104 , cpu_env , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_abd_s8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_abd_u8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_abd_s16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_abd_u16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_abd_s32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_abd_u32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_abd_s8 ( v104 , v104 , v128 ) ; goto LABEL_235 ; case Number : gen_helper_neon_abd_u8 ( v104 , v104 , v128 ) ; goto LABEL_235 ; case Number : gen_helper_neon_abd_s16 ( v104 , v104 , v128 ) ; goto LABEL_235 ; case Number : gen_helper_neon_abd_u16 ( v104 , v104 , v128 ) ; goto LABEL_235 ; case Number : gen_helper_neon_abd_s32 ( v104 , v104 , v128 ) ; goto LABEL_235 ; case Number : gen_helper_neon_abd_u32 ( v104 , v104 , v128 ) ; LABEL_235 : tcg_temp_free_i32 ( v128 ) ; v128 = neon_load_reg ( @@v43@@ , v56 ) ; gen_neon_add ( v46 , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : gen_helper_neon_mul_p8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_pmax_s8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_pmax_u8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_pmax_s16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_pmax_u16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : tcg_gen_smax_i32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : tcg_gen_umax_i32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_pmin_s8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_pmin_u8 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_pmin_s16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : gen_helper_neon_pmin_u16 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : tcg_gen_smin_i32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; case Number : tcg_gen_umin_i32 ( v104 , v104 , v128 ) ; goto LABEL_312 ; default : return Number L ; } case Number : if ( @@v86@@ ) { if ( v46 == Number ) { gen_helper_neon_qrdmulh_s16 ( v104 , cpu_env , v104 , v128 ) ; } else { if ( v46 != Number ) abort ( ) ; gen_helper_neon_qrdmulh_s32 ( v104 , cpu_env , v104 , v128 ) ; } } else if ( v46 == Number ) { gen_helper_neon_qdmulh_s16 ( v104 , cpu_env , v104 , v128 ) ; } else { if ( v46 != Number ) abort ( ) ; gen_helper_neon_qdmulh_s32 ( v104 , cpu_env , v104 , v128 ) ; } goto LABEL_312 ; case Number : if ( v46 == Number ) { tcg_gen_add_i32 ( v104 , v104 , v128 ) ; } else if ( v46 ) { gen_helper_neon_padd_u16 ( v104 , v104 , v128 ) ; } else { gen_helper_neon_padd_u8 ( v104 , v104 , v128 ) ; } goto LABEL_312 ; case Number : @@v224@@ = get_fpstatus_ptr ( Number ) ; @@v225@@ = neon_load_reg ( @@v43@@ , v56 ) ; if ( v46 ) gen_helper_vfp_negs ( v104 , v104 ) ; gen_helper_vfp_muladds ( v104 , v104 , v128 , @@v225@@ , @@v224@@ ) ; tcg_temp_free_i32 ( @@v225@@ ) ; tcg_temp_free_ptr ( @@v224@@ ) ; goto LABEL_312 ; case Number : @@v223@@ = get_fpstatus_ptr ( Number ) ; v15 = v46 | ( Number * @@v86@@ ) ; if ( v15 == Number ) { gen_helper_neon_abd_f32 ( v104 , v104 , v128 , @@v223@@ ) ; } else { if ( v15 > Number ) goto LABEL_279 ; if ( v15 == Number ) goto LABEL_276 ; if ( v15 > Number ) goto LABEL_279 ; if ( ! v15 ) { LABEL_276 : gen_helper_vfp_adds ( v104 , v104 , v128 , @@v223@@ ) ; } else { if ( v15 != Number ) LABEL_279 : abort ( ) ; gen_helper_vfp_subs ( v104 , v104 , v128 , @@v223@@ ) ; } } tcg_temp_free_ptr ( @@v223@@ ) ; LABEL_312 : tcg_temp_free_i32 ( v128 ) ; if ( @@v74@@ && @@v43@@ == @@v45@@ ) neon_store_scratch ( v56 , v104 ) ; else neon_store_reg ( @@v43@@ , v56 , v104 ) ; ++ v56 ; break ; case Number : @@v222@@ = get_fpstatus_ptr ( Number ) ; gen_helper_vfp_muls ( v104 , v104 , v128 , @@v222@@ ) ; if ( ! @@v86@@ ) { tcg_temp_free_i32 ( v128 ) ; v128 = neon_load_reg ( @@v43@@ , v56 ) ; if ( v46 ) gen_helper_vfp_subs ( v104 , v128 , v104 , @@v222@@ ) ; else gen_helper_vfp_adds ( v104 , v104 , v128 , @@v222@@ ) ; } tcg_temp_free_ptr ( @@v222@@ ) ; goto LABEL_312 ; case Number : @@v221@@ = get_fpstatus_ptr ( Number ) ; if ( @@v86@@ ) { if ( v46 ) gen_helper_neon_cgt_f32 ( v104 , v104 , v128 , @@v221@@ ) ; else gen_helper_neon_cge_f32 ( v104 , v104 , v128 , @@v221@@ ) ; } else { gen_helper_neon_ceq_f32 ( v104 , v104 , v128 , @@v221@@ ) ; } tcg_temp_free_ptr ( @@v221@@ ) ; goto LABEL_312 ; case Number : @@v220@@ = get_fpstatus_ptr ( Number ) ; if ( v46 ) gen_helper_neon_acgt_f32 ( v104 , v104 , v128 , @@v220@@ ) ; else gen_helper_neon_acge_f32 ( v104 , v104 , v128 , @@v220@@ ) ; tcg_temp_free_ptr ( @@v220@@ ) ; goto LABEL_312 ; case Number : @@v219@@ = get_fpstatus_ptr ( Number ) ; if ( v46 ) gen_helper_vfp_mins ( v104 , v104 , v128 , @@v219@@ ) ; else gen_helper_vfp_maxs ( v104 , v104 , v128 , @@v219@@ ) ; tcg_temp_free_ptr ( @@v219@@ ) ; goto LABEL_312 ; case Number : if ( @@v86@@ ) { @@v218@@ = get_fpstatus_ptr ( Number ) ; if ( v46 ) gen_helper_vfp_minnums ( v104 , v104 , v128 , @@v218@@ ) ; else gen_helper_vfp_maxnums ( v104 , v104 , v128 , @@v218@@ ) ; tcg_temp_free_ptr ( @@v218@@ ) ; } else if ( v46 ) { gen_helper_rsqrts_f32 ( v104 , v104 , v128 , cpu_env ) ; } else { gen_helper_recps_f32 ( v104 , v104 , v128 , cpu_env ) ; } goto LABEL_312 ; default : abort ( ) ; } } if ( @@v74@@ && @@v43@@ == @@v45@@ ) { for ( j = Number ; ; ++ j ) { v17 = ( @@a2@@ & Number ) != Number ? Number : Number ; if ( v17 <= j ) break ; v105 = neon_load_scratch ( j ) ; neon_store_reg ( @@v43@@ , j , v105 ) ; } } break ; } break ; default : goto LABEL_107 ; } return Number L ; } if ( ( @@a2@@ & Number ) == Number ) { if ( v46 == Number ) { LABEL_722 : if ( @@v86@@ ) { if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) != Number ) return Number L ; if ( ( @@a2@@ & Number ) == Number || ( @@a2@@ & Number ) != Number && ( @@v43@@ & Number ) != Number ) return Number L ; if ( ( @@a2@@ & Number ) != Number ) { @@v84@@ = Number ; @@v83@@ = ( @@a2@@ >> Number ) & Number ; } else if ( ( @@a2@@ & Number ) != Number ) { @@v84@@ = Number ; @@v83@@ = ( @@a2@@ >> Number ) & Number ; } else { @@v84@@ = Number ; @@v83@@ = ( @@a2@@ >> Number ) & Number ; } if ( ( @@a2@@ & Number ) != Number ) @@v37@@ = Number ; else @@v37@@ = Number ; if ( ( @@a2@@ & Number ) != Number ) v38 = Number ; else v38 = Number ; @@v39@@ = neon_element_offset ( @@v45@@ , @@v83@@ , @@v84@@ ) ; v40 = neon_reg_offset ( @@v43@@ , Number ) ; tcg_gen_gvec_dup_mem ( @@v84@@ , v40 , @@v39@@ , v38 , @@v37@@ ) ; } else { if ( ( int ) ( @@v44@@ + ( ( @@a2@@ >> Number ) & Number ) + Number ) > Number ) return Number L ; if ( ( @@a2@@ & Number ) != Number ) { v126 = neon_load_reg ( @@v43@@ , Number ) ; } else { v126 = tcg_temp_new_i32 ( ) ; tcg_gen_movi_i32 ( v126 , Number ) ; } v153 = neon_load_reg ( @@v45@@ , Number ) ; v167 = vfp_reg_ptr ( Number , @@v44@@ ) ; v179 = tcg_const_i32 ( Number * ( ( ( @@a2@@ >> Number ) & Number ) + Number ) ) ; gen_helper_neon_tbl ( v153 , v153 , v126 , v167 , v179 ) ; tcg_temp_free_i32 ( v126 ) ; if ( ( @@a2@@ & Number ) != Number ) { v127 = neon_load_reg ( @@v43@@ , Number ) ; } else { v127 = tcg_temp_new_i32 ( ) ; tcg_gen_movi_i32 ( v127 , Number ) ; } v162 = neon_load_reg ( @@v45@@ , Number ) ; gen_helper_neon_tbl ( v162 , v162 , v127 , v167 , v179 ) ; tcg_temp_free_i32 ( v179 ) ; tcg_temp_free_ptr ( v167 ) ; neon_store_reg ( @@v43@@ , Number , v153 ) ; neon_store_reg ( @@v43@@ , Number , v162 ) ; tcg_temp_free_i32 ( v127 ) ; } } else { v95 = ( @@a2@@ >> Number ) & Number | ( @@a2@@ >> Number ) & Number ; v49 = ( @@a2@@ >> Number ) & Number ; if ( ( ( ( int ) neon_2rm_sizes [ v95 ] >> ( ( @@a2@@ >> Number ) & Number ) ) & Number ) == Number ) return Number L ; if ( neon_2rm_is_v8_op ( v95 ) && ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( v95 != Number && v95 != Number && ( @@a2@@ & Number ) != Number && ( ( ( unsigned __int8 ) @@v43@@ | ( unsigned __int8 ) @@v45@@ ) & Number ) != Number ) return Number L ; switch ( v95 ) { case Number : for ( k = Number ; ; ++ k ) { v30 = ( @@a2@@ & Number ) != Number ? Number : Number ; if ( v30 <= k ) break ; v117 = neon_load_reg ( @@v45@@ , Number * k ) ; v137 = neon_load_reg ( @@v45@@ , Number * k + Number ) ; if ( v49 != Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) abort ( ) ; if ( v49 ) gen_swap_half ( v117 ) ; else tcg_gen_bswap32_i32 ( v117 , v117 ) ; } neon_store_reg ( @@v43@@ , Number * k + Number , v117 ) ; if ( v49 != Number ) { if ( v49 ) gen_swap_half ( v137 ) ; else tcg_gen_bswap32_i32 ( v137 , v137 ) ; } neon_store_reg ( @@v43@@ , Number * k , v137 ) ; } return Number L ; case Number : case Number : case Number : case Number : for ( l = Number ; l < @@v85@@ + Number ; ++ l ) { v31 = neon_load_reg ( @@v45@@ , Number * l ) ; gen_neon_widen ( cpu_V0 , v31 , v49 , v95 & Number ) ; v118 = neon_load_reg ( @@v45@@ , Number * l + Number ) ; gen_neon_widen ( cpu_V1 , v118 , v49 , v95 & Number ) ; if ( v49 == Number ) { tcg_gen_add_i64 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; } else { if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) abort ( ) ; if ( v49 ) gen_helper_neon_paddl_u32 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; else gen_helper_neon_paddl_u16 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; } if ( v95 > Number ) { neon_load_reg64 ( cpu_V1 , l + @@v43@@ ) ; gen_neon_addl ( v49 ) ; } neon_store_reg64 ( cpu_V0 , l + @@v43@@ ) ; } return Number L ; case Number : case Number : if ( ! isar_feature_aa32_aes ( * ( _QWORD * ) ( @@a1@@ + Number ) ) || ( ( ( unsigned __int8 ) @@v43@@ | ( unsigned __int8 ) @@v45@@ ) & Number ) != Number ) { return Number L ; } v164 = vfp_reg_ptr ( Number , @@v43@@ ) ; v169 = vfp_reg_ptr ( Number , @@v45@@ ) ; v33 = extract32 ( @@a2@@ , Number , Number ) ; v161 = tcg_const_i32 ( v33 ) ; if ( v95 == Number ) gen_helper_crypto_aese ( v164 , v169 , v161 ) ; else gen_helper_crypto_aesmc ( v164 , v169 , v161 ) ; tcg_temp_free_ptr ( v164 ) ; tcg_temp_free_ptr ( v169 ) ; tcg_temp_free_i32 ( v161 ) ; return Number L ; case Number : tcg_gen_gvec_not ( Number L , @@v88@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; return Number L ; case Number : if ( ! isar_feature_aa32_sha1 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) || ( ( ( unsigned __int8 ) @@v43@@ | ( unsigned __int8 ) @@v45@@ ) & Number ) != Number ) { return Number L ; } v165 = vfp_reg_ptr ( Number , @@v43@@ ) ; v170 = vfp_reg_ptr ( Number , @@v45@@ ) ; gen_helper_crypto_sha1h ( v165 , v170 ) ; tcg_temp_free_ptr ( v165 ) ; tcg_temp_free_ptr ( v170 ) ; return Number L ; case Number : tcg_gen_gvec_abs ( v49 , @@v88@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; return Number L ; case Number : tcg_gen_gvec_neg ( v49 , @@v88@@ , @@v90@@ , @@v87@@ , @@v87@@ ) ; return Number L ; case Number : if ( v49 != Number ) goto LABEL_853 ; for ( @@m@@ = Number ; ; @@m@@ += Number ) { v32 = ( @@a2@@ & Number ) != Number ? Number : Number ; if ( v32 <= @@m@@ ) break ; v119 = neon_load_reg ( @@v45@@ , @@m@@ ) ; v138 = neon_load_reg ( @@v43@@ , @@m@@ + Number ) ; neon_store_reg ( @@v45@@ , @@m@@ , v138 ) ; neon_store_reg ( @@v43@@ , @@m@@ + Number , v119 ) ; } return Number L ; case Number : return ( unsigned int ) gen_neon_unzip ( @@v43@@ , @@v45@@ , v49 , @@v85@@ ) != Number ; case Number : return ( unsigned int ) gen_neon_zip ( @@v43@@ , @@v45@@ , v49 , @@v85@@ ) != Number ; case Number : case Number : if ( ( @@v45@@ & Number ) != Number ) return Number L ; v139 = Number L ; for ( n = Number ; n <= Number ; ++ n ) { neon_load_reg64 ( cpu_V0 , n + @@v45@@ ) ; v120 = tcg_temp_new_i32 ( ) ; gen_neon_narrow_op ( v95 == Number , @@v85@@ , v49 , v120 , cpu_V0 ) ; if ( n ) { neon_store_reg ( @@v43@@ , Number , v139 ) ; neon_store_reg ( @@v43@@ , Number , v120 ) ; } else { v139 = v120 ; } } return Number L ; case Number : if ( ( @@a2@@ & Number ) != Number || ( @@v43@@ & Number ) != Number ) return Number L ; v121 = neon_load_reg ( @@v45@@ , Number ) ; v140 = neon_load_reg ( @@v45@@ , Number ) ; for ( ii = Number ; ii <= Number ; ++ ii ) { if ( ii == Number ) v121 = v140 ; gen_neon_widen ( cpu_V0 , v121 , v49 , Number ) ; tcg_gen_shli_i64 ( cpu_V0 , cpu_V0 , Number << v49 ) ; neon_store_reg64 ( cpu_V0 , ii + @@v43@@ ) ; } return Number L ; case Number : if ( ( ( ( unsigned __int8 ) @@v43@@ | ( unsigned __int8 ) @@v45@@ ) & Number ) != Number ) return Number L ; if ( ( @@a2@@ & Number ) != Number ) { if ( ! isar_feature_aa32_sha2 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; } else if ( ! isar_feature_aa32_sha1 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) { return Number L ; } v166 = vfp_reg_ptr ( Number , @@v43@@ ) ; v171 = vfp_reg_ptr ( Number , @@v45@@ ) ; if ( ( @@a2@@ & Number ) != Number ) gen_helper_crypto_sha256su0 ( v166 , v171 ) ; else gen_helper_crypto_sha1su1 ( v166 , v171 ) ; tcg_temp_free_ptr ( v166 ) ; tcg_temp_free_ptr ( v171 ) ; return Number L ; case Number : if ( ! isar_feature_aa32_fp16_spconv ( * ( _QWORD * ) ( @@a1@@ + Number ) ) || ( @@a2@@ & Number ) != Number || ( @@v45@@ & Number ) != Number ) return Number L ; @@v182@@ = get_fpstatus_ptr ( Number ) ; @@v183@@ = get_ahp_flag ( ) ; v122 = neon_load_reg ( @@v45@@ , Number ) ; gen_helper_vfp_fcvt_f32_to_f16 ( v122 , v122 , @@v182@@ , @@v183@@ ) ; v141 = neon_load_reg ( @@v45@@ , Number ) ; gen_helper_vfp_fcvt_f32_to_f16 ( v141 , v141 , @@v182@@ , @@v183@@ ) ; tcg_gen_shli_i32 ( v141 , v141 , Number L ) ; tcg_gen_or_i32 ( v141 , v141 , v122 ) ; tcg_temp_free_i32 ( v122 ) ; v123 = neon_load_reg ( @@v45@@ , Number ) ; gen_helper_vfp_fcvt_f32_to_f16 ( v123 , v123 , @@v182@@ , @@v183@@ ) ; v158 = neon_load_reg ( @@v45@@ , Number ) ; neon_store_reg ( @@v43@@ , Number , v141 ) ; gen_helper_vfp_fcvt_f32_to_f16 ( v158 , v158 , @@v182@@ , @@v183@@ ) ; tcg_gen_shli_i32 ( v158 , v158 , Number L ) ; tcg_gen_or_i32 ( v158 , v158 , v123 ) ; neon_store_reg ( @@v43@@ , Number , v158 ) ; tcg_temp_free_i32 ( v123 ) ; tcg_temp_free_i32 ( @@v183@@ ) ; tcg_temp_free_ptr ( @@v182@@ ) ; return Number L ; case Number : if ( ! isar_feature_aa32_fp16_spconv ( * ( _QWORD * ) ( @@a1@@ + Number ) ) || ( @@a2@@ & Number ) != Number || ( @@v43@@ & Number ) != Number ) return Number L ; @@v180@@ = get_fpstatus_ptr ( Number ) ; @@v181@@ = get_ahp_flag ( ) ; v159 = tcg_temp_new_i32 ( ) ; v124 = neon_load_reg ( @@v45@@ , Number ) ; v142 = neon_load_reg ( @@v45@@ , Number ) ; tcg_gen_ext16u_i32 ( v159 , v124 ) ; gen_helper_vfp_fcvt_f16_to_f32 ( v159 , v159 , @@v180@@ , @@v181@@ ) ; neon_store_reg ( @@v43@@ , Number , v159 ) ; tcg_gen_shri_i32 ( v124 , v124 , Number L ) ; gen_helper_vfp_fcvt_f16_to_f32 ( v124 , v124 , @@v180@@ , @@v181@@ ) ; neon_store_reg ( @@v43@@ , Number , v124 ) ; v160 = tcg_temp_new_i32 ( ) ; tcg_gen_ext16u_i32 ( v160 , v142 ) ; gen_helper_vfp_fcvt_f16_to_f32 ( v160 , v160 , @@v180@@ , @@v181@@ ) ; neon_store_reg ( @@v43@@ , Number , v160 ) ; tcg_gen_shri_i32 ( v142 , v142 , Number L ) ; gen_helper_vfp_fcvt_f16_to_f32 ( v142 , v142 , @@v180@@ , @@v181@@ ) ; neon_store_reg ( @@v43@@ , Number , v142 ) ; tcg_temp_free_i32 ( @@v181@@ ) ; tcg_temp_free_ptr ( @@v180@@ ) ; break ; default : LABEL_853 : for ( jj = Number ; ; ++ jj ) { v36 = ( @@a2@@ & Number ) != Number ? Number : Number ; if ( v36 <= jj ) break ; v125 = neon_load_reg ( @@v45@@ , jj ) ; switch ( v95 ) { case Number : if ( v49 ) { if ( v49 != Number ) abort ( ) ; gen_swap_half ( v125 ) ; } else { tcg_gen_bswap32_i32 ( v125 , v125 ) ; } break ; case Number : gen_rev16 ( v125 , v125 ) ; break ; case Number : if ( v49 == Number ) { gen_helper_neon_cls_s32 ( v125 , v125 ) ; } else { if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) abort ( ) ; if ( v49 ) gen_helper_neon_cls_s16 ( v125 , v125 ) ; else gen_helper_neon_cls_s8 ( v125 , v125 ) ; } break ; case Number : if ( v49 == Number ) { tcg_gen_clzi_i32 ( v125 , v125 , Number L ) ; } else { if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) abort ( ) ; if ( v49 ) gen_helper_neon_clz_u16 ( v125 , v125 ) ; else gen_helper_neon_clz_u8 ( v125 , v125 ) ; } break ; case Number : gen_helper_neon_cnt_u8 ( v125 , v125 ) ; break ; case Number : if ( v49 == Number ) { gen_helper_neon_qabs_s32 ( v125 , cpu_env , v125 ) ; } else { if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) abort ( ) ; if ( v49 ) gen_helper_neon_qabs_s16 ( v125 , cpu_env , v125 ) ; else gen_helper_neon_qabs_s8 ( v125 , cpu_env , v125 ) ; } break ; case Number : if ( v49 == Number ) { gen_helper_neon_qneg_s32 ( v125 , cpu_env , v125 ) ; } else { if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) abort ( ) ; if ( v49 ) gen_helper_neon_qneg_s16 ( v125 , cpu_env , v125 ) ; else gen_helper_neon_qneg_s8 ( v125 , cpu_env , v125 ) ; } break ; case Number : case Number : v143 = tcg_const_i32 ( Number L ) ; if ( v49 == Number ) { gen_helper_neon_cgt_s32 ( v125 , v125 , v143 ) ; } else { if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) abort ( ) ; if ( v49 ) gen_helper_neon_cgt_s16 ( v125 , v125 , v143 ) ; else gen_helper_neon_cgt_s8 ( v125 , v125 , v143 ) ; } tcg_temp_free_i32 ( v143 ) ; if ( v95 == Number ) goto LABEL_898 ; break ; case Number : case Number : v144 = tcg_const_i32 ( Number L ) ; if ( v49 == Number ) { gen_helper_neon_cge_s32 ( v125 , v125 , v144 ) ; } else { if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) abort ( ) ; if ( v49 ) gen_helper_neon_cge_s16 ( v125 , v125 , v144 ) ; else gen_helper_neon_cge_s8 ( v125 , v125 , v144 ) ; } tcg_temp_free_i32 ( v144 ) ; if ( v95 == Number ) LABEL_898 : tcg_gen_not_i32 ( v125 , v125 ) ; break ; case Number : v145 = tcg_const_i32 ( Number L ) ; if ( v49 == Number ) { gen_helper_neon_ceq_u32 ( v125 , v125 , v145 ) ; } else { if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) abort ( ) ; if ( v49 ) gen_helper_neon_ceq_u16 ( v125 , v125 , v145 ) ; else gen_helper_neon_ceq_u8 ( v125 , v125 , v145 ) ; } tcg_temp_free_i32 ( v145 ) ; break ; case Number : @@v202@@ = get_fpstatus_ptr ( Number ) ; v146 = tcg_const_i32 ( Number L ) ; gen_helper_neon_cgt_f32 ( v125 , v125 , v146 , @@v202@@ ) ; tcg_temp_free_i32 ( v146 ) ; tcg_temp_free_ptr ( @@v202@@ ) ; break ; case Number : @@v201@@ = get_fpstatus_ptr ( Number ) ; v147 = tcg_const_i32 ( Number L ) ; gen_helper_neon_cge_f32 ( v125 , v125 , v147 , @@v201@@ ) ; tcg_temp_free_i32 ( v147 ) ; tcg_temp_free_ptr ( @@v201@@ ) ; break ; case Number : @@v200@@ = get_fpstatus_ptr ( Number ) ; v148 = tcg_const_i32 ( Number L ) ; gen_helper_neon_ceq_f32 ( v125 , v125 , v148 , @@v200@@ ) ; tcg_temp_free_i32 ( v148 ) ; tcg_temp_free_ptr ( @@v200@@ ) ; break ; case Number : @@v199@@ = get_fpstatus_ptr ( Number ) ; v149 = tcg_const_i32 ( Number L ) ; gen_helper_neon_cge_f32 ( v125 , v149 , v125 , @@v199@@ ) ; tcg_temp_free_i32 ( v149 ) ; tcg_temp_free_ptr ( @@v199@@ ) ; break ; case Number : @@v198@@ = get_fpstatus_ptr ( Number ) ; v150 = tcg_const_i32 ( Number L ) ; gen_helper_neon_cgt_f32 ( v125 , v150 , v125 , @@v198@@ ) ; tcg_temp_free_i32 ( v150 ) ; tcg_temp_free_ptr ( @@v198@@ ) ; break ; case Number : gen_helper_vfp_abss ( v125 , v125 ) ; break ; case Number : gen_helper_vfp_negs ( v125 , v125 ) ; break ; case Number : v151 = neon_load_reg ( @@v43@@ , jj ) ; neon_store_reg ( @@v45@@ , jj , v151 ) ; break ; case Number : v152 = neon_load_reg ( @@v43@@ , jj ) ; if ( v49 ) { if ( v49 != Number ) abort ( ) ; gen_neon_trn_u16 ( v125 , v152 ) ; } else { gen_neon_trn_u8 ( v125 , v152 ) ; } neon_store_reg ( @@v45@@ , jj , v152 ) ; break ; case Number : case Number : case Number : case Number : case Number : @@v196@@ = get_fpstatus_ptr ( Number ) ; if ( v95 == Number ) @@v82@@ = Number ; else @@v82@@ = fp_decode_rm [ ( v95 >> Number ) & Number ^ Number ] ; v34 = arm_rmode_to_sf ( @@v82@@ ) ; @@v197@@ = tcg_const_i32 ( v34 ) ; gen_helper_set_neon_rmode ( @@v197@@ , @@v197@@ , cpu_env ) ; gen_helper_rints ( v125 , v125 , @@v196@@ ) ; gen_helper_set_neon_rmode ( @@v197@@ , @@v197@@ , cpu_env ) ; tcg_temp_free_ptr ( @@v196@@ ) ; tcg_temp_free_i32 ( @@v197@@ ) ; break ; case Number : @@v195@@ = get_fpstatus_ptr ( Number ) ; gen_helper_rints_exact ( v125 , v125 , @@v195@@ ) ; tcg_temp_free_ptr ( @@v195@@ ) ; break ; case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : @@v42@@ = ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) == Number ; @@v192@@ = get_fpstatus_ptr ( Number ) ; @@v96@@ = fp_decode_rm [ ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) ] ; @@v193@@ = tcg_const_i32 ( Number L ) ; v35 = arm_rmode_to_sf ( @@v96@@ ) ; @@v194@@ = tcg_const_i32 ( v35 ) ; gen_helper_set_neon_rmode ( @@v194@@ , @@v194@@ , cpu_env ) ; if ( @@v42@@ ) gen_helper_vfp_tosls ( v125 , v125 , @@v193@@ , @@v192@@ ) ; else gen_helper_vfp_touls ( v125 , v125 , @@v193@@ , @@v192@@ ) ; gen_helper_set_neon_rmode ( @@v194@@ , @@v194@@ , cpu_env ) ; tcg_temp_free_i32 ( @@v194@@ ) ; tcg_temp_free_i32 ( @@v193@@ ) ; tcg_temp_free_ptr ( @@v192@@ ) ; break ; case Number : @@v191@@ = get_fpstatus_ptr ( Number ) ; gen_helper_recpe_u32 ( v125 , v125 , @@v191@@ ) ; tcg_temp_free_ptr ( @@v191@@ ) ; break ; case Number : @@v190@@ = get_fpstatus_ptr ( Number ) ; gen_helper_rsqrte_u32 ( v125 , v125 , @@v190@@ ) ; tcg_temp_free_ptr ( @@v190@@ ) ; break ; case Number : @@v189@@ = get_fpstatus_ptr ( Number ) ; gen_helper_recpe_f32 ( v125 , v125 , @@v189@@ ) ; tcg_temp_free_ptr ( @@v189@@ ) ; break ; case Number : @@v188@@ = get_fpstatus_ptr ( Number ) ; gen_helper_rsqrte_f32 ( v125 , v125 , @@v188@@ ) ; tcg_temp_free_ptr ( @@v188@@ ) ; break ; case Number : @@v187@@ = get_fpstatus_ptr ( Number ) ; gen_helper_vfp_sitos ( v125 , v125 , @@v187@@ ) ; tcg_temp_free_ptr ( @@v187@@ ) ; break ; case Number : @@v186@@ = get_fpstatus_ptr ( Number ) ; gen_helper_vfp_uitos ( v125 , v125 , @@v186@@ ) ; tcg_temp_free_ptr ( @@v186@@ ) ; break ; case Number : @@v185@@ = get_fpstatus_ptr ( Number ) ; gen_helper_vfp_tosizs ( v125 , v125 , @@v185@@ ) ; tcg_temp_free_ptr ( @@v185@@ ) ; break ; case Number : @@v184@@ = get_fpstatus_ptr ( Number ) ; gen_helper_vfp_touizs ( v125 , v125 , @@v184@@ ) ; tcg_temp_free_ptr ( @@v184@@ ) ; break ; default : abort ( ) ; } neon_store_reg ( @@v43@@ , jj , v125 ) ; } return Number L ; } } } else { v79 = ( @@a2@@ >> Number ) & Number ; if ( v79 > Number && ( @@a2@@ & Number ) == Number ) return Number L ; if ( ( @@a2@@ & Number ) != Number && ( ( ( unsigned __int8 ) @@v45@@ | ( unsigned __int8 ) ( @@v44@@ | @@v43@@ ) ) & Number ) != Number ) return Number L ; if ( v79 ) { if ( v79 == Number ) { neon_load_reg64 ( cpu_V0 , @@v44@@ + Number ) ; if ( ( @@a2@@ & Number ) != Number ) neon_load_reg64 ( cpu_V1 , @@v45@@ ) ; } else if ( ( @@a2@@ & Number ) != Number ) { v204 = tcg_temp_new_i64 ( ) ; if ( v79 > Number ) { neon_load_reg64 ( cpu_V0 , @@v44@@ + Number ) ; neon_load_reg64 ( v204 , @@v45@@ ) ; } else { neon_load_reg64 ( cpu_V0 , @@v44@@ ) ; neon_load_reg64 ( v204 , @@v44@@ + Number ) ; } tcg_gen_shri_i64 ( cpu_V0 , cpu_V0 , Number * ( BYTE1 ( @@a2@@ ) & Number ) ) ; tcg_gen_shli_i64 ( cpu_V1 , v204 , Number * ( Number - ( BYTE1 ( @@a2@@ ) & Number ) ) ) ; tcg_gen_or_i64 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; if ( v79 > Number ) { neon_load_reg64 ( cpu_V1 , @@v45@@ + Number ) ; v79 -= Number ; } else { neon_load_reg64 ( cpu_V1 , @@v45@@ ) ; } tcg_gen_shli_i64 ( cpu_V1 , cpu_V1 , Number * ( Number - v79 ) ) ; tcg_gen_shri_i64 ( v204 , v204 , Number * v79 ) ; tcg_gen_or_i64 ( cpu_V1 , cpu_V1 , v204 ) ; tcg_temp_free_i64 ( v204 ) ; } else { neon_load_reg64 ( cpu_V0 , @@v44@@ ) ; tcg_gen_shri_i64 ( cpu_V0 , cpu_V0 , Number * v79 ) ; neon_load_reg64 ( cpu_V1 , @@v45@@ ) ; tcg_gen_shli_i64 ( cpu_V1 , cpu_V1 , Number * ( Number - v79 ) ) ; tcg_gen_or_i64 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; } } else { neon_load_reg64 ( cpu_V0 , @@v44@@ ) ; if ( ( @@a2@@ & Number ) != Number ) neon_load_reg64 ( cpu_V1 , @@v44@@ + Number ) ; } neon_store_reg64 ( cpu_V0 , @@v43@@ ) ; if ( ( @@a2@@ & Number ) != Number ) neon_store_reg64 ( cpu_V1 , @@v43@@ + Number ) ; } return Number L ; } v94 = ( @@a2@@ >> Number ) & Number ; if ( ( @@a2@@ & Number ) != Number ) { if ( ! v46 ) return Number L ; switch ( v94 ) { case Number : case Number : case Number : case Number : case Number : goto LABEL_645 ; case Number : case Number : case Number : if ( v46 == Number ) return Number L ; LABEL_645 : if ( @@v86@@ && ( ( ( unsigned __int8 ) @@v44@@ | ( unsigned __int8 ) @@v43@@ ) & Number ) != Number ) return Number L ; v113 = neon_get_scalar ( v46 , @@v45@@ ) ; neon_store_scratch ( Number , v113 ) ; for ( kk = Number ; ; ++ kk ) { v28 = @@v86@@ ? Number : Number ; if ( v28 <= kk ) break ; v114 = neon_load_scratch ( Number ) ; v134 = neon_load_reg ( @@v44@@ , kk ) ; if ( v94 == Number ) { if ( v46 == Number ) gen_helper_neon_qdmulh_s16 ( v114 , cpu_env , v114 , v134 ) ; else gen_helper_neon_qdmulh_s32 ( v114 , cpu_env , v114 , v134 ) ; } else if ( v94 == Number ) { if ( v46 == Number ) gen_helper_neon_qrdmulh_s16 ( v114 , cpu_env , v114 , v134 ) ; else gen_helper_neon_qrdmulh_s32 ( v114 , cpu_env , v114 , v134 ) ; } else if ( ( @@a2@@ & Number ) != Number ) { @@v208@@ = get_fpstatus_ptr ( Number ) ; gen_helper_vfp_muls ( v114 , v114 , v134 , @@v208@@ ) ; tcg_temp_free_ptr ( @@v208@@ ) ; } else if ( v46 == Number ) { tcg_gen_mul_i32 ( v114 , v114 , v134 ) ; } else { gen_helper_neon_mul_u16 ( v114 , v114 , v134 ) ; } tcg_temp_free_i32 ( v134 ) ; if ( ( ( @@a2@@ >> Number ) & Number ) <= Number ) { v135 = neon_load_reg ( @@v43@@ , kk ) ; if ( v94 == Number ) { @@v209@@ = get_fpstatus_ptr ( Number ) ; gen_helper_vfp_subs ( v114 , v135 , v114 , @@v209@@ ) ; tcg_temp_free_ptr ( @@v209@@ ) ; } else { if ( ( ( @@a2@@ >> Number ) & Number ) > Number ) goto LABEL_673 ; if ( v94 == Number ) { gen_neon_rsb ( v46 , v114 , v135 ) ; } else if ( v94 ) { if ( v94 != Number ) LABEL_673 : abort ( ) ; @@v210@@ = get_fpstatus_ptr ( Number ) ; gen_helper_vfp_adds ( v114 , v114 , v135 , @@v210@@ ) ; tcg_temp_free_ptr ( @@v210@@ ) ; } else { gen_neon_add ( v46 , v114 , v135 ) ; } } tcg_temp_free_i32 ( v135 ) ; } neon_store_reg ( @@v43@@ , kk , v114 ) ; } break ; case Number : case Number : case Number : goto LABEL_683 ; case Number : case Number : case Number : if ( @@v86@@ == Number ) return Number L ; LABEL_683 : if ( ( @@v43@@ & Number ) != Number ) return Number L ; v136 = neon_get_scalar ( v46 , @@v45@@ ) ; v207 = tcg_temp_new_i32 ( ) ; tcg_gen_mov_i32 ( v207 , v136 ) ; v156 = neon_load_reg ( @@v44@@ , Number ) ; for ( ll = Number ; ll <= Number ; ++ ll ) { if ( ll ) { v136 = v207 ; gen_neon_mull ( cpu_V0 , v156 , v207 , v46 , @@v86@@ ) ; } else { v115 = neon_load_reg ( @@v44@@ , Number ) ; gen_neon_mull ( cpu_V0 , v115 , v136 , v46 , @@v86@@ ) ; } if ( v94 != Number ) neon_load_reg64 ( cpu_V1 , ll + @@v43@@ ) ; switch ( v94 ) { case Number : goto LABEL_693 ; case Number : case Number : gen_neon_addl_saturate ( cpu_V0 , cpu_V0 , v46 ) ; if ( v94 == Number ) gen_neon_negl ( cpu_V0 , v46 ) ; gen_neon_addl_saturate ( cpu_V0 , cpu_V1 , v46 ) ; break ; case Number : gen_neon_negl ( cpu_V0 , v46 ) ; LABEL_693 : gen_neon_addl ( v46 ) ; break ; case Number : break ; case Number : gen_neon_addl_saturate ( cpu_V0 , cpu_V0 , v46 ) ; break ; default : abort ( ) ; } neon_store_reg64 ( cpu_V0 , ll + @@v43@@ ) ; } return Number L ; case Number : case Number : if ( ! isar_feature_aa32_rdm ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v86@@ && ( ( ( unsigned __int8 ) @@v44@@ | ( unsigned __int8 ) @@v43@@ ) & Number ) != Number ) return Number L ; if ( v94 == Number ) { if ( v46 == Number ) @@v177@@ = gen_helper_neon_qrdmlah_s16 ; else @@v177@@ = gen_helper_neon_qrdmlah_s32 ; } else if ( v46 == Number ) { @@v177@@ = gen_helper_neon_qrdmlsh_s16 ; } else { @@v177@@ = gen_helper_neon_qrdmlsh_s32 ; } v131 = neon_get_scalar ( v46 , @@v45@@ ) ; for ( mm = Number ; ; ++ mm ) { v29 = @@v86@@ ? Number : Number ; if ( v29 <= mm ) break ; v116 = neon_load_reg ( @@v44@@ , mm ) ; v157 = neon_load_reg ( @@v43@@ , mm ) ; @@v177@@ ( v116 , cpu_env , v116 , v131 , v157 ) ; tcg_temp_free_i32 ( v157 ) ; neon_store_reg ( @@v43@@ , mm , v116 ) ; } goto LABEL_468 ; default : g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; goto LABEL_722 ; } return Number L ; } @@v97@@ = * ( ( _DWORD * ) & neon_3reg_wide_56205 + Number * v94 ) ; @@v98@@ = * ( ( _DWORD * ) & unk_4E484 + Number * v94 ) ; @@v99@@ = * ( ( _DWORD * ) & unk_4E488 + Number * v94 ) ; @@v100@@ = dword_4E48C [ Number * v94 ] ; if ( ( ( @@v100@@ >> v46 ) & Number ) != Number || ( @@v100@@ & Number ) != Number && @@v86@@ ) return Number L ; if ( @@v98@@ && ( @@v44@@ & Number ) != Number || @@v99@@ && ( @@v45@@ & Number ) != Number || ! @@v99@@ && ( @@v43@@ & Number ) != Number ) return Number L ; if ( v94 == Number && v46 == Number ) { if ( ! isar_feature_aa32_pmull ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v211@@ = tcg_temp_new_i64 ( ) ; @@v212@@ = tcg_temp_new_i64 ( ) ; @@v213@@ = tcg_temp_new_i64 ( ) ; neon_load_reg64 ( @@v211@@ , @@v44@@ ) ; neon_load_reg64 ( @@v212@@ , @@v45@@ ) ; gen_helper_neon_pmull_64_lo ( @@v213@@ , @@v211@@ , @@v212@@ ) ; neon_store_reg64 ( @@v213@@ , @@v43@@ ) ; gen_helper_neon_pmull_64_hi ( @@v213@@ , @@v211@@ , @@v212@@ ) ; neon_store_reg64 ( @@v213@@ , @@v43@@ + Number ) ; tcg_temp_free_i64 ( @@v211@@ ) ; tcg_temp_free_i64 ( @@v212@@ ) ; tcg_temp_free_i64 ( @@v213@@ ) ; return Number L ; } if ( @@v43@@ != @@v45@@ || @@v99@@ ) { if ( @@v43@@ == @@v44@@ && ! @@v98@@ ) { v27 = neon_load_reg ( @@v44@@ , Number ) ; neon_store_scratch ( Number , v27 ) ; } } else { v26 = neon_load_reg ( @@v45@@ , Number ) ; neon_store_scratch ( Number , v26 ) ; } v155 = Number L ; for ( nn = Number ; ; ++ nn ) { if ( nn > Number ) return Number L ; if ( @@v98@@ ) { neon_load_reg64 ( cpu_V0 , nn + @@v44@@ ) ; v111 = Number L ; } else { if ( nn == Number && @@v43@@ == @@v44@@ ) v111 = neon_load_scratch ( Number ) ; else v111 = neon_load_reg ( @@v44@@ , nn ) ; if ( @@v97@@ ) gen_neon_widen ( cpu_V0 , v111 , v46 , @@v86@@ ) ; } if ( @@v99@@ ) { neon_load_reg64 ( cpu_V1 , nn + @@v45@@ ) ; v133 = Number L ; } else { if ( nn == Number && @@v43@@ == @@v45@@ ) v133 = neon_load_scratch ( Number ) ; else v133 = neon_load_reg ( @@v45@@ , nn ) ; if ( @@v97@@ ) gen_neon_widen ( cpu_V1 , v133 , v46 , @@v86@@ ) ; } switch ( v94 ) { case Number : case Number : case Number : gen_neon_addl ( v46 ) ; break ; case Number : case Number : case Number : gen_neon_subl ( v46 ) ; break ; case Number : case Number : switch ( @@v86@@ | ( Number * v46 ) ) { case Number : gen_helper_neon_abdl_s16 ( cpu_V0 , v111 , v133 ) ; break ; case Number : gen_helper_neon_abdl_u16 ( cpu_V0 , v111 , v133 ) ; break ; case Number : gen_helper_neon_abdl_s32 ( cpu_V0 , v111 , v133 ) ; break ; case Number : gen_helper_neon_abdl_u32 ( cpu_V0 , v111 , v133 ) ; break ; case Number : gen_helper_neon_abdl_s64 ( cpu_V0 , v111 , v133 ) ; break ; case Number : gen_helper_neon_abdl_u64 ( cpu_V0 , v111 , v133 ) ; break ; default : abort ( ) ; } tcg_temp_free_i32 ( v133 ) ; tcg_temp_free_i32 ( v111 ) ; break ; case Number : case Number : case Number : case Number : case Number : case Number : gen_neon_mull ( cpu_V0 , v111 , v133 , v46 , @@v86@@ ) ; break ; case Number : gen_helper_neon_mull_p8 ( cpu_V0 , v111 , v133 ) ; tcg_temp_free_i32 ( v133 ) ; tcg_temp_free_i32 ( v111 ) ; break ; default : abort ( ) ; } if ( v94 == Number ) { gen_neon_addl_saturate ( cpu_V0 , cpu_V0 , v46 ) ; neon_store_reg64 ( cpu_V0 , nn + @@v43@@ ) ; continue ; } if ( v94 == Number || ( ( @@a2@@ >> Number ) & Number ) > Number && ( ( @@a2@@ >> Number ) & Number ) <= Number ) break ; if ( v94 != Number && v94 != Number ) goto LABEL_636 ; v112 = tcg_temp_new_i32 ( ) ; if ( @@v86@@ ) { if ( v46 == Number ) { tcg_gen_addi_i64 ( cpu_V0 , cpu_V0 , Number ) ; tcg_gen_extrh_i64_i32 ( v112 , cpu_V0 ) ; } else if ( v46 ) { gen_helper_neon_narrow_round_high_u16 ( v112 , cpu_V0 ) ; } else { gen_helper_neon_narrow_round_high_u8 ( v112 , cpu_V0 ) ; } } else if ( v46 == Number ) { tcg_gen_extrh_i64_i32 ( v112 , cpu_V0 ) ; } else if ( v46 ) { gen_helper_neon_narrow_high_u16 ( v112 , cpu_V0 ) ; } else { gen_helper_neon_narrow_high_u8 ( v112 , cpu_V0 ) ; } if ( nn ) { neon_store_reg ( @@v43@@ , Number , v155 ) ; neon_store_reg ( @@v43@@ , Number , v112 ) ; } else { v155 = v112 ; } LABEL_637 : ; } neon_load_reg64 ( cpu_V1 , nn + @@v43@@ ) ; switch ( v94 ) { case Number : case Number : goto LABEL_615 ; case Number : case Number : gen_neon_addl_saturate ( cpu_V0 , cpu_V0 , v46 ) ; if ( v94 == Number ) gen_neon_negl ( cpu_V0 , v46 ) ; gen_neon_addl_saturate ( cpu_V0 , cpu_V1 , v46 ) ; break ; case Number : gen_neon_negl ( cpu_V0 , v46 ) ; LABEL_615 : gen_neon_addl ( v46 ) ; break ; default : abort ( ) ; } LABEL_636 : neon_store_reg64 ( cpu_V0 , nn + @@v43@@ ) ; goto LABEL_637 ; } if ( ( @@a2@@ & Number ) == Number ) { if ( ( @@a2@@ & Number ) != Number && ( @@v43@@ & Number ) != Number ) return Number L ; v93 = ( @@a2@@ >> Number ) & Number ; v78 = ( @@a2@@ >> Number ) & Number | ( @@v86@@ << Number ) | @@a2@@ & Number ; switch ( v93 ) { case Number : case Number : v78 <<= Number ; goto LABEL_530 ; case Number : case Number : v78 <<= Number ; goto LABEL_530 ; case Number : case Number : v78 <<= Number ; goto LABEL_530 ; case Number : case Number : v78 |= v78 << Number ; goto LABEL_530 ; case Number : case Number : v78 = ( v78 << Number ) | ( v78 << Number ) ; goto LABEL_530 ; case Number : v23 = v78 << Number ; LOBYTE ( v23 ) = Number ; v78 = v23 ; goto LABEL_530 ; case Number : v78 = ( v78 << Number ) | Number ; goto LABEL_530 ; case Number : v78 |= ( v78 << Number ) | ( v78 << Number ) | ( v78 << Number ) ; if ( ( @@a2@@ & Number ) != Number ) v78 = ~ v78 ; goto LABEL_530 ; case Number : if ( ( @@a2@@ & Number ) != Number ) return Number L ; if ( ( v78 & Number ) != Number ) v24 = Number ; else v24 = Number ; v78 = ( v78 << Number ) & Number | ( v78 << Number ) & Number | v24 ; LABEL_530 : if ( ( @@a2@@ & Number ) != Number ) v78 = ~ v78 ; @@v101@@ = neon_reg_offset ( @@v43@@ , Number ) ; if ( ( @@a2@@ & Number ) != Number ) v25 = Number ; else v25 = Number ; if ( ( v93 & Number ) != Number && ( ( @@a2@@ >> Number ) & Number ) <= Number ) { if ( ( @@a2@@ & Number ) != Number ) tcg_gen_gvec_andi ( Number L , @@v101@@ , @@v101@@ , v78 , v25 , v25 ) ; else tcg_gen_gvec_ori ( Number L , @@v101@@ , @@v101@@ , v78 , v25 , v25 ) ; } else if ( v93 == Number && ( @@a2@@ & Number ) != Number ) { @@v214@@ = tcg_temp_new_i64 ( ) ; for ( i1 = Number ; i1 <= @@v85@@ ; ++ i1 ) { @@v176@@ = Number L ; for ( @@i2@@ = Number ; @@i2@@ <= Number ; ++ @@i2@@ ) { if ( ( v78 & ( Number << ( Number * i1 + @@i2@@ ) ) ) != Number ) @@v176@@ |= Number L << ( Number * ( unsigned __int8 ) @@i2@@ ) ; } tcg_gen_movi_i64 ( @@v214@@ , @@v176@@ ) ; neon_store_reg64 ( @@v214@@ , i1 + @@v43@@ ) ; } tcg_temp_free_i64 ( @@v214@@ ) ; } else { tcg_gen_gvec_dup32i ( @@v101@@ , v25 , v25 , v78 ) ; } break ; default : goto LABEL_530 ; } return Number L ; } v92 = ( @@a2@@ >> Number ) & Number ; if ( ( @@a2@@ & Number ) != Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) > Number ) return Number L ; i3 = Number ; } else { for ( i3 = Number ; ( @@a2@@ & ( Number << ( i3 + Number ) ) ) == Number ; -- i3 ) ; } v50 = HIWORD ( @@a2@@ ) & ( ( Number << ( i3 + Number ) ) - Number ) ; if ( ( ( @@a2@@ >> Number ) & Number ) > Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) > Number ) { if ( v92 == Number ) { if ( ( @@a2@@ & Number ) != Number || ( @@v43@@ & Number ) != Number ) return Number L ; v110 = neon_load_reg ( @@v45@@ , Number ) ; v132 = neon_load_reg ( @@v45@@ , Number ) ; for ( i4 = Number ; i4 <= Number ; ++ i4 ) { if ( i4 == Number ) v110 = v132 ; gen_neon_widen ( cpu_V0 , v110 , i3 , @@v86@@ ) ; if ( v50 ) { tcg_gen_shli_i64 ( cpu_V0 , cpu_V0 , v50 ) ; if ( i3 <= Number || ! @@v86@@ ) { if ( i3 ) { if ( i3 == Number ) v77 = Number >> ( Number - ( BYTE2 ( @@a2@@ ) & ( ( Number << ( i3 + Number ) ) - Number ) ) ) ; else v77 = Number >> ( Number - ( BYTE2 ( @@a2@@ ) & ( ( Number << ( i3 + Number ) ) - Number ) ) ) ; } else { v77 = ( Number >> ( Number - v50 ) << Number ) | ( Number >> ( Number - v50 ) ) ; } if ( i3 > Number ) @@v174@@ = v77 ; else @@v174@@ = ( ( unsigned __int64 ) v77 << Number ) | v77 ; tcg_gen_andi_i64 ( cpu_V0 , cpu_V0 , ~ @@v174@@ ) ; } } neon_store_reg64 ( cpu_V0 , i4 + @@v43@@ ) ; } } else { if ( ( ( @@a2@@ >> Number ) & Number ) <= Number ) return Number L ; if ( ( @@a2@@ & Number ) == Number || ( @@a2@@ & Number ) != Number && ( ( ( unsigned __int8 ) @@v45@@ | ( unsigned __int8 ) @@v43@@ ) & Number ) != Number ) return Number L ; if ( ( @@a2@@ & Number ) != Number ) { if ( @@v86@@ ) @@v175@@ = gen_helper_vfp_touls_round_to_zero ; else @@v175@@ = gen_helper_vfp_tosls_round_to_zero ; } else if ( @@v86@@ ) { @@v175@@ = gen_helper_vfp_ultos ; } else { @@v175@@ = gen_helper_vfp_sltos ; } @@v215@@ = get_fpstatus_ptr ( Number ) ; @@v216@@ = tcg_const_i32 ( ( unsigned int ) ( Number - v50 ) ) ; for ( i5 = Number ; ; ++ i5 ) { v22 = ( @@a2@@ & Number ) != Number ? Number : Number ; if ( v22 <= i5 ) break ; @@v217@@ = neon_load_reg ( @@v45@@ , i5 ) ; @@v175@@ ( @@v217@@ , @@v217@@ , @@v216@@ , @@v215@@ ) ; neon_store_reg ( @@v43@@ , i5 , @@v217@@ ) ; } tcg_temp_free_ptr ( @@v215@@ ) ; tcg_temp_free_i32 ( @@v216@@ ) ; } } else { if ( v92 == Number ) v21 = @@v86@@ == Number ; else v21 = HIBYTE ( @@a2@@ ) & Number ; @@v102@@ = v21 ; if ( ( @@v45@@ & Number ) != Number ) return Number L ; v54 = v50 - ( Number << ( i3 + Number ) ) ; v48 = i3 + Number ; if ( v48 == Number ) { v203 = tcg_const_i64 ( v54 ) ; neon_load_reg64 ( cpu_V0 , @@v45@@ ) ; neon_load_reg64 ( cpu_V1 , @@v45@@ + Number ) ; for ( i6 = Number ; i6 <= Number ; ++ i6 ) { if ( i6 ) @@v173@@ = cpu_V1 ; else @@v173@@ = cpu_V0 ; if ( ( @@a2@@ & Number ) != Number ) { if ( @@v102@@ ) gen_helper_neon_rshl_u64 ( cpu_V0 , @@v173@@ , v203 ) ; else gen_helper_neon_rshl_s64 ( cpu_V0 , @@v173@@ , v203 ) ; } else if ( @@v102@@ ) { gen_helper_neon_shl_u64 ( cpu_V0 , @@v173@@ , v203 ) ; } else { gen_helper_neon_shl_s64 ( cpu_V0 , @@v173@@ , v203 ) ; } v107 = tcg_temp_new_i32 ( ) ; gen_neon_narrow_op ( v92 == Number , @@v86@@ , Number , v107 , cpu_V0 ) ; neon_store_reg ( @@v43@@ , i6 , v107 ) ; } tcg_temp_free_i64 ( v203 ) ; } else { if ( v48 == Number ) v76 = ( ( unsigned __int16 ) v54 << Number ) | ( unsigned __int16 ) v54 ; else v76 = v54 ; v131 = tcg_const_i32 ( v76 ) ; v206 = neon_load_reg ( @@v45@@ + Number , Number ) ; v178 = neon_load_reg ( @@v45@@ + Number , Number ) ; for ( i7 = Number ; i7 <= Number ; ++ i7 ) { if ( i7 ) { v108 = v206 ; gen_neon_shift_narrow ( v48 , v206 , v131 , @@v85@@ , @@v102@@ ) ; } else { v108 = neon_load_reg ( @@v45@@ , Number ) ; gen_neon_shift_narrow ( v48 , v108 , v131 , @@v85@@ , @@v102@@ ) ; } if ( i7 ) { v154 = v178 ; gen_neon_shift_narrow ( v48 , v178 , v131 , @@v85@@ , @@v102@@ ) ; } else { v154 = neon_load_reg ( @@v45@@ , Number ) ; gen_neon_shift_narrow ( v48 , v154 , v131 , @@v85@@ , @@v102@@ ) ; } tcg_gen_concat_i32_i64 ( cpu_V0 , v108 , v154 ) ; tcg_temp_free_i32 ( v108 ) ; tcg_temp_free_i32 ( v154 ) ; v109 = tcg_temp_new_i32 ( ) ; gen_neon_narrow_op ( v92 == Number , @@v86@@ , v48 - Number , v109 , cpu_V0 ) ; neon_store_reg ( @@v43@@ , i7 , v109 ) ; } LABEL_468 : tcg_temp_free_i32 ( v131 ) ; } } return Number L ; } if ( ( @@a2@@ & Number ) != Number && ( ( ( unsigned __int8 ) @@v45@@ | ( unsigned __int8 ) @@v43@@ ) & Number ) != Number ) return Number L ; if ( ! @@v86@@ && ( v92 == Number || v92 == Number ) ) return Number L ; if ( ( ( @@a2@@ >> Number ) & Number ) <= Number ) v50 -= Number << ( i3 + Number ) ; if ( v92 == Number ) { if ( @@v86@@ ) { if ( v50 < Number << i3 ) tcg_gen_gvec_2i ( @@v88@@ , @@v90@@ , @@v87@@ , @@v87@@ , v50 , & sli_op [ Number * i3 ] ) ; } else if ( v50 < Number << i3 ) { tcg_gen_gvec_shli ( ( unsigned int ) i3 , @@v88@@ , @@v90@@ , v50 , @@v87@@ , @@v87@@ ) ; } else { tcg_gen_gvec_dup8i ( @@v88@@ , @@v87@@ , @@v87@@ , Number L ) ; } result = Number L ; } else { if ( ( ( @@a2@@ >> Number ) & Number ) > Number ) goto LABEL_382 ; if ( v92 == Number ) { if ( @@v86@@ ) { v53 = - v50 ; if ( v53 < Number << i3 ) tcg_gen_gvec_2i ( @@v88@@ , @@v90@@ , @@v87@@ , @@v87@@ , v53 , & sri_op [ Number * i3 ] ) ; result = Number L ; } else { result = Number L ; } } else if ( v92 ) { if ( v92 != Number ) { LABEL_382 : if ( i3 == Number ) { @@v73@@ = @@v85@@ + Number ; } else { if ( ( @@a2@@ & Number ) != Number ) v20 = Number ; else v20 = Number ; @@v73@@ = v20 ; } v75 = dup_const ( ( unsigned int ) i3 , v50 ) ; for ( i8 = Number ; i8 < @@v73@@ ; ++ i8 ) { if ( i3 == Number ) { neon_load_reg64 ( cpu_V0 , i8 + @@v45@@ ) ; tcg_gen_movi_i64 ( cpu_V1 , v75 ) ; if ( v92 == Number ) { if ( @@v86@@ ) gen_helper_neon_qshl_u64 ( cpu_V0 , cpu_env , cpu_V0 , cpu_V1 ) ; else gen_helper_neon_qshl_s64 ( cpu_V0 , cpu_env , cpu_V0 , cpu_V1 ) ; } else if ( ( ( @@a2@@ >> Number ) & Number ) <= Number ) { if ( @@v86@@ ) gen_helper_neon_rshl_u64 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; else gen_helper_neon_rshl_s64 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; } else { gen_helper_neon_qshlu_s64 ( cpu_V0 , cpu_env , cpu_V0 , cpu_V1 ) ; } if ( v92 == Number ) { neon_load_reg64 ( cpu_V1 , i8 + @@v43@@ ) ; tcg_gen_add_i64 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; } neon_store_reg64 ( cpu_V0 , i8 + @@v43@@ ) ; } else { v106 = neon_load_reg ( @@v45@@ , i8 ) ; v129 = tcg_temp_new_i32 ( ) ; tcg_gen_movi_i32 ( v129 , v75 ) ; if ( v92 == Number ) { switch ( @@v86@@ | ( Number * i3 ) ) { case Number : gen_helper_neon_qshl_s8 ( v106 , cpu_env , v106 , v129 ) ; goto LABEL_429 ; case Number : gen_helper_neon_qshl_u8 ( v106 , cpu_env , v106 , v129 ) ; goto LABEL_429 ; case Number : gen_helper_neon_qshl_s16 ( v106 , cpu_env , v106 , v129 ) ; goto LABEL_429 ; case Number : gen_helper_neon_qshl_u16 ( v106 , cpu_env , v106 , v129 ) ; goto LABEL_429 ; case Number : gen_helper_neon_qshl_s32 ( v106 , cpu_env , v106 , v129 ) ; goto LABEL_429 ; case Number : gen_helper_neon_qshl_u32 ( v106 , cpu_env , v106 , v129 ) ; goto LABEL_429 ; default : return Number L ; } } if ( ( ( @@a2@@ >> Number ) & Number ) <= Number ) { switch ( @@v86@@ | ( Number * i3 ) ) { case Number : gen_helper_neon_rshl_s8 ( v106 , v106 , v129 ) ; goto LABEL_429 ; case Number : gen_helper_neon_rshl_u8 ( v106 , v106 , v129 ) ; goto LABEL_429 ; case Number : gen_helper_neon_rshl_s16 ( v106 , v106 , v129 ) ; goto LABEL_429 ; case Number : gen_helper_neon_rshl_u16 ( v106 , v106 , v129 ) ; goto LABEL_429 ; case Number : gen_helper_neon_rshl_s32 ( v106 , v106 , v129 ) ; goto LABEL_429 ; case Number : gen_helper_neon_rshl_u32 ( v106 , v106 , v129 ) ; goto LABEL_429 ; default : return Number L ; } } if ( i3 == Number ) { gen_helper_neon_qshlu_s32 ( v106 , cpu_env , v106 , v129 ) ; } else { if ( i3 > Number ) goto LABEL_420 ; if ( i3 ) { if ( i3 != Number ) LABEL_420 : abort ( ) ; gen_helper_neon_qshlu_s16 ( v106 , cpu_env , v106 , v129 ) ; } else { gen_helper_neon_qshlu_s8 ( v106 , cpu_env , v106 , v129 ) ; } } LABEL_429 : tcg_temp_free_i32 ( v129 ) ; if ( v92 == Number ) { v130 = neon_load_reg ( @@v43@@ , i8 ) ; gen_neon_add ( i3 , v106 , v130 ) ; tcg_temp_free_i32 ( v130 ) ; } neon_store_reg ( @@v43@@ , i8 , v106 ) ; } } return Number L ; } v52 = - v50 ; if ( @@v86@@ ) { if ( v52 < Number << i3 ) tcg_gen_gvec_2i ( @@v88@@ , @@v90@@ , @@v87@@ , @@v87@@ , v52 , & usra_op [ Number * i3 ] ) ; } else { v19 = ( Number << i3 ) - Number ; if ( v52 <= v19 ) v19 = v52 ; tcg_gen_gvec_2i ( @@v88@@ , @@v90@@ , @@v87@@ , @@v87@@ , v19 , & ssra_op [ Number * i3 ] ) ; } result = Number L ; } else { v51 = - v50 ; if ( @@v86@@ ) { if ( v51 < Number << i3 ) tcg_gen_gvec_shri ( ( unsigned int ) i3 , @@v88@@ , @@v90@@ , v51 , @@v87@@ , @@v87@@ ) ; else tcg_gen_gvec_dup8i ( @@v88@@ , @@v87@@ , @@v87@@ , Number L ) ; } else { v18 = ( Number << i3 ) - Number ; if ( v51 <= v18 ) v18 = v51 ; tcg_gen_gvec_sari ( ( unsigned int ) i3 , @@v88@@ , @@v90@@ , v18 , @@v87@@ , @@v87@@ ) ; } result = Number L ; } } return result ; }", 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|
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"location": "s96"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,017 |
[
"{\"name\": \"bswap32\", \"code\": \"__int64 __fastcall bswap32 ( unsigned int @@a1@@ ) { return _bswap_32 ( @@a1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"extract32\", \"code\": \"__int64 __fastcall extract32 ( unsigned int @@a1@@ , int @@a2@@ , int @@a3@@ ) { if ( @@a2@@ < Number || @@a3@@ <= Number || @@a3@@ > Number - @@a2@@ ) _assert_fail ( String , String , Number , String ) ; return ( @@a1@@ >> @@a2@@ ) & ( Number >> ( Number - @@a3@@ ) ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"isar_feature_aa32_aes\", \"code\": \"bool __fastcall isar_feature_aa32_aes ( __int64 @@a1@@ ) { return ( unsigned int ) extract32 ( * ( _DWORD * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_pmull\", \"code\": \"bool __fastcall isar_feature_aa32_pmull ( __int64 @@a1@@ ) { return ( unsigned int ) extract32 ( * ( _DWORD * ) ( @@a1@@ + Number ) , Number , Number ) > Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_sha1\", \"code\": \"bool __fastcall isar_feature_aa32_sha1 ( __int64 @@a1@@ ) { return ( unsigned int ) extract32 ( * ( _DWORD * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_sha2\", \"code\": \"bool __fastcall isar_feature_aa32_sha2 ( __int64 @@a1@@ ) { return ( unsigned int ) extract32 ( * ( _DWORD * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_rdm\", \"code\": \"bool __fastcall isar_feature_aa32_rdm ( __int64 @@a1@@ ) { return ( unsigned int ) extract32 ( * ( _DWORD * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_fp16_spconv\", \"code\": \"bool __fastcall isar_feature_aa32_fp16_spconv ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"syn_simd_access_trap\", \"code\": \"__int64 __fastcall syn_simd_access_trap ( int @@a1@@ , int @@a2@@ , char @@a3@@ ) { int v3 ; if ( @@a3@@ ) v3 = Number ; else v3 = Number ; return ( @@a1@@ << Number ) | v3 | ( @@a2@@ << Number ) | Number ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_i64\", \"code\": \"__int64 __fastcall tcg_temp_free_i64 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i64_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_ptr\", \"code\": \"__int64 __fastcall tcg_temp_free_ptr ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_ptr_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_temp_new_i64\", \"code\": \"__int64 tcg_temp_new_i64 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i64 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_adds\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_adds ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_adds , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_subs\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_subs ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_subs , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_muls\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_muls ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_muls , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_maxs\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_maxs ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_maxs , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_mins\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_mins ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_mins , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_maxnums\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_maxnums ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_maxnums , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_minnums\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_minnums ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_minnums , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_negs\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_negs ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i32_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_negs , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_abss\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_abss ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i32_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_abss , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_uitos\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_uitos ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_uitos , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_sitos\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_sitos ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_sitos , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_touizs\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_touizs ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_touizs , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_tosizs\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_tosizs ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_tosizs , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_tosls_round_to_zero\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_tosls_round_to_zero ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_tosls_round_to_zero , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_touls_round_to_zero\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_touls_round_to_zero ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_touls_round_to_zero , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_tosls\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_tosls ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_tosls , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_touls\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_touls ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_touls , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_sltos\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_sltos ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_sltos , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_ultos\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_ultos ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_ultos , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_set_neon_rmode\", \"code\": \"unsigned __int64 __fastcall gen_helper_set_neon_rmode ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_set_neon_rmode , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_fcvt_f16_to_f32\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_fcvt_f16_to_f32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_fcvt_f16_to_f32 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_fcvt_f32_to_f16\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_fcvt_f32_to_f16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_fcvt_f32_to_f16 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_muladds\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_muladds ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ ) { __int64 @@v5@@ ; __int64 @@v10@@ [ Number ] ; unsigned __int64 @@v11@@ ; @@v11@@ = __readfsqword ( Number ) ; @@v10@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v10@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v10@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v10@@ [ Number ] = tcgv_ptr_temp ( @@a5@@ ) ; @@v5@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_muladds , @@v5@@ , Number L , @@v10@@ ) ; return __readfsqword ( Number ) ^ @@v11@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r72\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v10\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_recps_f32\", \"code\": \"unsigned __int64 __fastcall gen_helper_recps_f32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_recps_f32 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_rsqrts_f32\", \"code\": \"unsigned __int64 __fastcall gen_helper_rsqrts_f32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_rsqrts_f32 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_recpe_f32\", \"code\": \"unsigned __int64 __fastcall gen_helper_recpe_f32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_recpe_f32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_rsqrte_f32\", \"code\": \"unsigned __int64 __fastcall gen_helper_rsqrte_f32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_rsqrte_f32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_recpe_u32\", \"code\": \"unsigned __int64 __fastcall gen_helper_recpe_u32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_recpe_u32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_rsqrte_u32\", \"code\": \"unsigned __int64 __fastcall gen_helper_rsqrte_u32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_rsqrte_u32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_tbl\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_tbl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ ) { __int64 @@v5@@ ; __int64 @@v10@@ [ Number ] ; unsigned __int64 @@v11@@ ; @@v11@@ = __readfsqword ( Number ) ; @@v10@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v10@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v10@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v10@@ [ Number ] = tcgv_i32_temp ( @@a5@@ ) ; @@v5@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_tbl , @@v5@@ , Number L , @@v10@@ ) ; return __readfsqword ( Number ) ^ @@v11@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r72\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v10\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_rints_exact\", \"code\": \"unsigned __int64 __fastcall gen_helper_rints_exact ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_rints_exact , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_rints\", \"code\": \"unsigned __int64 __fastcall gen_helper_rints ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_rints , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_hadd_s8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_hadd_s8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_hadd_s8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_hadd_u8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_hadd_u8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_hadd_u8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_hadd_s16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_hadd_s16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_hadd_s16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_hadd_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_hadd_u16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_hadd_u16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_hadd_s32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_hadd_s32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_hadd_s32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_hadd_u32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_hadd_u32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_hadd_u32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_rhadd_s8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_rhadd_s8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_rhadd_s8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_rhadd_u8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_rhadd_u8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_rhadd_u8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_rhadd_s16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_rhadd_s16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_rhadd_s16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_rhadd_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_rhadd_u16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_rhadd_u16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_rhadd_s32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_rhadd_s32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_rhadd_s32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_rhadd_u32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_rhadd_u32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_rhadd_u32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_hsub_s8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_hsub_s8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_hsub_s8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_hsub_u8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_hsub_u8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_hsub_u8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_hsub_s16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_hsub_s16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_hsub_s16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_hsub_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_hsub_u16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_hsub_u16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_hsub_s32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_hsub_s32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_hsub_s32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_hsub_u32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_hsub_u32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_hsub_u32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_cgt_s8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_cgt_s8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_cgt_s8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_cgt_s16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_cgt_s16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_cgt_s16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_cgt_s32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_cgt_s32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_cgt_s32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_cge_s8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_cge_s8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_cge_s8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_cge_s16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_cge_s16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_cge_s16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_cge_s32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_cge_s32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_cge_s32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_pmin_u8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_pmin_u8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_pmin_u8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_pmin_s8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_pmin_s8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_pmin_s8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_pmin_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_pmin_u16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_pmin_u16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_pmin_s16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_pmin_s16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_pmin_s16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_pmax_u8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_pmax_u8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_pmax_u8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_pmax_s8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_pmax_s8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_pmax_s8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_pmax_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_pmax_u16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_pmax_u16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_pmax_s16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_pmax_s16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_pmax_s16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_abd_u8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_abd_u8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_abd_u8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_abd_s8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_abd_s8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_abd_s8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_abd_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_abd_u16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_abd_u16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_abd_s16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_abd_s16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_abd_s16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_abd_u32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_abd_u32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_abd_u32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_abd_s32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_abd_s32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_abd_s32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_shl_u8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_shl_u8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_shl_u8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_shl_s8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_shl_s8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_shl_s8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_shl_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_shl_u16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_shl_u16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_shl_s16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_shl_s16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_shl_s16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_shl_u32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_shl_u32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_shl_u32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_shl_s32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_shl_s32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_shl_s32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_shl_u64\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_shl_u64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_shl_u64 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_shl_s64\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_shl_s64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_shl_s64 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_rshl_u8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_rshl_u8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_rshl_u8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_rshl_s8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_rshl_s8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_rshl_s8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_rshl_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_rshl_u16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_rshl_u16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_rshl_s16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_rshl_s16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_rshl_s16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_rshl_u32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_rshl_u32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_rshl_u32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_rshl_s32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_rshl_s32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_rshl_s32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_rshl_u64\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_rshl_u64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_rshl_u64 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_rshl_s64\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_rshl_s64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_rshl_s64 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qshl_u8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qshl_u8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qshl_u8 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qshl_s8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qshl_s8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qshl_s8 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qshl_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qshl_u16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qshl_u16 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qshl_s16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qshl_s16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qshl_s16 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qshl_u32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qshl_u32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qshl_u32 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qshl_s32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qshl_s32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qshl_s32 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qshl_u64\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qshl_u64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qshl_u64 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qshl_s64\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qshl_s64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qshl_s64 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qshlu_s8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qshlu_s8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qshlu_s8 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qshlu_s16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qshlu_s16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qshlu_s16 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qshlu_s32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qshlu_s32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qshlu_s32 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qshlu_s64\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qshlu_s64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qshlu_s64 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qrshl_u8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qrshl_u8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qrshl_u8 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qrshl_s8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qrshl_s8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qrshl_s8 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qrshl_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qrshl_u16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qrshl_u16 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qrshl_s16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qrshl_s16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qrshl_s16 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qrshl_u32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qrshl_u32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qrshl_u32 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qrshl_s32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qrshl_s32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qrshl_s32 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qrshl_u64\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qrshl_u64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qrshl_u64 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qrshl_s64\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qrshl_s64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qrshl_s64 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_padd_u8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_padd_u8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_padd_u8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_padd_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_padd_u16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_padd_u16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_mul_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_mul_u16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_mul_u16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_mul_p8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_mul_p8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_mul_p8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_mull_p8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_mull_p8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_mull_p8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_ceq_u8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_ceq_u8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_ceq_u8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_ceq_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_ceq_u16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_ceq_u16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_ceq_u32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_ceq_u32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_ceq_u32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_clz_u8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_clz_u8 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i32_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_clz_u8 , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_clz_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_clz_u16 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i32_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_clz_u16 , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_cls_s8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_cls_s8 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i32_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_cls_s8 , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_cls_s16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_cls_s16 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i32_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_cls_s16 , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_cls_s32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_cls_s32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i32_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_cls_s32 , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_cnt_u8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_cnt_u8 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i32_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_cnt_u8 , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qdmulh_s16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qdmulh_s16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qdmulh_s16 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qrdmulh_s16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qrdmulh_s16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qrdmulh_s16 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qrdmlah_s16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qrdmlah_s16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ ) { __int64 @@v5@@ ; __int64 @@v10@@ [ Number ] ; unsigned __int64 @@v11@@ ; @@v11@@ = __readfsqword ( Number ) ; @@v10@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v10@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v10@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v10@@ [ Number ] = tcgv_i32_temp ( @@a5@@ ) ; @@v5@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qrdmlah_s16 , @@v5@@ , Number L , @@v10@@ ) ; return __readfsqword ( Number ) ^ @@v11@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r72\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v10\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qrdmlsh_s16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qrdmlsh_s16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ ) { __int64 @@v5@@ ; __int64 @@v10@@ [ Number ] ; unsigned __int64 @@v11@@ ; @@v11@@ = __readfsqword ( Number ) ; @@v10@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v10@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v10@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v10@@ [ Number ] = tcgv_i32_temp ( @@a5@@ ) ; @@v5@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qrdmlsh_s16 , @@v5@@ , Number L , @@v10@@ ) ; return __readfsqword ( Number ) ^ @@v11@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r72\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v10\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qdmulh_s32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qdmulh_s32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qdmulh_s32 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qrdmulh_s32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qrdmulh_s32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qrdmulh_s32 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qrdmlah_s32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qrdmlah_s32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ ) { __int64 @@v5@@ ; __int64 @@v10@@ [ Number ] ; unsigned __int64 @@v11@@ ; @@v11@@ = __readfsqword ( Number ) ; @@v10@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v10@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v10@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v10@@ [ Number ] = tcgv_i32_temp ( @@a5@@ ) ; @@v5@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qrdmlah_s32 , @@v5@@ , Number L , @@v10@@ ) ; return __readfsqword ( Number ) ^ @@v11@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r72\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v10\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qrdmlsh_s32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qrdmlsh_s32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ ) { __int64 @@v5@@ ; __int64 @@v10@@ [ Number ] ; unsigned __int64 @@v11@@ ; @@v11@@ = __readfsqword ( Number ) ; @@v10@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v10@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v10@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v10@@ [ Number ] = tcgv_i32_temp ( @@a5@@ ) ; @@v5@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qrdmlsh_s32 , @@v5@@ , Number L , @@v10@@ ) ; return __readfsqword ( Number ) ^ @@v11@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r72\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v10\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_narrow_high_u8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_narrow_high_u8 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i64_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_narrow_high_u8 , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_narrow_high_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_narrow_high_u16 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i64_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_narrow_high_u16 , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_narrow_round_high_u8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_narrow_round_high_u8 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i64_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_narrow_round_high_u8 , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_narrow_round_high_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_narrow_round_high_u16 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i64_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_narrow_round_high_u16 , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_paddl_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_paddl_u16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_paddl_u16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_paddl_u32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_paddl_u32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_paddl_u32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_abdl_u16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_abdl_u16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_abdl_u16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_abdl_s16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_abdl_s16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_abdl_s16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_abdl_u32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_abdl_u32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_abdl_u32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_abdl_s32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_abdl_s32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_abdl_s32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_abdl_u64\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_abdl_u64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_abdl_u64 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_abdl_s64\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_abdl_s64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_abdl_s64 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qabs_s8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qabs_s8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qabs_s8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qabs_s16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qabs_s16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qabs_s16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qabs_s32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qabs_s32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qabs_s32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qneg_s8\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qneg_s8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qneg_s8 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qneg_s16\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qneg_s16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qneg_s16 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_qneg_s32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_qneg_s32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_qneg_s32 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_abd_f32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_abd_f32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_abd_f32 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_ceq_f32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_ceq_f32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_ceq_f32 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_cge_f32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_cge_f32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_cge_f32 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_cgt_f32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_cgt_f32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_cgt_f32 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_acge_f32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_acge_f32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_acge_f32 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_acgt_f32\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_acgt_f32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_acgt_f32 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_crypto_aese\", \"code\": \"unsigned __int64 __fastcall gen_helper_crypto_aese ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ [ Number ] ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v5@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v5@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; tcg_gen_callN ( & helper_crypto_aese , Number L , Number L , @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_crypto_aesmc\", \"code\": \"unsigned __int64 __fastcall gen_helper_crypto_aesmc ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ [ Number ] ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v5@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v5@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; tcg_gen_callN ( & helper_crypto_aesmc , Number L , Number L , @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_crypto_sha1_3reg\", \"code\": \"unsigned __int64 __fastcall gen_helper_crypto_sha1_3reg ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v7@@ [ Number ] ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; @@v7@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v7@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v7@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v7@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; tcg_gen_callN ( & helper_crypto_sha1_3reg , Number L , Number L , @@v7@@ ) ; return __readfsqword ( Number ) ^ @@v8@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_crypto_sha1h\", \"code\": \"unsigned __int64 __fastcall gen_helper_crypto_sha1h ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; tcg_gen_callN ( & helper_crypto_sha1h , Number L , Number L , @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_crypto_sha1su1\", \"code\": \"unsigned __int64 __fastcall gen_helper_crypto_sha1su1 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; tcg_gen_callN ( & helper_crypto_sha1su1 , Number L , Number L , @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_crypto_sha256h\", \"code\": \"unsigned __int64 __fastcall gen_helper_crypto_sha256h ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ [ Number ] ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v5@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v5@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; tcg_gen_callN ( & helper_crypto_sha256h , Number L , Number L , @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_crypto_sha256h2\", \"code\": \"unsigned __int64 __fastcall gen_helper_crypto_sha256h2 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ [ Number ] ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v5@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v5@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; tcg_gen_callN ( & helper_crypto_sha256h2 , Number L , Number L , @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_crypto_sha256su0\", \"code\": \"unsigned __int64 __fastcall gen_helper_crypto_sha256su0 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; tcg_gen_callN ( & helper_crypto_sha256su0 , Number L , Number L , @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_crypto_sha256su1\", \"code\": \"unsigned __int64 __fastcall gen_helper_crypto_sha256su1 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ [ Number ] ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v5@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v5@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; tcg_gen_callN ( & helper_crypto_sha256su1 , Number L , Number L , @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_pmull_64_lo\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_pmull_64_lo ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_pmull_64_lo , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_neon_pmull_64_hi\", \"code\": \"unsigned __int64 __fastcall gen_helper_neon_pmull_64_hi ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_neon_pmull_64_hi , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_gvec_qrdmlah_s16\", \"code\": \"unsigned __int64 __fastcall gen_helper_gvec_qrdmlah_s16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ ) { __int64 @@v9@@ [ Number ] ; unsigned __int64 @@v10@@ ; @@v10@@ = __readfsqword ( Number ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v9@@ [ Number ] = tcgv_i32_temp ( @@a5@@ ) ; tcg_gen_callN ( & helper_gvec_qrdmlah_s16 , Number L , Number L , @@v9@@ ) ; return __readfsqword ( Number ) ^ @@v10@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_gvec_qrdmlsh_s16\", \"code\": \"unsigned __int64 __fastcall gen_helper_gvec_qrdmlsh_s16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ ) { __int64 @@v9@@ [ Number ] ; unsigned __int64 @@v10@@ ; @@v10@@ = __readfsqword ( Number ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v9@@ [ Number ] = tcgv_i32_temp ( @@a5@@ ) ; tcg_gen_callN ( & helper_gvec_qrdmlsh_s16 , Number L , Number L , @@v9@@ ) ; return __readfsqword ( Number ) ^ @@v10@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_gvec_qrdmlah_s32\", \"code\": \"unsigned __int64 __fastcall gen_helper_gvec_qrdmlah_s32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ ) { __int64 @@v9@@ [ Number ] ; unsigned __int64 @@v10@@ ; @@v10@@ = __readfsqword ( Number ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v9@@ [ Number ] = tcgv_i32_temp ( @@a5@@ ) ; tcg_gen_callN ( & helper_gvec_qrdmlah_s32 , Number L , Number L , @@v9@@ ) ; return __readfsqword ( Number ) ^ @@v10@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_gvec_qrdmlsh_s32\", \"code\": \"unsigned __int64 __fastcall gen_helper_gvec_qrdmlsh_s32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ ) { __int64 @@v9@@ [ Number ] ; unsigned __int64 @@v10@@ ; @@v10@@ = __readfsqword ( Number ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v9@@ [ Number ] = tcgv_i32_temp ( @@a5@@ ) ; tcg_gen_callN ( & helper_gvec_qrdmlsh_s32 , Number L , Number L , @@v9@@ ) ; return __readfsqword ( Number ) ^ @@v10@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_mov_i32\", \"code\": \"__int64 __fastcall tcg_gen_mov_i32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@result@@ ; @@result@@ = @@a1@@ ; if ( @@a1@@ != @@a2@@ ) @@result@@ = tcg_gen_op2_i32 ( Number , @@a1@@ , @@a2@@ ) ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_gen_movi_i32\", \"code\": \"__int64 __fastcall tcg_gen_movi_i32 ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_op2i_i32 ( Number , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_add_i32\", \"code\": \"__int64 __fastcall tcg_gen_add_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_or_i32\", \"code\": \"__int64 __fastcall tcg_gen_or_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_mul_i32\", \"code\": \"__int64 __fastcall tcg_gen_mul_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_not_i32\", \"code\": \"__int64 __fastcall tcg_gen_not_i32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { return tcg_gen_op2_i32 ( Number , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_movi_i64\", \"code\": \"__int64 __fastcall tcg_gen_movi_i64 ( __int64 @@a1@@ , __int64 @@a2@@ ) { return tcg_gen_op2i_i64 ( Number , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_add_i64\", \"code\": \"__int64 __fastcall tcg_gen_add_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_or_i64\", \"code\": \"__int64 __fastcall tcg_gen_or_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"get_ahp_flag\", \"code\": \"__int64 get_ahp_flag ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_i32 ( ) ; tcg_gen_ld_i32 ( @@v1@@ , cpu_env , Number L ) ; tcg_gen_extract_i32 ( @@v1@@ , @@v1@@ , Number L , Number L ) ; return @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_exception\", \"code\": \"__int64 __fastcall gen_exception ( unsigned int @@a1@@ , unsigned int @@a2@@ , unsigned int @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_const_i32 ( @@a1@@ ) ; @@v6@@ = tcg_const_i32 ( @@a2@@ ) ; @@v7@@ = tcg_const_i32 ( @@a3@@ ) ; gen_helper_exception_with_syndrome ( cpu_env , @@v5@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_rev16\", \"code\": \"__int64 __fastcall gen_rev16 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v4@@ ; __int64 @@v5@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v5@@ = tcg_const_i32 ( Number L ) ; tcg_gen_shri_i32 ( @@v4@@ , @@a2@@ , Number L ) ; tcg_gen_and_i32 ( @@v4@@ , @@v4@@ , @@v5@@ ) ; tcg_gen_and_i32 ( @@a2@@ , @@a2@@ , @@v5@@ ) ; tcg_gen_shli_i32 ( @@a2@@ , @@a2@@ , Number L ) ; tcg_gen_or_i32 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; return tcg_temp_free_i32 ( @@v4@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_swap_half\", \"code\": \"__int64 __fastcall gen_swap_half ( __int64 @@a1@@ ) { return tcg_gen_rotri_i32 ( @@a1@@ , @@a1@@ , Number L ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_shl\", \"code\": \"__int64 __fastcall gen_shl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shl_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_shr\", \"code\": \"__int64 __fastcall gen_shr ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shr_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_exception_insn\", \"code\": \"__int64 __fastcall gen_exception_insn ( __int64 @@a1@@ , int @@a2@@ , unsigned int @@a3@@ , unsigned int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@result@@ ; gen_set_condexec ( @@a1@@ ) ; gen_set_pc_im ( @@a1@@ , @@a2@@ ) ; gen_exception ( @@a3@@ , @@a4@@ , @@a5@@ ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"get_fpstatus_ptr\", \"code\": \"__int64 __fastcall get_fpstatus_ptr ( int @@a1@@ ) { int @@v2@@ ; __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_ptr ( ) ; if ( @@a1@@ ) @@v2@@ = Number ; else @@v2@@ = Number ; tcg_gen_addi_ptr ( @@v3@@ , cpu_env , @@v2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_reg_offset\", \"code\": \"__int64 __fastcall neon_reg_offset ( int @@a1@@ , int @@a2@@ ) { return vfp_reg_offset ( Number , Number * @@a1@@ + @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"neon_element_offset\", \"code\": \"__int64 __fastcall neon_element_offset ( int @@a1@@ , int @@a2@@ , char @@a3@@ ) { return ( Number << @@a3@@ ) * @@a2@@ + neon_reg_offset ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"neon_load_reg\", \"code\": \"__int64 __fastcall neon_load_reg ( int @@a1@@ , int @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v2@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_ld_i32 ( @@v4@@ , cpu_env , @@v2@@ ) ; return @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_store_reg\", \"code\": \"__int64 __fastcall neon_store_reg ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; @@v3@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_st_i32 ( @@a3@@ , cpu_env , @@v3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_load_reg64\", \"code\": \"__int64 __fastcall neon_load_reg64 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_store_reg64\", \"code\": \"__int64 __fastcall neon_store_reg64 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_st_i64 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"vfp_reg_ptr\", \"code\": \"__int64 __fastcall vfp_reg_ptr ( char @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; @@v4@@ = tcg_temp_new_ptr ( ) ; @@v2@@ = vfp_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_addi_ptr ( @@v4@@ , cpu_env , @@v2@@ ) ; return @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_neon_add\", \"code\": \"__int64 __fastcall gen_neon_add ( int @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { if ( @@a1@@ == Number ) return tcg_gen_add_i32 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; if ( @@a1@@ > Number ) goto LABEL_9 ; if ( ! @@a1@@ ) return gen_helper_neon_add_u8 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; if ( @@a1@@ != Number ) LABEL_9 : abort ( ) ; return gen_helper_neon_add_u16 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_neon_rsb\", \"code\": \"__int64 __fastcall gen_neon_rsb ( int @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@result@@ ; if ( @@a1@@ == Number ) return tcg_gen_sub_i32 ( @@a2@@ , @@a3@@ , @@a2@@ ) ; if ( @@a1@@ <= Number ) { if ( @@a1@@ ) { if ( @@a1@@ == Number ) @@result@@ = gen_helper_neon_sub_u16 ( @@a2@@ , @@a3@@ , @@a2@@ ) ; } else { @@result@@ = gen_helper_neon_sub_u8 ( @@a2@@ , @@a3@@ , @@a2@@ ) ; } } return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_load_scratch\", \"code\": \"__int64 __fastcall neon_load_scratch ( int @@a1@@ ) { __int64 @@v2@@ ; @@v2@@ = tcg_temp_new_i32 ( ) ; tcg_gen_ld_i32 ( @@v2@@ , cpu_env , Number * ( @@a1@@ + Number L ) ) ; return @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_store_scratch\", \"code\": \"__int64 __fastcall neon_store_scratch ( int @@a1@@ , __int64 @@a2@@ ) { tcg_gen_st_i32 ( @@a2@@ , cpu_env , Number * ( @@a1@@ + Number L ) ) ; return tcg_temp_free_i32 ( @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"neon_get_scalar\", \"code\": \"__int64 __fastcall neon_get_scalar ( int @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; if ( @@a1@@ != Number ) return neon_load_reg ( @@a2@@ & Number , @@a2@@ >> Number ) ; @@v3@@ = neon_load_reg ( @@a2@@ & Number , @@a2@@ >> Number ) ; if ( ( @@a2@@ & Number ) != Number ) gen_neon_dup_high16 ( @@v3@@ ) ; else gen_neon_dup_low16 ( @@v3@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_neon_unzip\", \"code\": \"__int64 __fastcall gen_neon_unzip ( unsigned int @@a1@@ , unsigned int @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int64 @@v7@@ ; __int64 @@v8@@ ; if ( ! @@a4@@ && @@a3@@ == Number ) return Number L ; @@v7@@ = vfp_reg_ptr ( Number , @@a1@@ ) ; @@v8@@ = vfp_reg_ptr ( Number , @@a2@@ ) ; if ( @@a4@@ ) { if ( @@a3@@ == Number ) { gen_helper_neon_qunzip32 ( @@v7@@ , @@v8@@ ) ; } else { if ( @@a3@@ > Number ) goto LABEL_13 ; if ( @@a3@@ ) { if ( @@a3@@ != Number ) LABEL_13 : abort ( ) ; gen_helper_neon_qunzip16 ( @@v7@@ , @@v8@@ ) ; } else { gen_helper_neon_qunzip8 ( @@v7@@ , @@v8@@ ) ; } } } else if ( @@a3@@ ) { if ( @@a3@@ != Number ) abort ( ) ; gen_helper_neon_unzip16 ( @@v7@@ , @@v8@@ ) ; } else { gen_helper_neon_unzip8 ( @@v7@@ , @@v8@@ ) ; } tcg_temp_free_ptr ( @@v7@@ ) ; tcg_temp_free_ptr ( @@v8@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_neon_zip\", \"code\": \"__int64 __fastcall gen_neon_zip ( unsigned int @@a1@@ , unsigned int @@a2@@ , int @@a3@@ , int @@a4@@ ) { __int64 @@v7@@ ; __int64 @@v8@@ ; if ( ! @@a4@@ && @@a3@@ == Number ) return Number L ; @@v7@@ = vfp_reg_ptr ( Number , @@a1@@ ) ; @@v8@@ = vfp_reg_ptr ( Number , @@a2@@ ) ; if ( @@a4@@ ) { if ( @@a3@@ == Number ) { gen_helper_neon_qzip32 ( @@v7@@ , @@v8@@ ) ; } else { if ( @@a3@@ > Number ) goto LABEL_13 ; if ( @@a3@@ ) { if ( @@a3@@ != Number ) LABEL_13 : abort ( ) ; gen_helper_neon_qzip16 ( @@v7@@ , @@v8@@ ) ; } else { gen_helper_neon_qzip8 ( @@v7@@ , @@v8@@ ) ; } } } else if ( @@a3@@ ) { if ( @@a3@@ != Number ) abort ( ) ; gen_helper_neon_zip16 ( @@v7@@ , @@v8@@ ) ; } else { gen_helper_neon_zip8 ( @@v7@@ , @@v8@@ ) ; } tcg_temp_free_ptr ( @@v7@@ ) ; tcg_temp_free_ptr ( @@v8@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_neon_trn_u8\", \"code\": \"__int64 __fastcall gen_neon_trn_u8 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v4@@ ; __int64 @@v5@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_shli_i32 ( @@v4@@ , @@a1@@ , Number L ) ; tcg_gen_andi_i32 ( @@v4@@ , @@v4@@ , Number L ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a2@@ , Number L ) ; tcg_gen_or_i32 ( @@v4@@ , @@v4@@ , @@v5@@ ) ; tcg_gen_shri_i32 ( @@a2@@ , @@a2@@ , Number L ) ; tcg_gen_andi_i32 ( @@a2@@ , @@a2@@ , Number L ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a1@@ , Number L ) ; tcg_gen_or_i32 ( @@a2@@ , @@a2@@ , @@v5@@ ) ; tcg_gen_mov_i32 ( @@a1@@ , @@v4@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; return tcg_temp_free_i32 ( @@v4@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_neon_trn_u16\", \"code\": \"__int64 __fastcall gen_neon_trn_u16 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v4@@ ; __int64 @@v5@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_shli_i32 ( @@v4@@ , @@a1@@ , Number L ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a2@@ , Number ) ; tcg_gen_or_i32 ( @@v4@@ , @@v4@@ , @@v5@@ ) ; tcg_gen_shri_i32 ( @@a2@@ , @@a2@@ , Number L ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a1@@ , Number L ) ; tcg_gen_or_i32 ( @@a2@@ , @@a2@@ , @@v5@@ ) ; tcg_gen_mov_i32 ( @@a1@@ , @@v4@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; return tcg_temp_free_i32 ( @@v4@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_neon_narrow\", \"code\": \"__int64 __fastcall gen_neon_narrow ( int @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { if ( @@a1@@ == Number ) return tcg_gen_extrl_i64_i32 ( @@a2@@ , @@a3@@ ) ; if ( @@a1@@ > Number ) goto LABEL_9 ; if ( ! @@a1@@ ) return gen_helper_neon_narrow_u8 ( @@a2@@ , @@a3@@ ) ; if ( @@a1@@ != Number ) LABEL_9 : abort ( ) ; return gen_helper_neon_narrow_u16 ( @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_neon_shift_narrow\", \"code\": \"unsigned __int64 __fastcall gen_neon_shift_narrow ( int @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , int @@a5@@ ) { unsigned __int64 @@result@@ ; if ( @@a4@@ ) { if ( @@a5@@ ) { if ( @@a1@@ == Number ) { @@result@@ = gen_helper_neon_rshl_u16 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; } else { if ( @@a1@@ != Number ) abort ( ) ; @@result@@ = gen_helper_neon_rshl_u32 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; } } else if ( @@a1@@ == Number ) { @@result@@ = gen_helper_neon_rshl_s16 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; } else { if ( @@a1@@ != Number ) abort ( ) ; @@result@@ = gen_helper_neon_rshl_s32 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; } } else if ( @@a5@@ ) { if ( @@a1@@ == Number ) { @@result@@ = gen_helper_neon_shl_u16 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; } else { if ( @@a1@@ != Number ) abort ( ) ; @@result@@ = gen_helper_neon_shl_u32 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; } } else if ( @@a1@@ == Number ) { @@result@@ = gen_helper_neon_shl_s16 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; } else { if ( @@a1@@ != Number ) abort ( ) ; @@result@@ = gen_helper_neon_shl_s32 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_neon_widen\", \"code\": \"__int64 __fastcall gen_neon_widen ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ , int @@a4@@ ) { if ( ! @@a4@@ ) { if ( @@a3@@ == Number ) { tcg_gen_ext_i32_i64 ( @@a1@@ , @@a2@@ ) ; return tcg_temp_free_i32 ( @@a2@@ ) ; } if ( @@a3@@ <= Number ) { if ( ! @@a3@@ ) { gen_helper_neon_widen_s8 ( @@a1@@ , @@a2@@ ) ; return tcg_temp_free_i32 ( @@a2@@ ) ; } if ( @@a3@@ == Number ) { gen_helper_neon_widen_s16 ( @@a1@@ , @@a2@@ ) ; return tcg_temp_free_i32 ( @@a2@@ ) ; } } abort ( ) ; } if ( @@a3@@ == Number ) { tcg_gen_extu_i32_i64 ( @@a1@@ , @@a2@@ ) ; } else { if ( @@a3@@ > Number ) goto LABEL_10 ; if ( @@a3@@ ) { if ( @@a3@@ != Number ) LABEL_10 : abort ( ) ; gen_helper_neon_widen_u16 ( @@a1@@ , @@a2@@ ) ; } else { gen_helper_neon_widen_u8 ( @@a1@@ , @@a2@@ ) ; } } return tcg_temp_free_i32 ( @@a2@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_neon_addl\", \"code\": \"__int64 __fastcall gen_neon_addl ( int @@a1@@ ) { if ( @@a1@@ == Number ) return tcg_gen_add_i64 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; if ( @@a1@@ > Number ) goto LABEL_9 ; if ( ! @@a1@@ ) return gen_helper_neon_addl_u16 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; if ( @@a1@@ != Number ) LABEL_9 : abort ( ) ; return gen_helper_neon_addl_u32 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_neon_subl\", \"code\": \"__int64 __fastcall gen_neon_subl ( int @@a1@@ ) { if ( @@a1@@ == Number ) return tcg_gen_sub_i64 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; if ( @@a1@@ > Number ) goto LABEL_9 ; if ( ! @@a1@@ ) return gen_helper_neon_subl_u16 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; if ( @@a1@@ != Number ) LABEL_9 : abort ( ) ; return gen_helper_neon_subl_u32 ( cpu_V0 , cpu_V0 , cpu_V1 ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_neon_negl\", \"code\": \"__int64 __fastcall gen_neon_negl ( __int64 @@a1@@ , int @@a2@@ ) { if ( @@a2@@ == Number ) return tcg_gen_neg_i64 ( @@a1@@ , @@a1@@ ) ; if ( @@a2@@ > Number ) goto LABEL_9 ; if ( ! @@a2@@ ) return gen_helper_neon_negl_u16 ( @@a1@@ , @@a1@@ ) ; if ( @@a2@@ != Number ) LABEL_9 : abort ( ) ; return gen_helper_neon_negl_u32 ( @@a1@@ , @@a1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_neon_addl_saturate\", \"code\": \"unsigned __int64 __fastcall gen_neon_addl_saturate ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ ) { if ( @@a3@@ == Number ) return gen_helper_neon_addl_saturate_s32 ( @@a1@@ , cpu_env , @@a1@@ , @@a2@@ ) ; if ( @@a3@@ != Number ) abort ( ) ; return gen_helper_neon_addl_saturate_s64 ( @@a1@@ , cpu_env , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_neon_mull\", \"code\": \"unsigned __int64 __fastcall gen_neon_mull ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , int @@a5@@ ) { unsigned __int64 @@result@@ ; __int64 v8 ; __int64 v9 ; switch ( @@a5@@ | ( Number * @@a4@@ ) ) { case Number : @@result@@ = gen_helper_neon_mull_s8 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; break ; case Number : @@result@@ = gen_helper_neon_mull_u8 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; break ; case Number : @@result@@ = gen_helper_neon_mull_s16 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; break ; case Number : @@result@@ = gen_helper_neon_mull_u16 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; break ; case Number : v8 = gen_muls_i64_i32 ( @@a2@@ , @@a3@@ ) ; tcg_gen_mov_i64 ( @@a1@@ , v8 ) ; @@result@@ = tcg_temp_free_i64 ( v8 ) ; break ; case Number : v9 = gen_mulu_i64_i32 ( @@a2@@ , @@a3@@ ) ; tcg_gen_mov_i64 ( @@a1@@ , v9 ) ; @@result@@ = tcg_temp_free_i64 ( v9 ) ; break ; default : abort ( ) ; } if ( @@a4@@ <= Number ) { tcg_temp_free_i32 ( @@a2@@ ) ; @@result@@ = tcg_temp_free_i32 ( @@a3@@ ) ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_neon_narrow_op\", \"code\": \"unsigned __int64 __fastcall gen_neon_narrow_op ( int @@a1@@ , int @@a2@@ , int @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ ) { unsigned __int64 @@result@@ ; if ( @@a1@@ ) { if ( @@a2@@ ) @@result@@ = gen_neon_unarrow_sats ( @@a3@@ , @@a4@@ , @@a5@@ ) ; else @@result@@ = gen_neon_narrow ( @@a3@@ , @@a4@@ , @@a5@@ ) ; } else if ( @@a2@@ ) { @@result@@ = gen_neon_narrow_satu ( @@a3@@ , @@a4@@ , @@a5@@ ) ; } else { @@result@@ = gen_neon_narrow_sats ( @@a3@@ , @@a4@@ , @@a5@@ ) ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r72\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_2rm_is_v8_op\", \"code\": \"_BOOL8 __fastcall neon_2rm_is_v8_op ( unsigned int @@a1@@ ) { return @@a1@@ <= Number && ( ( Number L << @@a1@@ ) & Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"do_v81_helper\", \"code\": \"__int64 __fastcall do_v81_helper ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ , unsigned int @@a4@@ , unsigned int @@a5@@ , unsigned int @@a6@@ ) { __int64 @@v6@@ ; unsigned int @@v7@@ ; unsigned int @@v8@@ ; unsigned int @@v9@@ ; if ( ! isar_feature_aa32_rdm ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v6@@ = cpu_env ; @@v7@@ = vfp_reg_offset ( Number , @@a6@@ ) ; @@v8@@ = vfp_reg_offset ( Number , @@a5@@ ) ; @@v9@@ = vfp_reg_offset ( Number , @@a4@@ ) ; tcg_gen_gvec_3_ptr ( @@v9@@ , @@v8@@ , @@v7@@ , @@v6@@ , ( unsigned int ) ( Number * ( @@a3@@ + Number ) ) , ( unsigned int ) ( Number * ( @@a3@@ + Number ) ) , Number L , @@a2@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r120\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r128\"}, {\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"a6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r80\"}]}"
] |
{"name": "disas_neon_insn_3same_ext", "code": "__int64 __fastcall disas_neon_insn_3same_ext ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 result ; unsigned __int64 ( __fastcall * v3 ) ( __int64 , __int64 , __int64 , __int64 , __int64 ) ; unsigned __int64 ( __fastcall * v4 ) ( __int64 , __int64 , __int64 , __int64 , __int64 ) ; unsigned __int64 ( __fastcall * v5 ) ( __int64 , __int64 , __int64 , __int64 ) ; unsigned int @@v6@@ ; unsigned int v7 ; unsigned int v8 ; unsigned int v9 ; char @@v10@@ ; char @@v11@@ ; bool @@v12@@ ; bool @@v13@@ ; int @@v14@@ ; int @@v15@@ ; int @@v16@@ ; unsigned int @@v17@@ ; unsigned int @@v18@@ ; unsigned int @@v19@@ ; unsigned int @@v20@@ ; int @@v21@@ ; int @@v22@@ ; unsigned int @@v23@@ ; unsigned __int64 ( __fastcall * @@v24@@ ) ( __int64 , __int64 , __int64 , __int64 ) ; unsigned __int64 ( __fastcall * @@v25@@ ) ( __int64 , __int64 , __int64 , __int64 , __int64 ) ; __int64 @@v26@@ ; @@v24@@ = Number L ; @@v25@@ = Number L ; @@v17@@ = Number ; @@v10@@ = Number ; @@v12@@ = ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) != Number ; @@v11@@ = Number ; if ( ( @@a2@@ & Number ) == Number ) { @@v22@@ = extract32 ( @@a2@@ , Number , Number ) ; @@v17@@ = extract32 ( @@a2@@ , Number , Number ) ; if ( ! isar_feature_aa32_vcma ( * ( _QWORD * ) ( @@a1@@ + Number ) ) || ! @@v22@@ && ! isar_feature_aa32_fp16_arith ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v22@@ ) v3 = gen_helper_gvec_fcmlas ; else v3 = gen_helper_gvec_fcmlah ; @@v25@@ = v3 ; } else if ( ( @@a2@@ & Number ) == Number ) { @@v21@@ = extract32 ( @@a2@@ , Number , Number ) ; @@v17@@ = extract32 ( @@a2@@ , Number , Number ) ; if ( ! isar_feature_aa32_vcma ( * ( _QWORD * ) ( @@a1@@ + Number ) ) || ! @@v21@@ && ! isar_feature_aa32_fp16_arith ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v21@@ ) v4 = gen_helper_gvec_fcadds ; else v4 = gen_helper_gvec_fcaddh ; @@v25@@ = v4 ; } else if ( ( @@a2@@ & Number ) == Number ) { @@v13@@ = ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) != Number ; if ( ! isar_feature_aa32_dp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v13@@ ) v5 = gen_helper_gvec_udot_b ; else v5 = gen_helper_gvec_sdot_b ; @@v24@@ = v5 ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v20@@ = extract32 ( @@a2@@ , Number , Number ) ; if ( ! isar_feature_aa32_fhm ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v10@@ = Number ; @@v17@@ = @@v20@@ ; @@v25@@ = gen_helper_gvec_fmlal_a32 ; @@v11@@ = Number ; } if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v14@@ = ( ( unsigned __int16 ) @@a2@@ >> Number ) | ( @@a2@@ >> Number ) & Number ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v14@@ = ( unsigned __int16 ) @@a2@@ >> Number ; } if ( ( ( unsigned __int8 ) @@v14@@ & @@v12@@ ) != Number ) return Number L ; if ( @@v12@@ || @@v10@@ != Number ) { if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v15@@ = HIWORD ( @@a2@@ ) & Number | ( @@a2@@ >> Number ) & Number ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v15@@ = HIWORD ( @@a2@@ ) & Number ; } if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v16@@ = @@a2@@ & Number | ( @@a2@@ >> Number ) & Number ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v16@@ = @@a2@@ & Number ; } if ( ( @@v12@@ & ( unsigned __int8 ) ( @@v16@@ | @@v15@@ ) & ( ( unsigned __int8 ) @@v10@@ ^ Number ) ) != Number ) return Number L ; @@v18@@ = vfp_reg_offset ( Number , @@v15@@ ) ; @@v19@@ = vfp_reg_offset ( Number , @@v16@@ ) ; } else { @@v18@@ = vfp_reg_offset ( Number , ( @@a2@@ >> Number ) & Number | ( @@a2@@ >> Number ) & Number ) ; @@v19@@ = vfp_reg_offset ( Number , ( Number * ( _BYTE ) @@a2@@ ) & Number | ( @@a2@@ >> Number ) & Number ) ; } if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { @@v6@@ = * ( _DWORD * ) ( @@a1@@ + Number ) ; v7 = syn_simd_access_trap ( Number , Number , Number ) ; gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , v7 , @@v6@@ ) ; result = Number L ; } else if ( * ( _BYTE * ) ( @@a1@@ + Number ) != Number ) { result = Number L ; } else { @@v23@@ = Number * ( @@v12@@ + Number ) ; if ( @@v25@@ ) { if ( @@v11@@ ) @@v26@@ = cpu_env ; else @@v26@@ = get_fpstatus_ptr ( Number ) ; v8 = vfp_reg_offset ( Number , @@v14@@ ) ; tcg_gen_gvec_3_ptr ( v8 , @@v18@@ , @@v19@@ , @@v26@@ , @@v23@@ , @@v23@@ , @@v17@@ , @@v25@@ ) ; if ( @@v11@@ != Number ) tcg_temp_free_ptr ( @@v26@@ ) ; } else { v9 = vfp_reg_offset ( Number , @@v14@@ ) ; tcg_gen_gvec_3_ool ( v9 , @@v18@@ , @@v19@@ , @@v23@@ , @@v23@@ , @@v17@@ , @@v24@@ ) ; } result = Number L ; } return result ; }", "source": [{"n": "v6", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r32"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "v24", "t": {"T": 9, "n": "unsigned __int64 (__fastcall *)(__int64 a1, __int64 a2, __int64 a3, __int64 a4)"}, "location": "s104"}, {"n": "v23", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s108"}, {"n": "v22", "t": {"T": 1, "n": "int", "s": 4}, "location": "s112"}, {"n": "v21", "t": {"T": 1, "n": "int", "s": 4}, "location": "s116"}, {"n": "v20", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s120"}, {"n": "v19", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s124"}, {"n": "v18", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s128"}, {"n": "v17", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s132"}, {"n": "v16", "t": {"T": 1, "n": "int", "s": 4}, "location": "s136"}, {"n": "v15", "t": {"T": 1, "n": "int", "s": 4}, "location": "s140"}, {"n": "v14", "t": {"T": 1, "n": "int", "s": 4}, "location": "s144"}, {"n": "v13", "t": {"T": 1, "n": "bool", "s": 1}, "location": "s145"}, {"n": "v12", "t": {"T": 1, "n": "bool", "s": 1}, "location": "s146"}, {"n": "v11", "t": {"T": 1, "n": "char", "s": 1}, "location": "s147"}, {"n": "v10", "t": {"T": 1, "n": "char", "s": 1}, "location": "s148"}, {"n": "v26", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s88"}, {"n": "v25", "t": {"T": 9, "n": "unsigned __int64 (__fastcall *)(__int64 a1, __int64 a2, __int64 a3, __int64 a4, __int64 a5)"}, "location": "s96"}]}
|
[{"n": "v6", "t": {"T": 1, "n": "int", "s": 4}, "location": "r32"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "insn", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r64"}, {"n": "fn_gvec", "t": {"T": 9, "n": "gen_helper_gvec_3 *"}, "location": "s104"}, {"n": "opr_sz", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s108"}, {"n": "size", "t": {"T": 1, "n": "int", "s": 4}, "location": "s112"}, {"n": "size_0", "t": {"T": 1, "n": "int", "s": 4}, "location": "s116"}, {"n": "is_s", "t": {"T": 1, "n": "int", "s": 4}, "location": "s120"}, {"n": "off_rm", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s124"}, {"n": "off_rn", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s128"}, {"n": "data", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s132"}, {"n": "rm", "t": {"T": 1, "n": "int", "s": 4}, "location": "s136"}, {"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "s140"}, {"n": "rd", "t": {"T": 1, "n": "int", "s": 4}, "location": "s144"}, {"n": "u", "t": {"T": 1, "n": "bool", "s": 1}, "location": "s145"}, {"n": "q", "t": {"T": 1, "n": "bool", "s": 1}, "location": "s146"}, {"n": "ptr_is_env", "t": {"T": 1, "n": "bool", "s": 1}, "location": "s147"}, {"n": "is_long", "t": {"T": 1, "n": "bool", "s": 1}, "location": "s148"}, {"n": "ptr", "t": {"T": 3, "t": "TCGv_ptr_d"}, "location": "s88"}, {"n": "fn_gvec_ptr", "t": {"T": 9, "n": "void (__cdecl *)(TCGv_ptr arg1, TCGv_ptr arg2, TCGv_ptr arg3, TCGv_ptr arg4, TCGv_i32 arg5)"}, "location": "s96"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,018 |
[
"{\"name\": \"extract32\", \"code\": \"__int64 __fastcall extract32 ( unsigned int @@a1@@ , int @@a2@@ , int @@a3@@ ) { if ( @@a2@@ < Number || @@a3@@ <= Number || @@a3@@ > Number - @@a2@@ ) _assert_fail ( String , String , Number , String ) ; return ( @@a1@@ >> @@a2@@ ) & ( Number >> ( Number - @@a3@@ ) ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"isar_feature_aa32_vcma\", \"code\": \"bool __fastcall isar_feature_aa32_vcma ( __int64 @@a1@@ ) { return ( unsigned int ) extract32 ( * ( _DWORD * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_dp\", \"code\": \"bool __fastcall isar_feature_aa32_dp ( __int64 @@a1@@ ) { return ( unsigned int ) extract32 ( * ( _DWORD * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_fhm\", \"code\": \"bool __fastcall isar_feature_aa32_fhm ( __int64 @@a1@@ ) { return ( unsigned int ) extract32 ( * ( _DWORD * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_fp16_arith\", \"code\": \"bool __fastcall isar_feature_aa32_fp16_arith ( __int64 @@a1@@ ) { return extract64 ( * ( _QWORD * ) ( @@a1@@ + Number ) , Number , Number ) == Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"syn_simd_access_trap\", \"code\": \"__int64 __fastcall syn_simd_access_trap ( int @@a1@@ , int @@a2@@ , char @@a3@@ ) { int v3 ; if ( @@a3@@ ) v3 = Number ; else v3 = Number ; return ( @@a1@@ << Number ) | v3 | ( @@a2@@ << Number ) | Number ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_temp_free_ptr\", \"code\": \"__int64 __fastcall tcg_temp_free_ptr ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_ptr_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_helper_gvec_sdot_b\", \"code\": \"unsigned __int64 __fastcall gen_helper_gvec_sdot_b ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v7@@ [ Number ] ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; @@v7@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v7@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v7@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v7@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; tcg_gen_callN ( & helper_gvec_sdot_b , Number L , Number L , @@v7@@ ) ; return __readfsqword ( Number ) ^ @@v8@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_gvec_udot_b\", \"code\": \"unsigned __int64 __fastcall gen_helper_gvec_udot_b ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v7@@ [ Number ] ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; @@v7@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v7@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v7@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v7@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; tcg_gen_callN ( & helper_gvec_udot_b , Number L , Number L , @@v7@@ ) ; return __readfsqword ( Number ) ^ @@v8@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_gvec_fcaddh\", \"code\": \"unsigned __int64 __fastcall gen_helper_gvec_fcaddh ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ ) { __int64 @@v9@@ [ Number ] ; unsigned __int64 @@v10@@ ; @@v10@@ = __readfsqword ( Number ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v9@@ [ Number ] = tcgv_i32_temp ( @@a5@@ ) ; tcg_gen_callN ( & helper_gvec_fcaddh , Number L , Number L , @@v9@@ ) ; return __readfsqword ( Number ) ^ @@v10@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_gvec_fcadds\", \"code\": \"unsigned __int64 __fastcall gen_helper_gvec_fcadds ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ ) { __int64 @@v9@@ [ Number ] ; unsigned __int64 @@v10@@ ; @@v10@@ = __readfsqword ( Number ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v9@@ [ Number ] = tcgv_i32_temp ( @@a5@@ ) ; tcg_gen_callN ( & helper_gvec_fcadds , Number L , Number L , @@v9@@ ) ; return __readfsqword ( Number ) ^ @@v10@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_gvec_fcmlah\", \"code\": \"unsigned __int64 __fastcall gen_helper_gvec_fcmlah ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ ) { __int64 @@v9@@ [ Number ] ; unsigned __int64 @@v10@@ ; @@v10@@ = __readfsqword ( Number ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v9@@ [ Number ] = tcgv_i32_temp ( @@a5@@ ) ; tcg_gen_callN ( & helper_gvec_fcmlah , Number L , Number L , @@v9@@ ) ; return __readfsqword ( Number ) ^ @@v10@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_gvec_fcmlas\", \"code\": \"unsigned __int64 __fastcall gen_helper_gvec_fcmlas ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ ) { __int64 @@v9@@ [ Number ] ; unsigned __int64 @@v10@@ ; @@v10@@ = __readfsqword ( Number ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v9@@ [ Number ] = tcgv_i32_temp ( @@a5@@ ) ; tcg_gen_callN ( & helper_gvec_fcmlas , Number L , Number L , @@v9@@ ) ; return __readfsqword ( Number ) ^ @@v10@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_gvec_fmlal_a32\", \"code\": \"unsigned __int64 __fastcall gen_helper_gvec_fmlal_a32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ ) { __int64 @@v9@@ [ Number ] ; unsigned __int64 @@v10@@ ; @@v10@@ = __readfsqword ( Number ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v9@@ [ Number ] = tcgv_i32_temp ( @@a5@@ ) ; tcg_gen_callN ( & helper_gvec_fmlal_a32 , Number L , Number L , @@v9@@ ) ; return __readfsqword ( Number ) ^ @@v10@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_exception\", \"code\": \"__int64 __fastcall gen_exception ( unsigned int @@a1@@ , unsigned int @@a2@@ , unsigned int @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_const_i32 ( @@a1@@ ) ; @@v6@@ = tcg_const_i32 ( @@a2@@ ) ; @@v7@@ = tcg_const_i32 ( @@a3@@ ) ; gen_helper_exception_with_syndrome ( cpu_env , @@v5@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_exception_insn\", \"code\": \"__int64 __fastcall gen_exception_insn ( __int64 @@a1@@ , int @@a2@@ , unsigned int @@a3@@ , unsigned int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@result@@ ; gen_set_condexec ( @@a1@@ ) ; gen_set_pc_im ( @@a1@@ , @@a2@@ ) ; gen_exception ( @@a3@@ , @@a4@@ , @@a5@@ ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"get_fpstatus_ptr\", \"code\": \"__int64 __fastcall get_fpstatus_ptr ( int @@a1@@ ) { int @@v2@@ ; __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_ptr ( ) ; if ( @@a1@@ ) @@v2@@ = Number ; else @@v2@@ = Number ; tcg_gen_addi_ptr ( @@v3@@ , cpu_env , @@v2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"vfp_reg_offset\", \"code\": \"__int64 __fastcall vfp_reg_offset ( char @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v3@@ ; if ( @@a1@@ ) return Number * ( Number * ( ( @@a2@@ >> Number ) + Number L ) + ( @@a2@@ & Number ) ) ; @@v3@@ = Number * ( Number * ( ( @@a2@@ >> Number ) + Number L ) + ( ( @@a2@@ >> Number ) & Number ) ) ; if ( ( @@a2@@ & Number ) != Number ) @@v3@@ += Number L ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "disas_neon_insn_2reg_scalar_ext", "code": "__int64 __fastcall disas_neon_insn_2reg_scalar_ext ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 result ; unsigned __int64 ( __fastcall * v3 ) ( __int64 , __int64 , __int64 , __int64 , __int64 ) ; unsigned __int64 ( __fastcall * v4 ) ( __int64 , __int64 , __int64 , __int64 ) ; unsigned int @@v5@@ ; unsigned int v6 ; unsigned int v7 ; unsigned int v8 ; char @@v9@@ ; char @@v10@@ ; bool @@v11@@ ; int @@v12@@ ; int @@v13@@ ; unsigned int @@v14@@ ; unsigned int @@v15@@ ; unsigned int @@v16@@ ; unsigned int @@v17@@ ; int @@v18@@ ; int @@v19@@ ; int @@v20@@ ; unsigned int @@v21@@ ; int @@v22@@ ; int @@v23@@ ; int @@v24@@ ; int @@v25@@ ; int @@v26@@ ; unsigned int @@v27@@ ; unsigned __int64 ( __fastcall * @@v28@@ ) ( __int64 , __int64 , __int64 , __int64 ) ; unsigned __int64 ( __fastcall * @@v29@@ ) ( __int64 , __int64 , __int64 , __int64 , __int64 ) ; __int64 @@v30@@ ; @@v28@@ = Number L ; @@v29@@ = Number L ; @@v9@@ = Number ; @@v11@@ = ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) != Number ; @@v10@@ = Number ; if ( ( @@a2@@ & Number ) == Number ) { @@v25@@ = extract32 ( @@a2@@ , Number , Number ) ; @@v26@@ = extract32 ( @@a2@@ , Number , Number ) ; if ( ! isar_feature_aa32_vcma ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v26@@ ) { if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v14@@ = @@a2@@ & Number | ( @@a2@@ >> Number ) & Number ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v14@@ = @@a2@@ & Number ; } @@v18@@ = Number ; } else { if ( ! isar_feature_aa32_fp16_arith ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v14@@ = extract32 ( @@a2@@ , Number , Number ) ; @@v18@@ = extract32 ( @@a2@@ , Number , Number ) ; } @@v15@@ = @@v25@@ | ( Number * @@v18@@ ) ; if ( @@v26@@ ) v3 = gen_helper_gvec_fcmlas_idx ; else v3 = gen_helper_gvec_fcmlah_idx ; @@v29@@ = v3 ; } else if ( ( @@a2@@ & Number ) == Number ) { @@v24@@ = extract32 ( @@a2@@ , Number , Number ) ; if ( ! isar_feature_aa32_dp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v24@@ ) v4 = gen_helper_gvec_udot_idx_b ; else v4 = gen_helper_gvec_sdot_idx_b ; @@v28@@ = v4 ; @@v15@@ = extract32 ( @@a2@@ , Number , Number ) ; @@v14@@ = extract32 ( @@a2@@ , Number , Number ) ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v20@@ = extract32 ( @@a2@@ , Number , Number ) ; @@v21@@ = extract32 ( @@a2@@ , Number , Number ) ; @@v22@@ = extract32 ( @@a2@@ , Number , Number ) ; @@v23@@ = extract32 ( @@a2@@ , Number , Number ) ; if ( ! isar_feature_aa32_fhm ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v11@@ ) { @@v14@@ = @@v21@@ ; @@v19@@ = Number * @@v23@@ + @@v22@@ ; } else { @@v14@@ = Number * @@v21@@ + @@v23@@ ; @@v19@@ = @@v22@@ ; } @@v9@@ = Number ; @@v15@@ = @@v20@@ | ( Number * @@v19@@ ) ; @@v29@@ = gen_helper_gvec_fmlal_idx_a32 ; @@v10@@ = Number ; } if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v12@@ = ( ( unsigned __int16 ) @@a2@@ >> Number ) | ( @@a2@@ >> Number ) & Number ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v12@@ = ( unsigned __int16 ) @@a2@@ >> Number ; } if ( ( ( unsigned __int8 ) @@v12@@ & @@v11@@ ) != Number ) return Number L ; if ( @@v11@@ || @@v9@@ != Number ) { if ( arm_dc_feature ( @@a1@@ , Number ) ) { @@v13@@ = HIWORD ( @@a2@@ ) & Number | ( @@a2@@ >> Number ) & Number ; } else { if ( ( @@a2@@ & Number ) != Number ) return Number L ; @@v13@@ = HIWORD ( @@a2@@ ) & Number ; } if ( ( ( unsigned __int8 ) @@v13@@ & @@v11@@ & ( ( unsigned __int8 ) @@v9@@ ^ Number ) ) != Number ) return Number L ; @@v16@@ = vfp_reg_offset ( Number , @@v13@@ ) ; @@v17@@ = vfp_reg_offset ( Number , @@v14@@ ) ; } else { @@v16@@ = vfp_reg_offset ( Number , ( @@a2@@ >> Number ) & Number | ( @@a2@@ >> Number ) & Number ) ; @@v17@@ = vfp_reg_offset ( Number , @@v14@@ ) ; } if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { @@v5@@ = * ( _DWORD * ) ( @@a1@@ + Number ) ; v6 = syn_simd_access_trap ( Number , Number , Number ) ; gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , v6 , @@v5@@ ) ; result = Number L ; } else if ( * ( _BYTE * ) ( @@a1@@ + Number ) != Number ) { result = Number L ; } else { @@v27@@ = Number * ( @@v11@@ + Number ) ; if ( @@v29@@ ) { if ( @@v10@@ ) @@v30@@ = cpu_env ; else @@v30@@ = get_fpstatus_ptr ( Number ) ; v7 = vfp_reg_offset ( Number , @@v12@@ ) ; tcg_gen_gvec_3_ptr ( v7 , @@v16@@ , @@v17@@ , @@v30@@ , @@v27@@ , @@v27@@ , @@v15@@ , @@v29@@ ) ; if ( @@v10@@ != Number ) tcg_temp_free_ptr ( @@v30@@ ) ; } else { v8 = vfp_reg_offset ( Number , @@v12@@ ) ; tcg_gen_gvec_3_ool ( v8 , @@v16@@ , @@v17@@ , @@v27@@ , @@v27@@ , @@v15@@ , @@v28@@ ) ; } result = Number L ; } return result ; }", "source": [{"n": "v5", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r32"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "v25", "t": {"T": 1, "n": "int", "s": 4}, "location": "s100"}, {"n": "v24", "t": {"T": 1, "n": "int", "s": 4}, "location": "s104"}, {"n": "v23", "t": {"T": 1, "n": "int", "s": 4}, "location": "s108"}, {"n": "v22", "t": {"T": 1, "n": "int", "s": 4}, "location": "s112"}, {"n": "v21", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s116"}, {"n": "v20", "t": {"T": 1, "n": "int", "s": 4}, "location": "s120"}, {"n": "v19", "t": {"T": 1, "n": "int", "s": 4}, "location": "s124"}, {"n": "v18", "t": {"T": 1, "n": "int", "s": 4}, "location": "s128"}, {"n": "v17", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s132"}, {"n": "v16", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s136"}, {"n": "v15", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s140"}, {"n": "v14", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s144"}, {"n": "v13", "t": {"T": 1, "n": "int", "s": 4}, "location": "s148"}, {"n": "v12", "t": {"T": 1, "n": "int", "s": 4}, "location": "s152"}, {"n": "v11", "t": {"T": 1, "n": "bool", "s": 1}, "location": "s153"}, {"n": "v10", "t": {"T": 1, "n": "char", "s": 1}, "location": "s154"}, {"n": "v9", "t": {"T": 1, "n": "char", "s": 1}, "location": "s155"}, {"n": "v30", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s72"}, {"n": "v29", "t": {"T": 9, "n": "unsigned __int64 (__fastcall *)(__int64 a1, __int64 a2, __int64 a3, __int64 a4, __int64 a5)"}, "location": "s80"}, {"n": "v28", "t": {"T": 9, "n": "unsigned __int64 (__fastcall *)(__int64 a1, __int64 a2, __int64 a3, __int64 a4)"}, "location": "s88"}, {"n": "v27", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s92"}, {"n": "v26", "t": {"T": 1, "n": "int", "s": 4}, "location": "s96"}]}
|
[{"n": "v5", "t": {"T": 1, "n": "int", "s": 4}, "location": "r32"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "insn", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r64"}, {"n": "rot", "t": {"T": 1, "n": "int", "s": 4}, "location": "s100"}, {"n": "u", "t": {"T": 1, "n": "int", "s": 4}, "location": "s104"}, {"n": "m", "t": {"T": 1, "n": "int", "s": 4}, "location": "s108"}, {"n": "vm3", "t": {"T": 1, "n": "int", "s": 4}, "location": "s112"}, {"n": "vm20", "t": {"T": 1, "n": "int", "s": 4}, "location": "s116"}, {"n": "is_s", "t": {"T": 1, "n": "int", "s": 4}, "location": "s120"}, {"n": "index_0", "t": {"T": 1, "n": "int", "s": 4}, "location": "s124"}, {"n": "index", "t": {"T": 1, "n": "int", "s": 4}, "location": "s128"}, {"n": "off_rm", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s132"}, {"n": "off_rn", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s136"}, {"n": "data", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s140"}, {"n": "rm", "t": {"T": 1, "n": "int", "s": 4}, "location": "s144"}, {"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "s148"}, {"n": "rd", "t": {"T": 1, "n": "int", "s": 4}, "location": "s152"}, {"n": "q", "t": {"T": 1, "n": "bool", "s": 1}, "location": "s153"}, {"n": "ptr_is_env", "t": {"T": 1, "n": "bool", "s": 1}, "location": "s154"}, {"n": "is_long", "t": {"T": 1, "n": "bool", "s": 1}, "location": "s155"}, {"n": "ptr", "t": {"T": 3, "t": "TCGv_ptr_d"}, "location": "s72"}, {"n": "fn_gvec_ptr", "t": {"T": 9, "n": "void (__cdecl *)(TCGv_ptr arg1, TCGv_ptr arg2, TCGv_ptr arg3, TCGv_ptr arg4, TCGv_i32 arg5)"}, "location": "s80"}, {"n": "fn_gvec", "t": {"T": 9, "n": "gen_helper_gvec_3 *"}, "location": "s88"}, {"n": "opr_sz", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s92"}, {"n": "size", "t": {"T": 1, "n": "int", "s": 4}, "location": "s96"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,019 |
[
"{\"name\": \"extract32\", \"code\": \"__int64 __fastcall extract32 ( unsigned int @@a1@@ , int @@a2@@ , int @@a3@@ ) { if ( @@a2@@ < Number || @@a3@@ <= Number || @@a3@@ > Number - @@a2@@ ) _assert_fail ( String , String , Number , String ) ; return ( @@a1@@ >> @@a2@@ ) & ( Number >> ( Number - @@a3@@ ) ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"isar_feature_aa32_vcma\", \"code\": \"bool __fastcall isar_feature_aa32_vcma ( __int64 @@a1@@ ) { return ( unsigned int ) extract32 ( * ( _DWORD * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_dp\", \"code\": \"bool __fastcall isar_feature_aa32_dp ( __int64 @@a1@@ ) { return ( unsigned int ) extract32 ( * ( _DWORD * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_fhm\", \"code\": \"bool __fastcall isar_feature_aa32_fhm ( __int64 @@a1@@ ) { return ( unsigned int ) extract32 ( * ( _DWORD * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_fp16_arith\", \"code\": \"bool __fastcall isar_feature_aa32_fp16_arith ( __int64 @@a1@@ ) { return extract64 ( * ( _QWORD * ) ( @@a1@@ + Number ) , Number , Number ) == Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"syn_simd_access_trap\", \"code\": \"__int64 __fastcall syn_simd_access_trap ( int @@a1@@ , int @@a2@@ , char @@a3@@ ) { int v3 ; if ( @@a3@@ ) v3 = Number ; else v3 = Number ; return ( @@a1@@ << Number ) | v3 | ( @@a2@@ << Number ) | Number ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_temp_free_ptr\", \"code\": \"__int64 __fastcall tcg_temp_free_ptr ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_ptr_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_helper_gvec_sdot_idx_b\", \"code\": \"unsigned __int64 __fastcall gen_helper_gvec_sdot_idx_b ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v7@@ [ Number ] ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; @@v7@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v7@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v7@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v7@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; tcg_gen_callN ( & helper_gvec_sdot_idx_b , Number L , Number L , @@v7@@ ) ; return __readfsqword ( Number ) ^ @@v8@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_gvec_udot_idx_b\", \"code\": \"unsigned __int64 __fastcall gen_helper_gvec_udot_idx_b ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v7@@ [ Number ] ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; @@v7@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v7@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v7@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v7@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; tcg_gen_callN ( & helper_gvec_udot_idx_b , Number L , Number L , @@v7@@ ) ; return __readfsqword ( Number ) ^ @@v8@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_gvec_fcmlah\", \"code\": \"unsigned __int64 __fastcall gen_helper_gvec_fcmlah ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ ) { __int64 @@v9@@ [ Number ] ; unsigned __int64 @@v10@@ ; @@v10@@ = __readfsqword ( Number ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v9@@ [ Number ] = tcgv_i32_temp ( @@a5@@ ) ; tcg_gen_callN ( & helper_gvec_fcmlah , Number L , Number L , @@v9@@ ) ; return __readfsqword ( Number ) ^ @@v10@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_gvec_fcmlah_idx\", \"code\": \"unsigned __int64 __fastcall gen_helper_gvec_fcmlah_idx ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ ) { __int64 @@v9@@ [ Number ] ; unsigned __int64 @@v10@@ ; @@v10@@ = __readfsqword ( Number ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v9@@ [ Number ] = tcgv_i32_temp ( @@a5@@ ) ; tcg_gen_callN ( & helper_gvec_fcmlah_idx , Number L , Number L , @@v9@@ ) ; return __readfsqword ( Number ) ^ @@v10@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_gvec_fcmlas\", \"code\": \"unsigned __int64 __fastcall gen_helper_gvec_fcmlas ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ ) { __int64 @@v9@@ [ Number ] ; unsigned __int64 @@v10@@ ; @@v10@@ = __readfsqword ( Number ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v9@@ [ Number ] = tcgv_i32_temp ( @@a5@@ ) ; tcg_gen_callN ( & helper_gvec_fcmlas , Number L , Number L , @@v9@@ ) ; return __readfsqword ( Number ) ^ @@v10@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_gvec_fcmlas_idx\", \"code\": \"unsigned __int64 __fastcall gen_helper_gvec_fcmlas_idx ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ ) { __int64 @@v9@@ [ Number ] ; unsigned __int64 @@v10@@ ; @@v10@@ = __readfsqword ( Number ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v9@@ [ Number ] = tcgv_i32_temp ( @@a5@@ ) ; tcg_gen_callN ( & helper_gvec_fcmlas_idx , Number L , Number L , @@v9@@ ) ; return __readfsqword ( Number ) ^ @@v10@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_gvec_fmlal_idx_a32\", \"code\": \"unsigned __int64 __fastcall gen_helper_gvec_fmlal_idx_a32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ ) { __int64 @@v9@@ [ Number ] ; unsigned __int64 @@v10@@ ; @@v10@@ = __readfsqword ( Number ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v9@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v9@@ [ Number ] = tcgv_i32_temp ( @@a5@@ ) ; tcg_gen_callN ( & helper_gvec_fmlal_idx_a32 , Number L , Number L , @@v9@@ ) ; return __readfsqword ( Number ) ^ @@v10@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_exception\", \"code\": \"__int64 __fastcall gen_exception ( unsigned int @@a1@@ , unsigned int @@a2@@ , unsigned int @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_const_i32 ( @@a1@@ ) ; @@v6@@ = tcg_const_i32 ( @@a2@@ ) ; @@v7@@ = tcg_const_i32 ( @@a3@@ ) ; gen_helper_exception_with_syndrome ( cpu_env , @@v5@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_exception_insn\", \"code\": \"__int64 __fastcall gen_exception_insn ( __int64 @@a1@@ , int @@a2@@ , unsigned int @@a3@@ , unsigned int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@result@@ ; gen_set_condexec ( @@a1@@ ) ; gen_set_pc_im ( @@a1@@ , @@a2@@ ) ; gen_exception ( @@a3@@ , @@a4@@ , @@a5@@ ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"get_fpstatus_ptr\", \"code\": \"__int64 __fastcall get_fpstatus_ptr ( int @@a1@@ ) { int @@v2@@ ; __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_ptr ( ) ; if ( @@a1@@ ) @@v2@@ = Number ; else @@v2@@ = Number ; tcg_gen_addi_ptr ( @@v3@@ , cpu_env , @@v2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"vfp_reg_offset\", \"code\": \"__int64 __fastcall vfp_reg_offset ( char @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v3@@ ; if ( @@a1@@ ) return Number * ( Number * ( ( @@a2@@ >> Number ) + Number L ) + ( @@a2@@ & Number ) ) ; @@v3@@ = Number * ( Number * ( ( @@a2@@ >> Number ) + Number L ) + ( ( @@a2@@ >> Number ) & Number ) ) ; if ( ( @@a2@@ & Number ) != Number ) @@v3@@ += Number L ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "disas_coproc_insn", "code": "__int64 __fastcall disas_coproc_insn ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 result ; unsigned int v4 ; bool v5 ; const char * v6 ; const char * v7 ; const char * v8 ; const char * v9 ; char @@v10@@ ; unsigned int @@v11@@ ; unsigned int @@v12@@ ; unsigned int @@v13@@ ; int @@v14@@ ; unsigned int @@v15@@ ; unsigned int @@v16@@ ; int @@v17@@ ; unsigned int @@v18@@ ; int @@v19@@ ; __int64 @@v20@@ ; __int64 @@v21@@ ; __int64 @@v22@@ ; __int64 @@v23@@ ; __int64 @@v24@@ ; __int64 @@v25@@ ; __int64 @@v26@@ ; __int64 @@v27@@ ; __int64 @@v28@@ ; __int64 @@v29@@ ; __int64 @@v30@@ ; __int64 @@v31@@ ; __int64 @@v32@@ ; __int64 @@v33@@ ; __int64 @@v34@@ ; __int64 v35 ; __int64 v36 ; __int64 @@v37@@ ; @@v16@@ = ( @@a2@@ >> Number ) & Number ; if ( arm_dc_feature ( @@a1@@ , Number ) && ( ( @@a2@@ >> Number ) & Number ) <= Number ) { if ( ( unsigned int ) extract32 ( * ( _DWORD * ) ( @@a1@@ + Number ) , @@v16@@ , Number ) ) { if ( arm_dc_feature ( @@a1@@ , Number ) ) { result = disas_iwmmxt_insn ( @@a1@@ , @@a2@@ ) ; } else if ( arm_dc_feature ( @@a1@@ , Number ) ) { result = disas_dsp_insn ( @@a1@@ , @@a2@@ ) ; } else { result = Number L ; } } else { result = Number L ; } } else { if ( ( @@a2@@ & Number ) != Number && ( @@a2@@ & Number ) == Number ) return Number L ; @@v17@@ = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != Number ) { @@v11@@ = HIWORD ( @@a2@@ ) & Number ; @@v12@@ = ( @@a2@@ >> Number ) & Number ; @@v13@@ = ( unsigned __int8 ) @@a2@@ >> Number ; @@v14@@ = Number ; } else { @@v11@@ = Number ; @@v12@@ = ( unsigned __int8 ) @@a2@@ >> Number ; @@v13@@ = Number ; @@v14@@ = HIWORD ( @@a2@@ ) & Number ; } @@v18@@ = ( @@a2@@ >> Number ) & Number ; @@v19@@ = ( unsigned __int16 ) @@a2@@ >> Number ; @@v22@@ = get_arm_cp_reginfo ( * ( _QWORD * ) ( @@a1@@ + Number ) , @@v13@@ | ( @@v17@@ << Number ) | ( @@v11@@ << Number ) | ( ( ( @@a2@@ & Number ) == Number ) << Number ) | ( @@v16@@ << Number ) | ( * ( unsigned __int8 * ) ( @@a1@@ + Number ) << Number ) | ( Number * @@v12@@ ) ) ; if ( @@v22@@ ) { if ( ! cp_access_ok ( * ( _DWORD * ) ( @@a1@@ + Number ) , @@v22@@ , ( @@a2@@ & Number ) != Number ) ) return Number L ; if ( * ( _QWORD * ) ( @@v22@@ + Number ) || arm_dc_feature ( @@a1@@ , Number ) && ( ( @@a2@@ >> Number ) & Number ) <= Number ) { if ( @@v16@@ == Number ) { if ( ( @@a2@@ & Number ) != Number ) @@v15@@ = syn_cp14_rt_trap ( Number , Number , @@v12@@ , @@v13@@ , @@v11@@ , @@v17@@ , @@v19@@ , @@v18@@ , Number ) ; else @@v15@@ = syn_cp14_rrt_trap ( Number , Number , @@v12@@ , @@v17@@ , @@v19@@ , @@v14@@ , @@v18@@ , Number ) ; } else if ( @@v16@@ == Number ) { if ( ( @@a2@@ & Number ) != Number ) @@v15@@ = syn_cp15_rt_trap ( Number , Number , @@v12@@ , @@v13@@ , @@v11@@ , @@v17@@ , @@v19@@ , @@v18@@ , Number ) ; else @@v15@@ = syn_cp15_rrt_trap ( Number , Number , @@v12@@ , @@v17@@ , @@v19@@ , @@v14@@ , @@v18@@ , Number ) ; } else { if ( arm_dc_feature ( @@a1@@ , Number ) ) _assert_fail ( String , String , Number , String ) ; @@v15@@ = syn_uncategorized ( ) ; } gen_set_condexec ( @@a1@@ ) ; gen_set_pc_im ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; @@v23@@ = tcg_const_i64 ( @@v22@@ ) ; @@v24@@ = tcg_const_i32 ( @@v15@@ ) ; @@v25@@ = tcg_const_i32 ( @@v18@@ ) ; gen_helper_access_check_cp_reg ( cpu_env , @@v23@@ , @@v24@@ , @@v25@@ ) ; tcg_temp_free_ptr ( @@v23@@ ) ; tcg_temp_free_i32 ( @@v24@@ ) ; tcg_temp_free_i32 ( @@v25@@ ) ; } else if ( ( * ( _DWORD * ) ( @@v22@@ + Number ) & Number ) != Number ) { gen_set_condexec ( @@a1@@ ) ; gen_set_pc_im ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; } v4 = * ( _DWORD * ) ( @@v22@@ + Number ) & Number ; if ( v4 == Number ) return Number L ; if ( v4 == Number ) { if ( @@v18@@ ) { result = Number L ; } else { gen_set_pc_im ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; result = Number L ; } } else { if ( ( tb_cflags ( * ( _QWORD * ) @@a1@@ ) & Number ) != Number && ( * ( _DWORD * ) ( @@v22@@ + Number ) & Number ) != Number ) gen_io_start ( ) ; if ( @@v18@@ ) { if ( ( @@a2@@ & Number ) != Number ) { if ( ( * ( _DWORD * ) ( @@v22@@ + Number ) & Number ) != Number ) { @@v21@@ = tcg_const_i32 ( ( unsigned int ) * ( _QWORD * ) ( @@v22@@ + Number ) ) ; } else if ( * ( _QWORD * ) ( @@v22@@ + Number ) ) { @@v21@@ = tcg_temp_new_i32 ( ) ; @@v33@@ = tcg_const_i64 ( @@v22@@ ) ; gen_helper_get_cp_reg ( @@v21@@ , cpu_env , @@v33@@ ) ; tcg_temp_free_ptr ( @@v33@@ ) ; } else { @@v21@@ = load_cpu_offset ( * ( _QWORD * ) ( @@v22@@ + Number ) ) ; } if ( @@v19@@ == Number ) { gen_set_cpsr ( @@v21@@ , Number ) ; tcg_temp_free_i32 ( @@v21@@ ) ; } else { store_reg ( @@a1@@ , @@v19@@ , @@v21@@ ) ; } } else { if ( ( * ( _DWORD * ) ( @@v22@@ + Number ) & Number ) != Number ) { @@v20@@ = tcg_const_i64 ( * ( _QWORD * ) ( @@v22@@ + Number ) ) ; } else if ( * ( _QWORD * ) ( @@v22@@ + Number ) ) { @@v20@@ = tcg_temp_new_i64 ( ) ; @@v34@@ = tcg_const_i64 ( @@v22@@ ) ; gen_helper_get_cp_reg64 ( @@v20@@ , cpu_env , @@v34@@ ) ; tcg_temp_free_ptr ( @@v34@@ ) ; } else { @@v20@@ = tcg_temp_new_i64 ( ) ; tcg_gen_ld_i64 ( @@v20@@ , cpu_env , * ( _QWORD * ) ( @@v22@@ + Number ) ) ; } v35 = tcg_temp_new_i32 ( ) ; tcg_gen_extrl_i64_i32 ( v35 , @@v20@@ ) ; store_reg ( @@a1@@ , @@v19@@ , v35 ) ; v36 = tcg_temp_new_i32 ( ) ; tcg_gen_extrh_i64_i32 ( v36 , @@v20@@ ) ; tcg_temp_free_i64 ( @@v20@@ ) ; store_reg ( @@a1@@ , @@v14@@ , v36 ) ; } } else { if ( ( * ( _DWORD * ) ( @@v22@@ + Number ) & Number ) != Number ) return Number L ; if ( ( @@a2@@ & Number ) != Number ) { if ( * ( _QWORD * ) ( @@v22@@ + Number ) ) { @@v27@@ = load_reg ( @@a1@@ , @@v19@@ ) ; @@v28@@ = tcg_const_i64 ( @@v22@@ ) ; gen_helper_set_cp_reg ( cpu_env , @@v28@@ , @@v27@@ ) ; tcg_temp_free_ptr ( @@v28@@ ) ; tcg_temp_free_i32 ( @@v27@@ ) ; } else { @@v26@@ = load_reg ( @@a1@@ , @@v19@@ ) ; store_cpu_offset ( @@v26@@ , * ( _QWORD * ) ( @@v22@@ + Number ) ) ; } } else { @@v29@@ = tcg_temp_new_i64 ( ) ; @@v30@@ = load_reg ( @@a1@@ , @@v19@@ ) ; @@v31@@ = load_reg ( @@a1@@ , @@v14@@ ) ; tcg_gen_concat_i32_i64 ( @@v29@@ , @@v30@@ , @@v31@@ ) ; tcg_temp_free_i32 ( @@v30@@ ) ; tcg_temp_free_i32 ( @@v31@@ ) ; if ( * ( _QWORD * ) ( @@v22@@ + Number ) ) { @@v32@@ = tcg_const_i64 ( @@v22@@ ) ; gen_helper_set_cp_reg64 ( cpu_env , @@v32@@ , @@v29@@ ) ; tcg_temp_free_ptr ( @@v32@@ ) ; } else { tcg_gen_st_i64 ( @@v29@@ , cpu_env , * ( _QWORD * ) ( @@v22@@ + Number ) ) ; } tcg_temp_free_i64 ( @@v29@@ ) ; } } v5 = ( tb_cflags ( * ( _QWORD * ) @@a1@@ ) & Number ) != Number && ( * ( _DWORD * ) ( @@v22@@ + Number ) & Number ) != Number ; @@v10@@ = v5 ; if ( ! @@v18@@ && ( * ( _DWORD * ) ( @@v22@@ + Number ) & Number ) == Number ) { @@v37@@ = tcg_const_i32 ( * ( unsigned int * ) ( @@a1@@ + Number ) ) ; if ( arm_dc_feature ( @@a1@@ , Number ) ) gen_helper_rebuild_hflags_m32 ( cpu_env , @@v37@@ ) ; else gen_helper_rebuild_hflags_a32 ( cpu_env , @@v37@@ ) ; tcg_temp_free_i32 ( @@v37@@ ) ; @@v10@@ = Number ; } if ( @@v10@@ ) gen_lookup_tb ( @@a1@@ ) ; result = Number L ; } } else { if ( ( @@a2@@ & Number ) != Number ) { if ( qemu_loglevel_mask ( Number ) ) { if ( * ( _BYTE * ) ( @@a1@@ + Number ) ) v8 = String ; else v8 = String ; if ( @@v18@@ ) v9 = String ; else v9 = String ; qemu_log ( String , v9 , @@v16@@ , @@v12@@ , @@v11@@ , @@a2@@ & Number , @@v13@@ , v8 ) ; } } else if ( qemu_loglevel_mask ( Number ) ) { if ( * ( _BYTE * ) ( @@a1@@ + Number ) ) v6 = String ; else v6 = String ; if ( @@v18@@ ) v7 = String ; else v7 = String ; qemu_log ( String , v7 , @@v16@@ , @@v12@@ , @@a2@@ & Number , v6 ) ; } result = Number L ; } } return result ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "v24", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s104"}, {"n": "v23", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s112"}, {"n": "v22", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s120"}, {"n": "v21", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s128"}, {"n": "v20", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s136"}, {"n": "v19", "t": {"T": 1, "n": "int", "s": 4}, "location": "s140"}, {"n": "v18", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s144"}, {"n": "v17", "t": {"T": 1, "n": "int", "s": 4}, "location": "s148"}, {"n": "v16", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s156"}, {"n": "v15", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s160"}, {"n": "v14", "t": {"T": 1, "n": "int", "s": 4}, "location": "s164"}, {"n": "v13", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s168"}, {"n": "v12", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s172"}, {"n": "v11", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s176"}, {"n": "v10", "t": {"T": 1, "n": "char", "s": 1}, "location": "s177"}, {"n": "v34", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v33", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s32"}, {"n": "v32", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s40"}, {"n": "v31", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s48"}, {"n": "v30", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s56"}, {"n": "v29", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s64"}, {"n": "v28", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s72"}, {"n": "v37", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}, {"n": "v27", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s80"}, {"n": "v26", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s88"}, {"n": "v25", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s96"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "insn", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r64"}, {"n": "tcg_syn", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s104"}, {"n": "tmpptr", "t": {"T": 3, "t": "TCGv_ptr_d"}, "location": "s112"}, {"n": "ri", "t": {"T": 3, "t": "const ARMCPRegInfo_0"}, "location": "s120"}, {"n": "tmp_0", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s128"}, {"n": "tmp64", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s136"}, {"n": "rt", "t": {"T": 1, "n": "int", "s": 4}, "location": "s140"}, {"n": "isread", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "s144"}, {"n": "crm", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "s148"}, {"n": "cpnum", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "s156"}, {"n": "syndrome", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "s160"}, {"n": "rt2", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "s164"}, {"n": "opc2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s168"}, {"n": "opc1", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s172"}, {"n": "crn", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "s176"}, {"n": "need_exit_tb", "t": {"T": 1, "n": "bool", "s": 1}, "location": "s177"}, {"n": "tmpptr_0", "t": {"T": 3, "t": "TCGv_ptr_d"}, "location": "s24"}, {"n": "tmpptr_1", "t": {"T": 3, "t": "TCGv_ptr_d"}, "location": "s32"}, {"n": "tmpptr_2", "t": {"T": 3, "t": "TCGv_ptr_d"}, "location": "s40"}, {"n": "tmphi", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s48"}, {"n": "tmplo", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s56"}, {"n": "tmp64_0", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s64"}, {"n": "tmpptr_3", "t": {"T": 3, "t": "TCGv_ptr_d"}, "location": "s72"}, {"n": "tcg_el", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}, {"n": "tmp_1", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s80"}, {"n": "tmp_2", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s88"}, {"n": "tcg_isread", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s96"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 1,020 |
[
"{\"name\": \"extract32\", \"code\": \"__int64 __fastcall extract32 ( unsigned int @@a1@@ , int @@a2@@ , int @@a3@@ ) { if ( @@a2@@ < Number || @@a3@@ <= Number || @@a3@@ > Number - @@a2@@ ) _assert_fail ( String , String , Number , String ) ; return ( @@a1@@ >> @@a2@@ ) & ( Number >> ( Number - @@a3@@ ) ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"cp_access_ok\", \"code\": \"bool __fastcall cp_access_ok ( char @@a1@@ , __int64 @@a2@@ , char @@a3@@ ) { return ( ( * ( int * ) ( @@a2@@ + Number ) >> ( Number * @@a1@@ + @@a3@@ ) ) & Number ) != Number ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"syn_cp14_rt_trap\", \"code\": \"__int64 __fastcall syn_cp14_rt_trap ( int @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ , int @@a5@@ , int @@a6@@ , int @@a7@@ , int @@a8@@ , char @@a9@@ ) { int v9 ; if ( @@a9@@ ) v9 = Number ; else v9 = Number ; return @@a8@@ | ( Number * @@a7@@ ) | ( @@a5@@ << Number ) | ( @@a3@@ << Number ) | ( @@a4@@ << Number ) | ( @@a2@@ << Number ) | ( @@a1@@ << Number ) | v9 | ( unsigned int ) ( Number * @@a6@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"a6\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r80\"}, {\"n\": \"a7\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s-16\"}, {\"n\": \"a8\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s-24\"}, {\"n\": \"a9\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"s-32\"}]}",
"{\"name\": \"syn_cp15_rt_trap\", \"code\": \"__int64 __fastcall syn_cp15_rt_trap ( int @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ , int @@a5@@ , int @@a6@@ , int @@a7@@ , int @@a8@@ , char @@a9@@ ) { int v9 ; if ( @@a9@@ ) v9 = Number ; else v9 = Number ; return @@a8@@ | ( Number * @@a7@@ ) | ( @@a5@@ << Number ) | ( @@a3@@ << Number ) | ( @@a4@@ << Number ) | ( @@a2@@ << Number ) | ( @@a1@@ << Number ) | v9 | ( unsigned int ) ( Number * @@a6@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"a6\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r80\"}, {\"n\": \"a7\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s-16\"}, {\"n\": \"a8\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s-24\"}, {\"n\": \"a9\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"s-32\"}]}",
"{\"name\": \"syn_cp14_rrt_trap\", \"code\": \"__int64 __fastcall syn_cp14_rrt_trap ( int @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ , int @@a5@@ , int @@a6@@ , int @@a7@@ , char @@a8@@ ) { int v8 ; if ( @@a8@@ ) v8 = Number ; else v8 = Number ; return @@a7@@ | ( Number * @@a5@@ ) | ( @@a6@@ << Number ) | ( @@a3@@ << Number ) | ( @@a2@@ << Number ) | ( @@a1@@ << Number ) | v8 | ( unsigned int ) ( Number * @@a4@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"a6\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r80\"}, {\"n\": \"a7\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s-16\"}, {\"n\": \"a8\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"s-24\"}]}",
"{\"name\": \"syn_cp15_rrt_trap\", \"code\": \"__int64 __fastcall syn_cp15_rrt_trap ( int @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ , int @@a5@@ , int @@a6@@ , int @@a7@@ , char @@a8@@ ) { int v8 ; if ( @@a8@@ ) v8 = Number ; else v8 = Number ; return @@a7@@ | ( Number * @@a5@@ ) | ( @@a6@@ << Number ) | ( @@a3@@ << Number ) | ( @@a2@@ << Number ) | ( @@a1@@ << Number ) | v8 | ( unsigned int ) ( Number * @@a4@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"a6\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r80\"}, {\"n\": \"a7\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s-16\"}, {\"n\": \"a8\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"s-24\"}]}",
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_i64\", \"code\": \"__int64 __fastcall tcg_temp_free_i64 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i64_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_ptr\", \"code\": \"__int64 __fastcall tcg_temp_free_ptr ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_ptr_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_temp_new_i64\", \"code\": \"__int64 tcg_temp_new_i64 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i64 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"qemu_loglevel_mask\", \"code\": \"bool __fastcall qemu_loglevel_mask ( int @@a1@@ ) { return ( @@a1@@ & qemu_loglevel ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"tb_cflags\", \"code\": \"__int64 __fastcall tb_cflags ( __int64 @@a1@@ ) { return * ( unsigned int * ) ( @@a1@@ + Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_helper_access_check_cp_reg\", \"code\": \"unsigned __int64 __fastcall gen_helper_access_check_cp_reg ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v7@@ [ Number ] ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; @@v7@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v7@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v7@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v7@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; tcg_gen_callN ( & helper_access_check_cp_reg , Number L , Number L , @@v7@@ ) ; return __readfsqword ( Number ) ^ @@v8@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_set_cp_reg\", \"code\": \"unsigned __int64 __fastcall gen_helper_set_cp_reg ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ [ Number ] ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v5@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v5@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; tcg_gen_callN ( & helper_set_cp_reg , Number L , Number L , @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_get_cp_reg\", \"code\": \"unsigned __int64 __fastcall gen_helper_get_cp_reg ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_get_cp_reg , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_set_cp_reg64\", \"code\": \"unsigned __int64 __fastcall gen_helper_set_cp_reg64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ [ Number ] ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v5@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v5@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; tcg_gen_callN ( & helper_set_cp_reg64 , Number L , Number L , @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_get_cp_reg64\", \"code\": \"unsigned __int64 __fastcall gen_helper_get_cp_reg64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_get_cp_reg64 , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_rebuild_hflags_m32\", \"code\": \"unsigned __int64 __fastcall gen_helper_rebuild_hflags_m32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v3@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; tcg_gen_callN ( & helper_rebuild_hflags_m32 , Number L , Number L , @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_rebuild_hflags_a32\", \"code\": \"unsigned __int64 __fastcall gen_helper_rebuild_hflags_a32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v3@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; tcg_gen_callN ( & helper_rebuild_hflags_a32 , Number L , Number L , @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_ld_i64\", \"code\": \"__int64 __fastcall tcg_gen_ld_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_st_i64\", \"code\": \"__int64 __fastcall tcg_gen_st_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_io_start\", \"code\": \"__int64 gen_io_start ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_const_i32 ( Number L ) ; tcg_gen_st_i32 ( @@v1@@ , cpu_env , Number ) ; return tcg_temp_free_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_cpu_offset\", \"code\": \"__int64 __fastcall load_cpu_offset ( int @@a1@@ ) { __int64 @@v2@@ ; @@v2@@ = tcg_temp_new_i32 ( ) ; tcg_gen_ld_i32 ( @@v2@@ , cpu_env , @@a1@@ ) ; return @@v2@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_cpu_offset\", \"code\": \"__int64 __fastcall store_cpu_offset ( __int64 @@a1@@ , int @@a2@@ ) { tcg_gen_st_i32 ( @@a1@@ , cpu_env , @@a2@@ ) ; return tcg_temp_free_i32 ( @@a1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_set_cpsr\", \"code\": \"__int64 __fastcall gen_set_cpsr ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_const_i32 ( @@a2@@ ) ; gen_helper_cpsr_write ( cpu_env , @@a1@@ , @@v3@@ ) ; return tcg_temp_free_i32 ( @@v3@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_set_condexec\", \"code\": \"__int64 __fastcall gen_set_condexec ( __int64 @@a1@@ ) { __int64 @@result@@ ; int @@v2@@ ; __int64 @@v3@@ ; @@result@@ = * ( unsigned int * ) ( @@a1@@ + Number ) ; if ( ( _DWORD ) @@result@@ ) { @@v2@@ = ( Number * * ( _DWORD * ) ( @@a1@@ + Number ) ) | ( * ( int * ) ( @@a1@@ + Number ) >> Number ) ; @@v3@@ = tcg_temp_new_i32 ( ) ; tcg_gen_movi_i32 ( @@v3@@ , @@v2@@ ) ; @@result@@ = store_cpu_offset ( @@v3@@ , Number ) ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_set_pc_im\", \"code\": \"__int64 __fastcall gen_set_pc_im ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_movi_i32 ( qword_4BEB8 , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_lookup_tb\", \"code\": \"__int64 __fastcall gen_lookup_tb ( __int64 @@a1@@ ) { __int64 @@result@@ ; tcg_gen_movi_i32 ( qword_4BEB8 , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"disas_iwmmxt_insn\", \"code\": \"__int64 __fastcall disas_iwmmxt_insn ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 result ; int v3 ; int v4 ; int v5 ; int v6 ; int v7 ; int v8 ; int v9 ; int v10 ; unsigned int v11 ; int v12 ; int v13 ; int v14 ; unsigned int v15 ; int v16 ; int v17 ; unsigned int v18 ; int v19 ; int v20 ; int v21 ; int v22 ; int v23 ; int v24 ; int v25 ; int v26 ; int v27 ; int v28 ; int v29 ; int v30 ; int v31 ; int v32 ; unsigned int v33 ; int v34 ; int j ; int i ; int l ; int k ; int v39 ; int v40 ; int v41 ; int v42 ; int v43 ; int v44 ; int v45 ; int v46 ; int @@v47@@ ; int v48 ; int v49 ; int v50 ; int v51 ; int v52 ; int v53 ; int v54 ; int v55 ; int v56 ; int v57 ; int v58 ; int v59 ; int v60 ; int v61 ; int v62 ; int v63 ; int v64 ; int @@v65@@ ; __int64 v66 ; __int64 v67 ; __int64 v68 ; __int64 v69 ; __int64 v70 ; __int64 v71 ; __int64 v72 ; __int64 v73 ; __int64 v74 ; __int64 v75 ; __int64 v76 ; __int64 v77 ; __int64 v78 ; __int64 v79 ; __int64 v80 ; __int64 v81 ; __int64 v82 ; __int64 v83 ; __int64 v84 ; __int64 v85 ; __int64 v86 ; __int64 @@v87@@ ; __int64 @@v88@@ ; if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) != Number ) return Number L ; v11 = ( @@a2@@ >> Number ) & Number | ( unsigned __int8 ) ( @@a2@@ >> Number ) ; if ( v11 > Number ) return Number L ; if ( v11 < Number ) { if ( v11 > Number ) return Number L ; if ( v11 >= Number ) { switch ( v11 ) { case Number : case Number : LABEL_271 : if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) return Number L ; v45 = ( unsigned __int16 ) @@a2@@ >> Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v79 = tcg_temp_new_i32 ( ) ; if ( ( unsigned int ) gen_iwmmxt_shift ( @@a2@@ , Number , v79 ) ) goto LABEL_314 ; v26 = ( @@a2@@ >> Number ) & Number ; switch ( v26 ) { case Number : gen_helper_iwmmxt_srlq ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; break ; case Number : gen_helper_iwmmxt_srlw ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; break ; case Number : gen_helper_iwmmxt_srll ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; break ; } goto LABEL_316 ; case Number : goto LABEL_369 ; case Number : LABEL_258 : v43 = ( unsigned __int16 ) @@a2@@ >> Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v25 = ( @@a2@@ >> Number ) & Number ; if ( v25 == Number ) return Number L ; if ( v25 == Number ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_unpackhsl_M0 ( ) ; else gen_op_iwmmxt_unpackhul_M0 ( ) ; } else if ( v25 ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_unpackhsw_M0 ( ) ; else gen_op_iwmmxt_unpackhuw_M0 ( ) ; } else if ( ( @@a2@@ & Number ) != Number ) { gen_op_iwmmxt_unpackhsb_M0 ( ) ; } else { gen_op_iwmmxt_unpackhub_M0 ( ) ; } goto LABEL_385 ; case Number : LABEL_245 : v43 = ( unsigned __int16 ) @@a2@@ >> Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v24 = ( @@a2@@ >> Number ) & Number ; if ( v24 == Number ) return Number L ; if ( v24 == Number ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_unpacklsl_M0 ( ) ; else gen_op_iwmmxt_unpacklul_M0 ( ) ; } else if ( v24 ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_unpacklsw_M0 ( ) ; else gen_op_iwmmxt_unpackluw_M0 ( ) ; } else if ( ( @@a2@@ & Number ) != Number ) { gen_op_iwmmxt_unpacklsb_M0 ( ) ; } else { gen_op_iwmmxt_unpacklub_M0 ( ) ; } goto LABEL_385 ; case Number : LABEL_330 : v42 = ( unsigned __int16 ) @@a2@@ >> Number ; v58 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v31 = ( @@a2@@ >> Number ) & Number ; if ( v31 == Number ) return Number L ; if ( v31 == Number ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_maxsl_M0_wRn ( v58 ) ; else gen_op_iwmmxt_maxul_M0_wRn ( v58 ) ; } else if ( v31 ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_maxsw_M0_wRn ( v58 ) ; else gen_op_iwmmxt_maxuw_M0_wRn ( v58 ) ; } else if ( ( @@a2@@ & Number ) != Number ) { gen_op_iwmmxt_maxsb_M0_wRn ( v58 ) ; } else { gen_op_iwmmxt_maxub_M0_wRn ( v58 ) ; } break ; case Number : goto LABEL_357 ; case Number : goto LABEL_344 ; case Number : goto LABEL_356 ; default : return Number L ; } } else { if ( v11 > Number ) return Number L ; if ( v11 >= Number ) { switch ( v11 ) { case Number : LABEL_132 : v43 = ( unsigned __int16 ) @@a2@@ >> Number ; v55 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_avgw1_M0_wRn ( v55 ) ; else gen_op_iwmmxt_avgw0_M0_wRn ( v55 ) ; } else if ( ( @@a2@@ & Number ) != Number ) { gen_op_iwmmxt_avgb1_M0_wRn ( v55 ) ; } else { gen_op_iwmmxt_avgb0_M0_wRn ( v55 ) ; } goto LABEL_385 ; case Number : LABEL_222 : v64 = ( unsigned __int16 ) @@a2@@ >> Number ; if ( ( @@a2@@ & Number ) != Number || ( ( @@a2@@ >> Number ) & Number ) == Number ) return Number L ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v75 = tcg_temp_new_i32 ( ) ; v22 = ( @@a2@@ >> Number ) & Number ; if ( v22 == Number ) { gen_helper_iwmmxt_msbl ( v75 , cpu_M0 ) ; } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { if ( v22 ) gen_helper_iwmmxt_msbw ( v75 , cpu_M0 ) ; else gen_helper_iwmmxt_msbb ( v75 , cpu_M0 ) ; } goto LABEL_231 ; case Number : case Number : LABEL_292 : if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) return Number L ; v45 = ( unsigned __int16 ) @@a2@@ >> Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v79 = tcg_temp_new_i32 ( ) ; if ( ( unsigned int ) gen_iwmmxt_shift ( @@a2@@ , Number , v79 ) ) goto LABEL_314 ; v28 = ( @@a2@@ >> Number ) & Number ; switch ( v28 ) { case Number : gen_helper_iwmmxt_sllq ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; break ; case Number : gen_helper_iwmmxt_sllw ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; break ; case Number : gen_helper_iwmmxt_slll ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; break ; } goto LABEL_316 ; case Number : goto LABEL_232 ; case Number : LABEL_150 : v64 = ( unsigned __int16 ) @@a2@@ >> Number ; if ( v64 == Number || ( ( @@a2@@ >> Number ) & Number ) == Number ) return Number L ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v75 = tcg_temp_new_i32 ( ) ; v16 = ( @@a2@@ >> Number ) & Number ; if ( v16 == Number ) { tcg_gen_shri_i64 ( cpu_M0 , cpu_M0 , ( Number * ( _BYTE ) @@a2@@ ) & Number ) ; tcg_gen_extrl_i64_i32 ( v75 , cpu_M0 ) ; } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { if ( v16 ) { tcg_gen_shri_i64 ( cpu_M0 , cpu_M0 , ( Number * ( _BYTE ) @@a2@@ ) & Number ) ; tcg_gen_extrl_i64_i32 ( v75 , cpu_M0 ) ; if ( ( @@a2@@ & Number ) != Number ) tcg_gen_ext16s_i32 ( v75 , v75 ) ; else tcg_gen_andi_i32 ( v75 , v75 , Number ) ; } else { tcg_gen_shri_i64 ( cpu_M0 , cpu_M0 , ( Number * ( _BYTE ) @@a2@@ ) & Number ) ; tcg_gen_extrl_i64_i32 ( v75 , cpu_M0 ) ; if ( ( @@a2@@ & Number ) != Number ) tcg_gen_ext8s_i32 ( v75 , v75 ) ; else tcg_gen_andi_i32 ( v75 , v75 , Number L ) ; } } LABEL_231 : store_reg ( @@a1@@ , v64 , v75 ) ; return Number L ; case Number : goto LABEL_369 ; case Number : LABEL_99 : v43 = ( unsigned __int16 ) @@a2@@ >> Number ; v50 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v13 = ( @@a2@@ >> Number ) & Number ; if ( v13 == Number ) return Number L ; if ( v13 == Number ) { gen_op_iwmmxt_unpackhl_M0_wRn ( v50 ) ; } else if ( v13 ) { gen_op_iwmmxt_unpackhw_M0_wRn ( v50 ) ; } else { gen_op_iwmmxt_unpackhb_M0_wRn ( v50 ) ; } goto LABEL_385 ; case Number : LABEL_92 : v43 = ( unsigned __int16 ) @@a2@@ >> Number ; v49 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v12 = ( @@a2@@ >> Number ) & Number ; if ( v12 == Number ) return Number L ; if ( v12 == Number ) { gen_op_iwmmxt_unpackll_M0_wRn ( v49 ) ; } else if ( v12 ) { gen_op_iwmmxt_unpacklw_M0_wRn ( v49 ) ; } else { gen_op_iwmmxt_unpacklb_M0_wRn ( v49 ) ; } goto LABEL_385 ; case Number : LABEL_183 : if ( ( @@a2@@ & Number ) != ( _DWORD ) & loc_3F000 || ( ( @@a2@@ >> Number ) & Number ) == Number ) return Number L ; v78 = iwmmxt_load_creg ( Number ) ; v85 = tcg_temp_new_i32 ( ) ; tcg_gen_mov_i32 ( v85 , v78 ) ; v19 = ( @@a2@@ >> Number ) & Number ; if ( v19 == Number ) { tcg_gen_shli_i32 ( v85 , v85 , Number L ) ; tcg_gen_and_i32 ( v78 , v78 , v85 ) ; } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { if ( v19 ) { for ( i = Number ; i <= Number ; ++ i ) { tcg_gen_shli_i32 ( v85 , v85 , Number L ) ; tcg_gen_and_i32 ( v78 , v78 , v85 ) ; } } else { for ( j = Number ; j <= Number ; ++ j ) { tcg_gen_shli_i32 ( v85 , v85 , Number L ) ; tcg_gen_and_i32 ( v78 , v78 , v85 ) ; } } } goto LABEL_198 ; case Number : LABEL_206 : if ( ( @@a2@@ & Number ) != ( _DWORD ) & loc_3F000 || ( ( @@a2@@ >> Number ) & Number ) == Number ) return Number L ; v78 = iwmmxt_load_creg ( Number ) ; v85 = tcg_temp_new_i32 ( ) ; tcg_gen_mov_i32 ( v85 , v78 ) ; v21 = ( @@a2@@ >> Number ) & Number ; if ( v21 == Number ) { tcg_gen_shli_i32 ( v85 , v85 , Number L ) ; tcg_gen_or_i32 ( v78 , v78 , v85 ) ; } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { if ( v21 ) { for ( k = Number ; k <= Number ; ++ k ) { tcg_gen_shli_i32 ( v85 , v85 , Number L ) ; tcg_gen_or_i32 ( v78 , v78 , v85 ) ; } } else { for ( l = Number ; l <= Number ; ++ l ) { tcg_gen_shli_i32 ( v85 , v85 , Number L ) ; tcg_gen_or_i32 ( v78 , v78 , v85 ) ; } } } LABEL_198 : gen_set_cpsr ( v78 , Number ) ; tcg_temp_free_i32 ( v85 ) ; tcg_temp_free_i32 ( v78 ) ; return Number L ; case Number : goto LABEL_317 ; case Number : LABEL_164 : if ( ( @@a2@@ & Number ) != ( _DWORD ) & loc_3F000 || ( ( @@a2@@ >> Number ) & Number ) == Number ) return Number L ; v76 = iwmmxt_load_creg ( Number ) ; v17 = ( @@a2@@ >> Number ) & Number ; if ( v17 == Number ) { tcg_gen_shri_i32 ( v76 , v76 , ( ( Number * ( _BYTE ) @@a2@@ ) & Number ) + Number ) ; } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { if ( v17 ) tcg_gen_shri_i32 ( v76 , v76 , ( ( Number * ( _BYTE ) @@a2@@ ) & Number ) + Number ) ; else tcg_gen_shri_i32 ( v76 , v76 , ( Number * ( _BYTE ) @@a2@@ ) & Number ) ; } tcg_gen_shli_i32 ( v76 , v76 , Number L ) ; gen_set_cpsr ( v76 , Number ) ; tcg_temp_free_i32 ( v76 ) ; break ; case Number : goto LABEL_357 ; case Number : goto LABEL_344 ; case Number : goto LABEL_356 ; default : return Number L ; } return Number L ; } if ( v11 > Number ) return Number L ; if ( v11 < Number ) { if ( v11 <= Number ) { if ( v11 >= Number ) { switch ( v11 ) { case Number : LABEL_139 : gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v73 = iwmmxt_load_creg ( ( ( @@a2@@ >> Number ) & Number ) + Number ) ; tcg_gen_andi_i32 ( v73 , v73 , Number L ) ; iwmmxt_load_reg ( cpu_V1 , @@a2@@ & Number ) ; gen_helper_iwmmxt_align ( cpu_M0 , cpu_M0 , cpu_V1 , v73 ) ; tcg_temp_free_i32 ( v73 ) ; gen_op_iwmmxt_movq_wRn_M0 ( ( unsigned __int16 ) @@a2@@ >> Number ) ; gen_op_iwmmxt_set_mup ( ) ; return Number L ; case Number : case Number : goto LABEL_302 ; case Number : goto LABEL_232 ; case Number : goto LABEL_369 ; case Number : goto LABEL_317 ; case Number : goto LABEL_357 ; case Number : goto LABEL_344 ; case Number : goto LABEL_356 ; default : return Number L ; } } if ( v11 <= Number ) { if ( v11 >= Number ) { switch ( v11 ) { case Number : goto LABEL_139 ; case Number : case Number : goto LABEL_271 ; case Number : goto LABEL_369 ; case Number : goto LABEL_258 ; case Number : goto LABEL_245 ; case Number : LABEL_89 : v42 = ( unsigned __int16 ) @@a2@@ >> Number ; v48 = HIWORD ( @@a2@@ ) & Number ; gen_op_iwmmxt_movq_M0_wRn ( @@a2@@ & Number ) ; if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_maddsq_M0_wRn ( v48 ) ; else gen_op_iwmmxt_madduq_M0_wRn ( v48 ) ; goto LABEL_124 ; case Number : goto LABEL_330 ; case Number : goto LABEL_357 ; case Number : goto LABEL_344 ; case Number : goto LABEL_356 ; default : return Number L ; } } if ( v11 <= Number ) { if ( v11 >= Number ) { switch ( v11 ) { case Number : goto LABEL_132 ; case Number : goto LABEL_139 ; case Number : goto LABEL_222 ; case Number : case Number : goto LABEL_292 ; case Number : goto LABEL_232 ; case Number : goto LABEL_150 ; case Number : goto LABEL_369 ; case Number : goto LABEL_99 ; case Number : goto LABEL_92 ; case Number : goto LABEL_183 ; case Number : goto LABEL_206 ; case Number : goto LABEL_317 ; case Number : goto LABEL_164 ; case Number : goto LABEL_357 ; case Number : goto LABEL_344 ; case Number : goto LABEL_356 ; default : return Number L ; } } if ( v11 <= Number ) { if ( v11 >= Number ) { switch ( v11 ) { case Number : goto LABEL_132 ; case Number : goto LABEL_139 ; case Number : case Number : goto LABEL_282 ; case Number : goto LABEL_125 ; case Number : goto LABEL_369 ; case Number : goto LABEL_258 ; case Number : goto LABEL_245 ; case Number : goto LABEL_89 ; case Number : goto LABEL_330 ; case Number : goto LABEL_357 ; case Number : goto LABEL_344 ; case Number : goto LABEL_199 ; case Number : goto LABEL_356 ; default : return Number L ; } } if ( v11 <= Number ) { if ( v11 >= Number ) { switch ( v11 ) { case Number : LABEL_343 : gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v80 = tcg_const_i32 ( ( @@a2@@ >> Number ) & Number ) ; iwmmxt_load_reg ( cpu_V1 , @@a2@@ & Number ) ; gen_helper_iwmmxt_align ( cpu_M0 , cpu_M0 , cpu_V1 , v80 ) ; tcg_temp_free_i32 ( v80 ) ; gen_op_iwmmxt_movq_wRn_M0 ( ( unsigned __int16 ) @@a2@@ >> Number ) ; gen_op_iwmmxt_set_mup ( ) ; return Number L ; case Number : case Number : goto LABEL_302 ; case Number : goto LABEL_232 ; case Number : goto LABEL_369 ; case Number : LABEL_119 : v42 = ( unsigned __int16 ) @@a2@@ >> Number ; v53 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_macsw_M0_wRn ( v53 ) ; else gen_op_iwmmxt_macuw_M0_wRn ( v53 ) ; if ( ( @@a2@@ & Number ) == Number ) { iwmmxt_load_reg ( cpu_V1 , v42 ) ; tcg_gen_add_i64 ( cpu_M0 , cpu_M0 , cpu_V1 ) ; } goto LABEL_124 ; case Number : goto LABEL_317 ; case Number : goto LABEL_357 ; case Number : goto LABEL_344 ; case Number : goto LABEL_356 ; default : return Number L ; } } if ( v11 <= Number ) { if ( v11 >= Number ) { switch ( v11 ) { case Number : case Number : case Number : case Number : if ( ( unsigned __int8 ) @@a2@@ >> Number == Number ) return Number L ; v44 = HIWORD ( @@a2@@ ) & Number ; v74 = load_reg ( @@a1@@ , ( unsigned __int16 ) @@a2@@ >> Number ) ; gen_op_iwmmxt_movq_M0_wRn ( v44 ) ; v15 = ( unsigned __int8 ) @@a2@@ >> Number ; if ( v15 == Number ) { v84 = tcg_const_i32 ( Number ) ; @@v87@@ = tcg_const_i32 ( ( Number * ( _BYTE ) @@a2@@ ) & Number ) ; } else if ( v15 > Number ) { v84 = Number L ; @@v87@@ = Number L ; } else if ( ( unsigned __int8 ) @@a2@@ >> Number ) { v84 = tcg_const_i32 ( Number ) ; @@v87@@ = tcg_const_i32 ( ( Number * ( _BYTE ) @@a2@@ ) & Number ) ; } else { v84 = tcg_const_i32 ( Number L ) ; @@v87@@ = tcg_const_i32 ( ( Number * ( _BYTE ) @@a2@@ ) & Number ) ; } gen_helper_iwmmxt_insr ( cpu_M0 , cpu_M0 , v74 , v84 , @@v87@@ ) ; tcg_temp_free_i32 ( @@v87@@ ) ; tcg_temp_free_i32 ( v84 ) ; tcg_temp_free_i32 ( v74 ) ; gen_op_iwmmxt_movq_wRn_M0 ( v44 ) ; gen_op_iwmmxt_set_mup ( ) ; break ; case Number : goto LABEL_343 ; case Number : case Number : goto LABEL_271 ; case Number : goto LABEL_369 ; case Number : goto LABEL_258 ; case Number : goto LABEL_245 ; case Number : goto LABEL_119 ; case Number : goto LABEL_330 ; case Number : goto LABEL_357 ; case Number : goto LABEL_344 ; case Number : goto LABEL_356 ; default : return Number L ; } return Number L ; } if ( v11 <= Number ) { if ( v11 >= Number ) { switch ( v11 ) { case Number : case Number : case Number : case Number : if ( ( unsigned __int8 ) @@a2@@ >> Number == Number ) return Number L ; v77 = load_reg ( @@a1@@ , ( unsigned __int16 ) @@a2@@ >> Number ) ; v18 = ( unsigned __int8 ) @@a2@@ >> Number ; if ( v18 == Number ) { gen_helper_iwmmxt_bcstl ( cpu_M0 , v77 ) ; } else if ( v18 <= Number ) { if ( ( unsigned __int8 ) @@a2@@ >> Number ) gen_helper_iwmmxt_bcstw ( cpu_M0 , v77 ) ; else gen_helper_iwmmxt_bcstb ( cpu_M0 , v77 ) ; } tcg_temp_free_i32 ( v77 ) ; gen_op_iwmmxt_movq_wRn_M0 ( HIWORD ( @@a2@@ ) & Number ) ; gen_op_iwmmxt_set_mup ( ) ; break ; case Number : case Number : goto LABEL_343 ; case Number : case Number : goto LABEL_282 ; case Number : goto LABEL_125 ; case Number : case Number : goto LABEL_369 ; case Number : goto LABEL_258 ; case Number : goto LABEL_245 ; case Number : case Number : goto LABEL_119 ; case Number : case Number : LABEL_106 : v42 = ( unsigned __int16 ) @@a2@@ >> Number ; v51 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_sadw_M0_wRn ( v51 ) ; else gen_op_iwmmxt_sadb_M0_wRn ( v51 ) ; if ( ( @@a2@@ & Number ) == Number ) gen_op_iwmmxt_addl_M0_wRn ( v42 ) ; goto LABEL_124 ; case Number : goto LABEL_330 ; case Number : case Number : goto LABEL_357 ; case Number : case Number : goto LABEL_344 ; case Number : goto LABEL_199 ; case Number : case Number : goto LABEL_356 ; case Number : goto LABEL_222 ; case Number : case Number : goto LABEL_292 ; case Number : goto LABEL_232 ; case Number : goto LABEL_150 ; case Number : goto LABEL_99 ; case Number : goto LABEL_92 ; case Number : goto LABEL_183 ; case Number : goto LABEL_206 ; case Number : goto LABEL_317 ; case Number : goto LABEL_164 ; default : return Number L ; } return Number L ; } if ( v11 <= Number ) { switch ( v11 ) { case Number : gen_op_iwmmxt_movq_M0_wRn ( @@a2@@ & Number ) ; gen_op_iwmmxt_orq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; gen_op_iwmmxt_setpsr_nz ( ) ; gen_op_iwmmxt_movq_wRn_M0 ( ( unsigned __int16 ) @@a2@@ >> Number ) ; gen_op_iwmmxt_set_mup ( ) ; gen_op_iwmmxt_set_cup ( ) ; return Number L ; case Number : case Number : goto LABEL_343 ; case Number : case Number : goto LABEL_282 ; case Number : goto LABEL_125 ; case Number : case Number : goto LABEL_369 ; case Number : goto LABEL_258 ; case Number : goto LABEL_245 ; case Number : case Number : goto LABEL_112 ; case Number : if ( ( @@a2@@ & Number ) == Number ) { v63 = ( unsigned __int16 ) @@a2@@ >> Number ; v41 = HIWORD ( @@a2@@ ) & Number ; switch ( v41 ) { case Number : case Number : return Number L ; case Number : gen_op_iwmmxt_set_cup ( ) ; goto LABEL_80 ; case Number : LABEL_80 : v70 = iwmmxt_load_creg ( v41 ) ; v83 = load_reg ( @@a1@@ , v63 ) ; tcg_gen_andc_i32 ( v70 , v70 , v83 ) ; tcg_temp_free_i32 ( v83 ) ; iwmmxt_store_creg ( v41 , v70 ) ; return Number L ; case Number : case Number : case Number : case Number : gen_op_iwmmxt_set_cup ( ) ; v71 = load_reg ( @@a1@@ , v63 ) ; iwmmxt_store_creg ( v41 , v71 ) ; return Number L ; default : return Number L ; } } return Number L ; case Number : case Number : goto LABEL_106 ; case Number : goto LABEL_330 ; case Number : case Number : goto LABEL_357 ; case Number : case Number : goto LABEL_344 ; case Number : goto LABEL_199 ; case Number : case Number : goto LABEL_356 ; case Number : gen_op_iwmmxt_movq_M0_wRn ( @@a2@@ & Number ) ; gen_op_iwmmxt_xorq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; gen_op_iwmmxt_setpsr_nz ( ) ; gen_op_iwmmxt_movq_wRn_M0 ( ( unsigned __int16 ) @@a2@@ >> Number ) ; gen_op_iwmmxt_set_mup ( ) ; gen_op_iwmmxt_set_cup ( ) ; return Number L ; case Number : goto LABEL_222 ; case Number : case Number : goto LABEL_292 ; case Number : goto LABEL_232 ; case Number : goto LABEL_150 ; case Number : goto LABEL_99 ; case Number : goto LABEL_92 ; case Number : if ( ( @@a2@@ & Number ) != Number ) return Number L ; v72 = iwmmxt_load_creg ( HIWORD ( @@a2@@ ) & Number ) ; store_reg ( @@a1@@ , ( unsigned __int16 ) @@a2@@ >> Number , v72 ) ; break ; case Number : goto LABEL_183 ; case Number : goto LABEL_206 ; case Number : goto LABEL_317 ; case Number : goto LABEL_164 ; default : return Number L ; } return Number L ; } if ( v11 <= Number && v11 >= Number ) { switch ( v11 ) { case Number : gen_op_iwmmxt_movq_M0_wRn ( @@a2@@ & Number ) ; gen_op_iwmmxt_andq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; gen_op_iwmmxt_setpsr_nz ( ) ; gen_op_iwmmxt_movq_wRn_M0 ( ( unsigned __int16 ) @@a2@@ >> Number ) ; gen_op_iwmmxt_set_mup ( ) ; gen_op_iwmmxt_set_cup ( ) ; return Number L ; case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : case Number : v46 = ( @@a2@@ >> Number ) & Number ; @@v47@@ = ( unsigned __int16 ) @@a2@@ >> Number ; v62 = @@a2@@ & Number ; if ( @@v47@@ == Number || v62 == Number ) return Number L ; gen_op_iwmmxt_movq_M0_wRn ( v46 ) ; v82 = load_reg ( @@a1@@ , @@v47@@ ) ; v86 = load_reg ( @@a1@@ , v62 ) ; v33 = HIWORD ( @@a2@@ ) & Number ; if ( v33 >= Number ) { if ( ( @@a2@@ & Number ) != Number ) tcg_gen_shri_i32 ( v82 , v82 , Number L ) ; if ( ( @@a2@@ & Number ) != Number ) tcg_gen_shri_i32 ( v86 , v86 , Number L ) ; gen_helper_iwmmxt_muladdswl ( cpu_M0 , cpu_M0 , v82 , v86 ) ; } else if ( v33 ) { if ( v33 != Number ) { tcg_temp_free_i32 ( v86 ) ; tcg_temp_free_i32 ( v82 ) ; return Number L ; } gen_helper_iwmmxt_muladdsw ( cpu_M0 , cpu_M0 , v82 , v86 ) ; } else { gen_helper_iwmmxt_muladdsl ( cpu_M0 , cpu_M0 , v82 , v86 ) ; } tcg_temp_free_i32 ( v86 ) ; tcg_temp_free_i32 ( v82 ) ; gen_op_iwmmxt_movq_wRn_M0 ( v46 ) ; gen_op_iwmmxt_set_mup ( ) ; break ; case Number : case Number : goto LABEL_343 ; case Number : case Number : goto LABEL_271 ; case Number : case Number : goto LABEL_369 ; case Number : goto LABEL_258 ; case Number : goto LABEL_245 ; case Number : case Number : LABEL_112 : v42 = ( unsigned __int16 ) @@a2@@ >> Number ; v52 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_mulshw_M0_wRn ( v52 ) ; else gen_op_iwmmxt_mulslw_M0_wRn ( v52 ) ; } else if ( ( @@a2@@ & Number ) != Number ) { gen_op_iwmmxt_muluhw_M0_wRn ( v52 ) ; } else { gen_op_iwmmxt_mululw_M0_wRn ( v52 ) ; } goto LABEL_124 ; case Number : goto LABEL_330 ; case Number : case Number : goto LABEL_357 ; case Number : case Number : goto LABEL_344 ; case Number : case Number : goto LABEL_356 ; case Number : gen_op_iwmmxt_movq_M0_wRn ( @@a2@@ & Number ) ; tcg_gen_neg_i64 ( cpu_M0 , cpu_M0 ) ; gen_op_iwmmxt_andq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; gen_op_iwmmxt_setpsr_nz ( ) ; gen_op_iwmmxt_movq_wRn_M0 ( ( unsigned __int16 ) @@a2@@ >> Number ) ; gen_op_iwmmxt_set_mup ( ) ; gen_op_iwmmxt_set_cup ( ) ; return Number L ; case Number : case Number : goto LABEL_302 ; case Number : goto LABEL_232 ; case Number : goto LABEL_317 ; default : return Number L ; } return Number L ; } } } } } } } } return Number L ; } switch ( v11 ) { case Number : goto LABEL_132 ; case Number : case Number : LABEL_282 : if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) return Number L ; v45 = ( unsigned __int16 ) @@a2@@ >> Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v79 = tcg_temp_new_i32 ( ) ; if ( ( unsigned int ) gen_iwmmxt_shift ( @@a2@@ , Number , v79 ) ) goto LABEL_314 ; v27 = ( @@a2@@ >> Number ) & Number ; switch ( v27 ) { case Number : gen_helper_iwmmxt_sraq ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; break ; case Number : gen_helper_iwmmxt_sraw ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; break ; case Number : gen_helper_iwmmxt_sral ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; break ; } goto LABEL_316 ; case Number : LABEL_125 : v43 = ( unsigned __int16 ) @@a2@@ >> Number ; v54 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v14 = ( @@a2@@ >> Number ) & Number ; if ( v14 == Number ) return Number L ; if ( v14 == Number ) { gen_op_iwmmxt_cmpeql_M0_wRn ( v54 ) ; } else if ( v14 ) { gen_op_iwmmxt_cmpeqw_M0_wRn ( v54 ) ; } else { gen_op_iwmmxt_cmpeqb_M0_wRn ( v54 ) ; } goto LABEL_385 ; case Number : goto LABEL_369 ; case Number : goto LABEL_258 ; case Number : goto LABEL_245 ; case Number : goto LABEL_330 ; case Number : goto LABEL_357 ; case Number : goto LABEL_344 ; case Number : LABEL_199 : v42 = ( unsigned __int16 ) @@a2@@ >> Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v20 = ( @@a2@@ >> Number ) & Number ; if ( v20 == Number ) return Number L ; if ( v20 == Number ) { gen_helper_iwmmxt_addcl ( cpu_M0 , cpu_M0 ) ; } else if ( v20 ) { gen_helper_iwmmxt_addcw ( cpu_M0 , cpu_M0 ) ; } else { gen_helper_iwmmxt_addcb ( cpu_M0 , cpu_M0 ) ; } break ; case Number : goto LABEL_356 ; default : return Number L ; } } LABEL_124 : gen_op_iwmmxt_movq_wRn_M0 ( v42 ) ; gen_op_iwmmxt_set_mup ( ) ; return Number L ; } switch ( v11 ) { case Number : case Number : LABEL_302 : if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) return Number L ; v45 = ( unsigned __int16 ) @@a2@@ >> Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v79 = tcg_temp_new_i32 ( ) ; v29 = ( @@a2@@ >> Number ) & Number ; switch ( v29 ) { case Number : if ( ! ( unsigned int ) gen_iwmmxt_shift ( @@a2@@ , Number , v79 ) ) { gen_helper_iwmmxt_rorq ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; goto LABEL_316 ; } break ; case Number : if ( ! ( unsigned int ) gen_iwmmxt_shift ( @@a2@@ , Number , v79 ) ) { gen_helper_iwmmxt_rorw ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; LABEL_316 : tcg_temp_free_i32 ( v79 ) ; gen_op_iwmmxt_movq_wRn_M0 ( v45 ) ; gen_op_iwmmxt_set_mup ( ) ; gen_op_iwmmxt_set_cup ( ) ; return Number L ; } break ; case Number : if ( ! ( unsigned int ) gen_iwmmxt_shift ( @@a2@@ , Number , v79 ) ) { gen_helper_iwmmxt_rorl ( cpu_M0 , cpu_env , cpu_M0 , v79 ) ; goto LABEL_316 ; } break ; default : goto LABEL_316 ; } LABEL_314 : tcg_temp_free_i32 ( v79 ) ; return Number L ; case Number : LABEL_232 : v43 = ( unsigned __int16 ) @@a2@@ >> Number ; v56 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v23 = ( @@a2@@ >> Number ) & Number ; if ( v23 == Number ) return Number L ; if ( v23 == Number ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_cmpgtsl_M0_wRn ( v56 ) ; else gen_op_iwmmxt_cmpgtul_M0_wRn ( v56 ) ; } else if ( v23 ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_cmpgtsw_M0_wRn ( v56 ) ; else gen_op_iwmmxt_cmpgtuw_M0_wRn ( v56 ) ; } else if ( ( @@a2@@ & Number ) != Number ) { gen_op_iwmmxt_cmpgtsb_M0_wRn ( v56 ) ; } else { gen_op_iwmmxt_cmpgtub_M0_wRn ( v56 ) ; } goto LABEL_385 ; case Number : LABEL_369 : if ( ( @@a2@@ & Number ) == Number || ( ( @@a2@@ >> Number ) & Number ) == Number ) return Number L ; v43 = ( unsigned __int16 ) @@a2@@ >> Number ; v61 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v32 = ( @@a2@@ >> Number ) & Number ; switch ( v32 ) { case Number : if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_packsq_M0_wRn ( v61 ) ; else gen_op_iwmmxt_packuq_M0_wRn ( v61 ) ; break ; case Number : if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_packsw_M0_wRn ( v61 ) ; else gen_op_iwmmxt_packuw_M0_wRn ( v61 ) ; break ; case Number : if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_packsl_M0_wRn ( v61 ) ; else gen_op_iwmmxt_packul_M0_wRn ( v61 ) ; break ; } LABEL_385 : gen_op_iwmmxt_movq_wRn_M0 ( v43 ) ; gen_op_iwmmxt_set_mup ( ) ; gen_op_iwmmxt_set_cup ( ) ; return Number L ; case Number : LABEL_317 : v42 = ( unsigned __int16 ) @@a2@@ >> Number ; v57 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v30 = ( @@a2@@ >> Number ) & Number ; if ( v30 == Number ) return Number L ; if ( v30 == Number ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_minsl_M0_wRn ( v57 ) ; else gen_op_iwmmxt_minul_M0_wRn ( v57 ) ; } else if ( v30 ) { if ( ( @@a2@@ & Number ) != Number ) gen_op_iwmmxt_minsw_M0_wRn ( v57 ) ; else gen_op_iwmmxt_minuw_M0_wRn ( v57 ) ; } else if ( ( @@a2@@ & Number ) != Number ) { gen_op_iwmmxt_minsb_M0_wRn ( v57 ) ; } else { gen_op_iwmmxt_minub_M0_wRn ( v57 ) ; } goto LABEL_124 ; case Number : LABEL_357 : v43 = ( unsigned __int16 ) @@a2@@ >> Number ; v60 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; switch ( ( @@a2@@ >> Number ) & Number ) { case Number : gen_op_iwmmxt_addnb_M0_wRn ( v60 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_addub_M0_wRn ( v60 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_addsb_M0_wRn ( v60 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_addnw_M0_wRn ( v60 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_adduw_M0_wRn ( v60 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_addsw_M0_wRn ( v60 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_addnl_M0_wRn ( v60 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_addul_M0_wRn ( v60 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_addsl_M0_wRn ( v60 ) ; goto LABEL_385 ; default : result = Number L ; break ; } return result ; case Number : LABEL_344 : v43 = ( unsigned __int16 ) @@a2@@ >> Number ; v59 = @@a2@@ & Number ; gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; switch ( ( @@a2@@ >> Number ) & Number ) { case Number : gen_op_iwmmxt_subnb_M0_wRn ( v59 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_subub_M0_wRn ( v59 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_subsb_M0_wRn ( v59 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_subnw_M0_wRn ( v59 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_subuw_M0_wRn ( v59 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_subsw_M0_wRn ( v59 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_subnl_M0_wRn ( v59 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_subul_M0_wRn ( v59 ) ; goto LABEL_385 ; case Number : gen_op_iwmmxt_subsl_M0_wRn ( v59 ) ; goto LABEL_385 ; default : result = Number L ; break ; } return result ; case Number : LABEL_356 : gen_op_iwmmxt_movq_M0_wRn ( HIWORD ( @@a2@@ ) & Number ) ; v81 = tcg_const_i32 ( HIWORD ( @@a2@@ ) & Number | @@a2@@ & Number ) ; gen_helper_iwmmxt_shufh ( cpu_M0 , cpu_env , cpu_M0 , v81 ) ; tcg_temp_free_i32 ( v81 ) ; gen_op_iwmmxt_movq_wRn_M0 ( ( unsigned __int16 ) @@a2@@ >> Number ) ; gen_op_iwmmxt_set_mup ( ) ; gen_op_iwmmxt_set_cup ( ) ; return Number L ; default : return Number L ; } } if ( ( @@a2@@ & Number ) == Number ) { v39 = @@a2@@ & Number ; @@v65@@ = HIWORD ( @@a2@@ ) & Number ; if ( ( @@a2@@ & Number ) != Number ) { iwmmxt_load_reg ( cpu_V0 , v39 ) ; tcg_gen_extrl_i64_i32 ( cpu_R [ ( unsigned __int16 ) @@a2@@ >> Number ] , cpu_V0 ) ; tcg_gen_extrh_i64_i32 ( cpu_R [ @@v65@@ ] , cpu_V0 ) ; } else { tcg_gen_concat_i32_i64 ( cpu_V0 , cpu_R [ ( unsigned __int16 ) @@a2@@ >> Number ] , cpu_R [ @@v65@@ ] ) ; iwmmxt_store_reg ( cpu_V0 , v39 ) ; gen_op_iwmmxt_set_mup ( ) ; } result = Number L ; } else { v40 = ( unsigned __int16 ) @@a2@@ >> Number ; @@v88@@ = tcg_temp_new_i32 ( ) ; if ( gen_iwmmxt_address ( @@a1@@ , @@a2@@ , @@v88@@ ) ) { tcg_temp_free_i32 ( @@v88@@ ) ; result = Number L ; } else { if ( ( @@a2@@ & Number ) != Number ) { if ( @@a2@@ >> Number == Number ) { v67 = tcg_temp_new_i32 ( ) ; v3 = get_mem_index ( @@a1@@ ) ; gen_aa32_ld32u ( @@a1@@ , v67 , @@v88@@ , v3 ) ; iwmmxt_store_creg ( v40 , v67 ) ; } else { v34 = Number ; if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) != Number ) { v4 = get_mem_index ( @@a1@@ ) ; gen_aa32_ld64 ( @@a1@@ , cpu_M0 , @@v88@@ , v4 ) ; v34 = Number ; } else { v66 = tcg_temp_new_i32 ( ) ; v5 = get_mem_index ( @@a1@@ ) ; gen_aa32_ld32u ( @@a1@@ , v66 , @@v88@@ , v5 ) ; } } else { v66 = tcg_temp_new_i32 ( ) ; v6 = get_mem_index ( @@a1@@ ) ; if ( ( @@a2@@ & Number ) != Number ) gen_aa32_ld16u ( @@a1@@ , v66 , @@v88@@ , v6 ) ; else gen_aa32_ld8u ( @@a1@@ , v66 , @@v88@@ , v6 ) ; } if ( v34 ) { tcg_gen_extu_i32_i64 ( cpu_M0 , v66 ) ; tcg_temp_free_i32 ( v66 ) ; } gen_op_iwmmxt_movq_wRn_M0 ( v40 ) ; } } else if ( @@a2@@ >> Number == Number ) { v68 = iwmmxt_load_creg ( v40 ) ; v7 = get_mem_index ( @@a1@@ ) ; gen_aa32_st32 ( @@a1@@ , v68 , @@v88@@ , v7 ) ; tcg_temp_free_i32 ( v68 ) ; } else { gen_op_iwmmxt_movq_M0_wRn ( v40 ) ; v69 = tcg_temp_new_i32 ( ) ; if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) != Number ) { v8 = get_mem_index ( @@a1@@ ) ; gen_aa32_st64 ( @@a1@@ , cpu_M0 , @@v88@@ , v8 ) ; } else { tcg_gen_extrl_i64_i32 ( v69 , cpu_M0 ) ; v9 = get_mem_index ( @@a1@@ ) ; gen_aa32_st32 ( @@a1@@ , v69 , @@v88@@ , v9 ) ; } } else { tcg_gen_extrl_i64_i32 ( v69 , cpu_M0 ) ; v10 = get_mem_index ( @@a1@@ ) ; if ( ( @@a2@@ & Number ) != Number ) gen_aa32_st16 ( @@a1@@ , v69 , @@v88@@ , v10 ) ; else gen_aa32_st8 ( @@a1@@ , v69 , @@v88@@ , v10 ) ; } tcg_temp_free_i32 ( v69 ) ; } tcg_temp_free_i32 ( @@v88@@ ) ; result = Number L ; } } return result ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v87\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v65\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s36\"}, {\"n\": \"v47\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s52\"}, {\"n\": \"v88\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"disas_dsp_insn\", \"code\": \"__int64 __fastcall disas_dsp_insn ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 result ; unsigned int v3 ; int @@v4@@ ; int @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( ( @@a2@@ & Number ) == Number ) { if ( ( unsigned __int8 ) @@a2@@ >> Number ) return Number L ; @@v6@@ = load_reg ( @@a1@@ , ( unsigned __int16 ) @@a2@@ >> Number ) ; @@v7@@ = load_reg ( @@a1@@ , @@a2@@ & Number ) ; v3 = HIWORD ( @@a2@@ ) & Number ; if ( v3 >= Number ) { if ( ( @@a2@@ & Number ) != Number ) tcg_gen_shri_i32 ( @@v6@@ , @@v6@@ , Number L ) ; if ( ( @@a2@@ & Number ) != Number ) tcg_gen_shri_i32 ( @@v7@@ , @@v7@@ , Number L ) ; gen_helper_iwmmxt_muladdswl ( cpu_M0 , cpu_M0 , @@v6@@ , @@v7@@ ) ; } else if ( v3 ) { if ( v3 != Number ) return Number L ; gen_helper_iwmmxt_muladdsw ( cpu_M0 , cpu_M0 , @@v6@@ , @@v7@@ ) ; } else { gen_helper_iwmmxt_muladdsl ( cpu_M0 , cpu_M0 , @@v6@@ , @@v7@@ ) ; } tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; gen_op_iwmmxt_movq_wRn_M0 ( ( unsigned __int8 ) @@a2@@ >> Number ) ; result = Number L ; } else if ( ( @@a2@@ & Number ) == Number ) { @@v4@@ = HIWORD ( @@a2@@ ) & Number ; @@v5@@ = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != Number ) { result = Number L ; } else { if ( ( @@a2@@ & Number ) != Number ) { iwmmxt_load_reg ( cpu_V0 , @@v5@@ ) ; tcg_gen_extrl_i64_i32 ( cpu_R [ ( unsigned __int16 ) @@a2@@ >> Number ] , cpu_V0 ) ; tcg_gen_extrh_i64_i32 ( cpu_R [ @@v4@@ ] , cpu_V0 ) ; tcg_gen_andi_i32 ( cpu_R [ @@v4@@ ] , cpu_R [ @@v4@@ ] , Number L ) ; } else { tcg_gen_concat_i32_i64 ( cpu_V0 , cpu_R [ ( unsigned __int16 ) @@a2@@ >> Number ] , cpu_R [ @@v4@@ ] ) ; iwmmxt_store_reg ( cpu_V0 , @@v5@@ ) ; } result = Number L ; } } else { result = Number L ; } return result ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s28\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s36\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
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