input
stringlengths 144
489k
| output
stringlengths 45
339k
| shard
stringclasses 16
values | filename
stringlengths 135
135
| line_num
int64 0
2.62k
| context
list |
|---|---|---|---|---|---|
{"name": "trans_VDIV_sp", "code": "__int64 __fastcall trans_VDIV_sp ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { return do_vfp_3op_sp ( @@a1@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 , __int64 ) ) gen_helper_vfp_divs , * @@a2@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VDIV_sp"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 821 |
[
"{\"name\": \"gen_helper_vfp_divs\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_divs ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_divs , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"do_vfp_3op_sp\", \"code\": \"__int64 __fastcall do_vfp_3op_sp ( __int64 @@a1@@ , void ( __fastcall * @@a2@@ ) ( __int64 , __int64 , __int64 , __int64 ) , unsigned int @@a3@@ , unsigned int @@a4@@ , unsigned int @@a5@@ , char @@a6@@ ) { int @@v11@@ ; int @@v12@@ ; int @@v13@@ ; __int64 @@v14@@ ; __int64 @@v15@@ ; __int64 @@v16@@ ; __int64 @@v17@@ ; @@v11@@ = Number ; LOBYTE ( @@v12@@ ) = Number ; @@v13@@ = * ( _DWORD * ) ( @@a1@@ + Number ) ; if ( ! isar_feature_aa32_fpshvec ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@v13@@ || * ( _DWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; if ( @@v13@@ > Number ) { if ( vfp_sreg_is_scalar ( @@a3@@ ) ) { @@v13@@ = Number ; } else { @@v12@@ = * ( _DWORD * ) ( @@a1@@ + Number ) + Number ; if ( vfp_sreg_is_scalar ( @@a5@@ ) ) @@v11@@ = Number ; else @@v11@@ = @@v12@@ ; } } @@v14@@ = tcg_temp_new_i32 ( ) ; @@v15@@ = tcg_temp_new_i32 ( ) ; @@v16@@ = tcg_temp_new_i32 ( ) ; @@v17@@ = get_fpstatus_ptr ( Number ) ; neon_load_reg32 ( @@v14@@ , @@a4@@ ) ; neon_load_reg32 ( @@v15@@ , @@a5@@ ) ; while ( Number ) { if ( @@a6@@ ) neon_load_reg32 ( @@v16@@ , @@a3@@ ) ; @@a2@@ ( @@v16@@ , @@v14@@ , @@v15@@ , @@v17@@ ) ; neon_store_reg32 ( @@v16@@ , @@a3@@ ) ; if ( ! @@v13@@ ) break ; -- @@v13@@ ; @@a3@@ = vfp_advance_sreg ( @@a3@@ , @@v12@@ ) ; @@a4@@ = vfp_advance_sreg ( @@a4@@ , @@v12@@ ) ; neon_load_reg32 ( @@v14@@ , @@a4@@ ) ; if ( @@v11@@ ) { @@a5@@ = vfp_advance_sreg ( @@a5@@ , @@v11@@ ) ; neon_load_reg32 ( @@v15@@ , @@a5@@ ) ; } } tcg_temp_free_i32 ( @@v14@@ ) ; tcg_temp_free_i32 ( @@v15@@ ) ; tcg_temp_free_i32 ( @@v16@@ ) ; tcg_temp_free_ptr ( @@v17@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64, __int64)\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"a6\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r80\"}, {\"n\": \"v16\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s44\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s48\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s52\"}, {\"n\": \"v17\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_VDIV_dp", "code": "__int64 __fastcall trans_VDIV_dp ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { return do_vfp_3op_dp ( @@a1@@ , ( void ( __fastcall * ) ( __int64 , __int64 , __int64 , __int64 ) ) gen_helper_vfp_divd , * @@a2@@ , @@a2@@ [ Number ] , @@a2@@ [ Number ] , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VDIV_dp"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 822 |
[
"{\"name\": \"gen_helper_vfp_divd\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_divd ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_divd , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"do_vfp_3op_dp\", \"code\": \"__int64 __fastcall do_vfp_3op_dp ( __int64 @@a1@@ , void ( __fastcall * @@a2@@ ) ( __int64 , __int64 , __int64 , __int64 ) , unsigned int @@a3@@ , unsigned int @@a4@@ , unsigned int @@a5@@ , char @@a6@@ ) { int @@v11@@ ; int @@v12@@ ; int @@v13@@ ; __int64 @@v14@@ ; __int64 @@v15@@ ; __int64 @@v16@@ ; __int64 @@v17@@ ; @@v11@@ = Number ; LOBYTE ( @@v12@@ ) = Number ; @@v13@@ = * ( _DWORD * ) ( @@a1@@ + Number ) ; if ( ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( ( ( unsigned __int8 ) @@a5@@ | ( unsigned __int8 ) ( @@a4@@ | @@a3@@ ) ) & Number ) != Number ) { return Number L ; } if ( ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ! isar_feature_aa32_fpshvec ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@v13@@ || * ( _DWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; if ( @@v13@@ > Number ) { if ( vfp_dreg_is_scalar ( @@a3@@ ) ) { @@v13@@ = Number ; } else { @@v12@@ = ( * ( int * ) ( @@a1@@ + Number ) >> Number ) + Number ; if ( vfp_dreg_is_scalar ( @@a5@@ ) ) @@v11@@ = Number ; else @@v11@@ = @@v12@@ ; } } @@v14@@ = tcg_temp_new_i64 ( ) ; @@v15@@ = tcg_temp_new_i64 ( ) ; @@v16@@ = tcg_temp_new_i64 ( ) ; @@v17@@ = get_fpstatus_ptr ( Number ) ; neon_load_reg64 ( @@v14@@ , @@a4@@ ) ; neon_load_reg64 ( @@v15@@ , @@a5@@ ) ; while ( Number ) { if ( @@a6@@ ) neon_load_reg64 ( @@v16@@ , @@a3@@ ) ; @@a2@@ ( @@v16@@ , @@v14@@ , @@v15@@ , @@v17@@ ) ; neon_store_reg64 ( @@v16@@ , @@a3@@ ) ; if ( ! @@v13@@ ) break ; -- @@v13@@ ; @@a3@@ = vfp_advance_dreg ( @@a3@@ , @@v12@@ ) ; @@a4@@ = vfp_advance_dreg ( @@a4@@ , @@v12@@ ) ; neon_load_reg64 ( @@v14@@ , @@a4@@ ) ; if ( @@v11@@ ) { @@a5@@ = vfp_advance_dreg ( @@a5@@ , @@v11@@ ) ; neon_load_reg64 ( @@v15@@ , @@a5@@ ) ; } } tcg_temp_free_i64 ( @@v14@@ ) ; tcg_temp_free_i64 ( @@v15@@ ) ; tcg_temp_free_i64 ( @@v16@@ ) ; tcg_temp_free_ptr ( @@v17@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64, __int64, __int64)\"}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"a6\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r80\"}, {\"n\": \"v16\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s60\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s64\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s68\"}, {\"n\": \"v17\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_VFM_sp", "code": "__int64 __fastcall trans_VFM_sp ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; __int64 @@v5@@ ; __int64 @@v6@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) || * ( _DWORD * ) ( @@a1@@ + Number ) || * ( _DWORD * ) ( @@a1@@ + Number ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; @@v3@@ = tcg_temp_new_i32 ( ) ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v5@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v3@@ , @@a2@@ [ Number ] ) ; neon_load_reg32 ( @@v4@@ , @@a2@@ [ Number ] ) ; if ( @@a2@@ [ Number ] ) gen_helper_vfp_negs ( @@v3@@ , @@v3@@ ) ; neon_load_reg32 ( @@v5@@ , @@a2@@ [ Number ] ) ; if ( ( * @@a2@@ & Number ) != Number ) gen_helper_vfp_negs ( @@v5@@ , @@v5@@ ) ; @@v6@@ = get_fpstatus_ptr ( Number ) ; gen_helper_vfp_muladds ( @@v5@@ , @@v3@@ , @@v4@@ , @@v5@@ , @@v6@@ ) ; neon_store_reg32 ( @@v5@@ , @@a2@@ [ Number ] ) ; tcg_temp_free_ptr ( @@v6@@ ) ; tcg_temp_free_i32 ( @@v3@@ ) ; tcg_temp_free_i32 ( @@v4@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s32"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VFM_sp"}, "location": "r64"}, {"n": "vd", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "vm", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s24"}, {"n": "vn", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s32"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 823 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_ptr\", \"code\": \"__int64 __fastcall tcg_temp_free_ptr ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_ptr_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_negs\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_negs ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i32_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_negs , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_muladds\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_muladds ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ ) { __int64 @@v5@@ ; __int64 @@v10@@ [ Number ] ; unsigned __int64 @@v11@@ ; @@v11@@ = __readfsqword ( Number ) ; @@v10@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v10@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v10@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v10@@ [ Number ] = tcgv_ptr_temp ( @@a5@@ ) ; @@v5@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_muladds , @@v5@@ , Number L , @@v10@@ ) ; return __readfsqword ( Number ) ^ @@v11@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r72\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v10\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"get_fpstatus_ptr\", \"code\": \"__int64 __fastcall get_fpstatus_ptr ( int @@a1@@ ) { int @@v2@@ ; __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_ptr ( ) ; if ( @@a1@@ ) @@v2@@ = Number ; else @@v2@@ = Number ; tcg_gen_addi_ptr ( @@v3@@ , cpu_env , @@v2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_load_reg\", \"code\": \"__int64 __fastcall neon_load_reg ( int @@a1@@ , int @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v2@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_ld_i32 ( @@v4@@ , cpu_env , @@v2@@ ) ; return @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_store_reg\", \"code\": \"__int64 __fastcall neon_store_reg ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; @@v3@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_st_i32 ( @@a3@@ , cpu_env , @@v3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_load_reg32\", \"code\": \"__int64 __fastcall neon_load_reg32 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_ld_i32 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_store_reg32\", \"code\": \"__int64 __fastcall neon_store_reg32 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_st_i32 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"vfp_access_check\", \"code\": \"__int64 __fastcall vfp_access_check ( __int64 @@a1@@ ) { return full_vfp_access_check ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}"
] |
{"name": "trans_VFM_dp", "code": "__int64 __fastcall trans_VFM_dp ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; __int64 @@v5@@ ; __int64 @@v6@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) || * ( _DWORD * ) ( @@a1@@ + Number ) || * ( _DWORD * ) ( @@a1@@ + Number ) ) return Number L ; if ( ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( ( ( unsigned __int8 ) ( * ( ( _BYTE * ) @@a2@@ + Number ) | * ( ( _BYTE * ) @@a2@@ + Number ) ) | ( unsigned __int8 ) @@a2@@ [ Number ] ) & Number ) != Number ) { return Number L ; } if ( ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; @@v3@@ = tcg_temp_new_i64 ( ) ; @@v4@@ = tcg_temp_new_i64 ( ) ; @@v5@@ = tcg_temp_new_i64 ( ) ; neon_load_reg64 ( @@v3@@ , @@a2@@ [ Number ] ) ; neon_load_reg64 ( @@v4@@ , @@a2@@ [ Number ] ) ; if ( @@a2@@ [ Number ] ) gen_helper_vfp_negd ( @@v3@@ , @@v3@@ ) ; neon_load_reg64 ( @@v5@@ , @@a2@@ [ Number ] ) ; if ( ( * @@a2@@ & Number ) != Number ) gen_helper_vfp_negd ( @@v5@@ , @@v5@@ ) ; @@v6@@ = get_fpstatus_ptr ( Number ) ; gen_helper_vfp_muladdd ( @@v5@@ , @@v3@@ , @@v4@@ , @@v5@@ , @@v6@@ ) ; neon_store_reg64 ( @@v5@@ , @@a2@@ [ Number ] ) ; tcg_temp_free_ptr ( @@v6@@ ) ; tcg_temp_free_i64 ( @@v3@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; tcg_temp_free_i64 ( @@v5@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s32"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VFM_dp"}, "location": "r64"}, {"n": "vd", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s16"}, {"n": "vm", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s24"}, {"n": "vn", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s32"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 824 |
[
"{\"name\": \"isar_feature_aa32_fp_d32\", \"code\": \"bool __fastcall isar_feature_aa32_fp_d32 ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) > Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_fpdp\", \"code\": \"bool __fastcall isar_feature_aa32_fpdp ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"tcg_temp_free_i64\", \"code\": \"__int64 __fastcall tcg_temp_free_i64 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i64_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_ptr\", \"code\": \"__int64 __fastcall tcg_temp_free_ptr ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_ptr_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i64\", \"code\": \"__int64 tcg_temp_new_i64 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i64 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_negd\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_negd ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i64_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_negd , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_muladdd\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_muladdd ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ , __int64 @@a5@@ ) { __int64 @@v5@@ ; __int64 @@v10@@ [ Number ] ; unsigned __int64 @@v11@@ ; @@v11@@ = __readfsqword ( Number ) ; @@v10@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v10@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v10@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v10@@ [ Number ] = tcgv_ptr_temp ( @@a5@@ ) ; @@v5@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_muladdd , @@v5@@ , Number L , @@v10@@ ) ; return __readfsqword ( Number ) ^ @@v11@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r72\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v10\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"get_fpstatus_ptr\", \"code\": \"__int64 __fastcall get_fpstatus_ptr ( int @@a1@@ ) { int @@v2@@ ; __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_ptr ( ) ; if ( @@a1@@ ) @@v2@@ = Number ; else @@v2@@ = Number ; tcg_gen_addi_ptr ( @@v3@@ , cpu_env , @@v2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_load_reg\", \"code\": \"__int64 __fastcall neon_load_reg ( int @@a1@@ , int @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v2@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_ld_i32 ( @@v4@@ , cpu_env , @@v2@@ ) ; return @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_store_reg\", \"code\": \"__int64 __fastcall neon_store_reg ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; @@v3@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_st_i32 ( @@a3@@ , cpu_env , @@v3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_load_reg64\", \"code\": \"__int64 __fastcall neon_load_reg64 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_store_reg64\", \"code\": \"__int64 __fastcall neon_store_reg64 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_st_i64 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"vfp_access_check\", \"code\": \"__int64 __fastcall vfp_access_check ( __int64 @@a1@@ ) { return full_vfp_access_check ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}"
] |
{"name": "trans_VMOV_imm_sp", "code": "__int64 __fastcall trans_VMOV_imm_sp ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { unsigned int @@v3@@ ; int @@v4@@ ; int @@v5@@ ; unsigned int @@v6@@ ; __int64 @@v7@@ ; LOBYTE ( @@v4@@ ) = Number ; @@v5@@ = * ( _DWORD * ) ( @@a1@@ + Number ) ; @@v6@@ = @@a2@@ [ Number ] ; if ( ! isar_feature_aa32_fpshvec ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@v5@@ || * ( _DWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; if ( @@v5@@ > Number ) { if ( vfp_sreg_is_scalar ( @@v6@@ ) ) @@v5@@ = Number ; else @@v4@@ = * ( _DWORD * ) ( @@a1@@ + Number ) + Number ; } @@v3@@ = vfp_expand_imm ( Number , * @@a2@@ ) ; @@v7@@ = tcg_const_i32 ( @@v3@@ ) ; neon_store_reg32 ( @@v7@@ , @@v6@@ ) ; while ( @@v5@@ ) { -- @@v5@@ ; @@v6@@ = vfp_advance_sreg ( @@v6@@ , @@v4@@ ) ; neon_store_reg32 ( @@v7@@ , @@v6@@ ) ; } tcg_temp_free_i32 ( @@v7@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r8"}, {"n": "v6", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s20"}, {"n": "v5", "t": {"T": 1, "n": "int", "s": 4}, "location": "s24"}, {"n": "v4", "t": {"T": 1, "n": "int", "s": 4}, "location": "s28"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VMOV_imm_sp"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r8"}, {"n": "vd", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "s20"}, {"n": "veclen", "t": {"T": 1, "n": "int", "s": 4}, "location": "s24"}, {"n": "delta_d", "t": {"T": 1, "n": "int", "s": 4}, "location": "s28"}, {"n": "fd", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 825 |
[
"{\"name\": \"isar_feature_aa32_fpshvec\", \"code\": \"bool __fastcall isar_feature_aa32_fpshvec ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"neon_store_reg\", \"code\": \"__int64 __fastcall neon_store_reg ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; @@v3@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_st_i32 ( @@a3@@ , cpu_env , @@v3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_store_reg32\", \"code\": \"__int64 __fastcall neon_store_reg32 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_st_i32 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"vfp_expand_imm\", \"code\": \"unsigned __int64 __fastcall vfp_expand_imm ( int @@a1@@ , unsigned __int8 @@a2@@ ) { int v2 ; int v3 ; int v4 ; int v5 ; int v6 ; int v7 ; unsigned __int64 @@v9@@ ; if ( @@a1@@ == Number ) { if ( ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) ) v2 = Number ; else v2 = Number ; if ( ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) ) v3 = Number ; else v3 = Number ; @@v9@@ = ( unsigned __int64 ) ( v2 | v3 | ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) ) << Number ; } else { if ( @@a1@@ > Number ) { LABEL_27 : g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; return @@v9@@ ; } if ( @@a1@@ == Number ) { if ( ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) ) v6 = Number ; else v6 = Number ; if ( ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) ) v7 = Number ; else v7 = Number ; @@v9@@ = v6 | v7 | ( ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) << Number ) ; } else { if ( @@a1@@ != Number ) goto LABEL_27 ; if ( ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) ) v4 = Number ; else v4 = Number ; if ( ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) ) v5 = Number ; else v5 = Number ; @@v9@@ = ( unsigned __int64 ) ( v4 | v5 | ( Number * ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) ) ) << Number ; } } return @@v9@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int8\", \"s\": 1}, \"location\": \"r64\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s24\"}]}",
"{\"name\": \"vfp_access_check\", \"code\": \"__int64 __fastcall vfp_access_check ( __int64 @@a1@@ ) { return full_vfp_access_check ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"vfp_sreg_is_scalar\", \"code\": \"bool __fastcall vfp_sreg_is_scalar ( char @@a1@@ ) { return ( @@a1@@ & Number ) == Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r56\"}]}",
"{\"name\": \"vfp_advance_sreg\", \"code\": \"__int64 __fastcall vfp_advance_sreg ( int @@a1@@ , char @@a2@@ ) { return ( ( _BYTE ) @@a1@@ + @@a2@@ ) & Number | @@a1@@ & Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}"
] |
{"name": "trans_VMOV_imm_dp", "code": "__int64 __fastcall trans_VMOV_imm_dp ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { unsigned __int64 @@v3@@ ; int @@v4@@ ; int @@v5@@ ; unsigned int @@v6@@ ; __int64 @@v7@@ ; LOBYTE ( @@v4@@ ) = Number ; @@v5@@ = * ( _DWORD * ) ( @@a1@@ + Number ) ; @@v6@@ = @@a2@@ [ Number ] ; if ( ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@v6@@ & Number ) != Number ) return Number L ; if ( ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ! isar_feature_aa32_fpshvec ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@v5@@ || * ( _DWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; if ( @@v5@@ > Number ) { if ( vfp_dreg_is_scalar ( @@v6@@ ) ) @@v5@@ = Number ; else @@v4@@ = ( * ( int * ) ( @@a1@@ + Number ) >> Number ) + Number ; } @@v3@@ = vfp_expand_imm ( Number , * @@a2@@ ) ; @@v7@@ = tcg_const_i64 ( @@v3@@ ) ; neon_store_reg64 ( @@v7@@ , @@v6@@ ) ; while ( @@v5@@ ) { -- @@v5@@ ; @@v6@@ = vfp_advance_dreg ( @@v6@@ , @@v4@@ ) ; neon_store_reg64 ( @@v7@@ , @@v6@@ ) ; } tcg_temp_free_i64 ( @@v7@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "r8"}, {"n": "v6", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s36"}, {"n": "v5", "t": {"T": 1, "n": "int", "s": 4}, "location": "s40"}, {"n": "v4", "t": {"T": 1, "n": "int", "s": 4}, "location": "s44"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VMOV_imm_dp"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "uint64_t", "s": 8}, "location": "r8"}, {"n": "vd", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "s36"}, {"n": "veclen", "t": {"T": 1, "n": "int", "s": 4}, "location": "s40"}, {"n": "delta_d", "t": {"T": 1, "n": "int", "s": 4}, "location": "s44"}, {"n": "fd", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 826 |
[
"{\"name\": \"isar_feature_aa32_fp_d32\", \"code\": \"bool __fastcall isar_feature_aa32_fp_d32 ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) > Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_fpshvec\", \"code\": \"bool __fastcall isar_feature_aa32_fpshvec ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_fpdp\", \"code\": \"bool __fastcall isar_feature_aa32_fpdp ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"tcg_temp_free_i64\", \"code\": \"__int64 __fastcall tcg_temp_free_i64 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i64_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"neon_store_reg\", \"code\": \"__int64 __fastcall neon_store_reg ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; @@v3@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_st_i32 ( @@a3@@ , cpu_env , @@v3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_store_reg64\", \"code\": \"__int64 __fastcall neon_store_reg64 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_st_i64 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"vfp_expand_imm\", \"code\": \"unsigned __int64 __fastcall vfp_expand_imm ( int @@a1@@ , unsigned __int8 @@a2@@ ) { int v2 ; int v3 ; int v4 ; int v5 ; int v6 ; int v7 ; unsigned __int64 @@v9@@ ; if ( @@a1@@ == Number ) { if ( ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) ) v2 = Number ; else v2 = Number ; if ( ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) ) v3 = Number ; else v3 = Number ; @@v9@@ = ( unsigned __int64 ) ( v2 | v3 | ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) ) << Number ; } else { if ( @@a1@@ > Number ) { LABEL_27 : g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; return @@v9@@ ; } if ( @@a1@@ == Number ) { if ( ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) ) v6 = Number ; else v6 = Number ; if ( ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) ) v7 = Number ; else v7 = Number ; @@v9@@ = v6 | v7 | ( ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) << Number ) ; } else { if ( @@a1@@ != Number ) goto LABEL_27 ; if ( ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) ) v4 = Number ; else v4 = Number ; if ( ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) ) v5 = Number ; else v5 = Number ; @@v9@@ = ( unsigned __int64 ) ( v4 | v5 | ( Number * ( unsigned int ) extract32 ( @@a2@@ , Number , Number ) ) ) << Number ; } } return @@v9@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned __int8\", \"s\": 1}, \"location\": \"r64\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s24\"}]}",
"{\"name\": \"vfp_access_check\", \"code\": \"__int64 __fastcall vfp_access_check ( __int64 @@a1@@ ) { return full_vfp_access_check ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"vfp_dreg_is_scalar\", \"code\": \"bool __fastcall vfp_dreg_is_scalar ( char @@a1@@ ) { return ( @@a1@@ & Number ) == Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r56\"}]}",
"{\"name\": \"vfp_advance_dreg\", \"code\": \"__int64 __fastcall vfp_advance_dreg ( int @@a1@@ , char @@a2@@ ) { return ( ( _BYTE ) @@a1@@ + @@a2@@ ) & Number | @@a1@@ & Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}"
] |
{"name": "trans_VMOV_reg_sp", "code": "__int64 __fastcall trans_VMOV_reg_sp ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { return do_vfp_2op_sp ( @@a1@@ , ( void ( __fastcall * ) ( __int64 , __int64 ) ) tcg_gen_mov_i32 , * @@a2@@ , @@a2@@ [ Number ] ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VMOV_reg_sp"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 827 |
[
"{\"name\": \"tcg_gen_mov_i32\", \"code\": \"__int64 __fastcall tcg_gen_mov_i32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@result@@ ; @@result@@ = @@a1@@ ; if ( @@a1@@ != @@a2@@ ) @@result@@ = tcg_gen_op2_i32 ( Number , @@a1@@ , @@a2@@ ) ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"do_vfp_2op_sp\", \"code\": \"__int64 __fastcall do_vfp_2op_sp ( __int64 @@a1@@ , void ( __fastcall * @@a2@@ ) ( __int64 , __int64 ) , unsigned int @@a3@@ , unsigned int @@a4@@ ) { int @@v8@@ ; int @@v9@@ ; int @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; @@v8@@ = Number ; LOBYTE ( @@v9@@ ) = Number ; @@v10@@ = * ( _DWORD * ) ( @@a1@@ + Number ) ; if ( ! isar_feature_aa32_fpshvec ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@v10@@ || * ( _DWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; if ( @@v10@@ > Number ) { if ( vfp_sreg_is_scalar ( @@a3@@ ) ) { @@v10@@ = Number ; } else { @@v9@@ = * ( _DWORD * ) ( @@a1@@ + Number ) + Number ; if ( vfp_sreg_is_scalar ( @@a4@@ ) ) @@v8@@ = Number ; else @@v8@@ = @@v9@@ ; } } @@v11@@ = tcg_temp_new_i32 ( ) ; @@v12@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v11@@ , @@a4@@ ) ; while ( Number ) { @@a2@@ ( @@v12@@ , @@v11@@ ) ; neon_store_reg32 ( @@v12@@ , @@a3@@ ) ; if ( ! @@v10@@ ) break ; if ( ! @@v8@@ ) { while ( @@v10@@ -- ) { @@a3@@ = vfp_advance_sreg ( @@a3@@ , @@v9@@ ) ; neon_store_reg32 ( @@v12@@ , @@a3@@ ) ; } break ; } -- @@v10@@ ; @@a3@@ = vfp_advance_sreg ( @@a3@@ , @@v9@@ ) ; @@a4@@ = vfp_advance_sreg ( @@a4@@ , @@v8@@ ) ; neon_load_reg32 ( @@v11@@ , @@a4@@ ) ; } tcg_temp_free_i32 ( @@v11@@ ) ; tcg_temp_free_i32 ( @@v12@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64)\"}, \"location\": \"r64\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s28\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s32\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s36\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_VMOV_reg_dp", "code": "__int64 __fastcall trans_VMOV_reg_dp ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { return do_vfp_2op_dp ( @@a1@@ , ( void ( __fastcall * ) ( __int64 , __int64 ) ) tcg_gen_mov_i64 , * @@a2@@ , @@a2@@ [ Number ] ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VMOV_reg_dp"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 828 |
[
"{\"name\": \"tcg_gen_mov_i64\", \"code\": \"__int64 __fastcall tcg_gen_mov_i64 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@result@@ ; @@result@@ = @@a1@@ ; if ( @@a1@@ != @@a2@@ ) @@result@@ = tcg_gen_op2_i64 ( Number , @@a1@@ , @@a2@@ ) ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"do_vfp_2op_dp\", \"code\": \"__int64 __fastcall do_vfp_2op_dp ( __int64 @@a1@@ , void ( __fastcall * @@a2@@ ) ( __int64 , __int64 ) , unsigned int @@a3@@ , unsigned int @@a4@@ ) { int @@v8@@ ; int @@v9@@ ; int @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; @@v8@@ = Number ; LOBYTE ( @@v9@@ ) = Number ; @@v10@@ = * ( _DWORD * ) ( @@a1@@ + Number ) ; if ( ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( ( ( unsigned __int8 ) @@a4@@ | ( unsigned __int8 ) @@a3@@ ) & Number ) != Number ) return Number L ; if ( ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ! isar_feature_aa32_fpshvec ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@v10@@ || * ( _DWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; if ( @@v10@@ > Number ) { if ( vfp_dreg_is_scalar ( @@a3@@ ) ) { @@v10@@ = Number ; } else { @@v9@@ = ( * ( int * ) ( @@a1@@ + Number ) >> Number ) + Number ; if ( vfp_dreg_is_scalar ( @@a4@@ ) ) @@v8@@ = Number ; else @@v8@@ = @@v9@@ ; } } @@v11@@ = tcg_temp_new_i64 ( ) ; @@v12@@ = tcg_temp_new_i64 ( ) ; neon_load_reg64 ( @@v11@@ , @@a4@@ ) ; while ( Number ) { @@a2@@ ( @@v12@@ , @@v11@@ ) ; neon_store_reg64 ( @@v12@@ , @@a3@@ ) ; if ( ! @@v10@@ ) break ; if ( ! @@v8@@ ) { while ( @@v10@@ -- ) { @@a3@@ = vfp_advance_dreg ( @@a3@@ , @@v9@@ ) ; neon_store_reg64 ( @@v12@@ , @@a3@@ ) ; } break ; } -- @@v10@@ ; vfp_advance_dreg ( @@a3@@ , @@v9@@ ) ; @@a3@@ = vfp_advance_dreg ( @@a4@@ , @@v8@@ ) ; neon_load_reg64 ( @@v11@@ , @@a4@@ ) ; } tcg_temp_free_i64 ( @@v11@@ ) ; tcg_temp_free_i64 ( @@v12@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64)\"}, \"location\": \"r64\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s44\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s48\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s52\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_VABS_sp", "code": "__int64 __fastcall trans_VABS_sp ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { return do_vfp_2op_sp ( @@a1@@ , ( void ( __fastcall * ) ( __int64 , __int64 ) ) gen_helper_vfp_abss , * @@a2@@ , @@a2@@ [ Number ] ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VABS_sp"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 829 |
[
"{\"name\": \"gen_helper_vfp_abss\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_abss ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i32_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_abss , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"do_vfp_2op_sp\", \"code\": \"__int64 __fastcall do_vfp_2op_sp ( __int64 @@a1@@ , void ( __fastcall * @@a2@@ ) ( __int64 , __int64 ) , unsigned int @@a3@@ , unsigned int @@a4@@ ) { int @@v8@@ ; int @@v9@@ ; int @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; @@v8@@ = Number ; LOBYTE ( @@v9@@ ) = Number ; @@v10@@ = * ( _DWORD * ) ( @@a1@@ + Number ) ; if ( ! isar_feature_aa32_fpshvec ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@v10@@ || * ( _DWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; if ( @@v10@@ > Number ) { if ( vfp_sreg_is_scalar ( @@a3@@ ) ) { @@v10@@ = Number ; } else { @@v9@@ = * ( _DWORD * ) ( @@a1@@ + Number ) + Number ; if ( vfp_sreg_is_scalar ( @@a4@@ ) ) @@v8@@ = Number ; else @@v8@@ = @@v9@@ ; } } @@v11@@ = tcg_temp_new_i32 ( ) ; @@v12@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v11@@ , @@a4@@ ) ; while ( Number ) { @@a2@@ ( @@v12@@ , @@v11@@ ) ; neon_store_reg32 ( @@v12@@ , @@a3@@ ) ; if ( ! @@v10@@ ) break ; if ( ! @@v8@@ ) { while ( @@v10@@ -- ) { @@a3@@ = vfp_advance_sreg ( @@a3@@ , @@v9@@ ) ; neon_store_reg32 ( @@v12@@ , @@a3@@ ) ; } break ; } -- @@v10@@ ; @@a3@@ = vfp_advance_sreg ( @@a3@@ , @@v9@@ ) ; @@a4@@ = vfp_advance_sreg ( @@a4@@ , @@v8@@ ) ; neon_load_reg32 ( @@v11@@ , @@a4@@ ) ; } tcg_temp_free_i32 ( @@v11@@ ) ; tcg_temp_free_i32 ( @@v12@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64)\"}, \"location\": \"r64\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s28\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s32\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s36\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_VABS_dp", "code": "__int64 __fastcall trans_VABS_dp ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { return do_vfp_2op_dp ( @@a1@@ , ( void ( __fastcall * ) ( __int64 , __int64 ) ) gen_helper_vfp_absd , * @@a2@@ , @@a2@@ [ Number ] ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VABS_dp"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 830 |
[
"{\"name\": \"gen_helper_vfp_absd\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_absd ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i64_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_absd , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"do_vfp_2op_dp\", \"code\": \"__int64 __fastcall do_vfp_2op_dp ( __int64 @@a1@@ , void ( __fastcall * @@a2@@ ) ( __int64 , __int64 ) , unsigned int @@a3@@ , unsigned int @@a4@@ ) { int @@v8@@ ; int @@v9@@ ; int @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; @@v8@@ = Number ; LOBYTE ( @@v9@@ ) = Number ; @@v10@@ = * ( _DWORD * ) ( @@a1@@ + Number ) ; if ( ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( ( ( unsigned __int8 ) @@a4@@ | ( unsigned __int8 ) @@a3@@ ) & Number ) != Number ) return Number L ; if ( ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ! isar_feature_aa32_fpshvec ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@v10@@ || * ( _DWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; if ( @@v10@@ > Number ) { if ( vfp_dreg_is_scalar ( @@a3@@ ) ) { @@v10@@ = Number ; } else { @@v9@@ = ( * ( int * ) ( @@a1@@ + Number ) >> Number ) + Number ; if ( vfp_dreg_is_scalar ( @@a4@@ ) ) @@v8@@ = Number ; else @@v8@@ = @@v9@@ ; } } @@v11@@ = tcg_temp_new_i64 ( ) ; @@v12@@ = tcg_temp_new_i64 ( ) ; neon_load_reg64 ( @@v11@@ , @@a4@@ ) ; while ( Number ) { @@a2@@ ( @@v12@@ , @@v11@@ ) ; neon_store_reg64 ( @@v12@@ , @@a3@@ ) ; if ( ! @@v10@@ ) break ; if ( ! @@v8@@ ) { while ( @@v10@@ -- ) { @@a3@@ = vfp_advance_dreg ( @@a3@@ , @@v9@@ ) ; neon_store_reg64 ( @@v12@@ , @@a3@@ ) ; } break ; } -- @@v10@@ ; vfp_advance_dreg ( @@a3@@ , @@v9@@ ) ; @@a3@@ = vfp_advance_dreg ( @@a4@@ , @@v8@@ ) ; neon_load_reg64 ( @@v11@@ , @@a4@@ ) ; } tcg_temp_free_i64 ( @@v11@@ ) ; tcg_temp_free_i64 ( @@v12@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64)\"}, \"location\": \"r64\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s44\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s48\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s52\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_VNEG_sp", "code": "__int64 __fastcall trans_VNEG_sp ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { return do_vfp_2op_sp ( @@a1@@ , ( void ( __fastcall * ) ( __int64 , __int64 ) ) gen_helper_vfp_negs , * @@a2@@ , @@a2@@ [ Number ] ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VNEG_sp"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 831 |
[
"{\"name\": \"gen_helper_vfp_negs\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_negs ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i32_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_negs , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"do_vfp_2op_sp\", \"code\": \"__int64 __fastcall do_vfp_2op_sp ( __int64 @@a1@@ , void ( __fastcall * @@a2@@ ) ( __int64 , __int64 ) , unsigned int @@a3@@ , unsigned int @@a4@@ ) { int @@v8@@ ; int @@v9@@ ; int @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; @@v8@@ = Number ; LOBYTE ( @@v9@@ ) = Number ; @@v10@@ = * ( _DWORD * ) ( @@a1@@ + Number ) ; if ( ! isar_feature_aa32_fpshvec ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@v10@@ || * ( _DWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; if ( @@v10@@ > Number ) { if ( vfp_sreg_is_scalar ( @@a3@@ ) ) { @@v10@@ = Number ; } else { @@v9@@ = * ( _DWORD * ) ( @@a1@@ + Number ) + Number ; if ( vfp_sreg_is_scalar ( @@a4@@ ) ) @@v8@@ = Number ; else @@v8@@ = @@v9@@ ; } } @@v11@@ = tcg_temp_new_i32 ( ) ; @@v12@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v11@@ , @@a4@@ ) ; while ( Number ) { @@a2@@ ( @@v12@@ , @@v11@@ ) ; neon_store_reg32 ( @@v12@@ , @@a3@@ ) ; if ( ! @@v10@@ ) break ; if ( ! @@v8@@ ) { while ( @@v10@@ -- ) { @@a3@@ = vfp_advance_sreg ( @@a3@@ , @@v9@@ ) ; neon_store_reg32 ( @@v12@@ , @@a3@@ ) ; } break ; } -- @@v10@@ ; @@a3@@ = vfp_advance_sreg ( @@a3@@ , @@v9@@ ) ; @@a4@@ = vfp_advance_sreg ( @@a4@@ , @@v8@@ ) ; neon_load_reg32 ( @@v11@@ , @@a4@@ ) ; } tcg_temp_free_i32 ( @@v11@@ ) ; tcg_temp_free_i32 ( @@v12@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64)\"}, \"location\": \"r64\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s28\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s32\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s36\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_VNEG_dp", "code": "__int64 __fastcall trans_VNEG_dp ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { return do_vfp_2op_dp ( @@a1@@ , ( void ( __fastcall * ) ( __int64 , __int64 ) ) gen_helper_vfp_negd , * @@a2@@ , @@a2@@ [ Number ] ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VNEG_dp"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 832 |
[
"{\"name\": \"gen_helper_vfp_negd\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_negd ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; unsigned __int64 @@v5@@ ; @@v5@@ = __readfsqword ( Number ) ; @@v4@@ = tcgv_i64_temp ( @@a2@@ ) ; @@v2@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_negd , @@v2@@ , Number L , & @@v4@@ ) ; return __readfsqword ( Number ) ^ @@v5@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"do_vfp_2op_dp\", \"code\": \"__int64 __fastcall do_vfp_2op_dp ( __int64 @@a1@@ , void ( __fastcall * @@a2@@ ) ( __int64 , __int64 ) , unsigned int @@a3@@ , unsigned int @@a4@@ ) { int @@v8@@ ; int @@v9@@ ; int @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; @@v8@@ = Number ; LOBYTE ( @@v9@@ ) = Number ; @@v10@@ = * ( _DWORD * ) ( @@a1@@ + Number ) ; if ( ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( ( ( unsigned __int8 ) @@a4@@ | ( unsigned __int8 ) @@a3@@ ) & Number ) != Number ) return Number L ; if ( ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ! isar_feature_aa32_fpshvec ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@v10@@ || * ( _DWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; if ( @@v10@@ > Number ) { if ( vfp_dreg_is_scalar ( @@a3@@ ) ) { @@v10@@ = Number ; } else { @@v9@@ = ( * ( int * ) ( @@a1@@ + Number ) >> Number ) + Number ; if ( vfp_dreg_is_scalar ( @@a4@@ ) ) @@v8@@ = Number ; else @@v8@@ = @@v9@@ ; } } @@v11@@ = tcg_temp_new_i64 ( ) ; @@v12@@ = tcg_temp_new_i64 ( ) ; neon_load_reg64 ( @@v11@@ , @@a4@@ ) ; while ( Number ) { @@a2@@ ( @@v12@@ , @@v11@@ ) ; neon_store_reg64 ( @@v12@@ , @@a3@@ ) ; if ( ! @@v10@@ ) break ; if ( ! @@v8@@ ) { while ( @@v10@@ -- ) { @@a3@@ = vfp_advance_dreg ( @@a3@@ , @@v9@@ ) ; neon_store_reg64 ( @@v12@@ , @@a3@@ ) ; } break ; } -- @@v10@@ ; vfp_advance_dreg ( @@a3@@ , @@v9@@ ) ; @@a3@@ = vfp_advance_dreg ( @@a4@@ , @@v8@@ ) ; neon_load_reg64 ( @@v11@@ , @@a4@@ ) ; } tcg_temp_free_i64 ( @@v11@@ ) ; tcg_temp_free_i64 ( @@v12@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64)\"}, \"location\": \"r64\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s44\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s48\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s52\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_VSQRT_sp", "code": "unsigned __int64 __fastcall gen_VSQRT_sp ( __int64 @@a1@@ , __int64 @@a2@@ ) { return gen_helper_vfp_sqrts ( @@a1@@ , @@a2@@ , cpu_env ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "vd", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "vm", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 833 |
[
"{\"name\": \"gen_helper_vfp_sqrts\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_sqrts ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_sqrts , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_VSQRT_sp", "code": "__int64 __fastcall trans_VSQRT_sp ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { return do_vfp_2op_sp ( @@a1@@ , ( void ( __fastcall * ) ( __int64 , __int64 ) ) gen_VSQRT_sp , * @@a2@@ , @@a2@@ [ Number ] ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VSQRT_sp"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 834 |
[
"{\"name\": \"do_vfp_2op_sp\", \"code\": \"__int64 __fastcall do_vfp_2op_sp ( __int64 @@a1@@ , void ( __fastcall * @@a2@@ ) ( __int64 , __int64 ) , unsigned int @@a3@@ , unsigned int @@a4@@ ) { int @@v8@@ ; int @@v9@@ ; int @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; @@v8@@ = Number ; LOBYTE ( @@v9@@ ) = Number ; @@v10@@ = * ( _DWORD * ) ( @@a1@@ + Number ) ; if ( ! isar_feature_aa32_fpshvec ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@v10@@ || * ( _DWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; if ( @@v10@@ > Number ) { if ( vfp_sreg_is_scalar ( @@a3@@ ) ) { @@v10@@ = Number ; } else { @@v9@@ = * ( _DWORD * ) ( @@a1@@ + Number ) + Number ; if ( vfp_sreg_is_scalar ( @@a4@@ ) ) @@v8@@ = Number ; else @@v8@@ = @@v9@@ ; } } @@v11@@ = tcg_temp_new_i32 ( ) ; @@v12@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v11@@ , @@a4@@ ) ; while ( Number ) { @@a2@@ ( @@v12@@ , @@v11@@ ) ; neon_store_reg32 ( @@v12@@ , @@a3@@ ) ; if ( ! @@v10@@ ) break ; if ( ! @@v8@@ ) { while ( @@v10@@ -- ) { @@a3@@ = vfp_advance_sreg ( @@a3@@ , @@v9@@ ) ; neon_store_reg32 ( @@v12@@ , @@a3@@ ) ; } break ; } -- @@v10@@ ; @@a3@@ = vfp_advance_sreg ( @@a3@@ , @@v9@@ ) ; @@a4@@ = vfp_advance_sreg ( @@a4@@ , @@v8@@ ) ; neon_load_reg32 ( @@v11@@ , @@a4@@ ) ; } tcg_temp_free_i32 ( @@v11@@ ) ; tcg_temp_free_i32 ( @@v12@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64)\"}, \"location\": \"r64\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s28\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s32\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s36\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_VSQRT_sp\", \"code\": \"unsigned __int64 __fastcall gen_VSQRT_sp ( __int64 @@a1@@ , __int64 @@a2@@ ) { return gen_helper_vfp_sqrts ( @@a1@@ , @@a2@@ , cpu_env ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "gen_VSQRT_dp", "code": "unsigned __int64 __fastcall gen_VSQRT_dp ( __int64 @@a1@@ , __int64 @@a2@@ ) { return gen_helper_vfp_sqrtd ( @@a1@@ , @@a2@@ , cpu_env ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "vd", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r56"}, {"n": "vm", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 835 |
[
"{\"name\": \"gen_helper_vfp_sqrtd\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_sqrtd ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_sqrtd , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_VSQRT_dp", "code": "__int64 __fastcall trans_VSQRT_dp ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { return do_vfp_2op_dp ( @@a1@@ , ( void ( __fastcall * ) ( __int64 , __int64 ) ) gen_VSQRT_dp , * @@a2@@ , @@a2@@ [ Number ] ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VSQRT_dp"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 836 |
[
"{\"name\": \"do_vfp_2op_dp\", \"code\": \"__int64 __fastcall do_vfp_2op_dp ( __int64 @@a1@@ , void ( __fastcall * @@a2@@ ) ( __int64 , __int64 ) , unsigned int @@a3@@ , unsigned int @@a4@@ ) { int @@v8@@ ; int @@v9@@ ; int @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; @@v8@@ = Number ; LOBYTE ( @@v9@@ ) = Number ; @@v10@@ = * ( _DWORD * ) ( @@a1@@ + Number ) ; if ( ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( ( ( unsigned __int8 ) @@a4@@ | ( unsigned __int8 ) @@a3@@ ) & Number ) != Number ) return Number L ; if ( ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ! isar_feature_aa32_fpshvec ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@v10@@ || * ( _DWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; if ( @@v10@@ > Number ) { if ( vfp_dreg_is_scalar ( @@a3@@ ) ) { @@v10@@ = Number ; } else { @@v9@@ = ( * ( int * ) ( @@a1@@ + Number ) >> Number ) + Number ; if ( vfp_dreg_is_scalar ( @@a4@@ ) ) @@v8@@ = Number ; else @@v8@@ = @@v9@@ ; } } @@v11@@ = tcg_temp_new_i64 ( ) ; @@v12@@ = tcg_temp_new_i64 ( ) ; neon_load_reg64 ( @@v11@@ , @@a4@@ ) ; while ( Number ) { @@a2@@ ( @@v12@@ , @@v11@@ ) ; neon_store_reg64 ( @@v12@@ , @@a3@@ ) ; if ( ! @@v10@@ ) break ; if ( ! @@v8@@ ) { while ( @@v10@@ -- ) { @@a3@@ = vfp_advance_dreg ( @@a3@@ , @@v9@@ ) ; neon_store_reg64 ( @@v12@@ , @@a3@@ ) ; } break ; } -- @@v10@@ ; vfp_advance_dreg ( @@a3@@ , @@v9@@ ) ; @@a3@@ = vfp_advance_dreg ( @@a4@@ , @@v8@@ ) ; neon_load_reg64 ( @@v11@@ , @@a4@@ ) ; } tcg_temp_free_i64 ( @@v11@@ ) ; tcg_temp_free_i64 ( @@v12@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 9, \"n\": \"void (__fastcall *)(__int64, __int64)\"}, \"location\": \"r64\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s44\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s48\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s52\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_VSQRT_dp\", \"code\": \"unsigned __int64 __fastcall gen_VSQRT_dp ( __int64 @@a1@@ , __int64 @@a2@@ ) { return gen_helper_vfp_sqrtd ( @@a1@@ , @@a2@@ , cpu_env ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "trans_VCMP_sp", "code": "__int64 __fastcall trans_VCMP_sp ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; if ( @@a2@@ [ Number ] && @@a2@@ [ Number ] ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; @@v3@@ = tcg_temp_new_i32 ( ) ; @@v4@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v3@@ , @@a2@@ [ Number ] ) ; if ( @@a2@@ [ Number ] ) tcg_gen_movi_i32 ( @@v4@@ , Number ) ; else neon_load_reg32 ( @@v4@@ , @@a2@@ [ Number ] ) ; if ( * @@a2@@ ) gen_helper_vfp_cmpes ( @@v3@@ , @@v4@@ , cpu_env ) ; else gen_helper_vfp_cmps ( @@v3@@ , @@v4@@ , cpu_env ) ; tcg_temp_free_i32 ( @@v3@@ ) ; tcg_temp_free_i32 ( @@v4@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VCMP_sp"}, "location": "r64"}, {"n": "vd", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "vm", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 837 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_cmps\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_cmps ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ [ Number ] ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ [ Number ] = tcgv_i32_temp ( @@a1@@ ) ; @@v5@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v5@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; tcg_gen_callN ( & helper_vfp_cmps , Number L , Number L , @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_cmpes\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_cmpes ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ [ Number ] ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ [ Number ] = tcgv_i32_temp ( @@a1@@ ) ; @@v5@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v5@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; tcg_gen_callN ( & helper_vfp_cmpes , Number L , Number L , @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_movi_i32\", \"code\": \"__int64 __fastcall tcg_gen_movi_i32 ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_op2i_i32 ( Number , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_load_reg\", \"code\": \"__int64 __fastcall neon_load_reg ( int @@a1@@ , int @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v2@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_ld_i32 ( @@v4@@ , cpu_env , @@v2@@ ) ; return @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_load_reg32\", \"code\": \"__int64 __fastcall neon_load_reg32 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_ld_i32 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"vfp_access_check\", \"code\": \"__int64 __fastcall vfp_access_check ( __int64 @@a1@@ ) { return full_vfp_access_check ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}"
] |
{"name": "trans_VCMP_dp", "code": "__int64 __fastcall trans_VCMP_dp ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; if ( @@a2@@ [ Number ] && @@a2@@ [ Number ] ) return Number L ; if ( ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( ( ( unsigned __int8 ) @@a2@@ [ Number ] | ( unsigned __int8 ) @@a2@@ [ Number ] ) & Number ) != Number ) { return Number L ; } if ( ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; @@v3@@ = tcg_temp_new_i64 ( ) ; @@v4@@ = tcg_temp_new_i64 ( ) ; neon_load_reg64 ( @@v3@@ , @@a2@@ [ Number ] ) ; if ( @@a2@@ [ Number ] ) tcg_gen_movi_i64 ( @@v4@@ , Number L ) ; else neon_load_reg64 ( @@v4@@ , @@a2@@ [ Number ] ) ; if ( * @@a2@@ ) gen_helper_vfp_cmped ( @@v3@@ , @@v4@@ , cpu_env ) ; else gen_helper_vfp_cmpd ( @@v3@@ , @@v4@@ , cpu_env ) ; tcg_temp_free_i64 ( @@v3@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VCMP_dp"}, "location": "r64"}, {"n": "vd", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s16"}, {"n": "vm", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 838 |
[
"{\"name\": \"isar_feature_aa32_fp_d32\", \"code\": \"bool __fastcall isar_feature_aa32_fp_d32 ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) > Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_fpdp\", \"code\": \"bool __fastcall isar_feature_aa32_fpdp ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"tcg_temp_free_i64\", \"code\": \"__int64 __fastcall tcg_temp_free_i64 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i64_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i64\", \"code\": \"__int64 tcg_temp_new_i64 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i64 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_cmpd\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_cmpd ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ [ Number ] ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ [ Number ] = tcgv_i64_temp ( @@a1@@ ) ; @@v5@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v5@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; tcg_gen_callN ( & helper_vfp_cmpd , Number L , Number L , @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_cmped\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_cmped ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ [ Number ] ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ [ Number ] = tcgv_i64_temp ( @@a1@@ ) ; @@v5@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v5@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; tcg_gen_callN ( & helper_vfp_cmped , Number L , Number L , @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_movi_i64\", \"code\": \"__int64 __fastcall tcg_gen_movi_i64 ( __int64 @@a1@@ , __int64 @@a2@@ ) { return tcg_gen_op2i_i64 ( Number , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_load_reg\", \"code\": \"__int64 __fastcall neon_load_reg ( int @@a1@@ , int @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v2@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_ld_i32 ( @@v4@@ , cpu_env , @@v2@@ ) ; return @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_load_reg64\", \"code\": \"__int64 __fastcall neon_load_reg64 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"vfp_access_check\", \"code\": \"__int64 __fastcall vfp_access_check ( __int64 @@a1@@ ) { return full_vfp_access_check ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}"
] |
{"name": "trans_VCVT_f32_f16", "code": "__int64 __fastcall trans_VCVT_f32_f16 ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; __int64 @@v5@@ ; __int64 @@v6@@ ; if ( ! isar_feature_aa32_fp16_spconv ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) == Number ) { @@v4@@ = get_fpstatus_ptr ( Number ) ; @@v5@@ = get_ahp_flag ( ) ; @@v6@@ = tcg_temp_new_i32 ( ) ; @@v3@@ = vfp_f16_offset ( @@a2@@ [ Number ] , * @@a2@@ != Number ) ; tcg_gen_ld16u_i32 ( @@v6@@ , cpu_env , @@v3@@ ) ; gen_helper_vfp_fcvt_f16_to_f32 ( @@v6@@ , @@v6@@ , @@v4@@ , @@v5@@ ) ; neon_store_reg32 ( @@v6@@ , @@a2@@ [ Number ] ) ; tcg_temp_free_i32 ( @@v5@@ ) ; tcg_temp_free_ptr ( @@v4@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; } return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VCVT_f32_f16"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}, {"n": "ahp_mode", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "fpst", "t": {"T": 3, "t": "TCGv_ptr_d"}, "location": "s24"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 839 |
[
"{\"name\": \"isar_feature_aa32_fp16_spconv\", \"code\": \"bool __fastcall isar_feature_aa32_fp16_spconv ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_ptr\", \"code\": \"__int64 __fastcall tcg_temp_free_ptr ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_ptr_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_fcvt_f16_to_f32\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_fcvt_f16_to_f32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_fcvt_f16_to_f32 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_ld16u_i32\", \"code\": \"__int64 __fastcall tcg_gen_ld16u_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"get_ahp_flag\", \"code\": \"__int64 get_ahp_flag ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_i32 ( ) ; tcg_gen_ld_i32 ( @@v1@@ , cpu_env , Number L ) ; tcg_gen_extract_i32 ( @@v1@@ , @@v1@@ , Number L , Number L ) ; return @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"get_fpstatus_ptr\", \"code\": \"__int64 __fastcall get_fpstatus_ptr ( int @@a1@@ ) { int @@v2@@ ; __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_ptr ( ) ; if ( @@a1@@ ) @@v2@@ = Number ; else @@v2@@ = Number ; tcg_gen_addi_ptr ( @@v3@@ , cpu_env , @@v2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_store_reg\", \"code\": \"__int64 __fastcall neon_store_reg ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; @@v3@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_st_i32 ( @@a3@@ , cpu_env , @@v3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_store_reg32\", \"code\": \"__int64 __fastcall neon_store_reg32 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_st_i32 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"vfp_f16_offset\", \"code\": \"__int64 __fastcall vfp_f16_offset ( unsigned int @@a1@@ , char @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = vfp_reg_offset ( Number , @@a1@@ ) ; if ( @@a2@@ ) @@v3@@ += Number L ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"vfp_access_check\", \"code\": \"__int64 __fastcall vfp_access_check ( __int64 @@a1@@ ) { return full_vfp_access_check ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"trans_VCVT\", \"code\": \"__int64 __fastcall trans_VCVT ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { unsigned int @@v3@@ ; bool @@v4@@ ; bool @@v5@@ ; unsigned int @@v6@@ ; unsigned int @@v7@@ ; unsigned int @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; __int64 @@v13@@ ; __int64 @@v14@@ ; __int64 @@v15@@ ; __int64 @@v16@@ ; @@v4@@ = * @@a2@@ != Number ; @@v6@@ = fp_decode_rm [ @@a2@@ [ Number ] ] ; @@v5@@ = @@a2@@ [ Number ] != Number ; if ( ! isar_feature_aa32_vcvt_dr ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v4@@ && ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@a2@@ [ Number ] & Number ) != Number ) return Number L ; if ( @@v4@@ && ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v7@@ = @@a2@@ [ Number ] ; @@v8@@ = @@a2@@ [ Number ] ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; @@v9@@ = get_fpstatus_ptr ( Number ) ; @@v10@@ = tcg_const_i32 ( Number L ) ; @@v3@@ = arm_rmode_to_sf ( @@v6@@ ) ; @@v11@@ = tcg_const_i32 ( @@v3@@ ) ; gen_helper_set_rmode ( @@v11@@ , @@v11@@ , @@v9@@ ) ; if ( @@v4@@ ) { @@v14@@ = tcg_temp_new_i64 ( ) ; @@v15@@ = tcg_temp_new_i64 ( ) ; @@v16@@ = tcg_temp_new_i32 ( ) ; neon_load_reg64 ( @@v14@@ , @@v8@@ ) ; if ( @@v5@@ ) gen_helper_vfp_tosld ( @@v15@@ , @@v14@@ , @@v10@@ , @@v9@@ ) ; else gen_helper_vfp_tould ( @@v15@@ , @@v14@@ , @@v10@@ , @@v9@@ ) ; tcg_gen_extrl_i64_i32 ( @@v16@@ , @@v15@@ ) ; neon_store_reg32 ( @@v16@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v16@@ ) ; tcg_temp_free_i64 ( @@v15@@ ) ; tcg_temp_free_i64 ( @@v14@@ ) ; } else { @@v12@@ = tcg_temp_new_i32 ( ) ; @@v13@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v12@@ , @@v8@@ ) ; if ( @@v5@@ ) gen_helper_vfp_tosls ( @@v13@@ , @@v12@@ , @@v10@@ , @@v9@@ ) ; else gen_helper_vfp_touls ( @@v13@@ , @@v12@@ , @@v10@@ , @@v9@@ ) ; neon_store_reg32 ( @@v13@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v13@@ ) ; tcg_temp_free_i32 ( @@v12@@ ) ; } gen_helper_set_rmode ( @@v11@@ , @@v11@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_ptr ( @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s100\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s101\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s102\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s40\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s48\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s56\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s64\"}, {\"n\": \"v16\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s92\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s96\"}]}"
] |
{"name": "trans_VCVT_f64_f16", "code": "__int64 __fastcall trans_VCVT_f64_f16 ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( ! isar_feature_aa32_fp16_dpconv ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@a2@@ [ Number ] & Number ) != Number ) return Number L ; if ( ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) == Number ) { @@v4@@ = get_fpstatus_ptr ( Number ) ; @@v5@@ = get_ahp_flag ( ) ; @@v6@@ = tcg_temp_new_i32 ( ) ; @@v3@@ = vfp_f16_offset ( @@a2@@ [ Number ] , * @@a2@@ != Number ) ; tcg_gen_ld16u_i32 ( @@v6@@ , cpu_env , @@v3@@ ) ; @@v7@@ = tcg_temp_new_i64 ( ) ; gen_helper_vfp_fcvt_f16_to_f64 ( @@v7@@ , @@v6@@ , @@v4@@ , @@v5@@ ) ; neon_store_reg64 ( @@v7@@ , @@a2@@ [ Number ] ) ; tcg_temp_free_i32 ( @@v5@@ ) ; tcg_temp_free_ptr ( @@v4@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; tcg_temp_free_i64 ( @@v7@@ ) ; } return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s32"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VCVT_f64_f16"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "ahp_mode", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s24"}, {"n": "fpst", "t": {"T": 3, "t": "TCGv_ptr_d"}, "location": "s32"}, {"n": "vd", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 840 |
[
"{\"name\": \"isar_feature_aa32_fp_d32\", \"code\": \"bool __fastcall isar_feature_aa32_fp_d32 ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) > Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_fpdp\", \"code\": \"bool __fastcall isar_feature_aa32_fpdp ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_fp16_dpconv\", \"code\": \"bool __fastcall isar_feature_aa32_fp16_dpconv ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) > Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_i64\", \"code\": \"__int64 __fastcall tcg_temp_free_i64 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i64_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_ptr\", \"code\": \"__int64 __fastcall tcg_temp_free_ptr ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_ptr_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_temp_new_i64\", \"code\": \"__int64 tcg_temp_new_i64 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i64 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_fcvt_f16_to_f64\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_fcvt_f16_to_f64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_fcvt_f16_to_f64 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_ld16u_i32\", \"code\": \"__int64 __fastcall tcg_gen_ld16u_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"get_ahp_flag\", \"code\": \"__int64 get_ahp_flag ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_i32 ( ) ; tcg_gen_ld_i32 ( @@v1@@ , cpu_env , Number L ) ; tcg_gen_extract_i32 ( @@v1@@ , @@v1@@ , Number L , Number L ) ; return @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"get_fpstatus_ptr\", \"code\": \"__int64 __fastcall get_fpstatus_ptr ( int @@a1@@ ) { int @@v2@@ ; __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_ptr ( ) ; if ( @@a1@@ ) @@v2@@ = Number ; else @@v2@@ = Number ; tcg_gen_addi_ptr ( @@v3@@ , cpu_env , @@v2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_store_reg\", \"code\": \"__int64 __fastcall neon_store_reg ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; @@v3@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_st_i32 ( @@a3@@ , cpu_env , @@v3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_store_reg64\", \"code\": \"__int64 __fastcall neon_store_reg64 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_st_i64 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"vfp_f16_offset\", \"code\": \"__int64 __fastcall vfp_f16_offset ( unsigned int @@a1@@ , char @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = vfp_reg_offset ( Number , @@a1@@ ) ; if ( @@a2@@ ) @@v3@@ += Number L ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"vfp_access_check\", \"code\": \"__int64 __fastcall vfp_access_check ( __int64 @@a1@@ ) { return full_vfp_access_check ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"trans_VCVT\", \"code\": \"__int64 __fastcall trans_VCVT ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { unsigned int @@v3@@ ; bool @@v4@@ ; bool @@v5@@ ; unsigned int @@v6@@ ; unsigned int @@v7@@ ; unsigned int @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; __int64 @@v13@@ ; __int64 @@v14@@ ; __int64 @@v15@@ ; __int64 @@v16@@ ; @@v4@@ = * @@a2@@ != Number ; @@v6@@ = fp_decode_rm [ @@a2@@ [ Number ] ] ; @@v5@@ = @@a2@@ [ Number ] != Number ; if ( ! isar_feature_aa32_vcvt_dr ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v4@@ && ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@a2@@ [ Number ] & Number ) != Number ) return Number L ; if ( @@v4@@ && ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v7@@ = @@a2@@ [ Number ] ; @@v8@@ = @@a2@@ [ Number ] ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; @@v9@@ = get_fpstatus_ptr ( Number ) ; @@v10@@ = tcg_const_i32 ( Number L ) ; @@v3@@ = arm_rmode_to_sf ( @@v6@@ ) ; @@v11@@ = tcg_const_i32 ( @@v3@@ ) ; gen_helper_set_rmode ( @@v11@@ , @@v11@@ , @@v9@@ ) ; if ( @@v4@@ ) { @@v14@@ = tcg_temp_new_i64 ( ) ; @@v15@@ = tcg_temp_new_i64 ( ) ; @@v16@@ = tcg_temp_new_i32 ( ) ; neon_load_reg64 ( @@v14@@ , @@v8@@ ) ; if ( @@v5@@ ) gen_helper_vfp_tosld ( @@v15@@ , @@v14@@ , @@v10@@ , @@v9@@ ) ; else gen_helper_vfp_tould ( @@v15@@ , @@v14@@ , @@v10@@ , @@v9@@ ) ; tcg_gen_extrl_i64_i32 ( @@v16@@ , @@v15@@ ) ; neon_store_reg32 ( @@v16@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v16@@ ) ; tcg_temp_free_i64 ( @@v15@@ ) ; tcg_temp_free_i64 ( @@v14@@ ) ; } else { @@v12@@ = tcg_temp_new_i32 ( ) ; @@v13@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v12@@ , @@v8@@ ) ; if ( @@v5@@ ) gen_helper_vfp_tosls ( @@v13@@ , @@v12@@ , @@v10@@ , @@v9@@ ) ; else gen_helper_vfp_touls ( @@v13@@ , @@v12@@ , @@v10@@ , @@v9@@ ) ; neon_store_reg32 ( @@v13@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v13@@ ) ; tcg_temp_free_i32 ( @@v12@@ ) ; } gen_helper_set_rmode ( @@v11@@ , @@v11@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_ptr ( @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s100\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s101\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s102\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s40\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s48\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s56\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s64\"}, {\"n\": \"v16\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s92\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s96\"}]}"
] |
{"name": "trans_VCVT_f16_f32", "code": "__int64 __fastcall trans_VCVT_f16_f32 ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; __int64 @@v5@@ ; __int64 @@v6@@ ; if ( ! isar_feature_aa32_fp16_spconv ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) == Number ) { @@v4@@ = get_fpstatus_ptr ( Number ) ; @@v5@@ = get_ahp_flag ( ) ; @@v6@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v6@@ , @@a2@@ [ Number ] ) ; gen_helper_vfp_fcvt_f32_to_f16 ( @@v6@@ , @@v6@@ , @@v4@@ , @@v5@@ ) ; @@v3@@ = vfp_f16_offset ( @@a2@@ [ Number ] , * @@a2@@ != Number ) ; tcg_gen_st16_i32 ( @@v6@@ , cpu_env , @@v3@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; tcg_temp_free_ptr ( @@v4@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; } return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VCVT_f16_f32"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}, {"n": "ahp_mode", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "fpst", "t": {"T": 3, "t": "TCGv_ptr_d"}, "location": "s24"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 841 |
[
"{\"name\": \"isar_feature_aa32_fp16_spconv\", \"code\": \"bool __fastcall isar_feature_aa32_fp16_spconv ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_ptr\", \"code\": \"__int64 __fastcall tcg_temp_free_ptr ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_ptr_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_fcvt_f32_to_f16\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_fcvt_f32_to_f16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_fcvt_f32_to_f16 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_st16_i32\", \"code\": \"__int64 __fastcall tcg_gen_st16_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"get_ahp_flag\", \"code\": \"__int64 get_ahp_flag ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_i32 ( ) ; tcg_gen_ld_i32 ( @@v1@@ , cpu_env , Number L ) ; tcg_gen_extract_i32 ( @@v1@@ , @@v1@@ , Number L , Number L ) ; return @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"get_fpstatus_ptr\", \"code\": \"__int64 __fastcall get_fpstatus_ptr ( int @@a1@@ ) { int @@v2@@ ; __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_ptr ( ) ; if ( @@a1@@ ) @@v2@@ = Number ; else @@v2@@ = Number ; tcg_gen_addi_ptr ( @@v3@@ , cpu_env , @@v2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_load_reg\", \"code\": \"__int64 __fastcall neon_load_reg ( int @@a1@@ , int @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v2@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_ld_i32 ( @@v4@@ , cpu_env , @@v2@@ ) ; return @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_load_reg32\", \"code\": \"__int64 __fastcall neon_load_reg32 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_ld_i32 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"vfp_f16_offset\", \"code\": \"__int64 __fastcall vfp_f16_offset ( unsigned int @@a1@@ , char @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = vfp_reg_offset ( Number , @@a1@@ ) ; if ( @@a2@@ ) @@v3@@ += Number L ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"vfp_access_check\", \"code\": \"__int64 __fastcall vfp_access_check ( __int64 @@a1@@ ) { return full_vfp_access_check ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"trans_VCVT\", \"code\": \"__int64 __fastcall trans_VCVT ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { unsigned int @@v3@@ ; bool @@v4@@ ; bool @@v5@@ ; unsigned int @@v6@@ ; unsigned int @@v7@@ ; unsigned int @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; __int64 @@v13@@ ; __int64 @@v14@@ ; __int64 @@v15@@ ; __int64 @@v16@@ ; @@v4@@ = * @@a2@@ != Number ; @@v6@@ = fp_decode_rm [ @@a2@@ [ Number ] ] ; @@v5@@ = @@a2@@ [ Number ] != Number ; if ( ! isar_feature_aa32_vcvt_dr ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v4@@ && ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@a2@@ [ Number ] & Number ) != Number ) return Number L ; if ( @@v4@@ && ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v7@@ = @@a2@@ [ Number ] ; @@v8@@ = @@a2@@ [ Number ] ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; @@v9@@ = get_fpstatus_ptr ( Number ) ; @@v10@@ = tcg_const_i32 ( Number L ) ; @@v3@@ = arm_rmode_to_sf ( @@v6@@ ) ; @@v11@@ = tcg_const_i32 ( @@v3@@ ) ; gen_helper_set_rmode ( @@v11@@ , @@v11@@ , @@v9@@ ) ; if ( @@v4@@ ) { @@v14@@ = tcg_temp_new_i64 ( ) ; @@v15@@ = tcg_temp_new_i64 ( ) ; @@v16@@ = tcg_temp_new_i32 ( ) ; neon_load_reg64 ( @@v14@@ , @@v8@@ ) ; if ( @@v5@@ ) gen_helper_vfp_tosld ( @@v15@@ , @@v14@@ , @@v10@@ , @@v9@@ ) ; else gen_helper_vfp_tould ( @@v15@@ , @@v14@@ , @@v10@@ , @@v9@@ ) ; tcg_gen_extrl_i64_i32 ( @@v16@@ , @@v15@@ ) ; neon_store_reg32 ( @@v16@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v16@@ ) ; tcg_temp_free_i64 ( @@v15@@ ) ; tcg_temp_free_i64 ( @@v14@@ ) ; } else { @@v12@@ = tcg_temp_new_i32 ( ) ; @@v13@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v12@@ , @@v8@@ ) ; if ( @@v5@@ ) gen_helper_vfp_tosls ( @@v13@@ , @@v12@@ , @@v10@@ , @@v9@@ ) ; else gen_helper_vfp_touls ( @@v13@@ , @@v12@@ , @@v10@@ , @@v9@@ ) ; neon_store_reg32 ( @@v13@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v13@@ ) ; tcg_temp_free_i32 ( @@v12@@ ) ; } gen_helper_set_rmode ( @@v11@@ , @@v11@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_ptr ( @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s100\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s101\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s102\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s40\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s48\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s56\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s64\"}, {\"n\": \"v16\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s92\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s96\"}]}"
] |
{"name": "trans_VCVT_f16_f64", "code": "__int64 __fastcall trans_VCVT_f16_f64 ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( ! isar_feature_aa32_fp16_dpconv ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@a2@@ [ Number ] & Number ) != Number ) return Number L ; if ( ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) == Number ) { @@v4@@ = get_fpstatus_ptr ( Number ) ; @@v5@@ = get_ahp_flag ( ) ; @@v6@@ = tcg_temp_new_i32 ( ) ; @@v7@@ = tcg_temp_new_i64 ( ) ; neon_load_reg64 ( @@v7@@ , @@a2@@ [ Number ] ) ; gen_helper_vfp_fcvt_f64_to_f16 ( @@v6@@ , @@v7@@ , @@v4@@ , @@v5@@ ) ; tcg_temp_free_i64 ( @@v7@@ ) ; @@v3@@ = vfp_f16_offset ( @@a2@@ [ Number ] , * @@a2@@ != Number ) ; tcg_gen_st16_i32 ( @@v6@@ , cpu_env , @@v3@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; tcg_temp_free_ptr ( @@v4@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; } return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s32"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VCVT_f16_f64"}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "ahp_mode", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s24"}, {"n": "fpst", "t": {"T": 3, "t": "TCGv_ptr_d"}, "location": "s32"}, {"n": "vm", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 842 |
[
"{\"name\": \"isar_feature_aa32_fp_d32\", \"code\": \"bool __fastcall isar_feature_aa32_fp_d32 ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) > Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_fpdp\", \"code\": \"bool __fastcall isar_feature_aa32_fpdp ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_fp16_dpconv\", \"code\": \"bool __fastcall isar_feature_aa32_fp16_dpconv ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) > Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_i64\", \"code\": \"__int64 __fastcall tcg_temp_free_i64 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i64_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_ptr\", \"code\": \"__int64 __fastcall tcg_temp_free_ptr ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_ptr_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_temp_new_i64\", \"code\": \"__int64 tcg_temp_new_i64 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i64 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_fcvt_f64_to_f16\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_fcvt_f64_to_f16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_fcvt_f64_to_f16 , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_st16_i32\", \"code\": \"__int64 __fastcall tcg_gen_st16_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"get_ahp_flag\", \"code\": \"__int64 get_ahp_flag ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_i32 ( ) ; tcg_gen_ld_i32 ( @@v1@@ , cpu_env , Number L ) ; tcg_gen_extract_i32 ( @@v1@@ , @@v1@@ , Number L , Number L ) ; return @@v1@@ ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"get_fpstatus_ptr\", \"code\": \"__int64 __fastcall get_fpstatus_ptr ( int @@a1@@ ) { int @@v2@@ ; __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_ptr ( ) ; if ( @@a1@@ ) @@v2@@ = Number ; else @@v2@@ = Number ; tcg_gen_addi_ptr ( @@v3@@ , cpu_env , @@v2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_load_reg\", \"code\": \"__int64 __fastcall neon_load_reg ( int @@a1@@ , int @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v2@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_ld_i32 ( @@v4@@ , cpu_env , @@v2@@ ) ; return @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_load_reg64\", \"code\": \"__int64 __fastcall neon_load_reg64 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"vfp_f16_offset\", \"code\": \"__int64 __fastcall vfp_f16_offset ( unsigned int @@a1@@ , char @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = vfp_reg_offset ( Number , @@a1@@ ) ; if ( @@a2@@ ) @@v3@@ += Number L ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"vfp_access_check\", \"code\": \"__int64 __fastcall vfp_access_check ( __int64 @@a1@@ ) { return full_vfp_access_check ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"trans_VCVT\", \"code\": \"__int64 __fastcall trans_VCVT ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { unsigned int @@v3@@ ; bool @@v4@@ ; bool @@v5@@ ; unsigned int @@v6@@ ; unsigned int @@v7@@ ; unsigned int @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; __int64 @@v13@@ ; __int64 @@v14@@ ; __int64 @@v15@@ ; __int64 @@v16@@ ; @@v4@@ = * @@a2@@ != Number ; @@v6@@ = fp_decode_rm [ @@a2@@ [ Number ] ] ; @@v5@@ = @@a2@@ [ Number ] != Number ; if ( ! isar_feature_aa32_vcvt_dr ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v4@@ && ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@a2@@ [ Number ] & Number ) != Number ) return Number L ; if ( @@v4@@ && ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v7@@ = @@a2@@ [ Number ] ; @@v8@@ = @@a2@@ [ Number ] ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; @@v9@@ = get_fpstatus_ptr ( Number ) ; @@v10@@ = tcg_const_i32 ( Number L ) ; @@v3@@ = arm_rmode_to_sf ( @@v6@@ ) ; @@v11@@ = tcg_const_i32 ( @@v3@@ ) ; gen_helper_set_rmode ( @@v11@@ , @@v11@@ , @@v9@@ ) ; if ( @@v4@@ ) { @@v14@@ = tcg_temp_new_i64 ( ) ; @@v15@@ = tcg_temp_new_i64 ( ) ; @@v16@@ = tcg_temp_new_i32 ( ) ; neon_load_reg64 ( @@v14@@ , @@v8@@ ) ; if ( @@v5@@ ) gen_helper_vfp_tosld ( @@v15@@ , @@v14@@ , @@v10@@ , @@v9@@ ) ; else gen_helper_vfp_tould ( @@v15@@ , @@v14@@ , @@v10@@ , @@v9@@ ) ; tcg_gen_extrl_i64_i32 ( @@v16@@ , @@v15@@ ) ; neon_store_reg32 ( @@v16@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v16@@ ) ; tcg_temp_free_i64 ( @@v15@@ ) ; tcg_temp_free_i64 ( @@v14@@ ) ; } else { @@v12@@ = tcg_temp_new_i32 ( ) ; @@v13@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v12@@ , @@v8@@ ) ; if ( @@v5@@ ) gen_helper_vfp_tosls ( @@v13@@ , @@v12@@ , @@v10@@ , @@v9@@ ) ; else gen_helper_vfp_touls ( @@v13@@ , @@v12@@ , @@v10@@ , @@v9@@ ) ; neon_store_reg32 ( @@v13@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v13@@ ) ; tcg_temp_free_i32 ( @@v12@@ ) ; } gen_helper_set_rmode ( @@v11@@ , @@v11@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_ptr ( @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s100\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s101\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s102\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s40\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s48\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s56\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s64\"}, {\"n\": \"v16\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s92\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s96\"}]}"
] |
{"name": "trans_VRINTR_sp", "code": "__int64 __fastcall trans_VRINTR_sp ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; if ( ! isar_feature_aa32_vrint ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) == Number ) { @@v3@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v3@@ , @@a2@@ [ Number ] ) ; @@v4@@ = get_fpstatus_ptr ( Number ) ; gen_helper_rints ( @@v3@@ , @@v3@@ , @@v4@@ ) ; neon_store_reg32 ( @@v3@@ , * @@a2@@ ) ; tcg_temp_free_ptr ( @@v4@@ ) ; tcg_temp_free_i32 ( @@v3@@ ) ; } return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VRINTR_sp"}, "location": "r64"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "fpst", "t": {"T": 3, "t": "TCGv_ptr_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 843 |
[
"{\"name\": \"isar_feature_aa32_vrint\", \"code\": \"bool __fastcall isar_feature_aa32_vrint ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) > Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_ptr\", \"code\": \"__int64 __fastcall tcg_temp_free_ptr ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_ptr_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_rints\", \"code\": \"unsigned __int64 __fastcall gen_helper_rints ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_rints , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"get_fpstatus_ptr\", \"code\": \"__int64 __fastcall get_fpstatus_ptr ( int @@a1@@ ) { int @@v2@@ ; __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_ptr ( ) ; if ( @@a1@@ ) @@v2@@ = Number ; else @@v2@@ = Number ; tcg_gen_addi_ptr ( @@v3@@ , cpu_env , @@v2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_load_reg\", \"code\": \"__int64 __fastcall neon_load_reg ( int @@a1@@ , int @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v2@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_ld_i32 ( @@v4@@ , cpu_env , @@v2@@ ) ; return @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_store_reg\", \"code\": \"__int64 __fastcall neon_store_reg ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; @@v3@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_st_i32 ( @@a3@@ , cpu_env , @@v3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_load_reg32\", \"code\": \"__int64 __fastcall neon_load_reg32 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_ld_i32 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_store_reg32\", \"code\": \"__int64 __fastcall neon_store_reg32 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_st_i32 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"vfp_access_check\", \"code\": \"__int64 __fastcall vfp_access_check ( __int64 @@a1@@ ) { return full_vfp_access_check ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"trans_VRINT\", \"code\": \"__int64 __fastcall trans_VRINT ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { unsigned int @@v3@@ ; bool @@v4@@ ; unsigned int @@v5@@ ; unsigned int @@v6@@ ; unsigned int @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; __int64 @@v13@@ ; @@v4@@ = * @@a2@@ != Number ; @@v5@@ = fp_decode_rm [ @@a2@@ [ Number ] ] ; if ( ! isar_feature_aa32_vrint ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v4@@ && ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( ( ( unsigned __int8 ) @@a2@@ [ Number ] | ( unsigned __int8 ) @@a2@@ [ Number ] ) & Number ) != Number ) { return Number L ; } if ( @@v4@@ && ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v6@@ = @@a2@@ [ Number ] ; @@v7@@ = @@a2@@ [ Number ] ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; @@v8@@ = get_fpstatus_ptr ( Number ) ; @@v3@@ = arm_rmode_to_sf ( @@v5@@ ) ; @@v9@@ = tcg_const_i32 ( @@v3@@ ) ; gen_helper_set_rmode ( @@v9@@ , @@v9@@ , @@v8@@ ) ; if ( @@v4@@ ) { @@v12@@ = tcg_temp_new_i64 ( ) ; @@v13@@ = tcg_temp_new_i64 ( ) ; neon_load_reg64 ( @@v12@@ , @@v7@@ ) ; gen_helper_rintd ( @@v13@@ , @@v12@@ , @@v8@@ ) ; neon_store_reg64 ( @@v13@@ , @@v6@@ ) ; tcg_temp_free_i64 ( @@v12@@ ) ; tcg_temp_free_i64 ( @@v13@@ ) ; } else { @@v10@@ = tcg_temp_new_i32 ( ) ; @@v11@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v10@@ , @@v7@@ ) ; gen_helper_rints ( @@v11@@ , @@v10@@ , @@v8@@ ) ; neon_store_reg32 ( @@v11@@ , @@v6@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; } gen_helper_set_rmode ( @@v9@@ , @@v9@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_temp_free_ptr ( @@v8@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s40\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s48\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s76\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s80\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s84\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s85\"}]}"
] |
{"name": "trans_VRINTR_dp", "code": "__int64 __fastcall trans_VRINTR_dp ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; if ( ! isar_feature_aa32_vrint ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( ( ( unsigned __int8 ) * @@a2@@ | ( unsigned __int8 ) @@a2@@ [ Number ] ) & Number ) != Number ) return Number L ; if ( ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) == Number ) { @@v3@@ = tcg_temp_new_i64 ( ) ; neon_load_reg64 ( @@v3@@ , @@a2@@ [ Number ] ) ; @@v4@@ = get_fpstatus_ptr ( Number ) ; gen_helper_rintd ( @@v3@@ , @@v3@@ , @@v4@@ ) ; neon_store_reg64 ( @@v3@@ , * @@a2@@ ) ; tcg_temp_free_ptr ( @@v4@@ ) ; tcg_temp_free_i64 ( @@v3@@ ) ; } return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VRINTR_dp"}, "location": "r64"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s16"}, {"n": "fpst", "t": {"T": 3, "t": "TCGv_ptr_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 844 |
[
"{\"name\": \"isar_feature_aa32_fp_d32\", \"code\": \"bool __fastcall isar_feature_aa32_fp_d32 ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) > Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_fpdp\", \"code\": \"bool __fastcall isar_feature_aa32_fpdp ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_vrint\", \"code\": \"bool __fastcall isar_feature_aa32_vrint ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) > Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"tcg_temp_free_i64\", \"code\": \"__int64 __fastcall tcg_temp_free_i64 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i64_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_ptr\", \"code\": \"__int64 __fastcall tcg_temp_free_ptr ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_ptr_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i64\", \"code\": \"__int64 tcg_temp_new_i64 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i64 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_rintd\", \"code\": \"unsigned __int64 __fastcall gen_helper_rintd ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_rintd , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"get_fpstatus_ptr\", \"code\": \"__int64 __fastcall get_fpstatus_ptr ( int @@a1@@ ) { int @@v2@@ ; __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_ptr ( ) ; if ( @@a1@@ ) @@v2@@ = Number ; else @@v2@@ = Number ; tcg_gen_addi_ptr ( @@v3@@ , cpu_env , @@v2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_load_reg\", \"code\": \"__int64 __fastcall neon_load_reg ( int @@a1@@ , int @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v2@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_ld_i32 ( @@v4@@ , cpu_env , @@v2@@ ) ; return @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_store_reg\", \"code\": \"__int64 __fastcall neon_store_reg ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; @@v3@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_st_i32 ( @@a3@@ , cpu_env , @@v3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_load_reg64\", \"code\": \"__int64 __fastcall neon_load_reg64 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_store_reg64\", \"code\": \"__int64 __fastcall neon_store_reg64 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_st_i64 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"vfp_access_check\", \"code\": \"__int64 __fastcall vfp_access_check ( __int64 @@a1@@ ) { return full_vfp_access_check ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"trans_VRINT\", \"code\": \"__int64 __fastcall trans_VRINT ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { unsigned int @@v3@@ ; bool @@v4@@ ; unsigned int @@v5@@ ; unsigned int @@v6@@ ; unsigned int @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; __int64 @@v13@@ ; @@v4@@ = * @@a2@@ != Number ; @@v5@@ = fp_decode_rm [ @@a2@@ [ Number ] ] ; if ( ! isar_feature_aa32_vrint ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v4@@ && ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( ( ( unsigned __int8 ) @@a2@@ [ Number ] | ( unsigned __int8 ) @@a2@@ [ Number ] ) & Number ) != Number ) { return Number L ; } if ( @@v4@@ && ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v6@@ = @@a2@@ [ Number ] ; @@v7@@ = @@a2@@ [ Number ] ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; @@v8@@ = get_fpstatus_ptr ( Number ) ; @@v3@@ = arm_rmode_to_sf ( @@v5@@ ) ; @@v9@@ = tcg_const_i32 ( @@v3@@ ) ; gen_helper_set_rmode ( @@v9@@ , @@v9@@ , @@v8@@ ) ; if ( @@v4@@ ) { @@v12@@ = tcg_temp_new_i64 ( ) ; @@v13@@ = tcg_temp_new_i64 ( ) ; neon_load_reg64 ( @@v12@@ , @@v7@@ ) ; gen_helper_rintd ( @@v13@@ , @@v12@@ , @@v8@@ ) ; neon_store_reg64 ( @@v13@@ , @@v6@@ ) ; tcg_temp_free_i64 ( @@v12@@ ) ; tcg_temp_free_i64 ( @@v13@@ ) ; } else { @@v10@@ = tcg_temp_new_i32 ( ) ; @@v11@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v10@@ , @@v7@@ ) ; gen_helper_rints ( @@v11@@ , @@v10@@ , @@v8@@ ) ; neon_store_reg32 ( @@v11@@ , @@v6@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; } gen_helper_set_rmode ( @@v9@@ , @@v9@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_temp_free_ptr ( @@v8@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s40\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s48\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s76\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s80\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s84\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s85\"}]}"
] |
{"name": "trans_VRINTZ_sp", "code": "__int64 __fastcall trans_VRINTZ_sp ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; __int64 @@v5@@ ; if ( ! isar_feature_aa32_vrint ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) == Number ) { @@v3@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v3@@ , @@a2@@ [ Number ] ) ; @@v4@@ = get_fpstatus_ptr ( Number ) ; @@v5@@ = tcg_const_i32 ( Number L ) ; gen_helper_set_rmode ( @@v5@@ , @@v5@@ , @@v4@@ ) ; gen_helper_rints ( @@v3@@ , @@v3@@ , @@v4@@ ) ; gen_helper_set_rmode ( @@v5@@ , @@v5@@ , @@v4@@ ) ; neon_store_reg32 ( @@v3@@ , * @@a2@@ ) ; tcg_temp_free_ptr ( @@v4@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; tcg_temp_free_i32 ( @@v3@@ ) ; } return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VRINTZ_sp"}, "location": "r64"}, {"n": "fpst", "t": {"T": 3, "t": "TCGv_ptr_d"}, "location": "s16"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s24"}, {"n": "tcg_rmode", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 845 |
[
"{\"name\": \"isar_feature_aa32_vrint\", \"code\": \"bool __fastcall isar_feature_aa32_vrint ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) > Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_ptr\", \"code\": \"__int64 __fastcall tcg_temp_free_ptr ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_ptr_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_set_rmode\", \"code\": \"unsigned __int64 __fastcall gen_helper_set_rmode ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_set_rmode , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_rints\", \"code\": \"unsigned __int64 __fastcall gen_helper_rints ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_rints , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"get_fpstatus_ptr\", \"code\": \"__int64 __fastcall get_fpstatus_ptr ( int @@a1@@ ) { int @@v2@@ ; __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_ptr ( ) ; if ( @@a1@@ ) @@v2@@ = Number ; else @@v2@@ = Number ; tcg_gen_addi_ptr ( @@v3@@ , cpu_env , @@v2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_load_reg\", \"code\": \"__int64 __fastcall neon_load_reg ( int @@a1@@ , int @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v2@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_ld_i32 ( @@v4@@ , cpu_env , @@v2@@ ) ; return @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_store_reg\", \"code\": \"__int64 __fastcall neon_store_reg ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; @@v3@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_st_i32 ( @@a3@@ , cpu_env , @@v3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_load_reg32\", \"code\": \"__int64 __fastcall neon_load_reg32 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_ld_i32 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_store_reg32\", \"code\": \"__int64 __fastcall neon_store_reg32 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_st_i32 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"vfp_access_check\", \"code\": \"__int64 __fastcall vfp_access_check ( __int64 @@a1@@ ) { return full_vfp_access_check ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"trans_VRINT\", \"code\": \"__int64 __fastcall trans_VRINT ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { unsigned int @@v3@@ ; bool @@v4@@ ; unsigned int @@v5@@ ; unsigned int @@v6@@ ; unsigned int @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; __int64 @@v13@@ ; @@v4@@ = * @@a2@@ != Number ; @@v5@@ = fp_decode_rm [ @@a2@@ [ Number ] ] ; if ( ! isar_feature_aa32_vrint ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v4@@ && ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( ( ( unsigned __int8 ) @@a2@@ [ Number ] | ( unsigned __int8 ) @@a2@@ [ Number ] ) & Number ) != Number ) { return Number L ; } if ( @@v4@@ && ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v6@@ = @@a2@@ [ Number ] ; @@v7@@ = @@a2@@ [ Number ] ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; @@v8@@ = get_fpstatus_ptr ( Number ) ; @@v3@@ = arm_rmode_to_sf ( @@v5@@ ) ; @@v9@@ = tcg_const_i32 ( @@v3@@ ) ; gen_helper_set_rmode ( @@v9@@ , @@v9@@ , @@v8@@ ) ; if ( @@v4@@ ) { @@v12@@ = tcg_temp_new_i64 ( ) ; @@v13@@ = tcg_temp_new_i64 ( ) ; neon_load_reg64 ( @@v12@@ , @@v7@@ ) ; gen_helper_rintd ( @@v13@@ , @@v12@@ , @@v8@@ ) ; neon_store_reg64 ( @@v13@@ , @@v6@@ ) ; tcg_temp_free_i64 ( @@v12@@ ) ; tcg_temp_free_i64 ( @@v13@@ ) ; } else { @@v10@@ = tcg_temp_new_i32 ( ) ; @@v11@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v10@@ , @@v7@@ ) ; gen_helper_rints ( @@v11@@ , @@v10@@ , @@v8@@ ) ; neon_store_reg32 ( @@v11@@ , @@v6@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; } gen_helper_set_rmode ( @@v9@@ , @@v9@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_temp_free_ptr ( @@v8@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s40\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s48\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s76\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s80\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s84\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s85\"}]}"
] |
{"name": "trans_VRINTZ_dp", "code": "__int64 __fastcall trans_VRINTZ_dp ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; __int64 @@v5@@ ; if ( ! isar_feature_aa32_vrint ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( ( ( unsigned __int8 ) * @@a2@@ | ( unsigned __int8 ) @@a2@@ [ Number ] ) & Number ) != Number ) return Number L ; if ( ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) == Number ) { @@v3@@ = tcg_temp_new_i64 ( ) ; neon_load_reg64 ( @@v3@@ , @@a2@@ [ Number ] ) ; @@v4@@ = get_fpstatus_ptr ( Number ) ; @@v5@@ = tcg_const_i32 ( Number L ) ; gen_helper_set_rmode ( @@v5@@ , @@v5@@ , @@v4@@ ) ; gen_helper_rintd ( @@v3@@ , @@v3@@ , @@v4@@ ) ; gen_helper_set_rmode ( @@v5@@ , @@v5@@ , @@v4@@ ) ; neon_store_reg64 ( @@v3@@ , * @@a2@@ ) ; tcg_temp_free_ptr ( @@v4@@ ) ; tcg_temp_free_i64 ( @@v3@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; } return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VRINTZ_dp"}, "location": "r64"}, {"n": "fpst", "t": {"T": 3, "t": "TCGv_ptr_d"}, "location": "s16"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s24"}, {"n": "tcg_rmode", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 846 |
[
"{\"name\": \"isar_feature_aa32_fp_d32\", \"code\": \"bool __fastcall isar_feature_aa32_fp_d32 ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) > Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_fpdp\", \"code\": \"bool __fastcall isar_feature_aa32_fpdp ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_vrint\", \"code\": \"bool __fastcall isar_feature_aa32_vrint ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) > Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_i64\", \"code\": \"__int64 __fastcall tcg_temp_free_i64 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i64_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_ptr\", \"code\": \"__int64 __fastcall tcg_temp_free_ptr ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_ptr_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i64\", \"code\": \"__int64 tcg_temp_new_i64 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i64 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_set_rmode\", \"code\": \"unsigned __int64 __fastcall gen_helper_set_rmode ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_set_rmode , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_rintd\", \"code\": \"unsigned __int64 __fastcall gen_helper_rintd ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_rintd , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"get_fpstatus_ptr\", \"code\": \"__int64 __fastcall get_fpstatus_ptr ( int @@a1@@ ) { int @@v2@@ ; __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_ptr ( ) ; if ( @@a1@@ ) @@v2@@ = Number ; else @@v2@@ = Number ; tcg_gen_addi_ptr ( @@v3@@ , cpu_env , @@v2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_load_reg\", \"code\": \"__int64 __fastcall neon_load_reg ( int @@a1@@ , int @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v2@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_ld_i32 ( @@v4@@ , cpu_env , @@v2@@ ) ; return @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_store_reg\", \"code\": \"__int64 __fastcall neon_store_reg ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; @@v3@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_st_i32 ( @@a3@@ , cpu_env , @@v3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_load_reg64\", \"code\": \"__int64 __fastcall neon_load_reg64 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_store_reg64\", \"code\": \"__int64 __fastcall neon_store_reg64 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_st_i64 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"vfp_access_check\", \"code\": \"__int64 __fastcall vfp_access_check ( __int64 @@a1@@ ) { return full_vfp_access_check ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"trans_VRINT\", \"code\": \"__int64 __fastcall trans_VRINT ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { unsigned int @@v3@@ ; bool @@v4@@ ; unsigned int @@v5@@ ; unsigned int @@v6@@ ; unsigned int @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; __int64 @@v13@@ ; @@v4@@ = * @@a2@@ != Number ; @@v5@@ = fp_decode_rm [ @@a2@@ [ Number ] ] ; if ( ! isar_feature_aa32_vrint ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v4@@ && ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( ( ( unsigned __int8 ) @@a2@@ [ Number ] | ( unsigned __int8 ) @@a2@@ [ Number ] ) & Number ) != Number ) { return Number L ; } if ( @@v4@@ && ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v6@@ = @@a2@@ [ Number ] ; @@v7@@ = @@a2@@ [ Number ] ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; @@v8@@ = get_fpstatus_ptr ( Number ) ; @@v3@@ = arm_rmode_to_sf ( @@v5@@ ) ; @@v9@@ = tcg_const_i32 ( @@v3@@ ) ; gen_helper_set_rmode ( @@v9@@ , @@v9@@ , @@v8@@ ) ; if ( @@v4@@ ) { @@v12@@ = tcg_temp_new_i64 ( ) ; @@v13@@ = tcg_temp_new_i64 ( ) ; neon_load_reg64 ( @@v12@@ , @@v7@@ ) ; gen_helper_rintd ( @@v13@@ , @@v12@@ , @@v8@@ ) ; neon_store_reg64 ( @@v13@@ , @@v6@@ ) ; tcg_temp_free_i64 ( @@v12@@ ) ; tcg_temp_free_i64 ( @@v13@@ ) ; } else { @@v10@@ = tcg_temp_new_i32 ( ) ; @@v11@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v10@@ , @@v7@@ ) ; gen_helper_rints ( @@v11@@ , @@v10@@ , @@v8@@ ) ; neon_store_reg32 ( @@v11@@ , @@v6@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; } gen_helper_set_rmode ( @@v9@@ , @@v9@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_temp_free_ptr ( @@v8@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s40\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s48\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s76\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s80\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s84\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s85\"}]}"
] |
{"name": "trans_VRINTX_sp", "code": "__int64 __fastcall trans_VRINTX_sp ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; if ( ! isar_feature_aa32_vrint ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) == Number ) { @@v3@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v3@@ , @@a2@@ [ Number ] ) ; @@v4@@ = get_fpstatus_ptr ( Number ) ; gen_helper_rints_exact ( @@v3@@ , @@v3@@ , @@v4@@ ) ; neon_store_reg32 ( @@v3@@ , * @@a2@@ ) ; tcg_temp_free_ptr ( @@v4@@ ) ; tcg_temp_free_i32 ( @@v3@@ ) ; } return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VRINTX_sp"}, "location": "r64"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "fpst", "t": {"T": 3, "t": "TCGv_ptr_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 847 |
[
"{\"name\": \"isar_feature_aa32_vrint\", \"code\": \"bool __fastcall isar_feature_aa32_vrint ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) > Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_ptr\", \"code\": \"__int64 __fastcall tcg_temp_free_ptr ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_ptr_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_rints_exact\", \"code\": \"unsigned __int64 __fastcall gen_helper_rints_exact ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_rints_exact , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_rints\", \"code\": \"unsigned __int64 __fastcall gen_helper_rints ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_rints , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"get_fpstatus_ptr\", \"code\": \"__int64 __fastcall get_fpstatus_ptr ( int @@a1@@ ) { int @@v2@@ ; __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_ptr ( ) ; if ( @@a1@@ ) @@v2@@ = Number ; else @@v2@@ = Number ; tcg_gen_addi_ptr ( @@v3@@ , cpu_env , @@v2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_load_reg\", \"code\": \"__int64 __fastcall neon_load_reg ( int @@a1@@ , int @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v2@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_ld_i32 ( @@v4@@ , cpu_env , @@v2@@ ) ; return @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_store_reg\", \"code\": \"__int64 __fastcall neon_store_reg ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; @@v3@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_st_i32 ( @@a3@@ , cpu_env , @@v3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_load_reg32\", \"code\": \"__int64 __fastcall neon_load_reg32 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_ld_i32 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_store_reg32\", \"code\": \"__int64 __fastcall neon_store_reg32 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_st_i32 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"vfp_access_check\", \"code\": \"__int64 __fastcall vfp_access_check ( __int64 @@a1@@ ) { return full_vfp_access_check ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"trans_VRINT\", \"code\": \"__int64 __fastcall trans_VRINT ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { unsigned int @@v3@@ ; bool @@v4@@ ; unsigned int @@v5@@ ; unsigned int @@v6@@ ; unsigned int @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; __int64 @@v13@@ ; @@v4@@ = * @@a2@@ != Number ; @@v5@@ = fp_decode_rm [ @@a2@@ [ Number ] ] ; if ( ! isar_feature_aa32_vrint ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v4@@ && ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( ( ( unsigned __int8 ) @@a2@@ [ Number ] | ( unsigned __int8 ) @@a2@@ [ Number ] ) & Number ) != Number ) { return Number L ; } if ( @@v4@@ && ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v6@@ = @@a2@@ [ Number ] ; @@v7@@ = @@a2@@ [ Number ] ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; @@v8@@ = get_fpstatus_ptr ( Number ) ; @@v3@@ = arm_rmode_to_sf ( @@v5@@ ) ; @@v9@@ = tcg_const_i32 ( @@v3@@ ) ; gen_helper_set_rmode ( @@v9@@ , @@v9@@ , @@v8@@ ) ; if ( @@v4@@ ) { @@v12@@ = tcg_temp_new_i64 ( ) ; @@v13@@ = tcg_temp_new_i64 ( ) ; neon_load_reg64 ( @@v12@@ , @@v7@@ ) ; gen_helper_rintd ( @@v13@@ , @@v12@@ , @@v8@@ ) ; neon_store_reg64 ( @@v13@@ , @@v6@@ ) ; tcg_temp_free_i64 ( @@v12@@ ) ; tcg_temp_free_i64 ( @@v13@@ ) ; } else { @@v10@@ = tcg_temp_new_i32 ( ) ; @@v11@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v10@@ , @@v7@@ ) ; gen_helper_rints ( @@v11@@ , @@v10@@ , @@v8@@ ) ; neon_store_reg32 ( @@v11@@ , @@v6@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; } gen_helper_set_rmode ( @@v9@@ , @@v9@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_temp_free_ptr ( @@v8@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s40\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s48\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s76\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s80\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s84\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s85\"}]}"
] |
{"name": "trans_VRINTX_dp", "code": "__int64 __fastcall trans_VRINTX_dp ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; if ( ! isar_feature_aa32_vrint ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( ( ( unsigned __int8 ) * @@a2@@ | ( unsigned __int8 ) @@a2@@ [ Number ] ) & Number ) != Number ) return Number L ; if ( ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) == Number ) { @@v3@@ = tcg_temp_new_i64 ( ) ; neon_load_reg64 ( @@v3@@ , @@a2@@ [ Number ] ) ; @@v4@@ = get_fpstatus_ptr ( Number ) ; gen_helper_rintd_exact ( @@v3@@ , @@v3@@ , @@v4@@ ) ; neon_store_reg64 ( @@v3@@ , * @@a2@@ ) ; tcg_temp_free_ptr ( @@v4@@ ) ; tcg_temp_free_i64 ( @@v3@@ ) ; } return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VRINTX_dp"}, "location": "r64"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s16"}, {"n": "fpst", "t": {"T": 3, "t": "TCGv_ptr_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 848 |
[
"{\"name\": \"isar_feature_aa32_fp_d32\", \"code\": \"bool __fastcall isar_feature_aa32_fp_d32 ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) > Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_fpdp\", \"code\": \"bool __fastcall isar_feature_aa32_fpdp ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_vrint\", \"code\": \"bool __fastcall isar_feature_aa32_vrint ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) > Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"tcg_temp_free_i64\", \"code\": \"__int64 __fastcall tcg_temp_free_i64 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i64_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_ptr\", \"code\": \"__int64 __fastcall tcg_temp_free_ptr ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_ptr_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i64\", \"code\": \"__int64 tcg_temp_new_i64 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i64 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_rintd_exact\", \"code\": \"unsigned __int64 __fastcall gen_helper_rintd_exact ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_rintd_exact , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_rintd\", \"code\": \"unsigned __int64 __fastcall gen_helper_rintd ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_rintd , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"get_fpstatus_ptr\", \"code\": \"__int64 __fastcall get_fpstatus_ptr ( int @@a1@@ ) { int @@v2@@ ; __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_ptr ( ) ; if ( @@a1@@ ) @@v2@@ = Number ; else @@v2@@ = Number ; tcg_gen_addi_ptr ( @@v3@@ , cpu_env , @@v2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_load_reg\", \"code\": \"__int64 __fastcall neon_load_reg ( int @@a1@@ , int @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v2@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_ld_i32 ( @@v4@@ , cpu_env , @@v2@@ ) ; return @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_store_reg\", \"code\": \"__int64 __fastcall neon_store_reg ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; @@v3@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_st_i32 ( @@a3@@ , cpu_env , @@v3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_load_reg64\", \"code\": \"__int64 __fastcall neon_load_reg64 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_store_reg64\", \"code\": \"__int64 __fastcall neon_store_reg64 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_st_i64 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"vfp_access_check\", \"code\": \"__int64 __fastcall vfp_access_check ( __int64 @@a1@@ ) { return full_vfp_access_check ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"trans_VRINT\", \"code\": \"__int64 __fastcall trans_VRINT ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { unsigned int @@v3@@ ; bool @@v4@@ ; unsigned int @@v5@@ ; unsigned int @@v6@@ ; unsigned int @@v7@@ ; __int64 @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; __int64 @@v13@@ ; @@v4@@ = * @@a2@@ != Number ; @@v5@@ = fp_decode_rm [ @@a2@@ [ Number ] ] ; if ( ! isar_feature_aa32_vrint ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v4@@ && ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( ( ( unsigned __int8 ) @@a2@@ [ Number ] | ( unsigned __int8 ) @@a2@@ [ Number ] ) & Number ) != Number ) { return Number L ; } if ( @@v4@@ && ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v6@@ = @@a2@@ [ Number ] ; @@v7@@ = @@a2@@ [ Number ] ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; @@v8@@ = get_fpstatus_ptr ( Number ) ; @@v3@@ = arm_rmode_to_sf ( @@v5@@ ) ; @@v9@@ = tcg_const_i32 ( @@v3@@ ) ; gen_helper_set_rmode ( @@v9@@ , @@v9@@ , @@v8@@ ) ; if ( @@v4@@ ) { @@v12@@ = tcg_temp_new_i64 ( ) ; @@v13@@ = tcg_temp_new_i64 ( ) ; neon_load_reg64 ( @@v12@@ , @@v7@@ ) ; gen_helper_rintd ( @@v13@@ , @@v12@@ , @@v8@@ ) ; neon_store_reg64 ( @@v13@@ , @@v6@@ ) ; tcg_temp_free_i64 ( @@v12@@ ) ; tcg_temp_free_i64 ( @@v13@@ ) ; } else { @@v10@@ = tcg_temp_new_i32 ( ) ; @@v11@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v10@@ , @@v7@@ ) ; gen_helper_rints ( @@v11@@ , @@v10@@ , @@v8@@ ) ; neon_store_reg32 ( @@v11@@ , @@v6@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; } gen_helper_set_rmode ( @@v9@@ , @@v9@@ , @@v8@@ ) ; tcg_temp_free_i32 ( @@v9@@ ) ; tcg_temp_free_ptr ( @@v8@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s40\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s48\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s76\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s80\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s84\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s85\"}]}"
] |
{"name": "trans_VCVT_sp", "code": "__int64 __fastcall trans_VCVT_sp ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; if ( ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( * @@a2@@ & Number ) != Number ) return Number L ; if ( ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) == Number ) { @@v3@@ = tcg_temp_new_i32 ( ) ; @@v4@@ = tcg_temp_new_i64 ( ) ; neon_load_reg32 ( @@v3@@ , @@a2@@ [ Number ] ) ; gen_helper_vfp_fcvtds ( @@v4@@ , @@v3@@ , cpu_env ) ; neon_store_reg64 ( @@v4@@ , * @@a2@@ ) ; tcg_temp_free_i32 ( @@v3@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; } return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VCVT_sp"}, "location": "r64"}, {"n": "vm", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "vd", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 849 |
[
"{\"name\": \"isar_feature_aa32_fp_d32\", \"code\": \"bool __fastcall isar_feature_aa32_fp_d32 ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) > Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_fpdp\", \"code\": \"bool __fastcall isar_feature_aa32_fpdp ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_i64\", \"code\": \"__int64 __fastcall tcg_temp_free_i64 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i64_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_temp_new_i64\", \"code\": \"__int64 tcg_temp_new_i64 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i64 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_fcvtds\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_fcvtds ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_fcvtds , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"neon_load_reg\", \"code\": \"__int64 __fastcall neon_load_reg ( int @@a1@@ , int @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v2@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_ld_i32 ( @@v4@@ , cpu_env , @@v2@@ ) ; return @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_store_reg\", \"code\": \"__int64 __fastcall neon_store_reg ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; @@v3@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_st_i32 ( @@a3@@ , cpu_env , @@v3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_store_reg64\", \"code\": \"__int64 __fastcall neon_store_reg64 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_st_i64 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_load_reg32\", \"code\": \"__int64 __fastcall neon_load_reg32 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_ld_i32 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"vfp_access_check\", \"code\": \"__int64 __fastcall vfp_access_check ( __int64 @@a1@@ ) { return full_vfp_access_check ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"trans_VCVT\", \"code\": \"__int64 __fastcall trans_VCVT ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { unsigned int @@v3@@ ; bool @@v4@@ ; bool @@v5@@ ; unsigned int @@v6@@ ; unsigned int @@v7@@ ; unsigned int @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; __int64 @@v13@@ ; __int64 @@v14@@ ; __int64 @@v15@@ ; __int64 @@v16@@ ; @@v4@@ = * @@a2@@ != Number ; @@v6@@ = fp_decode_rm [ @@a2@@ [ Number ] ] ; @@v5@@ = @@a2@@ [ Number ] != Number ; if ( ! isar_feature_aa32_vcvt_dr ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v4@@ && ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@a2@@ [ Number ] & Number ) != Number ) return Number L ; if ( @@v4@@ && ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v7@@ = @@a2@@ [ Number ] ; @@v8@@ = @@a2@@ [ Number ] ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; @@v9@@ = get_fpstatus_ptr ( Number ) ; @@v10@@ = tcg_const_i32 ( Number L ) ; @@v3@@ = arm_rmode_to_sf ( @@v6@@ ) ; @@v11@@ = tcg_const_i32 ( @@v3@@ ) ; gen_helper_set_rmode ( @@v11@@ , @@v11@@ , @@v9@@ ) ; if ( @@v4@@ ) { @@v14@@ = tcg_temp_new_i64 ( ) ; @@v15@@ = tcg_temp_new_i64 ( ) ; @@v16@@ = tcg_temp_new_i32 ( ) ; neon_load_reg64 ( @@v14@@ , @@v8@@ ) ; if ( @@v5@@ ) gen_helper_vfp_tosld ( @@v15@@ , @@v14@@ , @@v10@@ , @@v9@@ ) ; else gen_helper_vfp_tould ( @@v15@@ , @@v14@@ , @@v10@@ , @@v9@@ ) ; tcg_gen_extrl_i64_i32 ( @@v16@@ , @@v15@@ ) ; neon_store_reg32 ( @@v16@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v16@@ ) ; tcg_temp_free_i64 ( @@v15@@ ) ; tcg_temp_free_i64 ( @@v14@@ ) ; } else { @@v12@@ = tcg_temp_new_i32 ( ) ; @@v13@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v12@@ , @@v8@@ ) ; if ( @@v5@@ ) gen_helper_vfp_tosls ( @@v13@@ , @@v12@@ , @@v10@@ , @@v9@@ ) ; else gen_helper_vfp_touls ( @@v13@@ , @@v12@@ , @@v10@@ , @@v9@@ ) ; neon_store_reg32 ( @@v13@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v13@@ ) ; tcg_temp_free_i32 ( @@v12@@ ) ; } gen_helper_set_rmode ( @@v11@@ , @@v11@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_ptr ( @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s100\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s101\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s102\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s40\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s48\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s56\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s64\"}, {\"n\": \"v16\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s92\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s96\"}]}"
] |
{"name": "trans_VCVT_dp", "code": "__int64 __fastcall trans_VCVT_dp ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; if ( ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@a2@@ [ Number ] & Number ) != Number ) return Number L ; if ( ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) == Number ) { @@v3@@ = tcg_temp_new_i32 ( ) ; @@v4@@ = tcg_temp_new_i64 ( ) ; neon_load_reg64 ( @@v4@@ , @@a2@@ [ Number ] ) ; gen_helper_vfp_fcvtsd ( @@v3@@ , @@v4@@ , cpu_env ) ; neon_store_reg32 ( @@v3@@ , * @@a2@@ ) ; tcg_temp_free_i32 ( @@v3@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; } return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VCVT_dp"}, "location": "r64"}, {"n": "vd", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "vm", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 850 |
[
"{\"name\": \"isar_feature_aa32_fp_d32\", \"code\": \"bool __fastcall isar_feature_aa32_fp_d32 ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) > Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_fpdp\", \"code\": \"bool __fastcall isar_feature_aa32_fpdp ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_i64\", \"code\": \"__int64 __fastcall tcg_temp_free_i64 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i64_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_temp_new_i64\", \"code\": \"__int64 tcg_temp_new_i64 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i64 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_fcvtsd\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_fcvtsd ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_fcvtsd , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"neon_load_reg\", \"code\": \"__int64 __fastcall neon_load_reg ( int @@a1@@ , int @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v2@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_ld_i32 ( @@v4@@ , cpu_env , @@v2@@ ) ; return @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_store_reg\", \"code\": \"__int64 __fastcall neon_store_reg ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; @@v3@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_st_i32 ( @@a3@@ , cpu_env , @@v3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_load_reg64\", \"code\": \"__int64 __fastcall neon_load_reg64 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_store_reg32\", \"code\": \"__int64 __fastcall neon_store_reg32 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_st_i32 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"vfp_access_check\", \"code\": \"__int64 __fastcall vfp_access_check ( __int64 @@a1@@ ) { return full_vfp_access_check ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"trans_VCVT\", \"code\": \"__int64 __fastcall trans_VCVT ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { unsigned int @@v3@@ ; bool @@v4@@ ; bool @@v5@@ ; unsigned int @@v6@@ ; unsigned int @@v7@@ ; unsigned int @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; __int64 @@v13@@ ; __int64 @@v14@@ ; __int64 @@v15@@ ; __int64 @@v16@@ ; @@v4@@ = * @@a2@@ != Number ; @@v6@@ = fp_decode_rm [ @@a2@@ [ Number ] ] ; @@v5@@ = @@a2@@ [ Number ] != Number ; if ( ! isar_feature_aa32_vcvt_dr ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v4@@ && ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@a2@@ [ Number ] & Number ) != Number ) return Number L ; if ( @@v4@@ && ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v7@@ = @@a2@@ [ Number ] ; @@v8@@ = @@a2@@ [ Number ] ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; @@v9@@ = get_fpstatus_ptr ( Number ) ; @@v10@@ = tcg_const_i32 ( Number L ) ; @@v3@@ = arm_rmode_to_sf ( @@v6@@ ) ; @@v11@@ = tcg_const_i32 ( @@v3@@ ) ; gen_helper_set_rmode ( @@v11@@ , @@v11@@ , @@v9@@ ) ; if ( @@v4@@ ) { @@v14@@ = tcg_temp_new_i64 ( ) ; @@v15@@ = tcg_temp_new_i64 ( ) ; @@v16@@ = tcg_temp_new_i32 ( ) ; neon_load_reg64 ( @@v14@@ , @@v8@@ ) ; if ( @@v5@@ ) gen_helper_vfp_tosld ( @@v15@@ , @@v14@@ , @@v10@@ , @@v9@@ ) ; else gen_helper_vfp_tould ( @@v15@@ , @@v14@@ , @@v10@@ , @@v9@@ ) ; tcg_gen_extrl_i64_i32 ( @@v16@@ , @@v15@@ ) ; neon_store_reg32 ( @@v16@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v16@@ ) ; tcg_temp_free_i64 ( @@v15@@ ) ; tcg_temp_free_i64 ( @@v14@@ ) ; } else { @@v12@@ = tcg_temp_new_i32 ( ) ; @@v13@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v12@@ , @@v8@@ ) ; if ( @@v5@@ ) gen_helper_vfp_tosls ( @@v13@@ , @@v12@@ , @@v10@@ , @@v9@@ ) ; else gen_helper_vfp_touls ( @@v13@@ , @@v12@@ , @@v10@@ , @@v9@@ ) ; neon_store_reg32 ( @@v13@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v13@@ ) ; tcg_temp_free_i32 ( @@v12@@ ) ; } gen_helper_set_rmode ( @@v11@@ , @@v11@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_ptr ( @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s100\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s101\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s102\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s40\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s48\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s56\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s64\"}, {\"n\": \"v16\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s92\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s96\"}]}"
] |
{"name": "trans_VCVT_int_sp", "code": "__int64 __fastcall trans_VCVT_int_sp ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; @@v3@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v3@@ , @@a2@@ [ Number ] ) ; @@v4@@ = get_fpstatus_ptr ( Number ) ; if ( * @@a2@@ ) gen_helper_vfp_sitos ( @@v3@@ , @@v3@@ , @@v4@@ ) ; else gen_helper_vfp_uitos ( @@v3@@ , @@v3@@ , @@v4@@ ) ; neon_store_reg32 ( @@v3@@ , @@a2@@ [ Number ] ) ; tcg_temp_free_i32 ( @@v3@@ ) ; tcg_temp_free_ptr ( @@v4@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VCVT_int_sp"}, "location": "r64"}, {"n": "vm", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "fpst", "t": {"T": 3, "t": "TCGv_ptr_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 851 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_ptr\", \"code\": \"__int64 __fastcall tcg_temp_free_ptr ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_ptr_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_uitos\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_uitos ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_uitos , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_sitos\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_sitos ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_sitos , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"get_fpstatus_ptr\", \"code\": \"__int64 __fastcall get_fpstatus_ptr ( int @@a1@@ ) { int @@v2@@ ; __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_ptr ( ) ; if ( @@a1@@ ) @@v2@@ = Number ; else @@v2@@ = Number ; tcg_gen_addi_ptr ( @@v3@@ , cpu_env , @@v2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_load_reg\", \"code\": \"__int64 __fastcall neon_load_reg ( int @@a1@@ , int @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v2@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_ld_i32 ( @@v4@@ , cpu_env , @@v2@@ ) ; return @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_store_reg\", \"code\": \"__int64 __fastcall neon_store_reg ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; @@v3@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_st_i32 ( @@a3@@ , cpu_env , @@v3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_load_reg32\", \"code\": \"__int64 __fastcall neon_load_reg32 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_ld_i32 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_store_reg32\", \"code\": \"__int64 __fastcall neon_store_reg32 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_st_i32 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"vfp_access_check\", \"code\": \"__int64 __fastcall vfp_access_check ( __int64 @@a1@@ ) { return full_vfp_access_check ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"trans_VCVT\", \"code\": \"__int64 __fastcall trans_VCVT ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { unsigned int @@v3@@ ; bool @@v4@@ ; bool @@v5@@ ; unsigned int @@v6@@ ; unsigned int @@v7@@ ; unsigned int @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; __int64 @@v13@@ ; __int64 @@v14@@ ; __int64 @@v15@@ ; __int64 @@v16@@ ; @@v4@@ = * @@a2@@ != Number ; @@v6@@ = fp_decode_rm [ @@a2@@ [ Number ] ] ; @@v5@@ = @@a2@@ [ Number ] != Number ; if ( ! isar_feature_aa32_vcvt_dr ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v4@@ && ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@a2@@ [ Number ] & Number ) != Number ) return Number L ; if ( @@v4@@ && ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v7@@ = @@a2@@ [ Number ] ; @@v8@@ = @@a2@@ [ Number ] ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; @@v9@@ = get_fpstatus_ptr ( Number ) ; @@v10@@ = tcg_const_i32 ( Number L ) ; @@v3@@ = arm_rmode_to_sf ( @@v6@@ ) ; @@v11@@ = tcg_const_i32 ( @@v3@@ ) ; gen_helper_set_rmode ( @@v11@@ , @@v11@@ , @@v9@@ ) ; if ( @@v4@@ ) { @@v14@@ = tcg_temp_new_i64 ( ) ; @@v15@@ = tcg_temp_new_i64 ( ) ; @@v16@@ = tcg_temp_new_i32 ( ) ; neon_load_reg64 ( @@v14@@ , @@v8@@ ) ; if ( @@v5@@ ) gen_helper_vfp_tosld ( @@v15@@ , @@v14@@ , @@v10@@ , @@v9@@ ) ; else gen_helper_vfp_tould ( @@v15@@ , @@v14@@ , @@v10@@ , @@v9@@ ) ; tcg_gen_extrl_i64_i32 ( @@v16@@ , @@v15@@ ) ; neon_store_reg32 ( @@v16@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v16@@ ) ; tcg_temp_free_i64 ( @@v15@@ ) ; tcg_temp_free_i64 ( @@v14@@ ) ; } else { @@v12@@ = tcg_temp_new_i32 ( ) ; @@v13@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v12@@ , @@v8@@ ) ; if ( @@v5@@ ) gen_helper_vfp_tosls ( @@v13@@ , @@v12@@ , @@v10@@ , @@v9@@ ) ; else gen_helper_vfp_touls ( @@v13@@ , @@v12@@ , @@v10@@ , @@v9@@ ) ; neon_store_reg32 ( @@v13@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v13@@ ) ; tcg_temp_free_i32 ( @@v12@@ ) ; } gen_helper_set_rmode ( @@v11@@ , @@v11@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_ptr ( @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s100\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s101\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s102\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s40\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s48\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s56\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s64\"}, {\"n\": \"v16\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s92\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s96\"}]}"
] |
{"name": "trans_VCVT_int_dp", "code": "__int64 __fastcall trans_VCVT_int_dp ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; __int64 @@v5@@ ; if ( ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@a2@@ [ Number ] & Number ) != Number ) return Number L ; if ( ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; @@v3@@ = tcg_temp_new_i32 ( ) ; @@v4@@ = tcg_temp_new_i64 ( ) ; neon_load_reg32 ( @@v3@@ , @@a2@@ [ Number ] ) ; @@v5@@ = get_fpstatus_ptr ( Number ) ; if ( * @@a2@@ ) gen_helper_vfp_sitod ( @@v4@@ , @@v3@@ , @@v5@@ ) ; else gen_helper_vfp_uitod ( @@v4@@ , @@v3@@ , @@v5@@ ) ; neon_store_reg64 ( @@v4@@ , @@a2@@ [ Number ] ) ; tcg_temp_free_i32 ( @@v3@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; tcg_temp_free_ptr ( @@v5@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VCVT_int_dp"}, "location": "r64"}, {"n": "vd", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s16"}, {"n": "vm", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s24"}, {"n": "fpst", "t": {"T": 3, "t": "TCGv_ptr_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 852 |
[
"{\"name\": \"isar_feature_aa32_fp_d32\", \"code\": \"bool __fastcall isar_feature_aa32_fp_d32 ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) > Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_fpdp\", \"code\": \"bool __fastcall isar_feature_aa32_fpdp ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_i64\", \"code\": \"__int64 __fastcall tcg_temp_free_i64 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i64_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_ptr\", \"code\": \"__int64 __fastcall tcg_temp_free_ptr ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_ptr_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_temp_new_i64\", \"code\": \"__int64 tcg_temp_new_i64 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i64 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_uitod\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_uitod ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_uitod , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_sitod\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_sitod ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_sitod , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"get_fpstatus_ptr\", \"code\": \"__int64 __fastcall get_fpstatus_ptr ( int @@a1@@ ) { int @@v2@@ ; __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_ptr ( ) ; if ( @@a1@@ ) @@v2@@ = Number ; else @@v2@@ = Number ; tcg_gen_addi_ptr ( @@v3@@ , cpu_env , @@v2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_load_reg\", \"code\": \"__int64 __fastcall neon_load_reg ( int @@a1@@ , int @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v2@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_ld_i32 ( @@v4@@ , cpu_env , @@v2@@ ) ; return @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_store_reg\", \"code\": \"__int64 __fastcall neon_store_reg ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; @@v3@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_st_i32 ( @@a3@@ , cpu_env , @@v3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_store_reg64\", \"code\": \"__int64 __fastcall neon_store_reg64 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_st_i64 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_load_reg32\", \"code\": \"__int64 __fastcall neon_load_reg32 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_ld_i32 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"vfp_access_check\", \"code\": \"__int64 __fastcall vfp_access_check ( __int64 @@a1@@ ) { return full_vfp_access_check ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"trans_VCVT\", \"code\": \"__int64 __fastcall trans_VCVT ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { unsigned int @@v3@@ ; bool @@v4@@ ; bool @@v5@@ ; unsigned int @@v6@@ ; unsigned int @@v7@@ ; unsigned int @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; __int64 @@v13@@ ; __int64 @@v14@@ ; __int64 @@v15@@ ; __int64 @@v16@@ ; @@v4@@ = * @@a2@@ != Number ; @@v6@@ = fp_decode_rm [ @@a2@@ [ Number ] ] ; @@v5@@ = @@a2@@ [ Number ] != Number ; if ( ! isar_feature_aa32_vcvt_dr ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v4@@ && ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@a2@@ [ Number ] & Number ) != Number ) return Number L ; if ( @@v4@@ && ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v7@@ = @@a2@@ [ Number ] ; @@v8@@ = @@a2@@ [ Number ] ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; @@v9@@ = get_fpstatus_ptr ( Number ) ; @@v10@@ = tcg_const_i32 ( Number L ) ; @@v3@@ = arm_rmode_to_sf ( @@v6@@ ) ; @@v11@@ = tcg_const_i32 ( @@v3@@ ) ; gen_helper_set_rmode ( @@v11@@ , @@v11@@ , @@v9@@ ) ; if ( @@v4@@ ) { @@v14@@ = tcg_temp_new_i64 ( ) ; @@v15@@ = tcg_temp_new_i64 ( ) ; @@v16@@ = tcg_temp_new_i32 ( ) ; neon_load_reg64 ( @@v14@@ , @@v8@@ ) ; if ( @@v5@@ ) gen_helper_vfp_tosld ( @@v15@@ , @@v14@@ , @@v10@@ , @@v9@@ ) ; else gen_helper_vfp_tould ( @@v15@@ , @@v14@@ , @@v10@@ , @@v9@@ ) ; tcg_gen_extrl_i64_i32 ( @@v16@@ , @@v15@@ ) ; neon_store_reg32 ( @@v16@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v16@@ ) ; tcg_temp_free_i64 ( @@v15@@ ) ; tcg_temp_free_i64 ( @@v14@@ ) ; } else { @@v12@@ = tcg_temp_new_i32 ( ) ; @@v13@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v12@@ , @@v8@@ ) ; if ( @@v5@@ ) gen_helper_vfp_tosls ( @@v13@@ , @@v12@@ , @@v10@@ , @@v9@@ ) ; else gen_helper_vfp_touls ( @@v13@@ , @@v12@@ , @@v10@@ , @@v9@@ ) ; neon_store_reg32 ( @@v13@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v13@@ ) ; tcg_temp_free_i32 ( @@v12@@ ) ; } gen_helper_set_rmode ( @@v11@@ , @@v11@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_ptr ( @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s100\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s101\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s102\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s40\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s48\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s56\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s64\"}, {\"n\": \"v16\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s92\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s96\"}]}"
] |
{"name": "trans_VJCVT", "code": "__int64 __fastcall trans_VJCVT ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; if ( ! isar_feature_aa32_jscvt ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@a2@@ [ Number ] & Number ) != Number ) return Number L ; if ( ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) == Number ) { @@v3@@ = tcg_temp_new_i64 ( ) ; @@v4@@ = tcg_temp_new_i32 ( ) ; neon_load_reg64 ( @@v3@@ , @@a2@@ [ Number ] ) ; gen_helper_vjcvt ( @@v4@@ , @@v3@@ , cpu_env ) ; neon_store_reg32 ( @@v4@@ , * @@a2@@ ) ; tcg_temp_free_i64 ( @@v3@@ ) ; tcg_temp_free_i32 ( @@v4@@ ) ; } return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "unsigned int"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VJCVT"}, "location": "r64"}, {"n": "vm", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s16"}, {"n": "vd", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 853 |
[
"{\"name\": \"isar_feature_aa32_jscvt\", \"code\": \"bool __fastcall isar_feature_aa32_jscvt ( __int64 @@a1@@ ) { return ( unsigned int ) extract32 ( * ( _DWORD * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_fp_d32\", \"code\": \"bool __fastcall isar_feature_aa32_fp_d32 ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) > Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_fpdp\", \"code\": \"bool __fastcall isar_feature_aa32_fpdp ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_i64\", \"code\": \"__int64 __fastcall tcg_temp_free_i64 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i64_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_temp_new_i64\", \"code\": \"__int64 tcg_temp_new_i64 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i64 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vjcvt\", \"code\": \"unsigned __int64 __fastcall gen_helper_vjcvt ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vjcvt , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"neon_load_reg\", \"code\": \"__int64 __fastcall neon_load_reg ( int @@a1@@ , int @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v2@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_ld_i32 ( @@v4@@ , cpu_env , @@v2@@ ) ; return @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_store_reg\", \"code\": \"__int64 __fastcall neon_store_reg ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; @@v3@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_st_i32 ( @@a3@@ , cpu_env , @@v3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_load_reg64\", \"code\": \"__int64 __fastcall neon_load_reg64 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_store_reg32\", \"code\": \"__int64 __fastcall neon_store_reg32 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_st_i32 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"vfp_access_check\", \"code\": \"__int64 __fastcall vfp_access_check ( __int64 @@a1@@ ) { return full_vfp_access_check ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}"
] |
{"name": "trans_VCVT_fix_sp", "code": "__int64 __fastcall trans_VCVT_fix_sp ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v3@@ ; unsigned int @@v4@@ ; __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; if ( ( @@a2@@ [ Number ] & Number ) != Number ) @@v3@@ = Number - * @@a2@@ ; else @@v3@@ = Number - * @@a2@@ ; @@v4@@ = @@v3@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v5@@ , @@a2@@ [ Number ] ) ; @@v6@@ = get_fpstatus_ptr ( Number ) ; @@v7@@ = tcg_const_i32 ( @@v4@@ ) ; switch ( @@a2@@ [ Number ] ) { case Number : gen_helper_vfp_shtos ( @@v5@@ , @@v5@@ , @@v7@@ , @@v6@@ ) ; break ; case Number : gen_helper_vfp_sltos ( @@v5@@ , @@v5@@ , @@v7@@ , @@v6@@ ) ; break ; case Number : gen_helper_vfp_uhtos ( @@v5@@ , @@v5@@ , @@v7@@ , @@v6@@ ) ; break ; case Number : gen_helper_vfp_ultos ( @@v5@@ , @@v5@@ , @@v7@@ , @@v6@@ ) ; break ; case Number : gen_helper_vfp_toshs_round_to_zero ( @@v5@@ , @@v5@@ , @@v7@@ , @@v6@@ ) ; break ; case Number : gen_helper_vfp_tosls_round_to_zero ( @@v5@@ , @@v5@@ , @@v7@@ , @@v6@@ ) ; break ; case Number : gen_helper_vfp_touhs_round_to_zero ( @@v5@@ , @@v5@@ , @@v7@@ , @@v6@@ ) ; break ; case Number : gen_helper_vfp_touls_round_to_zero ( @@v5@@ , @@v5@@ , @@v7@@ , @@v6@@ ) ; break ; default : g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; break ; } neon_store_reg32 ( @@v5@@ , @@a2@@ [ Number ] ) ; tcg_temp_free_i32 ( @@v5@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_ptr ( @@v6@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s28"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VCVT_fix_sp"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}, {"n": "fpst", "t": {"T": 3, "t": "TCGv_ptr_d"}, "location": "s16"}, {"n": "vd", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s24"}, {"n": "frac_bits", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s28"}, {"n": "shift", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 854 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_ptr\", \"code\": \"__int64 __fastcall tcg_temp_free_ptr ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_ptr_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_toshs_round_to_zero\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_toshs_round_to_zero ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_toshs_round_to_zero , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_tosls_round_to_zero\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_tosls_round_to_zero ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_tosls_round_to_zero , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_touhs_round_to_zero\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_touhs_round_to_zero ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_touhs_round_to_zero , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_touls_round_to_zero\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_touls_round_to_zero ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_touls_round_to_zero , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_tosls\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_tosls ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_tosls , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_touls\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_touls ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_touls , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_shtos\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_shtos ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_shtos , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_sltos\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_sltos ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_sltos , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_uhtos\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_uhtos ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_uhtos , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_ultos\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_ultos ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_ultos , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"get_fpstatus_ptr\", \"code\": \"__int64 __fastcall get_fpstatus_ptr ( int @@a1@@ ) { int @@v2@@ ; __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_ptr ( ) ; if ( @@a1@@ ) @@v2@@ = Number ; else @@v2@@ = Number ; tcg_gen_addi_ptr ( @@v3@@ , cpu_env , @@v2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_load_reg\", \"code\": \"__int64 __fastcall neon_load_reg ( int @@a1@@ , int @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v2@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_ld_i32 ( @@v4@@ , cpu_env , @@v2@@ ) ; return @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_store_reg\", \"code\": \"__int64 __fastcall neon_store_reg ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; @@v3@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_st_i32 ( @@a3@@ , cpu_env , @@v3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_load_reg32\", \"code\": \"__int64 __fastcall neon_load_reg32 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_ld_i32 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_store_reg32\", \"code\": \"__int64 __fastcall neon_store_reg32 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_st_i32 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"vfp_access_check\", \"code\": \"__int64 __fastcall vfp_access_check ( __int64 @@a1@@ ) { return full_vfp_access_check ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"trans_VCVT\", \"code\": \"__int64 __fastcall trans_VCVT ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { unsigned int @@v3@@ ; bool @@v4@@ ; bool @@v5@@ ; unsigned int @@v6@@ ; unsigned int @@v7@@ ; unsigned int @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; __int64 @@v13@@ ; __int64 @@v14@@ ; __int64 @@v15@@ ; __int64 @@v16@@ ; @@v4@@ = * @@a2@@ != Number ; @@v6@@ = fp_decode_rm [ @@a2@@ [ Number ] ] ; @@v5@@ = @@a2@@ [ Number ] != Number ; if ( ! isar_feature_aa32_vcvt_dr ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v4@@ && ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@a2@@ [ Number ] & Number ) != Number ) return Number L ; if ( @@v4@@ && ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v7@@ = @@a2@@ [ Number ] ; @@v8@@ = @@a2@@ [ Number ] ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; @@v9@@ = get_fpstatus_ptr ( Number ) ; @@v10@@ = tcg_const_i32 ( Number L ) ; @@v3@@ = arm_rmode_to_sf ( @@v6@@ ) ; @@v11@@ = tcg_const_i32 ( @@v3@@ ) ; gen_helper_set_rmode ( @@v11@@ , @@v11@@ , @@v9@@ ) ; if ( @@v4@@ ) { @@v14@@ = tcg_temp_new_i64 ( ) ; @@v15@@ = tcg_temp_new_i64 ( ) ; @@v16@@ = tcg_temp_new_i32 ( ) ; neon_load_reg64 ( @@v14@@ , @@v8@@ ) ; if ( @@v5@@ ) gen_helper_vfp_tosld ( @@v15@@ , @@v14@@ , @@v10@@ , @@v9@@ ) ; else gen_helper_vfp_tould ( @@v15@@ , @@v14@@ , @@v10@@ , @@v9@@ ) ; tcg_gen_extrl_i64_i32 ( @@v16@@ , @@v15@@ ) ; neon_store_reg32 ( @@v16@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v16@@ ) ; tcg_temp_free_i64 ( @@v15@@ ) ; tcg_temp_free_i64 ( @@v14@@ ) ; } else { @@v12@@ = tcg_temp_new_i32 ( ) ; @@v13@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v12@@ , @@v8@@ ) ; if ( @@v5@@ ) gen_helper_vfp_tosls ( @@v13@@ , @@v12@@ , @@v10@@ , @@v9@@ ) ; else gen_helper_vfp_touls ( @@v13@@ , @@v12@@ , @@v10@@ , @@v9@@ ) ; neon_store_reg32 ( @@v13@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v13@@ ) ; tcg_temp_free_i32 ( @@v12@@ ) ; } gen_helper_set_rmode ( @@v11@@ , @@v11@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_ptr ( @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s100\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s101\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s102\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s40\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s48\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s56\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s64\"}, {\"n\": \"v16\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s92\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s96\"}]}"
] |
{"name": "trans_VCVT_fix_dp", "code": "__int64 __fastcall trans_VCVT_fix_dp ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { int @@v3@@ ; unsigned int @@v4@@ ; __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; if ( ! arm_dc_feature ( @@a1@@ , Number ) ) return Number L ; if ( ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@a2@@ [ Number ] & Number ) != Number ) return Number L ; if ( ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; if ( ( @@a2@@ [ Number ] & Number ) != Number ) @@v3@@ = Number - * @@a2@@ ; else @@v3@@ = Number - * @@a2@@ ; @@v4@@ = @@v3@@ ; @@v5@@ = tcg_temp_new_i64 ( ) ; neon_load_reg64 ( @@v5@@ , @@a2@@ [ Number ] ) ; @@v6@@ = get_fpstatus_ptr ( Number ) ; @@v7@@ = tcg_const_i32 ( @@v4@@ ) ; switch ( @@a2@@ [ Number ] ) { case Number : gen_helper_vfp_shtod ( @@v5@@ , @@v5@@ , @@v7@@ , @@v6@@ ) ; break ; case Number : gen_helper_vfp_sltod ( @@v5@@ , @@v5@@ , @@v7@@ , @@v6@@ ) ; break ; case Number : gen_helper_vfp_uhtod ( @@v5@@ , @@v5@@ , @@v7@@ , @@v6@@ ) ; break ; case Number : gen_helper_vfp_ultod ( @@v5@@ , @@v5@@ , @@v7@@ , @@v6@@ ) ; break ; case Number : gen_helper_vfp_toshd_round_to_zero ( @@v5@@ , @@v5@@ , @@v7@@ , @@v6@@ ) ; break ; case Number : gen_helper_vfp_tosld_round_to_zero ( @@v5@@ , @@v5@@ , @@v7@@ , @@v6@@ ) ; break ; case Number : gen_helper_vfp_touhd_round_to_zero ( @@v5@@ , @@v5@@ , @@v7@@ , @@v6@@ ) ; break ; case Number : gen_helper_vfp_tould_round_to_zero ( @@v5@@ , @@v5@@ , @@v7@@ , @@v6@@ ) ; break ; default : g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; break ; } neon_store_reg64 ( @@v5@@ , @@a2@@ [ Number ] ) ; tcg_temp_free_i64 ( @@v5@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_ptr ( @@v6@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s44"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VCVT_fix_dp"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}, {"n": "fpst", "t": {"T": 3, "t": "TCGv_ptr_d"}, "location": "s16"}, {"n": "vd", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s24"}, {"n": "frac_bits", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s44"}, {"n": "shift", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 855 |
[
"{\"name\": \"isar_feature_aa32_fp_d32\", \"code\": \"bool __fastcall isar_feature_aa32_fp_d32 ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) > Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_fpdp\", \"code\": \"bool __fastcall isar_feature_aa32_fpdp ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_i64\", \"code\": \"__int64 __fastcall tcg_temp_free_i64 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i64_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_ptr\", \"code\": \"__int64 __fastcall tcg_temp_free_ptr ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_ptr_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i64\", \"code\": \"__int64 tcg_temp_new_i64 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i64 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_toshd_round_to_zero\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_toshd_round_to_zero ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_toshd_round_to_zero , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_tosld_round_to_zero\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_tosld_round_to_zero ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_tosld_round_to_zero , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_touhd_round_to_zero\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_touhd_round_to_zero ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_touhd_round_to_zero , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_tould_round_to_zero\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_tould_round_to_zero ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_tould_round_to_zero , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_tosld\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_tosld ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_tosld , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_tould\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_tould ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_tould , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_shtod\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_shtod ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_shtod , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_sltod\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_sltod ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_sltod , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_uhtod\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_uhtod ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_uhtod , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_ultod\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_ultod ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_ultod , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"get_fpstatus_ptr\", \"code\": \"__int64 __fastcall get_fpstatus_ptr ( int @@a1@@ ) { int @@v2@@ ; __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_ptr ( ) ; if ( @@a1@@ ) @@v2@@ = Number ; else @@v2@@ = Number ; tcg_gen_addi_ptr ( @@v3@@ , cpu_env , @@v2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_load_reg\", \"code\": \"__int64 __fastcall neon_load_reg ( int @@a1@@ , int @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v2@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_ld_i32 ( @@v4@@ , cpu_env , @@v2@@ ) ; return @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_store_reg\", \"code\": \"__int64 __fastcall neon_store_reg ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; @@v3@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_st_i32 ( @@a3@@ , cpu_env , @@v3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_load_reg64\", \"code\": \"__int64 __fastcall neon_load_reg64 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_store_reg64\", \"code\": \"__int64 __fastcall neon_store_reg64 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_st_i64 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"vfp_access_check\", \"code\": \"__int64 __fastcall vfp_access_check ( __int64 @@a1@@ ) { return full_vfp_access_check ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"trans_VCVT\", \"code\": \"__int64 __fastcall trans_VCVT ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { unsigned int @@v3@@ ; bool @@v4@@ ; bool @@v5@@ ; unsigned int @@v6@@ ; unsigned int @@v7@@ ; unsigned int @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; __int64 @@v13@@ ; __int64 @@v14@@ ; __int64 @@v15@@ ; __int64 @@v16@@ ; @@v4@@ = * @@a2@@ != Number ; @@v6@@ = fp_decode_rm [ @@a2@@ [ Number ] ] ; @@v5@@ = @@a2@@ [ Number ] != Number ; if ( ! isar_feature_aa32_vcvt_dr ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v4@@ && ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@a2@@ [ Number ] & Number ) != Number ) return Number L ; if ( @@v4@@ && ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v7@@ = @@a2@@ [ Number ] ; @@v8@@ = @@a2@@ [ Number ] ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; @@v9@@ = get_fpstatus_ptr ( Number ) ; @@v10@@ = tcg_const_i32 ( Number L ) ; @@v3@@ = arm_rmode_to_sf ( @@v6@@ ) ; @@v11@@ = tcg_const_i32 ( @@v3@@ ) ; gen_helper_set_rmode ( @@v11@@ , @@v11@@ , @@v9@@ ) ; if ( @@v4@@ ) { @@v14@@ = tcg_temp_new_i64 ( ) ; @@v15@@ = tcg_temp_new_i64 ( ) ; @@v16@@ = tcg_temp_new_i32 ( ) ; neon_load_reg64 ( @@v14@@ , @@v8@@ ) ; if ( @@v5@@ ) gen_helper_vfp_tosld ( @@v15@@ , @@v14@@ , @@v10@@ , @@v9@@ ) ; else gen_helper_vfp_tould ( @@v15@@ , @@v14@@ , @@v10@@ , @@v9@@ ) ; tcg_gen_extrl_i64_i32 ( @@v16@@ , @@v15@@ ) ; neon_store_reg32 ( @@v16@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v16@@ ) ; tcg_temp_free_i64 ( @@v15@@ ) ; tcg_temp_free_i64 ( @@v14@@ ) ; } else { @@v12@@ = tcg_temp_new_i32 ( ) ; @@v13@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v12@@ , @@v8@@ ) ; if ( @@v5@@ ) gen_helper_vfp_tosls ( @@v13@@ , @@v12@@ , @@v10@@ , @@v9@@ ) ; else gen_helper_vfp_touls ( @@v13@@ , @@v12@@ , @@v10@@ , @@v9@@ ) ; neon_store_reg32 ( @@v13@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v13@@ ) ; tcg_temp_free_i32 ( @@v12@@ ) ; } gen_helper_set_rmode ( @@v11@@ , @@v11@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_ptr ( @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s100\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s101\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s102\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s40\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s48\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s56\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s64\"}, {\"n\": \"v16\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s92\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s96\"}]}"
] |
{"name": "trans_VCVT_sp_int", "code": "__int64 __fastcall trans_VCVT_sp_int ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; @@v3@@ = get_fpstatus_ptr ( Number ) ; @@v4@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v4@@ , @@a2@@ [ Number ] ) ; if ( @@a2@@ [ Number ] ) { if ( * @@a2@@ ) gen_helper_vfp_tosizs ( @@v4@@ , @@v4@@ , @@v3@@ ) ; else gen_helper_vfp_tosis ( @@v4@@ , @@v4@@ , @@v3@@ ) ; } else if ( * @@a2@@ ) { gen_helper_vfp_touizs ( @@v4@@ , @@v4@@ , @@v3@@ ) ; } else { gen_helper_vfp_touis ( @@v4@@ , @@v4@@ , @@v3@@ ) ; } neon_store_reg32 ( @@v4@@ , @@a2@@ [ Number ] ) ; tcg_temp_free_i32 ( @@v4@@ ) ; tcg_temp_free_ptr ( @@v3@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VCVT_sp_int"}, "location": "r64"}, {"n": "fpst", "t": {"T": 3, "t": "TCGv_ptr_d"}, "location": "s16"}, {"n": "vm", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 856 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_ptr\", \"code\": \"__int64 __fastcall tcg_temp_free_ptr ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_ptr_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_touis\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_touis ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_touis , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_touizs\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_touizs ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_touizs , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_tosis\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_tosis ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_tosis , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_tosizs\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_tosizs ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_tosizs , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"get_fpstatus_ptr\", \"code\": \"__int64 __fastcall get_fpstatus_ptr ( int @@a1@@ ) { int @@v2@@ ; __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_ptr ( ) ; if ( @@a1@@ ) @@v2@@ = Number ; else @@v2@@ = Number ; tcg_gen_addi_ptr ( @@v3@@ , cpu_env , @@v2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_load_reg\", \"code\": \"__int64 __fastcall neon_load_reg ( int @@a1@@ , int @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v2@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_ld_i32 ( @@v4@@ , cpu_env , @@v2@@ ) ; return @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_store_reg\", \"code\": \"__int64 __fastcall neon_store_reg ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; @@v3@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_st_i32 ( @@a3@@ , cpu_env , @@v3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_load_reg32\", \"code\": \"__int64 __fastcall neon_load_reg32 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_ld_i32 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_store_reg32\", \"code\": \"__int64 __fastcall neon_store_reg32 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_st_i32 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"vfp_access_check\", \"code\": \"__int64 __fastcall vfp_access_check ( __int64 @@a1@@ ) { return full_vfp_access_check ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"trans_VCVT\", \"code\": \"__int64 __fastcall trans_VCVT ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { unsigned int @@v3@@ ; bool @@v4@@ ; bool @@v5@@ ; unsigned int @@v6@@ ; unsigned int @@v7@@ ; unsigned int @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; __int64 @@v13@@ ; __int64 @@v14@@ ; __int64 @@v15@@ ; __int64 @@v16@@ ; @@v4@@ = * @@a2@@ != Number ; @@v6@@ = fp_decode_rm [ @@a2@@ [ Number ] ] ; @@v5@@ = @@a2@@ [ Number ] != Number ; if ( ! isar_feature_aa32_vcvt_dr ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v4@@ && ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@a2@@ [ Number ] & Number ) != Number ) return Number L ; if ( @@v4@@ && ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v7@@ = @@a2@@ [ Number ] ; @@v8@@ = @@a2@@ [ Number ] ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; @@v9@@ = get_fpstatus_ptr ( Number ) ; @@v10@@ = tcg_const_i32 ( Number L ) ; @@v3@@ = arm_rmode_to_sf ( @@v6@@ ) ; @@v11@@ = tcg_const_i32 ( @@v3@@ ) ; gen_helper_set_rmode ( @@v11@@ , @@v11@@ , @@v9@@ ) ; if ( @@v4@@ ) { @@v14@@ = tcg_temp_new_i64 ( ) ; @@v15@@ = tcg_temp_new_i64 ( ) ; @@v16@@ = tcg_temp_new_i32 ( ) ; neon_load_reg64 ( @@v14@@ , @@v8@@ ) ; if ( @@v5@@ ) gen_helper_vfp_tosld ( @@v15@@ , @@v14@@ , @@v10@@ , @@v9@@ ) ; else gen_helper_vfp_tould ( @@v15@@ , @@v14@@ , @@v10@@ , @@v9@@ ) ; tcg_gen_extrl_i64_i32 ( @@v16@@ , @@v15@@ ) ; neon_store_reg32 ( @@v16@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v16@@ ) ; tcg_temp_free_i64 ( @@v15@@ ) ; tcg_temp_free_i64 ( @@v14@@ ) ; } else { @@v12@@ = tcg_temp_new_i32 ( ) ; @@v13@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v12@@ , @@v8@@ ) ; if ( @@v5@@ ) gen_helper_vfp_tosls ( @@v13@@ , @@v12@@ , @@v10@@ , @@v9@@ ) ; else gen_helper_vfp_touls ( @@v13@@ , @@v12@@ , @@v10@@ , @@v9@@ ) ; neon_store_reg32 ( @@v13@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v13@@ ) ; tcg_temp_free_i32 ( @@v12@@ ) ; } gen_helper_set_rmode ( @@v11@@ , @@v11@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_ptr ( @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s100\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s101\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s102\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s40\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s48\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s56\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s64\"}, {\"n\": \"v16\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s92\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s96\"}]}",
"{\"name\": \"trans_VCVT_sp\", \"code\": \"__int64 __fastcall trans_VCVT_sp ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; if ( ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( * @@a2@@ & Number ) != Number ) return Number L ; if ( ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) == Number ) { @@v3@@ = tcg_temp_new_i32 ( ) ; @@v4@@ = tcg_temp_new_i64 ( ) ; neon_load_reg32 ( @@v3@@ , @@a2@@ [ Number ] ) ; gen_helper_vfp_fcvtds ( @@v4@@ , @@v3@@ , cpu_env ) ; neon_store_reg64 ( @@v4@@ , * @@a2@@ ) ; tcg_temp_free_i32 ( @@v3@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; } return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "trans_VCVT_dp_int", "code": "__int64 __fastcall trans_VCVT_dp_int ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; __int64 @@v5@@ ; if ( ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@a2@@ [ Number ] & Number ) != Number ) return Number L ; if ( ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; @@v3@@ = get_fpstatus_ptr ( Number ) ; @@v4@@ = tcg_temp_new_i64 ( ) ; @@v5@@ = tcg_temp_new_i32 ( ) ; neon_load_reg64 ( @@v4@@ , @@a2@@ [ Number ] ) ; if ( @@a2@@ [ Number ] ) { if ( * @@a2@@ ) gen_helper_vfp_tosizd ( @@v5@@ , @@v4@@ , @@v3@@ ) ; else gen_helper_vfp_tosid ( @@v5@@ , @@v4@@ , @@v3@@ ) ; } else if ( * @@a2@@ ) { gen_helper_vfp_touizd ( @@v5@@ , @@v4@@ , @@v3@@ ) ; } else { gen_helper_vfp_touid ( @@v5@@ , @@v4@@ , @@v3@@ ) ; } neon_store_reg32 ( @@v5@@ , @@a2@@ [ Number ] ) ; tcg_temp_free_i32 ( @@v5@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; tcg_temp_free_ptr ( @@v3@@ ) ; return Number L ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_VCVT_dp_int"}, "location": "r64"}, {"n": "vm", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s16"}, {"n": "fpst", "t": {"T": 3, "t": "TCGv_ptr_d"}, "location": "s24"}, {"n": "vd", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 857 |
[
"{\"name\": \"isar_feature_aa32_fp_d32\", \"code\": \"bool __fastcall isar_feature_aa32_fp_d32 ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) > Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"isar_feature_aa32_fpdp\", \"code\": \"bool __fastcall isar_feature_aa32_fpdp ( __int64 @@a1@@ ) { return extract64 ( * ( unsigned int * ) ( @@a1@@ + Number ) , Number , Number ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_i64\", \"code\": \"__int64 __fastcall tcg_temp_free_i64 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i64_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_free_ptr\", \"code\": \"__int64 __fastcall tcg_temp_free_ptr ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_ptr_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_temp_new_i64\", \"code\": \"__int64 tcg_temp_new_i64 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i64 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_touid\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_touid ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_touid , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_touizd\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_touizd ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_touizd , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_tosid\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_tosid ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_tosid , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_vfp_tosizd\", \"code\": \"unsigned __int64 __fastcall gen_helper_vfp_tosizd ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_ptr_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_vfp_tosizd , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"get_fpstatus_ptr\", \"code\": \"__int64 __fastcall get_fpstatus_ptr ( int @@a1@@ ) { int @@v2@@ ; __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_ptr ( ) ; if ( @@a1@@ ) @@v2@@ = Number ; else @@v2@@ = Number ; tcg_gen_addi_ptr ( @@v3@@ , cpu_env , @@v2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_load_reg\", \"code\": \"__int64 __fastcall neon_load_reg ( int @@a1@@ , int @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v2@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_ld_i32 ( @@v4@@ , cpu_env , @@v2@@ ) ; return @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_store_reg\", \"code\": \"__int64 __fastcall neon_store_reg ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; @@v3@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_st_i32 ( @@a3@@ , cpu_env , @@v3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_load_reg64\", \"code\": \"__int64 __fastcall neon_load_reg64 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"neon_store_reg32\", \"code\": \"__int64 __fastcall neon_store_reg32 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_st_i32 ( @@a1@@ , cpu_env , @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"vfp_access_check\", \"code\": \"__int64 __fastcall vfp_access_check ( __int64 @@a1@@ ) { return full_vfp_access_check ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"trans_VCVT\", \"code\": \"__int64 __fastcall trans_VCVT ( __int64 @@a1@@ , _DWORD * @@a2@@ ) { unsigned int @@v3@@ ; bool @@v4@@ ; bool @@v5@@ ; unsigned int @@v6@@ ; unsigned int @@v7@@ ; unsigned int @@v8@@ ; __int64 @@v9@@ ; __int64 @@v10@@ ; __int64 @@v11@@ ; __int64 @@v12@@ ; __int64 @@v13@@ ; __int64 @@v14@@ ; __int64 @@v15@@ ; __int64 @@v16@@ ; @@v4@@ = * @@a2@@ != Number ; @@v6@@ = fp_decode_rm [ @@a2@@ [ Number ] ] ; @@v5@@ = @@a2@@ [ Number ] != Number ; if ( ! isar_feature_aa32_vcvt_dr ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( @@v4@@ && ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@a2@@ [ Number ] & Number ) != Number ) return Number L ; if ( @@v4@@ && ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; @@v7@@ = @@a2@@ [ Number ] ; @@v8@@ = @@a2@@ [ Number ] ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) != Number ) return Number L ; @@v9@@ = get_fpstatus_ptr ( Number ) ; @@v10@@ = tcg_const_i32 ( Number L ) ; @@v3@@ = arm_rmode_to_sf ( @@v6@@ ) ; @@v11@@ = tcg_const_i32 ( @@v3@@ ) ; gen_helper_set_rmode ( @@v11@@ , @@v11@@ , @@v9@@ ) ; if ( @@v4@@ ) { @@v14@@ = tcg_temp_new_i64 ( ) ; @@v15@@ = tcg_temp_new_i64 ( ) ; @@v16@@ = tcg_temp_new_i32 ( ) ; neon_load_reg64 ( @@v14@@ , @@v8@@ ) ; if ( @@v5@@ ) gen_helper_vfp_tosld ( @@v15@@ , @@v14@@ , @@v10@@ , @@v9@@ ) ; else gen_helper_vfp_tould ( @@v15@@ , @@v14@@ , @@v10@@ , @@v9@@ ) ; tcg_gen_extrl_i64_i32 ( @@v16@@ , @@v15@@ ) ; neon_store_reg32 ( @@v16@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v16@@ ) ; tcg_temp_free_i64 ( @@v15@@ ) ; tcg_temp_free_i64 ( @@v14@@ ) ; } else { @@v12@@ = tcg_temp_new_i32 ( ) ; @@v13@@ = tcg_temp_new_i32 ( ) ; neon_load_reg32 ( @@v12@@ , @@v8@@ ) ; if ( @@v5@@ ) gen_helper_vfp_tosls ( @@v13@@ , @@v12@@ , @@v10@@ , @@v9@@ ) ; else gen_helper_vfp_touls ( @@v13@@ , @@v12@@ , @@v10@@ , @@v9@@ ) ; neon_store_reg32 ( @@v13@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v13@@ ) ; tcg_temp_free_i32 ( @@v12@@ ) ; } gen_helper_set_rmode ( @@v11@@ , @@v11@@ , @@v9@@ ) ; tcg_temp_free_i32 ( @@v11@@ ) ; tcg_temp_free_i32 ( @@v10@@ ) ; tcg_temp_free_ptr ( @@v9@@ ) ; return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s100\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s101\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"bool\", \"s\": 1}, \"location\": \"s102\"}, {\"n\": \"v15\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v14\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v13\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s32\"}, {\"n\": \"v12\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s40\"}, {\"n\": \"v11\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s48\"}, {\"n\": \"v10\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s56\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s64\"}, {\"n\": \"v16\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s92\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"s96\"}]}",
"{\"name\": \"trans_VCVT_dp\", \"code\": \"__int64 __fastcall trans_VCVT_dp ( __int64 @@a1@@ , unsigned int * @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; if ( ! isar_feature_aa32_fp_d32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) && ( @@a2@@ [ Number ] & Number ) != Number ) return Number L ; if ( ! isar_feature_aa32_fpdp ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ) return Number L ; if ( ( unsigned __int8 ) vfp_access_check ( @@a1@@ ) == Number ) { @@v3@@ = tcg_temp_new_i32 ( ) ; @@v4@@ = tcg_temp_new_i64 ( ) ; neon_load_reg64 ( @@v4@@ , @@a2@@ [ Number ] ) ; gen_helper_vfp_fcvtsd ( @@v3@@ , @@v4@@ , cpu_env ) ; neon_store_reg32 ( @@v3@@ , * @@a2@@ ) ; tcg_temp_free_i32 ( @@v3@@ ) ; tcg_temp_free_i64 ( @@v4@@ ) ; } return Number L ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "iwmmxt_load_reg", "code": "__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}]}
|
[{"n": "var", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r56"}, {"n": "reg", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 858 |
[
"{\"name\": \"tcg_gen_ld_i64\", \"code\": \"__int64 __fastcall tcg_gen_ld_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "iwmmxt_store_reg", "code": "__int64 __fastcall iwmmxt_store_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_st_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}]}
|
[{"n": "var", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r56"}, {"n": "reg", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 859 |
[
"{\"name\": \"tcg_gen_st_i64\", \"code\": \"__int64 __fastcall tcg_gen_st_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "iwmmxt_load_creg", "code": "__int64 __fastcall iwmmxt_load_creg ( int @@a1@@ ) { __int64 @@v2@@ ; @@v2@@ = tcg_temp_new_i32 ( ) ; tcg_gen_ld_i32 ( @@v2@@ , cpu_env , Number * ( @@a1@@ + Number L ) ) ; return @@v2@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "v2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "reg", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "var", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 860 |
[
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_ld_i32\", \"code\": \"__int64 __fastcall tcg_gen_ld_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "iwmmxt_store_creg", "code": "__int64 __fastcall iwmmxt_store_creg ( int @@a1@@ , __int64 @@a2@@ ) { tcg_gen_st_i32 ( @@a2@@ , cpu_env , Number * ( @@a1@@ + Number L ) ) ; return tcg_temp_free_i32 ( @@a2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "reg", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "var", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 861 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_gen_st_i32\", \"code\": \"__int64 __fastcall tcg_gen_st_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_movq_wRn_M0", "code": "__int64 __fastcall gen_op_iwmmxt_movq_wRn_M0 ( int @@a1@@ ) { return iwmmxt_store_reg ( cpu_M0 , @@a1@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 862 |
[
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"iwmmxt_store_reg\", \"code\": \"__int64 __fastcall iwmmxt_store_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_st_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_movq_M0_wRn", "code": "__int64 __fastcall gen_op_iwmmxt_movq_M0_wRn ( int @@a1@@ ) { return iwmmxt_load_reg ( cpu_M0 , @@a1@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 863 |
[
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_orq_M0_wRn", "code": "__int64 __fastcall gen_op_iwmmxt_orq_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return tcg_gen_or_i64 ( cpu_M0 , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 864 |
[
"{\"name\": \"tcg_gen_or_i64\", \"code\": \"__int64 __fastcall tcg_gen_or_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_andq_M0_wRn", "code": "__int64 __fastcall gen_op_iwmmxt_andq_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return tcg_gen_and_i64 ( cpu_M0 , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 865 |
[
"{\"name\": \"tcg_gen_and_i64\", \"code\": \"__int64 __fastcall tcg_gen_and_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_xorq_M0_wRn", "code": "__int64 __fastcall gen_op_iwmmxt_xorq_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return tcg_gen_xor_i64 ( cpu_M0 , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 866 |
[
"{\"name\": \"tcg_gen_xor_i64\", \"code\": \"__int64 __fastcall tcg_gen_xor_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_maddsq_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_maddsq_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_maddsq ( cpu_M0 , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 867 |
[
"{\"name\": \"gen_helper_iwmmxt_maddsq\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_maddsq ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_maddsq , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_madduq_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_madduq_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_madduq ( cpu_M0 , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 868 |
[
"{\"name\": \"gen_helper_iwmmxt_madduq\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_madduq ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_madduq , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_sadb_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_sadb_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_sadb ( cpu_M0 , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 869 |
[
"{\"name\": \"gen_helper_iwmmxt_sadb\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_sadb ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_sadb , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_sadw_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_sadw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_sadw ( cpu_M0 , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 870 |
[
"{\"name\": \"gen_helper_iwmmxt_sadw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_sadw ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_sadw , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_mulslw_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_mulslw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_mulslw ( cpu_M0 , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 871 |
[
"{\"name\": \"gen_helper_iwmmxt_mulslw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_mulslw ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_mulslw , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_mulshw_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_mulshw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_mulshw ( cpu_M0 , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 872 |
[
"{\"name\": \"gen_helper_iwmmxt_mulshw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_mulshw ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_mulshw , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_mululw_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_mululw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_mululw ( cpu_M0 , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 873 |
[
"{\"name\": \"gen_helper_iwmmxt_mululw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_mululw ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_mululw , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_muluhw_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_muluhw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_muluhw ( cpu_M0 , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 874 |
[
"{\"name\": \"gen_helper_iwmmxt_muluhw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_muluhw ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_muluhw , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_macsw_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_macsw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_macsw ( cpu_M0 , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 875 |
[
"{\"name\": \"gen_helper_iwmmxt_macsw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_macsw ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_macsw , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_macuw_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_macuw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_macuw ( cpu_M0 , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 876 |
[
"{\"name\": \"gen_helper_iwmmxt_macuw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_macuw ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; __int64 @@v6@@ [ Number ] ; unsigned __int64 @@v7@@ ; @@v7@@ = __readfsqword ( Number ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a2@@ ) ; @@v6@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v3@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_macuw , @@v3@@ , Number L , @@v6@@ ) ; return __readfsqword ( Number ) ^ @@v7@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v6\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_unpacklb_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_unpacklb_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_unpacklb ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 877 |
[
"{\"name\": \"gen_helper_iwmmxt_unpacklb\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_unpacklb ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_unpacklb , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_unpacklw_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_unpacklw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_unpacklw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 878 |
[
"{\"name\": \"gen_helper_iwmmxt_unpacklw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_unpacklw ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_unpacklw , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_unpackll_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_unpackll_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_unpackll ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 879 |
[
"{\"name\": \"gen_helper_iwmmxt_unpackll\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_unpackll ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_unpackll , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_unpackhb_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_unpackhb_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_unpackhb ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 880 |
[
"{\"name\": \"gen_helper_iwmmxt_unpackhb\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_unpackhb ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_unpackhb , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_unpackhw_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_unpackhw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_unpackhw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 881 |
[
"{\"name\": \"gen_helper_iwmmxt_unpackhw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_unpackhw ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_unpackhw , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_unpackhl_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_unpackhl_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_unpackhl ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 882 |
[
"{\"name\": \"gen_helper_iwmmxt_unpackhl\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_unpackhl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_unpackhl , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_cmpeqb_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_cmpeqb_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_cmpeqb ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 883 |
[
"{\"name\": \"gen_helper_iwmmxt_cmpeqb\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_cmpeqb ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_cmpeqb , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_cmpeqw_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_cmpeqw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_cmpeqw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 884 |
[
"{\"name\": \"gen_helper_iwmmxt_cmpeqw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_cmpeqw ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_cmpeqw , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_cmpeql_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_cmpeql_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_cmpeql ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 885 |
[
"{\"name\": \"gen_helper_iwmmxt_cmpeql\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_cmpeql ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_cmpeql , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_cmpgtub_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_cmpgtub_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_cmpgtub ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 886 |
[
"{\"name\": \"gen_helper_iwmmxt_cmpgtub\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_cmpgtub ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_cmpgtub , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_cmpgtuw_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_cmpgtuw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_cmpgtuw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 887 |
[
"{\"name\": \"gen_helper_iwmmxt_cmpgtuw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_cmpgtuw ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_cmpgtuw , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_cmpgtul_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_cmpgtul_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_cmpgtul ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 888 |
[
"{\"name\": \"gen_helper_iwmmxt_cmpgtul\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_cmpgtul ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_cmpgtul , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_cmpgtsb_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_cmpgtsb_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_cmpgtsb ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 889 |
[
"{\"name\": \"gen_helper_iwmmxt_cmpgtsb\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_cmpgtsb ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_cmpgtsb , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_cmpgtsw_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_cmpgtsw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_cmpgtsw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 890 |
[
"{\"name\": \"gen_helper_iwmmxt_cmpgtsw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_cmpgtsw ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_cmpgtsw , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_cmpgtsl_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_cmpgtsl_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_cmpgtsl ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 891 |
[
"{\"name\": \"gen_helper_iwmmxt_cmpgtsl\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_cmpgtsl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_cmpgtsl , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_minsb_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_minsb_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_minsb ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 892 |
[
"{\"name\": \"gen_helper_iwmmxt_minsb\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_minsb ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_minsb , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_minsw_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_minsw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_minsw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 893 |
[
"{\"name\": \"gen_helper_iwmmxt_minsw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_minsw ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_minsw , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_minsl_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_minsl_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_minsl ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 894 |
[
"{\"name\": \"gen_helper_iwmmxt_minsl\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_minsl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_minsl , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_minub_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_minub_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_minub ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 895 |
[
"{\"name\": \"gen_helper_iwmmxt_minub\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_minub ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_minub , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_minuw_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_minuw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_minuw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 896 |
[
"{\"name\": \"gen_helper_iwmmxt_minuw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_minuw ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_minuw , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_minul_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_minul_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_minul ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 897 |
[
"{\"name\": \"gen_helper_iwmmxt_minul\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_minul ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_minul , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_maxsb_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_maxsb_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_maxsb ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 898 |
[
"{\"name\": \"gen_helper_iwmmxt_maxsb\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_maxsb ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_maxsb , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_maxsw_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_maxsw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_maxsw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 899 |
[
"{\"name\": \"gen_helper_iwmmxt_maxsw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_maxsw ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_maxsw , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_maxsl_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_maxsl_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_maxsl ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 900 |
[
"{\"name\": \"gen_helper_iwmmxt_maxsl\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_maxsl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_maxsl , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_maxub_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_maxub_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_maxub ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 901 |
[
"{\"name\": \"gen_helper_iwmmxt_maxub\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_maxub ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_maxub , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_maxuw_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_maxuw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_maxuw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 902 |
[
"{\"name\": \"gen_helper_iwmmxt_maxuw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_maxuw ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_maxuw , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_maxul_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_maxul_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_maxul ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 903 |
[
"{\"name\": \"gen_helper_iwmmxt_maxul\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_maxul ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_maxul , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_subnb_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_subnb_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_subnb ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 904 |
[
"{\"name\": \"gen_helper_iwmmxt_subnb\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_subnb ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_subnb , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_subnw_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_subnw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_subnw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 905 |
[
"{\"name\": \"gen_helper_iwmmxt_subnw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_subnw ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_subnw , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_subnl_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_subnl_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_subnl ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 906 |
[
"{\"name\": \"gen_helper_iwmmxt_subnl\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_subnl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_subnl , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_addnb_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_addnb_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_addnb ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 907 |
[
"{\"name\": \"gen_helper_iwmmxt_addnb\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_addnb ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_addnb , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_addnw_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_addnw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_addnw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 908 |
[
"{\"name\": \"gen_helper_iwmmxt_addnw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_addnw ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_addnw , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_addnl_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_addnl_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_addnl ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 909 |
[
"{\"name\": \"gen_helper_iwmmxt_addnl\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_addnl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_addnl , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_subub_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_subub_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_subub ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 910 |
[
"{\"name\": \"gen_helper_iwmmxt_subub\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_subub ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_subub , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_subuw_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_subuw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_subuw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 911 |
[
"{\"name\": \"gen_helper_iwmmxt_subuw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_subuw ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_subuw , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_subul_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_subul_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_subul ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 912 |
[
"{\"name\": \"gen_helper_iwmmxt_subul\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_subul ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_subul , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_addub_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_addub_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_addub ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 913 |
[
"{\"name\": \"gen_helper_iwmmxt_addub\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_addub ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_addub , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_adduw_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_adduw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_adduw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 914 |
[
"{\"name\": \"gen_helper_iwmmxt_adduw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_adduw ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_adduw , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_addul_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_addul_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_addul ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 915 |
[
"{\"name\": \"gen_helper_iwmmxt_addul\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_addul ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_addul , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_subsb_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_subsb_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_subsb ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 916 |
[
"{\"name\": \"gen_helper_iwmmxt_subsb\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_subsb ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_subsb , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_subsw_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_subsw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_subsw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 917 |
[
"{\"name\": \"gen_helper_iwmmxt_subsw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_subsw ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_subsw , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_subsl_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_subsl_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_subsl ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 918 |
[
"{\"name\": \"gen_helper_iwmmxt_subsl\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_subsl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_subsl , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_addsb_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_addsb_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_addsb ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 919 |
[
"{\"name\": \"gen_helper_iwmmxt_addsb\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_addsb ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_addsb , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_op_iwmmxt_addsw_M0_wRn", "code": "unsigned __int64 __fastcall gen_op_iwmmxt_addsw_M0_wRn ( int @@a1@@ ) { iwmmxt_load_reg ( cpu_V1 , @@a1@@ ) ; return gen_helper_iwmmxt_addsw ( cpu_M0 , cpu_env , cpu_M0 , cpu_V1 ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]}
|
[{"n": "rn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 920 |
[
"{\"name\": \"gen_helper_iwmmxt_addsw\", \"code\": \"unsigned __int64 __fastcall gen_helper_iwmmxt_addsw ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i64_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i64_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_iwmmxt_addsw , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"iwmmxt_load_reg\", \"code\": \"__int64 __fastcall iwmmxt_load_reg ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , Number * ( @@a2@@ + Number L ) ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
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