input
stringlengths 144
489k
| output
stringlengths 45
339k
| shard
stringclasses 16
values | filename
stringlengths 135
135
| line_num
int64 0
2.62k
| context
list |
|---|---|---|---|---|---|
{"name": "arm_dc_feature", "code": "_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "char", "s": 1}, "location": "r64"}]}
|
[{"n": "dc", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "feature", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 621 |
[] |
{"name": "get_mem_index", "code": "__int64 __fastcall get_mem_index ( __int64 @@a1@@ ) { return arm_to_core_mmu_idx ( * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 622 |
[
"{\"name\": \"arm_to_core_mmu_idx\", \"code\": \"__int64 __fastcall arm_to_core_mmu_idx ( char @@a1@@ ) { return @@a1@@ & Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r56\"}]}"
] |
{"name": "default_exception_el", "code": "__int64 __fastcall default_exception_el ( __int64 @@a1@@ ) { __int64 @@result@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) == Number && * ( _BYTE * ) ( @@a1@@ + Number ) ) return Number L ; @@result@@ = * ( unsigned int * ) ( @@a1@@ + Number ) ; if ( ( int ) @@result@@ <= Number ) @@result@@ = Number L ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "result", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 623 |
[] |
{"name": "disas_set_insn_syndrome", "code": "__int64 __fastcall disas_set_insn_syndrome ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@result@@ ; if ( ! * ( _QWORD * ) ( @@a1@@ + Number ) ) _assert_fail ( String , String , Number , String ) ; tcg_set_insn_start_param ( * ( _QWORD * ) ( @@a1@@ + Number ) , Number , ( @@a2@@ & Number ) >> Number ) ; @@result@@ = @@a1@@ ; * ( _QWORD * ) ( @@a1@@ + Number ) = Number L ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "syn", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 624 |
[
"{\"name\": \"tcg_set_insn_start_param\", \"code\": \"__int64 __fastcall tcg_set_insn_start_param ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { return tcg_set_insn_param ( @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "get_ahp_flag", "code": "__int64 get_ahp_flag ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_i32 ( ) ; tcg_gen_ld_i32 ( @@v1@@ , cpu_env , Number L ) ; tcg_gen_extract_i32 ( @@v1@@ , @@v1@@ , Number L , Number L ) ; return @@v1@@ ; }", "source": [{"n": "v1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "ret", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 625 |
[
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_ld_i32\", \"code\": \"__int64 __fastcall tcg_gen_ld_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "clear_pstate_bits", "code": "__int64 __fastcall clear_pstate_bits ( int @@a1@@ ) { __int64 @@v2@@ ; @@v2@@ = tcg_temp_new_i32 ( ) ; tcg_gen_ld_i32 ( @@v2@@ , cpu_env , Number L ) ; tcg_gen_andi_i32 ( @@v2@@ , @@v2@@ , ( unsigned int ) ~ @@a1@@ ) ; tcg_gen_st_i32 ( @@v2@@ , cpu_env , Number L ) ; return tcg_temp_free_i32 ( @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "v2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "bits", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r56"}, {"n": "p", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 626 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_ld_i32\", \"code\": \"__int64 __fastcall tcg_gen_ld_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_st_i32\", \"code\": \"__int64 __fastcall tcg_gen_st_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "gen_ss_advance", "code": "__int64 __fastcall gen_ss_advance ( __int64 @@a1@@ ) { __int64 @@result@@ ; @@result@@ = * ( unsigned __int8 * ) ( @@a1@@ + Number ) ; if ( ( _BYTE ) @@result@@ ) { * ( _BYTE * ) ( @@a1@@ + Number ) = Number ; @@result@@ = clear_pstate_bits ( Number ) ; } return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 627 |
[
"{\"name\": \"clear_pstate_bits\", \"code\": \"__int64 __fastcall clear_pstate_bits ( int @@a1@@ ) { __int64 @@v2@@ ; @@v2@@ = tcg_temp_new_i32 ( ) ; tcg_gen_ld_i32 ( @@v2@@ , cpu_env , Number L ) ; tcg_gen_andi_i32 ( @@v2@@ , @@v2@@ , ( unsigned int ) ~ @@a1@@ ) ; tcg_gen_st_i32 ( @@v2@@ , cpu_env , Number L ) ; return tcg_temp_free_i32 ( @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_exception", "code": "__int64 __fastcall gen_exception ( unsigned int @@a1@@ , unsigned int @@a2@@ , unsigned int @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_const_i32 ( @@a1@@ ) ; @@v6@@ = tcg_const_i32 ( @@a2@@ ) ; @@v7@@ = tcg_const_i32 ( @@a3@@ ) ; gen_helper_exception_with_syndrome ( cpu_env , @@v5@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "target_el", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r16"}, {"n": "excp", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "syndrome", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r64"}, {"n": "tcg_syn", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "tcg_excp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s24"}, {"n": "tcg_el", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 628 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_helper_exception_with_syndrome\", \"code\": \"unsigned __int64 __fastcall gen_helper_exception_with_syndrome ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v7@@ [ Number ] ; unsigned __int64 @@v8@@ ; @@v8@@ = __readfsqword ( Number ) ; @@v7@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v7@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v7@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v7@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; tcg_gen_callN ( & helper_exception_with_syndrome , Number L , Number L , @@v7@@ ) ; return __readfsqword ( Number ) ^ @@v8@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 2, \"n\": 5, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s48\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_swstep_exception", "code": "__int64 __fastcall gen_swstep_exception ( __int64 @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned int @@v3@@ ; unsigned int @@v4@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) < * ( _DWORD * ) ( @@a1@@ + Number ) ) _assert_fail ( String , String , Number , String ) ; @@v3@@ = * ( _DWORD * ) ( @@a1@@ + Number ) ; @@v4@@ = syn_swstep ( @@v3@@ == * ( _DWORD * ) ( @@a1@@ + Number ) , @@a2@@ , @@a3@@ ) ; return gen_exception ( Number , @@v4@@ , @@v3@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "v3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r32"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r8"}]}
|
[{"n": "ex", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "v3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r32"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "isv", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 629 |
[
"{\"name\": \"syn_swstep\", \"code\": \"__int64 __fastcall syn_swstep ( int @@a1@@ , int @@a2@@ , int @@a3@@ ) { return ( @@a2@@ << Number ) | ( @@a1@@ << Number ) | ( @@a3@@ << Number ) | Number ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_exception\", \"code\": \"__int64 __fastcall gen_exception ( unsigned int @@a1@@ , unsigned int @@a2@@ , unsigned int @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_const_i32 ( @@a1@@ ) ; @@v6@@ = tcg_const_i32 ( @@a2@@ ) ; @@v7@@ = tcg_const_i32 ( @@a3@@ ) ; gen_helper_exception_with_syndrome ( cpu_env , @@v5@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_io_start", "code": "__int64 gen_io_start ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_const_i32 ( Number L ) ; tcg_gen_st_i32 ( @@v1@@ , cpu_env , Number ) ; return tcg_temp_free_i32 ( @@v1@@ ) ; }", "source": [{"n": "v1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 630 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_gen_st_i32\", \"code\": \"__int64 __fastcall tcg_gen_st_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "gen_io_end", "code": "__int64 gen_io_end ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_const_i32 ( Number L ) ; tcg_gen_st_i32 ( @@v1@@ , cpu_env , Number ) ; return tcg_temp_free_i32 ( @@v1@@ ) ; }", "source": [{"n": "v1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 631 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_gen_st_i32\", \"code\": \"__int64 __fastcall tcg_gen_st_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "arm_translate_init", "code": "__int64 arm_translate_init ( ) { int @@i@@ ; for ( @@i@@ = Number ; @@i@@ <= Number ; ++ @@i@@ ) cpu_R [ @@i@@ ] = tcg_global_mem_new_i32 ( cpu_env , Number L * @@i@@ , ( __int64 ) regnames [ @@i@@ ] ) ; cpu_CF = tcg_global_mem_new_i32 ( cpu_env , Number L , ( __int64 ) String ) ; cpu_NF = tcg_global_mem_new_i32 ( cpu_env , Number L , ( __int64 ) String ) ; cpu_VF = tcg_global_mem_new_i32 ( cpu_env , Number L , ( __int64 ) String ) ; cpu_ZF = tcg_global_mem_new_i32 ( cpu_env , Number L , ( __int64 ) String ) ; cpu_exclusive_addr = tcg_global_mem_new_i64 ( cpu_env , Number L , ( __int64 ) String ) ; cpu_exclusive_val = tcg_global_mem_new_i64 ( cpu_env , Number L , ( __int64 ) String ) ; return a64_translate_init ( ) ; }", "source": [{"n": "i", "t": {"T": 1, "n": "int", "s": 4}, "location": "s4"}]}
|
[{"n": "i", "t": {"T": 1, "n": "int", "s": 4}, "location": "s4"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 632 |
[
"{\"name\": \"tcg_global_mem_new_i32\", \"code\": \"__int64 __fastcall tcg_global_mem_new_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v4@@ ; @@v4@@ = tcg_global_mem_new_internal ( Number L , @@a1@@ , @@a2@@ , @@a3@@ ) ; return temp_tcgv_i32 ( @@v4@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_global_mem_new_i64\", \"code\": \"__int64 __fastcall tcg_global_mem_new_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v4@@ ; @@v4@@ = tcg_global_mem_new_internal ( Number L , @@a1@@ , @@a2@@ , @@a3@@ ) ; return temp_tcgv_i64 ( @@v4@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "disas_set_da_iss", "code": "__int64 __fastcall disas_set_da_iss ( __int64 @@a1@@ , char @@a2@@ , __int16 @@a3@@ ) { __int64 @@result@@ ; int @@v4@@ ; int @@v5@@ ; @@v4@@ = @@a3@@ & Number ; @@result@@ = @@a3@@ & Number ; if ( ( @@a3@@ & Number ) == Number && @@v4@@ != Number ) { @@v5@@ = syn_data_abort_with_iss ( Number , @@a2@@ & Number , ( @@a2@@ & Number ) != Number , @@v4@@ , Number , ( @@a3@@ & Number ) != Number , Number , Number , Number , ( @@a3@@ & Number ) != Number , Number , ( @@a3@@ & Number ) != Number ) ; @@result@@ = disas_set_insn_syndrome ( @@a1@@ , @@v5@@ ) ; } return @@result@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int16", "s": 2}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "char", "s": 1}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}, {"n": "v5", "t": {"T": 1, "n": "int", "s": 4}, "location": "s4"}, {"n": "v4", "t": {"T": 1, "n": "int", "s": 4}, "location": "s8"}]}
|
[{"n": "issinfo", "t": {"T": 1, "n": "ISSInfo_0", "s": 4}, "location": "r16"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "memop", "t": {"T": 1, "n": "MemOp_0", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}, {"n": "syn", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "s4"}, {"n": "srt", "t": {"T": 1, "n": "__int32", "s": 4}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 633 |
[
"{\"name\": \"syn_data_abort_with_iss\", \"code\": \"__int64 __fastcall syn_data_abort_with_iss ( int @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ , int @@a5@@ , int @@a6@@ , int @@a7@@ , int @@a8@@ , int @@a9@@ , int @@a10@@ , int @@a11@@ , char @@a12@@ ) { int v12 ; if ( @@a12@@ ) v12 = Number ; else v12 = Number ; return @@a11@@ | ( @@a9@@ << Number ) | ( @@a8@@ << Number ) | ( @@a7@@ << Number ) | ( @@a6@@ << Number ) | ( @@a5@@ << Number ) | ( @@a4@@ << Number ) | ( @@a3@@ << Number ) | ( @@a2@@ << Number ) | ( @@a1@@ << Number ) | v12 | ( @@a10@@ << Number ) | Number ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"a6\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r80\"}, {\"n\": \"a7\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s-16\"}, {\"n\": \"a8\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s-24\"}, {\"n\": \"a9\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s-32\"}, {\"n\": \"a10\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s-40\"}, {\"n\": \"a11\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s-48\"}, {\"n\": \"a12\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"s-56\"}]}",
"{\"name\": \"disas_set_insn_syndrome\", \"code\": \"__int64 __fastcall disas_set_insn_syndrome ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@result@@ ; if ( ! * ( _QWORD * ) ( @@a1@@ + Number ) ) _assert_fail ( String , String , Number , String ) ; tcg_set_insn_start_param ( * ( _QWORD * ) ( @@a1@@ + Number ) , Number , ( @@a2@@ & Number ) >> Number ) ; @@result@@ = @@a1@@ ; * ( _QWORD * ) ( @@a1@@ + Number ) = Number L ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "get_a32_user_mem_index", "code": "__int64 __fastcall get_a32_user_mem_index ( __int64 @@a1@@ ) { __int64 @@result@@ ; switch ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; case Number : case Number : @@result@@ = arm_to_core_mmu_idx ( Number ) ; break ; default : @@result@@ = g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; break ; } return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "result", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 634 |
[
"{\"name\": \"arm_to_core_mmu_idx\", \"code\": \"__int64 __fastcall arm_to_core_mmu_idx ( char @@a1@@ ) { return @@a1@@ & Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r56\"}]}"
] |
{"name": "load_cpu_offset", "code": "__int64 __fastcall load_cpu_offset ( int @@a1@@ ) { __int64 @@v2@@ ; @@v2@@ = tcg_temp_new_i32 ( ) ; tcg_gen_ld_i32 ( @@v2@@ , cpu_env , @@a1@@ ) ; return @@v2@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "v2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "offset", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 635 |
[
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_ld_i32\", \"code\": \"__int64 __fastcall tcg_gen_ld_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "store_cpu_offset", "code": "__int64 __fastcall store_cpu_offset ( __int64 @@a1@@ , int @@a2@@ ) { tcg_gen_st_i32 ( @@a1@@ , cpu_env , @@a2@@ ) ; return tcg_temp_free_i32 ( @@a1@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}]}
|
[{"n": "var", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "offset", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 636 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_gen_st_i32\", \"code\": \"__int64 __fastcall tcg_gen_st_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "read_pc", "code": "__int64 __fastcall read_pc ( __int64 @@a1@@ ) { int @@v1@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v1@@ = Number ; else @@v1@@ = Number ; return ( unsigned int ) * ( _QWORD * ) ( @@a1@@ + Number ) + @@v1@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "v1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "v1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 637 |
[] |
{"name": "load_reg_var", "code": "__int64 __fastcall load_reg_var ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ ) { int @@v3@@ ; if ( @@a3@@ != Number ) return tcg_gen_mov_i32 ( @@a2@@ , cpu_R [ @@a3@@ ] ) ; @@v3@@ = read_pc ( @@a1@@ ) ; return tcg_gen_movi_i32 ( @@a2@@ , @@v3@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}]}
|
[{"n": "reg", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "var", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 638 |
[
"{\"name\": \"tcg_gen_mov_i32\", \"code\": \"__int64 __fastcall tcg_gen_mov_i32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@result@@ ; @@result@@ = @@a1@@ ; if ( @@a1@@ != @@a2@@ ) @@result@@ = tcg_gen_op2_i32 ( Number , @@a1@@ , @@a2@@ ) ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_gen_movi_i32\", \"code\": \"__int64 __fastcall tcg_gen_movi_i32 ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_op2i_i32 ( Number , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"read_pc\", \"code\": \"__int64 __fastcall read_pc ( __int64 @@a1@@ ) { int @@v1@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v1@@ = Number ; else @@v1@@ = Number ; return ( unsigned int ) * ( _QWORD * ) ( @@a1@@ + Number ) + @@v1@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "load_reg", "code": "__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "reg", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 639 |
[
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg_var\", \"code\": \"__int64 __fastcall load_reg_var ( __int64 @@a1@@ , __int64 @@a2@@ , int @@a3@@ ) { int @@v3@@ ; if ( @@a3@@ != Number ) return tcg_gen_mov_i32 ( @@a2@@ , cpu_R [ @@a3@@ ] ) ; @@v3@@ = read_pc ( @@a1@@ ) ; return tcg_gen_movi_i32 ( @@a2@@ , @@v3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}"
] |
{"name": "add_reg_for_lit", "code": "__int64 __fastcall add_reg_for_lit ( __int64 @@a1@@ , int @@a2@@ , unsigned int @@a3@@ ) { int @@v3@@ ; __int64 @@v6@@ ; @@v6@@ = tcg_temp_new_i32 ( ) ; if ( @@a2@@ == Number ) { @@v3@@ = read_pc ( @@a1@@ ) ; tcg_gen_movi_i32 ( @@v6@@ , ( @@v3@@ & Number ) + @@a3@@ ) ; } else { tcg_gen_addi_i32 ( @@v6@@ , cpu_R [ @@a2@@ ] , @@a3@@ ) ; } return @@v6@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r8"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "ofs", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "reg", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 640 |
[
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_movi_i32\", \"code\": \"__int64 __fastcall tcg_gen_movi_i32 ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_op2i_i32 ( Number , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"read_pc\", \"code\": \"__int64 __fastcall read_pc ( __int64 @@a1@@ ) { int @@v1@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) @@v1@@ = Number ; else @@v1@@ = Number ; return ( unsigned int ) * ( _QWORD * ) ( @@a1@@ + Number ) + @@v1@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r8\"}]}"
] |
{"name": "store_reg", "code": "__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}]}
|
[{"n": "var", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "reg", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 641 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_gen_mov_i32\", \"code\": \"__int64 __fastcall tcg_gen_mov_i32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@result@@ ; @@result@@ = @@a1@@ ; if ( @@a1@@ != @@a2@@ ) @@result@@ = tcg_gen_op2_i32 ( Number , @@a1@@ , @@a2@@ ) ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "store_sp_checked", "code": "__int64 __fastcall store_sp_checked ( __int64 @@a1@@ , __int64 @@a2@@ ) { if ( * ( _BYTE * ) ( @@a1@@ + Number ) ) gen_helper_v8m_stackcheck ( cpu_env , @@a2@@ ) ; return store_reg ( @@a1@@ , Number , @@a2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "var", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 642 |
[
"{\"name\": \"gen_helper_v8m_stackcheck\", \"code\": \"unsigned __int64 __fastcall gen_helper_v8m_stackcheck ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v3@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; tcg_gen_callN ( & helper_v8m_stackcheck , Number L , Number L , @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_set_cpsr", "code": "__int64 __fastcall gen_set_cpsr ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_const_i32 ( @@a2@@ ) ; gen_helper_cpsr_write ( cpu_env , @@a1@@ , @@v3@@ ) ; return tcg_temp_free_i32 ( @@v3@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "var", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "mask", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r64"}, {"n": "tmp_mask", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 643 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_helper_cpsr_write\", \"code\": \"unsigned __int64 __fastcall gen_helper_cpsr_write ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ [ Number ] ; unsigned __int64 @@v6@@ ; @@v6@@ = __readfsqword ( Number ) ; @@v5@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v5@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; @@v5@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; tcg_gen_callN ( & helper_cpsr_write , Number L , Number L , @@v5@@ ) ; return __readfsqword ( Number ) ^ @@v6@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_exception_internal", "code": "__int64 __fastcall gen_exception_internal ( unsigned int @@a1@@ ) { __int64 @@v2@@ ; @@v2@@ = tcg_const_i32 ( @@a1@@ ) ; if ( ! excp_is_internal ( @@a1@@ ) ) _assert_fail ( String , String , Number , String ) ; gen_helper_exception_internal ( cpu_env , @@v2@@ ) ; return tcg_temp_free_i32 ( @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "v2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "excp", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "tcg_excp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 644 |
[
"{\"name\": \"excp_is_internal\", \"code\": \"_BOOL8 __fastcall excp_is_internal ( int @@a1@@ ) { return @@a1@@ == Number || @@a1@@ == Number || @@a1@@ == Number || @@a1@@ == Number || @@a1@@ == Number || @@a1@@ == Number || @@a1@@ == Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_helper_exception_internal\", \"code\": \"unsigned __int64 __fastcall gen_helper_exception_internal ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v3@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; tcg_gen_callN ( & helper_exception_internal , Number L , Number L , @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_exception\", \"code\": \"__int64 __fastcall gen_exception ( unsigned int @@a1@@ , unsigned int @@a2@@ , unsigned int @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_const_i32 ( @@a1@@ ) ; @@v6@@ = tcg_const_i32 ( @@a2@@ ) ; @@v7@@ = tcg_const_i32 ( @@a3@@ ) ; gen_helper_exception_with_syndrome ( cpu_env , @@v5@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_step_complete_exception", "code": "__int64 __fastcall gen_step_complete_exception ( __int64 @@a1@@ ) { __int64 @@result@@ ; gen_ss_advance ( @@a1@@ ) ; gen_swstep_exception ( @@a1@@ , Number , * ( unsigned __int8 * ) ( @@a1@@ + Number ) ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 645 |
[
"{\"name\": \"gen_ss_advance\", \"code\": \"__int64 __fastcall gen_ss_advance ( __int64 @@a1@@ ) { __int64 @@result@@ ; @@result@@ = * ( unsigned __int8 * ) ( @@a1@@ + Number ) ; if ( ( _BYTE ) @@result@@ ) { * ( _BYTE * ) ( @@a1@@ + Number ) = Number ; @@result@@ = clear_pstate_bits ( Number ) ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_swstep_exception\", \"code\": \"__int64 __fastcall gen_swstep_exception ( __int64 @@a1@@ , int @@a2@@ , int @@a3@@ ) { unsigned int @@v3@@ ; unsigned int @@v4@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) < * ( _DWORD * ) ( @@a1@@ + Number ) ) _assert_fail ( String , String , Number , String ) ; @@v3@@ = * ( _DWORD * ) ( @@a1@@ + Number ) ; @@v4@@ = syn_swstep ( @@v3@@ == * ( _DWORD * ) ( @@a1@@ + Number ) , @@a2@@ , @@a3@@ ) ; return gen_exception ( Number , @@v4@@ , @@v3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}"
] |
{"name": "gen_singlestep_exception", "code": "__int64 __fastcall gen_singlestep_exception ( __int64 @@a1@@ ) { __int64 @@result@@ ; if ( * ( _BYTE * ) ( @@a1@@ + Number ) ) @@result@@ = gen_step_complete_exception ( @@a1@@ ) ; else @@result@@ = gen_exception_internal ( Number ) ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 646 |
[
"{\"name\": \"gen_exception\", \"code\": \"__int64 __fastcall gen_exception ( unsigned int @@a1@@ , unsigned int @@a2@@ , unsigned int @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_const_i32 ( @@a1@@ ) ; @@v6@@ = tcg_const_i32 ( @@a2@@ ) ; @@v7@@ = tcg_const_i32 ( @@a3@@ ) ; gen_helper_exception_with_syndrome ( cpu_env , @@v5@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_exception_internal\", \"code\": \"__int64 __fastcall gen_exception_internal ( unsigned int @@a1@@ ) { __int64 @@v2@@ ; @@v2@@ = tcg_const_i32 ( @@a1@@ ) ; if ( ! excp_is_internal ( @@a1@@ ) ) _assert_fail ( String , String , Number , String ) ; gen_helper_exception_internal ( cpu_env , @@v2@@ ) ; return tcg_temp_free_i32 ( @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_step_complete_exception\", \"code\": \"__int64 __fastcall gen_step_complete_exception ( __int64 @@a1@@ ) { __int64 @@result@@ ; gen_ss_advance ( @@a1@@ ) ; gen_swstep_exception ( @@a1@@ , Number , * ( unsigned __int8 * ) ( @@a1@@ + Number ) ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "is_singlestepping", "code": "_BOOL8 __fastcall is_singlestepping ( __int64 @@a1@@ ) { return * ( _BYTE * ) ( @@a1@@ + Number ) || * ( _BYTE * ) ( @@a1@@ + Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 647 |
[] |
{"name": "gen_smul_dual", "code": "__int64 __fastcall gen_smul_dual ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v4@@ ; __int64 @@v5@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_ext16s_i32 ( @@v4@@ , @@a1@@ ) ; tcg_gen_ext16s_i32 ( @@v5@@ , @@a2@@ ) ; tcg_gen_mul_i32 ( @@v4@@ , @@v4@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; tcg_gen_sari_i32 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_sari_i32 ( @@a2@@ , @@a2@@ , Number L ) ; tcg_gen_mul_i32 ( @@a2@@ , @@a2@@ , @@a1@@ ) ; tcg_gen_mov_i32 ( @@a1@@ , @@v4@@ ) ; return tcg_temp_free_i32 ( @@v4@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "a", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "b", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}, {"n": "tmp1", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "tmp2", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 648 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_mov_i32\", \"code\": \"__int64 __fastcall tcg_gen_mov_i32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@result@@ ; @@result@@ = @@a1@@ ; if ( @@a1@@ != @@a2@@ ) @@result@@ = tcg_gen_op2_i32 ( Number , @@a1@@ , @@a2@@ ) ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_gen_mul_i32\", \"code\": \"__int64 __fastcall tcg_gen_mul_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_sar\", \"code\": \"__int64 __fastcall gen_sar ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v5@@ , @@v5@@ , @@v6@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; tcg_gen_sar_i32 ( @@a1@@ , @@a2@@ , @@v5@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_rev16", "code": "__int64 __fastcall gen_rev16 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v4@@ ; __int64 @@v5@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v5@@ = tcg_const_i32 ( Number L ) ; tcg_gen_shri_i32 ( @@v4@@ , @@a2@@ , Number L ) ; tcg_gen_and_i32 ( @@v4@@ , @@v4@@ , @@v5@@ ) ; tcg_gen_and_i32 ( @@a2@@ , @@a2@@ , @@v5@@ ) ; tcg_gen_shli_i32 ( @@a2@@ , @@a2@@ , Number L ) ; tcg_gen_or_i32 ( @@a1@@ , @@a2@@ , @@v4@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; return tcg_temp_free_i32 ( @@v4@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "dest", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "var", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "mask", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 649 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_and_i32\", \"code\": \"__int64 __fastcall tcg_gen_and_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_or_i32\", \"code\": \"__int64 __fastcall tcg_gen_or_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_shl\", \"code\": \"__int64 __fastcall gen_shl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shl_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_shr\", \"code\": \"__int64 __fastcall gen_shr ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shr_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_revsh", "code": "__int64 __fastcall gen_revsh ( __int64 @@a1@@ , __int64 @@a2@@ ) { tcg_gen_ext16u_i32 ( @@a2@@ , @@a2@@ ) ; tcg_gen_bswap16_i32 ( @@a2@@ , @@a2@@ ) ; return tcg_gen_ext16s_i32 ( @@a1@@ , @@a2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "dest", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "var", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 650 |
[
"{\"name\": \"bswap16\", \"code\": \"__int16 __fastcall bswap16 ( __int16 @@a1@@ ) { return _bswap_16 ( @@a1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int16\", \"s\": 2}, \"location\": \"r56\"}]}"
] |
{"name": "gen_mulu_i64_i32", "code": "__int64 __fastcall gen_mulu_i64_i32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; __int64 @@v5@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; @@v4@@ = tcg_temp_new_i32 ( ) ; tcg_gen_mulu2_i32 ( @@v3@@ , @@v4@@ , @@a1@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@a1@@ ) ; tcg_temp_free_i32 ( @@a2@@ ) ; @@v5@@ = tcg_temp_new_i64 ( ) ; tcg_gen_concat_i32_i64 ( @@v5@@ , @@v3@@ , @@v4@@ ) ; tcg_temp_free_i32 ( @@v3@@ ) ; tcg_temp_free_i32 ( @@v4@@ ) ; return @@v5@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "a", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "b", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s16"}, {"n": "lo", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s24"}, {"n": "ret", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 651 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_temp_new_i64\", \"code\": \"__int64 tcg_temp_new_i64 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i64 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_muls_i64_i32", "code": "__int64 __fastcall gen_muls_i64_i32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ ; __int64 @@v4@@ ; __int64 @@v5@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; @@v4@@ = tcg_temp_new_i32 ( ) ; tcg_gen_muls2_i32 ( @@v3@@ , @@v4@@ , @@a1@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@a1@@ ) ; tcg_temp_free_i32 ( @@a2@@ ) ; @@v5@@ = tcg_temp_new_i64 ( ) ; tcg_gen_concat_i32_i64 ( @@v5@@ , @@v3@@ , @@v4@@ ) ; tcg_temp_free_i32 ( @@v3@@ ) ; tcg_temp_free_i32 ( @@v4@@ ) ; return @@v5@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "a", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "b", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "s16"}, {"n": "lo", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s24"}, {"n": "ret", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 652 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_temp_new_i64\", \"code\": \"__int64 tcg_temp_new_i64 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i64 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_swap_half", "code": "__int64 __fastcall gen_swap_half ( __int64 @@a1@@ ) { return tcg_gen_rotri_i32 ( @@a1@@ , @@a1@@ , Number L ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}]}
|
[{"n": "var", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 653 |
[] |
{"name": "gen_add16", "code": "__int64 __fastcall gen_add16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v6@@ ; @@v6@@ = tcg_temp_new_i32 ( ) ; tcg_gen_xor_i32 ( @@v6@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_andi_i32 ( @@v6@@ , @@v6@@ , Number ) ; tcg_gen_andi_i32 ( @@a2@@ , @@a2@@ , Number L ) ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , Number L ) ; tcg_gen_add_i32 ( @@a2@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_xor_i32 ( @@a1@@ , @@a2@@ , @@v6@@ ) ; return tcg_temp_free_i32 ( @@v6@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "t1", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "dest", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "t0", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 654 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_add_i32\", \"code\": \"__int64 __fastcall tcg_gen_add_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_xor_i32\", \"code\": \"__int64 __fastcall tcg_gen_xor_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "gen_logic_CC", "code": "__int64 __fastcall gen_logic_CC ( __int64 @@a1@@ ) { tcg_gen_mov_i32 ( cpu_NF , @@a1@@ ) ; return tcg_gen_mov_i32 ( cpu_ZF , @@a1@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}]}
|
[{"n": "var", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 655 |
[
"{\"name\": \"tcg_gen_mov_i32\", \"code\": \"__int64 __fastcall tcg_gen_mov_i32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@result@@ ; @@result@@ = @@a1@@ ; if ( @@a1@@ != @@a2@@ ) @@result@@ = tcg_gen_op2_i32 ( Number , @@a1@@ , @@a2@@ ) ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "gen_add_carry", "code": "__int64 __fastcall gen_add_carry ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { tcg_gen_add_i32 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; return tcg_gen_add_i32 ( @@a1@@ , @@a1@@ , cpu_CF ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "t1", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "dest", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "t0", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 656 |
[
"{\"name\": \"tcg_gen_add_i32\", \"code\": \"__int64 __fastcall tcg_gen_add_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "gen_sub_carry", "code": "__int64 __fastcall gen_sub_carry ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { tcg_gen_sub_i32 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_add_i32 ( @@a1@@ , @@a1@@ , cpu_CF ) ; return tcg_gen_subi_i32 ( @@a1@@ , @@a1@@ , Number L ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "t1", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "dest", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "t0", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 657 |
[
"{\"name\": \"tcg_gen_add_i32\", \"code\": \"__int64 __fastcall tcg_gen_add_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_sub_i32\", \"code\": \"__int64 __fastcall tcg_gen_sub_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "gen_add_CC", "code": "__int64 __fastcall gen_add_CC ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_movi_i32 ( @@v5@@ , Number ) ; tcg_gen_add2_i32 ( cpu_NF , cpu_CF , @@a2@@ , @@v5@@ , @@a3@@ , @@v5@@ ) ; tcg_gen_mov_i32 ( cpu_ZF , cpu_NF ) ; tcg_gen_xor_i32 ( cpu_VF , cpu_NF , @@a2@@ ) ; tcg_gen_xor_i32 ( @@v5@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_andc_i32 ( cpu_VF , cpu_VF , @@v5@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; return tcg_gen_mov_i32 ( @@a1@@ , cpu_NF ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "t1", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "dest", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "t0", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 658 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_mov_i32\", \"code\": \"__int64 __fastcall tcg_gen_mov_i32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@result@@ ; @@result@@ = @@a1@@ ; if ( @@a1@@ != @@a2@@ ) @@result@@ = tcg_gen_op2_i32 ( Number , @@a1@@ , @@a2@@ ) ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_gen_movi_i32\", \"code\": \"__int64 __fastcall tcg_gen_movi_i32 ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_op2i_i32 ( Number , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_xor_i32\", \"code\": \"__int64 __fastcall tcg_gen_xor_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "gen_adc_CC", "code": "__int64 __fastcall gen_adc_CC ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_movi_i32 ( @@v5@@ , Number ) ; tcg_gen_add2_i32 ( cpu_NF , cpu_CF , @@a2@@ , @@v5@@ , cpu_CF , @@v5@@ ) ; tcg_gen_add2_i32 ( cpu_NF , cpu_CF , cpu_NF , cpu_CF , @@a3@@ , @@v5@@ ) ; tcg_gen_mov_i32 ( cpu_ZF , cpu_NF ) ; tcg_gen_xor_i32 ( cpu_VF , cpu_NF , @@a2@@ ) ; tcg_gen_xor_i32 ( @@v5@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_andc_i32 ( cpu_VF , cpu_VF , @@v5@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; return tcg_gen_mov_i32 ( @@a1@@ , cpu_NF ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "t1", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "dest", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "t0", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 659 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_mov_i32\", \"code\": \"__int64 __fastcall tcg_gen_mov_i32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@result@@ ; @@result@@ = @@a1@@ ; if ( @@a1@@ != @@a2@@ ) @@result@@ = tcg_gen_op2_i32 ( Number , @@a1@@ , @@a2@@ ) ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_gen_movi_i32\", \"code\": \"__int64 __fastcall tcg_gen_movi_i32 ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_op2i_i32 ( Number , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_xor_i32\", \"code\": \"__int64 __fastcall tcg_gen_xor_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "gen_sub_CC", "code": "__int64 __fastcall gen_sub_CC ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; tcg_gen_sub_i32 ( cpu_NF , @@a2@@ , @@a3@@ ) ; tcg_gen_mov_i32 ( cpu_ZF , cpu_NF ) ; tcg_gen_setcond_i32 ( Number L , cpu_CF , @@a2@@ , @@a3@@ ) ; tcg_gen_xor_i32 ( cpu_VF , cpu_NF , @@a2@@ ) ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_xor_i32 ( @@v5@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_and_i32 ( cpu_VF , cpu_VF , @@v5@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; return tcg_gen_mov_i32 ( @@a1@@ , cpu_NF ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "t1", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "dest", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "t0", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 660 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_mov_i32\", \"code\": \"__int64 __fastcall tcg_gen_mov_i32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@result@@ ; @@result@@ = @@a1@@ ; if ( @@a1@@ != @@a2@@ ) @@result@@ = tcg_gen_op2_i32 ( Number , @@a1@@ , @@a2@@ ) ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_gen_sub_i32\", \"code\": \"__int64 __fastcall tcg_gen_sub_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_and_i32\", \"code\": \"__int64 __fastcall tcg_gen_and_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_xor_i32\", \"code\": \"__int64 __fastcall tcg_gen_xor_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "gen_sbc_CC", "code": "__int64 __fastcall gen_sbc_CC ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_not_i32 ( @@v5@@ , @@a3@@ ) ; gen_adc_CC ( @@a1@@ , @@a2@@ , @@v5@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "t1", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "dest", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "t0", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 661 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_not_i32\", \"code\": \"__int64 __fastcall tcg_gen_not_i32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { return tcg_gen_op2_i32 ( Number , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_adc_CC\", \"code\": \"__int64 __fastcall gen_adc_CC ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_movi_i32 ( @@v5@@ , Number ) ; tcg_gen_add2_i32 ( cpu_NF , cpu_CF , @@a2@@ , @@v5@@ , cpu_CF , @@v5@@ ) ; tcg_gen_add2_i32 ( cpu_NF , cpu_CF , cpu_NF , cpu_CF , @@a3@@ , @@v5@@ ) ; tcg_gen_mov_i32 ( cpu_ZF , cpu_NF ) ; tcg_gen_xor_i32 ( cpu_VF , cpu_NF , @@a2@@ ) ; tcg_gen_xor_i32 ( @@v5@@ , @@a2@@ , @@a3@@ ) ; tcg_gen_andc_i32 ( cpu_VF , cpu_VF , @@v5@@ ) ; tcg_temp_free_i32 ( @@v5@@ ) ; return tcg_gen_mov_i32 ( @@a1@@ , cpu_NF ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_shl", "code": "__int64 __fastcall gen_shl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shl_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "t1", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "dest", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "t0", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}, {"n": "tmp2", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "tmp1", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s24"}, {"n": "tmp3", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 662 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_shl_i32\", \"code\": \"__int64 __fastcall tcg_gen_shl_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "gen_shr", "code": "__int64 __fastcall gen_shr ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shr_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s24"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "t1", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "dest", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "t0", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}, {"n": "tmp2", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "tmp1", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s24"}, {"n": "tmp3", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 663 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_shr_i32\", \"code\": \"__int64 __fastcall tcg_gen_shr_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "gen_sar", "code": "__int64 __fastcall gen_sar ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v5@@ , @@v5@@ , @@v6@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; tcg_gen_sar_i32 ( @@a1@@ , @@a2@@ , @@v5@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "t1", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "dest", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "t0", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}, {"n": "tmp1", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s16"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 664 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_sar_i32\", \"code\": \"__int64 __fastcall tcg_gen_sar_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "shifter_out_im", "code": "__int64 __fastcall shifter_out_im ( __int64 @@a1@@ , unsigned int @@a2@@ ) { return tcg_gen_extract_i32 ( cpu_CF , @@a1@@ , @@a2@@ , Number L ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}]}
|
[{"n": "var", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "shift", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 665 |
[] |
{"name": "gen_arm_shift_im", "code": "void __fastcall gen_arm_shift_im ( __int64 @@a1@@ , int @@a2@@ , unsigned int @@a3@@ , int @@a4@@ ) { unsigned int @@v5@@ ; __int64 @@v6@@ ; @@v5@@ = @@a3@@ ; if ( @@a2@@ == Number ) { if ( @@a3@@ ) { if ( @@a4@@ ) shifter_out_im ( @@a1@@ , @@a3@@ - Number ) ; tcg_gen_rotri_i32 ( @@a1@@ , @@a1@@ , @@v5@@ ) ; } else { @@v6@@ = tcg_temp_new_i32 ( ) ; tcg_gen_shli_i32 ( @@v6@@ , cpu_CF , Number L ) ; if ( @@a4@@ ) shifter_out_im ( @@a1@@ , Number ) ; tcg_gen_shri_i32 ( @@a1@@ , @@a1@@ , Number L ) ; tcg_gen_or_i32 ( @@a1@@ , @@a1@@ , @@v6@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; } } else if ( @@a2@@ <= Number ) { if ( @@a2@@ == Number ) { if ( ! @@a3@@ ) @@v5@@ = Number ; if ( @@a4@@ ) shifter_out_im ( @@a1@@ , @@v5@@ - Number ) ; if ( @@v5@@ == Number ) @@v5@@ = Number ; tcg_gen_sari_i32 ( @@a1@@ , @@a1@@ , @@v5@@ ) ; } else if ( @@a2@@ ) { if ( @@a2@@ == Number ) { if ( @@a3@@ ) { if ( @@a4@@ ) shifter_out_im ( @@a1@@ , @@a3@@ - Number ) ; tcg_gen_shri_i32 ( @@a1@@ , @@a1@@ , @@v5@@ ) ; } else { if ( @@a4@@ ) tcg_gen_shri_i32 ( cpu_CF , @@a1@@ , Number L ) ; tcg_gen_movi_i32 ( @@a1@@ , Number ) ; } } } else if ( @@a3@@ ) { if ( @@a4@@ ) shifter_out_im ( @@a1@@ , Number - @@a3@@ ) ; tcg_gen_shli_i32 ( @@a1@@ , @@a1@@ , @@v5@@ ) ; } } }", "source": [{"n": "a3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v5", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s32"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "shift", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "flags", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "var", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "shiftop", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "shifta", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s32"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 666 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_movi_i32\", \"code\": \"__int64 __fastcall tcg_gen_movi_i32 ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_op2i_i32 ( Number , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_or_i32\", \"code\": \"__int64 __fastcall tcg_gen_or_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_shl\", \"code\": \"__int64 __fastcall gen_shl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shl_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_shr\", \"code\": \"__int64 __fastcall gen_shr ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shr_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_sar\", \"code\": \"__int64 __fastcall gen_sar ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v5@@ , @@v5@@ , @@v6@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; tcg_gen_sar_i32 ( @@a1@@ , @@a2@@ , @@v5@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"shifter_out_im\", \"code\": \"__int64 __fastcall shifter_out_im ( __int64 @@a1@@ , unsigned int @@a2@@ ) { return tcg_gen_extract_i32 ( cpu_CF , @@a1@@ , @@a2@@ , Number L ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_arm_shift_reg", "code": "__int64 __fastcall gen_arm_shift_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { if ( @@a4@@ ) { if ( @@a2@@ == Number ) { gen_helper_ror_cc ( @@a1@@ , cpu_env , @@a1@@ , @@a3@@ ) ; } else if ( @@a2@@ <= Number ) { if ( @@a2@@ == Number ) { gen_helper_sar_cc ( @@a1@@ , cpu_env , @@a1@@ , @@a3@@ ) ; } else if ( @@a2@@ ) { if ( @@a2@@ == Number ) gen_helper_shr_cc ( @@a1@@ , cpu_env , @@a1@@ , @@a3@@ ) ; } else { gen_helper_shl_cc ( @@a1@@ , cpu_env , @@a1@@ , @@a3@@ ) ; } } } else if ( @@a2@@ == Number ) { tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , Number L ) ; tcg_gen_rotr_i32 ( @@a1@@ , @@a1@@ , @@a3@@ ) ; } else if ( @@a2@@ <= Number ) { if ( @@a2@@ == Number ) { gen_sar ( @@a1@@ , @@a1@@ , @@a3@@ ) ; } else if ( @@a2@@ ) { if ( @@a2@@ == Number ) gen_shr ( @@a1@@ , @@a1@@ , @@a3@@ ) ; } else { gen_shl ( @@a1@@ , @@a1@@ , @@a3@@ ) ; } } return tcg_temp_free_i32 ( @@a3@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}]}
|
[{"n": "shift", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "flags", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "var", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "shiftop", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 667 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_helper_shl_cc\", \"code\": \"unsigned __int64 __fastcall gen_helper_shl_cc ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_shl_cc , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_shr_cc\", \"code\": \"unsigned __int64 __fastcall gen_helper_shr_cc ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_shr_cc , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_sar_cc\", \"code\": \"unsigned __int64 __fastcall gen_helper_sar_cc ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_sar_cc , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_helper_ror_cc\", \"code\": \"unsigned __int64 __fastcall gen_helper_ror_cc ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , __int64 @@a4@@ ) { __int64 @@v4@@ ; __int64 @@v8@@ [ Number ] ; unsigned __int64 @@v9@@ ; @@v9@@ = __readfsqword ( Number ) ; @@v8@@ [ Number ] = tcgv_ptr_temp ( @@a2@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a3@@ ) ; @@v8@@ [ Number ] = tcgv_i32_temp ( @@a4@@ ) ; @@v4@@ = tcgv_i32_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_ror_cc , @@v4@@ , Number L , @@v8@@ ) ; return __readfsqword ( Number ) ^ @@v9@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v8\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_shl\", \"code\": \"__int64 __fastcall gen_shl ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shl_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_shr\", \"code\": \"__int64 __fastcall gen_shr ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; @@v7@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v6@@ , @@v5@@ , @@v7@@ , @@v6@@ , @@a2@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_gen_andi_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_shr_i32 ( @@a1@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_sar\", \"code\": \"__int64 __fastcall gen_sar ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v5@@ , @@v5@@ , @@v6@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; tcg_gen_sar_i32 ( @@a1@@ , @@a2@@ , @@v5@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "arm_test_cc", "code": "__int64 __fastcall arm_test_cc ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@result@@ ; char @@v3@@ ; int @@v4@@ ; __int64 @@v5@@ ; @@v3@@ = Number ; switch ( @@a2@@ ) { case Number : case Number : @@v4@@ = Number ; @@v5@@ = cpu_ZF ; goto LABEL_11 ; case Number : case Number : @@v4@@ = Number ; @@v5@@ = cpu_CF ; goto LABEL_11 ; case Number : case Number : @@v4@@ = Number ; @@v5@@ = cpu_NF ; goto LABEL_11 ; case Number : case Number : @@v4@@ = Number ; @@v5@@ = cpu_VF ; goto LABEL_11 ; case Number : case Number : @@v4@@ = Number ; @@v5@@ = tcg_temp_new_i32 ( ) ; @@v3@@ = Number ; tcg_gen_neg_i32 ( @@v5@@ , cpu_CF ) ; tcg_gen_and_i32 ( @@v5@@ , @@v5@@ , cpu_ZF ) ; goto LABEL_11 ; case Number : case Number : @@v4@@ = Number ; @@v5@@ = tcg_temp_new_i32 ( ) ; @@v3@@ = Number ; tcg_gen_xor_i32 ( @@v5@@ , cpu_VF , cpu_NF ) ; goto LABEL_11 ; case Number : case Number : @@v4@@ = Number ; @@v5@@ = tcg_temp_new_i32 ( ) ; @@v3@@ = Number ; tcg_gen_xor_i32 ( @@v5@@ , cpu_VF , cpu_NF ) ; tcg_gen_sari_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_andc_i32 ( @@v5@@ , cpu_ZF , @@v5@@ ) ; LABEL_11 : if ( ( @@a2@@ & Number ) != Number ) @@v4@@ = tcg_invert_cond ( @@v4@@ ) ; break ; case Number : case Number : @@v4@@ = Number ; @@v5@@ = cpu_ZF ; break ; default : fprintf ( stderr , String , @@a2@@ ) ; abort ( ) ; } * ( _DWORD * ) @@a1@@ = @@v4@@ ; * ( _QWORD * ) ( @@a1@@ + Number ) = @@v5@@ ; @@result@@ = @@a1@@ ; * ( _BYTE * ) ( @@a1@@ + Number ) = @@v3@@ ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}, {"n": "v4", "t": {"T": 1, "n": "int", "s": 4}, "location": "s12"}, {"n": "v3", "t": {"T": 1, "n": "char", "s": 1}, "location": "s13"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "cmp", "t": {"T": 3, "t": "DisasCompare_0"}, "location": "r56"}, {"n": "cc", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}, {"n": "cond", "t": {"T": 1, "n": "TCGCond", "s": 4}, "location": "s12"}, {"n": "global", "t": {"T": 1, "n": "char", "s": 1}, "location": "s13"}, {"n": "value", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 668 |
[
"{\"name\": \"tcg_invert_cond\", \"code\": \"__int64 __fastcall tcg_invert_cond ( int @@a1@@ ) { return @@a1@@ ^ Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}]}",
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_and_i32\", \"code\": \"__int64 __fastcall tcg_gen_and_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_xor_i32\", \"code\": \"__int64 __fastcall tcg_gen_xor_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_op3_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_neg_i32\", \"code\": \"__int64 __fastcall tcg_gen_neg_i32 ( __int64 @@a1@@ , __int64 @@a2@@ ) { return tcg_gen_op2_i32 ( Number , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_sar\", \"code\": \"__int64 __fastcall gen_sar ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; @@v5@@ = tcg_temp_new_i32 ( ) ; tcg_gen_andi_i32 ( @@v5@@ , @@a3@@ , Number L ) ; @@v6@@ = tcg_const_i32 ( Number L ) ; tcg_gen_movcond_i32 ( Number L , @@v5@@ , @@v5@@ , @@v6@@ , @@v6@@ , @@v5@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; tcg_gen_sar_i32 ( @@a1@@ , @@a2@@ , @@v5@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "arm_free_cc", "code": "__int64 __fastcall arm_free_cc ( __int64 @@a1@@ ) { __int64 @@result@@ ; @@result@@ = * ( unsigned __int8 * ) ( @@a1@@ + Number ) ^ Number ; if ( * ( _BYTE * ) ( @@a1@@ + Number ) != Number ) @@result@@ = tcg_temp_free_i32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "cmp", "t": {"T": 3, "t": "DisasCompare_0"}, "location": "r56"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 669 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "arm_jump_cc", "code": "__int64 __fastcall arm_jump_cc ( unsigned int * @@a1@@ , __int64 @@a2@@ ) { return tcg_gen_brcondi_i32 ( * @@a1@@ , * ( ( _QWORD * ) @@a1@@ + Number ) , Number L , @@a2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 3, "t": "unsigned int"}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "cmp", "t": {"T": 3, "t": "DisasCompare_0"}, "location": "r56"}, {"n": "label", "t": {"T": 3, "t": "TCGLabel_0"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 670 |
[
"{\"name\": \"tcg_gen_br\", \"code\": \"__int64 __fastcall tcg_gen_br ( __int64 @@a1@@ ) { __int64 @@v1@@ ; ++ * ( _WORD * ) ( @@a1@@ + Number ) ; @@v1@@ = label_arg ( @@a1@@ ) ; return tcg_gen_op1 ( Number L , @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "arm_gen_test_cc", "code": "unsigned __int64 __fastcall arm_gen_test_cc ( unsigned int @@a1@@ , __int64 @@a2@@ ) { unsigned int @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; arm_test_cc ( ( __int64 ) @@v3@@ , @@a1@@ ) ; arm_jump_cc ( @@v3@@ , @@a2@@ ) ; arm_free_cc ( ( __int64 ) @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v3", "t": {"T": 2, "n": 6, "s": 4, "t": "unsigned int"}, "location": "s32"}, {"n": "v4", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]}
|
[{"n": "cc", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "label", "t": {"T": 3, "t": "TCGLabel_0"}, "location": "r64"}, {"n": "cmp", "t": {"T": 6, "n": "DisasCompare_0", "l": [{"T": 4, "n": "cond", "t": "TCGCond", "s": 4}, {"T": 5, "s": 4}, {"T": 4, "n": "value", "t": "TCGv_i32", "s": 8}, {"T": 4, "n": "value_global", "t": "bool", "s": 1}, {"T": 5, "s": 7}]}, "location": "s32"}, {"n": "v3", "t": {"T": 1, "n": "unsigned __int64", "s": 8}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 671 |
[
"{\"name\": \"arm_test_cc\", \"code\": \"__int64 __fastcall arm_test_cc ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@result@@ ; char @@v3@@ ; int @@v4@@ ; __int64 @@v5@@ ; @@v3@@ = Number ; switch ( @@a2@@ ) { case Number : case Number : @@v4@@ = Number ; @@v5@@ = cpu_ZF ; goto LABEL_11 ; case Number : case Number : @@v4@@ = Number ; @@v5@@ = cpu_CF ; goto LABEL_11 ; case Number : case Number : @@v4@@ = Number ; @@v5@@ = cpu_NF ; goto LABEL_11 ; case Number : case Number : @@v4@@ = Number ; @@v5@@ = cpu_VF ; goto LABEL_11 ; case Number : case Number : @@v4@@ = Number ; @@v5@@ = tcg_temp_new_i32 ( ) ; @@v3@@ = Number ; tcg_gen_neg_i32 ( @@v5@@ , cpu_CF ) ; tcg_gen_and_i32 ( @@v5@@ , @@v5@@ , cpu_ZF ) ; goto LABEL_11 ; case Number : case Number : @@v4@@ = Number ; @@v5@@ = tcg_temp_new_i32 ( ) ; @@v3@@ = Number ; tcg_gen_xor_i32 ( @@v5@@ , cpu_VF , cpu_NF ) ; goto LABEL_11 ; case Number : case Number : @@v4@@ = Number ; @@v5@@ = tcg_temp_new_i32 ( ) ; @@v3@@ = Number ; tcg_gen_xor_i32 ( @@v5@@ , cpu_VF , cpu_NF ) ; tcg_gen_sari_i32 ( @@v5@@ , @@v5@@ , Number L ) ; tcg_gen_andc_i32 ( @@v5@@ , cpu_ZF , @@v5@@ ) ; LABEL_11 : if ( ( @@a2@@ & Number ) != Number ) @@v4@@ = tcg_invert_cond ( @@v4@@ ) ; break ; case Number : case Number : @@v4@@ = Number ; @@v5@@ = cpu_ZF ; break ; default : fprintf ( stderr , String , @@a2@@ ) ; abort ( ) ; } * ( _DWORD * ) @@a1@@ = @@v4@@ ; * ( _QWORD * ) ( @@a1@@ + Number ) = @@v5@@ ; @@result@@ = @@a1@@ ; * ( _BYTE * ) ( @@a1@@ + Number ) = @@v3@@ ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"s13\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"arm_free_cc\", \"code\": \"__int64 __fastcall arm_free_cc ( __int64 @@a1@@ ) { __int64 @@result@@ ; @@result@@ = * ( unsigned __int8 * ) ( @@a1@@ + Number ) ^ Number ; if ( * ( _BYTE * ) ( @@a1@@ + Number ) != Number ) @@result@@ = tcg_temp_free_i32 ( * ( _QWORD * ) ( @@a1@@ + Number ) ) ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"arm_jump_cc\", \"code\": \"__int64 __fastcall arm_jump_cc ( unsigned int * @@a1@@ , __int64 @@a2@@ ) { return tcg_gen_brcondi_i32 ( * @@a1@@ , * ( ( _QWORD * ) @@a1@@ + Number ) , Number L , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 3, \"t\": \"unsigned int\"}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "gen_set_condexec", "code": "__int64 __fastcall gen_set_condexec ( __int64 @@a1@@ ) { __int64 @@result@@ ; int @@v2@@ ; __int64 @@v3@@ ; @@result@@ = * ( unsigned int * ) ( @@a1@@ + Number ) ; if ( ( _DWORD ) @@result@@ ) { @@v2@@ = ( Number * * ( _DWORD * ) ( @@a1@@ + Number ) ) | ( * ( int * ) ( @@a1@@ + Number ) >> Number ) ; @@v3@@ = tcg_temp_new_i32 ( ) ; tcg_gen_movi_i32 ( @@v3@@ , @@v2@@ ) ; @@result@@ = store_cpu_offset ( @@v3@@ , Number ) ; } return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "s12"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "", "t": {"T": 10}, "location": "r8"}, {"n": "val", "t": {"T": 1, "n": "int", "s": 4}, "location": "s12"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 672 |
[
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_movi_i32\", \"code\": \"__int64 __fastcall tcg_gen_movi_i32 ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_op2i_i32 ( Number , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"store_cpu_offset\", \"code\": \"__int64 __fastcall store_cpu_offset ( __int64 @@a1@@ , int @@a2@@ ) { tcg_gen_st_i32 ( @@a1@@ , cpu_env , @@a2@@ ) ; return tcg_temp_free_i32 ( @@a1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_set_pc_im", "code": "__int64 __fastcall gen_set_pc_im ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_movi_i32 ( qword_4BEB8 , @@a2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "val", "t": {"T": 1, "n": "target_ulong", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 673 |
[
"{\"name\": \"tcg_gen_movi_i32\", \"code\": \"__int64 __fastcall tcg_gen_movi_i32 ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_op2i_i32 ( Number , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_bx", "code": "__int64 __fastcall gen_bx ( __int64 @@a1@@ , __int64 @@a2@@ ) { * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; tcg_gen_andi_i32 ( qword_4BEB8 , @@a2@@ , Number L ) ; tcg_gen_andi_i32 ( @@a2@@ , @@a2@@ , Number L ) ; return store_cpu_offset ( @@a2@@ , Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "var", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 674 |
[
"{\"name\": \"store_cpu_offset\", \"code\": \"__int64 __fastcall store_cpu_offset ( __int64 @@a1@@ , int @@a2@@ ) { tcg_gen_st_i32 ( @@a1@@ , cpu_env , @@a2@@ ) ; return tcg_temp_free_i32 ( @@a1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_bx_excret", "code": "__int64 __fastcall gen_bx_excret ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@result@@ ; gen_bx ( @@a1@@ , @@a2@@ ) ; if ( arm_dc_feature ( @@a1@@ , Number ) || ( @@result@@ = * ( unsigned __int8 * ) ( @@a1@@ + Number ) , ( _BYTE ) @@result@@ ) && ( @@result@@ = arm_dc_feature ( @@a1@@ , Number ) , ( _DWORD ) @@result@@ ) ) { @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "var", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 675 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_bx\", \"code\": \"__int64 __fastcall gen_bx ( __int64 @@a1@@ , __int64 @@a2@@ ) { * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; tcg_gen_andi_i32 ( qword_4BEB8 , @@a2@@ , Number L ) ; tcg_gen_andi_i32 ( @@a2@@ , @@a2@@ , Number L ) ; return store_cpu_offset ( @@a2@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "gen_bx_excret_final_code", "code": "__int64 __fastcall gen_bx_excret_final_code ( __int64 @@a1@@ ) { unsigned int @@v2@@ ; _BYTE * @@v3@@ ; @@v3@@ = ( _BYTE * ) gen_new_label ( ) ; if ( arm_dc_feature ( @@a1@@ , Number ) ) @@v2@@ = Number ; else @@v2@@ = Number ; tcg_gen_brcondi_i32 ( Number L , qword_4BEB8 , @@v2@@ , @@v3@@ ) ; if ( is_singlestepping ( @@a1@@ ) ) gen_singlestep_exception ( @@a1@@ ) ; else tcg_gen_exit_tb ( Number L , Number L ) ; gen_set_label ( @@v3@@ ) ; gen_ss_advance ( @@a1@@ ) ; return gen_exception_internal ( Number ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "v2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "s12"}, {"n": "v3", "t": {"T": 3, "t": "_BYTE"}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "min_magic", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "s12"}, {"n": "excret_label", "t": {"T": 3, "t": "TCGLabel_0"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 676 |
[
"{\"name\": \"gen_set_label\", \"code\": \"__int64 __fastcall gen_set_label ( _BYTE * @@a1@@ ) { __int64 @@v1@@ ; * @@a1@@ |= Number ; @@v1@@ = label_arg ( ( __int64 ) @@a1@@ ) ; return tcg_gen_op1 ( Number L , @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 3, \"t\": \"_BYTE\"}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_gen_br\", \"code\": \"__int64 __fastcall tcg_gen_br ( __int64 @@a1@@ ) { __int64 @@v1@@ ; ++ * ( _WORD * ) ( @@a1@@ + Number ) ; @@v1@@ = label_arg ( @@a1@@ ) ; return tcg_gen_op1 ( Number L , @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_ss_advance\", \"code\": \"__int64 __fastcall gen_ss_advance ( __int64 @@a1@@ ) { __int64 @@result@@ ; @@result@@ = * ( unsigned __int8 * ) ( @@a1@@ + Number ) ; if ( ( _BYTE ) @@result@@ ) { * ( _BYTE * ) ( @@a1@@ + Number ) = Number ; @@result@@ = clear_pstate_bits ( Number ) ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_exception\", \"code\": \"__int64 __fastcall gen_exception ( unsigned int @@a1@@ , unsigned int @@a2@@ , unsigned int @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_const_i32 ( @@a1@@ ) ; @@v6@@ = tcg_const_i32 ( @@a2@@ ) ; @@v7@@ = tcg_const_i32 ( @@a3@@ ) ; gen_helper_exception_with_syndrome ( cpu_env , @@v5@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_exception_internal\", \"code\": \"__int64 __fastcall gen_exception_internal ( unsigned int @@a1@@ ) { __int64 @@v2@@ ; @@v2@@ = tcg_const_i32 ( @@a1@@ ) ; if ( ! excp_is_internal ( @@a1@@ ) ) _assert_fail ( String , String , Number , String ) ; gen_helper_exception_internal ( cpu_env , @@v2@@ ) ; return tcg_temp_free_i32 ( @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_singlestep_exception\", \"code\": \"__int64 __fastcall gen_singlestep_exception ( __int64 @@a1@@ ) { __int64 @@result@@ ; if ( * ( _BYTE * ) ( @@a1@@ + Number ) ) @@result@@ = gen_step_complete_exception ( @@a1@@ ) ; else @@result@@ = gen_exception_internal ( Number ) ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"is_singlestepping\", \"code\": \"_BOOL8 __fastcall is_singlestepping ( __int64 @@a1@@ ) { return * ( _BYTE * ) ( @@a1@@ + Number ) || * ( _BYTE * ) ( @@a1@@ + Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}]}",
"{\"name\": \"gen_bx\", \"code\": \"__int64 __fastcall gen_bx ( __int64 @@a1@@ , __int64 @@a2@@ ) { * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; tcg_gen_andi_i32 ( qword_4BEB8 , @@a2@@ , Number L ) ; tcg_gen_andi_i32 ( @@a2@@ , @@a2@@ , Number L ) ; return store_cpu_offset ( @@a2@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_bx_excret\", \"code\": \"__int64 __fastcall gen_bx_excret ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@result@@ ; gen_bx ( @@a1@@ , @@a2@@ ) ; if ( arm_dc_feature ( @@a1@@ , Number ) || ( @@result@@ = * ( unsigned __int8 * ) ( @@a1@@ + Number ) , ( _BYTE ) @@result@@ ) && ( @@result@@ = arm_dc_feature ( @@a1@@ , Number ) , ( _DWORD ) @@result@@ ) ) { @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "gen_bxns", "code": "__int64 __fastcall gen_bxns ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@result@@ ; __int64 @@v3@@ ; @@v3@@ = load_reg ( @@a1@@ , @@a2@@ ) ; gen_helper_v7m_bxns ( cpu_env , @@v3@@ ) ; tcg_temp_free_i32 ( @@v3@@ ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "rm", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}, {"n": "var", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 677 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_helper_v7m_bxns\", \"code\": \"unsigned __int64 __fastcall gen_helper_v7m_bxns ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v3@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; tcg_gen_callN ( & helper_v7m_bxns , Number L , Number L , @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_bx\", \"code\": \"__int64 __fastcall gen_bx ( __int64 @@a1@@ , __int64 @@a2@@ ) { * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; tcg_gen_andi_i32 ( qword_4BEB8 , @@a2@@ , Number L ) ; tcg_gen_andi_i32 ( @@a2@@ , @@a2@@ , Number L ) ; return store_cpu_offset ( @@a2@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "gen_blxns", "code": "__int64 __fastcall gen_blxns ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@result@@ ; __int64 @@v3@@ ; @@v3@@ = load_reg ( @@a1@@ , @@a2@@ ) ; gen_set_pc_im ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; gen_helper_v7m_blxns ( cpu_env , @@v3@@ ) ; tcg_temp_free_i32 ( @@v3@@ ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "rm", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}, {"n": "var", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 678 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_helper_v7m_blxns\", \"code\": \"unsigned __int64 __fastcall gen_helper_v7m_blxns ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v3@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; tcg_gen_callN ( & helper_v7m_blxns , Number L , Number L , @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_set_pc_im\", \"code\": \"__int64 __fastcall gen_set_pc_im ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_movi_i32 ( qword_4BEB8 , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "store_reg_bx", "code": "__int64 __fastcall store_reg_bx ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@result@@ ; if ( @@a2@@ == Number && arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = gen_bx ( @@a1@@ , @@a3@@ ) ; else @@result@@ = store_reg ( @@a1@@ , @@a2@@ , @@a3@@ ) ; return @@result@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "var", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "reg", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 679 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_bx\", \"code\": \"__int64 __fastcall gen_bx ( __int64 @@a1@@ , __int64 @@a2@@ ) { * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; tcg_gen_andi_i32 ( qword_4BEB8 , @@a2@@ , Number L ) ; tcg_gen_andi_i32 ( @@a2@@ , @@a2@@ , Number L ) ; return store_cpu_offset ( @@a2@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "store_reg_from_load", "code": "__int64 __fastcall store_reg_from_load ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@result@@ ; if ( @@a2@@ == Number && arm_dc_feature ( @@a1@@ , Number ) ) @@result@@ = gen_bx_excret ( @@a1@@ , @@a3@@ ) ; else @@result@@ = store_reg ( @@a1@@ , @@a2@@ , @@a3@@ ) ; return @@result@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "var", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "reg", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 680 |
[
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_bx\", \"code\": \"__int64 __fastcall gen_bx ( __int64 @@a1@@ , __int64 @@a2@@ ) { * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; tcg_gen_andi_i32 ( qword_4BEB8 , @@a2@@ , Number L ) ; tcg_gen_andi_i32 ( @@a2@@ , @@a2@@ , Number L ) ; return store_cpu_offset ( @@a2@@ , Number ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_bx_excret\", \"code\": \"__int64 __fastcall gen_bx_excret ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@result@@ ; gen_bx ( @@a1@@ , @@a2@@ ) ; if ( arm_dc_feature ( @@a1@@ , Number ) || ( @@result@@ = * ( unsigned __int8 * ) ( @@a1@@ + Number ) , ( _BYTE ) @@result@@ ) && ( @@result@@ = arm_dc_feature ( @@a1@@ , Number ) , ( _DWORD ) @@result@@ ) ) { @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "gen_aa32_addr", "code": "__int64 __fastcall gen_aa32_addr ( __int64 @@a1@@ , __int64 @@a2@@ , char @@a3@@ ) { __int64 @@v5@@ ; @@v5@@ = tcg_temp_new_i64 ( ) ; tcg_gen_extu_i32_i64 ( @@v5@@ , @@a2@@ ) ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) && ( @@a3@@ & Number ) == Number ) tcg_gen_xori_i64 ( @@v5@@ , @@v5@@ , Number - ( Number << ( @@a3@@ & Number ) ) ) ; return @@v5@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "char", "s": 1}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "v5", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "op", "t": {"T": 1, "n": "MemOp_0", "s": 4}, "location": "r16"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a32", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}, {"n": "addr", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 681 |
[
"{\"name\": \"tcg_temp_new_i64\", \"code\": \"__int64 tcg_temp_new_i64 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i64 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_aa32_ld_i32", "code": "__int64 __fastcall gen_aa32_ld_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ) @@a5@@ |= Number ; @@v9@@ = gen_aa32_addr ( @@a1@@ , @@a3@@ , @@a5@@ ) ; tcg_gen_qemu_ld_i32 ( @@a2@@ , @@v9@@ , @@a4@@ , @@a5@@ ) ; return tcg_temp_free_i64 ( @@v9@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "a5", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r72"}, {"n": "v9", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "a32", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "index", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "val", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}, {"n": "opc", "t": {"T": 1, "n": "MemOp_0", "s": 4}, "location": "r72"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 682 |
[
"{\"name\": \"tcg_temp_free_i64\", \"code\": \"__int64 __fastcall tcg_temp_free_i64 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i64_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_aa32_addr\", \"code\": \"__int64 __fastcall gen_aa32_addr ( __int64 @@a1@@ , __int64 @@a2@@ , char @@a3@@ ) { __int64 @@v5@@ ; @@v5@@ = tcg_temp_new_i64 ( ) ; tcg_gen_extu_i32_i64 ( @@v5@@ , @@a2@@ ) ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) && ( @@a3@@ & Number ) == Number ) tcg_gen_xori_i64 ( @@v5@@ , @@v5@@ , Number - ( Number << ( @@a3@@ & Number ) ) ) ; return @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_aa32_st_i32", "code": "__int64 __fastcall gen_aa32_st_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ) @@a5@@ |= Number ; @@v9@@ = gen_aa32_addr ( @@a1@@ , @@a3@@ , @@a5@@ ) ; tcg_gen_qemu_st_i32 ( @@a2@@ , @@v9@@ , @@a4@@ , @@a5@@ ) ; return tcg_temp_free_i64 ( @@v9@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "a5", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r72"}, {"n": "v9", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "a32", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "index", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "val", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}, {"n": "opc", "t": {"T": 1, "n": "MemOp_0", "s": 4}, "location": "r72"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 683 |
[
"{\"name\": \"tcg_temp_free_i64\", \"code\": \"__int64 __fastcall tcg_temp_free_i64 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i64_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"arm_dc_feature\", \"code\": \"_BOOL8 __fastcall arm_dc_feature ( __int64 @@a1@@ , char @@a2@@ ) { return ( ( * ( _QWORD * ) ( @@a1@@ + Number ) >> @@a2@@ ) & Number L ) != Number ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r64\"}]}",
"{\"name\": \"gen_aa32_addr\", \"code\": \"__int64 __fastcall gen_aa32_addr ( __int64 @@a1@@ , __int64 @@a2@@ , char @@a3@@ ) { __int64 @@v5@@ ; @@v5@@ = tcg_temp_new_i64 ( ) ; tcg_gen_extu_i32_i64 ( @@v5@@ , @@a2@@ ) ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) && ( @@a3@@ & Number ) == Number ) tcg_gen_xori_i64 ( @@v5@@ , @@v5@@ , Number - ( Number << ( @@a3@@ & Number ) ) ) ; return @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_aa32_frob64", "code": "__int64 __fastcall gen_aa32_frob64 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@result@@ ; @@result@@ = * ( unsigned int * ) ( @@a1@@ + Number ) ; if ( ( _DWORD ) @@result@@ ) @@result@@ = tcg_gen_rotri_i64 ( @@a2@@ , @@a2@@ , Number L ) ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "val", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 684 |
[] |
{"name": "gen_aa32_ld_i64", "code": "__int64 __fastcall gen_aa32_ld_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v8@@ ; @@v8@@ = gen_aa32_addr ( @@a1@@ , @@a3@@ , @@a5@@ ) ; tcg_gen_qemu_ld_i64 ( @@a2@@ , @@v8@@ , @@a4@@ , @@a5@@ ) ; gen_aa32_frob64 ( @@a1@@ , @@a2@@ ) ; return tcg_temp_free_i64 ( @@v8@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "a5", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r72"}, {"n": "v8", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "a32", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "index", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "val", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r64"}, {"n": "opc", "t": {"T": 1, "n": "MemOp_0", "s": 4}, "location": "r72"}, {"n": "", "t": {"T": 10}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 685 |
[
"{\"name\": \"tcg_temp_free_i64\", \"code\": \"__int64 __fastcall tcg_temp_free_i64 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i64_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_aa32_addr\", \"code\": \"__int64 __fastcall gen_aa32_addr ( __int64 @@a1@@ , __int64 @@a2@@ , char @@a3@@ ) { __int64 @@v5@@ ; @@v5@@ = tcg_temp_new_i64 ( ) ; tcg_gen_extu_i32_i64 ( @@v5@@ , @@a2@@ ) ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) && ( @@a3@@ & Number ) == Number ) tcg_gen_xori_i64 ( @@v5@@ , @@v5@@ , Number - ( Number << ( @@a3@@ & Number ) ) ) ; return @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_aa32_frob64\", \"code\": \"__int64 __fastcall gen_aa32_frob64 ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@result@@ ; @@result@@ = * ( unsigned int * ) ( @@a1@@ + Number ) ; if ( ( _DWORD ) @@result@@ ) @@result@@ = tcg_gen_rotri_i64 ( @@a2@@ , @@a2@@ , Number L ) ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "gen_aa32_ld64", "code": "__int64 __fastcall gen_aa32_ld64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { return gen_aa32_ld_i64 ( @@a1@@ , @@a2@@ , @@a3@@ , @@a4@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "a32", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "index", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "val", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 686 |
[
"{\"name\": \"gen_aa32_ld_i64\", \"code\": \"__int64 __fastcall gen_aa32_ld_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v8@@ ; @@v8@@ = gen_aa32_addr ( @@a1@@ , @@a3@@ , @@a5@@ ) ; tcg_gen_qemu_ld_i64 ( @@a2@@ , @@v8@@ , @@a4@@ , @@a5@@ ) ; gen_aa32_frob64 ( @@a1@@ , @@a2@@ ) ; return tcg_temp_free_i64 ( @@v8@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_aa32_st_i64", "code": "__int64 __fastcall gen_aa32_st_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v8@@ ; __int64 @@v9@@ ; @@v8@@ = gen_aa32_addr ( @@a1@@ , @@a3@@ , @@a5@@ ) ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { @@v9@@ = tcg_temp_new_i64 ( ) ; tcg_gen_rotri_i64 ( @@v9@@ , @@a2@@ , Number L ) ; tcg_gen_qemu_st_i64 ( @@v9@@ , @@v8@@ , @@a4@@ , @@a5@@ ) ; tcg_temp_free_i64 ( @@v9@@ ) ; } else { tcg_gen_qemu_st_i64 ( @@a2@@ , @@v8@@ , @@a4@@ , @@a5@@ ) ; } return tcg_temp_free_i64 ( @@v8@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}, {"n": "a5", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r72"}, {"n": "v8", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s16"}, {"n": "v9", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "a32", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "index", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "val", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r64"}, {"n": "opc", "t": {"T": 1, "n": "MemOp_0", "s": 4}, "location": "r72"}, {"n": "addr", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s16"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i64_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 687 |
[
"{\"name\": \"tcg_temp_free_i64\", \"code\": \"__int64 __fastcall tcg_temp_free_i64 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i64_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_temp_new_i64\", \"code\": \"__int64 tcg_temp_new_i64 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i64 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_aa32_addr\", \"code\": \"__int64 __fastcall gen_aa32_addr ( __int64 @@a1@@ , __int64 @@a2@@ , char @@a3@@ ) { __int64 @@v5@@ ; @@v5@@ = tcg_temp_new_i64 ( ) ; tcg_gen_extu_i32_i64 ( @@v5@@ , @@a2@@ ) ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) && ( @@a3@@ & Number ) == Number ) tcg_gen_xori_i64 ( @@v5@@ , @@v5@@ , Number - ( Number << ( @@a3@@ & Number ) ) ) ; return @@v5@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_aa32_st64", "code": "__int64 __fastcall gen_aa32_st64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { return gen_aa32_st_i64 ( @@a1@@ , @@a2@@ , @@a3@@ , @@a4@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "a32", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "index", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "val", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 688 |
[
"{\"name\": \"gen_aa32_st_i64\", \"code\": \"__int64 __fastcall gen_aa32_st_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v8@@ ; __int64 @@v9@@ ; @@v8@@ = gen_aa32_addr ( @@a1@@ , @@a3@@ , @@a5@@ ) ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) { @@v9@@ = tcg_temp_new_i64 ( ) ; tcg_gen_rotri_i64 ( @@v9@@ , @@a2@@ , Number L ) ; tcg_gen_qemu_st_i64 ( @@v9@@ , @@v8@@ , @@a4@@ , @@a5@@ ) ; tcg_temp_free_i64 ( @@v9@@ ) ; } else { tcg_gen_qemu_st_i64 ( @@a2@@ , @@v8@@ , @@a4@@ , @@a5@@ ) ; } return tcg_temp_free_i64 ( @@v8@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v8\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_aa32_ld8u", "code": "__int64 __fastcall gen_aa32_ld8u ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { return gen_aa32_ld_i32 ( @@a1@@ , @@a2@@ , @@a3@@ , @@a4@@ , * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "a32", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "index", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "val", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 689 |
[
"{\"name\": \"gen_aa32_ld_i32\", \"code\": \"__int64 __fastcall gen_aa32_ld_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ) @@a5@@ |= Number ; @@v9@@ = gen_aa32_addr ( @@a1@@ , @@a3@@ , @@a5@@ ) ; tcg_gen_qemu_ld_i32 ( @@a2@@ , @@v9@@ , @@a4@@ , @@a5@@ ) ; return tcg_temp_free_i64 ( @@v9@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_aa32_ld16u", "code": "__int64 __fastcall gen_aa32_ld16u ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { return gen_aa32_ld_i32 ( @@a1@@ , @@a2@@ , @@a3@@ , @@a4@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "a32", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "index", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "val", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 690 |
[
"{\"name\": \"gen_aa32_ld_i32\", \"code\": \"__int64 __fastcall gen_aa32_ld_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ) @@a5@@ |= Number ; @@v9@@ = gen_aa32_addr ( @@a1@@ , @@a3@@ , @@a5@@ ) ; tcg_gen_qemu_ld_i32 ( @@a2@@ , @@v9@@ , @@a4@@ , @@a5@@ ) ; return tcg_temp_free_i64 ( @@v9@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_aa32_ld32u", "code": "__int64 __fastcall gen_aa32_ld32u ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { return gen_aa32_ld_i32 ( @@a1@@ , @@a2@@ , @@a3@@ , @@a4@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "a32", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "index", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "val", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 691 |
[
"{\"name\": \"gen_aa32_ld_i32\", \"code\": \"__int64 __fastcall gen_aa32_ld_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ) @@a5@@ |= Number ; @@v9@@ = gen_aa32_addr ( @@a1@@ , @@a3@@ , @@a5@@ ) ; tcg_gen_qemu_ld_i32 ( @@a2@@ , @@v9@@ , @@a4@@ , @@a5@@ ) ; return tcg_temp_free_i64 ( @@v9@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_aa32_st8", "code": "__int64 __fastcall gen_aa32_st8 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { return gen_aa32_st_i32 ( @@a1@@ , @@a2@@ , @@a3@@ , @@a4@@ , * ( _DWORD * ) ( @@a1@@ + Number ) ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "a32", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "index", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "val", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 692 |
[
"{\"name\": \"gen_aa32_st_i32\", \"code\": \"__int64 __fastcall gen_aa32_st_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ) @@a5@@ |= Number ; @@v9@@ = gen_aa32_addr ( @@a1@@ , @@a3@@ , @@a5@@ ) ; tcg_gen_qemu_st_i32 ( @@a2@@ , @@v9@@ , @@a4@@ , @@a5@@ ) ; return tcg_temp_free_i64 ( @@v9@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_aa32_st16", "code": "__int64 __fastcall gen_aa32_st16 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { return gen_aa32_st_i32 ( @@a1@@ , @@a2@@ , @@a3@@ , @@a4@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "a32", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "index", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "val", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 693 |
[
"{\"name\": \"gen_aa32_st_i32\", \"code\": \"__int64 __fastcall gen_aa32_st_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ) @@a5@@ |= Number ; @@v9@@ = gen_aa32_addr ( @@a1@@ , @@a3@@ , @@a5@@ ) ; tcg_gen_qemu_st_i32 ( @@a2@@ , @@v9@@ , @@a4@@ , @@a5@@ ) ; return tcg_temp_free_i64 ( @@v9@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_aa32_st32", "code": "__int64 __fastcall gen_aa32_st32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ ) { return gen_aa32_st_i32 ( @@a1@@ , @@a2@@ , @@a3@@ , @@a4@@ , * ( _DWORD * ) ( @@a1@@ + Number ) | Number ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r64"}]}
|
[{"n": "a32", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "index", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "val", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 694 |
[
"{\"name\": \"gen_aa32_st_i32\", \"code\": \"__int64 __fastcall gen_aa32_st_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ , int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@v9@@ ; if ( arm_dc_feature ( @@a1@@ , Number ) && ! arm_dc_feature ( @@a1@@ , Number ) ) @@a5@@ |= Number ; @@v9@@ = gen_aa32_addr ( @@a1@@ , @@a3@@ , @@a5@@ ) ; tcg_gen_qemu_st_i32 ( @@a2@@ , @@v9@@ , @@a4@@ , @@a5@@ ) ; return tcg_temp_free_i64 ( @@v9@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"v9\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "gen_hvc", "code": "__int64 __fastcall gen_hvc ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@result@@ ; gen_set_pc_im ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; gen_helper_pre_hvc ( cpu_env ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = @@a2@@ ; gen_set_pc_im ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "imm16", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 695 |
[
"{\"name\": \"gen_helper_pre_hvc\", \"code\": \"unsigned __int64 __fastcall gen_helper_pre_hvc ( __int64 @@a1@@ ) { __int64 @@v2@@ ; unsigned __int64 @@v3@@ ; @@v3@@ = __readfsqword ( Number ) ; @@v2@@ = tcgv_ptr_temp ( @@a1@@ ) ; tcg_gen_callN ( & helper_pre_hvc , Number L , Number L , & @@v2@@ ) ; return __readfsqword ( Number ) ^ @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_set_pc_im\", \"code\": \"__int64 __fastcall gen_set_pc_im ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_movi_i32 ( qword_4BEB8 , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_smc", "code": "__int64 __fastcall gen_smc ( __int64 @@a1@@ ) { unsigned int v1 ; __int64 result ; __int64 @@v3@@ ; gen_set_pc_im ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; v1 = syn_aa32_smc ( ) ; @@v3@@ = tcg_const_i32 ( v1 ) ; gen_helper_pre_smc ( cpu_env , @@v3@@ ) ; tcg_temp_free_i32 ( @@v3@@ ) ; gen_set_pc_im ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; result = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return result ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 696 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_helper_pre_smc\", \"code\": \"unsigned __int64 __fastcall gen_helper_pre_smc ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v3@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; tcg_gen_callN ( & helper_pre_smc , Number L , Number L , @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_set_pc_im\", \"code\": \"__int64 __fastcall gen_set_pc_im ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_movi_i32 ( qword_4BEB8 , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_exception_internal_insn", "code": "__int64 __fastcall gen_exception_internal_insn ( __int64 @@a1@@ , int @@a2@@ , unsigned int @@a3@@ ) { __int64 @@result@@ ; gen_set_condexec ( @@a1@@ ) ; gen_set_pc_im ( @@a1@@ , @@a2@@ ) ; gen_exception_internal ( @@a3@@ ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "excp", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "pc", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 697 |
[
"{\"name\": \"gen_exception\", \"code\": \"__int64 __fastcall gen_exception ( unsigned int @@a1@@ , unsigned int @@a2@@ , unsigned int @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_const_i32 ( @@a1@@ ) ; @@v6@@ = tcg_const_i32 ( @@a2@@ ) ; @@v7@@ = tcg_const_i32 ( @@a3@@ ) ; gen_helper_exception_with_syndrome ( cpu_env , @@v5@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_exception_internal\", \"code\": \"__int64 __fastcall gen_exception_internal ( unsigned int @@a1@@ ) { __int64 @@v2@@ ; @@v2@@ = tcg_const_i32 ( @@a1@@ ) ; if ( ! excp_is_internal ( @@a1@@ ) ) _assert_fail ( String , String , Number , String ) ; gen_helper_exception_internal ( cpu_env , @@v2@@ ) ; return tcg_temp_free_i32 ( @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_set_condexec\", \"code\": \"__int64 __fastcall gen_set_condexec ( __int64 @@a1@@ ) { __int64 @@result@@ ; int @@v2@@ ; __int64 @@v3@@ ; @@result@@ = * ( unsigned int * ) ( @@a1@@ + Number ) ; if ( ( _DWORD ) @@result@@ ) { @@v2@@ = ( Number * * ( _DWORD * ) ( @@a1@@ + Number ) ) | ( * ( int * ) ( @@a1@@ + Number ) >> Number ) ; @@v3@@ = tcg_temp_new_i32 ( ) ; tcg_gen_movi_i32 ( @@v3@@ , @@v2@@ ) ; @@result@@ = store_cpu_offset ( @@v3@@ , Number ) ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_set_pc_im\", \"code\": \"__int64 __fastcall gen_set_pc_im ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_movi_i32 ( qword_4BEB8 , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_exception_insn", "code": "__int64 __fastcall gen_exception_insn ( __int64 @@a1@@ , int @@a2@@ , unsigned int @@a3@@ , unsigned int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@result@@ ; gen_set_condexec ( @@a1@@ ) ; gen_set_pc_im ( @@a1@@ , @@a2@@ ) ; gen_exception ( @@a3@@ , @@a4@@ , @@a5@@ ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "a5", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r72"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "excp", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "syn", "t": {"T": 1, "n": "int", "s": 4}, "location": "r24"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "pc", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r64"}, {"n": "target_el", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r72"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 698 |
[
"{\"name\": \"gen_exception\", \"code\": \"__int64 __fastcall gen_exception ( unsigned int @@a1@@ , unsigned int @@a2@@ , unsigned int @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_const_i32 ( @@a1@@ ) ; @@v6@@ = tcg_const_i32 ( @@a2@@ ) ; @@v7@@ = tcg_const_i32 ( @@a3@@ ) ; gen_helper_exception_with_syndrome ( cpu_env , @@v5@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_set_condexec\", \"code\": \"__int64 __fastcall gen_set_condexec ( __int64 @@a1@@ ) { __int64 @@result@@ ; int @@v2@@ ; __int64 @@v3@@ ; @@result@@ = * ( unsigned int * ) ( @@a1@@ + Number ) ; if ( ( _DWORD ) @@result@@ ) { @@v2@@ = ( Number * * ( _DWORD * ) ( @@a1@@ + Number ) ) | ( * ( int * ) ( @@a1@@ + Number ) >> Number ) ; @@v3@@ = tcg_temp_new_i32 ( ) ; tcg_gen_movi_i32 ( @@v3@@ , @@v2@@ ) ; @@result@@ = store_cpu_offset ( @@v3@@ , Number ) ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_set_pc_im\", \"code\": \"__int64 __fastcall gen_set_pc_im ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_movi_i32 ( qword_4BEB8 , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_exception_bkpt_insn", "code": "__int64 __fastcall gen_exception_bkpt_insn ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@result@@ ; __int64 @@v3@@ ; gen_set_condexec ( @@a1@@ ) ; gen_set_pc_im ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; @@v3@@ = tcg_const_i32 ( @@a2@@ ) ; gen_helper_exception_bkpt_insn ( cpu_env , @@v3@@ ) ; tcg_temp_free_i32 ( @@v3@@ ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "syn", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}, {"n": "tcg_syn", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 699 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_helper_exception_bkpt_insn\", \"code\": \"unsigned __int64 __fastcall gen_helper_exception_bkpt_insn ( __int64 @@a1@@ , __int64 @@a2@@ ) { __int64 @@v3@@ [ Number ] ; unsigned __int64 @@v4@@ ; @@v4@@ = __readfsqword ( Number ) ; @@v3@@ [ Number ] = tcgv_ptr_temp ( @@a1@@ ) ; @@v3@@ [ Number ] = tcgv_i32_temp ( @@a2@@ ) ; tcg_gen_callN ( & helper_exception_bkpt_insn , Number L , Number L , @@v3@@ ) ; return __readfsqword ( Number ) ^ @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 2, \"n\": 3, \"s\": 8, \"t\": \"__int64\"}, \"location\": \"s32\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_exception\", \"code\": \"__int64 __fastcall gen_exception ( unsigned int @@a1@@ , unsigned int @@a2@@ , unsigned int @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_const_i32 ( @@a1@@ ) ; @@v6@@ = tcg_const_i32 ( @@a2@@ ) ; @@v7@@ = tcg_const_i32 ( @@a3@@ ) ; gen_helper_exception_with_syndrome ( cpu_env , @@v5@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_set_condexec\", \"code\": \"__int64 __fastcall gen_set_condexec ( __int64 @@a1@@ ) { __int64 @@result@@ ; int @@v2@@ ; __int64 @@v3@@ ; @@result@@ = * ( unsigned int * ) ( @@a1@@ + Number ) ; if ( ( _DWORD ) @@result@@ ) { @@v2@@ = ( Number * * ( _DWORD * ) ( @@a1@@ + Number ) ) | ( * ( int * ) ( @@a1@@ + Number ) >> Number ) ; @@v3@@ = tcg_temp_new_i32 ( ) ; tcg_gen_movi_i32 ( @@v3@@ , @@v2@@ ) ; @@result@@ = store_cpu_offset ( @@v3@@ , Number ) ; } return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"s12\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_set_pc_im\", \"code\": \"__int64 __fastcall gen_set_pc_im ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_movi_i32 ( qword_4BEB8 , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "unallocated_encoding", "code": "__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }", "source": [{"n": "v1", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r32"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "v2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r8"}]}
|
[{"n": "v1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r32"}, {"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 700 |
[
"{\"name\": \"default_exception_el\", \"code\": \"__int64 __fastcall default_exception_el ( __int64 @@a1@@ ) { __int64 @@result@@ ; if ( * ( _DWORD * ) ( @@a1@@ + Number ) == Number && * ( _BYTE * ) ( @@a1@@ + Number ) ) return Number L ; @@result@@ = * ( unsigned int * ) ( @@a1@@ + Number ) ; if ( ( int ) @@result@@ <= Number ) @@result@@ = Number L ; return @@result@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"gen_exception\", \"code\": \"__int64 __fastcall gen_exception ( unsigned int @@a1@@ , unsigned int @@a2@@ , unsigned int @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_const_i32 ( @@a1@@ ) ; @@v6@@ = tcg_const_i32 ( @@a2@@ ) ; @@v7@@ = tcg_const_i32 ( @@a3@@ ) ; gen_helper_exception_with_syndrome ( cpu_env , @@v5@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_exception_insn\", \"code\": \"__int64 __fastcall gen_exception_insn ( __int64 @@a1@@ , int @@a2@@ , unsigned int @@a3@@ , unsigned int @@a4@@ , unsigned int @@a5@@ ) { __int64 @@result@@ ; gen_set_condexec ( @@a1@@ ) ; gen_set_pc_im ( @@a1@@ , @@a2@@ ) ; gen_exception ( @@a3@@ , @@a4@@ , @@a5@@ ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"a5\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r72\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "gen_lookup_tb", "code": "__int64 __fastcall gen_lookup_tb ( __int64 @@a1@@ ) { __int64 @@result@@ ; tcg_gen_movi_i32 ( qword_4BEB8 , * ( _QWORD * ) ( @@a1@@ + Number ) ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "result", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 701 |
[
"{\"name\": \"tcg_gen_movi_i32\", \"code\": \"__int64 __fastcall tcg_gen_movi_i32 ( __int64 @@a1@@ , int @@a2@@ ) { return tcg_gen_op2i_i32 ( Number , @@a1@@ , @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "gen_hlt", "code": "__int64 __fastcall gen_hlt ( __int64 @@a1@@ , int @@a2@@ ) { int v2 ; __int64 result ; if ( ( unsigned __int8 ) semihosting_enabled ( ) && * ( _DWORD * ) ( @@a1@@ + Number ) && ( ! * ( _DWORD * ) ( @@a1@@ + Number ) ? ( v2 = Number ) : ( v2 = Number ) , v2 == @@a2@@ ) ) { result = gen_exception_internal_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number ) ; } else { result = unallocated_encoding ( @@a1@@ ) ; } return result ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}]}
|
[{"n": "s", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "imm", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 702 |
[
"{\"name\": \"gen_exception\", \"code\": \"__int64 __fastcall gen_exception ( unsigned int @@a1@@ , unsigned int @@a2@@ , unsigned int @@a3@@ ) { __int64 @@v5@@ ; __int64 @@v6@@ ; __int64 @@v7@@ ; @@v5@@ = tcg_const_i32 ( @@a1@@ ) ; @@v6@@ = tcg_const_i32 ( @@a2@@ ) ; @@v7@@ = tcg_const_i32 ( @@a3@@ ) ; gen_helper_exception_with_syndrome ( cpu_env , @@v5@@ , @@v6@@ , @@v7@@ ) ; tcg_temp_free_i32 ( @@v7@@ ) ; tcg_temp_free_i32 ( @@v6@@ ) ; return tcg_temp_free_i32 ( @@v5@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s16\"}, {\"n\": \"v5\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s24\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_exception_internal\", \"code\": \"__int64 __fastcall gen_exception_internal ( unsigned int @@a1@@ ) { __int64 @@v2@@ ; @@v2@@ = tcg_const_i32 ( @@a1@@ ) ; if ( ! excp_is_internal ( @@a1@@ ) ) _assert_fail ( String , String , Number , String ) ; gen_helper_exception_internal ( cpu_env , @@v2@@ ) ; return tcg_temp_free_i32 ( @@v2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"gen_exception_internal_insn\", \"code\": \"__int64 __fastcall gen_exception_internal_insn ( __int64 @@a1@@ , int @@a2@@ , unsigned int @@a3@@ ) { __int64 @@result@@ ; gen_set_condexec ( @@a1@@ ) ; gen_set_pc_im ( @@a1@@ , @@a2@@ ) ; gen_exception_internal ( @@a3@@ ) ; @@result@@ = @@a1@@ ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; return @@result@@ ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"result\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"unallocated_encoding\", \"code\": \"__int64 __fastcall unallocated_encoding ( __int64 @@a1@@ ) { unsigned int @@v1@@ ; unsigned int @@v2@@ ; @@v1@@ = default_exception_el ( @@a1@@ ) ; @@v2@@ = syn_uncategorized ( ) ; return gen_exception_insn ( @@a1@@ , * ( _QWORD * ) ( @@a1@@ + Number ) , Number , @@v2@@ , @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r32\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r8\"}]}"
] |
{"name": "get_fpstatus_ptr", "code": "__int64 __fastcall get_fpstatus_ptr ( int @@a1@@ ) { int @@v2@@ ; __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_ptr ( ) ; if ( @@a1@@ ) @@v2@@ = Number ; else @@v2@@ = Number ; tcg_gen_addi_ptr ( @@v3@@ , cpu_env , @@v2@@ ) ; return @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "v2", "t": {"T": 1, "n": "int", "s": 4}, "location": "s12"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "neon", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "offset", "t": {"T": 1, "n": "int", "s": 4}, "location": "s12"}, {"n": "statusptr", "t": {"T": 3, "t": "TCGv_ptr_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 703 |
[
"{\"name\": \"tcg_temp_new_ptr\", \"code\": \"__int64 tcg_temp_new_ptr ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_ptr ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_addi_ptr\", \"code\": \"__int64 __fastcall tcg_gen_addi_ptr ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_addi_i64 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}"
] |
{"name": "vfp_reg_offset", "code": "__int64 __fastcall vfp_reg_offset ( char @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v3@@ ; if ( @@a1@@ ) return Number * ( Number * ( ( @@a2@@ >> Number ) + Number L ) + ( @@a2@@ & Number ) ) ; @@v3@@ = Number * ( Number * ( ( @@a2@@ >> Number ) + Number L ) + ( ( @@a2@@ >> Number ) & Number ) ) ; if ( ( @@a2@@ & Number ) != Number ) @@v3@@ += Number L ; return @@v3@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "char", "s": 1}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "dp", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r56"}, {"n": "reg", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "ofs", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 704 |
[] |
{"name": "neon_reg_offset", "code": "__int64 __fastcall neon_reg_offset ( int @@a1@@ , int @@a2@@ ) { return vfp_reg_offset ( Number , Number * @@a1@@ + @@a2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}]}
|
[{"n": "reg", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "n", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 705 |
[
"{\"name\": \"vfp_reg_offset\", \"code\": \"__int64 __fastcall vfp_reg_offset ( char @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v3@@ ; if ( @@a1@@ ) return Number * ( Number * ( ( @@a2@@ >> Number ) + Number L ) + ( @@a2@@ & Number ) ) ; @@v3@@ = Number * ( Number * ( ( @@a2@@ >> Number ) + Number L ) + ( ( @@a2@@ >> Number ) & Number ) ) ; if ( ( @@a2@@ & Number ) != Number ) @@v3@@ += Number L ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "neon_element_offset", "code": "__int64 __fastcall neon_element_offset ( int @@a1@@ , int @@a2@@ , char @@a3@@ ) { return ( Number << @@a3@@ ) * @@a2@@ + neon_reg_offset ( @@a1@@ , Number ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "char", "s": 1}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}]}
|
[{"n": "size", "t": {"T": 1, "n": "MemOp_0", "s": 4}, "location": "r16"}, {"n": "reg", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "element", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 706 |
[
"{\"name\": \"neon_reg_offset\", \"code\": \"__int64 __fastcall neon_reg_offset ( int @@a1@@ , int @@a2@@ ) { return vfp_reg_offset ( Number , Number * @@a1@@ + @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "neon_load_reg", "code": "__int64 __fastcall neon_load_reg ( int @@a1@@ , int @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v2@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_ld_i32 ( @@v4@@ , cpu_env , @@v2@@ ) ; return @@v4@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "reg", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "pass", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}, {"n": "tmp", "t": {"T": 3, "t": "TCGv_i32_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 707 |
[
"{\"name\": \"tcg_temp_new_i32\", \"code\": \"__int64 tcg_temp_new_i32 ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_i32 ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_ld_i32\", \"code\": \"__int64 __fastcall tcg_gen_ld_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_reg_offset\", \"code\": \"__int64 __fastcall neon_reg_offset ( int @@a1@@ , int @@a2@@ ) { return vfp_reg_offset ( Number , Number * @@a1@@ + @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "neon_load_element", "code": "__int64 __fastcall neon_load_element ( __int64 @@a1@@ , int @@a2@@ , int @@a3@@ , unsigned int @@a4@@ ) { __int64 @@v6@@ ; @@v6@@ = neon_element_offset ( @@a2@@ , @@a3@@ , @@a4@@ & Number ) ; if ( @@a4@@ == Number ) return tcg_gen_ld_i32 ( @@a1@@ , cpu_env , @@v6@@ ) ; if ( @@a4@@ > Number ) return g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; if ( @@a4@@ ) return tcg_gen_ld16u_i32 ( @@a1@@ , cpu_env , @@v6@@ ) ; return tcg_gen_ld8u_i32 ( @@a1@@ , cpu_env , @@v6@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "ele", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "mop", "t": {"T": 1, "n": "MemOp_0", "s": 4}, "location": "r24"}, {"n": "var", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "reg", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "offset", "t": {"T": 1, "n": "tcg_target_long", "s": 8}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 708 |
[
"{\"name\": \"tcg_gen_ld8u_i32\", \"code\": \"__int64 __fastcall tcg_gen_ld8u_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_ld16u_i32\", \"code\": \"__int64 __fastcall tcg_gen_ld16u_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_ld_i32\", \"code\": \"__int64 __fastcall tcg_gen_ld_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"neon_element_offset\", \"code\": \"__int64 __fastcall neon_element_offset ( int @@a1@@ , int @@a2@@ , char @@a3@@ ) { return ( Number << @@a3@@ ) * @@a2@@ + neon_reg_offset ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "neon_load_element64", "code": "__int64 __fastcall neon_load_element64 ( __int64 @@a1@@ , int @@a2@@ , int @@a3@@ , unsigned int @@a4@@ ) { __int64 @@v6@@ ; @@v6@@ = neon_element_offset ( @@a2@@ , @@a3@@ , @@a4@@ & Number ) ; if ( @@a4@@ == Number ) return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , @@v6@@ ) ; if ( @@a4@@ > Number ) return g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; if ( @@a4@@ == Number ) return tcg_gen_ld32u_i64 ( @@a1@@ , cpu_env , @@v6@@ ) ; if ( @@a4@@ ) return tcg_gen_ld16u_i64 ( @@a1@@ , cpu_env , @@v6@@ ) ; return tcg_gen_ld8u_i64 ( @@a1@@ , cpu_env , @@v6@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v6", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "ele", "t": {"T": 1, "n": "int", "s": 4}, "location": "r16"}, {"n": "mop", "t": {"T": 1, "n": "MemOp_0", "s": 4}, "location": "r24"}, {"n": "var", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r56"}, {"n": "reg", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "offset", "t": {"T": 1, "n": "tcg_target_long", "s": 8}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 709 |
[
"{\"name\": \"tcg_gen_ld8u_i64\", \"code\": \"__int64 __fastcall tcg_gen_ld8u_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_ld16u_i64\", \"code\": \"__int64 __fastcall tcg_gen_ld16u_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_ld32u_i64\", \"code\": \"__int64 __fastcall tcg_gen_ld32u_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_ld_i64\", \"code\": \"__int64 __fastcall tcg_gen_ld_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"neon_element_offset\", \"code\": \"__int64 __fastcall neon_element_offset ( int @@a1@@ , int @@a2@@ , char @@a3@@ ) { return ( Number << @@a3@@ ) * @@a2@@ + neon_reg_offset ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"neon_load_element\", \"code\": \"__int64 __fastcall neon_load_element ( __int64 @@a1@@ , int @@a2@@ , int @@a3@@ , unsigned int @@a4@@ ) { __int64 @@v6@@ ; @@v6@@ = neon_element_offset ( @@a2@@ , @@a3@@ , @@a4@@ & Number ) ; if ( @@a4@@ == Number ) return tcg_gen_ld_i32 ( @@a1@@ , cpu_env , @@v6@@ ) ; if ( @@a4@@ > Number ) return g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; if ( @@a4@@ ) return tcg_gen_ld16u_i32 ( @@a1@@ , cpu_env , @@v6@@ ) ; return tcg_gen_ld8u_i32 ( @@a1@@ , cpu_env , @@v6@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v6\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "neon_store_reg", "code": "__int64 __fastcall neon_store_reg ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; @@v3@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_st_i32 ( @@a3@@ , cpu_env , @@v3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v3", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "var", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r16"}, {"n": "reg", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "pass", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 710 |
[
"{\"name\": \"tcg_temp_free_i32\", \"code\": \"__int64 __fastcall tcg_temp_free_i32 ( __int64 @@a1@@ ) { __int64 @@v1@@ ; @@v1@@ = tcgv_i32_temp ( @@a1@@ ) ; return tcg_temp_free_internal ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}",
"{\"name\": \"tcg_gen_st_i32\", \"code\": \"__int64 __fastcall tcg_gen_st_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"neon_reg_offset\", \"code\": \"__int64 __fastcall neon_reg_offset ( int @@a1@@ , int @@a2@@ ) { return vfp_reg_offset ( Number , Number * @@a1@@ + @@a2@@ ) ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "neon_store_element", "code": "__int64 __fastcall neon_store_element ( int @@a1@@ , int @@a2@@ , unsigned int @@a3@@ , __int64 @@a4@@ ) { __int64 @@v7@@ ; @@v7@@ = neon_element_offset ( @@a1@@ , @@a2@@ , @@a3@@ ) ; if ( @@a3@@ == Number ) return tcg_gen_st_i32 ( @@a4@@ , cpu_env , @@v7@@ ) ; if ( @@a3@@ > Number ) return g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; if ( @@a3@@ ) return tcg_gen_st16_i32 ( @@a4@@ , cpu_env , @@v7@@ ) ; return tcg_gen_st8_i32 ( @@a4@@ , cpu_env , @@v7@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "size", "t": {"T": 1, "n": "MemOp_0", "s": 4}, "location": "r16"}, {"n": "var", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r24"}, {"n": "reg", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "ele", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "offset", "t": {"T": 1, "n": "tcg_target_long", "s": 8}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 711 |
[
"{\"name\": \"tcg_gen_st8_i32\", \"code\": \"__int64 __fastcall tcg_gen_st8_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_st16_i32\", \"code\": \"__int64 __fastcall tcg_gen_st16_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_st_i32\", \"code\": \"__int64 __fastcall tcg_gen_st_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"neon_element_offset\", \"code\": \"__int64 __fastcall neon_element_offset ( int @@a1@@ , int @@a2@@ , char @@a3@@ ) { return ( Number << @@a3@@ ) * @@a2@@ + neon_reg_offset ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}"
] |
{"name": "neon_store_element64", "code": "__int64 __fastcall neon_store_element64 ( int @@a1@@ , int @@a2@@ , unsigned int @@a3@@ , __int64 @@a4@@ ) { __int64 @@v7@@ ; @@v7@@ = neon_element_offset ( @@a1@@ , @@a2@@ , @@a3@@ ) ; if ( @@a3@@ == Number ) return tcg_gen_st_i64 ( @@a4@@ , cpu_env , @@v7@@ ) ; if ( @@a3@@ > Number ) return g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; if ( @@a3@@ == Number ) return tcg_gen_st32_i64 ( @@a4@@ , cpu_env , @@v7@@ ) ; if ( @@a3@@ ) return tcg_gen_st16_i64 ( @@a4@@ , cpu_env , @@v7@@ ) ; return tcg_gen_st8_i64 ( @@a4@@ , cpu_env , @@v7@@ ) ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "a4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r24"}, {"n": "a1", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "v7", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "size", "t": {"T": 1, "n": "MemOp_0", "s": 4}, "location": "r16"}, {"n": "var", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r24"}, {"n": "reg", "t": {"T": 1, "n": "int", "s": 4}, "location": "r56"}, {"n": "ele", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "offset", "t": {"T": 1, "n": "tcg_target_long", "s": 8}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 712 |
[
"{\"name\": \"tcg_gen_st8_i64\", \"code\": \"__int64 __fastcall tcg_gen_st8_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_st16_i64\", \"code\": \"__int64 __fastcall tcg_gen_st16_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_st32_i64\", \"code\": \"__int64 __fastcall tcg_gen_st32_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"tcg_gen_st_i64\", \"code\": \"__int64 __fastcall tcg_gen_st_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"neon_element_offset\", \"code\": \"__int64 __fastcall neon_element_offset ( int @@a1@@ , int @@a2@@ , char @@a3@@ ) { return ( Number << @@a3@@ ) * @@a2@@ + neon_reg_offset ( @@a1@@ , Number ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"neon_store_element\", \"code\": \"__int64 __fastcall neon_store_element ( int @@a1@@ , int @@a2@@ , unsigned int @@a3@@ , __int64 @@a4@@ ) { __int64 @@v7@@ ; @@v7@@ = neon_element_offset ( @@a1@@ , @@a2@@ , @@a3@@ ) ; if ( @@a3@@ == Number ) return tcg_gen_st_i32 ( @@a4@@ , cpu_env , @@v7@@ ) ; if ( @@a3@@ > Number ) return g_assertion_message_expr ( Number L , String , Number L , String , Number L ) ; if ( @@a3@@ ) return tcg_gen_st16_i32 ( @@a4@@ , cpu_env , @@v7@@ ) ; return tcg_gen_st8_i32 ( @@a4@@ , cpu_env , @@v7@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v7\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "neon_load_reg64", "code": "__int64 __fastcall neon_load_reg64 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_ld_i64 ( @@a1@@ , cpu_env , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "var", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r56"}, {"n": "reg", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 713 |
[
"{\"name\": \"tcg_gen_ld_i64\", \"code\": \"__int64 __fastcall tcg_gen_ld_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"vfp_reg_offset\", \"code\": \"__int64 __fastcall vfp_reg_offset ( char @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v3@@ ; if ( @@a1@@ ) return Number * ( Number * ( ( @@a2@@ >> Number ) + Number L ) + ( @@a2@@ & Number ) ) ; @@v3@@ = Number * ( Number * ( ( @@a2@@ >> Number ) + Number L ) + ( ( @@a2@@ >> Number ) & Number ) ) ; if ( ( @@a2@@ & Number ) != Number ) @@v3@@ += Number L ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_load_reg\", \"code\": \"__int64 __fastcall neon_load_reg ( int @@a1@@ , int @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v2@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_ld_i32 ( @@v4@@ , cpu_env , @@v2@@ ) ; return @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "neon_store_reg64", "code": "__int64 __fastcall neon_store_reg64 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_st_i64 ( @@a1@@ , cpu_env , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "var", "t": {"T": 1, "n": "TCGv_i64", "s": 8}, "location": "r56"}, {"n": "reg", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 714 |
[
"{\"name\": \"tcg_gen_st_i64\", \"code\": \"__int64 __fastcall tcg_gen_st_i64 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i64 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"vfp_reg_offset\", \"code\": \"__int64 __fastcall vfp_reg_offset ( char @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v3@@ ; if ( @@a1@@ ) return Number * ( Number * ( ( @@a2@@ >> Number ) + Number L ) + ( @@a2@@ & Number ) ) ; @@v3@@ = Number * ( Number * ( ( @@a2@@ >> Number ) + Number L ) + ( ( @@a2@@ >> Number ) & Number ) ) ; if ( ( @@a2@@ & Number ) != Number ) @@v3@@ += Number L ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_store_reg\", \"code\": \"__int64 __fastcall neon_store_reg ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; @@v3@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_st_i32 ( @@a3@@ , cpu_env , @@v3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "neon_load_reg32", "code": "__int64 __fastcall neon_load_reg32 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_ld_i32 ( @@a1@@ , cpu_env , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "var", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "reg", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 715 |
[
"{\"name\": \"tcg_gen_ld_i32\", \"code\": \"__int64 __fastcall tcg_gen_ld_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"load_reg\", \"code\": \"__int64 __fastcall load_reg ( __int64 @@a1@@ , int @@a2@@ ) { __int64 @@v3@@ ; @@v3@@ = tcg_temp_new_i32 ( ) ; load_reg_var ( @@a1@@ , @@v3@@ , @@a2@@ ) ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"vfp_reg_offset\", \"code\": \"__int64 __fastcall vfp_reg_offset ( char @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v3@@ ; if ( @@a1@@ ) return Number * ( Number * ( ( @@a2@@ >> Number ) + Number L ) + ( @@a2@@ & Number ) ) ; @@v3@@ = Number * ( Number * ( ( @@a2@@ >> Number ) + Number L ) + ( ( @@a2@@ >> Number ) & Number ) ) ; if ( ( @@a2@@ & Number ) != Number ) @@v3@@ += Number L ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_load_reg\", \"code\": \"__int64 __fastcall neon_load_reg ( int @@a1@@ , int @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; @@v4@@ = tcg_temp_new_i32 ( ) ; @@v2@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_ld_i32 ( @@v4@@ , cpu_env , @@v2@@ ) ; return @@v4@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}, {\"n\": \"v4\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "neon_store_reg32", "code": "__int64 __fastcall neon_store_reg32 ( __int64 @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; @@v2@@ = vfp_reg_offset ( Number , @@a2@@ ) ; return tcg_gen_st_i32 ( @@a1@@ , cpu_env , @@v2@@ ) ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}]}
|
[{"n": "var", "t": {"T": 1, "n": "TCGv_i32", "s": 8}, "location": "r56"}, {"n": "reg", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 716 |
[
"{\"name\": \"tcg_gen_st_i32\", \"code\": \"__int64 __fastcall tcg_gen_st_i32 ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_ldst_op_i32 ( Number , @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"store_reg\", \"code\": \"__int64 __fastcall store_reg ( __int64 @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 v3 ; if ( @@a2@@ == Number ) { if ( * ( _DWORD * ) ( @@a1@@ + Number ) ) v3 = Number L ; else v3 = Number L ; tcg_gen_andi_i32 ( @@a3@@ , @@a3@@ , v3 ) ; * ( _DWORD * ) ( @@a1@@ + Number ) = Number ; } tcg_gen_mov_i32 ( cpu_R [ @@a2@@ ] , @@a3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"vfp_reg_offset\", \"code\": \"__int64 __fastcall vfp_reg_offset ( char @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v3@@ ; if ( @@a1@@ ) return Number * ( Number * ( ( @@a2@@ >> Number ) + Number L ) + ( @@a2@@ & Number ) ) ; @@v3@@ = Number * ( Number * ( ( @@a2@@ >> Number ) + Number L ) + ( ( @@a2@@ >> Number ) & Number ) ) ; if ( ( @@a2@@ & Number ) != Number ) @@v3@@ += Number L ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"neon_store_reg\", \"code\": \"__int64 __fastcall neon_store_reg ( int @@a1@@ , int @@a2@@ , __int64 @@a3@@ ) { __int64 @@v3@@ ; @@v3@@ = neon_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_st_i32 ( @@a3@@ , cpu_env , @@v3@@ ) ; return tcg_temp_free_i32 ( @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r8\"}]}"
] |
{"name": "vfp_reg_ptr", "code": "__int64 __fastcall vfp_reg_ptr ( char @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v2@@ ; __int64 @@v4@@ ; @@v4@@ = tcg_temp_new_ptr ( ) ; @@v2@@ = vfp_reg_offset ( @@a1@@ , @@a2@@ ) ; tcg_gen_addi_ptr ( @@v4@@ , cpu_env , @@v2@@ ) ; return @@v4@@ ; }", "source": [{"n": "a1", "t": {"T": 1, "n": "char", "s": 1}, "location": "r56"}, {"n": "a2", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r64"}, {"n": "v2", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r8"}, {"n": "v4", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "s8"}]}
|
[{"n": "dp", "t": {"T": 1, "n": "bool", "s": 1}, "location": "r56"}, {"n": "reg", "t": {"T": 1, "n": "int", "s": 4}, "location": "r64"}, {"n": "", "t": {"T": 10}, "location": "r8"}, {"n": "ret", "t": {"T": 3, "t": "TCGv_ptr_d"}, "location": "s8"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 717 |
[
"{\"name\": \"tcg_temp_new_ptr\", \"code\": \"__int64 tcg_temp_new_ptr ( ) { __int64 @@v1@@ ; @@v1@@ = tcg_temp_new_internal ( Number L , Number L ) ; return temp_tcgv_ptr ( @@v1@@ ) ; }\", \"source\": [{\"n\": \"v1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}",
"{\"name\": \"tcg_gen_addi_ptr\", \"code\": \"__int64 __fastcall tcg_gen_addi_ptr ( __int64 @@a1@@ , __int64 @@a2@@ , __int64 @@a3@@ ) { return tcg_gen_addi_i64 ( @@a1@@ , @@a2@@ , @@a3@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r64\"}]}",
"{\"name\": \"vfp_reg_offset\", \"code\": \"__int64 __fastcall vfp_reg_offset ( char @@a1@@ , unsigned int @@a2@@ ) { __int64 @@v3@@ ; if ( @@a1@@ ) return Number * ( Number * ( ( @@a2@@ >> Number ) + Number L ) + ( @@a2@@ & Number ) ) ; @@v3@@ = Number * ( Number * ( ( @@a2@@ >> Number ) + Number L ) + ( ( @@a2@@ >> Number ) & Number ) ) ; if ( ( @@a2@@ & Number ) != Number ) @@v3@@ += Number L ; return @@v3@@ ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"char\", \"s\": 1}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v3\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "disas_vfp_extract_disas_vfp_Fmt_0", "code": "_DWORD * __fastcall disas_vfp_extract_disas_vfp_Fmt_0 ( __int64 @@a1@@ , _DWORD * @@a2@@ , unsigned int @@a3@@ ) { int v3 ; int v4 ; int v5 ; int v6 ; int v7 ; _DWORD * result ; @@a2@@ [ Number ] = extract32 ( @@a3@@ , Number , Number ) ; @@a2@@ [ Number ] = extract32 ( @@a3@@ , Number , Number ) ; v3 = extract32 ( @@a3@@ , Number , Number ) ; v4 = extract32 ( @@a3@@ , Number , Number ) ; @@a2@@ [ Number ] = deposit32 ( v4 , Number , Number , v3 ) ; @@a2@@ [ Number ] = Number ; v5 = extract32 ( @@a3@@ , Number , Number ) ; v6 = extract32 ( @@a3@@ , Number , Number ) ; v7 = deposit32 ( v6 , Number , Number , v5 ) ; result = @@a2@@ ; * @@a2@@ = v7 ; return result ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}]}
|
[{"n": "insn", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r16"}, {"n": "ctx", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_disas_vfp0"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 718 |
[
"{\"name\": \"extract32\", \"code\": \"__int64 __fastcall extract32 ( unsigned int @@a1@@ , int @@a2@@ , int @@a3@@ ) { if ( @@a2@@ < Number || @@a3@@ <= Number || @@a3@@ > Number - @@a2@@ ) _assert_fail ( String , String , Number , String ) ; return ( @@a1@@ >> @@a2@@ ) & ( Number >> ( Number - @@a3@@ ) ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"deposit32\", \"code\": \"__int64 __fastcall deposit32 ( int @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ ) { if ( @@a2@@ < Number || @@a3@@ <= Number || @@a3@@ > Number - @@a2@@ ) _assert_fail ( String , String , Number , String ) ; return @@a1@@ & ~ ( Number >> ( Number - @@a3@@ ) << @@a2@@ ) | ( Number >> ( Number - @@a3@@ ) << @@a2@@ ) & ( @@a4@@ << @@a2@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"disas_vfp\", \"code\": \"_BOOL8 __fastcall disas_vfp ( __int64 @@a1@@ , unsigned int @@a2@@ ) { unsigned int v2 ; _BOOL8 result ; unsigned int v4 ; unsigned int v5 ; unsigned int v6 ; unsigned int v7 ; unsigned int v8 ; unsigned int v9 ; unsigned int v10 ; unsigned int v11 ; unsigned int v12 ; unsigned int v13 ; unsigned int v14 ; unsigned int v15 ; _DWORD @@v16@@ [ Number ] ; unsigned __int64 @@v17@@ ; @@v17@@ = __readfsqword ( Number ) ; v2 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { v10 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_0 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VMOV_to_gp ( @@a1@@ , @@v16@@ ) != Number ; } else { result = Number L ; } } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_1 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VMOV_to_gp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_2 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VMOV_to_gp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v10 != Number ) { if ( v10 <= Number ) { if ( ! v10 ) { v11 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_22 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VFM_dp ( @@a1@@ , @@v16@@ ) != Number ; } if ( v11 != Number ) { if ( v11 <= Number ) { if ( ! v11 ) { disas_vfp_extract_disas_vfp_Fmt_18 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VMLS_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VMLA_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } if ( v11 == Number ) { disas_vfp_extract_disas_vfp_Fmt_18 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VNMUL_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VMUL_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } } return Number L ; } disas_vfp_extract_disas_vfp_Fmt_18 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VDIV_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } if ( v10 == Number ) { if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_6 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VDUP ( @@a1@@ , @@v16@@ ) != Number ; } else { result = Number L ; } } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_3 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VMOV_from_gp ( @@a1@@ , @@v16@@ ) != Number ; } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_4 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VMOV_from_gp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_5 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VMOV_from_gp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } } return Number L ; } v12 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != Number ) { if ( v12 == Number ) { disas_vfp_extract_disas_vfp_Fmt_20 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VFM_dp ( @@a1@@ , @@v16@@ ) != Number ; } if ( v12 <= Number ) { if ( ! v12 ) { disas_vfp_extract_disas_vfp_Fmt_18 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VNMLA_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VNMLS_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } if ( v12 == Number ) { disas_vfp_extract_disas_vfp_Fmt_18 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VSUB_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VADD_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } } return Number L ; } if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_24 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VMOV_imm_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } v13 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_37 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_fix_dp ( @@a1@@ , @@v16@@ ) != Number ; } if ( v13 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_39 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VCVT_dp_int ( @@a1@@ , @@v16@@ ) != Number ; } else if ( ( @@a2@@ & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_33 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) result = ( unsigned __int8 ) trans_VJCVT ( @@a1@@ , @@v16@@ ) != Number ; else result = Number L ; } else { disas_vfp_extract_disas_vfp_Fmt_35 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VCVT_int_dp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v13 > Number ) return Number L ; if ( ! v13 ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_28 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCMP_dp ( @@a1@@ , @@v16@@ ) != Number ; } disas_vfp_extract_disas_vfp_Fmt_26 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; v14 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_VSQRT_dp ( @@a1@@ , @@v16@@ ) != Number ; if ( v14 == Number ) return ( unsigned __int8 ) trans_VNEG_dp ( @@a1@@ , @@v16@@ ) != Number ; if ( v14 > Number ) goto LABEL_195 ; if ( ! v14 ) return ( unsigned __int8 ) trans_VMOV_reg_dp ( @@a1@@ , @@v16@@ ) != Number ; if ( v14 == Number ) result = ( unsigned __int8 ) trans_VABS_dp ( @@a1@@ , @@v16@@ ) != Number ; else LABEL_195 : result = Number L ; return result ; } if ( v13 != ( _DWORD ) & loc_20000 ) return Number L ; v15 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != ( _DWORD ) & unk_50000 ) { if ( v15 <= ( unsigned int ) & unk_50000 ) { if ( v15 == Number ) { disas_vfp_extract_disas_vfp_Fmt_26 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VRINTZ_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VRINTR_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } if ( v15 <= Number ) { if ( ! v15 ) { disas_vfp_extract_disas_vfp_Fmt_30 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_f64_f16 ( @@a1@@ , @@v16@@ ) != Number ; } if ( v15 == Number ) { disas_vfp_extract_disas_vfp_Fmt_31 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_f16_f64 ( @@a1@@ , @@v16@@ ) != Number ; } } } return Number L ; } if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_33 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VCVT_dp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_26 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VRINTX_dp ( @@a1@@ , @@v16@@ ) != Number ; } } else { if ( v2 > Number ) return Number L ; if ( v2 != Number ) { if ( v2 <= Number ) { if ( v2 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_16 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VLDM_VSTM_dp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_12 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VLDR_VSTR_dp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v2 <= Number ) { if ( v2 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_15 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VLDM_VSTM_sp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_11 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VLDR_VSTR_sp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v2 <= Number ) { if ( v2 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_13 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VLDM_VSTM_sp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_9 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_VMOV_64_sp ( @@a1@@ , @@v16@@ ) != Number ; else result = Number L ; } } else { if ( v2 != Number ) return Number L ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_14 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VLDM_VSTM_dp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_10 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_VMOV_64_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = Number L ; } } return result ; } } } return Number L ; } v4 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_7 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_VMSR_VMRS ( @@a1@@ , @@v16@@ ) != Number ; else result = Number L ; return result ; } if ( v4 != Number ) { if ( v4 <= Number ) { if ( v4 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_19 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VFM_sp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_17 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VDIV_sp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v4 <= Number ) { if ( v4 == Number ) { disas_vfp_extract_disas_vfp_Fmt_17 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; v6 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_VSUB_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v6 == Number ) return ( unsigned __int8 ) trans_VADD_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v6 > Number ) goto LABEL_66 ; if ( ! v6 ) return ( unsigned __int8 ) trans_VMUL_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v6 == Number ) result = ( unsigned __int8 ) trans_VNMUL_sp ( @@a1@@ , @@v16@@ ) != Number ; else LABEL_66 : result = Number L ; return result ; } if ( v4 <= Number ) { if ( ! v4 ) { disas_vfp_extract_disas_vfp_Fmt_17 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; v5 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_VNMLA_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v5 == Number ) return ( unsigned __int8 ) trans_VNMLS_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v5 > Number ) goto LABEL_52 ; if ( ! v5 ) return ( unsigned __int8 ) trans_VMLA_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v5 == Number ) result = ( unsigned __int8 ) trans_VMLS_sp ( @@a1@@ , @@v16@@ ) != Number ; else LABEL_52 : result = Number L ; return result ; } if ( v4 == Number ) { disas_vfp_extract_disas_vfp_Fmt_8 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VMOV_single ( @@a1@@ , @@v16@@ ) != Number ; return result ; } } } } return Number L ; } if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_21 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VFM_sp ( @@a1@@ , @@v16@@ ) != Number ; } if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_23 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VMOV_imm_sp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } v7 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_36 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_fix_sp ( @@a1@@ , @@v16@@ ) != Number ; } if ( v7 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_38 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VCVT_sp_int ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_34 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VCVT_int_sp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v7 > Number ) return Number L ; if ( ! v7 ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_27 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCMP_sp ( @@a1@@ , @@v16@@ ) != Number ; } disas_vfp_extract_disas_vfp_Fmt_25 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; v8 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_VSQRT_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v8 == Number ) return ( unsigned __int8 ) trans_VNEG_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v8 > Number ) goto LABEL_96 ; if ( ! v8 ) return ( unsigned __int8 ) trans_VMOV_reg_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v8 == Number ) result = ( unsigned __int8 ) trans_VABS_sp ( @@a1@@ , @@v16@@ ) != Number ; else LABEL_96 : result = Number L ; return result ; } if ( v7 != ( _DWORD ) & loc_20000 ) return Number L ; v9 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != ( _DWORD ) & unk_50000 ) { if ( v9 <= ( unsigned int ) & unk_50000 ) { if ( v9 == Number ) { disas_vfp_extract_disas_vfp_Fmt_25 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VRINTZ_sp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VRINTR_sp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } if ( v9 <= Number ) { if ( ! v9 ) { disas_vfp_extract_disas_vfp_Fmt_29 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_f32_f16 ( @@a1@@ , @@v16@@ ) != Number ; } if ( v9 == Number ) { disas_vfp_extract_disas_vfp_Fmt_29 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_f16_f32 ( @@a1@@ , @@v16@@ ) != Number ; } } } return Number L ; } if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_32 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VCVT_sp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_25 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VRINTX_sp ( @@a1@@ , @@v16@@ ) != Number ; } } return result ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v16\", \"t\": {\"T\": 2, \"n\": 10, \"s\": 4, \"t\": \"_DWORD\"}, \"location\": \"s48\"}, {\"n\": \"v17\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "disas_vfp_extract_disas_vfp_Fmt_1", "code": "_DWORD * __fastcall disas_vfp_extract_disas_vfp_Fmt_1 ( __int64 @@a1@@ , _DWORD * @@a2@@ , unsigned int @@a3@@ ) { int v3 ; int v4 ; int v5 ; int v6 ; int v7 ; _DWORD * result ; @@a2@@ [ Number ] = extract32 ( @@a3@@ , Number , Number ) ; @@a2@@ [ Number ] = extract32 ( @@a3@@ , Number , Number ) ; v3 = extract32 ( @@a3@@ , Number , Number ) ; v4 = extract32 ( @@a3@@ , Number , Number ) ; @@a2@@ [ Number ] = deposit32 ( v4 , Number , Number , v3 ) ; @@a2@@ [ Number ] = Number ; v5 = extract32 ( @@a3@@ , Number , Number ) ; v6 = extract32 ( @@a3@@ , Number , Number ) ; v7 = deposit32 ( v6 , Number , Number , v5 ) ; result = @@a2@@ ; * @@a2@@ = v7 ; return result ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}]}
|
[{"n": "insn", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r16"}, {"n": "ctx", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_disas_vfp0"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 719 |
[
"{\"name\": \"extract32\", \"code\": \"__int64 __fastcall extract32 ( unsigned int @@a1@@ , int @@a2@@ , int @@a3@@ ) { if ( @@a2@@ < Number || @@a3@@ <= Number || @@a3@@ > Number - @@a2@@ ) _assert_fail ( String , String , Number , String ) ; return ( @@a1@@ >> @@a2@@ ) & ( Number >> ( Number - @@a3@@ ) ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"deposit32\", \"code\": \"__int64 __fastcall deposit32 ( int @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ ) { if ( @@a2@@ < Number || @@a3@@ <= Number || @@a3@@ > Number - @@a2@@ ) _assert_fail ( String , String , Number , String ) ; return @@a1@@ & ~ ( Number >> ( Number - @@a3@@ ) << @@a2@@ ) | ( Number >> ( Number - @@a3@@ ) << @@a2@@ ) & ( @@a4@@ << @@a2@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"disas_vfp\", \"code\": \"_BOOL8 __fastcall disas_vfp ( __int64 @@a1@@ , unsigned int @@a2@@ ) { unsigned int v2 ; _BOOL8 result ; unsigned int v4 ; unsigned int v5 ; unsigned int v6 ; unsigned int v7 ; unsigned int v8 ; unsigned int v9 ; unsigned int v10 ; unsigned int v11 ; unsigned int v12 ; unsigned int v13 ; unsigned int v14 ; unsigned int v15 ; _DWORD @@v16@@ [ Number ] ; unsigned __int64 @@v17@@ ; @@v17@@ = __readfsqword ( Number ) ; v2 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { v10 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_0 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VMOV_to_gp ( @@a1@@ , @@v16@@ ) != Number ; } else { result = Number L ; } } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_1 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VMOV_to_gp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_2 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VMOV_to_gp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v10 != Number ) { if ( v10 <= Number ) { if ( ! v10 ) { v11 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_22 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VFM_dp ( @@a1@@ , @@v16@@ ) != Number ; } if ( v11 != Number ) { if ( v11 <= Number ) { if ( ! v11 ) { disas_vfp_extract_disas_vfp_Fmt_18 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VMLS_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VMLA_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } if ( v11 == Number ) { disas_vfp_extract_disas_vfp_Fmt_18 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VNMUL_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VMUL_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } } return Number L ; } disas_vfp_extract_disas_vfp_Fmt_18 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VDIV_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } if ( v10 == Number ) { if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_6 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VDUP ( @@a1@@ , @@v16@@ ) != Number ; } else { result = Number L ; } } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_3 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VMOV_from_gp ( @@a1@@ , @@v16@@ ) != Number ; } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_4 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VMOV_from_gp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_5 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VMOV_from_gp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } } return Number L ; } v12 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != Number ) { if ( v12 == Number ) { disas_vfp_extract_disas_vfp_Fmt_20 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VFM_dp ( @@a1@@ , @@v16@@ ) != Number ; } if ( v12 <= Number ) { if ( ! v12 ) { disas_vfp_extract_disas_vfp_Fmt_18 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VNMLA_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VNMLS_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } if ( v12 == Number ) { disas_vfp_extract_disas_vfp_Fmt_18 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VSUB_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VADD_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } } return Number L ; } if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_24 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VMOV_imm_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } v13 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_37 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_fix_dp ( @@a1@@ , @@v16@@ ) != Number ; } if ( v13 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_39 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VCVT_dp_int ( @@a1@@ , @@v16@@ ) != Number ; } else if ( ( @@a2@@ & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_33 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) result = ( unsigned __int8 ) trans_VJCVT ( @@a1@@ , @@v16@@ ) != Number ; else result = Number L ; } else { disas_vfp_extract_disas_vfp_Fmt_35 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VCVT_int_dp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v13 > Number ) return Number L ; if ( ! v13 ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_28 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCMP_dp ( @@a1@@ , @@v16@@ ) != Number ; } disas_vfp_extract_disas_vfp_Fmt_26 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; v14 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_VSQRT_dp ( @@a1@@ , @@v16@@ ) != Number ; if ( v14 == Number ) return ( unsigned __int8 ) trans_VNEG_dp ( @@a1@@ , @@v16@@ ) != Number ; if ( v14 > Number ) goto LABEL_195 ; if ( ! v14 ) return ( unsigned __int8 ) trans_VMOV_reg_dp ( @@a1@@ , @@v16@@ ) != Number ; if ( v14 == Number ) result = ( unsigned __int8 ) trans_VABS_dp ( @@a1@@ , @@v16@@ ) != Number ; else LABEL_195 : result = Number L ; return result ; } if ( v13 != ( _DWORD ) & loc_20000 ) return Number L ; v15 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != ( _DWORD ) & unk_50000 ) { if ( v15 <= ( unsigned int ) & unk_50000 ) { if ( v15 == Number ) { disas_vfp_extract_disas_vfp_Fmt_26 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VRINTZ_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VRINTR_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } if ( v15 <= Number ) { if ( ! v15 ) { disas_vfp_extract_disas_vfp_Fmt_30 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_f64_f16 ( @@a1@@ , @@v16@@ ) != Number ; } if ( v15 == Number ) { disas_vfp_extract_disas_vfp_Fmt_31 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_f16_f64 ( @@a1@@ , @@v16@@ ) != Number ; } } } return Number L ; } if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_33 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VCVT_dp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_26 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VRINTX_dp ( @@a1@@ , @@v16@@ ) != Number ; } } else { if ( v2 > Number ) return Number L ; if ( v2 != Number ) { if ( v2 <= Number ) { if ( v2 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_16 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VLDM_VSTM_dp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_12 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VLDR_VSTR_dp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v2 <= Number ) { if ( v2 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_15 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VLDM_VSTM_sp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_11 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VLDR_VSTR_sp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v2 <= Number ) { if ( v2 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_13 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VLDM_VSTM_sp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_9 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_VMOV_64_sp ( @@a1@@ , @@v16@@ ) != Number ; else result = Number L ; } } else { if ( v2 != Number ) return Number L ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_14 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VLDM_VSTM_dp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_10 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_VMOV_64_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = Number L ; } } return result ; } } } return Number L ; } v4 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_7 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_VMSR_VMRS ( @@a1@@ , @@v16@@ ) != Number ; else result = Number L ; return result ; } if ( v4 != Number ) { if ( v4 <= Number ) { if ( v4 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_19 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VFM_sp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_17 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VDIV_sp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v4 <= Number ) { if ( v4 == Number ) { disas_vfp_extract_disas_vfp_Fmt_17 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; v6 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_VSUB_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v6 == Number ) return ( unsigned __int8 ) trans_VADD_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v6 > Number ) goto LABEL_66 ; if ( ! v6 ) return ( unsigned __int8 ) trans_VMUL_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v6 == Number ) result = ( unsigned __int8 ) trans_VNMUL_sp ( @@a1@@ , @@v16@@ ) != Number ; else LABEL_66 : result = Number L ; return result ; } if ( v4 <= Number ) { if ( ! v4 ) { disas_vfp_extract_disas_vfp_Fmt_17 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; v5 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_VNMLA_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v5 == Number ) return ( unsigned __int8 ) trans_VNMLS_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v5 > Number ) goto LABEL_52 ; if ( ! v5 ) return ( unsigned __int8 ) trans_VMLA_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v5 == Number ) result = ( unsigned __int8 ) trans_VMLS_sp ( @@a1@@ , @@v16@@ ) != Number ; else LABEL_52 : result = Number L ; return result ; } if ( v4 == Number ) { disas_vfp_extract_disas_vfp_Fmt_8 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VMOV_single ( @@a1@@ , @@v16@@ ) != Number ; return result ; } } } } return Number L ; } if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_21 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VFM_sp ( @@a1@@ , @@v16@@ ) != Number ; } if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_23 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VMOV_imm_sp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } v7 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_36 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_fix_sp ( @@a1@@ , @@v16@@ ) != Number ; } if ( v7 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_38 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VCVT_sp_int ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_34 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VCVT_int_sp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v7 > Number ) return Number L ; if ( ! v7 ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_27 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCMP_sp ( @@a1@@ , @@v16@@ ) != Number ; } disas_vfp_extract_disas_vfp_Fmt_25 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; v8 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_VSQRT_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v8 == Number ) return ( unsigned __int8 ) trans_VNEG_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v8 > Number ) goto LABEL_96 ; if ( ! v8 ) return ( unsigned __int8 ) trans_VMOV_reg_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v8 == Number ) result = ( unsigned __int8 ) trans_VABS_sp ( @@a1@@ , @@v16@@ ) != Number ; else LABEL_96 : result = Number L ; return result ; } if ( v7 != ( _DWORD ) & loc_20000 ) return Number L ; v9 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != ( _DWORD ) & unk_50000 ) { if ( v9 <= ( unsigned int ) & unk_50000 ) { if ( v9 == Number ) { disas_vfp_extract_disas_vfp_Fmt_25 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VRINTZ_sp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VRINTR_sp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } if ( v9 <= Number ) { if ( ! v9 ) { disas_vfp_extract_disas_vfp_Fmt_29 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_f32_f16 ( @@a1@@ , @@v16@@ ) != Number ; } if ( v9 == Number ) { disas_vfp_extract_disas_vfp_Fmt_29 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_f16_f32 ( @@a1@@ , @@v16@@ ) != Number ; } } } return Number L ; } if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_32 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VCVT_sp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_25 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VRINTX_sp ( @@a1@@ , @@v16@@ ) != Number ; } } return result ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v16\", \"t\": {\"T\": 2, \"n\": 10, \"s\": 4, \"t\": \"_DWORD\"}, \"location\": \"s48\"}, {\"n\": \"v17\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
{"name": "disas_vfp_extract_disas_vfp_Fmt_10", "code": "_DWORD * __fastcall disas_vfp_extract_disas_vfp_Fmt_10 ( __int64 @@a1@@ , _DWORD * @@a2@@ , unsigned int @@a3@@ ) { int @@v3@@ ; int v4 ; int v5 ; _DWORD * result ; * @@a2@@ = extract32 ( @@a3@@ , Number , Number ) ; @@a2@@ [ Number ] = extract32 ( @@a3@@ , Number , Number ) ; @@a2@@ [ Number ] = extract32 ( @@a3@@ , Number , Number ) ; @@v3@@ = extract32 ( @@a3@@ , Number , Number ) ; v4 = extract32 ( @@a3@@ , Number , Number ) ; v5 = deposit32 ( v4 , Number , Number , @@v3@@ ) ; result = @@a2@@ ; @@a2@@ [ Number ] = v5 ; return result ; }", "source": [{"n": "a3", "t": {"T": 1, "n": "unsigned int", "s": 4}, "location": "r16"}, {"n": "v3", "t": {"T": 1, "n": "int", "s": 4}, "location": "r32"}, {"n": "a1", "t": {"T": 1, "n": "__int64", "s": 8}, "location": "r56"}, {"n": "a2", "t": {"T": 3, "t": "_DWORD"}, "location": "r64"}]}
|
[{"n": "insn", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r16"}, {"n": "v3", "t": {"T": 1, "n": "uint32_t", "s": 4}, "location": "r32"}, {"n": "ctx", "t": {"T": 3, "t": "DisasContext_0"}, "location": "r56"}, {"n": "a", "t": {"T": 3, "t": "arg_disas_vfp5"}, "location": "r64"}]
|
data1/train-shard-4.tar
|
0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9_0de5b970c4b623b11deb59e14880555bdda1f6bbad19a7820ea754471bf85af9.jsonl
| 720 |
[
"{\"name\": \"extract32\", \"code\": \"__int64 __fastcall extract32 ( unsigned int @@a1@@ , int @@a2@@ , int @@a3@@ ) { if ( @@a2@@ < Number || @@a3@@ <= Number || @@a3@@ > Number - @@a2@@ ) _assert_fail ( String , String , Number , String ) ; return ( @@a1@@ >> @@a2@@ ) & ( Number >> ( Number - @@a3@@ ) ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"deposit32\", \"code\": \"__int64 __fastcall deposit32 ( int @@a1@@ , int @@a2@@ , int @@a3@@ , int @@a4@@ ) { if ( @@a2@@ < Number || @@a3@@ <= Number || @@a3@@ > Number - @@a2@@ ) _assert_fail ( String , String , Number , String ) ; return @@a1@@ & ~ ( Number >> ( Number - @@a3@@ ) << @@a2@@ ) | ( Number >> ( Number - @@a3@@ ) << @@a2@@ ) & ( @@a4@@ << @@a2@@ ) ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a4\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r24\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"int\", \"s\": 4}, \"location\": \"r64\"}]}",
"{\"name\": \"disas_vfp_extract_disas_vfp_Fmt_1\", \"code\": \"_DWORD * __fastcall disas_vfp_extract_disas_vfp_Fmt_1 ( __int64 @@a1@@ , _DWORD * @@a2@@ , unsigned int @@a3@@ ) { int v3 ; int v4 ; int v5 ; int v6 ; int v7 ; _DWORD * result ; @@a2@@ [ Number ] = extract32 ( @@a3@@ , Number , Number ) ; @@a2@@ [ Number ] = extract32 ( @@a3@@ , Number , Number ) ; v3 = extract32 ( @@a3@@ , Number , Number ) ; v4 = extract32 ( @@a3@@ , Number , Number ) ; @@a2@@ [ Number ] = deposit32 ( v4 , Number , Number , v3 ) ; @@a2@@ [ Number ] = Number ; v5 = extract32 ( @@a3@@ , Number , Number ) ; v6 = extract32 ( @@a3@@ , Number , Number ) ; v7 = deposit32 ( v6 , Number , Number , v5 ) ; result = @@a2@@ ; * @@a2@@ = v7 ; return result ; }\", \"source\": [{\"n\": \"a3\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r16\"}, {\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 3, \"t\": \"_DWORD\"}, \"location\": \"r64\"}]}",
"{\"name\": \"disas_vfp\", \"code\": \"_BOOL8 __fastcall disas_vfp ( __int64 @@a1@@ , unsigned int @@a2@@ ) { unsigned int v2 ; _BOOL8 result ; unsigned int v4 ; unsigned int v5 ; unsigned int v6 ; unsigned int v7 ; unsigned int v8 ; unsigned int v9 ; unsigned int v10 ; unsigned int v11 ; unsigned int v12 ; unsigned int v13 ; unsigned int v14 ; unsigned int v15 ; _DWORD @@v16@@ [ Number ] ; unsigned __int64 @@v17@@ ; @@v17@@ = __readfsqword ( Number ) ; v2 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { v10 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_0 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VMOV_to_gp ( @@a1@@ , @@v16@@ ) != Number ; } else { result = Number L ; } } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_1 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VMOV_to_gp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_2 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VMOV_to_gp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v10 != Number ) { if ( v10 <= Number ) { if ( ! v10 ) { v11 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_22 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VFM_dp ( @@a1@@ , @@v16@@ ) != Number ; } if ( v11 != Number ) { if ( v11 <= Number ) { if ( ! v11 ) { disas_vfp_extract_disas_vfp_Fmt_18 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VMLS_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VMLA_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } if ( v11 == Number ) { disas_vfp_extract_disas_vfp_Fmt_18 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VNMUL_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VMUL_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } } return Number L ; } disas_vfp_extract_disas_vfp_Fmt_18 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VDIV_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } if ( v10 == Number ) { if ( ( @@a2@@ & Number ) != Number ) { if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_6 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VDUP ( @@a1@@ , @@v16@@ ) != Number ; } else { result = Number L ; } } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_3 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VMOV_from_gp ( @@a1@@ , @@v16@@ ) != Number ; } else if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_4 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VMOV_from_gp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_5 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VMOV_from_gp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } } return Number L ; } v12 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != Number ) { if ( v12 == Number ) { disas_vfp_extract_disas_vfp_Fmt_20 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VFM_dp ( @@a1@@ , @@v16@@ ) != Number ; } if ( v12 <= Number ) { if ( ! v12 ) { disas_vfp_extract_disas_vfp_Fmt_18 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VNMLA_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VNMLS_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } if ( v12 == Number ) { disas_vfp_extract_disas_vfp_Fmt_18 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VSUB_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VADD_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } } return Number L ; } if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_24 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VMOV_imm_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } v13 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_37 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_fix_dp ( @@a1@@ , @@v16@@ ) != Number ; } if ( v13 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_39 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VCVT_dp_int ( @@a1@@ , @@v16@@ ) != Number ; } else if ( ( @@a2@@ & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_33 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) result = ( unsigned __int8 ) trans_VJCVT ( @@a1@@ , @@v16@@ ) != Number ; else result = Number L ; } else { disas_vfp_extract_disas_vfp_Fmt_35 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VCVT_int_dp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v13 > Number ) return Number L ; if ( ! v13 ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_28 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCMP_dp ( @@a1@@ , @@v16@@ ) != Number ; } disas_vfp_extract_disas_vfp_Fmt_26 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; v14 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_VSQRT_dp ( @@a1@@ , @@v16@@ ) != Number ; if ( v14 == Number ) return ( unsigned __int8 ) trans_VNEG_dp ( @@a1@@ , @@v16@@ ) != Number ; if ( v14 > Number ) goto LABEL_195 ; if ( ! v14 ) return ( unsigned __int8 ) trans_VMOV_reg_dp ( @@a1@@ , @@v16@@ ) != Number ; if ( v14 == Number ) result = ( unsigned __int8 ) trans_VABS_dp ( @@a1@@ , @@v16@@ ) != Number ; else LABEL_195 : result = Number L ; return result ; } if ( v13 != ( _DWORD ) & loc_20000 ) return Number L ; v15 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != ( _DWORD ) & unk_50000 ) { if ( v15 <= ( unsigned int ) & unk_50000 ) { if ( v15 == Number ) { disas_vfp_extract_disas_vfp_Fmt_26 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VRINTZ_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VRINTR_dp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } if ( v15 <= Number ) { if ( ! v15 ) { disas_vfp_extract_disas_vfp_Fmt_30 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_f64_f16 ( @@a1@@ , @@v16@@ ) != Number ; } if ( v15 == Number ) { disas_vfp_extract_disas_vfp_Fmt_31 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_f16_f64 ( @@a1@@ , @@v16@@ ) != Number ; } } } return Number L ; } if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_33 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VCVT_dp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_26 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VRINTX_dp ( @@a1@@ , @@v16@@ ) != Number ; } } else { if ( v2 > Number ) return Number L ; if ( v2 != Number ) { if ( v2 <= Number ) { if ( v2 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_16 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VLDM_VSTM_dp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_12 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VLDR_VSTR_dp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v2 <= Number ) { if ( v2 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_15 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VLDM_VSTM_sp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_11 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VLDR_VSTR_sp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v2 <= Number ) { if ( v2 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_13 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VLDM_VSTM_sp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_9 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_VMOV_64_sp ( @@a1@@ , @@v16@@ ) != Number ; else result = Number L ; } } else { if ( v2 != Number ) return Number L ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_14 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VLDM_VSTM_dp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_10 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_VMOV_64_dp ( @@a1@@ , @@v16@@ ) != Number ; else result = Number L ; } } return result ; } } } return Number L ; } v4 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_7 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) == Number ) result = ( unsigned __int8 ) trans_VMSR_VMRS ( @@a1@@ , @@v16@@ ) != Number ; else result = Number L ; return result ; } if ( v4 != Number ) { if ( v4 <= Number ) { if ( v4 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_19 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VFM_sp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_17 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VDIV_sp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v4 <= Number ) { if ( v4 == Number ) { disas_vfp_extract_disas_vfp_Fmt_17 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; v6 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_VSUB_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v6 == Number ) return ( unsigned __int8 ) trans_VADD_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v6 > Number ) goto LABEL_66 ; if ( ! v6 ) return ( unsigned __int8 ) trans_VMUL_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v6 == Number ) result = ( unsigned __int8 ) trans_VNMUL_sp ( @@a1@@ , @@v16@@ ) != Number ; else LABEL_66 : result = Number L ; return result ; } if ( v4 <= Number ) { if ( ! v4 ) { disas_vfp_extract_disas_vfp_Fmt_17 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; v5 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_VNMLA_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v5 == Number ) return ( unsigned __int8 ) trans_VNMLS_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v5 > Number ) goto LABEL_52 ; if ( ! v5 ) return ( unsigned __int8 ) trans_VMLA_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v5 == Number ) result = ( unsigned __int8 ) trans_VMLS_sp ( @@a1@@ , @@v16@@ ) != Number ; else LABEL_52 : result = Number L ; return result ; } if ( v4 == Number ) { disas_vfp_extract_disas_vfp_Fmt_8 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VMOV_single ( @@a1@@ , @@v16@@ ) != Number ; return result ; } } } } return Number L ; } if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_21 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VFM_sp ( @@a1@@ , @@v16@@ ) != Number ; } if ( ( ( @@a2@@ >> Number ) & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_23 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VMOV_imm_sp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } v7 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) { disas_vfp_extract_disas_vfp_Fmt_36 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_fix_sp ( @@a1@@ , @@v16@@ ) != Number ; } if ( v7 == Number ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_38 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VCVT_sp_int ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_34 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( @@a2@@ & Number ) != Number ) result = Number L ; else result = ( unsigned __int8 ) trans_VCVT_int_sp ( @@a1@@ , @@v16@@ ) != Number ; } return result ; } if ( v7 > Number ) return Number L ; if ( ! v7 ) { if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_27 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCMP_sp ( @@a1@@ , @@v16@@ ) != Number ; } disas_vfp_extract_disas_vfp_Fmt_25 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; v8 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) == Number ) return ( unsigned __int8 ) trans_VSQRT_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v8 == Number ) return ( unsigned __int8 ) trans_VNEG_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v8 > Number ) goto LABEL_96 ; if ( ! v8 ) return ( unsigned __int8 ) trans_VMOV_reg_sp ( @@a1@@ , @@v16@@ ) != Number ; if ( v8 == Number ) result = ( unsigned __int8 ) trans_VABS_sp ( @@a1@@ , @@v16@@ ) != Number ; else LABEL_96 : result = Number L ; return result ; } if ( v7 != ( _DWORD ) & loc_20000 ) return Number L ; v9 = @@a2@@ & Number ; if ( ( @@a2@@ & Number ) != ( _DWORD ) & unk_50000 ) { if ( v9 <= ( unsigned int ) & unk_50000 ) { if ( v9 == Number ) { disas_vfp_extract_disas_vfp_Fmt_25 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) result = ( unsigned __int8 ) trans_VRINTZ_sp ( @@a1@@ , @@v16@@ ) != Number ; else result = ( unsigned __int8 ) trans_VRINTR_sp ( @@a1@@ , @@v16@@ ) != Number ; return result ; } if ( v9 <= Number ) { if ( ! v9 ) { disas_vfp_extract_disas_vfp_Fmt_29 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_f32_f16 ( @@a1@@ , @@v16@@ ) != Number ; } if ( v9 == Number ) { disas_vfp_extract_disas_vfp_Fmt_29 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; return ( unsigned __int8 ) trans_VCVT_f16_f32 ( @@a1@@ , @@v16@@ ) != Number ; } } } return Number L ; } if ( ( ( @@a2@@ >> Number ) & Number ) != Number ) { disas_vfp_extract_disas_vfp_Fmt_32 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VCVT_sp ( @@a1@@ , @@v16@@ ) != Number ; } else { disas_vfp_extract_disas_vfp_Fmt_25 ( @@a1@@ , @@v16@@ , @@a2@@ ) ; result = ( unsigned __int8 ) trans_VRINTX_sp ( @@a1@@ , @@v16@@ ) != Number ; } } return result ; }\", \"source\": [{\"n\": \"a1\", \"t\": {\"T\": 1, \"n\": \"__int64\", \"s\": 8}, \"location\": \"r56\"}, {\"n\": \"a2\", \"t\": {\"T\": 1, \"n\": \"unsigned int\", \"s\": 4}, \"location\": \"r64\"}, {\"n\": \"v16\", \"t\": {\"T\": 2, \"n\": 10, \"s\": 4, \"t\": \"_DWORD\"}, \"location\": \"s48\"}, {\"n\": \"v17\", \"t\": {\"T\": 1, \"n\": \"unsigned __int64\", \"s\": 8}, \"location\": \"s8\"}]}"
] |
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